diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..3bf1e4c0 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "BlueStuff"] + path = libs/BlueStuff + url = https://github.com/CTSRD-CHERI/BlueStuff.git diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v deleted file mode 100644 index 1cb3bfa4..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v +++ /dev/null @@ -1,1415 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// from_master_awready O 1 reg -// from_master_wready O 1 reg -// from_master_bvalid O 1 reg -// from_master_bid O 4 reg -// from_master_bresp O 2 reg -// from_master_arready O 1 reg -// from_master_rvalid O 1 reg -// from_master_rid O 4 reg -// from_master_rdata O 64 reg -// from_master_rresp O 2 reg -// from_master_rlast O 1 reg -// to_slave_awvalid O 1 reg -// to_slave_awid O 4 reg -// to_slave_awaddr O 64 reg -// to_slave_awlen O 8 reg -// to_slave_awsize O 3 reg -// to_slave_awburst O 2 reg -// to_slave_awlock O 1 reg -// to_slave_awcache O 4 reg -// to_slave_awprot O 3 reg -// to_slave_awqos O 4 reg -// to_slave_awregion O 4 reg -// to_slave_wvalid O 1 reg -// to_slave_wid O 4 reg -// to_slave_wdata O 64 reg -// to_slave_wstrb O 8 reg -// to_slave_wlast O 1 reg -// to_slave_bready O 1 reg -// to_slave_arvalid O 1 reg -// to_slave_arid O 4 reg -// to_slave_araddr O 64 reg -// to_slave_arlen O 8 reg -// to_slave_arsize O 3 reg -// to_slave_arburst O 2 reg -// to_slave_arlock O 1 reg -// to_slave_arcache O 4 reg -// to_slave_arprot O 3 reg -// to_slave_arqos O 4 reg -// to_slave_arregion O 4 reg -// to_slave_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// from_master_awvalid I 1 -// from_master_awid I 4 reg -// from_master_awaddr I 64 reg -// from_master_awlen I 8 reg -// from_master_awsize I 3 reg -// from_master_awburst I 2 reg -// from_master_awlock I 1 reg -// from_master_awcache I 4 reg -// from_master_awprot I 3 reg -// from_master_awqos I 4 reg -// from_master_awregion I 4 reg -// from_master_wvalid I 1 -// from_master_wid I 4 reg -// from_master_wdata I 64 reg -// from_master_wstrb I 8 reg -// from_master_wlast I 1 reg -// from_master_bready I 1 -// from_master_arvalid I 1 -// from_master_arid I 4 reg -// from_master_araddr I 64 reg -// from_master_arlen I 8 reg -// from_master_arsize I 3 reg -// from_master_arburst I 2 reg -// from_master_arlock I 1 reg -// from_master_arcache I 4 reg -// from_master_arprot I 3 reg -// from_master_arqos I 4 reg -// from_master_arregion I 4 reg -// from_master_rready I 1 -// to_slave_awready I 1 -// to_slave_wready I 1 -// to_slave_bvalid I 1 -// to_slave_bid I 4 reg -// to_slave_bresp I 2 reg -// to_slave_arready I 1 -// to_slave_rvalid I 1 -// to_slave_rid I 4 reg -// to_slave_rdata I 64 reg -// to_slave_rresp I 2 reg -// to_slave_rlast I 1 reg -// EN_reset I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkAXI4_Deburster_A(CLK, - RST_N, - - EN_reset, - RDY_reset, - - from_master_awvalid, - from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion, - - from_master_awready, - - from_master_wvalid, - from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast, - - from_master_wready, - - from_master_bvalid, - - from_master_bid, - - from_master_bresp, - - from_master_bready, - - from_master_arvalid, - from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion, - - from_master_arready, - - from_master_rvalid, - - from_master_rid, - - from_master_rdata, - - from_master_rresp, - - from_master_rlast, - - from_master_rready, - - to_slave_awvalid, - - to_slave_awid, - - to_slave_awaddr, - - to_slave_awlen, - - to_slave_awsize, - - to_slave_awburst, - - to_slave_awlock, - - to_slave_awcache, - - to_slave_awprot, - - to_slave_awqos, - - to_slave_awregion, - - to_slave_awready, - - to_slave_wvalid, - - to_slave_wid, - - to_slave_wdata, - - to_slave_wstrb, - - to_slave_wlast, - - to_slave_wready, - - to_slave_bvalid, - to_slave_bid, - to_slave_bresp, - - to_slave_bready, - - to_slave_arvalid, - - to_slave_arid, - - to_slave_araddr, - - to_slave_arlen, - - to_slave_arsize, - - to_slave_arburst, - - to_slave_arlock, - - to_slave_arcache, - - to_slave_arprot, - - to_slave_arqos, - - to_slave_arregion, - - to_slave_arready, - - to_slave_rvalid, - to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast, - - to_slave_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method from_master_m_awvalid - input from_master_awvalid; - input [3 : 0] from_master_awid; - input [63 : 0] from_master_awaddr; - input [7 : 0] from_master_awlen; - input [2 : 0] from_master_awsize; - input [1 : 0] from_master_awburst; - input from_master_awlock; - input [3 : 0] from_master_awcache; - input [2 : 0] from_master_awprot; - input [3 : 0] from_master_awqos; - input [3 : 0] from_master_awregion; - - // value method from_master_m_awready - output from_master_awready; - - // action method from_master_m_wvalid - input from_master_wvalid; - input [3 : 0] from_master_wid; - input [63 : 0] from_master_wdata; - input [7 : 0] from_master_wstrb; - input from_master_wlast; - - // value method from_master_m_wready - output from_master_wready; - - // value method from_master_m_bvalid - output from_master_bvalid; - - // value method from_master_m_bid - output [3 : 0] from_master_bid; - - // value method from_master_m_bresp - output [1 : 0] from_master_bresp; - - // value method from_master_m_buser - - // action method from_master_m_bready - input from_master_bready; - - // action method from_master_m_arvalid - input from_master_arvalid; - input [3 : 0] from_master_arid; - input [63 : 0] from_master_araddr; - input [7 : 0] from_master_arlen; - input [2 : 0] from_master_arsize; - input [1 : 0] from_master_arburst; - input from_master_arlock; - input [3 : 0] from_master_arcache; - input [2 : 0] from_master_arprot; - input [3 : 0] from_master_arqos; - input [3 : 0] from_master_arregion; - - // value method from_master_m_arready - output from_master_arready; - - // value method from_master_m_rvalid - output from_master_rvalid; - - // value method from_master_m_rid - output [3 : 0] from_master_rid; - - // value method from_master_m_rdata - output [63 : 0] from_master_rdata; - - // value method from_master_m_rresp - output [1 : 0] from_master_rresp; - - // value method from_master_m_rlast - output from_master_rlast; - - // value method from_master_m_ruser - - // action method from_master_m_rready - input from_master_rready; - - // value method to_slave_m_awvalid - output to_slave_awvalid; - - // value method to_slave_m_awid - output [3 : 0] to_slave_awid; - - // value method to_slave_m_awaddr - output [63 : 0] to_slave_awaddr; - - // value method to_slave_m_awlen - output [7 : 0] to_slave_awlen; - - // value method to_slave_m_awsize - output [2 : 0] to_slave_awsize; - - // value method to_slave_m_awburst - output [1 : 0] to_slave_awburst; - - // value method to_slave_m_awlock - output to_slave_awlock; - - // value method to_slave_m_awcache - output [3 : 0] to_slave_awcache; - - // value method to_slave_m_awprot - output [2 : 0] to_slave_awprot; - - // value method to_slave_m_awqos - output [3 : 0] to_slave_awqos; - - // value method to_slave_m_awregion - output [3 : 0] to_slave_awregion; - - // value method to_slave_m_awuser - - // action method to_slave_m_awready - input to_slave_awready; - - // value method to_slave_m_wvalid - output to_slave_wvalid; - - // value method to_slave_m_wid - output [3 : 0] to_slave_wid; - - // value method to_slave_m_wdata - output [63 : 0] to_slave_wdata; - - // value method to_slave_m_wstrb - output [7 : 0] to_slave_wstrb; - - // value method to_slave_m_wlast - output to_slave_wlast; - - // value method to_slave_m_wuser - - // action method to_slave_m_wready - input to_slave_wready; - - // action method to_slave_m_bvalid - input to_slave_bvalid; - input [3 : 0] to_slave_bid; - input [1 : 0] to_slave_bresp; - - // value method to_slave_m_bready - output to_slave_bready; - - // value method to_slave_m_arvalid - output to_slave_arvalid; - - // value method to_slave_m_arid - output [3 : 0] to_slave_arid; - - // value method to_slave_m_araddr - output [63 : 0] to_slave_araddr; - - // value method to_slave_m_arlen - output [7 : 0] to_slave_arlen; - - // value method to_slave_m_arsize - output [2 : 0] to_slave_arsize; - - // value method to_slave_m_arburst - output [1 : 0] to_slave_arburst; - - // value method to_slave_m_arlock - output to_slave_arlock; - - // value method to_slave_m_arcache - output [3 : 0] to_slave_arcache; - - // value method to_slave_m_arprot - output [2 : 0] to_slave_arprot; - - // value method to_slave_m_arqos - output [3 : 0] to_slave_arqos; - - // value method to_slave_m_arregion - output [3 : 0] to_slave_arregion; - - // value method to_slave_m_aruser - - // action method to_slave_m_arready - input to_slave_arready; - - // action method to_slave_m_rvalid - input to_slave_rvalid; - input [3 : 0] to_slave_rid; - input [63 : 0] to_slave_rdata; - input [1 : 0] to_slave_rresp; - input to_slave_rlast; - - // value method to_slave_m_rready - output to_slave_rready; - - // signals for module outputs - wire [63 : 0] from_master_rdata, - to_slave_araddr, - to_slave_awaddr, - to_slave_wdata; - wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb; - wire [3 : 0] from_master_bid, - from_master_rid, - to_slave_arcache, - to_slave_arid, - to_slave_arqos, - to_slave_arregion, - to_slave_awcache, - to_slave_awid, - to_slave_awqos, - to_slave_awregion, - to_slave_wid; - wire [2 : 0] to_slave_arprot, - to_slave_arsize, - to_slave_awprot, - to_slave_awsize; - wire [1 : 0] from_master_bresp, - from_master_rresp, - to_slave_arburst, - to_slave_awburst; - wire RDY_reset, - from_master_arready, - from_master_awready, - from_master_bvalid, - from_master_rlast, - from_master_rvalid, - from_master_wready, - to_slave_arlock, - to_slave_arvalid, - to_slave_awlock, - to_slave_awvalid, - to_slave_bready, - to_slave_rready, - to_slave_wlast, - to_slave_wvalid; - - // register m_rg_ar_beat_count - reg [7 : 0] m_rg_ar_beat_count; - wire [7 : 0] m_rg_ar_beat_count$D_IN; - wire m_rg_ar_beat_count$EN; - - // register m_rg_b_beat_count - reg [7 : 0] m_rg_b_beat_count; - wire [7 : 0] m_rg_b_beat_count$D_IN; - wire m_rg_b_beat_count$EN; - - // register m_rg_b_resp - reg [1 : 0] m_rg_b_resp; - wire [1 : 0] m_rg_b_resp$D_IN; - wire m_rg_b_resp$EN; - - // register m_rg_r_beat_count - reg [7 : 0] m_rg_r_beat_count; - wire [7 : 0] m_rg_r_beat_count$D_IN; - wire m_rg_r_beat_count$EN; - - // register m_rg_reset - reg m_rg_reset; - wire m_rg_reset$D_IN, m_rg_reset$EN; - - // register m_rg_w_beat_count - reg [7 : 0] m_rg_w_beat_count; - wire [7 : 0] m_rg_w_beat_count$D_IN; - wire m_rg_w_beat_count$EN; - - // ports of submodule m_f_r_arlen - wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT; - wire m_f_r_arlen$CLR, - m_f_r_arlen$DEQ, - m_f_r_arlen$EMPTY_N, - m_f_r_arlen$ENQ, - m_f_r_arlen$FULL_N; - - // ports of submodule m_f_w_awlen - wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT; - wire m_f_w_awlen$CLR, - m_f_w_awlen$DEQ, - m_f_w_awlen$EMPTY_N, - m_f_w_awlen$ENQ, - m_f_w_awlen$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_addr - wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN, - m_xactor_from_master_f_rd_addr$D_OUT; - wire m_xactor_from_master_f_rd_addr$CLR, - m_xactor_from_master_f_rd_addr$DEQ, - m_xactor_from_master_f_rd_addr$EMPTY_N, - m_xactor_from_master_f_rd_addr$ENQ, - m_xactor_from_master_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_data - wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN, - m_xactor_from_master_f_rd_data$D_OUT; - wire m_xactor_from_master_f_rd_data$CLR, - m_xactor_from_master_f_rd_data$DEQ, - m_xactor_from_master_f_rd_data$EMPTY_N, - m_xactor_from_master_f_rd_data$ENQ, - m_xactor_from_master_f_rd_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_addr - wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN, - m_xactor_from_master_f_wr_addr$D_OUT; - wire m_xactor_from_master_f_wr_addr$CLR, - m_xactor_from_master_f_wr_addr$DEQ, - m_xactor_from_master_f_wr_addr$EMPTY_N, - m_xactor_from_master_f_wr_addr$ENQ, - m_xactor_from_master_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_data - wire [76 : 0] m_xactor_from_master_f_wr_data$D_IN, - m_xactor_from_master_f_wr_data$D_OUT; - wire m_xactor_from_master_f_wr_data$CLR, - m_xactor_from_master_f_wr_data$DEQ, - m_xactor_from_master_f_wr_data$EMPTY_N, - m_xactor_from_master_f_wr_data$ENQ, - m_xactor_from_master_f_wr_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_resp - wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN, - m_xactor_from_master_f_wr_resp$D_OUT; - wire m_xactor_from_master_f_wr_resp$CLR, - m_xactor_from_master_f_wr_resp$DEQ, - m_xactor_from_master_f_wr_resp$EMPTY_N, - m_xactor_from_master_f_wr_resp$ENQ, - m_xactor_from_master_f_wr_resp$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_addr - wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN, - m_xactor_to_slave_f_rd_addr$D_OUT; - wire m_xactor_to_slave_f_rd_addr$CLR, - m_xactor_to_slave_f_rd_addr$DEQ, - m_xactor_to_slave_f_rd_addr$EMPTY_N, - m_xactor_to_slave_f_rd_addr$ENQ, - m_xactor_to_slave_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_data - wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN, - m_xactor_to_slave_f_rd_data$D_OUT; - wire m_xactor_to_slave_f_rd_data$CLR, - m_xactor_to_slave_f_rd_data$DEQ, - m_xactor_to_slave_f_rd_data$EMPTY_N, - m_xactor_to_slave_f_rd_data$ENQ, - m_xactor_to_slave_f_rd_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_addr - wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN, - m_xactor_to_slave_f_wr_addr$D_OUT; - wire m_xactor_to_slave_f_wr_addr$CLR, - m_xactor_to_slave_f_wr_addr$DEQ, - m_xactor_to_slave_f_wr_addr$EMPTY_N, - m_xactor_to_slave_f_wr_addr$ENQ, - m_xactor_to_slave_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_data - wire [76 : 0] m_xactor_to_slave_f_wr_data$D_IN, - m_xactor_to_slave_f_wr_data$D_OUT; - wire m_xactor_to_slave_f_wr_data$CLR, - m_xactor_to_slave_f_wr_data$DEQ, - m_xactor_to_slave_f_wr_data$EMPTY_N, - m_xactor_to_slave_f_wr_data$ENQ, - m_xactor_to_slave_f_wr_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_resp - wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN, - m_xactor_to_slave_f_wr_resp$D_OUT; - wire m_xactor_to_slave_f_wr_resp$CLR, - m_xactor_to_slave_f_wr_resp$DEQ, - m_xactor_to_slave_f_wr_resp$EMPTY_N, - m_xactor_to_slave_f_wr_resp$ENQ, - m_xactor_to_slave_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave, - CAN_FIRE_from_master_m_arvalid, - CAN_FIRE_from_master_m_awvalid, - CAN_FIRE_from_master_m_bready, - CAN_FIRE_from_master_m_rready, - CAN_FIRE_from_master_m_wvalid, - CAN_FIRE_reset, - CAN_FIRE_to_slave_m_arready, - CAN_FIRE_to_slave_m_awready, - CAN_FIRE_to_slave_m_bvalid, - CAN_FIRE_to_slave_m_rvalid, - CAN_FIRE_to_slave_m_wready, - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave, - WILL_FIRE_from_master_m_arvalid, - WILL_FIRE_from_master_m_awvalid, - WILL_FIRE_from_master_m_bready, - WILL_FIRE_from_master_m_rready, - WILL_FIRE_from_master_m_wvalid, - WILL_FIRE_reset, - WILL_FIRE_to_slave_m_arready, - WILL_FIRE_to_slave_m_awready, - WILL_FIRE_to_slave_m_bvalid, - WILL_FIRE_to_slave_m_rvalid, - WILL_FIRE_to_slave_m_wready; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2, - MUX_m_rg_b_beat_count$write_1__VAL_2, - MUX_m_rg_r_beat_count$write_1__VAL_2, - MUX_m_rg_w_beat_count$write_1__VAL_2; - wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2; - wire MUX_m_rg_b_resp$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2430; - reg [31 : 0] v__h1446; - reg [31 : 0] v__h1440; - reg [31 : 0] v__h2424; - // synopsys translate_on - - // remaining internal signals - wire [63 : 0] a_out_araddr__h2944, - a_out_awaddr__h1951, - addr___1__h2036, - addr___1__h3029; - wire [7 : 0] x__h2305, x__h2798, x__h3190, x__h3388; - wire m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95, - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51, - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106, - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35; - - // action method reset - assign RDY_reset = !m_rg_reset ; - assign CAN_FIRE_reset = !m_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method from_master_m_awvalid - assign CAN_FIRE_from_master_m_awvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_awvalid = 1'd1 ; - - // value method from_master_m_awready - assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ; - - // action method from_master_m_wvalid - assign CAN_FIRE_from_master_m_wvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_wvalid = 1'd1 ; - - // value method from_master_m_wready - assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ; - - // value method from_master_m_bvalid - assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ; - - // value method from_master_m_bid - assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ; - - // value method from_master_m_bresp - assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ; - - // action method from_master_m_bready - assign CAN_FIRE_from_master_m_bready = 1'd1 ; - assign WILL_FIRE_from_master_m_bready = 1'd1 ; - - // action method from_master_m_arvalid - assign CAN_FIRE_from_master_m_arvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_arvalid = 1'd1 ; - - // value method from_master_m_arready - assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ; - - // value method from_master_m_rvalid - assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ; - - // value method from_master_m_rid - assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ; - - // value method from_master_m_rdata - assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ; - - // value method from_master_m_rresp - assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ; - - // value method from_master_m_rlast - assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ; - - // action method from_master_m_rready - assign CAN_FIRE_from_master_m_rready = 1'd1 ; - assign WILL_FIRE_from_master_m_rready = 1'd1 ; - - // value method to_slave_m_awvalid - assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ; - - // value method to_slave_m_awid - assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ; - - // value method to_slave_m_awaddr - assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ; - - // value method to_slave_m_awlen - assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ; - - // value method to_slave_m_awsize - assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ; - - // value method to_slave_m_awburst - assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ; - - // value method to_slave_m_awlock - assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ; - - // value method to_slave_m_awcache - assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ; - - // value method to_slave_m_awprot - assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ; - - // value method to_slave_m_awqos - assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ; - - // value method to_slave_m_awregion - assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ; - - // action method to_slave_m_awready - assign CAN_FIRE_to_slave_m_awready = 1'd1 ; - assign WILL_FIRE_to_slave_m_awready = 1'd1 ; - - // value method to_slave_m_wvalid - assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ; - - // value method to_slave_m_wid - assign to_slave_wid = m_xactor_to_slave_f_wr_data$D_OUT[76:73] ; - - // value method to_slave_m_wdata - assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ; - - // value method to_slave_m_wstrb - assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ; - - // value method to_slave_m_wlast - assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ; - - // action method to_slave_m_wready - assign CAN_FIRE_to_slave_m_wready = 1'd1 ; - assign WILL_FIRE_to_slave_m_wready = 1'd1 ; - - // action method to_slave_m_bvalid - assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ; - - // value method to_slave_m_bready - assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ; - - // value method to_slave_m_arvalid - assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ; - - // value method to_slave_m_arid - assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ; - - // value method to_slave_m_araddr - assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ; - - // value method to_slave_m_arlen - assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ; - - // value method to_slave_m_arsize - assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ; - - // value method to_slave_m_arburst - assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ; - - // value method to_slave_m_arlock - assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ; - - // value method to_slave_m_arcache - assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ; - - // value method to_slave_m_arprot - assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ; - - // value method to_slave_m_arqos - assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ; - - // value method to_slave_m_arregion - assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ; - - // action method to_slave_m_arready - assign CAN_FIRE_to_slave_m_arready = 1'd1 ; - assign WILL_FIRE_to_slave_m_arready = 1'd1 ; - - // action method to_slave_m_rvalid - assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ; - - // value method to_slave_m_rready - assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ; - - // submodule m_f_r_arlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_r_arlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_r_arlen$D_IN), - .ENQ(m_f_r_arlen$ENQ), - .DEQ(m_f_r_arlen$DEQ), - .CLR(m_f_r_arlen$CLR), - .D_OUT(m_f_r_arlen$D_OUT), - .FULL_N(m_f_r_arlen$FULL_N), - .EMPTY_N(m_f_r_arlen$EMPTY_N)); - - // submodule m_f_w_awlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_w_awlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_w_awlen$D_IN), - .ENQ(m_f_w_awlen$ENQ), - .DEQ(m_f_w_awlen$DEQ), - .CLR(m_f_w_awlen$CLR), - .D_OUT(m_f_w_awlen$D_OUT), - .FULL_N(m_f_w_awlen$FULL_N), - .EMPTY_N(m_f_w_awlen$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_addr$D_IN), - .ENQ(m_xactor_from_master_f_rd_addr$ENQ), - .DEQ(m_xactor_from_master_f_rd_addr$DEQ), - .CLR(m_xactor_from_master_f_rd_addr$CLR), - .D_OUT(m_xactor_from_master_f_rd_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_data$D_IN), - .ENQ(m_xactor_from_master_f_rd_data$ENQ), - .DEQ(m_xactor_from_master_f_rd_data$DEQ), - .CLR(m_xactor_from_master_f_rd_data$CLR), - .D_OUT(m_xactor_from_master_f_rd_data$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_addr$D_IN), - .ENQ(m_xactor_from_master_f_wr_addr$ENQ), - .DEQ(m_xactor_from_master_f_wr_addr$DEQ), - .CLR(m_xactor_from_master_f_wr_addr$CLR), - .D_OUT(m_xactor_from_master_f_wr_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_data$D_IN), - .ENQ(m_xactor_from_master_f_wr_data$ENQ), - .DEQ(m_xactor_from_master_f_wr_data$DEQ), - .CLR(m_xactor_from_master_f_wr_data$CLR), - .D_OUT(m_xactor_from_master_f_wr_data$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_resp$D_IN), - .ENQ(m_xactor_from_master_f_wr_resp$ENQ), - .DEQ(m_xactor_from_master_f_wr_resp$DEQ), - .CLR(m_xactor_from_master_f_wr_resp$CLR), - .D_OUT(m_xactor_from_master_f_wr_resp$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_addr$D_IN), - .ENQ(m_xactor_to_slave_f_rd_addr$ENQ), - .DEQ(m_xactor_to_slave_f_rd_addr$DEQ), - .CLR(m_xactor_to_slave_f_rd_addr$CLR), - .D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_data$D_IN), - .ENQ(m_xactor_to_slave_f_rd_data$ENQ), - .DEQ(m_xactor_to_slave_f_rd_data$DEQ), - .CLR(m_xactor_to_slave_f_rd_data$CLR), - .D_OUT(m_xactor_to_slave_f_rd_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_addr$D_IN), - .ENQ(m_xactor_to_slave_f_wr_addr$ENQ), - .DEQ(m_xactor_to_slave_f_wr_addr$DEQ), - .CLR(m_xactor_to_slave_f_wr_addr$CLR), - .D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_data$D_IN), - .ENQ(m_xactor_to_slave_f_wr_data$ENQ), - .DEQ(m_xactor_to_slave_f_wr_data$DEQ), - .CLR(m_xactor_to_slave_f_wr_data$CLR), - .D_OUT(m_xactor_to_slave_f_wr_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_resp$D_IN), - .ENQ(m_xactor_to_slave_f_wr_resp$ENQ), - .DEQ(m_xactor_to_slave_f_wr_resp$DEQ), - .CLR(m_xactor_to_slave_f_wr_resp$CLR), - .D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave = - m_xactor_to_slave_f_wr_addr$FULL_N && - m_xactor_from_master_f_wr_addr$EMPTY_N && - m_xactor_to_slave_f_wr_data$FULL_N && - m_xactor_from_master_f_wr_data$EMPTY_N && - (m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - - // rule RL_m_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master = - m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N && - (m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 || - m_xactor_from_master_f_wr_resp$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - - // rule RL_m_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave = - m_xactor_to_slave_f_rd_addr$FULL_N && - m_xactor_from_master_f_rd_addr$EMPTY_N && - (m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - - // rule RL_m_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master = - m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N && - m_xactor_from_master_f_rd_data$FULL_N ; - assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ; - assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_b_resp$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - (m_rg_b_resp == 2'b0 && - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 || - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51) ; - assign MUX_m_rg_ar_beat_count$write_1__VAL_2 = - m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ? - x__h3190 : - 8'd0 ; - assign MUX_m_rg_b_beat_count$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - x__h2798 : - 8'd0 ; - assign MUX_m_rg_b_resp$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - 2'b0 ; - assign MUX_m_rg_r_beat_count$write_1__VAL_2 = - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ? - x__h3388 : - 8'd0 ; - assign MUX_m_rg_w_beat_count$write_1__VAL_2 = - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ? - x__h2305 : - 8'd0 ; - - // register m_rg_ar_beat_count - assign m_rg_ar_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ; - assign m_rg_ar_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ; - - // register m_rg_b_beat_count - assign m_rg_b_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ; - assign m_rg_b_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ; - - // register m_rg_b_resp - assign m_rg_b_resp$D_IN = - m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ; - assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ; - - // register m_rg_r_beat_count - assign m_rg_r_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ; - assign m_rg_r_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ; - - // register m_rg_reset - assign m_rg_reset$D_IN = !m_rg_reset ; - assign m_rg_reset$EN = m_rg_reset || EN_reset ; - - // register m_rg_w_beat_count - assign m_rg_w_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ; - assign m_rg_w_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ; - - // submodule m_f_r_arlen - assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_f_r_arlen$ENQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - m_rg_ar_beat_count == 8'd0 ; - assign m_f_r_arlen$DEQ = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master && - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ; - assign m_f_r_arlen$CLR = m_rg_reset ; - - // submodule m_f_w_awlen - assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign m_f_w_awlen$ENQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - m_rg_w_beat_count == 8'd0 ; - assign m_f_w_awlen$DEQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_f_w_awlen$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_addr - assign m_xactor_from_master_f_rd_addr$D_IN = - { from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion } ; - assign m_xactor_from_master_f_rd_addr$ENQ = - from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ; - assign m_xactor_from_master_f_rd_addr$DEQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - !m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ; - assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_data - assign m_xactor_from_master_f_rd_data$D_IN = - { m_xactor_to_slave_f_rd_data$D_OUT[70:1], - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 } ; - assign m_xactor_from_master_f_rd_data$ENQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_from_master_f_rd_data$DEQ = - from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ; - assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_addr - assign m_xactor_from_master_f_wr_addr$D_IN = - { from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion } ; - assign m_xactor_from_master_f_wr_addr$ENQ = - from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ; - assign m_xactor_from_master_f_wr_addr$DEQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ; - assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_data - assign m_xactor_from_master_f_wr_data$D_IN = - { from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast } ; - assign m_xactor_from_master_f_wr_data$ENQ = - from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ; - assign m_xactor_from_master_f_wr_data$DEQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_resp - assign m_xactor_from_master_f_wr_resp$D_IN = - { m_xactor_to_slave_f_wr_resp$D_OUT[5:2], - (m_rg_b_resp == 2'b0) ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - m_rg_b_resp } ; - assign m_xactor_from_master_f_wr_resp$ENQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_xactor_from_master_f_wr_resp$DEQ = - from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ; - assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_addr - assign m_xactor_to_slave_f_rd_addr$D_IN = - { m_xactor_from_master_f_rd_addr$D_OUT[96:93], - a_out_araddr__h2944, - 8'd0, - m_xactor_from_master_f_rd_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_rd_addr$ENQ = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - assign m_xactor_to_slave_f_rd_addr$DEQ = - m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ; - assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_data - assign m_xactor_to_slave_f_rd_data$D_IN = - { to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast } ; - assign m_xactor_to_slave_f_rd_data$ENQ = - to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ; - assign m_xactor_to_slave_f_rd_data$DEQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_addr - assign m_xactor_to_slave_f_wr_addr$D_IN = - { m_xactor_from_master_f_wr_addr$D_OUT[96:93], - a_out_awaddr__h1951, - 8'd0, - m_xactor_from_master_f_wr_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_wr_addr$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_addr$DEQ = - m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ; - assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_data - assign m_xactor_to_slave_f_wr_data$D_IN = - { m_xactor_from_master_f_wr_data$D_OUT[76:1], 1'd1 } ; - assign m_xactor_to_slave_f_wr_data$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_data$DEQ = - m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ; - assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_resp - assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ; - assign m_xactor_to_slave_f_wr_resp$ENQ = - to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ; - assign m_xactor_to_slave_f_wr_resp$DEQ = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ; - - // remaining internal signals - assign a_out_araddr__h2944 = - (m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h3029 : - m_xactor_from_master_f_rd_addr$D_OUT[92:29] ; - assign a_out_awaddr__h1951 = - (m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h2036 : - m_xactor_from_master_f_wr_addr$D_OUT[92:29] ; - assign addr___1__h2036 = - m_xactor_from_master_f_wr_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_w_beat_count } << - m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ; - assign addr___1__h3029 = - m_xactor_from_master_f_rd_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_ar_beat_count } << - m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ; - assign m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 = - m_rg_ar_beat_count < - m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 = - m_rg_b_beat_count < m_f_w_awlen$D_OUT ; - assign m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 = - m_rg_r_beat_count < m_f_r_arlen$D_OUT ; - assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 = - m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign x__h2305 = m_rg_w_beat_count + 8'd1 ; - assign x__h2798 = m_rg_b_beat_count + 8'd1 ; - assign x__h3190 = m_rg_ar_beat_count + 8'd1 ; - assign x__h3388 = m_rg_r_beat_count + 8'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0; - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (m_rg_ar_beat_count$EN) - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN; - if (m_rg_b_beat_count$EN) - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN; - if (m_rg_b_resp$EN) - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN; - if (m_rg_r_beat_count$EN) - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN; - if (m_rg_reset$EN) - m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN; - if (m_rg_w_beat_count$EN) - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_ar_beat_count = 8'hAA; - m_rg_b_beat_count = 8'hAA; - m_rg_b_resp = 2'h2; - m_rg_r_beat_count = 8'hAA; - m_rg_reset = 1'h0; - m_rg_w_beat_count = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - begin - v__h2430 = $stime; - #0; - end - v__h2424 = v__h2430 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", - v__h2424); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display(" WLAST not set on last data beat (awlen = %0d)", - m_xactor_from_master_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) - begin - v__h1446 = $stime; - #0; - end - v__h1440 = v__h1446 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) $display("%0d: %m::AXI4_Deburster.rl_reset", v__h1440); - end - // synopsys translate_on -endmodule // mkAXI4_Deburster_A - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v deleted file mode 100644 index 7b69d05e..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v +++ /dev/null @@ -1,2157 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkBoot_ROM(CLK, - RST_N, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready); - input CLK; - input RST_N; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_set_addr_map, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_module_ready - reg rg_module_ready; - wire rg_module_ready$D_IN, rg_module_ready$EN; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h808; - reg [31 : 0] v__h8928; - reg [31 : 0] v__h9221; - reg [31 : 0] v__h9331; - reg [31 : 0] v__h802; - reg [31 : 0] v__h8922; - reg [31 : 0] v__h9215; - reg [31 : 0] v__h9325; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] data64__h987; - reg [31 : 0] CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2; - wire [63 : 0] byte_addr__h705, rdata__h924; - wire [1 : 0] rdr_rresp__h957; - wire NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18, - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_module_ready - assign rg_module_ready$D_IN = 1'd1 ; - assign rg_module_ready$EN = EN_set_addr_map ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h924, - rdr_rresp__h957, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 ? - 2'b10 : - 2'b0 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = 1'b0 ; - - // remaining internal signals - assign NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 = - slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] || - slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ; - assign NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 = - slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] || - slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ; - assign byte_addr__h705 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign rdata__h924 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 64'd0 : - data64__h987 ; - assign rdr_rresp__h957 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 2'b10 : - 2'b0 ; - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16, - 64'd24, - 64'd56, - 64'd72, - 64'd80, - 64'd88, - 64'd200, - 64'd232, - 64'd312, - 64'd424, - 64'd448, - 64'd600, - 64'd728, - 64'd1136, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = 32'h0; - 64'd32: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h54040000; - 64'd40: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h88030000; - 64'd48: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h11000000; - 64'd64: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h50030000; - 64'd96, - 64'd112, - 64'd208, - 64'd224, - 64'd240, - 64'd432, - 64'd488, - 64'd872, - 64'd888: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h04000000; - 64'd104, 64'd120, 64'd504, 64'd792, 64'd920: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h02000000; - 64'd128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h16000000; - 64'd136: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h62626375; - 64'd144: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656B6970; - 64'd152: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65642D65; - 64'd160, - 64'd264, - 64'd280, - 64'd296, - 64'd336, - 64'd360, - 64'd384, - 64'd456, - 64'd552, - 64'd592, - 64'd608, - 64'd624, - 64'd672, - 64'd704, - 64'd760, - 64'd816, - 64'd840, - 64'd880: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h03000000; - 64'd168: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h26000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h732C7261; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7261622D; - 64'd192, - 64'd216, - 64'd400, - 64'd440, - 64'd496, - 64'd512, - 64'd584, - 64'd744, - 64'd752, - 64'd912: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h01000000; - 64'd248, 64'd896: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h80969800; - 64'd256: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40757063; - 64'd272: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h3F000000; - 64'd288, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4B000000; - 64'd304: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4F000000; - 64'd320: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h06000000; - 64'd328: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h63736972; - 64'd344: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h56000000; - 64'd352: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h75616D69; - 64'd368: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h60000000; - 64'd376: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h76732C76; - 64'd392: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69000000; - 64'd408: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70757272; - 64'd416: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F72746E; - 64'd464, 64'd632, 64'd712, 64'd824: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h1B000000; - 64'd472: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70632C76; - 64'd480: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00006374; - 64'd520: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h38407972; - 64'd528: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00303030; - 64'd536: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h07000000; - 64'd544: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D656D; - 64'd568: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000080; - 64'd576: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000010; - 64'd616: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h0F000000; - 64'd656: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69730063; - 64'd664: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7375622D; - 64'd680: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hA7000000; - 64'd688: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E696C63; - 64'd696, 64'd808: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h30303030; - 64'd720: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C632C76; - 64'd736: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h10000000; - 64'd776: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000002; - 64'd784: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000C00; - 64'd800: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h74726175; - 64'd832: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61303535; - 64'd856: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h000000C0; - 64'd864: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40000000; - 64'd904: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h08000000; - 64'd928: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h09000000; - 64'd936: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73736572; - 64'd944: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h2300736C; - 64'd952: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C65632D; - 64'd960: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61706D6F; - 64'd968: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D0065; - 64'd976: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656D6974; - 64'd984: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6572662D; - 64'd992: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h64007963; - 64'd1000: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79745F65; - 64'd1008: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73006765; - 64'd1016: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69720073; - 64'd1024: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00617369; - 64'd1032: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65707974; - 64'd1040: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h662D6B63; - 64'd1048: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79636E65; - 64'd1056, 64'd1072: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h72726574; - 64'd1064: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C6C6563; - 64'd1080: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h746E6F63; - 64'd1088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70007265; - 64'd1096: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7200656C; - 64'd1104: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E690073; - 64'd1112: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73747075; - 64'd1120: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65646E65; - 64'd1128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h68732D67; - default: CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00028067; - 64'd24: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80000000; - 64'd32: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hEDFE0DD0; - 64'd40: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h38000000; - 64'd48: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h28000000; - 64'd56, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h10000000; - 64'd64: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hCC000000; - 64'd72, - 64'd80, - 64'd104, - 64'd216, - 64'd296, - 64'd568, - 64'd576, - 64'd672, - 64'd680, - 64'd776, - 64'd784, - 64'd840, - 64'd856, - 64'd864, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = 32'h0; - 64'd88, 64'd256, 64'd688, 64'd800: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h01000000; - 64'd96, - 64'd112, - 64'd128, - 64'd208, - 64'd224, - 64'd240, - 64'd320, - 64'd432, - 64'd448, - 64'd488, - 64'd536, - 64'd736, - 64'd752, - 64'd872, - 64'd888, - 64'd904: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h03000000; - 64'd120, 64'd232, 64'd464: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0F000000; - 64'd136, 64'd328: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h1B000000; - 64'd144: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h732C7261; - 64'd152: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7261622D; - 64'd160, 64'd336: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000076; - 64'd168: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h12000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h62626375; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656B6970; - 64'd192: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000065; - 64'd200: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h73757063; - 64'd248: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C000000; - 64'd264, 64'd704, 64'd816: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000030; - 64'd272, 64'd288, 64'd392, 64'd600, 64'd616: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h04000000; - 64'd280: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00757063; - 64'd304: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h05000000; - 64'd312: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79616B6F; - 64'd344: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0A000000; - 64'd352: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h32337672; - 64'd360: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000073; - 64'd368, 64'd920: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0B000000; - 64'd376, 64'd472, 64'd720: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63736972; - 64'd384: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00003233; - 64'd400: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80969800; - 64'd408: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65746E69; - 64'd416: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F632D74; - 64'd424: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72656C6C; - 64'd440: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79000000; - 64'd456: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h8A000000; - 64'd480: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692D75; - 64'd496: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h9F000000; - 64'd504, 64'd512, 64'd584, 64'd608, 64'd624, 64'd792, 64'd928: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h02000000; - 64'd520: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6D656D; - 64'd528: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30303030; - 64'd544: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3F000000; - 64'd552: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00007972; - 64'd592: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00636F73; - 64'd632: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h21000000; - 64'd656: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F732D65; - 64'd664: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656C706D; - 64'd696: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30324074; - 64'd712: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0D000000; - 64'd728: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30746E69; - 64'd744, 64'd912: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAE000000; - 64'd760: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h07000000; - 64'd808: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30306340; - 64'd824: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h09000000; - 64'd832: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3631736E; - 64'd880: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hC2000000; - 64'd896: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h69000000; - 64'd936: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h64646123; - 64'd944: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C65632D; - 64'd952: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h657A6973; - 64'd960: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6300736C; - 64'd968: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C626974; - 64'd976: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h006C6564; - 64'd984: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65736162; - 64'd992: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E657571; - 64'd1000: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63697665; - 64'd1008: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72006570; - 64'd1016: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75746174; - 64'd1024: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C766373; - 64'd1032: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D756D6D; - 64'd1040: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6C6300; - 64'd1048: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75716572; - 64'd1056: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692300; - 64'd1064, 64'd1080: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D747075; - 64'd1072: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E690073; - 64'd1088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C6C6F72; - 64'd1096: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h646E6168; - 64'd1104: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65676E61; - 64'd1112: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72726574; - 64'd1120: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7478652D; - 64'd1128: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65720064; - 64'd1136: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00746669; - default: CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705 or - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 or - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2) - begin - case (byte_addr__h705) - 64'd0: data64__h987 = 64'h0202859300000297; - 64'd8: data64__h987 = 64'h0182A283F1402573; - default: data64__h987 = - { CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_module_ready$EN) - rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_module_ready = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - begin - v__h808 = $stime; - #0; - end - v__h802 = v__h808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", - v__h802); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - begin - v__h8928 = $stime; - #0; - end - v__h8922 = v__h8928 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", - v__h8922); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h9221 = $stime; - #0; - end - v__h9215 = v__h9221 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9215, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h9331 = $stime; - #0; - end - v__h9325 = v__h9331 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9325, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkBoot_ROM - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCPU.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCPU.v deleted file mode 100644 index 5a9b71bb..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCPU.v +++ /dev/null @@ -1,7043 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// hart0_server_reset_response_get O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_set_verbosity O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// hart0_server_reset_request_put I 1 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// nmi_req_set_not_clear I 1 -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// EN_hart0_server_reset_request_put I 1 -// EN_set_verbosity I 1 -// EN_hart0_server_reset_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// imem_master_arready, -// dmem_master_awready, -// dmem_master_wready) -> imem_master_rready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready, -// dmem_master_arready) -> dmem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCPU(CLK, - RST_N, - - hart0_server_reset_request_put, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - nmi_req_set_not_clear, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity); - input CLK; - input RST_N; - - // action method hart0_server_reset_request_put - input hart0_server_reset_request_put; - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // actionvalue method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, - RDY_set_verbosity, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - hart0_server_reset_response_get, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid; - - // register cfg_logdelay - reg [63 : 0] cfg_logdelay; - wire [63 : 0] cfg_logdelay$D_IN; - wire cfg_logdelay$EN; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register imem_rg_f3 - reg [2 : 0] imem_rg_f3; - wire [2 : 0] imem_rg_f3$D_IN; - wire imem_rg_f3$EN; - - // register imem_rg_instr_15_0 - reg [15 : 0] imem_rg_instr_15_0; - wire [15 : 0] imem_rg_instr_15_0$D_IN; - wire imem_rg_instr_15_0$EN; - - // register imem_rg_mstatus_MXR - reg imem_rg_mstatus_MXR; - wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN; - - // register imem_rg_pc - reg [31 : 0] imem_rg_pc; - reg [31 : 0] imem_rg_pc$D_IN; - wire imem_rg_pc$EN; - - // register imem_rg_priv - reg [1 : 0] imem_rg_priv; - wire [1 : 0] imem_rg_priv$D_IN; - wire imem_rg_priv$EN; - - // register imem_rg_satp - reg [31 : 0] imem_rg_satp; - wire [31 : 0] imem_rg_satp$D_IN; - wire imem_rg_satp$EN; - - // register imem_rg_sstatus_SUM - reg imem_rg_sstatus_SUM; - wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN; - - // register imem_rg_tval - reg [31 : 0] imem_rg_tval; - reg [31 : 0] imem_rg_tval$D_IN; - wire imem_rg_tval$EN; - - // register rg_cur_priv - reg [1 : 0] rg_cur_priv; - reg [1 : 0] rg_cur_priv$D_IN; - wire rg_cur_priv$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_next_pc - reg [31 : 0] rg_next_pc; - reg [31 : 0] rg_next_pc$D_IN; - wire rg_next_pc$EN; - - // register rg_run_on_reset - reg rg_run_on_reset; - wire rg_run_on_reset$D_IN, rg_run_on_reset$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_start_CPI_cycles - reg [63 : 0] rg_start_CPI_cycles; - wire [63 : 0] rg_start_CPI_cycles$D_IN; - wire rg_start_CPI_cycles$EN; - - // register rg_start_CPI_instrs - reg [63 : 0] rg_start_CPI_instrs; - wire [63 : 0] rg_start_CPI_instrs$D_IN; - wire rg_start_CPI_instrs$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register stage1_rg_full - reg stage1_rg_full; - reg stage1_rg_full$D_IN; - wire stage1_rg_full$EN; - - // register stage2_rg_full - reg stage2_rg_full; - reg stage2_rg_full$D_IN; - wire stage2_rg_full$EN; - - // register stage2_rg_resetting - reg stage2_rg_resetting; - wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN; - - // register stage2_rg_stage2 - reg [301 : 0] stage2_rg_stage2; - wire [301 : 0] stage2_rg_stage2$D_IN; - wire stage2_rg_stage2$EN; - - // register stage3_rg_full - reg stage3_rg_full; - reg stage3_rg_full$D_IN; - wire stage3_rg_full$EN; - - // register stage3_rg_stage3 - reg [142 : 0] stage3_rg_stage3; - wire [142 : 0] stage3_rg_stage3$D_IN; - wire stage3_rg_stage3$EN; - - // ports of submodule csr_regfile - reg [31 : 0] csr_regfile$csr_trap_actions_xtval; - reg [3 : 0] csr_regfile$csr_trap_actions_exc_code; - reg [1 : 0] csr_regfile$csr_ret_actions_from_priv; - wire [97 : 0] csr_regfile$csr_trap_actions; - wire [65 : 0] csr_regfile$csr_ret_actions; - wire [63 : 0] csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret; - wire [32 : 0] csr_regfile$read_csr; - wire [31 : 0] csr_regfile$csr_trap_actions_pc, - csr_regfile$mav_csr_write_word, - csr_regfile$read_mstatus, - csr_regfile$read_satp, - csr_regfile$read_sstatus; - wire [27 : 0] csr_regfile$read_misa; - wire [11 : 0] csr_regfile$access_permitted_1_csr_addr, - csr_regfile$access_permitted_2_csr_addr, - csr_regfile$csr_counter_read_fault_csr_addr, - csr_regfile$mav_csr_write_csr_addr, - csr_regfile$mav_read_csr_csr_addr, - csr_regfile$read_csr_csr_addr, - csr_regfile$read_csr_port2_csr_addr; - wire [4 : 0] csr_regfile$interrupt_pending, - csr_regfile$ma_update_fcsr_fflags_flags; - wire [2 : 0] csr_regfile$read_frm; - wire [1 : 0] csr_regfile$access_permitted_1_priv, - csr_regfile$access_permitted_2_priv, - csr_regfile$csr_counter_read_fault_priv, - csr_regfile$csr_trap_actions_from_priv, - csr_regfile$interrupt_pending_cur_priv, - csr_regfile$ma_update_mstatus_fs_fs; - wire csr_regfile$EN_csr_minstret_incr, - csr_regfile$EN_csr_ret_actions, - csr_regfile$EN_csr_trap_actions, - csr_regfile$EN_debug, - csr_regfile$EN_ma_update_fcsr_fflags, - csr_regfile$EN_ma_update_mstatus_fs, - csr_regfile$EN_mav_csr_write, - csr_regfile$EN_mav_read_csr, - csr_regfile$EN_server_reset_request_put, - csr_regfile$EN_server_reset_response_get, - csr_regfile$RDY_server_reset_request_put, - csr_regfile$RDY_server_reset_response_get, - csr_regfile$access_permitted_1, - csr_regfile$access_permitted_1_read_not_write, - csr_regfile$access_permitted_2, - csr_regfile$access_permitted_2_read_not_write, - csr_regfile$csr_trap_actions_interrupt, - csr_regfile$csr_trap_actions_nmi, - csr_regfile$m_external_interrupt_req_set_not_clear, - csr_regfile$nmi_pending, - csr_regfile$nmi_req_set_not_clear, - csr_regfile$s_external_interrupt_req_set_not_clear, - csr_regfile$software_interrupt_req_set_not_clear, - csr_regfile$timer_interrupt_req_set_not_clear, - csr_regfile$wfi_resume; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fpr_regfile - wire [63 : 0] fpr_regfile$read_rs1, - fpr_regfile$read_rs2, - fpr_regfile$read_rs3, - fpr_regfile$write_rd_rd_val; - wire [4 : 0] fpr_regfile$read_rs1_port2_rs1, - fpr_regfile$read_rs1_rs1, - fpr_regfile$read_rs2_rs2, - fpr_regfile$read_rs3_rs3, - fpr_regfile$write_rd_rd; - wire fpr_regfile$EN_server_reset_request_put, - fpr_regfile$EN_server_reset_response_get, - fpr_regfile$EN_write_rd, - fpr_regfile$RDY_server_reset_request_put, - fpr_regfile$RDY_server_reset_response_get; - - // ports of submodule gpr_regfile - wire [31 : 0] gpr_regfile$read_rs1, - gpr_regfile$read_rs2, - gpr_regfile$write_rd_rd_val; - wire [4 : 0] gpr_regfile$read_rs1_port2_rs1, - gpr_regfile$read_rs1_rs1, - gpr_regfile$read_rs2_rs2, - gpr_regfile$write_rd_rd; - wire gpr_regfile$EN_server_reset_request_put, - gpr_regfile$EN_server_reset_response_get, - gpr_regfile$EN_write_rd, - gpr_regfile$RDY_server_reset_request_put, - gpr_regfile$RDY_server_reset_response_get; - - // ports of submodule near_mem - reg [31 : 0] near_mem$imem_req_addr; - reg [1 : 0] near_mem$dmem_req_op; - reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM; - wire [63 : 0] near_mem$dmem_master_araddr, - near_mem$dmem_master_awaddr, - near_mem$dmem_master_rdata, - near_mem$dmem_master_wdata, - near_mem$dmem_req_store_value, - near_mem$dmem_word64, - near_mem$imem_master_araddr, - near_mem$imem_master_awaddr, - near_mem$imem_master_rdata, - near_mem$imem_master_wdata; - wire [31 : 0] near_mem$dmem_req_addr, - near_mem$dmem_req_satp, - near_mem$imem_instr, - near_mem$imem_pc, - near_mem$imem_req_satp; - wire [7 : 0] near_mem$dmem_master_arlen, - near_mem$dmem_master_awlen, - near_mem$dmem_master_wstrb, - near_mem$imem_master_arlen, - near_mem$imem_master_awlen, - near_mem$imem_master_wstrb, - near_mem$server_fence_request_put; - wire [6 : 0] near_mem$dmem_req_amo_funct7; - wire [3 : 0] near_mem$dmem_exc_code, - near_mem$dmem_master_arcache, - near_mem$dmem_master_arid, - near_mem$dmem_master_arqos, - near_mem$dmem_master_arregion, - near_mem$dmem_master_awcache, - near_mem$dmem_master_awid, - near_mem$dmem_master_awqos, - near_mem$dmem_master_awregion, - near_mem$dmem_master_bid, - near_mem$dmem_master_rid, - near_mem$dmem_master_wid, - near_mem$imem_exc_code, - near_mem$imem_master_arcache, - near_mem$imem_master_arid, - near_mem$imem_master_arqos, - near_mem$imem_master_arregion, - near_mem$imem_master_awcache, - near_mem$imem_master_awid, - near_mem$imem_master_awqos, - near_mem$imem_master_awregion, - near_mem$imem_master_bid, - near_mem$imem_master_rid, - near_mem$imem_master_wid; - wire [2 : 0] near_mem$dmem_master_arprot, - near_mem$dmem_master_arsize, - near_mem$dmem_master_awprot, - near_mem$dmem_master_awsize, - near_mem$dmem_req_f3, - near_mem$imem_master_arprot, - near_mem$imem_master_arsize, - near_mem$imem_master_awprot, - near_mem$imem_master_awsize, - near_mem$imem_req_f3; - wire [1 : 0] near_mem$dmem_master_arburst, - near_mem$dmem_master_awburst, - near_mem$dmem_master_bresp, - near_mem$dmem_master_rresp, - near_mem$dmem_req_priv, - near_mem$imem_master_arburst, - near_mem$imem_master_awburst, - near_mem$imem_master_bresp, - near_mem$imem_master_rresp, - near_mem$imem_req_priv; - wire near_mem$EN_dmem_req, - near_mem$EN_imem_req, - near_mem$EN_server_fence_i_request_put, - near_mem$EN_server_fence_i_response_get, - near_mem$EN_server_fence_request_put, - near_mem$EN_server_fence_response_get, - near_mem$EN_server_reset_request_put, - near_mem$EN_server_reset_response_get, - near_mem$EN_sfence_vma, - near_mem$RDY_server_fence_i_request_put, - near_mem$RDY_server_fence_i_response_get, - near_mem$RDY_server_fence_request_put, - near_mem$RDY_server_fence_response_get, - near_mem$RDY_server_reset_request_put, - near_mem$RDY_server_reset_response_get, - near_mem$dmem_exc, - near_mem$dmem_master_arlock, - near_mem$dmem_master_arready, - near_mem$dmem_master_arvalid, - near_mem$dmem_master_awlock, - near_mem$dmem_master_awready, - near_mem$dmem_master_awvalid, - near_mem$dmem_master_bready, - near_mem$dmem_master_bvalid, - near_mem$dmem_master_rlast, - near_mem$dmem_master_rready, - near_mem$dmem_master_rvalid, - near_mem$dmem_master_wlast, - near_mem$dmem_master_wready, - near_mem$dmem_master_wvalid, - near_mem$dmem_req_mstatus_MXR, - near_mem$dmem_req_sstatus_SUM, - near_mem$dmem_valid, - near_mem$imem_exc, - near_mem$imem_is_i32_not_i16, - near_mem$imem_master_arlock, - near_mem$imem_master_arready, - near_mem$imem_master_arvalid, - near_mem$imem_master_awlock, - near_mem$imem_master_awready, - near_mem$imem_master_awvalid, - near_mem$imem_master_bready, - near_mem$imem_master_bvalid, - near_mem$imem_master_rlast, - near_mem$imem_master_rready, - near_mem$imem_master_rvalid, - near_mem$imem_master_wlast, - near_mem$imem_master_wready, - near_mem$imem_master_wvalid, - near_mem$imem_valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_pc_reset_value; - - // ports of submodule stage1_f_reset_reqs - wire stage1_f_reset_reqs$CLR, - stage1_f_reset_reqs$DEQ, - stage1_f_reset_reqs$EMPTY_N, - stage1_f_reset_reqs$ENQ, - stage1_f_reset_reqs$FULL_N; - - // ports of submodule stage1_f_reset_rsps - wire stage1_f_reset_rsps$CLR, - stage1_f_reset_rsps$DEQ, - stage1_f_reset_rsps$EMPTY_N, - stage1_f_reset_rsps$ENQ, - stage1_f_reset_rsps$FULL_N; - - // ports of submodule stage2_f_reset_reqs - wire stage2_f_reset_reqs$CLR, - stage2_f_reset_reqs$DEQ, - stage2_f_reset_reqs$EMPTY_N, - stage2_f_reset_reqs$ENQ, - stage2_f_reset_reqs$FULL_N; - - // ports of submodule stage2_f_reset_rsps - wire stage2_f_reset_rsps$CLR, - stage2_f_reset_rsps$DEQ, - stage2_f_reset_rsps$EMPTY_N, - stage2_f_reset_rsps$ENQ, - stage2_f_reset_rsps$FULL_N; - - // ports of submodule stage2_fbox - wire [63 : 0] stage2_fbox$req_v1, - stage2_fbox$req_v2, - stage2_fbox$req_v3, - stage2_fbox$word_fst; - wire [6 : 0] stage2_fbox$req_f7, stage2_fbox$req_opcode; - wire [4 : 0] stage2_fbox$req_rs2, stage2_fbox$word_snd; - wire [2 : 0] stage2_fbox$req_rm; - wire stage2_fbox$EN_req, - stage2_fbox$EN_server_reset_request_put, - stage2_fbox$EN_server_reset_response_get, - stage2_fbox$RDY_server_reset_request_put, - stage2_fbox$RDY_server_reset_response_get, - stage2_fbox$valid; - - // ports of submodule stage2_mbox - wire [31 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word; - wire [3 : 0] stage2_mbox$set_verbosity_verbosity; - wire [2 : 0] stage2_mbox$req_f3; - wire stage2_mbox$EN_req, - stage2_mbox$EN_req_reset, - stage2_mbox$EN_rsp_reset, - stage2_mbox$EN_set_verbosity, - stage2_mbox$req_is_OP_not_OP_32, - stage2_mbox$valid; - - // ports of submodule stage3_f_reset_reqs - wire stage3_f_reset_reqs$CLR, - stage3_f_reset_reqs$DEQ, - stage3_f_reset_reqs$EMPTY_N, - stage3_f_reset_reqs$ENQ, - stage3_f_reset_reqs$FULL_N; - - // ports of submodule stage3_f_reset_rsps - wire stage3_f_reset_rsps$CLR, - stage3_f_reset_rsps$DEQ, - stage3_f_reset_rsps$EMPTY_N, - stage3_f_reset_rsps$ENQ, - stage3_f_reset_rsps$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_imem_rl_assert_fail, - CAN_FIRE_RL_imem_rl_fetch_next_32b, - CAN_FIRE_RL_rl_WFI_resume, - CAN_FIRE_RL_rl_finish_FENCE, - CAN_FIRE_RL_rl_finish_FENCE_I, - CAN_FIRE_RL_rl_finish_SFENCE_VMA, - CAN_FIRE_RL_rl_pipe, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_RL_rl_reset_from_WFI, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_show_pipe, - CAN_FIRE_RL_rl_stage1_CSRR_S_or_C, - CAN_FIRE_RL_rl_stage1_CSRR_W, - CAN_FIRE_RL_rl_stage1_FENCE, - CAN_FIRE_RL_rl_stage1_FENCE_I, - CAN_FIRE_RL_rl_stage1_SFENCE_VMA, - CAN_FIRE_RL_rl_stage1_WFI, - CAN_FIRE_RL_rl_stage1_interrupt, - CAN_FIRE_RL_rl_stage1_restart_after_csrrx, - CAN_FIRE_RL_rl_stage1_trap, - CAN_FIRE_RL_rl_stage1_xRET, - CAN_FIRE_RL_rl_stage2_nonpipe, - CAN_FIRE_RL_rl_trap_fetch, - CAN_FIRE_RL_stage1_rl_reset, - CAN_FIRE_RL_stage2_rl_reset_begin, - CAN_FIRE_RL_stage2_rl_reset_end, - CAN_FIRE_RL_stage3_rl_reset, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_set_verbosity, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_imem_rl_assert_fail, - WILL_FIRE_RL_imem_rl_fetch_next_32b, - WILL_FIRE_RL_rl_WFI_resume, - WILL_FIRE_RL_rl_finish_FENCE, - WILL_FIRE_RL_rl_finish_FENCE_I, - WILL_FIRE_RL_rl_finish_SFENCE_VMA, - WILL_FIRE_RL_rl_pipe, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_RL_rl_reset_from_WFI, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_show_pipe, - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C, - WILL_FIRE_RL_rl_stage1_CSRR_W, - WILL_FIRE_RL_rl_stage1_FENCE, - WILL_FIRE_RL_rl_stage1_FENCE_I, - WILL_FIRE_RL_rl_stage1_SFENCE_VMA, - WILL_FIRE_RL_rl_stage1_WFI, - WILL_FIRE_RL_rl_stage1_interrupt, - WILL_FIRE_RL_rl_stage1_restart_after_csrrx, - WILL_FIRE_RL_rl_stage1_trap, - WILL_FIRE_RL_rl_stage1_xRET, - WILL_FIRE_RL_rl_stage2_nonpipe, - WILL_FIRE_RL_rl_trap_fetch, - WILL_FIRE_RL_stage1_rl_reset, - WILL_FIRE_RL_stage2_rl_reset_begin, - WILL_FIRE_RL_stage2_rl_reset_end, - WILL_FIRE_RL_stage3_rl_reset, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_set_verbosity, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - reg [31 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2; - wire [31 : 0] MUX_near_mem$imem_req_2__VAL_1, - MUX_near_mem$imem_req_2__VAL_2, - MUX_near_mem$imem_req_2__VAL_5; - wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1, - MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_3; - wire MUX_csr_regfile$mav_csr_write_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_2, - MUX_gpr_regfile$write_rd_1__SEL_3, - MUX_imem_rg_f3$write_1__SEL_1, - MUX_imem_rg_f3$write_1__SEL_2, - MUX_imem_rg_mstatus_MXR$write_1__SEL_4, - MUX_imem_rg_pc$write_1__SEL_4, - MUX_near_mem$imem_req_1__SEL_6, - MUX_rg_cur_priv$write_1__SEL_1, - MUX_rg_mstatus_MXR$write_1__SEL_1, - MUX_rg_next_pc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_11, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_4, - MUX_rg_state$write_1__SEL_6, - MUX_rg_state$write_1__SEL_7, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9, - MUX_stage1_rg_full$write_1__VAL_2, - MUX_stage2_rg_full$write_1__VAL_2; - - // remaining internal signals - reg [63 : 0] CASE_theResult__604_BITS_6_TO_0_0b100011_alu_o_ETC__q20, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411, - x_out_data_to_stage2_val1__h13749, - x_out_data_to_stage3_rd_val__h6243, - x_out_fbypass_rd_val__h6870; - reg [31 : 0] CASE_theResult__604_BITS_6_TO_0_0b1100111_data_ETC__q19, - _theResult_____1_fst__h15237, - rs1_val__h22055, - value__h6422, - value__h6483, - x_out_bypass_rd_val__h6718, - x_out_data_to_stage2_addr__h13748; - reg [4 : 0] x_out_bypass_rd__h6717, - x_out_data_to_stage2_rd__h13747, - x_out_data_to_stage3_fpr_flags__h6242, - x_out_data_to_stage3_rd__h6239, - x_out_fbypass_rd__h6869; - reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q13, - CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15, - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16, - CASE_theResult__604_BITS_31_TO_20_0b0_CASE_rg__ETC__q14, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1152, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1176, - alu_outputs_exc_code__h14690, - x_out_trap_info_exc_code__h6459; - reg [2 : 0] CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260; - reg [1 : 0] CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1, - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2, - CASE_stage2_rg_stage2_BITS_235_TO_233_1_IF_NOT_ETC__q3; - reg CASE_theResult__604_BITS_6_TO_0_0b1000011_NOT__ETC__q7, - CASE_theResult__604_BITS_6_TO_0_0b1000011_theR_ETC__q10, - CASE_theResult__604_BITS_6_TO_0_0b10011_IF_NOT_ETC__q12, - CASE_theResult__604_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9, - CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8, - CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946, - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150, - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160, - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195, - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d230; - wire [127 : 0] csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d1854; - wire [63 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1412, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1432, - _theResult_____1_snd_fst_rd_val__h6855, - _theResult_____2_snd_rd_val__h6852, - _theResult____h26769, - _theResult___snd_rd_val__h6861, - alu_outputs___1_val1__h13900, - alu_outputs___1_val1__h14035, - alu_outputs___1_val1__h14076, - alu_outputs___1_val1__h14095, - alu_outputs___1_val1__h14114, - alu_outputs___1_val1__h14465, - alu_outputs___1_val1__h14489, - alu_outputs___1_val1__h14666, - alu_outputs___1_val1__h15021, - alu_outputs___1_val2__h13877, - alu_outputs___1_val2__h14180, - alu_outputs___1_val2__h15022, - cpi__h26771, - cpifrac__h26772, - data_to_stage3_rd_val__h6137, - delta_CPI_cycles__h26767, - delta_CPI_instrs___1__h26804, - delta_CPI_instrs__h26768, - frs1_val_bypassed__h4623, - frs2_val_bypassed__h4628, - output_stage2___1_data_to_stage3_rd_val__h6211, - rd_val__h17575, - rd_val__h17628, - rd_val__h17686, - x__h26770, - x_out_data_to_stage2_val2__h13750, - x_out_data_to_stage2_val3__h13751; - wire [31 : 0] IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1317, - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1801, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d570, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d571, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d572, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d573, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d574, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d576, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d578, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d579, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d580, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d582, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d583, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d584, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d586, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d587, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d588, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d596, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d598, - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1326, - _theResult_____1_fst__h15230, - _theResult_____1_fst__h15265, - _theResult_____1_fst_rd_val__h6696, - _theResult_____2_fst_rd_val__h6693, - _theResult____h14024, - _theResult____h4604, - _theResult___fst__h7192, - _theResult___fst__h7220, - _theResult___fst_rd_val__h6707, - _theResult___snd__h17391, - alu_outputs___1_addr__h13875, - alu_outputs___1_addr__h13899, - alu_outputs___1_addr__h13928, - alu_outputs___1_addr__h14154, - alu_outputs___1_addr__h14178, - branch_target__h13854, - data_to_stage2_addr__h13737, - fall_through_pc__h13698, - instr___1__h7017, - instr__h10372, - instr__h10544, - instr__h10717, - instr__h10910, - instr__h11103, - instr__h11220, - instr__h11398, - instr__h11517, - instr__h11612, - instr__h11748, - instr__h11884, - instr__h12020, - instr__h12358, - instr__h12461, - instr__h12606, - instr__h12798, - instr__h12993, - instr__h13466, - instr__h4602, - instr__h7292, - instr__h7437, - instr__h7629, - instr__h7824, - instr__h8053, - instr__h8396, - instr__h8786, - instr__h8902, - instr__h8967, - instr__h9284, - instr__h9622, - instr__h9806, - instr__h9935, - instr_out___1__h7162, - instr_out___1__h7194, - instr_out___1__h7222, - next_pc___1__h16893, - next_pc__h16891, - rd_val___1__h15218, - rd_val___1__h15226, - rd_val___1__h15233, - rd_val___1__h15240, - rd_val___1__h15247, - rd_val___1__h15254, - rd_val__h13631, - rd_val__h13674, - rd_val__h14066, - rd_val__h14086, - rd_val__h14105, - rd_val__h17285, - rd_val__h17337, - rd_val__h17359, - rs1_val__h14431, - rs1_val__h21562, - rs1_val_bypassed__h4612, - rs2_val__h13850, - trap_info_tval__h16726, - val__h13633, - val__h13676, - value__h16781, - x_out_data_to_stage2_instr__h13745, - x_out_next_pc__h13711, - y__h22359; - wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400, - theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q4; - wire [19 : 0] imm20__h9674; - wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429, - theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q5; - wire [11 : 0] imm12__h10170, - imm12__h10385, - imm12__h10581, - imm12__h10926, - imm12__h7293, - imm12__h7630, - imm12__h9546, - offset__h8000, - theResult__604_BITS_31_TO_20__q18, - theResult__604_BITS_31_TO_25_CONCAT_theResult__ETC__q6; - wire [9 : 0] nzimm10__h10168, nzimm10__h10383; - wire [8 : 0] offset__h8911; - wire [7 : 0] offset__h7063; - wire [6 : 0] offset__h7572; - wire [5 : 0] imm6__h9544; - wire [4 : 0] offset_BITS_4_TO_0___h13591, - offset_BITS_4_TO_0___h7561, - offset_BITS_4_TO_0___h7992, - rd__h7632, - rs1__h7631, - shamt__h14020; - wire [3 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1112, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1116, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1154, - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1108, - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1162, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178, - IF_rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7__ETC___d1150, - alu_outputs___1_exc_code__h14461, - cur_verbosity__h3131, - x_out_trap_info_exc_code__h16729; - wire [2 : 0] rm__h14593, x_out_data_to_stage2_rounding_mode__h13753; - wire [1 : 0] IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d256, - IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d284, - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289, - IF_near_mem_dmem_valid__22_AND_NOT_near_mem_dm_ETC___d254, - IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125, - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129, - IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127, - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134, - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263; - wire IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1095, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1602, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1127, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d971, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1851, - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602, - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604, - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d702, - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1676, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1744, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1746, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1749, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1763, - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1084, - NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1244, - NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1290, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1612, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1623, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1631, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607, - _0_OR_0_OR_near_mem_imem_exc__23_OR_IF_IF_NOT_n_ETC___d1742, - csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1605, - csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1610, - csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1616, - csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d414, - csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d420, - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d926, - fpr_regfile_RDY_server_reset_request_put__548__ETC___d1560, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1457, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1460, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1463, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1466, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1469, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1472, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1475, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1478, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1481, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1484, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1487, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1490, - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d614, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d616, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1601, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954, - rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7_EQ__ETC___d1148, - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766, - rg_state_6_EQ_3_618_AND_stage3_rg_full_2_OR_NO_ETC___d1637, - stage2_f_reset_rsps_i_notEmpty__571_AND_stage3_ETC___d1580, - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d647, - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d655; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // actionvalue method hart0_server_reset_response_get - assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ; - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = near_mem$imem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = near_mem$imem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = near_mem$imem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = near_mem$imem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = near_mem$imem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = near_mem$imem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = near_mem$imem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = near_mem$imem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = near_mem$imem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = near_mem$imem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = near_mem$imem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = near_mem$imem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = near_mem$imem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = near_mem$imem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = near_mem$imem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = near_mem$imem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = near_mem$imem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = near_mem$imem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = near_mem$imem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = near_mem$imem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = near_mem$imem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = near_mem$imem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = near_mem$imem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = near_mem$imem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = near_mem$imem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = near_mem$imem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = near_mem$imem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = near_mem$imem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = near_mem$imem_master_rready ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = near_mem$dmem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = near_mem$dmem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = near_mem$dmem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = near_mem$dmem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = near_mem$dmem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = near_mem$dmem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = near_mem$dmem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = near_mem$dmem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = near_mem$dmem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = near_mem$dmem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = near_mem$dmem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = near_mem$dmem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = near_mem$dmem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = near_mem$dmem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = near_mem$dmem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = near_mem$dmem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = near_mem$dmem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = near_mem$dmem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = near_mem$dmem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = near_mem$dmem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = near_mem$dmem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = near_mem$dmem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = near_mem$dmem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = near_mem$dmem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = near_mem$dmem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = near_mem$dmem_master_rready ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // submodule csr_regfile - mkCSR_RegFile csr_regfile(.CLK(CLK), - .RST_N(RST_N), - .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr), - .access_permitted_1_priv(csr_regfile$access_permitted_1_priv), - .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write), - .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr), - .access_permitted_2_priv(csr_regfile$access_permitted_2_priv), - .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write), - .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr), - .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv), - .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv), - .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code), - .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv), - .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt), - .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi), - .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc), - .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval), - .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv), - .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear), - .ma_update_fcsr_fflags_flags(csr_regfile$ma_update_fcsr_fflags_flags), - .ma_update_mstatus_fs_fs(csr_regfile$ma_update_mstatus_fs_fs), - .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr), - .mav_csr_write_word(csr_regfile$mav_csr_write_word), - .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr), - .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear), - .read_csr_csr_addr(csr_regfile$read_csr_csr_addr), - .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr), - .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear), - .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear), - .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get), - .EN_mav_read_csr(csr_regfile$EN_mav_read_csr), - .EN_mav_csr_write(csr_regfile$EN_mav_csr_write), - .EN_ma_update_fcsr_fflags(csr_regfile$EN_ma_update_fcsr_fflags), - .EN_ma_update_mstatus_fs(csr_regfile$EN_ma_update_mstatus_fs), - .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions), - .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions), - .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr), - .EN_debug(csr_regfile$EN_debug), - .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get), - .read_csr(csr_regfile$read_csr), - .read_csr_port2(), - .mav_read_csr(), - .mav_csr_write(), - .read_frm(csr_regfile$read_frm), - .read_misa(csr_regfile$read_misa), - .read_mstatus(csr_regfile$read_mstatus), - .read_sstatus(csr_regfile$read_sstatus), - .read_ustatus(), - .read_satp(csr_regfile$read_satp), - .csr_trap_actions(csr_regfile$csr_trap_actions), - .RDY_csr_trap_actions(), - .csr_ret_actions(csr_regfile$csr_ret_actions), - .RDY_csr_ret_actions(), - .read_csr_minstret(csr_regfile$read_csr_minstret), - .read_csr_mcycle(csr_regfile$read_csr_mcycle), - .read_csr_mtime(), - .access_permitted_1(csr_regfile$access_permitted_1), - .access_permitted_2(csr_regfile$access_permitted_2), - .csr_counter_read_fault(), - .csr_mip_read(), - .interrupt_pending(csr_regfile$interrupt_pending), - .wfi_resume(csr_regfile$wfi_resume), - .nmi_pending(csr_regfile$nmi_pending), - .RDY_debug()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fpr_regfile - mkFPR_RegFile fpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(fpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(fpr_regfile$read_rs1_rs1), - .read_rs2_rs2(fpr_regfile$read_rs2_rs2), - .read_rs3_rs3(fpr_regfile$read_rs3_rs3), - .write_rd_rd(fpr_regfile$write_rd_rd), - .write_rd_rd_val(fpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(fpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(fpr_regfile$EN_server_reset_response_get), - .EN_write_rd(fpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(fpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fpr_regfile$RDY_server_reset_response_get), - .read_rs1(fpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(fpr_regfile$read_rs2), - .read_rs3(fpr_regfile$read_rs3)); - - // submodule gpr_regfile - mkGPR_RegFile gpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(gpr_regfile$read_rs1_rs1), - .read_rs2_rs2(gpr_regfile$read_rs2_rs2), - .write_rd_rd(gpr_regfile$write_rd_rd), - .write_rd_rd_val(gpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get), - .EN_write_rd(gpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get), - .read_rs1(gpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(gpr_regfile$read_rs2)); - - // submodule near_mem - mkNear_Mem near_mem(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(near_mem$dmem_master_arready), - .dmem_master_awready(near_mem$dmem_master_awready), - .dmem_master_bid(near_mem$dmem_master_bid), - .dmem_master_bresp(near_mem$dmem_master_bresp), - .dmem_master_bvalid(near_mem$dmem_master_bvalid), - .dmem_master_rdata(near_mem$dmem_master_rdata), - .dmem_master_rid(near_mem$dmem_master_rid), - .dmem_master_rlast(near_mem$dmem_master_rlast), - .dmem_master_rresp(near_mem$dmem_master_rresp), - .dmem_master_rvalid(near_mem$dmem_master_rvalid), - .dmem_master_wready(near_mem$dmem_master_wready), - .dmem_req_addr(near_mem$dmem_req_addr), - .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7), - .dmem_req_f3(near_mem$dmem_req_f3), - .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR), - .dmem_req_op(near_mem$dmem_req_op), - .dmem_req_priv(near_mem$dmem_req_priv), - .dmem_req_satp(near_mem$dmem_req_satp), - .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM), - .dmem_req_store_value(near_mem$dmem_req_store_value), - .imem_master_arready(near_mem$imem_master_arready), - .imem_master_awready(near_mem$imem_master_awready), - .imem_master_bid(near_mem$imem_master_bid), - .imem_master_bresp(near_mem$imem_master_bresp), - .imem_master_bvalid(near_mem$imem_master_bvalid), - .imem_master_rdata(near_mem$imem_master_rdata), - .imem_master_rid(near_mem$imem_master_rid), - .imem_master_rlast(near_mem$imem_master_rlast), - .imem_master_rresp(near_mem$imem_master_rresp), - .imem_master_rvalid(near_mem$imem_master_rvalid), - .imem_master_wready(near_mem$imem_master_wready), - .imem_req_addr(near_mem$imem_req_addr), - .imem_req_f3(near_mem$imem_req_f3), - .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR), - .imem_req_priv(near_mem$imem_req_priv), - .imem_req_satp(near_mem$imem_req_satp), - .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM), - .server_fence_request_put(near_mem$server_fence_request_put), - .EN_server_reset_request_put(near_mem$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem$EN_server_reset_response_get), - .EN_imem_req(near_mem$EN_imem_req), - .EN_dmem_req(near_mem$EN_dmem_req), - .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put), - .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get), - .EN_server_fence_request_put(near_mem$EN_server_fence_request_put), - .EN_server_fence_response_get(near_mem$EN_server_fence_response_get), - .EN_sfence_vma(near_mem$EN_sfence_vma), - .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get), - .imem_valid(near_mem$imem_valid), - .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16), - .imem_pc(near_mem$imem_pc), - .imem_instr(near_mem$imem_instr), - .imem_exc(near_mem$imem_exc), - .imem_exc_code(near_mem$imem_exc_code), - .imem_tval(), - .imem_master_awvalid(near_mem$imem_master_awvalid), - .imem_master_awid(near_mem$imem_master_awid), - .imem_master_awaddr(near_mem$imem_master_awaddr), - .imem_master_awlen(near_mem$imem_master_awlen), - .imem_master_awsize(near_mem$imem_master_awsize), - .imem_master_awburst(near_mem$imem_master_awburst), - .imem_master_awlock(near_mem$imem_master_awlock), - .imem_master_awcache(near_mem$imem_master_awcache), - .imem_master_awprot(near_mem$imem_master_awprot), - .imem_master_awqos(near_mem$imem_master_awqos), - .imem_master_awregion(near_mem$imem_master_awregion), - .imem_master_wvalid(near_mem$imem_master_wvalid), - .imem_master_wid(near_mem$imem_master_wid), - .imem_master_wdata(near_mem$imem_master_wdata), - .imem_master_wstrb(near_mem$imem_master_wstrb), - .imem_master_wlast(near_mem$imem_master_wlast), - .imem_master_bready(near_mem$imem_master_bready), - .imem_master_arvalid(near_mem$imem_master_arvalid), - .imem_master_arid(near_mem$imem_master_arid), - .imem_master_araddr(near_mem$imem_master_araddr), - .imem_master_arlen(near_mem$imem_master_arlen), - .imem_master_arsize(near_mem$imem_master_arsize), - .imem_master_arburst(near_mem$imem_master_arburst), - .imem_master_arlock(near_mem$imem_master_arlock), - .imem_master_arcache(near_mem$imem_master_arcache), - .imem_master_arprot(near_mem$imem_master_arprot), - .imem_master_arqos(near_mem$imem_master_arqos), - .imem_master_arregion(near_mem$imem_master_arregion), - .imem_master_rready(near_mem$imem_master_rready), - .dmem_valid(near_mem$dmem_valid), - .dmem_word64(near_mem$dmem_word64), - .dmem_st_amo_val(), - .dmem_exc(near_mem$dmem_exc), - .dmem_exc_code(near_mem$dmem_exc_code), - .dmem_master_awvalid(near_mem$dmem_master_awvalid), - .dmem_master_awid(near_mem$dmem_master_awid), - .dmem_master_awaddr(near_mem$dmem_master_awaddr), - .dmem_master_awlen(near_mem$dmem_master_awlen), - .dmem_master_awsize(near_mem$dmem_master_awsize), - .dmem_master_awburst(near_mem$dmem_master_awburst), - .dmem_master_awlock(near_mem$dmem_master_awlock), - .dmem_master_awcache(near_mem$dmem_master_awcache), - .dmem_master_awprot(near_mem$dmem_master_awprot), - .dmem_master_awqos(near_mem$dmem_master_awqos), - .dmem_master_awregion(near_mem$dmem_master_awregion), - .dmem_master_wvalid(near_mem$dmem_master_wvalid), - .dmem_master_wid(near_mem$dmem_master_wid), - .dmem_master_wdata(near_mem$dmem_master_wdata), - .dmem_master_wstrb(near_mem$dmem_master_wstrb), - .dmem_master_wlast(near_mem$dmem_master_wlast), - .dmem_master_bready(near_mem$dmem_master_bready), - .dmem_master_arvalid(near_mem$dmem_master_arvalid), - .dmem_master_arid(near_mem$dmem_master_arid), - .dmem_master_araddr(near_mem$dmem_master_araddr), - .dmem_master_arlen(near_mem$dmem_master_arlen), - .dmem_master_arsize(near_mem$dmem_master_arsize), - .dmem_master_arburst(near_mem$dmem_master_arburst), - .dmem_master_arlock(near_mem$dmem_master_arlock), - .dmem_master_arcache(near_mem$dmem_master_arcache), - .dmem_master_arprot(near_mem$dmem_master_arprot), - .dmem_master_arqos(near_mem$dmem_master_arqos), - .dmem_master_arregion(near_mem$dmem_master_arregion), - .dmem_master_rready(near_mem$dmem_master_rready), - .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put), - .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get), - .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put), - .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get), - .RDY_sfence_vma()); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(soc_map$m_pc_reset_value), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule stage1_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_reqs$ENQ), - .DEQ(stage1_f_reset_reqs$DEQ), - .CLR(stage1_f_reset_reqs$CLR), - .FULL_N(stage1_f_reset_reqs$FULL_N), - .EMPTY_N(stage1_f_reset_reqs$EMPTY_N)); - - // submodule stage1_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_rsps$ENQ), - .DEQ(stage1_f_reset_rsps$DEQ), - .CLR(stage1_f_reset_rsps$CLR), - .FULL_N(stage1_f_reset_rsps$FULL_N), - .EMPTY_N(stage1_f_reset_rsps$EMPTY_N)); - - // submodule stage2_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_reqs$ENQ), - .DEQ(stage2_f_reset_reqs$DEQ), - .CLR(stage2_f_reset_reqs$CLR), - .FULL_N(stage2_f_reset_reqs$FULL_N), - .EMPTY_N(stage2_f_reset_reqs$EMPTY_N)); - - // submodule stage2_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_rsps$ENQ), - .DEQ(stage2_f_reset_rsps$DEQ), - .CLR(stage2_f_reset_rsps$CLR), - .FULL_N(stage2_f_reset_rsps$FULL_N), - .EMPTY_N(stage2_f_reset_rsps$EMPTY_N)); - - // submodule stage2_fbox - mkFBox_Top stage2_fbox(.CLK(CLK), - .RST_N(RST_N), - .req_f7(stage2_fbox$req_f7), - .req_opcode(stage2_fbox$req_opcode), - .req_rm(stage2_fbox$req_rm), - .req_rs2(stage2_fbox$req_rs2), - .req_v1(stage2_fbox$req_v1), - .req_v2(stage2_fbox$req_v2), - .req_v3(stage2_fbox$req_v3), - .EN_server_reset_request_put(stage2_fbox$EN_server_reset_request_put), - .EN_server_reset_response_get(stage2_fbox$EN_server_reset_response_get), - .EN_req(stage2_fbox$EN_req), - .RDY_server_reset_request_put(stage2_fbox$RDY_server_reset_request_put), - .RDY_server_reset_response_get(stage2_fbox$RDY_server_reset_response_get), - .valid(stage2_fbox$valid), - .word_fst(stage2_fbox$word_fst), - .word_snd(stage2_fbox$word_snd)); - - // submodule stage2_mbox - mkRISCV_MBox stage2_mbox(.CLK(CLK), - .RST_N(RST_N), - .req_f3(stage2_mbox$req_f3), - .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32), - .req_v1(stage2_mbox$req_v1), - .req_v2(stage2_mbox$req_v2), - .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity), - .EN_set_verbosity(stage2_mbox$EN_set_verbosity), - .EN_req_reset(stage2_mbox$EN_req_reset), - .EN_rsp_reset(stage2_mbox$EN_rsp_reset), - .EN_req(stage2_mbox$EN_req), - .RDY_set_verbosity(), - .RDY_req_reset(), - .RDY_rsp_reset(), - .valid(stage2_mbox$valid), - .word(stage2_mbox$word)); - - // submodule stage3_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_reqs$ENQ), - .DEQ(stage3_f_reset_reqs$DEQ), - .CLR(stage3_f_reset_reqs$CLR), - .FULL_N(stage3_f_reset_reqs$FULL_N), - .EMPTY_N(stage3_f_reset_reqs$EMPTY_N)); - - // submodule stage3_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_rsps$ENQ), - .DEQ(stage3_f_reset_rsps$DEQ), - .CLR(stage3_f_reset_rsps$CLR), - .FULL_N(stage3_f_reset_rsps$FULL_N), - .EMPTY_N(stage3_f_reset_rsps$EMPTY_N)); - - // rule RL_rl_show_pipe - assign CAN_FIRE_RL_rl_show_pipe = - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - rg_state != 4'd0 && - rg_state != 4'd1 && - rg_state != 4'd10 ; - assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ; - - // rule RL_rl_stage2_nonpipe - assign CAN_FIRE_RL_rl_stage2_nonpipe = - rg_state == 4'd3 && !stage3_rg_full && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd3 && - (!stage1_rg_full || - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622) ; - assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ; - - // rule RL_rl_stage1_CSRR_W - assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_stage1_CSRR_S_or_C - assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_stage1_restart_after_csrrx - assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx = - CAN_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // rule RL_rl_stage1_xRET - assign CAN_FIRE_RL_rl_stage1_xRET = - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd7 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd8 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd9) ; - assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ; - - // rule RL_rl_stage1_FENCE_I - assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - - // rule RL_rl_finish_FENCE_I - assign CAN_FIRE_RL_rl_finish_FENCE_I = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_i_response_get && - rg_state == 4'd7 ; - assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ; - - // rule RL_rl_stage1_FENCE - assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - - // rule RL_rl_finish_FENCE - assign CAN_FIRE_RL_rl_finish_FENCE = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_response_get && - rg_state == 4'd8 ; - assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ; - - // rule RL_rl_finish_SFENCE_VMA - assign CAN_FIRE_RL_rl_finish_SFENCE_VMA = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_finish_SFENCE_VMA = - CAN_FIRE_RL_rl_finish_SFENCE_VMA ; - - // rule RL_rl_stage1_WFI - assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - - // rule RL_rl_WFI_resume - assign CAN_FIRE_RL_rl_WFI_resume = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd10 && - csr_regfile$wfi_resume ; - assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ; - - // rule RL_rl_reset_from_WFI - assign CAN_FIRE_RL_rl_reset_from_WFI = - rg_state == 4'd10 && f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_4 ; - - // rule RL_rl_stage1_trap - assign CAN_FIRE_RL_rl_stage1_trap = - rg_state == 4'd4 || - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd11 ; - assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ; - - // rule RL_rl_trap_fetch - assign CAN_FIRE_RL_rl_trap_fetch = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd5 ; - assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; - - // rule RL_rl_stage1_interrupt - assign CAN_FIRE_RL_rl_stage1_interrupt = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - rg_state == 4'd3 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1602 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd0 && - !stage3_rg_full ; - assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ; - - // rule RL_imem_rl_assert_fail - assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ; - assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = - gpr_regfile$RDY_server_reset_response_get && - fpr_regfile$RDY_server_reset_response_get && - near_mem$RDY_server_reset_response_get && - csr_regfile$RDY_server_reset_response_get && - stage1_f_reset_rsps$EMPTY_N && - stage2_f_reset_rsps_i_notEmpty__571_AND_stage3_ETC___d1580 && - rg_state == 4'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_pipe - assign CAN_FIRE_RL_rl_pipe = - (csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1616 || - !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state_6_EQ_3_618_AND_stage3_rg_full_2_OR_NO_ETC___d1637 ; - assign WILL_FIRE_RL_rl_pipe = - CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_rl_stage1_SFENCE_VMA - assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = - gpr_regfile$RDY_server_reset_request_put && - fpr_regfile_RDY_server_reset_request_put__548__ETC___d1560 && - rg_state == 4'd0 ; - assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ; - - // rule RL_imem_rl_fetch_next_32b - assign CAN_FIRE_RL_imem_rl_fetch_next_32b = - near_mem$imem_valid && - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] == 2'b11 ; - assign WILL_FIRE_RL_imem_rl_fetch_next_32b = - CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_stage3_rl_reset - assign CAN_FIRE_RL_stage3_rl_reset = - stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ; - - // rule RL_stage2_rl_reset_end - assign CAN_FIRE_RL_stage2_rl_reset_end = - stage2_fbox$RDY_server_reset_response_get && - stage2_f_reset_rsps$FULL_N && - stage2_rg_resetting ; - assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ; - - // rule RL_stage2_rl_reset_begin - assign CAN_FIRE_RL_stage2_rl_reset_begin = - stage2_fbox$RDY_server_reset_request_put && - stage2_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_stage2_rl_reset_begin = - CAN_FIRE_RL_stage2_rl_reset_begin ; - - // rule RL_stage1_rl_reset - assign CAN_FIRE_RL_stage1_rl_reset = - stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_csr_regfile$mav_csr_write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 ; - assign MUX_gpr_regfile$write_rd_1__SEL_2 = - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - assign MUX_gpr_regfile$write_rd_1__SEL_3 = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - !stage3_rg_stage3[69] ; - assign MUX_imem_rg_f3$write_1__SEL_1 = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ; - assign MUX_imem_rg_f3$write_1__SEL_2 = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 ; - assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_imem_rg_pc$write_1__SEL_4 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_near_mem$imem_req_1__SEL_6 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_rg_cur_priv$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_mstatus_MXR$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_next_pc$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign MUX_rg_state$write_1__SEL_1 = - CAN_FIRE_RL_rl_reset_complete && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_2 = - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd2 ; - assign MUX_rg_state$write_1__SEL_3 = - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd3 ; - assign MUX_rg_state$write_1__SEL_4 = - CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ; - assign MUX_rg_state$write_1__SEL_6 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_rg_state$write_1__SEL_7 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_state$write_1__SEL_8 = - near_mem$RDY_server_fence_i_request_put && - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd5 ; - assign MUX_rg_state$write_1__SEL_9 = - near_mem$RDY_server_fence_request_put && - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd4 ; - assign MUX_rg_state$write_1__SEL_10 = - CAN_FIRE_RL_rl_stage1_SFENCE_VMA && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_11 = - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd10 ; - assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 = - (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ? - csr_regfile$interrupt_pending[3:0] : - 4'd0 ; - always@(x_out_data_to_stage2_instr__h13745 or - csr_regfile$read_csr or - y__h22359 or - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1801) - begin - case (x_out_data_to_stage2_instr__h13745[14:12]) - 3'b010, 3'b110: - MUX_csr_regfile$mav_csr_write_2__VAL_2 = - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1801; - default: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - csr_regfile$read_csr[31:0] & y__h22359; - endcase - end - assign MUX_near_mem$imem_req_2__VAL_1 = - { soc_map$m_pc_reset_value[31:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_2 = - { x_out_next_pc__h13711[31:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[31:2], 2'b0 } ; - assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd3 : 4'd2 ; - assign MUX_rg_state$write_1__VAL_2 = - csr_regfile$access_permitted_1 ? 4'd6 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_3 = - csr_regfile$access_permitted_2 ? 4'd6 : 4'd4 ; - assign MUX_stage1_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1749 || - (csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1610 || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1631) && - stage1_rg_full ; - assign MUX_stage2_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1744 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd2 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd0 ; - - // register cfg_logdelay - assign cfg_logdelay$D_IN = set_verbosity_logdelay ; - assign cfg_logdelay$EN = EN_set_verbosity ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register imem_rg_f3 - assign imem_rg_f3$D_IN = 3'b010 ; - assign imem_rg_f3$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_instr_15_0 - assign imem_rg_instr_15_0$D_IN = near_mem$imem_instr[31:16] ; - assign imem_rg_instr_15_0$EN = CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // register imem_rg_mstatus_MXR - assign imem_rg_mstatus_MXR$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_mstatus[19] : - rg_mstatus_MXR ; - assign imem_rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_pc - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h13711 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0]; - MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h13711; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_pc$D_IN = x_out_next_pc__h13711; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc; - default: imem_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_pc$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - - // register imem_rg_priv - assign imem_rg_priv$D_IN = rg_cur_priv ; - assign imem_rg_priv$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_satp - assign imem_rg_satp$D_IN = csr_regfile$read_satp ; - assign imem_rg_satp$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_sstatus_SUM - assign imem_rg_sstatus_SUM$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_sstatus[18] : - rg_sstatus_SUM ; - assign imem_rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_tval - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h13711 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or - rg_next_pc or - WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h16893) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_tval$D_IN = soc_map$m_pc_reset_value[31:0]; - MUX_imem_rg_f3$write_1__SEL_2: - imem_rg_tval$D_IN = x_out_next_pc__h13711; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_tval$D_IN = x_out_next_pc__h13711; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - imem_rg_tval$D_IN = next_pc___1__h16893; - default: imem_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_tval$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // register rg_cur_priv - always@(MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or - csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_cur_priv$write_1__SEL_1: - rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[33:32]; - WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11; - default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_cur_priv$EN = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_mstatus[19] : - csr_regfile$csr_trap_actions[53] ; - assign rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_next_pc - always@(MUX_rg_next_pc$write_1__SEL_1 or - x_out_next_pc__h13711 or - MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h13711; - MUX_rg_cur_priv$write_1__SEL_1: - rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34]; - default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_next_pc$EN = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET ; - - // register rg_run_on_reset - assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ; - assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_sstatus[18] : - csr_regfile$csr_trap_actions[52] ; - assign rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_start_CPI_cycles - assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ; - assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_start_CPI_instrs - assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ; - assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_state - always@(WILL_FIRE_RL_rl_reset_complete or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_stage1_CSRR_W or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or - MUX_rg_state$write_1__VAL_3 or - WILL_FIRE_RL_rl_reset_from_WFI or - WILL_FIRE_RL_rl_reset_start or - MUX_rg_state$write_1__SEL_6 or - MUX_rg_state$write_1__SEL_7 or - WILL_FIRE_RL_rl_stage1_FENCE_I or - WILL_FIRE_RL_rl_stage1_FENCE or - WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_reset_complete: - rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_stage1_CSRR_W: - rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: - rg_state$D_IN = MUX_rg_state$write_1__VAL_3; - WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1; - MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd5; - WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd7; - WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd8; - WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd10; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_complete || - WILL_FIRE_RL_rl_stage1_CSRR_W || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C || - WILL_FIRE_RL_rl_reset_from_WFI || - WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_WFI ; - - // register stage1_rg_full - always@(WILL_FIRE_RL_stage1_rl_reset or - WILL_FIRE_RL_rl_pipe or - MUX_stage1_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or - WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_trap_fetch or - WILL_FIRE_RL_rl_stage1_trap or - WILL_FIRE_RL_rl_WFI_resume or - WILL_FIRE_RL_rl_finish_SFENCE_VMA or - WILL_FIRE_RL_rl_finish_FENCE or - WILL_FIRE_RL_rl_finish_FENCE_I or - WILL_FIRE_RL_rl_stage1_xRET or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_interrupt: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_trap_fetch: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_trap: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I: - stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_xRET: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0; - default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage1_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage1_rl_reset || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register stage2_rg_full - always@(WILL_FIRE_RL_stage2_rl_reset_begin or - WILL_FIRE_RL_rl_pipe or - MUX_stage2_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage2_rl_reset_begin: stage2_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage2_nonpipe: - stage2_rg_full$D_IN = 1'd0; - default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage2_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage2_rl_reset_begin ; - - // register stage2_rg_resetting - assign stage2_rg_resetting$D_IN = WILL_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_rg_resetting$EN = - WILL_FIRE_RL_stage2_rl_reset_end || - WILL_FIRE_RL_stage2_rl_reset_begin ; - - // register stage2_rg_stage2 - assign stage2_rg_stage2$D_IN = - { rg_cur_priv, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260, - x_out_data_to_stage2_rd__h13747, - x_out_data_to_stage2_addr__h13748, - x_out_data_to_stage2_val1__h13749, - x_out_data_to_stage2_val2__h13750, - x_out_data_to_stage2_val3__h13751, - _theResult____h4604[6:0] == 7'b0000111 || - (_theResult____h4604[6:0] == 7'b1010011 || - _theResult____h4604[6:0] == 7'b1000011 || - _theResult____h4604[6:0] == 7'b1000111 || - _theResult____h4604[6:0] == 7'b1001011 || - _theResult____h4604[6:0] == 7'b1001111) && - (_theResult____h4604[31:25] != 7'h61 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h61 || - _theResult____h4604[24:20] != 5'd1) && - _theResult____h4604[31:25] != 7'h71 && - _theResult____h4604[31:25] != 7'h51 && - (_theResult____h4604[31:25] != 7'h60 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h60 || - _theResult____h4604[24:20] != 5'd1) && - _theResult____h4604[31:25] != 7'h70 && - _theResult____h4604[31:25] != 7'h50, - x_out_data_to_stage2_rounding_mode__h13753 } ; - assign stage2_rg_stage2$EN = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 ; - - // register stage3_rg_full - always@(WILL_FIRE_RL_stage3_rl_reset or - WILL_FIRE_RL_rl_pipe or - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 or - MUX_imem_rg_f3$write_1__SEL_1) - case (1'b1) - WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage3_rg_full$D_IN = - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2; - MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0; - default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage3_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_stage3_rl_reset ; - - // register stage3_rg_stage3 - assign stage3_rg_stage3$D_IN = - { stage2_rg_stage2[299:236], - stage2_rg_stage2[301:300], - stage2_rg_stage2[235:233] == 3'd0 || - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160, - x_out_data_to_stage3_rd__h6239, - stage2_rg_stage2[235:233] != 3'd0 && - stage2_rg_stage2[235:233] != 3'd1 && - stage2_rg_stage2[235:233] != 3'd4 && - stage2_rg_stage2[235:233] != 3'd2 && - stage2_rg_stage2[235:233] != 3'd3, - stage2_rg_stage2[235:233] != 3'd0 && - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195, - x_out_data_to_stage3_fpr_flags__h6242, - x_out_data_to_stage3_rd_val__h6243 } ; - assign stage3_rg_stage3$EN = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd2 ; - - // submodule csr_regfile - assign csr_regfile$access_permitted_1_csr_addr = - x_out_data_to_stage2_instr__h13745[31:20] ; - assign csr_regfile$access_permitted_1_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ; - assign csr_regfile$access_permitted_2_csr_addr = - x_out_data_to_stage2_instr__h13745[31:20] ; - assign csr_regfile$access_permitted_2_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_2_read_not_write = - rs1_val__h22055 == 32'd0 ; - assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ; - assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ; - always@(IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178) - begin - case (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178) - 4'd7: csr_regfile$csr_ret_actions_from_priv = 2'b11; - 4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b01; - default: csr_regfile$csr_ret_actions_from_priv = 2'b0; - endcase - end - always@(WILL_FIRE_RL_rl_stage1_interrupt or - MUX_csr_regfile$csr_trap_actions_5__VAL_1 or - WILL_FIRE_RL_rl_stage1_trap or - x_out_trap_info_exc_code__h16729 or - WILL_FIRE_RL_rl_stage2_nonpipe or x_out_trap_info_exc_code__h6459) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_exc_code = - MUX_csr_regfile$csr_trap_actions_5__VAL_1; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h16729; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h6459; - default: csr_regfile$csr_trap_actions_exc_code = - 4'b1010 /* unspecified value */ ; - endcase - end - assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ; - assign csr_regfile$csr_trap_actions_interrupt = - WILL_FIRE_RL_rl_stage1_interrupt && !csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_nmi = - WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_pc = - (WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap) ? - imem_rg_pc : - value__h6422 ; - always@(WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_stage1_trap or - value__h16781 or WILL_FIRE_RL_rl_stage2_nonpipe or value__h6483) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_xtval = 32'd0; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_xtval = value__h16781; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_xtval = value__h6483; - default: csr_regfile$csr_trap_actions_xtval = - 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ; - assign csr_regfile$m_external_interrupt_req_set_not_clear = - m_external_interrupt_req_set_not_clear ; - assign csr_regfile$ma_update_fcsr_fflags_flags = stage3_rg_stage3[68:64] ; - assign csr_regfile$ma_update_mstatus_fs_fs = 2'h3 ; - assign csr_regfile$mav_csr_write_csr_addr = - x_out_data_to_stage2_instr__h13745[31:20] ; - assign csr_regfile$mav_csr_write_word = - MUX_csr_regfile$mav_csr_write_1__SEL_1 ? - rs1_val__h21562 : - MUX_csr_regfile$mav_csr_write_2__VAL_2 ; - assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ; - assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign csr_regfile$read_csr_csr_addr = - x_out_data_to_stage2_instr__h13745[31:20] ; - assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ; - assign csr_regfile$s_external_interrupt_req_set_not_clear = - s_external_interrupt_req_set_not_clear ; - assign csr_regfile$software_interrupt_req_set_not_clear = - software_interrupt_req_set_not_clear ; - assign csr_regfile$timer_interrupt_req_set_not_clear = - timer_interrupt_req_set_not_clear ; - assign csr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign csr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign csr_regfile$EN_mav_read_csr = 1'b0 ; - assign csr_regfile$EN_mav_csr_write = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h13745[19:15] != 5'd0 ; - assign csr_regfile$EN_ma_update_fcsr_fflags = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - stage3_rg_stage3[70] ; - assign csr_regfile$EN_ma_update_mstatus_fs = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - (stage3_rg_stage3[70] || stage3_rg_stage3[69]) ; - assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_1 ; - assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ; - assign csr_regfile$EN_csr_minstret_incr = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd2 || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_stage1_WFI || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign csr_regfile$EN_debug = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = hart0_server_reset_request_put ; - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = - gpr_regfile$RDY_server_reset_request_put && - fpr_regfile_RDY_server_reset_request_put__548__ETC___d1560 && - rg_state == 4'd0 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = rg_run_on_reset ; - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fpr_regfile - assign fpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign fpr_regfile$read_rs1_rs1 = _theResult____h4604[19:15] ; - assign fpr_regfile$read_rs2_rs2 = _theResult____h4604[24:20] ; - assign fpr_regfile$read_rs3_rs3 = _theResult____h4604[31:27] ; - assign fpr_regfile$write_rd_rd = stage3_rg_stage3[75:71] ; - assign fpr_regfile$write_rd_rd_val = stage3_rg_stage3[63:0] ; - assign fpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign fpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign fpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - stage3_rg_stage3[69] ; - - // submodule gpr_regfile - assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign gpr_regfile$read_rs1_rs1 = _theResult____h4604[19:15] ; - assign gpr_regfile$read_rs2_rs2 = _theResult____h4604[24:20] ; - assign gpr_regfile$write_rd_rd = - MUX_gpr_regfile$write_rd_1__SEL_3 ? - stage3_rg_stage3[75:71] : - x_out_data_to_stage2_instr__h13745[11:7] ; - assign gpr_regfile$write_rd_rd_val = - (MUX_csr_regfile$mav_csr_write_1__SEL_1 || - MUX_gpr_regfile$write_rd_1__SEL_2) ? - csr_regfile$read_csr[31:0] : - stage3_rg_stage3[31:0] ; - assign gpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign gpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign gpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - !stage3_rg_stage3[69] ; - - // submodule near_mem - assign near_mem$dmem_master_arready = dmem_master_arready ; - assign near_mem$dmem_master_awready = dmem_master_awready ; - assign near_mem$dmem_master_bid = dmem_master_bid ; - assign near_mem$dmem_master_bresp = dmem_master_bresp ; - assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; - assign near_mem$dmem_master_rdata = dmem_master_rdata ; - assign near_mem$dmem_master_rid = dmem_master_rid ; - assign near_mem$dmem_master_rlast = dmem_master_rlast ; - assign near_mem$dmem_master_rresp = dmem_master_rresp ; - assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; - assign near_mem$dmem_master_wready = dmem_master_wready ; - assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h13748 ; - assign near_mem$dmem_req_amo_funct7 = - x_out_data_to_stage2_val1__h13749[6:0] ; - assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h13745[14:12] ; - assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ; - always@(IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260) - begin - case (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260) - 3'd1: near_mem$dmem_req_op = 2'd0; - 3'd2: near_mem$dmem_req_op = 2'd1; - default: near_mem$dmem_req_op = 2'd2; - endcase - end - assign near_mem$dmem_req_priv = - csr_regfile$read_mstatus[17] ? - csr_regfile$read_mstatus[12:11] : - rg_cur_priv ; - assign near_mem$dmem_req_satp = csr_regfile$read_satp ; - assign near_mem$dmem_req_sstatus_SUM = csr_regfile$read_sstatus[18] ; - assign near_mem$dmem_req_store_value = x_out_data_to_stage2_val2__h13750 ; - assign near_mem$imem_master_arready = imem_master_arready ; - assign near_mem$imem_master_awready = imem_master_awready ; - assign near_mem$imem_master_bid = imem_master_bid ; - assign near_mem$imem_master_bresp = imem_master_bresp ; - assign near_mem$imem_master_bvalid = imem_master_bvalid ; - assign near_mem$imem_master_rdata = imem_master_rdata ; - assign near_mem$imem_master_rid = imem_master_rid ; - assign near_mem$imem_master_rlast = imem_master_rlast ; - assign near_mem$imem_master_rresp = imem_master_rresp ; - assign near_mem$imem_master_rvalid = imem_master_rvalid ; - assign near_mem$imem_master_wready = imem_master_wready ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_near_mem$imem_req_2__VAL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - MUX_near_mem$imem_req_2__VAL_2 or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - next_pc___1__h16893 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_trap_fetch or - MUX_near_mem$imem_req_2__VAL_5 or MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1; - MUX_imem_rg_f3$write_1__SEL_2: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_addr = next_pc___1__h16893; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - default: near_mem$imem_req_addr = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_f3 = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_mstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_mstatus_MXR or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_mstatus_MXR) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_mstatus_MXR = imem_rg_mstatus_MXR; - default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_priv = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - MUX_near_mem$imem_req_1__SEL_6) ? - rg_cur_priv : - imem_rg_priv ; - assign near_mem$imem_req_satp = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? - imem_rg_satp : - csr_regfile$read_satp ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_sstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_sstatus_SUM or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_sstatus_SUM) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_sstatus_SUM = csr_regfile$read_sstatus[18]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_sstatus_SUM = imem_rg_sstatus_SUM; - default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$server_fence_request_put = - 8'b10101010 /* unspecified value */ ; - assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ; - assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ; - assign near_mem$EN_imem_req = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_imem_rl_fetch_next_32b || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_dmem_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 && - (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == - 3'd1 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == - 3'd2 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == - 3'd4) ; - assign near_mem$EN_server_fence_i_request_put = - MUX_rg_state$write_1__SEL_8 ; - assign near_mem$EN_server_fence_i_response_get = - CAN_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_9 ; - assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ; - assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_10 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule stage1_f_reset_reqs - assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage1_f_reset_rsps - assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage1_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_f_reset_reqs - assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage2_f_reset_reqs$DEQ = CAN_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage2_f_reset_rsps - assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage2_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_fbox - assign stage2_fbox$req_f7 = x_out_data_to_stage2_instr__h13745[31:25] ; - assign stage2_fbox$req_opcode = x_out_data_to_stage2_instr__h13745[6:0] ; - assign stage2_fbox$req_rm = x_out_data_to_stage2_rounding_mode__h13753 ; - assign stage2_fbox$req_rs2 = x_out_data_to_stage2_instr__h13745[24:20] ; - assign stage2_fbox$req_v1 = x_out_data_to_stage2_val1__h13749 ; - assign stage2_fbox$req_v2 = x_out_data_to_stage2_val2__h13750 ; - assign stage2_fbox$req_v3 = x_out_data_to_stage2_val3__h13751 ; - assign stage2_fbox$EN_server_reset_request_put = - CAN_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_fbox$EN_server_reset_response_get = - CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_fbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == - 3'd5 ; - - // submodule stage2_mbox - assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h13745[14:12] ; - assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4604[3] ; - assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h13749[31:0] ; - assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h13750[31:0] ; - assign stage2_mbox$set_verbosity_verbosity = 4'h0 ; - assign stage2_mbox$EN_set_verbosity = 1'b0 ; - assign stage2_mbox$EN_req_reset = 1'b0 ; - assign stage2_mbox$EN_rsp_reset = 1'b0 ; - assign stage2_mbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == - 3'd3 ; - - // submodule stage3_f_reset_reqs - assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage3_f_reset_rsps - assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage3_f_reset_rsps$CLR = 1'b0 ; - - // remaining internal signals - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1095 = - ((_theResult____h4604[6:0] == 7'b0010011 || - _theResult____h4604[6:0] == 7'b0110011) && - (_theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101)) ? - !_theResult____h4604[25] : - CASE_theResult__604_BITS_6_TO_0_0b10011_IF_NOT_ETC__q12 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 = - (_theResult____h4604[6:0] == 7'b1100011) ? - (_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b110 || - _theResult____h4604[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 : - _theResult____h4604[6:0] != 7'b1101111 && - _theResult____h4604[6:0] != 7'b1100111 && - (_theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[31:25] == 7'b0000001 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1095) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100 = - (_theResult____h4604[6:0] == 7'b1100011) ? - (_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b110 || - _theResult____h4604[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 : - _theResult____h4604[6:0] == 7'b1101111 || - _theResult____h4604[6:0] == 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1112 = - ((_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011) && - (_theResult____h4604[6:0] != 7'b0000111 || - csr_regfile$read_mstatus[14:13] != 2'h0)) ? - 4'd0 : - 4'd11 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1116 = - ((_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011) && - (_theResult____h4604[6:0] != 7'b0100111 || - csr_regfile$read_mstatus[14:13] != 2'h0)) ? - 4'd0 : - 4'd11 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1154 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1127 ? - 4'd6 : - ((_theResult____h4604[11:7] == 5'd0 && - _theResult____h4604[19:15] == 5'd0) ? - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1152 : - 4'd11) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1412 = - ((_theResult____h4604[6:0] == 7'b0010011 || - _theResult____h4604[6:0] == 7'b0110011) && - (_theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101)) ? - alu_outputs___1_val1__h14035 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1432 = - (_theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[31:25] == 7'b0000001) ? - alu_outputs___1_val2__h15022 : - CASE_theResult__604_BITS_6_TO_0_0b100011_alu_o_ETC__q20 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1602 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661 = - rs1_val_bypassed__h4612 == rs2_val__h13850 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663 = - (rs1_val_bypassed__h4612 ^ 32'h80000000) < - (rs2_val__h13850 ^ 32'h80000000) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665 = - rs1_val_bypassed__h4612 < rs2_val__h13850 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937 = - ((_theResult____h4604[6:0] == 7'b0010011 || - _theResult____h4604[6:0] == 7'b0110011) && - (_theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101)) ? - _theResult____h4604[25] : - CASE_theResult__604_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 = - (_theResult____h4604[6:0] == 7'b1100011) ? - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b110 && - _theResult____h4604[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 : - _theResult____h4604[6:0] == 7'b1101111 || - _theResult____h4604[6:0] == 7'b1100111 || - (_theResult____h4604[6:0] != 7'b0110011 || - _theResult____h4604[31:25] != 7'b0000001) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951 = - (_theResult____h4604[6:0] == 7'b1100011) ? - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b110 && - _theResult____h4604[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 : - _theResult____h4604[6:0] != 7'b1101111 && - _theResult____h4604[6:0] != 7'b1100111 ; - assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1108 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d702 ? - 4'd11 : - 4'd0 ; - assign IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1162 = - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1084 ? - 4'd0 : - 4'd11 ; - assign IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d256 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - ((stage2_rg_stage2[3] || stage2_rg_stage2[232:228] == 5'd0) ? - 2'd0 : - IF_near_mem_dmem_valid__22_AND_NOT_near_mem_dm_ETC___d254) : - 2'd0 ; - assign IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d284 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - (stage2_rg_stage2[3] ? - IF_near_mem_dmem_valid__22_AND_NOT_near_mem_dm_ETC___d254 : - 2'd0) : - 2'd0 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1127 = - _theResult____h4604[11:7] == 5'd0 && - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) && - _theResult____h4604[31:25] == 7'b0001001 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1317 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 ? - next_pc___1__h16893 : - next_pc__h16891 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d971 = - _theResult____h4604[14:12] == 3'b0 && - (_theResult____h4604[6:0] != 7'b0110011 || - !_theResult____h4604[30]) || - _theResult____h4604[14:12] == 3'b0 && - _theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[30] || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b110 || - _theResult____h4604[14:12] == 3'b111 ; - assign IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 = - near_mem$imem_exc ? - 4'd11 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1176 ; - assign IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1851 = - imem_rg_pc == csr_regfile$csr_trap_actions[97:66] ; - assign IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 = - (!stage2_rg_full || stage2_rg_stage2[235:233] == 3'd0) ? - 2'd0 : - CASE_stage2_rg_stage2_BITS_235_TO_233_1_IF_NOT_ETC__q3 ; - assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1801 = - csr_regfile$read_csr[31:0] | rs1_val__h22055 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d570 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b111) ? - instr__h12993 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b101) ? - instr__h13466 : - 32'h0) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d571 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b011) ? - instr__h12798 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d570 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d572 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:13] == 3'b111) ? - instr__h12606 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d571 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d573 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[11:7] != 5'd0 && - instr__h4602[15:13] == 3'b011 && - csr_regfile$read_misa[5]) ? - instr__h12461 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d572 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d574 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:12] == 4'b1001 && - instr__h4602[11:7] == 5'd0 && - instr__h4602[6:2] == 5'd0) ? - instr__h12358 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d573 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d576 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:10] == 6'b100011 && - instr__h4602[6:5] == 2'b01) ? - instr__h11884 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:10] == 6'b100011 && - instr__h4602[6:5] == 2'b0) ? - instr__h12020 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d574) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d578 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:10] == 6'b100011 && - instr__h4602[6:5] == 2'b11) ? - instr__h11612 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:10] == 6'b100011 && - instr__h4602[6:5] == 2'b10) ? - instr__h11748 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d576) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d579 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d420 && - instr__h4602[6:2] != 5'd0) ? - instr__h11517 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d578 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d580 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d414 && - instr__h4602[6:2] != 5'd0) ? - instr__h11398 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d579 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d582 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b100 && - instr__h4602[11:10] == 2'b01 && - imm6__h9544 != 6'd0 && - !instr__h4602[12]) ? - instr__h11103 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b100 && - instr__h4602[11:10] == 2'b10) ? - instr__h11220 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d580) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d583 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b100 && - instr__h4602[11:10] == 2'b0 && - imm6__h9544 != 6'd0 && - !instr__h4602[12]) ? - instr__h10910 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d582 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d584 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:13] == 3'b0 && - instr__h4602[11:7] != 5'd0 && - imm6__h9544 != 6'd0 && - !instr__h4602[12]) ? - instr__h10717 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d583 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d586 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b011 && - instr__h4602[11:7] == 5'd2 && - nzimm10__h10168 != 10'd0) ? - instr__h10372 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b0 && - nzimm10__h10383 != 10'd0) ? - instr__h10544 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d584) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d587 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b0 && - instr__h4602[11:7] != 5'd0 && - imm6__h9544 != 6'd0 || - csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b0 && - instr__h4602[11:7] == 5'd0 && - imm6__h9544 == 6'd0) ? - instr__h9935 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d586 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d588 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b011 && - instr__h4602[11:7] != 5'd0 && - instr__h4602[11:7] != 5'd2 && - imm6__h9544 != 6'd0) ? - instr__h9806 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d587 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b111) ? - instr__h9284 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b010 && - instr__h4602[11:7] != 5'd0) ? - instr__h9622 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d588) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b110) ? - instr__h8967 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d420 && - instr__h4602[6:2] == 5'd0) ? - instr__h8902 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d414 && - instr__h4602[6:2] == 5'd0) ? - instr__h8786 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b001) ? - instr__h8396 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b101) ? - instr__h8053 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d596 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b110) ? - instr__h7824 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b010) ? - instr__h7629 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d596 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d598 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:13] == 3'b110) ? - instr__h7437 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597 ; - assign IF_near_mem_dmem_valid__22_AND_NOT_near_mem_dm_ETC___d254 = - (near_mem$dmem_valid && !near_mem$dmem_exc) ? 2'd2 : 2'd1 ; - assign IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125 = - near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ; - assign IF_rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7__ETC___d1150 = - ((rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) && - _theResult____h4604[31:20] == 12'b000100000010) ? - 4'd8 : - (rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7_EQ__ETC___d1148 ? - 4'd10 : - 4'd11) ; - assign IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129 = - stage2_fbox$valid ? 2'd2 : 2'd1 ; - assign IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127 = - stage2_mbox$valid ? 2'd2 : 2'd1 ; - assign IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1 : - 2'd0 ; - assign IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 : - 2'd0 ; - assign IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602 = - x_out_bypass_rd__h6717 == _theResult____h4604[19:15] ; - assign IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604 = - x_out_bypass_rd__h6717 == _theResult____h4604[24:20] ; - assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d702 = - (_theResult____h4604[14:12] != 3'b0 || - _theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[30]) && - (_theResult____h4604[14:12] != 3'b0 || - _theResult____h4604[6:0] != 7'b0110011 || - !_theResult____h4604[30]) && - _theResult____h4604[14:12] != 3'b010 && - _theResult____h4604[14:12] != 3'b011 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b110 && - _theResult____h4604[14:12] != 3'b111 ; - assign NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 = - cur_verbosity__h3131 > 4'd1 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - (!stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1631) && - (!stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1623) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1676 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1676 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd2 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd0) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1676 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd2 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd0) && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103 || - !stage1_rg_full ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1744 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__23_OR_IF_IF_NOT_n_ETC___d1742) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1746 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__23_OR_IF_IF_NOT_n_ETC___d1742) && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd2 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd0) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1749 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1746 && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103 || - !stage1_rg_full) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1763 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) ; - assign NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1084 = - csr_regfile$read_mstatus[14:13] != 2'h0 && - CASE_theResult__604_BITS_6_TO_0_0b1000011_theR_ETC__q10 && - ((_theResult____h4604[14:12] == 3'b111) ? - csr_regfile$read_frm != 3'b101 && - csr_regfile$read_frm != 3'b110 && - csr_regfile$read_frm != 3'b111 : - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b110) ; - assign NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1244 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd4 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd5 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd6 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd7 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd8 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd9 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd10 ; - assign NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1290 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 != - 3'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 != - 3'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 != - 3'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 != - 3'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 != - 3'd4 ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 = - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] != 2'b11) ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] == 2'b11) && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] == 2'b11) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1612 = - !near_mem$imem_valid || - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == - 2'd1 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1623 = - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607 || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1631 = - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951 ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607 = - !near_mem$imem_valid || - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == - 2'd1 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604) ; - assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1326 = - { {20{theResult__604_BITS_31_TO_20__q18[11]}}, - theResult__604_BITS_31_TO_20__q18 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400 = - { {9{offset__h8000[11]}}, offset__h8000 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429 = - { {4{offset__h8911[8]}}, offset__h8911 } ; - assign _0_OR_0_OR_near_mem_imem_exc__23_OR_IF_IF_NOT_n_ETC___d1742 = - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951 ; - assign _theResult_____1_fst__h15230 = - (_theResult____h4604[14:12] == 3'b0 && - _theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[30]) ? - rd_val___1__h15226 : - _theResult_____1_fst__h15237 ; - assign _theResult_____1_fst__h15265 = - rs1_val_bypassed__h4612 & _theResult___snd__h17391 ; - assign _theResult_____1_fst_rd_val__h6696 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - _theResult_____2_fst_rd_val__h6693 : - stage2_rg_stage2[163:132] ; - assign _theResult_____1_snd_fst_rd_val__h6855 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - _theResult_____2_snd_rd_val__h6852 : - stage2_rg_stage2[195:132] ; - assign _theResult_____2_fst_rd_val__h6693 = - (stage2_rg_stage2[3] || stage2_rg_stage2[232:228] == 5'd0) ? - stage2_rg_stage2[163:132] : - near_mem$dmem_word64[31:0] ; - assign _theResult_____2_snd_rd_val__h6852 = - stage2_rg_stage2[3] ? - data_to_stage3_rd_val__h6137 : - stage2_rg_stage2[195:132] ; - assign _theResult____h14024 = - (_theResult____h4604[14:12] == 3'b001) ? - rd_val__h17285 : - (_theResult____h4604[30] ? rd_val__h17359 : rd_val__h17337) ; - assign _theResult____h26769 = - (delta_CPI_instrs__h26768 == 64'd0) ? - delta_CPI_instrs___1__h26804 : - delta_CPI_instrs__h26768 ; - assign _theResult____h4604 = x_out_data_to_stage2_instr__h13745 ; - assign _theResult___fst__h7192 = - (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11) ? - instr_out___1__h7194 : - _theResult___fst__h7220 ; - assign _theResult___fst__h7220 = - (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11) ? - instr_out___1__h7222 : - near_mem$imem_instr ; - assign _theResult___fst_rd_val__h6707 = - stage2_rg_stage2[3] ? - stage2_rg_stage2[163:132] : - stage2_fbox$word_fst[31:0] ; - assign _theResult___snd__h17391 = - (_theResult____h4604[6:0] == 7'b0010011) ? - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1326 : - rs2_val__h13850 ; - assign _theResult___snd_rd_val__h6861 = - stage2_rg_stage2[3] ? - stage2_fbox$word_fst : - stage2_rg_stage2[195:132] ; - assign alu_outputs___1_addr__h13875 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 ? - branch_target__h13854 : - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1317 ; - assign alu_outputs___1_addr__h13899 = - imem_rg_pc + - { {11{theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q4[20]}}, - theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q4 } ; - assign alu_outputs___1_addr__h13928 = - { alu_outputs___1_addr__h14154[31:1], 1'd0 } ; - assign alu_outputs___1_addr__h14154 = - rs1_val_bypassed__h4612 + - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1326 ; - assign alu_outputs___1_addr__h14178 = - rs1_val_bypassed__h4612 + - { {20{theResult__604_BITS_31_TO_25_CONCAT_theResult__ETC__q6[11]}}, - theResult__604_BITS_31_TO_25_CONCAT_theResult__ETC__q6 } ; - assign alu_outputs___1_exc_code__h14461 = - (_theResult____h4604[14:12] == 3'b0) ? - (IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1127 ? - 4'd2 : - ((_theResult____h4604[11:7] == 5'd0 && - _theResult____h4604[19:15] == 5'd0) ? - CASE_theResult__604_BITS_31_TO_20_0b0_CASE_rg__ETC__q14 : - 4'd2)) : - 4'd2 ; - assign alu_outputs___1_val1__h13900 = - { 32'd0, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1317 } ; - assign alu_outputs___1_val1__h14035 = { 32'd0, _theResult____h14024 } ; - assign alu_outputs___1_val1__h14076 = { 32'd0, rd_val__h14066 } ; - assign alu_outputs___1_val1__h14095 = { 32'd0, rd_val__h14086 } ; - assign alu_outputs___1_val1__h14114 = { 32'd0, rd_val__h14105 } ; - assign alu_outputs___1_val1__h14465 = { 32'd0, rs1_val__h14431 } ; - assign alu_outputs___1_val1__h14489 = - { 57'd0, _theResult____h4604[31:25] } ; - assign alu_outputs___1_val1__h14666 = - (_theResult____h4604[6:0] == 7'b1010011 && - (_theResult____h4604[31:25] == 7'h69 && - (_theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[24:20] == 5'd1) || - _theResult____h4604[31:25] == 7'h79 || - _theResult____h4604[31:25] == 7'h68 && - (_theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[24:20] == 5'd1) || - _theResult____h4604[31:25] == 7'h78)) ? - alu_outputs___1_val1__h15021 : - frs1_val_bypassed__h4623 ; - assign alu_outputs___1_val1__h15021 = { 32'd0, rs1_val_bypassed__h4612 } ; - assign alu_outputs___1_val2__h13877 = { 32'd0, branch_target__h13854 } ; - assign alu_outputs___1_val2__h14180 = - (_theResult____h4604[6:0] == 7'b0100111) ? - frs2_val_bypassed__h4628 : - alu_outputs___1_val2__h15022 ; - assign alu_outputs___1_val2__h15022 = { 32'd0, rs2_val__h13850 } ; - assign branch_target__h13854 = - imem_rg_pc + - { {19{theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q5[12]}}, - theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q5 } ; - assign cpi__h26771 = x__h26770 / 64'd10 ; - assign cpifrac__h26772 = x__h26770 % 64'd10 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1605 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1601 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1602 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1610 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd2 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd0 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1616 = - csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1605 || - (csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1610 || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1612 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - stage1_rg_full ; - assign csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d1854 = - delta_CPI_cycles__h26767 * 64'd10 ; - assign csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d414 = - csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:12] == 4'b1000 && - instr__h4602[11:7] != 5'd0 ; - assign csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d420 = - csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:12] == 4'b1001 && - instr__h4602[11:7] != 5'd0 ; - assign csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d926 = - csr_regfile$read_mstatus[14:13] == 2'h0 || - CASE_theResult__604_BITS_6_TO_0_0b1000011_NOT__ETC__q7 || - ((_theResult____h4604[14:12] == 3'b111) ? - csr_regfile$read_frm == 3'b101 || - csr_regfile$read_frm == 3'b110 || - csr_regfile$read_frm == 3'b111 : - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b110) ; - assign cur_verbosity__h3131 = - (csr_regfile$read_csr_minstret < cfg_logdelay) ? - 4'd0 : - cfg_verbosity ; - assign data_to_stage2_addr__h13737 = x_out_data_to_stage2_addr__h13748 ; - assign data_to_stage3_rd_val__h6137 = - stage2_rg_stage2[3] ? - ((stage2_rg_stage2[250:248] == 3'b010) ? - { 32'hFFFFFFFF, near_mem$dmem_word64[31:0] } : - near_mem$dmem_word64) : - near_mem$dmem_word64 ; - assign delta_CPI_cycles__h26767 = - csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ; - assign delta_CPI_instrs___1__h26804 = delta_CPI_instrs__h26768 + 64'd1 ; - assign delta_CPI_instrs__h26768 = - csr_regfile$read_csr_minstret - rg_start_CPI_instrs ; - assign fall_through_pc__h13698 = - imem_rg_pc + - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d614 ? - 32'd4 : - 32'd2) ; - assign fpr_regfile_RDY_server_reset_request_put__548__ETC___d1560 = - fpr_regfile$RDY_server_reset_request_put && - near_mem$RDY_server_reset_request_put && - csr_regfile$RDY_server_reset_request_put && - f_reset_reqs$EMPTY_N && - stage1_f_reset_reqs$FULL_N && - stage2_f_reset_reqs$FULL_N && - stage3_f_reset_reqs$FULL_N ; - assign frs1_val_bypassed__h4623 = - (IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6869 == _theResult____h4604[19:15]) ? - x_out_fbypass_rd_val__h6870 : - rd_val__h17575 ; - assign frs2_val_bypassed__h4628 = - (IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6869 == _theResult____h4604[24:20]) ? - x_out_fbypass_rd_val__h6870 : - rd_val__h17628 ; - assign imm12__h10170 = { {2{nzimm10__h10168[9]}}, nzimm10__h10168 } ; - assign imm12__h10385 = { 2'd0, nzimm10__h10383 } ; - assign imm12__h10581 = { 7'b0, instr__h4602[6:2] } ; - assign imm12__h10926 = { 7'b0100000, instr__h4602[6:2] } ; - assign imm12__h7293 = { 4'd0, offset__h7063 } ; - assign imm12__h7630 = { 5'd0, offset__h7572 } ; - assign imm12__h9546 = { {6{imm6__h9544[5]}}, imm6__h9544 } ; - assign imm20__h9674 = { {14{imm6__h9544[5]}}, imm6__h9544 } ; - assign imm6__h9544 = { instr__h4602[12], instr__h4602[6:2] } ; - assign instr___1__h7017 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[11:7] != 5'd0 && - instr__h4602[15:13] == 3'b010) ? - instr__h7292 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d598 ; - assign instr__h10372 = - { imm12__h10170, - instr__h4602[11:7], - 3'b0, - instr__h4602[11:7], - 7'b0010011 } ; - assign instr__h10544 = { imm12__h10385, 8'd16, rd__h7632, 7'b0010011 } ; - assign instr__h10717 = - { imm12__h10581, - instr__h4602[11:7], - 3'b001, - instr__h4602[11:7], - 7'b0010011 } ; - assign instr__h10910 = - { imm12__h10581, rs1__h7631, 3'b101, rs1__h7631, 7'b0010011 } ; - assign instr__h11103 = - { imm12__h10926, rs1__h7631, 3'b101, rs1__h7631, 7'b0010011 } ; - assign instr__h11220 = - { imm12__h9546, rs1__h7631, 3'b111, rs1__h7631, 7'b0010011 } ; - assign instr__h11398 = - { 7'b0, - instr__h4602[6:2], - 8'd0, - instr__h4602[11:7], - 7'b0110011 } ; - assign instr__h11517 = - { 7'b0, - instr__h4602[6:2], - instr__h4602[11:7], - 3'b0, - instr__h4602[11:7], - 7'b0110011 } ; - assign instr__h11612 = - { 7'b0, rd__h7632, rs1__h7631, 3'b111, rs1__h7631, 7'b0110011 } ; - assign instr__h11748 = - { 7'b0, rd__h7632, rs1__h7631, 3'b110, rs1__h7631, 7'b0110011 } ; - assign instr__h11884 = - { 7'b0, rd__h7632, rs1__h7631, 3'b100, rs1__h7631, 7'b0110011 } ; - assign instr__h12020 = - { 7'b0100000, - rd__h7632, - rs1__h7631, - 3'b0, - rs1__h7631, - 7'b0110011 } ; - assign instr__h12358 = - { 12'b000000000001, - instr__h4602[11:7], - 3'b0, - instr__h4602[11:7], - 7'b1110011 } ; - assign instr__h12461 = - { imm12__h7293, 8'd18, instr__h4602[11:7], 7'b0000111 } ; - assign instr__h12606 = - { 4'd0, - instr__h4602[8:7], - instr__h4602[12], - instr__h4602[6:2], - 8'd18, - offset_BITS_4_TO_0___h7561, - 7'b0100111 } ; - assign instr__h12798 = - { imm12__h7630, rs1__h7631, 3'b010, rd__h7632, 7'b0000111 } ; - assign instr__h12993 = - { 5'd0, - instr__h4602[5], - instr__h4602[12], - rd__h7632, - rs1__h7631, - 3'b010, - offset_BITS_4_TO_0___h7992, - 7'b0100111 } ; - assign instr__h13466 = - { 4'd0, - instr__h4602[6:5], - instr__h4602[12], - rd__h7632, - rs1__h7631, - 3'b011, - offset_BITS_4_TO_0___h13591, - 7'b0100111 } ; - assign instr__h4602 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 ? - instr_out___1__h7162 : - _theResult___fst__h7192 ; - assign instr__h7292 = - { imm12__h7293, 8'd18, instr__h4602[11:7], 7'b0000011 } ; - assign instr__h7437 = - { 4'd0, - instr__h4602[8:7], - instr__h4602[12], - instr__h4602[6:2], - 8'd18, - offset_BITS_4_TO_0___h7561, - 7'b0100011 } ; - assign instr__h7629 = - { imm12__h7630, rs1__h7631, 3'b010, rd__h7632, 7'b0000011 } ; - assign instr__h7824 = - { 5'd0, - instr__h4602[5], - instr__h4602[12], - rd__h7632, - rs1__h7631, - 3'b010, - offset_BITS_4_TO_0___h7992, - 7'b0100011 } ; - assign instr__h8053 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[19:12], - 12'd111 } ; - assign instr__h8396 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[19:12], - 12'd239 } ; - assign instr__h8786 = { 12'd0, instr__h4602[11:7], 15'd103 } ; - assign instr__h8902 = { 12'd0, instr__h4602[11:7], 15'd231 } ; - assign instr__h8967 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[10:5], - 5'd0, - rs1__h7631, - 3'b0, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[11], - 7'b1100011 } ; - assign instr__h9284 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[10:5], - 5'd0, - rs1__h7631, - 3'b001, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[11], - 7'b1100011 } ; - assign instr__h9622 = - { imm12__h9546, 8'd0, instr__h4602[11:7], 7'b0010011 } ; - assign instr__h9806 = { imm20__h9674, instr__h4602[11:7], 7'b0110111 } ; - assign instr__h9935 = - { imm12__h9546, - instr__h4602[11:7], - 3'b0, - instr__h4602[11:7], - 7'b0010011 } ; - assign instr_out___1__h7162 = - { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ; - assign instr_out___1__h7194 = { 16'b0, near_mem$imem_instr[15:0] } ; - assign instr_out___1__h7222 = { 16'b0, near_mem$imem_instr[31:16] } ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1457 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd0 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1460 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd1 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1463 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd2 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1466 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd3 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1469 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd4 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1472 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd5 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1475 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd6 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1478 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd7 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1481 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd8 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1484 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd9 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1487 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd10 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1490 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd4 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd5 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd6 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd7 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd8 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd9 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd10 ; - assign near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 = - near_mem$imem_pc[31:2] == imem_rg_pc[31:2] ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d614 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] == 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d616 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d614 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 = - near_mem$imem_pc == next_pc___1__h16893 ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1601 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 != - 2'd1 || - !IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602 && - !IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d616 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 != - 2'd1 || - !IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602 && - !IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) ; - assign next_pc___1__h16893 = imem_rg_pc + 32'd2 ; - assign next_pc__h16891 = imem_rg_pc + 32'd4 ; - assign nzimm10__h10168 = - { instr__h4602[12], - instr__h4602[4:3], - instr__h4602[5], - instr__h4602[2], - instr__h4602[6], - 4'b0 } ; - assign nzimm10__h10383 = - { instr__h4602[10:7], - instr__h4602[12:11], - instr__h4602[5], - instr__h4602[6], - 2'b0 } ; - assign offset_BITS_4_TO_0___h13591 = { instr__h4602[11:10], 3'b0 } ; - assign offset_BITS_4_TO_0___h7561 = { instr__h4602[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h7992 = - { instr__h4602[11:10], instr__h4602[6], 2'b0 } ; - assign offset__h7063 = - { instr__h4602[3:2], - instr__h4602[12], - instr__h4602[6:4], - 2'b0 } ; - assign offset__h7572 = - { instr__h4602[5], instr__h4602[12:10], instr__h4602[6], 2'b0 } ; - assign offset__h8000 = - { instr__h4602[12], - instr__h4602[8], - instr__h4602[10:9], - instr__h4602[6], - instr__h4602[7], - instr__h4602[2], - instr__h4602[11], - instr__h4602[5:3], - 1'b0 } ; - assign offset__h8911 = - { instr__h4602[12], - instr__h4602[6:5], - instr__h4602[2], - instr__h4602[11:10], - instr__h4602[4:3], - 1'b0 } ; - assign output_stage2___1_data_to_stage3_rd_val__h6211 = - { 32'd0, stage2_mbox$word } ; - assign rd__h7632 = { 2'b01, instr__h4602[4:2] } ; - assign rd_val___1__h15218 = - rs1_val_bypassed__h4612 + _theResult___snd__h17391 ; - assign rd_val___1__h15226 = - rs1_val_bypassed__h4612 - _theResult___snd__h17391 ; - assign rd_val___1__h15233 = - ((rs1_val_bypassed__h4612 ^ 32'h80000000) < - (_theResult___snd__h17391 ^ 32'h80000000)) ? - 32'd1 : - 32'd0 ; - assign rd_val___1__h15240 = - (rs1_val_bypassed__h4612 < _theResult___snd__h17391) ? - 32'd1 : - 32'd0 ; - assign rd_val___1__h15247 = - rs1_val_bypassed__h4612 ^ _theResult___snd__h17391 ; - assign rd_val___1__h15254 = - rs1_val_bypassed__h4612 | _theResult___snd__h17391 ; - assign rd_val__h13631 = - (!stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d647) ? - stage3_rg_stage3[31:0] : - gpr_regfile$read_rs1 ; - assign rd_val__h13674 = - (!stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d655) ? - stage3_rg_stage3[31:0] : - gpr_regfile$read_rs2 ; - assign rd_val__h14066 = - (_theResult____h4604[14:12] == 3'b0 && - (_theResult____h4604[6:0] != 7'b0110011 || - !_theResult____h4604[30])) ? - rd_val___1__h15218 : - _theResult_____1_fst__h15230 ; - assign rd_val__h14086 = { _theResult____h4604[31:12], 12'h0 } ; - assign rd_val__h14105 = imem_rg_pc + rd_val__h14086 ; - assign rd_val__h17285 = rs1_val_bypassed__h4612 << shamt__h14020 ; - assign rd_val__h17337 = rs1_val_bypassed__h4612 >> shamt__h14020 ; - assign rd_val__h17359 = - rs1_val_bypassed__h4612 >> shamt__h14020 | - ~(32'hFFFFFFFF >> shamt__h14020) & - {32{rs1_val_bypassed__h4612[31]}} ; - assign rd_val__h17575 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d647) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs1 ; - assign rd_val__h17628 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d655) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs2 ; - assign rd_val__h17686 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3[75:71] == _theResult____h4604[31:27]) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs3 ; - assign rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7_EQ__ETC___d1148 = - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] || - rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) && - _theResult____h4604[31:20] == 12'b000100000101 ; - assign rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 = - rg_state == 4'd3 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1763 && - !stage3_rg_full && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd0 ; - assign rg_state_6_EQ_3_618_AND_stage3_rg_full_2_OR_NO_ETC___d1637 = - rg_state == 4'd3 && - (stage3_rg_full || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd0 || - stage1_rg_full) && - (stage3_rg_full || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd3) && - (stage3_rg_full || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd0 || - !stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1623) && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd0 || - stage3_rg_full) ; - assign rm__h14593 = x_out_data_to_stage2_rounding_mode__h13753 ; - assign rs1__h7631 = { 2'b01, instr__h4602[9:7] } ; - assign rs1_val__h14431 = - _theResult____h4604[14] ? - { 27'd0, _theResult____h4604[19:15] } : - rs1_val_bypassed__h4612 ; - assign rs1_val__h21562 = - (x_out_data_to_stage2_instr__h13745[14:12] == 3'b001) ? - x_out_data_to_stage2_val1__h13749[31:0] : - { 27'd0, x_out_data_to_stage2_instr__h13745[19:15] } ; - assign rs1_val_bypassed__h4612 = - (_theResult____h4604[19:15] == 5'd0) ? 32'd0 : val__h13633 ; - assign rs2_val__h13850 = - (_theResult____h4604[24:20] == 5'd0) ? 32'd0 : val__h13676 ; - assign shamt__h14020 = - (_theResult____h4604[6:0] == 7'b0010011) ? - _theResult____h4604[24:20] : - rs2_val__h13850[4:0] ; - assign stage2_f_reset_rsps_i_notEmpty__571_AND_stage3_ETC___d1580 = - stage2_f_reset_rsps$EMPTY_N && stage3_f_reset_rsps$EMPTY_N && - f_reset_rsps$FULL_N && - (!rg_run_on_reset || - !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) ; - assign stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d647 = - stage3_rg_stage3[75:71] == _theResult____h4604[19:15] ; - assign stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d655 = - stage3_rg_stage3[75:71] == _theResult____h4604[24:20] ; - assign theResult__604_BITS_31_TO_20__q18 = _theResult____h4604[31:20] ; - assign theResult__604_BITS_31_TO_25_CONCAT_theResult__ETC__q6 = - { _theResult____h4604[31:25], _theResult____h4604[11:7] } ; - assign theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q4 = - { _theResult____h4604[31], - _theResult____h4604[19:12], - _theResult____h4604[20], - _theResult____h4604[30:21], - 1'b0 } ; - assign theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q5 = - { _theResult____h4604[31], - _theResult____h4604[7], - _theResult____h4604[30:25], - _theResult____h4604[11:8], - 1'b0 } ; - assign trap_info_tval__h16726 = - (_theResult____h4604[6:0] != 7'b1101111 && - _theResult____h4604[6:0] != 7'b1100111 && - (_theResult____h4604[6:0] != 7'b1110011 || - _theResult____h4604[14:12] != 3'b0 || - _theResult____h4604[11:7] != 5'd0 || - _theResult____h4604[19:15] != 5'd0 || - _theResult____h4604[31:20] != 12'b0 && - _theResult____h4604[31:20] != 12'b000000000001)) ? - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d614 ? - _theResult____h4604 : - { 16'd0, instr__h4602[15:0] }) : - CASE_theResult__604_BITS_6_TO_0_0b1100111_data_ETC__q19 ; - assign val__h13633 = - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == - 2'd2 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602) ? - x_out_bypass_rd_val__h6718 : - rd_val__h13631 ; - assign val__h13676 = - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == - 2'd2 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604) ? - x_out_bypass_rd_val__h6718 : - rd_val__h13674 ; - assign value__h16781 = - near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h16726 ; - assign x__h26770 = - csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d1854[63:0] / - _theResult____h26769 ; - assign x_out_data_to_stage2_instr__h13745 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 ? - instr___1__h7017 : - instr__h4602 ; - assign x_out_data_to_stage2_rounding_mode__h13753 = - (_theResult____h4604[14:12] == 3'b111) ? - csr_regfile$read_frm : - _theResult____h4604[14:12] ; - assign x_out_data_to_stage2_val2__h13750 = - (_theResult____h4604[6:0] == 7'b1100011) ? - alu_outputs___1_val2__h13877 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1432 ; - assign x_out_data_to_stage2_val3__h13751 = - (IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6869 == _theResult____h4604[31:27]) ? - x_out_fbypass_rd_val__h6870 : - rd_val__h17686 ; - assign x_out_next_pc__h13711 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100 ? - data_to_stage2_addr__h13737 : - fall_through_pc__h13698 ; - assign x_out_trap_info_exc_code__h16729 = - near_mem$imem_exc ? - near_mem$imem_exc_code : - alu_outputs_exc_code__h14690 ; - assign y__h22359 = ~rs1_val__h22055 ; - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd2, 3'd4: value__h6422 = stage2_rg_stage2[299:268]; - default: value__h6422 = stage2_rg_stage2[299:268]; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_exc_code) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd2, 3'd4: - x_out_trap_info_exc_code__h6459 = near_mem$dmem_exc_code; - default: x_out_trap_info_exc_code__h6459 = 4'd2; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd2, 3'd4: value__h6483 = stage2_rg_stage2[227:196]; - default: value__h6483 = 32'd0; - endcase - end - always@(stage2_rg_stage2 or stage2_fbox$word_snd) - begin - case (stage2_rg_stage2[235:233]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - x_out_data_to_stage3_fpr_flags__h6242 = 5'd0; - default: x_out_data_to_stage3_fpr_flags__h6242 = stage2_fbox$word_snd; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[235:233]) - 3'd0, 3'd1, 3'd4: - x_out_data_to_stage3_rd__h6239 = stage2_rg_stage2[232:228]; - 3'd2: x_out_data_to_stage3_rd__h6239 = 5'd0; - default: x_out_data_to_stage3_rd__h6239 = stage2_rg_stage2[232:228]; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[235:233]) - 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h6717 = stage2_rg_stage2[232:228]; - default: x_out_bypass_rd__h6717 = stage2_rg_stage2[232:228]; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd4: x_out_fbypass_rd__h6869 = stage2_rg_stage2[232:228]; - default: x_out_fbypass_rd__h6869 = stage2_rg_stage2[232:228]; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$word_fst or - data_to_stage3_rd_val__h6137 or - output_stage2___1_data_to_stage3_rd_val__h6211) - begin - case (stage2_rg_stage2[235:233]) - 3'd0: x_out_data_to_stage3_rd_val__h6243 = stage2_rg_stage2[195:132]; - 3'd1, 3'd4: - x_out_data_to_stage3_rd_val__h6243 = data_to_stage3_rd_val__h6137; - 3'd3: - x_out_data_to_stage3_rd_val__h6243 = - output_stage2___1_data_to_stage3_rd_val__h6211; - default: x_out_data_to_stage3_rd_val__h6243 = stage2_fbox$word_fst; - endcase - end - always@(stage2_rg_stage2 or - _theResult___fst_rd_val__h6707 or - _theResult_____1_fst_rd_val__h6696 or stage2_mbox$word) - begin - case (stage2_rg_stage2[235:233]) - 3'd0: x_out_bypass_rd_val__h6718 = stage2_rg_stage2[163:132]; - 3'd1, 3'd4: - x_out_bypass_rd_val__h6718 = _theResult_____1_fst_rd_val__h6696; - 3'd3: x_out_bypass_rd_val__h6718 = stage2_mbox$word; - default: x_out_bypass_rd_val__h6718 = _theResult___fst_rd_val__h6707; - endcase - end - always@(stage2_rg_stage2 or - _theResult___snd_rd_val__h6861 or - _theResult_____1_snd_fst_rd_val__h6855) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd4: - x_out_fbypass_rd_val__h6870 = - _theResult_____1_snd_fst_rd_val__h6855; - default: x_out_fbypass_rd_val__h6870 = _theResult___snd_rd_val__h6861; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129 or - IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125 or - IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127) - begin - case (stage2_rg_stage2[235:233]) - 3'd0: CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1 = 2'd2; - 3'd1, 3'd2, 3'd4: - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1 = - IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125; - 3'd3: - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1 = - IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127; - default: CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1 = - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$valid or - near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150 = - !near_mem$dmem_valid || near_mem$dmem_exc; - 3'd3: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150 = - !stage2_mbox$valid; - default: IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150 = - !stage2_fbox$valid; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$valid or - near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160 = - near_mem$dmem_valid && !near_mem$dmem_exc; - 3'd3: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160 = - stage2_mbox$valid; - default: IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160 = - stage2_fbox$valid; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd4: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) && - stage2_rg_stage2[3]; - default: IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195 = - stage2_rg_stage2[235:233] != 3'd2 && - stage2_rg_stage2[235:233] != 3'd3 && - stage2_rg_stage2[3]; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd4: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d230 = - near_mem$dmem_valid && near_mem$dmem_exc || - !stage2_rg_stage2[3]; - default: IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d230 = - stage2_rg_stage2[235:233] == 3'd2 || - stage2_rg_stage2[235:233] == 3'd3 || - !stage2_rg_stage2[3]; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129 or - IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d256 or - IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127) - begin - case (stage2_rg_stage2[235:233]) - 3'd0: CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 = 2'd2; - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 = - IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d256; - 3'd2: CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 = 2'd0; - 3'd3: - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 = - IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127; - default: CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 = - stage2_rg_stage2[3] ? - 2'd0 : - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129 or - IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d284) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_235_TO_233_1_IF_NOT_ETC__q3 = - IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d284; - 3'd2, 3'd3: - CASE_stage2_rg_stage2_BITS_235_TO_233_1_IF_NOT_ETC__q3 = 2'd0; - default: CASE_stage2_rg_stage2_BITS_235_TO_233_1_IF_NOT_ETC__q3 = - stage2_rg_stage2[3] ? - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129 : - 2'd0; - endcase - end - always@(_theResult____h4604) - begin - case (_theResult____h4604[6:0]) - 7'b0000011, - 7'b0000111, - 7'b0010011, - 7'b0010111, - 7'b0110011, - 7'b0110111, - 7'b1100111, - 7'b1101111: - x_out_data_to_stage2_rd__h13747 = _theResult____h4604[11:7]; - 7'b1100011: x_out_data_to_stage2_rd__h13747 = 5'd0; - default: x_out_data_to_stage2_rd__h13747 = _theResult____h4604[11:7]; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663) - begin - case (_theResult____h4604[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - _theResult____h4604[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663) - begin - case (_theResult____h4604[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - _theResult____h4604[14:12] == 3'b111 && - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665; - endcase - end - always@(_theResult____h4604 or rm__h14593) - begin - case (_theResult____h4604[6:0]) - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111: - CASE_theResult__604_BITS_6_TO_0_0b1000011_NOT__ETC__q7 = - _theResult____h4604[26:25] != 2'b0 && - _theResult____h4604[26:25] != 2'b01; - default: CASE_theResult__604_BITS_6_TO_0_0b1000011_NOT__ETC__q7 = - _theResult____h4604[31:25] != 7'h0 && - _theResult____h4604[31:25] != 7'h04 && - _theResult____h4604[31:25] != 7'h08 && - _theResult____h4604[31:25] != 7'h0C && - _theResult____h4604[31:25] != 7'h2C && - (_theResult____h4604[31:25] != 7'h10 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h10 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h10 || - rm__h14593 != 3'd2) && - (_theResult____h4604[31:25] != 7'h60 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h60 || - _theResult____h4604[24:20] != 5'd1) && - (_theResult____h4604[31:25] != 7'h68 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h68 || - _theResult____h4604[24:20] != 5'd1) && - (_theResult____h4604[31:25] != 7'h14 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h14 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h50 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h50 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h50 || - rm__h14593 != 3'd2) && - (_theResult____h4604[31:25] != 7'h70 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h78 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h70 || - rm__h14593 != 3'd1) && - _theResult____h4604[31:25] != 7'b0000001 && - _theResult____h4604[31:25] != 7'h05 && - _theResult____h4604[31:25] != 7'b0001001 && - _theResult____h4604[31:25] != 7'h0D && - _theResult____h4604[31:25] != 7'h2D && - (_theResult____h4604[31:25] != 7'h11 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h11 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h11 || - rm__h14593 != 3'd2) && - (_theResult____h4604[31:25] != 7'h61 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h61 || - _theResult____h4604[24:20] != 5'd1) && - (_theResult____h4604[31:25] != 7'h69 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h69 || - _theResult____h4604[24:20] != 5'd1) && - (_theResult____h4604[31:25] != 7'h21 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h20 || - _theResult____h4604[24:20] != 5'd1) && - (_theResult____h4604[31:25] != 7'h15 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h15 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h51 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h51 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h51 || - rm__h14593 != 3'd2) && - (_theResult____h4604[31:25] != 7'h71 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h79 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h71 || - rm__h14593 != 3'd1); - endcase - end - always@(_theResult____h4604 or - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d926 or - csr_regfile$read_mstatus) - begin - case (_theResult____h4604[6:0]) - 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930 = - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b010 && - _theResult____h4604[14:12] != 3'b011 || - csr_regfile$read_mstatus[14:13] == 2'h0; - 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930 = - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b010 && - _theResult____h4604[14:12] != 3'b011 || - csr_regfile$read_mstatus[14:13] == 2'h0; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930 = - _theResult____h4604[31:27] != 5'b00010 && - _theResult____h4604[31:27] != 5'b00011 && - _theResult____h4604[31:27] != 5'b0 && - _theResult____h4604[31:27] != 5'b00001 && - _theResult____h4604[31:27] != 5'b01100 && - _theResult____h4604[31:27] != 5'b01000 && - _theResult____h4604[31:27] != 5'b00100 && - _theResult____h4604[31:27] != 5'b10000 && - _theResult____h4604[31:27] != 5'b11000 && - _theResult____h4604[31:27] != 5'b10100 && - _theResult____h4604[31:27] != 5'b11100 || - _theResult____h4604[14:12] != 3'b010; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930 = - _theResult____h4604[6:0] != 7'b1010011 && - _theResult____h4604[6:0] != 7'b1000011 && - _theResult____h4604[6:0] != 7'b1000111 && - _theResult____h4604[6:0] != 7'b1001011 && - _theResult____h4604[6:0] != 7'b1001111 || - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d926; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930) - begin - case (_theResult____h4604[6:0]) - 7'b0000011: - CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b010 && - _theResult____h4604[14:12] != 3'b011; - 7'b0100011: - CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b010 && - _theResult____h4604[14:12] != 3'b011; - default: CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4604[6:0] == 7'b0001111 || - _theResult____h4604[6:0] == 7'b1110011 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930; - endcase - end - always@(_theResult____h4604 or - CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 or - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d702) - begin - case (_theResult____h4604[6:0]) - 7'b0010011, 7'b0110011: - CASE_theResult__604_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d702; - default: CASE_theResult__604_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = - _theResult____h4604[6:0] != 7'b0110111 && - _theResult____h4604[6:0] != 7'b0010111 && - CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8; - endcase - end - always@(_theResult____h4604 or rm__h14593) - begin - case (_theResult____h4604[6:0]) - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111: - CASE_theResult__604_BITS_6_TO_0_0b1000011_theR_ETC__q10 = - _theResult____h4604[26:25] == 2'b0 || - _theResult____h4604[26:25] == 2'b01; - default: CASE_theResult__604_BITS_6_TO_0_0b1000011_theR_ETC__q10 = - _theResult____h4604[31:25] == 7'h0 || - _theResult____h4604[31:25] == 7'h04 || - _theResult____h4604[31:25] == 7'h08 || - _theResult____h4604[31:25] == 7'h0C || - _theResult____h4604[31:25] == 7'h2C || - _theResult____h4604[31:25] == 7'h10 && - (rm__h14593 == 3'd0 || rm__h14593 == 3'd1 || - rm__h14593 == 3'd2) || - _theResult____h4604[31:25] == 7'h60 && - _theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[31:25] == 7'h60 && - _theResult____h4604[24:20] == 5'd1 || - _theResult____h4604[31:25] == 7'h68 && - (_theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[24:20] == 5'd1) || - _theResult____h4604[31:25] == 7'h14 && - (rm__h14593 == 3'd0 || rm__h14593 == 3'd1) || - _theResult____h4604[31:25] == 7'h50 && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h50 && - (rm__h14593 == 3'd1 || rm__h14593 == 3'd2) || - _theResult____h4604[31:25] == 7'h70 && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h78 && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h70 && - rm__h14593 == 3'd1 || - _theResult____h4604[31:25] == 7'b0000001 || - _theResult____h4604[31:25] == 7'h05 || - _theResult____h4604[31:25] == 7'b0001001 || - _theResult____h4604[31:25] == 7'h0D || - _theResult____h4604[31:25] == 7'h2D || - _theResult____h4604[31:25] == 7'h11 && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h11 && - (rm__h14593 == 3'd1 || rm__h14593 == 3'd2) || - _theResult____h4604[31:25] == 7'h61 && - _theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[31:25] == 7'h61 && - _theResult____h4604[24:20] == 5'd1 || - _theResult____h4604[31:25] == 7'h69 && - (_theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[24:20] == 5'd1) || - _theResult____h4604[31:25] == 7'h21 && - _theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[31:25] == 7'h20 && - _theResult____h4604[24:20] == 5'd1 || - _theResult____h4604[31:25] == 7'h15 && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h15 && - rm__h14593 == 3'd1 || - _theResult____h4604[31:25] == 7'h51 && - (rm__h14593 == 3'd0 || rm__h14593 == 3'd1) || - _theResult____h4604[31:25] == 7'h51 && - rm__h14593 == 3'd2 || - (_theResult____h4604[31:25] == 7'h71 || - _theResult____h4604[31:25] == 7'h79) && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h71 && rm__h14593 == 3'd1; - endcase - end - always@(_theResult____h4604 or - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1084 or - csr_regfile$read_mstatus) - begin - case (_theResult____h4604[6:0]) - 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088 = - (_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011) && - csr_regfile$read_mstatus[14:13] != 2'h0; - 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088 = - (_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011) && - csr_regfile$read_mstatus[14:13] != 2'h0; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088 = - (_theResult____h4604[31:27] == 5'b00010 || - _theResult____h4604[31:27] == 5'b00011 || - _theResult____h4604[31:27] == 5'b0 || - _theResult____h4604[31:27] == 5'b00001 || - _theResult____h4604[31:27] == 5'b01100 || - _theResult____h4604[31:27] == 5'b01000 || - _theResult____h4604[31:27] == 5'b00100 || - _theResult____h4604[31:27] == 5'b10000 || - _theResult____h4604[31:27] == 5'b11000 || - _theResult____h4604[31:27] == 5'b10100 || - _theResult____h4604[31:27] == 5'b11100) && - _theResult____h4604[14:12] == 3'b010; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088 = - (_theResult____h4604[6:0] == 7'b1010011 || - _theResult____h4604[6:0] == 7'b1000011 || - _theResult____h4604[6:0] == 7'b1000111 || - _theResult____h4604[6:0] == 7'b1001011 || - _theResult____h4604[6:0] == 7'b1001111) && - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1084; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088) - begin - case (_theResult____h4604[6:0]) - 7'b0000011: - CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11 = - _theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011; - 7'b0100011: - CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11 = - _theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011; - default: CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11 = - _theResult____h4604[6:0] != 7'b0001111 && - _theResult____h4604[6:0] != 7'b1110011 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088; - endcase - end - always@(_theResult____h4604 or - CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d971) - begin - case (_theResult____h4604[6:0]) - 7'b0010011, 7'b0110011: - CASE_theResult__604_BITS_6_TO_0_0b10011_IF_NOT_ETC__q12 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d971; - default: CASE_theResult__604_BITS_6_TO_0_0b10011_IF_NOT_ETC__q12 = - _theResult____h4604[6:0] == 7'b0110111 || - _theResult____h4604[6:0] == 7'b0010111 || - CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11; - endcase - end - always@(rg_cur_priv) - begin - case (rg_cur_priv) - 2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q13 = 4'd8; - 2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q13 = 4'd9; - default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q13 = 4'd11; - endcase - end - always@(_theResult____h4604 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q13) - begin - case (_theResult____h4604[31:20]) - 12'b0: - CASE_theResult__604_BITS_31_TO_20_0b0_CASE_rg__ETC__q14 = - CASE_rg_cur_priv_0b0_8_0b1_9_11__q13; - 12'b000000000001: - CASE_theResult__604_BITS_31_TO_20_0b0_CASE_rg__ETC__q14 = 4'd3; - default: CASE_theResult__604_BITS_31_TO_20_0b0_CASE_rg__ETC__q14 = 4'd2; - endcase - end - always@(_theResult____h4604 or alu_outputs___1_exc_code__h14461) - begin - case (_theResult____h4604[6:0]) - 7'b0000011, - 7'b0001111, - 7'b0010011, - 7'b0010111, - 7'b0100011, - 7'b0110011, - 7'b0110111, - 7'b1100011: - alu_outputs_exc_code__h14690 = 4'd2; - 7'b1100111, 7'b1101111: alu_outputs_exc_code__h14690 = 4'd0; - 7'b1110011: - alu_outputs_exc_code__h14690 = alu_outputs___1_exc_code__h14461; - default: alu_outputs_exc_code__h14690 = 4'd2; - endcase - end - always@(_theResult____h4604 or - rg_cur_priv or - IF_rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7__ETC___d1150) - begin - case (_theResult____h4604[31:20]) - 12'b0, 12'b000000000001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1152 = 4'd11; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1152 = - (rg_cur_priv == 2'b11 && - _theResult____h4604[31:20] == 12'b001100000010) ? - 4'd7 : - IF_rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7__ETC___d1150; - endcase - end - always@(_theResult____h4604) - begin - case (_theResult____h4604[14:12]) - 3'b0: CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd4; - 3'b001: CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd5; - default: CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd11; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1154) - begin - case (_theResult____h4604[14:12]) - 3'b0: - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1154; - 3'b001, 3'b101: - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16 = 4'd2; - 3'b010, 3'b011, 3'b110, 3'b111: - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16 = 4'd3; - 3'd4: CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16 = 4'd11; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1112 or - CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15 or - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1108 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1116 or - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1162 or - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16) - begin - case (_theResult____h4604[6:0]) - 7'b0000011, 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1112; - 7'b0001111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15; - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1108; - 7'b0010111, 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = 4'd0; - 7'b0100011, 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1116; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - ((_theResult____h4604[31:27] == 5'b00010 || - _theResult____h4604[31:27] == 5'b00011 || - _theResult____h4604[31:27] == 5'b0 || - _theResult____h4604[31:27] == 5'b00001 || - _theResult____h4604[31:27] == 5'b01100 || - _theResult____h4604[31:27] == 5'b01000 || - _theResult____h4604[31:27] == 5'b00100 || - _theResult____h4604[31:27] == 5'b10000 || - _theResult____h4604[31:27] == 5'b11000 || - _theResult____h4604[31:27] == 5'b10100 || - _theResult____h4604[31:27] == 5'b11100) && - _theResult____h4604[14:12] == 3'b010) ? - 4'd0 : - 4'd11; - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111, 7'b1010011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1162; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - 4'd11; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672) - begin - case (_theResult____h4604[6:0]) - 7'b1100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1176 = - (_theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b110 && - _theResult____h4604[14:12] != 3'b111) ? - 4'd11 : - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 ? - 4'd1 : - 4'd0); - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1176 = 4'd1; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1176 = - (_theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[31:25] == 7'b0000001) ? - 4'd0 : - (((_theResult____h4604[6:0] == 7'b0010011 || - _theResult____h4604[6:0] == 7'b0110011) && - (_theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101)) ? - (_theResult____h4604[25] ? 4'd11 : 4'd0) : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172); - endcase - end - always@(_theResult____h4604) - begin - case (_theResult____h4604[6:0]) - 7'b0000011, 7'b0000111: - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17 = 3'd1; - 7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111: - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17 = 3'd0; - 7'b0100011, 7'b0100111: - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17 = 3'd2; - 7'b0101111: - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17 = 3'd4; - default: CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17 = 3'd5; - endcase - end - always@(_theResult____h4604 or - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17) - begin - case (_theResult____h4604[6:0]) - 7'b1100011, 7'b1100111, 7'b1101111: - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 = 3'd0; - default: IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 = - (_theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[31:25] == 7'b0000001) ? - 3'd3 : - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17; - endcase - end - always@(_theResult____h4604 or - _theResult_____1_fst__h15265 or - rd_val___1__h15233 or - rd_val___1__h15240 or rd_val___1__h15247 or rd_val___1__h15254) - begin - case (_theResult____h4604[14:12]) - 3'b010: _theResult_____1_fst__h15237 = rd_val___1__h15233; - 3'b011: _theResult_____1_fst__h15237 = rd_val___1__h15240; - 3'b100: _theResult_____1_fst__h15237 = rd_val___1__h15247; - 3'b110: _theResult_____1_fst__h15237 = rd_val___1__h15254; - default: _theResult_____1_fst__h15237 = _theResult_____1_fst__h15265; - endcase - end - always@(_theResult____h4604 or - alu_outputs___1_addr__h14178 or - alu_outputs___1_addr__h14154 or - rs1_val_bypassed__h4612 or - alu_outputs___1_addr__h13875 or - alu_outputs___1_addr__h13928 or alu_outputs___1_addr__h13899) - begin - case (_theResult____h4604[6:0]) - 7'b0000011, 7'b0000111: - x_out_data_to_stage2_addr__h13748 = alu_outputs___1_addr__h14154; - 7'b0100011: - x_out_data_to_stage2_addr__h13748 = alu_outputs___1_addr__h14178; - 7'b0101111: x_out_data_to_stage2_addr__h13748 = rs1_val_bypassed__h4612; - 7'b1100011: - x_out_data_to_stage2_addr__h13748 = alu_outputs___1_addr__h13875; - 7'b1100111: - x_out_data_to_stage2_addr__h13748 = alu_outputs___1_addr__h13928; - 7'b1101111: - x_out_data_to_stage2_addr__h13748 = alu_outputs___1_addr__h13899; - default: x_out_data_to_stage2_addr__h13748 = - alu_outputs___1_addr__h14178; - endcase - end - always@(_theResult____h4604 or imem_rg_pc or data_to_stage2_addr__h13737) - begin - case (_theResult____h4604[6:0]) - 7'b1100111, 7'b1101111: - CASE_theResult__604_BITS_6_TO_0_0b1100111_data_ETC__q19 = - data_to_stage2_addr__h13737; - default: CASE_theResult__604_BITS_6_TO_0_0b1100111_data_ETC__q19 = - (_theResult____h4604[6:0] == 7'b1110011 && - _theResult____h4604[14:12] == 3'b0 && - _theResult____h4604[11:7] == 5'd0 && - _theResult____h4604[19:15] == 5'd0 && - _theResult____h4604[31:20] == 12'b000000000001) ? - imem_rg_pc : - 32'd0; - endcase - end - always@(_theResult____h4604 or - alu_outputs___1_val1__h14666 or - alu_outputs___1_val1__h14076 or - alu_outputs___1_val1__h14114 or - alu_outputs___1_val1__h14489 or - alu_outputs___1_val1__h14095 or alu_outputs___1_val1__h14465) - begin - case (_theResult____h4604[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14076; - 7'b0010111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14114; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14489; - 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14095; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14465; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14666; - endcase - end - always@(_theResult____h4604 or - alu_outputs___1_val1__h15021 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1412 or - alu_outputs___1_val1__h13900) - begin - case (_theResult____h4604[6:0]) - 7'b1100111, 7'b1101111: - x_out_data_to_stage2_val1__h13749 = alu_outputs___1_val1__h13900; - default: x_out_data_to_stage2_val1__h13749 = - (_theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[31:25] == 7'b0000001) ? - alu_outputs___1_val1__h15021 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1412; - endcase - end - always@(x_out_data_to_stage2_instr__h13745 or - x_out_data_to_stage2_val1__h13749) - begin - case (x_out_data_to_stage2_instr__h13745[14:12]) - 3'b010, 3'b011: - rs1_val__h22055 = x_out_data_to_stage2_val1__h13749[31:0]; - default: rs1_val__h22055 = - { 27'd0, x_out_data_to_stage2_instr__h13745[19:15] }; - endcase - end - always@(_theResult____h4604 or - frs2_val_bypassed__h4628 or - alu_outputs___1_val2__h14180 or alu_outputs___1_val2__h15022) - begin - case (_theResult____h4604[6:0]) - 7'b0100011, 7'b0100111: - CASE_theResult__604_BITS_6_TO_0_0b100011_alu_o_ETC__q20 = - alu_outputs___1_val2__h14180; - 7'b0101111: - CASE_theResult__604_BITS_6_TO_0_0b100011_alu_o_ETC__q20 = - alu_outputs___1_val2__h15022; - default: CASE_theResult__604_BITS_6_TO_0_0b100011_alu_o_ETC__q20 = - frs2_val_bypassed__h4628; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0; - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11; - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_logdelay$EN) - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN; - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_cur_priv$EN) - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN; - if (rg_run_on_reset$EN) - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (stage1_rg_full$EN) - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN; - if (stage2_rg_full$EN) - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN; - if (stage2_rg_resetting$EN) - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY - stage2_rg_resetting$D_IN; - if (stage3_rg_full$EN) - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN; - end - if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN; - if (imem_rg_instr_15_0$EN) - imem_rg_instr_15_0 <= `BSV_ASSIGNMENT_DELAY imem_rg_instr_15_0$D_IN; - if (imem_rg_mstatus_MXR$EN) - imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN; - if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN; - if (imem_rg_priv$EN) - imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN; - if (imem_rg_satp$EN) - imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN; - if (imem_rg_sstatus_SUM$EN) - imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN; - if (imem_rg_tval$EN) - imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_start_CPI_cycles$EN) - rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN; - if (rg_start_CPI_instrs$EN) - rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN; - if (stage2_rg_stage2$EN) - stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN; - if (stage3_rg_stage3$EN) - stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_logdelay = 64'hAAAAAAAAAAAAAAAA; - cfg_verbosity = 4'hA; - imem_rg_f3 = 3'h2; - imem_rg_instr_15_0 = 16'hAAAA; - imem_rg_mstatus_MXR = 1'h0; - imem_rg_pc = 32'hAAAAAAAA; - imem_rg_priv = 2'h2; - imem_rg_satp = 32'hAAAAAAAA; - imem_rg_sstatus_SUM = 1'h0; - imem_rg_tval = 32'hAAAAAAAA; - rg_cur_priv = 2'h2; - rg_mstatus_MXR = 1'h0; - rg_next_pc = 32'hAAAAAAAA; - rg_run_on_reset = 1'h0; - rg_sstatus_SUM = 1'h0; - rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA; - rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - stage1_rg_full = 1'h0; - stage2_rg_full = 1'h0; - stage2_rg_resetting = 1'h0; - stage2_rg_stage2 = - 302'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - stage3_rg_full = 1'h0; - stage3_rg_stage3 = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - rg_cur_priv, - csr_regfile$read_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write("MStatus{", - "sd:%0d", - csr_regfile$read_mstatus[14:13] == 2'h3 || - csr_regfile$read_mstatus[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2) - $write(" sxl:%0d uxl:%0d", 2'd0, 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tsr:%0d", csr_regfile$read_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tw:%0d", csr_regfile$read_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tvm:%0d", csr_regfile$read_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mxr:%0d", csr_regfile$read_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" sum:%0d", csr_regfile$read_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mprv:%0d", csr_regfile$read_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" xs:%0d", csr_regfile$read_mstatus[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" fs:%0d", csr_regfile$read_mstatus[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mpp:%0d", csr_regfile$read_mstatus[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" spp:%0d", csr_regfile$read_mstatus[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" pies:%0d_%0d%0d", - csr_regfile$read_mstatus[7], - csr_regfile$read_mstatus[5], - csr_regfile$read_mstatus[4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" ies:%0d_%0d%0d", - csr_regfile$read_mstatus[3], - csr_regfile$read_mstatus[1], - csr_regfile$read_mstatus[0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("Rd %0d ", stage3_rg_stage3[75:71]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("rd_val:%h", stage3_rg_stage3[31:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write("FRd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("FRd %0d ", stage3_rg_stage3[75:71]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("frd_val:%h", stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage2: pc 0x%08h instr 0x%08h priv %0d", - stage2_rg_stage2[299:268], - stage2_rg_stage2[267:236], - stage2_rg_stage2[301:300]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write("Output_Stage2", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[299:268]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("Output_Stage2", " NONPIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write("Output_Stage2", " PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[299:268], - stage2_rg_stage2[267:236], - stage2_rg_stage2[301:300]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - stage2_rg_stage2[235:233] != 3'd0 && - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - (stage2_rg_stage2[235:233] == 3'd0 || - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - stage2_rg_stage2[235:233] != 3'd0 && - stage2_rg_stage2[235:233] != 3'd1 && - stage2_rg_stage2[235:233] != 3'd4 && - stage2_rg_stage2[235:233] != 3'd2 && - stage2_rg_stage2[235:233] != 3'd3) - $write(" fflags: %05b", - "'h%h", - x_out_data_to_stage3_fpr_flags__h6242); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - (stage2_rg_stage2[235:233] == 3'd0 || - stage2_rg_stage2[235:233] == 3'd1 || - stage2_rg_stage2[235:233] == 3'd4 || - stage2_rg_stage2[235:233] == 3'd2 || - stage2_rg_stage2[235:233] == 3'd3)) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - stage2_rg_stage2[235:233] != 3'd0 && - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195) - $write(" frd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6239, - x_out_data_to_stage3_rd_val__h6243); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - (stage2_rg_stage2[235:233] == 3'd0 || - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d230)) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6239, - x_out_data_to_stage3_rd_val__h6243); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", value__h6422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", x_out_trap_info_exc_code__h6459); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", value__h6483, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", value__h6422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", x_out_trap_info_exc_code__h6459); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", value__h6483, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == 2'd0) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 != 2'd0) - $write("Rd %0d ", x_out_bypass_rd__h6717); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 != 2'd1) - $write("rd_val:%h", x_out_bypass_rd_val__h6718); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == 2'd0) - $write("FRd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 != 2'd0) - $write("FRd %0d ", x_out_fbypass_rd__h6869); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 != 2'd0 && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 != 2'd1) - $write("frd_val:%h", x_out_fbypass_rd_val__h6870); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage1: pc 0x%08h instr 0x%08h priv %0d", - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write("Output_Stage1", " BUSY pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write("Output_Stage1", " NONPIPE: pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write("Output_Stage1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) - $write("Output_Stage1", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(" PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd0) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd1) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd2) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd3) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd4) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd5) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd6) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd7) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd8) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd9) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd10) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1244) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n", - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(" op_stage2:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == 3'd0) - $write("OP_Stage2_ALU"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == 3'd1) - $write("OP_Stage2_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == 3'd2) - $write("OP_Stage2_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == 3'd3) - $write("OP_Stage2_M"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == 3'd4) - $write("OP_Stage2_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1290) - $write("OP_Stage2_FD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(" rd:%0d\n", x_out_data_to_stage2_rd__h13747); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(" addr:%h val1:%h val2:%h val3:%h}", - x_out_data_to_stage2_addr__h13748, - x_out_data_to_stage2_val1__h13749, - x_out_data_to_stage2_val2__h13750, - x_out_data_to_stage2_val3__h13751); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1457) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1460) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1463) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1466) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1469) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1472) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1475) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1478) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1481) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1484) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1487) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1490) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write("'h%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write("'h%h", x_out_trap_info_exc_code__h16729); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write("'h%h", value__h16781, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622) - $write(" next_pc 0x%08h", x_out_next_pc__h13711); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - value__h6422, - stage2_rg_stage2[267:236], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3131 != 4'd0) - $display(" mcause:0x%0h epc 0x%0h tval:0x%0h new pc 0x%0h, new mstatus 0x%0h", - csr_regfile$csr_trap_actions[33:2], - value__h6422, - value__h6483, - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[65:34]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h13745[19:15], - rs1_val__h21562, - x_out_data_to_stage2_instr__h13745[31:20], - csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h13745[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h13745[19:15], - rs1_val__h21562, - x_out_data_to_stage2_instr__h13745[31:20], - x_out_data_to_stage2_instr__h13745[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_CSRR_S_or_C", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h13745[19:15], - rs1_val__h22055, - x_out_data_to_stage2_instr__h13745[31:20], - csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h13745[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h13745[19:15], - rs1_val__h22055, - x_out_data_to_stage2_instr__h13745[31:20], - x_out_data_to_stage2_instr__h13745[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h13711); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d pc:%0x cur_priv:%0d", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - x_out_next_pc__h13711, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3131 != 4'd0) - $display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d", - csr_regfile$csr_ret_actions[65:34], - csr_regfile$csr_ret_actions[31:0], - csr_regfile$csr_ret_actions[33:32]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_stage1_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h3131 != 4'd0) - $display(" WFI resume"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_from_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1851) - $display("%0d: CPU.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x", - csr_regfile$read_csr_mcycle, - csr_regfile$csr_trap_actions[97:66], - x_out_data_to_stage2_instr__h13745); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1851) - $display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'", - cpi__h26771, - cpifrac__h26772, - delta_CPI_cycles__h26767, - _theResult____h26769); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1851) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3131 != 4'd0) - $display("%0d: CPU.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", - csr_regfile$read_csr_mcycle, - rg_cur_priv, - csr_regfile$csr_trap_actions[33:2], - imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3131 != 4'd0) - $display(" tval:0x%0h new pc:0x%0h new mstatus:0x%0h", - value__h16781, - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[65:34]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_trap_fetch && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3131 != 4'd0) - $display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", - csr_regfile$read_csr_mcycle, - imem_rg_pc, - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[1:0], - csr_regfile$csr_trap_actions[65:34]); - if (WILL_FIRE_RL_imem_rl_assert_fail) - $display("ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False"); - if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", - soc_map$m_pc_reset_value[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h", - csr_regfile$read_csr_mcycle, - soc_map$m_pc_reset_value[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage3_rg_stage3[69]) - $display(" S3.fa_deq: write FRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[75:71], - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - !stage3_rg_stage3[69]) - $display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[75:71], - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write(" S3.enq: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[299:268], - stage2_rg_stage2[267:236], - stage2_rg_stage2[301:300]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[235:233] != 3'd0 && - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[235:233] == 3'd0 || - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[235:233] != 3'd0 && - stage2_rg_stage2[235:233] != 3'd1 && - stage2_rg_stage2[235:233] != 3'd4 && - stage2_rg_stage2[235:233] != 3'd2 && - stage2_rg_stage2[235:233] != 3'd3) - $write(" fflags: %05b", - "'h%h", - x_out_data_to_stage3_fpr_flags__h6242); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[235:233] == 3'd0 || - stage2_rg_stage2[235:233] == 3'd1 || - stage2_rg_stage2[235:233] == 3'd4 || - stage2_rg_stage2[235:233] == 3'd2 || - stage2_rg_stage2[235:233] == 3'd3)) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[235:233] != 3'd0 && - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195) - $write(" frd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6239, - x_out_data_to_stage3_rd_val__h6243); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[235:233] == 3'd0 || - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d230)) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6239, - x_out_data_to_stage3_rd_val__h6243); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[299:268], - stage2_rg_stage2[267:236], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage2.enq (Data_Stage1_to_Stage2)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h13711); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $write("CPU: Bluespec RISC-V Piccolo v3.0"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) $display(" (RV32)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h3131 != 4'd0) - $display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle); - end - // synopsys translate_on -endmodule // mkCPU - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v deleted file mode 100644 index a9f5381f..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v +++ /dev/null @@ -1,228 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 32 -// fav_write O 32 -// fv_sie_read O 32 -// fav_sie_write O 32 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 32 -// fav_sie_write_misa I 28 -// fav_sie_write_wordxl I 32 -// EN_reset I 1 -// EN_fav_write I 1 -// EN_fav_sie_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// (fav_sie_write_misa, fav_sie_write_wordxl) -> fav_sie_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIE(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - fv_sie_read, - - fav_sie_write_misa, - fav_sie_write_wordxl, - EN_fav_sie_write, - fav_sie_write); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [31 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [31 : 0] fav_write_wordxl; - input EN_fav_write; - output [31 : 0] fav_write; - - // value method fv_sie_read - output [31 : 0] fv_sie_read; - - // actionvalue method fav_sie_write - input [27 : 0] fav_sie_write_misa; - input [31 : 0] fav_sie_write_wordxl; - input EN_fav_sie_write; - output [31 : 0] fav_sie_write; - - // signals for module outputs - wire [31 : 0] fav_sie_write, fav_write, fv_read, fv_sie_read; - - // register rg_mie - reg [11 : 0] rg_mie; - reg [11 : 0] rg_mie$D_IN; - wire rg_mie$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_sie_write, - CAN_FIRE_fav_write, - CAN_FIRE_reset, - WILL_FIRE_fav_sie_write, - WILL_FIRE_fav_write, - WILL_FIRE_reset; - - // inputs to muxes for submodule ports - wire [11 : 0] MUX_rg_mie$write_1__VAL_3; - - // remaining internal signals - wire [11 : 0] mie__h92, x__h458, x__h883; - wire seie__h123, - seie__h544, - ssie__h117, - ssie__h538, - stie__h120, - stie__h541, - ueie__h122, - ueie__h543, - usie__h116, - usie__h537, - utie__h119, - utie__h540; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 20'd0, rg_mie } ; - - // actionvalue method fav_write - assign fav_write = { 20'd0, mie__h92 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // value method fv_sie_read - assign fv_sie_read = { 20'd0, x__h458 } ; - - // actionvalue method fav_sie_write - assign fav_sie_write = { 20'd0, x__h883 } ; - assign CAN_FIRE_fav_sie_write = 1'd1 ; - assign WILL_FIRE_fav_sie_write = EN_fav_sie_write ; - - // inputs to muxes for submodule ports - assign MUX_rg_mie$write_1__VAL_3 = - { rg_mie[11], - 1'b0, - seie__h544, - ueie__h543, - rg_mie[7], - 1'b0, - stie__h541, - utie__h540, - rg_mie[3], - 1'b0, - ssie__h538, - usie__h537 } ; - - // register rg_mie - always@(EN_fav_write or - mie__h92 or - EN_reset or EN_fav_sie_write or MUX_rg_mie$write_1__VAL_3) - case (1'b1) - EN_fav_write: rg_mie$D_IN = mie__h92; - EN_reset: rg_mie$D_IN = 12'd0; - EN_fav_sie_write: rg_mie$D_IN = MUX_rg_mie$write_1__VAL_3; - default: rg_mie$D_IN = 12'b101010101010 /* unspecified value */ ; - endcase - assign rg_mie$EN = EN_fav_write || EN_fav_sie_write || EN_reset ; - - // remaining internal signals - assign mie__h92 = - { fav_write_wordxl[11], - 1'b0, - seie__h123, - ueie__h122, - fav_write_wordxl[7], - 1'b0, - stie__h120, - utie__h119, - fav_write_wordxl[3], - 1'b0, - ssie__h117, - usie__h116 } ; - assign seie__h123 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign seie__h544 = fav_sie_write_misa[18] && fav_sie_write_wordxl[9] ; - assign ssie__h117 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign ssie__h538 = fav_sie_write_misa[18] && fav_sie_write_wordxl[1] ; - assign stie__h120 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign stie__h541 = fav_sie_write_misa[18] && fav_sie_write_wordxl[5] ; - assign ueie__h122 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign ueie__h543 = fav_sie_write_misa[13] && fav_sie_write_wordxl[8] ; - assign usie__h116 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign usie__h537 = fav_sie_write_misa[13] && fav_sie_write_wordxl[0] ; - assign utie__h119 = fav_write_misa[13] && fav_write_wordxl[4] ; - assign utie__h540 = fav_sie_write_misa[13] && fav_sie_write_wordxl[4] ; - assign x__h458 = - { 2'd0, rg_mie[9:8], 2'd0, rg_mie[5:4], 2'd0, rg_mie[1:0] } ; - assign x__h883 = - { 2'd0, - seie__h544, - ueie__h543, - 2'd0, - stie__h541, - utie__h540, - 2'd0, - ssie__h538, - usie__h537 } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_mie = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIE - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v deleted file mode 100644 index a3222f14..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v +++ /dev/null @@ -1,374 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 32 -// fav_write O 32 -// fv_sip_read O 32 -// fav_sip_write O 32 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 32 -// fav_sip_write_misa I 28 -// fav_sip_write_wordxl I 32 -// m_external_interrupt_req_req I 1 reg -// s_external_interrupt_req_req I 1 reg -// software_interrupt_req_req I 1 reg -// timer_interrupt_req_req I 1 reg -// EN_reset I 1 -// EN_fav_write I 1 -// EN_fav_sip_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// (fav_sip_write_misa, fav_sip_write_wordxl) -> fav_sip_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIP(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - fv_sip_read, - - fav_sip_write_misa, - fav_sip_write_wordxl, - EN_fav_sip_write, - fav_sip_write, - - m_external_interrupt_req_req, - - s_external_interrupt_req_req, - - software_interrupt_req_req, - - timer_interrupt_req_req); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [31 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [31 : 0] fav_write_wordxl; - input EN_fav_write; - output [31 : 0] fav_write; - - // value method fv_sip_read - output [31 : 0] fv_sip_read; - - // actionvalue method fav_sip_write - input [27 : 0] fav_sip_write_misa; - input [31 : 0] fav_sip_write_wordxl; - input EN_fav_sip_write; - output [31 : 0] fav_sip_write; - - // action method m_external_interrupt_req - input m_external_interrupt_req_req; - - // action method s_external_interrupt_req - input s_external_interrupt_req_req; - - // action method software_interrupt_req - input software_interrupt_req_req; - - // action method timer_interrupt_req - input timer_interrupt_req_req; - - // signals for module outputs - wire [31 : 0] fav_sip_write, fav_write, fv_read, fv_sip_read; - - // register rg_meip - reg rg_meip; - wire rg_meip$D_IN, rg_meip$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_seip - reg rg_seip; - wire rg_seip$D_IN, rg_seip$EN; - - // register rg_ssip - reg rg_ssip; - reg rg_ssip$D_IN; - wire rg_ssip$EN; - - // register rg_stip - reg rg_stip; - wire rg_stip$D_IN, rg_stip$EN; - - // register rg_ueip - reg rg_ueip; - reg rg_ueip$D_IN; - wire rg_ueip$EN; - - // register rg_usip - reg rg_usip; - reg rg_usip$D_IN; - wire rg_usip$EN; - - // register rg_utip - reg rg_utip; - wire rg_utip$D_IN, rg_utip$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_sip_write, - CAN_FIRE_fav_write, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_reset, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_fav_sip_write, - WILL_FIRE_fav_write, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_reset, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // remaining internal signals - wire [11 : 0] new_mip__h528, new_mip__h946; - wire seip__h562, - ssip__h566, - ssip__h986, - stip__h564, - ueip__h563, - ueip__h985, - usip__h567, - usip__h987, - utip__h565; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 20'd0, new_mip__h528 } ; - - // actionvalue method fav_write - assign fav_write = { 20'd0, new_mip__h946 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // value method fv_sip_read - assign fv_sip_read = - { 22'd0, - rg_seip, - rg_ueip, - 2'b0, - rg_stip, - rg_utip, - 2'b0, - rg_ssip, - rg_usip } ; - - // actionvalue method fav_sip_write - assign fav_sip_write = - { 22'd0, - rg_seip, - ueip__h985, - 2'b0, - rg_stip, - rg_utip, - 2'b0, - ssip__h986, - usip__h987 } ; - assign CAN_FIRE_fav_sip_write = 1'd1 ; - assign WILL_FIRE_fav_sip_write = EN_fav_sip_write ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // register rg_meip - assign rg_meip$D_IN = m_external_interrupt_req_req ; - assign rg_meip$EN = 1'b1 ; - - // register rg_msip - assign rg_msip$D_IN = software_interrupt_req_req ; - assign rg_msip$EN = 1'b1 ; - - // register rg_mtip - assign rg_mtip$D_IN = timer_interrupt_req_req ; - assign rg_mtip$EN = 1'b1 ; - - // register rg_seip - assign rg_seip$D_IN = s_external_interrupt_req_req ; - assign rg_seip$EN = 1'b1 ; - - // register rg_ssip - always@(EN_reset or - EN_fav_write or ssip__h566 or EN_fav_sip_write or ssip__h986) - case (1'b1) - EN_reset: rg_ssip$D_IN = 1'd0; - EN_fav_write: rg_ssip$D_IN = ssip__h566; - EN_fav_sip_write: rg_ssip$D_IN = ssip__h986; - default: rg_ssip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_ssip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_stip - assign rg_stip$D_IN = !EN_reset && stip__h564 ; - assign rg_stip$EN = EN_fav_write || EN_reset ; - - // register rg_ueip - always@(EN_reset or - EN_fav_write or ueip__h563 or EN_fav_sip_write or ueip__h985) - case (1'b1) - EN_reset: rg_ueip$D_IN = 1'd0; - EN_fav_write: rg_ueip$D_IN = ueip__h563; - EN_fav_sip_write: rg_ueip$D_IN = ueip__h985; - default: rg_ueip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_ueip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_usip - always@(EN_reset or - EN_fav_write or usip__h567 or EN_fav_sip_write or usip__h987) - case (1'b1) - EN_reset: rg_usip$D_IN = 1'd0; - EN_fav_write: rg_usip$D_IN = usip__h567; - EN_fav_sip_write: rg_usip$D_IN = usip__h987; - default: rg_usip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_usip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_utip - assign rg_utip$D_IN = !EN_reset && utip__h565 ; - assign rg_utip$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign new_mip__h528 = - { rg_meip, - 1'b0, - rg_seip, - rg_ueip, - rg_mtip, - 1'b0, - rg_stip, - rg_utip, - rg_msip, - 1'b0, - rg_ssip, - rg_usip } ; - assign new_mip__h946 = - { rg_meip, - 1'b0, - seip__h562, - ueip__h563, - rg_mtip, - 1'b0, - stip__h564, - utip__h565, - rg_msip, - 1'b0, - ssip__h566, - usip__h567 } ; - assign seip__h562 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssip__h566 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign ssip__h986 = fav_sip_write_misa[18] && fav_sip_write_wordxl[1] ; - assign stip__h564 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueip__h563 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign ueip__h985 = fav_sip_write_misa[13] && fav_sip_write_wordxl[8] ; - assign usip__h567 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign usip__h987 = fav_sip_write_misa[13] && fav_sip_write_wordxl[0] ; - assign utip__h565 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN; - if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN; - if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN; - if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN; - if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN; - if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_meip = 1'h0; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_seip = 1'h0; - rg_ssip = 1'h0; - rg_stip = 1'h0; - rg_ueip = 1'h0; - rg_usip = 1'h0; - rg_utip = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIP - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v deleted file mode 100644 index 78e7758d..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v +++ /dev/null @@ -1,3747 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_csr O 33 -// read_csr_port2 O 33 -// mav_read_csr O 33 -// mav_csr_write O 32 -// read_frm O 3 reg -// read_misa O 28 const -// read_mstatus O 32 reg -// read_sstatus O 32 -// read_ustatus O 32 -// read_satp O 32 reg -// csr_trap_actions O 98 -// RDY_csr_trap_actions O 1 const -// csr_ret_actions O 66 -// RDY_csr_ret_actions O 1 const -// read_csr_minstret O 64 reg -// read_csr_mcycle O 64 reg -// read_csr_mtime O 64 reg -// access_permitted_1 O 1 -// access_permitted_2 O 1 -// csr_counter_read_fault O 1 -// csr_mip_read O 32 -// interrupt_pending O 5 -// wfi_resume O 1 -// nmi_pending O 1 reg -// RDY_debug O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// read_csr_csr_addr I 12 -// read_csr_port2_csr_addr I 12 -// mav_read_csr_csr_addr I 12 -// mav_csr_write_csr_addr I 12 -// mav_csr_write_word I 32 -// ma_update_fcsr_fflags_flags I 5 -// ma_update_mstatus_fs_fs I 2 -// csr_trap_actions_from_priv I 2 -// csr_trap_actions_pc I 32 -// csr_trap_actions_nmi I 1 -// csr_trap_actions_interrupt I 1 -// csr_trap_actions_exc_code I 4 -// csr_trap_actions_xtval I 32 -// csr_ret_actions_from_priv I 2 -// access_permitted_1_priv I 2 -// access_permitted_1_csr_addr I 12 -// access_permitted_1_read_not_write I 1 -// access_permitted_2_priv I 2 -// access_permitted_2_csr_addr I 12 -// access_permitted_2_read_not_write I 1 -// csr_counter_read_fault_priv I 2 -// csr_counter_read_fault_csr_addr I 12 -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// interrupt_pending_cur_priv I 2 -// nmi_req_set_not_clear I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_ma_update_fcsr_fflags I 1 -// EN_ma_update_mstatus_fs I 1 -// EN_csr_minstret_incr I 1 -// EN_debug I 1 unused -// EN_mav_read_csr I 1 unused -// EN_mav_csr_write I 1 -// EN_csr_trap_actions I 1 -// EN_csr_ret_actions I 1 -// -// Combinational paths from inputs to outputs: -// read_csr_csr_addr -> read_csr -// read_csr_port2_csr_addr -> read_csr_port2 -// (access_permitted_1_priv, -// access_permitted_1_csr_addr, -// access_permitted_1_read_not_write) -> access_permitted_1 -// (access_permitted_2_priv, -// access_permitted_2_csr_addr, -// access_permitted_2_read_not_write) -> access_permitted_2 -// (csr_counter_read_fault_priv, -// csr_counter_read_fault_csr_addr) -> csr_counter_read_fault -// interrupt_pending_cur_priv -> interrupt_pending -// mav_read_csr_csr_addr -> mav_read_csr -// (mav_csr_write_csr_addr, -// mav_csr_write_word, -// EN_mav_csr_write) -> mav_csr_write -// (csr_trap_actions_from_priv, -// csr_trap_actions_nmi, -// csr_trap_actions_interrupt, -// csr_trap_actions_exc_code) -> csr_trap_actions -// csr_ret_actions_from_priv -> csr_ret_actions -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_csr_csr_addr, - read_csr, - - read_csr_port2_csr_addr, - read_csr_port2, - - mav_read_csr_csr_addr, - EN_mav_read_csr, - mav_read_csr, - - mav_csr_write_csr_addr, - mav_csr_write_word, - EN_mav_csr_write, - mav_csr_write, - - read_frm, - - ma_update_fcsr_fflags_flags, - EN_ma_update_fcsr_fflags, - - ma_update_mstatus_fs_fs, - EN_ma_update_mstatus_fs, - - read_misa, - - read_mstatus, - - read_sstatus, - - read_ustatus, - - read_satp, - - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_nmi, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval, - EN_csr_trap_actions, - csr_trap_actions, - RDY_csr_trap_actions, - - csr_ret_actions_from_priv, - EN_csr_ret_actions, - csr_ret_actions, - RDY_csr_ret_actions, - - read_csr_minstret, - - EN_csr_minstret_incr, - - read_csr_mcycle, - - read_csr_mtime, - - access_permitted_1_priv, - access_permitted_1_csr_addr, - access_permitted_1_read_not_write, - access_permitted_1, - - access_permitted_2_priv, - access_permitted_2_csr_addr, - access_permitted_2_read_not_write, - access_permitted_2, - - csr_counter_read_fault_priv, - csr_counter_read_fault_csr_addr, - csr_counter_read_fault, - - csr_mip_read, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - interrupt_pending_cur_priv, - interrupt_pending, - - wfi_resume, - - nmi_req_set_not_clear, - - nmi_pending, - - EN_debug, - RDY_debug); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_csr - input [11 : 0] read_csr_csr_addr; - output [32 : 0] read_csr; - - // value method read_csr_port2 - input [11 : 0] read_csr_port2_csr_addr; - output [32 : 0] read_csr_port2; - - // actionvalue method mav_read_csr - input [11 : 0] mav_read_csr_csr_addr; - input EN_mav_read_csr; - output [32 : 0] mav_read_csr; - - // actionvalue method mav_csr_write - input [11 : 0] mav_csr_write_csr_addr; - input [31 : 0] mav_csr_write_word; - input EN_mav_csr_write; - output [31 : 0] mav_csr_write; - - // value method read_frm - output [2 : 0] read_frm; - - // action method ma_update_fcsr_fflags - input [4 : 0] ma_update_fcsr_fflags_flags; - input EN_ma_update_fcsr_fflags; - - // action method ma_update_mstatus_fs - input [1 : 0] ma_update_mstatus_fs_fs; - input EN_ma_update_mstatus_fs; - - // value method read_misa - output [27 : 0] read_misa; - - // value method read_mstatus - output [31 : 0] read_mstatus; - - // value method read_sstatus - output [31 : 0] read_sstatus; - - // value method read_ustatus - output [31 : 0] read_ustatus; - - // value method read_satp - output [31 : 0] read_satp; - - // actionvalue method csr_trap_actions - input [1 : 0] csr_trap_actions_from_priv; - input [31 : 0] csr_trap_actions_pc; - input csr_trap_actions_nmi; - input csr_trap_actions_interrupt; - input [3 : 0] csr_trap_actions_exc_code; - input [31 : 0] csr_trap_actions_xtval; - input EN_csr_trap_actions; - output [97 : 0] csr_trap_actions; - output RDY_csr_trap_actions; - - // actionvalue method csr_ret_actions - input [1 : 0] csr_ret_actions_from_priv; - input EN_csr_ret_actions; - output [65 : 0] csr_ret_actions; - output RDY_csr_ret_actions; - - // value method read_csr_minstret - output [63 : 0] read_csr_minstret; - - // action method csr_minstret_incr - input EN_csr_minstret_incr; - - // value method read_csr_mcycle - output [63 : 0] read_csr_mcycle; - - // value method read_csr_mtime - output [63 : 0] read_csr_mtime; - - // value method access_permitted_1 - input [1 : 0] access_permitted_1_priv; - input [11 : 0] access_permitted_1_csr_addr; - input access_permitted_1_read_not_write; - output access_permitted_1; - - // value method access_permitted_2 - input [1 : 0] access_permitted_2_priv; - input [11 : 0] access_permitted_2_csr_addr; - input access_permitted_2_read_not_write; - output access_permitted_2; - - // value method csr_counter_read_fault - input [1 : 0] csr_counter_read_fault_priv; - input [11 : 0] csr_counter_read_fault_csr_addr; - output csr_counter_read_fault; - - // value method csr_mip_read - output [31 : 0] csr_mip_read; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // value method interrupt_pending - input [1 : 0] interrupt_pending_cur_priv; - output [4 : 0] interrupt_pending; - - // value method wfi_resume - output wfi_resume; - - // action method nmi_req - input nmi_req_set_not_clear; - - // value method nmi_pending - output nmi_pending; - - // action method debug - input EN_debug; - output RDY_debug; - - // signals for module outputs - wire [97 : 0] csr_trap_actions; - wire [65 : 0] csr_ret_actions; - wire [63 : 0] read_csr_mcycle, read_csr_minstret, read_csr_mtime; - wire [32 : 0] mav_read_csr, read_csr, read_csr_port2; - wire [31 : 0] csr_mip_read, - mav_csr_write, - read_mstatus, - read_satp, - read_sstatus, - read_ustatus; - wire [27 : 0] read_misa; - wire [4 : 0] interrupt_pending; - wire [2 : 0] read_frm; - wire RDY_csr_ret_actions, - RDY_csr_trap_actions, - RDY_debug, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - access_permitted_1, - access_permitted_2, - csr_counter_read_fault, - nmi_pending, - wfi_resume; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register csr_mstatus_rg_mstatus - reg [31 : 0] csr_mstatus_rg_mstatus; - reg [31 : 0] csr_mstatus_rg_mstatus$D_IN; - wire csr_mstatus_rg_mstatus$EN; - - // register rg_dcsr - reg [31 : 0] rg_dcsr; - wire [31 : 0] rg_dcsr$D_IN; - wire rg_dcsr$EN; - - // register rg_dpc - reg [31 : 0] rg_dpc; - wire [31 : 0] rg_dpc$D_IN; - wire rg_dpc$EN; - - // register rg_dscratch0 - reg [31 : 0] rg_dscratch0; - wire [31 : 0] rg_dscratch0$D_IN; - wire rg_dscratch0$EN; - - // register rg_dscratch1 - reg [31 : 0] rg_dscratch1; - wire [31 : 0] rg_dscratch1$D_IN; - wire rg_dscratch1$EN; - - // register rg_fflags - reg [4 : 0] rg_fflags; - reg [4 : 0] rg_fflags$D_IN; - wire rg_fflags$EN; - - // register rg_frm - reg [2 : 0] rg_frm; - wire [2 : 0] rg_frm$D_IN; - wire rg_frm$EN; - - // register rg_mcause - reg [4 : 0] rg_mcause; - reg [4 : 0] rg_mcause$D_IN; - wire rg_mcause$EN; - - // register rg_mcounteren - reg [2 : 0] rg_mcounteren; - wire [2 : 0] rg_mcounteren$D_IN; - wire rg_mcounteren$EN; - - // register rg_mcycle - reg [63 : 0] rg_mcycle; - wire [63 : 0] rg_mcycle$D_IN; - wire rg_mcycle$EN; - - // register rg_medeleg - reg [15 : 0] rg_medeleg; - wire [15 : 0] rg_medeleg$D_IN; - wire rg_medeleg$EN; - - // register rg_mepc - reg [31 : 0] rg_mepc; - wire [31 : 0] rg_mepc$D_IN; - wire rg_mepc$EN; - - // register rg_mideleg - reg [11 : 0] rg_mideleg; - wire [11 : 0] rg_mideleg$D_IN; - wire rg_mideleg$EN; - - // register rg_minstret - reg [63 : 0] rg_minstret; - wire [63 : 0] rg_minstret$D_IN; - wire rg_minstret$EN; - - // register rg_mscratch - reg [31 : 0] rg_mscratch; - wire [31 : 0] rg_mscratch$D_IN; - wire rg_mscratch$EN; - - // register rg_mtval - reg [31 : 0] rg_mtval; - wire [31 : 0] rg_mtval$D_IN; - wire rg_mtval$EN; - - // register rg_mtvec - reg [30 : 0] rg_mtvec; - wire [30 : 0] rg_mtvec$D_IN; - wire rg_mtvec$EN; - - // register rg_nmi - reg rg_nmi; - wire rg_nmi$D_IN, rg_nmi$EN; - - // register rg_nmi_vector - reg [31 : 0] rg_nmi_vector; - wire [31 : 0] rg_nmi_vector$D_IN; - wire rg_nmi_vector$EN; - - // register rg_satp - reg [31 : 0] rg_satp; - wire [31 : 0] rg_satp$D_IN; - wire rg_satp$EN; - - // register rg_scause - reg [4 : 0] rg_scause; - reg [4 : 0] rg_scause$D_IN; - wire rg_scause$EN; - - // register rg_sepc - reg [31 : 0] rg_sepc; - wire [31 : 0] rg_sepc$D_IN; - wire rg_sepc$EN; - - // register rg_sscratch - reg [31 : 0] rg_sscratch; - wire [31 : 0] rg_sscratch$D_IN; - wire rg_sscratch$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_stval - reg [31 : 0] rg_stval; - wire [31 : 0] rg_stval$D_IN; - wire rg_stval$EN; - - // register rg_stvec - reg [30 : 0] rg_stvec; - wire [30 : 0] rg_stvec$D_IN; - wire rg_stvec$EN; - - // register rg_tdata1 - reg [31 : 0] rg_tdata1; - wire [31 : 0] rg_tdata1$D_IN; - wire rg_tdata1$EN; - - // register rg_tdata2 - reg [31 : 0] rg_tdata2; - wire [31 : 0] rg_tdata2$D_IN; - wire rg_tdata2$EN; - - // register rg_tdata3 - reg [31 : 0] rg_tdata3; - wire [31 : 0] rg_tdata3$D_IN; - wire rg_tdata3$EN; - - // register rg_tselect - reg [31 : 0] rg_tselect; - wire [31 : 0] rg_tselect$D_IN; - wire rg_tselect$EN; - - // ports of submodule csr_mie - wire [31 : 0] csr_mie$fav_sie_write, - csr_mie$fav_sie_write_wordxl, - csr_mie$fav_write, - csr_mie$fav_write_wordxl, - csr_mie$fv_read, - csr_mie$fv_sie_read; - wire [27 : 0] csr_mie$fav_sie_write_misa, csr_mie$fav_write_misa; - wire csr_mie$EN_fav_sie_write, csr_mie$EN_fav_write, csr_mie$EN_reset; - - // ports of submodule csr_mip - wire [31 : 0] csr_mip$fav_sip_write, - csr_mip$fav_sip_write_wordxl, - csr_mip$fav_write, - csr_mip$fav_write_wordxl, - csr_mip$fv_read, - csr_mip$fv_sip_read; - wire [27 : 0] csr_mip$fav_sip_write_misa, csr_mip$fav_write_misa; - wire csr_mip$EN_fav_sip_write, - csr_mip$EN_fav_write, - csr_mip$EN_reset, - csr_mip$m_external_interrupt_req_req, - csr_mip$s_external_interrupt_req_req, - csr_mip$software_interrupt_req_req, - csr_mip$timer_interrupt_req_req; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mtvec_reset_value, - soc_map$m_nmivec_reset_value; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_mcycle_incr, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_upd_minstret_csrrx, - CAN_FIRE_RL_rl_upd_minstret_incr, - CAN_FIRE_csr_minstret_incr, - CAN_FIRE_csr_ret_actions, - CAN_FIRE_csr_trap_actions, - CAN_FIRE_debug, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_ma_update_fcsr_fflags, - CAN_FIRE_ma_update_mstatus_fs, - CAN_FIRE_mav_csr_write, - CAN_FIRE_mav_read_csr, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_rl_mcycle_incr, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_upd_minstret_csrrx, - WILL_FIRE_RL_rl_upd_minstret_incr, - WILL_FIRE_csr_minstret_incr, - WILL_FIRE_csr_ret_actions, - WILL_FIRE_csr_trap_actions, - WILL_FIRE_debug, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_ma_update_fcsr_fflags, - WILL_FIRE_ma_update_mstatus_fs, - WILL_FIRE_mav_csr_write, - WILL_FIRE_mav_read_csr, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_rg_minstret$write_1__VAL_1, - MUX_rg_minstret$write_1__VAL_2, - MUX_rw_minstret$wset_1__VAL_1; - wire [31 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_2, - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4, - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5; - wire [30 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; - wire [15 : 0] MUX_rg_medeleg$write_1__VAL_1; - wire [4 : 0] MUX_rg_fflags$write_1__VAL_3, - MUX_rg_mcause$write_1__VAL_2, - MUX_rg_mcause$write_1__VAL_3; - wire [2 : 0] MUX_rg_frm$write_1__VAL_1; - wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_5, - MUX_rg_fflags$write_1__SEL_2, - MUX_rg_frm$write_1__SEL_1, - MUX_rg_mcause$write_1__SEL_2, - MUX_rg_mcause$write_1__SEL_3, - MUX_rg_mcounteren$write_1__SEL_1, - MUX_rg_medeleg$write_1__SEL_1, - MUX_rg_mideleg$write_1__SEL_1, - MUX_rg_mtvec$write_1__SEL_1, - MUX_rg_satp$write_1__SEL_1, - MUX_rg_scause$write_1__SEL_2, - MUX_rg_scause$write_1__SEL_3, - MUX_rg_sepc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2, - MUX_rg_stval$write_1__SEL_1, - MUX_rg_stvec$write_1__SEL_1, - MUX_rg_tdata1$write_1__SEL_1, - MUX_rw_minstret$wset_1__SEL_1; - - // remaining internal signals - reg [31 : 0] IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860, - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336, - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598, - y_avValue_fst__h8976; - reg [29 : 0] CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1; - reg CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2, - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990, - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093; - wire [63 : 0] x__h8408, x__h8516; - wire [31 : 0] IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484, - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682, - _theResult___fst__h12935, - _theResult___fst__h13136, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476, - exc_pc___1__h12025, - exc_pc__h11951, - mask__h10973, - mask__h10990, - mask__h12956, - mask__h12973, - result__h8591, - v__h10796, - v__h5698, - v__h5842, - v__h5956, - v__h7081, - v__h7117, - v__h7758, - v__h7820, - v__h7976, - val__h10974, - val__h10991, - val__h12974, - vector_offset__h11952, - wordxl1__h7212, - x__h10972, - x__h10985, - x__h11002, - x__h12806, - x__h12807, - x__h12955, - x__h12968, - x__h12985, - x__h9768, - y__h10986, - y__h11003, - y__h12969, - y__h12986, - y_avValue_fst__h11908, - y_avValue_fst__h11925, - y_avValue_snd_snd__h11998; - wire [22 : 0] fixed_up_val_23__h10840, - fixed_up_val_23__h12869, - fixed_up_val_23__h6007, - fixed_up_val_23__h7253, - fixed_up_val_23__h9209; - wire [5 : 0] ie_from_x__h12919, - ie_to_x__h10890, - pie_from_x__h12920, - pie_to_x__h10891; - wire [3 : 0] IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2171, - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2173, - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2174, - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2176, - exc_code__h12648; - wire [1 : 0] IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906, - _theResult____h14614, - _theResult____h14826, - _theResult____h15038, - _theResult____h15250, - _theResult____h15462, - _theResult____h15674, - _theResult____h15886, - _theResult____h16098, - _theResult____h16310, - _theResult___fst__h10902, - new_priv__h10791, - to_y__h13135; - wire NOT_access_permitted_1_csr_addr_ULT_0xC03_701__ETC___d1821, - NOT_access_permitted_2_csr_addr_ULT_0xC03_826__ETC___d1944, - NOT_cfg_verbosity_read__148_ULE_1_149___d1150, - NOT_csr_mip_fv_read__94_BIT_0_060_151_OR_NOT_c_ETC___d2158, - NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096, - NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123, - NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150, - NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131, - NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104, - NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140, - NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113, - NOT_csr_mip_fv_read__94_BIT_8_049_142_OR_NOT_c_ETC___d2149, - NOT_csr_mip_fv_read__94_BIT_9_016_115_OR_NOT_c_ETC___d2122, - NOT_csr_trap_actions_nmi_499_AND_csr_trap_acti_ETC___d1606, - NOT_mav_csr_write_csr_addr_ULT_0xB03_63_152_AN_ETC___d1159, - b__h10989, - b__h12972, - csr_mip_fv_read__94_BIT_0_060_AND_csr_mie_fv_r_ETC___d2069, - csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d1993, - csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d2059, - csr_mip_fv_read__94_BIT_1_027_AND_csr_mie_fv_r_ETC___d2036, - csr_mip_fv_read__94_BIT_3_994_AND_csr_mie_fv_r_ETC___d2003, - csr_mip_fv_read__94_BIT_4_071_AND_csr_mie_fv_r_ETC___d2080, - csr_mip_fv_read__94_BIT_5_038_AND_csr_mie_fv_r_ETC___d2047, - csr_mip_fv_read__94_BIT_7_005_AND_csr_mie_fv_r_ETC___d2014, - csr_mip_fv_read__94_BIT_8_049_AND_csr_mie_fv_r_ETC___d2058, - csr_mip_fv_read__94_BIT_9_016_AND_csr_mie_fv_r_ETC___d2025, - csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1508, - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1657, - deleg_bit___1__h10911, - deleg_bit___1__h10926, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065, - mav_csr_write_csr_addr_ULE_0x33F___d872, - mav_csr_write_csr_addr_ULE_0xB1F___d864, - mav_csr_write_csr_addr_ULE_0xB9F___d868, - mav_csr_write_csr_addr_ULT_0x323_71_OR_NOT_mav_ETC___d1145, - mav_csr_write_csr_addr_ULT_0x323___d871, - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d1147, - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876, - mav_csr_write_csr_addr_ULT_0xB03___d863, - mav_csr_write_csr_addr_ULT_0xB83___d867, - sd__h10839, - sd__h12868, - sd__h7252, - sd__h9208; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_csr - assign read_csr = - { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hC83 && read_csr_csr_addr <= 12'hC9F || - read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'hB83 && read_csr_csr_addr <= 12'hB9F || - read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || - read_csr_csr_addr == 12'h001 || - read_csr_csr_addr == 12'h002 || - read_csr_csr_addr == 12'h003 || - read_csr_csr_addr == 12'hC00 || - read_csr_csr_addr == 12'hC02 || - read_csr_csr_addr == 12'hC80 || - read_csr_csr_addr == 12'hC82 || - read_csr_csr_addr == 12'h100 || - read_csr_csr_addr == 12'h102 || - read_csr_csr_addr == 12'h103 || - read_csr_csr_addr == 12'h104 || - read_csr_csr_addr == 12'h105 || - read_csr_csr_addr == 12'h106 || - read_csr_csr_addr == 12'h140 || - read_csr_csr_addr == 12'h141 || - read_csr_csr_addr == 12'h142 || - read_csr_csr_addr == 12'h143 || - read_csr_csr_addr == 12'h144 || - read_csr_csr_addr == 12'h180 || - read_csr_csr_addr == 12'h302 || - read_csr_csr_addr == 12'h303 || - read_csr_csr_addr == 12'hF11 || - read_csr_csr_addr == 12'hF12 || - read_csr_csr_addr == 12'hF13 || - read_csr_csr_addr == 12'hF14 || - read_csr_csr_addr == 12'h300 || - read_csr_csr_addr == 12'h301 || - read_csr_csr_addr == 12'h304 || - read_csr_csr_addr == 12'h305 || - read_csr_csr_addr == 12'h306 || - read_csr_csr_addr == 12'h340 || - read_csr_csr_addr == 12'h341 || - read_csr_csr_addr == 12'h342 || - read_csr_csr_addr == 12'h343 || - read_csr_csr_addr == 12'h344 || - read_csr_csr_addr == 12'hB00 || - read_csr_csr_addr == 12'hB02 || - read_csr_csr_addr == 12'hB80 || - read_csr_csr_addr == 12'hB82 || - read_csr_csr_addr == 12'h7A0 || - read_csr_csr_addr == 12'h7A1 || - read_csr_csr_addr == 12'h7A2 || - read_csr_csr_addr == 12'h7A3, - (read_csr_csr_addr >= 12'hC03 && - read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hC83 && - read_csr_csr_addr <= 12'hC9F || - read_csr_csr_addr >= 12'hB03 && - read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'hB83 && - read_csr_csr_addr <= 12'hB9F || - read_csr_csr_addr >= 12'h323 && - read_csr_csr_addr <= 12'h33F) ? - 32'd0 : - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 } ; - - // value method read_csr_port2 - assign read_csr_port2 = - { read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hC83 && - read_csr_port2_csr_addr <= 12'hC9F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'hB83 && - read_csr_port2_csr_addr <= 12'hB9F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F || - read_csr_port2_csr_addr == 12'h001 || - read_csr_port2_csr_addr == 12'h002 || - read_csr_port2_csr_addr == 12'h003 || - read_csr_port2_csr_addr == 12'hC00 || - read_csr_port2_csr_addr == 12'hC02 || - read_csr_port2_csr_addr == 12'hC80 || - read_csr_port2_csr_addr == 12'hC82 || - read_csr_port2_csr_addr == 12'h100 || - read_csr_port2_csr_addr == 12'h102 || - read_csr_port2_csr_addr == 12'h103 || - read_csr_port2_csr_addr == 12'h104 || - read_csr_port2_csr_addr == 12'h105 || - read_csr_port2_csr_addr == 12'h106 || - read_csr_port2_csr_addr == 12'h140 || - read_csr_port2_csr_addr == 12'h141 || - read_csr_port2_csr_addr == 12'h142 || - read_csr_port2_csr_addr == 12'h143 || - read_csr_port2_csr_addr == 12'h144 || - read_csr_port2_csr_addr == 12'h180 || - read_csr_port2_csr_addr == 12'h302 || - read_csr_port2_csr_addr == 12'h303 || - read_csr_port2_csr_addr == 12'hF11 || - read_csr_port2_csr_addr == 12'hF12 || - read_csr_port2_csr_addr == 12'hF13 || - read_csr_port2_csr_addr == 12'hF14 || - read_csr_port2_csr_addr == 12'h300 || - read_csr_port2_csr_addr == 12'h301 || - read_csr_port2_csr_addr == 12'h304 || - read_csr_port2_csr_addr == 12'h305 || - read_csr_port2_csr_addr == 12'h306 || - read_csr_port2_csr_addr == 12'h340 || - read_csr_port2_csr_addr == 12'h341 || - read_csr_port2_csr_addr == 12'h342 || - read_csr_port2_csr_addr == 12'h343 || - read_csr_port2_csr_addr == 12'h344 || - read_csr_port2_csr_addr == 12'hB00 || - read_csr_port2_csr_addr == 12'hB02 || - read_csr_port2_csr_addr == 12'hB80 || - read_csr_port2_csr_addr == 12'hB82 || - read_csr_port2_csr_addr == 12'h7A0 || - read_csr_port2_csr_addr == 12'h7A1 || - read_csr_port2_csr_addr == 12'h7A2 || - read_csr_port2_csr_addr == 12'h7A3, - (read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hC83 && - read_csr_port2_csr_addr <= 12'hC9F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'hB83 && - read_csr_port2_csr_addr <= 12'hB9F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F) ? - 32'd0 : - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 } ; - - // actionvalue method mav_read_csr - assign mav_read_csr = - { mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hC83 && - mav_read_csr_csr_addr <= 12'hC9F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'hB83 && - mav_read_csr_csr_addr <= 12'hB9F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F || - mav_read_csr_csr_addr == 12'h001 || - mav_read_csr_csr_addr == 12'h002 || - mav_read_csr_csr_addr == 12'h003 || - mav_read_csr_csr_addr == 12'hC00 || - mav_read_csr_csr_addr == 12'hC02 || - mav_read_csr_csr_addr == 12'hC80 || - mav_read_csr_csr_addr == 12'hC82 || - mav_read_csr_csr_addr == 12'h100 || - mav_read_csr_csr_addr == 12'h102 || - mav_read_csr_csr_addr == 12'h103 || - mav_read_csr_csr_addr == 12'h104 || - mav_read_csr_csr_addr == 12'h105 || - mav_read_csr_csr_addr == 12'h106 || - mav_read_csr_csr_addr == 12'h140 || - mav_read_csr_csr_addr == 12'h141 || - mav_read_csr_csr_addr == 12'h142 || - mav_read_csr_csr_addr == 12'h143 || - mav_read_csr_csr_addr == 12'h144 || - mav_read_csr_csr_addr == 12'h180 || - mav_read_csr_csr_addr == 12'h302 || - mav_read_csr_csr_addr == 12'h303 || - mav_read_csr_csr_addr == 12'hF11 || - mav_read_csr_csr_addr == 12'hF12 || - mav_read_csr_csr_addr == 12'hF13 || - mav_read_csr_csr_addr == 12'hF14 || - mav_read_csr_csr_addr == 12'h300 || - mav_read_csr_csr_addr == 12'h301 || - mav_read_csr_csr_addr == 12'h304 || - mav_read_csr_csr_addr == 12'h305 || - mav_read_csr_csr_addr == 12'h306 || - mav_read_csr_csr_addr == 12'h340 || - mav_read_csr_csr_addr == 12'h341 || - mav_read_csr_csr_addr == 12'h342 || - mav_read_csr_csr_addr == 12'h343 || - mav_read_csr_csr_addr == 12'h344 || - mav_read_csr_csr_addr == 12'hB00 || - mav_read_csr_csr_addr == 12'hB02 || - mav_read_csr_csr_addr == 12'hB80 || - mav_read_csr_csr_addr == 12'hB82 || - mav_read_csr_csr_addr == 12'h7A0 || - mav_read_csr_csr_addr == 12'h7A1 || - mav_read_csr_csr_addr == 12'h7A2 || - mav_read_csr_csr_addr == 12'h7A3, - (mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hC83 && - mav_read_csr_csr_addr <= 12'hC9F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'hB83 && - mav_read_csr_csr_addr <= 12'hB9F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F) ? - 32'd0 : - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 } ; - assign CAN_FIRE_mav_read_csr = 1'd1 ; - assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; - - // actionvalue method mav_csr_write - assign mav_csr_write = - NOT_mav_csr_write_csr_addr_ULT_0xB03_63_152_AN_ETC___d1159 ? - 32'd0 : - y_avValue_fst__h8976 ; - assign CAN_FIRE_mav_csr_write = 1'd1 ; - assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; - - // value method read_frm - assign read_frm = rg_frm ; - - // action method ma_update_fcsr_fflags - assign CAN_FIRE_ma_update_fcsr_fflags = 1'd1 ; - assign WILL_FIRE_ma_update_fcsr_fflags = EN_ma_update_fcsr_fflags ; - - // action method ma_update_mstatus_fs - assign CAN_FIRE_ma_update_mstatus_fs = 1'd1 ; - assign WILL_FIRE_ma_update_mstatus_fs = EN_ma_update_mstatus_fs ; - - // value method read_misa - assign read_misa = 28'd68423981 ; - - // value method read_mstatus - assign read_mstatus = csr_mstatus_rg_mstatus ; - - // value method read_sstatus - assign read_sstatus = - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] } ; - - // value method read_ustatus - assign read_ustatus = - { 27'd0, - csr_mstatus_rg_mstatus[4], - 3'd0, - csr_mstatus_rg_mstatus[0] } ; - - // value method read_satp - assign read_satp = rg_satp ; - - // actionvalue method csr_trap_actions - assign csr_trap_actions = - { x__h9768, x__h12806, x__h12807, new_priv__h10791 } ; - assign RDY_csr_trap_actions = 1'd1 ; - assign CAN_FIRE_csr_trap_actions = 1'd1 ; - assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; - - // actionvalue method csr_ret_actions - assign csr_ret_actions = - (csr_ret_actions_from_priv == 2'b11) ? - { rg_mepc, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[12:11], - _theResult___fst__h12935 } : - { rg_sepc, to_y__h13135, _theResult___fst__h13136 } ; - assign RDY_csr_ret_actions = 1'd1 ; - assign CAN_FIRE_csr_ret_actions = 1'd1 ; - assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; - - // value method read_csr_minstret - assign read_csr_minstret = rg_minstret ; - - // action method csr_minstret_incr - assign CAN_FIRE_csr_minstret_incr = 1'd1 ; - assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; - - // value method read_csr_mcycle - assign read_csr_mcycle = rg_mcycle ; - - // value method read_csr_mtime - assign read_csr_mtime = rg_mcycle ; - - // value method access_permitted_1 - assign access_permitted_1 = - NOT_access_permitted_1_csr_addr_ULT_0xC03_701__ETC___d1821 && - (access_permitted_1_read_not_write || - access_permitted_1_csr_addr[11:10] != 2'b11) ; - - // value method access_permitted_2 - assign access_permitted_2 = - NOT_access_permitted_2_csr_addr_ULT_0xC03_826__ETC___d1944 && - (access_permitted_2_read_not_write || - access_permitted_2_csr_addr[11:10] != 2'b11) ; - - // value method csr_counter_read_fault - assign csr_counter_read_fault = - (csr_counter_read_fault_priv == 2'b01 || - csr_counter_read_fault_priv == 2'b0) && - (csr_counter_read_fault_csr_addr == 12'hC00 && - !rg_mcounteren[0] || - csr_counter_read_fault_csr_addr == 12'hC01 && - !rg_mcounteren[1] || - csr_counter_read_fault_csr_addr == 12'hC02 && - !rg_mcounteren[2] || - csr_counter_read_fault_csr_addr >= 12'hC03 && - csr_counter_read_fault_csr_addr <= 12'hC1F || - csr_counter_read_fault_csr_addr >= 12'hC83 && - csr_counter_read_fault_csr_addr <= 12'hC9F) ; - - // value method csr_mip_read - assign csr_mip_read = csr_mip$fv_read ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // value method interrupt_pending - assign interrupt_pending = - { csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d2059 || - csr_mip_fv_read__94_BIT_0_060_AND_csr_mie_fv_r_ETC___d2069 || - csr_mip_fv_read__94_BIT_4_071_AND_csr_mie_fv_r_ETC___d2080, - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2176 } ; - - // value method wfi_resume - assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 32'd0 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // value method nmi_pending - assign nmi_pending = rg_nmi ; - - // action method debug - assign RDY_debug = 1'd1 ; - assign CAN_FIRE_debug = 1'd1 ; - assign WILL_FIRE_debug = EN_debug ; - - // submodule csr_mie - mkCSR_MIE csr_mie(.CLK(CLK), - .RST_N(RST_N), - .fav_sie_write_misa(csr_mie$fav_sie_write_misa), - .fav_sie_write_wordxl(csr_mie$fav_sie_write_wordxl), - .fav_write_misa(csr_mie$fav_write_misa), - .fav_write_wordxl(csr_mie$fav_write_wordxl), - .EN_reset(csr_mie$EN_reset), - .EN_fav_write(csr_mie$EN_fav_write), - .EN_fav_sie_write(csr_mie$EN_fav_sie_write), - .fv_read(csr_mie$fv_read), - .fav_write(csr_mie$fav_write), - .fv_sie_read(csr_mie$fv_sie_read), - .fav_sie_write(csr_mie$fav_sie_write)); - - // submodule csr_mip - mkCSR_MIP csr_mip(.CLK(CLK), - .RST_N(RST_N), - .fav_sip_write_misa(csr_mip$fav_sip_write_misa), - .fav_sip_write_wordxl(csr_mip$fav_sip_write_wordxl), - .fav_write_misa(csr_mip$fav_write_misa), - .fav_write_wordxl(csr_mip$fav_write_wordxl), - .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), - .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), - .software_interrupt_req_req(csr_mip$software_interrupt_req_req), - .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), - .EN_reset(csr_mip$EN_reset), - .EN_fav_write(csr_mip$EN_fav_write), - .EN_fav_sip_write(csr_mip$EN_fav_sip_write), - .fv_read(csr_mip$fv_read), - .fav_write(csr_mip$fav_write), - .fv_sip_read(csr_mip$fv_sip_read), - .fav_sip_write(csr_mip$fav_sip_write)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), - .m_nmivec_reset_value(soc_map$m_nmivec_reset_value)); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = !rg_state ; - assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_mcycle_incr - assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; - assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; - - // rule RL_rl_upd_minstret_csrrx - assign CAN_FIRE_RL_rl_upd_minstret_csrrx = - MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; - assign WILL_FIRE_RL_rl_upd_minstret_csrrx = - CAN_FIRE_RL_rl_upd_minstret_csrrx ; - - // rule RL_rl_upd_minstret_incr - assign CAN_FIRE_RL_rl_upd_minstret_incr = - !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; - assign WILL_FIRE_RL_rl_upd_minstret_incr = - CAN_FIRE_RL_rl_upd_minstret_incr ; - - // inputs to muxes for submodule ports - assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h100 || - mav_csr_write_csr_addr == 12'h300) ; - assign MUX_rg_fflags$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h001 || - mav_csr_write_csr_addr == 12'h003) ; - assign MUX_rg_frm$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h002 || - mav_csr_write_csr_addr == 12'h003) ; - assign MUX_rg_mcause$write_1__SEL_2 = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) ; - assign MUX_rg_mcause$write_1__SEL_3 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h342 ; - assign MUX_rg_mcounteren$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h306 ; - assign MUX_rg_medeleg$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h302 ; - assign MUX_rg_mideleg$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h303 ; - assign MUX_rg_mtvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h305 ; - assign MUX_rg_satp$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h180 ; - assign MUX_rg_scause$write_1__SEL_2 = - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h10791 == 2'b01 ; - assign MUX_rg_scause$write_1__SEL_3 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h142 ; - assign MUX_rg_sepc$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h141 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; - assign MUX_rg_stval$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h143 ; - assign MUX_rg_stvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h105 ; - assign MUX_rg_tdata1$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h7A1 ; - assign MUX_rw_minstret$wset_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'hB02 || - mav_csr_write_csr_addr == 12'hB82) ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 = - { sd__h12868, 8'd0, fixed_up_val_23__h12869 } ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 = - { sd__h9208, 8'd0, fixed_up_val_23__h9209 } ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_5 = - { sd__h7252, - 8'd0, - (mav_csr_write_csr_addr == 12'h100) ? - fixed_up_val_23__h6007 : - fixed_up_val_23__h7253 } ; - assign MUX_rg_fflags$write_1__VAL_3 = - rg_fflags | ma_update_fcsr_fflags_flags ; - assign MUX_rg_frm$write_1__VAL_1 = - (mav_csr_write_csr_addr == 12'h002) ? - mav_csr_write_word[2:0] : - mav_csr_write_word[7:5] ; - assign MUX_rg_mcause$write_1__VAL_2 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - exc_code__h12648 } ; - assign MUX_rg_mcause$write_1__VAL_3 = - { mav_csr_write_word[31], mav_csr_write_word[3:0] } ; - assign MUX_rg_medeleg$write_1__VAL_1 = - { mav_csr_write_word[15], - 1'd0, - mav_csr_write_word[13:12], - 2'd0, - mav_csr_write_word[9:0] } ; - assign MUX_rg_minstret$write_1__VAL_1 = - MUX_rw_minstret$wset_1__SEL_1 ? - MUX_rw_minstret$wset_1__VAL_1 : - 64'd0 ; - assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; - assign MUX_rg_mtvec$write_1__VAL_1 = - { mav_csr_write_word[31:2], mav_csr_write_word[0] } ; - assign MUX_rg_mtvec$write_1__VAL_2 = - { soc_map$m_mtvec_reset_value[31:2], - soc_map$m_mtvec_reset_value[0] } ; - assign MUX_rw_minstret$wset_1__VAL_1 = - (mav_csr_write_csr_addr == 12'hB02) ? x__h8408 : x__h8516 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register csr_mstatus_rg_mstatus - always@(WILL_FIRE_RL_rl_reset_start or - EN_csr_ret_actions or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 or - EN_csr_trap_actions or - v__h10796 or - EN_ma_update_mstatus_fs or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 or - MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: csr_mstatus_rg_mstatus$D_IN = 32'd8192; - EN_csr_ret_actions: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_2; - EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = v__h10796; - EN_ma_update_mstatus_fs: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4; - MUX_csr_mstatus_rg_mstatus$write_1__SEL_5: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5; - default: csr_mstatus_rg_mstatus$D_IN = - 32'hAAAAAAAA /* unspecified value */ ; - endcase - assign csr_mstatus_rg_mstatus$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h100 || - mav_csr_write_csr_addr == 12'h300) || - EN_csr_trap_actions || - EN_ma_update_mstatus_fs || - EN_csr_ret_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_dcsr - assign rg_dcsr$D_IN = 32'h0 ; - assign rg_dcsr$EN = 1'b0 ; - - // register rg_dpc - assign rg_dpc$D_IN = 32'h0 ; - assign rg_dpc$EN = 1'b0 ; - - // register rg_dscratch0 - assign rg_dscratch0$D_IN = 32'h0 ; - assign rg_dscratch0$EN = 1'b0 ; - - // register rg_dscratch1 - assign rg_dscratch1$D_IN = 32'h0 ; - assign rg_dscratch1$EN = 1'b0 ; - - // register rg_fflags - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_fflags$write_1__SEL_2 or - mav_csr_write_word or - EN_ma_update_fcsr_fflags or MUX_rg_fflags$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_fflags$D_IN = 5'd0; - MUX_rg_fflags$write_1__SEL_2: rg_fflags$D_IN = mav_csr_write_word[4:0]; - EN_ma_update_fcsr_fflags: rg_fflags$D_IN = MUX_rg_fflags$write_1__VAL_3; - default: rg_fflags$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_fflags$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h001 || - mav_csr_write_csr_addr == 12'h003) || - EN_ma_update_fcsr_fflags || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_frm - assign rg_frm$D_IN = - MUX_rg_frm$write_1__SEL_1 ? MUX_rg_frm$write_1__VAL_1 : 3'd0 ; - assign rg_frm$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h002 || - mav_csr_write_csr_addr == 12'h003) || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_mcause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - MUX_rg_mcause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; - MUX_rg_mcause$write_1__SEL_2: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; - MUX_rg_mcause$write_1__SEL_3: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_mcause$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h342 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcounteren - assign rg_mcounteren$D_IN = - MUX_rg_mcounteren$write_1__SEL_1 ? - mav_csr_write_word[2:0] : - 3'd0 ; - assign rg_mcounteren$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h306 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcycle - assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; - assign rg_mcycle$EN = 1'd1 ; - - // register rg_medeleg - assign rg_medeleg$D_IN = - MUX_rg_medeleg$write_1__SEL_1 ? - MUX_rg_medeleg$write_1__VAL_1 : - 16'd0 ; - assign rg_medeleg$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h302 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mepc - assign rg_mepc$D_IN = - MUX_rg_mcause$write_1__SEL_2 ? - csr_trap_actions_pc : - mav_csr_write_word ; - assign rg_mepc$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h341 ; - - // register rg_mideleg - assign rg_mideleg$D_IN = - MUX_rg_mideleg$write_1__SEL_1 ? - mav_csr_write_word[11:0] : - 12'd0 ; - assign rg_mideleg$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h303 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_minstret - assign rg_minstret$D_IN = - WILL_FIRE_RL_rl_upd_minstret_csrrx ? - MUX_rg_minstret$write_1__VAL_1 : - MUX_rg_minstret$write_1__VAL_2 ; - assign rg_minstret$EN = - WILL_FIRE_RL_rl_upd_minstret_csrrx || - WILL_FIRE_RL_rl_upd_minstret_incr ; - - // register rg_mscratch - assign rg_mscratch$D_IN = mav_csr_write_word ; - assign rg_mscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h340 ; - - // register rg_mtval - assign rg_mtval$D_IN = - MUX_rg_mcause$write_1__SEL_2 ? - csr_trap_actions_xtval : - mav_csr_write_word ; - assign rg_mtval$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h343 ; - - // register rg_mtvec - assign rg_mtvec$D_IN = - MUX_rg_mtvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_mtvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h305 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_nmi - assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ; - assign rg_nmi$EN = 1'b1 ; - - // register rg_nmi_vector - assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value[31:0] ; - assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_satp - assign rg_satp$D_IN = - MUX_rg_satp$write_1__SEL_1 ? mav_csr_write_word : 32'd0 ; - assign rg_satp$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h180 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_scause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_scause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - MUX_rg_scause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_scause$D_IN = 5'd0; - MUX_rg_scause$write_1__SEL_2: - rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_2; - MUX_rg_scause$write_1__SEL_3: - rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_scause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_scause$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h142 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h10791 == 2'b01 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_sepc - assign rg_sepc$D_IN = - MUX_rg_sepc$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_pc ; - assign rg_sepc$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h141 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h10791 == 2'b01 ; - - // register rg_sscratch - assign rg_sscratch$D_IN = mav_csr_write_word ; - assign rg_sscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h140 ; - - // register rg_state - assign rg_state$D_IN = !EN_server_reset_request_put ; - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; - - // register rg_stval - assign rg_stval$D_IN = - MUX_rg_stval$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_xtval ; - assign rg_stval$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h143 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h10791 == 2'b01 ; - - // register rg_stvec - assign rg_stvec$D_IN = - MUX_rg_stvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_stvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h105 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata1 - assign rg_tdata1$D_IN = - MUX_rg_tdata1$write_1__SEL_1 ? result__h8591 : 32'd0 ; - assign rg_tdata1$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h7A1 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata2 - assign rg_tdata2$D_IN = mav_csr_write_word ; - assign rg_tdata2$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h7A2 ; - - // register rg_tdata3 - assign rg_tdata3$D_IN = mav_csr_write_word ; - assign rg_tdata3$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h7A3 ; - - // register rg_tselect - assign rg_tselect$D_IN = 32'd0 ; - assign rg_tselect$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h7A0 || - WILL_FIRE_RL_rl_reset_start ; - - // submodule csr_mie - assign csr_mie$fav_sie_write_misa = 28'd68423981 ; - assign csr_mie$fav_sie_write_wordxl = mav_csr_write_word ; - assign csr_mie$fav_write_misa = 28'd68423981 ; - assign csr_mie$fav_write_wordxl = mav_csr_write_word ; - assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mie$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h304 ; - assign csr_mie$EN_fav_sie_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h104 ; - - // submodule csr_mip - assign csr_mip$fav_sip_write_misa = 28'd68423981 ; - assign csr_mip$fav_sip_write_wordxl = mav_csr_write_word ; - assign csr_mip$fav_write_misa = 28'd68423981 ; - assign csr_mip$fav_write_wordxl = mav_csr_write_word ; - assign csr_mip$m_external_interrupt_req_req = - m_external_interrupt_req_set_not_clear ; - assign csr_mip$s_external_interrupt_req_req = - s_external_interrupt_req_set_not_clear ; - assign csr_mip$software_interrupt_req_req = - software_interrupt_req_set_not_clear ; - assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; - assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mip$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h344 ; - assign csr_mip$EN_fav_sip_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h144 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484 = - (new_priv__h10791 == 2'b11) ? - { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[31:13], - csr_trap_actions_from_priv, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[10:0] } : - { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[31:9], - csr_trap_actions_from_priv[0], - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[7:0] } ; - assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2171 = - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 && - NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104 && - NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113) ? - 4'd9 : - ((NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 && - NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104) ? - 4'd7 : - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 ? - 4'd3 : - 4'd11)) ; - assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2173 = - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 && - NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131) ? - 4'd5 : - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 ? - 4'd1 : - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2171) ; - assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2174 = - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 && - NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131 && - NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140) ? - 4'd8 : - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2173 ; - assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2176 = - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150 && - NOT_csr_mip_fv_read__94_BIT_0_060_151_OR_NOT_c_ETC___d2158) ? - 4'd4 : - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150 ? - 4'd0 : - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2174) ; - assign IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906 = - (csr_mstatus_rg_mstatus[12:11] == 2'b10) ? - 2'b01 : - csr_mstatus_rg_mstatus[12:11] ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682 = - (csr_ret_actions_from_priv == 2'b11) ? - _theResult___fst__h12935 : - _theResult___fst__h13136 ; - assign NOT_access_permitted_1_csr_addr_ULT_0xC03_701__ETC___d1821 = - (access_permitted_1_csr_addr >= 12'hC03 && - access_permitted_1_csr_addr <= 12'hC1F || - access_permitted_1_csr_addr >= 12'hB03 && - access_permitted_1_csr_addr <= 12'hB1F || - access_permitted_1_csr_addr >= 12'hC83 && - access_permitted_1_csr_addr <= 12'hC9F || - access_permitted_1_csr_addr >= 12'hB83 && - access_permitted_1_csr_addr <= 12'hB9F || - access_permitted_1_csr_addr >= 12'h323 && - access_permitted_1_csr_addr <= 12'h33F || - access_permitted_1_csr_addr == 12'h001 || - access_permitted_1_csr_addr == 12'h002 || - access_permitted_1_csr_addr == 12'h003 || - access_permitted_1_csr_addr == 12'hC00 || - access_permitted_1_csr_addr == 12'hC02 || - access_permitted_1_csr_addr == 12'hC80 || - access_permitted_1_csr_addr == 12'hC81 || - access_permitted_1_csr_addr == 12'hC82 || - access_permitted_1_csr_addr == 12'h100 || - access_permitted_1_csr_addr == 12'h102 || - access_permitted_1_csr_addr == 12'h103 || - access_permitted_1_csr_addr == 12'h104 || - access_permitted_1_csr_addr == 12'h105 || - access_permitted_1_csr_addr == 12'h106 || - access_permitted_1_csr_addr == 12'h140 || - access_permitted_1_csr_addr == 12'h141 || - access_permitted_1_csr_addr == 12'h142 || - access_permitted_1_csr_addr == 12'h143 || - access_permitted_1_csr_addr == 12'h144 || - access_permitted_1_csr_addr == 12'h180 || - access_permitted_1_csr_addr == 12'h302 || - access_permitted_1_csr_addr == 12'h303 || - access_permitted_1_csr_addr == 12'hF11 || - access_permitted_1_csr_addr == 12'hF12 || - access_permitted_1_csr_addr == 12'hF13 || - access_permitted_1_csr_addr == 12'hF14 || - access_permitted_1_csr_addr == 12'h300 || - access_permitted_1_csr_addr == 12'h301 || - access_permitted_1_csr_addr == 12'h304 || - access_permitted_1_csr_addr == 12'h305 || - access_permitted_1_csr_addr == 12'h306 || - access_permitted_1_csr_addr == 12'h340 || - access_permitted_1_csr_addr == 12'h341 || - access_permitted_1_csr_addr == 12'h342 || - access_permitted_1_csr_addr == 12'h343 || - access_permitted_1_csr_addr == 12'h344 || - access_permitted_1_csr_addr == 12'hB00 || - access_permitted_1_csr_addr == 12'hB02 || - access_permitted_1_csr_addr == 12'hB80 || - access_permitted_1_csr_addr == 12'hB82 || - access_permitted_1_csr_addr == 12'h7A0 || - access_permitted_1_csr_addr == 12'h7A1 || - access_permitted_1_csr_addr == 12'h7A2 || - access_permitted_1_csr_addr == 12'h7A3) && - access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && - (access_permitted_1_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_access_permitted_2_csr_addr_ULT_0xC03_826__ETC___d1944 = - (access_permitted_2_csr_addr >= 12'hC03 && - access_permitted_2_csr_addr <= 12'hC1F || - access_permitted_2_csr_addr >= 12'hB03 && - access_permitted_2_csr_addr <= 12'hB1F || - access_permitted_2_csr_addr >= 12'hC83 && - access_permitted_2_csr_addr <= 12'hC9F || - access_permitted_2_csr_addr >= 12'hB83 && - access_permitted_2_csr_addr <= 12'hB9F || - access_permitted_2_csr_addr >= 12'h323 && - access_permitted_2_csr_addr <= 12'h33F || - access_permitted_2_csr_addr == 12'h001 || - access_permitted_2_csr_addr == 12'h002 || - access_permitted_2_csr_addr == 12'h003 || - access_permitted_2_csr_addr == 12'hC00 || - access_permitted_2_csr_addr == 12'hC02 || - access_permitted_2_csr_addr == 12'hC80 || - access_permitted_2_csr_addr == 12'hC81 || - access_permitted_2_csr_addr == 12'hC82 || - access_permitted_2_csr_addr == 12'h100 || - access_permitted_2_csr_addr == 12'h102 || - access_permitted_2_csr_addr == 12'h103 || - access_permitted_2_csr_addr == 12'h104 || - access_permitted_2_csr_addr == 12'h105 || - access_permitted_2_csr_addr == 12'h106 || - access_permitted_2_csr_addr == 12'h140 || - access_permitted_2_csr_addr == 12'h141 || - access_permitted_2_csr_addr == 12'h142 || - access_permitted_2_csr_addr == 12'h143 || - access_permitted_2_csr_addr == 12'h144 || - access_permitted_2_csr_addr == 12'h180 || - access_permitted_2_csr_addr == 12'h302 || - access_permitted_2_csr_addr == 12'h303 || - access_permitted_2_csr_addr == 12'hF11 || - access_permitted_2_csr_addr == 12'hF12 || - access_permitted_2_csr_addr == 12'hF13 || - access_permitted_2_csr_addr == 12'hF14 || - access_permitted_2_csr_addr == 12'h300 || - access_permitted_2_csr_addr == 12'h301 || - access_permitted_2_csr_addr == 12'h304 || - access_permitted_2_csr_addr == 12'h305 || - access_permitted_2_csr_addr == 12'h306 || - access_permitted_2_csr_addr == 12'h340 || - access_permitted_2_csr_addr == 12'h341 || - access_permitted_2_csr_addr == 12'h342 || - access_permitted_2_csr_addr == 12'h343 || - access_permitted_2_csr_addr == 12'h344 || - access_permitted_2_csr_addr == 12'hB00 || - access_permitted_2_csr_addr == 12'hB02 || - access_permitted_2_csr_addr == 12'hB80 || - access_permitted_2_csr_addr == 12'hB82 || - access_permitted_2_csr_addr == 12'h7A0 || - access_permitted_2_csr_addr == 12'h7A1 || - access_permitted_2_csr_addr == 12'h7A2 || - access_permitted_2_csr_addr == 12'h7A3) && - access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && - (access_permitted_2_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_cfg_verbosity_read__148_ULE_1_149___d1150 = - cfg_verbosity > 4'd1 ; - assign NOT_csr_mip_fv_read__94_BIT_0_060_151_OR_NOT_c_ETC___d2158 = - !csr_mip$fv_read[0] || !csr_mie$fv_read[0] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 = - !csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 = - NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 && - NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104 && - NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113 && - NOT_csr_mip_fv_read__94_BIT_9_016_115_OR_NOT_c_ETC___d2122 ; - assign NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150 = - NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 && - NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131 && - NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140 && - NOT_csr_mip_fv_read__94_BIT_8_049_142_OR_NOT_c_ETC___d2149 ; - assign NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131 = - !csr_mip$fv_read[1] || !csr_mie$fv_read[1] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104 = - !csr_mip$fv_read[3] || !csr_mie$fv_read[3] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140 = - !csr_mip$fv_read[5] || !csr_mie$fv_read[5] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113 = - !csr_mip$fv_read[7] || !csr_mie$fv_read[7] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_8_049_142_OR_NOT_c_ETC___d2149 = - !csr_mip$fv_read[8] || !csr_mie$fv_read[8] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_9_016_115_OR_NOT_c_ETC___d2122 = - !csr_mip$fv_read[9] || !csr_mie$fv_read[9] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_trap_actions_nmi_499_AND_csr_trap_acti_ETC___d1606 = - !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h12648 != 4'd0 && - exc_code__h12648 != 4'd1 && - exc_code__h12648 != 4'd2 && - exc_code__h12648 != 4'd3 && - exc_code__h12648 != 4'd4 && - exc_code__h12648 != 4'd5 && - exc_code__h12648 != 4'd6 && - exc_code__h12648 != 4'd7 && - exc_code__h12648 != 4'd8 && - exc_code__h12648 != 4'd9 && - exc_code__h12648 != 4'd10 && - exc_code__h12648 != 4'd11 ; - assign NOT_mav_csr_write_csr_addr_ULT_0xB03_63_152_AN_ETC___d1159 = - !mav_csr_write_csr_addr_ULT_0xB03___d863 && - mav_csr_write_csr_addr_ULE_0xB1F___d864 || - !mav_csr_write_csr_addr_ULT_0xB83___d867 && - mav_csr_write_csr_addr_ULE_0xB9F___d868 || - !mav_csr_write_csr_addr_ULT_0x323___d871 && - mav_csr_write_csr_addr_ULE_0x33F___d872 ; - assign _theResult____h14614 = rg_mideleg[11] ? 2'b01 : 2'b11 ; - assign _theResult____h14826 = rg_mideleg[3] ? 2'b01 : 2'b11 ; - assign _theResult____h15038 = rg_mideleg[7] ? 2'b01 : 2'b11 ; - assign _theResult____h15250 = rg_mideleg[9] ? 2'b01 : 2'b11 ; - assign _theResult____h15462 = rg_mideleg[1] ? 2'b01 : 2'b11 ; - assign _theResult____h15674 = rg_mideleg[5] ? 2'b01 : 2'b11 ; - assign _theResult____h15886 = rg_mideleg[8] ? 2'b01 : 2'b11 ; - assign _theResult____h16098 = rg_mideleg[0] ? 2'b01 : 2'b11 ; - assign _theResult____h16310 = rg_mideleg[4] ? 2'b01 : 2'b11 ; - assign _theResult___fst__h10902 = - (csr_trap_actions_interrupt ? - deleg_bit___1__h10911 : - deleg_bit___1__h10926) ? - 2'b01 : - 2'b11 ; - assign _theResult___fst__h12935 = - { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[31:13], - 2'd0, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[10:0] } ; - assign _theResult___fst__h13136 = - { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[31:9], - 1'd0, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[7:0] } ; - assign b__h10989 = csr_mstatus_rg_mstatus[new_priv__h10791] ; - assign b__h12972 = - csr_mstatus_rg_mstatus[{ 3'd1, csr_ret_actions_from_priv }] ; - assign csr_mip_fv_read__94_BIT_0_060_AND_csr_mie_fv_r_ETC___d2069 = - csr_mip$fv_read[0] && csr_mie$fv_read[0] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d1993 = - csr_mip$fv_read[11] && csr_mie$fv_read[11] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d2059 = - csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d1993 || - csr_mip_fv_read__94_BIT_3_994_AND_csr_mie_fv_r_ETC___d2003 || - csr_mip_fv_read__94_BIT_7_005_AND_csr_mie_fv_r_ETC___d2014 || - csr_mip_fv_read__94_BIT_9_016_AND_csr_mie_fv_r_ETC___d2025 || - csr_mip_fv_read__94_BIT_1_027_AND_csr_mie_fv_r_ETC___d2036 || - csr_mip_fv_read__94_BIT_5_038_AND_csr_mie_fv_r_ETC___d2047 || - csr_mip_fv_read__94_BIT_8_049_AND_csr_mie_fv_r_ETC___d2058 ; - assign csr_mip_fv_read__94_BIT_1_027_AND_csr_mie_fv_r_ETC___d2036 = - csr_mip$fv_read[1] && csr_mie$fv_read[1] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_3_994_AND_csr_mie_fv_r_ETC___d2003 = - csr_mip$fv_read[3] && csr_mie$fv_read[3] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_4_071_AND_csr_mie_fv_r_ETC___d2080 = - csr_mip$fv_read[4] && csr_mie$fv_read[4] && - (interrupt_pending_cur_priv < _theResult____h16310 || - interrupt_pending_cur_priv == _theResult____h16310 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_5_038_AND_csr_mie_fv_r_ETC___d2047 = - csr_mip$fv_read[5] && csr_mie$fv_read[5] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_7_005_AND_csr_mie_fv_r_ETC___d2014 = - csr_mip$fv_read[7] && csr_mie$fv_read[7] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_8_049_AND_csr_mie_fv_r_ETC___d2058 = - csr_mip$fv_read[8] && csr_mie$fv_read[8] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_9_016_AND_csr_mie_fv_r_ETC___d2025 = - csr_mip$fv_read[9] && csr_mie$fv_read[9] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675 = - x__h12968 | mask__h12956 ; - assign csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476 = - x__h10985 | val__h10974 ; - assign csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1508 = - csr_trap_actions_interrupt && !csr_trap_actions_nmi && - CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 ; - assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1657 = - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 != 4'd0 && - exc_code__h12648 != 4'd1 && - exc_code__h12648 != 4'd2 && - exc_code__h12648 != 4'd3 && - exc_code__h12648 != 4'd4 && - exc_code__h12648 != 4'd5 && - exc_code__h12648 != 4'd6 && - exc_code__h12648 != 4'd7 && - exc_code__h12648 != 4'd8 && - exc_code__h12648 != 4'd9 && - exc_code__h12648 != 4'd11 && - exc_code__h12648 != 4'd12 && - exc_code__h12648 != 4'd13 && - exc_code__h12648 != 4'd15 ; - assign deleg_bit___1__h10911 = rg_mideleg[csr_trap_actions_exc_code] ; - assign deleg_bit___1__h10926 = rg_medeleg[csr_trap_actions_exc_code] ; - assign exc_code__h12648 = - csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; - assign exc_pc___1__h12025 = exc_pc__h11951 + vector_offset__h11952 ; - assign exc_pc__h11951 = - csr_trap_actions_nmi ? - rg_nmi_vector : - y_avValue_snd_snd__h11998 ; - assign fixed_up_val_23__h10840 = - { IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[22:17], - 2'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[14:13], - (IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[12:11] == - 2'b10) ? - 2'b01 : - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[12:11], - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[10:5], - 1'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[3:1], - 1'd0 } ; - assign fixed_up_val_23__h12869 = - { IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[22:17], - 2'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[14:13], - (IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[12:11] == - 2'b10) ? - 2'b01 : - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[12:11], - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[10:5], - 1'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[3:1], - 1'd0 } ; - assign fixed_up_val_23__h6007 = - { csr_mstatus_rg_mstatus[22:20], - mav_csr_write_word[19:18], - csr_mstatus_rg_mstatus[17], - 2'd0, - mav_csr_write_word[14:13], - IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906, - csr_mstatus_rg_mstatus[10:9], - mav_csr_write_word[8], - csr_mstatus_rg_mstatus[7:6], - mav_csr_write_word[5], - 1'd0, - csr_mstatus_rg_mstatus[3:2], - mav_csr_write_word[1], - 1'd0 } ; - assign fixed_up_val_23__h7253 = - { mav_csr_write_word[22:17], - 2'd0, - mav_csr_write_word[14:13], - (mav_csr_write_word[12:11] == 2'b10) ? - 2'b01 : - mav_csr_write_word[12:11], - mav_csr_write_word[10:5], - 1'd0, - mav_csr_write_word[3:1], - 1'd0 } ; - assign fixed_up_val_23__h9209 = - { csr_mstatus_rg_mstatus[22:17], - 2'd0, - ma_update_mstatus_fs_fs, - IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906, - csr_mstatus_rg_mstatus[10:5], - 1'd0, - csr_mstatus_rg_mstatus[3:1], - 1'd0 } ; - assign ie_from_x__h12919 = { 4'd0, csr_ret_actions_from_priv } ; - assign ie_to_x__h10890 = { 4'd0, new_priv__h10791 } ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982 = - interrupt_pending_cur_priv == _theResult____h14614 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000 = - interrupt_pending_cur_priv == _theResult____h14826 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011 = - interrupt_pending_cur_priv == _theResult____h15038 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022 = - interrupt_pending_cur_priv == _theResult____h15250 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033 = - interrupt_pending_cur_priv == _theResult____h15462 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044 = - interrupt_pending_cur_priv == _theResult____h15674 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055 = - interrupt_pending_cur_priv == _theResult____h15886 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066 = - interrupt_pending_cur_priv == _theResult____h16098 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981 = - interrupt_pending_cur_priv < _theResult____h14614 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999 = - interrupt_pending_cur_priv < _theResult____h14826 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010 = - interrupt_pending_cur_priv < _theResult____h15038 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021 = - interrupt_pending_cur_priv < _theResult____h15250 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032 = - interrupt_pending_cur_priv < _theResult____h15462 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043 = - interrupt_pending_cur_priv < _theResult____h15674 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054 = - interrupt_pending_cur_priv < _theResult____h15886 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065 = - interrupt_pending_cur_priv < _theResult____h16098 ; - assign mask__h10973 = 32'd1 << ie_to_x__h10890 ; - assign mask__h10990 = 32'd1 << pie_to_x__h10891 ; - assign mask__h12956 = 32'd1 << pie_from_x__h12920 ; - assign mask__h12973 = 32'd1 << ie_from_x__h12919 ; - assign mav_csr_write_csr_addr_ULE_0x33F___d872 = - mav_csr_write_csr_addr <= 12'h33F ; - assign mav_csr_write_csr_addr_ULE_0xB1F___d864 = - mav_csr_write_csr_addr <= 12'hB1F ; - assign mav_csr_write_csr_addr_ULE_0xB9F___d868 = - mav_csr_write_csr_addr <= 12'hB9F ; - assign mav_csr_write_csr_addr_ULT_0x323_71_OR_NOT_mav_ETC___d1145 = - (mav_csr_write_csr_addr_ULT_0x323___d871 || - !mav_csr_write_csr_addr_ULE_0x33F___d872) && - mav_csr_write_csr_addr != 12'h001 && - mav_csr_write_csr_addr != 12'h002 && - mav_csr_write_csr_addr != 12'h003 && - mav_csr_write_csr_addr != 12'h100 && - mav_csr_write_csr_addr != 12'h102 && - mav_csr_write_csr_addr != 12'h103 && - mav_csr_write_csr_addr != 12'h104 && - mav_csr_write_csr_addr != 12'h105 && - mav_csr_write_csr_addr != 12'h106 && - mav_csr_write_csr_addr != 12'h140 && - mav_csr_write_csr_addr != 12'h141 && - mav_csr_write_csr_addr != 12'h142 && - mav_csr_write_csr_addr != 12'h143 && - mav_csr_write_csr_addr != 12'h144 && - mav_csr_write_csr_addr != 12'h180 && - mav_csr_write_csr_addr != 12'h302 && - mav_csr_write_csr_addr != 12'h303 && - mav_csr_write_csr_addr != 12'hF11 && - mav_csr_write_csr_addr != 12'hF12 && - mav_csr_write_csr_addr != 12'hF13 && - mav_csr_write_csr_addr != 12'hF14 && - mav_csr_write_csr_addr != 12'h300 && - mav_csr_write_csr_addr != 12'h301 && - mav_csr_write_csr_addr != 12'h304 && - mav_csr_write_csr_addr != 12'h305 && - mav_csr_write_csr_addr != 12'h306 && - mav_csr_write_csr_addr != 12'h340 && - mav_csr_write_csr_addr != 12'h341 && - mav_csr_write_csr_addr != 12'h342 && - mav_csr_write_csr_addr != 12'h343 && - mav_csr_write_csr_addr != 12'h344 && - mav_csr_write_csr_addr != 12'hB00 && - mav_csr_write_csr_addr != 12'hB02 && - mav_csr_write_csr_addr != 12'hB80 && - mav_csr_write_csr_addr != 12'hB82 && - mav_csr_write_csr_addr != 12'h7A0 && - mav_csr_write_csr_addr != 12'h7A1 && - mav_csr_write_csr_addr != 12'h7A2 && - mav_csr_write_csr_addr != 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0x323___d871 = - mav_csr_write_csr_addr < 12'h323 ; - assign mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d1147 = - (mav_csr_write_csr_addr_ULT_0xB03___d863 || - !mav_csr_write_csr_addr_ULE_0xB1F___d864) && - (mav_csr_write_csr_addr_ULT_0xB83___d867 || - !mav_csr_write_csr_addr_ULE_0xB9F___d868) && - mav_csr_write_csr_addr_ULT_0x323_71_OR_NOT_mav_ETC___d1145 ; - assign mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 = - (mav_csr_write_csr_addr_ULT_0xB03___d863 || - !mav_csr_write_csr_addr_ULE_0xB1F___d864) && - (mav_csr_write_csr_addr_ULT_0xB83___d867 || - !mav_csr_write_csr_addr_ULE_0xB9F___d868) && - (mav_csr_write_csr_addr_ULT_0x323___d871 || - !mav_csr_write_csr_addr_ULE_0x33F___d872) ; - assign mav_csr_write_csr_addr_ULT_0xB03___d863 = - mav_csr_write_csr_addr < 12'hB03 ; - assign mav_csr_write_csr_addr_ULT_0xB83___d867 = - mav_csr_write_csr_addr < 12'hB83 ; - assign new_priv__h10791 = - csr_trap_actions_nmi ? - 2'b11 : - ((csr_trap_actions_from_priv == 2'b11) ? - csr_trap_actions_from_priv : - _theResult___fst__h10902) ; - assign pie_from_x__h12920 = { 4'd1, csr_ret_actions_from_priv } ; - assign pie_to_x__h10891 = { 4'd1, new_priv__h10791 } ; - assign result__h8591 = { 4'd0, mav_csr_write_word[27:0] } ; - assign sd__h10839 = - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[14:13] == - 2'h3 ; - assign sd__h12868 = - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[14:13] == - 2'h3 ; - assign sd__h7252 = mav_csr_write_word[14:13] == 2'h3 ; - assign sd__h9208 = ma_update_mstatus_fs_fs == 2'h3 ; - assign to_y__h13135 = - { 1'b0, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[8] } ; - assign v__h10796 = { sd__h10839, 8'd0, fixed_up_val_23__h10840 } ; - assign v__h5698 = { 27'd0, mav_csr_write_word[4:0] } ; - assign v__h5842 = { 24'd0, mav_csr_write_word[7:0] } ; - assign v__h5956 = - { sd__h7252, - 11'd0, - mav_csr_write_word[19:18], - 3'd0, - mav_csr_write_word[14:13], - 4'd0, - mav_csr_write_word[8], - 2'd0, - mav_csr_write_word[5], - 3'd0, - mav_csr_write_word[1], - 1'd0 } ; - assign v__h7081 = - { 16'd0, - mav_csr_write_word[15], - 1'd0, - mav_csr_write_word[13:12], - 2'd0, - mav_csr_write_word[9:0] } ; - assign v__h7117 = { 20'd0, mav_csr_write_word[11:0] } ; - assign v__h7758 = - { mav_csr_write_word[31:2], 1'b0, mav_csr_write_word[0] } ; - assign v__h7820 = { 29'd0, mav_csr_write_word[2:0] } ; - assign v__h7976 = - { mav_csr_write_word[31], 27'd0, mav_csr_write_word[3:0] } ; - assign val__h10974 = 32'd0 << ie_to_x__h10890 ; - assign val__h10991 = { 31'd0, b__h10989 } << pie_to_x__h10891 ; - assign val__h12974 = { 31'd0, b__h12972 } << ie_from_x__h12919 ; - assign vector_offset__h11952 = { 26'd0, csr_trap_actions_exc_code, 2'd0 } ; - assign wordxl1__h7212 = { sd__h7252, 8'd0, fixed_up_val_23__h7253 } ; - assign x__h10972 = x__h11002 | val__h10991 ; - assign x__h10985 = x__h10972 & y__h10986 ; - assign x__h11002 = csr_mstatus_rg_mstatus & y__h11003 ; - assign x__h12806 = - (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) ? - v__h10796 : - y_avValue_fst__h11925 ; - assign x__h12807 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - 27'd0, - exc_code__h12648 } ; - assign x__h12955 = x__h12985 | val__h12974 ; - assign x__h12968 = x__h12955 & y__h12969 ; - assign x__h12985 = csr_mstatus_rg_mstatus & y__h12986 ; - assign x__h8408 = { rg_minstret[63:32], mav_csr_write_word } ; - assign x__h8516 = { mav_csr_write_word, rg_minstret[31:0] } ; - assign x__h9768 = - csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1508 ? - exc_pc___1__h12025 : - exc_pc__h11951 ; - assign y__h10986 = ~mask__h10973 ; - assign y__h11003 = ~mask__h10990 ; - assign y__h12969 = ~mask__h12956 ; - assign y__h12986 = ~mask__h12973 ; - assign y_avValue_fst__h11908 = - { sd__h10839, - 11'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[19:18], - 3'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[14:13], - 4'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[8], - 2'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[5], - 3'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[1], - 1'd0 } ; - assign y_avValue_fst__h11925 = - (new_priv__h10791 == 2'b01) ? y_avValue_fst__h11908 : v__h10796 ; - assign y_avValue_snd_snd__h11998 = - { CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1, - 2'd0 } ; - always@(mav_csr_write_csr_addr or - v__h5698 or - v__h7820 or - v__h5842 or - v__h5956 or - csr_mie$fav_sie_write or - v__h7758 or - mav_csr_write_word or - v__h7976 or - csr_mip$fav_sip_write or - wordxl1__h7212 or - v__h7081 or - v__h7117 or csr_mie$fav_write or csr_mip$fav_write or result__h8591) - begin - case (mav_csr_write_csr_addr) - 12'h001: y_avValue_fst__h8976 = v__h5698; - 12'h002, 12'h306: y_avValue_fst__h8976 = v__h7820; - 12'h003: y_avValue_fst__h8976 = v__h5842; - 12'h100: y_avValue_fst__h8976 = v__h5956; - 12'h102, - 12'h103, - 12'h106, - 12'h301, - 12'h7A0, - 12'hF11, - 12'hF12, - 12'hF13, - 12'hF14: - y_avValue_fst__h8976 = 32'd0; - 12'h104: y_avValue_fst__h8976 = csr_mie$fav_sie_write; - 12'h105, 12'h305: y_avValue_fst__h8976 = v__h7758; - 12'h140, - 12'h141, - 12'h143, - 12'h180, - 12'h340, - 12'h341, - 12'h343, - 12'h7A2, - 12'h7A3, - 12'hB00, - 12'hB02, - 12'hB80, - 12'hB82: - y_avValue_fst__h8976 = mav_csr_write_word; - 12'h142, 12'h342: y_avValue_fst__h8976 = v__h7976; - 12'h144: y_avValue_fst__h8976 = csr_mip$fav_sip_write; - 12'h300: y_avValue_fst__h8976 = wordxl1__h7212; - 12'h302: y_avValue_fst__h8976 = v__h7081; - 12'h303: y_avValue_fst__h8976 = v__h7117; - 12'h304: y_avValue_fst__h8976 = csr_mie$fav_write; - 12'h344: y_avValue_fst__h8976 = csr_mip$fav_write; - 12'h7A1: y_avValue_fst__h8976 = result__h8591; - default: y_avValue_fst__h8976 = 32'd0; - endcase - end - always@(new_priv__h10791 or rg_mtvec or rg_stvec) - begin - case (new_priv__h10791) - 2'b01: - CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1 = - rg_stvec[30:1]; - 2'b11: - CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1 = - rg_mtvec[30:1]; - default: CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1 = - rg_mtvec[30:1]; - endcase - end - always@(new_priv__h10791 or rg_mtvec or rg_stvec) - begin - case (new_priv__h10791) - 2'b01: - CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_stvec[0]; - 2'b11: - CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_mtvec[0]; - default: CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_mtvec[0]; - endcase - end - always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) - begin - case (interrupt_pending_cur_priv) - 2'b0: - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990 = - csr_mstatus_rg_mstatus[0]; - 2'b01: - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990 = - csr_mstatus_rg_mstatus[1]; - default: IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990 = - interrupt_pending_cur_priv == 2'b11 && - csr_mstatus_rg_mstatus[3]; - endcase - end - always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) - begin - case (interrupt_pending_cur_priv) - 2'b0: - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093 = - !csr_mstatus_rg_mstatus[0]; - 2'b01: - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093 = - !csr_mstatus_rg_mstatus[1]; - default: IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093 = - interrupt_pending_cur_priv != 2'b11 || - !csr_mstatus_rg_mstatus[3]; - endcase - end - always@(read_csr_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_csr_addr) - 12'h001: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 27'd0, rg_fflags }; - 12'h002: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 29'd0, rg_frm }; - 12'h003: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 24'd0, rg_frm, rg_fflags }; - 12'h100: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = 32'd0; - 12'h104: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - csr_mie$fv_sie_read; - 12'h105: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { rg_stvec[30:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_sscratch; - 12'h141: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = rg_sepc; - 12'h142: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { rg_scause[4], 27'd0, rg_scause[3:0] }; - 12'h143: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_stval; - 12'h144: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - csr_mip$fv_sip_read; - 12'h180: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = rg_satp; - 12'h300: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - 32'd1075056941; - 12'h302: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 16'd0, rg_medeleg }; - 12'h303: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 20'd0, rg_mideleg }; - 12'h304: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_mscratch; - 12'h341: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = rg_mepc; - 12'h342: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_mtval; - 12'h344: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_tselect; - 12'h7A1: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_tdata1; - 12'h7A2: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_minstret[63:32]; - default: IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_tdata3; - endcase - end - always@(read_csr_port2_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_port2_csr_addr) - 12'h001: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 27'd0, rg_fflags }; - 12'h002: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 29'd0, rg_frm }; - 12'h003: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 24'd0, rg_frm, rg_fflags }; - 12'h100: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = 32'd0; - 12'h104: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - csr_mie$fv_sie_read; - 12'h105: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { rg_stvec[30:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_sscratch; - 12'h141: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = rg_sepc; - 12'h142: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { rg_scause[4], 27'd0, rg_scause[3:0] }; - 12'h143: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_stval; - 12'h144: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - csr_mip$fv_sip_read; - 12'h180: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = rg_satp; - 12'h300: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - 32'd1075056941; - 12'h302: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 16'd0, rg_medeleg }; - 12'h303: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 20'd0, rg_mideleg }; - 12'h304: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_mscratch; - 12'h341: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = rg_mepc; - 12'h342: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_mtval; - 12'h344: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_tselect; - 12'h7A1: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_tdata1; - 12'h7A2: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_minstret[63:32]; - default: IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_tdata3; - endcase - end - always@(mav_read_csr_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (mav_read_csr_csr_addr) - 12'h001: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 27'd0, rg_fflags }; - 12'h002: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 29'd0, rg_frm }; - 12'h003: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 24'd0, rg_frm, rg_fflags }; - 12'h100: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = 32'd0; - 12'h104: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - csr_mie$fv_sie_read; - 12'h105: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { rg_stvec[30:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_sscratch; - 12'h141: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = rg_sepc; - 12'h142: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { rg_scause[4], 27'd0, rg_scause[3:0] }; - 12'h143: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_stval; - 12'h144: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - csr_mip$fv_sip_read; - 12'h180: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = rg_satp; - 12'h300: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - 32'd1075056941; - 12'h302: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 16'd0, rg_medeleg }; - 12'h303: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 20'd0, rg_mideleg }; - 12'h304: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - csr_mie$fv_read; - 12'h305: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_mscratch; - 12'h341: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = rg_mepc; - 12'h342: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_mtval; - 12'h344: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - csr_mip$fv_read; - 12'h7A0: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_tselect; - 12'h7A1: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_tdata1; - 12'h7A2: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_minstret[63:32]; - default: IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_tdata3; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 32'd8192; - rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (csr_mstatus_rg_mstatus$EN) - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY - csr_mstatus_rg_mstatus$D_IN; - if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; - if (rg_minstret$EN) - rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; - if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; - if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; - if (rg_dscratch0$EN) - rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; - if (rg_dscratch1$EN) - rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; - if (rg_fflags$EN) rg_fflags <= `BSV_ASSIGNMENT_DELAY rg_fflags$D_IN; - if (rg_frm$EN) rg_frm <= `BSV_ASSIGNMENT_DELAY rg_frm$D_IN; - if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; - if (rg_mcounteren$EN) - rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; - if (rg_medeleg$EN) rg_medeleg <= `BSV_ASSIGNMENT_DELAY rg_medeleg$D_IN; - if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; - if (rg_mideleg$EN) rg_mideleg <= `BSV_ASSIGNMENT_DELAY rg_mideleg$D_IN; - if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; - if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; - if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; - if (rg_nmi_vector$EN) - rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN; - if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; - if (rg_scause$EN) rg_scause <= `BSV_ASSIGNMENT_DELAY rg_scause$D_IN; - if (rg_sepc$EN) rg_sepc <= `BSV_ASSIGNMENT_DELAY rg_sepc$D_IN; - if (rg_sscratch$EN) rg_sscratch <= `BSV_ASSIGNMENT_DELAY rg_sscratch$D_IN; - if (rg_stval$EN) rg_stval <= `BSV_ASSIGNMENT_DELAY rg_stval$D_IN; - if (rg_stvec$EN) rg_stvec <= `BSV_ASSIGNMENT_DELAY rg_stvec$D_IN; - if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; - if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; - if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; - if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - csr_mstatus_rg_mstatus = 32'hAAAAAAAA; - rg_dcsr = 32'hAAAAAAAA; - rg_dpc = 32'hAAAAAAAA; - rg_dscratch0 = 32'hAAAAAAAA; - rg_dscratch1 = 32'hAAAAAAAA; - rg_fflags = 5'h0A; - rg_frm = 3'h2; - rg_mcause = 5'h0A; - rg_mcounteren = 3'h2; - rg_mcycle = 64'hAAAAAAAAAAAAAAAA; - rg_medeleg = 16'hAAAA; - rg_mepc = 32'hAAAAAAAA; - rg_mideleg = 12'hAAA; - rg_minstret = 64'hAAAAAAAAAAAAAAAA; - rg_mscratch = 32'hAAAAAAAA; - rg_mtval = 32'hAAAAAAAA; - rg_mtvec = 31'h2AAAAAAA; - rg_nmi = 1'h0; - rg_nmi_vector = 32'hAAAAAAAA; - rg_satp = 32'hAAAAAAAA; - rg_scause = 5'h0A; - rg_sepc = 32'hAAAAAAAA; - rg_sscratch = 32'hAAAAAAAA; - rg_state = 1'h0; - rg_stval = 32'hAAAAAAAA; - rg_stvec = 31'h2AAAAAAA; - rg_tdata1 = 32'hAAAAAAAA; - rg_tdata2 = 32'hAAAAAAAA; - rg_tdata3 = 32'hAAAAAAAA; - rg_tselect = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) - $display("sstatus = 0x%0h", - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("sip = 0x%0h", csr_mip$fv_sip_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("sie = 0x%0h", csr_mie$fv_sie_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d1147 && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", - rg_mcycle, - mav_csr_write_csr_addr, - mav_csr_write_word); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" priv %0d: ", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" edeleg: 0x%0h", 16'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ideleg: 0x%0h", 12'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] != 4'd0 && - rg_scause[3:0] != 4'd1 && - rg_scause[3:0] != 4'd2 && - rg_scause[3:0] != 4'd3 && - rg_scause[3:0] != 4'd4 && - rg_scause[3:0] != 4'd5 && - rg_scause[3:0] != 4'd6 && - rg_scause[3:0] != 4'd7 && - rg_scause[3:0] != 4'd8 && - rg_scause[3:0] != 4'd9 && - rg_scause[3:0] != 4'd10 && - rg_scause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_scause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] != 4'd0 && - rg_scause[3:0] != 4'd1 && - rg_scause[3:0] != 4'd2 && - rg_scause[3:0] != 4'd3 && - rg_scause[3:0] != 4'd4 && - rg_scause[3:0] != 4'd5 && - rg_scause[3:0] != 4'd6 && - rg_scause[3:0] != 4'd7 && - rg_scause[3:0] != 4'd8 && - rg_scause[3:0] != 4'd9 && - rg_scause[3:0] != 4'd11 && - rg_scause[3:0] != 4'd12 && - rg_scause[3:0] != 4'd13 && - rg_scause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_scause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" status: 0x%0h", - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tvec: 0x%0h", { rg_stvec[30:1], 1'b0, rg_stvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" epc: 0x%0h", rg_sepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tval: 0x%0h", rg_stval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" priv %0d: ", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" edeleg: 0x%0h", rg_medeleg); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ideleg: 0x%0h", rg_mideleg); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd10 && - rg_mcause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd11 && - rg_mcause[3:0] != 4'd12 && - rg_mcause[3:0] != 4'd13 && - rg_mcause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" status: 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tvec: 0x%0h", { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" epc: 0x%0h", rg_mepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tval: 0x%0h", rg_mtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" Return: new pc 0x%0h ", x__h9768); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" new mstatus:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write("MStatus{", - "sd:%0d", - x__h12806[14:13] == 2'h3 || x__h12806[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tsr:%0d", x__h12806[22]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tw:%0d", x__h12806[21]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tvm:%0d", x__h12806[20]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" mxr:%0d", x__h12806[19]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" sum:%0d", x__h12806[18]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" mprv:%0d", x__h12806[17]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" xs:%0d", x__h12806[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" fs:%0d", x__h12806[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" mpp:%0d", x__h12806[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" spp:%0d", x__h12806[8]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" pies:%0d_%0d%0d", x__h12806[7], x__h12806[5], x__h12806[4]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ies:%0d_%0d%0d", x__h12806[3], x__h12806[1], x__h12806[0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" new xcause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - NOT_csr_trap_actions_nmi_499_AND_csr_trap_acti_ETC___d1606) - $write("unknown interrupt Exc_Code %d", exc_code__h12648); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1657) - $write("unknown trap Exc_Code %d", exc_code__h12648); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" new priv %0d", new_priv__h10791); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", - rg_mcycle, - m_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", - rg_mcycle, - s_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: CSR_RegFile: timer_interrupt_req: %x", - rg_mcycle, - timer_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: CSR_RegFile: software_interrupt_req: %x", - rg_mcycle, - software_interrupt_req_set_not_clear); - end - // synopsys translate_on -endmodule // mkCSR_RegFile - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCore.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCore.v deleted file mode 100644 index 5178628a..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCore.v +++ /dev/null @@ -1,2499 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// cpu_reset_server_response_get O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg -// cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg -// cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg -// cpu_imem_master_bready O 1 -// cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg -// cpu_imem_master_rready O 1 -// cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg -// cpu_dmem_master_awaddr O 64 reg -// cpu_dmem_master_awlen O 8 reg -// cpu_dmem_master_awsize O 3 reg -// cpu_dmem_master_awburst O 2 reg -// cpu_dmem_master_awlock O 1 reg -// cpu_dmem_master_awcache O 4 reg -// cpu_dmem_master_awprot O 3 reg -// cpu_dmem_master_awqos O 4 reg -// cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg -// cpu_dmem_master_wdata O 64 reg -// cpu_dmem_master_wstrb O 8 reg -// cpu_dmem_master_wlast O 1 reg -// cpu_dmem_master_bready O 1 reg -// cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg -// cpu_dmem_master_araddr O 64 reg -// cpu_dmem_master_arlen O 8 reg -// cpu_dmem_master_arsize O 3 reg -// cpu_dmem_master_arburst O 2 reg -// cpu_dmem_master_arlock O 1 reg -// cpu_dmem_master_arcache O 4 reg -// cpu_dmem_master_arprot O 3 reg -// cpu_dmem_master_arqos O 4 reg -// cpu_dmem_master_arregion O 4 reg -// cpu_dmem_master_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// cpu_reset_server_request_put I 1 reg -// cpu_imem_master_awready I 1 -// cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg -// cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg -// cpu_dmem_master_awready I 1 -// cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg -// cpu_dmem_master_bresp I 2 reg -// cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg -// cpu_dmem_master_rdata I 64 reg -// cpu_dmem_master_rresp I 2 reg -// cpu_dmem_master_rlast I 1 reg -// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// nmi_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (cpu_imem_master_awready, -// cpu_imem_master_wready, -// cpu_imem_master_arready) -> cpu_imem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCore(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - cpu_reset_server_request_put, - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, - - cpu_imem_master_awvalid, - - cpu_imem_master_awid, - - cpu_imem_master_awaddr, - - cpu_imem_master_awlen, - - cpu_imem_master_awsize, - - cpu_imem_master_awburst, - - cpu_imem_master_awlock, - - cpu_imem_master_awcache, - - cpu_imem_master_awprot, - - cpu_imem_master_awqos, - - cpu_imem_master_awregion, - - cpu_imem_master_awready, - - cpu_imem_master_wvalid, - - cpu_imem_master_wid, - - cpu_imem_master_wdata, - - cpu_imem_master_wstrb, - - cpu_imem_master_wlast, - - cpu_imem_master_wready, - - cpu_imem_master_bvalid, - cpu_imem_master_bid, - cpu_imem_master_bresp, - - cpu_imem_master_bready, - - cpu_imem_master_arvalid, - - cpu_imem_master_arid, - - cpu_imem_master_araddr, - - cpu_imem_master_arlen, - - cpu_imem_master_arsize, - - cpu_imem_master_arburst, - - cpu_imem_master_arlock, - - cpu_imem_master_arcache, - - cpu_imem_master_arprot, - - cpu_imem_master_arqos, - - cpu_imem_master_arregion, - - cpu_imem_master_arready, - - cpu_imem_master_rvalid, - cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast, - - cpu_imem_master_rready, - - cpu_dmem_master_awvalid, - - cpu_dmem_master_awid, - - cpu_dmem_master_awaddr, - - cpu_dmem_master_awlen, - - cpu_dmem_master_awsize, - - cpu_dmem_master_awburst, - - cpu_dmem_master_awlock, - - cpu_dmem_master_awcache, - - cpu_dmem_master_awprot, - - cpu_dmem_master_awqos, - - cpu_dmem_master_awregion, - - cpu_dmem_master_awready, - - cpu_dmem_master_wvalid, - - cpu_dmem_master_wid, - - cpu_dmem_master_wdata, - - cpu_dmem_master_wstrb, - - cpu_dmem_master_wlast, - - cpu_dmem_master_wready, - - cpu_dmem_master_bvalid, - cpu_dmem_master_bid, - cpu_dmem_master_bresp, - - cpu_dmem_master_bready, - - cpu_dmem_master_arvalid, - - cpu_dmem_master_arid, - - cpu_dmem_master_araddr, - - cpu_dmem_master_arlen, - - cpu_dmem_master_arsize, - - cpu_dmem_master_arburst, - - cpu_dmem_master_arlock, - - cpu_dmem_master_arcache, - - cpu_dmem_master_arprot, - - cpu_dmem_master_arqos, - - cpu_dmem_master_arregion, - - cpu_dmem_master_arready, - - cpu_dmem_master_rvalid, - cpu_dmem_master_rid, - cpu_dmem_master_rdata, - cpu_dmem_master_rresp, - cpu_dmem_master_rlast, - - cpu_dmem_master_rready, - - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - - nmi_req_set_not_clear); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method cpu_reset_server_request_put - input cpu_reset_server_request_put; - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // actionvalue method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; - - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; - - // value method cpu_imem_master_m_awaddr - output [63 : 0] cpu_imem_master_awaddr; - - // value method cpu_imem_master_m_awlen - output [7 : 0] cpu_imem_master_awlen; - - // value method cpu_imem_master_m_awsize - output [2 : 0] cpu_imem_master_awsize; - - // value method cpu_imem_master_m_awburst - output [1 : 0] cpu_imem_master_awburst; - - // value method cpu_imem_master_m_awlock - output cpu_imem_master_awlock; - - // value method cpu_imem_master_m_awcache - output [3 : 0] cpu_imem_master_awcache; - - // value method cpu_imem_master_m_awprot - output [2 : 0] cpu_imem_master_awprot; - - // value method cpu_imem_master_m_awqos - output [3 : 0] cpu_imem_master_awqos; - - // value method cpu_imem_master_m_awregion - output [3 : 0] cpu_imem_master_awregion; - - // value method cpu_imem_master_m_awuser - - // action method cpu_imem_master_m_awready - input cpu_imem_master_awready; - - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; - - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - - // value method cpu_imem_master_m_wdata - output [63 : 0] cpu_imem_master_wdata; - - // value method cpu_imem_master_m_wstrb - output [7 : 0] cpu_imem_master_wstrb; - - // value method cpu_imem_master_m_wlast - output cpu_imem_master_wlast; - - // value method cpu_imem_master_m_wuser - - // action method cpu_imem_master_m_wready - input cpu_imem_master_wready; - - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; - input [1 : 0] cpu_imem_master_bresp; - - // value method cpu_imem_master_m_bready - output cpu_imem_master_bready; - - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; - - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; - - // value method cpu_imem_master_m_araddr - output [63 : 0] cpu_imem_master_araddr; - - // value method cpu_imem_master_m_arlen - output [7 : 0] cpu_imem_master_arlen; - - // value method cpu_imem_master_m_arsize - output [2 : 0] cpu_imem_master_arsize; - - // value method cpu_imem_master_m_arburst - output [1 : 0] cpu_imem_master_arburst; - - // value method cpu_imem_master_m_arlock - output cpu_imem_master_arlock; - - // value method cpu_imem_master_m_arcache - output [3 : 0] cpu_imem_master_arcache; - - // value method cpu_imem_master_m_arprot - output [2 : 0] cpu_imem_master_arprot; - - // value method cpu_imem_master_m_arqos - output [3 : 0] cpu_imem_master_arqos; - - // value method cpu_imem_master_m_arregion - output [3 : 0] cpu_imem_master_arregion; - - // value method cpu_imem_master_m_aruser - - // action method cpu_imem_master_m_arready - input cpu_imem_master_arready; - - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; - input [63 : 0] cpu_imem_master_rdata; - input [1 : 0] cpu_imem_master_rresp; - input cpu_imem_master_rlast; - - // value method cpu_imem_master_m_rready - output cpu_imem_master_rready; - - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; - - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; - - // value method cpu_dmem_master_m_awaddr - output [63 : 0] cpu_dmem_master_awaddr; - - // value method cpu_dmem_master_m_awlen - output [7 : 0] cpu_dmem_master_awlen; - - // value method cpu_dmem_master_m_awsize - output [2 : 0] cpu_dmem_master_awsize; - - // value method cpu_dmem_master_m_awburst - output [1 : 0] cpu_dmem_master_awburst; - - // value method cpu_dmem_master_m_awlock - output cpu_dmem_master_awlock; - - // value method cpu_dmem_master_m_awcache - output [3 : 0] cpu_dmem_master_awcache; - - // value method cpu_dmem_master_m_awprot - output [2 : 0] cpu_dmem_master_awprot; - - // value method cpu_dmem_master_m_awqos - output [3 : 0] cpu_dmem_master_awqos; - - // value method cpu_dmem_master_m_awregion - output [3 : 0] cpu_dmem_master_awregion; - - // value method cpu_dmem_master_m_awuser - - // action method cpu_dmem_master_m_awready - input cpu_dmem_master_awready; - - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; - - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - - // value method cpu_dmem_master_m_wdata - output [63 : 0] cpu_dmem_master_wdata; - - // value method cpu_dmem_master_m_wstrb - output [7 : 0] cpu_dmem_master_wstrb; - - // value method cpu_dmem_master_m_wlast - output cpu_dmem_master_wlast; - - // value method cpu_dmem_master_m_wuser - - // action method cpu_dmem_master_m_wready - input cpu_dmem_master_wready; - - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; - input [1 : 0] cpu_dmem_master_bresp; - - // value method cpu_dmem_master_m_bready - output cpu_dmem_master_bready; - - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; - - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; - - // value method cpu_dmem_master_m_araddr - output [63 : 0] cpu_dmem_master_araddr; - - // value method cpu_dmem_master_m_arlen - output [7 : 0] cpu_dmem_master_arlen; - - // value method cpu_dmem_master_m_arsize - output [2 : 0] cpu_dmem_master_arsize; - - // value method cpu_dmem_master_m_arburst - output [1 : 0] cpu_dmem_master_arburst; - - // value method cpu_dmem_master_m_arlock - output cpu_dmem_master_arlock; - - // value method cpu_dmem_master_m_arcache - output [3 : 0] cpu_dmem_master_arcache; - - // value method cpu_dmem_master_m_arprot - output [2 : 0] cpu_dmem_master_arprot; - - // value method cpu_dmem_master_m_arqos - output [3 : 0] cpu_dmem_master_arqos; - - // value method cpu_dmem_master_m_arregion - output [3 : 0] cpu_dmem_master_arregion; - - // value method cpu_dmem_master_m_aruser - - // action method cpu_dmem_master_m_arready - input cpu_dmem_master_arready; - - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; - input [63 : 0] cpu_dmem_master_rdata; - input [1 : 0] cpu_dmem_master_rresp; - input cpu_dmem_master_rlast; - - // value method cpu_dmem_master_m_rready - output cpu_dmem_master_rready; - - // action method core_external_interrupt_sources_0_m_interrupt_req - input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_1_m_interrupt_req - input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_2_m_interrupt_req - input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_3_m_interrupt_req - input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_4_m_interrupt_req - input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_5_m_interrupt_req - input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_6_m_interrupt_req - input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_7_m_interrupt_req - input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_8_m_interrupt_req - input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_9_m_interrupt_req - input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_10_m_interrupt_req - input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_11_m_interrupt_req - input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_12_m_interrupt_req - input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_13_m_interrupt_req - input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_14_m_interrupt_req - input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_15_m_interrupt_req - input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // signals for module outputs - wire [63 : 0] cpu_dmem_master_araddr, - cpu_dmem_master_awaddr, - cpu_dmem_master_wdata, - cpu_imem_master_araddr, - cpu_imem_master_awaddr, - cpu_imem_master_wdata; - wire [7 : 0] cpu_dmem_master_arlen, - cpu_dmem_master_awlen, - cpu_dmem_master_wstrb, - cpu_imem_master_arlen, - cpu_imem_master_awlen, - cpu_imem_master_wstrb; - wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, - cpu_dmem_master_arqos, - cpu_dmem_master_arregion, - cpu_dmem_master_awcache, - cpu_dmem_master_awid, - cpu_dmem_master_awqos, - cpu_dmem_master_awregion, - cpu_dmem_master_wid, - cpu_imem_master_arcache, - cpu_imem_master_arid, - cpu_imem_master_arqos, - cpu_imem_master_arregion, - cpu_imem_master_awcache, - cpu_imem_master_awid, - cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; - wire [2 : 0] cpu_dmem_master_arprot, - cpu_dmem_master_arsize, - cpu_dmem_master_awprot, - cpu_dmem_master_awsize, - cpu_imem_master_arprot, - cpu_imem_master_arsize, - cpu_imem_master_awprot, - cpu_imem_master_awsize; - wire [1 : 0] cpu_dmem_master_arburst, - cpu_dmem_master_awburst, - cpu_imem_master_arburst, - cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_set_verbosity, - cpu_dmem_master_arlock, - cpu_dmem_master_arvalid, - cpu_dmem_master_awlock, - cpu_dmem_master_awvalid, - cpu_dmem_master_bready, - cpu_dmem_master_rready, - cpu_dmem_master_wlast, - cpu_dmem_master_wvalid, - cpu_imem_master_arlock, - cpu_imem_master_arvalid, - cpu_imem_master_awlock, - cpu_imem_master_awvalid, - cpu_imem_master_bready, - cpu_imem_master_rready, - cpu_imem_master_wlast, - cpu_imem_master_wvalid, - cpu_reset_server_response_get; - - // ports of submodule cpu - wire [63 : 0] cpu$dmem_master_araddr, - cpu$dmem_master_awaddr, - cpu$dmem_master_rdata, - cpu$dmem_master_wdata, - cpu$imem_master_araddr, - cpu$imem_master_awaddr, - cpu$imem_master_rdata, - cpu$imem_master_wdata, - cpu$set_verbosity_logdelay; - wire [7 : 0] cpu$dmem_master_arlen, - cpu$dmem_master_awlen, - cpu$dmem_master_wstrb, - cpu$imem_master_arlen, - cpu$imem_master_awlen, - cpu$imem_master_wstrb; - wire [3 : 0] cpu$dmem_master_arcache, - cpu$dmem_master_arid, - cpu$dmem_master_arqos, - cpu$dmem_master_arregion, - cpu$dmem_master_awcache, - cpu$dmem_master_awid, - cpu$dmem_master_awqos, - cpu$dmem_master_awregion, - cpu$dmem_master_bid, - cpu$dmem_master_rid, - cpu$dmem_master_wid, - cpu$imem_master_arcache, - cpu$imem_master_arid, - cpu$imem_master_arqos, - cpu$imem_master_arregion, - cpu$imem_master_awcache, - cpu$imem_master_awid, - cpu$imem_master_awqos, - cpu$imem_master_awregion, - cpu$imem_master_bid, - cpu$imem_master_rid, - cpu$imem_master_wid, - cpu$set_verbosity_verbosity; - wire [2 : 0] cpu$dmem_master_arprot, - cpu$dmem_master_arsize, - cpu$dmem_master_awprot, - cpu$dmem_master_awsize, - cpu$imem_master_arprot, - cpu$imem_master_arsize, - cpu$imem_master_awprot, - cpu$imem_master_awsize; - wire [1 : 0] cpu$dmem_master_arburst, - cpu$dmem_master_awburst, - cpu$dmem_master_bresp, - cpu$dmem_master_rresp, - cpu$imem_master_arburst, - cpu$imem_master_awburst, - cpu$imem_master_bresp, - cpu$imem_master_rresp; - wire cpu$EN_hart0_server_reset_request_put, - cpu$EN_hart0_server_reset_response_get, - cpu$EN_set_verbosity, - cpu$RDY_hart0_server_reset_request_put, - cpu$RDY_hart0_server_reset_response_get, - cpu$dmem_master_arlock, - cpu$dmem_master_arready, - cpu$dmem_master_arvalid, - cpu$dmem_master_awlock, - cpu$dmem_master_awready, - cpu$dmem_master_awvalid, - cpu$dmem_master_bready, - cpu$dmem_master_bvalid, - cpu$dmem_master_rlast, - cpu$dmem_master_rready, - cpu$dmem_master_rvalid, - cpu$dmem_master_wlast, - cpu$dmem_master_wready, - cpu$dmem_master_wvalid, - cpu$hart0_server_reset_request_put, - cpu$hart0_server_reset_response_get, - cpu$imem_master_arlock, - cpu$imem_master_arready, - cpu$imem_master_arvalid, - cpu$imem_master_awlock, - cpu$imem_master_awready, - cpu$imem_master_awvalid, - cpu$imem_master_bready, - cpu$imem_master_bvalid, - cpu$imem_master_rlast, - cpu$imem_master_rready, - cpu$imem_master_rvalid, - cpu$imem_master_wlast, - cpu$imem_master_wready, - cpu$imem_master_wvalid, - cpu$m_external_interrupt_req_set_not_clear, - cpu$nmi_req_set_not_clear, - cpu$s_external_interrupt_req_set_not_clear, - cpu$software_interrupt_req_set_not_clear, - cpu$timer_interrupt_req_set_not_clear; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_araddr, - fabric_2x3$v_to_slaves_2_awaddr, - fabric_2x3$v_to_slaves_2_rdata, - fabric_2x3$v_to_slaves_2_wdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb, - fabric_2x3$v_to_slaves_2_arlen, - fabric_2x3$v_to_slaves_2_awlen, - fabric_2x3$v_to_slaves_2_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_wid, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, - fabric_2x3$v_to_slaves_2_arcache, - fabric_2x3$v_to_slaves_2_arid, - fabric_2x3$v_to_slaves_2_arqos, - fabric_2x3$v_to_slaves_2_arregion, - fabric_2x3$v_to_slaves_2_awcache, - fabric_2x3$v_to_slaves_2_awid, - fabric_2x3$v_to_slaves_2_awqos, - fabric_2x3$v_to_slaves_2_awregion, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize, - fabric_2x3$v_to_slaves_2_arprot, - fabric_2x3$v_to_slaves_2_arsize, - fabric_2x3$v_to_slaves_2_awprot, - fabric_2x3$v_to_slaves_2_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_arburst, - fabric_2x3$v_to_slaves_2_awburst, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arlock, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_arvalid, - fabric_2x3$v_to_slaves_2_awlock, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_awvalid, - fabric_2x3$v_to_slaves_2_bready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rready, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wlast, - fabric_2x3$v_to_slaves_2_wready, - fabric_2x3$v_to_slaves_2_wvalid; - - // ports of submodule near_mem_io - wire [63 : 0] near_mem_io$axi4_slave_araddr, - near_mem_io$axi4_slave_awaddr, - near_mem_io$axi4_slave_rdata, - near_mem_io$axi4_slave_wdata, - near_mem_io$set_addr_map_addr_base, - near_mem_io$set_addr_map_addr_lim; - wire [7 : 0] near_mem_io$axi4_slave_arlen, - near_mem_io$axi4_slave_awlen, - near_mem_io$axi4_slave_wstrb; - wire [3 : 0] near_mem_io$axi4_slave_arcache, - near_mem_io$axi4_slave_arid, - near_mem_io$axi4_slave_arqos, - near_mem_io$axi4_slave_arregion, - near_mem_io$axi4_slave_awcache, - near_mem_io$axi4_slave_awid, - near_mem_io$axi4_slave_awqos, - near_mem_io$axi4_slave_awregion, - near_mem_io$axi4_slave_bid, - near_mem_io$axi4_slave_rid, - near_mem_io$axi4_slave_wid; - wire [2 : 0] near_mem_io$axi4_slave_arprot, - near_mem_io$axi4_slave_arsize, - near_mem_io$axi4_slave_awprot, - near_mem_io$axi4_slave_awsize; - wire [1 : 0] near_mem_io$axi4_slave_arburst, - near_mem_io$axi4_slave_awburst, - near_mem_io$axi4_slave_bresp, - near_mem_io$axi4_slave_rresp; - wire near_mem_io$EN_get_sw_interrupt_req_get, - near_mem_io$EN_get_timer_interrupt_req_get, - near_mem_io$EN_server_reset_request_put, - near_mem_io$EN_server_reset_response_get, - near_mem_io$EN_set_addr_map, - near_mem_io$RDY_get_sw_interrupt_req_get, - near_mem_io$RDY_get_timer_interrupt_req_get, - near_mem_io$RDY_server_reset_request_put, - near_mem_io$RDY_server_reset_response_get, - near_mem_io$axi4_slave_arlock, - near_mem_io$axi4_slave_arready, - near_mem_io$axi4_slave_arvalid, - near_mem_io$axi4_slave_awlock, - near_mem_io$axi4_slave_awready, - near_mem_io$axi4_slave_awvalid, - near_mem_io$axi4_slave_bready, - near_mem_io$axi4_slave_bvalid, - near_mem_io$axi4_slave_rlast, - near_mem_io$axi4_slave_rready, - near_mem_io$axi4_slave_rvalid, - near_mem_io$axi4_slave_wlast, - near_mem_io$axi4_slave_wready, - near_mem_io$axi4_slave_wvalid, - near_mem_io$get_sw_interrupt_req_get, - near_mem_io$get_timer_interrupt_req_get; - - // ports of submodule plic - wire [63 : 0] plic$axi4_slave_araddr, - plic$axi4_slave_awaddr, - plic$axi4_slave_rdata, - plic$axi4_slave_wdata, - plic$set_addr_map_addr_base, - plic$set_addr_map_addr_lim; - wire [7 : 0] plic$axi4_slave_arlen, - plic$axi4_slave_awlen, - plic$axi4_slave_wstrb; - wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, - plic$axi4_slave_arqos, - plic$axi4_slave_arregion, - plic$axi4_slave_awcache, - plic$axi4_slave_awid, - plic$axi4_slave_awqos, - plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, - plic$axi4_slave_wid, - plic$set_verbosity_verbosity; - wire [2 : 0] plic$axi4_slave_arprot, - plic$axi4_slave_arsize, - plic$axi4_slave_awprot, - plic$axi4_slave_awsize; - wire [1 : 0] plic$axi4_slave_arburst, - plic$axi4_slave_awburst, - plic$axi4_slave_bresp, - plic$axi4_slave_rresp; - wire plic$EN_server_reset_request_put, - plic$EN_server_reset_response_get, - plic$EN_set_addr_map, - plic$EN_set_verbosity, - plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, - plic$axi4_slave_arlock, - plic$axi4_slave_arready, - plic$axi4_slave_arvalid, - plic$axi4_slave_awlock, - plic$axi4_slave_awready, - plic$axi4_slave_awvalid, - plic$axi4_slave_bready, - plic$axi4_slave_bvalid, - plic$axi4_slave_rlast, - plic$axi4_slave_rready, - plic$axi4_slave_rvalid, - plic$axi4_slave_wlast, - plic$axi4_slave_wready, - plic$axi4_slave_wvalid, - plic$v_sources_0_m_interrupt_req_set_not_clear, - plic$v_sources_10_m_interrupt_req_set_not_clear, - plic$v_sources_11_m_interrupt_req_set_not_clear, - plic$v_sources_12_m_interrupt_req_set_not_clear, - plic$v_sources_13_m_interrupt_req_set_not_clear, - plic$v_sources_14_m_interrupt_req_set_not_clear, - plic$v_sources_15_m_interrupt_req_set_not_clear, - plic$v_sources_1_m_interrupt_req_set_not_clear, - plic$v_sources_2_m_interrupt_req_set_not_clear, - plic$v_sources_3_m_interrupt_req_set_not_clear, - plic$v_sources_4_m_interrupt_req_set_not_clear, - plic$v_sources_5_m_interrupt_req_set_not_clear, - plic$v_sources_6_m_interrupt_req_set_not_clear, - plic$v_sources_7_m_interrupt_req_set_not_clear, - plic$v_sources_8_m_interrupt_req_set_not_clear, - plic$v_sources_9_m_interrupt_req_set_not_clear, - plic$v_targets_0_m_eip, - plic$v_targets_1_m_eip; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_sw_interrupts, - CAN_FIRE_RL_rl_relay_timer_interrupts, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_nmi_req, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_sw_interrupts, - WILL_FIRE_RL_rl_relay_timer_interrupts, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_nmi_req, - WILL_FIRE_set_verbosity; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4310; - reg [31 : 0] v__h4551; - reg [31 : 0] v__h4304; - reg [31 : 0] v__h4545; - // synopsys translate_on - - // remaining internal signals - wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // actionvalue method cpu_reset_server_response_get - assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ; - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; - - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - - // value method cpu_imem_master_m_awid - assign cpu_imem_master_awid = cpu$imem_master_awid ; - - // value method cpu_imem_master_m_awaddr - assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; - - // value method cpu_imem_master_m_awlen - assign cpu_imem_master_awlen = cpu$imem_master_awlen ; - - // value method cpu_imem_master_m_awsize - assign cpu_imem_master_awsize = cpu$imem_master_awsize ; - - // value method cpu_imem_master_m_awburst - assign cpu_imem_master_awburst = cpu$imem_master_awburst ; - - // value method cpu_imem_master_m_awlock - assign cpu_imem_master_awlock = cpu$imem_master_awlock ; - - // value method cpu_imem_master_m_awcache - assign cpu_imem_master_awcache = cpu$imem_master_awcache ; - - // value method cpu_imem_master_m_awprot - assign cpu_imem_master_awprot = cpu$imem_master_awprot ; - - // value method cpu_imem_master_m_awqos - assign cpu_imem_master_awqos = cpu$imem_master_awqos ; - - // value method cpu_imem_master_m_awregion - assign cpu_imem_master_awregion = cpu$imem_master_awregion ; - - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; - - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; - - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = cpu$imem_master_wid ; - - // value method cpu_imem_master_m_wdata - assign cpu_imem_master_wdata = cpu$imem_master_wdata ; - - // value method cpu_imem_master_m_wstrb - assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; - - // value method cpu_imem_master_m_wlast - assign cpu_imem_master_wlast = cpu$imem_master_wlast ; - - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; - - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = cpu$imem_master_bready ; - - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; - - // value method cpu_imem_master_m_arid - assign cpu_imem_master_arid = cpu$imem_master_arid ; - - // value method cpu_imem_master_m_araddr - assign cpu_imem_master_araddr = cpu$imem_master_araddr ; - - // value method cpu_imem_master_m_arlen - assign cpu_imem_master_arlen = cpu$imem_master_arlen ; - - // value method cpu_imem_master_m_arsize - assign cpu_imem_master_arsize = cpu$imem_master_arsize ; - - // value method cpu_imem_master_m_arburst - assign cpu_imem_master_arburst = cpu$imem_master_arburst ; - - // value method cpu_imem_master_m_arlock - assign cpu_imem_master_arlock = cpu$imem_master_arlock ; - - // value method cpu_imem_master_m_arcache - assign cpu_imem_master_arcache = cpu$imem_master_arcache ; - - // value method cpu_imem_master_m_arprot - assign cpu_imem_master_arprot = cpu$imem_master_arprot ; - - // value method cpu_imem_master_m_arqos - assign cpu_imem_master_arqos = cpu$imem_master_arqos ; - - // value method cpu_imem_master_m_arregion - assign cpu_imem_master_arregion = cpu$imem_master_arregion ; - - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; - - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - - // value method cpu_imem_master_m_rready - assign cpu_imem_master_rready = cpu$imem_master_rready ; - - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; - - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; - - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; - - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; - - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; - - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; - - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; - - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; - - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; - - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; - - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; - - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; - - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; - - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; - - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; - - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; - - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; - - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; - - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; - - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; - - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; - - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; - - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; - - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; - - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; - - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; - - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; - - // action method core_external_interrupt_sources_0_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_1_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_2_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_3_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_4_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_5_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_6_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_7_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_8_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_9_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_10_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_11_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_12_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_13_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_14_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_15_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // submodule cpu - mkCPU cpu(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(cpu$dmem_master_arready), - .dmem_master_awready(cpu$dmem_master_awready), - .dmem_master_bid(cpu$dmem_master_bid), - .dmem_master_bresp(cpu$dmem_master_bresp), - .dmem_master_bvalid(cpu$dmem_master_bvalid), - .dmem_master_rdata(cpu$dmem_master_rdata), - .dmem_master_rid(cpu$dmem_master_rid), - .dmem_master_rlast(cpu$dmem_master_rlast), - .dmem_master_rresp(cpu$dmem_master_rresp), - .dmem_master_rvalid(cpu$dmem_master_rvalid), - .dmem_master_wready(cpu$dmem_master_wready), - .hart0_server_reset_request_put(cpu$hart0_server_reset_request_put), - .imem_master_arready(cpu$imem_master_arready), - .imem_master_awready(cpu$imem_master_awready), - .imem_master_bid(cpu$imem_master_bid), - .imem_master_bresp(cpu$imem_master_bresp), - .imem_master_bvalid(cpu$imem_master_bvalid), - .imem_master_rdata(cpu$imem_master_rdata), - .imem_master_rid(cpu$imem_master_rid), - .imem_master_rlast(cpu$imem_master_rlast), - .imem_master_rresp(cpu$imem_master_rresp), - .imem_master_rvalid(cpu$imem_master_rvalid), - .imem_master_wready(cpu$imem_master_wready), - .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), - .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), - .s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear), - .set_verbosity_logdelay(cpu$set_verbosity_logdelay), - .set_verbosity_verbosity(cpu$set_verbosity_verbosity), - .software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), - .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), - .EN_set_verbosity(cpu$EN_set_verbosity), - .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), - .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), - .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), - .imem_master_awvalid(cpu$imem_master_awvalid), - .imem_master_awid(cpu$imem_master_awid), - .imem_master_awaddr(cpu$imem_master_awaddr), - .imem_master_awlen(cpu$imem_master_awlen), - .imem_master_awsize(cpu$imem_master_awsize), - .imem_master_awburst(cpu$imem_master_awburst), - .imem_master_awlock(cpu$imem_master_awlock), - .imem_master_awcache(cpu$imem_master_awcache), - .imem_master_awprot(cpu$imem_master_awprot), - .imem_master_awqos(cpu$imem_master_awqos), - .imem_master_awregion(cpu$imem_master_awregion), - .imem_master_wvalid(cpu$imem_master_wvalid), - .imem_master_wid(cpu$imem_master_wid), - .imem_master_wdata(cpu$imem_master_wdata), - .imem_master_wstrb(cpu$imem_master_wstrb), - .imem_master_wlast(cpu$imem_master_wlast), - .imem_master_bready(cpu$imem_master_bready), - .imem_master_arvalid(cpu$imem_master_arvalid), - .imem_master_arid(cpu$imem_master_arid), - .imem_master_araddr(cpu$imem_master_araddr), - .imem_master_arlen(cpu$imem_master_arlen), - .imem_master_arsize(cpu$imem_master_arsize), - .imem_master_arburst(cpu$imem_master_arburst), - .imem_master_arlock(cpu$imem_master_arlock), - .imem_master_arcache(cpu$imem_master_arcache), - .imem_master_arprot(cpu$imem_master_arprot), - .imem_master_arqos(cpu$imem_master_arqos), - .imem_master_arregion(cpu$imem_master_arregion), - .imem_master_rready(cpu$imem_master_rready), - .dmem_master_awvalid(cpu$dmem_master_awvalid), - .dmem_master_awid(cpu$dmem_master_awid), - .dmem_master_awaddr(cpu$dmem_master_awaddr), - .dmem_master_awlen(cpu$dmem_master_awlen), - .dmem_master_awsize(cpu$dmem_master_awsize), - .dmem_master_awburst(cpu$dmem_master_awburst), - .dmem_master_awlock(cpu$dmem_master_awlock), - .dmem_master_awcache(cpu$dmem_master_awcache), - .dmem_master_awprot(cpu$dmem_master_awprot), - .dmem_master_awqos(cpu$dmem_master_awqos), - .dmem_master_awregion(cpu$dmem_master_awregion), - .dmem_master_wvalid(cpu$dmem_master_wvalid), - .dmem_master_wid(cpu$dmem_master_wid), - .dmem_master_wdata(cpu$dmem_master_wdata), - .dmem_master_wstrb(cpu$dmem_master_wstrb), - .dmem_master_wlast(cpu$dmem_master_wlast), - .dmem_master_bready(cpu$dmem_master_bready), - .dmem_master_arvalid(cpu$dmem_master_arvalid), - .dmem_master_arid(cpu$dmem_master_arid), - .dmem_master_araddr(cpu$dmem_master_araddr), - .dmem_master_arlen(cpu$dmem_master_arlen), - .dmem_master_arsize(cpu$dmem_master_arsize), - .dmem_master_arburst(cpu$dmem_master_arburst), - .dmem_master_arlock(cpu$dmem_master_arlock), - .dmem_master_arcache(cpu$dmem_master_arcache), - .dmem_master_arprot(cpu$dmem_master_arprot), - .dmem_master_arqos(cpu$dmem_master_arqos), - .dmem_master_arregion(cpu$dmem_master_arregion), - .dmem_master_rready(cpu$dmem_master_rready), - .RDY_set_verbosity()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(), - .v_from_masters_1_wready(), - .v_from_masters_1_bvalid(), - .v_from_masters_1_bid(), - .v_from_masters_1_bresp(), - .v_from_masters_1_arready(), - .v_from_masters_1_rvalid(), - .v_from_masters_1_rid(), - .v_from_masters_1_rdata(), - .v_from_masters_1_rresp(), - .v_from_masters_1_rlast(), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); - - // submodule near_mem_io - mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(near_mem_io$axi4_slave_araddr), - .axi4_slave_arburst(near_mem_io$axi4_slave_arburst), - .axi4_slave_arcache(near_mem_io$axi4_slave_arcache), - .axi4_slave_arid(near_mem_io$axi4_slave_arid), - .axi4_slave_arlen(near_mem_io$axi4_slave_arlen), - .axi4_slave_arlock(near_mem_io$axi4_slave_arlock), - .axi4_slave_arprot(near_mem_io$axi4_slave_arprot), - .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), - .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), - .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), - .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), - .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), - .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), - .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), - .axi4_slave_awid(near_mem_io$axi4_slave_awid), - .axi4_slave_awlen(near_mem_io$axi4_slave_awlen), - .axi4_slave_awlock(near_mem_io$axi4_slave_awlock), - .axi4_slave_awprot(near_mem_io$axi4_slave_awprot), - .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), - .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), - .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), - .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), - .axi4_slave_bready(near_mem_io$axi4_slave_bready), - .axi4_slave_rready(near_mem_io$axi4_slave_rready), - .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), - .axi4_slave_wid(near_mem_io$axi4_slave_wid), - .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), - .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), - .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), - .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), - .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), - .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), - .EN_set_addr_map(near_mem_io$EN_set_addr_map), - .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), - .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), - .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(near_mem_io$axi4_slave_awready), - .axi4_slave_wready(near_mem_io$axi4_slave_wready), - .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), - .axi4_slave_bid(near_mem_io$axi4_slave_bid), - .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), - .axi4_slave_arready(near_mem_io$axi4_slave_arready), - .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), - .axi4_slave_rid(near_mem_io$axi4_slave_rid), - .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), - .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), - .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), - .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), - .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), - .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), - .RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get)); - - // submodule plic - mkPLIC_16_2_7 plic(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(plic$axi4_slave_araddr), - .axi4_slave_arburst(plic$axi4_slave_arburst), - .axi4_slave_arcache(plic$axi4_slave_arcache), - .axi4_slave_arid(plic$axi4_slave_arid), - .axi4_slave_arlen(plic$axi4_slave_arlen), - .axi4_slave_arlock(plic$axi4_slave_arlock), - .axi4_slave_arprot(plic$axi4_slave_arprot), - .axi4_slave_arqos(plic$axi4_slave_arqos), - .axi4_slave_arregion(plic$axi4_slave_arregion), - .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), - .axi4_slave_awaddr(plic$axi4_slave_awaddr), - .axi4_slave_awburst(plic$axi4_slave_awburst), - .axi4_slave_awcache(plic$axi4_slave_awcache), - .axi4_slave_awid(plic$axi4_slave_awid), - .axi4_slave_awlen(plic$axi4_slave_awlen), - .axi4_slave_awlock(plic$axi4_slave_awlock), - .axi4_slave_awprot(plic$axi4_slave_awprot), - .axi4_slave_awqos(plic$axi4_slave_awqos), - .axi4_slave_awregion(plic$axi4_slave_awregion), - .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_bready(plic$axi4_slave_bready), - .axi4_slave_rready(plic$axi4_slave_rready), - .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), - .axi4_slave_wlast(plic$axi4_slave_wlast), - .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .set_addr_map_addr_base(plic$set_addr_map_addr_base), - .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), - .set_verbosity_verbosity(plic$set_verbosity_verbosity), - .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), - .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), - .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), - .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), - .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), - .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), - .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), - .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), - .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), - .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), - .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), - .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), - .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), - .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), - .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), - .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), - .EN_set_verbosity(plic$EN_set_verbosity), - .EN_show_PLIC_state(plic$EN_show_PLIC_state), - .EN_server_reset_request_put(plic$EN_server_reset_request_put), - .EN_server_reset_response_get(plic$EN_server_reset_response_get), - .EN_set_addr_map(plic$EN_set_addr_map), - .RDY_set_verbosity(), - .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(plic$axi4_slave_awready), - .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), - .axi4_slave_bid(plic$axi4_slave_bid), - .axi4_slave_bresp(plic$axi4_slave_bresp), - .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), - .axi4_slave_rid(plic$axi4_slave_rid), - .axi4_slave_rdata(plic$axi4_slave_rdata), - .axi4_slave_rresp(plic$axi4_slave_rresp), - .axi4_slave_rlast(plic$axi4_slave_rlast), - .v_targets_0_m_eip(plic$v_targets_0_m_eip), - .v_targets_1_m_eip(plic$v_targets_1_m_eip)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_relay_sw_interrupts - assign CAN_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // rule RL_rl_relay_timer_interrupts - assign CAN_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - - // rule RL_rl_relay_external_interrupts - assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule cpu - assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; - assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; - assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; - assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; - assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; - assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ; - assign cpu$imem_master_arready = cpu_imem_master_arready ; - assign cpu$imem_master_awready = cpu_imem_master_awready ; - assign cpu$imem_master_bid = cpu_imem_master_bid ; - assign cpu$imem_master_bresp = cpu_imem_master_bresp ; - assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; - assign cpu$imem_master_rdata = cpu_imem_master_rdata ; - assign cpu$imem_master_rid = cpu_imem_master_rid ; - assign cpu$imem_master_rlast = cpu_imem_master_rlast ; - assign cpu$imem_master_rresp = cpu_imem_master_rresp ; - assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; - assign cpu$imem_master_wready = cpu_imem_master_wready ; - assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; - assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; - assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; - assign cpu$software_interrupt_req_set_not_clear = - near_mem_io$get_sw_interrupt_req_get ; - assign cpu$timer_interrupt_req_set_not_clear = - near_mem_io$get_timer_interrupt_req_get ; - assign cpu$EN_hart0_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign cpu$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign cpu$EN_set_verbosity = EN_set_verbosity ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = cpu_reset_server_request_put ; - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ; - assign f_reset_rsps$ENQ = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; - assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; - assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; - assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; - assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; - assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; - assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; - assign fabric_2x3$v_from_masters_0_wid = cpu$dmem_master_wid ; - assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_awaddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_bready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_wdata = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wstrb = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; - assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; - - // submodule near_mem_io - assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign near_mem_io$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; - assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; - assign near_mem_io$set_addr_map_addr_base = - soc_map$m_near_mem_io_addr_base ; - assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; - assign near_mem_io$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign near_mem_io$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_set_addr_map = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_get_timer_interrupt_req_get = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign near_mem_io$EN_get_sw_interrupt_req_get = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_2_wid ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; - assign plic$set_verbosity_verbosity = 4'h0 ; - assign plic$v_sources_0_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; - assign plic$v_sources_10_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; - assign plic$v_sources_11_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; - assign plic$v_sources_12_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; - assign plic$v_sources_13_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; - assign plic$v_sources_14_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; - assign plic$v_sources_15_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; - assign plic$v_sources_1_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; - assign plic$v_sources_2_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; - assign plic$v_sources_3_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; - assign plic$v_sources_4_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; - assign plic$v_sources_5_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; - assign plic$v_sources_6_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; - assign plic$v_sources_7_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; - assign plic$v_sources_8_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; - assign plic$v_sources_9_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; - assign plic$EN_set_verbosity = 1'b0 ; - assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - cpu$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h4310 = $stime; - #0; - end - v__h4304 = v__h4310 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4304); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h4551 = $stime; - #0; - end - v__h4545 = v__h4551 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4545); - end - // synopsys translate_on -endmodule // mkCore - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Core.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Core.v deleted file mode 100644 index 46bcedc6..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Core.v +++ /dev/null @@ -1,8674 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// valid O 1 -// word_fst O 64 -// word_snd O 5 -// CLK I 1 clock -// RST_N I 1 reset -// req_opcode I 7 -// req_f7 I 7 -// req_rm I 3 -// req_rs2 I 5 -// req_v1 I 64 -// req_v2 I 64 -// req_v3 I 64 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFBox_Core(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_opcode, - req_f7, - req_rm, - req_rs2, - req_v1, - req_v2, - req_v3, - EN_req, - - valid, - - word_fst, - - word_snd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [6 : 0] req_opcode; - input [6 : 0] req_f7; - input [2 : 0] req_rm; - input [4 : 0] req_rs2; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input [63 : 0] req_v3; - input EN_req; - - // value method valid - output valid; - - // value method word_fst - output [63 : 0] word_fst; - - // value method word_snd - output [4 : 0] word_snd; - - // signals for module outputs - wire [63 : 0] word_fst; - wire [4 : 0] word_snd; - wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid; - - // inlined wires - wire [68 : 0] dw_result$wget; - wire dw_valid$wget, dw_valid$whas; - - // register requestR - reg [214 : 0] requestR; - wire [214 : 0] requestR$D_IN; - wire requestR$EN; - - // register resultR - reg [69 : 0] resultR; - reg [69 : 0] resultR$D_IN; - wire resultR$EN; - - // register stateR - reg [1 : 0] stateR; - reg [1 : 0] stateR$D_IN; - wire stateR$EN; - - // ports of submodule fpu - reg [201 : 0] fpu$server_core_request_put; - wire [69 : 0] fpu$server_core_response_get; - wire fpu$EN_server_core_request_put, - fpu$EN_server_core_response_get, - fpu$EN_server_reset_request_put, - fpu$EN_server_reset_response_get, - fpu$RDY_server_core_request_put, - fpu$RDY_server_core_response_get, - fpu$RDY_server_reset_request_put, - fpu$RDY_server_reset_response_get; - - // ports of submodule frmFpuF - wire frmFpuF$CLR, frmFpuF$DEQ, frmFpuF$D_IN, frmFpuF$ENQ; - - // ports of submodule resetReqsF - wire resetReqsF$CLR, - resetReqsF$DEQ, - resetReqsF$EMPTY_N, - resetReqsF$ENQ, - resetReqsF$FULL_N; - - // ports of submodule resetRspsF - wire resetRspsF$CLR, - resetRspsF$DEQ, - resetRspsF$EMPTY_N, - resetRspsF$ENQ, - resetRspsF$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_doFADD_D, - CAN_FIRE_RL_doFADD_S, - CAN_FIRE_RL_doFCLASS_D, - CAN_FIRE_RL_doFCLASS_S, - CAN_FIRE_RL_doFCVT_D_S, - CAN_FIRE_RL_doFCVT_D_W, - CAN_FIRE_RL_doFCVT_D_WU, - CAN_FIRE_RL_doFCVT_S_D, - CAN_FIRE_RL_doFCVT_S_W, - CAN_FIRE_RL_doFCVT_S_WU, - CAN_FIRE_RL_doFCVT_WU_D, - CAN_FIRE_RL_doFCVT_WU_S, - CAN_FIRE_RL_doFCVT_W_D, - CAN_FIRE_RL_doFCVT_W_S, - CAN_FIRE_RL_doFDIV_D, - CAN_FIRE_RL_doFDIV_S, - CAN_FIRE_RL_doFEQ_D, - CAN_FIRE_RL_doFEQ_S, - CAN_FIRE_RL_doFLE_D, - CAN_FIRE_RL_doFLE_S, - CAN_FIRE_RL_doFLT_D, - CAN_FIRE_RL_doFLT_S, - CAN_FIRE_RL_doFMADD_D, - CAN_FIRE_RL_doFMADD_S, - CAN_FIRE_RL_doFMAX_D, - CAN_FIRE_RL_doFMAX_S, - CAN_FIRE_RL_doFMIN_D, - CAN_FIRE_RL_doFMIN_S, - CAN_FIRE_RL_doFMSUB_D, - CAN_FIRE_RL_doFMSUB_S, - CAN_FIRE_RL_doFMUL_D, - CAN_FIRE_RL_doFMUL_S, - CAN_FIRE_RL_doFMV_D_X, - CAN_FIRE_RL_doFMV_W_X, - CAN_FIRE_RL_doFMV_X_D, - CAN_FIRE_RL_doFMV_X_W, - CAN_FIRE_RL_doFNMADD_D, - CAN_FIRE_RL_doFNMADD_S, - CAN_FIRE_RL_doFNMSUB_D, - CAN_FIRE_RL_doFNMSUB_S, - CAN_FIRE_RL_doFSGNJN_D, - CAN_FIRE_RL_doFSGNJN_S, - CAN_FIRE_RL_doFSGNJX_D, - CAN_FIRE_RL_doFSGNJX_S, - CAN_FIRE_RL_doFSGNJ_D, - CAN_FIRE_RL_doFSGNJ_S, - CAN_FIRE_RL_doFSQRT_D, - CAN_FIRE_RL_doFSQRT_S, - CAN_FIRE_RL_doFSUB_D, - CAN_FIRE_RL_doFSUB_S, - CAN_FIRE_RL_rl_drive_fpu_result, - CAN_FIRE_RL_rl_get_fpu_result, - CAN_FIRE_RL_rl_reset_begin, - CAN_FIRE_RL_rl_reset_end, - CAN_FIRE_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_RL_doFADD_D, - WILL_FIRE_RL_doFADD_S, - WILL_FIRE_RL_doFCLASS_D, - WILL_FIRE_RL_doFCLASS_S, - WILL_FIRE_RL_doFCVT_D_S, - WILL_FIRE_RL_doFCVT_D_W, - WILL_FIRE_RL_doFCVT_D_WU, - WILL_FIRE_RL_doFCVT_S_D, - WILL_FIRE_RL_doFCVT_S_W, - WILL_FIRE_RL_doFCVT_S_WU, - WILL_FIRE_RL_doFCVT_WU_D, - WILL_FIRE_RL_doFCVT_WU_S, - WILL_FIRE_RL_doFCVT_W_D, - WILL_FIRE_RL_doFCVT_W_S, - WILL_FIRE_RL_doFDIV_D, - WILL_FIRE_RL_doFDIV_S, - WILL_FIRE_RL_doFEQ_D, - WILL_FIRE_RL_doFEQ_S, - WILL_FIRE_RL_doFLE_D, - WILL_FIRE_RL_doFLE_S, - WILL_FIRE_RL_doFLT_D, - WILL_FIRE_RL_doFLT_S, - WILL_FIRE_RL_doFMADD_D, - WILL_FIRE_RL_doFMADD_S, - WILL_FIRE_RL_doFMAX_D, - WILL_FIRE_RL_doFMAX_S, - WILL_FIRE_RL_doFMIN_D, - WILL_FIRE_RL_doFMIN_S, - WILL_FIRE_RL_doFMSUB_D, - WILL_FIRE_RL_doFMSUB_S, - WILL_FIRE_RL_doFMUL_D, - WILL_FIRE_RL_doFMUL_S, - WILL_FIRE_RL_doFMV_D_X, - WILL_FIRE_RL_doFMV_W_X, - WILL_FIRE_RL_doFMV_X_D, - WILL_FIRE_RL_doFMV_X_W, - WILL_FIRE_RL_doFNMADD_D, - WILL_FIRE_RL_doFNMADD_S, - WILL_FIRE_RL_doFNMSUB_D, - WILL_FIRE_RL_doFNMSUB_S, - WILL_FIRE_RL_doFSGNJN_D, - WILL_FIRE_RL_doFSGNJN_S, - WILL_FIRE_RL_doFSGNJX_D, - WILL_FIRE_RL_doFSGNJX_S, - WILL_FIRE_RL_doFSGNJ_D, - WILL_FIRE_RL_doFSGNJ_S, - WILL_FIRE_RL_doFSQRT_D, - WILL_FIRE_RL_doFSQRT_S, - WILL_FIRE_RL_doFSUB_D, - WILL_FIRE_RL_doFSUB_S, - WILL_FIRE_RL_rl_drive_fpu_result, - WILL_FIRE_RL_rl_get_fpu_result, - WILL_FIRE_RL_rl_reset_begin, - WILL_FIRE_RL_rl_reset_end, - WILL_FIRE_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // inputs to muxes for submodule ports - wire [214 : 0] MUX_requestR$write_1__VAL_2; - wire [201 : 0] MUX_fpu$server_core_request_put_1__VAL_1, - MUX_fpu$server_core_request_put_1__VAL_10, - MUX_fpu$server_core_request_put_1__VAL_11, - MUX_fpu$server_core_request_put_1__VAL_12, - MUX_fpu$server_core_request_put_1__VAL_13, - MUX_fpu$server_core_request_put_1__VAL_14, - MUX_fpu$server_core_request_put_1__VAL_15, - MUX_fpu$server_core_request_put_1__VAL_16, - MUX_fpu$server_core_request_put_1__VAL_17, - MUX_fpu$server_core_request_put_1__VAL_18, - MUX_fpu$server_core_request_put_1__VAL_2, - MUX_fpu$server_core_request_put_1__VAL_3, - MUX_fpu$server_core_request_put_1__VAL_4, - MUX_fpu$server_core_request_put_1__VAL_5, - MUX_fpu$server_core_request_put_1__VAL_6, - MUX_fpu$server_core_request_put_1__VAL_7, - MUX_fpu$server_core_request_put_1__VAL_8, - MUX_fpu$server_core_request_put_1__VAL_9; - wire [69 : 0] MUX_resultR$write_1__VAL_10, - MUX_resultR$write_1__VAL_11, - MUX_resultR$write_1__VAL_12, - MUX_resultR$write_1__VAL_13, - MUX_resultR$write_1__VAL_14, - MUX_resultR$write_1__VAL_15, - MUX_resultR$write_1__VAL_16, - MUX_resultR$write_1__VAL_17, - MUX_resultR$write_1__VAL_18, - MUX_resultR$write_1__VAL_19, - MUX_resultR$write_1__VAL_20, - MUX_resultR$write_1__VAL_21, - MUX_resultR$write_1__VAL_22, - MUX_resultR$write_1__VAL_23, - MUX_resultR$write_1__VAL_24, - MUX_resultR$write_1__VAL_25, - MUX_resultR$write_1__VAL_26, - MUX_resultR$write_1__VAL_27, - MUX_resultR$write_1__VAL_28, - MUX_resultR$write_1__VAL_29, - MUX_resultR$write_1__VAL_3, - MUX_resultR$write_1__VAL_30, - MUX_resultR$write_1__VAL_31, - MUX_resultR$write_1__VAL_32, - MUX_resultR$write_1__VAL_33, - MUX_resultR$write_1__VAL_34, - MUX_resultR$write_1__VAL_35, - MUX_resultR$write_1__VAL_4, - MUX_resultR$write_1__VAL_5, - MUX_resultR$write_1__VAL_7, - MUX_resultR$write_1__VAL_8, - MUX_resultR$write_1__VAL_9; - wire [68 : 0] MUX_dw_result$wset_1__VAL_1; - wire MUX_dw_result$wset_1__SEL_1; - - // remaining internal signals - reg [51 : 0] CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q114, - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q115, - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q116, - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q117, - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q118, - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q119, - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q56, - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q57, - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q45, - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q46, - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q54, - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q55, - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q41, - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q42, - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617; - reg [22 : 0] CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q18, - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q19, - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q78, - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q79, - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q29, - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q30, - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q27, - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q28, - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q16, - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q17, - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q84, - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q85, - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q82, - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q83, - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q80, - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q81, - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754; - reg [10 : 0] CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q102, - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q103, - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q104, - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q105, - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q106, - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q107, - CASE_guard5160_0b0_0_0b1_0_0b10_out_exp5779_0b_ETC__q49, - CASE_guard5160_0b0_0_0b1_theResult___exp5776_0_ETC__q50, - CASE_guard5519_0b0_0_0b1_0_0b10_out_exp6138_0b_ETC__q44, - CASE_guard5519_0b0_0_0b1_theResult___exp6135_0_ETC__q43, - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_theR_ETC__q52, - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_x590_ETC__q53, - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_theR_ETC__q39, - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_x626_ETC__q40, - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5160_ETC__q51, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538; - reg [7 : 0] CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_theResu_ETC__q14, - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_x064_BI_ETC__q15, - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q70, - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q71, - CASE_guard3641_0b0_0_0b1_0_0b10_out_exp4057_0b_ETC__q22, - CASE_guard3641_0b0_0_0b1_theResult___exp4054_0_ETC__q23, - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_theRe_ETC__q25, - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_x4182_ETC__q26, - CASE_guard519_0b0_0_0b1_0_0b10_out_exp938_0b11_ETC__q13, - CASE_guard519_0b0_0_0b1_theResult___exp935_0b1_ETC__q12, - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q76, - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q77, - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q74, - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q75, - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q72, - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q73, - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard3641_ETC__q24, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716; - reg [2 : 0] IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50; - reg CASE_guard049_0b0_requestR_BIT_159_0b1_request_ETC__q10, - CASE_guard10776_0b0_requestR_BITS_191_TO_160_E_ETC__q108, - CASE_guard1080_0b0_requestR_BIT_191_0b1_reques_ETC__q86, - CASE_guard20084_0b0_requestR_BITS_191_TO_160_E_ETC__q110, - CASE_guard29151_0b0_requestR_BITS_191_TO_160_E_ETC__q112, - CASE_guard519_0b0_requestR_BIT_159_0b1_request_ETC__q8, - CASE_guard5519_0b0_requestR_BIT_159_0b1_reques_ETC__q35, - CASE_guard6249_0b0_requestR_BIT_159_0b1_reques_ETC__q37, - CASE_guard7668_0b0_requestR_BIT_191_0b1_reques_ETC__q92, - CASE_guard8804_0b0_requestR_BIT_191_0b1_reques_ETC__q90, - CASE_guard9815_0b0_requestR_BIT_191_0b1_reques_ETC__q88, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93; - wire [85 : 0] IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631, - b__h47244, - x__h47920, - x__h48943; - wire [64 : 0] _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78; - wire [63 : 0] IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1051, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1066, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1050, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1052, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1065, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1067, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1131, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1132, - IF_requestR_3_BITS_126_TO_116_754_EQ_2047_755__ETC___d3802, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3815, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3881, - res___1__h154853, - res___1__h155291, - res___1__h155301, - res___1__h155320, - res___1__h25997, - res___1__h26233, - res___1__h26243, - res___1__h26262, - res__h138561, - res__h142948, - res__h147441, - res__h150090, - res__h152730, - res__h154552, - res__h155336, - res__h155490, - res__h17988, - res__h18225, - res__h23375, - res__h24803, - res__h25817, - res__h26278, - res__h96811, - x__h139530, - x__h144023, - x__h148412, - x__h15077, - x__h151052, - x__h152874, - x__h154833, - x__h155457, - x__h16615, - x__h17309, - x__h19888, - x__h22358, - x__h22423, - x__h22505, - x__h2333, - x__h23933, - x__h2414, - x__h2492, - x__h24947, - x__h2584, - x__h25977, - x__h27284, - x__h27350, - x__h27418, - x__h27493, - x__h37386, - x__h46998, - x__h48519, - x__h49209, - x__h8990, - x__h97859; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q60, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q65, - IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q100, - IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q94, - IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q62, - IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q68, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845, - _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d3162, - _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_609__ETC___d2329, - _theResult____h120074, - _theResult____h61070, - _theResult____h78794, - _theResult___snd__h118688, - _theResult___snd__h118690, - _theResult___snd__h118697, - _theResult___snd__h118703, - _theResult___snd__h118726, - _theResult___snd__h128321, - _theResult___snd__h128332, - _theResult___snd__h128334, - _theResult___snd__h128344, - _theResult___snd__h128350, - _theResult___snd__h128373, - _theResult___snd__h137087, - _theResult___snd__h137101, - _theResult___snd__h137107, - _theResult___snd__h137125, - _theResult___snd__h69188, - _theResult___snd__h69199, - _theResult___snd__h69201, - _theResult___snd__h69211, - _theResult___snd__h69217, - _theResult___snd__h69240, - _theResult___snd__h77814, - _theResult___snd__h77816, - _theResult___snd__h77823, - _theResult___snd__h77829, - _theResult___snd__h77852, - _theResult___snd__h87041, - _theResult___snd__h87052, - _theResult___snd__h87054, - _theResult___snd__h87064, - _theResult___snd__h87070, - _theResult___snd__h87093, - _theResult___snd__h95691, - _theResult___snd__h95705, - _theResult___snd__h95711, - _theResult___snd__h95729, - b__h15323, - result__h120687, - result__h79407, - sfd__h53440, - sfdin__h128304, - sfdin__h69171, - sfdin__h87024, - x__h120782, - x__h15999, - x__h17039, - x__h79502; - wire [54 : 0] sfd___3__h35509, sfd___3__h45150, sfd__h27508, sfd__h37398; - wire [53 : 0] sfd__h118755, - sfd__h128402, - sfd__h137160, - sfd__h35536, - sfd__h36279, - sfd__h45177, - sfd__h45919, - value__h47246; - wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3592, - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3594, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3565, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3567, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3611, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3613, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1371, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1373, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1389, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1391, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3624, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1399, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1581, - _theResult___fst_sfd__h103665, - _theResult___fst_sfd__h119491, - _theResult___fst_sfd__h119494, - _theResult___fst_sfd__h129138, - _theResult___fst_sfd__h129141, - _theResult___fst_sfd__h137920, - _theResult___fst_sfd__h137923, - _theResult___fst_sfd__h137932, - _theResult___fst_sfd__h137938, - _theResult___fst_sfd__h36233, - _theResult___fst_sfd__h36989, - _theResult___fst_sfd__h36992, - _theResult___fst_sfd__h45873, - _theResult___fst_sfd__h46628, - _theResult___fst_sfd__h46631, - _theResult___fst_sfd__h49736, - _theResult___sfd__h119393, - _theResult___sfd__h129040, - _theResult___sfd__h137822, - _theResult___sfd__h36136, - _theResult___sfd__h36892, - _theResult___sfd__h45777, - _theResult___sfd__h46532, - _theResult___snd_fst_sfd__h119497, - _theResult___snd_fst_sfd__h137926, - _theResult___snd_fst_sfd__h36995, - _theResult___snd_fst_sfd__h46634, - _theResult___snd_fst_sfd__h99811, - out___1_sfd__h97925, - out_sfd__h119396, - out_sfd__h129043, - out_sfd__h137825, - out_sfd__h36139, - out_sfd__h36895, - out_sfd__h45780, - out_sfd__h46535, - value__h49279; - wire [32 : 0] _theResult_____2__h15258, - _theResult_____2__h47179, - out1___1__h15750, - out1___1__h47671; - wire [31 : 0] IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1047, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1060, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1062, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1048, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1063, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d904, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d963, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d900, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d902, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d961, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1686, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1688, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1747, - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1045, - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1059, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d1749, - IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d1690, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d833, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d965, - IF_requestR_3_BIT_191_202_THEN_2147483648_ELSE_ETC___d1619, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - requestR_BITS_159_TO_128__q1, - sfd___3__h13631, - sfd___3__h7509, - sfd__h2605, - x__h15080, - x__h16618, - x__h2340, - x__h2421, - x__h2499, - x__h2590, - x__h47001, - x__h48522, - x__h96817; - wire [30 : 0] IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29; - wire [24 : 0] sfd__h13658, - sfd__h14197, - sfd__h69269, - sfd__h7536, - sfd__h77881, - sfd__h8079, - sfd__h87122, - sfd__h95764, - value__h15325; - wire [23 : 0] NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624, - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1656, - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657, - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720; - wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2731, - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2733, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2777, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2779, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2750, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2752, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2796, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2798, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d416, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d418, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d434, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d436, - IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d2809, - _theResult___fst_sfd__h14151, - _theResult___fst_sfd__h14703, - _theResult___fst_sfd__h14706, - _theResult___fst_sfd__h61053, - _theResult___fst_sfd__h69802, - _theResult___fst_sfd__h69805, - _theResult___fst_sfd__h78414, - _theResult___fst_sfd__h78417, - _theResult___fst_sfd__h8033, - _theResult___fst_sfd__h8586, - _theResult___fst_sfd__h8589, - _theResult___fst_sfd__h87655, - _theResult___fst_sfd__h87658, - _theResult___fst_sfd__h96321, - _theResult___fst_sfd__h96324, - _theResult___fst_sfd__h96333, - _theResult___fst_sfd__h96339, - _theResult___fst_sfd__h98183, - _theResult___sfd__h14055, - _theResult___sfd__h14607, - _theResult___sfd__h69704, - _theResult___sfd__h78316, - _theResult___sfd__h7936, - _theResult___sfd__h8489, - _theResult___sfd__h87557, - _theResult___sfd__h96223, - _theResult___snd_fst_sfd__h14709, - _theResult___snd_fst_sfd__h53394, - _theResult___snd_fst_sfd__h78420, - _theResult___snd_fst_sfd__h8592, - _theResult___snd_fst_sfd__h96327, - out_sfd__h14058, - out_sfd__h14610, - out_sfd__h69707, - out_sfd__h78319, - out_sfd__h7939, - out_sfd__h8492, - out_sfd__h87560, - out_sfd__h96226, - sV1_sfd__h1205, - sV2_sfd__h1308, - value__h97928; - wire [19 : 0] NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d870, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934; - wire [11 : 0] IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3478, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96, - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322, - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1851, - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d3158, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3012, - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_609_ETC___d2325, - x__h120815, - x__h36264, - x__h45904, - x__h79535; - wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3463, - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3465, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3138, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3140, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3532, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3534, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1322, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1348, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1350, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q99, - _theResult___exp__h119392, - _theResult___exp__h129039, - _theResult___exp__h137821, - _theResult___exp__h36135, - _theResult___exp__h36891, - _theResult___exp__h45776, - _theResult___exp__h46531, - _theResult___fst_exp__h103664, - _theResult___fst_exp__h118728, - _theResult___fst_exp__h118734, - _theResult___fst_exp__h118737, - _theResult___fst_exp__h119490, - _theResult___fst_exp__h119493, - _theResult___fst_exp__h128310, - _theResult___fst_exp__h128375, - _theResult___fst_exp__h128381, - _theResult___fst_exp__h128384, - _theResult___fst_exp__h129137, - _theResult___fst_exp__h129140, - _theResult___fst_exp__h137093, - _theResult___fst_exp__h137132, - _theResult___fst_exp__h137138, - _theResult___fst_exp__h137141, - _theResult___fst_exp__h137919, - _theResult___fst_exp__h137922, - _theResult___fst_exp__h137931, - _theResult___fst_exp__h137934, - _theResult___fst_exp__h36232, - _theResult___fst_exp__h36988, - _theResult___fst_exp__h36991, - _theResult___fst_exp__h45872, - _theResult___fst_exp__h46627, - _theResult___fst_exp__h46630, - _theResult___snd_fst_exp__h119496, - _theResult___snd_fst_exp__h137925, - _theResult___snd_fst_exp__h36994, - _theResult___snd_fst_exp__h36997, - _theResult___snd_fst_exp__h37000, - _theResult___snd_fst_exp__h46633, - _theResult___snd_fst_exp__h46636, - _theResult___snd_fst_exp__h46639, - din_inc___2_exp__h137957, - din_inc___2_exp__h137987, - din_inc___2_exp__h138011, - din_inc___2_exp__h37034, - din_inc___2_exp__h46669, - out_exp__h119395, - out_exp__h129042, - out_exp__h137824, - out_exp__h36138, - out_exp__h36894, - out_exp__h45779, - out_exp__h46534, - requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622, - x__h97869; - wire [8 : 0] IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2643, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635, - x__h14182, - x__h8064; - wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2144, - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2146, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2628, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2630, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2301, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2303, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2697, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2699, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d367, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d393, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d395, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d405, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d722, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836, - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q67, - _theResult___exp__h14054, - _theResult___exp__h14606, - _theResult___exp__h69703, - _theResult___exp__h78315, - _theResult___exp__h7935, - _theResult___exp__h8488, - _theResult___exp__h87556, - _theResult___exp__h96222, - _theResult___fst_exp__h14150, - _theResult___fst_exp__h14702, - _theResult___fst_exp__h14705, - _theResult___fst_exp__h61052, - _theResult___fst_exp__h69177, - _theResult___fst_exp__h69242, - _theResult___fst_exp__h69248, - _theResult___fst_exp__h69251, - _theResult___fst_exp__h69801, - _theResult___fst_exp__h69804, - _theResult___fst_exp__h77854, - _theResult___fst_exp__h77860, - _theResult___fst_exp__h77863, - _theResult___fst_exp__h78413, - _theResult___fst_exp__h78416, - _theResult___fst_exp__h8032, - _theResult___fst_exp__h8585, - _theResult___fst_exp__h8588, - _theResult___fst_exp__h87030, - _theResult___fst_exp__h87095, - _theResult___fst_exp__h87101, - _theResult___fst_exp__h87104, - _theResult___fst_exp__h87654, - _theResult___fst_exp__h87657, - _theResult___fst_exp__h95697, - _theResult___fst_exp__h95736, - _theResult___fst_exp__h95742, - _theResult___fst_exp__h95745, - _theResult___fst_exp__h96320, - _theResult___fst_exp__h96323, - _theResult___fst_exp__h96332, - _theResult___fst_exp__h96335, - _theResult___snd_fst_exp__h14708, - _theResult___snd_fst_exp__h14711, - _theResult___snd_fst_exp__h14714, - _theResult___snd_fst_exp__h78419, - _theResult___snd_fst_exp__h8591, - _theResult___snd_fst_exp__h8594, - _theResult___snd_fst_exp__h8597, - _theResult___snd_fst_exp__h96326, - din_inc___2_exp__h14744, - din_inc___2_exp__h8631, - din_inc___2_exp__h96354, - din_inc___2_exp__h96378, - din_inc___2_exp__h96408, - din_inc___2_exp__h96432, - out_exp__h14057, - out_exp__h14609, - out_exp__h69706, - out_exp__h78318, - out_exp__h7938, - out_exp__h8491, - out_exp__h87559, - out_exp__h96225, - sV1_exp__h1204, - sV2_exp__h1307, - x__h49219; - wire [5 : 0] IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d2085, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d3404, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d2569, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1242, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d275, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1456, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d632; - wire [4 : 0] _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881, - x__h138663, - x__h143080, - x__h14848, - x__h152749, - x__h16413, - x__h17117, - x__h19349, - x__h24822, - x__h37156, - x__h46769, - x__h48317, - x__h49021, - x__h8757, - x__h96932; - wire [1 : 0] IF_sfd___33631_BIT_7_THEN_2_ELSE_0__q21, - IF_sfd___33631_BIT_8_THEN_2_ELSE_0__q20, - IF_sfd___3509_BIT_7_THEN_2_ELSE_0__q7, - IF_sfd___3509_BIT_8_THEN_2_ELSE_0__q6, - IF_sfd___35150_BIT_1_THEN_2_ELSE_0__q48, - IF_sfd___35150_BIT_2_THEN_2_ELSE_0__q47, - IF_sfd___35509_BIT_1_THEN_2_ELSE_0__q34, - IF_sfd___35509_BIT_2_THEN_2_ELSE_0__q33, - IF_sfdin28304_BIT_4_THEN_2_ELSE_0__q98, - IF_sfdin7024_BIT_33_THEN_2_ELSE_0__q66, - IF_sfdin9171_BIT_33_THEN_2_ELSE_0__q61, - IF_theResult___snd18688_BIT_4_THEN_2_ELSE_0__q95, - IF_theResult___snd37087_BIT_4_THEN_2_ELSE_0__q101, - IF_theResult___snd5691_BIT_33_THEN_2_ELSE_0__q69, - IF_theResult___snd7814_BIT_33_THEN_2_ELSE_0__q63, - IF_x5999_BIT_24_THEN_2_ELSE_0__q31, - IF_x7039_BIT_24_THEN_2_ELSE_0__q32, - IF_x7920_BIT_53_THEN_2_ELSE_0__q58, - IF_x8943_BIT_53_THEN_2_ELSE_0__q59, - guard__h110776, - guard__h120084, - guard__h129151, - guard__h13641, - guard__h14167, - guard__h15256, - guard__h15810, - guard__h16818, - guard__h35519, - guard__h36249, - guard__h45160, - guard__h45889, - guard__h47177, - guard__h47731, - guard__h48722, - guard__h61080, - guard__h69815, - guard__h7519, - guard__h78804, - guard__h8049, - guard__h87668; - wire IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_7_ETC___d2831, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1301, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1416, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d345, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d495, - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1598, - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d808, - IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d3648, - IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3656, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3660, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3695, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3698, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3705, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3719, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3731, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3743, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d926, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1712, - IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d1302, - IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d3640, - IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1040, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3658, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3717, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3729, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3741, - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2849, - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2927, - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2940, - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2953, - IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d1020, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2851, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2902, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2913, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2929, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2942, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2955, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1006, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1016, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1029, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1031, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1034, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1036, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1054, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1087, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1098, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1102, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d832, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d973, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d984, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1648, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1680, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1741, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d862, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d894, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d955, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d486, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d489, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d498, - IF_requestR_3_BIT_191_202_THEN_NOT_requestR_3__ETC___d3795, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d873, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d936, - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1659, - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1722, - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2921, - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2949, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1043, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1044, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1097, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1103, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1119, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d915, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d978, - NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d283, - NOT_requestR_3_BITS_159_TO_128_44_EQ_0_45_46_A_ETC___d800, - NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1701, - NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1764, - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3799, - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3860, - NOT_requestR_3_BITS_190_TO_180_609_ULT_request_ETC___d3839, - NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1101, - NOT_requestR_3_BIT_158_07_08_AND_NOT_requestR__ETC___d598, - NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157, - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323, - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2087, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3406, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2571, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3086, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3479, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2249, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2644, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2884, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2909, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2936, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014, - guard__h120682, - guard__h79402, - requestR_3_BITS_126_TO_116_754_EQ_0_768_AND_re_ETC___d3775, - requestR_3_BITS_179_TO_128_611_ULE_requestR_3__ETC___d3787, - requestR_3_BITS_179_TO_128_611_ULT_requestR_3__ETC___d3792, - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3771, - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3843, - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1759, - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1770, - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3763, - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3808, - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3828, - requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786, - requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3784, - requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3838, - requestR_3_BITS_190_TO_180_609_ULT_requestR_3__ETC___d3791, - requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d1042, - requestR_3_BIT_158_07_OR_requestR_3_BIT_157_09_ETC___d789, - requestR_3_BIT_159_6_OR_requestR_3_BIT_158_07__ETC___d811; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = resetReqsF$FULL_N ; - assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas && dw_valid$wget ; - - // value method word_fst - assign word_fst = dw_result$wget[68:5] ; - - // value method word_snd - assign word_snd = dw_result$wget[4:0] ; - - // submodule fpu - mkFPU fpu(.CLK(CLK), - .RST_N(RST_N), - .server_core_request_put(fpu$server_core_request_put), - .EN_server_core_request_put(fpu$EN_server_core_request_put), - .EN_server_core_response_get(fpu$EN_server_core_response_get), - .EN_server_reset_request_put(fpu$EN_server_reset_request_put), - .EN_server_reset_response_get(fpu$EN_server_reset_response_get), - .RDY_server_core_request_put(fpu$RDY_server_core_request_put), - .server_core_response_get(fpu$server_core_response_get), - .RDY_server_core_response_get(fpu$RDY_server_core_response_get), - .RDY_server_reset_request_put(fpu$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fpu$RDY_server_reset_response_get)); - - // submodule frmFpuF - FIFO2 #(.width(32'd1), .guarded(32'd1)) frmFpuF(.RST(RST_N), - .CLK(CLK), - .D_IN(frmFpuF$D_IN), - .ENQ(frmFpuF$ENQ), - .DEQ(frmFpuF$DEQ), - .CLR(frmFpuF$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N()); - - // submodule resetReqsF - FIFO20 #(.guarded(32'd1)) resetReqsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetReqsF$ENQ), - .DEQ(resetReqsF$DEQ), - .CLR(resetReqsF$CLR), - .FULL_N(resetReqsF$FULL_N), - .EMPTY_N(resetReqsF$EMPTY_N)); - - // submodule resetRspsF - FIFO20 #(.guarded(32'd1)) resetRspsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetRspsF$ENQ), - .DEQ(resetRspsF$DEQ), - .CLR(resetRspsF$CLR), - .FULL_N(resetRspsF$FULL_N), - .EMPTY_N(resetRspsF$EMPTY_N)); - - // rule RL_rl_reset_end - assign CAN_FIRE_RL_rl_reset_end = - fpu$RDY_server_reset_response_get && resetRspsF$FULL_N && - stateR == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_end = CAN_FIRE_RL_rl_reset_end ; - - // rule RL_doFADD_S - assign CAN_FIRE_RL_doFADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0 ; - assign WILL_FIRE_RL_doFADD_S = CAN_FIRE_RL_doFADD_S ; - - // rule RL_doFSUB_S - assign CAN_FIRE_RL_doFSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h04 ; - assign WILL_FIRE_RL_doFSUB_S = CAN_FIRE_RL_doFSUB_S ; - - // rule RL_doFMUL_S - assign CAN_FIRE_RL_doFMUL_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h08 ; - assign WILL_FIRE_RL_doFMUL_S = CAN_FIRE_RL_doFMUL_S ; - - // rule RL_doFMADD_S - assign CAN_FIRE_RL_doFMADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000011 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFMADD_S = CAN_FIRE_RL_doFMADD_S ; - - // rule RL_doFMSUB_S - assign CAN_FIRE_RL_doFMSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000111 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFMSUB_S = CAN_FIRE_RL_doFMSUB_S ; - - // rule RL_doFNMADD_S - assign CAN_FIRE_RL_doFNMADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001111 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFNMADD_S = CAN_FIRE_RL_doFNMADD_S ; - - // rule RL_doFNMSUB_S - assign CAN_FIRE_RL_doFNMSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001011 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFNMSUB_S = CAN_FIRE_RL_doFNMSUB_S ; - - // rule RL_doFDIV_S - assign CAN_FIRE_RL_doFDIV_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0C ; - assign WILL_FIRE_RL_doFDIV_S = CAN_FIRE_RL_doFDIV_S ; - - // rule RL_doFSQRT_S - assign CAN_FIRE_RL_doFSQRT_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h2C ; - assign WILL_FIRE_RL_doFSQRT_S = CAN_FIRE_RL_doFSQRT_S ; - - // rule RL_doFSGNJ_S - assign CAN_FIRE_RL_doFSGNJ_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFSGNJ_S = CAN_FIRE_RL_doFSGNJ_S ; - - // rule RL_doFSGNJN_S - assign CAN_FIRE_RL_doFSGNJN_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFSGNJN_S = CAN_FIRE_RL_doFSGNJN_S ; - - // rule RL_doFSGNJX_S - assign CAN_FIRE_RL_doFSGNJX_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFSGNJX_S = CAN_FIRE_RL_doFSGNJX_S ; - - // rule RL_doFCVT_S_W - assign CAN_FIRE_RL_doFCVT_S_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_S_W = CAN_FIRE_RL_doFCVT_S_W ; - - // rule RL_doFCVT_S_WU - assign CAN_FIRE_RL_doFCVT_S_WU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_S_WU = CAN_FIRE_RL_doFCVT_S_WU ; - - // rule RL_doFCVT_W_S - assign CAN_FIRE_RL_doFCVT_W_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_W_S = CAN_FIRE_RL_doFCVT_W_S ; - - // rule RL_doFCVT_WU_S - assign CAN_FIRE_RL_doFCVT_WU_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_WU_S = CAN_FIRE_RL_doFCVT_WU_S ; - - // rule RL_doFMIN_S - assign CAN_FIRE_RL_doFMIN_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h14 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMIN_S = CAN_FIRE_RL_doFMIN_S ; - - // rule RL_doFMAX_S - assign CAN_FIRE_RL_doFMAX_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h14 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFMAX_S = CAN_FIRE_RL_doFMAX_S ; - - // rule RL_doFMV_W_X - assign CAN_FIRE_RL_doFMV_W_X = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h78 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_W_X = CAN_FIRE_RL_doFMV_W_X ; - - // rule RL_doFMV_X_W - assign CAN_FIRE_RL_doFMV_X_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h70 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_X_W = CAN_FIRE_RL_doFMV_X_W ; - - // rule RL_doFEQ_S - assign CAN_FIRE_RL_doFEQ_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFEQ_S = CAN_FIRE_RL_doFEQ_S ; - - // rule RL_doFLT_S - assign CAN_FIRE_RL_doFLT_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFLT_S = CAN_FIRE_RL_doFLT_S ; - - // rule RL_doFLE_S - assign CAN_FIRE_RL_doFLE_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFLE_S = CAN_FIRE_RL_doFLE_S ; - - // rule RL_doFCLASS_S - assign CAN_FIRE_RL_doFCLASS_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h70 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFCLASS_S = CAN_FIRE_RL_doFCLASS_S ; - - // rule RL_doFADD_D - assign CAN_FIRE_RL_doFADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h01 ; - assign WILL_FIRE_RL_doFADD_D = CAN_FIRE_RL_doFADD_D ; - - // rule RL_doFSUB_D - assign CAN_FIRE_RL_doFSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h05 ; - assign WILL_FIRE_RL_doFSUB_D = CAN_FIRE_RL_doFSUB_D ; - - // rule RL_doFMUL_D - assign CAN_FIRE_RL_doFMUL_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h09 ; - assign WILL_FIRE_RL_doFMUL_D = CAN_FIRE_RL_doFMUL_D ; - - // rule RL_doFMADD_D - assign CAN_FIRE_RL_doFMADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000011 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFMADD_D = CAN_FIRE_RL_doFMADD_D ; - - // rule RL_doFMSUB_D - assign CAN_FIRE_RL_doFMSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000111 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFMSUB_D = CAN_FIRE_RL_doFMSUB_D ; - - // rule RL_doFNMADD_D - assign CAN_FIRE_RL_doFNMADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001111 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFNMADD_D = CAN_FIRE_RL_doFNMADD_D ; - - // rule RL_doFNMSUB_D - assign CAN_FIRE_RL_doFNMSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001011 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFNMSUB_D = CAN_FIRE_RL_doFNMSUB_D ; - - // rule RL_doFDIV_D - assign CAN_FIRE_RL_doFDIV_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0D ; - assign WILL_FIRE_RL_doFDIV_D = CAN_FIRE_RL_doFDIV_D ; - - // rule RL_doFSQRT_D - assign CAN_FIRE_RL_doFSQRT_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h2D ; - assign WILL_FIRE_RL_doFSQRT_D = CAN_FIRE_RL_doFSQRT_D ; - - // rule RL_doFSGNJ_D - assign CAN_FIRE_RL_doFSGNJ_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFSGNJ_D = CAN_FIRE_RL_doFSGNJ_D ; - - // rule RL_doFSGNJN_D - assign CAN_FIRE_RL_doFSGNJN_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFSGNJN_D = CAN_FIRE_RL_doFSGNJN_D ; - - // rule RL_doFSGNJX_D - assign CAN_FIRE_RL_doFSGNJX_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFSGNJX_D = CAN_FIRE_RL_doFSGNJX_D ; - - // rule RL_doFCVT_D_W - assign CAN_FIRE_RL_doFCVT_D_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_D_W = CAN_FIRE_RL_doFCVT_D_W ; - - // rule RL_doFCVT_D_WU - assign CAN_FIRE_RL_doFCVT_D_WU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_D_WU = CAN_FIRE_RL_doFCVT_D_WU ; - - // rule RL_doFCVT_W_D - assign CAN_FIRE_RL_doFCVT_W_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_W_D = CAN_FIRE_RL_doFCVT_W_D ; - - // rule RL_doFCVT_WU_D - assign CAN_FIRE_RL_doFCVT_WU_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_WU_D = CAN_FIRE_RL_doFCVT_WU_D ; - - // rule RL_doFCVT_S_D - assign CAN_FIRE_RL_doFCVT_S_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h20 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_S_D = CAN_FIRE_RL_doFCVT_S_D ; - - // rule RL_doFCVT_D_S - assign CAN_FIRE_RL_doFCVT_D_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h21 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_D_S = CAN_FIRE_RL_doFCVT_D_S ; - - // rule RL_doFMIN_D - assign CAN_FIRE_RL_doFMIN_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h15 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMIN_D = CAN_FIRE_RL_doFMIN_D ; - - // rule RL_doFMAX_D - assign CAN_FIRE_RL_doFMAX_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h15 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFMAX_D = CAN_FIRE_RL_doFMAX_D ; - - // rule RL_doFEQ_D - assign CAN_FIRE_RL_doFEQ_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFEQ_D = CAN_FIRE_RL_doFEQ_D ; - - // rule RL_doFLT_D - assign CAN_FIRE_RL_doFLT_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFLT_D = CAN_FIRE_RL_doFLT_D ; - - // rule RL_doFLE_D - assign CAN_FIRE_RL_doFLE_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFLE_D = CAN_FIRE_RL_doFLE_D ; - - // rule RL_doFMV_D_X - assign CAN_FIRE_RL_doFMV_D_X = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h79 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_D_X = CAN_FIRE_RL_doFMV_D_X ; - - // rule RL_doFMV_X_D - assign CAN_FIRE_RL_doFMV_X_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h71 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_X_D = CAN_FIRE_RL_doFMV_X_D ; - - // rule RL_doFCLASS_D - assign CAN_FIRE_RL_doFCLASS_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h71 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFCLASS_D = CAN_FIRE_RL_doFCLASS_D ; - - // rule RL_rl_get_fpu_result - assign CAN_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ; - assign WILL_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ; - - // rule RL_rl_drive_fpu_result - assign CAN_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ; - assign WILL_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ; - - // rule RL_rl_reset_begin - assign CAN_FIRE_RL_rl_reset_begin = - fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_begin = CAN_FIRE_RL_rl_reset_begin ; - - // inputs to muxes for submodule ports - assign MUX_dw_result$wset_1__SEL_1 = - fpu$RDY_server_core_response_get && stateR == 2'd2 ; - assign MUX_dw_result$wset_1__VAL_1 = - { x__h155457, fpu$server_core_response_get[4:0] } ; - assign MUX_fpu$server_core_request_put_1__VAL_1 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd0 } ; - assign MUX_fpu$server_core_request_put_1__VAL_2 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd1 } ; - assign MUX_fpu$server_core_request_put_1__VAL_3 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd2 } ; - assign MUX_fpu$server_core_request_put_1__VAL_4 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd5 } ; - assign MUX_fpu$server_core_request_put_1__VAL_5 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd6 } ; - assign MUX_fpu$server_core_request_put_1__VAL_6 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd7 } ; - assign MUX_fpu$server_core_request_put_1__VAL_7 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd8 } ; - assign MUX_fpu$server_core_request_put_1__VAL_8 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd3 } ; - assign MUX_fpu$server_core_request_put_1__VAL_9 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 130'h15555555555555554AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd4 } ; - assign MUX_fpu$server_core_request_put_1__VAL_10 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd0 } ; - assign MUX_fpu$server_core_request_put_1__VAL_11 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd1 } ; - assign MUX_fpu$server_core_request_put_1__VAL_12 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd2 } ; - assign MUX_fpu$server_core_request_put_1__VAL_13 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd5 } ; - assign MUX_fpu$server_core_request_put_1__VAL_14 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd6 } ; - assign MUX_fpu$server_core_request_put_1__VAL_15 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd7 } ; - assign MUX_fpu$server_core_request_put_1__VAL_16 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd8 } ; - assign MUX_fpu$server_core_request_put_1__VAL_17 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd3 } ; - assign MUX_fpu$server_core_request_put_1__VAL_18 = - { 1'd0, - requestR[191:128], - 130'h15555555555555554AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd4 } ; - assign MUX_requestR$write_1__VAL_2 = - { 1'd1, - req_opcode, - req_f7, - req_rs2, - req_rm, - req_v1, - req_v2, - req_v3 } ; - assign MUX_resultR$write_1__VAL_3 = - { 1'd1, x__h155457, fpu$server_core_response_get[4:0] } ; - assign MUX_resultR$write_1__VAL_4 = { 1'd1, x__h154833, 5'd0 } ; - assign MUX_resultR$write_1__VAL_5 = { 1'd1, requestR[191:128], 5'd0 } ; - assign MUX_resultR$write_1__VAL_7 = { 1'd1, x__h152874, x__h152749 } ; - assign MUX_resultR$write_1__VAL_8 = { 1'd1, x__h151052, x__h152749 } ; - assign MUX_resultR$write_1__VAL_9 = { 1'd1, x__h148412, x__h143080 } ; - assign MUX_resultR$write_1__VAL_10 = { 1'd1, x__h144023, x__h143080 } ; - assign MUX_resultR$write_1__VAL_11 = { 1'd1, x__h139530, x__h143080 } ; - assign MUX_resultR$write_1__VAL_12 = { 1'd1, x__h97859, x__h138663 } ; - assign MUX_resultR$write_1__VAL_13 = { 1'd1, x__h49209, x__h96932 } ; - assign MUX_resultR$write_1__VAL_14 = { 1'd1, x__h48519, x__h49021 } ; - assign MUX_resultR$write_1__VAL_15 = { 1'd1, x__h46998, x__h48317 } ; - assign MUX_resultR$write_1__VAL_16 = { 1'd1, x__h37386, x__h46769 } ; - assign MUX_resultR$write_1__VAL_17 = { 1'd1, x__h27493, x__h37156 } ; - assign MUX_resultR$write_1__VAL_18 = { 1'd1, x__h27418, 5'd0 } ; - assign MUX_resultR$write_1__VAL_19 = { 1'd1, x__h27350, 5'd0 } ; - assign MUX_resultR$write_1__VAL_20 = { 1'd1, x__h27284, 5'd0 } ; - assign MUX_resultR$write_1__VAL_21 = { 1'd1, x__h25977, 5'd0 } ; - assign MUX_resultR$write_1__VAL_22 = { 1'd1, x__h24947, x__h24822 } ; - assign MUX_resultR$write_1__VAL_23 = { 1'd1, x__h23933, x__h24822 } ; - assign MUX_resultR$write_1__VAL_24 = { 1'd1, x__h22505, x__h19349 } ; - assign MUX_resultR$write_1__VAL_25 = { 1'd1, x__h22423, 5'd0 } ; - assign MUX_resultR$write_1__VAL_26 = { 1'd1, x__h22358, 5'd0 } ; - assign MUX_resultR$write_1__VAL_27 = { 1'd1, x__h19888, x__h19349 } ; - assign MUX_resultR$write_1__VAL_28 = { 1'd1, x__h17309, x__h19349 } ; - assign MUX_resultR$write_1__VAL_29 = { 1'd1, x__h16615, x__h17117 } ; - assign MUX_resultR$write_1__VAL_30 = { 1'd1, x__h15077, x__h16413 } ; - assign MUX_resultR$write_1__VAL_31 = { 1'd1, x__h8990, x__h14848 } ; - assign MUX_resultR$write_1__VAL_32 = { 1'd1, x__h2584, x__h8757 } ; - assign MUX_resultR$write_1__VAL_33 = { 1'd1, x__h2492, 5'd0 } ; - assign MUX_resultR$write_1__VAL_34 = { 1'd1, x__h2414, 5'd0 } ; - assign MUX_resultR$write_1__VAL_35 = { 1'd1, x__h2333, 5'd0 } ; - - // inlined wires - assign dw_valid$wget = !WILL_FIRE_RL_rl_drive_fpu_result || resultR[69] ; - assign dw_valid$whas = - WILL_FIRE_RL_rl_drive_fpu_result || - WILL_FIRE_RL_rl_get_fpu_result ; - assign dw_result$wget = - WILL_FIRE_RL_rl_get_fpu_result ? - MUX_dw_result$wset_1__VAL_1 : - resultR[68:0] ; - - // register requestR - assign requestR$D_IN = - WILL_FIRE_RL_rl_reset_begin ? - 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - MUX_requestR$write_1__VAL_2 ; - assign requestR$EN = WILL_FIRE_RL_rl_reset_begin || EN_req ; - - // register resultR - always@(WILL_FIRE_RL_rl_reset_begin or - EN_req or - WILL_FIRE_RL_rl_get_fpu_result or - MUX_resultR$write_1__VAL_3 or - WILL_FIRE_RL_doFCLASS_D or - MUX_resultR$write_1__VAL_4 or - WILL_FIRE_RL_doFMV_X_D or - MUX_resultR$write_1__VAL_5 or - WILL_FIRE_RL_doFMV_D_X or - WILL_FIRE_RL_doFLE_D or - MUX_resultR$write_1__VAL_7 or - WILL_FIRE_RL_doFLT_D or - MUX_resultR$write_1__VAL_8 or - WILL_FIRE_RL_doFEQ_D or - MUX_resultR$write_1__VAL_9 or - WILL_FIRE_RL_doFMAX_D or - MUX_resultR$write_1__VAL_10 or - WILL_FIRE_RL_doFMIN_D or - MUX_resultR$write_1__VAL_11 or - WILL_FIRE_RL_doFCVT_D_S or - MUX_resultR$write_1__VAL_12 or - WILL_FIRE_RL_doFCVT_S_D or - MUX_resultR$write_1__VAL_13 or - WILL_FIRE_RL_doFCVT_WU_D or - MUX_resultR$write_1__VAL_14 or - WILL_FIRE_RL_doFCVT_W_D or - MUX_resultR$write_1__VAL_15 or - WILL_FIRE_RL_doFCVT_D_WU or - MUX_resultR$write_1__VAL_16 or - WILL_FIRE_RL_doFCVT_D_W or - MUX_resultR$write_1__VAL_17 or - WILL_FIRE_RL_doFSGNJX_D or - MUX_resultR$write_1__VAL_18 or - WILL_FIRE_RL_doFSGNJN_D or - MUX_resultR$write_1__VAL_19 or - WILL_FIRE_RL_doFSGNJ_D or - MUX_resultR$write_1__VAL_20 or - WILL_FIRE_RL_doFCLASS_S or - MUX_resultR$write_1__VAL_21 or - WILL_FIRE_RL_doFLE_S or - MUX_resultR$write_1__VAL_22 or - WILL_FIRE_RL_doFLT_S or - MUX_resultR$write_1__VAL_23 or - WILL_FIRE_RL_doFEQ_S or - MUX_resultR$write_1__VAL_24 or - WILL_FIRE_RL_doFMV_X_W or - MUX_resultR$write_1__VAL_25 or - WILL_FIRE_RL_doFMV_W_X or - MUX_resultR$write_1__VAL_26 or - WILL_FIRE_RL_doFMAX_S or - MUX_resultR$write_1__VAL_27 or - WILL_FIRE_RL_doFMIN_S or - MUX_resultR$write_1__VAL_28 or - WILL_FIRE_RL_doFCVT_WU_S or - MUX_resultR$write_1__VAL_29 or - WILL_FIRE_RL_doFCVT_W_S or - MUX_resultR$write_1__VAL_30 or - WILL_FIRE_RL_doFCVT_S_WU or - MUX_resultR$write_1__VAL_31 or - WILL_FIRE_RL_doFCVT_S_W or - MUX_resultR$write_1__VAL_32 or - WILL_FIRE_RL_doFSGNJX_S or - MUX_resultR$write_1__VAL_33 or - WILL_FIRE_RL_doFSGNJN_S or - MUX_resultR$write_1__VAL_34 or - WILL_FIRE_RL_doFSGNJ_S or MUX_resultR$write_1__VAL_35) - case (1'b1) - WILL_FIRE_RL_rl_reset_begin || EN_req: - resultR$D_IN = 70'h0AAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_get_fpu_result: resultR$D_IN = MUX_resultR$write_1__VAL_3; - WILL_FIRE_RL_doFCLASS_D: resultR$D_IN = MUX_resultR$write_1__VAL_4; - WILL_FIRE_RL_doFMV_X_D: resultR$D_IN = MUX_resultR$write_1__VAL_5; - WILL_FIRE_RL_doFMV_D_X: resultR$D_IN = MUX_resultR$write_1__VAL_5; - WILL_FIRE_RL_doFLE_D: resultR$D_IN = MUX_resultR$write_1__VAL_7; - WILL_FIRE_RL_doFLT_D: resultR$D_IN = MUX_resultR$write_1__VAL_8; - WILL_FIRE_RL_doFEQ_D: resultR$D_IN = MUX_resultR$write_1__VAL_9; - WILL_FIRE_RL_doFMAX_D: resultR$D_IN = MUX_resultR$write_1__VAL_10; - WILL_FIRE_RL_doFMIN_D: resultR$D_IN = MUX_resultR$write_1__VAL_11; - WILL_FIRE_RL_doFCVT_D_S: resultR$D_IN = MUX_resultR$write_1__VAL_12; - WILL_FIRE_RL_doFCVT_S_D: resultR$D_IN = MUX_resultR$write_1__VAL_13; - WILL_FIRE_RL_doFCVT_WU_D: resultR$D_IN = MUX_resultR$write_1__VAL_14; - WILL_FIRE_RL_doFCVT_W_D: resultR$D_IN = MUX_resultR$write_1__VAL_15; - WILL_FIRE_RL_doFCVT_D_WU: resultR$D_IN = MUX_resultR$write_1__VAL_16; - WILL_FIRE_RL_doFCVT_D_W: resultR$D_IN = MUX_resultR$write_1__VAL_17; - WILL_FIRE_RL_doFSGNJX_D: resultR$D_IN = MUX_resultR$write_1__VAL_18; - WILL_FIRE_RL_doFSGNJN_D: resultR$D_IN = MUX_resultR$write_1__VAL_19; - WILL_FIRE_RL_doFSGNJ_D: resultR$D_IN = MUX_resultR$write_1__VAL_20; - WILL_FIRE_RL_doFCLASS_S: resultR$D_IN = MUX_resultR$write_1__VAL_21; - WILL_FIRE_RL_doFLE_S: resultR$D_IN = MUX_resultR$write_1__VAL_22; - WILL_FIRE_RL_doFLT_S: resultR$D_IN = MUX_resultR$write_1__VAL_23; - WILL_FIRE_RL_doFEQ_S: resultR$D_IN = MUX_resultR$write_1__VAL_24; - WILL_FIRE_RL_doFMV_X_W: resultR$D_IN = MUX_resultR$write_1__VAL_25; - WILL_FIRE_RL_doFMV_W_X: resultR$D_IN = MUX_resultR$write_1__VAL_26; - WILL_FIRE_RL_doFMAX_S: resultR$D_IN = MUX_resultR$write_1__VAL_27; - WILL_FIRE_RL_doFMIN_S: resultR$D_IN = MUX_resultR$write_1__VAL_28; - WILL_FIRE_RL_doFCVT_WU_S: resultR$D_IN = MUX_resultR$write_1__VAL_29; - WILL_FIRE_RL_doFCVT_W_S: resultR$D_IN = MUX_resultR$write_1__VAL_30; - WILL_FIRE_RL_doFCVT_S_WU: resultR$D_IN = MUX_resultR$write_1__VAL_31; - WILL_FIRE_RL_doFCVT_S_W: resultR$D_IN = MUX_resultR$write_1__VAL_32; - WILL_FIRE_RL_doFSGNJX_S: resultR$D_IN = MUX_resultR$write_1__VAL_33; - WILL_FIRE_RL_doFSGNJN_S: resultR$D_IN = MUX_resultR$write_1__VAL_34; - WILL_FIRE_RL_doFSGNJ_S: resultR$D_IN = MUX_resultR$write_1__VAL_35; - default: resultR$D_IN = 70'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign resultR$EN = - WILL_FIRE_RL_rl_reset_begin || EN_req || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFSGNJ_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFLE_S || - WILL_FIRE_RL_doFCLASS_S || - WILL_FIRE_RL_doFSGNJ_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_rl_get_fpu_result ; - - // register stateR - always@(WILL_FIRE_RL_rl_reset_begin or - EN_req or - WILL_FIRE_RL_rl_get_fpu_result or - WILL_FIRE_RL_doFCLASS_D or - WILL_FIRE_RL_doFMV_X_D or - WILL_FIRE_RL_doFMV_D_X or - WILL_FIRE_RL_doFLE_D or - WILL_FIRE_RL_doFLT_D or - WILL_FIRE_RL_doFEQ_D or - WILL_FIRE_RL_doFMAX_D or - WILL_FIRE_RL_doFMIN_D or - WILL_FIRE_RL_doFCVT_D_S or - WILL_FIRE_RL_doFCVT_S_D or - WILL_FIRE_RL_doFCVT_WU_D or - WILL_FIRE_RL_doFCVT_W_D or - WILL_FIRE_RL_doFCVT_D_WU or - WILL_FIRE_RL_doFCVT_D_W or - WILL_FIRE_RL_doFSGNJX_D or - WILL_FIRE_RL_doFSGNJN_D or - WILL_FIRE_RL_doFSGNJ_D or - WILL_FIRE_RL_doFSQRT_D or - WILL_FIRE_RL_doFDIV_D or - WILL_FIRE_RL_doFNMSUB_D or - WILL_FIRE_RL_doFNMADD_D or - WILL_FIRE_RL_doFMSUB_D or - WILL_FIRE_RL_doFMADD_D or - WILL_FIRE_RL_doFMUL_D or - WILL_FIRE_RL_doFSUB_D or - WILL_FIRE_RL_doFADD_D or - WILL_FIRE_RL_doFCLASS_S or - WILL_FIRE_RL_doFLE_S or - WILL_FIRE_RL_doFLT_S or - WILL_FIRE_RL_doFEQ_S or - WILL_FIRE_RL_doFMV_X_W or - WILL_FIRE_RL_doFMV_W_X or - WILL_FIRE_RL_doFMAX_S or - WILL_FIRE_RL_doFMIN_S or - WILL_FIRE_RL_doFCVT_WU_S or - WILL_FIRE_RL_doFCVT_W_S or - WILL_FIRE_RL_doFCVT_S_WU or - WILL_FIRE_RL_doFCVT_S_W or - WILL_FIRE_RL_doFSGNJX_S or - WILL_FIRE_RL_doFSGNJN_S or - WILL_FIRE_RL_doFSGNJ_S or - WILL_FIRE_RL_doFSQRT_S or - WILL_FIRE_RL_doFDIV_S or - WILL_FIRE_RL_doFNMSUB_S or - WILL_FIRE_RL_doFNMADD_S or - WILL_FIRE_RL_doFMSUB_S or - WILL_FIRE_RL_doFMADD_S or - WILL_FIRE_RL_doFMUL_S or - WILL_FIRE_RL_doFSUB_S or - WILL_FIRE_RL_doFADD_S or WILL_FIRE_RL_rl_reset_end) - case (1'b1) - WILL_FIRE_RL_rl_reset_begin: stateR$D_IN = 2'd0; - EN_req: stateR$D_IN = 2'd1; - WILL_FIRE_RL_rl_get_fpu_result || WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJ_D: - stateR$D_IN = 2'd3; - WILL_FIRE_RL_doFSQRT_D || WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFADD_D: - stateR$D_IN = 2'd2; - WILL_FIRE_RL_doFCLASS_S || WILL_FIRE_RL_doFLE_S || WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJ_S: - stateR$D_IN = 2'd3; - WILL_FIRE_RL_doFSQRT_S || WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFADD_S: - stateR$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_end: stateR$D_IN = 2'd1; - default: stateR$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign stateR$EN = - WILL_FIRE_RL_rl_reset_begin || WILL_FIRE_RL_rl_reset_end || - EN_req || - WILL_FIRE_RL_doFSQRT_D || - WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFADD_D || - WILL_FIRE_RL_doFSQRT_S || - WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFADD_S || - WILL_FIRE_RL_rl_get_fpu_result || - WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJ_D || - WILL_FIRE_RL_doFCLASS_S || - WILL_FIRE_RL_doFLE_S || - WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJ_S ; - - // submodule fpu - always@(WILL_FIRE_RL_doFADD_S or - MUX_fpu$server_core_request_put_1__VAL_1 or - WILL_FIRE_RL_doFSUB_S or - MUX_fpu$server_core_request_put_1__VAL_2 or - WILL_FIRE_RL_doFMUL_S or - MUX_fpu$server_core_request_put_1__VAL_3 or - WILL_FIRE_RL_doFMADD_S or - MUX_fpu$server_core_request_put_1__VAL_4 or - WILL_FIRE_RL_doFMSUB_S or - MUX_fpu$server_core_request_put_1__VAL_5 or - WILL_FIRE_RL_doFNMADD_S or - MUX_fpu$server_core_request_put_1__VAL_6 or - WILL_FIRE_RL_doFNMSUB_S or - MUX_fpu$server_core_request_put_1__VAL_7 or - WILL_FIRE_RL_doFDIV_S or - MUX_fpu$server_core_request_put_1__VAL_8 or - WILL_FIRE_RL_doFSQRT_S or - MUX_fpu$server_core_request_put_1__VAL_9 or - WILL_FIRE_RL_doFADD_D or - MUX_fpu$server_core_request_put_1__VAL_10 or - WILL_FIRE_RL_doFSUB_D or - MUX_fpu$server_core_request_put_1__VAL_11 or - WILL_FIRE_RL_doFMUL_D or - MUX_fpu$server_core_request_put_1__VAL_12 or - WILL_FIRE_RL_doFMADD_D or - MUX_fpu$server_core_request_put_1__VAL_13 or - WILL_FIRE_RL_doFMSUB_D or - MUX_fpu$server_core_request_put_1__VAL_14 or - WILL_FIRE_RL_doFNMADD_D or - MUX_fpu$server_core_request_put_1__VAL_15 or - WILL_FIRE_RL_doFNMSUB_D or - MUX_fpu$server_core_request_put_1__VAL_16 or - WILL_FIRE_RL_doFDIV_D or - MUX_fpu$server_core_request_put_1__VAL_17 or - WILL_FIRE_RL_doFSQRT_D or MUX_fpu$server_core_request_put_1__VAL_18) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_doFADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_1; - WILL_FIRE_RL_doFSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_2; - WILL_FIRE_RL_doFMUL_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_3; - WILL_FIRE_RL_doFMADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_4; - WILL_FIRE_RL_doFMSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_5; - WILL_FIRE_RL_doFNMADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_6; - WILL_FIRE_RL_doFNMSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_7; - WILL_FIRE_RL_doFDIV_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_8; - WILL_FIRE_RL_doFSQRT_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_9; - WILL_FIRE_RL_doFADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_10; - WILL_FIRE_RL_doFSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_11; - WILL_FIRE_RL_doFMUL_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_12; - WILL_FIRE_RL_doFMADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_13; - WILL_FIRE_RL_doFMSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_14; - WILL_FIRE_RL_doFNMADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_15; - WILL_FIRE_RL_doFNMSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_16; - WILL_FIRE_RL_doFDIV_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_17; - WILL_FIRE_RL_doFSQRT_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_18; - default: fpu$server_core_request_put = - 202'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fpu$EN_server_core_request_put = - WILL_FIRE_RL_doFADD_S || WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFSQRT_S || - WILL_FIRE_RL_doFADD_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFSQRT_D ; - assign fpu$EN_server_core_response_get = MUX_dw_result$wset_1__SEL_1 ; - assign fpu$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_begin ; - assign fpu$EN_server_reset_response_get = CAN_FIRE_RL_rl_reset_end ; - - // submodule frmFpuF - assign frmFpuF$D_IN = 1'b0 ; - assign frmFpuF$ENQ = 1'b0 ; - assign frmFpuF$DEQ = 1'b0 ; - assign frmFpuF$CLR = CAN_FIRE_RL_rl_reset_begin ; - - // submodule resetReqsF - assign resetReqsF$ENQ = EN_server_reset_request_put ; - assign resetReqsF$DEQ = - fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ; - assign resetReqsF$CLR = 1'b0 ; - - // submodule resetRspsF - assign resetRspsF$ENQ = - fpu$RDY_server_reset_response_get && resetRspsF$FULL_N && - stateR == 2'd0 ; - assign resetRspsF$DEQ = EN_server_reset_response_get ; - assign resetRspsF$CLR = 1'b0 ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q60 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2087 ? - _theResult___snd__h69240 : - _theResult____h61070 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3406 ? - _theResult___snd__h128373 : - _theResult____h120074 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q65 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2571 ? - _theResult___snd__h87093 : - _theResult____h78794 ; - assign IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q100 = - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3479 ? - _theResult___snd__h118726 : - _theResult___snd__h137125 ; - assign IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q94 = - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3086 ? - _theResult___snd__h118726 : - 57'd0 ; - assign IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q62 = - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2249 ? - _theResult___snd__h77852 : - 57'd0 ; - assign IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q68 = - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2644 ? - _theResult___snd__h77852 : - _theResult___snd__h95729 ; - assign IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_7_ETC___d2831 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - ((_theResult___fst_exp__h69177 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard1080_0b0_requestR_BIT_191_0b1_reques_ETC__q86 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87)) : - ((_theResult___fst_exp__h77863 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9815_0b0_requestR_BIT_191_0b1_reques_ETC__q88 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1301 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5519_0b0_requestR_BIT_159_0b1_reques_ETC__q35 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36) : - ((x__h36264[10:0] == 11'd2047) ? - requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard6249_0b0_requestR_BIT_159_0b1_reques_ETC__q37 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1416 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 ? - guard__h35519 != 2'b0 : - x__h36264[10:0] != 11'd2047 && guard__h36249 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d345 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard519_0b0_requestR_BIT_159_0b1_request_ETC__q8 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9) : - ((x__h8064[7:0] == 8'd255) ? - requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard049_0b0_requestR_BIT_159_0b1_request_ETC__q10 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d495 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 ? - guard__h7519 != 2'b0 : - x__h8064[7:0] != 8'd255 && guard__h8049 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1598 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462 ? - guard__h45160 != 2'b0 : - x__h45904[10:0] != 11'd2047 && guard__h45889 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d808 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638 ? - guard__h13641 != 2'b0 : - x__h14182[7:0] != 8'd255 && guard__h14167 != 2'b0 ; - assign IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d2085 = - (_theResult____h61070[56] ? - 6'd0 : - (_theResult____h61070[55] ? - 6'd1 : - (_theResult____h61070[54] ? - 6'd2 : - (_theResult____h61070[53] ? - 6'd3 : - (_theResult____h61070[52] ? - 6'd4 : - (_theResult____h61070[51] ? - 6'd5 : - (_theResult____h61070[50] ? - 6'd6 : - (_theResult____h61070[49] ? - 6'd7 : - (_theResult____h61070[48] ? - 6'd8 : - (_theResult____h61070[47] ? - 6'd9 : - (_theResult____h61070[46] ? - 6'd10 : - (_theResult____h61070[45] ? - 6'd11 : - (_theResult____h61070[44] ? - 6'd12 : - (_theResult____h61070[43] ? - 6'd13 : - (_theResult____h61070[42] ? - 6'd14 : - (_theResult____h61070[41] ? - 6'd15 : - (_theResult____h61070[40] ? - 6'd16 : - (_theResult____h61070[39] ? - 6'd17 : - (_theResult____h61070[38] ? - 6'd18 : - (_theResult____h61070[37] ? - 6'd19 : - (_theResult____h61070[36] ? - 6'd20 : - (_theResult____h61070[35] ? - 6'd21 : - (_theResult____h61070[34] ? - 6'd22 : - (_theResult____h61070[33] ? - 6'd23 : - (_theResult____h61070[32] ? - 6'd24 : - (_theResult____h61070[31] ? - 6'd25 : - (_theResult____h61070[30] ? - 6'd26 : - (_theResult____h61070[29] ? - 6'd27 : - (_theResult____h61070[28] ? - 6'd28 : - (_theResult____h61070[27] ? - 6'd29 : - (_theResult____h61070[26] ? - 6'd30 : - (_theResult____h61070[25] ? - 6'd31 : - (_theResult____h61070[24] ? - 6'd32 : - (_theResult____h61070[23] ? - 6'd33 : - (_theResult____h61070[22] ? - 6'd34 : - (_theResult____h61070[21] ? - 6'd35 : - (_theResult____h61070[20] ? - 6'd36 : - (_theResult____h61070[19] ? - 6'd37 : - (_theResult____h61070[18] ? - 6'd38 : - (_theResult____h61070[17] ? - 6'd39 : - (_theResult____h61070[16] ? - 6'd40 : - (_theResult____h61070[15] ? - 6'd41 : - (_theResult____h61070[14] ? - 6'd42 : - (_theResult____h61070[13] ? - 6'd43 : - (_theResult____h61070[12] ? - 6'd44 : - (_theResult____h61070[11] ? - 6'd45 : - (_theResult____h61070[10] ? - 6'd46 : - (_theResult____h61070[9] ? - 6'd47 : - (_theResult____h61070[8] ? - 6'd48 : - (_theResult____h61070[7] ? - 6'd49 : - (_theResult____h61070[6] ? - 6'd50 : - (_theResult____h61070[5] ? - 6'd51 : - (_theResult____h61070[4] ? - 6'd52 : - (_theResult____h61070[3] ? - 6'd53 : - (_theResult____h61070[2] ? - 6'd54 : - (_theResult____h61070[1] ? - 6'd55 : - (_theResult____h61070[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d3404 = - (_theResult____h120074[56] ? - 6'd0 : - (_theResult____h120074[55] ? - 6'd1 : - (_theResult____h120074[54] ? - 6'd2 : - (_theResult____h120074[53] ? - 6'd3 : - (_theResult____h120074[52] ? - 6'd4 : - (_theResult____h120074[51] ? - 6'd5 : - (_theResult____h120074[50] ? - 6'd6 : - (_theResult____h120074[49] ? - 6'd7 : - (_theResult____h120074[48] ? - 6'd8 : - (_theResult____h120074[47] ? - 6'd9 : - (_theResult____h120074[46] ? - 6'd10 : - (_theResult____h120074[45] ? - 6'd11 : - (_theResult____h120074[44] ? - 6'd12 : - (_theResult____h120074[43] ? - 6'd13 : - (_theResult____h120074[42] ? - 6'd14 : - (_theResult____h120074[41] ? - 6'd15 : - (_theResult____h120074[40] ? - 6'd16 : - (_theResult____h120074[39] ? - 6'd17 : - (_theResult____h120074[38] ? - 6'd18 : - (_theResult____h120074[37] ? - 6'd19 : - (_theResult____h120074[36] ? - 6'd20 : - (_theResult____h120074[35] ? - 6'd21 : - (_theResult____h120074[34] ? - 6'd22 : - (_theResult____h120074[33] ? - 6'd23 : - (_theResult____h120074[32] ? - 6'd24 : - (_theResult____h120074[31] ? - 6'd25 : - (_theResult____h120074[30] ? - 6'd26 : - (_theResult____h120074[29] ? - 6'd27 : - (_theResult____h120074[28] ? - 6'd28 : - (_theResult____h120074[27] ? - 6'd29 : - (_theResult____h120074[26] ? - 6'd30 : - (_theResult____h120074[25] ? - 6'd31 : - (_theResult____h120074[24] ? - 6'd32 : - (_theResult____h120074[23] ? - 6'd33 : - (_theResult____h120074[22] ? - 6'd34 : - (_theResult____h120074[21] ? - 6'd35 : - (_theResult____h120074[20] ? - 6'd36 : - (_theResult____h120074[19] ? - 6'd37 : - (_theResult____h120074[18] ? - 6'd38 : - (_theResult____h120074[17] ? - 6'd39 : - (_theResult____h120074[16] ? - 6'd40 : - (_theResult____h120074[15] ? - 6'd41 : - (_theResult____h120074[14] ? - 6'd42 : - (_theResult____h120074[13] ? - 6'd43 : - (_theResult____h120074[12] ? - 6'd44 : - (_theResult____h120074[11] ? - 6'd45 : - (_theResult____h120074[10] ? - 6'd46 : - (_theResult____h120074[9] ? - 6'd47 : - (_theResult____h120074[8] ? - 6'd48 : - (_theResult____h120074[7] ? - 6'd49 : - (_theResult____h120074[6] ? - 6'd50 : - (_theResult____h120074[5] ? - 6'd51 : - (_theResult____h120074[4] ? - 6'd52 : - (_theResult____h120074[3] ? - 6'd53 : - (_theResult____h120074[2] ? - 6'd54 : - (_theResult____h120074[1] ? - 6'd55 : - (_theResult____h120074[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d2569 = - (_theResult____h78794[56] ? - 6'd0 : - (_theResult____h78794[55] ? - 6'd1 : - (_theResult____h78794[54] ? - 6'd2 : - (_theResult____h78794[53] ? - 6'd3 : - (_theResult____h78794[52] ? - 6'd4 : - (_theResult____h78794[51] ? - 6'd5 : - (_theResult____h78794[50] ? - 6'd6 : - (_theResult____h78794[49] ? - 6'd7 : - (_theResult____h78794[48] ? - 6'd8 : - (_theResult____h78794[47] ? - 6'd9 : - (_theResult____h78794[46] ? - 6'd10 : - (_theResult____h78794[45] ? - 6'd11 : - (_theResult____h78794[44] ? - 6'd12 : - (_theResult____h78794[43] ? - 6'd13 : - (_theResult____h78794[42] ? - 6'd14 : - (_theResult____h78794[41] ? - 6'd15 : - (_theResult____h78794[40] ? - 6'd16 : - (_theResult____h78794[39] ? - 6'd17 : - (_theResult____h78794[38] ? - 6'd18 : - (_theResult____h78794[37] ? - 6'd19 : - (_theResult____h78794[36] ? - 6'd20 : - (_theResult____h78794[35] ? - 6'd21 : - (_theResult____h78794[34] ? - 6'd22 : - (_theResult____h78794[33] ? - 6'd23 : - (_theResult____h78794[32] ? - 6'd24 : - (_theResult____h78794[31] ? - 6'd25 : - (_theResult____h78794[30] ? - 6'd26 : - (_theResult____h78794[29] ? - 6'd27 : - (_theResult____h78794[28] ? - 6'd28 : - (_theResult____h78794[27] ? - 6'd29 : - (_theResult____h78794[26] ? - 6'd30 : - (_theResult____h78794[25] ? - 6'd31 : - (_theResult____h78794[24] ? - 6'd32 : - (_theResult____h78794[23] ? - 6'd33 : - (_theResult____h78794[22] ? - 6'd34 : - (_theResult____h78794[21] ? - 6'd35 : - (_theResult____h78794[20] ? - 6'd36 : - (_theResult____h78794[19] ? - 6'd37 : - (_theResult____h78794[18] ? - 6'd38 : - (_theResult____h78794[17] ? - 6'd39 : - (_theResult____h78794[16] ? - 6'd40 : - (_theResult____h78794[15] ? - 6'd41 : - (_theResult____h78794[14] ? - 6'd42 : - (_theResult____h78794[13] ? - 6'd43 : - (_theResult____h78794[12] ? - 6'd44 : - (_theResult____h78794[11] ? - 6'd45 : - (_theResult____h78794[10] ? - 6'd46 : - (_theResult____h78794[9] ? - 6'd47 : - (_theResult____h78794[8] ? - 6'd48 : - (_theResult____h78794[7] ? - 6'd49 : - (_theResult____h78794[6] ? - 6'd50 : - (_theResult____h78794[5] ? - 6'd51 : - (_theResult____h78794[4] ? - 6'd52 : - (_theResult____h78794[3] ? - 6'd53 : - (_theResult____h78794[2] ? - 6'd54 : - (_theResult____h78794[1] ? - 6'd55 : - (_theResult____h78794[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d3648 = - (_theResult___fst_exp__h128310 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard20084_0b0_requestR_BITS_191_TO_160_E_ETC__q110 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2144 = - (guard__h61080 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h69177 : - _theResult___exp__h69703 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2146 = - (guard__h61080 == 2'b0) ? - _theResult___fst_exp__h69177 : - (requestR[191] ? - _theResult___exp__h69703 : - _theResult___fst_exp__h69177) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2731 = - (guard__h61080 == 2'b0 || requestR[191]) ? - sfdin__h69171[56:34] : - _theResult___sfd__h69704 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2733 = - (guard__h61080 == 2'b0) ? - sfdin__h69171[56:34] : - (requestR[191] ? - _theResult___sfd__h69704 : - sfdin__h69171[56:34]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3463 = - (guard__h120084 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h128310 : - _theResult___exp__h129039 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3465 = - (guard__h120084 == 2'b0) ? - _theResult___fst_exp__h128310 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h129039 : - _theResult___fst_exp__h128310) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3592 = - (guard__h120084 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - sfdin__h128304[56:5] : - _theResult___sfd__h129040 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3594 = - (guard__h120084 == 2'b0) ? - sfdin__h128304[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h129040 : - sfdin__h128304[56:5]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2628 = - (guard__h78804 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h87030 : - _theResult___exp__h87556 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2630 = - (guard__h78804 == 2'b0) ? - _theResult___fst_exp__h87030 : - (requestR[191] ? - _theResult___exp__h87556 : - _theResult___fst_exp__h87030) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2777 = - (guard__h78804 == 2'b0 || requestR[191]) ? - sfdin__h87024[56:34] : - _theResult___sfd__h87557 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2779 = - (guard__h78804 == 2'b0) ? - sfdin__h87024[56:34] : - (requestR[191] ? - _theResult___sfd__h87557 : - sfdin__h87024[56:34]) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3138 = - (guard__h110776 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h118737 : - _theResult___exp__h119392 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3140 = - (guard__h110776 == 2'b0) ? - _theResult___fst_exp__h118737 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h119392 : - _theResult___fst_exp__h118737) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3532 = - (guard__h129151 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h137141 : - _theResult___exp__h137821 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3534 = - (guard__h129151 == 2'b0) ? - _theResult___fst_exp__h137141 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h137821 : - _theResult___fst_exp__h137141) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3565 = - (guard__h110776 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___snd__h118688[56:5] : - _theResult___sfd__h119393 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3567 = - (guard__h110776 == 2'b0) ? - _theResult___snd__h118688[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h119393 : - _theResult___snd__h118688[56:5]) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3611 = - (guard__h129151 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___snd__h137087[56:5] : - _theResult___sfd__h137822 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3613 = - (guard__h129151 == 2'b0) ? - _theResult___snd__h137087[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h137822 : - _theResult___snd__h137087[56:5]) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2301 = - (guard__h69815 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h77863 : - _theResult___exp__h78315 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2303 = - (guard__h69815 == 2'b0) ? - _theResult___fst_exp__h77863 : - (requestR[191] ? - _theResult___exp__h78315 : - _theResult___fst_exp__h77863) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2697 = - (guard__h87668 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h95745 : - _theResult___exp__h96222 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2699 = - (guard__h87668 == 2'b0) ? - _theResult___fst_exp__h95745 : - (requestR[191] ? - _theResult___exp__h96222 : - _theResult___fst_exp__h95745) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2750 = - (guard__h69815 == 2'b0 || requestR[191]) ? - _theResult___snd__h77814[56:34] : - _theResult___sfd__h78316 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2752 = - (guard__h69815 == 2'b0) ? - _theResult___snd__h77814[56:34] : - (requestR[191] ? - _theResult___sfd__h78316 : - _theResult___snd__h77814[56:34]) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2796 = - (guard__h87668 == 2'b0 || requestR[191]) ? - _theResult___snd__h95691[56:34] : - _theResult___sfd__h96223 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2798 = - (guard__h87668 == 2'b0) ? - _theResult___snd__h95691[56:34] : - (requestR[191] ? - _theResult___sfd__h96223 : - _theResult___snd__h95691[56:34]) ; - assign IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3656 = - (_theResult___fst_exp__h137141 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard29151_0b0_requestR_BITS_191_TO_160_E_ETC__q112 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1322 = - (guard__h35519 == 2'b0) ? - 11'd0 : - (requestR[159] ? _theResult___exp__h36135 : 11'd0) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1348 = - (guard__h36249 == 2'b0 || requestR[159]) ? - x__h36264[10:0] : - _theResult___exp__h36891 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1350 = - (guard__h36249 == 2'b0) ? - x__h36264[10:0] : - (requestR[159] ? _theResult___exp__h36891 : x__h36264[10:0]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1371 = - (guard__h35519 == 2'b0 || requestR[159]) ? - sfd___3__h35509[54:3] : - _theResult___sfd__h36136 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1373 = - (guard__h35519 == 2'b0) ? - sfd___3__h35509[54:3] : - (requestR[159] ? - _theResult___sfd__h36136 : - sfd___3__h35509[54:3]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1389 = - (guard__h36249 == 2'b0 || requestR[159]) ? - sfd___3__h35509[53:2] : - _theResult___sfd__h36892 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1391 = - (guard__h36249 == 2'b0) ? - sfd___3__h35509[53:2] : - (requestR[159] ? - _theResult___sfd__h36892 : - sfd___3__h35509[53:2]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d367 = - (guard__h7519 == 2'b0) ? - 8'd0 : - (requestR[159] ? _theResult___exp__h7935 : 8'd0) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d393 = - (guard__h8049 == 2'b0 || requestR[159]) ? - x__h8064[7:0] : - _theResult___exp__h8488 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d395 = - (guard__h8049 == 2'b0) ? - x__h8064[7:0] : - (requestR[159] ? _theResult___exp__h8488 : x__h8064[7:0]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d416 = - (guard__h7519 == 2'b0 || requestR[159]) ? - sfd___3__h7509[31:9] : - _theResult___sfd__h7936 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d418 = - (guard__h7519 == 2'b0) ? - sfd___3__h7509[31:9] : - (requestR[159] ? - _theResult___sfd__h7936 : - sfd___3__h7509[31:9]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d434 = - (guard__h8049 == 2'b0 || requestR[159]) ? - sfd___3__h7509[30:8] : - _theResult___sfd__h8489 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d436 = - (guard__h8049 == 2'b0) ? - sfd___3__h7509[30:8] : - (requestR[159] ? - _theResult___sfd__h8489 : - sfd___3__h7509[30:8]) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1047 = - (sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308[22] || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1016) ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - (IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d1020 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1045) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1051 = - (sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308 != 23'd0 && - !sV2_sfd__h1308[22]) ? - res__h18225 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1050 ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1060 = - IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d1020 ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1059 ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1062 = - (sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308[22]) ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - (IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1016 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1060) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1066 = - (sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308 != 23'd0 && - !sV2_sfd__h1308[22]) ? - res__h18225 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1065 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1048 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22]) ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1047 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1050 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22] && - sV2_exp__h1307 == 8'd255 && - sV2_sfd__h1308[22]) ? - 64'hFFFFFFFF7FC00000 : - { 32'hFFFFFFFF, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1048 } ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1052 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22]) ? - res__h17988 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1051 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1063 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22]) ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1062 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1065 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22] && - sV2_exp__h1307 == 8'd255 && - sV2_sfd__h1308[22]) ? - 64'hFFFFFFFF7FC00000 : - { 32'hFFFFFFFF, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1063 } ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1067 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22]) ? - res__h17988 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1066 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1131 = - (sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0) ? - res___1__h26243 : - ((sV1_exp__h1204 == 8'd0) ? res___1__h26262 : res__h26278) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1132 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 == 23'd0) ? - res___1__h26233 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1131 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 = - ((sV1_exp__h1204 == 8'd0) ? - (sV1_sfd__h1205[22] ? - 6'd2 : - (sV1_sfd__h1205[21] ? - 6'd3 : - (sV1_sfd__h1205[20] ? - 6'd4 : - (sV1_sfd__h1205[19] ? - 6'd5 : - (sV1_sfd__h1205[18] ? - 6'd6 : - (sV1_sfd__h1205[17] ? - 6'd7 : - (sV1_sfd__h1205[16] ? - 6'd8 : - (sV1_sfd__h1205[15] ? - 6'd9 : - (sV1_sfd__h1205[14] ? - 6'd10 : - (sV1_sfd__h1205[13] ? - 6'd11 : - (sV1_sfd__h1205[12] ? - 6'd12 : - (sV1_sfd__h1205[11] ? - 6'd13 : - (sV1_sfd__h1205[10] ? - 6'd14 : - (sV1_sfd__h1205[9] ? - 6'd15 : - (sV1_sfd__h1205[8] ? - 6'd16 : - (sV1_sfd__h1205[7] ? - 6'd17 : - (sV1_sfd__h1205[6] ? - 6'd18 : - (sV1_sfd__h1205[5] ? - 6'd19 : - (sV1_sfd__h1205[4] ? - 6'd20 : - (sV1_sfd__h1205[3] ? - 6'd21 : - (sV1_sfd__h1205[2] ? - 6'd22 : - (sV1_sfd__h1205[1] ? - 6'd23 : - (sV1_sfd__h1205[0] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3624 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0) ? - _theResult___snd_fst_sfd__h99811 : - _theResult___fst_sfd__h137938 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3660 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 || - (sV1_exp__h1204 == 8'd255 || sV1_exp__h1204 == 8'd0) && - sV1_sfd__h1205 == 23'd0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((sV1_exp__h1204 == 8'd0) ? - IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d3640 : - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3658) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3695 = - (sV1_exp__h1204 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 && - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674[4] : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 && - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691[4] ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3698 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0) ? - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22] : - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3695 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3705 = - (sV1_exp__h1204 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 && - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674[3] : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 && - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691[3] ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3719 = - (sV1_exp__h1204 == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 || - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674[2] : - !SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 || - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3717 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3731 = - (sV1_exp__h1204 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 && - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 || - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674[1]) : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 && - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3729 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3743 = - (sV1_exp__h1204 == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 || - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674[0] : - !SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 || - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3741 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d904 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 == 23'd0) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d833 : - ((sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0) ? - 32'd0 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d902) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d963 = - (sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0) ? - 32'd0 : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934[19] ? - 32'hFFFFFFFF : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d961) ; - assign IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1242 = - sfd__h2605[31] ? - 6'd0 : - (sfd__h2605[30] ? - 6'd1 : - (sfd__h2605[29] ? - 6'd2 : - (sfd__h2605[28] ? - 6'd3 : - (sfd__h2605[27] ? - 6'd4 : - (sfd__h2605[26] ? - 6'd5 : - (sfd__h2605[25] ? - 6'd6 : - (sfd__h2605[24] ? - 6'd7 : - (sfd__h2605[23] ? - 6'd8 : - (sfd__h2605[22] ? - 6'd9 : - (sfd__h2605[21] ? - 6'd10 : - (sfd__h2605[20] ? - 6'd11 : - (sfd__h2605[19] ? - 6'd12 : - (sfd__h2605[18] ? - 6'd13 : - (sfd__h2605[17] ? - 6'd14 : - (sfd__h2605[16] ? - 6'd15 : - (sfd__h2605[15] ? - 6'd16 : - (sfd__h2605[14] ? - 6'd17 : - (sfd__h2605[13] ? - 6'd18 : - (sfd__h2605[12] ? - 6'd19 : - (sfd__h2605[11] ? - 6'd20 : - (sfd__h2605[10] ? - 6'd21 : - (sfd__h2605[9] ? - 6'd22 : - (sfd__h2605[8] ? - 6'd23 : - (sfd__h2605[7] ? - 6'd24 : - (sfd__h2605[6] ? - 6'd25 : - (sfd__h2605[5] ? - 6'd26 : - (sfd__h2605[4] ? - 6'd27 : - (sfd__h2605[3] ? - 6'd28 : - (sfd__h2605[2] ? - 6'd29 : - (sfd__h2605[1] ? - 6'd30 : - (sfd__h2605[0] ? - 6'd31 : - 6'd55))))))))))))))))))))))))))))))) ; - assign IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d275 = - sfd__h2605[31] ? - 6'd0 : - (sfd__h2605[30] ? - 6'd1 : - (sfd__h2605[29] ? - 6'd2 : - (sfd__h2605[28] ? - 6'd3 : - (sfd__h2605[27] ? - 6'd4 : - (sfd__h2605[26] ? - 6'd5 : - (sfd__h2605[25] ? - 6'd6 : - (sfd__h2605[24] ? - 6'd7 : - (sfd__h2605[23] ? - 6'd8 : - (sfd__h2605[22] ? - 6'd9 : - (sfd__h2605[21] ? - 6'd10 : - (sfd__h2605[20] ? - 6'd11 : - (sfd__h2605[19] ? - 6'd12 : - (sfd__h2605[18] ? - 6'd13 : - (sfd__h2605[17] ? - 6'd14 : - (sfd__h2605[16] ? - 6'd15 : - (sfd__h2605[15] ? - 6'd16 : - (sfd__h2605[14] ? - 6'd17 : - (sfd__h2605[13] ? - 6'd18 : - (sfd__h2605[12] ? - 6'd19 : - (sfd__h2605[11] ? - 6'd20 : - (sfd__h2605[10] ? - 6'd21 : - (sfd__h2605[9] ? - 6'd22 : - (sfd__h2605[8] ? - 6'd23 : - (sfd__h2605[7] ? - 6'd24 : - (sfd__h2605[6] ? - 6'd25 : - (sfd__h2605[5] ? - 6'd26 : - (sfd__h2605[4] ? - 6'd27 : - (sfd__h2605[3] ? - 6'd28 : - (sfd__h2605[2] ? - 6'd29 : - (sfd__h2605[1] ? - 6'd30 : - (sfd__h2605[0] ? - 6'd31 : - 6'd32))))))))))))))))))))))))))))))) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d900 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d873 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d894 ? - ((x__h15999[56:25] == 32'h7FFFFFFF) ? - x__h15999[56:25] : - x__h15999[56:25] + 32'd1) : - x__h15999[56:25]) : - 32'd0 ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d902 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838 == - 20'd1048545) ? - ((_theResult_____2__h15258[32:31] == 2'b11) ? - _theResult_____2__h15258[31:0] : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d833) : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871[19] ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d833 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d900) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d926 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838 == - 20'd1048545) ? - _theResult_____2__h15258[32:31] == 2'b11 && - guard__h15256 != 2'd0 : - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d873 || - guard__h15810 != 2'd0) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d961 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d936 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d955 ? - ((x__h17039[56:25] == 32'hFFFFFFFF) ? - x__h17039[56:25] : - x__h17039[56:25] + 32'd1) : - x__h17039[56:25]) : - 32'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1686 = - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1659 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1680 ? - ((x__h47920[85:54] == 32'h7FFFFFFF) ? - x__h47920[85:54] : - x__h47920[85:54] + 32'd1) : - x__h47920[85:54]) : - 32'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1688 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624 == - 24'd16777185) ? - ((_theResult_____2__h47179[32:31] == 2'b11) ? - _theResult_____2__h47179[31:0] : - IF_requestR_3_BIT_191_202_THEN_2147483648_ELSE_ETC___d1619) : - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657[23] ? - IF_requestR_3_BIT_191_202_THEN_2147483648_ELSE_ETC___d1619 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1686) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1712 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624 == - 24'd16777185) ? - _theResult_____2__h47179[32:31] == 2'b11 && - guard__h47177 != 2'd0 : - !NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1659 || - guard__h47731 != 2'd0) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1747 = - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1722 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1741 ? - ((x__h48943[85:54] == 32'hFFFFFFFF) ? - x__h48943[85:54] : - x__h48943[85:54] + 32'd1) : - x__h48943[85:54]) : - 32'd0 ; - assign IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d1302 = - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248) ? - requestR[159] : - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1301 ; - assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d3640 = - (!_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 || - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 || - _theResult___fst_exp__h118737 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10776_0b0_requestR_BITS_191_TO_160_E_ETC__q108 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109) ; - assign IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1045 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1044 ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 ; - assign IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1059 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1044 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1040 = - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1029 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1031 : - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1034 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 && - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1036 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3478 = - ((SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q99[10], - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q99 }) - - 12'd3074 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3658 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 ? - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d3648 : - IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3656) : - requestR[191:160] == 32'hFFFFFFFF && requestR[159] ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3717 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691[2] : - _theResult___fst_exp__h137922 == 11'd2047 && - _theResult___fst_sfd__h137923 == 52'd0 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3729 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691[1] : - _theResult___fst_exp__h137141 == 11'd0 && - guard__h129151 != 2'b0 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3741 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691[0] : - _theResult___fst_exp__h137141 != 11'd2047 && - guard__h129151 != 2'b0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2643 = - ((SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q67[7], - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q67 }) - - 9'd386 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2849 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - ((_theResult___fst_exp__h87030 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard8804_0b0_requestR_BIT_191_0b1_reques_ETC__q90 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91)) : - ((_theResult___fst_exp__h95745 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard7668_0b0_requestR_BIT_191_0b1_reques_ETC__q92 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93)) ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2927 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898[2] : - _theResult___fst_exp__h96323 == 8'd255 && - _theResult___fst_sfd__h96324 == 23'd0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2940 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898[1] : - _theResult___fst_exp__h95745 == 8'd0 && guard__h87668 != 2'b0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2953 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898[0] : - _theResult___fst_exp__h95745 != 8'd255 && - guard__h87668 != 2'b0 ; - assign IF_requestR_3_BITS_126_TO_116_754_EQ_2047_755__ETC___d3802 = - (requestR[126:116] == 11'd2047 && requestR[115] || - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3771) ? - requestR[191:128] : - (requestR_3_BITS_126_TO_116_754_EQ_0_768_AND_re_ETC___d3775 ? - requestR[127:64] : - res__h142948) ; - assign IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d1020 = - sV2_exp__h1307 == 8'd0 && sV2_sfd__h1308 == 23'd0 && - requestR[127:96] == 32'hFFFFFFFF && - requestR[95] && - sV1_exp__h1204 == 8'd0 && - sV1_sfd__h1205 == 23'd0 && - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ; - assign IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1399 = - (requestR[159:128] == 32'd0 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248) ? - 52'd0 : - _theResult___snd_fst_sfd__h36995 ; - assign IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1581 = - (requestR[159:128] == 32'd0 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 || - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461) ? - 52'd0 : - _theResult___snd_fst_sfd__h46634 ; - assign IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d405 = - (requestR[159:128] == 32'd0 || - !sfd__h2605[31] && !sfd__h2605[30] && !sfd__h2605[29] && - !sfd__h2605[28] && - !sfd__h2605[27] && - !sfd__h2605[26] && - !sfd__h2605[25] && - !sfd__h2605[24] && - !sfd__h2605[23] && - !sfd__h2605[22] && - !sfd__h2605[21] && - !sfd__h2605[20] && - !sfd__h2605[19] && - !sfd__h2605[18] && - !sfd__h2605[17] && - !sfd__h2605[16] && - !sfd__h2605[15] && - !sfd__h2605[14] && - !sfd__h2605[13] && - !sfd__h2605[12] && - !sfd__h2605[11] && - !sfd__h2605[10] && - !sfd__h2605[9] && - !sfd__h2605[8] && - !sfd__h2605[7] && - !sfd__h2605[6] && - !sfd__h2605[5] && - !sfd__h2605[4] && - !sfd__h2605[3] && - !sfd__h2605[2] && - !sfd__h2605[1] && - !sfd__h2605[0]) ? - 8'd0 : - _theResult___snd_fst_exp__h8597 ; - assign IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d722 = - (requestR[159:128] == 32'd0 || - !requestR[159] && - NOT_requestR_3_BIT_158_07_08_AND_NOT_requestR__ETC___d598) ? - 8'd0 : - _theResult___snd_fst_exp__h14714 ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d1749 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 32'd0 : - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720[23] ? - 32'hFFFFFFFF : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1747) ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3815 = - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3771 ? - requestR[127:64] : - (requestR_3_BITS_126_TO_116_754_EQ_0_768_AND_re_ETC___d3775 ? - requestR[191:128] : - res__h147441) ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3881 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - res___1__h155301 : - ((requestR[190:180] == 11'd0) ? - res___1__h155320 : - res__h155336) ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 = - ((requestR[190:180] == 11'd0) ? - (requestR[179] ? - 6'd2 : - (requestR[178] ? - 6'd3 : - (requestR[177] ? - 6'd4 : - (requestR[176] ? - 6'd5 : - (requestR[175] ? - 6'd6 : - (requestR[174] ? - 6'd7 : - (requestR[173] ? - 6'd8 : - (requestR[172] ? - 6'd9 : - (requestR[171] ? - 6'd10 : - (requestR[170] ? - 6'd11 : - (requestR[169] ? - 6'd12 : - (requestR[168] ? - 6'd13 : - (requestR[167] ? - 6'd14 : - (requestR[166] ? - 6'd15 : - (requestR[165] ? - 6'd16 : - (requestR[164] ? - 6'd17 : - (requestR[163] ? - 6'd18 : - (requestR[162] ? - 6'd19 : - (requestR[161] ? - 6'd20 : - (requestR[160] ? - 6'd21 : - (requestR[159] ? - 6'd22 : - (requestR[158] ? - 6'd23 : - (requestR[157] ? - 6'd24 : - (requestR[156] ? - 6'd25 : - (requestR[155] ? - 6'd26 : - (requestR[154] ? - 6'd27 : - (requestR[153] ? - 6'd28 : - (requestR[152] ? - 6'd29 : - (requestR[151] ? - 6'd30 : - (requestR[150] ? - 6'd31 : - (requestR[149] ? - 6'd32 : - (requestR[148] ? - 6'd33 : - (requestR[147] ? - 6'd34 : - (requestR[146] ? - 6'd35 : - (requestR[145] ? - 6'd36 : - (requestR[144] ? - 6'd37 : - (requestR[143] ? - 6'd38 : - (requestR[142] ? - 6'd39 : - (requestR[141] ? - 6'd40 : - (requestR[140] ? - 6'd41 : - (requestR[139] ? - 6'd42 : - (requestR[138] ? - 6'd43 : - (requestR[137] ? - 6'd44 : - (requestR[136] ? - 6'd45 : - (requestR[135] ? - 6'd46 : - (requestR[134] ? - 6'd47 : - (requestR[133] ? - 6'd48 : - (requestR[132] ? - 6'd49 : - (requestR[131] ? - 6'd50 : - (requestR[130] ? - 6'd51 : - (requestR[129] ? - 6'd52 : - (requestR[128] ? - 6'd53 : - 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2851 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 ? - IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_7_ETC___d2831 : - requestR[191]) : - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 ? - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2849 : - requestR[191]) ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2902 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2884 : - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 && - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898[4] ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2913 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2909 : - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 && - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898[3] ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2929 = - (requestR[190:180] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2921 : - !SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 || - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2927 ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2942 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2936 : - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 && - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2940 ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2955 = - (requestR[190:180] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2949 : - !SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 || - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2953 ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d1690 = - (requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0) ? - IF_requestR_3_BIT_191_202_THEN_2147483648_ELSE_ETC___d1619 : - ((requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 32'd0 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1688) ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d2809 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - _theResult___snd_fst_sfd__h53394 : - _theResult___fst_sfd__h96339 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1006 = - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22] && - sV2_exp__h1307 == 8'd255 && - sV2_sfd__h1308 != 23'd0 && - !sV2_sfd__h1308[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1016 = - sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159] && - sV2_exp__h1307 == 8'd0 && - sV2_sfd__h1308 == 23'd0 && - (requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1029 = - sV1_exp__h1204 < sV2_exp__h1307 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 = - sV1_exp__h1204 == sV2_exp__h1307 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1031 = - sV1_sfd__h1205 < sV2_sfd__h1308 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1034 = - sV1_exp__h1204 <= sV2_exp__h1307 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1036 = - sV1_sfd__h1205 <= sV2_sfd__h1308 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1054 = - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22] || - sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308 != 23'd0 && - !sV2_sfd__h1308[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1087 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1054 || - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22] || - sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1098 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1034 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1036) && - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1029 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 || - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1031) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1102 = - sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0 && - sV2_exp__h1307 == 8'd0 && - sV2_sfd__h1308 == 23'd0 || - NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1101 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[158:128] : - 31'h7FC00000 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d832 = - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 || - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) && - sV1_exp__h1204 == 8'd255 && - sV1_sfd__h1205 == 23'd0 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d833 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 32'h80000000 : - 32'h7FFFFFFF ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836 = - sV1_exp__h1204 - 8'd127 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - -b__h15323 : - b__h15323 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d965 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 32'd0 : - ((sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 == 23'd0) ? - 32'hFFFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d963) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d973 = - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 || - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 == 23'd0 || - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d936 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d955 && - x__h17039[56:25] == 32'hFFFFFFFF) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d984 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d973, - 3'd0, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d978 } == - 5'd0 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d973 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1648 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h47177 == 2'b10) ? - IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[53] : - guard__h47177 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h47177 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[85] && - guard__h47177 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1680 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h47731 == 2'b10) ? - x__h47920[54] : - guard__h47731 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h47731 != 2'd0 : - requestR[194:192] == 3'h1 && x__h47920[85] && - guard__h47731 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1741 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h48722 == 2'b10) ? - x__h48943[54] : - guard__h48722 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h48722 != 2'd0 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d862 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h15256 == 2'b10) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[24] : - guard__h15256 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h15256 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[56] && - guard__h15256 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d894 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h15810 == 2'b10) ? - x__h15999[25] : - guard__h15810 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h15810 != 2'd0 : - requestR[194:192] == 3'h1 && x__h15999[56] && - guard__h15810 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d955 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h16818 == 2'b10) ? - x__h17039[25] : - guard__h16818 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h16818 != 2'd0 ; - assign IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1456 = - requestR[159] ? - 6'd0 : - (requestR[158] ? - 6'd1 : - (requestR[157] ? - 6'd2 : - (requestR[156] ? - 6'd3 : - (requestR[155] ? - 6'd4 : - (requestR[154] ? - 6'd5 : - (requestR[153] ? - 6'd6 : - (requestR[152] ? - 6'd7 : - (requestR[151] ? - 6'd8 : - (requestR[150] ? - 6'd9 : - (requestR[149] ? - 6'd10 : - (requestR[148] ? - 6'd11 : - (requestR[147] ? - 6'd12 : - (requestR[146] ? - 6'd13 : - (requestR[145] ? - 6'd14 : - (requestR[144] ? - 6'd15 : - (requestR[143] ? - 6'd16 : - (requestR[142] ? - 6'd17 : - (requestR[141] ? - 6'd18 : - (requestR[140] ? - 6'd19 : - (requestR[139] ? - 6'd20 : - (requestR[138] ? - 6'd21 : - (requestR[137] ? - 6'd22 : - (requestR[136] ? - 6'd23 : - (requestR[135] ? - 6'd24 : - (requestR[134] ? - 6'd25 : - (requestR[133] ? - 6'd26 : - (requestR[132] ? - 6'd27 : - (requestR[131] ? - 6'd28 : - (requestR[130] ? - 6'd29 : - (requestR[129] ? - 6'd30 : - (requestR[128] ? - 6'd31 : - 6'd55))))))))))))))))))))))))))))))) ; - assign IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d632 = - requestR[159] ? - 6'd0 : - (requestR[158] ? - 6'd1 : - (requestR[157] ? - 6'd2 : - (requestR[156] ? - 6'd3 : - (requestR[155] ? - 6'd4 : - (requestR[154] ? - 6'd5 : - (requestR[153] ? - 6'd6 : - (requestR[152] ? - 6'd7 : - (requestR[151] ? - 6'd8 : - (requestR[150] ? - 6'd9 : - (requestR[149] ? - 6'd10 : - (requestR[148] ? - 6'd11 : - (requestR[147] ? - 6'd12 : - (requestR[146] ? - 6'd13 : - (requestR[145] ? - 6'd14 : - (requestR[144] ? - 6'd15 : - (requestR[143] ? - 6'd16 : - (requestR[142] ? - 6'd17 : - (requestR[141] ? - 6'd18 : - (requestR[140] ? - 6'd19 : - (requestR[139] ? - 6'd20 : - (requestR[138] ? - 6'd21 : - (requestR[137] ? - 6'd22 : - (requestR[136] ? - 6'd23 : - (requestR[135] ? - 6'd24 : - (requestR[134] ? - 6'd25 : - (requestR[133] ? - 6'd26 : - (requestR[132] ? - 6'd27 : - (requestR[131] ? - 6'd28 : - (requestR[130] ? - 6'd29 : - (requestR[129] ? - 6'd30 : - (requestR[128] ? - 6'd31 : - 6'd32))))))))))))))))))))))))))))))) ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d486 = - (sfd__h2605[31] || sfd__h2605[30] || sfd__h2605[29] || - sfd__h2605[28] || - sfd__h2605[27] || - sfd__h2605[26] || - sfd__h2605[25] || - sfd__h2605[24] || - sfd__h2605[23] || - sfd__h2605[22] || - sfd__h2605[21] || - sfd__h2605[20] || - sfd__h2605[19] || - sfd__h2605[18] || - sfd__h2605[17] || - sfd__h2605[16] || - sfd__h2605[15] || - sfd__h2605[14] || - sfd__h2605[13] || - sfd__h2605[12] || - sfd__h2605[11] || - sfd__h2605[10] || - sfd__h2605[9] || - sfd__h2605[8] || - sfd__h2605[7] || - sfd__h2605[6] || - sfd__h2605[5] || - sfd__h2605[4] || - sfd__h2605[3] || - sfd__h2605[2] || - sfd__h2605[1] || - sfd__h2605[0]) && - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 && - _theResult___fst_exp__h8588 == 8'd255 && - _theResult___fst_sfd__h8589 == 23'd0) ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d489 = - (sfd__h2605[31] || sfd__h2605[30] || sfd__h2605[29] || - sfd__h2605[28] || - sfd__h2605[27] || - sfd__h2605[26] || - sfd__h2605[25] || - sfd__h2605[24] || - sfd__h2605[23] || - sfd__h2605[22] || - sfd__h2605[21] || - sfd__h2605[20] || - sfd__h2605[19] || - sfd__h2605[18] || - sfd__h2605[17] || - sfd__h2605[16] || - sfd__h2605[15] || - sfd__h2605[14] || - sfd__h2605[13] || - sfd__h2605[12] || - sfd__h2605[11] || - sfd__h2605[10] || - sfd__h2605[9] || - sfd__h2605[8] || - sfd__h2605[7] || - sfd__h2605[6] || - sfd__h2605[5] || - sfd__h2605[4] || - sfd__h2605[3] || - sfd__h2605[2] || - sfd__h2605[1] || - sfd__h2605[0]) && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d498 = - (sfd__h2605[31] || sfd__h2605[30] || sfd__h2605[29] || - sfd__h2605[28] || - sfd__h2605[27] || - sfd__h2605[26] || - sfd__h2605[25] || - sfd__h2605[24] || - sfd__h2605[23] || - sfd__h2605[22] || - sfd__h2605[21] || - sfd__h2605[20] || - sfd__h2605[19] || - sfd__h2605[18] || - sfd__h2605[17] || - sfd__h2605[16] || - sfd__h2605[15] || - sfd__h2605[14] || - sfd__h2605[13] || - sfd__h2605[12] || - sfd__h2605[11] || - sfd__h2605[10] || - sfd__h2605[9] || - sfd__h2605[8] || - sfd__h2605[7] || - sfd__h2605[6] || - sfd__h2605[5] || - sfd__h2605[4] || - sfd__h2605[3] || - sfd__h2605[2] || - sfd__h2605[1] || - sfd__h2605[0]) && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 && - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d495 ; - assign IF_requestR_3_BIT_191_202_THEN_2147483648_ELSE_ETC___d1619 = - requestR[191] ? 32'h80000000 : 32'h7FFFFFFF ; - assign IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631 = - requestR[191] ? -b__h47244 : b__h47244 ; - assign IF_requestR_3_BIT_191_202_THEN_NOT_requestR_3__ETC___d3795 = - requestR[191] ? - !requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3784 || - requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 && - !requestR_3_BITS_179_TO_128_611_ULE_requestR_3__ETC___d3787 : - requestR_3_BITS_190_TO_180_609_ULT_requestR_3__ETC___d3791 || - requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 && - requestR_3_BITS_179_TO_128_611_ULT_requestR_3__ETC___d3792 ; - assign IF_sfd___33631_BIT_7_THEN_2_ELSE_0__q21 = - sfd___3__h13631[7] ? 2'd2 : 2'd0 ; - assign IF_sfd___33631_BIT_8_THEN_2_ELSE_0__q20 = - sfd___3__h13631[8] ? 2'd2 : 2'd0 ; - assign IF_sfd___3509_BIT_7_THEN_2_ELSE_0__q7 = - sfd___3__h7509[7] ? 2'd2 : 2'd0 ; - assign IF_sfd___3509_BIT_8_THEN_2_ELSE_0__q6 = - sfd___3__h7509[8] ? 2'd2 : 2'd0 ; - assign IF_sfd___35150_BIT_1_THEN_2_ELSE_0__q48 = - sfd___3__h45150[1] ? 2'd2 : 2'd0 ; - assign IF_sfd___35150_BIT_2_THEN_2_ELSE_0__q47 = - sfd___3__h45150[2] ? 2'd2 : 2'd0 ; - assign IF_sfd___35509_BIT_1_THEN_2_ELSE_0__q34 = - sfd___3__h35509[1] ? 2'd2 : 2'd0 ; - assign IF_sfd___35509_BIT_2_THEN_2_ELSE_0__q33 = - sfd___3__h35509[2] ? 2'd2 : 2'd0 ; - assign IF_sfdin28304_BIT_4_THEN_2_ELSE_0__q98 = - sfdin__h128304[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin7024_BIT_33_THEN_2_ELSE_0__q66 = - sfdin__h87024[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin9171_BIT_33_THEN_2_ELSE_0__q61 = - sfdin__h69171[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd18688_BIT_4_THEN_2_ELSE_0__q95 = - _theResult___snd__h118688[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd37087_BIT_4_THEN_2_ELSE_0__q101 = - _theResult___snd__h137087[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd5691_BIT_33_THEN_2_ELSE_0__q69 = - _theResult___snd__h95691[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd7814_BIT_33_THEN_2_ELSE_0__q63 = - _theResult___snd__h77814[33] ? 2'd2 : 2'd0 ; - assign IF_x5999_BIT_24_THEN_2_ELSE_0__q31 = x__h15999[24] ? 2'd2 : 2'd0 ; - assign IF_x7039_BIT_24_THEN_2_ELSE_0__q32 = x__h17039[24] ? 2'd2 : 2'd0 ; - assign IF_x7920_BIT_53_THEN_2_ELSE_0__q58 = x__h47920[53] ? 2'd2 : 2'd0 ; - assign IF_x8943_BIT_53_THEN_2_ELSE_0__q59 = x__h48943[53] ? 2'd2 : 2'd0 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838 = - -{ {12{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836[7]}}, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836 } ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d870 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838 + - 20'd32 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d870 - - 20'd2 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d873 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871 ^ - 20'h80000) <= - 20'd524320 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d870 - - 20'd1 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d936 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934 ^ - 20'h80000) <= - 20'd524320 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624 = - -{ {13{requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622[10]}}, - requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622 } ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1656 = - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624 + - 24'd32 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657 = - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1656 - - 24'd2 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1659 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657 ^ - 24'h800000) <= - 24'd8388640 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720 = - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1656 - - 24'd1 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1722 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720 ^ - 24'h800000) <= - 24'd8388640 ; - assign NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2921 = - !_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 || - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869[2] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2949 = - !_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 || - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869[0] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881[0]) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1043 = - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0 || - sV2_exp__h1307 != 8'd0 || - sV2_sfd__h1308 != 23'd0) && - requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d1042 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1044 = - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV2_exp__h1307 != 8'd255 || sV2_sfd__h1308 == 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1043 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1097 = - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1029 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 || - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1031) && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1034 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1036) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1103 = - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV2_exp__h1307 != 8'd255 || sV2_sfd__h1308 == 23'd0) && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1102 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1119 = - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV2_exp__h1307 != 8'd255 || sV2_sfd__h1308 == 23'd0) && - (requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d1042 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1102) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057 = - !sV1_sfd__h1205[21] && !sV1_sfd__h1205[20] && - !sV1_sfd__h1205[19] && - !sV1_sfd__h1205[18] && - !sV1_sfd__h1205[17] && - !sV1_sfd__h1205[16] && - !sV1_sfd__h1205[15] && - !sV1_sfd__h1205[14] && - !sV1_sfd__h1205[13] && - !sV1_sfd__h1205[12] && - !sV1_sfd__h1205[11] && - !sV1_sfd__h1205[10] && - !sV1_sfd__h1205[9] && - !sV1_sfd__h1205[8] && - !sV1_sfd__h1205[7] && - !sV1_sfd__h1205[6] && - !sV1_sfd__h1205[5] && - !sV1_sfd__h1205[4] && - !sV1_sfd__h1205[3] && - !sV1_sfd__h1205[2] && - !sV1_sfd__h1205[1] && - !sV1_sfd__h1205[0] ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d915 = - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - ((NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838 == - 20'd1048545) ? - _theResult_____2__h15258[32:31] != 2'b11 : - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d873 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d894 && - x__h15999[56:25] == 32'h7FFFFFFF) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d978 = - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d936 || - guard__h16818 != 2'd0) ; - assign NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d283 = - !sfd__h2605[31] && !sfd__h2605[30] && !sfd__h2605[29] && - !sfd__h2605[28] && - !sfd__h2605[27] && - !sfd__h2605[26] && - !sfd__h2605[25] && - !sfd__h2605[24] && - !sfd__h2605[23] && - !sfd__h2605[22] && - !sfd__h2605[21] && - !sfd__h2605[20] && - !sfd__h2605[19] && - !sfd__h2605[18] && - !sfd__h2605[17] && - !sfd__h2605[16] && - !sfd__h2605[15] && - !sfd__h2605[14] && - !sfd__h2605[13] && - !sfd__h2605[12] && - !sfd__h2605[11] && - !sfd__h2605[10] && - !sfd__h2605[9] && - !sfd__h2605[8] && - !sfd__h2605[7] && - !sfd__h2605[6] && - !sfd__h2605[5] && - !sfd__h2605[4] && - !sfd__h2605[3] && - !sfd__h2605[2] && - !sfd__h2605[1] && - !sfd__h2605[0] || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 ; - assign NOT_requestR_3_BITS_159_TO_128_44_EQ_0_45_46_A_ETC___d800 = - requestR[159:128] != 32'd0 && - (requestR[159] || - requestR_3_BIT_158_07_OR_requestR_3_BIT_157_09_ETC___d789) && - (!_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638 && - _theResult___fst_exp__h14705 == 8'd255 && - _theResult___fst_sfd__h14706 == 23'd0) ; - assign NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1701 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - ((NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624 == - 24'd16777185) ? - _theResult_____2__h47179[32:31] != 2'b11 : - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1659 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1680 && - x__h47920[85:54] == 32'h7FFFFFFF) ; - assign NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1764 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - !NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1722 || - guard__h48722 != 2'd0) ; - assign NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3799 = - (requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0 || - requestR[126:116] != 11'd0 || - requestR[115:64] != 52'd0) && - (requestR[191] && !requestR[127] || - (requestR[191] || !requestR[127]) && - IF_requestR_3_BIT_191_202_THEN_NOT_requestR_3__ETC___d3795) ; - assign NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3860 = - (requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - (requestR[191] && !requestR[127] || - (requestR[191] || !requestR[127]) && - IF_requestR_3_BIT_191_202_THEN_NOT_requestR_3__ETC___d3795 || - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3843) ; - assign NOT_requestR_3_BITS_190_TO_180_609_ULT_request_ETC___d3839 = - !requestR_3_BITS_190_TO_180_609_ULT_requestR_3__ETC___d3791 && - (!requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 || - !requestR_3_BITS_179_TO_128_611_ULT_requestR_3__ETC___d3792) && - requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3784 && - (!requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 || - requestR_3_BITS_179_TO_128_611_ULE_requestR_3__ETC___d3787) ; - assign NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1101 = - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159] || - requestR[127:96] == 32'hFFFFFFFF && requestR[95]) && - (requestR[191:160] == 32'hFFFFFFFF && requestR[159] || - requestR[127:96] != 32'hFFFFFFFF || - !requestR[95]) && - ((requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ? - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1097 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1098) ; - assign NOT_requestR_3_BIT_158_07_08_AND_NOT_requestR__ETC___d598 = - !requestR[158] && !requestR[157] && !requestR[156] && - !requestR[155] && - !requestR[154] && - !requestR[153] && - !requestR[152] && - !requestR[151] && - !requestR[150] && - !requestR[149] && - !requestR[148] && - !requestR[147] && - !requestR[146] && - !requestR[145] && - !requestR[144] && - !requestR[143] && - !requestR[142] && - !requestR[141] && - !requestR[140] && - !requestR[139] && - !requestR[138] && - !requestR[137] && - !requestR[136] && - !requestR[135] && - !requestR[134] && - !requestR[133] && - !requestR[132] && - !requestR[131] && - !requestR[130] && - !requestR[129] && - !requestR[128] ; - assign NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192 = - !requestR[179] && !requestR[178] && !requestR[177] && - !requestR[176] && - !requestR[175] && - !requestR[174] && - !requestR[173] && - !requestR[172] && - !requestR[171] && - !requestR[170] && - !requestR[169] && - !requestR[168] && - !requestR[167] && - !requestR[166] && - !requestR[165] && - !requestR[164] && - !requestR[163] && - !requestR[162] && - !requestR[161] && - !requestR[160] && - !requestR[159] && - NOT_requestR_3_BIT_158_07_08_AND_NOT_requestR__ETC___d598 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155 = - { {4{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836[7]}}, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836 } ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155 + - 12'd1023 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q99 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96[10:0] - - 11'd1023 ; - assign SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322 = - { requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622[10], - requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622 } ; - assign SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 = - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 = - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322 + - 12'd127 ; - assign SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q67 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64[7:0] - - 8'd127 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2087 = - ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d2085 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869 = - { 3'd0, - _theResult___fst_exp__h69177 == 8'd0 && - (sfdin__h69171[56:34] == 23'd0 || guard__h61080 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h69804 == 8'd255 && - _theResult___fst_sfd__h69805 == 23'd0, - 1'd0, - _theResult___fst_exp__h69177 != 8'd255 && - guard__h61080 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3406 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d3404 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691 = - { 3'd0, - _theResult___fst_exp__h128310 == 11'd0 && - (sfdin__h128304[56:5] == 52'd0 || guard__h120084 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h129140 == 11'd2047 && - _theResult___fst_sfd__h129141 == 52'd0, - 1'd0, - _theResult___fst_exp__h128310 != 11'd2047 && - guard__h120084 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2571 = - ({ 3'd0, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d2569 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898 = - { 3'd0, - _theResult___fst_exp__h87030 == 8'd0 && - (sfdin__h87024[56:34] == 23'd0 || guard__h78804 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h87657 == 8'd255 && - _theResult___fst_sfd__h87658 == 23'd0, - 1'd0, - _theResult___fst_exp__h87030 != 8'd255 && - guard__h78804 != 2'b0 } ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3086 = - ({ 6'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3479 = - ({ 6'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 } ^ - 12'h800) <= - (IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3478 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674 = - { 3'd0, - _theResult___fst_exp__h118737 == 11'd0 && - guard__h110776 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h119493 == 11'd2047 && - _theResult___fst_sfd__h119494 == 52'd0, - 1'd0, - _theResult___fst_exp__h118737 != 11'd2047 && - guard__h110776 != 2'b0 } ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2249 = - ({ 3'd0, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2644 = - ({ 3'd0, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 } ^ - 9'h100) <= - (IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2643 ^ - 9'h100) ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881 = - { 3'd0, - _theResult___fst_exp__h77863 == 8'd0 && guard__h69815 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h78416 == 8'd255 && - _theResult___fst_sfd__h78417 == 23'd0, - 1'd0, - _theResult___fst_exp__h77863 != 8'd255 && - guard__h69815 != 2'b0 } ; - assign _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d3162 = - b__h15323 >> - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d3158 ; - assign _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_609__ETC___d2329 = - sfd__h53440 >> - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_609_ETC___d2325 ; - assign _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78 = - { 33'h1AAAAAAAA, - requestR[63:32] == 32'hFFFFFFFF && requestR[31], - (requestR[63:32] == 32'hFFFFFFFF) ? - requestR[30:0] : - 31'h7FC00000 } ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1851 = - 12'd3074 - - { 6'd0, - requestR[179] ? - 6'd0 : - (requestR[178] ? - 6'd1 : - (requestR[177] ? - 6'd2 : - (requestR[176] ? - 6'd3 : - (requestR[175] ? - 6'd4 : - (requestR[174] ? - 6'd5 : - (requestR[173] ? - 6'd6 : - (requestR[172] ? - 6'd7 : - (requestR[171] ? - 6'd8 : - (requestR[170] ? - 6'd9 : - (requestR[169] ? - 6'd10 : - (requestR[168] ? - 6'd11 : - (requestR[167] ? - 6'd12 : - (requestR[166] ? - 6'd13 : - (requestR[165] ? - 6'd14 : - (requestR[164] ? - 6'd15 : - (requestR[163] ? - 6'd16 : - (requestR[162] ? - 6'd17 : - (requestR[161] ? - 6'd18 : - (requestR[160] ? - 6'd19 : - (requestR[159] ? - 6'd20 : - (requestR[158] ? - 6'd21 : - (requestR[157] ? - 6'd22 : - (requestR[156] ? - 6'd23 : - (requestR[155] ? - 6'd24 : - (requestR[154] ? - 6'd25 : - (requestR[153] ? - 6'd26 : - (requestR[152] ? - 6'd27 : - (requestR[151] ? - 6'd28 : - (requestR[150] ? - 6'd29 : - (requestR[149] ? - 6'd30 : - (requestR[148] ? - 6'd31 : - (requestR[147] ? - 6'd32 : - (requestR[146] ? - 6'd33 : - (requestR[145] ? - 6'd34 : - (requestR[144] ? - 6'd35 : - (requestR[143] ? - 6'd36 : - (requestR[142] ? - 6'd37 : - (requestR[141] ? - 6'd38 : - (requestR[140] ? - 6'd39 : - (requestR[139] ? - 6'd40 : - (requestR[138] ? - 6'd41 : - (requestR[137] ? - 6'd42 : - (requestR[136] ? - 6'd43 : - (requestR[135] ? - 6'd44 : - (requestR[134] ? - 6'd45 : - (requestR[133] ? - 6'd46 : - (requestR[132] ? - 6'd47 : - (requestR[131] ? - 6'd48 : - (requestR[130] ? - 6'd49 : - (requestR[129] ? - 6'd50 : - (requestR[128] ? - 6'd51 : - 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 = - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1851 ^ - 12'h800) <= - 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 = - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1851 ^ - 12'h800) < - 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2884 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869[4] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881[4]) ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2909 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869[3] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881[3]) ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2936 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869[1] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881[1]) ; - assign _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d3158 = - 12'd3074 - - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245 = - (12'd32 - - { 6'd0, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1242 }) - - 12'd1 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245 ^ - 12'h800) <= - 12'd3071 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245 ^ - 12'h800) < - 12'd974 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245 ^ - 12'h800) < - 12'd1026 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278 = - (9'd32 - - { 3'd0, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d275 }) - - 9'd1 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278 ^ - 9'h100) <= - 9'd383 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278 ^ - 9'h100) < - 9'd107 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278 ^ - 9'h100) < - 9'd130 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459 = - (12'd32 - - { 6'd0, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1456 }) - - 12'd1 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459 ^ - 12'h800) <= - 12'd3071 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459 ^ - 12'h800) < - 12'd974 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459 ^ - 12'h800) < - 12'd1026 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635 = - (9'd32 - - { 3'd0, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d632 }) - - 9'd1 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635 ^ - 9'h100) <= - 9'd383 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635 ^ - 9'h100) < - 9'd107 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635 ^ - 9'h100) < - 9'd130 ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3012 = - 12'd3970 - - { 7'd0, - sV1_sfd__h1205[22] ? - 5'd0 : - (sV1_sfd__h1205[21] ? - 5'd1 : - (sV1_sfd__h1205[20] ? - 5'd2 : - (sV1_sfd__h1205[19] ? - 5'd3 : - (sV1_sfd__h1205[18] ? - 5'd4 : - (sV1_sfd__h1205[17] ? - 5'd5 : - (sV1_sfd__h1205[16] ? - 5'd6 : - (sV1_sfd__h1205[15] ? - 5'd7 : - (sV1_sfd__h1205[14] ? - 5'd8 : - (sV1_sfd__h1205[13] ? - 5'd9 : - (sV1_sfd__h1205[12] ? - 5'd10 : - (sV1_sfd__h1205[11] ? - 5'd11 : - (sV1_sfd__h1205[10] ? - 5'd12 : - (sV1_sfd__h1205[9] ? - 5'd13 : - (sV1_sfd__h1205[8] ? - 5'd14 : - (sV1_sfd__h1205[7] ? - 5'd15 : - (sV1_sfd__h1205[6] ? - 5'd16 : - (sV1_sfd__h1205[5] ? - 5'd17 : - (sV1_sfd__h1205[4] ? - 5'd18 : - (sV1_sfd__h1205[3] ? - 5'd19 : - (sV1_sfd__h1205[2] ? - 5'd20 : - (sV1_sfd__h1205[1] ? - 5'd21 : - (sV1_sfd__h1205[0] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 = - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3012 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 = - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3012 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_609_ETC___d2325 = - 12'd3970 - - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322 ; - assign _theResult_____2__h15258 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d862 ? - out1___1__h15750 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[56:24] ; - assign _theResult_____2__h47179 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1648 ? - out1___1__h47671 : - IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[85:53] ; - assign _theResult____h120074 = - ((_3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d3158 ^ - 12'h800) < - 12'd2105) ? - result__h120687 : - ((value__h15325 == 25'd0) ? b__h15323 : 57'd1) ; - assign _theResult____h61070 = - (value__h47246 == 54'd0) ? sfd__h53440 : 57'd1 ; - assign _theResult____h78794 = - ((_3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_609_ETC___d2325 ^ - 12'h800) < - 12'd2105) ? - result__h79407 : - _theResult____h61070 ; - assign _theResult___exp__h119392 = - sfd__h118755[53] ? - ((_theResult___fst_exp__h118737 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h137957) : - ((_theResult___fst_exp__h118737 == 11'd0 && - sfd__h118755[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h118737) ; - assign _theResult___exp__h129039 = - sfd__h128402[53] ? - ((_theResult___fst_exp__h128310 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h137987) : - ((_theResult___fst_exp__h128310 == 11'd0 && - sfd__h128402[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h128310) ; - assign _theResult___exp__h137821 = - sfd__h137160[53] ? - ((_theResult___fst_exp__h137141 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h138011) : - ((_theResult___fst_exp__h137141 == 11'd0 && - sfd__h137160[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h137141) ; - assign _theResult___exp__h14054 = - (sfd__h13658[24] || sfd__h13658[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h14606 = - sfd__h14197[24] ? - ((x__h14182[7:0] == 8'd254) ? - 8'd255 : - din_inc___2_exp__h14744) : - ((x__h14182[7:0] == 8'd0 && sfd__h14197[24:23] == 2'b01) ? - 8'd1 : - x__h14182[7:0]) ; - assign _theResult___exp__h36135 = - (sfd__h35536[53] || sfd__h35536[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h36891 = - sfd__h36279[53] ? - ((x__h36264[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h37034) : - ((x__h36264[10:0] == 11'd0 && sfd__h36279[53:52] == 2'b01) ? - 11'd1 : - x__h36264[10:0]) ; - assign _theResult___exp__h45776 = - (sfd__h45177[53] || sfd__h45177[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h46531 = - sfd__h45919[53] ? - ((x__h45904[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h46669) : - ((x__h45904[10:0] == 11'd0 && sfd__h45919[53:52] == 2'b01) ? - 11'd1 : - x__h45904[10:0]) ; - assign _theResult___exp__h69703 = - sfd__h69269[24] ? - ((_theResult___fst_exp__h69177 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h96354) : - ((_theResult___fst_exp__h69177 == 8'd0 && - sfd__h69269[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h69177) ; - assign _theResult___exp__h78315 = - sfd__h77881[24] ? - ((_theResult___fst_exp__h77863 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h96378) : - ((_theResult___fst_exp__h77863 == 8'd0 && - sfd__h77881[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h77863) ; - assign _theResult___exp__h7935 = - (sfd__h7536[24] || sfd__h7536[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h8488 = - sfd__h8079[24] ? - ((x__h8064[7:0] == 8'd254) ? 8'd255 : din_inc___2_exp__h8631) : - ((x__h8064[7:0] == 8'd0 && sfd__h8079[24:23] == 2'b01) ? - 8'd1 : - x__h8064[7:0]) ; - assign _theResult___exp__h87556 = - sfd__h87122[24] ? - ((_theResult___fst_exp__h87030 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h96408) : - ((_theResult___fst_exp__h87030 == 8'd0 && - sfd__h87122[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h87030) ; - assign _theResult___exp__h96222 = - sfd__h95764[24] ? - ((_theResult___fst_exp__h95745 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h96432) : - ((_theResult___fst_exp__h95745 == 8'd0 && - sfd__h95764[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h95745) ; - assign _theResult___fst_exp__h103664 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 11'd2047 : - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 ; - assign _theResult___fst_exp__h118728 = - 11'd897 - - { 5'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 } ; - assign _theResult___fst_exp__h118734 = - (sV1_exp__h1204 == 8'd0 && !sV1_sfd__h1205[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057 || - !_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3086) ? - 11'd0 : - _theResult___fst_exp__h118728 ; - assign _theResult___fst_exp__h118737 = - (sV1_exp__h1204 == 8'd0) ? - _theResult___fst_exp__h118734 : - 11'd897 ; - assign _theResult___fst_exp__h119490 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q103 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 ; - assign _theResult___fst_exp__h119493 = - (_theResult___fst_exp__h118737 == 11'd2047) ? - _theResult___fst_exp__h118737 : - _theResult___fst_exp__h119490 ; - assign _theResult___fst_exp__h128310 = - _theResult____h120074[56] ? - 11'd2 : - _theResult___fst_exp__h128384 ; - assign _theResult___fst_exp__h128375 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d3404 } ; - assign _theResult___fst_exp__h128381 = - (!_theResult____h120074[56] && !_theResult____h120074[55] && - !_theResult____h120074[54] && - !_theResult____h120074[53] && - !_theResult____h120074[52] && - !_theResult____h120074[51] && - !_theResult____h120074[50] && - !_theResult____h120074[49] && - !_theResult____h120074[48] && - !_theResult____h120074[47] && - !_theResult____h120074[46] && - !_theResult____h120074[45] && - !_theResult____h120074[44] && - !_theResult____h120074[43] && - !_theResult____h120074[42] && - !_theResult____h120074[41] && - !_theResult____h120074[40] && - !_theResult____h120074[39] && - !_theResult____h120074[38] && - !_theResult____h120074[37] && - !_theResult____h120074[36] && - !_theResult____h120074[35] && - !_theResult____h120074[34] && - !_theResult____h120074[33] && - !_theResult____h120074[32] && - !_theResult____h120074[31] && - !_theResult____h120074[30] && - !_theResult____h120074[29] && - !_theResult____h120074[28] && - !_theResult____h120074[27] && - !_theResult____h120074[26] && - !_theResult____h120074[25] && - !_theResult____h120074[24] && - !_theResult____h120074[23] && - !_theResult____h120074[22] && - !_theResult____h120074[21] && - !_theResult____h120074[20] && - !_theResult____h120074[19] && - !_theResult____h120074[18] && - !_theResult____h120074[17] && - !_theResult____h120074[16] && - !_theResult____h120074[15] && - !_theResult____h120074[14] && - !_theResult____h120074[13] && - !_theResult____h120074[12] && - !_theResult____h120074[11] && - !_theResult____h120074[10] && - !_theResult____h120074[9] && - !_theResult____h120074[8] && - !_theResult____h120074[7] && - !_theResult____h120074[6] && - !_theResult____h120074[5] && - !_theResult____h120074[4] && - !_theResult____h120074[3] && - !_theResult____h120074[2] && - !_theResult____h120074[1] && - !_theResult____h120074[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3406) ? - 11'd0 : - _theResult___fst_exp__h128375 ; - assign _theResult___fst_exp__h128384 = - (!_theResult____h120074[56] && _theResult____h120074[55]) ? - 11'd1 : - _theResult___fst_exp__h128381 ; - assign _theResult___fst_exp__h129137 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q105 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 ; - assign _theResult___fst_exp__h129140 = - (_theResult___fst_exp__h128310 == 11'd2047) ? - _theResult___fst_exp__h128310 : - _theResult___fst_exp__h129137 ; - assign _theResult___fst_exp__h137093 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96[10:0] == - 11'd0) ? - 11'd1 : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96[10:0] ; - assign _theResult___fst_exp__h137132 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96[10:0] - - { 5'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 } ; - assign _theResult___fst_exp__h137138 = - (sV1_exp__h1204 == 8'd0 && !sV1_sfd__h1205[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057 || - !_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3479) ? - 11'd0 : - _theResult___fst_exp__h137132 ; - assign _theResult___fst_exp__h137141 = - (sV1_exp__h1204 == 8'd0) ? - _theResult___fst_exp__h137138 : - _theResult___fst_exp__h137093 ; - assign _theResult___fst_exp__h137919 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q107 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 ; - assign _theResult___fst_exp__h137922 = - (_theResult___fst_exp__h137141 == 11'd2047) ? - _theResult___fst_exp__h137141 : - _theResult___fst_exp__h137919 ; - assign _theResult___fst_exp__h137931 = - (sV1_exp__h1204 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 ? - _theResult___snd_fst_exp__h119496 : - _theResult___fst_exp__h103664) : - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 ? - _theResult___snd_fst_exp__h137925 : - _theResult___fst_exp__h103664) ; - assign _theResult___fst_exp__h137934 = - (sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h137931 ; - assign _theResult___fst_exp__h14150 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3641_0b0_0_0b1_0_0b10_out_exp4057_0b_ETC__q22 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard3641_ETC__q24 ; - assign _theResult___fst_exp__h14702 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_x4182_ETC__q26 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716 ; - assign _theResult___fst_exp__h14705 = - (x__h14182[7:0] == 8'd255) ? - x__h14182[7:0] : - _theResult___fst_exp__h14702 ; - assign _theResult___fst_exp__h36232 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5519_0b0_0_0b1_0_0b10_out_exp6138_0b_ETC__q44 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325 ; - assign _theResult___fst_exp__h36988 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_x626_ETC__q40 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 ; - assign _theResult___fst_exp__h36991 = - (x__h36264[10:0] == 11'd2047) ? - x__h36264[10:0] : - _theResult___fst_exp__h36988 ; - assign _theResult___fst_exp__h45872 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5160_0b0_0_0b1_0_0b10_out_exp5779_0b_ETC__q49 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5160_ETC__q51 ; - assign _theResult___fst_exp__h46627 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_x590_ETC__q53 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540 ; - assign _theResult___fst_exp__h46630 = - (x__h45904[10:0] == 11'd2047) ? - x__h45904[10:0] : - _theResult___fst_exp__h46627 ; - assign _theResult___fst_exp__h61052 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 8'd255 : - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 ; - assign _theResult___fst_exp__h69177 = - _theResult____h61070[56] ? 8'd2 : _theResult___fst_exp__h69251 ; - assign _theResult___fst_exp__h69242 = - 8'd0 - - { 2'd0, - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d2085 } ; - assign _theResult___fst_exp__h69248 = - (!_theResult____h61070[56] && !_theResult____h61070[55] && - !_theResult____h61070[54] && - !_theResult____h61070[53] && - !_theResult____h61070[52] && - !_theResult____h61070[51] && - !_theResult____h61070[50] && - !_theResult____h61070[49] && - !_theResult____h61070[48] && - !_theResult____h61070[47] && - !_theResult____h61070[46] && - !_theResult____h61070[45] && - !_theResult____h61070[44] && - !_theResult____h61070[43] && - !_theResult____h61070[42] && - !_theResult____h61070[41] && - !_theResult____h61070[40] && - !_theResult____h61070[39] && - !_theResult____h61070[38] && - !_theResult____h61070[37] && - !_theResult____h61070[36] && - !_theResult____h61070[35] && - !_theResult____h61070[34] && - !_theResult____h61070[33] && - !_theResult____h61070[32] && - !_theResult____h61070[31] && - !_theResult____h61070[30] && - !_theResult____h61070[29] && - !_theResult____h61070[28] && - !_theResult____h61070[27] && - !_theResult____h61070[26] && - !_theResult____h61070[25] && - !_theResult____h61070[24] && - !_theResult____h61070[23] && - !_theResult____h61070[22] && - !_theResult____h61070[21] && - !_theResult____h61070[20] && - !_theResult____h61070[19] && - !_theResult____h61070[18] && - !_theResult____h61070[17] && - !_theResult____h61070[16] && - !_theResult____h61070[15] && - !_theResult____h61070[14] && - !_theResult____h61070[13] && - !_theResult____h61070[12] && - !_theResult____h61070[11] && - !_theResult____h61070[10] && - !_theResult____h61070[9] && - !_theResult____h61070[8] && - !_theResult____h61070[7] && - !_theResult____h61070[6] && - !_theResult____h61070[5] && - !_theResult____h61070[4] && - !_theResult____h61070[3] && - !_theResult____h61070[2] && - !_theResult____h61070[1] && - !_theResult____h61070[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2087) ? - 8'd0 : - _theResult___fst_exp__h69242 ; - assign _theResult___fst_exp__h69251 = - (!_theResult____h61070[56] && _theResult____h61070[55]) ? - 8'd1 : - _theResult___fst_exp__h69248 ; - assign _theResult___fst_exp__h69801 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q71 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 ; - assign _theResult___fst_exp__h69804 = - (_theResult___fst_exp__h69177 == 8'd255) ? - _theResult___fst_exp__h69177 : - _theResult___fst_exp__h69801 ; - assign _theResult___fst_exp__h77854 = - 8'd129 - - { 2'd0, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 } ; - assign _theResult___fst_exp__h77860 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192 || - !_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2249) ? - 8'd0 : - _theResult___fst_exp__h77854 ; - assign _theResult___fst_exp__h77863 = - (requestR[190:180] == 11'd0) ? - _theResult___fst_exp__h77860 : - 8'd129 ; - assign _theResult___fst_exp__h78413 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q73 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 ; - assign _theResult___fst_exp__h78416 = - (_theResult___fst_exp__h77863 == 8'd255) ? - _theResult___fst_exp__h77863 : - _theResult___fst_exp__h78413 ; - assign _theResult___fst_exp__h8032 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard519_0b0_0_0b1_0_0b10_out_exp938_0b11_ETC__q13 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370 ; - assign _theResult___fst_exp__h8585 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_x064_BI_ETC__q15 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 ; - assign _theResult___fst_exp__h8588 = - (x__h8064[7:0] == 8'd255) ? - x__h8064[7:0] : - _theResult___fst_exp__h8585 ; - assign _theResult___fst_exp__h87030 = - _theResult____h78794[56] ? 8'd2 : _theResult___fst_exp__h87104 ; - assign _theResult___fst_exp__h87095 = - 8'd0 - - { 2'd0, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d2569 } ; - assign _theResult___fst_exp__h87101 = - (!_theResult____h78794[56] && !_theResult____h78794[55] && - !_theResult____h78794[54] && - !_theResult____h78794[53] && - !_theResult____h78794[52] && - !_theResult____h78794[51] && - !_theResult____h78794[50] && - !_theResult____h78794[49] && - !_theResult____h78794[48] && - !_theResult____h78794[47] && - !_theResult____h78794[46] && - !_theResult____h78794[45] && - !_theResult____h78794[44] && - !_theResult____h78794[43] && - !_theResult____h78794[42] && - !_theResult____h78794[41] && - !_theResult____h78794[40] && - !_theResult____h78794[39] && - !_theResult____h78794[38] && - !_theResult____h78794[37] && - !_theResult____h78794[36] && - !_theResult____h78794[35] && - !_theResult____h78794[34] && - !_theResult____h78794[33] && - !_theResult____h78794[32] && - !_theResult____h78794[31] && - !_theResult____h78794[30] && - !_theResult____h78794[29] && - !_theResult____h78794[28] && - !_theResult____h78794[27] && - !_theResult____h78794[26] && - !_theResult____h78794[25] && - !_theResult____h78794[24] && - !_theResult____h78794[23] && - !_theResult____h78794[22] && - !_theResult____h78794[21] && - !_theResult____h78794[20] && - !_theResult____h78794[19] && - !_theResult____h78794[18] && - !_theResult____h78794[17] && - !_theResult____h78794[16] && - !_theResult____h78794[15] && - !_theResult____h78794[14] && - !_theResult____h78794[13] && - !_theResult____h78794[12] && - !_theResult____h78794[11] && - !_theResult____h78794[10] && - !_theResult____h78794[9] && - !_theResult____h78794[8] && - !_theResult____h78794[7] && - !_theResult____h78794[6] && - !_theResult____h78794[5] && - !_theResult____h78794[4] && - !_theResult____h78794[3] && - !_theResult____h78794[2] && - !_theResult____h78794[1] && - !_theResult____h78794[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2571) ? - 8'd0 : - _theResult___fst_exp__h87095 ; - assign _theResult___fst_exp__h87104 = - (!_theResult____h78794[56] && _theResult____h78794[55]) ? - 8'd1 : - _theResult___fst_exp__h87101 ; - assign _theResult___fst_exp__h87654 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q75 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 ; - assign _theResult___fst_exp__h87657 = - (_theResult___fst_exp__h87030 == 8'd255) ? - _theResult___fst_exp__h87030 : - _theResult___fst_exp__h87654 ; - assign _theResult___fst_exp__h95697 = - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64[7:0] == - 8'd0) ? - 8'd1 : - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64[7:0] ; - assign _theResult___fst_exp__h95736 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64[7:0] - - { 2'd0, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 } ; - assign _theResult___fst_exp__h95742 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192 || - !_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2644) ? - 8'd0 : - _theResult___fst_exp__h95736 ; - assign _theResult___fst_exp__h95745 = - (requestR[190:180] == 11'd0) ? - _theResult___fst_exp__h95742 : - _theResult___fst_exp__h95697 ; - assign _theResult___fst_exp__h96320 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q77 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 ; - assign _theResult___fst_exp__h96323 = - (_theResult___fst_exp__h95745 == 8'd255) ? - _theResult___fst_exp__h95745 : - _theResult___fst_exp__h96320 ; - assign _theResult___fst_exp__h96332 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 ? - _theResult___snd_fst_exp__h78419 : - _theResult___fst_exp__h61052) : - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 ? - _theResult___snd_fst_exp__h96326 : - _theResult___fst_exp__h61052) ; - assign _theResult___fst_exp__h96335 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 8'd0 : - _theResult___fst_exp__h96332 ; - assign _theResult___fst_sfd__h103665 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 52'd0 : - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 ; - assign _theResult___fst_sfd__h119491 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q115 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 ; - assign _theResult___fst_sfd__h119494 = - (_theResult___fst_exp__h118737 == 11'd2047) ? - _theResult___snd__h118688[56:5] : - _theResult___fst_sfd__h119491 ; - assign _theResult___fst_sfd__h129138 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q117 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 ; - assign _theResult___fst_sfd__h129141 = - (_theResult___fst_exp__h128310 == 11'd2047) ? - sfdin__h128304[56:5] : - _theResult___fst_sfd__h129138 ; - assign _theResult___fst_sfd__h137920 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q119 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 ; - assign _theResult___fst_sfd__h137923 = - (_theResult___fst_exp__h137141 == 11'd2047) ? - _theResult___snd__h137087[56:5] : - _theResult___fst_sfd__h137920 ; - assign _theResult___fst_sfd__h137932 = - (sV1_exp__h1204 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 ? - _theResult___snd_fst_sfd__h119497 : - _theResult___fst_sfd__h103665) : - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 ? - _theResult___snd_fst_sfd__h137926 : - _theResult___fst_sfd__h103665) ; - assign _theResult___fst_sfd__h137938 = - ((sV1_exp__h1204 == 8'd255 || sV1_exp__h1204 == 8'd0) && - sV1_sfd__h1205 == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h137932 ; - assign _theResult___fst_sfd__h14151 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q30 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739 ; - assign _theResult___fst_sfd__h14703 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q28 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754 ; - assign _theResult___fst_sfd__h14706 = - (x__h14182[7:0] == 8'd255) ? - sfd___3__h13631[30:8] : - _theResult___fst_sfd__h14703 ; - assign _theResult___fst_sfd__h36233 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q46 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 ; - assign _theResult___fst_sfd__h36989 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q42 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 ; - assign _theResult___fst_sfd__h36992 = - (x__h36264[10:0] == 11'd2047) ? - sfd___3__h35509[53:2] : - _theResult___fst_sfd__h36989 ; - assign _theResult___fst_sfd__h45873 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q57 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562 ; - assign _theResult___fst_sfd__h46628 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q55 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577 ; - assign _theResult___fst_sfd__h46631 = - (x__h45904[10:0] == 11'd2047) ? - sfd___3__h45150[53:2] : - _theResult___fst_sfd__h46628 ; - assign _theResult___fst_sfd__h49736 = { 1'd1, requestR[178:128] } ; - assign _theResult___fst_sfd__h61053 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 23'd0 : - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 ; - assign _theResult___fst_sfd__h69802 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q79 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 ; - assign _theResult___fst_sfd__h69805 = - (_theResult___fst_exp__h69177 == 8'd255) ? - sfdin__h69171[56:34] : - _theResult___fst_sfd__h69802 ; - assign _theResult___fst_sfd__h78414 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q81 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 ; - assign _theResult___fst_sfd__h78417 = - (_theResult___fst_exp__h77863 == 8'd255) ? - _theResult___snd__h77814[56:34] : - _theResult___fst_sfd__h78414 ; - assign _theResult___fst_sfd__h8033 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q17 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 ; - assign _theResult___fst_sfd__h8586 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q19 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 ; - assign _theResult___fst_sfd__h8589 = - (x__h8064[7:0] == 8'd255) ? - sfd___3__h7509[30:8] : - _theResult___fst_sfd__h8586 ; - assign _theResult___fst_sfd__h87655 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q83 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 ; - assign _theResult___fst_sfd__h87658 = - (_theResult___fst_exp__h87030 == 8'd255) ? - sfdin__h87024[56:34] : - _theResult___fst_sfd__h87655 ; - assign _theResult___fst_sfd__h96321 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q85 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 ; - assign _theResult___fst_sfd__h96324 = - (_theResult___fst_exp__h95745 == 8'd255) ? - _theResult___snd__h95691[56:34] : - _theResult___fst_sfd__h96321 ; - assign _theResult___fst_sfd__h96333 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 ? - _theResult___snd_fst_sfd__h78420 : - _theResult___fst_sfd__h61053) : - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 ? - _theResult___snd_fst_sfd__h96327 : - _theResult___fst_sfd__h61053) ; - assign _theResult___fst_sfd__h96339 = - ((requestR[190:180] == 11'd2047 || requestR[190:180] == 11'd0) && - requestR[179:128] == 52'd0) ? - 23'd0 : - _theResult___fst_sfd__h96333 ; - assign _theResult___fst_sfd__h98183 = { 1'd1, sV1_sfd__h1205[21:0] } ; - assign _theResult___sfd__h119393 = - sfd__h118755[53] ? - ((_theResult___fst_exp__h118737 == 11'd2046) ? - 52'd0 : - sfd__h118755[52:1]) : - sfd__h118755[51:0] ; - assign _theResult___sfd__h129040 = - sfd__h128402[53] ? - ((_theResult___fst_exp__h128310 == 11'd2046) ? - 52'd0 : - sfd__h128402[52:1]) : - sfd__h128402[51:0] ; - assign _theResult___sfd__h137822 = - sfd__h137160[53] ? - ((_theResult___fst_exp__h137141 == 11'd2046) ? - 52'd0 : - sfd__h137160[52:1]) : - sfd__h137160[51:0] ; - assign _theResult___sfd__h14055 = - sfd__h13658[24] ? sfd__h13658[23:1] : sfd__h13658[22:0] ; - assign _theResult___sfd__h14607 = - sfd__h14197[24] ? - ((x__h14182[7:0] == 8'd254) ? 23'd0 : sfd__h14197[23:1]) : - sfd__h14197[22:0] ; - assign _theResult___sfd__h36136 = - sfd__h35536[53] ? sfd__h35536[52:1] : sfd__h35536[51:0] ; - assign _theResult___sfd__h36892 = - sfd__h36279[53] ? - ((x__h36264[10:0] == 11'd2046) ? 52'd0 : sfd__h36279[52:1]) : - sfd__h36279[51:0] ; - assign _theResult___sfd__h45777 = - sfd__h45177[53] ? sfd__h45177[52:1] : sfd__h45177[51:0] ; - assign _theResult___sfd__h46532 = - sfd__h45919[53] ? - ((x__h45904[10:0] == 11'd2046) ? 52'd0 : sfd__h45919[52:1]) : - sfd__h45919[51:0] ; - assign _theResult___sfd__h69704 = - sfd__h69269[24] ? - ((_theResult___fst_exp__h69177 == 8'd254) ? - 23'd0 : - sfd__h69269[23:1]) : - sfd__h69269[22:0] ; - assign _theResult___sfd__h78316 = - sfd__h77881[24] ? - ((_theResult___fst_exp__h77863 == 8'd254) ? - 23'd0 : - sfd__h77881[23:1]) : - sfd__h77881[22:0] ; - assign _theResult___sfd__h7936 = - sfd__h7536[24] ? sfd__h7536[23:1] : sfd__h7536[22:0] ; - assign _theResult___sfd__h8489 = - sfd__h8079[24] ? - ((x__h8064[7:0] == 8'd254) ? 23'd0 : sfd__h8079[23:1]) : - sfd__h8079[22:0] ; - assign _theResult___sfd__h87557 = - sfd__h87122[24] ? - ((_theResult___fst_exp__h87030 == 8'd254) ? - 23'd0 : - sfd__h87122[23:1]) : - sfd__h87122[22:0] ; - assign _theResult___sfd__h96223 = - sfd__h95764[24] ? - ((_theResult___fst_exp__h95745 == 8'd254) ? - 23'd0 : - sfd__h95764[23:1]) : - sfd__h95764[22:0] ; - assign _theResult___snd__h118688 = - (sV1_exp__h1204 == 8'd0) ? - _theResult___snd__h118697 : - _theResult___snd__h118690 ; - assign _theResult___snd__h118690 = { sV1_sfd__h1205, 34'd0 } ; - assign _theResult___snd__h118697 = - (sV1_exp__h1204 == 8'd0 && !sV1_sfd__h1205[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057) ? - b__h15323 : - _theResult___snd__h118703 ; - assign _theResult___snd__h118703 = - { IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q94[54:0], - 2'd0 } ; - assign _theResult___snd__h118726 = - b__h15323 << - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 ; - assign _theResult___snd__h128321 = { _theResult____h120074[55:0], 1'd0 } ; - assign _theResult___snd__h128332 = - (!_theResult____h120074[56] && _theResult____h120074[55]) ? - _theResult___snd__h128334 : - _theResult___snd__h128344 ; - assign _theResult___snd__h128334 = { _theResult____h120074[54:0], 2'd0 } ; - assign _theResult___snd__h128344 = - (!_theResult____h120074[56] && !_theResult____h120074[55] && - !_theResult____h120074[54] && - !_theResult____h120074[53] && - !_theResult____h120074[52] && - !_theResult____h120074[51] && - !_theResult____h120074[50] && - !_theResult____h120074[49] && - !_theResult____h120074[48] && - !_theResult____h120074[47] && - !_theResult____h120074[46] && - !_theResult____h120074[45] && - !_theResult____h120074[44] && - !_theResult____h120074[43] && - !_theResult____h120074[42] && - !_theResult____h120074[41] && - !_theResult____h120074[40] && - !_theResult____h120074[39] && - !_theResult____h120074[38] && - !_theResult____h120074[37] && - !_theResult____h120074[36] && - !_theResult____h120074[35] && - !_theResult____h120074[34] && - !_theResult____h120074[33] && - !_theResult____h120074[32] && - !_theResult____h120074[31] && - !_theResult____h120074[30] && - !_theResult____h120074[29] && - !_theResult____h120074[28] && - !_theResult____h120074[27] && - !_theResult____h120074[26] && - !_theResult____h120074[25] && - !_theResult____h120074[24] && - !_theResult____h120074[23] && - !_theResult____h120074[22] && - !_theResult____h120074[21] && - !_theResult____h120074[20] && - !_theResult____h120074[19] && - !_theResult____h120074[18] && - !_theResult____h120074[17] && - !_theResult____h120074[16] && - !_theResult____h120074[15] && - !_theResult____h120074[14] && - !_theResult____h120074[13] && - !_theResult____h120074[12] && - !_theResult____h120074[11] && - !_theResult____h120074[10] && - !_theResult____h120074[9] && - !_theResult____h120074[8] && - !_theResult____h120074[7] && - !_theResult____h120074[6] && - !_theResult____h120074[5] && - !_theResult____h120074[4] && - !_theResult____h120074[3] && - !_theResult____h120074[2] && - !_theResult____h120074[1] && - !_theResult____h120074[0]) ? - _theResult____h120074 : - _theResult___snd__h128350 ; - assign _theResult___snd__h128350 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97[54:0], - 2'd0 } ; - assign _theResult___snd__h128373 = - _theResult____h120074 << - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d3404 ; - assign _theResult___snd__h137087 = - (sV1_exp__h1204 == 8'd0) ? - _theResult___snd__h137101 : - _theResult___snd__h118690 ; - assign _theResult___snd__h137101 = - (sV1_exp__h1204 == 8'd0 && !sV1_sfd__h1205[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057) ? - b__h15323 : - _theResult___snd__h137107 ; - assign _theResult___snd__h137107 = - { IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q100[54:0], - 2'd0 } ; - assign _theResult___snd__h137125 = - b__h15323 << - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3478 ; - assign _theResult___snd__h69188 = { _theResult____h61070[55:0], 1'd0 } ; - assign _theResult___snd__h69199 = - (!_theResult____h61070[56] && _theResult____h61070[55]) ? - _theResult___snd__h69201 : - _theResult___snd__h69211 ; - assign _theResult___snd__h69201 = { _theResult____h61070[54:0], 2'd0 } ; - assign _theResult___snd__h69211 = - (!_theResult____h61070[56] && !_theResult____h61070[55] && - !_theResult____h61070[54] && - !_theResult____h61070[53] && - !_theResult____h61070[52] && - !_theResult____h61070[51] && - !_theResult____h61070[50] && - !_theResult____h61070[49] && - !_theResult____h61070[48] && - !_theResult____h61070[47] && - !_theResult____h61070[46] && - !_theResult____h61070[45] && - !_theResult____h61070[44] && - !_theResult____h61070[43] && - !_theResult____h61070[42] && - !_theResult____h61070[41] && - !_theResult____h61070[40] && - !_theResult____h61070[39] && - !_theResult____h61070[38] && - !_theResult____h61070[37] && - !_theResult____h61070[36] && - !_theResult____h61070[35] && - !_theResult____h61070[34] && - !_theResult____h61070[33] && - !_theResult____h61070[32] && - !_theResult____h61070[31] && - !_theResult____h61070[30] && - !_theResult____h61070[29] && - !_theResult____h61070[28] && - !_theResult____h61070[27] && - !_theResult____h61070[26] && - !_theResult____h61070[25] && - !_theResult____h61070[24] && - !_theResult____h61070[23] && - !_theResult____h61070[22] && - !_theResult____h61070[21] && - !_theResult____h61070[20] && - !_theResult____h61070[19] && - !_theResult____h61070[18] && - !_theResult____h61070[17] && - !_theResult____h61070[16] && - !_theResult____h61070[15] && - !_theResult____h61070[14] && - !_theResult____h61070[13] && - !_theResult____h61070[12] && - !_theResult____h61070[11] && - !_theResult____h61070[10] && - !_theResult____h61070[9] && - !_theResult____h61070[8] && - !_theResult____h61070[7] && - !_theResult____h61070[6] && - !_theResult____h61070[5] && - !_theResult____h61070[4] && - !_theResult____h61070[3] && - !_theResult____h61070[2] && - !_theResult____h61070[1] && - !_theResult____h61070[0]) ? - _theResult____h61070 : - _theResult___snd__h69217 ; - assign _theResult___snd__h69217 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q60[54:0], - 2'd0 } ; - assign _theResult___snd__h69240 = - _theResult____h61070 << - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d2085 ; - assign _theResult___snd__h77814 = - (requestR[190:180] == 11'd0) ? - _theResult___snd__h77823 : - _theResult___snd__h77816 ; - assign _theResult___snd__h77816 = { requestR[179:128], 5'd0 } ; - assign _theResult___snd__h77823 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192) ? - sfd__h53440 : - _theResult___snd__h77829 ; - assign _theResult___snd__h77829 = - { IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q62[54:0], - 2'd0 } ; - assign _theResult___snd__h77852 = - sfd__h53440 << - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 ; - assign _theResult___snd__h87041 = { _theResult____h78794[55:0], 1'd0 } ; - assign _theResult___snd__h87052 = - (!_theResult____h78794[56] && _theResult____h78794[55]) ? - _theResult___snd__h87054 : - _theResult___snd__h87064 ; - assign _theResult___snd__h87054 = { _theResult____h78794[54:0], 2'd0 } ; - assign _theResult___snd__h87064 = - (!_theResult____h78794[56] && !_theResult____h78794[55] && - !_theResult____h78794[54] && - !_theResult____h78794[53] && - !_theResult____h78794[52] && - !_theResult____h78794[51] && - !_theResult____h78794[50] && - !_theResult____h78794[49] && - !_theResult____h78794[48] && - !_theResult____h78794[47] && - !_theResult____h78794[46] && - !_theResult____h78794[45] && - !_theResult____h78794[44] && - !_theResult____h78794[43] && - !_theResult____h78794[42] && - !_theResult____h78794[41] && - !_theResult____h78794[40] && - !_theResult____h78794[39] && - !_theResult____h78794[38] && - !_theResult____h78794[37] && - !_theResult____h78794[36] && - !_theResult____h78794[35] && - !_theResult____h78794[34] && - !_theResult____h78794[33] && - !_theResult____h78794[32] && - !_theResult____h78794[31] && - !_theResult____h78794[30] && - !_theResult____h78794[29] && - !_theResult____h78794[28] && - !_theResult____h78794[27] && - !_theResult____h78794[26] && - !_theResult____h78794[25] && - !_theResult____h78794[24] && - !_theResult____h78794[23] && - !_theResult____h78794[22] && - !_theResult____h78794[21] && - !_theResult____h78794[20] && - !_theResult____h78794[19] && - !_theResult____h78794[18] && - !_theResult____h78794[17] && - !_theResult____h78794[16] && - !_theResult____h78794[15] && - !_theResult____h78794[14] && - !_theResult____h78794[13] && - !_theResult____h78794[12] && - !_theResult____h78794[11] && - !_theResult____h78794[10] && - !_theResult____h78794[9] && - !_theResult____h78794[8] && - !_theResult____h78794[7] && - !_theResult____h78794[6] && - !_theResult____h78794[5] && - !_theResult____h78794[4] && - !_theResult____h78794[3] && - !_theResult____h78794[2] && - !_theResult____h78794[1] && - !_theResult____h78794[0]) ? - _theResult____h78794 : - _theResult___snd__h87070 ; - assign _theResult___snd__h87070 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q65[54:0], - 2'd0 } ; - assign _theResult___snd__h87093 = - _theResult____h78794 << - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d2569 ; - assign _theResult___snd__h95691 = - (requestR[190:180] == 11'd0) ? - _theResult___snd__h95705 : - _theResult___snd__h77816 ; - assign _theResult___snd__h95705 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192) ? - sfd__h53440 : - _theResult___snd__h95711 ; - assign _theResult___snd__h95711 = - { IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q68[54:0], - 2'd0 } ; - assign _theResult___snd__h95729 = - sfd__h53440 << - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2643 ; - assign _theResult___snd_fst_exp__h119496 = - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 ? - 11'd0 : - _theResult___fst_exp__h119493 ; - assign _theResult___snd_fst_exp__h137925 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - _theResult___fst_exp__h129140 : - _theResult___fst_exp__h137922 ; - assign _theResult___snd_fst_exp__h14708 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638 ? - _theResult___fst_exp__h14150 : - _theResult___fst_exp__h14705 ; - assign _theResult___snd_fst_exp__h14711 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637 ? - 8'd0 : - _theResult___snd_fst_exp__h14708 ; - assign _theResult___snd_fst_exp__h14714 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 ? - _theResult___snd_fst_exp__h14711 : - 8'd255 ; - assign _theResult___snd_fst_exp__h36994 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 ? - _theResult___fst_exp__h36232 : - _theResult___fst_exp__h36991 ; - assign _theResult___snd_fst_exp__h36997 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248 ? - 11'd0 : - _theResult___snd_fst_exp__h36994 ; - assign _theResult___snd_fst_exp__h37000 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 ? - _theResult___snd_fst_exp__h36997 : - 11'd2047 ; - assign _theResult___snd_fst_exp__h46633 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462 ? - _theResult___fst_exp__h45872 : - _theResult___fst_exp__h46630 ; - assign _theResult___snd_fst_exp__h46636 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461 ? - 11'd0 : - _theResult___snd_fst_exp__h46633 ; - assign _theResult___snd_fst_exp__h46639 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 ? - _theResult___snd_fst_exp__h46636 : - 11'd2047 ; - assign _theResult___snd_fst_exp__h78419 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _theResult___fst_exp__h69804 : - _theResult___fst_exp__h78416 ; - assign _theResult___snd_fst_exp__h8591 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 ? - _theResult___fst_exp__h8032 : - _theResult___fst_exp__h8588 ; - assign _theResult___snd_fst_exp__h8594 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 ? - 8'd0 : - _theResult___snd_fst_exp__h8591 ; - assign _theResult___snd_fst_exp__h8597 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 ? - _theResult___snd_fst_exp__h8594 : - 8'd255 ; - assign _theResult___snd_fst_exp__h96326 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - _theResult___fst_exp__h87657 : - _theResult___fst_exp__h96323 ; - assign _theResult___snd_fst_sfd__h119497 = - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 ? - 52'd0 : - _theResult___fst_sfd__h119494 ; - assign _theResult___snd_fst_sfd__h137926 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - _theResult___fst_sfd__h129141 : - _theResult___fst_sfd__h137923 ; - assign _theResult___snd_fst_sfd__h14709 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638 ? - _theResult___fst_sfd__h14151 : - _theResult___fst_sfd__h14706 ; - assign _theResult___snd_fst_sfd__h36995 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 ? - _theResult___fst_sfd__h36233 : - _theResult___fst_sfd__h36992 ; - assign _theResult___snd_fst_sfd__h46634 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462 ? - _theResult___fst_sfd__h45873 : - _theResult___fst_sfd__h46631 ; - assign _theResult___snd_fst_sfd__h53394 = - (value__h49279[51:29] == 23'd0) ? - 23'd2097152 : - value__h49279[51:29] ; - assign _theResult___snd_fst_sfd__h78420 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _theResult___fst_sfd__h69805 : - _theResult___fst_sfd__h78417 ; - assign _theResult___snd_fst_sfd__h8592 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 ? - _theResult___fst_sfd__h8033 : - _theResult___fst_sfd__h8589 ; - assign _theResult___snd_fst_sfd__h96327 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - _theResult___fst_sfd__h87658 : - _theResult___fst_sfd__h96324 ; - assign _theResult___snd_fst_sfd__h99811 = - (value__h97928 == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h97925 ; - assign b__h15323 = { value__h15325, 32'd0 } ; - assign b__h47244 = { value__h47246, 32'd0 } ; - assign din_inc___2_exp__h137957 = _theResult___fst_exp__h118737 + 11'd1 ; - assign din_inc___2_exp__h137987 = _theResult___fst_exp__h128310 + 11'd1 ; - assign din_inc___2_exp__h138011 = _theResult___fst_exp__h137141 + 11'd1 ; - assign din_inc___2_exp__h14744 = x__h14182[7:0] + 8'd1 ; - assign din_inc___2_exp__h37034 = x__h36264[10:0] + 11'd1 ; - assign din_inc___2_exp__h46669 = x__h45904[10:0] + 11'd1 ; - assign din_inc___2_exp__h8631 = x__h8064[7:0] + 8'd1 ; - assign din_inc___2_exp__h96354 = _theResult___fst_exp__h69177 + 8'd1 ; - assign din_inc___2_exp__h96378 = _theResult___fst_exp__h77863 + 8'd1 ; - assign din_inc___2_exp__h96408 = _theResult___fst_exp__h87030 + 8'd1 ; - assign din_inc___2_exp__h96432 = _theResult___fst_exp__h95745 + 8'd1 ; - assign guard__h110776 = - { IF_theResult___snd18688_BIT_4_THEN_2_ELSE_0__q95[1], - { _theResult___snd__h118688[3:0], 52'd0 } != 56'd0 } ; - assign guard__h120084 = - { IF_sfdin28304_BIT_4_THEN_2_ELSE_0__q98[1], - { sfdin__h128304[3:0], 52'd0 } != 56'd0 } ; - assign guard__h120682 = x__h120782 != 57'd0 ; - assign guard__h129151 = - { IF_theResult___snd37087_BIT_4_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h137087[3:0], 52'd0 } != 56'd0 } ; - assign guard__h13641 = - { IF_sfd___33631_BIT_8_THEN_2_ELSE_0__q20[1], - { sfd___3__h13631[7:0], 23'd0 } != 31'd0 } ; - assign guard__h14167 = - { IF_sfd___33631_BIT_7_THEN_2_ELSE_0__q21[1], - { sfd___3__h13631[6:0], 24'd0 } != 31'd0 } ; - assign guard__h15256 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[23], - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[22:0], - 33'd0 } != - 56'd0 } ; - assign guard__h15810 = - { IF_x5999_BIT_24_THEN_2_ELSE_0__q31[1], - { x__h15999[23:0], 32'd0 } != 56'd0 } ; - assign guard__h16818 = - { IF_x7039_BIT_24_THEN_2_ELSE_0__q32[1], - { x__h17039[23:0], 32'd0 } != 56'd0 } ; - assign guard__h35519 = - { IF_sfd___35509_BIT_2_THEN_2_ELSE_0__q33[1], - { sfd___3__h35509[1:0], 52'd0 } != 54'd0 } ; - assign guard__h36249 = - { IF_sfd___35509_BIT_1_THEN_2_ELSE_0__q34[1], - { sfd___3__h35509[0], 53'd0 } != 54'd0 } ; - assign guard__h45160 = - { IF_sfd___35150_BIT_2_THEN_2_ELSE_0__q47[1], - { sfd___3__h45150[1:0], 52'd0 } != 54'd0 } ; - assign guard__h45889 = - { IF_sfd___35150_BIT_1_THEN_2_ELSE_0__q48[1], - { sfd___3__h45150[0], 53'd0 } != 54'd0 } ; - assign guard__h47177 = - { IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[52], - { IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[51:0], - 33'd0 } != - 85'd0 } ; - assign guard__h47731 = - { IF_x7920_BIT_53_THEN_2_ELSE_0__q58[1], - { x__h47920[52:0], 32'd0 } != 85'd0 } ; - assign guard__h48722 = - { IF_x8943_BIT_53_THEN_2_ELSE_0__q59[1], - { x__h48943[52:0], 32'd0 } != 85'd0 } ; - assign guard__h61080 = - { IF_sfdin9171_BIT_33_THEN_2_ELSE_0__q61[1], - { sfdin__h69171[32:0], 23'd0 } != 56'd0 } ; - assign guard__h69815 = - { IF_theResult___snd7814_BIT_33_THEN_2_ELSE_0__q63[1], - { _theResult___snd__h77814[32:0], 23'd0 } != 56'd0 } ; - assign guard__h7519 = - { IF_sfd___3509_BIT_8_THEN_2_ELSE_0__q6[1], - { sfd___3__h7509[7:0], 23'd0 } != 31'd0 } ; - assign guard__h78804 = - { IF_sfdin7024_BIT_33_THEN_2_ELSE_0__q66[1], - { sfdin__h87024[32:0], 23'd0 } != 56'd0 } ; - assign guard__h79402 = x__h79502 != 57'd0 ; - assign guard__h8049 = - { IF_sfd___3509_BIT_7_THEN_2_ELSE_0__q7[1], - { sfd___3__h7509[6:0], 24'd0 } != 31'd0 } ; - assign guard__h87668 = - { IF_theResult___snd5691_BIT_33_THEN_2_ELSE_0__q69[1], - { _theResult___snd__h95691[32:0], 23'd0 } != 56'd0 } ; - assign out1___1__h15750 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[56:24] + - 33'd1 ; - assign out1___1__h47671 = - IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[85:53] + - 33'd1 ; - assign out___1_sfd__h97925 = { value__h97928, 29'd0 } ; - assign out_exp__h119395 = - _theResult___snd__h118688[5] ? - _theResult___exp__h119392 : - _theResult___fst_exp__h118737 ; - assign out_exp__h129042 = - sfdin__h128304[5] ? - _theResult___exp__h129039 : - _theResult___fst_exp__h128310 ; - assign out_exp__h137824 = - _theResult___snd__h137087[5] ? - _theResult___exp__h137821 : - _theResult___fst_exp__h137141 ; - assign out_exp__h14057 = - sfd___3__h13631[9] ? _theResult___exp__h14054 : 8'd0 ; - assign out_exp__h14609 = - sfd___3__h13631[8] ? _theResult___exp__h14606 : x__h14182[7:0] ; - assign out_exp__h36138 = - sfd___3__h35509[3] ? _theResult___exp__h36135 : 11'd0 ; - assign out_exp__h36894 = - sfd___3__h35509[2] ? _theResult___exp__h36891 : x__h36264[10:0] ; - assign out_exp__h45779 = - sfd___3__h45150[3] ? _theResult___exp__h45776 : 11'd0 ; - assign out_exp__h46534 = - sfd___3__h45150[2] ? _theResult___exp__h46531 : x__h45904[10:0] ; - assign out_exp__h69706 = - sfdin__h69171[34] ? - _theResult___exp__h69703 : - _theResult___fst_exp__h69177 ; - assign out_exp__h78318 = - _theResult___snd__h77814[34] ? - _theResult___exp__h78315 : - _theResult___fst_exp__h77863 ; - assign out_exp__h7938 = sfd___3__h7509[9] ? _theResult___exp__h7935 : 8'd0 ; - assign out_exp__h8491 = - sfd___3__h7509[8] ? _theResult___exp__h8488 : x__h8064[7:0] ; - assign out_exp__h87559 = - sfdin__h87024[34] ? - _theResult___exp__h87556 : - _theResult___fst_exp__h87030 ; - assign out_exp__h96225 = - _theResult___snd__h95691[34] ? - _theResult___exp__h96222 : - _theResult___fst_exp__h95745 ; - assign out_sfd__h119396 = - _theResult___snd__h118688[5] ? - _theResult___sfd__h119393 : - _theResult___snd__h118688[56:5] ; - assign out_sfd__h129043 = - sfdin__h128304[5] ? - _theResult___sfd__h129040 : - sfdin__h128304[56:5] ; - assign out_sfd__h137825 = - _theResult___snd__h137087[5] ? - _theResult___sfd__h137822 : - _theResult___snd__h137087[56:5] ; - assign out_sfd__h14058 = - sfd___3__h13631[9] ? - _theResult___sfd__h14055 : - sfd___3__h13631[31:9] ; - assign out_sfd__h14610 = - sfd___3__h13631[8] ? - _theResult___sfd__h14607 : - sfd___3__h13631[30:8] ; - assign out_sfd__h36139 = - sfd___3__h35509[3] ? - _theResult___sfd__h36136 : - sfd___3__h35509[54:3] ; - assign out_sfd__h36895 = - sfd___3__h35509[2] ? - _theResult___sfd__h36892 : - sfd___3__h35509[53:2] ; - assign out_sfd__h45780 = - sfd___3__h45150[3] ? - _theResult___sfd__h45777 : - sfd___3__h45150[54:3] ; - assign out_sfd__h46535 = - sfd___3__h45150[2] ? - _theResult___sfd__h46532 : - sfd___3__h45150[53:2] ; - assign out_sfd__h69707 = - sfdin__h69171[34] ? - _theResult___sfd__h69704 : - sfdin__h69171[56:34] ; - assign out_sfd__h78319 = - _theResult___snd__h77814[34] ? - _theResult___sfd__h78316 : - _theResult___snd__h77814[56:34] ; - assign out_sfd__h7939 = - sfd___3__h7509[9] ? - _theResult___sfd__h7936 : - sfd___3__h7509[31:9] ; - assign out_sfd__h8492 = - sfd___3__h7509[8] ? - _theResult___sfd__h8489 : - sfd___3__h7509[30:8] ; - assign out_sfd__h87560 = - sfdin__h87024[34] ? - _theResult___sfd__h87557 : - sfdin__h87024[56:34] ; - assign out_sfd__h96226 = - _theResult___snd__h95691[34] ? - _theResult___sfd__h96223 : - _theResult___snd__h95691[56:34] ; - assign requestR_3_BITS_126_TO_116_754_EQ_0_768_AND_re_ETC___d3775 = - requestR[126:116] == 11'd0 && requestR[115:64] == 52'd0 && - requestR[127] && - requestR[190:180] == 11'd0 && - requestR[179:128] == 52'd0 && - !requestR[191] ; - assign requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 = - { requestR[127:96] == 32'hFFFFFFFF && requestR[95], - (requestR[127:96] == 32'hFFFFFFFF) ? - requestR[94:64] : - 31'h7FC00000 } ; - assign requestR_3_BITS_179_TO_128_611_ULE_requestR_3__ETC___d3787 = - requestR[179:128] <= requestR[115:64] ; - assign requestR_3_BITS_179_TO_128_611_ULT_requestR_3__ETC___d3792 = - requestR[179:128] < requestR[115:64] ; - assign requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3771 = - requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 && - requestR[191] && - requestR[126:116] == 11'd0 && - requestR[115:64] == 52'd0 && - !requestR[127] ; - assign requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3843 = - requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 && - requestR[126:116] == 11'd0 && - requestR[115:64] == 52'd0 || - (!requestR[191] || requestR[127]) && - (requestR[191] || !requestR[127]) && - (requestR[191] ? - requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3838 : - NOT_requestR_3_BITS_190_TO_180_609_ULT_request_ETC___d3839) ; - assign requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1759 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1722 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1741 && - x__h48943[85:54] == 32'hFFFFFFFF) ; - assign requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1770 = - { requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1759, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1764 } == - 5'd0 || - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1759 ; - assign requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3763 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115] ; - assign requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3808 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179] || - requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0 && - !requestR[115] ; - assign requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3828 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3808 || - requestR[190:180] == 11'd2047 && requestR[179] || - requestR[126:116] == 11'd2047 && requestR[115] ; - assign requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 = - requestR[190:180] == requestR[126:116] ; - assign requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622 = - requestR[190:180] - 11'd1023 ; - assign requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3784 = - requestR[190:180] <= requestR[126:116] ; - assign requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3838 = - requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3784 && - (!requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 || - requestR_3_BITS_179_TO_128_611_ULE_requestR_3__ETC___d3787) && - !requestR_3_BITS_190_TO_180_609_ULT_requestR_3__ETC___d3791 && - (!requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 || - !requestR_3_BITS_179_TO_128_611_ULT_requestR_3__ETC___d3792) ; - assign requestR_3_BITS_190_TO_180_609_ULT_requestR_3__ETC___d3791 = - requestR[190:180] < requestR[126:116] ; - assign requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d1042 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159] && - (requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) || - (requestR[191:160] == 32'hFFFFFFFF && requestR[159] || - requestR[127:96] != 32'hFFFFFFFF || - !requestR[95]) && - IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1040 ; - assign requestR_3_BIT_158_07_OR_requestR_3_BIT_157_09_ETC___d789 = - requestR[158] || requestR[157] || requestR[156] || - requestR[155] || - requestR[154] || - requestR[153] || - requestR[152] || - requestR[151] || - requestR[150] || - requestR[149] || - requestR[148] || - requestR[147] || - requestR[146] || - requestR[145] || - requestR[144] || - requestR[143] || - requestR[142] || - requestR[141] || - requestR[140] || - requestR[139] || - requestR[138] || - requestR[137] || - requestR[136] || - requestR[135] || - requestR[134] || - requestR[133] || - requestR[132] || - requestR[131] || - requestR[130] || - requestR[129] || - requestR[128] ; - assign requestR_3_BIT_159_6_OR_requestR_3_BIT_158_07__ETC___d811 = - (requestR[159] || - requestR_3_BIT_158_07_OR_requestR_3_BIT_157_09_ETC___d789) && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637 && - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d808 ; - assign requestR_BITS_159_TO_128__q1 = requestR[159:128] ; - assign res___1__h154853 = - (requestR[190:180] == 11'd2047 && requestR[179]) ? - 64'd512 : - 64'd256 ; - assign res___1__h155291 = requestR[191] ? 64'd1 : 64'd128 ; - assign res___1__h155301 = requestR[191] ? 64'd8 : 64'd16 ; - assign res___1__h155320 = requestR[191] ? 64'd4 : 64'd32 ; - assign res___1__h25997 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22]) ? - 64'd512 : - 64'd256 ; - assign res___1__h26233 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd1 : - 64'd128 ; - assign res___1__h26243 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd8 : - 64'd16 ; - assign res___1__h26262 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd4 : - 64'd32 ; - assign res__h138561 = - { IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3660, - x__h97869, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3624 } ; - assign res__h142948 = - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3799 ? - requestR[191:128] : - requestR[127:64] ; - assign res__h147441 = - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3799 ? - requestR[127:64] : - requestR[191:128] ; - assign res__h150090 = - ((requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3843) ? - 64'd1 : - 64'd0 ; - assign res__h152730 = - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3799 ? - 64'd1 : - 64'd0 ; - assign res__h154552 = - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3860 ? - 64'd1 : - 64'd0 ; - assign res__h155336 = requestR[191] ? 64'd2 : 64'd64 ; - assign res__h155490 = { 32'hFFFFFFFF, fpu$server_core_response_get[36:5] } ; - assign res__h17988 = - { 32'hFFFFFFFF, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 } ; - assign res__h18225 = - { 32'hFFFFFFFF, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign res__h23375 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1103 ? - 64'd1 : - 64'd0 ; - assign res__h24803 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1044 ? - 64'd1 : - 64'd0 ; - assign res__h25817 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1119 ? - 64'd1 : - 64'd0 ; - assign res__h26278 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd2 : - 64'd64 ; - assign res__h96811 = { 32'hFFFFFFFF, x__h96817 } ; - assign result__h120687 = - { _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d3162[56:1], - _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d3162[0] | - guard__h120682 } ; - assign result__h79407 = - { _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_609__ETC___d2329[56:1], - _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_609__ETC___d2329[0] | - guard__h79402 } ; - assign sV1_exp__h1204 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[158:151] : - 8'd255 ; - assign sV1_sfd__h1205 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[150:128] : - 23'd4194304 ; - assign sV2_exp__h1307 = - (requestR[127:96] == 32'hFFFFFFFF) ? requestR[94:87] : 8'd255 ; - assign sV2_sfd__h1308 = - (requestR[127:96] == 32'hFFFFFFFF) ? - requestR[86:64] : - 23'd4194304 ; - assign sfd___3__h13631 = - requestR[159:128] << - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d632 ; - assign sfd___3__h35509 = - sfd__h27508 << - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1242 ; - assign sfd___3__h45150 = - sfd__h37398 << - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1456 ; - assign sfd___3__h7509 = - sfd__h2605 << - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d275 ; - assign sfd__h118755 = - { 1'b0, - _theResult___fst_exp__h118737 != 11'd0, - _theResult___snd__h118688[56:5] } + - 54'd1 ; - assign sfd__h128402 = - { 1'b0, - _theResult___fst_exp__h128310 != 11'd0, - sfdin__h128304[56:5] } + - 54'd1 ; - assign sfd__h13658 = { 2'd0, sfd___3__h13631[31:9] } + 25'd1 ; - assign sfd__h137160 = - { 1'b0, - _theResult___fst_exp__h137141 != 11'd0, - _theResult___snd__h137087[56:5] } + - 54'd1 ; - assign sfd__h14197 = - { 1'b0, x__h14182[7:0] != 8'd0, sfd___3__h13631[30:8] } + 25'd1 ; - assign sfd__h2605 = requestR[159] ? -requestR[159:128] : requestR[159:128] ; - assign sfd__h27508 = { sfd__h2605, 23'd0 } ; - assign sfd__h35536 = { 2'd0, sfd___3__h35509[54:3] } + 54'd1 ; - assign sfd__h36279 = - { 1'b0, x__h36264[10:0] != 11'd0, sfd___3__h35509[53:2] } + - 54'd1 ; - assign sfd__h37398 = { requestR[159:128], 23'd0 } ; - assign sfd__h45177 = { 2'd0, sfd___3__h45150[54:3] } + 54'd1 ; - assign sfd__h45919 = - { 1'b0, x__h45904[10:0] != 11'd0, sfd___3__h45150[53:2] } + - 54'd1 ; - assign sfd__h53440 = { value__h47246, 3'd0 } ; - assign sfd__h69269 = - { 1'b0, - _theResult___fst_exp__h69177 != 8'd0, - sfdin__h69171[56:34] } + - 25'd1 ; - assign sfd__h7536 = { 2'd0, sfd___3__h7509[31:9] } + 25'd1 ; - assign sfd__h77881 = - { 1'b0, - _theResult___fst_exp__h77863 != 8'd0, - _theResult___snd__h77814[56:34] } + - 25'd1 ; - assign sfd__h8079 = - { 1'b0, x__h8064[7:0] != 8'd0, sfd___3__h7509[30:8] } + 25'd1 ; - assign sfd__h87122 = - { 1'b0, - _theResult___fst_exp__h87030 != 8'd0, - sfdin__h87024[56:34] } + - 25'd1 ; - assign sfd__h95764 = - { 1'b0, - _theResult___fst_exp__h95745 != 8'd0, - _theResult___snd__h95691[56:34] } + - 25'd1 ; - assign sfdin__h128304 = - _theResult____h120074[56] ? - _theResult___snd__h128321 : - _theResult___snd__h128332 ; - assign sfdin__h69171 = - _theResult____h61070[56] ? - _theResult___snd__h69188 : - _theResult___snd__h69199 ; - assign sfdin__h87024 = - _theResult____h78794[56] ? - _theResult___snd__h87041 : - _theResult___snd__h87052 ; - assign value__h15325 = { 1'b0, sV1_exp__h1204 != 8'd0, sV1_sfd__h1205 } ; - assign value__h47246 = - { 1'b0, requestR[190:180] != 11'd0, requestR[179:128] } ; - assign value__h49279 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179]) ? - _theResult___fst_sfd__h49736 : - requestR[179:128] ; - assign value__h97928 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22]) ? - _theResult___fst_sfd__h98183 : - sV1_sfd__h1205 ; - assign x__h120782 = b__h15323 << x__h120815 ; - assign x__h120815 = - 12'd57 - - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d3158 ; - assign x__h138663 = - { IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3698, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3705, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3719, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3731, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3743 } ; - assign x__h139530 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3763 ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115]) ? - requestR[191:128] : - ((requestR[190:180] == 11'd2047 && requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115]) ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && requestR[179]) ? - requestR[127:64] : - IF_requestR_3_BITS_126_TO_116_754_EQ_2047_755__ETC___d3802)))) ; - assign x__h14182 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635 + - 9'd127 ; - assign x__h143080 = - { requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3808, - 4'd0 } ; - assign x__h144023 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3763 ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115]) ? - requestR[191:128] : - ((requestR[190:180] == 11'd2047 && requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115]) ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && requestR[115]) ? - requestR[191:128] : - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3815))))) ; - assign x__h148412 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3828 ? - 64'd0 : - res__h150090 ; - assign x__h14848 = - { 2'd0, - NOT_requestR_3_BITS_159_TO_128_44_EQ_0_45_46_A_ETC___d800, - requestR[159:128] != 32'd0 && - (requestR[159] || - requestR_3_BIT_158_07_OR_requestR_3_BIT_157_09_ETC___d789) && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637, - requestR[159:128] != 32'd0 && - requestR_3_BIT_159_6_OR_requestR_3_BIT_158_07__ETC___d811 } ; - assign x__h15077 = { {32{x__h15080[31]}}, x__h15080 } ; - assign x__h15080 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d832 ? - 32'h7FFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d904 ; - assign x__h151052 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3828 ? - 64'd0 : - res__h152730 ; - assign x__h152749 = - { requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0, - 4'd0 } ; - assign x__h152874 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3828 ? - 64'd0 : - res__h154552 ; - assign x__h154833 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - res___1__h154853 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - res___1__h155291 : - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3881) ; - assign x__h155457 = - fpu$server_core_response_get[69] ? - res__h155490 : - fpu$server_core_response_get[68:5] ; - assign x__h15999 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845 >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871 | - ~(57'h1FFFFFFFFFFFFFF >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871) & - {57{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[56]}} ; - assign x__h16413 = - { sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 || - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 == 23'd0 || - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d915, - 3'd0, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d926 } ; - assign x__h16615 = { {32{x__h16618[31]}}, x__h16618 } ; - assign x__h16618 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d832 ? - 32'hFFFFFFFF : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d965 ; - assign x__h17039 = - { sV1_exp__h1204 != 8'd0, sV1_sfd__h1205, 33'd0 } >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934 ; - assign x__h17117 = - { (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d984 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d973, - 3'd0, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d978 } ; - assign x__h17309 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1006 ? - 64'hFFFFFFFF7FC00000 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1052 ; - assign x__h19349 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1054, - 4'd0 } ; - assign x__h19888 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1006 ? - 64'hFFFFFFFF7FC00000 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1067 ; - assign x__h22358 = { 32'hFFFFFFFF, requestR[159:128] } ; - assign x__h22423 = - { {32{requestR_BITS_159_TO_128__q1[31]}}, - requestR_BITS_159_TO_128__q1 } ; - assign x__h22505 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1087 ? - 64'd0 : - res__h23375 ; - assign x__h2333 = { 32'hFFFFFFFF, x__h2340 } ; - assign x__h2340 = - { requestR[127:96] == 32'hFFFFFFFF && requestR[95], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h23933 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1087 ? - 64'd0 : - res__h24803 ; - assign x__h2414 = { 32'hFFFFFFFF, x__h2421 } ; - assign x__h2421 = - { requestR[127:96] != 32'hFFFFFFFF || !requestR[95], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h24822 = - { sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 || - sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308 != 23'd0, - 4'd0 } ; - assign x__h2492 = { 32'hFFFFFFFF, x__h2499 } ; - assign x__h24947 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1087 ? - 64'd0 : - res__h25817 ; - assign x__h2499 = - { (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) != - (requestR[127:96] == 32'hFFFFFFFF && requestR[95]), - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h2584 = { 32'hFFFFFFFF, x__h2590 } ; - assign x__h2590 = - { requestR[159:128] != 32'd0 && - (NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d283 ? - requestR[159] : - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d345), - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d405, - (requestR[159:128] == 32'd0 || - NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d283) ? - 23'd0 : - _theResult___snd_fst_sfd__h8592 } ; - assign x__h25977 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0) ? - res___1__h25997 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1132 ; - assign x__h27284 = { requestR[127], requestR[190:128] } ; - assign x__h27350 = { !requestR[127], requestR[190:128] } ; - assign x__h27418 = { requestR[191] != requestR[127], requestR[190:128] } ; - assign x__h27493 = - { requestR[159:128] != 32'd0 && - IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d1302, - (requestR[159:128] == 32'd0) ? - 11'd0 : - _theResult___snd_fst_exp__h37000, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1399 } ; - assign x__h36264 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245 + - 12'd1023 ; - assign x__h37156 = - { 2'd0, - requestR[159:128] != 32'd0 && - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 && - _theResult___fst_exp__h36991 == 11'd2047 && - _theResult___fst_sfd__h36992 == 52'd0), - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248, - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248 && - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1416 } ; - assign x__h37386 = - { 1'd0, - (requestR[159:128] == 32'd0) ? - 11'd0 : - _theResult___snd_fst_exp__h46639, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1581 } ; - assign x__h45904 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459 + - 12'd1023 ; - assign x__h46769 = - { 2'd0, - requestR[159:128] != 32'd0 && - (!_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462 && - _theResult___fst_exp__h46630 == 11'd2047 && - _theResult___fst_sfd__h46631 == 52'd0), - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461, - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461 && - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1598 } ; - assign x__h46998 = { {32{x__h47001[31]}}, x__h47001 } ; - assign x__h47001 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'h7FFFFFFF : - IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d1690 ; - assign x__h47920 = - IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631 >> - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657 | - ~(86'h3FFFFFFFFFFFFFFFFFFFFF >> - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657) & - {86{IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[85]}} ; - assign x__h48317 = - { requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1701, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1712 } ; - assign x__h48519 = { {32{x__h48522[31]}}, x__h48522 } ; - assign x__h48522 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'hFFFFFFFF : - (requestR[191] ? - 32'd0 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'hFFFFFFFF : - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d1749)) ; - assign x__h48943 = - { requestR[190:180] != 11'd0, requestR[179:128], 33'd0 } >> - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720 ; - assign x__h49021 = - { requestR[191] ? - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1770 : - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1759, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1764 } ; - assign x__h49209 = - (x__h49219 == 8'd255 && - IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d2809[22]) ? - 64'hFFFFFFFF7FC00000 : - res__h96811 ; - assign x__h49219 = - (requestR[190:180] == 11'd2047) ? - 8'd255 : - _theResult___fst_exp__h96335 ; - assign x__h79502 = sfd__h53440 << x__h79535 ; - assign x__h79535 = - 12'd57 - - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_609_ETC___d2325 ; - assign x__h8064 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278 + - 9'd127 ; - assign x__h8757 = - { 2'd0, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d486, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d489, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d498 } ; - assign x__h8990 = - { 33'h1FFFFFFFE, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d722, - (requestR[159:128] == 32'd0 || - !requestR[159] && - NOT_requestR_3_BIT_158_07_08_AND_NOT_requestR__ETC___d598 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 || - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637) ? - 23'd0 : - _theResult___snd_fst_sfd__h14709 } ; - assign x__h96817 = - { (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - (requestR[190:180] == 11'd2047 || - requestR[190:180] == 11'd0) && - requestR[179:128] == 52'd0) ? - requestR[191] : - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2851, - x__h49219, - IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d2809 } ; - assign x__h96932 = - { (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179] : - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2902, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2913, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2929, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2942, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2955 } ; - assign x__h97859 = - (x__h97869 == 11'd2047 && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3624[51]) ? - 64'h7FF8000000000000 : - res__h138561 ; - assign x__h97869 = - (sV1_exp__h1204 == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h137934 ; - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd254; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = - requestR[191] ? 8'd255 : 8'd254; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = - requestR[191] ? 8'd254 : 8'd255; - default: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - 23'd8388607; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - requestR[191] ? 23'd0 : 23'd8388607; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - requestR[191] ? 23'd8388607 : 23'd0; - default: CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = 23'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd2046; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 11'd2047 : - 11'd2046; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 11'd2046 : - 11'd2047; - default: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - 52'hFFFFFFFFFFFFF; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 52'hFFFFFFFFFFFFF : - 52'd0; - default: CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = 52'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h0: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = - requestR[194:192]; - 3'h1: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd4; - 3'h2: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd3; - 3'h3: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd2; - 3'h4: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd1; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = - 3'd0; - endcase - end - always@(guard__h7519 or requestR) - begin - case (guard__h7519) - 2'b0, 2'b01, 2'b10: - CASE_guard519_0b0_requestR_BIT_159_0b1_request_ETC__q8 = - requestR[159]; - 2'd3: - CASE_guard519_0b0_requestR_BIT_159_0b1_request_ETC__q8 = - guard__h7519 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h7519) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 = - (guard__h7519 == 2'b0) ? - requestR[159] : - (guard__h7519 == 2'b01 || guard__h7519 == 2'b10 || - guard__h7519 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h8049 or requestR) - begin - case (guard__h8049) - 2'b0, 2'b01, 2'b10: - CASE_guard049_0b0_requestR_BIT_159_0b1_request_ETC__q10 = - requestR[159]; - 2'd3: - CASE_guard049_0b0_requestR_BIT_159_0b1_request_ETC__q10 = - guard__h8049 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h8049) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - (guard__h8049 == 2'b0) ? - requestR[159] : - (guard__h8049 == 2'b01 || guard__h8049 == 2'b10 || - guard__h8049 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h7519 or _theResult___exp__h7935) - begin - case (guard__h7519) - 2'b0: CASE_guard519_0b0_0_0b1_theResult___exp935_0b1_ETC__q12 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard519_0b0_0_0b1_theResult___exp935_0b1_ETC__q12 = - _theResult___exp__h7935; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d367 or - guard__h7519 or - _theResult___exp__h7935 or - CASE_guard519_0b0_0_0b1_theResult___exp935_0b1_ETC__q12) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d367; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370 = - (guard__h7519 == 2'b0 || requestR[159]) ? - 8'd0 : - _theResult___exp__h7935; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370 = - CASE_guard519_0b0_0_0b1_theResult___exp935_0b1_ETC__q12; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370 = - 8'd0; - endcase - end - always@(guard__h7519 or out_exp__h7938 or _theResult___exp__h7935) - begin - case (guard__h7519) - 2'b0, 2'b01: - CASE_guard519_0b0_0_0b1_0_0b10_out_exp938_0b11_ETC__q13 = 8'd0; - 2'b10: - CASE_guard519_0b0_0_0b1_0_0b10_out_exp938_0b11_ETC__q13 = - out_exp__h7938; - 2'b11: - CASE_guard519_0b0_0_0b1_0_0b10_out_exp938_0b11_ETC__q13 = - _theResult___exp__h7935; - endcase - end - always@(guard__h8049 or x__h8064 or _theResult___exp__h8488) - begin - case (guard__h8049) - 2'b0: - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_theResu_ETC__q14 = - x__h8064[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_theResu_ETC__q14 = - _theResult___exp__h8488; - endcase - end - always@(requestR or - x__h8064 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d395 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d393 or - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_theResu_ETC__q14) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 = - x__h8064[7:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d395; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d393; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 = - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_theResu_ETC__q14; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 = - 8'd0; - endcase - end - always@(guard__h8049 or - x__h8064 or out_exp__h8491 or _theResult___exp__h8488) - begin - case (guard__h8049) - 2'b0, 2'b01: - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_x064_BI_ETC__q15 = - x__h8064[7:0]; - 2'b10: - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_x064_BI_ETC__q15 = - out_exp__h8491; - 2'b11: - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_x064_BI_ETC__q15 = - _theResult___exp__h8488; - endcase - end - always@(guard__h7519 or sfd___3__h7509 or _theResult___sfd__h7936) - begin - case (guard__h7519) - 2'b0: - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q16 = - sfd___3__h7509[31:9]; - 2'b01, 2'b10, 2'b11: - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q16 = - _theResult___sfd__h7936; - endcase - end - always@(requestR or - sfd___3__h7509 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d418 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d416 or - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q16) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 = - sfd___3__h7509[31:9]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d418; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d416; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 = - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q16; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 = - 23'd0; - endcase - end - always@(guard__h7519 or - sfd___3__h7509 or out_sfd__h7939 or _theResult___sfd__h7936) - begin - case (guard__h7519) - 2'b0, 2'b01: - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q17 = - sfd___3__h7509[31:9]; - 2'b10: - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q17 = - out_sfd__h7939; - 2'b11: - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q17 = - _theResult___sfd__h7936; - endcase - end - always@(guard__h8049 or sfd___3__h7509 or _theResult___sfd__h8489) - begin - case (guard__h8049) - 2'b0: - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q18 = - sfd___3__h7509[30:8]; - 2'b01, 2'b10, 2'b11: - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q18 = - _theResult___sfd__h8489; - endcase - end - always@(requestR or - sfd___3__h7509 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d436 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d434 or - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q18) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 = - sfd___3__h7509[30:8]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d436; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d434; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 = - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q18; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 = - 23'd0; - endcase - end - always@(guard__h8049 or - sfd___3__h7509 or out_sfd__h8492 or _theResult___sfd__h8489) - begin - case (guard__h8049) - 2'b0, 2'b01: - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q19 = - sfd___3__h7509[30:8]; - 2'b10: - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q19 = - out_sfd__h8492; - 2'b11: - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q19 = - _theResult___sfd__h8489; - endcase - end - always@(guard__h13641 or out_exp__h14057 or _theResult___exp__h14054) - begin - case (guard__h13641) - 2'b0, 2'b01: - CASE_guard3641_0b0_0_0b1_0_0b10_out_exp4057_0b_ETC__q22 = 8'd0; - 2'b10: - CASE_guard3641_0b0_0_0b1_0_0b10_out_exp4057_0b_ETC__q22 = - out_exp__h14057; - 2'b11: - CASE_guard3641_0b0_0_0b1_0_0b10_out_exp4057_0b_ETC__q22 = - _theResult___exp__h14054; - endcase - end - always@(guard__h13641 or _theResult___exp__h14054) - begin - case (guard__h13641) - 2'b0: CASE_guard3641_0b0_0_0b1_theResult___exp4054_0_ETC__q23 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard3641_0b0_0_0b1_theResult___exp4054_0_ETC__q23 = - _theResult___exp__h14054; - endcase - end - always@(requestR or - guard__h13641 or - _theResult___exp__h14054 or - CASE_guard3641_0b0_0_0b1_theResult___exp4054_0_ETC__q23) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard3641_ETC__q24 = - (guard__h13641 == 2'b0) ? 8'd0 : _theResult___exp__h14054; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard3641_ETC__q24 = - CASE_guard3641_0b0_0_0b1_theResult___exp4054_0_ETC__q23; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard3641_ETC__q24 = 8'd0; - endcase - end - always@(guard__h14167 or x__h14182 or _theResult___exp__h14606) - begin - case (guard__h14167) - 2'b0: - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_theRe_ETC__q25 = - x__h14182[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_theRe_ETC__q25 = - _theResult___exp__h14606; - endcase - end - always@(requestR or - x__h14182 or - guard__h14167 or - _theResult___exp__h14606 or - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_theRe_ETC__q25) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716 = - x__h14182[7:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716 = - (guard__h14167 == 2'b0) ? - x__h14182[7:0] : - _theResult___exp__h14606; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716 = - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_theRe_ETC__q25; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716 = - 8'd0; - endcase - end - always@(guard__h14167 or - x__h14182 or out_exp__h14609 or _theResult___exp__h14606) - begin - case (guard__h14167) - 2'b0, 2'b01: - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_x4182_ETC__q26 = - x__h14182[7:0]; - 2'b10: - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_x4182_ETC__q26 = - out_exp__h14609; - 2'b11: - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_x4182_ETC__q26 = - _theResult___exp__h14606; - endcase - end - always@(guard__h14167 or sfd___3__h13631 or _theResult___sfd__h14607) - begin - case (guard__h14167) - 2'b0: - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q27 = - sfd___3__h13631[30:8]; - 2'b01, 2'b10, 2'b11: - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q27 = - _theResult___sfd__h14607; - endcase - end - always@(requestR or - sfd___3__h13631 or - guard__h14167 or - _theResult___sfd__h14607 or - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q27) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754 = - sfd___3__h13631[30:8]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754 = - (guard__h14167 == 2'b0) ? - sfd___3__h13631[30:8] : - _theResult___sfd__h14607; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754 = - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q27; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754 = - 23'd0; - endcase - end - always@(guard__h14167 or - sfd___3__h13631 or out_sfd__h14610 or _theResult___sfd__h14607) - begin - case (guard__h14167) - 2'b0, 2'b01: - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q28 = - sfd___3__h13631[30:8]; - 2'b10: - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q28 = - out_sfd__h14610; - 2'b11: - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q28 = - _theResult___sfd__h14607; - endcase - end - always@(guard__h13641 or sfd___3__h13631 or _theResult___sfd__h14055) - begin - case (guard__h13641) - 2'b0: - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q29 = - sfd___3__h13631[31:9]; - 2'b01, 2'b10, 2'b11: - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q29 = - _theResult___sfd__h14055; - endcase - end - always@(requestR or - sfd___3__h13631 or - guard__h13641 or - _theResult___sfd__h14055 or - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q29) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739 = - sfd___3__h13631[31:9]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739 = - (guard__h13641 == 2'b0) ? - sfd___3__h13631[31:9] : - _theResult___sfd__h14055; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739 = - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q29; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739 = - 23'd0; - endcase - end - always@(guard__h13641 or - sfd___3__h13631 or out_sfd__h14058 or _theResult___sfd__h14055) - begin - case (guard__h13641) - 2'b0, 2'b01: - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q30 = - sfd___3__h13631[31:9]; - 2'b10: - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q30 = - out_sfd__h14058; - 2'b11: - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q30 = - _theResult___sfd__h14055; - endcase - end - always@(guard__h35519 or requestR) - begin - case (guard__h35519) - 2'b0, 2'b01, 2'b10: - CASE_guard5519_0b0_requestR_BIT_159_0b1_reques_ETC__q35 = - requestR[159]; - 2'd3: - CASE_guard5519_0b0_requestR_BIT_159_0b1_reques_ETC__q35 = - guard__h35519 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h35519) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 = - (guard__h35519 == 2'b0) ? - requestR[159] : - (guard__h35519 == 2'b01 || guard__h35519 == 2'b10 || - guard__h35519 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h36249 or requestR) - begin - case (guard__h36249) - 2'b0, 2'b01, 2'b10: - CASE_guard6249_0b0_requestR_BIT_159_0b1_reques_ETC__q37 = - requestR[159]; - 2'd3: - CASE_guard6249_0b0_requestR_BIT_159_0b1_reques_ETC__q37 = - guard__h36249 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h36249) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 = - (guard__h36249 == 2'b0) ? - requestR[159] : - (guard__h36249 == 2'b01 || guard__h36249 == 2'b10 || - guard__h36249 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h36249 or x__h36264 or _theResult___exp__h36891) - begin - case (guard__h36249) - 2'b0: - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_theR_ETC__q39 = - x__h36264[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_theR_ETC__q39 = - _theResult___exp__h36891; - endcase - end - always@(requestR or - x__h36264 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1350 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1348 or - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_theR_ETC__q39) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 = - x__h36264[10:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1350; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1348; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 = - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_theR_ETC__q39; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 = - 11'd0; - endcase - end - always@(guard__h36249 or - x__h36264 or out_exp__h36894 or _theResult___exp__h36891) - begin - case (guard__h36249) - 2'b0, 2'b01: - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_x626_ETC__q40 = - x__h36264[10:0]; - 2'b10: - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_x626_ETC__q40 = - out_exp__h36894; - 2'b11: - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_x626_ETC__q40 = - _theResult___exp__h36891; - endcase - end - always@(guard__h36249 or sfd___3__h35509 or _theResult___sfd__h36892) - begin - case (guard__h36249) - 2'b0: - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q41 = - sfd___3__h35509[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q41 = - _theResult___sfd__h36892; - endcase - end - always@(requestR or - sfd___3__h35509 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1391 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1389 or - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q41) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 = - sfd___3__h35509[53:2]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1391; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1389; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 = - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q41; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 = - 52'd0; - endcase - end - always@(guard__h36249 or - sfd___3__h35509 or out_sfd__h36895 or _theResult___sfd__h36892) - begin - case (guard__h36249) - 2'b0, 2'b01: - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q42 = - sfd___3__h35509[53:2]; - 2'b10: - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q42 = - out_sfd__h36895; - 2'b11: - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q42 = - _theResult___sfd__h36892; - endcase - end - always@(guard__h35519 or _theResult___exp__h36135) - begin - case (guard__h35519) - 2'b0: CASE_guard5519_0b0_0_0b1_theResult___exp6135_0_ETC__q43 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard5519_0b0_0_0b1_theResult___exp6135_0_ETC__q43 = - _theResult___exp__h36135; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1322 or - guard__h35519 or - _theResult___exp__h36135 or - CASE_guard5519_0b0_0_0b1_theResult___exp6135_0_ETC__q43) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1322; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325 = - (guard__h35519 == 2'b0 || requestR[159]) ? - 11'd0 : - _theResult___exp__h36135; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325 = - CASE_guard5519_0b0_0_0b1_theResult___exp6135_0_ETC__q43; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325 = - 11'd0; - endcase - end - always@(guard__h35519 or out_exp__h36138 or _theResult___exp__h36135) - begin - case (guard__h35519) - 2'b0, 2'b01: - CASE_guard5519_0b0_0_0b1_0_0b10_out_exp6138_0b_ETC__q44 = 11'd0; - 2'b10: - CASE_guard5519_0b0_0_0b1_0_0b10_out_exp6138_0b_ETC__q44 = - out_exp__h36138; - 2'b11: - CASE_guard5519_0b0_0_0b1_0_0b10_out_exp6138_0b_ETC__q44 = - _theResult___exp__h36135; - endcase - end - always@(guard__h35519 or sfd___3__h35509 or _theResult___sfd__h36136) - begin - case (guard__h35519) - 2'b0: - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q45 = - sfd___3__h35509[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q45 = - _theResult___sfd__h36136; - endcase - end - always@(requestR or - sfd___3__h35509 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1373 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1371 or - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q45) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 = - sfd___3__h35509[54:3]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1373; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1371; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 = - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q45; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 = - 52'd0; - endcase - end - always@(guard__h35519 or - sfd___3__h35509 or out_sfd__h36139 or _theResult___sfd__h36136) - begin - case (guard__h35519) - 2'b0, 2'b01: - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q46 = - sfd___3__h35509[54:3]; - 2'b10: - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q46 = - out_sfd__h36139; - 2'b11: - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q46 = - _theResult___sfd__h36136; - endcase - end - always@(guard__h45160 or out_exp__h45779 or _theResult___exp__h45776) - begin - case (guard__h45160) - 2'b0, 2'b01: - CASE_guard5160_0b0_0_0b1_0_0b10_out_exp5779_0b_ETC__q49 = 11'd0; - 2'b10: - CASE_guard5160_0b0_0_0b1_0_0b10_out_exp5779_0b_ETC__q49 = - out_exp__h45779; - 2'b11: - CASE_guard5160_0b0_0_0b1_0_0b10_out_exp5779_0b_ETC__q49 = - _theResult___exp__h45776; - endcase - end - always@(guard__h45160 or _theResult___exp__h45776) - begin - case (guard__h45160) - 2'b0: CASE_guard5160_0b0_0_0b1_theResult___exp5776_0_ETC__q50 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard5160_0b0_0_0b1_theResult___exp5776_0_ETC__q50 = - _theResult___exp__h45776; - endcase - end - always@(requestR or - guard__h45160 or - _theResult___exp__h45776 or - CASE_guard5160_0b0_0_0b1_theResult___exp5776_0_ETC__q50) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5160_ETC__q51 = - (guard__h45160 == 2'b0) ? 11'd0 : _theResult___exp__h45776; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5160_ETC__q51 = - CASE_guard5160_0b0_0_0b1_theResult___exp5776_0_ETC__q50; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard5160_ETC__q51 = - 11'd0; - endcase - end - always@(guard__h45889 or x__h45904 or _theResult___exp__h46531) - begin - case (guard__h45889) - 2'b0: - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_theR_ETC__q52 = - x__h45904[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_theR_ETC__q52 = - _theResult___exp__h46531; - endcase - end - always@(requestR or - x__h45904 or - guard__h45889 or - _theResult___exp__h46531 or - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_theR_ETC__q52) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540 = - x__h45904[10:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540 = - (guard__h45889 == 2'b0) ? - x__h45904[10:0] : - _theResult___exp__h46531; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540 = - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_theR_ETC__q52; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540 = - 11'd0; - endcase - end - always@(guard__h45889 or - x__h45904 or out_exp__h46534 or _theResult___exp__h46531) - begin - case (guard__h45889) - 2'b0, 2'b01: - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_x590_ETC__q53 = - x__h45904[10:0]; - 2'b10: - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_x590_ETC__q53 = - out_exp__h46534; - 2'b11: - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_x590_ETC__q53 = - _theResult___exp__h46531; - endcase - end - always@(guard__h45889 or sfd___3__h45150 or _theResult___sfd__h46532) - begin - case (guard__h45889) - 2'b0: - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q54 = - sfd___3__h45150[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q54 = - _theResult___sfd__h46532; - endcase - end - always@(requestR or - sfd___3__h45150 or - guard__h45889 or - _theResult___sfd__h46532 or - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q54) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577 = - sfd___3__h45150[53:2]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577 = - (guard__h45889 == 2'b0) ? - sfd___3__h45150[53:2] : - _theResult___sfd__h46532; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577 = - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q54; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577 = - 52'd0; - endcase - end - always@(guard__h45889 or - sfd___3__h45150 or out_sfd__h46535 or _theResult___sfd__h46532) - begin - case (guard__h45889) - 2'b0, 2'b01: - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q55 = - sfd___3__h45150[53:2]; - 2'b10: - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q55 = - out_sfd__h46535; - 2'b11: - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q55 = - _theResult___sfd__h46532; - endcase - end - always@(guard__h45160 or sfd___3__h45150 or _theResult___sfd__h45777) - begin - case (guard__h45160) - 2'b0: - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q56 = - sfd___3__h45150[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q56 = - _theResult___sfd__h45777; - endcase - end - always@(requestR or - sfd___3__h45150 or - guard__h45160 or - _theResult___sfd__h45777 or - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q56) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562 = - sfd___3__h45150[54:3]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562 = - (guard__h45160 == 2'b0) ? - sfd___3__h45150[54:3] : - _theResult___sfd__h45777; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562 = - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q56; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562 = - 52'd0; - endcase - end - always@(guard__h45160 or - sfd___3__h45150 or out_sfd__h45780 or _theResult___sfd__h45777) - begin - case (guard__h45160) - 2'b0, 2'b01: - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q57 = - sfd___3__h45150[54:3]; - 2'b10: - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q57 = - out_sfd__h45780; - 2'b11: - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q57 = - _theResult___sfd__h45777; - endcase - end - always@(guard__h61080 or - _theResult___fst_exp__h69177 or _theResult___exp__h69703) - begin - case (guard__h61080) - 2'b0: - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q70 = - _theResult___fst_exp__h69177; - 2'b01, 2'b10, 2'b11: - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q70 = - _theResult___exp__h69703; - endcase - end - always@(requestR or - _theResult___fst_exp__h69177 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2146 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2144 or - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q70) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 = - _theResult___fst_exp__h69177; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2146; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2144; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 = - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q70; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 = - 8'd0; - endcase - end - always@(guard__h61080 or - _theResult___fst_exp__h69177 or - out_exp__h69706 or _theResult___exp__h69703) - begin - case (guard__h61080) - 2'b0, 2'b01: - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q71 = - _theResult___fst_exp__h69177; - 2'b10: - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q71 = - out_exp__h69706; - 2'b11: - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q71 = - _theResult___exp__h69703; - endcase - end - always@(guard__h69815 or - _theResult___fst_exp__h77863 or _theResult___exp__h78315) - begin - case (guard__h69815) - 2'b0: - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q72 = - _theResult___fst_exp__h77863; - 2'b01, 2'b10, 2'b11: - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q72 = - _theResult___exp__h78315; - endcase - end - always@(requestR or - _theResult___fst_exp__h77863 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2303 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2301 or - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q72) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 = - _theResult___fst_exp__h77863; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2303; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2301; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 = - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q72; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 = - 8'd0; - endcase - end - always@(guard__h69815 or - _theResult___fst_exp__h77863 or - out_exp__h78318 or _theResult___exp__h78315) - begin - case (guard__h69815) - 2'b0, 2'b01: - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q73 = - _theResult___fst_exp__h77863; - 2'b10: - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q73 = - out_exp__h78318; - 2'b11: - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q73 = - _theResult___exp__h78315; - endcase - end - always@(guard__h78804 or - _theResult___fst_exp__h87030 or _theResult___exp__h87556) - begin - case (guard__h78804) - 2'b0: - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q74 = - _theResult___fst_exp__h87030; - 2'b01, 2'b10, 2'b11: - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q74 = - _theResult___exp__h87556; - endcase - end - always@(requestR or - _theResult___fst_exp__h87030 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2630 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2628 or - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q74) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 = - _theResult___fst_exp__h87030; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2630; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2628; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 = - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q74; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 = - 8'd0; - endcase - end - always@(guard__h78804 or - _theResult___fst_exp__h87030 or - out_exp__h87559 or _theResult___exp__h87556) - begin - case (guard__h78804) - 2'b0, 2'b01: - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q75 = - _theResult___fst_exp__h87030; - 2'b10: - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q75 = - out_exp__h87559; - 2'b11: - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q75 = - _theResult___exp__h87556; - endcase - end - always@(guard__h87668 or - _theResult___fst_exp__h95745 or _theResult___exp__h96222) - begin - case (guard__h87668) - 2'b0: - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q76 = - _theResult___fst_exp__h95745; - 2'b01, 2'b10, 2'b11: - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q76 = - _theResult___exp__h96222; - endcase - end - always@(requestR or - _theResult___fst_exp__h95745 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2699 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2697 or - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q76) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 = - _theResult___fst_exp__h95745; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2699; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2697; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 = - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q76; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 = - 8'd0; - endcase - end - always@(guard__h87668 or - _theResult___fst_exp__h95745 or - out_exp__h96225 or _theResult___exp__h96222) - begin - case (guard__h87668) - 2'b0, 2'b01: - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q77 = - _theResult___fst_exp__h95745; - 2'b10: - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q77 = - out_exp__h96225; - 2'b11: - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q77 = - _theResult___exp__h96222; - endcase - end - always@(guard__h61080 or sfdin__h69171 or _theResult___sfd__h69704) - begin - case (guard__h61080) - 2'b0: - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q78 = - sfdin__h69171[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q78 = - _theResult___sfd__h69704; - endcase - end - always@(requestR or - sfdin__h69171 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2733 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2731 or - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q78) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 = - sfdin__h69171[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2733; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2731; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 = - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q78; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 = - 23'd0; - endcase - end - always@(guard__h61080 or - sfdin__h69171 or out_sfd__h69707 or _theResult___sfd__h69704) - begin - case (guard__h61080) - 2'b0, 2'b01: - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q79 = - sfdin__h69171[56:34]; - 2'b10: - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q79 = - out_sfd__h69707; - 2'b11: - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q79 = - _theResult___sfd__h69704; - endcase - end - always@(guard__h69815 or - _theResult___snd__h77814 or _theResult___sfd__h78316) - begin - case (guard__h69815) - 2'b0: - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q80 = - _theResult___snd__h77814[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q80 = - _theResult___sfd__h78316; - endcase - end - always@(requestR or - _theResult___snd__h77814 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2752 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2750 or - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q80) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 = - _theResult___snd__h77814[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2752; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2750; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 = - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q80; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 = - 23'd0; - endcase - end - always@(guard__h69815 or - _theResult___snd__h77814 or - out_sfd__h78319 or _theResult___sfd__h78316) - begin - case (guard__h69815) - 2'b0, 2'b01: - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q81 = - _theResult___snd__h77814[56:34]; - 2'b10: - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q81 = - out_sfd__h78319; - 2'b11: - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q81 = - _theResult___sfd__h78316; - endcase - end - always@(guard__h78804 or sfdin__h87024 or _theResult___sfd__h87557) - begin - case (guard__h78804) - 2'b0: - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q82 = - sfdin__h87024[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q82 = - _theResult___sfd__h87557; - endcase - end - always@(requestR or - sfdin__h87024 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2779 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2777 or - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q82) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 = - sfdin__h87024[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2779; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2777; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 = - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q82; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 = - 23'd0; - endcase - end - always@(guard__h78804 or - sfdin__h87024 or out_sfd__h87560 or _theResult___sfd__h87557) - begin - case (guard__h78804) - 2'b0, 2'b01: - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q83 = - sfdin__h87024[56:34]; - 2'b10: - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q83 = - out_sfd__h87560; - 2'b11: - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q83 = - _theResult___sfd__h87557; - endcase - end - always@(guard__h87668 or - _theResult___snd__h95691 or _theResult___sfd__h96223) - begin - case (guard__h87668) - 2'b0: - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q84 = - _theResult___snd__h95691[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q84 = - _theResult___sfd__h96223; - endcase - end - always@(requestR or - _theResult___snd__h95691 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2798 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2796 or - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q84) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 = - _theResult___snd__h95691[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2798; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2796; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 = - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q84; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 = - 23'd0; - endcase - end - always@(guard__h87668 or - _theResult___snd__h95691 or - out_sfd__h96226 or _theResult___sfd__h96223) - begin - case (guard__h87668) - 2'b0, 2'b01: - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q85 = - _theResult___snd__h95691[56:34]; - 2'b10: - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q85 = - out_sfd__h96226; - 2'b11: - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q85 = - _theResult___sfd__h96223; - endcase - end - always@(guard__h61080 or requestR) - begin - case (guard__h61080) - 2'b0, 2'b01, 2'b10: - CASE_guard1080_0b0_requestR_BIT_191_0b1_reques_ETC__q86 = - requestR[191]; - 2'd3: - CASE_guard1080_0b0_requestR_BIT_191_0b1_reques_ETC__q86 = - guard__h61080 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h61080) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 = - (guard__h61080 == 2'b0) ? - requestR[191] : - (guard__h61080 == 2'b01 || guard__h61080 == 2'b10 || - guard__h61080 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h69815 or requestR) - begin - case (guard__h69815) - 2'b0, 2'b01, 2'b10: - CASE_guard9815_0b0_requestR_BIT_191_0b1_reques_ETC__q88 = - requestR[191]; - 2'd3: - CASE_guard9815_0b0_requestR_BIT_191_0b1_reques_ETC__q88 = - guard__h69815 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h69815) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 = - (guard__h69815 == 2'b0) ? - requestR[191] : - (guard__h69815 == 2'b01 || guard__h69815 == 2'b10 || - guard__h69815 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h78804 or requestR) - begin - case (guard__h78804) - 2'b0, 2'b01, 2'b10: - CASE_guard8804_0b0_requestR_BIT_191_0b1_reques_ETC__q90 = - requestR[191]; - 2'd3: - CASE_guard8804_0b0_requestR_BIT_191_0b1_reques_ETC__q90 = - guard__h78804 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h78804) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 = - (guard__h78804 == 2'b0) ? - requestR[191] : - (guard__h78804 == 2'b01 || guard__h78804 == 2'b10 || - guard__h78804 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h87668 or requestR) - begin - case (guard__h87668) - 2'b0, 2'b01, 2'b10: - CASE_guard7668_0b0_requestR_BIT_191_0b1_reques_ETC__q92 = - requestR[191]; - 2'd3: - CASE_guard7668_0b0_requestR_BIT_191_0b1_reques_ETC__q92 = - guard__h87668 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h87668) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 = - (guard__h87668 == 2'b0) ? - requestR[191] : - (guard__h87668 == 2'b01 || guard__h87668 == 2'b10 || - guard__h87668 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h110776 or - _theResult___fst_exp__h118737 or _theResult___exp__h119392) - begin - case (guard__h110776) - 2'b0: - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q102 = - _theResult___fst_exp__h118737; - 2'b01, 2'b10, 2'b11: - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q102 = - _theResult___exp__h119392; - endcase - end - always@(requestR or - _theResult___fst_exp__h118737 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3140 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3138 or - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q102) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 = - _theResult___fst_exp__h118737; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3140; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3138; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 = - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q102; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 = - 11'd0; - endcase - end - always@(guard__h110776 or - _theResult___fst_exp__h118737 or - out_exp__h119395 or _theResult___exp__h119392) - begin - case (guard__h110776) - 2'b0, 2'b01: - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q103 = - _theResult___fst_exp__h118737; - 2'b10: - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q103 = - out_exp__h119395; - 2'b11: - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q103 = - _theResult___exp__h119392; - endcase - end - always@(guard__h120084 or - _theResult___fst_exp__h128310 or _theResult___exp__h129039) - begin - case (guard__h120084) - 2'b0: - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q104 = - _theResult___fst_exp__h128310; - 2'b01, 2'b10, 2'b11: - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q104 = - _theResult___exp__h129039; - endcase - end - always@(requestR or - _theResult___fst_exp__h128310 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3465 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3463 or - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q104) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 = - _theResult___fst_exp__h128310; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3465; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3463; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 = - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q104; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 = - 11'd0; - endcase - end - always@(guard__h120084 or - _theResult___fst_exp__h128310 or - out_exp__h129042 or _theResult___exp__h129039) - begin - case (guard__h120084) - 2'b0, 2'b01: - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q105 = - _theResult___fst_exp__h128310; - 2'b10: - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q105 = - out_exp__h129042; - 2'b11: - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q105 = - _theResult___exp__h129039; - endcase - end - always@(guard__h129151 or - _theResult___fst_exp__h137141 or _theResult___exp__h137821) - begin - case (guard__h129151) - 2'b0: - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q106 = - _theResult___fst_exp__h137141; - 2'b01, 2'b10, 2'b11: - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q106 = - _theResult___exp__h137821; - endcase - end - always@(requestR or - _theResult___fst_exp__h137141 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3534 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3532 or - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q106) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 = - _theResult___fst_exp__h137141; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3534; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3532; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 = - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q106; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 = - 11'd0; - endcase - end - always@(guard__h129151 or - _theResult___fst_exp__h137141 or - out_exp__h137824 or _theResult___exp__h137821) - begin - case (guard__h129151) - 2'b0, 2'b01: - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q107 = - _theResult___fst_exp__h137141; - 2'b10: - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q107 = - out_exp__h137824; - 2'b11: - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q107 = - _theResult___exp__h137821; - endcase - end - always@(guard__h110776 or requestR) - begin - case (guard__h110776) - 2'b0, 2'b01, 2'b10: - CASE_guard10776_0b0_requestR_BITS_191_TO_160_E_ETC__q108 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard10776_0b0_requestR_BITS_191_TO_160_E_ETC__q108 = - guard__h110776 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h110776) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 = - (guard__h110776 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h110776 == 2'b01 || guard__h110776 == 2'b10 || - guard__h110776 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h120084 or requestR) - begin - case (guard__h120084) - 2'b0, 2'b01, 2'b10: - CASE_guard20084_0b0_requestR_BITS_191_TO_160_E_ETC__q110 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard20084_0b0_requestR_BITS_191_TO_160_E_ETC__q110 = - guard__h120084 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h120084) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 = - (guard__h120084 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h120084 == 2'b01 || guard__h120084 == 2'b10 || - guard__h120084 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h129151 or requestR) - begin - case (guard__h129151) - 2'b0, 2'b01, 2'b10: - CASE_guard29151_0b0_requestR_BITS_191_TO_160_E_ETC__q112 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard29151_0b0_requestR_BITS_191_TO_160_E_ETC__q112 = - guard__h129151 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h129151) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 = - (guard__h129151 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h129151 == 2'b01 || guard__h129151 == 2'b10 || - guard__h129151 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h110776 or - _theResult___snd__h118688 or _theResult___sfd__h119393) - begin - case (guard__h110776) - 2'b0: - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q114 = - _theResult___snd__h118688[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q114 = - _theResult___sfd__h119393; - endcase - end - always@(requestR or - _theResult___snd__h118688 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3567 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3565 or - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q114) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 = - _theResult___snd__h118688[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3567; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3565; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 = - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q114; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 = - 52'd0; - endcase - end - always@(guard__h110776 or - _theResult___snd__h118688 or - out_sfd__h119396 or _theResult___sfd__h119393) - begin - case (guard__h110776) - 2'b0, 2'b01: - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q115 = - _theResult___snd__h118688[56:5]; - 2'b10: - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q115 = - out_sfd__h119396; - 2'b11: - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q115 = - _theResult___sfd__h119393; - endcase - end - always@(guard__h120084 or sfdin__h128304 or _theResult___sfd__h129040) - begin - case (guard__h120084) - 2'b0: - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q116 = - sfdin__h128304[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q116 = - _theResult___sfd__h129040; - endcase - end - always@(requestR or - sfdin__h128304 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3594 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3592 or - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q116) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 = - sfdin__h128304[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3594; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3592; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 = - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q116; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 = - 52'd0; - endcase - end - always@(guard__h120084 or - sfdin__h128304 or out_sfd__h129043 or _theResult___sfd__h129040) - begin - case (guard__h120084) - 2'b0, 2'b01: - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q117 = - sfdin__h128304[56:5]; - 2'b10: - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q117 = - out_sfd__h129043; - 2'b11: - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q117 = - _theResult___sfd__h129040; - endcase - end - always@(guard__h129151 or - _theResult___snd__h137087 or _theResult___sfd__h137822) - begin - case (guard__h129151) - 2'b0: - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q118 = - _theResult___snd__h137087[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q118 = - _theResult___sfd__h137822; - endcase - end - always@(requestR or - _theResult___snd__h137087 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3613 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3611 or - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q118) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 = - _theResult___snd__h137087[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3613; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3611; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 = - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q118; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 = - 52'd0; - endcase - end - always@(guard__h129151 or - _theResult___snd__h137087 or - out_sfd__h137825 or _theResult___sfd__h137822) - begin - case (guard__h129151) - 2'b0, 2'b01: - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q119 = - _theResult___snd__h137087[56:5]; - 2'b10: - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q119 = - out_sfd__h137825; - 2'b11: - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q119 = - _theResult___sfd__h137822; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - stateR <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (stateR$EN) stateR <= `BSV_ASSIGNMENT_DELAY stateR$D_IN; - end - if (requestR$EN) requestR <= `BSV_ASSIGNMENT_DELAY requestR$D_IN; - if (resultR$EN) resultR <= `BSV_ASSIGNMENT_DELAY resultR$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - requestR = 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - resultR = 70'h2AAAAAAAAAAAAAAAAA; - stateR = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkFBox_Core - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Top.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Top.v deleted file mode 100644 index 916b8699..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Top.v +++ /dev/null @@ -1,184 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// valid O 1 -// word_fst O 64 -// word_snd O 5 -// CLK I 1 clock -// RST_N I 1 reset -// req_opcode I 7 -// req_f7 I 7 -// req_rm I 3 -// req_rs2 I 5 -// req_v1 I 64 -// req_v2 I 64 -// req_v3 I 64 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFBox_Top(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_opcode, - req_f7, - req_rm, - req_rs2, - req_v1, - req_v2, - req_v3, - EN_req, - - valid, - - word_fst, - - word_snd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [6 : 0] req_opcode; - input [6 : 0] req_f7; - input [2 : 0] req_rm; - input [4 : 0] req_rs2; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input [63 : 0] req_v3; - input EN_req; - - // value method valid - output valid; - - // value method word_fst - output [63 : 0] word_fst; - - // value method word_snd - output [4 : 0] word_snd; - - // signals for module outputs - wire [63 : 0] word_fst; - wire [4 : 0] word_snd; - wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid; - - // ports of submodule fbox_core - wire [63 : 0] fbox_core$req_v1, - fbox_core$req_v2, - fbox_core$req_v3, - fbox_core$word_fst; - wire [6 : 0] fbox_core$req_f7, fbox_core$req_opcode; - wire [4 : 0] fbox_core$req_rs2, fbox_core$word_snd; - wire [2 : 0] fbox_core$req_rm; - wire fbox_core$EN_req, - fbox_core$EN_server_reset_request_put, - fbox_core$EN_server_reset_response_get, - fbox_core$RDY_server_reset_request_put, - fbox_core$RDY_server_reset_response_get, - fbox_core$valid; - - // rule scheduling signals - wire CAN_FIRE_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = - fbox_core$RDY_server_reset_request_put ; - assign CAN_FIRE_server_reset_request_put = - fbox_core$RDY_server_reset_request_put ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - fbox_core$RDY_server_reset_response_get ; - assign CAN_FIRE_server_reset_response_get = - fbox_core$RDY_server_reset_response_get ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = fbox_core$valid ; - - // value method word_fst - assign word_fst = fbox_core$word_fst ; - - // value method word_snd - assign word_snd = fbox_core$word_snd ; - - // submodule fbox_core - mkFBox_Core fbox_core(.CLK(CLK), - .RST_N(RST_N), - .req_f7(fbox_core$req_f7), - .req_opcode(fbox_core$req_opcode), - .req_rm(fbox_core$req_rm), - .req_rs2(fbox_core$req_rs2), - .req_v1(fbox_core$req_v1), - .req_v2(fbox_core$req_v2), - .req_v3(fbox_core$req_v3), - .EN_server_reset_request_put(fbox_core$EN_server_reset_request_put), - .EN_server_reset_response_get(fbox_core$EN_server_reset_response_get), - .EN_req(fbox_core$EN_req), - .RDY_server_reset_request_put(fbox_core$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fbox_core$RDY_server_reset_response_get), - .valid(fbox_core$valid), - .word_fst(fbox_core$word_fst), - .word_snd(fbox_core$word_snd)); - - // submodule fbox_core - assign fbox_core$req_f7 = req_f7 ; - assign fbox_core$req_opcode = req_opcode ; - assign fbox_core$req_rm = req_rm ; - assign fbox_core$req_rs2 = req_rs2 ; - assign fbox_core$req_v1 = req_v1 ; - assign fbox_core$req_v2 = req_v2 ; - assign fbox_core$req_v3 = req_v3 ; - assign fbox_core$EN_server_reset_request_put = EN_server_reset_request_put ; - assign fbox_core$EN_server_reset_response_get = - EN_server_reset_response_get ; - assign fbox_core$EN_req = EN_req ; -endmodule // mkFBox_Top - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPR_RegFile.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPR_RegFile.v deleted file mode 100644 index ae1589d4..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPR_RegFile.v +++ /dev/null @@ -1,258 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 64 -// read_rs1_port2 O 64 -// read_rs2 O 64 -// read_rs3 O 64 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// read_rs3_rs3 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - read_rs3_rs3, - read_rs3, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [63 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [63 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [63 : 0] read_rs2; - - // value method read_rs3 - input [4 : 0] read_rs3_rs3; - output [63 : 0] read_rs3; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [63 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [63 : 0] read_rs1, read_rs1_port2, read_rs2, read_rs3; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [63 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3, - regfile$D_OUT_4; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = regfile$D_OUT_4 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = regfile$D_OUT_3 ; - - // value method read_rs2 - assign read_rs2 = regfile$D_OUT_2 ; - - // value method read_rs3 - assign read_rs3 = regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd64), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(regfile$D_OUT_4), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs3_rs3 ; - assign regfile$ADDR_2 = read_rs2_rs2 ; - assign regfile$ADDR_3 = read_rs1_port2_rs1 ; - assign regfile$ADDR_4 = read_rs1_rs1 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkFPR_RegFile - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPU.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPU.v deleted file mode 100644 index ec7dfc10..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPU.v +++ /dev/null @@ -1,12705 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_core_request_put O 1 reg -// server_core_response_get O 70 reg -// RDY_server_core_response_get O 1 reg -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// server_core_request_put I 202 reg -// EN_server_core_request_put I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_server_core_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFPU(CLK, - RST_N, - - server_core_request_put, - EN_server_core_request_put, - RDY_server_core_request_put, - - EN_server_core_response_get, - server_core_response_get, - RDY_server_core_response_get, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get); - input CLK; - input RST_N; - - // action method server_core_request_put - input [201 : 0] server_core_request_put; - input EN_server_core_request_put; - output RDY_server_core_request_put; - - // actionvalue method server_core_response_get - input EN_server_core_response_get; - output [69 : 0] server_core_response_get; - output RDY_server_core_response_get; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // signals for module outputs - wire [69 : 0] server_core_response_get; - wire RDY_server_core_request_put, - RDY_server_core_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get; - - // inlined wires - reg [68 : 0] resWire$wget; - wire crg_done$EN_port0__write, - crg_done$EN_port1__write, - crg_done$port1__read, - crg_done$port2__read, - crg_done_1$EN_port0__write, - crg_done_1$EN_port1__write, - crg_done_1$port1__read, - crg_done_1$port2__read, - resWire$whas; - - // register crg_done - reg crg_done; - wire crg_done$D_IN, crg_done$EN; - - // register crg_done_1 - reg crg_done_1; - wire crg_done_1$D_IN, crg_done_1$EN; - - // register rg_b - reg [115 : 0] rg_b; - wire [115 : 0] rg_b$D_IN; - wire rg_b$EN; - - // register rg_busy - reg rg_busy; - wire rg_busy$D_IN, rg_busy$EN; - - // register rg_busy_1 - reg rg_busy_1; - wire rg_busy_1$D_IN, rg_busy_1$EN; - - // register rg_d - reg [57 : 0] rg_d; - wire [57 : 0] rg_d$D_IN; - wire rg_d$EN; - - // register rg_index - reg [5 : 0] rg_index; - wire [5 : 0] rg_index$D_IN; - wire rg_index$EN; - - // register rg_index_1 - reg [5 : 0] rg_index_1; - wire [5 : 0] rg_index_1$D_IN; - wire rg_index_1$EN; - - // register rg_q - reg [57 : 0] rg_q; - wire [57 : 0] rg_q$D_IN; - wire rg_q$EN; - - // register rg_r - reg [115 : 0] rg_r; - wire [115 : 0] rg_r$D_IN; - wire rg_r$EN; - - // register rg_r_1 - reg [115 : 0] rg_r_1; - wire [115 : 0] rg_r_1$D_IN; - wire rg_r_1$EN; - - // register rg_res - reg [116 : 0] rg_res; - wire [116 : 0] rg_res$D_IN; - wire rg_res$EN; - - // register rg_s - reg [115 : 0] rg_s; - wire [115 : 0] rg_s$D_IN; - wire rg_s$EN; - - // ports of submodule fpu_div64_fOperands_S0 - wire [130 : 0] fpu_div64_fOperands_S0$D_IN, fpu_div64_fOperands_S0$D_OUT; - wire fpu_div64_fOperands_S0$CLR, - fpu_div64_fOperands_S0$DEQ, - fpu_div64_fOperands_S0$EMPTY_N, - fpu_div64_fOperands_S0$ENQ, - fpu_div64_fOperands_S0$FULL_N; - - // ports of submodule fpu_div64_fResult_S5 - wire [68 : 0] fpu_div64_fResult_S5$D_IN, fpu_div64_fResult_S5$D_OUT; - wire fpu_div64_fResult_S5$CLR, - fpu_div64_fResult_S5$DEQ, - fpu_div64_fResult_S5$EMPTY_N, - fpu_div64_fResult_S5$ENQ, - fpu_div64_fResult_S5$FULL_N; - - // ports of submodule fpu_div64_fState_S1 - wire [318 : 0] fpu_div64_fState_S1$D_IN, fpu_div64_fState_S1$D_OUT; - wire fpu_div64_fState_S1$CLR, - fpu_div64_fState_S1$DEQ, - fpu_div64_fState_S1$EMPTY_N, - fpu_div64_fState_S1$ENQ, - fpu_div64_fState_S1$FULL_N; - - // ports of submodule fpu_div64_fState_S2 - wire [147 : 0] fpu_div64_fState_S2$D_IN, fpu_div64_fState_S2$D_OUT; - wire fpu_div64_fState_S2$CLR, - fpu_div64_fState_S2$DEQ, - fpu_div64_fState_S2$EMPTY_N, - fpu_div64_fState_S2$ENQ, - fpu_div64_fState_S2$FULL_N; - - // ports of submodule fpu_div64_fState_S3 - wire [194 : 0] fpu_div64_fState_S3$D_IN, fpu_div64_fState_S3$D_OUT; - wire fpu_div64_fState_S3$CLR, - fpu_div64_fState_S3$DEQ, - fpu_div64_fState_S3$EMPTY_N, - fpu_div64_fState_S3$ENQ, - fpu_div64_fState_S3$FULL_N; - - // ports of submodule fpu_div64_fState_S4 - wire [138 : 0] fpu_div64_fState_S4$D_IN, fpu_div64_fState_S4$D_OUT; - wire fpu_div64_fState_S4$CLR, - fpu_div64_fState_S4$DEQ, - fpu_div64_fState_S4$EMPTY_N, - fpu_div64_fState_S4$ENQ, - fpu_div64_fState_S4$FULL_N; - - // ports of submodule fpu_madd_fOperand_S0 - wire [195 : 0] fpu_madd_fOperand_S0$D_IN, fpu_madd_fOperand_S0$D_OUT; - wire fpu_madd_fOperand_S0$CLR, - fpu_madd_fOperand_S0$DEQ, - fpu_madd_fOperand_S0$EMPTY_N, - fpu_madd_fOperand_S0$ENQ, - fpu_madd_fOperand_S0$FULL_N; - - // ports of submodule fpu_madd_fProd_S2 - wire [105 : 0] fpu_madd_fProd_S2$D_IN, fpu_madd_fProd_S2$D_OUT; - wire fpu_madd_fProd_S2$CLR, - fpu_madd_fProd_S2$DEQ, - fpu_madd_fProd_S2$EMPTY_N, - fpu_madd_fProd_S2$ENQ, - fpu_madd_fProd_S2$FULL_N; - - // ports of submodule fpu_madd_fProd_S3 - wire [105 : 0] fpu_madd_fProd_S3$D_IN, fpu_madd_fProd_S3$D_OUT; - wire fpu_madd_fProd_S3$CLR, - fpu_madd_fProd_S3$DEQ, - fpu_madd_fProd_S3$EMPTY_N, - fpu_madd_fProd_S3$ENQ, - fpu_madd_fProd_S3$FULL_N; - - // ports of submodule fpu_madd_fResult_S9 - wire [68 : 0] fpu_madd_fResult_S9$D_IN, fpu_madd_fResult_S9$D_OUT; - wire fpu_madd_fResult_S9$CLR, - fpu_madd_fResult_S9$DEQ, - fpu_madd_fResult_S9$EMPTY_N, - fpu_madd_fResult_S9$ENQ, - fpu_madd_fResult_S9$FULL_N; - - // ports of submodule fpu_madd_fState_S1 - wire [257 : 0] fpu_madd_fState_S1$D_IN, fpu_madd_fState_S1$D_OUT; - wire fpu_madd_fState_S1$CLR, - fpu_madd_fState_S1$DEQ, - fpu_madd_fState_S1$EMPTY_N, - fpu_madd_fState_S1$ENQ, - fpu_madd_fState_S1$FULL_N; - - // ports of submodule fpu_madd_fState_S2 - wire [151 : 0] fpu_madd_fState_S2$D_IN, fpu_madd_fState_S2$D_OUT; - wire fpu_madd_fState_S2$CLR, - fpu_madd_fState_S2$DEQ, - fpu_madd_fState_S2$EMPTY_N, - fpu_madd_fState_S2$ENQ, - fpu_madd_fState_S2$FULL_N; - - // ports of submodule fpu_madd_fState_S3 - wire [151 : 0] fpu_madd_fState_S3$D_IN, fpu_madd_fState_S3$D_OUT; - wire fpu_madd_fState_S3$CLR, - fpu_madd_fState_S3$DEQ, - fpu_madd_fState_S3$EMPTY_N, - fpu_madd_fState_S3$ENQ, - fpu_madd_fState_S3$FULL_N; - - // ports of submodule fpu_madd_fState_S4 - wire [203 : 0] fpu_madd_fState_S4$D_IN, fpu_madd_fState_S4$D_OUT; - wire fpu_madd_fState_S4$CLR, - fpu_madd_fState_S4$DEQ, - fpu_madd_fState_S4$EMPTY_N, - fpu_madd_fState_S4$ENQ, - fpu_madd_fState_S4$FULL_N; - - // ports of submodule fpu_madd_fState_S5 - wire [215 : 0] fpu_madd_fState_S5$D_IN, fpu_madd_fState_S5$D_OUT; - wire fpu_madd_fState_S5$CLR, - fpu_madd_fState_S5$DEQ, - fpu_madd_fState_S5$EMPTY_N, - fpu_madd_fState_S5$ENQ, - fpu_madd_fState_S5$FULL_N; - - // ports of submodule fpu_madd_fState_S6 - wire [202 : 0] fpu_madd_fState_S6$D_IN, fpu_madd_fState_S6$D_OUT; - wire fpu_madd_fState_S6$CLR, - fpu_madd_fState_S6$DEQ, - fpu_madd_fState_S6$EMPTY_N, - fpu_madd_fState_S6$ENQ, - fpu_madd_fState_S6$FULL_N; - - // ports of submodule fpu_madd_fState_S7 - wire [202 : 0] fpu_madd_fState_S7$D_IN, fpu_madd_fState_S7$D_OUT; - wire fpu_madd_fState_S7$CLR, - fpu_madd_fState_S7$DEQ, - fpu_madd_fState_S7$EMPTY_N, - fpu_madd_fState_S7$ENQ, - fpu_madd_fState_S7$FULL_N; - - // ports of submodule fpu_madd_fState_S8 - wire [140 : 0] fpu_madd_fState_S8$D_IN, fpu_madd_fState_S8$D_OUT; - wire fpu_madd_fState_S8$CLR, - fpu_madd_fState_S8$DEQ, - fpu_madd_fState_S8$EMPTY_N, - fpu_madd_fState_S8$ENQ, - fpu_madd_fState_S8$FULL_N; - - // ports of submodule fpu_sqr64_fOperand_S0 - wire [66 : 0] fpu_sqr64_fOperand_S0$D_IN, fpu_sqr64_fOperand_S0$D_OUT; - wire fpu_sqr64_fOperand_S0$CLR, - fpu_sqr64_fOperand_S0$DEQ, - fpu_sqr64_fOperand_S0$EMPTY_N, - fpu_sqr64_fOperand_S0$ENQ, - fpu_sqr64_fOperand_S0$FULL_N; - - // ports of submodule fpu_sqr64_fResult_S5 - wire [68 : 0] fpu_sqr64_fResult_S5$D_IN, fpu_sqr64_fResult_S5$D_OUT; - wire fpu_sqr64_fResult_S5$CLR, - fpu_sqr64_fResult_S5$DEQ, - fpu_sqr64_fResult_S5$EMPTY_N, - fpu_sqr64_fResult_S5$ENQ, - fpu_sqr64_fResult_S5$FULL_N; - - // ports of submodule fpu_sqr64_fState_S1 - wire [194 : 0] fpu_sqr64_fState_S1$D_IN, fpu_sqr64_fState_S1$D_OUT; - wire fpu_sqr64_fState_S1$CLR, - fpu_sqr64_fState_S1$DEQ, - fpu_sqr64_fState_S1$EMPTY_N, - fpu_sqr64_fState_S1$ENQ, - fpu_sqr64_fState_S1$FULL_N; - - // ports of submodule fpu_sqr64_fState_S2 - wire [136 : 0] fpu_sqr64_fState_S2$D_IN, fpu_sqr64_fState_S2$D_OUT; - wire fpu_sqr64_fState_S2$CLR, - fpu_sqr64_fState_S2$DEQ, - fpu_sqr64_fState_S2$EMPTY_N, - fpu_sqr64_fState_S2$ENQ, - fpu_sqr64_fState_S2$FULL_N; - - // ports of submodule fpu_sqr64_fState_S3 - wire [195 : 0] fpu_sqr64_fState_S3$D_IN, fpu_sqr64_fState_S3$D_OUT; - wire fpu_sqr64_fState_S3$CLR, - fpu_sqr64_fState_S3$DEQ, - fpu_sqr64_fState_S3$EMPTY_N, - fpu_sqr64_fState_S3$ENQ, - fpu_sqr64_fState_S3$FULL_N; - - // ports of submodule fpu_sqr64_fState_S4 - wire [138 : 0] fpu_sqr64_fState_S4$D_IN, fpu_sqr64_fState_S4$D_OUT; - wire fpu_sqr64_fState_S4$CLR, - fpu_sqr64_fState_S4$DEQ, - fpu_sqr64_fState_S4$EMPTY_N, - fpu_sqr64_fState_S4$ENQ, - fpu_sqr64_fState_S4$FULL_N; - - // ports of submodule iFifo - wire [201 : 0] iFifo$D_IN, iFifo$D_OUT; - wire iFifo$CLR, iFifo$DEQ, iFifo$EMPTY_N, iFifo$ENQ, iFifo$FULL_N; - - // ports of submodule isDoubleFifo - wire isDoubleFifo$CLR, - isDoubleFifo$DEQ, - isDoubleFifo$D_IN, - isDoubleFifo$D_OUT, - isDoubleFifo$EMPTY_N, - isDoubleFifo$ENQ, - isDoubleFifo$FULL_N; - - // ports of submodule isNegateFifo - wire isNegateFifo$CLR, - isNegateFifo$DEQ, - isNegateFifo$D_IN, - isNegateFifo$D_OUT, - isNegateFifo$EMPTY_N, - isNegateFifo$ENQ, - isNegateFifo$FULL_N; - - // ports of submodule oFifo - wire [69 : 0] oFifo$D_IN, oFifo$D_OUT; - wire oFifo$CLR, oFifo$DEQ, oFifo$EMPTY_N, oFifo$ENQ, oFifo$FULL_N; - - // ports of submodule resetReqsF - wire resetReqsF$CLR, - resetReqsF$DEQ, - resetReqsF$EMPTY_N, - resetReqsF$ENQ, - resetReqsF$FULL_N; - - // ports of submodule resetRspsF - wire resetRspsF$CLR, - resetRspsF$DEQ, - resetRspsF$EMPTY_N, - resetRspsF$ENQ, - resetRspsF$FULL_N; - - // ports of submodule rmdFifo - wire [2 : 0] rmdFifo$D_IN, rmdFifo$D_OUT; - wire rmdFifo$CLR, rmdFifo$DEQ, rmdFifo$EMPTY_N, rmdFifo$ENQ, rmdFifo$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_fpu_div64_s1_stage, - CAN_FIRE_RL_fpu_div64_s2_stage, - CAN_FIRE_RL_fpu_div64_s3_stage, - CAN_FIRE_RL_fpu_div64_s4_stage, - CAN_FIRE_RL_fpu_div64_s5_stage, - CAN_FIRE_RL_fpu_madd_s1_stage, - CAN_FIRE_RL_fpu_madd_s2_stage, - CAN_FIRE_RL_fpu_madd_s3_stage, - CAN_FIRE_RL_fpu_madd_s4_stage, - CAN_FIRE_RL_fpu_madd_s5_stage, - CAN_FIRE_RL_fpu_madd_s6_stage, - CAN_FIRE_RL_fpu_madd_s7_stage, - CAN_FIRE_RL_fpu_madd_s8_stage, - CAN_FIRE_RL_fpu_madd_s9_stage, - CAN_FIRE_RL_fpu_sqr64_s1_stage, - CAN_FIRE_RL_fpu_sqr64_s2_stage, - CAN_FIRE_RL_fpu_sqr64_s3_stage, - CAN_FIRE_RL_fpu_sqr64_s4_stage, - CAN_FIRE_RL_fpu_sqr64_s5_stage, - CAN_FIRE_RL_getResDiv, - CAN_FIRE_RL_getResMAdd, - CAN_FIRE_RL_getResSqr, - CAN_FIRE_RL_passResult, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_start_op, - CAN_FIRE_RL_work, - CAN_FIRE_RL_work_1, - CAN_FIRE___me_check_22, - CAN_FIRE___me_check_23, - CAN_FIRE_server_core_request_put, - CAN_FIRE_server_core_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_RL_fpu_div64_s1_stage, - WILL_FIRE_RL_fpu_div64_s2_stage, - WILL_FIRE_RL_fpu_div64_s3_stage, - WILL_FIRE_RL_fpu_div64_s4_stage, - WILL_FIRE_RL_fpu_div64_s5_stage, - WILL_FIRE_RL_fpu_madd_s1_stage, - WILL_FIRE_RL_fpu_madd_s2_stage, - WILL_FIRE_RL_fpu_madd_s3_stage, - WILL_FIRE_RL_fpu_madd_s4_stage, - WILL_FIRE_RL_fpu_madd_s5_stage, - WILL_FIRE_RL_fpu_madd_s6_stage, - WILL_FIRE_RL_fpu_madd_s7_stage, - WILL_FIRE_RL_fpu_madd_s8_stage, - WILL_FIRE_RL_fpu_madd_s9_stage, - WILL_FIRE_RL_fpu_sqr64_s1_stage, - WILL_FIRE_RL_fpu_sqr64_s2_stage, - WILL_FIRE_RL_fpu_sqr64_s3_stage, - WILL_FIRE_RL_fpu_sqr64_s4_stage, - WILL_FIRE_RL_fpu_sqr64_s5_stage, - WILL_FIRE_RL_getResDiv, - WILL_FIRE_RL_getResMAdd, - WILL_FIRE_RL_getResSqr, - WILL_FIRE_RL_passResult, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_start_op, - WILL_FIRE_RL_work, - WILL_FIRE_RL_work_1, - WILL_FIRE___me_check_22, - WILL_FIRE___me_check_23, - WILL_FIRE_server_core_request_put, - WILL_FIRE_server_core_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // inputs to muxes for submodule ports - wire [116 : 0] MUX_rg_res$write_1__VAL_2; - wire [115 : 0] MUX_rg_b$write_1__VAL_1, - MUX_rg_b$write_1__VAL_2, - MUX_rg_r$write_1__VAL_1, - MUX_rg_r$write_1__VAL_2, - MUX_rg_r_1$write_1__VAL_2, - MUX_rg_s$write_1__VAL_1, - MUX_rg_s$write_1__VAL_2; - wire [57 : 0] MUX_rg_d$write_1__VAL_1, MUX_rg_q$write_1__VAL_2; - wire [5 : 0] MUX_rg_index$write_1__VAL_2, MUX_rg_index_1$write_1__VAL_2; - wire MUX_crg_done$port1__write_1__SEL_1, - MUX_crg_done$port1__write_1__SEL_2, - MUX_crg_done_1$port1__write_1__SEL_1, - MUX_crg_done_1$port1__write_1__SEL_2; - - // remaining internal signals - reg [63 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183, - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177, - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623; - reg [62 : 0] CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131, - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179; - reg [51 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4, - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110, - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111, - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112, - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113, - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75, - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76, - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77, - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78, - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79, - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80, - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48, - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49, - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50, - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51, - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52, - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53, - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108, - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109, - _theResult___fst_sfd__h142620, - _theResult___fst_sfd__h148292, - _theResult___fst_sfd__h164060, - _theResult___fst_sfd__h173650, - _theResult___fst_sfd__h182402, - _theResult___fst_sfd__h186932, - _theResult___fst_sfd__h19468, - _theResult___fst_sfd__h19957, - _theResult___fst_sfd__h202698, - _theResult___fst_sfd__h212288, - _theResult___fst_sfd__h221040, - _theResult___fst_sfd__h225871, - _theResult___fst_sfd__h241637, - _theResult___fst_sfd__h251227, - _theResult___fst_sfd__h259979, - _theResult___fst_sfd__h43554, - _theResult___fst_sfd__h95988; - reg [22 : 0] CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162, - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163, - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160, - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161, - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164, - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165, - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166, - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167, - _theResult___fst_sfd__h269560, - _theResult___fst_sfd__h278281, - _theResult___fst_sfd__h286863, - _theResult___fst_sfd__h296047, - _theResult___fst_sfd__h304683; - reg [10 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22, - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104, - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105, - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106, - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107, - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69, - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70, - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71, - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72, - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73, - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74, - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42, - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43, - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44, - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45, - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46, - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47, - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102, - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103, - _theResult___fst_exp__h142619, - _theResult___fst_exp__h148291, - _theResult___fst_exp__h164059, - _theResult___fst_exp__h173649, - _theResult___fst_exp__h182401, - _theResult___fst_exp__h186931, - _theResult___fst_exp__h19467, - _theResult___fst_exp__h202697, - _theResult___fst_exp__h212287, - _theResult___fst_exp__h221039, - _theResult___fst_exp__h225870, - _theResult___fst_exp__h241636, - _theResult___fst_exp__h251226, - _theResult___fst_exp__h259978, - _theResult___fst_exp__h43553, - _theResult___fst_exp__h95987; - reg [7 : 0] CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154, - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155, - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152, - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153, - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156, - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157, - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158, - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159, - _theResult___fst_exp__h269559, - _theResult___fst_exp__h278280, - _theResult___fst_exp__h286862, - _theResult___fst_exp__h296046, - _theResult___fst_exp__h304682; - reg CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9, - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126, - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178, - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122, - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116, - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124, - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118, - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87, - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81, - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89, - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83, - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91, - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85, - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54, - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56, - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145, - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144, - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58, - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147, - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146, - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149, - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148, - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120, - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114, - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151, - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348, - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028, - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418; - wire [194 : 0] IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212; - wire [139 : 0] IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595; - wire [118 : 0] IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959; - wire [115 : 0] IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83, - IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22, - IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72, - _theResult___fst__h1476, - _theResult___fst__h1515, - _theResult___fst__h1600, - _theResult___snd_fst__h1478, - _theResult___snd_fst__h1517, - _theResult___snd_fst__h1602, - _theResult___snd_snd__h1649, - _theResult___snd_snd__h1715, - _theResult___snd_snd_snd__h1481, - _theResult___snd_snd_snd__h1520, - _theResult___snd_snd_snd__h1605, - b___1__h77160, - b__h1608, - b__h1712, - b__h32583, - r__h1659, - r__h1663, - r__h1724, - r__h1753, - s__h1658, - s__h1723, - sum__h1606, - sum__h1710, - value__h32541, - x__h85931; - wire [113 : 0] x__h31426; - wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24, - _theResult___fst__h116827, - _theResult___snd__h130966, - _theResult___snd__h130980, - _theResult___snd__h130982, - _theResult___snd__h130994, - _theResult___snd__h131000, - _theResult___snd__h131018, - _theResult___snd__h131023, - fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012, - sfdBC__h115662, - sfdin__h130943, - x__h116896; - wire [68 : 0] IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081; - wire [63 : 0] IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612, - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330, - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555, - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618, - IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657, - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452, - fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936; - wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980, - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065, - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552; - wire [58 : 0] IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19, - _theResult___snd__h94767, - _theResult___snd__h94782, - _theResult___snd__h94784, - _theResult___snd__h94797, - _theResult___snd__h94803, - _theResult___snd__h94821, - _theResult___snd__h94826, - result__h85925, - sfdin__h94744, - x__h86149; - wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12, - IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14, - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10, - _theResult____h32523, - _theResult___snd__h34715, - _theResult___snd__h42350, - _theResult___snd__h42365, - _theResult___snd__h42367, - _theResult___snd__h42380, - _theResult___snd__h42386, - _theResult___snd__h42404, - _theResult___snd__h42409, - _theResult___snd_snd_snd__h33963, - result__h32617, - result__h32648, - result__h32823, - rg_q_PLUS_NEG_INV_rg_q_59_60___d561, - sfd___1__h60702, - sfd__h44951, - sfd__h44953, - sfdin__h34118, - sfdin__h42327, - x__h32762, - x__h33052, - x__h60693; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139, - IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29, - IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100, - IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93, - IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33, - IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40, - IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60, - IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67, - IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135, - IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038, - _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038, - _theResult____h164614, - _theResult____h203252, - _theResult____h242191, - _theResult____h269577, - _theResult____h287214, - _theResult___snd__h141392, - _theResult___snd__h141406, - _theResult___snd__h141408, - _theResult___snd__h141420, - _theResult___snd__h141426, - _theResult___snd__h141444, - _theResult___snd__h141449, - _theResult___snd__h163287, - _theResult___snd__h163289, - _theResult___snd__h163296, - _theResult___snd__h163302, - _theResult___snd__h163325, - _theResult___snd__h172863, - _theResult___snd__h172874, - _theResult___snd__h172876, - _theResult___snd__h172886, - _theResult___snd__h172892, - _theResult___snd__h172915, - _theResult___snd__h181599, - _theResult___snd__h181613, - _theResult___snd__h181619, - _theResult___snd__h181637, - _theResult___snd__h201925, - _theResult___snd__h201927, - _theResult___snd__h201934, - _theResult___snd__h201940, - _theResult___snd__h201963, - _theResult___snd__h211501, - _theResult___snd__h211512, - _theResult___snd__h211514, - _theResult___snd__h211524, - _theResult___snd__h211530, - _theResult___snd__h211553, - _theResult___snd__h220237, - _theResult___snd__h220251, - _theResult___snd__h220257, - _theResult___snd__h220275, - _theResult___snd__h240864, - _theResult___snd__h240866, - _theResult___snd__h240873, - _theResult___snd__h240879, - _theResult___snd__h240902, - _theResult___snd__h250440, - _theResult___snd__h250451, - _theResult___snd__h250453, - _theResult___snd__h250463, - _theResult___snd__h250469, - _theResult___snd__h250492, - _theResult___snd__h259176, - _theResult___snd__h259190, - _theResult___snd__h259196, - _theResult___snd__h259214, - _theResult___snd__h277697, - _theResult___snd__h277708, - _theResult___snd__h277710, - _theResult___snd__h277720, - _theResult___snd__h277726, - _theResult___snd__h277749, - _theResult___snd__h286293, - _theResult___snd__h286295, - _theResult___snd__h286302, - _theResult___snd__h286308, - _theResult___snd__h286331, - _theResult___snd__h295463, - _theResult___snd__h295474, - _theResult___snd__h295476, - _theResult___snd__h295486, - _theResult___snd__h295492, - _theResult___snd__h295515, - _theResult___snd__h304083, - _theResult___snd__h304097, - _theResult___snd__h304103, - _theResult___snd__h304121, - fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615, - guard__h132367, - result__h132372, - result__h165227, - result__h203865, - result__h242804, - result__h287827, - sfdA__h131577, - sfdBC__h131578, - sfd__h133119, - sfd__h144536, - sfd__h183176, - sfd__h222115, - sfd__h261975, - sfdin__h141369, - sfdin__h172846, - sfdin__h211484, - sfdin__h250423, - sfdin__h277680, - sfdin__h295446, - value__h32661, - x__h131940, - x__h131944, - x__h132359, - x__h132871, - x__h132880, - x__h165324, - x__h203962, - x__h242901, - x__h287924, - x__h31487; - wire [53 : 0] sfd__h142040, - sfd__h163354, - sfd__h172944, - sfd__h181672, - sfd__h201992, - sfd__h211582, - sfd__h220310, - sfd__h240931, - sfd__h250521, - sfd__h259249, - sfd__h42982, - sfd__h95416, - value__h270197, - value__h31429, - value__h53174; - wire [52 : 0] sfdA__h2035, - sfdA__h2039, - sfdB__h2036, - sfdB__h2041, - x__h114243, - x__h114255; - wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450, - _theResult___fst_sfd__h164063, - _theResult___fst_sfd__h173653, - _theResult___fst_sfd__h182405, - _theResult___fst_sfd__h182414, - _theResult___fst_sfd__h182420, - _theResult___fst_sfd__h202701, - _theResult___fst_sfd__h212291, - _theResult___fst_sfd__h221043, - _theResult___fst_sfd__h221052, - _theResult___fst_sfd__h221058, - _theResult___fst_sfd__h241640, - _theResult___fst_sfd__h251230, - _theResult___fst_sfd__h259982, - _theResult___fst_sfd__h259991, - _theResult___fst_sfd__h259997, - _theResult___fst_sfd__h43557, - _theResult___fst_sfd__h95991, - _theResult___fst_sfd__h96608, - _theResult___sfd__h142542, - _theResult___sfd__h163982, - _theResult___sfd__h173572, - _theResult___sfd__h182324, - _theResult___sfd__h202620, - _theResult___sfd__h212210, - _theResult___sfd__h220962, - _theResult___sfd__h241559, - _theResult___sfd__h251149, - _theResult___sfd__h259901, - _theResult___sfd__h43476, - _theResult___sfd__h95910, - _theResult___snd_fst_sfd__h144486, - _theResult___snd_fst_sfd__h164066, - _theResult___snd_fst_sfd__h182408, - _theResult___snd_fst_sfd__h183126, - _theResult___snd_fst_sfd__h202704, - _theResult___snd_fst_sfd__h221046, - _theResult___snd_fst_sfd__h222065, - _theResult___snd_fst_sfd__h241643, - _theResult___snd_fst_sfd__h259985, - _theResult___snd_fst_sfd__h31362, - out___1_sfd__h144235, - out___1_sfd__h182875, - out___1_sfd__h221814, - out_sfd__h142545, - out_sfd__h163985, - out_sfd__h173575, - out_sfd__h182327, - out_sfd__h202623, - out_sfd__h212213, - out_sfd__h220965, - out_sfd__h241562, - out_sfd__h251152, - out_sfd__h259904, - out_sfd__h43479, - out_sfd__h95913, - sfd__h18934, - sfd__h18937, - sfd__h45004, - sfd__h99402, - sfd__h99405, - sfd__h99408; - wire [24 : 0] sfd__h277778, - sfd__h286360, - sfd__h295544, - sfd__h304156, - value__h148923, - value__h187561, - value__h226500; - wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576, - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643, - _theResult___fst_sfd__h278284, - _theResult___fst_sfd__h286866, - _theResult___fst_sfd__h296050, - _theResult___fst_sfd__h304686, - _theResult___fst_sfd__h304695, - _theResult___fst_sfd__h304701, - _theResult___sfd__h278203, - _theResult___sfd__h286785, - _theResult___sfd__h295969, - _theResult___sfd__h304605, - _theResult___snd_fst_sfd__h261925, - _theResult___snd_fst_sfd__h286869, - _theResult___snd_fst_sfd__h304689, - out_sfd__h278206, - out_sfd__h286788, - out_sfd__h295972, - out_sfd__h304608, - sfd__h304707; - wire [12 : 0] IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352, - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568, - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195, - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007, - value__h130883, - value__h141307, - value__h31374, - value__h31550, - x__h116929, - x__h132471, - x__h52551, - x__h52569; - wire [11 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106, - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331, - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668, - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17, - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389, - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531, - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809, - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326, - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683, - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034, - x__h165357, - x__h203995, - x__h242934, - x__h287957; - wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433, - IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011, - IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66, - _theResult___exp__h142541, - _theResult___exp__h163981, - _theResult___exp__h173571, - _theResult___exp__h182323, - _theResult___exp__h202619, - _theResult___exp__h212209, - _theResult___exp__h220961, - _theResult___exp__h241558, - _theResult___exp__h251148, - _theResult___exp__h259900, - _theResult___exp__h43475, - _theResult___exp__h95909, - _theResult___fst__h31322, - _theResult___fst_exp__h130949, - _theResult___fst_exp__h130952, - _theResult___fst_exp__h130971, - _theResult___fst_exp__h130986, - _theResult___fst_exp__h131025, - _theResult___fst_exp__h131031, - _theResult___fst_exp__h131034, - _theResult___fst_exp__h141375, - _theResult___fst_exp__h141378, - _theResult___fst_exp__h141397, - _theResult___fst_exp__h141412, - _theResult___fst_exp__h141451, - _theResult___fst_exp__h141457, - _theResult___fst_exp__h141460, - _theResult___fst_exp__h163327, - _theResult___fst_exp__h163333, - _theResult___fst_exp__h163336, - _theResult___fst_exp__h164062, - _theResult___fst_exp__h172852, - _theResult___fst_exp__h172917, - _theResult___fst_exp__h172923, - _theResult___fst_exp__h172926, - _theResult___fst_exp__h173652, - _theResult___fst_exp__h181605, - _theResult___fst_exp__h181644, - _theResult___fst_exp__h181650, - _theResult___fst_exp__h181653, - _theResult___fst_exp__h182404, - _theResult___fst_exp__h182413, - _theResult___fst_exp__h182416, - _theResult___fst_exp__h201965, - _theResult___fst_exp__h201971, - _theResult___fst_exp__h201974, - _theResult___fst_exp__h202700, - _theResult___fst_exp__h211490, - _theResult___fst_exp__h211555, - _theResult___fst_exp__h211561, - _theResult___fst_exp__h211564, - _theResult___fst_exp__h212290, - _theResult___fst_exp__h220243, - _theResult___fst_exp__h220282, - _theResult___fst_exp__h220288, - _theResult___fst_exp__h220291, - _theResult___fst_exp__h221042, - _theResult___fst_exp__h221051, - _theResult___fst_exp__h221054, - _theResult___fst_exp__h240904, - _theResult___fst_exp__h240910, - _theResult___fst_exp__h240913, - _theResult___fst_exp__h241639, - _theResult___fst_exp__h250429, - _theResult___fst_exp__h250494, - _theResult___fst_exp__h250500, - _theResult___fst_exp__h250503, - _theResult___fst_exp__h251229, - _theResult___fst_exp__h259182, - _theResult___fst_exp__h259221, - _theResult___fst_exp__h259227, - _theResult___fst_exp__h259230, - _theResult___fst_exp__h259981, - _theResult___fst_exp__h259990, - _theResult___fst_exp__h259993, - _theResult___fst_exp__h42284, - _theResult___fst_exp__h42287, - _theResult___fst_exp__h42290, - _theResult___fst_exp__h42333, - _theResult___fst_exp__h42336, - _theResult___fst_exp__h42356, - _theResult___fst_exp__h42372, - _theResult___fst_exp__h42411, - _theResult___fst_exp__h42417, - _theResult___fst_exp__h42420, - _theResult___fst_exp__h43556, - _theResult___fst_exp__h94750, - _theResult___fst_exp__h94753, - _theResult___fst_exp__h94773, - _theResult___fst_exp__h94789, - _theResult___fst_exp__h94828, - _theResult___fst_exp__h94834, - _theResult___fst_exp__h94837, - _theResult___fst_exp__h95990, - _theResult___snd_fst_exp__h164065, - _theResult___snd_fst_exp__h182407, - _theResult___snd_fst_exp__h202703, - _theResult___snd_fst_exp__h221045, - _theResult___snd_fst_exp__h241642, - _theResult___snd_fst_exp__h259984, - _theResult___snd_fst_exp__h31334, - _theResult___snd_fst_exp__h31337, - _theResult___snd_fst_exp__h31361, - din_exp30866_MINUS_1023__q23, - din_exp__h130866, - din_inc___2_exp__h142626, - din_inc___2_exp__h182469, - din_inc___2_exp__h182504, - din_inc___2_exp__h182530, - din_inc___2_exp__h221107, - din_inc___2_exp__h221142, - din_inc___2_exp__h221168, - din_inc___2_exp__h260046, - din_inc___2_exp__h260081, - din_inc___2_exp__h260107, - din_inc___2_exp__h43566, - din_inc___2_exp__h96000, - fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7, - fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8, - fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128, - fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129, - fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27, - fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26, - fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16, - fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18, - out_exp__h142544, - out_exp__h163984, - out_exp__h173574, - out_exp__h182326, - out_exp__h202622, - out_exp__h212212, - out_exp__h220964, - out_exp__h241561, - out_exp__h251151, - out_exp__h259903, - out_exp__h43478, - out_exp__h95912, - resWirewget_BITS_67_TO_57_MINUS_1023__q137, - theResult___fst_exp2290_MINUS_1023__q11, - value41307_BITS_10_TO_0_MINUS_1023__q28, - x__h31541, - x__h32769, - x__h96539; - wire [8 : 0] IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332; - wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448, - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141, - _theResult___exp__h278202, - _theResult___exp__h286784, - _theResult___exp__h295968, - _theResult___exp__h304604, - _theResult___fst_exp__h277686, - _theResult___fst_exp__h277751, - _theResult___fst_exp__h277757, - _theResult___fst_exp__h277760, - _theResult___fst_exp__h278283, - _theResult___fst_exp__h286333, - _theResult___fst_exp__h286339, - _theResult___fst_exp__h286342, - _theResult___fst_exp__h286865, - _theResult___fst_exp__h295452, - _theResult___fst_exp__h295517, - _theResult___fst_exp__h295523, - _theResult___fst_exp__h295526, - _theResult___fst_exp__h296049, - _theResult___fst_exp__h304089, - _theResult___fst_exp__h304128, - _theResult___fst_exp__h304134, - _theResult___fst_exp__h304137, - _theResult___fst_exp__h304685, - _theResult___fst_exp__h304694, - _theResult___fst_exp__h304697, - _theResult___snd_fst_exp__h286868, - _theResult___snd_fst_exp__h304688, - din_inc___2_exp__h304723, - din_inc___2_exp__h304749, - din_inc___2_exp__h304784, - din_inc___2_exp__h304810, - exp__h304706, - iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95, - iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35, - iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62, - out_exp__h278205, - out_exp__h286787, - out_exp__h295971, - out_exp__h304607; - wire [6 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460, - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342, - x__h85465; - wire [5 : 0] IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982, - b__h11457, - b__h4039, - x__h60732; - wire [4 : 0] IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926, - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921, - IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688, - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501, - fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942, - fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043, - resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768; - wire [2 : 0] IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523; - wire [1 : 0] IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98, - IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13, - IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25, - IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30, - IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20, - IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65, - IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38, - IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134, - IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140, - IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94, - IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143, - IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101, - IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61, - IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68, - IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34, - IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41, - IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136, - _theResult___snd_fst__h131051, - _theResult___snd_fst__h141477, - _theResult___snd_fst__h42439, - _theResult___snd_fst__h94856, - _theResult___snd_snd__h131371, - _theResult___snd_snd_snd__h131369, - guardBC__h115666, - guard__h133123, - guard__h155375, - guard__h164624, - guard__h173663, - guard__h194013, - guard__h203262, - guard__h212301, - guard__h232952, - guard__h242201, - guard__h251240, - guard__h269587, - guard__h278294, - guard__h287224, - guard__h296060, - guard__h33946, - guard__h86435, - x__h131406, - x__h141760, - x__h42705, - x__h95138; - wire IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025, - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374, - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422, - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521, - IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610, - IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85, - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56, - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44, - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728, - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756, - NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946, - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400, - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481, - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488, - NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923, - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584, - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244, - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955, - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730, - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280, - _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463, - _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883, - _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904, - _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633, - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759, - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107, - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273, - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624, - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984, - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685, - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498, - fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359, - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405, - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857, - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926, - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004, - guard__h165222, - guard__h203860, - guard__h242799, - guard__h287822, - rg_index_1_4_PLUS_1_6_ULE_58___d37, - rg_index_1_4_ULE_58___d38, - rg_index_PLUS_1_ULE_57___d6, - rg_index_ULE_57___d7, - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63, - sfdlsb__h116825, - sfdlsb__h32643, - value_BIT_52___h53270; - - // action method server_core_request_put - assign RDY_server_core_request_put = iFifo$FULL_N ; - assign CAN_FIRE_server_core_request_put = iFifo$FULL_N ; - assign WILL_FIRE_server_core_request_put = EN_server_core_request_put ; - - // actionvalue method server_core_response_get - assign server_core_response_get = oFifo$D_OUT ; - assign RDY_server_core_response_get = oFifo$EMPTY_N ; - assign CAN_FIRE_server_core_response_get = oFifo$EMPTY_N ; - assign WILL_FIRE_server_core_response_get = EN_server_core_response_get ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = resetReqsF$FULL_N ; - assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // submodule fpu_div64_fOperands_S0 - FIFOL1 #(.width(32'd131)) fpu_div64_fOperands_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fOperands_S0$D_IN), - .ENQ(fpu_div64_fOperands_S0$ENQ), - .DEQ(fpu_div64_fOperands_S0$DEQ), - .CLR(fpu_div64_fOperands_S0$CLR), - .D_OUT(fpu_div64_fOperands_S0$D_OUT), - .FULL_N(fpu_div64_fOperands_S0$FULL_N), - .EMPTY_N(fpu_div64_fOperands_S0$EMPTY_N)); - - // submodule fpu_div64_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_div64_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fResult_S5$D_IN), - .ENQ(fpu_div64_fResult_S5$ENQ), - .DEQ(fpu_div64_fResult_S5$DEQ), - .CLR(fpu_div64_fResult_S5$CLR), - .D_OUT(fpu_div64_fResult_S5$D_OUT), - .FULL_N(fpu_div64_fResult_S5$FULL_N), - .EMPTY_N(fpu_div64_fResult_S5$EMPTY_N)); - - // submodule fpu_div64_fState_S1 - FIFOL1 #(.width(32'd319)) fpu_div64_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S1$D_IN), - .ENQ(fpu_div64_fState_S1$ENQ), - .DEQ(fpu_div64_fState_S1$DEQ), - .CLR(fpu_div64_fState_S1$CLR), - .D_OUT(fpu_div64_fState_S1$D_OUT), - .FULL_N(fpu_div64_fState_S1$FULL_N), - .EMPTY_N(fpu_div64_fState_S1$EMPTY_N)); - - // submodule fpu_div64_fState_S2 - FIFOL1 #(.width(32'd148)) fpu_div64_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S2$D_IN), - .ENQ(fpu_div64_fState_S2$ENQ), - .DEQ(fpu_div64_fState_S2$DEQ), - .CLR(fpu_div64_fState_S2$CLR), - .D_OUT(fpu_div64_fState_S2$D_OUT), - .FULL_N(fpu_div64_fState_S2$FULL_N), - .EMPTY_N(fpu_div64_fState_S2$EMPTY_N)); - - // submodule fpu_div64_fState_S3 - FIFOL1 #(.width(32'd195)) fpu_div64_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S3$D_IN), - .ENQ(fpu_div64_fState_S3$ENQ), - .DEQ(fpu_div64_fState_S3$DEQ), - .CLR(fpu_div64_fState_S3$CLR), - .D_OUT(fpu_div64_fState_S3$D_OUT), - .FULL_N(fpu_div64_fState_S3$FULL_N), - .EMPTY_N(fpu_div64_fState_S3$EMPTY_N)); - - // submodule fpu_div64_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_div64_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S4$D_IN), - .ENQ(fpu_div64_fState_S4$ENQ), - .DEQ(fpu_div64_fState_S4$DEQ), - .CLR(fpu_div64_fState_S4$CLR), - .D_OUT(fpu_div64_fState_S4$D_OUT), - .FULL_N(fpu_div64_fState_S4$FULL_N), - .EMPTY_N(fpu_div64_fState_S4$EMPTY_N)); - - // submodule fpu_madd_fOperand_S0 - FIFOL1 #(.width(32'd196)) fpu_madd_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fOperand_S0$D_IN), - .ENQ(fpu_madd_fOperand_S0$ENQ), - .DEQ(fpu_madd_fOperand_S0$DEQ), - .CLR(fpu_madd_fOperand_S0$CLR), - .D_OUT(fpu_madd_fOperand_S0$D_OUT), - .FULL_N(fpu_madd_fOperand_S0$FULL_N), - .EMPTY_N(fpu_madd_fOperand_S0$EMPTY_N)); - - // submodule fpu_madd_fProd_S2 - FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fProd_S2$D_IN), - .ENQ(fpu_madd_fProd_S2$ENQ), - .DEQ(fpu_madd_fProd_S2$DEQ), - .CLR(fpu_madd_fProd_S2$CLR), - .D_OUT(fpu_madd_fProd_S2$D_OUT), - .FULL_N(fpu_madd_fProd_S2$FULL_N), - .EMPTY_N(fpu_madd_fProd_S2$EMPTY_N)); - - // submodule fpu_madd_fProd_S3 - FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fProd_S3$D_IN), - .ENQ(fpu_madd_fProd_S3$ENQ), - .DEQ(fpu_madd_fProd_S3$DEQ), - .CLR(fpu_madd_fProd_S3$CLR), - .D_OUT(fpu_madd_fProd_S3$D_OUT), - .FULL_N(fpu_madd_fProd_S3$FULL_N), - .EMPTY_N(fpu_madd_fProd_S3$EMPTY_N)); - - // submodule fpu_madd_fResult_S9 - FIFOL1 #(.width(32'd69)) fpu_madd_fResult_S9(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fResult_S9$D_IN), - .ENQ(fpu_madd_fResult_S9$ENQ), - .DEQ(fpu_madd_fResult_S9$DEQ), - .CLR(fpu_madd_fResult_S9$CLR), - .D_OUT(fpu_madd_fResult_S9$D_OUT), - .FULL_N(fpu_madd_fResult_S9$FULL_N), - .EMPTY_N(fpu_madd_fResult_S9$EMPTY_N)); - - // submodule fpu_madd_fState_S1 - FIFOL1 #(.width(32'd258)) fpu_madd_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S1$D_IN), - .ENQ(fpu_madd_fState_S1$ENQ), - .DEQ(fpu_madd_fState_S1$DEQ), - .CLR(fpu_madd_fState_S1$CLR), - .D_OUT(fpu_madd_fState_S1$D_OUT), - .FULL_N(fpu_madd_fState_S1$FULL_N), - .EMPTY_N(fpu_madd_fState_S1$EMPTY_N)); - - // submodule fpu_madd_fState_S2 - FIFOL1 #(.width(32'd152)) fpu_madd_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S2$D_IN), - .ENQ(fpu_madd_fState_S2$ENQ), - .DEQ(fpu_madd_fState_S2$DEQ), - .CLR(fpu_madd_fState_S2$CLR), - .D_OUT(fpu_madd_fState_S2$D_OUT), - .FULL_N(fpu_madd_fState_S2$FULL_N), - .EMPTY_N(fpu_madd_fState_S2$EMPTY_N)); - - // submodule fpu_madd_fState_S3 - FIFOL1 #(.width(32'd152)) fpu_madd_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S3$D_IN), - .ENQ(fpu_madd_fState_S3$ENQ), - .DEQ(fpu_madd_fState_S3$DEQ), - .CLR(fpu_madd_fState_S3$CLR), - .D_OUT(fpu_madd_fState_S3$D_OUT), - .FULL_N(fpu_madd_fState_S3$FULL_N), - .EMPTY_N(fpu_madd_fState_S3$EMPTY_N)); - - // submodule fpu_madd_fState_S4 - FIFOL1 #(.width(32'd204)) fpu_madd_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S4$D_IN), - .ENQ(fpu_madd_fState_S4$ENQ), - .DEQ(fpu_madd_fState_S4$DEQ), - .CLR(fpu_madd_fState_S4$CLR), - .D_OUT(fpu_madd_fState_S4$D_OUT), - .FULL_N(fpu_madd_fState_S4$FULL_N), - .EMPTY_N(fpu_madd_fState_S4$EMPTY_N)); - - // submodule fpu_madd_fState_S5 - FIFOL1 #(.width(32'd216)) fpu_madd_fState_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S5$D_IN), - .ENQ(fpu_madd_fState_S5$ENQ), - .DEQ(fpu_madd_fState_S5$DEQ), - .CLR(fpu_madd_fState_S5$CLR), - .D_OUT(fpu_madd_fState_S5$D_OUT), - .FULL_N(fpu_madd_fState_S5$FULL_N), - .EMPTY_N(fpu_madd_fState_S5$EMPTY_N)); - - // submodule fpu_madd_fState_S6 - FIFOL1 #(.width(32'd203)) fpu_madd_fState_S6(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S6$D_IN), - .ENQ(fpu_madd_fState_S6$ENQ), - .DEQ(fpu_madd_fState_S6$DEQ), - .CLR(fpu_madd_fState_S6$CLR), - .D_OUT(fpu_madd_fState_S6$D_OUT), - .FULL_N(fpu_madd_fState_S6$FULL_N), - .EMPTY_N(fpu_madd_fState_S6$EMPTY_N)); - - // submodule fpu_madd_fState_S7 - FIFOL1 #(.width(32'd203)) fpu_madd_fState_S7(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S7$D_IN), - .ENQ(fpu_madd_fState_S7$ENQ), - .DEQ(fpu_madd_fState_S7$DEQ), - .CLR(fpu_madd_fState_S7$CLR), - .D_OUT(fpu_madd_fState_S7$D_OUT), - .FULL_N(fpu_madd_fState_S7$FULL_N), - .EMPTY_N(fpu_madd_fState_S7$EMPTY_N)); - - // submodule fpu_madd_fState_S8 - FIFOL1 #(.width(32'd141)) fpu_madd_fState_S8(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S8$D_IN), - .ENQ(fpu_madd_fState_S8$ENQ), - .DEQ(fpu_madd_fState_S8$DEQ), - .CLR(fpu_madd_fState_S8$CLR), - .D_OUT(fpu_madd_fState_S8$D_OUT), - .FULL_N(fpu_madd_fState_S8$FULL_N), - .EMPTY_N(fpu_madd_fState_S8$EMPTY_N)); - - // submodule fpu_sqr64_fOperand_S0 - FIFOL1 #(.width(32'd67)) fpu_sqr64_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fOperand_S0$D_IN), - .ENQ(fpu_sqr64_fOperand_S0$ENQ), - .DEQ(fpu_sqr64_fOperand_S0$DEQ), - .CLR(fpu_sqr64_fOperand_S0$CLR), - .D_OUT(fpu_sqr64_fOperand_S0$D_OUT), - .FULL_N(fpu_sqr64_fOperand_S0$FULL_N), - .EMPTY_N(fpu_sqr64_fOperand_S0$EMPTY_N)); - - // submodule fpu_sqr64_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_sqr64_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fResult_S5$D_IN), - .ENQ(fpu_sqr64_fResult_S5$ENQ), - .DEQ(fpu_sqr64_fResult_S5$DEQ), - .CLR(fpu_sqr64_fResult_S5$CLR), - .D_OUT(fpu_sqr64_fResult_S5$D_OUT), - .FULL_N(fpu_sqr64_fResult_S5$FULL_N), - .EMPTY_N(fpu_sqr64_fResult_S5$EMPTY_N)); - - // submodule fpu_sqr64_fState_S1 - FIFOL1 #(.width(32'd195)) fpu_sqr64_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S1$D_IN), - .ENQ(fpu_sqr64_fState_S1$ENQ), - .DEQ(fpu_sqr64_fState_S1$DEQ), - .CLR(fpu_sqr64_fState_S1$CLR), - .D_OUT(fpu_sqr64_fState_S1$D_OUT), - .FULL_N(fpu_sqr64_fState_S1$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S1$EMPTY_N)); - - // submodule fpu_sqr64_fState_S2 - FIFOL1 #(.width(32'd137)) fpu_sqr64_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S2$D_IN), - .ENQ(fpu_sqr64_fState_S2$ENQ), - .DEQ(fpu_sqr64_fState_S2$DEQ), - .CLR(fpu_sqr64_fState_S2$CLR), - .D_OUT(fpu_sqr64_fState_S2$D_OUT), - .FULL_N(fpu_sqr64_fState_S2$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S2$EMPTY_N)); - - // submodule fpu_sqr64_fState_S3 - FIFOL1 #(.width(32'd196)) fpu_sqr64_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S3$D_IN), - .ENQ(fpu_sqr64_fState_S3$ENQ), - .DEQ(fpu_sqr64_fState_S3$DEQ), - .CLR(fpu_sqr64_fState_S3$CLR), - .D_OUT(fpu_sqr64_fState_S3$D_OUT), - .FULL_N(fpu_sqr64_fState_S3$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S3$EMPTY_N)); - - // submodule fpu_sqr64_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_sqr64_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S4$D_IN), - .ENQ(fpu_sqr64_fState_S4$ENQ), - .DEQ(fpu_sqr64_fState_S4$DEQ), - .CLR(fpu_sqr64_fState_S4$CLR), - .D_OUT(fpu_sqr64_fState_S4$D_OUT), - .FULL_N(fpu_sqr64_fState_S4$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S4$EMPTY_N)); - - // submodule iFifo - FIFO2 #(.width(32'd202), .guarded(32'd1)) iFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(iFifo$D_IN), - .ENQ(iFifo$ENQ), - .DEQ(iFifo$DEQ), - .CLR(iFifo$CLR), - .D_OUT(iFifo$D_OUT), - .FULL_N(iFifo$FULL_N), - .EMPTY_N(iFifo$EMPTY_N)); - - // submodule isDoubleFifo - FIFO2 #(.width(32'd1), .guarded(32'd1)) isDoubleFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(isDoubleFifo$D_IN), - .ENQ(isDoubleFifo$ENQ), - .DEQ(isDoubleFifo$DEQ), - .CLR(isDoubleFifo$CLR), - .D_OUT(isDoubleFifo$D_OUT), - .FULL_N(isDoubleFifo$FULL_N), - .EMPTY_N(isDoubleFifo$EMPTY_N)); - - // submodule isNegateFifo - FIFO2 #(.width(32'd1), .guarded(32'd1)) isNegateFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(isNegateFifo$D_IN), - .ENQ(isNegateFifo$ENQ), - .DEQ(isNegateFifo$DEQ), - .CLR(isNegateFifo$CLR), - .D_OUT(isNegateFifo$D_OUT), - .FULL_N(isNegateFifo$FULL_N), - .EMPTY_N(isNegateFifo$EMPTY_N)); - - // submodule oFifo - FIFO2 #(.width(32'd70), .guarded(32'd1)) oFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(oFifo$D_IN), - .ENQ(oFifo$ENQ), - .DEQ(oFifo$DEQ), - .CLR(oFifo$CLR), - .D_OUT(oFifo$D_OUT), - .FULL_N(oFifo$FULL_N), - .EMPTY_N(oFifo$EMPTY_N)); - - // submodule resetReqsF - FIFO20 #(.guarded(32'd1)) resetReqsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetReqsF$ENQ), - .DEQ(resetReqsF$DEQ), - .CLR(resetReqsF$CLR), - .FULL_N(resetReqsF$FULL_N), - .EMPTY_N(resetReqsF$EMPTY_N)); - - // submodule resetRspsF - FIFO20 #(.guarded(32'd1)) resetRspsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetRspsF$ENQ), - .DEQ(resetRspsF$DEQ), - .CLR(resetRspsF$CLR), - .FULL_N(resetRspsF$FULL_N), - .EMPTY_N(resetRspsF$EMPTY_N)); - - // submodule rmdFifo - FIFO2 #(.width(32'd3), .guarded(32'd1)) rmdFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rmdFifo$D_IN), - .ENQ(rmdFifo$ENQ), - .DEQ(rmdFifo$DEQ), - .CLR(rmdFifo$CLR), - .D_OUT(rmdFifo$D_OUT), - .FULL_N(rmdFifo$FULL_N), - .EMPTY_N(rmdFifo$EMPTY_N)); - - // rule RL_getResDiv - assign CAN_FIRE_RL_getResDiv = fpu_div64_fResult_S5$EMPTY_N ; - assign WILL_FIRE_RL_getResDiv = fpu_div64_fResult_S5$EMPTY_N ; - - // rule RL_getResSqr - assign CAN_FIRE_RL_getResSqr = fpu_sqr64_fResult_S5$EMPTY_N ; - assign WILL_FIRE_RL_getResSqr = fpu_sqr64_fResult_S5$EMPTY_N ; - - // rule RL_getResMAdd - assign CAN_FIRE_RL_getResMAdd = fpu_madd_fResult_S9$EMPTY_N ; - assign WILL_FIRE_RL_getResMAdd = fpu_madd_fResult_S9$EMPTY_N ; - - // rule __me_check_22 - assign CAN_FIRE___me_check_22 = 1'b1 ; - assign WILL_FIRE___me_check_22 = 1'b1 ; - - // rule __me_check_23 - assign CAN_FIRE___me_check_23 = 1'b1 ; - assign WILL_FIRE___me_check_23 = 1'b1 ; - - // rule RL_passResult - assign CAN_FIRE_RL_passResult = - isDoubleFifo$EMPTY_N && isNegateFifo$EMPTY_N && - rmdFifo$EMPTY_N && - oFifo$FULL_N && - resWire$whas ; - assign WILL_FIRE_RL_passResult = CAN_FIRE_RL_passResult ; - - // rule RL_fpu_div64_s5_stage - assign CAN_FIRE_RL_fpu_div64_s5_stage = - fpu_div64_fState_S4$EMPTY_N && fpu_div64_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s5_stage = CAN_FIRE_RL_fpu_div64_s5_stage ; - - // rule RL_fpu_div64_s4_stage - assign CAN_FIRE_RL_fpu_div64_s4_stage = - fpu_div64_fState_S3$EMPTY_N && fpu_div64_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s4_stage = CAN_FIRE_RL_fpu_div64_s4_stage ; - - // rule RL_fpu_div64_s3_stage - assign CAN_FIRE_RL_fpu_div64_s3_stage = - fpu_div64_fState_S2$EMPTY_N && fpu_div64_fState_S3$FULL_N && - (fpu_div64_fState_S2$D_OUT[147] || crg_done) ; - assign WILL_FIRE_RL_fpu_div64_s3_stage = CAN_FIRE_RL_fpu_div64_s3_stage ; - - // rule RL_work - assign CAN_FIRE_RL_work = rg_busy ; - assign WILL_FIRE_RL_work = rg_busy ; - - // rule RL_fpu_div64_s2_stage - assign CAN_FIRE_RL_fpu_div64_s2_stage = - fpu_div64_fState_S1$EMPTY_N && fpu_div64_fState_S2$FULL_N && - (fpu_div64_fState_S1$D_OUT[318] || !rg_busy) ; - assign WILL_FIRE_RL_fpu_div64_s2_stage = - CAN_FIRE_RL_fpu_div64_s2_stage && !rg_busy ; - - // rule RL_fpu_div64_s1_stage - assign CAN_FIRE_RL_fpu_div64_s1_stage = - fpu_div64_fOperands_S0$EMPTY_N && fpu_div64_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s1_stage = CAN_FIRE_RL_fpu_div64_s1_stage ; - - // rule RL_fpu_sqr64_s5_stage - assign CAN_FIRE_RL_fpu_sqr64_s5_stage = - fpu_sqr64_fState_S4$EMPTY_N && fpu_sqr64_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s5_stage = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - - // rule RL_fpu_sqr64_s4_stage - assign CAN_FIRE_RL_fpu_sqr64_s4_stage = - fpu_sqr64_fState_S3$EMPTY_N && fpu_sqr64_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s4_stage = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - - // rule RL_fpu_sqr64_s3_stage - assign CAN_FIRE_RL_fpu_sqr64_s3_stage = - fpu_sqr64_fState_S2$EMPTY_N && fpu_sqr64_fState_S3$FULL_N && - (fpu_sqr64_fState_S2$D_OUT[136] || crg_done_1) ; - assign WILL_FIRE_RL_fpu_sqr64_s3_stage = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - - // rule RL_work_1 - assign CAN_FIRE_RL_work_1 = rg_busy_1 ; - assign WILL_FIRE_RL_work_1 = rg_busy_1 ; - - // rule RL_fpu_sqr64_s2_stage - assign CAN_FIRE_RL_fpu_sqr64_s2_stage = - fpu_sqr64_fState_S1$EMPTY_N && fpu_sqr64_fState_S2$FULL_N && - (fpu_sqr64_fState_S1$D_OUT[194] || !rg_busy_1) ; - assign WILL_FIRE_RL_fpu_sqr64_s2_stage = - CAN_FIRE_RL_fpu_sqr64_s2_stage && !rg_busy_1 ; - - // rule RL_fpu_sqr64_s1_stage - assign CAN_FIRE_RL_fpu_sqr64_s1_stage = - fpu_sqr64_fOperand_S0$EMPTY_N && fpu_sqr64_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s1_stage = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - - // rule RL_fpu_madd_s9_stage - assign CAN_FIRE_RL_fpu_madd_s9_stage = - fpu_madd_fState_S8$EMPTY_N && fpu_madd_fResult_S9$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s9_stage = CAN_FIRE_RL_fpu_madd_s9_stage ; - - // rule RL_fpu_madd_s8_stage - assign CAN_FIRE_RL_fpu_madd_s8_stage = - fpu_madd_fState_S7$EMPTY_N && fpu_madd_fState_S8$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s8_stage = CAN_FIRE_RL_fpu_madd_s8_stage ; - - // rule RL_fpu_madd_s7_stage - assign CAN_FIRE_RL_fpu_madd_s7_stage = - fpu_madd_fState_S6$EMPTY_N && fpu_madd_fState_S7$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s7_stage = CAN_FIRE_RL_fpu_madd_s7_stage ; - - // rule RL_fpu_madd_s6_stage - assign CAN_FIRE_RL_fpu_madd_s6_stage = - fpu_madd_fState_S5$EMPTY_N && fpu_madd_fState_S6$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s6_stage = CAN_FIRE_RL_fpu_madd_s6_stage ; - - // rule RL_fpu_madd_s5_stage - assign CAN_FIRE_RL_fpu_madd_s5_stage = - fpu_madd_fState_S4$EMPTY_N && fpu_madd_fState_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s5_stage = CAN_FIRE_RL_fpu_madd_s5_stage ; - - // rule RL_fpu_madd_s4_stage - assign CAN_FIRE_RL_fpu_madd_s4_stage = - fpu_madd_fState_S3$EMPTY_N && fpu_madd_fProd_S3$EMPTY_N && - fpu_madd_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s4_stage = CAN_FIRE_RL_fpu_madd_s4_stage ; - - // rule RL_fpu_madd_s3_stage - assign CAN_FIRE_RL_fpu_madd_s3_stage = - fpu_madd_fState_S2$EMPTY_N && fpu_madd_fProd_S2$EMPTY_N && - fpu_madd_fProd_S3$FULL_N && - fpu_madd_fState_S3$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s3_stage = CAN_FIRE_RL_fpu_madd_s3_stage ; - - // rule RL_fpu_madd_s2_stage - assign CAN_FIRE_RL_fpu_madd_s2_stage = - fpu_madd_fState_S1$EMPTY_N && fpu_madd_fProd_S2$FULL_N && - fpu_madd_fState_S2$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s2_stage = CAN_FIRE_RL_fpu_madd_s2_stage ; - - // rule RL_fpu_madd_s1_stage - assign CAN_FIRE_RL_fpu_madd_s1_stage = - fpu_madd_fOperand_S0$EMPTY_N && fpu_madd_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s1_stage = CAN_FIRE_RL_fpu_madd_s1_stage ; - - // rule RL_start_op - assign CAN_FIRE_RL_start_op = - iFifo$EMPTY_N && isDoubleFifo$FULL_N && isNegateFifo$FULL_N && - rmdFifo$FULL_N && - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 ; - assign WILL_FIRE_RL_start_op = CAN_FIRE_RL_start_op ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = resetReqsF$EMPTY_N && resetRspsF$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_crg_done$port1__write_1__SEL_1 = rg_busy && rg_index == 6'd28 ; - assign MUX_crg_done$port1__write_1__SEL_2 = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - assign MUX_crg_done_1$port1__write_1__SEL_1 = - rg_busy_1 && rg_index_1 == 6'd29 ; - assign MUX_crg_done_1$port1__write_1__SEL_2 = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - assign MUX_rg_b$write_1__VAL_1 = - fpu_sqr64_fState_S1$D_OUT[57] ? - 116'h40000000000000000000000000000 : - b___1__h77160 ; - assign MUX_rg_b$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___fst__h1476 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign MUX_rg_d$write_1__VAL_1 = - { 1'd0, fpu_div64_fState_S1$D_OUT[67:11] } ; - assign MUX_rg_index$write_1__VAL_2 = rg_index + 6'd1 ; - assign MUX_rg_index_1$write_1__VAL_2 = rg_index_1 + 6'd1 ; - assign MUX_rg_q$write_1__VAL_2 = - rg_index_PLUS_1_ULE_57___d6 ? - { IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14[56:0], - !IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] } : - IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 ; - assign MUX_rg_r$write_1__VAL_1 = - { 2'd0, fpu_div64_fState_S1$D_OUT[181:68] } ; - assign MUX_rg_r$write_1__VAL_2 = - rg_index_PLUS_1_ULE_57___d6 ? - (IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] ? - { IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0], - 1'd0 } + - b__h32583 : - { IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0], - 1'd0 } - - b__h32583) : - IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 ; - assign MUX_rg_r_1$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___snd_snd_snd__h1481 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 ; - assign MUX_rg_res$write_1__VAL_2 = - { rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44 || - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0 : - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44, - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 } ; - assign MUX_rg_s$write_1__VAL_1 = - { fpu_sqr64_fState_S1$D_OUT[57:0], 58'd0 } ; - assign MUX_rg_s$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___snd_fst__h1478 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 ; - - // inlined wires - always@(fpu_div64_fResult_S5$EMPTY_N or - fpu_div64_fResult_S5$D_OUT or - fpu_sqr64_fResult_S5$EMPTY_N or - fpu_sqr64_fResult_S5$D_OUT or - fpu_madd_fResult_S9$EMPTY_N or fpu_madd_fResult_S9$D_OUT) - begin - case (1'b1) // synopsys parallel_case - fpu_div64_fResult_S5$EMPTY_N: resWire$wget = fpu_div64_fResult_S5$D_OUT; - fpu_sqr64_fResult_S5$EMPTY_N: resWire$wget = fpu_sqr64_fResult_S5$D_OUT; - fpu_madd_fResult_S9$EMPTY_N: resWire$wget = fpu_madd_fResult_S9$D_OUT; - default: resWire$wget = 69'h0AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign resWire$whas = - fpu_div64_fResult_S5$EMPTY_N || fpu_sqr64_fResult_S5$EMPTY_N || - fpu_madd_fResult_S9$EMPTY_N ; - assign crg_done$EN_port0__write = - WILL_FIRE_RL_fpu_div64_s3_stage && - !fpu_div64_fState_S2$D_OUT[147] ; - assign crg_done$port1__read = !crg_done$EN_port0__write && crg_done ; - assign crg_done$EN_port1__write = - rg_busy && rg_index == 6'd28 || - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - assign crg_done$port2__read = - crg_done$EN_port1__write ? - MUX_crg_done$port1__write_1__SEL_1 : - crg_done$port1__read ; - assign crg_done_1$EN_port0__write = - WILL_FIRE_RL_fpu_sqr64_s3_stage && - !fpu_sqr64_fState_S2$D_OUT[136] ; - assign crg_done_1$port1__read = !crg_done_1$EN_port0__write && crg_done_1 ; - assign crg_done_1$EN_port1__write = - rg_busy_1 && rg_index_1 == 6'd29 || - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - assign crg_done_1$port2__read = - crg_done_1$EN_port1__write ? - MUX_crg_done_1$port1__write_1__SEL_1 : - crg_done_1$port1__read ; - - // register crg_done - assign crg_done$D_IN = crg_done$port2__read ; - assign crg_done$EN = 1'b1 ; - - // register crg_done_1 - assign crg_done_1$D_IN = crg_done_1$port2__read ; - assign crg_done_1$EN = 1'b1 ; - - // register rg_b - assign rg_b$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - MUX_rg_b$write_1__VAL_1 : - MUX_rg_b$write_1__VAL_2 ; - assign rg_b$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_busy - assign rg_busy$D_IN = !MUX_crg_done$port1__write_1__SEL_1 ; - assign rg_busy$EN = - rg_busy && rg_index == 6'd28 || - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - - // register rg_busy_1 - assign rg_busy_1$D_IN = !MUX_crg_done_1$port1__write_1__SEL_1 ; - assign rg_busy_1$EN = - rg_busy_1 && rg_index_1 == 6'd29 || - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - - // register rg_d - assign rg_d$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - MUX_rg_d$write_1__VAL_1 : - rg_d ; - assign rg_d$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_index - assign rg_index$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - 6'd0 : - MUX_rg_index$write_1__VAL_2 ; - assign rg_index$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_index_1 - assign rg_index_1$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 6'd0 : - MUX_rg_index_1$write_1__VAL_2 ; - assign rg_index_1$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_q - assign rg_q$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - 58'd0 : - MUX_rg_q$write_1__VAL_2 ; - assign rg_q$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_r - assign rg_r$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - MUX_rg_r$write_1__VAL_1 : - MUX_rg_r$write_1__VAL_2 ; - assign rg_r$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_r_1 - assign rg_r_1$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 116'd0 : - MUX_rg_r_1$write_1__VAL_2 ; - assign rg_r_1$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_res - assign rg_res$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - MUX_rg_res$write_1__VAL_2 ; - assign rg_res$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_s - assign rg_s$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - MUX_rg_s$write_1__VAL_1 : - MUX_rg_s$write_1__VAL_2 ; - assign rg_s$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // submodule fpu_div64_fOperands_S0 - assign fpu_div64_fOperands_S0$D_IN = - { IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330, - iFifo$D_OUT[6:4] } ; - assign fpu_div64_fOperands_S0$ENQ = - WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd3 ; - assign fpu_div64_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_div64_s1_stage ; - assign fpu_div64_fOperands_S0$CLR = 1'b0 ; - - // submodule fpu_div64_fResult_S5 - assign fpu_div64_fResult_S5$D_IN = - fpu_div64_fState_S4$D_OUT[138] ? - fpu_div64_fState_S4$D_OUT[137:69] : - { (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[65:2] : - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173, - fpu_div64_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h43556 == 11'd2047 && - _theResult___fst_sfd__h43557 == 52'd0, - 1'd0, - fpu_div64_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_div64_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_div64_fResult_S5$ENQ = CAN_FIRE_RL_fpu_div64_s5_stage ; - assign fpu_div64_fResult_S5$DEQ = fpu_div64_fResult_S5$EMPTY_N ; - assign fpu_div64_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S1 - assign fpu_div64_fState_S1$D_IN = - { fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363, - (fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118]) ? - { fpu_div64_fOperands_S0$D_OUT[130:119], sfd__h18934 } : - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455, - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0), - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - !IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488, - fpu_div64_fOperands_S0$D_OUT[2:0], - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405, - _theResult___snd_fst_exp__h31361, - _theResult___snd_fst_sfd__h31362, - x__h31426, - x__h31487, - x__h31541 } ; - assign fpu_div64_fState_S1$ENQ = CAN_FIRE_RL_fpu_div64_s1_stage ; - assign fpu_div64_fState_S1$DEQ = WILL_FIRE_RL_fpu_div64_s2_stage ; - assign fpu_div64_fState_S1$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S2 - assign fpu_div64_fState_S2$D_IN = - { fpu_div64_fState_S1$D_OUT[318:182], - fpu_div64_fState_S1$D_OUT[10:0] } ; - assign fpu_div64_fState_S2$ENQ = WILL_FIRE_RL_fpu_div64_s2_stage ; - assign fpu_div64_fState_S2$DEQ = CAN_FIRE_RL_fpu_div64_s3_stage ; - assign fpu_div64_fState_S2$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S3 - assign fpu_div64_fState_S3$D_IN = - { fpu_div64_fState_S2$D_OUT[147:11], x__h33052 } ; - assign fpu_div64_fState_S3$ENQ = CAN_FIRE_RL_fpu_div64_s3_stage ; - assign fpu_div64_fState_S3$DEQ = CAN_FIRE_RL_fpu_div64_s4_stage ; - assign fpu_div64_fState_S3$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S4 - assign fpu_div64_fState_S4$D_IN = - { (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[194] : - fpu_div64_fState_S3$D_OUT[194], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - fpu_div64_fState_S3$D_OUT[193:130] : - { CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174, - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 }) : - fpu_div64_fState_S3$D_OUT[193:130], - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926, - fpu_div64_fState_S3$D_OUT[124:122], - fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936, - x__h42705 } ; - assign fpu_div64_fState_S4$ENQ = CAN_FIRE_RL_fpu_div64_s4_stage ; - assign fpu_div64_fState_S4$DEQ = CAN_FIRE_RL_fpu_div64_s5_stage ; - assign fpu_div64_fState_S4$CLR = 1'b0 ; - - // submodule fpu_madd_fOperand_S0 - assign fpu_madd_fOperand_S0$D_IN = - { iFifo$D_OUT[3:0] != 4'd2, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623, - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176, - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177, - iFifo$D_OUT[6:4] } ; - assign fpu_madd_fOperand_S0$ENQ = - WILL_FIRE_RL_start_op && - (iFifo$D_OUT[3:0] == 4'd0 || iFifo$D_OUT[3:0] == 4'd1 || - iFifo$D_OUT[3:0] == 4'd2 || - iFifo$D_OUT[3:0] == 4'd5 || - iFifo$D_OUT[3:0] == 4'd6 || - iFifo$D_OUT[3:0] == 4'd7 || - iFifo$D_OUT[3:0] == 4'd8) ; - assign fpu_madd_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_madd_s1_stage ; - assign fpu_madd_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_madd_fProd_S2 - assign fpu_madd_fProd_S2$D_IN = - fpu_madd_fState_S1$D_OUT[105:53] * - fpu_madd_fState_S1$D_OUT[52:0] ; - assign fpu_madd_fProd_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fProd_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fProd_S2$CLR = 1'b0 ; - - // submodule fpu_madd_fProd_S3 - assign fpu_madd_fProd_S3$D_IN = fpu_madd_fProd_S2$D_OUT ; - assign fpu_madd_fProd_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fProd_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fProd_S3$CLR = 1'b0 ; - - // submodule fpu_madd_fResult_S9 - assign fpu_madd_fResult_S9$D_IN = - fpu_madd_fState_S8$D_OUT[140] ? - fpu_madd_fState_S8$D_OUT[139:71] : - IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 ; - assign fpu_madd_fResult_S9$ENQ = CAN_FIRE_RL_fpu_madd_s9_stage ; - assign fpu_madd_fResult_S9$DEQ = fpu_madd_fResult_S9$EMPTY_N ; - assign fpu_madd_fResult_S9$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S1 - assign fpu_madd_fState_S1$D_IN = - { x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54] || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947, - 4'd0, - fpu_madd_fOperand_S0$D_OUT[2:0], - fpu_madd_fOperand_S0$D_OUT[195], - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911, - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 } ; - assign fpu_madd_fState_S1$ENQ = CAN_FIRE_RL_fpu_madd_s1_stage ; - assign fpu_madd_fState_S1$DEQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fState_S1$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S2 - assign fpu_madd_fState_S2$D_IN = fpu_madd_fState_S1$D_OUT[257:106] ; - assign fpu_madd_fState_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fState_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fState_S2$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S3 - assign fpu_madd_fState_S3$D_IN = fpu_madd_fState_S2$D_OUT ; - assign fpu_madd_fState_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fState_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fState_S3$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S4 - assign fpu_madd_fState_S4$D_IN = - { fpu_madd_fState_S3$D_OUT[151:87], - IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525, - fpu_madd_fState_S3$D_OUT[81:14], - !fpu_madd_fState_S3$D_OUT[151] && fpu_madd_fState_S3$D_OUT[13], - fpu_madd_fState_S3$D_OUT[151] ? - 63'd0 : - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536, - x__h131406 } ; - assign fpu_madd_fState_S4$ENQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fState_S4$DEQ = CAN_FIRE_RL_fpu_madd_s5_stage ; - assign fpu_madd_fState_S4$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S5 - assign fpu_madd_fState_S5$D_IN = - { fpu_madd_fState_S4$D_OUT[203:130], - fpu_madd_fState_S4$D_OUT[129] != fpu_madd_fState_S4$D_OUT[65], - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - fpu_madd_fState_S4$D_OUT[65] : - fpu_madd_fState_S4$D_OUT[129], - IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 } ; - assign fpu_madd_fState_S5$ENQ = CAN_FIRE_RL_fpu_madd_s5_stage ; - assign fpu_madd_fState_S5$DEQ = CAN_FIRE_RL_fpu_madd_s6_stage ; - assign fpu_madd_fState_S5$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S6 - assign fpu_madd_fState_S6$D_IN = - { fpu_madd_fState_S5$D_OUT[215:127], - fpu_madd_fState_S5$D_OUT[113:57], - x__h132359 } ; - assign fpu_madd_fState_S6$ENQ = CAN_FIRE_RL_fpu_madd_s6_stage ; - assign fpu_madd_fState_S6$DEQ = CAN_FIRE_RL_fpu_madd_s7_stage ; - assign fpu_madd_fState_S6$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S7 - assign fpu_madd_fState_S7$D_IN = - { fpu_madd_fState_S6$D_OUT[202:114], x__h132871, x__h132880 } ; - assign fpu_madd_fState_S7$ENQ = CAN_FIRE_RL_fpu_madd_s7_stage ; - assign fpu_madd_fState_S7$DEQ = CAN_FIRE_RL_fpu_madd_s8_stage ; - assign fpu_madd_fState_S7$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S8 - assign fpu_madd_fState_S8$D_IN = - { fpu_madd_fState_S7$D_OUT[202:138], - fpu_madd_fState_S7$D_OUT[202] ? - fpu_madd_fState_S7$D_OUT[137:133] : - fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942, - fpu_madd_fState_S7$D_OUT[132:129], - !fpu_madd_fState_S7$D_OUT[202] && - fpu_madd_fState_S7$D_OUT[127], - fpu_madd_fState_S7$D_OUT[202] ? - 63'd0 : - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952, - x__h141760, - fpu_madd_fState_S7$D_OUT[128] } ; - assign fpu_madd_fState_S8$ENQ = CAN_FIRE_RL_fpu_madd_s8_stage ; - assign fpu_madd_fState_S8$DEQ = CAN_FIRE_RL_fpu_madd_s9_stage ; - assign fpu_madd_fState_S8$CLR = 1'b0 ; - - // submodule fpu_sqr64_fOperand_S0 - assign fpu_sqr64_fOperand_S0$D_IN = - { IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - iFifo$D_OUT[6:4] } ; - assign fpu_sqr64_fOperand_S0$ENQ = - WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd4 ; - assign fpu_sqr64_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - assign fpu_sqr64_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_sqr64_fResult_S5 - assign fpu_sqr64_fResult_S5$D_IN = - fpu_sqr64_fState_S4$D_OUT[138] ? - fpu_sqr64_fState_S4$D_OUT[137:69] : - { (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[65:2] : - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183, - fpu_sqr64_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h95990 == 11'd2047 && - _theResult___fst_sfd__h95991 == 52'd0, - 1'd0, - fpu_sqr64_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_sqr64_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_sqr64_fResult_S5$ENQ = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - assign fpu_sqr64_fResult_S5$DEQ = fpu_sqr64_fResult_S5$EMPTY_N ; - assign fpu_sqr64_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S1 - assign fpu_sqr64_fState_S1$D_IN = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_sqr64_fOperand_S0$D_OUT[54]) ? - { 1'd1, - fpu_sqr64_fOperand_S0$D_OUT[66:55], - sfd__h45004, - 130'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212 ; - assign fpu_sqr64_fState_S1$ENQ = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - assign fpu_sqr64_fState_S1$DEQ = WILL_FIRE_RL_fpu_sqr64_s2_stage ; - assign fpu_sqr64_fState_S1$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S2 - assign fpu_sqr64_fState_S2$D_IN = fpu_sqr64_fState_S1$D_OUT[194:58] ; - assign fpu_sqr64_fState_S2$ENQ = WILL_FIRE_RL_fpu_sqr64_s2_stage ; - assign fpu_sqr64_fState_S2$DEQ = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - assign fpu_sqr64_fState_S2$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S3 - assign fpu_sqr64_fState_S3$D_IN = { fpu_sqr64_fState_S2$D_OUT, x__h86149 } ; - assign fpu_sqr64_fState_S3$ENQ = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - assign fpu_sqr64_fState_S3$DEQ = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - assign fpu_sqr64_fState_S3$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S4 - assign fpu_sqr64_fState_S4$D_IN = - { fpu_sqr64_fState_S3$D_OUT[195:131], - fpu_sqr64_fState_S3$D_OUT[195] && - fpu_sqr64_fState_S3$D_OUT[130], - fpu_sqr64_fState_S3$D_OUT[195] && - fpu_sqr64_fState_S3$D_OUT[129], - IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671, - fpu_sqr64_fState_S3$D_OUT[125:122], - fpu_sqr64_fState_S3$D_OUT[195] ? - fpu_sqr64_fState_S3$D_OUT[121:59] : - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678, - x__h95138 } ; - assign fpu_sqr64_fState_S4$ENQ = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - assign fpu_sqr64_fState_S4$DEQ = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - assign fpu_sqr64_fState_S4$CLR = 1'b0 ; - - // submodule iFifo - assign iFifo$D_IN = server_core_request_put ; - assign iFifo$ENQ = EN_server_core_request_put ; - assign iFifo$DEQ = CAN_FIRE_RL_start_op ; - assign iFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule isDoubleFifo - assign isDoubleFifo$D_IN = !iFifo$D_OUT[201] ; - assign isDoubleFifo$ENQ = CAN_FIRE_RL_start_op ; - assign isDoubleFifo$DEQ = CAN_FIRE_RL_passResult ; - assign isDoubleFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule isNegateFifo - assign isNegateFifo$D_IN = - iFifo$D_OUT[3:0] == 4'd7 || iFifo$D_OUT[3:0] == 4'd8 ; - assign isNegateFifo$ENQ = CAN_FIRE_RL_start_op ; - assign isNegateFifo$DEQ = CAN_FIRE_RL_passResult ; - assign isNegateFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule oFifo - assign oFifo$D_IN = - { !isDoubleFifo$D_OUT, - IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657, - isDoubleFifo$D_OUT ? - resWire$wget[4:0] : - resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 } ; - assign oFifo$ENQ = CAN_FIRE_RL_passResult ; - assign oFifo$DEQ = EN_server_core_response_get ; - assign oFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule resetReqsF - assign resetReqsF$ENQ = EN_server_reset_request_put ; - assign resetReqsF$DEQ = CAN_FIRE_RL_rl_reset ; - assign resetReqsF$CLR = 1'b0 ; - - // submodule resetRspsF - assign resetRspsF$ENQ = CAN_FIRE_RL_rl_reset ; - assign resetRspsF$DEQ = EN_server_reset_response_get ; - assign resetRspsF$CLR = 1'b0 ; - - // submodule rmdFifo - assign rmdFifo$D_IN = iFifo$D_OUT[6:4] ; - assign rmdFifo$ENQ = CAN_FIRE_RL_start_op ; - assign rmdFifo$DEQ = CAN_FIRE_RL_passResult ; - assign rmdFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 ? - _theResult___snd__h277749 : - _theResult____h269577 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 ? - _theResult___snd__h172915 : - _theResult____h164614 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 ? - _theResult___snd__h250492 : - _theResult____h242191 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 ? - _theResult___snd__h211553 : - _theResult____h203252 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 ? - _theResult___snd__h295515 : - _theResult____h287214 ; - assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24 = - _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 ? - _theResult___snd__h131023 : - _theResult___snd__h131018 ; - assign IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12 = - _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883 ? - _theResult___snd__h42409 : - _theResult___snd__h42404 ; - assign IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29 = - _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 ? - _theResult___snd__h141449 : - _theResult___snd__h141444 ; - assign IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19 = - _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633 ? - _theResult___snd__h94826 : - _theResult___snd__h94821 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100 = - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 ? - _theResult___snd__h201963 : - _theResult___snd__h220275 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93 = - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 ? - _theResult___snd__h201963 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33 = - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 ? - _theResult___snd__h163325 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40 = - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 ? - _theResult___snd__h163325 : - _theResult___snd__h181637 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60 = - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 ? - _theResult___snd__h240902 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67 = - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 ? - _theResult___snd__h240902 : - _theResult___snd__h259214 ; - assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135 = - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 ? - _theResult___snd__h286331 : - 57'd0 ; - assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142 = - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 ? - _theResult___snd__h286331 : - _theResult___snd__h304121 ; - assign IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h43566, sfd__h42982[52:1] }) : - { IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977, - sfd__h42982[51:0] } ; - assign IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h142626, sfd__h142040[52:1] }) : - { IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986, - sfd__h142040[51:0] } ; - assign IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h96000, sfd__h95416[52:1] }) : - { IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721, - sfd__h95416[51:0] } ; - assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - ((_theResult___fst_exp__h277686 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823) : - ((_theResult___fst_exp__h286342 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023) ; - assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - ((_theResult___fst_exp__h277686 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388) : - ((_theResult___fst_exp__h286342 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[168] : - ((_theResult___fst_exp__h163336 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[38] : - ((_theResult___fst_exp__h240913 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 && - iFifo$D_OUT[6:4] != 3'd2 && - iFifo$D_OUT[6:4] != 3'd3 && - iFifo$D_OUT[6:4] != 3'd4 || - !iFifo$D_OUT[38] : - ((_theResult___fst_exp__h240913 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[103] : - ((_theResult___fst_exp__h201974 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 && - iFifo$D_OUT[6:4] != 3'd2 && - iFifo$D_OUT[6:4] != 3'd3 && - iFifo$D_OUT[6:4] != 3'd4 || - !iFifo$D_OUT[103] : - ((_theResult___fst_exp__h201974 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121) ; - assign IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 = - (_theResult____h269577[56] ? - 6'd0 : - (_theResult____h269577[55] ? - 6'd1 : - (_theResult____h269577[54] ? - 6'd2 : - (_theResult____h269577[53] ? - 6'd3 : - (_theResult____h269577[52] ? - 6'd4 : - (_theResult____h269577[51] ? - 6'd5 : - (_theResult____h269577[50] ? - 6'd6 : - (_theResult____h269577[49] ? - 6'd7 : - (_theResult____h269577[48] ? - 6'd8 : - (_theResult____h269577[47] ? - 6'd9 : - (_theResult____h269577[46] ? - 6'd10 : - (_theResult____h269577[45] ? - 6'd11 : - (_theResult____h269577[44] ? - 6'd12 : - (_theResult____h269577[43] ? - 6'd13 : - (_theResult____h269577[42] ? - 6'd14 : - (_theResult____h269577[41] ? - 6'd15 : - (_theResult____h269577[40] ? - 6'd16 : - (_theResult____h269577[39] ? - 6'd17 : - (_theResult____h269577[38] ? - 6'd18 : - (_theResult____h269577[37] ? - 6'd19 : - (_theResult____h269577[36] ? - 6'd20 : - (_theResult____h269577[35] ? - 6'd21 : - (_theResult____h269577[34] ? - 6'd22 : - (_theResult____h269577[33] ? - 6'd23 : - (_theResult____h269577[32] ? - 6'd24 : - (_theResult____h269577[31] ? - 6'd25 : - (_theResult____h269577[30] ? - 6'd26 : - (_theResult____h269577[29] ? - 6'd27 : - (_theResult____h269577[28] ? - 6'd28 : - (_theResult____h269577[27] ? - 6'd29 : - (_theResult____h269577[26] ? - 6'd30 : - (_theResult____h269577[25] ? - 6'd31 : - (_theResult____h269577[24] ? - 6'd32 : - (_theResult____h269577[23] ? - 6'd33 : - (_theResult____h269577[22] ? - 6'd34 : - (_theResult____h269577[21] ? - 6'd35 : - (_theResult____h269577[20] ? - 6'd36 : - (_theResult____h269577[19] ? - 6'd37 : - (_theResult____h269577[18] ? - 6'd38 : - (_theResult____h269577[17] ? - 6'd39 : - (_theResult____h269577[16] ? - 6'd40 : - (_theResult____h269577[15] ? - 6'd41 : - (_theResult____h269577[14] ? - 6'd42 : - (_theResult____h269577[13] ? - 6'd43 : - (_theResult____h269577[12] ? - 6'd44 : - (_theResult____h269577[11] ? - 6'd45 : - (_theResult____h269577[10] ? - 6'd46 : - (_theResult____h269577[9] ? - 6'd47 : - (_theResult____h269577[8] ? - 6'd48 : - (_theResult____h269577[7] ? - 6'd49 : - (_theResult____h269577[6] ? - 6'd50 : - (_theResult____h269577[5] ? - 6'd51 : - (_theResult____h269577[4] ? - 6'd52 : - (_theResult____h269577[3] ? - 6'd53 : - (_theResult____h269577[2] ? - 6'd54 : - (_theResult____h269577[1] ? - 6'd55 : - (_theResult____h269577[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 = - (_theResult____h203252[56] ? - 6'd0 : - (_theResult____h203252[55] ? - 6'd1 : - (_theResult____h203252[54] ? - 6'd2 : - (_theResult____h203252[53] ? - 6'd3 : - (_theResult____h203252[52] ? - 6'd4 : - (_theResult____h203252[51] ? - 6'd5 : - (_theResult____h203252[50] ? - 6'd6 : - (_theResult____h203252[49] ? - 6'd7 : - (_theResult____h203252[48] ? - 6'd8 : - (_theResult____h203252[47] ? - 6'd9 : - (_theResult____h203252[46] ? - 6'd10 : - (_theResult____h203252[45] ? - 6'd11 : - (_theResult____h203252[44] ? - 6'd12 : - (_theResult____h203252[43] ? - 6'd13 : - (_theResult____h203252[42] ? - 6'd14 : - (_theResult____h203252[41] ? - 6'd15 : - (_theResult____h203252[40] ? - 6'd16 : - (_theResult____h203252[39] ? - 6'd17 : - (_theResult____h203252[38] ? - 6'd18 : - (_theResult____h203252[37] ? - 6'd19 : - (_theResult____h203252[36] ? - 6'd20 : - (_theResult____h203252[35] ? - 6'd21 : - (_theResult____h203252[34] ? - 6'd22 : - (_theResult____h203252[33] ? - 6'd23 : - (_theResult____h203252[32] ? - 6'd24 : - (_theResult____h203252[31] ? - 6'd25 : - (_theResult____h203252[30] ? - 6'd26 : - (_theResult____h203252[29] ? - 6'd27 : - (_theResult____h203252[28] ? - 6'd28 : - (_theResult____h203252[27] ? - 6'd29 : - (_theResult____h203252[26] ? - 6'd30 : - (_theResult____h203252[25] ? - 6'd31 : - (_theResult____h203252[24] ? - 6'd32 : - (_theResult____h203252[23] ? - 6'd33 : - (_theResult____h203252[22] ? - 6'd34 : - (_theResult____h203252[21] ? - 6'd35 : - (_theResult____h203252[20] ? - 6'd36 : - (_theResult____h203252[19] ? - 6'd37 : - (_theResult____h203252[18] ? - 6'd38 : - (_theResult____h203252[17] ? - 6'd39 : - (_theResult____h203252[16] ? - 6'd40 : - (_theResult____h203252[15] ? - 6'd41 : - (_theResult____h203252[14] ? - 6'd42 : - (_theResult____h203252[13] ? - 6'd43 : - (_theResult____h203252[12] ? - 6'd44 : - (_theResult____h203252[11] ? - 6'd45 : - (_theResult____h203252[10] ? - 6'd46 : - (_theResult____h203252[9] ? - 6'd47 : - (_theResult____h203252[8] ? - 6'd48 : - (_theResult____h203252[7] ? - 6'd49 : - (_theResult____h203252[6] ? - 6'd50 : - (_theResult____h203252[5] ? - 6'd51 : - (_theResult____h203252[4] ? - 6'd52 : - (_theResult____h203252[3] ? - 6'd53 : - (_theResult____h203252[2] ? - 6'd54 : - (_theResult____h203252[1] ? - 6'd55 : - (_theResult____h203252[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 = - (_theResult____h164614[56] ? - 6'd0 : - (_theResult____h164614[55] ? - 6'd1 : - (_theResult____h164614[54] ? - 6'd2 : - (_theResult____h164614[53] ? - 6'd3 : - (_theResult____h164614[52] ? - 6'd4 : - (_theResult____h164614[51] ? - 6'd5 : - (_theResult____h164614[50] ? - 6'd6 : - (_theResult____h164614[49] ? - 6'd7 : - (_theResult____h164614[48] ? - 6'd8 : - (_theResult____h164614[47] ? - 6'd9 : - (_theResult____h164614[46] ? - 6'd10 : - (_theResult____h164614[45] ? - 6'd11 : - (_theResult____h164614[44] ? - 6'd12 : - (_theResult____h164614[43] ? - 6'd13 : - (_theResult____h164614[42] ? - 6'd14 : - (_theResult____h164614[41] ? - 6'd15 : - (_theResult____h164614[40] ? - 6'd16 : - (_theResult____h164614[39] ? - 6'd17 : - (_theResult____h164614[38] ? - 6'd18 : - (_theResult____h164614[37] ? - 6'd19 : - (_theResult____h164614[36] ? - 6'd20 : - (_theResult____h164614[35] ? - 6'd21 : - (_theResult____h164614[34] ? - 6'd22 : - (_theResult____h164614[33] ? - 6'd23 : - (_theResult____h164614[32] ? - 6'd24 : - (_theResult____h164614[31] ? - 6'd25 : - (_theResult____h164614[30] ? - 6'd26 : - (_theResult____h164614[29] ? - 6'd27 : - (_theResult____h164614[28] ? - 6'd28 : - (_theResult____h164614[27] ? - 6'd29 : - (_theResult____h164614[26] ? - 6'd30 : - (_theResult____h164614[25] ? - 6'd31 : - (_theResult____h164614[24] ? - 6'd32 : - (_theResult____h164614[23] ? - 6'd33 : - (_theResult____h164614[22] ? - 6'd34 : - (_theResult____h164614[21] ? - 6'd35 : - (_theResult____h164614[20] ? - 6'd36 : - (_theResult____h164614[19] ? - 6'd37 : - (_theResult____h164614[18] ? - 6'd38 : - (_theResult____h164614[17] ? - 6'd39 : - (_theResult____h164614[16] ? - 6'd40 : - (_theResult____h164614[15] ? - 6'd41 : - (_theResult____h164614[14] ? - 6'd42 : - (_theResult____h164614[13] ? - 6'd43 : - (_theResult____h164614[12] ? - 6'd44 : - (_theResult____h164614[11] ? - 6'd45 : - (_theResult____h164614[10] ? - 6'd46 : - (_theResult____h164614[9] ? - 6'd47 : - (_theResult____h164614[8] ? - 6'd48 : - (_theResult____h164614[7] ? - 6'd49 : - (_theResult____h164614[6] ? - 6'd50 : - (_theResult____h164614[5] ? - 6'd51 : - (_theResult____h164614[4] ? - 6'd52 : - (_theResult____h164614[3] ? - 6'd53 : - (_theResult____h164614[2] ? - 6'd54 : - (_theResult____h164614[1] ? - 6'd55 : - (_theResult____h164614[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 = - (_theResult____h242191[56] ? - 6'd0 : - (_theResult____h242191[55] ? - 6'd1 : - (_theResult____h242191[54] ? - 6'd2 : - (_theResult____h242191[53] ? - 6'd3 : - (_theResult____h242191[52] ? - 6'd4 : - (_theResult____h242191[51] ? - 6'd5 : - (_theResult____h242191[50] ? - 6'd6 : - (_theResult____h242191[49] ? - 6'd7 : - (_theResult____h242191[48] ? - 6'd8 : - (_theResult____h242191[47] ? - 6'd9 : - (_theResult____h242191[46] ? - 6'd10 : - (_theResult____h242191[45] ? - 6'd11 : - (_theResult____h242191[44] ? - 6'd12 : - (_theResult____h242191[43] ? - 6'd13 : - (_theResult____h242191[42] ? - 6'd14 : - (_theResult____h242191[41] ? - 6'd15 : - (_theResult____h242191[40] ? - 6'd16 : - (_theResult____h242191[39] ? - 6'd17 : - (_theResult____h242191[38] ? - 6'd18 : - (_theResult____h242191[37] ? - 6'd19 : - (_theResult____h242191[36] ? - 6'd20 : - (_theResult____h242191[35] ? - 6'd21 : - (_theResult____h242191[34] ? - 6'd22 : - (_theResult____h242191[33] ? - 6'd23 : - (_theResult____h242191[32] ? - 6'd24 : - (_theResult____h242191[31] ? - 6'd25 : - (_theResult____h242191[30] ? - 6'd26 : - (_theResult____h242191[29] ? - 6'd27 : - (_theResult____h242191[28] ? - 6'd28 : - (_theResult____h242191[27] ? - 6'd29 : - (_theResult____h242191[26] ? - 6'd30 : - (_theResult____h242191[25] ? - 6'd31 : - (_theResult____h242191[24] ? - 6'd32 : - (_theResult____h242191[23] ? - 6'd33 : - (_theResult____h242191[22] ? - 6'd34 : - (_theResult____h242191[21] ? - 6'd35 : - (_theResult____h242191[20] ? - 6'd36 : - (_theResult____h242191[19] ? - 6'd37 : - (_theResult____h242191[18] ? - 6'd38 : - (_theResult____h242191[17] ? - 6'd39 : - (_theResult____h242191[16] ? - 6'd40 : - (_theResult____h242191[15] ? - 6'd41 : - (_theResult____h242191[14] ? - 6'd42 : - (_theResult____h242191[13] ? - 6'd43 : - (_theResult____h242191[12] ? - 6'd44 : - (_theResult____h242191[11] ? - 6'd45 : - (_theResult____h242191[10] ? - 6'd46 : - (_theResult____h242191[9] ? - 6'd47 : - (_theResult____h242191[8] ? - 6'd48 : - (_theResult____h242191[7] ? - 6'd49 : - (_theResult____h242191[6] ? - 6'd50 : - (_theResult____h242191[5] ? - 6'd51 : - (_theResult____h242191[4] ? - 6'd52 : - (_theResult____h242191[3] ? - 6'd53 : - (_theResult____h242191[2] ? - 6'd54 : - (_theResult____h242191[1] ? - 6'd55 : - (_theResult____h242191[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 = - (_theResult____h287214[56] ? - 6'd0 : - (_theResult____h287214[55] ? - 6'd1 : - (_theResult____h287214[54] ? - 6'd2 : - (_theResult____h287214[53] ? - 6'd3 : - (_theResult____h287214[52] ? - 6'd4 : - (_theResult____h287214[51] ? - 6'd5 : - (_theResult____h287214[50] ? - 6'd6 : - (_theResult____h287214[49] ? - 6'd7 : - (_theResult____h287214[48] ? - 6'd8 : - (_theResult____h287214[47] ? - 6'd9 : - (_theResult____h287214[46] ? - 6'd10 : - (_theResult____h287214[45] ? - 6'd11 : - (_theResult____h287214[44] ? - 6'd12 : - (_theResult____h287214[43] ? - 6'd13 : - (_theResult____h287214[42] ? - 6'd14 : - (_theResult____h287214[41] ? - 6'd15 : - (_theResult____h287214[40] ? - 6'd16 : - (_theResult____h287214[39] ? - 6'd17 : - (_theResult____h287214[38] ? - 6'd18 : - (_theResult____h287214[37] ? - 6'd19 : - (_theResult____h287214[36] ? - 6'd20 : - (_theResult____h287214[35] ? - 6'd21 : - (_theResult____h287214[34] ? - 6'd22 : - (_theResult____h287214[33] ? - 6'd23 : - (_theResult____h287214[32] ? - 6'd24 : - (_theResult____h287214[31] ? - 6'd25 : - (_theResult____h287214[30] ? - 6'd26 : - (_theResult____h287214[29] ? - 6'd27 : - (_theResult____h287214[28] ? - 6'd28 : - (_theResult____h287214[27] ? - 6'd29 : - (_theResult____h287214[26] ? - 6'd30 : - (_theResult____h287214[25] ? - 6'd31 : - (_theResult____h287214[24] ? - 6'd32 : - (_theResult____h287214[23] ? - 6'd33 : - (_theResult____h287214[22] ? - 6'd34 : - (_theResult____h287214[21] ? - 6'd35 : - (_theResult____h287214[20] ? - 6'd36 : - (_theResult____h287214[19] ? - 6'd37 : - (_theResult____h287214[18] ? - 6'd38 : - (_theResult____h287214[17] ? - 6'd39 : - (_theResult____h287214[16] ? - 6'd40 : - (_theResult____h287214[15] ? - 6'd41 : - (_theResult____h287214[14] ? - 6'd42 : - (_theResult____h287214[13] ? - 6'd43 : - (_theResult____h287214[12] ? - 6'd44 : - (_theResult____h287214[11] ? - 6'd45 : - (_theResult____h287214[10] ? - 6'd46 : - (_theResult____h287214[9] ? - 6'd47 : - (_theResult____h287214[8] ? - 6'd48 : - (_theResult____h287214[7] ? - 6'd49 : - (_theResult____h287214[6] ? - 6'd50 : - (_theResult____h287214[5] ? - 6'd51 : - (_theResult____h287214[4] ? - 6'd52 : - (_theResult____h287214[3] ? - 6'd53 : - (_theResult____h287214[2] ? - 6'd54 : - (_theResult____h287214[1] ? - 6'd55 : - (_theResult____h287214[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 = - (din_exp__h130866 == 11'd0) ? - 12'd3074 : - { din_exp30866_MINUS_1023__q23[10], - din_exp30866_MINUS_1023__q23 } ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 = - (sfdBC__h115662[105] ? - 7'd0 : - (sfdBC__h115662[104] ? - 7'd1 : - (sfdBC__h115662[103] ? - 7'd2 : - (sfdBC__h115662[102] ? - 7'd3 : - (sfdBC__h115662[101] ? - 7'd4 : - (sfdBC__h115662[100] ? - 7'd5 : - (sfdBC__h115662[99] ? - 7'd6 : - (sfdBC__h115662[98] ? - 7'd7 : - (sfdBC__h115662[97] ? - 7'd8 : - (sfdBC__h115662[96] ? - 7'd9 : - (sfdBC__h115662[95] ? - 7'd10 : - (sfdBC__h115662[94] ? - 7'd11 : - (sfdBC__h115662[93] ? - 7'd12 : - (sfdBC__h115662[92] ? - 7'd13 : - (sfdBC__h115662[91] ? - 7'd14 : - (sfdBC__h115662[90] ? - 7'd15 : - (sfdBC__h115662[89] ? - 7'd16 : - (sfdBC__h115662[88] ? - 7'd17 : - (sfdBC__h115662[87] ? - 7'd18 : - (sfdBC__h115662[86] ? - 7'd19 : - (sfdBC__h115662[85] ? - 7'd20 : - (sfdBC__h115662[84] ? - 7'd21 : - (sfdBC__h115662[83] ? - 7'd22 : - (sfdBC__h115662[82] ? - 7'd23 : - (sfdBC__h115662[81] ? - 7'd24 : - (sfdBC__h115662[80] ? - 7'd25 : - (sfdBC__h115662[79] ? - 7'd26 : - (sfdBC__h115662[78] ? - 7'd27 : - (sfdBC__h115662[77] ? - 7'd28 : - (sfdBC__h115662[76] ? - 7'd29 : - (sfdBC__h115662[75] ? - 7'd30 : - (sfdBC__h115662[74] ? - 7'd31 : - (sfdBC__h115662[73] ? - 7'd32 : - (sfdBC__h115662[72] ? - 7'd33 : - (sfdBC__h115662[71] ? - 7'd34 : - (sfdBC__h115662[70] ? - 7'd35 : - (sfdBC__h115662[69] ? - 7'd36 : - (sfdBC__h115662[68] ? - 7'd37 : - (sfdBC__h115662[67] ? - 7'd38 : - (sfdBC__h115662[66] ? - 7'd39 : - (sfdBC__h115662[65] ? - 7'd40 : - (sfdBC__h115662[64] ? - 7'd41 : - (sfdBC__h115662[63] ? - 7'd42 : - (sfdBC__h115662[62] ? - 7'd43 : - (sfdBC__h115662[61] ? - 7'd44 : - (sfdBC__h115662[60] ? - 7'd45 : - (sfdBC__h115662[59] ? - 7'd46 : - (sfdBC__h115662[58] ? - 7'd47 : - (sfdBC__h115662[57] ? - 7'd48 : - (sfdBC__h115662[56] ? - 7'd49 : - (sfdBC__h115662[55] ? - 7'd50 : - (sfdBC__h115662[54] ? - 7'd51 : - (sfdBC__h115662[53] ? - 7'd52 : - (sfdBC__h115662[52] ? - 7'd53 : - (sfdBC__h115662[51] ? - 7'd54 : - (sfdBC__h115662[50] ? - 7'd55 : - (sfdBC__h115662[49] ? - 7'd56 : - (sfdBC__h115662[48] ? - 7'd57 : - (sfdBC__h115662[47] ? - 7'd58 : - (sfdBC__h115662[46] ? - 7'd59 : - (sfdBC__h115662[45] ? - 7'd60 : - (sfdBC__h115662[44] ? - 7'd61 : - (sfdBC__h115662[43] ? - 7'd62 : - (sfdBC__h115662[42] ? - 7'd63 : - (sfdBC__h115662[41] ? - 7'd64 : - (sfdBC__h115662[40] ? - 7'd65 : - (sfdBC__h115662[39] ? - 7'd66 : - (sfdBC__h115662[38] ? - 7'd67 : - (sfdBC__h115662[37] ? - 7'd68 : - (sfdBC__h115662[36] ? - 7'd69 : - (sfdBC__h115662[35] ? - 7'd70 : - (sfdBC__h115662[34] ? - 7'd71 : - (sfdBC__h115662[33] ? - 7'd72 : - (sfdBC__h115662[32] ? - 7'd73 : - (sfdBC__h115662[31] ? - 7'd74 : - (sfdBC__h115662[30] ? - 7'd75 : - (sfdBC__h115662[29] ? - 7'd76 : - (sfdBC__h115662[28] ? - 7'd77 : - (sfdBC__h115662[27] ? - 7'd78 : - (sfdBC__h115662[26] ? - 7'd79 : - (sfdBC__h115662[25] ? - 7'd80 : - (sfdBC__h115662[24] ? - 7'd81 : - (sfdBC__h115662[23] ? - 7'd82 : - (sfdBC__h115662[22] ? - 7'd83 : - (sfdBC__h115662[21] ? - 7'd84 : - (sfdBC__h115662[20] ? - 7'd85 : - (sfdBC__h115662[19] ? - 7'd86 : - (sfdBC__h115662[18] ? - 7'd87 : - (sfdBC__h115662[17] ? - 7'd88 : - (sfdBC__h115662[16] ? - 7'd89 : - (sfdBC__h115662[15] ? - 7'd90 : - (sfdBC__h115662[14] ? - 7'd91 : - (sfdBC__h115662[13] ? - 7'd92 : - (sfdBC__h115662[12] ? - 7'd93 : - (sfdBC__h115662[11] ? - 7'd94 : - (sfdBC__h115662[10] ? - 7'd95 : - (sfdBC__h115662[9] ? - 7'd96 : - (sfdBC__h115662[8] ? - 7'd97 : - (sfdBC__h115662[7] ? - 7'd98 : - (sfdBC__h115662[6] ? - 7'd99 : - (sfdBC__h115662[5] ? - 7'd100 : - (sfdBC__h115662[4] ? - 7'd101 : - (sfdBC__h115662[3] ? - 7'd102 : - (sfdBC__h115662[2] ? - 7'd103 : - (sfdBC__h115662[1] ? - 7'd104 : - (sfdBC__h115662[0] ? - 7'd105 : - 7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 = - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 - - 12'd3074 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h130949, sfdin__h130943[105:54] } ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 = - (guard__h269587 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h277686 : - _theResult___exp__h278202 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 = - (guard__h269587 == 2'b0) ? - _theResult___fst_exp__h277686 : - (resWire$wget[68] ? - _theResult___exp__h278202 : - _theResult___fst_exp__h277686) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 = - (guard__h269587 == 2'b0 || resWire$wget[68]) ? - sfdin__h277680[56:34] : - _theResult___sfd__h278203 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 = - (guard__h269587 == 2'b0) ? - sfdin__h277680[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h278203 : - sfdin__h277680[56:34]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 = - (guard__h164624 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h172852 : - _theResult___exp__h173571 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 = - (guard__h164624 == 2'b0) ? - _theResult___fst_exp__h172852 : - (iFifo$D_OUT[168] ? - _theResult___exp__h173571 : - _theResult___fst_exp__h172852) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 = - (guard__h164624 == 2'b0 || iFifo$D_OUT[168]) ? - sfdin__h172846[56:5] : - _theResult___sfd__h173572 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 = - (guard__h164624 == 2'b0) ? - sfdin__h172846[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h173572 : - sfdin__h172846[56:5]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 = - (guard__h242201 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h250429 : - _theResult___exp__h251148 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 = - (guard__h242201 == 2'b0) ? - _theResult___fst_exp__h250429 : - (iFifo$D_OUT[38] ? - _theResult___exp__h251148 : - _theResult___fst_exp__h250429) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 = - (guard__h242201 == 2'b0 || iFifo$D_OUT[38]) ? - sfdin__h250423[56:5] : - _theResult___sfd__h251149 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 = - (guard__h242201 == 2'b0) ? - sfdin__h250423[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h251149 : - sfdin__h250423[56:5]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 = - (guard__h203262 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h211490 : - _theResult___exp__h212209 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 = - (guard__h203262 == 2'b0) ? - _theResult___fst_exp__h211490 : - (iFifo$D_OUT[103] ? - _theResult___exp__h212209 : - _theResult___fst_exp__h211490) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 = - (guard__h203262 == 2'b0 || iFifo$D_OUT[103]) ? - sfdin__h211484[56:5] : - _theResult___sfd__h212210 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 = - (guard__h203262 == 2'b0) ? - sfdin__h211484[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h212210 : - sfdin__h211484[56:5]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 = - (guard__h287224 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h295452 : - _theResult___exp__h295968 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 = - (guard__h287224 == 2'b0) ? - _theResult___fst_exp__h295452 : - (resWire$wget[68] ? - _theResult___exp__h295968 : - _theResult___fst_exp__h295452) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 = - (guard__h287224 == 2'b0 || resWire$wget[68]) ? - sfdin__h295446[56:34] : - _theResult___sfd__h295969 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 = - (guard__h287224 == 2'b0) ? - sfdin__h295446[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h295969 : - sfdin__h295446[56:34]) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 = - (guard__h194013 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h201974 : - _theResult___exp__h202619 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 = - (guard__h194013 == 2'b0) ? - _theResult___fst_exp__h201974 : - (iFifo$D_OUT[103] ? - _theResult___exp__h202619 : - _theResult___fst_exp__h201974) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 = - (guard__h212301 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h220291 : - _theResult___exp__h220961 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 = - (guard__h212301 == 2'b0) ? - _theResult___fst_exp__h220291 : - (iFifo$D_OUT[103] ? - _theResult___exp__h220961 : - _theResult___fst_exp__h220291) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 = - (guard__h194013 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___snd__h201925[56:5] : - _theResult___sfd__h202620 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 = - (guard__h194013 == 2'b0) ? - _theResult___snd__h201925[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h202620 : - _theResult___snd__h201925[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 = - (guard__h212301 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___snd__h220237[56:5] : - _theResult___sfd__h220962 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 = - (guard__h212301 == 2'b0) ? - _theResult___snd__h220237[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h220962 : - _theResult___snd__h220237[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 = - (guard__h155375 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h163336 : - _theResult___exp__h163981 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 = - (guard__h155375 == 2'b0) ? - _theResult___fst_exp__h163336 : - (iFifo$D_OUT[168] ? - _theResult___exp__h163981 : - _theResult___fst_exp__h163336) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 = - (guard__h173663 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h181653 : - _theResult___exp__h182323 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 = - (guard__h173663 == 2'b0) ? - _theResult___fst_exp__h181653 : - (iFifo$D_OUT[168] ? - _theResult___exp__h182323 : - _theResult___fst_exp__h181653) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 = - (guard__h155375 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___snd__h163287[56:5] : - _theResult___sfd__h163982 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 = - (guard__h155375 == 2'b0) ? - _theResult___snd__h163287[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h163982 : - _theResult___snd__h163287[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 = - (guard__h173663 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___snd__h181599[56:5] : - _theResult___sfd__h182324 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 = - (guard__h173663 == 2'b0) ? - _theResult___snd__h181599[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h182324 : - _theResult___snd__h181599[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 = - (guard__h232952 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h240913 : - _theResult___exp__h241558 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 = - (guard__h232952 == 2'b0) ? - _theResult___fst_exp__h240913 : - (iFifo$D_OUT[38] ? - _theResult___exp__h241558 : - _theResult___fst_exp__h240913) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 = - (guard__h251240 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h259230 : - _theResult___exp__h259900 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 = - (guard__h251240 == 2'b0) ? - _theResult___fst_exp__h259230 : - (iFifo$D_OUT[38] ? - _theResult___exp__h259900 : - _theResult___fst_exp__h259230) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 = - (guard__h232952 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___snd__h240864[56:5] : - _theResult___sfd__h241559 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 = - (guard__h232952 == 2'b0) ? - _theResult___snd__h240864[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h241559 : - _theResult___snd__h240864[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 = - (guard__h251240 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___snd__h259176[56:5] : - _theResult___sfd__h259901 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 = - (guard__h251240 == 2'b0) ? - _theResult___snd__h259176[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h259901 : - _theResult___snd__h259176[56:5]) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 = - (guard__h278294 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h286342 : - _theResult___exp__h286784 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 = - (guard__h278294 == 2'b0) ? - _theResult___fst_exp__h286342 : - (resWire$wget[68] ? - _theResult___exp__h286784 : - _theResult___fst_exp__h286342) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 = - (guard__h296060 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h304137 : - _theResult___exp__h304604 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 = - (guard__h296060 == 2'b0) ? - _theResult___fst_exp__h304137 : - (resWire$wget[68] ? - _theResult___exp__h304604 : - _theResult___fst_exp__h304137) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 = - (guard__h278294 == 2'b0 || resWire$wget[68]) ? - _theResult___snd__h286293[56:34] : - _theResult___sfd__h286785 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 = - (guard__h278294 == 2'b0) ? - _theResult___snd__h286293[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h286785 : - _theResult___snd__h286293[56:34]) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 = - (guard__h296060 == 2'b0 || resWire$wget[68]) ? - _theResult___snd__h304083[56:34] : - _theResult___sfd__h304605 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 = - (guard__h296060 == 2'b0) ? - _theResult___snd__h304083[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h304605 : - _theResult___snd__h304083[56:34]) ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 12'd3074 : - { theResult___fst_exp2290_MINUS_1023__q11[10], - theResult___fst_exp2290_MINUS_1023__q11 } ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 = - (sfdin__h34118[57] ? - 6'd0 : - (sfdin__h34118[56] ? - 6'd1 : - (sfdin__h34118[55] ? - 6'd2 : - (sfdin__h34118[54] ? - 6'd3 : - (sfdin__h34118[53] ? - 6'd4 : - (sfdin__h34118[52] ? - 6'd5 : - (sfdin__h34118[51] ? - 6'd6 : - (sfdin__h34118[50] ? - 6'd7 : - (sfdin__h34118[49] ? - 6'd8 : - (sfdin__h34118[48] ? - 6'd9 : - (sfdin__h34118[47] ? - 6'd10 : - (sfdin__h34118[46] ? - 6'd11 : - (sfdin__h34118[45] ? - 6'd12 : - (sfdin__h34118[44] ? - 6'd13 : - (sfdin__h34118[43] ? - 6'd14 : - (sfdin__h34118[42] ? - 6'd15 : - (sfdin__h34118[41] ? - 6'd16 : - (sfdin__h34118[40] ? - 6'd17 : - (sfdin__h34118[39] ? - 6'd18 : - (sfdin__h34118[38] ? - 6'd19 : - (sfdin__h34118[37] ? - 6'd20 : - (sfdin__h34118[36] ? - 6'd21 : - (sfdin__h34118[35] ? - 6'd22 : - (sfdin__h34118[34] ? - 6'd23 : - (sfdin__h34118[33] ? - 6'd24 : - (sfdin__h34118[32] ? - 6'd25 : - (sfdin__h34118[31] ? - 6'd26 : - (sfdin__h34118[30] ? - 6'd27 : - (sfdin__h34118[29] ? - 6'd28 : - (sfdin__h34118[28] ? - 6'd29 : - (sfdin__h34118[27] ? - 6'd30 : - (sfdin__h34118[26] ? - 6'd31 : - (sfdin__h34118[25] ? - 6'd32 : - (sfdin__h34118[24] ? - 6'd33 : - (sfdin__h34118[23] ? - 6'd34 : - (sfdin__h34118[22] ? - 6'd35 : - (sfdin__h34118[21] ? - 6'd36 : - (sfdin__h34118[20] ? - 6'd37 : - (sfdin__h34118[19] ? - 6'd38 : - (sfdin__h34118[18] ? - 6'd39 : - (sfdin__h34118[17] ? - 6'd40 : - (sfdin__h34118[16] ? - 6'd41 : - (sfdin__h34118[15] ? - 6'd42 : - (sfdin__h34118[14] ? - 6'd43 : - (sfdin__h34118[13] ? - 6'd44 : - (sfdin__h34118[12] ? - 6'd45 : - (sfdin__h34118[11] ? - 6'd46 : - (sfdin__h34118[10] ? - 6'd47 : - (sfdin__h34118[9] ? - 6'd48 : - (sfdin__h34118[8] ? - 6'd49 : - (sfdin__h34118[7] ? - 6'd50 : - (sfdin__h34118[6] ? - 6'd51 : - (sfdin__h34118[5] ? - 6'd52 : - (sfdin__h34118[4] ? - 6'd53 : - (sfdin__h34118[3] ? - 6'd54 : - (sfdin__h34118[2] ? - 6'd55 : - (sfdin__h34118[1] ? - 6'd56 : - (sfdin__h34118[0] ? - 6'd57 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 = - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 - - 12'd3074 ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926 = - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 ? - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921 : - { fpu_div64_fState_S3$D_OUT[129:128], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[127] : - fpu_div64_fState_S3$D_OUT[127], - fpu_div64_fState_S3$D_OUT[126], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[125] : - fpu_div64_fState_S3$D_OUT[125] } ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h42333, sfdin__h42327[57:6] } ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 == 52'd0) ? - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194] : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ? - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 : - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194]) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 == 52'd0) ? - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ? - 63'h7FF0000000000000 : - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936 = - (x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51]) ? - { fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 } : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118]) ? - fpu_madd_fOperand_S0$D_OUT[130:67] : - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54]) ? - fpu_madd_fOperand_S0$D_OUT[66:3] : - { NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 })) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51]) ? - { fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - x__h96539, - sfd__h99402 } : - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 ; - assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 = - (sfd__h133119[56] ? - 6'd0 : - (sfd__h133119[55] ? - 6'd1 : - (sfd__h133119[54] ? - 6'd2 : - (sfd__h133119[53] ? - 6'd3 : - (sfd__h133119[52] ? - 6'd4 : - (sfd__h133119[51] ? - 6'd5 : - (sfd__h133119[50] ? - 6'd6 : - (sfd__h133119[49] ? - 6'd7 : - (sfd__h133119[48] ? - 6'd8 : - (sfd__h133119[47] ? - 6'd9 : - (sfd__h133119[46] ? - 6'd10 : - (sfd__h133119[45] ? - 6'd11 : - (sfd__h133119[44] ? - 6'd12 : - (sfd__h133119[43] ? - 6'd13 : - (sfd__h133119[42] ? - 6'd14 : - (sfd__h133119[41] ? - 6'd15 : - (sfd__h133119[40] ? - 6'd16 : - (sfd__h133119[39] ? - 6'd17 : - (sfd__h133119[38] ? - 6'd18 : - (sfd__h133119[37] ? - 6'd19 : - (sfd__h133119[36] ? - 6'd20 : - (sfd__h133119[35] ? - 6'd21 : - (sfd__h133119[34] ? - 6'd22 : - (sfd__h133119[33] ? - 6'd23 : - (sfd__h133119[32] ? - 6'd24 : - (sfd__h133119[31] ? - 6'd25 : - (sfd__h133119[30] ? - 6'd26 : - (sfd__h133119[29] ? - 6'd27 : - (sfd__h133119[28] ? - 6'd28 : - (sfd__h133119[27] ? - 6'd29 : - (sfd__h133119[26] ? - 6'd30 : - (sfd__h133119[25] ? - 6'd31 : - (sfd__h133119[24] ? - 6'd32 : - (sfd__h133119[23] ? - 6'd33 : - (sfd__h133119[22] ? - 6'd34 : - (sfd__h133119[21] ? - 6'd35 : - (sfd__h133119[20] ? - 6'd36 : - (sfd__h133119[19] ? - 6'd37 : - (sfd__h133119[18] ? - 6'd38 : - (sfd__h133119[17] ? - 6'd39 : - (sfd__h133119[16] ? - 6'd40 : - (sfd__h133119[15] ? - 6'd41 : - (sfd__h133119[14] ? - 6'd42 : - (sfd__h133119[13] ? - 6'd43 : - (sfd__h133119[12] ? - 6'd44 : - (sfd__h133119[11] ? - 6'd45 : - (sfd__h133119[10] ? - 6'd46 : - (sfd__h133119[9] ? - 6'd47 : - (sfd__h133119[8] ? - 6'd48 : - (sfd__h133119[7] ? - 6'd49 : - (sfd__h133119[6] ? - 6'd50 : - (sfd__h133119[5] ? - 6'd51 : - (sfd__h133119[4] ? - 6'd52 : - (sfd__h133119[3] ? - 6'd53 : - (sfd__h133119[2] ? - 6'd54 : - (sfd__h133119[1] ? - 6'd55 : - (sfd__h133119[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h141375, sfdin__h141369[56:5] } ; - assign IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - ((IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73) : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 ; - assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503 = - (!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ? - fpu_madd_fState_S3$D_OUT[86] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[4] ; - assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506 = - (!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ? - fpu_madd_fState_S3$D_OUT[85] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[3] ; - assign IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 = - { NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 : - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 - - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 : - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 - - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563, - x__h131940, - x__h131944 } ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 = - ((SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99[10], - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - ((_theResult___fst_exp__h211490 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117) : - ((_theResult___fst_exp__h220291 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119) ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - ((_theResult___fst_exp__h211490 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123) : - ((_theResult___fst_exp__h220291 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125) ; - assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 = - ((SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39[10], - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - ((_theResult___fst_exp__h172852 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57) : - ((_theResult___fst_exp__h181653 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59) ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 = - ((SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66[10], - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - ((_theResult___fst_exp__h250429 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84) : - ((_theResult___fst_exp__h259230 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86) ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - ((_theResult___fst_exp__h250429 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90) : - ((_theResult___fst_exp__h259230 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 = - ((SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141[7], - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 }) - - 9'd386 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - ((_theResult___fst_exp__h295452 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324) : - ((_theResult___fst_exp__h304137 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - ((_theResult___fst_exp__h295452 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409) : - ((_theResult___fst_exp__h304137 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[2] : - _theResult___fst_exp__h304685 == 8'd255 && - _theResult___fst_sfd__h304686 == 23'd0 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[1] : - _theResult___fst_exp__h304137 == 8'd0 && - guard__h296060 != 2'b0 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[0] : - _theResult___fst_exp__h304137 != 8'd255 && - guard__h296060 != 2'b0 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 = - (((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7[10]}}, - fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7 }) - - { 7'd0, b__h4039 }) - - (((fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8[10]}}, - fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8 }) - - { 7'd0, b__h11457 }) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) <= - 13'd5120 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) < - 13'd3020 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) < - 13'd3074 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401) ? - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 : - CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0) ? - 11'd2047 : - ((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353) ? - 11'd0 : - _theResult___fst_exp__h19467) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401) ? - 52'd0 : - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ? - _theResult___fst_sfd__h19957 : - _theResult___fst_sfd__h19468) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54]) ? - { fpu_div64_fOperands_S0$D_OUT[66:55], sfd__h18937 } : - ((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118]) ? - fpu_div64_fOperands_S0$D_OUT[130:67] : - ((fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54]) ? - fpu_div64_fOperands_S0$D_OUT[66:3] : - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452)) ; - assign IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] == 2'b0 && - !fpu_div64_fState_S3$D_OUT[194] : - !fpu_div64_fState_S3$D_OUT[194] ; - assign IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921 = - ((fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - { fpu_div64_fState_S3$D_OUT[129:128], - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[127], - fpu_div64_fState_S3$D_OUT[126], - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[125] } : - fpu_div64_fState_S3$D_OUT[129:125]) | - { 2'd0, - sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023, - _theResult___fst_exp__h42336 == 11'd0 && guard__h33946 != 2'd0, - sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023 } ; - assign IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h42982[53:52] == 2'b01) ? - 11'd1 : - fpu_div64_fState_S4$D_OUT[64:54] ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 = - (fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 && - !fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ? - 63'h7FF8000000000000 : - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 = - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118]) ? - { fpu_madd_fOperand_S0$D_OUT[130:119], sfd__h99405 } : - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54]) ? - { fpu_madd_fOperand_S0$D_OUT[66:55], sfd__h99408 } : - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936) ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 = - { ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128[10]}}, - fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 }) + - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129[10]}}, - fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 }), - x__h114243, - x__h114255 } ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54] || - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 || - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[193:131] : - 63'd0 ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 && - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54] || - NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fProd_S3$D_OUT != 106'd0 || - fpu_madd_fState_S3$D_OUT[83] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[1] ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fProd_S3$D_OUT != 106'd0 || - fpu_madd_fState_S3$D_OUT[82] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[0] ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - (fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - 63'd0 : - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534) : - 63'h7FEFFFFFFFFFFFFF ; - assign IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525 = - fpu_madd_fState_S3$D_OUT[151] ? - fpu_madd_fState_S3$D_OUT[86:82] : - { IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 } ; - assign IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 = - (fpu_madd_fState_S4$D_OUT[128:118] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27[10]}}, - fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27 } ; - assign IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 = - (fpu_madd_fState_S4$D_OUT[64:54] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26[10]}}, - fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26 } ; - assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 = - (value__h141307[10:0] == 11'd0) ? - 12'd3074 : - { value41307_BITS_10_TO_0_MINUS_1023__q28[10], - value41307_BITS_10_TO_0_MINUS_1023__q28 } ; - assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 = - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 - - 12'd3074 ; - assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 = - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd0 && - sfd__h142040[53:52] == 2'b01) ? - 11'd1 : - fpu_madd_fState_S8$D_OUT[65:55] ; - assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 = - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[65:55] : - _theResult___fst_exp__h142619 ; - assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060 = - (fpu_madd_fState_S8$D_OUT[67] && - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 == - 11'd0 && - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h142620) == - 52'd0 && - !fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043[0] && - fpu_madd_fState_S8$D_OUT[0]) ? - fpu_madd_fState_S8$D_OUT[70:68] == 3'd3 : - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[66] : - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127) ; - assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 = - { IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060, - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[65:3] : - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132, - fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 } ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0) ? - (fpu_sqr64_fOperand_S0$D_OUT[54] ? - 6'd2 : - (fpu_sqr64_fOperand_S0$D_OUT[53] ? - 6'd3 : - (fpu_sqr64_fOperand_S0$D_OUT[52] ? - 6'd4 : - (fpu_sqr64_fOperand_S0$D_OUT[51] ? - 6'd5 : - (fpu_sqr64_fOperand_S0$D_OUT[50] ? - 6'd6 : - (fpu_sqr64_fOperand_S0$D_OUT[49] ? - 6'd7 : - (fpu_sqr64_fOperand_S0$D_OUT[48] ? - 6'd8 : - (fpu_sqr64_fOperand_S0$D_OUT[47] ? - 6'd9 : - (fpu_sqr64_fOperand_S0$D_OUT[46] ? - 6'd10 : - (fpu_sqr64_fOperand_S0$D_OUT[45] ? - 6'd11 : - (fpu_sqr64_fOperand_S0$D_OUT[44] ? - 6'd12 : - (fpu_sqr64_fOperand_S0$D_OUT[43] ? - 6'd13 : - (fpu_sqr64_fOperand_S0$D_OUT[42] ? - 6'd14 : - (fpu_sqr64_fOperand_S0$D_OUT[41] ? - 6'd15 : - (fpu_sqr64_fOperand_S0$D_OUT[40] ? - 6'd16 : - (fpu_sqr64_fOperand_S0$D_OUT[39] ? - 6'd17 : - (fpu_sqr64_fOperand_S0$D_OUT[38] ? - 6'd18 : - (fpu_sqr64_fOperand_S0$D_OUT[37] ? - 6'd19 : - (fpu_sqr64_fOperand_S0$D_OUT[36] ? - 6'd20 : - (fpu_sqr64_fOperand_S0$D_OUT[35] ? - 6'd21 : - (fpu_sqr64_fOperand_S0$D_OUT[34] ? - 6'd22 : - (fpu_sqr64_fOperand_S0$D_OUT[33] ? - 6'd23 : - (fpu_sqr64_fOperand_S0$D_OUT[32] ? - 6'd24 : - (fpu_sqr64_fOperand_S0$D_OUT[31] ? - 6'd25 : - (fpu_sqr64_fOperand_S0$D_OUT[30] ? - 6'd26 : - (fpu_sqr64_fOperand_S0$D_OUT[29] ? - 6'd27 : - (fpu_sqr64_fOperand_S0$D_OUT[28] ? - 6'd28 : - (fpu_sqr64_fOperand_S0$D_OUT[27] ? - 6'd29 : - (fpu_sqr64_fOperand_S0$D_OUT[26] ? - 6'd30 : - (fpu_sqr64_fOperand_S0$D_OUT[25] ? - 6'd31 : - (fpu_sqr64_fOperand_S0$D_OUT[24] ? - 6'd32 : - (fpu_sqr64_fOperand_S0$D_OUT[23] ? - 6'd33 : - (fpu_sqr64_fOperand_S0$D_OUT[22] ? - 6'd34 : - (fpu_sqr64_fOperand_S0$D_OUT[21] ? - 6'd35 : - (fpu_sqr64_fOperand_S0$D_OUT[20] ? - 6'd36 : - (fpu_sqr64_fOperand_S0$D_OUT[19] ? - 6'd37 : - (fpu_sqr64_fOperand_S0$D_OUT[18] ? - 6'd38 : - (fpu_sqr64_fOperand_S0$D_OUT[17] ? - 6'd39 : - (fpu_sqr64_fOperand_S0$D_OUT[16] ? - 6'd40 : - (fpu_sqr64_fOperand_S0$D_OUT[15] ? - 6'd41 : - (fpu_sqr64_fOperand_S0$D_OUT[14] ? - 6'd42 : - (fpu_sqr64_fOperand_S0$D_OUT[13] ? - 6'd43 : - (fpu_sqr64_fOperand_S0$D_OUT[12] ? - 6'd44 : - (fpu_sqr64_fOperand_S0$D_OUT[11] ? - 6'd45 : - (fpu_sqr64_fOperand_S0$D_OUT[10] ? - 6'd46 : - (fpu_sqr64_fOperand_S0$D_OUT[9] ? - 6'd47 : - (fpu_sqr64_fOperand_S0$D_OUT[8] ? - 6'd48 : - (fpu_sqr64_fOperand_S0$D_OUT[7] ? - 6'd49 : - (fpu_sqr64_fOperand_S0$D_OUT[6] ? - 6'd50 : - (fpu_sqr64_fOperand_S0$D_OUT[5] ? - 6'd51 : - (fpu_sqr64_fOperand_S0$D_OUT[4] ? - 6'd52 : - (fpu_sqr64_fOperand_S0$D_OUT[3] ? - 6'd53 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1 ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195 = - ((fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16[10]}}, - fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16 }) - - { 7'd0, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 } ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212 = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54] || - fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] == 52'd0 && - !fpu_sqr64_fOperand_S0$D_OUT[66]) ? - { 1'd1, - fpu_sqr64_fOperand_S0$D_OUT[66:3], - 130'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - (fpu_sqr64_fOperand_S0$D_OUT[66] ? - 195'h5FFE00000000000020AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - { 70'h155555555555555540, - fpu_sqr64_fOperand_S0$D_OUT[2:0], - fpu_sqr64_fOperand_S0$D_OUT[66], - x__h52551[10:0], - fpu_sqr64_fOperand_S0$D_OUT[54:3], - x__h60693 }) ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195[12:1] ; - assign IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 = - (fpu_sqr64_fState_S1$D_OUT[57] ? - 7'd0 : - (fpu_sqr64_fState_S1$D_OUT[56] ? - 7'd1 : - (fpu_sqr64_fState_S1$D_OUT[55] ? - 7'd2 : - (fpu_sqr64_fState_S1$D_OUT[54] ? - 7'd3 : - (fpu_sqr64_fState_S1$D_OUT[53] ? - 7'd4 : - (fpu_sqr64_fState_S1$D_OUT[52] ? - 7'd5 : - (fpu_sqr64_fState_S1$D_OUT[51] ? - 7'd6 : - (fpu_sqr64_fState_S1$D_OUT[50] ? - 7'd7 : - (fpu_sqr64_fState_S1$D_OUT[49] ? - 7'd8 : - (fpu_sqr64_fState_S1$D_OUT[48] ? - 7'd9 : - (fpu_sqr64_fState_S1$D_OUT[47] ? - 7'd10 : - (fpu_sqr64_fState_S1$D_OUT[46] ? - 7'd11 : - (fpu_sqr64_fState_S1$D_OUT[45] ? - 7'd12 : - (fpu_sqr64_fState_S1$D_OUT[44] ? - 7'd13 : - (fpu_sqr64_fState_S1$D_OUT[43] ? - 7'd14 : - (fpu_sqr64_fState_S1$D_OUT[42] ? - 7'd15 : - (fpu_sqr64_fState_S1$D_OUT[41] ? - 7'd16 : - (fpu_sqr64_fState_S1$D_OUT[40] ? - 7'd17 : - (fpu_sqr64_fState_S1$D_OUT[39] ? - 7'd18 : - (fpu_sqr64_fState_S1$D_OUT[38] ? - 7'd19 : - (fpu_sqr64_fState_S1$D_OUT[37] ? - 7'd20 : - (fpu_sqr64_fState_S1$D_OUT[36] ? - 7'd21 : - (fpu_sqr64_fState_S1$D_OUT[35] ? - 7'd22 : - (fpu_sqr64_fState_S1$D_OUT[34] ? - 7'd23 : - (fpu_sqr64_fState_S1$D_OUT[33] ? - 7'd24 : - (fpu_sqr64_fState_S1$D_OUT[32] ? - 7'd25 : - (fpu_sqr64_fState_S1$D_OUT[31] ? - 7'd26 : - (fpu_sqr64_fState_S1$D_OUT[30] ? - 7'd27 : - (fpu_sqr64_fState_S1$D_OUT[29] ? - 7'd28 : - (fpu_sqr64_fState_S1$D_OUT[28] ? - 7'd29 : - (fpu_sqr64_fState_S1$D_OUT[27] ? - 7'd30 : - (fpu_sqr64_fState_S1$D_OUT[26] ? - 7'd31 : - (fpu_sqr64_fState_S1$D_OUT[25] ? - 7'd32 : - (fpu_sqr64_fState_S1$D_OUT[24] ? - 7'd33 : - (fpu_sqr64_fState_S1$D_OUT[23] ? - 7'd34 : - (fpu_sqr64_fState_S1$D_OUT[22] ? - 7'd35 : - (fpu_sqr64_fState_S1$D_OUT[21] ? - 7'd36 : - (fpu_sqr64_fState_S1$D_OUT[20] ? - 7'd37 : - (fpu_sqr64_fState_S1$D_OUT[19] ? - 7'd38 : - (fpu_sqr64_fState_S1$D_OUT[18] ? - 7'd39 : - (fpu_sqr64_fState_S1$D_OUT[17] ? - 7'd40 : - (fpu_sqr64_fState_S1$D_OUT[16] ? - 7'd41 : - (fpu_sqr64_fState_S1$D_OUT[15] ? - 7'd42 : - (fpu_sqr64_fState_S1$D_OUT[14] ? - 7'd43 : - (fpu_sqr64_fState_S1$D_OUT[13] ? - 7'd44 : - (fpu_sqr64_fState_S1$D_OUT[12] ? - 7'd45 : - (fpu_sqr64_fState_S1$D_OUT[11] ? - 7'd46 : - (fpu_sqr64_fState_S1$D_OUT[10] ? - 7'd47 : - (fpu_sqr64_fState_S1$D_OUT[9] ? - 7'd48 : - (fpu_sqr64_fState_S1$D_OUT[8] ? - 7'd49 : - (fpu_sqr64_fState_S1$D_OUT[7] ? - 7'd50 : - (fpu_sqr64_fState_S1$D_OUT[6] ? - 7'd51 : - (fpu_sqr64_fState_S1$D_OUT[5] ? - 7'd52 : - (fpu_sqr64_fState_S1$D_OUT[4] ? - 7'd53 : - (fpu_sqr64_fState_S1$D_OUT[3] ? - 7'd54 : - (fpu_sqr64_fState_S1$D_OUT[2] ? - 7'd55 : - (fpu_sqr64_fState_S1$D_OUT[1] ? - 7'd56 : - (fpu_sqr64_fState_S1$D_OUT[0] ? - 7'd57 : - 7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 12'd3074 : - { fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18[10], - fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18 } ; - assign IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 = - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 - - 12'd3074 ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671 = - fpu_sqr64_fState_S3$D_OUT[195] ? - fpu_sqr64_fState_S3$D_OUT[128:126] : - { fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023, - _theResult___fst_exp__h94753 == 11'd0 && - guard__h86435 != 2'd0, - fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023 } ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h94750, sfdin__h94744[58:7] } ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 = - (fpu_sqr64_fState_S3$D_OUT[58] ? - 6'd0 : - (fpu_sqr64_fState_S3$D_OUT[57] ? - 6'd1 : - (fpu_sqr64_fState_S3$D_OUT[56] ? - 6'd2 : - (fpu_sqr64_fState_S3$D_OUT[55] ? - 6'd3 : - (fpu_sqr64_fState_S3$D_OUT[54] ? - 6'd4 : - (fpu_sqr64_fState_S3$D_OUT[53] ? - 6'd5 : - (fpu_sqr64_fState_S3$D_OUT[52] ? - 6'd6 : - (fpu_sqr64_fState_S3$D_OUT[51] ? - 6'd7 : - (fpu_sqr64_fState_S3$D_OUT[50] ? - 6'd8 : - (fpu_sqr64_fState_S3$D_OUT[49] ? - 6'd9 : - (fpu_sqr64_fState_S3$D_OUT[48] ? - 6'd10 : - (fpu_sqr64_fState_S3$D_OUT[47] ? - 6'd11 : - (fpu_sqr64_fState_S3$D_OUT[46] ? - 6'd12 : - (fpu_sqr64_fState_S3$D_OUT[45] ? - 6'd13 : - (fpu_sqr64_fState_S3$D_OUT[44] ? - 6'd14 : - (fpu_sqr64_fState_S3$D_OUT[43] ? - 6'd15 : - (fpu_sqr64_fState_S3$D_OUT[42] ? - 6'd16 : - (fpu_sqr64_fState_S3$D_OUT[41] ? - 6'd17 : - (fpu_sqr64_fState_S3$D_OUT[40] ? - 6'd18 : - (fpu_sqr64_fState_S3$D_OUT[39] ? - 6'd19 : - (fpu_sqr64_fState_S3$D_OUT[38] ? - 6'd20 : - (fpu_sqr64_fState_S3$D_OUT[37] ? - 6'd21 : - (fpu_sqr64_fState_S3$D_OUT[36] ? - 6'd22 : - (fpu_sqr64_fState_S3$D_OUT[35] ? - 6'd23 : - (fpu_sqr64_fState_S3$D_OUT[34] ? - 6'd24 : - (fpu_sqr64_fState_S3$D_OUT[33] ? - 6'd25 : - (fpu_sqr64_fState_S3$D_OUT[32] ? - 6'd26 : - (fpu_sqr64_fState_S3$D_OUT[31] ? - 6'd27 : - (fpu_sqr64_fState_S3$D_OUT[30] ? - 6'd28 : - (fpu_sqr64_fState_S3$D_OUT[29] ? - 6'd29 : - (fpu_sqr64_fState_S3$D_OUT[28] ? - 6'd30 : - (fpu_sqr64_fState_S3$D_OUT[27] ? - 6'd31 : - (fpu_sqr64_fState_S3$D_OUT[26] ? - 6'd32 : - (fpu_sqr64_fState_S3$D_OUT[25] ? - 6'd33 : - (fpu_sqr64_fState_S3$D_OUT[24] ? - 6'd34 : - (fpu_sqr64_fState_S3$D_OUT[23] ? - 6'd35 : - (fpu_sqr64_fState_S3$D_OUT[22] ? - 6'd36 : - (fpu_sqr64_fState_S3$D_OUT[21] ? - 6'd37 : - (fpu_sqr64_fState_S3$D_OUT[20] ? - 6'd38 : - (fpu_sqr64_fState_S3$D_OUT[19] ? - 6'd39 : - (fpu_sqr64_fState_S3$D_OUT[18] ? - 6'd40 : - (fpu_sqr64_fState_S3$D_OUT[17] ? - 6'd41 : - (fpu_sqr64_fState_S3$D_OUT[16] ? - 6'd42 : - (fpu_sqr64_fState_S3$D_OUT[15] ? - 6'd43 : - (fpu_sqr64_fState_S3$D_OUT[14] ? - 6'd44 : - (fpu_sqr64_fState_S3$D_OUT[13] ? - 6'd45 : - (fpu_sqr64_fState_S3$D_OUT[12] ? - 6'd46 : - (fpu_sqr64_fState_S3$D_OUT[11] ? - 6'd47 : - (fpu_sqr64_fState_S3$D_OUT[10] ? - 6'd48 : - (fpu_sqr64_fState_S3$D_OUT[9] ? - 6'd49 : - (fpu_sqr64_fState_S3$D_OUT[8] ? - 6'd50 : - (fpu_sqr64_fState_S3$D_OUT[7] ? - 6'd51 : - (fpu_sqr64_fState_S3$D_OUT[6] ? - 6'd52 : - (fpu_sqr64_fState_S3$D_OUT[5] ? - 6'd53 : - (fpu_sqr64_fState_S3$D_OUT[4] ? - 6'd54 : - (fpu_sqr64_fState_S3$D_OUT[3] ? - 6'd55 : - (fpu_sqr64_fState_S3$D_OUT[2] ? - 6'd56 : - (fpu_sqr64_fState_S3$D_OUT[1] ? - 6'd57 : - (fpu_sqr64_fState_S3$D_OUT[0] ? - 6'd58 : - 6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h95416[53:52] == 2'b01) ? - 11'd1 : - fpu_sqr64_fState_S4$D_OUT[64:54] ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 = - ((iFifo$D_OUT[102:95] == 8'd0) ? - (iFifo$D_OUT[94] ? - 6'd2 : - (iFifo$D_OUT[93] ? - 6'd3 : - (iFifo$D_OUT[92] ? - 6'd4 : - (iFifo$D_OUT[91] ? - 6'd5 : - (iFifo$D_OUT[90] ? - 6'd6 : - (iFifo$D_OUT[89] ? - 6'd7 : - (iFifo$D_OUT[88] ? - 6'd8 : - (iFifo$D_OUT[87] ? - 6'd9 : - (iFifo$D_OUT[86] ? - 6'd10 : - (iFifo$D_OUT[85] ? - 6'd11 : - (iFifo$D_OUT[84] ? - 6'd12 : - (iFifo$D_OUT[83] ? - 6'd13 : - (iFifo$D_OUT[82] ? - 6'd14 : - (iFifo$D_OUT[81] ? - 6'd15 : - (iFifo$D_OUT[80] ? - 6'd16 : - (iFifo$D_OUT[79] ? - 6'd17 : - (iFifo$D_OUT[78] ? - 6'd18 : - (iFifo$D_OUT[77] ? - 6'd19 : - (iFifo$D_OUT[76] ? - 6'd20 : - (iFifo$D_OUT[75] ? - 6'd21 : - (iFifo$D_OUT[74] ? - 6'd22 : - (iFifo$D_OUT[73] ? - 6'd23 : - (iFifo$D_OUT[72] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 = - { (iFifo$D_OUT[102:95] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h221054, - (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0) ? - _theResult___snd_fst_sfd__h183126 : - _theResult___fst_sfd__h221058 } ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 = - { (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0 || - (iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - iFifo$D_OUT[103] : - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 = - { (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0 || - (iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - !iFifo$D_OUT[103] : - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 = - ((iFifo$D_OUT[167:160] == 8'd0) ? - (iFifo$D_OUT[159] ? - 6'd2 : - (iFifo$D_OUT[158] ? - 6'd3 : - (iFifo$D_OUT[157] ? - 6'd4 : - (iFifo$D_OUT[156] ? - 6'd5 : - (iFifo$D_OUT[155] ? - 6'd6 : - (iFifo$D_OUT[154] ? - 6'd7 : - (iFifo$D_OUT[153] ? - 6'd8 : - (iFifo$D_OUT[152] ? - 6'd9 : - (iFifo$D_OUT[151] ? - 6'd10 : - (iFifo$D_OUT[150] ? - 6'd11 : - (iFifo$D_OUT[149] ? - 6'd12 : - (iFifo$D_OUT[148] ? - 6'd13 : - (iFifo$D_OUT[147] ? - 6'd14 : - (iFifo$D_OUT[146] ? - 6'd15 : - (iFifo$D_OUT[145] ? - 6'd16 : - (iFifo$D_OUT[144] ? - 6'd17 : - (iFifo$D_OUT[143] ? - 6'd18 : - (iFifo$D_OUT[142] ? - 6'd19 : - (iFifo$D_OUT[141] ? - 6'd20 : - (iFifo$D_OUT[140] ? - 6'd21 : - (iFifo$D_OUT[139] ? - 6'd22 : - (iFifo$D_OUT[138] ? - 6'd23 : - (iFifo$D_OUT[137] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 = - { (iFifo$D_OUT[167:160] == 8'd255 && - iFifo$D_OUT[159:137] != 23'd0 || - (iFifo$D_OUT[167:160] == 8'd255 || - iFifo$D_OUT[167:160] == 8'd0) && - iFifo$D_OUT[159:137] == 23'd0) ? - iFifo$D_OUT[168] : - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665, - (iFifo$D_OUT[167:160] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h182416, - (iFifo$D_OUT[167:160] == 8'd255 && - iFifo$D_OUT[159:137] != 23'd0) ? - _theResult___snd_fst_sfd__h144486 : - _theResult___fst_sfd__h182420 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 = - ((iFifo$D_OUT[37:30] == 8'd0) ? - (iFifo$D_OUT[29] ? - 6'd2 : - (iFifo$D_OUT[28] ? - 6'd3 : - (iFifo$D_OUT[27] ? - 6'd4 : - (iFifo$D_OUT[26] ? - 6'd5 : - (iFifo$D_OUT[25] ? - 6'd6 : - (iFifo$D_OUT[24] ? - 6'd7 : - (iFifo$D_OUT[23] ? - 6'd8 : - (iFifo$D_OUT[22] ? - 6'd9 : - (iFifo$D_OUT[21] ? - 6'd10 : - (iFifo$D_OUT[20] ? - 6'd11 : - (iFifo$D_OUT[19] ? - 6'd12 : - (iFifo$D_OUT[18] ? - 6'd13 : - (iFifo$D_OUT[17] ? - 6'd14 : - (iFifo$D_OUT[16] ? - 6'd15 : - (iFifo$D_OUT[15] ? - 6'd16 : - (iFifo$D_OUT[14] ? - 6'd17 : - (iFifo$D_OUT[13] ? - 6'd18 : - (iFifo$D_OUT[12] ? - 6'd19 : - (iFifo$D_OUT[11] ? - 6'd20 : - (iFifo$D_OUT[10] ? - 6'd21 : - (iFifo$D_OUT[9] ? - 6'd22 : - (iFifo$D_OUT[8] ? - 6'd23 : - (iFifo$D_OUT[7] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 = - { (iFifo$D_OUT[37:30] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h259993, - (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0) ? - _theResult___snd_fst_sfd__h222065 : - _theResult___fst_sfd__h259997 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 = - { (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 || - (iFifo$D_OUT[37:30] == 8'd255 || - iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - iFifo$D_OUT[38] : - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 = - { (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 || - (iFifo$D_OUT[37:30] == 8'd255 || - iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - !iFifo$D_OUT[38] : - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ; - assign IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 = - iFifo$D_OUT[136] ? - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 : - iFifo$D_OUT[135:72] ; - assign IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 = - iFifo$D_OUT[201] ? - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 : - iFifo$D_OUT[200:137] ; - assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555 = - iFifo$D_OUT[71] ? - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 : - iFifo$D_OUT[70:7] ; - assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 = - iFifo$D_OUT[71] ? - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 : - { iFifo$D_OUT[71] || !iFifo$D_OUT[70], iFifo$D_OUT[69:7] } ; - assign IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657 = - isDoubleFifo$D_OUT ? - { isNegateFifo$D_OUT ^ resWire$wget[68], resWire$wget[67:5] } : - { 32'hAAAAAAAA, - IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424, - exp__h304706, - sfd__h304707 } ; - assign IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424 = - isNegateFifo$D_OUT ? - ((resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0 || - (resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - !resWire$wget[68] : - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377) : - ((resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0 || - (resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - resWire$wget[68] : - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 = - ((resWire$wget[67:57] == 11'd0) ? - (resWire$wget[56] ? - 6'd2 : - (resWire$wget[55] ? - 6'd3 : - (resWire$wget[54] ? - 6'd4 : - (resWire$wget[53] ? - 6'd5 : - (resWire$wget[52] ? - 6'd6 : - (resWire$wget[51] ? - 6'd7 : - (resWire$wget[50] ? - 6'd8 : - (resWire$wget[49] ? - 6'd9 : - (resWire$wget[48] ? - 6'd10 : - (resWire$wget[47] ? - 6'd11 : - (resWire$wget[46] ? - 6'd12 : - (resWire$wget[45] ? - 6'd13 : - (resWire$wget[44] ? - 6'd14 : - (resWire$wget[43] ? - 6'd15 : - (resWire$wget[42] ? - 6'd16 : - (resWire$wget[41] ? - 6'd17 : - (resWire$wget[40] ? - 6'd18 : - (resWire$wget[39] ? - 6'd19 : - (resWire$wget[38] ? - 6'd20 : - (resWire$wget[37] ? - 6'd21 : - (resWire$wget[36] ? - 6'd22 : - (resWire$wget[35] ? - 6'd23 : - (resWire$wget[34] ? - 6'd24 : - (resWire$wget[33] ? - 6'd25 : - (resWire$wget[32] ? - 6'd26 : - (resWire$wget[31] ? - 6'd27 : - (resWire$wget[30] ? - 6'd28 : - (resWire$wget[29] ? - 6'd29 : - (resWire$wget[28] ? - 6'd30 : - (resWire$wget[27] ? - 6'd31 : - (resWire$wget[26] ? - 6'd32 : - (resWire$wget[25] ? - 6'd33 : - (resWire$wget[24] ? - 6'd34 : - (resWire$wget[23] ? - 6'd35 : - (resWire$wget[22] ? - 6'd36 : - (resWire$wget[21] ? - 6'd37 : - (resWire$wget[20] ? - 6'd38 : - (resWire$wget[19] ? - 6'd39 : - (resWire$wget[18] ? - 6'd40 : - (resWire$wget[17] ? - 6'd41 : - (resWire$wget[16] ? - 6'd42 : - (resWire$wget[15] ? - 6'd43 : - (resWire$wget[14] ? - 6'd44 : - (resWire$wget[13] ? - 6'd45 : - (resWire$wget[12] ? - 6'd46 : - (resWire$wget[11] ? - 6'd47 : - (resWire$wget[10] ? - 6'd48 : - (resWire$wget[9] ? - 6'd49 : - (resWire$wget[8] ? - 6'd50 : - (resWire$wget[7] ? - 6'd51 : - (resWire$wget[6] ? - 6'd52 : - (resWire$wget[5] ? - 6'd53 : - 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[4] ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[3] ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736 = - (resWire$wget[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 : - !SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 || - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 = - (resWire$wget[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 : - !SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 || - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 = - rg_index_1_4_ULE_58___d38 ? _theResult___fst__h1515 : rg_b ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 = - rg_index_1_4_ULE_58___d38 ? - _theResult___snd_snd_snd__h1520 : - rg_r_1 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 = - rg_index_1_4_ULE_58___d38 ? - IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72 : - rg_res[115:0] ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 = - rg_index_1_4_ULE_58___d38 ? _theResult___snd_fst__h1517 : rg_s ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 < - sum__h1710 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 = - rg_index_1_4_ULE_58___d38 ? - rg_b != 116'd0 && !rg_res[116] : - !rg_res[116] ; - assign IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44 = - rg_index_1_4_ULE_58___d38 ? - rg_b == 116'd0 || rg_res[116] : - rg_res[116] ; - assign IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 = - rg_index_ULE_57___d7 ? - (rg_r[115] ? - { rg_r[114:0], 1'd0 } + b__h32583 : - { rg_r[114:0], 1'd0 } - b__h32583) : - rg_r ; - assign IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 = - rg_index_ULE_57___d7 ? { rg_q[56:0], !rg_r[115] } : rg_q ; - assign IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10 = - rg_r[115] ? - rg_q_PLUS_NEG_INV_rg_q_59_60___d561 - 58'd1 : - rg_q_PLUS_NEG_INV_rg_q_59_60___d561 ; - assign IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72 = - rg_res[116] ? - rg_res[115:0] : - ((rg_b == 116'd0) ? rg_r_1 : rg_res[115:0]) ; - assign IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98 = - sfdin__h211484[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13 = - sfdin__h42327[5] ? 2'd2 : 2'd0 ; - assign IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25 = - sfdin__h130943[53] ? 2'd2 : 2'd0 ; - assign IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30 = - sfdin__h141369[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20 = - sfdin__h94744[6] ? 2'd2 : 2'd0 ; - assign IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65 = - sfdin__h250423[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38 = - sfdin__h172846[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134 = - sfdin__h277680[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140 = - sfdin__h295446[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94 = - _theResult___snd__h201925[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143 = - _theResult___snd__h304083[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101 = - _theResult___snd__h220237[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61 = - _theResult___snd__h240864[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68 = - _theResult___snd__h259176[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34 = - _theResult___snd__h163287[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41 = - _theResult___snd__h181599[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136 = - _theResult___snd__h286293[33] ? 2'd2 : 2'd0 ; - assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 = - !_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 || - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[2] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 = - !_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 || - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[0] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[0]) ; - assign NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 = - (x__h96539 != 11'd2047 || !_theResult___fst_sfd__h96608[51]) && - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - !fpu_madd_fOperand_S0$D_OUT[118]) && - (fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - !fpu_madd_fOperand_S0$D_OUT[54]) && - (fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 && - !fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 = - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452 = - { NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 && - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436 ? - 52'h8000000000000 : - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450 } ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481 = - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 && - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488 = - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (!IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355) ; - assign NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923 = - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) && - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) && - (x__h96539 != 11'd2047 || - _theResult___fst_sfd__h96608 != 52'd0 || - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0) && - (fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) || - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) && - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 ; - assign NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 = - fpu_madd_fOperand_S0$D_OUT[130] != - fpu_madd_fOperand_S0$D_OUT[66] ; - assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510 = - !fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - (fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fState_S3$D_OUT[84] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[2]) ; - assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 = - { NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 : - fpu_madd_fState_S3$D_OUT[83], - !fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 } ; - assign NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 = - !fpu_madd_fState_S4$D_OUT[130] || - (IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 ^ - 13'h1000) > - (IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 ^ - 13'h1000) || - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 == - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 && - sfdBC__h131578 > sfdA__h131577 ; - assign NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 = - !iFifo$D_OUT[158] && !iFifo$D_OUT[157] && !iFifo$D_OUT[156] && - !iFifo$D_OUT[155] && - !iFifo$D_OUT[154] && - !iFifo$D_OUT[153] && - !iFifo$D_OUT[152] && - !iFifo$D_OUT[151] && - !iFifo$D_OUT[150] && - !iFifo$D_OUT[149] && - !iFifo$D_OUT[148] && - !iFifo$D_OUT[147] && - !iFifo$D_OUT[146] && - !iFifo$D_OUT[145] && - !iFifo$D_OUT[144] && - !iFifo$D_OUT[143] && - !iFifo$D_OUT[142] && - !iFifo$D_OUT[141] && - !iFifo$D_OUT[140] && - !iFifo$D_OUT[139] && - !iFifo$D_OUT[138] && - !iFifo$D_OUT[137] ; - assign NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 = - !iFifo$D_OUT[28] && !iFifo$D_OUT[27] && !iFifo$D_OUT[26] && - !iFifo$D_OUT[25] && - !iFifo$D_OUT[24] && - !iFifo$D_OUT[23] && - !iFifo$D_OUT[22] && - !iFifo$D_OUT[21] && - !iFifo$D_OUT[20] && - !iFifo$D_OUT[19] && - !iFifo$D_OUT[18] && - !iFifo$D_OUT[17] && - !iFifo$D_OUT[16] && - !iFifo$D_OUT[15] && - !iFifo$D_OUT[14] && - !iFifo$D_OUT[13] && - !iFifo$D_OUT[12] && - !iFifo$D_OUT[11] && - !iFifo$D_OUT[10] && - !iFifo$D_OUT[9] && - !iFifo$D_OUT[8] && - !iFifo$D_OUT[7] ; - assign NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 = - !iFifo$D_OUT[93] && !iFifo$D_OUT[92] && !iFifo$D_OUT[91] && - !iFifo$D_OUT[90] && - !iFifo$D_OUT[89] && - !iFifo$D_OUT[88] && - !iFifo$D_OUT[87] && - !iFifo$D_OUT[86] && - !iFifo$D_OUT[85] && - !iFifo$D_OUT[84] && - !iFifo$D_OUT[83] && - !iFifo$D_OUT[82] && - !iFifo$D_OUT[81] && - !iFifo$D_OUT[80] && - !iFifo$D_OUT[79] && - !iFifo$D_OUT[78] && - !iFifo$D_OUT[77] && - !iFifo$D_OUT[76] && - !iFifo$D_OUT[75] && - !iFifo$D_OUT[74] && - !iFifo$D_OUT[73] && - !iFifo$D_OUT[72] ; - assign NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 = - !resWire$wget[56] && !resWire$wget[55] && !resWire$wget[54] && - !resWire$wget[53] && - !resWire$wget[52] && - !resWire$wget[51] && - !resWire$wget[50] && - !resWire$wget[49] && - !resWire$wget[48] && - !resWire$wget[47] && - !resWire$wget[46] && - !resWire$wget[45] && - !resWire$wget[44] && - !resWire$wget[43] && - !resWire$wget[42] && - !resWire$wget[41] && - !resWire$wget[40] && - !resWire$wget[39] && - !resWire$wget[38] && - !resWire$wget[37] && - !resWire$wget[36] && - !resWire$wget[35] && - !resWire$wget[34] && - !resWire$wget[33] && - !resWire$wget[32] && - !resWire$wget[31] && - !resWire$wget[30] && - !resWire$wget[29] && - !resWire$wget[28] && - !resWire$wget[27] && - !resWire$wget[26] && - !resWire$wget[25] && - !resWire$wget[24] && - !resWire$wget[23] && - !resWire$wget[22] && - !resWire$wget[21] && - !resWire$wget[20] && - !resWire$wget[19] && - !resWire$wget[18] && - !resWire$wget[17] && - !resWire$wget[16] && - !resWire$wget[15] && - !resWire$wget[14] && - !resWire$wget[13] && - !resWire$wget[12] && - !resWire$wget[11] && - !resWire$wget[10] && - !resWire$wget[9] && - !resWire$wget[8] && - !resWire$wget[7] && - !resWire$wget[6] && - !resWire$wget[5] ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 = - { {4{iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95[7]}}, - iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 } ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] - - 11'd1023 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 = - { {4{iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35[7]}}, - iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 } ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] - - 11'd1023 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 = - { {4{iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62[7]}}, - iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 } ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] - - 11'd1023 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 = - { resWirewget_BITS_67_TO_57_MINUS_1023__q137[10], - resWirewget_BITS_67_TO_57_MINUS_1023__q137 } ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 + - 12'd127 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] - - 8'd127 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 = - ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676 = - { 3'd0, - _theResult___fst_exp__h277686 == 8'd0 && - (sfdin__h277680[56:34] == 23'd0 || guard__h269587 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h278283 == 8'd255 && - _theResult___fst_sfd__h278284 == 23'd0, - 1'd0, - _theResult___fst_exp__h277686 != 8'd255 && - guard__h269587 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 = - ({ 3'd0, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705 = - { 3'd0, - _theResult___fst_exp__h295452 == 8'd0 && - (sfdin__h295446[56:34] == 23'd0 || guard__h287224 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h296049 == 8'd255 && - _theResult___fst_sfd__h296050 == 23'd0, - 1'd0, - _theResult___fst_exp__h295452 != 8'd255 && - guard__h287224 != 2'b0 } ; - assign _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 = - ({ 5'd0, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ^ - 12'h800) <= - (IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883 = - ({ 6'd0, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 } ^ - 12'h800) <= - (IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 = - ({ 6'd0, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ^ - 12'h800) <= - (IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ^ - 12'h800) ; - assign _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633 = - ({ 6'd0, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 } ^ - 12'h800) <= - (IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 = - ({ 6'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 = - ({ 6'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 = - ({ 6'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 = - ({ 6'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 = - ({ 6'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 = - ({ 6'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ^ - 12'h800) ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 = - ({ 3'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 = - ({ 3'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^ - 9'h100) <= - (IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ^ - 9'h100) ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688 = - { 3'd0, - _theResult___fst_exp__h286342 == 8'd0 && - guard__h278294 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h286865 == 8'd255 && - _theResult___fst_sfd__h286866 == 23'd0, - 1'd0, - _theResult___fst_exp__h286342 != 8'd255 && - guard__h278294 != 2'b0 } ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813 = - sfd__h183176 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330 = - sfd__h144536 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038 = - sfd__h222115 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ; - assign _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038 = - sfd__h261975 >> - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 = - 12'd3074 - - { 6'd0, - resWire$wget[56] ? - 6'd0 : - (resWire$wget[55] ? - 6'd1 : - (resWire$wget[54] ? - 6'd2 : - (resWire$wget[53] ? - 6'd3 : - (resWire$wget[52] ? - 6'd4 : - (resWire$wget[51] ? - 6'd5 : - (resWire$wget[50] ? - 6'd6 : - (resWire$wget[49] ? - 6'd7 : - (resWire$wget[48] ? - 6'd8 : - (resWire$wget[47] ? - 6'd9 : - (resWire$wget[46] ? - 6'd10 : - (resWire$wget[45] ? - 6'd11 : - (resWire$wget[44] ? - 6'd12 : - (resWire$wget[43] ? - 6'd13 : - (resWire$wget[42] ? - 6'd14 : - (resWire$wget[41] ? - 6'd15 : - (resWire$wget[40] ? - 6'd16 : - (resWire$wget[39] ? - 6'd17 : - (resWire$wget[38] ? - 6'd18 : - (resWire$wget[37] ? - 6'd19 : - (resWire$wget[36] ? - 6'd20 : - (resWire$wget[35] ? - 6'd21 : - (resWire$wget[34] ? - 6'd22 : - (resWire$wget[33] ? - 6'd23 : - (resWire$wget[32] ? - 6'd24 : - (resWire$wget[31] ? - 6'd25 : - (resWire$wget[30] ? - 6'd26 : - (resWire$wget[29] ? - 6'd27 : - (resWire$wget[28] ? - 6'd28 : - (resWire$wget[27] ? - 6'd29 : - (resWire$wget[26] ? - 6'd30 : - (resWire$wget[25] ? - 6'd31 : - (resWire$wget[24] ? - 6'd32 : - (resWire$wget[23] ? - 6'd33 : - (resWire$wget[22] ? - 6'd34 : - (resWire$wget[21] ? - 6'd35 : - (resWire$wget[20] ? - 6'd36 : - (resWire$wget[19] ? - 6'd37 : - (resWire$wget[18] ? - 6'd38 : - (resWire$wget[17] ? - 6'd39 : - (resWire$wget[16] ? - 6'd40 : - (resWire$wget[15] ? - 6'd41 : - (resWire$wget[14] ? - 6'd42 : - (resWire$wget[13] ? - 6'd43 : - (resWire$wget[12] ? - 6'd44 : - (resWire$wget[11] ? - 6'd45 : - (resWire$wget[10] ? - 6'd46 : - (resWire$wget[9] ? - 6'd47 : - (resWire$wget[8] ? - 6'd48 : - (resWire$wget[7] ? - 6'd49 : - (resWire$wget[6] ? - 6'd50 : - (resWire$wget[5] ? - 6'd51 : - 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 = - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^ - 12'h800) <= - 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 = - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^ - 12'h800) < - 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[4] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[4]) ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[3] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[3]) ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[1] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[1]) ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[159] ? - 5'd0 : - (iFifo$D_OUT[158] ? - 5'd1 : - (iFifo$D_OUT[157] ? - 5'd2 : - (iFifo$D_OUT[156] ? - 5'd3 : - (iFifo$D_OUT[155] ? - 5'd4 : - (iFifo$D_OUT[154] ? - 5'd5 : - (iFifo$D_OUT[153] ? - 5'd6 : - (iFifo$D_OUT[152] ? - 5'd7 : - (iFifo$D_OUT[151] ? - 5'd8 : - (iFifo$D_OUT[150] ? - 5'd9 : - (iFifo$D_OUT[149] ? - 5'd10 : - (iFifo$D_OUT[148] ? - 5'd11 : - (iFifo$D_OUT[147] ? - 5'd12 : - (iFifo$D_OUT[146] ? - 5'd13 : - (iFifo$D_OUT[145] ? - 5'd14 : - (iFifo$D_OUT[144] ? - 5'd15 : - (iFifo$D_OUT[143] ? - 5'd16 : - (iFifo$D_OUT[142] ? - 5'd17 : - (iFifo$D_OUT[141] ? - 5'd18 : - (iFifo$D_OUT[140] ? - 5'd19 : - (iFifo$D_OUT[139] ? - 5'd20 : - (iFifo$D_OUT[138] ? - 5'd21 : - (iFifo$D_OUT[137] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[29] ? - 5'd0 : - (iFifo$D_OUT[28] ? - 5'd1 : - (iFifo$D_OUT[27] ? - 5'd2 : - (iFifo$D_OUT[26] ? - 5'd3 : - (iFifo$D_OUT[25] ? - 5'd4 : - (iFifo$D_OUT[24] ? - 5'd5 : - (iFifo$D_OUT[23] ? - 5'd6 : - (iFifo$D_OUT[22] ? - 5'd7 : - (iFifo$D_OUT[21] ? - 5'd8 : - (iFifo$D_OUT[20] ? - 5'd9 : - (iFifo$D_OUT[19] ? - 5'd10 : - (iFifo$D_OUT[18] ? - 5'd11 : - (iFifo$D_OUT[17] ? - 5'd12 : - (iFifo$D_OUT[16] ? - 5'd13 : - (iFifo$D_OUT[15] ? - 5'd14 : - (iFifo$D_OUT[14] ? - 5'd15 : - (iFifo$D_OUT[13] ? - 5'd16 : - (iFifo$D_OUT[12] ? - 5'd17 : - (iFifo$D_OUT[11] ? - 5'd18 : - (iFifo$D_OUT[10] ? - 5'd19 : - (iFifo$D_OUT[9] ? - 5'd20 : - (iFifo$D_OUT[8] ? - 5'd21 : - (iFifo$D_OUT[7] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[94] ? - 5'd0 : - (iFifo$D_OUT[93] ? - 5'd1 : - (iFifo$D_OUT[92] ? - 5'd2 : - (iFifo$D_OUT[91] ? - 5'd3 : - (iFifo$D_OUT[90] ? - 5'd4 : - (iFifo$D_OUT[89] ? - 5'd5 : - (iFifo$D_OUT[88] ? - 5'd6 : - (iFifo$D_OUT[87] ? - 5'd7 : - (iFifo$D_OUT[86] ? - 5'd8 : - (iFifo$D_OUT[85] ? - 5'd9 : - (iFifo$D_OUT[84] ? - 5'd10 : - (iFifo$D_OUT[83] ? - 5'd11 : - (iFifo$D_OUT[82] ? - 5'd12 : - (iFifo$D_OUT[81] ? - 5'd13 : - (iFifo$D_OUT[80] ? - 5'd14 : - (iFifo$D_OUT[79] ? - 5'd15 : - (iFifo$D_OUT[78] ? - 5'd16 : - (iFifo$D_OUT[77] ? - 5'd17 : - (iFifo$D_OUT[76] ? - 5'd18 : - (iFifo$D_OUT[75] ? - 5'd19 : - (iFifo$D_OUT[74] ? - 5'd20 : - (iFifo$D_OUT[73] ? - 5'd21 : - (iFifo$D_OUT[72] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 = - 12'd3970 - - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ; - assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 = - 13'd7170 - fpu_madd_fState_S3$D_OUT[12:0] ; - assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 = - (_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ^ - 13'h1000) <= - 13'd4096 ; - assign _theResult____h164614 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ^ - 12'h800) < - 12'd2105) ? - result__h165227 : - ((value__h148923 == 25'd0) ? sfd__h144536 : 57'd1) ; - assign _theResult____h203252 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ^ - 12'h800) < - 12'd2105) ? - result__h203865 : - ((value__h187561 == 25'd0) ? sfd__h183176 : 57'd1) ; - assign _theResult____h242191 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ^ - 12'h800) < - 12'd2105) ? - result__h242804 : - ((value__h226500 == 25'd0) ? sfd__h222115 : 57'd1) ; - assign _theResult____h269577 = - (value__h270197 == 54'd0) ? sfd__h261975 : 57'd1 ; - assign _theResult____h287214 = - ((_3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ^ - 12'h800) < - 12'd2105) ? - result__h287827 : - _theResult____h269577 ; - assign _theResult____h32523 = - (fpu_div64_fState_S2$D_OUT[10:0] < 11'd58) ? - result__h32648 : - result__h32823 ; - assign _theResult___exp__h142541 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h142626) : - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 ; - assign _theResult___exp__h163981 = - sfd__h163354[53] ? - ((_theResult___fst_exp__h163336 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182469) : - ((_theResult___fst_exp__h163336 == 11'd0 && - sfd__h163354[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h163336) ; - assign _theResult___exp__h173571 = - sfd__h172944[53] ? - ((_theResult___fst_exp__h172852 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182504) : - ((_theResult___fst_exp__h172852 == 11'd0 && - sfd__h172944[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h172852) ; - assign _theResult___exp__h182323 = - sfd__h181672[53] ? - ((_theResult___fst_exp__h181653 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182530) : - ((_theResult___fst_exp__h181653 == 11'd0 && - sfd__h181672[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h181653) ; - assign _theResult___exp__h202619 = - sfd__h201992[53] ? - ((_theResult___fst_exp__h201974 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221107) : - ((_theResult___fst_exp__h201974 == 11'd0 && - sfd__h201992[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h201974) ; - assign _theResult___exp__h212209 = - sfd__h211582[53] ? - ((_theResult___fst_exp__h211490 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221142) : - ((_theResult___fst_exp__h211490 == 11'd0 && - sfd__h211582[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h211490) ; - assign _theResult___exp__h220961 = - sfd__h220310[53] ? - ((_theResult___fst_exp__h220291 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221168) : - ((_theResult___fst_exp__h220291 == 11'd0 && - sfd__h220310[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h220291) ; - assign _theResult___exp__h241558 = - sfd__h240931[53] ? - ((_theResult___fst_exp__h240913 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260046) : - ((_theResult___fst_exp__h240913 == 11'd0 && - sfd__h240931[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h240913) ; - assign _theResult___exp__h251148 = - sfd__h250521[53] ? - ((_theResult___fst_exp__h250429 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260081) : - ((_theResult___fst_exp__h250429 == 11'd0 && - sfd__h250521[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h250429) ; - assign _theResult___exp__h259900 = - sfd__h259249[53] ? - ((_theResult___fst_exp__h259230 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260107) : - ((_theResult___fst_exp__h259230 == 11'd0 && - sfd__h259249[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h259230) ; - assign _theResult___exp__h278202 = - sfd__h277778[24] ? - ((_theResult___fst_exp__h277686 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304723) : - ((_theResult___fst_exp__h277686 == 8'd0 && - sfd__h277778[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h277686) ; - assign _theResult___exp__h286784 = - sfd__h286360[24] ? - ((_theResult___fst_exp__h286342 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304749) : - ((_theResult___fst_exp__h286342 == 8'd0 && - sfd__h286360[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h286342) ; - assign _theResult___exp__h295968 = - sfd__h295544[24] ? - ((_theResult___fst_exp__h295452 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304784) : - ((_theResult___fst_exp__h295452 == 8'd0 && - sfd__h295544[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h295452) ; - assign _theResult___exp__h304604 = - sfd__h304156[24] ? - ((_theResult___fst_exp__h304137 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304810) : - ((_theResult___fst_exp__h304137 == 8'd0 && - sfd__h304156[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h304137) ; - assign _theResult___exp__h43475 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h43566) : - IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977 ; - assign _theResult___exp__h95909 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h96000) : - IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721 ; - assign _theResult___fst__h116827 = - { fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[105:1], - fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[0] | - sfdlsb__h116825 } ; - assign _theResult___fst__h1476 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___fst__h1600 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign _theResult___fst__h1515 = - (rg_res[116] || rg_b == 116'd0) ? rg_b : b__h1608 ; - assign _theResult___fst__h1600 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 : - b__h1712 ; - assign _theResult___fst__h31322 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499 ? - value__h31550[10:0] : - 11'd0 ; - assign _theResult___fst_exp__h130949 = - sfdBC__h115662[105] ? - _theResult___fst_exp__h130971 : - _theResult___fst_exp__h131034 ; - assign _theResult___fst_exp__h130952 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h130949 ; - assign _theResult___fst_exp__h130971 = - (din_exp__h130866 == 11'd0) ? 11'd2 : din_exp__h130866 + 11'd1 ; - assign _theResult___fst_exp__h130986 = - (din_exp__h130866 == 11'd0) ? 11'd1 : din_exp__h130866 ; - assign _theResult___fst_exp__h131025 = - din_exp__h130866 - - { 4'd0, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ; - assign _theResult___fst_exp__h131031 = - (!sfdBC__h115662[105] && !sfdBC__h115662[104] && - !sfdBC__h115662[103] && - !sfdBC__h115662[102] && - !sfdBC__h115662[101] && - !sfdBC__h115662[100] && - !sfdBC__h115662[99] && - !sfdBC__h115662[98] && - !sfdBC__h115662[97] && - !sfdBC__h115662[96] && - !sfdBC__h115662[95] && - !sfdBC__h115662[94] && - !sfdBC__h115662[93] && - !sfdBC__h115662[92] && - !sfdBC__h115662[91] && - !sfdBC__h115662[90] && - !sfdBC__h115662[89] && - !sfdBC__h115662[88] && - !sfdBC__h115662[87] && - !sfdBC__h115662[86] && - !sfdBC__h115662[85] && - !sfdBC__h115662[84] && - !sfdBC__h115662[83] && - !sfdBC__h115662[82] && - !sfdBC__h115662[81] && - !sfdBC__h115662[80] && - !sfdBC__h115662[79] && - !sfdBC__h115662[78] && - !sfdBC__h115662[77] && - !sfdBC__h115662[76] && - !sfdBC__h115662[75] && - !sfdBC__h115662[74] && - !sfdBC__h115662[73] && - !sfdBC__h115662[72] && - !sfdBC__h115662[71] && - !sfdBC__h115662[70] && - !sfdBC__h115662[69] && - !sfdBC__h115662[68] && - !sfdBC__h115662[67] && - !sfdBC__h115662[66] && - !sfdBC__h115662[65] && - !sfdBC__h115662[64] && - !sfdBC__h115662[63] && - !sfdBC__h115662[62] && - !sfdBC__h115662[61] && - !sfdBC__h115662[60] && - !sfdBC__h115662[59] && - !sfdBC__h115662[58] && - !sfdBC__h115662[57] && - !sfdBC__h115662[56] && - !sfdBC__h115662[55] && - !sfdBC__h115662[54] && - !sfdBC__h115662[53] && - !sfdBC__h115662[52] && - !sfdBC__h115662[51] && - !sfdBC__h115662[50] && - !sfdBC__h115662[49] && - !sfdBC__h115662[48] && - !sfdBC__h115662[47] && - !sfdBC__h115662[46] && - !sfdBC__h115662[45] && - !sfdBC__h115662[44] && - !sfdBC__h115662[43] && - !sfdBC__h115662[42] && - !sfdBC__h115662[41] && - !sfdBC__h115662[40] && - !sfdBC__h115662[39] && - !sfdBC__h115662[38] && - !sfdBC__h115662[37] && - !sfdBC__h115662[36] && - !sfdBC__h115662[35] && - !sfdBC__h115662[34] && - !sfdBC__h115662[33] && - !sfdBC__h115662[32] && - !sfdBC__h115662[31] && - !sfdBC__h115662[30] && - !sfdBC__h115662[29] && - !sfdBC__h115662[28] && - !sfdBC__h115662[27] && - !sfdBC__h115662[26] && - !sfdBC__h115662[25] && - !sfdBC__h115662[24] && - !sfdBC__h115662[23] && - !sfdBC__h115662[22] && - !sfdBC__h115662[21] && - !sfdBC__h115662[20] && - !sfdBC__h115662[19] && - !sfdBC__h115662[18] && - !sfdBC__h115662[17] && - !sfdBC__h115662[16] && - !sfdBC__h115662[15] && - !sfdBC__h115662[14] && - !sfdBC__h115662[13] && - !sfdBC__h115662[12] && - !sfdBC__h115662[11] && - !sfdBC__h115662[10] && - !sfdBC__h115662[9] && - !sfdBC__h115662[8] && - !sfdBC__h115662[7] && - !sfdBC__h115662[6] && - !sfdBC__h115662[5] && - !sfdBC__h115662[4] && - !sfdBC__h115662[3] && - !sfdBC__h115662[2] && - !sfdBC__h115662[1] && - !sfdBC__h115662[0] || - !_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463) ? - 11'd0 : - _theResult___fst_exp__h131025 ; - assign _theResult___fst_exp__h131034 = - (!sfdBC__h115662[105] && sfdBC__h115662[104]) ? - _theResult___fst_exp__h130986 : - _theResult___fst_exp__h131031 ; - assign _theResult___fst_exp__h141375 = - sfd__h133119[56] ? - _theResult___fst_exp__h141397 : - _theResult___fst_exp__h141460 ; - assign _theResult___fst_exp__h141378 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h141375 ; - assign _theResult___fst_exp__h141397 = - (value__h141307[10:0] == 11'd0) ? - 11'd2 : - value__h141307[10:0] + 11'd1 ; - assign _theResult___fst_exp__h141412 = - (value__h141307[10:0] == 11'd0) ? 11'd1 : value__h141307[10:0] ; - assign _theResult___fst_exp__h141451 = - value__h141307[10:0] - - { 5'd0, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ; - assign _theResult___fst_exp__h141457 = - (!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] && - !sfd__h133119[53] && - !sfd__h133119[52] && - !sfd__h133119[51] && - !sfd__h133119[50] && - !sfd__h133119[49] && - !sfd__h133119[48] && - !sfd__h133119[47] && - !sfd__h133119[46] && - !sfd__h133119[45] && - !sfd__h133119[44] && - !sfd__h133119[43] && - !sfd__h133119[42] && - !sfd__h133119[41] && - !sfd__h133119[40] && - !sfd__h133119[39] && - !sfd__h133119[38] && - !sfd__h133119[37] && - !sfd__h133119[36] && - !sfd__h133119[35] && - !sfd__h133119[34] && - !sfd__h133119[33] && - !sfd__h133119[32] && - !sfd__h133119[31] && - !sfd__h133119[30] && - !sfd__h133119[29] && - !sfd__h133119[28] && - !sfd__h133119[27] && - !sfd__h133119[26] && - !sfd__h133119[25] && - !sfd__h133119[24] && - !sfd__h133119[23] && - !sfd__h133119[22] && - !sfd__h133119[21] && - !sfd__h133119[20] && - !sfd__h133119[19] && - !sfd__h133119[18] && - !sfd__h133119[17] && - !sfd__h133119[16] && - !sfd__h133119[15] && - !sfd__h133119[14] && - !sfd__h133119[13] && - !sfd__h133119[12] && - !sfd__h133119[11] && - !sfd__h133119[10] && - !sfd__h133119[9] && - !sfd__h133119[8] && - !sfd__h133119[7] && - !sfd__h133119[6] && - !sfd__h133119[5] && - !sfd__h133119[4] && - !sfd__h133119[3] && - !sfd__h133119[2] && - !sfd__h133119[1] && - !sfd__h133119[0] || - !_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904) ? - 11'd0 : - _theResult___fst_exp__h141451 ; - assign _theResult___fst_exp__h141460 = - (!sfd__h133119[56] && sfd__h133119[55]) ? - _theResult___fst_exp__h141412 : - _theResult___fst_exp__h141457 ; - assign _theResult___fst_exp__h163327 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ; - assign _theResult___fst_exp__h163333 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 || - !_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273) ? - 11'd0 : - _theResult___fst_exp__h163327 ; - assign _theResult___fst_exp__h163336 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___fst_exp__h163333 : - 11'd897 ; - assign _theResult___fst_exp__h164062 = - (_theResult___fst_exp__h163336 == 11'd2047) ? - _theResult___fst_exp__h163336 : - _theResult___fst_exp__h164059 ; - assign _theResult___fst_exp__h172852 = - _theResult____h164614[56] ? - 11'd2 : - _theResult___fst_exp__h172926 ; - assign _theResult___fst_exp__h172917 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ; - assign _theResult___fst_exp__h172923 = - (!_theResult____h164614[56] && !_theResult____h164614[55] && - !_theResult____h164614[54] && - !_theResult____h164614[53] && - !_theResult____h164614[52] && - !_theResult____h164614[51] && - !_theResult____h164614[50] && - !_theResult____h164614[49] && - !_theResult____h164614[48] && - !_theResult____h164614[47] && - !_theResult____h164614[46] && - !_theResult____h164614[45] && - !_theResult____h164614[44] && - !_theResult____h164614[43] && - !_theResult____h164614[42] && - !_theResult____h164614[41] && - !_theResult____h164614[40] && - !_theResult____h164614[39] && - !_theResult____h164614[38] && - !_theResult____h164614[37] && - !_theResult____h164614[36] && - !_theResult____h164614[35] && - !_theResult____h164614[34] && - !_theResult____h164614[33] && - !_theResult____h164614[32] && - !_theResult____h164614[31] && - !_theResult____h164614[30] && - !_theResult____h164614[29] && - !_theResult____h164614[28] && - !_theResult____h164614[27] && - !_theResult____h164614[26] && - !_theResult____h164614[25] && - !_theResult____h164614[24] && - !_theResult____h164614[23] && - !_theResult____h164614[22] && - !_theResult____h164614[21] && - !_theResult____h164614[20] && - !_theResult____h164614[19] && - !_theResult____h164614[18] && - !_theResult____h164614[17] && - !_theResult____h164614[16] && - !_theResult____h164614[15] && - !_theResult____h164614[14] && - !_theResult____h164614[13] && - !_theResult____h164614[12] && - !_theResult____h164614[11] && - !_theResult____h164614[10] && - !_theResult____h164614[9] && - !_theResult____h164614[8] && - !_theResult____h164614[7] && - !_theResult____h164614[6] && - !_theResult____h164614[5] && - !_theResult____h164614[4] && - !_theResult____h164614[3] && - !_theResult____h164614[2] && - !_theResult____h164614[1] && - !_theResult____h164614[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574) ? - 11'd0 : - _theResult___fst_exp__h172917 ; - assign _theResult___fst_exp__h172926 = - (!_theResult____h164614[56] && _theResult____h164614[55]) ? - 11'd1 : - _theResult___fst_exp__h172923 ; - assign _theResult___fst_exp__h173652 = - (_theResult___fst_exp__h172852 == 11'd2047) ? - _theResult___fst_exp__h172852 : - _theResult___fst_exp__h173649 ; - assign _theResult___fst_exp__h181605 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] ; - assign _theResult___fst_exp__h181644 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ; - assign _theResult___fst_exp__h181650 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 || - !_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624) ? - 11'd0 : - _theResult___fst_exp__h181644 ; - assign _theResult___fst_exp__h181653 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___fst_exp__h181650 : - _theResult___fst_exp__h181605 ; - assign _theResult___fst_exp__h182404 = - (_theResult___fst_exp__h181653 == 11'd2047) ? - _theResult___fst_exp__h181653 : - _theResult___fst_exp__h182401 ; - assign _theResult___fst_exp__h182413 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - _theResult___snd_fst_exp__h164065 : - _theResult___fst_exp__h148291) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - _theResult___snd_fst_exp__h182407 : - _theResult___fst_exp__h148291) ; - assign _theResult___fst_exp__h182416 = - (iFifo$D_OUT[167:160] == 8'd0 && iFifo$D_OUT[159:137] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h182413 ; - assign _theResult___fst_exp__h201965 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ; - assign _theResult___fst_exp__h201971 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 || - !_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759) ? - 11'd0 : - _theResult___fst_exp__h201965 ; - assign _theResult___fst_exp__h201974 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___fst_exp__h201971 : - 11'd897 ; - assign _theResult___fst_exp__h202700 = - (_theResult___fst_exp__h201974 == 11'd2047) ? - _theResult___fst_exp__h201974 : - _theResult___fst_exp__h202697 ; - assign _theResult___fst_exp__h211490 = - _theResult____h203252[56] ? - 11'd2 : - _theResult___fst_exp__h211564 ; - assign _theResult___fst_exp__h211555 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ; - assign _theResult___fst_exp__h211561 = - (!_theResult____h203252[56] && !_theResult____h203252[55] && - !_theResult____h203252[54] && - !_theResult____h203252[53] && - !_theResult____h203252[52] && - !_theResult____h203252[51] && - !_theResult____h203252[50] && - !_theResult____h203252[49] && - !_theResult____h203252[48] && - !_theResult____h203252[47] && - !_theResult____h203252[46] && - !_theResult____h203252[45] && - !_theResult____h203252[44] && - !_theResult____h203252[43] && - !_theResult____h203252[42] && - !_theResult____h203252[41] && - !_theResult____h203252[40] && - !_theResult____h203252[39] && - !_theResult____h203252[38] && - !_theResult____h203252[37] && - !_theResult____h203252[36] && - !_theResult____h203252[35] && - !_theResult____h203252[34] && - !_theResult____h203252[33] && - !_theResult____h203252[32] && - !_theResult____h203252[31] && - !_theResult____h203252[30] && - !_theResult____h203252[29] && - !_theResult____h203252[28] && - !_theResult____h203252[27] && - !_theResult____h203252[26] && - !_theResult____h203252[25] && - !_theResult____h203252[24] && - !_theResult____h203252[23] && - !_theResult____h203252[22] && - !_theResult____h203252[21] && - !_theResult____h203252[20] && - !_theResult____h203252[19] && - !_theResult____h203252[18] && - !_theResult____h203252[17] && - !_theResult____h203252[16] && - !_theResult____h203252[15] && - !_theResult____h203252[14] && - !_theResult____h203252[13] && - !_theResult____h203252[12] && - !_theResult____h203252[11] && - !_theResult____h203252[10] && - !_theResult____h203252[9] && - !_theResult____h203252[8] && - !_theResult____h203252[7] && - !_theResult____h203252[6] && - !_theResult____h203252[5] && - !_theResult____h203252[4] && - !_theResult____h203252[3] && - !_theResult____h203252[2] && - !_theResult____h203252[1] && - !_theResult____h203252[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057) ? - 11'd0 : - _theResult___fst_exp__h211555 ; - assign _theResult___fst_exp__h211564 = - (!_theResult____h203252[56] && _theResult____h203252[55]) ? - 11'd1 : - _theResult___fst_exp__h211561 ; - assign _theResult___fst_exp__h212290 = - (_theResult___fst_exp__h211490 == 11'd2047) ? - _theResult___fst_exp__h211490 : - _theResult___fst_exp__h212287 ; - assign _theResult___fst_exp__h220243 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] ; - assign _theResult___fst_exp__h220282 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ; - assign _theResult___fst_exp__h220288 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 || - !_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107) ? - 11'd0 : - _theResult___fst_exp__h220282 ; - assign _theResult___fst_exp__h220291 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___fst_exp__h220288 : - _theResult___fst_exp__h220243 ; - assign _theResult___fst_exp__h221042 = - (_theResult___fst_exp__h220291 == 11'd2047) ? - _theResult___fst_exp__h220291 : - _theResult___fst_exp__h221039 ; - assign _theResult___fst_exp__h221051 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - _theResult___snd_fst_exp__h202703 : - _theResult___fst_exp__h186931) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - _theResult___snd_fst_exp__h221045 : - _theResult___fst_exp__h186931) ; - assign _theResult___fst_exp__h221054 = - (iFifo$D_OUT[102:95] == 8'd0 && iFifo$D_OUT[94:72] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h221051 ; - assign _theResult___fst_exp__h240904 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ; - assign _theResult___fst_exp__h240910 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 || - !_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984) ? - 11'd0 : - _theResult___fst_exp__h240904 ; - assign _theResult___fst_exp__h240913 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___fst_exp__h240910 : - 11'd897 ; - assign _theResult___fst_exp__h241639 = - (_theResult___fst_exp__h240913 == 11'd2047) ? - _theResult___fst_exp__h240913 : - _theResult___fst_exp__h241636 ; - assign _theResult___fst_exp__h250429 = - _theResult____h242191[56] ? - 11'd2 : - _theResult___fst_exp__h250503 ; - assign _theResult___fst_exp__h250494 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ; - assign _theResult___fst_exp__h250500 = - (!_theResult____h242191[56] && !_theResult____h242191[55] && - !_theResult____h242191[54] && - !_theResult____h242191[53] && - !_theResult____h242191[52] && - !_theResult____h242191[51] && - !_theResult____h242191[50] && - !_theResult____h242191[49] && - !_theResult____h242191[48] && - !_theResult____h242191[47] && - !_theResult____h242191[46] && - !_theResult____h242191[45] && - !_theResult____h242191[44] && - !_theResult____h242191[43] && - !_theResult____h242191[42] && - !_theResult____h242191[41] && - !_theResult____h242191[40] && - !_theResult____h242191[39] && - !_theResult____h242191[38] && - !_theResult____h242191[37] && - !_theResult____h242191[36] && - !_theResult____h242191[35] && - !_theResult____h242191[34] && - !_theResult____h242191[33] && - !_theResult____h242191[32] && - !_theResult____h242191[31] && - !_theResult____h242191[30] && - !_theResult____h242191[29] && - !_theResult____h242191[28] && - !_theResult____h242191[27] && - !_theResult____h242191[26] && - !_theResult____h242191[25] && - !_theResult____h242191[24] && - !_theResult____h242191[23] && - !_theResult____h242191[22] && - !_theResult____h242191[21] && - !_theResult____h242191[20] && - !_theResult____h242191[19] && - !_theResult____h242191[18] && - !_theResult____h242191[17] && - !_theResult____h242191[16] && - !_theResult____h242191[15] && - !_theResult____h242191[14] && - !_theResult____h242191[13] && - !_theResult____h242191[12] && - !_theResult____h242191[11] && - !_theResult____h242191[10] && - !_theResult____h242191[9] && - !_theResult____h242191[8] && - !_theResult____h242191[7] && - !_theResult____h242191[6] && - !_theResult____h242191[5] && - !_theResult____h242191[4] && - !_theResult____h242191[3] && - !_theResult____h242191[2] && - !_theResult____h242191[1] && - !_theResult____h242191[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282) ? - 11'd0 : - _theResult___fst_exp__h250494 ; - assign _theResult___fst_exp__h250503 = - (!_theResult____h242191[56] && _theResult____h242191[55]) ? - 11'd1 : - _theResult___fst_exp__h250500 ; - assign _theResult___fst_exp__h251229 = - (_theResult___fst_exp__h250429 == 11'd2047) ? - _theResult___fst_exp__h250429 : - _theResult___fst_exp__h251226 ; - assign _theResult___fst_exp__h259182 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] ; - assign _theResult___fst_exp__h259221 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ; - assign _theResult___fst_exp__h259227 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 || - !_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332) ? - 11'd0 : - _theResult___fst_exp__h259221 ; - assign _theResult___fst_exp__h259230 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___fst_exp__h259227 : - _theResult___fst_exp__h259182 ; - assign _theResult___fst_exp__h259981 = - (_theResult___fst_exp__h259230 == 11'd2047) ? - _theResult___fst_exp__h259230 : - _theResult___fst_exp__h259978 ; - assign _theResult___fst_exp__h259990 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - _theResult___snd_fst_exp__h241642 : - _theResult___fst_exp__h225870) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - _theResult___snd_fst_exp__h259984 : - _theResult___fst_exp__h225870) ; - assign _theResult___fst_exp__h259993 = - (iFifo$D_OUT[37:30] == 8'd0 && iFifo$D_OUT[29:7] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h259990 ; - assign _theResult___fst_exp__h277686 = - _theResult____h269577[56] ? - 8'd2 : - _theResult___fst_exp__h277760 ; - assign _theResult___fst_exp__h277751 = - 8'd0 - - { 2'd0, - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ; - assign _theResult___fst_exp__h277757 = - (!_theResult____h269577[56] && !_theResult____h269577[55] && - !_theResult____h269577[54] && - !_theResult____h269577[53] && - !_theResult____h269577[52] && - !_theResult____h269577[51] && - !_theResult____h269577[50] && - !_theResult____h269577[49] && - !_theResult____h269577[48] && - !_theResult____h269577[47] && - !_theResult____h269577[46] && - !_theResult____h269577[45] && - !_theResult____h269577[44] && - !_theResult____h269577[43] && - !_theResult____h269577[42] && - !_theResult____h269577[41] && - !_theResult____h269577[40] && - !_theResult____h269577[39] && - !_theResult____h269577[38] && - !_theResult____h269577[37] && - !_theResult____h269577[36] && - !_theResult____h269577[35] && - !_theResult____h269577[34] && - !_theResult____h269577[33] && - !_theResult____h269577[32] && - !_theResult____h269577[31] && - !_theResult____h269577[30] && - !_theResult____h269577[29] && - !_theResult____h269577[28] && - !_theResult____h269577[27] && - !_theResult____h269577[26] && - !_theResult____h269577[25] && - !_theResult____h269577[24] && - !_theResult____h269577[23] && - !_theResult____h269577[22] && - !_theResult____h269577[21] && - !_theResult____h269577[20] && - !_theResult____h269577[19] && - !_theResult____h269577[18] && - !_theResult____h269577[17] && - !_theResult____h269577[16] && - !_theResult____h269577[15] && - !_theResult____h269577[14] && - !_theResult____h269577[13] && - !_theResult____h269577[12] && - !_theResult____h269577[11] && - !_theResult____h269577[10] && - !_theResult____h269577[9] && - !_theResult____h269577[8] && - !_theResult____h269577[7] && - !_theResult____h269577[6] && - !_theResult____h269577[5] && - !_theResult____h269577[4] && - !_theResult____h269577[3] && - !_theResult____h269577[2] && - !_theResult____h269577[1] && - !_theResult____h269577[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769) ? - 8'd0 : - _theResult___fst_exp__h277751 ; - assign _theResult___fst_exp__h277760 = - (!_theResult____h269577[56] && _theResult____h269577[55]) ? - 8'd1 : - _theResult___fst_exp__h277757 ; - assign _theResult___fst_exp__h278283 = - (_theResult___fst_exp__h277686 == 8'd255) ? - _theResult___fst_exp__h277686 : - _theResult___fst_exp__h278280 ; - assign _theResult___fst_exp__h286333 = - 8'd129 - - { 2'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ; - assign _theResult___fst_exp__h286339 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 || - !_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984) ? - 8'd0 : - _theResult___fst_exp__h286333 ; - assign _theResult___fst_exp__h286342 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___fst_exp__h286339 : - 8'd129 ; - assign _theResult___fst_exp__h286865 = - (_theResult___fst_exp__h286342 == 8'd255) ? - _theResult___fst_exp__h286342 : - _theResult___fst_exp__h286862 ; - assign _theResult___fst_exp__h295452 = - _theResult____h287214[56] ? - 8'd2 : - _theResult___fst_exp__h295526 ; - assign _theResult___fst_exp__h295517 = - 8'd0 - - { 2'd0, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ; - assign _theResult___fst_exp__h295523 = - (!_theResult____h287214[56] && !_theResult____h287214[55] && - !_theResult____h287214[54] && - !_theResult____h287214[53] && - !_theResult____h287214[52] && - !_theResult____h287214[51] && - !_theResult____h287214[50] && - !_theResult____h287214[49] && - !_theResult____h287214[48] && - !_theResult____h287214[47] && - !_theResult____h287214[46] && - !_theResult____h287214[45] && - !_theResult____h287214[44] && - !_theResult____h287214[43] && - !_theResult____h287214[42] && - !_theResult____h287214[41] && - !_theResult____h287214[40] && - !_theResult____h287214[39] && - !_theResult____h287214[38] && - !_theResult____h287214[37] && - !_theResult____h287214[36] && - !_theResult____h287214[35] && - !_theResult____h287214[34] && - !_theResult____h287214[33] && - !_theResult____h287214[32] && - !_theResult____h287214[31] && - !_theResult____h287214[30] && - !_theResult____h287214[29] && - !_theResult____h287214[28] && - !_theResult____h287214[27] && - !_theResult____h287214[26] && - !_theResult____h287214[25] && - !_theResult____h287214[24] && - !_theResult____h287214[23] && - !_theResult____h287214[22] && - !_theResult____h287214[21] && - !_theResult____h287214[20] && - !_theResult____h287214[19] && - !_theResult____h287214[18] && - !_theResult____h287214[17] && - !_theResult____h287214[16] && - !_theResult____h287214[15] && - !_theResult____h287214[14] && - !_theResult____h287214[13] && - !_theResult____h287214[12] && - !_theResult____h287214[11] && - !_theResult____h287214[10] && - !_theResult____h287214[9] && - !_theResult____h287214[8] && - !_theResult____h287214[7] && - !_theResult____h287214[6] && - !_theResult____h287214[5] && - !_theResult____h287214[4] && - !_theResult____h287214[3] && - !_theResult____h287214[2] && - !_theResult____h287214[1] && - !_theResult____h287214[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280) ? - 8'd0 : - _theResult___fst_exp__h295517 ; - assign _theResult___fst_exp__h295526 = - (!_theResult____h287214[56] && _theResult____h287214[55]) ? - 8'd1 : - _theResult___fst_exp__h295523 ; - assign _theResult___fst_exp__h296049 = - (_theResult___fst_exp__h295452 == 8'd255) ? - _theResult___fst_exp__h295452 : - _theResult___fst_exp__h296046 ; - assign _theResult___fst_exp__h304089 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] == - 8'd0) ? - 8'd1 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] ; - assign _theResult___fst_exp__h304128 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] - - { 2'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ; - assign _theResult___fst_exp__h304134 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 || - !_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333) ? - 8'd0 : - _theResult___fst_exp__h304128 ; - assign _theResult___fst_exp__h304137 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___fst_exp__h304134 : - _theResult___fst_exp__h304089 ; - assign _theResult___fst_exp__h304685 = - (_theResult___fst_exp__h304137 == 8'd255) ? - _theResult___fst_exp__h304137 : - _theResult___fst_exp__h304682 ; - assign _theResult___fst_exp__h304694 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - _theResult___snd_fst_exp__h286868 : - _theResult___fst_exp__h269559) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - _theResult___snd_fst_exp__h304688 : - _theResult___fst_exp__h269559) ; - assign _theResult___fst_exp__h304697 = - (resWire$wget[67:57] == 11'd0 && resWire$wget[56:5] == 52'd0) ? - 8'd0 : - _theResult___fst_exp__h304694 ; - assign _theResult___fst_exp__h42284 = - fpu_div64_fState_S3$D_OUT[120:110] - 11'd1 ; - assign _theResult___fst_exp__h42287 = - (fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___fst_exp__h42284 : - 11'd2046 ; - assign _theResult___fst_exp__h42290 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___fst_exp__h42287 : - fpu_div64_fState_S3$D_OUT[120:110] ; - assign _theResult___fst_exp__h42333 = - sfdin__h34118[57] ? - _theResult___fst_exp__h42356 : - _theResult___fst_exp__h42420 ; - assign _theResult___fst_exp__h42336 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h42333 ; - assign _theResult___fst_exp__h42356 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 11'd2 : - _theResult___fst_exp__h42290 + 11'd1 ; - assign _theResult___fst_exp__h42372 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 11'd1 : - _theResult___fst_exp__h42290 ; - assign _theResult___fst_exp__h42411 = - _theResult___fst_exp__h42290 - - { 5'd0, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 } ; - assign _theResult___fst_exp__h42417 = - (!sfdin__h34118[57] && !sfdin__h34118[56] && - !sfdin__h34118[55] && - !sfdin__h34118[54] && - !sfdin__h34118[53] && - !sfdin__h34118[52] && - !sfdin__h34118[51] && - !sfdin__h34118[50] && - !sfdin__h34118[49] && - !sfdin__h34118[48] && - !sfdin__h34118[47] && - !sfdin__h34118[46] && - !sfdin__h34118[45] && - !sfdin__h34118[44] && - !sfdin__h34118[43] && - !sfdin__h34118[42] && - !sfdin__h34118[41] && - !sfdin__h34118[40] && - !sfdin__h34118[39] && - !sfdin__h34118[38] && - !sfdin__h34118[37] && - !sfdin__h34118[36] && - !sfdin__h34118[35] && - !sfdin__h34118[34] && - !sfdin__h34118[33] && - !sfdin__h34118[32] && - !sfdin__h34118[31] && - !sfdin__h34118[30] && - !sfdin__h34118[29] && - !sfdin__h34118[28] && - !sfdin__h34118[27] && - !sfdin__h34118[26] && - !sfdin__h34118[25] && - !sfdin__h34118[24] && - !sfdin__h34118[23] && - !sfdin__h34118[22] && - !sfdin__h34118[21] && - !sfdin__h34118[20] && - !sfdin__h34118[19] && - !sfdin__h34118[18] && - !sfdin__h34118[17] && - !sfdin__h34118[16] && - !sfdin__h34118[15] && - !sfdin__h34118[14] && - !sfdin__h34118[13] && - !sfdin__h34118[12] && - !sfdin__h34118[11] && - !sfdin__h34118[10] && - !sfdin__h34118[9] && - !sfdin__h34118[8] && - !sfdin__h34118[7] && - !sfdin__h34118[6] && - !sfdin__h34118[5] && - !sfdin__h34118[4] && - !sfdin__h34118[3] && - !sfdin__h34118[2] && - !sfdin__h34118[1] && - !sfdin__h34118[0] || - !_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883) ? - 11'd0 : - _theResult___fst_exp__h42411 ; - assign _theResult___fst_exp__h42420 = - (!sfdin__h34118[57] && sfdin__h34118[56]) ? - _theResult___fst_exp__h42372 : - _theResult___fst_exp__h42417 ; - assign _theResult___fst_exp__h43556 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h43553 ; - assign _theResult___fst_exp__h94750 = - fpu_sqr64_fState_S3$D_OUT[58] ? - _theResult___fst_exp__h94773 : - _theResult___fst_exp__h94837 ; - assign _theResult___fst_exp__h94753 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h94750 ; - assign _theResult___fst_exp__h94773 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd2 : - fpu_sqr64_fState_S3$D_OUT[121:111] + 11'd1 ; - assign _theResult___fst_exp__h94789 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd1 : - fpu_sqr64_fState_S3$D_OUT[121:111] ; - assign _theResult___fst_exp__h94828 = - fpu_sqr64_fState_S3$D_OUT[121:111] - - { 5'd0, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 } ; - assign _theResult___fst_exp__h94834 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - !fpu_sqr64_fState_S3$D_OUT[57] && - !fpu_sqr64_fState_S3$D_OUT[56] && - !fpu_sqr64_fState_S3$D_OUT[55] && - !fpu_sqr64_fState_S3$D_OUT[54] && - !fpu_sqr64_fState_S3$D_OUT[53] && - !fpu_sqr64_fState_S3$D_OUT[52] && - !fpu_sqr64_fState_S3$D_OUT[51] && - !fpu_sqr64_fState_S3$D_OUT[50] && - !fpu_sqr64_fState_S3$D_OUT[49] && - !fpu_sqr64_fState_S3$D_OUT[48] && - !fpu_sqr64_fState_S3$D_OUT[47] && - !fpu_sqr64_fState_S3$D_OUT[46] && - !fpu_sqr64_fState_S3$D_OUT[45] && - !fpu_sqr64_fState_S3$D_OUT[44] && - !fpu_sqr64_fState_S3$D_OUT[43] && - !fpu_sqr64_fState_S3$D_OUT[42] && - !fpu_sqr64_fState_S3$D_OUT[41] && - !fpu_sqr64_fState_S3$D_OUT[40] && - !fpu_sqr64_fState_S3$D_OUT[39] && - !fpu_sqr64_fState_S3$D_OUT[38] && - !fpu_sqr64_fState_S3$D_OUT[37] && - !fpu_sqr64_fState_S3$D_OUT[36] && - !fpu_sqr64_fState_S3$D_OUT[35] && - !fpu_sqr64_fState_S3$D_OUT[34] && - !fpu_sqr64_fState_S3$D_OUT[33] && - !fpu_sqr64_fState_S3$D_OUT[32] && - !fpu_sqr64_fState_S3$D_OUT[31] && - !fpu_sqr64_fState_S3$D_OUT[30] && - !fpu_sqr64_fState_S3$D_OUT[29] && - !fpu_sqr64_fState_S3$D_OUT[28] && - !fpu_sqr64_fState_S3$D_OUT[27] && - !fpu_sqr64_fState_S3$D_OUT[26] && - !fpu_sqr64_fState_S3$D_OUT[25] && - !fpu_sqr64_fState_S3$D_OUT[24] && - !fpu_sqr64_fState_S3$D_OUT[23] && - !fpu_sqr64_fState_S3$D_OUT[22] && - !fpu_sqr64_fState_S3$D_OUT[21] && - !fpu_sqr64_fState_S3$D_OUT[20] && - !fpu_sqr64_fState_S3$D_OUT[19] && - !fpu_sqr64_fState_S3$D_OUT[18] && - !fpu_sqr64_fState_S3$D_OUT[17] && - !fpu_sqr64_fState_S3$D_OUT[16] && - !fpu_sqr64_fState_S3$D_OUT[15] && - !fpu_sqr64_fState_S3$D_OUT[14] && - !fpu_sqr64_fState_S3$D_OUT[13] && - !fpu_sqr64_fState_S3$D_OUT[12] && - !fpu_sqr64_fState_S3$D_OUT[11] && - !fpu_sqr64_fState_S3$D_OUT[10] && - !fpu_sqr64_fState_S3$D_OUT[9] && - !fpu_sqr64_fState_S3$D_OUT[8] && - !fpu_sqr64_fState_S3$D_OUT[7] && - !fpu_sqr64_fState_S3$D_OUT[6] && - !fpu_sqr64_fState_S3$D_OUT[5] && - !fpu_sqr64_fState_S3$D_OUT[4] && - !fpu_sqr64_fState_S3$D_OUT[3] && - !fpu_sqr64_fState_S3$D_OUT[2] && - !fpu_sqr64_fState_S3$D_OUT[1] && - !fpu_sqr64_fState_S3$D_OUT[0] || - !_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633) ? - 11'd0 : - _theResult___fst_exp__h94828 ; - assign _theResult___fst_exp__h94837 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - fpu_sqr64_fState_S3$D_OUT[57]) ? - _theResult___fst_exp__h94789 : - _theResult___fst_exp__h94834 ; - assign _theResult___fst_exp__h95990 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h95987 ; - assign _theResult___fst_sfd__h164063 = - (_theResult___fst_exp__h163336 == 11'd2047) ? - _theResult___snd__h163287[56:5] : - _theResult___fst_sfd__h164060 ; - assign _theResult___fst_sfd__h173653 = - (_theResult___fst_exp__h172852 == 11'd2047) ? - sfdin__h172846[56:5] : - _theResult___fst_sfd__h173650 ; - assign _theResult___fst_sfd__h182405 = - (_theResult___fst_exp__h181653 == 11'd2047) ? - _theResult___snd__h181599[56:5] : - _theResult___fst_sfd__h182402 ; - assign _theResult___fst_sfd__h182414 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - _theResult___snd_fst_sfd__h164066 : - _theResult___fst_sfd__h148292) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - _theResult___snd_fst_sfd__h182408 : - _theResult___fst_sfd__h148292) ; - assign _theResult___fst_sfd__h182420 = - ((iFifo$D_OUT[167:160] == 8'd255 || - iFifo$D_OUT[167:160] == 8'd0) && - iFifo$D_OUT[159:137] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h182414 ; - assign _theResult___fst_sfd__h202701 = - (_theResult___fst_exp__h201974 == 11'd2047) ? - _theResult___snd__h201925[56:5] : - _theResult___fst_sfd__h202698 ; - assign _theResult___fst_sfd__h212291 = - (_theResult___fst_exp__h211490 == 11'd2047) ? - sfdin__h211484[56:5] : - _theResult___fst_sfd__h212288 ; - assign _theResult___fst_sfd__h221043 = - (_theResult___fst_exp__h220291 == 11'd2047) ? - _theResult___snd__h220237[56:5] : - _theResult___fst_sfd__h221040 ; - assign _theResult___fst_sfd__h221052 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - _theResult___snd_fst_sfd__h202704 : - _theResult___fst_sfd__h186932) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - _theResult___snd_fst_sfd__h221046 : - _theResult___fst_sfd__h186932) ; - assign _theResult___fst_sfd__h221058 = - ((iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h221052 ; - assign _theResult___fst_sfd__h241640 = - (_theResult___fst_exp__h240913 == 11'd2047) ? - _theResult___snd__h240864[56:5] : - _theResult___fst_sfd__h241637 ; - assign _theResult___fst_sfd__h251230 = - (_theResult___fst_exp__h250429 == 11'd2047) ? - sfdin__h250423[56:5] : - _theResult___fst_sfd__h251227 ; - assign _theResult___fst_sfd__h259982 = - (_theResult___fst_exp__h259230 == 11'd2047) ? - _theResult___snd__h259176[56:5] : - _theResult___fst_sfd__h259979 ; - assign _theResult___fst_sfd__h259991 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - _theResult___snd_fst_sfd__h241643 : - _theResult___fst_sfd__h225871) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - _theResult___snd_fst_sfd__h259985 : - _theResult___fst_sfd__h225871) ; - assign _theResult___fst_sfd__h259997 = - ((iFifo$D_OUT[37:30] == 8'd255 || iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h259991 ; - assign _theResult___fst_sfd__h278284 = - (_theResult___fst_exp__h277686 == 8'd255) ? - sfdin__h277680[56:34] : - _theResult___fst_sfd__h278281 ; - assign _theResult___fst_sfd__h286866 = - (_theResult___fst_exp__h286342 == 8'd255) ? - _theResult___snd__h286293[56:34] : - _theResult___fst_sfd__h286863 ; - assign _theResult___fst_sfd__h296050 = - (_theResult___fst_exp__h295452 == 8'd255) ? - sfdin__h295446[56:34] : - _theResult___fst_sfd__h296047 ; - assign _theResult___fst_sfd__h304686 = - (_theResult___fst_exp__h304137 == 8'd255) ? - _theResult___snd__h304083[56:34] : - _theResult___fst_sfd__h304683 ; - assign _theResult___fst_sfd__h304695 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - _theResult___snd_fst_sfd__h286869 : - _theResult___fst_sfd__h269560) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - _theResult___snd_fst_sfd__h304689 : - _theResult___fst_sfd__h269560) ; - assign _theResult___fst_sfd__h304701 = - ((resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - 23'd0 : - _theResult___fst_sfd__h304695 ; - assign _theResult___fst_sfd__h43557 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h43554 ; - assign _theResult___fst_sfd__h95991 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h95988 ; - assign _theResult___fst_sfd__h96608 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[182:131] : - 52'd0 ; - assign _theResult___sfd__h142542 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 52'd0 : - sfd__h142040[52:1]) : - sfd__h142040[51:0] ; - assign _theResult___sfd__h163982 = - sfd__h163354[53] ? - ((_theResult___fst_exp__h163336 == 11'd2046) ? - 52'd0 : - sfd__h163354[52:1]) : - sfd__h163354[51:0] ; - assign _theResult___sfd__h173572 = - sfd__h172944[53] ? - ((_theResult___fst_exp__h172852 == 11'd2046) ? - 52'd0 : - sfd__h172944[52:1]) : - sfd__h172944[51:0] ; - assign _theResult___sfd__h182324 = - sfd__h181672[53] ? - ((_theResult___fst_exp__h181653 == 11'd2046) ? - 52'd0 : - sfd__h181672[52:1]) : - sfd__h181672[51:0] ; - assign _theResult___sfd__h202620 = - sfd__h201992[53] ? - ((_theResult___fst_exp__h201974 == 11'd2046) ? - 52'd0 : - sfd__h201992[52:1]) : - sfd__h201992[51:0] ; - assign _theResult___sfd__h212210 = - sfd__h211582[53] ? - ((_theResult___fst_exp__h211490 == 11'd2046) ? - 52'd0 : - sfd__h211582[52:1]) : - sfd__h211582[51:0] ; - assign _theResult___sfd__h220962 = - sfd__h220310[53] ? - ((_theResult___fst_exp__h220291 == 11'd2046) ? - 52'd0 : - sfd__h220310[52:1]) : - sfd__h220310[51:0] ; - assign _theResult___sfd__h241559 = - sfd__h240931[53] ? - ((_theResult___fst_exp__h240913 == 11'd2046) ? - 52'd0 : - sfd__h240931[52:1]) : - sfd__h240931[51:0] ; - assign _theResult___sfd__h251149 = - sfd__h250521[53] ? - ((_theResult___fst_exp__h250429 == 11'd2046) ? - 52'd0 : - sfd__h250521[52:1]) : - sfd__h250521[51:0] ; - assign _theResult___sfd__h259901 = - sfd__h259249[53] ? - ((_theResult___fst_exp__h259230 == 11'd2046) ? - 52'd0 : - sfd__h259249[52:1]) : - sfd__h259249[51:0] ; - assign _theResult___sfd__h278203 = - sfd__h277778[24] ? - ((_theResult___fst_exp__h277686 == 8'd254) ? - 23'd0 : - sfd__h277778[23:1]) : - sfd__h277778[22:0] ; - assign _theResult___sfd__h286785 = - sfd__h286360[24] ? - ((_theResult___fst_exp__h286342 == 8'd254) ? - 23'd0 : - sfd__h286360[23:1]) : - sfd__h286360[22:0] ; - assign _theResult___sfd__h295969 = - sfd__h295544[24] ? - ((_theResult___fst_exp__h295452 == 8'd254) ? - 23'd0 : - sfd__h295544[23:1]) : - sfd__h295544[22:0] ; - assign _theResult___sfd__h304605 = - sfd__h304156[24] ? - ((_theResult___fst_exp__h304137 == 8'd254) ? - 23'd0 : - sfd__h304156[23:1]) : - sfd__h304156[22:0] ; - assign _theResult___sfd__h43476 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h42982[52:1]) : - sfd__h42982[51:0] ; - assign _theResult___sfd__h95910 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h95416[52:1]) : - sfd__h95416[51:0] ; - assign _theResult___snd__h130966 = { sfdBC__h115662[104:0], 1'd0 } ; - assign _theResult___snd__h130980 = - (!sfdBC__h115662[105] && sfdBC__h115662[104]) ? - _theResult___snd__h130982 : - _theResult___snd__h130994 ; - assign _theResult___snd__h130982 = { sfdBC__h115662[103:0], 2'd0 } ; - assign _theResult___snd__h130994 = - (!sfdBC__h115662[105] && !sfdBC__h115662[104] && - !sfdBC__h115662[103] && - !sfdBC__h115662[102] && - !sfdBC__h115662[101] && - !sfdBC__h115662[100] && - !sfdBC__h115662[99] && - !sfdBC__h115662[98] && - !sfdBC__h115662[97] && - !sfdBC__h115662[96] && - !sfdBC__h115662[95] && - !sfdBC__h115662[94] && - !sfdBC__h115662[93] && - !sfdBC__h115662[92] && - !sfdBC__h115662[91] && - !sfdBC__h115662[90] && - !sfdBC__h115662[89] && - !sfdBC__h115662[88] && - !sfdBC__h115662[87] && - !sfdBC__h115662[86] && - !sfdBC__h115662[85] && - !sfdBC__h115662[84] && - !sfdBC__h115662[83] && - !sfdBC__h115662[82] && - !sfdBC__h115662[81] && - !sfdBC__h115662[80] && - !sfdBC__h115662[79] && - !sfdBC__h115662[78] && - !sfdBC__h115662[77] && - !sfdBC__h115662[76] && - !sfdBC__h115662[75] && - !sfdBC__h115662[74] && - !sfdBC__h115662[73] && - !sfdBC__h115662[72] && - !sfdBC__h115662[71] && - !sfdBC__h115662[70] && - !sfdBC__h115662[69] && - !sfdBC__h115662[68] && - !sfdBC__h115662[67] && - !sfdBC__h115662[66] && - !sfdBC__h115662[65] && - !sfdBC__h115662[64] && - !sfdBC__h115662[63] && - !sfdBC__h115662[62] && - !sfdBC__h115662[61] && - !sfdBC__h115662[60] && - !sfdBC__h115662[59] && - !sfdBC__h115662[58] && - !sfdBC__h115662[57] && - !sfdBC__h115662[56] && - !sfdBC__h115662[55] && - !sfdBC__h115662[54] && - !sfdBC__h115662[53] && - !sfdBC__h115662[52] && - !sfdBC__h115662[51] && - !sfdBC__h115662[50] && - !sfdBC__h115662[49] && - !sfdBC__h115662[48] && - !sfdBC__h115662[47] && - !sfdBC__h115662[46] && - !sfdBC__h115662[45] && - !sfdBC__h115662[44] && - !sfdBC__h115662[43] && - !sfdBC__h115662[42] && - !sfdBC__h115662[41] && - !sfdBC__h115662[40] && - !sfdBC__h115662[39] && - !sfdBC__h115662[38] && - !sfdBC__h115662[37] && - !sfdBC__h115662[36] && - !sfdBC__h115662[35] && - !sfdBC__h115662[34] && - !sfdBC__h115662[33] && - !sfdBC__h115662[32] && - !sfdBC__h115662[31] && - !sfdBC__h115662[30] && - !sfdBC__h115662[29] && - !sfdBC__h115662[28] && - !sfdBC__h115662[27] && - !sfdBC__h115662[26] && - !sfdBC__h115662[25] && - !sfdBC__h115662[24] && - !sfdBC__h115662[23] && - !sfdBC__h115662[22] && - !sfdBC__h115662[21] && - !sfdBC__h115662[20] && - !sfdBC__h115662[19] && - !sfdBC__h115662[18] && - !sfdBC__h115662[17] && - !sfdBC__h115662[16] && - !sfdBC__h115662[15] && - !sfdBC__h115662[14] && - !sfdBC__h115662[13] && - !sfdBC__h115662[12] && - !sfdBC__h115662[11] && - !sfdBC__h115662[10] && - !sfdBC__h115662[9] && - !sfdBC__h115662[8] && - !sfdBC__h115662[7] && - !sfdBC__h115662[6] && - !sfdBC__h115662[5] && - !sfdBC__h115662[4] && - !sfdBC__h115662[3] && - !sfdBC__h115662[2] && - !sfdBC__h115662[1] && - !sfdBC__h115662[0]) ? - sfdBC__h115662 : - _theResult___snd__h131000 ; - assign _theResult___snd__h131000 = - { IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24[103:0], - 2'd0 } ; - assign _theResult___snd__h131018 = - sfdBC__h115662 << - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ; - assign _theResult___snd__h131023 = - sfdBC__h115662 << - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 ; - assign _theResult___snd__h141392 = { sfd__h133119[55:0], 1'd0 } ; - assign _theResult___snd__h141406 = - (!sfd__h133119[56] && sfd__h133119[55]) ? - _theResult___snd__h141408 : - _theResult___snd__h141420 ; - assign _theResult___snd__h141408 = { sfd__h133119[54:0], 2'd0 } ; - assign _theResult___snd__h141420 = - (!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] && - !sfd__h133119[53] && - !sfd__h133119[52] && - !sfd__h133119[51] && - !sfd__h133119[50] && - !sfd__h133119[49] && - !sfd__h133119[48] && - !sfd__h133119[47] && - !sfd__h133119[46] && - !sfd__h133119[45] && - !sfd__h133119[44] && - !sfd__h133119[43] && - !sfd__h133119[42] && - !sfd__h133119[41] && - !sfd__h133119[40] && - !sfd__h133119[39] && - !sfd__h133119[38] && - !sfd__h133119[37] && - !sfd__h133119[36] && - !sfd__h133119[35] && - !sfd__h133119[34] && - !sfd__h133119[33] && - !sfd__h133119[32] && - !sfd__h133119[31] && - !sfd__h133119[30] && - !sfd__h133119[29] && - !sfd__h133119[28] && - !sfd__h133119[27] && - !sfd__h133119[26] && - !sfd__h133119[25] && - !sfd__h133119[24] && - !sfd__h133119[23] && - !sfd__h133119[22] && - !sfd__h133119[21] && - !sfd__h133119[20] && - !sfd__h133119[19] && - !sfd__h133119[18] && - !sfd__h133119[17] && - !sfd__h133119[16] && - !sfd__h133119[15] && - !sfd__h133119[14] && - !sfd__h133119[13] && - !sfd__h133119[12] && - !sfd__h133119[11] && - !sfd__h133119[10] && - !sfd__h133119[9] && - !sfd__h133119[8] && - !sfd__h133119[7] && - !sfd__h133119[6] && - !sfd__h133119[5] && - !sfd__h133119[4] && - !sfd__h133119[3] && - !sfd__h133119[2] && - !sfd__h133119[1] && - !sfd__h133119[0]) ? - sfd__h133119 : - _theResult___snd__h141426 ; - assign _theResult___snd__h141426 = - { IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29[54:0], - 2'd0 } ; - assign _theResult___snd__h141444 = - sfd__h133119 << - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ; - assign _theResult___snd__h141449 = - sfd__h133119 << - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 ; - assign _theResult___snd__h163287 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___snd__h163296 : - _theResult___snd__h163289 ; - assign _theResult___snd__h163289 = { iFifo$D_OUT[159:137], 34'd0 } ; - assign _theResult___snd__h163296 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ? - sfd__h144536 : - _theResult___snd__h163302 ; - assign _theResult___snd__h163302 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33[54:0], - 2'd0 } ; - assign _theResult___snd__h163325 = - sfd__h144536 << - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 ; - assign _theResult___snd__h172863 = { _theResult____h164614[55:0], 1'd0 } ; - assign _theResult___snd__h172874 = - (!_theResult____h164614[56] && _theResult____h164614[55]) ? - _theResult___snd__h172876 : - _theResult___snd__h172886 ; - assign _theResult___snd__h172876 = { _theResult____h164614[54:0], 2'd0 } ; - assign _theResult___snd__h172886 = - (!_theResult____h164614[56] && !_theResult____h164614[55] && - !_theResult____h164614[54] && - !_theResult____h164614[53] && - !_theResult____h164614[52] && - !_theResult____h164614[51] && - !_theResult____h164614[50] && - !_theResult____h164614[49] && - !_theResult____h164614[48] && - !_theResult____h164614[47] && - !_theResult____h164614[46] && - !_theResult____h164614[45] && - !_theResult____h164614[44] && - !_theResult____h164614[43] && - !_theResult____h164614[42] && - !_theResult____h164614[41] && - !_theResult____h164614[40] && - !_theResult____h164614[39] && - !_theResult____h164614[38] && - !_theResult____h164614[37] && - !_theResult____h164614[36] && - !_theResult____h164614[35] && - !_theResult____h164614[34] && - !_theResult____h164614[33] && - !_theResult____h164614[32] && - !_theResult____h164614[31] && - !_theResult____h164614[30] && - !_theResult____h164614[29] && - !_theResult____h164614[28] && - !_theResult____h164614[27] && - !_theResult____h164614[26] && - !_theResult____h164614[25] && - !_theResult____h164614[24] && - !_theResult____h164614[23] && - !_theResult____h164614[22] && - !_theResult____h164614[21] && - !_theResult____h164614[20] && - !_theResult____h164614[19] && - !_theResult____h164614[18] && - !_theResult____h164614[17] && - !_theResult____h164614[16] && - !_theResult____h164614[15] && - !_theResult____h164614[14] && - !_theResult____h164614[13] && - !_theResult____h164614[12] && - !_theResult____h164614[11] && - !_theResult____h164614[10] && - !_theResult____h164614[9] && - !_theResult____h164614[8] && - !_theResult____h164614[7] && - !_theResult____h164614[6] && - !_theResult____h164614[5] && - !_theResult____h164614[4] && - !_theResult____h164614[3] && - !_theResult____h164614[2] && - !_theResult____h164614[1] && - !_theResult____h164614[0]) ? - _theResult____h164614 : - _theResult___snd__h172892 ; - assign _theResult___snd__h172892 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37[54:0], - 2'd0 } ; - assign _theResult___snd__h172915 = - _theResult____h164614 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 ; - assign _theResult___snd__h181599 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___snd__h181613 : - _theResult___snd__h163289 ; - assign _theResult___snd__h181613 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ? - sfd__h144536 : - _theResult___snd__h181619 ; - assign _theResult___snd__h181619 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40[54:0], - 2'd0 } ; - assign _theResult___snd__h181637 = - sfd__h144536 << - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ; - assign _theResult___snd__h201925 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___snd__h201934 : - _theResult___snd__h201927 ; - assign _theResult___snd__h201927 = { iFifo$D_OUT[94:72], 34'd0 } ; - assign _theResult___snd__h201934 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ? - sfd__h183176 : - _theResult___snd__h201940 ; - assign _theResult___snd__h201940 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93[54:0], - 2'd0 } ; - assign _theResult___snd__h201963 = - sfd__h183176 << - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 ; - assign _theResult___snd__h211501 = { _theResult____h203252[55:0], 1'd0 } ; - assign _theResult___snd__h211512 = - (!_theResult____h203252[56] && _theResult____h203252[55]) ? - _theResult___snd__h211514 : - _theResult___snd__h211524 ; - assign _theResult___snd__h211514 = { _theResult____h203252[54:0], 2'd0 } ; - assign _theResult___snd__h211524 = - (!_theResult____h203252[56] && !_theResult____h203252[55] && - !_theResult____h203252[54] && - !_theResult____h203252[53] && - !_theResult____h203252[52] && - !_theResult____h203252[51] && - !_theResult____h203252[50] && - !_theResult____h203252[49] && - !_theResult____h203252[48] && - !_theResult____h203252[47] && - !_theResult____h203252[46] && - !_theResult____h203252[45] && - !_theResult____h203252[44] && - !_theResult____h203252[43] && - !_theResult____h203252[42] && - !_theResult____h203252[41] && - !_theResult____h203252[40] && - !_theResult____h203252[39] && - !_theResult____h203252[38] && - !_theResult____h203252[37] && - !_theResult____h203252[36] && - !_theResult____h203252[35] && - !_theResult____h203252[34] && - !_theResult____h203252[33] && - !_theResult____h203252[32] && - !_theResult____h203252[31] && - !_theResult____h203252[30] && - !_theResult____h203252[29] && - !_theResult____h203252[28] && - !_theResult____h203252[27] && - !_theResult____h203252[26] && - !_theResult____h203252[25] && - !_theResult____h203252[24] && - !_theResult____h203252[23] && - !_theResult____h203252[22] && - !_theResult____h203252[21] && - !_theResult____h203252[20] && - !_theResult____h203252[19] && - !_theResult____h203252[18] && - !_theResult____h203252[17] && - !_theResult____h203252[16] && - !_theResult____h203252[15] && - !_theResult____h203252[14] && - !_theResult____h203252[13] && - !_theResult____h203252[12] && - !_theResult____h203252[11] && - !_theResult____h203252[10] && - !_theResult____h203252[9] && - !_theResult____h203252[8] && - !_theResult____h203252[7] && - !_theResult____h203252[6] && - !_theResult____h203252[5] && - !_theResult____h203252[4] && - !_theResult____h203252[3] && - !_theResult____h203252[2] && - !_theResult____h203252[1] && - !_theResult____h203252[0]) ? - _theResult____h203252 : - _theResult___snd__h211530 ; - assign _theResult___snd__h211530 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97[54:0], - 2'd0 } ; - assign _theResult___snd__h211553 = - _theResult____h203252 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 ; - assign _theResult___snd__h220237 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___snd__h220251 : - _theResult___snd__h201927 ; - assign _theResult___snd__h220251 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ? - sfd__h183176 : - _theResult___snd__h220257 ; - assign _theResult___snd__h220257 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100[54:0], - 2'd0 } ; - assign _theResult___snd__h220275 = - sfd__h183176 << - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ; - assign _theResult___snd__h240864 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___snd__h240873 : - _theResult___snd__h240866 ; - assign _theResult___snd__h240866 = { iFifo$D_OUT[29:7], 34'd0 } ; - assign _theResult___snd__h240873 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ? - sfd__h222115 : - _theResult___snd__h240879 ; - assign _theResult___snd__h240879 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60[54:0], - 2'd0 } ; - assign _theResult___snd__h240902 = - sfd__h222115 << - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 ; - assign _theResult___snd__h250440 = { _theResult____h242191[55:0], 1'd0 } ; - assign _theResult___snd__h250451 = - (!_theResult____h242191[56] && _theResult____h242191[55]) ? - _theResult___snd__h250453 : - _theResult___snd__h250463 ; - assign _theResult___snd__h250453 = { _theResult____h242191[54:0], 2'd0 } ; - assign _theResult___snd__h250463 = - (!_theResult____h242191[56] && !_theResult____h242191[55] && - !_theResult____h242191[54] && - !_theResult____h242191[53] && - !_theResult____h242191[52] && - !_theResult____h242191[51] && - !_theResult____h242191[50] && - !_theResult____h242191[49] && - !_theResult____h242191[48] && - !_theResult____h242191[47] && - !_theResult____h242191[46] && - !_theResult____h242191[45] && - !_theResult____h242191[44] && - !_theResult____h242191[43] && - !_theResult____h242191[42] && - !_theResult____h242191[41] && - !_theResult____h242191[40] && - !_theResult____h242191[39] && - !_theResult____h242191[38] && - !_theResult____h242191[37] && - !_theResult____h242191[36] && - !_theResult____h242191[35] && - !_theResult____h242191[34] && - !_theResult____h242191[33] && - !_theResult____h242191[32] && - !_theResult____h242191[31] && - !_theResult____h242191[30] && - !_theResult____h242191[29] && - !_theResult____h242191[28] && - !_theResult____h242191[27] && - !_theResult____h242191[26] && - !_theResult____h242191[25] && - !_theResult____h242191[24] && - !_theResult____h242191[23] && - !_theResult____h242191[22] && - !_theResult____h242191[21] && - !_theResult____h242191[20] && - !_theResult____h242191[19] && - !_theResult____h242191[18] && - !_theResult____h242191[17] && - !_theResult____h242191[16] && - !_theResult____h242191[15] && - !_theResult____h242191[14] && - !_theResult____h242191[13] && - !_theResult____h242191[12] && - !_theResult____h242191[11] && - !_theResult____h242191[10] && - !_theResult____h242191[9] && - !_theResult____h242191[8] && - !_theResult____h242191[7] && - !_theResult____h242191[6] && - !_theResult____h242191[5] && - !_theResult____h242191[4] && - !_theResult____h242191[3] && - !_theResult____h242191[2] && - !_theResult____h242191[1] && - !_theResult____h242191[0]) ? - _theResult____h242191 : - _theResult___snd__h250469 ; - assign _theResult___snd__h250469 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64[54:0], - 2'd0 } ; - assign _theResult___snd__h250492 = - _theResult____h242191 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 ; - assign _theResult___snd__h259176 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___snd__h259190 : - _theResult___snd__h240866 ; - assign _theResult___snd__h259190 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ? - sfd__h222115 : - _theResult___snd__h259196 ; - assign _theResult___snd__h259196 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67[54:0], - 2'd0 } ; - assign _theResult___snd__h259214 = - sfd__h222115 << - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ; - assign _theResult___snd__h277697 = { _theResult____h269577[55:0], 1'd0 } ; - assign _theResult___snd__h277708 = - (!_theResult____h269577[56] && _theResult____h269577[55]) ? - _theResult___snd__h277710 : - _theResult___snd__h277720 ; - assign _theResult___snd__h277710 = { _theResult____h269577[54:0], 2'd0 } ; - assign _theResult___snd__h277720 = - (!_theResult____h269577[56] && !_theResult____h269577[55] && - !_theResult____h269577[54] && - !_theResult____h269577[53] && - !_theResult____h269577[52] && - !_theResult____h269577[51] && - !_theResult____h269577[50] && - !_theResult____h269577[49] && - !_theResult____h269577[48] && - !_theResult____h269577[47] && - !_theResult____h269577[46] && - !_theResult____h269577[45] && - !_theResult____h269577[44] && - !_theResult____h269577[43] && - !_theResult____h269577[42] && - !_theResult____h269577[41] && - !_theResult____h269577[40] && - !_theResult____h269577[39] && - !_theResult____h269577[38] && - !_theResult____h269577[37] && - !_theResult____h269577[36] && - !_theResult____h269577[35] && - !_theResult____h269577[34] && - !_theResult____h269577[33] && - !_theResult____h269577[32] && - !_theResult____h269577[31] && - !_theResult____h269577[30] && - !_theResult____h269577[29] && - !_theResult____h269577[28] && - !_theResult____h269577[27] && - !_theResult____h269577[26] && - !_theResult____h269577[25] && - !_theResult____h269577[24] && - !_theResult____h269577[23] && - !_theResult____h269577[22] && - !_theResult____h269577[21] && - !_theResult____h269577[20] && - !_theResult____h269577[19] && - !_theResult____h269577[18] && - !_theResult____h269577[17] && - !_theResult____h269577[16] && - !_theResult____h269577[15] && - !_theResult____h269577[14] && - !_theResult____h269577[13] && - !_theResult____h269577[12] && - !_theResult____h269577[11] && - !_theResult____h269577[10] && - !_theResult____h269577[9] && - !_theResult____h269577[8] && - !_theResult____h269577[7] && - !_theResult____h269577[6] && - !_theResult____h269577[5] && - !_theResult____h269577[4] && - !_theResult____h269577[3] && - !_theResult____h269577[2] && - !_theResult____h269577[1] && - !_theResult____h269577[0]) ? - _theResult____h269577 : - _theResult___snd__h277726 ; - assign _theResult___snd__h277726 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133[54:0], - 2'd0 } ; - assign _theResult___snd__h277749 = - _theResult____h269577 << - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 ; - assign _theResult___snd__h286293 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___snd__h286302 : - _theResult___snd__h286295 ; - assign _theResult___snd__h286295 = { resWire$wget[56:5], 5'd0 } ; - assign _theResult___snd__h286302 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ? - sfd__h261975 : - _theResult___snd__h286308 ; - assign _theResult___snd__h286308 = - { IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135[54:0], - 2'd0 } ; - assign _theResult___snd__h286331 = - sfd__h261975 << - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 ; - assign _theResult___snd__h295463 = { _theResult____h287214[55:0], 1'd0 } ; - assign _theResult___snd__h295474 = - (!_theResult____h287214[56] && _theResult____h287214[55]) ? - _theResult___snd__h295476 : - _theResult___snd__h295486 ; - assign _theResult___snd__h295476 = { _theResult____h287214[54:0], 2'd0 } ; - assign _theResult___snd__h295486 = - (!_theResult____h287214[56] && !_theResult____h287214[55] && - !_theResult____h287214[54] && - !_theResult____h287214[53] && - !_theResult____h287214[52] && - !_theResult____h287214[51] && - !_theResult____h287214[50] && - !_theResult____h287214[49] && - !_theResult____h287214[48] && - !_theResult____h287214[47] && - !_theResult____h287214[46] && - !_theResult____h287214[45] && - !_theResult____h287214[44] && - !_theResult____h287214[43] && - !_theResult____h287214[42] && - !_theResult____h287214[41] && - !_theResult____h287214[40] && - !_theResult____h287214[39] && - !_theResult____h287214[38] && - !_theResult____h287214[37] && - !_theResult____h287214[36] && - !_theResult____h287214[35] && - !_theResult____h287214[34] && - !_theResult____h287214[33] && - !_theResult____h287214[32] && - !_theResult____h287214[31] && - !_theResult____h287214[30] && - !_theResult____h287214[29] && - !_theResult____h287214[28] && - !_theResult____h287214[27] && - !_theResult____h287214[26] && - !_theResult____h287214[25] && - !_theResult____h287214[24] && - !_theResult____h287214[23] && - !_theResult____h287214[22] && - !_theResult____h287214[21] && - !_theResult____h287214[20] && - !_theResult____h287214[19] && - !_theResult____h287214[18] && - !_theResult____h287214[17] && - !_theResult____h287214[16] && - !_theResult____h287214[15] && - !_theResult____h287214[14] && - !_theResult____h287214[13] && - !_theResult____h287214[12] && - !_theResult____h287214[11] && - !_theResult____h287214[10] && - !_theResult____h287214[9] && - !_theResult____h287214[8] && - !_theResult____h287214[7] && - !_theResult____h287214[6] && - !_theResult____h287214[5] && - !_theResult____h287214[4] && - !_theResult____h287214[3] && - !_theResult____h287214[2] && - !_theResult____h287214[1] && - !_theResult____h287214[0]) ? - _theResult____h287214 : - _theResult___snd__h295492 ; - assign _theResult___snd__h295492 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139[54:0], - 2'd0 } ; - assign _theResult___snd__h295515 = - _theResult____h287214 << - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 ; - assign _theResult___snd__h304083 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___snd__h304097 : - _theResult___snd__h286295 ; - assign _theResult___snd__h304097 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ? - sfd__h261975 : - _theResult___snd__h304103 ; - assign _theResult___snd__h304103 = - { IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142[54:0], - 2'd0 } ; - assign _theResult___snd__h304121 = - sfd__h261975 << - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ; - assign _theResult___snd__h34715 = - { fpu_div64_fState_S3$D_OUT[56:0], 1'd0 } ; - assign _theResult___snd__h42350 = { sfdin__h34118[56:0], 1'd0 } ; - assign _theResult___snd__h42365 = - (!sfdin__h34118[57] && sfdin__h34118[56]) ? - _theResult___snd__h42367 : - _theResult___snd__h42380 ; - assign _theResult___snd__h42367 = { sfdin__h34118[55:0], 2'd0 } ; - assign _theResult___snd__h42380 = - (!sfdin__h34118[57] && !sfdin__h34118[56] && - !sfdin__h34118[55] && - !sfdin__h34118[54] && - !sfdin__h34118[53] && - !sfdin__h34118[52] && - !sfdin__h34118[51] && - !sfdin__h34118[50] && - !sfdin__h34118[49] && - !sfdin__h34118[48] && - !sfdin__h34118[47] && - !sfdin__h34118[46] && - !sfdin__h34118[45] && - !sfdin__h34118[44] && - !sfdin__h34118[43] && - !sfdin__h34118[42] && - !sfdin__h34118[41] && - !sfdin__h34118[40] && - !sfdin__h34118[39] && - !sfdin__h34118[38] && - !sfdin__h34118[37] && - !sfdin__h34118[36] && - !sfdin__h34118[35] && - !sfdin__h34118[34] && - !sfdin__h34118[33] && - !sfdin__h34118[32] && - !sfdin__h34118[31] && - !sfdin__h34118[30] && - !sfdin__h34118[29] && - !sfdin__h34118[28] && - !sfdin__h34118[27] && - !sfdin__h34118[26] && - !sfdin__h34118[25] && - !sfdin__h34118[24] && - !sfdin__h34118[23] && - !sfdin__h34118[22] && - !sfdin__h34118[21] && - !sfdin__h34118[20] && - !sfdin__h34118[19] && - !sfdin__h34118[18] && - !sfdin__h34118[17] && - !sfdin__h34118[16] && - !sfdin__h34118[15] && - !sfdin__h34118[14] && - !sfdin__h34118[13] && - !sfdin__h34118[12] && - !sfdin__h34118[11] && - !sfdin__h34118[10] && - !sfdin__h34118[9] && - !sfdin__h34118[8] && - !sfdin__h34118[7] && - !sfdin__h34118[6] && - !sfdin__h34118[5] && - !sfdin__h34118[4] && - !sfdin__h34118[3] && - !sfdin__h34118[2] && - !sfdin__h34118[1] && - !sfdin__h34118[0]) ? - sfdin__h34118 : - _theResult___snd__h42386 ; - assign _theResult___snd__h42386 = - { IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12[55:0], - 2'd0 } ; - assign _theResult___snd__h42404 = - sfdin__h34118 << - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 ; - assign _theResult___snd__h42409 = - sfdin__h34118 << - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 ; - assign _theResult___snd__h94767 = - { fpu_sqr64_fState_S3$D_OUT[57:0], 1'd0 } ; - assign _theResult___snd__h94782 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - fpu_sqr64_fState_S3$D_OUT[57]) ? - _theResult___snd__h94784 : - _theResult___snd__h94797 ; - assign _theResult___snd__h94784 = - { fpu_sqr64_fState_S3$D_OUT[56:0], 2'd0 } ; - assign _theResult___snd__h94797 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - !fpu_sqr64_fState_S3$D_OUT[57] && - !fpu_sqr64_fState_S3$D_OUT[56] && - !fpu_sqr64_fState_S3$D_OUT[55] && - !fpu_sqr64_fState_S3$D_OUT[54] && - !fpu_sqr64_fState_S3$D_OUT[53] && - !fpu_sqr64_fState_S3$D_OUT[52] && - !fpu_sqr64_fState_S3$D_OUT[51] && - !fpu_sqr64_fState_S3$D_OUT[50] && - !fpu_sqr64_fState_S3$D_OUT[49] && - !fpu_sqr64_fState_S3$D_OUT[48] && - !fpu_sqr64_fState_S3$D_OUT[47] && - !fpu_sqr64_fState_S3$D_OUT[46] && - !fpu_sqr64_fState_S3$D_OUT[45] && - !fpu_sqr64_fState_S3$D_OUT[44] && - !fpu_sqr64_fState_S3$D_OUT[43] && - !fpu_sqr64_fState_S3$D_OUT[42] && - !fpu_sqr64_fState_S3$D_OUT[41] && - !fpu_sqr64_fState_S3$D_OUT[40] && - !fpu_sqr64_fState_S3$D_OUT[39] && - !fpu_sqr64_fState_S3$D_OUT[38] && - !fpu_sqr64_fState_S3$D_OUT[37] && - !fpu_sqr64_fState_S3$D_OUT[36] && - !fpu_sqr64_fState_S3$D_OUT[35] && - !fpu_sqr64_fState_S3$D_OUT[34] && - !fpu_sqr64_fState_S3$D_OUT[33] && - !fpu_sqr64_fState_S3$D_OUT[32] && - !fpu_sqr64_fState_S3$D_OUT[31] && - !fpu_sqr64_fState_S3$D_OUT[30] && - !fpu_sqr64_fState_S3$D_OUT[29] && - !fpu_sqr64_fState_S3$D_OUT[28] && - !fpu_sqr64_fState_S3$D_OUT[27] && - !fpu_sqr64_fState_S3$D_OUT[26] && - !fpu_sqr64_fState_S3$D_OUT[25] && - !fpu_sqr64_fState_S3$D_OUT[24] && - !fpu_sqr64_fState_S3$D_OUT[23] && - !fpu_sqr64_fState_S3$D_OUT[22] && - !fpu_sqr64_fState_S3$D_OUT[21] && - !fpu_sqr64_fState_S3$D_OUT[20] && - !fpu_sqr64_fState_S3$D_OUT[19] && - !fpu_sqr64_fState_S3$D_OUT[18] && - !fpu_sqr64_fState_S3$D_OUT[17] && - !fpu_sqr64_fState_S3$D_OUT[16] && - !fpu_sqr64_fState_S3$D_OUT[15] && - !fpu_sqr64_fState_S3$D_OUT[14] && - !fpu_sqr64_fState_S3$D_OUT[13] && - !fpu_sqr64_fState_S3$D_OUT[12] && - !fpu_sqr64_fState_S3$D_OUT[11] && - !fpu_sqr64_fState_S3$D_OUT[10] && - !fpu_sqr64_fState_S3$D_OUT[9] && - !fpu_sqr64_fState_S3$D_OUT[8] && - !fpu_sqr64_fState_S3$D_OUT[7] && - !fpu_sqr64_fState_S3$D_OUT[6] && - !fpu_sqr64_fState_S3$D_OUT[5] && - !fpu_sqr64_fState_S3$D_OUT[4] && - !fpu_sqr64_fState_S3$D_OUT[3] && - !fpu_sqr64_fState_S3$D_OUT[2] && - !fpu_sqr64_fState_S3$D_OUT[1] && - !fpu_sqr64_fState_S3$D_OUT[0]) ? - fpu_sqr64_fState_S3$D_OUT[58:0] : - _theResult___snd__h94803 ; - assign _theResult___snd__h94803 = - { IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19[56:0], - 2'd0 } ; - assign _theResult___snd__h94821 = - fpu_sqr64_fState_S3$D_OUT[58:0] << - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 ; - assign _theResult___snd__h94826 = - fpu_sqr64_fState_S3$D_OUT[58:0] << - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 ; - assign _theResult___snd_fst__h131051 = - { IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25[1], - { sfdin__h130943[52:0], 52'd0 } != 105'd0 } ; - assign _theResult___snd_fst__h141477 = - { IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30[1], - { sfdin__h141369[3:0], 52'd0 } != 56'd0 } ; - assign _theResult___snd_fst__h1478 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___snd_fst__h1602 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 ; - assign _theResult___snd_fst__h1517 = - (rg_res[116] || rg_b == 116'd0 || - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63) ? - rg_s : - s__h1658 ; - assign _theResult___snd_fst__h1602 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0 || - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 : - s__h1723 ; - assign _theResult___snd_fst__h42439 = - { IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13[1], - { sfdin__h42327[4:0], 52'd0 } != 57'd0 } ; - assign _theResult___snd_fst__h94856 = - { IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20[1], - { sfdin__h94744[5:0], 52'd0 } != 58'd0 } ; - assign _theResult___snd_fst_exp__h164065 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - 11'd0 : - _theResult___fst_exp__h164062 ; - assign _theResult___snd_fst_exp__h182407 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - _theResult___fst_exp__h173652 : - _theResult___fst_exp__h182404 ; - assign _theResult___snd_fst_exp__h202703 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - 11'd0 : - _theResult___fst_exp__h202700 ; - assign _theResult___snd_fst_exp__h221045 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - _theResult___fst_exp__h212290 : - _theResult___fst_exp__h221042 ; - assign _theResult___snd_fst_exp__h241642 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - 11'd0 : - _theResult___fst_exp__h241639 ; - assign _theResult___snd_fst_exp__h259984 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - _theResult___fst_exp__h251229 : - _theResult___fst_exp__h259981 ; - assign _theResult___snd_fst_exp__h286868 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _theResult___fst_exp__h278283 : - _theResult___fst_exp__h286865 ; - assign _theResult___snd_fst_exp__h304688 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _theResult___fst_exp__h296049 : - _theResult___fst_exp__h304685 ; - assign _theResult___snd_fst_exp__h31334 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499) ? - 11'd0 : - value__h31374[10:0] ; - assign _theResult___snd_fst_exp__h31337 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ? - _theResult___snd_fst_exp__h31334 : - 11'd2046 ; - assign _theResult___snd_fst_exp__h31361 = - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 ? - 11'd0 : - _theResult___snd_fst_exp__h31337 ; - assign _theResult___snd_fst_sfd__h144486 = - (iFifo$D_OUT[159:137] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h144235 ; - assign _theResult___snd_fst_sfd__h164066 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - 52'd0 : - _theResult___fst_sfd__h164063 ; - assign _theResult___snd_fst_sfd__h182408 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - _theResult___fst_sfd__h173653 : - _theResult___fst_sfd__h182405 ; - assign _theResult___snd_fst_sfd__h183126 = - (iFifo$D_OUT[94:72] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h182875 ; - assign _theResult___snd_fst_sfd__h202704 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - 52'd0 : - _theResult___fst_sfd__h202701 ; - assign _theResult___snd_fst_sfd__h221046 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - _theResult___fst_sfd__h212291 : - _theResult___fst_sfd__h221043 ; - assign _theResult___snd_fst_sfd__h222065 = - (iFifo$D_OUT[29:7] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h221814 ; - assign _theResult___snd_fst_sfd__h241643 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - 52'd0 : - _theResult___fst_sfd__h241640 ; - assign _theResult___snd_fst_sfd__h259985 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - _theResult___fst_sfd__h251230 : - _theResult___fst_sfd__h259982 ; - assign _theResult___snd_fst_sfd__h261925 = - (resWire$wget[56:34] == 23'd0) ? - 23'd2097152 : - resWire$wget[56:34] ; - assign _theResult___snd_fst_sfd__h286869 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _theResult___fst_sfd__h278284 : - _theResult___fst_sfd__h286866 ; - assign _theResult___snd_fst_sfd__h304689 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _theResult___fst_sfd__h296050 : - _theResult___fst_sfd__h304686 ; - assign _theResult___snd_fst_sfd__h31362 = - (fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353) ? - 52'd0 : - 52'hFFFFFFFFFFFFF ; - assign _theResult___snd_snd__h131371 = - (fpu_madd_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ; - assign _theResult___snd_snd__h1649 = - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63 ? r__h1663 : r__h1659 ; - assign _theResult___snd_snd__h1715 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85 ? - r__h1753 : - r__h1724 ; - assign _theResult___snd_snd_snd__h131369 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - _theResult___snd_snd__h131371 : - guardBC__h115666 ; - assign _theResult___snd_snd_snd__h1481 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___snd_snd_snd__h1605 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 ; - assign _theResult___snd_snd_snd__h1520 = - (rg_res[116] || rg_b == 116'd0) ? - rg_r_1 : - _theResult___snd_snd__h1649 ; - assign _theResult___snd_snd_snd__h1605 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 : - _theResult___snd_snd__h1715 ; - assign _theResult___snd_snd_snd__h33963 = - (fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___snd__h34715 : - fpu_div64_fState_S3$D_OUT[57:0] ; - assign b___1__h77160 = 116'h40000000000000000000000000000 >> x__h85465 ; - assign b__h11457 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0) ? - (fpu_div64_fOperands_S0$D_OUT[54] ? - 6'd1 : - (fpu_div64_fOperands_S0$D_OUT[53] ? - 6'd2 : - (fpu_div64_fOperands_S0$D_OUT[52] ? - 6'd3 : - (fpu_div64_fOperands_S0$D_OUT[51] ? - 6'd4 : - (fpu_div64_fOperands_S0$D_OUT[50] ? - 6'd5 : - (fpu_div64_fOperands_S0$D_OUT[49] ? - 6'd6 : - (fpu_div64_fOperands_S0$D_OUT[48] ? - 6'd7 : - (fpu_div64_fOperands_S0$D_OUT[47] ? - 6'd8 : - (fpu_div64_fOperands_S0$D_OUT[46] ? - 6'd9 : - (fpu_div64_fOperands_S0$D_OUT[45] ? - 6'd10 : - (fpu_div64_fOperands_S0$D_OUT[44] ? - 6'd11 : - (fpu_div64_fOperands_S0$D_OUT[43] ? - 6'd12 : - (fpu_div64_fOperands_S0$D_OUT[42] ? - 6'd13 : - (fpu_div64_fOperands_S0$D_OUT[41] ? - 6'd14 : - (fpu_div64_fOperands_S0$D_OUT[40] ? - 6'd15 : - (fpu_div64_fOperands_S0$D_OUT[39] ? - 6'd16 : - (fpu_div64_fOperands_S0$D_OUT[38] ? - 6'd17 : - (fpu_div64_fOperands_S0$D_OUT[37] ? - 6'd18 : - (fpu_div64_fOperands_S0$D_OUT[36] ? - 6'd19 : - (fpu_div64_fOperands_S0$D_OUT[35] ? - 6'd20 : - (fpu_div64_fOperands_S0$D_OUT[34] ? - 6'd21 : - (fpu_div64_fOperands_S0$D_OUT[33] ? - 6'd22 : - (fpu_div64_fOperands_S0$D_OUT[32] ? - 6'd23 : - (fpu_div64_fOperands_S0$D_OUT[31] ? - 6'd24 : - (fpu_div64_fOperands_S0$D_OUT[30] ? - 6'd25 : - (fpu_div64_fOperands_S0$D_OUT[29] ? - 6'd26 : - (fpu_div64_fOperands_S0$D_OUT[28] ? - 6'd27 : - (fpu_div64_fOperands_S0$D_OUT[27] ? - 6'd28 : - (fpu_div64_fOperands_S0$D_OUT[26] ? - 6'd29 : - (fpu_div64_fOperands_S0$D_OUT[25] ? - 6'd30 : - (fpu_div64_fOperands_S0$D_OUT[24] ? - 6'd31 : - (fpu_div64_fOperands_S0$D_OUT[23] ? - 6'd32 : - (fpu_div64_fOperands_S0$D_OUT[22] ? - 6'd33 : - (fpu_div64_fOperands_S0$D_OUT[21] ? - 6'd34 : - (fpu_div64_fOperands_S0$D_OUT[20] ? - 6'd35 : - (fpu_div64_fOperands_S0$D_OUT[19] ? - 6'd36 : - (fpu_div64_fOperands_S0$D_OUT[18] ? - 6'd37 : - (fpu_div64_fOperands_S0$D_OUT[17] ? - 6'd38 : - (fpu_div64_fOperands_S0$D_OUT[16] ? - 6'd39 : - (fpu_div64_fOperands_S0$D_OUT[15] ? - 6'd40 : - (fpu_div64_fOperands_S0$D_OUT[14] ? - 6'd41 : - (fpu_div64_fOperands_S0$D_OUT[13] ? - 6'd42 : - (fpu_div64_fOperands_S0$D_OUT[12] ? - 6'd43 : - (fpu_div64_fOperands_S0$D_OUT[11] ? - 6'd44 : - (fpu_div64_fOperands_S0$D_OUT[10] ? - 6'd45 : - (fpu_div64_fOperands_S0$D_OUT[9] ? - 6'd46 : - (fpu_div64_fOperands_S0$D_OUT[8] ? - 6'd47 : - (fpu_div64_fOperands_S0$D_OUT[7] ? - 6'd48 : - (fpu_div64_fOperands_S0$D_OUT[6] ? - 6'd49 : - (fpu_div64_fOperands_S0$D_OUT[5] ? - 6'd50 : - (fpu_div64_fOperands_S0$D_OUT[4] ? - 6'd51 : - (fpu_div64_fOperands_S0$D_OUT[3] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign b__h1608 = { 2'd0, rg_b[115:2] } ; - assign b__h1712 = - { 2'd0, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49[115:2] } ; - assign b__h32583 = { rg_d, 58'd0 } ; - assign b__h4039 = - (fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0) ? - (fpu_div64_fOperands_S0$D_OUT[118] ? - 6'd1 : - (fpu_div64_fOperands_S0$D_OUT[117] ? - 6'd2 : - (fpu_div64_fOperands_S0$D_OUT[116] ? - 6'd3 : - (fpu_div64_fOperands_S0$D_OUT[115] ? - 6'd4 : - (fpu_div64_fOperands_S0$D_OUT[114] ? - 6'd5 : - (fpu_div64_fOperands_S0$D_OUT[113] ? - 6'd6 : - (fpu_div64_fOperands_S0$D_OUT[112] ? - 6'd7 : - (fpu_div64_fOperands_S0$D_OUT[111] ? - 6'd8 : - (fpu_div64_fOperands_S0$D_OUT[110] ? - 6'd9 : - (fpu_div64_fOperands_S0$D_OUT[109] ? - 6'd10 : - (fpu_div64_fOperands_S0$D_OUT[108] ? - 6'd11 : - (fpu_div64_fOperands_S0$D_OUT[107] ? - 6'd12 : - (fpu_div64_fOperands_S0$D_OUT[106] ? - 6'd13 : - (fpu_div64_fOperands_S0$D_OUT[105] ? - 6'd14 : - (fpu_div64_fOperands_S0$D_OUT[104] ? - 6'd15 : - (fpu_div64_fOperands_S0$D_OUT[103] ? - 6'd16 : - (fpu_div64_fOperands_S0$D_OUT[102] ? - 6'd17 : - (fpu_div64_fOperands_S0$D_OUT[101] ? - 6'd18 : - (fpu_div64_fOperands_S0$D_OUT[100] ? - 6'd19 : - (fpu_div64_fOperands_S0$D_OUT[99] ? - 6'd20 : - (fpu_div64_fOperands_S0$D_OUT[98] ? - 6'd21 : - (fpu_div64_fOperands_S0$D_OUT[97] ? - 6'd22 : - (fpu_div64_fOperands_S0$D_OUT[96] ? - 6'd23 : - (fpu_div64_fOperands_S0$D_OUT[95] ? - 6'd24 : - (fpu_div64_fOperands_S0$D_OUT[94] ? - 6'd25 : - (fpu_div64_fOperands_S0$D_OUT[93] ? - 6'd26 : - (fpu_div64_fOperands_S0$D_OUT[92] ? - 6'd27 : - (fpu_div64_fOperands_S0$D_OUT[91] ? - 6'd28 : - (fpu_div64_fOperands_S0$D_OUT[90] ? - 6'd29 : - (fpu_div64_fOperands_S0$D_OUT[89] ? - 6'd30 : - (fpu_div64_fOperands_S0$D_OUT[88] ? - 6'd31 : - (fpu_div64_fOperands_S0$D_OUT[87] ? - 6'd32 : - (fpu_div64_fOperands_S0$D_OUT[86] ? - 6'd33 : - (fpu_div64_fOperands_S0$D_OUT[85] ? - 6'd34 : - (fpu_div64_fOperands_S0$D_OUT[84] ? - 6'd35 : - (fpu_div64_fOperands_S0$D_OUT[83] ? - 6'd36 : - (fpu_div64_fOperands_S0$D_OUT[82] ? - 6'd37 : - (fpu_div64_fOperands_S0$D_OUT[81] ? - 6'd38 : - (fpu_div64_fOperands_S0$D_OUT[80] ? - 6'd39 : - (fpu_div64_fOperands_S0$D_OUT[79] ? - 6'd40 : - (fpu_div64_fOperands_S0$D_OUT[78] ? - 6'd41 : - (fpu_div64_fOperands_S0$D_OUT[77] ? - 6'd42 : - (fpu_div64_fOperands_S0$D_OUT[76] ? - 6'd43 : - (fpu_div64_fOperands_S0$D_OUT[75] ? - 6'd44 : - (fpu_div64_fOperands_S0$D_OUT[74] ? - 6'd45 : - (fpu_div64_fOperands_S0$D_OUT[73] ? - 6'd46 : - (fpu_div64_fOperands_S0$D_OUT[72] ? - 6'd47 : - (fpu_div64_fOperands_S0$D_OUT[71] ? - 6'd48 : - (fpu_div64_fOperands_S0$D_OUT[70] ? - 6'd49 : - (fpu_div64_fOperands_S0$D_OUT[69] ? - 6'd50 : - (fpu_div64_fOperands_S0$D_OUT[68] ? - 6'd51 : - (fpu_div64_fOperands_S0$D_OUT[67] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign din_exp30866_MINUS_1023__q23 = din_exp__h130866 - 11'd1023 ; - assign din_exp__h130866 = - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ? - value__h130883[10:0] : - 11'd0 ; - assign din_inc___2_exp__h142626 = fpu_madd_fState_S8$D_OUT[65:55] + 11'd1 ; - assign din_inc___2_exp__h182469 = _theResult___fst_exp__h163336 + 11'd1 ; - assign din_inc___2_exp__h182504 = _theResult___fst_exp__h172852 + 11'd1 ; - assign din_inc___2_exp__h182530 = _theResult___fst_exp__h181653 + 11'd1 ; - assign din_inc___2_exp__h221107 = _theResult___fst_exp__h201974 + 11'd1 ; - assign din_inc___2_exp__h221142 = _theResult___fst_exp__h211490 + 11'd1 ; - assign din_inc___2_exp__h221168 = _theResult___fst_exp__h220291 + 11'd1 ; - assign din_inc___2_exp__h260046 = _theResult___fst_exp__h240913 + 11'd1 ; - assign din_inc___2_exp__h260081 = _theResult___fst_exp__h250429 + 11'd1 ; - assign din_inc___2_exp__h260107 = _theResult___fst_exp__h259230 + 11'd1 ; - assign din_inc___2_exp__h304723 = _theResult___fst_exp__h277686 + 8'd1 ; - assign din_inc___2_exp__h304749 = _theResult___fst_exp__h286342 + 8'd1 ; - assign din_inc___2_exp__h304784 = _theResult___fst_exp__h295452 + 8'd1 ; - assign din_inc___2_exp__h304810 = _theResult___fst_exp__h304137 + 8'd1 ; - assign din_inc___2_exp__h43566 = fpu_div64_fState_S4$D_OUT[64:54] + 11'd1 ; - assign din_inc___2_exp__h96000 = fpu_sqr64_fState_S4$D_OUT[64:54] + 11'd1 ; - assign exp__h304706 = - (resWire$wget[67:57] == 11'd2047) ? - 8'd255 : - _theResult___fst_exp__h304697 ; - assign fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7 = - fpu_div64_fOperands_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8 = - fpu_div64_fOperands_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401 ; - assign fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359 = - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - !IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ; - assign fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 = - fpu_div64_fOperands_S0$D_OUT[130] == - fpu_div64_fOperands_S0$D_OUT[66] ; - assign fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936 = - { fpu_div64_fState_S3$D_OUT[121], - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 ? - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929 : - ((fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - { _theResult___fst_exp__h42284, - fpu_div64_fState_S3$D_OUT[109:58] } : - 63'h7FEFFFFFFFFFFFFF) : - fpu_div64_fState_S3$D_OUT[120:58]) } ; - assign fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 = - fpu_madd_fOperand_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 = - fpu_madd_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 = - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 || - x__h96539 == 11'd0 && _theResult___fst_sfd__h96608 == 52'd0 && - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) && - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 ; - assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 = - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 = - (fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194]) == - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 ; - assign fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012 = - fpu_madd_fProd_S3$D_OUT >> - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ; - assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 = - (fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ; - assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 = - (fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ; - assign fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501 = - fpu_madd_fState_S3$D_OUT[86:82] | - { 2'd0, - sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023, - _theResult___fst_exp__h130952 == 11'd0 && - guardBC__h115666 != 2'd0, - sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023 } ; - assign fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27 = - fpu_madd_fState_S4$D_OUT[128:118] - 11'd1023 ; - assign fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26 = - fpu_madd_fState_S4$D_OUT[64:54] - 11'd1023 ; - assign fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615 = - fpu_madd_fState_S5$D_OUT[56:0] >> - fpu_madd_fState_S5$D_OUT[126:114] ; - assign fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942 = - fpu_madd_fState_S7$D_OUT[137:133] | - { 2'd0, - sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023, - _theResult___fst_exp__h141378 == 11'd0 && - guard__h133123 != 2'd0, - sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023 } ; - assign fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 = - fpu_madd_fState_S8$D_OUT[75:71] | - { 2'd0, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 == - 11'd2047 && - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h142620) == - 52'd0, - 1'd0, - fpu_madd_fState_S8$D_OUT[65:55] != 11'd2047 && - fpu_madd_fState_S8$D_OUT[2:1] != 2'b0 } ; - assign fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16 = - fpu_sqr64_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18 = - fpu_sqr64_fState_S3$D_OUT[121:111] - 11'd1023 ; - assign guardBC__h115666 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h131051 ; - assign guard__h132367 = fpu_madd_fState_S5$D_OUT[56:0] << x__h132471 ; - assign guard__h133123 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h141477 ; - assign guard__h155375 = - { IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34[1], - { _theResult___snd__h163287[3:0], 52'd0 } != 56'd0 } ; - assign guard__h164624 = - { IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38[1], - { sfdin__h172846[3:0], 52'd0 } != 56'd0 } ; - assign guard__h165222 = x__h165324 != 57'd0 ; - assign guard__h173663 = - { IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41[1], - { _theResult___snd__h181599[3:0], 52'd0 } != 56'd0 } ; - assign guard__h194013 = - { IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94[1], - { _theResult___snd__h201925[3:0], 52'd0 } != 56'd0 } ; - assign guard__h203262 = - { IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98[1], - { sfdin__h211484[3:0], 52'd0 } != 56'd0 } ; - assign guard__h203860 = x__h203962 != 57'd0 ; - assign guard__h212301 = - { IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h220237[3:0], 52'd0 } != 56'd0 } ; - assign guard__h232952 = - { IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61[1], - { _theResult___snd__h240864[3:0], 52'd0 } != 56'd0 } ; - assign guard__h242201 = - { IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65[1], - { sfdin__h250423[3:0], 52'd0 } != 56'd0 } ; - assign guard__h242799 = x__h242901 != 57'd0 ; - assign guard__h251240 = - { IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68[1], - { _theResult___snd__h259176[3:0], 52'd0 } != 56'd0 } ; - assign guard__h269587 = - { IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134[1], - { sfdin__h277680[32:0], 23'd0 } != 56'd0 } ; - assign guard__h278294 = - { IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136[1], - { _theResult___snd__h286293[32:0], 23'd0 } != 56'd0 } ; - assign guard__h287224 = - { IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140[1], - { sfdin__h295446[32:0], 23'd0 } != 56'd0 } ; - assign guard__h287822 = x__h287924 != 57'd0 ; - assign guard__h296060 = - { IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143[1], - { _theResult___snd__h304083[32:0], 23'd0 } != 56'd0 } ; - assign guard__h33946 = x__h42705 ; - assign guard__h86435 = x__h95138 ; - assign iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 = - iFifo$D_OUT[102:95] - 8'd127 ; - assign iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 = - iFifo$D_OUT[167:160] - 8'd127 ; - assign iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 = - iFifo$D_OUT[37:30] - 8'd127 ; - assign out___1_sfd__h144235 = { iFifo$D_OUT[159:137], 29'd0 } ; - assign out___1_sfd__h182875 = { iFifo$D_OUT[94:72], 29'd0 } ; - assign out___1_sfd__h221814 = { iFifo$D_OUT[29:7], 29'd0 } ; - assign out_exp__h142544 = - fpu_madd_fState_S8$D_OUT[3] ? - _theResult___exp__h142541 : - fpu_madd_fState_S8$D_OUT[65:55] ; - assign out_exp__h163984 = - _theResult___snd__h163287[5] ? - _theResult___exp__h163981 : - _theResult___fst_exp__h163336 ; - assign out_exp__h173574 = - sfdin__h172846[5] ? - _theResult___exp__h173571 : - _theResult___fst_exp__h172852 ; - assign out_exp__h182326 = - _theResult___snd__h181599[5] ? - _theResult___exp__h182323 : - _theResult___fst_exp__h181653 ; - assign out_exp__h202622 = - _theResult___snd__h201925[5] ? - _theResult___exp__h202619 : - _theResult___fst_exp__h201974 ; - assign out_exp__h212212 = - sfdin__h211484[5] ? - _theResult___exp__h212209 : - _theResult___fst_exp__h211490 ; - assign out_exp__h220964 = - _theResult___snd__h220237[5] ? - _theResult___exp__h220961 : - _theResult___fst_exp__h220291 ; - assign out_exp__h241561 = - _theResult___snd__h240864[5] ? - _theResult___exp__h241558 : - _theResult___fst_exp__h240913 ; - assign out_exp__h251151 = - sfdin__h250423[5] ? - _theResult___exp__h251148 : - _theResult___fst_exp__h250429 ; - assign out_exp__h259903 = - _theResult___snd__h259176[5] ? - _theResult___exp__h259900 : - _theResult___fst_exp__h259230 ; - assign out_exp__h278205 = - sfdin__h277680[34] ? - _theResult___exp__h278202 : - _theResult___fst_exp__h277686 ; - assign out_exp__h286787 = - _theResult___snd__h286293[34] ? - _theResult___exp__h286784 : - _theResult___fst_exp__h286342 ; - assign out_exp__h295971 = - sfdin__h295446[34] ? - _theResult___exp__h295968 : - _theResult___fst_exp__h295452 ; - assign out_exp__h304607 = - _theResult___snd__h304083[34] ? - _theResult___exp__h304604 : - _theResult___fst_exp__h304137 ; - assign out_exp__h43478 = - fpu_div64_fState_S4$D_OUT[2] ? - _theResult___exp__h43475 : - fpu_div64_fState_S4$D_OUT[64:54] ; - assign out_exp__h95912 = - fpu_sqr64_fState_S4$D_OUT[2] ? - _theResult___exp__h95909 : - fpu_sqr64_fState_S4$D_OUT[64:54] ; - assign out_sfd__h142545 = - fpu_madd_fState_S8$D_OUT[3] ? - _theResult___sfd__h142542 : - fpu_madd_fState_S8$D_OUT[54:3] ; - assign out_sfd__h163985 = - _theResult___snd__h163287[5] ? - _theResult___sfd__h163982 : - _theResult___snd__h163287[56:5] ; - assign out_sfd__h173575 = - sfdin__h172846[5] ? - _theResult___sfd__h173572 : - sfdin__h172846[56:5] ; - assign out_sfd__h182327 = - _theResult___snd__h181599[5] ? - _theResult___sfd__h182324 : - _theResult___snd__h181599[56:5] ; - assign out_sfd__h202623 = - _theResult___snd__h201925[5] ? - _theResult___sfd__h202620 : - _theResult___snd__h201925[56:5] ; - assign out_sfd__h212213 = - sfdin__h211484[5] ? - _theResult___sfd__h212210 : - sfdin__h211484[56:5] ; - assign out_sfd__h220965 = - _theResult___snd__h220237[5] ? - _theResult___sfd__h220962 : - _theResult___snd__h220237[56:5] ; - assign out_sfd__h241562 = - _theResult___snd__h240864[5] ? - _theResult___sfd__h241559 : - _theResult___snd__h240864[56:5] ; - assign out_sfd__h251152 = - sfdin__h250423[5] ? - _theResult___sfd__h251149 : - sfdin__h250423[56:5] ; - assign out_sfd__h259904 = - _theResult___snd__h259176[5] ? - _theResult___sfd__h259901 : - _theResult___snd__h259176[56:5] ; - assign out_sfd__h278206 = - sfdin__h277680[34] ? - _theResult___sfd__h278203 : - sfdin__h277680[56:34] ; - assign out_sfd__h286788 = - _theResult___snd__h286293[34] ? - _theResult___sfd__h286785 : - _theResult___snd__h286293[56:34] ; - assign out_sfd__h295972 = - sfdin__h295446[34] ? - _theResult___sfd__h295969 : - sfdin__h295446[56:34] ; - assign out_sfd__h304608 = - _theResult___snd__h304083[34] ? - _theResult___sfd__h304605 : - _theResult___snd__h304083[56:34] ; - assign out_sfd__h43479 = - fpu_div64_fState_S4$D_OUT[2] ? - _theResult___sfd__h43476 : - fpu_div64_fState_S4$D_OUT[53:2] ; - assign out_sfd__h95913 = - fpu_sqr64_fState_S4$D_OUT[2] ? - _theResult___sfd__h95910 : - fpu_sqr64_fState_S4$D_OUT[53:2] ; - assign r__h1659 = r__h1663 + rg_b ; - assign r__h1663 = { 1'd0, rg_r_1[115:1] } ; - assign r__h1724 = - r__h1753 + - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign r__h1753 = - { 1'd0, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69[115:1] } ; - assign resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 = - resWire$wget[4:0] | - { (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 } ; - assign resWirewget_BITS_67_TO_57_MINUS_1023__q137 = - resWire$wget[67:57] - 11'd1023 ; - assign result__h132372 = - { fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[56:1], - fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[0] | - guard__h132367 != 57'd0 } ; - assign result__h165227 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[0] | - guard__h165222 } ; - assign result__h203865 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[0] | - guard__h203860 } ; - assign result__h242804 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[0] | - guard__h242799 } ; - assign result__h287827 = - { _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[56:1], - _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[0] | - guard__h287822 } ; - assign result__h32617 = { _theResult____h32523[57:1], 1'd1 } ; - assign result__h32648 = - { 1'd0, - value__h32661[56:1], - value__h32661[0] | sfdlsb__h32643 } ; - assign result__h32823 = - (IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] == - 57'd0) ? - 58'd0 : - 58'd1 ; - assign result__h85925 = { x__h85931[58:1], 1'd1 } ; - assign rg_index_1_4_PLUS_1_6_ULE_58___d37 = rg_index_1 + 6'd1 <= 6'd58 ; - assign rg_index_1_4_ULE_58___d38 = rg_index_1 <= 6'd58 ; - assign rg_index_PLUS_1_ULE_57___d6 = rg_index + 6'd1 <= 6'd57 ; - assign rg_index_ULE_57___d7 = rg_index <= 6'd57 ; - assign rg_q_PLUS_NEG_INV_rg_q_59_60___d561 = rg_q + -(~rg_q) ; - assign rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63 = rg_s < sum__h1606 ; - assign s__h1658 = rg_s - sum__h1606 ; - assign s__h1723 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 - - sum__h1710 ; - assign sfdA__h131577 = - { 1'b0, - fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } ; - assign sfdA__h2035 = - { fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0, - fpu_div64_fOperands_S0$D_OUT[118:67] } ; - assign sfdA__h2039 = sfdA__h2035 << b__h4039 ; - assign sfdBC__h115662 = - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ? - fpu_madd_fProd_S3$D_OUT : - _theResult___fst__h116827 ; - assign sfdBC__h131578 = - { 1'b0, - fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } ; - assign sfdB__h2036 = - { fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0, - fpu_div64_fOperands_S0$D_OUT[54:3] } ; - assign sfdB__h2041 = sfdB__h2036 << b__h11457 ; - assign sfd___1__h60702 = { 1'd0, sfd__h44953[57:1] } ; - assign sfd__h133119 = - fpu_madd_fState_S7$D_OUT[128] ? - fpu_madd_fState_S7$D_OUT[56:0] : - fpu_madd_fState_S7$D_OUT[113:57] ; - assign sfd__h142040 = - { 1'b0, - fpu_madd_fState_S8$D_OUT[65:55] != 11'd0, - fpu_madd_fState_S8$D_OUT[54:3] } + - 54'd1 ; - assign sfd__h144536 = { value__h148923, 32'd0 } ; - assign sfd__h163354 = - { 1'b0, - _theResult___fst_exp__h163336 != 11'd0, - _theResult___snd__h163287[56:5] } + - 54'd1 ; - assign sfd__h172944 = - { 1'b0, - _theResult___fst_exp__h172852 != 11'd0, - sfdin__h172846[56:5] } + - 54'd1 ; - assign sfd__h181672 = - { 1'b0, - _theResult___fst_exp__h181653 != 11'd0, - _theResult___snd__h181599[56:5] } + - 54'd1 ; - assign sfd__h183176 = { value__h187561, 32'd0 } ; - assign sfd__h18934 = { 1'd1, fpu_div64_fOperands_S0$D_OUT[117:67] } ; - assign sfd__h18937 = { 1'd1, fpu_div64_fOperands_S0$D_OUT[53:3] } ; - assign sfd__h201992 = - { 1'b0, - _theResult___fst_exp__h201974 != 11'd0, - _theResult___snd__h201925[56:5] } + - 54'd1 ; - assign sfd__h211582 = - { 1'b0, - _theResult___fst_exp__h211490 != 11'd0, - sfdin__h211484[56:5] } + - 54'd1 ; - assign sfd__h220310 = - { 1'b0, - _theResult___fst_exp__h220291 != 11'd0, - _theResult___snd__h220237[56:5] } + - 54'd1 ; - assign sfd__h222115 = { value__h226500, 32'd0 } ; - assign sfd__h240931 = - { 1'b0, - _theResult___fst_exp__h240913 != 11'd0, - _theResult___snd__h240864[56:5] } + - 54'd1 ; - assign sfd__h250521 = - { 1'b0, - _theResult___fst_exp__h250429 != 11'd0, - sfdin__h250423[56:5] } + - 54'd1 ; - assign sfd__h259249 = - { 1'b0, - _theResult___fst_exp__h259230 != 11'd0, - _theResult___snd__h259176[56:5] } + - 54'd1 ; - assign sfd__h261975 = { value__h270197, 3'd0 } ; - assign sfd__h277778 = - { 1'b0, - _theResult___fst_exp__h277686 != 8'd0, - sfdin__h277680[56:34] } + - 25'd1 ; - assign sfd__h286360 = - { 1'b0, - _theResult___fst_exp__h286342 != 8'd0, - _theResult___snd__h286293[56:34] } + - 25'd1 ; - assign sfd__h295544 = - { 1'b0, - _theResult___fst_exp__h295452 != 8'd0, - sfdin__h295446[56:34] } + - 25'd1 ; - assign sfd__h304156 = - { 1'b0, - _theResult___fst_exp__h304137 != 8'd0, - _theResult___snd__h304083[56:34] } + - 25'd1 ; - assign sfd__h304707 = - (resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h261925 : - _theResult___fst_sfd__h304701 ; - assign sfd__h42982 = - { 1'b0, - fpu_div64_fState_S4$D_OUT[64:54] != 11'd0, - fpu_div64_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfd__h44951 = { value__h53174, 4'd0 } ; - assign sfd__h44953 = sfd__h44951 << x__h60732 ; - assign sfd__h45004 = { 1'd1, fpu_sqr64_fOperand_S0$D_OUT[53:3] } ; - assign sfd__h95416 = - { 1'b0, - fpu_sqr64_fState_S4$D_OUT[64:54] != 11'd0, - fpu_sqr64_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfd__h99402 = { 1'd1, _theResult___fst_sfd__h96608[50:0] } ; - assign sfd__h99405 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[117:67] } ; - assign sfd__h99408 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[53:3] } ; - assign sfdin__h130943 = - sfdBC__h115662[105] ? - _theResult___snd__h130966 : - _theResult___snd__h130980 ; - assign sfdin__h141369 = - sfd__h133119[56] ? - _theResult___snd__h141392 : - _theResult___snd__h141406 ; - assign sfdin__h172846 = - _theResult____h164614[56] ? - _theResult___snd__h172863 : - _theResult___snd__h172874 ; - assign sfdin__h211484 = - _theResult____h203252[56] ? - _theResult___snd__h211501 : - _theResult___snd__h211512 ; - assign sfdin__h250423 = - _theResult____h242191[56] ? - _theResult___snd__h250440 : - _theResult___snd__h250451 ; - assign sfdin__h277680 = - _theResult____h269577[56] ? - _theResult___snd__h277697 : - _theResult___snd__h277708 ; - assign sfdin__h295446 = - _theResult____h287214[56] ? - _theResult___snd__h295463 : - _theResult___snd__h295474 ; - assign sfdin__h34118 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___snd_snd_snd__h33963 : - fpu_div64_fState_S3$D_OUT[57:0] ; - assign sfdin__h42327 = - sfdin__h34118[57] ? - _theResult___snd__h42350 : - _theResult___snd__h42365 ; - assign sfdin__h94744 = - fpu_sqr64_fState_S3$D_OUT[58] ? - _theResult___snd__h94767 : - _theResult___snd__h94782 ; - assign sfdlsb__h116825 = x__h116896 != 106'd0 ; - assign sfdlsb__h32643 = x__h32762 != 58'd0 ; - assign sum__h1606 = rg_r_1 + rg_b ; - assign sum__h1710 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 + - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign theResult___fst_exp2290_MINUS_1023__q11 = - _theResult___fst_exp__h42290 - 11'd1023 ; - assign value41307_BITS_10_TO_0_MINUS_1023__q28 = - value__h141307[10:0] - 11'd1023 ; - assign value_BIT_52___h53270 = fpu_sqr64_fOperand_S0$D_OUT[65:55] != 11'd0 ; - assign value__h130883 = fpu_madd_fState_S3$D_OUT[12:0] + 13'd1023 ; - assign value__h141307 = fpu_madd_fState_S7$D_OUT[126:114] + 13'd1023 ; - assign value__h148923 = - { 1'b0, iFifo$D_OUT[167:160] != 8'd0, iFifo$D_OUT[159:137] } ; - assign value__h187561 = - { 1'b0, iFifo$D_OUT[102:95] != 8'd0, iFifo$D_OUT[94:72] } ; - assign value__h226500 = - { 1'b0, iFifo$D_OUT[37:30] != 8'd0, iFifo$D_OUT[29:7] } ; - assign value__h270197 = - { 1'b0, resWire$wget[67:57] != 11'd0, resWire$wget[56:5] } ; - assign value__h31374 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 + - 13'd1023 ; - assign value__h31429 = { 1'b0, sfdA__h2039 } ; - assign value__h31550 = - 13'd7170 - - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ; - assign value__h32541 = rg_r[115] ? rg_r + b__h32583 : rg_r ; - assign value__h32661 = - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] >> - fpu_div64_fState_S2$D_OUT[10:0] ; - assign value__h53174 = - { 1'b0, - value_BIT_52___h53270, - fpu_sqr64_fOperand_S0$D_OUT[54:3] } ; - assign x__h114243 = - { fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0, - fpu_madd_fOperand_S0$D_OUT[118:67] } ; - assign x__h114255 = - { fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0, - fpu_madd_fOperand_S0$D_OUT[54:3] } ; - assign x__h116896 = fpu_madd_fProd_S3$D_OUT << x__h116929 ; - assign x__h116929 = - 13'd106 - - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ; - assign x__h131406 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - _theResult___snd_snd_snd__h131369 : - 2'd3 ; - assign x__h131940 = - { 1'b0, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - { fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } : - { fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } } ; - assign x__h131944 = - { 1'b0, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - { fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } : - { fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } } ; - assign x__h132359 = - fpu_madd_fState_S5$D_OUT[215] ? - fpu_madd_fState_S5$D_OUT[56:0] : - (((fpu_madd_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ? - result__h132372 : - ((fpu_madd_fState_S5$D_OUT[56:0] == 57'd0) ? - fpu_madd_fState_S5$D_OUT[56:0] : - 57'd1)) ; - assign x__h132471 = 13'd57 - fpu_madd_fState_S5$D_OUT[126:114] ; - assign x__h132871 = - fpu_madd_fState_S6$D_OUT[113:57] + - fpu_madd_fState_S6$D_OUT[56:0] ; - assign x__h132880 = - fpu_madd_fState_S6$D_OUT[113:57] - - fpu_madd_fState_S6$D_OUT[56:0] ; - assign x__h141760 = fpu_madd_fState_S7$D_OUT[202] ? 2'd0 : guard__h133123 ; - assign x__h165324 = sfd__h144536 << x__h165357 ; - assign x__h165357 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ; - assign x__h203962 = sfd__h183176 << x__h203995 ; - assign x__h203995 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ; - assign x__h242901 = sfd__h222115 << x__h242934 ; - assign x__h242934 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ; - assign x__h287924 = sfd__h261975 << x__h287957 ; - assign x__h287957 = - 12'd57 - - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ; - assign x__h31426 = { value__h31429, 60'd0 } ; - assign x__h31487 = { sfdB__h2041, 4'b0 } ; - assign x__h31541 = - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363 ? - 11'd0 : - _theResult___fst__h31322 ; - assign x__h32762 = - { 1'd0, - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] } << - x__h32769 ; - assign x__h32769 = 11'd58 - fpu_div64_fState_S2$D_OUT[10:0] ; - assign x__h33052 = - (value__h32541[114:58] == 57'd0) ? - _theResult____h32523 : - result__h32617 ; - assign x__h42705 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h42439 ; - assign x__h52551 = x__h52569 + 13'd1024 ; - assign x__h52569 = - { IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17[11], - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17 } ; - assign x__h60693 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195[0] ? - sfd__h44953 : - sfd___1__h60702 ; - assign x__h60732 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 - - 6'd1 ; - assign x__h85465 = - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342[0] ? - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 + - 7'd1 : - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 ; - assign x__h85931 = rg_res[116] ? rg_res[115:0] : 116'd0 ; - assign x__h86149 = (rg_s == 116'd0) ? x__h85931[58:0] : result__h85925 ; - assign x__h95138 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h94856 ; - assign x__h96539 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[193:183] : - 11'd0 ; - always@(fpu_div64_fState_S4$D_OUT or - out_sfd__h43479 or _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - fpu_div64_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - out_sfd__h43479; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - _theResult___sfd__h43476; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 = - fpu_div64_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 = - _theResult___sfd__h43476; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 or - _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h43554 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1; - 3'd1: - _theResult___fst_sfd__h43554 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2; - 3'd2: - _theResult___fst_sfd__h43554 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[53:2] : - _theResult___sfd__h43476; - 3'd3: - _theResult___fst_sfd__h43554 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[53:2] : - (fpu_div64_fState_S4$D_OUT[65] ? - _theResult___sfd__h43476 : - fpu_div64_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h43554 = fpu_div64_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h43554 = 52'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - out_sfd__h95913 or _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - fpu_sqr64_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - out_sfd__h95913; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - _theResult___sfd__h95910; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 = - fpu_sqr64_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 = - _theResult___sfd__h95910; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 or - _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h95988 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3; - 3'd1: - _theResult___fst_sfd__h95988 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4; - 3'd2: - _theResult___fst_sfd__h95988 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - _theResult___sfd__h95910; - 3'd3: - _theResult___fst_sfd__h95988 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - _theResult___sfd__h95910 : - fpu_sqr64_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h95988 = fpu_sqr64_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h95988 = 52'd0; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - out_sfd__h142545 or _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - fpu_madd_fState_S8$D_OUT[54:3]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - out_sfd__h142545; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - _theResult___sfd__h142542; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 = - fpu_madd_fState_S8$D_OUT[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 = - _theResult___sfd__h142542; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 or - _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_sfd__h142620 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5; - 3'd1: - _theResult___fst_sfd__h142620 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6; - 3'd2: - _theResult___fst_sfd__h142620 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___sfd__h142542; - 3'd3: - _theResult___fst_sfd__h142620 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[54:3] : - (fpu_madd_fState_S8$D_OUT[66] ? - _theResult___sfd__h142542 : - fpu_madd_fState_S8$D_OUT[54:3]); - 3'd4: _theResult___fst_sfd__h142620 = fpu_madd_fState_S8$D_OUT[54:3]; - default: _theResult___fst_sfd__h142620 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h148291 = 11'd2047; - 3'd2: - _theResult___fst_exp__h148291 = - iFifo$D_OUT[168] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h148291 = - iFifo$D_OUT[168] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h148291 = 11'd2046; - default: _theResult___fst_exp__h148291 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h148292 = 52'd0; - 3'd2: - _theResult___fst_sfd__h148292 = - iFifo$D_OUT[168] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h148292 = - iFifo$D_OUT[168] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h148292 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h148292 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h186931 = 11'd2047; - 3'd2: - _theResult___fst_exp__h186931 = - iFifo$D_OUT[103] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h186931 = - iFifo$D_OUT[103] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h186931 = 11'd2046; - default: _theResult___fst_exp__h186931 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h225870 = 11'd2047; - 3'd2: - _theResult___fst_exp__h225870 = - iFifo$D_OUT[38] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h225870 = - iFifo$D_OUT[38] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h225870 = 11'd2046; - default: _theResult___fst_exp__h225870 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h186932 = 52'd0; - 3'd2: - _theResult___fst_sfd__h186932 = - iFifo$D_OUT[103] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h186932 = - iFifo$D_OUT[103] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h186932 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h186932 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h225871 = 52'd0; - 3'd2: - _theResult___fst_sfd__h225871 = - iFifo$D_OUT[38] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h225871 = - iFifo$D_OUT[38] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h225871 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h225871 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_exp__h19467 = 11'd2047; - 3'd2: - _theResult___fst_exp__h19467 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 11'd2047 : - 11'd2046; - 3'd3: - _theResult___fst_exp__h19467 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 11'd2046 : - 11'd2047; - 3'd4: _theResult___fst_exp__h19467 = 11'd2046; - default: _theResult___fst_exp__h19467 = 11'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_sfd__h19468 = 52'd0; - 3'd2: - _theResult___fst_sfd__h19468 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'd3: - _theResult___fst_sfd__h19468 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'hFFFFFFFFFFFFF : - 52'd0; - 3'd4: _theResult___fst_sfd__h19468 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h19468 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0: _theResult___fst_sfd__h19957 = 52'd0; - 3'd1: _theResult___fst_sfd__h19957 = 52'd1; - 3'd2: - _theResult___fst_sfd__h19957 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd1 : - 52'd0; - 3'd3: - _theResult___fst_sfd__h19957 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd0 : - 52'd1; - default: _theResult___fst_sfd__h19957 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 = - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405; - default: CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 = - fpu_div64_fOperands_S0$D_OUT[2:0] == 3'd4 && - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - out_exp__h43478 or _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - fpu_div64_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - out_exp__h43478; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - _theResult___exp__h43475; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 = - fpu_div64_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 = - _theResult___exp__h43475; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 or - _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h43553 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14; - 3'd1: - _theResult___fst_exp__h43553 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15; - 3'd2: - _theResult___fst_exp__h43553 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[64:54] : - _theResult___exp__h43475; - 3'd3: - _theResult___fst_exp__h43553 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[64:54] : - (fpu_div64_fState_S4$D_OUT[65] ? - _theResult___exp__h43475 : - fpu_div64_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h43553 = fpu_div64_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h43553 = 11'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - out_exp__h95912 or _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - fpu_sqr64_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - out_exp__h95912; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - _theResult___exp__h95909; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 = - fpu_sqr64_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 = - _theResult___exp__h95909; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 or - _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h95987 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21; - 3'd1: - _theResult___fst_exp__h95987 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22; - 3'd2: - _theResult___fst_exp__h95987 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - _theResult___exp__h95909; - 3'd3: - _theResult___fst_exp__h95987 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - _theResult___exp__h95909 : - fpu_sqr64_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h95987 = fpu_sqr64_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h95987 = 11'd0; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - out_exp__h142544 or _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - fpu_madd_fState_S8$D_OUT[65:55]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - out_exp__h142544; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - _theResult___exp__h142541; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 = - fpu_madd_fState_S8$D_OUT[65:55]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 = - _theResult___exp__h142541; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 or - _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_exp__h142619 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31; - 3'd1: - _theResult___fst_exp__h142619 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32; - 3'd2: - _theResult___fst_exp__h142619 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[65:55] : - _theResult___exp__h142541; - 3'd3: - _theResult___fst_exp__h142619 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[65:55] : - (fpu_madd_fState_S8$D_OUT[66] ? - _theResult___exp__h142541 : - fpu_madd_fState_S8$D_OUT[65:55]); - 3'd4: _theResult___fst_exp__h142619 = fpu_madd_fState_S8$D_OUT[65:55]; - default: _theResult___fst_exp__h142619 = 11'd0; - endcase - end - always@(guard__h155375 or - _theResult___fst_exp__h163336 or - out_exp__h163984 or _theResult___exp__h163981) - begin - case (guard__h155375) - 2'b0, 2'b01: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - _theResult___fst_exp__h163336; - 2'b10: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - out_exp__h163984; - 2'b11: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - _theResult___exp__h163981; - endcase - end - always@(guard__h155375 or - _theResult___fst_exp__h163336 or _theResult___exp__h163981) - begin - case (guard__h155375) - 2'b0: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 = - _theResult___fst_exp__h163336; - 2'b01, 2'b10, 2'b11: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 = - _theResult___exp__h163981; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 or - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 or - _theResult___fst_exp__h163336) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h164059 = - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42; - 3'd1: - _theResult___fst_exp__h164059 = - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43; - 3'd2: - _theResult___fst_exp__h164059 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690; - 3'd3: - _theResult___fst_exp__h164059 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692; - 3'd4: _theResult___fst_exp__h164059 = _theResult___fst_exp__h163336; - default: _theResult___fst_exp__h164059 = 11'd0; - endcase - end - always@(guard__h164624 or - _theResult___fst_exp__h172852 or - out_exp__h173574 or _theResult___exp__h173571) - begin - case (guard__h164624) - 2'b0, 2'b01: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - _theResult___fst_exp__h172852; - 2'b10: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - out_exp__h173574; - 2'b11: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - _theResult___exp__h173571; - endcase - end - always@(guard__h164624 or - _theResult___fst_exp__h172852 or _theResult___exp__h173571) - begin - case (guard__h164624) - 2'b0: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 = - _theResult___fst_exp__h172852; - 2'b01, 2'b10, 2'b11: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 = - _theResult___exp__h173571; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 or - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 or - _theResult___fst_exp__h172852) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h173649 = - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44; - 3'd1: - _theResult___fst_exp__h173649 = - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45; - 3'd2: - _theResult___fst_exp__h173649 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729; - 3'd3: - _theResult___fst_exp__h173649 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731; - 3'd4: _theResult___fst_exp__h173649 = _theResult___fst_exp__h172852; - default: _theResult___fst_exp__h173649 = 11'd0; - endcase - end - always@(guard__h173663 or - _theResult___fst_exp__h181653 or - out_exp__h182326 or _theResult___exp__h182323) - begin - case (guard__h173663) - 2'b0, 2'b01: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - _theResult___fst_exp__h181653; - 2'b10: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - out_exp__h182326; - 2'b11: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - _theResult___exp__h182323; - endcase - end - always@(guard__h173663 or - _theResult___fst_exp__h181653 or _theResult___exp__h182323) - begin - case (guard__h173663) - 2'b0: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 = - _theResult___fst_exp__h181653; - 2'b01, 2'b10, 2'b11: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 = - _theResult___exp__h182323; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 or - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 or - _theResult___fst_exp__h181653) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h182401 = - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46; - 3'd1: - _theResult___fst_exp__h182401 = - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47; - 3'd2: - _theResult___fst_exp__h182401 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760; - 3'd3: - _theResult___fst_exp__h182401 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762; - 3'd4: _theResult___fst_exp__h182401 = _theResult___fst_exp__h181653; - default: _theResult___fst_exp__h182401 = 11'd0; - endcase - end - always@(guard__h155375 or - _theResult___snd__h163287 or - out_sfd__h163985 or _theResult___sfd__h163982) - begin - case (guard__h155375) - 2'b0, 2'b01: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - _theResult___snd__h163287[56:5]; - 2'b10: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - out_sfd__h163985; - 2'b11: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - _theResult___sfd__h163982; - endcase - end - always@(guard__h155375 or - _theResult___snd__h163287 or _theResult___sfd__h163982) - begin - case (guard__h155375) - 2'b0: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 = - _theResult___snd__h163287[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 = - _theResult___sfd__h163982; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 or - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 or - _theResult___snd__h163287) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h164060 = - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48; - 3'd1: - _theResult___fst_sfd__h164060 = - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49; - 3'd2: - _theResult___fst_sfd__h164060 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786; - 3'd3: - _theResult___fst_sfd__h164060 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788; - 3'd4: _theResult___fst_sfd__h164060 = _theResult___snd__h163287[56:5]; - default: _theResult___fst_sfd__h164060 = 52'd0; - endcase - end - always@(guard__h164624 or - sfdin__h172846 or out_sfd__h173575 or _theResult___sfd__h173572) - begin - case (guard__h164624) - 2'b0, 2'b01: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - sfdin__h172846[56:5]; - 2'b10: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - out_sfd__h173575; - 2'b11: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - _theResult___sfd__h173572; - endcase - end - always@(guard__h164624 or sfdin__h172846 or _theResult___sfd__h173572) - begin - case (guard__h164624) - 2'b0: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 = - sfdin__h172846[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 = - _theResult___sfd__h173572; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 or - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 or - sfdin__h172846) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h173650 = - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50; - 3'd1: - _theResult___fst_sfd__h173650 = - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51; - 3'd2: - _theResult___fst_sfd__h173650 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813; - 3'd3: - _theResult___fst_sfd__h173650 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815; - 3'd4: _theResult___fst_sfd__h173650 = sfdin__h172846[56:5]; - default: _theResult___fst_sfd__h173650 = 52'd0; - endcase - end - always@(guard__h173663 or - _theResult___snd__h181599 or - out_sfd__h182327 or _theResult___sfd__h182324) - begin - case (guard__h173663) - 2'b0, 2'b01: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - _theResult___snd__h181599[56:5]; - 2'b10: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - out_sfd__h182327; - 2'b11: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - _theResult___sfd__h182324; - endcase - end - always@(guard__h173663 or - _theResult___snd__h181599 or _theResult___sfd__h182324) - begin - case (guard__h173663) - 2'b0: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 = - _theResult___snd__h181599[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 = - _theResult___sfd__h182324; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 or - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 or - _theResult___snd__h181599) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h182402 = - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52; - 3'd1: - _theResult___fst_sfd__h182402 = - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53; - 3'd2: - _theResult___fst_sfd__h182402 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832; - 3'd3: - _theResult___fst_sfd__h182402 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834; - 3'd4: _theResult___fst_sfd__h182402 = _theResult___snd__h181599[56:5]; - default: _theResult___fst_sfd__h182402 = 52'd0; - endcase - end - always@(guard__h155375 or iFifo$D_OUT) - begin - case (guard__h155375) - 2'b0, 2'b01, 2'b10: - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 = - guard__h155375 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 or - guard__h155375) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - (guard__h155375 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h155375 == 2'b01 || guard__h155375 == 2'b10 || - guard__h155375 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 = - iFifo$D_OUT[168]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h164624 or iFifo$D_OUT) - begin - case (guard__h164624) - 2'b0, 2'b01, 2'b10: - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 = - guard__h164624 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 or - guard__h164624) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - (guard__h164624 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h164624 == 2'b01 || guard__h164624 == 2'b10 || - guard__h164624 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h173663 or iFifo$D_OUT) - begin - case (guard__h173663) - 2'b0, 2'b01, 2'b10: - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 = - guard__h173663 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 or - guard__h173663) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - (guard__h173663 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h173663 == 2'b01 || guard__h173663 == 2'b10 || - guard__h173663 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h232952 or - _theResult___fst_exp__h240913 or - out_exp__h241561 or _theResult___exp__h241558) - begin - case (guard__h232952) - 2'b0, 2'b01: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - _theResult___fst_exp__h240913; - 2'b10: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - out_exp__h241561; - 2'b11: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - _theResult___exp__h241558; - endcase - end - always@(guard__h232952 or - _theResult___fst_exp__h240913 or _theResult___exp__h241558) - begin - case (guard__h232952) - 2'b0: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 = - _theResult___fst_exp__h240913; - 2'b01, 2'b10, 2'b11: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 = - _theResult___exp__h241558; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 or - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 or - _theResult___fst_exp__h240913) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h241636 = - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69; - 3'd1: - _theResult___fst_exp__h241636 = - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70; - 3'd2: - _theResult___fst_exp__h241636 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398; - 3'd3: - _theResult___fst_exp__h241636 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400; - 3'd4: _theResult___fst_exp__h241636 = _theResult___fst_exp__h240913; - default: _theResult___fst_exp__h241636 = 11'd0; - endcase - end - always@(guard__h242201 or - _theResult___fst_exp__h250429 or - out_exp__h251151 or _theResult___exp__h251148) - begin - case (guard__h242201) - 2'b0, 2'b01: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - _theResult___fst_exp__h250429; - 2'b10: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - out_exp__h251151; - 2'b11: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - _theResult___exp__h251148; - endcase - end - always@(guard__h242201 or - _theResult___fst_exp__h250429 or _theResult___exp__h251148) - begin - case (guard__h242201) - 2'b0: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 = - _theResult___fst_exp__h250429; - 2'b01, 2'b10, 2'b11: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 = - _theResult___exp__h251148; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 or - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 or - _theResult___fst_exp__h250429) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h251226 = - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71; - 3'd1: - _theResult___fst_exp__h251226 = - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72; - 3'd2: - _theResult___fst_exp__h251226 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436; - 3'd3: - _theResult___fst_exp__h251226 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438; - 3'd4: _theResult___fst_exp__h251226 = _theResult___fst_exp__h250429; - default: _theResult___fst_exp__h251226 = 11'd0; - endcase - end - always@(guard__h251240 or - _theResult___fst_exp__h259230 or - out_exp__h259903 or _theResult___exp__h259900) - begin - case (guard__h251240) - 2'b0, 2'b01: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - _theResult___fst_exp__h259230; - 2'b10: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - out_exp__h259903; - 2'b11: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - _theResult___exp__h259900; - endcase - end - always@(guard__h251240 or - _theResult___fst_exp__h259230 or _theResult___exp__h259900) - begin - case (guard__h251240) - 2'b0: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 = - _theResult___fst_exp__h259230; - 2'b01, 2'b10, 2'b11: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 = - _theResult___exp__h259900; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 or - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 or - _theResult___fst_exp__h259230) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h259978 = - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73; - 3'd1: - _theResult___fst_exp__h259978 = - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74; - 3'd2: - _theResult___fst_exp__h259978 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467; - 3'd3: - _theResult___fst_exp__h259978 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469; - 3'd4: _theResult___fst_exp__h259978 = _theResult___fst_exp__h259230; - default: _theResult___fst_exp__h259978 = 11'd0; - endcase - end - always@(guard__h232952 or - _theResult___snd__h240864 or - out_sfd__h241562 or _theResult___sfd__h241559) - begin - case (guard__h232952) - 2'b0, 2'b01: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - _theResult___snd__h240864[56:5]; - 2'b10: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - out_sfd__h241562; - 2'b11: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - _theResult___sfd__h241559; - endcase - end - always@(guard__h232952 or - _theResult___snd__h240864 or _theResult___sfd__h241559) - begin - case (guard__h232952) - 2'b0: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 = - _theResult___snd__h240864[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 = - _theResult___sfd__h241559; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 or - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 or - _theResult___snd__h240864) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h241637 = - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75; - 3'd1: - _theResult___fst_sfd__h241637 = - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76; - 3'd2: - _theResult___fst_sfd__h241637 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493; - 3'd3: - _theResult___fst_sfd__h241637 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495; - 3'd4: _theResult___fst_sfd__h241637 = _theResult___snd__h240864[56:5]; - default: _theResult___fst_sfd__h241637 = 52'd0; - endcase - end - always@(guard__h242201 or - sfdin__h250423 or out_sfd__h251152 or _theResult___sfd__h251149) - begin - case (guard__h242201) - 2'b0, 2'b01: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - sfdin__h250423[56:5]; - 2'b10: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - out_sfd__h251152; - 2'b11: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - _theResult___sfd__h251149; - endcase - end - always@(guard__h242201 or sfdin__h250423 or _theResult___sfd__h251149) - begin - case (guard__h242201) - 2'b0: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 = - sfdin__h250423[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 = - _theResult___sfd__h251149; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 or - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 or - sfdin__h250423) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h251227 = - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77; - 3'd1: - _theResult___fst_sfd__h251227 = - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78; - 3'd2: - _theResult___fst_sfd__h251227 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519; - 3'd3: - _theResult___fst_sfd__h251227 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521; - 3'd4: _theResult___fst_sfd__h251227 = sfdin__h250423[56:5]; - default: _theResult___fst_sfd__h251227 = 52'd0; - endcase - end - always@(guard__h251240 or - _theResult___snd__h259176 or - out_sfd__h259904 or _theResult___sfd__h259901) - begin - case (guard__h251240) - 2'b0, 2'b01: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - _theResult___snd__h259176[56:5]; - 2'b10: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - out_sfd__h259904; - 2'b11: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - _theResult___sfd__h259901; - endcase - end - always@(guard__h251240 or - _theResult___snd__h259176 or _theResult___sfd__h259901) - begin - case (guard__h251240) - 2'b0: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 = - _theResult___snd__h259176[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 = - _theResult___sfd__h259901; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 or - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 or - _theResult___snd__h259176) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h259979 = - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79; - 3'd1: - _theResult___fst_sfd__h259979 = - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80; - 3'd2: - _theResult___fst_sfd__h259979 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538; - 3'd3: - _theResult___fst_sfd__h259979 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540; - 3'd4: _theResult___fst_sfd__h259979 = _theResult___snd__h259176[56:5]; - default: _theResult___fst_sfd__h259979 = 52'd0; - endcase - end - always@(guard__h232952 or iFifo$D_OUT) - begin - case (guard__h232952) - 2'b0, 2'b01, 2'b10: - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 = - guard__h232952 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 or - guard__h232952) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - (guard__h232952 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h232952 == 2'b01 || guard__h232952 == 2'b10 || - guard__h232952 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 = - iFifo$D_OUT[38]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h242201 or iFifo$D_OUT) - begin - case (guard__h242201) - 2'b0, 2'b01, 2'b10: - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 = - guard__h242201 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 or - guard__h242201) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - (guard__h242201 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h242201 == 2'b01 || guard__h242201 == 2'b10 || - guard__h242201 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h251240 or iFifo$D_OUT) - begin - case (guard__h251240) - 2'b0, 2'b01, 2'b10: - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 = - guard__h251240 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 or - guard__h251240) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - (guard__h251240 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h251240 == 2'b01 || guard__h251240 == 2'b10 || - guard__h251240 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h232952 or iFifo$D_OUT) - begin - case (guard__h232952) - 2'b0, 2'b01, 2'b10: - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 = - guard__h232952 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 or - guard__h232952) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - (guard__h232952 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h232952 != 2'b01 && guard__h232952 != 2'b10 && - guard__h232952 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h242201 or iFifo$D_OUT) - begin - case (guard__h242201) - 2'b0, 2'b01, 2'b10: - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 = - guard__h242201 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 or - guard__h242201) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - (guard__h242201 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h242201 != 2'b01 && guard__h242201 != 2'b10 && - guard__h242201 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h251240 or iFifo$D_OUT) - begin - case (guard__h251240) - 2'b0, 2'b01, 2'b10: - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 = - guard__h251240 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 or - guard__h251240) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - (guard__h251240 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h251240 != 2'b01 && guard__h251240 != 2'b10 && - guard__h251240 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 = - !iFifo$D_OUT[38]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h194013 or - _theResult___fst_exp__h201974 or - out_exp__h202622 or _theResult___exp__h202619) - begin - case (guard__h194013) - 2'b0, 2'b01: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - _theResult___fst_exp__h201974; - 2'b10: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - out_exp__h202622; - 2'b11: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - _theResult___exp__h202619; - endcase - end - always@(guard__h194013 or - _theResult___fst_exp__h201974 or _theResult___exp__h202619) - begin - case (guard__h194013) - 2'b0: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 = - _theResult___fst_exp__h201974; - 2'b01, 2'b10, 2'b11: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 = - _theResult___exp__h202619; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 or - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 or - _theResult___fst_exp__h201974) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h202697 = - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102; - 3'd1: - _theResult___fst_exp__h202697 = - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103; - 3'd2: - _theResult___fst_exp__h202697 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173; - 3'd3: - _theResult___fst_exp__h202697 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175; - 3'd4: _theResult___fst_exp__h202697 = _theResult___fst_exp__h201974; - default: _theResult___fst_exp__h202697 = 11'd0; - endcase - end - always@(guard__h203262 or - _theResult___fst_exp__h211490 or - out_exp__h212212 or _theResult___exp__h212209) - begin - case (guard__h203262) - 2'b0, 2'b01: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - _theResult___fst_exp__h211490; - 2'b10: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - out_exp__h212212; - 2'b11: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - _theResult___exp__h212209; - endcase - end - always@(guard__h203262 or - _theResult___fst_exp__h211490 or _theResult___exp__h212209) - begin - case (guard__h203262) - 2'b0: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 = - _theResult___fst_exp__h211490; - 2'b01, 2'b10, 2'b11: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 = - _theResult___exp__h212209; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 or - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 or - _theResult___fst_exp__h211490) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h212287 = - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104; - 3'd1: - _theResult___fst_exp__h212287 = - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105; - 3'd2: - _theResult___fst_exp__h212287 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211; - 3'd3: - _theResult___fst_exp__h212287 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213; - 3'd4: _theResult___fst_exp__h212287 = _theResult___fst_exp__h211490; - default: _theResult___fst_exp__h212287 = 11'd0; - endcase - end - always@(guard__h212301 or - _theResult___fst_exp__h220291 or - out_exp__h220964 or _theResult___exp__h220961) - begin - case (guard__h212301) - 2'b0, 2'b01: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - _theResult___fst_exp__h220291; - 2'b10: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - out_exp__h220964; - 2'b11: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - _theResult___exp__h220961; - endcase - end - always@(guard__h212301 or - _theResult___fst_exp__h220291 or _theResult___exp__h220961) - begin - case (guard__h212301) - 2'b0: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 = - _theResult___fst_exp__h220291; - 2'b01, 2'b10, 2'b11: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 = - _theResult___exp__h220961; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 or - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 or - _theResult___fst_exp__h220291) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h221039 = - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106; - 3'd1: - _theResult___fst_exp__h221039 = - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107; - 3'd2: - _theResult___fst_exp__h221039 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242; - 3'd3: - _theResult___fst_exp__h221039 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244; - 3'd4: _theResult___fst_exp__h221039 = _theResult___fst_exp__h220291; - default: _theResult___fst_exp__h221039 = 11'd0; - endcase - end - always@(guard__h194013 or - _theResult___snd__h201925 or - out_sfd__h202623 or _theResult___sfd__h202620) - begin - case (guard__h194013) - 2'b0, 2'b01: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - _theResult___snd__h201925[56:5]; - 2'b10: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - out_sfd__h202623; - 2'b11: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - _theResult___sfd__h202620; - endcase - end - always@(guard__h194013 or - _theResult___snd__h201925 or _theResult___sfd__h202620) - begin - case (guard__h194013) - 2'b0: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 = - _theResult___snd__h201925[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 = - _theResult___sfd__h202620; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 or - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 or - _theResult___snd__h201925) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h202698 = - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108; - 3'd1: - _theResult___fst_sfd__h202698 = - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109; - 3'd2: - _theResult___fst_sfd__h202698 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268; - 3'd3: - _theResult___fst_sfd__h202698 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270; - 3'd4: _theResult___fst_sfd__h202698 = _theResult___snd__h201925[56:5]; - default: _theResult___fst_sfd__h202698 = 52'd0; - endcase - end - always@(guard__h203262 or - sfdin__h211484 or out_sfd__h212213 or _theResult___sfd__h212210) - begin - case (guard__h203262) - 2'b0, 2'b01: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - sfdin__h211484[56:5]; - 2'b10: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - out_sfd__h212213; - 2'b11: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - _theResult___sfd__h212210; - endcase - end - always@(guard__h203262 or sfdin__h211484 or _theResult___sfd__h212210) - begin - case (guard__h203262) - 2'b0: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 = - sfdin__h211484[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 = - _theResult___sfd__h212210; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 or - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 or - sfdin__h211484) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h212288 = - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110; - 3'd1: - _theResult___fst_sfd__h212288 = - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111; - 3'd2: - _theResult___fst_sfd__h212288 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294; - 3'd3: - _theResult___fst_sfd__h212288 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296; - 3'd4: _theResult___fst_sfd__h212288 = sfdin__h211484[56:5]; - default: _theResult___fst_sfd__h212288 = 52'd0; - endcase - end - always@(guard__h212301 or - _theResult___snd__h220237 or - out_sfd__h220965 or _theResult___sfd__h220962) - begin - case (guard__h212301) - 2'b0, 2'b01: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - _theResult___snd__h220237[56:5]; - 2'b10: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - out_sfd__h220965; - 2'b11: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - _theResult___sfd__h220962; - endcase - end - always@(guard__h212301 or - _theResult___snd__h220237 or _theResult___sfd__h220962) - begin - case (guard__h212301) - 2'b0: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 = - _theResult___snd__h220237[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 = - _theResult___sfd__h220962; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 or - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 or - _theResult___snd__h220237) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h221040 = - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112; - 3'd1: - _theResult___fst_sfd__h221040 = - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113; - 3'd2: - _theResult___fst_sfd__h221040 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313; - 3'd3: - _theResult___fst_sfd__h221040 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315; - 3'd4: _theResult___fst_sfd__h221040 = _theResult___snd__h220237[56:5]; - default: _theResult___fst_sfd__h221040 = 52'd0; - endcase - end - always@(guard__h194013 or iFifo$D_OUT) - begin - case (guard__h194013) - 2'b0, 2'b01, 2'b10: - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 = - guard__h194013 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 or - guard__h194013) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - (guard__h194013 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h194013 == 2'b01 || guard__h194013 == 2'b10 || - guard__h194013 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 = - iFifo$D_OUT[103]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h203262 or iFifo$D_OUT) - begin - case (guard__h203262) - 2'b0, 2'b01, 2'b10: - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 = - guard__h203262 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 or - guard__h203262) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - (guard__h203262 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h203262 == 2'b01 || guard__h203262 == 2'b10 || - guard__h203262 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h212301 or iFifo$D_OUT) - begin - case (guard__h212301) - 2'b0, 2'b01, 2'b10: - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 = - guard__h212301 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 or - guard__h212301) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - (guard__h212301 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h212301 == 2'b01 || guard__h212301 == 2'b10 || - guard__h212301 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h194013 or iFifo$D_OUT) - begin - case (guard__h194013) - 2'b0, 2'b01, 2'b10: - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 = - guard__h194013 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 or - guard__h194013) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - (guard__h194013 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h194013 != 2'b01 && guard__h194013 != 2'b10 && - guard__h194013 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 = - !iFifo$D_OUT[103]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(guard__h203262 or iFifo$D_OUT) - begin - case (guard__h203262) - 2'b0, 2'b01, 2'b10: - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 = - guard__h203262 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 or - guard__h203262) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - (guard__h203262 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h203262 != 2'b01 && guard__h203262 != 2'b10 && - guard__h203262 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(guard__h212301 or iFifo$D_OUT) - begin - case (guard__h212301) - 2'b0, 2'b01, 2'b10: - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 = - guard__h212301 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 or - guard__h212301) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - (guard__h212301 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h212301 != 2'b01 && guard__h212301 != 2'b10 && - guard__h212301 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(fpu_madd_fState_S8$D_OUT) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 = - fpu_madd_fState_S8$D_OUT[66]; - 2'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 = - fpu_madd_fState_S8$D_OUT[2:1] == 2'b11 && - fpu_madd_fState_S8$D_OUT[66]; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126; - 3'd1: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[66] : - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b01 || - fpu_madd_fState_S8$D_OUT[2:1] == 2'b10 || - fpu_madd_fState_S8$D_OUT[2:1] == 2'b11) && - fpu_madd_fState_S8$D_OUT[66]; - 3'd2, 3'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - fpu_madd_fState_S8$D_OUT[66]; - default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - fpu_madd_fState_S8$D_OUT[70:68] == 3'd4 && - fpu_madd_fState_S8$D_OUT[66]; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 or - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848; - 4'd5, 4'd7: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555; - 4'd6: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618; - default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - fpu_madd_fState_S8$D_OUT[3] ? - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 : - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 = - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 = - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130; - 3'd1: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131; - 3'd2: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[65:3] : - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - 3'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[65:3] : - (fpu_madd_fState_S8$D_OUT[66] ? - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 : - fpu_madd_fState_S8$D_OUT[65:3]); - 3'd4: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - fpu_madd_fState_S8$D_OUT[65:3]; - default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - 63'd0; - endcase - end - always@(iFifo$D_OUT or - fpu_madd_fOperand_S0$FULL_N or - fpu_div64_fOperands_S0$FULL_N or fpu_sqr64_fOperand_S0$FULL_N) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1, 4'd2, 4'd5, 4'd6, 4'd7: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_madd_fOperand_S0$FULL_N; - 4'd3: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_div64_fOperands_S0$FULL_N; - 4'd4: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_sqr64_fOperand_S0$FULL_N; - default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - iFifo$D_OUT[3:0] != 4'd8 || fpu_madd_fOperand_S0$FULL_N; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1: _theResult___fst_exp__h269559 = 8'd255; - 3'd2: - _theResult___fst_exp__h269559 = resWire$wget[68] ? 8'd254 : 8'd255; - 3'd3: - _theResult___fst_exp__h269559 = resWire$wget[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h269559 = 8'd254; - default: _theResult___fst_exp__h269559 = 8'd0; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1: _theResult___fst_sfd__h269560 = 23'd0; - 3'd2: - _theResult___fst_sfd__h269560 = - resWire$wget[68] ? 23'd8388607 : 23'd0; - 3'd3: - _theResult___fst_sfd__h269560 = - resWire$wget[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h269560 = 23'd8388607; - default: _theResult___fst_sfd__h269560 = 23'd0; - endcase - end - always@(guard__h269587 or resWire$wget) - begin - case (guard__h269587) - 2'b0, 2'b01, 2'b10: - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 = - resWire$wget[68]; - 2'd3: - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 = - guard__h269587 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 or - guard__h269587) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - (guard__h269587 == 2'b0) ? - resWire$wget[68] : - (guard__h269587 == 2'b01 || guard__h269587 == 2'b10 || - guard__h269587 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h269587 or resWire$wget) - begin - case (guard__h269587) - 2'b0, 2'b01, 2'b10: - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 = - !resWire$wget[68]; - 2'd3: - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 = - guard__h269587 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 or - guard__h269587) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - (guard__h269587 == 2'b0) ? - !resWire$wget[68] : - guard__h269587 != 2'b01 && guard__h269587 != 2'b10 && - guard__h269587 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h278294 or resWire$wget) - begin - case (guard__h278294) - 2'b0, 2'b01, 2'b10: - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 = - resWire$wget[68]; - 2'd3: - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 = - guard__h278294 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 or - guard__h278294) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - (guard__h278294 == 2'b0) ? - resWire$wget[68] : - (guard__h278294 == 2'b01 || guard__h278294 == 2'b10 || - guard__h278294 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h278294 or resWire$wget) - begin - case (guard__h278294) - 2'b0, 2'b01, 2'b10: - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 = - !resWire$wget[68]; - 2'd3: - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 = - guard__h278294 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 or - guard__h278294) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - (guard__h278294 == 2'b0) ? - !resWire$wget[68] : - guard__h278294 != 2'b01 && guard__h278294 != 2'b10 && - guard__h278294 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h287224 or resWire$wget) - begin - case (guard__h287224) - 2'b0, 2'b01, 2'b10: - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 = - resWire$wget[68]; - 2'd3: - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 = - guard__h287224 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 or - guard__h287224) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - (guard__h287224 == 2'b0) ? - resWire$wget[68] : - (guard__h287224 == 2'b01 || guard__h287224 == 2'b10 || - guard__h287224 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h287224 or resWire$wget) - begin - case (guard__h287224) - 2'b0, 2'b01, 2'b10: - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 = - !resWire$wget[68]; - 2'd3: - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 = - guard__h287224 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 or - guard__h287224) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - (guard__h287224 == 2'b0) ? - !resWire$wget[68] : - guard__h287224 != 2'b01 && guard__h287224 != 2'b10 && - guard__h287224 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h296060 or resWire$wget) - begin - case (guard__h296060) - 2'b0, 2'b01, 2'b10: - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 = - resWire$wget[68]; - 2'd3: - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 = - guard__h296060 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 or - guard__h296060) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - (guard__h296060 == 2'b0) ? - resWire$wget[68] : - (guard__h296060 == 2'b01 || guard__h296060 == 2'b10 || - guard__h296060 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h296060 or resWire$wget) - begin - case (guard__h296060) - 2'b0, 2'b01, 2'b10: - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 = - !resWire$wget[68]; - 2'd3: - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 = - guard__h296060 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 or - guard__h296060) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - (guard__h296060 == 2'b0) ? - !resWire$wget[68] : - guard__h296060 != 2'b01 && guard__h296060 != 2'b10 && - guard__h296060 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h278294 or - _theResult___fst_exp__h286342 or - out_exp__h286787 or _theResult___exp__h286784) - begin - case (guard__h278294) - 2'b0, 2'b01: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - _theResult___fst_exp__h286342; - 2'b10: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - out_exp__h286787; - 2'b11: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - _theResult___exp__h286784; - endcase - end - always@(guard__h278294 or - _theResult___fst_exp__h286342 or _theResult___exp__h286784) - begin - case (guard__h278294) - 2'b0: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 = - _theResult___fst_exp__h286342; - 2'b01, 2'b10, 2'b11: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 = - _theResult___exp__h286784; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 or - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 or - _theResult___fst_exp__h286342) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h286862 = - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152; - 3'd1: - _theResult___fst_exp__h286862 = - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153; - 3'd2: - _theResult___fst_exp__h286862 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479; - 3'd3: - _theResult___fst_exp__h286862 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481; - 3'd4: _theResult___fst_exp__h286862 = _theResult___fst_exp__h286342; - default: _theResult___fst_exp__h286862 = 8'd0; - endcase - end - always@(guard__h269587 or - _theResult___fst_exp__h277686 or - out_exp__h278205 or _theResult___exp__h278202) - begin - case (guard__h269587) - 2'b0, 2'b01: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - _theResult___fst_exp__h277686; - 2'b10: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - out_exp__h278205; - 2'b11: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - _theResult___exp__h278202; - endcase - end - always@(guard__h269587 or - _theResult___fst_exp__h277686 or _theResult___exp__h278202) - begin - case (guard__h269587) - 2'b0: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 = - _theResult___fst_exp__h277686; - 2'b01, 2'b10, 2'b11: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 = - _theResult___exp__h278202; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 or - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 or - _theResult___fst_exp__h277686) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h278280 = - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154; - 3'd1: - _theResult___fst_exp__h278280 = - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155; - 3'd2: - _theResult___fst_exp__h278280 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448; - 3'd3: - _theResult___fst_exp__h278280 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450; - 3'd4: _theResult___fst_exp__h278280 = _theResult___fst_exp__h277686; - default: _theResult___fst_exp__h278280 = 8'd0; - endcase - end - always@(guard__h287224 or - _theResult___fst_exp__h295452 or - out_exp__h295971 or _theResult___exp__h295968) - begin - case (guard__h287224) - 2'b0, 2'b01: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - _theResult___fst_exp__h295452; - 2'b10: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - out_exp__h295971; - 2'b11: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - _theResult___exp__h295968; - endcase - end - always@(guard__h287224 or - _theResult___fst_exp__h295452 or _theResult___exp__h295968) - begin - case (guard__h287224) - 2'b0: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 = - _theResult___fst_exp__h295452; - 2'b01, 2'b10, 2'b11: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 = - _theResult___exp__h295968; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 or - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 or - _theResult___fst_exp__h295452) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h296046 = - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156; - 3'd1: - _theResult___fst_exp__h296046 = - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157; - 3'd2: - _theResult___fst_exp__h296046 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518; - 3'd3: - _theResult___fst_exp__h296046 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520; - 3'd4: _theResult___fst_exp__h296046 = _theResult___fst_exp__h295452; - default: _theResult___fst_exp__h296046 = 8'd0; - endcase - end - always@(guard__h296060 or - _theResult___fst_exp__h304137 or - out_exp__h304607 or _theResult___exp__h304604) - begin - case (guard__h296060) - 2'b0, 2'b01: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - _theResult___fst_exp__h304137; - 2'b10: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - out_exp__h304607; - 2'b11: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - _theResult___exp__h304604; - endcase - end - always@(guard__h296060 or - _theResult___fst_exp__h304137 or _theResult___exp__h304604) - begin - case (guard__h296060) - 2'b0: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 = - _theResult___fst_exp__h304137; - 2'b01, 2'b10, 2'b11: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 = - _theResult___exp__h304604; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 or - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 or - _theResult___fst_exp__h304137) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h304682 = - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158; - 3'd1: - _theResult___fst_exp__h304682 = - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159; - 3'd2: - _theResult___fst_exp__h304682 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549; - 3'd3: - _theResult___fst_exp__h304682 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551; - 3'd4: _theResult___fst_exp__h304682 = _theResult___fst_exp__h304137; - default: _theResult___fst_exp__h304682 = 8'd0; - endcase - end - always@(guard__h278294 or - _theResult___snd__h286293 or - out_sfd__h286788 or _theResult___sfd__h286785) - begin - case (guard__h278294) - 2'b0, 2'b01: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - _theResult___snd__h286293[56:34]; - 2'b10: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - out_sfd__h286788; - 2'b11: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - _theResult___sfd__h286785; - endcase - end - always@(guard__h278294 or - _theResult___snd__h286293 or _theResult___sfd__h286785) - begin - case (guard__h278294) - 2'b0: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 = - _theResult___snd__h286293[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 = - _theResult___sfd__h286785; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 or - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 or - _theResult___snd__h286293) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h286863 = - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160; - 3'd1: - _theResult___fst_sfd__h286863 = - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161; - 3'd2: - _theResult___fst_sfd__h286863 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595; - 3'd3: - _theResult___fst_sfd__h286863 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597; - 3'd4: _theResult___fst_sfd__h286863 = _theResult___snd__h286293[56:34]; - default: _theResult___fst_sfd__h286863 = 23'd0; - endcase - end - always@(guard__h269587 or - sfdin__h277680 or out_sfd__h278206 or _theResult___sfd__h278203) - begin - case (guard__h269587) - 2'b0, 2'b01: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - sfdin__h277680[56:34]; - 2'b10: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - out_sfd__h278206; - 2'b11: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - _theResult___sfd__h278203; - endcase - end - always@(guard__h269587 or sfdin__h277680 or _theResult___sfd__h278203) - begin - case (guard__h269587) - 2'b0: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 = - sfdin__h277680[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 = - _theResult___sfd__h278203; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 or - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 or - sfdin__h277680) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h278281 = - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162; - 3'd1: - _theResult___fst_sfd__h278281 = - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163; - 3'd2: - _theResult___fst_sfd__h278281 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576; - 3'd3: - _theResult___fst_sfd__h278281 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578; - 3'd4: _theResult___fst_sfd__h278281 = sfdin__h277680[56:34]; - default: _theResult___fst_sfd__h278281 = 23'd0; - endcase - end - always@(guard__h287224 or - sfdin__h295446 or out_sfd__h295972 or _theResult___sfd__h295969) - begin - case (guard__h287224) - 2'b0, 2'b01: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - sfdin__h295446[56:34]; - 2'b10: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - out_sfd__h295972; - 2'b11: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - _theResult___sfd__h295969; - endcase - end - always@(guard__h287224 or sfdin__h295446 or _theResult___sfd__h295969) - begin - case (guard__h287224) - 2'b0: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 = - sfdin__h295446[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 = - _theResult___sfd__h295969; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 or - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 or - sfdin__h295446) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h296047 = - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164; - 3'd1: - _theResult___fst_sfd__h296047 = - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165; - 3'd2: - _theResult___fst_sfd__h296047 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622; - 3'd3: - _theResult___fst_sfd__h296047 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624; - 3'd4: _theResult___fst_sfd__h296047 = sfdin__h295446[56:34]; - default: _theResult___fst_sfd__h296047 = 23'd0; - endcase - end - always@(guard__h296060 or - _theResult___snd__h304083 or - out_sfd__h304608 or _theResult___sfd__h304605) - begin - case (guard__h296060) - 2'b0, 2'b01: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - _theResult___snd__h304083[56:34]; - 2'b10: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - out_sfd__h304608; - 2'b11: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - _theResult___sfd__h304605; - endcase - end - always@(guard__h296060 or - _theResult___snd__h304083 or _theResult___sfd__h304605) - begin - case (guard__h296060) - 2'b0: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 = - _theResult___snd__h304083[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 = - _theResult___sfd__h304605; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 or - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 or - _theResult___snd__h304083) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h304683 = - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166; - 3'd1: - _theResult___fst_sfd__h304683 = - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167; - 3'd2: - _theResult___fst_sfd__h304683 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641; - 3'd3: - _theResult___fst_sfd__h304683 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643; - 3'd4: _theResult___fst_sfd__h304683 = _theResult___snd__h304083[56:34]; - default: _theResult___fst_sfd__h304683 = 23'd0; - endcase - end - always@(fpu_div64_fState_S4$D_OUT) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 = - fpu_div64_fState_S4$D_OUT[65]; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 = - fpu_div64_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_div64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - 3'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[64:2] : - (fpu_div64_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 : - fpu_div64_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - fpu_div64_fState_S4$D_OUT[64:2]; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - 63'd0; - endcase - end - always@(fpu_div64_fState_S4$D_OUT) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 = - fpu_div64_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 = - fpu_div64_fState_S4$D_OUT[1:0] == 2'b11 && - fpu_div64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - fpu_div64_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - fpu_div64_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 : - fpu_div64_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 = - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 or - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - { CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 }; - 3'd1: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[65:2] : - { (fpu_div64_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_div64_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_div64_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_div64_fState_S4$D_OUT[65], - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 }; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - { CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 }; - endcase - end - always@(fpu_div64_fState_S3$D_OUT) - begin - case (fpu_div64_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174 = - fpu_div64_fState_S3$D_OUT[121]; - default: CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174 = - fpu_div64_fState_S3$D_OUT[124:122] == 3'd4 && - fpu_div64_fState_S3$D_OUT[121]; - endcase - end - always@(fpu_div64_fState_S3$D_OUT) - begin - case (fpu_div64_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'h7FF0000000000000; - 3'd2: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - fpu_div64_fState_S3$D_OUT[121] ? - 63'h7FEFFFFFFFFFFFFF : - 63'h7FF0000000000000; - 3'd3: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - fpu_div64_fState_S3$D_OUT[121] ? - 63'h7FF0000000000000 : - 63'h7FEFFFFFFFFFFFFF; - 3'd4: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'h7FEFFFFFFFFFFFFF; - default: CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'd0; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 or - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378) - begin - case (iFifo$D_OUT[3:0]) - 4'd0: - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330; - 4'd1: - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - iFifo$D_OUT[136] ? - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 : - { iFifo$D_OUT[136] || !iFifo$D_OUT[135], - iFifo$D_OUT[134:72] }; - default: CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1: - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 = - 64'h3FF0000000000000; - default: CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 = - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 = - fpu_sqr64_fState_S4$D_OUT[65]; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 = - fpu_sqr64_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_sqr64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - 3'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[64:2] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 : - fpu_sqr64_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - fpu_sqr64_fState_S4$D_OUT[64:2]; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - 63'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 = - fpu_sqr64_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 = - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b11 && - fpu_sqr64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - fpu_sqr64_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - fpu_sqr64_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 : - fpu_sqr64_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 = - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - { CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 }; - 3'd1: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[65:2] : - { (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_sqr64_fState_S4$D_OUT[65], - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 }; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - { CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - crg_done <= `BSV_ASSIGNMENT_DELAY 1'd0; - crg_done_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (crg_done$EN) crg_done <= `BSV_ASSIGNMENT_DELAY crg_done$D_IN; - if (crg_done_1$EN) - crg_done_1 <= `BSV_ASSIGNMENT_DELAY crg_done_1$D_IN; - if (rg_busy$EN) rg_busy <= `BSV_ASSIGNMENT_DELAY rg_busy$D_IN; - if (rg_busy_1$EN) rg_busy_1 <= `BSV_ASSIGNMENT_DELAY rg_busy_1$D_IN; - end - if (rg_b$EN) rg_b <= `BSV_ASSIGNMENT_DELAY rg_b$D_IN; - if (rg_d$EN) rg_d <= `BSV_ASSIGNMENT_DELAY rg_d$D_IN; - if (rg_index$EN) rg_index <= `BSV_ASSIGNMENT_DELAY rg_index$D_IN; - if (rg_index_1$EN) rg_index_1 <= `BSV_ASSIGNMENT_DELAY rg_index_1$D_IN; - if (rg_q$EN) rg_q <= `BSV_ASSIGNMENT_DELAY rg_q$D_IN; - if (rg_r$EN) rg_r <= `BSV_ASSIGNMENT_DELAY rg_r$D_IN; - if (rg_r_1$EN) rg_r_1 <= `BSV_ASSIGNMENT_DELAY rg_r_1$D_IN; - if (rg_res$EN) rg_res <= `BSV_ASSIGNMENT_DELAY rg_res$D_IN; - if (rg_s$EN) rg_s <= `BSV_ASSIGNMENT_DELAY rg_s$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - crg_done = 1'h0; - crg_done_1 = 1'h0; - rg_b = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_busy = 1'h0; - rg_busy_1 = 1'h0; - rg_d = 58'h2AAAAAAAAAAAAAA; - rg_index = 6'h2A; - rg_index_1 = 6'h2A; - rg_q = 58'h2AAAAAAAAAAAAAA; - rg_r = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_r_1 = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_res = 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_s = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (fpu_div64_fResult_S5$EMPTY_N && fpu_madd_fResult_S9$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 29: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResDiv] and\n [RL_getResMAdd] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fpu_div64_fResult_S5$EMPTY_N && fpu_sqr64_fResult_S5$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 29: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResDiv] and [RL_getResSqr]\n ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fpu_sqr64_fResult_S5$EMPTY_N && fpu_madd_fResult_S9$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 40: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResSqr] and\n [RL_getResMAdd] ) fired in the same clock cycle.\n"); - end - // synopsys translate_on -endmodule // mkFPU - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric.v deleted file mode 100644 index 771fc0dc..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric.v +++ /dev/null @@ -1,8149 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 = - fabric_cfg_verbosity > 4'd1 ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - $display("%0d: %m::AXI4_Fabric.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v deleted file mode 100644 index 2e372865..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v +++ /dev/null @@ -1,7465 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_2x3(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8650; - reg [31 : 0] v__h9025; - reg [31 : 0] v__h9400; - reg [31 : 0] v__h9845; - reg [31 : 0] v__h10214; - reg [31 : 0] v__h10583; - reg [31 : 0] v__h11872; - reg [31 : 0] v__h12325; - reg [31 : 0] v__h12702; - reg [31 : 0] v__h12994; - reg [31 : 0] v__h13286; - reg [31 : 0] v__h13589; - reg [31 : 0] v__h13855; - reg [31 : 0] v__h14121; - reg [31 : 0] v__h14385; - reg [31 : 0] v__h14611; - reg [31 : 0] v__h15040; - reg [31 : 0] v__h15396; - reg [31 : 0] v__h15752; - reg [31 : 0] v__h16169; - reg [31 : 0] v__h16501; - reg [31 : 0] v__h16833; - reg [31 : 0] v__h17849; - reg [31 : 0] v__h18100; - reg [31 : 0] v__h18475; - reg [31 : 0] v__h18716; - reg [31 : 0] v__h19091; - reg [31 : 0] v__h19332; - reg [31 : 0] v__h19694; - reg [31 : 0] v__h19945; - reg [31 : 0] v__h20275; - reg [31 : 0] v__h20516; - reg [31 : 0] v__h20846; - reg [31 : 0] v__h21087; - reg [31 : 0] v__h21600; - reg [31 : 0] v__h22001; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8644; - reg [31 : 0] v__h9019; - reg [31 : 0] v__h9394; - reg [31 : 0] v__h9839; - reg [31 : 0] v__h10208; - reg [31 : 0] v__h10577; - reg [31 : 0] v__h11866; - reg [31 : 0] v__h12319; - reg [31 : 0] v__h12696; - reg [31 : 0] v__h12988; - reg [31 : 0] v__h13280; - reg [31 : 0] v__h13583; - reg [31 : 0] v__h13849; - reg [31 : 0] v__h14115; - reg [31 : 0] v__h14379; - reg [31 : 0] v__h14605; - reg [31 : 0] v__h15034; - reg [31 : 0] v__h15390; - reg [31 : 0] v__h15746; - reg [31 : 0] v__h16163; - reg [31 : 0] v__h16495; - reg [31 : 0] v__h16827; - reg [31 : 0] v__h17843; - reg [31 : 0] v__h18094; - reg [31 : 0] v__h18469; - reg [31 : 0] v__h18710; - reg [31 : 0] v__h19085; - reg [31 : 0] v__h19326; - reg [31 : 0] v__h19688; - reg [31 : 0] v__h19939; - reg [31 : 0] v__h20269; - reg [31 : 0] v__h20510; - reg [31 : 0] v__h20840; - reg [31 : 0] v__h21081; - reg [31 : 0] v__h21594; - reg [31 : 0] v__h21995; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11777, - x__h12230, - x__h17986, - x__h18612, - x__h19228, - x__h21532, - x__h21933; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - x1_avValue_rresp__h17964, - x1_avValue_rresp__h18590, - x1_avValue_rresp__h19206; - wire _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156, - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371, - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411, - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540, - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - 8'd0 : - x__h17986 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - 8'd0 : - x__h18612 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - 8'd0 : - x__h19228 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? - 8'd0 : - x__h11777 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ? - 8'd0 : - x__h12230 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ? - 8'd0 : - x__h21532 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ? - 8'd0 : - x__h21933 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - x1_avValue_rresp__h17964 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - x1_avValue_rresp__h18590 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - x1_avValue_rresp__h19206 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h17964 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18590 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19206 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11777 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12230 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h17986 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h18612 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19228 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21532 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h21933 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8650 = $stime; - #0; - end - v__h8644 = v__h8650 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8644, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9025 = $stime; - #0; - end - v__h9019 = v__h9025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9019, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9400 = $stime; - #0; - end - v__h9394 = v__h9400 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9394, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9845 = $stime; - #0; - end - v__h9839 = v__h9845 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9839, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10214 = $stime; - #0; - end - v__h10208 = v__h10214 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10208, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10583 = $stime; - #0; - end - v__h10577 = v__h10583 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10577, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h11872 = $stime; - #0; - end - v__h11866 = v__h11872 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h11866, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12325 = $stime; - #0; - end - v__h12319 = v__h12325 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12319, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12702 = $stime; - #0; - end - v__h12696 = v__h12702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12696, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h12994 = $stime; - #0; - end - v__h12988 = v__h12994 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12988, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13286 = $stime; - #0; - end - v__h13280 = v__h13286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13280, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13589 = $stime; - #0; - end - v__h13583 = v__h13589 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13583, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13855 = $stime; - #0; - end - v__h13849 = v__h13855 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13849, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14121 = $stime; - #0; - end - v__h14115 = v__h14121 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14115, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14385 = $stime; - #0; - end - v__h14379 = v__h14385 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14379, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14611 = $stime; - #0; - end - v__h14605 = v__h14611 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14605, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15040 = $stime; - #0; - end - v__h15034 = v__h15040 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15034, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15396 = $stime; - #0; - end - v__h15390 = v__h15396 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15390, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15752 = $stime; - #0; - end - v__h15746 = v__h15752 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15746, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16169 = $stime; - #0; - end - v__h16163 = v__h16169 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16163, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16501 = $stime; - #0; - end - v__h16495 = v__h16501 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16495, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16833 = $stime; - #0; - end - v__h16827 = v__h16833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16827, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h17849 = $stime; - #0; - end - v__h17843 = v__h17849 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h17843, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18100 = $stime; - #0; - end - v__h18094 = v__h18100 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18094, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18475 = $stime; - #0; - end - v__h18469 = v__h18475 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18469, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h18716 = $stime; - #0; - end - v__h18710 = v__h18716 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18710, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19091 = $stime; - #0; - end - v__h19085 = v__h19091 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19085, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19332 = $stime; - #0; - end - v__h19326 = v__h19332 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19326, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h19694 = $stime; - #0; - end - v__h19688 = v__h19694 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19688, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19945 = $stime; - #0; - end - v__h19939 = v__h19945 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19939, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20275 = $stime; - #0; - end - v__h20269 = v__h20275 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20269, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20516 = $stime; - #0; - end - v__h20510 = v__h20516 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20510, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h20846 = $stime; - #0; - end - v__h20840 = v__h20846 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20840, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21087 = $stime; - #0; - end - v__h21081 = v__h21087 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21081, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21600 = $stime; - #0; - end - v__h21594 = v__h21600 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21594, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22001 = $stime; - #0; - end - v__h21995 = v__h22001 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21995, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_2x3 - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v deleted file mode 100644 index ac19188b..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v +++ /dev/null @@ -1,8145 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_AXI4(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_AXI4 - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v deleted file mode 100644 index a238e586..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v +++ /dev/null @@ -1,249 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 32 -// read_rs1_port2 O 32 -// read_rs2 O 32 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 32 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// Combinational paths from inputs to outputs: -// read_rs1_rs1 -> read_rs1 -// read_rs1_port2_rs1 -> read_rs1_port2 -// read_rs2_rs2 -> read_rs2 -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkGPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [31 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [31 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [31 : 0] read_rs2; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [31 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [31 : 0] read_rs1, read_rs1_port2, read_rs2; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [31 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 32'd0 : regfile$D_OUT_3 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = - (read_rs1_port2_rs1 == 5'd0) ? 32'd0 : regfile$D_OUT_2 ; - - // value method read_rs2 - assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 32'd0 : regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd32), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs2_rs2 ; - assign regfile$ADDR_2 = read_rs1_port2_rs1 ; - assign regfile$ADDR_3 = read_rs1_rs1 ; - assign regfile$ADDR_4 = 5'h0 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkGPR_RegFile - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v deleted file mode 100644 index f4d13fdd..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 64 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 32 -// put_args_y_is_signed I 1 -// put_args_y I 32 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_32(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [31 : 0] put_args_x; - input put_args_y_is_signed; - input [31 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [63 : 0] result_value; - - // signals for module outputs - wire [63 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [63 : 0] m_rg_x; - wire [63 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [63 : 0] m_rg_xy; - wire [63 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [31 : 0] m_rg_y; - wire [31 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [63 : 0] xy___1__h654; - wire [31 : 0] _theResult___fst__h491, - _theResult___fst__h494, - _theResult___fst__h536, - _theResult___fst__h539, - _theResult___snd_fst__h531; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 32'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h654 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 32'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h491 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h539 : - _theResult___snd_fst__h531 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[31] != put_args_y[31] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 = - put_args_x_is_signed ? - put_args_x[31] : - put_args_y_is_signed && put_args_y[31] ; - assign _theResult___fst__h491 = - put_args_x_is_signed ? _theResult___fst__h494 : put_args_x ; - assign _theResult___fst__h494 = put_args_x[31] ? -put_args_x : put_args_x ; - assign _theResult___fst__h536 = - put_args_y_is_signed ? _theResult___fst__h539 : put_args_y ; - assign _theResult___fst__h539 = put_args_y[31] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h531 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h536 ; - assign xy___1__h654 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 64'hAAAAAAAAAAAAAAAA; - m_rg_xy = 64'hAAAAAAAAAAAAAAAA; - m_rg_y = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_32 - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v deleted file mode 100644 index 0b513191..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 128 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 64 -// put_args_y_is_signed I 1 -// put_args_y I 64 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_64(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [63 : 0] put_args_x; - input put_args_y_is_signed; - input [63 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [127 : 0] result_value; - - // signals for module outputs - wire [127 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [127 : 0] m_rg_x; - wire [127 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [127 : 0] m_rg_xy; - wire [127 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [63 : 0] m_rg_y; - wire [63 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [127 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [127 : 0] xy___1__h648; - wire [63 : 0] _theResult___fst__h488, - _theResult___fst__h491, - _theResult___fst__h533, - _theResult___fst__h536, - _theResult___snd_fst__h528; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 64'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h648 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 64'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h488 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h536 : - _theResult___snd_fst__h528 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[63] != put_args_y[63] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 = - put_args_x_is_signed ? - put_args_x[63] : - put_args_y_is_signed && put_args_y[63] ; - assign _theResult___fst__h488 = - put_args_x_is_signed ? _theResult___fst__h491 : put_args_x ; - assign _theResult___fst__h491 = put_args_x[63] ? -put_args_x : put_args_x ; - assign _theResult___fst__h533 = - put_args_y_is_signed ? _theResult___fst__h536 : put_args_y ; - assign _theResult___fst__h536 = put_args_y[63] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h528 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h533 ; - assign xy___1__h648 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_y = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_64 - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v deleted file mode 100644 index 1218855b..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v +++ /dev/null @@ -1,7786 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// valid O 1 -// addr O 32 reg -// word64 O 64 -// st_amo_val O 64 -// exc O 1 -// exc_code O 4 reg -// RDY_server_flush_request_put O 1 reg -// RDY_server_flush_response_get O 1 -// RDY_tlb_flush O 1 const -// mem_master_awvalid O 1 -// mem_master_awid O 4 reg -// mem_master_awaddr O 64 reg -// mem_master_awlen O 8 reg -// mem_master_awsize O 3 reg -// mem_master_awburst O 2 reg -// mem_master_awlock O 1 reg -// mem_master_awcache O 4 reg -// mem_master_awprot O 3 reg -// mem_master_awqos O 4 reg -// mem_master_awregion O 4 reg -// mem_master_wvalid O 1 -// mem_master_wid O 4 reg -// mem_master_wdata O 64 reg -// mem_master_wstrb O 8 reg -// mem_master_wlast O 1 reg -// mem_master_bready O 1 -// mem_master_arvalid O 1 -// mem_master_arid O 4 reg -// mem_master_araddr O 64 reg -// mem_master_arlen O 8 reg -// mem_master_arsize O 3 reg -// mem_master_arburst O 2 reg -// mem_master_arlock O 1 reg -// mem_master_arcache O 4 reg -// mem_master_arprot O 3 reg -// mem_master_arqos O 4 reg -// mem_master_arregion O 4 reg -// mem_master_rready O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_op I 2 -// req_f3 I 3 -// req_amo_funct7 I 7 reg -// req_addr I 32 -// req_st_value I 64 -// req_priv I 2 reg -// req_sstatus_SUM I 1 reg -// req_mstatus_MXR I 1 reg -// req_satp I 32 reg -// mem_master_awready I 1 -// mem_master_wready I 1 -// mem_master_bvalid I 1 -// mem_master_bid I 4 reg -// mem_master_bresp I 2 reg -// mem_master_arready I 1 -// mem_master_rvalid I 1 -// mem_master_rid I 4 reg -// mem_master_rdata I 64 reg -// mem_master_rresp I 2 reg -// mem_master_rlast I 1 reg -// EN_set_verbosity I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// EN_server_flush_request_put I 1 -// EN_server_flush_response_get I 1 -// EN_tlb_flush I 1 -// -// Combinational paths from inputs to outputs: -// (mem_master_awready, mem_master_wready) -> valid -// (mem_master_awready, mem_master_wready) -> word64 -// (mem_master_awready, mem_master_wready) -> st_amo_val -// (mem_master_awready, mem_master_wready) -> mem_master_bready -// (mem_master_awready, -// mem_master_wready, -// mem_master_arready, -// EN_req) -> mem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMMU_Cache(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_op, - req_f3, - req_amo_funct7, - req_addr, - req_st_value, - req_priv, - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - EN_req, - - valid, - - addr, - - word64, - - st_amo_val, - - exc, - - exc_code, - - EN_server_flush_request_put, - RDY_server_flush_request_put, - - EN_server_flush_response_get, - RDY_server_flush_response_get, - - EN_tlb_flush, - RDY_tlb_flush, - - mem_master_awvalid, - - mem_master_awid, - - mem_master_awaddr, - - mem_master_awlen, - - mem_master_awsize, - - mem_master_awburst, - - mem_master_awlock, - - mem_master_awcache, - - mem_master_awprot, - - mem_master_awqos, - - mem_master_awregion, - - mem_master_awready, - - mem_master_wvalid, - - mem_master_wid, - - mem_master_wdata, - - mem_master_wstrb, - - mem_master_wlast, - - mem_master_wready, - - mem_master_bvalid, - mem_master_bid, - mem_master_bresp, - - mem_master_bready, - - mem_master_arvalid, - - mem_master_arid, - - mem_master_araddr, - - mem_master_arlen, - - mem_master_arsize, - - mem_master_arburst, - - mem_master_arlock, - - mem_master_arcache, - - mem_master_arprot, - - mem_master_arqos, - - mem_master_arregion, - - mem_master_arready, - - mem_master_rvalid, - mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast, - - mem_master_rready); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [1 : 0] req_op; - input [2 : 0] req_f3; - input [6 : 0] req_amo_funct7; - input [31 : 0] req_addr; - input [63 : 0] req_st_value; - input [1 : 0] req_priv; - input req_sstatus_SUM; - input req_mstatus_MXR; - input [31 : 0] req_satp; - input EN_req; - - // value method valid - output valid; - - // value method addr - output [31 : 0] addr; - - // value method word64 - output [63 : 0] word64; - - // value method st_amo_val - output [63 : 0] st_amo_val; - - // value method exc - output exc; - - // value method exc_code - output [3 : 0] exc_code; - - // action method server_flush_request_put - input EN_server_flush_request_put; - output RDY_server_flush_request_put; - - // action method server_flush_response_get - input EN_server_flush_response_get; - output RDY_server_flush_response_get; - - // action method tlb_flush - input EN_tlb_flush; - output RDY_tlb_flush; - - // value method mem_master_m_awvalid - output mem_master_awvalid; - - // value method mem_master_m_awid - output [3 : 0] mem_master_awid; - - // value method mem_master_m_awaddr - output [63 : 0] mem_master_awaddr; - - // value method mem_master_m_awlen - output [7 : 0] mem_master_awlen; - - // value method mem_master_m_awsize - output [2 : 0] mem_master_awsize; - - // value method mem_master_m_awburst - output [1 : 0] mem_master_awburst; - - // value method mem_master_m_awlock - output mem_master_awlock; - - // value method mem_master_m_awcache - output [3 : 0] mem_master_awcache; - - // value method mem_master_m_awprot - output [2 : 0] mem_master_awprot; - - // value method mem_master_m_awqos - output [3 : 0] mem_master_awqos; - - // value method mem_master_m_awregion - output [3 : 0] mem_master_awregion; - - // value method mem_master_m_awuser - - // action method mem_master_m_awready - input mem_master_awready; - - // value method mem_master_m_wvalid - output mem_master_wvalid; - - // value method mem_master_m_wid - output [3 : 0] mem_master_wid; - - // value method mem_master_m_wdata - output [63 : 0] mem_master_wdata; - - // value method mem_master_m_wstrb - output [7 : 0] mem_master_wstrb; - - // value method mem_master_m_wlast - output mem_master_wlast; - - // value method mem_master_m_wuser - - // action method mem_master_m_wready - input mem_master_wready; - - // action method mem_master_m_bvalid - input mem_master_bvalid; - input [3 : 0] mem_master_bid; - input [1 : 0] mem_master_bresp; - - // value method mem_master_m_bready - output mem_master_bready; - - // value method mem_master_m_arvalid - output mem_master_arvalid; - - // value method mem_master_m_arid - output [3 : 0] mem_master_arid; - - // value method mem_master_m_araddr - output [63 : 0] mem_master_araddr; - - // value method mem_master_m_arlen - output [7 : 0] mem_master_arlen; - - // value method mem_master_m_arsize - output [2 : 0] mem_master_arsize; - - // value method mem_master_m_arburst - output [1 : 0] mem_master_arburst; - - // value method mem_master_m_arlock - output mem_master_arlock; - - // value method mem_master_m_arcache - output [3 : 0] mem_master_arcache; - - // value method mem_master_m_arprot - output [2 : 0] mem_master_arprot; - - // value method mem_master_m_arqos - output [3 : 0] mem_master_arqos; - - // value method mem_master_m_arregion - output [3 : 0] mem_master_arregion; - - // value method mem_master_m_aruser - - // action method mem_master_m_arready - input mem_master_arready; - - // action method mem_master_m_rvalid - input mem_master_rvalid; - input [3 : 0] mem_master_rid; - input [63 : 0] mem_master_rdata; - input [1 : 0] mem_master_rresp; - input mem_master_rlast; - - // value method mem_master_m_rready - output mem_master_rready; - - // signals for module outputs - reg [63 : 0] word64; - wire [63 : 0] mem_master_araddr, - mem_master_awaddr, - mem_master_wdata, - st_amo_val; - wire [31 : 0] addr; - wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; - wire [3 : 0] exc_code, - mem_master_arcache, - mem_master_arid, - mem_master_arqos, - mem_master_arregion, - mem_master_awcache, - mem_master_awid, - mem_master_awqos, - mem_master_awregion, - mem_master_wid; - wire [2 : 0] mem_master_arprot, - mem_master_arsize, - mem_master_awprot, - mem_master_awsize; - wire [1 : 0] mem_master_arburst, mem_master_awburst; - wire RDY_server_flush_request_put, - RDY_server_flush_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_verbosity, - RDY_tlb_flush, - exc, - mem_master_arlock, - mem_master_arvalid, - mem_master_awlock, - mem_master_awvalid, - mem_master_bready, - mem_master_rready, - mem_master_wlast, - mem_master_wvalid, - valid; - - // inlined wires - reg [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1; - wire [10 : 0] crg_sb_to_load_delay$port0__write_1, - crg_sb_to_load_delay$port2__read; - wire [3 : 0] ctr_wr_rsps_pending_crg$port1__write_1, - ctr_wr_rsps_pending_crg$port2__read, - ctr_wr_rsps_pending_crg$port3__read; - wire crg_sb_to_load_delay$EN_port1__write, - ctr_wr_rsps_pending_crg$EN_port0__write, - ctr_wr_rsps_pending_crg$EN_port2__write, - dw_valid$whas, - master_xactor_crg_rd_addr_full$EN_port0__write, - master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port1__read, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port0__write, - master_xactor_crg_rd_data_full$EN_port1__write, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port1__read, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port0__write, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$EN_port2__write, - master_xactor_crg_wr_addr_full$port1__read, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port0__write, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$EN_port2__write, - master_xactor_crg_wr_data_full$port1__read, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read, - master_xactor_crg_wr_resp_full$EN_port0__write, - master_xactor_crg_wr_resp_full$EN_port2__write, - master_xactor_crg_wr_resp_full$port1__read, - master_xactor_crg_wr_resp_full$port2__read, - master_xactor_crg_wr_resp_full$port3__read; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_sb_to_load_delay - reg [10 : 0] crg_sb_to_load_delay; - wire [10 : 0] crg_sb_to_load_delay$D_IN; - wire crg_sb_to_load_delay$EN; - - // register ctr_wr_rsps_pending_crg - reg [3 : 0] ctr_wr_rsps_pending_crg; - wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN; - wire ctr_wr_rsps_pending_crg$EN; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - reg [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - reg [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [76 : 0] master_xactor_rg_wr_data; - reg [76 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - - // register rg_addr - reg [31 : 0] rg_addr; - wire [31 : 0] rg_addr$D_IN; - wire rg_addr$EN; - - // register rg_amo_funct7 - reg [6 : 0] rg_amo_funct7; - wire [6 : 0] rg_amo_funct7$D_IN; - wire rg_amo_funct7$EN; - - // register rg_cset_in_cache - reg [6 : 0] rg_cset_in_cache; - wire [6 : 0] rg_cset_in_cache$D_IN; - wire rg_cset_in_cache$EN; - - // register rg_error_during_refill - reg rg_error_during_refill; - wire rg_error_during_refill$D_IN, rg_error_during_refill$EN; - - // register rg_exc_code - reg [3 : 0] rg_exc_code; - reg [3 : 0] rg_exc_code$D_IN; - wire rg_exc_code$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_ld_val - reg [63 : 0] rg_ld_val; - reg [63 : 0] rg_ld_val$D_IN; - wire rg_ld_val$EN; - - // register rg_lower_word32 - reg [31 : 0] rg_lower_word32; - wire [31 : 0] rg_lower_word32$D_IN; - wire rg_lower_word32$EN; - - // register rg_lower_word32_full - reg rg_lower_word32_full; - wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN; - - // register rg_lrsc_pa - reg [33 : 0] rg_lrsc_pa; - wire [33 : 0] rg_lrsc_pa$D_IN; - wire rg_lrsc_pa$EN; - - // register rg_lrsc_valid - reg rg_lrsc_valid; - wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_op - reg [1 : 0] rg_op; - wire [1 : 0] rg_op$D_IN; - wire rg_op$EN; - - // register rg_pa - reg [33 : 0] rg_pa; - wire [33 : 0] rg_pa$D_IN; - wire rg_pa$EN; - - // register rg_priv - reg [1 : 0] rg_priv; - wire [1 : 0] rg_priv$D_IN; - wire rg_priv$EN; - - // register rg_pte_pa - reg [33 : 0] rg_pte_pa; - wire [33 : 0] rg_pte_pa$D_IN; - wire rg_pte_pa$EN; - - // register rg_satp - reg [31 : 0] rg_satp; - wire [31 : 0] rg_satp$D_IN; - wire rg_satp$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_st_amo_val - reg [63 : 0] rg_st_amo_val; - wire [63 : 0] rg_st_amo_val$D_IN; - wire rg_st_amo_val$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_word64_set_in_cache - reg [8 : 0] rg_word64_set_in_cache; - wire [8 : 0] rg_word64_set_in_cache$D_IN; - wire rg_word64_set_in_cache$EN; - - // ports of submodule f_pte_writebacks - wire [65 : 0] f_pte_writebacks$D_IN, f_pte_writebacks$D_OUT; - wire f_pte_writebacks$CLR, - f_pte_writebacks$DEQ, - f_pte_writebacks$EMPTY_N, - f_pte_writebacks$ENQ, - f_pte_writebacks$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule ram_state_and_ctag_cset - wire [22 : 0] ram_state_and_ctag_cset$DIA, - ram_state_and_ctag_cset$DIB, - ram_state_and_ctag_cset$DOB; - wire [6 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB; - wire ram_state_and_ctag_cset$ENA, - ram_state_and_ctag_cset$ENB, - ram_state_and_ctag_cset$WEA, - ram_state_and_ctag_cset$WEB; - - // ports of submodule ram_word64_set - reg [63 : 0] ram_word64_set$DIB; - reg [8 : 0] ram_word64_set$ADDRB; - wire [63 : 0] ram_word64_set$DIA, ram_word64_set$DOB; - wire [8 : 0] ram_word64_set$ADDRA; - wire ram_word64_set$ENA, - ram_word64_set$ENB, - ram_word64_set$WEA, - ram_word64_set$WEB; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - wire soc_map$m_is_mem_addr; - - // ports of submodule tlb - reg [31 : 0] tlb$insert_pte; - reg [1 : 0] tlb$insert_level; - wire [68 : 0] tlb$lookup; - wire [33 : 0] tlb$insert_pte_pa; - wire [19 : 0] tlb$insert_vpn, tlb$lookup_vpn; - wire [8 : 0] tlb$insert_asid, tlb$lookup_asid; - wire tlb$EN_flush, tlb$EN_insert, tlb$RDY_insert, tlb$RDY_lookup; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_ST_AMO_response, - CAN_FIRE_RL_rl_cache_refill_rsps_loop, - CAN_FIRE_RL_rl_discard_write_rsp, - CAN_FIRE_RL_rl_drive_exception_rsp, - CAN_FIRE_RL_rl_io_AMO_SC_req, - CAN_FIRE_RL_rl_io_AMO_op_req, - CAN_FIRE_RL_rl_io_AMO_read_rsp, - CAN_FIRE_RL_rl_io_read_req, - CAN_FIRE_RL_rl_io_read_rsp, - CAN_FIRE_RL_rl_io_write_req, - CAN_FIRE_RL_rl_maintain_io_read_rsp, - CAN_FIRE_RL_rl_probe_and_immed_rsp, - CAN_FIRE_RL_rl_ptw_level_0, - CAN_FIRE_RL_rl_ptw_level_1, - CAN_FIRE_RL_rl_rereq, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_shift_sb_to_load_delay, - CAN_FIRE_RL_rl_start_cache_refill, - CAN_FIRE_RL_rl_start_reset, - CAN_FIRE_RL_rl_start_tlb_refill, - CAN_FIRE_RL_rl_writeback_updated_PTE, - CAN_FIRE_mem_master_m_arready, - CAN_FIRE_mem_master_m_awready, - CAN_FIRE_mem_master_m_bvalid, - CAN_FIRE_mem_master_m_rvalid, - CAN_FIRE_mem_master_m_wready, - CAN_FIRE_req, - CAN_FIRE_server_flush_request_put, - CAN_FIRE_server_flush_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_verbosity, - CAN_FIRE_tlb_flush, - WILL_FIRE_RL_rl_ST_AMO_response, - WILL_FIRE_RL_rl_cache_refill_rsps_loop, - WILL_FIRE_RL_rl_discard_write_rsp, - WILL_FIRE_RL_rl_drive_exception_rsp, - WILL_FIRE_RL_rl_io_AMO_SC_req, - WILL_FIRE_RL_rl_io_AMO_op_req, - WILL_FIRE_RL_rl_io_AMO_read_rsp, - WILL_FIRE_RL_rl_io_read_req, - WILL_FIRE_RL_rl_io_read_rsp, - WILL_FIRE_RL_rl_io_write_req, - WILL_FIRE_RL_rl_maintain_io_read_rsp, - WILL_FIRE_RL_rl_probe_and_immed_rsp, - WILL_FIRE_RL_rl_ptw_level_0, - WILL_FIRE_RL_rl_ptw_level_1, - WILL_FIRE_RL_rl_rereq, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_shift_sb_to_load_delay, - WILL_FIRE_RL_rl_start_cache_refill, - WILL_FIRE_RL_rl_start_reset, - WILL_FIRE_RL_rl_start_tlb_refill, - WILL_FIRE_RL_rl_writeback_updated_PTE, - WILL_FIRE_mem_master_m_arready, - WILL_FIRE_mem_master_m_awready, - WILL_FIRE_mem_master_m_bvalid, - WILL_FIRE_mem_master_m_rvalid, - WILL_FIRE_mem_master_m_wready, - WILL_FIRE_req, - WILL_FIRE_server_flush_request_put, - WILL_FIRE_server_flush_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_verbosity, - WILL_FIRE_tlb_flush; - - // inputs to muxes for submodule ports - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2, - MUX_master_xactor_rg_rd_addr$write_1__VAL_3, - MUX_master_xactor_rg_rd_addr$write_1__VAL_4, - MUX_master_xactor_rg_wr_addr$write_1__VAL_1, - MUX_master_xactor_rg_wr_addr$write_1__VAL_2, - MUX_master_xactor_rg_wr_addr$write_1__VAL_4; - wire [76 : 0] MUX_master_xactor_rg_wr_data$write_1__VAL_1, - MUX_master_xactor_rg_wr_data$write_1__VAL_2, - MUX_master_xactor_rg_wr_data$write_1__VAL_3, - MUX_master_xactor_rg_wr_data$write_1__VAL_4; - wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3, - MUX_ram_word64_set$a_put_3__VAL_2, - MUX_rg_ld_val$write_1__VAL_2; - wire [33 : 0] MUX_rg_pa$write_1__VAL_1; - wire [22 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1; - wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2, - MUX_ram_word64_set$b_put_2__VAL_4; - wire [6 : 0] MUX_rg_cset_in_cache$write_1__VAL_1; - wire [3 : 0] MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_5, - MUX_rg_state$write_1__VAL_10, - MUX_rg_state$write_1__VAL_11, - MUX_rg_state$write_1__VAL_12, - MUX_rg_state$write_1__VAL_13, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_6; - wire MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1, - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2, - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_1, - MUX_dw_output_ld_val$wset_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_4, - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1, - MUX_master_xactor_rg_rd_addr$write_1__SEL_2, - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1, - MUX_ram_word64_set$a_put_2__SEL_1, - MUX_ram_word64_set$b_put_1__SEL_2, - MUX_rg_error_during_refill$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_2, - MUX_rg_exc_code$write_1__SEL_3, - MUX_rg_exc_code$write_1__SEL_5, - MUX_rg_exc_code$write_1__SEL_6, - MUX_rg_exc_code$write_1__SEL_7, - MUX_rg_ld_val$write_1__SEL_2, - MUX_rg_lrsc_valid$write_1__SEL_2, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_13, - MUX_rg_state$write_1__SEL_17, - MUX_rg_state$write_1__SEL_3, - MUX_tlb$insert_1__SEL_1, - MUX_tlb$insert_1__SEL_2, - MUX_tlb$insert_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4748; - reg [31 : 0] v__h4849; - reg [31 : 0] v__h29722; - reg [31 : 0] v__h30620; - reg [31 : 0] v__h4385; - reg [31 : 0] v__h5300; - reg [31 : 0] v__h14916; - reg [31 : 0] v__h19135; - reg [31 : 0] v__h18560; - reg [31 : 0] v__h22571; - reg [31 : 0] v__h24184; - reg [31 : 0] v__h23942; - reg [31 : 0] v__h24605; - reg [31 : 0] v__h24493; - reg [31 : 0] v__h24113; - reg [31 : 0] v__h25145; - reg [31 : 0] v__h25216; - reg [31 : 0] v__h25298; - reg [31 : 0] v__h25074; - reg [31 : 0] v__h26206; - reg [31 : 0] v__h26428; - reg [31 : 0] v__h28410; - reg [31 : 0] v__h29510; - reg [31 : 0] v__h29617; - reg [31 : 0] v__h29802; - reg [31 : 0] v__h30324; - reg [31 : 0] v__h30738; - reg [31 : 0] v__h3751; - reg [31 : 0] v__h31056; - reg [31 : 0] v__h31231; - reg [31 : 0] v__h33844; - reg [31 : 0] v__h34096; - reg [31 : 0] v__h31327; - reg [31 : 0] v__h23206; - reg [31 : 0] v__h25423; - reg [31 : 0] v__h28036; - reg [31 : 0] v__h35065; - reg [31 : 0] v__h36219; - reg [31 : 0] v__h34716; - reg [31 : 0] v__h34677; - reg [31 : 0] v__h3745; - reg [31 : 0] v__h4379; - reg [31 : 0] v__h4742; - reg [31 : 0] v__h4843; - reg [31 : 0] v__h5294; - reg [31 : 0] v__h14910; - reg [31 : 0] v__h18554; - reg [31 : 0] v__h19129; - reg [31 : 0] v__h22565; - reg [31 : 0] v__h23200; - reg [31 : 0] v__h23936; - reg [31 : 0] v__h24107; - reg [31 : 0] v__h24178; - reg [31 : 0] v__h24487; - reg [31 : 0] v__h24599; - reg [31 : 0] v__h25068; - reg [31 : 0] v__h25139; - reg [31 : 0] v__h25210; - reg [31 : 0] v__h25292; - reg [31 : 0] v__h25417; - reg [31 : 0] v__h26200; - reg [31 : 0] v__h26422; - reg [31 : 0] v__h28030; - reg [31 : 0] v__h28404; - reg [31 : 0] v__h29504; - reg [31 : 0] v__h29611; - reg [31 : 0] v__h29716; - reg [31 : 0] v__h29796; - reg [31 : 0] v__h30318; - reg [31 : 0] v__h30614; - reg [31 : 0] v__h30732; - reg [31 : 0] v__h31050; - reg [31 : 0] v__h31225; - reg [31 : 0] v__h31321; - reg [31 : 0] v__h33838; - reg [31 : 0] v__h34090; - reg [31 : 0] v__h34671; - reg [31 : 0] v__h34710; - reg [31 : 0] v__h35059; - reg [31 : 0] v__h36213; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50, - CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30, - CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34, - CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35, - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33, - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752, - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627, - _theResult_____2__h19664, - _theResult_____2__h31649, - ld_val__h28519, - mem_req_wr_data_wdata__h18931, - mem_req_wr_data_wdata__h22367, - mem_req_wr_data_wdata__h30120, - mem_req_wr_data_wdata__h31624, - new_ld_val__h31357, - new_value__h17651, - new_value__h7622, - w1__h19656, - w1__h31637, - w1__h31641; - reg [33 : 0] _theResult___fst__h6689; - reg [7 : 0] mem_req_wr_data_wstrb__h18932, mem_req_wr_data_wstrb__h31625; - reg [2 : 0] value__h30942, value__h33968; - reg CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d285, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d290, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211, - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245, - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297; - wire [63 : 0] IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d574, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560, - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691, - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d784, - _theResult___snd_fst__h18939, - _theResult___snd_fst__h22375, - _theResult___snd_fst__h30128, - _theResult___snd_fst__h31632, - addr__h7263, - cline_fabric_addr__h25476, - lev_0_pte_pa_w64_fa__h24218, - lev_1_pte_pa_w64_fa__h23261, - mem_req_wr_addr_awaddr__h31419, - mem_req_wr_addr_awaddr__h3403, - mem_req_wr_data_wdata__h3595, - new_st_val__h19386, - new_st_val__h19668, - new_st_val__h19759, - new_st_val__h20739, - new_st_val__h20743, - new_st_val__h20747, - new_st_val__h20751, - new_st_val__h20756, - new_st_val__h20762, - new_st_val__h20767, - new_st_val__h31653, - new_st_val__h31744, - new_st_val__h33604, - new_st_val__h33608, - new_st_val__h33612, - new_st_val__h33616, - new_st_val__h33621, - new_st_val__h33627, - new_st_val__h33632, - result__h14033, - result__h14061, - result__h14089, - result__h14117, - result__h14145, - result__h14173, - result__h14201, - result__h14246, - result__h14274, - result__h14302, - result__h14330, - result__h14358, - result__h14386, - result__h14414, - result__h14442, - result__h14487, - result__h14515, - result__h14543, - result__h14571, - result__h14612, - result__h14640, - result__h14668, - result__h14696, - result__h14737, - result__h14765, - result__h14804, - result__h14832, - result__h28579, - result__h28609, - result__h28636, - result__h28663, - result__h28690, - result__h28717, - result__h28744, - result__h28771, - result__h28815, - result__h28842, - result__h28869, - result__h28896, - result__h28923, - result__h28950, - result__h28977, - result__h29004, - result__h29048, - result__h29075, - result__h29102, - result__h29129, - result__h29169, - result__h29196, - result__h29223, - result__h29250, - result__h29290, - result__h29317, - result__h29355, - result__h29382, - result__h31832, - result__h32740, - result__h32768, - result__h32796, - result__h32824, - result__h32852, - result__h32880, - result__h32908, - result__h32953, - result__h32981, - result__h33009, - result__h33037, - result__h33065, - result__h33093, - result__h33121, - result__h33149, - result__h33194, - result__h33222, - result__h33250, - result__h33278, - result__h33319, - result__h33347, - result__h33375, - result__h33403, - result__h33444, - result__h33472, - result__h33511, - result__h33539, - result__h7677, - st_val__h31369, - st_val__h3324, - w1___1__h19727, - w1___1__h31712, - w2___1__h31713, - w2__h31643, - word64__h7440, - x__h15303, - y__h7713; - wire [33 : 0] _theResult___fst__h6315, - _theResult___fst__h6387, - cline_addr__h25475, - lev_0_PTN_pa__h24214, - lev_0_pte_pa__h24216, - lev_0_pte_pa_w64__h24217, - lev_1_pte_pa__h23259, - lev_1_pte_pa_w64__h23260, - pa___1__h6695, - pa___1__h6744, - pa__h6215, - satp_pa__h2468, - vpn_0_pa__h24215, - vpn_1_pa__h23258, - x1_avValue_pa__h6227; - wire [31 : 0] _theResult____h23570, - _theResult___snd_fst__h6317, - _theResult___snd_fst__h6389, - _theResult___snd_fst__h6827, - ld_val8519_BITS_31_TO_0__q38, - ld_val8519_BITS_63_TO_32__q45, - master_xactor_rg_rd_data_BITS_34_TO_3__q3, - master_xactor_rg_rd_data_BITS_66_TO_35__q10, - new_value622_BITS_31_TO_0__q31, - pte___1__h6876, - pte___1__h6904, - pte___2__h6687, - rg_st_amo_val_BITS_31_TO_0__q32, - w11637_BITS_31_TO_0__q51, - word64440_BITS_31_TO_0__q17, - word64440_BITS_63_TO_32__q24, - x1_avValue_pte__h6230; - wire [15 : 0] ld_val8519_BITS_15_TO_0__q37, - ld_val8519_BITS_31_TO_16__q41, - ld_val8519_BITS_47_TO_32__q44, - ld_val8519_BITS_63_TO_48__q48, - master_xactor_rg_rd_data_BITS_18_TO_3__q2, - master_xactor_rg_rd_data_BITS_34_TO_19__q6, - master_xactor_rg_rd_data_BITS_50_TO_35__q9, - master_xactor_rg_rd_data_BITS_66_TO_51__q13, - word64440_BITS_15_TO_0__q16, - word64440_BITS_31_TO_16__q20, - word64440_BITS_47_TO_32__q23, - word64440_BITS_63_TO_48__q27; - wire [7 : 0] ld_val8519_BITS_15_TO_8__q39, - ld_val8519_BITS_23_TO_16__q40, - ld_val8519_BITS_31_TO_24__q42, - ld_val8519_BITS_39_TO_32__q43, - ld_val8519_BITS_47_TO_40__q46, - ld_val8519_BITS_55_TO_48__q47, - ld_val8519_BITS_63_TO_56__q49, - ld_val8519_BITS_7_TO_0__q36, - master_xactor_rg_rd_data_BITS_10_TO_3__q1, - master_xactor_rg_rd_data_BITS_18_TO_11__q4, - master_xactor_rg_rd_data_BITS_26_TO_19__q5, - master_xactor_rg_rd_data_BITS_34_TO_27__q7, - master_xactor_rg_rd_data_BITS_42_TO_35__q8, - master_xactor_rg_rd_data_BITS_50_TO_43__q11, - master_xactor_rg_rd_data_BITS_58_TO_51__q12, - master_xactor_rg_rd_data_BITS_66_TO_59__q14, - mem_req_wr_data_wstrb__h3596, - strobe64__h18865, - strobe64__h18867, - strobe64__h18869, - strobe64__h31558, - strobe64__h31560, - strobe64__h31562, - word64440_BITS_15_TO_8__q18, - word64440_BITS_23_TO_16__q19, - word64440_BITS_31_TO_24__q21, - word64440_BITS_39_TO_32__q22, - word64440_BITS_47_TO_40__q25, - word64440_BITS_55_TO_48__q26, - word64440_BITS_63_TO_56__q28, - word64440_BITS_7_TO_0__q15; - wire [5 : 0] shift_bits__h18732, shift_bits__h31425, shift_bits__h3414; - wire [3 : 0] IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d396, - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d395, - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d398, - access_exc_code__h3148, - b__h23160, - exc_code___1__h6589, - x1_avValue_exc_code__h6228; - wire IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d293, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217, - IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d305, - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d304, - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432, - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d284, - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d289, - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d292, - NOT_IF_rg_pte_pa_98_BIT_2_99_THEN_master_xacto_ETC___d926, - NOT_cfg_verbosity_read__5_ULE_2_014___d1015, - NOT_cfg_verbosity_read__5_ULT_2_02___d403, - NOT_dmem_not_imem_07_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d338, - NOT_dmem_not_imem_07_OR_NOT_rg_op_2_EQ_0_3_4_A_ETC___d114, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d621, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d634, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d761, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d795, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d813, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d852, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d857, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d863, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d871, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d875, - NOT_master_xactor_rg_rd_data_94_BITS_2_TO_1_95_ETC___d919, - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199, - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d434, - NOT_req_f3_BITS_1_TO_0_344_EQ_0b0_345_346_AND__ETC___d1365, - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_7__ETC___d294, - NOT_rg_op_2_EQ_0_3_4_AND_NOT_rg_op_2_EQ_2_5_6__ETC___d389, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d443, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d631, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d758, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d850, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d855, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d861, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d869, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d629, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d756, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d816, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d822, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d828, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d834, - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d345, - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d368, - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d406, - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d580, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d148, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d307, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d365, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d417, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d418, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d425, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d428, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d449, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d455, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d456, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d588, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d594, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d601, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d607, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d613, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d623, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d636, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d763, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d768, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d797, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d803, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d809, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d815, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d820, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d826, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d832, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d838, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d839, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d846, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d847, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d865, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d877, - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129, - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d145, - cfg_verbosity_read__5_ULE_1___d26, - dmem_not_imem_AND_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_ETC___d340, - dmem_not_imem_OR_NOT_rg_op_2_EQ_0_3_4_AND_NOT__ETC___d106, - lrsc_result__h15293, - master_xactor_crg_rd_data_full_port1__read__93_ETC___d1176, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d958, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d962, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d968, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d994, - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178, - ram_state_and_ctag_cset_b_read__73_BIT_22_74_A_ETC___d435, - req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374, - rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d610, - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d384, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d421, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d446, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d450, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d585, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d604, - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d444, - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d632, - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d759, - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d764, - rg_op_2_EQ_2_5_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d248, - rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123, - rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d136, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d309, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d353, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d392, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d393, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d411, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d414, - rg_priv_6_ULE_0b1___d67, - rg_state_0_EQ_12_043_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d1045, - rg_state_0_EQ_3_12_AND_NOT_rg_op_2_EQ_0_3_4_AN_ETC___d316, - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112, - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d347, - y__h6515; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method addr - assign addr = rg_addr ; - - // value method word64 - always@(MUX_dw_output_ld_val$wset_1__SEL_1 or - ld_val__h28519 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h31357 or - MUX_dw_output_ld_val$wset_1__SEL_3 or - MUX_dw_output_ld_val$wset_1__VAL_3 or - MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h28519; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - word64 = new_ld_val__h31357; - MUX_dw_output_ld_val$wset_1__SEL_3: - word64 = MUX_dw_output_ld_val$wset_1__VAL_3; - MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val; - default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // value method st_amo_val - assign st_amo_val = - MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ; - - // value method exc - assign exc = rg_state == 4'd4 ; - - // value method exc_code - assign exc_code = rg_exc_code ; - - // action method server_flush_request_put - assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; - - // action method server_flush_response_get - assign RDY_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; - - // action method tlb_flush - assign RDY_tlb_flush = 1'd1 ; - assign CAN_FIRE_tlb_flush = 1'd1 ; - assign WILL_FIRE_tlb_flush = EN_tlb_flush ; - - // value method mem_master_m_awvalid - assign mem_master_awvalid = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - - // value method mem_master_m_awid - assign mem_master_awid = master_xactor_rg_wr_addr[96:93] ; - - // value method mem_master_m_awaddr - assign mem_master_awaddr = master_xactor_rg_wr_addr[92:29] ; - - // value method mem_master_m_awlen - assign mem_master_awlen = master_xactor_rg_wr_addr[28:21] ; - - // value method mem_master_m_awsize - assign mem_master_awsize = master_xactor_rg_wr_addr[20:18] ; - - // value method mem_master_m_awburst - assign mem_master_awburst = master_xactor_rg_wr_addr[17:16] ; - - // value method mem_master_m_awlock - assign mem_master_awlock = master_xactor_rg_wr_addr[15] ; - - // value method mem_master_m_awcache - assign mem_master_awcache = master_xactor_rg_wr_addr[14:11] ; - - // value method mem_master_m_awprot - assign mem_master_awprot = master_xactor_rg_wr_addr[10:8] ; - - // value method mem_master_m_awqos - assign mem_master_awqos = master_xactor_rg_wr_addr[7:4] ; - - // value method mem_master_m_awregion - assign mem_master_awregion = master_xactor_rg_wr_addr[3:0] ; - - // action method mem_master_m_awready - assign CAN_FIRE_mem_master_m_awready = 1'd1 ; - assign WILL_FIRE_mem_master_m_awready = 1'd1 ; - - // value method mem_master_m_wvalid - assign mem_master_wvalid = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - - // value method mem_master_m_wid - assign mem_master_wid = master_xactor_rg_wr_data[76:73] ; - - // value method mem_master_m_wdata - assign mem_master_wdata = master_xactor_rg_wr_data[72:9] ; - - // value method mem_master_m_wstrb - assign mem_master_wstrb = master_xactor_rg_wr_data[8:1] ; - - // value method mem_master_m_wlast - assign mem_master_wlast = master_xactor_rg_wr_data[0] ; - - // action method mem_master_m_wready - assign CAN_FIRE_mem_master_m_wready = 1'd1 ; - assign WILL_FIRE_mem_master_m_wready = 1'd1 ; - - // action method mem_master_m_bvalid - assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ; - - // value method mem_master_m_bready - assign mem_master_bready = !master_xactor_crg_wr_resp_full$port2__read ; - - // value method mem_master_m_arvalid - assign mem_master_arvalid = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - - // value method mem_master_m_arid - assign mem_master_arid = master_xactor_rg_rd_addr[96:93] ; - - // value method mem_master_m_araddr - assign mem_master_araddr = master_xactor_rg_rd_addr[92:29] ; - - // value method mem_master_m_arlen - assign mem_master_arlen = master_xactor_rg_rd_addr[28:21] ; - - // value method mem_master_m_arsize - assign mem_master_arsize = master_xactor_rg_rd_addr[20:18] ; - - // value method mem_master_m_arburst - assign mem_master_arburst = master_xactor_rg_rd_addr[17:16] ; - - // value method mem_master_m_arlock - assign mem_master_arlock = master_xactor_rg_rd_addr[15] ; - - // value method mem_master_m_arcache - assign mem_master_arcache = master_xactor_rg_rd_addr[14:11] ; - - // value method mem_master_m_arprot - assign mem_master_arprot = master_xactor_rg_rd_addr[10:8] ; - - // value method mem_master_m_arqos - assign mem_master_arqos = master_xactor_rg_rd_addr[7:4] ; - - // value method mem_master_m_arregion - assign mem_master_arregion = master_xactor_rg_rd_addr[3:0] ; - - // action method mem_master_m_arready - assign CAN_FIRE_mem_master_m_arready = 1'd1 ; - assign WILL_FIRE_mem_master_m_arready = 1'd1 ; - - // action method mem_master_m_rvalid - assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ; - - // value method mem_master_m_rready - assign mem_master_rready = !master_xactor_crg_rd_data_full$port2__read ; - - // submodule f_pte_writebacks - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_pte_writebacks(.RST(RST_N), - .CLK(CLK), - .D_IN(f_pte_writebacks$D_IN), - .ENQ(f_pte_writebacks$ENQ), - .DEQ(f_pte_writebacks$DEQ), - .CLR(f_pte_writebacks$CLR), - .D_OUT(f_pte_writebacks$D_OUT), - .FULL_N(f_pte_writebacks$FULL_N), - .EMPTY_N(f_pte_writebacks$EMPTY_N)); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule ram_state_and_ctag_cset - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd7), - .DATA_WIDTH(32'd23), - .MEMSIZE(8'd128)) ram_state_and_ctag_cset(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_state_and_ctag_cset$ADDRA), - .ADDRB(ram_state_and_ctag_cset$ADDRB), - .DIA(ram_state_and_ctag_cset$DIA), - .DIB(ram_state_and_ctag_cset$DIB), - .WEA(ram_state_and_ctag_cset$WEA), - .WEB(ram_state_and_ctag_cset$WEB), - .ENA(ram_state_and_ctag_cset$ENA), - .ENB(ram_state_and_ctag_cset$ENB), - .DOA(), - .DOB(ram_state_and_ctag_cset$DOB)); - - // submodule ram_word64_set - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd9), - .DATA_WIDTH(32'd64), - .MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_word64_set$ADDRA), - .ADDRB(ram_word64_set$ADDRB), - .DIA(ram_word64_set$DIA), - .DIB(ram_word64_set$DIB), - .WEA(ram_word64_set$WEA), - .WEB(ram_word64_set$WEB), - .ENA(ram_word64_set$ENA), - .ENB(ram_word64_set$ENB), - .DOA(), - .DOB(ram_word64_set$DOB)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(soc_map$m_is_mem_addr), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule tlb - mkTLB #(.dmem_not_imem(dmem_not_imem)) tlb(.CLK(CLK), - .RST_N(RST_N), - .insert_asid(tlb$insert_asid), - .insert_level(tlb$insert_level), - .insert_pte(tlb$insert_pte), - .insert_pte_pa(tlb$insert_pte_pa), - .insert_vpn(tlb$insert_vpn), - .lookup_asid(tlb$lookup_asid), - .lookup_vpn(tlb$lookup_vpn), - .EN_flush(tlb$EN_flush), - .EN_insert(tlb$EN_insert), - .RDY_flush(), - .lookup(tlb$lookup), - .RDY_lookup(tlb$RDY_lookup), - .RDY_insert(tlb$RDY_insert)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = WILL_FIRE_RL_rl_reset ; - assign WILL_FIRE_RL_rl_reset = - (rg_cset_in_cache != 7'd127 || - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) && - rg_state == 4'd1 ; - - // rule RL_rl_shift_sb_to_load_delay - assign CAN_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - assign WILL_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - - // rule RL_rl_rereq - assign CAN_FIRE_RL_rl_rereq = rg_state == 4'd10 ; - assign WILL_FIRE_RL_rl_rereq = - CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ; - - // rule RL_rl_ST_AMO_response - assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 4'd11 ; - assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ; - - // rule RL_rl_maintain_io_read_rsp - assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 4'd14 ; - assign WILL_FIRE_RL_rl_maintain_io_read_rsp = - CAN_FIRE_RL_rl_maintain_io_read_rsp ; - - // rule RL_rl_io_AMO_SC_req - assign CAN_FIRE_RL_rl_io_AMO_SC_req = - rg_state == 4'd12 && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_SC_req = - CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_drive_exception_rsp - assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ; - assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ; - - // rule RL_rl_start_reset - assign CAN_FIRE_RL_rl_start_reset = - f_reset_reqs$EMPTY_N && rg_state != 4'd1 ; - assign WILL_FIRE_RL_rl_start_reset = CAN_FIRE_RL_rl_start_reset ; - - // rule RL_rl_probe_and_immed_rsp - assign CAN_FIRE_RL_rl_probe_and_immed_rsp = - (cfg_verbosity_read__5_ULE_1___d26 || tlb$RDY_lookup) && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$RDY_lookup) && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d309 && - rg_state_0_EQ_3_12_AND_NOT_rg_op_2_EQ_0_3_4_AN_ETC___d316 ; - assign WILL_FIRE_RL_rl_probe_and_immed_rsp = - CAN_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_ptw_level_1 - assign CAN_FIRE_RL_rl_ptw_level_1 = - master_xactor_crg_rd_data_full$port1__read && - NOT_master_xactor_rg_rd_data_94_BITS_2_TO_1_95_ETC___d919 && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_ptw_level_1 = - CAN_FIRE_RL_rl_ptw_level_1 && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_ptw_level_0 - assign CAN_FIRE_RL_rl_ptw_level_0 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - !_theResult____h23570[3] && !_theResult____h23570[1] || - tlb$RDY_insert) && - rg_state == 4'd7 ; - assign WILL_FIRE_RL_rl_ptw_level_0 = - CAN_FIRE_RL_rl_ptw_level_0 && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_cache_refill_rsps_loop - assign CAN_FIRE_RL_rl_cache_refill_rsps_loop = - master_xactor_crg_rd_data_full$port1__read && rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_cache_refill_rsps_loop = - CAN_FIRE_RL_rl_cache_refill_rsps_loop && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_rsp - assign CAN_FIRE_RL_rl_io_read_rsp = - master_xactor_crg_rd_data_full$port1__read && rg_state == 4'd13 ; - assign WILL_FIRE_RL_rl_io_read_rsp = - CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_write_req - assign CAN_FIRE_RL_rl_io_write_req = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - rg_state == 4'd12 && - rg_op == 2'd1 ; - assign WILL_FIRE_RL_rl_io_write_req = - CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_op_req - assign CAN_FIRE_RL_rl_io_AMO_op_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 4'd12 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] != 5'b00010 && - rg_amo_funct7[6:2] != 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_op_req = - CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_writeback_updated_PTE - assign CAN_FIRE_RL_rl_writeback_updated_PTE = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - f_pte_writebacks$EMPTY_N ; - assign WILL_FIRE_RL_rl_writeback_updated_PTE = - CAN_FIRE_RL_rl_writeback_updated_PTE && - !WILL_FIRE_RL_rl_io_AMO_read_rsp && - !WILL_FIRE_RL_rl_io_write_req && - !WILL_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_read_rsp - assign CAN_FIRE_RL_rl_io_AMO_read_rsp = - master_xactor_crg_rd_data_full_port1__read__93_ETC___d1176 && - rg_state == 4'd15 ; - assign WILL_FIRE_RL_rl_io_AMO_read_rsp = - CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_tlb_refill - assign CAN_FIRE_RL_rl_start_tlb_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 4'd5 && - b__h23160 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_tlb_refill = - CAN_FIRE_RL_rl_start_tlb_refill && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_cache_refill - assign CAN_FIRE_RL_rl_start_cache_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 4'd8 && - b__h23160 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_cache_refill = - CAN_FIRE_RL_rl_start_cache_refill && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_req - assign CAN_FIRE_RL_rl_io_read_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state_0_EQ_12_043_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d1045 ; - assign WILL_FIRE_RL_rl_io_read_req = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_discard_write_rsp - assign CAN_FIRE_RL_rl_discard_write_rsp = - b__h23160 != 4'd0 && master_xactor_crg_wr_resp_full$port1__read ; - assign WILL_FIRE_RL_rl_discard_write_rsp = - CAN_FIRE_RL_rl_discard_write_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // inputs to muxes for submodule ports - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3 = - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign MUX_dw_output_ld_val$wset_1__SEL_1 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_dw_output_ld_val$wset_1__SEL_3 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d456 ; - assign MUX_dw_output_ld_val$wset_1__SEL_4 = - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - !_theResult____h23570[2] && - !_theResult____h23570[3] && - !_theResult____h23570[1] ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ; - assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 = - EN_req && - req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374 ; - assign MUX_ram_word64_set$a_put_2__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ram_word64_set$b_put_1__SEL_2 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 ; - assign MUX_rg_error_during_refill$write_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_1 = - EN_req && - NOT_req_f3_BITS_1_TO_0_344_EQ_0b0_345_346_AND__ETC___d1365 ; - assign MUX_rg_exc_code$write_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_3 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_5 = - WILL_FIRE_RL_rl_ptw_level_0 && - (!_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - !_theResult____h23570[3] && !_theResult____h23570[1] || - master_xactor_rg_rd_data[2:1] != 2'b0) ; - assign MUX_rg_exc_code$write_1__SEL_6 = - WILL_FIRE_RL_rl_ptw_level_1 && - NOT_IF_rg_pte_pa_98_BIT_2_99_THEN_master_xacto_ETC___d926 ; - assign MUX_rg_exc_code$write_1__SEL_7 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 ; - assign MUX_rg_ld_val$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d623 ; - assign MUX_rg_lrsc_valid$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d449 ; - assign MUX_rg_state$write_1__SEL_3 = - CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ; - assign MUX_rg_state$write_1__SEL_10 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 ; - assign MUX_rg_state$write_1__SEL_13 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d393 ; - assign MUX_rg_state$write_1__SEL_17 = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign MUX_tlb$insert_1__SEL_1 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 ; - assign MUX_tlb$insert_1__SEL_2 = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d958 ; - assign MUX_tlb$insert_1__SEL_3 = - WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 = - ctr_wr_rsps_pending_crg + 4'd1 ; - assign MUX_dw_output_ld_val$wset_1__VAL_3 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - new_value__h7622 : - new_value__h17651 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, lev_0_pte_pa_w64_fa__h24218, 29'd851968 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, - mem_req_wr_addr_awaddr__h31419, - 8'd0, - value__h30942, - 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_3 = - { 4'd0, lev_1_pte_pa_w64_fa__h23261, 29'd589824 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_4 = - { 4'd0, cline_fabric_addr__h25476, 29'd7143424 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_1 = - { 4'd0, - mem_req_wr_addr_awaddr__h31419, - 8'd0, - value__h33968, - 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_2 = - { 4'd0, addr__h7263, 8'd0, value__h33968, 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_4 = - { 4'd0, mem_req_wr_addr_awaddr__h3403, 29'd589824 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_1 = - { 4'd0, - mem_req_wr_data_wdata__h31624, - mem_req_wr_data_wstrb__h31625, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_2 = - { 4'd0, - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d784, - mem_req_wr_data_wstrb__h18932, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_3 = - { 4'd0, - mem_req_wr_data_wdata__h3595, - mem_req_wr_data_wstrb__h3596, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_4 = - { 4'd0, - mem_req_wr_data_wdata__h30120, - mem_req_wr_data_wstrb__h31625, - 1'd1 } ; - assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 = { 1'd1, rg_pa[33:12] } ; - assign MUX_ram_word64_set$a_put_3__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 : - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 ; - assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ; - assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:5], 2'd0 } ; - assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 7'd1 ; - assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ; - assign MUX_rg_exc_code$write_1__VAL_5 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - exc_code___1__h6589 : - access_exc_code__h3148 ; - assign MUX_rg_ld_val$write_1__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - x__h15303 : - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 ; - assign MUX_rg_pa$write_1__VAL_1 = { 2'd0, req_addr } ; - assign MUX_rg_state$write_1__VAL_2 = - NOT_req_f3_BITS_1_TO_0_344_EQ_0b0_345_346_AND__ETC___d1365 ? - 4'd4 : - 4'd3 ; - assign MUX_rg_state$write_1__VAL_6 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? 4'd14 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_10 = - (master_xactor_rg_rd_data[2:1] != 2'b0 || - rg_error_during_refill) ? - 4'd4 : - 4'd10 ; - assign MUX_rg_state$write_1__VAL_11 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - ((!_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - !_theResult____h23570[3] && !_theResult____h23570[1]) ? - 4'd4 : - 4'd10) : - 4'd4 ; - assign MUX_rg_state$write_1__VAL_12 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - ((!_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2]) ? - 4'd4 : - ((!_theResult____h23570[3] && !_theResult____h23570[1]) ? - 4'd7 : - ((_theResult____h23570[19:10] == 10'd0) ? - 4'd10 : - 4'd4))) : - 4'd4 ; - assign MUX_rg_state$write_1__VAL_13 = - (rg_priv_6_ULE_0b1___d67 && rg_satp[31] && !tlb$lookup[68]) ? - 4'd5 : - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d398 ; - - // inlined wires - assign dw_valid$whas = - (WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_read_rsp) && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d456 || - WILL_FIRE_RL_rl_drive_exception_rsp || - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign master_xactor_crg_wr_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_addr_full$port1__read = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full$port1__read && - mem_master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full$port1__read ; - assign master_xactor_crg_wr_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign master_xactor_crg_wr_addr_full$port3__read = - master_xactor_crg_wr_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_data_full$port1__read = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full$port1__read && mem_master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full$port1__read ; - assign master_xactor_crg_wr_data_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign master_xactor_crg_wr_data_full$port3__read = - master_xactor_crg_wr_data_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_wr_resp_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_resp_full$port1__read = - !master_xactor_crg_wr_resp_full$EN_port0__write && - master_xactor_crg_wr_resp_full ; - assign master_xactor_crg_wr_resp_full$port2__read = - !WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_crg_wr_resp_full$port1__read ; - assign master_xactor_crg_wr_resp_full$EN_port2__write = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_wr_resp_full$port3__read = - master_xactor_crg_wr_resp_full$EN_port2__write || - master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_addr_full$port1__read = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full$port1__read && - mem_master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full$port1__read ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - !_theResult____h23570[2] && - !_theResult____h23570[3] && - !_theResult____h23570[1] || - WILL_FIRE_RL_rl_io_AMO_op_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_tlb_refill ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_data_full$port1__read = - !master_xactor_crg_rd_data_full$EN_port0__write && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port1__write = - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_cache_refill_rsps_loop || - WILL_FIRE_RL_rl_ptw_level_0 || - WILL_FIRE_RL_rl_ptw_level_1 || - WILL_FIRE_RL_rl_io_AMO_read_rsp ; - assign master_xactor_crg_rd_data_full$port2__read = - !master_xactor_crg_rd_data_full$EN_port1__write && - master_xactor_crg_rd_data_full$port1__read ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - mem_master_rvalid && - !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - assign ctr_wr_rsps_pending_crg$EN_port0__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - default: ctr_wr_rsps_pending_crg$port0__write_1 = - 4'b1010 /* unspecified value */ ; - endcase - end - assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h23160 - 4'd1 ; - assign ctr_wr_rsps_pending_crg$port2__read = - WILL_FIRE_RL_rl_discard_write_rsp ? - ctr_wr_rsps_pending_crg$port1__write_1 : - b__h23160 ; - assign ctr_wr_rsps_pending_crg$EN_port2__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign ctr_wr_rsps_pending_crg$port3__read = - ctr_wr_rsps_pending_crg$EN_port2__write ? - 4'd0 : - ctr_wr_rsps_pending_crg$port2__read ; - assign crg_sb_to_load_delay$port0__write_1 = - { 1'd0, crg_sb_to_load_delay[10:1] } ; - assign crg_sb_to_load_delay$EN_port1__write = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d763 ; - assign crg_sb_to_load_delay$port2__read = - crg_sb_to_load_delay$EN_port1__write ? - 11'd2047 : - crg_sb_to_load_delay$port0__write_1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register crg_sb_to_load_delay - assign crg_sb_to_load_delay$D_IN = crg_sb_to_load_delay$port2__read ; - assign crg_sb_to_load_delay$EN = 1'b1 ; - - // register ctr_wr_rsps_pending_crg - assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ; - assign ctr_wr_rsps_pending_crg$EN = 1'b1 ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = - master_xactor_crg_wr_resp_full$port3__read ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - always@(MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 or - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 or - MUX_master_xactor_rg_rd_addr$write_1__SEL_2 or - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 or - WILL_FIRE_RL_rl_start_tlb_refill or - MUX_master_xactor_rg_rd_addr$write_1__VAL_3 or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_master_xactor_rg_rd_addr$write_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_1; - MUX_master_xactor_rg_rd_addr$write_1__SEL_2: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_2; - WILL_FIRE_RL_rl_start_tlb_refill: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_3; - WILL_FIRE_RL_rl_start_cache_refill: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_4; - default: master_xactor_rg_rd_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_rd_addr$EN = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - !_theResult____h23570[2] && - !_theResult____h23570[3] && - !_theResult____h23570[1] || - WILL_FIRE_RL_rl_io_AMO_op_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_tlb_refill || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_writeback_updated_PTE or - MUX_master_xactor_rg_wr_addr$write_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - WILL_FIRE_RL_rl_writeback_updated_PTE: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_4; - default: master_xactor_rg_wr_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_addr$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - - // register master_xactor_rg_wr_data - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_data$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_data$write_1__VAL_2 or - WILL_FIRE_RL_rl_writeback_updated_PTE or - MUX_master_xactor_rg_wr_data$write_1__VAL_3 or - WILL_FIRE_RL_rl_io_write_req or - MUX_master_xactor_rg_wr_data$write_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_2; - WILL_FIRE_RL_rl_writeback_updated_PTE: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_4; - default: master_xactor_rg_wr_data$D_IN = - 77'h0AAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_data$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 || - WILL_FIRE_RL_rl_writeback_updated_PTE || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = - { mem_master_bid, mem_master_bresp } ; - assign master_xactor_rg_wr_resp$EN = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - - // register rg_addr - assign rg_addr$D_IN = req_addr ; - assign rg_addr$EN = EN_req ; - - // register rg_amo_funct7 - assign rg_amo_funct7$D_IN = req_amo_funct7 ; - assign rg_amo_funct7$EN = EN_req ; - - // register rg_cset_in_cache - assign rg_cset_in_cache$D_IN = - WILL_FIRE_RL_rl_reset ? - MUX_rg_cset_in_cache$write_1__VAL_1 : - 7'd0 ; - assign rg_cset_in_cache$EN = - WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ; - - // register rg_error_during_refill - assign rg_error_during_refill$D_IN = - MUX_rg_error_during_refill$write_1__SEL_1 ; - assign rg_error_during_refill$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register rg_exc_code - always@(MUX_rg_exc_code$write_1__SEL_1 or - MUX_rg_exc_code$write_1__VAL_1 or - MUX_rg_exc_code$write_1__SEL_2 or - MUX_rg_exc_code$write_1__SEL_3 or - MUX_rg_error_during_refill$write_1__SEL_1 or - access_exc_code__h3148 or - MUX_rg_exc_code$write_1__SEL_5 or - MUX_rg_exc_code$write_1__VAL_5 or - MUX_rg_exc_code$write_1__SEL_6 or - MUX_rg_exc_code$write_1__SEL_7 or x1_avValue_exc_code__h6228) - case (1'b1) - MUX_rg_exc_code$write_1__SEL_1: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1; - MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7; - MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5; - MUX_rg_error_during_refill$write_1__SEL_1: - rg_exc_code$D_IN = access_exc_code__h3148; - MUX_rg_exc_code$write_1__SEL_5: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5; - MUX_rg_exc_code$write_1__SEL_6: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5; - MUX_rg_exc_code$write_1__SEL_7: - rg_exc_code$D_IN = x1_avValue_exc_code__h6228; - default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_exc_code$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - EN_req && - NOT_req_f3_BITS_1_TO_0_344_EQ_0b0_345_346_AND__ETC___d1365 || - WILL_FIRE_RL_rl_ptw_level_1 && - NOT_IF_rg_pte_pa_98_BIT_2_99_THEN_master_xacto_ETC___d926 || - WILL_FIRE_RL_rl_ptw_level_0 && - (!_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - !_theResult____h23570[3] && !_theResult____h23570[1] || - master_xactor_rg_rd_data[2:1] != 2'b0) ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_ld_val - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h31357 or - MUX_rg_ld_val$write_1__SEL_2 or - MUX_rg_ld_val$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_rsp or - ld_val__h28519 or WILL_FIRE_RL_rl_io_AMO_SC_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - rg_ld_val$D_IN = new_ld_val__h31357; - MUX_rg_ld_val$write_1__SEL_2: - rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h28519; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1; - default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_ld_val$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d623 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_SC_req ; - - // register rg_lower_word32 - assign rg_lower_word32$D_IN = 32'h0 ; - assign rg_lower_word32$EN = 1'b0 ; - - // register rg_lower_word32_full - assign rg_lower_word32_full$D_IN = 1'd0 ; - assign rg_lower_word32_full$EN = - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_lrsc_pa - assign rg_lrsc_pa$D_IN = x1_avValue_pa__h6227 ; - assign rg_lrsc_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d594 ; - - // register rg_lrsc_valid - assign rg_lrsc_valid$D_IN = - MUX_rg_lrsc_valid$write_1__SEL_2 && - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d450 ; - assign rg_lrsc_valid$EN = - WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d449 || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = req_mstatus_MXR ; - assign rg_mstatus_MXR$EN = EN_req ; - - // register rg_op - assign rg_op$D_IN = req_op ; - assign rg_op$EN = EN_req ; - - // register rg_pa - assign rg_pa$D_IN = - EN_req ? MUX_rg_pa$write_1__VAL_1 : x1_avValue_pa__h6227 ; - assign rg_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d418 || - EN_req ; - - // register rg_priv - assign rg_priv$D_IN = req_priv ; - assign rg_priv$EN = EN_req ; - - // register rg_pte_pa - assign rg_pte_pa$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - lev_0_pte_pa__h24216 : - lev_1_pte_pa__h23259 ; - assign rg_pte_pa$EN = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - !_theResult____h23570[2] && - !_theResult____h23570[3] && - !_theResult____h23570[1] || - WILL_FIRE_RL_rl_start_tlb_refill ; - - // register rg_satp - assign rg_satp$D_IN = req_satp ; - assign rg_satp$EN = EN_req ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = req_sstatus_SUM ; - assign rg_sstatus_SUM$EN = EN_req ; - - // register rg_st_amo_val - assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h19386 ; - assign rg_st_amo_val$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d877 || - EN_req ; - - // register rg_state - always@(EN_tlb_flush or - EN_req or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_req or - WILL_FIRE_RL_rl_start_cache_refill or - WILL_FIRE_RL_rl_start_tlb_refill or - WILL_FIRE_RL_rl_io_AMO_read_rsp or - MUX_rg_state$write_1__VAL_6 or - WILL_FIRE_RL_rl_io_AMO_op_req or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_io_read_rsp or - MUX_rg_state$write_1__SEL_10 or - MUX_rg_state$write_1__VAL_10 or - WILL_FIRE_RL_rl_ptw_level_0 or - MUX_rg_state$write_1__VAL_11 or - WILL_FIRE_RL_rl_ptw_level_1 or - MUX_rg_state$write_1__VAL_12 or - MUX_rg_state$write_1__SEL_13 or - MUX_rg_state$write_1__VAL_13 or - WILL_FIRE_RL_rl_start_reset or - WILL_FIRE_RL_rl_io_AMO_SC_req or - WILL_FIRE_RL_rl_rereq or MUX_rg_state$write_1__SEL_17) - case (1'b1) - EN_tlb_flush: rg_state$D_IN = 4'd2; - EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 4'd13; - WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_start_tlb_refill: rg_state$D_IN = 4'd6; - WILL_FIRE_RL_rl_io_AMO_read_rsp: - rg_state$D_IN = MUX_rg_state$write_1__VAL_6; - WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 4'd15; - WILL_FIRE_RL_rl_io_write_req: rg_state$D_IN = 4'd11; - WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_6; - MUX_rg_state$write_1__SEL_10: - rg_state$D_IN = MUX_rg_state$write_1__VAL_10; - WILL_FIRE_RL_rl_ptw_level_0: rg_state$D_IN = MUX_rg_state$write_1__VAL_11; - WILL_FIRE_RL_rl_ptw_level_1: rg_state$D_IN = MUX_rg_state$write_1__VAL_12; - MUX_rg_state$write_1__SEL_13: - rg_state$D_IN = MUX_rg_state$write_1__VAL_13; - WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 4'd1; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_state$D_IN = 4'd11; - WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_17: rg_state$D_IN = 4'd2; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_state$EN = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d393 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_ptw_level_1 || - WILL_FIRE_RL_rl_ptw_level_0 || - EN_req || - WILL_FIRE_RL_rl_start_reset || - EN_tlb_flush || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_tlb_refill || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_io_AMO_SC_req || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_io_AMO_op_req ; - - // register rg_word64_set_in_cache - assign rg_word64_set_in_cache$D_IN = - MUX_ram_word64_set$b_put_1__SEL_2 ? - MUX_ram_word64_set$b_put_2__VAL_2 : - MUX_ram_word64_set$b_put_2__VAL_4 ; - assign rg_word64_set_in_cache$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule f_pte_writebacks - assign f_pte_writebacks$D_IN = { tlb$lookup[33:0], x1_avValue_pte__h6230 } ; - assign f_pte_writebacks$ENQ = MUX_tlb$insert_1__SEL_1 ; - assign f_pte_writebacks$DEQ = WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign f_pte_writebacks$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = !EN_server_reset_request_put ; - assign f_reset_reqs$ENQ = - EN_server_reset_request_put || EN_server_flush_request_put ; - assign f_reset_reqs$DEQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ; - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign f_reset_rsps$DEQ = - EN_server_flush_response_get || EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule ram_state_and_ctag_cset - assign ram_state_and_ctag_cset$ADDRA = - WILL_FIRE_RL_rl_start_cache_refill ? - rg_addr[11:5] : - rg_cset_in_cache ; - assign ram_state_and_ctag_cset$ADDRB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - req_addr[11:5] : - rg_addr[11:5] ; - assign ram_state_and_ctag_cset$DIA = - WILL_FIRE_RL_rl_start_cache_refill ? - MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 : - 23'd2796202 ; - assign ram_state_and_ctag_cset$DIB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - 23'b01010101010101010101010 /* unspecified value */ : - 23'b01010101010101010101010 /* unspecified value */ ; - assign ram_state_and_ctag_cset$WEA = 1'd1 ; - assign ram_state_and_ctag_cset$WEB = 1'd0 ; - assign ram_state_and_ctag_cset$ENA = - WILL_FIRE_RL_rl_start_cache_refill || WILL_FIRE_RL_rl_reset ; - assign ram_state_and_ctag_cset$ENB = - EN_req && - req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374 || - WILL_FIRE_RL_rl_rereq ; - - // submodule ram_word64_set - assign ram_word64_set$ADDRA = - MUX_ram_word64_set$a_put_2__SEL_1 ? - rg_word64_set_in_cache : - rg_addr[11:3] ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - req_addr or - MUX_ram_word64_set$b_put_1__SEL_2 or - MUX_ram_word64_set$b_put_2__VAL_2 or - WILL_FIRE_RL_rl_rereq or - rg_addr or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_ram_word64_set$b_put_2__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$ADDRB = req_addr[11:3]; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2; - WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3]; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4; - default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ; - endcase - end - assign ram_word64_set$DIA = - MUX_ram_word64_set$a_put_2__SEL_1 ? - master_xactor_rg_rd_data[66:3] : - MUX_ram_word64_set$a_put_3__VAL_2 ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - MUX_ram_word64_set$b_put_1__SEL_2 or - WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_rereq: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - default: ram_word64_set$DIB = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign ram_word64_set$WEA = 1'd1 ; - assign ram_word64_set$WEB = 1'd0 ; - assign ram_word64_set$ENA = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d636 ; - assign ram_word64_set$ENB = - EN_req && - req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = { 30'd0, x1_avValue_pa__h6227 } ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule tlb - assign tlb$insert_asid = rg_satp[30:22] ; - always@(MUX_tlb$insert_1__SEL_1 or - tlb$lookup or MUX_tlb$insert_1__SEL_2 or MUX_tlb$insert_1__SEL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_tlb$insert_1__SEL_1: tlb$insert_level = tlb$lookup[35:34]; - MUX_tlb$insert_1__SEL_2: tlb$insert_level = 2'd1; - MUX_tlb$insert_1__SEL_3: tlb$insert_level = 2'd0; - default: tlb$insert_level = 2'b10 /* unspecified value */ ; - endcase - end - always@(MUX_tlb$insert_1__SEL_1 or - x1_avValue_pte__h6230 or - MUX_tlb$insert_1__SEL_2 or - _theResult____h23570 or MUX_tlb$insert_1__SEL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_tlb$insert_1__SEL_1: tlb$insert_pte = x1_avValue_pte__h6230; - MUX_tlb$insert_1__SEL_2: tlb$insert_pte = _theResult____h23570; - MUX_tlb$insert_1__SEL_3: tlb$insert_pte = _theResult____h23570; - default: tlb$insert_pte = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign tlb$insert_pte_pa = - MUX_tlb$insert_1__SEL_1 ? tlb$lookup[33:0] : rg_pte_pa ; - assign tlb$insert_vpn = rg_addr[31:12] ; - assign tlb$lookup_asid = rg_satp[30:22] ; - assign tlb$lookup_vpn = rg_addr[31:12] ; - assign tlb$EN_flush = WILL_FIRE_RL_rl_start_reset || EN_tlb_flush ; - assign tlb$EN_insert = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 || - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d958 || - WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) ; - - // remaining internal signals - assign IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d293 = - (x1_avValue_pa__h6227[2:0] == 3'h0) ? - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 : - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d292 ; - assign IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d574 = - (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; - assign IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253 = - (rg_addr[2:0] == 3'h0) ? ld_val__h28519 : 64'd0 ; - assign IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217 = - (rg_addr[2:0] == 3'h0) ? - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199 : - rg_addr[2:0] != 3'h4 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199 ; - assign IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560 = - (rg_addr[2:0] == 3'h0) ? word64__h7440 : 64'd0 ; - assign IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 = - (rg_f3 == 3'b010) ? - { {32{rg_st_amo_val_BITS_31_TO_0__q32[31]}}, - rg_st_amo_val_BITS_31_TO_0__q32 } : - rg_st_amo_val ; - assign IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d305 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - !ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 || - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 : - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d304 ; - assign IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d396 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd8 : - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d395 ; - assign IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d304 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - rg_op_2_EQ_2_5_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d248 : - !ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297 && - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 && - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 ; - assign IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d395 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - 4'd11 : - ((!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) ? - 4'd8 : - 4'd11) ; - assign IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d784 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - mem_req_wr_data_wdata__h18931 : - mem_req_wr_data_wdata__h22367 ; - assign IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d398 = - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 ? - 4'd4 : - ((dmem_not_imem && !soc_map$m_is_mem_addr) ? - 4'd12 : - IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d396) ; - assign IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 = - x1_avValue_pa__h6227 == rg_lrsc_pa ; - assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d284 = - x1_avValue_pa__h6227[2:0] != 3'h7 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d289 = - x1_avValue_pa__h6227[2:0] != 3'h6 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d292 = - x1_avValue_pa__h6227[2:0] != 3'h4 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_IF_rg_pte_pa_98_BIT_2_99_THEN_master_xacto_ETC___d926 = - !_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - (_theResult____h23570[3] || _theResult____h23570[1]) && - _theResult____h23570[19:10] != 10'd0 || - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign NOT_cfg_verbosity_read__5_ULE_2_014___d1015 = cfg_verbosity > 4'd2 ; - assign NOT_cfg_verbosity_read__5_ULT_2_02___d403 = cfg_verbosity >= 4'd2 ; - assign NOT_dmem_not_imem_07_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d338 = - !dmem_not_imem && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb$lookup[39] ; - assign NOT_dmem_not_imem_07_OR_NOT_rg_op_2_EQ_0_3_4_A_ETC___d114 = - !dmem_not_imem || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - !tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d621 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - rg_op != 2'd1 && ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d634 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d632 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d761 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d759 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d795 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d813 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d852 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d850 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d857 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d855 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d863 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d861 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d871 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d869 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d875 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d631 ; - assign NOT_master_xactor_rg_rd_data_94_BITS_2_TO_1_95_ETC___d919 = - master_xactor_rg_rd_data[2:1] != 2'b0 || - !_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - ((!_theResult____h23570[3] && !_theResult____h23570[1]) ? - !master_xactor_crg_rd_addr_full$port2__read : - _theResult____h23570[19:10] != 10'd0 || tlb$RDY_insert) ; - assign NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199 = - !ram_state_and_ctag_cset$DOB[22] || !rg_priv_6_ULE_0b1___d67 || - !rg_satp[31] || - tlb$RDY_lookup ; - assign NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d434 = - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 ; - assign NOT_req_f3_BITS_1_TO_0_344_EQ_0b0_345_346_AND__ETC___d1365 = - req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && - (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && - (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; - assign NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_7__ETC___d294 = - rg_f3 != 3'b011 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_rg_op_2_EQ_0_3_4_AND_NOT_rg_op_2_EQ_2_5_6__ETC___d389 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d443 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d631 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d758 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d850 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d855 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d861 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d869 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d629 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d756 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d816 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d822 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d828 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d834 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d345 = - (rg_priv != 2'b0 || tlb$lookup[40]) && - (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) && - (NOT_dmem_not_imem_07_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d338 || - dmem_not_imem_AND_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_ETC___d340 || - dmem_not_imem && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - tlb$lookup[38]) ; - assign NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d368 = - (rg_priv != 2'b0 || tlb$lookup[40]) && - (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) && - dmem_not_imem && - tlb$lookup[38] ; - assign NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d406 = - (rg_priv != 2'b0 || tlb$lookup[40]) && - (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) && - tlb$lookup[42] && - !pte___2__h6687[7] && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ; - assign NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d580 = - (rg_priv != 2'b0 || tlb$lookup[40]) && - (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) && - (!dmem_not_imem && tlb$lookup[39] || - dmem_not_imem && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112) ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d148 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d136 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d145 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d307 = - (NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d148 || - tlb$RDY_insert && tlb$RDY_lookup && f_pte_writebacks$FULL_N) && - (dmem_not_imem && !soc_map$m_is_mem_addr || - IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d305) ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || - tlb$lookup[68] && - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d345 && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d347 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d365 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d136 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d145 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d417 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d345 && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d347 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d418 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d417 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d425 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - (rg_priv != 2'b0 || tlb$lookup[40]) && - (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) && - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d421 && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d347 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d428 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d425 && - dmem_not_imem && - !soc_map$m_is_mem_addr && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d449 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d417 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d446 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d455 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d417 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d450 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15293) ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d456 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d455 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d580 && - tlb$lookup[42] ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d588 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d585 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d594 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d601 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d607 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d604 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d613 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d610 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d368 && - tlb$lookup[42] && - tlb$lookup[43] ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d623 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d621 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d636 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d634 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d763 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d761 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d768 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d764 || - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d631) ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d768 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d797 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d795 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d803 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - rg_lrsc_valid && - !rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d809 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !rg_lrsc_valid && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d815 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d813 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d820 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d816 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d820 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d826 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d822 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d832 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d828 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d832 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d838 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d834 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d839 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d838 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d846 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15293 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d847 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d846 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d852 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d857 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d865 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d863 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d871 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d877 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d875 ; - assign NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129 = - !tlb$lookup[42] || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - !tlb$lookup[43] ; - assign NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d145 = - !tlb$lookup[42] || !tlb$lookup[43] || pte___2__h6687[7] || - rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ; - assign _theResult____h23570 = - rg_pte_pa[2] ? - master_xactor_rg_rd_data[66:35] : - master_xactor_rg_rd_data[34:3] ; - assign _theResult___fst__h6315 = - tlb$lookup[68] ? _theResult___fst__h6387 : pa__h6215 ; - assign _theResult___fst__h6387 = - (rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129) ? - pa__h6215 : - _theResult___fst__h6689 ; - assign _theResult___snd_fst__h18939 = rg_st_amo_val << shift_bits__h18732 ; - assign _theResult___snd_fst__h22375 = - new_st_val__h19386 << shift_bits__h18732 ; - assign _theResult___snd_fst__h30128 = rg_st_amo_val << shift_bits__h31425 ; - assign _theResult___snd_fst__h31632 = st_val__h31369 << shift_bits__h31425 ; - assign _theResult___snd_fst__h6317 = - tlb$lookup[68] ? - _theResult___snd_fst__h6389 : - tlb$lookup[67:36] ; - assign _theResult___snd_fst__h6389 = - (rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129) ? - tlb$lookup[67:36] : - _theResult___snd_fst__h6827 ; - assign _theResult___snd_fst__h6827 = - (!pte___2__h6687[7] && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010)) ? - pte___1__h6904 : - pte___2__h6687 ; - assign access_exc_code__h3148 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd5 : - 4'd7) : - 4'd1 ; - assign addr__h7263 = { 30'd0, x1_avValue_pa__h6227 } ; - assign b__h23160 = - ctr_wr_rsps_pending_crg$EN_port0__write ? - ctr_wr_rsps_pending_crg$port0__write_1 : - ctr_wr_rsps_pending_crg ; - assign cfg_verbosity_read__5_ULE_1___d26 = cfg_verbosity <= 4'd1 ; - assign cline_addr__h25475 = { rg_pa[33:5], 5'd0 } ; - assign cline_fabric_addr__h25476 = { 30'd0, cline_addr__h25475 } ; - assign dmem_not_imem_AND_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_ETC___d340 = - dmem_not_imem && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112 ; - assign dmem_not_imem_OR_NOT_rg_op_2_EQ_0_3_4_AND_NOT__ETC___d106 = - dmem_not_imem || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - !tlb$lookup[39] ; - assign exc_code___1__h6589 = x1_avValue_exc_code__h6228 ; - assign ld_val8519_BITS_15_TO_0__q37 = ld_val__h28519[15:0] ; - assign ld_val8519_BITS_15_TO_8__q39 = ld_val__h28519[15:8] ; - assign ld_val8519_BITS_23_TO_16__q40 = ld_val__h28519[23:16] ; - assign ld_val8519_BITS_31_TO_0__q38 = ld_val__h28519[31:0] ; - assign ld_val8519_BITS_31_TO_16__q41 = ld_val__h28519[31:16] ; - assign ld_val8519_BITS_31_TO_24__q42 = ld_val__h28519[31:24] ; - assign ld_val8519_BITS_39_TO_32__q43 = ld_val__h28519[39:32] ; - assign ld_val8519_BITS_47_TO_32__q44 = ld_val__h28519[47:32] ; - assign ld_val8519_BITS_47_TO_40__q46 = ld_val__h28519[47:40] ; - assign ld_val8519_BITS_55_TO_48__q47 = ld_val__h28519[55:48] ; - assign ld_val8519_BITS_63_TO_32__q45 = ld_val__h28519[63:32] ; - assign ld_val8519_BITS_63_TO_48__q48 = ld_val__h28519[63:48] ; - assign ld_val8519_BITS_63_TO_56__q49 = ld_val__h28519[63:56] ; - assign ld_val8519_BITS_7_TO_0__q36 = ld_val__h28519[7:0] ; - assign lev_0_PTN_pa__h24214 = { _theResult____h23570[31:10], 12'b0 } ; - assign lev_0_pte_pa__h24216 = lev_0_PTN_pa__h24214 + vpn_0_pa__h24215 ; - assign lev_0_pte_pa_w64__h24217 = { lev_0_pte_pa__h24216[33:3], 3'b0 } ; - assign lev_0_pte_pa_w64_fa__h24218 = { 30'd0, lev_0_pte_pa_w64__h24217 } ; - assign lev_1_pte_pa__h23259 = satp_pa__h2468 + vpn_1_pa__h23258 ; - assign lev_1_pte_pa_w64__h23260 = { lev_1_pte_pa__h23259[33:3], 3'b0 } ; - assign lev_1_pte_pa_w64_fa__h23261 = { 30'd0, lev_1_pte_pa_w64__h23260 } ; - assign lrsc_result__h15293 = - !rg_lrsc_valid || - !rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234 ; - assign master_xactor_crg_rd_data_full_port1__read__93_ETC___d1176 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - (!_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2]) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - !_theResult____h23570[2] && - !_theResult____h23570[3] && - !_theResult____h23570[1] && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d958 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) && - _theResult____h23570[19:10] == 10'd0 ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d962 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) && - _theResult____h23570[19:10] == 10'd0 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d968 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) && - _theResult____h23570[19:10] != 10'd0 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d994 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign master_xactor_rg_rd_data_BITS_10_TO_3__q1 = - master_xactor_rg_rd_data[10:3] ; - assign master_xactor_rg_rd_data_BITS_18_TO_11__q4 = - master_xactor_rg_rd_data[18:11] ; - assign master_xactor_rg_rd_data_BITS_18_TO_3__q2 = - master_xactor_rg_rd_data[18:3] ; - assign master_xactor_rg_rd_data_BITS_26_TO_19__q5 = - master_xactor_rg_rd_data[26:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_19__q6 = - master_xactor_rg_rd_data[34:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_27__q7 = - master_xactor_rg_rd_data[34:27] ; - assign master_xactor_rg_rd_data_BITS_34_TO_3__q3 = - master_xactor_rg_rd_data[34:3] ; - assign master_xactor_rg_rd_data_BITS_42_TO_35__q8 = - master_xactor_rg_rd_data[42:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_35__q9 = - master_xactor_rg_rd_data[50:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_43__q11 = - master_xactor_rg_rd_data[50:43] ; - assign master_xactor_rg_rd_data_BITS_58_TO_51__q12 = - master_xactor_rg_rd_data[58:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_35__q10 = - master_xactor_rg_rd_data[66:35] ; - assign master_xactor_rg_rd_data_BITS_66_TO_51__q13 = - master_xactor_rg_rd_data[66:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_59__q14 = - master_xactor_rg_rd_data[66:59] ; - assign mem_req_wr_addr_awaddr__h31419 = { 30'd0, rg_pa } ; - assign mem_req_wr_addr_awaddr__h3403 = - { 30'd0, f_pte_writebacks$D_OUT[65:32] } ; - assign mem_req_wr_data_wdata__h3595 = st_val__h3324 << shift_bits__h3414 ; - assign mem_req_wr_data_wstrb__h3596 = - 8'b00001111 << f_pte_writebacks$D_OUT[34:32] ; - assign new_st_val__h19386 = - (rg_f3 == 3'b010) ? - new_st_val__h19668 : - _theResult_____2__h19664 ; - assign new_st_val__h19668 = { 32'd0, _theResult_____2__h19664[31:0] } ; - assign new_st_val__h19759 = - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 + - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ; - assign new_st_val__h20739 = w1__h19656 ^ w2__h31643 ; - assign new_st_val__h20743 = w1__h19656 & w2__h31643 ; - assign new_st_val__h20747 = w1__h19656 | w2__h31643 ; - assign new_st_val__h20751 = - (w1__h19656 < w2__h31643) ? w1__h19656 : w2__h31643 ; - assign new_st_val__h20756 = - (w1__h19656 <= w2__h31643) ? w2__h31643 : w1__h19656 ; - assign new_st_val__h20762 = - ((IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 ^ - 64'h8000000000000000) < - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ^ - 64'h8000000000000000)) ? - w1__h19656 : - w2__h31643 ; - assign new_st_val__h20767 = - ((IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 ^ - 64'h8000000000000000) <= - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ^ - 64'h8000000000000000)) ? - w2__h31643 : - w1__h19656 ; - assign new_st_val__h31653 = { 32'd0, _theResult_____2__h31649[31:0] } ; - assign new_st_val__h31744 = - new_ld_val__h31357 + - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ; - assign new_st_val__h33604 = w1__h31641 ^ w2__h31643 ; - assign new_st_val__h33608 = w1__h31641 & w2__h31643 ; - assign new_st_val__h33612 = w1__h31641 | w2__h31643 ; - assign new_st_val__h33616 = - (w1__h31641 < w2__h31643) ? w1__h31641 : w2__h31643 ; - assign new_st_val__h33621 = - (w1__h31641 <= w2__h31643) ? w2__h31643 : w1__h31641 ; - assign new_st_val__h33627 = - ((new_ld_val__h31357 ^ 64'h8000000000000000) < - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ^ - 64'h8000000000000000)) ? - w1__h31641 : - w2__h31643 ; - assign new_st_val__h33632 = - ((new_ld_val__h31357 ^ 64'h8000000000000000) <= - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ^ - 64'h8000000000000000)) ? - w2__h31643 : - w1__h31641 ; - assign new_value622_BITS_31_TO_0__q31 = new_value__h7622[31:0] ; - assign pa___1__h6695 = { tlb$lookup[67:46], rg_addr[11:0] } ; - assign pa___1__h6744 = { tlb$lookup[67:56], rg_addr[21:0] } ; - assign pa__h6215 = { 2'd0, rg_addr } ; - assign pte___1__h6876 = { tlb$lookup[67:43], 1'd1, tlb$lookup[41:36] } ; - assign pte___1__h6904 = - { pte___2__h6687[31:8], 1'd1, pte___2__h6687[6:0] } ; - assign pte___2__h6687 = - tlb$lookup[42] ? tlb$lookup[67:36] : pte___1__h6876 ; - assign ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 = - ram_state_and_ctag_cset$DOB[21:0] == - x1_avValue_pa__h6227[33:12] ; - assign ram_state_and_ctag_cset_b_read__73_BIT_22_74_A_ETC___d435 = - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d434 ; - assign req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374 = - req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || - req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || - req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; - assign result__h14033 = - { {56{word64440_BITS_15_TO_8__q18[7]}}, - word64440_BITS_15_TO_8__q18 } ; - assign result__h14061 = - { {56{word64440_BITS_23_TO_16__q19[7]}}, - word64440_BITS_23_TO_16__q19 } ; - assign result__h14089 = - { {56{word64440_BITS_31_TO_24__q21[7]}}, - word64440_BITS_31_TO_24__q21 } ; - assign result__h14117 = - { {56{word64440_BITS_39_TO_32__q22[7]}}, - word64440_BITS_39_TO_32__q22 } ; - assign result__h14145 = - { {56{word64440_BITS_47_TO_40__q25[7]}}, - word64440_BITS_47_TO_40__q25 } ; - assign result__h14173 = - { {56{word64440_BITS_55_TO_48__q26[7]}}, - word64440_BITS_55_TO_48__q26 } ; - assign result__h14201 = - { {56{word64440_BITS_63_TO_56__q28[7]}}, - word64440_BITS_63_TO_56__q28 } ; - assign result__h14246 = { 56'd0, word64__h7440[7:0] } ; - assign result__h14274 = { 56'd0, word64__h7440[15:8] } ; - assign result__h14302 = { 56'd0, word64__h7440[23:16] } ; - assign result__h14330 = { 56'd0, word64__h7440[31:24] } ; - assign result__h14358 = { 56'd0, word64__h7440[39:32] } ; - assign result__h14386 = { 56'd0, word64__h7440[47:40] } ; - assign result__h14414 = { 56'd0, word64__h7440[55:48] } ; - assign result__h14442 = { 56'd0, word64__h7440[63:56] } ; - assign result__h14487 = - { {48{word64440_BITS_15_TO_0__q16[15]}}, - word64440_BITS_15_TO_0__q16 } ; - assign result__h14515 = - { {48{word64440_BITS_31_TO_16__q20[15]}}, - word64440_BITS_31_TO_16__q20 } ; - assign result__h14543 = - { {48{word64440_BITS_47_TO_32__q23[15]}}, - word64440_BITS_47_TO_32__q23 } ; - assign result__h14571 = - { {48{word64440_BITS_63_TO_48__q27[15]}}, - word64440_BITS_63_TO_48__q27 } ; - assign result__h14612 = { 48'd0, word64__h7440[15:0] } ; - assign result__h14640 = { 48'd0, word64__h7440[31:16] } ; - assign result__h14668 = { 48'd0, word64__h7440[47:32] } ; - assign result__h14696 = { 48'd0, word64__h7440[63:48] } ; - assign result__h14737 = - { {32{word64440_BITS_31_TO_0__q17[31]}}, - word64440_BITS_31_TO_0__q17 } ; - assign result__h14765 = - { {32{word64440_BITS_63_TO_32__q24[31]}}, - word64440_BITS_63_TO_32__q24 } ; - assign result__h14804 = { 32'd0, word64__h7440[31:0] } ; - assign result__h14832 = { 32'd0, word64__h7440[63:32] } ; - assign result__h28579 = - { {56{master_xactor_rg_rd_data_BITS_10_TO_3__q1[7]}}, - master_xactor_rg_rd_data_BITS_10_TO_3__q1 } ; - assign result__h28609 = - { {56{master_xactor_rg_rd_data_BITS_18_TO_11__q4[7]}}, - master_xactor_rg_rd_data_BITS_18_TO_11__q4 } ; - assign result__h28636 = - { {56{master_xactor_rg_rd_data_BITS_26_TO_19__q5[7]}}, - master_xactor_rg_rd_data_BITS_26_TO_19__q5 } ; - assign result__h28663 = - { {56{master_xactor_rg_rd_data_BITS_34_TO_27__q7[7]}}, - master_xactor_rg_rd_data_BITS_34_TO_27__q7 } ; - assign result__h28690 = - { {56{master_xactor_rg_rd_data_BITS_42_TO_35__q8[7]}}, - master_xactor_rg_rd_data_BITS_42_TO_35__q8 } ; - assign result__h28717 = - { {56{master_xactor_rg_rd_data_BITS_50_TO_43__q11[7]}}, - master_xactor_rg_rd_data_BITS_50_TO_43__q11 } ; - assign result__h28744 = - { {56{master_xactor_rg_rd_data_BITS_58_TO_51__q12[7]}}, - master_xactor_rg_rd_data_BITS_58_TO_51__q12 } ; - assign result__h28771 = - { {56{master_xactor_rg_rd_data_BITS_66_TO_59__q14[7]}}, - master_xactor_rg_rd_data_BITS_66_TO_59__q14 } ; - assign result__h28815 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h28842 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h28869 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h28896 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h28923 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h28950 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h28977 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h29004 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h29048 = - { {48{master_xactor_rg_rd_data_BITS_18_TO_3__q2[15]}}, - master_xactor_rg_rd_data_BITS_18_TO_3__q2 } ; - assign result__h29075 = - { {48{master_xactor_rg_rd_data_BITS_34_TO_19__q6[15]}}, - master_xactor_rg_rd_data_BITS_34_TO_19__q6 } ; - assign result__h29102 = - { {48{master_xactor_rg_rd_data_BITS_50_TO_35__q9[15]}}, - master_xactor_rg_rd_data_BITS_50_TO_35__q9 } ; - assign result__h29129 = - { {48{master_xactor_rg_rd_data_BITS_66_TO_51__q13[15]}}, - master_xactor_rg_rd_data_BITS_66_TO_51__q13 } ; - assign result__h29169 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h29196 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h29223 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h29250 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h29290 = - { {32{master_xactor_rg_rd_data_BITS_34_TO_3__q3[31]}}, - master_xactor_rg_rd_data_BITS_34_TO_3__q3 } ; - assign result__h29317 = - { {32{master_xactor_rg_rd_data_BITS_66_TO_35__q10[31]}}, - master_xactor_rg_rd_data_BITS_66_TO_35__q10 } ; - assign result__h29355 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h29382 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; - assign result__h31832 = - { {56{ld_val8519_BITS_7_TO_0__q36[7]}}, - ld_val8519_BITS_7_TO_0__q36 } ; - assign result__h32740 = - { {56{ld_val8519_BITS_15_TO_8__q39[7]}}, - ld_val8519_BITS_15_TO_8__q39 } ; - assign result__h32768 = - { {56{ld_val8519_BITS_23_TO_16__q40[7]}}, - ld_val8519_BITS_23_TO_16__q40 } ; - assign result__h32796 = - { {56{ld_val8519_BITS_31_TO_24__q42[7]}}, - ld_val8519_BITS_31_TO_24__q42 } ; - assign result__h32824 = - { {56{ld_val8519_BITS_39_TO_32__q43[7]}}, - ld_val8519_BITS_39_TO_32__q43 } ; - assign result__h32852 = - { {56{ld_val8519_BITS_47_TO_40__q46[7]}}, - ld_val8519_BITS_47_TO_40__q46 } ; - assign result__h32880 = - { {56{ld_val8519_BITS_55_TO_48__q47[7]}}, - ld_val8519_BITS_55_TO_48__q47 } ; - assign result__h32908 = - { {56{ld_val8519_BITS_63_TO_56__q49[7]}}, - ld_val8519_BITS_63_TO_56__q49 } ; - assign result__h32953 = { 56'd0, ld_val__h28519[7:0] } ; - assign result__h32981 = { 56'd0, ld_val__h28519[15:8] } ; - assign result__h33009 = { 56'd0, ld_val__h28519[23:16] } ; - assign result__h33037 = { 56'd0, ld_val__h28519[31:24] } ; - assign result__h33065 = { 56'd0, ld_val__h28519[39:32] } ; - assign result__h33093 = { 56'd0, ld_val__h28519[47:40] } ; - assign result__h33121 = { 56'd0, ld_val__h28519[55:48] } ; - assign result__h33149 = { 56'd0, ld_val__h28519[63:56] } ; - assign result__h33194 = - { {48{ld_val8519_BITS_15_TO_0__q37[15]}}, - ld_val8519_BITS_15_TO_0__q37 } ; - assign result__h33222 = - { {48{ld_val8519_BITS_31_TO_16__q41[15]}}, - ld_val8519_BITS_31_TO_16__q41 } ; - assign result__h33250 = - { {48{ld_val8519_BITS_47_TO_32__q44[15]}}, - ld_val8519_BITS_47_TO_32__q44 } ; - assign result__h33278 = - { {48{ld_val8519_BITS_63_TO_48__q48[15]}}, - ld_val8519_BITS_63_TO_48__q48 } ; - assign result__h33319 = { 48'd0, ld_val__h28519[15:0] } ; - assign result__h33347 = { 48'd0, ld_val__h28519[31:16] } ; - assign result__h33375 = { 48'd0, ld_val__h28519[47:32] } ; - assign result__h33403 = { 48'd0, ld_val__h28519[63:48] } ; - assign result__h33444 = - { {32{ld_val8519_BITS_31_TO_0__q38[31]}}, - ld_val8519_BITS_31_TO_0__q38 } ; - assign result__h33472 = - { {32{ld_val8519_BITS_63_TO_32__q45[31]}}, - ld_val8519_BITS_63_TO_32__q45 } ; - assign result__h33511 = { 32'd0, ld_val__h28519[31:0] } ; - assign result__h33539 = { 32'd0, ld_val__h28519[63:32] } ; - assign result__h7677 = - { {56{word64440_BITS_7_TO_0__q15[7]}}, - word64440_BITS_7_TO_0__q15 } ; - assign rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d610 = - rg_amo_funct7[6:2] == 5'b00010 && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234 = - rg_lrsc_pa == x1_avValue_pa__h6227 ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d384 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d421 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - tlb$lookup[38] ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d446 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset_b_read__73_BIT_22_74_A_ETC___d435 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d444 ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d450 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d585 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d604 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d444 = - rg_op == 2'd1 && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d443 ; - assign rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d632 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d629 || - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d631 ; - assign rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d759 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d756 || - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d758 ; - assign rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d764 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) ; - assign rg_op_2_EQ_2_5_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d248 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15293 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 ; - assign rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123 = - rg_priv == 2'b0 && !tlb$lookup[40] || - rg_priv == 2'b01 && tlb$lookup[40] && !rg_sstatus_SUM || - dmem_not_imem_OR_NOT_rg_op_2_EQ_0_3_4_AND_NOT__ETC___d106 && - NOT_dmem_not_imem_07_OR_NOT_rg_op_2_EQ_0_3_4_A_ETC___d114 && - (!dmem_not_imem || rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - !tlb$lookup[38]) ; - assign rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d136 = - rg_priv == 2'b0 && !tlb$lookup[40] || - rg_priv == 2'b01 && tlb$lookup[40] && !rg_sstatus_SUM || - !dmem_not_imem || - !tlb$lookup[38] ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && tlb$lookup[68] && - (rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129) ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d309 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && !tlb$lookup[68] || - (rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 ? - tlb$RDY_lookup : - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d307) ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d353 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && - (rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129) && - tlb$lookup[68] ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && tlb$lookup[68] && - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d368 && - tlb$lookup[42] && - tlb$lookup[43] && - !pte___2__h6687[7] && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d392 = - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 || - dmem_not_imem && !soc_map$m_is_mem_addr || - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d384 || - NOT_rg_op_2_EQ_0_3_4_AND_NOT_rg_op_2_EQ_2_5_6__ETC___d389 ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d393 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && !tlb$lookup[68] || - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d392 ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d411 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && tlb$lookup[68] && - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d406 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403 && - dmem_not_imem && - tlb$lookup[38] && - tlb$lookup[43] ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d414 = - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403 && - (!dmem_not_imem || !tlb$lookup[38] || !tlb$lookup[43]) ; - assign rg_priv_6_ULE_0b1___d67 = rg_priv <= 2'b01 ; - assign rg_st_amo_val_BITS_31_TO_0__q32 = rg_st_amo_val[31:0] ; - assign rg_state_0_EQ_12_043_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d1045 = - rg_state == 4'd12 && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - b__h23160 == 4'd0 ; - assign rg_state_0_EQ_3_12_AND_NOT_rg_op_2_EQ_0_3_4_AN_ETC___d316 = - rg_state == 4'd3 && - (rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - crg_sb_to_load_delay$port0__write_1 == 11'd0) ; - assign satp_pa__h2468 = { rg_satp[21:0], 12'b0 } ; - assign shift_bits__h18732 = { x1_avValue_pa__h6227[2:0], 3'b0 } ; - assign shift_bits__h31425 = { rg_pa[2:0], 3'b0 } ; - assign shift_bits__h3414 = { f_pte_writebacks$D_OUT[34:32], 3'b0 } ; - assign st_val__h31369 = - (rg_f3 == 3'b010) ? - new_st_val__h31653 : - _theResult_____2__h31649 ; - assign st_val__h3324 = { 32'd0, f_pte_writebacks$D_OUT[31:0] } ; - assign strobe64__h18865 = 8'b00000001 << x1_avValue_pa__h6227[2:0] ; - assign strobe64__h18867 = 8'b00000011 << x1_avValue_pa__h6227[2:0] ; - assign strobe64__h18869 = 8'b00001111 << x1_avValue_pa__h6227[2:0] ; - assign strobe64__h31558 = 8'b00000001 << rg_pa[2:0] ; - assign strobe64__h31560 = 8'b00000011 << rg_pa[2:0] ; - assign strobe64__h31562 = 8'b00001111 << rg_pa[2:0] ; - assign tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112 = - tlb$lookup[37] | y__h6515 ; - assign tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d347 = - tlb$lookup[42] && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - tlb$lookup[43]) ; - assign vpn_0_pa__h24215 = { 22'd0, rg_addr[21:12], 2'd0 } ; - assign vpn_1_pa__h23258 = { 22'd0, rg_addr[31:22], 2'd0 } ; - assign w11637_BITS_31_TO_0__q51 = w1__h31637[31:0] ; - assign w1___1__h19727 = { 32'd0, new_value__h7622[31:0] } ; - assign w1___1__h31712 = { 32'd0, w1__h31637[31:0] } ; - assign w2___1__h31713 = { 32'd0, rg_st_amo_val[31:0] } ; - assign w2__h31643 = (rg_f3 == 3'b010) ? w2___1__h31713 : rg_st_amo_val ; - assign word64440_BITS_15_TO_0__q16 = word64__h7440[15:0] ; - assign word64440_BITS_15_TO_8__q18 = word64__h7440[15:8] ; - assign word64440_BITS_23_TO_16__q19 = word64__h7440[23:16] ; - assign word64440_BITS_31_TO_0__q17 = word64__h7440[31:0] ; - assign word64440_BITS_31_TO_16__q20 = word64__h7440[31:16] ; - assign word64440_BITS_31_TO_24__q21 = word64__h7440[31:24] ; - assign word64440_BITS_39_TO_32__q22 = word64__h7440[39:32] ; - assign word64440_BITS_47_TO_32__q23 = word64__h7440[47:32] ; - assign word64440_BITS_47_TO_40__q25 = word64__h7440[47:40] ; - assign word64440_BITS_55_TO_48__q26 = word64__h7440[55:48] ; - assign word64440_BITS_63_TO_32__q24 = word64__h7440[63:32] ; - assign word64440_BITS_63_TO_48__q27 = word64__h7440[63:48] ; - assign word64440_BITS_63_TO_56__q28 = word64__h7440[63:56] ; - assign word64440_BITS_7_TO_0__q15 = word64__h7440[7:0] ; - assign word64__h7440 = ram_word64_set$DOB & y__h7713 ; - assign x1_avValue_exc_code__h6228 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd13 : - 4'd15) : - 4'd12 ; - assign x1_avValue_pa__h6227 = - (rg_priv_6_ULE_0b1___d67 && rg_satp[31]) ? - _theResult___fst__h6315 : - pa__h6215 ; - assign x1_avValue_pte__h6230 = - (rg_priv_6_ULE_0b1___d67 && rg_satp[31]) ? - _theResult___snd_fst__h6317 : - tlb$lookup[67:36] ; - assign x__h15303 = { 63'd0, lrsc_result__h15293 } ; - assign y__h6515 = rg_mstatus_MXR & tlb$lookup[39] ; - assign y__h7713 = - {64{ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178}} ; - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h30942 = 3'b0; - 2'b01: value__h30942 = 3'b001; - 2'b10: value__h30942 = 3'b010; - 2'd3: value__h30942 = 3'b011; - endcase - end - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h33968 = 3'b0; - 2'b01: value__h33968 = 3'b001; - 2'b10: value__h33968 = 3'b010; - 2'b11: value__h33968 = 3'b011; - endcase - end - always@(tlb$lookup or pa__h6215 or pa___1__h6695 or pa___1__h6744) - begin - case (tlb$lookup[35:34]) - 2'd0: _theResult___fst__h6689 = pa___1__h6695; - 2'd1: _theResult___fst__h6689 = pa___1__h6744; - default: _theResult___fst__h6689 = pa__h6215; - endcase - end - always@(rg_f3 or strobe64__h31558 or strobe64__h31560 or strobe64__h31562) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h31625 = strobe64__h31558; - 2'b01: mem_req_wr_data_wstrb__h31625 = strobe64__h31560; - 2'b10: mem_req_wr_data_wstrb__h31625 = strobe64__h31562; - 2'b11: mem_req_wr_data_wstrb__h31625 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h30128) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h30120 = _theResult___snd_fst__h30128; - 2'd3: mem_req_wr_data_wdata__h30120 = rg_st_amo_val; - endcase - end - always@(rg_f3 or strobe64__h18865 or strobe64__h18867 or strobe64__h18869) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h18932 = strobe64__h18865; - 2'b01: mem_req_wr_data_wstrb__h18932 = strobe64__h18867; - 2'b10: mem_req_wr_data_wstrb__h18932 = strobe64__h18869; - 2'b11: mem_req_wr_data_wstrb__h18932 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h18939) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h18931 = _theResult___snd_fst__h18939; - 2'd3: mem_req_wr_data_wdata__h18931 = rg_st_amo_val; - endcase - end - always@(rg_f3 or rg_priv_6_ULE_0b1___d67 or rg_satp or tlb$RDY_lookup) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01: - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$RDY_lookup; - default: IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 = - rg_f3[1:0] != 2'b10 || !rg_priv_6_ULE_0b1___d67 || - !rg_satp[31] || - tlb$RDY_lookup; - endcase - end - always@(rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199) - begin - case (rg_addr[2:0]) - 3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 = - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199; - 3'd7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 = - rg_addr[2:0] != 3'h7 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199; - endcase - end - always@(rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199) - begin - case (rg_addr[2:0]) - 3'h0, 3'h2, 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 = - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 = - rg_addr[2:0] != 3'h6 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199; - endcase - end - always@(rg_f3 or - rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217) - begin - case (rg_f3) - 3'b0, 3'b100: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203; - 3'b001, 3'b101: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211; - 3'b010, 3'b110: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217; - default: IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - rg_f3 != 3'b011 || rg_addr[2:0] != 3'h0 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199; - endcase - end - always@(rg_amo_funct7 or - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225) - begin - case (rg_amo_funct7[6:2]) - 5'b0, 5'b00100, 5'b01000, 5'b01100, 5'b10000, 5'b11000, 5'b11100: - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 = - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225; - default: CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 = - rg_amo_funct7[6:2] != 5'b10100 || - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225; - endcase - end - always@(x1_avValue_pa__h6227 or - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d284 or - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d285 = - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29; - 3'd7: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d285 = - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d284; - endcase - end - always@(x1_avValue_pa__h6227 or - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d289 or - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0, 3'h2, 3'h4: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d290 = - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29; - default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d290 = - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d289; - endcase - end - always@(rg_f3 or - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_7__ETC___d294 or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d285 or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d290 or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d293) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d285; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d290; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d293; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297 = - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_7__ETC___d294; - endcase - end - always@(rg_addr or - result__h7677 or - result__h14033 or - result__h14061 or - result__h14089 or - result__h14117 or - result__h14145 or result__h14173 or result__h14201) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h7677; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14033; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14061; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14089; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14117; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14145; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14173; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14201; - endcase - end - always@(rg_addr or - result__h14246 or - result__h14274 or - result__h14302 or - result__h14330 or - result__h14358 or - result__h14386 or result__h14414 or result__h14442) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14246; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14274; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14302; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14330; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14358; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14386; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14414; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14442; - endcase - end - always@(rg_addr or - result__h14487 or - result__h14515 or result__h14543 or result__h14571) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 = - result__h14487; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 = - result__h14515; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 = - result__h14543; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 = - result__h14571; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 = - 64'd0; - endcase - end - always@(rg_addr or - result__h14612 or - result__h14640 or result__h14668 or result__h14696) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 = - result__h14612; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 = - result__h14640; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 = - result__h14668; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 = - result__h14696; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 = - 64'd0; - endcase - end - always@(rg_addr or result__h14804 or result__h14832) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559 = - result__h14804; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559 = - result__h14832; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559 = - 64'd0; - endcase - end - always@(rg_addr or result__h14737 or result__h14765) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30 = - result__h14737; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30 = - result__h14765; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559) - begin - case (rg_f3) - 3'b0: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513; - 3'b001: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541; - 3'b010: - new_value__h7622 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30; - 3'b011: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560; - 3'b100: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529; - 3'b101: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549; - 3'b110: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559; - 3'd7: new_value__h7622 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 or - w1___1__h19727 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559) - begin - case (rg_f3) - 3'b0: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513; - 3'b001: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541; - 3'b010: w1__h19656 = w1___1__h19727; - 3'b011: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560; - 3'b100: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529; - 3'b101: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549; - 3'b110: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559; - 3'd7: w1__h19656 = 64'd0; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 = - { ram_word64_set$DOB[63:16], rg_st_amo_val[15:0] }; - 3'h2: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 = - { rg_st_amo_val[15:0], ram_word64_set$DOB[47:0] }; - default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 = - ram_word64_set$DOB; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:8], rg_st_amo_val[7:0] }; - 3'h1: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:16], - rg_st_amo_val[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:24], - rg_st_amo_val[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:40], - rg_st_amo_val[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:56], - rg_st_amo_val[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { rg_st_amo_val[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 or - new_value622_BITS_31_TO_0__q31 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513; - 3'b001: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541; - 3'b010: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - { {32{new_value622_BITS_31_TO_0__q31[31]}}, - new_value622_BITS_31_TO_0__q31 }; - 3'b011: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560; - 3'b100: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529; - 3'b101: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549; - 3'b110: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559; - 3'd7: IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h20767 or - new_st_val__h19759 or - w2__h31643 or - new_st_val__h20739 or - new_st_val__h20747 or - new_st_val__h20743 or - new_st_val__h20762 or new_st_val__h20751 or new_st_val__h20756) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h19664 = new_st_val__h19759; - 5'b00001: _theResult_____2__h19664 = w2__h31643; - 5'b00100: _theResult_____2__h19664 = new_st_val__h20739; - 5'b01000: _theResult_____2__h19664 = new_st_val__h20747; - 5'b01100: _theResult_____2__h19664 = new_st_val__h20743; - 5'b10000: _theResult_____2__h19664 = new_st_val__h20762; - 5'b11000: _theResult_____2__h19664 = new_st_val__h20751; - 5'b11100: _theResult_____2__h19664 = new_st_val__h20756; - default: _theResult_____2__h19664 = new_st_val__h20767; - endcase - end - always@(rg_f3 or new_st_val__h19386 or _theResult___snd_fst__h22375) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h22367 = _theResult___snd_fst__h22375; - 2'd3: mem_req_wr_data_wdata__h22367 = new_st_val__h19386; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or new_st_val__h19386) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 = - { ram_word64_set$DOB[63:16], new_st_val__h19386[15:0] }; - 3'h2: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 = - { ram_word64_set$DOB[63:32], - new_st_val__h19386[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 = - { ram_word64_set$DOB[63:48], - new_st_val__h19386[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 = - { new_st_val__h19386[15:0], ram_word64_set$DOB[47:0] }; - default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 = - ram_word64_set$DOB; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or new_st_val__h19386) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:8], new_st_val__h19386[7:0] }; - 3'h1: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:16], - new_st_val__h19386[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:24], - new_st_val__h19386[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:32], - new_st_val__h19386[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:40], - new_st_val__h19386[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:48], - new_st_val__h19386[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:56], - new_st_val__h19386[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { new_st_val__h19386[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - { ram_word64_set$DOB[63:32], rg_st_amo_val[31:0] }; - 3'h4: - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - { rg_st_amo_val[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 or - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33 or - rg_st_amo_val) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 = - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33; - 3'b011: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 = - rg_st_amo_val; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or - result__h29169 or - result__h29196 or result__h29223 or result__h29250) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 = - result__h29169; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 = - result__h29196; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 = - result__h29223; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 = - result__h29250; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 = - 64'd0; - endcase - end - always@(rg_addr or - result__h29048 or - result__h29075 or result__h29102 or result__h29129) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 = - result__h29048; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 = - result__h29075; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 = - result__h29102; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 = - result__h29129; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28815 or - result__h28842 or - result__h28869 or - result__h28896 or - result__h28923 or - result__h28950 or result__h28977 or result__h29004) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28815; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28842; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28869; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28896; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28923; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28950; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28977; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h29004; - endcase - end - always@(rg_addr or - result__h28579 or - result__h28609 or - result__h28636 or - result__h28663 or - result__h28690 or - result__h28717 or result__h28744 or result__h28771) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28579; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28609; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28636; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28663; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28690; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28717; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28744; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28771; - endcase - end - always@(rg_addr or result__h29290 or result__h29317) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34 = - result__h29290; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34 = - result__h29317; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34 = - 64'd0; - endcase - end - always@(rg_addr or result__h29355 or result__h29382) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35 = - result__h29355; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35 = - result__h29382; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 or - CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34 or - rg_addr or - master_xactor_rg_rd_data or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 or - CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35) - begin - case (rg_f3) - 3'b0: - ld_val__h28519 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084; - 3'b001: - ld_val__h28519 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112; - 3'b010: - ld_val__h28519 = - CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34; - 3'b011: - ld_val__h28519 = - (rg_addr[2:0] == 3'h0) ? master_xactor_rg_rd_data[66:3] : 64'd0; - 3'b100: - ld_val__h28519 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100; - 3'b101: - ld_val__h28519 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120; - 3'b110: - ld_val__h28519 = - CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35; - 3'd7: ld_val__h28519 = 64'd0; - endcase - end - always@(rg_addr or result__h33511 or result__h33539) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252 = - result__h33511; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252 = - result__h33539; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252 = - 64'd0; - endcase - end - always@(rg_addr or - result__h33319 or - result__h33347 or result__h33375 or result__h33403) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 = - result__h33319; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 = - result__h33347; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 = - result__h33375; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 = - result__h33403; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 = - 64'd0; - endcase - end - always@(rg_addr or - result__h33194 or - result__h33222 or result__h33250 or result__h33278) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 = - result__h33194; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 = - result__h33222; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 = - result__h33250; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 = - result__h33278; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 = - 64'd0; - endcase - end - always@(rg_addr or - result__h32953 or - result__h32981 or - result__h33009 or - result__h33037 or - result__h33065 or - result__h33093 or result__h33121 or result__h33149) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h32953; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h32981; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33009; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33037; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33065; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33093; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33121; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33149; - endcase - end - always@(rg_addr or - result__h31832 or - result__h32740 or - result__h32768 or - result__h32796 or - result__h32824 or - result__h32852 or result__h32880 or result__h32908) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h31832; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32740; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32768; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32796; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32824; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32852; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32880; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32908; - endcase - end - always@(rg_addr or result__h33444 or result__h33472) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50 = - result__h33444; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50 = - result__h33472; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 or - CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252) - begin - case (rg_f3) - 3'b0: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206; - 3'b001: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234; - 3'b010: - w1__h31637 = - CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50; - 3'b011: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253; - 3'b100: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222; - 3'b101: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242; - 3'b110: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252; - 3'd7: w1__h31637 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 or - w1___1__h31712 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252) - begin - case (rg_f3) - 3'b0: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206; - 3'b001: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234; - 3'b010: w1__h31641 = w1___1__h31712; - 3'b011: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253; - 3'b100: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222; - 3'b101: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242; - 3'b110: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252; - 3'd7: w1__h31641 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 or - w11637_BITS_31_TO_0__q51 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252) - begin - case (rg_f3) - 3'b0: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206; - 3'b001: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234; - 3'b010: - new_ld_val__h31357 = - { {32{w11637_BITS_31_TO_0__q51[31]}}, - w11637_BITS_31_TO_0__q51 }; - 3'b011: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253; - 3'b100: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222; - 3'b101: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242; - 3'b110: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252; - 3'd7: new_ld_val__h31357 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h33632 or - new_st_val__h31744 or - w2__h31643 or - new_st_val__h33604 or - new_st_val__h33612 or - new_st_val__h33608 or - new_st_val__h33627 or new_st_val__h33616 or new_st_val__h33621) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h31649 = new_st_val__h31744; - 5'b00001: _theResult_____2__h31649 = w2__h31643; - 5'b00100: _theResult_____2__h31649 = new_st_val__h33604; - 5'b01000: _theResult_____2__h31649 = new_st_val__h33612; - 5'b01100: _theResult_____2__h31649 = new_st_val__h33608; - 5'b10000: _theResult_____2__h31649 = new_st_val__h33627; - 5'b11000: _theResult_____2__h31649 = new_st_val__h33616; - 5'b11100: _theResult_____2__h31649 = new_st_val__h33621; - default: _theResult_____2__h31649 = new_st_val__h33632; - endcase - end - always@(rg_f3 or st_val__h31369 or _theResult___snd_fst__h31632) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h31624 = _theResult___snd_fst__h31632; - 2'd3: mem_req_wr_data_wdata__h31624 = st_val__h31369; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or new_st_val__h19386) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - { ram_word64_set$DOB[63:32], new_st_val__h19386[31:0] }; - 3'h4: - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - { new_st_val__h19386[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 or - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52 or - new_st_val__h19386) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 = - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52; - 3'b011: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 = - new_st_val__h19386; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d574) - begin - case (rg_f3) - 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: - new_value__h17651 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d574; - 3'd7: new_value__h17651 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 7'd0; - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_sb_to_load_delay$EN) - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY - crg_sb_to_load_delay$D_IN; - if (ctr_wr_rsps_pending_crg$EN) - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY - ctr_wr_rsps_pending_crg$D_IN; - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_cset_in_cache$EN) - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN; - if (rg_lower_word32_full$EN) - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY - rg_lower_word32_full$D_IN; - if (rg_lrsc_valid$EN) - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; - if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN; - if (rg_amo_funct7$EN) - rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN; - if (rg_error_during_refill$EN) - rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY - rg_error_during_refill$D_IN; - if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN; - if (rg_lower_word32$EN) - rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN; - if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN; - if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN; - if (rg_priv$EN) rg_priv <= `BSV_ASSIGNMENT_DELAY rg_priv$D_IN; - if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN; - if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_st_amo_val$EN) - rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN; - if (rg_word64_set_in_cache$EN) - rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY - rg_word64_set_in_cache$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_sb_to_load_delay = 11'h2AA; - ctr_wr_rsps_pending_crg = 4'hA; - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; - rg_addr = 32'hAAAAAAAA; - rg_amo_funct7 = 7'h2A; - rg_cset_in_cache = 7'h2A; - rg_error_during_refill = 1'h0; - rg_exc_code = 4'hA; - rg_f3 = 3'h2; - rg_ld_val = 64'hAAAAAAAAAAAAAAAA; - rg_lower_word32 = 32'hAAAAAAAA; - rg_lower_word32_full = 1'h0; - rg_lrsc_pa = 34'h2AAAAAAAA; - rg_lrsc_valid = 1'h0; - rg_mstatus_MXR = 1'h0; - rg_op = 2'h2; - rg_pa = 34'h2AAAAAAAA; - rg_priv = 2'h2; - rg_pte_pa = 34'h2AAAAAAAA; - rg_satp = 32'hAAAAAAAA; - rg_sstatus_SUM = 1'h0; - rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - rg_word64_set_in_cache = 9'h0AA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - begin - v__h4748 = $stime; - #0; - end - v__h4742 = v__h4748 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h4742, - "D_MMU_Cache", - $signed(32'd128), - $signed(32'd1)); - else - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h4742, - "I_MMU_Cache", - $signed(32'd128), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - !cfg_verbosity_read__5_ULE_1___d26 && - f_reset_reqs$D_OUT) - begin - v__h4849 = $stime; - #0; - end - v__h4843 = v__h4849 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - !cfg_verbosity_read__5_ULE_1___d26 && - f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: Flushed", v__h4843, "D_MMU_Cache"); - else - $display("%0d: %s.rl_reset: Flushed", v__h4843, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_rereq && !cfg_verbosity_read__5_ULE_1___d26) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - rg_addr[11:5], - rg_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h29722 = $stime; - #0; - end - v__h29716 = v__h29722 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29716, - "D_MMU_Cache", - rg_addr, - rg_ld_val); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29716, - "I_MMU_Cache", - rg_addr, - rg_ld_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h30620 = $stime; - #0; - end - v__h30614 = v__h30620 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h30614, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h30614, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__5_ULE_1___d26) - $display(" FAIL due to I/O address."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__5_ULE_1___d26) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h4385 = $stime; - #0; - end - v__h4379 = v__h4385 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_start_reset", v__h4379, "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_reset", v__h4379, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h5300 = $stime; - #0; - end - v__h5294 = v__h5300 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h5294, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h5294, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - rg_satp[31]) - $display(" Priv:%0d SATP:{mode %0d asid %0h pa %0h} VA:%0h.%0h.%0h", - rg_priv, - rg_satp[31], - rg_satp[30:22], - satp_pa__h2468, - rg_addr[31:22], - rg_addr[21:12], - rg_addr[11:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", - { 2'd0, rg_addr[31:12] }, - rg_addr[11:5], - rg_addr[4:3], - rg_addr[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" CSet 0x%0x: (state, tag):", rg_addr[11:5]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" ("); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - ram_state_and_ctag_cset$DOB[22]) - $write("CTAG_CLEAN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - !ram_state_and_ctag_cset$DOB[22]) - $write("CTAG_EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - ram_state_and_ctag_cset$DOB[22]) - $write(", 0x%0x", ram_state_and_ctag_cset$DOB[21:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - !ram_state_and_ctag_cset$DOB[22]) - $write(", --"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(")"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" TLB result: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d353) - $write("VM_XLATE_EXCEPTION"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - rg_priv_6_ULE_0b1___d67 && - rg_satp[31] && - !tlb$lookup[68]) - $write("VM_XLATE_TLB_MISS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", x1_avValue_exc_code__h6228); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "pte_modified: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d365) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", x1_avValue_pte__h6230, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $display(" fa_record_pte_A_D_updates:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("TLB_Lookup_Result { ", "hit: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", tlb$lookup[67:36]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pte_level: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", tlb$lookup[35:34]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pte_pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", tlb$lookup[33:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d411) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d414) - $write("VM_XLATE_EXCEPTION"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", x1_avValue_exc_code__h6228); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pte_modified: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d414) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d411) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", x1_avValue_pte__h6230, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d428) - $display(" => IO_REQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d588) - begin - v__h14916 = $stime; - #0; - end - v__h14910 = v__h14916 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d588) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h14910, - "D_MMU_Cache", - rg_addr, - word64__h7440, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h14910, - "I_MMU_Cache", - rg_addr, - word64__h7440, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d601) - $display(" AMO LR: reserving PA 0x%0h", x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d588) - $display(" Read-hit: addr 0x%0h word64 0x%0h", - rg_addr, - word64__h7440); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d607) - $display(" Read Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d613) - $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", - rg_lrsc_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d797) - $display(" ST: cancelling LR/SC reservation for PA", - x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d803) - $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", - rg_lrsc_pa, - x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d809) - $display(" AMO SC: fail due to invalid LR/SC reservation"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d815) - $display(" AMO SC result = %0d", lrsc_result__h15293); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821) - $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", - x1_avValue_pa__h6227, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821) - $write(" 0x%0x", - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d826) - $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", - x1_avValue_pa__h6227, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d839) - begin - v__h19135 = $stime; - #0; - end - v__h19129 = v__h19135 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d839) - $display("%0d: ERROR: CreditCounter: overflow", v__h19129); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d839) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", addr__h7263); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", value__h33968); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", mem_req_wr_data_wdata__h18931); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", mem_req_wr_data_wstrb__h18932); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $display(" => rl_write_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d847) - begin - v__h18560 = $stime; - #0; - end - v__h18554 = v__h18560 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d847) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h18554, - "D_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h18554, - "I_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d847) - $display(" AMO SC: Fail response for addr 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854) - $display(" AMO Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", - rg_addr, - rg_amo_funct7, - rg_f3, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $display(" PA 0x%0h ", x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $display(" Cache word64 0x%0h, load-result 0x%0h", - word64__h7440, - word64__h7440); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $display(" 0x%0h op 0x%0h -> 0x%0h", - word64__h7440, - word64__h7440, - new_st_val__h19386); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(" 0x%0x", - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d865) - begin - v__h22571 = $stime; - #0; - end - v__h22565 = v__h22571 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d865) - $display("%0d: ERROR: CreditCounter: overflow", v__h22565); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d865) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", addr__h7263); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", value__h33968); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", mem_req_wr_data_wdata__h22367); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", mem_req_wr_data_wstrb__h18932); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873) - $display(" AMO_op: cancelling LR/SC reservation for PA", - x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935) - begin - v__h24184 = $stime; - #0; - end - v__h24178 = v__h24184 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h24178, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h24178, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - begin - v__h23942 = $stime; - #0; - end - v__h23936 = v__h23942 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - if (dmem_not_imem) - $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0", - v__h23936, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - else - $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0", - v__h23936, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $display(" Req for level 0 PTE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", lev_0_pte_pa_w64_fa__h24218); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d962) - begin - v__h24605 = $stime; - #0; - end - v__h24599 = v__h24605 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d962) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage", - v__h24599, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage", - v__h24599, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d962) - $display(" Addr Space megapage pa: 0x%0h", lev_0_PTN_pa__h24214); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d968) - begin - v__h24493 = $stime; - #0; - end - v__h24487 = v__h24493 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d968) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h", - v__h24487, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h", - v__h24487, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) && - _theResult____h23570[19:10] != 10'd0) - $display(" Invalid PTE: PPN [0] is not zero; page fault %0d", - exc_code___1__h6589); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h24113 = $stime; - #0; - end - v__h24107 = v__h24113 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h24107, - "D_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3148); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h24107, - "I_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935) - begin - v__h25145 = $stime; - #0; - end - v__h25139 = v__h25145 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h25139, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h25139, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - begin - v__h25216 = $stime; - #0; - end - v__h25210 = v__h25216 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d", - v__h25210, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d", - v__h25210, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d994) - begin - v__h25298 = $stime; - #0; - end - v__h25292 = v__h25298 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d994) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE", - v__h25292, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE", - v__h25292, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d994) - $display(" Addr Space page pa: 0x%0h", lev_0_PTN_pa__h24214); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h25074 = $stime; - #0; - end - v__h25068 = v__h25074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h25068, - "D_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3148); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h25068, - "I_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - begin - v__h26206 = $stime; - #0; - end - v__h26200 = v__h26206 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h26200, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h26200, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h26428 = $stime; - #0; - end - v__h26422 = v__h26428 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h26422, - "D_MMU_Cache", - access_exc_code__h3148); - else - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h26422, - "I_MMU_Cache", - access_exc_code__h3148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 && - (master_xactor_rg_rd_data[2:1] != 2'b0 || rg_error_during_refill) && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" => MODULE_EXCEPTION_RSP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !rg_error_during_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" => CACHE_REREQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", - rg_word64_set_in_cache, - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(" 0x%0x", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h28410 = $stime; - #0; - end - v__h28404 = v__h28410 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h28404, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h28404, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h29510 = $stime; - #0; - end - v__h29504 = v__h29510 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29504, - "D_MMU_Cache", - rg_addr, - ld_val__h28519); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29504, - "I_MMU_Cache", - rg_addr, - ld_val__h28519); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h29617 = $stime; - #0; - end - v__h29611 = v__h29617 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h29611, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h29611, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h29802 = $stime; - #0; - end - v__h29796 = v__h29802 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h29796, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h29796, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h30324 = $stime; - #0; - end - v__h30318 = v__h30324 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h30318); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_addr_awaddr__h31419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", value__h33968); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wdata__h30120); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wstrb__h31625); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h30738 = $stime; - #0; - end - v__h30732 = v__h30738 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h30732, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h30732, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_addr_awaddr__h31419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", value__h30942); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h3751 = $stime; - #0; - end - v__h3745 = v__h3751 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h3745); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_addr_awaddr__h3403); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'b010); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wdata__h3595); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wstrb__h3596); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h31056 = $stime; - #0; - end - v__h31050 = v__h31056 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h31050, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h31050, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h31231 = $stime; - #0; - end - v__h31225 = v__h31231 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h31225, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h31225, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h33844 = $stime; - #0; - end - v__h33838 = v__h33844 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h33838); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_addr_awaddr__h31419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", value__h33968); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wdata__h31624); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wstrb__h31625); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h34096 = $stime; - #0; - end - v__h34090 = v__h34096 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h34090, - "D_MMU_Cache", - rg_addr, - new_ld_val__h31357); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h34090, - "I_MMU_Cache", - rg_addr, - new_ld_val__h31357); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h31327 = $stime; - #0; - end - v__h31321 = v__h31327 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h31321, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h31321, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h23206 = $stime; - #0; - end - v__h23200 = v__h23206 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 1 PTE", - v__h23200, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 1 PTE", - v__h23200, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", lev_1_pte_pa_w64_fa__h23261); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'b010); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h25423 = $stime; - #0; - end - v__h25417 = v__h25423 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_start_cache_refill: ", - v__h25417, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_cache_refill: ", - v__h25417, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", cline_fabric_addr__h25476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" Victim way %0d; => CACHE_REFILL", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h28036 = $stime; - #0; - end - v__h28030 = v__h28036 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h28030, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h28030, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_addr_awaddr__h31419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", value__h30942); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h35065 = $stime; - #0; - end - v__h35059 = v__h35065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $write("%0d: %s.req: op:", v__h35059, "D_MMU_Cache"); - else - $write("%0d: %s.req: op:", v__h35059, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_op == 2'd0) - $write("CACHE_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_op == 2'd1) - $write("CACHE_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_op != 2'd0 && - req_op != 2'd1) - $write("CACHE_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", - req_f3, - req_addr, - req_st_value); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_priv == 2'b0) - $write("U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_priv == 2'b01) - $write("S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_priv == 2'b11) - $write("M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_priv != 2'b0 && - req_priv != 2'b01 && - req_priv != 2'b11) - $write("RESERVED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26) - $display(" amo_funct7 = 0x%0h", req_amo_funct7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && - req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374 && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - req_addr[11:5], - req_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_tlb_flush && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h36219 = $stime; - #0; - end - v__h36213 = v__h36219 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_tlb_flush && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.tlb_flush", v__h36213, "D_MMU_Cache"); - else - $display("%0d: %s.tlb_flush", v__h36213, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h34716 = $stime; - #0; - end - v__h34710 = v__h34716 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h34710, - "D_MMU_Cache", - $unsigned(b__h23160)); - else - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h34710, - "I_MMU_Cache", - $unsigned(b__h23160)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - begin - v__h34677 = $stime; - #0; - end - v__h34671 = v__h34677 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - if (dmem_not_imem) - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h34671, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h34671, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("\n"); - end - // synopsys translate_on -endmodule // mkMMU_Cache - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v deleted file mode 100644 index f673c615..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v +++ /dev/null @@ -1,2169 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// to_raw_mem_response_put I 256 -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_to_raw_mem_response_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Controller(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [63 : 0] slave_rdata; - wire [7 : 0] status; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // inlined wires - reg [353 : 0] f_raw_mem_reqs_rv$port1__write_1; - wire [353 : 0] f_raw_mem_reqs_rv$port1__read, - f_raw_mem_reqs_rv$port2__read, - f_raw_mem_reqs_rv$port3__read; - wire [256 : 0] f_raw_mem_rsps_rv$port1__read, - f_raw_mem_rsps_rv$port1__write_1, - f_raw_mem_rsps_rv$port2__read, - f_raw_mem_rsps_rv$port3__read; - wire [170 : 0] f_reqs_rv$port1__read, - f_reqs_rv$port1__write_1, - f_reqs_rv$port2__read; - wire f_raw_mem_reqs_rv$EN_port1__write, - f_reqs_rv$EN_port0__write, - f_reqs_rv$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register f_raw_mem_reqs_rv - reg [353 : 0] f_raw_mem_reqs_rv; - wire [353 : 0] f_raw_mem_reqs_rv$D_IN; - wire f_raw_mem_reqs_rv$EN; - - // register f_raw_mem_rsps_rv - reg [256 : 0] f_raw_mem_rsps_rv; - wire [256 : 0] f_raw_mem_rsps_rv$D_IN; - wire f_raw_mem_rsps_rv$EN; - - // register f_reqs_rv - reg [170 : 0] f_reqs_rv; - wire [170 : 0] f_reqs_rv$D_IN; - wire f_reqs_rv$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_cached_clean - reg rg_cached_clean; - wire rg_cached_clean$D_IN, rg_cached_clean$EN; - - // register rg_cached_raw_mem_addr - reg [63 : 0] rg_cached_raw_mem_addr; - wire [63 : 0] rg_cached_raw_mem_addr$D_IN; - wire rg_cached_raw_mem_addr$EN; - - // register rg_cached_raw_mem_word - reg [255 : 0] rg_cached_raw_mem_word; - wire [255 : 0] rg_cached_raw_mem_word$D_IN; - wire rg_cached_raw_mem_word$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_status - reg [7 : 0] rg_status; - wire [7 : 0] rg_status$D_IN; - wire rg_status$EN; - - // register rg_tohost_addr - reg [63 : 0] rg_tohost_addr; - wire [63 : 0] rg_tohost_addr$D_IN; - wire rg_tohost_addr$EN; - - // register rg_watch_tohost - reg rg_watch_tohost; - wire rg_watch_tohost$D_IN, rg_watch_tohost$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_external_reset, - CAN_FIRE_RL_rl_invalid_rd_address, - CAN_FIRE_RL_rl_invalid_wr_address, - CAN_FIRE_RL_rl_merge_rd_req, - CAN_FIRE_RL_rl_merge_wr_req, - CAN_FIRE_RL_rl_miss_clean_req, - CAN_FIRE_RL_rl_power_on_reset, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reload, - CAN_FIRE_RL_rl_reset_reload_cache, - CAN_FIRE_RL_rl_writeback_dirty, - CAN_FIRE_RL_rl_writeback_dirty_idle, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_external_reset, - WILL_FIRE_RL_rl_invalid_rd_address, - WILL_FIRE_RL_rl_invalid_wr_address, - WILL_FIRE_RL_rl_merge_rd_req, - WILL_FIRE_RL_rl_merge_wr_req, - WILL_FIRE_RL_rl_miss_clean_req, - WILL_FIRE_RL_rl_power_on_reset, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reload, - WILL_FIRE_RL_rl_reset_reload_cache, - WILL_FIRE_RL_rl_writeback_dirty, - WILL_FIRE_RL_rl_writeback_dirty_idle, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire [353 : 0] MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1, - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - wire [255 : 0] MUX_rg_cached_raw_mem_word$write_1__VAL_1; - wire [170 : 0] MUX_f_reqs_rv$port1__write_1__VAL_1, - MUX_f_reqs_rv$port1__write_1__VAL_2; - wire [70 : 0] MUX_slave_xactor_f_rd_data$enq_1__VAL_1, - MUX_slave_xactor_f_rd_data$enq_1__VAL_2; - wire [5 : 0] MUX_slave_xactor_f_wr_resp$enq_1__VAL_1, - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2; - wire MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2538; - reg [31 : 0] v__h3481; - reg [31 : 0] v__h3974; - reg [31 : 0] v__h4443; - reg [31 : 0] v__h4706; - reg [31 : 0] v__h5425; - reg [31 : 0] v__h7622; - reg [31 : 0] v__h7823; - reg [31 : 0] v__h8335; - reg [31 : 0] v__h9119; - reg [31 : 0] v__h9714; - reg [31 : 0] v__h2853; - reg [31 : 0] v__h3193; - reg [31 : 0] v__h1743; - reg [31 : 0] v__h2088; - reg [31 : 0] v__h1737; - reg [31 : 0] v__h2082; - reg [31 : 0] v__h2532; - reg [31 : 0] v__h2847; - reg [31 : 0] v__h3187; - reg [31 : 0] v__h3475; - reg [31 : 0] v__h3968; - reg [31 : 0] v__h4437; - reg [31 : 0] v__h4700; - reg [31 : 0] v__h5419; - reg [31 : 0] v__h7616; - reg [31 : 0] v__h7817; - reg [31 : 0] v__h8329; - reg [31 : 0] v__h9113; - reg [31 : 0] v__h9708; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rdata__h5068, word64_old__h5862; - wire [63 : 0] exit_value__h7860, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1, - mask__h5867, - req_raw_mem_addr__h3314, - updated_word64__h5868, - x__h6241, - y__h6242, - y__h6243; - wire [7 : 0] SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191; - wire [4 : 0] n__h5067; - wire NOT_cfg_verbosity_read_ULE_1___d5, - NOT_cfg_verbosity_read_ULE_2_2___d33, - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279, - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128, - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123, - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126, - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135, - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284, - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131, - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = rg_state == 2'd3 ; - assign CAN_FIRE_set_addr_map = rg_state == 2'd3 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = f_raw_mem_reqs_rv[352:0] ; - assign RDY_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign CAN_FIRE_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = !f_raw_mem_rsps_rv$port1__read[256] ; - assign CAN_FIRE_to_raw_mem_response_put = - !f_raw_mem_rsps_rv$port1__read[256] ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // value method status - assign status = rg_status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset_reload_cache - assign CAN_FIRE_RL_rl_reset_reload_cache = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_reload_cache = - CAN_FIRE_RL_rl_reset_reload_cache ; - - // rule RL_rl_writeback_dirty_idle - assign CAN_FIRE_RL_rl_writeback_dirty_idle = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd3 && - !f_reqs_rv[170] && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty_idle = - CAN_FIRE_RL_rl_writeback_dirty_idle ; - - // rule RL_rl_writeback_dirty - assign CAN_FIRE_RL_rl_writeback_dirty = - !f_raw_mem_reqs_rv$port1__read[353] && f_reqs_rv[170] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty = CAN_FIRE_RL_rl_writeback_dirty ; - - // rule RL_rl_miss_clean_req - assign CAN_FIRE_RL_rl_miss_clean_req = - f_reqs_rv[170] && !f_raw_mem_reqs_rv$port1__read[353] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - rg_cached_clean ; - assign WILL_FIRE_RL_rl_miss_clean_req = - CAN_FIRE_RL_rl_miss_clean_req && - !WILL_FIRE_RL_rl_external_reset && - !EN_set_addr_map ; - - // rule RL_rl_reload - assign CAN_FIRE_RL_rl_reload = f_raw_mem_rsps_rv[256] && rg_state == 2'd2 ; - assign WILL_FIRE_RL_rl_reload = CAN_FIRE_RL_rl_reload ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_invalid_rd_address - assign CAN_FIRE_RL_rl_invalid_rd_address = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_rd_address = - CAN_FIRE_RL_rl_invalid_rd_address ; - - // rule RL_rl_invalid_wr_address - assign CAN_FIRE_RL_rl_invalid_wr_address = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_wr_address = - CAN_FIRE_RL_rl_invalid_wr_address ; - - // rule RL_rl_merge_rd_req - assign CAN_FIRE_RL_rl_merge_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && !f_reqs_rv$port1__read[170] ; - assign WILL_FIRE_RL_rl_merge_rd_req = CAN_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_merge_wr_req - assign CAN_FIRE_RL_rl_merge_wr_req = - !f_reqs_rv$port1__read[170] && slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N ; - assign WILL_FIRE_RL_rl_merge_wr_req = - CAN_FIRE_RL_rl_merge_wr_req && !WILL_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_power_on_reset - assign CAN_FIRE_RL_rl_power_on_reset = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_power_on_reset = CAN_FIRE_RL_rl_power_on_reset ; - - // rule RL_rl_external_reset - assign CAN_FIRE_RL_rl_external_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && rg_state == 2'd3 ; - assign WILL_FIRE_RL_rl_external_reset = CAN_FIRE_RL_rl_external_reset ; - - // inputs to muxes for submodule ports - assign MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - assign MUX_rg_state$write_1__SEL_1 = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - assign MUX_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 = - { 34'h3FFFFFFFF, - rg_cached_raw_mem_addr, - rg_cached_raw_mem_word } ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3 = - { 34'h2FFFFFFFF, - req_raw_mem_addr__h3314, - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_1 = - { 2'd2, slave_xactor_f_rd_addr$D_OUT, 72'hAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_2 = - { 2'd3, - slave_xactor_f_wr_addr$D_OUT, - slave_xactor_f_wr_data$D_OUT[8:1], - slave_xactor_f_wr_data$D_OUT[72:9] } ; - assign MUX_rg_cached_raw_mem_word$write_1__VAL_1 = - { (f_reqs_rv[105:104] == 2'd3) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[255:192], - (f_reqs_rv[105:104] == 2'd2) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[191:128], - (f_reqs_rv[105:104] == 2'd1) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[127:64], - (f_reqs_rv[105:104] == 2'd0) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[63:0] } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_1 = - { f_reqs_rv[168:165], rdata__h5068, 3'd1 } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_2 = - { f_reqs_rv[168:101], 3'd5 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 = - { f_reqs_rv[168:165], 2'd0 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 = - { f_reqs_rv[168:165], 2'd2 } ; - - // inlined wires - assign f_reqs_rv$EN_port0__write = - WILL_FIRE_RL_rl_invalid_wr_address || - WILL_FIRE_RL_rl_invalid_rd_address || - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs_rv$port1__read = - f_reqs_rv$EN_port0__write ? - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_reqs_rv ; - assign f_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_merge_rd_req || WILL_FIRE_RL_rl_merge_wr_req ; - assign f_reqs_rv$port1__write_1 = - WILL_FIRE_RL_rl_merge_rd_req ? - MUX_f_reqs_rv$port1__write_1__VAL_1 : - MUX_f_reqs_rv$port1__write_1__VAL_2 ; - assign f_reqs_rv$port2__read = - f_reqs_rv$EN_port1__write ? - f_reqs_rv$port1__write_1 : - f_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port1__read = - EN_to_raw_mem_request_get ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv ; - assign f_raw_mem_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_miss_clean_req ; - always@(MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 or - WILL_FIRE_RL_rl_reset_reload_cache or - WILL_FIRE_RL_rl_miss_clean_req or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1; - WILL_FIRE_RL_rl_reset_reload_cache: - f_raw_mem_reqs_rv$port1__write_1 = - 354'h2FFFFFFFF0000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_miss_clean_req: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - default: f_raw_mem_reqs_rv$port1__write_1 = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign f_raw_mem_reqs_rv$port2__read = - f_raw_mem_reqs_rv$EN_port1__write ? - f_raw_mem_reqs_rv$port1__write_1 : - f_raw_mem_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv$port2__read ; - assign f_raw_mem_rsps_rv$port1__read = - CAN_FIRE_RL_rl_reload ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv ; - assign f_raw_mem_rsps_rv$port1__write_1 = - { 1'd1, to_raw_mem_response_put } ; - assign f_raw_mem_rsps_rv$port2__read = - EN_to_raw_mem_response_put ? - f_raw_mem_rsps_rv$port1__write_1 : - f_raw_mem_rsps_rv$port1__read ; - assign f_raw_mem_rsps_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv$port2__read ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register f_raw_mem_reqs_rv - assign f_raw_mem_reqs_rv$D_IN = f_raw_mem_reqs_rv$port3__read ; - assign f_raw_mem_reqs_rv$EN = 1'b1 ; - - // register f_raw_mem_rsps_rv - assign f_raw_mem_rsps_rv$D_IN = f_raw_mem_rsps_rv$port3__read ; - assign f_raw_mem_rsps_rv$EN = 1'b1 ; - - // register f_reqs_rv - assign f_reqs_rv$D_IN = f_reqs_rv$port2__read ; - assign f_reqs_rv$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_cached_clean - assign rg_cached_clean$D_IN = !WILL_FIRE_RL_rl_process_wr_req ; - assign rg_cached_clean$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload || - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - - // register rg_cached_raw_mem_addr - assign rg_cached_raw_mem_addr$D_IN = - WILL_FIRE_RL_rl_miss_clean_req ? - req_raw_mem_addr__h3314 : - 64'd0 ; - assign rg_cached_raw_mem_addr$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_cached_raw_mem_word - assign rg_cached_raw_mem_word$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_rg_cached_raw_mem_word$write_1__VAL_1 : - f_raw_mem_rsps_rv[255:0] ; - assign rg_cached_raw_mem_word$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload ; - - // register rg_state - always@(MUX_rg_state$write_1__SEL_1 or - MUX_rg_state$write_1__SEL_2 or WILL_FIRE_RL_rl_reload) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_state$write_1__SEL_1: rg_state$D_IN = 2'd1; - MUX_rg_state$write_1__SEL_2: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reload: rg_state$D_IN = 2'd3; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset || - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_reload ; - - // register rg_status - assign rg_status$D_IN = - (WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset) ? - 8'd0 : - 8'd1 ; - assign rg_status$EN = - WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 || - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - - // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_watch_tohost ; - - // register rg_watch_tohost - assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ; - assign rg_watch_tohost$EN = EN_set_watch_tohost ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_merge_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_slave_xactor_f_rd_data$enq_1__VAL_1 : - MUX_slave_xactor_f_rd_data$enq_1__VAL_2 ; - assign slave_xactor_f_rd_data$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_invalid_rd_address ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 : - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 ; - assign slave_xactor_f_wr_resp$ENQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_invalid_wr_address ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_1 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d5 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read_ULE_2_2___d33 = cfg_verbosity > 4'd2 ; - assign NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 = - f_reqs_rv[92:90] != 3'b0 && - (f_reqs_rv[92:90] != 3'b001 || f_reqs_rv[101]) && - (f_reqs_rv[92:90] != 3'b010 || f_reqs_rv[102:101] != 2'h0) && - (f_reqs_rv[92:90] != 3'b011 || f_reqs_rv[103:101] != 3'h0) && - (f_reqs_rv[92:90] != 3'b100 || f_reqs_rv[104:101] != 4'h0) && - (f_reqs_rv[92:90] != 3'b101 || f_reqs_rv[105:101] != 5'h0) && - (f_reqs_rv[92:90] != 3'b110 || f_reqs_rv[106:101] != 6'h0) && - (f_reqs_rv[92:90] != 3'b111 || f_reqs_rv[107:101] != 7'h0) ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 = {8{f_reqs_rv[64]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212 = {8{f_reqs_rv[65]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208 = {8{f_reqs_rv[66]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205 = {8{f_reqs_rv[67]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201 = {8{f_reqs_rv[68]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198 = {8{f_reqs_rv[69]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194 = {8{f_reqs_rv[70]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191 = {8{f_reqs_rv[71]}} ; - assign exit_value__h7860 = { 1'd0, f_reqs_rv[63:1] } ; - assign f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1 = - f_reqs_rv[164:101] - rg_addr_base ; - assign f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 = - f_reqs_rv[164:101] < rg_addr_lim ; - assign f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 = - f_reqs_rv[92:90] == 3'b0 || - f_reqs_rv[92:90] == 3'b001 && !f_reqs_rv[101] || - f_reqs_rv[92:90] == 3'b010 && f_reqs_rv[102:101] == 2'h0 || - f_reqs_rv[92:90] == 3'b011 && f_reqs_rv[103:101] == 3'h0 || - f_reqs_rv[92:90] == 3'b100 && f_reqs_rv[104:101] == 4'h0 || - f_reqs_rv[92:90] == 3'b101 && f_reqs_rv[105:101] == 5'h0 || - f_reqs_rv[92:90] == 3'b110 && f_reqs_rv[106:101] == 6'h0 || - f_reqs_rv[92:90] == 3'b111 && f_reqs_rv[107:101] == 7'h0 ; - assign mask__h5867 = - { SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - assign n__h5067 = { 3'd0, f_reqs_rv[105:104] } ; - assign req_raw_mem_addr__h3314 = - { 5'd0, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1[63:5] } ; - assign rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 = - rg_addr_base <= f_reqs_rv[164:101] ; - assign rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 = - rg_cached_raw_mem_addr == req_raw_mem_addr__h3314 ; - assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 = - rg_state == 2'd3 && - (NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 || - !rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 || - !f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128) ; - assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 = - rg_state == 2'd3 && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 && - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 && - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 ; - assign rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 = - rg_watch_tohost && f_reqs_rv[164:101] == rg_tohost_addr && - f_reqs_rv[63:0] != 64'd0 ; - assign updated_word64__h5868 = x__h6241 | y__h6242 ; - assign x__h6241 = word64_old__h5862 & y__h6243 ; - assign y__h6242 = f_reqs_rv[63:0] & mask__h5867 ; - assign y__h6243 = - { ~SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - ~SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - ~SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - ~SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - ~SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - ~SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - ~SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - ~SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - always@(f_reqs_rv or rg_cached_raw_mem_word) - begin - case (f_reqs_rv[105:104]) - 2'd0: word64_old__h5862 = rg_cached_raw_mem_word[63:0]; - 2'd1: word64_old__h5862 = rg_cached_raw_mem_word[127:64]; - 2'd2: word64_old__h5862 = rg_cached_raw_mem_word[191:128]; - 2'd3: word64_old__h5862 = rg_cached_raw_mem_word[255:192]; - endcase - end - always@(n__h5067 or rg_cached_raw_mem_word) - begin - case (n__h5067) - 5'd0: rdata__h5068 = rg_cached_raw_mem_word[63:0]; - 5'd1: rdata__h5068 = rg_cached_raw_mem_word[127:64]; - 5'd2: rdata__h5068 = rg_cached_raw_mem_word[191:128]; - 5'd3: rdata__h5068 = rg_cached_raw_mem_word[255:192]; - default: rdata__h5068 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - rg_status <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000; - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (f_raw_mem_reqs_rv$EN) - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_reqs_rv$D_IN; - if (f_raw_mem_rsps_rv$EN) - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_rsps_rv$D_IN; - if (f_reqs_rv$EN) f_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_reqs_rv$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_status$EN) rg_status <= `BSV_ASSIGNMENT_DELAY rg_status$D_IN; - if (rg_tohost_addr$EN) - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; - if (rg_watch_tohost$EN) - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_cached_clean$EN) - rg_cached_clean <= `BSV_ASSIGNMENT_DELAY rg_cached_clean$D_IN; - if (rg_cached_raw_mem_addr$EN) - rg_cached_raw_mem_addr <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_addr$D_IN; - if (rg_cached_raw_mem_word$EN) - rg_cached_raw_mem_word <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_word$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - f_raw_mem_reqs_rv = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv = 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_cached_clean = 1'h0; - rg_cached_raw_mem_addr = 64'hAAAAAAAAAAAAAAAA; - rg_cached_raw_mem_word = - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state = 2'h2; - rg_status = 8'hAA; - rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; - rg_watch_tohost = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2538 = $stime; - #0; - end - v__h2532 = v__h2538 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING", - v__h2532); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3481 = $stime; - #0; - end - v__h3475 = v__h3481 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h", - v__h3475, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3974 = $stime; - #0; - end - v__h3968 = v__h3974 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h", - v__h3968, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4443 = $stime; - #0; - end - v__h4437 = v__h4443 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h", - v__h4437, - req_raw_mem_addr__h3314); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_reload: raw addr 0x%0h", - v__h4700, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", f_raw_mem_rsps_rv[255:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h5425 = $stime; - #0; - end - v__h5419 = v__h5425 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", rdata__h5068); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h7622 = $stime; - #0; - end - v__h7616 = v__h7622 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7616); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - begin - v__h7823 = $stime; - #0; - end - v__h7817 = v__h7823 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - $display("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h () data 0x%0h", - v__h7817, - f_reqs_rv[164:101], - f_reqs_rv[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] == 63'd0) - $display("PASS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] != 63'd0) - $display("FAIL %0d", exit_value__h7860); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - begin - v__h8335 = $stime; - #0; - end - v__h8329 = v__h8335 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("%0d: ERROR: Mem_Controller:", v__h8329); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" read-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" read-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - begin - v__h9119 = $stime; - #0; - end - v__h9113 = v__h9119 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("%0d: ERROR: Mem_Controller:", v__h9113); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" write-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" write-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - begin - v__h9714 = $stime; - #0; - end - v__h9708 = v__h9714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - $display("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9708, - set_addr_map_addr_base, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h2853 = $stime; - #0; - end - v__h2847 = v__h2853 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_rd_req", v__h2847); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3193 = $stime; - #0; - end - v__h3187 = v__h3193 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_wr_req", v__h3187); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h1743 = $stime; - #0; - end - v__h1737 = v__h1743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_power_on_reset", v__h1737); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2088 = $stime; - #0; - end - v__h2082 = v__h2088 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE", - v__h2082); - end - // synopsys translate_on -endmodule // mkMem_Controller - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v deleted file mode 100644 index 104c51b0..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v +++ /dev/null @@ -1,192 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_mem_server_request_put O 1 reg -// mem_server_response_get O 256 reg -// RDY_mem_server_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// mem_server_request_put I 353 -// EN_mem_server_request_put I 1 -// EN_mem_server_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Model(CLK, - RST_N, - - mem_server_request_put, - EN_mem_server_request_put, - RDY_mem_server_request_put, - - EN_mem_server_response_get, - mem_server_response_get, - RDY_mem_server_response_get); - input CLK; - input RST_N; - - // action method mem_server_request_put - input [352 : 0] mem_server_request_put; - input EN_mem_server_request_put; - output RDY_mem_server_request_put; - - // actionvalue method mem_server_response_get - input EN_mem_server_response_get; - output [255 : 0] mem_server_response_get; - output RDY_mem_server_response_get; - - // signals for module outputs - wire [255 : 0] mem_server_response_get; - wire RDY_mem_server_request_put, RDY_mem_server_response_get; - - // ports of submodule f_raw_mem_rsps - wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT; - wire f_raw_mem_rsps$CLR, - f_raw_mem_rsps$DEQ, - f_raw_mem_rsps$EMPTY_N, - f_raw_mem_rsps$ENQ, - f_raw_mem_rsps$FULL_N; - - // ports of submodule rf - wire [255 : 0] rf$D_IN, rf$D_OUT_1; - wire [63 : 0] rf$ADDR_1, - rf$ADDR_2, - rf$ADDR_3, - rf$ADDR_4, - rf$ADDR_5, - rf$ADDR_IN; - wire rf$WE; - - // rule scheduling signals - wire CAN_FIRE_mem_server_request_put, - CAN_FIRE_mem_server_response_get, - WILL_FIRE_mem_server_request_put, - WILL_FIRE_mem_server_response_get; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h371; - reg [31 : 0] v__h365; - // synopsys translate_on - - // remaining internal signals - wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2; - - // action method mem_server_request_put - assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ; - - // actionvalue method mem_server_response_get - assign mem_server_response_get = f_raw_mem_rsps$D_OUT ; - assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ; - - // submodule f_raw_mem_rsps - FIFO2 #(.width(32'd256), .guarded(32'd1)) f_raw_mem_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_raw_mem_rsps$D_IN), - .ENQ(f_raw_mem_rsps$ENQ), - .DEQ(f_raw_mem_rsps$DEQ), - .CLR(f_raw_mem_rsps$CLR), - .D_OUT(f_raw_mem_rsps$D_OUT), - .FULL_N(f_raw_mem_rsps$FULL_N), - .EMPTY_N(f_raw_mem_rsps$EMPTY_N)); - - // submodule rf - RegFileLoad #(.file("Mem.hex"), - .addr_width(32'd64), - .data_width(32'd256), - .lo(64'd0), - .hi(64'd8388607), - .binary(1'd0)) rf(.CLK(CLK), - .ADDR_1(rf$ADDR_1), - .ADDR_2(rf$ADDR_2), - .ADDR_3(rf$ADDR_3), - .ADDR_4(rf$ADDR_4), - .ADDR_5(rf$ADDR_5), - .ADDR_IN(rf$ADDR_IN), - .D_IN(rf$D_IN), - .WE(rf$WE), - .D_OUT_1(rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule f_raw_mem_rsps - assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ; - assign f_raw_mem_rsps$ENQ = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - !mem_server_request_put[352] ; - assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ; - assign f_raw_mem_rsps$CLR = 1'b0 ; - - // submodule rf - assign rf$ADDR_1 = mem_server_request_put[319:256] ; - assign rf$ADDR_2 = 64'h0 ; - assign rf$ADDR_3 = 64'h0 ; - assign rf$ADDR_4 = 64'h0 ; - assign rf$ADDR_5 = 64'h0 ; - assign rf$ADDR_IN = mem_server_request_put[319:256] ; - assign rf$D_IN = mem_server_request_put[255:0] ; - assign rf$WE = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - mem_server_request_put[352] ; - - // remaining internal signals - assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 = - mem_server_request_put[319:256] < 64'h0000000000800000 ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - begin - v__h371 = $stime; - #0; - end - v__h365 = v__h371 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)", - v__h365, - mem_server_request_put[319:256], - 64'h0000000000800000); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkMem_Model - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v deleted file mode 100644 index f7edd910..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v +++ /dev/null @@ -1,1655 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 -// RDY_server_reset_response_get O 1 reg -// imem_valid O 1 -// imem_is_i32_not_i16 O 1 const -// imem_pc O 32 reg -// imem_instr O 32 -// imem_exc O 1 -// imem_exc_code O 4 reg -// imem_tval O 32 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_valid O 1 -// dmem_word64 O 64 -// dmem_st_amo_val O 64 -// dmem_exc O 1 -// dmem_exc_code O 4 reg -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_server_fence_i_request_put O 1 -// RDY_server_fence_i_response_get O 1 -// RDY_server_fence_request_put O 1 reg -// RDY_server_fence_response_get O 1 -// RDY_sfence_vma O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// imem_req_f3 I 3 -// imem_req_addr I 32 -// imem_req_priv I 2 reg -// imem_req_sstatus_SUM I 1 reg -// imem_req_mstatus_MXR I 1 reg -// imem_req_satp I 32 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_req_op I 2 -// dmem_req_f3 I 3 -// dmem_req_amo_funct7 I 7 reg -// dmem_req_addr I 32 -// dmem_req_store_value I 64 -// dmem_req_priv I 2 reg -// dmem_req_sstatus_SUM I 1 reg -// dmem_req_mstatus_MXR I 1 reg -// dmem_req_satp I 32 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// server_fence_request_put I 8 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_imem_req I 1 -// EN_dmem_req I 1 -// EN_server_fence_i_request_put I 1 -// EN_server_fence_i_response_get I 1 -// EN_server_fence_request_put I 1 -// EN_server_fence_response_get I 1 -// EN_sfence_vma I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_valid -// (imem_master_awready, imem_master_wready) -> imem_instr -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// imem_master_arready, -// EN_imem_req) -> imem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_valid -// (dmem_master_awready, dmem_master_wready) -> dmem_word64 -// (dmem_master_awready, dmem_master_wready) -> dmem_st_amo_val -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// (dmem_master_awready, -// dmem_master_wready, -// dmem_master_arready, -// EN_dmem_req) -> dmem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - imem_req_f3, - imem_req_addr, - imem_req_priv, - imem_req_sstatus_SUM, - imem_req_mstatus_MXR, - imem_req_satp, - EN_imem_req, - - imem_valid, - - imem_is_i32_not_i16, - - imem_pc, - - imem_instr, - - imem_exc, - - imem_exc_code, - - imem_tval, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_req_op, - dmem_req_f3, - dmem_req_amo_funct7, - dmem_req_addr, - dmem_req_store_value, - dmem_req_priv, - dmem_req_sstatus_SUM, - dmem_req_mstatus_MXR, - dmem_req_satp, - EN_dmem_req, - - dmem_valid, - - dmem_word64, - - dmem_st_amo_val, - - dmem_exc, - - dmem_exc_code, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - EN_server_fence_i_request_put, - RDY_server_fence_i_request_put, - - EN_server_fence_i_response_get, - RDY_server_fence_i_response_get, - - server_fence_request_put, - EN_server_fence_request_put, - RDY_server_fence_request_put, - - EN_server_fence_response_get, - RDY_server_fence_response_get, - - EN_sfence_vma, - RDY_sfence_vma); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method imem_req - input [2 : 0] imem_req_f3; - input [31 : 0] imem_req_addr; - input [1 : 0] imem_req_priv; - input imem_req_sstatus_SUM; - input imem_req_mstatus_MXR; - input [31 : 0] imem_req_satp; - input EN_imem_req; - - // value method imem_valid - output imem_valid; - - // value method imem_is_i32_not_i16 - output imem_is_i32_not_i16; - - // value method imem_pc - output [31 : 0] imem_pc; - - // value method imem_instr - output [31 : 0] imem_instr; - - // value method imem_exc - output imem_exc; - - // value method imem_exc_code - output [3 : 0] imem_exc_code; - - // value method imem_tval - output [31 : 0] imem_tval; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // action method dmem_req - input [1 : 0] dmem_req_op; - input [2 : 0] dmem_req_f3; - input [6 : 0] dmem_req_amo_funct7; - input [31 : 0] dmem_req_addr; - input [63 : 0] dmem_req_store_value; - input [1 : 0] dmem_req_priv; - input dmem_req_sstatus_SUM; - input dmem_req_mstatus_MXR; - input [31 : 0] dmem_req_satp; - input EN_dmem_req; - - // value method dmem_valid - output dmem_valid; - - // value method dmem_word64 - output [63 : 0] dmem_word64; - - // value method dmem_st_amo_val - output [63 : 0] dmem_st_amo_val; - - // value method dmem_exc - output dmem_exc; - - // value method dmem_exc_code - output [3 : 0] dmem_exc_code; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method server_fence_i_request_put - input EN_server_fence_i_request_put; - output RDY_server_fence_i_request_put; - - // action method server_fence_i_response_get - input EN_server_fence_i_response_get; - output RDY_server_fence_i_response_get; - - // action method server_fence_request_put - input [7 : 0] server_fence_request_put; - input EN_server_fence_request_put; - output RDY_server_fence_request_put; - - // action method server_fence_response_get - input EN_server_fence_response_get; - output RDY_server_fence_response_get; - - // action method sfence_vma - input EN_sfence_vma; - output RDY_sfence_vma; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - dmem_st_amo_val, - dmem_word64, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [31 : 0] imem_instr, imem_pc, imem_tval; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_exc_code, - dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_exc_code, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_server_fence_i_request_put, - RDY_server_fence_i_response_get, - RDY_server_fence_request_put, - RDY_server_fence_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_sfence_vma, - dmem_exc, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - dmem_valid, - imem_exc, - imem_is_i32_not_i16, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid, - imem_valid; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule dcache - wire [63 : 0] dcache$mem_master_araddr, - dcache$mem_master_awaddr, - dcache$mem_master_rdata, - dcache$mem_master_wdata, - dcache$req_st_value, - dcache$st_amo_val, - dcache$word64; - wire [31 : 0] dcache$req_addr, dcache$req_satp; - wire [7 : 0] dcache$mem_master_arlen, - dcache$mem_master_awlen, - dcache$mem_master_wstrb; - wire [6 : 0] dcache$req_amo_funct7; - wire [3 : 0] dcache$exc_code, - dcache$mem_master_arcache, - dcache$mem_master_arid, - dcache$mem_master_arqos, - dcache$mem_master_arregion, - dcache$mem_master_awcache, - dcache$mem_master_awid, - dcache$mem_master_awqos, - dcache$mem_master_awregion, - dcache$mem_master_bid, - dcache$mem_master_rid, - dcache$mem_master_wid, - dcache$set_verbosity_verbosity; - wire [2 : 0] dcache$mem_master_arprot, - dcache$mem_master_arsize, - dcache$mem_master_awprot, - dcache$mem_master_awsize, - dcache$req_f3; - wire [1 : 0] dcache$mem_master_arburst, - dcache$mem_master_awburst, - dcache$mem_master_bresp, - dcache$mem_master_rresp, - dcache$req_op, - dcache$req_priv; - wire dcache$EN_req, - dcache$EN_server_flush_request_put, - dcache$EN_server_flush_response_get, - dcache$EN_server_reset_request_put, - dcache$EN_server_reset_response_get, - dcache$EN_set_verbosity, - dcache$EN_tlb_flush, - dcache$RDY_server_flush_request_put, - dcache$RDY_server_flush_response_get, - dcache$RDY_server_reset_request_put, - dcache$RDY_server_reset_response_get, - dcache$exc, - dcache$mem_master_arlock, - dcache$mem_master_arready, - dcache$mem_master_arvalid, - dcache$mem_master_awlock, - dcache$mem_master_awready, - dcache$mem_master_awvalid, - dcache$mem_master_bready, - dcache$mem_master_bvalid, - dcache$mem_master_rlast, - dcache$mem_master_rready, - dcache$mem_master_rvalid, - dcache$mem_master_wlast, - dcache$mem_master_wready, - dcache$mem_master_wvalid, - dcache$req_mstatus_MXR, - dcache$req_sstatus_SUM, - dcache$valid; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule icache - wire [63 : 0] icache$mem_master_araddr, - icache$mem_master_awaddr, - icache$mem_master_rdata, - icache$mem_master_wdata, - icache$req_st_value, - icache$word64; - wire [31 : 0] icache$addr, icache$req_addr, icache$req_satp; - wire [7 : 0] icache$mem_master_arlen, - icache$mem_master_awlen, - icache$mem_master_wstrb; - wire [6 : 0] icache$req_amo_funct7; - wire [3 : 0] icache$exc_code, - icache$mem_master_arcache, - icache$mem_master_arid, - icache$mem_master_arqos, - icache$mem_master_arregion, - icache$mem_master_awcache, - icache$mem_master_awid, - icache$mem_master_awqos, - icache$mem_master_awregion, - icache$mem_master_bid, - icache$mem_master_rid, - icache$mem_master_wid, - icache$set_verbosity_verbosity; - wire [2 : 0] icache$mem_master_arprot, - icache$mem_master_arsize, - icache$mem_master_awprot, - icache$mem_master_awsize, - icache$req_f3; - wire [1 : 0] icache$mem_master_arburst, - icache$mem_master_awburst, - icache$mem_master_bresp, - icache$mem_master_rresp, - icache$req_op, - icache$req_priv; - wire icache$EN_req, - icache$EN_server_flush_request_put, - icache$EN_server_flush_response_get, - icache$EN_server_reset_request_put, - icache$EN_server_reset_response_get, - icache$EN_set_verbosity, - icache$EN_tlb_flush, - icache$RDY_server_flush_request_put, - icache$RDY_server_flush_response_get, - icache$RDY_server_reset_request_put, - icache$RDY_server_reset_response_get, - icache$exc, - icache$mem_master_arlock, - icache$mem_master_arready, - icache$mem_master_arvalid, - icache$mem_master_awlock, - icache$mem_master_awready, - icache$mem_master_awvalid, - icache$mem_master_bready, - icache$mem_master_bvalid, - icache$mem_master_rlast, - icache$mem_master_rready, - icache$mem_master_rvalid, - icache$mem_master_wlast, - icache$mem_master_wready, - icache$mem_master_wvalid, - icache$req_mstatus_MXR, - icache$req_sstatus_SUM, - icache$valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_dmem_req, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_imem_req, - CAN_FIRE_server_fence_i_request_put, - CAN_FIRE_server_fence_i_response_get, - CAN_FIRE_server_fence_request_put, - CAN_FIRE_server_fence_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_sfence_vma, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_dmem_req, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_imem_req, - WILL_FIRE_server_fence_i_request_put, - WILL_FIRE_server_fence_i_response_get, - WILL_FIRE_server_fence_request_put, - WILL_FIRE_server_fence_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_sfence_vma; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h1675; - reg [31 : 0] v__h1826; - reg [31 : 0] v__h1669; - reg [31 : 0] v__h1820; - // synopsys translate_on - - // remaining internal signals - wire NOT_cfg_verbosity_read_ULE_1___d9; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = rg_state == 2'd2 ; - assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method imem_req - assign CAN_FIRE_imem_req = 1'd1 ; - assign WILL_FIRE_imem_req = EN_imem_req ; - - // value method imem_valid - assign imem_valid = icache$valid ; - - // value method imem_is_i32_not_i16 - assign imem_is_i32_not_i16 = 1'd1 ; - - // value method imem_pc - assign imem_pc = icache$addr ; - - // value method imem_instr - assign imem_instr = icache$word64[31:0] ; - - // value method imem_exc - assign imem_exc = icache$exc ; - - // value method imem_exc_code - assign imem_exc_code = icache$exc_code ; - - // value method imem_tval - assign imem_tval = icache$addr ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = icache$mem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = icache$mem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = icache$mem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = icache$mem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = icache$mem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = icache$mem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = icache$mem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = icache$mem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = icache$mem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = icache$mem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = icache$mem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = icache$mem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = icache$mem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = icache$mem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = icache$mem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = icache$mem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = icache$mem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = icache$mem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = icache$mem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = icache$mem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = icache$mem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = icache$mem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = icache$mem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = icache$mem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = icache$mem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = icache$mem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = icache$mem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = icache$mem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = icache$mem_master_rready ; - - // action method dmem_req - assign CAN_FIRE_dmem_req = 1'd1 ; - assign WILL_FIRE_dmem_req = EN_dmem_req ; - - // value method dmem_valid - assign dmem_valid = dcache$valid ; - - // value method dmem_word64 - assign dmem_word64 = dcache$word64 ; - - // value method dmem_st_amo_val - assign dmem_st_amo_val = dcache$st_amo_val ; - - // value method dmem_exc - assign dmem_exc = dcache$exc ; - - // value method dmem_exc_code - assign dmem_exc_code = dcache$exc_code ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = dcache$mem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = dcache$mem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = dcache$mem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = dcache$mem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = dcache$mem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = dcache$mem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = dcache$mem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = dcache$mem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = dcache$mem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = dcache$mem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = dcache$mem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = dcache$mem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = dcache$mem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = dcache$mem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = dcache$mem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = dcache$mem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = dcache$mem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = dcache$mem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = dcache$mem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = dcache$mem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = dcache$mem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = dcache$mem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = dcache$mem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = dcache$mem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = dcache$mem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = dcache$mem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = dcache$mem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = dcache$mem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = dcache$mem_master_rready ; - - // action method server_fence_i_request_put - assign RDY_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_i_request_put = - EN_server_fence_i_request_put ; - - // action method server_fence_i_response_get - assign RDY_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_i_response_get = - EN_server_fence_i_response_get ; - - // action method server_fence_request_put - assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_request_put = - dcache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ; - - // action method server_fence_response_get - assign RDY_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ; - - // action method sfence_vma - assign RDY_sfence_vma = 1'd1 ; - assign CAN_FIRE_sfence_vma = 1'd1 ; - assign WILL_FIRE_sfence_vma = EN_sfence_vma ; - - // submodule dcache - mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(dcache$mem_master_arready), - .mem_master_awready(dcache$mem_master_awready), - .mem_master_bid(dcache$mem_master_bid), - .mem_master_bresp(dcache$mem_master_bresp), - .mem_master_bvalid(dcache$mem_master_bvalid), - .mem_master_rdata(dcache$mem_master_rdata), - .mem_master_rid(dcache$mem_master_rid), - .mem_master_rlast(dcache$mem_master_rlast), - .mem_master_rresp(dcache$mem_master_rresp), - .mem_master_rvalid(dcache$mem_master_rvalid), - .mem_master_wready(dcache$mem_master_wready), - .req_addr(dcache$req_addr), - .req_amo_funct7(dcache$req_amo_funct7), - .req_f3(dcache$req_f3), - .req_mstatus_MXR(dcache$req_mstatus_MXR), - .req_op(dcache$req_op), - .req_priv(dcache$req_priv), - .req_satp(dcache$req_satp), - .req_sstatus_SUM(dcache$req_sstatus_SUM), - .req_st_value(dcache$req_st_value), - .set_verbosity_verbosity(dcache$set_verbosity_verbosity), - .EN_set_verbosity(dcache$EN_set_verbosity), - .EN_server_reset_request_put(dcache$EN_server_reset_request_put), - .EN_server_reset_response_get(dcache$EN_server_reset_response_get), - .EN_req(dcache$EN_req), - .EN_server_flush_request_put(dcache$EN_server_flush_request_put), - .EN_server_flush_response_get(dcache$EN_server_flush_response_get), - .EN_tlb_flush(dcache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), - .valid(dcache$valid), - .addr(), - .word64(dcache$word64), - .st_amo_val(dcache$st_amo_val), - .exc(dcache$exc), - .exc_code(dcache$exc_code), - .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(dcache$mem_master_awvalid), - .mem_master_awid(dcache$mem_master_awid), - .mem_master_awaddr(dcache$mem_master_awaddr), - .mem_master_awlen(dcache$mem_master_awlen), - .mem_master_awsize(dcache$mem_master_awsize), - .mem_master_awburst(dcache$mem_master_awburst), - .mem_master_awlock(dcache$mem_master_awlock), - .mem_master_awcache(dcache$mem_master_awcache), - .mem_master_awprot(dcache$mem_master_awprot), - .mem_master_awqos(dcache$mem_master_awqos), - .mem_master_awregion(dcache$mem_master_awregion), - .mem_master_wvalid(dcache$mem_master_wvalid), - .mem_master_wid(dcache$mem_master_wid), - .mem_master_wdata(dcache$mem_master_wdata), - .mem_master_wstrb(dcache$mem_master_wstrb), - .mem_master_wlast(dcache$mem_master_wlast), - .mem_master_bready(dcache$mem_master_bready), - .mem_master_arvalid(dcache$mem_master_arvalid), - .mem_master_arid(dcache$mem_master_arid), - .mem_master_araddr(dcache$mem_master_araddr), - .mem_master_arlen(dcache$mem_master_arlen), - .mem_master_arsize(dcache$mem_master_arsize), - .mem_master_arburst(dcache$mem_master_arburst), - .mem_master_arlock(dcache$mem_master_arlock), - .mem_master_arcache(dcache$mem_master_arcache), - .mem_master_arprot(dcache$mem_master_arprot), - .mem_master_arqos(dcache$mem_master_arqos), - .mem_master_arregion(dcache$mem_master_arregion), - .mem_master_rready(dcache$mem_master_rready)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule icache - mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(icache$mem_master_arready), - .mem_master_awready(icache$mem_master_awready), - .mem_master_bid(icache$mem_master_bid), - .mem_master_bresp(icache$mem_master_bresp), - .mem_master_bvalid(icache$mem_master_bvalid), - .mem_master_rdata(icache$mem_master_rdata), - .mem_master_rid(icache$mem_master_rid), - .mem_master_rlast(icache$mem_master_rlast), - .mem_master_rresp(icache$mem_master_rresp), - .mem_master_rvalid(icache$mem_master_rvalid), - .mem_master_wready(icache$mem_master_wready), - .req_addr(icache$req_addr), - .req_amo_funct7(icache$req_amo_funct7), - .req_f3(icache$req_f3), - .req_mstatus_MXR(icache$req_mstatus_MXR), - .req_op(icache$req_op), - .req_priv(icache$req_priv), - .req_satp(icache$req_satp), - .req_sstatus_SUM(icache$req_sstatus_SUM), - .req_st_value(icache$req_st_value), - .set_verbosity_verbosity(icache$set_verbosity_verbosity), - .EN_set_verbosity(icache$EN_set_verbosity), - .EN_server_reset_request_put(icache$EN_server_reset_request_put), - .EN_server_reset_response_get(icache$EN_server_reset_response_get), - .EN_req(icache$EN_req), - .EN_server_flush_request_put(icache$EN_server_flush_request_put), - .EN_server_flush_response_get(icache$EN_server_flush_response_get), - .EN_tlb_flush(icache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), - .valid(icache$valid), - .addr(icache$addr), - .word64(icache$word64), - .st_amo_val(), - .exc(icache$exc), - .exc_code(icache$exc_code), - .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(icache$mem_master_awvalid), - .mem_master_awid(icache$mem_master_awid), - .mem_master_awaddr(icache$mem_master_awaddr), - .mem_master_awlen(icache$mem_master_awlen), - .mem_master_awsize(icache$mem_master_awsize), - .mem_master_awburst(icache$mem_master_awburst), - .mem_master_awlock(icache$mem_master_awlock), - .mem_master_awcache(icache$mem_master_awcache), - .mem_master_awprot(icache$mem_master_awprot), - .mem_master_awqos(icache$mem_master_awqos), - .mem_master_awregion(icache$mem_master_awregion), - .mem_master_wvalid(icache$mem_master_wvalid), - .mem_master_wid(icache$mem_master_wid), - .mem_master_wdata(icache$mem_master_wdata), - .mem_master_wstrb(icache$mem_master_wstrb), - .mem_master_wlast(icache$mem_master_wlast), - .mem_master_bready(icache$mem_master_bready), - .mem_master_arvalid(icache$mem_master_arvalid), - .mem_master_arid(icache$mem_master_arid), - .mem_master_araddr(icache$mem_master_araddr), - .mem_master_arlen(icache$mem_master_arlen), - .mem_master_arsize(icache$mem_master_arsize), - .mem_master_arburst(icache$mem_master_arburst), - .mem_master_arlock(icache$mem_master_arlock), - .mem_master_arcache(icache$mem_master_arcache), - .mem_master_arprot(icache$mem_master_arprot), - .mem_master_arqos(icache$mem_master_arqos), - .mem_master_arregion(icache$mem_master_arregion), - .mem_master_rready(icache$mem_master_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - dcache$RDY_server_reset_request_put && - icache$RDY_server_reset_request_put && - rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && - !EN_server_fence_i_request_put ; - assign MUX_rg_state$write_1__SEL_3 = - dcache$RDY_server_reset_response_get && - icache$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - rg_state == 2'd1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete) - begin - case (1'b1) // synopsys parallel_case - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1; - WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset || - WILL_FIRE_RL_rl_reset_complete ; - - // submodule dcache - assign dcache$mem_master_arready = dmem_master_arready ; - assign dcache$mem_master_awready = dmem_master_awready ; - assign dcache$mem_master_bid = dmem_master_bid ; - assign dcache$mem_master_bresp = dmem_master_bresp ; - assign dcache$mem_master_bvalid = dmem_master_bvalid ; - assign dcache$mem_master_rdata = dmem_master_rdata ; - assign dcache$mem_master_rid = dmem_master_rid ; - assign dcache$mem_master_rlast = dmem_master_rlast ; - assign dcache$mem_master_rresp = dmem_master_rresp ; - assign dcache$mem_master_rvalid = dmem_master_rvalid ; - assign dcache$mem_master_wready = dmem_master_wready ; - assign dcache$req_addr = dmem_req_addr ; - assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ; - assign dcache$req_f3 = dmem_req_f3 ; - assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ; - assign dcache$req_op = dmem_req_op ; - assign dcache$req_priv = dmem_req_priv ; - assign dcache$req_satp = dmem_req_satp ; - assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ; - assign dcache$req_st_value = dmem_req_store_value ; - assign dcache$set_verbosity_verbosity = 4'h0 ; - assign dcache$EN_set_verbosity = 1'b0 ; - assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign dcache$EN_req = EN_dmem_req ; - assign dcache$EN_server_flush_request_put = - EN_server_fence_i_request_put || EN_server_fence_request_put ; - assign dcache$EN_server_flush_response_get = - EN_server_fence_i_response_get || EN_server_fence_response_get ; - assign dcache$EN_tlb_flush = EN_sfence_vma ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule icache - assign icache$mem_master_arready = imem_master_arready ; - assign icache$mem_master_awready = imem_master_awready ; - assign icache$mem_master_bid = imem_master_bid ; - assign icache$mem_master_bresp = imem_master_bresp ; - assign icache$mem_master_bvalid = imem_master_bvalid ; - assign icache$mem_master_rdata = imem_master_rdata ; - assign icache$mem_master_rid = imem_master_rid ; - assign icache$mem_master_rlast = imem_master_rlast ; - assign icache$mem_master_rresp = imem_master_rresp ; - assign icache$mem_master_rvalid = imem_master_rvalid ; - assign icache$mem_master_wready = imem_master_wready ; - assign icache$req_addr = imem_req_addr ; - assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ; - assign icache$req_f3 = imem_req_f3 ; - assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ; - assign icache$req_op = 2'd0 ; - assign icache$req_priv = imem_req_priv ; - assign icache$req_satp = imem_req_satp ; - assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ; - assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign icache$set_verbosity_verbosity = 4'h0 ; - assign icache$EN_set_verbosity = 1'b0 ; - assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign icache$EN_req = EN_imem_req ; - assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ; - assign icache$EN_server_flush_response_get = - EN_server_fence_i_response_get ; - assign icache$EN_tlb_flush = EN_sfence_vma ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1675 = $stime; - #0; - end - v__h1669 = v__h1675 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset", v__h1669); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1826 = $stime; - #0; - end - v__h1820 = v__h1826 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset_complete", v__h1820); - end - // synopsys translate_on -endmodule // mkNear_Mem - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v deleted file mode 100644 index 32e93584..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v +++ /dev/null @@ -1,1308 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// RDY_server_request_put O 1 reg -// server_response_get O 66 reg -// RDY_server_response_get O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// server_request_put I 137 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_server_request_put I 1 -// EN_server_response_get I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - server_request_put, - EN_server_request_put, - RDY_server_request_put, - - EN_server_response_get, - server_response_get, - RDY_server_response_get, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method server_request_put - input [136 : 0] server_request_put; - input EN_server_request_put; - output RDY_server_request_put; - - // actionvalue method server_response_get - input EN_server_response_get; - output [65 : 0] server_response_get; - output RDY_server_response_get; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [65 : 0] server_response_get; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_request_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_server_response_get, - RDY_set_addr_map, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reqs - wire [136 : 0] f_reqs$D_IN, f_reqs$D_OUT; - wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_rsps - wire [65 : 0] f_rsps$D_IN, f_rsps$D_OUT; - wire f_rsps$CLR, f_rsps$DEQ, f_rsps$EMPTY_N, f_rsps$ENQ, f_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_request_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_server_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_request_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_server_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire [65 : 0] MUX_f_rsps$enq_1__VAL_1, MUX_f_rsps$enq_1__VAL_2; - wire [63 : 0] MUX_crg_time$port1__write_1__VAL_1, - MUX_crg_timecmp$port1__write_1__VAL_1; - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8676; - reg [31 : 0] v__h8808; - reg [31 : 0] v__h1471; - reg [31 : 0] v__h1868; - reg [31 : 0] v__h2065; - reg [31 : 0] v__h1714; - reg [31 : 0] v__h2442; - reg [31 : 0] v__h7890; - reg [31 : 0] v__h8258; - reg [31 : 0] v__h8368; - reg [31 : 0] v__h8475; - reg [31 : 0] v__h1465; - reg [31 : 0] v__h1708; - reg [31 : 0] v__h1862; - reg [31 : 0] v__h2059; - reg [31 : 0] v__h2436; - reg [31 : 0] v__h7884; - reg [31 : 0] v__h8252; - reg [31 : 0] v__h8362; - reg [31 : 0] v__h8469; - reg [31 : 0] v__h8670; - reg [31 : 0] v__h8802; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rsp_rdata__h2209; - wire [63 : 0] byte_addr__h1981, - mask__h2865, - mask__h5362, - new_data__h5360, - new_time__h4107, - new_time__h6632, - new_timecmp__h2834, - new_timecmp__h5331, - old_time__h6631, - rdata__h1996, - rdata__h2020, - rdata__h2026, - x__h2876, - x__h4149, - x__h5373, - x__h6674, - y__h2877, - y__h2878, - y__h5374, - y__h5375; - wire [7 : 0] SEXT_f_reqs_first__8_BIT_0_31___d132, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_7_07___d108; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method server_request_put - assign RDY_server_request_put = f_reqs$FULL_N ; - assign CAN_FIRE_server_request_put = f_reqs$FULL_N ; - assign WILL_FIRE_server_request_put = EN_server_request_put ; - - // actionvalue method server_response_get - assign server_response_get = f_rsps$D_OUT ; - assign RDY_server_response_get = f_rsps$EMPTY_N ; - assign CAN_FIRE_server_response_get = f_rsps$EMPTY_N ; - assign WILL_FIRE_server_response_get = EN_server_response_get ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reqs - FIFO2 #(.width(32'd137), .guarded(32'd1)) f_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reqs$D_IN), - .ENQ(f_reqs$ENQ), - .DEQ(f_reqs$DEQ), - .CLR(f_reqs$CLR), - .D_OUT(f_reqs$D_OUT), - .FULL_N(f_reqs$FULL_N), - .EMPTY_N(f_reqs$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_rsps - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_rsps$D_IN), - .ENQ(f_rsps$ENQ), - .DEQ(f_rsps$DEQ), - .CLR(f_rsps$CLR), - .D_OUT(f_rsps$D_OUT), - .FULL_N(f_rsps$FULL_N), - .EMPTY_N(f_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && rg_state && - !f_reset_reqs$EMPTY_N && - f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && - (byte_addr__h1981 != 64'h0 || - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - f_sw_interrupt_req$FULL_N) && - rg_state && - !f_reset_reqs$EMPTY_N && - !f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign MUX_crg_time$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h000000000000BFF8) ? - new_time__h4107 : - new_time__h6632 ; - assign MUX_crg_timecmp$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h0000000000004000) ? - new_timecmp__h2834 : - new_timecmp__h5331 ; - assign MUX_f_rsps$enq_1__VAL_1 = - { 1'd1, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - rsp_rdata__h2209 } ; - assign MUX_f_rsps$enq_1__VAL_2 = - { 1'd0, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - 64'hAAAAAAAAAAAAAAAA } ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? - MUX_crg_time$port1__write_1__VAL_1 : - 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h6631 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - MUX_crg_timecmp$port1__write_1__VAL_1 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = MUX_rg_msip$write_1__SEL_1 && f_reqs$D_OUT[8] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reqs - assign f_reqs$D_IN = server_request_put ; - assign f_reqs$ENQ = EN_server_request_put ; - assign f_reqs$DEQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_rsps - assign f_rsps$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_f_rsps$enq_1__VAL_1 : - MUX_f_rsps$enq_1__VAL_2 ; - assign f_rsps$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_process_wr_req ; - assign f_rsps$DEQ = EN_server_response_get ; - assign f_rsps$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = f_reqs$D_OUT[8] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_f_reqs_first__8_BIT_0_31___d132 = {8{f_reqs$D_OUT[0]}} ; - assign SEXT_f_reqs_first__8_BIT_1_28___d129 = {8{f_reqs$D_OUT[1]}} ; - assign SEXT_f_reqs_first__8_BIT_2_24___d125 = {8{f_reqs$D_OUT[2]}} ; - assign SEXT_f_reqs_first__8_BIT_3_21___d122 = {8{f_reqs$D_OUT[3]}} ; - assign SEXT_f_reqs_first__8_BIT_4_17___d118 = {8{f_reqs$D_OUT[4]}} ; - assign SEXT_f_reqs_first__8_BIT_5_14___d115 = {8{f_reqs$D_OUT[5]}} ; - assign SEXT_f_reqs_first__8_BIT_6_10___d111 = {8{f_reqs$D_OUT[6]}} ; - assign SEXT_f_reqs_first__8_BIT_7_07___d108 = {8{f_reqs$D_OUT[7]}} ; - assign byte_addr__h1981 = f_reqs$D_OUT[135:72] - rg_addr_base ; - assign mask__h2865 = - { SEXT_f_reqs_first__8_BIT_7_07___d108, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign mask__h5362 = - { SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'd0 } ; - assign new_data__h5360 = { f_reqs$D_OUT[39:8], 32'h0 } ; - assign new_time__h4107 = x__h4149 | y__h2877 ; - assign new_time__h6632 = x__h6674 | y__h5374 ; - assign new_timecmp__h2834 = x__h2876 | y__h2877 ; - assign new_timecmp__h5331 = x__h5373 | y__h5374 ; - assign old_time__h6631 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata__h1996 = { 63'd0, rg_msip } ; - assign rdata__h2020 = { 32'd0, crg_timecmp[63:32] } ; - assign rdata__h2026 = { 32'd0, crg_time[63:32] } ; - assign rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 = - rg_msip == f_reqs$D_OUT[8] ; - assign x__h2876 = crg_timecmp & y__h2878 ; - assign x__h4149 = old_time__h6631 & y__h2878 ; - assign x__h5373 = crg_timecmp & y__h5375 ; - assign x__h6674 = old_time__h6631 & y__h5375 ; - assign y__h2877 = f_reqs$D_OUT[71:8] & mask__h2865 ; - assign y__h2878 = - { ~SEXT_f_reqs_first__8_BIT_7_07___d108, - ~SEXT_f_reqs_first__8_BIT_6_10___d111, - ~SEXT_f_reqs_first__8_BIT_5_14___d115, - ~SEXT_f_reqs_first__8_BIT_4_17___d118, - ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign y__h5374 = new_data__h5360 & mask__h5362 ; - assign y__h5375 = - { ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'hFFFFFFFF } ; - always@(byte_addr__h1981 or - rdata__h1996 or - crg_timecmp or rdata__h2020 or crg_time or rdata__h2026) - begin - case (byte_addr__h1981) - 64'h0: rsp_rdata__h2209 = rdata__h1996; - 64'h0000000000000004: rsp_rdata__h2209 = 64'd0; - 64'h0000000000004000: rsp_rdata__h2209 = crg_timecmp; - 64'h0000000000004004: rsp_rdata__h2209 = rdata__h2020; - 64'h000000000000BFF8: rsp_rdata__h2209 = crg_time; - 64'h000000000000BFFC: rsp_rdata__h2209 = rdata__h2026; - default: rsp_rdata__h2209 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8676 = $stime; - #0; - end - v__h8670 = v__h8676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_timer_interrupt_req: %x", - v__h8670, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8808 = $stime; - #0; - end - v__h8802 = v__h8808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_sw_interrupt_req: %x", - v__h8802, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1471 = $stime; - #0; - end - v__h1465 = v__h1471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO.rl_reset", v__h1465); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1868 = $stime; - #0; - end - v__h1862 = v__h1868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_rd_req: rg_mtip = %0d", - v__h1862, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h2065 = $stime; - #0; - end - v__h2059 = v__h2065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_rd_req: unrecognized addr", - v__h2059); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rsp_rdata__h2209, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1714 = $stime; - #0; - end - v__h1708 = v__h1714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h1708, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2442 = $stime; - #0; - end - v__h2436 = v__h2442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_wr_req: rg_mtip = %0d", - v__h2436, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", f_reqs$D_OUT[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h2834); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h2834 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h4107); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h5331); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h5331 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h6632); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h7890 = $stime; - #0; - end - v__h7884 = v__h7890 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_wr_req: unrecognized addr", - v__h7884); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 64'hAAAAAAAAAAAAAAAA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h8258 = $stime; - #0; - end - v__h8252 = v__h8258 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h8252, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h8368 = $stime; - #0; - end - v__h8362 = v__h8368 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h8362, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h8475 = $stime; - #0; - end - v__h8469 = v__h8475 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h8469, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v deleted file mode 100644 index 0883c8da..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v +++ /dev/null @@ -1,2812 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO_AXI4(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h10065; - reg [31 : 0] v__h10197; - reg [31 : 0] v__h1852; - reg [31 : 0] v__h2269; - reg [31 : 0] v__h2453; - reg [31 : 0] v__h2640; - reg [31 : 0] v__h2878; - reg [31 : 0] v__h2095; - reg [31 : 0] v__h3161; - reg [31 : 0] v__h3391; - reg [31 : 0] v__h8927; - reg [31 : 0] v__h9148; - reg [31 : 0] v__h9475; - reg [31 : 0] v__h9585; - reg [31 : 0] v__h9692; - reg [31 : 0] v__h1846; - reg [31 : 0] v__h2089; - reg [31 : 0] v__h2263; - reg [31 : 0] v__h2447; - reg [31 : 0] v__h2634; - reg [31 : 0] v__h2872; - reg [31 : 0] v__h3155; - reg [31 : 0] v__h3385; - reg [31 : 0] v__h8921; - reg [31 : 0] v__h9142; - reg [31 : 0] v__h9469; - reg [31 : 0] v__h9579; - reg [31 : 0] v__h9686; - reg [31 : 0] v__h10059; - reg [31 : 0] v__h10191; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] _theResult___fst__h2566; - reg [1 : 0] _theResult___snd__h2567, v__h3517; - wire [63 : 0] byte_addr__h2405, - byte_addr__h3353, - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190, - mask__h3798, - new_time__h5056, - new_timecmp__h3767, - old_time__h7614, - rdata___1__h2562, - x__h2751, - x__h3809, - x__h5098, - y__h3810, - y__h3811; - wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153; - wire [1 : 0] rresp__h2548, v__h3357; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108, - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53, - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102, - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? new_time__h5056 : 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h7614 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - new_timecmp__h3767 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = - MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - x__h2751, - rresp__h2548, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3357 } ; - assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 = - {8{slave_xactor_f_wr_data$D_OUT[1]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174 = - {8{slave_xactor_f_wr_data$D_OUT[2]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170 = - {8{slave_xactor_f_wr_data$D_OUT[3]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167 = - {8{slave_xactor_f_wr_data$D_OUT[4]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163 = - {8{slave_xactor_f_wr_data$D_OUT[5]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160 = - {8{slave_xactor_f_wr_data$D_OUT[6]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156 = - {8{slave_xactor_f_wr_data$D_OUT[7]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153 = - {8{slave_xactor_f_wr_data$D_OUT[8]}} ; - assign byte_addr__h2405 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign byte_addr__h3353 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190 = - new_timecmp__h3767 - old_time__h7614 ; - assign mask__h3798 = - { SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - assign new_time__h5056 = x__h5098 | y__h3810 ; - assign new_timecmp__h3767 = x__h3809 | y__h3810 ; - assign old_time__h7614 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata___1__h2562 = { 63'd0, rg_msip } ; - assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 = - rg_msip == slave_xactor_f_wr_data$D_OUT[9] ; - assign rresp__h2548 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 2'b11 : - _theResult___snd__h2567 ; - assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 = - slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 = - slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 || - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - f_sw_interrupt_req$FULL_N) ; - assign v__h3357 = - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ? - 2'b11 : - v__h3517 ; - assign x__h2751 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 64'd0 : - _theResult___fst__h2566 ; - assign x__h3809 = crg_timecmp & y__h3811 ; - assign x__h5098 = old_time__h7614 & y__h3811 ; - assign y__h3810 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3798 ; - assign y__h3811 = - { ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - always@(byte_addr__h2405) - begin - case (byte_addr__h2405) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - _theResult___snd__h2567 = 2'b0; - default: _theResult___snd__h2567 = 2'b11; - endcase - end - always@(byte_addr__h2405 or rdata___1__h2562 or crg_timecmp or crg_time) - begin - case (byte_addr__h2405) - 64'h0: _theResult___fst__h2566 = rdata___1__h2562; - 64'h0000000000000004: _theResult___fst__h2566 = 64'd0; - 64'h0000000000004000, 64'h0000000000004004: - _theResult___fst__h2566 = crg_timecmp; - 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___fst__h2566 = crg_time; - default: _theResult___fst__h2566 = 64'd0; - endcase - end - always@(byte_addr__h3353) - begin - case (byte_addr__h3353) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - v__h3517 = 2'b0; - default: v__h3517 = 2'b11; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10065 = $stime; - #0; - end - v__h10059 = v__h10065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x", - v__h10059, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10197 = $stime; - #0; - end - v__h10191 = v__h10197 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x", - v__h10191, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1852 = $stime; - #0; - end - v__h1846 = v__h1852 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1846); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2269 = $stime; - #0; - end - v__h2263 = v__h2269 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", - v__h2263, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - begin - v__h2453 = $stime; - #0; - end - v__h2447 = v__h2453 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2447); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - begin - v__h2640 = $stime; - #0; - end - v__h2634 = v__h2640 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2634); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2878 = $stime; - #0; - end - v__h2872 = v__h2878 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2872); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", x__h2751); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rresp__h2548); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2095 = $stime; - #0; - end - v__h2089 = v__h2095 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h2089, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h3161 = $stime; - #0; - end - v__h3155 = v__h3161 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", - v__h3155, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - begin - v__h3391 = $stime; - #0; - end - v__h3385 = v__h3391 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h3385); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - begin - v__h8927 = $stime; - #0; - end - v__h8921 = v__h8927 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h8921); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h9148 = $stime; - #0; - end - v__h9142 = v__h9148 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9142); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", v__h3357); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h9475 = $stime; - #0; - end - v__h9469 = v__h9475 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9469, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h9585 = $stime; - #0; - end - v__h9579 = v__h9585 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9579, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h9692 = $stime; - #0; - end - v__h9686 = v__h9692 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9686, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO_AXI4 - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v deleted file mode 100644 index f74de61e..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v +++ /dev/null @@ -1,26991 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_show_PLIC_state O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// v_targets_0_m_eip O 1 -// v_targets_1_m_eip O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// v_sources_0_m_interrupt_req_set_not_clear I 1 -// v_sources_1_m_interrupt_req_set_not_clear I 1 -// v_sources_2_m_interrupt_req_set_not_clear I 1 -// v_sources_3_m_interrupt_req_set_not_clear I 1 -// v_sources_4_m_interrupt_req_set_not_clear I 1 -// v_sources_5_m_interrupt_req_set_not_clear I 1 -// v_sources_6_m_interrupt_req_set_not_clear I 1 -// v_sources_7_m_interrupt_req_set_not_clear I 1 -// v_sources_8_m_interrupt_req_set_not_clear I 1 -// v_sources_9_m_interrupt_req_set_not_clear I 1 -// v_sources_10_m_interrupt_req_set_not_clear I 1 -// v_sources_11_m_interrupt_req_set_not_clear I 1 -// v_sources_12_m_interrupt_req_set_not_clear I 1 -// v_sources_13_m_interrupt_req_set_not_clear I 1 -// v_sources_14_m_interrupt_req_set_not_clear I 1 -// v_sources_15_m_interrupt_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_show_PLIC_state I 1 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkPLIC_16_2_7(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_show_PLIC_state, - RDY_show_PLIC_state, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - v_sources_0_m_interrupt_req_set_not_clear, - - v_sources_1_m_interrupt_req_set_not_clear, - - v_sources_2_m_interrupt_req_set_not_clear, - - v_sources_3_m_interrupt_req_set_not_clear, - - v_sources_4_m_interrupt_req_set_not_clear, - - v_sources_5_m_interrupt_req_set_not_clear, - - v_sources_6_m_interrupt_req_set_not_clear, - - v_sources_7_m_interrupt_req_set_not_clear, - - v_sources_8_m_interrupt_req_set_not_clear, - - v_sources_9_m_interrupt_req_set_not_clear, - - v_sources_10_m_interrupt_req_set_not_clear, - - v_sources_11_m_interrupt_req_set_not_clear, - - v_sources_12_m_interrupt_req_set_not_clear, - - v_sources_13_m_interrupt_req_set_not_clear, - - v_sources_14_m_interrupt_req_set_not_clear, - - v_sources_15_m_interrupt_req_set_not_clear, - - v_targets_0_m_eip, - - v_targets_1_m_eip); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method show_PLIC_state - input EN_show_PLIC_state; - output RDY_show_PLIC_state; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // action method v_sources_0_m_interrupt_req - input v_sources_0_m_interrupt_req_set_not_clear; - - // action method v_sources_1_m_interrupt_req - input v_sources_1_m_interrupt_req_set_not_clear; - - // action method v_sources_2_m_interrupt_req - input v_sources_2_m_interrupt_req_set_not_clear; - - // action method v_sources_3_m_interrupt_req - input v_sources_3_m_interrupt_req_set_not_clear; - - // action method v_sources_4_m_interrupt_req - input v_sources_4_m_interrupt_req_set_not_clear; - - // action method v_sources_5_m_interrupt_req - input v_sources_5_m_interrupt_req_set_not_clear; - - // action method v_sources_6_m_interrupt_req - input v_sources_6_m_interrupt_req_set_not_clear; - - // action method v_sources_7_m_interrupt_req - input v_sources_7_m_interrupt_req_set_not_clear; - - // action method v_sources_8_m_interrupt_req - input v_sources_8_m_interrupt_req_set_not_clear; - - // action method v_sources_9_m_interrupt_req - input v_sources_9_m_interrupt_req_set_not_clear; - - // action method v_sources_10_m_interrupt_req - input v_sources_10_m_interrupt_req_set_not_clear; - - // action method v_sources_11_m_interrupt_req - input v_sources_11_m_interrupt_req_set_not_clear; - - // action method v_sources_12_m_interrupt_req - input v_sources_12_m_interrupt_req_set_not_clear; - - // action method v_sources_13_m_interrupt_req - input v_sources_13_m_interrupt_req_set_not_clear; - - // action method v_sources_14_m_interrupt_req - input v_sources_14_m_interrupt_req_set_not_clear; - - // action method v_sources_15_m_interrupt_req - input v_sources_15_m_interrupt_req_set_not_clear; - - // value method v_targets_0_m_eip - output v_targets_0_m_eip; - - // value method v_targets_1_m_eip - output v_targets_1_m_eip; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_verbosity, - RDY_show_PLIC_state, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - v_targets_0_m_eip, - v_targets_1_m_eip; - - // register m_cfg_verbosity - reg [3 : 0] m_cfg_verbosity; - wire [3 : 0] m_cfg_verbosity$D_IN; - wire m_cfg_verbosity$EN; - - // register m_rg_addr_base - reg [63 : 0] m_rg_addr_base; - wire [63 : 0] m_rg_addr_base$D_IN; - wire m_rg_addr_base$EN; - - // register m_rg_addr_lim - reg [63 : 0] m_rg_addr_lim; - wire [63 : 0] m_rg_addr_lim$D_IN; - wire m_rg_addr_lim$EN; - - // register m_vrg_servicing_source_0 - reg [4 : 0] m_vrg_servicing_source_0; - wire [4 : 0] m_vrg_servicing_source_0$D_IN; - wire m_vrg_servicing_source_0$EN; - - // register m_vrg_servicing_source_1 - reg [4 : 0] m_vrg_servicing_source_1; - wire [4 : 0] m_vrg_servicing_source_1$D_IN; - wire m_vrg_servicing_source_1$EN; - - // register m_vrg_source_busy_0 - reg m_vrg_source_busy_0; - wire m_vrg_source_busy_0$D_IN, m_vrg_source_busy_0$EN; - - // register m_vrg_source_busy_1 - reg m_vrg_source_busy_1; - wire m_vrg_source_busy_1$D_IN, m_vrg_source_busy_1$EN; - - // register m_vrg_source_busy_10 - reg m_vrg_source_busy_10; - wire m_vrg_source_busy_10$D_IN, m_vrg_source_busy_10$EN; - - // register m_vrg_source_busy_11 - reg m_vrg_source_busy_11; - wire m_vrg_source_busy_11$D_IN, m_vrg_source_busy_11$EN; - - // register m_vrg_source_busy_12 - reg m_vrg_source_busy_12; - wire m_vrg_source_busy_12$D_IN, m_vrg_source_busy_12$EN; - - // register m_vrg_source_busy_13 - reg m_vrg_source_busy_13; - wire m_vrg_source_busy_13$D_IN, m_vrg_source_busy_13$EN; - - // register m_vrg_source_busy_14 - reg m_vrg_source_busy_14; - wire m_vrg_source_busy_14$D_IN, m_vrg_source_busy_14$EN; - - // register m_vrg_source_busy_15 - reg m_vrg_source_busy_15; - wire m_vrg_source_busy_15$D_IN, m_vrg_source_busy_15$EN; - - // register m_vrg_source_busy_16 - reg m_vrg_source_busy_16; - wire m_vrg_source_busy_16$D_IN, m_vrg_source_busy_16$EN; - - // register m_vrg_source_busy_2 - reg m_vrg_source_busy_2; - wire m_vrg_source_busy_2$D_IN, m_vrg_source_busy_2$EN; - - // register m_vrg_source_busy_3 - reg m_vrg_source_busy_3; - wire m_vrg_source_busy_3$D_IN, m_vrg_source_busy_3$EN; - - // register m_vrg_source_busy_4 - reg m_vrg_source_busy_4; - wire m_vrg_source_busy_4$D_IN, m_vrg_source_busy_4$EN; - - // register m_vrg_source_busy_5 - reg m_vrg_source_busy_5; - wire m_vrg_source_busy_5$D_IN, m_vrg_source_busy_5$EN; - - // register m_vrg_source_busy_6 - reg m_vrg_source_busy_6; - wire m_vrg_source_busy_6$D_IN, m_vrg_source_busy_6$EN; - - // register m_vrg_source_busy_7 - reg m_vrg_source_busy_7; - wire m_vrg_source_busy_7$D_IN, m_vrg_source_busy_7$EN; - - // register m_vrg_source_busy_8 - reg m_vrg_source_busy_8; - wire m_vrg_source_busy_8$D_IN, m_vrg_source_busy_8$EN; - - // register m_vrg_source_busy_9 - reg m_vrg_source_busy_9; - wire m_vrg_source_busy_9$D_IN, m_vrg_source_busy_9$EN; - - // register m_vrg_source_ip_0 - reg m_vrg_source_ip_0; - wire m_vrg_source_ip_0$D_IN, m_vrg_source_ip_0$EN; - - // register m_vrg_source_ip_1 - reg m_vrg_source_ip_1; - wire m_vrg_source_ip_1$D_IN, m_vrg_source_ip_1$EN; - - // register m_vrg_source_ip_10 - reg m_vrg_source_ip_10; - wire m_vrg_source_ip_10$D_IN, m_vrg_source_ip_10$EN; - - // register m_vrg_source_ip_11 - reg m_vrg_source_ip_11; - wire m_vrg_source_ip_11$D_IN, m_vrg_source_ip_11$EN; - - // register m_vrg_source_ip_12 - reg m_vrg_source_ip_12; - wire m_vrg_source_ip_12$D_IN, m_vrg_source_ip_12$EN; - - // register m_vrg_source_ip_13 - reg m_vrg_source_ip_13; - wire m_vrg_source_ip_13$D_IN, m_vrg_source_ip_13$EN; - - // register m_vrg_source_ip_14 - reg m_vrg_source_ip_14; - wire m_vrg_source_ip_14$D_IN, m_vrg_source_ip_14$EN; - - // register m_vrg_source_ip_15 - reg m_vrg_source_ip_15; - wire m_vrg_source_ip_15$D_IN, m_vrg_source_ip_15$EN; - - // register m_vrg_source_ip_16 - reg m_vrg_source_ip_16; - wire m_vrg_source_ip_16$D_IN, m_vrg_source_ip_16$EN; - - // register m_vrg_source_ip_2 - reg m_vrg_source_ip_2; - wire m_vrg_source_ip_2$D_IN, m_vrg_source_ip_2$EN; - - // register m_vrg_source_ip_3 - reg m_vrg_source_ip_3; - wire m_vrg_source_ip_3$D_IN, m_vrg_source_ip_3$EN; - - // register m_vrg_source_ip_4 - reg m_vrg_source_ip_4; - wire m_vrg_source_ip_4$D_IN, m_vrg_source_ip_4$EN; - - // register m_vrg_source_ip_5 - reg m_vrg_source_ip_5; - wire m_vrg_source_ip_5$D_IN, m_vrg_source_ip_5$EN; - - // register m_vrg_source_ip_6 - reg m_vrg_source_ip_6; - wire m_vrg_source_ip_6$D_IN, m_vrg_source_ip_6$EN; - - // register m_vrg_source_ip_7 - reg m_vrg_source_ip_7; - wire m_vrg_source_ip_7$D_IN, m_vrg_source_ip_7$EN; - - // register m_vrg_source_ip_8 - reg m_vrg_source_ip_8; - wire m_vrg_source_ip_8$D_IN, m_vrg_source_ip_8$EN; - - // register m_vrg_source_ip_9 - reg m_vrg_source_ip_9; - wire m_vrg_source_ip_9$D_IN, m_vrg_source_ip_9$EN; - - // register m_vrg_source_prio_0 - reg [2 : 0] m_vrg_source_prio_0; - wire [2 : 0] m_vrg_source_prio_0$D_IN; - wire m_vrg_source_prio_0$EN; - - // register m_vrg_source_prio_1 - reg [2 : 0] m_vrg_source_prio_1; - wire [2 : 0] m_vrg_source_prio_1$D_IN; - wire m_vrg_source_prio_1$EN; - - // register m_vrg_source_prio_10 - reg [2 : 0] m_vrg_source_prio_10; - wire [2 : 0] m_vrg_source_prio_10$D_IN; - wire m_vrg_source_prio_10$EN; - - // register m_vrg_source_prio_11 - reg [2 : 0] m_vrg_source_prio_11; - wire [2 : 0] m_vrg_source_prio_11$D_IN; - wire m_vrg_source_prio_11$EN; - - // register m_vrg_source_prio_12 - reg [2 : 0] m_vrg_source_prio_12; - wire [2 : 0] m_vrg_source_prio_12$D_IN; - wire m_vrg_source_prio_12$EN; - - // register m_vrg_source_prio_13 - reg [2 : 0] m_vrg_source_prio_13; - wire [2 : 0] m_vrg_source_prio_13$D_IN; - wire m_vrg_source_prio_13$EN; - - // register m_vrg_source_prio_14 - reg [2 : 0] m_vrg_source_prio_14; - wire [2 : 0] m_vrg_source_prio_14$D_IN; - wire m_vrg_source_prio_14$EN; - - // register m_vrg_source_prio_15 - reg [2 : 0] m_vrg_source_prio_15; - wire [2 : 0] m_vrg_source_prio_15$D_IN; - wire m_vrg_source_prio_15$EN; - - // register m_vrg_source_prio_16 - reg [2 : 0] m_vrg_source_prio_16; - wire [2 : 0] m_vrg_source_prio_16$D_IN; - wire m_vrg_source_prio_16$EN; - - // register m_vrg_source_prio_2 - reg [2 : 0] m_vrg_source_prio_2; - wire [2 : 0] m_vrg_source_prio_2$D_IN; - wire m_vrg_source_prio_2$EN; - - // register m_vrg_source_prio_3 - reg [2 : 0] m_vrg_source_prio_3; - wire [2 : 0] m_vrg_source_prio_3$D_IN; - wire m_vrg_source_prio_3$EN; - - // register m_vrg_source_prio_4 - reg [2 : 0] m_vrg_source_prio_4; - wire [2 : 0] m_vrg_source_prio_4$D_IN; - wire m_vrg_source_prio_4$EN; - - // register m_vrg_source_prio_5 - reg [2 : 0] m_vrg_source_prio_5; - wire [2 : 0] m_vrg_source_prio_5$D_IN; - wire m_vrg_source_prio_5$EN; - - // register m_vrg_source_prio_6 - reg [2 : 0] m_vrg_source_prio_6; - wire [2 : 0] m_vrg_source_prio_6$D_IN; - wire m_vrg_source_prio_6$EN; - - // register m_vrg_source_prio_7 - reg [2 : 0] m_vrg_source_prio_7; - wire [2 : 0] m_vrg_source_prio_7$D_IN; - wire m_vrg_source_prio_7$EN; - - // register m_vrg_source_prio_8 - reg [2 : 0] m_vrg_source_prio_8; - wire [2 : 0] m_vrg_source_prio_8$D_IN; - wire m_vrg_source_prio_8$EN; - - // register m_vrg_source_prio_9 - reg [2 : 0] m_vrg_source_prio_9; - wire [2 : 0] m_vrg_source_prio_9$D_IN; - wire m_vrg_source_prio_9$EN; - - // register m_vrg_target_threshold_0 - reg [2 : 0] m_vrg_target_threshold_0; - wire [2 : 0] m_vrg_target_threshold_0$D_IN; - wire m_vrg_target_threshold_0$EN; - - // register m_vrg_target_threshold_1 - reg [2 : 0] m_vrg_target_threshold_1; - wire [2 : 0] m_vrg_target_threshold_1$D_IN; - wire m_vrg_target_threshold_1$EN; - - // register m_vvrg_ie_0_0 - reg m_vvrg_ie_0_0; - wire m_vvrg_ie_0_0$D_IN, m_vvrg_ie_0_0$EN; - - // register m_vvrg_ie_0_1 - reg m_vvrg_ie_0_1; - wire m_vvrg_ie_0_1$D_IN, m_vvrg_ie_0_1$EN; - - // register m_vvrg_ie_0_10 - reg m_vvrg_ie_0_10; - wire m_vvrg_ie_0_10$D_IN, m_vvrg_ie_0_10$EN; - - // register m_vvrg_ie_0_11 - reg m_vvrg_ie_0_11; - wire m_vvrg_ie_0_11$D_IN, m_vvrg_ie_0_11$EN; - - // register m_vvrg_ie_0_12 - reg m_vvrg_ie_0_12; - wire m_vvrg_ie_0_12$D_IN, m_vvrg_ie_0_12$EN; - - // register m_vvrg_ie_0_13 - reg m_vvrg_ie_0_13; - wire m_vvrg_ie_0_13$D_IN, m_vvrg_ie_0_13$EN; - - // register m_vvrg_ie_0_14 - reg m_vvrg_ie_0_14; - wire m_vvrg_ie_0_14$D_IN, m_vvrg_ie_0_14$EN; - - // register m_vvrg_ie_0_15 - reg m_vvrg_ie_0_15; - wire m_vvrg_ie_0_15$D_IN, m_vvrg_ie_0_15$EN; - - // register m_vvrg_ie_0_16 - reg m_vvrg_ie_0_16; - wire m_vvrg_ie_0_16$D_IN, m_vvrg_ie_0_16$EN; - - // register m_vvrg_ie_0_2 - reg m_vvrg_ie_0_2; - wire m_vvrg_ie_0_2$D_IN, m_vvrg_ie_0_2$EN; - - // register m_vvrg_ie_0_3 - reg m_vvrg_ie_0_3; - wire m_vvrg_ie_0_3$D_IN, m_vvrg_ie_0_3$EN; - - // register m_vvrg_ie_0_4 - reg m_vvrg_ie_0_4; - wire m_vvrg_ie_0_4$D_IN, m_vvrg_ie_0_4$EN; - - // register m_vvrg_ie_0_5 - reg m_vvrg_ie_0_5; - wire m_vvrg_ie_0_5$D_IN, m_vvrg_ie_0_5$EN; - - // register m_vvrg_ie_0_6 - reg m_vvrg_ie_0_6; - wire m_vvrg_ie_0_6$D_IN, m_vvrg_ie_0_6$EN; - - // register m_vvrg_ie_0_7 - reg m_vvrg_ie_0_7; - wire m_vvrg_ie_0_7$D_IN, m_vvrg_ie_0_7$EN; - - // register m_vvrg_ie_0_8 - reg m_vvrg_ie_0_8; - wire m_vvrg_ie_0_8$D_IN, m_vvrg_ie_0_8$EN; - - // register m_vvrg_ie_0_9 - reg m_vvrg_ie_0_9; - wire m_vvrg_ie_0_9$D_IN, m_vvrg_ie_0_9$EN; - - // register m_vvrg_ie_1_0 - reg m_vvrg_ie_1_0; - wire m_vvrg_ie_1_0$D_IN, m_vvrg_ie_1_0$EN; - - // register m_vvrg_ie_1_1 - reg m_vvrg_ie_1_1; - wire m_vvrg_ie_1_1$D_IN, m_vvrg_ie_1_1$EN; - - // register m_vvrg_ie_1_10 - reg m_vvrg_ie_1_10; - wire m_vvrg_ie_1_10$D_IN, m_vvrg_ie_1_10$EN; - - // register m_vvrg_ie_1_11 - reg m_vvrg_ie_1_11; - wire m_vvrg_ie_1_11$D_IN, m_vvrg_ie_1_11$EN; - - // register m_vvrg_ie_1_12 - reg m_vvrg_ie_1_12; - wire m_vvrg_ie_1_12$D_IN, m_vvrg_ie_1_12$EN; - - // register m_vvrg_ie_1_13 - reg m_vvrg_ie_1_13; - wire m_vvrg_ie_1_13$D_IN, m_vvrg_ie_1_13$EN; - - // register m_vvrg_ie_1_14 - reg m_vvrg_ie_1_14; - wire m_vvrg_ie_1_14$D_IN, m_vvrg_ie_1_14$EN; - - // register m_vvrg_ie_1_15 - reg m_vvrg_ie_1_15; - wire m_vvrg_ie_1_15$D_IN, m_vvrg_ie_1_15$EN; - - // register m_vvrg_ie_1_16 - reg m_vvrg_ie_1_16; - wire m_vvrg_ie_1_16$D_IN, m_vvrg_ie_1_16$EN; - - // register m_vvrg_ie_1_2 - reg m_vvrg_ie_1_2; - wire m_vvrg_ie_1_2$D_IN, m_vvrg_ie_1_2$EN; - - // register m_vvrg_ie_1_3 - reg m_vvrg_ie_1_3; - wire m_vvrg_ie_1_3$D_IN, m_vvrg_ie_1_3$EN; - - // register m_vvrg_ie_1_4 - reg m_vvrg_ie_1_4; - wire m_vvrg_ie_1_4$D_IN, m_vvrg_ie_1_4$EN; - - // register m_vvrg_ie_1_5 - reg m_vvrg_ie_1_5; - wire m_vvrg_ie_1_5$D_IN, m_vvrg_ie_1_5$EN; - - // register m_vvrg_ie_1_6 - reg m_vvrg_ie_1_6; - wire m_vvrg_ie_1_6$D_IN, m_vvrg_ie_1_6$EN; - - // register m_vvrg_ie_1_7 - reg m_vvrg_ie_1_7; - wire m_vvrg_ie_1_7$D_IN, m_vvrg_ie_1_7$EN; - - // register m_vvrg_ie_1_8 - reg m_vvrg_ie_1_8; - wire m_vvrg_ie_1_8$D_IN, m_vvrg_ie_1_8$EN; - - // register m_vvrg_ie_1_9 - reg m_vvrg_ie_1_9; - wire m_vvrg_ie_1_9$D_IN, m_vvrg_ie_1_9$EN; - - // ports of submodule m_f_reset_reqs - wire m_f_reset_reqs$CLR, - m_f_reset_reqs$DEQ, - m_f_reset_reqs$EMPTY_N, - m_f_reset_reqs$ENQ, - m_f_reset_reqs$FULL_N; - - // ports of submodule m_f_reset_rsps - wire m_f_reset_rsps$CLR, - m_f_reset_rsps$DEQ, - m_f_reset_rsps$EMPTY_N, - m_f_reset_rsps$ENQ, - m_f_reset_rsps$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_addr - wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT; - wire m_slave_xactor_f_rd_addr$CLR, - m_slave_xactor_f_rd_addr$DEQ, - m_slave_xactor_f_rd_addr$EMPTY_N, - m_slave_xactor_f_rd_addr$ENQ, - m_slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_data - wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT; - wire m_slave_xactor_f_rd_data$CLR, - m_slave_xactor_f_rd_data$DEQ, - m_slave_xactor_f_rd_data$EMPTY_N, - m_slave_xactor_f_rd_data$ENQ, - m_slave_xactor_f_rd_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_addr - wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT; - wire m_slave_xactor_f_wr_addr$CLR, - m_slave_xactor_f_wr_addr$DEQ, - m_slave_xactor_f_wr_addr$EMPTY_N, - m_slave_xactor_f_wr_addr$ENQ, - m_slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; - wire m_slave_xactor_f_wr_data$CLR, - m_slave_xactor_f_wr_data$DEQ, - m_slave_xactor_f_wr_data$EMPTY_N, - m_slave_xactor_f_wr_data$ENQ, - m_slave_xactor_f_wr_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_resp - wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT; - wire m_slave_xactor_f_wr_resp$CLR, - m_slave_xactor_f_wr_resp$DEQ, - m_slave_xactor_f_wr_resp$EMPTY_N, - m_slave_xactor_f_wr_resp$ENQ, - m_slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_process_rd_req, - CAN_FIRE_RL_m_rl_process_wr_req, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_verbosity, - CAN_FIRE_show_PLIC_state, - CAN_FIRE_v_sources_0_m_interrupt_req, - CAN_FIRE_v_sources_10_m_interrupt_req, - CAN_FIRE_v_sources_11_m_interrupt_req, - CAN_FIRE_v_sources_12_m_interrupt_req, - CAN_FIRE_v_sources_13_m_interrupt_req, - CAN_FIRE_v_sources_14_m_interrupt_req, - CAN_FIRE_v_sources_15_m_interrupt_req, - CAN_FIRE_v_sources_1_m_interrupt_req, - CAN_FIRE_v_sources_2_m_interrupt_req, - CAN_FIRE_v_sources_3_m_interrupt_req, - CAN_FIRE_v_sources_4_m_interrupt_req, - CAN_FIRE_v_sources_5_m_interrupt_req, - CAN_FIRE_v_sources_6_m_interrupt_req, - CAN_FIRE_v_sources_7_m_interrupt_req, - CAN_FIRE_v_sources_8_m_interrupt_req, - CAN_FIRE_v_sources_9_m_interrupt_req, - WILL_FIRE_RL_m_rl_process_rd_req, - WILL_FIRE_RL_m_rl_process_wr_req, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_verbosity, - WILL_FIRE_show_PLIC_state, - WILL_FIRE_v_sources_0_m_interrupt_req, - WILL_FIRE_v_sources_10_m_interrupt_req, - WILL_FIRE_v_sources_11_m_interrupt_req, - WILL_FIRE_v_sources_12_m_interrupt_req, - WILL_FIRE_v_sources_13_m_interrupt_req, - WILL_FIRE_v_sources_14_m_interrupt_req, - WILL_FIRE_v_sources_15_m_interrupt_req, - WILL_FIRE_v_sources_1_m_interrupt_req, - WILL_FIRE_v_sources_2_m_interrupt_req, - WILL_FIRE_v_sources_3_m_interrupt_req, - WILL_FIRE_v_sources_4_m_interrupt_req, - WILL_FIRE_v_sources_5_m_interrupt_req, - WILL_FIRE_v_sources_6_m_interrupt_req, - WILL_FIRE_v_sources_7_m_interrupt_req, - WILL_FIRE_v_sources_8_m_interrupt_req, - WILL_FIRE_v_sources_9_m_interrupt_req; - - // inputs to muxes for submodule ports - wire MUX_m_vrg_servicing_source_0$write_1__SEL_1, - MUX_m_vrg_servicing_source_1$write_1__SEL_1, - MUX_m_vrg_source_busy_0$write_1__SEL_2, - MUX_m_vrg_source_busy_1$write_1__SEL_1, - MUX_m_vrg_source_busy_1$write_1__SEL_2, - MUX_m_vrg_source_busy_10$write_1__SEL_1, - MUX_m_vrg_source_busy_10$write_1__SEL_2, - MUX_m_vrg_source_busy_11$write_1__SEL_1, - MUX_m_vrg_source_busy_11$write_1__SEL_2, - MUX_m_vrg_source_busy_12$write_1__SEL_1, - MUX_m_vrg_source_busy_12$write_1__SEL_2, - MUX_m_vrg_source_busy_13$write_1__SEL_1, - MUX_m_vrg_source_busy_13$write_1__SEL_2, - MUX_m_vrg_source_busy_14$write_1__SEL_1, - MUX_m_vrg_source_busy_14$write_1__SEL_2, - MUX_m_vrg_source_busy_15$write_1__SEL_1, - MUX_m_vrg_source_busy_15$write_1__SEL_2, - MUX_m_vrg_source_busy_16$write_1__SEL_1, - MUX_m_vrg_source_busy_16$write_1__SEL_2, - MUX_m_vrg_source_busy_2$write_1__SEL_1, - MUX_m_vrg_source_busy_2$write_1__SEL_2, - MUX_m_vrg_source_busy_3$write_1__SEL_1, - MUX_m_vrg_source_busy_3$write_1__SEL_2, - MUX_m_vrg_source_busy_4$write_1__SEL_1, - MUX_m_vrg_source_busy_4$write_1__SEL_2, - MUX_m_vrg_source_busy_5$write_1__SEL_1, - MUX_m_vrg_source_busy_5$write_1__SEL_2, - MUX_m_vrg_source_busy_6$write_1__SEL_1, - MUX_m_vrg_source_busy_6$write_1__SEL_2, - MUX_m_vrg_source_busy_7$write_1__SEL_1, - MUX_m_vrg_source_busy_7$write_1__SEL_2, - MUX_m_vrg_source_busy_8$write_1__SEL_1, - MUX_m_vrg_source_busy_8$write_1__SEL_2, - MUX_m_vrg_source_busy_9$write_1__SEL_1, - MUX_m_vrg_source_busy_9$write_1__SEL_2, - MUX_m_vrg_source_prio_0$write_1__SEL_1, - MUX_m_vrg_source_prio_1$write_1__SEL_1, - MUX_m_vrg_source_prio_10$write_1__SEL_1, - MUX_m_vrg_source_prio_11$write_1__SEL_1, - MUX_m_vrg_source_prio_12$write_1__SEL_1, - MUX_m_vrg_source_prio_13$write_1__SEL_1, - MUX_m_vrg_source_prio_14$write_1__SEL_1, - MUX_m_vrg_source_prio_15$write_1__SEL_1, - MUX_m_vrg_source_prio_16$write_1__SEL_1, - MUX_m_vrg_source_prio_2$write_1__SEL_1, - MUX_m_vrg_source_prio_3$write_1__SEL_1, - MUX_m_vrg_source_prio_4$write_1__SEL_1, - MUX_m_vrg_source_prio_5$write_1__SEL_1, - MUX_m_vrg_source_prio_6$write_1__SEL_1, - MUX_m_vrg_source_prio_7$write_1__SEL_1, - MUX_m_vrg_source_prio_8$write_1__SEL_1, - MUX_m_vrg_source_prio_9$write_1__SEL_1, - MUX_m_vrg_target_threshold_0$write_1__SEL_1, - MUX_m_vrg_target_threshold_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__VAL_1, - MUX_m_vvrg_ie_0_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_1$write_1__VAL_1, - MUX_m_vvrg_ie_0_10$write_1__SEL_1, - MUX_m_vvrg_ie_0_10$write_1__VAL_1, - MUX_m_vvrg_ie_0_11$write_1__SEL_1, - MUX_m_vvrg_ie_0_11$write_1__VAL_1, - MUX_m_vvrg_ie_0_12$write_1__SEL_1, - MUX_m_vvrg_ie_0_12$write_1__VAL_1, - MUX_m_vvrg_ie_0_13$write_1__SEL_1, - MUX_m_vvrg_ie_0_13$write_1__VAL_1, - MUX_m_vvrg_ie_0_14$write_1__SEL_1, - MUX_m_vvrg_ie_0_14$write_1__VAL_1, - MUX_m_vvrg_ie_0_15$write_1__SEL_1, - MUX_m_vvrg_ie_0_15$write_1__VAL_1, - MUX_m_vvrg_ie_0_16$write_1__SEL_1, - MUX_m_vvrg_ie_0_16$write_1__VAL_1, - MUX_m_vvrg_ie_0_2$write_1__SEL_1, - MUX_m_vvrg_ie_0_2$write_1__VAL_1, - MUX_m_vvrg_ie_0_3$write_1__SEL_1, - MUX_m_vvrg_ie_0_3$write_1__VAL_1, - MUX_m_vvrg_ie_0_4$write_1__SEL_1, - MUX_m_vvrg_ie_0_4$write_1__VAL_1, - MUX_m_vvrg_ie_0_5$write_1__SEL_1, - MUX_m_vvrg_ie_0_5$write_1__VAL_1, - MUX_m_vvrg_ie_0_6$write_1__SEL_1, - MUX_m_vvrg_ie_0_6$write_1__VAL_1, - MUX_m_vvrg_ie_0_7$write_1__SEL_1, - MUX_m_vvrg_ie_0_7$write_1__VAL_1, - MUX_m_vvrg_ie_0_8$write_1__SEL_1, - MUX_m_vvrg_ie_0_8$write_1__VAL_1, - MUX_m_vvrg_ie_0_9$write_1__SEL_1, - MUX_m_vvrg_ie_0_9$write_1__VAL_1, - MUX_m_vvrg_ie_1_0$write_1__SEL_1, - MUX_m_vvrg_ie_1_0$write_1__VAL_1, - MUX_m_vvrg_ie_1_1$write_1__SEL_1, - MUX_m_vvrg_ie_1_1$write_1__VAL_1, - MUX_m_vvrg_ie_1_10$write_1__SEL_1, - MUX_m_vvrg_ie_1_10$write_1__VAL_1, - MUX_m_vvrg_ie_1_11$write_1__SEL_1, - MUX_m_vvrg_ie_1_11$write_1__VAL_1, - MUX_m_vvrg_ie_1_12$write_1__SEL_1, - MUX_m_vvrg_ie_1_12$write_1__VAL_1, - MUX_m_vvrg_ie_1_13$write_1__SEL_1, - MUX_m_vvrg_ie_1_13$write_1__VAL_1, - MUX_m_vvrg_ie_1_14$write_1__SEL_1, - MUX_m_vvrg_ie_1_14$write_1__VAL_1, - MUX_m_vvrg_ie_1_15$write_1__SEL_1, - MUX_m_vvrg_ie_1_15$write_1__VAL_1, - MUX_m_vvrg_ie_1_16$write_1__SEL_1, - MUX_m_vvrg_ie_1_16$write_1__VAL_1, - MUX_m_vvrg_ie_1_2$write_1__SEL_1, - MUX_m_vvrg_ie_1_2$write_1__VAL_1, - MUX_m_vvrg_ie_1_3$write_1__SEL_1, - MUX_m_vvrg_ie_1_3$write_1__VAL_1, - MUX_m_vvrg_ie_1_4$write_1__SEL_1, - MUX_m_vvrg_ie_1_4$write_1__VAL_1, - MUX_m_vvrg_ie_1_5$write_1__SEL_1, - MUX_m_vvrg_ie_1_5$write_1__VAL_1, - MUX_m_vvrg_ie_1_6$write_1__SEL_1, - MUX_m_vvrg_ie_1_6$write_1__VAL_1, - MUX_m_vvrg_ie_1_7$write_1__SEL_1, - MUX_m_vvrg_ie_1_7$write_1__VAL_1, - MUX_m_vvrg_ie_1_8$write_1__SEL_1, - MUX_m_vvrg_ie_1_8$write_1__VAL_1, - MUX_m_vvrg_ie_1_9$write_1__SEL_1, - MUX_m_vvrg_ie_1_9$write_1__VAL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h75676; - reg [31 : 0] v__h75874; - reg [31 : 0] v__h76072; - reg [31 : 0] v__h76270; - reg [31 : 0] v__h76468; - reg [31 : 0] v__h76666; - reg [31 : 0] v__h76864; - reg [31 : 0] v__h77062; - reg [31 : 0] v__h77260; - reg [31 : 0] v__h77458; - reg [31 : 0] v__h77656; - reg [31 : 0] v__h77854; - reg [31 : 0] v__h78052; - reg [31 : 0] v__h78250; - reg [31 : 0] v__h78448; - reg [31 : 0] v__h78646; - reg [31 : 0] v__h6144; - reg [31 : 0] v__h13080; - reg [31 : 0] v__h13265; - reg [31 : 0] v__h13463; - reg [31 : 0] v__h13713; - reg [31 : 0] v__h18186; - reg [31 : 0] v__h23802; - reg [31 : 0] v__h25975; - reg [31 : 0] v__h24056; - reg [31 : 0] v__h26250; - reg [31 : 0] v__h26463; - reg [31 : 0] v__h26740; - reg [31 : 0] v__h26968; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h28048; - reg [31 : 0] v__h67030; - reg [31 : 0] v__h67318; - reg [31 : 0] v__h67847; - reg [31 : 0] v__h67933; - reg [31 : 0] v__h68132; - reg [31 : 0] v__h68353; - reg [31 : 0] v__h74690; - reg [31 : 0] v__h74800; - reg [31 : 0] v__h74913; - reg [31 : 0] v__h6138; - reg [31 : 0] v__h13074; - reg [31 : 0] v__h13259; - reg [31 : 0] v__h13457; - reg [31 : 0] v__h13707; - reg [31 : 0] v__h18180; - reg [31 : 0] v__h23796; - reg [31 : 0] v__h24050; - reg [31 : 0] v__h25969; - reg [31 : 0] v__h26244; - reg [31 : 0] v__h26457; - reg [31 : 0] v__h26734; - reg [31 : 0] v__h26962; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28042; - reg [31 : 0] v__h67024; - reg [31 : 0] v__h67312; - reg [31 : 0] v__h67841; - reg [31 : 0] v__h67927; - reg [31 : 0] v__h68126; - reg [31 : 0] v__h68347; - reg [31 : 0] v__h74684; - reg [31 : 0] v__h74794; - reg [31 : 0] v__h74907; - reg [31 : 0] v__h75670; - reg [31 : 0] v__h75868; - reg [31 : 0] v__h76066; - reg [31 : 0] v__h76264; - reg [31 : 0] v__h76462; - reg [31 : 0] v__h76660; - reg [31 : 0] v__h76858; - reg [31 : 0] v__h77056; - reg [31 : 0] v__h77254; - reg [31 : 0] v__h77452; - reg [31 : 0] v__h77650; - reg [31 : 0] v__h77848; - reg [31 : 0] v__h78046; - reg [31 : 0] v__h78244; - reg [31 : 0] v__h78442; - reg [31 : 0] v__h78640; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] y_avValue_fst__h26148; - reg [4 : 0] x__h24011, x__h67487; - reg [2 : 0] x__h13493, x__h23832; - reg [1 : 0] v__h67107, y_avValue_snd__h26149; - reg CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - wire [63 : 0] addr_offset__h13216, - addr_offset__h26929, - rdata___1__h26404, - rdata__h26202, - v__h13422, - v__h13671, - v__h18144, - v__h23761, - v__h25455, - v__h25474, - x__h26361, - y_avValue_fst__h26094, - y_avValue_fst__h26115, - y_avValue_fst__h26127, - y_avValue_fst__h26143, - y_avValue_fst__h26159, - y_avValue_fst__h26164, - y_avValue_fst__h26175, - y_avValue_fst__h26180, - y_avValue_fst__h26194; - wire [31 : 0] v_ie__h18147, - v_ip__h13674, - wdata32__h26930, - x__h23673, - x__h67110; - wire [9 : 0] source_id__h15665, - source_id__h15772, - source_id__h15845, - source_id__h15918, - source_id__h15991, - source_id__h16064, - source_id__h16137, - source_id__h16210, - source_id__h16283, - source_id__h16356, - source_id__h16429, - source_id__h16502, - source_id__h16575, - source_id__h16648, - source_id__h16721, - source_id__h16794, - source_id__h16867, - source_id__h16940, - source_id__h17013, - source_id__h17086, - source_id__h17159, - source_id__h17232, - source_id__h17305, - source_id__h17378, - source_id__h17451, - source_id__h17524, - source_id__h17597, - source_id__h17670, - source_id__h17743, - source_id__h17816, - source_id__h17889, - source_id__h20137, - source_id__h20313, - source_id__h20421, - source_id__h20529, - source_id__h20637, - source_id__h20745, - source_id__h20853, - source_id__h20961, - source_id__h21069, - source_id__h21177, - source_id__h21285, - source_id__h21393, - source_id__h21501, - source_id__h21609, - source_id__h21717, - source_id__h21825, - source_id__h21933, - source_id__h22041, - source_id__h22149, - source_id__h22257, - source_id__h22365, - source_id__h22473, - source_id__h22581, - source_id__h22689, - source_id__h22797, - source_id__h22905, - source_id__h23013, - source_id__h23121, - source_id__h23229, - source_id__h23337, - source_id__h23445, - source_id__h29475, - source_id__h30685, - source_id__h31895, - source_id__h33105, - source_id__h34315, - source_id__h35525, - source_id__h36735, - source_id__h37945, - source_id__h39155, - source_id__h40365, - source_id__h41575, - source_id__h42785, - source_id__h43995, - source_id__h45205, - source_id__h46415, - source_id__h47625, - source_id__h48835, - source_id__h50045, - source_id__h51255, - source_id__h52465, - source_id__h53675, - source_id__h54885, - source_id__h56095, - source_id__h57305, - source_id__h58515, - source_id__h59725, - source_id__h60935, - source_id__h62145, - source_id__h63355, - source_id__h64565, - source_id__h65775, - source_id__h67436, - source_id_base__h13630, - source_id_base__h28148; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71313, - b__h73318, - max_id__h23959; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71312, - a__h73317; - wire [1 : 0] rresp__h26203, - v__h26934, - v__h27094, - v__h27107, - v__h27942, - v__h27961, - v__h28125, - v__h28144, - v__h67144, - v__h67432, - v__h67476, - y_avValue_snd__h26095, - y_avValue_snd__h26116, - y_avValue_snd__h26128, - y_avValue_snd__h26144, - y_avValue_snd__h26160, - y_avValue_snd__h26165, - y_avValue_snd__h26176, - y_avValue_snd__h26181, - y_avValue_snd__h26195; - wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, - NOT_m_cfg_verbosity_read_ULE_1_5___d16, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982, - NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313, - NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321, - NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329, - NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337, - NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345, - NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353, - NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361, - NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242, - NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249, - NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257, - NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265, - 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_dfoo312, - _dfoo313, - _dfoo314, - _dfoo315, - _dfoo316, - _dfoo317, - _dfoo318, - _dfoo319, - _dfoo32, - _dfoo320, - _dfoo321, - _dfoo322, - _dfoo323, - _dfoo324, - _dfoo325, - _dfoo326, - _dfoo327, - _dfoo328, - _dfoo329, - _dfoo33, - _dfoo330, - _dfoo331, - _dfoo332, - _dfoo333, - _dfoo334, - _dfoo335, - _dfoo336, - _dfoo337, - _dfoo338, - _dfoo339, - _dfoo34, - _dfoo340, - _dfoo342, - _dfoo344, - _dfoo346, - _dfoo348, - _dfoo35, - _dfoo350, - _dfoo352, - _dfoo354, - _dfoo356, - _dfoo358, - _dfoo36, - _dfoo360, - _dfoo362, - _dfoo364, - _dfoo366, - _dfoo368, - _dfoo37, - _dfoo370, - _dfoo372, - _dfoo374, - _dfoo376, - _dfoo378, - _dfoo38, - _dfoo380, - _dfoo382, - _dfoo384, - _dfoo386, - _dfoo388, - _dfoo39, - _dfoo390, - _dfoo392, - _dfoo394, - _dfoo396, - _dfoo398, - _dfoo4, - _dfoo40, - _dfoo400, - _dfoo402, - _dfoo404, - _dfoo406, - _dfoo408, - _dfoo409, - _dfoo41, - _dfoo410, - _dfoo411, - _dfoo412, - _dfoo413, - _dfoo414, - _dfoo415, - _dfoo416, - _dfoo417, - _dfoo418, - _dfoo419, - _dfoo42, - _dfoo420, - _dfoo421, - _dfoo422, - _dfoo423, - _dfoo424, - _dfoo425, - _dfoo426, - _dfoo427, - _dfoo428, - _dfoo429, - _dfoo43, - _dfoo430, - _dfoo431, - _dfoo432, - _dfoo433, - _dfoo434, - _dfoo435, - _dfoo436, - _dfoo437, - _dfoo438, - _dfoo439, - _dfoo44, - _dfoo440, - _dfoo441, - _dfoo442, - _dfoo443, - _dfoo444, - _dfoo445, - _dfoo446, - _dfoo447, - _dfoo448, - _dfoo449, - _dfoo45, - _dfoo450, - _dfoo451, - _dfoo452, - _dfoo453, - _dfoo454, - _dfoo455, - _dfoo456, - _dfoo457, - _dfoo458, - _dfoo459, - _dfoo46, - _dfoo460, - _dfoo461, - _dfoo462, - _dfoo463, - _dfoo464, - _dfoo465, - _dfoo466, - _dfoo467, - _dfoo468, - _dfoo469, - _dfoo47, - _dfoo470, - _dfoo471, - _dfoo472, - _dfoo473, - _dfoo474, - _dfoo475, - _dfoo476, - _dfoo478, - _dfoo48, - _dfoo480, - _dfoo482, - _dfoo484, - _dfoo486, - _dfoo488, - _dfoo49, - _dfoo490, - _dfoo492, - _dfoo494, - _dfoo496, - _dfoo498, - _dfoo5, - _dfoo50, - _dfoo500, - _dfoo502, - _dfoo504, - _dfoo506, - _dfoo508, - _dfoo51, - _dfoo510, - _dfoo512, - _dfoo514, - _dfoo516, - _dfoo518, - _dfoo52, - _dfoo520, - _dfoo522, - _dfoo524, - _dfoo526, - _dfoo528, - _dfoo53, - _dfoo530, - _dfoo532, - _dfoo534, - _dfoo536, - _dfoo538, - _dfoo54, - _dfoo540, - _dfoo542, - _dfoo544, - _dfoo545, - _dfoo546, - _dfoo547, - _dfoo548, - _dfoo549, - _dfoo55, - _dfoo550, - _dfoo551, - _dfoo552, - _dfoo553, - _dfoo554, - _dfoo555, - _dfoo556, - _dfoo557, - _dfoo558, - _dfoo559, - _dfoo56, - _dfoo560, - _dfoo561, - _dfoo562, - _dfoo563, - _dfoo564, - _dfoo565, - _dfoo566, - _dfoo567, - _dfoo568, - _dfoo569, - _dfoo57, - _dfoo570, - _dfoo571, - _dfoo572, - _dfoo573, - _dfoo574, - _dfoo575, - _dfoo576, - _dfoo577, - _dfoo578, - _dfoo579, - _dfoo58, - _dfoo580, - _dfoo581, - _dfoo582, - _dfoo583, - _dfoo584, - _dfoo585, - _dfoo586, - _dfoo587, - _dfoo588, - _dfoo589, - _dfoo59, - _dfoo590, - _dfoo591, - _dfoo592, - _dfoo593, - _dfoo594, - _dfoo595, - _dfoo596, - _dfoo597, - _dfoo598, - _dfoo599, - _dfoo6, - _dfoo60, - _dfoo600, - _dfoo601, - _dfoo602, - _dfoo603, - _dfoo604, - _dfoo605, - _dfoo606, - _dfoo607, - _dfoo608, - _dfoo609, - _dfoo61, - _dfoo610, - _dfoo611, - _dfoo612, - _dfoo614, - _dfoo616, - _dfoo618, - _dfoo62, - _dfoo620, - _dfoo622, - _dfoo624, - _dfoo626, - _dfoo628, - _dfoo63, - _dfoo630, - _dfoo632, - _dfoo634, - _dfoo636, - _dfoo638, - _dfoo64, - _dfoo640, - _dfoo642, - _dfoo644, - _dfoo646, - _dfoo648, - _dfoo65, - _dfoo650, - _dfoo652, - _dfoo654, - _dfoo656, - _dfoo658, - _dfoo66, - _dfoo660, - _dfoo662, - _dfoo664, - _dfoo666, - _dfoo668, - _dfoo67, - _dfoo670, - _dfoo672, - _dfoo674, - _dfoo676, - _dfoo678, - _dfoo68, - _dfoo680, - _dfoo681, - _dfoo682, - _dfoo683, - _dfoo684, - _dfoo685, - _dfoo686, - _dfoo687, - _dfoo688, - _dfoo689, - _dfoo690, - _dfoo691, - _dfoo692, - _dfoo693, - _dfoo694, - _dfoo695, - _dfoo696, - _dfoo697, - _dfoo698, - _dfoo699, - _dfoo7, - _dfoo70, - _dfoo700, - _dfoo701, - _dfoo702, - _dfoo703, - _dfoo704, - _dfoo705, - _dfoo706, - _dfoo707, - _dfoo708, - _dfoo709, - _dfoo710, - _dfoo711, - _dfoo712, - _dfoo713, - _dfoo714, - _dfoo715, - _dfoo716, - _dfoo717, - _dfoo718, - _dfoo719, - _dfoo72, - _dfoo720, - _dfoo721, - _dfoo722, - _dfoo723, - _dfoo724, - _dfoo725, - _dfoo726, - _dfoo727, - _dfoo728, - _dfoo729, - _dfoo730, - _dfoo731, - _dfoo732, - _dfoo733, - _dfoo734, - _dfoo735, - _dfoo736, - _dfoo737, - _dfoo738, - _dfoo739, - _dfoo74, - _dfoo740, - _dfoo741, - _dfoo742, - _dfoo743, - _dfoo744, - _dfoo745, - _dfoo746, - _dfoo747, - _dfoo748, - _dfoo750, - _dfoo752, - _dfoo754, - _dfoo756, - _dfoo758, - _dfoo76, - _dfoo760, - _dfoo762, - _dfoo764, - _dfoo766, - _dfoo768, - _dfoo770, - _dfoo772, - _dfoo774, - _dfoo776, - _dfoo778, - _dfoo78, - _dfoo780, - _dfoo782, - _dfoo784, - _dfoo786, - _dfoo788, - _dfoo790, - _dfoo792, - _dfoo794, - _dfoo796, - _dfoo798, - _dfoo8, - _dfoo80, - _dfoo800, - _dfoo802, - _dfoo804, - _dfoo806, - _dfoo808, - _dfoo810, - _dfoo812, - _dfoo814, - _dfoo816, - _dfoo817, - _dfoo818, - _dfoo819, - _dfoo82, - _dfoo820, - _dfoo821, - _dfoo822, - _dfoo823, - _dfoo824, - _dfoo825, - _dfoo826, - _dfoo827, - _dfoo828, - _dfoo829, - _dfoo830, - _dfoo831, - _dfoo832, - _dfoo833, - _dfoo834, - _dfoo835, - _dfoo836, - _dfoo837, - _dfoo838, - _dfoo839, - _dfoo84, - _dfoo840, - _dfoo841, - _dfoo842, - _dfoo843, - _dfoo844, - _dfoo845, - _dfoo846, - _dfoo847, - _dfoo848, - _dfoo849, - _dfoo850, - _dfoo851, - _dfoo852, - _dfoo853, - _dfoo854, - _dfoo855, - _dfoo856, - _dfoo857, - _dfoo858, - _dfoo859, - _dfoo86, - _dfoo860, - _dfoo861, - _dfoo862, - _dfoo863, - _dfoo864, - _dfoo865, - _dfoo866, - _dfoo867, - _dfoo868, - _dfoo869, - _dfoo870, - _dfoo871, - _dfoo872, - _dfoo873, - _dfoo874, - _dfoo875, - _dfoo876, - _dfoo877, - _dfoo878, - _dfoo879, - _dfoo88, - _dfoo880, - _dfoo881, - _dfoo882, - _dfoo883, - _dfoo884, - _dfoo886, - _dfoo888, - _dfoo890, - _dfoo892, - _dfoo894, - _dfoo896, - _dfoo898, - _dfoo9, - _dfoo90, - _dfoo900, - _dfoo902, - _dfoo904, - _dfoo906, - _dfoo908, - _dfoo910, - _dfoo912, - _dfoo914, - _dfoo916, - _dfoo918, - _dfoo92, - _dfoo920, - _dfoo922, - _dfoo924, - _dfoo926, - _dfoo928, - _dfoo930, - _dfoo932, - _dfoo934, - _dfoo936, - _dfoo938, - _dfoo94, - _dfoo940, - _dfoo942, - _dfoo944, - _dfoo946, - _dfoo948, - _dfoo950, - _dfoo952, - _dfoo953, - _dfoo954, - _dfoo955, - _dfoo956, - _dfoo957, - _dfoo958, - _dfoo959, - _dfoo96, - _dfoo960, - _dfoo961, - _dfoo962, - _dfoo963, - _dfoo964, - _dfoo965, - _dfoo966, - _dfoo967, - _dfoo968, - _dfoo969, - _dfoo970, - _dfoo971, - _dfoo972, - _dfoo973, - _dfoo974, - _dfoo975, - _dfoo976, - _dfoo977, - _dfoo978, - _dfoo979, - _dfoo98, - _dfoo980, - _dfoo981, - _dfoo982, - _dfoo983, - _dfoo984, - _dfoo985, - _dfoo986, - _dfoo987, - _dfoo988, - _dfoo989, - _dfoo990, - _dfoo991, - _dfoo992, - _dfoo993, - _dfoo994, - _dfoo995, - _dfoo996, - _dfoo997, - _dfoo998, - _dfoo999, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, - m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method show_PLIC_state - assign RDY_show_PLIC_state = 1'd1 ; - assign CAN_FIRE_show_PLIC_state = 1'd1 ; - assign WILL_FIRE_show_PLIC_state = EN_show_PLIC_state ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // action method v_sources_0_m_interrupt_req - assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - - // action method v_sources_1_m_interrupt_req - assign CAN_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - - // action method v_sources_2_m_interrupt_req - assign CAN_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - - // action method v_sources_3_m_interrupt_req - assign CAN_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - - // action method v_sources_4_m_interrupt_req - assign CAN_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - - // action method v_sources_5_m_interrupt_req - assign CAN_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - - // action method v_sources_6_m_interrupt_req - assign CAN_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - - // action method v_sources_7_m_interrupt_req - assign CAN_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - - // action method v_sources_8_m_interrupt_req - assign CAN_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - - // action method v_sources_9_m_interrupt_req - assign CAN_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - - // action method v_sources_10_m_interrupt_req - assign CAN_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - - // action method v_sources_11_m_interrupt_req - assign CAN_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - - // action method v_sources_12_m_interrupt_req - assign CAN_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - - // action method v_sources_13_m_interrupt_req - assign CAN_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - - // action method v_sources_14_m_interrupt_req - assign CAN_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - - // action method v_sources_15_m_interrupt_req - assign CAN_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - - // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71312 > m_vrg_target_threshold_0 ; - - // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73317 > m_vrg_target_threshold_1 ; - - // submodule m_f_reset_reqs - FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_reqs$ENQ), - .DEQ(m_f_reset_reqs$DEQ), - .CLR(m_f_reset_reqs$CLR), - .FULL_N(m_f_reset_reqs$FULL_N), - .EMPTY_N(m_f_reset_reqs$EMPTY_N)); - - // submodule m_f_reset_rsps - FIFO20 #(.guarded(32'd1)) m_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_rsps$ENQ), - .DEQ(m_f_reset_rsps$DEQ), - .CLR(m_f_reset_rsps$CLR), - .FULL_N(m_f_reset_rsps$FULL_N), - .EMPTY_N(m_f_reset_rsps$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_addr$D_IN), - .ENQ(m_slave_xactor_f_rd_addr$ENQ), - .DEQ(m_slave_xactor_f_rd_addr$DEQ), - .CLR(m_slave_xactor_f_rd_addr$CLR), - .D_OUT(m_slave_xactor_f_rd_addr$D_OUT), - .FULL_N(m_slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_data$D_IN), - .ENQ(m_slave_xactor_f_rd_data$ENQ), - .DEQ(m_slave_xactor_f_rd_data$DEQ), - .CLR(m_slave_xactor_f_rd_data$CLR), - .D_OUT(m_slave_xactor_f_rd_data$D_OUT), - .FULL_N(m_slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_addr$D_IN), - .ENQ(m_slave_xactor_f_wr_addr$ENQ), - .DEQ(m_slave_xactor_f_wr_addr$DEQ), - .CLR(m_slave_xactor_f_wr_addr$CLR), - .D_OUT(m_slave_xactor_f_wr_addr$D_OUT), - .FULL_N(m_slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_data$D_IN), - .ENQ(m_slave_xactor_f_wr_data$ENQ), - .DEQ(m_slave_xactor_f_wr_data$DEQ), - .CLR(m_slave_xactor_f_wr_data$CLR), - .D_OUT(m_slave_xactor_f_wr_data$D_OUT), - .FULL_N(m_slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_resp$D_IN), - .ENQ(m_slave_xactor_f_wr_resp$ENQ), - .DEQ(m_slave_xactor_f_wr_resp$DEQ), - .CLR(m_slave_xactor_f_wr_resp$CLR), - .D_OUT(m_slave_xactor_f_wr_resp$D_OUT), - .FULL_N(m_slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = - m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - - // rule RL_m_rl_process_rd_req - assign CAN_FIRE_RL_m_rl_process_rd_req = - m_slave_xactor_f_rd_addr$EMPTY_N && - m_slave_xactor_f_rd_data$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - - // rule RL_m_rl_process_wr_req - assign CAN_FIRE_RL_m_rl_process_wr_req = - m_slave_xactor_f_wr_addr$EMPTY_N && - m_slave_xactor_f_wr_data$EMPTY_N && - m_slave_xactor_f_wr_resp$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_wr_req = - CAN_FIRE_RL_m_rl_process_wr_req && - !WILL_FIRE_RL_m_rl_process_rd_req ; - - // inputs to muxes for submodule ports - assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; - assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; - assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; - assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; - assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; - assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; - assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; - assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; - assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; - assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; - assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; - assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; - assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; - assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; - assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; - assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; - assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; - assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; - assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; - assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; - assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ; - assign MUX_m_vvrg_ie_0_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ; - assign MUX_m_vvrg_ie_0_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ; - assign MUX_m_vvrg_ie_0_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ; - assign MUX_m_vvrg_ie_0_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ; - assign MUX_m_vvrg_ie_0_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ; - assign MUX_m_vvrg_ie_0_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ; - assign MUX_m_vvrg_ie_0_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ; - assign MUX_m_vvrg_ie_0_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ; - assign MUX_m_vvrg_ie_0_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ; - assign MUX_m_vvrg_ie_0_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ; - assign MUX_m_vvrg_ie_0_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ; - assign MUX_m_vvrg_ie_0_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ; - assign MUX_m_vvrg_ie_0_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ; - assign MUX_m_vvrg_ie_0_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ; - assign MUX_m_vvrg_ie_0_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ; - assign MUX_m_vvrg_ie_1_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ; - assign MUX_m_vvrg_ie_1_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ; - assign MUX_m_vvrg_ie_1_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ; - assign MUX_m_vvrg_ie_1_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ; - assign MUX_m_vvrg_ie_1_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ; - assign MUX_m_vvrg_ie_1_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ; - assign MUX_m_vvrg_ie_1_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ; - assign MUX_m_vvrg_ie_1_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ; - assign MUX_m_vvrg_ie_1_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ; - assign MUX_m_vvrg_ie_1_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ; - assign MUX_m_vvrg_ie_1_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ; - assign MUX_m_vvrg_ie_1_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ; - assign MUX_m_vvrg_ie_1_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ; - assign MUX_m_vvrg_ie_1_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ; - assign MUX_m_vvrg_ie_1_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ; - assign MUX_m_vvrg_ie_1_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ; - assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; - assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2040 ; - assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2038 ; - assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2020 ; - assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2018 ; - assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2016 ; - assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2014 ; - assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2012 ; - assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2010 ; - assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2008 ; - assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2036 ; - assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2034 ; - assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2032 ; - assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2030 ; - assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2028 ; - assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2026 ; - assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2024 ; - assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2022 ; - assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2006 ; - assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2004 ; - assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1986 ; - assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1984 ; - assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1982 ; - assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1980 ; - assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1978 ; - assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1976 ; - assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1974 ; - assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2002 ; - assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2000 ; - assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1998 ; - assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1996 ; - assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1994 ; - assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1992 ; - assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1990 ; - assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1988 ; - - // register m_cfg_verbosity - assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign m_cfg_verbosity$EN = EN_set_verbosity ; - - // register m_rg_addr_base - assign m_rg_addr_base$D_IN = set_addr_map_addr_base ; - assign m_rg_addr_base$EN = EN_set_addr_map ; - - // register m_rg_addr_lim - assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign m_rg_addr_lim$EN = EN_set_addr_map ; - - // register m_vrg_servicing_source_0 - assign m_vrg_servicing_source_0$D_IN = - MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_servicing_source_1 - assign m_vrg_servicing_source_1$D_IN = - MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_0 - assign m_vrg_source_busy_0$D_IN = - !MUX_m_vrg_source_busy_0$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_1 - assign m_vrg_source_busy_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_10 - assign m_vrg_source_busy_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_11 - assign m_vrg_source_busy_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_12 - assign m_vrg_source_busy_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_13 - assign m_vrg_source_busy_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_14 - assign m_vrg_source_busy_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_15 - assign m_vrg_source_busy_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_16 - assign m_vrg_source_busy_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_2 - assign m_vrg_source_busy_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_3 - assign m_vrg_source_busy_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_4 - assign m_vrg_source_busy_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_5 - assign m_vrg_source_busy_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_6 - assign m_vrg_source_busy_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_7 - assign m_vrg_source_busy_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_8 - assign m_vrg_source_busy_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_9 - assign m_vrg_source_busy_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_0 - assign m_vrg_source_ip_0$D_IN = 1'd0 ; - assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_1 - assign m_vrg_source_ip_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_0_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_1$EN = - !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_10 - assign m_vrg_source_ip_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_9_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_10$EN = - !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_11 - assign m_vrg_source_ip_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_10_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_11$EN = - !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_12 - assign m_vrg_source_ip_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_11_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_12$EN = - !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_13 - assign m_vrg_source_ip_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_12_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_13$EN = - !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_14 - assign m_vrg_source_ip_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_13_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_14$EN = - !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_15 - assign m_vrg_source_ip_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_14_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_15$EN = - !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_16 - assign m_vrg_source_ip_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_15_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_16$EN = - !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_2 - assign m_vrg_source_ip_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_1_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_2$EN = - !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_3 - assign m_vrg_source_ip_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_2_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_3$EN = - !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_4 - assign m_vrg_source_ip_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_3_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_4$EN = - !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_5 - assign m_vrg_source_ip_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_4_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_5$EN = - !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_6 - assign m_vrg_source_ip_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_5_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_6$EN = - !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_7 - assign m_vrg_source_ip_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_6_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_7$EN = - !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_8 - assign m_vrg_source_ip_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_7_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_8$EN = - !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_9 - assign m_vrg_source_ip_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_8_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_9$EN = - !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_0 - assign m_vrg_source_prio_0$D_IN = - MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_1 - assign m_vrg_source_prio_1$D_IN = - MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_10 - assign m_vrg_source_prio_10$D_IN = - MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_11 - assign m_vrg_source_prio_11$D_IN = - MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_12 - assign m_vrg_source_prio_12$D_IN = - MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_13 - assign m_vrg_source_prio_13$D_IN = - MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_14 - assign m_vrg_source_prio_14$D_IN = - MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_15 - assign m_vrg_source_prio_15$D_IN = - MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_16 - assign m_vrg_source_prio_16$D_IN = - MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_2 - assign m_vrg_source_prio_2$D_IN = - MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_3 - assign m_vrg_source_prio_3$D_IN = - MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_4 - assign m_vrg_source_prio_4$D_IN = - MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_5 - assign m_vrg_source_prio_5$D_IN = - MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_6 - assign m_vrg_source_prio_6$D_IN = - MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_7 - assign m_vrg_source_prio_7$D_IN = - MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_8 - assign m_vrg_source_prio_8$D_IN = - MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_9 - assign m_vrg_source_prio_9$D_IN = - MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_0 - assign m_vrg_target_threshold_0$D_IN = - MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_1 - assign m_vrg_target_threshold_1$D_IN = - MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_0 - assign m_vvrg_ie_0_0$D_IN = - MUX_m_vvrg_ie_0_0$write_1__SEL_1 && - MUX_m_vvrg_ie_0_0$write_1__VAL_1 ; - assign m_vvrg_ie_0_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_1 - assign m_vvrg_ie_0_1$D_IN = - MUX_m_vvrg_ie_0_1$write_1__SEL_1 && - MUX_m_vvrg_ie_0_1$write_1__VAL_1 ; - assign m_vvrg_ie_0_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_10 - assign m_vvrg_ie_0_10$D_IN = - MUX_m_vvrg_ie_0_10$write_1__SEL_1 && - MUX_m_vvrg_ie_0_10$write_1__VAL_1 ; - assign m_vvrg_ie_0_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_11 - assign m_vvrg_ie_0_11$D_IN = - MUX_m_vvrg_ie_0_11$write_1__SEL_1 && - MUX_m_vvrg_ie_0_11$write_1__VAL_1 ; - assign m_vvrg_ie_0_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_12 - assign m_vvrg_ie_0_12$D_IN = - MUX_m_vvrg_ie_0_12$write_1__SEL_1 && - MUX_m_vvrg_ie_0_12$write_1__VAL_1 ; - assign m_vvrg_ie_0_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_13 - assign m_vvrg_ie_0_13$D_IN = - MUX_m_vvrg_ie_0_13$write_1__SEL_1 && - MUX_m_vvrg_ie_0_13$write_1__VAL_1 ; - assign m_vvrg_ie_0_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_14 - assign m_vvrg_ie_0_14$D_IN = - MUX_m_vvrg_ie_0_14$write_1__SEL_1 && - MUX_m_vvrg_ie_0_14$write_1__VAL_1 ; - assign m_vvrg_ie_0_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_15 - assign m_vvrg_ie_0_15$D_IN = - MUX_m_vvrg_ie_0_15$write_1__SEL_1 && - MUX_m_vvrg_ie_0_15$write_1__VAL_1 ; - assign m_vvrg_ie_0_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_16 - assign m_vvrg_ie_0_16$D_IN = - MUX_m_vvrg_ie_0_16$write_1__SEL_1 && - MUX_m_vvrg_ie_0_16$write_1__VAL_1 ; - assign m_vvrg_ie_0_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_2 - assign m_vvrg_ie_0_2$D_IN = - MUX_m_vvrg_ie_0_2$write_1__SEL_1 && - MUX_m_vvrg_ie_0_2$write_1__VAL_1 ; - assign m_vvrg_ie_0_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_3 - assign m_vvrg_ie_0_3$D_IN = - MUX_m_vvrg_ie_0_3$write_1__SEL_1 && - MUX_m_vvrg_ie_0_3$write_1__VAL_1 ; - assign m_vvrg_ie_0_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_4 - assign m_vvrg_ie_0_4$D_IN = - MUX_m_vvrg_ie_0_4$write_1__SEL_1 && - MUX_m_vvrg_ie_0_4$write_1__VAL_1 ; - assign m_vvrg_ie_0_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_5 - assign m_vvrg_ie_0_5$D_IN = - MUX_m_vvrg_ie_0_5$write_1__SEL_1 && - MUX_m_vvrg_ie_0_5$write_1__VAL_1 ; - assign m_vvrg_ie_0_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_6 - assign m_vvrg_ie_0_6$D_IN = - MUX_m_vvrg_ie_0_6$write_1__SEL_1 && - MUX_m_vvrg_ie_0_6$write_1__VAL_1 ; - assign m_vvrg_ie_0_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_7 - assign m_vvrg_ie_0_7$D_IN = - MUX_m_vvrg_ie_0_7$write_1__SEL_1 && - MUX_m_vvrg_ie_0_7$write_1__VAL_1 ; - assign m_vvrg_ie_0_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_8 - assign m_vvrg_ie_0_8$D_IN = - MUX_m_vvrg_ie_0_8$write_1__SEL_1 && - MUX_m_vvrg_ie_0_8$write_1__VAL_1 ; - assign m_vvrg_ie_0_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_9 - assign m_vvrg_ie_0_9$D_IN = - MUX_m_vvrg_ie_0_9$write_1__SEL_1 && - MUX_m_vvrg_ie_0_9$write_1__VAL_1 ; - assign m_vvrg_ie_0_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_0 - assign m_vvrg_ie_1_0$D_IN = - MUX_m_vvrg_ie_1_0$write_1__SEL_1 && - MUX_m_vvrg_ie_1_0$write_1__VAL_1 ; - assign m_vvrg_ie_1_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_1 - assign m_vvrg_ie_1_1$D_IN = - MUX_m_vvrg_ie_1_1$write_1__SEL_1 && - MUX_m_vvrg_ie_1_1$write_1__VAL_1 ; - assign m_vvrg_ie_1_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_10 - assign m_vvrg_ie_1_10$D_IN = - MUX_m_vvrg_ie_1_10$write_1__SEL_1 && - MUX_m_vvrg_ie_1_10$write_1__VAL_1 ; - assign m_vvrg_ie_1_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_11 - assign m_vvrg_ie_1_11$D_IN = - MUX_m_vvrg_ie_1_11$write_1__SEL_1 && - MUX_m_vvrg_ie_1_11$write_1__VAL_1 ; - assign m_vvrg_ie_1_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_12 - assign m_vvrg_ie_1_12$D_IN = - MUX_m_vvrg_ie_1_12$write_1__SEL_1 && - MUX_m_vvrg_ie_1_12$write_1__VAL_1 ; - assign m_vvrg_ie_1_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_13 - assign m_vvrg_ie_1_13$D_IN = - MUX_m_vvrg_ie_1_13$write_1__SEL_1 && - MUX_m_vvrg_ie_1_13$write_1__VAL_1 ; - assign m_vvrg_ie_1_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_14 - assign m_vvrg_ie_1_14$D_IN = - MUX_m_vvrg_ie_1_14$write_1__SEL_1 && - MUX_m_vvrg_ie_1_14$write_1__VAL_1 ; - assign m_vvrg_ie_1_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_15 - assign m_vvrg_ie_1_15$D_IN = - MUX_m_vvrg_ie_1_15$write_1__SEL_1 && - MUX_m_vvrg_ie_1_15$write_1__VAL_1 ; - assign m_vvrg_ie_1_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_16 - assign m_vvrg_ie_1_16$D_IN = - MUX_m_vvrg_ie_1_16$write_1__SEL_1 && - MUX_m_vvrg_ie_1_16$write_1__VAL_1 ; - assign m_vvrg_ie_1_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_2 - assign m_vvrg_ie_1_2$D_IN = - MUX_m_vvrg_ie_1_2$write_1__SEL_1 && - MUX_m_vvrg_ie_1_2$write_1__VAL_1 ; - assign m_vvrg_ie_1_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_3 - assign m_vvrg_ie_1_3$D_IN = - MUX_m_vvrg_ie_1_3$write_1__SEL_1 && - MUX_m_vvrg_ie_1_3$write_1__VAL_1 ; - assign m_vvrg_ie_1_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_4 - assign m_vvrg_ie_1_4$D_IN = - MUX_m_vvrg_ie_1_4$write_1__SEL_1 && - MUX_m_vvrg_ie_1_4$write_1__VAL_1 ; - assign m_vvrg_ie_1_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_5 - assign m_vvrg_ie_1_5$D_IN = - MUX_m_vvrg_ie_1_5$write_1__SEL_1 && - MUX_m_vvrg_ie_1_5$write_1__VAL_1 ; - assign m_vvrg_ie_1_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_6 - assign m_vvrg_ie_1_6$D_IN = - MUX_m_vvrg_ie_1_6$write_1__SEL_1 && - MUX_m_vvrg_ie_1_6$write_1__VAL_1 ; - assign m_vvrg_ie_1_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_7 - assign m_vvrg_ie_1_7$D_IN = - MUX_m_vvrg_ie_1_7$write_1__SEL_1 && - MUX_m_vvrg_ie_1_7$write_1__VAL_1 ; - assign m_vvrg_ie_1_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_8 - assign m_vvrg_ie_1_8$D_IN = - MUX_m_vvrg_ie_1_8$write_1__SEL_1 && - MUX_m_vvrg_ie_1_8$write_1__VAL_1 ; - assign m_vvrg_ie_1_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_9 - assign m_vvrg_ie_1_9$D_IN = - MUX_m_vvrg_ie_1_9$write_1__SEL_1 && - MUX_m_vvrg_ie_1_9$write_1__VAL_1 ; - assign m_vvrg_ie_1_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 || - WILL_FIRE_RL_m_rl_reset ; - - // submodule m_f_reset_reqs - assign m_f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign m_f_reset_reqs$DEQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_reqs$CLR = 1'b0 ; - - // submodule m_f_reset_rsps - assign m_f_reset_rsps$ENQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign m_f_reset_rsps$CLR = 1'b0 ; - - // submodule m_slave_xactor_f_rd_addr - assign m_slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign m_slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ; - assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_rd_data - assign m_slave_xactor_f_rd_data$D_IN = - { m_slave_xactor_f_rd_addr$D_OUT[96:93], - x__h26361, - rresp__h26203, - 1'd1 } ; - assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ; - assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_addr - assign m_slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign m_slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ; - assign m_slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_data - assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign m_slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; - assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_resp - assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26934 } ; - assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; - assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ; - - // remaining internal signals - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 : - ((x__h23673 == 32'h00200000) ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 : - x__h23673 != 32'h00200004 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 || - x__h24011 != 5'd0) ; - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - addr_offset__h13216[11:2] == 10'd0 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 : - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67110 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67110 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26929[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 = - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - 5'd2 : - (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ; - assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200000 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30685 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31895 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33105 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34315 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35525 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36735 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37945 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39155 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40365 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41575 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42785 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43995 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45205 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46415 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47625 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48835 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50045 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51255 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52465 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53675 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54885 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56095 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57305 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58515 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59725 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60935 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62145 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63355 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64565 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65775 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29475 <= 10'd16 ; - assign NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313 = - !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321 = - !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_11 != - v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329 = - !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_12 != - v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337 = - !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_13 != - v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345 = - !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_14 != - v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353 = - !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_15 != - v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361 = - !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_16 != - v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242 = - !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249 = - !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257 = - !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265 = - !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273 = - !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281 = - !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289 = - !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297 = - !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305 = - !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; - assign _dfoo1 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo10 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo100 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo32 ; - assign _dfoo1000 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo932 ; - assign _dfoo1001 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo865 ; - assign _dfoo1002 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo934 ; - assign _dfoo1003 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo867 ; - assign _dfoo1004 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo936 ; - assign _dfoo1005 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo869 ; - assign _dfoo1006 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo938 ; - assign _dfoo1007 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo871 ; - assign _dfoo1008 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo940 ; - assign _dfoo1009 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo873 ; - assign _dfoo1010 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo942 ; - assign _dfoo1011 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo875 ; - assign _dfoo1012 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo944 ; - assign _dfoo1013 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo877 ; - assign _dfoo1014 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo946 ; - assign _dfoo1015 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo879 ; - assign _dfoo1016 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo948 ; - assign _dfoo1017 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo881 ; - assign _dfoo1018 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo950 ; - assign _dfoo1019 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo883 ; - assign _dfoo102 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo34 ; - assign _dfoo1020 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo952 ; - assign _dfoo1022 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo954 ; - assign _dfoo1024 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo956 ; - assign _dfoo1026 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo958 ; - assign _dfoo1028 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo960 ; - assign _dfoo1030 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo962 ; - assign _dfoo1032 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo964 ; - assign _dfoo1034 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo966 ; - assign _dfoo1036 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo968 ; - assign _dfoo1038 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo970 ; - assign _dfoo104 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo36 ; - assign _dfoo1040 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo972 ; - assign _dfoo1042 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo974 ; - assign _dfoo1044 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo976 ; - assign _dfoo1046 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo978 ; - assign _dfoo1048 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo980 ; - assign _dfoo1050 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo982 ; - assign _dfoo1052 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo984 ; - assign _dfoo1054 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo986 ; - assign _dfoo1056 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo988 ; - assign _dfoo1058 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo990 ; - assign _dfoo106 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo38 ; - assign _dfoo1060 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo992 ; - assign _dfoo1062 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo994 ; - assign _dfoo1064 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo996 ; - assign _dfoo1066 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo998 ; - assign _dfoo1068 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1000 ; - assign _dfoo1070 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1002 ; - assign _dfoo1072 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1004 ; - assign _dfoo1074 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1006 ; - assign _dfoo1076 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1008 ; - assign _dfoo1078 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1010 ; - assign _dfoo108 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo40 ; - assign _dfoo1080 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1012 ; - assign _dfoo1082 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1014 ; - assign _dfoo1084 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1016 ; - assign _dfoo1086 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1018 ; - assign _dfoo1088 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1020 ; - assign _dfoo1089 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo953 ; - assign _dfoo1090 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1022 ; - assign _dfoo1091 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo955 ; - assign _dfoo1092 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1024 ; - assign _dfoo1093 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo957 ; - assign _dfoo1094 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1026 ; - assign _dfoo1095 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo959 ; - assign _dfoo1096 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1028 ; - assign _dfoo1097 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo961 ; - assign _dfoo1098 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1030 ; - assign _dfoo1099 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo963 ; - assign _dfoo11 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo110 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo42 ; - assign _dfoo1100 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1032 ; - assign _dfoo1101 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo965 ; - assign _dfoo1102 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1034 ; - assign _dfoo1103 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo967 ; - assign _dfoo1104 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1036 ; - assign _dfoo1105 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo969 ; - assign _dfoo1106 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1038 ; - assign _dfoo1107 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo971 ; - assign _dfoo1108 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1040 ; - assign _dfoo1109 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo973 ; - assign _dfoo1110 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1042 ; - assign _dfoo1111 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo975 ; - assign _dfoo1112 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1044 ; - assign _dfoo1113 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo977 ; - assign _dfoo1114 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1046 ; - assign _dfoo1115 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo979 ; - assign _dfoo1116 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1048 ; - assign _dfoo1117 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo981 ; - assign _dfoo1118 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1050 ; - assign _dfoo1119 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo983 ; - assign _dfoo112 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo44 ; - assign _dfoo1120 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1052 ; - assign _dfoo1121 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo985 ; - assign _dfoo1122 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1054 ; - assign _dfoo1123 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo987 ; - assign _dfoo1124 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1056 ; - assign _dfoo1125 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo989 ; - assign _dfoo1126 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1058 ; - assign _dfoo1127 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo991 ; - assign _dfoo1128 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1060 ; - assign _dfoo1129 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo993 ; - assign _dfoo1130 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1062 ; - assign _dfoo1131 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo995 ; - assign _dfoo1132 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1064 ; - assign _dfoo1133 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo997 ; - assign _dfoo1134 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1066 ; - assign _dfoo1135 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo999 ; - assign _dfoo1136 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1068 ; - assign _dfoo1137 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1001 ; - assign _dfoo1138 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1070 ; - assign _dfoo1139 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1003 ; - assign _dfoo114 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo46 ; - assign _dfoo1140 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1072 ; - assign _dfoo1141 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1005 ; - assign _dfoo1142 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1074 ; - assign _dfoo1143 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1007 ; - assign _dfoo1144 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1076 ; - assign _dfoo1145 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1009 ; - assign _dfoo1146 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1078 ; - assign _dfoo1147 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1011 ; - assign _dfoo1148 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1080 ; - assign _dfoo1149 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1013 ; - assign _dfoo1150 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1082 ; - assign _dfoo1151 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1015 ; - assign _dfoo1152 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1084 ; - assign _dfoo1153 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1017 ; - assign _dfoo1154 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1086 ; - assign _dfoo1155 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1019 ; - assign _dfoo1156 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1088 ; - assign _dfoo1158 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1090 ; - assign _dfoo116 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo48 ; - assign _dfoo1160 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1092 ; - assign _dfoo1162 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1094 ; - assign _dfoo1164 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1096 ; - assign _dfoo1166 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1098 ; - assign _dfoo1168 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1100 ; - assign _dfoo1170 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1102 ; - assign _dfoo1172 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1104 ; - assign _dfoo1174 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1106 ; - assign _dfoo1176 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1108 ; - assign _dfoo1178 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1110 ; - assign _dfoo118 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo50 ; - assign _dfoo1180 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1112 ; - assign _dfoo1182 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1114 ; - assign _dfoo1184 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1116 ; - assign _dfoo1186 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1118 ; - assign _dfoo1188 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1120 ; - assign _dfoo1190 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1122 ; - assign _dfoo1192 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1124 ; - assign _dfoo1194 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1126 ; - assign _dfoo1196 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1128 ; - assign _dfoo1198 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1130 ; - assign _dfoo12 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo120 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo52 ; - assign _dfoo1200 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1132 ; - assign _dfoo1202 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1134 ; - assign _dfoo1204 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1136 ; - assign _dfoo1206 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1138 ; - assign _dfoo1208 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1140 ; - assign _dfoo1210 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1142 ; - assign _dfoo1212 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1144 ; - assign _dfoo1214 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1146 ; - assign _dfoo1216 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1148 ; - assign _dfoo1218 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1150 ; - assign _dfoo122 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo54 ; - assign _dfoo1220 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1152 ; - assign _dfoo1222 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1154 ; - assign _dfoo1224 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1156 ; - assign _dfoo1225 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1089 ; - assign _dfoo1226 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1158 ; - assign _dfoo1227 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1091 ; - assign _dfoo1228 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1160 ; - assign _dfoo1229 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1093 ; - assign _dfoo1230 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1162 ; - assign _dfoo1231 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1095 ; - assign _dfoo1232 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1164 ; - assign _dfoo1233 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1097 ; - assign _dfoo1234 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1166 ; - assign _dfoo1235 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1099 ; - assign _dfoo1236 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1168 ; - assign _dfoo1237 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1101 ; - assign _dfoo1238 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1170 ; - assign _dfoo1239 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1103 ; - assign _dfoo124 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo56 ; - assign _dfoo1240 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1172 ; - assign _dfoo1241 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1105 ; - assign _dfoo1242 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1174 ; - assign _dfoo1243 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1107 ; - assign _dfoo1244 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1176 ; - assign _dfoo1245 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1109 ; - assign _dfoo1246 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1178 ; - assign _dfoo1247 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1111 ; - assign _dfoo1248 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1180 ; - assign _dfoo1249 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1113 ; - assign _dfoo1250 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1182 ; - assign _dfoo1251 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1115 ; - assign _dfoo1252 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1184 ; - assign _dfoo1253 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1117 ; - assign _dfoo1254 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1186 ; - assign _dfoo1255 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1119 ; - assign _dfoo1256 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1188 ; - assign _dfoo1257 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1121 ; - assign _dfoo1258 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1190 ; - assign _dfoo1259 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1123 ; - assign _dfoo126 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo58 ; - assign _dfoo1260 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1192 ; - assign _dfoo1261 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1125 ; - assign _dfoo1262 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1194 ; - assign _dfoo1263 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1127 ; - assign _dfoo1264 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1196 ; - assign _dfoo1265 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1129 ; - assign _dfoo1266 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1198 ; - assign _dfoo1267 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1131 ; - assign _dfoo1268 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1200 ; - assign _dfoo1269 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1133 ; - assign _dfoo1270 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1202 ; - assign _dfoo1271 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1135 ; - assign _dfoo1272 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1204 ; - assign _dfoo1273 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1137 ; - assign _dfoo1274 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1206 ; - assign _dfoo1275 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1139 ; - assign _dfoo1276 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1208 ; - assign _dfoo1277 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1141 ; - assign _dfoo1278 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1210 ; - assign _dfoo1279 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1143 ; - assign _dfoo128 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo60 ; - assign _dfoo1280 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1212 ; - assign _dfoo1281 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1145 ; - assign _dfoo1282 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1214 ; - assign _dfoo1283 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1147 ; - assign _dfoo1284 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1216 ; - assign _dfoo1285 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1149 ; - assign _dfoo1286 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1218 ; - assign _dfoo1287 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1151 ; - assign _dfoo1288 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1220 ; - assign _dfoo1289 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1153 ; - assign _dfoo1290 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1222 ; - assign _dfoo1291 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1155 ; - assign _dfoo1292 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1224 ; - assign _dfoo1294 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1226 ; - assign _dfoo1296 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1228 ; - assign _dfoo1298 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1230 ; - assign _dfoo13 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo130 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo62 ; - assign _dfoo1300 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1232 ; - assign _dfoo1302 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1234 ; - assign _dfoo1304 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1236 ; - assign _dfoo1306 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1238 ; - assign _dfoo1308 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1240 ; - assign _dfoo1310 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1242 ; - assign _dfoo1312 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1244 ; - assign _dfoo1314 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1246 ; - assign _dfoo1316 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1248 ; - assign _dfoo1318 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1250 ; - assign _dfoo132 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo64 ; - assign _dfoo1320 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1252 ; - assign _dfoo1322 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1254 ; - assign _dfoo1324 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1256 ; - assign _dfoo1326 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1258 ; - assign _dfoo1328 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1260 ; - assign _dfoo1330 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1262 ; - assign _dfoo1332 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1264 ; - assign _dfoo1334 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1266 ; - assign _dfoo1336 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1268 ; - assign _dfoo1338 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1270 ; - assign _dfoo134 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo66 ; - assign _dfoo1340 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1272 ; - assign _dfoo1342 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1274 ; - assign _dfoo1344 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1276 ; - assign _dfoo1346 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1278 ; - assign _dfoo1348 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1280 ; - assign _dfoo1350 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1282 ; - assign _dfoo1352 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1284 ; - assign _dfoo1354 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1286 ; - assign _dfoo1356 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1288 ; - assign _dfoo1358 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1290 ; - assign _dfoo136 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo68 ; - assign _dfoo1360 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1292 ; - assign _dfoo1361 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1225 ; - assign _dfoo1362 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1294 ; - assign _dfoo1363 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1227 ; - assign _dfoo1364 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1296 ; - assign _dfoo1365 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1229 ; - assign _dfoo1366 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1298 ; - assign _dfoo1367 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1231 ; - assign _dfoo1368 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1300 ; - assign _dfoo1369 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1233 ; - assign _dfoo137 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo1 ; - assign _dfoo1370 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1302 ; - assign _dfoo1371 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1235 ; - assign _dfoo1372 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1304 ; - assign _dfoo1373 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1237 ; - assign _dfoo1374 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1306 ; - assign _dfoo1375 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1239 ; - assign _dfoo1376 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1308 ; - assign _dfoo1377 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1241 ; - assign _dfoo1378 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1310 ; - assign _dfoo1379 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1243 ; - assign _dfoo138 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo70 ; - assign _dfoo1380 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1312 ; - assign _dfoo1381 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1245 ; - assign _dfoo1382 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1314 ; - assign _dfoo1383 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1247 ; - assign _dfoo1384 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1316 ; - assign _dfoo1385 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1249 ; - assign _dfoo1386 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1318 ; - assign _dfoo1387 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1251 ; - assign _dfoo1388 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1320 ; - assign _dfoo1389 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1253 ; - assign _dfoo139 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo3 ; - assign _dfoo1390 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1322 ; - assign _dfoo1391 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1255 ; - assign _dfoo1392 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1324 ; - assign _dfoo1393 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1257 ; - assign _dfoo1394 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1326 ; - assign _dfoo1395 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1259 ; - assign _dfoo1396 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1328 ; - assign _dfoo1397 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1261 ; - assign _dfoo1398 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1330 ; - assign _dfoo1399 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1263 ; - assign _dfoo14 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo140 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo72 ; - assign _dfoo1400 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1332 ; - assign _dfoo1401 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1265 ; - assign _dfoo1402 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1334 ; - assign _dfoo1403 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1267 ; - assign _dfoo1404 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1336 ; - assign _dfoo1405 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1269 ; - assign _dfoo1406 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1338 ; - assign _dfoo1407 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1271 ; - assign _dfoo1408 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1340 ; - assign _dfoo1409 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1273 ; - assign _dfoo141 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo5 ; - assign _dfoo1410 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1342 ; - assign _dfoo1411 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1275 ; - assign _dfoo1412 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1344 ; - assign _dfoo1413 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1277 ; - assign _dfoo1414 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1346 ; - assign _dfoo1415 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1279 ; - assign _dfoo1416 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1348 ; - assign _dfoo1417 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1281 ; - assign _dfoo1418 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1350 ; - assign _dfoo1419 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1283 ; - assign _dfoo142 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo74 ; - assign _dfoo1420 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1352 ; - assign _dfoo1421 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1285 ; - assign _dfoo1422 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1354 ; - assign _dfoo1423 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1287 ; - assign _dfoo1424 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1356 ; - assign _dfoo1425 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1289 ; - assign _dfoo1426 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1358 ; - assign _dfoo1427 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1291 ; - assign _dfoo1428 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1360 ; - assign _dfoo143 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo7 ; - assign _dfoo1430 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1362 ; - assign _dfoo1432 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1364 ; - assign _dfoo1434 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1366 ; - assign _dfoo1436 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1368 ; - assign _dfoo1438 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1370 ; - assign _dfoo144 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo76 ; - assign _dfoo1440 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1372 ; - assign _dfoo1442 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1374 ; - assign _dfoo1444 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1376 ; - assign _dfoo1446 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1378 ; - assign _dfoo1448 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1380 ; - assign _dfoo145 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo9 ; - assign _dfoo1450 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1382 ; - assign _dfoo1452 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1384 ; - assign _dfoo1454 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1386 ; - assign _dfoo1456 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1388 ; - assign _dfoo1458 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1390 ; - assign _dfoo146 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo78 ; - assign _dfoo1460 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1392 ; - assign _dfoo1462 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1394 ; - assign _dfoo1464 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1396 ; - assign _dfoo1466 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1398 ; - assign _dfoo1468 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1400 ; - assign _dfoo147 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo11 ; - assign _dfoo1470 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1402 ; - assign _dfoo1472 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1404 ; - assign _dfoo1474 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1406 ; - assign _dfoo1476 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1408 ; - assign _dfoo1478 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1410 ; - assign _dfoo148 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo80 ; - assign _dfoo1480 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1412 ; - assign _dfoo1482 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1414 ; - assign _dfoo1484 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1416 ; - assign _dfoo1486 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1418 ; - assign _dfoo1488 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1420 ; - assign _dfoo149 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo13 ; - assign _dfoo1490 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1422 ; - assign _dfoo1492 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1424 ; - assign _dfoo1494 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1426 ; - assign _dfoo1496 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1428 ; - assign _dfoo1497 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1361 ; - assign _dfoo1498 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1430 ; - assign _dfoo1499 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1363 ; - assign _dfoo15 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo150 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo82 ; - assign _dfoo1500 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1432 ; - assign _dfoo1501 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1365 ; - assign _dfoo1502 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1434 ; - assign _dfoo1503 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1367 ; - assign _dfoo1504 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1436 ; - assign _dfoo1505 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1369 ; - assign _dfoo1506 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1438 ; - assign _dfoo1507 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1371 ; - assign _dfoo1508 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1440 ; - assign _dfoo1509 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1373 ; - assign _dfoo151 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo15 ; - assign _dfoo1510 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1442 ; - assign _dfoo1511 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1375 ; - assign _dfoo1512 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1444 ; - assign _dfoo1513 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1377 ; - assign _dfoo1514 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1446 ; - assign _dfoo1515 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1379 ; - assign _dfoo1516 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1448 ; - assign _dfoo1517 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1381 ; - assign _dfoo1518 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1450 ; - assign _dfoo1519 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1383 ; - assign _dfoo152 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo84 ; - assign _dfoo1520 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1452 ; - assign _dfoo1521 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1385 ; - assign _dfoo1522 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1454 ; - assign _dfoo1523 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1387 ; - assign _dfoo1524 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1456 ; - assign _dfoo1525 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1389 ; - assign _dfoo1526 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1458 ; - assign _dfoo1527 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1391 ; - assign _dfoo1528 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1460 ; - assign _dfoo1529 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1393 ; - assign _dfoo153 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo17 ; - assign _dfoo1530 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1462 ; - assign _dfoo1531 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1395 ; - assign _dfoo1532 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1464 ; - assign _dfoo1533 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1397 ; - assign _dfoo1534 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1466 ; - assign _dfoo1535 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1399 ; - assign _dfoo1536 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1468 ; - assign _dfoo1537 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1401 ; - assign _dfoo1538 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1470 ; - assign _dfoo1539 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1403 ; - assign _dfoo154 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo86 ; - assign _dfoo1540 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1472 ; - assign _dfoo1541 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1405 ; - assign _dfoo1542 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1474 ; - assign _dfoo1543 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1407 ; - assign _dfoo1544 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1476 ; - assign _dfoo1545 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1409 ; - assign _dfoo1546 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1478 ; - assign _dfoo1547 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1411 ; - assign _dfoo1548 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1480 ; - assign _dfoo1549 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1413 ; - assign _dfoo155 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo19 ; - assign _dfoo1550 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1482 ; - assign _dfoo1551 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1415 ; - assign _dfoo1552 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1484 ; - assign _dfoo1553 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1417 ; - assign _dfoo1554 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1486 ; - assign _dfoo1555 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1419 ; - assign _dfoo1556 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1488 ; - assign _dfoo1557 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1421 ; - assign _dfoo1558 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1490 ; - assign _dfoo1559 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1423 ; - assign _dfoo156 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo88 ; - assign _dfoo1560 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1492 ; - assign _dfoo1561 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1425 ; - assign _dfoo1562 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1494 ; - assign _dfoo1563 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1427 ; - assign _dfoo1564 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1496 ; - assign _dfoo1566 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1498 ; - assign _dfoo1568 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1500 ; - assign _dfoo157 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo21 ; - assign _dfoo1570 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1502 ; - assign _dfoo1572 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1504 ; - assign _dfoo1574 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1506 ; - assign _dfoo1576 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1508 ; - assign _dfoo1578 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1510 ; - assign _dfoo158 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo90 ; - assign _dfoo1580 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1512 ; - assign _dfoo1582 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1514 ; - assign _dfoo1584 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1516 ; - assign _dfoo1586 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1518 ; - assign _dfoo1588 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1520 ; - assign _dfoo159 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo23 ; - assign _dfoo1590 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1522 ; - assign _dfoo1592 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1524 ; - assign _dfoo1594 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1526 ; - assign _dfoo1596 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1528 ; - assign _dfoo1598 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1530 ; - assign _dfoo16 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo160 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo92 ; - assign _dfoo1600 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1532 ; - assign _dfoo1602 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1534 ; - assign _dfoo1604 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1536 ; - assign _dfoo1606 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1538 ; - assign _dfoo1608 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1540 ; - assign _dfoo161 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo25 ; - assign _dfoo1610 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1542 ; - assign _dfoo1612 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1544 ; - assign _dfoo1614 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1546 ; - assign _dfoo1616 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1548 ; - assign _dfoo1618 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1550 ; - assign _dfoo162 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo94 ; - assign _dfoo1620 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1552 ; - assign _dfoo1622 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1554 ; - assign _dfoo1624 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1556 ; - assign _dfoo1626 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1558 ; - assign _dfoo1628 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1560 ; - assign _dfoo163 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo27 ; - assign _dfoo1630 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1562 ; - assign _dfoo1632 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1564 ; - assign _dfoo1633 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1497 ; - assign _dfoo1634 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1566 ; - assign _dfoo1635 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1499 ; - assign _dfoo1636 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1568 ; - assign _dfoo1637 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1501 ; - assign _dfoo1638 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1570 ; - assign _dfoo1639 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1503 ; - assign _dfoo164 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo96 ; - assign _dfoo1640 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1572 ; - assign _dfoo1641 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1505 ; - assign _dfoo1642 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1574 ; - assign _dfoo1643 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1507 ; - assign _dfoo1644 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1576 ; - assign _dfoo1645 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1509 ; - assign _dfoo1646 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1578 ; - assign _dfoo1647 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1511 ; - assign _dfoo1648 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1580 ; - assign _dfoo1649 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1513 ; - assign _dfoo165 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo29 ; - assign _dfoo1650 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1582 ; - assign _dfoo1651 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1515 ; - assign _dfoo1652 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1584 ; - assign _dfoo1653 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1517 ; - assign _dfoo1654 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1586 ; - assign _dfoo1655 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1519 ; - assign _dfoo1656 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1588 ; - assign _dfoo1657 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1521 ; - assign _dfoo1658 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1590 ; - assign _dfoo1659 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1523 ; - assign _dfoo166 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo98 ; - assign _dfoo1660 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1592 ; - assign _dfoo1661 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1525 ; - assign _dfoo1662 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1594 ; - assign _dfoo1663 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1527 ; - assign _dfoo1664 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1596 ; - assign _dfoo1665 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1529 ; - assign _dfoo1666 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1598 ; - assign _dfoo1667 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1531 ; - assign _dfoo1668 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1600 ; - assign _dfoo1669 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1533 ; - assign _dfoo167 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo31 ; - assign _dfoo1670 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1602 ; - assign _dfoo1671 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1535 ; - assign _dfoo1672 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1604 ; - assign _dfoo1673 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1537 ; - assign _dfoo1674 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1606 ; - assign _dfoo1675 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1539 ; - assign _dfoo1676 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1608 ; - assign _dfoo1677 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1541 ; - assign _dfoo1678 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1610 ; - assign _dfoo1679 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1543 ; - assign _dfoo168 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo100 ; - assign _dfoo1680 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1612 ; - assign _dfoo1681 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1545 ; - assign _dfoo1682 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1614 ; - assign _dfoo1683 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1547 ; - assign _dfoo1684 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1616 ; - assign _dfoo1685 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1549 ; - assign _dfoo1686 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1618 ; - assign _dfoo1687 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1551 ; - assign _dfoo1688 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1620 ; - assign _dfoo1689 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1553 ; - assign _dfoo169 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo33 ; - assign _dfoo1690 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1622 ; - assign _dfoo1691 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1555 ; - assign _dfoo1692 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1624 ; - assign _dfoo1693 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1557 ; - assign _dfoo1694 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1626 ; - assign _dfoo1695 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1559 ; - assign _dfoo1696 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1628 ; - assign _dfoo1697 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1561 ; - assign _dfoo1698 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1630 ; - assign _dfoo1699 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1563 ; - assign _dfoo17 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo170 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo102 ; - assign _dfoo1700 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1632 ; - assign _dfoo1702 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1634 ; - assign _dfoo1704 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1636 ; - assign _dfoo1706 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1638 ; - assign _dfoo1708 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1640 ; - assign _dfoo171 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo35 ; - assign _dfoo1710 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1642 ; - assign _dfoo1712 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1644 ; - assign _dfoo1714 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1646 ; - assign _dfoo1716 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1648 ; - assign _dfoo1718 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1650 ; - assign _dfoo172 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo104 ; - assign _dfoo1720 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1652 ; - assign _dfoo1722 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1654 ; - assign _dfoo1724 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1656 ; - assign _dfoo1726 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1658 ; - assign _dfoo1728 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1660 ; - assign _dfoo173 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo37 ; - assign _dfoo1730 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1662 ; - assign _dfoo1732 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1664 ; - assign _dfoo1734 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1666 ; - assign _dfoo1736 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1668 ; - assign _dfoo1738 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1670 ; - assign _dfoo174 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo106 ; - assign _dfoo1740 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1672 ; - assign _dfoo1742 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1674 ; - assign _dfoo1744 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1676 ; - assign _dfoo1746 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1678 ; - assign _dfoo1748 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1680 ; - assign _dfoo175 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo39 ; - assign _dfoo1750 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1682 ; - assign _dfoo1752 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1684 ; - assign _dfoo1754 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1686 ; - assign _dfoo1756 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1688 ; - assign _dfoo1758 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1690 ; - assign _dfoo176 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo108 ; - assign _dfoo1760 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1692 ; - assign _dfoo1762 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1694 ; - assign _dfoo1764 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1696 ; - assign _dfoo1766 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1698 ; - assign _dfoo1768 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1700 ; - assign _dfoo1769 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1633 ; - assign _dfoo177 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo41 ; - assign _dfoo1770 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1702 ; - assign _dfoo1771 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1635 ; - assign _dfoo1772 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1704 ; - assign _dfoo1773 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1637 ; - assign _dfoo1774 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1706 ; - assign _dfoo1775 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1639 ; - assign _dfoo1776 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1708 ; - assign _dfoo1777 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1641 ; - assign _dfoo1778 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1710 ; - assign _dfoo1779 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1643 ; - assign _dfoo178 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo110 ; - assign _dfoo1780 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1712 ; - assign _dfoo1781 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1645 ; - assign _dfoo1782 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1714 ; - assign _dfoo1783 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1647 ; - assign _dfoo1784 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1716 ; - assign _dfoo1785 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1649 ; - assign _dfoo1786 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1718 ; - assign _dfoo1787 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1651 ; - assign _dfoo1788 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1720 ; - assign _dfoo1789 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1653 ; - assign _dfoo179 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo43 ; - assign _dfoo1790 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1722 ; - assign _dfoo1791 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1655 ; - assign _dfoo1792 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1724 ; - assign _dfoo1793 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1657 ; - assign _dfoo1794 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1726 ; - assign _dfoo1795 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1659 ; - assign _dfoo1796 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1728 ; - assign _dfoo1797 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1661 ; - assign _dfoo1798 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1730 ; - assign _dfoo1799 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1663 ; - assign _dfoo18 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo180 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo112 ; - assign _dfoo1800 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1732 ; - assign _dfoo1801 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1665 ; - assign _dfoo1802 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1734 ; - assign _dfoo1803 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1667 ; - assign _dfoo1804 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1736 ; - assign _dfoo1805 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1669 ; - assign _dfoo1806 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1738 ; - assign _dfoo1807 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1671 ; - assign _dfoo1808 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1740 ; - assign _dfoo1809 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1673 ; - assign _dfoo181 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo45 ; - assign _dfoo1810 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1742 ; - assign _dfoo1811 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1675 ; - assign _dfoo1812 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1744 ; - assign _dfoo1813 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1677 ; - assign _dfoo1814 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1746 ; - assign _dfoo1815 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1679 ; - assign _dfoo1816 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1748 ; - assign _dfoo1817 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1681 ; - assign _dfoo1818 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1750 ; - assign _dfoo1819 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1683 ; - assign _dfoo182 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo114 ; - assign _dfoo1820 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1752 ; - assign _dfoo1821 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1685 ; - assign _dfoo1822 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1754 ; - assign _dfoo1823 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1687 ; - assign _dfoo1824 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1756 ; - assign _dfoo1825 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1689 ; - assign _dfoo1826 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1758 ; - assign _dfoo1827 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1691 ; - assign _dfoo1828 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1760 ; - assign _dfoo1829 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1693 ; - assign _dfoo183 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo47 ; - assign _dfoo1830 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1762 ; - assign _dfoo1831 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1695 ; - assign _dfoo1832 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1764 ; - assign _dfoo1833 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1697 ; - assign _dfoo1834 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1766 ; - assign _dfoo1835 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1699 ; - assign _dfoo1836 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1768 ; - assign _dfoo1838 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1770 ; - assign _dfoo184 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo116 ; - assign _dfoo1840 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1772 ; - assign _dfoo1842 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1774 ; - assign _dfoo1844 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1776 ; - assign _dfoo1846 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1778 ; - assign _dfoo1848 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1780 ; - assign _dfoo185 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo49 ; - assign _dfoo1850 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1782 ; - assign _dfoo1852 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1784 ; - assign _dfoo1854 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1786 ; - assign _dfoo1856 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1788 ; - assign _dfoo1858 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1790 ; - assign _dfoo186 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo118 ; - assign _dfoo1860 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1792 ; - assign _dfoo1862 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1794 ; - assign _dfoo1864 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1796 ; - assign _dfoo1866 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1798 ; - assign _dfoo1868 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1800 ; - assign _dfoo187 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo51 ; - assign _dfoo1870 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1802 ; - assign _dfoo1872 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1804 ; - assign _dfoo1874 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1806 ; - assign _dfoo1876 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1808 ; - assign _dfoo1878 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1810 ; - assign _dfoo188 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo120 ; - assign _dfoo1880 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1812 ; - assign _dfoo1882 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1814 ; - assign _dfoo1884 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1816 ; - assign _dfoo1886 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1818 ; - assign _dfoo1888 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1820 ; - assign _dfoo189 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo53 ; - assign _dfoo1890 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1822 ; - assign _dfoo1892 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1824 ; - assign _dfoo1894 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1826 ; - assign _dfoo1896 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1828 ; - assign _dfoo1898 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1830 ; - assign _dfoo19 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo190 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo122 ; - assign _dfoo1900 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1832 ; - assign _dfoo1902 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1834 ; - assign _dfoo1904 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1836 ; - assign _dfoo1905 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1769 ; - assign _dfoo1906 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1838 ; - assign _dfoo1907 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1771 ; - assign _dfoo1908 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1840 ; - assign _dfoo1909 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1773 ; - assign _dfoo191 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo55 ; - assign _dfoo1910 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1842 ; - assign _dfoo1911 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1775 ; - assign _dfoo1912 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1844 ; - assign _dfoo1913 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1777 ; - assign _dfoo1914 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1846 ; - assign _dfoo1915 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1779 ; - assign _dfoo1916 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1848 ; - assign _dfoo1917 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1781 ; - assign _dfoo1918 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1850 ; - assign _dfoo1919 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1783 ; - assign _dfoo192 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo124 ; - assign _dfoo1920 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1852 ; - assign _dfoo1921 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1785 ; - assign _dfoo1922 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1854 ; - assign _dfoo1923 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1787 ; - assign _dfoo1924 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1856 ; - assign _dfoo1925 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1789 ; - assign _dfoo1926 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1858 ; - assign _dfoo1927 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1791 ; - assign _dfoo1928 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1860 ; - assign _dfoo1929 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1793 ; - assign _dfoo193 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo57 ; - assign _dfoo1930 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1862 ; - assign _dfoo1931 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1795 ; - assign _dfoo1932 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1864 ; - assign _dfoo1933 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1797 ; - assign _dfoo1934 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1866 ; - assign _dfoo1935 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1799 ; - assign _dfoo1936 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1868 ; - assign _dfoo1937 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1801 ; - assign _dfoo1938 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1870 ; - assign _dfoo1939 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1803 ; - assign _dfoo194 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo126 ; - assign _dfoo1940 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1872 ; - assign _dfoo1941 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1805 ; - assign _dfoo1942 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1874 ; - assign _dfoo1943 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1807 ; - assign _dfoo1944 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1876 ; - assign _dfoo1945 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1809 ; - assign _dfoo1946 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1878 ; - assign _dfoo1947 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1811 ; - assign _dfoo1948 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1880 ; - assign _dfoo1949 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1813 ; - assign _dfoo195 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo59 ; - assign _dfoo1950 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1882 ; - assign _dfoo1951 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1815 ; - assign _dfoo1952 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1884 ; - assign _dfoo1953 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1817 ; - assign _dfoo1954 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1886 ; - assign _dfoo1955 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1819 ; - assign _dfoo1956 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1888 ; - assign _dfoo1957 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1821 ; - assign _dfoo1958 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1890 ; - assign _dfoo1959 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1823 ; - assign _dfoo196 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo128 ; - assign _dfoo1960 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1892 ; - assign _dfoo1961 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1825 ; - assign _dfoo1962 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1894 ; - assign _dfoo1963 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1827 ; - assign _dfoo1964 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1896 ; - assign _dfoo1965 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1829 ; - assign _dfoo1966 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1898 ; - assign _dfoo1967 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1831 ; - assign _dfoo1968 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1900 ; - assign _dfoo1969 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1833 ; - assign _dfoo197 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo61 ; - assign _dfoo1970 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1902 ; - assign _dfoo1971 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1835 ; - assign _dfoo1972 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1904 ; - assign _dfoo1974 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1906 ; - assign _dfoo1976 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1908 ; - assign _dfoo1978 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1910 ; - assign _dfoo198 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo130 ; - assign _dfoo1980 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1912 ; - assign _dfoo1982 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1914 ; - assign _dfoo1984 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1916 ; - assign _dfoo1986 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1918 ; - assign _dfoo1988 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1920 ; - assign _dfoo199 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo63 ; - assign _dfoo1990 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1922 ; - assign _dfoo1992 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1924 ; - assign _dfoo1994 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1926 ; - assign _dfoo1996 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1928 ; - assign _dfoo1998 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1930 ; - assign _dfoo2 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo20 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo200 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo132 ; - assign _dfoo2000 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1932 ; - assign _dfoo2002 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1934 ; - assign _dfoo2004 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1936 ; - assign _dfoo2006 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1938 ; - assign _dfoo2008 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1940 ; - assign _dfoo201 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo65 ; - assign _dfoo2010 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1942 ; - assign _dfoo2012 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1944 ; - assign _dfoo2014 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1946 ; - assign _dfoo2016 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1948 ; - assign _dfoo2018 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1950 ; - assign _dfoo202 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo134 ; - assign _dfoo2020 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1952 ; - assign _dfoo2022 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1954 ; - assign _dfoo2024 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1956 ; - assign _dfoo2026 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1958 ; - assign _dfoo2028 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1960 ; - assign _dfoo203 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo67 ; - assign _dfoo2030 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1962 ; - assign _dfoo2032 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1964 ; - assign _dfoo2034 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1966 ; - assign _dfoo2036 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1968 ; - assign _dfoo2038 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1970 ; - assign _dfoo204 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo136 ; - assign _dfoo2040 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1972 ; - assign _dfoo2041 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1905 ; - assign _dfoo2043 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1907 ; - assign _dfoo2045 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1909 ; - assign _dfoo2047 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1911 ; - assign _dfoo2049 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1913 ; - assign _dfoo2051 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1915 ; - assign _dfoo2053 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1917 ; - assign _dfoo2055 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1919 ; - assign _dfoo2057 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1921 ; - assign _dfoo2059 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1923 ; - assign _dfoo206 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo138 ; - assign _dfoo2061 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1925 ; - assign _dfoo2063 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1927 ; - assign _dfoo2065 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1929 ; - assign _dfoo2067 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1931 ; - assign _dfoo2069 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1933 ; - assign _dfoo2071 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1935 ; - assign _dfoo2073 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1937 ; - assign _dfoo2075 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1939 ; - assign _dfoo2077 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1941 ; - assign _dfoo2079 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1943 ; - assign _dfoo208 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo140 ; - assign _dfoo2081 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1945 ; - assign _dfoo2083 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1947 ; - assign _dfoo2085 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1949 ; - assign _dfoo2087 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1951 ; - assign _dfoo2089 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1953 ; - assign _dfoo2091 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1955 ; - assign _dfoo2093 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1957 ; - assign _dfoo2095 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1959 ; - assign _dfoo2097 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1961 ; - assign _dfoo2099 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1963 ; - assign _dfoo21 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo210 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo142 ; - assign _dfoo2101 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1965 ; - assign _dfoo2103 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1967 ; - assign _dfoo2105 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1969 ; - assign _dfoo2107 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1971 ; - assign _dfoo212 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo144 ; - assign _dfoo214 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo146 ; - assign _dfoo216 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo148 ; - assign _dfoo218 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo150 ; - assign _dfoo22 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo220 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo152 ; - assign _dfoo222 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo154 ; - assign _dfoo224 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo156 ; - assign _dfoo226 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo158 ; - assign _dfoo228 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo160 ; - assign _dfoo23 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo230 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo162 ; - assign _dfoo232 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo164 ; - assign _dfoo234 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo166 ; - assign _dfoo236 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo168 ; - assign _dfoo238 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo170 ; - assign _dfoo24 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo240 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo172 ; - assign _dfoo242 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo174 ; - assign _dfoo244 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo176 ; - assign _dfoo246 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo178 ; - assign _dfoo248 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo180 ; - assign _dfoo25 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo250 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo182 ; - assign _dfoo252 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo184 ; - assign _dfoo254 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo186 ; - assign _dfoo256 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo188 ; - assign _dfoo258 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo190 ; - assign _dfoo26 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo260 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo192 ; - assign _dfoo262 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo194 ; - assign _dfoo264 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo196 ; - assign _dfoo266 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo198 ; - assign _dfoo268 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo200 ; - assign _dfoo27 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo270 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo202 ; - assign _dfoo272 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo204 ; - assign _dfoo273 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo137 ; - assign _dfoo274 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo206 ; - assign _dfoo275 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo139 ; - assign _dfoo276 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo208 ; - assign _dfoo277 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo141 ; - assign _dfoo278 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo210 ; - assign _dfoo279 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo143 ; - assign _dfoo28 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo280 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo212 ; - assign _dfoo281 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo145 ; - assign _dfoo282 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo214 ; - assign _dfoo283 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo147 ; - assign _dfoo284 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo216 ; - assign _dfoo285 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo149 ; - assign _dfoo286 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo218 ; - assign _dfoo287 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo151 ; - assign _dfoo288 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo220 ; - assign _dfoo289 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo153 ; - assign _dfoo29 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo290 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo222 ; - assign _dfoo291 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo155 ; - assign _dfoo292 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo224 ; - assign _dfoo293 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo157 ; - assign _dfoo294 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo226 ; - assign _dfoo295 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo159 ; - assign _dfoo296 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo228 ; - assign _dfoo297 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo161 ; - assign _dfoo298 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo230 ; - assign _dfoo299 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo163 ; - assign _dfoo3 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo30 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo300 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo232 ; - assign _dfoo301 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo165 ; - assign _dfoo302 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo234 ; - assign _dfoo303 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo167 ; - assign _dfoo304 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo236 ; - assign _dfoo305 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo169 ; - assign _dfoo306 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo238 ; - assign _dfoo307 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo171 ; - assign _dfoo308 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo240 ; - assign _dfoo309 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo173 ; - assign _dfoo31 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo310 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo242 ; - assign _dfoo311 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo175 ; - assign _dfoo312 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo244 ; - assign _dfoo313 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo177 ; - assign _dfoo314 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo246 ; - assign _dfoo315 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo179 ; - assign _dfoo316 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo248 ; - assign _dfoo317 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo181 ; - assign _dfoo318 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo250 ; - assign _dfoo319 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo183 ; - assign _dfoo32 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo320 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo252 ; - assign _dfoo321 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo185 ; - assign _dfoo322 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo254 ; - assign _dfoo323 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo187 ; - assign _dfoo324 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo256 ; - assign _dfoo325 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo189 ; - assign _dfoo326 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo258 ; - assign _dfoo327 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo191 ; - assign _dfoo328 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo260 ; - assign _dfoo329 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo193 ; - assign _dfoo33 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo330 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo262 ; - assign _dfoo331 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo195 ; - assign _dfoo332 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo264 ; - assign _dfoo333 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo197 ; - assign _dfoo334 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo266 ; - assign _dfoo335 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo199 ; - assign _dfoo336 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo268 ; - assign _dfoo337 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo201 ; - assign _dfoo338 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo270 ; - assign _dfoo339 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo203 ; - assign _dfoo34 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo340 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo272 ; - assign _dfoo342 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo274 ; - assign _dfoo344 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo276 ; - assign _dfoo346 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo278 ; - assign _dfoo348 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo280 ; - assign _dfoo35 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo350 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo282 ; - assign _dfoo352 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo284 ; - assign _dfoo354 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo286 ; - assign _dfoo356 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo288 ; - assign _dfoo358 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo290 ; - assign _dfoo36 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo360 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo292 ; - assign _dfoo362 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo294 ; - assign _dfoo364 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo296 ; - assign _dfoo366 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo298 ; - assign _dfoo368 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo300 ; - assign _dfoo37 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo370 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo302 ; - assign _dfoo372 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo304 ; - assign _dfoo374 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo306 ; - assign _dfoo376 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo308 ; - assign _dfoo378 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo310 ; - assign _dfoo38 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo380 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo312 ; - assign _dfoo382 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo314 ; - assign _dfoo384 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo316 ; - assign _dfoo386 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo318 ; - assign _dfoo388 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo320 ; - assign _dfoo39 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo390 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo322 ; - assign _dfoo392 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo324 ; - assign _dfoo394 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo326 ; - assign _dfoo396 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo328 ; - assign _dfoo398 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo330 ; - assign _dfoo4 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo40 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo400 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo332 ; - assign _dfoo402 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo334 ; - assign _dfoo404 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo336 ; - assign _dfoo406 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo338 ; - assign _dfoo408 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo340 ; - assign _dfoo409 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo273 ; - assign _dfoo41 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo410 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo342 ; - assign _dfoo411 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo275 ; - assign _dfoo412 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo344 ; - assign _dfoo413 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo277 ; - assign _dfoo414 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo346 ; - assign _dfoo415 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo279 ; - assign _dfoo416 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo348 ; - assign _dfoo417 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo281 ; - assign _dfoo418 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo350 ; - assign _dfoo419 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo283 ; - assign _dfoo42 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo420 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo352 ; - assign _dfoo421 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo285 ; - assign _dfoo422 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo354 ; - assign _dfoo423 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo287 ; - assign _dfoo424 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo356 ; - assign _dfoo425 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo289 ; - assign _dfoo426 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo358 ; - assign _dfoo427 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo291 ; - assign _dfoo428 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo360 ; - assign _dfoo429 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo293 ; - assign _dfoo43 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo430 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo362 ; - assign _dfoo431 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo295 ; - assign _dfoo432 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo364 ; - assign _dfoo433 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo297 ; - assign _dfoo434 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo366 ; - assign _dfoo435 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo299 ; - assign _dfoo436 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo368 ; - assign _dfoo437 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo301 ; - assign _dfoo438 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo370 ; - assign _dfoo439 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo303 ; - assign _dfoo44 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo440 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo372 ; - assign _dfoo441 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo305 ; - assign _dfoo442 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo374 ; - assign _dfoo443 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo307 ; - assign _dfoo444 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo376 ; - assign _dfoo445 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo309 ; - assign _dfoo446 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo378 ; - assign _dfoo447 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo311 ; - assign _dfoo448 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo380 ; - assign _dfoo449 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo313 ; - assign _dfoo45 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo450 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo382 ; - assign _dfoo451 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo315 ; - assign _dfoo452 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo384 ; - assign _dfoo453 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo317 ; - assign _dfoo454 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo386 ; - assign _dfoo455 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo319 ; - assign _dfoo456 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo388 ; - assign _dfoo457 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo321 ; - assign _dfoo458 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo390 ; - assign _dfoo459 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo323 ; - assign _dfoo46 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo460 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo392 ; - assign _dfoo461 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo325 ; - assign _dfoo462 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo394 ; - assign _dfoo463 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo327 ; - assign _dfoo464 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo396 ; - assign _dfoo465 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo329 ; - assign _dfoo466 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo398 ; - assign _dfoo467 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo331 ; - assign _dfoo468 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo400 ; - assign _dfoo469 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo333 ; - assign _dfoo47 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo470 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo402 ; - assign _dfoo471 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo335 ; - assign _dfoo472 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo404 ; - assign _dfoo473 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo337 ; - assign _dfoo474 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo406 ; - assign _dfoo475 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo339 ; - assign _dfoo476 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo408 ; - assign _dfoo478 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo410 ; - assign _dfoo48 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo480 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo412 ; - assign _dfoo482 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo414 ; - assign _dfoo484 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo416 ; - assign _dfoo486 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo418 ; - assign _dfoo488 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo420 ; - assign _dfoo49 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo490 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo422 ; - assign _dfoo492 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo424 ; - assign _dfoo494 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo426 ; - assign _dfoo496 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo428 ; - assign _dfoo498 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo430 ; - assign _dfoo5 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo50 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo500 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo432 ; - assign _dfoo502 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo434 ; - assign _dfoo504 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo436 ; - assign _dfoo506 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo438 ; - assign _dfoo508 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo440 ; - assign _dfoo51 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo510 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo442 ; - assign _dfoo512 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo444 ; - assign _dfoo514 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo446 ; - assign _dfoo516 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo448 ; - assign _dfoo518 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo450 ; - assign _dfoo52 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo520 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo452 ; - assign _dfoo522 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo454 ; - assign _dfoo524 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo456 ; - assign _dfoo526 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo458 ; - assign _dfoo528 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo460 ; - assign _dfoo53 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo530 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo462 ; - assign _dfoo532 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo464 ; - assign _dfoo534 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo466 ; - assign _dfoo536 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo468 ; - assign _dfoo538 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo470 ; - assign _dfoo54 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo540 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo472 ; - assign _dfoo542 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo474 ; - assign _dfoo544 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo476 ; - assign _dfoo545 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo409 ; - assign _dfoo546 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo478 ; - assign _dfoo547 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo411 ; - assign _dfoo548 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo480 ; - assign _dfoo549 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo413 ; - assign _dfoo55 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo550 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo482 ; - assign _dfoo551 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo415 ; - assign _dfoo552 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo484 ; - assign _dfoo553 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo417 ; - assign _dfoo554 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo486 ; - assign _dfoo555 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo419 ; - assign _dfoo556 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo488 ; - assign _dfoo557 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo421 ; - assign _dfoo558 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo490 ; - assign _dfoo559 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo423 ; - assign _dfoo56 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo560 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo492 ; - assign _dfoo561 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo425 ; - assign _dfoo562 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo494 ; - assign _dfoo563 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo427 ; - assign _dfoo564 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo496 ; - assign _dfoo565 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo429 ; - assign _dfoo566 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo498 ; - assign _dfoo567 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo431 ; - assign _dfoo568 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo500 ; - assign _dfoo569 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo433 ; - assign _dfoo57 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo570 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo502 ; - assign _dfoo571 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo435 ; - assign _dfoo572 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo504 ; - assign _dfoo573 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo437 ; - assign _dfoo574 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo506 ; - assign _dfoo575 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo439 ; - assign _dfoo576 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo508 ; - assign _dfoo577 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo441 ; - assign _dfoo578 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo510 ; - assign _dfoo579 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo443 ; - assign _dfoo58 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo580 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo512 ; - assign _dfoo581 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo445 ; - assign _dfoo582 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo514 ; - assign _dfoo583 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo447 ; - assign _dfoo584 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo516 ; - assign _dfoo585 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo449 ; - assign _dfoo586 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo518 ; - assign _dfoo587 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo451 ; - assign _dfoo588 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo520 ; - assign _dfoo589 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo453 ; - assign _dfoo59 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo590 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo522 ; - assign _dfoo591 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo455 ; - assign _dfoo592 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo524 ; - assign _dfoo593 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo457 ; - assign _dfoo594 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo526 ; - assign _dfoo595 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo459 ; - assign _dfoo596 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo528 ; - assign _dfoo597 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo461 ; - assign _dfoo598 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo530 ; - assign _dfoo599 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo463 ; - assign _dfoo6 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo60 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo600 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo532 ; - assign _dfoo601 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo465 ; - assign _dfoo602 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo534 ; - assign _dfoo603 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo467 ; - assign _dfoo604 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo536 ; - assign _dfoo605 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo469 ; - assign _dfoo606 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo538 ; - assign _dfoo607 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo471 ; - assign _dfoo608 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo540 ; - assign _dfoo609 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo473 ; - assign _dfoo61 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo610 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo542 ; - assign _dfoo611 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo475 ; - assign _dfoo612 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo544 ; - assign _dfoo614 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo546 ; - assign _dfoo616 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo548 ; - assign _dfoo618 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo550 ; - assign _dfoo62 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo620 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo552 ; - assign _dfoo622 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo554 ; - assign _dfoo624 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo556 ; - assign _dfoo626 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo558 ; - assign _dfoo628 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo560 ; - assign _dfoo63 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo630 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo562 ; - assign _dfoo632 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo564 ; - assign _dfoo634 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo566 ; - assign _dfoo636 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo568 ; - assign _dfoo638 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo570 ; - assign _dfoo64 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo640 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo572 ; - assign _dfoo642 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo574 ; - assign _dfoo644 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo576 ; - assign _dfoo646 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo578 ; - assign _dfoo648 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo580 ; - assign _dfoo65 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo650 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo582 ; - assign _dfoo652 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo584 ; - assign _dfoo654 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo586 ; - assign _dfoo656 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo588 ; - assign _dfoo658 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo590 ; - assign _dfoo66 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo660 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo592 ; - assign _dfoo662 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo594 ; - assign _dfoo664 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo596 ; - assign _dfoo666 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo598 ; - assign _dfoo668 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo600 ; - assign _dfoo67 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo670 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo602 ; - assign _dfoo672 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo604 ; - assign _dfoo674 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo606 ; - assign _dfoo676 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo608 ; - assign _dfoo678 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo610 ; - assign _dfoo68 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo680 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo612 ; - assign _dfoo681 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo545 ; - assign _dfoo682 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo614 ; - assign _dfoo683 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo547 ; - assign _dfoo684 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo616 ; - assign _dfoo685 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo549 ; - assign _dfoo686 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo618 ; - assign _dfoo687 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo551 ; - assign _dfoo688 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo620 ; - assign _dfoo689 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo553 ; - assign _dfoo690 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo622 ; - assign _dfoo691 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo555 ; - assign _dfoo692 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo624 ; - assign _dfoo693 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo557 ; - assign _dfoo694 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo626 ; - assign _dfoo695 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo559 ; - assign _dfoo696 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo628 ; - assign _dfoo697 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo561 ; - assign _dfoo698 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo630 ; - assign _dfoo699 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo563 ; - assign _dfoo7 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo70 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo2 ; - assign _dfoo700 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo632 ; - assign _dfoo701 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo565 ; - assign _dfoo702 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo634 ; - assign _dfoo703 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo567 ; - assign _dfoo704 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo636 ; - assign _dfoo705 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo569 ; - assign _dfoo706 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo638 ; - assign _dfoo707 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo571 ; - assign _dfoo708 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo640 ; - assign _dfoo709 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo573 ; - assign _dfoo710 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo642 ; - assign _dfoo711 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo575 ; - assign _dfoo712 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo644 ; - assign _dfoo713 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo577 ; - assign _dfoo714 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo646 ; - assign _dfoo715 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo579 ; - assign _dfoo716 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo648 ; - assign _dfoo717 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo581 ; - assign _dfoo718 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo650 ; - assign _dfoo719 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo583 ; - assign _dfoo72 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo4 ; - assign _dfoo720 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo652 ; - assign _dfoo721 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo585 ; - assign _dfoo722 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo654 ; - assign _dfoo723 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo587 ; - assign _dfoo724 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo656 ; - assign _dfoo725 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo589 ; - assign _dfoo726 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo658 ; - assign _dfoo727 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo591 ; - assign _dfoo728 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo660 ; - assign _dfoo729 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo593 ; - assign _dfoo730 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo662 ; - assign _dfoo731 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo595 ; - assign _dfoo732 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo664 ; - assign _dfoo733 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo597 ; - assign _dfoo734 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo666 ; - assign _dfoo735 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo599 ; - assign _dfoo736 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo668 ; - assign _dfoo737 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo601 ; - assign _dfoo738 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo670 ; - assign _dfoo739 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo603 ; - assign _dfoo74 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo6 ; - assign _dfoo740 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo672 ; - assign _dfoo741 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo605 ; - assign _dfoo742 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo674 ; - assign _dfoo743 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo607 ; - assign _dfoo744 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo676 ; - assign _dfoo745 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo609 ; - assign _dfoo746 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo678 ; - assign _dfoo747 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo611 ; - assign _dfoo748 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo680 ; - assign _dfoo750 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo682 ; - assign _dfoo752 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo684 ; - assign _dfoo754 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo686 ; - assign _dfoo756 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo688 ; - assign _dfoo758 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo690 ; - assign _dfoo76 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo8 ; - assign _dfoo760 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo692 ; - assign _dfoo762 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo694 ; - assign _dfoo764 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo696 ; - assign _dfoo766 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo698 ; - assign _dfoo768 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo700 ; - assign _dfoo770 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo702 ; - assign _dfoo772 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo704 ; - assign _dfoo774 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo706 ; - assign _dfoo776 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo708 ; - assign _dfoo778 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo710 ; - assign _dfoo78 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo10 ; - assign _dfoo780 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo712 ; - assign _dfoo782 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo714 ; - assign _dfoo784 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo716 ; - assign _dfoo786 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo718 ; - assign _dfoo788 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo720 ; - assign _dfoo790 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo722 ; - assign _dfoo792 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo724 ; - assign _dfoo794 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo726 ; - assign _dfoo796 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo728 ; - assign _dfoo798 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo730 ; - assign _dfoo8 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo80 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo12 ; - assign _dfoo800 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo732 ; - assign _dfoo802 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo734 ; - assign _dfoo804 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo736 ; - assign _dfoo806 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo738 ; - assign _dfoo808 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo740 ; - assign _dfoo810 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo742 ; - assign _dfoo812 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo744 ; - assign _dfoo814 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo746 ; - assign _dfoo816 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo748 ; - assign _dfoo817 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo681 ; - assign _dfoo818 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo750 ; - assign _dfoo819 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo683 ; - assign _dfoo82 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo14 ; - assign _dfoo820 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo752 ; - assign _dfoo821 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo685 ; - assign _dfoo822 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo754 ; - assign _dfoo823 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo687 ; - assign _dfoo824 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo756 ; - assign _dfoo825 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo689 ; - assign _dfoo826 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo758 ; - assign _dfoo827 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo691 ; - assign _dfoo828 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo760 ; - assign _dfoo829 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo693 ; - assign _dfoo830 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo762 ; - assign _dfoo831 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo695 ; - assign _dfoo832 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo764 ; - assign _dfoo833 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo697 ; - assign _dfoo834 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo766 ; - assign _dfoo835 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo699 ; - assign _dfoo836 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo768 ; - assign _dfoo837 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo701 ; - assign _dfoo838 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo770 ; - assign _dfoo839 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo703 ; - assign _dfoo84 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo16 ; - assign _dfoo840 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo772 ; - assign _dfoo841 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo705 ; - assign _dfoo842 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo774 ; - assign _dfoo843 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo707 ; - assign _dfoo844 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo776 ; - assign _dfoo845 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo709 ; - assign _dfoo846 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo778 ; - assign _dfoo847 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo711 ; - assign _dfoo848 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo780 ; - assign _dfoo849 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo713 ; - assign _dfoo850 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo782 ; - assign _dfoo851 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo715 ; - assign _dfoo852 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo784 ; - assign _dfoo853 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo717 ; - assign _dfoo854 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo786 ; - assign _dfoo855 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo719 ; - assign _dfoo856 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo788 ; - assign _dfoo857 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo721 ; - assign _dfoo858 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo790 ; - assign _dfoo859 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo723 ; - assign _dfoo86 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo18 ; - assign _dfoo860 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo792 ; - assign _dfoo861 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo725 ; - assign _dfoo862 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo794 ; - assign _dfoo863 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo727 ; - assign _dfoo864 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo796 ; - assign _dfoo865 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo729 ; - assign _dfoo866 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo798 ; - assign _dfoo867 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo731 ; - assign _dfoo868 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo800 ; - assign _dfoo869 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo733 ; - assign _dfoo870 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo802 ; - assign _dfoo871 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo735 ; - assign _dfoo872 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo804 ; - assign _dfoo873 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo737 ; - assign _dfoo874 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo806 ; - assign _dfoo875 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo739 ; - assign _dfoo876 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo808 ; - assign _dfoo877 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo741 ; - assign _dfoo878 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo810 ; - assign _dfoo879 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo743 ; - assign _dfoo88 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo20 ; - assign _dfoo880 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo812 ; - assign _dfoo881 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo745 ; - assign _dfoo882 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo814 ; - assign _dfoo883 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo747 ; - assign _dfoo884 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo816 ; - assign _dfoo886 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo818 ; - assign _dfoo888 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo820 ; - assign _dfoo890 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo822 ; - assign _dfoo892 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo824 ; - assign _dfoo894 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo826 ; - assign _dfoo896 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo828 ; - assign _dfoo898 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo830 ; - assign _dfoo9 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo90 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo22 ; - assign _dfoo900 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo832 ; - assign _dfoo902 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo834 ; - assign _dfoo904 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo836 ; - assign _dfoo906 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo838 ; - assign _dfoo908 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo840 ; - assign _dfoo910 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo842 ; - assign _dfoo912 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo844 ; - assign _dfoo914 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo846 ; - assign _dfoo916 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo848 ; - assign _dfoo918 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo850 ; - assign _dfoo92 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo24 ; - assign _dfoo920 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo852 ; - assign _dfoo922 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo854 ; - assign _dfoo924 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo856 ; - assign _dfoo926 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo858 ; - assign _dfoo928 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo860 ; - assign _dfoo930 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo862 ; - assign _dfoo932 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo864 ; - assign _dfoo934 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo866 ; - assign _dfoo936 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo868 ; - assign _dfoo938 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo870 ; - assign _dfoo94 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo26 ; - assign _dfoo940 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo872 ; - assign _dfoo942 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo874 ; - assign _dfoo944 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo876 ; - assign _dfoo946 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo878 ; - assign _dfoo948 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo880 ; - assign _dfoo950 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo882 ; - assign _dfoo952 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo884 ; - assign _dfoo953 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo817 ; - assign _dfoo954 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo886 ; - assign _dfoo955 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo819 ; - assign _dfoo956 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo888 ; - assign _dfoo957 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo821 ; - assign _dfoo958 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo890 ; - assign _dfoo959 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo823 ; - assign _dfoo96 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo28 ; - assign _dfoo960 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo892 ; - assign _dfoo961 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo825 ; - assign _dfoo962 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo894 ; - assign _dfoo963 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo827 ; - assign _dfoo964 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo896 ; - assign _dfoo965 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo829 ; - assign _dfoo966 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo898 ; - assign _dfoo967 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo831 ; - assign _dfoo968 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo900 ; - assign _dfoo969 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo833 ; - assign _dfoo970 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo902 ; - assign _dfoo971 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo835 ; - assign _dfoo972 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo904 ; - assign _dfoo973 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo837 ; - assign _dfoo974 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo906 ; - assign _dfoo975 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo839 ; - assign _dfoo976 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo908 ; - assign _dfoo977 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo841 ; - assign _dfoo978 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo910 ; - assign _dfoo979 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo843 ; - assign _dfoo98 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo30 ; - assign _dfoo980 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo912 ; - assign _dfoo981 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo845 ; - assign _dfoo982 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo914 ; - assign _dfoo983 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo847 ; - assign _dfoo984 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo916 ; - assign _dfoo985 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo849 ; - assign _dfoo986 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo918 ; - assign _dfoo987 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo851 ; - assign _dfoo988 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo920 ; - assign _dfoo989 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo853 ; - assign _dfoo990 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo922 ; - assign _dfoo991 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo855 ; - assign _dfoo992 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo924 ; - assign _dfoo993 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo857 ; - assign _dfoo994 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo926 ; - assign _dfoo995 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo859 ; - assign _dfoo996 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo928 ; - assign _dfoo997 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo861 ; - assign _dfoo998 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo930 ; - assign _dfoo999 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo863 ; - assign a__h71312 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73317 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; - assign addr_offset__h13216 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26929 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71313 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73318 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = - addr_offset__h13216 < 64'h0000000000003000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = - addr_offset__h13216[11:7] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 = - addr_offset__h13216 < 64'h0000000000001000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 = - addr_offset__h13216[11:2] <= 10'd16 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 = - addr_offset__h13216[16:12] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 = - addr_offset__h13216 < 64'h0000000000002000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = - source_id_base__h13630 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26929[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26929[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26929[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26929 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26929[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26929[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26929[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26929[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26929[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26929[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26929[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26929[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26929[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26929[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26929[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26929[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26929[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26929[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26929[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26929[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26929[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26929 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28148 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26929 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26929[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26929[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26929[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && - m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && - m_vvrg_ie_1_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && - m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && - m_vvrg_ie_1_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && - m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && - m_vvrg_ie_1_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && - m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && - m_vvrg_ie_1_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 || - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 || - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 || - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 || - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && - m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && - m_vvrg_ie_1_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && - m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && - m_vvrg_ie_1_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && - m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && - m_vvrg_ie_1_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = - m_vrg_source_ip_16 && - !m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 || - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 || - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 || - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 ; - assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = - m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && - m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && - m_vvrg_ie_1_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && - m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && - m_vvrg_ie_1_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && - m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && - m_vvrg_ie_1_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && - m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && - m_vvrg_ie_1_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && - m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && - m_vvrg_ie_1_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && - m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && - m_vvrg_ie_1_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 || - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 || - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 || - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 || - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && - m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && - m_vvrg_ie_1_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && - m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && - m_vvrg_ie_1_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; - assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 = - m_vrg_source_prio_16 <= - (m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ; - assign max_id__h23959 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ; - assign rdata___1__h26404 = { rdata__h26202[31:0], 32'h0 } ; - assign rdata__h26202 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 64'd0 : - y_avValue_fst__h26194 ; - assign rresp__h26203 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 2'b11 : - y_avValue_snd__h26195 ; - assign source_id__h15665 = { addr_offset__h13216[4:0], 5'd31 } ; - assign source_id__h15772 = { addr_offset__h13216[4:0], 5'd30 } ; - assign source_id__h15845 = { addr_offset__h13216[4:0], 5'd29 } ; - assign source_id__h15918 = { addr_offset__h13216[4:0], 5'd28 } ; - assign source_id__h15991 = { addr_offset__h13216[4:0], 5'd27 } ; - assign source_id__h16064 = { addr_offset__h13216[4:0], 5'd26 } ; - assign source_id__h16137 = { addr_offset__h13216[4:0], 5'd25 } ; - assign source_id__h16210 = { addr_offset__h13216[4:0], 5'd24 } ; - assign source_id__h16283 = { addr_offset__h13216[4:0], 5'd23 } ; - assign source_id__h16356 = { addr_offset__h13216[4:0], 5'd22 } ; - assign source_id__h16429 = { addr_offset__h13216[4:0], 5'd21 } ; - assign source_id__h16502 = { addr_offset__h13216[4:0], 5'd20 } ; - assign source_id__h16575 = { addr_offset__h13216[4:0], 5'd19 } ; - assign source_id__h16648 = { addr_offset__h13216[4:0], 5'd18 } ; - assign source_id__h16721 = { addr_offset__h13216[4:0], 5'd17 } ; - assign source_id__h16794 = { addr_offset__h13216[4:0], 5'd16 } ; - assign source_id__h16867 = { addr_offset__h13216[4:0], 5'd15 } ; - assign source_id__h16940 = { addr_offset__h13216[4:0], 5'd14 } ; - assign source_id__h17013 = { addr_offset__h13216[4:0], 5'd13 } ; - assign source_id__h17086 = { addr_offset__h13216[4:0], 5'd12 } ; - assign source_id__h17159 = { addr_offset__h13216[4:0], 5'd11 } ; - assign source_id__h17232 = { addr_offset__h13216[4:0], 5'd10 } ; - assign source_id__h17305 = { addr_offset__h13216[4:0], 5'd9 } ; - assign source_id__h17378 = { addr_offset__h13216[4:0], 5'd8 } ; - assign source_id__h17451 = { addr_offset__h13216[4:0], 5'd7 } ; - assign source_id__h17524 = { addr_offset__h13216[4:0], 5'd6 } ; - assign source_id__h17597 = { addr_offset__h13216[4:0], 5'd5 } ; - assign source_id__h17670 = { addr_offset__h13216[4:0], 5'd4 } ; - assign source_id__h17743 = { addr_offset__h13216[4:0], 5'd3 } ; - assign source_id__h17816 = { addr_offset__h13216[4:0], 5'd2 } ; - assign source_id__h17889 = { addr_offset__h13216[4:0], 5'd1 } ; - assign source_id__h20137 = 10'd31 + source_id_base__h13630 ; - assign source_id__h20313 = 10'd30 + source_id_base__h13630 ; - assign source_id__h20421 = 10'd29 + source_id_base__h13630 ; - assign source_id__h20529 = 10'd28 + source_id_base__h13630 ; - assign source_id__h20637 = 10'd27 + source_id_base__h13630 ; - assign source_id__h20745 = 10'd26 + source_id_base__h13630 ; - assign source_id__h20853 = 10'd25 + source_id_base__h13630 ; - assign source_id__h20961 = 10'd24 + source_id_base__h13630 ; - assign source_id__h21069 = 10'd23 + source_id_base__h13630 ; - assign source_id__h21177 = 10'd22 + source_id_base__h13630 ; - assign source_id__h21285 = 10'd21 + source_id_base__h13630 ; - assign source_id__h21393 = 10'd20 + source_id_base__h13630 ; - assign source_id__h21501 = 10'd19 + source_id_base__h13630 ; - assign source_id__h21609 = 10'd18 + source_id_base__h13630 ; - assign source_id__h21717 = 10'd17 + source_id_base__h13630 ; - assign source_id__h21825 = 10'd16 + source_id_base__h13630 ; - assign source_id__h21933 = 10'd15 + source_id_base__h13630 ; - assign source_id__h22041 = 10'd14 + source_id_base__h13630 ; - assign source_id__h22149 = 10'd13 + source_id_base__h13630 ; - assign source_id__h22257 = 10'd12 + source_id_base__h13630 ; - assign source_id__h22365 = 10'd11 + source_id_base__h13630 ; - assign source_id__h22473 = 10'd10 + source_id_base__h13630 ; - assign source_id__h22581 = 10'd9 + source_id_base__h13630 ; - assign source_id__h22689 = 10'd8 + source_id_base__h13630 ; - assign source_id__h22797 = 10'd7 + source_id_base__h13630 ; - assign source_id__h22905 = 10'd6 + source_id_base__h13630 ; - assign source_id__h23013 = 10'd5 + source_id_base__h13630 ; - assign source_id__h23121 = 10'd4 + source_id_base__h13630 ; - assign source_id__h23229 = 10'd3 + source_id_base__h13630 ; - assign source_id__h23337 = 10'd2 + source_id_base__h13630 ; - assign source_id__h23445 = 10'd1 + source_id_base__h13630 ; - assign source_id__h29475 = { addr_offset__h26929[4:0], 5'd1 } ; - assign source_id__h30685 = { addr_offset__h26929[4:0], 5'd2 } ; - assign source_id__h31895 = { addr_offset__h26929[4:0], 5'd3 } ; - assign source_id__h33105 = { addr_offset__h26929[4:0], 5'd4 } ; - assign source_id__h34315 = { addr_offset__h26929[4:0], 5'd5 } ; - assign source_id__h35525 = { addr_offset__h26929[4:0], 5'd6 } ; - assign source_id__h36735 = { addr_offset__h26929[4:0], 5'd7 } ; - assign source_id__h37945 = { addr_offset__h26929[4:0], 5'd8 } ; - assign source_id__h39155 = { addr_offset__h26929[4:0], 5'd9 } ; - assign source_id__h40365 = { addr_offset__h26929[4:0], 5'd10 } ; - assign source_id__h41575 = { addr_offset__h26929[4:0], 5'd11 } ; - assign source_id__h42785 = { addr_offset__h26929[4:0], 5'd12 } ; - assign source_id__h43995 = { addr_offset__h26929[4:0], 5'd13 } ; - assign source_id__h45205 = { addr_offset__h26929[4:0], 5'd14 } ; - assign source_id__h46415 = { addr_offset__h26929[4:0], 5'd15 } ; - assign source_id__h47625 = { addr_offset__h26929[4:0], 5'd16 } ; - assign source_id__h48835 = { addr_offset__h26929[4:0], 5'd17 } ; - assign source_id__h50045 = { addr_offset__h26929[4:0], 5'd18 } ; - assign source_id__h51255 = { addr_offset__h26929[4:0], 5'd19 } ; - assign source_id__h52465 = { addr_offset__h26929[4:0], 5'd20 } ; - assign source_id__h53675 = { addr_offset__h26929[4:0], 5'd21 } ; - assign source_id__h54885 = { addr_offset__h26929[4:0], 5'd22 } ; - assign source_id__h56095 = { addr_offset__h26929[4:0], 5'd23 } ; - assign source_id__h57305 = { addr_offset__h26929[4:0], 5'd24 } ; - assign source_id__h58515 = { addr_offset__h26929[4:0], 5'd25 } ; - assign source_id__h59725 = { addr_offset__h26929[4:0], 5'd26 } ; - assign source_id__h60935 = { addr_offset__h26929[4:0], 5'd27 } ; - assign source_id__h62145 = { addr_offset__h26929[4:0], 5'd28 } ; - assign source_id__h63355 = { addr_offset__h26929[4:0], 5'd29 } ; - assign source_id__h64565 = { addr_offset__h26929[4:0], 5'd30 } ; - assign source_id__h65775 = { addr_offset__h26929[4:0], 5'd31 } ; - assign source_id__h67436 = { 5'd0, x__h67487 } ; - assign source_id_base__h13630 = { addr_offset__h13216[4:0], 5'h0 } ; - assign source_id_base__h28148 = { addr_offset__h26929[4:0], 5'h0 } ; - assign v__h13422 = { 61'd0, x__h13493 } ; - assign v__h13671 = { 32'd0, v_ip__h13674 } ; - assign v__h18144 = { 32'd0, v_ie__h18147 } ; - assign v__h23761 = { 61'd0, x__h23832 } ; - assign v__h25455 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ? - v__h25474 : - 64'd0 ; - assign v__h25474 = { 59'd0, max_id__h23959 } ; - assign v__h26934 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? - 2'b11 : - v__h27094 ; - assign v__h27094 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27107 : - v__h27942 ; - assign v__h27107 = - (addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? - 2'b0 : - 2'b10 ; - assign v__h27942 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27961 : - v__h28125 ; - assign v__h27961 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? - 2'b0 : - 2'b10 ; - assign v__h28125 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28144 : - v__h67107 ; - assign v__h28144 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? - 2'b0 : - 2'b10 ; - assign v__h67144 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - 2'b0 : - 2'b10 ; - assign v__h67432 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67476 : - 2'b10 ; - assign v__h67476 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? - 2'b0 : - 2'b10 ; - assign v_ie__h18147 = - { source_id__h20137 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h20313 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h20421 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h20529 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h20637 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h20745 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h20853 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h20961 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h21069 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h21177 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h21285 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h21393 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h21501 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h21609 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h21717 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h21825 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h21933 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h22041 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h22149 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h22257 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h22365 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h22473 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h22581 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h22689 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h22797 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h22905 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h23013 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h23121 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h23229 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h23337 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h23445 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h13674 = - { source_id__h15665 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - source_id__h15772 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - source_id__h15845 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - source_id__h15918 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - source_id__h15991 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - source_id__h16064 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - source_id__h16137 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - source_id__h16210 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - source_id__h16283 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - source_id__h16356 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - source_id__h16429 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - source_id__h16502 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - source_id__h16575 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - source_id__h16648 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - source_id__h16721 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - source_id__h16794 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - source_id__h16867 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - source_id__h16940 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - source_id__h17013 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - source_id__h17086 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - source_id__h17159 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - source_id__h17232 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - source_id__h17305 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - source_id__h17378 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - source_id__h17451 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - source_id__h17524 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - source_id__h17597 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - source_id__h17670 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - source_id__h17743 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - source_id__h17816 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - source_id__h17889 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26930 = - (addr_offset__h26929[2:0] == 3'd4) ? - m_slave_xactor_f_wr_data$D_OUT[72:41] : - m_slave_xactor_f_wr_data$D_OUT[40:9] ; - assign x__h23673 = - { addr_offset__h13216[31:16], 4'd0, addr_offset__h13216[11:0] } ; - assign x__h26361 = - (addr_offset__h13216[2:0] == 3'd4) ? - rdata___1__h26404 : - rdata__h26202 ; - assign x__h67110 = - { addr_offset__h26929[31:16], 4'd0, addr_offset__h26929[11:0] } ; - assign y_avValue_fst__h26094 = (x__h24011 == 5'd0) ? v__h25455 : 64'd0 ; - assign y_avValue_fst__h26115 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_fst__h26094 : - 64'd0 ; - assign y_avValue_fst__h26127 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - v__h23761 : - 64'd0 ; - assign y_avValue_fst__h26143 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - v__h18144 : - 64'd0 ; - assign y_avValue_fst__h26159 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - v__h13671 : - 64'd0 ; - assign y_avValue_fst__h26164 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_fst__h26143 : - y_avValue_fst__h26148 ; - assign y_avValue_fst__h26175 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - v__h13422 : - 64'd0 ; - assign y_avValue_fst__h26180 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_fst__h26159 : - y_avValue_fst__h26164 ; - assign y_avValue_fst__h26194 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_fst__h26175 : - y_avValue_fst__h26180 ; - assign y_avValue_snd__h26095 = (x__h24011 == 5'd0) ? 2'b0 : 2'b10 ; - assign y_avValue_snd__h26116 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_snd__h26095 : - 2'b10 ; - assign y_avValue_snd__h26128 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26144 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26160 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26165 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_snd__h26144 : - y_avValue_snd__h26149 ; - assign y_avValue_snd__h26176 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26181 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_snd__h26160 : - y_avValue_snd__h26165 ; - assign y_avValue_snd__h26195 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_snd__h26176 : - y_avValue_snd__h26181 ; - always@(addr_offset__h13216 or - m_vrg_source_prio_0 or - m_vrg_source_prio_1 or - m_vrg_source_prio_2 or - m_vrg_source_prio_3 or - m_vrg_source_prio_4 or - m_vrg_source_prio_5 or - m_vrg_source_prio_6 or - m_vrg_source_prio_7 or - m_vrg_source_prio_8 or - m_vrg_source_prio_9 or - m_vrg_source_prio_10 or - m_vrg_source_prio_11 or - m_vrg_source_prio_12 or - m_vrg_source_prio_13 or - m_vrg_source_prio_14 or - m_vrg_source_prio_15 or m_vrg_source_prio_16) - begin - case (addr_offset__h13216[11:2]) - 10'd0: x__h13493 = m_vrg_source_prio_0; - 10'd1: x__h13493 = m_vrg_source_prio_1; - 10'd2: x__h13493 = m_vrg_source_prio_2; - 10'd3: x__h13493 = m_vrg_source_prio_3; - 10'd4: x__h13493 = m_vrg_source_prio_4; - 10'd5: x__h13493 = m_vrg_source_prio_5; - 10'd6: x__h13493 = m_vrg_source_prio_6; - 10'd7: x__h13493 = m_vrg_source_prio_7; - 10'd8: x__h13493 = m_vrg_source_prio_8; - 10'd9: x__h13493 = m_vrg_source_prio_9; - 10'd10: x__h13493 = m_vrg_source_prio_10; - 10'd11: x__h13493 = m_vrg_source_prio_11; - 10'd12: x__h13493 = m_vrg_source_prio_12; - 10'd13: x__h13493 = m_vrg_source_prio_13; - 10'd14: x__h13493 = m_vrg_source_prio_14; - 10'd15: x__h13493 = m_vrg_source_prio_15; - 10'd16: x__h13493 = m_vrg_source_prio_16; - default: x__h13493 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_target_threshold_0 or m_vrg_target_threshold_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h23832 = m_vrg_target_threshold_0; - 5'd1: x__h23832 = m_vrg_target_threshold_1; - default: x__h23832 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h24011 = m_vrg_servicing_source_0; - 5'd1: x__h24011 = m_vrg_servicing_source_1; - default: x__h24011 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h26929 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h26929[16:12]) - 5'd0: x__h67487 = m_vrg_servicing_source_0; - 5'd1: x__h67487 = m_vrg_servicing_source_1; - default: x__h67487 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15665 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15665) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15772 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15772) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15845 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15845) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15918 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15918) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15991 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15991) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16064 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16064) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17159 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17159) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16137 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16137) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16210 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16210) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16283 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16283) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16356 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16356) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16429 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16429) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16502 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16502) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16575 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16575) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16648 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16648) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16721 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16721) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16794 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16794) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16867 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16867) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16940 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16940) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17013 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17013) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17086 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17086) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17232 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17232) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17305 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17305) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17378 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17378) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17451 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17451) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17524 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17524) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17597 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17597) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17670 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17670) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17743 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17743) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17889 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17889) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17816 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17816) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_snd__h26128 or y_avValue_snd__h26116) - begin - case (x__h23673) - 32'h00200000: y_avValue_snd__h26149 = y_avValue_snd__h26128; - 32'h00200004: y_avValue_snd__h26149 = y_avValue_snd__h26116; - default: y_avValue_snd__h26149 = 2'b10; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_0_1; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_1_1; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_0_2; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_1_2; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_0_3; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_1_3; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_0_4; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_1_4; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_0_5; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_1_5; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_0_6; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_1_6; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_0_7; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_1_7; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_0_8; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_1_8; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_0_9; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_1_9; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_0_10; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_1_10; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_0_11; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_1_11; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_0_12; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_1_12; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_0_13; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_1_13; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_0_14; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_1_14; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_0_15; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_1_15; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_0_16; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_1_16; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_fst__h26127 or y_avValue_fst__h26115) - begin - case (x__h23673) - 32'h00200000: y_avValue_fst__h26148 = y_avValue_fst__h26127; - 32'h00200004: y_avValue_fst__h26148 = y_avValue_fst__h26115; - default: y_avValue_fst__h26148 = 64'd0; - endcase - end - always@(source_id__h67436 or - m_vrg_source_busy_0 or - m_vrg_source_busy_1 or - m_vrg_source_busy_2 or - m_vrg_source_busy_3 or - m_vrg_source_busy_4 or - m_vrg_source_busy_5 or - m_vrg_source_busy_6 or - m_vrg_source_busy_7 or - m_vrg_source_busy_8 or - m_vrg_source_busy_9 or - m_vrg_source_busy_10 or - m_vrg_source_busy_11 or - m_vrg_source_busy_12 or - m_vrg_source_busy_13 or - m_vrg_source_busy_14 or - m_vrg_source_busy_15 or m_vrg_source_busy_16) - begin - case (source_id__h67436) - 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_0; - 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_1; - 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_2; - 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_3; - 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_4; - 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_5; - 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_6; - 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_7; - 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_8; - 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_9; - 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_10; - 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_11; - 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_12; - 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_13; - 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_14; - 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_15; - 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h67110 or v__h67144 or v__h67432) - begin - case (x__h67110) - 32'h00200000: v__h67107 = v__h67144; - 32'h00200004: v__h67107 = v__h67432; - default: v__h67107 = 2'b10; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_cfg_verbosity$EN) - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN; - if (m_vrg_servicing_source_0$EN) - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_0$D_IN; - if (m_vrg_servicing_source_1$EN) - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_1$D_IN; - if (m_vrg_source_busy_0$EN) - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_0$D_IN; - if (m_vrg_source_busy_1$EN) - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_1$D_IN; - if (m_vrg_source_busy_10$EN) - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_10$D_IN; - if (m_vrg_source_busy_11$EN) - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_11$D_IN; - if (m_vrg_source_busy_12$EN) - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_12$D_IN; - if (m_vrg_source_busy_13$EN) - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_13$D_IN; - if (m_vrg_source_busy_14$EN) - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_14$D_IN; - if (m_vrg_source_busy_15$EN) - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_15$D_IN; - if (m_vrg_source_busy_16$EN) - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_16$D_IN; - if (m_vrg_source_busy_2$EN) - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_2$D_IN; - if (m_vrg_source_busy_3$EN) - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_3$D_IN; - if (m_vrg_source_busy_4$EN) - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_4$D_IN; - if (m_vrg_source_busy_5$EN) - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_5$D_IN; - if (m_vrg_source_busy_6$EN) - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_6$D_IN; - if (m_vrg_source_busy_7$EN) - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_7$D_IN; - if (m_vrg_source_busy_8$EN) - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_8$D_IN; - if (m_vrg_source_busy_9$EN) - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_9$D_IN; - if (m_vrg_source_ip_0$EN) - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_0$D_IN; - if (m_vrg_source_ip_1$EN) - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_1$D_IN; - if (m_vrg_source_ip_10$EN) - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_10$D_IN; - if (m_vrg_source_ip_11$EN) - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_11$D_IN; - if (m_vrg_source_ip_12$EN) - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_12$D_IN; - if (m_vrg_source_ip_13$EN) - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_13$D_IN; - if (m_vrg_source_ip_14$EN) - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_14$D_IN; - if (m_vrg_source_ip_15$EN) - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_15$D_IN; - if (m_vrg_source_ip_16$EN) - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_16$D_IN; - if (m_vrg_source_ip_2$EN) - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_2$D_IN; - if (m_vrg_source_ip_3$EN) - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_3$D_IN; - if (m_vrg_source_ip_4$EN) - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_4$D_IN; - if (m_vrg_source_ip_5$EN) - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_5$D_IN; - if (m_vrg_source_ip_6$EN) - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_6$D_IN; - if (m_vrg_source_ip_7$EN) - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_7$D_IN; - if (m_vrg_source_ip_8$EN) - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_8$D_IN; - if (m_vrg_source_ip_9$EN) - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_9$D_IN; - if (m_vrg_source_prio_0$EN) - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_0$D_IN; - if (m_vrg_source_prio_1$EN) - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_1$D_IN; - if (m_vrg_source_prio_10$EN) - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_10$D_IN; - if (m_vrg_source_prio_11$EN) - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_11$D_IN; - if (m_vrg_source_prio_12$EN) - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_12$D_IN; - if (m_vrg_source_prio_13$EN) - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_13$D_IN; - if (m_vrg_source_prio_14$EN) - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_14$D_IN; - if (m_vrg_source_prio_15$EN) - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_15$D_IN; - if (m_vrg_source_prio_16$EN) - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_16$D_IN; - if (m_vrg_source_prio_2$EN) - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_2$D_IN; - if (m_vrg_source_prio_3$EN) - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_3$D_IN; - if (m_vrg_source_prio_4$EN) - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_4$D_IN; - if (m_vrg_source_prio_5$EN) - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_5$D_IN; - if (m_vrg_source_prio_6$EN) - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_6$D_IN; - if (m_vrg_source_prio_7$EN) - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_7$D_IN; - if (m_vrg_source_prio_8$EN) - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_8$D_IN; - if (m_vrg_source_prio_9$EN) - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_9$D_IN; - if (m_vrg_target_threshold_0$EN) - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_0$D_IN; - if (m_vrg_target_threshold_1$EN) - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_1$D_IN; - if (m_vvrg_ie_0_0$EN) - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_0$D_IN; - if (m_vvrg_ie_0_1$EN) - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_1$D_IN; - if (m_vvrg_ie_0_10$EN) - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_10$D_IN; - if (m_vvrg_ie_0_11$EN) - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_11$D_IN; - if (m_vvrg_ie_0_12$EN) - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_12$D_IN; - if (m_vvrg_ie_0_13$EN) - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_13$D_IN; - if (m_vvrg_ie_0_14$EN) - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_14$D_IN; - if (m_vvrg_ie_0_15$EN) - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_15$D_IN; - if (m_vvrg_ie_0_16$EN) - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_16$D_IN; - if (m_vvrg_ie_0_2$EN) - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_2$D_IN; - if (m_vvrg_ie_0_3$EN) - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_3$D_IN; - if (m_vvrg_ie_0_4$EN) - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_4$D_IN; - if (m_vvrg_ie_0_5$EN) - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_5$D_IN; - if (m_vvrg_ie_0_6$EN) - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_6$D_IN; - if (m_vvrg_ie_0_7$EN) - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_7$D_IN; - if (m_vvrg_ie_0_8$EN) - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_8$D_IN; - if (m_vvrg_ie_0_9$EN) - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_9$D_IN; - if (m_vvrg_ie_1_0$EN) - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_0$D_IN; - if (m_vvrg_ie_1_1$EN) - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_1$D_IN; - if (m_vvrg_ie_1_10$EN) - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_10$D_IN; - if (m_vvrg_ie_1_11$EN) - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_11$D_IN; - if (m_vvrg_ie_1_12$EN) - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_12$D_IN; - if (m_vvrg_ie_1_13$EN) - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_13$D_IN; - if (m_vvrg_ie_1_14$EN) - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_14$D_IN; - if (m_vvrg_ie_1_15$EN) - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_15$D_IN; - if (m_vvrg_ie_1_16$EN) - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_16$D_IN; - if (m_vvrg_ie_1_2$EN) - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_2$D_IN; - if (m_vvrg_ie_1_3$EN) - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_3$D_IN; - if (m_vvrg_ie_1_4$EN) - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_4$D_IN; - if (m_vvrg_ie_1_5$EN) - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_5$D_IN; - if (m_vvrg_ie_1_6$EN) - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_6$D_IN; - if (m_vvrg_ie_1_7$EN) - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_7$D_IN; - if (m_vvrg_ie_1_8$EN) - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_8$D_IN; - if (m_vvrg_ie_1_9$EN) - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_9$D_IN; - end - if (m_rg_addr_base$EN) - m_rg_addr_base <= `BSV_ASSIGNMENT_DELAY m_rg_addr_base$D_IN; - if (m_rg_addr_lim$EN) - m_rg_addr_lim <= `BSV_ASSIGNMENT_DELAY m_rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_cfg_verbosity = 4'hA; - m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - m_vrg_servicing_source_0 = 5'h0A; - m_vrg_servicing_source_1 = 5'h0A; - m_vrg_source_busy_0 = 1'h0; - m_vrg_source_busy_1 = 1'h0; - m_vrg_source_busy_10 = 1'h0; - m_vrg_source_busy_11 = 1'h0; - m_vrg_source_busy_12 = 1'h0; - m_vrg_source_busy_13 = 1'h0; - m_vrg_source_busy_14 = 1'h0; - m_vrg_source_busy_15 = 1'h0; - m_vrg_source_busy_16 = 1'h0; - m_vrg_source_busy_2 = 1'h0; - m_vrg_source_busy_3 = 1'h0; - m_vrg_source_busy_4 = 1'h0; - m_vrg_source_busy_5 = 1'h0; - m_vrg_source_busy_6 = 1'h0; - m_vrg_source_busy_7 = 1'h0; - m_vrg_source_busy_8 = 1'h0; - m_vrg_source_busy_9 = 1'h0; - m_vrg_source_ip_0 = 1'h0; - m_vrg_source_ip_1 = 1'h0; - m_vrg_source_ip_10 = 1'h0; - m_vrg_source_ip_11 = 1'h0; - m_vrg_source_ip_12 = 1'h0; - m_vrg_source_ip_13 = 1'h0; - m_vrg_source_ip_14 = 1'h0; - m_vrg_source_ip_15 = 1'h0; - m_vrg_source_ip_16 = 1'h0; - m_vrg_source_ip_2 = 1'h0; - m_vrg_source_ip_3 = 1'h0; - m_vrg_source_ip_4 = 1'h0; - m_vrg_source_ip_5 = 1'h0; - m_vrg_source_ip_6 = 1'h0; - m_vrg_source_ip_7 = 1'h0; - m_vrg_source_ip_8 = 1'h0; - m_vrg_source_ip_9 = 1'h0; - m_vrg_source_prio_0 = 3'h2; - m_vrg_source_prio_1 = 3'h2; - m_vrg_source_prio_10 = 3'h2; - m_vrg_source_prio_11 = 3'h2; - m_vrg_source_prio_12 = 3'h2; - m_vrg_source_prio_13 = 3'h2; - m_vrg_source_prio_14 = 3'h2; - m_vrg_source_prio_15 = 3'h2; - m_vrg_source_prio_16 = 3'h2; - m_vrg_source_prio_2 = 3'h2; - m_vrg_source_prio_3 = 3'h2; - m_vrg_source_prio_4 = 3'h2; - m_vrg_source_prio_5 = 3'h2; - m_vrg_source_prio_6 = 3'h2; - m_vrg_source_prio_7 = 3'h2; - m_vrg_source_prio_8 = 3'h2; - m_vrg_source_prio_9 = 3'h2; - m_vrg_target_threshold_0 = 3'h2; - m_vrg_target_threshold_1 = 3'h2; - m_vvrg_ie_0_0 = 1'h0; - m_vvrg_ie_0_1 = 1'h0; - m_vvrg_ie_0_10 = 1'h0; - m_vvrg_ie_0_11 = 1'h0; - m_vvrg_ie_0_12 = 1'h0; - m_vvrg_ie_0_13 = 1'h0; - m_vvrg_ie_0_14 = 1'h0; - m_vvrg_ie_0_15 = 1'h0; - m_vvrg_ie_0_16 = 1'h0; - m_vvrg_ie_0_2 = 1'h0; - m_vvrg_ie_0_3 = 1'h0; - m_vvrg_ie_0_4 = 1'h0; - m_vvrg_ie_0_5 = 1'h0; - m_vvrg_ie_0_6 = 1'h0; - m_vvrg_ie_0_7 = 1'h0; - m_vvrg_ie_0_8 = 1'h0; - m_vvrg_ie_0_9 = 1'h0; - m_vvrg_ie_1_0 = 1'h0; - m_vvrg_ie_1_1 = 1'h0; - m_vvrg_ie_1_10 = 1'h0; - m_vvrg_ie_1_11 = 1'h0; - m_vvrg_ie_1_12 = 1'h0; - m_vvrg_ie_1_13 = 1'h0; - m_vvrg_ie_1_14 = 1'h0; - m_vvrg_ie_1_15 = 1'h0; - m_vvrg_ie_1_16 = 1'h0; - m_vvrg_ie_1_2 = 1'h0; - m_vvrg_ie_1_3 = 1'h0; - m_vvrg_ie_1_4 = 1'h0; - m_vvrg_ie_1_5 = 1'h0; - m_vvrg_ie_1_6 = 1'h0; - m_vvrg_ie_1_7 = 1'h0; - m_vvrg_ie_1_8 = 1'h0; - m_vvrg_ie_1_9 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src IPs :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src Prios:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src busy :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71312, - m_vrg_target_threshold_0, - b__h71313, - m_vrg_servicing_source_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73317, - m_vrg_target_threshold_1, - b__h73318, - m_vrg_servicing_source_1); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - begin - v__h75676 = $stime; - #0; - end - v__h75670 = v__h75676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75670, - $signed(32'd1), - v_sources_0_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - begin - v__h75874 = $stime; - #0; - end - v__h75868 = v__h75874 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75868, - $signed(32'd2), - v_sources_1_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - begin - v__h76072 = $stime; - #0; - end - v__h76066 = v__h76072 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76066, - $signed(32'd3), - v_sources_2_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - begin - v__h76270 = $stime; - #0; - end - v__h76264 = v__h76270 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76264, - $signed(32'd4), - v_sources_3_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - begin - v__h76468 = $stime; - #0; - end - v__h76462 = v__h76468 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76462, - $signed(32'd5), - v_sources_4_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - begin - v__h76666 = $stime; - #0; - end - v__h76660 = v__h76666 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76660, - $signed(32'd6), - v_sources_5_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - begin - v__h76864 = $stime; - #0; - end - v__h76858 = v__h76864 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76858, - $signed(32'd7), - v_sources_6_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - begin - v__h77062 = $stime; - #0; - end - v__h77056 = v__h77062 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77056, - $signed(32'd8), - v_sources_7_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - begin - v__h77260 = $stime; - #0; - end - v__h77254 = v__h77260 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77254, - $signed(32'd9), - v_sources_8_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - begin - v__h77458 = $stime; - #0; - end - v__h77452 = v__h77458 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77452, - $signed(32'd10), - v_sources_9_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - begin - v__h77656 = $stime; - #0; - end - v__h77650 = v__h77656 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77650, - $signed(32'd11), - v_sources_10_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - begin - v__h77854 = $stime; - #0; - end - v__h77848 = v__h77854 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77848, - $signed(32'd12), - v_sources_11_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - begin - v__h78052 = $stime; - #0; - end - v__h78046 = v__h78052 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78046, - $signed(32'd13), - v_sources_12_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - begin - v__h78250 = $stime; - #0; - end - v__h78244 = v__h78250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78244, - $signed(32'd14), - v_sources_13_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - begin - v__h78448 = $stime; - #0; - end - v__h78442 = v__h78448 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78442, - $signed(32'd15), - v_sources_14_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - begin - v__h78646 = $stime; - #0; - end - v__h78640 = v__h78646 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78640, - $signed(32'd16), - v_sources_15_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - begin - v__h6144 = $stime; - #0; - end - v__h6138 = v__h6144 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h6138); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h13080 = $stime; - #0; - end - v__h13074 = v__h13080 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req:", v__h13074); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - begin - v__h13265 = $stime; - #0; - end - v__h13259 = v__h13265 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h13259); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - begin - v__h13463 = $stime; - #0; - end - v__h13457 = v__h13463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h13457, - addr_offset__h13216[11:2], - v__h13422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - begin - v__h13713 = $stime; - #0; - end - v__h13707 = v__h13713 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h13707, - source_id_base__h13630, - v__h13671); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - begin - v__h18186 = $stime; - #0; - end - v__h18180 = v__h18186 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h18180, - source_id_base__h13630, - v__h18144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - begin - v__h23802 = $stime; - #0; - end - v__h23796 = v__h23802 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h23796, - addr_offset__h13216[16:12], - v__h23761); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - begin - v__h25975 = $stime; - #0; - end - v__h25969 = v__h25975 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h25969, - addr_offset__h13216[16:12], - v__h25474); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - begin - v__h24056 = $stime; - #0; - end - v__h24050 = v__h24056 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h24050, - addr_offset__h13216[16:12]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Still servicing interrupt from source %0d", x__h24011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Trying to claim service for source %0d", - max_id__h23959); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Ignoring."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - begin - v__h26250 = $stime; - #0; - end - v__h26244 = v__h26250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h26244); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26463 = $stime; - #0; - end - v__h26457 = v__h26463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req", v__h26457); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", x__h26361); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", rresp__h26203); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26740 = $stime; - #0; - end - v__h26734 = v__h26740 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26734); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - begin - v__h26968 = $stime; - #0; - end - v__h26962 = v__h26968 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26962); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - begin - v__h27865 = $stime; - #0; - end - v__h27859 = v__h27865 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27859, - addr_offset__h26929[11:2], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - begin - v__h28048 = $stime; - #0; - end - v__h28042 = v__h28048 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28042, - source_id_base__h28148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - begin - v__h67030 = $stime; - #0; - end - v__h67024 = v__h67030 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67024, - addr_offset__h26929[11:7], - source_id_base__h28148, - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - begin - v__h67318 = $stime; - #0; - end - v__h67312 = v__h67318 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67312, - addr_offset__h26929[16:12], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - begin - v__h67847 = $stime; - #0; - end - v__h67841 = v__h67847 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67841, - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - begin - v__h67933 = $stime; - #0; - end - v__h67927 = v__h67933 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67927); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Completion message from target %0d to source %0d", - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Ignoring"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - begin - v__h68132 = $stime; - #0; - end - v__h68126 = v__h68132 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68126); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h68353 = $stime; - #0; - end - v__h68347 = v__h68353 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68347); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26934); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h74690 = $stime; - #0; - end - v__h74684 = v__h74690 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74684, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h74800 = $stime; - #0; - end - v__h74794 = v__h74800 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74794, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - begin - v__h74913 = $stime; - #0; - end - v__h74907 = v__h74913 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74907, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkPLIC_16_2_7 - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v deleted file mode 100644 index 570d9b06..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v +++ /dev/null @@ -1,663 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_req_reset O 1 const -// RDY_rsp_reset O 1 const -// valid O 1 -// word O 32 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_is_OP_not_OP_32 I 1 reg -// req_f3 I 3 -// req_v1 I 32 -// req_v2 I 32 -// EN_set_verbosity I 1 -// EN_req_reset I 1 unused -// EN_rsp_reset I 1 unused -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkRISCV_MBox(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_req_reset, - RDY_req_reset, - - EN_rsp_reset, - RDY_rsp_reset, - - req_is_OP_not_OP_32, - req_f3, - req_v1, - req_v2, - EN_req, - - valid, - - word); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method req_reset - input EN_req_reset; - output RDY_req_reset; - - // action method rsp_reset - input EN_rsp_reset; - output RDY_rsp_reset; - - // action method req - input req_is_OP_not_OP_32; - input [2 : 0] req_f3; - input [31 : 0] req_v1; - input [31 : 0] req_v2; - input EN_req; - - // value method valid - output valid; - - // value method word - output [31 : 0] word; - - // signals for module outputs - wire [31 : 0] word; - wire RDY_req_reset, RDY_rsp_reset, RDY_set_verbosity, valid; - - // inlined wires - wire dw_valid$whas; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register intDiv_rg_denom2 - reg [31 : 0] intDiv_rg_denom2; - reg [31 : 0] intDiv_rg_denom2$D_IN; - wire intDiv_rg_denom2$EN; - - // register intDiv_rg_denom_is_signed - reg intDiv_rg_denom_is_signed; - wire intDiv_rg_denom_is_signed$D_IN, intDiv_rg_denom_is_signed$EN; - - // register intDiv_rg_n - reg [31 : 0] intDiv_rg_n; - reg [31 : 0] intDiv_rg_n$D_IN; - wire intDiv_rg_n$EN; - - // register intDiv_rg_numer_is_signed - reg intDiv_rg_numer_is_signed; - wire intDiv_rg_numer_is_signed$D_IN, intDiv_rg_numer_is_signed$EN; - - // register intDiv_rg_quo - reg [31 : 0] intDiv_rg_quo; - reg [31 : 0] intDiv_rg_quo$D_IN; - wire intDiv_rg_quo$EN; - - // register intDiv_rg_quoIsNeg - reg intDiv_rg_quoIsNeg; - wire intDiv_rg_quoIsNeg$D_IN, intDiv_rg_quoIsNeg$EN; - - // register intDiv_rg_remIsNeg - reg intDiv_rg_remIsNeg; - wire intDiv_rg_remIsNeg$D_IN, intDiv_rg_remIsNeg$EN; - - // register intDiv_rg_state - reg [2 : 0] intDiv_rg_state; - reg [2 : 0] intDiv_rg_state$D_IN; - wire intDiv_rg_state$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_is_OP_not_OP_32 - reg rg_is_OP_not_OP_32; - wire rg_is_OP_not_OP_32$D_IN, rg_is_OP_not_OP_32$EN; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_v1 - reg [31 : 0] rg_v1; - reg [31 : 0] rg_v1$D_IN; - wire rg_v1$EN; - - // register rg_v2 - reg [31 : 0] rg_v2; - wire [31 : 0] rg_v2$D_IN; - wire rg_v2$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_intDiv_rl_loop1, - CAN_FIRE_RL_intDiv_rl_loop2, - CAN_FIRE_RL_intDiv_rl_start_div_by_zero, - CAN_FIRE_RL_intDiv_rl_start_overflow, - CAN_FIRE_RL_intDiv_rl_start_s, - CAN_FIRE_RL_rg_div_rem, - CAN_FIRE_RL_rl_mul, - CAN_FIRE_RL_rl_mul2, - CAN_FIRE_req, - CAN_FIRE_req_reset, - CAN_FIRE_rsp_reset, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_intDiv_rl_loop1, - WILL_FIRE_RL_intDiv_rl_loop2, - WILL_FIRE_RL_intDiv_rl_start_div_by_zero, - WILL_FIRE_RL_intDiv_rl_start_overflow, - WILL_FIRE_RL_intDiv_rl_start_s, - WILL_FIRE_RL_rg_div_rem, - WILL_FIRE_RL_rl_mul, - WILL_FIRE_RL_rl_mul2, - WILL_FIRE_req, - WILL_FIRE_req_reset, - WILL_FIRE_rsp_reset, - WILL_FIRE_set_verbosity; - - // inputs to muxes for submodule ports - wire [31 : 0] MUX_dw_result$wset_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_1, - MUX_intDiv_rg_denom2$write_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_3, - MUX_intDiv_rg_n$write_1__VAL_1, - MUX_intDiv_rg_n$write_1__VAL_2, - MUX_intDiv_rg_quo$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_2, - MUX_rg_v1$write_1__VAL_3, - MUX_rg_v1$write_1__VAL_4; - wire [1 : 0] MUX_rg_state$write_1__VAL_1; - wire MUX_intDiv_rg_denom2$write_1__SEL_1, - MUX_intDiv_rg_denom2$write_1__SEL_2, - MUX_intDiv_rg_quo$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_2, - MUX_intDiv_rg_state$write_1__SEL_3, - MUX_rg_v1$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h3263; - reg [31 : 0] v__h3257; - // synopsys translate_on - - // remaining internal signals - wire [127 : 0] SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113, - SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105, - _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110; - wire [63 : 0] SEXT_rg_v1____d103, rg_v1_MUL_rg_v2___d100, v1__h3150; - wire [31 : 0] _theResult___fst__h787, - _theResult___snd_fst__h782, - denom___1__h729, - numer___1__h728, - v__h3074, - v__h3132, - v__h3183, - x__h2611, - x__h2697, - x__h2767, - x__h2782, - y__h2490; - wire IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39, - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47, - rg_v1_ULT_intDiv_rg_denom2_4___d59, - rg_v1_ULT_rg_v2___d55; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method req_reset - assign RDY_req_reset = 1'd1 ; - assign CAN_FIRE_req_reset = 1'd1 ; - assign WILL_FIRE_req_reset = EN_req_reset ; - - // action method rsp_reset - assign RDY_rsp_reset = 1'd1 ; - assign CAN_FIRE_rsp_reset = 1'd1 ; - assign WILL_FIRE_rsp_reset = EN_rsp_reset ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method word - assign word = WILL_FIRE_RL_rl_mul2 ? rg_v1 : MUX_dw_result$wset_1__VAL_2 ; - - // rule RL_rl_mul2 - assign CAN_FIRE_RL_rl_mul2 = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_mul2 = CAN_FIRE_RL_rl_mul2 ; - - // rule RL_rg_div_rem - assign CAN_FIRE_RL_rg_div_rem = - rg_state == 2'd2 && intDiv_rg_state == 3'd4 ; - assign WILL_FIRE_RL_rg_div_rem = CAN_FIRE_RL_rg_div_rem ; - - // rule RL_intDiv_rl_start_div_by_zero - assign CAN_FIRE_RL_intDiv_rl_start_div_by_zero = - intDiv_rg_state == 3'd1 && rg_v2 == 32'd0 ; - assign WILL_FIRE_RL_intDiv_rl_start_div_by_zero = - CAN_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // rule RL_intDiv_rl_start_overflow - assign CAN_FIRE_RL_intDiv_rl_start_overflow = - intDiv_rg_state == 3'd1 && intDiv_rg_numer_is_signed && - rg_v1 == 32'h80000000 && - intDiv_rg_denom_is_signed && - rg_v2 == 32'hFFFFFFFF ; - assign WILL_FIRE_RL_intDiv_rl_start_overflow = - CAN_FIRE_RL_intDiv_rl_start_overflow && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_start_s - assign CAN_FIRE_RL_intDiv_rl_start_s = - intDiv_rg_state == 3'd1 && rg_v2 != 32'd0 && - (!intDiv_rg_numer_is_signed || rg_v1 != 32'h80000000 || - !intDiv_rg_denom_is_signed || - rg_v2 != 32'hFFFFFFFF) ; - assign WILL_FIRE_RL_intDiv_rl_start_s = - CAN_FIRE_RL_intDiv_rl_start_s && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_loop1 - assign CAN_FIRE_RL_intDiv_rl_loop1 = intDiv_rg_state == 3'd2 ; - assign WILL_FIRE_RL_intDiv_rl_loop1 = CAN_FIRE_RL_intDiv_rl_loop1 ; - - // rule RL_rl_mul - assign CAN_FIRE_RL_rl_mul = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_mul = rg_state == 2'd0 ; - - // rule RL_intDiv_rl_loop2 - assign CAN_FIRE_RL_intDiv_rl_loop2 = intDiv_rg_state == 3'd3 ; - assign WILL_FIRE_RL_intDiv_rl_loop2 = - CAN_FIRE_RL_intDiv_rl_loop2 && !WILL_FIRE_RL_rl_mul ; - - // inputs to muxes for submodule ports - assign MUX_intDiv_rg_denom2$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 ; - assign MUX_intDiv_rg_denom2$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 ; - assign MUX_intDiv_rg_quo$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_quoIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_intDiv_rg_state$write_1__SEL_1 = EN_req && req_f3[2] ; - assign MUX_intDiv_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 ; - assign MUX_intDiv_rg_state$write_1__SEL_3 = - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 ; - assign MUX_rg_v1$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_remIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_dw_result$wset_1__VAL_2 = rg_f3[1] ? rg_v1 : intDiv_rg_quo ; - assign MUX_intDiv_rg_denom2$write_1__VAL_1 = - { intDiv_rg_denom2[30:0], 1'd0 } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_2 = - { 1'd0, intDiv_rg_denom2[31:1] } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_3 = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - denom___1__h729 : - _theResult___snd_fst__h782 ; - assign MUX_intDiv_rg_n$write_1__VAL_1 = { intDiv_rg_n[30:0], 1'd0 } ; - assign MUX_intDiv_rg_n$write_1__VAL_2 = { 1'd0, intDiv_rg_n[31:1] } ; - assign MUX_intDiv_rg_quo$write_1__VAL_1 = - rg_v1_ULT_rg_v2___d55 ? x__h2697 : x__h2782 ; - assign MUX_rg_state$write_1__VAL_1 = req_f3[2] ? 2'd2 : 2'd0 ; - assign MUX_rg_v1$write_1__VAL_2 = - rg_v1_ULT_rg_v2___d55 ? x__h2767 : x__h2611 ; - assign MUX_rg_v1$write_1__VAL_3 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - rg_v1_MUL_rg_v2___d100[31:0] : - v__h3074 ; - assign MUX_rg_v1$write_1__VAL_4 = - intDiv_rg_numer_is_signed ? numer___1__h728 : rg_v1 ; - - // inlined wires - assign dw_valid$whas = WILL_FIRE_RL_rg_div_rem || WILL_FIRE_RL_rl_mul2 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register intDiv_rg_denom2 - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_denom2$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_denom2$write_1__VAL_2 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_intDiv_rg_denom2$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_3; - default: intDiv_rg_denom2$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_denom2$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_denom_is_signed - assign intDiv_rg_denom_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_denom_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_n - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_n$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_n$write_1__VAL_2 or WILL_FIRE_RL_intDiv_rl_start_s) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_n$D_IN = 32'd1; - default: intDiv_rg_n$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_n$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_numer_is_signed - assign intDiv_rg_numer_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_numer_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_quo - always@(MUX_intDiv_rg_quo$write_1__SEL_1 or - MUX_intDiv_rg_quo$write_1__VAL_1 or - WILL_FIRE_RL_intDiv_rl_start_overflow or - rg_v1 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_quo$write_1__SEL_1: - intDiv_rg_quo$D_IN = MUX_intDiv_rg_quo$write_1__VAL_1; - WILL_FIRE_RL_intDiv_rl_start_overflow: intDiv_rg_quo$D_IN = rg_v1; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_quo$D_IN = 32'd0; - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_quo$D_IN = 32'hFFFFFFFF; - default: intDiv_rg_quo$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_quo$EN = - MUX_intDiv_rg_quo$write_1__SEL_1 || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register intDiv_rg_quoIsNeg - assign intDiv_rg_quoIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[31] != rg_v2[31] : - IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39 ; - assign intDiv_rg_quoIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_remIsNeg - assign intDiv_rg_remIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[31] : - intDiv_rg_numer_is_signed && rg_v1[31] ; - assign intDiv_rg_remIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_state - always@(MUX_intDiv_rg_state$write_1__SEL_1 or - MUX_intDiv_rg_state$write_1__SEL_2 or - MUX_intDiv_rg_state$write_1__SEL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_overflow or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - case (1'b1) - MUX_intDiv_rg_state$write_1__SEL_1: intDiv_rg_state$D_IN = 3'd1; - MUX_intDiv_rg_state$write_1__SEL_2: intDiv_rg_state$D_IN = 3'd4; - MUX_intDiv_rg_state$write_1__SEL_3: intDiv_rg_state$D_IN = 3'd3; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_state$D_IN = 3'd2; - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_state$D_IN = 3'd4; - default: intDiv_rg_state$D_IN = 3'b010 /* unspecified value */ ; - endcase - assign intDiv_rg_state$EN = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 || - EN_req && req_f3[2] || - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_is_OP_not_OP_32 - assign rg_is_OP_not_OP_32$D_IN = req_is_OP_not_OP_32 ; - assign rg_is_OP_not_OP_32$EN = EN_req ; - - // register rg_state - assign rg_state$D_IN = EN_req ? MUX_rg_state$write_1__VAL_1 : 2'd1 ; - assign rg_state$EN = EN_req || WILL_FIRE_RL_rl_mul ; - - // register rg_v1 - always@(EN_req or - req_v1 or - MUX_rg_v1$write_1__SEL_2 or - MUX_rg_v1$write_1__VAL_2 or - WILL_FIRE_RL_rl_mul or - MUX_rg_v1$write_1__VAL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_rg_v1$write_1__VAL_4 or WILL_FIRE_RL_intDiv_rl_start_overflow) - case (1'b1) - EN_req: rg_v1$D_IN = req_v1; - MUX_rg_v1$write_1__SEL_2: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_2; - WILL_FIRE_RL_rl_mul: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_3; - WILL_FIRE_RL_intDiv_rl_start_s: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_4; - WILL_FIRE_RL_intDiv_rl_start_overflow: rg_v1$D_IN = 32'd0; - default: rg_v1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - assign rg_v1$EN = - MUX_rg_v1$write_1__SEL_2 || EN_req || WILL_FIRE_RL_rl_mul || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow ; - - // register rg_v2 - assign rg_v2$D_IN = EN_req ? req_v2 : MUX_intDiv_rg_denom2$write_1__VAL_3 ; - assign rg_v2$EN = EN_req || WILL_FIRE_RL_intDiv_rl_start_s ; - - // remaining internal signals - assign IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39 = - intDiv_rg_numer_is_signed ? - rg_v1[31] : - intDiv_rg_denom_is_signed && rg_v2[31] ; - assign SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113 = - SEXT_rg_v1____d103 * { 32'd0, rg_v2 } ; - assign SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105 = - SEXT_rg_v1____d103 * { {32{rg_v2[31]}}, rg_v2 } ; - assign SEXT_rg_v1____d103 = { {32{rg_v1[31]}}, rg_v1 } ; - assign _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110 = - v1__h3150 * { 32'd0, rg_v2 } ; - assign _theResult___fst__h787 = - intDiv_rg_denom_is_signed ? denom___1__h729 : rg_v2 ; - assign _theResult___snd_fst__h782 = - intDiv_rg_numer_is_signed ? rg_v2 : _theResult___fst__h787 ; - assign denom___1__h729 = rg_v2[31] ? -rg_v2 : rg_v2 ; - assign intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 = - intDiv_rg_denom2 <= y__h2490 ; - assign numer___1__h728 = rg_v1[31] ? x__h2767 : rg_v1 ; - assign rg_v1_MUL_rg_v2___d100 = rg_v1 * rg_v2 ; - assign rg_v1_ULT_intDiv_rg_denom2_4___d59 = rg_v1 < intDiv_rg_denom2 ; - assign rg_v1_ULT_rg_v2___d55 = rg_v1 < rg_v2 ; - assign v1__h3150 = { 32'd0, rg_v1 } ; - assign v__h3074 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b001) ? - SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105[63:32] : - v__h3132 ; - assign v__h3132 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b011) ? - _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110[63:32] : - v__h3183 ; - assign v__h3183 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b010) ? - SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113[63:32] : - 32'hFFFFFFFF ; - assign x__h2611 = rg_v1 - intDiv_rg_denom2 ; - assign x__h2697 = -intDiv_rg_quo ; - assign x__h2767 = -rg_v1 ; - assign x__h2782 = intDiv_rg_quo + intDiv_rg_n ; - assign y__h2490 = { 1'd0, rg_v1[31:1] } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (intDiv_rg_state$EN) - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY intDiv_rg_state$D_IN; - end - if (intDiv_rg_denom2$EN) - intDiv_rg_denom2 <= `BSV_ASSIGNMENT_DELAY intDiv_rg_denom2$D_IN; - if (intDiv_rg_denom_is_signed$EN) - intDiv_rg_denom_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_denom_is_signed$D_IN; - if (intDiv_rg_n$EN) intDiv_rg_n <= `BSV_ASSIGNMENT_DELAY intDiv_rg_n$D_IN; - if (intDiv_rg_numer_is_signed$EN) - intDiv_rg_numer_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_numer_is_signed$D_IN; - if (intDiv_rg_quo$EN) - intDiv_rg_quo <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quo$D_IN; - if (intDiv_rg_quoIsNeg$EN) - intDiv_rg_quoIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quoIsNeg$D_IN; - if (intDiv_rg_remIsNeg$EN) - intDiv_rg_remIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_remIsNeg$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_is_OP_not_OP_32$EN) - rg_is_OP_not_OP_32 <= `BSV_ASSIGNMENT_DELAY rg_is_OP_not_OP_32$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_v1$EN) rg_v1 <= `BSV_ASSIGNMENT_DELAY rg_v1$D_IN; - if (rg_v2$EN) rg_v2 <= `BSV_ASSIGNMENT_DELAY rg_v2$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - intDiv_rg_denom2 = 32'hAAAAAAAA; - intDiv_rg_denom_is_signed = 1'h0; - intDiv_rg_n = 32'hAAAAAAAA; - intDiv_rg_numer_is_signed = 1'h0; - intDiv_rg_quo = 32'hAAAAAAAA; - intDiv_rg_quoIsNeg = 1'h0; - intDiv_rg_remIsNeg = 1'h0; - intDiv_rg_state = 3'h2; - rg_f3 = 3'h2; - rg_is_OP_not_OP_32 = 1'h0; - rg_state = 2'h2; - rg_v1 = 32'hAAAAAAAA; - rg_v2 = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && cfg_verbosity > 4'd1) - $display(" RISCV_MBox.rl_mul"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - begin - v__h3263 = $stime; - #0; - end - v__h3257 = v__h3263 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $display("%0d: ERROR: RISCV_MBox.rl_mul: illegal f3.", v__h3257); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $display(" f3 0x%0h v1 0x%0h v2 0x%0h", rg_f3, rg_v1, rg_v2); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkRISCV_MBox - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v deleted file mode 100644 index c88e21cd..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v +++ /dev/null @@ -1,298 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// m_near_mem_io_addr_base O 64 const -// m_near_mem_io_addr_size O 64 const -// m_near_mem_io_addr_lim O 64 const -// m_plic_addr_base O 64 const -// m_plic_addr_size O 64 const -// m_plic_addr_lim O 64 const -// m_uart0_addr_base O 64 const -// m_uart0_addr_size O 64 const -// m_uart0_addr_lim O 64 const -// m_boot_rom_addr_base O 64 const -// m_boot_rom_addr_size O 64 const -// m_boot_rom_addr_lim O 64 const -// m_mem0_controller_addr_base O 64 const -// m_mem0_controller_addr_size O 64 const -// m_mem0_controller_addr_lim O 64 const -// m_tcm_addr_base O 64 const -// m_tcm_addr_size O 64 const -// m_tcm_addr_lim O 64 const -// m_is_mem_addr O 1 -// m_is_IO_addr O 1 -// m_is_near_mem_IO_addr O 1 -// m_pc_reset_value O 64 const -// m_mtvec_reset_value O 64 const -// m_nmivec_reset_value O 64 const -// CLK I 1 unused -// RST_N I 1 unused -// m_is_mem_addr_addr I 64 -// m_is_IO_addr_addr I 64 -// m_is_near_mem_IO_addr_addr I 64 -// -// Combinational paths from inputs to outputs: -// m_is_mem_addr_addr -> m_is_mem_addr -// m_is_IO_addr_addr -> m_is_IO_addr -// m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Map(CLK, - RST_N, - - m_near_mem_io_addr_base, - - m_near_mem_io_addr_size, - - m_near_mem_io_addr_lim, - - m_plic_addr_base, - - m_plic_addr_size, - - m_plic_addr_lim, - - m_uart0_addr_base, - - m_uart0_addr_size, - - m_uart0_addr_lim, - - m_boot_rom_addr_base, - - m_boot_rom_addr_size, - - m_boot_rom_addr_lim, - - m_mem0_controller_addr_base, - - m_mem0_controller_addr_size, - - m_mem0_controller_addr_lim, - - m_tcm_addr_base, - - m_tcm_addr_size, - - m_tcm_addr_lim, - - m_is_mem_addr_addr, - m_is_mem_addr, - - m_is_IO_addr_addr, - m_is_IO_addr, - - m_is_near_mem_IO_addr_addr, - m_is_near_mem_IO_addr, - - m_pc_reset_value, - - m_mtvec_reset_value, - - m_nmivec_reset_value); - input CLK; - input RST_N; - - // value method m_near_mem_io_addr_base - output [63 : 0] m_near_mem_io_addr_base; - - // value method m_near_mem_io_addr_size - output [63 : 0] m_near_mem_io_addr_size; - - // value method m_near_mem_io_addr_lim - output [63 : 0] m_near_mem_io_addr_lim; - - // value method m_plic_addr_base - output [63 : 0] m_plic_addr_base; - - // value method m_plic_addr_size - output [63 : 0] m_plic_addr_size; - - // value method m_plic_addr_lim - output [63 : 0] m_plic_addr_lim; - - // value method m_uart0_addr_base - output [63 : 0] m_uart0_addr_base; - - // value method m_uart0_addr_size - output [63 : 0] m_uart0_addr_size; - - // value method m_uart0_addr_lim - output [63 : 0] m_uart0_addr_lim; - - // value method m_boot_rom_addr_base - output [63 : 0] m_boot_rom_addr_base; - - // value method m_boot_rom_addr_size - output [63 : 0] m_boot_rom_addr_size; - - // value method m_boot_rom_addr_lim - output [63 : 0] m_boot_rom_addr_lim; - - // value method m_mem0_controller_addr_base - output [63 : 0] m_mem0_controller_addr_base; - - // value method m_mem0_controller_addr_size - output [63 : 0] m_mem0_controller_addr_size; - - // value method m_mem0_controller_addr_lim - output [63 : 0] m_mem0_controller_addr_lim; - - // value method m_tcm_addr_base - output [63 : 0] m_tcm_addr_base; - - // value method m_tcm_addr_size - output [63 : 0] m_tcm_addr_size; - - // value method m_tcm_addr_lim - output [63 : 0] m_tcm_addr_lim; - - // value method m_is_mem_addr - input [63 : 0] m_is_mem_addr_addr; - output m_is_mem_addr; - - // value method m_is_IO_addr - input [63 : 0] m_is_IO_addr_addr; - output m_is_IO_addr; - - // value method m_is_near_mem_IO_addr - input [63 : 0] m_is_near_mem_IO_addr_addr; - output m_is_near_mem_IO_addr; - - // value method m_pc_reset_value - output [63 : 0] m_pc_reset_value; - - // value method m_mtvec_reset_value - output [63 : 0] m_mtvec_reset_value; - - // value method m_nmivec_reset_value - output [63 : 0] m_nmivec_reset_value; - - // signals for module outputs - wire [63 : 0] m_boot_rom_addr_base, - m_boot_rom_addr_lim, - m_boot_rom_addr_size, - m_mem0_controller_addr_base, - m_mem0_controller_addr_lim, - m_mem0_controller_addr_size, - m_mtvec_reset_value, - m_near_mem_io_addr_base, - m_near_mem_io_addr_lim, - m_near_mem_io_addr_size, - m_nmivec_reset_value, - m_pc_reset_value, - m_plic_addr_base, - m_plic_addr_lim, - m_plic_addr_size, - m_tcm_addr_base, - m_tcm_addr_lim, - m_tcm_addr_size, - m_uart0_addr_base, - m_uart0_addr_lim, - m_uart0_addr_size; - wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; - - // value method m_near_mem_io_addr_base - assign m_near_mem_io_addr_base = 64'h0000000002000000 ; - - // value method m_near_mem_io_addr_size - assign m_near_mem_io_addr_size = 64'h000000000000C000 ; - - // value method m_near_mem_io_addr_lim - assign m_near_mem_io_addr_lim = 64'd33603584 ; - - // value method m_plic_addr_base - assign m_plic_addr_base = 64'h000000000C000000 ; - - // value method m_plic_addr_size - assign m_plic_addr_size = 64'h0000000000400000 ; - - // value method m_plic_addr_lim - assign m_plic_addr_lim = 64'd205520896 ; - - // value method m_uart0_addr_base - assign m_uart0_addr_base = 64'h00000000C0000000 ; - - // value method m_uart0_addr_size - assign m_uart0_addr_size = 64'h0000000000000080 ; - - // value method m_uart0_addr_lim - assign m_uart0_addr_lim = 64'h00000000C0000080 ; - - // value method m_boot_rom_addr_base - assign m_boot_rom_addr_base = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_size - assign m_boot_rom_addr_size = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_lim - assign m_boot_rom_addr_lim = 64'd8192 ; - - // value method m_mem0_controller_addr_base - assign m_mem0_controller_addr_base = 64'h0000000080000000 ; - - // value method m_mem0_controller_addr_size - assign m_mem0_controller_addr_size = 64'h0000000010000000 ; - - // value method m_mem0_controller_addr_lim - assign m_mem0_controller_addr_lim = 64'h0000000090000000 ; - - // value method m_tcm_addr_base - assign m_tcm_addr_base = 64'h0 ; - - // value method m_tcm_addr_size - assign m_tcm_addr_size = 64'd0 ; - - // value method m_tcm_addr_lim - assign m_tcm_addr_lim = 64'd0 ; - - // value method m_is_mem_addr - assign m_is_mem_addr = - m_is_mem_addr_addr >= 64'h0000000000001000 && - m_is_mem_addr_addr < 64'd8192 || - m_is_mem_addr_addr >= 64'h0000000080000000 && - m_is_mem_addr_addr < 64'h0000000090000000 ; - - // value method m_is_IO_addr - assign m_is_IO_addr = - m_is_IO_addr_addr >= 64'h0000000002000000 && - m_is_IO_addr_addr < 64'd33603584 || - m_is_IO_addr_addr >= 64'h000000000C000000 && - m_is_IO_addr_addr < 64'd205520896 || - m_is_IO_addr_addr >= 64'h00000000C0000000 && - m_is_IO_addr_addr < 64'h00000000C0000080 ; - - // value method m_is_near_mem_IO_addr - assign m_is_near_mem_IO_addr = - m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 && - m_is_near_mem_IO_addr_addr < 64'd33603584 ; - - // value method m_pc_reset_value - assign m_pc_reset_value = 64'h0000000000001000 ; - - // value method m_mtvec_reset_value - assign m_mtvec_reset_value = 64'h0000000000001000 ; - - // value method m_nmivec_reset_value - assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ; -endmodule // mkSoC_Map - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v deleted file mode 100644 index 42e03763..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v +++ /dev/null @@ -1,2333 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// to_raw_mem_response_put I 256 -// put_from_console_put I 8 reg -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_set_verbosity I 1 -// EN_to_raw_mem_response_put I 1 -// EN_put_from_console_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Top(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [7 : 0] get_to_console_get, status; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_set_verbosity, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule boot_rom - wire [63 : 0] boot_rom$set_addr_map_addr_base, - boot_rom$set_addr_map_addr_lim, - boot_rom$slave_araddr, - boot_rom$slave_awaddr, - boot_rom$slave_rdata, - boot_rom$slave_wdata; - wire [7 : 0] boot_rom$slave_arlen, - boot_rom$slave_awlen, - boot_rom$slave_wstrb; - wire [3 : 0] boot_rom$slave_arcache, - boot_rom$slave_arid, - boot_rom$slave_arqos, - boot_rom$slave_arregion, - boot_rom$slave_awcache, - boot_rom$slave_awid, - boot_rom$slave_awqos, - boot_rom$slave_awregion, - boot_rom$slave_bid, - boot_rom$slave_rid, - boot_rom$slave_wid; - wire [2 : 0] boot_rom$slave_arprot, - boot_rom$slave_arsize, - boot_rom$slave_awprot, - boot_rom$slave_awsize; - wire [1 : 0] boot_rom$slave_arburst, - boot_rom$slave_awburst, - boot_rom$slave_bresp, - boot_rom$slave_rresp; - wire boot_rom$EN_set_addr_map, - boot_rom$slave_arlock, - boot_rom$slave_arready, - boot_rom$slave_arvalid, - boot_rom$slave_awlock, - boot_rom$slave_awready, - boot_rom$slave_awvalid, - boot_rom$slave_bready, - boot_rom$slave_bvalid, - boot_rom$slave_rlast, - boot_rom$slave_rready, - boot_rom$slave_rvalid, - boot_rom$slave_wlast, - boot_rom$slave_wready, - boot_rom$slave_wvalid; - - // ports of submodule boot_rom_axi4_deburster - wire [63 : 0] boot_rom_axi4_deburster$from_master_araddr, - boot_rom_axi4_deburster$from_master_awaddr, - boot_rom_axi4_deburster$from_master_rdata, - boot_rom_axi4_deburster$from_master_wdata, - boot_rom_axi4_deburster$to_slave_araddr, - boot_rom_axi4_deburster$to_slave_awaddr, - boot_rom_axi4_deburster$to_slave_rdata, - boot_rom_axi4_deburster$to_slave_wdata; - wire [7 : 0] boot_rom_axi4_deburster$from_master_arlen, - boot_rom_axi4_deburster$from_master_awlen, - boot_rom_axi4_deburster$from_master_wstrb, - boot_rom_axi4_deburster$to_slave_arlen, - boot_rom_axi4_deburster$to_slave_awlen, - boot_rom_axi4_deburster$to_slave_wstrb; - wire [3 : 0] boot_rom_axi4_deburster$from_master_arcache, - boot_rom_axi4_deburster$from_master_arid, - boot_rom_axi4_deburster$from_master_arqos, - boot_rom_axi4_deburster$from_master_arregion, - boot_rom_axi4_deburster$from_master_awcache, - boot_rom_axi4_deburster$from_master_awid, - boot_rom_axi4_deburster$from_master_awqos, - boot_rom_axi4_deburster$from_master_awregion, - boot_rom_axi4_deburster$from_master_bid, - boot_rom_axi4_deburster$from_master_rid, - boot_rom_axi4_deburster$from_master_wid, - boot_rom_axi4_deburster$to_slave_arcache, - boot_rom_axi4_deburster$to_slave_arid, - boot_rom_axi4_deburster$to_slave_arqos, - boot_rom_axi4_deburster$to_slave_arregion, - boot_rom_axi4_deburster$to_slave_awcache, - boot_rom_axi4_deburster$to_slave_awid, - boot_rom_axi4_deburster$to_slave_awqos, - boot_rom_axi4_deburster$to_slave_awregion, - boot_rom_axi4_deburster$to_slave_bid, - boot_rom_axi4_deburster$to_slave_rid, - boot_rom_axi4_deburster$to_slave_wid; - wire [2 : 0] boot_rom_axi4_deburster$from_master_arprot, - boot_rom_axi4_deburster$from_master_arsize, - boot_rom_axi4_deburster$from_master_awprot, - boot_rom_axi4_deburster$from_master_awsize, - boot_rom_axi4_deburster$to_slave_arprot, - boot_rom_axi4_deburster$to_slave_arsize, - boot_rom_axi4_deburster$to_slave_awprot, - boot_rom_axi4_deburster$to_slave_awsize; - wire [1 : 0] boot_rom_axi4_deburster$from_master_arburst, - boot_rom_axi4_deburster$from_master_awburst, - boot_rom_axi4_deburster$from_master_bresp, - boot_rom_axi4_deburster$from_master_rresp, - boot_rom_axi4_deburster$to_slave_arburst, - boot_rom_axi4_deburster$to_slave_awburst, - boot_rom_axi4_deburster$to_slave_bresp, - boot_rom_axi4_deburster$to_slave_rresp; - wire boot_rom_axi4_deburster$EN_reset, - boot_rom_axi4_deburster$from_master_arlock, - boot_rom_axi4_deburster$from_master_arready, - boot_rom_axi4_deburster$from_master_arvalid, - boot_rom_axi4_deburster$from_master_awlock, - boot_rom_axi4_deburster$from_master_awready, - boot_rom_axi4_deburster$from_master_awvalid, - boot_rom_axi4_deburster$from_master_bready, - boot_rom_axi4_deburster$from_master_bvalid, - boot_rom_axi4_deburster$from_master_rlast, - boot_rom_axi4_deburster$from_master_rready, - boot_rom_axi4_deburster$from_master_rvalid, - boot_rom_axi4_deburster$from_master_wlast, - boot_rom_axi4_deburster$from_master_wready, - boot_rom_axi4_deburster$from_master_wvalid, - boot_rom_axi4_deburster$to_slave_arlock, - boot_rom_axi4_deburster$to_slave_arready, - boot_rom_axi4_deburster$to_slave_arvalid, - boot_rom_axi4_deburster$to_slave_awlock, - boot_rom_axi4_deburster$to_slave_awready, - boot_rom_axi4_deburster$to_slave_awvalid, - boot_rom_axi4_deburster$to_slave_bready, - boot_rom_axi4_deburster$to_slave_bvalid, - boot_rom_axi4_deburster$to_slave_rlast, - boot_rom_axi4_deburster$to_slave_rready, - boot_rom_axi4_deburster$to_slave_rvalid, - boot_rom_axi4_deburster$to_slave_wlast, - boot_rom_axi4_deburster$to_slave_wready, - boot_rom_axi4_deburster$to_slave_wvalid; - - // ports of submodule core - wire [63 : 0] core$cpu_dmem_master_araddr, - core$cpu_dmem_master_awaddr, - core$cpu_dmem_master_rdata, - core$cpu_dmem_master_wdata, - core$cpu_imem_master_araddr, - core$cpu_imem_master_awaddr, - core$cpu_imem_master_rdata, - core$cpu_imem_master_wdata, - core$set_verbosity_logdelay; - wire [7 : 0] core$cpu_dmem_master_arlen, - core$cpu_dmem_master_awlen, - core$cpu_dmem_master_wstrb, - core$cpu_imem_master_arlen, - core$cpu_imem_master_awlen, - core$cpu_imem_master_wstrb; - wire [3 : 0] core$cpu_dmem_master_arcache, - core$cpu_dmem_master_arid, - core$cpu_dmem_master_arqos, - core$cpu_dmem_master_arregion, - core$cpu_dmem_master_awcache, - core$cpu_dmem_master_awid, - core$cpu_dmem_master_awqos, - core$cpu_dmem_master_awregion, - core$cpu_dmem_master_bid, - core$cpu_dmem_master_rid, - core$cpu_dmem_master_wid, - core$cpu_imem_master_arcache, - core$cpu_imem_master_arid, - core$cpu_imem_master_arqos, - core$cpu_imem_master_arregion, - core$cpu_imem_master_awcache, - core$cpu_imem_master_awid, - core$cpu_imem_master_awqos, - core$cpu_imem_master_awregion, - core$cpu_imem_master_bid, - core$cpu_imem_master_rid, - core$cpu_imem_master_wid, - core$set_verbosity_verbosity; - wire [2 : 0] core$cpu_dmem_master_arprot, - core$cpu_dmem_master_arsize, - core$cpu_dmem_master_awprot, - core$cpu_dmem_master_awsize, - core$cpu_imem_master_arprot, - core$cpu_imem_master_arsize, - core$cpu_imem_master_awprot, - core$cpu_imem_master_awsize; - wire [1 : 0] core$cpu_dmem_master_arburst, - core$cpu_dmem_master_awburst, - core$cpu_dmem_master_bresp, - core$cpu_dmem_master_rresp, - core$cpu_imem_master_arburst, - core$cpu_imem_master_awburst, - core$cpu_imem_master_bresp, - core$cpu_imem_master_rresp; - wire core$EN_cpu_reset_server_request_put, - core$EN_cpu_reset_server_response_get, - core$EN_set_verbosity, - core$RDY_cpu_reset_server_request_put, - core$RDY_cpu_reset_server_response_get, - core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - core$cpu_dmem_master_arlock, - core$cpu_dmem_master_arready, - core$cpu_dmem_master_arvalid, - core$cpu_dmem_master_awlock, - core$cpu_dmem_master_awready, - core$cpu_dmem_master_awvalid, - core$cpu_dmem_master_bready, - core$cpu_dmem_master_bvalid, - core$cpu_dmem_master_rlast, - core$cpu_dmem_master_rready, - core$cpu_dmem_master_rvalid, - core$cpu_dmem_master_wlast, - core$cpu_dmem_master_wready, - core$cpu_dmem_master_wvalid, - core$cpu_imem_master_arlock, - core$cpu_imem_master_arready, - core$cpu_imem_master_arvalid, - core$cpu_imem_master_awlock, - core$cpu_imem_master_awready, - core$cpu_imem_master_awvalid, - core$cpu_imem_master_bready, - core$cpu_imem_master_bvalid, - core$cpu_imem_master_rlast, - core$cpu_imem_master_rready, - core$cpu_imem_master_rvalid, - core$cpu_imem_master_wlast, - core$cpu_imem_master_wready, - core$cpu_imem_master_wvalid, - core$cpu_reset_server_request_put, - core$nmi_req_set_not_clear; - - // ports of submodule fabric - wire [63 : 0] fabric$v_from_masters_0_araddr, - fabric$v_from_masters_0_awaddr, - fabric$v_from_masters_0_rdata, - fabric$v_from_masters_0_wdata, - fabric$v_from_masters_1_araddr, - fabric$v_from_masters_1_awaddr, - fabric$v_from_masters_1_rdata, - fabric$v_from_masters_1_wdata, - fabric$v_to_slaves_0_araddr, - fabric$v_to_slaves_0_awaddr, - fabric$v_to_slaves_0_rdata, - fabric$v_to_slaves_0_wdata, - fabric$v_to_slaves_1_araddr, - fabric$v_to_slaves_1_awaddr, - fabric$v_to_slaves_1_rdata, - fabric$v_to_slaves_1_wdata, - fabric$v_to_slaves_2_araddr, - fabric$v_to_slaves_2_awaddr, - fabric$v_to_slaves_2_rdata, - fabric$v_to_slaves_2_wdata; - wire [7 : 0] fabric$v_from_masters_0_arlen, - fabric$v_from_masters_0_awlen, - fabric$v_from_masters_0_wstrb, - fabric$v_from_masters_1_arlen, - fabric$v_from_masters_1_awlen, - fabric$v_from_masters_1_wstrb, - fabric$v_to_slaves_0_arlen, - fabric$v_to_slaves_0_awlen, - fabric$v_to_slaves_0_wstrb, - fabric$v_to_slaves_1_arlen, - fabric$v_to_slaves_1_awlen, - fabric$v_to_slaves_1_wstrb, - fabric$v_to_slaves_2_arlen, - fabric$v_to_slaves_2_awlen, - fabric$v_to_slaves_2_wstrb; - wire [3 : 0] fabric$set_verbosity_verbosity, - fabric$v_from_masters_0_arcache, - fabric$v_from_masters_0_arid, - fabric$v_from_masters_0_arqos, - fabric$v_from_masters_0_arregion, - fabric$v_from_masters_0_awcache, - fabric$v_from_masters_0_awid, - fabric$v_from_masters_0_awqos, - fabric$v_from_masters_0_awregion, - fabric$v_from_masters_0_bid, - fabric$v_from_masters_0_rid, - fabric$v_from_masters_0_wid, - fabric$v_from_masters_1_arcache, - fabric$v_from_masters_1_arid, - fabric$v_from_masters_1_arqos, - fabric$v_from_masters_1_arregion, - fabric$v_from_masters_1_awcache, - fabric$v_from_masters_1_awid, - fabric$v_from_masters_1_awqos, - fabric$v_from_masters_1_awregion, - fabric$v_from_masters_1_bid, - fabric$v_from_masters_1_rid, - fabric$v_from_masters_1_wid, - fabric$v_to_slaves_0_arcache, - fabric$v_to_slaves_0_arid, - fabric$v_to_slaves_0_arqos, - fabric$v_to_slaves_0_arregion, - fabric$v_to_slaves_0_awcache, - fabric$v_to_slaves_0_awid, - fabric$v_to_slaves_0_awqos, - fabric$v_to_slaves_0_awregion, - fabric$v_to_slaves_0_bid, - fabric$v_to_slaves_0_rid, - fabric$v_to_slaves_0_wid, - fabric$v_to_slaves_1_arcache, - fabric$v_to_slaves_1_arid, - fabric$v_to_slaves_1_arqos, - fabric$v_to_slaves_1_arregion, - fabric$v_to_slaves_1_awcache, - fabric$v_to_slaves_1_awid, - fabric$v_to_slaves_1_awqos, - fabric$v_to_slaves_1_awregion, - fabric$v_to_slaves_1_bid, - fabric$v_to_slaves_1_rid, - fabric$v_to_slaves_1_wid, - fabric$v_to_slaves_2_arcache, - fabric$v_to_slaves_2_arid, - fabric$v_to_slaves_2_arqos, - fabric$v_to_slaves_2_arregion, - fabric$v_to_slaves_2_awcache, - fabric$v_to_slaves_2_awid, - fabric$v_to_slaves_2_awqos, - fabric$v_to_slaves_2_awregion, - fabric$v_to_slaves_2_bid, - fabric$v_to_slaves_2_rid, - fabric$v_to_slaves_2_wid; - wire [2 : 0] fabric$v_from_masters_0_arprot, - fabric$v_from_masters_0_arsize, - fabric$v_from_masters_0_awprot, - fabric$v_from_masters_0_awsize, - fabric$v_from_masters_1_arprot, - fabric$v_from_masters_1_arsize, - fabric$v_from_masters_1_awprot, - fabric$v_from_masters_1_awsize, - fabric$v_to_slaves_0_arprot, - fabric$v_to_slaves_0_arsize, - fabric$v_to_slaves_0_awprot, - fabric$v_to_slaves_0_awsize, - fabric$v_to_slaves_1_arprot, - fabric$v_to_slaves_1_arsize, - fabric$v_to_slaves_1_awprot, - fabric$v_to_slaves_1_awsize, - fabric$v_to_slaves_2_arprot, - fabric$v_to_slaves_2_arsize, - fabric$v_to_slaves_2_awprot, - fabric$v_to_slaves_2_awsize; - wire [1 : 0] fabric$v_from_masters_0_arburst, - fabric$v_from_masters_0_awburst, - fabric$v_from_masters_0_bresp, - fabric$v_from_masters_0_rresp, - fabric$v_from_masters_1_arburst, - fabric$v_from_masters_1_awburst, - fabric$v_from_masters_1_bresp, - fabric$v_from_masters_1_rresp, - fabric$v_to_slaves_0_arburst, - fabric$v_to_slaves_0_awburst, - fabric$v_to_slaves_0_bresp, - fabric$v_to_slaves_0_rresp, - fabric$v_to_slaves_1_arburst, - fabric$v_to_slaves_1_awburst, - fabric$v_to_slaves_1_bresp, - fabric$v_to_slaves_1_rresp, - fabric$v_to_slaves_2_arburst, - fabric$v_to_slaves_2_awburst, - fabric$v_to_slaves_2_bresp, - fabric$v_to_slaves_2_rresp; - wire fabric$EN_reset, - fabric$EN_set_verbosity, - fabric$RDY_reset, - fabric$v_from_masters_0_arlock, - fabric$v_from_masters_0_arready, - fabric$v_from_masters_0_arvalid, - fabric$v_from_masters_0_awlock, - fabric$v_from_masters_0_awready, - fabric$v_from_masters_0_awvalid, - fabric$v_from_masters_0_bready, - fabric$v_from_masters_0_bvalid, - fabric$v_from_masters_0_rlast, - fabric$v_from_masters_0_rready, - fabric$v_from_masters_0_rvalid, - fabric$v_from_masters_0_wlast, - fabric$v_from_masters_0_wready, - fabric$v_from_masters_0_wvalid, - fabric$v_from_masters_1_arlock, - fabric$v_from_masters_1_arready, - fabric$v_from_masters_1_arvalid, - fabric$v_from_masters_1_awlock, - fabric$v_from_masters_1_awready, - fabric$v_from_masters_1_awvalid, - fabric$v_from_masters_1_bready, - fabric$v_from_masters_1_bvalid, - fabric$v_from_masters_1_rlast, - fabric$v_from_masters_1_rready, - fabric$v_from_masters_1_rvalid, - fabric$v_from_masters_1_wlast, - fabric$v_from_masters_1_wready, - fabric$v_from_masters_1_wvalid, - fabric$v_to_slaves_0_arlock, - fabric$v_to_slaves_0_arready, - fabric$v_to_slaves_0_arvalid, - fabric$v_to_slaves_0_awlock, - fabric$v_to_slaves_0_awready, - fabric$v_to_slaves_0_awvalid, - fabric$v_to_slaves_0_bready, - fabric$v_to_slaves_0_bvalid, - fabric$v_to_slaves_0_rlast, - fabric$v_to_slaves_0_rready, - fabric$v_to_slaves_0_rvalid, - fabric$v_to_slaves_0_wlast, - fabric$v_to_slaves_0_wready, - fabric$v_to_slaves_0_wvalid, - fabric$v_to_slaves_1_arlock, - fabric$v_to_slaves_1_arready, - fabric$v_to_slaves_1_arvalid, - fabric$v_to_slaves_1_awlock, - fabric$v_to_slaves_1_awready, - fabric$v_to_slaves_1_awvalid, - fabric$v_to_slaves_1_bready, - fabric$v_to_slaves_1_bvalid, - fabric$v_to_slaves_1_rlast, - fabric$v_to_slaves_1_rready, - fabric$v_to_slaves_1_rvalid, - fabric$v_to_slaves_1_wlast, - fabric$v_to_slaves_1_wready, - fabric$v_to_slaves_1_wvalid, - fabric$v_to_slaves_2_arlock, - fabric$v_to_slaves_2_arready, - fabric$v_to_slaves_2_arvalid, - fabric$v_to_slaves_2_awlock, - fabric$v_to_slaves_2_awready, - fabric$v_to_slaves_2_awvalid, - fabric$v_to_slaves_2_bready, - fabric$v_to_slaves_2_bvalid, - fabric$v_to_slaves_2_rlast, - fabric$v_to_slaves_2_rready, - fabric$v_to_slaves_2_rvalid, - fabric$v_to_slaves_2_wlast, - fabric$v_to_slaves_2_wready, - fabric$v_to_slaves_2_wvalid; - - // ports of submodule mem0_controller - wire [352 : 0] mem0_controller$to_raw_mem_request_get; - wire [255 : 0] mem0_controller$to_raw_mem_response_put; - wire [63 : 0] mem0_controller$set_addr_map_addr_base, - mem0_controller$set_addr_map_addr_lim, - mem0_controller$set_watch_tohost_tohost_addr, - mem0_controller$slave_araddr, - mem0_controller$slave_awaddr, - mem0_controller$slave_rdata, - mem0_controller$slave_wdata; - wire [7 : 0] mem0_controller$slave_arlen, - mem0_controller$slave_awlen, - mem0_controller$slave_wstrb, - mem0_controller$status; - wire [3 : 0] mem0_controller$slave_arcache, - mem0_controller$slave_arid, - mem0_controller$slave_arqos, - mem0_controller$slave_arregion, - mem0_controller$slave_awcache, - mem0_controller$slave_awid, - mem0_controller$slave_awqos, - mem0_controller$slave_awregion, - mem0_controller$slave_bid, - mem0_controller$slave_rid, - mem0_controller$slave_wid; - wire [2 : 0] mem0_controller$slave_arprot, - mem0_controller$slave_arsize, - mem0_controller$slave_awprot, - mem0_controller$slave_awsize; - wire [1 : 0] mem0_controller$slave_arburst, - mem0_controller$slave_awburst, - mem0_controller$slave_bresp, - mem0_controller$slave_rresp; - wire mem0_controller$EN_server_reset_request_put, - mem0_controller$EN_server_reset_response_get, - mem0_controller$EN_set_addr_map, - mem0_controller$EN_set_watch_tohost, - mem0_controller$EN_to_raw_mem_request_get, - mem0_controller$EN_to_raw_mem_response_put, - mem0_controller$RDY_server_reset_request_put, - mem0_controller$RDY_server_reset_response_get, - mem0_controller$RDY_set_addr_map, - mem0_controller$RDY_to_raw_mem_request_get, - mem0_controller$RDY_to_raw_mem_response_put, - mem0_controller$set_watch_tohost_watch_tohost, - mem0_controller$slave_arlock, - mem0_controller$slave_arready, - mem0_controller$slave_arvalid, - mem0_controller$slave_awlock, - mem0_controller$slave_awready, - mem0_controller$slave_awvalid, - mem0_controller$slave_bready, - mem0_controller$slave_bvalid, - mem0_controller$slave_rlast, - mem0_controller$slave_rready, - mem0_controller$slave_rvalid, - mem0_controller$slave_wlast, - mem0_controller$slave_wready, - mem0_controller$slave_wvalid; - - // ports of submodule mem0_controller_axi4_deburster - wire [63 : 0] mem0_controller_axi4_deburster$from_master_araddr, - mem0_controller_axi4_deburster$from_master_awaddr, - mem0_controller_axi4_deburster$from_master_rdata, - mem0_controller_axi4_deburster$from_master_wdata, - mem0_controller_axi4_deburster$to_slave_araddr, - mem0_controller_axi4_deburster$to_slave_awaddr, - mem0_controller_axi4_deburster$to_slave_rdata, - mem0_controller_axi4_deburster$to_slave_wdata; - wire [7 : 0] mem0_controller_axi4_deburster$from_master_arlen, - mem0_controller_axi4_deburster$from_master_awlen, - mem0_controller_axi4_deburster$from_master_wstrb, - mem0_controller_axi4_deburster$to_slave_arlen, - mem0_controller_axi4_deburster$to_slave_awlen, - mem0_controller_axi4_deburster$to_slave_wstrb; - wire [3 : 0] mem0_controller_axi4_deburster$from_master_arcache, - mem0_controller_axi4_deburster$from_master_arid, - mem0_controller_axi4_deburster$from_master_arqos, - mem0_controller_axi4_deburster$from_master_arregion, - mem0_controller_axi4_deburster$from_master_awcache, - mem0_controller_axi4_deburster$from_master_awid, - mem0_controller_axi4_deburster$from_master_awqos, - mem0_controller_axi4_deburster$from_master_awregion, - mem0_controller_axi4_deburster$from_master_bid, - mem0_controller_axi4_deburster$from_master_rid, - mem0_controller_axi4_deburster$from_master_wid, - mem0_controller_axi4_deburster$to_slave_arcache, - mem0_controller_axi4_deburster$to_slave_arid, - mem0_controller_axi4_deburster$to_slave_arqos, - mem0_controller_axi4_deburster$to_slave_arregion, - mem0_controller_axi4_deburster$to_slave_awcache, - mem0_controller_axi4_deburster$to_slave_awid, - mem0_controller_axi4_deburster$to_slave_awqos, - mem0_controller_axi4_deburster$to_slave_awregion, - mem0_controller_axi4_deburster$to_slave_bid, - mem0_controller_axi4_deburster$to_slave_rid, - mem0_controller_axi4_deburster$to_slave_wid; - wire [2 : 0] mem0_controller_axi4_deburster$from_master_arprot, - mem0_controller_axi4_deburster$from_master_arsize, - mem0_controller_axi4_deburster$from_master_awprot, - mem0_controller_axi4_deburster$from_master_awsize, - mem0_controller_axi4_deburster$to_slave_arprot, - mem0_controller_axi4_deburster$to_slave_arsize, - mem0_controller_axi4_deburster$to_slave_awprot, - mem0_controller_axi4_deburster$to_slave_awsize; - wire [1 : 0] mem0_controller_axi4_deburster$from_master_arburst, - mem0_controller_axi4_deburster$from_master_awburst, - mem0_controller_axi4_deburster$from_master_bresp, - mem0_controller_axi4_deburster$from_master_rresp, - mem0_controller_axi4_deburster$to_slave_arburst, - mem0_controller_axi4_deburster$to_slave_awburst, - mem0_controller_axi4_deburster$to_slave_bresp, - mem0_controller_axi4_deburster$to_slave_rresp; - wire mem0_controller_axi4_deburster$EN_reset, - mem0_controller_axi4_deburster$from_master_arlock, - mem0_controller_axi4_deburster$from_master_arready, - mem0_controller_axi4_deburster$from_master_arvalid, - mem0_controller_axi4_deburster$from_master_awlock, - mem0_controller_axi4_deburster$from_master_awready, - mem0_controller_axi4_deburster$from_master_awvalid, - mem0_controller_axi4_deburster$from_master_bready, - mem0_controller_axi4_deburster$from_master_bvalid, - mem0_controller_axi4_deburster$from_master_rlast, - mem0_controller_axi4_deburster$from_master_rready, - mem0_controller_axi4_deburster$from_master_rvalid, - mem0_controller_axi4_deburster$from_master_wlast, - mem0_controller_axi4_deburster$from_master_wready, - mem0_controller_axi4_deburster$from_master_wvalid, - mem0_controller_axi4_deburster$to_slave_arlock, - mem0_controller_axi4_deburster$to_slave_arready, - mem0_controller_axi4_deburster$to_slave_arvalid, - mem0_controller_axi4_deburster$to_slave_awlock, - mem0_controller_axi4_deburster$to_slave_awready, - mem0_controller_axi4_deburster$to_slave_awvalid, - mem0_controller_axi4_deburster$to_slave_bready, - mem0_controller_axi4_deburster$to_slave_bvalid, - mem0_controller_axi4_deburster$to_slave_rlast, - mem0_controller_axi4_deburster$to_slave_rready, - mem0_controller_axi4_deburster$to_slave_rvalid, - mem0_controller_axi4_deburster$to_slave_wlast, - mem0_controller_axi4_deburster$to_slave_wready, - mem0_controller_axi4_deburster$to_slave_wvalid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // ports of submodule uart0 - wire [63 : 0] uart0$set_addr_map_addr_base, - uart0$set_addr_map_addr_lim, - uart0$slave_araddr, - uart0$slave_awaddr, - uart0$slave_rdata, - uart0$slave_wdata; - wire [7 : 0] uart0$get_to_console_get, - uart0$put_from_console_put, - uart0$slave_arlen, - uart0$slave_awlen, - uart0$slave_wstrb; - wire [3 : 0] uart0$slave_arcache, - uart0$slave_arid, - uart0$slave_arqos, - uart0$slave_arregion, - uart0$slave_awcache, - uart0$slave_awid, - uart0$slave_awqos, - uart0$slave_awregion, - uart0$slave_bid, - uart0$slave_rid, - uart0$slave_wid; - wire [2 : 0] uart0$slave_arprot, - uart0$slave_arsize, - uart0$slave_awprot, - uart0$slave_awsize; - wire [1 : 0] uart0$slave_arburst, - uart0$slave_awburst, - uart0$slave_bresp, - uart0$slave_rresp; - wire uart0$EN_get_to_console_get, - uart0$EN_put_from_console_put, - uart0$EN_server_reset_request_put, - uart0$EN_server_reset_response_get, - uart0$EN_set_addr_map, - uart0$RDY_get_to_console_get, - uart0$RDY_put_from_console_put, - uart0$RDY_server_reset_request_put, - uart0$RDY_server_reset_response_get, - uart0$intr, - uart0$slave_arlock, - uart0$slave_arready, - uart0$slave_arvalid, - uart0$slave_awlock, - uart0$slave_awready, - uart0$slave_awvalid, - uart0$slave_bready, - uart0$slave_bvalid, - uart0$slave_rlast, - uart0$slave_rready, - uart0$slave_rvalid, - uart0$slave_wlast, - uart0$slave_wready, - uart0$slave_wvalid; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_connect_external_interrupt_requests, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_addr_channel_5, - CAN_FIRE_RL_rl_rd_addr_channel_6, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, - CAN_FIRE_RL_rl_rd_data_channel_5, - CAN_FIRE_RL_rl_rd_data_channel_6, - CAN_FIRE_RL_rl_reset_complete_initial, - CAN_FIRE_RL_rl_reset_start_initial, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_addr_channel_5, - CAN_FIRE_RL_rl_wr_addr_channel_6, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_data_channel_5, - CAN_FIRE_RL_rl_wr_data_channel_6, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, - CAN_FIRE_RL_rl_wr_response_channel_5, - CAN_FIRE_RL_rl_wr_response_channel_6, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_set_verbosity, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_connect_external_interrupt_requests, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_addr_channel_5, - WILL_FIRE_RL_rl_rd_addr_channel_6, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, - WILL_FIRE_RL_rl_rd_data_channel_5, - WILL_FIRE_RL_rl_rd_data_channel_6, - WILL_FIRE_RL_rl_reset_complete_initial, - WILL_FIRE_RL_rl_reset_start_initial, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_addr_channel_5, - WILL_FIRE_RL_rl_wr_addr_channel_6, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_data_channel_5, - WILL_FIRE_RL_rl_wr_data_channel_6, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, - WILL_FIRE_RL_rl_wr_response_channel_5, - WILL_FIRE_RL_rl_wr_response_channel_6, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_set_verbosity, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h11286; - reg [31 : 0] v__h11556; - reg [31 : 0] v__h11280; - reg [31 : 0] v__h11550; - // synopsys translate_on - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = mem0_controller$to_raw_mem_request_get ; - assign RDY_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign CAN_FIRE_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign CAN_FIRE_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // actionvalue method get_to_console_get - assign get_to_console_get = uart0$get_to_console_get ; - assign RDY_get_to_console_get = uart0$RDY_get_to_console_get ; - assign CAN_FIRE_get_to_console_get = uart0$RDY_get_to_console_get ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = uart0$RDY_put_from_console_put ; - assign CAN_FIRE_put_from_console_put = uart0$RDY_put_from_console_put ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method status - assign status = mem0_controller$status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule boot_rom - mkBoot_ROM boot_rom(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(boot_rom$set_addr_map_addr_base), - .set_addr_map_addr_lim(boot_rom$set_addr_map_addr_lim), - .slave_araddr(boot_rom$slave_araddr), - .slave_arburst(boot_rom$slave_arburst), - .slave_arcache(boot_rom$slave_arcache), - .slave_arid(boot_rom$slave_arid), - .slave_arlen(boot_rom$slave_arlen), - .slave_arlock(boot_rom$slave_arlock), - .slave_arprot(boot_rom$slave_arprot), - .slave_arqos(boot_rom$slave_arqos), - .slave_arregion(boot_rom$slave_arregion), - .slave_arsize(boot_rom$slave_arsize), - .slave_arvalid(boot_rom$slave_arvalid), - .slave_awaddr(boot_rom$slave_awaddr), - .slave_awburst(boot_rom$slave_awburst), - .slave_awcache(boot_rom$slave_awcache), - .slave_awid(boot_rom$slave_awid), - .slave_awlen(boot_rom$slave_awlen), - .slave_awlock(boot_rom$slave_awlock), - .slave_awprot(boot_rom$slave_awprot), - .slave_awqos(boot_rom$slave_awqos), - .slave_awregion(boot_rom$slave_awregion), - .slave_awsize(boot_rom$slave_awsize), - .slave_awvalid(boot_rom$slave_awvalid), - .slave_bready(boot_rom$slave_bready), - .slave_rready(boot_rom$slave_rready), - .slave_wdata(boot_rom$slave_wdata), - .slave_wid(boot_rom$slave_wid), - .slave_wlast(boot_rom$slave_wlast), - .slave_wstrb(boot_rom$slave_wstrb), - .slave_wvalid(boot_rom$slave_wvalid), - .EN_set_addr_map(boot_rom$EN_set_addr_map), - .RDY_set_addr_map(), - .slave_awready(boot_rom$slave_awready), - .slave_wready(boot_rom$slave_wready), - .slave_bvalid(boot_rom$slave_bvalid), - .slave_bid(boot_rom$slave_bid), - .slave_bresp(boot_rom$slave_bresp), - .slave_arready(boot_rom$slave_arready), - .slave_rvalid(boot_rom$slave_rvalid), - .slave_rid(boot_rom$slave_rid), - .slave_rdata(boot_rom$slave_rdata), - .slave_rresp(boot_rom$slave_rresp), - .slave_rlast(boot_rom$slave_rlast)); - - // submodule boot_rom_axi4_deburster - mkAXI4_Deburster_A boot_rom_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(boot_rom_axi4_deburster$from_master_araddr), - .from_master_arburst(boot_rom_axi4_deburster$from_master_arburst), - .from_master_arcache(boot_rom_axi4_deburster$from_master_arcache), - .from_master_arid(boot_rom_axi4_deburster$from_master_arid), - .from_master_arlen(boot_rom_axi4_deburster$from_master_arlen), - .from_master_arlock(boot_rom_axi4_deburster$from_master_arlock), - .from_master_arprot(boot_rom_axi4_deburster$from_master_arprot), - .from_master_arqos(boot_rom_axi4_deburster$from_master_arqos), - .from_master_arregion(boot_rom_axi4_deburster$from_master_arregion), - .from_master_arsize(boot_rom_axi4_deburster$from_master_arsize), - .from_master_arvalid(boot_rom_axi4_deburster$from_master_arvalid), - .from_master_awaddr(boot_rom_axi4_deburster$from_master_awaddr), - .from_master_awburst(boot_rom_axi4_deburster$from_master_awburst), - .from_master_awcache(boot_rom_axi4_deburster$from_master_awcache), - .from_master_awid(boot_rom_axi4_deburster$from_master_awid), - .from_master_awlen(boot_rom_axi4_deburster$from_master_awlen), - .from_master_awlock(boot_rom_axi4_deburster$from_master_awlock), - .from_master_awprot(boot_rom_axi4_deburster$from_master_awprot), - .from_master_awqos(boot_rom_axi4_deburster$from_master_awqos), - .from_master_awregion(boot_rom_axi4_deburster$from_master_awregion), - .from_master_awsize(boot_rom_axi4_deburster$from_master_awsize), - .from_master_awvalid(boot_rom_axi4_deburster$from_master_awvalid), - .from_master_bready(boot_rom_axi4_deburster$from_master_bready), - .from_master_rready(boot_rom_axi4_deburster$from_master_rready), - .from_master_wdata(boot_rom_axi4_deburster$from_master_wdata), - .from_master_wid(boot_rom_axi4_deburster$from_master_wid), - .from_master_wlast(boot_rom_axi4_deburster$from_master_wlast), - .from_master_wstrb(boot_rom_axi4_deburster$from_master_wstrb), - .from_master_wvalid(boot_rom_axi4_deburster$from_master_wvalid), - .to_slave_arready(boot_rom_axi4_deburster$to_slave_arready), - .to_slave_awready(boot_rom_axi4_deburster$to_slave_awready), - .to_slave_bid(boot_rom_axi4_deburster$to_slave_bid), - .to_slave_bresp(boot_rom_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(boot_rom_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(boot_rom_axi4_deburster$to_slave_rdata), - .to_slave_rid(boot_rom_axi4_deburster$to_slave_rid), - .to_slave_rlast(boot_rom_axi4_deburster$to_slave_rlast), - .to_slave_rresp(boot_rom_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(boot_rom_axi4_deburster$to_slave_rvalid), - .to_slave_wready(boot_rom_axi4_deburster$to_slave_wready), - .EN_reset(boot_rom_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(boot_rom_axi4_deburster$from_master_awready), - .from_master_wready(boot_rom_axi4_deburster$from_master_wready), - .from_master_bvalid(boot_rom_axi4_deburster$from_master_bvalid), - .from_master_bid(boot_rom_axi4_deburster$from_master_bid), - .from_master_bresp(boot_rom_axi4_deburster$from_master_bresp), - .from_master_arready(boot_rom_axi4_deburster$from_master_arready), - .from_master_rvalid(boot_rom_axi4_deburster$from_master_rvalid), - .from_master_rid(boot_rom_axi4_deburster$from_master_rid), - .from_master_rdata(boot_rom_axi4_deburster$from_master_rdata), - .from_master_rresp(boot_rom_axi4_deburster$from_master_rresp), - .from_master_rlast(boot_rom_axi4_deburster$from_master_rlast), - .to_slave_awvalid(boot_rom_axi4_deburster$to_slave_awvalid), - .to_slave_awid(boot_rom_axi4_deburster$to_slave_awid), - .to_slave_awaddr(boot_rom_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(boot_rom_axi4_deburster$to_slave_awlen), - .to_slave_awsize(boot_rom_axi4_deburster$to_slave_awsize), - .to_slave_awburst(boot_rom_axi4_deburster$to_slave_awburst), - .to_slave_awlock(boot_rom_axi4_deburster$to_slave_awlock), - .to_slave_awcache(boot_rom_axi4_deburster$to_slave_awcache), - .to_slave_awprot(boot_rom_axi4_deburster$to_slave_awprot), - .to_slave_awqos(boot_rom_axi4_deburster$to_slave_awqos), - .to_slave_awregion(boot_rom_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(boot_rom_axi4_deburster$to_slave_wvalid), - .to_slave_wid(boot_rom_axi4_deburster$to_slave_wid), - .to_slave_wdata(boot_rom_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(boot_rom_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(boot_rom_axi4_deburster$to_slave_wlast), - .to_slave_bready(boot_rom_axi4_deburster$to_slave_bready), - .to_slave_arvalid(boot_rom_axi4_deburster$to_slave_arvalid), - .to_slave_arid(boot_rom_axi4_deburster$to_slave_arid), - .to_slave_araddr(boot_rom_axi4_deburster$to_slave_araddr), - .to_slave_arlen(boot_rom_axi4_deburster$to_slave_arlen), - .to_slave_arsize(boot_rom_axi4_deburster$to_slave_arsize), - .to_slave_arburst(boot_rom_axi4_deburster$to_slave_arburst), - .to_slave_arlock(boot_rom_axi4_deburster$to_slave_arlock), - .to_slave_arcache(boot_rom_axi4_deburster$to_slave_arcache), - .to_slave_arprot(boot_rom_axi4_deburster$to_slave_arprot), - .to_slave_arqos(boot_rom_axi4_deburster$to_slave_arqos), - .to_slave_arregion(boot_rom_axi4_deburster$to_slave_arregion), - .to_slave_rready(boot_rom_axi4_deburster$to_slave_rready)); - - // submodule core - mkCore core(.CLK(CLK), - .RST_N(RST_N), - .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_12_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_13_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_14_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_15_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_1_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_2_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_3_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_4_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_5_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_6_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_7_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_8_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_9_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear), - .cpu_dmem_master_arready(core$cpu_dmem_master_arready), - .cpu_dmem_master_awready(core$cpu_dmem_master_awready), - .cpu_dmem_master_bid(core$cpu_dmem_master_bid), - .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), - .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata), - .cpu_dmem_master_rid(core$cpu_dmem_master_rid), - .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast), - .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), - .cpu_dmem_master_wready(core$cpu_dmem_master_wready), - .cpu_imem_master_arready(core$cpu_imem_master_arready), - .cpu_imem_master_awready(core$cpu_imem_master_awready), - .cpu_imem_master_bid(core$cpu_imem_master_bid), - .cpu_imem_master_bresp(core$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), - .cpu_imem_master_rdata(core$cpu_imem_master_rdata), - .cpu_imem_master_rid(core$cpu_imem_master_rid), - .cpu_imem_master_rlast(core$cpu_imem_master_rlast), - .cpu_imem_master_rresp(core$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), - .cpu_imem_master_wready(core$cpu_imem_master_wready), - .cpu_reset_server_request_put(core$cpu_reset_server_request_put), - .nmi_req_set_not_clear(core$nmi_req_set_not_clear), - .set_verbosity_logdelay(core$set_verbosity_logdelay), - .set_verbosity_verbosity(core$set_verbosity_verbosity), - .EN_set_verbosity(core$EN_set_verbosity), - .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get), - .RDY_set_verbosity(), - .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put), - .cpu_reset_server_response_get(), - .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), - .cpu_imem_master_awid(core$cpu_imem_master_awid), - .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr), - .cpu_imem_master_awlen(core$cpu_imem_master_awlen), - .cpu_imem_master_awsize(core$cpu_imem_master_awsize), - .cpu_imem_master_awburst(core$cpu_imem_master_awburst), - .cpu_imem_master_awlock(core$cpu_imem_master_awlock), - .cpu_imem_master_awcache(core$cpu_imem_master_awcache), - .cpu_imem_master_awprot(core$cpu_imem_master_awprot), - .cpu_imem_master_awqos(core$cpu_imem_master_awqos), - .cpu_imem_master_awregion(core$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), - .cpu_imem_master_wid(core$cpu_imem_master_wid), - .cpu_imem_master_wdata(core$cpu_imem_master_wdata), - .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb), - .cpu_imem_master_wlast(core$cpu_imem_master_wlast), - .cpu_imem_master_bready(core$cpu_imem_master_bready), - .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), - .cpu_imem_master_arid(core$cpu_imem_master_arid), - .cpu_imem_master_araddr(core$cpu_imem_master_araddr), - .cpu_imem_master_arlen(core$cpu_imem_master_arlen), - .cpu_imem_master_arsize(core$cpu_imem_master_arsize), - .cpu_imem_master_arburst(core$cpu_imem_master_arburst), - .cpu_imem_master_arlock(core$cpu_imem_master_arlock), - .cpu_imem_master_arcache(core$cpu_imem_master_arcache), - .cpu_imem_master_arprot(core$cpu_imem_master_arprot), - .cpu_imem_master_arqos(core$cpu_imem_master_arqos), - .cpu_imem_master_arregion(core$cpu_imem_master_arregion), - .cpu_imem_master_rready(core$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), - .cpu_dmem_master_awid(core$cpu_dmem_master_awid), - .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr), - .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen), - .cpu_dmem_master_awsize(core$cpu_dmem_master_awsize), - .cpu_dmem_master_awburst(core$cpu_dmem_master_awburst), - .cpu_dmem_master_awlock(core$cpu_dmem_master_awlock), - .cpu_dmem_master_awcache(core$cpu_dmem_master_awcache), - .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot), - .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos), - .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(core$cpu_dmem_master_wid), - .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata), - .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb), - .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast), - .cpu_dmem_master_bready(core$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), - .cpu_dmem_master_arid(core$cpu_dmem_master_arid), - .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr), - .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen), - .cpu_dmem_master_arsize(core$cpu_dmem_master_arsize), - .cpu_dmem_master_arburst(core$cpu_dmem_master_arburst), - .cpu_dmem_master_arlock(core$cpu_dmem_master_arlock), - .cpu_dmem_master_arcache(core$cpu_dmem_master_arcache), - .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot), - .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos), - .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion), - .cpu_dmem_master_rready(core$cpu_dmem_master_rready)); - - // submodule fabric - mkFabric_AXI4 fabric(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric$v_to_slaves_2_wready), - .EN_reset(fabric$EN_reset), - .EN_set_verbosity(fabric$EN_set_verbosity), - .RDY_reset(fabric$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric$v_to_slaves_2_rready)); - - // submodule mem0_controller - mkMem_Controller mem0_controller(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(mem0_controller$set_addr_map_addr_base), - .set_addr_map_addr_lim(mem0_controller$set_addr_map_addr_lim), - .set_watch_tohost_tohost_addr(mem0_controller$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(mem0_controller$set_watch_tohost_watch_tohost), - .slave_araddr(mem0_controller$slave_araddr), - .slave_arburst(mem0_controller$slave_arburst), - .slave_arcache(mem0_controller$slave_arcache), - .slave_arid(mem0_controller$slave_arid), - .slave_arlen(mem0_controller$slave_arlen), - .slave_arlock(mem0_controller$slave_arlock), - .slave_arprot(mem0_controller$slave_arprot), - .slave_arqos(mem0_controller$slave_arqos), - .slave_arregion(mem0_controller$slave_arregion), - .slave_arsize(mem0_controller$slave_arsize), - .slave_arvalid(mem0_controller$slave_arvalid), - .slave_awaddr(mem0_controller$slave_awaddr), - .slave_awburst(mem0_controller$slave_awburst), - .slave_awcache(mem0_controller$slave_awcache), - .slave_awid(mem0_controller$slave_awid), - .slave_awlen(mem0_controller$slave_awlen), - .slave_awlock(mem0_controller$slave_awlock), - .slave_awprot(mem0_controller$slave_awprot), - .slave_awqos(mem0_controller$slave_awqos), - .slave_awregion(mem0_controller$slave_awregion), - .slave_awsize(mem0_controller$slave_awsize), - .slave_awvalid(mem0_controller$slave_awvalid), - .slave_bready(mem0_controller$slave_bready), - .slave_rready(mem0_controller$slave_rready), - .slave_wdata(mem0_controller$slave_wdata), - .slave_wid(mem0_controller$slave_wid), - .slave_wlast(mem0_controller$slave_wlast), - .slave_wstrb(mem0_controller$slave_wstrb), - .slave_wvalid(mem0_controller$slave_wvalid), - .to_raw_mem_response_put(mem0_controller$to_raw_mem_response_put), - .EN_server_reset_request_put(mem0_controller$EN_server_reset_request_put), - .EN_server_reset_response_get(mem0_controller$EN_server_reset_response_get), - .EN_set_addr_map(mem0_controller$EN_set_addr_map), - .EN_to_raw_mem_request_get(mem0_controller$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(mem0_controller$EN_to_raw_mem_response_put), - .EN_set_watch_tohost(mem0_controller$EN_set_watch_tohost), - .RDY_server_reset_request_put(mem0_controller$RDY_server_reset_request_put), - .RDY_server_reset_response_get(mem0_controller$RDY_server_reset_response_get), - .RDY_set_addr_map(mem0_controller$RDY_set_addr_map), - .slave_awready(mem0_controller$slave_awready), - .slave_wready(mem0_controller$slave_wready), - .slave_bvalid(mem0_controller$slave_bvalid), - .slave_bid(mem0_controller$slave_bid), - .slave_bresp(mem0_controller$slave_bresp), - .slave_arready(mem0_controller$slave_arready), - .slave_rvalid(mem0_controller$slave_rvalid), - .slave_rid(mem0_controller$slave_rid), - .slave_rdata(mem0_controller$slave_rdata), - .slave_rresp(mem0_controller$slave_rresp), - .slave_rlast(mem0_controller$slave_rlast), - .to_raw_mem_request_get(mem0_controller$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(mem0_controller$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(mem0_controller$RDY_to_raw_mem_response_put), - .status(mem0_controller$status), - .RDY_set_watch_tohost()); - - // submodule mem0_controller_axi4_deburster - mkAXI4_Deburster_A mem0_controller_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(mem0_controller_axi4_deburster$from_master_araddr), - .from_master_arburst(mem0_controller_axi4_deburster$from_master_arburst), - .from_master_arcache(mem0_controller_axi4_deburster$from_master_arcache), - .from_master_arid(mem0_controller_axi4_deburster$from_master_arid), - .from_master_arlen(mem0_controller_axi4_deburster$from_master_arlen), - .from_master_arlock(mem0_controller_axi4_deburster$from_master_arlock), - .from_master_arprot(mem0_controller_axi4_deburster$from_master_arprot), - .from_master_arqos(mem0_controller_axi4_deburster$from_master_arqos), - .from_master_arregion(mem0_controller_axi4_deburster$from_master_arregion), - .from_master_arsize(mem0_controller_axi4_deburster$from_master_arsize), - .from_master_arvalid(mem0_controller_axi4_deburster$from_master_arvalid), - .from_master_awaddr(mem0_controller_axi4_deburster$from_master_awaddr), - .from_master_awburst(mem0_controller_axi4_deburster$from_master_awburst), - .from_master_awcache(mem0_controller_axi4_deburster$from_master_awcache), - .from_master_awid(mem0_controller_axi4_deburster$from_master_awid), - .from_master_awlen(mem0_controller_axi4_deburster$from_master_awlen), - .from_master_awlock(mem0_controller_axi4_deburster$from_master_awlock), - .from_master_awprot(mem0_controller_axi4_deburster$from_master_awprot), - .from_master_awqos(mem0_controller_axi4_deburster$from_master_awqos), - .from_master_awregion(mem0_controller_axi4_deburster$from_master_awregion), - .from_master_awsize(mem0_controller_axi4_deburster$from_master_awsize), - .from_master_awvalid(mem0_controller_axi4_deburster$from_master_awvalid), - .from_master_bready(mem0_controller_axi4_deburster$from_master_bready), - .from_master_rready(mem0_controller_axi4_deburster$from_master_rready), - .from_master_wdata(mem0_controller_axi4_deburster$from_master_wdata), - .from_master_wid(mem0_controller_axi4_deburster$from_master_wid), - .from_master_wlast(mem0_controller_axi4_deburster$from_master_wlast), - .from_master_wstrb(mem0_controller_axi4_deburster$from_master_wstrb), - .from_master_wvalid(mem0_controller_axi4_deburster$from_master_wvalid), - .to_slave_arready(mem0_controller_axi4_deburster$to_slave_arready), - .to_slave_awready(mem0_controller_axi4_deburster$to_slave_awready), - .to_slave_bid(mem0_controller_axi4_deburster$to_slave_bid), - .to_slave_bresp(mem0_controller_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(mem0_controller_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(mem0_controller_axi4_deburster$to_slave_rdata), - .to_slave_rid(mem0_controller_axi4_deburster$to_slave_rid), - .to_slave_rlast(mem0_controller_axi4_deburster$to_slave_rlast), - .to_slave_rresp(mem0_controller_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(mem0_controller_axi4_deburster$to_slave_rvalid), - .to_slave_wready(mem0_controller_axi4_deburster$to_slave_wready), - .EN_reset(mem0_controller_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(mem0_controller_axi4_deburster$from_master_awready), - .from_master_wready(mem0_controller_axi4_deburster$from_master_wready), - .from_master_bvalid(mem0_controller_axi4_deburster$from_master_bvalid), - .from_master_bid(mem0_controller_axi4_deburster$from_master_bid), - .from_master_bresp(mem0_controller_axi4_deburster$from_master_bresp), - .from_master_arready(mem0_controller_axi4_deburster$from_master_arready), - .from_master_rvalid(mem0_controller_axi4_deburster$from_master_rvalid), - .from_master_rid(mem0_controller_axi4_deburster$from_master_rid), - .from_master_rdata(mem0_controller_axi4_deburster$from_master_rdata), - .from_master_rresp(mem0_controller_axi4_deburster$from_master_rresp), - .from_master_rlast(mem0_controller_axi4_deburster$from_master_rlast), - .to_slave_awvalid(mem0_controller_axi4_deburster$to_slave_awvalid), - .to_slave_awid(mem0_controller_axi4_deburster$to_slave_awid), - .to_slave_awaddr(mem0_controller_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(mem0_controller_axi4_deburster$to_slave_awlen), - .to_slave_awsize(mem0_controller_axi4_deburster$to_slave_awsize), - .to_slave_awburst(mem0_controller_axi4_deburster$to_slave_awburst), - .to_slave_awlock(mem0_controller_axi4_deburster$to_slave_awlock), - .to_slave_awcache(mem0_controller_axi4_deburster$to_slave_awcache), - .to_slave_awprot(mem0_controller_axi4_deburster$to_slave_awprot), - .to_slave_awqos(mem0_controller_axi4_deburster$to_slave_awqos), - .to_slave_awregion(mem0_controller_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(mem0_controller_axi4_deburster$to_slave_wvalid), - .to_slave_wid(mem0_controller_axi4_deburster$to_slave_wid), - .to_slave_wdata(mem0_controller_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(mem0_controller_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(mem0_controller_axi4_deburster$to_slave_wlast), - .to_slave_bready(mem0_controller_axi4_deburster$to_slave_bready), - .to_slave_arvalid(mem0_controller_axi4_deburster$to_slave_arvalid), - .to_slave_arid(mem0_controller_axi4_deburster$to_slave_arid), - .to_slave_araddr(mem0_controller_axi4_deburster$to_slave_araddr), - .to_slave_arlen(mem0_controller_axi4_deburster$to_slave_arlen), - .to_slave_arsize(mem0_controller_axi4_deburster$to_slave_arsize), - .to_slave_arburst(mem0_controller_axi4_deburster$to_slave_arburst), - .to_slave_arlock(mem0_controller_axi4_deburster$to_slave_arlock), - .to_slave_arcache(mem0_controller_axi4_deburster$to_slave_arcache), - .to_slave_arprot(mem0_controller_axi4_deburster$to_slave_arprot), - .to_slave_arqos(mem0_controller_axi4_deburster$to_slave_arqos), - .to_slave_arregion(mem0_controller_axi4_deburster$to_slave_arregion), - .to_slave_rready(mem0_controller_axi4_deburster$to_slave_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule uart0 - mkUART uart0(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(uart0$put_from_console_put), - .set_addr_map_addr_base(uart0$set_addr_map_addr_base), - .set_addr_map_addr_lim(uart0$set_addr_map_addr_lim), - .slave_araddr(uart0$slave_araddr), - .slave_arburst(uart0$slave_arburst), - .slave_arcache(uart0$slave_arcache), - .slave_arid(uart0$slave_arid), - .slave_arlen(uart0$slave_arlen), - .slave_arlock(uart0$slave_arlock), - .slave_arprot(uart0$slave_arprot), - .slave_arqos(uart0$slave_arqos), - .slave_arregion(uart0$slave_arregion), - .slave_arsize(uart0$slave_arsize), - .slave_arvalid(uart0$slave_arvalid), - .slave_awaddr(uart0$slave_awaddr), - .slave_awburst(uart0$slave_awburst), - .slave_awcache(uart0$slave_awcache), - .slave_awid(uart0$slave_awid), - .slave_awlen(uart0$slave_awlen), - .slave_awlock(uart0$slave_awlock), - .slave_awprot(uart0$slave_awprot), - .slave_awqos(uart0$slave_awqos), - .slave_awregion(uart0$slave_awregion), - .slave_awsize(uart0$slave_awsize), - .slave_awvalid(uart0$slave_awvalid), - .slave_bready(uart0$slave_bready), - .slave_rready(uart0$slave_rready), - .slave_wdata(uart0$slave_wdata), - .slave_wid(uart0$slave_wid), - .slave_wlast(uart0$slave_wlast), - .slave_wstrb(uart0$slave_wstrb), - .slave_wvalid(uart0$slave_wvalid), - .EN_server_reset_request_put(uart0$EN_server_reset_request_put), - .EN_server_reset_response_get(uart0$EN_server_reset_response_get), - .EN_set_addr_map(uart0$EN_set_addr_map), - .EN_get_to_console_get(uart0$EN_get_to_console_get), - .EN_put_from_console_put(uart0$EN_put_from_console_put), - .RDY_server_reset_request_put(uart0$RDY_server_reset_request_put), - .RDY_server_reset_response_get(uart0$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .slave_awready(uart0$slave_awready), - .slave_wready(uart0$slave_wready), - .slave_bvalid(uart0$slave_bvalid), - .slave_bid(uart0$slave_bid), - .slave_bresp(uart0$slave_bresp), - .slave_arready(uart0$slave_arready), - .slave_rvalid(uart0$slave_rvalid), - .slave_rid(uart0$slave_rid), - .slave_rdata(uart0$slave_rdata), - .slave_rresp(uart0$slave_rresp), - .slave_rlast(uart0$slave_rlast), - .get_to_console_get(uart0$get_to_console_get), - .RDY_get_to_console_get(uart0$RDY_get_to_console_get), - .RDY_put_from_console_put(uart0$RDY_put_from_console_put), - .intr(uart0$intr)); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_5 - assign CAN_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - - // rule RL_rl_wr_data_channel_5 - assign CAN_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_response_channel_5 - assign CAN_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_5 - assign CAN_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - - // rule RL_rl_rd_data_channel_5 - assign CAN_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_6 - assign CAN_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - - // rule RL_rl_wr_data_channel_6 - assign CAN_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - - // rule RL_rl_wr_response_channel_6 - assign CAN_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_6 - assign CAN_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - - // rule RL_rl_rd_data_channel_6 - assign CAN_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - - // rule RL_rl_connect_external_interrupt_requests - assign CAN_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - - // rule RL_rl_reset_start_initial - assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete_initial - assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete_initial = - MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = - mem0_controller$RDY_server_reset_request_put && - uart0$RDY_server_reset_request_put && - fabric$RDY_reset && - core$RDY_cpu_reset_server_request_put && - rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && - mem0_controller$RDY_server_reset_response_get && - uart0$RDY_server_reset_response_get && - core$RDY_cpu_reset_server_response_get && - rg_state == 2'd1 ; - - // register rg_state - assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_start_initial || - WILL_FIRE_RL_rl_reset_complete_initial ; - - // submodule boot_rom - assign boot_rom$set_addr_map_addr_base = soc_map$m_boot_rom_addr_base ; - assign boot_rom$set_addr_map_addr_lim = soc_map$m_boot_rom_addr_lim ; - assign boot_rom$slave_araddr = boot_rom_axi4_deburster$to_slave_araddr ; - assign boot_rom$slave_arburst = boot_rom_axi4_deburster$to_slave_arburst ; - assign boot_rom$slave_arcache = boot_rom_axi4_deburster$to_slave_arcache ; - assign boot_rom$slave_arid = boot_rom_axi4_deburster$to_slave_arid ; - assign boot_rom$slave_arlen = boot_rom_axi4_deburster$to_slave_arlen ; - assign boot_rom$slave_arlock = boot_rom_axi4_deburster$to_slave_arlock ; - assign boot_rom$slave_arprot = boot_rom_axi4_deburster$to_slave_arprot ; - assign boot_rom$slave_arqos = boot_rom_axi4_deburster$to_slave_arqos ; - assign boot_rom$slave_arregion = boot_rom_axi4_deburster$to_slave_arregion ; - assign boot_rom$slave_arsize = boot_rom_axi4_deburster$to_slave_arsize ; - assign boot_rom$slave_arvalid = boot_rom_axi4_deburster$to_slave_arvalid ; - assign boot_rom$slave_awaddr = boot_rom_axi4_deburster$to_slave_awaddr ; - assign boot_rom$slave_awburst = boot_rom_axi4_deburster$to_slave_awburst ; - assign boot_rom$slave_awcache = boot_rom_axi4_deburster$to_slave_awcache ; - assign boot_rom$slave_awid = boot_rom_axi4_deburster$to_slave_awid ; - assign boot_rom$slave_awlen = boot_rom_axi4_deburster$to_slave_awlen ; - assign boot_rom$slave_awlock = boot_rom_axi4_deburster$to_slave_awlock ; - assign boot_rom$slave_awprot = boot_rom_axi4_deburster$to_slave_awprot ; - assign boot_rom$slave_awqos = boot_rom_axi4_deburster$to_slave_awqos ; - assign boot_rom$slave_awregion = boot_rom_axi4_deburster$to_slave_awregion ; - assign boot_rom$slave_awsize = boot_rom_axi4_deburster$to_slave_awsize ; - assign boot_rom$slave_awvalid = boot_rom_axi4_deburster$to_slave_awvalid ; - assign boot_rom$slave_bready = boot_rom_axi4_deburster$to_slave_bready ; - assign boot_rom$slave_rready = boot_rom_axi4_deburster$to_slave_rready ; - assign boot_rom$slave_wdata = boot_rom_axi4_deburster$to_slave_wdata ; - assign boot_rom$slave_wid = boot_rom_axi4_deburster$to_slave_wid ; - assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; - assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; - assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - - // submodule boot_rom_axi4_deburster - assign boot_rom_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_0_araddr ; - assign boot_rom_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_0_arburst ; - assign boot_rom_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_0_arcache ; - assign boot_rom_axi4_deburster$from_master_arid = - fabric$v_to_slaves_0_arid ; - assign boot_rom_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_0_arlen ; - assign boot_rom_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_0_arlock ; - assign boot_rom_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_0_arprot ; - assign boot_rom_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_0_arqos ; - assign boot_rom_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_0_arregion ; - assign boot_rom_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_0_arsize ; - assign boot_rom_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_0_arvalid ; - assign boot_rom_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_0_awaddr ; - assign boot_rom_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_0_awburst ; - assign boot_rom_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_0_awcache ; - assign boot_rom_axi4_deburster$from_master_awid = - fabric$v_to_slaves_0_awid ; - assign boot_rom_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_0_awlen ; - assign boot_rom_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_0_awlock ; - assign boot_rom_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_0_awprot ; - assign boot_rom_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_0_awqos ; - assign boot_rom_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_0_awregion ; - assign boot_rom_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_0_awsize ; - assign boot_rom_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_0_awvalid ; - assign boot_rom_axi4_deburster$from_master_bready = - fabric$v_to_slaves_0_bready ; - assign boot_rom_axi4_deburster$from_master_rready = - fabric$v_to_slaves_0_rready ; - assign boot_rom_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_0_wdata ; - assign boot_rom_axi4_deburster$from_master_wid = fabric$v_to_slaves_0_wid ; - assign boot_rom_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_0_wlast ; - assign boot_rom_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_0_wstrb ; - assign boot_rom_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_0_wvalid ; - assign boot_rom_axi4_deburster$to_slave_arready = boot_rom$slave_arready ; - assign boot_rom_axi4_deburster$to_slave_awready = boot_rom$slave_awready ; - assign boot_rom_axi4_deburster$to_slave_bid = boot_rom$slave_bid ; - assign boot_rom_axi4_deburster$to_slave_bresp = boot_rom$slave_bresp ; - assign boot_rom_axi4_deburster$to_slave_bvalid = boot_rom$slave_bvalid ; - assign boot_rom_axi4_deburster$to_slave_rdata = boot_rom$slave_rdata ; - assign boot_rom_axi4_deburster$to_slave_rid = boot_rom$slave_rid ; - assign boot_rom_axi4_deburster$to_slave_rlast = boot_rom$slave_rlast ; - assign boot_rom_axi4_deburster$to_slave_rresp = boot_rom$slave_rresp ; - assign boot_rom_axi4_deburster$to_slave_rvalid = boot_rom$slave_rvalid ; - assign boot_rom_axi4_deburster$to_slave_wready = boot_rom$slave_wready ; - assign boot_rom_axi4_deburster$EN_reset = 1'b0 ; - - // submodule core - assign core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = - uart0$intr ; - assign core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$cpu_dmem_master_arready = fabric$v_from_masters_1_arready ; - assign core$cpu_dmem_master_awready = fabric$v_from_masters_1_awready ; - assign core$cpu_dmem_master_bid = fabric$v_from_masters_1_bid ; - assign core$cpu_dmem_master_bresp = fabric$v_from_masters_1_bresp ; - assign core$cpu_dmem_master_bvalid = fabric$v_from_masters_1_bvalid ; - assign core$cpu_dmem_master_rdata = fabric$v_from_masters_1_rdata ; - assign core$cpu_dmem_master_rid = fabric$v_from_masters_1_rid ; - assign core$cpu_dmem_master_rlast = fabric$v_from_masters_1_rlast ; - assign core$cpu_dmem_master_rresp = fabric$v_from_masters_1_rresp ; - assign core$cpu_dmem_master_rvalid = fabric$v_from_masters_1_rvalid ; - assign core$cpu_dmem_master_wready = fabric$v_from_masters_1_wready ; - assign core$cpu_imem_master_arready = fabric$v_from_masters_0_arready ; - assign core$cpu_imem_master_awready = fabric$v_from_masters_0_awready ; - assign core$cpu_imem_master_bid = fabric$v_from_masters_0_bid ; - assign core$cpu_imem_master_bresp = fabric$v_from_masters_0_bresp ; - assign core$cpu_imem_master_bvalid = fabric$v_from_masters_0_bvalid ; - assign core$cpu_imem_master_rdata = fabric$v_from_masters_0_rdata ; - assign core$cpu_imem_master_rid = fabric$v_from_masters_0_rid ; - assign core$cpu_imem_master_rlast = fabric$v_from_masters_0_rlast ; - assign core$cpu_imem_master_rresp = fabric$v_from_masters_0_rresp ; - assign core$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ; - assign core$cpu_imem_master_wready = fabric$v_from_masters_0_wready ; - assign core$cpu_reset_server_request_put = 1'd1 ; - assign core$nmi_req_set_not_clear = 1'd0 ; - assign core$set_verbosity_logdelay = set_verbosity_logdelay ; - assign core$set_verbosity_verbosity = set_verbosity_verbosity ; - assign core$EN_set_verbosity = EN_set_verbosity ; - assign core$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; - assign core$EN_cpu_reset_server_response_get = MUX_rg_state$write_1__SEL_2 ; - - // submodule fabric - assign fabric$set_verbosity_verbosity = 4'h0 ; - assign fabric$v_from_masters_0_araddr = core$cpu_imem_master_araddr ; - assign fabric$v_from_masters_0_arburst = core$cpu_imem_master_arburst ; - assign fabric$v_from_masters_0_arcache = core$cpu_imem_master_arcache ; - assign fabric$v_from_masters_0_arid = core$cpu_imem_master_arid ; - assign fabric$v_from_masters_0_arlen = core$cpu_imem_master_arlen ; - assign fabric$v_from_masters_0_arlock = core$cpu_imem_master_arlock ; - assign fabric$v_from_masters_0_arprot = core$cpu_imem_master_arprot ; - assign fabric$v_from_masters_0_arqos = core$cpu_imem_master_arqos ; - assign fabric$v_from_masters_0_arregion = core$cpu_imem_master_arregion ; - assign fabric$v_from_masters_0_arsize = core$cpu_imem_master_arsize ; - assign fabric$v_from_masters_0_arvalid = core$cpu_imem_master_arvalid ; - assign fabric$v_from_masters_0_awaddr = core$cpu_imem_master_awaddr ; - assign fabric$v_from_masters_0_awburst = core$cpu_imem_master_awburst ; - assign fabric$v_from_masters_0_awcache = core$cpu_imem_master_awcache ; - assign fabric$v_from_masters_0_awid = core$cpu_imem_master_awid ; - assign fabric$v_from_masters_0_awlen = core$cpu_imem_master_awlen ; - assign fabric$v_from_masters_0_awlock = core$cpu_imem_master_awlock ; - assign fabric$v_from_masters_0_awprot = core$cpu_imem_master_awprot ; - assign fabric$v_from_masters_0_awqos = core$cpu_imem_master_awqos ; - assign fabric$v_from_masters_0_awregion = core$cpu_imem_master_awregion ; - assign fabric$v_from_masters_0_awsize = core$cpu_imem_master_awsize ; - assign fabric$v_from_masters_0_awvalid = core$cpu_imem_master_awvalid ; - assign fabric$v_from_masters_0_bready = core$cpu_imem_master_bready ; - assign fabric$v_from_masters_0_rready = core$cpu_imem_master_rready ; - assign fabric$v_from_masters_0_wdata = core$cpu_imem_master_wdata ; - assign fabric$v_from_masters_0_wid = core$cpu_imem_master_wid ; - assign fabric$v_from_masters_0_wlast = core$cpu_imem_master_wlast ; - assign fabric$v_from_masters_0_wstrb = core$cpu_imem_master_wstrb ; - assign fabric$v_from_masters_0_wvalid = core$cpu_imem_master_wvalid ; - assign fabric$v_from_masters_1_araddr = core$cpu_dmem_master_araddr ; - assign fabric$v_from_masters_1_arburst = core$cpu_dmem_master_arburst ; - assign fabric$v_from_masters_1_arcache = core$cpu_dmem_master_arcache ; - assign fabric$v_from_masters_1_arid = core$cpu_dmem_master_arid ; - assign fabric$v_from_masters_1_arlen = core$cpu_dmem_master_arlen ; - assign fabric$v_from_masters_1_arlock = core$cpu_dmem_master_arlock ; - assign fabric$v_from_masters_1_arprot = core$cpu_dmem_master_arprot ; - assign fabric$v_from_masters_1_arqos = core$cpu_dmem_master_arqos ; - assign fabric$v_from_masters_1_arregion = core$cpu_dmem_master_arregion ; - assign fabric$v_from_masters_1_arsize = core$cpu_dmem_master_arsize ; - assign fabric$v_from_masters_1_arvalid = core$cpu_dmem_master_arvalid ; - assign fabric$v_from_masters_1_awaddr = core$cpu_dmem_master_awaddr ; - assign fabric$v_from_masters_1_awburst = core$cpu_dmem_master_awburst ; - assign fabric$v_from_masters_1_awcache = core$cpu_dmem_master_awcache ; - assign fabric$v_from_masters_1_awid = core$cpu_dmem_master_awid ; - assign fabric$v_from_masters_1_awlen = core$cpu_dmem_master_awlen ; - assign fabric$v_from_masters_1_awlock = core$cpu_dmem_master_awlock ; - assign fabric$v_from_masters_1_awprot = core$cpu_dmem_master_awprot ; - assign fabric$v_from_masters_1_awqos = core$cpu_dmem_master_awqos ; - assign fabric$v_from_masters_1_awregion = core$cpu_dmem_master_awregion ; - assign fabric$v_from_masters_1_awsize = core$cpu_dmem_master_awsize ; - assign fabric$v_from_masters_1_awvalid = core$cpu_dmem_master_awvalid ; - assign fabric$v_from_masters_1_bready = core$cpu_dmem_master_bready ; - assign fabric$v_from_masters_1_rready = core$cpu_dmem_master_rready ; - assign fabric$v_from_masters_1_wdata = core$cpu_dmem_master_wdata ; - assign fabric$v_from_masters_1_wid = core$cpu_dmem_master_wid ; - assign fabric$v_from_masters_1_wlast = core$cpu_dmem_master_wlast ; - assign fabric$v_from_masters_1_wstrb = core$cpu_dmem_master_wstrb ; - assign fabric$v_from_masters_1_wvalid = core$cpu_dmem_master_wvalid ; - assign fabric$v_to_slaves_0_arready = - boot_rom_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_0_awready = - boot_rom_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_0_bid = boot_rom_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_0_bresp = - boot_rom_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_0_bvalid = - boot_rom_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_0_rdata = - boot_rom_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_0_rid = boot_rom_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_0_rlast = - boot_rom_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_0_rresp = - boot_rom_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_0_rvalid = - boot_rom_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_0_wready = - boot_rom_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_1_arready = - mem0_controller_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_1_awready = - mem0_controller_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_1_bid = - mem0_controller_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_1_bresp = - mem0_controller_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_1_bvalid = - mem0_controller_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_1_rdata = - mem0_controller_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_1_rid = - mem0_controller_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_1_rlast = - mem0_controller_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_1_rresp = - mem0_controller_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_1_rvalid = - mem0_controller_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_1_wready = - mem0_controller_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_2_arready = uart0$slave_arready ; - assign fabric$v_to_slaves_2_awready = uart0$slave_awready ; - assign fabric$v_to_slaves_2_bid = uart0$slave_bid ; - assign fabric$v_to_slaves_2_bresp = uart0$slave_bresp ; - assign fabric$v_to_slaves_2_bvalid = uart0$slave_bvalid ; - assign fabric$v_to_slaves_2_rdata = uart0$slave_rdata ; - assign fabric$v_to_slaves_2_rid = uart0$slave_rid ; - assign fabric$v_to_slaves_2_rlast = uart0$slave_rlast ; - assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; - assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; - assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; - assign fabric$EN_set_verbosity = 1'b0 ; - - // submodule mem0_controller - assign mem0_controller$set_addr_map_addr_base = - soc_map$m_mem0_controller_addr_base ; - assign mem0_controller$set_addr_map_addr_lim = - soc_map$m_mem0_controller_addr_lim ; - assign mem0_controller$set_watch_tohost_tohost_addr = - set_watch_tohost_tohost_addr ; - assign mem0_controller$set_watch_tohost_watch_tohost = - set_watch_tohost_watch_tohost ; - assign mem0_controller$slave_araddr = - mem0_controller_axi4_deburster$to_slave_araddr ; - assign mem0_controller$slave_arburst = - mem0_controller_axi4_deburster$to_slave_arburst ; - assign mem0_controller$slave_arcache = - mem0_controller_axi4_deburster$to_slave_arcache ; - assign mem0_controller$slave_arid = - mem0_controller_axi4_deburster$to_slave_arid ; - assign mem0_controller$slave_arlen = - mem0_controller_axi4_deburster$to_slave_arlen ; - assign mem0_controller$slave_arlock = - mem0_controller_axi4_deburster$to_slave_arlock ; - assign mem0_controller$slave_arprot = - mem0_controller_axi4_deburster$to_slave_arprot ; - assign mem0_controller$slave_arqos = - mem0_controller_axi4_deburster$to_slave_arqos ; - assign mem0_controller$slave_arregion = - mem0_controller_axi4_deburster$to_slave_arregion ; - assign mem0_controller$slave_arsize = - mem0_controller_axi4_deburster$to_slave_arsize ; - assign mem0_controller$slave_arvalid = - mem0_controller_axi4_deburster$to_slave_arvalid ; - assign mem0_controller$slave_awaddr = - mem0_controller_axi4_deburster$to_slave_awaddr ; - assign mem0_controller$slave_awburst = - mem0_controller_axi4_deburster$to_slave_awburst ; - assign mem0_controller$slave_awcache = - mem0_controller_axi4_deburster$to_slave_awcache ; - assign mem0_controller$slave_awid = - mem0_controller_axi4_deburster$to_slave_awid ; - assign mem0_controller$slave_awlen = - mem0_controller_axi4_deburster$to_slave_awlen ; - assign mem0_controller$slave_awlock = - mem0_controller_axi4_deburster$to_slave_awlock ; - assign mem0_controller$slave_awprot = - mem0_controller_axi4_deburster$to_slave_awprot ; - assign mem0_controller$slave_awqos = - mem0_controller_axi4_deburster$to_slave_awqos ; - assign mem0_controller$slave_awregion = - mem0_controller_axi4_deburster$to_slave_awregion ; - assign mem0_controller$slave_awsize = - mem0_controller_axi4_deburster$to_slave_awsize ; - assign mem0_controller$slave_awvalid = - mem0_controller_axi4_deburster$to_slave_awvalid ; - assign mem0_controller$slave_bready = - mem0_controller_axi4_deburster$to_slave_bready ; - assign mem0_controller$slave_rready = - mem0_controller_axi4_deburster$to_slave_rready ; - assign mem0_controller$slave_wdata = - mem0_controller_axi4_deburster$to_slave_wdata ; - assign mem0_controller$slave_wid = - mem0_controller_axi4_deburster$to_slave_wid ; - assign mem0_controller$slave_wlast = - mem0_controller_axi4_deburster$to_slave_wlast ; - assign mem0_controller$slave_wstrb = - mem0_controller_axi4_deburster$to_slave_wstrb ; - assign mem0_controller$slave_wvalid = - mem0_controller_axi4_deburster$to_slave_wvalid ; - assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; - assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; - assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_to_raw_mem_request_get = - EN_to_raw_mem_request_get ; - assign mem0_controller$EN_to_raw_mem_response_put = - EN_to_raw_mem_response_put ; - assign mem0_controller$EN_set_watch_tohost = EN_set_watch_tohost ; - - // submodule mem0_controller_axi4_deburster - assign mem0_controller_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_1_araddr ; - assign mem0_controller_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_1_arburst ; - assign mem0_controller_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_1_arcache ; - assign mem0_controller_axi4_deburster$from_master_arid = - fabric$v_to_slaves_1_arid ; - assign mem0_controller_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_1_arlen ; - assign mem0_controller_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_1_arlock ; - assign mem0_controller_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_1_arprot ; - assign mem0_controller_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_1_arqos ; - assign mem0_controller_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_1_arregion ; - assign mem0_controller_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_1_arsize ; - assign mem0_controller_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_1_arvalid ; - assign mem0_controller_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_1_awaddr ; - assign mem0_controller_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_1_awburst ; - assign mem0_controller_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_1_awcache ; - assign mem0_controller_axi4_deburster$from_master_awid = - fabric$v_to_slaves_1_awid ; - assign mem0_controller_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_1_awlen ; - assign mem0_controller_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_1_awlock ; - assign mem0_controller_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_1_awprot ; - assign mem0_controller_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_1_awqos ; - assign mem0_controller_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_1_awregion ; - assign mem0_controller_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_1_awsize ; - assign mem0_controller_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_1_awvalid ; - assign mem0_controller_axi4_deburster$from_master_bready = - fabric$v_to_slaves_1_bready ; - assign mem0_controller_axi4_deburster$from_master_rready = - fabric$v_to_slaves_1_rready ; - assign mem0_controller_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_1_wdata ; - assign mem0_controller_axi4_deburster$from_master_wid = - fabric$v_to_slaves_1_wid ; - assign mem0_controller_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_1_wlast ; - assign mem0_controller_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_1_wstrb ; - assign mem0_controller_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_1_wvalid ; - assign mem0_controller_axi4_deburster$to_slave_arready = - mem0_controller$slave_arready ; - assign mem0_controller_axi4_deburster$to_slave_awready = - mem0_controller$slave_awready ; - assign mem0_controller_axi4_deburster$to_slave_bid = - mem0_controller$slave_bid ; - assign mem0_controller_axi4_deburster$to_slave_bresp = - mem0_controller$slave_bresp ; - assign mem0_controller_axi4_deburster$to_slave_bvalid = - mem0_controller$slave_bvalid ; - assign mem0_controller_axi4_deburster$to_slave_rdata = - mem0_controller$slave_rdata ; - assign mem0_controller_axi4_deburster$to_slave_rid = - mem0_controller$slave_rid ; - assign mem0_controller_axi4_deburster$to_slave_rlast = - mem0_controller$slave_rlast ; - assign mem0_controller_axi4_deburster$to_slave_rresp = - mem0_controller$slave_rresp ; - assign mem0_controller_axi4_deburster$to_slave_rvalid = - mem0_controller$slave_rvalid ; - assign mem0_controller_axi4_deburster$to_slave_wready = - mem0_controller$slave_wready ; - assign mem0_controller_axi4_deburster$EN_reset = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule uart0 - assign uart0$put_from_console_put = put_from_console_put ; - assign uart0$set_addr_map_addr_base = soc_map$m_uart0_addr_base ; - assign uart0$set_addr_map_addr_lim = soc_map$m_uart0_addr_lim ; - assign uart0$slave_araddr = fabric$v_to_slaves_2_araddr ; - assign uart0$slave_arburst = fabric$v_to_slaves_2_arburst ; - assign uart0$slave_arcache = fabric$v_to_slaves_2_arcache ; - assign uart0$slave_arid = fabric$v_to_slaves_2_arid ; - assign uart0$slave_arlen = fabric$v_to_slaves_2_arlen ; - assign uart0$slave_arlock = fabric$v_to_slaves_2_arlock ; - assign uart0$slave_arprot = fabric$v_to_slaves_2_arprot ; - assign uart0$slave_arqos = fabric$v_to_slaves_2_arqos ; - assign uart0$slave_arregion = fabric$v_to_slaves_2_arregion ; - assign uart0$slave_arsize = fabric$v_to_slaves_2_arsize ; - assign uart0$slave_arvalid = fabric$v_to_slaves_2_arvalid ; - assign uart0$slave_awaddr = fabric$v_to_slaves_2_awaddr ; - assign uart0$slave_awburst = fabric$v_to_slaves_2_awburst ; - assign uart0$slave_awcache = fabric$v_to_slaves_2_awcache ; - assign uart0$slave_awid = fabric$v_to_slaves_2_awid ; - assign uart0$slave_awlen = fabric$v_to_slaves_2_awlen ; - assign uart0$slave_awlock = fabric$v_to_slaves_2_awlock ; - assign uart0$slave_awprot = fabric$v_to_slaves_2_awprot ; - assign uart0$slave_awqos = fabric$v_to_slaves_2_awqos ; - assign uart0$slave_awregion = fabric$v_to_slaves_2_awregion ; - assign uart0$slave_awsize = fabric$v_to_slaves_2_awsize ; - assign uart0$slave_awvalid = fabric$v_to_slaves_2_awvalid ; - assign uart0$slave_bready = fabric$v_to_slaves_2_bready ; - assign uart0$slave_rready = fabric$v_to_slaves_2_rready ; - assign uart0$slave_wdata = fabric$v_to_slaves_2_wdata ; - assign uart0$slave_wid = fabric$v_to_slaves_2_wid ; - assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; - assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; - assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_get_to_console_get = EN_get_to_console_get ; - assign uart0$EN_put_from_console_put = EN_put_from_console_put ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - begin - v__h11286 = $stime; - #0; - end - v__h11280 = v__h11286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - $display("%0d:%m.rl_reset_start_initial ...", v__h11280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - begin - v__h11556 = $stime; - #0; - end - v__h11550 = v__h11556 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - $display("%0d:%m.rl_reset_complete_initial", v__h11550); - end - // synopsys translate_on -endmodule // mkSoC_Top - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTLB.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTLB.v deleted file mode 100644 index 80794990..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTLB.v +++ /dev/null @@ -1,452 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_flush O 1 const -// lookup O 69 -// RDY_lookup O 1 -// RDY_insert O 1 -// CLK I 1 clock -// RST_N I 1 reset -// lookup_asid I 9 -// lookup_vpn I 20 -// insert_asid I 9 reg -// insert_vpn I 20 -// insert_pte I 32 reg -// insert_level I 2 -// insert_pte_pa I 34 reg -// EN_flush I 1 -// EN_insert I 1 -// -// Combinational paths from inputs to outputs: -// (lookup_asid, lookup_vpn) -> lookup -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTLB(CLK, - RST_N, - - EN_flush, - RDY_flush, - - lookup_asid, - lookup_vpn, - lookup, - RDY_lookup, - - insert_asid, - insert_vpn, - insert_pte, - insert_level, - insert_pte_pa, - EN_insert, - RDY_insert); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method flush - input EN_flush; - output RDY_flush; - - // value method lookup - input [8 : 0] lookup_asid; - input [19 : 0] lookup_vpn; - output [68 : 0] lookup; - output RDY_lookup; - - // action method insert - input [8 : 0] insert_asid; - input [19 : 0] insert_vpn; - input [31 : 0] insert_pte; - input [1 : 0] insert_level; - input [33 : 0] insert_pte_pa; - input EN_insert; - output RDY_insert; - - // signals for module outputs - wire [68 : 0] lookup; - wire RDY_flush, RDY_insert, RDY_lookup; - - // register rg_flushing - reg rg_flushing; - wire rg_flushing$D_IN, rg_flushing$EN; - - // register tlb0_valids_0 - reg tlb0_valids_0; - wire tlb0_valids_0$D_IN, tlb0_valids_0$EN; - - // register tlb0_valids_1 - reg tlb0_valids_1; - wire tlb0_valids_1$D_IN, tlb0_valids_1$EN; - - // register tlb0_valids_2 - reg tlb0_valids_2; - wire tlb0_valids_2$D_IN, tlb0_valids_2$EN; - - // register tlb0_valids_3 - reg tlb0_valids_3; - wire tlb0_valids_3$D_IN, tlb0_valids_3$EN; - - // register tlb1_valids_0 - reg tlb1_valids_0; - wire tlb1_valids_0$D_IN, tlb1_valids_0$EN; - - // register tlb1_valids_1 - reg tlb1_valids_1; - wire tlb1_valids_1$D_IN, tlb1_valids_1$EN; - - // register tlb1_valids_2 - reg tlb1_valids_2; - wire tlb1_valids_2$D_IN, tlb1_valids_2$EN; - - // register tlb1_valids_3 - reg tlb1_valids_3; - wire tlb1_valids_3$D_IN, tlb1_valids_3$EN; - - // ports of submodule tlb0_entries - wire [102 : 0] tlb0_entries$D_IN, tlb0_entries$D_OUT_1; - wire [1 : 0] tlb0_entries$ADDR_1, - tlb0_entries$ADDR_2, - tlb0_entries$ADDR_3, - tlb0_entries$ADDR_4, - tlb0_entries$ADDR_5, - tlb0_entries$ADDR_IN; - wire tlb0_entries$WE; - - // ports of submodule tlb1_entries - wire [92 : 0] tlb1_entries$D_IN, tlb1_entries$D_OUT_1; - wire [1 : 0] tlb1_entries$ADDR_1, - tlb1_entries$ADDR_2, - tlb1_entries$ADDR_3, - tlb1_entries$ADDR_4, - tlb1_entries$ADDR_5, - tlb1_entries$ADDR_IN; - wire tlb1_entries$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_initialize, - CAN_FIRE_flush, - CAN_FIRE_insert, - WILL_FIRE_RL_rl_initialize, - WILL_FIRE_flush, - WILL_FIRE_insert; - - // inputs to muxes for submodule ports - wire MUX_tlb0_valids_0$write_1__SEL_1, - MUX_tlb0_valids_1$write_1__SEL_1, - MUX_tlb0_valids_2$write_1__SEL_1, - MUX_tlb0_valids_3$write_1__SEL_1, - MUX_tlb1_valids_0$write_1__SEL_1, - MUX_tlb1_valids_1$write_1__SEL_1, - MUX_tlb1_valids_2$write_1__SEL_1, - MUX_tlb1_valids_3$write_1__SEL_1; - - // remaining internal signals - reg SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30, - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8; - wire [67 : 0] IF_NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb_ETC___d62; - wire [27 : 0] tag__h2330, tag__h2574; - wire [17 : 0] tag__h2210, tag__h2585; - wire NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_v_ETC___d23, - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d41, - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d33, - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d40, - tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d12, - tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d21; - - // action method flush - assign RDY_flush = 1'd1 ; - assign CAN_FIRE_flush = 1'd1 ; - assign WILL_FIRE_flush = EN_flush ; - - // value method lookup - assign lookup = - { NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_v_ETC___d23 && - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d41 || - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 && - (tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d12 || - tlb1_entries$D_OUT_1[39]) && - tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d21 && - (!SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 || - !tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d33 && - !tlb0_entries$D_OUT_1[39] || - !tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d40), - IF_NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb_ETC___d62 } ; - assign RDY_lookup = !rg_flushing ; - - // action method insert - assign RDY_insert = !rg_flushing ; - assign CAN_FIRE_insert = !rg_flushing ; - assign WILL_FIRE_insert = EN_insert ; - - // submodule tlb0_entries - RegFile #(.addr_width(32'd2), - .data_width(32'd103), - .lo(2'h0), - .hi(2'd3)) tlb0_entries(.CLK(CLK), - .ADDR_1(tlb0_entries$ADDR_1), - .ADDR_2(tlb0_entries$ADDR_2), - .ADDR_3(tlb0_entries$ADDR_3), - .ADDR_4(tlb0_entries$ADDR_4), - .ADDR_5(tlb0_entries$ADDR_5), - .ADDR_IN(tlb0_entries$ADDR_IN), - .D_IN(tlb0_entries$D_IN), - .WE(tlb0_entries$WE), - .D_OUT_1(tlb0_entries$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule tlb1_entries - RegFile #(.addr_width(32'd2), - .data_width(32'd93), - .lo(2'h0), - .hi(2'd3)) tlb1_entries(.CLK(CLK), - .ADDR_1(tlb1_entries$ADDR_1), - .ADDR_2(tlb1_entries$ADDR_2), - .ADDR_3(tlb1_entries$ADDR_3), - .ADDR_4(tlb1_entries$ADDR_4), - .ADDR_5(tlb1_entries$ADDR_5), - .ADDR_IN(tlb1_entries$ADDR_IN), - .D_IN(tlb1_entries$D_IN), - .WE(tlb1_entries$WE), - .D_OUT_1(tlb1_entries$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_initialize - assign CAN_FIRE_RL_rl_initialize = rg_flushing ; - assign WILL_FIRE_RL_rl_initialize = rg_flushing ; - - // inputs to muxes for submodule ports - assign MUX_tlb0_valids_0$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd0 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_1$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd1 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_2$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd2 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_3$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd3 && insert_level == 2'd0 ; - assign MUX_tlb1_valids_0$write_1__SEL_1 = - EN_insert && insert_vpn[11:10] == 2'd0 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_1$write_1__SEL_1 = - EN_insert && insert_vpn[11:10] == 2'd1 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_2$write_1__SEL_1 = - EN_insert && insert_vpn[11:10] == 2'd2 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_3$write_1__SEL_1 = - EN_insert && insert_vpn[11:10] == 2'd3 && insert_level == 2'd1 ; - - // register rg_flushing - assign rg_flushing$D_IN = EN_flush ; - assign rg_flushing$EN = rg_flushing || EN_flush ; - - // register tlb0_valids_0 - assign tlb0_valids_0$D_IN = MUX_tlb0_valids_0$write_1__SEL_1 ; - assign tlb0_valids_0$EN = - EN_insert && insert_vpn[1:0] == 2'd0 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_1 - assign tlb0_valids_1$D_IN = MUX_tlb0_valids_1$write_1__SEL_1 ; - assign tlb0_valids_1$EN = - EN_insert && insert_vpn[1:0] == 2'd1 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_2 - assign tlb0_valids_2$D_IN = MUX_tlb0_valids_2$write_1__SEL_1 ; - assign tlb0_valids_2$EN = - EN_insert && insert_vpn[1:0] == 2'd2 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_3 - assign tlb0_valids_3$D_IN = MUX_tlb0_valids_3$write_1__SEL_1 ; - assign tlb0_valids_3$EN = - EN_insert && insert_vpn[1:0] == 2'd3 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb1_valids_0 - assign tlb1_valids_0$D_IN = MUX_tlb1_valids_0$write_1__SEL_1 ; - assign tlb1_valids_0$EN = - EN_insert && insert_vpn[11:10] == 2'd0 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_1 - assign tlb1_valids_1$D_IN = MUX_tlb1_valids_1$write_1__SEL_1 ; - assign tlb1_valids_1$EN = - EN_insert && insert_vpn[11:10] == 2'd1 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_2 - assign tlb1_valids_2$D_IN = MUX_tlb1_valids_2$write_1__SEL_1 ; - assign tlb1_valids_2$EN = - EN_insert && insert_vpn[11:10] == 2'd2 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_3 - assign tlb1_valids_3$D_IN = MUX_tlb1_valids_3$write_1__SEL_1 ; - assign tlb1_valids_3$EN = - EN_insert && insert_vpn[11:10] == 2'd3 && insert_level == 2'd1 || - rg_flushing ; - - // submodule tlb0_entries - assign tlb0_entries$ADDR_1 = lookup_vpn[1:0] ; - assign tlb0_entries$ADDR_2 = 2'h0 ; - assign tlb0_entries$ADDR_3 = 2'h0 ; - assign tlb0_entries$ADDR_4 = 2'h0 ; - assign tlb0_entries$ADDR_5 = 2'h0 ; - assign tlb0_entries$ADDR_IN = insert_vpn[1:0] ; - assign tlb0_entries$D_IN = - { insert_asid, tag__h2574, insert_pte, insert_pte_pa } ; - assign tlb0_entries$WE = EN_insert && insert_level == 2'd0 ; - - // submodule tlb1_entries - assign tlb1_entries$ADDR_1 = lookup_vpn[11:10] ; - assign tlb1_entries$ADDR_2 = 2'h0 ; - assign tlb1_entries$ADDR_3 = 2'h0 ; - assign tlb1_entries$ADDR_4 = 2'h0 ; - assign tlb1_entries$ADDR_5 = 2'h0 ; - assign tlb1_entries$ADDR_IN = insert_vpn[11:10] ; - assign tlb1_entries$D_IN = - { insert_asid, tag__h2585, insert_pte, insert_pte_pa } ; - assign tlb1_entries$WE = EN_insert && insert_level == 2'd1 ; - - // remaining internal signals - assign IF_NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb_ETC___d62 = - (NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_v_ETC___d23 && - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d41) ? - { tlb0_entries$D_OUT_1[65:34], - 2'd0, - tlb0_entries$D_OUT_1[33:0] } : - { tlb1_entries$D_OUT_1[65:34], - 2'd1, - tlb1_entries$D_OUT_1[33:0] } ; - assign NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_v_ETC___d23 = - !SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 || - !tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d12 && - !tlb1_entries$D_OUT_1[39] || - !tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d21 ; - assign SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d41 = - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 && - (tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d33 || - tlb0_entries$D_OUT_1[39]) && - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d40 ; - assign tag__h2210 = { 10'd0, lookup_vpn[19:12] } ; - assign tag__h2330 = { 10'd0, lookup_vpn[19:2] } ; - assign tag__h2574 = { 10'd0, insert_vpn[19:2] } ; - assign tag__h2585 = { 10'd0, insert_vpn[19:12] } ; - assign tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d33 = - tlb0_entries$D_OUT_1[102:94] == lookup_asid ; - assign tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d40 = - tlb0_entries$D_OUT_1[93:66] == tag__h2330 ; - assign tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d12 = - tlb1_entries$D_OUT_1[92:84] == lookup_asid ; - assign tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d21 = - tlb1_entries$D_OUT_1[83:66] == tag__h2210 ; - always@(lookup_vpn or - tlb1_valids_0 or tlb1_valids_1 or tlb1_valids_2 or tlb1_valids_3) - begin - case (lookup_vpn[11:10]) - 2'd0: - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 = - tlb1_valids_0; - 2'd1: - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 = - tlb1_valids_1; - 2'd2: - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 = - tlb1_valids_2; - 2'd3: - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 = - tlb1_valids_3; - endcase - end - always@(lookup_vpn or - tlb0_valids_0 or tlb0_valids_1 or tlb0_valids_2 or tlb0_valids_3) - begin - case (lookup_vpn[1:0]) - 2'd0: - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 = - tlb0_valids_0; - 2'd1: - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 = - tlb0_valids_1; - 2'd2: - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 = - tlb0_valids_2; - 2'd3: - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 = - tlb0_valids_3; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_flushing <= `BSV_ASSIGNMENT_DELAY 1'd1; - end - else - begin - if (rg_flushing$EN) - rg_flushing <= `BSV_ASSIGNMENT_DELAY rg_flushing$D_IN; - end - if (tlb0_valids_0$EN) - tlb0_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_0$D_IN; - if (tlb0_valids_1$EN) - tlb0_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_1$D_IN; - if (tlb0_valids_2$EN) - tlb0_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_2$D_IN; - if (tlb0_valids_3$EN) - tlb0_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_3$D_IN; - if (tlb1_valids_0$EN) - tlb1_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_0$D_IN; - if (tlb1_valids_1$EN) - tlb1_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_1$D_IN; - if (tlb1_valids_2$EN) - tlb1_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_2$D_IN; - if (tlb1_valids_3$EN) - tlb1_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_flushing = 1'h0; - tlb0_valids_0 = 1'h0; - tlb0_valids_1 = 1'h0; - tlb0_valids_2 = 1'h0; - tlb0_valids_3 = 1'h0; - tlb1_valids_0 = 1'h0; - tlb1_valids_1 = 1'h0; - tlb1_valids_2 = 1'h0; - tlb1_valids_3 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkTLB - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v deleted file mode 100644 index a195f14f..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v +++ /dev/null @@ -1,255 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// CLK I 1 clock -// RST_N I 1 reset -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTop_HW_Side(CLK, - RST_N); - input CLK; - input RST_N; - - // register rg_banner_printed - reg rg_banner_printed; - wire rg_banner_printed$D_IN, rg_banner_printed$EN; - - // ports of submodule mem_model - wire [352 : 0] mem_model$mem_server_request_put; - wire [255 : 0] mem_model$mem_server_response_get; - wire mem_model$EN_mem_server_request_put, - mem_model$EN_mem_server_response_get, - mem_model$RDY_mem_server_request_put, - mem_model$RDY_mem_server_response_get; - - // ports of submodule soc_top - wire [352 : 0] soc_top$to_raw_mem_request_get; - wire [255 : 0] soc_top$to_raw_mem_response_put; - wire [63 : 0] soc_top$set_verbosity_logdelay, - soc_top$set_watch_tohost_tohost_addr; - wire [7 : 0] soc_top$get_to_console_get, - soc_top$put_from_console_put, - soc_top$status; - wire [3 : 0] soc_top$set_verbosity_verbosity; - wire soc_top$EN_get_to_console_get, - soc_top$EN_put_from_console_put, - soc_top$EN_set_verbosity, - soc_top$EN_set_watch_tohost, - soc_top$EN_to_raw_mem_request_get, - soc_top$EN_to_raw_mem_response_put, - soc_top$RDY_get_to_console_get, - soc_top$RDY_to_raw_mem_request_get, - soc_top$RDY_to_raw_mem_response_put, - soc_top$set_watch_tohost_watch_tohost; - - // rule scheduling signals - wire CAN_FIRE_RL_memCnx_ClientServerRequest, - CAN_FIRE_RL_memCnx_ClientServerResponse, - CAN_FIRE_RL_rl_relay_console_out, - CAN_FIRE_RL_rl_step0, - CAN_FIRE_RL_rl_terminate, - WILL_FIRE_RL_memCnx_ClientServerRequest, - WILL_FIRE_RL_memCnx_ClientServerResponse, - WILL_FIRE_RL_rl_relay_console_out, - WILL_FIRE_RL_rl_step0, - WILL_FIRE_RL_rl_terminate; - - // declarations used by system tasks - // synopsys translate_off - reg TASK_testplusargs___d12; - reg TASK_testplusargs___d11; - reg [31 : 0] v__h536; - reg [31 : 0] v__h530; - // synopsys translate_on - - // submodule mem_model - mkMem_Model mem_model(.CLK(CLK), - .RST_N(RST_N), - .mem_server_request_put(mem_model$mem_server_request_put), - .EN_mem_server_request_put(mem_model$EN_mem_server_request_put), - .EN_mem_server_response_get(mem_model$EN_mem_server_response_get), - .RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put), - .mem_server_response_get(mem_model$mem_server_response_get), - .RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get)); - - // submodule soc_top - mkSoC_Top soc_top(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(soc_top$put_from_console_put), - .set_verbosity_logdelay(soc_top$set_verbosity_logdelay), - .set_verbosity_verbosity(soc_top$set_verbosity_verbosity), - .set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost), - .to_raw_mem_response_put(soc_top$to_raw_mem_response_put), - .EN_set_verbosity(soc_top$EN_set_verbosity), - .EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put), - .EN_get_to_console_get(soc_top$EN_get_to_console_get), - .EN_put_from_console_put(soc_top$EN_put_from_console_put), - .EN_set_watch_tohost(soc_top$EN_set_watch_tohost), - .RDY_set_verbosity(), - .to_raw_mem_request_get(soc_top$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put), - .get_to_console_get(soc_top$get_to_console_get), - .RDY_get_to_console_get(soc_top$RDY_get_to_console_get), - .RDY_put_from_console_put(), - .status(soc_top$status), - .RDY_set_watch_tohost()); - - // rule RL_rl_step0 - assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ; - assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ; - - // rule RL_rl_terminate - assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ; - assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ; - - // rule RL_rl_relay_console_out - assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - - // rule RL_memCnx_ClientServerRequest - assign CAN_FIRE_RL_memCnx_ClientServerRequest = - soc_top$RDY_to_raw_mem_request_get && - mem_model$RDY_mem_server_request_put ; - assign WILL_FIRE_RL_memCnx_ClientServerRequest = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - - // rule RL_memCnx_ClientServerResponse - assign CAN_FIRE_RL_memCnx_ClientServerResponse = - soc_top$RDY_to_raw_mem_response_put && - mem_model$RDY_mem_server_response_get ; - assign WILL_FIRE_RL_memCnx_ClientServerResponse = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // register rg_banner_printed - assign rg_banner_printed$D_IN = 1'd1 ; - assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ; - - // submodule mem_model - assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ; - assign mem_model$EN_mem_server_request_put = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign mem_model$EN_mem_server_response_get = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // submodule soc_top - assign soc_top$put_from_console_put = 8'h0 ; - assign soc_top$set_verbosity_logdelay = 64'd0 ; - assign soc_top$set_verbosity_verbosity = - TASK_testplusargs___d11 ? - 4'd2 : - (TASK_testplusargs___d12 ? 4'd1 : 4'd0) ; - assign soc_top$set_watch_tohost_tohost_addr = 64'h0 ; - assign soc_top$set_watch_tohost_watch_tohost = 1'b0 ; - assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ; - assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ; - assign soc_top$EN_to_raw_mem_request_get = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign soc_top$EN_to_raw_mem_response_put = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ; - assign soc_top$EN_put_from_console_put = 1'b0 ; - assign soc_top$EN_set_watch_tohost = 1'b0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_banner_printed$EN) - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_banner_printed = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Bluespec RISC-V standalone system simulation v1.2"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d12 = $test$plusargs("v1"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d11 = $test$plusargs("v2"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h536 = $stime; - #0; - end - v__h530 = v__h536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $display("%0d: %m.rl_terminate: soc_top status is 0x%0h (= 0d%0d)", - v__h530, - soc_top$status, - soc_top$status); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) - $write("%c", soc_top$get_to_console_get); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001); - end - // synopsys translate_on -endmodule // mkTop_HW_Side - diff --git a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkUART.v b/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkUART.v deleted file mode 100644 index 033775ea..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkUART.v +++ /dev/null @@ -1,2925 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// intr O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// put_from_console_put I 8 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_put_from_console_put I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkUART(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - intr); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method intr - output intr; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [7 : 0] get_to_console_get; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - intr, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register cfg_verbosity - reg [7 : 0] cfg_verbosity; - wire [7 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_dll - reg [7 : 0] rg_dll; - wire [7 : 0] rg_dll$D_IN; - wire rg_dll$EN; - - // register rg_dlm - reg [7 : 0] rg_dlm; - wire [7 : 0] rg_dlm$D_IN; - wire rg_dlm$EN; - - // register rg_fcr - reg [7 : 0] rg_fcr; - wire [7 : 0] rg_fcr$D_IN; - wire rg_fcr$EN; - - // register rg_ier - reg [7 : 0] rg_ier; - wire [7 : 0] rg_ier$D_IN; - wire rg_ier$EN; - - // register rg_lcr - reg [7 : 0] rg_lcr; - wire [7 : 0] rg_lcr$D_IN; - wire rg_lcr$EN; - - // register rg_lsr - reg [7 : 0] rg_lsr; - reg [7 : 0] rg_lsr$D_IN; - wire rg_lsr$EN; - - // register rg_mcr - reg [7 : 0] rg_mcr; - wire [7 : 0] rg_mcr$D_IN; - wire rg_mcr$EN; - - // register rg_msr - reg [7 : 0] rg_msr; - wire [7 : 0] rg_msr$D_IN; - wire rg_msr$EN; - - // register rg_rbr - reg [7 : 0] rg_rbr; - wire [7 : 0] rg_rbr$D_IN; - wire rg_rbr$EN; - - // register rg_scr - reg [7 : 0] rg_scr; - wire [7 : 0] rg_scr$D_IN; - wire rg_scr$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_thr - reg [7 : 0] rg_thr; - wire [7 : 0] rg_thr$D_IN; - wire rg_thr$EN; - - // ports of submodule f_from_console - wire [7 : 0] f_from_console$D_IN, f_from_console$D_OUT; - wire f_from_console$CLR, - f_from_console$DEQ, - f_from_console$EMPTY_N, - f_from_console$ENQ, - f_from_console$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_to_console - wire [7 : 0] f_to_console$D_IN, f_to_console$D_OUT; - wire f_to_console$CLR, - f_to_console$DEQ, - f_to_console$EMPTY_N, - f_to_console$ENQ, - f_to_console$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_receive, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_receive, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_rg_lsr$write_1__VAL_3; - wire MUX_rg_lsr$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2519; - reg [31 : 0] v__h2187; - reg [31 : 0] v__h2025; - reg [31 : 0] v__h2898; - reg [31 : 0] v__h3244; - reg [31 : 0] v__h4006; - reg [31 : 0] v__h3449; - reg [31 : 0] v__h4306; - reg [31 : 0] v__h4749; - reg [31 : 0] v__h4859; - reg [31 : 0] v__h1811; - reg [31 : 0] v__h1805; - reg [31 : 0] v__h2019; - reg [31 : 0] v__h2181; - reg [31 : 0] v__h2513; - reg [31 : 0] v__h2892; - reg [31 : 0] v__h3238; - reg [31 : 0] v__h3443; - reg [31 : 0] v__h4000; - reg [31 : 0] v__h4300; - reg [31 : 0] v__h4743; - reg [31 : 0] v__h4853; - // synopsys translate_on - - // remaining internal signals - reg [7 : 0] y_avValue_snd__h2683; - wire [63 : 0] rdata__h2759, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133; - wire [7 : 0] fn_iir__h1356, - new_lsr__h4516, - x__h2797, - y_avValue_snd__h2696, - y_avValue_snd__h2709, - y_avValue_snd__h2724, - y_avValue_snd__h2738; - wire [1 : 0] rdr_rresp__h2792, - v__h3147, - v__h3395, - v__h3575, - y_avValue_fst__h2737, - y_avValue_fst__h2751; - wire NOT_cfg_verbosity_read_ULE_1_24___d125, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188, - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method get_to_console_get - assign get_to_console_get = f_to_console$D_OUT ; - assign RDY_get_to_console_get = f_to_console$EMPTY_N ; - assign CAN_FIRE_get_to_console_get = f_to_console$EMPTY_N ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = f_from_console$FULL_N ; - assign CAN_FIRE_put_from_console_put = f_from_console$FULL_N ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method intr - assign intr = !fn_iir__h1356[0] ; - - // submodule f_from_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_from_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_from_console$D_IN), - .ENQ(f_from_console$ENQ), - .DEQ(f_from_console$DEQ), - .CLR(f_from_console$CLR), - .D_OUT(f_from_console$D_OUT), - .FULL_N(f_from_console$FULL_N), - .EMPTY_N(f_from_console$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_to_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_to_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_to_console$D_IN), - .ENQ(f_to_console$ENQ), - .DEQ(f_to_console$DEQ), - .CLR(f_to_console$CLR), - .D_OUT(f_to_console$D_OUT), - .FULL_N(f_to_console$FULL_N), - .EMPTY_N(f_to_console$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 && - rg_state ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_receive - assign CAN_FIRE_RL_rl_receive = f_from_console$EMPTY_N && !rg_lsr[0] ; - assign WILL_FIRE_RL_rl_receive = - CAN_FIRE_RL_rl_receive && !WILL_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_rg_lsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 ; - assign MUX_rg_lsr$write_1__VAL_3 = { rg_lsr[7:1], 1'd0 } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 8'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_dll - assign rg_dll$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dll$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 || - WILL_FIRE_RL_rl_reset ; - - // register rg_dlm - assign rg_dlm$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dlm$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 || - WILL_FIRE_RL_rl_reset ; - - // register rg_fcr - assign rg_fcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_fcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h2 || - WILL_FIRE_RL_rl_reset ; - - // register rg_ier - assign rg_ier$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_ier$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lcr - assign rg_lcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_lcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h3 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lsr - always@(WILL_FIRE_RL_rl_reset or - WILL_FIRE_RL_rl_receive or - new_lsr__h4516 or - MUX_rg_lsr$write_1__SEL_3 or MUX_rg_lsr$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset: rg_lsr$D_IN = 8'd96; - WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h4516; - MUX_rg_lsr$write_1__SEL_3: rg_lsr$D_IN = MUX_rg_lsr$write_1__VAL_3; - default: rg_lsr$D_IN = 8'b10101010 /* unspecified value */ ; - endcase - assign rg_lsr$EN = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 || - WILL_FIRE_RL_rl_receive || - WILL_FIRE_RL_rl_reset ; - - // register rg_mcr - assign rg_mcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_mcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h4 || - WILL_FIRE_RL_rl_reset ; - - // register rg_msr - assign rg_msr$D_IN = 8'd0 ; - assign rg_msr$EN = CAN_FIRE_RL_rl_reset ; - - // register rg_rbr - assign rg_rbr$D_IN = f_from_console$D_OUT ; - assign rg_rbr$EN = WILL_FIRE_RL_rl_receive ; - - // register rg_scr - assign rg_scr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_scr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h7 || - WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = 1'd1 ; - assign rg_state$EN = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // register rg_thr - assign rg_thr$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_thr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - - // submodule f_from_console - assign f_from_console$D_IN = put_from_console_put ; - assign f_from_console$ENQ = EN_put_from_console_put ; - assign f_from_console$DEQ = WILL_FIRE_RL_rl_receive ; - assign f_from_console$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_to_console - assign f_to_console$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign f_to_console$ENQ = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - assign f_to_console$DEQ = EN_get_to_console_get ; - assign f_to_console$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h2759, - rdr_rresp__h2792, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3147 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_24___d125 = cfg_verbosity > 8'd1 ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - slave_xactor_f_wr_data$D_OUT[0] ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - !slave_xactor_f_wr_data$D_OUT[0] ; - assign fn_iir__h1356 = - (rg_ier[0] && rg_lsr[0]) ? 8'h04 : (rg_ier[1] ? 8'h02 : 8'd0) ; - assign new_lsr__h4516 = { rg_lsr[7:1], 1'd1 } ; - assign rdata__h2759 = { 56'd0, x__h2797 } ; - assign rdr_rresp__h2792 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0) ? - y_avValue_fst__h2751 : - 2'b10 ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 = - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - rg_lcr[7] ; - assign slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 = - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1] || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7] || - f_to_console$FULL_N) ; - assign v__h3147 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) ? - 2'b10 : - v__h3395 ; - assign v__h3395 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0) ? - v__h3575 : - 2'b11 ; - assign v__h3575 = y_avValue_fst__h2737 ; - assign x__h2797 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0 || - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) ? - 8'd0 : - y_avValue_snd__h2738 ; - assign y_avValue_fst__h2737 = 2'b0 ; - assign y_avValue_fst__h2751 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0) ? - y_avValue_fst__h2737 : - 2'b11 ; - assign y_avValue_snd__h2696 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - rg_lcr[7]) ? - rg_dlm : - y_avValue_snd__h2683 ; - assign y_avValue_snd__h2709 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - !rg_lcr[7]) ? - rg_ier : - y_avValue_snd__h2696 ; - assign y_avValue_snd__h2724 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - rg_lcr[7]) ? - rg_dll : - y_avValue_snd__h2709 ; - assign y_avValue_snd__h2738 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7]) ? - rg_rbr : - y_avValue_snd__h2724 ; - always@(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 or - fn_iir__h1356 or rg_lcr or rg_mcr or rg_lsr or rg_msr or rg_scr) - begin - case (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3]) - 3'h2: y_avValue_snd__h2683 = fn_iir__h1356; - 3'h3: y_avValue_snd__h2683 = rg_lcr; - 3'h4: y_avValue_snd__h2683 = rg_mcr; - 3'h5: y_avValue_snd__h2683 = rg_lsr; - 3'h6: y_avValue_snd__h2683 = rg_msr; - 3'h7: y_avValue_snd__h2683 = rg_scr; - default: y_avValue_snd__h2683 = 8'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dll <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dlm <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_fcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_ier <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lsr <= `BSV_ASSIGNMENT_DELAY 8'd96; - rg_mcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_msr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_scr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_dll$EN) rg_dll <= `BSV_ASSIGNMENT_DELAY rg_dll$D_IN; - if (rg_dlm$EN) rg_dlm <= `BSV_ASSIGNMENT_DELAY rg_dlm$D_IN; - if (rg_fcr$EN) rg_fcr <= `BSV_ASSIGNMENT_DELAY rg_fcr$D_IN; - if (rg_ier$EN) rg_ier <= `BSV_ASSIGNMENT_DELAY rg_ier$D_IN; - if (rg_lcr$EN) rg_lcr <= `BSV_ASSIGNMENT_DELAY rg_lcr$D_IN; - if (rg_lsr$EN) rg_lsr <= `BSV_ASSIGNMENT_DELAY rg_lsr$D_IN; - if (rg_mcr$EN) rg_mcr <= `BSV_ASSIGNMENT_DELAY rg_mcr$D_IN; - if (rg_msr$EN) rg_msr <= `BSV_ASSIGNMENT_DELAY rg_msr$D_IN; - if (rg_scr$EN) rg_scr <= `BSV_ASSIGNMENT_DELAY rg_scr$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_rbr$EN) rg_rbr <= `BSV_ASSIGNMENT_DELAY rg_rbr$D_IN; - if (rg_thr$EN) rg_thr <= `BSV_ASSIGNMENT_DELAY rg_thr$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 8'hAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_dll = 8'hAA; - rg_dlm = 8'hAA; - rg_fcr = 8'hAA; - rg_ier = 8'hAA; - rg_lcr = 8'hAA; - rg_lsr = 8'hAA; - rg_mcr = 8'hAA; - rg_msr = 8'hAA; - rg_rbr = 8'hAA; - rg_scr = 8'hAA; - rg_state = 1'h0; - rg_thr = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - begin - v__h2519 = $stime; - #0; - end - v__h2513 = v__h2519 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2513); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - begin - v__h2187 = $stime; - #0; - end - v__h2181 = v__h2187 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2181); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - begin - v__h2025 = $stime; - #0; - end - v__h2019 = v__h2025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: misaligned addr", - v__h2019); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h2898 = $stime; - #0; - end - v__h2892 = v__h2898 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_rd_req", v__h2892); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdata__h2759); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdr_rresp__h2792); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - begin - v__h3244 = $stime; - #0; - end - v__h3238 = v__h3244 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $display("%0d: ERROR: UART.rl_process_wr_req: misaligned addr", - v__h3238); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - begin - v__h4006 = $stime; - #0; - end - v__h4000 = v__h4006 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h4000); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - begin - v__h3449 = $stime; - #0; - end - v__h3443 = v__h3449 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h3443); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h4306 = $stime; - #0; - end - v__h4300 = v__h4306 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_wr_req", v__h4300); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", v__h3147); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h4749 = $stime; - #0; - end - v__h4743 = v__h4749 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_base 0x%0h is not 8-Byte-aligned", - v__h4743, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h4859 = $stime; - #0; - end - v__h4853 = v__h4859 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_lim 0x%0h is not 8-Byte-aligned", - v__h4853, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_receive && NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("UART_Model.rl_receive: received char 0x%0h; new_lsr = 0x%0h", - f_from_console$D_OUT, - new_lsr__h4516); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - begin - v__h1811 = $stime; - #0; - end - v__h1805 = v__h1811 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - $display("%0d: UART.rl_reset", v__h1805); - end - // synopsys translate_on -endmodule // mkUART - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v deleted file mode 100644 index 1cb3bfa4..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v +++ /dev/null @@ -1,1415 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// from_master_awready O 1 reg -// from_master_wready O 1 reg -// from_master_bvalid O 1 reg -// from_master_bid O 4 reg -// from_master_bresp O 2 reg -// from_master_arready O 1 reg -// from_master_rvalid O 1 reg -// from_master_rid O 4 reg -// from_master_rdata O 64 reg -// from_master_rresp O 2 reg -// from_master_rlast O 1 reg -// to_slave_awvalid O 1 reg -// to_slave_awid O 4 reg -// to_slave_awaddr O 64 reg -// to_slave_awlen O 8 reg -// to_slave_awsize O 3 reg -// to_slave_awburst O 2 reg -// to_slave_awlock O 1 reg -// to_slave_awcache O 4 reg -// to_slave_awprot O 3 reg -// to_slave_awqos O 4 reg -// to_slave_awregion O 4 reg -// to_slave_wvalid O 1 reg -// to_slave_wid O 4 reg -// to_slave_wdata O 64 reg -// to_slave_wstrb O 8 reg -// to_slave_wlast O 1 reg -// to_slave_bready O 1 reg -// to_slave_arvalid O 1 reg -// to_slave_arid O 4 reg -// to_slave_araddr O 64 reg -// to_slave_arlen O 8 reg -// to_slave_arsize O 3 reg -// to_slave_arburst O 2 reg -// to_slave_arlock O 1 reg -// to_slave_arcache O 4 reg -// to_slave_arprot O 3 reg -// to_slave_arqos O 4 reg -// to_slave_arregion O 4 reg -// to_slave_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// from_master_awvalid I 1 -// from_master_awid I 4 reg -// from_master_awaddr I 64 reg -// from_master_awlen I 8 reg -// from_master_awsize I 3 reg -// from_master_awburst I 2 reg -// from_master_awlock I 1 reg -// from_master_awcache I 4 reg -// from_master_awprot I 3 reg -// from_master_awqos I 4 reg -// from_master_awregion I 4 reg -// from_master_wvalid I 1 -// from_master_wid I 4 reg -// from_master_wdata I 64 reg -// from_master_wstrb I 8 reg -// from_master_wlast I 1 reg -// from_master_bready I 1 -// from_master_arvalid I 1 -// from_master_arid I 4 reg -// from_master_araddr I 64 reg -// from_master_arlen I 8 reg -// from_master_arsize I 3 reg -// from_master_arburst I 2 reg -// from_master_arlock I 1 reg -// from_master_arcache I 4 reg -// from_master_arprot I 3 reg -// from_master_arqos I 4 reg -// from_master_arregion I 4 reg -// from_master_rready I 1 -// to_slave_awready I 1 -// to_slave_wready I 1 -// to_slave_bvalid I 1 -// to_slave_bid I 4 reg -// to_slave_bresp I 2 reg -// to_slave_arready I 1 -// to_slave_rvalid I 1 -// to_slave_rid I 4 reg -// to_slave_rdata I 64 reg -// to_slave_rresp I 2 reg -// to_slave_rlast I 1 reg -// EN_reset I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkAXI4_Deburster_A(CLK, - RST_N, - - EN_reset, - RDY_reset, - - from_master_awvalid, - from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion, - - from_master_awready, - - from_master_wvalid, - from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast, - - from_master_wready, - - from_master_bvalid, - - from_master_bid, - - from_master_bresp, - - from_master_bready, - - from_master_arvalid, - from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion, - - from_master_arready, - - from_master_rvalid, - - from_master_rid, - - from_master_rdata, - - from_master_rresp, - - from_master_rlast, - - from_master_rready, - - to_slave_awvalid, - - to_slave_awid, - - to_slave_awaddr, - - to_slave_awlen, - - to_slave_awsize, - - to_slave_awburst, - - to_slave_awlock, - - to_slave_awcache, - - to_slave_awprot, - - to_slave_awqos, - - to_slave_awregion, - - to_slave_awready, - - to_slave_wvalid, - - to_slave_wid, - - to_slave_wdata, - - to_slave_wstrb, - - to_slave_wlast, - - to_slave_wready, - - to_slave_bvalid, - to_slave_bid, - to_slave_bresp, - - to_slave_bready, - - to_slave_arvalid, - - to_slave_arid, - - to_slave_araddr, - - to_slave_arlen, - - to_slave_arsize, - - to_slave_arburst, - - to_slave_arlock, - - to_slave_arcache, - - to_slave_arprot, - - to_slave_arqos, - - to_slave_arregion, - - to_slave_arready, - - to_slave_rvalid, - to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast, - - to_slave_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method from_master_m_awvalid - input from_master_awvalid; - input [3 : 0] from_master_awid; - input [63 : 0] from_master_awaddr; - input [7 : 0] from_master_awlen; - input [2 : 0] from_master_awsize; - input [1 : 0] from_master_awburst; - input from_master_awlock; - input [3 : 0] from_master_awcache; - input [2 : 0] from_master_awprot; - input [3 : 0] from_master_awqos; - input [3 : 0] from_master_awregion; - - // value method from_master_m_awready - output from_master_awready; - - // action method from_master_m_wvalid - input from_master_wvalid; - input [3 : 0] from_master_wid; - input [63 : 0] from_master_wdata; - input [7 : 0] from_master_wstrb; - input from_master_wlast; - - // value method from_master_m_wready - output from_master_wready; - - // value method from_master_m_bvalid - output from_master_bvalid; - - // value method from_master_m_bid - output [3 : 0] from_master_bid; - - // value method from_master_m_bresp - output [1 : 0] from_master_bresp; - - // value method from_master_m_buser - - // action method from_master_m_bready - input from_master_bready; - - // action method from_master_m_arvalid - input from_master_arvalid; - input [3 : 0] from_master_arid; - input [63 : 0] from_master_araddr; - input [7 : 0] from_master_arlen; - input [2 : 0] from_master_arsize; - input [1 : 0] from_master_arburst; - input from_master_arlock; - input [3 : 0] from_master_arcache; - input [2 : 0] from_master_arprot; - input [3 : 0] from_master_arqos; - input [3 : 0] from_master_arregion; - - // value method from_master_m_arready - output from_master_arready; - - // value method from_master_m_rvalid - output from_master_rvalid; - - // value method from_master_m_rid - output [3 : 0] from_master_rid; - - // value method from_master_m_rdata - output [63 : 0] from_master_rdata; - - // value method from_master_m_rresp - output [1 : 0] from_master_rresp; - - // value method from_master_m_rlast - output from_master_rlast; - - // value method from_master_m_ruser - - // action method from_master_m_rready - input from_master_rready; - - // value method to_slave_m_awvalid - output to_slave_awvalid; - - // value method to_slave_m_awid - output [3 : 0] to_slave_awid; - - // value method to_slave_m_awaddr - output [63 : 0] to_slave_awaddr; - - // value method to_slave_m_awlen - output [7 : 0] to_slave_awlen; - - // value method to_slave_m_awsize - output [2 : 0] to_slave_awsize; - - // value method to_slave_m_awburst - output [1 : 0] to_slave_awburst; - - // value method to_slave_m_awlock - output to_slave_awlock; - - // value method to_slave_m_awcache - output [3 : 0] to_slave_awcache; - - // value method to_slave_m_awprot - output [2 : 0] to_slave_awprot; - - // value method to_slave_m_awqos - output [3 : 0] to_slave_awqos; - - // value method to_slave_m_awregion - output [3 : 0] to_slave_awregion; - - // value method to_slave_m_awuser - - // action method to_slave_m_awready - input to_slave_awready; - - // value method to_slave_m_wvalid - output to_slave_wvalid; - - // value method to_slave_m_wid - output [3 : 0] to_slave_wid; - - // value method to_slave_m_wdata - output [63 : 0] to_slave_wdata; - - // value method to_slave_m_wstrb - output [7 : 0] to_slave_wstrb; - - // value method to_slave_m_wlast - output to_slave_wlast; - - // value method to_slave_m_wuser - - // action method to_slave_m_wready - input to_slave_wready; - - // action method to_slave_m_bvalid - input to_slave_bvalid; - input [3 : 0] to_slave_bid; - input [1 : 0] to_slave_bresp; - - // value method to_slave_m_bready - output to_slave_bready; - - // value method to_slave_m_arvalid - output to_slave_arvalid; - - // value method to_slave_m_arid - output [3 : 0] to_slave_arid; - - // value method to_slave_m_araddr - output [63 : 0] to_slave_araddr; - - // value method to_slave_m_arlen - output [7 : 0] to_slave_arlen; - - // value method to_slave_m_arsize - output [2 : 0] to_slave_arsize; - - // value method to_slave_m_arburst - output [1 : 0] to_slave_arburst; - - // value method to_slave_m_arlock - output to_slave_arlock; - - // value method to_slave_m_arcache - output [3 : 0] to_slave_arcache; - - // value method to_slave_m_arprot - output [2 : 0] to_slave_arprot; - - // value method to_slave_m_arqos - output [3 : 0] to_slave_arqos; - - // value method to_slave_m_arregion - output [3 : 0] to_slave_arregion; - - // value method to_slave_m_aruser - - // action method to_slave_m_arready - input to_slave_arready; - - // action method to_slave_m_rvalid - input to_slave_rvalid; - input [3 : 0] to_slave_rid; - input [63 : 0] to_slave_rdata; - input [1 : 0] to_slave_rresp; - input to_slave_rlast; - - // value method to_slave_m_rready - output to_slave_rready; - - // signals for module outputs - wire [63 : 0] from_master_rdata, - to_slave_araddr, - to_slave_awaddr, - to_slave_wdata; - wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb; - wire [3 : 0] from_master_bid, - from_master_rid, - to_slave_arcache, - to_slave_arid, - to_slave_arqos, - to_slave_arregion, - to_slave_awcache, - to_slave_awid, - to_slave_awqos, - to_slave_awregion, - to_slave_wid; - wire [2 : 0] to_slave_arprot, - to_slave_arsize, - to_slave_awprot, - to_slave_awsize; - wire [1 : 0] from_master_bresp, - from_master_rresp, - to_slave_arburst, - to_slave_awburst; - wire RDY_reset, - from_master_arready, - from_master_awready, - from_master_bvalid, - from_master_rlast, - from_master_rvalid, - from_master_wready, - to_slave_arlock, - to_slave_arvalid, - to_slave_awlock, - to_slave_awvalid, - to_slave_bready, - to_slave_rready, - to_slave_wlast, - to_slave_wvalid; - - // register m_rg_ar_beat_count - reg [7 : 0] m_rg_ar_beat_count; - wire [7 : 0] m_rg_ar_beat_count$D_IN; - wire m_rg_ar_beat_count$EN; - - // register m_rg_b_beat_count - reg [7 : 0] m_rg_b_beat_count; - wire [7 : 0] m_rg_b_beat_count$D_IN; - wire m_rg_b_beat_count$EN; - - // register m_rg_b_resp - reg [1 : 0] m_rg_b_resp; - wire [1 : 0] m_rg_b_resp$D_IN; - wire m_rg_b_resp$EN; - - // register m_rg_r_beat_count - reg [7 : 0] m_rg_r_beat_count; - wire [7 : 0] m_rg_r_beat_count$D_IN; - wire m_rg_r_beat_count$EN; - - // register m_rg_reset - reg m_rg_reset; - wire m_rg_reset$D_IN, m_rg_reset$EN; - - // register m_rg_w_beat_count - reg [7 : 0] m_rg_w_beat_count; - wire [7 : 0] m_rg_w_beat_count$D_IN; - wire m_rg_w_beat_count$EN; - - // ports of submodule m_f_r_arlen - wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT; - wire m_f_r_arlen$CLR, - m_f_r_arlen$DEQ, - m_f_r_arlen$EMPTY_N, - m_f_r_arlen$ENQ, - m_f_r_arlen$FULL_N; - - // ports of submodule m_f_w_awlen - wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT; - wire m_f_w_awlen$CLR, - m_f_w_awlen$DEQ, - m_f_w_awlen$EMPTY_N, - m_f_w_awlen$ENQ, - m_f_w_awlen$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_addr - wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN, - m_xactor_from_master_f_rd_addr$D_OUT; - wire m_xactor_from_master_f_rd_addr$CLR, - m_xactor_from_master_f_rd_addr$DEQ, - m_xactor_from_master_f_rd_addr$EMPTY_N, - m_xactor_from_master_f_rd_addr$ENQ, - m_xactor_from_master_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_data - wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN, - m_xactor_from_master_f_rd_data$D_OUT; - wire m_xactor_from_master_f_rd_data$CLR, - m_xactor_from_master_f_rd_data$DEQ, - m_xactor_from_master_f_rd_data$EMPTY_N, - m_xactor_from_master_f_rd_data$ENQ, - m_xactor_from_master_f_rd_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_addr - wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN, - m_xactor_from_master_f_wr_addr$D_OUT; - wire m_xactor_from_master_f_wr_addr$CLR, - m_xactor_from_master_f_wr_addr$DEQ, - m_xactor_from_master_f_wr_addr$EMPTY_N, - m_xactor_from_master_f_wr_addr$ENQ, - m_xactor_from_master_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_data - wire [76 : 0] m_xactor_from_master_f_wr_data$D_IN, - m_xactor_from_master_f_wr_data$D_OUT; - wire m_xactor_from_master_f_wr_data$CLR, - m_xactor_from_master_f_wr_data$DEQ, - m_xactor_from_master_f_wr_data$EMPTY_N, - m_xactor_from_master_f_wr_data$ENQ, - m_xactor_from_master_f_wr_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_resp - wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN, - m_xactor_from_master_f_wr_resp$D_OUT; - wire m_xactor_from_master_f_wr_resp$CLR, - m_xactor_from_master_f_wr_resp$DEQ, - m_xactor_from_master_f_wr_resp$EMPTY_N, - m_xactor_from_master_f_wr_resp$ENQ, - m_xactor_from_master_f_wr_resp$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_addr - wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN, - m_xactor_to_slave_f_rd_addr$D_OUT; - wire m_xactor_to_slave_f_rd_addr$CLR, - m_xactor_to_slave_f_rd_addr$DEQ, - m_xactor_to_slave_f_rd_addr$EMPTY_N, - m_xactor_to_slave_f_rd_addr$ENQ, - m_xactor_to_slave_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_data - wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN, - m_xactor_to_slave_f_rd_data$D_OUT; - wire m_xactor_to_slave_f_rd_data$CLR, - m_xactor_to_slave_f_rd_data$DEQ, - m_xactor_to_slave_f_rd_data$EMPTY_N, - m_xactor_to_slave_f_rd_data$ENQ, - m_xactor_to_slave_f_rd_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_addr - wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN, - m_xactor_to_slave_f_wr_addr$D_OUT; - wire m_xactor_to_slave_f_wr_addr$CLR, - m_xactor_to_slave_f_wr_addr$DEQ, - m_xactor_to_slave_f_wr_addr$EMPTY_N, - m_xactor_to_slave_f_wr_addr$ENQ, - m_xactor_to_slave_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_data - wire [76 : 0] m_xactor_to_slave_f_wr_data$D_IN, - m_xactor_to_slave_f_wr_data$D_OUT; - wire m_xactor_to_slave_f_wr_data$CLR, - m_xactor_to_slave_f_wr_data$DEQ, - m_xactor_to_slave_f_wr_data$EMPTY_N, - m_xactor_to_slave_f_wr_data$ENQ, - m_xactor_to_slave_f_wr_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_resp - wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN, - m_xactor_to_slave_f_wr_resp$D_OUT; - wire m_xactor_to_slave_f_wr_resp$CLR, - m_xactor_to_slave_f_wr_resp$DEQ, - m_xactor_to_slave_f_wr_resp$EMPTY_N, - m_xactor_to_slave_f_wr_resp$ENQ, - m_xactor_to_slave_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave, - CAN_FIRE_from_master_m_arvalid, - CAN_FIRE_from_master_m_awvalid, - CAN_FIRE_from_master_m_bready, - CAN_FIRE_from_master_m_rready, - CAN_FIRE_from_master_m_wvalid, - CAN_FIRE_reset, - CAN_FIRE_to_slave_m_arready, - CAN_FIRE_to_slave_m_awready, - CAN_FIRE_to_slave_m_bvalid, - CAN_FIRE_to_slave_m_rvalid, - CAN_FIRE_to_slave_m_wready, - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave, - WILL_FIRE_from_master_m_arvalid, - WILL_FIRE_from_master_m_awvalid, - WILL_FIRE_from_master_m_bready, - WILL_FIRE_from_master_m_rready, - WILL_FIRE_from_master_m_wvalid, - WILL_FIRE_reset, - WILL_FIRE_to_slave_m_arready, - WILL_FIRE_to_slave_m_awready, - WILL_FIRE_to_slave_m_bvalid, - WILL_FIRE_to_slave_m_rvalid, - WILL_FIRE_to_slave_m_wready; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2, - MUX_m_rg_b_beat_count$write_1__VAL_2, - MUX_m_rg_r_beat_count$write_1__VAL_2, - MUX_m_rg_w_beat_count$write_1__VAL_2; - wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2; - wire MUX_m_rg_b_resp$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2430; - reg [31 : 0] v__h1446; - reg [31 : 0] v__h1440; - reg [31 : 0] v__h2424; - // synopsys translate_on - - // remaining internal signals - wire [63 : 0] a_out_araddr__h2944, - a_out_awaddr__h1951, - addr___1__h2036, - addr___1__h3029; - wire [7 : 0] x__h2305, x__h2798, x__h3190, x__h3388; - wire m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95, - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51, - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106, - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35; - - // action method reset - assign RDY_reset = !m_rg_reset ; - assign CAN_FIRE_reset = !m_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method from_master_m_awvalid - assign CAN_FIRE_from_master_m_awvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_awvalid = 1'd1 ; - - // value method from_master_m_awready - assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ; - - // action method from_master_m_wvalid - assign CAN_FIRE_from_master_m_wvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_wvalid = 1'd1 ; - - // value method from_master_m_wready - assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ; - - // value method from_master_m_bvalid - assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ; - - // value method from_master_m_bid - assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ; - - // value method from_master_m_bresp - assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ; - - // action method from_master_m_bready - assign CAN_FIRE_from_master_m_bready = 1'd1 ; - assign WILL_FIRE_from_master_m_bready = 1'd1 ; - - // action method from_master_m_arvalid - assign CAN_FIRE_from_master_m_arvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_arvalid = 1'd1 ; - - // value method from_master_m_arready - assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ; - - // value method from_master_m_rvalid - assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ; - - // value method from_master_m_rid - assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ; - - // value method from_master_m_rdata - assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ; - - // value method from_master_m_rresp - assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ; - - // value method from_master_m_rlast - assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ; - - // action method from_master_m_rready - assign CAN_FIRE_from_master_m_rready = 1'd1 ; - assign WILL_FIRE_from_master_m_rready = 1'd1 ; - - // value method to_slave_m_awvalid - assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ; - - // value method to_slave_m_awid - assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ; - - // value method to_slave_m_awaddr - assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ; - - // value method to_slave_m_awlen - assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ; - - // value method to_slave_m_awsize - assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ; - - // value method to_slave_m_awburst - assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ; - - // value method to_slave_m_awlock - assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ; - - // value method to_slave_m_awcache - assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ; - - // value method to_slave_m_awprot - assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ; - - // value method to_slave_m_awqos - assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ; - - // value method to_slave_m_awregion - assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ; - - // action method to_slave_m_awready - assign CAN_FIRE_to_slave_m_awready = 1'd1 ; - assign WILL_FIRE_to_slave_m_awready = 1'd1 ; - - // value method to_slave_m_wvalid - assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ; - - // value method to_slave_m_wid - assign to_slave_wid = m_xactor_to_slave_f_wr_data$D_OUT[76:73] ; - - // value method to_slave_m_wdata - assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ; - - // value method to_slave_m_wstrb - assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ; - - // value method to_slave_m_wlast - assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ; - - // action method to_slave_m_wready - assign CAN_FIRE_to_slave_m_wready = 1'd1 ; - assign WILL_FIRE_to_slave_m_wready = 1'd1 ; - - // action method to_slave_m_bvalid - assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ; - - // value method to_slave_m_bready - assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ; - - // value method to_slave_m_arvalid - assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ; - - // value method to_slave_m_arid - assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ; - - // value method to_slave_m_araddr - assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ; - - // value method to_slave_m_arlen - assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ; - - // value method to_slave_m_arsize - assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ; - - // value method to_slave_m_arburst - assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ; - - // value method to_slave_m_arlock - assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ; - - // value method to_slave_m_arcache - assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ; - - // value method to_slave_m_arprot - assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ; - - // value method to_slave_m_arqos - assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ; - - // value method to_slave_m_arregion - assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ; - - // action method to_slave_m_arready - assign CAN_FIRE_to_slave_m_arready = 1'd1 ; - assign WILL_FIRE_to_slave_m_arready = 1'd1 ; - - // action method to_slave_m_rvalid - assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ; - - // value method to_slave_m_rready - assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ; - - // submodule m_f_r_arlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_r_arlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_r_arlen$D_IN), - .ENQ(m_f_r_arlen$ENQ), - .DEQ(m_f_r_arlen$DEQ), - .CLR(m_f_r_arlen$CLR), - .D_OUT(m_f_r_arlen$D_OUT), - .FULL_N(m_f_r_arlen$FULL_N), - .EMPTY_N(m_f_r_arlen$EMPTY_N)); - - // submodule m_f_w_awlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_w_awlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_w_awlen$D_IN), - .ENQ(m_f_w_awlen$ENQ), - .DEQ(m_f_w_awlen$DEQ), - .CLR(m_f_w_awlen$CLR), - .D_OUT(m_f_w_awlen$D_OUT), - .FULL_N(m_f_w_awlen$FULL_N), - .EMPTY_N(m_f_w_awlen$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_addr$D_IN), - .ENQ(m_xactor_from_master_f_rd_addr$ENQ), - .DEQ(m_xactor_from_master_f_rd_addr$DEQ), - .CLR(m_xactor_from_master_f_rd_addr$CLR), - .D_OUT(m_xactor_from_master_f_rd_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_data$D_IN), - .ENQ(m_xactor_from_master_f_rd_data$ENQ), - .DEQ(m_xactor_from_master_f_rd_data$DEQ), - .CLR(m_xactor_from_master_f_rd_data$CLR), - .D_OUT(m_xactor_from_master_f_rd_data$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_addr$D_IN), - .ENQ(m_xactor_from_master_f_wr_addr$ENQ), - .DEQ(m_xactor_from_master_f_wr_addr$DEQ), - .CLR(m_xactor_from_master_f_wr_addr$CLR), - .D_OUT(m_xactor_from_master_f_wr_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_data$D_IN), - .ENQ(m_xactor_from_master_f_wr_data$ENQ), - .DEQ(m_xactor_from_master_f_wr_data$DEQ), - .CLR(m_xactor_from_master_f_wr_data$CLR), - .D_OUT(m_xactor_from_master_f_wr_data$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_resp$D_IN), - .ENQ(m_xactor_from_master_f_wr_resp$ENQ), - .DEQ(m_xactor_from_master_f_wr_resp$DEQ), - .CLR(m_xactor_from_master_f_wr_resp$CLR), - .D_OUT(m_xactor_from_master_f_wr_resp$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_addr$D_IN), - .ENQ(m_xactor_to_slave_f_rd_addr$ENQ), - .DEQ(m_xactor_to_slave_f_rd_addr$DEQ), - .CLR(m_xactor_to_slave_f_rd_addr$CLR), - .D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_data$D_IN), - .ENQ(m_xactor_to_slave_f_rd_data$ENQ), - .DEQ(m_xactor_to_slave_f_rd_data$DEQ), - .CLR(m_xactor_to_slave_f_rd_data$CLR), - .D_OUT(m_xactor_to_slave_f_rd_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_addr$D_IN), - .ENQ(m_xactor_to_slave_f_wr_addr$ENQ), - .DEQ(m_xactor_to_slave_f_wr_addr$DEQ), - .CLR(m_xactor_to_slave_f_wr_addr$CLR), - .D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_data$D_IN), - .ENQ(m_xactor_to_slave_f_wr_data$ENQ), - .DEQ(m_xactor_to_slave_f_wr_data$DEQ), - .CLR(m_xactor_to_slave_f_wr_data$CLR), - .D_OUT(m_xactor_to_slave_f_wr_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_resp$D_IN), - .ENQ(m_xactor_to_slave_f_wr_resp$ENQ), - .DEQ(m_xactor_to_slave_f_wr_resp$DEQ), - .CLR(m_xactor_to_slave_f_wr_resp$CLR), - .D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave = - m_xactor_to_slave_f_wr_addr$FULL_N && - m_xactor_from_master_f_wr_addr$EMPTY_N && - m_xactor_to_slave_f_wr_data$FULL_N && - m_xactor_from_master_f_wr_data$EMPTY_N && - (m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - - // rule RL_m_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master = - m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N && - (m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 || - m_xactor_from_master_f_wr_resp$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - - // rule RL_m_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave = - m_xactor_to_slave_f_rd_addr$FULL_N && - m_xactor_from_master_f_rd_addr$EMPTY_N && - (m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - - // rule RL_m_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master = - m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N && - m_xactor_from_master_f_rd_data$FULL_N ; - assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ; - assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_b_resp$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - (m_rg_b_resp == 2'b0 && - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 || - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51) ; - assign MUX_m_rg_ar_beat_count$write_1__VAL_2 = - m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ? - x__h3190 : - 8'd0 ; - assign MUX_m_rg_b_beat_count$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - x__h2798 : - 8'd0 ; - assign MUX_m_rg_b_resp$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - 2'b0 ; - assign MUX_m_rg_r_beat_count$write_1__VAL_2 = - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ? - x__h3388 : - 8'd0 ; - assign MUX_m_rg_w_beat_count$write_1__VAL_2 = - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ? - x__h2305 : - 8'd0 ; - - // register m_rg_ar_beat_count - assign m_rg_ar_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ; - assign m_rg_ar_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ; - - // register m_rg_b_beat_count - assign m_rg_b_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ; - assign m_rg_b_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ; - - // register m_rg_b_resp - assign m_rg_b_resp$D_IN = - m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ; - assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ; - - // register m_rg_r_beat_count - assign m_rg_r_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ; - assign m_rg_r_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ; - - // register m_rg_reset - assign m_rg_reset$D_IN = !m_rg_reset ; - assign m_rg_reset$EN = m_rg_reset || EN_reset ; - - // register m_rg_w_beat_count - assign m_rg_w_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ; - assign m_rg_w_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ; - - // submodule m_f_r_arlen - assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_f_r_arlen$ENQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - m_rg_ar_beat_count == 8'd0 ; - assign m_f_r_arlen$DEQ = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master && - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ; - assign m_f_r_arlen$CLR = m_rg_reset ; - - // submodule m_f_w_awlen - assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign m_f_w_awlen$ENQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - m_rg_w_beat_count == 8'd0 ; - assign m_f_w_awlen$DEQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_f_w_awlen$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_addr - assign m_xactor_from_master_f_rd_addr$D_IN = - { from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion } ; - assign m_xactor_from_master_f_rd_addr$ENQ = - from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ; - assign m_xactor_from_master_f_rd_addr$DEQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - !m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ; - assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_data - assign m_xactor_from_master_f_rd_data$D_IN = - { m_xactor_to_slave_f_rd_data$D_OUT[70:1], - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 } ; - assign m_xactor_from_master_f_rd_data$ENQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_from_master_f_rd_data$DEQ = - from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ; - assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_addr - assign m_xactor_from_master_f_wr_addr$D_IN = - { from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion } ; - assign m_xactor_from_master_f_wr_addr$ENQ = - from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ; - assign m_xactor_from_master_f_wr_addr$DEQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ; - assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_data - assign m_xactor_from_master_f_wr_data$D_IN = - { from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast } ; - assign m_xactor_from_master_f_wr_data$ENQ = - from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ; - assign m_xactor_from_master_f_wr_data$DEQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_resp - assign m_xactor_from_master_f_wr_resp$D_IN = - { m_xactor_to_slave_f_wr_resp$D_OUT[5:2], - (m_rg_b_resp == 2'b0) ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - m_rg_b_resp } ; - assign m_xactor_from_master_f_wr_resp$ENQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_xactor_from_master_f_wr_resp$DEQ = - from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ; - assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_addr - assign m_xactor_to_slave_f_rd_addr$D_IN = - { m_xactor_from_master_f_rd_addr$D_OUT[96:93], - a_out_araddr__h2944, - 8'd0, - m_xactor_from_master_f_rd_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_rd_addr$ENQ = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - assign m_xactor_to_slave_f_rd_addr$DEQ = - m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ; - assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_data - assign m_xactor_to_slave_f_rd_data$D_IN = - { to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast } ; - assign m_xactor_to_slave_f_rd_data$ENQ = - to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ; - assign m_xactor_to_slave_f_rd_data$DEQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_addr - assign m_xactor_to_slave_f_wr_addr$D_IN = - { m_xactor_from_master_f_wr_addr$D_OUT[96:93], - a_out_awaddr__h1951, - 8'd0, - m_xactor_from_master_f_wr_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_wr_addr$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_addr$DEQ = - m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ; - assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_data - assign m_xactor_to_slave_f_wr_data$D_IN = - { m_xactor_from_master_f_wr_data$D_OUT[76:1], 1'd1 } ; - assign m_xactor_to_slave_f_wr_data$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_data$DEQ = - m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ; - assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_resp - assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ; - assign m_xactor_to_slave_f_wr_resp$ENQ = - to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ; - assign m_xactor_to_slave_f_wr_resp$DEQ = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ; - - // remaining internal signals - assign a_out_araddr__h2944 = - (m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h3029 : - m_xactor_from_master_f_rd_addr$D_OUT[92:29] ; - assign a_out_awaddr__h1951 = - (m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h2036 : - m_xactor_from_master_f_wr_addr$D_OUT[92:29] ; - assign addr___1__h2036 = - m_xactor_from_master_f_wr_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_w_beat_count } << - m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ; - assign addr___1__h3029 = - m_xactor_from_master_f_rd_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_ar_beat_count } << - m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ; - assign m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 = - m_rg_ar_beat_count < - m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 = - m_rg_b_beat_count < m_f_w_awlen$D_OUT ; - assign m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 = - m_rg_r_beat_count < m_f_r_arlen$D_OUT ; - assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 = - m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign x__h2305 = m_rg_w_beat_count + 8'd1 ; - assign x__h2798 = m_rg_b_beat_count + 8'd1 ; - assign x__h3190 = m_rg_ar_beat_count + 8'd1 ; - assign x__h3388 = m_rg_r_beat_count + 8'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0; - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (m_rg_ar_beat_count$EN) - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN; - if (m_rg_b_beat_count$EN) - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN; - if (m_rg_b_resp$EN) - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN; - if (m_rg_r_beat_count$EN) - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN; - if (m_rg_reset$EN) - m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN; - if (m_rg_w_beat_count$EN) - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_ar_beat_count = 8'hAA; - m_rg_b_beat_count = 8'hAA; - m_rg_b_resp = 2'h2; - m_rg_r_beat_count = 8'hAA; - m_rg_reset = 1'h0; - m_rg_w_beat_count = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - begin - v__h2430 = $stime; - #0; - end - v__h2424 = v__h2430 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", - v__h2424); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display(" WLAST not set on last data beat (awlen = %0d)", - m_xactor_from_master_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) - begin - v__h1446 = $stime; - #0; - end - v__h1440 = v__h1446 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) $display("%0d: %m::AXI4_Deburster.rl_reset", v__h1440); - end - // synopsys translate_on -endmodule // mkAXI4_Deburster_A - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v deleted file mode 100644 index 7b69d05e..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v +++ /dev/null @@ -1,2157 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkBoot_ROM(CLK, - RST_N, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready); - input CLK; - input RST_N; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_set_addr_map, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_module_ready - reg rg_module_ready; - wire rg_module_ready$D_IN, rg_module_ready$EN; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h808; - reg [31 : 0] v__h8928; - reg [31 : 0] v__h9221; - reg [31 : 0] v__h9331; - reg [31 : 0] v__h802; - reg [31 : 0] v__h8922; - reg [31 : 0] v__h9215; - reg [31 : 0] v__h9325; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] data64__h987; - reg [31 : 0] CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2; - wire [63 : 0] byte_addr__h705, rdata__h924; - wire [1 : 0] rdr_rresp__h957; - wire NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18, - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_module_ready - assign rg_module_ready$D_IN = 1'd1 ; - assign rg_module_ready$EN = EN_set_addr_map ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h924, - rdr_rresp__h957, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 ? - 2'b10 : - 2'b0 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = 1'b0 ; - - // remaining internal signals - assign NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 = - slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] || - slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ; - assign NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 = - slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] || - slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ; - assign byte_addr__h705 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign rdata__h924 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 64'd0 : - data64__h987 ; - assign rdr_rresp__h957 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 2'b10 : - 2'b0 ; - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16, - 64'd24, - 64'd56, - 64'd72, - 64'd80, - 64'd88, - 64'd200, - 64'd232, - 64'd312, - 64'd424, - 64'd448, - 64'd600, - 64'd728, - 64'd1136, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = 32'h0; - 64'd32: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h54040000; - 64'd40: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h88030000; - 64'd48: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h11000000; - 64'd64: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h50030000; - 64'd96, - 64'd112, - 64'd208, - 64'd224, - 64'd240, - 64'd432, - 64'd488, - 64'd872, - 64'd888: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h04000000; - 64'd104, 64'd120, 64'd504, 64'd792, 64'd920: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h02000000; - 64'd128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h16000000; - 64'd136: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h62626375; - 64'd144: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656B6970; - 64'd152: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65642D65; - 64'd160, - 64'd264, - 64'd280, - 64'd296, - 64'd336, - 64'd360, - 64'd384, - 64'd456, - 64'd552, - 64'd592, - 64'd608, - 64'd624, - 64'd672, - 64'd704, - 64'd760, - 64'd816, - 64'd840, - 64'd880: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h03000000; - 64'd168: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h26000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h732C7261; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7261622D; - 64'd192, - 64'd216, - 64'd400, - 64'd440, - 64'd496, - 64'd512, - 64'd584, - 64'd744, - 64'd752, - 64'd912: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h01000000; - 64'd248, 64'd896: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h80969800; - 64'd256: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40757063; - 64'd272: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h3F000000; - 64'd288, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4B000000; - 64'd304: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4F000000; - 64'd320: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h06000000; - 64'd328: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h63736972; - 64'd344: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h56000000; - 64'd352: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h75616D69; - 64'd368: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h60000000; - 64'd376: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h76732C76; - 64'd392: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69000000; - 64'd408: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70757272; - 64'd416: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F72746E; - 64'd464, 64'd632, 64'd712, 64'd824: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h1B000000; - 64'd472: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70632C76; - 64'd480: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00006374; - 64'd520: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h38407972; - 64'd528: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00303030; - 64'd536: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h07000000; - 64'd544: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D656D; - 64'd568: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000080; - 64'd576: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000010; - 64'd616: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h0F000000; - 64'd656: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69730063; - 64'd664: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7375622D; - 64'd680: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hA7000000; - 64'd688: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E696C63; - 64'd696, 64'd808: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h30303030; - 64'd720: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C632C76; - 64'd736: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h10000000; - 64'd776: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000002; - 64'd784: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000C00; - 64'd800: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h74726175; - 64'd832: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61303535; - 64'd856: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h000000C0; - 64'd864: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40000000; - 64'd904: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h08000000; - 64'd928: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h09000000; - 64'd936: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73736572; - 64'd944: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h2300736C; - 64'd952: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C65632D; - 64'd960: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61706D6F; - 64'd968: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D0065; - 64'd976: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656D6974; - 64'd984: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6572662D; - 64'd992: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h64007963; - 64'd1000: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79745F65; - 64'd1008: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73006765; - 64'd1016: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69720073; - 64'd1024: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00617369; - 64'd1032: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65707974; - 64'd1040: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h662D6B63; - 64'd1048: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79636E65; - 64'd1056, 64'd1072: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h72726574; - 64'd1064: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C6C6563; - 64'd1080: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h746E6F63; - 64'd1088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70007265; - 64'd1096: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7200656C; - 64'd1104: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E690073; - 64'd1112: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73747075; - 64'd1120: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65646E65; - 64'd1128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h68732D67; - default: CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00028067; - 64'd24: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80000000; - 64'd32: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hEDFE0DD0; - 64'd40: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h38000000; - 64'd48: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h28000000; - 64'd56, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h10000000; - 64'd64: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hCC000000; - 64'd72, - 64'd80, - 64'd104, - 64'd216, - 64'd296, - 64'd568, - 64'd576, - 64'd672, - 64'd680, - 64'd776, - 64'd784, - 64'd840, - 64'd856, - 64'd864, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = 32'h0; - 64'd88, 64'd256, 64'd688, 64'd800: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h01000000; - 64'd96, - 64'd112, - 64'd128, - 64'd208, - 64'd224, - 64'd240, - 64'd320, - 64'd432, - 64'd448, - 64'd488, - 64'd536, - 64'd736, - 64'd752, - 64'd872, - 64'd888, - 64'd904: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h03000000; - 64'd120, 64'd232, 64'd464: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0F000000; - 64'd136, 64'd328: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h1B000000; - 64'd144: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h732C7261; - 64'd152: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7261622D; - 64'd160, 64'd336: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000076; - 64'd168: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h12000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h62626375; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656B6970; - 64'd192: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000065; - 64'd200: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h73757063; - 64'd248: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C000000; - 64'd264, 64'd704, 64'd816: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000030; - 64'd272, 64'd288, 64'd392, 64'd600, 64'd616: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h04000000; - 64'd280: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00757063; - 64'd304: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h05000000; - 64'd312: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79616B6F; - 64'd344: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0A000000; - 64'd352: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h32337672; - 64'd360: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000073; - 64'd368, 64'd920: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0B000000; - 64'd376, 64'd472, 64'd720: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63736972; - 64'd384: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00003233; - 64'd400: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80969800; - 64'd408: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65746E69; - 64'd416: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F632D74; - 64'd424: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72656C6C; - 64'd440: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79000000; - 64'd456: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h8A000000; - 64'd480: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692D75; - 64'd496: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h9F000000; - 64'd504, 64'd512, 64'd584, 64'd608, 64'd624, 64'd792, 64'd928: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h02000000; - 64'd520: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6D656D; - 64'd528: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30303030; - 64'd544: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3F000000; - 64'd552: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00007972; - 64'd592: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00636F73; - 64'd632: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h21000000; - 64'd656: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F732D65; - 64'd664: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656C706D; - 64'd696: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30324074; - 64'd712: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0D000000; - 64'd728: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30746E69; - 64'd744, 64'd912: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAE000000; - 64'd760: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h07000000; - 64'd808: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30306340; - 64'd824: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h09000000; - 64'd832: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3631736E; - 64'd880: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hC2000000; - 64'd896: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h69000000; - 64'd936: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h64646123; - 64'd944: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C65632D; - 64'd952: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h657A6973; - 64'd960: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6300736C; - 64'd968: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C626974; - 64'd976: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h006C6564; - 64'd984: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65736162; - 64'd992: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E657571; - 64'd1000: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63697665; - 64'd1008: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72006570; - 64'd1016: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75746174; - 64'd1024: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C766373; - 64'd1032: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D756D6D; - 64'd1040: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6C6300; - 64'd1048: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75716572; - 64'd1056: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692300; - 64'd1064, 64'd1080: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D747075; - 64'd1072: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E690073; - 64'd1088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C6C6F72; - 64'd1096: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h646E6168; - 64'd1104: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65676E61; - 64'd1112: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72726574; - 64'd1120: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7478652D; - 64'd1128: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65720064; - 64'd1136: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00746669; - default: CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705 or - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 or - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2) - begin - case (byte_addr__h705) - 64'd0: data64__h987 = 64'h0202859300000297; - 64'd8: data64__h987 = 64'h0182A283F1402573; - default: data64__h987 = - { CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_module_ready$EN) - rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_module_ready = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - begin - v__h808 = $stime; - #0; - end - v__h802 = v__h808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", - v__h802); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - begin - v__h8928 = $stime; - #0; - end - v__h8922 = v__h8928 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", - v__h8922); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h9221 = $stime; - #0; - end - v__h9215 = v__h9221 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9215, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h9331 = $stime; - #0; - end - v__h9325 = v__h9331 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9325, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkBoot_ROM - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCPU.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCPU.v deleted file mode 100644 index 5a9b71bb..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCPU.v +++ /dev/null @@ -1,7043 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// hart0_server_reset_response_get O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_set_verbosity O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// hart0_server_reset_request_put I 1 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// nmi_req_set_not_clear I 1 -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// EN_hart0_server_reset_request_put I 1 -// EN_set_verbosity I 1 -// EN_hart0_server_reset_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// imem_master_arready, -// dmem_master_awready, -// dmem_master_wready) -> imem_master_rready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready, -// dmem_master_arready) -> dmem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCPU(CLK, - RST_N, - - hart0_server_reset_request_put, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - nmi_req_set_not_clear, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity); - input CLK; - input RST_N; - - // action method hart0_server_reset_request_put - input hart0_server_reset_request_put; - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // actionvalue method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, - RDY_set_verbosity, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - hart0_server_reset_response_get, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid; - - // register cfg_logdelay - reg [63 : 0] cfg_logdelay; - wire [63 : 0] cfg_logdelay$D_IN; - wire cfg_logdelay$EN; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register imem_rg_f3 - reg [2 : 0] imem_rg_f3; - wire [2 : 0] imem_rg_f3$D_IN; - wire imem_rg_f3$EN; - - // register imem_rg_instr_15_0 - reg [15 : 0] imem_rg_instr_15_0; - wire [15 : 0] imem_rg_instr_15_0$D_IN; - wire imem_rg_instr_15_0$EN; - - // register imem_rg_mstatus_MXR - reg imem_rg_mstatus_MXR; - wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN; - - // register imem_rg_pc - reg [31 : 0] imem_rg_pc; - reg [31 : 0] imem_rg_pc$D_IN; - wire imem_rg_pc$EN; - - // register imem_rg_priv - reg [1 : 0] imem_rg_priv; - wire [1 : 0] imem_rg_priv$D_IN; - wire imem_rg_priv$EN; - - // register imem_rg_satp - reg [31 : 0] imem_rg_satp; - wire [31 : 0] imem_rg_satp$D_IN; - wire imem_rg_satp$EN; - - // register imem_rg_sstatus_SUM - reg imem_rg_sstatus_SUM; - wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN; - - // register imem_rg_tval - reg [31 : 0] imem_rg_tval; - reg [31 : 0] imem_rg_tval$D_IN; - wire imem_rg_tval$EN; - - // register rg_cur_priv - reg [1 : 0] rg_cur_priv; - reg [1 : 0] rg_cur_priv$D_IN; - wire rg_cur_priv$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_next_pc - reg [31 : 0] rg_next_pc; - reg [31 : 0] rg_next_pc$D_IN; - wire rg_next_pc$EN; - - // register rg_run_on_reset - reg rg_run_on_reset; - wire rg_run_on_reset$D_IN, rg_run_on_reset$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_start_CPI_cycles - reg [63 : 0] rg_start_CPI_cycles; - wire [63 : 0] rg_start_CPI_cycles$D_IN; - wire rg_start_CPI_cycles$EN; - - // register rg_start_CPI_instrs - reg [63 : 0] rg_start_CPI_instrs; - wire [63 : 0] rg_start_CPI_instrs$D_IN; - wire rg_start_CPI_instrs$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register stage1_rg_full - reg stage1_rg_full; - reg stage1_rg_full$D_IN; - wire stage1_rg_full$EN; - - // register stage2_rg_full - reg stage2_rg_full; - reg stage2_rg_full$D_IN; - wire stage2_rg_full$EN; - - // register stage2_rg_resetting - reg stage2_rg_resetting; - wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN; - - // register stage2_rg_stage2 - reg [301 : 0] stage2_rg_stage2; - wire [301 : 0] stage2_rg_stage2$D_IN; - wire stage2_rg_stage2$EN; - - // register stage3_rg_full - reg stage3_rg_full; - reg stage3_rg_full$D_IN; - wire stage3_rg_full$EN; - - // register stage3_rg_stage3 - reg [142 : 0] stage3_rg_stage3; - wire [142 : 0] stage3_rg_stage3$D_IN; - wire stage3_rg_stage3$EN; - - // ports of submodule csr_regfile - reg [31 : 0] csr_regfile$csr_trap_actions_xtval; - reg [3 : 0] csr_regfile$csr_trap_actions_exc_code; - reg [1 : 0] csr_regfile$csr_ret_actions_from_priv; - wire [97 : 0] csr_regfile$csr_trap_actions; - wire [65 : 0] csr_regfile$csr_ret_actions; - wire [63 : 0] csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret; - wire [32 : 0] csr_regfile$read_csr; - wire [31 : 0] csr_regfile$csr_trap_actions_pc, - csr_regfile$mav_csr_write_word, - csr_regfile$read_mstatus, - csr_regfile$read_satp, - csr_regfile$read_sstatus; - wire [27 : 0] csr_regfile$read_misa; - wire [11 : 0] csr_regfile$access_permitted_1_csr_addr, - csr_regfile$access_permitted_2_csr_addr, - csr_regfile$csr_counter_read_fault_csr_addr, - csr_regfile$mav_csr_write_csr_addr, - csr_regfile$mav_read_csr_csr_addr, - csr_regfile$read_csr_csr_addr, - csr_regfile$read_csr_port2_csr_addr; - wire [4 : 0] csr_regfile$interrupt_pending, - csr_regfile$ma_update_fcsr_fflags_flags; - wire [2 : 0] csr_regfile$read_frm; - wire [1 : 0] csr_regfile$access_permitted_1_priv, - csr_regfile$access_permitted_2_priv, - csr_regfile$csr_counter_read_fault_priv, - csr_regfile$csr_trap_actions_from_priv, - csr_regfile$interrupt_pending_cur_priv, - csr_regfile$ma_update_mstatus_fs_fs; - wire csr_regfile$EN_csr_minstret_incr, - csr_regfile$EN_csr_ret_actions, - csr_regfile$EN_csr_trap_actions, - csr_regfile$EN_debug, - csr_regfile$EN_ma_update_fcsr_fflags, - csr_regfile$EN_ma_update_mstatus_fs, - csr_regfile$EN_mav_csr_write, - csr_regfile$EN_mav_read_csr, - csr_regfile$EN_server_reset_request_put, - csr_regfile$EN_server_reset_response_get, - csr_regfile$RDY_server_reset_request_put, - csr_regfile$RDY_server_reset_response_get, - csr_regfile$access_permitted_1, - csr_regfile$access_permitted_1_read_not_write, - csr_regfile$access_permitted_2, - csr_regfile$access_permitted_2_read_not_write, - csr_regfile$csr_trap_actions_interrupt, - csr_regfile$csr_trap_actions_nmi, - csr_regfile$m_external_interrupt_req_set_not_clear, - csr_regfile$nmi_pending, - csr_regfile$nmi_req_set_not_clear, - csr_regfile$s_external_interrupt_req_set_not_clear, - csr_regfile$software_interrupt_req_set_not_clear, - csr_regfile$timer_interrupt_req_set_not_clear, - csr_regfile$wfi_resume; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fpr_regfile - wire [63 : 0] fpr_regfile$read_rs1, - fpr_regfile$read_rs2, - fpr_regfile$read_rs3, - fpr_regfile$write_rd_rd_val; - wire [4 : 0] fpr_regfile$read_rs1_port2_rs1, - fpr_regfile$read_rs1_rs1, - fpr_regfile$read_rs2_rs2, - fpr_regfile$read_rs3_rs3, - fpr_regfile$write_rd_rd; - wire fpr_regfile$EN_server_reset_request_put, - fpr_regfile$EN_server_reset_response_get, - fpr_regfile$EN_write_rd, - fpr_regfile$RDY_server_reset_request_put, - fpr_regfile$RDY_server_reset_response_get; - - // ports of submodule gpr_regfile - wire [31 : 0] gpr_regfile$read_rs1, - gpr_regfile$read_rs2, - gpr_regfile$write_rd_rd_val; - wire [4 : 0] gpr_regfile$read_rs1_port2_rs1, - gpr_regfile$read_rs1_rs1, - gpr_regfile$read_rs2_rs2, - gpr_regfile$write_rd_rd; - wire gpr_regfile$EN_server_reset_request_put, - gpr_regfile$EN_server_reset_response_get, - gpr_regfile$EN_write_rd, - gpr_regfile$RDY_server_reset_request_put, - gpr_regfile$RDY_server_reset_response_get; - - // ports of submodule near_mem - reg [31 : 0] near_mem$imem_req_addr; - reg [1 : 0] near_mem$dmem_req_op; - reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM; - wire [63 : 0] near_mem$dmem_master_araddr, - near_mem$dmem_master_awaddr, - near_mem$dmem_master_rdata, - near_mem$dmem_master_wdata, - near_mem$dmem_req_store_value, - near_mem$dmem_word64, - near_mem$imem_master_araddr, - near_mem$imem_master_awaddr, - near_mem$imem_master_rdata, - near_mem$imem_master_wdata; - wire [31 : 0] near_mem$dmem_req_addr, - near_mem$dmem_req_satp, - near_mem$imem_instr, - near_mem$imem_pc, - near_mem$imem_req_satp; - wire [7 : 0] near_mem$dmem_master_arlen, - near_mem$dmem_master_awlen, - near_mem$dmem_master_wstrb, - near_mem$imem_master_arlen, - near_mem$imem_master_awlen, - near_mem$imem_master_wstrb, - near_mem$server_fence_request_put; - wire [6 : 0] near_mem$dmem_req_amo_funct7; - wire [3 : 0] near_mem$dmem_exc_code, - near_mem$dmem_master_arcache, - near_mem$dmem_master_arid, - near_mem$dmem_master_arqos, - near_mem$dmem_master_arregion, - near_mem$dmem_master_awcache, - near_mem$dmem_master_awid, - near_mem$dmem_master_awqos, - near_mem$dmem_master_awregion, - near_mem$dmem_master_bid, - near_mem$dmem_master_rid, - near_mem$dmem_master_wid, - near_mem$imem_exc_code, - near_mem$imem_master_arcache, - near_mem$imem_master_arid, - near_mem$imem_master_arqos, - near_mem$imem_master_arregion, - near_mem$imem_master_awcache, - near_mem$imem_master_awid, - near_mem$imem_master_awqos, - near_mem$imem_master_awregion, - near_mem$imem_master_bid, - near_mem$imem_master_rid, - near_mem$imem_master_wid; - wire [2 : 0] near_mem$dmem_master_arprot, - near_mem$dmem_master_arsize, - near_mem$dmem_master_awprot, - near_mem$dmem_master_awsize, - near_mem$dmem_req_f3, - near_mem$imem_master_arprot, - near_mem$imem_master_arsize, - near_mem$imem_master_awprot, - near_mem$imem_master_awsize, - near_mem$imem_req_f3; - wire [1 : 0] near_mem$dmem_master_arburst, - near_mem$dmem_master_awburst, - near_mem$dmem_master_bresp, - near_mem$dmem_master_rresp, - near_mem$dmem_req_priv, - near_mem$imem_master_arburst, - near_mem$imem_master_awburst, - near_mem$imem_master_bresp, - near_mem$imem_master_rresp, - near_mem$imem_req_priv; - wire near_mem$EN_dmem_req, - near_mem$EN_imem_req, - near_mem$EN_server_fence_i_request_put, - near_mem$EN_server_fence_i_response_get, - near_mem$EN_server_fence_request_put, - near_mem$EN_server_fence_response_get, - near_mem$EN_server_reset_request_put, - near_mem$EN_server_reset_response_get, - near_mem$EN_sfence_vma, - near_mem$RDY_server_fence_i_request_put, - near_mem$RDY_server_fence_i_response_get, - near_mem$RDY_server_fence_request_put, - near_mem$RDY_server_fence_response_get, - near_mem$RDY_server_reset_request_put, - near_mem$RDY_server_reset_response_get, - near_mem$dmem_exc, - near_mem$dmem_master_arlock, - near_mem$dmem_master_arready, - near_mem$dmem_master_arvalid, - near_mem$dmem_master_awlock, - near_mem$dmem_master_awready, - near_mem$dmem_master_awvalid, - near_mem$dmem_master_bready, - near_mem$dmem_master_bvalid, - near_mem$dmem_master_rlast, - near_mem$dmem_master_rready, - near_mem$dmem_master_rvalid, - near_mem$dmem_master_wlast, - near_mem$dmem_master_wready, - near_mem$dmem_master_wvalid, - near_mem$dmem_req_mstatus_MXR, - near_mem$dmem_req_sstatus_SUM, - near_mem$dmem_valid, - near_mem$imem_exc, - near_mem$imem_is_i32_not_i16, - near_mem$imem_master_arlock, - near_mem$imem_master_arready, - near_mem$imem_master_arvalid, - near_mem$imem_master_awlock, - near_mem$imem_master_awready, - near_mem$imem_master_awvalid, - near_mem$imem_master_bready, - near_mem$imem_master_bvalid, - near_mem$imem_master_rlast, - near_mem$imem_master_rready, - near_mem$imem_master_rvalid, - near_mem$imem_master_wlast, - near_mem$imem_master_wready, - near_mem$imem_master_wvalid, - near_mem$imem_valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_pc_reset_value; - - // ports of submodule stage1_f_reset_reqs - wire stage1_f_reset_reqs$CLR, - stage1_f_reset_reqs$DEQ, - stage1_f_reset_reqs$EMPTY_N, - stage1_f_reset_reqs$ENQ, - stage1_f_reset_reqs$FULL_N; - - // ports of submodule stage1_f_reset_rsps - wire stage1_f_reset_rsps$CLR, - stage1_f_reset_rsps$DEQ, - stage1_f_reset_rsps$EMPTY_N, - stage1_f_reset_rsps$ENQ, - stage1_f_reset_rsps$FULL_N; - - // ports of submodule stage2_f_reset_reqs - wire stage2_f_reset_reqs$CLR, - stage2_f_reset_reqs$DEQ, - stage2_f_reset_reqs$EMPTY_N, - stage2_f_reset_reqs$ENQ, - stage2_f_reset_reqs$FULL_N; - - // ports of submodule stage2_f_reset_rsps - wire stage2_f_reset_rsps$CLR, - stage2_f_reset_rsps$DEQ, - stage2_f_reset_rsps$EMPTY_N, - stage2_f_reset_rsps$ENQ, - stage2_f_reset_rsps$FULL_N; - - // ports of submodule stage2_fbox - wire [63 : 0] stage2_fbox$req_v1, - stage2_fbox$req_v2, - stage2_fbox$req_v3, - stage2_fbox$word_fst; - wire [6 : 0] stage2_fbox$req_f7, stage2_fbox$req_opcode; - wire [4 : 0] stage2_fbox$req_rs2, stage2_fbox$word_snd; - wire [2 : 0] stage2_fbox$req_rm; - wire stage2_fbox$EN_req, - stage2_fbox$EN_server_reset_request_put, - stage2_fbox$EN_server_reset_response_get, - stage2_fbox$RDY_server_reset_request_put, - stage2_fbox$RDY_server_reset_response_get, - stage2_fbox$valid; - - // ports of submodule stage2_mbox - wire [31 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word; - wire [3 : 0] stage2_mbox$set_verbosity_verbosity; - wire [2 : 0] stage2_mbox$req_f3; - wire stage2_mbox$EN_req, - stage2_mbox$EN_req_reset, - stage2_mbox$EN_rsp_reset, - stage2_mbox$EN_set_verbosity, - stage2_mbox$req_is_OP_not_OP_32, - stage2_mbox$valid; - - // ports of submodule stage3_f_reset_reqs - wire stage3_f_reset_reqs$CLR, - stage3_f_reset_reqs$DEQ, - stage3_f_reset_reqs$EMPTY_N, - stage3_f_reset_reqs$ENQ, - stage3_f_reset_reqs$FULL_N; - - // ports of submodule stage3_f_reset_rsps - wire stage3_f_reset_rsps$CLR, - stage3_f_reset_rsps$DEQ, - stage3_f_reset_rsps$EMPTY_N, - stage3_f_reset_rsps$ENQ, - stage3_f_reset_rsps$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_imem_rl_assert_fail, - CAN_FIRE_RL_imem_rl_fetch_next_32b, - CAN_FIRE_RL_rl_WFI_resume, - CAN_FIRE_RL_rl_finish_FENCE, - CAN_FIRE_RL_rl_finish_FENCE_I, - CAN_FIRE_RL_rl_finish_SFENCE_VMA, - CAN_FIRE_RL_rl_pipe, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_RL_rl_reset_from_WFI, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_show_pipe, - CAN_FIRE_RL_rl_stage1_CSRR_S_or_C, - CAN_FIRE_RL_rl_stage1_CSRR_W, - CAN_FIRE_RL_rl_stage1_FENCE, - CAN_FIRE_RL_rl_stage1_FENCE_I, - CAN_FIRE_RL_rl_stage1_SFENCE_VMA, - CAN_FIRE_RL_rl_stage1_WFI, - CAN_FIRE_RL_rl_stage1_interrupt, - CAN_FIRE_RL_rl_stage1_restart_after_csrrx, - CAN_FIRE_RL_rl_stage1_trap, - CAN_FIRE_RL_rl_stage1_xRET, - CAN_FIRE_RL_rl_stage2_nonpipe, - CAN_FIRE_RL_rl_trap_fetch, - CAN_FIRE_RL_stage1_rl_reset, - CAN_FIRE_RL_stage2_rl_reset_begin, - CAN_FIRE_RL_stage2_rl_reset_end, - CAN_FIRE_RL_stage3_rl_reset, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_set_verbosity, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_imem_rl_assert_fail, - WILL_FIRE_RL_imem_rl_fetch_next_32b, - WILL_FIRE_RL_rl_WFI_resume, - WILL_FIRE_RL_rl_finish_FENCE, - WILL_FIRE_RL_rl_finish_FENCE_I, - WILL_FIRE_RL_rl_finish_SFENCE_VMA, - WILL_FIRE_RL_rl_pipe, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_RL_rl_reset_from_WFI, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_show_pipe, - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C, - WILL_FIRE_RL_rl_stage1_CSRR_W, - WILL_FIRE_RL_rl_stage1_FENCE, - WILL_FIRE_RL_rl_stage1_FENCE_I, - WILL_FIRE_RL_rl_stage1_SFENCE_VMA, - WILL_FIRE_RL_rl_stage1_WFI, - WILL_FIRE_RL_rl_stage1_interrupt, - WILL_FIRE_RL_rl_stage1_restart_after_csrrx, - WILL_FIRE_RL_rl_stage1_trap, - WILL_FIRE_RL_rl_stage1_xRET, - WILL_FIRE_RL_rl_stage2_nonpipe, - WILL_FIRE_RL_rl_trap_fetch, - WILL_FIRE_RL_stage1_rl_reset, - WILL_FIRE_RL_stage2_rl_reset_begin, - WILL_FIRE_RL_stage2_rl_reset_end, - WILL_FIRE_RL_stage3_rl_reset, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_set_verbosity, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - reg [31 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2; - wire [31 : 0] MUX_near_mem$imem_req_2__VAL_1, - MUX_near_mem$imem_req_2__VAL_2, - MUX_near_mem$imem_req_2__VAL_5; - wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1, - MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_3; - wire MUX_csr_regfile$mav_csr_write_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_2, - MUX_gpr_regfile$write_rd_1__SEL_3, - MUX_imem_rg_f3$write_1__SEL_1, - MUX_imem_rg_f3$write_1__SEL_2, - MUX_imem_rg_mstatus_MXR$write_1__SEL_4, - MUX_imem_rg_pc$write_1__SEL_4, - MUX_near_mem$imem_req_1__SEL_6, - MUX_rg_cur_priv$write_1__SEL_1, - MUX_rg_mstatus_MXR$write_1__SEL_1, - MUX_rg_next_pc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_11, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_4, - MUX_rg_state$write_1__SEL_6, - MUX_rg_state$write_1__SEL_7, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9, - MUX_stage1_rg_full$write_1__VAL_2, - MUX_stage2_rg_full$write_1__VAL_2; - - // remaining internal signals - reg [63 : 0] CASE_theResult__604_BITS_6_TO_0_0b100011_alu_o_ETC__q20, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411, - x_out_data_to_stage2_val1__h13749, - x_out_data_to_stage3_rd_val__h6243, - x_out_fbypass_rd_val__h6870; - reg [31 : 0] CASE_theResult__604_BITS_6_TO_0_0b1100111_data_ETC__q19, - _theResult_____1_fst__h15237, - rs1_val__h22055, - value__h6422, - value__h6483, - x_out_bypass_rd_val__h6718, - x_out_data_to_stage2_addr__h13748; - reg [4 : 0] x_out_bypass_rd__h6717, - x_out_data_to_stage2_rd__h13747, - x_out_data_to_stage3_fpr_flags__h6242, - x_out_data_to_stage3_rd__h6239, - x_out_fbypass_rd__h6869; - reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q13, - CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15, - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16, - CASE_theResult__604_BITS_31_TO_20_0b0_CASE_rg__ETC__q14, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1152, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1176, - alu_outputs_exc_code__h14690, - x_out_trap_info_exc_code__h6459; - reg [2 : 0] CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260; - reg [1 : 0] CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1, - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2, - CASE_stage2_rg_stage2_BITS_235_TO_233_1_IF_NOT_ETC__q3; - reg CASE_theResult__604_BITS_6_TO_0_0b1000011_NOT__ETC__q7, - CASE_theResult__604_BITS_6_TO_0_0b1000011_theR_ETC__q10, - CASE_theResult__604_BITS_6_TO_0_0b10011_IF_NOT_ETC__q12, - CASE_theResult__604_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9, - CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8, - CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946, - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150, - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160, - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195, - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d230; - wire [127 : 0] csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d1854; - wire [63 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1412, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1432, - _theResult_____1_snd_fst_rd_val__h6855, - _theResult_____2_snd_rd_val__h6852, - _theResult____h26769, - _theResult___snd_rd_val__h6861, - alu_outputs___1_val1__h13900, - alu_outputs___1_val1__h14035, - alu_outputs___1_val1__h14076, - alu_outputs___1_val1__h14095, - alu_outputs___1_val1__h14114, - alu_outputs___1_val1__h14465, - alu_outputs___1_val1__h14489, - alu_outputs___1_val1__h14666, - alu_outputs___1_val1__h15021, - alu_outputs___1_val2__h13877, - alu_outputs___1_val2__h14180, - alu_outputs___1_val2__h15022, - cpi__h26771, - cpifrac__h26772, - data_to_stage3_rd_val__h6137, - delta_CPI_cycles__h26767, - delta_CPI_instrs___1__h26804, - delta_CPI_instrs__h26768, - frs1_val_bypassed__h4623, - frs2_val_bypassed__h4628, - output_stage2___1_data_to_stage3_rd_val__h6211, - rd_val__h17575, - rd_val__h17628, - rd_val__h17686, - x__h26770, - x_out_data_to_stage2_val2__h13750, - x_out_data_to_stage2_val3__h13751; - wire [31 : 0] IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1317, - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1801, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d570, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d571, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d572, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d573, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d574, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d576, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d578, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d579, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d580, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d582, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d583, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d584, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d586, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d587, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d588, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d596, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d598, - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1326, - _theResult_____1_fst__h15230, - _theResult_____1_fst__h15265, - _theResult_____1_fst_rd_val__h6696, - _theResult_____2_fst_rd_val__h6693, - _theResult____h14024, - _theResult____h4604, - _theResult___fst__h7192, - _theResult___fst__h7220, - _theResult___fst_rd_val__h6707, - _theResult___snd__h17391, - alu_outputs___1_addr__h13875, - alu_outputs___1_addr__h13899, - alu_outputs___1_addr__h13928, - alu_outputs___1_addr__h14154, - alu_outputs___1_addr__h14178, - branch_target__h13854, - data_to_stage2_addr__h13737, - fall_through_pc__h13698, - instr___1__h7017, - instr__h10372, - instr__h10544, - instr__h10717, - instr__h10910, - instr__h11103, - instr__h11220, - instr__h11398, - instr__h11517, - instr__h11612, - instr__h11748, - instr__h11884, - instr__h12020, - instr__h12358, - instr__h12461, - instr__h12606, - instr__h12798, - instr__h12993, - instr__h13466, - instr__h4602, - instr__h7292, - instr__h7437, - instr__h7629, - instr__h7824, - instr__h8053, - instr__h8396, - instr__h8786, - instr__h8902, - instr__h8967, - instr__h9284, - instr__h9622, - instr__h9806, - instr__h9935, - instr_out___1__h7162, - instr_out___1__h7194, - instr_out___1__h7222, - next_pc___1__h16893, - next_pc__h16891, - rd_val___1__h15218, - rd_val___1__h15226, - rd_val___1__h15233, - rd_val___1__h15240, - rd_val___1__h15247, - rd_val___1__h15254, - rd_val__h13631, - rd_val__h13674, - rd_val__h14066, - rd_val__h14086, - rd_val__h14105, - rd_val__h17285, - rd_val__h17337, - rd_val__h17359, - rs1_val__h14431, - rs1_val__h21562, - rs1_val_bypassed__h4612, - rs2_val__h13850, - trap_info_tval__h16726, - val__h13633, - val__h13676, - value__h16781, - x_out_data_to_stage2_instr__h13745, - x_out_next_pc__h13711, - y__h22359; - wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400, - theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q4; - wire [19 : 0] imm20__h9674; - wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429, - theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q5; - wire [11 : 0] imm12__h10170, - imm12__h10385, - imm12__h10581, - imm12__h10926, - imm12__h7293, - imm12__h7630, - imm12__h9546, - offset__h8000, - theResult__604_BITS_31_TO_20__q18, - theResult__604_BITS_31_TO_25_CONCAT_theResult__ETC__q6; - wire [9 : 0] nzimm10__h10168, nzimm10__h10383; - wire [8 : 0] offset__h8911; - wire [7 : 0] offset__h7063; - wire [6 : 0] offset__h7572; - wire [5 : 0] imm6__h9544; - wire [4 : 0] offset_BITS_4_TO_0___h13591, - offset_BITS_4_TO_0___h7561, - offset_BITS_4_TO_0___h7992, - rd__h7632, - rs1__h7631, - shamt__h14020; - wire [3 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1112, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1116, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1154, - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1108, - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1162, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178, - IF_rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7__ETC___d1150, - alu_outputs___1_exc_code__h14461, - cur_verbosity__h3131, - x_out_trap_info_exc_code__h16729; - wire [2 : 0] rm__h14593, x_out_data_to_stage2_rounding_mode__h13753; - wire [1 : 0] IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d256, - IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d284, - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289, - IF_near_mem_dmem_valid__22_AND_NOT_near_mem_dm_ETC___d254, - IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125, - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129, - IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127, - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134, - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263; - wire IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1095, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1602, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1127, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d971, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1851, - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602, - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604, - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d702, - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1676, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1744, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1746, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1749, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1763, - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1084, - NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1244, - NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1290, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1612, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1623, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1631, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607, - _0_OR_0_OR_near_mem_imem_exc__23_OR_IF_IF_NOT_n_ETC___d1742, - csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1605, - csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1610, - csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1616, - csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d414, - csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d420, - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d926, - fpr_regfile_RDY_server_reset_request_put__548__ETC___d1560, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1457, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1460, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1463, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1466, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1469, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1472, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1475, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1478, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1481, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1484, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1487, - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1490, - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d614, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d616, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1601, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954, - rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7_EQ__ETC___d1148, - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766, - rg_state_6_EQ_3_618_AND_stage3_rg_full_2_OR_NO_ETC___d1637, - stage2_f_reset_rsps_i_notEmpty__571_AND_stage3_ETC___d1580, - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d647, - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d655; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // actionvalue method hart0_server_reset_response_get - assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ; - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = near_mem$imem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = near_mem$imem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = near_mem$imem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = near_mem$imem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = near_mem$imem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = near_mem$imem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = near_mem$imem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = near_mem$imem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = near_mem$imem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = near_mem$imem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = near_mem$imem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = near_mem$imem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = near_mem$imem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = near_mem$imem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = near_mem$imem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = near_mem$imem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = near_mem$imem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = near_mem$imem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = near_mem$imem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = near_mem$imem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = near_mem$imem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = near_mem$imem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = near_mem$imem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = near_mem$imem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = near_mem$imem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = near_mem$imem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = near_mem$imem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = near_mem$imem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = near_mem$imem_master_rready ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = near_mem$dmem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = near_mem$dmem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = near_mem$dmem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = near_mem$dmem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = near_mem$dmem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = near_mem$dmem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = near_mem$dmem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = near_mem$dmem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = near_mem$dmem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = near_mem$dmem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = near_mem$dmem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = near_mem$dmem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = near_mem$dmem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = near_mem$dmem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = near_mem$dmem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = near_mem$dmem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = near_mem$dmem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = near_mem$dmem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = near_mem$dmem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = near_mem$dmem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = near_mem$dmem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = near_mem$dmem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = near_mem$dmem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = near_mem$dmem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = near_mem$dmem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = near_mem$dmem_master_rready ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // submodule csr_regfile - mkCSR_RegFile csr_regfile(.CLK(CLK), - .RST_N(RST_N), - .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr), - .access_permitted_1_priv(csr_regfile$access_permitted_1_priv), - .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write), - .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr), - .access_permitted_2_priv(csr_regfile$access_permitted_2_priv), - .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write), - .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr), - .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv), - .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv), - .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code), - .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv), - .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt), - .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi), - .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc), - .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval), - .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv), - .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear), - .ma_update_fcsr_fflags_flags(csr_regfile$ma_update_fcsr_fflags_flags), - .ma_update_mstatus_fs_fs(csr_regfile$ma_update_mstatus_fs_fs), - .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr), - .mav_csr_write_word(csr_regfile$mav_csr_write_word), - .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr), - .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear), - .read_csr_csr_addr(csr_regfile$read_csr_csr_addr), - .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr), - .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear), - .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear), - .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get), - .EN_mav_read_csr(csr_regfile$EN_mav_read_csr), - .EN_mav_csr_write(csr_regfile$EN_mav_csr_write), - .EN_ma_update_fcsr_fflags(csr_regfile$EN_ma_update_fcsr_fflags), - .EN_ma_update_mstatus_fs(csr_regfile$EN_ma_update_mstatus_fs), - .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions), - .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions), - .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr), - .EN_debug(csr_regfile$EN_debug), - .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get), - .read_csr(csr_regfile$read_csr), - .read_csr_port2(), - .mav_read_csr(), - .mav_csr_write(), - .read_frm(csr_regfile$read_frm), - .read_misa(csr_regfile$read_misa), - .read_mstatus(csr_regfile$read_mstatus), - .read_sstatus(csr_regfile$read_sstatus), - .read_ustatus(), - .read_satp(csr_regfile$read_satp), - .csr_trap_actions(csr_regfile$csr_trap_actions), - .RDY_csr_trap_actions(), - .csr_ret_actions(csr_regfile$csr_ret_actions), - .RDY_csr_ret_actions(), - .read_csr_minstret(csr_regfile$read_csr_minstret), - .read_csr_mcycle(csr_regfile$read_csr_mcycle), - .read_csr_mtime(), - .access_permitted_1(csr_regfile$access_permitted_1), - .access_permitted_2(csr_regfile$access_permitted_2), - .csr_counter_read_fault(), - .csr_mip_read(), - .interrupt_pending(csr_regfile$interrupt_pending), - .wfi_resume(csr_regfile$wfi_resume), - .nmi_pending(csr_regfile$nmi_pending), - .RDY_debug()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fpr_regfile - mkFPR_RegFile fpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(fpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(fpr_regfile$read_rs1_rs1), - .read_rs2_rs2(fpr_regfile$read_rs2_rs2), - .read_rs3_rs3(fpr_regfile$read_rs3_rs3), - .write_rd_rd(fpr_regfile$write_rd_rd), - .write_rd_rd_val(fpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(fpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(fpr_regfile$EN_server_reset_response_get), - .EN_write_rd(fpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(fpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fpr_regfile$RDY_server_reset_response_get), - .read_rs1(fpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(fpr_regfile$read_rs2), - .read_rs3(fpr_regfile$read_rs3)); - - // submodule gpr_regfile - mkGPR_RegFile gpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(gpr_regfile$read_rs1_rs1), - .read_rs2_rs2(gpr_regfile$read_rs2_rs2), - .write_rd_rd(gpr_regfile$write_rd_rd), - .write_rd_rd_val(gpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get), - .EN_write_rd(gpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get), - .read_rs1(gpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(gpr_regfile$read_rs2)); - - // submodule near_mem - mkNear_Mem near_mem(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(near_mem$dmem_master_arready), - .dmem_master_awready(near_mem$dmem_master_awready), - .dmem_master_bid(near_mem$dmem_master_bid), - .dmem_master_bresp(near_mem$dmem_master_bresp), - .dmem_master_bvalid(near_mem$dmem_master_bvalid), - .dmem_master_rdata(near_mem$dmem_master_rdata), - .dmem_master_rid(near_mem$dmem_master_rid), - .dmem_master_rlast(near_mem$dmem_master_rlast), - .dmem_master_rresp(near_mem$dmem_master_rresp), - .dmem_master_rvalid(near_mem$dmem_master_rvalid), - .dmem_master_wready(near_mem$dmem_master_wready), - .dmem_req_addr(near_mem$dmem_req_addr), - .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7), - .dmem_req_f3(near_mem$dmem_req_f3), - .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR), - .dmem_req_op(near_mem$dmem_req_op), - .dmem_req_priv(near_mem$dmem_req_priv), - .dmem_req_satp(near_mem$dmem_req_satp), - .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM), - .dmem_req_store_value(near_mem$dmem_req_store_value), - .imem_master_arready(near_mem$imem_master_arready), - .imem_master_awready(near_mem$imem_master_awready), - .imem_master_bid(near_mem$imem_master_bid), - .imem_master_bresp(near_mem$imem_master_bresp), - .imem_master_bvalid(near_mem$imem_master_bvalid), - .imem_master_rdata(near_mem$imem_master_rdata), - .imem_master_rid(near_mem$imem_master_rid), - .imem_master_rlast(near_mem$imem_master_rlast), - .imem_master_rresp(near_mem$imem_master_rresp), - .imem_master_rvalid(near_mem$imem_master_rvalid), - .imem_master_wready(near_mem$imem_master_wready), - .imem_req_addr(near_mem$imem_req_addr), - .imem_req_f3(near_mem$imem_req_f3), - .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR), - .imem_req_priv(near_mem$imem_req_priv), - .imem_req_satp(near_mem$imem_req_satp), - .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM), - .server_fence_request_put(near_mem$server_fence_request_put), - .EN_server_reset_request_put(near_mem$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem$EN_server_reset_response_get), - .EN_imem_req(near_mem$EN_imem_req), - .EN_dmem_req(near_mem$EN_dmem_req), - .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put), - .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get), - .EN_server_fence_request_put(near_mem$EN_server_fence_request_put), - .EN_server_fence_response_get(near_mem$EN_server_fence_response_get), - .EN_sfence_vma(near_mem$EN_sfence_vma), - .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get), - .imem_valid(near_mem$imem_valid), - .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16), - .imem_pc(near_mem$imem_pc), - .imem_instr(near_mem$imem_instr), - .imem_exc(near_mem$imem_exc), - .imem_exc_code(near_mem$imem_exc_code), - .imem_tval(), - .imem_master_awvalid(near_mem$imem_master_awvalid), - .imem_master_awid(near_mem$imem_master_awid), - .imem_master_awaddr(near_mem$imem_master_awaddr), - .imem_master_awlen(near_mem$imem_master_awlen), - .imem_master_awsize(near_mem$imem_master_awsize), - .imem_master_awburst(near_mem$imem_master_awburst), - .imem_master_awlock(near_mem$imem_master_awlock), - .imem_master_awcache(near_mem$imem_master_awcache), - .imem_master_awprot(near_mem$imem_master_awprot), - .imem_master_awqos(near_mem$imem_master_awqos), - .imem_master_awregion(near_mem$imem_master_awregion), - .imem_master_wvalid(near_mem$imem_master_wvalid), - .imem_master_wid(near_mem$imem_master_wid), - .imem_master_wdata(near_mem$imem_master_wdata), - .imem_master_wstrb(near_mem$imem_master_wstrb), - .imem_master_wlast(near_mem$imem_master_wlast), - .imem_master_bready(near_mem$imem_master_bready), - .imem_master_arvalid(near_mem$imem_master_arvalid), - .imem_master_arid(near_mem$imem_master_arid), - .imem_master_araddr(near_mem$imem_master_araddr), - .imem_master_arlen(near_mem$imem_master_arlen), - .imem_master_arsize(near_mem$imem_master_arsize), - .imem_master_arburst(near_mem$imem_master_arburst), - .imem_master_arlock(near_mem$imem_master_arlock), - .imem_master_arcache(near_mem$imem_master_arcache), - .imem_master_arprot(near_mem$imem_master_arprot), - .imem_master_arqos(near_mem$imem_master_arqos), - .imem_master_arregion(near_mem$imem_master_arregion), - .imem_master_rready(near_mem$imem_master_rready), - .dmem_valid(near_mem$dmem_valid), - .dmem_word64(near_mem$dmem_word64), - .dmem_st_amo_val(), - .dmem_exc(near_mem$dmem_exc), - .dmem_exc_code(near_mem$dmem_exc_code), - .dmem_master_awvalid(near_mem$dmem_master_awvalid), - .dmem_master_awid(near_mem$dmem_master_awid), - .dmem_master_awaddr(near_mem$dmem_master_awaddr), - .dmem_master_awlen(near_mem$dmem_master_awlen), - .dmem_master_awsize(near_mem$dmem_master_awsize), - .dmem_master_awburst(near_mem$dmem_master_awburst), - .dmem_master_awlock(near_mem$dmem_master_awlock), - .dmem_master_awcache(near_mem$dmem_master_awcache), - .dmem_master_awprot(near_mem$dmem_master_awprot), - .dmem_master_awqos(near_mem$dmem_master_awqos), - .dmem_master_awregion(near_mem$dmem_master_awregion), - .dmem_master_wvalid(near_mem$dmem_master_wvalid), - .dmem_master_wid(near_mem$dmem_master_wid), - .dmem_master_wdata(near_mem$dmem_master_wdata), - .dmem_master_wstrb(near_mem$dmem_master_wstrb), - .dmem_master_wlast(near_mem$dmem_master_wlast), - .dmem_master_bready(near_mem$dmem_master_bready), - .dmem_master_arvalid(near_mem$dmem_master_arvalid), - .dmem_master_arid(near_mem$dmem_master_arid), - .dmem_master_araddr(near_mem$dmem_master_araddr), - .dmem_master_arlen(near_mem$dmem_master_arlen), - .dmem_master_arsize(near_mem$dmem_master_arsize), - .dmem_master_arburst(near_mem$dmem_master_arburst), - .dmem_master_arlock(near_mem$dmem_master_arlock), - .dmem_master_arcache(near_mem$dmem_master_arcache), - .dmem_master_arprot(near_mem$dmem_master_arprot), - .dmem_master_arqos(near_mem$dmem_master_arqos), - .dmem_master_arregion(near_mem$dmem_master_arregion), - .dmem_master_rready(near_mem$dmem_master_rready), - .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put), - .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get), - .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put), - .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get), - .RDY_sfence_vma()); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(soc_map$m_pc_reset_value), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule stage1_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_reqs$ENQ), - .DEQ(stage1_f_reset_reqs$DEQ), - .CLR(stage1_f_reset_reqs$CLR), - .FULL_N(stage1_f_reset_reqs$FULL_N), - .EMPTY_N(stage1_f_reset_reqs$EMPTY_N)); - - // submodule stage1_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_rsps$ENQ), - .DEQ(stage1_f_reset_rsps$DEQ), - .CLR(stage1_f_reset_rsps$CLR), - .FULL_N(stage1_f_reset_rsps$FULL_N), - .EMPTY_N(stage1_f_reset_rsps$EMPTY_N)); - - // submodule stage2_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_reqs$ENQ), - .DEQ(stage2_f_reset_reqs$DEQ), - .CLR(stage2_f_reset_reqs$CLR), - .FULL_N(stage2_f_reset_reqs$FULL_N), - .EMPTY_N(stage2_f_reset_reqs$EMPTY_N)); - - // submodule stage2_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_rsps$ENQ), - .DEQ(stage2_f_reset_rsps$DEQ), - .CLR(stage2_f_reset_rsps$CLR), - .FULL_N(stage2_f_reset_rsps$FULL_N), - .EMPTY_N(stage2_f_reset_rsps$EMPTY_N)); - - // submodule stage2_fbox - mkFBox_Top stage2_fbox(.CLK(CLK), - .RST_N(RST_N), - .req_f7(stage2_fbox$req_f7), - .req_opcode(stage2_fbox$req_opcode), - .req_rm(stage2_fbox$req_rm), - .req_rs2(stage2_fbox$req_rs2), - .req_v1(stage2_fbox$req_v1), - .req_v2(stage2_fbox$req_v2), - .req_v3(stage2_fbox$req_v3), - .EN_server_reset_request_put(stage2_fbox$EN_server_reset_request_put), - .EN_server_reset_response_get(stage2_fbox$EN_server_reset_response_get), - .EN_req(stage2_fbox$EN_req), - .RDY_server_reset_request_put(stage2_fbox$RDY_server_reset_request_put), - .RDY_server_reset_response_get(stage2_fbox$RDY_server_reset_response_get), - .valid(stage2_fbox$valid), - .word_fst(stage2_fbox$word_fst), - .word_snd(stage2_fbox$word_snd)); - - // submodule stage2_mbox - mkRISCV_MBox stage2_mbox(.CLK(CLK), - .RST_N(RST_N), - .req_f3(stage2_mbox$req_f3), - .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32), - .req_v1(stage2_mbox$req_v1), - .req_v2(stage2_mbox$req_v2), - .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity), - .EN_set_verbosity(stage2_mbox$EN_set_verbosity), - .EN_req_reset(stage2_mbox$EN_req_reset), - .EN_rsp_reset(stage2_mbox$EN_rsp_reset), - .EN_req(stage2_mbox$EN_req), - .RDY_set_verbosity(), - .RDY_req_reset(), - .RDY_rsp_reset(), - .valid(stage2_mbox$valid), - .word(stage2_mbox$word)); - - // submodule stage3_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_reqs$ENQ), - .DEQ(stage3_f_reset_reqs$DEQ), - .CLR(stage3_f_reset_reqs$CLR), - .FULL_N(stage3_f_reset_reqs$FULL_N), - .EMPTY_N(stage3_f_reset_reqs$EMPTY_N)); - - // submodule stage3_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_rsps$ENQ), - .DEQ(stage3_f_reset_rsps$DEQ), - .CLR(stage3_f_reset_rsps$CLR), - .FULL_N(stage3_f_reset_rsps$FULL_N), - .EMPTY_N(stage3_f_reset_rsps$EMPTY_N)); - - // rule RL_rl_show_pipe - assign CAN_FIRE_RL_rl_show_pipe = - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - rg_state != 4'd0 && - rg_state != 4'd1 && - rg_state != 4'd10 ; - assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ; - - // rule RL_rl_stage2_nonpipe - assign CAN_FIRE_RL_rl_stage2_nonpipe = - rg_state == 4'd3 && !stage3_rg_full && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd3 && - (!stage1_rg_full || - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622) ; - assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ; - - // rule RL_rl_stage1_CSRR_W - assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_stage1_CSRR_S_or_C - assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_stage1_restart_after_csrrx - assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx = - CAN_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // rule RL_rl_stage1_xRET - assign CAN_FIRE_RL_rl_stage1_xRET = - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd7 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd8 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd9) ; - assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ; - - // rule RL_rl_stage1_FENCE_I - assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - - // rule RL_rl_finish_FENCE_I - assign CAN_FIRE_RL_rl_finish_FENCE_I = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_i_response_get && - rg_state == 4'd7 ; - assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ; - - // rule RL_rl_stage1_FENCE - assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - - // rule RL_rl_finish_FENCE - assign CAN_FIRE_RL_rl_finish_FENCE = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_response_get && - rg_state == 4'd8 ; - assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ; - - // rule RL_rl_finish_SFENCE_VMA - assign CAN_FIRE_RL_rl_finish_SFENCE_VMA = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_finish_SFENCE_VMA = - CAN_FIRE_RL_rl_finish_SFENCE_VMA ; - - // rule RL_rl_stage1_WFI - assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - - // rule RL_rl_WFI_resume - assign CAN_FIRE_RL_rl_WFI_resume = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd10 && - csr_regfile$wfi_resume ; - assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ; - - // rule RL_rl_reset_from_WFI - assign CAN_FIRE_RL_rl_reset_from_WFI = - rg_state == 4'd10 && f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_4 ; - - // rule RL_rl_stage1_trap - assign CAN_FIRE_RL_rl_stage1_trap = - rg_state == 4'd4 || - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd11 ; - assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ; - - // rule RL_rl_trap_fetch - assign CAN_FIRE_RL_rl_trap_fetch = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd5 ; - assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; - - // rule RL_rl_stage1_interrupt - assign CAN_FIRE_RL_rl_stage1_interrupt = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - rg_state == 4'd3 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1602 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd0 && - !stage3_rg_full ; - assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ; - - // rule RL_imem_rl_assert_fail - assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ; - assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = - gpr_regfile$RDY_server_reset_response_get && - fpr_regfile$RDY_server_reset_response_get && - near_mem$RDY_server_reset_response_get && - csr_regfile$RDY_server_reset_response_get && - stage1_f_reset_rsps$EMPTY_N && - stage2_f_reset_rsps_i_notEmpty__571_AND_stage3_ETC___d1580 && - rg_state == 4'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_pipe - assign CAN_FIRE_RL_rl_pipe = - (csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1616 || - !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state_6_EQ_3_618_AND_stage3_rg_full_2_OR_NO_ETC___d1637 ; - assign WILL_FIRE_RL_rl_pipe = - CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_rl_stage1_SFENCE_VMA - assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = - gpr_regfile$RDY_server_reset_request_put && - fpr_regfile_RDY_server_reset_request_put__548__ETC___d1560 && - rg_state == 4'd0 ; - assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ; - - // rule RL_imem_rl_fetch_next_32b - assign CAN_FIRE_RL_imem_rl_fetch_next_32b = - near_mem$imem_valid && - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] == 2'b11 ; - assign WILL_FIRE_RL_imem_rl_fetch_next_32b = - CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_stage3_rl_reset - assign CAN_FIRE_RL_stage3_rl_reset = - stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ; - - // rule RL_stage2_rl_reset_end - assign CAN_FIRE_RL_stage2_rl_reset_end = - stage2_fbox$RDY_server_reset_response_get && - stage2_f_reset_rsps$FULL_N && - stage2_rg_resetting ; - assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ; - - // rule RL_stage2_rl_reset_begin - assign CAN_FIRE_RL_stage2_rl_reset_begin = - stage2_fbox$RDY_server_reset_request_put && - stage2_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_stage2_rl_reset_begin = - CAN_FIRE_RL_stage2_rl_reset_begin ; - - // rule RL_stage1_rl_reset - assign CAN_FIRE_RL_stage1_rl_reset = - stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_csr_regfile$mav_csr_write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 ; - assign MUX_gpr_regfile$write_rd_1__SEL_2 = - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - assign MUX_gpr_regfile$write_rd_1__SEL_3 = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - !stage3_rg_stage3[69] ; - assign MUX_imem_rg_f3$write_1__SEL_1 = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ; - assign MUX_imem_rg_f3$write_1__SEL_2 = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 ; - assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_imem_rg_pc$write_1__SEL_4 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_near_mem$imem_req_1__SEL_6 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_rg_cur_priv$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_mstatus_MXR$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_next_pc$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign MUX_rg_state$write_1__SEL_1 = - CAN_FIRE_RL_rl_reset_complete && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_2 = - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd2 ; - assign MUX_rg_state$write_1__SEL_3 = - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd3 ; - assign MUX_rg_state$write_1__SEL_4 = - CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ; - assign MUX_rg_state$write_1__SEL_6 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_rg_state$write_1__SEL_7 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_state$write_1__SEL_8 = - near_mem$RDY_server_fence_i_request_put && - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd5 ; - assign MUX_rg_state$write_1__SEL_9 = - near_mem$RDY_server_fence_request_put && - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd4 ; - assign MUX_rg_state$write_1__SEL_10 = - CAN_FIRE_RL_rl_stage1_SFENCE_VMA && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_11 = - rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd10 ; - assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 = - (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ? - csr_regfile$interrupt_pending[3:0] : - 4'd0 ; - always@(x_out_data_to_stage2_instr__h13745 or - csr_regfile$read_csr or - y__h22359 or - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1801) - begin - case (x_out_data_to_stage2_instr__h13745[14:12]) - 3'b010, 3'b110: - MUX_csr_regfile$mav_csr_write_2__VAL_2 = - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1801; - default: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - csr_regfile$read_csr[31:0] & y__h22359; - endcase - end - assign MUX_near_mem$imem_req_2__VAL_1 = - { soc_map$m_pc_reset_value[31:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_2 = - { x_out_next_pc__h13711[31:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[31:2], 2'b0 } ; - assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd3 : 4'd2 ; - assign MUX_rg_state$write_1__VAL_2 = - csr_regfile$access_permitted_1 ? 4'd6 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_3 = - csr_regfile$access_permitted_2 ? 4'd6 : 4'd4 ; - assign MUX_stage1_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1749 || - (csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1610 || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1631) && - stage1_rg_full ; - assign MUX_stage2_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1744 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd2 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd0 ; - - // register cfg_logdelay - assign cfg_logdelay$D_IN = set_verbosity_logdelay ; - assign cfg_logdelay$EN = EN_set_verbosity ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register imem_rg_f3 - assign imem_rg_f3$D_IN = 3'b010 ; - assign imem_rg_f3$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_instr_15_0 - assign imem_rg_instr_15_0$D_IN = near_mem$imem_instr[31:16] ; - assign imem_rg_instr_15_0$EN = CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // register imem_rg_mstatus_MXR - assign imem_rg_mstatus_MXR$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_mstatus[19] : - rg_mstatus_MXR ; - assign imem_rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_pc - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h13711 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0]; - MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h13711; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_pc$D_IN = x_out_next_pc__h13711; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc; - default: imem_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_pc$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - - // register imem_rg_priv - assign imem_rg_priv$D_IN = rg_cur_priv ; - assign imem_rg_priv$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_satp - assign imem_rg_satp$D_IN = csr_regfile$read_satp ; - assign imem_rg_satp$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_sstatus_SUM - assign imem_rg_sstatus_SUM$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_sstatus[18] : - rg_sstatus_SUM ; - assign imem_rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_tval - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h13711 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or - rg_next_pc or - WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h16893) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_tval$D_IN = soc_map$m_pc_reset_value[31:0]; - MUX_imem_rg_f3$write_1__SEL_2: - imem_rg_tval$D_IN = x_out_next_pc__h13711; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_tval$D_IN = x_out_next_pc__h13711; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - imem_rg_tval$D_IN = next_pc___1__h16893; - default: imem_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_tval$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // register rg_cur_priv - always@(MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or - csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_cur_priv$write_1__SEL_1: - rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[33:32]; - WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11; - default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_cur_priv$EN = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_mstatus[19] : - csr_regfile$csr_trap_actions[53] ; - assign rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_next_pc - always@(MUX_rg_next_pc$write_1__SEL_1 or - x_out_next_pc__h13711 or - MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h13711; - MUX_rg_cur_priv$write_1__SEL_1: - rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34]; - default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_next_pc$EN = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET ; - - // register rg_run_on_reset - assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ; - assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_sstatus[18] : - csr_regfile$csr_trap_actions[52] ; - assign rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_start_CPI_cycles - assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ; - assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_start_CPI_instrs - assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ; - assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_state - always@(WILL_FIRE_RL_rl_reset_complete or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_stage1_CSRR_W or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or - MUX_rg_state$write_1__VAL_3 or - WILL_FIRE_RL_rl_reset_from_WFI or - WILL_FIRE_RL_rl_reset_start or - MUX_rg_state$write_1__SEL_6 or - MUX_rg_state$write_1__SEL_7 or - WILL_FIRE_RL_rl_stage1_FENCE_I or - WILL_FIRE_RL_rl_stage1_FENCE or - WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_reset_complete: - rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_stage1_CSRR_W: - rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: - rg_state$D_IN = MUX_rg_state$write_1__VAL_3; - WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1; - MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd5; - WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd7; - WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd8; - WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd10; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_complete || - WILL_FIRE_RL_rl_stage1_CSRR_W || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C || - WILL_FIRE_RL_rl_reset_from_WFI || - WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_WFI ; - - // register stage1_rg_full - always@(WILL_FIRE_RL_stage1_rl_reset or - WILL_FIRE_RL_rl_pipe or - MUX_stage1_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or - WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_trap_fetch or - WILL_FIRE_RL_rl_stage1_trap or - WILL_FIRE_RL_rl_WFI_resume or - WILL_FIRE_RL_rl_finish_SFENCE_VMA or - WILL_FIRE_RL_rl_finish_FENCE or - WILL_FIRE_RL_rl_finish_FENCE_I or - WILL_FIRE_RL_rl_stage1_xRET or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_interrupt: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_trap_fetch: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_trap: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I: - stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_xRET: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0; - default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage1_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage1_rl_reset || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register stage2_rg_full - always@(WILL_FIRE_RL_stage2_rl_reset_begin or - WILL_FIRE_RL_rl_pipe or - MUX_stage2_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage2_rl_reset_begin: stage2_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage2_nonpipe: - stage2_rg_full$D_IN = 1'd0; - default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage2_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage2_rl_reset_begin ; - - // register stage2_rg_resetting - assign stage2_rg_resetting$D_IN = WILL_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_rg_resetting$EN = - WILL_FIRE_RL_stage2_rl_reset_end || - WILL_FIRE_RL_stage2_rl_reset_begin ; - - // register stage2_rg_stage2 - assign stage2_rg_stage2$D_IN = - { rg_cur_priv, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260, - x_out_data_to_stage2_rd__h13747, - x_out_data_to_stage2_addr__h13748, - x_out_data_to_stage2_val1__h13749, - x_out_data_to_stage2_val2__h13750, - x_out_data_to_stage2_val3__h13751, - _theResult____h4604[6:0] == 7'b0000111 || - (_theResult____h4604[6:0] == 7'b1010011 || - _theResult____h4604[6:0] == 7'b1000011 || - _theResult____h4604[6:0] == 7'b1000111 || - _theResult____h4604[6:0] == 7'b1001011 || - _theResult____h4604[6:0] == 7'b1001111) && - (_theResult____h4604[31:25] != 7'h61 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h61 || - _theResult____h4604[24:20] != 5'd1) && - _theResult____h4604[31:25] != 7'h71 && - _theResult____h4604[31:25] != 7'h51 && - (_theResult____h4604[31:25] != 7'h60 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h60 || - _theResult____h4604[24:20] != 5'd1) && - _theResult____h4604[31:25] != 7'h70 && - _theResult____h4604[31:25] != 7'h50, - x_out_data_to_stage2_rounding_mode__h13753 } ; - assign stage2_rg_stage2$EN = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 ; - - // register stage3_rg_full - always@(WILL_FIRE_RL_stage3_rl_reset or - WILL_FIRE_RL_rl_pipe or - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 or - MUX_imem_rg_f3$write_1__SEL_1) - case (1'b1) - WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage3_rg_full$D_IN = - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2; - MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0; - default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage3_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_stage3_rl_reset ; - - // register stage3_rg_stage3 - assign stage3_rg_stage3$D_IN = - { stage2_rg_stage2[299:236], - stage2_rg_stage2[301:300], - stage2_rg_stage2[235:233] == 3'd0 || - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160, - x_out_data_to_stage3_rd__h6239, - stage2_rg_stage2[235:233] != 3'd0 && - stage2_rg_stage2[235:233] != 3'd1 && - stage2_rg_stage2[235:233] != 3'd4 && - stage2_rg_stage2[235:233] != 3'd2 && - stage2_rg_stage2[235:233] != 3'd3, - stage2_rg_stage2[235:233] != 3'd0 && - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195, - x_out_data_to_stage3_fpr_flags__h6242, - x_out_data_to_stage3_rd_val__h6243 } ; - assign stage3_rg_stage3$EN = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd2 ; - - // submodule csr_regfile - assign csr_regfile$access_permitted_1_csr_addr = - x_out_data_to_stage2_instr__h13745[31:20] ; - assign csr_regfile$access_permitted_1_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ; - assign csr_regfile$access_permitted_2_csr_addr = - x_out_data_to_stage2_instr__h13745[31:20] ; - assign csr_regfile$access_permitted_2_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_2_read_not_write = - rs1_val__h22055 == 32'd0 ; - assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ; - assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ; - always@(IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178) - begin - case (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178) - 4'd7: csr_regfile$csr_ret_actions_from_priv = 2'b11; - 4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b01; - default: csr_regfile$csr_ret_actions_from_priv = 2'b0; - endcase - end - always@(WILL_FIRE_RL_rl_stage1_interrupt or - MUX_csr_regfile$csr_trap_actions_5__VAL_1 or - WILL_FIRE_RL_rl_stage1_trap or - x_out_trap_info_exc_code__h16729 or - WILL_FIRE_RL_rl_stage2_nonpipe or x_out_trap_info_exc_code__h6459) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_exc_code = - MUX_csr_regfile$csr_trap_actions_5__VAL_1; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h16729; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h6459; - default: csr_regfile$csr_trap_actions_exc_code = - 4'b1010 /* unspecified value */ ; - endcase - end - assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ; - assign csr_regfile$csr_trap_actions_interrupt = - WILL_FIRE_RL_rl_stage1_interrupt && !csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_nmi = - WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_pc = - (WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap) ? - imem_rg_pc : - value__h6422 ; - always@(WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_stage1_trap or - value__h16781 or WILL_FIRE_RL_rl_stage2_nonpipe or value__h6483) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_xtval = 32'd0; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_xtval = value__h16781; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_xtval = value__h6483; - default: csr_regfile$csr_trap_actions_xtval = - 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ; - assign csr_regfile$m_external_interrupt_req_set_not_clear = - m_external_interrupt_req_set_not_clear ; - assign csr_regfile$ma_update_fcsr_fflags_flags = stage3_rg_stage3[68:64] ; - assign csr_regfile$ma_update_mstatus_fs_fs = 2'h3 ; - assign csr_regfile$mav_csr_write_csr_addr = - x_out_data_to_stage2_instr__h13745[31:20] ; - assign csr_regfile$mav_csr_write_word = - MUX_csr_regfile$mav_csr_write_1__SEL_1 ? - rs1_val__h21562 : - MUX_csr_regfile$mav_csr_write_2__VAL_2 ; - assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ; - assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign csr_regfile$read_csr_csr_addr = - x_out_data_to_stage2_instr__h13745[31:20] ; - assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ; - assign csr_regfile$s_external_interrupt_req_set_not_clear = - s_external_interrupt_req_set_not_clear ; - assign csr_regfile$software_interrupt_req_set_not_clear = - software_interrupt_req_set_not_clear ; - assign csr_regfile$timer_interrupt_req_set_not_clear = - timer_interrupt_req_set_not_clear ; - assign csr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign csr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign csr_regfile$EN_mav_read_csr = 1'b0 ; - assign csr_regfile$EN_mav_csr_write = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h13745[19:15] != 5'd0 ; - assign csr_regfile$EN_ma_update_fcsr_fflags = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - stage3_rg_stage3[70] ; - assign csr_regfile$EN_ma_update_mstatus_fs = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - (stage3_rg_stage3[70] || stage3_rg_stage3[69]) ; - assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_1 ; - assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ; - assign csr_regfile$EN_csr_minstret_incr = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd2 || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_stage1_WFI || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign csr_regfile$EN_debug = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = hart0_server_reset_request_put ; - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = - gpr_regfile$RDY_server_reset_request_put && - fpr_regfile_RDY_server_reset_request_put__548__ETC___d1560 && - rg_state == 4'd0 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = rg_run_on_reset ; - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fpr_regfile - assign fpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign fpr_regfile$read_rs1_rs1 = _theResult____h4604[19:15] ; - assign fpr_regfile$read_rs2_rs2 = _theResult____h4604[24:20] ; - assign fpr_regfile$read_rs3_rs3 = _theResult____h4604[31:27] ; - assign fpr_regfile$write_rd_rd = stage3_rg_stage3[75:71] ; - assign fpr_regfile$write_rd_rd_val = stage3_rg_stage3[63:0] ; - assign fpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign fpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign fpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - stage3_rg_stage3[69] ; - - // submodule gpr_regfile - assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign gpr_regfile$read_rs1_rs1 = _theResult____h4604[19:15] ; - assign gpr_regfile$read_rs2_rs2 = _theResult____h4604[24:20] ; - assign gpr_regfile$write_rd_rd = - MUX_gpr_regfile$write_rd_1__SEL_3 ? - stage3_rg_stage3[75:71] : - x_out_data_to_stage2_instr__h13745[11:7] ; - assign gpr_regfile$write_rd_rd_val = - (MUX_csr_regfile$mav_csr_write_1__SEL_1 || - MUX_gpr_regfile$write_rd_1__SEL_2) ? - csr_regfile$read_csr[31:0] : - stage3_rg_stage3[31:0] ; - assign gpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign gpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign gpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - !stage3_rg_stage3[69] ; - - // submodule near_mem - assign near_mem$dmem_master_arready = dmem_master_arready ; - assign near_mem$dmem_master_awready = dmem_master_awready ; - assign near_mem$dmem_master_bid = dmem_master_bid ; - assign near_mem$dmem_master_bresp = dmem_master_bresp ; - assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; - assign near_mem$dmem_master_rdata = dmem_master_rdata ; - assign near_mem$dmem_master_rid = dmem_master_rid ; - assign near_mem$dmem_master_rlast = dmem_master_rlast ; - assign near_mem$dmem_master_rresp = dmem_master_rresp ; - assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; - assign near_mem$dmem_master_wready = dmem_master_wready ; - assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h13748 ; - assign near_mem$dmem_req_amo_funct7 = - x_out_data_to_stage2_val1__h13749[6:0] ; - assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h13745[14:12] ; - assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ; - always@(IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260) - begin - case (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260) - 3'd1: near_mem$dmem_req_op = 2'd0; - 3'd2: near_mem$dmem_req_op = 2'd1; - default: near_mem$dmem_req_op = 2'd2; - endcase - end - assign near_mem$dmem_req_priv = - csr_regfile$read_mstatus[17] ? - csr_regfile$read_mstatus[12:11] : - rg_cur_priv ; - assign near_mem$dmem_req_satp = csr_regfile$read_satp ; - assign near_mem$dmem_req_sstatus_SUM = csr_regfile$read_sstatus[18] ; - assign near_mem$dmem_req_store_value = x_out_data_to_stage2_val2__h13750 ; - assign near_mem$imem_master_arready = imem_master_arready ; - assign near_mem$imem_master_awready = imem_master_awready ; - assign near_mem$imem_master_bid = imem_master_bid ; - assign near_mem$imem_master_bresp = imem_master_bresp ; - assign near_mem$imem_master_bvalid = imem_master_bvalid ; - assign near_mem$imem_master_rdata = imem_master_rdata ; - assign near_mem$imem_master_rid = imem_master_rid ; - assign near_mem$imem_master_rlast = imem_master_rlast ; - assign near_mem$imem_master_rresp = imem_master_rresp ; - assign near_mem$imem_master_rvalid = imem_master_rvalid ; - assign near_mem$imem_master_wready = imem_master_wready ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_near_mem$imem_req_2__VAL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - MUX_near_mem$imem_req_2__VAL_2 or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - next_pc___1__h16893 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_trap_fetch or - MUX_near_mem$imem_req_2__VAL_5 or MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1; - MUX_imem_rg_f3$write_1__SEL_2: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_addr = next_pc___1__h16893; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - default: near_mem$imem_req_addr = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_f3 = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_mstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_mstatus_MXR or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_mstatus_MXR) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_mstatus_MXR = imem_rg_mstatus_MXR; - default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_priv = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - MUX_near_mem$imem_req_1__SEL_6) ? - rg_cur_priv : - imem_rg_priv ; - assign near_mem$imem_req_satp = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? - imem_rg_satp : - csr_regfile$read_satp ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_sstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_sstatus_SUM or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_sstatus_SUM) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_sstatus_SUM = csr_regfile$read_sstatus[18]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_sstatus_SUM = imem_rg_sstatus_SUM; - default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$server_fence_request_put = - 8'b10101010 /* unspecified value */ ; - assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ; - assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ; - assign near_mem$EN_imem_req = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 || - WILL_FIRE_RL_imem_rl_fetch_next_32b || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_dmem_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 && - (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == - 3'd1 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == - 3'd2 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == - 3'd4) ; - assign near_mem$EN_server_fence_i_request_put = - MUX_rg_state$write_1__SEL_8 ; - assign near_mem$EN_server_fence_i_response_get = - CAN_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_9 ; - assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ; - assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_10 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule stage1_f_reset_reqs - assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage1_f_reset_rsps - assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage1_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_f_reset_reqs - assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage2_f_reset_reqs$DEQ = CAN_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage2_f_reset_rsps - assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage2_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_fbox - assign stage2_fbox$req_f7 = x_out_data_to_stage2_instr__h13745[31:25] ; - assign stage2_fbox$req_opcode = x_out_data_to_stage2_instr__h13745[6:0] ; - assign stage2_fbox$req_rm = x_out_data_to_stage2_rounding_mode__h13753 ; - assign stage2_fbox$req_rs2 = x_out_data_to_stage2_instr__h13745[24:20] ; - assign stage2_fbox$req_v1 = x_out_data_to_stage2_val1__h13749 ; - assign stage2_fbox$req_v2 = x_out_data_to_stage2_val2__h13750 ; - assign stage2_fbox$req_v3 = x_out_data_to_stage2_val3__h13751 ; - assign stage2_fbox$EN_server_reset_request_put = - CAN_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_fbox$EN_server_reset_response_get = - CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_fbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == - 3'd5 ; - - // submodule stage2_mbox - assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h13745[14:12] ; - assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4604[3] ; - assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h13749[31:0] ; - assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h13750[31:0] ; - assign stage2_mbox$set_verbosity_verbosity = 4'h0 ; - assign stage2_mbox$EN_set_verbosity = 1'b0 ; - assign stage2_mbox$EN_req_reset = 1'b0 ; - assign stage2_mbox$EN_rsp_reset = 1'b0 ; - assign stage2_mbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == - 3'd3 ; - - // submodule stage3_f_reset_reqs - assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage3_f_reset_rsps - assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage3_f_reset_rsps$CLR = 1'b0 ; - - // remaining internal signals - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1095 = - ((_theResult____h4604[6:0] == 7'b0010011 || - _theResult____h4604[6:0] == 7'b0110011) && - (_theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101)) ? - !_theResult____h4604[25] : - CASE_theResult__604_BITS_6_TO_0_0b10011_IF_NOT_ETC__q12 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 = - (_theResult____h4604[6:0] == 7'b1100011) ? - (_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b110 || - _theResult____h4604[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 : - _theResult____h4604[6:0] != 7'b1101111 && - _theResult____h4604[6:0] != 7'b1100111 && - (_theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[31:25] == 7'b0000001 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1095) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100 = - (_theResult____h4604[6:0] == 7'b1100011) ? - (_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b110 || - _theResult____h4604[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 : - _theResult____h4604[6:0] == 7'b1101111 || - _theResult____h4604[6:0] == 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1112 = - ((_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011) && - (_theResult____h4604[6:0] != 7'b0000111 || - csr_regfile$read_mstatus[14:13] != 2'h0)) ? - 4'd0 : - 4'd11 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1116 = - ((_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011) && - (_theResult____h4604[6:0] != 7'b0100111 || - csr_regfile$read_mstatus[14:13] != 2'h0)) ? - 4'd0 : - 4'd11 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1154 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1127 ? - 4'd6 : - ((_theResult____h4604[11:7] == 5'd0 && - _theResult____h4604[19:15] == 5'd0) ? - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1152 : - 4'd11) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1412 = - ((_theResult____h4604[6:0] == 7'b0010011 || - _theResult____h4604[6:0] == 7'b0110011) && - (_theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101)) ? - alu_outputs___1_val1__h14035 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1432 = - (_theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[31:25] == 7'b0000001) ? - alu_outputs___1_val2__h15022 : - CASE_theResult__604_BITS_6_TO_0_0b100011_alu_o_ETC__q20 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1602 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661 = - rs1_val_bypassed__h4612 == rs2_val__h13850 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663 = - (rs1_val_bypassed__h4612 ^ 32'h80000000) < - (rs2_val__h13850 ^ 32'h80000000) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665 = - rs1_val_bypassed__h4612 < rs2_val__h13850 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937 = - ((_theResult____h4604[6:0] == 7'b0010011 || - _theResult____h4604[6:0] == 7'b0110011) && - (_theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101)) ? - _theResult____h4604[25] : - CASE_theResult__604_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 = - (_theResult____h4604[6:0] == 7'b1100011) ? - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b110 && - _theResult____h4604[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 : - _theResult____h4604[6:0] == 7'b1101111 || - _theResult____h4604[6:0] == 7'b1100111 || - (_theResult____h4604[6:0] != 7'b0110011 || - _theResult____h4604[31:25] != 7'b0000001) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951 = - (_theResult____h4604[6:0] == 7'b1100011) ? - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b110 && - _theResult____h4604[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 : - _theResult____h4604[6:0] != 7'b1101111 && - _theResult____h4604[6:0] != 7'b1100111 ; - assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1108 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d702 ? - 4'd11 : - 4'd0 ; - assign IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1162 = - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1084 ? - 4'd0 : - 4'd11 ; - assign IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d256 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - ((stage2_rg_stage2[3] || stage2_rg_stage2[232:228] == 5'd0) ? - 2'd0 : - IF_near_mem_dmem_valid__22_AND_NOT_near_mem_dm_ETC___d254) : - 2'd0 ; - assign IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d284 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - (stage2_rg_stage2[3] ? - IF_near_mem_dmem_valid__22_AND_NOT_near_mem_dm_ETC___d254 : - 2'd0) : - 2'd0 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1127 = - _theResult____h4604[11:7] == 5'd0 && - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) && - _theResult____h4604[31:25] == 7'b0001001 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1317 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 ? - next_pc___1__h16893 : - next_pc__h16891 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d971 = - _theResult____h4604[14:12] == 3'b0 && - (_theResult____h4604[6:0] != 7'b0110011 || - !_theResult____h4604[30]) || - _theResult____h4604[14:12] == 3'b0 && - _theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[30] || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b110 || - _theResult____h4604[14:12] == 3'b111 ; - assign IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 = - near_mem$imem_exc ? - 4'd11 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1176 ; - assign IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1851 = - imem_rg_pc == csr_regfile$csr_trap_actions[97:66] ; - assign IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 = - (!stage2_rg_full || stage2_rg_stage2[235:233] == 3'd0) ? - 2'd0 : - CASE_stage2_rg_stage2_BITS_235_TO_233_1_IF_NOT_ETC__q3 ; - assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1801 = - csr_regfile$read_csr[31:0] | rs1_val__h22055 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d570 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b111) ? - instr__h12993 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b101) ? - instr__h13466 : - 32'h0) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d571 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b011) ? - instr__h12798 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d570 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d572 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:13] == 3'b111) ? - instr__h12606 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d571 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d573 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[11:7] != 5'd0 && - instr__h4602[15:13] == 3'b011 && - csr_regfile$read_misa[5]) ? - instr__h12461 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d572 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d574 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:12] == 4'b1001 && - instr__h4602[11:7] == 5'd0 && - instr__h4602[6:2] == 5'd0) ? - instr__h12358 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d573 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d576 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:10] == 6'b100011 && - instr__h4602[6:5] == 2'b01) ? - instr__h11884 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:10] == 6'b100011 && - instr__h4602[6:5] == 2'b0) ? - instr__h12020 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d574) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d578 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:10] == 6'b100011 && - instr__h4602[6:5] == 2'b11) ? - instr__h11612 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:10] == 6'b100011 && - instr__h4602[6:5] == 2'b10) ? - instr__h11748 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d576) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d579 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d420 && - instr__h4602[6:2] != 5'd0) ? - instr__h11517 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d578 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d580 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d414 && - instr__h4602[6:2] != 5'd0) ? - instr__h11398 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d579 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d582 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b100 && - instr__h4602[11:10] == 2'b01 && - imm6__h9544 != 6'd0 && - !instr__h4602[12]) ? - instr__h11103 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b100 && - instr__h4602[11:10] == 2'b10) ? - instr__h11220 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d580) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d583 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b100 && - instr__h4602[11:10] == 2'b0 && - imm6__h9544 != 6'd0 && - !instr__h4602[12]) ? - instr__h10910 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d582 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d584 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:13] == 3'b0 && - instr__h4602[11:7] != 5'd0 && - imm6__h9544 != 6'd0 && - !instr__h4602[12]) ? - instr__h10717 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d583 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d586 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b011 && - instr__h4602[11:7] == 5'd2 && - nzimm10__h10168 != 10'd0) ? - instr__h10372 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b0 && - nzimm10__h10383 != 10'd0) ? - instr__h10544 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d584) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d587 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b0 && - instr__h4602[11:7] != 5'd0 && - imm6__h9544 != 6'd0 || - csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b0 && - instr__h4602[11:7] == 5'd0 && - imm6__h9544 == 6'd0) ? - instr__h9935 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d586 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d588 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b011 && - instr__h4602[11:7] != 5'd0 && - instr__h4602[11:7] != 5'd2 && - imm6__h9544 != 6'd0) ? - instr__h9806 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d587 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b111) ? - instr__h9284 : - ((csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b010 && - instr__h4602[11:7] != 5'd0) ? - instr__h9622 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d588) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b110) ? - instr__h8967 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d420 && - instr__h4602[6:2] == 5'd0) ? - instr__h8902 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d414 && - instr__h4602[6:2] == 5'd0) ? - instr__h8786 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b001) ? - instr__h8396 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b01 && - instr__h4602[15:13] == 3'b101) ? - instr__h8053 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d596 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b110) ? - instr__h7824 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b0 && - instr__h4602[15:13] == 3'b010) ? - instr__h7629 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d596 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d598 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:13] == 3'b110) ? - instr__h7437 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597 ; - assign IF_near_mem_dmem_valid__22_AND_NOT_near_mem_dm_ETC___d254 = - (near_mem$dmem_valid && !near_mem$dmem_exc) ? 2'd2 : 2'd1 ; - assign IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125 = - near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ; - assign IF_rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7__ETC___d1150 = - ((rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) && - _theResult____h4604[31:20] == 12'b000100000010) ? - 4'd8 : - (rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7_EQ__ETC___d1148 ? - 4'd10 : - 4'd11) ; - assign IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129 = - stage2_fbox$valid ? 2'd2 : 2'd1 ; - assign IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127 = - stage2_mbox$valid ? 2'd2 : 2'd1 ; - assign IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1 : - 2'd0 ; - assign IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 : - 2'd0 ; - assign IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602 = - x_out_bypass_rd__h6717 == _theResult____h4604[19:15] ; - assign IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604 = - x_out_bypass_rd__h6717 == _theResult____h4604[24:20] ; - assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d702 = - (_theResult____h4604[14:12] != 3'b0 || - _theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[30]) && - (_theResult____h4604[14:12] != 3'b0 || - _theResult____h4604[6:0] != 7'b0110011 || - !_theResult____h4604[30]) && - _theResult____h4604[14:12] != 3'b010 && - _theResult____h4604[14:12] != 3'b011 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b110 && - _theResult____h4604[14:12] != 3'b111 ; - assign NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 = - cur_verbosity__h3131 > 4'd1 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - (!stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1631) && - (!stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1623) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1676 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1676 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd2 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd0) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1676 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd2 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd0) && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103 || - !stage1_rg_full ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1744 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__23_OR_IF_IF_NOT_n_ETC___d1742) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1746 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__23_OR_IF_IF_NOT_n_ETC___d1742) && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd2 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd0) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1749 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1746 && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103 || - !stage1_rg_full) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1763 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) ; - assign NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1084 = - csr_regfile$read_mstatus[14:13] != 2'h0 && - CASE_theResult__604_BITS_6_TO_0_0b1000011_theR_ETC__q10 && - ((_theResult____h4604[14:12] == 3'b111) ? - csr_regfile$read_frm != 3'b101 && - csr_regfile$read_frm != 3'b110 && - csr_regfile$read_frm != 3'b111 : - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b110) ; - assign NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1244 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd4 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd5 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd6 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd7 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd8 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd9 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd10 ; - assign NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1290 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 != - 3'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 != - 3'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 != - 3'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 != - 3'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 != - 3'd4 ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 = - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] != 2'b11) ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] == 2'b11) && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] == 2'b11) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1612 = - !near_mem$imem_valid || - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == - 2'd1 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1623 = - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607 || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1631 = - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951 ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607 = - !near_mem$imem_valid || - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == - 2'd1 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604) ; - assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1326 = - { {20{theResult__604_BITS_31_TO_20__q18[11]}}, - theResult__604_BITS_31_TO_20__q18 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400 = - { {9{offset__h8000[11]}}, offset__h8000 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429 = - { {4{offset__h8911[8]}}, offset__h8911 } ; - assign _0_OR_0_OR_near_mem_imem_exc__23_OR_IF_IF_NOT_n_ETC___d1742 = - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951 ; - assign _theResult_____1_fst__h15230 = - (_theResult____h4604[14:12] == 3'b0 && - _theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[30]) ? - rd_val___1__h15226 : - _theResult_____1_fst__h15237 ; - assign _theResult_____1_fst__h15265 = - rs1_val_bypassed__h4612 & _theResult___snd__h17391 ; - assign _theResult_____1_fst_rd_val__h6696 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - _theResult_____2_fst_rd_val__h6693 : - stage2_rg_stage2[163:132] ; - assign _theResult_____1_snd_fst_rd_val__h6855 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - _theResult_____2_snd_rd_val__h6852 : - stage2_rg_stage2[195:132] ; - assign _theResult_____2_fst_rd_val__h6693 = - (stage2_rg_stage2[3] || stage2_rg_stage2[232:228] == 5'd0) ? - stage2_rg_stage2[163:132] : - near_mem$dmem_word64[31:0] ; - assign _theResult_____2_snd_rd_val__h6852 = - stage2_rg_stage2[3] ? - data_to_stage3_rd_val__h6137 : - stage2_rg_stage2[195:132] ; - assign _theResult____h14024 = - (_theResult____h4604[14:12] == 3'b001) ? - rd_val__h17285 : - (_theResult____h4604[30] ? rd_val__h17359 : rd_val__h17337) ; - assign _theResult____h26769 = - (delta_CPI_instrs__h26768 == 64'd0) ? - delta_CPI_instrs___1__h26804 : - delta_CPI_instrs__h26768 ; - assign _theResult____h4604 = x_out_data_to_stage2_instr__h13745 ; - assign _theResult___fst__h7192 = - (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11) ? - instr_out___1__h7194 : - _theResult___fst__h7220 ; - assign _theResult___fst__h7220 = - (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11) ? - instr_out___1__h7222 : - near_mem$imem_instr ; - assign _theResult___fst_rd_val__h6707 = - stage2_rg_stage2[3] ? - stage2_rg_stage2[163:132] : - stage2_fbox$word_fst[31:0] ; - assign _theResult___snd__h17391 = - (_theResult____h4604[6:0] == 7'b0010011) ? - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1326 : - rs2_val__h13850 ; - assign _theResult___snd_rd_val__h6861 = - stage2_rg_stage2[3] ? - stage2_fbox$word_fst : - stage2_rg_stage2[195:132] ; - assign alu_outputs___1_addr__h13875 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 ? - branch_target__h13854 : - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1317 ; - assign alu_outputs___1_addr__h13899 = - imem_rg_pc + - { {11{theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q4[20]}}, - theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q4 } ; - assign alu_outputs___1_addr__h13928 = - { alu_outputs___1_addr__h14154[31:1], 1'd0 } ; - assign alu_outputs___1_addr__h14154 = - rs1_val_bypassed__h4612 + - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1326 ; - assign alu_outputs___1_addr__h14178 = - rs1_val_bypassed__h4612 + - { {20{theResult__604_BITS_31_TO_25_CONCAT_theResult__ETC__q6[11]}}, - theResult__604_BITS_31_TO_25_CONCAT_theResult__ETC__q6 } ; - assign alu_outputs___1_exc_code__h14461 = - (_theResult____h4604[14:12] == 3'b0) ? - (IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1127 ? - 4'd2 : - ((_theResult____h4604[11:7] == 5'd0 && - _theResult____h4604[19:15] == 5'd0) ? - CASE_theResult__604_BITS_31_TO_20_0b0_CASE_rg__ETC__q14 : - 4'd2)) : - 4'd2 ; - assign alu_outputs___1_val1__h13900 = - { 32'd0, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1317 } ; - assign alu_outputs___1_val1__h14035 = { 32'd0, _theResult____h14024 } ; - assign alu_outputs___1_val1__h14076 = { 32'd0, rd_val__h14066 } ; - assign alu_outputs___1_val1__h14095 = { 32'd0, rd_val__h14086 } ; - assign alu_outputs___1_val1__h14114 = { 32'd0, rd_val__h14105 } ; - assign alu_outputs___1_val1__h14465 = { 32'd0, rs1_val__h14431 } ; - assign alu_outputs___1_val1__h14489 = - { 57'd0, _theResult____h4604[31:25] } ; - assign alu_outputs___1_val1__h14666 = - (_theResult____h4604[6:0] == 7'b1010011 && - (_theResult____h4604[31:25] == 7'h69 && - (_theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[24:20] == 5'd1) || - _theResult____h4604[31:25] == 7'h79 || - _theResult____h4604[31:25] == 7'h68 && - (_theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[24:20] == 5'd1) || - _theResult____h4604[31:25] == 7'h78)) ? - alu_outputs___1_val1__h15021 : - frs1_val_bypassed__h4623 ; - assign alu_outputs___1_val1__h15021 = { 32'd0, rs1_val_bypassed__h4612 } ; - assign alu_outputs___1_val2__h13877 = { 32'd0, branch_target__h13854 } ; - assign alu_outputs___1_val2__h14180 = - (_theResult____h4604[6:0] == 7'b0100111) ? - frs2_val_bypassed__h4628 : - alu_outputs___1_val2__h15022 ; - assign alu_outputs___1_val2__h15022 = { 32'd0, rs2_val__h13850 } ; - assign branch_target__h13854 = - imem_rg_pc + - { {19{theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q5[12]}}, - theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q5 } ; - assign cpi__h26771 = x__h26770 / 64'd10 ; - assign cpifrac__h26772 = x__h26770 % 64'd10 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1605 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1601 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1602 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1610 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd2 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd0 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1616 = - csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1605 || - (csr_regfile_interrupt_pending_rg_cur_priv_7_59_ETC___d1610 || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1612 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - stage1_rg_full ; - assign csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d1854 = - delta_CPI_cycles__h26767 * 64'd10 ; - assign csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d414 = - csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:12] == 4'b1000 && - instr__h4602[11:7] != 5'd0 ; - assign csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d420 = - csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[15:12] == 4'b1001 && - instr__h4602[11:7] != 5'd0 ; - assign csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d926 = - csr_regfile$read_mstatus[14:13] == 2'h0 || - CASE_theResult__604_BITS_6_TO_0_0b1000011_NOT__ETC__q7 || - ((_theResult____h4604[14:12] == 3'b111) ? - csr_regfile$read_frm == 3'b101 || - csr_regfile$read_frm == 3'b110 || - csr_regfile$read_frm == 3'b111 : - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b110) ; - assign cur_verbosity__h3131 = - (csr_regfile$read_csr_minstret < cfg_logdelay) ? - 4'd0 : - cfg_verbosity ; - assign data_to_stage2_addr__h13737 = x_out_data_to_stage2_addr__h13748 ; - assign data_to_stage3_rd_val__h6137 = - stage2_rg_stage2[3] ? - ((stage2_rg_stage2[250:248] == 3'b010) ? - { 32'hFFFFFFFF, near_mem$dmem_word64[31:0] } : - near_mem$dmem_word64) : - near_mem$dmem_word64 ; - assign delta_CPI_cycles__h26767 = - csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ; - assign delta_CPI_instrs___1__h26804 = delta_CPI_instrs__h26768 + 64'd1 ; - assign delta_CPI_instrs__h26768 = - csr_regfile$read_csr_minstret - rg_start_CPI_instrs ; - assign fall_through_pc__h13698 = - imem_rg_pc + - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d614 ? - 32'd4 : - 32'd2) ; - assign fpr_regfile_RDY_server_reset_request_put__548__ETC___d1560 = - fpr_regfile$RDY_server_reset_request_put && - near_mem$RDY_server_reset_request_put && - csr_regfile$RDY_server_reset_request_put && - f_reset_reqs$EMPTY_N && - stage1_f_reset_reqs$FULL_N && - stage2_f_reset_reqs$FULL_N && - stage3_f_reset_reqs$FULL_N ; - assign frs1_val_bypassed__h4623 = - (IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6869 == _theResult____h4604[19:15]) ? - x_out_fbypass_rd_val__h6870 : - rd_val__h17575 ; - assign frs2_val_bypassed__h4628 = - (IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6869 == _theResult____h4604[24:20]) ? - x_out_fbypass_rd_val__h6870 : - rd_val__h17628 ; - assign imm12__h10170 = { {2{nzimm10__h10168[9]}}, nzimm10__h10168 } ; - assign imm12__h10385 = { 2'd0, nzimm10__h10383 } ; - assign imm12__h10581 = { 7'b0, instr__h4602[6:2] } ; - assign imm12__h10926 = { 7'b0100000, instr__h4602[6:2] } ; - assign imm12__h7293 = { 4'd0, offset__h7063 } ; - assign imm12__h7630 = { 5'd0, offset__h7572 } ; - assign imm12__h9546 = { {6{imm6__h9544[5]}}, imm6__h9544 } ; - assign imm20__h9674 = { {14{imm6__h9544[5]}}, imm6__h9544 } ; - assign imm6__h9544 = { instr__h4602[12], instr__h4602[6:2] } ; - assign instr___1__h7017 = - (csr_regfile$read_misa[2] && instr__h4602[1:0] == 2'b10 && - instr__h4602[11:7] != 5'd0 && - instr__h4602[15:13] == 3'b010) ? - instr__h7292 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d598 ; - assign instr__h10372 = - { imm12__h10170, - instr__h4602[11:7], - 3'b0, - instr__h4602[11:7], - 7'b0010011 } ; - assign instr__h10544 = { imm12__h10385, 8'd16, rd__h7632, 7'b0010011 } ; - assign instr__h10717 = - { imm12__h10581, - instr__h4602[11:7], - 3'b001, - instr__h4602[11:7], - 7'b0010011 } ; - assign instr__h10910 = - { imm12__h10581, rs1__h7631, 3'b101, rs1__h7631, 7'b0010011 } ; - assign instr__h11103 = - { imm12__h10926, rs1__h7631, 3'b101, rs1__h7631, 7'b0010011 } ; - assign instr__h11220 = - { imm12__h9546, rs1__h7631, 3'b111, rs1__h7631, 7'b0010011 } ; - assign instr__h11398 = - { 7'b0, - instr__h4602[6:2], - 8'd0, - instr__h4602[11:7], - 7'b0110011 } ; - assign instr__h11517 = - { 7'b0, - instr__h4602[6:2], - instr__h4602[11:7], - 3'b0, - instr__h4602[11:7], - 7'b0110011 } ; - assign instr__h11612 = - { 7'b0, rd__h7632, rs1__h7631, 3'b111, rs1__h7631, 7'b0110011 } ; - assign instr__h11748 = - { 7'b0, rd__h7632, rs1__h7631, 3'b110, rs1__h7631, 7'b0110011 } ; - assign instr__h11884 = - { 7'b0, rd__h7632, rs1__h7631, 3'b100, rs1__h7631, 7'b0110011 } ; - assign instr__h12020 = - { 7'b0100000, - rd__h7632, - rs1__h7631, - 3'b0, - rs1__h7631, - 7'b0110011 } ; - assign instr__h12358 = - { 12'b000000000001, - instr__h4602[11:7], - 3'b0, - instr__h4602[11:7], - 7'b1110011 } ; - assign instr__h12461 = - { imm12__h7293, 8'd18, instr__h4602[11:7], 7'b0000111 } ; - assign instr__h12606 = - { 4'd0, - instr__h4602[8:7], - instr__h4602[12], - instr__h4602[6:2], - 8'd18, - offset_BITS_4_TO_0___h7561, - 7'b0100111 } ; - assign instr__h12798 = - { imm12__h7630, rs1__h7631, 3'b010, rd__h7632, 7'b0000111 } ; - assign instr__h12993 = - { 5'd0, - instr__h4602[5], - instr__h4602[12], - rd__h7632, - rs1__h7631, - 3'b010, - offset_BITS_4_TO_0___h7992, - 7'b0100111 } ; - assign instr__h13466 = - { 4'd0, - instr__h4602[6:5], - instr__h4602[12], - rd__h7632, - rs1__h7631, - 3'b011, - offset_BITS_4_TO_0___h13591, - 7'b0100111 } ; - assign instr__h4602 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 ? - instr_out___1__h7162 : - _theResult___fst__h7192 ; - assign instr__h7292 = - { imm12__h7293, 8'd18, instr__h4602[11:7], 7'b0000011 } ; - assign instr__h7437 = - { 4'd0, - instr__h4602[8:7], - instr__h4602[12], - instr__h4602[6:2], - 8'd18, - offset_BITS_4_TO_0___h7561, - 7'b0100011 } ; - assign instr__h7629 = - { imm12__h7630, rs1__h7631, 3'b010, rd__h7632, 7'b0000011 } ; - assign instr__h7824 = - { 5'd0, - instr__h4602[5], - instr__h4602[12], - rd__h7632, - rs1__h7631, - 3'b010, - offset_BITS_4_TO_0___h7992, - 7'b0100011 } ; - assign instr__h8053 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[19:12], - 12'd111 } ; - assign instr__h8396 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d400[19:12], - 12'd239 } ; - assign instr__h8786 = { 12'd0, instr__h4602[11:7], 15'd103 } ; - assign instr__h8902 = { 12'd0, instr__h4602[11:7], 15'd231 } ; - assign instr__h8967 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[10:5], - 5'd0, - rs1__h7631, - 3'b0, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[11], - 7'b1100011 } ; - assign instr__h9284 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[10:5], - 5'd0, - rs1__h7631, - 3'b001, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d429[11], - 7'b1100011 } ; - assign instr__h9622 = - { imm12__h9546, 8'd0, instr__h4602[11:7], 7'b0010011 } ; - assign instr__h9806 = { imm20__h9674, instr__h4602[11:7], 7'b0110111 } ; - assign instr__h9935 = - { imm12__h9546, - instr__h4602[11:7], - 3'b0, - instr__h4602[11:7], - 7'b0010011 } ; - assign instr_out___1__h7162 = - { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ; - assign instr_out___1__h7194 = { 16'b0, near_mem$imem_instr[15:0] } ; - assign instr_out___1__h7222 = { 16'b0, near_mem$imem_instr[31:16] } ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1457 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd0 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1460 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd1 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1463 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd2 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1466 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd3 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1469 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd4 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1472 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd5 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1475 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd6 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1478 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd7 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1481 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd8 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1484 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd9 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1487 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == - 4'd10 ; - assign near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1490 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd4 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd5 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd6 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd7 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd8 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd9 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 != - 4'd10 ; - assign near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 = - near_mem$imem_pc[31:2] == imem_rg_pc[31:2] ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d614 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] == 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d616 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d614 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 = - near_mem$imem_pc == next_pc___1__h16893 ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1601 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 != - 2'd1 || - !IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602 && - !IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d616 && - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 != - 2'd1 || - !IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602 && - !IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d940 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d951) ; - assign next_pc___1__h16893 = imem_rg_pc + 32'd2 ; - assign next_pc__h16891 = imem_rg_pc + 32'd4 ; - assign nzimm10__h10168 = - { instr__h4602[12], - instr__h4602[4:3], - instr__h4602[5], - instr__h4602[2], - instr__h4602[6], - 4'b0 } ; - assign nzimm10__h10383 = - { instr__h4602[10:7], - instr__h4602[12:11], - instr__h4602[5], - instr__h4602[6], - 2'b0 } ; - assign offset_BITS_4_TO_0___h13591 = { instr__h4602[11:10], 3'b0 } ; - assign offset_BITS_4_TO_0___h7561 = { instr__h4602[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h7992 = - { instr__h4602[11:10], instr__h4602[6], 2'b0 } ; - assign offset__h7063 = - { instr__h4602[3:2], - instr__h4602[12], - instr__h4602[6:4], - 2'b0 } ; - assign offset__h7572 = - { instr__h4602[5], instr__h4602[12:10], instr__h4602[6], 2'b0 } ; - assign offset__h8000 = - { instr__h4602[12], - instr__h4602[8], - instr__h4602[10:9], - instr__h4602[6], - instr__h4602[7], - instr__h4602[2], - instr__h4602[11], - instr__h4602[5:3], - 1'b0 } ; - assign offset__h8911 = - { instr__h4602[12], - instr__h4602[6:5], - instr__h4602[2], - instr__h4602[11:10], - instr__h4602[4:3], - 1'b0 } ; - assign output_stage2___1_data_to_stage3_rd_val__h6211 = - { 32'd0, stage2_mbox$word } ; - assign rd__h7632 = { 2'b01, instr__h4602[4:2] } ; - assign rd_val___1__h15218 = - rs1_val_bypassed__h4612 + _theResult___snd__h17391 ; - assign rd_val___1__h15226 = - rs1_val_bypassed__h4612 - _theResult___snd__h17391 ; - assign rd_val___1__h15233 = - ((rs1_val_bypassed__h4612 ^ 32'h80000000) < - (_theResult___snd__h17391 ^ 32'h80000000)) ? - 32'd1 : - 32'd0 ; - assign rd_val___1__h15240 = - (rs1_val_bypassed__h4612 < _theResult___snd__h17391) ? - 32'd1 : - 32'd0 ; - assign rd_val___1__h15247 = - rs1_val_bypassed__h4612 ^ _theResult___snd__h17391 ; - assign rd_val___1__h15254 = - rs1_val_bypassed__h4612 | _theResult___snd__h17391 ; - assign rd_val__h13631 = - (!stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d647) ? - stage3_rg_stage3[31:0] : - gpr_regfile$read_rs1 ; - assign rd_val__h13674 = - (!stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d655) ? - stage3_rg_stage3[31:0] : - gpr_regfile$read_rs2 ; - assign rd_val__h14066 = - (_theResult____h4604[14:12] == 3'b0 && - (_theResult____h4604[6:0] != 7'b0110011 || - !_theResult____h4604[30])) ? - rd_val___1__h15218 : - _theResult_____1_fst__h15230 ; - assign rd_val__h14086 = { _theResult____h4604[31:12], 12'h0 } ; - assign rd_val__h14105 = imem_rg_pc + rd_val__h14086 ; - assign rd_val__h17285 = rs1_val_bypassed__h4612 << shamt__h14020 ; - assign rd_val__h17337 = rs1_val_bypassed__h4612 >> shamt__h14020 ; - assign rd_val__h17359 = - rs1_val_bypassed__h4612 >> shamt__h14020 | - ~(32'hFFFFFFFF >> shamt__h14020) & - {32{rs1_val_bypassed__h4612[31]}} ; - assign rd_val__h17575 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d647) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs1 ; - assign rd_val__h17628 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d655) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs2 ; - assign rd_val__h17686 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3[75:71] == _theResult____h4604[31:27]) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs3 ; - assign rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7_EQ__ETC___d1148 = - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] || - rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) && - _theResult____h4604[31:20] == 12'b000100000101 ; - assign rg_state_6_EQ_3_618_AND_NOT_csr_regfile_interr_ETC___d1766 = - rg_state == 4'd3 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1763 && - !stage3_rg_full && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == - 2'd0 ; - assign rg_state_6_EQ_3_618_AND_stage3_rg_full_2_OR_NO_ETC___d1637 = - rg_state == 4'd3 && - (stage3_rg_full || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd0 || - stage1_rg_full) && - (stage3_rg_full || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd3) && - (stage3_rg_full || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd0 || - !stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1623) && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 || - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != - 2'd0 || - stage3_rg_full) ; - assign rm__h14593 = x_out_data_to_stage2_rounding_mode__h13753 ; - assign rs1__h7631 = { 2'b01, instr__h4602[9:7] } ; - assign rs1_val__h14431 = - _theResult____h4604[14] ? - { 27'd0, _theResult____h4604[19:15] } : - rs1_val_bypassed__h4612 ; - assign rs1_val__h21562 = - (x_out_data_to_stage2_instr__h13745[14:12] == 3'b001) ? - x_out_data_to_stage2_val1__h13749[31:0] : - { 27'd0, x_out_data_to_stage2_instr__h13745[19:15] } ; - assign rs1_val_bypassed__h4612 = - (_theResult____h4604[19:15] == 5'd0) ? 32'd0 : val__h13633 ; - assign rs2_val__h13850 = - (_theResult____h4604[24:20] == 5'd0) ? 32'd0 : val__h13676 ; - assign shamt__h14020 = - (_theResult____h4604[6:0] == 7'b0010011) ? - _theResult____h4604[24:20] : - rs2_val__h13850[4:0] ; - assign stage2_f_reset_rsps_i_notEmpty__571_AND_stage3_ETC___d1580 = - stage2_f_reset_rsps$EMPTY_N && stage3_f_reset_rsps$EMPTY_N && - f_reset_rsps$FULL_N && - (!rg_run_on_reset || - !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) ; - assign stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d647 = - stage3_rg_stage3[75:71] == _theResult____h4604[19:15] ; - assign stage3_rg_stage3_4_BITS_75_TO_71_3_EQ_IF_NOT_n_ETC___d655 = - stage3_rg_stage3[75:71] == _theResult____h4604[24:20] ; - assign theResult__604_BITS_31_TO_20__q18 = _theResult____h4604[31:20] ; - assign theResult__604_BITS_31_TO_25_CONCAT_theResult__ETC__q6 = - { _theResult____h4604[31:25], _theResult____h4604[11:7] } ; - assign theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q4 = - { _theResult____h4604[31], - _theResult____h4604[19:12], - _theResult____h4604[20], - _theResult____h4604[30:21], - 1'b0 } ; - assign theResult__604_BIT_31_CONCAT_theResult__604_BI_ETC__q5 = - { _theResult____h4604[31], - _theResult____h4604[7], - _theResult____h4604[30:25], - _theResult____h4604[11:8], - 1'b0 } ; - assign trap_info_tval__h16726 = - (_theResult____h4604[6:0] != 7'b1101111 && - _theResult____h4604[6:0] != 7'b1100111 && - (_theResult____h4604[6:0] != 7'b1110011 || - _theResult____h4604[14:12] != 3'b0 || - _theResult____h4604[11:7] != 5'd0 || - _theResult____h4604[19:15] != 5'd0 || - _theResult____h4604[31:20] != 12'b0 && - _theResult____h4604[31:20] != 12'b000000000001)) ? - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d614 ? - _theResult____h4604 : - { 16'd0, instr__h4602[15:0] }) : - CASE_theResult__604_BITS_6_TO_0_0b1100111_data_ETC__q19 ; - assign val__h13633 = - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == - 2'd2 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d602) ? - x_out_bypass_rd_val__h6718 : - rd_val__h13631 ; - assign val__h13676 = - (IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == - 2'd2 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d604) ? - x_out_bypass_rd_val__h6718 : - rd_val__h13674 ; - assign value__h16781 = - near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h16726 ; - assign x__h26770 = - csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d1854[63:0] / - _theResult____h26769 ; - assign x_out_data_to_stage2_instr__h13745 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 ? - instr___1__h7017 : - instr__h4602 ; - assign x_out_data_to_stage2_rounding_mode__h13753 = - (_theResult____h4604[14:12] == 3'b111) ? - csr_regfile$read_frm : - _theResult____h4604[14:12] ; - assign x_out_data_to_stage2_val2__h13750 = - (_theResult____h4604[6:0] == 7'b1100011) ? - alu_outputs___1_val2__h13877 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1432 ; - assign x_out_data_to_stage2_val3__h13751 = - (IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6869 == _theResult____h4604[31:27]) ? - x_out_fbypass_rd_val__h6870 : - rd_val__h17686 ; - assign x_out_next_pc__h13711 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100 ? - data_to_stage2_addr__h13737 : - fall_through_pc__h13698 ; - assign x_out_trap_info_exc_code__h16729 = - near_mem$imem_exc ? - near_mem$imem_exc_code : - alu_outputs_exc_code__h14690 ; - assign y__h22359 = ~rs1_val__h22055 ; - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd2, 3'd4: value__h6422 = stage2_rg_stage2[299:268]; - default: value__h6422 = stage2_rg_stage2[299:268]; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_exc_code) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd2, 3'd4: - x_out_trap_info_exc_code__h6459 = near_mem$dmem_exc_code; - default: x_out_trap_info_exc_code__h6459 = 4'd2; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd2, 3'd4: value__h6483 = stage2_rg_stage2[227:196]; - default: value__h6483 = 32'd0; - endcase - end - always@(stage2_rg_stage2 or stage2_fbox$word_snd) - begin - case (stage2_rg_stage2[235:233]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - x_out_data_to_stage3_fpr_flags__h6242 = 5'd0; - default: x_out_data_to_stage3_fpr_flags__h6242 = stage2_fbox$word_snd; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[235:233]) - 3'd0, 3'd1, 3'd4: - x_out_data_to_stage3_rd__h6239 = stage2_rg_stage2[232:228]; - 3'd2: x_out_data_to_stage3_rd__h6239 = 5'd0; - default: x_out_data_to_stage3_rd__h6239 = stage2_rg_stage2[232:228]; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[235:233]) - 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h6717 = stage2_rg_stage2[232:228]; - default: x_out_bypass_rd__h6717 = stage2_rg_stage2[232:228]; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd4: x_out_fbypass_rd__h6869 = stage2_rg_stage2[232:228]; - default: x_out_fbypass_rd__h6869 = stage2_rg_stage2[232:228]; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$word_fst or - data_to_stage3_rd_val__h6137 or - output_stage2___1_data_to_stage3_rd_val__h6211) - begin - case (stage2_rg_stage2[235:233]) - 3'd0: x_out_data_to_stage3_rd_val__h6243 = stage2_rg_stage2[195:132]; - 3'd1, 3'd4: - x_out_data_to_stage3_rd_val__h6243 = data_to_stage3_rd_val__h6137; - 3'd3: - x_out_data_to_stage3_rd_val__h6243 = - output_stage2___1_data_to_stage3_rd_val__h6211; - default: x_out_data_to_stage3_rd_val__h6243 = stage2_fbox$word_fst; - endcase - end - always@(stage2_rg_stage2 or - _theResult___fst_rd_val__h6707 or - _theResult_____1_fst_rd_val__h6696 or stage2_mbox$word) - begin - case (stage2_rg_stage2[235:233]) - 3'd0: x_out_bypass_rd_val__h6718 = stage2_rg_stage2[163:132]; - 3'd1, 3'd4: - x_out_bypass_rd_val__h6718 = _theResult_____1_fst_rd_val__h6696; - 3'd3: x_out_bypass_rd_val__h6718 = stage2_mbox$word; - default: x_out_bypass_rd_val__h6718 = _theResult___fst_rd_val__h6707; - endcase - end - always@(stage2_rg_stage2 or - _theResult___snd_rd_val__h6861 or - _theResult_____1_snd_fst_rd_val__h6855) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd4: - x_out_fbypass_rd_val__h6870 = - _theResult_____1_snd_fst_rd_val__h6855; - default: x_out_fbypass_rd_val__h6870 = _theResult___snd_rd_val__h6861; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129 or - IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125 or - IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127) - begin - case (stage2_rg_stage2[235:233]) - 3'd0: CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1 = 2'd2; - 3'd1, 3'd2, 3'd4: - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1 = - IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125; - 3'd3: - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1 = - IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127; - default: CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q1 = - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$valid or - near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150 = - !near_mem$dmem_valid || near_mem$dmem_exc; - 3'd3: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150 = - !stage2_mbox$valid; - default: IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150 = - !stage2_fbox$valid; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$valid or - near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160 = - near_mem$dmem_valid && !near_mem$dmem_exc; - 3'd3: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160 = - stage2_mbox$valid; - default: IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160 = - stage2_fbox$valid; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd4: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) && - stage2_rg_stage2[3]; - default: IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195 = - stage2_rg_stage2[235:233] != 3'd2 && - stage2_rg_stage2[235:233] != 3'd3 && - stage2_rg_stage2[3]; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd4: - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d230 = - near_mem$dmem_valid && near_mem$dmem_exc || - !stage2_rg_stage2[3]; - default: IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d230 = - stage2_rg_stage2[235:233] == 3'd2 || - stage2_rg_stage2[235:233] == 3'd3 || - !stage2_rg_stage2[3]; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129 or - IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d256 or - IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127) - begin - case (stage2_rg_stage2[235:233]) - 3'd0: CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 = 2'd2; - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 = - IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d256; - 3'd2: CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 = 2'd0; - 3'd3: - CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 = - IF_stage2_mbox_valid__26_THEN_2_ELSE_1___d127; - default: CASE_stage2_rg_stage2_BITS_235_TO_233_0_2_1_IF_ETC__q2 = - stage2_rg_stage2[3] ? - 2'd0 : - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129 or - IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d284) - begin - case (stage2_rg_stage2[235:233]) - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_235_TO_233_1_IF_NOT_ETC__q3 = - IF_NOT_near_mem_dmem_valid__22_44_OR_NOT_near__ETC___d284; - 3'd2, 3'd3: - CASE_stage2_rg_stage2_BITS_235_TO_233_1_IF_NOT_ETC__q3 = 2'd0; - default: CASE_stage2_rg_stage2_BITS_235_TO_233_1_IF_NOT_ETC__q3 = - stage2_rg_stage2[3] ? - IF_stage2_fbox_valid__28_THEN_2_ELSE_1___d129 : - 2'd0; - endcase - end - always@(_theResult____h4604) - begin - case (_theResult____h4604[6:0]) - 7'b0000011, - 7'b0000111, - 7'b0010011, - 7'b0010111, - 7'b0110011, - 7'b0110111, - 7'b1100111, - 7'b1101111: - x_out_data_to_stage2_rd__h13747 = _theResult____h4604[11:7]; - 7'b1100011: x_out_data_to_stage2_rd__h13747 = 5'd0; - default: x_out_data_to_stage2_rd__h13747 = _theResult____h4604[11:7]; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663) - begin - case (_theResult____h4604[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d946 = - _theResult____h4604[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663) - begin - case (_theResult____h4604[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d661; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d663; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 = - _theResult____h4604[14:12] == 3'b111 && - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d665; - endcase - end - always@(_theResult____h4604 or rm__h14593) - begin - case (_theResult____h4604[6:0]) - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111: - CASE_theResult__604_BITS_6_TO_0_0b1000011_NOT__ETC__q7 = - _theResult____h4604[26:25] != 2'b0 && - _theResult____h4604[26:25] != 2'b01; - default: CASE_theResult__604_BITS_6_TO_0_0b1000011_NOT__ETC__q7 = - _theResult____h4604[31:25] != 7'h0 && - _theResult____h4604[31:25] != 7'h04 && - _theResult____h4604[31:25] != 7'h08 && - _theResult____h4604[31:25] != 7'h0C && - _theResult____h4604[31:25] != 7'h2C && - (_theResult____h4604[31:25] != 7'h10 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h10 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h10 || - rm__h14593 != 3'd2) && - (_theResult____h4604[31:25] != 7'h60 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h60 || - _theResult____h4604[24:20] != 5'd1) && - (_theResult____h4604[31:25] != 7'h68 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h68 || - _theResult____h4604[24:20] != 5'd1) && - (_theResult____h4604[31:25] != 7'h14 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h14 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h50 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h50 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h50 || - rm__h14593 != 3'd2) && - (_theResult____h4604[31:25] != 7'h70 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h78 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h70 || - rm__h14593 != 3'd1) && - _theResult____h4604[31:25] != 7'b0000001 && - _theResult____h4604[31:25] != 7'h05 && - _theResult____h4604[31:25] != 7'b0001001 && - _theResult____h4604[31:25] != 7'h0D && - _theResult____h4604[31:25] != 7'h2D && - (_theResult____h4604[31:25] != 7'h11 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h11 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h11 || - rm__h14593 != 3'd2) && - (_theResult____h4604[31:25] != 7'h61 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h61 || - _theResult____h4604[24:20] != 5'd1) && - (_theResult____h4604[31:25] != 7'h69 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h69 || - _theResult____h4604[24:20] != 5'd1) && - (_theResult____h4604[31:25] != 7'h21 || - _theResult____h4604[24:20] != 5'd0) && - (_theResult____h4604[31:25] != 7'h20 || - _theResult____h4604[24:20] != 5'd1) && - (_theResult____h4604[31:25] != 7'h15 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h15 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h51 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h51 || - rm__h14593 != 3'd1) && - (_theResult____h4604[31:25] != 7'h51 || - rm__h14593 != 3'd2) && - (_theResult____h4604[31:25] != 7'h71 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h79 || - rm__h14593 != 3'd0) && - (_theResult____h4604[31:25] != 7'h71 || - rm__h14593 != 3'd1); - endcase - end - always@(_theResult____h4604 or - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d926 or - csr_regfile$read_mstatus) - begin - case (_theResult____h4604[6:0]) - 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930 = - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b010 && - _theResult____h4604[14:12] != 3'b011 || - csr_regfile$read_mstatus[14:13] == 2'h0; - 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930 = - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b010 && - _theResult____h4604[14:12] != 3'b011 || - csr_regfile$read_mstatus[14:13] == 2'h0; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930 = - _theResult____h4604[31:27] != 5'b00010 && - _theResult____h4604[31:27] != 5'b00011 && - _theResult____h4604[31:27] != 5'b0 && - _theResult____h4604[31:27] != 5'b00001 && - _theResult____h4604[31:27] != 5'b01100 && - _theResult____h4604[31:27] != 5'b01000 && - _theResult____h4604[31:27] != 5'b00100 && - _theResult____h4604[31:27] != 5'b10000 && - _theResult____h4604[31:27] != 5'b11000 && - _theResult____h4604[31:27] != 5'b10100 && - _theResult____h4604[31:27] != 5'b11100 || - _theResult____h4604[14:12] != 3'b010; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930 = - _theResult____h4604[6:0] != 7'b1010011 && - _theResult____h4604[6:0] != 7'b1000011 && - _theResult____h4604[6:0] != 7'b1000111 && - _theResult____h4604[6:0] != 7'b1001011 && - _theResult____h4604[6:0] != 7'b1001111 || - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d926; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930) - begin - case (_theResult____h4604[6:0]) - 7'b0000011: - CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b010 && - _theResult____h4604[14:12] != 3'b011; - 7'b0100011: - CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b010 && - _theResult____h4604[14:12] != 3'b011; - default: CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4604[6:0] == 7'b0001111 || - _theResult____h4604[6:0] == 7'b1110011 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d930; - endcase - end - always@(_theResult____h4604 or - CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 or - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d702) - begin - case (_theResult____h4604[6:0]) - 7'b0010011, 7'b0110011: - CASE_theResult__604_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d702; - default: CASE_theResult__604_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = - _theResult____h4604[6:0] != 7'b0110111 && - _theResult____h4604[6:0] != 7'b0010111 && - CASE_theResult__604_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8; - endcase - end - always@(_theResult____h4604 or rm__h14593) - begin - case (_theResult____h4604[6:0]) - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111: - CASE_theResult__604_BITS_6_TO_0_0b1000011_theR_ETC__q10 = - _theResult____h4604[26:25] == 2'b0 || - _theResult____h4604[26:25] == 2'b01; - default: CASE_theResult__604_BITS_6_TO_0_0b1000011_theR_ETC__q10 = - _theResult____h4604[31:25] == 7'h0 || - _theResult____h4604[31:25] == 7'h04 || - _theResult____h4604[31:25] == 7'h08 || - _theResult____h4604[31:25] == 7'h0C || - _theResult____h4604[31:25] == 7'h2C || - _theResult____h4604[31:25] == 7'h10 && - (rm__h14593 == 3'd0 || rm__h14593 == 3'd1 || - rm__h14593 == 3'd2) || - _theResult____h4604[31:25] == 7'h60 && - _theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[31:25] == 7'h60 && - _theResult____h4604[24:20] == 5'd1 || - _theResult____h4604[31:25] == 7'h68 && - (_theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[24:20] == 5'd1) || - _theResult____h4604[31:25] == 7'h14 && - (rm__h14593 == 3'd0 || rm__h14593 == 3'd1) || - _theResult____h4604[31:25] == 7'h50 && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h50 && - (rm__h14593 == 3'd1 || rm__h14593 == 3'd2) || - _theResult____h4604[31:25] == 7'h70 && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h78 && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h70 && - rm__h14593 == 3'd1 || - _theResult____h4604[31:25] == 7'b0000001 || - _theResult____h4604[31:25] == 7'h05 || - _theResult____h4604[31:25] == 7'b0001001 || - _theResult____h4604[31:25] == 7'h0D || - _theResult____h4604[31:25] == 7'h2D || - _theResult____h4604[31:25] == 7'h11 && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h11 && - (rm__h14593 == 3'd1 || rm__h14593 == 3'd2) || - _theResult____h4604[31:25] == 7'h61 && - _theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[31:25] == 7'h61 && - _theResult____h4604[24:20] == 5'd1 || - _theResult____h4604[31:25] == 7'h69 && - (_theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[24:20] == 5'd1) || - _theResult____h4604[31:25] == 7'h21 && - _theResult____h4604[24:20] == 5'd0 || - _theResult____h4604[31:25] == 7'h20 && - _theResult____h4604[24:20] == 5'd1 || - _theResult____h4604[31:25] == 7'h15 && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h15 && - rm__h14593 == 3'd1 || - _theResult____h4604[31:25] == 7'h51 && - (rm__h14593 == 3'd0 || rm__h14593 == 3'd1) || - _theResult____h4604[31:25] == 7'h51 && - rm__h14593 == 3'd2 || - (_theResult____h4604[31:25] == 7'h71 || - _theResult____h4604[31:25] == 7'h79) && - rm__h14593 == 3'd0 || - _theResult____h4604[31:25] == 7'h71 && rm__h14593 == 3'd1; - endcase - end - always@(_theResult____h4604 or - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1084 or - csr_regfile$read_mstatus) - begin - case (_theResult____h4604[6:0]) - 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088 = - (_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011) && - csr_regfile$read_mstatus[14:13] != 2'h0; - 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088 = - (_theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011) && - csr_regfile$read_mstatus[14:13] != 2'h0; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088 = - (_theResult____h4604[31:27] == 5'b00010 || - _theResult____h4604[31:27] == 5'b00011 || - _theResult____h4604[31:27] == 5'b0 || - _theResult____h4604[31:27] == 5'b00001 || - _theResult____h4604[31:27] == 5'b01100 || - _theResult____h4604[31:27] == 5'b01000 || - _theResult____h4604[31:27] == 5'b00100 || - _theResult____h4604[31:27] == 5'b10000 || - _theResult____h4604[31:27] == 5'b11000 || - _theResult____h4604[31:27] == 5'b10100 || - _theResult____h4604[31:27] == 5'b11100) && - _theResult____h4604[14:12] == 3'b010; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088 = - (_theResult____h4604[6:0] == 7'b1010011 || - _theResult____h4604[6:0] == 7'b1000011 || - _theResult____h4604[6:0] == 7'b1000111 || - _theResult____h4604[6:0] == 7'b1001011 || - _theResult____h4604[6:0] == 7'b1001111) && - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1084; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088) - begin - case (_theResult____h4604[6:0]) - 7'b0000011: - CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11 = - _theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b100 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011; - 7'b0100011: - CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11 = - _theResult____h4604[14:12] == 3'b0 || - _theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b010 || - _theResult____h4604[14:12] == 3'b011; - default: CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11 = - _theResult____h4604[6:0] != 7'b0001111 && - _theResult____h4604[6:0] != 7'b1110011 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1088; - endcase - end - always@(_theResult____h4604 or - CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d971) - begin - case (_theResult____h4604[6:0]) - 7'b0010011, 7'b0110011: - CASE_theResult__604_BITS_6_TO_0_0b10011_IF_NOT_ETC__q12 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d971; - default: CASE_theResult__604_BITS_6_TO_0_0b10011_IF_NOT_ETC__q12 = - _theResult____h4604[6:0] == 7'b0110111 || - _theResult____h4604[6:0] == 7'b0010111 || - CASE_theResult__604_BITS_6_TO_0_0b11_theResult_ETC__q11; - endcase - end - always@(rg_cur_priv) - begin - case (rg_cur_priv) - 2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q13 = 4'd8; - 2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q13 = 4'd9; - default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q13 = 4'd11; - endcase - end - always@(_theResult____h4604 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q13) - begin - case (_theResult____h4604[31:20]) - 12'b0: - CASE_theResult__604_BITS_31_TO_20_0b0_CASE_rg__ETC__q14 = - CASE_rg_cur_priv_0b0_8_0b1_9_11__q13; - 12'b000000000001: - CASE_theResult__604_BITS_31_TO_20_0b0_CASE_rg__ETC__q14 = 4'd3; - default: CASE_theResult__604_BITS_31_TO_20_0b0_CASE_rg__ETC__q14 = 4'd2; - endcase - end - always@(_theResult____h4604 or alu_outputs___1_exc_code__h14461) - begin - case (_theResult____h4604[6:0]) - 7'b0000011, - 7'b0001111, - 7'b0010011, - 7'b0010111, - 7'b0100011, - 7'b0110011, - 7'b0110111, - 7'b1100011: - alu_outputs_exc_code__h14690 = 4'd2; - 7'b1100111, 7'b1101111: alu_outputs_exc_code__h14690 = 4'd0; - 7'b1110011: - alu_outputs_exc_code__h14690 = alu_outputs___1_exc_code__h14461; - default: alu_outputs_exc_code__h14690 = 4'd2; - endcase - end - always@(_theResult____h4604 or - rg_cur_priv or - IF_rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7__ETC___d1150) - begin - case (_theResult____h4604[31:20]) - 12'b0, 12'b000000000001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1152 = 4'd11; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1152 = - (rg_cur_priv == 2'b11 && - _theResult____h4604[31:20] == 12'b001100000010) ? - 4'd7 : - IF_rg_cur_priv_7_EQ_0b11_121_OR_rg_cur_priv_7__ETC___d1150; - endcase - end - always@(_theResult____h4604) - begin - case (_theResult____h4604[14:12]) - 3'b0: CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd4; - 3'b001: CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd5; - default: CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd11; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1154) - begin - case (_theResult____h4604[14:12]) - 3'b0: - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1154; - 3'b001, 3'b101: - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16 = 4'd2; - 3'b010, 3'b011, 3'b110, 3'b111: - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16 = 4'd3; - 3'd4: CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16 = 4'd11; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1112 or - CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15 or - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1108 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1116 or - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1162 or - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16) - begin - case (_theResult____h4604[6:0]) - 7'b0000011, 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1112; - 7'b0001111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - CASE_theResult__604_BITS_14_TO_12_0b0_4_0b1_5_11__q15; - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1108; - 7'b0010111, 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = 4'd0; - 7'b0100011, 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1116; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - ((_theResult____h4604[31:27] == 5'b00010 || - _theResult____h4604[31:27] == 5'b00011 || - _theResult____h4604[31:27] == 5'b0 || - _theResult____h4604[31:27] == 5'b00001 || - _theResult____h4604[31:27] == 5'b01100 || - _theResult____h4604[31:27] == 5'b01000 || - _theResult____h4604[31:27] == 5'b00100 || - _theResult____h4604[31:27] == 5'b10000 || - _theResult____h4604[31:27] == 5'b11000 || - _theResult____h4604[31:27] == 5'b10100 || - _theResult____h4604[31:27] == 5'b11100) && - _theResult____h4604[14:12] == 3'b010) ? - 4'd0 : - 4'd11; - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111, 7'b1010011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1162; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - CASE_theResult__604_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q16; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 = - 4'd11; - endcase - end - always@(_theResult____h4604 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672) - begin - case (_theResult____h4604[6:0]) - 7'b1100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1176 = - (_theResult____h4604[14:12] != 3'b0 && - _theResult____h4604[14:12] != 3'b001 && - _theResult____h4604[14:12] != 3'b100 && - _theResult____h4604[14:12] != 3'b101 && - _theResult____h4604[14:12] != 3'b110 && - _theResult____h4604[14:12] != 3'b111) ? - 4'd11 : - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d672 ? - 4'd1 : - 4'd0); - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1176 = 4'd1; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1176 = - (_theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[31:25] == 7'b0000001) ? - 4'd0 : - (((_theResult____h4604[6:0] == 7'b0010011 || - _theResult____h4604[6:0] == 7'b0110011) && - (_theResult____h4604[14:12] == 3'b001 || - _theResult____h4604[14:12] == 3'b101)) ? - (_theResult____h4604[25] ? 4'd11 : 4'd0) : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1172); - endcase - end - always@(_theResult____h4604) - begin - case (_theResult____h4604[6:0]) - 7'b0000011, 7'b0000111: - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17 = 3'd1; - 7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111: - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17 = 3'd0; - 7'b0100011, 7'b0100111: - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17 = 3'd2; - 7'b0101111: - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17 = 3'd4; - default: CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17 = 3'd5; - endcase - end - always@(_theResult____h4604 or - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17) - begin - case (_theResult____h4604[6:0]) - 7'b1100011, 7'b1100111, 7'b1101111: - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 = 3'd0; - default: IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 = - (_theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[31:25] == 7'b0000001) ? - 3'd3 : - CASE_theResult__604_BITS_6_TO_0_0b11_1_0b111_1_ETC__q17; - endcase - end - always@(_theResult____h4604 or - _theResult_____1_fst__h15265 or - rd_val___1__h15233 or - rd_val___1__h15240 or rd_val___1__h15247 or rd_val___1__h15254) - begin - case (_theResult____h4604[14:12]) - 3'b010: _theResult_____1_fst__h15237 = rd_val___1__h15233; - 3'b011: _theResult_____1_fst__h15237 = rd_val___1__h15240; - 3'b100: _theResult_____1_fst__h15237 = rd_val___1__h15247; - 3'b110: _theResult_____1_fst__h15237 = rd_val___1__h15254; - default: _theResult_____1_fst__h15237 = _theResult_____1_fst__h15265; - endcase - end - always@(_theResult____h4604 or - alu_outputs___1_addr__h14178 or - alu_outputs___1_addr__h14154 or - rs1_val_bypassed__h4612 or - alu_outputs___1_addr__h13875 or - alu_outputs___1_addr__h13928 or alu_outputs___1_addr__h13899) - begin - case (_theResult____h4604[6:0]) - 7'b0000011, 7'b0000111: - x_out_data_to_stage2_addr__h13748 = alu_outputs___1_addr__h14154; - 7'b0100011: - x_out_data_to_stage2_addr__h13748 = alu_outputs___1_addr__h14178; - 7'b0101111: x_out_data_to_stage2_addr__h13748 = rs1_val_bypassed__h4612; - 7'b1100011: - x_out_data_to_stage2_addr__h13748 = alu_outputs___1_addr__h13875; - 7'b1100111: - x_out_data_to_stage2_addr__h13748 = alu_outputs___1_addr__h13928; - 7'b1101111: - x_out_data_to_stage2_addr__h13748 = alu_outputs___1_addr__h13899; - default: x_out_data_to_stage2_addr__h13748 = - alu_outputs___1_addr__h14178; - endcase - end - always@(_theResult____h4604 or imem_rg_pc or data_to_stage2_addr__h13737) - begin - case (_theResult____h4604[6:0]) - 7'b1100111, 7'b1101111: - CASE_theResult__604_BITS_6_TO_0_0b1100111_data_ETC__q19 = - data_to_stage2_addr__h13737; - default: CASE_theResult__604_BITS_6_TO_0_0b1100111_data_ETC__q19 = - (_theResult____h4604[6:0] == 7'b1110011 && - _theResult____h4604[14:12] == 3'b0 && - _theResult____h4604[11:7] == 5'd0 && - _theResult____h4604[19:15] == 5'd0 && - _theResult____h4604[31:20] == 12'b000000000001) ? - imem_rg_pc : - 32'd0; - endcase - end - always@(_theResult____h4604 or - alu_outputs___1_val1__h14666 or - alu_outputs___1_val1__h14076 or - alu_outputs___1_val1__h14114 or - alu_outputs___1_val1__h14489 or - alu_outputs___1_val1__h14095 or alu_outputs___1_val1__h14465) - begin - case (_theResult____h4604[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14076; - 7'b0010111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14114; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14489; - 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14095; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14465; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1411 = - alu_outputs___1_val1__h14666; - endcase - end - always@(_theResult____h4604 or - alu_outputs___1_val1__h15021 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1412 or - alu_outputs___1_val1__h13900) - begin - case (_theResult____h4604[6:0]) - 7'b1100111, 7'b1101111: - x_out_data_to_stage2_val1__h13749 = alu_outputs___1_val1__h13900; - default: x_out_data_to_stage2_val1__h13749 = - (_theResult____h4604[6:0] == 7'b0110011 && - _theResult____h4604[31:25] == 7'b0000001) ? - alu_outputs___1_val1__h15021 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1412; - endcase - end - always@(x_out_data_to_stage2_instr__h13745 or - x_out_data_to_stage2_val1__h13749) - begin - case (x_out_data_to_stage2_instr__h13745[14:12]) - 3'b010, 3'b011: - rs1_val__h22055 = x_out_data_to_stage2_val1__h13749[31:0]; - default: rs1_val__h22055 = - { 27'd0, x_out_data_to_stage2_instr__h13745[19:15] }; - endcase - end - always@(_theResult____h4604 or - frs2_val_bypassed__h4628 or - alu_outputs___1_val2__h14180 or alu_outputs___1_val2__h15022) - begin - case (_theResult____h4604[6:0]) - 7'b0100011, 7'b0100111: - CASE_theResult__604_BITS_6_TO_0_0b100011_alu_o_ETC__q20 = - alu_outputs___1_val2__h14180; - 7'b0101111: - CASE_theResult__604_BITS_6_TO_0_0b100011_alu_o_ETC__q20 = - alu_outputs___1_val2__h15022; - default: CASE_theResult__604_BITS_6_TO_0_0b100011_alu_o_ETC__q20 = - frs2_val_bypassed__h4628; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0; - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11; - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_logdelay$EN) - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN; - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_cur_priv$EN) - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN; - if (rg_run_on_reset$EN) - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (stage1_rg_full$EN) - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN; - if (stage2_rg_full$EN) - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN; - if (stage2_rg_resetting$EN) - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY - stage2_rg_resetting$D_IN; - if (stage3_rg_full$EN) - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN; - end - if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN; - if (imem_rg_instr_15_0$EN) - imem_rg_instr_15_0 <= `BSV_ASSIGNMENT_DELAY imem_rg_instr_15_0$D_IN; - if (imem_rg_mstatus_MXR$EN) - imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN; - if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN; - if (imem_rg_priv$EN) - imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN; - if (imem_rg_satp$EN) - imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN; - if (imem_rg_sstatus_SUM$EN) - imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN; - if (imem_rg_tval$EN) - imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_start_CPI_cycles$EN) - rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN; - if (rg_start_CPI_instrs$EN) - rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN; - if (stage2_rg_stage2$EN) - stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN; - if (stage3_rg_stage3$EN) - stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_logdelay = 64'hAAAAAAAAAAAAAAAA; - cfg_verbosity = 4'hA; - imem_rg_f3 = 3'h2; - imem_rg_instr_15_0 = 16'hAAAA; - imem_rg_mstatus_MXR = 1'h0; - imem_rg_pc = 32'hAAAAAAAA; - imem_rg_priv = 2'h2; - imem_rg_satp = 32'hAAAAAAAA; - imem_rg_sstatus_SUM = 1'h0; - imem_rg_tval = 32'hAAAAAAAA; - rg_cur_priv = 2'h2; - rg_mstatus_MXR = 1'h0; - rg_next_pc = 32'hAAAAAAAA; - rg_run_on_reset = 1'h0; - rg_sstatus_SUM = 1'h0; - rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA; - rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - stage1_rg_full = 1'h0; - stage2_rg_full = 1'h0; - stage2_rg_resetting = 1'h0; - stage2_rg_stage2 = - 302'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - stage3_rg_full = 1'h0; - stage3_rg_stage3 = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - rg_cur_priv, - csr_regfile$read_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write("MStatus{", - "sd:%0d", - csr_regfile$read_mstatus[14:13] == 2'h3 || - csr_regfile$read_mstatus[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2) - $write(" sxl:%0d uxl:%0d", 2'd0, 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tsr:%0d", csr_regfile$read_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tw:%0d", csr_regfile$read_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tvm:%0d", csr_regfile$read_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mxr:%0d", csr_regfile$read_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" sum:%0d", csr_regfile$read_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mprv:%0d", csr_regfile$read_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" xs:%0d", csr_regfile$read_mstatus[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" fs:%0d", csr_regfile$read_mstatus[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mpp:%0d", csr_regfile$read_mstatus[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" spp:%0d", csr_regfile$read_mstatus[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" pies:%0d_%0d%0d", - csr_regfile$read_mstatus[7], - csr_regfile$read_mstatus[5], - csr_regfile$read_mstatus[4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" ies:%0d_%0d%0d", - csr_regfile$read_mstatus[3], - csr_regfile$read_mstatus[1], - csr_regfile$read_mstatus[0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("Rd %0d ", stage3_rg_stage3[75:71]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("rd_val:%h", stage3_rg_stage3[31:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write("FRd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("FRd %0d ", stage3_rg_stage3[75:71]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("frd_val:%h", stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage2: pc 0x%08h instr 0x%08h priv %0d", - stage2_rg_stage2[299:268], - stage2_rg_stage2[267:236], - stage2_rg_stage2[301:300]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write("Output_Stage2", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[299:268]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("Output_Stage2", " NONPIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write("Output_Stage2", " PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[299:268], - stage2_rg_stage2[267:236], - stage2_rg_stage2[301:300]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - stage2_rg_stage2[235:233] != 3'd0 && - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - (stage2_rg_stage2[235:233] == 3'd0 || - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - stage2_rg_stage2[235:233] != 3'd0 && - stage2_rg_stage2[235:233] != 3'd1 && - stage2_rg_stage2[235:233] != 3'd4 && - stage2_rg_stage2[235:233] != 3'd2 && - stage2_rg_stage2[235:233] != 3'd3) - $write(" fflags: %05b", - "'h%h", - x_out_data_to_stage3_fpr_flags__h6242); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - (stage2_rg_stage2[235:233] == 3'd0 || - stage2_rg_stage2[235:233] == 3'd1 || - stage2_rg_stage2[235:233] == 3'd4 || - stage2_rg_stage2[235:233] == 3'd2 || - stage2_rg_stage2[235:233] == 3'd3)) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - stage2_rg_stage2[235:233] != 3'd0 && - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195) - $write(" frd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6239, - x_out_data_to_stage3_rd_val__h6243); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3 && - (stage2_rg_stage2[235:233] == 3'd0 || - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d230)) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6239, - x_out_data_to_stage3_rd_val__h6243); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", value__h6422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", x_out_trap_info_exc_code__h6459); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", value__h6483, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", value__h6422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", x_out_trap_info_exc_code__h6459); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd3) - $write("'h%h", value__h6483, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd1 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == 2'd0) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 != 2'd0) - $write("Rd %0d ", x_out_bypass_rd__h6717); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 != 2'd0 && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d263 != 2'd1) - $write("rd_val:%h", x_out_bypass_rd_val__h6718); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == 2'd0) - $write("FRd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 != 2'd0) - $write("FRd %0d ", x_out_fbypass_rd__h6869); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 != 2'd0 && - IF_NOT_stage2_rg_full_8_36_OR_stage2_rg_stage2_ETC___d289 != 2'd1) - $write("frd_val:%h", x_out_fbypass_rd_val__h6870); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage1: pc 0x%08h instr 0x%08h priv %0d", - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write("Output_Stage1", " BUSY pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write("Output_Stage1", " NONPIPE: pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write("Output_Stage1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) - $write("Output_Stage1", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(" PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd0) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd1) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd2) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd3) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd4) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd5) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd6) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd7) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd8) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd9) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1178 == 4'd10) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1244) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n", - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(" op_stage2:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == 3'd0) - $write("OP_Stage2_ALU"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == 3'd1) - $write("OP_Stage2_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == 3'd2) - $write("OP_Stage2_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == 3'd3) - $write("OP_Stage2_M"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1098 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1100) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1260 == 3'd4) - $write("OP_Stage2_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - NOT_near_mem_imem_exc__23_56_AND_IF_IF_NOT_nea_ETC___d1290) - $write("OP_Stage2_FD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(" rd:%0d\n", x_out_data_to_stage2_rd__h13747); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(" addr:%h val1:%h val2:%h val3:%h}", - x_out_data_to_stage2_addr__h13748, - x_out_data_to_stage2_val1__h13749, - x_out_data_to_stage2_val2__h13750, - x_out_data_to_stage2_val3__h13751); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1457) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1460) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1463) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1466) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1469) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1472) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1475) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1478) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1481) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1484) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1487) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622 && - near_mem_imem_exc__23_OR_IF_IF_NOT_near_mem_im_ETC___d1490) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write("'h%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write("'h%h", x_out_trap_info_exc_code__h16729); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d954) - $write("'h%h", value__h16781, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1103) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d607) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d622) - $write(" next_pc 0x%08h", x_out_next_pc__h13711); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - value__h6422, - stage2_rg_stage2[267:236], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3131 != 4'd0) - $display(" mcause:0x%0h epc 0x%0h tval:0x%0h new pc 0x%0h, new mstatus 0x%0h", - csr_regfile$csr_trap_actions[33:2], - value__h6422, - value__h6483, - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[65:34]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h13745[19:15], - rs1_val__h21562, - x_out_data_to_stage2_instr__h13745[31:20], - csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h13745[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h13745[19:15], - rs1_val__h21562, - x_out_data_to_stage2_instr__h13745[31:20], - x_out_data_to_stage2_instr__h13745[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_CSRR_S_or_C", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h13745[19:15], - rs1_val__h22055, - x_out_data_to_stage2_instr__h13745[31:20], - csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h13745[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h13745[19:15], - rs1_val__h22055, - x_out_data_to_stage2_instr__h13745[31:20], - x_out_data_to_stage2_instr__h13745[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h13711); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d pc:%0x cur_priv:%0d", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - x_out_next_pc__h13711, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3131 != 4'd0) - $display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d", - csr_regfile$csr_ret_actions[65:34], - csr_regfile$csr_ret_actions[31:0], - csr_regfile$csr_ret_actions[33:32]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_stage1_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h3131 != 4'd0) - $display(" WFI resume"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_from_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1851) - $display("%0d: CPU.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x", - csr_regfile$read_csr_mcycle, - csr_regfile$csr_trap_actions[97:66], - x_out_data_to_stage2_instr__h13745); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1851) - $display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'", - cpi__h26771, - cpifrac__h26772, - delta_CPI_cycles__h26767, - _theResult____h26769); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1851) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3131 != 4'd0) - $display("%0d: CPU.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", - csr_regfile$read_csr_mcycle, - rg_cur_priv, - csr_regfile$csr_trap_actions[33:2], - imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3131 != 4'd0) - $display(" tval:0x%0h new pc:0x%0h new mstatus:0x%0h", - value__h16781, - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[65:34]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_trap_fetch && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3131 != 4'd0) - $display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", - csr_regfile$read_csr_mcycle, - imem_rg_pc, - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[1:0], - csr_regfile$csr_trap_actions[65:34]); - if (WILL_FIRE_RL_imem_rl_assert_fail) - $display("ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False"); - if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", - soc_map$m_pc_reset_value[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h", - csr_regfile$read_csr_mcycle, - soc_map$m_pc_reset_value[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage3_rg_stage3[69]) - $display(" S3.fa_deq: write FRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[75:71], - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - !stage3_rg_stage3[69]) - $display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[75:71], - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write(" S3.enq: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[299:268], - stage2_rg_stage2[267:236], - stage2_rg_stage2[301:300]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[235:233] != 3'd0 && - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d150) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[235:233] == 3'd0 || - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d160)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[235:233] != 3'd0 && - stage2_rg_stage2[235:233] != 3'd1 && - stage2_rg_stage2[235:233] != 3'd4 && - stage2_rg_stage2[235:233] != 3'd2 && - stage2_rg_stage2[235:233] != 3'd3) - $write(" fflags: %05b", - "'h%h", - x_out_data_to_stage3_fpr_flags__h6242); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[235:233] == 3'd0 || - stage2_rg_stage2[235:233] == 3'd1 || - stage2_rg_stage2[235:233] == 3'd4 || - stage2_rg_stage2[235:233] == 3'd2 || - stage2_rg_stage2[235:233] == 3'd3)) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[235:233] != 3'd0 && - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d195) - $write(" frd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6239, - x_out_data_to_stage3_rd_val__h6243); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[235:233] == 3'd0 || - IF_stage2_rg_stage2_9_BITS_235_TO_233_00_EQ_1__ETC___d230)) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6239, - x_out_data_to_stage3_rd_val__h6243); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_8_THEN_IF_stage2_rg_stage2_9_ETC___d134 == 2'd2 && - cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[299:268], - stage2_rg_stage2[267:236], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1679 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage2.enq (Data_Stage1_to_Stage2)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1634 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1735 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h13711); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h3131 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h13745, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $write("CPU: Bluespec RISC-V Piccolo v3.0"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) $display(" (RV32)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h3131 != 4'd0) - $display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle); - end - // synopsys translate_on -endmodule // mkCPU - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v deleted file mode 100644 index a9f5381f..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v +++ /dev/null @@ -1,228 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 32 -// fav_write O 32 -// fv_sie_read O 32 -// fav_sie_write O 32 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 32 -// fav_sie_write_misa I 28 -// fav_sie_write_wordxl I 32 -// EN_reset I 1 -// EN_fav_write I 1 -// EN_fav_sie_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// (fav_sie_write_misa, fav_sie_write_wordxl) -> fav_sie_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIE(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - fv_sie_read, - - fav_sie_write_misa, - fav_sie_write_wordxl, - EN_fav_sie_write, - fav_sie_write); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [31 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [31 : 0] fav_write_wordxl; - input EN_fav_write; - output [31 : 0] fav_write; - - // value method fv_sie_read - output [31 : 0] fv_sie_read; - - // actionvalue method fav_sie_write - input [27 : 0] fav_sie_write_misa; - input [31 : 0] fav_sie_write_wordxl; - input EN_fav_sie_write; - output [31 : 0] fav_sie_write; - - // signals for module outputs - wire [31 : 0] fav_sie_write, fav_write, fv_read, fv_sie_read; - - // register rg_mie - reg [11 : 0] rg_mie; - reg [11 : 0] rg_mie$D_IN; - wire rg_mie$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_sie_write, - CAN_FIRE_fav_write, - CAN_FIRE_reset, - WILL_FIRE_fav_sie_write, - WILL_FIRE_fav_write, - WILL_FIRE_reset; - - // inputs to muxes for submodule ports - wire [11 : 0] MUX_rg_mie$write_1__VAL_3; - - // remaining internal signals - wire [11 : 0] mie__h92, x__h458, x__h883; - wire seie__h123, - seie__h544, - ssie__h117, - ssie__h538, - stie__h120, - stie__h541, - ueie__h122, - ueie__h543, - usie__h116, - usie__h537, - utie__h119, - utie__h540; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 20'd0, rg_mie } ; - - // actionvalue method fav_write - assign fav_write = { 20'd0, mie__h92 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // value method fv_sie_read - assign fv_sie_read = { 20'd0, x__h458 } ; - - // actionvalue method fav_sie_write - assign fav_sie_write = { 20'd0, x__h883 } ; - assign CAN_FIRE_fav_sie_write = 1'd1 ; - assign WILL_FIRE_fav_sie_write = EN_fav_sie_write ; - - // inputs to muxes for submodule ports - assign MUX_rg_mie$write_1__VAL_3 = - { rg_mie[11], - 1'b0, - seie__h544, - ueie__h543, - rg_mie[7], - 1'b0, - stie__h541, - utie__h540, - rg_mie[3], - 1'b0, - ssie__h538, - usie__h537 } ; - - // register rg_mie - always@(EN_fav_write or - mie__h92 or - EN_reset or EN_fav_sie_write or MUX_rg_mie$write_1__VAL_3) - case (1'b1) - EN_fav_write: rg_mie$D_IN = mie__h92; - EN_reset: rg_mie$D_IN = 12'd0; - EN_fav_sie_write: rg_mie$D_IN = MUX_rg_mie$write_1__VAL_3; - default: rg_mie$D_IN = 12'b101010101010 /* unspecified value */ ; - endcase - assign rg_mie$EN = EN_fav_write || EN_fav_sie_write || EN_reset ; - - // remaining internal signals - assign mie__h92 = - { fav_write_wordxl[11], - 1'b0, - seie__h123, - ueie__h122, - fav_write_wordxl[7], - 1'b0, - stie__h120, - utie__h119, - fav_write_wordxl[3], - 1'b0, - ssie__h117, - usie__h116 } ; - assign seie__h123 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign seie__h544 = fav_sie_write_misa[18] && fav_sie_write_wordxl[9] ; - assign ssie__h117 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign ssie__h538 = fav_sie_write_misa[18] && fav_sie_write_wordxl[1] ; - assign stie__h120 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign stie__h541 = fav_sie_write_misa[18] && fav_sie_write_wordxl[5] ; - assign ueie__h122 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign ueie__h543 = fav_sie_write_misa[13] && fav_sie_write_wordxl[8] ; - assign usie__h116 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign usie__h537 = fav_sie_write_misa[13] && fav_sie_write_wordxl[0] ; - assign utie__h119 = fav_write_misa[13] && fav_write_wordxl[4] ; - assign utie__h540 = fav_sie_write_misa[13] && fav_sie_write_wordxl[4] ; - assign x__h458 = - { 2'd0, rg_mie[9:8], 2'd0, rg_mie[5:4], 2'd0, rg_mie[1:0] } ; - assign x__h883 = - { 2'd0, - seie__h544, - ueie__h543, - 2'd0, - stie__h541, - utie__h540, - 2'd0, - ssie__h538, - usie__h537 } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_mie = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIE - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v deleted file mode 100644 index a3222f14..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v +++ /dev/null @@ -1,374 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 32 -// fav_write O 32 -// fv_sip_read O 32 -// fav_sip_write O 32 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 32 -// fav_sip_write_misa I 28 -// fav_sip_write_wordxl I 32 -// m_external_interrupt_req_req I 1 reg -// s_external_interrupt_req_req I 1 reg -// software_interrupt_req_req I 1 reg -// timer_interrupt_req_req I 1 reg -// EN_reset I 1 -// EN_fav_write I 1 -// EN_fav_sip_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// (fav_sip_write_misa, fav_sip_write_wordxl) -> fav_sip_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIP(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - fv_sip_read, - - fav_sip_write_misa, - fav_sip_write_wordxl, - EN_fav_sip_write, - fav_sip_write, - - m_external_interrupt_req_req, - - s_external_interrupt_req_req, - - software_interrupt_req_req, - - timer_interrupt_req_req); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [31 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [31 : 0] fav_write_wordxl; - input EN_fav_write; - output [31 : 0] fav_write; - - // value method fv_sip_read - output [31 : 0] fv_sip_read; - - // actionvalue method fav_sip_write - input [27 : 0] fav_sip_write_misa; - input [31 : 0] fav_sip_write_wordxl; - input EN_fav_sip_write; - output [31 : 0] fav_sip_write; - - // action method m_external_interrupt_req - input m_external_interrupt_req_req; - - // action method s_external_interrupt_req - input s_external_interrupt_req_req; - - // action method software_interrupt_req - input software_interrupt_req_req; - - // action method timer_interrupt_req - input timer_interrupt_req_req; - - // signals for module outputs - wire [31 : 0] fav_sip_write, fav_write, fv_read, fv_sip_read; - - // register rg_meip - reg rg_meip; - wire rg_meip$D_IN, rg_meip$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_seip - reg rg_seip; - wire rg_seip$D_IN, rg_seip$EN; - - // register rg_ssip - reg rg_ssip; - reg rg_ssip$D_IN; - wire rg_ssip$EN; - - // register rg_stip - reg rg_stip; - wire rg_stip$D_IN, rg_stip$EN; - - // register rg_ueip - reg rg_ueip; - reg rg_ueip$D_IN; - wire rg_ueip$EN; - - // register rg_usip - reg rg_usip; - reg rg_usip$D_IN; - wire rg_usip$EN; - - // register rg_utip - reg rg_utip; - wire rg_utip$D_IN, rg_utip$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_sip_write, - CAN_FIRE_fav_write, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_reset, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_fav_sip_write, - WILL_FIRE_fav_write, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_reset, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // remaining internal signals - wire [11 : 0] new_mip__h528, new_mip__h946; - wire seip__h562, - ssip__h566, - ssip__h986, - stip__h564, - ueip__h563, - ueip__h985, - usip__h567, - usip__h987, - utip__h565; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 20'd0, new_mip__h528 } ; - - // actionvalue method fav_write - assign fav_write = { 20'd0, new_mip__h946 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // value method fv_sip_read - assign fv_sip_read = - { 22'd0, - rg_seip, - rg_ueip, - 2'b0, - rg_stip, - rg_utip, - 2'b0, - rg_ssip, - rg_usip } ; - - // actionvalue method fav_sip_write - assign fav_sip_write = - { 22'd0, - rg_seip, - ueip__h985, - 2'b0, - rg_stip, - rg_utip, - 2'b0, - ssip__h986, - usip__h987 } ; - assign CAN_FIRE_fav_sip_write = 1'd1 ; - assign WILL_FIRE_fav_sip_write = EN_fav_sip_write ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // register rg_meip - assign rg_meip$D_IN = m_external_interrupt_req_req ; - assign rg_meip$EN = 1'b1 ; - - // register rg_msip - assign rg_msip$D_IN = software_interrupt_req_req ; - assign rg_msip$EN = 1'b1 ; - - // register rg_mtip - assign rg_mtip$D_IN = timer_interrupt_req_req ; - assign rg_mtip$EN = 1'b1 ; - - // register rg_seip - assign rg_seip$D_IN = s_external_interrupt_req_req ; - assign rg_seip$EN = 1'b1 ; - - // register rg_ssip - always@(EN_reset or - EN_fav_write or ssip__h566 or EN_fav_sip_write or ssip__h986) - case (1'b1) - EN_reset: rg_ssip$D_IN = 1'd0; - EN_fav_write: rg_ssip$D_IN = ssip__h566; - EN_fav_sip_write: rg_ssip$D_IN = ssip__h986; - default: rg_ssip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_ssip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_stip - assign rg_stip$D_IN = !EN_reset && stip__h564 ; - assign rg_stip$EN = EN_fav_write || EN_reset ; - - // register rg_ueip - always@(EN_reset or - EN_fav_write or ueip__h563 or EN_fav_sip_write or ueip__h985) - case (1'b1) - EN_reset: rg_ueip$D_IN = 1'd0; - EN_fav_write: rg_ueip$D_IN = ueip__h563; - EN_fav_sip_write: rg_ueip$D_IN = ueip__h985; - default: rg_ueip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_ueip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_usip - always@(EN_reset or - EN_fav_write or usip__h567 or EN_fav_sip_write or usip__h987) - case (1'b1) - EN_reset: rg_usip$D_IN = 1'd0; - EN_fav_write: rg_usip$D_IN = usip__h567; - EN_fav_sip_write: rg_usip$D_IN = usip__h987; - default: rg_usip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_usip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_utip - assign rg_utip$D_IN = !EN_reset && utip__h565 ; - assign rg_utip$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign new_mip__h528 = - { rg_meip, - 1'b0, - rg_seip, - rg_ueip, - rg_mtip, - 1'b0, - rg_stip, - rg_utip, - rg_msip, - 1'b0, - rg_ssip, - rg_usip } ; - assign new_mip__h946 = - { rg_meip, - 1'b0, - seip__h562, - ueip__h563, - rg_mtip, - 1'b0, - stip__h564, - utip__h565, - rg_msip, - 1'b0, - ssip__h566, - usip__h567 } ; - assign seip__h562 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssip__h566 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign ssip__h986 = fav_sip_write_misa[18] && fav_sip_write_wordxl[1] ; - assign stip__h564 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueip__h563 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign ueip__h985 = fav_sip_write_misa[13] && fav_sip_write_wordxl[8] ; - assign usip__h567 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign usip__h987 = fav_sip_write_misa[13] && fav_sip_write_wordxl[0] ; - assign utip__h565 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN; - if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN; - if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN; - if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN; - if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN; - if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_meip = 1'h0; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_seip = 1'h0; - rg_ssip = 1'h0; - rg_stip = 1'h0; - rg_ueip = 1'h0; - rg_usip = 1'h0; - rg_utip = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIP - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v deleted file mode 100644 index 78e7758d..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v +++ /dev/null @@ -1,3747 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_csr O 33 -// read_csr_port2 O 33 -// mav_read_csr O 33 -// mav_csr_write O 32 -// read_frm O 3 reg -// read_misa O 28 const -// read_mstatus O 32 reg -// read_sstatus O 32 -// read_ustatus O 32 -// read_satp O 32 reg -// csr_trap_actions O 98 -// RDY_csr_trap_actions O 1 const -// csr_ret_actions O 66 -// RDY_csr_ret_actions O 1 const -// read_csr_minstret O 64 reg -// read_csr_mcycle O 64 reg -// read_csr_mtime O 64 reg -// access_permitted_1 O 1 -// access_permitted_2 O 1 -// csr_counter_read_fault O 1 -// csr_mip_read O 32 -// interrupt_pending O 5 -// wfi_resume O 1 -// nmi_pending O 1 reg -// RDY_debug O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// read_csr_csr_addr I 12 -// read_csr_port2_csr_addr I 12 -// mav_read_csr_csr_addr I 12 -// mav_csr_write_csr_addr I 12 -// mav_csr_write_word I 32 -// ma_update_fcsr_fflags_flags I 5 -// ma_update_mstatus_fs_fs I 2 -// csr_trap_actions_from_priv I 2 -// csr_trap_actions_pc I 32 -// csr_trap_actions_nmi I 1 -// csr_trap_actions_interrupt I 1 -// csr_trap_actions_exc_code I 4 -// csr_trap_actions_xtval I 32 -// csr_ret_actions_from_priv I 2 -// access_permitted_1_priv I 2 -// access_permitted_1_csr_addr I 12 -// access_permitted_1_read_not_write I 1 -// access_permitted_2_priv I 2 -// access_permitted_2_csr_addr I 12 -// access_permitted_2_read_not_write I 1 -// csr_counter_read_fault_priv I 2 -// csr_counter_read_fault_csr_addr I 12 -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// interrupt_pending_cur_priv I 2 -// nmi_req_set_not_clear I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_ma_update_fcsr_fflags I 1 -// EN_ma_update_mstatus_fs I 1 -// EN_csr_minstret_incr I 1 -// EN_debug I 1 unused -// EN_mav_read_csr I 1 unused -// EN_mav_csr_write I 1 -// EN_csr_trap_actions I 1 -// EN_csr_ret_actions I 1 -// -// Combinational paths from inputs to outputs: -// read_csr_csr_addr -> read_csr -// read_csr_port2_csr_addr -> read_csr_port2 -// (access_permitted_1_priv, -// access_permitted_1_csr_addr, -// access_permitted_1_read_not_write) -> access_permitted_1 -// (access_permitted_2_priv, -// access_permitted_2_csr_addr, -// access_permitted_2_read_not_write) -> access_permitted_2 -// (csr_counter_read_fault_priv, -// csr_counter_read_fault_csr_addr) -> csr_counter_read_fault -// interrupt_pending_cur_priv -> interrupt_pending -// mav_read_csr_csr_addr -> mav_read_csr -// (mav_csr_write_csr_addr, -// mav_csr_write_word, -// EN_mav_csr_write) -> mav_csr_write -// (csr_trap_actions_from_priv, -// csr_trap_actions_nmi, -// csr_trap_actions_interrupt, -// csr_trap_actions_exc_code) -> csr_trap_actions -// csr_ret_actions_from_priv -> csr_ret_actions -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_csr_csr_addr, - read_csr, - - read_csr_port2_csr_addr, - read_csr_port2, - - mav_read_csr_csr_addr, - EN_mav_read_csr, - mav_read_csr, - - mav_csr_write_csr_addr, - mav_csr_write_word, - EN_mav_csr_write, - mav_csr_write, - - read_frm, - - ma_update_fcsr_fflags_flags, - EN_ma_update_fcsr_fflags, - - ma_update_mstatus_fs_fs, - EN_ma_update_mstatus_fs, - - read_misa, - - read_mstatus, - - read_sstatus, - - read_ustatus, - - read_satp, - - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_nmi, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval, - EN_csr_trap_actions, - csr_trap_actions, - RDY_csr_trap_actions, - - csr_ret_actions_from_priv, - EN_csr_ret_actions, - csr_ret_actions, - RDY_csr_ret_actions, - - read_csr_minstret, - - EN_csr_minstret_incr, - - read_csr_mcycle, - - read_csr_mtime, - - access_permitted_1_priv, - access_permitted_1_csr_addr, - access_permitted_1_read_not_write, - access_permitted_1, - - access_permitted_2_priv, - access_permitted_2_csr_addr, - access_permitted_2_read_not_write, - access_permitted_2, - - csr_counter_read_fault_priv, - csr_counter_read_fault_csr_addr, - csr_counter_read_fault, - - csr_mip_read, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - interrupt_pending_cur_priv, - interrupt_pending, - - wfi_resume, - - nmi_req_set_not_clear, - - nmi_pending, - - EN_debug, - RDY_debug); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_csr - input [11 : 0] read_csr_csr_addr; - output [32 : 0] read_csr; - - // value method read_csr_port2 - input [11 : 0] read_csr_port2_csr_addr; - output [32 : 0] read_csr_port2; - - // actionvalue method mav_read_csr - input [11 : 0] mav_read_csr_csr_addr; - input EN_mav_read_csr; - output [32 : 0] mav_read_csr; - - // actionvalue method mav_csr_write - input [11 : 0] mav_csr_write_csr_addr; - input [31 : 0] mav_csr_write_word; - input EN_mav_csr_write; - output [31 : 0] mav_csr_write; - - // value method read_frm - output [2 : 0] read_frm; - - // action method ma_update_fcsr_fflags - input [4 : 0] ma_update_fcsr_fflags_flags; - input EN_ma_update_fcsr_fflags; - - // action method ma_update_mstatus_fs - input [1 : 0] ma_update_mstatus_fs_fs; - input EN_ma_update_mstatus_fs; - - // value method read_misa - output [27 : 0] read_misa; - - // value method read_mstatus - output [31 : 0] read_mstatus; - - // value method read_sstatus - output [31 : 0] read_sstatus; - - // value method read_ustatus - output [31 : 0] read_ustatus; - - // value method read_satp - output [31 : 0] read_satp; - - // actionvalue method csr_trap_actions - input [1 : 0] csr_trap_actions_from_priv; - input [31 : 0] csr_trap_actions_pc; - input csr_trap_actions_nmi; - input csr_trap_actions_interrupt; - input [3 : 0] csr_trap_actions_exc_code; - input [31 : 0] csr_trap_actions_xtval; - input EN_csr_trap_actions; - output [97 : 0] csr_trap_actions; - output RDY_csr_trap_actions; - - // actionvalue method csr_ret_actions - input [1 : 0] csr_ret_actions_from_priv; - input EN_csr_ret_actions; - output [65 : 0] csr_ret_actions; - output RDY_csr_ret_actions; - - // value method read_csr_minstret - output [63 : 0] read_csr_minstret; - - // action method csr_minstret_incr - input EN_csr_minstret_incr; - - // value method read_csr_mcycle - output [63 : 0] read_csr_mcycle; - - // value method read_csr_mtime - output [63 : 0] read_csr_mtime; - - // value method access_permitted_1 - input [1 : 0] access_permitted_1_priv; - input [11 : 0] access_permitted_1_csr_addr; - input access_permitted_1_read_not_write; - output access_permitted_1; - - // value method access_permitted_2 - input [1 : 0] access_permitted_2_priv; - input [11 : 0] access_permitted_2_csr_addr; - input access_permitted_2_read_not_write; - output access_permitted_2; - - // value method csr_counter_read_fault - input [1 : 0] csr_counter_read_fault_priv; - input [11 : 0] csr_counter_read_fault_csr_addr; - output csr_counter_read_fault; - - // value method csr_mip_read - output [31 : 0] csr_mip_read; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // value method interrupt_pending - input [1 : 0] interrupt_pending_cur_priv; - output [4 : 0] interrupt_pending; - - // value method wfi_resume - output wfi_resume; - - // action method nmi_req - input nmi_req_set_not_clear; - - // value method nmi_pending - output nmi_pending; - - // action method debug - input EN_debug; - output RDY_debug; - - // signals for module outputs - wire [97 : 0] csr_trap_actions; - wire [65 : 0] csr_ret_actions; - wire [63 : 0] read_csr_mcycle, read_csr_minstret, read_csr_mtime; - wire [32 : 0] mav_read_csr, read_csr, read_csr_port2; - wire [31 : 0] csr_mip_read, - mav_csr_write, - read_mstatus, - read_satp, - read_sstatus, - read_ustatus; - wire [27 : 0] read_misa; - wire [4 : 0] interrupt_pending; - wire [2 : 0] read_frm; - wire RDY_csr_ret_actions, - RDY_csr_trap_actions, - RDY_debug, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - access_permitted_1, - access_permitted_2, - csr_counter_read_fault, - nmi_pending, - wfi_resume; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register csr_mstatus_rg_mstatus - reg [31 : 0] csr_mstatus_rg_mstatus; - reg [31 : 0] csr_mstatus_rg_mstatus$D_IN; - wire csr_mstatus_rg_mstatus$EN; - - // register rg_dcsr - reg [31 : 0] rg_dcsr; - wire [31 : 0] rg_dcsr$D_IN; - wire rg_dcsr$EN; - - // register rg_dpc - reg [31 : 0] rg_dpc; - wire [31 : 0] rg_dpc$D_IN; - wire rg_dpc$EN; - - // register rg_dscratch0 - reg [31 : 0] rg_dscratch0; - wire [31 : 0] rg_dscratch0$D_IN; - wire rg_dscratch0$EN; - - // register rg_dscratch1 - reg [31 : 0] rg_dscratch1; - wire [31 : 0] rg_dscratch1$D_IN; - wire rg_dscratch1$EN; - - // register rg_fflags - reg [4 : 0] rg_fflags; - reg [4 : 0] rg_fflags$D_IN; - wire rg_fflags$EN; - - // register rg_frm - reg [2 : 0] rg_frm; - wire [2 : 0] rg_frm$D_IN; - wire rg_frm$EN; - - // register rg_mcause - reg [4 : 0] rg_mcause; - reg [4 : 0] rg_mcause$D_IN; - wire rg_mcause$EN; - - // register rg_mcounteren - reg [2 : 0] rg_mcounteren; - wire [2 : 0] rg_mcounteren$D_IN; - wire rg_mcounteren$EN; - - // register rg_mcycle - reg [63 : 0] rg_mcycle; - wire [63 : 0] rg_mcycle$D_IN; - wire rg_mcycle$EN; - - // register rg_medeleg - reg [15 : 0] rg_medeleg; - wire [15 : 0] rg_medeleg$D_IN; - wire rg_medeleg$EN; - - // register rg_mepc - reg [31 : 0] rg_mepc; - wire [31 : 0] rg_mepc$D_IN; - wire rg_mepc$EN; - - // register rg_mideleg - reg [11 : 0] rg_mideleg; - wire [11 : 0] rg_mideleg$D_IN; - wire rg_mideleg$EN; - - // register rg_minstret - reg [63 : 0] rg_minstret; - wire [63 : 0] rg_minstret$D_IN; - wire rg_minstret$EN; - - // register rg_mscratch - reg [31 : 0] rg_mscratch; - wire [31 : 0] rg_mscratch$D_IN; - wire rg_mscratch$EN; - - // register rg_mtval - reg [31 : 0] rg_mtval; - wire [31 : 0] rg_mtval$D_IN; - wire rg_mtval$EN; - - // register rg_mtvec - reg [30 : 0] rg_mtvec; - wire [30 : 0] rg_mtvec$D_IN; - wire rg_mtvec$EN; - - // register rg_nmi - reg rg_nmi; - wire rg_nmi$D_IN, rg_nmi$EN; - - // register rg_nmi_vector - reg [31 : 0] rg_nmi_vector; - wire [31 : 0] rg_nmi_vector$D_IN; - wire rg_nmi_vector$EN; - - // register rg_satp - reg [31 : 0] rg_satp; - wire [31 : 0] rg_satp$D_IN; - wire rg_satp$EN; - - // register rg_scause - reg [4 : 0] rg_scause; - reg [4 : 0] rg_scause$D_IN; - wire rg_scause$EN; - - // register rg_sepc - reg [31 : 0] rg_sepc; - wire [31 : 0] rg_sepc$D_IN; - wire rg_sepc$EN; - - // register rg_sscratch - reg [31 : 0] rg_sscratch; - wire [31 : 0] rg_sscratch$D_IN; - wire rg_sscratch$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_stval - reg [31 : 0] rg_stval; - wire [31 : 0] rg_stval$D_IN; - wire rg_stval$EN; - - // register rg_stvec - reg [30 : 0] rg_stvec; - wire [30 : 0] rg_stvec$D_IN; - wire rg_stvec$EN; - - // register rg_tdata1 - reg [31 : 0] rg_tdata1; - wire [31 : 0] rg_tdata1$D_IN; - wire rg_tdata1$EN; - - // register rg_tdata2 - reg [31 : 0] rg_tdata2; - wire [31 : 0] rg_tdata2$D_IN; - wire rg_tdata2$EN; - - // register rg_tdata3 - reg [31 : 0] rg_tdata3; - wire [31 : 0] rg_tdata3$D_IN; - wire rg_tdata3$EN; - - // register rg_tselect - reg [31 : 0] rg_tselect; - wire [31 : 0] rg_tselect$D_IN; - wire rg_tselect$EN; - - // ports of submodule csr_mie - wire [31 : 0] csr_mie$fav_sie_write, - csr_mie$fav_sie_write_wordxl, - csr_mie$fav_write, - csr_mie$fav_write_wordxl, - csr_mie$fv_read, - csr_mie$fv_sie_read; - wire [27 : 0] csr_mie$fav_sie_write_misa, csr_mie$fav_write_misa; - wire csr_mie$EN_fav_sie_write, csr_mie$EN_fav_write, csr_mie$EN_reset; - - // ports of submodule csr_mip - wire [31 : 0] csr_mip$fav_sip_write, - csr_mip$fav_sip_write_wordxl, - csr_mip$fav_write, - csr_mip$fav_write_wordxl, - csr_mip$fv_read, - csr_mip$fv_sip_read; - wire [27 : 0] csr_mip$fav_sip_write_misa, csr_mip$fav_write_misa; - wire csr_mip$EN_fav_sip_write, - csr_mip$EN_fav_write, - csr_mip$EN_reset, - csr_mip$m_external_interrupt_req_req, - csr_mip$s_external_interrupt_req_req, - csr_mip$software_interrupt_req_req, - csr_mip$timer_interrupt_req_req; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mtvec_reset_value, - soc_map$m_nmivec_reset_value; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_mcycle_incr, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_upd_minstret_csrrx, - CAN_FIRE_RL_rl_upd_minstret_incr, - CAN_FIRE_csr_minstret_incr, - CAN_FIRE_csr_ret_actions, - CAN_FIRE_csr_trap_actions, - CAN_FIRE_debug, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_ma_update_fcsr_fflags, - CAN_FIRE_ma_update_mstatus_fs, - CAN_FIRE_mav_csr_write, - CAN_FIRE_mav_read_csr, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_rl_mcycle_incr, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_upd_minstret_csrrx, - WILL_FIRE_RL_rl_upd_minstret_incr, - WILL_FIRE_csr_minstret_incr, - WILL_FIRE_csr_ret_actions, - WILL_FIRE_csr_trap_actions, - WILL_FIRE_debug, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_ma_update_fcsr_fflags, - WILL_FIRE_ma_update_mstatus_fs, - WILL_FIRE_mav_csr_write, - WILL_FIRE_mav_read_csr, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_rg_minstret$write_1__VAL_1, - MUX_rg_minstret$write_1__VAL_2, - MUX_rw_minstret$wset_1__VAL_1; - wire [31 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_2, - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4, - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5; - wire [30 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; - wire [15 : 0] MUX_rg_medeleg$write_1__VAL_1; - wire [4 : 0] MUX_rg_fflags$write_1__VAL_3, - MUX_rg_mcause$write_1__VAL_2, - MUX_rg_mcause$write_1__VAL_3; - wire [2 : 0] MUX_rg_frm$write_1__VAL_1; - wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_5, - MUX_rg_fflags$write_1__SEL_2, - MUX_rg_frm$write_1__SEL_1, - MUX_rg_mcause$write_1__SEL_2, - MUX_rg_mcause$write_1__SEL_3, - MUX_rg_mcounteren$write_1__SEL_1, - MUX_rg_medeleg$write_1__SEL_1, - MUX_rg_mideleg$write_1__SEL_1, - MUX_rg_mtvec$write_1__SEL_1, - MUX_rg_satp$write_1__SEL_1, - MUX_rg_scause$write_1__SEL_2, - MUX_rg_scause$write_1__SEL_3, - MUX_rg_sepc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2, - MUX_rg_stval$write_1__SEL_1, - MUX_rg_stvec$write_1__SEL_1, - MUX_rg_tdata1$write_1__SEL_1, - MUX_rw_minstret$wset_1__SEL_1; - - // remaining internal signals - reg [31 : 0] IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860, - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336, - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598, - y_avValue_fst__h8976; - reg [29 : 0] CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1; - reg CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2, - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990, - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093; - wire [63 : 0] x__h8408, x__h8516; - wire [31 : 0] IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484, - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682, - _theResult___fst__h12935, - _theResult___fst__h13136, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476, - exc_pc___1__h12025, - exc_pc__h11951, - mask__h10973, - mask__h10990, - mask__h12956, - mask__h12973, - result__h8591, - v__h10796, - v__h5698, - v__h5842, - v__h5956, - v__h7081, - v__h7117, - v__h7758, - v__h7820, - v__h7976, - val__h10974, - val__h10991, - val__h12974, - vector_offset__h11952, - wordxl1__h7212, - x__h10972, - x__h10985, - x__h11002, - x__h12806, - x__h12807, - x__h12955, - x__h12968, - x__h12985, - x__h9768, - y__h10986, - y__h11003, - y__h12969, - y__h12986, - y_avValue_fst__h11908, - y_avValue_fst__h11925, - y_avValue_snd_snd__h11998; - wire [22 : 0] fixed_up_val_23__h10840, - fixed_up_val_23__h12869, - fixed_up_val_23__h6007, - fixed_up_val_23__h7253, - fixed_up_val_23__h9209; - wire [5 : 0] ie_from_x__h12919, - ie_to_x__h10890, - pie_from_x__h12920, - pie_to_x__h10891; - wire [3 : 0] IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2171, - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2173, - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2174, - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2176, - exc_code__h12648; - wire [1 : 0] IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906, - _theResult____h14614, - _theResult____h14826, - _theResult____h15038, - _theResult____h15250, - _theResult____h15462, - _theResult____h15674, - _theResult____h15886, - _theResult____h16098, - _theResult____h16310, - _theResult___fst__h10902, - new_priv__h10791, - to_y__h13135; - wire NOT_access_permitted_1_csr_addr_ULT_0xC03_701__ETC___d1821, - NOT_access_permitted_2_csr_addr_ULT_0xC03_826__ETC___d1944, - NOT_cfg_verbosity_read__148_ULE_1_149___d1150, - NOT_csr_mip_fv_read__94_BIT_0_060_151_OR_NOT_c_ETC___d2158, - NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096, - NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123, - NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150, - NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131, - NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104, - NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140, - NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113, - NOT_csr_mip_fv_read__94_BIT_8_049_142_OR_NOT_c_ETC___d2149, - NOT_csr_mip_fv_read__94_BIT_9_016_115_OR_NOT_c_ETC___d2122, - NOT_csr_trap_actions_nmi_499_AND_csr_trap_acti_ETC___d1606, - NOT_mav_csr_write_csr_addr_ULT_0xB03_63_152_AN_ETC___d1159, - b__h10989, - b__h12972, - csr_mip_fv_read__94_BIT_0_060_AND_csr_mie_fv_r_ETC___d2069, - csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d1993, - csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d2059, - csr_mip_fv_read__94_BIT_1_027_AND_csr_mie_fv_r_ETC___d2036, - csr_mip_fv_read__94_BIT_3_994_AND_csr_mie_fv_r_ETC___d2003, - csr_mip_fv_read__94_BIT_4_071_AND_csr_mie_fv_r_ETC___d2080, - csr_mip_fv_read__94_BIT_5_038_AND_csr_mie_fv_r_ETC___d2047, - csr_mip_fv_read__94_BIT_7_005_AND_csr_mie_fv_r_ETC___d2014, - csr_mip_fv_read__94_BIT_8_049_AND_csr_mie_fv_r_ETC___d2058, - csr_mip_fv_read__94_BIT_9_016_AND_csr_mie_fv_r_ETC___d2025, - csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1508, - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1657, - deleg_bit___1__h10911, - deleg_bit___1__h10926, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065, - mav_csr_write_csr_addr_ULE_0x33F___d872, - mav_csr_write_csr_addr_ULE_0xB1F___d864, - mav_csr_write_csr_addr_ULE_0xB9F___d868, - mav_csr_write_csr_addr_ULT_0x323_71_OR_NOT_mav_ETC___d1145, - mav_csr_write_csr_addr_ULT_0x323___d871, - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d1147, - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876, - mav_csr_write_csr_addr_ULT_0xB03___d863, - mav_csr_write_csr_addr_ULT_0xB83___d867, - sd__h10839, - sd__h12868, - sd__h7252, - sd__h9208; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_csr - assign read_csr = - { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hC83 && read_csr_csr_addr <= 12'hC9F || - read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'hB83 && read_csr_csr_addr <= 12'hB9F || - read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || - read_csr_csr_addr == 12'h001 || - read_csr_csr_addr == 12'h002 || - read_csr_csr_addr == 12'h003 || - read_csr_csr_addr == 12'hC00 || - read_csr_csr_addr == 12'hC02 || - read_csr_csr_addr == 12'hC80 || - read_csr_csr_addr == 12'hC82 || - read_csr_csr_addr == 12'h100 || - read_csr_csr_addr == 12'h102 || - read_csr_csr_addr == 12'h103 || - read_csr_csr_addr == 12'h104 || - read_csr_csr_addr == 12'h105 || - read_csr_csr_addr == 12'h106 || - read_csr_csr_addr == 12'h140 || - read_csr_csr_addr == 12'h141 || - read_csr_csr_addr == 12'h142 || - read_csr_csr_addr == 12'h143 || - read_csr_csr_addr == 12'h144 || - read_csr_csr_addr == 12'h180 || - read_csr_csr_addr == 12'h302 || - read_csr_csr_addr == 12'h303 || - read_csr_csr_addr == 12'hF11 || - read_csr_csr_addr == 12'hF12 || - read_csr_csr_addr == 12'hF13 || - read_csr_csr_addr == 12'hF14 || - read_csr_csr_addr == 12'h300 || - read_csr_csr_addr == 12'h301 || - read_csr_csr_addr == 12'h304 || - read_csr_csr_addr == 12'h305 || - read_csr_csr_addr == 12'h306 || - read_csr_csr_addr == 12'h340 || - read_csr_csr_addr == 12'h341 || - read_csr_csr_addr == 12'h342 || - read_csr_csr_addr == 12'h343 || - read_csr_csr_addr == 12'h344 || - read_csr_csr_addr == 12'hB00 || - read_csr_csr_addr == 12'hB02 || - read_csr_csr_addr == 12'hB80 || - read_csr_csr_addr == 12'hB82 || - read_csr_csr_addr == 12'h7A0 || - read_csr_csr_addr == 12'h7A1 || - read_csr_csr_addr == 12'h7A2 || - read_csr_csr_addr == 12'h7A3, - (read_csr_csr_addr >= 12'hC03 && - read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hC83 && - read_csr_csr_addr <= 12'hC9F || - read_csr_csr_addr >= 12'hB03 && - read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'hB83 && - read_csr_csr_addr <= 12'hB9F || - read_csr_csr_addr >= 12'h323 && - read_csr_csr_addr <= 12'h33F) ? - 32'd0 : - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 } ; - - // value method read_csr_port2 - assign read_csr_port2 = - { read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hC83 && - read_csr_port2_csr_addr <= 12'hC9F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'hB83 && - read_csr_port2_csr_addr <= 12'hB9F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F || - read_csr_port2_csr_addr == 12'h001 || - read_csr_port2_csr_addr == 12'h002 || - read_csr_port2_csr_addr == 12'h003 || - read_csr_port2_csr_addr == 12'hC00 || - read_csr_port2_csr_addr == 12'hC02 || - read_csr_port2_csr_addr == 12'hC80 || - read_csr_port2_csr_addr == 12'hC82 || - read_csr_port2_csr_addr == 12'h100 || - read_csr_port2_csr_addr == 12'h102 || - read_csr_port2_csr_addr == 12'h103 || - read_csr_port2_csr_addr == 12'h104 || - read_csr_port2_csr_addr == 12'h105 || - read_csr_port2_csr_addr == 12'h106 || - read_csr_port2_csr_addr == 12'h140 || - read_csr_port2_csr_addr == 12'h141 || - read_csr_port2_csr_addr == 12'h142 || - read_csr_port2_csr_addr == 12'h143 || - read_csr_port2_csr_addr == 12'h144 || - read_csr_port2_csr_addr == 12'h180 || - read_csr_port2_csr_addr == 12'h302 || - read_csr_port2_csr_addr == 12'h303 || - read_csr_port2_csr_addr == 12'hF11 || - read_csr_port2_csr_addr == 12'hF12 || - read_csr_port2_csr_addr == 12'hF13 || - read_csr_port2_csr_addr == 12'hF14 || - read_csr_port2_csr_addr == 12'h300 || - read_csr_port2_csr_addr == 12'h301 || - read_csr_port2_csr_addr == 12'h304 || - read_csr_port2_csr_addr == 12'h305 || - read_csr_port2_csr_addr == 12'h306 || - read_csr_port2_csr_addr == 12'h340 || - read_csr_port2_csr_addr == 12'h341 || - read_csr_port2_csr_addr == 12'h342 || - read_csr_port2_csr_addr == 12'h343 || - read_csr_port2_csr_addr == 12'h344 || - read_csr_port2_csr_addr == 12'hB00 || - read_csr_port2_csr_addr == 12'hB02 || - read_csr_port2_csr_addr == 12'hB80 || - read_csr_port2_csr_addr == 12'hB82 || - read_csr_port2_csr_addr == 12'h7A0 || - read_csr_port2_csr_addr == 12'h7A1 || - read_csr_port2_csr_addr == 12'h7A2 || - read_csr_port2_csr_addr == 12'h7A3, - (read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hC83 && - read_csr_port2_csr_addr <= 12'hC9F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'hB83 && - read_csr_port2_csr_addr <= 12'hB9F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F) ? - 32'd0 : - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 } ; - - // actionvalue method mav_read_csr - assign mav_read_csr = - { mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hC83 && - mav_read_csr_csr_addr <= 12'hC9F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'hB83 && - mav_read_csr_csr_addr <= 12'hB9F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F || - mav_read_csr_csr_addr == 12'h001 || - mav_read_csr_csr_addr == 12'h002 || - mav_read_csr_csr_addr == 12'h003 || - mav_read_csr_csr_addr == 12'hC00 || - mav_read_csr_csr_addr == 12'hC02 || - mav_read_csr_csr_addr == 12'hC80 || - mav_read_csr_csr_addr == 12'hC82 || - mav_read_csr_csr_addr == 12'h100 || - mav_read_csr_csr_addr == 12'h102 || - mav_read_csr_csr_addr == 12'h103 || - mav_read_csr_csr_addr == 12'h104 || - mav_read_csr_csr_addr == 12'h105 || - mav_read_csr_csr_addr == 12'h106 || - mav_read_csr_csr_addr == 12'h140 || - mav_read_csr_csr_addr == 12'h141 || - mav_read_csr_csr_addr == 12'h142 || - mav_read_csr_csr_addr == 12'h143 || - mav_read_csr_csr_addr == 12'h144 || - mav_read_csr_csr_addr == 12'h180 || - mav_read_csr_csr_addr == 12'h302 || - mav_read_csr_csr_addr == 12'h303 || - mav_read_csr_csr_addr == 12'hF11 || - mav_read_csr_csr_addr == 12'hF12 || - mav_read_csr_csr_addr == 12'hF13 || - mav_read_csr_csr_addr == 12'hF14 || - mav_read_csr_csr_addr == 12'h300 || - mav_read_csr_csr_addr == 12'h301 || - mav_read_csr_csr_addr == 12'h304 || - mav_read_csr_csr_addr == 12'h305 || - mav_read_csr_csr_addr == 12'h306 || - mav_read_csr_csr_addr == 12'h340 || - mav_read_csr_csr_addr == 12'h341 || - mav_read_csr_csr_addr == 12'h342 || - mav_read_csr_csr_addr == 12'h343 || - mav_read_csr_csr_addr == 12'h344 || - mav_read_csr_csr_addr == 12'hB00 || - mav_read_csr_csr_addr == 12'hB02 || - mav_read_csr_csr_addr == 12'hB80 || - mav_read_csr_csr_addr == 12'hB82 || - mav_read_csr_csr_addr == 12'h7A0 || - mav_read_csr_csr_addr == 12'h7A1 || - mav_read_csr_csr_addr == 12'h7A2 || - mav_read_csr_csr_addr == 12'h7A3, - (mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hC83 && - mav_read_csr_csr_addr <= 12'hC9F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'hB83 && - mav_read_csr_csr_addr <= 12'hB9F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F) ? - 32'd0 : - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 } ; - assign CAN_FIRE_mav_read_csr = 1'd1 ; - assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; - - // actionvalue method mav_csr_write - assign mav_csr_write = - NOT_mav_csr_write_csr_addr_ULT_0xB03_63_152_AN_ETC___d1159 ? - 32'd0 : - y_avValue_fst__h8976 ; - assign CAN_FIRE_mav_csr_write = 1'd1 ; - assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; - - // value method read_frm - assign read_frm = rg_frm ; - - // action method ma_update_fcsr_fflags - assign CAN_FIRE_ma_update_fcsr_fflags = 1'd1 ; - assign WILL_FIRE_ma_update_fcsr_fflags = EN_ma_update_fcsr_fflags ; - - // action method ma_update_mstatus_fs - assign CAN_FIRE_ma_update_mstatus_fs = 1'd1 ; - assign WILL_FIRE_ma_update_mstatus_fs = EN_ma_update_mstatus_fs ; - - // value method read_misa - assign read_misa = 28'd68423981 ; - - // value method read_mstatus - assign read_mstatus = csr_mstatus_rg_mstatus ; - - // value method read_sstatus - assign read_sstatus = - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] } ; - - // value method read_ustatus - assign read_ustatus = - { 27'd0, - csr_mstatus_rg_mstatus[4], - 3'd0, - csr_mstatus_rg_mstatus[0] } ; - - // value method read_satp - assign read_satp = rg_satp ; - - // actionvalue method csr_trap_actions - assign csr_trap_actions = - { x__h9768, x__h12806, x__h12807, new_priv__h10791 } ; - assign RDY_csr_trap_actions = 1'd1 ; - assign CAN_FIRE_csr_trap_actions = 1'd1 ; - assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; - - // actionvalue method csr_ret_actions - assign csr_ret_actions = - (csr_ret_actions_from_priv == 2'b11) ? - { rg_mepc, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[12:11], - _theResult___fst__h12935 } : - { rg_sepc, to_y__h13135, _theResult___fst__h13136 } ; - assign RDY_csr_ret_actions = 1'd1 ; - assign CAN_FIRE_csr_ret_actions = 1'd1 ; - assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; - - // value method read_csr_minstret - assign read_csr_minstret = rg_minstret ; - - // action method csr_minstret_incr - assign CAN_FIRE_csr_minstret_incr = 1'd1 ; - assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; - - // value method read_csr_mcycle - assign read_csr_mcycle = rg_mcycle ; - - // value method read_csr_mtime - assign read_csr_mtime = rg_mcycle ; - - // value method access_permitted_1 - assign access_permitted_1 = - NOT_access_permitted_1_csr_addr_ULT_0xC03_701__ETC___d1821 && - (access_permitted_1_read_not_write || - access_permitted_1_csr_addr[11:10] != 2'b11) ; - - // value method access_permitted_2 - assign access_permitted_2 = - NOT_access_permitted_2_csr_addr_ULT_0xC03_826__ETC___d1944 && - (access_permitted_2_read_not_write || - access_permitted_2_csr_addr[11:10] != 2'b11) ; - - // value method csr_counter_read_fault - assign csr_counter_read_fault = - (csr_counter_read_fault_priv == 2'b01 || - csr_counter_read_fault_priv == 2'b0) && - (csr_counter_read_fault_csr_addr == 12'hC00 && - !rg_mcounteren[0] || - csr_counter_read_fault_csr_addr == 12'hC01 && - !rg_mcounteren[1] || - csr_counter_read_fault_csr_addr == 12'hC02 && - !rg_mcounteren[2] || - csr_counter_read_fault_csr_addr >= 12'hC03 && - csr_counter_read_fault_csr_addr <= 12'hC1F || - csr_counter_read_fault_csr_addr >= 12'hC83 && - csr_counter_read_fault_csr_addr <= 12'hC9F) ; - - // value method csr_mip_read - assign csr_mip_read = csr_mip$fv_read ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // value method interrupt_pending - assign interrupt_pending = - { csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d2059 || - csr_mip_fv_read__94_BIT_0_060_AND_csr_mie_fv_r_ETC___d2069 || - csr_mip_fv_read__94_BIT_4_071_AND_csr_mie_fv_r_ETC___d2080, - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2176 } ; - - // value method wfi_resume - assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 32'd0 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // value method nmi_pending - assign nmi_pending = rg_nmi ; - - // action method debug - assign RDY_debug = 1'd1 ; - assign CAN_FIRE_debug = 1'd1 ; - assign WILL_FIRE_debug = EN_debug ; - - // submodule csr_mie - mkCSR_MIE csr_mie(.CLK(CLK), - .RST_N(RST_N), - .fav_sie_write_misa(csr_mie$fav_sie_write_misa), - .fav_sie_write_wordxl(csr_mie$fav_sie_write_wordxl), - .fav_write_misa(csr_mie$fav_write_misa), - .fav_write_wordxl(csr_mie$fav_write_wordxl), - .EN_reset(csr_mie$EN_reset), - .EN_fav_write(csr_mie$EN_fav_write), - .EN_fav_sie_write(csr_mie$EN_fav_sie_write), - .fv_read(csr_mie$fv_read), - .fav_write(csr_mie$fav_write), - .fv_sie_read(csr_mie$fv_sie_read), - .fav_sie_write(csr_mie$fav_sie_write)); - - // submodule csr_mip - mkCSR_MIP csr_mip(.CLK(CLK), - .RST_N(RST_N), - .fav_sip_write_misa(csr_mip$fav_sip_write_misa), - .fav_sip_write_wordxl(csr_mip$fav_sip_write_wordxl), - .fav_write_misa(csr_mip$fav_write_misa), - .fav_write_wordxl(csr_mip$fav_write_wordxl), - .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), - .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), - .software_interrupt_req_req(csr_mip$software_interrupt_req_req), - .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), - .EN_reset(csr_mip$EN_reset), - .EN_fav_write(csr_mip$EN_fav_write), - .EN_fav_sip_write(csr_mip$EN_fav_sip_write), - .fv_read(csr_mip$fv_read), - .fav_write(csr_mip$fav_write), - .fv_sip_read(csr_mip$fv_sip_read), - .fav_sip_write(csr_mip$fav_sip_write)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), - .m_nmivec_reset_value(soc_map$m_nmivec_reset_value)); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = !rg_state ; - assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_mcycle_incr - assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; - assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; - - // rule RL_rl_upd_minstret_csrrx - assign CAN_FIRE_RL_rl_upd_minstret_csrrx = - MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; - assign WILL_FIRE_RL_rl_upd_minstret_csrrx = - CAN_FIRE_RL_rl_upd_minstret_csrrx ; - - // rule RL_rl_upd_minstret_incr - assign CAN_FIRE_RL_rl_upd_minstret_incr = - !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; - assign WILL_FIRE_RL_rl_upd_minstret_incr = - CAN_FIRE_RL_rl_upd_minstret_incr ; - - // inputs to muxes for submodule ports - assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h100 || - mav_csr_write_csr_addr == 12'h300) ; - assign MUX_rg_fflags$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h001 || - mav_csr_write_csr_addr == 12'h003) ; - assign MUX_rg_frm$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h002 || - mav_csr_write_csr_addr == 12'h003) ; - assign MUX_rg_mcause$write_1__SEL_2 = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) ; - assign MUX_rg_mcause$write_1__SEL_3 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h342 ; - assign MUX_rg_mcounteren$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h306 ; - assign MUX_rg_medeleg$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h302 ; - assign MUX_rg_mideleg$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h303 ; - assign MUX_rg_mtvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h305 ; - assign MUX_rg_satp$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h180 ; - assign MUX_rg_scause$write_1__SEL_2 = - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h10791 == 2'b01 ; - assign MUX_rg_scause$write_1__SEL_3 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h142 ; - assign MUX_rg_sepc$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h141 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; - assign MUX_rg_stval$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h143 ; - assign MUX_rg_stvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h105 ; - assign MUX_rg_tdata1$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h7A1 ; - assign MUX_rw_minstret$wset_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'hB02 || - mav_csr_write_csr_addr == 12'hB82) ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 = - { sd__h12868, 8'd0, fixed_up_val_23__h12869 } ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 = - { sd__h9208, 8'd0, fixed_up_val_23__h9209 } ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_5 = - { sd__h7252, - 8'd0, - (mav_csr_write_csr_addr == 12'h100) ? - fixed_up_val_23__h6007 : - fixed_up_val_23__h7253 } ; - assign MUX_rg_fflags$write_1__VAL_3 = - rg_fflags | ma_update_fcsr_fflags_flags ; - assign MUX_rg_frm$write_1__VAL_1 = - (mav_csr_write_csr_addr == 12'h002) ? - mav_csr_write_word[2:0] : - mav_csr_write_word[7:5] ; - assign MUX_rg_mcause$write_1__VAL_2 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - exc_code__h12648 } ; - assign MUX_rg_mcause$write_1__VAL_3 = - { mav_csr_write_word[31], mav_csr_write_word[3:0] } ; - assign MUX_rg_medeleg$write_1__VAL_1 = - { mav_csr_write_word[15], - 1'd0, - mav_csr_write_word[13:12], - 2'd0, - mav_csr_write_word[9:0] } ; - assign MUX_rg_minstret$write_1__VAL_1 = - MUX_rw_minstret$wset_1__SEL_1 ? - MUX_rw_minstret$wset_1__VAL_1 : - 64'd0 ; - assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; - assign MUX_rg_mtvec$write_1__VAL_1 = - { mav_csr_write_word[31:2], mav_csr_write_word[0] } ; - assign MUX_rg_mtvec$write_1__VAL_2 = - { soc_map$m_mtvec_reset_value[31:2], - soc_map$m_mtvec_reset_value[0] } ; - assign MUX_rw_minstret$wset_1__VAL_1 = - (mav_csr_write_csr_addr == 12'hB02) ? x__h8408 : x__h8516 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register csr_mstatus_rg_mstatus - always@(WILL_FIRE_RL_rl_reset_start or - EN_csr_ret_actions or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 or - EN_csr_trap_actions or - v__h10796 or - EN_ma_update_mstatus_fs or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 or - MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: csr_mstatus_rg_mstatus$D_IN = 32'd8192; - EN_csr_ret_actions: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_2; - EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = v__h10796; - EN_ma_update_mstatus_fs: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4; - MUX_csr_mstatus_rg_mstatus$write_1__SEL_5: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5; - default: csr_mstatus_rg_mstatus$D_IN = - 32'hAAAAAAAA /* unspecified value */ ; - endcase - assign csr_mstatus_rg_mstatus$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h100 || - mav_csr_write_csr_addr == 12'h300) || - EN_csr_trap_actions || - EN_ma_update_mstatus_fs || - EN_csr_ret_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_dcsr - assign rg_dcsr$D_IN = 32'h0 ; - assign rg_dcsr$EN = 1'b0 ; - - // register rg_dpc - assign rg_dpc$D_IN = 32'h0 ; - assign rg_dpc$EN = 1'b0 ; - - // register rg_dscratch0 - assign rg_dscratch0$D_IN = 32'h0 ; - assign rg_dscratch0$EN = 1'b0 ; - - // register rg_dscratch1 - assign rg_dscratch1$D_IN = 32'h0 ; - assign rg_dscratch1$EN = 1'b0 ; - - // register rg_fflags - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_fflags$write_1__SEL_2 or - mav_csr_write_word or - EN_ma_update_fcsr_fflags or MUX_rg_fflags$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_fflags$D_IN = 5'd0; - MUX_rg_fflags$write_1__SEL_2: rg_fflags$D_IN = mav_csr_write_word[4:0]; - EN_ma_update_fcsr_fflags: rg_fflags$D_IN = MUX_rg_fflags$write_1__VAL_3; - default: rg_fflags$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_fflags$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h001 || - mav_csr_write_csr_addr == 12'h003) || - EN_ma_update_fcsr_fflags || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_frm - assign rg_frm$D_IN = - MUX_rg_frm$write_1__SEL_1 ? MUX_rg_frm$write_1__VAL_1 : 3'd0 ; - assign rg_frm$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - (mav_csr_write_csr_addr == 12'h002 || - mav_csr_write_csr_addr == 12'h003) || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_mcause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - MUX_rg_mcause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; - MUX_rg_mcause$write_1__SEL_2: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; - MUX_rg_mcause$write_1__SEL_3: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_mcause$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h342 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcounteren - assign rg_mcounteren$D_IN = - MUX_rg_mcounteren$write_1__SEL_1 ? - mav_csr_write_word[2:0] : - 3'd0 ; - assign rg_mcounteren$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h306 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcycle - assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; - assign rg_mcycle$EN = 1'd1 ; - - // register rg_medeleg - assign rg_medeleg$D_IN = - MUX_rg_medeleg$write_1__SEL_1 ? - MUX_rg_medeleg$write_1__VAL_1 : - 16'd0 ; - assign rg_medeleg$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h302 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mepc - assign rg_mepc$D_IN = - MUX_rg_mcause$write_1__SEL_2 ? - csr_trap_actions_pc : - mav_csr_write_word ; - assign rg_mepc$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h341 ; - - // register rg_mideleg - assign rg_mideleg$D_IN = - MUX_rg_mideleg$write_1__SEL_1 ? - mav_csr_write_word[11:0] : - 12'd0 ; - assign rg_mideleg$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h303 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_minstret - assign rg_minstret$D_IN = - WILL_FIRE_RL_rl_upd_minstret_csrrx ? - MUX_rg_minstret$write_1__VAL_1 : - MUX_rg_minstret$write_1__VAL_2 ; - assign rg_minstret$EN = - WILL_FIRE_RL_rl_upd_minstret_csrrx || - WILL_FIRE_RL_rl_upd_minstret_incr ; - - // register rg_mscratch - assign rg_mscratch$D_IN = mav_csr_write_word ; - assign rg_mscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h340 ; - - // register rg_mtval - assign rg_mtval$D_IN = - MUX_rg_mcause$write_1__SEL_2 ? - csr_trap_actions_xtval : - mav_csr_write_word ; - assign rg_mtval$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h343 ; - - // register rg_mtvec - assign rg_mtvec$D_IN = - MUX_rg_mtvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_mtvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h305 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_nmi - assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ; - assign rg_nmi$EN = 1'b1 ; - - // register rg_nmi_vector - assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value[31:0] ; - assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_satp - assign rg_satp$D_IN = - MUX_rg_satp$write_1__SEL_1 ? mav_csr_write_word : 32'd0 ; - assign rg_satp$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h180 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_scause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_scause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - MUX_rg_scause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_scause$D_IN = 5'd0; - MUX_rg_scause$write_1__SEL_2: - rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_2; - MUX_rg_scause$write_1__SEL_3: - rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_scause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_scause$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h142 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h10791 == 2'b01 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_sepc - assign rg_sepc$D_IN = - MUX_rg_sepc$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_pc ; - assign rg_sepc$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h141 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h10791 == 2'b01 ; - - // register rg_sscratch - assign rg_sscratch$D_IN = mav_csr_write_word ; - assign rg_sscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h140 ; - - // register rg_state - assign rg_state$D_IN = !EN_server_reset_request_put ; - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; - - // register rg_stval - assign rg_stval$D_IN = - MUX_rg_stval$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_xtval ; - assign rg_stval$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h143 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h10791 == 2'b01 ; - - // register rg_stvec - assign rg_stvec$D_IN = - MUX_rg_stvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_stvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h105 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata1 - assign rg_tdata1$D_IN = - MUX_rg_tdata1$write_1__SEL_1 ? result__h8591 : 32'd0 ; - assign rg_tdata1$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h7A1 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata2 - assign rg_tdata2$D_IN = mav_csr_write_word ; - assign rg_tdata2$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h7A2 ; - - // register rg_tdata3 - assign rg_tdata3$D_IN = mav_csr_write_word ; - assign rg_tdata3$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h7A3 ; - - // register rg_tselect - assign rg_tselect$D_IN = 32'd0 ; - assign rg_tselect$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h7A0 || - WILL_FIRE_RL_rl_reset_start ; - - // submodule csr_mie - assign csr_mie$fav_sie_write_misa = 28'd68423981 ; - assign csr_mie$fav_sie_write_wordxl = mav_csr_write_word ; - assign csr_mie$fav_write_misa = 28'd68423981 ; - assign csr_mie$fav_write_wordxl = mav_csr_write_word ; - assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mie$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h304 ; - assign csr_mie$EN_fav_sie_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h104 ; - - // submodule csr_mip - assign csr_mip$fav_sip_write_misa = 28'd68423981 ; - assign csr_mip$fav_sip_write_wordxl = mav_csr_write_word ; - assign csr_mip$fav_write_misa = 28'd68423981 ; - assign csr_mip$fav_write_wordxl = mav_csr_write_word ; - assign csr_mip$m_external_interrupt_req_req = - m_external_interrupt_req_set_not_clear ; - assign csr_mip$s_external_interrupt_req_req = - s_external_interrupt_req_set_not_clear ; - assign csr_mip$software_interrupt_req_req = - software_interrupt_req_set_not_clear ; - assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; - assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mip$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h344 ; - assign csr_mip$EN_fav_sip_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 && - mav_csr_write_csr_addr == 12'h144 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484 = - (new_priv__h10791 == 2'b11) ? - { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[31:13], - csr_trap_actions_from_priv, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[10:0] } : - { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[31:9], - csr_trap_actions_from_priv[0], - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476[7:0] } ; - assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2171 = - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 && - NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104 && - NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113) ? - 4'd9 : - ((NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 && - NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104) ? - 4'd7 : - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 ? - 4'd3 : - 4'd11)) ; - assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2173 = - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 && - NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131) ? - 4'd5 : - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 ? - 4'd1 : - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2171) ; - assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2174 = - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 && - NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131 && - NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140) ? - 4'd8 : - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2173 ; - assign IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2176 = - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150 && - NOT_csr_mip_fv_read__94_BIT_0_060_151_OR_NOT_c_ETC___d2158) ? - 4'd4 : - (NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150 ? - 4'd0 : - IF_NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_N_ETC___d2174) ; - assign IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906 = - (csr_mstatus_rg_mstatus[12:11] == 2'b10) ? - 2'b01 : - csr_mstatus_rg_mstatus[12:11] ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682 = - (csr_ret_actions_from_priv == 2'b11) ? - _theResult___fst__h12935 : - _theResult___fst__h13136 ; - assign NOT_access_permitted_1_csr_addr_ULT_0xC03_701__ETC___d1821 = - (access_permitted_1_csr_addr >= 12'hC03 && - access_permitted_1_csr_addr <= 12'hC1F || - access_permitted_1_csr_addr >= 12'hB03 && - access_permitted_1_csr_addr <= 12'hB1F || - access_permitted_1_csr_addr >= 12'hC83 && - access_permitted_1_csr_addr <= 12'hC9F || - access_permitted_1_csr_addr >= 12'hB83 && - access_permitted_1_csr_addr <= 12'hB9F || - access_permitted_1_csr_addr >= 12'h323 && - access_permitted_1_csr_addr <= 12'h33F || - access_permitted_1_csr_addr == 12'h001 || - access_permitted_1_csr_addr == 12'h002 || - access_permitted_1_csr_addr == 12'h003 || - access_permitted_1_csr_addr == 12'hC00 || - access_permitted_1_csr_addr == 12'hC02 || - access_permitted_1_csr_addr == 12'hC80 || - access_permitted_1_csr_addr == 12'hC81 || - access_permitted_1_csr_addr == 12'hC82 || - access_permitted_1_csr_addr == 12'h100 || - access_permitted_1_csr_addr == 12'h102 || - access_permitted_1_csr_addr == 12'h103 || - access_permitted_1_csr_addr == 12'h104 || - access_permitted_1_csr_addr == 12'h105 || - access_permitted_1_csr_addr == 12'h106 || - access_permitted_1_csr_addr == 12'h140 || - access_permitted_1_csr_addr == 12'h141 || - access_permitted_1_csr_addr == 12'h142 || - access_permitted_1_csr_addr == 12'h143 || - access_permitted_1_csr_addr == 12'h144 || - access_permitted_1_csr_addr == 12'h180 || - access_permitted_1_csr_addr == 12'h302 || - access_permitted_1_csr_addr == 12'h303 || - access_permitted_1_csr_addr == 12'hF11 || - access_permitted_1_csr_addr == 12'hF12 || - access_permitted_1_csr_addr == 12'hF13 || - access_permitted_1_csr_addr == 12'hF14 || - access_permitted_1_csr_addr == 12'h300 || - access_permitted_1_csr_addr == 12'h301 || - access_permitted_1_csr_addr == 12'h304 || - access_permitted_1_csr_addr == 12'h305 || - access_permitted_1_csr_addr == 12'h306 || - access_permitted_1_csr_addr == 12'h340 || - access_permitted_1_csr_addr == 12'h341 || - access_permitted_1_csr_addr == 12'h342 || - access_permitted_1_csr_addr == 12'h343 || - access_permitted_1_csr_addr == 12'h344 || - access_permitted_1_csr_addr == 12'hB00 || - access_permitted_1_csr_addr == 12'hB02 || - access_permitted_1_csr_addr == 12'hB80 || - access_permitted_1_csr_addr == 12'hB82 || - access_permitted_1_csr_addr == 12'h7A0 || - access_permitted_1_csr_addr == 12'h7A1 || - access_permitted_1_csr_addr == 12'h7A2 || - access_permitted_1_csr_addr == 12'h7A3) && - access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && - (access_permitted_1_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_access_permitted_2_csr_addr_ULT_0xC03_826__ETC___d1944 = - (access_permitted_2_csr_addr >= 12'hC03 && - access_permitted_2_csr_addr <= 12'hC1F || - access_permitted_2_csr_addr >= 12'hB03 && - access_permitted_2_csr_addr <= 12'hB1F || - access_permitted_2_csr_addr >= 12'hC83 && - access_permitted_2_csr_addr <= 12'hC9F || - access_permitted_2_csr_addr >= 12'hB83 && - access_permitted_2_csr_addr <= 12'hB9F || - access_permitted_2_csr_addr >= 12'h323 && - access_permitted_2_csr_addr <= 12'h33F || - access_permitted_2_csr_addr == 12'h001 || - access_permitted_2_csr_addr == 12'h002 || - access_permitted_2_csr_addr == 12'h003 || - access_permitted_2_csr_addr == 12'hC00 || - access_permitted_2_csr_addr == 12'hC02 || - access_permitted_2_csr_addr == 12'hC80 || - access_permitted_2_csr_addr == 12'hC81 || - access_permitted_2_csr_addr == 12'hC82 || - access_permitted_2_csr_addr == 12'h100 || - access_permitted_2_csr_addr == 12'h102 || - access_permitted_2_csr_addr == 12'h103 || - access_permitted_2_csr_addr == 12'h104 || - access_permitted_2_csr_addr == 12'h105 || - access_permitted_2_csr_addr == 12'h106 || - access_permitted_2_csr_addr == 12'h140 || - access_permitted_2_csr_addr == 12'h141 || - access_permitted_2_csr_addr == 12'h142 || - access_permitted_2_csr_addr == 12'h143 || - access_permitted_2_csr_addr == 12'h144 || - access_permitted_2_csr_addr == 12'h180 || - access_permitted_2_csr_addr == 12'h302 || - access_permitted_2_csr_addr == 12'h303 || - access_permitted_2_csr_addr == 12'hF11 || - access_permitted_2_csr_addr == 12'hF12 || - access_permitted_2_csr_addr == 12'hF13 || - access_permitted_2_csr_addr == 12'hF14 || - access_permitted_2_csr_addr == 12'h300 || - access_permitted_2_csr_addr == 12'h301 || - access_permitted_2_csr_addr == 12'h304 || - access_permitted_2_csr_addr == 12'h305 || - access_permitted_2_csr_addr == 12'h306 || - access_permitted_2_csr_addr == 12'h340 || - access_permitted_2_csr_addr == 12'h341 || - access_permitted_2_csr_addr == 12'h342 || - access_permitted_2_csr_addr == 12'h343 || - access_permitted_2_csr_addr == 12'h344 || - access_permitted_2_csr_addr == 12'hB00 || - access_permitted_2_csr_addr == 12'hB02 || - access_permitted_2_csr_addr == 12'hB80 || - access_permitted_2_csr_addr == 12'hB82 || - access_permitted_2_csr_addr == 12'h7A0 || - access_permitted_2_csr_addr == 12'h7A1 || - access_permitted_2_csr_addr == 12'h7A2 || - access_permitted_2_csr_addr == 12'h7A3) && - access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && - (access_permitted_2_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_cfg_verbosity_read__148_ULE_1_149___d1150 = - cfg_verbosity > 4'd1 ; - assign NOT_csr_mip_fv_read__94_BIT_0_060_151_OR_NOT_c_ETC___d2158 = - !csr_mip$fv_read[0] || !csr_mie$fv_read[0] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 = - !csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 = - NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2096 && - NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104 && - NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113 && - NOT_csr_mip_fv_read__94_BIT_9_016_115_OR_NOT_c_ETC___d2122 ; - assign NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2150 = - NOT_csr_mip_fv_read__94_BIT_11_976_082_OR_NOT__ETC___d2123 && - NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131 && - NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140 && - NOT_csr_mip_fv_read__94_BIT_8_049_142_OR_NOT_c_ETC___d2149 ; - assign NOT_csr_mip_fv_read__94_BIT_1_027_124_OR_NOT_c_ETC___d2131 = - !csr_mip$fv_read[1] || !csr_mie$fv_read[1] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_3_994_097_OR_NOT_c_ETC___d2104 = - !csr_mip$fv_read[3] || !csr_mie$fv_read[3] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_5_038_133_OR_NOT_c_ETC___d2140 = - !csr_mip$fv_read[5] || !csr_mie$fv_read[5] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_7_005_106_OR_NOT_c_ETC___d2113 = - !csr_mip$fv_read[7] || !csr_mie$fv_read[7] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_8_049_142_OR_NOT_c_ETC___d2149 = - !csr_mip$fv_read[8] || !csr_mie$fv_read[8] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_mip_fv_read__94_BIT_9_016_115_OR_NOT_c_ETC___d2122 = - !csr_mip$fv_read[9] || !csr_mie$fv_read[9] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022 || - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093) ; - assign NOT_csr_trap_actions_nmi_499_AND_csr_trap_acti_ETC___d1606 = - !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h12648 != 4'd0 && - exc_code__h12648 != 4'd1 && - exc_code__h12648 != 4'd2 && - exc_code__h12648 != 4'd3 && - exc_code__h12648 != 4'd4 && - exc_code__h12648 != 4'd5 && - exc_code__h12648 != 4'd6 && - exc_code__h12648 != 4'd7 && - exc_code__h12648 != 4'd8 && - exc_code__h12648 != 4'd9 && - exc_code__h12648 != 4'd10 && - exc_code__h12648 != 4'd11 ; - assign NOT_mav_csr_write_csr_addr_ULT_0xB03_63_152_AN_ETC___d1159 = - !mav_csr_write_csr_addr_ULT_0xB03___d863 && - mav_csr_write_csr_addr_ULE_0xB1F___d864 || - !mav_csr_write_csr_addr_ULT_0xB83___d867 && - mav_csr_write_csr_addr_ULE_0xB9F___d868 || - !mav_csr_write_csr_addr_ULT_0x323___d871 && - mav_csr_write_csr_addr_ULE_0x33F___d872 ; - assign _theResult____h14614 = rg_mideleg[11] ? 2'b01 : 2'b11 ; - assign _theResult____h14826 = rg_mideleg[3] ? 2'b01 : 2'b11 ; - assign _theResult____h15038 = rg_mideleg[7] ? 2'b01 : 2'b11 ; - assign _theResult____h15250 = rg_mideleg[9] ? 2'b01 : 2'b11 ; - assign _theResult____h15462 = rg_mideleg[1] ? 2'b01 : 2'b11 ; - assign _theResult____h15674 = rg_mideleg[5] ? 2'b01 : 2'b11 ; - assign _theResult____h15886 = rg_mideleg[8] ? 2'b01 : 2'b11 ; - assign _theResult____h16098 = rg_mideleg[0] ? 2'b01 : 2'b11 ; - assign _theResult____h16310 = rg_mideleg[4] ? 2'b01 : 2'b11 ; - assign _theResult___fst__h10902 = - (csr_trap_actions_interrupt ? - deleg_bit___1__h10911 : - deleg_bit___1__h10926) ? - 2'b01 : - 2'b11 ; - assign _theResult___fst__h12935 = - { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[31:13], - 2'd0, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[10:0] } ; - assign _theResult___fst__h13136 = - { csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[31:9], - 1'd0, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[7:0] } ; - assign b__h10989 = csr_mstatus_rg_mstatus[new_priv__h10791] ; - assign b__h12972 = - csr_mstatus_rg_mstatus[{ 3'd1, csr_ret_actions_from_priv }] ; - assign csr_mip_fv_read__94_BIT_0_060_AND_csr_mie_fv_r_ETC___d2069 = - csr_mip$fv_read[0] && csr_mie$fv_read[0] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d1993 = - csr_mip$fv_read[11] && csr_mie$fv_read[11] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d2059 = - csr_mip_fv_read__94_BIT_11_976_AND_csr_mie_fv__ETC___d1993 || - csr_mip_fv_read__94_BIT_3_994_AND_csr_mie_fv_r_ETC___d2003 || - csr_mip_fv_read__94_BIT_7_005_AND_csr_mie_fv_r_ETC___d2014 || - csr_mip_fv_read__94_BIT_9_016_AND_csr_mie_fv_r_ETC___d2025 || - csr_mip_fv_read__94_BIT_1_027_AND_csr_mie_fv_r_ETC___d2036 || - csr_mip_fv_read__94_BIT_5_038_AND_csr_mie_fv_r_ETC___d2047 || - csr_mip_fv_read__94_BIT_8_049_AND_csr_mie_fv_r_ETC___d2058 ; - assign csr_mip_fv_read__94_BIT_1_027_AND_csr_mie_fv_r_ETC___d2036 = - csr_mip$fv_read[1] && csr_mie$fv_read[1] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_3_994_AND_csr_mie_fv_r_ETC___d2003 = - csr_mip$fv_read[3] && csr_mie$fv_read[3] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_4_071_AND_csr_mie_fv_r_ETC___d2080 = - csr_mip$fv_read[4] && csr_mie$fv_read[4] && - (interrupt_pending_cur_priv < _theResult____h16310 || - interrupt_pending_cur_priv == _theResult____h16310 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_5_038_AND_csr_mie_fv_r_ETC___d2047 = - csr_mip$fv_read[5] && csr_mie$fv_read[5] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_7_005_AND_csr_mie_fv_r_ETC___d2014 = - csr_mip$fv_read[7] && csr_mie$fv_read[7] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_8_049_AND_csr_mie_fv_r_ETC___d2058 = - csr_mip$fv_read[8] && csr_mie$fv_read[8] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mip_fv_read__94_BIT_9_016_AND_csr_mie_fv_r_ETC___d2025 = - csr_mip$fv_read[9] && csr_mie$fv_read[9] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022 && - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990) ; - assign csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675 = - x__h12968 | mask__h12956 ; - assign csr_mstatus_rg_mstatus_46_AND_INV_1_SL_1_CONCA_ETC___d1476 = - x__h10985 | val__h10974 ; - assign csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1508 = - csr_trap_actions_interrupt && !csr_trap_actions_nmi && - CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 ; - assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1657 = - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 != 4'd0 && - exc_code__h12648 != 4'd1 && - exc_code__h12648 != 4'd2 && - exc_code__h12648 != 4'd3 && - exc_code__h12648 != 4'd4 && - exc_code__h12648 != 4'd5 && - exc_code__h12648 != 4'd6 && - exc_code__h12648 != 4'd7 && - exc_code__h12648 != 4'd8 && - exc_code__h12648 != 4'd9 && - exc_code__h12648 != 4'd11 && - exc_code__h12648 != 4'd12 && - exc_code__h12648 != 4'd13 && - exc_code__h12648 != 4'd15 ; - assign deleg_bit___1__h10911 = rg_mideleg[csr_trap_actions_exc_code] ; - assign deleg_bit___1__h10926 = rg_medeleg[csr_trap_actions_exc_code] ; - assign exc_code__h12648 = - csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; - assign exc_pc___1__h12025 = exc_pc__h11951 + vector_offset__h11952 ; - assign exc_pc__h11951 = - csr_trap_actions_nmi ? - rg_nmi_vector : - y_avValue_snd_snd__h11998 ; - assign fixed_up_val_23__h10840 = - { IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[22:17], - 2'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[14:13], - (IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[12:11] == - 2'b10) ? - 2'b01 : - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[12:11], - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[10:5], - 1'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[3:1], - 1'd0 } ; - assign fixed_up_val_23__h12869 = - { IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[22:17], - 2'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[14:13], - (IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[12:11] == - 2'b10) ? - 2'b01 : - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[12:11], - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[10:5], - 1'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[3:1], - 1'd0 } ; - assign fixed_up_val_23__h6007 = - { csr_mstatus_rg_mstatus[22:20], - mav_csr_write_word[19:18], - csr_mstatus_rg_mstatus[17], - 2'd0, - mav_csr_write_word[14:13], - IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906, - csr_mstatus_rg_mstatus[10:9], - mav_csr_write_word[8], - csr_mstatus_rg_mstatus[7:6], - mav_csr_write_word[5], - 1'd0, - csr_mstatus_rg_mstatus[3:2], - mav_csr_write_word[1], - 1'd0 } ; - assign fixed_up_val_23__h7253 = - { mav_csr_write_word[22:17], - 2'd0, - mav_csr_write_word[14:13], - (mav_csr_write_word[12:11] == 2'b10) ? - 2'b01 : - mav_csr_write_word[12:11], - mav_csr_write_word[10:5], - 1'd0, - mav_csr_write_word[3:1], - 1'd0 } ; - assign fixed_up_val_23__h9209 = - { csr_mstatus_rg_mstatus[22:17], - 2'd0, - ma_update_mstatus_fs_fs, - IF_csr_mstatus_rg_mstatus_46_BITS_12_TO_11_04__ETC___d906, - csr_mstatus_rg_mstatus[10:5], - 1'd0, - csr_mstatus_rg_mstatus[3:1], - 1'd0 } ; - assign ie_from_x__h12919 = { 4'd0, csr_ret_actions_from_priv } ; - assign ie_to_x__h10890 = { 4'd0, new_priv__h10791 } ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d1982 = - interrupt_pending_cur_priv == _theResult____h14614 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2000 = - interrupt_pending_cur_priv == _theResult____h14826 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2011 = - interrupt_pending_cur_priv == _theResult____h15038 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2022 = - interrupt_pending_cur_priv == _theResult____h15250 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2033 = - interrupt_pending_cur_priv == _theResult____h15462 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2044 = - interrupt_pending_cur_priv == _theResult____h15674 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2055 = - interrupt_pending_cur_priv == _theResult____h15886 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_75_ETC___d2066 = - interrupt_pending_cur_priv == _theResult____h16098 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1981 = - interrupt_pending_cur_priv < _theResult____h14614 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d1999 = - interrupt_pending_cur_priv < _theResult____h14826 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2010 = - interrupt_pending_cur_priv < _theResult____h15038 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2021 = - interrupt_pending_cur_priv < _theResult____h15250 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2032 = - interrupt_pending_cur_priv < _theResult____h15462 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2043 = - interrupt_pending_cur_priv < _theResult____h15674 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2054 = - interrupt_pending_cur_priv < _theResult____h15886 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_7_ETC___d2065 = - interrupt_pending_cur_priv < _theResult____h16098 ; - assign mask__h10973 = 32'd1 << ie_to_x__h10890 ; - assign mask__h10990 = 32'd1 << pie_to_x__h10891 ; - assign mask__h12956 = 32'd1 << pie_from_x__h12920 ; - assign mask__h12973 = 32'd1 << ie_from_x__h12919 ; - assign mav_csr_write_csr_addr_ULE_0x33F___d872 = - mav_csr_write_csr_addr <= 12'h33F ; - assign mav_csr_write_csr_addr_ULE_0xB1F___d864 = - mav_csr_write_csr_addr <= 12'hB1F ; - assign mav_csr_write_csr_addr_ULE_0xB9F___d868 = - mav_csr_write_csr_addr <= 12'hB9F ; - assign mav_csr_write_csr_addr_ULT_0x323_71_OR_NOT_mav_ETC___d1145 = - (mav_csr_write_csr_addr_ULT_0x323___d871 || - !mav_csr_write_csr_addr_ULE_0x33F___d872) && - mav_csr_write_csr_addr != 12'h001 && - mav_csr_write_csr_addr != 12'h002 && - mav_csr_write_csr_addr != 12'h003 && - mav_csr_write_csr_addr != 12'h100 && - mav_csr_write_csr_addr != 12'h102 && - mav_csr_write_csr_addr != 12'h103 && - mav_csr_write_csr_addr != 12'h104 && - mav_csr_write_csr_addr != 12'h105 && - mav_csr_write_csr_addr != 12'h106 && - mav_csr_write_csr_addr != 12'h140 && - mav_csr_write_csr_addr != 12'h141 && - mav_csr_write_csr_addr != 12'h142 && - mav_csr_write_csr_addr != 12'h143 && - mav_csr_write_csr_addr != 12'h144 && - mav_csr_write_csr_addr != 12'h180 && - mav_csr_write_csr_addr != 12'h302 && - mav_csr_write_csr_addr != 12'h303 && - mav_csr_write_csr_addr != 12'hF11 && - mav_csr_write_csr_addr != 12'hF12 && - mav_csr_write_csr_addr != 12'hF13 && - mav_csr_write_csr_addr != 12'hF14 && - mav_csr_write_csr_addr != 12'h300 && - mav_csr_write_csr_addr != 12'h301 && - mav_csr_write_csr_addr != 12'h304 && - mav_csr_write_csr_addr != 12'h305 && - mav_csr_write_csr_addr != 12'h306 && - mav_csr_write_csr_addr != 12'h340 && - mav_csr_write_csr_addr != 12'h341 && - mav_csr_write_csr_addr != 12'h342 && - mav_csr_write_csr_addr != 12'h343 && - mav_csr_write_csr_addr != 12'h344 && - mav_csr_write_csr_addr != 12'hB00 && - mav_csr_write_csr_addr != 12'hB02 && - mav_csr_write_csr_addr != 12'hB80 && - mav_csr_write_csr_addr != 12'hB82 && - mav_csr_write_csr_addr != 12'h7A0 && - mav_csr_write_csr_addr != 12'h7A1 && - mav_csr_write_csr_addr != 12'h7A2 && - mav_csr_write_csr_addr != 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0x323___d871 = - mav_csr_write_csr_addr < 12'h323 ; - assign mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d1147 = - (mav_csr_write_csr_addr_ULT_0xB03___d863 || - !mav_csr_write_csr_addr_ULE_0xB1F___d864) && - (mav_csr_write_csr_addr_ULT_0xB83___d867 || - !mav_csr_write_csr_addr_ULE_0xB9F___d868) && - mav_csr_write_csr_addr_ULT_0x323_71_OR_NOT_mav_ETC___d1145 ; - assign mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d876 = - (mav_csr_write_csr_addr_ULT_0xB03___d863 || - !mav_csr_write_csr_addr_ULE_0xB1F___d864) && - (mav_csr_write_csr_addr_ULT_0xB83___d867 || - !mav_csr_write_csr_addr_ULE_0xB9F___d868) && - (mav_csr_write_csr_addr_ULT_0x323___d871 || - !mav_csr_write_csr_addr_ULE_0x33F___d872) ; - assign mav_csr_write_csr_addr_ULT_0xB03___d863 = - mav_csr_write_csr_addr < 12'hB03 ; - assign mav_csr_write_csr_addr_ULT_0xB83___d867 = - mav_csr_write_csr_addr < 12'hB83 ; - assign new_priv__h10791 = - csr_trap_actions_nmi ? - 2'b11 : - ((csr_trap_actions_from_priv == 2'b11) ? - csr_trap_actions_from_priv : - _theResult___fst__h10902) ; - assign pie_from_x__h12920 = { 4'd1, csr_ret_actions_from_priv } ; - assign pie_to_x__h10891 = { 4'd1, new_priv__h10791 } ; - assign result__h8591 = { 4'd0, mav_csr_write_word[27:0] } ; - assign sd__h10839 = - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[14:13] == - 2'h3 ; - assign sd__h12868 = - IF_csr_ret_actions_from_priv_EQ_0b11_661_THEN__ETC___d1682[14:13] == - 2'h3 ; - assign sd__h7252 = mav_csr_write_word[14:13] == 2'h3 ; - assign sd__h9208 = ma_update_mstatus_fs_fs == 2'h3 ; - assign to_y__h13135 = - { 1'b0, - csr_mstatus_rg_mstatus_46_AND_INV_1_SL_0_CONCA_ETC___d1675[8] } ; - assign v__h10796 = { sd__h10839, 8'd0, fixed_up_val_23__h10840 } ; - assign v__h5698 = { 27'd0, mav_csr_write_word[4:0] } ; - assign v__h5842 = { 24'd0, mav_csr_write_word[7:0] } ; - assign v__h5956 = - { sd__h7252, - 11'd0, - mav_csr_write_word[19:18], - 3'd0, - mav_csr_write_word[14:13], - 4'd0, - mav_csr_write_word[8], - 2'd0, - mav_csr_write_word[5], - 3'd0, - mav_csr_write_word[1], - 1'd0 } ; - assign v__h7081 = - { 16'd0, - mav_csr_write_word[15], - 1'd0, - mav_csr_write_word[13:12], - 2'd0, - mav_csr_write_word[9:0] } ; - assign v__h7117 = { 20'd0, mav_csr_write_word[11:0] } ; - assign v__h7758 = - { mav_csr_write_word[31:2], 1'b0, mav_csr_write_word[0] } ; - assign v__h7820 = { 29'd0, mav_csr_write_word[2:0] } ; - assign v__h7976 = - { mav_csr_write_word[31], 27'd0, mav_csr_write_word[3:0] } ; - assign val__h10974 = 32'd0 << ie_to_x__h10890 ; - assign val__h10991 = { 31'd0, b__h10989 } << pie_to_x__h10891 ; - assign val__h12974 = { 31'd0, b__h12972 } << ie_from_x__h12919 ; - assign vector_offset__h11952 = { 26'd0, csr_trap_actions_exc_code, 2'd0 } ; - assign wordxl1__h7212 = { sd__h7252, 8'd0, fixed_up_val_23__h7253 } ; - assign x__h10972 = x__h11002 | val__h10991 ; - assign x__h10985 = x__h10972 & y__h10986 ; - assign x__h11002 = csr_mstatus_rg_mstatus & y__h11003 ; - assign x__h12806 = - (csr_trap_actions_nmi || new_priv__h10791 == 2'b11) ? - v__h10796 : - y_avValue_fst__h11925 ; - assign x__h12807 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - 27'd0, - exc_code__h12648 } ; - assign x__h12955 = x__h12985 | val__h12974 ; - assign x__h12968 = x__h12955 & y__h12969 ; - assign x__h12985 = csr_mstatus_rg_mstatus & y__h12986 ; - assign x__h8408 = { rg_minstret[63:32], mav_csr_write_word } ; - assign x__h8516 = { mav_csr_write_word, rg_minstret[31:0] } ; - assign x__h9768 = - csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1508 ? - exc_pc___1__h12025 : - exc_pc__h11951 ; - assign y__h10986 = ~mask__h10973 ; - assign y__h11003 = ~mask__h10990 ; - assign y__h12969 = ~mask__h12956 ; - assign y__h12986 = ~mask__h12973 ; - assign y_avValue_fst__h11908 = - { sd__h10839, - 11'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[19:18], - 3'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[14:13], - 4'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[8], - 2'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[5], - 3'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1484[1], - 1'd0 } ; - assign y_avValue_fst__h11925 = - (new_priv__h10791 == 2'b01) ? y_avValue_fst__h11908 : v__h10796 ; - assign y_avValue_snd_snd__h11998 = - { CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1, - 2'd0 } ; - always@(mav_csr_write_csr_addr or - v__h5698 or - v__h7820 or - v__h5842 or - v__h5956 or - csr_mie$fav_sie_write or - v__h7758 or - mav_csr_write_word or - v__h7976 or - csr_mip$fav_sip_write or - wordxl1__h7212 or - v__h7081 or - v__h7117 or csr_mie$fav_write or csr_mip$fav_write or result__h8591) - begin - case (mav_csr_write_csr_addr) - 12'h001: y_avValue_fst__h8976 = v__h5698; - 12'h002, 12'h306: y_avValue_fst__h8976 = v__h7820; - 12'h003: y_avValue_fst__h8976 = v__h5842; - 12'h100: y_avValue_fst__h8976 = v__h5956; - 12'h102, - 12'h103, - 12'h106, - 12'h301, - 12'h7A0, - 12'hF11, - 12'hF12, - 12'hF13, - 12'hF14: - y_avValue_fst__h8976 = 32'd0; - 12'h104: y_avValue_fst__h8976 = csr_mie$fav_sie_write; - 12'h105, 12'h305: y_avValue_fst__h8976 = v__h7758; - 12'h140, - 12'h141, - 12'h143, - 12'h180, - 12'h340, - 12'h341, - 12'h343, - 12'h7A2, - 12'h7A3, - 12'hB00, - 12'hB02, - 12'hB80, - 12'hB82: - y_avValue_fst__h8976 = mav_csr_write_word; - 12'h142, 12'h342: y_avValue_fst__h8976 = v__h7976; - 12'h144: y_avValue_fst__h8976 = csr_mip$fav_sip_write; - 12'h300: y_avValue_fst__h8976 = wordxl1__h7212; - 12'h302: y_avValue_fst__h8976 = v__h7081; - 12'h303: y_avValue_fst__h8976 = v__h7117; - 12'h304: y_avValue_fst__h8976 = csr_mie$fav_write; - 12'h344: y_avValue_fst__h8976 = csr_mip$fav_write; - 12'h7A1: y_avValue_fst__h8976 = result__h8591; - default: y_avValue_fst__h8976 = 32'd0; - endcase - end - always@(new_priv__h10791 or rg_mtvec or rg_stvec) - begin - case (new_priv__h10791) - 2'b01: - CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1 = - rg_stvec[30:1]; - 2'b11: - CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1 = - rg_mtvec[30:1]; - default: CASE_new_priv0791_0b1_rg_stvec_BITS_30_TO_1_0b_ETC__q1 = - rg_mtvec[30:1]; - endcase - end - always@(new_priv__h10791 or rg_mtvec or rg_stvec) - begin - case (new_priv__h10791) - 2'b01: - CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_stvec[0]; - 2'b11: - CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_mtvec[0]; - default: CASE_new_priv0791_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_mtvec[0]; - endcase - end - always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) - begin - case (interrupt_pending_cur_priv) - 2'b0: - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990 = - csr_mstatus_rg_mstatus[0]; - 2'b01: - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990 = - csr_mstatus_rg_mstatus[1]; - default: IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d1990 = - interrupt_pending_cur_priv == 2'b11 && - csr_mstatus_rg_mstatus[3]; - endcase - end - always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) - begin - case (interrupt_pending_cur_priv) - 2'b0: - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093 = - !csr_mstatus_rg_mstatus[0]; - 2'b01: - IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093 = - !csr_mstatus_rg_mstatus[1]; - default: IF_interrupt_pending_cur_priv_EQ_0b0_983_THEN__ETC___d2093 = - interrupt_pending_cur_priv != 2'b11 || - !csr_mstatus_rg_mstatus[3]; - endcase - end - always@(read_csr_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_csr_addr) - 12'h001: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 27'd0, rg_fflags }; - 12'h002: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 29'd0, rg_frm }; - 12'h003: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 24'd0, rg_frm, rg_fflags }; - 12'h100: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = 32'd0; - 12'h104: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - csr_mie$fv_sie_read; - 12'h105: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { rg_stvec[30:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_sscratch; - 12'h141: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = rg_sepc; - 12'h142: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { rg_scause[4], 27'd0, rg_scause[3:0] }; - 12'h143: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_stval; - 12'h144: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - csr_mip$fv_sip_read; - 12'h180: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = rg_satp; - 12'h300: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - 32'd1075056941; - 12'h302: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 16'd0, rg_medeleg }; - 12'h303: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 20'd0, rg_mideleg }; - 12'h304: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_mscratch; - 12'h341: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = rg_mepc; - 12'h342: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_mtval; - 12'h344: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_tselect; - 12'h7A1: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_tdata1; - 12'h7A2: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_minstret[63:32]; - default: IF_read_csr_csr_addr_EQ_0x1_9_THEN_0_CONCAT_rg_ETC___d336 = - rg_tdata3; - endcase - end - always@(read_csr_port2_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_port2_csr_addr) - 12'h001: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 27'd0, rg_fflags }; - 12'h002: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 29'd0, rg_frm }; - 12'h003: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 24'd0, rg_frm, rg_fflags }; - 12'h100: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = 32'd0; - 12'h104: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - csr_mie$fv_sie_read; - 12'h105: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { rg_stvec[30:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_sscratch; - 12'h141: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = rg_sepc; - 12'h142: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { rg_scause[4], 27'd0, rg_scause[3:0] }; - 12'h143: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_stval; - 12'h144: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - csr_mip$fv_sip_read; - 12'h180: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = rg_satp; - 12'h300: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - 32'd1075056941; - 12'h302: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 16'd0, rg_medeleg }; - 12'h303: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 20'd0, rg_mideleg }; - 12'h304: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_mscratch; - 12'h341: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = rg_mepc; - 12'h342: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_mtval; - 12'h344: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_tselect; - 12'h7A1: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_tdata1; - 12'h7A2: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_minstret[63:32]; - default: IF_read_csr_port2_csr_addr_EQ_0x1_59_THEN_0_CO_ETC___d598 = - rg_tdata3; - endcase - end - always@(mav_read_csr_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (mav_read_csr_csr_addr) - 12'h001: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 27'd0, rg_fflags }; - 12'h002: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 29'd0, rg_frm }; - 12'h003: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 24'd0, rg_frm, rg_fflags }; - 12'h100: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = 32'd0; - 12'h104: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - csr_mie$fv_sie_read; - 12'h105: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { rg_stvec[30:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_sscratch; - 12'h141: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = rg_sepc; - 12'h142: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { rg_scause[4], 27'd0, rg_scause[3:0] }; - 12'h143: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_stval; - 12'h144: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - csr_mip$fv_sip_read; - 12'h180: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = rg_satp; - 12'h300: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - 32'd1075056941; - 12'h302: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 16'd0, rg_medeleg }; - 12'h303: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 20'd0, rg_mideleg }; - 12'h304: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - csr_mie$fv_read; - 12'h305: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_mscratch; - 12'h341: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = rg_mepc; - 12'h342: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_mtval; - 12'h344: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - csr_mip$fv_read; - 12'h7A0: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_tselect; - 12'h7A1: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_tdata1; - 12'h7A2: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_minstret[63:32]; - default: IF_mav_read_csr_csr_addr_EQ_0x1_21_THEN_0_CONC_ETC___d860 = - rg_tdata3; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 32'd8192; - rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (csr_mstatus_rg_mstatus$EN) - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY - csr_mstatus_rg_mstatus$D_IN; - if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; - if (rg_minstret$EN) - rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; - if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; - if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; - if (rg_dscratch0$EN) - rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; - if (rg_dscratch1$EN) - rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; - if (rg_fflags$EN) rg_fflags <= `BSV_ASSIGNMENT_DELAY rg_fflags$D_IN; - if (rg_frm$EN) rg_frm <= `BSV_ASSIGNMENT_DELAY rg_frm$D_IN; - if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; - if (rg_mcounteren$EN) - rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; - if (rg_medeleg$EN) rg_medeleg <= `BSV_ASSIGNMENT_DELAY rg_medeleg$D_IN; - if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; - if (rg_mideleg$EN) rg_mideleg <= `BSV_ASSIGNMENT_DELAY rg_mideleg$D_IN; - if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; - if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; - if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; - if (rg_nmi_vector$EN) - rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN; - if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; - if (rg_scause$EN) rg_scause <= `BSV_ASSIGNMENT_DELAY rg_scause$D_IN; - if (rg_sepc$EN) rg_sepc <= `BSV_ASSIGNMENT_DELAY rg_sepc$D_IN; - if (rg_sscratch$EN) rg_sscratch <= `BSV_ASSIGNMENT_DELAY rg_sscratch$D_IN; - if (rg_stval$EN) rg_stval <= `BSV_ASSIGNMENT_DELAY rg_stval$D_IN; - if (rg_stvec$EN) rg_stvec <= `BSV_ASSIGNMENT_DELAY rg_stvec$D_IN; - if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; - if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; - if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; - if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - csr_mstatus_rg_mstatus = 32'hAAAAAAAA; - rg_dcsr = 32'hAAAAAAAA; - rg_dpc = 32'hAAAAAAAA; - rg_dscratch0 = 32'hAAAAAAAA; - rg_dscratch1 = 32'hAAAAAAAA; - rg_fflags = 5'h0A; - rg_frm = 3'h2; - rg_mcause = 5'h0A; - rg_mcounteren = 3'h2; - rg_mcycle = 64'hAAAAAAAAAAAAAAAA; - rg_medeleg = 16'hAAAA; - rg_mepc = 32'hAAAAAAAA; - rg_mideleg = 12'hAAA; - rg_minstret = 64'hAAAAAAAAAAAAAAAA; - rg_mscratch = 32'hAAAAAAAA; - rg_mtval = 32'hAAAAAAAA; - rg_mtvec = 31'h2AAAAAAA; - rg_nmi = 1'h0; - rg_nmi_vector = 32'hAAAAAAAA; - rg_satp = 32'hAAAAAAAA; - rg_scause = 5'h0A; - rg_sepc = 32'hAAAAAAAA; - rg_sscratch = 32'hAAAAAAAA; - rg_state = 1'h0; - rg_stval = 32'hAAAAAAAA; - rg_stvec = 31'h2AAAAAAA; - rg_tdata1 = 32'hAAAAAAAA; - rg_tdata2 = 32'hAAAAAAAA; - rg_tdata3 = 32'hAAAAAAAA; - rg_tselect = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) - $display("sstatus = 0x%0h", - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("sip = 0x%0h", csr_mip$fv_sip_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("sie = 0x%0h", csr_mie$fv_sie_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_63_OR_NOT_mav_ETC___d1147 && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", - rg_mcycle, - mav_csr_write_csr_addr, - mav_csr_write_word); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" priv %0d: ", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" edeleg: 0x%0h", 16'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ideleg: 0x%0h", 12'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_scause[4] && - rg_scause[3:0] != 4'd0 && - rg_scause[3:0] != 4'd1 && - rg_scause[3:0] != 4'd2 && - rg_scause[3:0] != 4'd3 && - rg_scause[3:0] != 4'd4 && - rg_scause[3:0] != 4'd5 && - rg_scause[3:0] != 4'd6 && - rg_scause[3:0] != 4'd7 && - rg_scause[3:0] != 4'd8 && - rg_scause[3:0] != 4'd9 && - rg_scause[3:0] != 4'd10 && - rg_scause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_scause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_scause[4] && - rg_scause[3:0] != 4'd0 && - rg_scause[3:0] != 4'd1 && - rg_scause[3:0] != 4'd2 && - rg_scause[3:0] != 4'd3 && - rg_scause[3:0] != 4'd4 && - rg_scause[3:0] != 4'd5 && - rg_scause[3:0] != 4'd6 && - rg_scause[3:0] != 4'd7 && - rg_scause[3:0] != 4'd8 && - rg_scause[3:0] != 4'd9 && - rg_scause[3:0] != 4'd11 && - rg_scause[3:0] != 4'd12 && - rg_scause[3:0] != 4'd13 && - rg_scause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_scause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" status: 0x%0h", - { csr_mstatus_rg_mstatus[31], - 11'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tvec: 0x%0h", { rg_stvec[30:1], 1'b0, rg_stvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" epc: 0x%0h", rg_sepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tval: 0x%0h", rg_stval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" priv %0d: ", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" edeleg: 0x%0h", rg_medeleg); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ideleg: 0x%0h", rg_mideleg); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd10 && - rg_mcause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd11 && - rg_mcause[3:0] != 4'd12 && - rg_mcause[3:0] != 4'd13 && - rg_mcause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" status: 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tvec: 0x%0h", { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" epc: 0x%0h", rg_mepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tval: 0x%0h", rg_mtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" Return: new pc 0x%0h ", x__h9768); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" new mstatus:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write("MStatus{", - "sd:%0d", - x__h12806[14:13] == 2'h3 || x__h12806[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tsr:%0d", x__h12806[22]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tw:%0d", x__h12806[21]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" tvm:%0d", x__h12806[20]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" mxr:%0d", x__h12806[19]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" sum:%0d", x__h12806[18]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" mprv:%0d", x__h12806[17]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" xs:%0d", x__h12806[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" fs:%0d", x__h12806[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" mpp:%0d", x__h12806[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" spp:%0d", x__h12806[8]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" pies:%0d_%0d%0d", x__h12806[7], x__h12806[5], x__h12806[4]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" ies:%0d_%0d%0d", x__h12806[3], x__h12806[1], x__h12806[0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" new xcause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h12648 == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - NOT_csr_trap_actions_nmi_499_AND_csr_trap_acti_ETC___d1606) - $write("unknown interrupt Exc_Code %d", exc_code__h12648); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h12648 == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150 && - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1657) - $write("unknown trap Exc_Code %d", exc_code__h12648); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $write(" new priv %0d", new_priv__h10791); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && - NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", - rg_mcycle, - m_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", - rg_mcycle, - s_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: CSR_RegFile: timer_interrupt_req: %x", - rg_mcycle, - timer_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__148_ULE_1_149___d1150) - $display("%0d: CSR_RegFile: software_interrupt_req: %x", - rg_mcycle, - software_interrupt_req_set_not_clear); - end - // synopsys translate_on -endmodule // mkCSR_RegFile - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCore.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCore.v deleted file mode 100644 index 5178628a..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCore.v +++ /dev/null @@ -1,2499 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// cpu_reset_server_response_get O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg -// cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg -// cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg -// cpu_imem_master_bready O 1 -// cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg -// cpu_imem_master_rready O 1 -// cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg -// cpu_dmem_master_awaddr O 64 reg -// cpu_dmem_master_awlen O 8 reg -// cpu_dmem_master_awsize O 3 reg -// cpu_dmem_master_awburst O 2 reg -// cpu_dmem_master_awlock O 1 reg -// cpu_dmem_master_awcache O 4 reg -// cpu_dmem_master_awprot O 3 reg -// cpu_dmem_master_awqos O 4 reg -// cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg -// cpu_dmem_master_wdata O 64 reg -// cpu_dmem_master_wstrb O 8 reg -// cpu_dmem_master_wlast O 1 reg -// cpu_dmem_master_bready O 1 reg -// cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg -// cpu_dmem_master_araddr O 64 reg -// cpu_dmem_master_arlen O 8 reg -// cpu_dmem_master_arsize O 3 reg -// cpu_dmem_master_arburst O 2 reg -// cpu_dmem_master_arlock O 1 reg -// cpu_dmem_master_arcache O 4 reg -// cpu_dmem_master_arprot O 3 reg -// cpu_dmem_master_arqos O 4 reg -// cpu_dmem_master_arregion O 4 reg -// cpu_dmem_master_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// cpu_reset_server_request_put I 1 reg -// cpu_imem_master_awready I 1 -// cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg -// cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg -// cpu_dmem_master_awready I 1 -// cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg -// cpu_dmem_master_bresp I 2 reg -// cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg -// cpu_dmem_master_rdata I 64 reg -// cpu_dmem_master_rresp I 2 reg -// cpu_dmem_master_rlast I 1 reg -// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// nmi_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (cpu_imem_master_awready, -// cpu_imem_master_wready, -// cpu_imem_master_arready) -> cpu_imem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCore(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - cpu_reset_server_request_put, - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, - - cpu_imem_master_awvalid, - - cpu_imem_master_awid, - - cpu_imem_master_awaddr, - - cpu_imem_master_awlen, - - cpu_imem_master_awsize, - - cpu_imem_master_awburst, - - cpu_imem_master_awlock, - - cpu_imem_master_awcache, - - cpu_imem_master_awprot, - - cpu_imem_master_awqos, - - cpu_imem_master_awregion, - - cpu_imem_master_awready, - - cpu_imem_master_wvalid, - - cpu_imem_master_wid, - - cpu_imem_master_wdata, - - cpu_imem_master_wstrb, - - cpu_imem_master_wlast, - - cpu_imem_master_wready, - - cpu_imem_master_bvalid, - cpu_imem_master_bid, - cpu_imem_master_bresp, - - cpu_imem_master_bready, - - cpu_imem_master_arvalid, - - cpu_imem_master_arid, - - cpu_imem_master_araddr, - - cpu_imem_master_arlen, - - cpu_imem_master_arsize, - - cpu_imem_master_arburst, - - cpu_imem_master_arlock, - - cpu_imem_master_arcache, - - cpu_imem_master_arprot, - - cpu_imem_master_arqos, - - cpu_imem_master_arregion, - - cpu_imem_master_arready, - - cpu_imem_master_rvalid, - cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast, - - cpu_imem_master_rready, - - cpu_dmem_master_awvalid, - - cpu_dmem_master_awid, - - cpu_dmem_master_awaddr, - - cpu_dmem_master_awlen, - - cpu_dmem_master_awsize, - - cpu_dmem_master_awburst, - - cpu_dmem_master_awlock, - - cpu_dmem_master_awcache, - - cpu_dmem_master_awprot, - - cpu_dmem_master_awqos, - - cpu_dmem_master_awregion, - - cpu_dmem_master_awready, - - cpu_dmem_master_wvalid, - - cpu_dmem_master_wid, - - cpu_dmem_master_wdata, - - cpu_dmem_master_wstrb, - - cpu_dmem_master_wlast, - - cpu_dmem_master_wready, - - cpu_dmem_master_bvalid, - cpu_dmem_master_bid, - cpu_dmem_master_bresp, - - cpu_dmem_master_bready, - - cpu_dmem_master_arvalid, - - cpu_dmem_master_arid, - - cpu_dmem_master_araddr, - - cpu_dmem_master_arlen, - - cpu_dmem_master_arsize, - - cpu_dmem_master_arburst, - - cpu_dmem_master_arlock, - - cpu_dmem_master_arcache, - - cpu_dmem_master_arprot, - - cpu_dmem_master_arqos, - - cpu_dmem_master_arregion, - - cpu_dmem_master_arready, - - cpu_dmem_master_rvalid, - cpu_dmem_master_rid, - cpu_dmem_master_rdata, - cpu_dmem_master_rresp, - cpu_dmem_master_rlast, - - cpu_dmem_master_rready, - - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - - nmi_req_set_not_clear); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method cpu_reset_server_request_put - input cpu_reset_server_request_put; - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // actionvalue method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; - - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; - - // value method cpu_imem_master_m_awaddr - output [63 : 0] cpu_imem_master_awaddr; - - // value method cpu_imem_master_m_awlen - output [7 : 0] cpu_imem_master_awlen; - - // value method cpu_imem_master_m_awsize - output [2 : 0] cpu_imem_master_awsize; - - // value method cpu_imem_master_m_awburst - output [1 : 0] cpu_imem_master_awburst; - - // value method cpu_imem_master_m_awlock - output cpu_imem_master_awlock; - - // value method cpu_imem_master_m_awcache - output [3 : 0] cpu_imem_master_awcache; - - // value method cpu_imem_master_m_awprot - output [2 : 0] cpu_imem_master_awprot; - - // value method cpu_imem_master_m_awqos - output [3 : 0] cpu_imem_master_awqos; - - // value method cpu_imem_master_m_awregion - output [3 : 0] cpu_imem_master_awregion; - - // value method cpu_imem_master_m_awuser - - // action method cpu_imem_master_m_awready - input cpu_imem_master_awready; - - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; - - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - - // value method cpu_imem_master_m_wdata - output [63 : 0] cpu_imem_master_wdata; - - // value method cpu_imem_master_m_wstrb - output [7 : 0] cpu_imem_master_wstrb; - - // value method cpu_imem_master_m_wlast - output cpu_imem_master_wlast; - - // value method cpu_imem_master_m_wuser - - // action method cpu_imem_master_m_wready - input cpu_imem_master_wready; - - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; - input [1 : 0] cpu_imem_master_bresp; - - // value method cpu_imem_master_m_bready - output cpu_imem_master_bready; - - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; - - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; - - // value method cpu_imem_master_m_araddr - output [63 : 0] cpu_imem_master_araddr; - - // value method cpu_imem_master_m_arlen - output [7 : 0] cpu_imem_master_arlen; - - // value method cpu_imem_master_m_arsize - output [2 : 0] cpu_imem_master_arsize; - - // value method cpu_imem_master_m_arburst - output [1 : 0] cpu_imem_master_arburst; - - // value method cpu_imem_master_m_arlock - output cpu_imem_master_arlock; - - // value method cpu_imem_master_m_arcache - output [3 : 0] cpu_imem_master_arcache; - - // value method cpu_imem_master_m_arprot - output [2 : 0] cpu_imem_master_arprot; - - // value method cpu_imem_master_m_arqos - output [3 : 0] cpu_imem_master_arqos; - - // value method cpu_imem_master_m_arregion - output [3 : 0] cpu_imem_master_arregion; - - // value method cpu_imem_master_m_aruser - - // action method cpu_imem_master_m_arready - input cpu_imem_master_arready; - - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; - input [63 : 0] cpu_imem_master_rdata; - input [1 : 0] cpu_imem_master_rresp; - input cpu_imem_master_rlast; - - // value method cpu_imem_master_m_rready - output cpu_imem_master_rready; - - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; - - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; - - // value method cpu_dmem_master_m_awaddr - output [63 : 0] cpu_dmem_master_awaddr; - - // value method cpu_dmem_master_m_awlen - output [7 : 0] cpu_dmem_master_awlen; - - // value method cpu_dmem_master_m_awsize - output [2 : 0] cpu_dmem_master_awsize; - - // value method cpu_dmem_master_m_awburst - output [1 : 0] cpu_dmem_master_awburst; - - // value method cpu_dmem_master_m_awlock - output cpu_dmem_master_awlock; - - // value method cpu_dmem_master_m_awcache - output [3 : 0] cpu_dmem_master_awcache; - - // value method cpu_dmem_master_m_awprot - output [2 : 0] cpu_dmem_master_awprot; - - // value method cpu_dmem_master_m_awqos - output [3 : 0] cpu_dmem_master_awqos; - - // value method cpu_dmem_master_m_awregion - output [3 : 0] cpu_dmem_master_awregion; - - // value method cpu_dmem_master_m_awuser - - // action method cpu_dmem_master_m_awready - input cpu_dmem_master_awready; - - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; - - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - - // value method cpu_dmem_master_m_wdata - output [63 : 0] cpu_dmem_master_wdata; - - // value method cpu_dmem_master_m_wstrb - output [7 : 0] cpu_dmem_master_wstrb; - - // value method cpu_dmem_master_m_wlast - output cpu_dmem_master_wlast; - - // value method cpu_dmem_master_m_wuser - - // action method cpu_dmem_master_m_wready - input cpu_dmem_master_wready; - - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; - input [1 : 0] cpu_dmem_master_bresp; - - // value method cpu_dmem_master_m_bready - output cpu_dmem_master_bready; - - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; - - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; - - // value method cpu_dmem_master_m_araddr - output [63 : 0] cpu_dmem_master_araddr; - - // value method cpu_dmem_master_m_arlen - output [7 : 0] cpu_dmem_master_arlen; - - // value method cpu_dmem_master_m_arsize - output [2 : 0] cpu_dmem_master_arsize; - - // value method cpu_dmem_master_m_arburst - output [1 : 0] cpu_dmem_master_arburst; - - // value method cpu_dmem_master_m_arlock - output cpu_dmem_master_arlock; - - // value method cpu_dmem_master_m_arcache - output [3 : 0] cpu_dmem_master_arcache; - - // value method cpu_dmem_master_m_arprot - output [2 : 0] cpu_dmem_master_arprot; - - // value method cpu_dmem_master_m_arqos - output [3 : 0] cpu_dmem_master_arqos; - - // value method cpu_dmem_master_m_arregion - output [3 : 0] cpu_dmem_master_arregion; - - // value method cpu_dmem_master_m_aruser - - // action method cpu_dmem_master_m_arready - input cpu_dmem_master_arready; - - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; - input [63 : 0] cpu_dmem_master_rdata; - input [1 : 0] cpu_dmem_master_rresp; - input cpu_dmem_master_rlast; - - // value method cpu_dmem_master_m_rready - output cpu_dmem_master_rready; - - // action method core_external_interrupt_sources_0_m_interrupt_req - input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_1_m_interrupt_req - input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_2_m_interrupt_req - input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_3_m_interrupt_req - input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_4_m_interrupt_req - input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_5_m_interrupt_req - input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_6_m_interrupt_req - input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_7_m_interrupt_req - input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_8_m_interrupt_req - input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_9_m_interrupt_req - input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_10_m_interrupt_req - input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_11_m_interrupt_req - input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_12_m_interrupt_req - input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_13_m_interrupt_req - input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_14_m_interrupt_req - input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_15_m_interrupt_req - input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // signals for module outputs - wire [63 : 0] cpu_dmem_master_araddr, - cpu_dmem_master_awaddr, - cpu_dmem_master_wdata, - cpu_imem_master_araddr, - cpu_imem_master_awaddr, - cpu_imem_master_wdata; - wire [7 : 0] cpu_dmem_master_arlen, - cpu_dmem_master_awlen, - cpu_dmem_master_wstrb, - cpu_imem_master_arlen, - cpu_imem_master_awlen, - cpu_imem_master_wstrb; - wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, - cpu_dmem_master_arqos, - cpu_dmem_master_arregion, - cpu_dmem_master_awcache, - cpu_dmem_master_awid, - cpu_dmem_master_awqos, - cpu_dmem_master_awregion, - cpu_dmem_master_wid, - cpu_imem_master_arcache, - cpu_imem_master_arid, - cpu_imem_master_arqos, - cpu_imem_master_arregion, - cpu_imem_master_awcache, - cpu_imem_master_awid, - cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; - wire [2 : 0] cpu_dmem_master_arprot, - cpu_dmem_master_arsize, - cpu_dmem_master_awprot, - cpu_dmem_master_awsize, - cpu_imem_master_arprot, - cpu_imem_master_arsize, - cpu_imem_master_awprot, - cpu_imem_master_awsize; - wire [1 : 0] cpu_dmem_master_arburst, - cpu_dmem_master_awburst, - cpu_imem_master_arburst, - cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_set_verbosity, - cpu_dmem_master_arlock, - cpu_dmem_master_arvalid, - cpu_dmem_master_awlock, - cpu_dmem_master_awvalid, - cpu_dmem_master_bready, - cpu_dmem_master_rready, - cpu_dmem_master_wlast, - cpu_dmem_master_wvalid, - cpu_imem_master_arlock, - cpu_imem_master_arvalid, - cpu_imem_master_awlock, - cpu_imem_master_awvalid, - cpu_imem_master_bready, - cpu_imem_master_rready, - cpu_imem_master_wlast, - cpu_imem_master_wvalid, - cpu_reset_server_response_get; - - // ports of submodule cpu - wire [63 : 0] cpu$dmem_master_araddr, - cpu$dmem_master_awaddr, - cpu$dmem_master_rdata, - cpu$dmem_master_wdata, - cpu$imem_master_araddr, - cpu$imem_master_awaddr, - cpu$imem_master_rdata, - cpu$imem_master_wdata, - cpu$set_verbosity_logdelay; - wire [7 : 0] cpu$dmem_master_arlen, - cpu$dmem_master_awlen, - cpu$dmem_master_wstrb, - cpu$imem_master_arlen, - cpu$imem_master_awlen, - cpu$imem_master_wstrb; - wire [3 : 0] cpu$dmem_master_arcache, - cpu$dmem_master_arid, - cpu$dmem_master_arqos, - cpu$dmem_master_arregion, - cpu$dmem_master_awcache, - cpu$dmem_master_awid, - cpu$dmem_master_awqos, - cpu$dmem_master_awregion, - cpu$dmem_master_bid, - cpu$dmem_master_rid, - cpu$dmem_master_wid, - cpu$imem_master_arcache, - cpu$imem_master_arid, - cpu$imem_master_arqos, - cpu$imem_master_arregion, - cpu$imem_master_awcache, - cpu$imem_master_awid, - cpu$imem_master_awqos, - cpu$imem_master_awregion, - cpu$imem_master_bid, - cpu$imem_master_rid, - cpu$imem_master_wid, - cpu$set_verbosity_verbosity; - wire [2 : 0] cpu$dmem_master_arprot, - cpu$dmem_master_arsize, - cpu$dmem_master_awprot, - cpu$dmem_master_awsize, - cpu$imem_master_arprot, - cpu$imem_master_arsize, - cpu$imem_master_awprot, - cpu$imem_master_awsize; - wire [1 : 0] cpu$dmem_master_arburst, - cpu$dmem_master_awburst, - cpu$dmem_master_bresp, - cpu$dmem_master_rresp, - cpu$imem_master_arburst, - cpu$imem_master_awburst, - cpu$imem_master_bresp, - cpu$imem_master_rresp; - wire cpu$EN_hart0_server_reset_request_put, - cpu$EN_hart0_server_reset_response_get, - cpu$EN_set_verbosity, - cpu$RDY_hart0_server_reset_request_put, - cpu$RDY_hart0_server_reset_response_get, - cpu$dmem_master_arlock, - cpu$dmem_master_arready, - cpu$dmem_master_arvalid, - cpu$dmem_master_awlock, - cpu$dmem_master_awready, - cpu$dmem_master_awvalid, - cpu$dmem_master_bready, - cpu$dmem_master_bvalid, - cpu$dmem_master_rlast, - cpu$dmem_master_rready, - cpu$dmem_master_rvalid, - cpu$dmem_master_wlast, - cpu$dmem_master_wready, - cpu$dmem_master_wvalid, - cpu$hart0_server_reset_request_put, - cpu$hart0_server_reset_response_get, - cpu$imem_master_arlock, - cpu$imem_master_arready, - cpu$imem_master_arvalid, - cpu$imem_master_awlock, - cpu$imem_master_awready, - cpu$imem_master_awvalid, - cpu$imem_master_bready, - cpu$imem_master_bvalid, - cpu$imem_master_rlast, - cpu$imem_master_rready, - cpu$imem_master_rvalid, - cpu$imem_master_wlast, - cpu$imem_master_wready, - cpu$imem_master_wvalid, - cpu$m_external_interrupt_req_set_not_clear, - cpu$nmi_req_set_not_clear, - cpu$s_external_interrupt_req_set_not_clear, - cpu$software_interrupt_req_set_not_clear, - cpu$timer_interrupt_req_set_not_clear; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_araddr, - fabric_2x3$v_to_slaves_2_awaddr, - fabric_2x3$v_to_slaves_2_rdata, - fabric_2x3$v_to_slaves_2_wdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb, - fabric_2x3$v_to_slaves_2_arlen, - fabric_2x3$v_to_slaves_2_awlen, - fabric_2x3$v_to_slaves_2_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_wid, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, - fabric_2x3$v_to_slaves_2_arcache, - fabric_2x3$v_to_slaves_2_arid, - fabric_2x3$v_to_slaves_2_arqos, - fabric_2x3$v_to_slaves_2_arregion, - fabric_2x3$v_to_slaves_2_awcache, - fabric_2x3$v_to_slaves_2_awid, - fabric_2x3$v_to_slaves_2_awqos, - fabric_2x3$v_to_slaves_2_awregion, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize, - fabric_2x3$v_to_slaves_2_arprot, - fabric_2x3$v_to_slaves_2_arsize, - fabric_2x3$v_to_slaves_2_awprot, - fabric_2x3$v_to_slaves_2_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_arburst, - fabric_2x3$v_to_slaves_2_awburst, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arlock, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_arvalid, - fabric_2x3$v_to_slaves_2_awlock, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_awvalid, - fabric_2x3$v_to_slaves_2_bready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rready, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wlast, - fabric_2x3$v_to_slaves_2_wready, - fabric_2x3$v_to_slaves_2_wvalid; - - // ports of submodule near_mem_io - wire [63 : 0] near_mem_io$axi4_slave_araddr, - near_mem_io$axi4_slave_awaddr, - near_mem_io$axi4_slave_rdata, - near_mem_io$axi4_slave_wdata, - near_mem_io$set_addr_map_addr_base, - near_mem_io$set_addr_map_addr_lim; - wire [7 : 0] near_mem_io$axi4_slave_arlen, - near_mem_io$axi4_slave_awlen, - near_mem_io$axi4_slave_wstrb; - wire [3 : 0] near_mem_io$axi4_slave_arcache, - near_mem_io$axi4_slave_arid, - near_mem_io$axi4_slave_arqos, - near_mem_io$axi4_slave_arregion, - near_mem_io$axi4_slave_awcache, - near_mem_io$axi4_slave_awid, - near_mem_io$axi4_slave_awqos, - near_mem_io$axi4_slave_awregion, - near_mem_io$axi4_slave_bid, - near_mem_io$axi4_slave_rid, - near_mem_io$axi4_slave_wid; - wire [2 : 0] near_mem_io$axi4_slave_arprot, - near_mem_io$axi4_slave_arsize, - near_mem_io$axi4_slave_awprot, - near_mem_io$axi4_slave_awsize; - wire [1 : 0] near_mem_io$axi4_slave_arburst, - near_mem_io$axi4_slave_awburst, - near_mem_io$axi4_slave_bresp, - near_mem_io$axi4_slave_rresp; - wire near_mem_io$EN_get_sw_interrupt_req_get, - near_mem_io$EN_get_timer_interrupt_req_get, - near_mem_io$EN_server_reset_request_put, - near_mem_io$EN_server_reset_response_get, - near_mem_io$EN_set_addr_map, - near_mem_io$RDY_get_sw_interrupt_req_get, - near_mem_io$RDY_get_timer_interrupt_req_get, - near_mem_io$RDY_server_reset_request_put, - near_mem_io$RDY_server_reset_response_get, - near_mem_io$axi4_slave_arlock, - near_mem_io$axi4_slave_arready, - near_mem_io$axi4_slave_arvalid, - near_mem_io$axi4_slave_awlock, - near_mem_io$axi4_slave_awready, - near_mem_io$axi4_slave_awvalid, - near_mem_io$axi4_slave_bready, - near_mem_io$axi4_slave_bvalid, - near_mem_io$axi4_slave_rlast, - near_mem_io$axi4_slave_rready, - near_mem_io$axi4_slave_rvalid, - near_mem_io$axi4_slave_wlast, - near_mem_io$axi4_slave_wready, - near_mem_io$axi4_slave_wvalid, - near_mem_io$get_sw_interrupt_req_get, - near_mem_io$get_timer_interrupt_req_get; - - // ports of submodule plic - wire [63 : 0] plic$axi4_slave_araddr, - plic$axi4_slave_awaddr, - plic$axi4_slave_rdata, - plic$axi4_slave_wdata, - plic$set_addr_map_addr_base, - plic$set_addr_map_addr_lim; - wire [7 : 0] plic$axi4_slave_arlen, - plic$axi4_slave_awlen, - plic$axi4_slave_wstrb; - wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, - plic$axi4_slave_arqos, - plic$axi4_slave_arregion, - plic$axi4_slave_awcache, - plic$axi4_slave_awid, - plic$axi4_slave_awqos, - plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, - plic$axi4_slave_wid, - plic$set_verbosity_verbosity; - wire [2 : 0] plic$axi4_slave_arprot, - plic$axi4_slave_arsize, - plic$axi4_slave_awprot, - plic$axi4_slave_awsize; - wire [1 : 0] plic$axi4_slave_arburst, - plic$axi4_slave_awburst, - plic$axi4_slave_bresp, - plic$axi4_slave_rresp; - wire plic$EN_server_reset_request_put, - plic$EN_server_reset_response_get, - plic$EN_set_addr_map, - plic$EN_set_verbosity, - plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, - plic$axi4_slave_arlock, - plic$axi4_slave_arready, - plic$axi4_slave_arvalid, - plic$axi4_slave_awlock, - plic$axi4_slave_awready, - plic$axi4_slave_awvalid, - plic$axi4_slave_bready, - plic$axi4_slave_bvalid, - plic$axi4_slave_rlast, - plic$axi4_slave_rready, - plic$axi4_slave_rvalid, - plic$axi4_slave_wlast, - plic$axi4_slave_wready, - plic$axi4_slave_wvalid, - plic$v_sources_0_m_interrupt_req_set_not_clear, - plic$v_sources_10_m_interrupt_req_set_not_clear, - plic$v_sources_11_m_interrupt_req_set_not_clear, - plic$v_sources_12_m_interrupt_req_set_not_clear, - plic$v_sources_13_m_interrupt_req_set_not_clear, - plic$v_sources_14_m_interrupt_req_set_not_clear, - plic$v_sources_15_m_interrupt_req_set_not_clear, - plic$v_sources_1_m_interrupt_req_set_not_clear, - plic$v_sources_2_m_interrupt_req_set_not_clear, - plic$v_sources_3_m_interrupt_req_set_not_clear, - plic$v_sources_4_m_interrupt_req_set_not_clear, - plic$v_sources_5_m_interrupt_req_set_not_clear, - plic$v_sources_6_m_interrupt_req_set_not_clear, - plic$v_sources_7_m_interrupt_req_set_not_clear, - plic$v_sources_8_m_interrupt_req_set_not_clear, - plic$v_sources_9_m_interrupt_req_set_not_clear, - plic$v_targets_0_m_eip, - plic$v_targets_1_m_eip; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_sw_interrupts, - CAN_FIRE_RL_rl_relay_timer_interrupts, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_nmi_req, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_sw_interrupts, - WILL_FIRE_RL_rl_relay_timer_interrupts, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_nmi_req, - WILL_FIRE_set_verbosity; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4310; - reg [31 : 0] v__h4551; - reg [31 : 0] v__h4304; - reg [31 : 0] v__h4545; - // synopsys translate_on - - // remaining internal signals - wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // actionvalue method cpu_reset_server_response_get - assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ; - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; - - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - - // value method cpu_imem_master_m_awid - assign cpu_imem_master_awid = cpu$imem_master_awid ; - - // value method cpu_imem_master_m_awaddr - assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; - - // value method cpu_imem_master_m_awlen - assign cpu_imem_master_awlen = cpu$imem_master_awlen ; - - // value method cpu_imem_master_m_awsize - assign cpu_imem_master_awsize = cpu$imem_master_awsize ; - - // value method cpu_imem_master_m_awburst - assign cpu_imem_master_awburst = cpu$imem_master_awburst ; - - // value method cpu_imem_master_m_awlock - assign cpu_imem_master_awlock = cpu$imem_master_awlock ; - - // value method cpu_imem_master_m_awcache - assign cpu_imem_master_awcache = cpu$imem_master_awcache ; - - // value method cpu_imem_master_m_awprot - assign cpu_imem_master_awprot = cpu$imem_master_awprot ; - - // value method cpu_imem_master_m_awqos - assign cpu_imem_master_awqos = cpu$imem_master_awqos ; - - // value method cpu_imem_master_m_awregion - assign cpu_imem_master_awregion = cpu$imem_master_awregion ; - - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; - - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; - - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = cpu$imem_master_wid ; - - // value method cpu_imem_master_m_wdata - assign cpu_imem_master_wdata = cpu$imem_master_wdata ; - - // value method cpu_imem_master_m_wstrb - assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; - - // value method cpu_imem_master_m_wlast - assign cpu_imem_master_wlast = cpu$imem_master_wlast ; - - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; - - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = cpu$imem_master_bready ; - - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; - - // value method cpu_imem_master_m_arid - assign cpu_imem_master_arid = cpu$imem_master_arid ; - - // value method cpu_imem_master_m_araddr - assign cpu_imem_master_araddr = cpu$imem_master_araddr ; - - // value method cpu_imem_master_m_arlen - assign cpu_imem_master_arlen = cpu$imem_master_arlen ; - - // value method cpu_imem_master_m_arsize - assign cpu_imem_master_arsize = cpu$imem_master_arsize ; - - // value method cpu_imem_master_m_arburst - assign cpu_imem_master_arburst = cpu$imem_master_arburst ; - - // value method cpu_imem_master_m_arlock - assign cpu_imem_master_arlock = cpu$imem_master_arlock ; - - // value method cpu_imem_master_m_arcache - assign cpu_imem_master_arcache = cpu$imem_master_arcache ; - - // value method cpu_imem_master_m_arprot - assign cpu_imem_master_arprot = cpu$imem_master_arprot ; - - // value method cpu_imem_master_m_arqos - assign cpu_imem_master_arqos = cpu$imem_master_arqos ; - - // value method cpu_imem_master_m_arregion - assign cpu_imem_master_arregion = cpu$imem_master_arregion ; - - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; - - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - - // value method cpu_imem_master_m_rready - assign cpu_imem_master_rready = cpu$imem_master_rready ; - - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; - - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; - - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; - - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; - - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; - - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; - - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; - - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; - - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; - - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; - - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; - - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; - - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; - - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; - - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; - - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; - - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; - - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; - - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; - - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; - - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; - - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; - - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; - - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; - - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; - - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; - - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; - - // action method core_external_interrupt_sources_0_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_1_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_2_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_3_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_4_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_5_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_6_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_7_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_8_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_9_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_10_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_11_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_12_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_13_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_14_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_15_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // submodule cpu - mkCPU cpu(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(cpu$dmem_master_arready), - .dmem_master_awready(cpu$dmem_master_awready), - .dmem_master_bid(cpu$dmem_master_bid), - .dmem_master_bresp(cpu$dmem_master_bresp), - .dmem_master_bvalid(cpu$dmem_master_bvalid), - .dmem_master_rdata(cpu$dmem_master_rdata), - .dmem_master_rid(cpu$dmem_master_rid), - .dmem_master_rlast(cpu$dmem_master_rlast), - .dmem_master_rresp(cpu$dmem_master_rresp), - .dmem_master_rvalid(cpu$dmem_master_rvalid), - .dmem_master_wready(cpu$dmem_master_wready), - .hart0_server_reset_request_put(cpu$hart0_server_reset_request_put), - .imem_master_arready(cpu$imem_master_arready), - .imem_master_awready(cpu$imem_master_awready), - .imem_master_bid(cpu$imem_master_bid), - .imem_master_bresp(cpu$imem_master_bresp), - .imem_master_bvalid(cpu$imem_master_bvalid), - .imem_master_rdata(cpu$imem_master_rdata), - .imem_master_rid(cpu$imem_master_rid), - .imem_master_rlast(cpu$imem_master_rlast), - .imem_master_rresp(cpu$imem_master_rresp), - .imem_master_rvalid(cpu$imem_master_rvalid), - .imem_master_wready(cpu$imem_master_wready), - .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), - .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), - .s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear), - .set_verbosity_logdelay(cpu$set_verbosity_logdelay), - .set_verbosity_verbosity(cpu$set_verbosity_verbosity), - .software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), - .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), - .EN_set_verbosity(cpu$EN_set_verbosity), - .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), - .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), - .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), - .imem_master_awvalid(cpu$imem_master_awvalid), - .imem_master_awid(cpu$imem_master_awid), - .imem_master_awaddr(cpu$imem_master_awaddr), - .imem_master_awlen(cpu$imem_master_awlen), - .imem_master_awsize(cpu$imem_master_awsize), - .imem_master_awburst(cpu$imem_master_awburst), - .imem_master_awlock(cpu$imem_master_awlock), - .imem_master_awcache(cpu$imem_master_awcache), - .imem_master_awprot(cpu$imem_master_awprot), - .imem_master_awqos(cpu$imem_master_awqos), - .imem_master_awregion(cpu$imem_master_awregion), - .imem_master_wvalid(cpu$imem_master_wvalid), - .imem_master_wid(cpu$imem_master_wid), - .imem_master_wdata(cpu$imem_master_wdata), - .imem_master_wstrb(cpu$imem_master_wstrb), - .imem_master_wlast(cpu$imem_master_wlast), - .imem_master_bready(cpu$imem_master_bready), - .imem_master_arvalid(cpu$imem_master_arvalid), - .imem_master_arid(cpu$imem_master_arid), - .imem_master_araddr(cpu$imem_master_araddr), - .imem_master_arlen(cpu$imem_master_arlen), - .imem_master_arsize(cpu$imem_master_arsize), - .imem_master_arburst(cpu$imem_master_arburst), - .imem_master_arlock(cpu$imem_master_arlock), - .imem_master_arcache(cpu$imem_master_arcache), - .imem_master_arprot(cpu$imem_master_arprot), - .imem_master_arqos(cpu$imem_master_arqos), - .imem_master_arregion(cpu$imem_master_arregion), - .imem_master_rready(cpu$imem_master_rready), - .dmem_master_awvalid(cpu$dmem_master_awvalid), - .dmem_master_awid(cpu$dmem_master_awid), - .dmem_master_awaddr(cpu$dmem_master_awaddr), - .dmem_master_awlen(cpu$dmem_master_awlen), - .dmem_master_awsize(cpu$dmem_master_awsize), - .dmem_master_awburst(cpu$dmem_master_awburst), - .dmem_master_awlock(cpu$dmem_master_awlock), - .dmem_master_awcache(cpu$dmem_master_awcache), - .dmem_master_awprot(cpu$dmem_master_awprot), - .dmem_master_awqos(cpu$dmem_master_awqos), - .dmem_master_awregion(cpu$dmem_master_awregion), - .dmem_master_wvalid(cpu$dmem_master_wvalid), - .dmem_master_wid(cpu$dmem_master_wid), - .dmem_master_wdata(cpu$dmem_master_wdata), - .dmem_master_wstrb(cpu$dmem_master_wstrb), - .dmem_master_wlast(cpu$dmem_master_wlast), - .dmem_master_bready(cpu$dmem_master_bready), - .dmem_master_arvalid(cpu$dmem_master_arvalid), - .dmem_master_arid(cpu$dmem_master_arid), - .dmem_master_araddr(cpu$dmem_master_araddr), - .dmem_master_arlen(cpu$dmem_master_arlen), - .dmem_master_arsize(cpu$dmem_master_arsize), - .dmem_master_arburst(cpu$dmem_master_arburst), - .dmem_master_arlock(cpu$dmem_master_arlock), - .dmem_master_arcache(cpu$dmem_master_arcache), - .dmem_master_arprot(cpu$dmem_master_arprot), - .dmem_master_arqos(cpu$dmem_master_arqos), - .dmem_master_arregion(cpu$dmem_master_arregion), - .dmem_master_rready(cpu$dmem_master_rready), - .RDY_set_verbosity()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(), - .v_from_masters_1_wready(), - .v_from_masters_1_bvalid(), - .v_from_masters_1_bid(), - .v_from_masters_1_bresp(), - .v_from_masters_1_arready(), - .v_from_masters_1_rvalid(), - .v_from_masters_1_rid(), - .v_from_masters_1_rdata(), - .v_from_masters_1_rresp(), - .v_from_masters_1_rlast(), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); - - // submodule near_mem_io - mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(near_mem_io$axi4_slave_araddr), - .axi4_slave_arburst(near_mem_io$axi4_slave_arburst), - .axi4_slave_arcache(near_mem_io$axi4_slave_arcache), - .axi4_slave_arid(near_mem_io$axi4_slave_arid), - .axi4_slave_arlen(near_mem_io$axi4_slave_arlen), - .axi4_slave_arlock(near_mem_io$axi4_slave_arlock), - .axi4_slave_arprot(near_mem_io$axi4_slave_arprot), - .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), - .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), - .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), - .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), - .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), - .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), - .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), - .axi4_slave_awid(near_mem_io$axi4_slave_awid), - .axi4_slave_awlen(near_mem_io$axi4_slave_awlen), - .axi4_slave_awlock(near_mem_io$axi4_slave_awlock), - .axi4_slave_awprot(near_mem_io$axi4_slave_awprot), - .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), - .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), - .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), - .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), - .axi4_slave_bready(near_mem_io$axi4_slave_bready), - .axi4_slave_rready(near_mem_io$axi4_slave_rready), - .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), - .axi4_slave_wid(near_mem_io$axi4_slave_wid), - .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), - .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), - .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), - .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), - .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), - .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), - .EN_set_addr_map(near_mem_io$EN_set_addr_map), - .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), - .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), - .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(near_mem_io$axi4_slave_awready), - .axi4_slave_wready(near_mem_io$axi4_slave_wready), - .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), - .axi4_slave_bid(near_mem_io$axi4_slave_bid), - .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), - .axi4_slave_arready(near_mem_io$axi4_slave_arready), - .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), - .axi4_slave_rid(near_mem_io$axi4_slave_rid), - .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), - .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), - .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), - .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), - .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), - .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), - .RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get)); - - // submodule plic - mkPLIC_16_2_7 plic(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(plic$axi4_slave_araddr), - .axi4_slave_arburst(plic$axi4_slave_arburst), - .axi4_slave_arcache(plic$axi4_slave_arcache), - .axi4_slave_arid(plic$axi4_slave_arid), - .axi4_slave_arlen(plic$axi4_slave_arlen), - .axi4_slave_arlock(plic$axi4_slave_arlock), - .axi4_slave_arprot(plic$axi4_slave_arprot), - .axi4_slave_arqos(plic$axi4_slave_arqos), - .axi4_slave_arregion(plic$axi4_slave_arregion), - .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), - .axi4_slave_awaddr(plic$axi4_slave_awaddr), - .axi4_slave_awburst(plic$axi4_slave_awburst), - .axi4_slave_awcache(plic$axi4_slave_awcache), - .axi4_slave_awid(plic$axi4_slave_awid), - .axi4_slave_awlen(plic$axi4_slave_awlen), - .axi4_slave_awlock(plic$axi4_slave_awlock), - .axi4_slave_awprot(plic$axi4_slave_awprot), - .axi4_slave_awqos(plic$axi4_slave_awqos), - .axi4_slave_awregion(plic$axi4_slave_awregion), - .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_bready(plic$axi4_slave_bready), - .axi4_slave_rready(plic$axi4_slave_rready), - .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), - .axi4_slave_wlast(plic$axi4_slave_wlast), - .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .set_addr_map_addr_base(plic$set_addr_map_addr_base), - .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), - .set_verbosity_verbosity(plic$set_verbosity_verbosity), - .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), - .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), - .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), - .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), - .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), - .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), - .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), - .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), - .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), - .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), - .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), - .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), - .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), - .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), - .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), - .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), - .EN_set_verbosity(plic$EN_set_verbosity), - .EN_show_PLIC_state(plic$EN_show_PLIC_state), - .EN_server_reset_request_put(plic$EN_server_reset_request_put), - .EN_server_reset_response_get(plic$EN_server_reset_response_get), - .EN_set_addr_map(plic$EN_set_addr_map), - .RDY_set_verbosity(), - .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(plic$axi4_slave_awready), - .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), - .axi4_slave_bid(plic$axi4_slave_bid), - .axi4_slave_bresp(plic$axi4_slave_bresp), - .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), - .axi4_slave_rid(plic$axi4_slave_rid), - .axi4_slave_rdata(plic$axi4_slave_rdata), - .axi4_slave_rresp(plic$axi4_slave_rresp), - .axi4_slave_rlast(plic$axi4_slave_rlast), - .v_targets_0_m_eip(plic$v_targets_0_m_eip), - .v_targets_1_m_eip(plic$v_targets_1_m_eip)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_relay_sw_interrupts - assign CAN_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // rule RL_rl_relay_timer_interrupts - assign CAN_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - - // rule RL_rl_relay_external_interrupts - assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule cpu - assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; - assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; - assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; - assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; - assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; - assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ; - assign cpu$imem_master_arready = cpu_imem_master_arready ; - assign cpu$imem_master_awready = cpu_imem_master_awready ; - assign cpu$imem_master_bid = cpu_imem_master_bid ; - assign cpu$imem_master_bresp = cpu_imem_master_bresp ; - assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; - assign cpu$imem_master_rdata = cpu_imem_master_rdata ; - assign cpu$imem_master_rid = cpu_imem_master_rid ; - assign cpu$imem_master_rlast = cpu_imem_master_rlast ; - assign cpu$imem_master_rresp = cpu_imem_master_rresp ; - assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; - assign cpu$imem_master_wready = cpu_imem_master_wready ; - assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; - assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; - assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; - assign cpu$software_interrupt_req_set_not_clear = - near_mem_io$get_sw_interrupt_req_get ; - assign cpu$timer_interrupt_req_set_not_clear = - near_mem_io$get_timer_interrupt_req_get ; - assign cpu$EN_hart0_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign cpu$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign cpu$EN_set_verbosity = EN_set_verbosity ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = cpu_reset_server_request_put ; - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ; - assign f_reset_rsps$ENQ = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; - assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; - assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; - assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; - assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; - assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; - assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; - assign fabric_2x3$v_from_masters_0_wid = cpu$dmem_master_wid ; - assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_awaddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_bready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_wdata = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wstrb = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; - assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; - - // submodule near_mem_io - assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign near_mem_io$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; - assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; - assign near_mem_io$set_addr_map_addr_base = - soc_map$m_near_mem_io_addr_base ; - assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; - assign near_mem_io$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign near_mem_io$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_set_addr_map = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_get_timer_interrupt_req_get = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign near_mem_io$EN_get_sw_interrupt_req_get = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_2_wid ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; - assign plic$set_verbosity_verbosity = 4'h0 ; - assign plic$v_sources_0_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; - assign plic$v_sources_10_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; - assign plic$v_sources_11_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; - assign plic$v_sources_12_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; - assign plic$v_sources_13_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; - assign plic$v_sources_14_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; - assign plic$v_sources_15_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; - assign plic$v_sources_1_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; - assign plic$v_sources_2_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; - assign plic$v_sources_3_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; - assign plic$v_sources_4_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; - assign plic$v_sources_5_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; - assign plic$v_sources_6_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; - assign plic$v_sources_7_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; - assign plic$v_sources_8_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; - assign plic$v_sources_9_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; - assign plic$EN_set_verbosity = 1'b0 ; - assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - cpu$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h4310 = $stime; - #0; - end - v__h4304 = v__h4310 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4304); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h4551 = $stime; - #0; - end - v__h4545 = v__h4551 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4545); - end - // synopsys translate_on -endmodule // mkCore - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Core.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Core.v deleted file mode 100644 index 46bcedc6..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Core.v +++ /dev/null @@ -1,8674 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// valid O 1 -// word_fst O 64 -// word_snd O 5 -// CLK I 1 clock -// RST_N I 1 reset -// req_opcode I 7 -// req_f7 I 7 -// req_rm I 3 -// req_rs2 I 5 -// req_v1 I 64 -// req_v2 I 64 -// req_v3 I 64 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFBox_Core(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_opcode, - req_f7, - req_rm, - req_rs2, - req_v1, - req_v2, - req_v3, - EN_req, - - valid, - - word_fst, - - word_snd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [6 : 0] req_opcode; - input [6 : 0] req_f7; - input [2 : 0] req_rm; - input [4 : 0] req_rs2; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input [63 : 0] req_v3; - input EN_req; - - // value method valid - output valid; - - // value method word_fst - output [63 : 0] word_fst; - - // value method word_snd - output [4 : 0] word_snd; - - // signals for module outputs - wire [63 : 0] word_fst; - wire [4 : 0] word_snd; - wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid; - - // inlined wires - wire [68 : 0] dw_result$wget; - wire dw_valid$wget, dw_valid$whas; - - // register requestR - reg [214 : 0] requestR; - wire [214 : 0] requestR$D_IN; - wire requestR$EN; - - // register resultR - reg [69 : 0] resultR; - reg [69 : 0] resultR$D_IN; - wire resultR$EN; - - // register stateR - reg [1 : 0] stateR; - reg [1 : 0] stateR$D_IN; - wire stateR$EN; - - // ports of submodule fpu - reg [201 : 0] fpu$server_core_request_put; - wire [69 : 0] fpu$server_core_response_get; - wire fpu$EN_server_core_request_put, - fpu$EN_server_core_response_get, - fpu$EN_server_reset_request_put, - fpu$EN_server_reset_response_get, - fpu$RDY_server_core_request_put, - fpu$RDY_server_core_response_get, - fpu$RDY_server_reset_request_put, - fpu$RDY_server_reset_response_get; - - // ports of submodule frmFpuF - wire frmFpuF$CLR, frmFpuF$DEQ, frmFpuF$D_IN, frmFpuF$ENQ; - - // ports of submodule resetReqsF - wire resetReqsF$CLR, - resetReqsF$DEQ, - resetReqsF$EMPTY_N, - resetReqsF$ENQ, - resetReqsF$FULL_N; - - // ports of submodule resetRspsF - wire resetRspsF$CLR, - resetRspsF$DEQ, - resetRspsF$EMPTY_N, - resetRspsF$ENQ, - resetRspsF$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_doFADD_D, - CAN_FIRE_RL_doFADD_S, - CAN_FIRE_RL_doFCLASS_D, - CAN_FIRE_RL_doFCLASS_S, - CAN_FIRE_RL_doFCVT_D_S, - CAN_FIRE_RL_doFCVT_D_W, - CAN_FIRE_RL_doFCVT_D_WU, - CAN_FIRE_RL_doFCVT_S_D, - CAN_FIRE_RL_doFCVT_S_W, - CAN_FIRE_RL_doFCVT_S_WU, - CAN_FIRE_RL_doFCVT_WU_D, - CAN_FIRE_RL_doFCVT_WU_S, - CAN_FIRE_RL_doFCVT_W_D, - CAN_FIRE_RL_doFCVT_W_S, - CAN_FIRE_RL_doFDIV_D, - CAN_FIRE_RL_doFDIV_S, - CAN_FIRE_RL_doFEQ_D, - CAN_FIRE_RL_doFEQ_S, - CAN_FIRE_RL_doFLE_D, - CAN_FIRE_RL_doFLE_S, - CAN_FIRE_RL_doFLT_D, - CAN_FIRE_RL_doFLT_S, - CAN_FIRE_RL_doFMADD_D, - CAN_FIRE_RL_doFMADD_S, - CAN_FIRE_RL_doFMAX_D, - CAN_FIRE_RL_doFMAX_S, - CAN_FIRE_RL_doFMIN_D, - CAN_FIRE_RL_doFMIN_S, - CAN_FIRE_RL_doFMSUB_D, - CAN_FIRE_RL_doFMSUB_S, - CAN_FIRE_RL_doFMUL_D, - CAN_FIRE_RL_doFMUL_S, - CAN_FIRE_RL_doFMV_D_X, - CAN_FIRE_RL_doFMV_W_X, - CAN_FIRE_RL_doFMV_X_D, - CAN_FIRE_RL_doFMV_X_W, - CAN_FIRE_RL_doFNMADD_D, - CAN_FIRE_RL_doFNMADD_S, - CAN_FIRE_RL_doFNMSUB_D, - CAN_FIRE_RL_doFNMSUB_S, - CAN_FIRE_RL_doFSGNJN_D, - CAN_FIRE_RL_doFSGNJN_S, - CAN_FIRE_RL_doFSGNJX_D, - CAN_FIRE_RL_doFSGNJX_S, - CAN_FIRE_RL_doFSGNJ_D, - CAN_FIRE_RL_doFSGNJ_S, - CAN_FIRE_RL_doFSQRT_D, - CAN_FIRE_RL_doFSQRT_S, - CAN_FIRE_RL_doFSUB_D, - CAN_FIRE_RL_doFSUB_S, - CAN_FIRE_RL_rl_drive_fpu_result, - CAN_FIRE_RL_rl_get_fpu_result, - CAN_FIRE_RL_rl_reset_begin, - CAN_FIRE_RL_rl_reset_end, - CAN_FIRE_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_RL_doFADD_D, - WILL_FIRE_RL_doFADD_S, - WILL_FIRE_RL_doFCLASS_D, - WILL_FIRE_RL_doFCLASS_S, - WILL_FIRE_RL_doFCVT_D_S, - WILL_FIRE_RL_doFCVT_D_W, - WILL_FIRE_RL_doFCVT_D_WU, - WILL_FIRE_RL_doFCVT_S_D, - WILL_FIRE_RL_doFCVT_S_W, - WILL_FIRE_RL_doFCVT_S_WU, - WILL_FIRE_RL_doFCVT_WU_D, - WILL_FIRE_RL_doFCVT_WU_S, - WILL_FIRE_RL_doFCVT_W_D, - WILL_FIRE_RL_doFCVT_W_S, - WILL_FIRE_RL_doFDIV_D, - WILL_FIRE_RL_doFDIV_S, - WILL_FIRE_RL_doFEQ_D, - WILL_FIRE_RL_doFEQ_S, - WILL_FIRE_RL_doFLE_D, - WILL_FIRE_RL_doFLE_S, - WILL_FIRE_RL_doFLT_D, - WILL_FIRE_RL_doFLT_S, - WILL_FIRE_RL_doFMADD_D, - WILL_FIRE_RL_doFMADD_S, - WILL_FIRE_RL_doFMAX_D, - WILL_FIRE_RL_doFMAX_S, - WILL_FIRE_RL_doFMIN_D, - WILL_FIRE_RL_doFMIN_S, - WILL_FIRE_RL_doFMSUB_D, - WILL_FIRE_RL_doFMSUB_S, - WILL_FIRE_RL_doFMUL_D, - WILL_FIRE_RL_doFMUL_S, - WILL_FIRE_RL_doFMV_D_X, - WILL_FIRE_RL_doFMV_W_X, - WILL_FIRE_RL_doFMV_X_D, - WILL_FIRE_RL_doFMV_X_W, - WILL_FIRE_RL_doFNMADD_D, - WILL_FIRE_RL_doFNMADD_S, - WILL_FIRE_RL_doFNMSUB_D, - WILL_FIRE_RL_doFNMSUB_S, - WILL_FIRE_RL_doFSGNJN_D, - WILL_FIRE_RL_doFSGNJN_S, - WILL_FIRE_RL_doFSGNJX_D, - WILL_FIRE_RL_doFSGNJX_S, - WILL_FIRE_RL_doFSGNJ_D, - WILL_FIRE_RL_doFSGNJ_S, - WILL_FIRE_RL_doFSQRT_D, - WILL_FIRE_RL_doFSQRT_S, - WILL_FIRE_RL_doFSUB_D, - WILL_FIRE_RL_doFSUB_S, - WILL_FIRE_RL_rl_drive_fpu_result, - WILL_FIRE_RL_rl_get_fpu_result, - WILL_FIRE_RL_rl_reset_begin, - WILL_FIRE_RL_rl_reset_end, - WILL_FIRE_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // inputs to muxes for submodule ports - wire [214 : 0] MUX_requestR$write_1__VAL_2; - wire [201 : 0] MUX_fpu$server_core_request_put_1__VAL_1, - MUX_fpu$server_core_request_put_1__VAL_10, - MUX_fpu$server_core_request_put_1__VAL_11, - MUX_fpu$server_core_request_put_1__VAL_12, - MUX_fpu$server_core_request_put_1__VAL_13, - MUX_fpu$server_core_request_put_1__VAL_14, - MUX_fpu$server_core_request_put_1__VAL_15, - MUX_fpu$server_core_request_put_1__VAL_16, - MUX_fpu$server_core_request_put_1__VAL_17, - MUX_fpu$server_core_request_put_1__VAL_18, - MUX_fpu$server_core_request_put_1__VAL_2, - MUX_fpu$server_core_request_put_1__VAL_3, - MUX_fpu$server_core_request_put_1__VAL_4, - MUX_fpu$server_core_request_put_1__VAL_5, - MUX_fpu$server_core_request_put_1__VAL_6, - MUX_fpu$server_core_request_put_1__VAL_7, - MUX_fpu$server_core_request_put_1__VAL_8, - MUX_fpu$server_core_request_put_1__VAL_9; - wire [69 : 0] MUX_resultR$write_1__VAL_10, - MUX_resultR$write_1__VAL_11, - MUX_resultR$write_1__VAL_12, - MUX_resultR$write_1__VAL_13, - MUX_resultR$write_1__VAL_14, - MUX_resultR$write_1__VAL_15, - MUX_resultR$write_1__VAL_16, - MUX_resultR$write_1__VAL_17, - MUX_resultR$write_1__VAL_18, - MUX_resultR$write_1__VAL_19, - MUX_resultR$write_1__VAL_20, - MUX_resultR$write_1__VAL_21, - MUX_resultR$write_1__VAL_22, - MUX_resultR$write_1__VAL_23, - MUX_resultR$write_1__VAL_24, - MUX_resultR$write_1__VAL_25, - MUX_resultR$write_1__VAL_26, - MUX_resultR$write_1__VAL_27, - MUX_resultR$write_1__VAL_28, - MUX_resultR$write_1__VAL_29, - MUX_resultR$write_1__VAL_3, - MUX_resultR$write_1__VAL_30, - MUX_resultR$write_1__VAL_31, - MUX_resultR$write_1__VAL_32, - MUX_resultR$write_1__VAL_33, - MUX_resultR$write_1__VAL_34, - MUX_resultR$write_1__VAL_35, - MUX_resultR$write_1__VAL_4, - MUX_resultR$write_1__VAL_5, - MUX_resultR$write_1__VAL_7, - MUX_resultR$write_1__VAL_8, - MUX_resultR$write_1__VAL_9; - wire [68 : 0] MUX_dw_result$wset_1__VAL_1; - wire MUX_dw_result$wset_1__SEL_1; - - // remaining internal signals - reg [51 : 0] CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q114, - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q115, - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q116, - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q117, - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q118, - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q119, - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q56, - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q57, - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q45, - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q46, - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q54, - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q55, - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q41, - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q42, - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617; - reg [22 : 0] CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q18, - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q19, - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q78, - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q79, - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q29, - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q30, - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q27, - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q28, - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q16, - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q17, - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q84, - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q85, - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q82, - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q83, - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q80, - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q81, - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754; - reg [10 : 0] CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q102, - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q103, - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q104, - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q105, - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q106, - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q107, - CASE_guard5160_0b0_0_0b1_0_0b10_out_exp5779_0b_ETC__q49, - CASE_guard5160_0b0_0_0b1_theResult___exp5776_0_ETC__q50, - CASE_guard5519_0b0_0_0b1_0_0b10_out_exp6138_0b_ETC__q44, - CASE_guard5519_0b0_0_0b1_theResult___exp6135_0_ETC__q43, - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_theR_ETC__q52, - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_x590_ETC__q53, - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_theR_ETC__q39, - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_x626_ETC__q40, - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5160_ETC__q51, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538; - reg [7 : 0] CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_theResu_ETC__q14, - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_x064_BI_ETC__q15, - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q70, - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q71, - CASE_guard3641_0b0_0_0b1_0_0b10_out_exp4057_0b_ETC__q22, - CASE_guard3641_0b0_0_0b1_theResult___exp4054_0_ETC__q23, - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_theRe_ETC__q25, - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_x4182_ETC__q26, - CASE_guard519_0b0_0_0b1_0_0b10_out_exp938_0b11_ETC__q13, - CASE_guard519_0b0_0_0b1_theResult___exp935_0b1_ETC__q12, - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q76, - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q77, - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q74, - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q75, - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q72, - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q73, - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard3641_ETC__q24, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716; - reg [2 : 0] IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50; - reg CASE_guard049_0b0_requestR_BIT_159_0b1_request_ETC__q10, - CASE_guard10776_0b0_requestR_BITS_191_TO_160_E_ETC__q108, - CASE_guard1080_0b0_requestR_BIT_191_0b1_reques_ETC__q86, - CASE_guard20084_0b0_requestR_BITS_191_TO_160_E_ETC__q110, - CASE_guard29151_0b0_requestR_BITS_191_TO_160_E_ETC__q112, - CASE_guard519_0b0_requestR_BIT_159_0b1_request_ETC__q8, - CASE_guard5519_0b0_requestR_BIT_159_0b1_reques_ETC__q35, - CASE_guard6249_0b0_requestR_BIT_159_0b1_reques_ETC__q37, - CASE_guard7668_0b0_requestR_BIT_191_0b1_reques_ETC__q92, - CASE_guard8804_0b0_requestR_BIT_191_0b1_reques_ETC__q90, - CASE_guard9815_0b0_requestR_BIT_191_0b1_reques_ETC__q88, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93; - wire [85 : 0] IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631, - b__h47244, - x__h47920, - x__h48943; - wire [64 : 0] _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78; - wire [63 : 0] IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1051, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1066, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1050, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1052, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1065, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1067, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1131, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1132, - IF_requestR_3_BITS_126_TO_116_754_EQ_2047_755__ETC___d3802, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3815, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3881, - res___1__h154853, - res___1__h155291, - res___1__h155301, - res___1__h155320, - res___1__h25997, - res___1__h26233, - res___1__h26243, - res___1__h26262, - res__h138561, - res__h142948, - res__h147441, - res__h150090, - res__h152730, - res__h154552, - res__h155336, - res__h155490, - res__h17988, - res__h18225, - res__h23375, - res__h24803, - res__h25817, - res__h26278, - res__h96811, - x__h139530, - x__h144023, - x__h148412, - x__h15077, - x__h151052, - x__h152874, - x__h154833, - x__h155457, - x__h16615, - x__h17309, - x__h19888, - x__h22358, - x__h22423, - x__h22505, - x__h2333, - x__h23933, - x__h2414, - x__h2492, - x__h24947, - x__h2584, - x__h25977, - x__h27284, - x__h27350, - x__h27418, - x__h27493, - x__h37386, - x__h46998, - x__h48519, - x__h49209, - x__h8990, - x__h97859; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q60, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q65, - IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q100, - IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q94, - IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q62, - IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q68, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845, - _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d3162, - _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_609__ETC___d2329, - _theResult____h120074, - _theResult____h61070, - _theResult____h78794, - _theResult___snd__h118688, - _theResult___snd__h118690, - _theResult___snd__h118697, - _theResult___snd__h118703, - _theResult___snd__h118726, - _theResult___snd__h128321, - _theResult___snd__h128332, - _theResult___snd__h128334, - _theResult___snd__h128344, - _theResult___snd__h128350, - _theResult___snd__h128373, - _theResult___snd__h137087, - _theResult___snd__h137101, - _theResult___snd__h137107, - _theResult___snd__h137125, - _theResult___snd__h69188, - _theResult___snd__h69199, - _theResult___snd__h69201, - _theResult___snd__h69211, - _theResult___snd__h69217, - _theResult___snd__h69240, - _theResult___snd__h77814, - _theResult___snd__h77816, - _theResult___snd__h77823, - _theResult___snd__h77829, - _theResult___snd__h77852, - _theResult___snd__h87041, - _theResult___snd__h87052, - _theResult___snd__h87054, - _theResult___snd__h87064, - _theResult___snd__h87070, - _theResult___snd__h87093, - _theResult___snd__h95691, - _theResult___snd__h95705, - _theResult___snd__h95711, - _theResult___snd__h95729, - b__h15323, - result__h120687, - result__h79407, - sfd__h53440, - sfdin__h128304, - sfdin__h69171, - sfdin__h87024, - x__h120782, - x__h15999, - x__h17039, - x__h79502; - wire [54 : 0] sfd___3__h35509, sfd___3__h45150, sfd__h27508, sfd__h37398; - wire [53 : 0] sfd__h118755, - sfd__h128402, - sfd__h137160, - sfd__h35536, - sfd__h36279, - sfd__h45177, - sfd__h45919, - value__h47246; - wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3592, - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3594, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3565, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3567, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3611, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3613, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1371, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1373, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1389, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1391, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3624, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1399, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1581, - _theResult___fst_sfd__h103665, - _theResult___fst_sfd__h119491, - _theResult___fst_sfd__h119494, - _theResult___fst_sfd__h129138, - _theResult___fst_sfd__h129141, - _theResult___fst_sfd__h137920, - _theResult___fst_sfd__h137923, - _theResult___fst_sfd__h137932, - _theResult___fst_sfd__h137938, - _theResult___fst_sfd__h36233, - _theResult___fst_sfd__h36989, - _theResult___fst_sfd__h36992, - _theResult___fst_sfd__h45873, - _theResult___fst_sfd__h46628, - _theResult___fst_sfd__h46631, - _theResult___fst_sfd__h49736, - _theResult___sfd__h119393, - _theResult___sfd__h129040, - _theResult___sfd__h137822, - _theResult___sfd__h36136, - _theResult___sfd__h36892, - _theResult___sfd__h45777, - _theResult___sfd__h46532, - _theResult___snd_fst_sfd__h119497, - _theResult___snd_fst_sfd__h137926, - _theResult___snd_fst_sfd__h36995, - _theResult___snd_fst_sfd__h46634, - _theResult___snd_fst_sfd__h99811, - out___1_sfd__h97925, - out_sfd__h119396, - out_sfd__h129043, - out_sfd__h137825, - out_sfd__h36139, - out_sfd__h36895, - out_sfd__h45780, - out_sfd__h46535, - value__h49279; - wire [32 : 0] _theResult_____2__h15258, - _theResult_____2__h47179, - out1___1__h15750, - out1___1__h47671; - wire [31 : 0] IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1047, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1060, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1062, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1048, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1063, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d904, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d963, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d900, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d902, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d961, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1686, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1688, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1747, - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1045, - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1059, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d1749, - IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d1690, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d833, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d965, - IF_requestR_3_BIT_191_202_THEN_2147483648_ELSE_ETC___d1619, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - requestR_BITS_159_TO_128__q1, - sfd___3__h13631, - sfd___3__h7509, - sfd__h2605, - x__h15080, - x__h16618, - x__h2340, - x__h2421, - x__h2499, - x__h2590, - x__h47001, - x__h48522, - x__h96817; - wire [30 : 0] IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29; - wire [24 : 0] sfd__h13658, - sfd__h14197, - sfd__h69269, - sfd__h7536, - sfd__h77881, - sfd__h8079, - sfd__h87122, - sfd__h95764, - value__h15325; - wire [23 : 0] NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624, - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1656, - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657, - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720; - wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2731, - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2733, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2777, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2779, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2750, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2752, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2796, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2798, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d416, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d418, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d434, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d436, - IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d2809, - _theResult___fst_sfd__h14151, - _theResult___fst_sfd__h14703, - _theResult___fst_sfd__h14706, - _theResult___fst_sfd__h61053, - _theResult___fst_sfd__h69802, - _theResult___fst_sfd__h69805, - _theResult___fst_sfd__h78414, - _theResult___fst_sfd__h78417, - _theResult___fst_sfd__h8033, - _theResult___fst_sfd__h8586, - _theResult___fst_sfd__h8589, - _theResult___fst_sfd__h87655, - _theResult___fst_sfd__h87658, - _theResult___fst_sfd__h96321, - _theResult___fst_sfd__h96324, - _theResult___fst_sfd__h96333, - _theResult___fst_sfd__h96339, - _theResult___fst_sfd__h98183, - _theResult___sfd__h14055, - _theResult___sfd__h14607, - _theResult___sfd__h69704, - _theResult___sfd__h78316, - _theResult___sfd__h7936, - _theResult___sfd__h8489, - _theResult___sfd__h87557, - _theResult___sfd__h96223, - _theResult___snd_fst_sfd__h14709, - _theResult___snd_fst_sfd__h53394, - _theResult___snd_fst_sfd__h78420, - _theResult___snd_fst_sfd__h8592, - _theResult___snd_fst_sfd__h96327, - out_sfd__h14058, - out_sfd__h14610, - out_sfd__h69707, - out_sfd__h78319, - out_sfd__h7939, - out_sfd__h8492, - out_sfd__h87560, - out_sfd__h96226, - sV1_sfd__h1205, - sV2_sfd__h1308, - value__h97928; - wire [19 : 0] NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d870, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934; - wire [11 : 0] IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3478, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96, - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322, - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1851, - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d3158, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3012, - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_609_ETC___d2325, - x__h120815, - x__h36264, - x__h45904, - x__h79535; - wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3463, - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3465, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3138, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3140, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3532, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3534, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1322, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1348, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1350, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q99, - _theResult___exp__h119392, - _theResult___exp__h129039, - _theResult___exp__h137821, - _theResult___exp__h36135, - _theResult___exp__h36891, - _theResult___exp__h45776, - _theResult___exp__h46531, - _theResult___fst_exp__h103664, - _theResult___fst_exp__h118728, - _theResult___fst_exp__h118734, - _theResult___fst_exp__h118737, - _theResult___fst_exp__h119490, - _theResult___fst_exp__h119493, - _theResult___fst_exp__h128310, - _theResult___fst_exp__h128375, - _theResult___fst_exp__h128381, - _theResult___fst_exp__h128384, - _theResult___fst_exp__h129137, - _theResult___fst_exp__h129140, - _theResult___fst_exp__h137093, - _theResult___fst_exp__h137132, - _theResult___fst_exp__h137138, - _theResult___fst_exp__h137141, - _theResult___fst_exp__h137919, - _theResult___fst_exp__h137922, - _theResult___fst_exp__h137931, - _theResult___fst_exp__h137934, - _theResult___fst_exp__h36232, - _theResult___fst_exp__h36988, - _theResult___fst_exp__h36991, - _theResult___fst_exp__h45872, - _theResult___fst_exp__h46627, - _theResult___fst_exp__h46630, - _theResult___snd_fst_exp__h119496, - _theResult___snd_fst_exp__h137925, - _theResult___snd_fst_exp__h36994, - _theResult___snd_fst_exp__h36997, - _theResult___snd_fst_exp__h37000, - _theResult___snd_fst_exp__h46633, - _theResult___snd_fst_exp__h46636, - _theResult___snd_fst_exp__h46639, - din_inc___2_exp__h137957, - din_inc___2_exp__h137987, - din_inc___2_exp__h138011, - din_inc___2_exp__h37034, - din_inc___2_exp__h46669, - out_exp__h119395, - out_exp__h129042, - out_exp__h137824, - out_exp__h36138, - out_exp__h36894, - out_exp__h45779, - out_exp__h46534, - requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622, - x__h97869; - wire [8 : 0] IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2643, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635, - x__h14182, - x__h8064; - wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2144, - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2146, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2628, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2630, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2301, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2303, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2697, - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2699, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d367, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d393, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d395, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d405, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d722, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836, - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q67, - _theResult___exp__h14054, - _theResult___exp__h14606, - _theResult___exp__h69703, - _theResult___exp__h78315, - _theResult___exp__h7935, - _theResult___exp__h8488, - _theResult___exp__h87556, - _theResult___exp__h96222, - _theResult___fst_exp__h14150, - _theResult___fst_exp__h14702, - _theResult___fst_exp__h14705, - _theResult___fst_exp__h61052, - _theResult___fst_exp__h69177, - _theResult___fst_exp__h69242, - _theResult___fst_exp__h69248, - _theResult___fst_exp__h69251, - _theResult___fst_exp__h69801, - _theResult___fst_exp__h69804, - _theResult___fst_exp__h77854, - _theResult___fst_exp__h77860, - _theResult___fst_exp__h77863, - _theResult___fst_exp__h78413, - _theResult___fst_exp__h78416, - _theResult___fst_exp__h8032, - _theResult___fst_exp__h8585, - _theResult___fst_exp__h8588, - _theResult___fst_exp__h87030, - _theResult___fst_exp__h87095, - _theResult___fst_exp__h87101, - _theResult___fst_exp__h87104, - _theResult___fst_exp__h87654, - _theResult___fst_exp__h87657, - _theResult___fst_exp__h95697, - _theResult___fst_exp__h95736, - _theResult___fst_exp__h95742, - _theResult___fst_exp__h95745, - _theResult___fst_exp__h96320, - _theResult___fst_exp__h96323, - _theResult___fst_exp__h96332, - _theResult___fst_exp__h96335, - _theResult___snd_fst_exp__h14708, - _theResult___snd_fst_exp__h14711, - _theResult___snd_fst_exp__h14714, - _theResult___snd_fst_exp__h78419, - _theResult___snd_fst_exp__h8591, - _theResult___snd_fst_exp__h8594, - _theResult___snd_fst_exp__h8597, - _theResult___snd_fst_exp__h96326, - din_inc___2_exp__h14744, - din_inc___2_exp__h8631, - din_inc___2_exp__h96354, - din_inc___2_exp__h96378, - din_inc___2_exp__h96408, - din_inc___2_exp__h96432, - out_exp__h14057, - out_exp__h14609, - out_exp__h69706, - out_exp__h78318, - out_exp__h7938, - out_exp__h8491, - out_exp__h87559, - out_exp__h96225, - sV1_exp__h1204, - sV2_exp__h1307, - x__h49219; - wire [5 : 0] IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d2085, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d3404, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d2569, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1242, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d275, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1456, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d632; - wire [4 : 0] _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881, - x__h138663, - x__h143080, - x__h14848, - x__h152749, - x__h16413, - x__h17117, - x__h19349, - x__h24822, - x__h37156, - x__h46769, - x__h48317, - x__h49021, - x__h8757, - x__h96932; - wire [1 : 0] IF_sfd___33631_BIT_7_THEN_2_ELSE_0__q21, - IF_sfd___33631_BIT_8_THEN_2_ELSE_0__q20, - IF_sfd___3509_BIT_7_THEN_2_ELSE_0__q7, - IF_sfd___3509_BIT_8_THEN_2_ELSE_0__q6, - IF_sfd___35150_BIT_1_THEN_2_ELSE_0__q48, - IF_sfd___35150_BIT_2_THEN_2_ELSE_0__q47, - IF_sfd___35509_BIT_1_THEN_2_ELSE_0__q34, - IF_sfd___35509_BIT_2_THEN_2_ELSE_0__q33, - IF_sfdin28304_BIT_4_THEN_2_ELSE_0__q98, - IF_sfdin7024_BIT_33_THEN_2_ELSE_0__q66, - IF_sfdin9171_BIT_33_THEN_2_ELSE_0__q61, - IF_theResult___snd18688_BIT_4_THEN_2_ELSE_0__q95, - IF_theResult___snd37087_BIT_4_THEN_2_ELSE_0__q101, - IF_theResult___snd5691_BIT_33_THEN_2_ELSE_0__q69, - IF_theResult___snd7814_BIT_33_THEN_2_ELSE_0__q63, - IF_x5999_BIT_24_THEN_2_ELSE_0__q31, - IF_x7039_BIT_24_THEN_2_ELSE_0__q32, - IF_x7920_BIT_53_THEN_2_ELSE_0__q58, - IF_x8943_BIT_53_THEN_2_ELSE_0__q59, - guard__h110776, - guard__h120084, - guard__h129151, - guard__h13641, - guard__h14167, - guard__h15256, - guard__h15810, - guard__h16818, - guard__h35519, - guard__h36249, - guard__h45160, - guard__h45889, - guard__h47177, - guard__h47731, - guard__h48722, - guard__h61080, - guard__h69815, - guard__h7519, - guard__h78804, - guard__h8049, - guard__h87668; - wire IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_7_ETC___d2831, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1301, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1416, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d345, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d495, - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1598, - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d808, - IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d3648, - IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3656, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3660, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3695, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3698, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3705, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3719, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3731, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3743, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d926, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1712, - IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d1302, - IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d3640, - IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1040, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3658, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3717, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3729, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3741, - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2849, - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2927, - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2940, - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2953, - IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d1020, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2851, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2902, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2913, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2929, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2942, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2955, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1006, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1016, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1029, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1031, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1034, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1036, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1054, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1087, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1098, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1102, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d832, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d973, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d984, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1648, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1680, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1741, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d862, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d894, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d955, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d486, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d489, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d498, - IF_requestR_3_BIT_191_202_THEN_NOT_requestR_3__ETC___d3795, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d873, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d936, - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1659, - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1722, - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2921, - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2949, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1043, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1044, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1097, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1103, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1119, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d915, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d978, - NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d283, - NOT_requestR_3_BITS_159_TO_128_44_EQ_0_45_46_A_ETC___d800, - NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1701, - NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1764, - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3799, - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3860, - NOT_requestR_3_BITS_190_TO_180_609_ULT_request_ETC___d3839, - NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1101, - NOT_requestR_3_BIT_158_07_08_AND_NOT_requestR__ETC___d598, - NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157, - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323, - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2087, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3406, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2571, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3086, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3479, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2249, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2644, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2884, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2909, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2936, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014, - guard__h120682, - guard__h79402, - requestR_3_BITS_126_TO_116_754_EQ_0_768_AND_re_ETC___d3775, - requestR_3_BITS_179_TO_128_611_ULE_requestR_3__ETC___d3787, - requestR_3_BITS_179_TO_128_611_ULT_requestR_3__ETC___d3792, - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3771, - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3843, - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1759, - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1770, - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3763, - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3808, - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3828, - requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786, - requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3784, - requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3838, - requestR_3_BITS_190_TO_180_609_ULT_requestR_3__ETC___d3791, - requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d1042, - requestR_3_BIT_158_07_OR_requestR_3_BIT_157_09_ETC___d789, - requestR_3_BIT_159_6_OR_requestR_3_BIT_158_07__ETC___d811; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = resetReqsF$FULL_N ; - assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas && dw_valid$wget ; - - // value method word_fst - assign word_fst = dw_result$wget[68:5] ; - - // value method word_snd - assign word_snd = dw_result$wget[4:0] ; - - // submodule fpu - mkFPU fpu(.CLK(CLK), - .RST_N(RST_N), - .server_core_request_put(fpu$server_core_request_put), - .EN_server_core_request_put(fpu$EN_server_core_request_put), - .EN_server_core_response_get(fpu$EN_server_core_response_get), - .EN_server_reset_request_put(fpu$EN_server_reset_request_put), - .EN_server_reset_response_get(fpu$EN_server_reset_response_get), - .RDY_server_core_request_put(fpu$RDY_server_core_request_put), - .server_core_response_get(fpu$server_core_response_get), - .RDY_server_core_response_get(fpu$RDY_server_core_response_get), - .RDY_server_reset_request_put(fpu$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fpu$RDY_server_reset_response_get)); - - // submodule frmFpuF - FIFO2 #(.width(32'd1), .guarded(32'd1)) frmFpuF(.RST(RST_N), - .CLK(CLK), - .D_IN(frmFpuF$D_IN), - .ENQ(frmFpuF$ENQ), - .DEQ(frmFpuF$DEQ), - .CLR(frmFpuF$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N()); - - // submodule resetReqsF - FIFO20 #(.guarded(32'd1)) resetReqsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetReqsF$ENQ), - .DEQ(resetReqsF$DEQ), - .CLR(resetReqsF$CLR), - .FULL_N(resetReqsF$FULL_N), - .EMPTY_N(resetReqsF$EMPTY_N)); - - // submodule resetRspsF - FIFO20 #(.guarded(32'd1)) resetRspsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetRspsF$ENQ), - .DEQ(resetRspsF$DEQ), - .CLR(resetRspsF$CLR), - .FULL_N(resetRspsF$FULL_N), - .EMPTY_N(resetRspsF$EMPTY_N)); - - // rule RL_rl_reset_end - assign CAN_FIRE_RL_rl_reset_end = - fpu$RDY_server_reset_response_get && resetRspsF$FULL_N && - stateR == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_end = CAN_FIRE_RL_rl_reset_end ; - - // rule RL_doFADD_S - assign CAN_FIRE_RL_doFADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0 ; - assign WILL_FIRE_RL_doFADD_S = CAN_FIRE_RL_doFADD_S ; - - // rule RL_doFSUB_S - assign CAN_FIRE_RL_doFSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h04 ; - assign WILL_FIRE_RL_doFSUB_S = CAN_FIRE_RL_doFSUB_S ; - - // rule RL_doFMUL_S - assign CAN_FIRE_RL_doFMUL_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h08 ; - assign WILL_FIRE_RL_doFMUL_S = CAN_FIRE_RL_doFMUL_S ; - - // rule RL_doFMADD_S - assign CAN_FIRE_RL_doFMADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000011 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFMADD_S = CAN_FIRE_RL_doFMADD_S ; - - // rule RL_doFMSUB_S - assign CAN_FIRE_RL_doFMSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000111 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFMSUB_S = CAN_FIRE_RL_doFMSUB_S ; - - // rule RL_doFNMADD_S - assign CAN_FIRE_RL_doFNMADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001111 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFNMADD_S = CAN_FIRE_RL_doFNMADD_S ; - - // rule RL_doFNMSUB_S - assign CAN_FIRE_RL_doFNMSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001011 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFNMSUB_S = CAN_FIRE_RL_doFNMSUB_S ; - - // rule RL_doFDIV_S - assign CAN_FIRE_RL_doFDIV_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0C ; - assign WILL_FIRE_RL_doFDIV_S = CAN_FIRE_RL_doFDIV_S ; - - // rule RL_doFSQRT_S - assign CAN_FIRE_RL_doFSQRT_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h2C ; - assign WILL_FIRE_RL_doFSQRT_S = CAN_FIRE_RL_doFSQRT_S ; - - // rule RL_doFSGNJ_S - assign CAN_FIRE_RL_doFSGNJ_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFSGNJ_S = CAN_FIRE_RL_doFSGNJ_S ; - - // rule RL_doFSGNJN_S - assign CAN_FIRE_RL_doFSGNJN_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFSGNJN_S = CAN_FIRE_RL_doFSGNJN_S ; - - // rule RL_doFSGNJX_S - assign CAN_FIRE_RL_doFSGNJX_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFSGNJX_S = CAN_FIRE_RL_doFSGNJX_S ; - - // rule RL_doFCVT_S_W - assign CAN_FIRE_RL_doFCVT_S_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_S_W = CAN_FIRE_RL_doFCVT_S_W ; - - // rule RL_doFCVT_S_WU - assign CAN_FIRE_RL_doFCVT_S_WU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_S_WU = CAN_FIRE_RL_doFCVT_S_WU ; - - // rule RL_doFCVT_W_S - assign CAN_FIRE_RL_doFCVT_W_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_W_S = CAN_FIRE_RL_doFCVT_W_S ; - - // rule RL_doFCVT_WU_S - assign CAN_FIRE_RL_doFCVT_WU_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_WU_S = CAN_FIRE_RL_doFCVT_WU_S ; - - // rule RL_doFMIN_S - assign CAN_FIRE_RL_doFMIN_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h14 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMIN_S = CAN_FIRE_RL_doFMIN_S ; - - // rule RL_doFMAX_S - assign CAN_FIRE_RL_doFMAX_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h14 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFMAX_S = CAN_FIRE_RL_doFMAX_S ; - - // rule RL_doFMV_W_X - assign CAN_FIRE_RL_doFMV_W_X = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h78 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_W_X = CAN_FIRE_RL_doFMV_W_X ; - - // rule RL_doFMV_X_W - assign CAN_FIRE_RL_doFMV_X_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h70 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_X_W = CAN_FIRE_RL_doFMV_X_W ; - - // rule RL_doFEQ_S - assign CAN_FIRE_RL_doFEQ_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFEQ_S = CAN_FIRE_RL_doFEQ_S ; - - // rule RL_doFLT_S - assign CAN_FIRE_RL_doFLT_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFLT_S = CAN_FIRE_RL_doFLT_S ; - - // rule RL_doFLE_S - assign CAN_FIRE_RL_doFLE_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFLE_S = CAN_FIRE_RL_doFLE_S ; - - // rule RL_doFCLASS_S - assign CAN_FIRE_RL_doFCLASS_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h70 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFCLASS_S = CAN_FIRE_RL_doFCLASS_S ; - - // rule RL_doFADD_D - assign CAN_FIRE_RL_doFADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h01 ; - assign WILL_FIRE_RL_doFADD_D = CAN_FIRE_RL_doFADD_D ; - - // rule RL_doFSUB_D - assign CAN_FIRE_RL_doFSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h05 ; - assign WILL_FIRE_RL_doFSUB_D = CAN_FIRE_RL_doFSUB_D ; - - // rule RL_doFMUL_D - assign CAN_FIRE_RL_doFMUL_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h09 ; - assign WILL_FIRE_RL_doFMUL_D = CAN_FIRE_RL_doFMUL_D ; - - // rule RL_doFMADD_D - assign CAN_FIRE_RL_doFMADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000011 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFMADD_D = CAN_FIRE_RL_doFMADD_D ; - - // rule RL_doFMSUB_D - assign CAN_FIRE_RL_doFMSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000111 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFMSUB_D = CAN_FIRE_RL_doFMSUB_D ; - - // rule RL_doFNMADD_D - assign CAN_FIRE_RL_doFNMADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001111 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFNMADD_D = CAN_FIRE_RL_doFNMADD_D ; - - // rule RL_doFNMSUB_D - assign CAN_FIRE_RL_doFNMSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001011 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFNMSUB_D = CAN_FIRE_RL_doFNMSUB_D ; - - // rule RL_doFDIV_D - assign CAN_FIRE_RL_doFDIV_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0D ; - assign WILL_FIRE_RL_doFDIV_D = CAN_FIRE_RL_doFDIV_D ; - - // rule RL_doFSQRT_D - assign CAN_FIRE_RL_doFSQRT_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h2D ; - assign WILL_FIRE_RL_doFSQRT_D = CAN_FIRE_RL_doFSQRT_D ; - - // rule RL_doFSGNJ_D - assign CAN_FIRE_RL_doFSGNJ_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFSGNJ_D = CAN_FIRE_RL_doFSGNJ_D ; - - // rule RL_doFSGNJN_D - assign CAN_FIRE_RL_doFSGNJN_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFSGNJN_D = CAN_FIRE_RL_doFSGNJN_D ; - - // rule RL_doFSGNJX_D - assign CAN_FIRE_RL_doFSGNJX_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFSGNJX_D = CAN_FIRE_RL_doFSGNJX_D ; - - // rule RL_doFCVT_D_W - assign CAN_FIRE_RL_doFCVT_D_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_D_W = CAN_FIRE_RL_doFCVT_D_W ; - - // rule RL_doFCVT_D_WU - assign CAN_FIRE_RL_doFCVT_D_WU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_D_WU = CAN_FIRE_RL_doFCVT_D_WU ; - - // rule RL_doFCVT_W_D - assign CAN_FIRE_RL_doFCVT_W_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_W_D = CAN_FIRE_RL_doFCVT_W_D ; - - // rule RL_doFCVT_WU_D - assign CAN_FIRE_RL_doFCVT_WU_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_WU_D = CAN_FIRE_RL_doFCVT_WU_D ; - - // rule RL_doFCVT_S_D - assign CAN_FIRE_RL_doFCVT_S_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h20 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_S_D = CAN_FIRE_RL_doFCVT_S_D ; - - // rule RL_doFCVT_D_S - assign CAN_FIRE_RL_doFCVT_D_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h21 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_D_S = CAN_FIRE_RL_doFCVT_D_S ; - - // rule RL_doFMIN_D - assign CAN_FIRE_RL_doFMIN_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h15 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMIN_D = CAN_FIRE_RL_doFMIN_D ; - - // rule RL_doFMAX_D - assign CAN_FIRE_RL_doFMAX_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h15 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFMAX_D = CAN_FIRE_RL_doFMAX_D ; - - // rule RL_doFEQ_D - assign CAN_FIRE_RL_doFEQ_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFEQ_D = CAN_FIRE_RL_doFEQ_D ; - - // rule RL_doFLT_D - assign CAN_FIRE_RL_doFLT_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFLT_D = CAN_FIRE_RL_doFLT_D ; - - // rule RL_doFLE_D - assign CAN_FIRE_RL_doFLE_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFLE_D = CAN_FIRE_RL_doFLE_D ; - - // rule RL_doFMV_D_X - assign CAN_FIRE_RL_doFMV_D_X = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h79 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_D_X = CAN_FIRE_RL_doFMV_D_X ; - - // rule RL_doFMV_X_D - assign CAN_FIRE_RL_doFMV_X_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h71 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_X_D = CAN_FIRE_RL_doFMV_X_D ; - - // rule RL_doFCLASS_D - assign CAN_FIRE_RL_doFCLASS_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h71 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFCLASS_D = CAN_FIRE_RL_doFCLASS_D ; - - // rule RL_rl_get_fpu_result - assign CAN_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ; - assign WILL_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ; - - // rule RL_rl_drive_fpu_result - assign CAN_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ; - assign WILL_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ; - - // rule RL_rl_reset_begin - assign CAN_FIRE_RL_rl_reset_begin = - fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_begin = CAN_FIRE_RL_rl_reset_begin ; - - // inputs to muxes for submodule ports - assign MUX_dw_result$wset_1__SEL_1 = - fpu$RDY_server_core_response_get && stateR == 2'd2 ; - assign MUX_dw_result$wset_1__VAL_1 = - { x__h155457, fpu$server_core_response_get[4:0] } ; - assign MUX_fpu$server_core_request_put_1__VAL_1 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd0 } ; - assign MUX_fpu$server_core_request_put_1__VAL_2 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd1 } ; - assign MUX_fpu$server_core_request_put_1__VAL_3 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd2 } ; - assign MUX_fpu$server_core_request_put_1__VAL_4 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd5 } ; - assign MUX_fpu$server_core_request_put_1__VAL_5 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd6 } ; - assign MUX_fpu$server_core_request_put_1__VAL_6 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd7 } ; - assign MUX_fpu$server_core_request_put_1__VAL_7 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd8 } ; - assign MUX_fpu$server_core_request_put_1__VAL_8 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd3 } ; - assign MUX_fpu$server_core_request_put_1__VAL_9 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 130'h15555555555555554AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd4 } ; - assign MUX_fpu$server_core_request_put_1__VAL_10 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd0 } ; - assign MUX_fpu$server_core_request_put_1__VAL_11 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd1 } ; - assign MUX_fpu$server_core_request_put_1__VAL_12 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd2 } ; - assign MUX_fpu$server_core_request_put_1__VAL_13 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd5 } ; - assign MUX_fpu$server_core_request_put_1__VAL_14 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd6 } ; - assign MUX_fpu$server_core_request_put_1__VAL_15 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd7 } ; - assign MUX_fpu$server_core_request_put_1__VAL_16 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd8 } ; - assign MUX_fpu$server_core_request_put_1__VAL_17 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd3 } ; - assign MUX_fpu$server_core_request_put_1__VAL_18 = - { 1'd0, - requestR[191:128], - 130'h15555555555555554AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd4 } ; - assign MUX_requestR$write_1__VAL_2 = - { 1'd1, - req_opcode, - req_f7, - req_rs2, - req_rm, - req_v1, - req_v2, - req_v3 } ; - assign MUX_resultR$write_1__VAL_3 = - { 1'd1, x__h155457, fpu$server_core_response_get[4:0] } ; - assign MUX_resultR$write_1__VAL_4 = { 1'd1, x__h154833, 5'd0 } ; - assign MUX_resultR$write_1__VAL_5 = { 1'd1, requestR[191:128], 5'd0 } ; - assign MUX_resultR$write_1__VAL_7 = { 1'd1, x__h152874, x__h152749 } ; - assign MUX_resultR$write_1__VAL_8 = { 1'd1, x__h151052, x__h152749 } ; - assign MUX_resultR$write_1__VAL_9 = { 1'd1, x__h148412, x__h143080 } ; - assign MUX_resultR$write_1__VAL_10 = { 1'd1, x__h144023, x__h143080 } ; - assign MUX_resultR$write_1__VAL_11 = { 1'd1, x__h139530, x__h143080 } ; - assign MUX_resultR$write_1__VAL_12 = { 1'd1, x__h97859, x__h138663 } ; - assign MUX_resultR$write_1__VAL_13 = { 1'd1, x__h49209, x__h96932 } ; - assign MUX_resultR$write_1__VAL_14 = { 1'd1, x__h48519, x__h49021 } ; - assign MUX_resultR$write_1__VAL_15 = { 1'd1, x__h46998, x__h48317 } ; - assign MUX_resultR$write_1__VAL_16 = { 1'd1, x__h37386, x__h46769 } ; - assign MUX_resultR$write_1__VAL_17 = { 1'd1, x__h27493, x__h37156 } ; - assign MUX_resultR$write_1__VAL_18 = { 1'd1, x__h27418, 5'd0 } ; - assign MUX_resultR$write_1__VAL_19 = { 1'd1, x__h27350, 5'd0 } ; - assign MUX_resultR$write_1__VAL_20 = { 1'd1, x__h27284, 5'd0 } ; - assign MUX_resultR$write_1__VAL_21 = { 1'd1, x__h25977, 5'd0 } ; - assign MUX_resultR$write_1__VAL_22 = { 1'd1, x__h24947, x__h24822 } ; - assign MUX_resultR$write_1__VAL_23 = { 1'd1, x__h23933, x__h24822 } ; - assign MUX_resultR$write_1__VAL_24 = { 1'd1, x__h22505, x__h19349 } ; - assign MUX_resultR$write_1__VAL_25 = { 1'd1, x__h22423, 5'd0 } ; - assign MUX_resultR$write_1__VAL_26 = { 1'd1, x__h22358, 5'd0 } ; - assign MUX_resultR$write_1__VAL_27 = { 1'd1, x__h19888, x__h19349 } ; - assign MUX_resultR$write_1__VAL_28 = { 1'd1, x__h17309, x__h19349 } ; - assign MUX_resultR$write_1__VAL_29 = { 1'd1, x__h16615, x__h17117 } ; - assign MUX_resultR$write_1__VAL_30 = { 1'd1, x__h15077, x__h16413 } ; - assign MUX_resultR$write_1__VAL_31 = { 1'd1, x__h8990, x__h14848 } ; - assign MUX_resultR$write_1__VAL_32 = { 1'd1, x__h2584, x__h8757 } ; - assign MUX_resultR$write_1__VAL_33 = { 1'd1, x__h2492, 5'd0 } ; - assign MUX_resultR$write_1__VAL_34 = { 1'd1, x__h2414, 5'd0 } ; - assign MUX_resultR$write_1__VAL_35 = { 1'd1, x__h2333, 5'd0 } ; - - // inlined wires - assign dw_valid$wget = !WILL_FIRE_RL_rl_drive_fpu_result || resultR[69] ; - assign dw_valid$whas = - WILL_FIRE_RL_rl_drive_fpu_result || - WILL_FIRE_RL_rl_get_fpu_result ; - assign dw_result$wget = - WILL_FIRE_RL_rl_get_fpu_result ? - MUX_dw_result$wset_1__VAL_1 : - resultR[68:0] ; - - // register requestR - assign requestR$D_IN = - WILL_FIRE_RL_rl_reset_begin ? - 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - MUX_requestR$write_1__VAL_2 ; - assign requestR$EN = WILL_FIRE_RL_rl_reset_begin || EN_req ; - - // register resultR - always@(WILL_FIRE_RL_rl_reset_begin or - EN_req or - WILL_FIRE_RL_rl_get_fpu_result or - MUX_resultR$write_1__VAL_3 or - WILL_FIRE_RL_doFCLASS_D or - MUX_resultR$write_1__VAL_4 or - WILL_FIRE_RL_doFMV_X_D or - MUX_resultR$write_1__VAL_5 or - WILL_FIRE_RL_doFMV_D_X or - WILL_FIRE_RL_doFLE_D or - MUX_resultR$write_1__VAL_7 or - WILL_FIRE_RL_doFLT_D or - MUX_resultR$write_1__VAL_8 or - WILL_FIRE_RL_doFEQ_D or - MUX_resultR$write_1__VAL_9 or - WILL_FIRE_RL_doFMAX_D or - MUX_resultR$write_1__VAL_10 or - WILL_FIRE_RL_doFMIN_D or - MUX_resultR$write_1__VAL_11 or - WILL_FIRE_RL_doFCVT_D_S or - MUX_resultR$write_1__VAL_12 or - WILL_FIRE_RL_doFCVT_S_D or - MUX_resultR$write_1__VAL_13 or - WILL_FIRE_RL_doFCVT_WU_D or - MUX_resultR$write_1__VAL_14 or - WILL_FIRE_RL_doFCVT_W_D or - MUX_resultR$write_1__VAL_15 or - WILL_FIRE_RL_doFCVT_D_WU or - MUX_resultR$write_1__VAL_16 or - WILL_FIRE_RL_doFCVT_D_W or - MUX_resultR$write_1__VAL_17 or - WILL_FIRE_RL_doFSGNJX_D or - MUX_resultR$write_1__VAL_18 or - WILL_FIRE_RL_doFSGNJN_D or - MUX_resultR$write_1__VAL_19 or - WILL_FIRE_RL_doFSGNJ_D or - MUX_resultR$write_1__VAL_20 or - WILL_FIRE_RL_doFCLASS_S or - MUX_resultR$write_1__VAL_21 or - WILL_FIRE_RL_doFLE_S or - MUX_resultR$write_1__VAL_22 or - WILL_FIRE_RL_doFLT_S or - MUX_resultR$write_1__VAL_23 or - WILL_FIRE_RL_doFEQ_S or - MUX_resultR$write_1__VAL_24 or - WILL_FIRE_RL_doFMV_X_W or - MUX_resultR$write_1__VAL_25 or - WILL_FIRE_RL_doFMV_W_X or - MUX_resultR$write_1__VAL_26 or - WILL_FIRE_RL_doFMAX_S or - MUX_resultR$write_1__VAL_27 or - WILL_FIRE_RL_doFMIN_S or - MUX_resultR$write_1__VAL_28 or - WILL_FIRE_RL_doFCVT_WU_S or - MUX_resultR$write_1__VAL_29 or - WILL_FIRE_RL_doFCVT_W_S or - MUX_resultR$write_1__VAL_30 or - WILL_FIRE_RL_doFCVT_S_WU or - MUX_resultR$write_1__VAL_31 or - WILL_FIRE_RL_doFCVT_S_W or - MUX_resultR$write_1__VAL_32 or - WILL_FIRE_RL_doFSGNJX_S or - MUX_resultR$write_1__VAL_33 or - WILL_FIRE_RL_doFSGNJN_S or - MUX_resultR$write_1__VAL_34 or - WILL_FIRE_RL_doFSGNJ_S or MUX_resultR$write_1__VAL_35) - case (1'b1) - WILL_FIRE_RL_rl_reset_begin || EN_req: - resultR$D_IN = 70'h0AAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_get_fpu_result: resultR$D_IN = MUX_resultR$write_1__VAL_3; - WILL_FIRE_RL_doFCLASS_D: resultR$D_IN = MUX_resultR$write_1__VAL_4; - WILL_FIRE_RL_doFMV_X_D: resultR$D_IN = MUX_resultR$write_1__VAL_5; - WILL_FIRE_RL_doFMV_D_X: resultR$D_IN = MUX_resultR$write_1__VAL_5; - WILL_FIRE_RL_doFLE_D: resultR$D_IN = MUX_resultR$write_1__VAL_7; - WILL_FIRE_RL_doFLT_D: resultR$D_IN = MUX_resultR$write_1__VAL_8; - WILL_FIRE_RL_doFEQ_D: resultR$D_IN = MUX_resultR$write_1__VAL_9; - WILL_FIRE_RL_doFMAX_D: resultR$D_IN = MUX_resultR$write_1__VAL_10; - WILL_FIRE_RL_doFMIN_D: resultR$D_IN = MUX_resultR$write_1__VAL_11; - WILL_FIRE_RL_doFCVT_D_S: resultR$D_IN = MUX_resultR$write_1__VAL_12; - WILL_FIRE_RL_doFCVT_S_D: resultR$D_IN = MUX_resultR$write_1__VAL_13; - WILL_FIRE_RL_doFCVT_WU_D: resultR$D_IN = MUX_resultR$write_1__VAL_14; - WILL_FIRE_RL_doFCVT_W_D: resultR$D_IN = MUX_resultR$write_1__VAL_15; - WILL_FIRE_RL_doFCVT_D_WU: resultR$D_IN = MUX_resultR$write_1__VAL_16; - WILL_FIRE_RL_doFCVT_D_W: resultR$D_IN = MUX_resultR$write_1__VAL_17; - WILL_FIRE_RL_doFSGNJX_D: resultR$D_IN = MUX_resultR$write_1__VAL_18; - WILL_FIRE_RL_doFSGNJN_D: resultR$D_IN = MUX_resultR$write_1__VAL_19; - WILL_FIRE_RL_doFSGNJ_D: resultR$D_IN = MUX_resultR$write_1__VAL_20; - WILL_FIRE_RL_doFCLASS_S: resultR$D_IN = MUX_resultR$write_1__VAL_21; - WILL_FIRE_RL_doFLE_S: resultR$D_IN = MUX_resultR$write_1__VAL_22; - WILL_FIRE_RL_doFLT_S: resultR$D_IN = MUX_resultR$write_1__VAL_23; - WILL_FIRE_RL_doFEQ_S: resultR$D_IN = MUX_resultR$write_1__VAL_24; - WILL_FIRE_RL_doFMV_X_W: resultR$D_IN = MUX_resultR$write_1__VAL_25; - WILL_FIRE_RL_doFMV_W_X: resultR$D_IN = MUX_resultR$write_1__VAL_26; - WILL_FIRE_RL_doFMAX_S: resultR$D_IN = MUX_resultR$write_1__VAL_27; - WILL_FIRE_RL_doFMIN_S: resultR$D_IN = MUX_resultR$write_1__VAL_28; - WILL_FIRE_RL_doFCVT_WU_S: resultR$D_IN = MUX_resultR$write_1__VAL_29; - WILL_FIRE_RL_doFCVT_W_S: resultR$D_IN = MUX_resultR$write_1__VAL_30; - WILL_FIRE_RL_doFCVT_S_WU: resultR$D_IN = MUX_resultR$write_1__VAL_31; - WILL_FIRE_RL_doFCVT_S_W: resultR$D_IN = MUX_resultR$write_1__VAL_32; - WILL_FIRE_RL_doFSGNJX_S: resultR$D_IN = MUX_resultR$write_1__VAL_33; - WILL_FIRE_RL_doFSGNJN_S: resultR$D_IN = MUX_resultR$write_1__VAL_34; - WILL_FIRE_RL_doFSGNJ_S: resultR$D_IN = MUX_resultR$write_1__VAL_35; - default: resultR$D_IN = 70'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign resultR$EN = - WILL_FIRE_RL_rl_reset_begin || EN_req || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFSGNJ_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFLE_S || - WILL_FIRE_RL_doFCLASS_S || - WILL_FIRE_RL_doFSGNJ_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_rl_get_fpu_result ; - - // register stateR - always@(WILL_FIRE_RL_rl_reset_begin or - EN_req or - WILL_FIRE_RL_rl_get_fpu_result or - WILL_FIRE_RL_doFCLASS_D or - WILL_FIRE_RL_doFMV_X_D or - WILL_FIRE_RL_doFMV_D_X or - WILL_FIRE_RL_doFLE_D or - WILL_FIRE_RL_doFLT_D or - WILL_FIRE_RL_doFEQ_D or - WILL_FIRE_RL_doFMAX_D or - WILL_FIRE_RL_doFMIN_D or - WILL_FIRE_RL_doFCVT_D_S or - WILL_FIRE_RL_doFCVT_S_D or - WILL_FIRE_RL_doFCVT_WU_D or - WILL_FIRE_RL_doFCVT_W_D or - WILL_FIRE_RL_doFCVT_D_WU or - WILL_FIRE_RL_doFCVT_D_W or - WILL_FIRE_RL_doFSGNJX_D or - WILL_FIRE_RL_doFSGNJN_D or - WILL_FIRE_RL_doFSGNJ_D or - WILL_FIRE_RL_doFSQRT_D or - WILL_FIRE_RL_doFDIV_D or - WILL_FIRE_RL_doFNMSUB_D or - WILL_FIRE_RL_doFNMADD_D or - WILL_FIRE_RL_doFMSUB_D or - WILL_FIRE_RL_doFMADD_D or - WILL_FIRE_RL_doFMUL_D or - WILL_FIRE_RL_doFSUB_D or - WILL_FIRE_RL_doFADD_D or - WILL_FIRE_RL_doFCLASS_S or - WILL_FIRE_RL_doFLE_S or - WILL_FIRE_RL_doFLT_S or - WILL_FIRE_RL_doFEQ_S or - WILL_FIRE_RL_doFMV_X_W or - WILL_FIRE_RL_doFMV_W_X or - WILL_FIRE_RL_doFMAX_S or - WILL_FIRE_RL_doFMIN_S or - WILL_FIRE_RL_doFCVT_WU_S or - WILL_FIRE_RL_doFCVT_W_S or - WILL_FIRE_RL_doFCVT_S_WU or - WILL_FIRE_RL_doFCVT_S_W or - WILL_FIRE_RL_doFSGNJX_S or - WILL_FIRE_RL_doFSGNJN_S or - WILL_FIRE_RL_doFSGNJ_S or - WILL_FIRE_RL_doFSQRT_S or - WILL_FIRE_RL_doFDIV_S or - WILL_FIRE_RL_doFNMSUB_S or - WILL_FIRE_RL_doFNMADD_S or - WILL_FIRE_RL_doFMSUB_S or - WILL_FIRE_RL_doFMADD_S or - WILL_FIRE_RL_doFMUL_S or - WILL_FIRE_RL_doFSUB_S or - WILL_FIRE_RL_doFADD_S or WILL_FIRE_RL_rl_reset_end) - case (1'b1) - WILL_FIRE_RL_rl_reset_begin: stateR$D_IN = 2'd0; - EN_req: stateR$D_IN = 2'd1; - WILL_FIRE_RL_rl_get_fpu_result || WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJ_D: - stateR$D_IN = 2'd3; - WILL_FIRE_RL_doFSQRT_D || WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFADD_D: - stateR$D_IN = 2'd2; - WILL_FIRE_RL_doFCLASS_S || WILL_FIRE_RL_doFLE_S || WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJ_S: - stateR$D_IN = 2'd3; - WILL_FIRE_RL_doFSQRT_S || WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFADD_S: - stateR$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_end: stateR$D_IN = 2'd1; - default: stateR$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign stateR$EN = - WILL_FIRE_RL_rl_reset_begin || WILL_FIRE_RL_rl_reset_end || - EN_req || - WILL_FIRE_RL_doFSQRT_D || - WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFADD_D || - WILL_FIRE_RL_doFSQRT_S || - WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFADD_S || - WILL_FIRE_RL_rl_get_fpu_result || - WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJ_D || - WILL_FIRE_RL_doFCLASS_S || - WILL_FIRE_RL_doFLE_S || - WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJ_S ; - - // submodule fpu - always@(WILL_FIRE_RL_doFADD_S or - MUX_fpu$server_core_request_put_1__VAL_1 or - WILL_FIRE_RL_doFSUB_S or - MUX_fpu$server_core_request_put_1__VAL_2 or - WILL_FIRE_RL_doFMUL_S or - MUX_fpu$server_core_request_put_1__VAL_3 or - WILL_FIRE_RL_doFMADD_S or - MUX_fpu$server_core_request_put_1__VAL_4 or - WILL_FIRE_RL_doFMSUB_S or - MUX_fpu$server_core_request_put_1__VAL_5 or - WILL_FIRE_RL_doFNMADD_S or - MUX_fpu$server_core_request_put_1__VAL_6 or - WILL_FIRE_RL_doFNMSUB_S or - MUX_fpu$server_core_request_put_1__VAL_7 or - WILL_FIRE_RL_doFDIV_S or - MUX_fpu$server_core_request_put_1__VAL_8 or - WILL_FIRE_RL_doFSQRT_S or - MUX_fpu$server_core_request_put_1__VAL_9 or - WILL_FIRE_RL_doFADD_D or - MUX_fpu$server_core_request_put_1__VAL_10 or - WILL_FIRE_RL_doFSUB_D or - MUX_fpu$server_core_request_put_1__VAL_11 or - WILL_FIRE_RL_doFMUL_D or - MUX_fpu$server_core_request_put_1__VAL_12 or - WILL_FIRE_RL_doFMADD_D or - MUX_fpu$server_core_request_put_1__VAL_13 or - WILL_FIRE_RL_doFMSUB_D or - MUX_fpu$server_core_request_put_1__VAL_14 or - WILL_FIRE_RL_doFNMADD_D or - MUX_fpu$server_core_request_put_1__VAL_15 or - WILL_FIRE_RL_doFNMSUB_D or - MUX_fpu$server_core_request_put_1__VAL_16 or - WILL_FIRE_RL_doFDIV_D or - MUX_fpu$server_core_request_put_1__VAL_17 or - WILL_FIRE_RL_doFSQRT_D or MUX_fpu$server_core_request_put_1__VAL_18) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_doFADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_1; - WILL_FIRE_RL_doFSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_2; - WILL_FIRE_RL_doFMUL_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_3; - WILL_FIRE_RL_doFMADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_4; - WILL_FIRE_RL_doFMSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_5; - WILL_FIRE_RL_doFNMADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_6; - WILL_FIRE_RL_doFNMSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_7; - WILL_FIRE_RL_doFDIV_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_8; - WILL_FIRE_RL_doFSQRT_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_9; - WILL_FIRE_RL_doFADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_10; - WILL_FIRE_RL_doFSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_11; - WILL_FIRE_RL_doFMUL_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_12; - WILL_FIRE_RL_doFMADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_13; - WILL_FIRE_RL_doFMSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_14; - WILL_FIRE_RL_doFNMADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_15; - WILL_FIRE_RL_doFNMSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_16; - WILL_FIRE_RL_doFDIV_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_17; - WILL_FIRE_RL_doFSQRT_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_18; - default: fpu$server_core_request_put = - 202'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fpu$EN_server_core_request_put = - WILL_FIRE_RL_doFADD_S || WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFSQRT_S || - WILL_FIRE_RL_doFADD_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFSQRT_D ; - assign fpu$EN_server_core_response_get = MUX_dw_result$wset_1__SEL_1 ; - assign fpu$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_begin ; - assign fpu$EN_server_reset_response_get = CAN_FIRE_RL_rl_reset_end ; - - // submodule frmFpuF - assign frmFpuF$D_IN = 1'b0 ; - assign frmFpuF$ENQ = 1'b0 ; - assign frmFpuF$DEQ = 1'b0 ; - assign frmFpuF$CLR = CAN_FIRE_RL_rl_reset_begin ; - - // submodule resetReqsF - assign resetReqsF$ENQ = EN_server_reset_request_put ; - assign resetReqsF$DEQ = - fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ; - assign resetReqsF$CLR = 1'b0 ; - - // submodule resetRspsF - assign resetRspsF$ENQ = - fpu$RDY_server_reset_response_get && resetRspsF$FULL_N && - stateR == 2'd0 ; - assign resetRspsF$DEQ = EN_server_reset_response_get ; - assign resetRspsF$CLR = 1'b0 ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q60 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2087 ? - _theResult___snd__h69240 : - _theResult____h61070 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3406 ? - _theResult___snd__h128373 : - _theResult____h120074 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q65 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2571 ? - _theResult___snd__h87093 : - _theResult____h78794 ; - assign IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q100 = - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3479 ? - _theResult___snd__h118726 : - _theResult___snd__h137125 ; - assign IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q94 = - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3086 ? - _theResult___snd__h118726 : - 57'd0 ; - assign IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q62 = - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2249 ? - _theResult___snd__h77852 : - 57'd0 ; - assign IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q68 = - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2644 ? - _theResult___snd__h77852 : - _theResult___snd__h95729 ; - assign IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_7_ETC___d2831 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - ((_theResult___fst_exp__h69177 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard1080_0b0_requestR_BIT_191_0b1_reques_ETC__q86 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87)) : - ((_theResult___fst_exp__h77863 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9815_0b0_requestR_BIT_191_0b1_reques_ETC__q88 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1301 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5519_0b0_requestR_BIT_159_0b1_reques_ETC__q35 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36) : - ((x__h36264[10:0] == 11'd2047) ? - requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard6249_0b0_requestR_BIT_159_0b1_reques_ETC__q37 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1416 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 ? - guard__h35519 != 2'b0 : - x__h36264[10:0] != 11'd2047 && guard__h36249 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d345 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard519_0b0_requestR_BIT_159_0b1_request_ETC__q8 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9) : - ((x__h8064[7:0] == 8'd255) ? - requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard049_0b0_requestR_BIT_159_0b1_request_ETC__q10 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d495 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 ? - guard__h7519 != 2'b0 : - x__h8064[7:0] != 8'd255 && guard__h8049 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1598 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462 ? - guard__h45160 != 2'b0 : - x__h45904[10:0] != 11'd2047 && guard__h45889 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d808 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638 ? - guard__h13641 != 2'b0 : - x__h14182[7:0] != 8'd255 && guard__h14167 != 2'b0 ; - assign IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d2085 = - (_theResult____h61070[56] ? - 6'd0 : - (_theResult____h61070[55] ? - 6'd1 : - (_theResult____h61070[54] ? - 6'd2 : - (_theResult____h61070[53] ? - 6'd3 : - (_theResult____h61070[52] ? - 6'd4 : - (_theResult____h61070[51] ? - 6'd5 : - (_theResult____h61070[50] ? - 6'd6 : - (_theResult____h61070[49] ? - 6'd7 : - (_theResult____h61070[48] ? - 6'd8 : - (_theResult____h61070[47] ? - 6'd9 : - (_theResult____h61070[46] ? - 6'd10 : - (_theResult____h61070[45] ? - 6'd11 : - (_theResult____h61070[44] ? - 6'd12 : - (_theResult____h61070[43] ? - 6'd13 : - (_theResult____h61070[42] ? - 6'd14 : - (_theResult____h61070[41] ? - 6'd15 : - (_theResult____h61070[40] ? - 6'd16 : - (_theResult____h61070[39] ? - 6'd17 : - (_theResult____h61070[38] ? - 6'd18 : - (_theResult____h61070[37] ? - 6'd19 : - (_theResult____h61070[36] ? - 6'd20 : - (_theResult____h61070[35] ? - 6'd21 : - (_theResult____h61070[34] ? - 6'd22 : - (_theResult____h61070[33] ? - 6'd23 : - (_theResult____h61070[32] ? - 6'd24 : - (_theResult____h61070[31] ? - 6'd25 : - (_theResult____h61070[30] ? - 6'd26 : - (_theResult____h61070[29] ? - 6'd27 : - (_theResult____h61070[28] ? - 6'd28 : - (_theResult____h61070[27] ? - 6'd29 : - (_theResult____h61070[26] ? - 6'd30 : - (_theResult____h61070[25] ? - 6'd31 : - (_theResult____h61070[24] ? - 6'd32 : - (_theResult____h61070[23] ? - 6'd33 : - (_theResult____h61070[22] ? - 6'd34 : - (_theResult____h61070[21] ? - 6'd35 : - (_theResult____h61070[20] ? - 6'd36 : - (_theResult____h61070[19] ? - 6'd37 : - (_theResult____h61070[18] ? - 6'd38 : - (_theResult____h61070[17] ? - 6'd39 : - (_theResult____h61070[16] ? - 6'd40 : - (_theResult____h61070[15] ? - 6'd41 : - (_theResult____h61070[14] ? - 6'd42 : - (_theResult____h61070[13] ? - 6'd43 : - (_theResult____h61070[12] ? - 6'd44 : - (_theResult____h61070[11] ? - 6'd45 : - (_theResult____h61070[10] ? - 6'd46 : - (_theResult____h61070[9] ? - 6'd47 : - (_theResult____h61070[8] ? - 6'd48 : - (_theResult____h61070[7] ? - 6'd49 : - (_theResult____h61070[6] ? - 6'd50 : - (_theResult____h61070[5] ? - 6'd51 : - (_theResult____h61070[4] ? - 6'd52 : - (_theResult____h61070[3] ? - 6'd53 : - (_theResult____h61070[2] ? - 6'd54 : - (_theResult____h61070[1] ? - 6'd55 : - (_theResult____h61070[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d3404 = - (_theResult____h120074[56] ? - 6'd0 : - (_theResult____h120074[55] ? - 6'd1 : - (_theResult____h120074[54] ? - 6'd2 : - (_theResult____h120074[53] ? - 6'd3 : - (_theResult____h120074[52] ? - 6'd4 : - (_theResult____h120074[51] ? - 6'd5 : - (_theResult____h120074[50] ? - 6'd6 : - (_theResult____h120074[49] ? - 6'd7 : - (_theResult____h120074[48] ? - 6'd8 : - (_theResult____h120074[47] ? - 6'd9 : - (_theResult____h120074[46] ? - 6'd10 : - (_theResult____h120074[45] ? - 6'd11 : - (_theResult____h120074[44] ? - 6'd12 : - (_theResult____h120074[43] ? - 6'd13 : - (_theResult____h120074[42] ? - 6'd14 : - (_theResult____h120074[41] ? - 6'd15 : - (_theResult____h120074[40] ? - 6'd16 : - (_theResult____h120074[39] ? - 6'd17 : - (_theResult____h120074[38] ? - 6'd18 : - (_theResult____h120074[37] ? - 6'd19 : - (_theResult____h120074[36] ? - 6'd20 : - (_theResult____h120074[35] ? - 6'd21 : - (_theResult____h120074[34] ? - 6'd22 : - (_theResult____h120074[33] ? - 6'd23 : - (_theResult____h120074[32] ? - 6'd24 : - (_theResult____h120074[31] ? - 6'd25 : - (_theResult____h120074[30] ? - 6'd26 : - (_theResult____h120074[29] ? - 6'd27 : - (_theResult____h120074[28] ? - 6'd28 : - (_theResult____h120074[27] ? - 6'd29 : - (_theResult____h120074[26] ? - 6'd30 : - (_theResult____h120074[25] ? - 6'd31 : - (_theResult____h120074[24] ? - 6'd32 : - (_theResult____h120074[23] ? - 6'd33 : - (_theResult____h120074[22] ? - 6'd34 : - (_theResult____h120074[21] ? - 6'd35 : - (_theResult____h120074[20] ? - 6'd36 : - (_theResult____h120074[19] ? - 6'd37 : - (_theResult____h120074[18] ? - 6'd38 : - (_theResult____h120074[17] ? - 6'd39 : - (_theResult____h120074[16] ? - 6'd40 : - (_theResult____h120074[15] ? - 6'd41 : - (_theResult____h120074[14] ? - 6'd42 : - (_theResult____h120074[13] ? - 6'd43 : - (_theResult____h120074[12] ? - 6'd44 : - (_theResult____h120074[11] ? - 6'd45 : - (_theResult____h120074[10] ? - 6'd46 : - (_theResult____h120074[9] ? - 6'd47 : - (_theResult____h120074[8] ? - 6'd48 : - (_theResult____h120074[7] ? - 6'd49 : - (_theResult____h120074[6] ? - 6'd50 : - (_theResult____h120074[5] ? - 6'd51 : - (_theResult____h120074[4] ? - 6'd52 : - (_theResult____h120074[3] ? - 6'd53 : - (_theResult____h120074[2] ? - 6'd54 : - (_theResult____h120074[1] ? - 6'd55 : - (_theResult____h120074[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d2569 = - (_theResult____h78794[56] ? - 6'd0 : - (_theResult____h78794[55] ? - 6'd1 : - (_theResult____h78794[54] ? - 6'd2 : - (_theResult____h78794[53] ? - 6'd3 : - (_theResult____h78794[52] ? - 6'd4 : - (_theResult____h78794[51] ? - 6'd5 : - (_theResult____h78794[50] ? - 6'd6 : - (_theResult____h78794[49] ? - 6'd7 : - (_theResult____h78794[48] ? - 6'd8 : - (_theResult____h78794[47] ? - 6'd9 : - (_theResult____h78794[46] ? - 6'd10 : - (_theResult____h78794[45] ? - 6'd11 : - (_theResult____h78794[44] ? - 6'd12 : - (_theResult____h78794[43] ? - 6'd13 : - (_theResult____h78794[42] ? - 6'd14 : - (_theResult____h78794[41] ? - 6'd15 : - (_theResult____h78794[40] ? - 6'd16 : - (_theResult____h78794[39] ? - 6'd17 : - (_theResult____h78794[38] ? - 6'd18 : - (_theResult____h78794[37] ? - 6'd19 : - (_theResult____h78794[36] ? - 6'd20 : - (_theResult____h78794[35] ? - 6'd21 : - (_theResult____h78794[34] ? - 6'd22 : - (_theResult____h78794[33] ? - 6'd23 : - (_theResult____h78794[32] ? - 6'd24 : - (_theResult____h78794[31] ? - 6'd25 : - (_theResult____h78794[30] ? - 6'd26 : - (_theResult____h78794[29] ? - 6'd27 : - (_theResult____h78794[28] ? - 6'd28 : - (_theResult____h78794[27] ? - 6'd29 : - (_theResult____h78794[26] ? - 6'd30 : - (_theResult____h78794[25] ? - 6'd31 : - (_theResult____h78794[24] ? - 6'd32 : - (_theResult____h78794[23] ? - 6'd33 : - (_theResult____h78794[22] ? - 6'd34 : - (_theResult____h78794[21] ? - 6'd35 : - (_theResult____h78794[20] ? - 6'd36 : - (_theResult____h78794[19] ? - 6'd37 : - (_theResult____h78794[18] ? - 6'd38 : - (_theResult____h78794[17] ? - 6'd39 : - (_theResult____h78794[16] ? - 6'd40 : - (_theResult____h78794[15] ? - 6'd41 : - (_theResult____h78794[14] ? - 6'd42 : - (_theResult____h78794[13] ? - 6'd43 : - (_theResult____h78794[12] ? - 6'd44 : - (_theResult____h78794[11] ? - 6'd45 : - (_theResult____h78794[10] ? - 6'd46 : - (_theResult____h78794[9] ? - 6'd47 : - (_theResult____h78794[8] ? - 6'd48 : - (_theResult____h78794[7] ? - 6'd49 : - (_theResult____h78794[6] ? - 6'd50 : - (_theResult____h78794[5] ? - 6'd51 : - (_theResult____h78794[4] ? - 6'd52 : - (_theResult____h78794[3] ? - 6'd53 : - (_theResult____h78794[2] ? - 6'd54 : - (_theResult____h78794[1] ? - 6'd55 : - (_theResult____h78794[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d3648 = - (_theResult___fst_exp__h128310 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard20084_0b0_requestR_BITS_191_TO_160_E_ETC__q110 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2144 = - (guard__h61080 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h69177 : - _theResult___exp__h69703 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2146 = - (guard__h61080 == 2'b0) ? - _theResult___fst_exp__h69177 : - (requestR[191] ? - _theResult___exp__h69703 : - _theResult___fst_exp__h69177) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2731 = - (guard__h61080 == 2'b0 || requestR[191]) ? - sfdin__h69171[56:34] : - _theResult___sfd__h69704 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2733 = - (guard__h61080 == 2'b0) ? - sfdin__h69171[56:34] : - (requestR[191] ? - _theResult___sfd__h69704 : - sfdin__h69171[56:34]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3463 = - (guard__h120084 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h128310 : - _theResult___exp__h129039 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3465 = - (guard__h120084 == 2'b0) ? - _theResult___fst_exp__h128310 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h129039 : - _theResult___fst_exp__h128310) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3592 = - (guard__h120084 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - sfdin__h128304[56:5] : - _theResult___sfd__h129040 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3594 = - (guard__h120084 == 2'b0) ? - sfdin__h128304[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h129040 : - sfdin__h128304[56:5]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2628 = - (guard__h78804 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h87030 : - _theResult___exp__h87556 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2630 = - (guard__h78804 == 2'b0) ? - _theResult___fst_exp__h87030 : - (requestR[191] ? - _theResult___exp__h87556 : - _theResult___fst_exp__h87030) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2777 = - (guard__h78804 == 2'b0 || requestR[191]) ? - sfdin__h87024[56:34] : - _theResult___sfd__h87557 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2779 = - (guard__h78804 == 2'b0) ? - sfdin__h87024[56:34] : - (requestR[191] ? - _theResult___sfd__h87557 : - sfdin__h87024[56:34]) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3138 = - (guard__h110776 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h118737 : - _theResult___exp__h119392 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3140 = - (guard__h110776 == 2'b0) ? - _theResult___fst_exp__h118737 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h119392 : - _theResult___fst_exp__h118737) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3532 = - (guard__h129151 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h137141 : - _theResult___exp__h137821 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3534 = - (guard__h129151 == 2'b0) ? - _theResult___fst_exp__h137141 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h137821 : - _theResult___fst_exp__h137141) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3565 = - (guard__h110776 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___snd__h118688[56:5] : - _theResult___sfd__h119393 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3567 = - (guard__h110776 == 2'b0) ? - _theResult___snd__h118688[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h119393 : - _theResult___snd__h118688[56:5]) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3611 = - (guard__h129151 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___snd__h137087[56:5] : - _theResult___sfd__h137822 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3613 = - (guard__h129151 == 2'b0) ? - _theResult___snd__h137087[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h137822 : - _theResult___snd__h137087[56:5]) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2301 = - (guard__h69815 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h77863 : - _theResult___exp__h78315 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2303 = - (guard__h69815 == 2'b0) ? - _theResult___fst_exp__h77863 : - (requestR[191] ? - _theResult___exp__h78315 : - _theResult___fst_exp__h77863) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2697 = - (guard__h87668 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h95745 : - _theResult___exp__h96222 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2699 = - (guard__h87668 == 2'b0) ? - _theResult___fst_exp__h95745 : - (requestR[191] ? - _theResult___exp__h96222 : - _theResult___fst_exp__h95745) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2750 = - (guard__h69815 == 2'b0 || requestR[191]) ? - _theResult___snd__h77814[56:34] : - _theResult___sfd__h78316 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2752 = - (guard__h69815 == 2'b0) ? - _theResult___snd__h77814[56:34] : - (requestR[191] ? - _theResult___sfd__h78316 : - _theResult___snd__h77814[56:34]) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2796 = - (guard__h87668 == 2'b0 || requestR[191]) ? - _theResult___snd__h95691[56:34] : - _theResult___sfd__h96223 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2798 = - (guard__h87668 == 2'b0) ? - _theResult___snd__h95691[56:34] : - (requestR[191] ? - _theResult___sfd__h96223 : - _theResult___snd__h95691[56:34]) ; - assign IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3656 = - (_theResult___fst_exp__h137141 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard29151_0b0_requestR_BITS_191_TO_160_E_ETC__q112 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1322 = - (guard__h35519 == 2'b0) ? - 11'd0 : - (requestR[159] ? _theResult___exp__h36135 : 11'd0) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1348 = - (guard__h36249 == 2'b0 || requestR[159]) ? - x__h36264[10:0] : - _theResult___exp__h36891 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1350 = - (guard__h36249 == 2'b0) ? - x__h36264[10:0] : - (requestR[159] ? _theResult___exp__h36891 : x__h36264[10:0]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1371 = - (guard__h35519 == 2'b0 || requestR[159]) ? - sfd___3__h35509[54:3] : - _theResult___sfd__h36136 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1373 = - (guard__h35519 == 2'b0) ? - sfd___3__h35509[54:3] : - (requestR[159] ? - _theResult___sfd__h36136 : - sfd___3__h35509[54:3]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1389 = - (guard__h36249 == 2'b0 || requestR[159]) ? - sfd___3__h35509[53:2] : - _theResult___sfd__h36892 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1391 = - (guard__h36249 == 2'b0) ? - sfd___3__h35509[53:2] : - (requestR[159] ? - _theResult___sfd__h36892 : - sfd___3__h35509[53:2]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d367 = - (guard__h7519 == 2'b0) ? - 8'd0 : - (requestR[159] ? _theResult___exp__h7935 : 8'd0) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d393 = - (guard__h8049 == 2'b0 || requestR[159]) ? - x__h8064[7:0] : - _theResult___exp__h8488 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d395 = - (guard__h8049 == 2'b0) ? - x__h8064[7:0] : - (requestR[159] ? _theResult___exp__h8488 : x__h8064[7:0]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d416 = - (guard__h7519 == 2'b0 || requestR[159]) ? - sfd___3__h7509[31:9] : - _theResult___sfd__h7936 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d418 = - (guard__h7519 == 2'b0) ? - sfd___3__h7509[31:9] : - (requestR[159] ? - _theResult___sfd__h7936 : - sfd___3__h7509[31:9]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d434 = - (guard__h8049 == 2'b0 || requestR[159]) ? - sfd___3__h7509[30:8] : - _theResult___sfd__h8489 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d436 = - (guard__h8049 == 2'b0) ? - sfd___3__h7509[30:8] : - (requestR[159] ? - _theResult___sfd__h8489 : - sfd___3__h7509[30:8]) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1047 = - (sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308[22] || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1016) ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - (IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d1020 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1045) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1051 = - (sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308 != 23'd0 && - !sV2_sfd__h1308[22]) ? - res__h18225 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1050 ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1060 = - IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d1020 ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1059 ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1062 = - (sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308[22]) ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - (IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1016 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1060) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1066 = - (sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308 != 23'd0 && - !sV2_sfd__h1308[22]) ? - res__h18225 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1065 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1048 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22]) ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1047 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1050 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22] && - sV2_exp__h1307 == 8'd255 && - sV2_sfd__h1308[22]) ? - 64'hFFFFFFFF7FC00000 : - { 32'hFFFFFFFF, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1048 } ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1052 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22]) ? - res__h17988 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1051 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1063 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22]) ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1062 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1065 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22] && - sV2_exp__h1307 == 8'd255 && - sV2_sfd__h1308[22]) ? - 64'hFFFFFFFF7FC00000 : - { 32'hFFFFFFFF, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1063 } ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1067 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22]) ? - res__h17988 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d1066 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1131 = - (sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0) ? - res___1__h26243 : - ((sV1_exp__h1204 == 8'd0) ? res___1__h26262 : res__h26278) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1132 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 == 23'd0) ? - res___1__h26233 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1131 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 = - ((sV1_exp__h1204 == 8'd0) ? - (sV1_sfd__h1205[22] ? - 6'd2 : - (sV1_sfd__h1205[21] ? - 6'd3 : - (sV1_sfd__h1205[20] ? - 6'd4 : - (sV1_sfd__h1205[19] ? - 6'd5 : - (sV1_sfd__h1205[18] ? - 6'd6 : - (sV1_sfd__h1205[17] ? - 6'd7 : - (sV1_sfd__h1205[16] ? - 6'd8 : - (sV1_sfd__h1205[15] ? - 6'd9 : - (sV1_sfd__h1205[14] ? - 6'd10 : - (sV1_sfd__h1205[13] ? - 6'd11 : - (sV1_sfd__h1205[12] ? - 6'd12 : - (sV1_sfd__h1205[11] ? - 6'd13 : - (sV1_sfd__h1205[10] ? - 6'd14 : - (sV1_sfd__h1205[9] ? - 6'd15 : - (sV1_sfd__h1205[8] ? - 6'd16 : - (sV1_sfd__h1205[7] ? - 6'd17 : - (sV1_sfd__h1205[6] ? - 6'd18 : - (sV1_sfd__h1205[5] ? - 6'd19 : - (sV1_sfd__h1205[4] ? - 6'd20 : - (sV1_sfd__h1205[3] ? - 6'd21 : - (sV1_sfd__h1205[2] ? - 6'd22 : - (sV1_sfd__h1205[1] ? - 6'd23 : - (sV1_sfd__h1205[0] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3624 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0) ? - _theResult___snd_fst_sfd__h99811 : - _theResult___fst_sfd__h137938 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3660 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 || - (sV1_exp__h1204 == 8'd255 || sV1_exp__h1204 == 8'd0) && - sV1_sfd__h1205 == 23'd0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((sV1_exp__h1204 == 8'd0) ? - IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d3640 : - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3658) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3695 = - (sV1_exp__h1204 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 && - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674[4] : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 && - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691[4] ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3698 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0) ? - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22] : - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3695 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3705 = - (sV1_exp__h1204 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 && - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674[3] : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 && - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691[3] ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3719 = - (sV1_exp__h1204 == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 || - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674[2] : - !SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 || - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3717 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3731 = - (sV1_exp__h1204 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 && - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 || - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674[1]) : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 && - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3729 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3743 = - (sV1_exp__h1204 == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 || - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674[0] : - !SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 || - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3741 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d904 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 == 23'd0) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d833 : - ((sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0) ? - 32'd0 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d902) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d963 = - (sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0) ? - 32'd0 : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934[19] ? - 32'hFFFFFFFF : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d961) ; - assign IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1242 = - sfd__h2605[31] ? - 6'd0 : - (sfd__h2605[30] ? - 6'd1 : - (sfd__h2605[29] ? - 6'd2 : - (sfd__h2605[28] ? - 6'd3 : - (sfd__h2605[27] ? - 6'd4 : - (sfd__h2605[26] ? - 6'd5 : - (sfd__h2605[25] ? - 6'd6 : - (sfd__h2605[24] ? - 6'd7 : - (sfd__h2605[23] ? - 6'd8 : - (sfd__h2605[22] ? - 6'd9 : - (sfd__h2605[21] ? - 6'd10 : - (sfd__h2605[20] ? - 6'd11 : - (sfd__h2605[19] ? - 6'd12 : - (sfd__h2605[18] ? - 6'd13 : - (sfd__h2605[17] ? - 6'd14 : - (sfd__h2605[16] ? - 6'd15 : - (sfd__h2605[15] ? - 6'd16 : - (sfd__h2605[14] ? - 6'd17 : - (sfd__h2605[13] ? - 6'd18 : - (sfd__h2605[12] ? - 6'd19 : - (sfd__h2605[11] ? - 6'd20 : - (sfd__h2605[10] ? - 6'd21 : - (sfd__h2605[9] ? - 6'd22 : - (sfd__h2605[8] ? - 6'd23 : - (sfd__h2605[7] ? - 6'd24 : - (sfd__h2605[6] ? - 6'd25 : - (sfd__h2605[5] ? - 6'd26 : - (sfd__h2605[4] ? - 6'd27 : - (sfd__h2605[3] ? - 6'd28 : - (sfd__h2605[2] ? - 6'd29 : - (sfd__h2605[1] ? - 6'd30 : - (sfd__h2605[0] ? - 6'd31 : - 6'd55))))))))))))))))))))))))))))))) ; - assign IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d275 = - sfd__h2605[31] ? - 6'd0 : - (sfd__h2605[30] ? - 6'd1 : - (sfd__h2605[29] ? - 6'd2 : - (sfd__h2605[28] ? - 6'd3 : - (sfd__h2605[27] ? - 6'd4 : - (sfd__h2605[26] ? - 6'd5 : - (sfd__h2605[25] ? - 6'd6 : - (sfd__h2605[24] ? - 6'd7 : - (sfd__h2605[23] ? - 6'd8 : - (sfd__h2605[22] ? - 6'd9 : - (sfd__h2605[21] ? - 6'd10 : - (sfd__h2605[20] ? - 6'd11 : - (sfd__h2605[19] ? - 6'd12 : - (sfd__h2605[18] ? - 6'd13 : - (sfd__h2605[17] ? - 6'd14 : - (sfd__h2605[16] ? - 6'd15 : - (sfd__h2605[15] ? - 6'd16 : - (sfd__h2605[14] ? - 6'd17 : - (sfd__h2605[13] ? - 6'd18 : - (sfd__h2605[12] ? - 6'd19 : - (sfd__h2605[11] ? - 6'd20 : - (sfd__h2605[10] ? - 6'd21 : - (sfd__h2605[9] ? - 6'd22 : - (sfd__h2605[8] ? - 6'd23 : - (sfd__h2605[7] ? - 6'd24 : - (sfd__h2605[6] ? - 6'd25 : - (sfd__h2605[5] ? - 6'd26 : - (sfd__h2605[4] ? - 6'd27 : - (sfd__h2605[3] ? - 6'd28 : - (sfd__h2605[2] ? - 6'd29 : - (sfd__h2605[1] ? - 6'd30 : - (sfd__h2605[0] ? - 6'd31 : - 6'd32))))))))))))))))))))))))))))))) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d900 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d873 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d894 ? - ((x__h15999[56:25] == 32'h7FFFFFFF) ? - x__h15999[56:25] : - x__h15999[56:25] + 32'd1) : - x__h15999[56:25]) : - 32'd0 ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d902 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838 == - 20'd1048545) ? - ((_theResult_____2__h15258[32:31] == 2'b11) ? - _theResult_____2__h15258[31:0] : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d833) : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871[19] ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d833 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d900) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d926 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838 == - 20'd1048545) ? - _theResult_____2__h15258[32:31] == 2'b11 && - guard__h15256 != 2'd0 : - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d873 || - guard__h15810 != 2'd0) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d961 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d936 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d955 ? - ((x__h17039[56:25] == 32'hFFFFFFFF) ? - x__h17039[56:25] : - x__h17039[56:25] + 32'd1) : - x__h17039[56:25]) : - 32'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1686 = - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1659 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1680 ? - ((x__h47920[85:54] == 32'h7FFFFFFF) ? - x__h47920[85:54] : - x__h47920[85:54] + 32'd1) : - x__h47920[85:54]) : - 32'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1688 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624 == - 24'd16777185) ? - ((_theResult_____2__h47179[32:31] == 2'b11) ? - _theResult_____2__h47179[31:0] : - IF_requestR_3_BIT_191_202_THEN_2147483648_ELSE_ETC___d1619) : - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657[23] ? - IF_requestR_3_BIT_191_202_THEN_2147483648_ELSE_ETC___d1619 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1686) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1712 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624 == - 24'd16777185) ? - _theResult_____2__h47179[32:31] == 2'b11 && - guard__h47177 != 2'd0 : - !NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1659 || - guard__h47731 != 2'd0) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1747 = - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1722 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1741 ? - ((x__h48943[85:54] == 32'hFFFFFFFF) ? - x__h48943[85:54] : - x__h48943[85:54] + 32'd1) : - x__h48943[85:54]) : - 32'd0 ; - assign IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d1302 = - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248) ? - requestR[159] : - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1301 ; - assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d3640 = - (!_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 || - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 || - _theResult___fst_exp__h118737 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10776_0b0_requestR_BITS_191_TO_160_E_ETC__q108 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109) ; - assign IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1045 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1044 ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 ; - assign IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d1059 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1044 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1040 = - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1029 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1031 : - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1034 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 && - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1036 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3478 = - ((SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q99[10], - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q99 }) - - 12'd3074 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3658 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 ? - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d3648 : - IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3656) : - requestR[191:160] == 32'hFFFFFFFF && requestR[159] ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3717 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691[2] : - _theResult___fst_exp__h137922 == 11'd2047 && - _theResult___fst_sfd__h137923 == 52'd0 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3729 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691[1] : - _theResult___fst_exp__h137141 == 11'd0 && - guard__h129151 != 2'b0 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3741 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691[0] : - _theResult___fst_exp__h137141 != 11'd2047 && - guard__h129151 != 2'b0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2643 = - ((SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q67[7], - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q67 }) - - 9'd386 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2849 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - ((_theResult___fst_exp__h87030 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard8804_0b0_requestR_BIT_191_0b1_reques_ETC__q90 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91)) : - ((_theResult___fst_exp__h95745 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard7668_0b0_requestR_BIT_191_0b1_reques_ETC__q92 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93)) ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2927 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898[2] : - _theResult___fst_exp__h96323 == 8'd255 && - _theResult___fst_sfd__h96324 == 23'd0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2940 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898[1] : - _theResult___fst_exp__h95745 == 8'd0 && guard__h87668 != 2'b0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2953 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898[0] : - _theResult___fst_exp__h95745 != 8'd255 && - guard__h87668 != 2'b0 ; - assign IF_requestR_3_BITS_126_TO_116_754_EQ_2047_755__ETC___d3802 = - (requestR[126:116] == 11'd2047 && requestR[115] || - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3771) ? - requestR[191:128] : - (requestR_3_BITS_126_TO_116_754_EQ_0_768_AND_re_ETC___d3775 ? - requestR[127:64] : - res__h142948) ; - assign IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d1020 = - sV2_exp__h1307 == 8'd0 && sV2_sfd__h1308 == 23'd0 && - requestR[127:96] == 32'hFFFFFFFF && - requestR[95] && - sV1_exp__h1204 == 8'd0 && - sV1_sfd__h1205 == 23'd0 && - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ; - assign IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1399 = - (requestR[159:128] == 32'd0 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248) ? - 52'd0 : - _theResult___snd_fst_sfd__h36995 ; - assign IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1581 = - (requestR[159:128] == 32'd0 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 || - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461) ? - 52'd0 : - _theResult___snd_fst_sfd__h46634 ; - assign IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d405 = - (requestR[159:128] == 32'd0 || - !sfd__h2605[31] && !sfd__h2605[30] && !sfd__h2605[29] && - !sfd__h2605[28] && - !sfd__h2605[27] && - !sfd__h2605[26] && - !sfd__h2605[25] && - !sfd__h2605[24] && - !sfd__h2605[23] && - !sfd__h2605[22] && - !sfd__h2605[21] && - !sfd__h2605[20] && - !sfd__h2605[19] && - !sfd__h2605[18] && - !sfd__h2605[17] && - !sfd__h2605[16] && - !sfd__h2605[15] && - !sfd__h2605[14] && - !sfd__h2605[13] && - !sfd__h2605[12] && - !sfd__h2605[11] && - !sfd__h2605[10] && - !sfd__h2605[9] && - !sfd__h2605[8] && - !sfd__h2605[7] && - !sfd__h2605[6] && - !sfd__h2605[5] && - !sfd__h2605[4] && - !sfd__h2605[3] && - !sfd__h2605[2] && - !sfd__h2605[1] && - !sfd__h2605[0]) ? - 8'd0 : - _theResult___snd_fst_exp__h8597 ; - assign IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d722 = - (requestR[159:128] == 32'd0 || - !requestR[159] && - NOT_requestR_3_BIT_158_07_08_AND_NOT_requestR__ETC___d598) ? - 8'd0 : - _theResult___snd_fst_exp__h14714 ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d1749 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 32'd0 : - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720[23] ? - 32'hFFFFFFFF : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1747) ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3815 = - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3771 ? - requestR[127:64] : - (requestR_3_BITS_126_TO_116_754_EQ_0_768_AND_re_ETC___d3775 ? - requestR[191:128] : - res__h147441) ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3881 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - res___1__h155301 : - ((requestR[190:180] == 11'd0) ? - res___1__h155320 : - res__h155336) ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 = - ((requestR[190:180] == 11'd0) ? - (requestR[179] ? - 6'd2 : - (requestR[178] ? - 6'd3 : - (requestR[177] ? - 6'd4 : - (requestR[176] ? - 6'd5 : - (requestR[175] ? - 6'd6 : - (requestR[174] ? - 6'd7 : - (requestR[173] ? - 6'd8 : - (requestR[172] ? - 6'd9 : - (requestR[171] ? - 6'd10 : - (requestR[170] ? - 6'd11 : - (requestR[169] ? - 6'd12 : - (requestR[168] ? - 6'd13 : - (requestR[167] ? - 6'd14 : - (requestR[166] ? - 6'd15 : - (requestR[165] ? - 6'd16 : - (requestR[164] ? - 6'd17 : - (requestR[163] ? - 6'd18 : - (requestR[162] ? - 6'd19 : - (requestR[161] ? - 6'd20 : - (requestR[160] ? - 6'd21 : - (requestR[159] ? - 6'd22 : - (requestR[158] ? - 6'd23 : - (requestR[157] ? - 6'd24 : - (requestR[156] ? - 6'd25 : - (requestR[155] ? - 6'd26 : - (requestR[154] ? - 6'd27 : - (requestR[153] ? - 6'd28 : - (requestR[152] ? - 6'd29 : - (requestR[151] ? - 6'd30 : - (requestR[150] ? - 6'd31 : - (requestR[149] ? - 6'd32 : - (requestR[148] ? - 6'd33 : - (requestR[147] ? - 6'd34 : - (requestR[146] ? - 6'd35 : - (requestR[145] ? - 6'd36 : - (requestR[144] ? - 6'd37 : - (requestR[143] ? - 6'd38 : - (requestR[142] ? - 6'd39 : - (requestR[141] ? - 6'd40 : - (requestR[140] ? - 6'd41 : - (requestR[139] ? - 6'd42 : - (requestR[138] ? - 6'd43 : - (requestR[137] ? - 6'd44 : - (requestR[136] ? - 6'd45 : - (requestR[135] ? - 6'd46 : - (requestR[134] ? - 6'd47 : - (requestR[133] ? - 6'd48 : - (requestR[132] ? - 6'd49 : - (requestR[131] ? - 6'd50 : - (requestR[130] ? - 6'd51 : - (requestR[129] ? - 6'd52 : - (requestR[128] ? - 6'd53 : - 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2851 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 ? - IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_7_ETC___d2831 : - requestR[191]) : - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 ? - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2849 : - requestR[191]) ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2902 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2884 : - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 && - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898[4] ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2913 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2909 : - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 && - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898[3] ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2929 = - (requestR[190:180] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2921 : - !SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 || - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2927 ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2942 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2936 : - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 && - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2940 ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2955 = - (requestR[190:180] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2949 : - !SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 || - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2953 ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d1690 = - (requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0) ? - IF_requestR_3_BIT_191_202_THEN_2147483648_ELSE_ETC___d1619 : - ((requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 32'd0 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1688) ; - assign IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d2809 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - _theResult___snd_fst_sfd__h53394 : - _theResult___fst_sfd__h96339 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1006 = - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22] && - sV2_exp__h1307 == 8'd255 && - sV2_sfd__h1308 != 23'd0 && - !sV2_sfd__h1308[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1016 = - sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159] && - sV2_exp__h1307 == 8'd0 && - sV2_sfd__h1308 == 23'd0 && - (requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1029 = - sV1_exp__h1204 < sV2_exp__h1307 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 = - sV1_exp__h1204 == sV2_exp__h1307 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1031 = - sV1_sfd__h1205 < sV2_sfd__h1308 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1034 = - sV1_exp__h1204 <= sV2_exp__h1307 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1036 = - sV1_sfd__h1205 <= sV2_sfd__h1308 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1054 = - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22] || - sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308 != 23'd0 && - !sV2_sfd__h1308[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1087 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1054 || - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22] || - sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1098 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1034 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1036) && - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1029 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 || - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1031) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1102 = - sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0 && - sV2_exp__h1307 == 8'd0 && - sV2_sfd__h1308 == 23'd0 || - NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1101 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[158:128] : - 31'h7FC00000 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d832 = - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 || - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) && - sV1_exp__h1204 == 8'd255 && - sV1_sfd__h1205 == 23'd0 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d833 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 32'h80000000 : - 32'h7FFFFFFF ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836 = - sV1_exp__h1204 - 8'd127 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - -b__h15323 : - b__h15323 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d965 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 32'd0 : - ((sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 == 23'd0) ? - 32'hFFFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d963) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d973 = - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 || - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 == 23'd0 || - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d936 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d955 && - x__h17039[56:25] == 32'hFFFFFFFF) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d984 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d973, - 3'd0, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d978 } == - 5'd0 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d973 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1648 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h47177 == 2'b10) ? - IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[53] : - guard__h47177 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h47177 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[85] && - guard__h47177 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1680 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h47731 == 2'b10) ? - x__h47920[54] : - guard__h47731 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h47731 != 2'd0 : - requestR[194:192] == 3'h1 && x__h47920[85] && - guard__h47731 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1741 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h48722 == 2'b10) ? - x__h48943[54] : - guard__h48722 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h48722 != 2'd0 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d862 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h15256 == 2'b10) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[24] : - guard__h15256 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h15256 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[56] && - guard__h15256 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d894 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h15810 == 2'b10) ? - x__h15999[25] : - guard__h15810 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h15810 != 2'd0 : - requestR[194:192] == 3'h1 && x__h15999[56] && - guard__h15810 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d955 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h16818 == 2'b10) ? - x__h17039[25] : - guard__h16818 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h16818 != 2'd0 ; - assign IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1456 = - requestR[159] ? - 6'd0 : - (requestR[158] ? - 6'd1 : - (requestR[157] ? - 6'd2 : - (requestR[156] ? - 6'd3 : - (requestR[155] ? - 6'd4 : - (requestR[154] ? - 6'd5 : - (requestR[153] ? - 6'd6 : - (requestR[152] ? - 6'd7 : - (requestR[151] ? - 6'd8 : - (requestR[150] ? - 6'd9 : - (requestR[149] ? - 6'd10 : - (requestR[148] ? - 6'd11 : - (requestR[147] ? - 6'd12 : - (requestR[146] ? - 6'd13 : - (requestR[145] ? - 6'd14 : - (requestR[144] ? - 6'd15 : - (requestR[143] ? - 6'd16 : - (requestR[142] ? - 6'd17 : - (requestR[141] ? - 6'd18 : - (requestR[140] ? - 6'd19 : - (requestR[139] ? - 6'd20 : - (requestR[138] ? - 6'd21 : - (requestR[137] ? - 6'd22 : - (requestR[136] ? - 6'd23 : - (requestR[135] ? - 6'd24 : - (requestR[134] ? - 6'd25 : - (requestR[133] ? - 6'd26 : - (requestR[132] ? - 6'd27 : - (requestR[131] ? - 6'd28 : - (requestR[130] ? - 6'd29 : - (requestR[129] ? - 6'd30 : - (requestR[128] ? - 6'd31 : - 6'd55))))))))))))))))))))))))))))))) ; - assign IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d632 = - requestR[159] ? - 6'd0 : - (requestR[158] ? - 6'd1 : - (requestR[157] ? - 6'd2 : - (requestR[156] ? - 6'd3 : - (requestR[155] ? - 6'd4 : - (requestR[154] ? - 6'd5 : - (requestR[153] ? - 6'd6 : - (requestR[152] ? - 6'd7 : - (requestR[151] ? - 6'd8 : - (requestR[150] ? - 6'd9 : - (requestR[149] ? - 6'd10 : - (requestR[148] ? - 6'd11 : - (requestR[147] ? - 6'd12 : - (requestR[146] ? - 6'd13 : - (requestR[145] ? - 6'd14 : - (requestR[144] ? - 6'd15 : - (requestR[143] ? - 6'd16 : - (requestR[142] ? - 6'd17 : - (requestR[141] ? - 6'd18 : - (requestR[140] ? - 6'd19 : - (requestR[139] ? - 6'd20 : - (requestR[138] ? - 6'd21 : - (requestR[137] ? - 6'd22 : - (requestR[136] ? - 6'd23 : - (requestR[135] ? - 6'd24 : - (requestR[134] ? - 6'd25 : - (requestR[133] ? - 6'd26 : - (requestR[132] ? - 6'd27 : - (requestR[131] ? - 6'd28 : - (requestR[130] ? - 6'd29 : - (requestR[129] ? - 6'd30 : - (requestR[128] ? - 6'd31 : - 6'd32))))))))))))))))))))))))))))))) ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d486 = - (sfd__h2605[31] || sfd__h2605[30] || sfd__h2605[29] || - sfd__h2605[28] || - sfd__h2605[27] || - sfd__h2605[26] || - sfd__h2605[25] || - sfd__h2605[24] || - sfd__h2605[23] || - sfd__h2605[22] || - sfd__h2605[21] || - sfd__h2605[20] || - sfd__h2605[19] || - sfd__h2605[18] || - sfd__h2605[17] || - sfd__h2605[16] || - sfd__h2605[15] || - sfd__h2605[14] || - sfd__h2605[13] || - sfd__h2605[12] || - sfd__h2605[11] || - sfd__h2605[10] || - sfd__h2605[9] || - sfd__h2605[8] || - sfd__h2605[7] || - sfd__h2605[6] || - sfd__h2605[5] || - sfd__h2605[4] || - sfd__h2605[3] || - sfd__h2605[2] || - sfd__h2605[1] || - sfd__h2605[0]) && - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 && - _theResult___fst_exp__h8588 == 8'd255 && - _theResult___fst_sfd__h8589 == 23'd0) ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d489 = - (sfd__h2605[31] || sfd__h2605[30] || sfd__h2605[29] || - sfd__h2605[28] || - sfd__h2605[27] || - sfd__h2605[26] || - sfd__h2605[25] || - sfd__h2605[24] || - sfd__h2605[23] || - sfd__h2605[22] || - sfd__h2605[21] || - sfd__h2605[20] || - sfd__h2605[19] || - sfd__h2605[18] || - sfd__h2605[17] || - sfd__h2605[16] || - sfd__h2605[15] || - sfd__h2605[14] || - sfd__h2605[13] || - sfd__h2605[12] || - sfd__h2605[11] || - sfd__h2605[10] || - sfd__h2605[9] || - sfd__h2605[8] || - sfd__h2605[7] || - sfd__h2605[6] || - sfd__h2605[5] || - sfd__h2605[4] || - sfd__h2605[3] || - sfd__h2605[2] || - sfd__h2605[1] || - sfd__h2605[0]) && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d498 = - (sfd__h2605[31] || sfd__h2605[30] || sfd__h2605[29] || - sfd__h2605[28] || - sfd__h2605[27] || - sfd__h2605[26] || - sfd__h2605[25] || - sfd__h2605[24] || - sfd__h2605[23] || - sfd__h2605[22] || - sfd__h2605[21] || - sfd__h2605[20] || - sfd__h2605[19] || - sfd__h2605[18] || - sfd__h2605[17] || - sfd__h2605[16] || - sfd__h2605[15] || - sfd__h2605[14] || - sfd__h2605[13] || - sfd__h2605[12] || - sfd__h2605[11] || - sfd__h2605[10] || - sfd__h2605[9] || - sfd__h2605[8] || - sfd__h2605[7] || - sfd__h2605[6] || - sfd__h2605[5] || - sfd__h2605[4] || - sfd__h2605[3] || - sfd__h2605[2] || - sfd__h2605[1] || - sfd__h2605[0]) && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 && - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d495 ; - assign IF_requestR_3_BIT_191_202_THEN_2147483648_ELSE_ETC___d1619 = - requestR[191] ? 32'h80000000 : 32'h7FFFFFFF ; - assign IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631 = - requestR[191] ? -b__h47244 : b__h47244 ; - assign IF_requestR_3_BIT_191_202_THEN_NOT_requestR_3__ETC___d3795 = - requestR[191] ? - !requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3784 || - requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 && - !requestR_3_BITS_179_TO_128_611_ULE_requestR_3__ETC___d3787 : - requestR_3_BITS_190_TO_180_609_ULT_requestR_3__ETC___d3791 || - requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 && - requestR_3_BITS_179_TO_128_611_ULT_requestR_3__ETC___d3792 ; - assign IF_sfd___33631_BIT_7_THEN_2_ELSE_0__q21 = - sfd___3__h13631[7] ? 2'd2 : 2'd0 ; - assign IF_sfd___33631_BIT_8_THEN_2_ELSE_0__q20 = - sfd___3__h13631[8] ? 2'd2 : 2'd0 ; - assign IF_sfd___3509_BIT_7_THEN_2_ELSE_0__q7 = - sfd___3__h7509[7] ? 2'd2 : 2'd0 ; - assign IF_sfd___3509_BIT_8_THEN_2_ELSE_0__q6 = - sfd___3__h7509[8] ? 2'd2 : 2'd0 ; - assign IF_sfd___35150_BIT_1_THEN_2_ELSE_0__q48 = - sfd___3__h45150[1] ? 2'd2 : 2'd0 ; - assign IF_sfd___35150_BIT_2_THEN_2_ELSE_0__q47 = - sfd___3__h45150[2] ? 2'd2 : 2'd0 ; - assign IF_sfd___35509_BIT_1_THEN_2_ELSE_0__q34 = - sfd___3__h35509[1] ? 2'd2 : 2'd0 ; - assign IF_sfd___35509_BIT_2_THEN_2_ELSE_0__q33 = - sfd___3__h35509[2] ? 2'd2 : 2'd0 ; - assign IF_sfdin28304_BIT_4_THEN_2_ELSE_0__q98 = - sfdin__h128304[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin7024_BIT_33_THEN_2_ELSE_0__q66 = - sfdin__h87024[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin9171_BIT_33_THEN_2_ELSE_0__q61 = - sfdin__h69171[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd18688_BIT_4_THEN_2_ELSE_0__q95 = - _theResult___snd__h118688[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd37087_BIT_4_THEN_2_ELSE_0__q101 = - _theResult___snd__h137087[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd5691_BIT_33_THEN_2_ELSE_0__q69 = - _theResult___snd__h95691[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd7814_BIT_33_THEN_2_ELSE_0__q63 = - _theResult___snd__h77814[33] ? 2'd2 : 2'd0 ; - assign IF_x5999_BIT_24_THEN_2_ELSE_0__q31 = x__h15999[24] ? 2'd2 : 2'd0 ; - assign IF_x7039_BIT_24_THEN_2_ELSE_0__q32 = x__h17039[24] ? 2'd2 : 2'd0 ; - assign IF_x7920_BIT_53_THEN_2_ELSE_0__q58 = x__h47920[53] ? 2'd2 : 2'd0 ; - assign IF_x8943_BIT_53_THEN_2_ELSE_0__q59 = x__h48943[53] ? 2'd2 : 2'd0 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838 = - -{ {12{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836[7]}}, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836 } ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d870 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838 + - 20'd32 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d870 - - 20'd2 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d873 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871 ^ - 20'h80000) <= - 20'd524320 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d870 - - 20'd1 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d936 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934 ^ - 20'h80000) <= - 20'd524320 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624 = - -{ {13{requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622[10]}}, - requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622 } ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1656 = - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624 + - 24'd32 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657 = - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1656 - - 24'd2 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1659 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657 ^ - 24'h800000) <= - 24'd8388640 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720 = - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1656 - - 24'd1 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1722 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720 ^ - 24'h800000) <= - 24'd8388640 ; - assign NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2921 = - !_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 || - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869[2] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d2949 = - !_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 || - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869[0] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881[0]) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1043 = - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0 || - sV2_exp__h1307 != 8'd0 || - sV2_sfd__h1308 != 23'd0) && - requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d1042 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1044 = - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV2_exp__h1307 != 8'd255 || sV2_sfd__h1308 == 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1043 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1097 = - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1029 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 || - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1031) && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1034 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1030 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1036) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1103 = - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV2_exp__h1307 != 8'd255 || sV2_sfd__h1308 == 23'd0) && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1102 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1119 = - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV2_exp__h1307 != 8'd255 || sV2_sfd__h1308 == 23'd0) && - (requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d1042 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1102) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057 = - !sV1_sfd__h1205[21] && !sV1_sfd__h1205[20] && - !sV1_sfd__h1205[19] && - !sV1_sfd__h1205[18] && - !sV1_sfd__h1205[17] && - !sV1_sfd__h1205[16] && - !sV1_sfd__h1205[15] && - !sV1_sfd__h1205[14] && - !sV1_sfd__h1205[13] && - !sV1_sfd__h1205[12] && - !sV1_sfd__h1205[11] && - !sV1_sfd__h1205[10] && - !sV1_sfd__h1205[9] && - !sV1_sfd__h1205[8] && - !sV1_sfd__h1205[7] && - !sV1_sfd__h1205[6] && - !sV1_sfd__h1205[5] && - !sV1_sfd__h1205[4] && - !sV1_sfd__h1205[3] && - !sV1_sfd__h1205[2] && - !sV1_sfd__h1205[1] && - !sV1_sfd__h1205[0] ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d915 = - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - ((NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d838 == - 20'd1048545) ? - _theResult_____2__h15258[32:31] != 2'b11 : - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d873 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d894 && - x__h15999[56:25] == 32'h7FFFFFFF) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d978 = - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d936 || - guard__h16818 != 2'd0) ; - assign NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d283 = - !sfd__h2605[31] && !sfd__h2605[30] && !sfd__h2605[29] && - !sfd__h2605[28] && - !sfd__h2605[27] && - !sfd__h2605[26] && - !sfd__h2605[25] && - !sfd__h2605[24] && - !sfd__h2605[23] && - !sfd__h2605[22] && - !sfd__h2605[21] && - !sfd__h2605[20] && - !sfd__h2605[19] && - !sfd__h2605[18] && - !sfd__h2605[17] && - !sfd__h2605[16] && - !sfd__h2605[15] && - !sfd__h2605[14] && - !sfd__h2605[13] && - !sfd__h2605[12] && - !sfd__h2605[11] && - !sfd__h2605[10] && - !sfd__h2605[9] && - !sfd__h2605[8] && - !sfd__h2605[7] && - !sfd__h2605[6] && - !sfd__h2605[5] && - !sfd__h2605[4] && - !sfd__h2605[3] && - !sfd__h2605[2] && - !sfd__h2605[1] && - !sfd__h2605[0] || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 ; - assign NOT_requestR_3_BITS_159_TO_128_44_EQ_0_45_46_A_ETC___d800 = - requestR[159:128] != 32'd0 && - (requestR[159] || - requestR_3_BIT_158_07_OR_requestR_3_BIT_157_09_ETC___d789) && - (!_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638 && - _theResult___fst_exp__h14705 == 8'd255 && - _theResult___fst_sfd__h14706 == 23'd0) ; - assign NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1701 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - ((NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1624 == - 24'd16777185) ? - _theResult_____2__h47179[32:31] != 2'b11 : - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1659 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1680 && - x__h47920[85:54] == 32'h7FFFFFFF) ; - assign NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1764 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - !NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1722 || - guard__h48722 != 2'd0) ; - assign NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3799 = - (requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0 || - requestR[126:116] != 11'd0 || - requestR[115:64] != 52'd0) && - (requestR[191] && !requestR[127] || - (requestR[191] || !requestR[127]) && - IF_requestR_3_BIT_191_202_THEN_NOT_requestR_3__ETC___d3795) ; - assign NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3860 = - (requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - (requestR[191] && !requestR[127] || - (requestR[191] || !requestR[127]) && - IF_requestR_3_BIT_191_202_THEN_NOT_requestR_3__ETC___d3795 || - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3843) ; - assign NOT_requestR_3_BITS_190_TO_180_609_ULT_request_ETC___d3839 = - !requestR_3_BITS_190_TO_180_609_ULT_requestR_3__ETC___d3791 && - (!requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 || - !requestR_3_BITS_179_TO_128_611_ULT_requestR_3__ETC___d3792) && - requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3784 && - (!requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 || - requestR_3_BITS_179_TO_128_611_ULE_requestR_3__ETC___d3787) ; - assign NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1101 = - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159] || - requestR[127:96] == 32'hFFFFFFFF && requestR[95]) && - (requestR[191:160] == 32'hFFFFFFFF && requestR[159] || - requestR[127:96] != 32'hFFFFFFFF || - !requestR[95]) && - ((requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ? - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1097 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1098) ; - assign NOT_requestR_3_BIT_158_07_08_AND_NOT_requestR__ETC___d598 = - !requestR[158] && !requestR[157] && !requestR[156] && - !requestR[155] && - !requestR[154] && - !requestR[153] && - !requestR[152] && - !requestR[151] && - !requestR[150] && - !requestR[149] && - !requestR[148] && - !requestR[147] && - !requestR[146] && - !requestR[145] && - !requestR[144] && - !requestR[143] && - !requestR[142] && - !requestR[141] && - !requestR[140] && - !requestR[139] && - !requestR[138] && - !requestR[137] && - !requestR[136] && - !requestR[135] && - !requestR[134] && - !requestR[133] && - !requestR[132] && - !requestR[131] && - !requestR[130] && - !requestR[129] && - !requestR[128] ; - assign NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192 = - !requestR[179] && !requestR[178] && !requestR[177] && - !requestR[176] && - !requestR[175] && - !requestR[174] && - !requestR[173] && - !requestR[172] && - !requestR[171] && - !requestR[170] && - !requestR[169] && - !requestR[168] && - !requestR[167] && - !requestR[166] && - !requestR[165] && - !requestR[164] && - !requestR[163] && - !requestR[162] && - !requestR[161] && - !requestR[160] && - !requestR[159] && - NOT_requestR_3_BIT_158_07_08_AND_NOT_requestR__ETC___d598 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155 = - { {4{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836[7]}}, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d836 } ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155 + - 12'd1023 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q99 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96[10:0] - - 11'd1023 ; - assign SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322 = - { requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622[10], - requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622 } ; - assign SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 = - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 = - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322 + - 12'd127 ; - assign SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q67 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64[7:0] - - 8'd127 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2087 = - ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d2085 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869 = - { 3'd0, - _theResult___fst_exp__h69177 == 8'd0 && - (sfdin__h69171[56:34] == 23'd0 || guard__h61080 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h69804 == 8'd255 && - _theResult___fst_sfd__h69805 == 23'd0, - 1'd0, - _theResult___fst_exp__h69177 != 8'd255 && - guard__h61080 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3406 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d3404 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3691 = - { 3'd0, - _theResult___fst_exp__h128310 == 11'd0 && - (sfdin__h128304[56:5] == 52'd0 || guard__h120084 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h129140 == 11'd2047 && - _theResult___fst_sfd__h129141 == 52'd0, - 1'd0, - _theResult___fst_exp__h128310 != 11'd2047 && - guard__h120084 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2571 = - ({ 3'd0, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d2569 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2898 = - { 3'd0, - _theResult___fst_exp__h87030 == 8'd0 && - (sfdin__h87024[56:34] == 23'd0 || guard__h78804 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h87657 == 8'd255 && - _theResult___fst_sfd__h87658 == 23'd0, - 1'd0, - _theResult___fst_exp__h87030 != 8'd255 && - guard__h78804 != 2'b0 } ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3086 = - ({ 6'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3479 = - ({ 6'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 } ^ - 12'h800) <= - (IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3478 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3674 = - { 3'd0, - _theResult___fst_exp__h118737 == 11'd0 && - guard__h110776 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h119493 == 11'd2047 && - _theResult___fst_sfd__h119494 == 52'd0, - 1'd0, - _theResult___fst_exp__h118737 != 11'd2047 && - guard__h110776 != 2'b0 } ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2249 = - ({ 3'd0, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2644 = - ({ 3'd0, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 } ^ - 9'h100) <= - (IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2643 ^ - 9'h100) ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881 = - { 3'd0, - _theResult___fst_exp__h77863 == 8'd0 && guard__h69815 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h78416 == 8'd255 && - _theResult___fst_sfd__h78417 == 23'd0, - 1'd0, - _theResult___fst_exp__h77863 != 8'd255 && - guard__h69815 != 2'b0 } ; - assign _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d3162 = - b__h15323 >> - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d3158 ; - assign _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_609__ETC___d2329 = - sfd__h53440 >> - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_609_ETC___d2325 ; - assign _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78 = - { 33'h1AAAAAAAA, - requestR[63:32] == 32'hFFFFFFFF && requestR[31], - (requestR[63:32] == 32'hFFFFFFFF) ? - requestR[30:0] : - 31'h7FC00000 } ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1851 = - 12'd3074 - - { 6'd0, - requestR[179] ? - 6'd0 : - (requestR[178] ? - 6'd1 : - (requestR[177] ? - 6'd2 : - (requestR[176] ? - 6'd3 : - (requestR[175] ? - 6'd4 : - (requestR[174] ? - 6'd5 : - (requestR[173] ? - 6'd6 : - (requestR[172] ? - 6'd7 : - (requestR[171] ? - 6'd8 : - (requestR[170] ? - 6'd9 : - (requestR[169] ? - 6'd10 : - (requestR[168] ? - 6'd11 : - (requestR[167] ? - 6'd12 : - (requestR[166] ? - 6'd13 : - (requestR[165] ? - 6'd14 : - (requestR[164] ? - 6'd15 : - (requestR[163] ? - 6'd16 : - (requestR[162] ? - 6'd17 : - (requestR[161] ? - 6'd18 : - (requestR[160] ? - 6'd19 : - (requestR[159] ? - 6'd20 : - (requestR[158] ? - 6'd21 : - (requestR[157] ? - 6'd22 : - (requestR[156] ? - 6'd23 : - (requestR[155] ? - 6'd24 : - (requestR[154] ? - 6'd25 : - (requestR[153] ? - 6'd26 : - (requestR[152] ? - 6'd27 : - (requestR[151] ? - 6'd28 : - (requestR[150] ? - 6'd29 : - (requestR[149] ? - 6'd30 : - (requestR[148] ? - 6'd31 : - (requestR[147] ? - 6'd32 : - (requestR[146] ? - 6'd33 : - (requestR[145] ? - 6'd34 : - (requestR[144] ? - 6'd35 : - (requestR[143] ? - 6'd36 : - (requestR[142] ? - 6'd37 : - (requestR[141] ? - 6'd38 : - (requestR[140] ? - 6'd39 : - (requestR[139] ? - 6'd40 : - (requestR[138] ? - 6'd41 : - (requestR[137] ? - 6'd42 : - (requestR[136] ? - 6'd43 : - (requestR[135] ? - 6'd44 : - (requestR[134] ? - 6'd45 : - (requestR[133] ? - 6'd46 : - (requestR[132] ? - 6'd47 : - (requestR[131] ? - 6'd48 : - (requestR[130] ? - 6'd49 : - (requestR[129] ? - 6'd50 : - (requestR[128] ? - 6'd51 : - 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 = - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1851 ^ - 12'h800) <= - 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 = - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1851 ^ - 12'h800) < - 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2884 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869[4] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881[4]) ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2909 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869[3] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881[3]) ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d2936 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2869[1] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2881[1]) ; - assign _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d3158 = - 12'd3074 - - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3155 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245 = - (12'd32 - - { 6'd0, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1242 }) - - 12'd1 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245 ^ - 12'h800) <= - 12'd3071 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245 ^ - 12'h800) < - 12'd974 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245 ^ - 12'h800) < - 12'd1026 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278 = - (9'd32 - - { 3'd0, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d275 }) - - 9'd1 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278 ^ - 9'h100) <= - 9'd383 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278 ^ - 9'h100) < - 9'd107 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278 ^ - 9'h100) < - 9'd130 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459 = - (12'd32 - - { 6'd0, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1456 }) - - 12'd1 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459 ^ - 12'h800) <= - 12'd3071 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459 ^ - 12'h800) < - 12'd974 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459 ^ - 12'h800) < - 12'd1026 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635 = - (9'd32 - - { 3'd0, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d632 }) - - 9'd1 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635 ^ - 9'h100) <= - 9'd383 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635 ^ - 9'h100) < - 9'd107 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635 ^ - 9'h100) < - 9'd130 ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3012 = - 12'd3970 - - { 7'd0, - sV1_sfd__h1205[22] ? - 5'd0 : - (sV1_sfd__h1205[21] ? - 5'd1 : - (sV1_sfd__h1205[20] ? - 5'd2 : - (sV1_sfd__h1205[19] ? - 5'd3 : - (sV1_sfd__h1205[18] ? - 5'd4 : - (sV1_sfd__h1205[17] ? - 5'd5 : - (sV1_sfd__h1205[16] ? - 5'd6 : - (sV1_sfd__h1205[15] ? - 5'd7 : - (sV1_sfd__h1205[14] ? - 5'd8 : - (sV1_sfd__h1205[13] ? - 5'd9 : - (sV1_sfd__h1205[12] ? - 5'd10 : - (sV1_sfd__h1205[11] ? - 5'd11 : - (sV1_sfd__h1205[10] ? - 5'd12 : - (sV1_sfd__h1205[9] ? - 5'd13 : - (sV1_sfd__h1205[8] ? - 5'd14 : - (sV1_sfd__h1205[7] ? - 5'd15 : - (sV1_sfd__h1205[6] ? - 5'd16 : - (sV1_sfd__h1205[5] ? - 5'd17 : - (sV1_sfd__h1205[4] ? - 5'd18 : - (sV1_sfd__h1205[3] ? - 5'd19 : - (sV1_sfd__h1205[2] ? - 5'd20 : - (sV1_sfd__h1205[1] ? - 5'd21 : - (sV1_sfd__h1205[0] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 = - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3012 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 = - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3012 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_609_ETC___d2325 = - 12'd3970 - - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2322 ; - assign _theResult_____2__h15258 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d862 ? - out1___1__h15750 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[56:24] ; - assign _theResult_____2__h47179 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1648 ? - out1___1__h47671 : - IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[85:53] ; - assign _theResult____h120074 = - ((_3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d3158 ^ - 12'h800) < - 12'd2105) ? - result__h120687 : - ((value__h15325 == 25'd0) ? b__h15323 : 57'd1) ; - assign _theResult____h61070 = - (value__h47246 == 54'd0) ? sfd__h53440 : 57'd1 ; - assign _theResult____h78794 = - ((_3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_609_ETC___d2325 ^ - 12'h800) < - 12'd2105) ? - result__h79407 : - _theResult____h61070 ; - assign _theResult___exp__h119392 = - sfd__h118755[53] ? - ((_theResult___fst_exp__h118737 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h137957) : - ((_theResult___fst_exp__h118737 == 11'd0 && - sfd__h118755[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h118737) ; - assign _theResult___exp__h129039 = - sfd__h128402[53] ? - ((_theResult___fst_exp__h128310 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h137987) : - ((_theResult___fst_exp__h128310 == 11'd0 && - sfd__h128402[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h128310) ; - assign _theResult___exp__h137821 = - sfd__h137160[53] ? - ((_theResult___fst_exp__h137141 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h138011) : - ((_theResult___fst_exp__h137141 == 11'd0 && - sfd__h137160[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h137141) ; - assign _theResult___exp__h14054 = - (sfd__h13658[24] || sfd__h13658[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h14606 = - sfd__h14197[24] ? - ((x__h14182[7:0] == 8'd254) ? - 8'd255 : - din_inc___2_exp__h14744) : - ((x__h14182[7:0] == 8'd0 && sfd__h14197[24:23] == 2'b01) ? - 8'd1 : - x__h14182[7:0]) ; - assign _theResult___exp__h36135 = - (sfd__h35536[53] || sfd__h35536[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h36891 = - sfd__h36279[53] ? - ((x__h36264[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h37034) : - ((x__h36264[10:0] == 11'd0 && sfd__h36279[53:52] == 2'b01) ? - 11'd1 : - x__h36264[10:0]) ; - assign _theResult___exp__h45776 = - (sfd__h45177[53] || sfd__h45177[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h46531 = - sfd__h45919[53] ? - ((x__h45904[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h46669) : - ((x__h45904[10:0] == 11'd0 && sfd__h45919[53:52] == 2'b01) ? - 11'd1 : - x__h45904[10:0]) ; - assign _theResult___exp__h69703 = - sfd__h69269[24] ? - ((_theResult___fst_exp__h69177 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h96354) : - ((_theResult___fst_exp__h69177 == 8'd0 && - sfd__h69269[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h69177) ; - assign _theResult___exp__h78315 = - sfd__h77881[24] ? - ((_theResult___fst_exp__h77863 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h96378) : - ((_theResult___fst_exp__h77863 == 8'd0 && - sfd__h77881[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h77863) ; - assign _theResult___exp__h7935 = - (sfd__h7536[24] || sfd__h7536[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h8488 = - sfd__h8079[24] ? - ((x__h8064[7:0] == 8'd254) ? 8'd255 : din_inc___2_exp__h8631) : - ((x__h8064[7:0] == 8'd0 && sfd__h8079[24:23] == 2'b01) ? - 8'd1 : - x__h8064[7:0]) ; - assign _theResult___exp__h87556 = - sfd__h87122[24] ? - ((_theResult___fst_exp__h87030 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h96408) : - ((_theResult___fst_exp__h87030 == 8'd0 && - sfd__h87122[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h87030) ; - assign _theResult___exp__h96222 = - sfd__h95764[24] ? - ((_theResult___fst_exp__h95745 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h96432) : - ((_theResult___fst_exp__h95745 == 8'd0 && - sfd__h95764[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h95745) ; - assign _theResult___fst_exp__h103664 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 11'd2047 : - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 ; - assign _theResult___fst_exp__h118728 = - 11'd897 - - { 5'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 } ; - assign _theResult___fst_exp__h118734 = - (sV1_exp__h1204 == 8'd0 && !sV1_sfd__h1205[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057 || - !_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3086) ? - 11'd0 : - _theResult___fst_exp__h118728 ; - assign _theResult___fst_exp__h118737 = - (sV1_exp__h1204 == 8'd0) ? - _theResult___fst_exp__h118734 : - 11'd897 ; - assign _theResult___fst_exp__h119490 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q103 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 ; - assign _theResult___fst_exp__h119493 = - (_theResult___fst_exp__h118737 == 11'd2047) ? - _theResult___fst_exp__h118737 : - _theResult___fst_exp__h119490 ; - assign _theResult___fst_exp__h128310 = - _theResult____h120074[56] ? - 11'd2 : - _theResult___fst_exp__h128384 ; - assign _theResult___fst_exp__h128375 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d3404 } ; - assign _theResult___fst_exp__h128381 = - (!_theResult____h120074[56] && !_theResult____h120074[55] && - !_theResult____h120074[54] && - !_theResult____h120074[53] && - !_theResult____h120074[52] && - !_theResult____h120074[51] && - !_theResult____h120074[50] && - !_theResult____h120074[49] && - !_theResult____h120074[48] && - !_theResult____h120074[47] && - !_theResult____h120074[46] && - !_theResult____h120074[45] && - !_theResult____h120074[44] && - !_theResult____h120074[43] && - !_theResult____h120074[42] && - !_theResult____h120074[41] && - !_theResult____h120074[40] && - !_theResult____h120074[39] && - !_theResult____h120074[38] && - !_theResult____h120074[37] && - !_theResult____h120074[36] && - !_theResult____h120074[35] && - !_theResult____h120074[34] && - !_theResult____h120074[33] && - !_theResult____h120074[32] && - !_theResult____h120074[31] && - !_theResult____h120074[30] && - !_theResult____h120074[29] && - !_theResult____h120074[28] && - !_theResult____h120074[27] && - !_theResult____h120074[26] && - !_theResult____h120074[25] && - !_theResult____h120074[24] && - !_theResult____h120074[23] && - !_theResult____h120074[22] && - !_theResult____h120074[21] && - !_theResult____h120074[20] && - !_theResult____h120074[19] && - !_theResult____h120074[18] && - !_theResult____h120074[17] && - !_theResult____h120074[16] && - !_theResult____h120074[15] && - !_theResult____h120074[14] && - !_theResult____h120074[13] && - !_theResult____h120074[12] && - !_theResult____h120074[11] && - !_theResult____h120074[10] && - !_theResult____h120074[9] && - !_theResult____h120074[8] && - !_theResult____h120074[7] && - !_theResult____h120074[6] && - !_theResult____h120074[5] && - !_theResult____h120074[4] && - !_theResult____h120074[3] && - !_theResult____h120074[2] && - !_theResult____h120074[1] && - !_theResult____h120074[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d3406) ? - 11'd0 : - _theResult___fst_exp__h128375 ; - assign _theResult___fst_exp__h128384 = - (!_theResult____h120074[56] && _theResult____h120074[55]) ? - 11'd1 : - _theResult___fst_exp__h128381 ; - assign _theResult___fst_exp__h129137 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q105 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 ; - assign _theResult___fst_exp__h129140 = - (_theResult___fst_exp__h128310 == 11'd2047) ? - _theResult___fst_exp__h128310 : - _theResult___fst_exp__h129137 ; - assign _theResult___fst_exp__h137093 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96[10:0] == - 11'd0) ? - 11'd1 : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96[10:0] ; - assign _theResult___fst_exp__h137132 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q96[10:0] - - { 5'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 } ; - assign _theResult___fst_exp__h137138 = - (sV1_exp__h1204 == 8'd0 && !sV1_sfd__h1205[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057 || - !_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d3479) ? - 11'd0 : - _theResult___fst_exp__h137132 ; - assign _theResult___fst_exp__h137141 = - (sV1_exp__h1204 == 8'd0) ? - _theResult___fst_exp__h137138 : - _theResult___fst_exp__h137093 ; - assign _theResult___fst_exp__h137919 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q107 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 ; - assign _theResult___fst_exp__h137922 = - (_theResult___fst_exp__h137141 == 11'd2047) ? - _theResult___fst_exp__h137141 : - _theResult___fst_exp__h137919 ; - assign _theResult___fst_exp__h137931 = - (sV1_exp__h1204 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 ? - _theResult___snd_fst_exp__h119496 : - _theResult___fst_exp__h103664) : - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 ? - _theResult___snd_fst_exp__h137925 : - _theResult___fst_exp__h103664) ; - assign _theResult___fst_exp__h137934 = - (sV1_exp__h1204 == 8'd0 && sV1_sfd__h1205 == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h137931 ; - assign _theResult___fst_exp__h14150 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3641_0b0_0_0b1_0_0b10_out_exp4057_0b_ETC__q22 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard3641_ETC__q24 ; - assign _theResult___fst_exp__h14702 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_x4182_ETC__q26 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716 ; - assign _theResult___fst_exp__h14705 = - (x__h14182[7:0] == 8'd255) ? - x__h14182[7:0] : - _theResult___fst_exp__h14702 ; - assign _theResult___fst_exp__h36232 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5519_0b0_0_0b1_0_0b10_out_exp6138_0b_ETC__q44 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325 ; - assign _theResult___fst_exp__h36988 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_x626_ETC__q40 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 ; - assign _theResult___fst_exp__h36991 = - (x__h36264[10:0] == 11'd2047) ? - x__h36264[10:0] : - _theResult___fst_exp__h36988 ; - assign _theResult___fst_exp__h45872 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5160_0b0_0_0b1_0_0b10_out_exp5779_0b_ETC__q49 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5160_ETC__q51 ; - assign _theResult___fst_exp__h46627 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_x590_ETC__q53 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540 ; - assign _theResult___fst_exp__h46630 = - (x__h45904[10:0] == 11'd2047) ? - x__h45904[10:0] : - _theResult___fst_exp__h46627 ; - assign _theResult___fst_exp__h61052 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 8'd255 : - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 ; - assign _theResult___fst_exp__h69177 = - _theResult____h61070[56] ? 8'd2 : _theResult___fst_exp__h69251 ; - assign _theResult___fst_exp__h69242 = - 8'd0 - - { 2'd0, - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d2085 } ; - assign _theResult___fst_exp__h69248 = - (!_theResult____h61070[56] && !_theResult____h61070[55] && - !_theResult____h61070[54] && - !_theResult____h61070[53] && - !_theResult____h61070[52] && - !_theResult____h61070[51] && - !_theResult____h61070[50] && - !_theResult____h61070[49] && - !_theResult____h61070[48] && - !_theResult____h61070[47] && - !_theResult____h61070[46] && - !_theResult____h61070[45] && - !_theResult____h61070[44] && - !_theResult____h61070[43] && - !_theResult____h61070[42] && - !_theResult____h61070[41] && - !_theResult____h61070[40] && - !_theResult____h61070[39] && - !_theResult____h61070[38] && - !_theResult____h61070[37] && - !_theResult____h61070[36] && - !_theResult____h61070[35] && - !_theResult____h61070[34] && - !_theResult____h61070[33] && - !_theResult____h61070[32] && - !_theResult____h61070[31] && - !_theResult____h61070[30] && - !_theResult____h61070[29] && - !_theResult____h61070[28] && - !_theResult____h61070[27] && - !_theResult____h61070[26] && - !_theResult____h61070[25] && - !_theResult____h61070[24] && - !_theResult____h61070[23] && - !_theResult____h61070[22] && - !_theResult____h61070[21] && - !_theResult____h61070[20] && - !_theResult____h61070[19] && - !_theResult____h61070[18] && - !_theResult____h61070[17] && - !_theResult____h61070[16] && - !_theResult____h61070[15] && - !_theResult____h61070[14] && - !_theResult____h61070[13] && - !_theResult____h61070[12] && - !_theResult____h61070[11] && - !_theResult____h61070[10] && - !_theResult____h61070[9] && - !_theResult____h61070[8] && - !_theResult____h61070[7] && - !_theResult____h61070[6] && - !_theResult____h61070[5] && - !_theResult____h61070[4] && - !_theResult____h61070[3] && - !_theResult____h61070[2] && - !_theResult____h61070[1] && - !_theResult____h61070[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d2087) ? - 8'd0 : - _theResult___fst_exp__h69242 ; - assign _theResult___fst_exp__h69251 = - (!_theResult____h61070[56] && _theResult____h61070[55]) ? - 8'd1 : - _theResult___fst_exp__h69248 ; - assign _theResult___fst_exp__h69801 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q71 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 ; - assign _theResult___fst_exp__h69804 = - (_theResult___fst_exp__h69177 == 8'd255) ? - _theResult___fst_exp__h69177 : - _theResult___fst_exp__h69801 ; - assign _theResult___fst_exp__h77854 = - 8'd129 - - { 2'd0, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 } ; - assign _theResult___fst_exp__h77860 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192 || - !_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2249) ? - 8'd0 : - _theResult___fst_exp__h77854 ; - assign _theResult___fst_exp__h77863 = - (requestR[190:180] == 11'd0) ? - _theResult___fst_exp__h77860 : - 8'd129 ; - assign _theResult___fst_exp__h78413 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q73 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 ; - assign _theResult___fst_exp__h78416 = - (_theResult___fst_exp__h77863 == 8'd255) ? - _theResult___fst_exp__h77863 : - _theResult___fst_exp__h78413 ; - assign _theResult___fst_exp__h8032 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard519_0b0_0_0b1_0_0b10_out_exp938_0b11_ETC__q13 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370 ; - assign _theResult___fst_exp__h8585 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_x064_BI_ETC__q15 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 ; - assign _theResult___fst_exp__h8588 = - (x__h8064[7:0] == 8'd255) ? - x__h8064[7:0] : - _theResult___fst_exp__h8585 ; - assign _theResult___fst_exp__h87030 = - _theResult____h78794[56] ? 8'd2 : _theResult___fst_exp__h87104 ; - assign _theResult___fst_exp__h87095 = - 8'd0 - - { 2'd0, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d2569 } ; - assign _theResult___fst_exp__h87101 = - (!_theResult____h78794[56] && !_theResult____h78794[55] && - !_theResult____h78794[54] && - !_theResult____h78794[53] && - !_theResult____h78794[52] && - !_theResult____h78794[51] && - !_theResult____h78794[50] && - !_theResult____h78794[49] && - !_theResult____h78794[48] && - !_theResult____h78794[47] && - !_theResult____h78794[46] && - !_theResult____h78794[45] && - !_theResult____h78794[44] && - !_theResult____h78794[43] && - !_theResult____h78794[42] && - !_theResult____h78794[41] && - !_theResult____h78794[40] && - !_theResult____h78794[39] && - !_theResult____h78794[38] && - !_theResult____h78794[37] && - !_theResult____h78794[36] && - !_theResult____h78794[35] && - !_theResult____h78794[34] && - !_theResult____h78794[33] && - !_theResult____h78794[32] && - !_theResult____h78794[31] && - !_theResult____h78794[30] && - !_theResult____h78794[29] && - !_theResult____h78794[28] && - !_theResult____h78794[27] && - !_theResult____h78794[26] && - !_theResult____h78794[25] && - !_theResult____h78794[24] && - !_theResult____h78794[23] && - !_theResult____h78794[22] && - !_theResult____h78794[21] && - !_theResult____h78794[20] && - !_theResult____h78794[19] && - !_theResult____h78794[18] && - !_theResult____h78794[17] && - !_theResult____h78794[16] && - !_theResult____h78794[15] && - !_theResult____h78794[14] && - !_theResult____h78794[13] && - !_theResult____h78794[12] && - !_theResult____h78794[11] && - !_theResult____h78794[10] && - !_theResult____h78794[9] && - !_theResult____h78794[8] && - !_theResult____h78794[7] && - !_theResult____h78794[6] && - !_theResult____h78794[5] && - !_theResult____h78794[4] && - !_theResult____h78794[3] && - !_theResult____h78794[2] && - !_theResult____h78794[1] && - !_theResult____h78794[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d2571) ? - 8'd0 : - _theResult___fst_exp__h87095 ; - assign _theResult___fst_exp__h87104 = - (!_theResult____h78794[56] && _theResult____h78794[55]) ? - 8'd1 : - _theResult___fst_exp__h87101 ; - assign _theResult___fst_exp__h87654 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q75 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 ; - assign _theResult___fst_exp__h87657 = - (_theResult___fst_exp__h87030 == 8'd255) ? - _theResult___fst_exp__h87030 : - _theResult___fst_exp__h87654 ; - assign _theResult___fst_exp__h95697 = - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64[7:0] == - 8'd0) ? - 8'd1 : - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64[7:0] ; - assign _theResult___fst_exp__h95736 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC__q64[7:0] - - { 2'd0, - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 } ; - assign _theResult___fst_exp__h95742 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192 || - !_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609_EQ__ETC___d2644) ? - 8'd0 : - _theResult___fst_exp__h95736 ; - assign _theResult___fst_exp__h95745 = - (requestR[190:180] == 11'd0) ? - _theResult___fst_exp__h95742 : - _theResult___fst_exp__h95697 ; - assign _theResult___fst_exp__h96320 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q77 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 ; - assign _theResult___fst_exp__h96323 = - (_theResult___fst_exp__h95745 == 8'd255) ? - _theResult___fst_exp__h95745 : - _theResult___fst_exp__h96320 ; - assign _theResult___fst_exp__h96332 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 ? - _theResult___snd_fst_exp__h78419 : - _theResult___fst_exp__h61052) : - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 ? - _theResult___snd_fst_exp__h96326 : - _theResult___fst_exp__h61052) ; - assign _theResult___fst_exp__h96335 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 8'd0 : - _theResult___fst_exp__h96332 ; - assign _theResult___fst_sfd__h103665 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 52'd0 : - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 ; - assign _theResult___fst_sfd__h119491 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q115 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 ; - assign _theResult___fst_sfd__h119494 = - (_theResult___fst_exp__h118737 == 11'd2047) ? - _theResult___snd__h118688[56:5] : - _theResult___fst_sfd__h119491 ; - assign _theResult___fst_sfd__h129138 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q117 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 ; - assign _theResult___fst_sfd__h129141 = - (_theResult___fst_exp__h128310 == 11'd2047) ? - sfdin__h128304[56:5] : - _theResult___fst_sfd__h129138 ; - assign _theResult___fst_sfd__h137920 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q119 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 ; - assign _theResult___fst_sfd__h137923 = - (_theResult___fst_exp__h137141 == 11'd2047) ? - _theResult___snd__h137087[56:5] : - _theResult___fst_sfd__h137920 ; - assign _theResult___fst_sfd__h137932 = - (sV1_exp__h1204 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3013 ? - _theResult___snd_fst_sfd__h119497 : - _theResult___fst_sfd__h103665) : - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3156 ? - _theResult___snd_fst_sfd__h137926 : - _theResult___fst_sfd__h103665) ; - assign _theResult___fst_sfd__h137938 = - ((sV1_exp__h1204 == 8'd255 || sV1_exp__h1204 == 8'd0) && - sV1_sfd__h1205 == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h137932 ; - assign _theResult___fst_sfd__h14151 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q30 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739 ; - assign _theResult___fst_sfd__h14703 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q28 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754 ; - assign _theResult___fst_sfd__h14706 = - (x__h14182[7:0] == 8'd255) ? - sfd___3__h13631[30:8] : - _theResult___fst_sfd__h14703 ; - assign _theResult___fst_sfd__h36233 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q46 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 ; - assign _theResult___fst_sfd__h36989 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q42 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 ; - assign _theResult___fst_sfd__h36992 = - (x__h36264[10:0] == 11'd2047) ? - sfd___3__h35509[53:2] : - _theResult___fst_sfd__h36989 ; - assign _theResult___fst_sfd__h45873 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q57 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562 ; - assign _theResult___fst_sfd__h46628 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q55 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577 ; - assign _theResult___fst_sfd__h46631 = - (x__h45904[10:0] == 11'd2047) ? - sfd___3__h45150[53:2] : - _theResult___fst_sfd__h46628 ; - assign _theResult___fst_sfd__h49736 = { 1'd1, requestR[178:128] } ; - assign _theResult___fst_sfd__h61053 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 23'd0 : - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 ; - assign _theResult___fst_sfd__h69802 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q79 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 ; - assign _theResult___fst_sfd__h69805 = - (_theResult___fst_exp__h69177 == 8'd255) ? - sfdin__h69171[56:34] : - _theResult___fst_sfd__h69802 ; - assign _theResult___fst_sfd__h78414 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q81 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 ; - assign _theResult___fst_sfd__h78417 = - (_theResult___fst_exp__h77863 == 8'd255) ? - _theResult___snd__h77814[56:34] : - _theResult___fst_sfd__h78414 ; - assign _theResult___fst_sfd__h8033 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q17 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 ; - assign _theResult___fst_sfd__h8586 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q19 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 ; - assign _theResult___fst_sfd__h8589 = - (x__h8064[7:0] == 8'd255) ? - sfd___3__h7509[30:8] : - _theResult___fst_sfd__h8586 ; - assign _theResult___fst_sfd__h87655 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q83 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 ; - assign _theResult___fst_sfd__h87658 = - (_theResult___fst_exp__h87030 == 8'd255) ? - sfdin__h87024[56:34] : - _theResult___fst_sfd__h87655 ; - assign _theResult___fst_sfd__h96321 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q85 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 ; - assign _theResult___fst_sfd__h96324 = - (_theResult___fst_exp__h95745 == 8'd255) ? - _theResult___snd__h95691[56:34] : - _theResult___fst_sfd__h96321 ; - assign _theResult___fst_sfd__h96333 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1852 ? - _theResult___snd_fst_sfd__h78420 : - _theResult___fst_sfd__h61053) : - (SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2323 ? - _theResult___snd_fst_sfd__h96327 : - _theResult___fst_sfd__h61053) ; - assign _theResult___fst_sfd__h96339 = - ((requestR[190:180] == 11'd2047 || requestR[190:180] == 11'd0) && - requestR[179:128] == 52'd0) ? - 23'd0 : - _theResult___fst_sfd__h96333 ; - assign _theResult___fst_sfd__h98183 = { 1'd1, sV1_sfd__h1205[21:0] } ; - assign _theResult___sfd__h119393 = - sfd__h118755[53] ? - ((_theResult___fst_exp__h118737 == 11'd2046) ? - 52'd0 : - sfd__h118755[52:1]) : - sfd__h118755[51:0] ; - assign _theResult___sfd__h129040 = - sfd__h128402[53] ? - ((_theResult___fst_exp__h128310 == 11'd2046) ? - 52'd0 : - sfd__h128402[52:1]) : - sfd__h128402[51:0] ; - assign _theResult___sfd__h137822 = - sfd__h137160[53] ? - ((_theResult___fst_exp__h137141 == 11'd2046) ? - 52'd0 : - sfd__h137160[52:1]) : - sfd__h137160[51:0] ; - assign _theResult___sfd__h14055 = - sfd__h13658[24] ? sfd__h13658[23:1] : sfd__h13658[22:0] ; - assign _theResult___sfd__h14607 = - sfd__h14197[24] ? - ((x__h14182[7:0] == 8'd254) ? 23'd0 : sfd__h14197[23:1]) : - sfd__h14197[22:0] ; - assign _theResult___sfd__h36136 = - sfd__h35536[53] ? sfd__h35536[52:1] : sfd__h35536[51:0] ; - assign _theResult___sfd__h36892 = - sfd__h36279[53] ? - ((x__h36264[10:0] == 11'd2046) ? 52'd0 : sfd__h36279[52:1]) : - sfd__h36279[51:0] ; - assign _theResult___sfd__h45777 = - sfd__h45177[53] ? sfd__h45177[52:1] : sfd__h45177[51:0] ; - assign _theResult___sfd__h46532 = - sfd__h45919[53] ? - ((x__h45904[10:0] == 11'd2046) ? 52'd0 : sfd__h45919[52:1]) : - sfd__h45919[51:0] ; - assign _theResult___sfd__h69704 = - sfd__h69269[24] ? - ((_theResult___fst_exp__h69177 == 8'd254) ? - 23'd0 : - sfd__h69269[23:1]) : - sfd__h69269[22:0] ; - assign _theResult___sfd__h78316 = - sfd__h77881[24] ? - ((_theResult___fst_exp__h77863 == 8'd254) ? - 23'd0 : - sfd__h77881[23:1]) : - sfd__h77881[22:0] ; - assign _theResult___sfd__h7936 = - sfd__h7536[24] ? sfd__h7536[23:1] : sfd__h7536[22:0] ; - assign _theResult___sfd__h8489 = - sfd__h8079[24] ? - ((x__h8064[7:0] == 8'd254) ? 23'd0 : sfd__h8079[23:1]) : - sfd__h8079[22:0] ; - assign _theResult___sfd__h87557 = - sfd__h87122[24] ? - ((_theResult___fst_exp__h87030 == 8'd254) ? - 23'd0 : - sfd__h87122[23:1]) : - sfd__h87122[22:0] ; - assign _theResult___sfd__h96223 = - sfd__h95764[24] ? - ((_theResult___fst_exp__h95745 == 8'd254) ? - 23'd0 : - sfd__h95764[23:1]) : - sfd__h95764[22:0] ; - assign _theResult___snd__h118688 = - (sV1_exp__h1204 == 8'd0) ? - _theResult___snd__h118697 : - _theResult___snd__h118690 ; - assign _theResult___snd__h118690 = { sV1_sfd__h1205, 34'd0 } ; - assign _theResult___snd__h118697 = - (sV1_exp__h1204 == 8'd0 && !sV1_sfd__h1205[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057) ? - b__h15323 : - _theResult___snd__h118703 ; - assign _theResult___snd__h118703 = - { IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q94[54:0], - 2'd0 } ; - assign _theResult___snd__h118726 = - b__h15323 << - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3084 ; - assign _theResult___snd__h128321 = { _theResult____h120074[55:0], 1'd0 } ; - assign _theResult___snd__h128332 = - (!_theResult____h120074[56] && _theResult____h120074[55]) ? - _theResult___snd__h128334 : - _theResult___snd__h128344 ; - assign _theResult___snd__h128334 = { _theResult____h120074[54:0], 2'd0 } ; - assign _theResult___snd__h128344 = - (!_theResult____h120074[56] && !_theResult____h120074[55] && - !_theResult____h120074[54] && - !_theResult____h120074[53] && - !_theResult____h120074[52] && - !_theResult____h120074[51] && - !_theResult____h120074[50] && - !_theResult____h120074[49] && - !_theResult____h120074[48] && - !_theResult____h120074[47] && - !_theResult____h120074[46] && - !_theResult____h120074[45] && - !_theResult____h120074[44] && - !_theResult____h120074[43] && - !_theResult____h120074[42] && - !_theResult____h120074[41] && - !_theResult____h120074[40] && - !_theResult____h120074[39] && - !_theResult____h120074[38] && - !_theResult____h120074[37] && - !_theResult____h120074[36] && - !_theResult____h120074[35] && - !_theResult____h120074[34] && - !_theResult____h120074[33] && - !_theResult____h120074[32] && - !_theResult____h120074[31] && - !_theResult____h120074[30] && - !_theResult____h120074[29] && - !_theResult____h120074[28] && - !_theResult____h120074[27] && - !_theResult____h120074[26] && - !_theResult____h120074[25] && - !_theResult____h120074[24] && - !_theResult____h120074[23] && - !_theResult____h120074[22] && - !_theResult____h120074[21] && - !_theResult____h120074[20] && - !_theResult____h120074[19] && - !_theResult____h120074[18] && - !_theResult____h120074[17] && - !_theResult____h120074[16] && - !_theResult____h120074[15] && - !_theResult____h120074[14] && - !_theResult____h120074[13] && - !_theResult____h120074[12] && - !_theResult____h120074[11] && - !_theResult____h120074[10] && - !_theResult____h120074[9] && - !_theResult____h120074[8] && - !_theResult____h120074[7] && - !_theResult____h120074[6] && - !_theResult____h120074[5] && - !_theResult____h120074[4] && - !_theResult____h120074[3] && - !_theResult____h120074[2] && - !_theResult____h120074[1] && - !_theResult____h120074[0]) ? - _theResult____h120074 : - _theResult___snd__h128350 ; - assign _theResult___snd__h128350 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97[54:0], - 2'd0 } ; - assign _theResult___snd__h128373 = - _theResult____h120074 << - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d3404 ; - assign _theResult___snd__h137087 = - (sV1_exp__h1204 == 8'd0) ? - _theResult___snd__h137101 : - _theResult___snd__h118690 ; - assign _theResult___snd__h137101 = - (sV1_exp__h1204 == 8'd0 && !sV1_sfd__h1205[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3057) ? - b__h15323 : - _theResult___snd__h137107 ; - assign _theResult___snd__h137107 = - { IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q100[54:0], - 2'd0 } ; - assign _theResult___snd__h137125 = - b__h15323 << - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d3478 ; - assign _theResult___snd__h69188 = { _theResult____h61070[55:0], 1'd0 } ; - assign _theResult___snd__h69199 = - (!_theResult____h61070[56] && _theResult____h61070[55]) ? - _theResult___snd__h69201 : - _theResult___snd__h69211 ; - assign _theResult___snd__h69201 = { _theResult____h61070[54:0], 2'd0 } ; - assign _theResult___snd__h69211 = - (!_theResult____h61070[56] && !_theResult____h61070[55] && - !_theResult____h61070[54] && - !_theResult____h61070[53] && - !_theResult____h61070[52] && - !_theResult____h61070[51] && - !_theResult____h61070[50] && - !_theResult____h61070[49] && - !_theResult____h61070[48] && - !_theResult____h61070[47] && - !_theResult____h61070[46] && - !_theResult____h61070[45] && - !_theResult____h61070[44] && - !_theResult____h61070[43] && - !_theResult____h61070[42] && - !_theResult____h61070[41] && - !_theResult____h61070[40] && - !_theResult____h61070[39] && - !_theResult____h61070[38] && - !_theResult____h61070[37] && - !_theResult____h61070[36] && - !_theResult____h61070[35] && - !_theResult____h61070[34] && - !_theResult____h61070[33] && - !_theResult____h61070[32] && - !_theResult____h61070[31] && - !_theResult____h61070[30] && - !_theResult____h61070[29] && - !_theResult____h61070[28] && - !_theResult____h61070[27] && - !_theResult____h61070[26] && - !_theResult____h61070[25] && - !_theResult____h61070[24] && - !_theResult____h61070[23] && - !_theResult____h61070[22] && - !_theResult____h61070[21] && - !_theResult____h61070[20] && - !_theResult____h61070[19] && - !_theResult____h61070[18] && - !_theResult____h61070[17] && - !_theResult____h61070[16] && - !_theResult____h61070[15] && - !_theResult____h61070[14] && - !_theResult____h61070[13] && - !_theResult____h61070[12] && - !_theResult____h61070[11] && - !_theResult____h61070[10] && - !_theResult____h61070[9] && - !_theResult____h61070[8] && - !_theResult____h61070[7] && - !_theResult____h61070[6] && - !_theResult____h61070[5] && - !_theResult____h61070[4] && - !_theResult____h61070[3] && - !_theResult____h61070[2] && - !_theResult____h61070[1] && - !_theResult____h61070[0]) ? - _theResult____h61070 : - _theResult___snd__h69217 ; - assign _theResult___snd__h69217 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q60[54:0], - 2'd0 } ; - assign _theResult___snd__h69240 = - _theResult____h61070 << - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d2085 ; - assign _theResult___snd__h77814 = - (requestR[190:180] == 11'd0) ? - _theResult___snd__h77823 : - _theResult___snd__h77816 ; - assign _theResult___snd__h77816 = { requestR[179:128], 5'd0 } ; - assign _theResult___snd__h77823 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192) ? - sfd__h53440 : - _theResult___snd__h77829 ; - assign _theResult___snd__h77829 = - { IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q62[54:0], - 2'd0 } ; - assign _theResult___snd__h77852 = - sfd__h53440 << - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2247 ; - assign _theResult___snd__h87041 = { _theResult____h78794[55:0], 1'd0 } ; - assign _theResult___snd__h87052 = - (!_theResult____h78794[56] && _theResult____h78794[55]) ? - _theResult___snd__h87054 : - _theResult___snd__h87064 ; - assign _theResult___snd__h87054 = { _theResult____h78794[54:0], 2'd0 } ; - assign _theResult___snd__h87064 = - (!_theResult____h78794[56] && !_theResult____h78794[55] && - !_theResult____h78794[54] && - !_theResult____h78794[53] && - !_theResult____h78794[52] && - !_theResult____h78794[51] && - !_theResult____h78794[50] && - !_theResult____h78794[49] && - !_theResult____h78794[48] && - !_theResult____h78794[47] && - !_theResult____h78794[46] && - !_theResult____h78794[45] && - !_theResult____h78794[44] && - !_theResult____h78794[43] && - !_theResult____h78794[42] && - !_theResult____h78794[41] && - !_theResult____h78794[40] && - !_theResult____h78794[39] && - !_theResult____h78794[38] && - !_theResult____h78794[37] && - !_theResult____h78794[36] && - !_theResult____h78794[35] && - !_theResult____h78794[34] && - !_theResult____h78794[33] && - !_theResult____h78794[32] && - !_theResult____h78794[31] && - !_theResult____h78794[30] && - !_theResult____h78794[29] && - !_theResult____h78794[28] && - !_theResult____h78794[27] && - !_theResult____h78794[26] && - !_theResult____h78794[25] && - !_theResult____h78794[24] && - !_theResult____h78794[23] && - !_theResult____h78794[22] && - !_theResult____h78794[21] && - !_theResult____h78794[20] && - !_theResult____h78794[19] && - !_theResult____h78794[18] && - !_theResult____h78794[17] && - !_theResult____h78794[16] && - !_theResult____h78794[15] && - !_theResult____h78794[14] && - !_theResult____h78794[13] && - !_theResult____h78794[12] && - !_theResult____h78794[11] && - !_theResult____h78794[10] && - !_theResult____h78794[9] && - !_theResult____h78794[8] && - !_theResult____h78794[7] && - !_theResult____h78794[6] && - !_theResult____h78794[5] && - !_theResult____h78794[4] && - !_theResult____h78794[3] && - !_theResult____h78794[2] && - !_theResult____h78794[1] && - !_theResult____h78794[0]) ? - _theResult____h78794 : - _theResult___snd__h87070 ; - assign _theResult___snd__h87070 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q65[54:0], - 2'd0 } ; - assign _theResult___snd__h87093 = - _theResult____h78794 << - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d2569 ; - assign _theResult___snd__h95691 = - (requestR[190:180] == 11'd0) ? - _theResult___snd__h95705 : - _theResult___snd__h77816 ; - assign _theResult___snd__h95705 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_778_153_AND_NOT_request_ETC___d2192) ? - sfd__h53440 : - _theResult___snd__h95711 ; - assign _theResult___snd__h95711 = - { IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_609__ETC__q68[54:0], - 2'd0 } ; - assign _theResult___snd__h95729 = - sfd__h53440 << - IF_SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1_ETC___d2643 ; - assign _theResult___snd_fst_exp__h119496 = - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 ? - 11'd0 : - _theResult___fst_exp__h119493 ; - assign _theResult___snd_fst_exp__h137925 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - _theResult___fst_exp__h129140 : - _theResult___fst_exp__h137922 ; - assign _theResult___snd_fst_exp__h14708 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638 ? - _theResult___fst_exp__h14150 : - _theResult___fst_exp__h14705 ; - assign _theResult___snd_fst_exp__h14711 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637 ? - 8'd0 : - _theResult___snd_fst_exp__h14708 ; - assign _theResult___snd_fst_exp__h14714 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 ? - _theResult___snd_fst_exp__h14711 : - 8'd255 ; - assign _theResult___snd_fst_exp__h36994 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 ? - _theResult___fst_exp__h36232 : - _theResult___fst_exp__h36991 ; - assign _theResult___snd_fst_exp__h36997 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248 ? - 11'd0 : - _theResult___snd_fst_exp__h36994 ; - assign _theResult___snd_fst_exp__h37000 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 ? - _theResult___snd_fst_exp__h36997 : - 11'd2047 ; - assign _theResult___snd_fst_exp__h46633 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462 ? - _theResult___fst_exp__h45872 : - _theResult___fst_exp__h46630 ; - assign _theResult___snd_fst_exp__h46636 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461 ? - 11'd0 : - _theResult___snd_fst_exp__h46633 ; - assign _theResult___snd_fst_exp__h46639 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 ? - _theResult___snd_fst_exp__h46636 : - 11'd2047 ; - assign _theResult___snd_fst_exp__h78419 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _theResult___fst_exp__h69804 : - _theResult___fst_exp__h78416 ; - assign _theResult___snd_fst_exp__h8591 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 ? - _theResult___fst_exp__h8032 : - _theResult___fst_exp__h8588 ; - assign _theResult___snd_fst_exp__h8594 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d281 ? - 8'd0 : - _theResult___snd_fst_exp__h8591 ; - assign _theResult___snd_fst_exp__h8597 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d279 ? - _theResult___snd_fst_exp__h8594 : - 8'd255 ; - assign _theResult___snd_fst_exp__h96326 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - _theResult___fst_exp__h87657 : - _theResult___fst_exp__h96323 ; - assign _theResult___snd_fst_sfd__h119497 = - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d3014 ? - 52'd0 : - _theResult___fst_sfd__h119494 ; - assign _theResult___snd_fst_sfd__h137926 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d3157 ? - _theResult___fst_sfd__h129141 : - _theResult___fst_sfd__h137923 ; - assign _theResult___snd_fst_sfd__h14709 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d638 ? - _theResult___fst_sfd__h14151 : - _theResult___fst_sfd__h14706 ; - assign _theResult___snd_fst_sfd__h36995 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 ? - _theResult___fst_sfd__h36233 : - _theResult___fst_sfd__h36992 ; - assign _theResult___snd_fst_sfd__h46634 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462 ? - _theResult___fst_sfd__h45873 : - _theResult___fst_sfd__h46631 ; - assign _theResult___snd_fst_sfd__h53394 = - (value__h49279[51:29] == 23'd0) ? - 23'd2097152 : - value__h49279[51:29] ; - assign _theResult___snd_fst_sfd__h78420 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_778__ETC___d1853 ? - _theResult___fst_sfd__h69805 : - _theResult___fst_sfd__h78417 ; - assign _theResult___snd_fst_sfd__h8592 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d284 ? - _theResult___fst_sfd__h8033 : - _theResult___fst_sfd__h8589 ; - assign _theResult___snd_fst_sfd__h96327 = - SEXT_requestR_3_BITS_190_TO_180_609_MINUS_1023_ETC___d2324 ? - _theResult___fst_sfd__h87658 : - _theResult___fst_sfd__h96324 ; - assign _theResult___snd_fst_sfd__h99811 = - (value__h97928 == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h97925 ; - assign b__h15323 = { value__h15325, 32'd0 } ; - assign b__h47244 = { value__h47246, 32'd0 } ; - assign din_inc___2_exp__h137957 = _theResult___fst_exp__h118737 + 11'd1 ; - assign din_inc___2_exp__h137987 = _theResult___fst_exp__h128310 + 11'd1 ; - assign din_inc___2_exp__h138011 = _theResult___fst_exp__h137141 + 11'd1 ; - assign din_inc___2_exp__h14744 = x__h14182[7:0] + 8'd1 ; - assign din_inc___2_exp__h37034 = x__h36264[10:0] + 11'd1 ; - assign din_inc___2_exp__h46669 = x__h45904[10:0] + 11'd1 ; - assign din_inc___2_exp__h8631 = x__h8064[7:0] + 8'd1 ; - assign din_inc___2_exp__h96354 = _theResult___fst_exp__h69177 + 8'd1 ; - assign din_inc___2_exp__h96378 = _theResult___fst_exp__h77863 + 8'd1 ; - assign din_inc___2_exp__h96408 = _theResult___fst_exp__h87030 + 8'd1 ; - assign din_inc___2_exp__h96432 = _theResult___fst_exp__h95745 + 8'd1 ; - assign guard__h110776 = - { IF_theResult___snd18688_BIT_4_THEN_2_ELSE_0__q95[1], - { _theResult___snd__h118688[3:0], 52'd0 } != 56'd0 } ; - assign guard__h120084 = - { IF_sfdin28304_BIT_4_THEN_2_ELSE_0__q98[1], - { sfdin__h128304[3:0], 52'd0 } != 56'd0 } ; - assign guard__h120682 = x__h120782 != 57'd0 ; - assign guard__h129151 = - { IF_theResult___snd37087_BIT_4_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h137087[3:0], 52'd0 } != 56'd0 } ; - assign guard__h13641 = - { IF_sfd___33631_BIT_8_THEN_2_ELSE_0__q20[1], - { sfd___3__h13631[7:0], 23'd0 } != 31'd0 } ; - assign guard__h14167 = - { IF_sfd___33631_BIT_7_THEN_2_ELSE_0__q21[1], - { sfd___3__h13631[6:0], 24'd0 } != 31'd0 } ; - assign guard__h15256 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[23], - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[22:0], - 33'd0 } != - 56'd0 } ; - assign guard__h15810 = - { IF_x5999_BIT_24_THEN_2_ELSE_0__q31[1], - { x__h15999[23:0], 32'd0 } != 56'd0 } ; - assign guard__h16818 = - { IF_x7039_BIT_24_THEN_2_ELSE_0__q32[1], - { x__h17039[23:0], 32'd0 } != 56'd0 } ; - assign guard__h35519 = - { IF_sfd___35509_BIT_2_THEN_2_ELSE_0__q33[1], - { sfd___3__h35509[1:0], 52'd0 } != 54'd0 } ; - assign guard__h36249 = - { IF_sfd___35509_BIT_1_THEN_2_ELSE_0__q34[1], - { sfd___3__h35509[0], 53'd0 } != 54'd0 } ; - assign guard__h45160 = - { IF_sfd___35150_BIT_2_THEN_2_ELSE_0__q47[1], - { sfd___3__h45150[1:0], 52'd0 } != 54'd0 } ; - assign guard__h45889 = - { IF_sfd___35150_BIT_1_THEN_2_ELSE_0__q48[1], - { sfd___3__h45150[0], 53'd0 } != 54'd0 } ; - assign guard__h47177 = - { IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[52], - { IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[51:0], - 33'd0 } != - 85'd0 } ; - assign guard__h47731 = - { IF_x7920_BIT_53_THEN_2_ELSE_0__q58[1], - { x__h47920[52:0], 32'd0 } != 85'd0 } ; - assign guard__h48722 = - { IF_x8943_BIT_53_THEN_2_ELSE_0__q59[1], - { x__h48943[52:0], 32'd0 } != 85'd0 } ; - assign guard__h61080 = - { IF_sfdin9171_BIT_33_THEN_2_ELSE_0__q61[1], - { sfdin__h69171[32:0], 23'd0 } != 56'd0 } ; - assign guard__h69815 = - { IF_theResult___snd7814_BIT_33_THEN_2_ELSE_0__q63[1], - { _theResult___snd__h77814[32:0], 23'd0 } != 56'd0 } ; - assign guard__h7519 = - { IF_sfd___3509_BIT_8_THEN_2_ELSE_0__q6[1], - { sfd___3__h7509[7:0], 23'd0 } != 31'd0 } ; - assign guard__h78804 = - { IF_sfdin7024_BIT_33_THEN_2_ELSE_0__q66[1], - { sfdin__h87024[32:0], 23'd0 } != 56'd0 } ; - assign guard__h79402 = x__h79502 != 57'd0 ; - assign guard__h8049 = - { IF_sfd___3509_BIT_7_THEN_2_ELSE_0__q7[1], - { sfd___3__h7509[6:0], 24'd0 } != 31'd0 } ; - assign guard__h87668 = - { IF_theResult___snd5691_BIT_33_THEN_2_ELSE_0__q69[1], - { _theResult___snd__h95691[32:0], 23'd0 } != 56'd0 } ; - assign out1___1__h15750 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[56:24] + - 33'd1 ; - assign out1___1__h47671 = - IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[85:53] + - 33'd1 ; - assign out___1_sfd__h97925 = { value__h97928, 29'd0 } ; - assign out_exp__h119395 = - _theResult___snd__h118688[5] ? - _theResult___exp__h119392 : - _theResult___fst_exp__h118737 ; - assign out_exp__h129042 = - sfdin__h128304[5] ? - _theResult___exp__h129039 : - _theResult___fst_exp__h128310 ; - assign out_exp__h137824 = - _theResult___snd__h137087[5] ? - _theResult___exp__h137821 : - _theResult___fst_exp__h137141 ; - assign out_exp__h14057 = - sfd___3__h13631[9] ? _theResult___exp__h14054 : 8'd0 ; - assign out_exp__h14609 = - sfd___3__h13631[8] ? _theResult___exp__h14606 : x__h14182[7:0] ; - assign out_exp__h36138 = - sfd___3__h35509[3] ? _theResult___exp__h36135 : 11'd0 ; - assign out_exp__h36894 = - sfd___3__h35509[2] ? _theResult___exp__h36891 : x__h36264[10:0] ; - assign out_exp__h45779 = - sfd___3__h45150[3] ? _theResult___exp__h45776 : 11'd0 ; - assign out_exp__h46534 = - sfd___3__h45150[2] ? _theResult___exp__h46531 : x__h45904[10:0] ; - assign out_exp__h69706 = - sfdin__h69171[34] ? - _theResult___exp__h69703 : - _theResult___fst_exp__h69177 ; - assign out_exp__h78318 = - _theResult___snd__h77814[34] ? - _theResult___exp__h78315 : - _theResult___fst_exp__h77863 ; - assign out_exp__h7938 = sfd___3__h7509[9] ? _theResult___exp__h7935 : 8'd0 ; - assign out_exp__h8491 = - sfd___3__h7509[8] ? _theResult___exp__h8488 : x__h8064[7:0] ; - assign out_exp__h87559 = - sfdin__h87024[34] ? - _theResult___exp__h87556 : - _theResult___fst_exp__h87030 ; - assign out_exp__h96225 = - _theResult___snd__h95691[34] ? - _theResult___exp__h96222 : - _theResult___fst_exp__h95745 ; - assign out_sfd__h119396 = - _theResult___snd__h118688[5] ? - _theResult___sfd__h119393 : - _theResult___snd__h118688[56:5] ; - assign out_sfd__h129043 = - sfdin__h128304[5] ? - _theResult___sfd__h129040 : - sfdin__h128304[56:5] ; - assign out_sfd__h137825 = - _theResult___snd__h137087[5] ? - _theResult___sfd__h137822 : - _theResult___snd__h137087[56:5] ; - assign out_sfd__h14058 = - sfd___3__h13631[9] ? - _theResult___sfd__h14055 : - sfd___3__h13631[31:9] ; - assign out_sfd__h14610 = - sfd___3__h13631[8] ? - _theResult___sfd__h14607 : - sfd___3__h13631[30:8] ; - assign out_sfd__h36139 = - sfd___3__h35509[3] ? - _theResult___sfd__h36136 : - sfd___3__h35509[54:3] ; - assign out_sfd__h36895 = - sfd___3__h35509[2] ? - _theResult___sfd__h36892 : - sfd___3__h35509[53:2] ; - assign out_sfd__h45780 = - sfd___3__h45150[3] ? - _theResult___sfd__h45777 : - sfd___3__h45150[54:3] ; - assign out_sfd__h46535 = - sfd___3__h45150[2] ? - _theResult___sfd__h46532 : - sfd___3__h45150[53:2] ; - assign out_sfd__h69707 = - sfdin__h69171[34] ? - _theResult___sfd__h69704 : - sfdin__h69171[56:34] ; - assign out_sfd__h78319 = - _theResult___snd__h77814[34] ? - _theResult___sfd__h78316 : - _theResult___snd__h77814[56:34] ; - assign out_sfd__h7939 = - sfd___3__h7509[9] ? - _theResult___sfd__h7936 : - sfd___3__h7509[31:9] ; - assign out_sfd__h8492 = - sfd___3__h7509[8] ? - _theResult___sfd__h8489 : - sfd___3__h7509[30:8] ; - assign out_sfd__h87560 = - sfdin__h87024[34] ? - _theResult___sfd__h87557 : - sfdin__h87024[56:34] ; - assign out_sfd__h96226 = - _theResult___snd__h95691[34] ? - _theResult___sfd__h96223 : - _theResult___snd__h95691[56:34] ; - assign requestR_3_BITS_126_TO_116_754_EQ_0_768_AND_re_ETC___d3775 = - requestR[126:116] == 11'd0 && requestR[115:64] == 52'd0 && - requestR[127] && - requestR[190:180] == 11'd0 && - requestR[179:128] == 52'd0 && - !requestR[191] ; - assign requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 = - { requestR[127:96] == 32'hFFFFFFFF && requestR[95], - (requestR[127:96] == 32'hFFFFFFFF) ? - requestR[94:64] : - 31'h7FC00000 } ; - assign requestR_3_BITS_179_TO_128_611_ULE_requestR_3__ETC___d3787 = - requestR[179:128] <= requestR[115:64] ; - assign requestR_3_BITS_179_TO_128_611_ULT_requestR_3__ETC___d3792 = - requestR[179:128] < requestR[115:64] ; - assign requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3771 = - requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 && - requestR[191] && - requestR[126:116] == 11'd0 && - requestR[115:64] == 52'd0 && - !requestR[127] ; - assign requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3843 = - requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 && - requestR[126:116] == 11'd0 && - requestR[115:64] == 52'd0 || - (!requestR[191] || requestR[127]) && - (requestR[191] || !requestR[127]) && - (requestR[191] ? - requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3838 : - NOT_requestR_3_BITS_190_TO_180_609_ULT_request_ETC___d3839) ; - assign requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1759 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - (NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1722 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1741 && - x__h48943[85:54] == 32'hFFFFFFFF) ; - assign requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1770 = - { requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1759, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1764 } == - 5'd0 || - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1759 ; - assign requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3763 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115] ; - assign requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3808 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179] || - requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0 && - !requestR[115] ; - assign requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3828 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3808 || - requestR[190:180] == 11'd2047 && requestR[179] || - requestR[126:116] == 11'd2047 && requestR[115] ; - assign requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 = - requestR[190:180] == requestR[126:116] ; - assign requestR_3_BITS_190_TO_180_609_MINUS_1023___d1622 = - requestR[190:180] - 11'd1023 ; - assign requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3784 = - requestR[190:180] <= requestR[126:116] ; - assign requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3838 = - requestR_3_BITS_190_TO_180_609_ULE_requestR_3__ETC___d3784 && - (!requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 || - requestR_3_BITS_179_TO_128_611_ULE_requestR_3__ETC___d3787) && - !requestR_3_BITS_190_TO_180_609_ULT_requestR_3__ETC___d3791 && - (!requestR_3_BITS_190_TO_180_609_EQ_requestR_3_B_ETC___d3786 || - !requestR_3_BITS_179_TO_128_611_ULT_requestR_3__ETC___d3792) ; - assign requestR_3_BITS_190_TO_180_609_ULT_requestR_3__ETC___d3791 = - requestR[190:180] < requestR[126:116] ; - assign requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d1042 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159] && - (requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) || - (requestR[191:160] == 32'hFFFFFFFF && requestR[159] || - requestR[127:96] != 32'hFFFFFFFF || - !requestR[95]) && - IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1040 ; - assign requestR_3_BIT_158_07_OR_requestR_3_BIT_157_09_ETC___d789 = - requestR[158] || requestR[157] || requestR[156] || - requestR[155] || - requestR[154] || - requestR[153] || - requestR[152] || - requestR[151] || - requestR[150] || - requestR[149] || - requestR[148] || - requestR[147] || - requestR[146] || - requestR[145] || - requestR[144] || - requestR[143] || - requestR[142] || - requestR[141] || - requestR[140] || - requestR[139] || - requestR[138] || - requestR[137] || - requestR[136] || - requestR[135] || - requestR[134] || - requestR[133] || - requestR[132] || - requestR[131] || - requestR[130] || - requestR[129] || - requestR[128] ; - assign requestR_3_BIT_159_6_OR_requestR_3_BIT_158_07__ETC___d811 = - (requestR[159] || - requestR_3_BIT_158_07_OR_requestR_3_BIT_157_09_ETC___d789) && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637 && - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d808 ; - assign requestR_BITS_159_TO_128__q1 = requestR[159:128] ; - assign res___1__h154853 = - (requestR[190:180] == 11'd2047 && requestR[179]) ? - 64'd512 : - 64'd256 ; - assign res___1__h155291 = requestR[191] ? 64'd1 : 64'd128 ; - assign res___1__h155301 = requestR[191] ? 64'd8 : 64'd16 ; - assign res___1__h155320 = requestR[191] ? 64'd4 : 64'd32 ; - assign res___1__h25997 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205[22]) ? - 64'd512 : - 64'd256 ; - assign res___1__h26233 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd1 : - 64'd128 ; - assign res___1__h26243 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd8 : - 64'd16 ; - assign res___1__h26262 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd4 : - 64'd32 ; - assign res__h138561 = - { IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3660, - x__h97869, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3624 } ; - assign res__h142948 = - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3799 ? - requestR[191:128] : - requestR[127:64] ; - assign res__h147441 = - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3799 ? - requestR[127:64] : - requestR[191:128] ; - assign res__h150090 = - ((requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_re_ETC___d3843) ? - 64'd1 : - 64'd0 ; - assign res__h152730 = - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3799 ? - 64'd1 : - 64'd0 ; - assign res__h154552 = - NOT_requestR_3_BITS_190_TO_180_609_EQ_2047_610_ETC___d3860 ? - 64'd1 : - 64'd0 ; - assign res__h155336 = requestR[191] ? 64'd2 : 64'd64 ; - assign res__h155490 = { 32'hFFFFFFFF, fpu$server_core_response_get[36:5] } ; - assign res__h17988 = - { 32'hFFFFFFFF, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 } ; - assign res__h18225 = - { 32'hFFFFFFFF, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign res__h23375 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1103 ? - 64'd1 : - 64'd0 ; - assign res__h24803 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1044 ? - 64'd1 : - 64'd0 ; - assign res__h25817 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1119 ? - 64'd1 : - 64'd0 ; - assign res__h26278 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd2 : - 64'd64 ; - assign res__h96811 = { 32'hFFFFFFFF, x__h96817 } ; - assign result__h120687 = - { _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d3162[56:1], - _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d3162[0] | - guard__h120682 } ; - assign result__h79407 = - { _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_609__ETC___d2329[56:1], - _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_609__ETC___d2329[0] | - guard__h79402 } ; - assign sV1_exp__h1204 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[158:151] : - 8'd255 ; - assign sV1_sfd__h1205 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[150:128] : - 23'd4194304 ; - assign sV2_exp__h1307 = - (requestR[127:96] == 32'hFFFFFFFF) ? requestR[94:87] : 8'd255 ; - assign sV2_sfd__h1308 = - (requestR[127:96] == 32'hFFFFFFFF) ? - requestR[86:64] : - 23'd4194304 ; - assign sfd___3__h13631 = - requestR[159:128] << - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d632 ; - assign sfd___3__h35509 = - sfd__h27508 << - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1242 ; - assign sfd___3__h45150 = - sfd__h37398 << - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1456 ; - assign sfd___3__h7509 = - sfd__h2605 << - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d275 ; - assign sfd__h118755 = - { 1'b0, - _theResult___fst_exp__h118737 != 11'd0, - _theResult___snd__h118688[56:5] } + - 54'd1 ; - assign sfd__h128402 = - { 1'b0, - _theResult___fst_exp__h128310 != 11'd0, - sfdin__h128304[56:5] } + - 54'd1 ; - assign sfd__h13658 = { 2'd0, sfd___3__h13631[31:9] } + 25'd1 ; - assign sfd__h137160 = - { 1'b0, - _theResult___fst_exp__h137141 != 11'd0, - _theResult___snd__h137087[56:5] } + - 54'd1 ; - assign sfd__h14197 = - { 1'b0, x__h14182[7:0] != 8'd0, sfd___3__h13631[30:8] } + 25'd1 ; - assign sfd__h2605 = requestR[159] ? -requestR[159:128] : requestR[159:128] ; - assign sfd__h27508 = { sfd__h2605, 23'd0 } ; - assign sfd__h35536 = { 2'd0, sfd___3__h35509[54:3] } + 54'd1 ; - assign sfd__h36279 = - { 1'b0, x__h36264[10:0] != 11'd0, sfd___3__h35509[53:2] } + - 54'd1 ; - assign sfd__h37398 = { requestR[159:128], 23'd0 } ; - assign sfd__h45177 = { 2'd0, sfd___3__h45150[54:3] } + 54'd1 ; - assign sfd__h45919 = - { 1'b0, x__h45904[10:0] != 11'd0, sfd___3__h45150[53:2] } + - 54'd1 ; - assign sfd__h53440 = { value__h47246, 3'd0 } ; - assign sfd__h69269 = - { 1'b0, - _theResult___fst_exp__h69177 != 8'd0, - sfdin__h69171[56:34] } + - 25'd1 ; - assign sfd__h7536 = { 2'd0, sfd___3__h7509[31:9] } + 25'd1 ; - assign sfd__h77881 = - { 1'b0, - _theResult___fst_exp__h77863 != 8'd0, - _theResult___snd__h77814[56:34] } + - 25'd1 ; - assign sfd__h8079 = - { 1'b0, x__h8064[7:0] != 8'd0, sfd___3__h7509[30:8] } + 25'd1 ; - assign sfd__h87122 = - { 1'b0, - _theResult___fst_exp__h87030 != 8'd0, - sfdin__h87024[56:34] } + - 25'd1 ; - assign sfd__h95764 = - { 1'b0, - _theResult___fst_exp__h95745 != 8'd0, - _theResult___snd__h95691[56:34] } + - 25'd1 ; - assign sfdin__h128304 = - _theResult____h120074[56] ? - _theResult___snd__h128321 : - _theResult___snd__h128332 ; - assign sfdin__h69171 = - _theResult____h61070[56] ? - _theResult___snd__h69188 : - _theResult___snd__h69199 ; - assign sfdin__h87024 = - _theResult____h78794[56] ? - _theResult___snd__h87041 : - _theResult___snd__h87052 ; - assign value__h15325 = { 1'b0, sV1_exp__h1204 != 8'd0, sV1_sfd__h1205 } ; - assign value__h47246 = - { 1'b0, requestR[190:180] != 11'd0, requestR[179:128] } ; - assign value__h49279 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179]) ? - _theResult___fst_sfd__h49736 : - requestR[179:128] ; - assign value__h97928 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 && - !sV1_sfd__h1205[22]) ? - _theResult___fst_sfd__h98183 : - sV1_sfd__h1205 ; - assign x__h120782 = b__h15323 << x__h120815 ; - assign x__h120815 = - 12'd57 - - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d3158 ; - assign x__h138663 = - { IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3698, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3705, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3719, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3731, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3743 } ; - assign x__h139530 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3763 ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115]) ? - requestR[191:128] : - ((requestR[190:180] == 11'd2047 && requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115]) ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && requestR[179]) ? - requestR[127:64] : - IF_requestR_3_BITS_126_TO_116_754_EQ_2047_755__ETC___d3802)))) ; - assign x__h14182 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d635 + - 9'd127 ; - assign x__h143080 = - { requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3808, - 4'd0 } ; - assign x__h144023 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3763 ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115]) ? - requestR[191:128] : - ((requestR[190:180] == 11'd2047 && requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115]) ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && requestR[115]) ? - requestR[191:128] : - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3815))))) ; - assign x__h148412 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3828 ? - 64'd0 : - res__h150090 ; - assign x__h14848 = - { 2'd0, - NOT_requestR_3_BITS_159_TO_128_44_EQ_0_45_46_A_ETC___d800, - requestR[159:128] != 32'd0 && - (requestR[159] || - requestR_3_BIT_158_07_OR_requestR_3_BIT_157_09_ETC___d789) && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637, - requestR[159:128] != 32'd0 && - requestR_3_BIT_159_6_OR_requestR_3_BIT_158_07__ETC___d811 } ; - assign x__h15077 = { {32{x__h15080[31]}}, x__h15080 } ; - assign x__h15080 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d832 ? - 32'h7FFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d904 ; - assign x__h151052 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3828 ? - 64'd0 : - res__h152730 ; - assign x__h152749 = - { requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0, - 4'd0 } ; - assign x__h152874 = - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d3828 ? - 64'd0 : - res__h154552 ; - assign x__h154833 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - res___1__h154853 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - res___1__h155291 : - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d3881) ; - assign x__h155457 = - fpu$server_core_response_get[69] ? - res__h155490 : - fpu$server_core_response_get[68:5] ; - assign x__h15999 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845 >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871 | - ~(57'h1FFFFFFFFFFFFFF >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d871) & - {57{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d845[56]}} ; - assign x__h16413 = - { sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 || - sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 == 23'd0 || - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d915, - 3'd0, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - (sV1_exp__h1204 != 8'd0 || sV1_sfd__h1205 != 23'd0) && - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d926 } ; - assign x__h16615 = { {32{x__h16618[31]}}, x__h16618 } ; - assign x__h16618 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d832 ? - 32'hFFFFFFFF : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d965 ; - assign x__h17039 = - { sV1_exp__h1204 != 8'd0, sV1_sfd__h1205, 33'd0 } >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d934 ; - assign x__h17117 = - { (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d984 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d973, - 3'd0, - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 == 23'd0) && - (sV1_exp__h1204 != 8'd255 || sV1_sfd__h1205 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d978 } ; - assign x__h17309 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1006 ? - 64'hFFFFFFFF7FC00000 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1052 ; - assign x__h19349 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1054, - 4'd0 } ; - assign x__h19888 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1006 ? - 64'hFFFFFFFF7FC00000 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1067 ; - assign x__h22358 = { 32'hFFFFFFFF, requestR[159:128] } ; - assign x__h22423 = - { {32{requestR_BITS_159_TO_128__q1[31]}}, - requestR_BITS_159_TO_128__q1 } ; - assign x__h22505 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1087 ? - 64'd0 : - res__h23375 ; - assign x__h2333 = { 32'hFFFFFFFF, x__h2340 } ; - assign x__h2340 = - { requestR[127:96] == 32'hFFFFFFFF && requestR[95], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h23933 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1087 ? - 64'd0 : - res__h24803 ; - assign x__h2414 = { 32'hFFFFFFFF, x__h2421 } ; - assign x__h2421 = - { requestR[127:96] != 32'hFFFFFFFF || !requestR[95], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h24822 = - { sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0 || - sV2_exp__h1307 == 8'd255 && sV2_sfd__h1308 != 23'd0, - 4'd0 } ; - assign x__h2492 = { 32'hFFFFFFFF, x__h2499 } ; - assign x__h24947 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1087 ? - 64'd0 : - res__h25817 ; - assign x__h2499 = - { (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) != - (requestR[127:96] == 32'hFFFFFFFF && requestR[95]), - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h2584 = { 32'hFFFFFFFF, x__h2590 } ; - assign x__h2590 = - { requestR[159:128] != 32'd0 && - (NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d283 ? - requestR[159] : - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d345), - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d405, - (requestR[159:128] == 32'd0 || - NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d283) ? - 23'd0 : - _theResult___snd_fst_sfd__h8592 } ; - assign x__h25977 = - (sV1_exp__h1204 == 8'd255 && sV1_sfd__h1205 != 23'd0) ? - res___1__h25997 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1132 ; - assign x__h27284 = { requestR[127], requestR[190:128] } ; - assign x__h27350 = { !requestR[127], requestR[190:128] } ; - assign x__h27418 = { requestR[191] != requestR[127], requestR[190:128] } ; - assign x__h27493 = - { requestR[159:128] != 32'd0 && - IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d1302, - (requestR[159:128] == 32'd0) ? - 11'd0 : - _theResult___snd_fst_exp__h37000, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1399 } ; - assign x__h36264 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1245 + - 12'd1023 ; - assign x__h37156 = - { 2'd0, - requestR[159:128] != 32'd0 && - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1250 && - _theResult___fst_exp__h36991 == 11'd2047 && - _theResult___fst_sfd__h36992 == 52'd0), - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248, - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1246 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1248 && - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1416 } ; - assign x__h37386 = - { 1'd0, - (requestR[159:128] == 32'd0) ? - 11'd0 : - _theResult___snd_fst_exp__h46639, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d1581 } ; - assign x__h45904 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1459 + - 12'd1023 ; - assign x__h46769 = - { 2'd0, - requestR[159:128] != 32'd0 && - (!_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1462 && - _theResult___fst_exp__h46630 == 11'd2047 && - _theResult___fst_sfd__h46631 == 52'd0), - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461, - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1460 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1461 && - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1598 } ; - assign x__h46998 = { {32{x__h47001[31]}}, x__h47001 } ; - assign x__h47001 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'h7FFFFFFF : - IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d1690 ; - assign x__h47920 = - IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631 >> - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657 | - ~(86'h3FFFFFFFFFFFFFFFFFFFFF >> - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1657) & - {86{IF_requestR_3_BIT_191_202_THEN_NEG_0b0_CONCAT__ETC___d1631[85]}} ; - assign x__h48317 = - { requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1701, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_609_MIN_ETC___d1712 } ; - assign x__h48519 = { {32{x__h48522[31]}}, x__h48522 } ; - assign x__h48522 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'hFFFFFFFF : - (requestR[191] ? - 32'd0 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'hFFFFFFFF : - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_AND_ETC___d1749)) ; - assign x__h48943 = - { requestR[190:180] != 11'd0, requestR[179:128], 33'd0 } >> - NEG_SEXT_requestR_3_BITS_190_TO_180_609_MINUS__ETC___d1720 ; - assign x__h49021 = - { requestR[191] ? - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1770 : - requestR_3_BITS_190_TO_180_609_EQ_2047_610_AND_ETC___d1759, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_609_EQ_0_620_62_ETC___d1764 } ; - assign x__h49209 = - (x__h49219 == 8'd255 && - IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d2809[22]) ? - 64'hFFFFFFFF7FC00000 : - res__h96811 ; - assign x__h49219 = - (requestR[190:180] == 11'd2047) ? - 8'd255 : - _theResult___fst_exp__h96335 ; - assign x__h79502 = sfd__h53440 << x__h79535 ; - assign x__h79535 = - 12'd57 - - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_609_ETC___d2325 ; - assign x__h8064 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d278 + - 9'd127 ; - assign x__h8757 = - { 2'd0, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d486, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d489, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d498 } ; - assign x__h8990 = - { 33'h1FFFFFFFE, - IF_requestR_3_BITS_159_TO_128_44_EQ_0_45_OR_NO_ETC___d722, - (requestR[159:128] == 32'd0 || - !requestR[159] && - NOT_requestR_3_BIT_158_07_08_AND_NOT_requestR__ETC___d598 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d636 || - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d637) ? - 23'd0 : - _theResult___snd_fst_sfd__h14709 } ; - assign x__h96817 = - { (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - (requestR[190:180] == 11'd2047 || - requestR[190:180] == 11'd0) && - requestR[179:128] == 52'd0) ? - requestR[191] : - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2851, - x__h49219, - IF_requestR_3_BITS_190_TO_180_609_EQ_2047_610__ETC___d2809 } ; - assign x__h96932 = - { (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179] : - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2902, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2913, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2929, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2942, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_609_EQ_0_620_THE_ETC___d2955 } ; - assign x__h97859 = - (x__h97869 == 11'd2047 && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3624[51]) ? - 64'h7FF8000000000000 : - res__h138561 ; - assign x__h97869 = - (sV1_exp__h1204 == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h137934 ; - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd254; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = - requestR[191] ? 8'd255 : 8'd254; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = - requestR[191] ? 8'd254 : 8'd255; - default: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - 23'd8388607; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - requestR[191] ? 23'd0 : 23'd8388607; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - requestR[191] ? 23'd8388607 : 23'd0; - default: CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = 23'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd2046; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 11'd2047 : - 11'd2046; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 11'd2046 : - 11'd2047; - default: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - 52'hFFFFFFFFFFFFF; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 52'hFFFFFFFFFFFFF : - 52'd0; - default: CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = 52'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h0: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = - requestR[194:192]; - 3'h1: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd4; - 3'h2: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd3; - 3'h3: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd2; - 3'h4: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd1; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = - 3'd0; - endcase - end - always@(guard__h7519 or requestR) - begin - case (guard__h7519) - 2'b0, 2'b01, 2'b10: - CASE_guard519_0b0_requestR_BIT_159_0b1_request_ETC__q8 = - requestR[159]; - 2'd3: - CASE_guard519_0b0_requestR_BIT_159_0b1_request_ETC__q8 = - guard__h7519 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h7519) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 = - (guard__h7519 == 2'b0) ? - requestR[159] : - (guard__h7519 == 2'b01 || guard__h7519 == 2'b10 || - guard__h7519 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h8049 or requestR) - begin - case (guard__h8049) - 2'b0, 2'b01, 2'b10: - CASE_guard049_0b0_requestR_BIT_159_0b1_request_ETC__q10 = - requestR[159]; - 2'd3: - CASE_guard049_0b0_requestR_BIT_159_0b1_request_ETC__q10 = - guard__h8049 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h8049) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - (guard__h8049 == 2'b0) ? - requestR[159] : - (guard__h8049 == 2'b01 || guard__h8049 == 2'b10 || - guard__h8049 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h7519 or _theResult___exp__h7935) - begin - case (guard__h7519) - 2'b0: CASE_guard519_0b0_0_0b1_theResult___exp935_0b1_ETC__q12 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard519_0b0_0_0b1_theResult___exp935_0b1_ETC__q12 = - _theResult___exp__h7935; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d367 or - guard__h7519 or - _theResult___exp__h7935 or - CASE_guard519_0b0_0_0b1_theResult___exp935_0b1_ETC__q12) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d367; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370 = - (guard__h7519 == 2'b0 || requestR[159]) ? - 8'd0 : - _theResult___exp__h7935; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370 = - CASE_guard519_0b0_0_0b1_theResult___exp935_0b1_ETC__q12; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d370 = - 8'd0; - endcase - end - always@(guard__h7519 or out_exp__h7938 or _theResult___exp__h7935) - begin - case (guard__h7519) - 2'b0, 2'b01: - CASE_guard519_0b0_0_0b1_0_0b10_out_exp938_0b11_ETC__q13 = 8'd0; - 2'b10: - CASE_guard519_0b0_0_0b1_0_0b10_out_exp938_0b11_ETC__q13 = - out_exp__h7938; - 2'b11: - CASE_guard519_0b0_0_0b1_0_0b10_out_exp938_0b11_ETC__q13 = - _theResult___exp__h7935; - endcase - end - always@(guard__h8049 or x__h8064 or _theResult___exp__h8488) - begin - case (guard__h8049) - 2'b0: - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_theResu_ETC__q14 = - x__h8064[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_theResu_ETC__q14 = - _theResult___exp__h8488; - endcase - end - always@(requestR or - x__h8064 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d395 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d393 or - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_theResu_ETC__q14) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 = - x__h8064[7:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d395; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d393; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 = - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_theResu_ETC__q14; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d399 = - 8'd0; - endcase - end - always@(guard__h8049 or - x__h8064 or out_exp__h8491 or _theResult___exp__h8488) - begin - case (guard__h8049) - 2'b0, 2'b01: - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_x064_BI_ETC__q15 = - x__h8064[7:0]; - 2'b10: - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_x064_BI_ETC__q15 = - out_exp__h8491; - 2'b11: - CASE_guard049_0b0_x064_BITS_7_TO_0_0b1_x064_BI_ETC__q15 = - _theResult___exp__h8488; - endcase - end - always@(guard__h7519 or sfd___3__h7509 or _theResult___sfd__h7936) - begin - case (guard__h7519) - 2'b0: - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q16 = - sfd___3__h7509[31:9]; - 2'b01, 2'b10, 2'b11: - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q16 = - _theResult___sfd__h7936; - endcase - end - always@(requestR or - sfd___3__h7509 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d418 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d416 or - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q16) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 = - sfd___3__h7509[31:9]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d418; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d416; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 = - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q16; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d422 = - 23'd0; - endcase - end - always@(guard__h7519 or - sfd___3__h7509 or out_sfd__h7939 or _theResult___sfd__h7936) - begin - case (guard__h7519) - 2'b0, 2'b01: - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q17 = - sfd___3__h7509[31:9]; - 2'b10: - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q17 = - out_sfd__h7939; - 2'b11: - CASE_guard519_0b0_sfd___3509_BITS_31_TO_9_0b1__ETC__q17 = - _theResult___sfd__h7936; - endcase - end - always@(guard__h8049 or sfd___3__h7509 or _theResult___sfd__h8489) - begin - case (guard__h8049) - 2'b0: - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q18 = - sfd___3__h7509[30:8]; - 2'b01, 2'b10, 2'b11: - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q18 = - _theResult___sfd__h8489; - endcase - end - always@(requestR or - sfd___3__h7509 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d436 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d434 or - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q18) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 = - sfd___3__h7509[30:8]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d436; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d434; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 = - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q18; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d440 = - 23'd0; - endcase - end - always@(guard__h8049 or - sfd___3__h7509 or out_sfd__h8492 or _theResult___sfd__h8489) - begin - case (guard__h8049) - 2'b0, 2'b01: - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q19 = - sfd___3__h7509[30:8]; - 2'b10: - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q19 = - out_sfd__h8492; - 2'b11: - CASE_guard049_0b0_sfd___3509_BITS_30_TO_8_0b1__ETC__q19 = - _theResult___sfd__h8489; - endcase - end - always@(guard__h13641 or out_exp__h14057 or _theResult___exp__h14054) - begin - case (guard__h13641) - 2'b0, 2'b01: - CASE_guard3641_0b0_0_0b1_0_0b10_out_exp4057_0b_ETC__q22 = 8'd0; - 2'b10: - CASE_guard3641_0b0_0_0b1_0_0b10_out_exp4057_0b_ETC__q22 = - out_exp__h14057; - 2'b11: - CASE_guard3641_0b0_0_0b1_0_0b10_out_exp4057_0b_ETC__q22 = - _theResult___exp__h14054; - endcase - end - always@(guard__h13641 or _theResult___exp__h14054) - begin - case (guard__h13641) - 2'b0: CASE_guard3641_0b0_0_0b1_theResult___exp4054_0_ETC__q23 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard3641_0b0_0_0b1_theResult___exp4054_0_ETC__q23 = - _theResult___exp__h14054; - endcase - end - always@(requestR or - guard__h13641 or - _theResult___exp__h14054 or - CASE_guard3641_0b0_0_0b1_theResult___exp4054_0_ETC__q23) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard3641_ETC__q24 = - (guard__h13641 == 2'b0) ? 8'd0 : _theResult___exp__h14054; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard3641_ETC__q24 = - CASE_guard3641_0b0_0_0b1_theResult___exp4054_0_ETC__q23; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard3641_ETC__q24 = 8'd0; - endcase - end - always@(guard__h14167 or x__h14182 or _theResult___exp__h14606) - begin - case (guard__h14167) - 2'b0: - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_theRe_ETC__q25 = - x__h14182[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_theRe_ETC__q25 = - _theResult___exp__h14606; - endcase - end - always@(requestR or - x__h14182 or - guard__h14167 or - _theResult___exp__h14606 or - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_theRe_ETC__q25) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716 = - x__h14182[7:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716 = - (guard__h14167 == 2'b0) ? - x__h14182[7:0] : - _theResult___exp__h14606; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716 = - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_theRe_ETC__q25; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d716 = - 8'd0; - endcase - end - always@(guard__h14167 or - x__h14182 or out_exp__h14609 or _theResult___exp__h14606) - begin - case (guard__h14167) - 2'b0, 2'b01: - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_x4182_ETC__q26 = - x__h14182[7:0]; - 2'b10: - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_x4182_ETC__q26 = - out_exp__h14609; - 2'b11: - CASE_guard4167_0b0_x4182_BITS_7_TO_0_0b1_x4182_ETC__q26 = - _theResult___exp__h14606; - endcase - end - always@(guard__h14167 or sfd___3__h13631 or _theResult___sfd__h14607) - begin - case (guard__h14167) - 2'b0: - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q27 = - sfd___3__h13631[30:8]; - 2'b01, 2'b10, 2'b11: - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q27 = - _theResult___sfd__h14607; - endcase - end - always@(requestR or - sfd___3__h13631 or - guard__h14167 or - _theResult___sfd__h14607 or - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q27) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754 = - sfd___3__h13631[30:8]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754 = - (guard__h14167 == 2'b0) ? - sfd___3__h13631[30:8] : - _theResult___sfd__h14607; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754 = - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q27; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d754 = - 23'd0; - endcase - end - always@(guard__h14167 or - sfd___3__h13631 or out_sfd__h14610 or _theResult___sfd__h14607) - begin - case (guard__h14167) - 2'b0, 2'b01: - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q28 = - sfd___3__h13631[30:8]; - 2'b10: - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q28 = - out_sfd__h14610; - 2'b11: - CASE_guard4167_0b0_sfd___33631_BITS_30_TO_8_0b_ETC__q28 = - _theResult___sfd__h14607; - endcase - end - always@(guard__h13641 or sfd___3__h13631 or _theResult___sfd__h14055) - begin - case (guard__h13641) - 2'b0: - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q29 = - sfd___3__h13631[31:9]; - 2'b01, 2'b10, 2'b11: - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q29 = - _theResult___sfd__h14055; - endcase - end - always@(requestR or - sfd___3__h13631 or - guard__h13641 or - _theResult___sfd__h14055 or - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q29) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739 = - sfd___3__h13631[31:9]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739 = - (guard__h13641 == 2'b0) ? - sfd___3__h13631[31:9] : - _theResult___sfd__h14055; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739 = - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q29; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d739 = - 23'd0; - endcase - end - always@(guard__h13641 or - sfd___3__h13631 or out_sfd__h14058 or _theResult___sfd__h14055) - begin - case (guard__h13641) - 2'b0, 2'b01: - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q30 = - sfd___3__h13631[31:9]; - 2'b10: - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q30 = - out_sfd__h14058; - 2'b11: - CASE_guard3641_0b0_sfd___33631_BITS_31_TO_9_0b_ETC__q30 = - _theResult___sfd__h14055; - endcase - end - always@(guard__h35519 or requestR) - begin - case (guard__h35519) - 2'b0, 2'b01, 2'b10: - CASE_guard5519_0b0_requestR_BIT_159_0b1_reques_ETC__q35 = - requestR[159]; - 2'd3: - CASE_guard5519_0b0_requestR_BIT_159_0b1_reques_ETC__q35 = - guard__h35519 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h35519) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 = - (guard__h35519 == 2'b0) ? - requestR[159] : - (guard__h35519 == 2'b01 || guard__h35519 == 2'b10 || - guard__h35519 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h36249 or requestR) - begin - case (guard__h36249) - 2'b0, 2'b01, 2'b10: - CASE_guard6249_0b0_requestR_BIT_159_0b1_reques_ETC__q37 = - requestR[159]; - 2'd3: - CASE_guard6249_0b0_requestR_BIT_159_0b1_reques_ETC__q37 = - guard__h36249 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h36249) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 = - (guard__h36249 == 2'b0) ? - requestR[159] : - (guard__h36249 == 2'b01 || guard__h36249 == 2'b10 || - guard__h36249 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h36249 or x__h36264 or _theResult___exp__h36891) - begin - case (guard__h36249) - 2'b0: - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_theR_ETC__q39 = - x__h36264[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_theR_ETC__q39 = - _theResult___exp__h36891; - endcase - end - always@(requestR or - x__h36264 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1350 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1348 or - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_theR_ETC__q39) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 = - x__h36264[10:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1350; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1348; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 = - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_theR_ETC__q39; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1354 = - 11'd0; - endcase - end - always@(guard__h36249 or - x__h36264 or out_exp__h36894 or _theResult___exp__h36891) - begin - case (guard__h36249) - 2'b0, 2'b01: - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_x626_ETC__q40 = - x__h36264[10:0]; - 2'b10: - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_x626_ETC__q40 = - out_exp__h36894; - 2'b11: - CASE_guard6249_0b0_x6264_BITS_10_TO_0_0b1_x626_ETC__q40 = - _theResult___exp__h36891; - endcase - end - always@(guard__h36249 or sfd___3__h35509 or _theResult___sfd__h36892) - begin - case (guard__h36249) - 2'b0: - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q41 = - sfd___3__h35509[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q41 = - _theResult___sfd__h36892; - endcase - end - always@(requestR or - sfd___3__h35509 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1391 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1389 or - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q41) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 = - sfd___3__h35509[53:2]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1391; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1389; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 = - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q41; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1395 = - 52'd0; - endcase - end - always@(guard__h36249 or - sfd___3__h35509 or out_sfd__h36895 or _theResult___sfd__h36892) - begin - case (guard__h36249) - 2'b0, 2'b01: - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q42 = - sfd___3__h35509[53:2]; - 2'b10: - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q42 = - out_sfd__h36895; - 2'b11: - CASE_guard6249_0b0_sfd___35509_BITS_53_TO_2_0b_ETC__q42 = - _theResult___sfd__h36892; - endcase - end - always@(guard__h35519 or _theResult___exp__h36135) - begin - case (guard__h35519) - 2'b0: CASE_guard5519_0b0_0_0b1_theResult___exp6135_0_ETC__q43 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard5519_0b0_0_0b1_theResult___exp6135_0_ETC__q43 = - _theResult___exp__h36135; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1322 or - guard__h35519 or - _theResult___exp__h36135 or - CASE_guard5519_0b0_0_0b1_theResult___exp6135_0_ETC__q43) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1322; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325 = - (guard__h35519 == 2'b0 || requestR[159]) ? - 11'd0 : - _theResult___exp__h36135; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325 = - CASE_guard5519_0b0_0_0b1_theResult___exp6135_0_ETC__q43; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1325 = - 11'd0; - endcase - end - always@(guard__h35519 or out_exp__h36138 or _theResult___exp__h36135) - begin - case (guard__h35519) - 2'b0, 2'b01: - CASE_guard5519_0b0_0_0b1_0_0b10_out_exp6138_0b_ETC__q44 = 11'd0; - 2'b10: - CASE_guard5519_0b0_0_0b1_0_0b10_out_exp6138_0b_ETC__q44 = - out_exp__h36138; - 2'b11: - CASE_guard5519_0b0_0_0b1_0_0b10_out_exp6138_0b_ETC__q44 = - _theResult___exp__h36135; - endcase - end - always@(guard__h35519 or sfd___3__h35509 or _theResult___sfd__h36136) - begin - case (guard__h35519) - 2'b0: - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q45 = - sfd___3__h35509[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q45 = - _theResult___sfd__h36136; - endcase - end - always@(requestR or - sfd___3__h35509 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1373 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1371 or - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q45) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 = - sfd___3__h35509[54:3]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1373; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1371; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 = - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q45; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1377 = - 52'd0; - endcase - end - always@(guard__h35519 or - sfd___3__h35509 or out_sfd__h36139 or _theResult___sfd__h36136) - begin - case (guard__h35519) - 2'b0, 2'b01: - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q46 = - sfd___3__h35509[54:3]; - 2'b10: - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q46 = - out_sfd__h36139; - 2'b11: - CASE_guard5519_0b0_sfd___35509_BITS_54_TO_3_0b_ETC__q46 = - _theResult___sfd__h36136; - endcase - end - always@(guard__h45160 or out_exp__h45779 or _theResult___exp__h45776) - begin - case (guard__h45160) - 2'b0, 2'b01: - CASE_guard5160_0b0_0_0b1_0_0b10_out_exp5779_0b_ETC__q49 = 11'd0; - 2'b10: - CASE_guard5160_0b0_0_0b1_0_0b10_out_exp5779_0b_ETC__q49 = - out_exp__h45779; - 2'b11: - CASE_guard5160_0b0_0_0b1_0_0b10_out_exp5779_0b_ETC__q49 = - _theResult___exp__h45776; - endcase - end - always@(guard__h45160 or _theResult___exp__h45776) - begin - case (guard__h45160) - 2'b0: CASE_guard5160_0b0_0_0b1_theResult___exp5776_0_ETC__q50 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard5160_0b0_0_0b1_theResult___exp5776_0_ETC__q50 = - _theResult___exp__h45776; - endcase - end - always@(requestR or - guard__h45160 or - _theResult___exp__h45776 or - CASE_guard5160_0b0_0_0b1_theResult___exp5776_0_ETC__q50) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5160_ETC__q51 = - (guard__h45160 == 2'b0) ? 11'd0 : _theResult___exp__h45776; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5160_ETC__q51 = - CASE_guard5160_0b0_0_0b1_theResult___exp5776_0_ETC__q50; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard5160_ETC__q51 = - 11'd0; - endcase - end - always@(guard__h45889 or x__h45904 or _theResult___exp__h46531) - begin - case (guard__h45889) - 2'b0: - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_theR_ETC__q52 = - x__h45904[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_theR_ETC__q52 = - _theResult___exp__h46531; - endcase - end - always@(requestR or - x__h45904 or - guard__h45889 or - _theResult___exp__h46531 or - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_theR_ETC__q52) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540 = - x__h45904[10:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540 = - (guard__h45889 == 2'b0) ? - x__h45904[10:0] : - _theResult___exp__h46531; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540 = - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_theR_ETC__q52; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1540 = - 11'd0; - endcase - end - always@(guard__h45889 or - x__h45904 or out_exp__h46534 or _theResult___exp__h46531) - begin - case (guard__h45889) - 2'b0, 2'b01: - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_x590_ETC__q53 = - x__h45904[10:0]; - 2'b10: - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_x590_ETC__q53 = - out_exp__h46534; - 2'b11: - CASE_guard5889_0b0_x5904_BITS_10_TO_0_0b1_x590_ETC__q53 = - _theResult___exp__h46531; - endcase - end - always@(guard__h45889 or sfd___3__h45150 or _theResult___sfd__h46532) - begin - case (guard__h45889) - 2'b0: - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q54 = - sfd___3__h45150[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q54 = - _theResult___sfd__h46532; - endcase - end - always@(requestR or - sfd___3__h45150 or - guard__h45889 or - _theResult___sfd__h46532 or - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q54) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577 = - sfd___3__h45150[53:2]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577 = - (guard__h45889 == 2'b0) ? - sfd___3__h45150[53:2] : - _theResult___sfd__h46532; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577 = - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q54; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1577 = - 52'd0; - endcase - end - always@(guard__h45889 or - sfd___3__h45150 or out_sfd__h46535 or _theResult___sfd__h46532) - begin - case (guard__h45889) - 2'b0, 2'b01: - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q55 = - sfd___3__h45150[53:2]; - 2'b10: - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q55 = - out_sfd__h46535; - 2'b11: - CASE_guard5889_0b0_sfd___35150_BITS_53_TO_2_0b_ETC__q55 = - _theResult___sfd__h46532; - endcase - end - always@(guard__h45160 or sfd___3__h45150 or _theResult___sfd__h45777) - begin - case (guard__h45160) - 2'b0: - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q56 = - sfd___3__h45150[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q56 = - _theResult___sfd__h45777; - endcase - end - always@(requestR or - sfd___3__h45150 or - guard__h45160 or - _theResult___sfd__h45777 or - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q56) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562 = - sfd___3__h45150[54:3]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562 = - (guard__h45160 == 2'b0) ? - sfd___3__h45150[54:3] : - _theResult___sfd__h45777; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562 = - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q56; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1562 = - 52'd0; - endcase - end - always@(guard__h45160 or - sfd___3__h45150 or out_sfd__h45780 or _theResult___sfd__h45777) - begin - case (guard__h45160) - 2'b0, 2'b01: - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q57 = - sfd___3__h45150[54:3]; - 2'b10: - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q57 = - out_sfd__h45780; - 2'b11: - CASE_guard5160_0b0_sfd___35150_BITS_54_TO_3_0b_ETC__q57 = - _theResult___sfd__h45777; - endcase - end - always@(guard__h61080 or - _theResult___fst_exp__h69177 or _theResult___exp__h69703) - begin - case (guard__h61080) - 2'b0: - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q70 = - _theResult___fst_exp__h69177; - 2'b01, 2'b10, 2'b11: - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q70 = - _theResult___exp__h69703; - endcase - end - always@(requestR or - _theResult___fst_exp__h69177 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2146 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2144 or - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q70) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 = - _theResult___fst_exp__h69177; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2146; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2144; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 = - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q70; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2150 = - 8'd0; - endcase - end - always@(guard__h61080 or - _theResult___fst_exp__h69177 or - out_exp__h69706 or _theResult___exp__h69703) - begin - case (guard__h61080) - 2'b0, 2'b01: - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q71 = - _theResult___fst_exp__h69177; - 2'b10: - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q71 = - out_exp__h69706; - 2'b11: - CASE_guard1080_0b0_theResult___fst_exp9177_0b1_ETC__q71 = - _theResult___exp__h69703; - endcase - end - always@(guard__h69815 or - _theResult___fst_exp__h77863 or _theResult___exp__h78315) - begin - case (guard__h69815) - 2'b0: - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q72 = - _theResult___fst_exp__h77863; - 2'b01, 2'b10, 2'b11: - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q72 = - _theResult___exp__h78315; - endcase - end - always@(requestR or - _theResult___fst_exp__h77863 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2303 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2301 or - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q72) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 = - _theResult___fst_exp__h77863; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2303; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2301; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 = - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q72; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2307 = - 8'd0; - endcase - end - always@(guard__h69815 or - _theResult___fst_exp__h77863 or - out_exp__h78318 or _theResult___exp__h78315) - begin - case (guard__h69815) - 2'b0, 2'b01: - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q73 = - _theResult___fst_exp__h77863; - 2'b10: - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q73 = - out_exp__h78318; - 2'b11: - CASE_guard9815_0b0_theResult___fst_exp7863_0b1_ETC__q73 = - _theResult___exp__h78315; - endcase - end - always@(guard__h78804 or - _theResult___fst_exp__h87030 or _theResult___exp__h87556) - begin - case (guard__h78804) - 2'b0: - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q74 = - _theResult___fst_exp__h87030; - 2'b01, 2'b10, 2'b11: - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q74 = - _theResult___exp__h87556; - endcase - end - always@(requestR or - _theResult___fst_exp__h87030 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2630 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2628 or - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q74) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 = - _theResult___fst_exp__h87030; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2630; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2628; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 = - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q74; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2634 = - 8'd0; - endcase - end - always@(guard__h78804 or - _theResult___fst_exp__h87030 or - out_exp__h87559 or _theResult___exp__h87556) - begin - case (guard__h78804) - 2'b0, 2'b01: - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q75 = - _theResult___fst_exp__h87030; - 2'b10: - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q75 = - out_exp__h87559; - 2'b11: - CASE_guard8804_0b0_theResult___fst_exp7030_0b1_ETC__q75 = - _theResult___exp__h87556; - endcase - end - always@(guard__h87668 or - _theResult___fst_exp__h95745 or _theResult___exp__h96222) - begin - case (guard__h87668) - 2'b0: - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q76 = - _theResult___fst_exp__h95745; - 2'b01, 2'b10, 2'b11: - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q76 = - _theResult___exp__h96222; - endcase - end - always@(requestR or - _theResult___fst_exp__h95745 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2699 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2697 or - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q76) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 = - _theResult___fst_exp__h95745; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2699; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2697; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 = - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q76; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2703 = - 8'd0; - endcase - end - always@(guard__h87668 or - _theResult___fst_exp__h95745 or - out_exp__h96225 or _theResult___exp__h96222) - begin - case (guard__h87668) - 2'b0, 2'b01: - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q77 = - _theResult___fst_exp__h95745; - 2'b10: - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q77 = - out_exp__h96225; - 2'b11: - CASE_guard7668_0b0_theResult___fst_exp5745_0b1_ETC__q77 = - _theResult___exp__h96222; - endcase - end - always@(guard__h61080 or sfdin__h69171 or _theResult___sfd__h69704) - begin - case (guard__h61080) - 2'b0: - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q78 = - sfdin__h69171[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q78 = - _theResult___sfd__h69704; - endcase - end - always@(requestR or - sfdin__h69171 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2733 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2731 or - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q78) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 = - sfdin__h69171[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2733; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d2731; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 = - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q78; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2737 = - 23'd0; - endcase - end - always@(guard__h61080 or - sfdin__h69171 or out_sfd__h69707 or _theResult___sfd__h69704) - begin - case (guard__h61080) - 2'b0, 2'b01: - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q79 = - sfdin__h69171[56:34]; - 2'b10: - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q79 = - out_sfd__h69707; - 2'b11: - CASE_guard1080_0b0_sfdin9171_BITS_56_TO_34_0b1_ETC__q79 = - _theResult___sfd__h69704; - endcase - end - always@(guard__h69815 or - _theResult___snd__h77814 or _theResult___sfd__h78316) - begin - case (guard__h69815) - 2'b0: - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q80 = - _theResult___snd__h77814[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q80 = - _theResult___sfd__h78316; - endcase - end - always@(requestR or - _theResult___snd__h77814 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2752 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2750 or - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q80) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 = - _theResult___snd__h77814[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2752; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2750; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 = - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q80; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2756 = - 23'd0; - endcase - end - always@(guard__h69815 or - _theResult___snd__h77814 or - out_sfd__h78319 or _theResult___sfd__h78316) - begin - case (guard__h69815) - 2'b0, 2'b01: - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q81 = - _theResult___snd__h77814[56:34]; - 2'b10: - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q81 = - out_sfd__h78319; - 2'b11: - CASE_guard9815_0b0_theResult___snd7814_BITS_56_ETC__q81 = - _theResult___sfd__h78316; - endcase - end - always@(guard__h78804 or sfdin__h87024 or _theResult___sfd__h87557) - begin - case (guard__h78804) - 2'b0: - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q82 = - sfdin__h87024[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q82 = - _theResult___sfd__h87557; - endcase - end - always@(requestR or - sfdin__h87024 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2779 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2777 or - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q82) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 = - sfdin__h87024[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2779; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d2777; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 = - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q82; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2783 = - 23'd0; - endcase - end - always@(guard__h78804 or - sfdin__h87024 or out_sfd__h87560 or _theResult___sfd__h87557) - begin - case (guard__h78804) - 2'b0, 2'b01: - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q83 = - sfdin__h87024[56:34]; - 2'b10: - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q83 = - out_sfd__h87560; - 2'b11: - CASE_guard8804_0b0_sfdin7024_BITS_56_TO_34_0b1_ETC__q83 = - _theResult___sfd__h87557; - endcase - end - always@(guard__h87668 or - _theResult___snd__h95691 or _theResult___sfd__h96223) - begin - case (guard__h87668) - 2'b0: - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q84 = - _theResult___snd__h95691[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q84 = - _theResult___sfd__h96223; - endcase - end - always@(requestR or - _theResult___snd__h95691 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2798 or - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2796 or - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q84) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 = - _theResult___snd__h95691[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2798; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 = - IF_IF_IF_requestR_3_BITS_190_TO_180_609_EQ_0_6_ETC___d2796; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 = - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q84; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2802 = - 23'd0; - endcase - end - always@(guard__h87668 or - _theResult___snd__h95691 or - out_sfd__h96226 or _theResult___sfd__h96223) - begin - case (guard__h87668) - 2'b0, 2'b01: - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q85 = - _theResult___snd__h95691[56:34]; - 2'b10: - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q85 = - out_sfd__h96226; - 2'b11: - CASE_guard7668_0b0_theResult___snd5691_BITS_56_ETC__q85 = - _theResult___sfd__h96223; - endcase - end - always@(guard__h61080 or requestR) - begin - case (guard__h61080) - 2'b0, 2'b01, 2'b10: - CASE_guard1080_0b0_requestR_BIT_191_0b1_reques_ETC__q86 = - requestR[191]; - 2'd3: - CASE_guard1080_0b0_requestR_BIT_191_0b1_reques_ETC__q86 = - guard__h61080 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h61080) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 = - (guard__h61080 == 2'b0) ? - requestR[191] : - (guard__h61080 == 2'b01 || guard__h61080 == 2'b10 || - guard__h61080 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h69815 or requestR) - begin - case (guard__h69815) - 2'b0, 2'b01, 2'b10: - CASE_guard9815_0b0_requestR_BIT_191_0b1_reques_ETC__q88 = - requestR[191]; - 2'd3: - CASE_guard9815_0b0_requestR_BIT_191_0b1_reques_ETC__q88 = - guard__h69815 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h69815) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 = - (guard__h69815 == 2'b0) ? - requestR[191] : - (guard__h69815 == 2'b01 || guard__h69815 == 2'b10 || - guard__h69815 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h78804 or requestR) - begin - case (guard__h78804) - 2'b0, 2'b01, 2'b10: - CASE_guard8804_0b0_requestR_BIT_191_0b1_reques_ETC__q90 = - requestR[191]; - 2'd3: - CASE_guard8804_0b0_requestR_BIT_191_0b1_reques_ETC__q90 = - guard__h78804 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h78804) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 = - (guard__h78804 == 2'b0) ? - requestR[191] : - (guard__h78804 == 2'b01 || guard__h78804 == 2'b10 || - guard__h78804 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h87668 or requestR) - begin - case (guard__h87668) - 2'b0, 2'b01, 2'b10: - CASE_guard7668_0b0_requestR_BIT_191_0b1_reques_ETC__q92 = - requestR[191]; - 2'd3: - CASE_guard7668_0b0_requestR_BIT_191_0b1_reques_ETC__q92 = - guard__h87668 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h87668) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 = - (guard__h87668 == 2'b0) ? - requestR[191] : - (guard__h87668 == 2'b01 || guard__h87668 == 2'b10 || - guard__h87668 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h110776 or - _theResult___fst_exp__h118737 or _theResult___exp__h119392) - begin - case (guard__h110776) - 2'b0: - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q102 = - _theResult___fst_exp__h118737; - 2'b01, 2'b10, 2'b11: - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q102 = - _theResult___exp__h119392; - endcase - end - always@(requestR or - _theResult___fst_exp__h118737 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3140 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3138 or - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q102) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 = - _theResult___fst_exp__h118737; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3140; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3138; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 = - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q102; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3144 = - 11'd0; - endcase - end - always@(guard__h110776 or - _theResult___fst_exp__h118737 or - out_exp__h119395 or _theResult___exp__h119392) - begin - case (guard__h110776) - 2'b0, 2'b01: - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q103 = - _theResult___fst_exp__h118737; - 2'b10: - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q103 = - out_exp__h119395; - 2'b11: - CASE_guard10776_0b0_theResult___fst_exp18737_0_ETC__q103 = - _theResult___exp__h119392; - endcase - end - always@(guard__h120084 or - _theResult___fst_exp__h128310 or _theResult___exp__h129039) - begin - case (guard__h120084) - 2'b0: - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q104 = - _theResult___fst_exp__h128310; - 2'b01, 2'b10, 2'b11: - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q104 = - _theResult___exp__h129039; - endcase - end - always@(requestR or - _theResult___fst_exp__h128310 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3465 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3463 or - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q104) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 = - _theResult___fst_exp__h128310; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3465; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3463; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 = - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q104; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3469 = - 11'd0; - endcase - end - always@(guard__h120084 or - _theResult___fst_exp__h128310 or - out_exp__h129042 or _theResult___exp__h129039) - begin - case (guard__h120084) - 2'b0, 2'b01: - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q105 = - _theResult___fst_exp__h128310; - 2'b10: - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q105 = - out_exp__h129042; - 2'b11: - CASE_guard20084_0b0_theResult___fst_exp28310_0_ETC__q105 = - _theResult___exp__h129039; - endcase - end - always@(guard__h129151 or - _theResult___fst_exp__h137141 or _theResult___exp__h137821) - begin - case (guard__h129151) - 2'b0: - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q106 = - _theResult___fst_exp__h137141; - 2'b01, 2'b10, 2'b11: - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q106 = - _theResult___exp__h137821; - endcase - end - always@(requestR or - _theResult___fst_exp__h137141 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3534 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3532 or - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q106) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 = - _theResult___fst_exp__h137141; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3534; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3532; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 = - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q106; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3538 = - 11'd0; - endcase - end - always@(guard__h129151 or - _theResult___fst_exp__h137141 or - out_exp__h137824 or _theResult___exp__h137821) - begin - case (guard__h129151) - 2'b0, 2'b01: - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q107 = - _theResult___fst_exp__h137141; - 2'b10: - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q107 = - out_exp__h137824; - 2'b11: - CASE_guard29151_0b0_theResult___fst_exp37141_0_ETC__q107 = - _theResult___exp__h137821; - endcase - end - always@(guard__h110776 or requestR) - begin - case (guard__h110776) - 2'b0, 2'b01, 2'b10: - CASE_guard10776_0b0_requestR_BITS_191_TO_160_E_ETC__q108 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard10776_0b0_requestR_BITS_191_TO_160_E_ETC__q108 = - guard__h110776 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h110776) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 = - (guard__h110776 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h110776 == 2'b01 || guard__h110776 == 2'b10 || - guard__h110776 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h120084 or requestR) - begin - case (guard__h120084) - 2'b0, 2'b01, 2'b10: - CASE_guard20084_0b0_requestR_BITS_191_TO_160_E_ETC__q110 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard20084_0b0_requestR_BITS_191_TO_160_E_ETC__q110 = - guard__h120084 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h120084) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 = - (guard__h120084 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h120084 == 2'b01 || guard__h120084 == 2'b10 || - guard__h120084 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h129151 or requestR) - begin - case (guard__h129151) - 2'b0, 2'b01, 2'b10: - CASE_guard29151_0b0_requestR_BITS_191_TO_160_E_ETC__q112 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard29151_0b0_requestR_BITS_191_TO_160_E_ETC__q112 = - guard__h129151 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h129151) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 = - (guard__h129151 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h129151 == 2'b01 || guard__h129151 == 2'b10 || - guard__h129151 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h110776 or - _theResult___snd__h118688 or _theResult___sfd__h119393) - begin - case (guard__h110776) - 2'b0: - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q114 = - _theResult___snd__h118688[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q114 = - _theResult___sfd__h119393; - endcase - end - always@(requestR or - _theResult___snd__h118688 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3567 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3565 or - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q114) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 = - _theResult___snd__h118688[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3567; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3565; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 = - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q114; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3571 = - 52'd0; - endcase - end - always@(guard__h110776 or - _theResult___snd__h118688 or - out_sfd__h119396 or _theResult___sfd__h119393) - begin - case (guard__h110776) - 2'b0, 2'b01: - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q115 = - _theResult___snd__h118688[56:5]; - 2'b10: - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q115 = - out_sfd__h119396; - 2'b11: - CASE_guard10776_0b0_theResult___snd18688_BITS__ETC__q115 = - _theResult___sfd__h119393; - endcase - end - always@(guard__h120084 or sfdin__h128304 or _theResult___sfd__h129040) - begin - case (guard__h120084) - 2'b0: - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q116 = - sfdin__h128304[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q116 = - _theResult___sfd__h129040; - endcase - end - always@(requestR or - sfdin__h128304 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3594 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3592 or - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q116) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 = - sfdin__h128304[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3594; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d3592; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 = - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q116; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3598 = - 52'd0; - endcase - end - always@(guard__h120084 or - sfdin__h128304 or out_sfd__h129043 or _theResult___sfd__h129040) - begin - case (guard__h120084) - 2'b0, 2'b01: - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q117 = - sfdin__h128304[56:5]; - 2'b10: - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q117 = - out_sfd__h129043; - 2'b11: - CASE_guard20084_0b0_sfdin28304_BITS_56_TO_5_0b_ETC__q117 = - _theResult___sfd__h129040; - endcase - end - always@(guard__h129151 or - _theResult___snd__h137087 or _theResult___sfd__h137822) - begin - case (guard__h129151) - 2'b0: - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q118 = - _theResult___snd__h137087[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q118 = - _theResult___sfd__h137822; - endcase - end - always@(requestR or - _theResult___snd__h137087 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3613 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3611 or - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q118) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 = - _theResult___snd__h137087[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3613; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d3611; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 = - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q118; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3617 = - 52'd0; - endcase - end - always@(guard__h129151 or - _theResult___snd__h137087 or - out_sfd__h137825 or _theResult___sfd__h137822) - begin - case (guard__h129151) - 2'b0, 2'b01: - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q119 = - _theResult___snd__h137087[56:5]; - 2'b10: - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q119 = - out_sfd__h137825; - 2'b11: - CASE_guard29151_0b0_theResult___snd37087_BITS__ETC__q119 = - _theResult___sfd__h137822; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - stateR <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (stateR$EN) stateR <= `BSV_ASSIGNMENT_DELAY stateR$D_IN; - end - if (requestR$EN) requestR <= `BSV_ASSIGNMENT_DELAY requestR$D_IN; - if (resultR$EN) resultR <= `BSV_ASSIGNMENT_DELAY resultR$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - requestR = 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - resultR = 70'h2AAAAAAAAAAAAAAAAA; - stateR = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkFBox_Core - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Top.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Top.v deleted file mode 100644 index 916b8699..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Top.v +++ /dev/null @@ -1,184 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// valid O 1 -// word_fst O 64 -// word_snd O 5 -// CLK I 1 clock -// RST_N I 1 reset -// req_opcode I 7 -// req_f7 I 7 -// req_rm I 3 -// req_rs2 I 5 -// req_v1 I 64 -// req_v2 I 64 -// req_v3 I 64 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFBox_Top(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_opcode, - req_f7, - req_rm, - req_rs2, - req_v1, - req_v2, - req_v3, - EN_req, - - valid, - - word_fst, - - word_snd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [6 : 0] req_opcode; - input [6 : 0] req_f7; - input [2 : 0] req_rm; - input [4 : 0] req_rs2; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input [63 : 0] req_v3; - input EN_req; - - // value method valid - output valid; - - // value method word_fst - output [63 : 0] word_fst; - - // value method word_snd - output [4 : 0] word_snd; - - // signals for module outputs - wire [63 : 0] word_fst; - wire [4 : 0] word_snd; - wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid; - - // ports of submodule fbox_core - wire [63 : 0] fbox_core$req_v1, - fbox_core$req_v2, - fbox_core$req_v3, - fbox_core$word_fst; - wire [6 : 0] fbox_core$req_f7, fbox_core$req_opcode; - wire [4 : 0] fbox_core$req_rs2, fbox_core$word_snd; - wire [2 : 0] fbox_core$req_rm; - wire fbox_core$EN_req, - fbox_core$EN_server_reset_request_put, - fbox_core$EN_server_reset_response_get, - fbox_core$RDY_server_reset_request_put, - fbox_core$RDY_server_reset_response_get, - fbox_core$valid; - - // rule scheduling signals - wire CAN_FIRE_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = - fbox_core$RDY_server_reset_request_put ; - assign CAN_FIRE_server_reset_request_put = - fbox_core$RDY_server_reset_request_put ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - fbox_core$RDY_server_reset_response_get ; - assign CAN_FIRE_server_reset_response_get = - fbox_core$RDY_server_reset_response_get ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = fbox_core$valid ; - - // value method word_fst - assign word_fst = fbox_core$word_fst ; - - // value method word_snd - assign word_snd = fbox_core$word_snd ; - - // submodule fbox_core - mkFBox_Core fbox_core(.CLK(CLK), - .RST_N(RST_N), - .req_f7(fbox_core$req_f7), - .req_opcode(fbox_core$req_opcode), - .req_rm(fbox_core$req_rm), - .req_rs2(fbox_core$req_rs2), - .req_v1(fbox_core$req_v1), - .req_v2(fbox_core$req_v2), - .req_v3(fbox_core$req_v3), - .EN_server_reset_request_put(fbox_core$EN_server_reset_request_put), - .EN_server_reset_response_get(fbox_core$EN_server_reset_response_get), - .EN_req(fbox_core$EN_req), - .RDY_server_reset_request_put(fbox_core$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fbox_core$RDY_server_reset_response_get), - .valid(fbox_core$valid), - .word_fst(fbox_core$word_fst), - .word_snd(fbox_core$word_snd)); - - // submodule fbox_core - assign fbox_core$req_f7 = req_f7 ; - assign fbox_core$req_opcode = req_opcode ; - assign fbox_core$req_rm = req_rm ; - assign fbox_core$req_rs2 = req_rs2 ; - assign fbox_core$req_v1 = req_v1 ; - assign fbox_core$req_v2 = req_v2 ; - assign fbox_core$req_v3 = req_v3 ; - assign fbox_core$EN_server_reset_request_put = EN_server_reset_request_put ; - assign fbox_core$EN_server_reset_response_get = - EN_server_reset_response_get ; - assign fbox_core$EN_req = EN_req ; -endmodule // mkFBox_Top - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPR_RegFile.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPR_RegFile.v deleted file mode 100644 index ae1589d4..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPR_RegFile.v +++ /dev/null @@ -1,258 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 64 -// read_rs1_port2 O 64 -// read_rs2 O 64 -// read_rs3 O 64 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// read_rs3_rs3 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - read_rs3_rs3, - read_rs3, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [63 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [63 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [63 : 0] read_rs2; - - // value method read_rs3 - input [4 : 0] read_rs3_rs3; - output [63 : 0] read_rs3; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [63 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [63 : 0] read_rs1, read_rs1_port2, read_rs2, read_rs3; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [63 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3, - regfile$D_OUT_4; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = regfile$D_OUT_4 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = regfile$D_OUT_3 ; - - // value method read_rs2 - assign read_rs2 = regfile$D_OUT_2 ; - - // value method read_rs3 - assign read_rs3 = regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd64), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(regfile$D_OUT_4), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs3_rs3 ; - assign regfile$ADDR_2 = read_rs2_rs2 ; - assign regfile$ADDR_3 = read_rs1_port2_rs1 ; - assign regfile$ADDR_4 = read_rs1_rs1 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkFPR_RegFile - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPU.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPU.v deleted file mode 100644 index ec7dfc10..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPU.v +++ /dev/null @@ -1,12705 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_core_request_put O 1 reg -// server_core_response_get O 70 reg -// RDY_server_core_response_get O 1 reg -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// server_core_request_put I 202 reg -// EN_server_core_request_put I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_server_core_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFPU(CLK, - RST_N, - - server_core_request_put, - EN_server_core_request_put, - RDY_server_core_request_put, - - EN_server_core_response_get, - server_core_response_get, - RDY_server_core_response_get, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get); - input CLK; - input RST_N; - - // action method server_core_request_put - input [201 : 0] server_core_request_put; - input EN_server_core_request_put; - output RDY_server_core_request_put; - - // actionvalue method server_core_response_get - input EN_server_core_response_get; - output [69 : 0] server_core_response_get; - output RDY_server_core_response_get; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // signals for module outputs - wire [69 : 0] server_core_response_get; - wire RDY_server_core_request_put, - RDY_server_core_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get; - - // inlined wires - reg [68 : 0] resWire$wget; - wire crg_done$EN_port0__write, - crg_done$EN_port1__write, - crg_done$port1__read, - crg_done$port2__read, - crg_done_1$EN_port0__write, - crg_done_1$EN_port1__write, - crg_done_1$port1__read, - crg_done_1$port2__read, - resWire$whas; - - // register crg_done - reg crg_done; - wire crg_done$D_IN, crg_done$EN; - - // register crg_done_1 - reg crg_done_1; - wire crg_done_1$D_IN, crg_done_1$EN; - - // register rg_b - reg [115 : 0] rg_b; - wire [115 : 0] rg_b$D_IN; - wire rg_b$EN; - - // register rg_busy - reg rg_busy; - wire rg_busy$D_IN, rg_busy$EN; - - // register rg_busy_1 - reg rg_busy_1; - wire rg_busy_1$D_IN, rg_busy_1$EN; - - // register rg_d - reg [57 : 0] rg_d; - wire [57 : 0] rg_d$D_IN; - wire rg_d$EN; - - // register rg_index - reg [5 : 0] rg_index; - wire [5 : 0] rg_index$D_IN; - wire rg_index$EN; - - // register rg_index_1 - reg [5 : 0] rg_index_1; - wire [5 : 0] rg_index_1$D_IN; - wire rg_index_1$EN; - - // register rg_q - reg [57 : 0] rg_q; - wire [57 : 0] rg_q$D_IN; - wire rg_q$EN; - - // register rg_r - reg [115 : 0] rg_r; - wire [115 : 0] rg_r$D_IN; - wire rg_r$EN; - - // register rg_r_1 - reg [115 : 0] rg_r_1; - wire [115 : 0] rg_r_1$D_IN; - wire rg_r_1$EN; - - // register rg_res - reg [116 : 0] rg_res; - wire [116 : 0] rg_res$D_IN; - wire rg_res$EN; - - // register rg_s - reg [115 : 0] rg_s; - wire [115 : 0] rg_s$D_IN; - wire rg_s$EN; - - // ports of submodule fpu_div64_fOperands_S0 - wire [130 : 0] fpu_div64_fOperands_S0$D_IN, fpu_div64_fOperands_S0$D_OUT; - wire fpu_div64_fOperands_S0$CLR, - fpu_div64_fOperands_S0$DEQ, - fpu_div64_fOperands_S0$EMPTY_N, - fpu_div64_fOperands_S0$ENQ, - fpu_div64_fOperands_S0$FULL_N; - - // ports of submodule fpu_div64_fResult_S5 - wire [68 : 0] fpu_div64_fResult_S5$D_IN, fpu_div64_fResult_S5$D_OUT; - wire fpu_div64_fResult_S5$CLR, - fpu_div64_fResult_S5$DEQ, - fpu_div64_fResult_S5$EMPTY_N, - fpu_div64_fResult_S5$ENQ, - fpu_div64_fResult_S5$FULL_N; - - // ports of submodule fpu_div64_fState_S1 - wire [318 : 0] fpu_div64_fState_S1$D_IN, fpu_div64_fState_S1$D_OUT; - wire fpu_div64_fState_S1$CLR, - fpu_div64_fState_S1$DEQ, - fpu_div64_fState_S1$EMPTY_N, - fpu_div64_fState_S1$ENQ, - fpu_div64_fState_S1$FULL_N; - - // ports of submodule fpu_div64_fState_S2 - wire [147 : 0] fpu_div64_fState_S2$D_IN, fpu_div64_fState_S2$D_OUT; - wire fpu_div64_fState_S2$CLR, - fpu_div64_fState_S2$DEQ, - fpu_div64_fState_S2$EMPTY_N, - fpu_div64_fState_S2$ENQ, - fpu_div64_fState_S2$FULL_N; - - // ports of submodule fpu_div64_fState_S3 - wire [194 : 0] fpu_div64_fState_S3$D_IN, fpu_div64_fState_S3$D_OUT; - wire fpu_div64_fState_S3$CLR, - fpu_div64_fState_S3$DEQ, - fpu_div64_fState_S3$EMPTY_N, - fpu_div64_fState_S3$ENQ, - fpu_div64_fState_S3$FULL_N; - - // ports of submodule fpu_div64_fState_S4 - wire [138 : 0] fpu_div64_fState_S4$D_IN, fpu_div64_fState_S4$D_OUT; - wire fpu_div64_fState_S4$CLR, - fpu_div64_fState_S4$DEQ, - fpu_div64_fState_S4$EMPTY_N, - fpu_div64_fState_S4$ENQ, - fpu_div64_fState_S4$FULL_N; - - // ports of submodule fpu_madd_fOperand_S0 - wire [195 : 0] fpu_madd_fOperand_S0$D_IN, fpu_madd_fOperand_S0$D_OUT; - wire fpu_madd_fOperand_S0$CLR, - fpu_madd_fOperand_S0$DEQ, - fpu_madd_fOperand_S0$EMPTY_N, - fpu_madd_fOperand_S0$ENQ, - fpu_madd_fOperand_S0$FULL_N; - - // ports of submodule fpu_madd_fProd_S2 - wire [105 : 0] fpu_madd_fProd_S2$D_IN, fpu_madd_fProd_S2$D_OUT; - wire fpu_madd_fProd_S2$CLR, - fpu_madd_fProd_S2$DEQ, - fpu_madd_fProd_S2$EMPTY_N, - fpu_madd_fProd_S2$ENQ, - fpu_madd_fProd_S2$FULL_N; - - // ports of submodule fpu_madd_fProd_S3 - wire [105 : 0] fpu_madd_fProd_S3$D_IN, fpu_madd_fProd_S3$D_OUT; - wire fpu_madd_fProd_S3$CLR, - fpu_madd_fProd_S3$DEQ, - fpu_madd_fProd_S3$EMPTY_N, - fpu_madd_fProd_S3$ENQ, - fpu_madd_fProd_S3$FULL_N; - - // ports of submodule fpu_madd_fResult_S9 - wire [68 : 0] fpu_madd_fResult_S9$D_IN, fpu_madd_fResult_S9$D_OUT; - wire fpu_madd_fResult_S9$CLR, - fpu_madd_fResult_S9$DEQ, - fpu_madd_fResult_S9$EMPTY_N, - fpu_madd_fResult_S9$ENQ, - fpu_madd_fResult_S9$FULL_N; - - // ports of submodule fpu_madd_fState_S1 - wire [257 : 0] fpu_madd_fState_S1$D_IN, fpu_madd_fState_S1$D_OUT; - wire fpu_madd_fState_S1$CLR, - fpu_madd_fState_S1$DEQ, - fpu_madd_fState_S1$EMPTY_N, - fpu_madd_fState_S1$ENQ, - fpu_madd_fState_S1$FULL_N; - - // ports of submodule fpu_madd_fState_S2 - wire [151 : 0] fpu_madd_fState_S2$D_IN, fpu_madd_fState_S2$D_OUT; - wire fpu_madd_fState_S2$CLR, - fpu_madd_fState_S2$DEQ, - fpu_madd_fState_S2$EMPTY_N, - fpu_madd_fState_S2$ENQ, - fpu_madd_fState_S2$FULL_N; - - // ports of submodule fpu_madd_fState_S3 - wire [151 : 0] fpu_madd_fState_S3$D_IN, fpu_madd_fState_S3$D_OUT; - wire fpu_madd_fState_S3$CLR, - fpu_madd_fState_S3$DEQ, - fpu_madd_fState_S3$EMPTY_N, - fpu_madd_fState_S3$ENQ, - fpu_madd_fState_S3$FULL_N; - - // ports of submodule fpu_madd_fState_S4 - wire [203 : 0] fpu_madd_fState_S4$D_IN, fpu_madd_fState_S4$D_OUT; - wire fpu_madd_fState_S4$CLR, - fpu_madd_fState_S4$DEQ, - fpu_madd_fState_S4$EMPTY_N, - fpu_madd_fState_S4$ENQ, - fpu_madd_fState_S4$FULL_N; - - // ports of submodule fpu_madd_fState_S5 - wire [215 : 0] fpu_madd_fState_S5$D_IN, fpu_madd_fState_S5$D_OUT; - wire fpu_madd_fState_S5$CLR, - fpu_madd_fState_S5$DEQ, - fpu_madd_fState_S5$EMPTY_N, - fpu_madd_fState_S5$ENQ, - fpu_madd_fState_S5$FULL_N; - - // ports of submodule fpu_madd_fState_S6 - wire [202 : 0] fpu_madd_fState_S6$D_IN, fpu_madd_fState_S6$D_OUT; - wire fpu_madd_fState_S6$CLR, - fpu_madd_fState_S6$DEQ, - fpu_madd_fState_S6$EMPTY_N, - fpu_madd_fState_S6$ENQ, - fpu_madd_fState_S6$FULL_N; - - // ports of submodule fpu_madd_fState_S7 - wire [202 : 0] fpu_madd_fState_S7$D_IN, fpu_madd_fState_S7$D_OUT; - wire fpu_madd_fState_S7$CLR, - fpu_madd_fState_S7$DEQ, - fpu_madd_fState_S7$EMPTY_N, - fpu_madd_fState_S7$ENQ, - fpu_madd_fState_S7$FULL_N; - - // ports of submodule fpu_madd_fState_S8 - wire [140 : 0] fpu_madd_fState_S8$D_IN, fpu_madd_fState_S8$D_OUT; - wire fpu_madd_fState_S8$CLR, - fpu_madd_fState_S8$DEQ, - fpu_madd_fState_S8$EMPTY_N, - fpu_madd_fState_S8$ENQ, - fpu_madd_fState_S8$FULL_N; - - // ports of submodule fpu_sqr64_fOperand_S0 - wire [66 : 0] fpu_sqr64_fOperand_S0$D_IN, fpu_sqr64_fOperand_S0$D_OUT; - wire fpu_sqr64_fOperand_S0$CLR, - fpu_sqr64_fOperand_S0$DEQ, - fpu_sqr64_fOperand_S0$EMPTY_N, - fpu_sqr64_fOperand_S0$ENQ, - fpu_sqr64_fOperand_S0$FULL_N; - - // ports of submodule fpu_sqr64_fResult_S5 - wire [68 : 0] fpu_sqr64_fResult_S5$D_IN, fpu_sqr64_fResult_S5$D_OUT; - wire fpu_sqr64_fResult_S5$CLR, - fpu_sqr64_fResult_S5$DEQ, - fpu_sqr64_fResult_S5$EMPTY_N, - fpu_sqr64_fResult_S5$ENQ, - fpu_sqr64_fResult_S5$FULL_N; - - // ports of submodule fpu_sqr64_fState_S1 - wire [194 : 0] fpu_sqr64_fState_S1$D_IN, fpu_sqr64_fState_S1$D_OUT; - wire fpu_sqr64_fState_S1$CLR, - fpu_sqr64_fState_S1$DEQ, - fpu_sqr64_fState_S1$EMPTY_N, - fpu_sqr64_fState_S1$ENQ, - fpu_sqr64_fState_S1$FULL_N; - - // ports of submodule fpu_sqr64_fState_S2 - wire [136 : 0] fpu_sqr64_fState_S2$D_IN, fpu_sqr64_fState_S2$D_OUT; - wire fpu_sqr64_fState_S2$CLR, - fpu_sqr64_fState_S2$DEQ, - fpu_sqr64_fState_S2$EMPTY_N, - fpu_sqr64_fState_S2$ENQ, - fpu_sqr64_fState_S2$FULL_N; - - // ports of submodule fpu_sqr64_fState_S3 - wire [195 : 0] fpu_sqr64_fState_S3$D_IN, fpu_sqr64_fState_S3$D_OUT; - wire fpu_sqr64_fState_S3$CLR, - fpu_sqr64_fState_S3$DEQ, - fpu_sqr64_fState_S3$EMPTY_N, - fpu_sqr64_fState_S3$ENQ, - fpu_sqr64_fState_S3$FULL_N; - - // ports of submodule fpu_sqr64_fState_S4 - wire [138 : 0] fpu_sqr64_fState_S4$D_IN, fpu_sqr64_fState_S4$D_OUT; - wire fpu_sqr64_fState_S4$CLR, - fpu_sqr64_fState_S4$DEQ, - fpu_sqr64_fState_S4$EMPTY_N, - fpu_sqr64_fState_S4$ENQ, - fpu_sqr64_fState_S4$FULL_N; - - // ports of submodule iFifo - wire [201 : 0] iFifo$D_IN, iFifo$D_OUT; - wire iFifo$CLR, iFifo$DEQ, iFifo$EMPTY_N, iFifo$ENQ, iFifo$FULL_N; - - // ports of submodule isDoubleFifo - wire isDoubleFifo$CLR, - isDoubleFifo$DEQ, - isDoubleFifo$D_IN, - isDoubleFifo$D_OUT, - isDoubleFifo$EMPTY_N, - isDoubleFifo$ENQ, - isDoubleFifo$FULL_N; - - // ports of submodule isNegateFifo - wire isNegateFifo$CLR, - isNegateFifo$DEQ, - isNegateFifo$D_IN, - isNegateFifo$D_OUT, - isNegateFifo$EMPTY_N, - isNegateFifo$ENQ, - isNegateFifo$FULL_N; - - // ports of submodule oFifo - wire [69 : 0] oFifo$D_IN, oFifo$D_OUT; - wire oFifo$CLR, oFifo$DEQ, oFifo$EMPTY_N, oFifo$ENQ, oFifo$FULL_N; - - // ports of submodule resetReqsF - wire resetReqsF$CLR, - resetReqsF$DEQ, - resetReqsF$EMPTY_N, - resetReqsF$ENQ, - resetReqsF$FULL_N; - - // ports of submodule resetRspsF - wire resetRspsF$CLR, - resetRspsF$DEQ, - resetRspsF$EMPTY_N, - resetRspsF$ENQ, - resetRspsF$FULL_N; - - // ports of submodule rmdFifo - wire [2 : 0] rmdFifo$D_IN, rmdFifo$D_OUT; - wire rmdFifo$CLR, rmdFifo$DEQ, rmdFifo$EMPTY_N, rmdFifo$ENQ, rmdFifo$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_fpu_div64_s1_stage, - CAN_FIRE_RL_fpu_div64_s2_stage, - CAN_FIRE_RL_fpu_div64_s3_stage, - CAN_FIRE_RL_fpu_div64_s4_stage, - CAN_FIRE_RL_fpu_div64_s5_stage, - CAN_FIRE_RL_fpu_madd_s1_stage, - CAN_FIRE_RL_fpu_madd_s2_stage, - CAN_FIRE_RL_fpu_madd_s3_stage, - CAN_FIRE_RL_fpu_madd_s4_stage, - CAN_FIRE_RL_fpu_madd_s5_stage, - CAN_FIRE_RL_fpu_madd_s6_stage, - CAN_FIRE_RL_fpu_madd_s7_stage, - CAN_FIRE_RL_fpu_madd_s8_stage, - CAN_FIRE_RL_fpu_madd_s9_stage, - CAN_FIRE_RL_fpu_sqr64_s1_stage, - CAN_FIRE_RL_fpu_sqr64_s2_stage, - CAN_FIRE_RL_fpu_sqr64_s3_stage, - CAN_FIRE_RL_fpu_sqr64_s4_stage, - CAN_FIRE_RL_fpu_sqr64_s5_stage, - CAN_FIRE_RL_getResDiv, - CAN_FIRE_RL_getResMAdd, - CAN_FIRE_RL_getResSqr, - CAN_FIRE_RL_passResult, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_start_op, - CAN_FIRE_RL_work, - CAN_FIRE_RL_work_1, - CAN_FIRE___me_check_22, - CAN_FIRE___me_check_23, - CAN_FIRE_server_core_request_put, - CAN_FIRE_server_core_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_RL_fpu_div64_s1_stage, - WILL_FIRE_RL_fpu_div64_s2_stage, - WILL_FIRE_RL_fpu_div64_s3_stage, - WILL_FIRE_RL_fpu_div64_s4_stage, - WILL_FIRE_RL_fpu_div64_s5_stage, - WILL_FIRE_RL_fpu_madd_s1_stage, - WILL_FIRE_RL_fpu_madd_s2_stage, - WILL_FIRE_RL_fpu_madd_s3_stage, - WILL_FIRE_RL_fpu_madd_s4_stage, - WILL_FIRE_RL_fpu_madd_s5_stage, - WILL_FIRE_RL_fpu_madd_s6_stage, - WILL_FIRE_RL_fpu_madd_s7_stage, - WILL_FIRE_RL_fpu_madd_s8_stage, - WILL_FIRE_RL_fpu_madd_s9_stage, - WILL_FIRE_RL_fpu_sqr64_s1_stage, - WILL_FIRE_RL_fpu_sqr64_s2_stage, - WILL_FIRE_RL_fpu_sqr64_s3_stage, - WILL_FIRE_RL_fpu_sqr64_s4_stage, - WILL_FIRE_RL_fpu_sqr64_s5_stage, - WILL_FIRE_RL_getResDiv, - WILL_FIRE_RL_getResMAdd, - WILL_FIRE_RL_getResSqr, - WILL_FIRE_RL_passResult, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_start_op, - WILL_FIRE_RL_work, - WILL_FIRE_RL_work_1, - WILL_FIRE___me_check_22, - WILL_FIRE___me_check_23, - WILL_FIRE_server_core_request_put, - WILL_FIRE_server_core_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // inputs to muxes for submodule ports - wire [116 : 0] MUX_rg_res$write_1__VAL_2; - wire [115 : 0] MUX_rg_b$write_1__VAL_1, - MUX_rg_b$write_1__VAL_2, - MUX_rg_r$write_1__VAL_1, - MUX_rg_r$write_1__VAL_2, - MUX_rg_r_1$write_1__VAL_2, - MUX_rg_s$write_1__VAL_1, - MUX_rg_s$write_1__VAL_2; - wire [57 : 0] MUX_rg_d$write_1__VAL_1, MUX_rg_q$write_1__VAL_2; - wire [5 : 0] MUX_rg_index$write_1__VAL_2, MUX_rg_index_1$write_1__VAL_2; - wire MUX_crg_done$port1__write_1__SEL_1, - MUX_crg_done$port1__write_1__SEL_2, - MUX_crg_done_1$port1__write_1__SEL_1, - MUX_crg_done_1$port1__write_1__SEL_2; - - // remaining internal signals - reg [63 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183, - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177, - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623; - reg [62 : 0] CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131, - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179; - reg [51 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4, - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110, - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111, - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112, - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113, - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75, - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76, - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77, - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78, - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79, - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80, - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48, - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49, - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50, - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51, - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52, - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53, - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108, - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109, - _theResult___fst_sfd__h142620, - _theResult___fst_sfd__h148292, - _theResult___fst_sfd__h164060, - _theResult___fst_sfd__h173650, - _theResult___fst_sfd__h182402, - _theResult___fst_sfd__h186932, - _theResult___fst_sfd__h19468, - _theResult___fst_sfd__h19957, - _theResult___fst_sfd__h202698, - _theResult___fst_sfd__h212288, - _theResult___fst_sfd__h221040, - _theResult___fst_sfd__h225871, - _theResult___fst_sfd__h241637, - _theResult___fst_sfd__h251227, - _theResult___fst_sfd__h259979, - _theResult___fst_sfd__h43554, - _theResult___fst_sfd__h95988; - reg [22 : 0] CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162, - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163, - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160, - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161, - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164, - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165, - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166, - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167, - _theResult___fst_sfd__h269560, - _theResult___fst_sfd__h278281, - _theResult___fst_sfd__h286863, - _theResult___fst_sfd__h296047, - _theResult___fst_sfd__h304683; - reg [10 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22, - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104, - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105, - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106, - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107, - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69, - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70, - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71, - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72, - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73, - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74, - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42, - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43, - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44, - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45, - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46, - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47, - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102, - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103, - _theResult___fst_exp__h142619, - _theResult___fst_exp__h148291, - _theResult___fst_exp__h164059, - _theResult___fst_exp__h173649, - _theResult___fst_exp__h182401, - _theResult___fst_exp__h186931, - _theResult___fst_exp__h19467, - _theResult___fst_exp__h202697, - _theResult___fst_exp__h212287, - _theResult___fst_exp__h221039, - _theResult___fst_exp__h225870, - _theResult___fst_exp__h241636, - _theResult___fst_exp__h251226, - _theResult___fst_exp__h259978, - _theResult___fst_exp__h43553, - _theResult___fst_exp__h95987; - reg [7 : 0] CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154, - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155, - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152, - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153, - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156, - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157, - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158, - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159, - _theResult___fst_exp__h269559, - _theResult___fst_exp__h278280, - _theResult___fst_exp__h286862, - _theResult___fst_exp__h296046, - _theResult___fst_exp__h304682; - reg CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9, - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126, - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178, - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122, - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116, - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124, - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118, - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87, - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81, - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89, - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83, - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91, - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85, - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54, - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56, - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145, - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144, - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58, - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147, - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146, - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149, - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148, - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120, - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114, - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151, - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348, - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028, - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418; - wire [194 : 0] IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212; - wire [139 : 0] IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595; - wire [118 : 0] IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959; - wire [115 : 0] IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83, - IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22, - IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72, - _theResult___fst__h1476, - _theResult___fst__h1515, - _theResult___fst__h1600, - _theResult___snd_fst__h1478, - _theResult___snd_fst__h1517, - _theResult___snd_fst__h1602, - _theResult___snd_snd__h1649, - _theResult___snd_snd__h1715, - _theResult___snd_snd_snd__h1481, - _theResult___snd_snd_snd__h1520, - _theResult___snd_snd_snd__h1605, - b___1__h77160, - b__h1608, - b__h1712, - b__h32583, - r__h1659, - r__h1663, - r__h1724, - r__h1753, - s__h1658, - s__h1723, - sum__h1606, - sum__h1710, - value__h32541, - x__h85931; - wire [113 : 0] x__h31426; - wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24, - _theResult___fst__h116827, - _theResult___snd__h130966, - _theResult___snd__h130980, - _theResult___snd__h130982, - _theResult___snd__h130994, - _theResult___snd__h131000, - _theResult___snd__h131018, - _theResult___snd__h131023, - fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012, - sfdBC__h115662, - sfdin__h130943, - x__h116896; - wire [68 : 0] IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081; - wire [63 : 0] IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612, - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330, - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555, - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618, - IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657, - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452, - fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936; - wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980, - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065, - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552; - wire [58 : 0] IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19, - _theResult___snd__h94767, - _theResult___snd__h94782, - _theResult___snd__h94784, - _theResult___snd__h94797, - _theResult___snd__h94803, - _theResult___snd__h94821, - _theResult___snd__h94826, - result__h85925, - sfdin__h94744, - x__h86149; - wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12, - IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14, - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10, - _theResult____h32523, - _theResult___snd__h34715, - _theResult___snd__h42350, - _theResult___snd__h42365, - _theResult___snd__h42367, - _theResult___snd__h42380, - _theResult___snd__h42386, - _theResult___snd__h42404, - _theResult___snd__h42409, - _theResult___snd_snd_snd__h33963, - result__h32617, - result__h32648, - result__h32823, - rg_q_PLUS_NEG_INV_rg_q_59_60___d561, - sfd___1__h60702, - sfd__h44951, - sfd__h44953, - sfdin__h34118, - sfdin__h42327, - x__h32762, - x__h33052, - x__h60693; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139, - IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29, - IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100, - IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93, - IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33, - IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40, - IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60, - IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67, - IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135, - IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038, - _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038, - _theResult____h164614, - _theResult____h203252, - _theResult____h242191, - _theResult____h269577, - _theResult____h287214, - _theResult___snd__h141392, - _theResult___snd__h141406, - _theResult___snd__h141408, - _theResult___snd__h141420, - _theResult___snd__h141426, - _theResult___snd__h141444, - _theResult___snd__h141449, - _theResult___snd__h163287, - _theResult___snd__h163289, - _theResult___snd__h163296, - _theResult___snd__h163302, - _theResult___snd__h163325, - _theResult___snd__h172863, - _theResult___snd__h172874, - _theResult___snd__h172876, - _theResult___snd__h172886, - _theResult___snd__h172892, - _theResult___snd__h172915, - _theResult___snd__h181599, - _theResult___snd__h181613, - _theResult___snd__h181619, - _theResult___snd__h181637, - _theResult___snd__h201925, - _theResult___snd__h201927, - _theResult___snd__h201934, - _theResult___snd__h201940, - _theResult___snd__h201963, - _theResult___snd__h211501, - _theResult___snd__h211512, - _theResult___snd__h211514, - _theResult___snd__h211524, - _theResult___snd__h211530, - _theResult___snd__h211553, - _theResult___snd__h220237, - _theResult___snd__h220251, - _theResult___snd__h220257, - _theResult___snd__h220275, - _theResult___snd__h240864, - _theResult___snd__h240866, - _theResult___snd__h240873, - _theResult___snd__h240879, - _theResult___snd__h240902, - _theResult___snd__h250440, - _theResult___snd__h250451, - _theResult___snd__h250453, - _theResult___snd__h250463, - _theResult___snd__h250469, - _theResult___snd__h250492, - _theResult___snd__h259176, - _theResult___snd__h259190, - _theResult___snd__h259196, - _theResult___snd__h259214, - _theResult___snd__h277697, - _theResult___snd__h277708, - _theResult___snd__h277710, - _theResult___snd__h277720, - _theResult___snd__h277726, - _theResult___snd__h277749, - _theResult___snd__h286293, - _theResult___snd__h286295, - _theResult___snd__h286302, - _theResult___snd__h286308, - _theResult___snd__h286331, - _theResult___snd__h295463, - _theResult___snd__h295474, - _theResult___snd__h295476, - _theResult___snd__h295486, - _theResult___snd__h295492, - _theResult___snd__h295515, - _theResult___snd__h304083, - _theResult___snd__h304097, - _theResult___snd__h304103, - _theResult___snd__h304121, - fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615, - guard__h132367, - result__h132372, - result__h165227, - result__h203865, - result__h242804, - result__h287827, - sfdA__h131577, - sfdBC__h131578, - sfd__h133119, - sfd__h144536, - sfd__h183176, - sfd__h222115, - sfd__h261975, - sfdin__h141369, - sfdin__h172846, - sfdin__h211484, - sfdin__h250423, - sfdin__h277680, - sfdin__h295446, - value__h32661, - x__h131940, - x__h131944, - x__h132359, - x__h132871, - x__h132880, - x__h165324, - x__h203962, - x__h242901, - x__h287924, - x__h31487; - wire [53 : 0] sfd__h142040, - sfd__h163354, - sfd__h172944, - sfd__h181672, - sfd__h201992, - sfd__h211582, - sfd__h220310, - sfd__h240931, - sfd__h250521, - sfd__h259249, - sfd__h42982, - sfd__h95416, - value__h270197, - value__h31429, - value__h53174; - wire [52 : 0] sfdA__h2035, - sfdA__h2039, - sfdB__h2036, - sfdB__h2041, - x__h114243, - x__h114255; - wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450, - _theResult___fst_sfd__h164063, - _theResult___fst_sfd__h173653, - _theResult___fst_sfd__h182405, - _theResult___fst_sfd__h182414, - _theResult___fst_sfd__h182420, - _theResult___fst_sfd__h202701, - _theResult___fst_sfd__h212291, - _theResult___fst_sfd__h221043, - _theResult___fst_sfd__h221052, - _theResult___fst_sfd__h221058, - _theResult___fst_sfd__h241640, - _theResult___fst_sfd__h251230, - _theResult___fst_sfd__h259982, - _theResult___fst_sfd__h259991, - _theResult___fst_sfd__h259997, - _theResult___fst_sfd__h43557, - _theResult___fst_sfd__h95991, - _theResult___fst_sfd__h96608, - _theResult___sfd__h142542, - _theResult___sfd__h163982, - _theResult___sfd__h173572, - _theResult___sfd__h182324, - _theResult___sfd__h202620, - _theResult___sfd__h212210, - _theResult___sfd__h220962, - _theResult___sfd__h241559, - _theResult___sfd__h251149, - _theResult___sfd__h259901, - _theResult___sfd__h43476, - _theResult___sfd__h95910, - _theResult___snd_fst_sfd__h144486, - _theResult___snd_fst_sfd__h164066, - _theResult___snd_fst_sfd__h182408, - _theResult___snd_fst_sfd__h183126, - _theResult___snd_fst_sfd__h202704, - _theResult___snd_fst_sfd__h221046, - _theResult___snd_fst_sfd__h222065, - _theResult___snd_fst_sfd__h241643, - _theResult___snd_fst_sfd__h259985, - _theResult___snd_fst_sfd__h31362, - out___1_sfd__h144235, - out___1_sfd__h182875, - out___1_sfd__h221814, - out_sfd__h142545, - out_sfd__h163985, - out_sfd__h173575, - out_sfd__h182327, - out_sfd__h202623, - out_sfd__h212213, - out_sfd__h220965, - out_sfd__h241562, - out_sfd__h251152, - out_sfd__h259904, - out_sfd__h43479, - out_sfd__h95913, - sfd__h18934, - sfd__h18937, - sfd__h45004, - sfd__h99402, - sfd__h99405, - sfd__h99408; - wire [24 : 0] sfd__h277778, - sfd__h286360, - sfd__h295544, - sfd__h304156, - value__h148923, - value__h187561, - value__h226500; - wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576, - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643, - _theResult___fst_sfd__h278284, - _theResult___fst_sfd__h286866, - _theResult___fst_sfd__h296050, - _theResult___fst_sfd__h304686, - _theResult___fst_sfd__h304695, - _theResult___fst_sfd__h304701, - _theResult___sfd__h278203, - _theResult___sfd__h286785, - _theResult___sfd__h295969, - _theResult___sfd__h304605, - _theResult___snd_fst_sfd__h261925, - _theResult___snd_fst_sfd__h286869, - _theResult___snd_fst_sfd__h304689, - out_sfd__h278206, - out_sfd__h286788, - out_sfd__h295972, - out_sfd__h304608, - sfd__h304707; - wire [12 : 0] IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352, - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568, - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195, - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007, - value__h130883, - value__h141307, - value__h31374, - value__h31550, - x__h116929, - x__h132471, - x__h52551, - x__h52569; - wire [11 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106, - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331, - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668, - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17, - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389, - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531, - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809, - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326, - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683, - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034, - x__h165357, - x__h203995, - x__h242934, - x__h287957; - wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433, - IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011, - IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66, - _theResult___exp__h142541, - _theResult___exp__h163981, - _theResult___exp__h173571, - _theResult___exp__h182323, - _theResult___exp__h202619, - _theResult___exp__h212209, - _theResult___exp__h220961, - _theResult___exp__h241558, - _theResult___exp__h251148, - _theResult___exp__h259900, - _theResult___exp__h43475, - _theResult___exp__h95909, - _theResult___fst__h31322, - _theResult___fst_exp__h130949, - _theResult___fst_exp__h130952, - _theResult___fst_exp__h130971, - _theResult___fst_exp__h130986, - _theResult___fst_exp__h131025, - _theResult___fst_exp__h131031, - _theResult___fst_exp__h131034, - _theResult___fst_exp__h141375, - _theResult___fst_exp__h141378, - _theResult___fst_exp__h141397, - _theResult___fst_exp__h141412, - _theResult___fst_exp__h141451, - _theResult___fst_exp__h141457, - _theResult___fst_exp__h141460, - _theResult___fst_exp__h163327, - _theResult___fst_exp__h163333, - _theResult___fst_exp__h163336, - _theResult___fst_exp__h164062, - _theResult___fst_exp__h172852, - _theResult___fst_exp__h172917, - _theResult___fst_exp__h172923, - _theResult___fst_exp__h172926, - _theResult___fst_exp__h173652, - _theResult___fst_exp__h181605, - _theResult___fst_exp__h181644, - _theResult___fst_exp__h181650, - _theResult___fst_exp__h181653, - _theResult___fst_exp__h182404, - _theResult___fst_exp__h182413, - _theResult___fst_exp__h182416, - _theResult___fst_exp__h201965, - _theResult___fst_exp__h201971, - _theResult___fst_exp__h201974, - _theResult___fst_exp__h202700, - _theResult___fst_exp__h211490, - _theResult___fst_exp__h211555, - _theResult___fst_exp__h211561, - _theResult___fst_exp__h211564, - _theResult___fst_exp__h212290, - _theResult___fst_exp__h220243, - _theResult___fst_exp__h220282, - _theResult___fst_exp__h220288, - _theResult___fst_exp__h220291, - _theResult___fst_exp__h221042, - _theResult___fst_exp__h221051, - _theResult___fst_exp__h221054, - _theResult___fst_exp__h240904, - _theResult___fst_exp__h240910, - _theResult___fst_exp__h240913, - _theResult___fst_exp__h241639, - _theResult___fst_exp__h250429, - _theResult___fst_exp__h250494, - _theResult___fst_exp__h250500, - _theResult___fst_exp__h250503, - _theResult___fst_exp__h251229, - _theResult___fst_exp__h259182, - _theResult___fst_exp__h259221, - _theResult___fst_exp__h259227, - _theResult___fst_exp__h259230, - _theResult___fst_exp__h259981, - _theResult___fst_exp__h259990, - _theResult___fst_exp__h259993, - _theResult___fst_exp__h42284, - _theResult___fst_exp__h42287, - _theResult___fst_exp__h42290, - _theResult___fst_exp__h42333, - _theResult___fst_exp__h42336, - _theResult___fst_exp__h42356, - _theResult___fst_exp__h42372, - _theResult___fst_exp__h42411, - _theResult___fst_exp__h42417, - _theResult___fst_exp__h42420, - _theResult___fst_exp__h43556, - _theResult___fst_exp__h94750, - _theResult___fst_exp__h94753, - _theResult___fst_exp__h94773, - _theResult___fst_exp__h94789, - _theResult___fst_exp__h94828, - _theResult___fst_exp__h94834, - _theResult___fst_exp__h94837, - _theResult___fst_exp__h95990, - _theResult___snd_fst_exp__h164065, - _theResult___snd_fst_exp__h182407, - _theResult___snd_fst_exp__h202703, - _theResult___snd_fst_exp__h221045, - _theResult___snd_fst_exp__h241642, - _theResult___snd_fst_exp__h259984, - _theResult___snd_fst_exp__h31334, - _theResult___snd_fst_exp__h31337, - _theResult___snd_fst_exp__h31361, - din_exp30866_MINUS_1023__q23, - din_exp__h130866, - din_inc___2_exp__h142626, - din_inc___2_exp__h182469, - din_inc___2_exp__h182504, - din_inc___2_exp__h182530, - din_inc___2_exp__h221107, - din_inc___2_exp__h221142, - din_inc___2_exp__h221168, - din_inc___2_exp__h260046, - din_inc___2_exp__h260081, - din_inc___2_exp__h260107, - din_inc___2_exp__h43566, - din_inc___2_exp__h96000, - fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7, - fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8, - fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128, - fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129, - fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27, - fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26, - fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16, - fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18, - out_exp__h142544, - out_exp__h163984, - out_exp__h173574, - out_exp__h182326, - out_exp__h202622, - out_exp__h212212, - out_exp__h220964, - out_exp__h241561, - out_exp__h251151, - out_exp__h259903, - out_exp__h43478, - out_exp__h95912, - resWirewget_BITS_67_TO_57_MINUS_1023__q137, - theResult___fst_exp2290_MINUS_1023__q11, - value41307_BITS_10_TO_0_MINUS_1023__q28, - x__h31541, - x__h32769, - x__h96539; - wire [8 : 0] IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332; - wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448, - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141, - _theResult___exp__h278202, - _theResult___exp__h286784, - _theResult___exp__h295968, - _theResult___exp__h304604, - _theResult___fst_exp__h277686, - _theResult___fst_exp__h277751, - _theResult___fst_exp__h277757, - _theResult___fst_exp__h277760, - _theResult___fst_exp__h278283, - _theResult___fst_exp__h286333, - _theResult___fst_exp__h286339, - _theResult___fst_exp__h286342, - _theResult___fst_exp__h286865, - _theResult___fst_exp__h295452, - _theResult___fst_exp__h295517, - _theResult___fst_exp__h295523, - _theResult___fst_exp__h295526, - _theResult___fst_exp__h296049, - _theResult___fst_exp__h304089, - _theResult___fst_exp__h304128, - _theResult___fst_exp__h304134, - _theResult___fst_exp__h304137, - _theResult___fst_exp__h304685, - _theResult___fst_exp__h304694, - _theResult___fst_exp__h304697, - _theResult___snd_fst_exp__h286868, - _theResult___snd_fst_exp__h304688, - din_inc___2_exp__h304723, - din_inc___2_exp__h304749, - din_inc___2_exp__h304784, - din_inc___2_exp__h304810, - exp__h304706, - iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95, - iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35, - iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62, - out_exp__h278205, - out_exp__h286787, - out_exp__h295971, - out_exp__h304607; - wire [6 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460, - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342, - x__h85465; - wire [5 : 0] IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982, - b__h11457, - b__h4039, - x__h60732; - wire [4 : 0] IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926, - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921, - IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688, - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501, - fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942, - fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043, - resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768; - wire [2 : 0] IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523; - wire [1 : 0] IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98, - IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13, - IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25, - IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30, - IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20, - IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65, - IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38, - IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134, - IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140, - IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94, - IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143, - IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101, - IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61, - IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68, - IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34, - IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41, - IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136, - _theResult___snd_fst__h131051, - _theResult___snd_fst__h141477, - _theResult___snd_fst__h42439, - _theResult___snd_fst__h94856, - _theResult___snd_snd__h131371, - _theResult___snd_snd_snd__h131369, - guardBC__h115666, - guard__h133123, - guard__h155375, - guard__h164624, - guard__h173663, - guard__h194013, - guard__h203262, - guard__h212301, - guard__h232952, - guard__h242201, - guard__h251240, - guard__h269587, - guard__h278294, - guard__h287224, - guard__h296060, - guard__h33946, - guard__h86435, - x__h131406, - x__h141760, - x__h42705, - x__h95138; - wire IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025, - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374, - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422, - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521, - IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610, - IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85, - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56, - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44, - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728, - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756, - NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946, - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400, - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481, - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488, - NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923, - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584, - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244, - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955, - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730, - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280, - _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463, - _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883, - _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904, - _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633, - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759, - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107, - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273, - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624, - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984, - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685, - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498, - fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359, - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405, - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857, - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926, - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004, - guard__h165222, - guard__h203860, - guard__h242799, - guard__h287822, - rg_index_1_4_PLUS_1_6_ULE_58___d37, - rg_index_1_4_ULE_58___d38, - rg_index_PLUS_1_ULE_57___d6, - rg_index_ULE_57___d7, - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63, - sfdlsb__h116825, - sfdlsb__h32643, - value_BIT_52___h53270; - - // action method server_core_request_put - assign RDY_server_core_request_put = iFifo$FULL_N ; - assign CAN_FIRE_server_core_request_put = iFifo$FULL_N ; - assign WILL_FIRE_server_core_request_put = EN_server_core_request_put ; - - // actionvalue method server_core_response_get - assign server_core_response_get = oFifo$D_OUT ; - assign RDY_server_core_response_get = oFifo$EMPTY_N ; - assign CAN_FIRE_server_core_response_get = oFifo$EMPTY_N ; - assign WILL_FIRE_server_core_response_get = EN_server_core_response_get ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = resetReqsF$FULL_N ; - assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // submodule fpu_div64_fOperands_S0 - FIFOL1 #(.width(32'd131)) fpu_div64_fOperands_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fOperands_S0$D_IN), - .ENQ(fpu_div64_fOperands_S0$ENQ), - .DEQ(fpu_div64_fOperands_S0$DEQ), - .CLR(fpu_div64_fOperands_S0$CLR), - .D_OUT(fpu_div64_fOperands_S0$D_OUT), - .FULL_N(fpu_div64_fOperands_S0$FULL_N), - .EMPTY_N(fpu_div64_fOperands_S0$EMPTY_N)); - - // submodule fpu_div64_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_div64_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fResult_S5$D_IN), - .ENQ(fpu_div64_fResult_S5$ENQ), - .DEQ(fpu_div64_fResult_S5$DEQ), - .CLR(fpu_div64_fResult_S5$CLR), - .D_OUT(fpu_div64_fResult_S5$D_OUT), - .FULL_N(fpu_div64_fResult_S5$FULL_N), - .EMPTY_N(fpu_div64_fResult_S5$EMPTY_N)); - - // submodule fpu_div64_fState_S1 - FIFOL1 #(.width(32'd319)) fpu_div64_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S1$D_IN), - .ENQ(fpu_div64_fState_S1$ENQ), - .DEQ(fpu_div64_fState_S1$DEQ), - .CLR(fpu_div64_fState_S1$CLR), - .D_OUT(fpu_div64_fState_S1$D_OUT), - .FULL_N(fpu_div64_fState_S1$FULL_N), - .EMPTY_N(fpu_div64_fState_S1$EMPTY_N)); - - // submodule fpu_div64_fState_S2 - FIFOL1 #(.width(32'd148)) fpu_div64_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S2$D_IN), - .ENQ(fpu_div64_fState_S2$ENQ), - .DEQ(fpu_div64_fState_S2$DEQ), - .CLR(fpu_div64_fState_S2$CLR), - .D_OUT(fpu_div64_fState_S2$D_OUT), - .FULL_N(fpu_div64_fState_S2$FULL_N), - .EMPTY_N(fpu_div64_fState_S2$EMPTY_N)); - - // submodule fpu_div64_fState_S3 - FIFOL1 #(.width(32'd195)) fpu_div64_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S3$D_IN), - .ENQ(fpu_div64_fState_S3$ENQ), - .DEQ(fpu_div64_fState_S3$DEQ), - .CLR(fpu_div64_fState_S3$CLR), - .D_OUT(fpu_div64_fState_S3$D_OUT), - .FULL_N(fpu_div64_fState_S3$FULL_N), - .EMPTY_N(fpu_div64_fState_S3$EMPTY_N)); - - // submodule fpu_div64_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_div64_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S4$D_IN), - .ENQ(fpu_div64_fState_S4$ENQ), - .DEQ(fpu_div64_fState_S4$DEQ), - .CLR(fpu_div64_fState_S4$CLR), - .D_OUT(fpu_div64_fState_S4$D_OUT), - .FULL_N(fpu_div64_fState_S4$FULL_N), - .EMPTY_N(fpu_div64_fState_S4$EMPTY_N)); - - // submodule fpu_madd_fOperand_S0 - FIFOL1 #(.width(32'd196)) fpu_madd_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fOperand_S0$D_IN), - .ENQ(fpu_madd_fOperand_S0$ENQ), - .DEQ(fpu_madd_fOperand_S0$DEQ), - .CLR(fpu_madd_fOperand_S0$CLR), - .D_OUT(fpu_madd_fOperand_S0$D_OUT), - .FULL_N(fpu_madd_fOperand_S0$FULL_N), - .EMPTY_N(fpu_madd_fOperand_S0$EMPTY_N)); - - // submodule fpu_madd_fProd_S2 - FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fProd_S2$D_IN), - .ENQ(fpu_madd_fProd_S2$ENQ), - .DEQ(fpu_madd_fProd_S2$DEQ), - .CLR(fpu_madd_fProd_S2$CLR), - .D_OUT(fpu_madd_fProd_S2$D_OUT), - .FULL_N(fpu_madd_fProd_S2$FULL_N), - .EMPTY_N(fpu_madd_fProd_S2$EMPTY_N)); - - // submodule fpu_madd_fProd_S3 - FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fProd_S3$D_IN), - .ENQ(fpu_madd_fProd_S3$ENQ), - .DEQ(fpu_madd_fProd_S3$DEQ), - .CLR(fpu_madd_fProd_S3$CLR), - .D_OUT(fpu_madd_fProd_S3$D_OUT), - .FULL_N(fpu_madd_fProd_S3$FULL_N), - .EMPTY_N(fpu_madd_fProd_S3$EMPTY_N)); - - // submodule fpu_madd_fResult_S9 - FIFOL1 #(.width(32'd69)) fpu_madd_fResult_S9(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fResult_S9$D_IN), - .ENQ(fpu_madd_fResult_S9$ENQ), - .DEQ(fpu_madd_fResult_S9$DEQ), - .CLR(fpu_madd_fResult_S9$CLR), - .D_OUT(fpu_madd_fResult_S9$D_OUT), - .FULL_N(fpu_madd_fResult_S9$FULL_N), - .EMPTY_N(fpu_madd_fResult_S9$EMPTY_N)); - - // submodule fpu_madd_fState_S1 - FIFOL1 #(.width(32'd258)) fpu_madd_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S1$D_IN), - .ENQ(fpu_madd_fState_S1$ENQ), - .DEQ(fpu_madd_fState_S1$DEQ), - .CLR(fpu_madd_fState_S1$CLR), - .D_OUT(fpu_madd_fState_S1$D_OUT), - .FULL_N(fpu_madd_fState_S1$FULL_N), - .EMPTY_N(fpu_madd_fState_S1$EMPTY_N)); - - // submodule fpu_madd_fState_S2 - FIFOL1 #(.width(32'd152)) fpu_madd_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S2$D_IN), - .ENQ(fpu_madd_fState_S2$ENQ), - .DEQ(fpu_madd_fState_S2$DEQ), - .CLR(fpu_madd_fState_S2$CLR), - .D_OUT(fpu_madd_fState_S2$D_OUT), - .FULL_N(fpu_madd_fState_S2$FULL_N), - .EMPTY_N(fpu_madd_fState_S2$EMPTY_N)); - - // submodule fpu_madd_fState_S3 - FIFOL1 #(.width(32'd152)) fpu_madd_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S3$D_IN), - .ENQ(fpu_madd_fState_S3$ENQ), - .DEQ(fpu_madd_fState_S3$DEQ), - .CLR(fpu_madd_fState_S3$CLR), - .D_OUT(fpu_madd_fState_S3$D_OUT), - .FULL_N(fpu_madd_fState_S3$FULL_N), - .EMPTY_N(fpu_madd_fState_S3$EMPTY_N)); - - // submodule fpu_madd_fState_S4 - FIFOL1 #(.width(32'd204)) fpu_madd_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S4$D_IN), - .ENQ(fpu_madd_fState_S4$ENQ), - .DEQ(fpu_madd_fState_S4$DEQ), - .CLR(fpu_madd_fState_S4$CLR), - .D_OUT(fpu_madd_fState_S4$D_OUT), - .FULL_N(fpu_madd_fState_S4$FULL_N), - .EMPTY_N(fpu_madd_fState_S4$EMPTY_N)); - - // submodule fpu_madd_fState_S5 - FIFOL1 #(.width(32'd216)) fpu_madd_fState_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S5$D_IN), - .ENQ(fpu_madd_fState_S5$ENQ), - .DEQ(fpu_madd_fState_S5$DEQ), - .CLR(fpu_madd_fState_S5$CLR), - .D_OUT(fpu_madd_fState_S5$D_OUT), - .FULL_N(fpu_madd_fState_S5$FULL_N), - .EMPTY_N(fpu_madd_fState_S5$EMPTY_N)); - - // submodule fpu_madd_fState_S6 - FIFOL1 #(.width(32'd203)) fpu_madd_fState_S6(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S6$D_IN), - .ENQ(fpu_madd_fState_S6$ENQ), - .DEQ(fpu_madd_fState_S6$DEQ), - .CLR(fpu_madd_fState_S6$CLR), - .D_OUT(fpu_madd_fState_S6$D_OUT), - .FULL_N(fpu_madd_fState_S6$FULL_N), - .EMPTY_N(fpu_madd_fState_S6$EMPTY_N)); - - // submodule fpu_madd_fState_S7 - FIFOL1 #(.width(32'd203)) fpu_madd_fState_S7(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S7$D_IN), - .ENQ(fpu_madd_fState_S7$ENQ), - .DEQ(fpu_madd_fState_S7$DEQ), - .CLR(fpu_madd_fState_S7$CLR), - .D_OUT(fpu_madd_fState_S7$D_OUT), - .FULL_N(fpu_madd_fState_S7$FULL_N), - .EMPTY_N(fpu_madd_fState_S7$EMPTY_N)); - - // submodule fpu_madd_fState_S8 - FIFOL1 #(.width(32'd141)) fpu_madd_fState_S8(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S8$D_IN), - .ENQ(fpu_madd_fState_S8$ENQ), - .DEQ(fpu_madd_fState_S8$DEQ), - .CLR(fpu_madd_fState_S8$CLR), - .D_OUT(fpu_madd_fState_S8$D_OUT), - .FULL_N(fpu_madd_fState_S8$FULL_N), - .EMPTY_N(fpu_madd_fState_S8$EMPTY_N)); - - // submodule fpu_sqr64_fOperand_S0 - FIFOL1 #(.width(32'd67)) fpu_sqr64_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fOperand_S0$D_IN), - .ENQ(fpu_sqr64_fOperand_S0$ENQ), - .DEQ(fpu_sqr64_fOperand_S0$DEQ), - .CLR(fpu_sqr64_fOperand_S0$CLR), - .D_OUT(fpu_sqr64_fOperand_S0$D_OUT), - .FULL_N(fpu_sqr64_fOperand_S0$FULL_N), - .EMPTY_N(fpu_sqr64_fOperand_S0$EMPTY_N)); - - // submodule fpu_sqr64_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_sqr64_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fResult_S5$D_IN), - .ENQ(fpu_sqr64_fResult_S5$ENQ), - .DEQ(fpu_sqr64_fResult_S5$DEQ), - .CLR(fpu_sqr64_fResult_S5$CLR), - .D_OUT(fpu_sqr64_fResult_S5$D_OUT), - .FULL_N(fpu_sqr64_fResult_S5$FULL_N), - .EMPTY_N(fpu_sqr64_fResult_S5$EMPTY_N)); - - // submodule fpu_sqr64_fState_S1 - FIFOL1 #(.width(32'd195)) fpu_sqr64_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S1$D_IN), - .ENQ(fpu_sqr64_fState_S1$ENQ), - .DEQ(fpu_sqr64_fState_S1$DEQ), - .CLR(fpu_sqr64_fState_S1$CLR), - .D_OUT(fpu_sqr64_fState_S1$D_OUT), - .FULL_N(fpu_sqr64_fState_S1$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S1$EMPTY_N)); - - // submodule fpu_sqr64_fState_S2 - FIFOL1 #(.width(32'd137)) fpu_sqr64_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S2$D_IN), - .ENQ(fpu_sqr64_fState_S2$ENQ), - .DEQ(fpu_sqr64_fState_S2$DEQ), - .CLR(fpu_sqr64_fState_S2$CLR), - .D_OUT(fpu_sqr64_fState_S2$D_OUT), - .FULL_N(fpu_sqr64_fState_S2$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S2$EMPTY_N)); - - // submodule fpu_sqr64_fState_S3 - FIFOL1 #(.width(32'd196)) fpu_sqr64_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S3$D_IN), - .ENQ(fpu_sqr64_fState_S3$ENQ), - .DEQ(fpu_sqr64_fState_S3$DEQ), - .CLR(fpu_sqr64_fState_S3$CLR), - .D_OUT(fpu_sqr64_fState_S3$D_OUT), - .FULL_N(fpu_sqr64_fState_S3$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S3$EMPTY_N)); - - // submodule fpu_sqr64_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_sqr64_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S4$D_IN), - .ENQ(fpu_sqr64_fState_S4$ENQ), - .DEQ(fpu_sqr64_fState_S4$DEQ), - .CLR(fpu_sqr64_fState_S4$CLR), - .D_OUT(fpu_sqr64_fState_S4$D_OUT), - .FULL_N(fpu_sqr64_fState_S4$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S4$EMPTY_N)); - - // submodule iFifo - FIFO2 #(.width(32'd202), .guarded(32'd1)) iFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(iFifo$D_IN), - .ENQ(iFifo$ENQ), - .DEQ(iFifo$DEQ), - .CLR(iFifo$CLR), - .D_OUT(iFifo$D_OUT), - .FULL_N(iFifo$FULL_N), - .EMPTY_N(iFifo$EMPTY_N)); - - // submodule isDoubleFifo - FIFO2 #(.width(32'd1), .guarded(32'd1)) isDoubleFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(isDoubleFifo$D_IN), - .ENQ(isDoubleFifo$ENQ), - .DEQ(isDoubleFifo$DEQ), - .CLR(isDoubleFifo$CLR), - .D_OUT(isDoubleFifo$D_OUT), - .FULL_N(isDoubleFifo$FULL_N), - .EMPTY_N(isDoubleFifo$EMPTY_N)); - - // submodule isNegateFifo - FIFO2 #(.width(32'd1), .guarded(32'd1)) isNegateFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(isNegateFifo$D_IN), - .ENQ(isNegateFifo$ENQ), - .DEQ(isNegateFifo$DEQ), - .CLR(isNegateFifo$CLR), - .D_OUT(isNegateFifo$D_OUT), - .FULL_N(isNegateFifo$FULL_N), - .EMPTY_N(isNegateFifo$EMPTY_N)); - - // submodule oFifo - FIFO2 #(.width(32'd70), .guarded(32'd1)) oFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(oFifo$D_IN), - .ENQ(oFifo$ENQ), - .DEQ(oFifo$DEQ), - .CLR(oFifo$CLR), - .D_OUT(oFifo$D_OUT), - .FULL_N(oFifo$FULL_N), - .EMPTY_N(oFifo$EMPTY_N)); - - // submodule resetReqsF - FIFO20 #(.guarded(32'd1)) resetReqsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetReqsF$ENQ), - .DEQ(resetReqsF$DEQ), - .CLR(resetReqsF$CLR), - .FULL_N(resetReqsF$FULL_N), - .EMPTY_N(resetReqsF$EMPTY_N)); - - // submodule resetRspsF - FIFO20 #(.guarded(32'd1)) resetRspsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetRspsF$ENQ), - .DEQ(resetRspsF$DEQ), - .CLR(resetRspsF$CLR), - .FULL_N(resetRspsF$FULL_N), - .EMPTY_N(resetRspsF$EMPTY_N)); - - // submodule rmdFifo - FIFO2 #(.width(32'd3), .guarded(32'd1)) rmdFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rmdFifo$D_IN), - .ENQ(rmdFifo$ENQ), - .DEQ(rmdFifo$DEQ), - .CLR(rmdFifo$CLR), - .D_OUT(rmdFifo$D_OUT), - .FULL_N(rmdFifo$FULL_N), - .EMPTY_N(rmdFifo$EMPTY_N)); - - // rule RL_getResDiv - assign CAN_FIRE_RL_getResDiv = fpu_div64_fResult_S5$EMPTY_N ; - assign WILL_FIRE_RL_getResDiv = fpu_div64_fResult_S5$EMPTY_N ; - - // rule RL_getResSqr - assign CAN_FIRE_RL_getResSqr = fpu_sqr64_fResult_S5$EMPTY_N ; - assign WILL_FIRE_RL_getResSqr = fpu_sqr64_fResult_S5$EMPTY_N ; - - // rule RL_getResMAdd - assign CAN_FIRE_RL_getResMAdd = fpu_madd_fResult_S9$EMPTY_N ; - assign WILL_FIRE_RL_getResMAdd = fpu_madd_fResult_S9$EMPTY_N ; - - // rule __me_check_22 - assign CAN_FIRE___me_check_22 = 1'b1 ; - assign WILL_FIRE___me_check_22 = 1'b1 ; - - // rule __me_check_23 - assign CAN_FIRE___me_check_23 = 1'b1 ; - assign WILL_FIRE___me_check_23 = 1'b1 ; - - // rule RL_passResult - assign CAN_FIRE_RL_passResult = - isDoubleFifo$EMPTY_N && isNegateFifo$EMPTY_N && - rmdFifo$EMPTY_N && - oFifo$FULL_N && - resWire$whas ; - assign WILL_FIRE_RL_passResult = CAN_FIRE_RL_passResult ; - - // rule RL_fpu_div64_s5_stage - assign CAN_FIRE_RL_fpu_div64_s5_stage = - fpu_div64_fState_S4$EMPTY_N && fpu_div64_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s5_stage = CAN_FIRE_RL_fpu_div64_s5_stage ; - - // rule RL_fpu_div64_s4_stage - assign CAN_FIRE_RL_fpu_div64_s4_stage = - fpu_div64_fState_S3$EMPTY_N && fpu_div64_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s4_stage = CAN_FIRE_RL_fpu_div64_s4_stage ; - - // rule RL_fpu_div64_s3_stage - assign CAN_FIRE_RL_fpu_div64_s3_stage = - fpu_div64_fState_S2$EMPTY_N && fpu_div64_fState_S3$FULL_N && - (fpu_div64_fState_S2$D_OUT[147] || crg_done) ; - assign WILL_FIRE_RL_fpu_div64_s3_stage = CAN_FIRE_RL_fpu_div64_s3_stage ; - - // rule RL_work - assign CAN_FIRE_RL_work = rg_busy ; - assign WILL_FIRE_RL_work = rg_busy ; - - // rule RL_fpu_div64_s2_stage - assign CAN_FIRE_RL_fpu_div64_s2_stage = - fpu_div64_fState_S1$EMPTY_N && fpu_div64_fState_S2$FULL_N && - (fpu_div64_fState_S1$D_OUT[318] || !rg_busy) ; - assign WILL_FIRE_RL_fpu_div64_s2_stage = - CAN_FIRE_RL_fpu_div64_s2_stage && !rg_busy ; - - // rule RL_fpu_div64_s1_stage - assign CAN_FIRE_RL_fpu_div64_s1_stage = - fpu_div64_fOperands_S0$EMPTY_N && fpu_div64_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s1_stage = CAN_FIRE_RL_fpu_div64_s1_stage ; - - // rule RL_fpu_sqr64_s5_stage - assign CAN_FIRE_RL_fpu_sqr64_s5_stage = - fpu_sqr64_fState_S4$EMPTY_N && fpu_sqr64_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s5_stage = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - - // rule RL_fpu_sqr64_s4_stage - assign CAN_FIRE_RL_fpu_sqr64_s4_stage = - fpu_sqr64_fState_S3$EMPTY_N && fpu_sqr64_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s4_stage = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - - // rule RL_fpu_sqr64_s3_stage - assign CAN_FIRE_RL_fpu_sqr64_s3_stage = - fpu_sqr64_fState_S2$EMPTY_N && fpu_sqr64_fState_S3$FULL_N && - (fpu_sqr64_fState_S2$D_OUT[136] || crg_done_1) ; - assign WILL_FIRE_RL_fpu_sqr64_s3_stage = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - - // rule RL_work_1 - assign CAN_FIRE_RL_work_1 = rg_busy_1 ; - assign WILL_FIRE_RL_work_1 = rg_busy_1 ; - - // rule RL_fpu_sqr64_s2_stage - assign CAN_FIRE_RL_fpu_sqr64_s2_stage = - fpu_sqr64_fState_S1$EMPTY_N && fpu_sqr64_fState_S2$FULL_N && - (fpu_sqr64_fState_S1$D_OUT[194] || !rg_busy_1) ; - assign WILL_FIRE_RL_fpu_sqr64_s2_stage = - CAN_FIRE_RL_fpu_sqr64_s2_stage && !rg_busy_1 ; - - // rule RL_fpu_sqr64_s1_stage - assign CAN_FIRE_RL_fpu_sqr64_s1_stage = - fpu_sqr64_fOperand_S0$EMPTY_N && fpu_sqr64_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s1_stage = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - - // rule RL_fpu_madd_s9_stage - assign CAN_FIRE_RL_fpu_madd_s9_stage = - fpu_madd_fState_S8$EMPTY_N && fpu_madd_fResult_S9$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s9_stage = CAN_FIRE_RL_fpu_madd_s9_stage ; - - // rule RL_fpu_madd_s8_stage - assign CAN_FIRE_RL_fpu_madd_s8_stage = - fpu_madd_fState_S7$EMPTY_N && fpu_madd_fState_S8$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s8_stage = CAN_FIRE_RL_fpu_madd_s8_stage ; - - // rule RL_fpu_madd_s7_stage - assign CAN_FIRE_RL_fpu_madd_s7_stage = - fpu_madd_fState_S6$EMPTY_N && fpu_madd_fState_S7$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s7_stage = CAN_FIRE_RL_fpu_madd_s7_stage ; - - // rule RL_fpu_madd_s6_stage - assign CAN_FIRE_RL_fpu_madd_s6_stage = - fpu_madd_fState_S5$EMPTY_N && fpu_madd_fState_S6$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s6_stage = CAN_FIRE_RL_fpu_madd_s6_stage ; - - // rule RL_fpu_madd_s5_stage - assign CAN_FIRE_RL_fpu_madd_s5_stage = - fpu_madd_fState_S4$EMPTY_N && fpu_madd_fState_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s5_stage = CAN_FIRE_RL_fpu_madd_s5_stage ; - - // rule RL_fpu_madd_s4_stage - assign CAN_FIRE_RL_fpu_madd_s4_stage = - fpu_madd_fState_S3$EMPTY_N && fpu_madd_fProd_S3$EMPTY_N && - fpu_madd_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s4_stage = CAN_FIRE_RL_fpu_madd_s4_stage ; - - // rule RL_fpu_madd_s3_stage - assign CAN_FIRE_RL_fpu_madd_s3_stage = - fpu_madd_fState_S2$EMPTY_N && fpu_madd_fProd_S2$EMPTY_N && - fpu_madd_fProd_S3$FULL_N && - fpu_madd_fState_S3$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s3_stage = CAN_FIRE_RL_fpu_madd_s3_stage ; - - // rule RL_fpu_madd_s2_stage - assign CAN_FIRE_RL_fpu_madd_s2_stage = - fpu_madd_fState_S1$EMPTY_N && fpu_madd_fProd_S2$FULL_N && - fpu_madd_fState_S2$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s2_stage = CAN_FIRE_RL_fpu_madd_s2_stage ; - - // rule RL_fpu_madd_s1_stage - assign CAN_FIRE_RL_fpu_madd_s1_stage = - fpu_madd_fOperand_S0$EMPTY_N && fpu_madd_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s1_stage = CAN_FIRE_RL_fpu_madd_s1_stage ; - - // rule RL_start_op - assign CAN_FIRE_RL_start_op = - iFifo$EMPTY_N && isDoubleFifo$FULL_N && isNegateFifo$FULL_N && - rmdFifo$FULL_N && - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 ; - assign WILL_FIRE_RL_start_op = CAN_FIRE_RL_start_op ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = resetReqsF$EMPTY_N && resetRspsF$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_crg_done$port1__write_1__SEL_1 = rg_busy && rg_index == 6'd28 ; - assign MUX_crg_done$port1__write_1__SEL_2 = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - assign MUX_crg_done_1$port1__write_1__SEL_1 = - rg_busy_1 && rg_index_1 == 6'd29 ; - assign MUX_crg_done_1$port1__write_1__SEL_2 = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - assign MUX_rg_b$write_1__VAL_1 = - fpu_sqr64_fState_S1$D_OUT[57] ? - 116'h40000000000000000000000000000 : - b___1__h77160 ; - assign MUX_rg_b$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___fst__h1476 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign MUX_rg_d$write_1__VAL_1 = - { 1'd0, fpu_div64_fState_S1$D_OUT[67:11] } ; - assign MUX_rg_index$write_1__VAL_2 = rg_index + 6'd1 ; - assign MUX_rg_index_1$write_1__VAL_2 = rg_index_1 + 6'd1 ; - assign MUX_rg_q$write_1__VAL_2 = - rg_index_PLUS_1_ULE_57___d6 ? - { IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14[56:0], - !IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] } : - IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 ; - assign MUX_rg_r$write_1__VAL_1 = - { 2'd0, fpu_div64_fState_S1$D_OUT[181:68] } ; - assign MUX_rg_r$write_1__VAL_2 = - rg_index_PLUS_1_ULE_57___d6 ? - (IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] ? - { IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0], - 1'd0 } + - b__h32583 : - { IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0], - 1'd0 } - - b__h32583) : - IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 ; - assign MUX_rg_r_1$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___snd_snd_snd__h1481 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 ; - assign MUX_rg_res$write_1__VAL_2 = - { rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44 || - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0 : - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44, - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 } ; - assign MUX_rg_s$write_1__VAL_1 = - { fpu_sqr64_fState_S1$D_OUT[57:0], 58'd0 } ; - assign MUX_rg_s$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___snd_fst__h1478 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 ; - - // inlined wires - always@(fpu_div64_fResult_S5$EMPTY_N or - fpu_div64_fResult_S5$D_OUT or - fpu_sqr64_fResult_S5$EMPTY_N or - fpu_sqr64_fResult_S5$D_OUT or - fpu_madd_fResult_S9$EMPTY_N or fpu_madd_fResult_S9$D_OUT) - begin - case (1'b1) // synopsys parallel_case - fpu_div64_fResult_S5$EMPTY_N: resWire$wget = fpu_div64_fResult_S5$D_OUT; - fpu_sqr64_fResult_S5$EMPTY_N: resWire$wget = fpu_sqr64_fResult_S5$D_OUT; - fpu_madd_fResult_S9$EMPTY_N: resWire$wget = fpu_madd_fResult_S9$D_OUT; - default: resWire$wget = 69'h0AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign resWire$whas = - fpu_div64_fResult_S5$EMPTY_N || fpu_sqr64_fResult_S5$EMPTY_N || - fpu_madd_fResult_S9$EMPTY_N ; - assign crg_done$EN_port0__write = - WILL_FIRE_RL_fpu_div64_s3_stage && - !fpu_div64_fState_S2$D_OUT[147] ; - assign crg_done$port1__read = !crg_done$EN_port0__write && crg_done ; - assign crg_done$EN_port1__write = - rg_busy && rg_index == 6'd28 || - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - assign crg_done$port2__read = - crg_done$EN_port1__write ? - MUX_crg_done$port1__write_1__SEL_1 : - crg_done$port1__read ; - assign crg_done_1$EN_port0__write = - WILL_FIRE_RL_fpu_sqr64_s3_stage && - !fpu_sqr64_fState_S2$D_OUT[136] ; - assign crg_done_1$port1__read = !crg_done_1$EN_port0__write && crg_done_1 ; - assign crg_done_1$EN_port1__write = - rg_busy_1 && rg_index_1 == 6'd29 || - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - assign crg_done_1$port2__read = - crg_done_1$EN_port1__write ? - MUX_crg_done_1$port1__write_1__SEL_1 : - crg_done_1$port1__read ; - - // register crg_done - assign crg_done$D_IN = crg_done$port2__read ; - assign crg_done$EN = 1'b1 ; - - // register crg_done_1 - assign crg_done_1$D_IN = crg_done_1$port2__read ; - assign crg_done_1$EN = 1'b1 ; - - // register rg_b - assign rg_b$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - MUX_rg_b$write_1__VAL_1 : - MUX_rg_b$write_1__VAL_2 ; - assign rg_b$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_busy - assign rg_busy$D_IN = !MUX_crg_done$port1__write_1__SEL_1 ; - assign rg_busy$EN = - rg_busy && rg_index == 6'd28 || - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - - // register rg_busy_1 - assign rg_busy_1$D_IN = !MUX_crg_done_1$port1__write_1__SEL_1 ; - assign rg_busy_1$EN = - rg_busy_1 && rg_index_1 == 6'd29 || - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - - // register rg_d - assign rg_d$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - MUX_rg_d$write_1__VAL_1 : - rg_d ; - assign rg_d$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_index - assign rg_index$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - 6'd0 : - MUX_rg_index$write_1__VAL_2 ; - assign rg_index$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_index_1 - assign rg_index_1$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 6'd0 : - MUX_rg_index_1$write_1__VAL_2 ; - assign rg_index_1$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_q - assign rg_q$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - 58'd0 : - MUX_rg_q$write_1__VAL_2 ; - assign rg_q$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_r - assign rg_r$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - MUX_rg_r$write_1__VAL_1 : - MUX_rg_r$write_1__VAL_2 ; - assign rg_r$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_r_1 - assign rg_r_1$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 116'd0 : - MUX_rg_r_1$write_1__VAL_2 ; - assign rg_r_1$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_res - assign rg_res$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - MUX_rg_res$write_1__VAL_2 ; - assign rg_res$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_s - assign rg_s$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - MUX_rg_s$write_1__VAL_1 : - MUX_rg_s$write_1__VAL_2 ; - assign rg_s$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // submodule fpu_div64_fOperands_S0 - assign fpu_div64_fOperands_S0$D_IN = - { IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330, - iFifo$D_OUT[6:4] } ; - assign fpu_div64_fOperands_S0$ENQ = - WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd3 ; - assign fpu_div64_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_div64_s1_stage ; - assign fpu_div64_fOperands_S0$CLR = 1'b0 ; - - // submodule fpu_div64_fResult_S5 - assign fpu_div64_fResult_S5$D_IN = - fpu_div64_fState_S4$D_OUT[138] ? - fpu_div64_fState_S4$D_OUT[137:69] : - { (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[65:2] : - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173, - fpu_div64_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h43556 == 11'd2047 && - _theResult___fst_sfd__h43557 == 52'd0, - 1'd0, - fpu_div64_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_div64_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_div64_fResult_S5$ENQ = CAN_FIRE_RL_fpu_div64_s5_stage ; - assign fpu_div64_fResult_S5$DEQ = fpu_div64_fResult_S5$EMPTY_N ; - assign fpu_div64_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S1 - assign fpu_div64_fState_S1$D_IN = - { fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363, - (fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118]) ? - { fpu_div64_fOperands_S0$D_OUT[130:119], sfd__h18934 } : - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455, - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0), - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - !IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488, - fpu_div64_fOperands_S0$D_OUT[2:0], - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405, - _theResult___snd_fst_exp__h31361, - _theResult___snd_fst_sfd__h31362, - x__h31426, - x__h31487, - x__h31541 } ; - assign fpu_div64_fState_S1$ENQ = CAN_FIRE_RL_fpu_div64_s1_stage ; - assign fpu_div64_fState_S1$DEQ = WILL_FIRE_RL_fpu_div64_s2_stage ; - assign fpu_div64_fState_S1$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S2 - assign fpu_div64_fState_S2$D_IN = - { fpu_div64_fState_S1$D_OUT[318:182], - fpu_div64_fState_S1$D_OUT[10:0] } ; - assign fpu_div64_fState_S2$ENQ = WILL_FIRE_RL_fpu_div64_s2_stage ; - assign fpu_div64_fState_S2$DEQ = CAN_FIRE_RL_fpu_div64_s3_stage ; - assign fpu_div64_fState_S2$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S3 - assign fpu_div64_fState_S3$D_IN = - { fpu_div64_fState_S2$D_OUT[147:11], x__h33052 } ; - assign fpu_div64_fState_S3$ENQ = CAN_FIRE_RL_fpu_div64_s3_stage ; - assign fpu_div64_fState_S3$DEQ = CAN_FIRE_RL_fpu_div64_s4_stage ; - assign fpu_div64_fState_S3$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S4 - assign fpu_div64_fState_S4$D_IN = - { (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[194] : - fpu_div64_fState_S3$D_OUT[194], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - fpu_div64_fState_S3$D_OUT[193:130] : - { CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174, - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 }) : - fpu_div64_fState_S3$D_OUT[193:130], - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926, - fpu_div64_fState_S3$D_OUT[124:122], - fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936, - x__h42705 } ; - assign fpu_div64_fState_S4$ENQ = CAN_FIRE_RL_fpu_div64_s4_stage ; - assign fpu_div64_fState_S4$DEQ = CAN_FIRE_RL_fpu_div64_s5_stage ; - assign fpu_div64_fState_S4$CLR = 1'b0 ; - - // submodule fpu_madd_fOperand_S0 - assign fpu_madd_fOperand_S0$D_IN = - { iFifo$D_OUT[3:0] != 4'd2, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623, - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176, - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177, - iFifo$D_OUT[6:4] } ; - assign fpu_madd_fOperand_S0$ENQ = - WILL_FIRE_RL_start_op && - (iFifo$D_OUT[3:0] == 4'd0 || iFifo$D_OUT[3:0] == 4'd1 || - iFifo$D_OUT[3:0] == 4'd2 || - iFifo$D_OUT[3:0] == 4'd5 || - iFifo$D_OUT[3:0] == 4'd6 || - iFifo$D_OUT[3:0] == 4'd7 || - iFifo$D_OUT[3:0] == 4'd8) ; - assign fpu_madd_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_madd_s1_stage ; - assign fpu_madd_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_madd_fProd_S2 - assign fpu_madd_fProd_S2$D_IN = - fpu_madd_fState_S1$D_OUT[105:53] * - fpu_madd_fState_S1$D_OUT[52:0] ; - assign fpu_madd_fProd_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fProd_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fProd_S2$CLR = 1'b0 ; - - // submodule fpu_madd_fProd_S3 - assign fpu_madd_fProd_S3$D_IN = fpu_madd_fProd_S2$D_OUT ; - assign fpu_madd_fProd_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fProd_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fProd_S3$CLR = 1'b0 ; - - // submodule fpu_madd_fResult_S9 - assign fpu_madd_fResult_S9$D_IN = - fpu_madd_fState_S8$D_OUT[140] ? - fpu_madd_fState_S8$D_OUT[139:71] : - IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 ; - assign fpu_madd_fResult_S9$ENQ = CAN_FIRE_RL_fpu_madd_s9_stage ; - assign fpu_madd_fResult_S9$DEQ = fpu_madd_fResult_S9$EMPTY_N ; - assign fpu_madd_fResult_S9$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S1 - assign fpu_madd_fState_S1$D_IN = - { x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54] || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947, - 4'd0, - fpu_madd_fOperand_S0$D_OUT[2:0], - fpu_madd_fOperand_S0$D_OUT[195], - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911, - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 } ; - assign fpu_madd_fState_S1$ENQ = CAN_FIRE_RL_fpu_madd_s1_stage ; - assign fpu_madd_fState_S1$DEQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fState_S1$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S2 - assign fpu_madd_fState_S2$D_IN = fpu_madd_fState_S1$D_OUT[257:106] ; - assign fpu_madd_fState_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fState_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fState_S2$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S3 - assign fpu_madd_fState_S3$D_IN = fpu_madd_fState_S2$D_OUT ; - assign fpu_madd_fState_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fState_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fState_S3$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S4 - assign fpu_madd_fState_S4$D_IN = - { fpu_madd_fState_S3$D_OUT[151:87], - IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525, - fpu_madd_fState_S3$D_OUT[81:14], - !fpu_madd_fState_S3$D_OUT[151] && fpu_madd_fState_S3$D_OUT[13], - fpu_madd_fState_S3$D_OUT[151] ? - 63'd0 : - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536, - x__h131406 } ; - assign fpu_madd_fState_S4$ENQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fState_S4$DEQ = CAN_FIRE_RL_fpu_madd_s5_stage ; - assign fpu_madd_fState_S4$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S5 - assign fpu_madd_fState_S5$D_IN = - { fpu_madd_fState_S4$D_OUT[203:130], - fpu_madd_fState_S4$D_OUT[129] != fpu_madd_fState_S4$D_OUT[65], - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - fpu_madd_fState_S4$D_OUT[65] : - fpu_madd_fState_S4$D_OUT[129], - IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 } ; - assign fpu_madd_fState_S5$ENQ = CAN_FIRE_RL_fpu_madd_s5_stage ; - assign fpu_madd_fState_S5$DEQ = CAN_FIRE_RL_fpu_madd_s6_stage ; - assign fpu_madd_fState_S5$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S6 - assign fpu_madd_fState_S6$D_IN = - { fpu_madd_fState_S5$D_OUT[215:127], - fpu_madd_fState_S5$D_OUT[113:57], - x__h132359 } ; - assign fpu_madd_fState_S6$ENQ = CAN_FIRE_RL_fpu_madd_s6_stage ; - assign fpu_madd_fState_S6$DEQ = CAN_FIRE_RL_fpu_madd_s7_stage ; - assign fpu_madd_fState_S6$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S7 - assign fpu_madd_fState_S7$D_IN = - { fpu_madd_fState_S6$D_OUT[202:114], x__h132871, x__h132880 } ; - assign fpu_madd_fState_S7$ENQ = CAN_FIRE_RL_fpu_madd_s7_stage ; - assign fpu_madd_fState_S7$DEQ = CAN_FIRE_RL_fpu_madd_s8_stage ; - assign fpu_madd_fState_S7$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S8 - assign fpu_madd_fState_S8$D_IN = - { fpu_madd_fState_S7$D_OUT[202:138], - fpu_madd_fState_S7$D_OUT[202] ? - fpu_madd_fState_S7$D_OUT[137:133] : - fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942, - fpu_madd_fState_S7$D_OUT[132:129], - !fpu_madd_fState_S7$D_OUT[202] && - fpu_madd_fState_S7$D_OUT[127], - fpu_madd_fState_S7$D_OUT[202] ? - 63'd0 : - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952, - x__h141760, - fpu_madd_fState_S7$D_OUT[128] } ; - assign fpu_madd_fState_S8$ENQ = CAN_FIRE_RL_fpu_madd_s8_stage ; - assign fpu_madd_fState_S8$DEQ = CAN_FIRE_RL_fpu_madd_s9_stage ; - assign fpu_madd_fState_S8$CLR = 1'b0 ; - - // submodule fpu_sqr64_fOperand_S0 - assign fpu_sqr64_fOperand_S0$D_IN = - { IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - iFifo$D_OUT[6:4] } ; - assign fpu_sqr64_fOperand_S0$ENQ = - WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd4 ; - assign fpu_sqr64_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - assign fpu_sqr64_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_sqr64_fResult_S5 - assign fpu_sqr64_fResult_S5$D_IN = - fpu_sqr64_fState_S4$D_OUT[138] ? - fpu_sqr64_fState_S4$D_OUT[137:69] : - { (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[65:2] : - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183, - fpu_sqr64_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h95990 == 11'd2047 && - _theResult___fst_sfd__h95991 == 52'd0, - 1'd0, - fpu_sqr64_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_sqr64_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_sqr64_fResult_S5$ENQ = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - assign fpu_sqr64_fResult_S5$DEQ = fpu_sqr64_fResult_S5$EMPTY_N ; - assign fpu_sqr64_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S1 - assign fpu_sqr64_fState_S1$D_IN = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_sqr64_fOperand_S0$D_OUT[54]) ? - { 1'd1, - fpu_sqr64_fOperand_S0$D_OUT[66:55], - sfd__h45004, - 130'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212 ; - assign fpu_sqr64_fState_S1$ENQ = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - assign fpu_sqr64_fState_S1$DEQ = WILL_FIRE_RL_fpu_sqr64_s2_stage ; - assign fpu_sqr64_fState_S1$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S2 - assign fpu_sqr64_fState_S2$D_IN = fpu_sqr64_fState_S1$D_OUT[194:58] ; - assign fpu_sqr64_fState_S2$ENQ = WILL_FIRE_RL_fpu_sqr64_s2_stage ; - assign fpu_sqr64_fState_S2$DEQ = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - assign fpu_sqr64_fState_S2$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S3 - assign fpu_sqr64_fState_S3$D_IN = { fpu_sqr64_fState_S2$D_OUT, x__h86149 } ; - assign fpu_sqr64_fState_S3$ENQ = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - assign fpu_sqr64_fState_S3$DEQ = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - assign fpu_sqr64_fState_S3$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S4 - assign fpu_sqr64_fState_S4$D_IN = - { fpu_sqr64_fState_S3$D_OUT[195:131], - fpu_sqr64_fState_S3$D_OUT[195] && - fpu_sqr64_fState_S3$D_OUT[130], - fpu_sqr64_fState_S3$D_OUT[195] && - fpu_sqr64_fState_S3$D_OUT[129], - IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671, - fpu_sqr64_fState_S3$D_OUT[125:122], - fpu_sqr64_fState_S3$D_OUT[195] ? - fpu_sqr64_fState_S3$D_OUT[121:59] : - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678, - x__h95138 } ; - assign fpu_sqr64_fState_S4$ENQ = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - assign fpu_sqr64_fState_S4$DEQ = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - assign fpu_sqr64_fState_S4$CLR = 1'b0 ; - - // submodule iFifo - assign iFifo$D_IN = server_core_request_put ; - assign iFifo$ENQ = EN_server_core_request_put ; - assign iFifo$DEQ = CAN_FIRE_RL_start_op ; - assign iFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule isDoubleFifo - assign isDoubleFifo$D_IN = !iFifo$D_OUT[201] ; - assign isDoubleFifo$ENQ = CAN_FIRE_RL_start_op ; - assign isDoubleFifo$DEQ = CAN_FIRE_RL_passResult ; - assign isDoubleFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule isNegateFifo - assign isNegateFifo$D_IN = - iFifo$D_OUT[3:0] == 4'd7 || iFifo$D_OUT[3:0] == 4'd8 ; - assign isNegateFifo$ENQ = CAN_FIRE_RL_start_op ; - assign isNegateFifo$DEQ = CAN_FIRE_RL_passResult ; - assign isNegateFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule oFifo - assign oFifo$D_IN = - { !isDoubleFifo$D_OUT, - IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657, - isDoubleFifo$D_OUT ? - resWire$wget[4:0] : - resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 } ; - assign oFifo$ENQ = CAN_FIRE_RL_passResult ; - assign oFifo$DEQ = EN_server_core_response_get ; - assign oFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule resetReqsF - assign resetReqsF$ENQ = EN_server_reset_request_put ; - assign resetReqsF$DEQ = CAN_FIRE_RL_rl_reset ; - assign resetReqsF$CLR = 1'b0 ; - - // submodule resetRspsF - assign resetRspsF$ENQ = CAN_FIRE_RL_rl_reset ; - assign resetRspsF$DEQ = EN_server_reset_response_get ; - assign resetRspsF$CLR = 1'b0 ; - - // submodule rmdFifo - assign rmdFifo$D_IN = iFifo$D_OUT[6:4] ; - assign rmdFifo$ENQ = CAN_FIRE_RL_start_op ; - assign rmdFifo$DEQ = CAN_FIRE_RL_passResult ; - assign rmdFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 ? - _theResult___snd__h277749 : - _theResult____h269577 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 ? - _theResult___snd__h172915 : - _theResult____h164614 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 ? - _theResult___snd__h250492 : - _theResult____h242191 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 ? - _theResult___snd__h211553 : - _theResult____h203252 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 ? - _theResult___snd__h295515 : - _theResult____h287214 ; - assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24 = - _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 ? - _theResult___snd__h131023 : - _theResult___snd__h131018 ; - assign IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12 = - _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883 ? - _theResult___snd__h42409 : - _theResult___snd__h42404 ; - assign IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29 = - _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 ? - _theResult___snd__h141449 : - _theResult___snd__h141444 ; - assign IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19 = - _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633 ? - _theResult___snd__h94826 : - _theResult___snd__h94821 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100 = - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 ? - _theResult___snd__h201963 : - _theResult___snd__h220275 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93 = - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 ? - _theResult___snd__h201963 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33 = - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 ? - _theResult___snd__h163325 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40 = - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 ? - _theResult___snd__h163325 : - _theResult___snd__h181637 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60 = - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 ? - _theResult___snd__h240902 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67 = - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 ? - _theResult___snd__h240902 : - _theResult___snd__h259214 ; - assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135 = - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 ? - _theResult___snd__h286331 : - 57'd0 ; - assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142 = - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 ? - _theResult___snd__h286331 : - _theResult___snd__h304121 ; - assign IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h43566, sfd__h42982[52:1] }) : - { IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977, - sfd__h42982[51:0] } ; - assign IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h142626, sfd__h142040[52:1] }) : - { IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986, - sfd__h142040[51:0] } ; - assign IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h96000, sfd__h95416[52:1] }) : - { IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721, - sfd__h95416[51:0] } ; - assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - ((_theResult___fst_exp__h277686 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823) : - ((_theResult___fst_exp__h286342 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023) ; - assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - ((_theResult___fst_exp__h277686 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388) : - ((_theResult___fst_exp__h286342 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[168] : - ((_theResult___fst_exp__h163336 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[38] : - ((_theResult___fst_exp__h240913 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 && - iFifo$D_OUT[6:4] != 3'd2 && - iFifo$D_OUT[6:4] != 3'd3 && - iFifo$D_OUT[6:4] != 3'd4 || - !iFifo$D_OUT[38] : - ((_theResult___fst_exp__h240913 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[103] : - ((_theResult___fst_exp__h201974 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 && - iFifo$D_OUT[6:4] != 3'd2 && - iFifo$D_OUT[6:4] != 3'd3 && - iFifo$D_OUT[6:4] != 3'd4 || - !iFifo$D_OUT[103] : - ((_theResult___fst_exp__h201974 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121) ; - assign IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 = - (_theResult____h269577[56] ? - 6'd0 : - (_theResult____h269577[55] ? - 6'd1 : - (_theResult____h269577[54] ? - 6'd2 : - (_theResult____h269577[53] ? - 6'd3 : - (_theResult____h269577[52] ? - 6'd4 : - (_theResult____h269577[51] ? - 6'd5 : - (_theResult____h269577[50] ? - 6'd6 : - (_theResult____h269577[49] ? - 6'd7 : - (_theResult____h269577[48] ? - 6'd8 : - (_theResult____h269577[47] ? - 6'd9 : - (_theResult____h269577[46] ? - 6'd10 : - (_theResult____h269577[45] ? - 6'd11 : - (_theResult____h269577[44] ? - 6'd12 : - (_theResult____h269577[43] ? - 6'd13 : - (_theResult____h269577[42] ? - 6'd14 : - (_theResult____h269577[41] ? - 6'd15 : - (_theResult____h269577[40] ? - 6'd16 : - (_theResult____h269577[39] ? - 6'd17 : - (_theResult____h269577[38] ? - 6'd18 : - (_theResult____h269577[37] ? - 6'd19 : - (_theResult____h269577[36] ? - 6'd20 : - (_theResult____h269577[35] ? - 6'd21 : - (_theResult____h269577[34] ? - 6'd22 : - (_theResult____h269577[33] ? - 6'd23 : - (_theResult____h269577[32] ? - 6'd24 : - (_theResult____h269577[31] ? - 6'd25 : - (_theResult____h269577[30] ? - 6'd26 : - (_theResult____h269577[29] ? - 6'd27 : - (_theResult____h269577[28] ? - 6'd28 : - (_theResult____h269577[27] ? - 6'd29 : - (_theResult____h269577[26] ? - 6'd30 : - (_theResult____h269577[25] ? - 6'd31 : - (_theResult____h269577[24] ? - 6'd32 : - (_theResult____h269577[23] ? - 6'd33 : - (_theResult____h269577[22] ? - 6'd34 : - (_theResult____h269577[21] ? - 6'd35 : - (_theResult____h269577[20] ? - 6'd36 : - (_theResult____h269577[19] ? - 6'd37 : - (_theResult____h269577[18] ? - 6'd38 : - (_theResult____h269577[17] ? - 6'd39 : - (_theResult____h269577[16] ? - 6'd40 : - (_theResult____h269577[15] ? - 6'd41 : - (_theResult____h269577[14] ? - 6'd42 : - (_theResult____h269577[13] ? - 6'd43 : - (_theResult____h269577[12] ? - 6'd44 : - (_theResult____h269577[11] ? - 6'd45 : - (_theResult____h269577[10] ? - 6'd46 : - (_theResult____h269577[9] ? - 6'd47 : - (_theResult____h269577[8] ? - 6'd48 : - (_theResult____h269577[7] ? - 6'd49 : - (_theResult____h269577[6] ? - 6'd50 : - (_theResult____h269577[5] ? - 6'd51 : - (_theResult____h269577[4] ? - 6'd52 : - (_theResult____h269577[3] ? - 6'd53 : - (_theResult____h269577[2] ? - 6'd54 : - (_theResult____h269577[1] ? - 6'd55 : - (_theResult____h269577[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 = - (_theResult____h203252[56] ? - 6'd0 : - (_theResult____h203252[55] ? - 6'd1 : - (_theResult____h203252[54] ? - 6'd2 : - (_theResult____h203252[53] ? - 6'd3 : - (_theResult____h203252[52] ? - 6'd4 : - (_theResult____h203252[51] ? - 6'd5 : - (_theResult____h203252[50] ? - 6'd6 : - (_theResult____h203252[49] ? - 6'd7 : - (_theResult____h203252[48] ? - 6'd8 : - (_theResult____h203252[47] ? - 6'd9 : - (_theResult____h203252[46] ? - 6'd10 : - (_theResult____h203252[45] ? - 6'd11 : - (_theResult____h203252[44] ? - 6'd12 : - (_theResult____h203252[43] ? - 6'd13 : - (_theResult____h203252[42] ? - 6'd14 : - (_theResult____h203252[41] ? - 6'd15 : - (_theResult____h203252[40] ? - 6'd16 : - (_theResult____h203252[39] ? - 6'd17 : - (_theResult____h203252[38] ? - 6'd18 : - (_theResult____h203252[37] ? - 6'd19 : - (_theResult____h203252[36] ? - 6'd20 : - (_theResult____h203252[35] ? - 6'd21 : - (_theResult____h203252[34] ? - 6'd22 : - (_theResult____h203252[33] ? - 6'd23 : - (_theResult____h203252[32] ? - 6'd24 : - (_theResult____h203252[31] ? - 6'd25 : - (_theResult____h203252[30] ? - 6'd26 : - (_theResult____h203252[29] ? - 6'd27 : - (_theResult____h203252[28] ? - 6'd28 : - (_theResult____h203252[27] ? - 6'd29 : - (_theResult____h203252[26] ? - 6'd30 : - (_theResult____h203252[25] ? - 6'd31 : - (_theResult____h203252[24] ? - 6'd32 : - (_theResult____h203252[23] ? - 6'd33 : - (_theResult____h203252[22] ? - 6'd34 : - (_theResult____h203252[21] ? - 6'd35 : - (_theResult____h203252[20] ? - 6'd36 : - (_theResult____h203252[19] ? - 6'd37 : - (_theResult____h203252[18] ? - 6'd38 : - (_theResult____h203252[17] ? - 6'd39 : - (_theResult____h203252[16] ? - 6'd40 : - (_theResult____h203252[15] ? - 6'd41 : - (_theResult____h203252[14] ? - 6'd42 : - (_theResult____h203252[13] ? - 6'd43 : - (_theResult____h203252[12] ? - 6'd44 : - (_theResult____h203252[11] ? - 6'd45 : - (_theResult____h203252[10] ? - 6'd46 : - (_theResult____h203252[9] ? - 6'd47 : - (_theResult____h203252[8] ? - 6'd48 : - (_theResult____h203252[7] ? - 6'd49 : - (_theResult____h203252[6] ? - 6'd50 : - (_theResult____h203252[5] ? - 6'd51 : - (_theResult____h203252[4] ? - 6'd52 : - (_theResult____h203252[3] ? - 6'd53 : - (_theResult____h203252[2] ? - 6'd54 : - (_theResult____h203252[1] ? - 6'd55 : - (_theResult____h203252[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 = - (_theResult____h164614[56] ? - 6'd0 : - (_theResult____h164614[55] ? - 6'd1 : - (_theResult____h164614[54] ? - 6'd2 : - (_theResult____h164614[53] ? - 6'd3 : - (_theResult____h164614[52] ? - 6'd4 : - (_theResult____h164614[51] ? - 6'd5 : - (_theResult____h164614[50] ? - 6'd6 : - (_theResult____h164614[49] ? - 6'd7 : - (_theResult____h164614[48] ? - 6'd8 : - (_theResult____h164614[47] ? - 6'd9 : - (_theResult____h164614[46] ? - 6'd10 : - (_theResult____h164614[45] ? - 6'd11 : - (_theResult____h164614[44] ? - 6'd12 : - (_theResult____h164614[43] ? - 6'd13 : - (_theResult____h164614[42] ? - 6'd14 : - (_theResult____h164614[41] ? - 6'd15 : - (_theResult____h164614[40] ? - 6'd16 : - (_theResult____h164614[39] ? - 6'd17 : - (_theResult____h164614[38] ? - 6'd18 : - (_theResult____h164614[37] ? - 6'd19 : - (_theResult____h164614[36] ? - 6'd20 : - (_theResult____h164614[35] ? - 6'd21 : - (_theResult____h164614[34] ? - 6'd22 : - (_theResult____h164614[33] ? - 6'd23 : - (_theResult____h164614[32] ? - 6'd24 : - (_theResult____h164614[31] ? - 6'd25 : - (_theResult____h164614[30] ? - 6'd26 : - (_theResult____h164614[29] ? - 6'd27 : - (_theResult____h164614[28] ? - 6'd28 : - (_theResult____h164614[27] ? - 6'd29 : - (_theResult____h164614[26] ? - 6'd30 : - (_theResult____h164614[25] ? - 6'd31 : - (_theResult____h164614[24] ? - 6'd32 : - (_theResult____h164614[23] ? - 6'd33 : - (_theResult____h164614[22] ? - 6'd34 : - (_theResult____h164614[21] ? - 6'd35 : - (_theResult____h164614[20] ? - 6'd36 : - (_theResult____h164614[19] ? - 6'd37 : - (_theResult____h164614[18] ? - 6'd38 : - (_theResult____h164614[17] ? - 6'd39 : - (_theResult____h164614[16] ? - 6'd40 : - (_theResult____h164614[15] ? - 6'd41 : - (_theResult____h164614[14] ? - 6'd42 : - (_theResult____h164614[13] ? - 6'd43 : - (_theResult____h164614[12] ? - 6'd44 : - (_theResult____h164614[11] ? - 6'd45 : - (_theResult____h164614[10] ? - 6'd46 : - (_theResult____h164614[9] ? - 6'd47 : - (_theResult____h164614[8] ? - 6'd48 : - (_theResult____h164614[7] ? - 6'd49 : - (_theResult____h164614[6] ? - 6'd50 : - (_theResult____h164614[5] ? - 6'd51 : - (_theResult____h164614[4] ? - 6'd52 : - (_theResult____h164614[3] ? - 6'd53 : - (_theResult____h164614[2] ? - 6'd54 : - (_theResult____h164614[1] ? - 6'd55 : - (_theResult____h164614[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 = - (_theResult____h242191[56] ? - 6'd0 : - (_theResult____h242191[55] ? - 6'd1 : - (_theResult____h242191[54] ? - 6'd2 : - (_theResult____h242191[53] ? - 6'd3 : - (_theResult____h242191[52] ? - 6'd4 : - (_theResult____h242191[51] ? - 6'd5 : - (_theResult____h242191[50] ? - 6'd6 : - (_theResult____h242191[49] ? - 6'd7 : - (_theResult____h242191[48] ? - 6'd8 : - (_theResult____h242191[47] ? - 6'd9 : - (_theResult____h242191[46] ? - 6'd10 : - (_theResult____h242191[45] ? - 6'd11 : - (_theResult____h242191[44] ? - 6'd12 : - (_theResult____h242191[43] ? - 6'd13 : - (_theResult____h242191[42] ? - 6'd14 : - (_theResult____h242191[41] ? - 6'd15 : - (_theResult____h242191[40] ? - 6'd16 : - (_theResult____h242191[39] ? - 6'd17 : - (_theResult____h242191[38] ? - 6'd18 : - (_theResult____h242191[37] ? - 6'd19 : - (_theResult____h242191[36] ? - 6'd20 : - (_theResult____h242191[35] ? - 6'd21 : - (_theResult____h242191[34] ? - 6'd22 : - (_theResult____h242191[33] ? - 6'd23 : - (_theResult____h242191[32] ? - 6'd24 : - (_theResult____h242191[31] ? - 6'd25 : - (_theResult____h242191[30] ? - 6'd26 : - (_theResult____h242191[29] ? - 6'd27 : - (_theResult____h242191[28] ? - 6'd28 : - (_theResult____h242191[27] ? - 6'd29 : - (_theResult____h242191[26] ? - 6'd30 : - (_theResult____h242191[25] ? - 6'd31 : - (_theResult____h242191[24] ? - 6'd32 : - (_theResult____h242191[23] ? - 6'd33 : - (_theResult____h242191[22] ? - 6'd34 : - (_theResult____h242191[21] ? - 6'd35 : - (_theResult____h242191[20] ? - 6'd36 : - (_theResult____h242191[19] ? - 6'd37 : - (_theResult____h242191[18] ? - 6'd38 : - (_theResult____h242191[17] ? - 6'd39 : - (_theResult____h242191[16] ? - 6'd40 : - (_theResult____h242191[15] ? - 6'd41 : - (_theResult____h242191[14] ? - 6'd42 : - (_theResult____h242191[13] ? - 6'd43 : - (_theResult____h242191[12] ? - 6'd44 : - (_theResult____h242191[11] ? - 6'd45 : - (_theResult____h242191[10] ? - 6'd46 : - (_theResult____h242191[9] ? - 6'd47 : - (_theResult____h242191[8] ? - 6'd48 : - (_theResult____h242191[7] ? - 6'd49 : - (_theResult____h242191[6] ? - 6'd50 : - (_theResult____h242191[5] ? - 6'd51 : - (_theResult____h242191[4] ? - 6'd52 : - (_theResult____h242191[3] ? - 6'd53 : - (_theResult____h242191[2] ? - 6'd54 : - (_theResult____h242191[1] ? - 6'd55 : - (_theResult____h242191[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 = - (_theResult____h287214[56] ? - 6'd0 : - (_theResult____h287214[55] ? - 6'd1 : - (_theResult____h287214[54] ? - 6'd2 : - (_theResult____h287214[53] ? - 6'd3 : - (_theResult____h287214[52] ? - 6'd4 : - (_theResult____h287214[51] ? - 6'd5 : - (_theResult____h287214[50] ? - 6'd6 : - (_theResult____h287214[49] ? - 6'd7 : - (_theResult____h287214[48] ? - 6'd8 : - (_theResult____h287214[47] ? - 6'd9 : - (_theResult____h287214[46] ? - 6'd10 : - (_theResult____h287214[45] ? - 6'd11 : - (_theResult____h287214[44] ? - 6'd12 : - (_theResult____h287214[43] ? - 6'd13 : - (_theResult____h287214[42] ? - 6'd14 : - (_theResult____h287214[41] ? - 6'd15 : - (_theResult____h287214[40] ? - 6'd16 : - (_theResult____h287214[39] ? - 6'd17 : - (_theResult____h287214[38] ? - 6'd18 : - (_theResult____h287214[37] ? - 6'd19 : - (_theResult____h287214[36] ? - 6'd20 : - (_theResult____h287214[35] ? - 6'd21 : - (_theResult____h287214[34] ? - 6'd22 : - (_theResult____h287214[33] ? - 6'd23 : - (_theResult____h287214[32] ? - 6'd24 : - (_theResult____h287214[31] ? - 6'd25 : - (_theResult____h287214[30] ? - 6'd26 : - (_theResult____h287214[29] ? - 6'd27 : - (_theResult____h287214[28] ? - 6'd28 : - (_theResult____h287214[27] ? - 6'd29 : - (_theResult____h287214[26] ? - 6'd30 : - (_theResult____h287214[25] ? - 6'd31 : - (_theResult____h287214[24] ? - 6'd32 : - (_theResult____h287214[23] ? - 6'd33 : - (_theResult____h287214[22] ? - 6'd34 : - (_theResult____h287214[21] ? - 6'd35 : - (_theResult____h287214[20] ? - 6'd36 : - (_theResult____h287214[19] ? - 6'd37 : - (_theResult____h287214[18] ? - 6'd38 : - (_theResult____h287214[17] ? - 6'd39 : - (_theResult____h287214[16] ? - 6'd40 : - (_theResult____h287214[15] ? - 6'd41 : - (_theResult____h287214[14] ? - 6'd42 : - (_theResult____h287214[13] ? - 6'd43 : - (_theResult____h287214[12] ? - 6'd44 : - (_theResult____h287214[11] ? - 6'd45 : - (_theResult____h287214[10] ? - 6'd46 : - (_theResult____h287214[9] ? - 6'd47 : - (_theResult____h287214[8] ? - 6'd48 : - (_theResult____h287214[7] ? - 6'd49 : - (_theResult____h287214[6] ? - 6'd50 : - (_theResult____h287214[5] ? - 6'd51 : - (_theResult____h287214[4] ? - 6'd52 : - (_theResult____h287214[3] ? - 6'd53 : - (_theResult____h287214[2] ? - 6'd54 : - (_theResult____h287214[1] ? - 6'd55 : - (_theResult____h287214[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 = - (din_exp__h130866 == 11'd0) ? - 12'd3074 : - { din_exp30866_MINUS_1023__q23[10], - din_exp30866_MINUS_1023__q23 } ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 = - (sfdBC__h115662[105] ? - 7'd0 : - (sfdBC__h115662[104] ? - 7'd1 : - (sfdBC__h115662[103] ? - 7'd2 : - (sfdBC__h115662[102] ? - 7'd3 : - (sfdBC__h115662[101] ? - 7'd4 : - (sfdBC__h115662[100] ? - 7'd5 : - (sfdBC__h115662[99] ? - 7'd6 : - (sfdBC__h115662[98] ? - 7'd7 : - (sfdBC__h115662[97] ? - 7'd8 : - (sfdBC__h115662[96] ? - 7'd9 : - (sfdBC__h115662[95] ? - 7'd10 : - (sfdBC__h115662[94] ? - 7'd11 : - (sfdBC__h115662[93] ? - 7'd12 : - (sfdBC__h115662[92] ? - 7'd13 : - (sfdBC__h115662[91] ? - 7'd14 : - (sfdBC__h115662[90] ? - 7'd15 : - (sfdBC__h115662[89] ? - 7'd16 : - (sfdBC__h115662[88] ? - 7'd17 : - (sfdBC__h115662[87] ? - 7'd18 : - (sfdBC__h115662[86] ? - 7'd19 : - (sfdBC__h115662[85] ? - 7'd20 : - (sfdBC__h115662[84] ? - 7'd21 : - (sfdBC__h115662[83] ? - 7'd22 : - (sfdBC__h115662[82] ? - 7'd23 : - (sfdBC__h115662[81] ? - 7'd24 : - (sfdBC__h115662[80] ? - 7'd25 : - (sfdBC__h115662[79] ? - 7'd26 : - (sfdBC__h115662[78] ? - 7'd27 : - (sfdBC__h115662[77] ? - 7'd28 : - (sfdBC__h115662[76] ? - 7'd29 : - (sfdBC__h115662[75] ? - 7'd30 : - (sfdBC__h115662[74] ? - 7'd31 : - (sfdBC__h115662[73] ? - 7'd32 : - (sfdBC__h115662[72] ? - 7'd33 : - (sfdBC__h115662[71] ? - 7'd34 : - (sfdBC__h115662[70] ? - 7'd35 : - (sfdBC__h115662[69] ? - 7'd36 : - (sfdBC__h115662[68] ? - 7'd37 : - (sfdBC__h115662[67] ? - 7'd38 : - (sfdBC__h115662[66] ? - 7'd39 : - (sfdBC__h115662[65] ? - 7'd40 : - (sfdBC__h115662[64] ? - 7'd41 : - (sfdBC__h115662[63] ? - 7'd42 : - (sfdBC__h115662[62] ? - 7'd43 : - (sfdBC__h115662[61] ? - 7'd44 : - (sfdBC__h115662[60] ? - 7'd45 : - (sfdBC__h115662[59] ? - 7'd46 : - (sfdBC__h115662[58] ? - 7'd47 : - (sfdBC__h115662[57] ? - 7'd48 : - (sfdBC__h115662[56] ? - 7'd49 : - (sfdBC__h115662[55] ? - 7'd50 : - (sfdBC__h115662[54] ? - 7'd51 : - (sfdBC__h115662[53] ? - 7'd52 : - (sfdBC__h115662[52] ? - 7'd53 : - (sfdBC__h115662[51] ? - 7'd54 : - (sfdBC__h115662[50] ? - 7'd55 : - (sfdBC__h115662[49] ? - 7'd56 : - (sfdBC__h115662[48] ? - 7'd57 : - (sfdBC__h115662[47] ? - 7'd58 : - (sfdBC__h115662[46] ? - 7'd59 : - (sfdBC__h115662[45] ? - 7'd60 : - (sfdBC__h115662[44] ? - 7'd61 : - (sfdBC__h115662[43] ? - 7'd62 : - (sfdBC__h115662[42] ? - 7'd63 : - (sfdBC__h115662[41] ? - 7'd64 : - (sfdBC__h115662[40] ? - 7'd65 : - (sfdBC__h115662[39] ? - 7'd66 : - (sfdBC__h115662[38] ? - 7'd67 : - (sfdBC__h115662[37] ? - 7'd68 : - (sfdBC__h115662[36] ? - 7'd69 : - (sfdBC__h115662[35] ? - 7'd70 : - (sfdBC__h115662[34] ? - 7'd71 : - (sfdBC__h115662[33] ? - 7'd72 : - (sfdBC__h115662[32] ? - 7'd73 : - (sfdBC__h115662[31] ? - 7'd74 : - (sfdBC__h115662[30] ? - 7'd75 : - (sfdBC__h115662[29] ? - 7'd76 : - (sfdBC__h115662[28] ? - 7'd77 : - (sfdBC__h115662[27] ? - 7'd78 : - (sfdBC__h115662[26] ? - 7'd79 : - (sfdBC__h115662[25] ? - 7'd80 : - (sfdBC__h115662[24] ? - 7'd81 : - (sfdBC__h115662[23] ? - 7'd82 : - (sfdBC__h115662[22] ? - 7'd83 : - (sfdBC__h115662[21] ? - 7'd84 : - (sfdBC__h115662[20] ? - 7'd85 : - (sfdBC__h115662[19] ? - 7'd86 : - (sfdBC__h115662[18] ? - 7'd87 : - (sfdBC__h115662[17] ? - 7'd88 : - (sfdBC__h115662[16] ? - 7'd89 : - (sfdBC__h115662[15] ? - 7'd90 : - (sfdBC__h115662[14] ? - 7'd91 : - (sfdBC__h115662[13] ? - 7'd92 : - (sfdBC__h115662[12] ? - 7'd93 : - (sfdBC__h115662[11] ? - 7'd94 : - (sfdBC__h115662[10] ? - 7'd95 : - (sfdBC__h115662[9] ? - 7'd96 : - (sfdBC__h115662[8] ? - 7'd97 : - (sfdBC__h115662[7] ? - 7'd98 : - (sfdBC__h115662[6] ? - 7'd99 : - (sfdBC__h115662[5] ? - 7'd100 : - (sfdBC__h115662[4] ? - 7'd101 : - (sfdBC__h115662[3] ? - 7'd102 : - (sfdBC__h115662[2] ? - 7'd103 : - (sfdBC__h115662[1] ? - 7'd104 : - (sfdBC__h115662[0] ? - 7'd105 : - 7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 = - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 - - 12'd3074 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h130949, sfdin__h130943[105:54] } ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 = - (guard__h269587 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h277686 : - _theResult___exp__h278202 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 = - (guard__h269587 == 2'b0) ? - _theResult___fst_exp__h277686 : - (resWire$wget[68] ? - _theResult___exp__h278202 : - _theResult___fst_exp__h277686) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 = - (guard__h269587 == 2'b0 || resWire$wget[68]) ? - sfdin__h277680[56:34] : - _theResult___sfd__h278203 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 = - (guard__h269587 == 2'b0) ? - sfdin__h277680[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h278203 : - sfdin__h277680[56:34]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 = - (guard__h164624 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h172852 : - _theResult___exp__h173571 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 = - (guard__h164624 == 2'b0) ? - _theResult___fst_exp__h172852 : - (iFifo$D_OUT[168] ? - _theResult___exp__h173571 : - _theResult___fst_exp__h172852) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 = - (guard__h164624 == 2'b0 || iFifo$D_OUT[168]) ? - sfdin__h172846[56:5] : - _theResult___sfd__h173572 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 = - (guard__h164624 == 2'b0) ? - sfdin__h172846[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h173572 : - sfdin__h172846[56:5]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 = - (guard__h242201 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h250429 : - _theResult___exp__h251148 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 = - (guard__h242201 == 2'b0) ? - _theResult___fst_exp__h250429 : - (iFifo$D_OUT[38] ? - _theResult___exp__h251148 : - _theResult___fst_exp__h250429) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 = - (guard__h242201 == 2'b0 || iFifo$D_OUT[38]) ? - sfdin__h250423[56:5] : - _theResult___sfd__h251149 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 = - (guard__h242201 == 2'b0) ? - sfdin__h250423[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h251149 : - sfdin__h250423[56:5]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 = - (guard__h203262 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h211490 : - _theResult___exp__h212209 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 = - (guard__h203262 == 2'b0) ? - _theResult___fst_exp__h211490 : - (iFifo$D_OUT[103] ? - _theResult___exp__h212209 : - _theResult___fst_exp__h211490) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 = - (guard__h203262 == 2'b0 || iFifo$D_OUT[103]) ? - sfdin__h211484[56:5] : - _theResult___sfd__h212210 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 = - (guard__h203262 == 2'b0) ? - sfdin__h211484[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h212210 : - sfdin__h211484[56:5]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 = - (guard__h287224 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h295452 : - _theResult___exp__h295968 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 = - (guard__h287224 == 2'b0) ? - _theResult___fst_exp__h295452 : - (resWire$wget[68] ? - _theResult___exp__h295968 : - _theResult___fst_exp__h295452) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 = - (guard__h287224 == 2'b0 || resWire$wget[68]) ? - sfdin__h295446[56:34] : - _theResult___sfd__h295969 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 = - (guard__h287224 == 2'b0) ? - sfdin__h295446[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h295969 : - sfdin__h295446[56:34]) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 = - (guard__h194013 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h201974 : - _theResult___exp__h202619 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 = - (guard__h194013 == 2'b0) ? - _theResult___fst_exp__h201974 : - (iFifo$D_OUT[103] ? - _theResult___exp__h202619 : - _theResult___fst_exp__h201974) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 = - (guard__h212301 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h220291 : - _theResult___exp__h220961 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 = - (guard__h212301 == 2'b0) ? - _theResult___fst_exp__h220291 : - (iFifo$D_OUT[103] ? - _theResult___exp__h220961 : - _theResult___fst_exp__h220291) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 = - (guard__h194013 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___snd__h201925[56:5] : - _theResult___sfd__h202620 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 = - (guard__h194013 == 2'b0) ? - _theResult___snd__h201925[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h202620 : - _theResult___snd__h201925[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 = - (guard__h212301 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___snd__h220237[56:5] : - _theResult___sfd__h220962 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 = - (guard__h212301 == 2'b0) ? - _theResult___snd__h220237[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h220962 : - _theResult___snd__h220237[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 = - (guard__h155375 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h163336 : - _theResult___exp__h163981 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 = - (guard__h155375 == 2'b0) ? - _theResult___fst_exp__h163336 : - (iFifo$D_OUT[168] ? - _theResult___exp__h163981 : - _theResult___fst_exp__h163336) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 = - (guard__h173663 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h181653 : - _theResult___exp__h182323 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 = - (guard__h173663 == 2'b0) ? - _theResult___fst_exp__h181653 : - (iFifo$D_OUT[168] ? - _theResult___exp__h182323 : - _theResult___fst_exp__h181653) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 = - (guard__h155375 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___snd__h163287[56:5] : - _theResult___sfd__h163982 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 = - (guard__h155375 == 2'b0) ? - _theResult___snd__h163287[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h163982 : - _theResult___snd__h163287[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 = - (guard__h173663 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___snd__h181599[56:5] : - _theResult___sfd__h182324 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 = - (guard__h173663 == 2'b0) ? - _theResult___snd__h181599[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h182324 : - _theResult___snd__h181599[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 = - (guard__h232952 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h240913 : - _theResult___exp__h241558 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 = - (guard__h232952 == 2'b0) ? - _theResult___fst_exp__h240913 : - (iFifo$D_OUT[38] ? - _theResult___exp__h241558 : - _theResult___fst_exp__h240913) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 = - (guard__h251240 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h259230 : - _theResult___exp__h259900 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 = - (guard__h251240 == 2'b0) ? - _theResult___fst_exp__h259230 : - (iFifo$D_OUT[38] ? - _theResult___exp__h259900 : - _theResult___fst_exp__h259230) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 = - (guard__h232952 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___snd__h240864[56:5] : - _theResult___sfd__h241559 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 = - (guard__h232952 == 2'b0) ? - _theResult___snd__h240864[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h241559 : - _theResult___snd__h240864[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 = - (guard__h251240 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___snd__h259176[56:5] : - _theResult___sfd__h259901 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 = - (guard__h251240 == 2'b0) ? - _theResult___snd__h259176[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h259901 : - _theResult___snd__h259176[56:5]) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 = - (guard__h278294 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h286342 : - _theResult___exp__h286784 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 = - (guard__h278294 == 2'b0) ? - _theResult___fst_exp__h286342 : - (resWire$wget[68] ? - _theResult___exp__h286784 : - _theResult___fst_exp__h286342) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 = - (guard__h296060 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h304137 : - _theResult___exp__h304604 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 = - (guard__h296060 == 2'b0) ? - _theResult___fst_exp__h304137 : - (resWire$wget[68] ? - _theResult___exp__h304604 : - _theResult___fst_exp__h304137) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 = - (guard__h278294 == 2'b0 || resWire$wget[68]) ? - _theResult___snd__h286293[56:34] : - _theResult___sfd__h286785 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 = - (guard__h278294 == 2'b0) ? - _theResult___snd__h286293[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h286785 : - _theResult___snd__h286293[56:34]) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 = - (guard__h296060 == 2'b0 || resWire$wget[68]) ? - _theResult___snd__h304083[56:34] : - _theResult___sfd__h304605 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 = - (guard__h296060 == 2'b0) ? - _theResult___snd__h304083[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h304605 : - _theResult___snd__h304083[56:34]) ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 12'd3074 : - { theResult___fst_exp2290_MINUS_1023__q11[10], - theResult___fst_exp2290_MINUS_1023__q11 } ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 = - (sfdin__h34118[57] ? - 6'd0 : - (sfdin__h34118[56] ? - 6'd1 : - (sfdin__h34118[55] ? - 6'd2 : - (sfdin__h34118[54] ? - 6'd3 : - (sfdin__h34118[53] ? - 6'd4 : - (sfdin__h34118[52] ? - 6'd5 : - (sfdin__h34118[51] ? - 6'd6 : - (sfdin__h34118[50] ? - 6'd7 : - (sfdin__h34118[49] ? - 6'd8 : - (sfdin__h34118[48] ? - 6'd9 : - (sfdin__h34118[47] ? - 6'd10 : - (sfdin__h34118[46] ? - 6'd11 : - (sfdin__h34118[45] ? - 6'd12 : - (sfdin__h34118[44] ? - 6'd13 : - (sfdin__h34118[43] ? - 6'd14 : - (sfdin__h34118[42] ? - 6'd15 : - (sfdin__h34118[41] ? - 6'd16 : - (sfdin__h34118[40] ? - 6'd17 : - (sfdin__h34118[39] ? - 6'd18 : - (sfdin__h34118[38] ? - 6'd19 : - (sfdin__h34118[37] ? - 6'd20 : - (sfdin__h34118[36] ? - 6'd21 : - (sfdin__h34118[35] ? - 6'd22 : - (sfdin__h34118[34] ? - 6'd23 : - (sfdin__h34118[33] ? - 6'd24 : - (sfdin__h34118[32] ? - 6'd25 : - (sfdin__h34118[31] ? - 6'd26 : - (sfdin__h34118[30] ? - 6'd27 : - (sfdin__h34118[29] ? - 6'd28 : - (sfdin__h34118[28] ? - 6'd29 : - (sfdin__h34118[27] ? - 6'd30 : - (sfdin__h34118[26] ? - 6'd31 : - (sfdin__h34118[25] ? - 6'd32 : - (sfdin__h34118[24] ? - 6'd33 : - (sfdin__h34118[23] ? - 6'd34 : - (sfdin__h34118[22] ? - 6'd35 : - (sfdin__h34118[21] ? - 6'd36 : - (sfdin__h34118[20] ? - 6'd37 : - (sfdin__h34118[19] ? - 6'd38 : - (sfdin__h34118[18] ? - 6'd39 : - (sfdin__h34118[17] ? - 6'd40 : - (sfdin__h34118[16] ? - 6'd41 : - (sfdin__h34118[15] ? - 6'd42 : - (sfdin__h34118[14] ? - 6'd43 : - (sfdin__h34118[13] ? - 6'd44 : - (sfdin__h34118[12] ? - 6'd45 : - (sfdin__h34118[11] ? - 6'd46 : - (sfdin__h34118[10] ? - 6'd47 : - (sfdin__h34118[9] ? - 6'd48 : - (sfdin__h34118[8] ? - 6'd49 : - (sfdin__h34118[7] ? - 6'd50 : - (sfdin__h34118[6] ? - 6'd51 : - (sfdin__h34118[5] ? - 6'd52 : - (sfdin__h34118[4] ? - 6'd53 : - (sfdin__h34118[3] ? - 6'd54 : - (sfdin__h34118[2] ? - 6'd55 : - (sfdin__h34118[1] ? - 6'd56 : - (sfdin__h34118[0] ? - 6'd57 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 = - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 - - 12'd3074 ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926 = - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 ? - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921 : - { fpu_div64_fState_S3$D_OUT[129:128], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[127] : - fpu_div64_fState_S3$D_OUT[127], - fpu_div64_fState_S3$D_OUT[126], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[125] : - fpu_div64_fState_S3$D_OUT[125] } ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h42333, sfdin__h42327[57:6] } ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 == 52'd0) ? - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194] : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ? - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 : - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194]) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 == 52'd0) ? - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ? - 63'h7FF0000000000000 : - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936 = - (x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51]) ? - { fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 } : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118]) ? - fpu_madd_fOperand_S0$D_OUT[130:67] : - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54]) ? - fpu_madd_fOperand_S0$D_OUT[66:3] : - { NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 })) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51]) ? - { fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - x__h96539, - sfd__h99402 } : - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 ; - assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 = - (sfd__h133119[56] ? - 6'd0 : - (sfd__h133119[55] ? - 6'd1 : - (sfd__h133119[54] ? - 6'd2 : - (sfd__h133119[53] ? - 6'd3 : - (sfd__h133119[52] ? - 6'd4 : - (sfd__h133119[51] ? - 6'd5 : - (sfd__h133119[50] ? - 6'd6 : - (sfd__h133119[49] ? - 6'd7 : - (sfd__h133119[48] ? - 6'd8 : - (sfd__h133119[47] ? - 6'd9 : - (sfd__h133119[46] ? - 6'd10 : - (sfd__h133119[45] ? - 6'd11 : - (sfd__h133119[44] ? - 6'd12 : - (sfd__h133119[43] ? - 6'd13 : - (sfd__h133119[42] ? - 6'd14 : - (sfd__h133119[41] ? - 6'd15 : - (sfd__h133119[40] ? - 6'd16 : - (sfd__h133119[39] ? - 6'd17 : - (sfd__h133119[38] ? - 6'd18 : - (sfd__h133119[37] ? - 6'd19 : - (sfd__h133119[36] ? - 6'd20 : - (sfd__h133119[35] ? - 6'd21 : - (sfd__h133119[34] ? - 6'd22 : - (sfd__h133119[33] ? - 6'd23 : - (sfd__h133119[32] ? - 6'd24 : - (sfd__h133119[31] ? - 6'd25 : - (sfd__h133119[30] ? - 6'd26 : - (sfd__h133119[29] ? - 6'd27 : - (sfd__h133119[28] ? - 6'd28 : - (sfd__h133119[27] ? - 6'd29 : - (sfd__h133119[26] ? - 6'd30 : - (sfd__h133119[25] ? - 6'd31 : - (sfd__h133119[24] ? - 6'd32 : - (sfd__h133119[23] ? - 6'd33 : - (sfd__h133119[22] ? - 6'd34 : - (sfd__h133119[21] ? - 6'd35 : - (sfd__h133119[20] ? - 6'd36 : - (sfd__h133119[19] ? - 6'd37 : - (sfd__h133119[18] ? - 6'd38 : - (sfd__h133119[17] ? - 6'd39 : - (sfd__h133119[16] ? - 6'd40 : - (sfd__h133119[15] ? - 6'd41 : - (sfd__h133119[14] ? - 6'd42 : - (sfd__h133119[13] ? - 6'd43 : - (sfd__h133119[12] ? - 6'd44 : - (sfd__h133119[11] ? - 6'd45 : - (sfd__h133119[10] ? - 6'd46 : - (sfd__h133119[9] ? - 6'd47 : - (sfd__h133119[8] ? - 6'd48 : - (sfd__h133119[7] ? - 6'd49 : - (sfd__h133119[6] ? - 6'd50 : - (sfd__h133119[5] ? - 6'd51 : - (sfd__h133119[4] ? - 6'd52 : - (sfd__h133119[3] ? - 6'd53 : - (sfd__h133119[2] ? - 6'd54 : - (sfd__h133119[1] ? - 6'd55 : - (sfd__h133119[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h141375, sfdin__h141369[56:5] } ; - assign IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - ((IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73) : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 ; - assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503 = - (!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ? - fpu_madd_fState_S3$D_OUT[86] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[4] ; - assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506 = - (!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ? - fpu_madd_fState_S3$D_OUT[85] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[3] ; - assign IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 = - { NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 : - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 - - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 : - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 - - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563, - x__h131940, - x__h131944 } ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 = - ((SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99[10], - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - ((_theResult___fst_exp__h211490 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117) : - ((_theResult___fst_exp__h220291 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119) ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - ((_theResult___fst_exp__h211490 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123) : - ((_theResult___fst_exp__h220291 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125) ; - assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 = - ((SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39[10], - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - ((_theResult___fst_exp__h172852 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57) : - ((_theResult___fst_exp__h181653 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59) ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 = - ((SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66[10], - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - ((_theResult___fst_exp__h250429 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84) : - ((_theResult___fst_exp__h259230 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86) ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - ((_theResult___fst_exp__h250429 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90) : - ((_theResult___fst_exp__h259230 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 = - ((SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141[7], - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 }) - - 9'd386 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - ((_theResult___fst_exp__h295452 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324) : - ((_theResult___fst_exp__h304137 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - ((_theResult___fst_exp__h295452 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409) : - ((_theResult___fst_exp__h304137 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[2] : - _theResult___fst_exp__h304685 == 8'd255 && - _theResult___fst_sfd__h304686 == 23'd0 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[1] : - _theResult___fst_exp__h304137 == 8'd0 && - guard__h296060 != 2'b0 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[0] : - _theResult___fst_exp__h304137 != 8'd255 && - guard__h296060 != 2'b0 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 = - (((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7[10]}}, - fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7 }) - - { 7'd0, b__h4039 }) - - (((fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8[10]}}, - fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8 }) - - { 7'd0, b__h11457 }) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) <= - 13'd5120 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) < - 13'd3020 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) < - 13'd3074 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401) ? - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 : - CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0) ? - 11'd2047 : - ((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353) ? - 11'd0 : - _theResult___fst_exp__h19467) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401) ? - 52'd0 : - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ? - _theResult___fst_sfd__h19957 : - _theResult___fst_sfd__h19468) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54]) ? - { fpu_div64_fOperands_S0$D_OUT[66:55], sfd__h18937 } : - ((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118]) ? - fpu_div64_fOperands_S0$D_OUT[130:67] : - ((fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54]) ? - fpu_div64_fOperands_S0$D_OUT[66:3] : - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452)) ; - assign IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] == 2'b0 && - !fpu_div64_fState_S3$D_OUT[194] : - !fpu_div64_fState_S3$D_OUT[194] ; - assign IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921 = - ((fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - { fpu_div64_fState_S3$D_OUT[129:128], - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[127], - fpu_div64_fState_S3$D_OUT[126], - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[125] } : - fpu_div64_fState_S3$D_OUT[129:125]) | - { 2'd0, - sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023, - _theResult___fst_exp__h42336 == 11'd0 && guard__h33946 != 2'd0, - sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023 } ; - assign IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h42982[53:52] == 2'b01) ? - 11'd1 : - fpu_div64_fState_S4$D_OUT[64:54] ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 = - (fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 && - !fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ? - 63'h7FF8000000000000 : - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 = - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118]) ? - { fpu_madd_fOperand_S0$D_OUT[130:119], sfd__h99405 } : - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54]) ? - { fpu_madd_fOperand_S0$D_OUT[66:55], sfd__h99408 } : - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936) ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 = - { ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128[10]}}, - fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 }) + - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129[10]}}, - fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 }), - x__h114243, - x__h114255 } ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54] || - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 || - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[193:131] : - 63'd0 ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 && - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54] || - NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fProd_S3$D_OUT != 106'd0 || - fpu_madd_fState_S3$D_OUT[83] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[1] ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fProd_S3$D_OUT != 106'd0 || - fpu_madd_fState_S3$D_OUT[82] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[0] ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - (fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - 63'd0 : - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534) : - 63'h7FEFFFFFFFFFFFFF ; - assign IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525 = - fpu_madd_fState_S3$D_OUT[151] ? - fpu_madd_fState_S3$D_OUT[86:82] : - { IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 } ; - assign IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 = - (fpu_madd_fState_S4$D_OUT[128:118] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27[10]}}, - fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27 } ; - assign IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 = - (fpu_madd_fState_S4$D_OUT[64:54] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26[10]}}, - fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26 } ; - assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 = - (value__h141307[10:0] == 11'd0) ? - 12'd3074 : - { value41307_BITS_10_TO_0_MINUS_1023__q28[10], - value41307_BITS_10_TO_0_MINUS_1023__q28 } ; - assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 = - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 - - 12'd3074 ; - assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 = - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd0 && - sfd__h142040[53:52] == 2'b01) ? - 11'd1 : - fpu_madd_fState_S8$D_OUT[65:55] ; - assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 = - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[65:55] : - _theResult___fst_exp__h142619 ; - assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060 = - (fpu_madd_fState_S8$D_OUT[67] && - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 == - 11'd0 && - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h142620) == - 52'd0 && - !fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043[0] && - fpu_madd_fState_S8$D_OUT[0]) ? - fpu_madd_fState_S8$D_OUT[70:68] == 3'd3 : - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[66] : - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127) ; - assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 = - { IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060, - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[65:3] : - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132, - fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 } ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0) ? - (fpu_sqr64_fOperand_S0$D_OUT[54] ? - 6'd2 : - (fpu_sqr64_fOperand_S0$D_OUT[53] ? - 6'd3 : - (fpu_sqr64_fOperand_S0$D_OUT[52] ? - 6'd4 : - (fpu_sqr64_fOperand_S0$D_OUT[51] ? - 6'd5 : - (fpu_sqr64_fOperand_S0$D_OUT[50] ? - 6'd6 : - (fpu_sqr64_fOperand_S0$D_OUT[49] ? - 6'd7 : - (fpu_sqr64_fOperand_S0$D_OUT[48] ? - 6'd8 : - (fpu_sqr64_fOperand_S0$D_OUT[47] ? - 6'd9 : - (fpu_sqr64_fOperand_S0$D_OUT[46] ? - 6'd10 : - (fpu_sqr64_fOperand_S0$D_OUT[45] ? - 6'd11 : - (fpu_sqr64_fOperand_S0$D_OUT[44] ? - 6'd12 : - (fpu_sqr64_fOperand_S0$D_OUT[43] ? - 6'd13 : - (fpu_sqr64_fOperand_S0$D_OUT[42] ? - 6'd14 : - (fpu_sqr64_fOperand_S0$D_OUT[41] ? - 6'd15 : - (fpu_sqr64_fOperand_S0$D_OUT[40] ? - 6'd16 : - (fpu_sqr64_fOperand_S0$D_OUT[39] ? - 6'd17 : - (fpu_sqr64_fOperand_S0$D_OUT[38] ? - 6'd18 : - (fpu_sqr64_fOperand_S0$D_OUT[37] ? - 6'd19 : - (fpu_sqr64_fOperand_S0$D_OUT[36] ? - 6'd20 : - (fpu_sqr64_fOperand_S0$D_OUT[35] ? - 6'd21 : - (fpu_sqr64_fOperand_S0$D_OUT[34] ? - 6'd22 : - (fpu_sqr64_fOperand_S0$D_OUT[33] ? - 6'd23 : - (fpu_sqr64_fOperand_S0$D_OUT[32] ? - 6'd24 : - (fpu_sqr64_fOperand_S0$D_OUT[31] ? - 6'd25 : - (fpu_sqr64_fOperand_S0$D_OUT[30] ? - 6'd26 : - (fpu_sqr64_fOperand_S0$D_OUT[29] ? - 6'd27 : - (fpu_sqr64_fOperand_S0$D_OUT[28] ? - 6'd28 : - (fpu_sqr64_fOperand_S0$D_OUT[27] ? - 6'd29 : - (fpu_sqr64_fOperand_S0$D_OUT[26] ? - 6'd30 : - (fpu_sqr64_fOperand_S0$D_OUT[25] ? - 6'd31 : - (fpu_sqr64_fOperand_S0$D_OUT[24] ? - 6'd32 : - (fpu_sqr64_fOperand_S0$D_OUT[23] ? - 6'd33 : - (fpu_sqr64_fOperand_S0$D_OUT[22] ? - 6'd34 : - (fpu_sqr64_fOperand_S0$D_OUT[21] ? - 6'd35 : - (fpu_sqr64_fOperand_S0$D_OUT[20] ? - 6'd36 : - (fpu_sqr64_fOperand_S0$D_OUT[19] ? - 6'd37 : - (fpu_sqr64_fOperand_S0$D_OUT[18] ? - 6'd38 : - (fpu_sqr64_fOperand_S0$D_OUT[17] ? - 6'd39 : - (fpu_sqr64_fOperand_S0$D_OUT[16] ? - 6'd40 : - (fpu_sqr64_fOperand_S0$D_OUT[15] ? - 6'd41 : - (fpu_sqr64_fOperand_S0$D_OUT[14] ? - 6'd42 : - (fpu_sqr64_fOperand_S0$D_OUT[13] ? - 6'd43 : - (fpu_sqr64_fOperand_S0$D_OUT[12] ? - 6'd44 : - (fpu_sqr64_fOperand_S0$D_OUT[11] ? - 6'd45 : - (fpu_sqr64_fOperand_S0$D_OUT[10] ? - 6'd46 : - (fpu_sqr64_fOperand_S0$D_OUT[9] ? - 6'd47 : - (fpu_sqr64_fOperand_S0$D_OUT[8] ? - 6'd48 : - (fpu_sqr64_fOperand_S0$D_OUT[7] ? - 6'd49 : - (fpu_sqr64_fOperand_S0$D_OUT[6] ? - 6'd50 : - (fpu_sqr64_fOperand_S0$D_OUT[5] ? - 6'd51 : - (fpu_sqr64_fOperand_S0$D_OUT[4] ? - 6'd52 : - (fpu_sqr64_fOperand_S0$D_OUT[3] ? - 6'd53 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1 ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195 = - ((fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16[10]}}, - fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16 }) - - { 7'd0, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 } ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212 = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54] || - fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] == 52'd0 && - !fpu_sqr64_fOperand_S0$D_OUT[66]) ? - { 1'd1, - fpu_sqr64_fOperand_S0$D_OUT[66:3], - 130'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - (fpu_sqr64_fOperand_S0$D_OUT[66] ? - 195'h5FFE00000000000020AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - { 70'h155555555555555540, - fpu_sqr64_fOperand_S0$D_OUT[2:0], - fpu_sqr64_fOperand_S0$D_OUT[66], - x__h52551[10:0], - fpu_sqr64_fOperand_S0$D_OUT[54:3], - x__h60693 }) ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195[12:1] ; - assign IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 = - (fpu_sqr64_fState_S1$D_OUT[57] ? - 7'd0 : - (fpu_sqr64_fState_S1$D_OUT[56] ? - 7'd1 : - (fpu_sqr64_fState_S1$D_OUT[55] ? - 7'd2 : - (fpu_sqr64_fState_S1$D_OUT[54] ? - 7'd3 : - (fpu_sqr64_fState_S1$D_OUT[53] ? - 7'd4 : - (fpu_sqr64_fState_S1$D_OUT[52] ? - 7'd5 : - (fpu_sqr64_fState_S1$D_OUT[51] ? - 7'd6 : - (fpu_sqr64_fState_S1$D_OUT[50] ? - 7'd7 : - (fpu_sqr64_fState_S1$D_OUT[49] ? - 7'd8 : - (fpu_sqr64_fState_S1$D_OUT[48] ? - 7'd9 : - (fpu_sqr64_fState_S1$D_OUT[47] ? - 7'd10 : - (fpu_sqr64_fState_S1$D_OUT[46] ? - 7'd11 : - (fpu_sqr64_fState_S1$D_OUT[45] ? - 7'd12 : - (fpu_sqr64_fState_S1$D_OUT[44] ? - 7'd13 : - (fpu_sqr64_fState_S1$D_OUT[43] ? - 7'd14 : - (fpu_sqr64_fState_S1$D_OUT[42] ? - 7'd15 : - (fpu_sqr64_fState_S1$D_OUT[41] ? - 7'd16 : - (fpu_sqr64_fState_S1$D_OUT[40] ? - 7'd17 : - (fpu_sqr64_fState_S1$D_OUT[39] ? - 7'd18 : - (fpu_sqr64_fState_S1$D_OUT[38] ? - 7'd19 : - (fpu_sqr64_fState_S1$D_OUT[37] ? - 7'd20 : - (fpu_sqr64_fState_S1$D_OUT[36] ? - 7'd21 : - (fpu_sqr64_fState_S1$D_OUT[35] ? - 7'd22 : - (fpu_sqr64_fState_S1$D_OUT[34] ? - 7'd23 : - (fpu_sqr64_fState_S1$D_OUT[33] ? - 7'd24 : - (fpu_sqr64_fState_S1$D_OUT[32] ? - 7'd25 : - (fpu_sqr64_fState_S1$D_OUT[31] ? - 7'd26 : - (fpu_sqr64_fState_S1$D_OUT[30] ? - 7'd27 : - (fpu_sqr64_fState_S1$D_OUT[29] ? - 7'd28 : - (fpu_sqr64_fState_S1$D_OUT[28] ? - 7'd29 : - (fpu_sqr64_fState_S1$D_OUT[27] ? - 7'd30 : - (fpu_sqr64_fState_S1$D_OUT[26] ? - 7'd31 : - (fpu_sqr64_fState_S1$D_OUT[25] ? - 7'd32 : - (fpu_sqr64_fState_S1$D_OUT[24] ? - 7'd33 : - (fpu_sqr64_fState_S1$D_OUT[23] ? - 7'd34 : - (fpu_sqr64_fState_S1$D_OUT[22] ? - 7'd35 : - (fpu_sqr64_fState_S1$D_OUT[21] ? - 7'd36 : - (fpu_sqr64_fState_S1$D_OUT[20] ? - 7'd37 : - (fpu_sqr64_fState_S1$D_OUT[19] ? - 7'd38 : - (fpu_sqr64_fState_S1$D_OUT[18] ? - 7'd39 : - (fpu_sqr64_fState_S1$D_OUT[17] ? - 7'd40 : - (fpu_sqr64_fState_S1$D_OUT[16] ? - 7'd41 : - (fpu_sqr64_fState_S1$D_OUT[15] ? - 7'd42 : - (fpu_sqr64_fState_S1$D_OUT[14] ? - 7'd43 : - (fpu_sqr64_fState_S1$D_OUT[13] ? - 7'd44 : - (fpu_sqr64_fState_S1$D_OUT[12] ? - 7'd45 : - (fpu_sqr64_fState_S1$D_OUT[11] ? - 7'd46 : - (fpu_sqr64_fState_S1$D_OUT[10] ? - 7'd47 : - (fpu_sqr64_fState_S1$D_OUT[9] ? - 7'd48 : - (fpu_sqr64_fState_S1$D_OUT[8] ? - 7'd49 : - (fpu_sqr64_fState_S1$D_OUT[7] ? - 7'd50 : - (fpu_sqr64_fState_S1$D_OUT[6] ? - 7'd51 : - (fpu_sqr64_fState_S1$D_OUT[5] ? - 7'd52 : - (fpu_sqr64_fState_S1$D_OUT[4] ? - 7'd53 : - (fpu_sqr64_fState_S1$D_OUT[3] ? - 7'd54 : - (fpu_sqr64_fState_S1$D_OUT[2] ? - 7'd55 : - (fpu_sqr64_fState_S1$D_OUT[1] ? - 7'd56 : - (fpu_sqr64_fState_S1$D_OUT[0] ? - 7'd57 : - 7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 12'd3074 : - { fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18[10], - fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18 } ; - assign IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 = - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 - - 12'd3074 ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671 = - fpu_sqr64_fState_S3$D_OUT[195] ? - fpu_sqr64_fState_S3$D_OUT[128:126] : - { fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023, - _theResult___fst_exp__h94753 == 11'd0 && - guard__h86435 != 2'd0, - fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023 } ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h94750, sfdin__h94744[58:7] } ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 = - (fpu_sqr64_fState_S3$D_OUT[58] ? - 6'd0 : - (fpu_sqr64_fState_S3$D_OUT[57] ? - 6'd1 : - (fpu_sqr64_fState_S3$D_OUT[56] ? - 6'd2 : - (fpu_sqr64_fState_S3$D_OUT[55] ? - 6'd3 : - (fpu_sqr64_fState_S3$D_OUT[54] ? - 6'd4 : - (fpu_sqr64_fState_S3$D_OUT[53] ? - 6'd5 : - (fpu_sqr64_fState_S3$D_OUT[52] ? - 6'd6 : - (fpu_sqr64_fState_S3$D_OUT[51] ? - 6'd7 : - (fpu_sqr64_fState_S3$D_OUT[50] ? - 6'd8 : - (fpu_sqr64_fState_S3$D_OUT[49] ? - 6'd9 : - (fpu_sqr64_fState_S3$D_OUT[48] ? - 6'd10 : - (fpu_sqr64_fState_S3$D_OUT[47] ? - 6'd11 : - (fpu_sqr64_fState_S3$D_OUT[46] ? - 6'd12 : - (fpu_sqr64_fState_S3$D_OUT[45] ? - 6'd13 : - (fpu_sqr64_fState_S3$D_OUT[44] ? - 6'd14 : - (fpu_sqr64_fState_S3$D_OUT[43] ? - 6'd15 : - (fpu_sqr64_fState_S3$D_OUT[42] ? - 6'd16 : - (fpu_sqr64_fState_S3$D_OUT[41] ? - 6'd17 : - (fpu_sqr64_fState_S3$D_OUT[40] ? - 6'd18 : - (fpu_sqr64_fState_S3$D_OUT[39] ? - 6'd19 : - (fpu_sqr64_fState_S3$D_OUT[38] ? - 6'd20 : - (fpu_sqr64_fState_S3$D_OUT[37] ? - 6'd21 : - (fpu_sqr64_fState_S3$D_OUT[36] ? - 6'd22 : - (fpu_sqr64_fState_S3$D_OUT[35] ? - 6'd23 : - (fpu_sqr64_fState_S3$D_OUT[34] ? - 6'd24 : - (fpu_sqr64_fState_S3$D_OUT[33] ? - 6'd25 : - (fpu_sqr64_fState_S3$D_OUT[32] ? - 6'd26 : - (fpu_sqr64_fState_S3$D_OUT[31] ? - 6'd27 : - (fpu_sqr64_fState_S3$D_OUT[30] ? - 6'd28 : - (fpu_sqr64_fState_S3$D_OUT[29] ? - 6'd29 : - (fpu_sqr64_fState_S3$D_OUT[28] ? - 6'd30 : - (fpu_sqr64_fState_S3$D_OUT[27] ? - 6'd31 : - (fpu_sqr64_fState_S3$D_OUT[26] ? - 6'd32 : - (fpu_sqr64_fState_S3$D_OUT[25] ? - 6'd33 : - (fpu_sqr64_fState_S3$D_OUT[24] ? - 6'd34 : - (fpu_sqr64_fState_S3$D_OUT[23] ? - 6'd35 : - (fpu_sqr64_fState_S3$D_OUT[22] ? - 6'd36 : - (fpu_sqr64_fState_S3$D_OUT[21] ? - 6'd37 : - (fpu_sqr64_fState_S3$D_OUT[20] ? - 6'd38 : - (fpu_sqr64_fState_S3$D_OUT[19] ? - 6'd39 : - (fpu_sqr64_fState_S3$D_OUT[18] ? - 6'd40 : - (fpu_sqr64_fState_S3$D_OUT[17] ? - 6'd41 : - (fpu_sqr64_fState_S3$D_OUT[16] ? - 6'd42 : - (fpu_sqr64_fState_S3$D_OUT[15] ? - 6'd43 : - (fpu_sqr64_fState_S3$D_OUT[14] ? - 6'd44 : - (fpu_sqr64_fState_S3$D_OUT[13] ? - 6'd45 : - (fpu_sqr64_fState_S3$D_OUT[12] ? - 6'd46 : - (fpu_sqr64_fState_S3$D_OUT[11] ? - 6'd47 : - (fpu_sqr64_fState_S3$D_OUT[10] ? - 6'd48 : - (fpu_sqr64_fState_S3$D_OUT[9] ? - 6'd49 : - (fpu_sqr64_fState_S3$D_OUT[8] ? - 6'd50 : - (fpu_sqr64_fState_S3$D_OUT[7] ? - 6'd51 : - (fpu_sqr64_fState_S3$D_OUT[6] ? - 6'd52 : - (fpu_sqr64_fState_S3$D_OUT[5] ? - 6'd53 : - (fpu_sqr64_fState_S3$D_OUT[4] ? - 6'd54 : - (fpu_sqr64_fState_S3$D_OUT[3] ? - 6'd55 : - (fpu_sqr64_fState_S3$D_OUT[2] ? - 6'd56 : - (fpu_sqr64_fState_S3$D_OUT[1] ? - 6'd57 : - (fpu_sqr64_fState_S3$D_OUT[0] ? - 6'd58 : - 6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h95416[53:52] == 2'b01) ? - 11'd1 : - fpu_sqr64_fState_S4$D_OUT[64:54] ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 = - ((iFifo$D_OUT[102:95] == 8'd0) ? - (iFifo$D_OUT[94] ? - 6'd2 : - (iFifo$D_OUT[93] ? - 6'd3 : - (iFifo$D_OUT[92] ? - 6'd4 : - (iFifo$D_OUT[91] ? - 6'd5 : - (iFifo$D_OUT[90] ? - 6'd6 : - (iFifo$D_OUT[89] ? - 6'd7 : - (iFifo$D_OUT[88] ? - 6'd8 : - (iFifo$D_OUT[87] ? - 6'd9 : - (iFifo$D_OUT[86] ? - 6'd10 : - (iFifo$D_OUT[85] ? - 6'd11 : - (iFifo$D_OUT[84] ? - 6'd12 : - (iFifo$D_OUT[83] ? - 6'd13 : - (iFifo$D_OUT[82] ? - 6'd14 : - (iFifo$D_OUT[81] ? - 6'd15 : - (iFifo$D_OUT[80] ? - 6'd16 : - (iFifo$D_OUT[79] ? - 6'd17 : - (iFifo$D_OUT[78] ? - 6'd18 : - (iFifo$D_OUT[77] ? - 6'd19 : - (iFifo$D_OUT[76] ? - 6'd20 : - (iFifo$D_OUT[75] ? - 6'd21 : - (iFifo$D_OUT[74] ? - 6'd22 : - (iFifo$D_OUT[73] ? - 6'd23 : - (iFifo$D_OUT[72] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 = - { (iFifo$D_OUT[102:95] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h221054, - (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0) ? - _theResult___snd_fst_sfd__h183126 : - _theResult___fst_sfd__h221058 } ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 = - { (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0 || - (iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - iFifo$D_OUT[103] : - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 = - { (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0 || - (iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - !iFifo$D_OUT[103] : - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 = - ((iFifo$D_OUT[167:160] == 8'd0) ? - (iFifo$D_OUT[159] ? - 6'd2 : - (iFifo$D_OUT[158] ? - 6'd3 : - (iFifo$D_OUT[157] ? - 6'd4 : - (iFifo$D_OUT[156] ? - 6'd5 : - (iFifo$D_OUT[155] ? - 6'd6 : - (iFifo$D_OUT[154] ? - 6'd7 : - (iFifo$D_OUT[153] ? - 6'd8 : - (iFifo$D_OUT[152] ? - 6'd9 : - (iFifo$D_OUT[151] ? - 6'd10 : - (iFifo$D_OUT[150] ? - 6'd11 : - (iFifo$D_OUT[149] ? - 6'd12 : - (iFifo$D_OUT[148] ? - 6'd13 : - (iFifo$D_OUT[147] ? - 6'd14 : - (iFifo$D_OUT[146] ? - 6'd15 : - (iFifo$D_OUT[145] ? - 6'd16 : - (iFifo$D_OUT[144] ? - 6'd17 : - (iFifo$D_OUT[143] ? - 6'd18 : - (iFifo$D_OUT[142] ? - 6'd19 : - (iFifo$D_OUT[141] ? - 6'd20 : - (iFifo$D_OUT[140] ? - 6'd21 : - (iFifo$D_OUT[139] ? - 6'd22 : - (iFifo$D_OUT[138] ? - 6'd23 : - (iFifo$D_OUT[137] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 = - { (iFifo$D_OUT[167:160] == 8'd255 && - iFifo$D_OUT[159:137] != 23'd0 || - (iFifo$D_OUT[167:160] == 8'd255 || - iFifo$D_OUT[167:160] == 8'd0) && - iFifo$D_OUT[159:137] == 23'd0) ? - iFifo$D_OUT[168] : - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665, - (iFifo$D_OUT[167:160] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h182416, - (iFifo$D_OUT[167:160] == 8'd255 && - iFifo$D_OUT[159:137] != 23'd0) ? - _theResult___snd_fst_sfd__h144486 : - _theResult___fst_sfd__h182420 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 = - ((iFifo$D_OUT[37:30] == 8'd0) ? - (iFifo$D_OUT[29] ? - 6'd2 : - (iFifo$D_OUT[28] ? - 6'd3 : - (iFifo$D_OUT[27] ? - 6'd4 : - (iFifo$D_OUT[26] ? - 6'd5 : - (iFifo$D_OUT[25] ? - 6'd6 : - (iFifo$D_OUT[24] ? - 6'd7 : - (iFifo$D_OUT[23] ? - 6'd8 : - (iFifo$D_OUT[22] ? - 6'd9 : - (iFifo$D_OUT[21] ? - 6'd10 : - (iFifo$D_OUT[20] ? - 6'd11 : - (iFifo$D_OUT[19] ? - 6'd12 : - (iFifo$D_OUT[18] ? - 6'd13 : - (iFifo$D_OUT[17] ? - 6'd14 : - (iFifo$D_OUT[16] ? - 6'd15 : - (iFifo$D_OUT[15] ? - 6'd16 : - (iFifo$D_OUT[14] ? - 6'd17 : - (iFifo$D_OUT[13] ? - 6'd18 : - (iFifo$D_OUT[12] ? - 6'd19 : - (iFifo$D_OUT[11] ? - 6'd20 : - (iFifo$D_OUT[10] ? - 6'd21 : - (iFifo$D_OUT[9] ? - 6'd22 : - (iFifo$D_OUT[8] ? - 6'd23 : - (iFifo$D_OUT[7] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 = - { (iFifo$D_OUT[37:30] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h259993, - (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0) ? - _theResult___snd_fst_sfd__h222065 : - _theResult___fst_sfd__h259997 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 = - { (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 || - (iFifo$D_OUT[37:30] == 8'd255 || - iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - iFifo$D_OUT[38] : - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 = - { (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 || - (iFifo$D_OUT[37:30] == 8'd255 || - iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - !iFifo$D_OUT[38] : - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ; - assign IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 = - iFifo$D_OUT[136] ? - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 : - iFifo$D_OUT[135:72] ; - assign IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 = - iFifo$D_OUT[201] ? - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 : - iFifo$D_OUT[200:137] ; - assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555 = - iFifo$D_OUT[71] ? - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 : - iFifo$D_OUT[70:7] ; - assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 = - iFifo$D_OUT[71] ? - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 : - { iFifo$D_OUT[71] || !iFifo$D_OUT[70], iFifo$D_OUT[69:7] } ; - assign IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657 = - isDoubleFifo$D_OUT ? - { isNegateFifo$D_OUT ^ resWire$wget[68], resWire$wget[67:5] } : - { 32'hAAAAAAAA, - IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424, - exp__h304706, - sfd__h304707 } ; - assign IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424 = - isNegateFifo$D_OUT ? - ((resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0 || - (resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - !resWire$wget[68] : - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377) : - ((resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0 || - (resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - resWire$wget[68] : - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 = - ((resWire$wget[67:57] == 11'd0) ? - (resWire$wget[56] ? - 6'd2 : - (resWire$wget[55] ? - 6'd3 : - (resWire$wget[54] ? - 6'd4 : - (resWire$wget[53] ? - 6'd5 : - (resWire$wget[52] ? - 6'd6 : - (resWire$wget[51] ? - 6'd7 : - (resWire$wget[50] ? - 6'd8 : - (resWire$wget[49] ? - 6'd9 : - (resWire$wget[48] ? - 6'd10 : - (resWire$wget[47] ? - 6'd11 : - (resWire$wget[46] ? - 6'd12 : - (resWire$wget[45] ? - 6'd13 : - (resWire$wget[44] ? - 6'd14 : - (resWire$wget[43] ? - 6'd15 : - (resWire$wget[42] ? - 6'd16 : - (resWire$wget[41] ? - 6'd17 : - (resWire$wget[40] ? - 6'd18 : - (resWire$wget[39] ? - 6'd19 : - (resWire$wget[38] ? - 6'd20 : - (resWire$wget[37] ? - 6'd21 : - (resWire$wget[36] ? - 6'd22 : - (resWire$wget[35] ? - 6'd23 : - (resWire$wget[34] ? - 6'd24 : - (resWire$wget[33] ? - 6'd25 : - (resWire$wget[32] ? - 6'd26 : - (resWire$wget[31] ? - 6'd27 : - (resWire$wget[30] ? - 6'd28 : - (resWire$wget[29] ? - 6'd29 : - (resWire$wget[28] ? - 6'd30 : - (resWire$wget[27] ? - 6'd31 : - (resWire$wget[26] ? - 6'd32 : - (resWire$wget[25] ? - 6'd33 : - (resWire$wget[24] ? - 6'd34 : - (resWire$wget[23] ? - 6'd35 : - (resWire$wget[22] ? - 6'd36 : - (resWire$wget[21] ? - 6'd37 : - (resWire$wget[20] ? - 6'd38 : - (resWire$wget[19] ? - 6'd39 : - (resWire$wget[18] ? - 6'd40 : - (resWire$wget[17] ? - 6'd41 : - (resWire$wget[16] ? - 6'd42 : - (resWire$wget[15] ? - 6'd43 : - (resWire$wget[14] ? - 6'd44 : - (resWire$wget[13] ? - 6'd45 : - (resWire$wget[12] ? - 6'd46 : - (resWire$wget[11] ? - 6'd47 : - (resWire$wget[10] ? - 6'd48 : - (resWire$wget[9] ? - 6'd49 : - (resWire$wget[8] ? - 6'd50 : - (resWire$wget[7] ? - 6'd51 : - (resWire$wget[6] ? - 6'd52 : - (resWire$wget[5] ? - 6'd53 : - 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[4] ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[3] ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736 = - (resWire$wget[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 : - !SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 || - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 = - (resWire$wget[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 : - !SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 || - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 = - rg_index_1_4_ULE_58___d38 ? _theResult___fst__h1515 : rg_b ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 = - rg_index_1_4_ULE_58___d38 ? - _theResult___snd_snd_snd__h1520 : - rg_r_1 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 = - rg_index_1_4_ULE_58___d38 ? - IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72 : - rg_res[115:0] ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 = - rg_index_1_4_ULE_58___d38 ? _theResult___snd_fst__h1517 : rg_s ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 < - sum__h1710 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 = - rg_index_1_4_ULE_58___d38 ? - rg_b != 116'd0 && !rg_res[116] : - !rg_res[116] ; - assign IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44 = - rg_index_1_4_ULE_58___d38 ? - rg_b == 116'd0 || rg_res[116] : - rg_res[116] ; - assign IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 = - rg_index_ULE_57___d7 ? - (rg_r[115] ? - { rg_r[114:0], 1'd0 } + b__h32583 : - { rg_r[114:0], 1'd0 } - b__h32583) : - rg_r ; - assign IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 = - rg_index_ULE_57___d7 ? { rg_q[56:0], !rg_r[115] } : rg_q ; - assign IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10 = - rg_r[115] ? - rg_q_PLUS_NEG_INV_rg_q_59_60___d561 - 58'd1 : - rg_q_PLUS_NEG_INV_rg_q_59_60___d561 ; - assign IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72 = - rg_res[116] ? - rg_res[115:0] : - ((rg_b == 116'd0) ? rg_r_1 : rg_res[115:0]) ; - assign IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98 = - sfdin__h211484[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13 = - sfdin__h42327[5] ? 2'd2 : 2'd0 ; - assign IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25 = - sfdin__h130943[53] ? 2'd2 : 2'd0 ; - assign IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30 = - sfdin__h141369[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20 = - sfdin__h94744[6] ? 2'd2 : 2'd0 ; - assign IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65 = - sfdin__h250423[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38 = - sfdin__h172846[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134 = - sfdin__h277680[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140 = - sfdin__h295446[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94 = - _theResult___snd__h201925[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143 = - _theResult___snd__h304083[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101 = - _theResult___snd__h220237[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61 = - _theResult___snd__h240864[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68 = - _theResult___snd__h259176[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34 = - _theResult___snd__h163287[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41 = - _theResult___snd__h181599[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136 = - _theResult___snd__h286293[33] ? 2'd2 : 2'd0 ; - assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 = - !_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 || - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[2] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 = - !_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 || - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[0] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[0]) ; - assign NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 = - (x__h96539 != 11'd2047 || !_theResult___fst_sfd__h96608[51]) && - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - !fpu_madd_fOperand_S0$D_OUT[118]) && - (fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - !fpu_madd_fOperand_S0$D_OUT[54]) && - (fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 && - !fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 = - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452 = - { NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 && - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436 ? - 52'h8000000000000 : - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450 } ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481 = - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 && - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488 = - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (!IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355) ; - assign NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923 = - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) && - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) && - (x__h96539 != 11'd2047 || - _theResult___fst_sfd__h96608 != 52'd0 || - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0) && - (fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) || - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) && - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 ; - assign NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 = - fpu_madd_fOperand_S0$D_OUT[130] != - fpu_madd_fOperand_S0$D_OUT[66] ; - assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510 = - !fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - (fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fState_S3$D_OUT[84] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[2]) ; - assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 = - { NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 : - fpu_madd_fState_S3$D_OUT[83], - !fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 } ; - assign NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 = - !fpu_madd_fState_S4$D_OUT[130] || - (IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 ^ - 13'h1000) > - (IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 ^ - 13'h1000) || - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 == - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 && - sfdBC__h131578 > sfdA__h131577 ; - assign NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 = - !iFifo$D_OUT[158] && !iFifo$D_OUT[157] && !iFifo$D_OUT[156] && - !iFifo$D_OUT[155] && - !iFifo$D_OUT[154] && - !iFifo$D_OUT[153] && - !iFifo$D_OUT[152] && - !iFifo$D_OUT[151] && - !iFifo$D_OUT[150] && - !iFifo$D_OUT[149] && - !iFifo$D_OUT[148] && - !iFifo$D_OUT[147] && - !iFifo$D_OUT[146] && - !iFifo$D_OUT[145] && - !iFifo$D_OUT[144] && - !iFifo$D_OUT[143] && - !iFifo$D_OUT[142] && - !iFifo$D_OUT[141] && - !iFifo$D_OUT[140] && - !iFifo$D_OUT[139] && - !iFifo$D_OUT[138] && - !iFifo$D_OUT[137] ; - assign NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 = - !iFifo$D_OUT[28] && !iFifo$D_OUT[27] && !iFifo$D_OUT[26] && - !iFifo$D_OUT[25] && - !iFifo$D_OUT[24] && - !iFifo$D_OUT[23] && - !iFifo$D_OUT[22] && - !iFifo$D_OUT[21] && - !iFifo$D_OUT[20] && - !iFifo$D_OUT[19] && - !iFifo$D_OUT[18] && - !iFifo$D_OUT[17] && - !iFifo$D_OUT[16] && - !iFifo$D_OUT[15] && - !iFifo$D_OUT[14] && - !iFifo$D_OUT[13] && - !iFifo$D_OUT[12] && - !iFifo$D_OUT[11] && - !iFifo$D_OUT[10] && - !iFifo$D_OUT[9] && - !iFifo$D_OUT[8] && - !iFifo$D_OUT[7] ; - assign NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 = - !iFifo$D_OUT[93] && !iFifo$D_OUT[92] && !iFifo$D_OUT[91] && - !iFifo$D_OUT[90] && - !iFifo$D_OUT[89] && - !iFifo$D_OUT[88] && - !iFifo$D_OUT[87] && - !iFifo$D_OUT[86] && - !iFifo$D_OUT[85] && - !iFifo$D_OUT[84] && - !iFifo$D_OUT[83] && - !iFifo$D_OUT[82] && - !iFifo$D_OUT[81] && - !iFifo$D_OUT[80] && - !iFifo$D_OUT[79] && - !iFifo$D_OUT[78] && - !iFifo$D_OUT[77] && - !iFifo$D_OUT[76] && - !iFifo$D_OUT[75] && - !iFifo$D_OUT[74] && - !iFifo$D_OUT[73] && - !iFifo$D_OUT[72] ; - assign NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 = - !resWire$wget[56] && !resWire$wget[55] && !resWire$wget[54] && - !resWire$wget[53] && - !resWire$wget[52] && - !resWire$wget[51] && - !resWire$wget[50] && - !resWire$wget[49] && - !resWire$wget[48] && - !resWire$wget[47] && - !resWire$wget[46] && - !resWire$wget[45] && - !resWire$wget[44] && - !resWire$wget[43] && - !resWire$wget[42] && - !resWire$wget[41] && - !resWire$wget[40] && - !resWire$wget[39] && - !resWire$wget[38] && - !resWire$wget[37] && - !resWire$wget[36] && - !resWire$wget[35] && - !resWire$wget[34] && - !resWire$wget[33] && - !resWire$wget[32] && - !resWire$wget[31] && - !resWire$wget[30] && - !resWire$wget[29] && - !resWire$wget[28] && - !resWire$wget[27] && - !resWire$wget[26] && - !resWire$wget[25] && - !resWire$wget[24] && - !resWire$wget[23] && - !resWire$wget[22] && - !resWire$wget[21] && - !resWire$wget[20] && - !resWire$wget[19] && - !resWire$wget[18] && - !resWire$wget[17] && - !resWire$wget[16] && - !resWire$wget[15] && - !resWire$wget[14] && - !resWire$wget[13] && - !resWire$wget[12] && - !resWire$wget[11] && - !resWire$wget[10] && - !resWire$wget[9] && - !resWire$wget[8] && - !resWire$wget[7] && - !resWire$wget[6] && - !resWire$wget[5] ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 = - { {4{iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95[7]}}, - iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 } ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] - - 11'd1023 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 = - { {4{iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35[7]}}, - iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 } ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] - - 11'd1023 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 = - { {4{iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62[7]}}, - iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 } ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] - - 11'd1023 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 = - { resWirewget_BITS_67_TO_57_MINUS_1023__q137[10], - resWirewget_BITS_67_TO_57_MINUS_1023__q137 } ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 + - 12'd127 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] - - 8'd127 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 = - ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676 = - { 3'd0, - _theResult___fst_exp__h277686 == 8'd0 && - (sfdin__h277680[56:34] == 23'd0 || guard__h269587 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h278283 == 8'd255 && - _theResult___fst_sfd__h278284 == 23'd0, - 1'd0, - _theResult___fst_exp__h277686 != 8'd255 && - guard__h269587 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 = - ({ 3'd0, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705 = - { 3'd0, - _theResult___fst_exp__h295452 == 8'd0 && - (sfdin__h295446[56:34] == 23'd0 || guard__h287224 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h296049 == 8'd255 && - _theResult___fst_sfd__h296050 == 23'd0, - 1'd0, - _theResult___fst_exp__h295452 != 8'd255 && - guard__h287224 != 2'b0 } ; - assign _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 = - ({ 5'd0, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ^ - 12'h800) <= - (IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883 = - ({ 6'd0, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 } ^ - 12'h800) <= - (IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 = - ({ 6'd0, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ^ - 12'h800) <= - (IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ^ - 12'h800) ; - assign _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633 = - ({ 6'd0, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 } ^ - 12'h800) <= - (IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 = - ({ 6'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 = - ({ 6'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 = - ({ 6'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 = - ({ 6'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 = - ({ 6'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 = - ({ 6'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ^ - 12'h800) ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 = - ({ 3'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 = - ({ 3'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^ - 9'h100) <= - (IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ^ - 9'h100) ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688 = - { 3'd0, - _theResult___fst_exp__h286342 == 8'd0 && - guard__h278294 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h286865 == 8'd255 && - _theResult___fst_sfd__h286866 == 23'd0, - 1'd0, - _theResult___fst_exp__h286342 != 8'd255 && - guard__h278294 != 2'b0 } ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813 = - sfd__h183176 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330 = - sfd__h144536 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038 = - sfd__h222115 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ; - assign _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038 = - sfd__h261975 >> - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 = - 12'd3074 - - { 6'd0, - resWire$wget[56] ? - 6'd0 : - (resWire$wget[55] ? - 6'd1 : - (resWire$wget[54] ? - 6'd2 : - (resWire$wget[53] ? - 6'd3 : - (resWire$wget[52] ? - 6'd4 : - (resWire$wget[51] ? - 6'd5 : - (resWire$wget[50] ? - 6'd6 : - (resWire$wget[49] ? - 6'd7 : - (resWire$wget[48] ? - 6'd8 : - (resWire$wget[47] ? - 6'd9 : - (resWire$wget[46] ? - 6'd10 : - (resWire$wget[45] ? - 6'd11 : - (resWire$wget[44] ? - 6'd12 : - (resWire$wget[43] ? - 6'd13 : - (resWire$wget[42] ? - 6'd14 : - (resWire$wget[41] ? - 6'd15 : - (resWire$wget[40] ? - 6'd16 : - (resWire$wget[39] ? - 6'd17 : - (resWire$wget[38] ? - 6'd18 : - (resWire$wget[37] ? - 6'd19 : - (resWire$wget[36] ? - 6'd20 : - (resWire$wget[35] ? - 6'd21 : - (resWire$wget[34] ? - 6'd22 : - (resWire$wget[33] ? - 6'd23 : - (resWire$wget[32] ? - 6'd24 : - (resWire$wget[31] ? - 6'd25 : - (resWire$wget[30] ? - 6'd26 : - (resWire$wget[29] ? - 6'd27 : - (resWire$wget[28] ? - 6'd28 : - (resWire$wget[27] ? - 6'd29 : - (resWire$wget[26] ? - 6'd30 : - (resWire$wget[25] ? - 6'd31 : - (resWire$wget[24] ? - 6'd32 : - (resWire$wget[23] ? - 6'd33 : - (resWire$wget[22] ? - 6'd34 : - (resWire$wget[21] ? - 6'd35 : - (resWire$wget[20] ? - 6'd36 : - (resWire$wget[19] ? - 6'd37 : - (resWire$wget[18] ? - 6'd38 : - (resWire$wget[17] ? - 6'd39 : - (resWire$wget[16] ? - 6'd40 : - (resWire$wget[15] ? - 6'd41 : - (resWire$wget[14] ? - 6'd42 : - (resWire$wget[13] ? - 6'd43 : - (resWire$wget[12] ? - 6'd44 : - (resWire$wget[11] ? - 6'd45 : - (resWire$wget[10] ? - 6'd46 : - (resWire$wget[9] ? - 6'd47 : - (resWire$wget[8] ? - 6'd48 : - (resWire$wget[7] ? - 6'd49 : - (resWire$wget[6] ? - 6'd50 : - (resWire$wget[5] ? - 6'd51 : - 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 = - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^ - 12'h800) <= - 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 = - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^ - 12'h800) < - 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[4] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[4]) ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[3] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[3]) ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[1] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[1]) ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[159] ? - 5'd0 : - (iFifo$D_OUT[158] ? - 5'd1 : - (iFifo$D_OUT[157] ? - 5'd2 : - (iFifo$D_OUT[156] ? - 5'd3 : - (iFifo$D_OUT[155] ? - 5'd4 : - (iFifo$D_OUT[154] ? - 5'd5 : - (iFifo$D_OUT[153] ? - 5'd6 : - (iFifo$D_OUT[152] ? - 5'd7 : - (iFifo$D_OUT[151] ? - 5'd8 : - (iFifo$D_OUT[150] ? - 5'd9 : - (iFifo$D_OUT[149] ? - 5'd10 : - (iFifo$D_OUT[148] ? - 5'd11 : - (iFifo$D_OUT[147] ? - 5'd12 : - (iFifo$D_OUT[146] ? - 5'd13 : - (iFifo$D_OUT[145] ? - 5'd14 : - (iFifo$D_OUT[144] ? - 5'd15 : - (iFifo$D_OUT[143] ? - 5'd16 : - (iFifo$D_OUT[142] ? - 5'd17 : - (iFifo$D_OUT[141] ? - 5'd18 : - (iFifo$D_OUT[140] ? - 5'd19 : - (iFifo$D_OUT[139] ? - 5'd20 : - (iFifo$D_OUT[138] ? - 5'd21 : - (iFifo$D_OUT[137] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[29] ? - 5'd0 : - (iFifo$D_OUT[28] ? - 5'd1 : - (iFifo$D_OUT[27] ? - 5'd2 : - (iFifo$D_OUT[26] ? - 5'd3 : - (iFifo$D_OUT[25] ? - 5'd4 : - (iFifo$D_OUT[24] ? - 5'd5 : - (iFifo$D_OUT[23] ? - 5'd6 : - (iFifo$D_OUT[22] ? - 5'd7 : - (iFifo$D_OUT[21] ? - 5'd8 : - (iFifo$D_OUT[20] ? - 5'd9 : - (iFifo$D_OUT[19] ? - 5'd10 : - (iFifo$D_OUT[18] ? - 5'd11 : - (iFifo$D_OUT[17] ? - 5'd12 : - (iFifo$D_OUT[16] ? - 5'd13 : - (iFifo$D_OUT[15] ? - 5'd14 : - (iFifo$D_OUT[14] ? - 5'd15 : - (iFifo$D_OUT[13] ? - 5'd16 : - (iFifo$D_OUT[12] ? - 5'd17 : - (iFifo$D_OUT[11] ? - 5'd18 : - (iFifo$D_OUT[10] ? - 5'd19 : - (iFifo$D_OUT[9] ? - 5'd20 : - (iFifo$D_OUT[8] ? - 5'd21 : - (iFifo$D_OUT[7] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[94] ? - 5'd0 : - (iFifo$D_OUT[93] ? - 5'd1 : - (iFifo$D_OUT[92] ? - 5'd2 : - (iFifo$D_OUT[91] ? - 5'd3 : - (iFifo$D_OUT[90] ? - 5'd4 : - (iFifo$D_OUT[89] ? - 5'd5 : - (iFifo$D_OUT[88] ? - 5'd6 : - (iFifo$D_OUT[87] ? - 5'd7 : - (iFifo$D_OUT[86] ? - 5'd8 : - (iFifo$D_OUT[85] ? - 5'd9 : - (iFifo$D_OUT[84] ? - 5'd10 : - (iFifo$D_OUT[83] ? - 5'd11 : - (iFifo$D_OUT[82] ? - 5'd12 : - (iFifo$D_OUT[81] ? - 5'd13 : - (iFifo$D_OUT[80] ? - 5'd14 : - (iFifo$D_OUT[79] ? - 5'd15 : - (iFifo$D_OUT[78] ? - 5'd16 : - (iFifo$D_OUT[77] ? - 5'd17 : - (iFifo$D_OUT[76] ? - 5'd18 : - (iFifo$D_OUT[75] ? - 5'd19 : - (iFifo$D_OUT[74] ? - 5'd20 : - (iFifo$D_OUT[73] ? - 5'd21 : - (iFifo$D_OUT[72] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 = - 12'd3970 - - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ; - assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 = - 13'd7170 - fpu_madd_fState_S3$D_OUT[12:0] ; - assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 = - (_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ^ - 13'h1000) <= - 13'd4096 ; - assign _theResult____h164614 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ^ - 12'h800) < - 12'd2105) ? - result__h165227 : - ((value__h148923 == 25'd0) ? sfd__h144536 : 57'd1) ; - assign _theResult____h203252 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ^ - 12'h800) < - 12'd2105) ? - result__h203865 : - ((value__h187561 == 25'd0) ? sfd__h183176 : 57'd1) ; - assign _theResult____h242191 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ^ - 12'h800) < - 12'd2105) ? - result__h242804 : - ((value__h226500 == 25'd0) ? sfd__h222115 : 57'd1) ; - assign _theResult____h269577 = - (value__h270197 == 54'd0) ? sfd__h261975 : 57'd1 ; - assign _theResult____h287214 = - ((_3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ^ - 12'h800) < - 12'd2105) ? - result__h287827 : - _theResult____h269577 ; - assign _theResult____h32523 = - (fpu_div64_fState_S2$D_OUT[10:0] < 11'd58) ? - result__h32648 : - result__h32823 ; - assign _theResult___exp__h142541 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h142626) : - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 ; - assign _theResult___exp__h163981 = - sfd__h163354[53] ? - ((_theResult___fst_exp__h163336 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182469) : - ((_theResult___fst_exp__h163336 == 11'd0 && - sfd__h163354[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h163336) ; - assign _theResult___exp__h173571 = - sfd__h172944[53] ? - ((_theResult___fst_exp__h172852 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182504) : - ((_theResult___fst_exp__h172852 == 11'd0 && - sfd__h172944[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h172852) ; - assign _theResult___exp__h182323 = - sfd__h181672[53] ? - ((_theResult___fst_exp__h181653 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182530) : - ((_theResult___fst_exp__h181653 == 11'd0 && - sfd__h181672[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h181653) ; - assign _theResult___exp__h202619 = - sfd__h201992[53] ? - ((_theResult___fst_exp__h201974 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221107) : - ((_theResult___fst_exp__h201974 == 11'd0 && - sfd__h201992[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h201974) ; - assign _theResult___exp__h212209 = - sfd__h211582[53] ? - ((_theResult___fst_exp__h211490 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221142) : - ((_theResult___fst_exp__h211490 == 11'd0 && - sfd__h211582[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h211490) ; - assign _theResult___exp__h220961 = - sfd__h220310[53] ? - ((_theResult___fst_exp__h220291 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221168) : - ((_theResult___fst_exp__h220291 == 11'd0 && - sfd__h220310[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h220291) ; - assign _theResult___exp__h241558 = - sfd__h240931[53] ? - ((_theResult___fst_exp__h240913 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260046) : - ((_theResult___fst_exp__h240913 == 11'd0 && - sfd__h240931[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h240913) ; - assign _theResult___exp__h251148 = - sfd__h250521[53] ? - ((_theResult___fst_exp__h250429 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260081) : - ((_theResult___fst_exp__h250429 == 11'd0 && - sfd__h250521[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h250429) ; - assign _theResult___exp__h259900 = - sfd__h259249[53] ? - ((_theResult___fst_exp__h259230 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260107) : - ((_theResult___fst_exp__h259230 == 11'd0 && - sfd__h259249[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h259230) ; - assign _theResult___exp__h278202 = - sfd__h277778[24] ? - ((_theResult___fst_exp__h277686 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304723) : - ((_theResult___fst_exp__h277686 == 8'd0 && - sfd__h277778[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h277686) ; - assign _theResult___exp__h286784 = - sfd__h286360[24] ? - ((_theResult___fst_exp__h286342 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304749) : - ((_theResult___fst_exp__h286342 == 8'd0 && - sfd__h286360[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h286342) ; - assign _theResult___exp__h295968 = - sfd__h295544[24] ? - ((_theResult___fst_exp__h295452 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304784) : - ((_theResult___fst_exp__h295452 == 8'd0 && - sfd__h295544[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h295452) ; - assign _theResult___exp__h304604 = - sfd__h304156[24] ? - ((_theResult___fst_exp__h304137 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304810) : - ((_theResult___fst_exp__h304137 == 8'd0 && - sfd__h304156[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h304137) ; - assign _theResult___exp__h43475 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h43566) : - IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977 ; - assign _theResult___exp__h95909 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h96000) : - IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721 ; - assign _theResult___fst__h116827 = - { fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[105:1], - fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[0] | - sfdlsb__h116825 } ; - assign _theResult___fst__h1476 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___fst__h1600 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign _theResult___fst__h1515 = - (rg_res[116] || rg_b == 116'd0) ? rg_b : b__h1608 ; - assign _theResult___fst__h1600 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 : - b__h1712 ; - assign _theResult___fst__h31322 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499 ? - value__h31550[10:0] : - 11'd0 ; - assign _theResult___fst_exp__h130949 = - sfdBC__h115662[105] ? - _theResult___fst_exp__h130971 : - _theResult___fst_exp__h131034 ; - assign _theResult___fst_exp__h130952 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h130949 ; - assign _theResult___fst_exp__h130971 = - (din_exp__h130866 == 11'd0) ? 11'd2 : din_exp__h130866 + 11'd1 ; - assign _theResult___fst_exp__h130986 = - (din_exp__h130866 == 11'd0) ? 11'd1 : din_exp__h130866 ; - assign _theResult___fst_exp__h131025 = - din_exp__h130866 - - { 4'd0, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ; - assign _theResult___fst_exp__h131031 = - (!sfdBC__h115662[105] && !sfdBC__h115662[104] && - !sfdBC__h115662[103] && - !sfdBC__h115662[102] && - !sfdBC__h115662[101] && - !sfdBC__h115662[100] && - !sfdBC__h115662[99] && - !sfdBC__h115662[98] && - !sfdBC__h115662[97] && - !sfdBC__h115662[96] && - !sfdBC__h115662[95] && - !sfdBC__h115662[94] && - !sfdBC__h115662[93] && - !sfdBC__h115662[92] && - !sfdBC__h115662[91] && - !sfdBC__h115662[90] && - !sfdBC__h115662[89] && - !sfdBC__h115662[88] && - !sfdBC__h115662[87] && - !sfdBC__h115662[86] && - !sfdBC__h115662[85] && - !sfdBC__h115662[84] && - !sfdBC__h115662[83] && - !sfdBC__h115662[82] && - !sfdBC__h115662[81] && - !sfdBC__h115662[80] && - !sfdBC__h115662[79] && - !sfdBC__h115662[78] && - !sfdBC__h115662[77] && - !sfdBC__h115662[76] && - !sfdBC__h115662[75] && - !sfdBC__h115662[74] && - !sfdBC__h115662[73] && - !sfdBC__h115662[72] && - !sfdBC__h115662[71] && - !sfdBC__h115662[70] && - !sfdBC__h115662[69] && - !sfdBC__h115662[68] && - !sfdBC__h115662[67] && - !sfdBC__h115662[66] && - !sfdBC__h115662[65] && - !sfdBC__h115662[64] && - !sfdBC__h115662[63] && - !sfdBC__h115662[62] && - !sfdBC__h115662[61] && - !sfdBC__h115662[60] && - !sfdBC__h115662[59] && - !sfdBC__h115662[58] && - !sfdBC__h115662[57] && - !sfdBC__h115662[56] && - !sfdBC__h115662[55] && - !sfdBC__h115662[54] && - !sfdBC__h115662[53] && - !sfdBC__h115662[52] && - !sfdBC__h115662[51] && - !sfdBC__h115662[50] && - !sfdBC__h115662[49] && - !sfdBC__h115662[48] && - !sfdBC__h115662[47] && - !sfdBC__h115662[46] && - !sfdBC__h115662[45] && - !sfdBC__h115662[44] && - !sfdBC__h115662[43] && - !sfdBC__h115662[42] && - !sfdBC__h115662[41] && - !sfdBC__h115662[40] && - !sfdBC__h115662[39] && - !sfdBC__h115662[38] && - !sfdBC__h115662[37] && - !sfdBC__h115662[36] && - !sfdBC__h115662[35] && - !sfdBC__h115662[34] && - !sfdBC__h115662[33] && - !sfdBC__h115662[32] && - !sfdBC__h115662[31] && - !sfdBC__h115662[30] && - !sfdBC__h115662[29] && - !sfdBC__h115662[28] && - !sfdBC__h115662[27] && - !sfdBC__h115662[26] && - !sfdBC__h115662[25] && - !sfdBC__h115662[24] && - !sfdBC__h115662[23] && - !sfdBC__h115662[22] && - !sfdBC__h115662[21] && - !sfdBC__h115662[20] && - !sfdBC__h115662[19] && - !sfdBC__h115662[18] && - !sfdBC__h115662[17] && - !sfdBC__h115662[16] && - !sfdBC__h115662[15] && - !sfdBC__h115662[14] && - !sfdBC__h115662[13] && - !sfdBC__h115662[12] && - !sfdBC__h115662[11] && - !sfdBC__h115662[10] && - !sfdBC__h115662[9] && - !sfdBC__h115662[8] && - !sfdBC__h115662[7] && - !sfdBC__h115662[6] && - !sfdBC__h115662[5] && - !sfdBC__h115662[4] && - !sfdBC__h115662[3] && - !sfdBC__h115662[2] && - !sfdBC__h115662[1] && - !sfdBC__h115662[0] || - !_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463) ? - 11'd0 : - _theResult___fst_exp__h131025 ; - assign _theResult___fst_exp__h131034 = - (!sfdBC__h115662[105] && sfdBC__h115662[104]) ? - _theResult___fst_exp__h130986 : - _theResult___fst_exp__h131031 ; - assign _theResult___fst_exp__h141375 = - sfd__h133119[56] ? - _theResult___fst_exp__h141397 : - _theResult___fst_exp__h141460 ; - assign _theResult___fst_exp__h141378 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h141375 ; - assign _theResult___fst_exp__h141397 = - (value__h141307[10:0] == 11'd0) ? - 11'd2 : - value__h141307[10:0] + 11'd1 ; - assign _theResult___fst_exp__h141412 = - (value__h141307[10:0] == 11'd0) ? 11'd1 : value__h141307[10:0] ; - assign _theResult___fst_exp__h141451 = - value__h141307[10:0] - - { 5'd0, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ; - assign _theResult___fst_exp__h141457 = - (!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] && - !sfd__h133119[53] && - !sfd__h133119[52] && - !sfd__h133119[51] && - !sfd__h133119[50] && - !sfd__h133119[49] && - !sfd__h133119[48] && - !sfd__h133119[47] && - !sfd__h133119[46] && - !sfd__h133119[45] && - !sfd__h133119[44] && - !sfd__h133119[43] && - !sfd__h133119[42] && - !sfd__h133119[41] && - !sfd__h133119[40] && - !sfd__h133119[39] && - !sfd__h133119[38] && - !sfd__h133119[37] && - !sfd__h133119[36] && - !sfd__h133119[35] && - !sfd__h133119[34] && - !sfd__h133119[33] && - !sfd__h133119[32] && - !sfd__h133119[31] && - !sfd__h133119[30] && - !sfd__h133119[29] && - !sfd__h133119[28] && - !sfd__h133119[27] && - !sfd__h133119[26] && - !sfd__h133119[25] && - !sfd__h133119[24] && - !sfd__h133119[23] && - !sfd__h133119[22] && - !sfd__h133119[21] && - !sfd__h133119[20] && - !sfd__h133119[19] && - !sfd__h133119[18] && - !sfd__h133119[17] && - !sfd__h133119[16] && - !sfd__h133119[15] && - !sfd__h133119[14] && - !sfd__h133119[13] && - !sfd__h133119[12] && - !sfd__h133119[11] && - !sfd__h133119[10] && - !sfd__h133119[9] && - !sfd__h133119[8] && - !sfd__h133119[7] && - !sfd__h133119[6] && - !sfd__h133119[5] && - !sfd__h133119[4] && - !sfd__h133119[3] && - !sfd__h133119[2] && - !sfd__h133119[1] && - !sfd__h133119[0] || - !_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904) ? - 11'd0 : - _theResult___fst_exp__h141451 ; - assign _theResult___fst_exp__h141460 = - (!sfd__h133119[56] && sfd__h133119[55]) ? - _theResult___fst_exp__h141412 : - _theResult___fst_exp__h141457 ; - assign _theResult___fst_exp__h163327 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ; - assign _theResult___fst_exp__h163333 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 || - !_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273) ? - 11'd0 : - _theResult___fst_exp__h163327 ; - assign _theResult___fst_exp__h163336 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___fst_exp__h163333 : - 11'd897 ; - assign _theResult___fst_exp__h164062 = - (_theResult___fst_exp__h163336 == 11'd2047) ? - _theResult___fst_exp__h163336 : - _theResult___fst_exp__h164059 ; - assign _theResult___fst_exp__h172852 = - _theResult____h164614[56] ? - 11'd2 : - _theResult___fst_exp__h172926 ; - assign _theResult___fst_exp__h172917 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ; - assign _theResult___fst_exp__h172923 = - (!_theResult____h164614[56] && !_theResult____h164614[55] && - !_theResult____h164614[54] && - !_theResult____h164614[53] && - !_theResult____h164614[52] && - !_theResult____h164614[51] && - !_theResult____h164614[50] && - !_theResult____h164614[49] && - !_theResult____h164614[48] && - !_theResult____h164614[47] && - !_theResult____h164614[46] && - !_theResult____h164614[45] && - !_theResult____h164614[44] && - !_theResult____h164614[43] && - !_theResult____h164614[42] && - !_theResult____h164614[41] && - !_theResult____h164614[40] && - !_theResult____h164614[39] && - !_theResult____h164614[38] && - !_theResult____h164614[37] && - !_theResult____h164614[36] && - !_theResult____h164614[35] && - !_theResult____h164614[34] && - !_theResult____h164614[33] && - !_theResult____h164614[32] && - !_theResult____h164614[31] && - !_theResult____h164614[30] && - !_theResult____h164614[29] && - !_theResult____h164614[28] && - !_theResult____h164614[27] && - !_theResult____h164614[26] && - !_theResult____h164614[25] && - !_theResult____h164614[24] && - !_theResult____h164614[23] && - !_theResult____h164614[22] && - !_theResult____h164614[21] && - !_theResult____h164614[20] && - !_theResult____h164614[19] && - !_theResult____h164614[18] && - !_theResult____h164614[17] && - !_theResult____h164614[16] && - !_theResult____h164614[15] && - !_theResult____h164614[14] && - !_theResult____h164614[13] && - !_theResult____h164614[12] && - !_theResult____h164614[11] && - !_theResult____h164614[10] && - !_theResult____h164614[9] && - !_theResult____h164614[8] && - !_theResult____h164614[7] && - !_theResult____h164614[6] && - !_theResult____h164614[5] && - !_theResult____h164614[4] && - !_theResult____h164614[3] && - !_theResult____h164614[2] && - !_theResult____h164614[1] && - !_theResult____h164614[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574) ? - 11'd0 : - _theResult___fst_exp__h172917 ; - assign _theResult___fst_exp__h172926 = - (!_theResult____h164614[56] && _theResult____h164614[55]) ? - 11'd1 : - _theResult___fst_exp__h172923 ; - assign _theResult___fst_exp__h173652 = - (_theResult___fst_exp__h172852 == 11'd2047) ? - _theResult___fst_exp__h172852 : - _theResult___fst_exp__h173649 ; - assign _theResult___fst_exp__h181605 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] ; - assign _theResult___fst_exp__h181644 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ; - assign _theResult___fst_exp__h181650 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 || - !_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624) ? - 11'd0 : - _theResult___fst_exp__h181644 ; - assign _theResult___fst_exp__h181653 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___fst_exp__h181650 : - _theResult___fst_exp__h181605 ; - assign _theResult___fst_exp__h182404 = - (_theResult___fst_exp__h181653 == 11'd2047) ? - _theResult___fst_exp__h181653 : - _theResult___fst_exp__h182401 ; - assign _theResult___fst_exp__h182413 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - _theResult___snd_fst_exp__h164065 : - _theResult___fst_exp__h148291) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - _theResult___snd_fst_exp__h182407 : - _theResult___fst_exp__h148291) ; - assign _theResult___fst_exp__h182416 = - (iFifo$D_OUT[167:160] == 8'd0 && iFifo$D_OUT[159:137] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h182413 ; - assign _theResult___fst_exp__h201965 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ; - assign _theResult___fst_exp__h201971 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 || - !_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759) ? - 11'd0 : - _theResult___fst_exp__h201965 ; - assign _theResult___fst_exp__h201974 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___fst_exp__h201971 : - 11'd897 ; - assign _theResult___fst_exp__h202700 = - (_theResult___fst_exp__h201974 == 11'd2047) ? - _theResult___fst_exp__h201974 : - _theResult___fst_exp__h202697 ; - assign _theResult___fst_exp__h211490 = - _theResult____h203252[56] ? - 11'd2 : - _theResult___fst_exp__h211564 ; - assign _theResult___fst_exp__h211555 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ; - assign _theResult___fst_exp__h211561 = - (!_theResult____h203252[56] && !_theResult____h203252[55] && - !_theResult____h203252[54] && - !_theResult____h203252[53] && - !_theResult____h203252[52] && - !_theResult____h203252[51] && - !_theResult____h203252[50] && - !_theResult____h203252[49] && - !_theResult____h203252[48] && - !_theResult____h203252[47] && - !_theResult____h203252[46] && - !_theResult____h203252[45] && - !_theResult____h203252[44] && - !_theResult____h203252[43] && - !_theResult____h203252[42] && - !_theResult____h203252[41] && - !_theResult____h203252[40] && - !_theResult____h203252[39] && - !_theResult____h203252[38] && - !_theResult____h203252[37] && - !_theResult____h203252[36] && - !_theResult____h203252[35] && - !_theResult____h203252[34] && - !_theResult____h203252[33] && - !_theResult____h203252[32] && - !_theResult____h203252[31] && - !_theResult____h203252[30] && - !_theResult____h203252[29] && - !_theResult____h203252[28] && - !_theResult____h203252[27] && - !_theResult____h203252[26] && - !_theResult____h203252[25] && - !_theResult____h203252[24] && - !_theResult____h203252[23] && - !_theResult____h203252[22] && - !_theResult____h203252[21] && - !_theResult____h203252[20] && - !_theResult____h203252[19] && - !_theResult____h203252[18] && - !_theResult____h203252[17] && - !_theResult____h203252[16] && - !_theResult____h203252[15] && - !_theResult____h203252[14] && - !_theResult____h203252[13] && - !_theResult____h203252[12] && - !_theResult____h203252[11] && - !_theResult____h203252[10] && - !_theResult____h203252[9] && - !_theResult____h203252[8] && - !_theResult____h203252[7] && - !_theResult____h203252[6] && - !_theResult____h203252[5] && - !_theResult____h203252[4] && - !_theResult____h203252[3] && - !_theResult____h203252[2] && - !_theResult____h203252[1] && - !_theResult____h203252[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057) ? - 11'd0 : - _theResult___fst_exp__h211555 ; - assign _theResult___fst_exp__h211564 = - (!_theResult____h203252[56] && _theResult____h203252[55]) ? - 11'd1 : - _theResult___fst_exp__h211561 ; - assign _theResult___fst_exp__h212290 = - (_theResult___fst_exp__h211490 == 11'd2047) ? - _theResult___fst_exp__h211490 : - _theResult___fst_exp__h212287 ; - assign _theResult___fst_exp__h220243 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] ; - assign _theResult___fst_exp__h220282 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ; - assign _theResult___fst_exp__h220288 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 || - !_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107) ? - 11'd0 : - _theResult___fst_exp__h220282 ; - assign _theResult___fst_exp__h220291 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___fst_exp__h220288 : - _theResult___fst_exp__h220243 ; - assign _theResult___fst_exp__h221042 = - (_theResult___fst_exp__h220291 == 11'd2047) ? - _theResult___fst_exp__h220291 : - _theResult___fst_exp__h221039 ; - assign _theResult___fst_exp__h221051 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - _theResult___snd_fst_exp__h202703 : - _theResult___fst_exp__h186931) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - _theResult___snd_fst_exp__h221045 : - _theResult___fst_exp__h186931) ; - assign _theResult___fst_exp__h221054 = - (iFifo$D_OUT[102:95] == 8'd0 && iFifo$D_OUT[94:72] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h221051 ; - assign _theResult___fst_exp__h240904 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ; - assign _theResult___fst_exp__h240910 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 || - !_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984) ? - 11'd0 : - _theResult___fst_exp__h240904 ; - assign _theResult___fst_exp__h240913 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___fst_exp__h240910 : - 11'd897 ; - assign _theResult___fst_exp__h241639 = - (_theResult___fst_exp__h240913 == 11'd2047) ? - _theResult___fst_exp__h240913 : - _theResult___fst_exp__h241636 ; - assign _theResult___fst_exp__h250429 = - _theResult____h242191[56] ? - 11'd2 : - _theResult___fst_exp__h250503 ; - assign _theResult___fst_exp__h250494 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ; - assign _theResult___fst_exp__h250500 = - (!_theResult____h242191[56] && !_theResult____h242191[55] && - !_theResult____h242191[54] && - !_theResult____h242191[53] && - !_theResult____h242191[52] && - !_theResult____h242191[51] && - !_theResult____h242191[50] && - !_theResult____h242191[49] && - !_theResult____h242191[48] && - !_theResult____h242191[47] && - !_theResult____h242191[46] && - !_theResult____h242191[45] && - !_theResult____h242191[44] && - !_theResult____h242191[43] && - !_theResult____h242191[42] && - !_theResult____h242191[41] && - !_theResult____h242191[40] && - !_theResult____h242191[39] && - !_theResult____h242191[38] && - !_theResult____h242191[37] && - !_theResult____h242191[36] && - !_theResult____h242191[35] && - !_theResult____h242191[34] && - !_theResult____h242191[33] && - !_theResult____h242191[32] && - !_theResult____h242191[31] && - !_theResult____h242191[30] && - !_theResult____h242191[29] && - !_theResult____h242191[28] && - !_theResult____h242191[27] && - !_theResult____h242191[26] && - !_theResult____h242191[25] && - !_theResult____h242191[24] && - !_theResult____h242191[23] && - !_theResult____h242191[22] && - !_theResult____h242191[21] && - !_theResult____h242191[20] && - !_theResult____h242191[19] && - !_theResult____h242191[18] && - !_theResult____h242191[17] && - !_theResult____h242191[16] && - !_theResult____h242191[15] && - !_theResult____h242191[14] && - !_theResult____h242191[13] && - !_theResult____h242191[12] && - !_theResult____h242191[11] && - !_theResult____h242191[10] && - !_theResult____h242191[9] && - !_theResult____h242191[8] && - !_theResult____h242191[7] && - !_theResult____h242191[6] && - !_theResult____h242191[5] && - !_theResult____h242191[4] && - !_theResult____h242191[3] && - !_theResult____h242191[2] && - !_theResult____h242191[1] && - !_theResult____h242191[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282) ? - 11'd0 : - _theResult___fst_exp__h250494 ; - assign _theResult___fst_exp__h250503 = - (!_theResult____h242191[56] && _theResult____h242191[55]) ? - 11'd1 : - _theResult___fst_exp__h250500 ; - assign _theResult___fst_exp__h251229 = - (_theResult___fst_exp__h250429 == 11'd2047) ? - _theResult___fst_exp__h250429 : - _theResult___fst_exp__h251226 ; - assign _theResult___fst_exp__h259182 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] ; - assign _theResult___fst_exp__h259221 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ; - assign _theResult___fst_exp__h259227 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 || - !_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332) ? - 11'd0 : - _theResult___fst_exp__h259221 ; - assign _theResult___fst_exp__h259230 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___fst_exp__h259227 : - _theResult___fst_exp__h259182 ; - assign _theResult___fst_exp__h259981 = - (_theResult___fst_exp__h259230 == 11'd2047) ? - _theResult___fst_exp__h259230 : - _theResult___fst_exp__h259978 ; - assign _theResult___fst_exp__h259990 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - _theResult___snd_fst_exp__h241642 : - _theResult___fst_exp__h225870) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - _theResult___snd_fst_exp__h259984 : - _theResult___fst_exp__h225870) ; - assign _theResult___fst_exp__h259993 = - (iFifo$D_OUT[37:30] == 8'd0 && iFifo$D_OUT[29:7] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h259990 ; - assign _theResult___fst_exp__h277686 = - _theResult____h269577[56] ? - 8'd2 : - _theResult___fst_exp__h277760 ; - assign _theResult___fst_exp__h277751 = - 8'd0 - - { 2'd0, - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ; - assign _theResult___fst_exp__h277757 = - (!_theResult____h269577[56] && !_theResult____h269577[55] && - !_theResult____h269577[54] && - !_theResult____h269577[53] && - !_theResult____h269577[52] && - !_theResult____h269577[51] && - !_theResult____h269577[50] && - !_theResult____h269577[49] && - !_theResult____h269577[48] && - !_theResult____h269577[47] && - !_theResult____h269577[46] && - !_theResult____h269577[45] && - !_theResult____h269577[44] && - !_theResult____h269577[43] && - !_theResult____h269577[42] && - !_theResult____h269577[41] && - !_theResult____h269577[40] && - !_theResult____h269577[39] && - !_theResult____h269577[38] && - !_theResult____h269577[37] && - !_theResult____h269577[36] && - !_theResult____h269577[35] && - !_theResult____h269577[34] && - !_theResult____h269577[33] && - !_theResult____h269577[32] && - !_theResult____h269577[31] && - !_theResult____h269577[30] && - !_theResult____h269577[29] && - !_theResult____h269577[28] && - !_theResult____h269577[27] && - !_theResult____h269577[26] && - !_theResult____h269577[25] && - !_theResult____h269577[24] && - !_theResult____h269577[23] && - !_theResult____h269577[22] && - !_theResult____h269577[21] && - !_theResult____h269577[20] && - !_theResult____h269577[19] && - !_theResult____h269577[18] && - !_theResult____h269577[17] && - !_theResult____h269577[16] && - !_theResult____h269577[15] && - !_theResult____h269577[14] && - !_theResult____h269577[13] && - !_theResult____h269577[12] && - !_theResult____h269577[11] && - !_theResult____h269577[10] && - !_theResult____h269577[9] && - !_theResult____h269577[8] && - !_theResult____h269577[7] && - !_theResult____h269577[6] && - !_theResult____h269577[5] && - !_theResult____h269577[4] && - !_theResult____h269577[3] && - !_theResult____h269577[2] && - !_theResult____h269577[1] && - !_theResult____h269577[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769) ? - 8'd0 : - _theResult___fst_exp__h277751 ; - assign _theResult___fst_exp__h277760 = - (!_theResult____h269577[56] && _theResult____h269577[55]) ? - 8'd1 : - _theResult___fst_exp__h277757 ; - assign _theResult___fst_exp__h278283 = - (_theResult___fst_exp__h277686 == 8'd255) ? - _theResult___fst_exp__h277686 : - _theResult___fst_exp__h278280 ; - assign _theResult___fst_exp__h286333 = - 8'd129 - - { 2'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ; - assign _theResult___fst_exp__h286339 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 || - !_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984) ? - 8'd0 : - _theResult___fst_exp__h286333 ; - assign _theResult___fst_exp__h286342 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___fst_exp__h286339 : - 8'd129 ; - assign _theResult___fst_exp__h286865 = - (_theResult___fst_exp__h286342 == 8'd255) ? - _theResult___fst_exp__h286342 : - _theResult___fst_exp__h286862 ; - assign _theResult___fst_exp__h295452 = - _theResult____h287214[56] ? - 8'd2 : - _theResult___fst_exp__h295526 ; - assign _theResult___fst_exp__h295517 = - 8'd0 - - { 2'd0, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ; - assign _theResult___fst_exp__h295523 = - (!_theResult____h287214[56] && !_theResult____h287214[55] && - !_theResult____h287214[54] && - !_theResult____h287214[53] && - !_theResult____h287214[52] && - !_theResult____h287214[51] && - !_theResult____h287214[50] && - !_theResult____h287214[49] && - !_theResult____h287214[48] && - !_theResult____h287214[47] && - !_theResult____h287214[46] && - !_theResult____h287214[45] && - !_theResult____h287214[44] && - !_theResult____h287214[43] && - !_theResult____h287214[42] && - !_theResult____h287214[41] && - !_theResult____h287214[40] && - !_theResult____h287214[39] && - !_theResult____h287214[38] && - !_theResult____h287214[37] && - !_theResult____h287214[36] && - !_theResult____h287214[35] && - !_theResult____h287214[34] && - !_theResult____h287214[33] && - !_theResult____h287214[32] && - !_theResult____h287214[31] && - !_theResult____h287214[30] && - !_theResult____h287214[29] && - !_theResult____h287214[28] && - !_theResult____h287214[27] && - !_theResult____h287214[26] && - !_theResult____h287214[25] && - !_theResult____h287214[24] && - !_theResult____h287214[23] && - !_theResult____h287214[22] && - !_theResult____h287214[21] && - !_theResult____h287214[20] && - !_theResult____h287214[19] && - !_theResult____h287214[18] && - !_theResult____h287214[17] && - !_theResult____h287214[16] && - !_theResult____h287214[15] && - !_theResult____h287214[14] && - !_theResult____h287214[13] && - !_theResult____h287214[12] && - !_theResult____h287214[11] && - !_theResult____h287214[10] && - !_theResult____h287214[9] && - !_theResult____h287214[8] && - !_theResult____h287214[7] && - !_theResult____h287214[6] && - !_theResult____h287214[5] && - !_theResult____h287214[4] && - !_theResult____h287214[3] && - !_theResult____h287214[2] && - !_theResult____h287214[1] && - !_theResult____h287214[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280) ? - 8'd0 : - _theResult___fst_exp__h295517 ; - assign _theResult___fst_exp__h295526 = - (!_theResult____h287214[56] && _theResult____h287214[55]) ? - 8'd1 : - _theResult___fst_exp__h295523 ; - assign _theResult___fst_exp__h296049 = - (_theResult___fst_exp__h295452 == 8'd255) ? - _theResult___fst_exp__h295452 : - _theResult___fst_exp__h296046 ; - assign _theResult___fst_exp__h304089 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] == - 8'd0) ? - 8'd1 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] ; - assign _theResult___fst_exp__h304128 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] - - { 2'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ; - assign _theResult___fst_exp__h304134 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 || - !_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333) ? - 8'd0 : - _theResult___fst_exp__h304128 ; - assign _theResult___fst_exp__h304137 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___fst_exp__h304134 : - _theResult___fst_exp__h304089 ; - assign _theResult___fst_exp__h304685 = - (_theResult___fst_exp__h304137 == 8'd255) ? - _theResult___fst_exp__h304137 : - _theResult___fst_exp__h304682 ; - assign _theResult___fst_exp__h304694 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - _theResult___snd_fst_exp__h286868 : - _theResult___fst_exp__h269559) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - _theResult___snd_fst_exp__h304688 : - _theResult___fst_exp__h269559) ; - assign _theResult___fst_exp__h304697 = - (resWire$wget[67:57] == 11'd0 && resWire$wget[56:5] == 52'd0) ? - 8'd0 : - _theResult___fst_exp__h304694 ; - assign _theResult___fst_exp__h42284 = - fpu_div64_fState_S3$D_OUT[120:110] - 11'd1 ; - assign _theResult___fst_exp__h42287 = - (fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___fst_exp__h42284 : - 11'd2046 ; - assign _theResult___fst_exp__h42290 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___fst_exp__h42287 : - fpu_div64_fState_S3$D_OUT[120:110] ; - assign _theResult___fst_exp__h42333 = - sfdin__h34118[57] ? - _theResult___fst_exp__h42356 : - _theResult___fst_exp__h42420 ; - assign _theResult___fst_exp__h42336 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h42333 ; - assign _theResult___fst_exp__h42356 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 11'd2 : - _theResult___fst_exp__h42290 + 11'd1 ; - assign _theResult___fst_exp__h42372 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 11'd1 : - _theResult___fst_exp__h42290 ; - assign _theResult___fst_exp__h42411 = - _theResult___fst_exp__h42290 - - { 5'd0, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 } ; - assign _theResult___fst_exp__h42417 = - (!sfdin__h34118[57] && !sfdin__h34118[56] && - !sfdin__h34118[55] && - !sfdin__h34118[54] && - !sfdin__h34118[53] && - !sfdin__h34118[52] && - !sfdin__h34118[51] && - !sfdin__h34118[50] && - !sfdin__h34118[49] && - !sfdin__h34118[48] && - !sfdin__h34118[47] && - !sfdin__h34118[46] && - !sfdin__h34118[45] && - !sfdin__h34118[44] && - !sfdin__h34118[43] && - !sfdin__h34118[42] && - !sfdin__h34118[41] && - !sfdin__h34118[40] && - !sfdin__h34118[39] && - !sfdin__h34118[38] && - !sfdin__h34118[37] && - !sfdin__h34118[36] && - !sfdin__h34118[35] && - !sfdin__h34118[34] && - !sfdin__h34118[33] && - !sfdin__h34118[32] && - !sfdin__h34118[31] && - !sfdin__h34118[30] && - !sfdin__h34118[29] && - !sfdin__h34118[28] && - !sfdin__h34118[27] && - !sfdin__h34118[26] && - !sfdin__h34118[25] && - !sfdin__h34118[24] && - !sfdin__h34118[23] && - !sfdin__h34118[22] && - !sfdin__h34118[21] && - !sfdin__h34118[20] && - !sfdin__h34118[19] && - !sfdin__h34118[18] && - !sfdin__h34118[17] && - !sfdin__h34118[16] && - !sfdin__h34118[15] && - !sfdin__h34118[14] && - !sfdin__h34118[13] && - !sfdin__h34118[12] && - !sfdin__h34118[11] && - !sfdin__h34118[10] && - !sfdin__h34118[9] && - !sfdin__h34118[8] && - !sfdin__h34118[7] && - !sfdin__h34118[6] && - !sfdin__h34118[5] && - !sfdin__h34118[4] && - !sfdin__h34118[3] && - !sfdin__h34118[2] && - !sfdin__h34118[1] && - !sfdin__h34118[0] || - !_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883) ? - 11'd0 : - _theResult___fst_exp__h42411 ; - assign _theResult___fst_exp__h42420 = - (!sfdin__h34118[57] && sfdin__h34118[56]) ? - _theResult___fst_exp__h42372 : - _theResult___fst_exp__h42417 ; - assign _theResult___fst_exp__h43556 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h43553 ; - assign _theResult___fst_exp__h94750 = - fpu_sqr64_fState_S3$D_OUT[58] ? - _theResult___fst_exp__h94773 : - _theResult___fst_exp__h94837 ; - assign _theResult___fst_exp__h94753 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h94750 ; - assign _theResult___fst_exp__h94773 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd2 : - fpu_sqr64_fState_S3$D_OUT[121:111] + 11'd1 ; - assign _theResult___fst_exp__h94789 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd1 : - fpu_sqr64_fState_S3$D_OUT[121:111] ; - assign _theResult___fst_exp__h94828 = - fpu_sqr64_fState_S3$D_OUT[121:111] - - { 5'd0, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 } ; - assign _theResult___fst_exp__h94834 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - !fpu_sqr64_fState_S3$D_OUT[57] && - !fpu_sqr64_fState_S3$D_OUT[56] && - !fpu_sqr64_fState_S3$D_OUT[55] && - !fpu_sqr64_fState_S3$D_OUT[54] && - !fpu_sqr64_fState_S3$D_OUT[53] && - !fpu_sqr64_fState_S3$D_OUT[52] && - !fpu_sqr64_fState_S3$D_OUT[51] && - !fpu_sqr64_fState_S3$D_OUT[50] && - !fpu_sqr64_fState_S3$D_OUT[49] && - !fpu_sqr64_fState_S3$D_OUT[48] && - !fpu_sqr64_fState_S3$D_OUT[47] && - !fpu_sqr64_fState_S3$D_OUT[46] && - !fpu_sqr64_fState_S3$D_OUT[45] && - !fpu_sqr64_fState_S3$D_OUT[44] && - !fpu_sqr64_fState_S3$D_OUT[43] && - !fpu_sqr64_fState_S3$D_OUT[42] && - !fpu_sqr64_fState_S3$D_OUT[41] && - !fpu_sqr64_fState_S3$D_OUT[40] && - !fpu_sqr64_fState_S3$D_OUT[39] && - !fpu_sqr64_fState_S3$D_OUT[38] && - !fpu_sqr64_fState_S3$D_OUT[37] && - !fpu_sqr64_fState_S3$D_OUT[36] && - !fpu_sqr64_fState_S3$D_OUT[35] && - !fpu_sqr64_fState_S3$D_OUT[34] && - !fpu_sqr64_fState_S3$D_OUT[33] && - !fpu_sqr64_fState_S3$D_OUT[32] && - !fpu_sqr64_fState_S3$D_OUT[31] && - !fpu_sqr64_fState_S3$D_OUT[30] && - !fpu_sqr64_fState_S3$D_OUT[29] && - !fpu_sqr64_fState_S3$D_OUT[28] && - !fpu_sqr64_fState_S3$D_OUT[27] && - !fpu_sqr64_fState_S3$D_OUT[26] && - !fpu_sqr64_fState_S3$D_OUT[25] && - !fpu_sqr64_fState_S3$D_OUT[24] && - !fpu_sqr64_fState_S3$D_OUT[23] && - !fpu_sqr64_fState_S3$D_OUT[22] && - !fpu_sqr64_fState_S3$D_OUT[21] && - !fpu_sqr64_fState_S3$D_OUT[20] && - !fpu_sqr64_fState_S3$D_OUT[19] && - !fpu_sqr64_fState_S3$D_OUT[18] && - !fpu_sqr64_fState_S3$D_OUT[17] && - !fpu_sqr64_fState_S3$D_OUT[16] && - !fpu_sqr64_fState_S3$D_OUT[15] && - !fpu_sqr64_fState_S3$D_OUT[14] && - !fpu_sqr64_fState_S3$D_OUT[13] && - !fpu_sqr64_fState_S3$D_OUT[12] && - !fpu_sqr64_fState_S3$D_OUT[11] && - !fpu_sqr64_fState_S3$D_OUT[10] && - !fpu_sqr64_fState_S3$D_OUT[9] && - !fpu_sqr64_fState_S3$D_OUT[8] && - !fpu_sqr64_fState_S3$D_OUT[7] && - !fpu_sqr64_fState_S3$D_OUT[6] && - !fpu_sqr64_fState_S3$D_OUT[5] && - !fpu_sqr64_fState_S3$D_OUT[4] && - !fpu_sqr64_fState_S3$D_OUT[3] && - !fpu_sqr64_fState_S3$D_OUT[2] && - !fpu_sqr64_fState_S3$D_OUT[1] && - !fpu_sqr64_fState_S3$D_OUT[0] || - !_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633) ? - 11'd0 : - _theResult___fst_exp__h94828 ; - assign _theResult___fst_exp__h94837 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - fpu_sqr64_fState_S3$D_OUT[57]) ? - _theResult___fst_exp__h94789 : - _theResult___fst_exp__h94834 ; - assign _theResult___fst_exp__h95990 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h95987 ; - assign _theResult___fst_sfd__h164063 = - (_theResult___fst_exp__h163336 == 11'd2047) ? - _theResult___snd__h163287[56:5] : - _theResult___fst_sfd__h164060 ; - assign _theResult___fst_sfd__h173653 = - (_theResult___fst_exp__h172852 == 11'd2047) ? - sfdin__h172846[56:5] : - _theResult___fst_sfd__h173650 ; - assign _theResult___fst_sfd__h182405 = - (_theResult___fst_exp__h181653 == 11'd2047) ? - _theResult___snd__h181599[56:5] : - _theResult___fst_sfd__h182402 ; - assign _theResult___fst_sfd__h182414 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - _theResult___snd_fst_sfd__h164066 : - _theResult___fst_sfd__h148292) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - _theResult___snd_fst_sfd__h182408 : - _theResult___fst_sfd__h148292) ; - assign _theResult___fst_sfd__h182420 = - ((iFifo$D_OUT[167:160] == 8'd255 || - iFifo$D_OUT[167:160] == 8'd0) && - iFifo$D_OUT[159:137] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h182414 ; - assign _theResult___fst_sfd__h202701 = - (_theResult___fst_exp__h201974 == 11'd2047) ? - _theResult___snd__h201925[56:5] : - _theResult___fst_sfd__h202698 ; - assign _theResult___fst_sfd__h212291 = - (_theResult___fst_exp__h211490 == 11'd2047) ? - sfdin__h211484[56:5] : - _theResult___fst_sfd__h212288 ; - assign _theResult___fst_sfd__h221043 = - (_theResult___fst_exp__h220291 == 11'd2047) ? - _theResult___snd__h220237[56:5] : - _theResult___fst_sfd__h221040 ; - assign _theResult___fst_sfd__h221052 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - _theResult___snd_fst_sfd__h202704 : - _theResult___fst_sfd__h186932) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - _theResult___snd_fst_sfd__h221046 : - _theResult___fst_sfd__h186932) ; - assign _theResult___fst_sfd__h221058 = - ((iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h221052 ; - assign _theResult___fst_sfd__h241640 = - (_theResult___fst_exp__h240913 == 11'd2047) ? - _theResult___snd__h240864[56:5] : - _theResult___fst_sfd__h241637 ; - assign _theResult___fst_sfd__h251230 = - (_theResult___fst_exp__h250429 == 11'd2047) ? - sfdin__h250423[56:5] : - _theResult___fst_sfd__h251227 ; - assign _theResult___fst_sfd__h259982 = - (_theResult___fst_exp__h259230 == 11'd2047) ? - _theResult___snd__h259176[56:5] : - _theResult___fst_sfd__h259979 ; - assign _theResult___fst_sfd__h259991 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - _theResult___snd_fst_sfd__h241643 : - _theResult___fst_sfd__h225871) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - _theResult___snd_fst_sfd__h259985 : - _theResult___fst_sfd__h225871) ; - assign _theResult___fst_sfd__h259997 = - ((iFifo$D_OUT[37:30] == 8'd255 || iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h259991 ; - assign _theResult___fst_sfd__h278284 = - (_theResult___fst_exp__h277686 == 8'd255) ? - sfdin__h277680[56:34] : - _theResult___fst_sfd__h278281 ; - assign _theResult___fst_sfd__h286866 = - (_theResult___fst_exp__h286342 == 8'd255) ? - _theResult___snd__h286293[56:34] : - _theResult___fst_sfd__h286863 ; - assign _theResult___fst_sfd__h296050 = - (_theResult___fst_exp__h295452 == 8'd255) ? - sfdin__h295446[56:34] : - _theResult___fst_sfd__h296047 ; - assign _theResult___fst_sfd__h304686 = - (_theResult___fst_exp__h304137 == 8'd255) ? - _theResult___snd__h304083[56:34] : - _theResult___fst_sfd__h304683 ; - assign _theResult___fst_sfd__h304695 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - _theResult___snd_fst_sfd__h286869 : - _theResult___fst_sfd__h269560) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - _theResult___snd_fst_sfd__h304689 : - _theResult___fst_sfd__h269560) ; - assign _theResult___fst_sfd__h304701 = - ((resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - 23'd0 : - _theResult___fst_sfd__h304695 ; - assign _theResult___fst_sfd__h43557 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h43554 ; - assign _theResult___fst_sfd__h95991 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h95988 ; - assign _theResult___fst_sfd__h96608 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[182:131] : - 52'd0 ; - assign _theResult___sfd__h142542 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 52'd0 : - sfd__h142040[52:1]) : - sfd__h142040[51:0] ; - assign _theResult___sfd__h163982 = - sfd__h163354[53] ? - ((_theResult___fst_exp__h163336 == 11'd2046) ? - 52'd0 : - sfd__h163354[52:1]) : - sfd__h163354[51:0] ; - assign _theResult___sfd__h173572 = - sfd__h172944[53] ? - ((_theResult___fst_exp__h172852 == 11'd2046) ? - 52'd0 : - sfd__h172944[52:1]) : - sfd__h172944[51:0] ; - assign _theResult___sfd__h182324 = - sfd__h181672[53] ? - ((_theResult___fst_exp__h181653 == 11'd2046) ? - 52'd0 : - sfd__h181672[52:1]) : - sfd__h181672[51:0] ; - assign _theResult___sfd__h202620 = - sfd__h201992[53] ? - ((_theResult___fst_exp__h201974 == 11'd2046) ? - 52'd0 : - sfd__h201992[52:1]) : - sfd__h201992[51:0] ; - assign _theResult___sfd__h212210 = - sfd__h211582[53] ? - ((_theResult___fst_exp__h211490 == 11'd2046) ? - 52'd0 : - sfd__h211582[52:1]) : - sfd__h211582[51:0] ; - assign _theResult___sfd__h220962 = - sfd__h220310[53] ? - ((_theResult___fst_exp__h220291 == 11'd2046) ? - 52'd0 : - sfd__h220310[52:1]) : - sfd__h220310[51:0] ; - assign _theResult___sfd__h241559 = - sfd__h240931[53] ? - ((_theResult___fst_exp__h240913 == 11'd2046) ? - 52'd0 : - sfd__h240931[52:1]) : - sfd__h240931[51:0] ; - assign _theResult___sfd__h251149 = - sfd__h250521[53] ? - ((_theResult___fst_exp__h250429 == 11'd2046) ? - 52'd0 : - sfd__h250521[52:1]) : - sfd__h250521[51:0] ; - assign _theResult___sfd__h259901 = - sfd__h259249[53] ? - ((_theResult___fst_exp__h259230 == 11'd2046) ? - 52'd0 : - sfd__h259249[52:1]) : - sfd__h259249[51:0] ; - assign _theResult___sfd__h278203 = - sfd__h277778[24] ? - ((_theResult___fst_exp__h277686 == 8'd254) ? - 23'd0 : - sfd__h277778[23:1]) : - sfd__h277778[22:0] ; - assign _theResult___sfd__h286785 = - sfd__h286360[24] ? - ((_theResult___fst_exp__h286342 == 8'd254) ? - 23'd0 : - sfd__h286360[23:1]) : - sfd__h286360[22:0] ; - assign _theResult___sfd__h295969 = - sfd__h295544[24] ? - ((_theResult___fst_exp__h295452 == 8'd254) ? - 23'd0 : - sfd__h295544[23:1]) : - sfd__h295544[22:0] ; - assign _theResult___sfd__h304605 = - sfd__h304156[24] ? - ((_theResult___fst_exp__h304137 == 8'd254) ? - 23'd0 : - sfd__h304156[23:1]) : - sfd__h304156[22:0] ; - assign _theResult___sfd__h43476 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h42982[52:1]) : - sfd__h42982[51:0] ; - assign _theResult___sfd__h95910 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h95416[52:1]) : - sfd__h95416[51:0] ; - assign _theResult___snd__h130966 = { sfdBC__h115662[104:0], 1'd0 } ; - assign _theResult___snd__h130980 = - (!sfdBC__h115662[105] && sfdBC__h115662[104]) ? - _theResult___snd__h130982 : - _theResult___snd__h130994 ; - assign _theResult___snd__h130982 = { sfdBC__h115662[103:0], 2'd0 } ; - assign _theResult___snd__h130994 = - (!sfdBC__h115662[105] && !sfdBC__h115662[104] && - !sfdBC__h115662[103] && - !sfdBC__h115662[102] && - !sfdBC__h115662[101] && - !sfdBC__h115662[100] && - !sfdBC__h115662[99] && - !sfdBC__h115662[98] && - !sfdBC__h115662[97] && - !sfdBC__h115662[96] && - !sfdBC__h115662[95] && - !sfdBC__h115662[94] && - !sfdBC__h115662[93] && - !sfdBC__h115662[92] && - !sfdBC__h115662[91] && - !sfdBC__h115662[90] && - !sfdBC__h115662[89] && - !sfdBC__h115662[88] && - !sfdBC__h115662[87] && - !sfdBC__h115662[86] && - !sfdBC__h115662[85] && - !sfdBC__h115662[84] && - !sfdBC__h115662[83] && - !sfdBC__h115662[82] && - !sfdBC__h115662[81] && - !sfdBC__h115662[80] && - !sfdBC__h115662[79] && - !sfdBC__h115662[78] && - !sfdBC__h115662[77] && - !sfdBC__h115662[76] && - !sfdBC__h115662[75] && - !sfdBC__h115662[74] && - !sfdBC__h115662[73] && - !sfdBC__h115662[72] && - !sfdBC__h115662[71] && - !sfdBC__h115662[70] && - !sfdBC__h115662[69] && - !sfdBC__h115662[68] && - !sfdBC__h115662[67] && - !sfdBC__h115662[66] && - !sfdBC__h115662[65] && - !sfdBC__h115662[64] && - !sfdBC__h115662[63] && - !sfdBC__h115662[62] && - !sfdBC__h115662[61] && - !sfdBC__h115662[60] && - !sfdBC__h115662[59] && - !sfdBC__h115662[58] && - !sfdBC__h115662[57] && - !sfdBC__h115662[56] && - !sfdBC__h115662[55] && - !sfdBC__h115662[54] && - !sfdBC__h115662[53] && - !sfdBC__h115662[52] && - !sfdBC__h115662[51] && - !sfdBC__h115662[50] && - !sfdBC__h115662[49] && - !sfdBC__h115662[48] && - !sfdBC__h115662[47] && - !sfdBC__h115662[46] && - !sfdBC__h115662[45] && - !sfdBC__h115662[44] && - !sfdBC__h115662[43] && - !sfdBC__h115662[42] && - !sfdBC__h115662[41] && - !sfdBC__h115662[40] && - !sfdBC__h115662[39] && - !sfdBC__h115662[38] && - !sfdBC__h115662[37] && - !sfdBC__h115662[36] && - !sfdBC__h115662[35] && - !sfdBC__h115662[34] && - !sfdBC__h115662[33] && - !sfdBC__h115662[32] && - !sfdBC__h115662[31] && - !sfdBC__h115662[30] && - !sfdBC__h115662[29] && - !sfdBC__h115662[28] && - !sfdBC__h115662[27] && - !sfdBC__h115662[26] && - !sfdBC__h115662[25] && - !sfdBC__h115662[24] && - !sfdBC__h115662[23] && - !sfdBC__h115662[22] && - !sfdBC__h115662[21] && - !sfdBC__h115662[20] && - !sfdBC__h115662[19] && - !sfdBC__h115662[18] && - !sfdBC__h115662[17] && - !sfdBC__h115662[16] && - !sfdBC__h115662[15] && - !sfdBC__h115662[14] && - !sfdBC__h115662[13] && - !sfdBC__h115662[12] && - !sfdBC__h115662[11] && - !sfdBC__h115662[10] && - !sfdBC__h115662[9] && - !sfdBC__h115662[8] && - !sfdBC__h115662[7] && - !sfdBC__h115662[6] && - !sfdBC__h115662[5] && - !sfdBC__h115662[4] && - !sfdBC__h115662[3] && - !sfdBC__h115662[2] && - !sfdBC__h115662[1] && - !sfdBC__h115662[0]) ? - sfdBC__h115662 : - _theResult___snd__h131000 ; - assign _theResult___snd__h131000 = - { IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24[103:0], - 2'd0 } ; - assign _theResult___snd__h131018 = - sfdBC__h115662 << - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ; - assign _theResult___snd__h131023 = - sfdBC__h115662 << - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 ; - assign _theResult___snd__h141392 = { sfd__h133119[55:0], 1'd0 } ; - assign _theResult___snd__h141406 = - (!sfd__h133119[56] && sfd__h133119[55]) ? - _theResult___snd__h141408 : - _theResult___snd__h141420 ; - assign _theResult___snd__h141408 = { sfd__h133119[54:0], 2'd0 } ; - assign _theResult___snd__h141420 = - (!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] && - !sfd__h133119[53] && - !sfd__h133119[52] && - !sfd__h133119[51] && - !sfd__h133119[50] && - !sfd__h133119[49] && - !sfd__h133119[48] && - !sfd__h133119[47] && - !sfd__h133119[46] && - !sfd__h133119[45] && - !sfd__h133119[44] && - !sfd__h133119[43] && - !sfd__h133119[42] && - !sfd__h133119[41] && - !sfd__h133119[40] && - !sfd__h133119[39] && - !sfd__h133119[38] && - !sfd__h133119[37] && - !sfd__h133119[36] && - !sfd__h133119[35] && - !sfd__h133119[34] && - !sfd__h133119[33] && - !sfd__h133119[32] && - !sfd__h133119[31] && - !sfd__h133119[30] && - !sfd__h133119[29] && - !sfd__h133119[28] && - !sfd__h133119[27] && - !sfd__h133119[26] && - !sfd__h133119[25] && - !sfd__h133119[24] && - !sfd__h133119[23] && - !sfd__h133119[22] && - !sfd__h133119[21] && - !sfd__h133119[20] && - !sfd__h133119[19] && - !sfd__h133119[18] && - !sfd__h133119[17] && - !sfd__h133119[16] && - !sfd__h133119[15] && - !sfd__h133119[14] && - !sfd__h133119[13] && - !sfd__h133119[12] && - !sfd__h133119[11] && - !sfd__h133119[10] && - !sfd__h133119[9] && - !sfd__h133119[8] && - !sfd__h133119[7] && - !sfd__h133119[6] && - !sfd__h133119[5] && - !sfd__h133119[4] && - !sfd__h133119[3] && - !sfd__h133119[2] && - !sfd__h133119[1] && - !sfd__h133119[0]) ? - sfd__h133119 : - _theResult___snd__h141426 ; - assign _theResult___snd__h141426 = - { IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29[54:0], - 2'd0 } ; - assign _theResult___snd__h141444 = - sfd__h133119 << - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ; - assign _theResult___snd__h141449 = - sfd__h133119 << - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 ; - assign _theResult___snd__h163287 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___snd__h163296 : - _theResult___snd__h163289 ; - assign _theResult___snd__h163289 = { iFifo$D_OUT[159:137], 34'd0 } ; - assign _theResult___snd__h163296 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ? - sfd__h144536 : - _theResult___snd__h163302 ; - assign _theResult___snd__h163302 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33[54:0], - 2'd0 } ; - assign _theResult___snd__h163325 = - sfd__h144536 << - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 ; - assign _theResult___snd__h172863 = { _theResult____h164614[55:0], 1'd0 } ; - assign _theResult___snd__h172874 = - (!_theResult____h164614[56] && _theResult____h164614[55]) ? - _theResult___snd__h172876 : - _theResult___snd__h172886 ; - assign _theResult___snd__h172876 = { _theResult____h164614[54:0], 2'd0 } ; - assign _theResult___snd__h172886 = - (!_theResult____h164614[56] && !_theResult____h164614[55] && - !_theResult____h164614[54] && - !_theResult____h164614[53] && - !_theResult____h164614[52] && - !_theResult____h164614[51] && - !_theResult____h164614[50] && - !_theResult____h164614[49] && - !_theResult____h164614[48] && - !_theResult____h164614[47] && - !_theResult____h164614[46] && - !_theResult____h164614[45] && - !_theResult____h164614[44] && - !_theResult____h164614[43] && - !_theResult____h164614[42] && - !_theResult____h164614[41] && - !_theResult____h164614[40] && - !_theResult____h164614[39] && - !_theResult____h164614[38] && - !_theResult____h164614[37] && - !_theResult____h164614[36] && - !_theResult____h164614[35] && - !_theResult____h164614[34] && - !_theResult____h164614[33] && - !_theResult____h164614[32] && - !_theResult____h164614[31] && - !_theResult____h164614[30] && - !_theResult____h164614[29] && - !_theResult____h164614[28] && - !_theResult____h164614[27] && - !_theResult____h164614[26] && - !_theResult____h164614[25] && - !_theResult____h164614[24] && - !_theResult____h164614[23] && - !_theResult____h164614[22] && - !_theResult____h164614[21] && - !_theResult____h164614[20] && - !_theResult____h164614[19] && - !_theResult____h164614[18] && - !_theResult____h164614[17] && - !_theResult____h164614[16] && - !_theResult____h164614[15] && - !_theResult____h164614[14] && - !_theResult____h164614[13] && - !_theResult____h164614[12] && - !_theResult____h164614[11] && - !_theResult____h164614[10] && - !_theResult____h164614[9] && - !_theResult____h164614[8] && - !_theResult____h164614[7] && - !_theResult____h164614[6] && - !_theResult____h164614[5] && - !_theResult____h164614[4] && - !_theResult____h164614[3] && - !_theResult____h164614[2] && - !_theResult____h164614[1] && - !_theResult____h164614[0]) ? - _theResult____h164614 : - _theResult___snd__h172892 ; - assign _theResult___snd__h172892 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37[54:0], - 2'd0 } ; - assign _theResult___snd__h172915 = - _theResult____h164614 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 ; - assign _theResult___snd__h181599 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___snd__h181613 : - _theResult___snd__h163289 ; - assign _theResult___snd__h181613 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ? - sfd__h144536 : - _theResult___snd__h181619 ; - assign _theResult___snd__h181619 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40[54:0], - 2'd0 } ; - assign _theResult___snd__h181637 = - sfd__h144536 << - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ; - assign _theResult___snd__h201925 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___snd__h201934 : - _theResult___snd__h201927 ; - assign _theResult___snd__h201927 = { iFifo$D_OUT[94:72], 34'd0 } ; - assign _theResult___snd__h201934 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ? - sfd__h183176 : - _theResult___snd__h201940 ; - assign _theResult___snd__h201940 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93[54:0], - 2'd0 } ; - assign _theResult___snd__h201963 = - sfd__h183176 << - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 ; - assign _theResult___snd__h211501 = { _theResult____h203252[55:0], 1'd0 } ; - assign _theResult___snd__h211512 = - (!_theResult____h203252[56] && _theResult____h203252[55]) ? - _theResult___snd__h211514 : - _theResult___snd__h211524 ; - assign _theResult___snd__h211514 = { _theResult____h203252[54:0], 2'd0 } ; - assign _theResult___snd__h211524 = - (!_theResult____h203252[56] && !_theResult____h203252[55] && - !_theResult____h203252[54] && - !_theResult____h203252[53] && - !_theResult____h203252[52] && - !_theResult____h203252[51] && - !_theResult____h203252[50] && - !_theResult____h203252[49] && - !_theResult____h203252[48] && - !_theResult____h203252[47] && - !_theResult____h203252[46] && - !_theResult____h203252[45] && - !_theResult____h203252[44] && - !_theResult____h203252[43] && - !_theResult____h203252[42] && - !_theResult____h203252[41] && - !_theResult____h203252[40] && - !_theResult____h203252[39] && - !_theResult____h203252[38] && - !_theResult____h203252[37] && - !_theResult____h203252[36] && - !_theResult____h203252[35] && - !_theResult____h203252[34] && - !_theResult____h203252[33] && - !_theResult____h203252[32] && - !_theResult____h203252[31] && - !_theResult____h203252[30] && - !_theResult____h203252[29] && - !_theResult____h203252[28] && - !_theResult____h203252[27] && - !_theResult____h203252[26] && - !_theResult____h203252[25] && - !_theResult____h203252[24] && - !_theResult____h203252[23] && - !_theResult____h203252[22] && - !_theResult____h203252[21] && - !_theResult____h203252[20] && - !_theResult____h203252[19] && - !_theResult____h203252[18] && - !_theResult____h203252[17] && - !_theResult____h203252[16] && - !_theResult____h203252[15] && - !_theResult____h203252[14] && - !_theResult____h203252[13] && - !_theResult____h203252[12] && - !_theResult____h203252[11] && - !_theResult____h203252[10] && - !_theResult____h203252[9] && - !_theResult____h203252[8] && - !_theResult____h203252[7] && - !_theResult____h203252[6] && - !_theResult____h203252[5] && - !_theResult____h203252[4] && - !_theResult____h203252[3] && - !_theResult____h203252[2] && - !_theResult____h203252[1] && - !_theResult____h203252[0]) ? - _theResult____h203252 : - _theResult___snd__h211530 ; - assign _theResult___snd__h211530 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97[54:0], - 2'd0 } ; - assign _theResult___snd__h211553 = - _theResult____h203252 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 ; - assign _theResult___snd__h220237 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___snd__h220251 : - _theResult___snd__h201927 ; - assign _theResult___snd__h220251 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ? - sfd__h183176 : - _theResult___snd__h220257 ; - assign _theResult___snd__h220257 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100[54:0], - 2'd0 } ; - assign _theResult___snd__h220275 = - sfd__h183176 << - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ; - assign _theResult___snd__h240864 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___snd__h240873 : - _theResult___snd__h240866 ; - assign _theResult___snd__h240866 = { iFifo$D_OUT[29:7], 34'd0 } ; - assign _theResult___snd__h240873 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ? - sfd__h222115 : - _theResult___snd__h240879 ; - assign _theResult___snd__h240879 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60[54:0], - 2'd0 } ; - assign _theResult___snd__h240902 = - sfd__h222115 << - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 ; - assign _theResult___snd__h250440 = { _theResult____h242191[55:0], 1'd0 } ; - assign _theResult___snd__h250451 = - (!_theResult____h242191[56] && _theResult____h242191[55]) ? - _theResult___snd__h250453 : - _theResult___snd__h250463 ; - assign _theResult___snd__h250453 = { _theResult____h242191[54:0], 2'd0 } ; - assign _theResult___snd__h250463 = - (!_theResult____h242191[56] && !_theResult____h242191[55] && - !_theResult____h242191[54] && - !_theResult____h242191[53] && - !_theResult____h242191[52] && - !_theResult____h242191[51] && - !_theResult____h242191[50] && - !_theResult____h242191[49] && - !_theResult____h242191[48] && - !_theResult____h242191[47] && - !_theResult____h242191[46] && - !_theResult____h242191[45] && - !_theResult____h242191[44] && - !_theResult____h242191[43] && - !_theResult____h242191[42] && - !_theResult____h242191[41] && - !_theResult____h242191[40] && - !_theResult____h242191[39] && - !_theResult____h242191[38] && - !_theResult____h242191[37] && - !_theResult____h242191[36] && - !_theResult____h242191[35] && - !_theResult____h242191[34] && - !_theResult____h242191[33] && - !_theResult____h242191[32] && - !_theResult____h242191[31] && - !_theResult____h242191[30] && - !_theResult____h242191[29] && - !_theResult____h242191[28] && - !_theResult____h242191[27] && - !_theResult____h242191[26] && - !_theResult____h242191[25] && - !_theResult____h242191[24] && - !_theResult____h242191[23] && - !_theResult____h242191[22] && - !_theResult____h242191[21] && - !_theResult____h242191[20] && - !_theResult____h242191[19] && - !_theResult____h242191[18] && - !_theResult____h242191[17] && - !_theResult____h242191[16] && - !_theResult____h242191[15] && - !_theResult____h242191[14] && - !_theResult____h242191[13] && - !_theResult____h242191[12] && - !_theResult____h242191[11] && - !_theResult____h242191[10] && - !_theResult____h242191[9] && - !_theResult____h242191[8] && - !_theResult____h242191[7] && - !_theResult____h242191[6] && - !_theResult____h242191[5] && - !_theResult____h242191[4] && - !_theResult____h242191[3] && - !_theResult____h242191[2] && - !_theResult____h242191[1] && - !_theResult____h242191[0]) ? - _theResult____h242191 : - _theResult___snd__h250469 ; - assign _theResult___snd__h250469 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64[54:0], - 2'd0 } ; - assign _theResult___snd__h250492 = - _theResult____h242191 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 ; - assign _theResult___snd__h259176 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___snd__h259190 : - _theResult___snd__h240866 ; - assign _theResult___snd__h259190 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ? - sfd__h222115 : - _theResult___snd__h259196 ; - assign _theResult___snd__h259196 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67[54:0], - 2'd0 } ; - assign _theResult___snd__h259214 = - sfd__h222115 << - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ; - assign _theResult___snd__h277697 = { _theResult____h269577[55:0], 1'd0 } ; - assign _theResult___snd__h277708 = - (!_theResult____h269577[56] && _theResult____h269577[55]) ? - _theResult___snd__h277710 : - _theResult___snd__h277720 ; - assign _theResult___snd__h277710 = { _theResult____h269577[54:0], 2'd0 } ; - assign _theResult___snd__h277720 = - (!_theResult____h269577[56] && !_theResult____h269577[55] && - !_theResult____h269577[54] && - !_theResult____h269577[53] && - !_theResult____h269577[52] && - !_theResult____h269577[51] && - !_theResult____h269577[50] && - !_theResult____h269577[49] && - !_theResult____h269577[48] && - !_theResult____h269577[47] && - !_theResult____h269577[46] && - !_theResult____h269577[45] && - !_theResult____h269577[44] && - !_theResult____h269577[43] && - !_theResult____h269577[42] && - !_theResult____h269577[41] && - !_theResult____h269577[40] && - !_theResult____h269577[39] && - !_theResult____h269577[38] && - !_theResult____h269577[37] && - !_theResult____h269577[36] && - !_theResult____h269577[35] && - !_theResult____h269577[34] && - !_theResult____h269577[33] && - !_theResult____h269577[32] && - !_theResult____h269577[31] && - !_theResult____h269577[30] && - !_theResult____h269577[29] && - !_theResult____h269577[28] && - !_theResult____h269577[27] && - !_theResult____h269577[26] && - !_theResult____h269577[25] && - !_theResult____h269577[24] && - !_theResult____h269577[23] && - !_theResult____h269577[22] && - !_theResult____h269577[21] && - !_theResult____h269577[20] && - !_theResult____h269577[19] && - !_theResult____h269577[18] && - !_theResult____h269577[17] && - !_theResult____h269577[16] && - !_theResult____h269577[15] && - !_theResult____h269577[14] && - !_theResult____h269577[13] && - !_theResult____h269577[12] && - !_theResult____h269577[11] && - !_theResult____h269577[10] && - !_theResult____h269577[9] && - !_theResult____h269577[8] && - !_theResult____h269577[7] && - !_theResult____h269577[6] && - !_theResult____h269577[5] && - !_theResult____h269577[4] && - !_theResult____h269577[3] && - !_theResult____h269577[2] && - !_theResult____h269577[1] && - !_theResult____h269577[0]) ? - _theResult____h269577 : - _theResult___snd__h277726 ; - assign _theResult___snd__h277726 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133[54:0], - 2'd0 } ; - assign _theResult___snd__h277749 = - _theResult____h269577 << - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 ; - assign _theResult___snd__h286293 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___snd__h286302 : - _theResult___snd__h286295 ; - assign _theResult___snd__h286295 = { resWire$wget[56:5], 5'd0 } ; - assign _theResult___snd__h286302 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ? - sfd__h261975 : - _theResult___snd__h286308 ; - assign _theResult___snd__h286308 = - { IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135[54:0], - 2'd0 } ; - assign _theResult___snd__h286331 = - sfd__h261975 << - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 ; - assign _theResult___snd__h295463 = { _theResult____h287214[55:0], 1'd0 } ; - assign _theResult___snd__h295474 = - (!_theResult____h287214[56] && _theResult____h287214[55]) ? - _theResult___snd__h295476 : - _theResult___snd__h295486 ; - assign _theResult___snd__h295476 = { _theResult____h287214[54:0], 2'd0 } ; - assign _theResult___snd__h295486 = - (!_theResult____h287214[56] && !_theResult____h287214[55] && - !_theResult____h287214[54] && - !_theResult____h287214[53] && - !_theResult____h287214[52] && - !_theResult____h287214[51] && - !_theResult____h287214[50] && - !_theResult____h287214[49] && - !_theResult____h287214[48] && - !_theResult____h287214[47] && - !_theResult____h287214[46] && - !_theResult____h287214[45] && - !_theResult____h287214[44] && - !_theResult____h287214[43] && - !_theResult____h287214[42] && - !_theResult____h287214[41] && - !_theResult____h287214[40] && - !_theResult____h287214[39] && - !_theResult____h287214[38] && - !_theResult____h287214[37] && - !_theResult____h287214[36] && - !_theResult____h287214[35] && - !_theResult____h287214[34] && - !_theResult____h287214[33] && - !_theResult____h287214[32] && - !_theResult____h287214[31] && - !_theResult____h287214[30] && - !_theResult____h287214[29] && - !_theResult____h287214[28] && - !_theResult____h287214[27] && - !_theResult____h287214[26] && - !_theResult____h287214[25] && - !_theResult____h287214[24] && - !_theResult____h287214[23] && - !_theResult____h287214[22] && - !_theResult____h287214[21] && - !_theResult____h287214[20] && - !_theResult____h287214[19] && - !_theResult____h287214[18] && - !_theResult____h287214[17] && - !_theResult____h287214[16] && - !_theResult____h287214[15] && - !_theResult____h287214[14] && - !_theResult____h287214[13] && - !_theResult____h287214[12] && - !_theResult____h287214[11] && - !_theResult____h287214[10] && - !_theResult____h287214[9] && - !_theResult____h287214[8] && - !_theResult____h287214[7] && - !_theResult____h287214[6] && - !_theResult____h287214[5] && - !_theResult____h287214[4] && - !_theResult____h287214[3] && - !_theResult____h287214[2] && - !_theResult____h287214[1] && - !_theResult____h287214[0]) ? - _theResult____h287214 : - _theResult___snd__h295492 ; - assign _theResult___snd__h295492 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139[54:0], - 2'd0 } ; - assign _theResult___snd__h295515 = - _theResult____h287214 << - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 ; - assign _theResult___snd__h304083 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___snd__h304097 : - _theResult___snd__h286295 ; - assign _theResult___snd__h304097 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ? - sfd__h261975 : - _theResult___snd__h304103 ; - assign _theResult___snd__h304103 = - { IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142[54:0], - 2'd0 } ; - assign _theResult___snd__h304121 = - sfd__h261975 << - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ; - assign _theResult___snd__h34715 = - { fpu_div64_fState_S3$D_OUT[56:0], 1'd0 } ; - assign _theResult___snd__h42350 = { sfdin__h34118[56:0], 1'd0 } ; - assign _theResult___snd__h42365 = - (!sfdin__h34118[57] && sfdin__h34118[56]) ? - _theResult___snd__h42367 : - _theResult___snd__h42380 ; - assign _theResult___snd__h42367 = { sfdin__h34118[55:0], 2'd0 } ; - assign _theResult___snd__h42380 = - (!sfdin__h34118[57] && !sfdin__h34118[56] && - !sfdin__h34118[55] && - !sfdin__h34118[54] && - !sfdin__h34118[53] && - !sfdin__h34118[52] && - !sfdin__h34118[51] && - !sfdin__h34118[50] && - !sfdin__h34118[49] && - !sfdin__h34118[48] && - !sfdin__h34118[47] && - !sfdin__h34118[46] && - !sfdin__h34118[45] && - !sfdin__h34118[44] && - !sfdin__h34118[43] && - !sfdin__h34118[42] && - !sfdin__h34118[41] && - !sfdin__h34118[40] && - !sfdin__h34118[39] && - !sfdin__h34118[38] && - !sfdin__h34118[37] && - !sfdin__h34118[36] && - !sfdin__h34118[35] && - !sfdin__h34118[34] && - !sfdin__h34118[33] && - !sfdin__h34118[32] && - !sfdin__h34118[31] && - !sfdin__h34118[30] && - !sfdin__h34118[29] && - !sfdin__h34118[28] && - !sfdin__h34118[27] && - !sfdin__h34118[26] && - !sfdin__h34118[25] && - !sfdin__h34118[24] && - !sfdin__h34118[23] && - !sfdin__h34118[22] && - !sfdin__h34118[21] && - !sfdin__h34118[20] && - !sfdin__h34118[19] && - !sfdin__h34118[18] && - !sfdin__h34118[17] && - !sfdin__h34118[16] && - !sfdin__h34118[15] && - !sfdin__h34118[14] && - !sfdin__h34118[13] && - !sfdin__h34118[12] && - !sfdin__h34118[11] && - !sfdin__h34118[10] && - !sfdin__h34118[9] && - !sfdin__h34118[8] && - !sfdin__h34118[7] && - !sfdin__h34118[6] && - !sfdin__h34118[5] && - !sfdin__h34118[4] && - !sfdin__h34118[3] && - !sfdin__h34118[2] && - !sfdin__h34118[1] && - !sfdin__h34118[0]) ? - sfdin__h34118 : - _theResult___snd__h42386 ; - assign _theResult___snd__h42386 = - { IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12[55:0], - 2'd0 } ; - assign _theResult___snd__h42404 = - sfdin__h34118 << - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 ; - assign _theResult___snd__h42409 = - sfdin__h34118 << - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 ; - assign _theResult___snd__h94767 = - { fpu_sqr64_fState_S3$D_OUT[57:0], 1'd0 } ; - assign _theResult___snd__h94782 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - fpu_sqr64_fState_S3$D_OUT[57]) ? - _theResult___snd__h94784 : - _theResult___snd__h94797 ; - assign _theResult___snd__h94784 = - { fpu_sqr64_fState_S3$D_OUT[56:0], 2'd0 } ; - assign _theResult___snd__h94797 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - !fpu_sqr64_fState_S3$D_OUT[57] && - !fpu_sqr64_fState_S3$D_OUT[56] && - !fpu_sqr64_fState_S3$D_OUT[55] && - !fpu_sqr64_fState_S3$D_OUT[54] && - !fpu_sqr64_fState_S3$D_OUT[53] && - !fpu_sqr64_fState_S3$D_OUT[52] && - !fpu_sqr64_fState_S3$D_OUT[51] && - !fpu_sqr64_fState_S3$D_OUT[50] && - !fpu_sqr64_fState_S3$D_OUT[49] && - !fpu_sqr64_fState_S3$D_OUT[48] && - !fpu_sqr64_fState_S3$D_OUT[47] && - !fpu_sqr64_fState_S3$D_OUT[46] && - !fpu_sqr64_fState_S3$D_OUT[45] && - !fpu_sqr64_fState_S3$D_OUT[44] && - !fpu_sqr64_fState_S3$D_OUT[43] && - !fpu_sqr64_fState_S3$D_OUT[42] && - !fpu_sqr64_fState_S3$D_OUT[41] && - !fpu_sqr64_fState_S3$D_OUT[40] && - !fpu_sqr64_fState_S3$D_OUT[39] && - !fpu_sqr64_fState_S3$D_OUT[38] && - !fpu_sqr64_fState_S3$D_OUT[37] && - !fpu_sqr64_fState_S3$D_OUT[36] && - !fpu_sqr64_fState_S3$D_OUT[35] && - !fpu_sqr64_fState_S3$D_OUT[34] && - !fpu_sqr64_fState_S3$D_OUT[33] && - !fpu_sqr64_fState_S3$D_OUT[32] && - !fpu_sqr64_fState_S3$D_OUT[31] && - !fpu_sqr64_fState_S3$D_OUT[30] && - !fpu_sqr64_fState_S3$D_OUT[29] && - !fpu_sqr64_fState_S3$D_OUT[28] && - !fpu_sqr64_fState_S3$D_OUT[27] && - !fpu_sqr64_fState_S3$D_OUT[26] && - !fpu_sqr64_fState_S3$D_OUT[25] && - !fpu_sqr64_fState_S3$D_OUT[24] && - !fpu_sqr64_fState_S3$D_OUT[23] && - !fpu_sqr64_fState_S3$D_OUT[22] && - !fpu_sqr64_fState_S3$D_OUT[21] && - !fpu_sqr64_fState_S3$D_OUT[20] && - !fpu_sqr64_fState_S3$D_OUT[19] && - !fpu_sqr64_fState_S3$D_OUT[18] && - !fpu_sqr64_fState_S3$D_OUT[17] && - !fpu_sqr64_fState_S3$D_OUT[16] && - !fpu_sqr64_fState_S3$D_OUT[15] && - !fpu_sqr64_fState_S3$D_OUT[14] && - !fpu_sqr64_fState_S3$D_OUT[13] && - !fpu_sqr64_fState_S3$D_OUT[12] && - !fpu_sqr64_fState_S3$D_OUT[11] && - !fpu_sqr64_fState_S3$D_OUT[10] && - !fpu_sqr64_fState_S3$D_OUT[9] && - !fpu_sqr64_fState_S3$D_OUT[8] && - !fpu_sqr64_fState_S3$D_OUT[7] && - !fpu_sqr64_fState_S3$D_OUT[6] && - !fpu_sqr64_fState_S3$D_OUT[5] && - !fpu_sqr64_fState_S3$D_OUT[4] && - !fpu_sqr64_fState_S3$D_OUT[3] && - !fpu_sqr64_fState_S3$D_OUT[2] && - !fpu_sqr64_fState_S3$D_OUT[1] && - !fpu_sqr64_fState_S3$D_OUT[0]) ? - fpu_sqr64_fState_S3$D_OUT[58:0] : - _theResult___snd__h94803 ; - assign _theResult___snd__h94803 = - { IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19[56:0], - 2'd0 } ; - assign _theResult___snd__h94821 = - fpu_sqr64_fState_S3$D_OUT[58:0] << - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 ; - assign _theResult___snd__h94826 = - fpu_sqr64_fState_S3$D_OUT[58:0] << - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 ; - assign _theResult___snd_fst__h131051 = - { IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25[1], - { sfdin__h130943[52:0], 52'd0 } != 105'd0 } ; - assign _theResult___snd_fst__h141477 = - { IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30[1], - { sfdin__h141369[3:0], 52'd0 } != 56'd0 } ; - assign _theResult___snd_fst__h1478 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___snd_fst__h1602 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 ; - assign _theResult___snd_fst__h1517 = - (rg_res[116] || rg_b == 116'd0 || - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63) ? - rg_s : - s__h1658 ; - assign _theResult___snd_fst__h1602 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0 || - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 : - s__h1723 ; - assign _theResult___snd_fst__h42439 = - { IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13[1], - { sfdin__h42327[4:0], 52'd0 } != 57'd0 } ; - assign _theResult___snd_fst__h94856 = - { IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20[1], - { sfdin__h94744[5:0], 52'd0 } != 58'd0 } ; - assign _theResult___snd_fst_exp__h164065 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - 11'd0 : - _theResult___fst_exp__h164062 ; - assign _theResult___snd_fst_exp__h182407 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - _theResult___fst_exp__h173652 : - _theResult___fst_exp__h182404 ; - assign _theResult___snd_fst_exp__h202703 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - 11'd0 : - _theResult___fst_exp__h202700 ; - assign _theResult___snd_fst_exp__h221045 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - _theResult___fst_exp__h212290 : - _theResult___fst_exp__h221042 ; - assign _theResult___snd_fst_exp__h241642 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - 11'd0 : - _theResult___fst_exp__h241639 ; - assign _theResult___snd_fst_exp__h259984 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - _theResult___fst_exp__h251229 : - _theResult___fst_exp__h259981 ; - assign _theResult___snd_fst_exp__h286868 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _theResult___fst_exp__h278283 : - _theResult___fst_exp__h286865 ; - assign _theResult___snd_fst_exp__h304688 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _theResult___fst_exp__h296049 : - _theResult___fst_exp__h304685 ; - assign _theResult___snd_fst_exp__h31334 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499) ? - 11'd0 : - value__h31374[10:0] ; - assign _theResult___snd_fst_exp__h31337 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ? - _theResult___snd_fst_exp__h31334 : - 11'd2046 ; - assign _theResult___snd_fst_exp__h31361 = - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 ? - 11'd0 : - _theResult___snd_fst_exp__h31337 ; - assign _theResult___snd_fst_sfd__h144486 = - (iFifo$D_OUT[159:137] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h144235 ; - assign _theResult___snd_fst_sfd__h164066 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - 52'd0 : - _theResult___fst_sfd__h164063 ; - assign _theResult___snd_fst_sfd__h182408 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - _theResult___fst_sfd__h173653 : - _theResult___fst_sfd__h182405 ; - assign _theResult___snd_fst_sfd__h183126 = - (iFifo$D_OUT[94:72] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h182875 ; - assign _theResult___snd_fst_sfd__h202704 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - 52'd0 : - _theResult___fst_sfd__h202701 ; - assign _theResult___snd_fst_sfd__h221046 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - _theResult___fst_sfd__h212291 : - _theResult___fst_sfd__h221043 ; - assign _theResult___snd_fst_sfd__h222065 = - (iFifo$D_OUT[29:7] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h221814 ; - assign _theResult___snd_fst_sfd__h241643 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - 52'd0 : - _theResult___fst_sfd__h241640 ; - assign _theResult___snd_fst_sfd__h259985 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - _theResult___fst_sfd__h251230 : - _theResult___fst_sfd__h259982 ; - assign _theResult___snd_fst_sfd__h261925 = - (resWire$wget[56:34] == 23'd0) ? - 23'd2097152 : - resWire$wget[56:34] ; - assign _theResult___snd_fst_sfd__h286869 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _theResult___fst_sfd__h278284 : - _theResult___fst_sfd__h286866 ; - assign _theResult___snd_fst_sfd__h304689 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _theResult___fst_sfd__h296050 : - _theResult___fst_sfd__h304686 ; - assign _theResult___snd_fst_sfd__h31362 = - (fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353) ? - 52'd0 : - 52'hFFFFFFFFFFFFF ; - assign _theResult___snd_snd__h131371 = - (fpu_madd_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ; - assign _theResult___snd_snd__h1649 = - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63 ? r__h1663 : r__h1659 ; - assign _theResult___snd_snd__h1715 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85 ? - r__h1753 : - r__h1724 ; - assign _theResult___snd_snd_snd__h131369 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - _theResult___snd_snd__h131371 : - guardBC__h115666 ; - assign _theResult___snd_snd_snd__h1481 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___snd_snd_snd__h1605 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 ; - assign _theResult___snd_snd_snd__h1520 = - (rg_res[116] || rg_b == 116'd0) ? - rg_r_1 : - _theResult___snd_snd__h1649 ; - assign _theResult___snd_snd_snd__h1605 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 : - _theResult___snd_snd__h1715 ; - assign _theResult___snd_snd_snd__h33963 = - (fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___snd__h34715 : - fpu_div64_fState_S3$D_OUT[57:0] ; - assign b___1__h77160 = 116'h40000000000000000000000000000 >> x__h85465 ; - assign b__h11457 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0) ? - (fpu_div64_fOperands_S0$D_OUT[54] ? - 6'd1 : - (fpu_div64_fOperands_S0$D_OUT[53] ? - 6'd2 : - (fpu_div64_fOperands_S0$D_OUT[52] ? - 6'd3 : - (fpu_div64_fOperands_S0$D_OUT[51] ? - 6'd4 : - (fpu_div64_fOperands_S0$D_OUT[50] ? - 6'd5 : - (fpu_div64_fOperands_S0$D_OUT[49] ? - 6'd6 : - (fpu_div64_fOperands_S0$D_OUT[48] ? - 6'd7 : - (fpu_div64_fOperands_S0$D_OUT[47] ? - 6'd8 : - (fpu_div64_fOperands_S0$D_OUT[46] ? - 6'd9 : - (fpu_div64_fOperands_S0$D_OUT[45] ? - 6'd10 : - (fpu_div64_fOperands_S0$D_OUT[44] ? - 6'd11 : - (fpu_div64_fOperands_S0$D_OUT[43] ? - 6'd12 : - (fpu_div64_fOperands_S0$D_OUT[42] ? - 6'd13 : - (fpu_div64_fOperands_S0$D_OUT[41] ? - 6'd14 : - (fpu_div64_fOperands_S0$D_OUT[40] ? - 6'd15 : - (fpu_div64_fOperands_S0$D_OUT[39] ? - 6'd16 : - (fpu_div64_fOperands_S0$D_OUT[38] ? - 6'd17 : - (fpu_div64_fOperands_S0$D_OUT[37] ? - 6'd18 : - (fpu_div64_fOperands_S0$D_OUT[36] ? - 6'd19 : - (fpu_div64_fOperands_S0$D_OUT[35] ? - 6'd20 : - (fpu_div64_fOperands_S0$D_OUT[34] ? - 6'd21 : - (fpu_div64_fOperands_S0$D_OUT[33] ? - 6'd22 : - (fpu_div64_fOperands_S0$D_OUT[32] ? - 6'd23 : - (fpu_div64_fOperands_S0$D_OUT[31] ? - 6'd24 : - (fpu_div64_fOperands_S0$D_OUT[30] ? - 6'd25 : - (fpu_div64_fOperands_S0$D_OUT[29] ? - 6'd26 : - (fpu_div64_fOperands_S0$D_OUT[28] ? - 6'd27 : - (fpu_div64_fOperands_S0$D_OUT[27] ? - 6'd28 : - (fpu_div64_fOperands_S0$D_OUT[26] ? - 6'd29 : - (fpu_div64_fOperands_S0$D_OUT[25] ? - 6'd30 : - (fpu_div64_fOperands_S0$D_OUT[24] ? - 6'd31 : - (fpu_div64_fOperands_S0$D_OUT[23] ? - 6'd32 : - (fpu_div64_fOperands_S0$D_OUT[22] ? - 6'd33 : - (fpu_div64_fOperands_S0$D_OUT[21] ? - 6'd34 : - (fpu_div64_fOperands_S0$D_OUT[20] ? - 6'd35 : - (fpu_div64_fOperands_S0$D_OUT[19] ? - 6'd36 : - (fpu_div64_fOperands_S0$D_OUT[18] ? - 6'd37 : - (fpu_div64_fOperands_S0$D_OUT[17] ? - 6'd38 : - (fpu_div64_fOperands_S0$D_OUT[16] ? - 6'd39 : - (fpu_div64_fOperands_S0$D_OUT[15] ? - 6'd40 : - (fpu_div64_fOperands_S0$D_OUT[14] ? - 6'd41 : - (fpu_div64_fOperands_S0$D_OUT[13] ? - 6'd42 : - (fpu_div64_fOperands_S0$D_OUT[12] ? - 6'd43 : - (fpu_div64_fOperands_S0$D_OUT[11] ? - 6'd44 : - (fpu_div64_fOperands_S0$D_OUT[10] ? - 6'd45 : - (fpu_div64_fOperands_S0$D_OUT[9] ? - 6'd46 : - (fpu_div64_fOperands_S0$D_OUT[8] ? - 6'd47 : - (fpu_div64_fOperands_S0$D_OUT[7] ? - 6'd48 : - (fpu_div64_fOperands_S0$D_OUT[6] ? - 6'd49 : - (fpu_div64_fOperands_S0$D_OUT[5] ? - 6'd50 : - (fpu_div64_fOperands_S0$D_OUT[4] ? - 6'd51 : - (fpu_div64_fOperands_S0$D_OUT[3] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign b__h1608 = { 2'd0, rg_b[115:2] } ; - assign b__h1712 = - { 2'd0, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49[115:2] } ; - assign b__h32583 = { rg_d, 58'd0 } ; - assign b__h4039 = - (fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0) ? - (fpu_div64_fOperands_S0$D_OUT[118] ? - 6'd1 : - (fpu_div64_fOperands_S0$D_OUT[117] ? - 6'd2 : - (fpu_div64_fOperands_S0$D_OUT[116] ? - 6'd3 : - (fpu_div64_fOperands_S0$D_OUT[115] ? - 6'd4 : - (fpu_div64_fOperands_S0$D_OUT[114] ? - 6'd5 : - (fpu_div64_fOperands_S0$D_OUT[113] ? - 6'd6 : - (fpu_div64_fOperands_S0$D_OUT[112] ? - 6'd7 : - (fpu_div64_fOperands_S0$D_OUT[111] ? - 6'd8 : - (fpu_div64_fOperands_S0$D_OUT[110] ? - 6'd9 : - (fpu_div64_fOperands_S0$D_OUT[109] ? - 6'd10 : - (fpu_div64_fOperands_S0$D_OUT[108] ? - 6'd11 : - (fpu_div64_fOperands_S0$D_OUT[107] ? - 6'd12 : - (fpu_div64_fOperands_S0$D_OUT[106] ? - 6'd13 : - (fpu_div64_fOperands_S0$D_OUT[105] ? - 6'd14 : - (fpu_div64_fOperands_S0$D_OUT[104] ? - 6'd15 : - (fpu_div64_fOperands_S0$D_OUT[103] ? - 6'd16 : - (fpu_div64_fOperands_S0$D_OUT[102] ? - 6'd17 : - (fpu_div64_fOperands_S0$D_OUT[101] ? - 6'd18 : - (fpu_div64_fOperands_S0$D_OUT[100] ? - 6'd19 : - (fpu_div64_fOperands_S0$D_OUT[99] ? - 6'd20 : - (fpu_div64_fOperands_S0$D_OUT[98] ? - 6'd21 : - (fpu_div64_fOperands_S0$D_OUT[97] ? - 6'd22 : - (fpu_div64_fOperands_S0$D_OUT[96] ? - 6'd23 : - (fpu_div64_fOperands_S0$D_OUT[95] ? - 6'd24 : - (fpu_div64_fOperands_S0$D_OUT[94] ? - 6'd25 : - (fpu_div64_fOperands_S0$D_OUT[93] ? - 6'd26 : - (fpu_div64_fOperands_S0$D_OUT[92] ? - 6'd27 : - (fpu_div64_fOperands_S0$D_OUT[91] ? - 6'd28 : - (fpu_div64_fOperands_S0$D_OUT[90] ? - 6'd29 : - (fpu_div64_fOperands_S0$D_OUT[89] ? - 6'd30 : - (fpu_div64_fOperands_S0$D_OUT[88] ? - 6'd31 : - (fpu_div64_fOperands_S0$D_OUT[87] ? - 6'd32 : - (fpu_div64_fOperands_S0$D_OUT[86] ? - 6'd33 : - (fpu_div64_fOperands_S0$D_OUT[85] ? - 6'd34 : - (fpu_div64_fOperands_S0$D_OUT[84] ? - 6'd35 : - (fpu_div64_fOperands_S0$D_OUT[83] ? - 6'd36 : - (fpu_div64_fOperands_S0$D_OUT[82] ? - 6'd37 : - (fpu_div64_fOperands_S0$D_OUT[81] ? - 6'd38 : - (fpu_div64_fOperands_S0$D_OUT[80] ? - 6'd39 : - (fpu_div64_fOperands_S0$D_OUT[79] ? - 6'd40 : - (fpu_div64_fOperands_S0$D_OUT[78] ? - 6'd41 : - (fpu_div64_fOperands_S0$D_OUT[77] ? - 6'd42 : - (fpu_div64_fOperands_S0$D_OUT[76] ? - 6'd43 : - (fpu_div64_fOperands_S0$D_OUT[75] ? - 6'd44 : - (fpu_div64_fOperands_S0$D_OUT[74] ? - 6'd45 : - (fpu_div64_fOperands_S0$D_OUT[73] ? - 6'd46 : - (fpu_div64_fOperands_S0$D_OUT[72] ? - 6'd47 : - (fpu_div64_fOperands_S0$D_OUT[71] ? - 6'd48 : - (fpu_div64_fOperands_S0$D_OUT[70] ? - 6'd49 : - (fpu_div64_fOperands_S0$D_OUT[69] ? - 6'd50 : - (fpu_div64_fOperands_S0$D_OUT[68] ? - 6'd51 : - (fpu_div64_fOperands_S0$D_OUT[67] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign din_exp30866_MINUS_1023__q23 = din_exp__h130866 - 11'd1023 ; - assign din_exp__h130866 = - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ? - value__h130883[10:0] : - 11'd0 ; - assign din_inc___2_exp__h142626 = fpu_madd_fState_S8$D_OUT[65:55] + 11'd1 ; - assign din_inc___2_exp__h182469 = _theResult___fst_exp__h163336 + 11'd1 ; - assign din_inc___2_exp__h182504 = _theResult___fst_exp__h172852 + 11'd1 ; - assign din_inc___2_exp__h182530 = _theResult___fst_exp__h181653 + 11'd1 ; - assign din_inc___2_exp__h221107 = _theResult___fst_exp__h201974 + 11'd1 ; - assign din_inc___2_exp__h221142 = _theResult___fst_exp__h211490 + 11'd1 ; - assign din_inc___2_exp__h221168 = _theResult___fst_exp__h220291 + 11'd1 ; - assign din_inc___2_exp__h260046 = _theResult___fst_exp__h240913 + 11'd1 ; - assign din_inc___2_exp__h260081 = _theResult___fst_exp__h250429 + 11'd1 ; - assign din_inc___2_exp__h260107 = _theResult___fst_exp__h259230 + 11'd1 ; - assign din_inc___2_exp__h304723 = _theResult___fst_exp__h277686 + 8'd1 ; - assign din_inc___2_exp__h304749 = _theResult___fst_exp__h286342 + 8'd1 ; - assign din_inc___2_exp__h304784 = _theResult___fst_exp__h295452 + 8'd1 ; - assign din_inc___2_exp__h304810 = _theResult___fst_exp__h304137 + 8'd1 ; - assign din_inc___2_exp__h43566 = fpu_div64_fState_S4$D_OUT[64:54] + 11'd1 ; - assign din_inc___2_exp__h96000 = fpu_sqr64_fState_S4$D_OUT[64:54] + 11'd1 ; - assign exp__h304706 = - (resWire$wget[67:57] == 11'd2047) ? - 8'd255 : - _theResult___fst_exp__h304697 ; - assign fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7 = - fpu_div64_fOperands_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8 = - fpu_div64_fOperands_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401 ; - assign fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359 = - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - !IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ; - assign fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 = - fpu_div64_fOperands_S0$D_OUT[130] == - fpu_div64_fOperands_S0$D_OUT[66] ; - assign fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936 = - { fpu_div64_fState_S3$D_OUT[121], - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 ? - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929 : - ((fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - { _theResult___fst_exp__h42284, - fpu_div64_fState_S3$D_OUT[109:58] } : - 63'h7FEFFFFFFFFFFFFF) : - fpu_div64_fState_S3$D_OUT[120:58]) } ; - assign fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 = - fpu_madd_fOperand_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 = - fpu_madd_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 = - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 || - x__h96539 == 11'd0 && _theResult___fst_sfd__h96608 == 52'd0 && - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) && - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 ; - assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 = - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 = - (fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194]) == - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 ; - assign fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012 = - fpu_madd_fProd_S3$D_OUT >> - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ; - assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 = - (fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ; - assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 = - (fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ; - assign fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501 = - fpu_madd_fState_S3$D_OUT[86:82] | - { 2'd0, - sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023, - _theResult___fst_exp__h130952 == 11'd0 && - guardBC__h115666 != 2'd0, - sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023 } ; - assign fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27 = - fpu_madd_fState_S4$D_OUT[128:118] - 11'd1023 ; - assign fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26 = - fpu_madd_fState_S4$D_OUT[64:54] - 11'd1023 ; - assign fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615 = - fpu_madd_fState_S5$D_OUT[56:0] >> - fpu_madd_fState_S5$D_OUT[126:114] ; - assign fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942 = - fpu_madd_fState_S7$D_OUT[137:133] | - { 2'd0, - sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023, - _theResult___fst_exp__h141378 == 11'd0 && - guard__h133123 != 2'd0, - sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023 } ; - assign fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 = - fpu_madd_fState_S8$D_OUT[75:71] | - { 2'd0, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 == - 11'd2047 && - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h142620) == - 52'd0, - 1'd0, - fpu_madd_fState_S8$D_OUT[65:55] != 11'd2047 && - fpu_madd_fState_S8$D_OUT[2:1] != 2'b0 } ; - assign fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16 = - fpu_sqr64_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18 = - fpu_sqr64_fState_S3$D_OUT[121:111] - 11'd1023 ; - assign guardBC__h115666 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h131051 ; - assign guard__h132367 = fpu_madd_fState_S5$D_OUT[56:0] << x__h132471 ; - assign guard__h133123 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h141477 ; - assign guard__h155375 = - { IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34[1], - { _theResult___snd__h163287[3:0], 52'd0 } != 56'd0 } ; - assign guard__h164624 = - { IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38[1], - { sfdin__h172846[3:0], 52'd0 } != 56'd0 } ; - assign guard__h165222 = x__h165324 != 57'd0 ; - assign guard__h173663 = - { IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41[1], - { _theResult___snd__h181599[3:0], 52'd0 } != 56'd0 } ; - assign guard__h194013 = - { IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94[1], - { _theResult___snd__h201925[3:0], 52'd0 } != 56'd0 } ; - assign guard__h203262 = - { IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98[1], - { sfdin__h211484[3:0], 52'd0 } != 56'd0 } ; - assign guard__h203860 = x__h203962 != 57'd0 ; - assign guard__h212301 = - { IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h220237[3:0], 52'd0 } != 56'd0 } ; - assign guard__h232952 = - { IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61[1], - { _theResult___snd__h240864[3:0], 52'd0 } != 56'd0 } ; - assign guard__h242201 = - { IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65[1], - { sfdin__h250423[3:0], 52'd0 } != 56'd0 } ; - assign guard__h242799 = x__h242901 != 57'd0 ; - assign guard__h251240 = - { IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68[1], - { _theResult___snd__h259176[3:0], 52'd0 } != 56'd0 } ; - assign guard__h269587 = - { IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134[1], - { sfdin__h277680[32:0], 23'd0 } != 56'd0 } ; - assign guard__h278294 = - { IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136[1], - { _theResult___snd__h286293[32:0], 23'd0 } != 56'd0 } ; - assign guard__h287224 = - { IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140[1], - { sfdin__h295446[32:0], 23'd0 } != 56'd0 } ; - assign guard__h287822 = x__h287924 != 57'd0 ; - assign guard__h296060 = - { IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143[1], - { _theResult___snd__h304083[32:0], 23'd0 } != 56'd0 } ; - assign guard__h33946 = x__h42705 ; - assign guard__h86435 = x__h95138 ; - assign iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 = - iFifo$D_OUT[102:95] - 8'd127 ; - assign iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 = - iFifo$D_OUT[167:160] - 8'd127 ; - assign iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 = - iFifo$D_OUT[37:30] - 8'd127 ; - assign out___1_sfd__h144235 = { iFifo$D_OUT[159:137], 29'd0 } ; - assign out___1_sfd__h182875 = { iFifo$D_OUT[94:72], 29'd0 } ; - assign out___1_sfd__h221814 = { iFifo$D_OUT[29:7], 29'd0 } ; - assign out_exp__h142544 = - fpu_madd_fState_S8$D_OUT[3] ? - _theResult___exp__h142541 : - fpu_madd_fState_S8$D_OUT[65:55] ; - assign out_exp__h163984 = - _theResult___snd__h163287[5] ? - _theResult___exp__h163981 : - _theResult___fst_exp__h163336 ; - assign out_exp__h173574 = - sfdin__h172846[5] ? - _theResult___exp__h173571 : - _theResult___fst_exp__h172852 ; - assign out_exp__h182326 = - _theResult___snd__h181599[5] ? - _theResult___exp__h182323 : - _theResult___fst_exp__h181653 ; - assign out_exp__h202622 = - _theResult___snd__h201925[5] ? - _theResult___exp__h202619 : - _theResult___fst_exp__h201974 ; - assign out_exp__h212212 = - sfdin__h211484[5] ? - _theResult___exp__h212209 : - _theResult___fst_exp__h211490 ; - assign out_exp__h220964 = - _theResult___snd__h220237[5] ? - _theResult___exp__h220961 : - _theResult___fst_exp__h220291 ; - assign out_exp__h241561 = - _theResult___snd__h240864[5] ? - _theResult___exp__h241558 : - _theResult___fst_exp__h240913 ; - assign out_exp__h251151 = - sfdin__h250423[5] ? - _theResult___exp__h251148 : - _theResult___fst_exp__h250429 ; - assign out_exp__h259903 = - _theResult___snd__h259176[5] ? - _theResult___exp__h259900 : - _theResult___fst_exp__h259230 ; - assign out_exp__h278205 = - sfdin__h277680[34] ? - _theResult___exp__h278202 : - _theResult___fst_exp__h277686 ; - assign out_exp__h286787 = - _theResult___snd__h286293[34] ? - _theResult___exp__h286784 : - _theResult___fst_exp__h286342 ; - assign out_exp__h295971 = - sfdin__h295446[34] ? - _theResult___exp__h295968 : - _theResult___fst_exp__h295452 ; - assign out_exp__h304607 = - _theResult___snd__h304083[34] ? - _theResult___exp__h304604 : - _theResult___fst_exp__h304137 ; - assign out_exp__h43478 = - fpu_div64_fState_S4$D_OUT[2] ? - _theResult___exp__h43475 : - fpu_div64_fState_S4$D_OUT[64:54] ; - assign out_exp__h95912 = - fpu_sqr64_fState_S4$D_OUT[2] ? - _theResult___exp__h95909 : - fpu_sqr64_fState_S4$D_OUT[64:54] ; - assign out_sfd__h142545 = - fpu_madd_fState_S8$D_OUT[3] ? - _theResult___sfd__h142542 : - fpu_madd_fState_S8$D_OUT[54:3] ; - assign out_sfd__h163985 = - _theResult___snd__h163287[5] ? - _theResult___sfd__h163982 : - _theResult___snd__h163287[56:5] ; - assign out_sfd__h173575 = - sfdin__h172846[5] ? - _theResult___sfd__h173572 : - sfdin__h172846[56:5] ; - assign out_sfd__h182327 = - _theResult___snd__h181599[5] ? - _theResult___sfd__h182324 : - _theResult___snd__h181599[56:5] ; - assign out_sfd__h202623 = - _theResult___snd__h201925[5] ? - _theResult___sfd__h202620 : - _theResult___snd__h201925[56:5] ; - assign out_sfd__h212213 = - sfdin__h211484[5] ? - _theResult___sfd__h212210 : - sfdin__h211484[56:5] ; - assign out_sfd__h220965 = - _theResult___snd__h220237[5] ? - _theResult___sfd__h220962 : - _theResult___snd__h220237[56:5] ; - assign out_sfd__h241562 = - _theResult___snd__h240864[5] ? - _theResult___sfd__h241559 : - _theResult___snd__h240864[56:5] ; - assign out_sfd__h251152 = - sfdin__h250423[5] ? - _theResult___sfd__h251149 : - sfdin__h250423[56:5] ; - assign out_sfd__h259904 = - _theResult___snd__h259176[5] ? - _theResult___sfd__h259901 : - _theResult___snd__h259176[56:5] ; - assign out_sfd__h278206 = - sfdin__h277680[34] ? - _theResult___sfd__h278203 : - sfdin__h277680[56:34] ; - assign out_sfd__h286788 = - _theResult___snd__h286293[34] ? - _theResult___sfd__h286785 : - _theResult___snd__h286293[56:34] ; - assign out_sfd__h295972 = - sfdin__h295446[34] ? - _theResult___sfd__h295969 : - sfdin__h295446[56:34] ; - assign out_sfd__h304608 = - _theResult___snd__h304083[34] ? - _theResult___sfd__h304605 : - _theResult___snd__h304083[56:34] ; - assign out_sfd__h43479 = - fpu_div64_fState_S4$D_OUT[2] ? - _theResult___sfd__h43476 : - fpu_div64_fState_S4$D_OUT[53:2] ; - assign out_sfd__h95913 = - fpu_sqr64_fState_S4$D_OUT[2] ? - _theResult___sfd__h95910 : - fpu_sqr64_fState_S4$D_OUT[53:2] ; - assign r__h1659 = r__h1663 + rg_b ; - assign r__h1663 = { 1'd0, rg_r_1[115:1] } ; - assign r__h1724 = - r__h1753 + - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign r__h1753 = - { 1'd0, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69[115:1] } ; - assign resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 = - resWire$wget[4:0] | - { (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 } ; - assign resWirewget_BITS_67_TO_57_MINUS_1023__q137 = - resWire$wget[67:57] - 11'd1023 ; - assign result__h132372 = - { fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[56:1], - fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[0] | - guard__h132367 != 57'd0 } ; - assign result__h165227 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[0] | - guard__h165222 } ; - assign result__h203865 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[0] | - guard__h203860 } ; - assign result__h242804 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[0] | - guard__h242799 } ; - assign result__h287827 = - { _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[56:1], - _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[0] | - guard__h287822 } ; - assign result__h32617 = { _theResult____h32523[57:1], 1'd1 } ; - assign result__h32648 = - { 1'd0, - value__h32661[56:1], - value__h32661[0] | sfdlsb__h32643 } ; - assign result__h32823 = - (IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] == - 57'd0) ? - 58'd0 : - 58'd1 ; - assign result__h85925 = { x__h85931[58:1], 1'd1 } ; - assign rg_index_1_4_PLUS_1_6_ULE_58___d37 = rg_index_1 + 6'd1 <= 6'd58 ; - assign rg_index_1_4_ULE_58___d38 = rg_index_1 <= 6'd58 ; - assign rg_index_PLUS_1_ULE_57___d6 = rg_index + 6'd1 <= 6'd57 ; - assign rg_index_ULE_57___d7 = rg_index <= 6'd57 ; - assign rg_q_PLUS_NEG_INV_rg_q_59_60___d561 = rg_q + -(~rg_q) ; - assign rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63 = rg_s < sum__h1606 ; - assign s__h1658 = rg_s - sum__h1606 ; - assign s__h1723 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 - - sum__h1710 ; - assign sfdA__h131577 = - { 1'b0, - fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } ; - assign sfdA__h2035 = - { fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0, - fpu_div64_fOperands_S0$D_OUT[118:67] } ; - assign sfdA__h2039 = sfdA__h2035 << b__h4039 ; - assign sfdBC__h115662 = - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ? - fpu_madd_fProd_S3$D_OUT : - _theResult___fst__h116827 ; - assign sfdBC__h131578 = - { 1'b0, - fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } ; - assign sfdB__h2036 = - { fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0, - fpu_div64_fOperands_S0$D_OUT[54:3] } ; - assign sfdB__h2041 = sfdB__h2036 << b__h11457 ; - assign sfd___1__h60702 = { 1'd0, sfd__h44953[57:1] } ; - assign sfd__h133119 = - fpu_madd_fState_S7$D_OUT[128] ? - fpu_madd_fState_S7$D_OUT[56:0] : - fpu_madd_fState_S7$D_OUT[113:57] ; - assign sfd__h142040 = - { 1'b0, - fpu_madd_fState_S8$D_OUT[65:55] != 11'd0, - fpu_madd_fState_S8$D_OUT[54:3] } + - 54'd1 ; - assign sfd__h144536 = { value__h148923, 32'd0 } ; - assign sfd__h163354 = - { 1'b0, - _theResult___fst_exp__h163336 != 11'd0, - _theResult___snd__h163287[56:5] } + - 54'd1 ; - assign sfd__h172944 = - { 1'b0, - _theResult___fst_exp__h172852 != 11'd0, - sfdin__h172846[56:5] } + - 54'd1 ; - assign sfd__h181672 = - { 1'b0, - _theResult___fst_exp__h181653 != 11'd0, - _theResult___snd__h181599[56:5] } + - 54'd1 ; - assign sfd__h183176 = { value__h187561, 32'd0 } ; - assign sfd__h18934 = { 1'd1, fpu_div64_fOperands_S0$D_OUT[117:67] } ; - assign sfd__h18937 = { 1'd1, fpu_div64_fOperands_S0$D_OUT[53:3] } ; - assign sfd__h201992 = - { 1'b0, - _theResult___fst_exp__h201974 != 11'd0, - _theResult___snd__h201925[56:5] } + - 54'd1 ; - assign sfd__h211582 = - { 1'b0, - _theResult___fst_exp__h211490 != 11'd0, - sfdin__h211484[56:5] } + - 54'd1 ; - assign sfd__h220310 = - { 1'b0, - _theResult___fst_exp__h220291 != 11'd0, - _theResult___snd__h220237[56:5] } + - 54'd1 ; - assign sfd__h222115 = { value__h226500, 32'd0 } ; - assign sfd__h240931 = - { 1'b0, - _theResult___fst_exp__h240913 != 11'd0, - _theResult___snd__h240864[56:5] } + - 54'd1 ; - assign sfd__h250521 = - { 1'b0, - _theResult___fst_exp__h250429 != 11'd0, - sfdin__h250423[56:5] } + - 54'd1 ; - assign sfd__h259249 = - { 1'b0, - _theResult___fst_exp__h259230 != 11'd0, - _theResult___snd__h259176[56:5] } + - 54'd1 ; - assign sfd__h261975 = { value__h270197, 3'd0 } ; - assign sfd__h277778 = - { 1'b0, - _theResult___fst_exp__h277686 != 8'd0, - sfdin__h277680[56:34] } + - 25'd1 ; - assign sfd__h286360 = - { 1'b0, - _theResult___fst_exp__h286342 != 8'd0, - _theResult___snd__h286293[56:34] } + - 25'd1 ; - assign sfd__h295544 = - { 1'b0, - _theResult___fst_exp__h295452 != 8'd0, - sfdin__h295446[56:34] } + - 25'd1 ; - assign sfd__h304156 = - { 1'b0, - _theResult___fst_exp__h304137 != 8'd0, - _theResult___snd__h304083[56:34] } + - 25'd1 ; - assign sfd__h304707 = - (resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h261925 : - _theResult___fst_sfd__h304701 ; - assign sfd__h42982 = - { 1'b0, - fpu_div64_fState_S4$D_OUT[64:54] != 11'd0, - fpu_div64_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfd__h44951 = { value__h53174, 4'd0 } ; - assign sfd__h44953 = sfd__h44951 << x__h60732 ; - assign sfd__h45004 = { 1'd1, fpu_sqr64_fOperand_S0$D_OUT[53:3] } ; - assign sfd__h95416 = - { 1'b0, - fpu_sqr64_fState_S4$D_OUT[64:54] != 11'd0, - fpu_sqr64_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfd__h99402 = { 1'd1, _theResult___fst_sfd__h96608[50:0] } ; - assign sfd__h99405 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[117:67] } ; - assign sfd__h99408 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[53:3] } ; - assign sfdin__h130943 = - sfdBC__h115662[105] ? - _theResult___snd__h130966 : - _theResult___snd__h130980 ; - assign sfdin__h141369 = - sfd__h133119[56] ? - _theResult___snd__h141392 : - _theResult___snd__h141406 ; - assign sfdin__h172846 = - _theResult____h164614[56] ? - _theResult___snd__h172863 : - _theResult___snd__h172874 ; - assign sfdin__h211484 = - _theResult____h203252[56] ? - _theResult___snd__h211501 : - _theResult___snd__h211512 ; - assign sfdin__h250423 = - _theResult____h242191[56] ? - _theResult___snd__h250440 : - _theResult___snd__h250451 ; - assign sfdin__h277680 = - _theResult____h269577[56] ? - _theResult___snd__h277697 : - _theResult___snd__h277708 ; - assign sfdin__h295446 = - _theResult____h287214[56] ? - _theResult___snd__h295463 : - _theResult___snd__h295474 ; - assign sfdin__h34118 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___snd_snd_snd__h33963 : - fpu_div64_fState_S3$D_OUT[57:0] ; - assign sfdin__h42327 = - sfdin__h34118[57] ? - _theResult___snd__h42350 : - _theResult___snd__h42365 ; - assign sfdin__h94744 = - fpu_sqr64_fState_S3$D_OUT[58] ? - _theResult___snd__h94767 : - _theResult___snd__h94782 ; - assign sfdlsb__h116825 = x__h116896 != 106'd0 ; - assign sfdlsb__h32643 = x__h32762 != 58'd0 ; - assign sum__h1606 = rg_r_1 + rg_b ; - assign sum__h1710 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 + - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign theResult___fst_exp2290_MINUS_1023__q11 = - _theResult___fst_exp__h42290 - 11'd1023 ; - assign value41307_BITS_10_TO_0_MINUS_1023__q28 = - value__h141307[10:0] - 11'd1023 ; - assign value_BIT_52___h53270 = fpu_sqr64_fOperand_S0$D_OUT[65:55] != 11'd0 ; - assign value__h130883 = fpu_madd_fState_S3$D_OUT[12:0] + 13'd1023 ; - assign value__h141307 = fpu_madd_fState_S7$D_OUT[126:114] + 13'd1023 ; - assign value__h148923 = - { 1'b0, iFifo$D_OUT[167:160] != 8'd0, iFifo$D_OUT[159:137] } ; - assign value__h187561 = - { 1'b0, iFifo$D_OUT[102:95] != 8'd0, iFifo$D_OUT[94:72] } ; - assign value__h226500 = - { 1'b0, iFifo$D_OUT[37:30] != 8'd0, iFifo$D_OUT[29:7] } ; - assign value__h270197 = - { 1'b0, resWire$wget[67:57] != 11'd0, resWire$wget[56:5] } ; - assign value__h31374 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 + - 13'd1023 ; - assign value__h31429 = { 1'b0, sfdA__h2039 } ; - assign value__h31550 = - 13'd7170 - - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ; - assign value__h32541 = rg_r[115] ? rg_r + b__h32583 : rg_r ; - assign value__h32661 = - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] >> - fpu_div64_fState_S2$D_OUT[10:0] ; - assign value__h53174 = - { 1'b0, - value_BIT_52___h53270, - fpu_sqr64_fOperand_S0$D_OUT[54:3] } ; - assign x__h114243 = - { fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0, - fpu_madd_fOperand_S0$D_OUT[118:67] } ; - assign x__h114255 = - { fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0, - fpu_madd_fOperand_S0$D_OUT[54:3] } ; - assign x__h116896 = fpu_madd_fProd_S3$D_OUT << x__h116929 ; - assign x__h116929 = - 13'd106 - - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ; - assign x__h131406 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - _theResult___snd_snd_snd__h131369 : - 2'd3 ; - assign x__h131940 = - { 1'b0, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - { fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } : - { fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } } ; - assign x__h131944 = - { 1'b0, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - { fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } : - { fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } } ; - assign x__h132359 = - fpu_madd_fState_S5$D_OUT[215] ? - fpu_madd_fState_S5$D_OUT[56:0] : - (((fpu_madd_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ? - result__h132372 : - ((fpu_madd_fState_S5$D_OUT[56:0] == 57'd0) ? - fpu_madd_fState_S5$D_OUT[56:0] : - 57'd1)) ; - assign x__h132471 = 13'd57 - fpu_madd_fState_S5$D_OUT[126:114] ; - assign x__h132871 = - fpu_madd_fState_S6$D_OUT[113:57] + - fpu_madd_fState_S6$D_OUT[56:0] ; - assign x__h132880 = - fpu_madd_fState_S6$D_OUT[113:57] - - fpu_madd_fState_S6$D_OUT[56:0] ; - assign x__h141760 = fpu_madd_fState_S7$D_OUT[202] ? 2'd0 : guard__h133123 ; - assign x__h165324 = sfd__h144536 << x__h165357 ; - assign x__h165357 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ; - assign x__h203962 = sfd__h183176 << x__h203995 ; - assign x__h203995 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ; - assign x__h242901 = sfd__h222115 << x__h242934 ; - assign x__h242934 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ; - assign x__h287924 = sfd__h261975 << x__h287957 ; - assign x__h287957 = - 12'd57 - - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ; - assign x__h31426 = { value__h31429, 60'd0 } ; - assign x__h31487 = { sfdB__h2041, 4'b0 } ; - assign x__h31541 = - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363 ? - 11'd0 : - _theResult___fst__h31322 ; - assign x__h32762 = - { 1'd0, - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] } << - x__h32769 ; - assign x__h32769 = 11'd58 - fpu_div64_fState_S2$D_OUT[10:0] ; - assign x__h33052 = - (value__h32541[114:58] == 57'd0) ? - _theResult____h32523 : - result__h32617 ; - assign x__h42705 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h42439 ; - assign x__h52551 = x__h52569 + 13'd1024 ; - assign x__h52569 = - { IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17[11], - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17 } ; - assign x__h60693 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195[0] ? - sfd__h44953 : - sfd___1__h60702 ; - assign x__h60732 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 - - 6'd1 ; - assign x__h85465 = - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342[0] ? - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 + - 7'd1 : - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 ; - assign x__h85931 = rg_res[116] ? rg_res[115:0] : 116'd0 ; - assign x__h86149 = (rg_s == 116'd0) ? x__h85931[58:0] : result__h85925 ; - assign x__h95138 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h94856 ; - assign x__h96539 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[193:183] : - 11'd0 ; - always@(fpu_div64_fState_S4$D_OUT or - out_sfd__h43479 or _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - fpu_div64_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - out_sfd__h43479; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - _theResult___sfd__h43476; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 = - fpu_div64_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 = - _theResult___sfd__h43476; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 or - _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h43554 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1; - 3'd1: - _theResult___fst_sfd__h43554 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2; - 3'd2: - _theResult___fst_sfd__h43554 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[53:2] : - _theResult___sfd__h43476; - 3'd3: - _theResult___fst_sfd__h43554 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[53:2] : - (fpu_div64_fState_S4$D_OUT[65] ? - _theResult___sfd__h43476 : - fpu_div64_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h43554 = fpu_div64_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h43554 = 52'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - out_sfd__h95913 or _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - fpu_sqr64_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - out_sfd__h95913; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - _theResult___sfd__h95910; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 = - fpu_sqr64_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 = - _theResult___sfd__h95910; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 or - _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h95988 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3; - 3'd1: - _theResult___fst_sfd__h95988 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4; - 3'd2: - _theResult___fst_sfd__h95988 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - _theResult___sfd__h95910; - 3'd3: - _theResult___fst_sfd__h95988 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - _theResult___sfd__h95910 : - fpu_sqr64_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h95988 = fpu_sqr64_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h95988 = 52'd0; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - out_sfd__h142545 or _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - fpu_madd_fState_S8$D_OUT[54:3]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - out_sfd__h142545; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - _theResult___sfd__h142542; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 = - fpu_madd_fState_S8$D_OUT[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 = - _theResult___sfd__h142542; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 or - _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_sfd__h142620 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5; - 3'd1: - _theResult___fst_sfd__h142620 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6; - 3'd2: - _theResult___fst_sfd__h142620 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___sfd__h142542; - 3'd3: - _theResult___fst_sfd__h142620 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[54:3] : - (fpu_madd_fState_S8$D_OUT[66] ? - _theResult___sfd__h142542 : - fpu_madd_fState_S8$D_OUT[54:3]); - 3'd4: _theResult___fst_sfd__h142620 = fpu_madd_fState_S8$D_OUT[54:3]; - default: _theResult___fst_sfd__h142620 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h148291 = 11'd2047; - 3'd2: - _theResult___fst_exp__h148291 = - iFifo$D_OUT[168] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h148291 = - iFifo$D_OUT[168] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h148291 = 11'd2046; - default: _theResult___fst_exp__h148291 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h148292 = 52'd0; - 3'd2: - _theResult___fst_sfd__h148292 = - iFifo$D_OUT[168] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h148292 = - iFifo$D_OUT[168] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h148292 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h148292 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h186931 = 11'd2047; - 3'd2: - _theResult___fst_exp__h186931 = - iFifo$D_OUT[103] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h186931 = - iFifo$D_OUT[103] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h186931 = 11'd2046; - default: _theResult___fst_exp__h186931 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h225870 = 11'd2047; - 3'd2: - _theResult___fst_exp__h225870 = - iFifo$D_OUT[38] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h225870 = - iFifo$D_OUT[38] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h225870 = 11'd2046; - default: _theResult___fst_exp__h225870 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h186932 = 52'd0; - 3'd2: - _theResult___fst_sfd__h186932 = - iFifo$D_OUT[103] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h186932 = - iFifo$D_OUT[103] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h186932 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h186932 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h225871 = 52'd0; - 3'd2: - _theResult___fst_sfd__h225871 = - iFifo$D_OUT[38] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h225871 = - iFifo$D_OUT[38] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h225871 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h225871 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_exp__h19467 = 11'd2047; - 3'd2: - _theResult___fst_exp__h19467 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 11'd2047 : - 11'd2046; - 3'd3: - _theResult___fst_exp__h19467 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 11'd2046 : - 11'd2047; - 3'd4: _theResult___fst_exp__h19467 = 11'd2046; - default: _theResult___fst_exp__h19467 = 11'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_sfd__h19468 = 52'd0; - 3'd2: - _theResult___fst_sfd__h19468 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'd3: - _theResult___fst_sfd__h19468 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'hFFFFFFFFFFFFF : - 52'd0; - 3'd4: _theResult___fst_sfd__h19468 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h19468 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0: _theResult___fst_sfd__h19957 = 52'd0; - 3'd1: _theResult___fst_sfd__h19957 = 52'd1; - 3'd2: - _theResult___fst_sfd__h19957 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd1 : - 52'd0; - 3'd3: - _theResult___fst_sfd__h19957 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd0 : - 52'd1; - default: _theResult___fst_sfd__h19957 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 = - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405; - default: CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 = - fpu_div64_fOperands_S0$D_OUT[2:0] == 3'd4 && - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - out_exp__h43478 or _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - fpu_div64_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - out_exp__h43478; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - _theResult___exp__h43475; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 = - fpu_div64_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 = - _theResult___exp__h43475; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 or - _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h43553 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14; - 3'd1: - _theResult___fst_exp__h43553 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15; - 3'd2: - _theResult___fst_exp__h43553 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[64:54] : - _theResult___exp__h43475; - 3'd3: - _theResult___fst_exp__h43553 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[64:54] : - (fpu_div64_fState_S4$D_OUT[65] ? - _theResult___exp__h43475 : - fpu_div64_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h43553 = fpu_div64_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h43553 = 11'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - out_exp__h95912 or _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - fpu_sqr64_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - out_exp__h95912; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - _theResult___exp__h95909; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 = - fpu_sqr64_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 = - _theResult___exp__h95909; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 or - _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h95987 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21; - 3'd1: - _theResult___fst_exp__h95987 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22; - 3'd2: - _theResult___fst_exp__h95987 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - _theResult___exp__h95909; - 3'd3: - _theResult___fst_exp__h95987 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - _theResult___exp__h95909 : - fpu_sqr64_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h95987 = fpu_sqr64_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h95987 = 11'd0; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - out_exp__h142544 or _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - fpu_madd_fState_S8$D_OUT[65:55]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - out_exp__h142544; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - _theResult___exp__h142541; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 = - fpu_madd_fState_S8$D_OUT[65:55]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 = - _theResult___exp__h142541; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 or - _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_exp__h142619 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31; - 3'd1: - _theResult___fst_exp__h142619 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32; - 3'd2: - _theResult___fst_exp__h142619 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[65:55] : - _theResult___exp__h142541; - 3'd3: - _theResult___fst_exp__h142619 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[65:55] : - (fpu_madd_fState_S8$D_OUT[66] ? - _theResult___exp__h142541 : - fpu_madd_fState_S8$D_OUT[65:55]); - 3'd4: _theResult___fst_exp__h142619 = fpu_madd_fState_S8$D_OUT[65:55]; - default: _theResult___fst_exp__h142619 = 11'd0; - endcase - end - always@(guard__h155375 or - _theResult___fst_exp__h163336 or - out_exp__h163984 or _theResult___exp__h163981) - begin - case (guard__h155375) - 2'b0, 2'b01: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - _theResult___fst_exp__h163336; - 2'b10: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - out_exp__h163984; - 2'b11: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - _theResult___exp__h163981; - endcase - end - always@(guard__h155375 or - _theResult___fst_exp__h163336 or _theResult___exp__h163981) - begin - case (guard__h155375) - 2'b0: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 = - _theResult___fst_exp__h163336; - 2'b01, 2'b10, 2'b11: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 = - _theResult___exp__h163981; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 or - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 or - _theResult___fst_exp__h163336) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h164059 = - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42; - 3'd1: - _theResult___fst_exp__h164059 = - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43; - 3'd2: - _theResult___fst_exp__h164059 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690; - 3'd3: - _theResult___fst_exp__h164059 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692; - 3'd4: _theResult___fst_exp__h164059 = _theResult___fst_exp__h163336; - default: _theResult___fst_exp__h164059 = 11'd0; - endcase - end - always@(guard__h164624 or - _theResult___fst_exp__h172852 or - out_exp__h173574 or _theResult___exp__h173571) - begin - case (guard__h164624) - 2'b0, 2'b01: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - _theResult___fst_exp__h172852; - 2'b10: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - out_exp__h173574; - 2'b11: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - _theResult___exp__h173571; - endcase - end - always@(guard__h164624 or - _theResult___fst_exp__h172852 or _theResult___exp__h173571) - begin - case (guard__h164624) - 2'b0: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 = - _theResult___fst_exp__h172852; - 2'b01, 2'b10, 2'b11: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 = - _theResult___exp__h173571; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 or - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 or - _theResult___fst_exp__h172852) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h173649 = - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44; - 3'd1: - _theResult___fst_exp__h173649 = - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45; - 3'd2: - _theResult___fst_exp__h173649 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729; - 3'd3: - _theResult___fst_exp__h173649 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731; - 3'd4: _theResult___fst_exp__h173649 = _theResult___fst_exp__h172852; - default: _theResult___fst_exp__h173649 = 11'd0; - endcase - end - always@(guard__h173663 or - _theResult___fst_exp__h181653 or - out_exp__h182326 or _theResult___exp__h182323) - begin - case (guard__h173663) - 2'b0, 2'b01: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - _theResult___fst_exp__h181653; - 2'b10: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - out_exp__h182326; - 2'b11: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - _theResult___exp__h182323; - endcase - end - always@(guard__h173663 or - _theResult___fst_exp__h181653 or _theResult___exp__h182323) - begin - case (guard__h173663) - 2'b0: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 = - _theResult___fst_exp__h181653; - 2'b01, 2'b10, 2'b11: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 = - _theResult___exp__h182323; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 or - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 or - _theResult___fst_exp__h181653) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h182401 = - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46; - 3'd1: - _theResult___fst_exp__h182401 = - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47; - 3'd2: - _theResult___fst_exp__h182401 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760; - 3'd3: - _theResult___fst_exp__h182401 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762; - 3'd4: _theResult___fst_exp__h182401 = _theResult___fst_exp__h181653; - default: _theResult___fst_exp__h182401 = 11'd0; - endcase - end - always@(guard__h155375 or - _theResult___snd__h163287 or - out_sfd__h163985 or _theResult___sfd__h163982) - begin - case (guard__h155375) - 2'b0, 2'b01: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - _theResult___snd__h163287[56:5]; - 2'b10: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - out_sfd__h163985; - 2'b11: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - _theResult___sfd__h163982; - endcase - end - always@(guard__h155375 or - _theResult___snd__h163287 or _theResult___sfd__h163982) - begin - case (guard__h155375) - 2'b0: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 = - _theResult___snd__h163287[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 = - _theResult___sfd__h163982; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 or - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 or - _theResult___snd__h163287) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h164060 = - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48; - 3'd1: - _theResult___fst_sfd__h164060 = - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49; - 3'd2: - _theResult___fst_sfd__h164060 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786; - 3'd3: - _theResult___fst_sfd__h164060 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788; - 3'd4: _theResult___fst_sfd__h164060 = _theResult___snd__h163287[56:5]; - default: _theResult___fst_sfd__h164060 = 52'd0; - endcase - end - always@(guard__h164624 or - sfdin__h172846 or out_sfd__h173575 or _theResult___sfd__h173572) - begin - case (guard__h164624) - 2'b0, 2'b01: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - sfdin__h172846[56:5]; - 2'b10: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - out_sfd__h173575; - 2'b11: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - _theResult___sfd__h173572; - endcase - end - always@(guard__h164624 or sfdin__h172846 or _theResult___sfd__h173572) - begin - case (guard__h164624) - 2'b0: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 = - sfdin__h172846[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 = - _theResult___sfd__h173572; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 or - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 or - sfdin__h172846) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h173650 = - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50; - 3'd1: - _theResult___fst_sfd__h173650 = - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51; - 3'd2: - _theResult___fst_sfd__h173650 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813; - 3'd3: - _theResult___fst_sfd__h173650 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815; - 3'd4: _theResult___fst_sfd__h173650 = sfdin__h172846[56:5]; - default: _theResult___fst_sfd__h173650 = 52'd0; - endcase - end - always@(guard__h173663 or - _theResult___snd__h181599 or - out_sfd__h182327 or _theResult___sfd__h182324) - begin - case (guard__h173663) - 2'b0, 2'b01: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - _theResult___snd__h181599[56:5]; - 2'b10: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - out_sfd__h182327; - 2'b11: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - _theResult___sfd__h182324; - endcase - end - always@(guard__h173663 or - _theResult___snd__h181599 or _theResult___sfd__h182324) - begin - case (guard__h173663) - 2'b0: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 = - _theResult___snd__h181599[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 = - _theResult___sfd__h182324; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 or - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 or - _theResult___snd__h181599) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h182402 = - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52; - 3'd1: - _theResult___fst_sfd__h182402 = - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53; - 3'd2: - _theResult___fst_sfd__h182402 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832; - 3'd3: - _theResult___fst_sfd__h182402 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834; - 3'd4: _theResult___fst_sfd__h182402 = _theResult___snd__h181599[56:5]; - default: _theResult___fst_sfd__h182402 = 52'd0; - endcase - end - always@(guard__h155375 or iFifo$D_OUT) - begin - case (guard__h155375) - 2'b0, 2'b01, 2'b10: - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 = - guard__h155375 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 or - guard__h155375) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - (guard__h155375 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h155375 == 2'b01 || guard__h155375 == 2'b10 || - guard__h155375 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 = - iFifo$D_OUT[168]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h164624 or iFifo$D_OUT) - begin - case (guard__h164624) - 2'b0, 2'b01, 2'b10: - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 = - guard__h164624 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 or - guard__h164624) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - (guard__h164624 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h164624 == 2'b01 || guard__h164624 == 2'b10 || - guard__h164624 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h173663 or iFifo$D_OUT) - begin - case (guard__h173663) - 2'b0, 2'b01, 2'b10: - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 = - guard__h173663 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 or - guard__h173663) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - (guard__h173663 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h173663 == 2'b01 || guard__h173663 == 2'b10 || - guard__h173663 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h232952 or - _theResult___fst_exp__h240913 or - out_exp__h241561 or _theResult___exp__h241558) - begin - case (guard__h232952) - 2'b0, 2'b01: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - _theResult___fst_exp__h240913; - 2'b10: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - out_exp__h241561; - 2'b11: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - _theResult___exp__h241558; - endcase - end - always@(guard__h232952 or - _theResult___fst_exp__h240913 or _theResult___exp__h241558) - begin - case (guard__h232952) - 2'b0: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 = - _theResult___fst_exp__h240913; - 2'b01, 2'b10, 2'b11: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 = - _theResult___exp__h241558; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 or - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 or - _theResult___fst_exp__h240913) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h241636 = - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69; - 3'd1: - _theResult___fst_exp__h241636 = - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70; - 3'd2: - _theResult___fst_exp__h241636 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398; - 3'd3: - _theResult___fst_exp__h241636 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400; - 3'd4: _theResult___fst_exp__h241636 = _theResult___fst_exp__h240913; - default: _theResult___fst_exp__h241636 = 11'd0; - endcase - end - always@(guard__h242201 or - _theResult___fst_exp__h250429 or - out_exp__h251151 or _theResult___exp__h251148) - begin - case (guard__h242201) - 2'b0, 2'b01: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - _theResult___fst_exp__h250429; - 2'b10: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - out_exp__h251151; - 2'b11: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - _theResult___exp__h251148; - endcase - end - always@(guard__h242201 or - _theResult___fst_exp__h250429 or _theResult___exp__h251148) - begin - case (guard__h242201) - 2'b0: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 = - _theResult___fst_exp__h250429; - 2'b01, 2'b10, 2'b11: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 = - _theResult___exp__h251148; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 or - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 or - _theResult___fst_exp__h250429) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h251226 = - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71; - 3'd1: - _theResult___fst_exp__h251226 = - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72; - 3'd2: - _theResult___fst_exp__h251226 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436; - 3'd3: - _theResult___fst_exp__h251226 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438; - 3'd4: _theResult___fst_exp__h251226 = _theResult___fst_exp__h250429; - default: _theResult___fst_exp__h251226 = 11'd0; - endcase - end - always@(guard__h251240 or - _theResult___fst_exp__h259230 or - out_exp__h259903 or _theResult___exp__h259900) - begin - case (guard__h251240) - 2'b0, 2'b01: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - _theResult___fst_exp__h259230; - 2'b10: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - out_exp__h259903; - 2'b11: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - _theResult___exp__h259900; - endcase - end - always@(guard__h251240 or - _theResult___fst_exp__h259230 or _theResult___exp__h259900) - begin - case (guard__h251240) - 2'b0: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 = - _theResult___fst_exp__h259230; - 2'b01, 2'b10, 2'b11: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 = - _theResult___exp__h259900; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 or - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 or - _theResult___fst_exp__h259230) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h259978 = - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73; - 3'd1: - _theResult___fst_exp__h259978 = - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74; - 3'd2: - _theResult___fst_exp__h259978 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467; - 3'd3: - _theResult___fst_exp__h259978 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469; - 3'd4: _theResult___fst_exp__h259978 = _theResult___fst_exp__h259230; - default: _theResult___fst_exp__h259978 = 11'd0; - endcase - end - always@(guard__h232952 or - _theResult___snd__h240864 or - out_sfd__h241562 or _theResult___sfd__h241559) - begin - case (guard__h232952) - 2'b0, 2'b01: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - _theResult___snd__h240864[56:5]; - 2'b10: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - out_sfd__h241562; - 2'b11: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - _theResult___sfd__h241559; - endcase - end - always@(guard__h232952 or - _theResult___snd__h240864 or _theResult___sfd__h241559) - begin - case (guard__h232952) - 2'b0: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 = - _theResult___snd__h240864[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 = - _theResult___sfd__h241559; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 or - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 or - _theResult___snd__h240864) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h241637 = - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75; - 3'd1: - _theResult___fst_sfd__h241637 = - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76; - 3'd2: - _theResult___fst_sfd__h241637 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493; - 3'd3: - _theResult___fst_sfd__h241637 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495; - 3'd4: _theResult___fst_sfd__h241637 = _theResult___snd__h240864[56:5]; - default: _theResult___fst_sfd__h241637 = 52'd0; - endcase - end - always@(guard__h242201 or - sfdin__h250423 or out_sfd__h251152 or _theResult___sfd__h251149) - begin - case (guard__h242201) - 2'b0, 2'b01: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - sfdin__h250423[56:5]; - 2'b10: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - out_sfd__h251152; - 2'b11: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - _theResult___sfd__h251149; - endcase - end - always@(guard__h242201 or sfdin__h250423 or _theResult___sfd__h251149) - begin - case (guard__h242201) - 2'b0: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 = - sfdin__h250423[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 = - _theResult___sfd__h251149; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 or - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 or - sfdin__h250423) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h251227 = - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77; - 3'd1: - _theResult___fst_sfd__h251227 = - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78; - 3'd2: - _theResult___fst_sfd__h251227 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519; - 3'd3: - _theResult___fst_sfd__h251227 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521; - 3'd4: _theResult___fst_sfd__h251227 = sfdin__h250423[56:5]; - default: _theResult___fst_sfd__h251227 = 52'd0; - endcase - end - always@(guard__h251240 or - _theResult___snd__h259176 or - out_sfd__h259904 or _theResult___sfd__h259901) - begin - case (guard__h251240) - 2'b0, 2'b01: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - _theResult___snd__h259176[56:5]; - 2'b10: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - out_sfd__h259904; - 2'b11: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - _theResult___sfd__h259901; - endcase - end - always@(guard__h251240 or - _theResult___snd__h259176 or _theResult___sfd__h259901) - begin - case (guard__h251240) - 2'b0: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 = - _theResult___snd__h259176[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 = - _theResult___sfd__h259901; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 or - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 or - _theResult___snd__h259176) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h259979 = - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79; - 3'd1: - _theResult___fst_sfd__h259979 = - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80; - 3'd2: - _theResult___fst_sfd__h259979 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538; - 3'd3: - _theResult___fst_sfd__h259979 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540; - 3'd4: _theResult___fst_sfd__h259979 = _theResult___snd__h259176[56:5]; - default: _theResult___fst_sfd__h259979 = 52'd0; - endcase - end - always@(guard__h232952 or iFifo$D_OUT) - begin - case (guard__h232952) - 2'b0, 2'b01, 2'b10: - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 = - guard__h232952 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 or - guard__h232952) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - (guard__h232952 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h232952 == 2'b01 || guard__h232952 == 2'b10 || - guard__h232952 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 = - iFifo$D_OUT[38]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h242201 or iFifo$D_OUT) - begin - case (guard__h242201) - 2'b0, 2'b01, 2'b10: - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 = - guard__h242201 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 or - guard__h242201) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - (guard__h242201 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h242201 == 2'b01 || guard__h242201 == 2'b10 || - guard__h242201 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h251240 or iFifo$D_OUT) - begin - case (guard__h251240) - 2'b0, 2'b01, 2'b10: - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 = - guard__h251240 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 or - guard__h251240) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - (guard__h251240 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h251240 == 2'b01 || guard__h251240 == 2'b10 || - guard__h251240 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h232952 or iFifo$D_OUT) - begin - case (guard__h232952) - 2'b0, 2'b01, 2'b10: - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 = - guard__h232952 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 or - guard__h232952) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - (guard__h232952 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h232952 != 2'b01 && guard__h232952 != 2'b10 && - guard__h232952 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h242201 or iFifo$D_OUT) - begin - case (guard__h242201) - 2'b0, 2'b01, 2'b10: - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 = - guard__h242201 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 or - guard__h242201) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - (guard__h242201 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h242201 != 2'b01 && guard__h242201 != 2'b10 && - guard__h242201 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h251240 or iFifo$D_OUT) - begin - case (guard__h251240) - 2'b0, 2'b01, 2'b10: - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 = - guard__h251240 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 or - guard__h251240) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - (guard__h251240 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h251240 != 2'b01 && guard__h251240 != 2'b10 && - guard__h251240 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 = - !iFifo$D_OUT[38]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h194013 or - _theResult___fst_exp__h201974 or - out_exp__h202622 or _theResult___exp__h202619) - begin - case (guard__h194013) - 2'b0, 2'b01: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - _theResult___fst_exp__h201974; - 2'b10: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - out_exp__h202622; - 2'b11: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - _theResult___exp__h202619; - endcase - end - always@(guard__h194013 or - _theResult___fst_exp__h201974 or _theResult___exp__h202619) - begin - case (guard__h194013) - 2'b0: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 = - _theResult___fst_exp__h201974; - 2'b01, 2'b10, 2'b11: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 = - _theResult___exp__h202619; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 or - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 or - _theResult___fst_exp__h201974) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h202697 = - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102; - 3'd1: - _theResult___fst_exp__h202697 = - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103; - 3'd2: - _theResult___fst_exp__h202697 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173; - 3'd3: - _theResult___fst_exp__h202697 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175; - 3'd4: _theResult___fst_exp__h202697 = _theResult___fst_exp__h201974; - default: _theResult___fst_exp__h202697 = 11'd0; - endcase - end - always@(guard__h203262 or - _theResult___fst_exp__h211490 or - out_exp__h212212 or _theResult___exp__h212209) - begin - case (guard__h203262) - 2'b0, 2'b01: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - _theResult___fst_exp__h211490; - 2'b10: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - out_exp__h212212; - 2'b11: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - _theResult___exp__h212209; - endcase - end - always@(guard__h203262 or - _theResult___fst_exp__h211490 or _theResult___exp__h212209) - begin - case (guard__h203262) - 2'b0: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 = - _theResult___fst_exp__h211490; - 2'b01, 2'b10, 2'b11: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 = - _theResult___exp__h212209; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 or - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 or - _theResult___fst_exp__h211490) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h212287 = - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104; - 3'd1: - _theResult___fst_exp__h212287 = - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105; - 3'd2: - _theResult___fst_exp__h212287 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211; - 3'd3: - _theResult___fst_exp__h212287 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213; - 3'd4: _theResult___fst_exp__h212287 = _theResult___fst_exp__h211490; - default: _theResult___fst_exp__h212287 = 11'd0; - endcase - end - always@(guard__h212301 or - _theResult___fst_exp__h220291 or - out_exp__h220964 or _theResult___exp__h220961) - begin - case (guard__h212301) - 2'b0, 2'b01: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - _theResult___fst_exp__h220291; - 2'b10: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - out_exp__h220964; - 2'b11: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - _theResult___exp__h220961; - endcase - end - always@(guard__h212301 or - _theResult___fst_exp__h220291 or _theResult___exp__h220961) - begin - case (guard__h212301) - 2'b0: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 = - _theResult___fst_exp__h220291; - 2'b01, 2'b10, 2'b11: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 = - _theResult___exp__h220961; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 or - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 or - _theResult___fst_exp__h220291) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h221039 = - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106; - 3'd1: - _theResult___fst_exp__h221039 = - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107; - 3'd2: - _theResult___fst_exp__h221039 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242; - 3'd3: - _theResult___fst_exp__h221039 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244; - 3'd4: _theResult___fst_exp__h221039 = _theResult___fst_exp__h220291; - default: _theResult___fst_exp__h221039 = 11'd0; - endcase - end - always@(guard__h194013 or - _theResult___snd__h201925 or - out_sfd__h202623 or _theResult___sfd__h202620) - begin - case (guard__h194013) - 2'b0, 2'b01: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - _theResult___snd__h201925[56:5]; - 2'b10: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - out_sfd__h202623; - 2'b11: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - _theResult___sfd__h202620; - endcase - end - always@(guard__h194013 or - _theResult___snd__h201925 or _theResult___sfd__h202620) - begin - case (guard__h194013) - 2'b0: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 = - _theResult___snd__h201925[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 = - _theResult___sfd__h202620; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 or - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 or - _theResult___snd__h201925) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h202698 = - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108; - 3'd1: - _theResult___fst_sfd__h202698 = - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109; - 3'd2: - _theResult___fst_sfd__h202698 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268; - 3'd3: - _theResult___fst_sfd__h202698 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270; - 3'd4: _theResult___fst_sfd__h202698 = _theResult___snd__h201925[56:5]; - default: _theResult___fst_sfd__h202698 = 52'd0; - endcase - end - always@(guard__h203262 or - sfdin__h211484 or out_sfd__h212213 or _theResult___sfd__h212210) - begin - case (guard__h203262) - 2'b0, 2'b01: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - sfdin__h211484[56:5]; - 2'b10: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - out_sfd__h212213; - 2'b11: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - _theResult___sfd__h212210; - endcase - end - always@(guard__h203262 or sfdin__h211484 or _theResult___sfd__h212210) - begin - case (guard__h203262) - 2'b0: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 = - sfdin__h211484[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 = - _theResult___sfd__h212210; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 or - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 or - sfdin__h211484) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h212288 = - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110; - 3'd1: - _theResult___fst_sfd__h212288 = - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111; - 3'd2: - _theResult___fst_sfd__h212288 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294; - 3'd3: - _theResult___fst_sfd__h212288 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296; - 3'd4: _theResult___fst_sfd__h212288 = sfdin__h211484[56:5]; - default: _theResult___fst_sfd__h212288 = 52'd0; - endcase - end - always@(guard__h212301 or - _theResult___snd__h220237 or - out_sfd__h220965 or _theResult___sfd__h220962) - begin - case (guard__h212301) - 2'b0, 2'b01: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - _theResult___snd__h220237[56:5]; - 2'b10: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - out_sfd__h220965; - 2'b11: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - _theResult___sfd__h220962; - endcase - end - always@(guard__h212301 or - _theResult___snd__h220237 or _theResult___sfd__h220962) - begin - case (guard__h212301) - 2'b0: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 = - _theResult___snd__h220237[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 = - _theResult___sfd__h220962; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 or - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 or - _theResult___snd__h220237) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h221040 = - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112; - 3'd1: - _theResult___fst_sfd__h221040 = - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113; - 3'd2: - _theResult___fst_sfd__h221040 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313; - 3'd3: - _theResult___fst_sfd__h221040 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315; - 3'd4: _theResult___fst_sfd__h221040 = _theResult___snd__h220237[56:5]; - default: _theResult___fst_sfd__h221040 = 52'd0; - endcase - end - always@(guard__h194013 or iFifo$D_OUT) - begin - case (guard__h194013) - 2'b0, 2'b01, 2'b10: - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 = - guard__h194013 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 or - guard__h194013) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - (guard__h194013 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h194013 == 2'b01 || guard__h194013 == 2'b10 || - guard__h194013 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 = - iFifo$D_OUT[103]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h203262 or iFifo$D_OUT) - begin - case (guard__h203262) - 2'b0, 2'b01, 2'b10: - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 = - guard__h203262 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 or - guard__h203262) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - (guard__h203262 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h203262 == 2'b01 || guard__h203262 == 2'b10 || - guard__h203262 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h212301 or iFifo$D_OUT) - begin - case (guard__h212301) - 2'b0, 2'b01, 2'b10: - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 = - guard__h212301 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 or - guard__h212301) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - (guard__h212301 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h212301 == 2'b01 || guard__h212301 == 2'b10 || - guard__h212301 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h194013 or iFifo$D_OUT) - begin - case (guard__h194013) - 2'b0, 2'b01, 2'b10: - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 = - guard__h194013 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 or - guard__h194013) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - (guard__h194013 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h194013 != 2'b01 && guard__h194013 != 2'b10 && - guard__h194013 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 = - !iFifo$D_OUT[103]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(guard__h203262 or iFifo$D_OUT) - begin - case (guard__h203262) - 2'b0, 2'b01, 2'b10: - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 = - guard__h203262 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 or - guard__h203262) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - (guard__h203262 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h203262 != 2'b01 && guard__h203262 != 2'b10 && - guard__h203262 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(guard__h212301 or iFifo$D_OUT) - begin - case (guard__h212301) - 2'b0, 2'b01, 2'b10: - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 = - guard__h212301 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 or - guard__h212301) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - (guard__h212301 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h212301 != 2'b01 && guard__h212301 != 2'b10 && - guard__h212301 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(fpu_madd_fState_S8$D_OUT) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 = - fpu_madd_fState_S8$D_OUT[66]; - 2'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 = - fpu_madd_fState_S8$D_OUT[2:1] == 2'b11 && - fpu_madd_fState_S8$D_OUT[66]; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126; - 3'd1: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[66] : - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b01 || - fpu_madd_fState_S8$D_OUT[2:1] == 2'b10 || - fpu_madd_fState_S8$D_OUT[2:1] == 2'b11) && - fpu_madd_fState_S8$D_OUT[66]; - 3'd2, 3'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - fpu_madd_fState_S8$D_OUT[66]; - default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - fpu_madd_fState_S8$D_OUT[70:68] == 3'd4 && - fpu_madd_fState_S8$D_OUT[66]; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 or - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848; - 4'd5, 4'd7: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555; - 4'd6: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618; - default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - fpu_madd_fState_S8$D_OUT[3] ? - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 : - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 = - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 = - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130; - 3'd1: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131; - 3'd2: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[65:3] : - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - 3'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[65:3] : - (fpu_madd_fState_S8$D_OUT[66] ? - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 : - fpu_madd_fState_S8$D_OUT[65:3]); - 3'd4: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - fpu_madd_fState_S8$D_OUT[65:3]; - default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - 63'd0; - endcase - end - always@(iFifo$D_OUT or - fpu_madd_fOperand_S0$FULL_N or - fpu_div64_fOperands_S0$FULL_N or fpu_sqr64_fOperand_S0$FULL_N) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1, 4'd2, 4'd5, 4'd6, 4'd7: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_madd_fOperand_S0$FULL_N; - 4'd3: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_div64_fOperands_S0$FULL_N; - 4'd4: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_sqr64_fOperand_S0$FULL_N; - default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - iFifo$D_OUT[3:0] != 4'd8 || fpu_madd_fOperand_S0$FULL_N; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1: _theResult___fst_exp__h269559 = 8'd255; - 3'd2: - _theResult___fst_exp__h269559 = resWire$wget[68] ? 8'd254 : 8'd255; - 3'd3: - _theResult___fst_exp__h269559 = resWire$wget[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h269559 = 8'd254; - default: _theResult___fst_exp__h269559 = 8'd0; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1: _theResult___fst_sfd__h269560 = 23'd0; - 3'd2: - _theResult___fst_sfd__h269560 = - resWire$wget[68] ? 23'd8388607 : 23'd0; - 3'd3: - _theResult___fst_sfd__h269560 = - resWire$wget[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h269560 = 23'd8388607; - default: _theResult___fst_sfd__h269560 = 23'd0; - endcase - end - always@(guard__h269587 or resWire$wget) - begin - case (guard__h269587) - 2'b0, 2'b01, 2'b10: - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 = - resWire$wget[68]; - 2'd3: - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 = - guard__h269587 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 or - guard__h269587) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - (guard__h269587 == 2'b0) ? - resWire$wget[68] : - (guard__h269587 == 2'b01 || guard__h269587 == 2'b10 || - guard__h269587 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h269587 or resWire$wget) - begin - case (guard__h269587) - 2'b0, 2'b01, 2'b10: - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 = - !resWire$wget[68]; - 2'd3: - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 = - guard__h269587 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 or - guard__h269587) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - (guard__h269587 == 2'b0) ? - !resWire$wget[68] : - guard__h269587 != 2'b01 && guard__h269587 != 2'b10 && - guard__h269587 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h278294 or resWire$wget) - begin - case (guard__h278294) - 2'b0, 2'b01, 2'b10: - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 = - resWire$wget[68]; - 2'd3: - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 = - guard__h278294 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 or - guard__h278294) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - (guard__h278294 == 2'b0) ? - resWire$wget[68] : - (guard__h278294 == 2'b01 || guard__h278294 == 2'b10 || - guard__h278294 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h278294 or resWire$wget) - begin - case (guard__h278294) - 2'b0, 2'b01, 2'b10: - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 = - !resWire$wget[68]; - 2'd3: - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 = - guard__h278294 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 or - guard__h278294) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - (guard__h278294 == 2'b0) ? - !resWire$wget[68] : - guard__h278294 != 2'b01 && guard__h278294 != 2'b10 && - guard__h278294 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h287224 or resWire$wget) - begin - case (guard__h287224) - 2'b0, 2'b01, 2'b10: - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 = - resWire$wget[68]; - 2'd3: - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 = - guard__h287224 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 or - guard__h287224) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - (guard__h287224 == 2'b0) ? - resWire$wget[68] : - (guard__h287224 == 2'b01 || guard__h287224 == 2'b10 || - guard__h287224 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h287224 or resWire$wget) - begin - case (guard__h287224) - 2'b0, 2'b01, 2'b10: - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 = - !resWire$wget[68]; - 2'd3: - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 = - guard__h287224 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 or - guard__h287224) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - (guard__h287224 == 2'b0) ? - !resWire$wget[68] : - guard__h287224 != 2'b01 && guard__h287224 != 2'b10 && - guard__h287224 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h296060 or resWire$wget) - begin - case (guard__h296060) - 2'b0, 2'b01, 2'b10: - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 = - resWire$wget[68]; - 2'd3: - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 = - guard__h296060 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 or - guard__h296060) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - (guard__h296060 == 2'b0) ? - resWire$wget[68] : - (guard__h296060 == 2'b01 || guard__h296060 == 2'b10 || - guard__h296060 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h296060 or resWire$wget) - begin - case (guard__h296060) - 2'b0, 2'b01, 2'b10: - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 = - !resWire$wget[68]; - 2'd3: - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 = - guard__h296060 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 or - guard__h296060) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - (guard__h296060 == 2'b0) ? - !resWire$wget[68] : - guard__h296060 != 2'b01 && guard__h296060 != 2'b10 && - guard__h296060 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h278294 or - _theResult___fst_exp__h286342 or - out_exp__h286787 or _theResult___exp__h286784) - begin - case (guard__h278294) - 2'b0, 2'b01: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - _theResult___fst_exp__h286342; - 2'b10: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - out_exp__h286787; - 2'b11: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - _theResult___exp__h286784; - endcase - end - always@(guard__h278294 or - _theResult___fst_exp__h286342 or _theResult___exp__h286784) - begin - case (guard__h278294) - 2'b0: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 = - _theResult___fst_exp__h286342; - 2'b01, 2'b10, 2'b11: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 = - _theResult___exp__h286784; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 or - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 or - _theResult___fst_exp__h286342) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h286862 = - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152; - 3'd1: - _theResult___fst_exp__h286862 = - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153; - 3'd2: - _theResult___fst_exp__h286862 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479; - 3'd3: - _theResult___fst_exp__h286862 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481; - 3'd4: _theResult___fst_exp__h286862 = _theResult___fst_exp__h286342; - default: _theResult___fst_exp__h286862 = 8'd0; - endcase - end - always@(guard__h269587 or - _theResult___fst_exp__h277686 or - out_exp__h278205 or _theResult___exp__h278202) - begin - case (guard__h269587) - 2'b0, 2'b01: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - _theResult___fst_exp__h277686; - 2'b10: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - out_exp__h278205; - 2'b11: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - _theResult___exp__h278202; - endcase - end - always@(guard__h269587 or - _theResult___fst_exp__h277686 or _theResult___exp__h278202) - begin - case (guard__h269587) - 2'b0: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 = - _theResult___fst_exp__h277686; - 2'b01, 2'b10, 2'b11: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 = - _theResult___exp__h278202; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 or - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 or - _theResult___fst_exp__h277686) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h278280 = - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154; - 3'd1: - _theResult___fst_exp__h278280 = - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155; - 3'd2: - _theResult___fst_exp__h278280 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448; - 3'd3: - _theResult___fst_exp__h278280 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450; - 3'd4: _theResult___fst_exp__h278280 = _theResult___fst_exp__h277686; - default: _theResult___fst_exp__h278280 = 8'd0; - endcase - end - always@(guard__h287224 or - _theResult___fst_exp__h295452 or - out_exp__h295971 or _theResult___exp__h295968) - begin - case (guard__h287224) - 2'b0, 2'b01: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - _theResult___fst_exp__h295452; - 2'b10: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - out_exp__h295971; - 2'b11: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - _theResult___exp__h295968; - endcase - end - always@(guard__h287224 or - _theResult___fst_exp__h295452 or _theResult___exp__h295968) - begin - case (guard__h287224) - 2'b0: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 = - _theResult___fst_exp__h295452; - 2'b01, 2'b10, 2'b11: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 = - _theResult___exp__h295968; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 or - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 or - _theResult___fst_exp__h295452) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h296046 = - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156; - 3'd1: - _theResult___fst_exp__h296046 = - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157; - 3'd2: - _theResult___fst_exp__h296046 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518; - 3'd3: - _theResult___fst_exp__h296046 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520; - 3'd4: _theResult___fst_exp__h296046 = _theResult___fst_exp__h295452; - default: _theResult___fst_exp__h296046 = 8'd0; - endcase - end - always@(guard__h296060 or - _theResult___fst_exp__h304137 or - out_exp__h304607 or _theResult___exp__h304604) - begin - case (guard__h296060) - 2'b0, 2'b01: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - _theResult___fst_exp__h304137; - 2'b10: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - out_exp__h304607; - 2'b11: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - _theResult___exp__h304604; - endcase - end - always@(guard__h296060 or - _theResult___fst_exp__h304137 or _theResult___exp__h304604) - begin - case (guard__h296060) - 2'b0: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 = - _theResult___fst_exp__h304137; - 2'b01, 2'b10, 2'b11: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 = - _theResult___exp__h304604; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 or - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 or - _theResult___fst_exp__h304137) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h304682 = - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158; - 3'd1: - _theResult___fst_exp__h304682 = - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159; - 3'd2: - _theResult___fst_exp__h304682 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549; - 3'd3: - _theResult___fst_exp__h304682 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551; - 3'd4: _theResult___fst_exp__h304682 = _theResult___fst_exp__h304137; - default: _theResult___fst_exp__h304682 = 8'd0; - endcase - end - always@(guard__h278294 or - _theResult___snd__h286293 or - out_sfd__h286788 or _theResult___sfd__h286785) - begin - case (guard__h278294) - 2'b0, 2'b01: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - _theResult___snd__h286293[56:34]; - 2'b10: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - out_sfd__h286788; - 2'b11: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - _theResult___sfd__h286785; - endcase - end - always@(guard__h278294 or - _theResult___snd__h286293 or _theResult___sfd__h286785) - begin - case (guard__h278294) - 2'b0: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 = - _theResult___snd__h286293[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 = - _theResult___sfd__h286785; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 or - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 or - _theResult___snd__h286293) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h286863 = - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160; - 3'd1: - _theResult___fst_sfd__h286863 = - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161; - 3'd2: - _theResult___fst_sfd__h286863 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595; - 3'd3: - _theResult___fst_sfd__h286863 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597; - 3'd4: _theResult___fst_sfd__h286863 = _theResult___snd__h286293[56:34]; - default: _theResult___fst_sfd__h286863 = 23'd0; - endcase - end - always@(guard__h269587 or - sfdin__h277680 or out_sfd__h278206 or _theResult___sfd__h278203) - begin - case (guard__h269587) - 2'b0, 2'b01: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - sfdin__h277680[56:34]; - 2'b10: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - out_sfd__h278206; - 2'b11: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - _theResult___sfd__h278203; - endcase - end - always@(guard__h269587 or sfdin__h277680 or _theResult___sfd__h278203) - begin - case (guard__h269587) - 2'b0: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 = - sfdin__h277680[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 = - _theResult___sfd__h278203; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 or - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 or - sfdin__h277680) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h278281 = - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162; - 3'd1: - _theResult___fst_sfd__h278281 = - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163; - 3'd2: - _theResult___fst_sfd__h278281 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576; - 3'd3: - _theResult___fst_sfd__h278281 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578; - 3'd4: _theResult___fst_sfd__h278281 = sfdin__h277680[56:34]; - default: _theResult___fst_sfd__h278281 = 23'd0; - endcase - end - always@(guard__h287224 or - sfdin__h295446 or out_sfd__h295972 or _theResult___sfd__h295969) - begin - case (guard__h287224) - 2'b0, 2'b01: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - sfdin__h295446[56:34]; - 2'b10: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - out_sfd__h295972; - 2'b11: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - _theResult___sfd__h295969; - endcase - end - always@(guard__h287224 or sfdin__h295446 or _theResult___sfd__h295969) - begin - case (guard__h287224) - 2'b0: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 = - sfdin__h295446[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 = - _theResult___sfd__h295969; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 or - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 or - sfdin__h295446) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h296047 = - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164; - 3'd1: - _theResult___fst_sfd__h296047 = - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165; - 3'd2: - _theResult___fst_sfd__h296047 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622; - 3'd3: - _theResult___fst_sfd__h296047 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624; - 3'd4: _theResult___fst_sfd__h296047 = sfdin__h295446[56:34]; - default: _theResult___fst_sfd__h296047 = 23'd0; - endcase - end - always@(guard__h296060 or - _theResult___snd__h304083 or - out_sfd__h304608 or _theResult___sfd__h304605) - begin - case (guard__h296060) - 2'b0, 2'b01: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - _theResult___snd__h304083[56:34]; - 2'b10: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - out_sfd__h304608; - 2'b11: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - _theResult___sfd__h304605; - endcase - end - always@(guard__h296060 or - _theResult___snd__h304083 or _theResult___sfd__h304605) - begin - case (guard__h296060) - 2'b0: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 = - _theResult___snd__h304083[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 = - _theResult___sfd__h304605; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 or - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 or - _theResult___snd__h304083) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h304683 = - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166; - 3'd1: - _theResult___fst_sfd__h304683 = - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167; - 3'd2: - _theResult___fst_sfd__h304683 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641; - 3'd3: - _theResult___fst_sfd__h304683 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643; - 3'd4: _theResult___fst_sfd__h304683 = _theResult___snd__h304083[56:34]; - default: _theResult___fst_sfd__h304683 = 23'd0; - endcase - end - always@(fpu_div64_fState_S4$D_OUT) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 = - fpu_div64_fState_S4$D_OUT[65]; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 = - fpu_div64_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_div64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - 3'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[64:2] : - (fpu_div64_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 : - fpu_div64_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - fpu_div64_fState_S4$D_OUT[64:2]; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - 63'd0; - endcase - end - always@(fpu_div64_fState_S4$D_OUT) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 = - fpu_div64_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 = - fpu_div64_fState_S4$D_OUT[1:0] == 2'b11 && - fpu_div64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - fpu_div64_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - fpu_div64_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 : - fpu_div64_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 = - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 or - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - { CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 }; - 3'd1: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[65:2] : - { (fpu_div64_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_div64_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_div64_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_div64_fState_S4$D_OUT[65], - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 }; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - { CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 }; - endcase - end - always@(fpu_div64_fState_S3$D_OUT) - begin - case (fpu_div64_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174 = - fpu_div64_fState_S3$D_OUT[121]; - default: CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174 = - fpu_div64_fState_S3$D_OUT[124:122] == 3'd4 && - fpu_div64_fState_S3$D_OUT[121]; - endcase - end - always@(fpu_div64_fState_S3$D_OUT) - begin - case (fpu_div64_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'h7FF0000000000000; - 3'd2: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - fpu_div64_fState_S3$D_OUT[121] ? - 63'h7FEFFFFFFFFFFFFF : - 63'h7FF0000000000000; - 3'd3: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - fpu_div64_fState_S3$D_OUT[121] ? - 63'h7FF0000000000000 : - 63'h7FEFFFFFFFFFFFFF; - 3'd4: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'h7FEFFFFFFFFFFFFF; - default: CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'd0; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 or - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378) - begin - case (iFifo$D_OUT[3:0]) - 4'd0: - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330; - 4'd1: - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - iFifo$D_OUT[136] ? - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 : - { iFifo$D_OUT[136] || !iFifo$D_OUT[135], - iFifo$D_OUT[134:72] }; - default: CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1: - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 = - 64'h3FF0000000000000; - default: CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 = - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 = - fpu_sqr64_fState_S4$D_OUT[65]; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 = - fpu_sqr64_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_sqr64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - 3'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[64:2] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 : - fpu_sqr64_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - fpu_sqr64_fState_S4$D_OUT[64:2]; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - 63'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 = - fpu_sqr64_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 = - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b11 && - fpu_sqr64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - fpu_sqr64_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - fpu_sqr64_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 : - fpu_sqr64_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 = - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - { CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 }; - 3'd1: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[65:2] : - { (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_sqr64_fState_S4$D_OUT[65], - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 }; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - { CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - crg_done <= `BSV_ASSIGNMENT_DELAY 1'd0; - crg_done_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (crg_done$EN) crg_done <= `BSV_ASSIGNMENT_DELAY crg_done$D_IN; - if (crg_done_1$EN) - crg_done_1 <= `BSV_ASSIGNMENT_DELAY crg_done_1$D_IN; - if (rg_busy$EN) rg_busy <= `BSV_ASSIGNMENT_DELAY rg_busy$D_IN; - if (rg_busy_1$EN) rg_busy_1 <= `BSV_ASSIGNMENT_DELAY rg_busy_1$D_IN; - end - if (rg_b$EN) rg_b <= `BSV_ASSIGNMENT_DELAY rg_b$D_IN; - if (rg_d$EN) rg_d <= `BSV_ASSIGNMENT_DELAY rg_d$D_IN; - if (rg_index$EN) rg_index <= `BSV_ASSIGNMENT_DELAY rg_index$D_IN; - if (rg_index_1$EN) rg_index_1 <= `BSV_ASSIGNMENT_DELAY rg_index_1$D_IN; - if (rg_q$EN) rg_q <= `BSV_ASSIGNMENT_DELAY rg_q$D_IN; - if (rg_r$EN) rg_r <= `BSV_ASSIGNMENT_DELAY rg_r$D_IN; - if (rg_r_1$EN) rg_r_1 <= `BSV_ASSIGNMENT_DELAY rg_r_1$D_IN; - if (rg_res$EN) rg_res <= `BSV_ASSIGNMENT_DELAY rg_res$D_IN; - if (rg_s$EN) rg_s <= `BSV_ASSIGNMENT_DELAY rg_s$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - crg_done = 1'h0; - crg_done_1 = 1'h0; - rg_b = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_busy = 1'h0; - rg_busy_1 = 1'h0; - rg_d = 58'h2AAAAAAAAAAAAAA; - rg_index = 6'h2A; - rg_index_1 = 6'h2A; - rg_q = 58'h2AAAAAAAAAAAAAA; - rg_r = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_r_1 = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_res = 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_s = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (fpu_div64_fResult_S5$EMPTY_N && fpu_madd_fResult_S9$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 29: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResDiv] and\n [RL_getResMAdd] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fpu_div64_fResult_S5$EMPTY_N && fpu_sqr64_fResult_S5$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 29: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResDiv] and [RL_getResSqr]\n ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fpu_sqr64_fResult_S5$EMPTY_N && fpu_madd_fResult_S9$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 40: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResSqr] and\n [RL_getResMAdd] ) fired in the same clock cycle.\n"); - end - // synopsys translate_on -endmodule // mkFPU - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric.v deleted file mode 100644 index 771fc0dc..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric.v +++ /dev/null @@ -1,8149 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 = - fabric_cfg_verbosity > 4'd1 ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - $display("%0d: %m::AXI4_Fabric.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v deleted file mode 100644 index 2e372865..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v +++ /dev/null @@ -1,7465 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_2x3(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8650; - reg [31 : 0] v__h9025; - reg [31 : 0] v__h9400; - reg [31 : 0] v__h9845; - reg [31 : 0] v__h10214; - reg [31 : 0] v__h10583; - reg [31 : 0] v__h11872; - reg [31 : 0] v__h12325; - reg [31 : 0] v__h12702; - reg [31 : 0] v__h12994; - reg [31 : 0] v__h13286; - reg [31 : 0] v__h13589; - reg [31 : 0] v__h13855; - reg [31 : 0] v__h14121; - reg [31 : 0] v__h14385; - reg [31 : 0] v__h14611; - reg [31 : 0] v__h15040; - reg [31 : 0] v__h15396; - reg [31 : 0] v__h15752; - reg [31 : 0] v__h16169; - reg [31 : 0] v__h16501; - reg [31 : 0] v__h16833; - reg [31 : 0] v__h17849; - reg [31 : 0] v__h18100; - reg [31 : 0] v__h18475; - reg [31 : 0] v__h18716; - reg [31 : 0] v__h19091; - reg [31 : 0] v__h19332; - reg [31 : 0] v__h19694; - reg [31 : 0] v__h19945; - reg [31 : 0] v__h20275; - reg [31 : 0] v__h20516; - reg [31 : 0] v__h20846; - reg [31 : 0] v__h21087; - reg [31 : 0] v__h21600; - reg [31 : 0] v__h22001; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8644; - reg [31 : 0] v__h9019; - reg [31 : 0] v__h9394; - reg [31 : 0] v__h9839; - reg [31 : 0] v__h10208; - reg [31 : 0] v__h10577; - reg [31 : 0] v__h11866; - reg [31 : 0] v__h12319; - reg [31 : 0] v__h12696; - reg [31 : 0] v__h12988; - reg [31 : 0] v__h13280; - reg [31 : 0] v__h13583; - reg [31 : 0] v__h13849; - reg [31 : 0] v__h14115; - reg [31 : 0] v__h14379; - reg [31 : 0] v__h14605; - reg [31 : 0] v__h15034; - reg [31 : 0] v__h15390; - reg [31 : 0] v__h15746; - reg [31 : 0] v__h16163; - reg [31 : 0] v__h16495; - reg [31 : 0] v__h16827; - reg [31 : 0] v__h17843; - reg [31 : 0] v__h18094; - reg [31 : 0] v__h18469; - reg [31 : 0] v__h18710; - reg [31 : 0] v__h19085; - reg [31 : 0] v__h19326; - reg [31 : 0] v__h19688; - reg [31 : 0] v__h19939; - reg [31 : 0] v__h20269; - reg [31 : 0] v__h20510; - reg [31 : 0] v__h20840; - reg [31 : 0] v__h21081; - reg [31 : 0] v__h21594; - reg [31 : 0] v__h21995; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11777, - x__h12230, - x__h17986, - x__h18612, - x__h19228, - x__h21532, - x__h21933; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - x1_avValue_rresp__h17964, - x1_avValue_rresp__h18590, - x1_avValue_rresp__h19206; - wire _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156, - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371, - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411, - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540, - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - 8'd0 : - x__h17986 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - 8'd0 : - x__h18612 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - 8'd0 : - x__h19228 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? - 8'd0 : - x__h11777 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ? - 8'd0 : - x__h12230 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ? - 8'd0 : - x__h21532 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ? - 8'd0 : - x__h21933 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - x1_avValue_rresp__h17964 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - x1_avValue_rresp__h18590 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - x1_avValue_rresp__h19206 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h17964 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18590 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19206 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11777 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12230 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h17986 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h18612 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19228 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21532 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h21933 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8650 = $stime; - #0; - end - v__h8644 = v__h8650 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8644, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9025 = $stime; - #0; - end - v__h9019 = v__h9025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9019, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9400 = $stime; - #0; - end - v__h9394 = v__h9400 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9394, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9845 = $stime; - #0; - end - v__h9839 = v__h9845 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9839, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10214 = $stime; - #0; - end - v__h10208 = v__h10214 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10208, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10583 = $stime; - #0; - end - v__h10577 = v__h10583 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10577, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h11872 = $stime; - #0; - end - v__h11866 = v__h11872 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h11866, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12325 = $stime; - #0; - end - v__h12319 = v__h12325 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12319, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12702 = $stime; - #0; - end - v__h12696 = v__h12702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12696, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h12994 = $stime; - #0; - end - v__h12988 = v__h12994 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12988, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13286 = $stime; - #0; - end - v__h13280 = v__h13286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13280, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13589 = $stime; - #0; - end - v__h13583 = v__h13589 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13583, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13855 = $stime; - #0; - end - v__h13849 = v__h13855 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13849, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14121 = $stime; - #0; - end - v__h14115 = v__h14121 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14115, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14385 = $stime; - #0; - end - v__h14379 = v__h14385 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14379, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14611 = $stime; - #0; - end - v__h14605 = v__h14611 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14605, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15040 = $stime; - #0; - end - v__h15034 = v__h15040 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15034, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15396 = $stime; - #0; - end - v__h15390 = v__h15396 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15390, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15752 = $stime; - #0; - end - v__h15746 = v__h15752 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15746, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16169 = $stime; - #0; - end - v__h16163 = v__h16169 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16163, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16501 = $stime; - #0; - end - v__h16495 = v__h16501 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16495, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16833 = $stime; - #0; - end - v__h16827 = v__h16833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16827, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h17849 = $stime; - #0; - end - v__h17843 = v__h17849 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h17843, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18100 = $stime; - #0; - end - v__h18094 = v__h18100 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18094, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18475 = $stime; - #0; - end - v__h18469 = v__h18475 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18469, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h18716 = $stime; - #0; - end - v__h18710 = v__h18716 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18710, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19091 = $stime; - #0; - end - v__h19085 = v__h19091 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19085, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19332 = $stime; - #0; - end - v__h19326 = v__h19332 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19326, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h19694 = $stime; - #0; - end - v__h19688 = v__h19694 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19688, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19945 = $stime; - #0; - end - v__h19939 = v__h19945 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19939, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20275 = $stime; - #0; - end - v__h20269 = v__h20275 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20269, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20516 = $stime; - #0; - end - v__h20510 = v__h20516 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20510, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h20846 = $stime; - #0; - end - v__h20840 = v__h20846 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20840, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21087 = $stime; - #0; - end - v__h21081 = v__h21087 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21081, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21600 = $stime; - #0; - end - v__h21594 = v__h21600 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21594, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22001 = $stime; - #0; - end - v__h21995 = v__h22001 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21995, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_2x3 - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v deleted file mode 100644 index ac19188b..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v +++ /dev/null @@ -1,8145 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_AXI4(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_AXI4 - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v deleted file mode 100644 index a238e586..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v +++ /dev/null @@ -1,249 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 32 -// read_rs1_port2 O 32 -// read_rs2 O 32 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 32 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// Combinational paths from inputs to outputs: -// read_rs1_rs1 -> read_rs1 -// read_rs1_port2_rs1 -> read_rs1_port2 -// read_rs2_rs2 -> read_rs2 -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkGPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [31 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [31 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [31 : 0] read_rs2; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [31 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [31 : 0] read_rs1, read_rs1_port2, read_rs2; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [31 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 32'd0 : regfile$D_OUT_3 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = - (read_rs1_port2_rs1 == 5'd0) ? 32'd0 : regfile$D_OUT_2 ; - - // value method read_rs2 - assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 32'd0 : regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd32), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs2_rs2 ; - assign regfile$ADDR_2 = read_rs1_port2_rs1 ; - assign regfile$ADDR_3 = read_rs1_rs1 ; - assign regfile$ADDR_4 = 5'h0 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkGPR_RegFile - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v deleted file mode 100644 index f4d13fdd..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 64 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 32 -// put_args_y_is_signed I 1 -// put_args_y I 32 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_32(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [31 : 0] put_args_x; - input put_args_y_is_signed; - input [31 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [63 : 0] result_value; - - // signals for module outputs - wire [63 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [63 : 0] m_rg_x; - wire [63 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [63 : 0] m_rg_xy; - wire [63 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [31 : 0] m_rg_y; - wire [31 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [63 : 0] xy___1__h654; - wire [31 : 0] _theResult___fst__h491, - _theResult___fst__h494, - _theResult___fst__h536, - _theResult___fst__h539, - _theResult___snd_fst__h531; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 32'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h654 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 32'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h491 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h539 : - _theResult___snd_fst__h531 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[31] != put_args_y[31] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 = - put_args_x_is_signed ? - put_args_x[31] : - put_args_y_is_signed && put_args_y[31] ; - assign _theResult___fst__h491 = - put_args_x_is_signed ? _theResult___fst__h494 : put_args_x ; - assign _theResult___fst__h494 = put_args_x[31] ? -put_args_x : put_args_x ; - assign _theResult___fst__h536 = - put_args_y_is_signed ? _theResult___fst__h539 : put_args_y ; - assign _theResult___fst__h539 = put_args_y[31] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h531 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h536 ; - assign xy___1__h654 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 64'hAAAAAAAAAAAAAAAA; - m_rg_xy = 64'hAAAAAAAAAAAAAAAA; - m_rg_y = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_32 - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v deleted file mode 100644 index 0b513191..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 128 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 64 -// put_args_y_is_signed I 1 -// put_args_y I 64 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_64(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [63 : 0] put_args_x; - input put_args_y_is_signed; - input [63 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [127 : 0] result_value; - - // signals for module outputs - wire [127 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [127 : 0] m_rg_x; - wire [127 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [127 : 0] m_rg_xy; - wire [127 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [63 : 0] m_rg_y; - wire [63 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [127 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [127 : 0] xy___1__h648; - wire [63 : 0] _theResult___fst__h488, - _theResult___fst__h491, - _theResult___fst__h533, - _theResult___fst__h536, - _theResult___snd_fst__h528; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 64'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h648 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 64'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h488 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h536 : - _theResult___snd_fst__h528 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[63] != put_args_y[63] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 = - put_args_x_is_signed ? - put_args_x[63] : - put_args_y_is_signed && put_args_y[63] ; - assign _theResult___fst__h488 = - put_args_x_is_signed ? _theResult___fst__h491 : put_args_x ; - assign _theResult___fst__h491 = put_args_x[63] ? -put_args_x : put_args_x ; - assign _theResult___fst__h533 = - put_args_y_is_signed ? _theResult___fst__h536 : put_args_y ; - assign _theResult___fst__h536 = put_args_y[63] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h528 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h533 ; - assign xy___1__h648 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_y = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_64 - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v deleted file mode 100644 index 747914d6..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v +++ /dev/null @@ -1,7784 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// valid O 1 -// addr O 32 reg -// word64 O 64 -// st_amo_val O 64 -// exc O 1 -// exc_code O 4 reg -// RDY_server_flush_request_put O 1 reg -// RDY_server_flush_response_get O 1 -// RDY_tlb_flush O 1 const -// mem_master_awvalid O 1 -// mem_master_awid O 4 reg -// mem_master_awaddr O 64 reg -// mem_master_awlen O 8 reg -// mem_master_awsize O 3 reg -// mem_master_awburst O 2 reg -// mem_master_awlock O 1 reg -// mem_master_awcache O 4 reg -// mem_master_awprot O 3 reg -// mem_master_awqos O 4 reg -// mem_master_awregion O 4 reg -// mem_master_wvalid O 1 -// mem_master_wid O 4 reg -// mem_master_wdata O 64 reg -// mem_master_wstrb O 8 reg -// mem_master_wlast O 1 reg -// mem_master_bready O 1 -// mem_master_arvalid O 1 -// mem_master_arid O 4 reg -// mem_master_araddr O 64 reg -// mem_master_arlen O 8 reg -// mem_master_arsize O 3 reg -// mem_master_arburst O 2 reg -// mem_master_arlock O 1 reg -// mem_master_arcache O 4 reg -// mem_master_arprot O 3 reg -// mem_master_arqos O 4 reg -// mem_master_arregion O 4 reg -// mem_master_rready O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_op I 2 -// req_f3 I 3 -// req_amo_funct7 I 7 reg -// req_addr I 32 -// req_st_value I 64 -// req_priv I 2 reg -// req_sstatus_SUM I 1 reg -// req_mstatus_MXR I 1 reg -// req_satp I 32 reg -// mem_master_awready I 1 -// mem_master_wready I 1 -// mem_master_bvalid I 1 -// mem_master_bid I 4 reg -// mem_master_bresp I 2 reg -// mem_master_arready I 1 -// mem_master_rvalid I 1 -// mem_master_rid I 4 reg -// mem_master_rdata I 64 reg -// mem_master_rresp I 2 reg -// mem_master_rlast I 1 reg -// EN_set_verbosity I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// EN_server_flush_request_put I 1 -// EN_server_flush_response_get I 1 -// EN_tlb_flush I 1 -// -// Combinational paths from inputs to outputs: -// (mem_master_awready, mem_master_wready) -> valid -// (mem_master_awready, mem_master_wready) -> word64 -// (mem_master_awready, mem_master_wready) -> st_amo_val -// (mem_master_awready, mem_master_wready) -> mem_master_bready -// (mem_master_awready, -// mem_master_wready, -// mem_master_arready, -// EN_req) -> mem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMMU_Cache(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_op, - req_f3, - req_amo_funct7, - req_addr, - req_st_value, - req_priv, - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - EN_req, - - valid, - - addr, - - word64, - - st_amo_val, - - exc, - - exc_code, - - EN_server_flush_request_put, - RDY_server_flush_request_put, - - EN_server_flush_response_get, - RDY_server_flush_response_get, - - EN_tlb_flush, - RDY_tlb_flush, - - mem_master_awvalid, - - mem_master_awid, - - mem_master_awaddr, - - mem_master_awlen, - - mem_master_awsize, - - mem_master_awburst, - - mem_master_awlock, - - mem_master_awcache, - - mem_master_awprot, - - mem_master_awqos, - - mem_master_awregion, - - mem_master_awready, - - mem_master_wvalid, - - mem_master_wid, - - mem_master_wdata, - - mem_master_wstrb, - - mem_master_wlast, - - mem_master_wready, - - mem_master_bvalid, - mem_master_bid, - mem_master_bresp, - - mem_master_bready, - - mem_master_arvalid, - - mem_master_arid, - - mem_master_araddr, - - mem_master_arlen, - - mem_master_arsize, - - mem_master_arburst, - - mem_master_arlock, - - mem_master_arcache, - - mem_master_arprot, - - mem_master_arqos, - - mem_master_arregion, - - mem_master_arready, - - mem_master_rvalid, - mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast, - - mem_master_rready); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [1 : 0] req_op; - input [2 : 0] req_f3; - input [6 : 0] req_amo_funct7; - input [31 : 0] req_addr; - input [63 : 0] req_st_value; - input [1 : 0] req_priv; - input req_sstatus_SUM; - input req_mstatus_MXR; - input [31 : 0] req_satp; - input EN_req; - - // value method valid - output valid; - - // value method addr - output [31 : 0] addr; - - // value method word64 - output [63 : 0] word64; - - // value method st_amo_val - output [63 : 0] st_amo_val; - - // value method exc - output exc; - - // value method exc_code - output [3 : 0] exc_code; - - // action method server_flush_request_put - input EN_server_flush_request_put; - output RDY_server_flush_request_put; - - // action method server_flush_response_get - input EN_server_flush_response_get; - output RDY_server_flush_response_get; - - // action method tlb_flush - input EN_tlb_flush; - output RDY_tlb_flush; - - // value method mem_master_m_awvalid - output mem_master_awvalid; - - // value method mem_master_m_awid - output [3 : 0] mem_master_awid; - - // value method mem_master_m_awaddr - output [63 : 0] mem_master_awaddr; - - // value method mem_master_m_awlen - output [7 : 0] mem_master_awlen; - - // value method mem_master_m_awsize - output [2 : 0] mem_master_awsize; - - // value method mem_master_m_awburst - output [1 : 0] mem_master_awburst; - - // value method mem_master_m_awlock - output mem_master_awlock; - - // value method mem_master_m_awcache - output [3 : 0] mem_master_awcache; - - // value method mem_master_m_awprot - output [2 : 0] mem_master_awprot; - - // value method mem_master_m_awqos - output [3 : 0] mem_master_awqos; - - // value method mem_master_m_awregion - output [3 : 0] mem_master_awregion; - - // value method mem_master_m_awuser - - // action method mem_master_m_awready - input mem_master_awready; - - // value method mem_master_m_wvalid - output mem_master_wvalid; - - // value method mem_master_m_wid - output [3 : 0] mem_master_wid; - - // value method mem_master_m_wdata - output [63 : 0] mem_master_wdata; - - // value method mem_master_m_wstrb - output [7 : 0] mem_master_wstrb; - - // value method mem_master_m_wlast - output mem_master_wlast; - - // value method mem_master_m_wuser - - // action method mem_master_m_wready - input mem_master_wready; - - // action method mem_master_m_bvalid - input mem_master_bvalid; - input [3 : 0] mem_master_bid; - input [1 : 0] mem_master_bresp; - - // value method mem_master_m_bready - output mem_master_bready; - - // value method mem_master_m_arvalid - output mem_master_arvalid; - - // value method mem_master_m_arid - output [3 : 0] mem_master_arid; - - // value method mem_master_m_araddr - output [63 : 0] mem_master_araddr; - - // value method mem_master_m_arlen - output [7 : 0] mem_master_arlen; - - // value method mem_master_m_arsize - output [2 : 0] mem_master_arsize; - - // value method mem_master_m_arburst - output [1 : 0] mem_master_arburst; - - // value method mem_master_m_arlock - output mem_master_arlock; - - // value method mem_master_m_arcache - output [3 : 0] mem_master_arcache; - - // value method mem_master_m_arprot - output [2 : 0] mem_master_arprot; - - // value method mem_master_m_arqos - output [3 : 0] mem_master_arqos; - - // value method mem_master_m_arregion - output [3 : 0] mem_master_arregion; - - // value method mem_master_m_aruser - - // action method mem_master_m_arready - input mem_master_arready; - - // action method mem_master_m_rvalid - input mem_master_rvalid; - input [3 : 0] mem_master_rid; - input [63 : 0] mem_master_rdata; - input [1 : 0] mem_master_rresp; - input mem_master_rlast; - - // value method mem_master_m_rready - output mem_master_rready; - - // signals for module outputs - reg [63 : 0] word64; - wire [63 : 0] mem_master_araddr, - mem_master_awaddr, - mem_master_wdata, - st_amo_val; - wire [31 : 0] addr; - wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; - wire [3 : 0] exc_code, - mem_master_arcache, - mem_master_arid, - mem_master_arqos, - mem_master_arregion, - mem_master_awcache, - mem_master_awid, - mem_master_awqos, - mem_master_awregion, - mem_master_wid; - wire [2 : 0] mem_master_arprot, - mem_master_arsize, - mem_master_awprot, - mem_master_awsize; - wire [1 : 0] mem_master_arburst, mem_master_awburst; - wire RDY_server_flush_request_put, - RDY_server_flush_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_verbosity, - RDY_tlb_flush, - exc, - mem_master_arlock, - mem_master_arvalid, - mem_master_awlock, - mem_master_awvalid, - mem_master_bready, - mem_master_rready, - mem_master_wlast, - mem_master_wvalid, - valid; - - // inlined wires - reg [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1; - wire [10 : 0] crg_sb_to_load_delay$port0__write_1, - crg_sb_to_load_delay$port2__read; - wire [3 : 0] ctr_wr_rsps_pending_crg$port1__write_1, - ctr_wr_rsps_pending_crg$port2__read, - ctr_wr_rsps_pending_crg$port3__read; - wire crg_sb_to_load_delay$EN_port1__write, - ctr_wr_rsps_pending_crg$EN_port0__write, - ctr_wr_rsps_pending_crg$EN_port2__write, - dw_valid$whas, - master_xactor_crg_rd_addr_full$EN_port0__write, - master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port1__read, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port0__write, - master_xactor_crg_rd_data_full$EN_port1__write, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port1__read, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port0__write, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$EN_port2__write, - master_xactor_crg_wr_addr_full$port1__read, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port0__write, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$EN_port2__write, - master_xactor_crg_wr_data_full$port1__read, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read, - master_xactor_crg_wr_resp_full$EN_port0__write, - master_xactor_crg_wr_resp_full$EN_port2__write, - master_xactor_crg_wr_resp_full$port1__read, - master_xactor_crg_wr_resp_full$port2__read, - master_xactor_crg_wr_resp_full$port3__read; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_sb_to_load_delay - reg [10 : 0] crg_sb_to_load_delay; - wire [10 : 0] crg_sb_to_load_delay$D_IN; - wire crg_sb_to_load_delay$EN; - - // register ctr_wr_rsps_pending_crg - reg [3 : 0] ctr_wr_rsps_pending_crg; - wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN; - wire ctr_wr_rsps_pending_crg$EN; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - reg [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - reg [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [76 : 0] master_xactor_rg_wr_data; - reg [76 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - - // register rg_addr - reg [31 : 0] rg_addr; - wire [31 : 0] rg_addr$D_IN; - wire rg_addr$EN; - - // register rg_amo_funct7 - reg [6 : 0] rg_amo_funct7; - wire [6 : 0] rg_amo_funct7$D_IN; - wire rg_amo_funct7$EN; - - // register rg_cset_in_cache - reg [6 : 0] rg_cset_in_cache; - wire [6 : 0] rg_cset_in_cache$D_IN; - wire rg_cset_in_cache$EN; - - // register rg_error_during_refill - reg rg_error_during_refill; - wire rg_error_during_refill$D_IN, rg_error_during_refill$EN; - - // register rg_exc_code - reg [3 : 0] rg_exc_code; - reg [3 : 0] rg_exc_code$D_IN; - wire rg_exc_code$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_ld_val - reg [63 : 0] rg_ld_val; - reg [63 : 0] rg_ld_val$D_IN; - wire rg_ld_val$EN; - - // register rg_lower_word32 - reg [31 : 0] rg_lower_word32; - wire [31 : 0] rg_lower_word32$D_IN; - wire rg_lower_word32$EN; - - // register rg_lower_word32_full - reg rg_lower_word32_full; - wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN; - - // register rg_lrsc_pa - reg [33 : 0] rg_lrsc_pa; - wire [33 : 0] rg_lrsc_pa$D_IN; - wire rg_lrsc_pa$EN; - - // register rg_lrsc_valid - reg rg_lrsc_valid; - wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_op - reg [1 : 0] rg_op; - wire [1 : 0] rg_op$D_IN; - wire rg_op$EN; - - // register rg_pa - reg [33 : 0] rg_pa; - wire [33 : 0] rg_pa$D_IN; - wire rg_pa$EN; - - // register rg_priv - reg [1 : 0] rg_priv; - wire [1 : 0] rg_priv$D_IN; - wire rg_priv$EN; - - // register rg_pte_pa - reg [33 : 0] rg_pte_pa; - wire [33 : 0] rg_pte_pa$D_IN; - wire rg_pte_pa$EN; - - // register rg_satp - reg [31 : 0] rg_satp; - wire [31 : 0] rg_satp$D_IN; - wire rg_satp$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_st_amo_val - reg [63 : 0] rg_st_amo_val; - wire [63 : 0] rg_st_amo_val$D_IN; - wire rg_st_amo_val$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_word64_set_in_cache - reg [8 : 0] rg_word64_set_in_cache; - wire [8 : 0] rg_word64_set_in_cache$D_IN; - wire rg_word64_set_in_cache$EN; - - // ports of submodule f_pte_writebacks - wire [65 : 0] f_pte_writebacks$D_IN, f_pte_writebacks$D_OUT; - wire f_pte_writebacks$CLR, - f_pte_writebacks$DEQ, - f_pte_writebacks$EMPTY_N, - f_pte_writebacks$ENQ, - f_pte_writebacks$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule ram_state_and_ctag_cset - wire [22 : 0] ram_state_and_ctag_cset$DIA, - ram_state_and_ctag_cset$DIB, - ram_state_and_ctag_cset$DOB; - wire [6 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB; - wire ram_state_and_ctag_cset$ENA, - ram_state_and_ctag_cset$ENB, - ram_state_and_ctag_cset$WEA, - ram_state_and_ctag_cset$WEB; - - // ports of submodule ram_word64_set - reg [63 : 0] ram_word64_set$DIB; - reg [8 : 0] ram_word64_set$ADDRB; - wire [63 : 0] ram_word64_set$DIA, ram_word64_set$DOB; - wire [8 : 0] ram_word64_set$ADDRA; - wire ram_word64_set$ENA, - ram_word64_set$ENB, - ram_word64_set$WEA, - ram_word64_set$WEB; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - wire soc_map$m_is_mem_addr; - - // ports of submodule tlb - reg [31 : 0] tlb$insert_pte; - reg [1 : 0] tlb$insert_level; - wire [68 : 0] tlb$lookup; - wire [33 : 0] tlb$insert_pte_pa; - wire [19 : 0] tlb$insert_vpn, tlb$lookup_vpn; - wire [8 : 0] tlb$insert_asid, tlb$lookup_asid; - wire tlb$EN_flush, tlb$EN_insert, tlb$RDY_insert, tlb$RDY_lookup; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_ST_AMO_response, - CAN_FIRE_RL_rl_cache_refill_rsps_loop, - CAN_FIRE_RL_rl_discard_write_rsp, - CAN_FIRE_RL_rl_drive_exception_rsp, - CAN_FIRE_RL_rl_io_AMO_SC_req, - CAN_FIRE_RL_rl_io_AMO_op_req, - CAN_FIRE_RL_rl_io_AMO_read_rsp, - CAN_FIRE_RL_rl_io_read_req, - CAN_FIRE_RL_rl_io_read_rsp, - CAN_FIRE_RL_rl_io_write_req, - CAN_FIRE_RL_rl_maintain_io_read_rsp, - CAN_FIRE_RL_rl_probe_and_immed_rsp, - CAN_FIRE_RL_rl_ptw_level_0, - CAN_FIRE_RL_rl_ptw_level_1, - CAN_FIRE_RL_rl_rereq, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_shift_sb_to_load_delay, - CAN_FIRE_RL_rl_start_cache_refill, - CAN_FIRE_RL_rl_start_reset, - CAN_FIRE_RL_rl_start_tlb_refill, - CAN_FIRE_RL_rl_writeback_updated_PTE, - CAN_FIRE_mem_master_m_arready, - CAN_FIRE_mem_master_m_awready, - CAN_FIRE_mem_master_m_bvalid, - CAN_FIRE_mem_master_m_rvalid, - CAN_FIRE_mem_master_m_wready, - CAN_FIRE_req, - CAN_FIRE_server_flush_request_put, - CAN_FIRE_server_flush_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_verbosity, - CAN_FIRE_tlb_flush, - WILL_FIRE_RL_rl_ST_AMO_response, - WILL_FIRE_RL_rl_cache_refill_rsps_loop, - WILL_FIRE_RL_rl_discard_write_rsp, - WILL_FIRE_RL_rl_drive_exception_rsp, - WILL_FIRE_RL_rl_io_AMO_SC_req, - WILL_FIRE_RL_rl_io_AMO_op_req, - WILL_FIRE_RL_rl_io_AMO_read_rsp, - WILL_FIRE_RL_rl_io_read_req, - WILL_FIRE_RL_rl_io_read_rsp, - WILL_FIRE_RL_rl_io_write_req, - WILL_FIRE_RL_rl_maintain_io_read_rsp, - WILL_FIRE_RL_rl_probe_and_immed_rsp, - WILL_FIRE_RL_rl_ptw_level_0, - WILL_FIRE_RL_rl_ptw_level_1, - WILL_FIRE_RL_rl_rereq, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_shift_sb_to_load_delay, - WILL_FIRE_RL_rl_start_cache_refill, - WILL_FIRE_RL_rl_start_reset, - WILL_FIRE_RL_rl_start_tlb_refill, - WILL_FIRE_RL_rl_writeback_updated_PTE, - WILL_FIRE_mem_master_m_arready, - WILL_FIRE_mem_master_m_awready, - WILL_FIRE_mem_master_m_bvalid, - WILL_FIRE_mem_master_m_rvalid, - WILL_FIRE_mem_master_m_wready, - WILL_FIRE_req, - WILL_FIRE_server_flush_request_put, - WILL_FIRE_server_flush_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_verbosity, - WILL_FIRE_tlb_flush; - - // inputs to muxes for submodule ports - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2, - MUX_master_xactor_rg_rd_addr$write_1__VAL_3, - MUX_master_xactor_rg_rd_addr$write_1__VAL_4, - MUX_master_xactor_rg_wr_addr$write_1__VAL_1, - MUX_master_xactor_rg_wr_addr$write_1__VAL_2, - MUX_master_xactor_rg_wr_addr$write_1__VAL_4; - wire [76 : 0] MUX_master_xactor_rg_wr_data$write_1__VAL_1, - MUX_master_xactor_rg_wr_data$write_1__VAL_2, - MUX_master_xactor_rg_wr_data$write_1__VAL_3, - MUX_master_xactor_rg_wr_data$write_1__VAL_4; - wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3, - MUX_ram_word64_set$a_put_3__VAL_2, - MUX_rg_ld_val$write_1__VAL_2; - wire [33 : 0] MUX_rg_pa$write_1__VAL_1; - wire [22 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1; - wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2, - MUX_ram_word64_set$b_put_2__VAL_4; - wire [6 : 0] MUX_rg_cset_in_cache$write_1__VAL_1; - wire [3 : 0] MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_5, - MUX_rg_state$write_1__VAL_10, - MUX_rg_state$write_1__VAL_11, - MUX_rg_state$write_1__VAL_12, - MUX_rg_state$write_1__VAL_13, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_6; - wire MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2, - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_1, - MUX_dw_output_ld_val$wset_1__SEL_2, - MUX_dw_output_ld_val$wset_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_4, - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1, - MUX_master_xactor_rg_rd_addr$write_1__SEL_2, - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1, - MUX_ram_word64_set$a_put_1__SEL_1, - MUX_ram_word64_set$b_put_1__SEL_2, - MUX_rg_error_during_refill$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_2, - MUX_rg_exc_code$write_1__SEL_3, - MUX_rg_exc_code$write_1__SEL_5, - MUX_rg_exc_code$write_1__SEL_6, - MUX_rg_exc_code$write_1__SEL_7, - MUX_rg_ld_val$write_1__SEL_2, - MUX_rg_lrsc_valid$write_1__SEL_2, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_13, - MUX_rg_state$write_1__SEL_17, - MUX_rg_state$write_1__SEL_3, - MUX_tlb$insert_1__SEL_1, - MUX_tlb$insert_1__SEL_2, - MUX_tlb$insert_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4748; - reg [31 : 0] v__h4849; - reg [31 : 0] v__h29722; - reg [31 : 0] v__h30620; - reg [31 : 0] v__h4385; - reg [31 : 0] v__h5300; - reg [31 : 0] v__h14916; - reg [31 : 0] v__h19135; - reg [31 : 0] v__h18560; - reg [31 : 0] v__h22571; - reg [31 : 0] v__h24184; - reg [31 : 0] v__h23942; - reg [31 : 0] v__h24605; - reg [31 : 0] v__h24493; - reg [31 : 0] v__h24113; - reg [31 : 0] v__h25145; - reg [31 : 0] v__h25216; - reg [31 : 0] v__h25298; - reg [31 : 0] v__h25074; - reg [31 : 0] v__h26206; - reg [31 : 0] v__h26428; - reg [31 : 0] v__h28410; - reg [31 : 0] v__h29510; - reg [31 : 0] v__h29617; - reg [31 : 0] v__h29802; - reg [31 : 0] v__h30324; - reg [31 : 0] v__h30738; - reg [31 : 0] v__h3751; - reg [31 : 0] v__h31056; - reg [31 : 0] v__h31231; - reg [31 : 0] v__h33844; - reg [31 : 0] v__h34096; - reg [31 : 0] v__h31327; - reg [31 : 0] v__h23206; - reg [31 : 0] v__h25423; - reg [31 : 0] v__h28036; - reg [31 : 0] v__h35065; - reg [31 : 0] v__h36219; - reg [31 : 0] v__h34716; - reg [31 : 0] v__h34677; - reg [31 : 0] v__h3745; - reg [31 : 0] v__h4379; - reg [31 : 0] v__h4742; - reg [31 : 0] v__h4843; - reg [31 : 0] v__h5294; - reg [31 : 0] v__h14910; - reg [31 : 0] v__h18554; - reg [31 : 0] v__h19129; - reg [31 : 0] v__h22565; - reg [31 : 0] v__h23200; - reg [31 : 0] v__h23936; - reg [31 : 0] v__h24107; - reg [31 : 0] v__h24178; - reg [31 : 0] v__h24487; - reg [31 : 0] v__h24599; - reg [31 : 0] v__h25068; - reg [31 : 0] v__h25139; - reg [31 : 0] v__h25210; - reg [31 : 0] v__h25292; - reg [31 : 0] v__h25417; - reg [31 : 0] v__h26200; - reg [31 : 0] v__h26422; - reg [31 : 0] v__h28030; - reg [31 : 0] v__h28404; - reg [31 : 0] v__h29504; - reg [31 : 0] v__h29611; - reg [31 : 0] v__h29716; - reg [31 : 0] v__h29796; - reg [31 : 0] v__h30318; - reg [31 : 0] v__h30614; - reg [31 : 0] v__h30732; - reg [31 : 0] v__h31050; - reg [31 : 0] v__h31225; - reg [31 : 0] v__h31321; - reg [31 : 0] v__h33838; - reg [31 : 0] v__h34090; - reg [31 : 0] v__h34671; - reg [31 : 0] v__h34710; - reg [31 : 0] v__h35059; - reg [31 : 0] v__h36213; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50, - CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30, - CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34, - CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35, - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33, - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752, - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627, - _theResult_____2__h19664, - _theResult_____2__h31649, - ld_val__h28519, - mem_req_wr_data_wdata__h18931, - mem_req_wr_data_wdata__h22367, - mem_req_wr_data_wdata__h30120, - mem_req_wr_data_wdata__h31624, - new_ld_val__h31357, - new_value__h17651, - new_value__h7622, - w1__h19656, - w1__h31637, - w1__h31641; - reg [33 : 0] _theResult___fst__h6689; - reg [7 : 0] mem_req_wr_data_wstrb__h18932, mem_req_wr_data_wstrb__h31625; - reg [2 : 0] value__h30942, value__h33968; - reg CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d285, - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d290, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211, - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245, - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297; - wire [63 : 0] IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d574, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560, - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691, - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d784, - _theResult___snd_fst__h18939, - _theResult___snd_fst__h22375, - _theResult___snd_fst__h30128, - _theResult___snd_fst__h31632, - addr__h7263, - cline_fabric_addr__h25476, - lev_0_pte_pa_w64_fa__h24218, - lev_1_pte_pa_w64_fa__h23261, - mem_req_wr_addr_awaddr__h31419, - mem_req_wr_addr_awaddr__h3403, - mem_req_wr_data_wdata__h3595, - new_st_val__h19386, - new_st_val__h19668, - new_st_val__h19759, - new_st_val__h20739, - new_st_val__h20743, - new_st_val__h20747, - new_st_val__h20751, - new_st_val__h20756, - new_st_val__h20762, - new_st_val__h20767, - new_st_val__h31653, - new_st_val__h31744, - new_st_val__h33604, - new_st_val__h33608, - new_st_val__h33612, - new_st_val__h33616, - new_st_val__h33621, - new_st_val__h33627, - new_st_val__h33632, - result__h14033, - result__h14061, - result__h14089, - result__h14117, - result__h14145, - result__h14173, - result__h14201, - result__h14246, - result__h14274, - result__h14302, - result__h14330, - result__h14358, - result__h14386, - result__h14414, - result__h14442, - result__h14487, - result__h14515, - result__h14543, - result__h14571, - result__h14612, - result__h14640, - result__h14668, - result__h14696, - result__h14737, - result__h14765, - result__h14804, - result__h14832, - result__h28579, - result__h28609, - result__h28636, - result__h28663, - result__h28690, - result__h28717, - result__h28744, - result__h28771, - result__h28815, - result__h28842, - result__h28869, - result__h28896, - result__h28923, - result__h28950, - result__h28977, - result__h29004, - result__h29048, - result__h29075, - result__h29102, - result__h29129, - result__h29169, - result__h29196, - result__h29223, - result__h29250, - result__h29290, - result__h29317, - result__h29355, - result__h29382, - result__h31832, - result__h32740, - result__h32768, - result__h32796, - result__h32824, - result__h32852, - result__h32880, - result__h32908, - result__h32953, - result__h32981, - result__h33009, - result__h33037, - result__h33065, - result__h33093, - result__h33121, - result__h33149, - result__h33194, - result__h33222, - result__h33250, - result__h33278, - result__h33319, - result__h33347, - result__h33375, - result__h33403, - result__h33444, - result__h33472, - result__h33511, - result__h33539, - result__h7677, - st_val__h31369, - st_val__h3324, - w1___1__h19727, - w1___1__h31712, - w2___1__h31713, - w2__h31643, - word64__h7440, - x__h15303, - y__h7713; - wire [33 : 0] _theResult___fst__h6315, - _theResult___fst__h6387, - cline_addr__h25475, - lev_0_PTN_pa__h24214, - lev_0_pte_pa__h24216, - lev_0_pte_pa_w64__h24217, - lev_1_pte_pa__h23259, - lev_1_pte_pa_w64__h23260, - pa___1__h6695, - pa___1__h6744, - pa__h6215, - satp_pa__h2468, - vpn_0_pa__h24215, - vpn_1_pa__h23258, - x1_avValue_pa__h6227; - wire [31 : 0] _theResult____h23570, - _theResult___snd_fst__h6317, - _theResult___snd_fst__h6389, - _theResult___snd_fst__h6827, - ld_val8519_BITS_31_TO_0__q38, - ld_val8519_BITS_63_TO_32__q45, - master_xactor_rg_rd_data_BITS_34_TO_3__q3, - master_xactor_rg_rd_data_BITS_66_TO_35__q10, - new_value622_BITS_31_TO_0__q31, - pte___1__h6876, - pte___1__h6904, - pte___2__h6687, - rg_st_amo_val_BITS_31_TO_0__q32, - w11637_BITS_31_TO_0__q51, - word64440_BITS_31_TO_0__q17, - word64440_BITS_63_TO_32__q24, - x1_avValue_pte__h6230; - wire [15 : 0] ld_val8519_BITS_15_TO_0__q37, - ld_val8519_BITS_31_TO_16__q41, - ld_val8519_BITS_47_TO_32__q44, - ld_val8519_BITS_63_TO_48__q48, - master_xactor_rg_rd_data_BITS_18_TO_3__q2, - master_xactor_rg_rd_data_BITS_34_TO_19__q6, - master_xactor_rg_rd_data_BITS_50_TO_35__q9, - master_xactor_rg_rd_data_BITS_66_TO_51__q13, - word64440_BITS_15_TO_0__q16, - word64440_BITS_31_TO_16__q20, - word64440_BITS_47_TO_32__q23, - word64440_BITS_63_TO_48__q27; - wire [7 : 0] ld_val8519_BITS_15_TO_8__q39, - ld_val8519_BITS_23_TO_16__q40, - ld_val8519_BITS_31_TO_24__q42, - ld_val8519_BITS_39_TO_32__q43, - ld_val8519_BITS_47_TO_40__q46, - ld_val8519_BITS_55_TO_48__q47, - ld_val8519_BITS_63_TO_56__q49, - ld_val8519_BITS_7_TO_0__q36, - master_xactor_rg_rd_data_BITS_10_TO_3__q1, - master_xactor_rg_rd_data_BITS_18_TO_11__q4, - master_xactor_rg_rd_data_BITS_26_TO_19__q5, - master_xactor_rg_rd_data_BITS_34_TO_27__q7, - master_xactor_rg_rd_data_BITS_42_TO_35__q8, - master_xactor_rg_rd_data_BITS_50_TO_43__q11, - master_xactor_rg_rd_data_BITS_58_TO_51__q12, - master_xactor_rg_rd_data_BITS_66_TO_59__q14, - mem_req_wr_data_wstrb__h3596, - strobe64__h18865, - strobe64__h18867, - strobe64__h18869, - strobe64__h31558, - strobe64__h31560, - strobe64__h31562, - word64440_BITS_15_TO_8__q18, - word64440_BITS_23_TO_16__q19, - word64440_BITS_31_TO_24__q21, - word64440_BITS_39_TO_32__q22, - word64440_BITS_47_TO_40__q25, - word64440_BITS_55_TO_48__q26, - word64440_BITS_63_TO_56__q28, - word64440_BITS_7_TO_0__q15; - wire [5 : 0] shift_bits__h18732, shift_bits__h31425, shift_bits__h3414; - wire [3 : 0] IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d396, - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d395, - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d398, - access_exc_code__h3148, - b__h23160, - exc_code___1__h6589, - x1_avValue_exc_code__h6228; - wire IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d293, - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217, - IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d305, - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d304, - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432, - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d284, - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d289, - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d292, - NOT_IF_rg_pte_pa_98_BIT_2_99_THEN_master_xacto_ETC___d926, - NOT_cfg_verbosity_read__5_ULE_2_014___d1015, - NOT_cfg_verbosity_read__5_ULT_2_02___d403, - NOT_dmem_not_imem_07_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d338, - NOT_dmem_not_imem_07_OR_NOT_rg_op_2_EQ_0_3_4_A_ETC___d114, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d621, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d634, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d761, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d795, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d813, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d852, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d857, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d863, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d871, - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d875, - NOT_master_xactor_rg_rd_data_94_BITS_2_TO_1_95_ETC___d919, - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199, - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d434, - NOT_req_f3_BITS_1_TO_0_344_EQ_0b0_345_346_AND__ETC___d1365, - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_7__ETC___d294, - NOT_rg_op_2_EQ_0_3_4_AND_NOT_rg_op_2_EQ_2_5_6__ETC___d389, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d443, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d631, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d758, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d850, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d855, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d861, - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d869, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d629, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d756, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d816, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d822, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d828, - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d834, - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d345, - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d368, - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d406, - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d580, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d148, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d307, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d365, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d417, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d418, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d425, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d428, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d449, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d455, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d456, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d588, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d594, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d601, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d607, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d613, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d623, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d636, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d763, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d768, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d797, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d803, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d809, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d815, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d820, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d826, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d832, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d838, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d839, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d846, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d847, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d865, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873, - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d877, - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129, - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d145, - cfg_verbosity_read__5_ULE_1___d26, - dmem_not_imem_AND_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_ETC___d340, - dmem_not_imem_OR_NOT_rg_op_2_EQ_0_3_4_AND_NOT__ETC___d106, - lrsc_result__h15293, - master_xactor_crg_rd_data_full_port1__read__93_ETC___d1176, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d958, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d962, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d968, - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d994, - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178, - ram_state_and_ctag_cset_b_read__73_BIT_22_74_A_ETC___d435, - req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374, - rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d610, - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d384, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d421, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d446, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d450, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d585, - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d604, - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d444, - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d632, - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d759, - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d764, - rg_op_2_EQ_2_5_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d248, - rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123, - rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d136, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d309, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d353, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d392, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d393, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d411, - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d414, - rg_priv_6_ULE_0b1___d67, - rg_state_0_EQ_12_043_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d1045, - rg_state_0_EQ_3_12_AND_NOT_rg_op_2_EQ_0_3_4_AN_ETC___d316, - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112, - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d347, - y__h6515; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method addr - assign addr = rg_addr ; - - // value method word64 - always@(MUX_dw_output_ld_val$wset_1__SEL_1 or - ld_val__h28519 or - MUX_dw_output_ld_val$wset_1__SEL_2 or - new_ld_val__h31357 or - MUX_dw_output_ld_val$wset_1__SEL_3 or - MUX_dw_output_ld_val$wset_1__VAL_3 or - MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h28519; - MUX_dw_output_ld_val$wset_1__SEL_2: word64 = new_ld_val__h31357; - MUX_dw_output_ld_val$wset_1__SEL_3: - word64 = MUX_dw_output_ld_val$wset_1__VAL_3; - MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val; - default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // value method st_amo_val - assign st_amo_val = - MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ; - - // value method exc - assign exc = rg_state == 4'd4 ; - - // value method exc_code - assign exc_code = rg_exc_code ; - - // action method server_flush_request_put - assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; - - // action method server_flush_response_get - assign RDY_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; - - // action method tlb_flush - assign RDY_tlb_flush = 1'd1 ; - assign CAN_FIRE_tlb_flush = 1'd1 ; - assign WILL_FIRE_tlb_flush = EN_tlb_flush ; - - // value method mem_master_m_awvalid - assign mem_master_awvalid = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - - // value method mem_master_m_awid - assign mem_master_awid = master_xactor_rg_wr_addr[96:93] ; - - // value method mem_master_m_awaddr - assign mem_master_awaddr = master_xactor_rg_wr_addr[92:29] ; - - // value method mem_master_m_awlen - assign mem_master_awlen = master_xactor_rg_wr_addr[28:21] ; - - // value method mem_master_m_awsize - assign mem_master_awsize = master_xactor_rg_wr_addr[20:18] ; - - // value method mem_master_m_awburst - assign mem_master_awburst = master_xactor_rg_wr_addr[17:16] ; - - // value method mem_master_m_awlock - assign mem_master_awlock = master_xactor_rg_wr_addr[15] ; - - // value method mem_master_m_awcache - assign mem_master_awcache = master_xactor_rg_wr_addr[14:11] ; - - // value method mem_master_m_awprot - assign mem_master_awprot = master_xactor_rg_wr_addr[10:8] ; - - // value method mem_master_m_awqos - assign mem_master_awqos = master_xactor_rg_wr_addr[7:4] ; - - // value method mem_master_m_awregion - assign mem_master_awregion = master_xactor_rg_wr_addr[3:0] ; - - // action method mem_master_m_awready - assign CAN_FIRE_mem_master_m_awready = 1'd1 ; - assign WILL_FIRE_mem_master_m_awready = 1'd1 ; - - // value method mem_master_m_wvalid - assign mem_master_wvalid = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - - // value method mem_master_m_wid - assign mem_master_wid = master_xactor_rg_wr_data[76:73] ; - - // value method mem_master_m_wdata - assign mem_master_wdata = master_xactor_rg_wr_data[72:9] ; - - // value method mem_master_m_wstrb - assign mem_master_wstrb = master_xactor_rg_wr_data[8:1] ; - - // value method mem_master_m_wlast - assign mem_master_wlast = master_xactor_rg_wr_data[0] ; - - // action method mem_master_m_wready - assign CAN_FIRE_mem_master_m_wready = 1'd1 ; - assign WILL_FIRE_mem_master_m_wready = 1'd1 ; - - // action method mem_master_m_bvalid - assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ; - - // value method mem_master_m_bready - assign mem_master_bready = !master_xactor_crg_wr_resp_full$port2__read ; - - // value method mem_master_m_arvalid - assign mem_master_arvalid = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - - // value method mem_master_m_arid - assign mem_master_arid = master_xactor_rg_rd_addr[96:93] ; - - // value method mem_master_m_araddr - assign mem_master_araddr = master_xactor_rg_rd_addr[92:29] ; - - // value method mem_master_m_arlen - assign mem_master_arlen = master_xactor_rg_rd_addr[28:21] ; - - // value method mem_master_m_arsize - assign mem_master_arsize = master_xactor_rg_rd_addr[20:18] ; - - // value method mem_master_m_arburst - assign mem_master_arburst = master_xactor_rg_rd_addr[17:16] ; - - // value method mem_master_m_arlock - assign mem_master_arlock = master_xactor_rg_rd_addr[15] ; - - // value method mem_master_m_arcache - assign mem_master_arcache = master_xactor_rg_rd_addr[14:11] ; - - // value method mem_master_m_arprot - assign mem_master_arprot = master_xactor_rg_rd_addr[10:8] ; - - // value method mem_master_m_arqos - assign mem_master_arqos = master_xactor_rg_rd_addr[7:4] ; - - // value method mem_master_m_arregion - assign mem_master_arregion = master_xactor_rg_rd_addr[3:0] ; - - // action method mem_master_m_arready - assign CAN_FIRE_mem_master_m_arready = 1'd1 ; - assign WILL_FIRE_mem_master_m_arready = 1'd1 ; - - // action method mem_master_m_rvalid - assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ; - - // value method mem_master_m_rready - assign mem_master_rready = !master_xactor_crg_rd_data_full$port2__read ; - - // submodule f_pte_writebacks - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_pte_writebacks(.RST(RST_N), - .CLK(CLK), - .D_IN(f_pte_writebacks$D_IN), - .ENQ(f_pte_writebacks$ENQ), - .DEQ(f_pte_writebacks$DEQ), - .CLR(f_pte_writebacks$CLR), - .D_OUT(f_pte_writebacks$D_OUT), - .FULL_N(f_pte_writebacks$FULL_N), - .EMPTY_N(f_pte_writebacks$EMPTY_N)); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule ram_state_and_ctag_cset - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd7), - .DATA_WIDTH(32'd23), - .MEMSIZE(8'd128)) ram_state_and_ctag_cset(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_state_and_ctag_cset$ADDRA), - .ADDRB(ram_state_and_ctag_cset$ADDRB), - .DIA(ram_state_and_ctag_cset$DIA), - .DIB(ram_state_and_ctag_cset$DIB), - .WEA(ram_state_and_ctag_cset$WEA), - .WEB(ram_state_and_ctag_cset$WEB), - .ENA(ram_state_and_ctag_cset$ENA), - .ENB(ram_state_and_ctag_cset$ENB), - .DOA(), - .DOB(ram_state_and_ctag_cset$DOB)); - - // submodule ram_word64_set - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd9), - .DATA_WIDTH(32'd64), - .MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_word64_set$ADDRA), - .ADDRB(ram_word64_set$ADDRB), - .DIA(ram_word64_set$DIA), - .DIB(ram_word64_set$DIB), - .WEA(ram_word64_set$WEA), - .WEB(ram_word64_set$WEB), - .ENA(ram_word64_set$ENA), - .ENB(ram_word64_set$ENB), - .DOA(), - .DOB(ram_word64_set$DOB)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(soc_map$m_is_mem_addr), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule tlb - mkTLB #(.dmem_not_imem(dmem_not_imem)) tlb(.CLK(CLK), - .RST_N(RST_N), - .insert_asid(tlb$insert_asid), - .insert_level(tlb$insert_level), - .insert_pte(tlb$insert_pte), - .insert_pte_pa(tlb$insert_pte_pa), - .insert_vpn(tlb$insert_vpn), - .lookup_asid(tlb$lookup_asid), - .lookup_vpn(tlb$lookup_vpn), - .EN_flush(tlb$EN_flush), - .EN_insert(tlb$EN_insert), - .RDY_flush(), - .lookup(tlb$lookup), - .RDY_lookup(tlb$RDY_lookup), - .RDY_insert(tlb$RDY_insert)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = WILL_FIRE_RL_rl_reset ; - assign WILL_FIRE_RL_rl_reset = - (rg_cset_in_cache != 7'd127 || - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) && - rg_state == 4'd1 ; - - // rule RL_rl_shift_sb_to_load_delay - assign CAN_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - assign WILL_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - - // rule RL_rl_rereq - assign CAN_FIRE_RL_rl_rereq = rg_state == 4'd10 ; - assign WILL_FIRE_RL_rl_rereq = - CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ; - - // rule RL_rl_ST_AMO_response - assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 4'd11 ; - assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ; - - // rule RL_rl_maintain_io_read_rsp - assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 4'd14 ; - assign WILL_FIRE_RL_rl_maintain_io_read_rsp = - CAN_FIRE_RL_rl_maintain_io_read_rsp ; - - // rule RL_rl_io_AMO_SC_req - assign CAN_FIRE_RL_rl_io_AMO_SC_req = - rg_state == 4'd12 && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_SC_req = - CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_drive_exception_rsp - assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ; - assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ; - - // rule RL_rl_start_reset - assign CAN_FIRE_RL_rl_start_reset = - f_reset_reqs$EMPTY_N && rg_state != 4'd1 ; - assign WILL_FIRE_RL_rl_start_reset = CAN_FIRE_RL_rl_start_reset ; - - // rule RL_rl_probe_and_immed_rsp - assign CAN_FIRE_RL_rl_probe_and_immed_rsp = - (cfg_verbosity_read__5_ULE_1___d26 || tlb$RDY_lookup) && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$RDY_lookup) && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d309 && - rg_state_0_EQ_3_12_AND_NOT_rg_op_2_EQ_0_3_4_AN_ETC___d316 ; - assign WILL_FIRE_RL_rl_probe_and_immed_rsp = - CAN_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_ptw_level_1 - assign CAN_FIRE_RL_rl_ptw_level_1 = - master_xactor_crg_rd_data_full$port1__read && - NOT_master_xactor_rg_rd_data_94_BITS_2_TO_1_95_ETC___d919 && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_ptw_level_1 = - CAN_FIRE_RL_rl_ptw_level_1 && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_ptw_level_0 - assign CAN_FIRE_RL_rl_ptw_level_0 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - !_theResult____h23570[3] && !_theResult____h23570[1] || - tlb$RDY_insert) && - rg_state == 4'd7 ; - assign WILL_FIRE_RL_rl_ptw_level_0 = - CAN_FIRE_RL_rl_ptw_level_0 && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_cache_refill_rsps_loop - assign CAN_FIRE_RL_rl_cache_refill_rsps_loop = - master_xactor_crg_rd_data_full$port1__read && rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_cache_refill_rsps_loop = - CAN_FIRE_RL_rl_cache_refill_rsps_loop && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_rsp - assign CAN_FIRE_RL_rl_io_read_rsp = - master_xactor_crg_rd_data_full$port1__read && rg_state == 4'd13 ; - assign WILL_FIRE_RL_rl_io_read_rsp = - CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_write_req - assign CAN_FIRE_RL_rl_io_write_req = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - rg_state == 4'd12 && - rg_op == 2'd1 ; - assign WILL_FIRE_RL_rl_io_write_req = - CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_op_req - assign CAN_FIRE_RL_rl_io_AMO_op_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 4'd12 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] != 5'b00010 && - rg_amo_funct7[6:2] != 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_op_req = - CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_writeback_updated_PTE - assign CAN_FIRE_RL_rl_writeback_updated_PTE = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - f_pte_writebacks$EMPTY_N ; - assign WILL_FIRE_RL_rl_writeback_updated_PTE = - CAN_FIRE_RL_rl_writeback_updated_PTE && - !WILL_FIRE_RL_rl_io_AMO_read_rsp && - !WILL_FIRE_RL_rl_io_write_req && - !WILL_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_read_rsp - assign CAN_FIRE_RL_rl_io_AMO_read_rsp = - master_xactor_crg_rd_data_full_port1__read__93_ETC___d1176 && - rg_state == 4'd15 ; - assign WILL_FIRE_RL_rl_io_AMO_read_rsp = - CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_tlb_refill - assign CAN_FIRE_RL_rl_start_tlb_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 4'd5 && - b__h23160 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_tlb_refill = - CAN_FIRE_RL_rl_start_tlb_refill && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_cache_refill - assign CAN_FIRE_RL_rl_start_cache_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 4'd8 && - b__h23160 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_cache_refill = - CAN_FIRE_RL_rl_start_cache_refill && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_req - assign CAN_FIRE_RL_rl_io_read_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state_0_EQ_12_043_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d1045 ; - assign WILL_FIRE_RL_rl_io_read_req = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_discard_write_rsp - assign CAN_FIRE_RL_rl_discard_write_rsp = - b__h23160 != 4'd0 && master_xactor_crg_wr_resp_full$port1__read ; - assign WILL_FIRE_RL_rl_discard_write_rsp = - CAN_FIRE_RL_rl_discard_write_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // inputs to muxes for submodule ports - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3 = - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign MUX_dw_output_ld_val$wset_1__SEL_1 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_dw_output_ld_val$wset_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_dw_output_ld_val$wset_1__SEL_3 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d456 ; - assign MUX_dw_output_ld_val$wset_1__SEL_4 = - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - !_theResult____h23570[2] && - !_theResult____h23570[3] && - !_theResult____h23570[1] ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ; - assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 = - EN_req && - req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374 ; - assign MUX_ram_word64_set$a_put_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ram_word64_set$b_put_1__SEL_2 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 ; - assign MUX_rg_error_during_refill$write_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_1 = - EN_req && - NOT_req_f3_BITS_1_TO_0_344_EQ_0b0_345_346_AND__ETC___d1365 ; - assign MUX_rg_exc_code$write_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_3 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_5 = - WILL_FIRE_RL_rl_ptw_level_0 && - (!_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - !_theResult____h23570[3] && !_theResult____h23570[1] || - master_xactor_rg_rd_data[2:1] != 2'b0) ; - assign MUX_rg_exc_code$write_1__SEL_6 = - WILL_FIRE_RL_rl_ptw_level_1 && - NOT_IF_rg_pte_pa_98_BIT_2_99_THEN_master_xacto_ETC___d926 ; - assign MUX_rg_exc_code$write_1__SEL_7 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 ; - assign MUX_rg_ld_val$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d623 ; - assign MUX_rg_lrsc_valid$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d449 ; - assign MUX_rg_state$write_1__SEL_3 = - CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ; - assign MUX_rg_state$write_1__SEL_10 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 ; - assign MUX_rg_state$write_1__SEL_13 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d393 ; - assign MUX_rg_state$write_1__SEL_17 = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign MUX_tlb$insert_1__SEL_1 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 ; - assign MUX_tlb$insert_1__SEL_2 = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d958 ; - assign MUX_tlb$insert_1__SEL_3 = - WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 = - ctr_wr_rsps_pending_crg + 4'd1 ; - assign MUX_dw_output_ld_val$wset_1__VAL_3 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - new_value__h7622 : - new_value__h17651 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, lev_0_pte_pa_w64_fa__h24218, 29'd851968 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, - mem_req_wr_addr_awaddr__h31419, - 8'd0, - value__h30942, - 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_3 = - { 4'd0, lev_1_pte_pa_w64_fa__h23261, 29'd589824 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_4 = - { 4'd0, cline_fabric_addr__h25476, 29'd7143424 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_1 = - { 4'd0, - mem_req_wr_addr_awaddr__h31419, - 8'd0, - value__h33968, - 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_2 = - { 4'd0, addr__h7263, 8'd0, value__h33968, 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_4 = - { 4'd0, mem_req_wr_addr_awaddr__h3403, 29'd589824 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_1 = - { 4'd0, - mem_req_wr_data_wdata__h31624, - mem_req_wr_data_wstrb__h31625, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_2 = - { 4'd0, - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d784, - mem_req_wr_data_wstrb__h18932, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_3 = - { 4'd0, - mem_req_wr_data_wdata__h3595, - mem_req_wr_data_wstrb__h3596, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_4 = - { 4'd0, - mem_req_wr_data_wdata__h30120, - mem_req_wr_data_wstrb__h31625, - 1'd1 } ; - assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 = { 1'd1, rg_pa[33:12] } ; - assign MUX_ram_word64_set$a_put_3__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 : - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 ; - assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ; - assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:5], 2'd0 } ; - assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 7'd1 ; - assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ; - assign MUX_rg_exc_code$write_1__VAL_5 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - exc_code___1__h6589 : - access_exc_code__h3148 ; - assign MUX_rg_ld_val$write_1__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - x__h15303 : - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 ; - assign MUX_rg_pa$write_1__VAL_1 = { 2'd0, req_addr } ; - assign MUX_rg_state$write_1__VAL_2 = - NOT_req_f3_BITS_1_TO_0_344_EQ_0b0_345_346_AND__ETC___d1365 ? - 4'd4 : - 4'd3 ; - assign MUX_rg_state$write_1__VAL_6 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? 4'd14 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_10 = - (master_xactor_rg_rd_data[2:1] != 2'b0 || - rg_error_during_refill) ? - 4'd4 : - 4'd10 ; - assign MUX_rg_state$write_1__VAL_11 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - ((!_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - !_theResult____h23570[3] && !_theResult____h23570[1]) ? - 4'd4 : - 4'd10) : - 4'd4 ; - assign MUX_rg_state$write_1__VAL_12 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - ((!_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2]) ? - 4'd4 : - ((!_theResult____h23570[3] && !_theResult____h23570[1]) ? - 4'd7 : - ((_theResult____h23570[19:10] == 10'd0) ? - 4'd10 : - 4'd4))) : - 4'd4 ; - assign MUX_rg_state$write_1__VAL_13 = - (rg_priv_6_ULE_0b1___d67 && rg_satp[31] && !tlb$lookup[68]) ? - 4'd5 : - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d398 ; - - // inlined wires - assign dw_valid$whas = - (WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_read_rsp) && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d456 || - WILL_FIRE_RL_rl_drive_exception_rsp || - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign master_xactor_crg_wr_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_addr_full$port1__read = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full$port1__read && - mem_master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full$port1__read ; - assign master_xactor_crg_wr_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign master_xactor_crg_wr_addr_full$port3__read = - master_xactor_crg_wr_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_data_full$port1__read = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full$port1__read && mem_master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full$port1__read ; - assign master_xactor_crg_wr_data_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign master_xactor_crg_wr_data_full$port3__read = - master_xactor_crg_wr_data_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_wr_resp_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_resp_full$port1__read = - !master_xactor_crg_wr_resp_full$EN_port0__write && - master_xactor_crg_wr_resp_full ; - assign master_xactor_crg_wr_resp_full$port2__read = - !WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_crg_wr_resp_full$port1__read ; - assign master_xactor_crg_wr_resp_full$EN_port2__write = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_wr_resp_full$port3__read = - master_xactor_crg_wr_resp_full$EN_port2__write || - master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_addr_full$port1__read = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full$port1__read && - mem_master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full$port1__read ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - !_theResult____h23570[2] && - !_theResult____h23570[3] && - !_theResult____h23570[1] || - WILL_FIRE_RL_rl_io_AMO_op_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_tlb_refill ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_data_full$port1__read = - !master_xactor_crg_rd_data_full$EN_port0__write && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port1__write = - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_cache_refill_rsps_loop || - WILL_FIRE_RL_rl_ptw_level_0 || - WILL_FIRE_RL_rl_ptw_level_1 || - WILL_FIRE_RL_rl_io_AMO_read_rsp ; - assign master_xactor_crg_rd_data_full$port2__read = - !master_xactor_crg_rd_data_full$EN_port1__write && - master_xactor_crg_rd_data_full$port1__read ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - mem_master_rvalid && - !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - assign ctr_wr_rsps_pending_crg$EN_port0__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - always@(MUX_dw_output_ld_val$wset_1__SEL_2 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_2: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - default: ctr_wr_rsps_pending_crg$port0__write_1 = - 4'b1010 /* unspecified value */ ; - endcase - end - assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h23160 - 4'd1 ; - assign ctr_wr_rsps_pending_crg$port2__read = - WILL_FIRE_RL_rl_discard_write_rsp ? - ctr_wr_rsps_pending_crg$port1__write_1 : - b__h23160 ; - assign ctr_wr_rsps_pending_crg$EN_port2__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign ctr_wr_rsps_pending_crg$port3__read = - ctr_wr_rsps_pending_crg$EN_port2__write ? - 4'd0 : - ctr_wr_rsps_pending_crg$port2__read ; - assign crg_sb_to_load_delay$port0__write_1 = - { 1'd0, crg_sb_to_load_delay[10:1] } ; - assign crg_sb_to_load_delay$EN_port1__write = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d763 ; - assign crg_sb_to_load_delay$port2__read = - crg_sb_to_load_delay$EN_port1__write ? - 11'd2047 : - crg_sb_to_load_delay$port0__write_1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register crg_sb_to_load_delay - assign crg_sb_to_load_delay$D_IN = crg_sb_to_load_delay$port2__read ; - assign crg_sb_to_load_delay$EN = 1'b1 ; - - // register ctr_wr_rsps_pending_crg - assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ; - assign ctr_wr_rsps_pending_crg$EN = 1'b1 ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = - master_xactor_crg_wr_resp_full$port3__read ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - always@(MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 or - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 or - MUX_master_xactor_rg_rd_addr$write_1__SEL_2 or - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 or - WILL_FIRE_RL_rl_start_tlb_refill or - MUX_master_xactor_rg_rd_addr$write_1__VAL_3 or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_master_xactor_rg_rd_addr$write_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_1; - MUX_master_xactor_rg_rd_addr$write_1__SEL_2: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_2; - WILL_FIRE_RL_rl_start_tlb_refill: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_3; - WILL_FIRE_RL_rl_start_cache_refill: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_4; - default: master_xactor_rg_rd_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_rd_addr$EN = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - !_theResult____h23570[2] && - !_theResult____h23570[3] && - !_theResult____h23570[1] || - WILL_FIRE_RL_rl_io_AMO_op_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_tlb_refill || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - always@(MUX_dw_output_ld_val$wset_1__SEL_2 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_writeback_updated_PTE or - MUX_master_xactor_rg_wr_addr$write_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_2: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - WILL_FIRE_RL_rl_writeback_updated_PTE: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_4; - default: master_xactor_rg_wr_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_addr$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - - // register master_xactor_rg_wr_data - always@(MUX_dw_output_ld_val$wset_1__SEL_2 or - MUX_master_xactor_rg_wr_data$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_data$write_1__VAL_2 or - WILL_FIRE_RL_rl_writeback_updated_PTE or - MUX_master_xactor_rg_wr_data$write_1__VAL_3 or - WILL_FIRE_RL_rl_io_write_req or - MUX_master_xactor_rg_wr_data$write_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_2: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_2; - WILL_FIRE_RL_rl_writeback_updated_PTE: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_4; - default: master_xactor_rg_wr_data$D_IN = - 77'h0AAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_data$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 || - WILL_FIRE_RL_rl_writeback_updated_PTE || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = - { mem_master_bid, mem_master_bresp } ; - assign master_xactor_rg_wr_resp$EN = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - - // register rg_addr - assign rg_addr$D_IN = req_addr ; - assign rg_addr$EN = EN_req ; - - // register rg_amo_funct7 - assign rg_amo_funct7$D_IN = req_amo_funct7 ; - assign rg_amo_funct7$EN = EN_req ; - - // register rg_cset_in_cache - assign rg_cset_in_cache$D_IN = - WILL_FIRE_RL_rl_reset ? - MUX_rg_cset_in_cache$write_1__VAL_1 : - 7'd0 ; - assign rg_cset_in_cache$EN = - WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ; - - // register rg_error_during_refill - assign rg_error_during_refill$D_IN = - MUX_rg_error_during_refill$write_1__SEL_1 ; - assign rg_error_during_refill$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register rg_exc_code - always@(MUX_rg_exc_code$write_1__SEL_1 or - MUX_rg_exc_code$write_1__VAL_1 or - MUX_rg_exc_code$write_1__SEL_2 or - MUX_rg_exc_code$write_1__SEL_3 or - MUX_rg_error_during_refill$write_1__SEL_1 or - access_exc_code__h3148 or - MUX_rg_exc_code$write_1__SEL_5 or - MUX_rg_exc_code$write_1__VAL_5 or - MUX_rg_exc_code$write_1__SEL_6 or - MUX_rg_exc_code$write_1__SEL_7 or x1_avValue_exc_code__h6228) - case (1'b1) - MUX_rg_exc_code$write_1__SEL_1: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1; - MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7; - MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5; - MUX_rg_error_during_refill$write_1__SEL_1: - rg_exc_code$D_IN = access_exc_code__h3148; - MUX_rg_exc_code$write_1__SEL_5: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5; - MUX_rg_exc_code$write_1__SEL_6: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5; - MUX_rg_exc_code$write_1__SEL_7: - rg_exc_code$D_IN = x1_avValue_exc_code__h6228; - default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_exc_code$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - EN_req && - NOT_req_f3_BITS_1_TO_0_344_EQ_0b0_345_346_AND__ETC___d1365 || - WILL_FIRE_RL_rl_ptw_level_1 && - NOT_IF_rg_pte_pa_98_BIT_2_99_THEN_master_xacto_ETC___d926 || - WILL_FIRE_RL_rl_ptw_level_0 && - (!_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - !_theResult____h23570[3] && !_theResult____h23570[1] || - master_xactor_rg_rd_data[2:1] != 2'b0) ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_ld_val - always@(MUX_dw_output_ld_val$wset_1__SEL_2 or - new_ld_val__h31357 or - MUX_rg_ld_val$write_1__SEL_2 or - MUX_rg_ld_val$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_rsp or - ld_val__h28519 or WILL_FIRE_RL_rl_io_AMO_SC_req) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_2: rg_ld_val$D_IN = new_ld_val__h31357; - MUX_rg_ld_val$write_1__SEL_2: - rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h28519; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1; - default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_ld_val$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d623 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_SC_req ; - - // register rg_lower_word32 - assign rg_lower_word32$D_IN = 32'h0 ; - assign rg_lower_word32$EN = 1'b0 ; - - // register rg_lower_word32_full - assign rg_lower_word32_full$D_IN = 1'd0 ; - assign rg_lower_word32_full$EN = - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_lrsc_pa - assign rg_lrsc_pa$D_IN = x1_avValue_pa__h6227 ; - assign rg_lrsc_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d594 ; - - // register rg_lrsc_valid - assign rg_lrsc_valid$D_IN = - MUX_rg_lrsc_valid$write_1__SEL_2 && - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d450 ; - assign rg_lrsc_valid$EN = - WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d449 || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = req_mstatus_MXR ; - assign rg_mstatus_MXR$EN = EN_req ; - - // register rg_op - assign rg_op$D_IN = req_op ; - assign rg_op$EN = EN_req ; - - // register rg_pa - assign rg_pa$D_IN = - EN_req ? MUX_rg_pa$write_1__VAL_1 : x1_avValue_pa__h6227 ; - assign rg_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d418 || - EN_req ; - - // register rg_priv - assign rg_priv$D_IN = req_priv ; - assign rg_priv$EN = EN_req ; - - // register rg_pte_pa - assign rg_pte_pa$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - lev_0_pte_pa__h24216 : - lev_1_pte_pa__h23259 ; - assign rg_pte_pa$EN = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - !_theResult____h23570[2] && - !_theResult____h23570[3] && - !_theResult____h23570[1] || - WILL_FIRE_RL_rl_start_tlb_refill ; - - // register rg_satp - assign rg_satp$D_IN = req_satp ; - assign rg_satp$EN = EN_req ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = req_sstatus_SUM ; - assign rg_sstatus_SUM$EN = EN_req ; - - // register rg_st_amo_val - assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h19386 ; - assign rg_st_amo_val$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d877 || - EN_req ; - - // register rg_state - always@(EN_tlb_flush or - EN_req or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_req or - WILL_FIRE_RL_rl_start_cache_refill or - WILL_FIRE_RL_rl_start_tlb_refill or - WILL_FIRE_RL_rl_io_AMO_read_rsp or - MUX_rg_state$write_1__VAL_6 or - WILL_FIRE_RL_rl_io_AMO_op_req or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_io_read_rsp or - MUX_rg_state$write_1__SEL_10 or - MUX_rg_state$write_1__VAL_10 or - WILL_FIRE_RL_rl_ptw_level_0 or - MUX_rg_state$write_1__VAL_11 or - WILL_FIRE_RL_rl_ptw_level_1 or - MUX_rg_state$write_1__VAL_12 or - MUX_rg_state$write_1__SEL_13 or - MUX_rg_state$write_1__VAL_13 or - WILL_FIRE_RL_rl_start_reset or - WILL_FIRE_RL_rl_io_AMO_SC_req or - WILL_FIRE_RL_rl_rereq or MUX_rg_state$write_1__SEL_17) - case (1'b1) - EN_tlb_flush: rg_state$D_IN = 4'd2; - EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 4'd13; - WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_start_tlb_refill: rg_state$D_IN = 4'd6; - WILL_FIRE_RL_rl_io_AMO_read_rsp: - rg_state$D_IN = MUX_rg_state$write_1__VAL_6; - WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 4'd15; - WILL_FIRE_RL_rl_io_write_req: rg_state$D_IN = 4'd11; - WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_6; - MUX_rg_state$write_1__SEL_10: - rg_state$D_IN = MUX_rg_state$write_1__VAL_10; - WILL_FIRE_RL_rl_ptw_level_0: rg_state$D_IN = MUX_rg_state$write_1__VAL_11; - WILL_FIRE_RL_rl_ptw_level_1: rg_state$D_IN = MUX_rg_state$write_1__VAL_12; - MUX_rg_state$write_1__SEL_13: - rg_state$D_IN = MUX_rg_state$write_1__VAL_13; - WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 4'd1; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_state$D_IN = 4'd11; - WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_17: rg_state$D_IN = 4'd2; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_state$EN = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d393 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_ptw_level_1 || - WILL_FIRE_RL_rl_ptw_level_0 || - EN_req || - WILL_FIRE_RL_rl_start_reset || - EN_tlb_flush || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_tlb_refill || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_io_AMO_SC_req || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_io_AMO_op_req ; - - // register rg_word64_set_in_cache - assign rg_word64_set_in_cache$D_IN = - MUX_ram_word64_set$b_put_1__SEL_2 ? - MUX_ram_word64_set$b_put_2__VAL_2 : - MUX_ram_word64_set$b_put_2__VAL_4 ; - assign rg_word64_set_in_cache$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule f_pte_writebacks - assign f_pte_writebacks$D_IN = { tlb$lookup[33:0], x1_avValue_pte__h6230 } ; - assign f_pte_writebacks$ENQ = MUX_tlb$insert_1__SEL_1 ; - assign f_pte_writebacks$DEQ = WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign f_pte_writebacks$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = !EN_server_reset_request_put ; - assign f_reset_reqs$ENQ = - EN_server_reset_request_put || EN_server_flush_request_put ; - assign f_reset_reqs$DEQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ; - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign f_reset_rsps$DEQ = - EN_server_flush_response_get || EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule ram_state_and_ctag_cset - assign ram_state_and_ctag_cset$ADDRA = - WILL_FIRE_RL_rl_start_cache_refill ? - rg_addr[11:5] : - rg_cset_in_cache ; - assign ram_state_and_ctag_cset$ADDRB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - req_addr[11:5] : - rg_addr[11:5] ; - assign ram_state_and_ctag_cset$DIA = - WILL_FIRE_RL_rl_start_cache_refill ? - MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 : - 23'd2796202 ; - assign ram_state_and_ctag_cset$DIB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - 23'b01010101010101010101010 /* unspecified value */ : - 23'b01010101010101010101010 /* unspecified value */ ; - assign ram_state_and_ctag_cset$WEA = 1'd1 ; - assign ram_state_and_ctag_cset$WEB = 1'd0 ; - assign ram_state_and_ctag_cset$ENA = - WILL_FIRE_RL_rl_start_cache_refill || WILL_FIRE_RL_rl_reset ; - assign ram_state_and_ctag_cset$ENB = - EN_req && - req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374 || - WILL_FIRE_RL_rl_rereq ; - - // submodule ram_word64_set - assign ram_word64_set$ADDRA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - rg_word64_set_in_cache : - rg_addr[11:3] ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - req_addr or - MUX_ram_word64_set$b_put_1__SEL_2 or - MUX_ram_word64_set$b_put_2__VAL_2 or - WILL_FIRE_RL_rl_rereq or - rg_addr or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_ram_word64_set$b_put_2__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$ADDRB = req_addr[11:3]; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2; - WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3]; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4; - default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ; - endcase - end - assign ram_word64_set$DIA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - master_xactor_rg_rd_data[66:3] : - MUX_ram_word64_set$a_put_3__VAL_2 ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - MUX_ram_word64_set$b_put_1__SEL_2 or - WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_rereq: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - default: ram_word64_set$DIB = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign ram_word64_set$WEA = 1'd1 ; - assign ram_word64_set$WEB = 1'd0 ; - assign ram_word64_set$ENA = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d636 ; - assign ram_word64_set$ENB = - EN_req && - req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = { 30'd0, x1_avValue_pa__h6227 } ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule tlb - assign tlb$insert_asid = rg_satp[30:22] ; - always@(MUX_tlb$insert_1__SEL_1 or - tlb$lookup or MUX_tlb$insert_1__SEL_2 or MUX_tlb$insert_1__SEL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_tlb$insert_1__SEL_1: tlb$insert_level = tlb$lookup[35:34]; - MUX_tlb$insert_1__SEL_2: tlb$insert_level = 2'd1; - MUX_tlb$insert_1__SEL_3: tlb$insert_level = 2'd0; - default: tlb$insert_level = 2'b10 /* unspecified value */ ; - endcase - end - always@(MUX_tlb$insert_1__SEL_1 or - x1_avValue_pte__h6230 or - MUX_tlb$insert_1__SEL_2 or - _theResult____h23570 or MUX_tlb$insert_1__SEL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_tlb$insert_1__SEL_1: tlb$insert_pte = x1_avValue_pte__h6230; - MUX_tlb$insert_1__SEL_2: tlb$insert_pte = _theResult____h23570; - MUX_tlb$insert_1__SEL_3: tlb$insert_pte = _theResult____h23570; - default: tlb$insert_pte = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign tlb$insert_pte_pa = - MUX_tlb$insert_1__SEL_1 ? tlb$lookup[33:0] : rg_pte_pa ; - assign tlb$insert_vpn = rg_addr[31:12] ; - assign tlb$lookup_asid = rg_satp[30:22] ; - assign tlb$lookup_vpn = rg_addr[31:12] ; - assign tlb$EN_flush = WILL_FIRE_RL_rl_start_reset || EN_tlb_flush ; - assign tlb$EN_insert = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 || - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d958 || - WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) ; - - // remaining internal signals - assign IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d293 = - (x1_avValue_pa__h6227[2:0] == 3'h0) ? - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 : - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d292 ; - assign IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d574 = - (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; - assign IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253 = - (rg_addr[2:0] == 3'h0) ? ld_val__h28519 : 64'd0 ; - assign IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217 = - (rg_addr[2:0] == 3'h0) ? - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199 : - rg_addr[2:0] != 3'h4 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199 ; - assign IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560 = - (rg_addr[2:0] == 3'h0) ? word64__h7440 : 64'd0 ; - assign IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 = - (rg_f3 == 3'b010) ? - { {32{rg_st_amo_val_BITS_31_TO_0__q32[31]}}, - rg_st_amo_val_BITS_31_TO_0__q32 } : - rg_st_amo_val ; - assign IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d305 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - !ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 || - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 : - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d304 ; - assign IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d396 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd8 : - IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d395 ; - assign IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d304 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - rg_op_2_EQ_2_5_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d248 : - !ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297 && - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 && - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 ; - assign IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d395 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - 4'd11 : - ((!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) ? - 4'd8 : - 4'd11) ; - assign IF_rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_am_ETC___d784 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - mem_req_wr_data_wdata__h18931 : - mem_req_wr_data_wdata__h22367 ; - assign IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d398 = - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 ? - 4'd4 : - ((dmem_not_imem && !soc_map$m_is_mem_addr) ? - 4'd12 : - IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d396) ; - assign IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 = - x1_avValue_pa__h6227 == rg_lrsc_pa ; - assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d284 = - x1_avValue_pa__h6227[2:0] != 3'h7 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d289 = - x1_avValue_pa__h6227[2:0] != 3'h6 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d292 = - x1_avValue_pa__h6227[2:0] != 3'h4 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_IF_rg_pte_pa_98_BIT_2_99_THEN_master_xacto_ETC___d926 = - !_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - (_theResult____h23570[3] || _theResult____h23570[1]) && - _theResult____h23570[19:10] != 10'd0 || - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign NOT_cfg_verbosity_read__5_ULE_2_014___d1015 = cfg_verbosity > 4'd2 ; - assign NOT_cfg_verbosity_read__5_ULT_2_02___d403 = cfg_verbosity >= 4'd2 ; - assign NOT_dmem_not_imem_07_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d338 = - !dmem_not_imem && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb$lookup[39] ; - assign NOT_dmem_not_imem_07_OR_NOT_rg_op_2_EQ_0_3_4_A_ETC___d114 = - !dmem_not_imem || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - !tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d621 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - rg_op != 2'd1 && ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d634 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d632 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d761 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d759 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d795 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d813 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d852 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d850 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d857 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d855 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d863 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d861 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d871 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d869 ; - assign NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d875 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d631 ; - assign NOT_master_xactor_rg_rd_data_94_BITS_2_TO_1_95_ETC___d919 = - master_xactor_rg_rd_data[2:1] != 2'b0 || - !_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2] || - ((!_theResult____h23570[3] && !_theResult____h23570[1]) ? - !master_xactor_crg_rd_addr_full$port2__read : - _theResult____h23570[19:10] != 10'd0 || tlb$RDY_insert) ; - assign NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199 = - !ram_state_and_ctag_cset$DOB[22] || !rg_priv_6_ULE_0b1___d67 || - !rg_satp[31] || - tlb$RDY_lookup ; - assign NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d434 = - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 ; - assign NOT_req_f3_BITS_1_TO_0_344_EQ_0b0_345_346_AND__ETC___d1365 = - req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && - (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && - (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; - assign NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_7__ETC___d294 = - rg_f3 != 3'b011 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_rg_op_2_EQ_0_3_4_AND_NOT_rg_op_2_EQ_2_5_6__ETC___d389 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d443 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d631 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d758 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d850 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d855 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d861 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d869 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d629 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d756 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d816 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d822 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d828 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d834 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d345 = - (rg_priv != 2'b0 || tlb$lookup[40]) && - (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) && - (NOT_dmem_not_imem_07_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d338 || - dmem_not_imem_AND_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_ETC___d340 || - dmem_not_imem && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - tlb$lookup[38]) ; - assign NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d368 = - (rg_priv != 2'b0 || tlb$lookup[40]) && - (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) && - dmem_not_imem && - tlb$lookup[38] ; - assign NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d406 = - (rg_priv != 2'b0 || tlb$lookup[40]) && - (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) && - tlb$lookup[42] && - !pte___2__h6687[7] && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ; - assign NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d580 = - (rg_priv != 2'b0 || tlb$lookup[40]) && - (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) && - (!dmem_not_imem && tlb$lookup[39] || - dmem_not_imem && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112) ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d148 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d136 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d145 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d307 = - (NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d148 || - tlb$RDY_lookup && tlb$RDY_insert && f_pte_writebacks$FULL_N) && - (dmem_not_imem && !soc_map$m_is_mem_addr || - IF_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_ETC___d305) ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || - tlb$lookup[68] && - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d345 && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d347 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d365 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d136 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d145 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d417 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d345 && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d347 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d418 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d417 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d425 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - (rg_priv != 2'b0 || tlb$lookup[40]) && - (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) && - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d421 && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d347 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d428 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d425 && - dmem_not_imem && - !soc_map$m_is_mem_addr && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d449 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d417 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d446 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d455 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d417 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d450 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15293) ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d456 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d455 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d580 && - tlb$lookup[42] ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d588 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d585 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d594 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d601 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d607 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d604 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d613 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d583 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d610 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || !tlb$lookup[68] || - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d368 && - tlb$lookup[42] && - tlb$lookup[43] ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d623 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d621 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d636 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d634 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d763 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d761 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d768 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d764 || - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d631) ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d769 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d768 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d797 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d795 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d803 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - rg_lrsc_valid && - !rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d809 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !rg_lrsc_valid && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d815 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d813 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d820 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d816 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d820 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d826 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d822 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d832 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d828 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d832 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d838 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d834 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d839 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d838 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d846 = - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15293 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d847 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d846 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d852 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d857 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d865 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d863 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d871 ; - assign NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d877 = - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d617 && - NOT_dmem_not_imem_07_OR_soc_map_m_is_mem_addr__ETC___d875 ; - assign NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129 = - !tlb$lookup[42] || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - !tlb$lookup[43] ; - assign NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d145 = - !tlb$lookup[42] || !tlb$lookup[43] || pte___2__h6687[7] || - rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ; - assign _theResult____h23570 = - rg_pte_pa[2] ? - master_xactor_rg_rd_data[66:35] : - master_xactor_rg_rd_data[34:3] ; - assign _theResult___fst__h6315 = - tlb$lookup[68] ? _theResult___fst__h6387 : pa__h6215 ; - assign _theResult___fst__h6387 = - (rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129) ? - pa__h6215 : - _theResult___fst__h6689 ; - assign _theResult___snd_fst__h18939 = rg_st_amo_val << shift_bits__h18732 ; - assign _theResult___snd_fst__h22375 = - new_st_val__h19386 << shift_bits__h18732 ; - assign _theResult___snd_fst__h30128 = rg_st_amo_val << shift_bits__h31425 ; - assign _theResult___snd_fst__h31632 = st_val__h31369 << shift_bits__h31425 ; - assign _theResult___snd_fst__h6317 = - tlb$lookup[68] ? - _theResult___snd_fst__h6389 : - tlb$lookup[67:36] ; - assign _theResult___snd_fst__h6389 = - (rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129) ? - tlb$lookup[67:36] : - _theResult___snd_fst__h6827 ; - assign _theResult___snd_fst__h6827 = - (!pte___2__h6687[7] && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010)) ? - pte___1__h6904 : - pte___2__h6687 ; - assign access_exc_code__h3148 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd5 : - 4'd7) : - 4'd1 ; - assign addr__h7263 = { 30'd0, x1_avValue_pa__h6227 } ; - assign b__h23160 = - ctr_wr_rsps_pending_crg$EN_port0__write ? - ctr_wr_rsps_pending_crg$port0__write_1 : - ctr_wr_rsps_pending_crg ; - assign cfg_verbosity_read__5_ULE_1___d26 = cfg_verbosity <= 4'd1 ; - assign cline_addr__h25475 = { rg_pa[33:5], 5'd0 } ; - assign cline_fabric_addr__h25476 = { 30'd0, cline_addr__h25475 } ; - assign dmem_not_imem_AND_rg_op_2_EQ_0_3_OR_rg_op_2_EQ_ETC___d340 = - dmem_not_imem && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112 ; - assign dmem_not_imem_OR_NOT_rg_op_2_EQ_0_3_4_AND_NOT__ETC___d106 = - dmem_not_imem || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - !tlb$lookup[39] ; - assign exc_code___1__h6589 = x1_avValue_exc_code__h6228 ; - assign ld_val8519_BITS_15_TO_0__q37 = ld_val__h28519[15:0] ; - assign ld_val8519_BITS_15_TO_8__q39 = ld_val__h28519[15:8] ; - assign ld_val8519_BITS_23_TO_16__q40 = ld_val__h28519[23:16] ; - assign ld_val8519_BITS_31_TO_0__q38 = ld_val__h28519[31:0] ; - assign ld_val8519_BITS_31_TO_16__q41 = ld_val__h28519[31:16] ; - assign ld_val8519_BITS_31_TO_24__q42 = ld_val__h28519[31:24] ; - assign ld_val8519_BITS_39_TO_32__q43 = ld_val__h28519[39:32] ; - assign ld_val8519_BITS_47_TO_32__q44 = ld_val__h28519[47:32] ; - assign ld_val8519_BITS_47_TO_40__q46 = ld_val__h28519[47:40] ; - assign ld_val8519_BITS_55_TO_48__q47 = ld_val__h28519[55:48] ; - assign ld_val8519_BITS_63_TO_32__q45 = ld_val__h28519[63:32] ; - assign ld_val8519_BITS_63_TO_48__q48 = ld_val__h28519[63:48] ; - assign ld_val8519_BITS_63_TO_56__q49 = ld_val__h28519[63:56] ; - assign ld_val8519_BITS_7_TO_0__q36 = ld_val__h28519[7:0] ; - assign lev_0_PTN_pa__h24214 = { _theResult____h23570[31:10], 12'b0 } ; - assign lev_0_pte_pa__h24216 = lev_0_PTN_pa__h24214 + vpn_0_pa__h24215 ; - assign lev_0_pte_pa_w64__h24217 = { lev_0_pte_pa__h24216[33:3], 3'b0 } ; - assign lev_0_pte_pa_w64_fa__h24218 = { 30'd0, lev_0_pte_pa_w64__h24217 } ; - assign lev_1_pte_pa__h23259 = satp_pa__h2468 + vpn_1_pa__h23258 ; - assign lev_1_pte_pa_w64__h23260 = { lev_1_pte_pa__h23259[33:3], 3'b0 } ; - assign lev_1_pte_pa_w64_fa__h23261 = { 30'd0, lev_1_pte_pa_w64__h23260 } ; - assign lrsc_result__h15293 = - !rg_lrsc_valid || - !rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234 ; - assign master_xactor_crg_rd_data_full_port1__read__93_ETC___d1176 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - (!_theResult____h23570[0] || - !_theResult____h23570[1] && _theResult____h23570[2]) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - !_theResult____h23570[2] && - !_theResult____h23570[3] && - !_theResult____h23570[1] && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d958 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) && - _theResult____h23570[19:10] == 10'd0 ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d962 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) && - _theResult____h23570[19:10] == 10'd0 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d968 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) && - _theResult____h23570[19:10] != 10'd0 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d994 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign master_xactor_rg_rd_data_BITS_10_TO_3__q1 = - master_xactor_rg_rd_data[10:3] ; - assign master_xactor_rg_rd_data_BITS_18_TO_11__q4 = - master_xactor_rg_rd_data[18:11] ; - assign master_xactor_rg_rd_data_BITS_18_TO_3__q2 = - master_xactor_rg_rd_data[18:3] ; - assign master_xactor_rg_rd_data_BITS_26_TO_19__q5 = - master_xactor_rg_rd_data[26:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_19__q6 = - master_xactor_rg_rd_data[34:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_27__q7 = - master_xactor_rg_rd_data[34:27] ; - assign master_xactor_rg_rd_data_BITS_34_TO_3__q3 = - master_xactor_rg_rd_data[34:3] ; - assign master_xactor_rg_rd_data_BITS_42_TO_35__q8 = - master_xactor_rg_rd_data[42:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_35__q9 = - master_xactor_rg_rd_data[50:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_43__q11 = - master_xactor_rg_rd_data[50:43] ; - assign master_xactor_rg_rd_data_BITS_58_TO_51__q12 = - master_xactor_rg_rd_data[58:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_35__q10 = - master_xactor_rg_rd_data[66:35] ; - assign master_xactor_rg_rd_data_BITS_66_TO_51__q13 = - master_xactor_rg_rd_data[66:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_59__q14 = - master_xactor_rg_rd_data[66:59] ; - assign mem_req_wr_addr_awaddr__h31419 = { 30'd0, rg_pa } ; - assign mem_req_wr_addr_awaddr__h3403 = - { 30'd0, f_pte_writebacks$D_OUT[65:32] } ; - assign mem_req_wr_data_wdata__h3595 = st_val__h3324 << shift_bits__h3414 ; - assign mem_req_wr_data_wstrb__h3596 = - 8'b00001111 << f_pte_writebacks$D_OUT[34:32] ; - assign new_st_val__h19386 = - (rg_f3 == 3'b010) ? - new_st_val__h19668 : - _theResult_____2__h19664 ; - assign new_st_val__h19668 = { 32'd0, _theResult_____2__h19664[31:0] } ; - assign new_st_val__h19759 = - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 + - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ; - assign new_st_val__h20739 = w1__h19656 ^ w2__h31643 ; - assign new_st_val__h20743 = w1__h19656 & w2__h31643 ; - assign new_st_val__h20747 = w1__h19656 | w2__h31643 ; - assign new_st_val__h20751 = - (w1__h19656 < w2__h31643) ? w1__h19656 : w2__h31643 ; - assign new_st_val__h20756 = - (w1__h19656 <= w2__h31643) ? w2__h31643 : w1__h19656 ; - assign new_st_val__h20762 = - ((IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 ^ - 64'h8000000000000000) < - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ^ - 64'h8000000000000000)) ? - w1__h19656 : - w2__h31643 ; - assign new_st_val__h20767 = - ((IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 ^ - 64'h8000000000000000) <= - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ^ - 64'h8000000000000000)) ? - w2__h31643 : - w1__h19656 ; - assign new_st_val__h31653 = { 32'd0, _theResult_____2__h31649[31:0] } ; - assign new_st_val__h31744 = - new_ld_val__h31357 + - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ; - assign new_st_val__h33604 = w1__h31641 ^ w2__h31643 ; - assign new_st_val__h33608 = w1__h31641 & w2__h31643 ; - assign new_st_val__h33612 = w1__h31641 | w2__h31643 ; - assign new_st_val__h33616 = - (w1__h31641 < w2__h31643) ? w1__h31641 : w2__h31643 ; - assign new_st_val__h33621 = - (w1__h31641 <= w2__h31643) ? w2__h31643 : w1__h31641 ; - assign new_st_val__h33627 = - ((new_ld_val__h31357 ^ 64'h8000000000000000) < - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ^ - 64'h8000000000000000)) ? - w1__h31641 : - w2__h31643 ; - assign new_st_val__h33632 = - ((new_ld_val__h31357 ^ 64'h8000000000000000) <= - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d691 ^ - 64'h8000000000000000)) ? - w2__h31643 : - w1__h31641 ; - assign new_value622_BITS_31_TO_0__q31 = new_value__h7622[31:0] ; - assign pa___1__h6695 = { tlb$lookup[67:46], rg_addr[11:0] } ; - assign pa___1__h6744 = { tlb$lookup[67:56], rg_addr[21:0] } ; - assign pa__h6215 = { 2'd0, rg_addr } ; - assign pte___1__h6876 = { tlb$lookup[67:43], 1'd1, tlb$lookup[41:36] } ; - assign pte___1__h6904 = - { pte___2__h6687[31:8], 1'd1, pte___2__h6687[6:0] } ; - assign pte___2__h6687 = - tlb$lookup[42] ? tlb$lookup[67:36] : pte___1__h6876 ; - assign ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 = - ram_state_and_ctag_cset$DOB[21:0] == - x1_avValue_pa__h6227[33:12] ; - assign ram_state_and_ctag_cset_b_read__73_BIT_22_74_A_ETC___d435 = - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d434 ; - assign req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374 = - req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || - req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || - req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; - assign result__h14033 = - { {56{word64440_BITS_15_TO_8__q18[7]}}, - word64440_BITS_15_TO_8__q18 } ; - assign result__h14061 = - { {56{word64440_BITS_23_TO_16__q19[7]}}, - word64440_BITS_23_TO_16__q19 } ; - assign result__h14089 = - { {56{word64440_BITS_31_TO_24__q21[7]}}, - word64440_BITS_31_TO_24__q21 } ; - assign result__h14117 = - { {56{word64440_BITS_39_TO_32__q22[7]}}, - word64440_BITS_39_TO_32__q22 } ; - assign result__h14145 = - { {56{word64440_BITS_47_TO_40__q25[7]}}, - word64440_BITS_47_TO_40__q25 } ; - assign result__h14173 = - { {56{word64440_BITS_55_TO_48__q26[7]}}, - word64440_BITS_55_TO_48__q26 } ; - assign result__h14201 = - { {56{word64440_BITS_63_TO_56__q28[7]}}, - word64440_BITS_63_TO_56__q28 } ; - assign result__h14246 = { 56'd0, word64__h7440[7:0] } ; - assign result__h14274 = { 56'd0, word64__h7440[15:8] } ; - assign result__h14302 = { 56'd0, word64__h7440[23:16] } ; - assign result__h14330 = { 56'd0, word64__h7440[31:24] } ; - assign result__h14358 = { 56'd0, word64__h7440[39:32] } ; - assign result__h14386 = { 56'd0, word64__h7440[47:40] } ; - assign result__h14414 = { 56'd0, word64__h7440[55:48] } ; - assign result__h14442 = { 56'd0, word64__h7440[63:56] } ; - assign result__h14487 = - { {48{word64440_BITS_15_TO_0__q16[15]}}, - word64440_BITS_15_TO_0__q16 } ; - assign result__h14515 = - { {48{word64440_BITS_31_TO_16__q20[15]}}, - word64440_BITS_31_TO_16__q20 } ; - assign result__h14543 = - { {48{word64440_BITS_47_TO_32__q23[15]}}, - word64440_BITS_47_TO_32__q23 } ; - assign result__h14571 = - { {48{word64440_BITS_63_TO_48__q27[15]}}, - word64440_BITS_63_TO_48__q27 } ; - assign result__h14612 = { 48'd0, word64__h7440[15:0] } ; - assign result__h14640 = { 48'd0, word64__h7440[31:16] } ; - assign result__h14668 = { 48'd0, word64__h7440[47:32] } ; - assign result__h14696 = { 48'd0, word64__h7440[63:48] } ; - assign result__h14737 = - { {32{word64440_BITS_31_TO_0__q17[31]}}, - word64440_BITS_31_TO_0__q17 } ; - assign result__h14765 = - { {32{word64440_BITS_63_TO_32__q24[31]}}, - word64440_BITS_63_TO_32__q24 } ; - assign result__h14804 = { 32'd0, word64__h7440[31:0] } ; - assign result__h14832 = { 32'd0, word64__h7440[63:32] } ; - assign result__h28579 = - { {56{master_xactor_rg_rd_data_BITS_10_TO_3__q1[7]}}, - master_xactor_rg_rd_data_BITS_10_TO_3__q1 } ; - assign result__h28609 = - { {56{master_xactor_rg_rd_data_BITS_18_TO_11__q4[7]}}, - master_xactor_rg_rd_data_BITS_18_TO_11__q4 } ; - assign result__h28636 = - { {56{master_xactor_rg_rd_data_BITS_26_TO_19__q5[7]}}, - master_xactor_rg_rd_data_BITS_26_TO_19__q5 } ; - assign result__h28663 = - { {56{master_xactor_rg_rd_data_BITS_34_TO_27__q7[7]}}, - master_xactor_rg_rd_data_BITS_34_TO_27__q7 } ; - assign result__h28690 = - { {56{master_xactor_rg_rd_data_BITS_42_TO_35__q8[7]}}, - master_xactor_rg_rd_data_BITS_42_TO_35__q8 } ; - assign result__h28717 = - { {56{master_xactor_rg_rd_data_BITS_50_TO_43__q11[7]}}, - master_xactor_rg_rd_data_BITS_50_TO_43__q11 } ; - assign result__h28744 = - { {56{master_xactor_rg_rd_data_BITS_58_TO_51__q12[7]}}, - master_xactor_rg_rd_data_BITS_58_TO_51__q12 } ; - assign result__h28771 = - { {56{master_xactor_rg_rd_data_BITS_66_TO_59__q14[7]}}, - master_xactor_rg_rd_data_BITS_66_TO_59__q14 } ; - assign result__h28815 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h28842 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h28869 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h28896 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h28923 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h28950 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h28977 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h29004 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h29048 = - { {48{master_xactor_rg_rd_data_BITS_18_TO_3__q2[15]}}, - master_xactor_rg_rd_data_BITS_18_TO_3__q2 } ; - assign result__h29075 = - { {48{master_xactor_rg_rd_data_BITS_34_TO_19__q6[15]}}, - master_xactor_rg_rd_data_BITS_34_TO_19__q6 } ; - assign result__h29102 = - { {48{master_xactor_rg_rd_data_BITS_50_TO_35__q9[15]}}, - master_xactor_rg_rd_data_BITS_50_TO_35__q9 } ; - assign result__h29129 = - { {48{master_xactor_rg_rd_data_BITS_66_TO_51__q13[15]}}, - master_xactor_rg_rd_data_BITS_66_TO_51__q13 } ; - assign result__h29169 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h29196 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h29223 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h29250 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h29290 = - { {32{master_xactor_rg_rd_data_BITS_34_TO_3__q3[31]}}, - master_xactor_rg_rd_data_BITS_34_TO_3__q3 } ; - assign result__h29317 = - { {32{master_xactor_rg_rd_data_BITS_66_TO_35__q10[31]}}, - master_xactor_rg_rd_data_BITS_66_TO_35__q10 } ; - assign result__h29355 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h29382 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; - assign result__h31832 = - { {56{ld_val8519_BITS_7_TO_0__q36[7]}}, - ld_val8519_BITS_7_TO_0__q36 } ; - assign result__h32740 = - { {56{ld_val8519_BITS_15_TO_8__q39[7]}}, - ld_val8519_BITS_15_TO_8__q39 } ; - assign result__h32768 = - { {56{ld_val8519_BITS_23_TO_16__q40[7]}}, - ld_val8519_BITS_23_TO_16__q40 } ; - assign result__h32796 = - { {56{ld_val8519_BITS_31_TO_24__q42[7]}}, - ld_val8519_BITS_31_TO_24__q42 } ; - assign result__h32824 = - { {56{ld_val8519_BITS_39_TO_32__q43[7]}}, - ld_val8519_BITS_39_TO_32__q43 } ; - assign result__h32852 = - { {56{ld_val8519_BITS_47_TO_40__q46[7]}}, - ld_val8519_BITS_47_TO_40__q46 } ; - assign result__h32880 = - { {56{ld_val8519_BITS_55_TO_48__q47[7]}}, - ld_val8519_BITS_55_TO_48__q47 } ; - assign result__h32908 = - { {56{ld_val8519_BITS_63_TO_56__q49[7]}}, - ld_val8519_BITS_63_TO_56__q49 } ; - assign result__h32953 = { 56'd0, ld_val__h28519[7:0] } ; - assign result__h32981 = { 56'd0, ld_val__h28519[15:8] } ; - assign result__h33009 = { 56'd0, ld_val__h28519[23:16] } ; - assign result__h33037 = { 56'd0, ld_val__h28519[31:24] } ; - assign result__h33065 = { 56'd0, ld_val__h28519[39:32] } ; - assign result__h33093 = { 56'd0, ld_val__h28519[47:40] } ; - assign result__h33121 = { 56'd0, ld_val__h28519[55:48] } ; - assign result__h33149 = { 56'd0, ld_val__h28519[63:56] } ; - assign result__h33194 = - { {48{ld_val8519_BITS_15_TO_0__q37[15]}}, - ld_val8519_BITS_15_TO_0__q37 } ; - assign result__h33222 = - { {48{ld_val8519_BITS_31_TO_16__q41[15]}}, - ld_val8519_BITS_31_TO_16__q41 } ; - assign result__h33250 = - { {48{ld_val8519_BITS_47_TO_32__q44[15]}}, - ld_val8519_BITS_47_TO_32__q44 } ; - assign result__h33278 = - { {48{ld_val8519_BITS_63_TO_48__q48[15]}}, - ld_val8519_BITS_63_TO_48__q48 } ; - assign result__h33319 = { 48'd0, ld_val__h28519[15:0] } ; - assign result__h33347 = { 48'd0, ld_val__h28519[31:16] } ; - assign result__h33375 = { 48'd0, ld_val__h28519[47:32] } ; - assign result__h33403 = { 48'd0, ld_val__h28519[63:48] } ; - assign result__h33444 = - { {32{ld_val8519_BITS_31_TO_0__q38[31]}}, - ld_val8519_BITS_31_TO_0__q38 } ; - assign result__h33472 = - { {32{ld_val8519_BITS_63_TO_32__q45[31]}}, - ld_val8519_BITS_63_TO_32__q45 } ; - assign result__h33511 = { 32'd0, ld_val__h28519[31:0] } ; - assign result__h33539 = { 32'd0, ld_val__h28519[63:32] } ; - assign result__h7677 = - { {56{word64440_BITS_7_TO_0__q15[7]}}, - word64440_BITS_7_TO_0__q15 } ; - assign rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d610 = - rg_amo_funct7[6:2] == 5'b00010 && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234 = - rg_lrsc_pa == x1_avValue_pa__h6227 ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d384 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d421 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - tlb$lookup[38] ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d446 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset_b_read__73_BIT_22_74_A_ETC___d435 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d444 ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d450 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d585 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178 && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d604 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178) && - !cfg_verbosity_read__5_ULE_1___d26 ; - assign rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d444 = - rg_op == 2'd1 && - IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0__ETC___d432 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d443 ; - assign rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d632 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d629 || - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d631 ; - assign rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d759 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_2_EQ_2_5_6_OR_NOT_rg_amo_funct7_7_BI_ETC___d756 || - NOT_rg_op_2_EQ_1_27_40_AND_NOT_rg_op_2_EQ_2_5__ETC___d758 ; - assign rg_op_2_EQ_1_27_OR_rg_op_2_EQ_2_5_AND_rg_amo_f_ETC___d764 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_6_ULE_0b1_7_AND_rg_ETC___d234) ; - assign rg_op_2_EQ_2_5_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d248 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15293 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 ; - assign rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123 = - rg_priv == 2'b0 && !tlb$lookup[40] || - rg_priv == 2'b01 && tlb$lookup[40] && !rg_sstatus_SUM || - dmem_not_imem_OR_NOT_rg_op_2_EQ_0_3_4_AND_NOT__ETC___d106 && - NOT_dmem_not_imem_07_OR_NOT_rg_op_2_EQ_0_3_4_A_ETC___d114 && - (!dmem_not_imem || rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - !tlb$lookup[38]) ; - assign rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d136 = - rg_priv == 2'b0 && !tlb$lookup[40] || - rg_priv == 2'b01 && tlb$lookup[40] && !rg_sstatus_SUM || - !dmem_not_imem || - !tlb$lookup[38] ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && tlb$lookup[68] && - (rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129) ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d309 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && !tlb$lookup[68] || - (rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 ? - tlb$RDY_lookup : - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d307) ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d353 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && - (rg_priv_6_EQ_0b0_2_AND_NOT_tlb_lookup_rg_satp__ETC___d123 || - NOT_tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_ad_ETC___d129) && - tlb$lookup[68] ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && tlb$lookup[68] && - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d368 && - tlb$lookup[42] && - tlb$lookup[43] && - !pte___2__h6687[7] && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d392 = - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d132 || - dmem_not_imem && !soc_map$m_is_mem_addr || - rg_op_2_EQ_0_3_OR_rg_op_2_EQ_2_5_AND_rg_amo_fu_ETC___d384 || - NOT_rg_op_2_EQ_0_3_4_AND_NOT_rg_op_2_EQ_2_5_6__ETC___d389 ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d393 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && !tlb$lookup[68] || - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d392 ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d411 = - rg_priv_6_ULE_0b1___d67 && rg_satp[31] && tlb$lookup[68] && - NOT_rg_priv_6_EQ_0b0_2_31_OR_tlb_lookup_rg_sat_ETC___d406 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403 && - dmem_not_imem && - tlb$lookup[38] && - tlb$lookup[43] ; - assign rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d414 = - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403 && - (!dmem_not_imem || !tlb$lookup[38] || !tlb$lookup[43]) ; - assign rg_priv_6_ULE_0b1___d67 = rg_priv <= 2'b01 ; - assign rg_st_amo_val_BITS_31_TO_0__q32 = rg_st_amo_val[31:0] ; - assign rg_state_0_EQ_12_043_AND_rg_op_2_EQ_0_3_OR_rg__ETC___d1045 = - rg_state == 4'd12 && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - b__h23160 == 4'd0 ; - assign rg_state_0_EQ_3_12_AND_NOT_rg_op_2_EQ_0_3_4_AN_ETC___d316 = - rg_state == 4'd3 && - (rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - crg_sb_to_load_delay$port0__write_1 == 11'd0) ; - assign satp_pa__h2468 = { rg_satp[21:0], 12'b0 } ; - assign shift_bits__h18732 = { x1_avValue_pa__h6227[2:0], 3'b0 } ; - assign shift_bits__h31425 = { rg_pa[2:0], 3'b0 } ; - assign shift_bits__h3414 = { f_pte_writebacks$D_OUT[34:32], 3'b0 } ; - assign st_val__h31369 = - (rg_f3 == 3'b010) ? - new_st_val__h31653 : - _theResult_____2__h31649 ; - assign st_val__h3324 = { 32'd0, f_pte_writebacks$D_OUT[31:0] } ; - assign strobe64__h18865 = 8'b00000001 << x1_avValue_pa__h6227[2:0] ; - assign strobe64__h18867 = 8'b00000011 << x1_avValue_pa__h6227[2:0] ; - assign strobe64__h18869 = 8'b00001111 << x1_avValue_pa__h6227[2:0] ; - assign strobe64__h31558 = 8'b00000001 << rg_pa[2:0] ; - assign strobe64__h31560 = 8'b00000011 << rg_pa[2:0] ; - assign strobe64__h31562 = 8'b00001111 << rg_pa[2:0] ; - assign tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d112 = - tlb$lookup[37] | y__h6515 ; - assign tlb_lookup_rg_satp_9_BITS_30_TO_22_5_rg_addr_6_ETC___d347 = - tlb$lookup[42] && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - tlb$lookup[43]) ; - assign vpn_0_pa__h24215 = { 22'd0, rg_addr[21:12], 2'd0 } ; - assign vpn_1_pa__h23258 = { 22'd0, rg_addr[31:22], 2'd0 } ; - assign w11637_BITS_31_TO_0__q51 = w1__h31637[31:0] ; - assign w1___1__h19727 = { 32'd0, new_value__h7622[31:0] } ; - assign w1___1__h31712 = { 32'd0, w1__h31637[31:0] } ; - assign w2___1__h31713 = { 32'd0, rg_st_amo_val[31:0] } ; - assign w2__h31643 = (rg_f3 == 3'b010) ? w2___1__h31713 : rg_st_amo_val ; - assign word64440_BITS_15_TO_0__q16 = word64__h7440[15:0] ; - assign word64440_BITS_15_TO_8__q18 = word64__h7440[15:8] ; - assign word64440_BITS_23_TO_16__q19 = word64__h7440[23:16] ; - assign word64440_BITS_31_TO_0__q17 = word64__h7440[31:0] ; - assign word64440_BITS_31_TO_16__q20 = word64__h7440[31:16] ; - assign word64440_BITS_31_TO_24__q21 = word64__h7440[31:24] ; - assign word64440_BITS_39_TO_32__q22 = word64__h7440[39:32] ; - assign word64440_BITS_47_TO_32__q23 = word64__h7440[47:32] ; - assign word64440_BITS_47_TO_40__q25 = word64__h7440[47:40] ; - assign word64440_BITS_55_TO_48__q26 = word64__h7440[55:48] ; - assign word64440_BITS_63_TO_32__q24 = word64__h7440[63:32] ; - assign word64440_BITS_63_TO_48__q27 = word64__h7440[63:48] ; - assign word64440_BITS_63_TO_56__q28 = word64__h7440[63:56] ; - assign word64440_BITS_7_TO_0__q15 = word64__h7440[7:0] ; - assign word64__h7440 = ram_word64_set$DOB & y__h7713 ; - assign x1_avValue_exc_code__h6228 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd13 : - 4'd15) : - 4'd12 ; - assign x1_avValue_pa__h6227 = - (rg_priv_6_ULE_0b1___d67 && rg_satp[31]) ? - _theResult___fst__h6315 : - pa__h6215 ; - assign x1_avValue_pte__h6230 = - (rg_priv_6_ULE_0b1___d67 && rg_satp[31]) ? - _theResult___snd_fst__h6317 : - tlb$lookup[67:36] ; - assign x__h15303 = { 63'd0, lrsc_result__h15293 } ; - assign y__h6515 = rg_mstatus_MXR & tlb$lookup[39] ; - assign y__h7713 = - {64{ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__73_BITS_21_TO__ETC___d178}} ; - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h30942 = 3'b0; - 2'b01: value__h30942 = 3'b001; - 2'b10: value__h30942 = 3'b010; - 2'd3: value__h30942 = 3'b011; - endcase - end - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h33968 = 3'b0; - 2'b01: value__h33968 = 3'b001; - 2'b10: value__h33968 = 3'b010; - 2'b11: value__h33968 = 3'b011; - endcase - end - always@(tlb$lookup or pa__h6215 or pa___1__h6695 or pa___1__h6744) - begin - case (tlb$lookup[35:34]) - 2'd0: _theResult___fst__h6689 = pa___1__h6695; - 2'd1: _theResult___fst__h6689 = pa___1__h6744; - default: _theResult___fst__h6689 = pa__h6215; - endcase - end - always@(rg_f3 or strobe64__h31558 or strobe64__h31560 or strobe64__h31562) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h31625 = strobe64__h31558; - 2'b01: mem_req_wr_data_wstrb__h31625 = strobe64__h31560; - 2'b10: mem_req_wr_data_wstrb__h31625 = strobe64__h31562; - 2'b11: mem_req_wr_data_wstrb__h31625 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h30128) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h30120 = _theResult___snd_fst__h30128; - 2'd3: mem_req_wr_data_wdata__h30120 = rg_st_amo_val; - endcase - end - always@(rg_f3 or strobe64__h18865 or strobe64__h18867 or strobe64__h18869) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h18932 = strobe64__h18865; - 2'b01: mem_req_wr_data_wstrb__h18932 = strobe64__h18867; - 2'b10: mem_req_wr_data_wstrb__h18932 = strobe64__h18869; - 2'b11: mem_req_wr_data_wstrb__h18932 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h18939) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h18931 = _theResult___snd_fst__h18939; - 2'd3: mem_req_wr_data_wdata__h18931 = rg_st_amo_val; - endcase - end - always@(rg_f3 or rg_priv_6_ULE_0b1___d67 or rg_satp or tlb$RDY_lookup) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01: - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 = - !rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$RDY_lookup; - default: IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 = - rg_f3[1:0] != 2'b10 || !rg_priv_6_ULE_0b1___d67 || - !rg_satp[31] || - tlb$RDY_lookup; - endcase - end - always@(rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199) - begin - case (rg_addr[2:0]) - 3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 = - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199; - 3'd7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 = - rg_addr[2:0] != 3'h7 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199; - endcase - end - always@(rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199) - begin - case (rg_addr[2:0]) - 3'h0, 3'h2, 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 = - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 = - rg_addr[2:0] != 3'h6 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199; - endcase - end - always@(rg_f3 or - rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217) - begin - case (rg_f3) - 3'b0, 3'b100: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203; - 3'b001, 3'b101: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211; - 3'b010, 3'b110: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217; - default: IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - rg_f3 != 3'b011 || rg_addr[2:0] != 3'h0 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_22__ETC___d199; - endcase - end - always@(rg_amo_funct7 or - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225) - begin - case (rg_amo_funct7[6:2]) - 5'b0, 5'b00100, 5'b01000, 5'b01100, 5'b10000, 5'b11000, 5'b11100: - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 = - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225; - default: CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 = - rg_amo_funct7[6:2] != 5'b10100 || - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225; - endcase - end - always@(x1_avValue_pa__h6227 or - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d284 or - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d285 = - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29; - 3'd7: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d285 = - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d284; - endcase - end - always@(x1_avValue_pa__h6227 or - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d289 or - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0, 3'h2, 3'h4: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d290 = - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29; - default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d290 = - NOT_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_3_ETC___d289; - endcase - end - always@(rg_f3 or - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_7__ETC___d294 or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d285 or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d290 or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d293) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d285; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d290; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d293; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d297 = - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_7__ETC___d294; - endcase - end - always@(rg_addr or - result__h7677 or - result__h14033 or - result__h14061 or - result__h14089 or - result__h14117 or - result__h14145 or result__h14173 or result__h14201) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h7677; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14033; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14061; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14089; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14117; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14145; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14173; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 = - result__h14201; - endcase - end - always@(rg_addr or - result__h14246 or - result__h14274 or - result__h14302 or - result__h14330 or - result__h14358 or - result__h14386 or result__h14414 or result__h14442) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14246; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14274; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14302; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14330; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14358; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14386; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14414; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 = - result__h14442; - endcase - end - always@(rg_addr or - result__h14487 or - result__h14515 or result__h14543 or result__h14571) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 = - result__h14487; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 = - result__h14515; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 = - result__h14543; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 = - result__h14571; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 = - 64'd0; - endcase - end - always@(rg_addr or - result__h14612 or - result__h14640 or result__h14668 or result__h14696) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 = - result__h14612; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 = - result__h14640; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 = - result__h14668; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 = - result__h14696; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 = - 64'd0; - endcase - end - always@(rg_addr or result__h14804 or result__h14832) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559 = - result__h14804; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559 = - result__h14832; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559 = - 64'd0; - endcase - end - always@(rg_addr or result__h14737 or result__h14765) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30 = - result__h14737; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30 = - result__h14765; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559) - begin - case (rg_f3) - 3'b0: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513; - 3'b001: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541; - 3'b010: - new_value__h7622 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4737_0x4_re_ETC__q30; - 3'b011: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560; - 3'b100: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529; - 3'b101: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549; - 3'b110: - new_value__h7622 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559; - 3'd7: new_value__h7622 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 or - w1___1__h19727 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559) - begin - case (rg_f3) - 3'b0: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513; - 3'b001: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541; - 3'b010: w1__h19656 = w1___1__h19727; - 3'b011: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560; - 3'b100: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529; - 3'b101: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549; - 3'b110: - w1__h19656 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559; - 3'd7: w1__h19656 = 64'd0; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 = - { ram_word64_set$DOB[63:16], rg_st_amo_val[15:0] }; - 3'h2: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 = - { rg_st_amo_val[15:0], ram_word64_set$DOB[47:0] }; - default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 = - ram_word64_set$DOB; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:8], rg_st_amo_val[7:0] }; - 3'h1: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:16], - rg_st_amo_val[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:24], - rg_st_amo_val[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:40], - rg_st_amo_val[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { ram_word64_set$DOB[63:56], - rg_st_amo_val[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 = - { rg_st_amo_val[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541 or - new_value622_BITS_31_TO_0__q31 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d513; - 3'b001: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d541; - 3'b010: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - { {32{new_value622_BITS_31_TO_0__q31[31]}}, - new_value622_BITS_31_TO_0__q31 }; - 3'b011: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d560; - 3'b100: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d529; - 3'b101: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d549; - 3'b110: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d559; - 3'd7: IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d627 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h20767 or - new_st_val__h19759 or - w2__h31643 or - new_st_val__h20739 or - new_st_val__h20747 or - new_st_val__h20743 or - new_st_val__h20762 or new_st_val__h20751 or new_st_val__h20756) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h19664 = new_st_val__h19759; - 5'b00001: _theResult_____2__h19664 = w2__h31643; - 5'b00100: _theResult_____2__h19664 = new_st_val__h20739; - 5'b01000: _theResult_____2__h19664 = new_st_val__h20747; - 5'b01100: _theResult_____2__h19664 = new_st_val__h20743; - 5'b10000: _theResult_____2__h19664 = new_st_val__h20762; - 5'b11000: _theResult_____2__h19664 = new_st_val__h20751; - 5'b11100: _theResult_____2__h19664 = new_st_val__h20756; - default: _theResult_____2__h19664 = new_st_val__h20767; - endcase - end - always@(rg_f3 or new_st_val__h19386 or _theResult___snd_fst__h22375) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h22367 = _theResult___snd_fst__h22375; - 2'd3: mem_req_wr_data_wdata__h22367 = new_st_val__h19386; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or new_st_val__h19386) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 = - { ram_word64_set$DOB[63:16], new_st_val__h19386[15:0] }; - 3'h2: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 = - { ram_word64_set$DOB[63:32], - new_st_val__h19386[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 = - { ram_word64_set$DOB[63:48], - new_st_val__h19386[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 = - { new_st_val__h19386[15:0], ram_word64_set$DOB[47:0] }; - default: IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 = - ram_word64_set$DOB; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or new_st_val__h19386) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:8], new_st_val__h19386[7:0] }; - 3'h1: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:16], - new_st_val__h19386[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:24], - new_st_val__h19386[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:32], - new_st_val__h19386[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:40], - new_st_val__h19386[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:48], - new_st_val__h19386[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { ram_word64_set$DOB[63:56], - new_st_val__h19386[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 = - { new_st_val__h19386[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - { ram_word64_set$DOB[63:32], rg_st_amo_val[31:0] }; - 3'h4: - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - { rg_st_amo_val[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669 or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678 or - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33 or - rg_st_amo_val) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d669; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d678; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 = - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q33; - 3'b011: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 = - rg_st_amo_val; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or - result__h29169 or - result__h29196 or result__h29223 or result__h29250) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 = - result__h29169; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 = - result__h29196; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 = - result__h29223; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 = - result__h29250; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 = - 64'd0; - endcase - end - always@(rg_addr or - result__h29048 or - result__h29075 or result__h29102 or result__h29129) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 = - result__h29048; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 = - result__h29075; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 = - result__h29102; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 = - result__h29129; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28815 or - result__h28842 or - result__h28869 or - result__h28896 or - result__h28923 or - result__h28950 or result__h28977 or result__h29004) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28815; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28842; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28869; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28896; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28923; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28950; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h28977; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 = - result__h29004; - endcase - end - always@(rg_addr or - result__h28579 or - result__h28609 or - result__h28636 or - result__h28663 or - result__h28690 or - result__h28717 or result__h28744 or result__h28771) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28579; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28609; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28636; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28663; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28690; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28717; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28744; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 = - result__h28771; - endcase - end - always@(rg_addr or result__h29290 or result__h29317) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34 = - result__h29290; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34 = - result__h29317; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34 = - 64'd0; - endcase - end - always@(rg_addr or result__h29355 or result__h29382) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35 = - result__h29355; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35 = - result__h29382; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112 or - CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34 or - rg_addr or - master_xactor_rg_rd_data or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120 or - CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35) - begin - case (rg_f3) - 3'b0: - ld_val__h28519 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1084; - 3'b001: - ld_val__h28519 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1112; - 3'b010: - ld_val__h28519 = - CASE_rg_addr_BITS_2_TO_0_0x0_result9290_0x4_re_ETC__q34; - 3'b011: - ld_val__h28519 = - (rg_addr[2:0] == 3'h0) ? master_xactor_rg_rd_data[66:3] : 64'd0; - 3'b100: - ld_val__h28519 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1100; - 3'b101: - ld_val__h28519 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1120; - 3'b110: - ld_val__h28519 = - CASE_rg_addr_BITS_2_TO_0_0x0_result9355_0x4_re_ETC__q35; - 3'd7: ld_val__h28519 = 64'd0; - endcase - end - always@(rg_addr or result__h33511 or result__h33539) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252 = - result__h33511; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252 = - result__h33539; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252 = - 64'd0; - endcase - end - always@(rg_addr or - result__h33319 or - result__h33347 or result__h33375 or result__h33403) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 = - result__h33319; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 = - result__h33347; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 = - result__h33375; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 = - result__h33403; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 = - 64'd0; - endcase - end - always@(rg_addr or - result__h33194 or - result__h33222 or result__h33250 or result__h33278) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 = - result__h33194; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 = - result__h33222; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 = - result__h33250; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 = - result__h33278; - default: IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 = - 64'd0; - endcase - end - always@(rg_addr or - result__h32953 or - result__h32981 or - result__h33009 or - result__h33037 or - result__h33065 or - result__h33093 or result__h33121 or result__h33149) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h32953; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h32981; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33009; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33037; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33065; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33093; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33121; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 = - result__h33149; - endcase - end - always@(rg_addr or - result__h31832 or - result__h32740 or - result__h32768 or - result__h32796 or - result__h32824 or - result__h32852 or result__h32880 or result__h32908) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h31832; - 3'h1: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32740; - 3'h2: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32768; - 3'h3: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32796; - 3'h4: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32824; - 3'h5: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32852; - 3'h6: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32880; - 3'h7: - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 = - result__h32908; - endcase - end - always@(rg_addr or result__h33444 or result__h33472) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50 = - result__h33444; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50 = - result__h33472; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 or - CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252) - begin - case (rg_f3) - 3'b0: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206; - 3'b001: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234; - 3'b010: - w1__h31637 = - CASE_rg_addr_BITS_2_TO_0_0x0_result3444_0x4_re_ETC__q50; - 3'b011: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253; - 3'b100: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222; - 3'b101: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242; - 3'b110: - w1__h31637 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252; - 3'd7: w1__h31637 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 or - w1___1__h31712 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252) - begin - case (rg_f3) - 3'b0: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206; - 3'b001: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234; - 3'b010: w1__h31641 = w1___1__h31712; - 3'b011: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253; - 3'b100: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222; - 3'b101: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242; - 3'b110: - w1__h31641 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252; - 3'd7: w1__h31641 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234 or - w11637_BITS_31_TO_0__q51 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242 or - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252) - begin - case (rg_f3) - 3'b0: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1206; - 3'b001: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1234; - 3'b010: - new_ld_val__h31357 = - { {32{w11637_BITS_31_TO_0__q51[31]}}, - w11637_BITS_31_TO_0__q51 }; - 3'b011: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1253; - 3'b100: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1222; - 3'b101: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1242; - 3'b110: - new_ld_val__h31357 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1252; - 3'd7: new_ld_val__h31357 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h33632 or - new_st_val__h31744 or - w2__h31643 or - new_st_val__h33604 or - new_st_val__h33612 or - new_st_val__h33608 or - new_st_val__h33627 or new_st_val__h33616 or new_st_val__h33621) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h31649 = new_st_val__h31744; - 5'b00001: _theResult_____2__h31649 = w2__h31643; - 5'b00100: _theResult_____2__h31649 = new_st_val__h33604; - 5'b01000: _theResult_____2__h31649 = new_st_val__h33612; - 5'b01100: _theResult_____2__h31649 = new_st_val__h33608; - 5'b10000: _theResult_____2__h31649 = new_st_val__h33627; - 5'b11000: _theResult_____2__h31649 = new_st_val__h33616; - 5'b11100: _theResult_____2__h31649 = new_st_val__h33621; - default: _theResult_____2__h31649 = new_st_val__h33632; - endcase - end - always@(rg_f3 or st_val__h31369 or _theResult___snd_fst__h31632) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h31624 = _theResult___snd_fst__h31632; - 2'd3: mem_req_wr_data_wdata__h31624 = st_val__h31369; - endcase - end - always@(x1_avValue_pa__h6227 or ram_word64_set$DOB or new_st_val__h19386) - begin - case (x1_avValue_pa__h6227[2:0]) - 3'h0: - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - { ram_word64_set$DOB[63:32], new_st_val__h19386[31:0] }; - 3'h4: - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - { new_st_val__h19386[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734 or - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743 or - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52 or - new_st_val__h19386) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d734; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 = - IF_IF_rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_ETC___d743; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 = - CASE_x1_avValue_pa227_BITS_2_TO_0_0x0_ram_word_ETC__q52; - 3'b011: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 = - new_st_val__h19386; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d574) - begin - case (rg_f3) - 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: - new_value__h17651 = - IF_rg_addr_6_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d574; - 3'd7: new_value__h17651 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 7'd0; - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_sb_to_load_delay$EN) - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY - crg_sb_to_load_delay$D_IN; - if (ctr_wr_rsps_pending_crg$EN) - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY - ctr_wr_rsps_pending_crg$D_IN; - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_cset_in_cache$EN) - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN; - if (rg_lower_word32_full$EN) - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY - rg_lower_word32_full$D_IN; - if (rg_lrsc_valid$EN) - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; - if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN; - if (rg_amo_funct7$EN) - rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN; - if (rg_error_during_refill$EN) - rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY - rg_error_during_refill$D_IN; - if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN; - if (rg_lower_word32$EN) - rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN; - if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN; - if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN; - if (rg_priv$EN) rg_priv <= `BSV_ASSIGNMENT_DELAY rg_priv$D_IN; - if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN; - if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_st_amo_val$EN) - rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN; - if (rg_word64_set_in_cache$EN) - rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY - rg_word64_set_in_cache$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_sb_to_load_delay = 11'h2AA; - ctr_wr_rsps_pending_crg = 4'hA; - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; - rg_addr = 32'hAAAAAAAA; - rg_amo_funct7 = 7'h2A; - rg_cset_in_cache = 7'h2A; - rg_error_during_refill = 1'h0; - rg_exc_code = 4'hA; - rg_f3 = 3'h2; - rg_ld_val = 64'hAAAAAAAAAAAAAAAA; - rg_lower_word32 = 32'hAAAAAAAA; - rg_lower_word32_full = 1'h0; - rg_lrsc_pa = 34'h2AAAAAAAA; - rg_lrsc_valid = 1'h0; - rg_mstatus_MXR = 1'h0; - rg_op = 2'h2; - rg_pa = 34'h2AAAAAAAA; - rg_priv = 2'h2; - rg_pte_pa = 34'h2AAAAAAAA; - rg_satp = 32'hAAAAAAAA; - rg_sstatus_SUM = 1'h0; - rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - rg_word64_set_in_cache = 9'h0AA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - begin - v__h4748 = $stime; - #0; - end - v__h4742 = v__h4748 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h4742, - "D_MMU_Cache", - $signed(32'd128), - $signed(32'd1)); - else - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h4742, - "I_MMU_Cache", - $signed(32'd128), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - !cfg_verbosity_read__5_ULE_1___d26 && - f_reset_reqs$D_OUT) - begin - v__h4849 = $stime; - #0; - end - v__h4843 = v__h4849 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - !cfg_verbosity_read__5_ULE_1___d26 && - f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: Flushed", v__h4843, "D_MMU_Cache"); - else - $display("%0d: %s.rl_reset: Flushed", v__h4843, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_rereq && !cfg_verbosity_read__5_ULE_1___d26) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - rg_addr[11:5], - rg_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h29722 = $stime; - #0; - end - v__h29716 = v__h29722 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29716, - "D_MMU_Cache", - rg_addr, - rg_ld_val); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29716, - "I_MMU_Cache", - rg_addr, - rg_ld_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h30620 = $stime; - #0; - end - v__h30614 = v__h30620 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h30614, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h30614, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__5_ULE_1___d26) - $display(" FAIL due to I/O address."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__5_ULE_1___d26) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h4385 = $stime; - #0; - end - v__h4379 = v__h4385 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_start_reset", v__h4379, "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_reset", v__h4379, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h5300 = $stime; - #0; - end - v__h5294 = v__h5300 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h5294, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h5294, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - rg_satp[31]) - $display(" Priv:%0d SATP:{mode %0d asid %0h pa %0h} VA:%0h.%0h.%0h", - rg_priv, - rg_satp[31], - rg_satp[30:22], - satp_pa__h2468, - rg_addr[31:22], - rg_addr[21:12], - rg_addr[11:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", - { 2'd0, rg_addr[31:12] }, - rg_addr[11:5], - rg_addr[4:3], - rg_addr[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" CSet 0x%0x: (state, tag):", rg_addr[11:5]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" ("); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - ram_state_and_ctag_cset$DOB[22]) - $write("CTAG_CLEAN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - !ram_state_and_ctag_cset$DOB[22]) - $write("CTAG_EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - ram_state_and_ctag_cset$DOB[22]) - $write(", 0x%0x", ram_state_and_ctag_cset$DOB[21:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - !ram_state_and_ctag_cset$DOB[22]) - $write(", --"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(")"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" TLB result: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d350) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d353) - $write("VM_XLATE_EXCEPTION"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - rg_priv_6_ULE_0b1___d67 && - rg_satp[31] && - !tlb$lookup[68]) - $write("VM_XLATE_TLB_MISS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", x1_avValue_exc_code__h6228); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "pte_modified: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d365) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", x1_avValue_pte__h6230, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $display(" fa_record_pte_A_D_updates:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("TLB_Lookup_Result { ", "hit: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", tlb$lookup[67:36]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pte_level: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", tlb$lookup[35:34]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pte_pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", tlb$lookup[33:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d411) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d414) - $write("VM_XLATE_EXCEPTION"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", x1_avValue_exc_code__h6228); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pte_modified: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d414) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d411) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("'h%h", x1_avValue_pte__h6230, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_6_ULE_0b1_7_AND_rg_satp_9_BIT_31_0_4_A_ETC___d375 && - NOT_cfg_verbosity_read__5_ULT_2_02___d403) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d428) - $display(" => IO_REQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d588) - begin - v__h14916 = $stime; - #0; - end - v__h14910 = v__h14916 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d588) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h14910, - "D_MMU_Cache", - rg_addr, - word64__h7440, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h14910, - "I_MMU_Cache", - rg_addr, - word64__h7440, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d601) - $display(" AMO LR: reserving PA 0x%0h", x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d588) - $display(" Read-hit: addr 0x%0h word64 0x%0h", - rg_addr, - word64__h7440); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d607) - $display(" Read Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d613) - $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", - rg_lrsc_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d797) - $display(" ST: cancelling LR/SC reservation for PA", - x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d803) - $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", - rg_lrsc_pa, - x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d809) - $display(" AMO SC: fail due to invalid LR/SC reservation"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d815) - $display(" AMO SC result = %0d", lrsc_result__h15293); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821) - $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", - x1_avValue_pa__h6227, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821) - $write(" 0x%0x", - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d687); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d821) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_6_ULE_0b1___d67 || !rg_satp[31] || tlb$lookup[68]) && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d826) - $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", - x1_avValue_pa__h6227, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d839) - begin - v__h19135 = $stime; - #0; - end - v__h19129 = v__h19135 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d839) - $display("%0d: ERROR: CreditCounter: overflow", v__h19129); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d839) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", addr__h7263); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", value__h33968); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", mem_req_wr_data_wdata__h18931); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", mem_req_wr_data_wstrb__h18932); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d833) - $display(" => rl_write_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d847) - begin - v__h18560 = $stime; - #0; - end - v__h18554 = v__h18560 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d847) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h18554, - "D_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h18554, - "I_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d847) - $display(" AMO SC: Fail response for addr 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d854) - $display(" AMO Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", - rg_addr, - rg_amo_funct7, - rg_f3, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $display(" PA 0x%0h ", x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $display(" Cache word64 0x%0h, load-result 0x%0h", - word64__h7440, - word64__h7440); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $display(" 0x%0h op 0x%0h -> 0x%0h", - word64__h7440, - word64__h7440, - new_st_val__h19386); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(" 0x%0x", - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_6_ULE_ETC___d752); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d865) - begin - v__h22571 = $stime; - #0; - end - v__h22565 = v__h22571 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d865) - $display("%0d: ERROR: CreditCounter: overflow", v__h22565); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d865) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", addr__h7263); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", value__h33968); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", mem_req_wr_data_wdata__h22367); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", mem_req_wr_data_wstrb__h18932); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d859) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_6_ULE_0b1_7_8_OR_NOT_rg_satp_9_BIT_ETC___d873) - $display(" AMO_op: cancelling LR/SC reservation for PA", - x1_avValue_pa__h6227); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935) - begin - v__h24184 = $stime; - #0; - end - v__h24178 = v__h24184 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h24178, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h24178, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - begin - v__h23942 = $stime; - #0; - end - v__h23936 = v__h23942 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - if (dmem_not_imem) - $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0", - v__h23936, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - else - $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0", - v__h23936, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $display(" Req for level 0 PTE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", lev_0_pte_pa_w64_fa__h24218); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d962) - begin - v__h24605 = $stime; - #0; - end - v__h24599 = v__h24605 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d962) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage", - v__h24599, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage", - v__h24599, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d962) - $display(" Addr Space megapage pa: 0x%0h", lev_0_PTN_pa__h24214); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d968) - begin - v__h24493 = $stime; - #0; - end - v__h24487 = v__h24493 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d968) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h", - v__h24487, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h", - v__h24487, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - _theResult____h23570[0] && - (_theResult____h23570[1] || !_theResult____h23570[2]) && - (_theResult____h23570[3] || _theResult____h23570[1]) && - _theResult____h23570[19:10] != 10'd0) - $display(" Invalid PTE: PPN [0] is not zero; page fault %0d", - exc_code___1__h6589); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h24113 = $stime; - #0; - end - v__h24107 = v__h24113 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h24107, - "D_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3148); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h24107, - "I_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935) - begin - v__h25145 = $stime; - #0; - end - v__h25139 = v__h25145 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d935) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h25139, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h25139, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - begin - v__h25216 = $stime; - #0; - end - v__h25210 = v__h25216 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d943) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d", - v__h25210, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d", - v__h25210, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa, - exc_code___1__h6589); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d994) - begin - v__h25298 = $stime; - #0; - end - v__h25292 = v__h25298 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d994) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE", - v__h25292, - "D_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE", - v__h25292, - "I_MMU_Cache", - rg_addr, - _theResult____h23570, - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_94_BITS_2_TO_1_95_EQ__ETC___d994) - $display(" Addr Space page pa: 0x%0h", lev_0_PTN_pa__h24214); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h25074 = $stime; - #0; - end - v__h25068 = v__h25074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h25068, - "D_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3148); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h25068, - "I_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - begin - v__h26206 = $stime; - #0; - end - v__h26200 = v__h26206 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h26200, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h26200, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h26428 = $stime; - #0; - end - v__h26422 = v__h26428 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h26422, - "D_MMU_Cache", - access_exc_code__h3148); - else - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h26422, - "I_MMU_Cache", - access_exc_code__h3148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 && - (master_xactor_rg_rd_data[2:1] != 2'b0 || rg_error_during_refill) && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" => MODULE_EXCEPTION_RSP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !rg_error_during_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" => CACHE_REREQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", - rg_word64_set_in_cache, - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write(" 0x%0x", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__5_ULE_2_014___d1015) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h28410 = $stime; - #0; - end - v__h28404 = v__h28410 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h28404, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h28404, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h29510 = $stime; - #0; - end - v__h29504 = v__h29510 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29504, - "D_MMU_Cache", - rg_addr, - ld_val__h28519); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29504, - "I_MMU_Cache", - rg_addr, - ld_val__h28519); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h29617 = $stime; - #0; - end - v__h29611 = v__h29617 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h29611, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h29611, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h29802 = $stime; - #0; - end - v__h29796 = v__h29802 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h29796, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h29796, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h30324 = $stime; - #0; - end - v__h30318 = v__h30324 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h30318); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_addr_awaddr__h31419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", value__h33968); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wdata__h30120); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wstrb__h31625); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__5_ULE_1___d26) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h30738 = $stime; - #0; - end - v__h30732 = v__h30738 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h30732, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h30732, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_addr_awaddr__h31419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", value__h30942); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h3751 = $stime; - #0; - end - v__h3745 = v__h3751 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h3745); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_addr_awaddr__h3403); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'b010); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wdata__h3595); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wstrb__h3596); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h31056 = $stime; - #0; - end - v__h31050 = v__h31056 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h31050, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h31050, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h31231 = $stime; - #0; - end - v__h31225 = v__h31231 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h31225, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h31225, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h33844 = $stime; - #0; - end - v__h33838 = v__h33844 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h33838); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_addr_awaddr__h31419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", value__h33968); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wdata__h31624); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_data_wstrb__h31625); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h34096 = $stime; - #0; - end - v__h34090 = v__h34096 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h34090, - "D_MMU_Cache", - rg_addr, - new_ld_val__h31357); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h34090, - "I_MMU_Cache", - rg_addr, - new_ld_val__h31357); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h31327 = $stime; - #0; - end - v__h31321 = v__h31327 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h31321, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h31321, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h23206 = $stime; - #0; - end - v__h23200 = v__h23206 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 1 PTE", - v__h23200, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 1 PTE", - v__h23200, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", lev_1_pte_pa_w64_fa__h23261); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'b010); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h25423 = $stime; - #0; - end - v__h25417 = v__h25423 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_start_cache_refill: ", - v__h25417, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_cache_refill: ", - v__h25417, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", cline_fabric_addr__h25476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" Victim way %0d; => CACHE_REFILL", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h28036 = $stime; - #0; - end - v__h28030 = v__h28036 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h28030, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h28030, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", mem_req_wr_addr_awaddr__h31419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", value__h30942); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h35065 = $stime; - #0; - end - v__h35059 = v__h35065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $write("%0d: %s.req: op:", v__h35059, "D_MMU_Cache"); - else - $write("%0d: %s.req: op:", v__h35059, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_op == 2'd0) - $write("CACHE_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_op == 2'd1) - $write("CACHE_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_op != 2'd0 && - req_op != 2'd1) - $write("CACHE_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", - req_f3, - req_addr, - req_st_value); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_priv == 2'b0) - $write("U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_priv == 2'b01) - $write("S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_priv == 2'b11) - $write("M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26 && req_priv != 2'b0 && - req_priv != 2'b01 && - req_priv != 2'b11) - $write("RESERVED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26) - $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__5_ULE_1___d26) - $display(" amo_funct7 = 0x%0h", req_amo_funct7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && - req_f3_BITS_1_TO_0_344_EQ_0b0_345_OR_req_f3_BI_ETC___d1374 && - !cfg_verbosity_read__5_ULE_1___d26) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - req_addr[11:5], - req_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_tlb_flush && !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h36219 = $stime; - #0; - end - v__h36213 = v__h36219 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_tlb_flush && !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $display("%0d: %s.tlb_flush", v__h36213, "D_MMU_Cache"); - else - $display("%0d: %s.tlb_flush", v__h36213, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - begin - v__h34716 = $stime; - #0; - end - v__h34710 = v__h34716 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - if (dmem_not_imem) - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h34710, - "D_MMU_Cache", - $unsigned(b__h23160)); - else - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h34710, - "I_MMU_Cache", - $unsigned(b__h23160)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__5_ULE_1___d26) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - begin - v__h34677 = $stime; - #0; - end - v__h34671 = v__h34677 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - if (dmem_not_imem) - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h34671, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h34671, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("\n"); - end - // synopsys translate_on -endmodule // mkMMU_Cache - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v deleted file mode 100644 index f673c615..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v +++ /dev/null @@ -1,2169 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// to_raw_mem_response_put I 256 -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_to_raw_mem_response_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Controller(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [63 : 0] slave_rdata; - wire [7 : 0] status; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // inlined wires - reg [353 : 0] f_raw_mem_reqs_rv$port1__write_1; - wire [353 : 0] f_raw_mem_reqs_rv$port1__read, - f_raw_mem_reqs_rv$port2__read, - f_raw_mem_reqs_rv$port3__read; - wire [256 : 0] f_raw_mem_rsps_rv$port1__read, - f_raw_mem_rsps_rv$port1__write_1, - f_raw_mem_rsps_rv$port2__read, - f_raw_mem_rsps_rv$port3__read; - wire [170 : 0] f_reqs_rv$port1__read, - f_reqs_rv$port1__write_1, - f_reqs_rv$port2__read; - wire f_raw_mem_reqs_rv$EN_port1__write, - f_reqs_rv$EN_port0__write, - f_reqs_rv$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register f_raw_mem_reqs_rv - reg [353 : 0] f_raw_mem_reqs_rv; - wire [353 : 0] f_raw_mem_reqs_rv$D_IN; - wire f_raw_mem_reqs_rv$EN; - - // register f_raw_mem_rsps_rv - reg [256 : 0] f_raw_mem_rsps_rv; - wire [256 : 0] f_raw_mem_rsps_rv$D_IN; - wire f_raw_mem_rsps_rv$EN; - - // register f_reqs_rv - reg [170 : 0] f_reqs_rv; - wire [170 : 0] f_reqs_rv$D_IN; - wire f_reqs_rv$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_cached_clean - reg rg_cached_clean; - wire rg_cached_clean$D_IN, rg_cached_clean$EN; - - // register rg_cached_raw_mem_addr - reg [63 : 0] rg_cached_raw_mem_addr; - wire [63 : 0] rg_cached_raw_mem_addr$D_IN; - wire rg_cached_raw_mem_addr$EN; - - // register rg_cached_raw_mem_word - reg [255 : 0] rg_cached_raw_mem_word; - wire [255 : 0] rg_cached_raw_mem_word$D_IN; - wire rg_cached_raw_mem_word$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_status - reg [7 : 0] rg_status; - wire [7 : 0] rg_status$D_IN; - wire rg_status$EN; - - // register rg_tohost_addr - reg [63 : 0] rg_tohost_addr; - wire [63 : 0] rg_tohost_addr$D_IN; - wire rg_tohost_addr$EN; - - // register rg_watch_tohost - reg rg_watch_tohost; - wire rg_watch_tohost$D_IN, rg_watch_tohost$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_external_reset, - CAN_FIRE_RL_rl_invalid_rd_address, - CAN_FIRE_RL_rl_invalid_wr_address, - CAN_FIRE_RL_rl_merge_rd_req, - CAN_FIRE_RL_rl_merge_wr_req, - CAN_FIRE_RL_rl_miss_clean_req, - CAN_FIRE_RL_rl_power_on_reset, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reload, - CAN_FIRE_RL_rl_reset_reload_cache, - CAN_FIRE_RL_rl_writeback_dirty, - CAN_FIRE_RL_rl_writeback_dirty_idle, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_external_reset, - WILL_FIRE_RL_rl_invalid_rd_address, - WILL_FIRE_RL_rl_invalid_wr_address, - WILL_FIRE_RL_rl_merge_rd_req, - WILL_FIRE_RL_rl_merge_wr_req, - WILL_FIRE_RL_rl_miss_clean_req, - WILL_FIRE_RL_rl_power_on_reset, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reload, - WILL_FIRE_RL_rl_reset_reload_cache, - WILL_FIRE_RL_rl_writeback_dirty, - WILL_FIRE_RL_rl_writeback_dirty_idle, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire [353 : 0] MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1, - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - wire [255 : 0] MUX_rg_cached_raw_mem_word$write_1__VAL_1; - wire [170 : 0] MUX_f_reqs_rv$port1__write_1__VAL_1, - MUX_f_reqs_rv$port1__write_1__VAL_2; - wire [70 : 0] MUX_slave_xactor_f_rd_data$enq_1__VAL_1, - MUX_slave_xactor_f_rd_data$enq_1__VAL_2; - wire [5 : 0] MUX_slave_xactor_f_wr_resp$enq_1__VAL_1, - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2; - wire MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2538; - reg [31 : 0] v__h3481; - reg [31 : 0] v__h3974; - reg [31 : 0] v__h4443; - reg [31 : 0] v__h4706; - reg [31 : 0] v__h5425; - reg [31 : 0] v__h7622; - reg [31 : 0] v__h7823; - reg [31 : 0] v__h8335; - reg [31 : 0] v__h9119; - reg [31 : 0] v__h9714; - reg [31 : 0] v__h2853; - reg [31 : 0] v__h3193; - reg [31 : 0] v__h1743; - reg [31 : 0] v__h2088; - reg [31 : 0] v__h1737; - reg [31 : 0] v__h2082; - reg [31 : 0] v__h2532; - reg [31 : 0] v__h2847; - reg [31 : 0] v__h3187; - reg [31 : 0] v__h3475; - reg [31 : 0] v__h3968; - reg [31 : 0] v__h4437; - reg [31 : 0] v__h4700; - reg [31 : 0] v__h5419; - reg [31 : 0] v__h7616; - reg [31 : 0] v__h7817; - reg [31 : 0] v__h8329; - reg [31 : 0] v__h9113; - reg [31 : 0] v__h9708; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rdata__h5068, word64_old__h5862; - wire [63 : 0] exit_value__h7860, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1, - mask__h5867, - req_raw_mem_addr__h3314, - updated_word64__h5868, - x__h6241, - y__h6242, - y__h6243; - wire [7 : 0] SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191; - wire [4 : 0] n__h5067; - wire NOT_cfg_verbosity_read_ULE_1___d5, - NOT_cfg_verbosity_read_ULE_2_2___d33, - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279, - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128, - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123, - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126, - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135, - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284, - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131, - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = rg_state == 2'd3 ; - assign CAN_FIRE_set_addr_map = rg_state == 2'd3 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = f_raw_mem_reqs_rv[352:0] ; - assign RDY_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign CAN_FIRE_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = !f_raw_mem_rsps_rv$port1__read[256] ; - assign CAN_FIRE_to_raw_mem_response_put = - !f_raw_mem_rsps_rv$port1__read[256] ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // value method status - assign status = rg_status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset_reload_cache - assign CAN_FIRE_RL_rl_reset_reload_cache = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_reload_cache = - CAN_FIRE_RL_rl_reset_reload_cache ; - - // rule RL_rl_writeback_dirty_idle - assign CAN_FIRE_RL_rl_writeback_dirty_idle = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd3 && - !f_reqs_rv[170] && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty_idle = - CAN_FIRE_RL_rl_writeback_dirty_idle ; - - // rule RL_rl_writeback_dirty - assign CAN_FIRE_RL_rl_writeback_dirty = - !f_raw_mem_reqs_rv$port1__read[353] && f_reqs_rv[170] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty = CAN_FIRE_RL_rl_writeback_dirty ; - - // rule RL_rl_miss_clean_req - assign CAN_FIRE_RL_rl_miss_clean_req = - f_reqs_rv[170] && !f_raw_mem_reqs_rv$port1__read[353] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - rg_cached_clean ; - assign WILL_FIRE_RL_rl_miss_clean_req = - CAN_FIRE_RL_rl_miss_clean_req && - !WILL_FIRE_RL_rl_external_reset && - !EN_set_addr_map ; - - // rule RL_rl_reload - assign CAN_FIRE_RL_rl_reload = f_raw_mem_rsps_rv[256] && rg_state == 2'd2 ; - assign WILL_FIRE_RL_rl_reload = CAN_FIRE_RL_rl_reload ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_invalid_rd_address - assign CAN_FIRE_RL_rl_invalid_rd_address = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_rd_address = - CAN_FIRE_RL_rl_invalid_rd_address ; - - // rule RL_rl_invalid_wr_address - assign CAN_FIRE_RL_rl_invalid_wr_address = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_wr_address = - CAN_FIRE_RL_rl_invalid_wr_address ; - - // rule RL_rl_merge_rd_req - assign CAN_FIRE_RL_rl_merge_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && !f_reqs_rv$port1__read[170] ; - assign WILL_FIRE_RL_rl_merge_rd_req = CAN_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_merge_wr_req - assign CAN_FIRE_RL_rl_merge_wr_req = - !f_reqs_rv$port1__read[170] && slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N ; - assign WILL_FIRE_RL_rl_merge_wr_req = - CAN_FIRE_RL_rl_merge_wr_req && !WILL_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_power_on_reset - assign CAN_FIRE_RL_rl_power_on_reset = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_power_on_reset = CAN_FIRE_RL_rl_power_on_reset ; - - // rule RL_rl_external_reset - assign CAN_FIRE_RL_rl_external_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && rg_state == 2'd3 ; - assign WILL_FIRE_RL_rl_external_reset = CAN_FIRE_RL_rl_external_reset ; - - // inputs to muxes for submodule ports - assign MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - assign MUX_rg_state$write_1__SEL_1 = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - assign MUX_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 = - { 34'h3FFFFFFFF, - rg_cached_raw_mem_addr, - rg_cached_raw_mem_word } ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3 = - { 34'h2FFFFFFFF, - req_raw_mem_addr__h3314, - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_1 = - { 2'd2, slave_xactor_f_rd_addr$D_OUT, 72'hAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_2 = - { 2'd3, - slave_xactor_f_wr_addr$D_OUT, - slave_xactor_f_wr_data$D_OUT[8:1], - slave_xactor_f_wr_data$D_OUT[72:9] } ; - assign MUX_rg_cached_raw_mem_word$write_1__VAL_1 = - { (f_reqs_rv[105:104] == 2'd3) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[255:192], - (f_reqs_rv[105:104] == 2'd2) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[191:128], - (f_reqs_rv[105:104] == 2'd1) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[127:64], - (f_reqs_rv[105:104] == 2'd0) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[63:0] } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_1 = - { f_reqs_rv[168:165], rdata__h5068, 3'd1 } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_2 = - { f_reqs_rv[168:101], 3'd5 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 = - { f_reqs_rv[168:165], 2'd0 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 = - { f_reqs_rv[168:165], 2'd2 } ; - - // inlined wires - assign f_reqs_rv$EN_port0__write = - WILL_FIRE_RL_rl_invalid_wr_address || - WILL_FIRE_RL_rl_invalid_rd_address || - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs_rv$port1__read = - f_reqs_rv$EN_port0__write ? - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_reqs_rv ; - assign f_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_merge_rd_req || WILL_FIRE_RL_rl_merge_wr_req ; - assign f_reqs_rv$port1__write_1 = - WILL_FIRE_RL_rl_merge_rd_req ? - MUX_f_reqs_rv$port1__write_1__VAL_1 : - MUX_f_reqs_rv$port1__write_1__VAL_2 ; - assign f_reqs_rv$port2__read = - f_reqs_rv$EN_port1__write ? - f_reqs_rv$port1__write_1 : - f_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port1__read = - EN_to_raw_mem_request_get ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv ; - assign f_raw_mem_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_miss_clean_req ; - always@(MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 or - WILL_FIRE_RL_rl_reset_reload_cache or - WILL_FIRE_RL_rl_miss_clean_req or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1; - WILL_FIRE_RL_rl_reset_reload_cache: - f_raw_mem_reqs_rv$port1__write_1 = - 354'h2FFFFFFFF0000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_miss_clean_req: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - default: f_raw_mem_reqs_rv$port1__write_1 = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign f_raw_mem_reqs_rv$port2__read = - f_raw_mem_reqs_rv$EN_port1__write ? - f_raw_mem_reqs_rv$port1__write_1 : - f_raw_mem_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv$port2__read ; - assign f_raw_mem_rsps_rv$port1__read = - CAN_FIRE_RL_rl_reload ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv ; - assign f_raw_mem_rsps_rv$port1__write_1 = - { 1'd1, to_raw_mem_response_put } ; - assign f_raw_mem_rsps_rv$port2__read = - EN_to_raw_mem_response_put ? - f_raw_mem_rsps_rv$port1__write_1 : - f_raw_mem_rsps_rv$port1__read ; - assign f_raw_mem_rsps_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv$port2__read ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register f_raw_mem_reqs_rv - assign f_raw_mem_reqs_rv$D_IN = f_raw_mem_reqs_rv$port3__read ; - assign f_raw_mem_reqs_rv$EN = 1'b1 ; - - // register f_raw_mem_rsps_rv - assign f_raw_mem_rsps_rv$D_IN = f_raw_mem_rsps_rv$port3__read ; - assign f_raw_mem_rsps_rv$EN = 1'b1 ; - - // register f_reqs_rv - assign f_reqs_rv$D_IN = f_reqs_rv$port2__read ; - assign f_reqs_rv$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_cached_clean - assign rg_cached_clean$D_IN = !WILL_FIRE_RL_rl_process_wr_req ; - assign rg_cached_clean$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload || - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - - // register rg_cached_raw_mem_addr - assign rg_cached_raw_mem_addr$D_IN = - WILL_FIRE_RL_rl_miss_clean_req ? - req_raw_mem_addr__h3314 : - 64'd0 ; - assign rg_cached_raw_mem_addr$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_cached_raw_mem_word - assign rg_cached_raw_mem_word$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_rg_cached_raw_mem_word$write_1__VAL_1 : - f_raw_mem_rsps_rv[255:0] ; - assign rg_cached_raw_mem_word$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload ; - - // register rg_state - always@(MUX_rg_state$write_1__SEL_1 or - MUX_rg_state$write_1__SEL_2 or WILL_FIRE_RL_rl_reload) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_state$write_1__SEL_1: rg_state$D_IN = 2'd1; - MUX_rg_state$write_1__SEL_2: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reload: rg_state$D_IN = 2'd3; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset || - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_reload ; - - // register rg_status - assign rg_status$D_IN = - (WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset) ? - 8'd0 : - 8'd1 ; - assign rg_status$EN = - WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 || - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - - // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_watch_tohost ; - - // register rg_watch_tohost - assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ; - assign rg_watch_tohost$EN = EN_set_watch_tohost ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_merge_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_slave_xactor_f_rd_data$enq_1__VAL_1 : - MUX_slave_xactor_f_rd_data$enq_1__VAL_2 ; - assign slave_xactor_f_rd_data$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_invalid_rd_address ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 : - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 ; - assign slave_xactor_f_wr_resp$ENQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_invalid_wr_address ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_1 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d5 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read_ULE_2_2___d33 = cfg_verbosity > 4'd2 ; - assign NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 = - f_reqs_rv[92:90] != 3'b0 && - (f_reqs_rv[92:90] != 3'b001 || f_reqs_rv[101]) && - (f_reqs_rv[92:90] != 3'b010 || f_reqs_rv[102:101] != 2'h0) && - (f_reqs_rv[92:90] != 3'b011 || f_reqs_rv[103:101] != 3'h0) && - (f_reqs_rv[92:90] != 3'b100 || f_reqs_rv[104:101] != 4'h0) && - (f_reqs_rv[92:90] != 3'b101 || f_reqs_rv[105:101] != 5'h0) && - (f_reqs_rv[92:90] != 3'b110 || f_reqs_rv[106:101] != 6'h0) && - (f_reqs_rv[92:90] != 3'b111 || f_reqs_rv[107:101] != 7'h0) ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 = {8{f_reqs_rv[64]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212 = {8{f_reqs_rv[65]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208 = {8{f_reqs_rv[66]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205 = {8{f_reqs_rv[67]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201 = {8{f_reqs_rv[68]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198 = {8{f_reqs_rv[69]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194 = {8{f_reqs_rv[70]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191 = {8{f_reqs_rv[71]}} ; - assign exit_value__h7860 = { 1'd0, f_reqs_rv[63:1] } ; - assign f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1 = - f_reqs_rv[164:101] - rg_addr_base ; - assign f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 = - f_reqs_rv[164:101] < rg_addr_lim ; - assign f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 = - f_reqs_rv[92:90] == 3'b0 || - f_reqs_rv[92:90] == 3'b001 && !f_reqs_rv[101] || - f_reqs_rv[92:90] == 3'b010 && f_reqs_rv[102:101] == 2'h0 || - f_reqs_rv[92:90] == 3'b011 && f_reqs_rv[103:101] == 3'h0 || - f_reqs_rv[92:90] == 3'b100 && f_reqs_rv[104:101] == 4'h0 || - f_reqs_rv[92:90] == 3'b101 && f_reqs_rv[105:101] == 5'h0 || - f_reqs_rv[92:90] == 3'b110 && f_reqs_rv[106:101] == 6'h0 || - f_reqs_rv[92:90] == 3'b111 && f_reqs_rv[107:101] == 7'h0 ; - assign mask__h5867 = - { SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - assign n__h5067 = { 3'd0, f_reqs_rv[105:104] } ; - assign req_raw_mem_addr__h3314 = - { 5'd0, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1[63:5] } ; - assign rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 = - rg_addr_base <= f_reqs_rv[164:101] ; - assign rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 = - rg_cached_raw_mem_addr == req_raw_mem_addr__h3314 ; - assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 = - rg_state == 2'd3 && - (NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 || - !rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 || - !f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128) ; - assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 = - rg_state == 2'd3 && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 && - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 && - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 ; - assign rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 = - rg_watch_tohost && f_reqs_rv[164:101] == rg_tohost_addr && - f_reqs_rv[63:0] != 64'd0 ; - assign updated_word64__h5868 = x__h6241 | y__h6242 ; - assign x__h6241 = word64_old__h5862 & y__h6243 ; - assign y__h6242 = f_reqs_rv[63:0] & mask__h5867 ; - assign y__h6243 = - { ~SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - ~SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - ~SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - ~SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - ~SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - ~SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - ~SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - ~SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - always@(f_reqs_rv or rg_cached_raw_mem_word) - begin - case (f_reqs_rv[105:104]) - 2'd0: word64_old__h5862 = rg_cached_raw_mem_word[63:0]; - 2'd1: word64_old__h5862 = rg_cached_raw_mem_word[127:64]; - 2'd2: word64_old__h5862 = rg_cached_raw_mem_word[191:128]; - 2'd3: word64_old__h5862 = rg_cached_raw_mem_word[255:192]; - endcase - end - always@(n__h5067 or rg_cached_raw_mem_word) - begin - case (n__h5067) - 5'd0: rdata__h5068 = rg_cached_raw_mem_word[63:0]; - 5'd1: rdata__h5068 = rg_cached_raw_mem_word[127:64]; - 5'd2: rdata__h5068 = rg_cached_raw_mem_word[191:128]; - 5'd3: rdata__h5068 = rg_cached_raw_mem_word[255:192]; - default: rdata__h5068 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - rg_status <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000; - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (f_raw_mem_reqs_rv$EN) - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_reqs_rv$D_IN; - if (f_raw_mem_rsps_rv$EN) - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_rsps_rv$D_IN; - if (f_reqs_rv$EN) f_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_reqs_rv$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_status$EN) rg_status <= `BSV_ASSIGNMENT_DELAY rg_status$D_IN; - if (rg_tohost_addr$EN) - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; - if (rg_watch_tohost$EN) - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_cached_clean$EN) - rg_cached_clean <= `BSV_ASSIGNMENT_DELAY rg_cached_clean$D_IN; - if (rg_cached_raw_mem_addr$EN) - rg_cached_raw_mem_addr <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_addr$D_IN; - if (rg_cached_raw_mem_word$EN) - rg_cached_raw_mem_word <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_word$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - f_raw_mem_reqs_rv = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv = 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_cached_clean = 1'h0; - rg_cached_raw_mem_addr = 64'hAAAAAAAAAAAAAAAA; - rg_cached_raw_mem_word = - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state = 2'h2; - rg_status = 8'hAA; - rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; - rg_watch_tohost = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2538 = $stime; - #0; - end - v__h2532 = v__h2538 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING", - v__h2532); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3481 = $stime; - #0; - end - v__h3475 = v__h3481 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h", - v__h3475, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3974 = $stime; - #0; - end - v__h3968 = v__h3974 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h", - v__h3968, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4443 = $stime; - #0; - end - v__h4437 = v__h4443 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h", - v__h4437, - req_raw_mem_addr__h3314); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_reload: raw addr 0x%0h", - v__h4700, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", f_raw_mem_rsps_rv[255:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h5425 = $stime; - #0; - end - v__h5419 = v__h5425 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", rdata__h5068); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h7622 = $stime; - #0; - end - v__h7616 = v__h7622 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7616); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - begin - v__h7823 = $stime; - #0; - end - v__h7817 = v__h7823 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - $display("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h () data 0x%0h", - v__h7817, - f_reqs_rv[164:101], - f_reqs_rv[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] == 63'd0) - $display("PASS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] != 63'd0) - $display("FAIL %0d", exit_value__h7860); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - begin - v__h8335 = $stime; - #0; - end - v__h8329 = v__h8335 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("%0d: ERROR: Mem_Controller:", v__h8329); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" read-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" read-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - begin - v__h9119 = $stime; - #0; - end - v__h9113 = v__h9119 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("%0d: ERROR: Mem_Controller:", v__h9113); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" write-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" write-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - begin - v__h9714 = $stime; - #0; - end - v__h9708 = v__h9714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - $display("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9708, - set_addr_map_addr_base, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h2853 = $stime; - #0; - end - v__h2847 = v__h2853 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_rd_req", v__h2847); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3193 = $stime; - #0; - end - v__h3187 = v__h3193 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_wr_req", v__h3187); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h1743 = $stime; - #0; - end - v__h1737 = v__h1743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_power_on_reset", v__h1737); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2088 = $stime; - #0; - end - v__h2082 = v__h2088 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE", - v__h2082); - end - // synopsys translate_on -endmodule // mkMem_Controller - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v deleted file mode 100644 index 104c51b0..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v +++ /dev/null @@ -1,192 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_mem_server_request_put O 1 reg -// mem_server_response_get O 256 reg -// RDY_mem_server_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// mem_server_request_put I 353 -// EN_mem_server_request_put I 1 -// EN_mem_server_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Model(CLK, - RST_N, - - mem_server_request_put, - EN_mem_server_request_put, - RDY_mem_server_request_put, - - EN_mem_server_response_get, - mem_server_response_get, - RDY_mem_server_response_get); - input CLK; - input RST_N; - - // action method mem_server_request_put - input [352 : 0] mem_server_request_put; - input EN_mem_server_request_put; - output RDY_mem_server_request_put; - - // actionvalue method mem_server_response_get - input EN_mem_server_response_get; - output [255 : 0] mem_server_response_get; - output RDY_mem_server_response_get; - - // signals for module outputs - wire [255 : 0] mem_server_response_get; - wire RDY_mem_server_request_put, RDY_mem_server_response_get; - - // ports of submodule f_raw_mem_rsps - wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT; - wire f_raw_mem_rsps$CLR, - f_raw_mem_rsps$DEQ, - f_raw_mem_rsps$EMPTY_N, - f_raw_mem_rsps$ENQ, - f_raw_mem_rsps$FULL_N; - - // ports of submodule rf - wire [255 : 0] rf$D_IN, rf$D_OUT_1; - wire [63 : 0] rf$ADDR_1, - rf$ADDR_2, - rf$ADDR_3, - rf$ADDR_4, - rf$ADDR_5, - rf$ADDR_IN; - wire rf$WE; - - // rule scheduling signals - wire CAN_FIRE_mem_server_request_put, - CAN_FIRE_mem_server_response_get, - WILL_FIRE_mem_server_request_put, - WILL_FIRE_mem_server_response_get; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h371; - reg [31 : 0] v__h365; - // synopsys translate_on - - // remaining internal signals - wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2; - - // action method mem_server_request_put - assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ; - - // actionvalue method mem_server_response_get - assign mem_server_response_get = f_raw_mem_rsps$D_OUT ; - assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ; - - // submodule f_raw_mem_rsps - FIFO2 #(.width(32'd256), .guarded(32'd1)) f_raw_mem_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_raw_mem_rsps$D_IN), - .ENQ(f_raw_mem_rsps$ENQ), - .DEQ(f_raw_mem_rsps$DEQ), - .CLR(f_raw_mem_rsps$CLR), - .D_OUT(f_raw_mem_rsps$D_OUT), - .FULL_N(f_raw_mem_rsps$FULL_N), - .EMPTY_N(f_raw_mem_rsps$EMPTY_N)); - - // submodule rf - RegFileLoad #(.file("Mem.hex"), - .addr_width(32'd64), - .data_width(32'd256), - .lo(64'd0), - .hi(64'd8388607), - .binary(1'd0)) rf(.CLK(CLK), - .ADDR_1(rf$ADDR_1), - .ADDR_2(rf$ADDR_2), - .ADDR_3(rf$ADDR_3), - .ADDR_4(rf$ADDR_4), - .ADDR_5(rf$ADDR_5), - .ADDR_IN(rf$ADDR_IN), - .D_IN(rf$D_IN), - .WE(rf$WE), - .D_OUT_1(rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule f_raw_mem_rsps - assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ; - assign f_raw_mem_rsps$ENQ = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - !mem_server_request_put[352] ; - assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ; - assign f_raw_mem_rsps$CLR = 1'b0 ; - - // submodule rf - assign rf$ADDR_1 = mem_server_request_put[319:256] ; - assign rf$ADDR_2 = 64'h0 ; - assign rf$ADDR_3 = 64'h0 ; - assign rf$ADDR_4 = 64'h0 ; - assign rf$ADDR_5 = 64'h0 ; - assign rf$ADDR_IN = mem_server_request_put[319:256] ; - assign rf$D_IN = mem_server_request_put[255:0] ; - assign rf$WE = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - mem_server_request_put[352] ; - - // remaining internal signals - assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 = - mem_server_request_put[319:256] < 64'h0000000000800000 ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - begin - v__h371 = $stime; - #0; - end - v__h365 = v__h371 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)", - v__h365, - mem_server_request_put[319:256], - 64'h0000000000800000); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkMem_Model - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v deleted file mode 100644 index f7edd910..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v +++ /dev/null @@ -1,1655 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 -// RDY_server_reset_response_get O 1 reg -// imem_valid O 1 -// imem_is_i32_not_i16 O 1 const -// imem_pc O 32 reg -// imem_instr O 32 -// imem_exc O 1 -// imem_exc_code O 4 reg -// imem_tval O 32 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_valid O 1 -// dmem_word64 O 64 -// dmem_st_amo_val O 64 -// dmem_exc O 1 -// dmem_exc_code O 4 reg -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_server_fence_i_request_put O 1 -// RDY_server_fence_i_response_get O 1 -// RDY_server_fence_request_put O 1 reg -// RDY_server_fence_response_get O 1 -// RDY_sfence_vma O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// imem_req_f3 I 3 -// imem_req_addr I 32 -// imem_req_priv I 2 reg -// imem_req_sstatus_SUM I 1 reg -// imem_req_mstatus_MXR I 1 reg -// imem_req_satp I 32 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_req_op I 2 -// dmem_req_f3 I 3 -// dmem_req_amo_funct7 I 7 reg -// dmem_req_addr I 32 -// dmem_req_store_value I 64 -// dmem_req_priv I 2 reg -// dmem_req_sstatus_SUM I 1 reg -// dmem_req_mstatus_MXR I 1 reg -// dmem_req_satp I 32 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// server_fence_request_put I 8 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_imem_req I 1 -// EN_dmem_req I 1 -// EN_server_fence_i_request_put I 1 -// EN_server_fence_i_response_get I 1 -// EN_server_fence_request_put I 1 -// EN_server_fence_response_get I 1 -// EN_sfence_vma I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_valid -// (imem_master_awready, imem_master_wready) -> imem_instr -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// imem_master_arready, -// EN_imem_req) -> imem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_valid -// (dmem_master_awready, dmem_master_wready) -> dmem_word64 -// (dmem_master_awready, dmem_master_wready) -> dmem_st_amo_val -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// (dmem_master_awready, -// dmem_master_wready, -// dmem_master_arready, -// EN_dmem_req) -> dmem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - imem_req_f3, - imem_req_addr, - imem_req_priv, - imem_req_sstatus_SUM, - imem_req_mstatus_MXR, - imem_req_satp, - EN_imem_req, - - imem_valid, - - imem_is_i32_not_i16, - - imem_pc, - - imem_instr, - - imem_exc, - - imem_exc_code, - - imem_tval, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_req_op, - dmem_req_f3, - dmem_req_amo_funct7, - dmem_req_addr, - dmem_req_store_value, - dmem_req_priv, - dmem_req_sstatus_SUM, - dmem_req_mstatus_MXR, - dmem_req_satp, - EN_dmem_req, - - dmem_valid, - - dmem_word64, - - dmem_st_amo_val, - - dmem_exc, - - dmem_exc_code, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - EN_server_fence_i_request_put, - RDY_server_fence_i_request_put, - - EN_server_fence_i_response_get, - RDY_server_fence_i_response_get, - - server_fence_request_put, - EN_server_fence_request_put, - RDY_server_fence_request_put, - - EN_server_fence_response_get, - RDY_server_fence_response_get, - - EN_sfence_vma, - RDY_sfence_vma); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method imem_req - input [2 : 0] imem_req_f3; - input [31 : 0] imem_req_addr; - input [1 : 0] imem_req_priv; - input imem_req_sstatus_SUM; - input imem_req_mstatus_MXR; - input [31 : 0] imem_req_satp; - input EN_imem_req; - - // value method imem_valid - output imem_valid; - - // value method imem_is_i32_not_i16 - output imem_is_i32_not_i16; - - // value method imem_pc - output [31 : 0] imem_pc; - - // value method imem_instr - output [31 : 0] imem_instr; - - // value method imem_exc - output imem_exc; - - // value method imem_exc_code - output [3 : 0] imem_exc_code; - - // value method imem_tval - output [31 : 0] imem_tval; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // action method dmem_req - input [1 : 0] dmem_req_op; - input [2 : 0] dmem_req_f3; - input [6 : 0] dmem_req_amo_funct7; - input [31 : 0] dmem_req_addr; - input [63 : 0] dmem_req_store_value; - input [1 : 0] dmem_req_priv; - input dmem_req_sstatus_SUM; - input dmem_req_mstatus_MXR; - input [31 : 0] dmem_req_satp; - input EN_dmem_req; - - // value method dmem_valid - output dmem_valid; - - // value method dmem_word64 - output [63 : 0] dmem_word64; - - // value method dmem_st_amo_val - output [63 : 0] dmem_st_amo_val; - - // value method dmem_exc - output dmem_exc; - - // value method dmem_exc_code - output [3 : 0] dmem_exc_code; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method server_fence_i_request_put - input EN_server_fence_i_request_put; - output RDY_server_fence_i_request_put; - - // action method server_fence_i_response_get - input EN_server_fence_i_response_get; - output RDY_server_fence_i_response_get; - - // action method server_fence_request_put - input [7 : 0] server_fence_request_put; - input EN_server_fence_request_put; - output RDY_server_fence_request_put; - - // action method server_fence_response_get - input EN_server_fence_response_get; - output RDY_server_fence_response_get; - - // action method sfence_vma - input EN_sfence_vma; - output RDY_sfence_vma; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - dmem_st_amo_val, - dmem_word64, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [31 : 0] imem_instr, imem_pc, imem_tval; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_exc_code, - dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_exc_code, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_server_fence_i_request_put, - RDY_server_fence_i_response_get, - RDY_server_fence_request_put, - RDY_server_fence_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_sfence_vma, - dmem_exc, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - dmem_valid, - imem_exc, - imem_is_i32_not_i16, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid, - imem_valid; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule dcache - wire [63 : 0] dcache$mem_master_araddr, - dcache$mem_master_awaddr, - dcache$mem_master_rdata, - dcache$mem_master_wdata, - dcache$req_st_value, - dcache$st_amo_val, - dcache$word64; - wire [31 : 0] dcache$req_addr, dcache$req_satp; - wire [7 : 0] dcache$mem_master_arlen, - dcache$mem_master_awlen, - dcache$mem_master_wstrb; - wire [6 : 0] dcache$req_amo_funct7; - wire [3 : 0] dcache$exc_code, - dcache$mem_master_arcache, - dcache$mem_master_arid, - dcache$mem_master_arqos, - dcache$mem_master_arregion, - dcache$mem_master_awcache, - dcache$mem_master_awid, - dcache$mem_master_awqos, - dcache$mem_master_awregion, - dcache$mem_master_bid, - dcache$mem_master_rid, - dcache$mem_master_wid, - dcache$set_verbosity_verbosity; - wire [2 : 0] dcache$mem_master_arprot, - dcache$mem_master_arsize, - dcache$mem_master_awprot, - dcache$mem_master_awsize, - dcache$req_f3; - wire [1 : 0] dcache$mem_master_arburst, - dcache$mem_master_awburst, - dcache$mem_master_bresp, - dcache$mem_master_rresp, - dcache$req_op, - dcache$req_priv; - wire dcache$EN_req, - dcache$EN_server_flush_request_put, - dcache$EN_server_flush_response_get, - dcache$EN_server_reset_request_put, - dcache$EN_server_reset_response_get, - dcache$EN_set_verbosity, - dcache$EN_tlb_flush, - dcache$RDY_server_flush_request_put, - dcache$RDY_server_flush_response_get, - dcache$RDY_server_reset_request_put, - dcache$RDY_server_reset_response_get, - dcache$exc, - dcache$mem_master_arlock, - dcache$mem_master_arready, - dcache$mem_master_arvalid, - dcache$mem_master_awlock, - dcache$mem_master_awready, - dcache$mem_master_awvalid, - dcache$mem_master_bready, - dcache$mem_master_bvalid, - dcache$mem_master_rlast, - dcache$mem_master_rready, - dcache$mem_master_rvalid, - dcache$mem_master_wlast, - dcache$mem_master_wready, - dcache$mem_master_wvalid, - dcache$req_mstatus_MXR, - dcache$req_sstatus_SUM, - dcache$valid; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule icache - wire [63 : 0] icache$mem_master_araddr, - icache$mem_master_awaddr, - icache$mem_master_rdata, - icache$mem_master_wdata, - icache$req_st_value, - icache$word64; - wire [31 : 0] icache$addr, icache$req_addr, icache$req_satp; - wire [7 : 0] icache$mem_master_arlen, - icache$mem_master_awlen, - icache$mem_master_wstrb; - wire [6 : 0] icache$req_amo_funct7; - wire [3 : 0] icache$exc_code, - icache$mem_master_arcache, - icache$mem_master_arid, - icache$mem_master_arqos, - icache$mem_master_arregion, - icache$mem_master_awcache, - icache$mem_master_awid, - icache$mem_master_awqos, - icache$mem_master_awregion, - icache$mem_master_bid, - icache$mem_master_rid, - icache$mem_master_wid, - icache$set_verbosity_verbosity; - wire [2 : 0] icache$mem_master_arprot, - icache$mem_master_arsize, - icache$mem_master_awprot, - icache$mem_master_awsize, - icache$req_f3; - wire [1 : 0] icache$mem_master_arburst, - icache$mem_master_awburst, - icache$mem_master_bresp, - icache$mem_master_rresp, - icache$req_op, - icache$req_priv; - wire icache$EN_req, - icache$EN_server_flush_request_put, - icache$EN_server_flush_response_get, - icache$EN_server_reset_request_put, - icache$EN_server_reset_response_get, - icache$EN_set_verbosity, - icache$EN_tlb_flush, - icache$RDY_server_flush_request_put, - icache$RDY_server_flush_response_get, - icache$RDY_server_reset_request_put, - icache$RDY_server_reset_response_get, - icache$exc, - icache$mem_master_arlock, - icache$mem_master_arready, - icache$mem_master_arvalid, - icache$mem_master_awlock, - icache$mem_master_awready, - icache$mem_master_awvalid, - icache$mem_master_bready, - icache$mem_master_bvalid, - icache$mem_master_rlast, - icache$mem_master_rready, - icache$mem_master_rvalid, - icache$mem_master_wlast, - icache$mem_master_wready, - icache$mem_master_wvalid, - icache$req_mstatus_MXR, - icache$req_sstatus_SUM, - icache$valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_dmem_req, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_imem_req, - CAN_FIRE_server_fence_i_request_put, - CAN_FIRE_server_fence_i_response_get, - CAN_FIRE_server_fence_request_put, - CAN_FIRE_server_fence_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_sfence_vma, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_dmem_req, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_imem_req, - WILL_FIRE_server_fence_i_request_put, - WILL_FIRE_server_fence_i_response_get, - WILL_FIRE_server_fence_request_put, - WILL_FIRE_server_fence_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_sfence_vma; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h1675; - reg [31 : 0] v__h1826; - reg [31 : 0] v__h1669; - reg [31 : 0] v__h1820; - // synopsys translate_on - - // remaining internal signals - wire NOT_cfg_verbosity_read_ULE_1___d9; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = rg_state == 2'd2 ; - assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method imem_req - assign CAN_FIRE_imem_req = 1'd1 ; - assign WILL_FIRE_imem_req = EN_imem_req ; - - // value method imem_valid - assign imem_valid = icache$valid ; - - // value method imem_is_i32_not_i16 - assign imem_is_i32_not_i16 = 1'd1 ; - - // value method imem_pc - assign imem_pc = icache$addr ; - - // value method imem_instr - assign imem_instr = icache$word64[31:0] ; - - // value method imem_exc - assign imem_exc = icache$exc ; - - // value method imem_exc_code - assign imem_exc_code = icache$exc_code ; - - // value method imem_tval - assign imem_tval = icache$addr ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = icache$mem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = icache$mem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = icache$mem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = icache$mem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = icache$mem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = icache$mem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = icache$mem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = icache$mem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = icache$mem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = icache$mem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = icache$mem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = icache$mem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = icache$mem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = icache$mem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = icache$mem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = icache$mem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = icache$mem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = icache$mem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = icache$mem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = icache$mem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = icache$mem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = icache$mem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = icache$mem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = icache$mem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = icache$mem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = icache$mem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = icache$mem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = icache$mem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = icache$mem_master_rready ; - - // action method dmem_req - assign CAN_FIRE_dmem_req = 1'd1 ; - assign WILL_FIRE_dmem_req = EN_dmem_req ; - - // value method dmem_valid - assign dmem_valid = dcache$valid ; - - // value method dmem_word64 - assign dmem_word64 = dcache$word64 ; - - // value method dmem_st_amo_val - assign dmem_st_amo_val = dcache$st_amo_val ; - - // value method dmem_exc - assign dmem_exc = dcache$exc ; - - // value method dmem_exc_code - assign dmem_exc_code = dcache$exc_code ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = dcache$mem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = dcache$mem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = dcache$mem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = dcache$mem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = dcache$mem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = dcache$mem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = dcache$mem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = dcache$mem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = dcache$mem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = dcache$mem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = dcache$mem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = dcache$mem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = dcache$mem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = dcache$mem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = dcache$mem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = dcache$mem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = dcache$mem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = dcache$mem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = dcache$mem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = dcache$mem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = dcache$mem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = dcache$mem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = dcache$mem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = dcache$mem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = dcache$mem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = dcache$mem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = dcache$mem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = dcache$mem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = dcache$mem_master_rready ; - - // action method server_fence_i_request_put - assign RDY_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_i_request_put = - EN_server_fence_i_request_put ; - - // action method server_fence_i_response_get - assign RDY_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_i_response_get = - EN_server_fence_i_response_get ; - - // action method server_fence_request_put - assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_request_put = - dcache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ; - - // action method server_fence_response_get - assign RDY_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ; - - // action method sfence_vma - assign RDY_sfence_vma = 1'd1 ; - assign CAN_FIRE_sfence_vma = 1'd1 ; - assign WILL_FIRE_sfence_vma = EN_sfence_vma ; - - // submodule dcache - mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(dcache$mem_master_arready), - .mem_master_awready(dcache$mem_master_awready), - .mem_master_bid(dcache$mem_master_bid), - .mem_master_bresp(dcache$mem_master_bresp), - .mem_master_bvalid(dcache$mem_master_bvalid), - .mem_master_rdata(dcache$mem_master_rdata), - .mem_master_rid(dcache$mem_master_rid), - .mem_master_rlast(dcache$mem_master_rlast), - .mem_master_rresp(dcache$mem_master_rresp), - .mem_master_rvalid(dcache$mem_master_rvalid), - .mem_master_wready(dcache$mem_master_wready), - .req_addr(dcache$req_addr), - .req_amo_funct7(dcache$req_amo_funct7), - .req_f3(dcache$req_f3), - .req_mstatus_MXR(dcache$req_mstatus_MXR), - .req_op(dcache$req_op), - .req_priv(dcache$req_priv), - .req_satp(dcache$req_satp), - .req_sstatus_SUM(dcache$req_sstatus_SUM), - .req_st_value(dcache$req_st_value), - .set_verbosity_verbosity(dcache$set_verbosity_verbosity), - .EN_set_verbosity(dcache$EN_set_verbosity), - .EN_server_reset_request_put(dcache$EN_server_reset_request_put), - .EN_server_reset_response_get(dcache$EN_server_reset_response_get), - .EN_req(dcache$EN_req), - .EN_server_flush_request_put(dcache$EN_server_flush_request_put), - .EN_server_flush_response_get(dcache$EN_server_flush_response_get), - .EN_tlb_flush(dcache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), - .valid(dcache$valid), - .addr(), - .word64(dcache$word64), - .st_amo_val(dcache$st_amo_val), - .exc(dcache$exc), - .exc_code(dcache$exc_code), - .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(dcache$mem_master_awvalid), - .mem_master_awid(dcache$mem_master_awid), - .mem_master_awaddr(dcache$mem_master_awaddr), - .mem_master_awlen(dcache$mem_master_awlen), - .mem_master_awsize(dcache$mem_master_awsize), - .mem_master_awburst(dcache$mem_master_awburst), - .mem_master_awlock(dcache$mem_master_awlock), - .mem_master_awcache(dcache$mem_master_awcache), - .mem_master_awprot(dcache$mem_master_awprot), - .mem_master_awqos(dcache$mem_master_awqos), - .mem_master_awregion(dcache$mem_master_awregion), - .mem_master_wvalid(dcache$mem_master_wvalid), - .mem_master_wid(dcache$mem_master_wid), - .mem_master_wdata(dcache$mem_master_wdata), - .mem_master_wstrb(dcache$mem_master_wstrb), - .mem_master_wlast(dcache$mem_master_wlast), - .mem_master_bready(dcache$mem_master_bready), - .mem_master_arvalid(dcache$mem_master_arvalid), - .mem_master_arid(dcache$mem_master_arid), - .mem_master_araddr(dcache$mem_master_araddr), - .mem_master_arlen(dcache$mem_master_arlen), - .mem_master_arsize(dcache$mem_master_arsize), - .mem_master_arburst(dcache$mem_master_arburst), - .mem_master_arlock(dcache$mem_master_arlock), - .mem_master_arcache(dcache$mem_master_arcache), - .mem_master_arprot(dcache$mem_master_arprot), - .mem_master_arqos(dcache$mem_master_arqos), - .mem_master_arregion(dcache$mem_master_arregion), - .mem_master_rready(dcache$mem_master_rready)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule icache - mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(icache$mem_master_arready), - .mem_master_awready(icache$mem_master_awready), - .mem_master_bid(icache$mem_master_bid), - .mem_master_bresp(icache$mem_master_bresp), - .mem_master_bvalid(icache$mem_master_bvalid), - .mem_master_rdata(icache$mem_master_rdata), - .mem_master_rid(icache$mem_master_rid), - .mem_master_rlast(icache$mem_master_rlast), - .mem_master_rresp(icache$mem_master_rresp), - .mem_master_rvalid(icache$mem_master_rvalid), - .mem_master_wready(icache$mem_master_wready), - .req_addr(icache$req_addr), - .req_amo_funct7(icache$req_amo_funct7), - .req_f3(icache$req_f3), - .req_mstatus_MXR(icache$req_mstatus_MXR), - .req_op(icache$req_op), - .req_priv(icache$req_priv), - .req_satp(icache$req_satp), - .req_sstatus_SUM(icache$req_sstatus_SUM), - .req_st_value(icache$req_st_value), - .set_verbosity_verbosity(icache$set_verbosity_verbosity), - .EN_set_verbosity(icache$EN_set_verbosity), - .EN_server_reset_request_put(icache$EN_server_reset_request_put), - .EN_server_reset_response_get(icache$EN_server_reset_response_get), - .EN_req(icache$EN_req), - .EN_server_flush_request_put(icache$EN_server_flush_request_put), - .EN_server_flush_response_get(icache$EN_server_flush_response_get), - .EN_tlb_flush(icache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), - .valid(icache$valid), - .addr(icache$addr), - .word64(icache$word64), - .st_amo_val(), - .exc(icache$exc), - .exc_code(icache$exc_code), - .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(icache$mem_master_awvalid), - .mem_master_awid(icache$mem_master_awid), - .mem_master_awaddr(icache$mem_master_awaddr), - .mem_master_awlen(icache$mem_master_awlen), - .mem_master_awsize(icache$mem_master_awsize), - .mem_master_awburst(icache$mem_master_awburst), - .mem_master_awlock(icache$mem_master_awlock), - .mem_master_awcache(icache$mem_master_awcache), - .mem_master_awprot(icache$mem_master_awprot), - .mem_master_awqos(icache$mem_master_awqos), - .mem_master_awregion(icache$mem_master_awregion), - .mem_master_wvalid(icache$mem_master_wvalid), - .mem_master_wid(icache$mem_master_wid), - .mem_master_wdata(icache$mem_master_wdata), - .mem_master_wstrb(icache$mem_master_wstrb), - .mem_master_wlast(icache$mem_master_wlast), - .mem_master_bready(icache$mem_master_bready), - .mem_master_arvalid(icache$mem_master_arvalid), - .mem_master_arid(icache$mem_master_arid), - .mem_master_araddr(icache$mem_master_araddr), - .mem_master_arlen(icache$mem_master_arlen), - .mem_master_arsize(icache$mem_master_arsize), - .mem_master_arburst(icache$mem_master_arburst), - .mem_master_arlock(icache$mem_master_arlock), - .mem_master_arcache(icache$mem_master_arcache), - .mem_master_arprot(icache$mem_master_arprot), - .mem_master_arqos(icache$mem_master_arqos), - .mem_master_arregion(icache$mem_master_arregion), - .mem_master_rready(icache$mem_master_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - dcache$RDY_server_reset_request_put && - icache$RDY_server_reset_request_put && - rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && - !EN_server_fence_i_request_put ; - assign MUX_rg_state$write_1__SEL_3 = - dcache$RDY_server_reset_response_get && - icache$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - rg_state == 2'd1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete) - begin - case (1'b1) // synopsys parallel_case - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1; - WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset || - WILL_FIRE_RL_rl_reset_complete ; - - // submodule dcache - assign dcache$mem_master_arready = dmem_master_arready ; - assign dcache$mem_master_awready = dmem_master_awready ; - assign dcache$mem_master_bid = dmem_master_bid ; - assign dcache$mem_master_bresp = dmem_master_bresp ; - assign dcache$mem_master_bvalid = dmem_master_bvalid ; - assign dcache$mem_master_rdata = dmem_master_rdata ; - assign dcache$mem_master_rid = dmem_master_rid ; - assign dcache$mem_master_rlast = dmem_master_rlast ; - assign dcache$mem_master_rresp = dmem_master_rresp ; - assign dcache$mem_master_rvalid = dmem_master_rvalid ; - assign dcache$mem_master_wready = dmem_master_wready ; - assign dcache$req_addr = dmem_req_addr ; - assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ; - assign dcache$req_f3 = dmem_req_f3 ; - assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ; - assign dcache$req_op = dmem_req_op ; - assign dcache$req_priv = dmem_req_priv ; - assign dcache$req_satp = dmem_req_satp ; - assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ; - assign dcache$req_st_value = dmem_req_store_value ; - assign dcache$set_verbosity_verbosity = 4'h0 ; - assign dcache$EN_set_verbosity = 1'b0 ; - assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign dcache$EN_req = EN_dmem_req ; - assign dcache$EN_server_flush_request_put = - EN_server_fence_i_request_put || EN_server_fence_request_put ; - assign dcache$EN_server_flush_response_get = - EN_server_fence_i_response_get || EN_server_fence_response_get ; - assign dcache$EN_tlb_flush = EN_sfence_vma ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule icache - assign icache$mem_master_arready = imem_master_arready ; - assign icache$mem_master_awready = imem_master_awready ; - assign icache$mem_master_bid = imem_master_bid ; - assign icache$mem_master_bresp = imem_master_bresp ; - assign icache$mem_master_bvalid = imem_master_bvalid ; - assign icache$mem_master_rdata = imem_master_rdata ; - assign icache$mem_master_rid = imem_master_rid ; - assign icache$mem_master_rlast = imem_master_rlast ; - assign icache$mem_master_rresp = imem_master_rresp ; - assign icache$mem_master_rvalid = imem_master_rvalid ; - assign icache$mem_master_wready = imem_master_wready ; - assign icache$req_addr = imem_req_addr ; - assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ; - assign icache$req_f3 = imem_req_f3 ; - assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ; - assign icache$req_op = 2'd0 ; - assign icache$req_priv = imem_req_priv ; - assign icache$req_satp = imem_req_satp ; - assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ; - assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign icache$set_verbosity_verbosity = 4'h0 ; - assign icache$EN_set_verbosity = 1'b0 ; - assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign icache$EN_req = EN_imem_req ; - assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ; - assign icache$EN_server_flush_response_get = - EN_server_fence_i_response_get ; - assign icache$EN_tlb_flush = EN_sfence_vma ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1675 = $stime; - #0; - end - v__h1669 = v__h1675 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset", v__h1669); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1826 = $stime; - #0; - end - v__h1820 = v__h1826 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset_complete", v__h1820); - end - // synopsys translate_on -endmodule // mkNear_Mem - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v deleted file mode 100644 index 32e93584..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v +++ /dev/null @@ -1,1308 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// RDY_server_request_put O 1 reg -// server_response_get O 66 reg -// RDY_server_response_get O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// server_request_put I 137 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_server_request_put I 1 -// EN_server_response_get I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - server_request_put, - EN_server_request_put, - RDY_server_request_put, - - EN_server_response_get, - server_response_get, - RDY_server_response_get, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method server_request_put - input [136 : 0] server_request_put; - input EN_server_request_put; - output RDY_server_request_put; - - // actionvalue method server_response_get - input EN_server_response_get; - output [65 : 0] server_response_get; - output RDY_server_response_get; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [65 : 0] server_response_get; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_request_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_server_response_get, - RDY_set_addr_map, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reqs - wire [136 : 0] f_reqs$D_IN, f_reqs$D_OUT; - wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_rsps - wire [65 : 0] f_rsps$D_IN, f_rsps$D_OUT; - wire f_rsps$CLR, f_rsps$DEQ, f_rsps$EMPTY_N, f_rsps$ENQ, f_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_request_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_server_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_request_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_server_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire [65 : 0] MUX_f_rsps$enq_1__VAL_1, MUX_f_rsps$enq_1__VAL_2; - wire [63 : 0] MUX_crg_time$port1__write_1__VAL_1, - MUX_crg_timecmp$port1__write_1__VAL_1; - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8676; - reg [31 : 0] v__h8808; - reg [31 : 0] v__h1471; - reg [31 : 0] v__h1868; - reg [31 : 0] v__h2065; - reg [31 : 0] v__h1714; - reg [31 : 0] v__h2442; - reg [31 : 0] v__h7890; - reg [31 : 0] v__h8258; - reg [31 : 0] v__h8368; - reg [31 : 0] v__h8475; - reg [31 : 0] v__h1465; - reg [31 : 0] v__h1708; - reg [31 : 0] v__h1862; - reg [31 : 0] v__h2059; - reg [31 : 0] v__h2436; - reg [31 : 0] v__h7884; - reg [31 : 0] v__h8252; - reg [31 : 0] v__h8362; - reg [31 : 0] v__h8469; - reg [31 : 0] v__h8670; - reg [31 : 0] v__h8802; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rsp_rdata__h2209; - wire [63 : 0] byte_addr__h1981, - mask__h2865, - mask__h5362, - new_data__h5360, - new_time__h4107, - new_time__h6632, - new_timecmp__h2834, - new_timecmp__h5331, - old_time__h6631, - rdata__h1996, - rdata__h2020, - rdata__h2026, - x__h2876, - x__h4149, - x__h5373, - x__h6674, - y__h2877, - y__h2878, - y__h5374, - y__h5375; - wire [7 : 0] SEXT_f_reqs_first__8_BIT_0_31___d132, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_7_07___d108; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method server_request_put - assign RDY_server_request_put = f_reqs$FULL_N ; - assign CAN_FIRE_server_request_put = f_reqs$FULL_N ; - assign WILL_FIRE_server_request_put = EN_server_request_put ; - - // actionvalue method server_response_get - assign server_response_get = f_rsps$D_OUT ; - assign RDY_server_response_get = f_rsps$EMPTY_N ; - assign CAN_FIRE_server_response_get = f_rsps$EMPTY_N ; - assign WILL_FIRE_server_response_get = EN_server_response_get ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reqs - FIFO2 #(.width(32'd137), .guarded(32'd1)) f_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reqs$D_IN), - .ENQ(f_reqs$ENQ), - .DEQ(f_reqs$DEQ), - .CLR(f_reqs$CLR), - .D_OUT(f_reqs$D_OUT), - .FULL_N(f_reqs$FULL_N), - .EMPTY_N(f_reqs$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_rsps - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_rsps$D_IN), - .ENQ(f_rsps$ENQ), - .DEQ(f_rsps$DEQ), - .CLR(f_rsps$CLR), - .D_OUT(f_rsps$D_OUT), - .FULL_N(f_rsps$FULL_N), - .EMPTY_N(f_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && rg_state && - !f_reset_reqs$EMPTY_N && - f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && - (byte_addr__h1981 != 64'h0 || - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - f_sw_interrupt_req$FULL_N) && - rg_state && - !f_reset_reqs$EMPTY_N && - !f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign MUX_crg_time$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h000000000000BFF8) ? - new_time__h4107 : - new_time__h6632 ; - assign MUX_crg_timecmp$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h0000000000004000) ? - new_timecmp__h2834 : - new_timecmp__h5331 ; - assign MUX_f_rsps$enq_1__VAL_1 = - { 1'd1, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - rsp_rdata__h2209 } ; - assign MUX_f_rsps$enq_1__VAL_2 = - { 1'd0, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - 64'hAAAAAAAAAAAAAAAA } ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? - MUX_crg_time$port1__write_1__VAL_1 : - 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h6631 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - MUX_crg_timecmp$port1__write_1__VAL_1 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = MUX_rg_msip$write_1__SEL_1 && f_reqs$D_OUT[8] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reqs - assign f_reqs$D_IN = server_request_put ; - assign f_reqs$ENQ = EN_server_request_put ; - assign f_reqs$DEQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_rsps - assign f_rsps$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_f_rsps$enq_1__VAL_1 : - MUX_f_rsps$enq_1__VAL_2 ; - assign f_rsps$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_process_wr_req ; - assign f_rsps$DEQ = EN_server_response_get ; - assign f_rsps$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = f_reqs$D_OUT[8] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_f_reqs_first__8_BIT_0_31___d132 = {8{f_reqs$D_OUT[0]}} ; - assign SEXT_f_reqs_first__8_BIT_1_28___d129 = {8{f_reqs$D_OUT[1]}} ; - assign SEXT_f_reqs_first__8_BIT_2_24___d125 = {8{f_reqs$D_OUT[2]}} ; - assign SEXT_f_reqs_first__8_BIT_3_21___d122 = {8{f_reqs$D_OUT[3]}} ; - assign SEXT_f_reqs_first__8_BIT_4_17___d118 = {8{f_reqs$D_OUT[4]}} ; - assign SEXT_f_reqs_first__8_BIT_5_14___d115 = {8{f_reqs$D_OUT[5]}} ; - assign SEXT_f_reqs_first__8_BIT_6_10___d111 = {8{f_reqs$D_OUT[6]}} ; - assign SEXT_f_reqs_first__8_BIT_7_07___d108 = {8{f_reqs$D_OUT[7]}} ; - assign byte_addr__h1981 = f_reqs$D_OUT[135:72] - rg_addr_base ; - assign mask__h2865 = - { SEXT_f_reqs_first__8_BIT_7_07___d108, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign mask__h5362 = - { SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'd0 } ; - assign new_data__h5360 = { f_reqs$D_OUT[39:8], 32'h0 } ; - assign new_time__h4107 = x__h4149 | y__h2877 ; - assign new_time__h6632 = x__h6674 | y__h5374 ; - assign new_timecmp__h2834 = x__h2876 | y__h2877 ; - assign new_timecmp__h5331 = x__h5373 | y__h5374 ; - assign old_time__h6631 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata__h1996 = { 63'd0, rg_msip } ; - assign rdata__h2020 = { 32'd0, crg_timecmp[63:32] } ; - assign rdata__h2026 = { 32'd0, crg_time[63:32] } ; - assign rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 = - rg_msip == f_reqs$D_OUT[8] ; - assign x__h2876 = crg_timecmp & y__h2878 ; - assign x__h4149 = old_time__h6631 & y__h2878 ; - assign x__h5373 = crg_timecmp & y__h5375 ; - assign x__h6674 = old_time__h6631 & y__h5375 ; - assign y__h2877 = f_reqs$D_OUT[71:8] & mask__h2865 ; - assign y__h2878 = - { ~SEXT_f_reqs_first__8_BIT_7_07___d108, - ~SEXT_f_reqs_first__8_BIT_6_10___d111, - ~SEXT_f_reqs_first__8_BIT_5_14___d115, - ~SEXT_f_reqs_first__8_BIT_4_17___d118, - ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign y__h5374 = new_data__h5360 & mask__h5362 ; - assign y__h5375 = - { ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'hFFFFFFFF } ; - always@(byte_addr__h1981 or - rdata__h1996 or - crg_timecmp or rdata__h2020 or crg_time or rdata__h2026) - begin - case (byte_addr__h1981) - 64'h0: rsp_rdata__h2209 = rdata__h1996; - 64'h0000000000000004: rsp_rdata__h2209 = 64'd0; - 64'h0000000000004000: rsp_rdata__h2209 = crg_timecmp; - 64'h0000000000004004: rsp_rdata__h2209 = rdata__h2020; - 64'h000000000000BFF8: rsp_rdata__h2209 = crg_time; - 64'h000000000000BFFC: rsp_rdata__h2209 = rdata__h2026; - default: rsp_rdata__h2209 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8676 = $stime; - #0; - end - v__h8670 = v__h8676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_timer_interrupt_req: %x", - v__h8670, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8808 = $stime; - #0; - end - v__h8802 = v__h8808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_sw_interrupt_req: %x", - v__h8802, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1471 = $stime; - #0; - end - v__h1465 = v__h1471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO.rl_reset", v__h1465); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1868 = $stime; - #0; - end - v__h1862 = v__h1868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_rd_req: rg_mtip = %0d", - v__h1862, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h2065 = $stime; - #0; - end - v__h2059 = v__h2065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_rd_req: unrecognized addr", - v__h2059); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rsp_rdata__h2209, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1714 = $stime; - #0; - end - v__h1708 = v__h1714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h1708, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2442 = $stime; - #0; - end - v__h2436 = v__h2442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_wr_req: rg_mtip = %0d", - v__h2436, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", f_reqs$D_OUT[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h2834); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h2834 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h4107); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h5331); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h5331 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h6632); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h7890 = $stime; - #0; - end - v__h7884 = v__h7890 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_wr_req: unrecognized addr", - v__h7884); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 64'hAAAAAAAAAAAAAAAA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h8258 = $stime; - #0; - end - v__h8252 = v__h8258 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h8252, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h8368 = $stime; - #0; - end - v__h8362 = v__h8368 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h8362, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h8475 = $stime; - #0; - end - v__h8469 = v__h8475 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h8469, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v deleted file mode 100644 index 0883c8da..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v +++ /dev/null @@ -1,2812 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO_AXI4(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h10065; - reg [31 : 0] v__h10197; - reg [31 : 0] v__h1852; - reg [31 : 0] v__h2269; - reg [31 : 0] v__h2453; - reg [31 : 0] v__h2640; - reg [31 : 0] v__h2878; - reg [31 : 0] v__h2095; - reg [31 : 0] v__h3161; - reg [31 : 0] v__h3391; - reg [31 : 0] v__h8927; - reg [31 : 0] v__h9148; - reg [31 : 0] v__h9475; - reg [31 : 0] v__h9585; - reg [31 : 0] v__h9692; - reg [31 : 0] v__h1846; - reg [31 : 0] v__h2089; - reg [31 : 0] v__h2263; - reg [31 : 0] v__h2447; - reg [31 : 0] v__h2634; - reg [31 : 0] v__h2872; - reg [31 : 0] v__h3155; - reg [31 : 0] v__h3385; - reg [31 : 0] v__h8921; - reg [31 : 0] v__h9142; - reg [31 : 0] v__h9469; - reg [31 : 0] v__h9579; - reg [31 : 0] v__h9686; - reg [31 : 0] v__h10059; - reg [31 : 0] v__h10191; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] _theResult___fst__h2566; - reg [1 : 0] _theResult___snd__h2567, v__h3517; - wire [63 : 0] byte_addr__h2405, - byte_addr__h3353, - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190, - mask__h3798, - new_time__h5056, - new_timecmp__h3767, - old_time__h7614, - rdata___1__h2562, - x__h2751, - x__h3809, - x__h5098, - y__h3810, - y__h3811; - wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153; - wire [1 : 0] rresp__h2548, v__h3357; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108, - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53, - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102, - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? new_time__h5056 : 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h7614 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - new_timecmp__h3767 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = - MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - x__h2751, - rresp__h2548, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3357 } ; - assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 = - {8{slave_xactor_f_wr_data$D_OUT[1]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174 = - {8{slave_xactor_f_wr_data$D_OUT[2]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170 = - {8{slave_xactor_f_wr_data$D_OUT[3]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167 = - {8{slave_xactor_f_wr_data$D_OUT[4]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163 = - {8{slave_xactor_f_wr_data$D_OUT[5]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160 = - {8{slave_xactor_f_wr_data$D_OUT[6]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156 = - {8{slave_xactor_f_wr_data$D_OUT[7]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153 = - {8{slave_xactor_f_wr_data$D_OUT[8]}} ; - assign byte_addr__h2405 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign byte_addr__h3353 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190 = - new_timecmp__h3767 - old_time__h7614 ; - assign mask__h3798 = - { SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - assign new_time__h5056 = x__h5098 | y__h3810 ; - assign new_timecmp__h3767 = x__h3809 | y__h3810 ; - assign old_time__h7614 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata___1__h2562 = { 63'd0, rg_msip } ; - assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 = - rg_msip == slave_xactor_f_wr_data$D_OUT[9] ; - assign rresp__h2548 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 2'b11 : - _theResult___snd__h2567 ; - assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 = - slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 = - slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 || - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - f_sw_interrupt_req$FULL_N) ; - assign v__h3357 = - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ? - 2'b11 : - v__h3517 ; - assign x__h2751 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 64'd0 : - _theResult___fst__h2566 ; - assign x__h3809 = crg_timecmp & y__h3811 ; - assign x__h5098 = old_time__h7614 & y__h3811 ; - assign y__h3810 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3798 ; - assign y__h3811 = - { ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - always@(byte_addr__h2405) - begin - case (byte_addr__h2405) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - _theResult___snd__h2567 = 2'b0; - default: _theResult___snd__h2567 = 2'b11; - endcase - end - always@(byte_addr__h2405 or rdata___1__h2562 or crg_timecmp or crg_time) - begin - case (byte_addr__h2405) - 64'h0: _theResult___fst__h2566 = rdata___1__h2562; - 64'h0000000000000004: _theResult___fst__h2566 = 64'd0; - 64'h0000000000004000, 64'h0000000000004004: - _theResult___fst__h2566 = crg_timecmp; - 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___fst__h2566 = crg_time; - default: _theResult___fst__h2566 = 64'd0; - endcase - end - always@(byte_addr__h3353) - begin - case (byte_addr__h3353) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - v__h3517 = 2'b0; - default: v__h3517 = 2'b11; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10065 = $stime; - #0; - end - v__h10059 = v__h10065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x", - v__h10059, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10197 = $stime; - #0; - end - v__h10191 = v__h10197 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x", - v__h10191, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1852 = $stime; - #0; - end - v__h1846 = v__h1852 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1846); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2269 = $stime; - #0; - end - v__h2263 = v__h2269 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", - v__h2263, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - begin - v__h2453 = $stime; - #0; - end - v__h2447 = v__h2453 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2447); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - begin - v__h2640 = $stime; - #0; - end - v__h2634 = v__h2640 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2634); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2878 = $stime; - #0; - end - v__h2872 = v__h2878 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2872); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", x__h2751); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rresp__h2548); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2095 = $stime; - #0; - end - v__h2089 = v__h2095 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h2089, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h3161 = $stime; - #0; - end - v__h3155 = v__h3161 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", - v__h3155, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - begin - v__h3391 = $stime; - #0; - end - v__h3385 = v__h3391 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h3385); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - begin - v__h8927 = $stime; - #0; - end - v__h8921 = v__h8927 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h8921); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h9148 = $stime; - #0; - end - v__h9142 = v__h9148 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9142); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", v__h3357); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h9475 = $stime; - #0; - end - v__h9469 = v__h9475 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9469, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h9585 = $stime; - #0; - end - v__h9579 = v__h9585 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9579, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h9692 = $stime; - #0; - end - v__h9686 = v__h9692 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9686, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO_AXI4 - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v deleted file mode 100644 index f74de61e..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v +++ /dev/null @@ -1,26991 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_show_PLIC_state O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// v_targets_0_m_eip O 1 -// v_targets_1_m_eip O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// v_sources_0_m_interrupt_req_set_not_clear I 1 -// v_sources_1_m_interrupt_req_set_not_clear I 1 -// v_sources_2_m_interrupt_req_set_not_clear I 1 -// v_sources_3_m_interrupt_req_set_not_clear I 1 -// v_sources_4_m_interrupt_req_set_not_clear I 1 -// v_sources_5_m_interrupt_req_set_not_clear I 1 -// v_sources_6_m_interrupt_req_set_not_clear I 1 -// v_sources_7_m_interrupt_req_set_not_clear I 1 -// v_sources_8_m_interrupt_req_set_not_clear I 1 -// v_sources_9_m_interrupt_req_set_not_clear I 1 -// v_sources_10_m_interrupt_req_set_not_clear I 1 -// v_sources_11_m_interrupt_req_set_not_clear I 1 -// v_sources_12_m_interrupt_req_set_not_clear I 1 -// v_sources_13_m_interrupt_req_set_not_clear I 1 -// v_sources_14_m_interrupt_req_set_not_clear I 1 -// v_sources_15_m_interrupt_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_show_PLIC_state I 1 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkPLIC_16_2_7(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_show_PLIC_state, - RDY_show_PLIC_state, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - v_sources_0_m_interrupt_req_set_not_clear, - - v_sources_1_m_interrupt_req_set_not_clear, - - v_sources_2_m_interrupt_req_set_not_clear, - - v_sources_3_m_interrupt_req_set_not_clear, - - v_sources_4_m_interrupt_req_set_not_clear, - - v_sources_5_m_interrupt_req_set_not_clear, - - v_sources_6_m_interrupt_req_set_not_clear, - - v_sources_7_m_interrupt_req_set_not_clear, - - v_sources_8_m_interrupt_req_set_not_clear, - - v_sources_9_m_interrupt_req_set_not_clear, - - v_sources_10_m_interrupt_req_set_not_clear, - - v_sources_11_m_interrupt_req_set_not_clear, - - v_sources_12_m_interrupt_req_set_not_clear, - - v_sources_13_m_interrupt_req_set_not_clear, - - v_sources_14_m_interrupt_req_set_not_clear, - - v_sources_15_m_interrupt_req_set_not_clear, - - v_targets_0_m_eip, - - v_targets_1_m_eip); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method show_PLIC_state - input EN_show_PLIC_state; - output RDY_show_PLIC_state; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // action method v_sources_0_m_interrupt_req - input v_sources_0_m_interrupt_req_set_not_clear; - - // action method v_sources_1_m_interrupt_req - input v_sources_1_m_interrupt_req_set_not_clear; - - // action method v_sources_2_m_interrupt_req - input v_sources_2_m_interrupt_req_set_not_clear; - - // action method v_sources_3_m_interrupt_req - input v_sources_3_m_interrupt_req_set_not_clear; - - // action method v_sources_4_m_interrupt_req - input v_sources_4_m_interrupt_req_set_not_clear; - - // action method v_sources_5_m_interrupt_req - input v_sources_5_m_interrupt_req_set_not_clear; - - // action method v_sources_6_m_interrupt_req - input v_sources_6_m_interrupt_req_set_not_clear; - - // action method v_sources_7_m_interrupt_req - input v_sources_7_m_interrupt_req_set_not_clear; - - // action method v_sources_8_m_interrupt_req - input v_sources_8_m_interrupt_req_set_not_clear; - - // action method v_sources_9_m_interrupt_req - input v_sources_9_m_interrupt_req_set_not_clear; - - // action method v_sources_10_m_interrupt_req - input v_sources_10_m_interrupt_req_set_not_clear; - - // action method v_sources_11_m_interrupt_req - input v_sources_11_m_interrupt_req_set_not_clear; - - // action method v_sources_12_m_interrupt_req - input v_sources_12_m_interrupt_req_set_not_clear; - - // action method v_sources_13_m_interrupt_req - input v_sources_13_m_interrupt_req_set_not_clear; - - // action method v_sources_14_m_interrupt_req - input v_sources_14_m_interrupt_req_set_not_clear; - - // action method v_sources_15_m_interrupt_req - input v_sources_15_m_interrupt_req_set_not_clear; - - // value method v_targets_0_m_eip - output v_targets_0_m_eip; - - // value method v_targets_1_m_eip - output v_targets_1_m_eip; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_verbosity, - RDY_show_PLIC_state, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - v_targets_0_m_eip, - v_targets_1_m_eip; - - // register m_cfg_verbosity - reg [3 : 0] m_cfg_verbosity; - wire [3 : 0] m_cfg_verbosity$D_IN; - wire m_cfg_verbosity$EN; - - // register m_rg_addr_base - reg [63 : 0] m_rg_addr_base; - wire [63 : 0] m_rg_addr_base$D_IN; - wire m_rg_addr_base$EN; - - // register m_rg_addr_lim - reg [63 : 0] m_rg_addr_lim; - wire [63 : 0] m_rg_addr_lim$D_IN; - wire m_rg_addr_lim$EN; - - // register m_vrg_servicing_source_0 - reg [4 : 0] m_vrg_servicing_source_0; - wire [4 : 0] m_vrg_servicing_source_0$D_IN; - wire m_vrg_servicing_source_0$EN; - - // register m_vrg_servicing_source_1 - reg [4 : 0] m_vrg_servicing_source_1; - wire [4 : 0] m_vrg_servicing_source_1$D_IN; - wire m_vrg_servicing_source_1$EN; - - // register m_vrg_source_busy_0 - reg m_vrg_source_busy_0; - wire m_vrg_source_busy_0$D_IN, m_vrg_source_busy_0$EN; - - // register m_vrg_source_busy_1 - reg m_vrg_source_busy_1; - wire m_vrg_source_busy_1$D_IN, m_vrg_source_busy_1$EN; - - // register m_vrg_source_busy_10 - reg m_vrg_source_busy_10; - wire m_vrg_source_busy_10$D_IN, m_vrg_source_busy_10$EN; - - // register m_vrg_source_busy_11 - reg m_vrg_source_busy_11; - wire m_vrg_source_busy_11$D_IN, m_vrg_source_busy_11$EN; - - // register m_vrg_source_busy_12 - reg m_vrg_source_busy_12; - wire m_vrg_source_busy_12$D_IN, m_vrg_source_busy_12$EN; - - // register m_vrg_source_busy_13 - reg m_vrg_source_busy_13; - wire m_vrg_source_busy_13$D_IN, m_vrg_source_busy_13$EN; - - // register m_vrg_source_busy_14 - reg m_vrg_source_busy_14; - wire m_vrg_source_busy_14$D_IN, m_vrg_source_busy_14$EN; - - // register m_vrg_source_busy_15 - reg m_vrg_source_busy_15; - wire m_vrg_source_busy_15$D_IN, m_vrg_source_busy_15$EN; - - // register m_vrg_source_busy_16 - reg m_vrg_source_busy_16; - wire m_vrg_source_busy_16$D_IN, m_vrg_source_busy_16$EN; - - // register m_vrg_source_busy_2 - reg m_vrg_source_busy_2; - wire m_vrg_source_busy_2$D_IN, m_vrg_source_busy_2$EN; - - // register m_vrg_source_busy_3 - reg m_vrg_source_busy_3; - wire m_vrg_source_busy_3$D_IN, m_vrg_source_busy_3$EN; - - // register m_vrg_source_busy_4 - reg m_vrg_source_busy_4; - wire m_vrg_source_busy_4$D_IN, m_vrg_source_busy_4$EN; - - // register m_vrg_source_busy_5 - reg m_vrg_source_busy_5; - wire m_vrg_source_busy_5$D_IN, m_vrg_source_busy_5$EN; - - // register m_vrg_source_busy_6 - reg m_vrg_source_busy_6; - wire m_vrg_source_busy_6$D_IN, m_vrg_source_busy_6$EN; - - // register m_vrg_source_busy_7 - reg m_vrg_source_busy_7; - wire m_vrg_source_busy_7$D_IN, m_vrg_source_busy_7$EN; - - // register m_vrg_source_busy_8 - reg m_vrg_source_busy_8; - wire m_vrg_source_busy_8$D_IN, m_vrg_source_busy_8$EN; - - // register m_vrg_source_busy_9 - reg m_vrg_source_busy_9; - wire m_vrg_source_busy_9$D_IN, m_vrg_source_busy_9$EN; - - // register m_vrg_source_ip_0 - reg m_vrg_source_ip_0; - wire m_vrg_source_ip_0$D_IN, m_vrg_source_ip_0$EN; - - // register m_vrg_source_ip_1 - reg m_vrg_source_ip_1; - wire m_vrg_source_ip_1$D_IN, m_vrg_source_ip_1$EN; - - // register m_vrg_source_ip_10 - reg m_vrg_source_ip_10; - wire m_vrg_source_ip_10$D_IN, m_vrg_source_ip_10$EN; - - // register m_vrg_source_ip_11 - reg m_vrg_source_ip_11; - wire m_vrg_source_ip_11$D_IN, m_vrg_source_ip_11$EN; - - // register m_vrg_source_ip_12 - reg m_vrg_source_ip_12; - wire m_vrg_source_ip_12$D_IN, m_vrg_source_ip_12$EN; - - // register m_vrg_source_ip_13 - reg m_vrg_source_ip_13; - wire m_vrg_source_ip_13$D_IN, m_vrg_source_ip_13$EN; - - // register m_vrg_source_ip_14 - reg m_vrg_source_ip_14; - wire m_vrg_source_ip_14$D_IN, m_vrg_source_ip_14$EN; - - // register m_vrg_source_ip_15 - reg m_vrg_source_ip_15; - wire m_vrg_source_ip_15$D_IN, m_vrg_source_ip_15$EN; - - // register m_vrg_source_ip_16 - reg m_vrg_source_ip_16; - wire m_vrg_source_ip_16$D_IN, m_vrg_source_ip_16$EN; - - // register m_vrg_source_ip_2 - reg m_vrg_source_ip_2; - wire m_vrg_source_ip_2$D_IN, m_vrg_source_ip_2$EN; - - // register m_vrg_source_ip_3 - reg m_vrg_source_ip_3; - wire m_vrg_source_ip_3$D_IN, m_vrg_source_ip_3$EN; - - // register m_vrg_source_ip_4 - reg m_vrg_source_ip_4; - wire m_vrg_source_ip_4$D_IN, m_vrg_source_ip_4$EN; - - // register m_vrg_source_ip_5 - reg m_vrg_source_ip_5; - wire m_vrg_source_ip_5$D_IN, m_vrg_source_ip_5$EN; - - // register m_vrg_source_ip_6 - reg m_vrg_source_ip_6; - wire m_vrg_source_ip_6$D_IN, m_vrg_source_ip_6$EN; - - // register m_vrg_source_ip_7 - reg m_vrg_source_ip_7; - wire m_vrg_source_ip_7$D_IN, m_vrg_source_ip_7$EN; - - // register m_vrg_source_ip_8 - reg m_vrg_source_ip_8; - wire m_vrg_source_ip_8$D_IN, m_vrg_source_ip_8$EN; - - // register m_vrg_source_ip_9 - reg m_vrg_source_ip_9; - wire m_vrg_source_ip_9$D_IN, m_vrg_source_ip_9$EN; - - // register m_vrg_source_prio_0 - reg [2 : 0] m_vrg_source_prio_0; - wire [2 : 0] m_vrg_source_prio_0$D_IN; - wire m_vrg_source_prio_0$EN; - - // register m_vrg_source_prio_1 - reg [2 : 0] m_vrg_source_prio_1; - wire [2 : 0] m_vrg_source_prio_1$D_IN; - wire m_vrg_source_prio_1$EN; - - // register m_vrg_source_prio_10 - reg [2 : 0] m_vrg_source_prio_10; - wire [2 : 0] m_vrg_source_prio_10$D_IN; - wire m_vrg_source_prio_10$EN; - - // register m_vrg_source_prio_11 - reg [2 : 0] m_vrg_source_prio_11; - wire [2 : 0] m_vrg_source_prio_11$D_IN; - wire m_vrg_source_prio_11$EN; - - // register m_vrg_source_prio_12 - reg [2 : 0] m_vrg_source_prio_12; - wire [2 : 0] m_vrg_source_prio_12$D_IN; - wire m_vrg_source_prio_12$EN; - - // register m_vrg_source_prio_13 - reg [2 : 0] m_vrg_source_prio_13; - wire [2 : 0] m_vrg_source_prio_13$D_IN; - wire m_vrg_source_prio_13$EN; - - // register m_vrg_source_prio_14 - reg [2 : 0] m_vrg_source_prio_14; - wire [2 : 0] m_vrg_source_prio_14$D_IN; - wire m_vrg_source_prio_14$EN; - - // register m_vrg_source_prio_15 - reg [2 : 0] m_vrg_source_prio_15; - wire [2 : 0] m_vrg_source_prio_15$D_IN; - wire m_vrg_source_prio_15$EN; - - // register m_vrg_source_prio_16 - reg [2 : 0] m_vrg_source_prio_16; - wire [2 : 0] m_vrg_source_prio_16$D_IN; - wire m_vrg_source_prio_16$EN; - - // register m_vrg_source_prio_2 - reg [2 : 0] m_vrg_source_prio_2; - wire [2 : 0] m_vrg_source_prio_2$D_IN; - wire m_vrg_source_prio_2$EN; - - // register m_vrg_source_prio_3 - reg [2 : 0] m_vrg_source_prio_3; - wire [2 : 0] m_vrg_source_prio_3$D_IN; - wire m_vrg_source_prio_3$EN; - - // register m_vrg_source_prio_4 - reg [2 : 0] m_vrg_source_prio_4; - wire [2 : 0] m_vrg_source_prio_4$D_IN; - wire m_vrg_source_prio_4$EN; - - // register m_vrg_source_prio_5 - reg [2 : 0] m_vrg_source_prio_5; - wire [2 : 0] m_vrg_source_prio_5$D_IN; - wire m_vrg_source_prio_5$EN; - - // register m_vrg_source_prio_6 - reg [2 : 0] m_vrg_source_prio_6; - wire [2 : 0] m_vrg_source_prio_6$D_IN; - wire m_vrg_source_prio_6$EN; - - // register m_vrg_source_prio_7 - reg [2 : 0] m_vrg_source_prio_7; - wire [2 : 0] m_vrg_source_prio_7$D_IN; - wire m_vrg_source_prio_7$EN; - - // register m_vrg_source_prio_8 - reg [2 : 0] m_vrg_source_prio_8; - wire [2 : 0] m_vrg_source_prio_8$D_IN; - wire m_vrg_source_prio_8$EN; - - // register m_vrg_source_prio_9 - reg [2 : 0] m_vrg_source_prio_9; - wire [2 : 0] m_vrg_source_prio_9$D_IN; - wire m_vrg_source_prio_9$EN; - - // register m_vrg_target_threshold_0 - reg [2 : 0] m_vrg_target_threshold_0; - wire [2 : 0] m_vrg_target_threshold_0$D_IN; - wire m_vrg_target_threshold_0$EN; - - // register m_vrg_target_threshold_1 - reg [2 : 0] m_vrg_target_threshold_1; - wire [2 : 0] m_vrg_target_threshold_1$D_IN; - wire m_vrg_target_threshold_1$EN; - - // register m_vvrg_ie_0_0 - reg m_vvrg_ie_0_0; - wire m_vvrg_ie_0_0$D_IN, m_vvrg_ie_0_0$EN; - - // register m_vvrg_ie_0_1 - reg m_vvrg_ie_0_1; - wire m_vvrg_ie_0_1$D_IN, m_vvrg_ie_0_1$EN; - - // register m_vvrg_ie_0_10 - reg m_vvrg_ie_0_10; - wire m_vvrg_ie_0_10$D_IN, m_vvrg_ie_0_10$EN; - - // register m_vvrg_ie_0_11 - reg m_vvrg_ie_0_11; - wire m_vvrg_ie_0_11$D_IN, m_vvrg_ie_0_11$EN; - - // register m_vvrg_ie_0_12 - reg m_vvrg_ie_0_12; - wire m_vvrg_ie_0_12$D_IN, m_vvrg_ie_0_12$EN; - - // register m_vvrg_ie_0_13 - reg m_vvrg_ie_0_13; - wire m_vvrg_ie_0_13$D_IN, m_vvrg_ie_0_13$EN; - - // register m_vvrg_ie_0_14 - reg m_vvrg_ie_0_14; - wire m_vvrg_ie_0_14$D_IN, m_vvrg_ie_0_14$EN; - - // register m_vvrg_ie_0_15 - reg m_vvrg_ie_0_15; - wire m_vvrg_ie_0_15$D_IN, m_vvrg_ie_0_15$EN; - - // register m_vvrg_ie_0_16 - reg m_vvrg_ie_0_16; - wire m_vvrg_ie_0_16$D_IN, m_vvrg_ie_0_16$EN; - - // register m_vvrg_ie_0_2 - reg m_vvrg_ie_0_2; - wire m_vvrg_ie_0_2$D_IN, m_vvrg_ie_0_2$EN; - - // register m_vvrg_ie_0_3 - reg m_vvrg_ie_0_3; - wire m_vvrg_ie_0_3$D_IN, m_vvrg_ie_0_3$EN; - - // register m_vvrg_ie_0_4 - reg m_vvrg_ie_0_4; - wire m_vvrg_ie_0_4$D_IN, m_vvrg_ie_0_4$EN; - - // register m_vvrg_ie_0_5 - reg m_vvrg_ie_0_5; - wire m_vvrg_ie_0_5$D_IN, m_vvrg_ie_0_5$EN; - - // register m_vvrg_ie_0_6 - reg m_vvrg_ie_0_6; - wire m_vvrg_ie_0_6$D_IN, m_vvrg_ie_0_6$EN; - - // register m_vvrg_ie_0_7 - reg m_vvrg_ie_0_7; - wire m_vvrg_ie_0_7$D_IN, m_vvrg_ie_0_7$EN; - - // register m_vvrg_ie_0_8 - reg m_vvrg_ie_0_8; - wire m_vvrg_ie_0_8$D_IN, m_vvrg_ie_0_8$EN; - - // register m_vvrg_ie_0_9 - reg m_vvrg_ie_0_9; - wire m_vvrg_ie_0_9$D_IN, m_vvrg_ie_0_9$EN; - - // register m_vvrg_ie_1_0 - reg m_vvrg_ie_1_0; - wire m_vvrg_ie_1_0$D_IN, m_vvrg_ie_1_0$EN; - - // register m_vvrg_ie_1_1 - reg m_vvrg_ie_1_1; - wire m_vvrg_ie_1_1$D_IN, m_vvrg_ie_1_1$EN; - - // register m_vvrg_ie_1_10 - reg m_vvrg_ie_1_10; - wire m_vvrg_ie_1_10$D_IN, m_vvrg_ie_1_10$EN; - - // register m_vvrg_ie_1_11 - reg m_vvrg_ie_1_11; - wire m_vvrg_ie_1_11$D_IN, m_vvrg_ie_1_11$EN; - - // register m_vvrg_ie_1_12 - reg m_vvrg_ie_1_12; - wire m_vvrg_ie_1_12$D_IN, m_vvrg_ie_1_12$EN; - - // register m_vvrg_ie_1_13 - reg m_vvrg_ie_1_13; - wire m_vvrg_ie_1_13$D_IN, m_vvrg_ie_1_13$EN; - - // register m_vvrg_ie_1_14 - reg m_vvrg_ie_1_14; - wire m_vvrg_ie_1_14$D_IN, m_vvrg_ie_1_14$EN; - - // register m_vvrg_ie_1_15 - reg m_vvrg_ie_1_15; - wire m_vvrg_ie_1_15$D_IN, m_vvrg_ie_1_15$EN; - - // register m_vvrg_ie_1_16 - reg m_vvrg_ie_1_16; - wire m_vvrg_ie_1_16$D_IN, m_vvrg_ie_1_16$EN; - - // register m_vvrg_ie_1_2 - reg m_vvrg_ie_1_2; - wire m_vvrg_ie_1_2$D_IN, m_vvrg_ie_1_2$EN; - - // register m_vvrg_ie_1_3 - reg m_vvrg_ie_1_3; - wire m_vvrg_ie_1_3$D_IN, m_vvrg_ie_1_3$EN; - - // register m_vvrg_ie_1_4 - reg m_vvrg_ie_1_4; - wire m_vvrg_ie_1_4$D_IN, m_vvrg_ie_1_4$EN; - - // register m_vvrg_ie_1_5 - reg m_vvrg_ie_1_5; - wire m_vvrg_ie_1_5$D_IN, m_vvrg_ie_1_5$EN; - - // register m_vvrg_ie_1_6 - reg m_vvrg_ie_1_6; - wire m_vvrg_ie_1_6$D_IN, m_vvrg_ie_1_6$EN; - - // register m_vvrg_ie_1_7 - reg m_vvrg_ie_1_7; - wire m_vvrg_ie_1_7$D_IN, m_vvrg_ie_1_7$EN; - - // register m_vvrg_ie_1_8 - reg m_vvrg_ie_1_8; - wire m_vvrg_ie_1_8$D_IN, m_vvrg_ie_1_8$EN; - - // register m_vvrg_ie_1_9 - reg m_vvrg_ie_1_9; - wire m_vvrg_ie_1_9$D_IN, m_vvrg_ie_1_9$EN; - - // ports of submodule m_f_reset_reqs - wire m_f_reset_reqs$CLR, - m_f_reset_reqs$DEQ, - m_f_reset_reqs$EMPTY_N, - m_f_reset_reqs$ENQ, - m_f_reset_reqs$FULL_N; - - // ports of submodule m_f_reset_rsps - wire m_f_reset_rsps$CLR, - m_f_reset_rsps$DEQ, - m_f_reset_rsps$EMPTY_N, - m_f_reset_rsps$ENQ, - m_f_reset_rsps$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_addr - wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT; - wire m_slave_xactor_f_rd_addr$CLR, - m_slave_xactor_f_rd_addr$DEQ, - m_slave_xactor_f_rd_addr$EMPTY_N, - m_slave_xactor_f_rd_addr$ENQ, - m_slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_data - wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT; - wire m_slave_xactor_f_rd_data$CLR, - m_slave_xactor_f_rd_data$DEQ, - m_slave_xactor_f_rd_data$EMPTY_N, - m_slave_xactor_f_rd_data$ENQ, - m_slave_xactor_f_rd_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_addr - wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT; - wire m_slave_xactor_f_wr_addr$CLR, - m_slave_xactor_f_wr_addr$DEQ, - m_slave_xactor_f_wr_addr$EMPTY_N, - m_slave_xactor_f_wr_addr$ENQ, - m_slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; - wire m_slave_xactor_f_wr_data$CLR, - m_slave_xactor_f_wr_data$DEQ, - m_slave_xactor_f_wr_data$EMPTY_N, - m_slave_xactor_f_wr_data$ENQ, - m_slave_xactor_f_wr_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_resp - wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT; - wire m_slave_xactor_f_wr_resp$CLR, - m_slave_xactor_f_wr_resp$DEQ, - m_slave_xactor_f_wr_resp$EMPTY_N, - m_slave_xactor_f_wr_resp$ENQ, - m_slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_process_rd_req, - CAN_FIRE_RL_m_rl_process_wr_req, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_verbosity, - CAN_FIRE_show_PLIC_state, - CAN_FIRE_v_sources_0_m_interrupt_req, - CAN_FIRE_v_sources_10_m_interrupt_req, - CAN_FIRE_v_sources_11_m_interrupt_req, - CAN_FIRE_v_sources_12_m_interrupt_req, - CAN_FIRE_v_sources_13_m_interrupt_req, - CAN_FIRE_v_sources_14_m_interrupt_req, - CAN_FIRE_v_sources_15_m_interrupt_req, - CAN_FIRE_v_sources_1_m_interrupt_req, - CAN_FIRE_v_sources_2_m_interrupt_req, - CAN_FIRE_v_sources_3_m_interrupt_req, - CAN_FIRE_v_sources_4_m_interrupt_req, - CAN_FIRE_v_sources_5_m_interrupt_req, - CAN_FIRE_v_sources_6_m_interrupt_req, - CAN_FIRE_v_sources_7_m_interrupt_req, - CAN_FIRE_v_sources_8_m_interrupt_req, - CAN_FIRE_v_sources_9_m_interrupt_req, - WILL_FIRE_RL_m_rl_process_rd_req, - WILL_FIRE_RL_m_rl_process_wr_req, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_verbosity, - WILL_FIRE_show_PLIC_state, - WILL_FIRE_v_sources_0_m_interrupt_req, - WILL_FIRE_v_sources_10_m_interrupt_req, - WILL_FIRE_v_sources_11_m_interrupt_req, - WILL_FIRE_v_sources_12_m_interrupt_req, - WILL_FIRE_v_sources_13_m_interrupt_req, - WILL_FIRE_v_sources_14_m_interrupt_req, - WILL_FIRE_v_sources_15_m_interrupt_req, - WILL_FIRE_v_sources_1_m_interrupt_req, - WILL_FIRE_v_sources_2_m_interrupt_req, - WILL_FIRE_v_sources_3_m_interrupt_req, - WILL_FIRE_v_sources_4_m_interrupt_req, - WILL_FIRE_v_sources_5_m_interrupt_req, - WILL_FIRE_v_sources_6_m_interrupt_req, - WILL_FIRE_v_sources_7_m_interrupt_req, - WILL_FIRE_v_sources_8_m_interrupt_req, - WILL_FIRE_v_sources_9_m_interrupt_req; - - // inputs to muxes for submodule ports - wire MUX_m_vrg_servicing_source_0$write_1__SEL_1, - MUX_m_vrg_servicing_source_1$write_1__SEL_1, - MUX_m_vrg_source_busy_0$write_1__SEL_2, - MUX_m_vrg_source_busy_1$write_1__SEL_1, - MUX_m_vrg_source_busy_1$write_1__SEL_2, - MUX_m_vrg_source_busy_10$write_1__SEL_1, - MUX_m_vrg_source_busy_10$write_1__SEL_2, - MUX_m_vrg_source_busy_11$write_1__SEL_1, - MUX_m_vrg_source_busy_11$write_1__SEL_2, - MUX_m_vrg_source_busy_12$write_1__SEL_1, - MUX_m_vrg_source_busy_12$write_1__SEL_2, - MUX_m_vrg_source_busy_13$write_1__SEL_1, - MUX_m_vrg_source_busy_13$write_1__SEL_2, - MUX_m_vrg_source_busy_14$write_1__SEL_1, - MUX_m_vrg_source_busy_14$write_1__SEL_2, - MUX_m_vrg_source_busy_15$write_1__SEL_1, - MUX_m_vrg_source_busy_15$write_1__SEL_2, - MUX_m_vrg_source_busy_16$write_1__SEL_1, - MUX_m_vrg_source_busy_16$write_1__SEL_2, - MUX_m_vrg_source_busy_2$write_1__SEL_1, - MUX_m_vrg_source_busy_2$write_1__SEL_2, - MUX_m_vrg_source_busy_3$write_1__SEL_1, - MUX_m_vrg_source_busy_3$write_1__SEL_2, - MUX_m_vrg_source_busy_4$write_1__SEL_1, - MUX_m_vrg_source_busy_4$write_1__SEL_2, - MUX_m_vrg_source_busy_5$write_1__SEL_1, - MUX_m_vrg_source_busy_5$write_1__SEL_2, - MUX_m_vrg_source_busy_6$write_1__SEL_1, - MUX_m_vrg_source_busy_6$write_1__SEL_2, - MUX_m_vrg_source_busy_7$write_1__SEL_1, - MUX_m_vrg_source_busy_7$write_1__SEL_2, - MUX_m_vrg_source_busy_8$write_1__SEL_1, - MUX_m_vrg_source_busy_8$write_1__SEL_2, - MUX_m_vrg_source_busy_9$write_1__SEL_1, - MUX_m_vrg_source_busy_9$write_1__SEL_2, - MUX_m_vrg_source_prio_0$write_1__SEL_1, - MUX_m_vrg_source_prio_1$write_1__SEL_1, - MUX_m_vrg_source_prio_10$write_1__SEL_1, - MUX_m_vrg_source_prio_11$write_1__SEL_1, - MUX_m_vrg_source_prio_12$write_1__SEL_1, - MUX_m_vrg_source_prio_13$write_1__SEL_1, - MUX_m_vrg_source_prio_14$write_1__SEL_1, - MUX_m_vrg_source_prio_15$write_1__SEL_1, - MUX_m_vrg_source_prio_16$write_1__SEL_1, - MUX_m_vrg_source_prio_2$write_1__SEL_1, - MUX_m_vrg_source_prio_3$write_1__SEL_1, - MUX_m_vrg_source_prio_4$write_1__SEL_1, - MUX_m_vrg_source_prio_5$write_1__SEL_1, - MUX_m_vrg_source_prio_6$write_1__SEL_1, - MUX_m_vrg_source_prio_7$write_1__SEL_1, - MUX_m_vrg_source_prio_8$write_1__SEL_1, - MUX_m_vrg_source_prio_9$write_1__SEL_1, - MUX_m_vrg_target_threshold_0$write_1__SEL_1, - MUX_m_vrg_target_threshold_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__VAL_1, - MUX_m_vvrg_ie_0_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_1$write_1__VAL_1, - MUX_m_vvrg_ie_0_10$write_1__SEL_1, - MUX_m_vvrg_ie_0_10$write_1__VAL_1, - MUX_m_vvrg_ie_0_11$write_1__SEL_1, - MUX_m_vvrg_ie_0_11$write_1__VAL_1, - MUX_m_vvrg_ie_0_12$write_1__SEL_1, - MUX_m_vvrg_ie_0_12$write_1__VAL_1, - MUX_m_vvrg_ie_0_13$write_1__SEL_1, - MUX_m_vvrg_ie_0_13$write_1__VAL_1, - MUX_m_vvrg_ie_0_14$write_1__SEL_1, - MUX_m_vvrg_ie_0_14$write_1__VAL_1, - MUX_m_vvrg_ie_0_15$write_1__SEL_1, - MUX_m_vvrg_ie_0_15$write_1__VAL_1, - MUX_m_vvrg_ie_0_16$write_1__SEL_1, - MUX_m_vvrg_ie_0_16$write_1__VAL_1, - MUX_m_vvrg_ie_0_2$write_1__SEL_1, - MUX_m_vvrg_ie_0_2$write_1__VAL_1, - MUX_m_vvrg_ie_0_3$write_1__SEL_1, - MUX_m_vvrg_ie_0_3$write_1__VAL_1, - MUX_m_vvrg_ie_0_4$write_1__SEL_1, - MUX_m_vvrg_ie_0_4$write_1__VAL_1, - MUX_m_vvrg_ie_0_5$write_1__SEL_1, - MUX_m_vvrg_ie_0_5$write_1__VAL_1, - MUX_m_vvrg_ie_0_6$write_1__SEL_1, - MUX_m_vvrg_ie_0_6$write_1__VAL_1, - MUX_m_vvrg_ie_0_7$write_1__SEL_1, - MUX_m_vvrg_ie_0_7$write_1__VAL_1, - MUX_m_vvrg_ie_0_8$write_1__SEL_1, - MUX_m_vvrg_ie_0_8$write_1__VAL_1, - MUX_m_vvrg_ie_0_9$write_1__SEL_1, - MUX_m_vvrg_ie_0_9$write_1__VAL_1, - MUX_m_vvrg_ie_1_0$write_1__SEL_1, - MUX_m_vvrg_ie_1_0$write_1__VAL_1, - MUX_m_vvrg_ie_1_1$write_1__SEL_1, - MUX_m_vvrg_ie_1_1$write_1__VAL_1, - MUX_m_vvrg_ie_1_10$write_1__SEL_1, - MUX_m_vvrg_ie_1_10$write_1__VAL_1, - MUX_m_vvrg_ie_1_11$write_1__SEL_1, - MUX_m_vvrg_ie_1_11$write_1__VAL_1, - MUX_m_vvrg_ie_1_12$write_1__SEL_1, - MUX_m_vvrg_ie_1_12$write_1__VAL_1, - MUX_m_vvrg_ie_1_13$write_1__SEL_1, - MUX_m_vvrg_ie_1_13$write_1__VAL_1, - MUX_m_vvrg_ie_1_14$write_1__SEL_1, - MUX_m_vvrg_ie_1_14$write_1__VAL_1, - MUX_m_vvrg_ie_1_15$write_1__SEL_1, - MUX_m_vvrg_ie_1_15$write_1__VAL_1, - MUX_m_vvrg_ie_1_16$write_1__SEL_1, - MUX_m_vvrg_ie_1_16$write_1__VAL_1, - MUX_m_vvrg_ie_1_2$write_1__SEL_1, - MUX_m_vvrg_ie_1_2$write_1__VAL_1, - MUX_m_vvrg_ie_1_3$write_1__SEL_1, - MUX_m_vvrg_ie_1_3$write_1__VAL_1, - MUX_m_vvrg_ie_1_4$write_1__SEL_1, - MUX_m_vvrg_ie_1_4$write_1__VAL_1, - MUX_m_vvrg_ie_1_5$write_1__SEL_1, - MUX_m_vvrg_ie_1_5$write_1__VAL_1, - MUX_m_vvrg_ie_1_6$write_1__SEL_1, - MUX_m_vvrg_ie_1_6$write_1__VAL_1, - MUX_m_vvrg_ie_1_7$write_1__SEL_1, - MUX_m_vvrg_ie_1_7$write_1__VAL_1, - MUX_m_vvrg_ie_1_8$write_1__SEL_1, - MUX_m_vvrg_ie_1_8$write_1__VAL_1, - MUX_m_vvrg_ie_1_9$write_1__SEL_1, - MUX_m_vvrg_ie_1_9$write_1__VAL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h75676; - reg [31 : 0] v__h75874; - reg [31 : 0] v__h76072; - reg [31 : 0] v__h76270; - reg [31 : 0] v__h76468; - reg [31 : 0] v__h76666; - reg [31 : 0] v__h76864; - reg [31 : 0] v__h77062; - reg [31 : 0] v__h77260; - reg [31 : 0] v__h77458; - reg [31 : 0] v__h77656; - reg [31 : 0] v__h77854; - reg [31 : 0] v__h78052; - reg [31 : 0] v__h78250; - reg [31 : 0] v__h78448; - reg [31 : 0] v__h78646; - reg [31 : 0] v__h6144; - reg [31 : 0] v__h13080; - reg [31 : 0] v__h13265; - reg [31 : 0] v__h13463; - reg [31 : 0] v__h13713; - reg [31 : 0] v__h18186; - reg [31 : 0] v__h23802; - reg [31 : 0] v__h25975; - reg [31 : 0] v__h24056; - reg [31 : 0] v__h26250; - reg [31 : 0] v__h26463; - reg [31 : 0] v__h26740; - reg [31 : 0] v__h26968; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h28048; - reg [31 : 0] v__h67030; - reg [31 : 0] v__h67318; - reg [31 : 0] v__h67847; - reg [31 : 0] v__h67933; - reg [31 : 0] v__h68132; - reg [31 : 0] v__h68353; - reg [31 : 0] v__h74690; - reg [31 : 0] v__h74800; - reg [31 : 0] v__h74913; - reg [31 : 0] v__h6138; - reg [31 : 0] v__h13074; - reg [31 : 0] v__h13259; - reg [31 : 0] v__h13457; - reg [31 : 0] v__h13707; - reg [31 : 0] v__h18180; - reg [31 : 0] v__h23796; - reg [31 : 0] v__h24050; - reg [31 : 0] v__h25969; - reg [31 : 0] v__h26244; - reg [31 : 0] v__h26457; - reg [31 : 0] v__h26734; - reg [31 : 0] v__h26962; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28042; - reg [31 : 0] v__h67024; - reg [31 : 0] v__h67312; - reg [31 : 0] v__h67841; - reg [31 : 0] v__h67927; - reg [31 : 0] v__h68126; - reg [31 : 0] v__h68347; - reg [31 : 0] v__h74684; - reg [31 : 0] v__h74794; - reg [31 : 0] v__h74907; - reg [31 : 0] v__h75670; - reg [31 : 0] v__h75868; - reg [31 : 0] v__h76066; - reg [31 : 0] v__h76264; - reg [31 : 0] v__h76462; - reg [31 : 0] v__h76660; - reg [31 : 0] v__h76858; - reg [31 : 0] v__h77056; - reg [31 : 0] v__h77254; - reg [31 : 0] v__h77452; - reg [31 : 0] v__h77650; - reg [31 : 0] v__h77848; - reg [31 : 0] v__h78046; - reg [31 : 0] v__h78244; - reg [31 : 0] v__h78442; - reg [31 : 0] v__h78640; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] y_avValue_fst__h26148; - reg [4 : 0] x__h24011, x__h67487; - reg [2 : 0] x__h13493, x__h23832; - reg [1 : 0] v__h67107, y_avValue_snd__h26149; - reg CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - wire [63 : 0] addr_offset__h13216, - addr_offset__h26929, - rdata___1__h26404, - rdata__h26202, - v__h13422, - v__h13671, - v__h18144, - v__h23761, - v__h25455, - v__h25474, - x__h26361, - y_avValue_fst__h26094, - y_avValue_fst__h26115, - y_avValue_fst__h26127, - y_avValue_fst__h26143, - y_avValue_fst__h26159, - y_avValue_fst__h26164, - y_avValue_fst__h26175, - y_avValue_fst__h26180, - y_avValue_fst__h26194; - wire [31 : 0] v_ie__h18147, - v_ip__h13674, - wdata32__h26930, - x__h23673, - x__h67110; - wire [9 : 0] source_id__h15665, - source_id__h15772, - source_id__h15845, - source_id__h15918, - source_id__h15991, - source_id__h16064, - source_id__h16137, - source_id__h16210, - source_id__h16283, - source_id__h16356, - source_id__h16429, - source_id__h16502, - source_id__h16575, - source_id__h16648, - source_id__h16721, - source_id__h16794, - source_id__h16867, - source_id__h16940, - source_id__h17013, - source_id__h17086, - source_id__h17159, - source_id__h17232, - source_id__h17305, - source_id__h17378, - source_id__h17451, - source_id__h17524, - source_id__h17597, - source_id__h17670, - source_id__h17743, - source_id__h17816, - source_id__h17889, - source_id__h20137, - source_id__h20313, - source_id__h20421, - source_id__h20529, - source_id__h20637, - source_id__h20745, - source_id__h20853, - source_id__h20961, - source_id__h21069, - source_id__h21177, - source_id__h21285, - source_id__h21393, - source_id__h21501, - source_id__h21609, - source_id__h21717, - source_id__h21825, - source_id__h21933, - source_id__h22041, - source_id__h22149, - source_id__h22257, - source_id__h22365, - source_id__h22473, - source_id__h22581, - source_id__h22689, - source_id__h22797, - source_id__h22905, - source_id__h23013, - source_id__h23121, - source_id__h23229, - source_id__h23337, - source_id__h23445, - source_id__h29475, - source_id__h30685, - source_id__h31895, - source_id__h33105, - source_id__h34315, - source_id__h35525, - source_id__h36735, - source_id__h37945, - source_id__h39155, - source_id__h40365, - source_id__h41575, - source_id__h42785, - source_id__h43995, - source_id__h45205, - source_id__h46415, - source_id__h47625, - source_id__h48835, - source_id__h50045, - source_id__h51255, - source_id__h52465, - source_id__h53675, - source_id__h54885, - source_id__h56095, - source_id__h57305, - source_id__h58515, - source_id__h59725, - source_id__h60935, - source_id__h62145, - source_id__h63355, - source_id__h64565, - source_id__h65775, - source_id__h67436, - source_id_base__h13630, - source_id_base__h28148; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71313, - b__h73318, - max_id__h23959; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71312, - a__h73317; - wire [1 : 0] rresp__h26203, - v__h26934, - v__h27094, - v__h27107, - v__h27942, - v__h27961, - v__h28125, - v__h28144, - v__h67144, - v__h67432, - v__h67476, - y_avValue_snd__h26095, - y_avValue_snd__h26116, - y_avValue_snd__h26128, - y_avValue_snd__h26144, - y_avValue_snd__h26160, - y_avValue_snd__h26165, - y_avValue_snd__h26176, - y_avValue_snd__h26181, - y_avValue_snd__h26195; - wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, - NOT_m_cfg_verbosity_read_ULE_1_5___d16, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982, - NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313, - NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321, - NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329, - NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337, - NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345, - NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353, - NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361, - NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242, - NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249, - NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257, - NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265, - NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273, - NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281, - NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289, - NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297, - NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305, - _dfoo1, - _dfoo10, - _dfoo100, - _dfoo1000, - _dfoo1001, - _dfoo1002, - _dfoo1003, - _dfoo1004, - _dfoo1005, - _dfoo1006, - _dfoo1007, - _dfoo1008, - _dfoo1009, - _dfoo1010, - _dfoo1011, - _dfoo1012, - _dfoo1013, - _dfoo1014, - _dfoo1015, - _dfoo1016, - _dfoo1017, - _dfoo1018, - _dfoo1019, - _dfoo102, - _dfoo1020, - _dfoo1022, - _dfoo1024, - _dfoo1026, - _dfoo1028, - _dfoo1030, - _dfoo1032, - _dfoo1034, - _dfoo1036, - _dfoo1038, - _dfoo104, - _dfoo1040, - _dfoo1042, - _dfoo1044, - _dfoo1046, - _dfoo1048, - _dfoo1050, - _dfoo1052, - _dfoo1054, - _dfoo1056, - _dfoo1058, - _dfoo106, - _dfoo1060, - _dfoo1062, - _dfoo1064, - _dfoo1066, - _dfoo1068, - _dfoo1070, - _dfoo1072, - _dfoo1074, - _dfoo1076, - _dfoo1078, - _dfoo108, - _dfoo1080, - _dfoo1082, - _dfoo1084, - _dfoo1086, - _dfoo1088, - _dfoo1089, - _dfoo1090, - _dfoo1091, - _dfoo1092, - _dfoo1093, - _dfoo1094, - _dfoo1095, - _dfoo1096, - _dfoo1097, - _dfoo1098, - _dfoo1099, - _dfoo11, - _dfoo110, - _dfoo1100, - _dfoo1101, - _dfoo1102, - _dfoo1103, - _dfoo1104, - _dfoo1105, - _dfoo1106, - _dfoo1107, - _dfoo1108, - _dfoo1109, - _dfoo1110, - _dfoo1111, - _dfoo1112, - _dfoo1113, - _dfoo1114, - _dfoo1115, - _dfoo1116, - _dfoo1117, - _dfoo1118, - _dfoo1119, - _dfoo112, - _dfoo1120, - _dfoo1121, - _dfoo1122, - _dfoo1123, - _dfoo1124, - _dfoo1125, - _dfoo1126, - _dfoo1127, - _dfoo1128, - _dfoo1129, - _dfoo1130, - _dfoo1131, - _dfoo1132, - _dfoo1133, - _dfoo1134, - _dfoo1135, - _dfoo1136, - _dfoo1137, - _dfoo1138, - _dfoo1139, - _dfoo114, - _dfoo1140, - _dfoo1141, - _dfoo1142, - _dfoo1143, - _dfoo1144, - _dfoo1145, - _dfoo1146, - _dfoo1147, - _dfoo1148, - _dfoo1149, - _dfoo1150, - _dfoo1151, - _dfoo1152, - _dfoo1153, - _dfoo1154, - _dfoo1155, - _dfoo1156, - _dfoo1158, - _dfoo116, - _dfoo1160, - _dfoo1162, - _dfoo1164, - _dfoo1166, - _dfoo1168, - _dfoo1170, - _dfoo1172, - _dfoo1174, - _dfoo1176, - _dfoo1178, - _dfoo118, - _dfoo1180, - _dfoo1182, - _dfoo1184, - _dfoo1186, - _dfoo1188, - _dfoo1190, - _dfoo1192, - _dfoo1194, - _dfoo1196, - _dfoo1198, - _dfoo12, - _dfoo120, - _dfoo1200, - _dfoo1202, - _dfoo1204, - _dfoo1206, - _dfoo1208, - _dfoo1210, - _dfoo1212, - _dfoo1214, - _dfoo1216, - _dfoo1218, - _dfoo122, - _dfoo1220, - _dfoo1222, - _dfoo1224, - _dfoo1225, - _dfoo1226, - _dfoo1227, - _dfoo1228, - _dfoo1229, - _dfoo1230, - _dfoo1231, - _dfoo1232, - _dfoo1233, - _dfoo1234, - _dfoo1235, - _dfoo1236, - _dfoo1237, - _dfoo1238, - _dfoo1239, - _dfoo124, - _dfoo1240, - _dfoo1241, - _dfoo1242, - _dfoo1243, - _dfoo1244, - _dfoo1245, - _dfoo1246, - _dfoo1247, - _dfoo1248, - _dfoo1249, - _dfoo1250, - _dfoo1251, - _dfoo1252, - _dfoo1253, - _dfoo1254, - _dfoo1255, - _dfoo1256, - _dfoo1257, - _dfoo1258, - _dfoo1259, - _dfoo126, - _dfoo1260, - _dfoo1261, - _dfoo1262, - _dfoo1263, - _dfoo1264, - _dfoo1265, - _dfoo1266, - _dfoo1267, - _dfoo1268, - _dfoo1269, - _dfoo1270, - _dfoo1271, - _dfoo1272, - _dfoo1273, - _dfoo1274, - _dfoo1275, - _dfoo1276, - _dfoo1277, - _dfoo1278, - _dfoo1279, - _dfoo128, - _dfoo1280, - _dfoo1281, - _dfoo1282, - _dfoo1283, - _dfoo1284, - _dfoo1285, - _dfoo1286, - _dfoo1287, - _dfoo1288, - _dfoo1289, - _dfoo1290, - _dfoo1291, - _dfoo1292, - _dfoo1294, - _dfoo1296, - _dfoo1298, - _dfoo13, - _dfoo130, - _dfoo1300, - _dfoo1302, - _dfoo1304, - _dfoo1306, - _dfoo1308, - _dfoo1310, - _dfoo1312, - _dfoo1314, - _dfoo1316, - _dfoo1318, - _dfoo132, - _dfoo1320, - _dfoo1322, - _dfoo1324, - _dfoo1326, - _dfoo1328, - _dfoo1330, - _dfoo1332, - _dfoo1334, - _dfoo1336, - _dfoo1338, - _dfoo134, - _dfoo1340, - _dfoo1342, - _dfoo1344, - _dfoo1346, - _dfoo1348, - _dfoo1350, - _dfoo1352, - _dfoo1354, - _dfoo1356, - _dfoo1358, - _dfoo136, - _dfoo1360, - _dfoo1361, - _dfoo1362, - _dfoo1363, - _dfoo1364, - _dfoo1365, - _dfoo1366, - _dfoo1367, - _dfoo1368, - _dfoo1369, - _dfoo137, - _dfoo1370, - _dfoo1371, - _dfoo1372, - _dfoo1373, - _dfoo1374, - _dfoo1375, - _dfoo1376, - _dfoo1377, - _dfoo1378, - _dfoo1379, - _dfoo138, - _dfoo1380, - _dfoo1381, - _dfoo1382, - _dfoo1383, - _dfoo1384, - _dfoo1385, - _dfoo1386, - _dfoo1387, - _dfoo1388, - _dfoo1389, - _dfoo139, - _dfoo1390, - _dfoo1391, - _dfoo1392, - _dfoo1393, - _dfoo1394, - _dfoo1395, - _dfoo1396, - _dfoo1397, - _dfoo1398, - _dfoo1399, - _dfoo14, - _dfoo140, - _dfoo1400, - _dfoo1401, - _dfoo1402, - _dfoo1403, - _dfoo1404, - _dfoo1405, - _dfoo1406, - _dfoo1407, - _dfoo1408, - _dfoo1409, - _dfoo141, - _dfoo1410, - _dfoo1411, - _dfoo1412, - _dfoo1413, - _dfoo1414, - _dfoo1415, - _dfoo1416, - _dfoo1417, - _dfoo1418, - _dfoo1419, - _dfoo142, - _dfoo1420, - _dfoo1421, - _dfoo1422, - _dfoo1423, - _dfoo1424, - _dfoo1425, - _dfoo1426, - _dfoo1427, - _dfoo1428, - _dfoo143, - _dfoo1430, - _dfoo1432, - _dfoo1434, - _dfoo1436, - _dfoo1438, - _dfoo144, - _dfoo1440, - _dfoo1442, - _dfoo1444, - _dfoo1446, - _dfoo1448, - _dfoo145, - _dfoo1450, - _dfoo1452, - _dfoo1454, - _dfoo1456, - _dfoo1458, - _dfoo146, - _dfoo1460, - _dfoo1462, - _dfoo1464, - _dfoo1466, - _dfoo1468, - _dfoo147, - _dfoo1470, - _dfoo1472, - _dfoo1474, - _dfoo1476, - _dfoo1478, - _dfoo148, - _dfoo1480, - _dfoo1482, - _dfoo1484, - _dfoo1486, - _dfoo1488, - _dfoo149, - _dfoo1490, - _dfoo1492, - _dfoo1494, - _dfoo1496, - _dfoo1497, - _dfoo1498, - _dfoo1499, - _dfoo15, - _dfoo150, - _dfoo1500, - _dfoo1501, - _dfoo1502, - _dfoo1503, - _dfoo1504, - _dfoo1505, - _dfoo1506, - _dfoo1507, - _dfoo1508, - _dfoo1509, - _dfoo151, - _dfoo1510, - _dfoo1511, - _dfoo1512, - _dfoo1513, - _dfoo1514, - _dfoo1515, - _dfoo1516, - _dfoo1517, - _dfoo1518, - _dfoo1519, - _dfoo152, - _dfoo1520, - _dfoo1521, - _dfoo1522, - _dfoo1523, - _dfoo1524, - _dfoo1525, - _dfoo1526, - _dfoo1527, - _dfoo1528, - _dfoo1529, - _dfoo153, - _dfoo1530, - _dfoo1531, - _dfoo1532, - _dfoo1533, - _dfoo1534, - _dfoo1535, - _dfoo1536, - _dfoo1537, - _dfoo1538, - _dfoo1539, - _dfoo154, - _dfoo1540, - _dfoo1541, - _dfoo1542, - _dfoo1543, - _dfoo1544, - _dfoo1545, - _dfoo1546, - _dfoo1547, - _dfoo1548, - _dfoo1549, - _dfoo155, - _dfoo1550, - _dfoo1551, - _dfoo1552, - _dfoo1553, - _dfoo1554, - _dfoo1555, - _dfoo1556, - _dfoo1557, - _dfoo1558, - _dfoo1559, - _dfoo156, - _dfoo1560, - _dfoo1561, - _dfoo1562, - _dfoo1563, - _dfoo1564, - _dfoo1566, - _dfoo1568, - _dfoo157, - _dfoo1570, - _dfoo1572, - _dfoo1574, - _dfoo1576, - _dfoo1578, - _dfoo158, - _dfoo1580, - _dfoo1582, - _dfoo1584, - _dfoo1586, - _dfoo1588, - _dfoo159, - _dfoo1590, - _dfoo1592, - _dfoo1594, - _dfoo1596, - _dfoo1598, - _dfoo16, - _dfoo160, - _dfoo1600, - _dfoo1602, - _dfoo1604, - _dfoo1606, - _dfoo1608, - _dfoo161, - _dfoo1610, - _dfoo1612, - _dfoo1614, - _dfoo1616, - _dfoo1618, - _dfoo162, - _dfoo1620, - _dfoo1622, - _dfoo1624, - _dfoo1626, - _dfoo1628, - _dfoo163, - _dfoo1630, - _dfoo1632, - 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m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, - m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method show_PLIC_state - assign RDY_show_PLIC_state = 1'd1 ; - assign CAN_FIRE_show_PLIC_state = 1'd1 ; - assign WILL_FIRE_show_PLIC_state = EN_show_PLIC_state ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // action method v_sources_0_m_interrupt_req - assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - - // action method v_sources_1_m_interrupt_req - assign CAN_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - - // action method v_sources_2_m_interrupt_req - assign CAN_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - - // action method v_sources_3_m_interrupt_req - assign CAN_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - - // action method v_sources_4_m_interrupt_req - assign CAN_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - - // action method v_sources_5_m_interrupt_req - assign CAN_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - - // action method v_sources_6_m_interrupt_req - assign CAN_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - - // action method v_sources_7_m_interrupt_req - assign CAN_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - - // action method v_sources_8_m_interrupt_req - assign CAN_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - - // action method v_sources_9_m_interrupt_req - assign CAN_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - - // action method v_sources_10_m_interrupt_req - assign CAN_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - - // action method v_sources_11_m_interrupt_req - assign CAN_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - - // action method v_sources_12_m_interrupt_req - assign CAN_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - - // action method v_sources_13_m_interrupt_req - assign CAN_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - - // action method v_sources_14_m_interrupt_req - assign CAN_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - - // action method v_sources_15_m_interrupt_req - assign CAN_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - - // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71312 > m_vrg_target_threshold_0 ; - - // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73317 > m_vrg_target_threshold_1 ; - - // submodule m_f_reset_reqs - FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_reqs$ENQ), - .DEQ(m_f_reset_reqs$DEQ), - .CLR(m_f_reset_reqs$CLR), - .FULL_N(m_f_reset_reqs$FULL_N), - .EMPTY_N(m_f_reset_reqs$EMPTY_N)); - - // submodule m_f_reset_rsps - FIFO20 #(.guarded(32'd1)) m_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_rsps$ENQ), - .DEQ(m_f_reset_rsps$DEQ), - .CLR(m_f_reset_rsps$CLR), - .FULL_N(m_f_reset_rsps$FULL_N), - .EMPTY_N(m_f_reset_rsps$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_addr$D_IN), - .ENQ(m_slave_xactor_f_rd_addr$ENQ), - .DEQ(m_slave_xactor_f_rd_addr$DEQ), - .CLR(m_slave_xactor_f_rd_addr$CLR), - .D_OUT(m_slave_xactor_f_rd_addr$D_OUT), - .FULL_N(m_slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_data$D_IN), - .ENQ(m_slave_xactor_f_rd_data$ENQ), - .DEQ(m_slave_xactor_f_rd_data$DEQ), - .CLR(m_slave_xactor_f_rd_data$CLR), - .D_OUT(m_slave_xactor_f_rd_data$D_OUT), - .FULL_N(m_slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_addr$D_IN), - .ENQ(m_slave_xactor_f_wr_addr$ENQ), - .DEQ(m_slave_xactor_f_wr_addr$DEQ), - .CLR(m_slave_xactor_f_wr_addr$CLR), - .D_OUT(m_slave_xactor_f_wr_addr$D_OUT), - .FULL_N(m_slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_data$D_IN), - .ENQ(m_slave_xactor_f_wr_data$ENQ), - .DEQ(m_slave_xactor_f_wr_data$DEQ), - .CLR(m_slave_xactor_f_wr_data$CLR), - .D_OUT(m_slave_xactor_f_wr_data$D_OUT), - .FULL_N(m_slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_resp$D_IN), - .ENQ(m_slave_xactor_f_wr_resp$ENQ), - .DEQ(m_slave_xactor_f_wr_resp$DEQ), - .CLR(m_slave_xactor_f_wr_resp$CLR), - .D_OUT(m_slave_xactor_f_wr_resp$D_OUT), - .FULL_N(m_slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = - m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - - // rule RL_m_rl_process_rd_req - assign CAN_FIRE_RL_m_rl_process_rd_req = - m_slave_xactor_f_rd_addr$EMPTY_N && - m_slave_xactor_f_rd_data$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - - // rule RL_m_rl_process_wr_req - assign CAN_FIRE_RL_m_rl_process_wr_req = - m_slave_xactor_f_wr_addr$EMPTY_N && - m_slave_xactor_f_wr_data$EMPTY_N && - m_slave_xactor_f_wr_resp$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_wr_req = - CAN_FIRE_RL_m_rl_process_wr_req && - !WILL_FIRE_RL_m_rl_process_rd_req ; - - // inputs to muxes for submodule ports - assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; - assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; - assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; - assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; - assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; - assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; - assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; - assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; - assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; - assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; - assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; - assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; - assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; - assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; - assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; - assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; - assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; - assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; - assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; - assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; - assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ; - assign MUX_m_vvrg_ie_0_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ; - assign MUX_m_vvrg_ie_0_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ; - assign MUX_m_vvrg_ie_0_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ; - assign MUX_m_vvrg_ie_0_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ; - assign MUX_m_vvrg_ie_0_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ; - assign MUX_m_vvrg_ie_0_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ; - assign MUX_m_vvrg_ie_0_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ; - assign MUX_m_vvrg_ie_0_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ; - assign MUX_m_vvrg_ie_0_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ; - assign MUX_m_vvrg_ie_0_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ; - assign MUX_m_vvrg_ie_0_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ; - assign MUX_m_vvrg_ie_0_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ; - assign MUX_m_vvrg_ie_0_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ; - assign MUX_m_vvrg_ie_0_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ; - assign MUX_m_vvrg_ie_0_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ; - assign MUX_m_vvrg_ie_1_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ; - assign MUX_m_vvrg_ie_1_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ; - assign MUX_m_vvrg_ie_1_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ; - assign MUX_m_vvrg_ie_1_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ; - assign MUX_m_vvrg_ie_1_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ; - assign MUX_m_vvrg_ie_1_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ; - assign MUX_m_vvrg_ie_1_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ; - assign MUX_m_vvrg_ie_1_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ; - assign MUX_m_vvrg_ie_1_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ; - assign MUX_m_vvrg_ie_1_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ; - assign MUX_m_vvrg_ie_1_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ; - assign MUX_m_vvrg_ie_1_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ; - assign MUX_m_vvrg_ie_1_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ; - assign MUX_m_vvrg_ie_1_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ; - assign MUX_m_vvrg_ie_1_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ; - assign MUX_m_vvrg_ie_1_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ; - assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; - assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2040 ; - assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2038 ; - assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2020 ; - assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2018 ; - assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2016 ; - assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2014 ; - assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2012 ; - assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2010 ; - assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2008 ; - assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2036 ; - assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2034 ; - assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2032 ; - assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2030 ; - assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2028 ; - assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2026 ; - assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2024 ; - assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2022 ; - assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2006 ; - assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2004 ; - assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1986 ; - assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1984 ; - assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1982 ; - assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1980 ; - assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1978 ; - assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1976 ; - assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1974 ; - assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2002 ; - assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2000 ; - assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1998 ; - assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1996 ; - assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1994 ; - assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1992 ; - assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1990 ; - assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1988 ; - - // register m_cfg_verbosity - assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign m_cfg_verbosity$EN = EN_set_verbosity ; - - // register m_rg_addr_base - assign m_rg_addr_base$D_IN = set_addr_map_addr_base ; - assign m_rg_addr_base$EN = EN_set_addr_map ; - - // register m_rg_addr_lim - assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign m_rg_addr_lim$EN = EN_set_addr_map ; - - // register m_vrg_servicing_source_0 - assign m_vrg_servicing_source_0$D_IN = - MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_servicing_source_1 - assign m_vrg_servicing_source_1$D_IN = - MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_0 - assign m_vrg_source_busy_0$D_IN = - !MUX_m_vrg_source_busy_0$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_1 - assign m_vrg_source_busy_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_10 - assign m_vrg_source_busy_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_11 - assign m_vrg_source_busy_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_12 - assign m_vrg_source_busy_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_13 - assign m_vrg_source_busy_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_14 - assign m_vrg_source_busy_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_15 - assign m_vrg_source_busy_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_16 - assign m_vrg_source_busy_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_2 - assign m_vrg_source_busy_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_3 - assign m_vrg_source_busy_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_4 - assign m_vrg_source_busy_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_5 - assign m_vrg_source_busy_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_6 - assign m_vrg_source_busy_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_7 - assign m_vrg_source_busy_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_8 - assign m_vrg_source_busy_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_9 - assign m_vrg_source_busy_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_0 - assign m_vrg_source_ip_0$D_IN = 1'd0 ; - assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_1 - assign m_vrg_source_ip_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_0_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_1$EN = - !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_10 - assign m_vrg_source_ip_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_9_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_10$EN = - !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_11 - assign m_vrg_source_ip_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_10_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_11$EN = - !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_12 - assign m_vrg_source_ip_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_11_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_12$EN = - !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_13 - assign m_vrg_source_ip_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_12_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_13$EN = - !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_14 - assign m_vrg_source_ip_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_13_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_14$EN = - !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_15 - assign m_vrg_source_ip_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_14_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_15$EN = - !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_16 - assign m_vrg_source_ip_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_15_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_16$EN = - !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_2 - assign m_vrg_source_ip_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_1_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_2$EN = - !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_3 - assign m_vrg_source_ip_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_2_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_3$EN = - !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_4 - assign m_vrg_source_ip_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_3_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_4$EN = - !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_5 - assign m_vrg_source_ip_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_4_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_5$EN = - !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_6 - assign m_vrg_source_ip_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_5_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_6$EN = - !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_7 - assign m_vrg_source_ip_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_6_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_7$EN = - !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_8 - assign m_vrg_source_ip_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_7_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_8$EN = - !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_9 - assign m_vrg_source_ip_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_8_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_9$EN = - !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_0 - assign m_vrg_source_prio_0$D_IN = - MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_1 - assign m_vrg_source_prio_1$D_IN = - MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_10 - assign m_vrg_source_prio_10$D_IN = - MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_11 - assign m_vrg_source_prio_11$D_IN = - MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_12 - assign m_vrg_source_prio_12$D_IN = - MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_13 - assign m_vrg_source_prio_13$D_IN = - MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_14 - assign m_vrg_source_prio_14$D_IN = - MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_15 - assign m_vrg_source_prio_15$D_IN = - MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_16 - assign m_vrg_source_prio_16$D_IN = - MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_2 - assign m_vrg_source_prio_2$D_IN = - MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_3 - assign m_vrg_source_prio_3$D_IN = - MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_4 - assign m_vrg_source_prio_4$D_IN = - MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_5 - assign m_vrg_source_prio_5$D_IN = - MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_6 - assign m_vrg_source_prio_6$D_IN = - MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_7 - assign m_vrg_source_prio_7$D_IN = - MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_8 - assign m_vrg_source_prio_8$D_IN = - MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_9 - assign m_vrg_source_prio_9$D_IN = - MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_0 - assign m_vrg_target_threshold_0$D_IN = - MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_1 - assign m_vrg_target_threshold_1$D_IN = - MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_0 - assign m_vvrg_ie_0_0$D_IN = - MUX_m_vvrg_ie_0_0$write_1__SEL_1 && - MUX_m_vvrg_ie_0_0$write_1__VAL_1 ; - assign m_vvrg_ie_0_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_1 - assign m_vvrg_ie_0_1$D_IN = - MUX_m_vvrg_ie_0_1$write_1__SEL_1 && - MUX_m_vvrg_ie_0_1$write_1__VAL_1 ; - assign m_vvrg_ie_0_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_10 - assign m_vvrg_ie_0_10$D_IN = - MUX_m_vvrg_ie_0_10$write_1__SEL_1 && - MUX_m_vvrg_ie_0_10$write_1__VAL_1 ; - assign m_vvrg_ie_0_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_11 - assign m_vvrg_ie_0_11$D_IN = - MUX_m_vvrg_ie_0_11$write_1__SEL_1 && - MUX_m_vvrg_ie_0_11$write_1__VAL_1 ; - assign m_vvrg_ie_0_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_12 - assign m_vvrg_ie_0_12$D_IN = - MUX_m_vvrg_ie_0_12$write_1__SEL_1 && - MUX_m_vvrg_ie_0_12$write_1__VAL_1 ; - assign m_vvrg_ie_0_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_13 - assign m_vvrg_ie_0_13$D_IN = - MUX_m_vvrg_ie_0_13$write_1__SEL_1 && - MUX_m_vvrg_ie_0_13$write_1__VAL_1 ; - assign m_vvrg_ie_0_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_14 - assign m_vvrg_ie_0_14$D_IN = - MUX_m_vvrg_ie_0_14$write_1__SEL_1 && - MUX_m_vvrg_ie_0_14$write_1__VAL_1 ; - assign m_vvrg_ie_0_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_15 - assign m_vvrg_ie_0_15$D_IN = - MUX_m_vvrg_ie_0_15$write_1__SEL_1 && - MUX_m_vvrg_ie_0_15$write_1__VAL_1 ; - assign m_vvrg_ie_0_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_16 - assign m_vvrg_ie_0_16$D_IN = - MUX_m_vvrg_ie_0_16$write_1__SEL_1 && - MUX_m_vvrg_ie_0_16$write_1__VAL_1 ; - assign m_vvrg_ie_0_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_2 - assign m_vvrg_ie_0_2$D_IN = - MUX_m_vvrg_ie_0_2$write_1__SEL_1 && - MUX_m_vvrg_ie_0_2$write_1__VAL_1 ; - assign m_vvrg_ie_0_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_3 - assign m_vvrg_ie_0_3$D_IN = - MUX_m_vvrg_ie_0_3$write_1__SEL_1 && - MUX_m_vvrg_ie_0_3$write_1__VAL_1 ; - assign m_vvrg_ie_0_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_4 - assign m_vvrg_ie_0_4$D_IN = - MUX_m_vvrg_ie_0_4$write_1__SEL_1 && - MUX_m_vvrg_ie_0_4$write_1__VAL_1 ; - assign m_vvrg_ie_0_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_5 - assign m_vvrg_ie_0_5$D_IN = - MUX_m_vvrg_ie_0_5$write_1__SEL_1 && - MUX_m_vvrg_ie_0_5$write_1__VAL_1 ; - assign m_vvrg_ie_0_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_6 - assign m_vvrg_ie_0_6$D_IN = - MUX_m_vvrg_ie_0_6$write_1__SEL_1 && - MUX_m_vvrg_ie_0_6$write_1__VAL_1 ; - assign m_vvrg_ie_0_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_7 - assign m_vvrg_ie_0_7$D_IN = - MUX_m_vvrg_ie_0_7$write_1__SEL_1 && - MUX_m_vvrg_ie_0_7$write_1__VAL_1 ; - assign m_vvrg_ie_0_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_8 - assign m_vvrg_ie_0_8$D_IN = - MUX_m_vvrg_ie_0_8$write_1__SEL_1 && - MUX_m_vvrg_ie_0_8$write_1__VAL_1 ; - assign m_vvrg_ie_0_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_9 - assign m_vvrg_ie_0_9$D_IN = - MUX_m_vvrg_ie_0_9$write_1__SEL_1 && - MUX_m_vvrg_ie_0_9$write_1__VAL_1 ; - assign m_vvrg_ie_0_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_0 - assign m_vvrg_ie_1_0$D_IN = - MUX_m_vvrg_ie_1_0$write_1__SEL_1 && - MUX_m_vvrg_ie_1_0$write_1__VAL_1 ; - assign m_vvrg_ie_1_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_1 - assign m_vvrg_ie_1_1$D_IN = - MUX_m_vvrg_ie_1_1$write_1__SEL_1 && - MUX_m_vvrg_ie_1_1$write_1__VAL_1 ; - assign m_vvrg_ie_1_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_10 - assign m_vvrg_ie_1_10$D_IN = - MUX_m_vvrg_ie_1_10$write_1__SEL_1 && - MUX_m_vvrg_ie_1_10$write_1__VAL_1 ; - assign m_vvrg_ie_1_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_11 - assign m_vvrg_ie_1_11$D_IN = - MUX_m_vvrg_ie_1_11$write_1__SEL_1 && - MUX_m_vvrg_ie_1_11$write_1__VAL_1 ; - assign m_vvrg_ie_1_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_12 - assign m_vvrg_ie_1_12$D_IN = - MUX_m_vvrg_ie_1_12$write_1__SEL_1 && - MUX_m_vvrg_ie_1_12$write_1__VAL_1 ; - assign m_vvrg_ie_1_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_13 - assign m_vvrg_ie_1_13$D_IN = - MUX_m_vvrg_ie_1_13$write_1__SEL_1 && - MUX_m_vvrg_ie_1_13$write_1__VAL_1 ; - assign m_vvrg_ie_1_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_14 - assign m_vvrg_ie_1_14$D_IN = - MUX_m_vvrg_ie_1_14$write_1__SEL_1 && - MUX_m_vvrg_ie_1_14$write_1__VAL_1 ; - assign m_vvrg_ie_1_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_15 - assign m_vvrg_ie_1_15$D_IN = - MUX_m_vvrg_ie_1_15$write_1__SEL_1 && - MUX_m_vvrg_ie_1_15$write_1__VAL_1 ; - assign m_vvrg_ie_1_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_16 - assign m_vvrg_ie_1_16$D_IN = - MUX_m_vvrg_ie_1_16$write_1__SEL_1 && - MUX_m_vvrg_ie_1_16$write_1__VAL_1 ; - assign m_vvrg_ie_1_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_2 - assign m_vvrg_ie_1_2$D_IN = - MUX_m_vvrg_ie_1_2$write_1__SEL_1 && - MUX_m_vvrg_ie_1_2$write_1__VAL_1 ; - assign m_vvrg_ie_1_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_3 - assign m_vvrg_ie_1_3$D_IN = - MUX_m_vvrg_ie_1_3$write_1__SEL_1 && - MUX_m_vvrg_ie_1_3$write_1__VAL_1 ; - assign m_vvrg_ie_1_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_4 - assign m_vvrg_ie_1_4$D_IN = - MUX_m_vvrg_ie_1_4$write_1__SEL_1 && - MUX_m_vvrg_ie_1_4$write_1__VAL_1 ; - assign m_vvrg_ie_1_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_5 - assign m_vvrg_ie_1_5$D_IN = - MUX_m_vvrg_ie_1_5$write_1__SEL_1 && - MUX_m_vvrg_ie_1_5$write_1__VAL_1 ; - assign m_vvrg_ie_1_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_6 - assign m_vvrg_ie_1_6$D_IN = - MUX_m_vvrg_ie_1_6$write_1__SEL_1 && - MUX_m_vvrg_ie_1_6$write_1__VAL_1 ; - assign m_vvrg_ie_1_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_7 - assign m_vvrg_ie_1_7$D_IN = - MUX_m_vvrg_ie_1_7$write_1__SEL_1 && - MUX_m_vvrg_ie_1_7$write_1__VAL_1 ; - assign m_vvrg_ie_1_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_8 - assign m_vvrg_ie_1_8$D_IN = - MUX_m_vvrg_ie_1_8$write_1__SEL_1 && - MUX_m_vvrg_ie_1_8$write_1__VAL_1 ; - assign m_vvrg_ie_1_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_9 - assign m_vvrg_ie_1_9$D_IN = - MUX_m_vvrg_ie_1_9$write_1__SEL_1 && - MUX_m_vvrg_ie_1_9$write_1__VAL_1 ; - assign m_vvrg_ie_1_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 || - WILL_FIRE_RL_m_rl_reset ; - - // submodule m_f_reset_reqs - assign m_f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign m_f_reset_reqs$DEQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_reqs$CLR = 1'b0 ; - - // submodule m_f_reset_rsps - assign m_f_reset_rsps$ENQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign m_f_reset_rsps$CLR = 1'b0 ; - - // submodule m_slave_xactor_f_rd_addr - assign m_slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign m_slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ; - assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_rd_data - assign m_slave_xactor_f_rd_data$D_IN = - { m_slave_xactor_f_rd_addr$D_OUT[96:93], - x__h26361, - rresp__h26203, - 1'd1 } ; - assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ; - assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_addr - assign m_slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign m_slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ; - assign m_slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_data - assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign m_slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; - assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_resp - assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26934 } ; - assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; - assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ; - - // remaining internal signals - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 : - ((x__h23673 == 32'h00200000) ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 : - x__h23673 != 32'h00200004 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 || - x__h24011 != 5'd0) ; - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - addr_offset__h13216[11:2] == 10'd0 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 : - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67110 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67110 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26929[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 = - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - 5'd2 : - (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ; - assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200000 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30685 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31895 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33105 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34315 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35525 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36735 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37945 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39155 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40365 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41575 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42785 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43995 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45205 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46415 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47625 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48835 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50045 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51255 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52465 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53675 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54885 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56095 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57305 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58515 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59725 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60935 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62145 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63355 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64565 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65775 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29475 <= 10'd16 ; - assign NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313 = - !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321 = - !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_11 != - v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329 = - !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_12 != - v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337 = - !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_13 != - v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345 = - !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_14 != - v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353 = - !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_15 != - v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361 = - !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_16 != - v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242 = - !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249 = - !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257 = - !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265 = - !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273 = - !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281 = - !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289 = - !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297 = - !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305 = - !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; - assign _dfoo1 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo10 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo100 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo32 ; - assign _dfoo1000 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo932 ; - assign _dfoo1001 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo865 ; - assign _dfoo1002 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo934 ; - assign _dfoo1003 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo867 ; - assign _dfoo1004 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo936 ; - assign _dfoo1005 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo869 ; - assign _dfoo1006 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo938 ; - assign _dfoo1007 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo871 ; - assign _dfoo1008 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo940 ; - assign _dfoo1009 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo873 ; - assign _dfoo1010 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo942 ; - assign _dfoo1011 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo875 ; - assign _dfoo1012 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo944 ; - assign _dfoo1013 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo877 ; - assign _dfoo1014 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo946 ; - assign _dfoo1015 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo879 ; - assign _dfoo1016 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo948 ; - assign _dfoo1017 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo881 ; - assign _dfoo1018 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo950 ; - assign _dfoo1019 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo883 ; - assign _dfoo102 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo34 ; - assign _dfoo1020 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo952 ; - assign _dfoo1022 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo954 ; - assign _dfoo1024 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo956 ; - assign _dfoo1026 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo958 ; - assign _dfoo1028 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo960 ; - assign _dfoo1030 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo962 ; - assign _dfoo1032 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo964 ; - assign _dfoo1034 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo966 ; - assign _dfoo1036 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo968 ; - assign _dfoo1038 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo970 ; - assign _dfoo104 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo36 ; - assign _dfoo1040 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo972 ; - assign _dfoo1042 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo974 ; - assign _dfoo1044 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo976 ; - assign _dfoo1046 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo978 ; - assign _dfoo1048 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo980 ; - assign _dfoo1050 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo982 ; - assign _dfoo1052 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo984 ; - assign _dfoo1054 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo986 ; - assign _dfoo1056 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo988 ; - assign _dfoo1058 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo990 ; - assign _dfoo106 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo38 ; - assign _dfoo1060 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo992 ; - assign _dfoo1062 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo994 ; - assign _dfoo1064 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo996 ; - assign _dfoo1066 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo998 ; - assign _dfoo1068 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1000 ; - assign _dfoo1070 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1002 ; - assign _dfoo1072 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1004 ; - assign _dfoo1074 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1006 ; - assign _dfoo1076 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1008 ; - assign _dfoo1078 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1010 ; - assign _dfoo108 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo40 ; - assign _dfoo1080 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1012 ; - assign _dfoo1082 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1014 ; - assign _dfoo1084 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1016 ; - assign _dfoo1086 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1018 ; - assign _dfoo1088 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1020 ; - assign _dfoo1089 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo953 ; - assign _dfoo1090 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1022 ; - assign _dfoo1091 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo955 ; - assign _dfoo1092 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1024 ; - assign _dfoo1093 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo957 ; - assign _dfoo1094 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1026 ; - assign _dfoo1095 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo959 ; - assign _dfoo1096 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1028 ; - assign _dfoo1097 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo961 ; - assign _dfoo1098 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1030 ; - assign _dfoo1099 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo963 ; - assign _dfoo11 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo110 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo42 ; - assign _dfoo1100 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1032 ; - assign _dfoo1101 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo965 ; - assign _dfoo1102 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1034 ; - assign _dfoo1103 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo967 ; - assign _dfoo1104 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1036 ; - assign _dfoo1105 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo969 ; - assign _dfoo1106 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1038 ; - assign _dfoo1107 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo971 ; - assign _dfoo1108 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1040 ; - assign _dfoo1109 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo973 ; - assign _dfoo1110 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1042 ; - assign _dfoo1111 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo975 ; - assign _dfoo1112 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1044 ; - assign _dfoo1113 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo977 ; - assign _dfoo1114 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1046 ; - assign _dfoo1115 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo979 ; - assign _dfoo1116 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1048 ; - assign _dfoo1117 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo981 ; - assign _dfoo1118 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1050 ; - assign _dfoo1119 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo983 ; - assign _dfoo112 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo44 ; - assign _dfoo1120 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1052 ; - assign _dfoo1121 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo985 ; - assign _dfoo1122 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1054 ; - assign _dfoo1123 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo987 ; - assign _dfoo1124 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1056 ; - assign _dfoo1125 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo989 ; - assign _dfoo1126 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1058 ; - assign _dfoo1127 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo991 ; - assign _dfoo1128 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1060 ; - assign _dfoo1129 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo993 ; - assign _dfoo1130 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1062 ; - assign _dfoo1131 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo995 ; - assign _dfoo1132 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1064 ; - assign _dfoo1133 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo997 ; - assign _dfoo1134 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1066 ; - assign _dfoo1135 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo999 ; - assign _dfoo1136 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1068 ; - assign _dfoo1137 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1001 ; - assign _dfoo1138 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1070 ; - assign _dfoo1139 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1003 ; - assign _dfoo114 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo46 ; - assign _dfoo1140 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1072 ; - assign _dfoo1141 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1005 ; - assign _dfoo1142 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1074 ; - assign _dfoo1143 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1007 ; - assign _dfoo1144 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1076 ; - assign _dfoo1145 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1009 ; - assign _dfoo1146 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1078 ; - assign _dfoo1147 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1011 ; - assign _dfoo1148 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1080 ; - assign _dfoo1149 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1013 ; - assign _dfoo1150 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1082 ; - assign _dfoo1151 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1015 ; - assign _dfoo1152 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1084 ; - assign _dfoo1153 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1017 ; - assign _dfoo1154 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1086 ; - assign _dfoo1155 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1019 ; - assign _dfoo1156 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1088 ; - assign _dfoo1158 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1090 ; - assign _dfoo116 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo48 ; - assign _dfoo1160 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1092 ; - assign _dfoo1162 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1094 ; - assign _dfoo1164 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1096 ; - assign _dfoo1166 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1098 ; - assign _dfoo1168 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1100 ; - assign _dfoo1170 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1102 ; - assign _dfoo1172 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1104 ; - assign _dfoo1174 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1106 ; - assign _dfoo1176 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1108 ; - assign _dfoo1178 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1110 ; - assign _dfoo118 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo50 ; - assign _dfoo1180 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1112 ; - assign _dfoo1182 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1114 ; - assign _dfoo1184 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1116 ; - assign _dfoo1186 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1118 ; - assign _dfoo1188 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1120 ; - assign _dfoo1190 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1122 ; - assign _dfoo1192 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1124 ; - assign _dfoo1194 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1126 ; - assign _dfoo1196 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1128 ; - assign _dfoo1198 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1130 ; - assign _dfoo12 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo120 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo52 ; - assign _dfoo1200 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1132 ; - assign _dfoo1202 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1134 ; - assign _dfoo1204 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1136 ; - assign _dfoo1206 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1138 ; - assign _dfoo1208 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1140 ; - assign _dfoo1210 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1142 ; - assign _dfoo1212 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1144 ; - assign _dfoo1214 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1146 ; - assign _dfoo1216 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1148 ; - assign _dfoo1218 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1150 ; - assign _dfoo122 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo54 ; - assign _dfoo1220 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1152 ; - assign _dfoo1222 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1154 ; - assign _dfoo1224 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1156 ; - assign _dfoo1225 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1089 ; - assign _dfoo1226 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1158 ; - assign _dfoo1227 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1091 ; - assign _dfoo1228 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1160 ; - assign _dfoo1229 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1093 ; - assign _dfoo1230 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1162 ; - assign _dfoo1231 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1095 ; - assign _dfoo1232 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1164 ; - assign _dfoo1233 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1097 ; - assign _dfoo1234 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1166 ; - assign _dfoo1235 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1099 ; - assign _dfoo1236 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1168 ; - assign _dfoo1237 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1101 ; - assign _dfoo1238 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1170 ; - assign _dfoo1239 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1103 ; - assign _dfoo124 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo56 ; - assign _dfoo1240 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1172 ; - assign _dfoo1241 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1105 ; - assign _dfoo1242 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1174 ; - assign _dfoo1243 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1107 ; - assign _dfoo1244 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1176 ; - assign _dfoo1245 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1109 ; - assign _dfoo1246 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1178 ; - assign _dfoo1247 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1111 ; - assign _dfoo1248 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1180 ; - assign _dfoo1249 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1113 ; - assign _dfoo1250 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1182 ; - assign _dfoo1251 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1115 ; - assign _dfoo1252 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1184 ; - assign _dfoo1253 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1117 ; - assign _dfoo1254 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1186 ; - assign _dfoo1255 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1119 ; - assign _dfoo1256 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1188 ; - assign _dfoo1257 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1121 ; - assign _dfoo1258 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1190 ; - assign _dfoo1259 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1123 ; - assign _dfoo126 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo58 ; - assign _dfoo1260 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1192 ; - assign _dfoo1261 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1125 ; - assign _dfoo1262 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1194 ; - assign _dfoo1263 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1127 ; - assign _dfoo1264 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1196 ; - assign _dfoo1265 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1129 ; - assign _dfoo1266 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1198 ; - assign _dfoo1267 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1131 ; - assign _dfoo1268 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1200 ; - assign _dfoo1269 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1133 ; - assign _dfoo1270 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1202 ; - assign _dfoo1271 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1135 ; - assign _dfoo1272 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1204 ; - assign _dfoo1273 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1137 ; - assign _dfoo1274 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1206 ; - assign _dfoo1275 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1139 ; - assign _dfoo1276 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1208 ; - assign _dfoo1277 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1141 ; - assign _dfoo1278 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1210 ; - assign _dfoo1279 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1143 ; - assign _dfoo128 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo60 ; - assign _dfoo1280 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1212 ; - assign _dfoo1281 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1145 ; - assign _dfoo1282 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1214 ; - assign _dfoo1283 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1147 ; - assign _dfoo1284 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1216 ; - assign _dfoo1285 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1149 ; - assign _dfoo1286 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1218 ; - assign _dfoo1287 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1151 ; - assign _dfoo1288 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1220 ; - assign _dfoo1289 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1153 ; - assign _dfoo1290 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1222 ; - assign _dfoo1291 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1155 ; - assign _dfoo1292 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1224 ; - assign _dfoo1294 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1226 ; - assign _dfoo1296 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1228 ; - assign _dfoo1298 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1230 ; - assign _dfoo13 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo130 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo62 ; - assign _dfoo1300 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1232 ; - assign _dfoo1302 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1234 ; - assign _dfoo1304 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1236 ; - assign _dfoo1306 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1238 ; - assign _dfoo1308 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1240 ; - assign _dfoo1310 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1242 ; - assign _dfoo1312 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1244 ; - assign _dfoo1314 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1246 ; - assign _dfoo1316 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1248 ; - assign _dfoo1318 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1250 ; - assign _dfoo132 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo64 ; - assign _dfoo1320 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1252 ; - assign _dfoo1322 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1254 ; - assign _dfoo1324 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1256 ; - assign _dfoo1326 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1258 ; - assign _dfoo1328 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1260 ; - assign _dfoo1330 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1262 ; - assign _dfoo1332 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1264 ; - assign _dfoo1334 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1266 ; - assign _dfoo1336 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1268 ; - assign _dfoo1338 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1270 ; - assign _dfoo134 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo66 ; - assign _dfoo1340 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1272 ; - assign _dfoo1342 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1274 ; - assign _dfoo1344 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1276 ; - assign _dfoo1346 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1278 ; - assign _dfoo1348 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1280 ; - assign _dfoo1350 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1282 ; - assign _dfoo1352 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1284 ; - assign _dfoo1354 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1286 ; - assign _dfoo1356 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1288 ; - assign _dfoo1358 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1290 ; - assign _dfoo136 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo68 ; - assign _dfoo1360 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1292 ; - assign _dfoo1361 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1225 ; - assign _dfoo1362 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1294 ; - assign _dfoo1363 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1227 ; - assign _dfoo1364 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1296 ; - assign _dfoo1365 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1229 ; - assign _dfoo1366 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1298 ; - assign _dfoo1367 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1231 ; - assign _dfoo1368 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1300 ; - assign _dfoo1369 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1233 ; - assign _dfoo137 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo1 ; - assign _dfoo1370 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1302 ; - assign _dfoo1371 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1235 ; - assign _dfoo1372 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1304 ; - assign _dfoo1373 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1237 ; - assign _dfoo1374 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1306 ; - assign _dfoo1375 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1239 ; - assign _dfoo1376 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1308 ; - assign _dfoo1377 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1241 ; - assign _dfoo1378 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1310 ; - assign _dfoo1379 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1243 ; - assign _dfoo138 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo70 ; - assign _dfoo1380 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1312 ; - assign _dfoo1381 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1245 ; - assign _dfoo1382 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1314 ; - assign _dfoo1383 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1247 ; - assign _dfoo1384 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1316 ; - assign _dfoo1385 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1249 ; - assign _dfoo1386 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1318 ; - assign _dfoo1387 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1251 ; - assign _dfoo1388 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1320 ; - assign _dfoo1389 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1253 ; - assign _dfoo139 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo3 ; - assign _dfoo1390 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1322 ; - assign _dfoo1391 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1255 ; - assign _dfoo1392 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1324 ; - assign _dfoo1393 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1257 ; - assign _dfoo1394 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1326 ; - assign _dfoo1395 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1259 ; - assign _dfoo1396 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1328 ; - assign _dfoo1397 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1261 ; - assign _dfoo1398 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1330 ; - assign _dfoo1399 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1263 ; - assign _dfoo14 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo140 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo72 ; - assign _dfoo1400 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1332 ; - assign _dfoo1401 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1265 ; - assign _dfoo1402 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1334 ; - assign _dfoo1403 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1267 ; - assign _dfoo1404 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1336 ; - assign _dfoo1405 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1269 ; - assign _dfoo1406 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1338 ; - assign _dfoo1407 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1271 ; - assign _dfoo1408 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1340 ; - assign _dfoo1409 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1273 ; - assign _dfoo141 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo5 ; - assign _dfoo1410 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1342 ; - assign _dfoo1411 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1275 ; - assign _dfoo1412 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1344 ; - assign _dfoo1413 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1277 ; - assign _dfoo1414 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1346 ; - assign _dfoo1415 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1279 ; - assign _dfoo1416 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1348 ; - assign _dfoo1417 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1281 ; - assign _dfoo1418 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1350 ; - assign _dfoo1419 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1283 ; - assign _dfoo142 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo74 ; - assign _dfoo1420 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1352 ; - assign _dfoo1421 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1285 ; - assign _dfoo1422 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1354 ; - assign _dfoo1423 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1287 ; - assign _dfoo1424 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1356 ; - assign _dfoo1425 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1289 ; - assign _dfoo1426 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1358 ; - assign _dfoo1427 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1291 ; - assign _dfoo1428 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1360 ; - assign _dfoo143 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo7 ; - assign _dfoo1430 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1362 ; - assign _dfoo1432 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1364 ; - assign _dfoo1434 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1366 ; - assign _dfoo1436 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1368 ; - assign _dfoo1438 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1370 ; - assign _dfoo144 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo76 ; - assign _dfoo1440 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1372 ; - assign _dfoo1442 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1374 ; - assign _dfoo1444 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1376 ; - assign _dfoo1446 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1378 ; - assign _dfoo1448 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1380 ; - assign _dfoo145 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo9 ; - assign _dfoo1450 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1382 ; - assign _dfoo1452 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1384 ; - assign _dfoo1454 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1386 ; - assign _dfoo1456 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1388 ; - assign _dfoo1458 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1390 ; - assign _dfoo146 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo78 ; - assign _dfoo1460 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1392 ; - assign _dfoo1462 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1394 ; - assign _dfoo1464 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1396 ; - assign _dfoo1466 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1398 ; - assign _dfoo1468 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1400 ; - assign _dfoo147 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo11 ; - assign _dfoo1470 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1402 ; - assign _dfoo1472 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1404 ; - assign _dfoo1474 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1406 ; - assign _dfoo1476 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1408 ; - assign _dfoo1478 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1410 ; - assign _dfoo148 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo80 ; - assign _dfoo1480 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1412 ; - assign _dfoo1482 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1414 ; - assign _dfoo1484 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1416 ; - assign _dfoo1486 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1418 ; - assign _dfoo1488 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1420 ; - assign _dfoo149 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo13 ; - assign _dfoo1490 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1422 ; - assign _dfoo1492 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1424 ; - assign _dfoo1494 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1426 ; - assign _dfoo1496 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1428 ; - assign _dfoo1497 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1361 ; - assign _dfoo1498 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1430 ; - assign _dfoo1499 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1363 ; - assign _dfoo15 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo150 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo82 ; - assign _dfoo1500 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1432 ; - assign _dfoo1501 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1365 ; - assign _dfoo1502 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1434 ; - assign _dfoo1503 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1367 ; - assign _dfoo1504 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1436 ; - assign _dfoo1505 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1369 ; - assign _dfoo1506 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1438 ; - assign _dfoo1507 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1371 ; - assign _dfoo1508 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1440 ; - assign _dfoo1509 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1373 ; - assign _dfoo151 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo15 ; - assign _dfoo1510 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1442 ; - assign _dfoo1511 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1375 ; - assign _dfoo1512 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1444 ; - assign _dfoo1513 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1377 ; - assign _dfoo1514 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1446 ; - assign _dfoo1515 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1379 ; - assign _dfoo1516 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1448 ; - assign _dfoo1517 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1381 ; - assign _dfoo1518 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1450 ; - assign _dfoo1519 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1383 ; - assign _dfoo152 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo84 ; - assign _dfoo1520 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1452 ; - assign _dfoo1521 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1385 ; - assign _dfoo1522 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1454 ; - assign _dfoo1523 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1387 ; - assign _dfoo1524 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1456 ; - assign _dfoo1525 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1389 ; - assign _dfoo1526 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1458 ; - assign _dfoo1527 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1391 ; - assign _dfoo1528 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1460 ; - assign _dfoo1529 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1393 ; - assign _dfoo153 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo17 ; - assign _dfoo1530 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1462 ; - assign _dfoo1531 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1395 ; - assign _dfoo1532 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1464 ; - assign _dfoo1533 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1397 ; - assign _dfoo1534 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1466 ; - assign _dfoo1535 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1399 ; - assign _dfoo1536 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1468 ; - assign _dfoo1537 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1401 ; - assign _dfoo1538 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1470 ; - assign _dfoo1539 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1403 ; - assign _dfoo154 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo86 ; - assign _dfoo1540 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1472 ; - assign _dfoo1541 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1405 ; - assign _dfoo1542 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1474 ; - assign _dfoo1543 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1407 ; - assign _dfoo1544 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1476 ; - assign _dfoo1545 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1409 ; - assign _dfoo1546 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1478 ; - assign _dfoo1547 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1411 ; - assign _dfoo1548 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1480 ; - assign _dfoo1549 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1413 ; - assign _dfoo155 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo19 ; - assign _dfoo1550 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1482 ; - assign _dfoo1551 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1415 ; - assign _dfoo1552 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1484 ; - assign _dfoo1553 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1417 ; - assign _dfoo1554 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1486 ; - assign _dfoo1555 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1419 ; - assign _dfoo1556 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1488 ; - assign _dfoo1557 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1421 ; - assign _dfoo1558 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1490 ; - assign _dfoo1559 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1423 ; - assign _dfoo156 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo88 ; - assign _dfoo1560 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1492 ; - assign _dfoo1561 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1425 ; - assign _dfoo1562 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1494 ; - assign _dfoo1563 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1427 ; - assign _dfoo1564 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1496 ; - assign _dfoo1566 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1498 ; - assign _dfoo1568 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1500 ; - assign _dfoo157 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo21 ; - assign _dfoo1570 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1502 ; - assign _dfoo1572 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1504 ; - assign _dfoo1574 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1506 ; - assign _dfoo1576 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1508 ; - assign _dfoo1578 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1510 ; - assign _dfoo158 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo90 ; - assign _dfoo1580 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1512 ; - assign _dfoo1582 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1514 ; - assign _dfoo1584 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1516 ; - assign _dfoo1586 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1518 ; - assign _dfoo1588 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1520 ; - assign _dfoo159 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo23 ; - assign _dfoo1590 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1522 ; - assign _dfoo1592 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1524 ; - assign _dfoo1594 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1526 ; - assign _dfoo1596 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1528 ; - assign _dfoo1598 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1530 ; - assign _dfoo16 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo160 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo92 ; - assign _dfoo1600 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1532 ; - assign _dfoo1602 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1534 ; - assign _dfoo1604 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1536 ; - assign _dfoo1606 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1538 ; - assign _dfoo1608 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1540 ; - assign _dfoo161 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo25 ; - assign _dfoo1610 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1542 ; - assign _dfoo1612 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1544 ; - assign _dfoo1614 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1546 ; - assign _dfoo1616 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1548 ; - assign _dfoo1618 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1550 ; - assign _dfoo162 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo94 ; - assign _dfoo1620 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1552 ; - assign _dfoo1622 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1554 ; - assign _dfoo1624 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1556 ; - assign _dfoo1626 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1558 ; - assign _dfoo1628 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1560 ; - assign _dfoo163 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo27 ; - assign _dfoo1630 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1562 ; - assign _dfoo1632 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1564 ; - assign _dfoo1633 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1497 ; - assign _dfoo1634 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1566 ; - assign _dfoo1635 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1499 ; - assign _dfoo1636 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1568 ; - assign _dfoo1637 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1501 ; - assign _dfoo1638 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1570 ; - assign _dfoo1639 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1503 ; - assign _dfoo164 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo96 ; - assign _dfoo1640 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1572 ; - assign _dfoo1641 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1505 ; - assign _dfoo1642 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1574 ; - assign _dfoo1643 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1507 ; - assign _dfoo1644 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1576 ; - assign _dfoo1645 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1509 ; - assign _dfoo1646 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1578 ; - assign _dfoo1647 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1511 ; - assign _dfoo1648 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1580 ; - assign _dfoo1649 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1513 ; - assign _dfoo165 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo29 ; - assign _dfoo1650 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1582 ; - assign _dfoo1651 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1515 ; - assign _dfoo1652 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1584 ; - assign _dfoo1653 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1517 ; - assign _dfoo1654 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1586 ; - assign _dfoo1655 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1519 ; - assign _dfoo1656 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1588 ; - assign _dfoo1657 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1521 ; - assign _dfoo1658 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1590 ; - assign _dfoo1659 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1523 ; - assign _dfoo166 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo98 ; - assign _dfoo1660 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1592 ; - assign _dfoo1661 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1525 ; - assign _dfoo1662 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1594 ; - assign _dfoo1663 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1527 ; - assign _dfoo1664 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1596 ; - assign _dfoo1665 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1529 ; - assign _dfoo1666 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1598 ; - assign _dfoo1667 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1531 ; - assign _dfoo1668 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1600 ; - assign _dfoo1669 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1533 ; - assign _dfoo167 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo31 ; - assign _dfoo1670 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1602 ; - assign _dfoo1671 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1535 ; - assign _dfoo1672 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1604 ; - assign _dfoo1673 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1537 ; - assign _dfoo1674 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1606 ; - assign _dfoo1675 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1539 ; - assign _dfoo1676 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1608 ; - assign _dfoo1677 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1541 ; - assign _dfoo1678 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1610 ; - assign _dfoo1679 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1543 ; - assign _dfoo168 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo100 ; - assign _dfoo1680 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1612 ; - assign _dfoo1681 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1545 ; - assign _dfoo1682 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1614 ; - assign _dfoo1683 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1547 ; - assign _dfoo1684 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1616 ; - assign _dfoo1685 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1549 ; - assign _dfoo1686 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1618 ; - assign _dfoo1687 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1551 ; - assign _dfoo1688 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1620 ; - assign _dfoo1689 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1553 ; - assign _dfoo169 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo33 ; - assign _dfoo1690 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1622 ; - assign _dfoo1691 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1555 ; - assign _dfoo1692 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1624 ; - assign _dfoo1693 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1557 ; - assign _dfoo1694 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1626 ; - assign _dfoo1695 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1559 ; - assign _dfoo1696 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1628 ; - assign _dfoo1697 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1561 ; - assign _dfoo1698 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1630 ; - assign _dfoo1699 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1563 ; - assign _dfoo17 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo170 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo102 ; - assign _dfoo1700 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1632 ; - assign _dfoo1702 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1634 ; - assign _dfoo1704 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1636 ; - assign _dfoo1706 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1638 ; - assign _dfoo1708 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1640 ; - assign _dfoo171 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo35 ; - assign _dfoo1710 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1642 ; - assign _dfoo1712 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1644 ; - assign _dfoo1714 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1646 ; - assign _dfoo1716 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1648 ; - assign _dfoo1718 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1650 ; - assign _dfoo172 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo104 ; - assign _dfoo1720 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1652 ; - assign _dfoo1722 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1654 ; - assign _dfoo1724 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1656 ; - assign _dfoo1726 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1658 ; - assign _dfoo1728 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1660 ; - assign _dfoo173 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo37 ; - assign _dfoo1730 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1662 ; - assign _dfoo1732 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1664 ; - assign _dfoo1734 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1666 ; - assign _dfoo1736 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1668 ; - assign _dfoo1738 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1670 ; - assign _dfoo174 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo106 ; - assign _dfoo1740 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1672 ; - assign _dfoo1742 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1674 ; - assign _dfoo1744 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1676 ; - assign _dfoo1746 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1678 ; - assign _dfoo1748 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1680 ; - assign _dfoo175 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo39 ; - assign _dfoo1750 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1682 ; - assign _dfoo1752 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1684 ; - assign _dfoo1754 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1686 ; - assign _dfoo1756 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1688 ; - assign _dfoo1758 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1690 ; - assign _dfoo176 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo108 ; - assign _dfoo1760 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1692 ; - assign _dfoo1762 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1694 ; - assign _dfoo1764 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1696 ; - assign _dfoo1766 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1698 ; - assign _dfoo1768 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1700 ; - assign _dfoo1769 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1633 ; - assign _dfoo177 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo41 ; - assign _dfoo1770 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1702 ; - assign _dfoo1771 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1635 ; - assign _dfoo1772 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1704 ; - assign _dfoo1773 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1637 ; - assign _dfoo1774 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1706 ; - assign _dfoo1775 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1639 ; - assign _dfoo1776 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1708 ; - assign _dfoo1777 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1641 ; - assign _dfoo1778 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1710 ; - assign _dfoo1779 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1643 ; - assign _dfoo178 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo110 ; - assign _dfoo1780 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1712 ; - assign _dfoo1781 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1645 ; - assign _dfoo1782 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1714 ; - assign _dfoo1783 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1647 ; - assign _dfoo1784 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1716 ; - assign _dfoo1785 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1649 ; - assign _dfoo1786 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1718 ; - assign _dfoo1787 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1651 ; - assign _dfoo1788 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1720 ; - assign _dfoo1789 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1653 ; - assign _dfoo179 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo43 ; - assign _dfoo1790 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1722 ; - assign _dfoo1791 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1655 ; - assign _dfoo1792 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1724 ; - assign _dfoo1793 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1657 ; - assign _dfoo1794 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1726 ; - assign _dfoo1795 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1659 ; - assign _dfoo1796 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1728 ; - assign _dfoo1797 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1661 ; - assign _dfoo1798 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1730 ; - assign _dfoo1799 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1663 ; - assign _dfoo18 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo180 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo112 ; - assign _dfoo1800 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1732 ; - assign _dfoo1801 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1665 ; - assign _dfoo1802 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1734 ; - assign _dfoo1803 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1667 ; - assign _dfoo1804 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1736 ; - assign _dfoo1805 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1669 ; - assign _dfoo1806 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1738 ; - assign _dfoo1807 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1671 ; - assign _dfoo1808 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1740 ; - assign _dfoo1809 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1673 ; - assign _dfoo181 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo45 ; - assign _dfoo1810 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1742 ; - assign _dfoo1811 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1675 ; - assign _dfoo1812 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1744 ; - assign _dfoo1813 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1677 ; - assign _dfoo1814 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1746 ; - assign _dfoo1815 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1679 ; - assign _dfoo1816 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1748 ; - assign _dfoo1817 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1681 ; - assign _dfoo1818 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1750 ; - assign _dfoo1819 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1683 ; - assign _dfoo182 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo114 ; - assign _dfoo1820 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1752 ; - assign _dfoo1821 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1685 ; - assign _dfoo1822 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1754 ; - assign _dfoo1823 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1687 ; - assign _dfoo1824 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1756 ; - assign _dfoo1825 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1689 ; - assign _dfoo1826 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1758 ; - assign _dfoo1827 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1691 ; - assign _dfoo1828 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1760 ; - assign _dfoo1829 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1693 ; - assign _dfoo183 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo47 ; - assign _dfoo1830 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1762 ; - assign _dfoo1831 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1695 ; - assign _dfoo1832 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1764 ; - assign _dfoo1833 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1697 ; - assign _dfoo1834 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1766 ; - assign _dfoo1835 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1699 ; - assign _dfoo1836 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1768 ; - assign _dfoo1838 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1770 ; - assign _dfoo184 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo116 ; - assign _dfoo1840 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1772 ; - assign _dfoo1842 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1774 ; - assign _dfoo1844 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1776 ; - assign _dfoo1846 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1778 ; - assign _dfoo1848 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1780 ; - assign _dfoo185 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo49 ; - assign _dfoo1850 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1782 ; - assign _dfoo1852 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1784 ; - assign _dfoo1854 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1786 ; - assign _dfoo1856 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1788 ; - assign _dfoo1858 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1790 ; - assign _dfoo186 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo118 ; - assign _dfoo1860 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1792 ; - assign _dfoo1862 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1794 ; - assign _dfoo1864 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1796 ; - assign _dfoo1866 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1798 ; - assign _dfoo1868 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1800 ; - assign _dfoo187 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo51 ; - assign _dfoo1870 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1802 ; - assign _dfoo1872 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1804 ; - assign _dfoo1874 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1806 ; - assign _dfoo1876 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1808 ; - assign _dfoo1878 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1810 ; - assign _dfoo188 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo120 ; - assign _dfoo1880 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1812 ; - assign _dfoo1882 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1814 ; - assign _dfoo1884 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1816 ; - assign _dfoo1886 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1818 ; - assign _dfoo1888 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1820 ; - assign _dfoo189 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo53 ; - assign _dfoo1890 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1822 ; - assign _dfoo1892 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1824 ; - assign _dfoo1894 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1826 ; - assign _dfoo1896 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1828 ; - assign _dfoo1898 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1830 ; - assign _dfoo19 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo190 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo122 ; - assign _dfoo1900 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1832 ; - assign _dfoo1902 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1834 ; - assign _dfoo1904 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1836 ; - assign _dfoo1905 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1769 ; - assign _dfoo1906 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1838 ; - assign _dfoo1907 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1771 ; - assign _dfoo1908 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1840 ; - assign _dfoo1909 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1773 ; - assign _dfoo191 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo55 ; - assign _dfoo1910 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1842 ; - assign _dfoo1911 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1775 ; - assign _dfoo1912 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1844 ; - assign _dfoo1913 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1777 ; - assign _dfoo1914 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1846 ; - assign _dfoo1915 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1779 ; - assign _dfoo1916 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1848 ; - assign _dfoo1917 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1781 ; - assign _dfoo1918 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1850 ; - assign _dfoo1919 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1783 ; - assign _dfoo192 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo124 ; - assign _dfoo1920 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1852 ; - assign _dfoo1921 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1785 ; - assign _dfoo1922 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1854 ; - assign _dfoo1923 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1787 ; - assign _dfoo1924 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1856 ; - assign _dfoo1925 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1789 ; - assign _dfoo1926 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1858 ; - assign _dfoo1927 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1791 ; - assign _dfoo1928 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1860 ; - assign _dfoo1929 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1793 ; - assign _dfoo193 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo57 ; - assign _dfoo1930 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1862 ; - assign _dfoo1931 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1795 ; - assign _dfoo1932 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1864 ; - assign _dfoo1933 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1797 ; - assign _dfoo1934 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1866 ; - assign _dfoo1935 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1799 ; - assign _dfoo1936 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1868 ; - assign _dfoo1937 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1801 ; - assign _dfoo1938 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1870 ; - assign _dfoo1939 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1803 ; - assign _dfoo194 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo126 ; - assign _dfoo1940 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1872 ; - assign _dfoo1941 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1805 ; - assign _dfoo1942 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1874 ; - assign _dfoo1943 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1807 ; - assign _dfoo1944 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1876 ; - assign _dfoo1945 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1809 ; - assign _dfoo1946 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1878 ; - assign _dfoo1947 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1811 ; - assign _dfoo1948 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1880 ; - assign _dfoo1949 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1813 ; - assign _dfoo195 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo59 ; - assign _dfoo1950 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1882 ; - assign _dfoo1951 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1815 ; - assign _dfoo1952 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1884 ; - assign _dfoo1953 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1817 ; - assign _dfoo1954 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1886 ; - assign _dfoo1955 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1819 ; - assign _dfoo1956 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1888 ; - assign _dfoo1957 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1821 ; - assign _dfoo1958 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1890 ; - assign _dfoo1959 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1823 ; - assign _dfoo196 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo128 ; - assign _dfoo1960 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1892 ; - assign _dfoo1961 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1825 ; - assign _dfoo1962 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1894 ; - assign _dfoo1963 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1827 ; - assign _dfoo1964 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1896 ; - assign _dfoo1965 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1829 ; - assign _dfoo1966 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1898 ; - assign _dfoo1967 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1831 ; - assign _dfoo1968 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1900 ; - assign _dfoo1969 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1833 ; - assign _dfoo197 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo61 ; - assign _dfoo1970 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1902 ; - assign _dfoo1971 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1835 ; - assign _dfoo1972 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1904 ; - assign _dfoo1974 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1906 ; - assign _dfoo1976 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1908 ; - assign _dfoo1978 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1910 ; - assign _dfoo198 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo130 ; - assign _dfoo1980 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1912 ; - assign _dfoo1982 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1914 ; - assign _dfoo1984 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1916 ; - assign _dfoo1986 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1918 ; - assign _dfoo1988 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1920 ; - assign _dfoo199 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo63 ; - assign _dfoo1990 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1922 ; - assign _dfoo1992 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1924 ; - assign _dfoo1994 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1926 ; - assign _dfoo1996 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1928 ; - assign _dfoo1998 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1930 ; - assign _dfoo2 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo20 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo200 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo132 ; - assign _dfoo2000 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1932 ; - assign _dfoo2002 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1934 ; - assign _dfoo2004 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1936 ; - assign _dfoo2006 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1938 ; - assign _dfoo2008 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1940 ; - assign _dfoo201 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo65 ; - assign _dfoo2010 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1942 ; - assign _dfoo2012 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1944 ; - assign _dfoo2014 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1946 ; - assign _dfoo2016 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1948 ; - assign _dfoo2018 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1950 ; - assign _dfoo202 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo134 ; - assign _dfoo2020 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1952 ; - assign _dfoo2022 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1954 ; - assign _dfoo2024 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1956 ; - assign _dfoo2026 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1958 ; - assign _dfoo2028 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1960 ; - assign _dfoo203 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo67 ; - assign _dfoo2030 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1962 ; - assign _dfoo2032 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1964 ; - assign _dfoo2034 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1966 ; - assign _dfoo2036 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1968 ; - assign _dfoo2038 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1970 ; - assign _dfoo204 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo136 ; - assign _dfoo2040 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1972 ; - assign _dfoo2041 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1905 ; - assign _dfoo2043 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1907 ; - assign _dfoo2045 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1909 ; - assign _dfoo2047 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1911 ; - assign _dfoo2049 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1913 ; - assign _dfoo2051 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1915 ; - assign _dfoo2053 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1917 ; - assign _dfoo2055 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1919 ; - assign _dfoo2057 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1921 ; - assign _dfoo2059 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1923 ; - assign _dfoo206 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo138 ; - assign _dfoo2061 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1925 ; - assign _dfoo2063 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1927 ; - assign _dfoo2065 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1929 ; - assign _dfoo2067 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1931 ; - assign _dfoo2069 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1933 ; - assign _dfoo2071 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1935 ; - assign _dfoo2073 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1937 ; - assign _dfoo2075 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1939 ; - assign _dfoo2077 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1941 ; - assign _dfoo2079 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1943 ; - assign _dfoo208 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo140 ; - assign _dfoo2081 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1945 ; - assign _dfoo2083 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1947 ; - assign _dfoo2085 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1949 ; - assign _dfoo2087 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1951 ; - assign _dfoo2089 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1953 ; - assign _dfoo2091 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1955 ; - assign _dfoo2093 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1957 ; - assign _dfoo2095 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1959 ; - assign _dfoo2097 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1961 ; - assign _dfoo2099 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1963 ; - assign _dfoo21 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo210 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo142 ; - assign _dfoo2101 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1965 ; - assign _dfoo2103 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1967 ; - assign _dfoo2105 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1969 ; - assign _dfoo2107 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1971 ; - assign _dfoo212 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo144 ; - assign _dfoo214 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo146 ; - assign _dfoo216 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo148 ; - assign _dfoo218 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo150 ; - assign _dfoo22 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo220 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo152 ; - assign _dfoo222 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo154 ; - assign _dfoo224 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo156 ; - assign _dfoo226 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo158 ; - assign _dfoo228 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo160 ; - assign _dfoo23 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo230 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo162 ; - assign _dfoo232 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo164 ; - assign _dfoo234 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo166 ; - assign _dfoo236 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo168 ; - assign _dfoo238 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo170 ; - assign _dfoo24 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo240 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo172 ; - assign _dfoo242 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo174 ; - assign _dfoo244 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo176 ; - assign _dfoo246 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo178 ; - assign _dfoo248 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo180 ; - assign _dfoo25 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo250 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo182 ; - assign _dfoo252 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo184 ; - assign _dfoo254 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo186 ; - assign _dfoo256 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo188 ; - assign _dfoo258 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo190 ; - assign _dfoo26 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo260 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo192 ; - assign _dfoo262 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo194 ; - assign _dfoo264 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo196 ; - assign _dfoo266 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo198 ; - assign _dfoo268 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo200 ; - assign _dfoo27 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo270 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo202 ; - assign _dfoo272 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo204 ; - assign _dfoo273 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo137 ; - assign _dfoo274 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo206 ; - assign _dfoo275 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo139 ; - assign _dfoo276 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo208 ; - assign _dfoo277 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo141 ; - assign _dfoo278 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo210 ; - assign _dfoo279 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo143 ; - assign _dfoo28 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo280 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo212 ; - assign _dfoo281 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo145 ; - assign _dfoo282 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo214 ; - assign _dfoo283 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo147 ; - assign _dfoo284 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo216 ; - assign _dfoo285 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo149 ; - assign _dfoo286 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo218 ; - assign _dfoo287 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo151 ; - assign _dfoo288 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo220 ; - assign _dfoo289 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo153 ; - assign _dfoo29 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo290 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo222 ; - assign _dfoo291 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo155 ; - assign _dfoo292 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo224 ; - assign _dfoo293 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo157 ; - assign _dfoo294 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo226 ; - assign _dfoo295 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo159 ; - assign _dfoo296 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo228 ; - assign _dfoo297 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo161 ; - assign _dfoo298 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo230 ; - assign _dfoo299 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo163 ; - assign _dfoo3 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo30 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo300 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo232 ; - assign _dfoo301 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo165 ; - assign _dfoo302 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo234 ; - assign _dfoo303 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo167 ; - assign _dfoo304 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo236 ; - assign _dfoo305 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo169 ; - assign _dfoo306 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo238 ; - assign _dfoo307 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo171 ; - assign _dfoo308 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo240 ; - assign _dfoo309 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo173 ; - assign _dfoo31 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo310 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo242 ; - assign _dfoo311 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo175 ; - assign _dfoo312 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo244 ; - assign _dfoo313 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo177 ; - assign _dfoo314 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo246 ; - assign _dfoo315 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo179 ; - assign _dfoo316 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo248 ; - assign _dfoo317 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo181 ; - assign _dfoo318 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo250 ; - assign _dfoo319 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo183 ; - assign _dfoo32 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo320 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo252 ; - assign _dfoo321 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo185 ; - assign _dfoo322 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo254 ; - assign _dfoo323 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo187 ; - assign _dfoo324 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo256 ; - assign _dfoo325 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo189 ; - assign _dfoo326 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo258 ; - assign _dfoo327 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo191 ; - assign _dfoo328 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo260 ; - assign _dfoo329 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo193 ; - assign _dfoo33 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo330 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo262 ; - assign _dfoo331 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo195 ; - assign _dfoo332 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo264 ; - assign _dfoo333 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo197 ; - assign _dfoo334 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo266 ; - assign _dfoo335 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo199 ; - assign _dfoo336 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo268 ; - assign _dfoo337 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo201 ; - assign _dfoo338 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo270 ; - assign _dfoo339 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo203 ; - assign _dfoo34 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo340 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo272 ; - assign _dfoo342 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo274 ; - assign _dfoo344 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo276 ; - assign _dfoo346 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo278 ; - assign _dfoo348 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo280 ; - assign _dfoo35 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo350 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo282 ; - assign _dfoo352 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo284 ; - assign _dfoo354 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo286 ; - assign _dfoo356 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo288 ; - assign _dfoo358 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo290 ; - assign _dfoo36 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo360 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo292 ; - assign _dfoo362 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo294 ; - assign _dfoo364 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo296 ; - assign _dfoo366 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo298 ; - assign _dfoo368 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo300 ; - assign _dfoo37 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo370 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo302 ; - assign _dfoo372 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo304 ; - assign _dfoo374 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo306 ; - assign _dfoo376 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo308 ; - assign _dfoo378 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo310 ; - assign _dfoo38 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo380 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo312 ; - assign _dfoo382 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo314 ; - assign _dfoo384 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo316 ; - assign _dfoo386 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo318 ; - assign _dfoo388 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo320 ; - assign _dfoo39 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo390 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo322 ; - assign _dfoo392 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo324 ; - assign _dfoo394 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo326 ; - assign _dfoo396 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo328 ; - assign _dfoo398 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo330 ; - assign _dfoo4 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo40 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo400 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo332 ; - assign _dfoo402 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo334 ; - assign _dfoo404 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo336 ; - assign _dfoo406 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo338 ; - assign _dfoo408 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo340 ; - assign _dfoo409 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo273 ; - assign _dfoo41 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo410 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo342 ; - assign _dfoo411 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo275 ; - assign _dfoo412 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo344 ; - assign _dfoo413 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo277 ; - assign _dfoo414 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo346 ; - assign _dfoo415 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo279 ; - assign _dfoo416 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo348 ; - assign _dfoo417 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo281 ; - assign _dfoo418 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo350 ; - assign _dfoo419 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo283 ; - assign _dfoo42 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo420 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo352 ; - assign _dfoo421 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo285 ; - assign _dfoo422 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo354 ; - assign _dfoo423 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo287 ; - assign _dfoo424 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo356 ; - assign _dfoo425 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo289 ; - assign _dfoo426 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo358 ; - assign _dfoo427 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo291 ; - assign _dfoo428 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo360 ; - assign _dfoo429 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo293 ; - assign _dfoo43 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo430 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo362 ; - assign _dfoo431 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo295 ; - assign _dfoo432 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo364 ; - assign _dfoo433 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo297 ; - assign _dfoo434 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo366 ; - assign _dfoo435 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo299 ; - assign _dfoo436 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo368 ; - assign _dfoo437 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo301 ; - assign _dfoo438 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo370 ; - assign _dfoo439 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo303 ; - assign _dfoo44 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo440 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo372 ; - assign _dfoo441 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo305 ; - assign _dfoo442 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo374 ; - assign _dfoo443 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo307 ; - assign _dfoo444 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo376 ; - assign _dfoo445 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo309 ; - assign _dfoo446 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo378 ; - assign _dfoo447 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo311 ; - assign _dfoo448 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo380 ; - assign _dfoo449 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo313 ; - assign _dfoo45 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo450 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo382 ; - assign _dfoo451 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo315 ; - assign _dfoo452 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo384 ; - assign _dfoo453 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo317 ; - assign _dfoo454 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo386 ; - assign _dfoo455 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo319 ; - assign _dfoo456 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo388 ; - assign _dfoo457 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo321 ; - assign _dfoo458 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo390 ; - assign _dfoo459 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo323 ; - assign _dfoo46 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo460 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo392 ; - assign _dfoo461 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo325 ; - assign _dfoo462 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo394 ; - assign _dfoo463 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo327 ; - assign _dfoo464 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo396 ; - assign _dfoo465 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo329 ; - assign _dfoo466 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo398 ; - assign _dfoo467 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo331 ; - assign _dfoo468 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo400 ; - assign _dfoo469 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo333 ; - assign _dfoo47 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo470 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo402 ; - assign _dfoo471 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo335 ; - assign _dfoo472 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo404 ; - assign _dfoo473 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo337 ; - assign _dfoo474 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo406 ; - assign _dfoo475 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo339 ; - assign _dfoo476 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo408 ; - assign _dfoo478 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo410 ; - assign _dfoo48 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo480 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo412 ; - assign _dfoo482 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo414 ; - assign _dfoo484 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo416 ; - assign _dfoo486 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo418 ; - assign _dfoo488 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo420 ; - assign _dfoo49 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo490 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo422 ; - assign _dfoo492 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo424 ; - assign _dfoo494 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo426 ; - assign _dfoo496 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo428 ; - assign _dfoo498 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo430 ; - assign _dfoo5 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo50 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo500 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo432 ; - assign _dfoo502 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo434 ; - assign _dfoo504 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo436 ; - assign _dfoo506 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo438 ; - assign _dfoo508 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo440 ; - assign _dfoo51 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo510 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo442 ; - assign _dfoo512 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo444 ; - assign _dfoo514 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo446 ; - assign _dfoo516 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo448 ; - assign _dfoo518 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo450 ; - assign _dfoo52 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo520 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo452 ; - assign _dfoo522 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo454 ; - assign _dfoo524 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo456 ; - assign _dfoo526 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo458 ; - assign _dfoo528 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo460 ; - assign _dfoo53 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo530 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo462 ; - assign _dfoo532 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo464 ; - assign _dfoo534 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo466 ; - assign _dfoo536 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo468 ; - assign _dfoo538 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo470 ; - assign _dfoo54 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo540 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo472 ; - assign _dfoo542 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo474 ; - assign _dfoo544 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo476 ; - assign _dfoo545 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo409 ; - assign _dfoo546 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo478 ; - assign _dfoo547 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo411 ; - assign _dfoo548 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo480 ; - assign _dfoo549 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo413 ; - assign _dfoo55 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo550 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo482 ; - assign _dfoo551 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo415 ; - assign _dfoo552 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo484 ; - assign _dfoo553 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo417 ; - assign _dfoo554 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo486 ; - assign _dfoo555 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo419 ; - assign _dfoo556 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo488 ; - assign _dfoo557 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo421 ; - assign _dfoo558 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo490 ; - assign _dfoo559 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo423 ; - assign _dfoo56 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo560 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo492 ; - assign _dfoo561 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo425 ; - assign _dfoo562 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo494 ; - assign _dfoo563 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo427 ; - assign _dfoo564 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo496 ; - assign _dfoo565 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo429 ; - assign _dfoo566 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo498 ; - assign _dfoo567 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo431 ; - assign _dfoo568 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo500 ; - assign _dfoo569 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo433 ; - assign _dfoo57 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo570 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo502 ; - assign _dfoo571 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo435 ; - assign _dfoo572 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo504 ; - assign _dfoo573 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo437 ; - assign _dfoo574 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo506 ; - assign _dfoo575 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo439 ; - assign _dfoo576 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo508 ; - assign _dfoo577 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo441 ; - assign _dfoo578 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo510 ; - assign _dfoo579 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo443 ; - assign _dfoo58 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo580 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo512 ; - assign _dfoo581 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo445 ; - assign _dfoo582 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo514 ; - assign _dfoo583 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo447 ; - assign _dfoo584 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo516 ; - assign _dfoo585 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo449 ; - assign _dfoo586 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo518 ; - assign _dfoo587 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo451 ; - assign _dfoo588 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo520 ; - assign _dfoo589 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo453 ; - assign _dfoo59 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo590 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo522 ; - assign _dfoo591 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo455 ; - assign _dfoo592 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo524 ; - assign _dfoo593 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo457 ; - assign _dfoo594 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo526 ; - assign _dfoo595 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo459 ; - assign _dfoo596 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo528 ; - assign _dfoo597 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo461 ; - assign _dfoo598 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo530 ; - assign _dfoo599 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo463 ; - assign _dfoo6 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo60 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo600 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo532 ; - assign _dfoo601 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo465 ; - assign _dfoo602 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo534 ; - assign _dfoo603 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo467 ; - assign _dfoo604 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo536 ; - assign _dfoo605 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo469 ; - assign _dfoo606 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo538 ; - assign _dfoo607 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo471 ; - assign _dfoo608 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo540 ; - assign _dfoo609 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo473 ; - assign _dfoo61 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo610 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo542 ; - assign _dfoo611 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo475 ; - assign _dfoo612 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo544 ; - assign _dfoo614 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo546 ; - assign _dfoo616 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo548 ; - assign _dfoo618 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo550 ; - assign _dfoo62 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo620 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo552 ; - assign _dfoo622 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo554 ; - assign _dfoo624 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo556 ; - assign _dfoo626 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo558 ; - assign _dfoo628 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo560 ; - assign _dfoo63 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo630 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo562 ; - assign _dfoo632 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo564 ; - assign _dfoo634 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo566 ; - assign _dfoo636 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo568 ; - assign _dfoo638 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo570 ; - assign _dfoo64 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo640 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo572 ; - assign _dfoo642 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo574 ; - assign _dfoo644 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo576 ; - assign _dfoo646 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo578 ; - assign _dfoo648 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo580 ; - assign _dfoo65 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo650 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo582 ; - assign _dfoo652 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo584 ; - assign _dfoo654 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo586 ; - assign _dfoo656 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo588 ; - assign _dfoo658 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo590 ; - assign _dfoo66 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo660 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo592 ; - assign _dfoo662 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo594 ; - assign _dfoo664 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo596 ; - assign _dfoo666 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo598 ; - assign _dfoo668 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo600 ; - assign _dfoo67 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo670 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo602 ; - assign _dfoo672 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo604 ; - assign _dfoo674 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo606 ; - assign _dfoo676 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo608 ; - assign _dfoo678 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo610 ; - assign _dfoo68 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo680 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo612 ; - assign _dfoo681 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo545 ; - assign _dfoo682 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo614 ; - assign _dfoo683 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo547 ; - assign _dfoo684 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo616 ; - assign _dfoo685 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo549 ; - assign _dfoo686 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo618 ; - assign _dfoo687 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo551 ; - assign _dfoo688 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo620 ; - assign _dfoo689 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo553 ; - assign _dfoo690 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo622 ; - assign _dfoo691 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo555 ; - assign _dfoo692 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo624 ; - assign _dfoo693 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo557 ; - assign _dfoo694 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo626 ; - assign _dfoo695 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo559 ; - assign _dfoo696 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo628 ; - assign _dfoo697 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo561 ; - assign _dfoo698 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo630 ; - assign _dfoo699 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo563 ; - assign _dfoo7 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo70 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo2 ; - assign _dfoo700 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo632 ; - assign _dfoo701 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo565 ; - assign _dfoo702 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo634 ; - assign _dfoo703 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo567 ; - assign _dfoo704 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo636 ; - assign _dfoo705 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo569 ; - assign _dfoo706 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo638 ; - assign _dfoo707 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo571 ; - assign _dfoo708 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo640 ; - assign _dfoo709 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo573 ; - assign _dfoo710 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo642 ; - assign _dfoo711 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo575 ; - assign _dfoo712 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo644 ; - assign _dfoo713 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo577 ; - assign _dfoo714 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo646 ; - assign _dfoo715 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo579 ; - assign _dfoo716 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo648 ; - assign _dfoo717 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo581 ; - assign _dfoo718 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo650 ; - assign _dfoo719 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo583 ; - assign _dfoo72 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo4 ; - assign _dfoo720 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo652 ; - assign _dfoo721 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo585 ; - assign _dfoo722 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo654 ; - assign _dfoo723 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo587 ; - assign _dfoo724 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo656 ; - assign _dfoo725 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo589 ; - assign _dfoo726 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo658 ; - assign _dfoo727 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo591 ; - assign _dfoo728 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo660 ; - assign _dfoo729 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo593 ; - assign _dfoo730 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo662 ; - assign _dfoo731 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo595 ; - assign _dfoo732 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo664 ; - assign _dfoo733 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo597 ; - assign _dfoo734 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo666 ; - assign _dfoo735 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo599 ; - assign _dfoo736 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo668 ; - assign _dfoo737 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo601 ; - assign _dfoo738 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo670 ; - assign _dfoo739 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo603 ; - assign _dfoo74 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo6 ; - assign _dfoo740 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo672 ; - assign _dfoo741 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo605 ; - assign _dfoo742 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo674 ; - assign _dfoo743 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo607 ; - assign _dfoo744 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo676 ; - assign _dfoo745 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo609 ; - assign _dfoo746 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo678 ; - assign _dfoo747 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo611 ; - assign _dfoo748 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo680 ; - assign _dfoo750 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo682 ; - assign _dfoo752 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo684 ; - assign _dfoo754 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo686 ; - assign _dfoo756 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo688 ; - assign _dfoo758 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo690 ; - assign _dfoo76 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo8 ; - assign _dfoo760 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo692 ; - assign _dfoo762 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo694 ; - assign _dfoo764 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo696 ; - assign _dfoo766 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo698 ; - assign _dfoo768 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo700 ; - assign _dfoo770 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo702 ; - assign _dfoo772 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo704 ; - assign _dfoo774 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo706 ; - assign _dfoo776 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo708 ; - assign _dfoo778 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo710 ; - assign _dfoo78 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo10 ; - assign _dfoo780 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo712 ; - assign _dfoo782 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo714 ; - assign _dfoo784 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo716 ; - assign _dfoo786 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo718 ; - assign _dfoo788 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo720 ; - assign _dfoo790 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo722 ; - assign _dfoo792 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo724 ; - assign _dfoo794 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo726 ; - assign _dfoo796 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo728 ; - assign _dfoo798 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo730 ; - assign _dfoo8 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo80 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo12 ; - assign _dfoo800 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo732 ; - assign _dfoo802 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo734 ; - assign _dfoo804 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo736 ; - assign _dfoo806 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo738 ; - assign _dfoo808 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo740 ; - assign _dfoo810 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo742 ; - assign _dfoo812 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo744 ; - assign _dfoo814 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo746 ; - assign _dfoo816 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo748 ; - assign _dfoo817 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo681 ; - assign _dfoo818 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo750 ; - assign _dfoo819 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo683 ; - assign _dfoo82 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo14 ; - assign _dfoo820 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo752 ; - assign _dfoo821 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo685 ; - assign _dfoo822 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo754 ; - assign _dfoo823 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo687 ; - assign _dfoo824 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo756 ; - assign _dfoo825 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo689 ; - assign _dfoo826 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo758 ; - assign _dfoo827 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo691 ; - assign _dfoo828 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo760 ; - assign _dfoo829 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo693 ; - assign _dfoo830 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo762 ; - assign _dfoo831 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo695 ; - assign _dfoo832 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo764 ; - assign _dfoo833 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo697 ; - assign _dfoo834 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo766 ; - assign _dfoo835 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo699 ; - assign _dfoo836 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo768 ; - assign _dfoo837 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo701 ; - assign _dfoo838 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo770 ; - assign _dfoo839 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo703 ; - assign _dfoo84 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo16 ; - assign _dfoo840 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo772 ; - assign _dfoo841 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo705 ; - assign _dfoo842 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo774 ; - assign _dfoo843 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo707 ; - assign _dfoo844 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo776 ; - assign _dfoo845 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo709 ; - assign _dfoo846 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo778 ; - assign _dfoo847 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo711 ; - assign _dfoo848 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo780 ; - assign _dfoo849 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo713 ; - assign _dfoo850 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo782 ; - assign _dfoo851 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo715 ; - assign _dfoo852 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo784 ; - assign _dfoo853 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo717 ; - assign _dfoo854 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo786 ; - assign _dfoo855 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo719 ; - assign _dfoo856 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo788 ; - assign _dfoo857 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo721 ; - assign _dfoo858 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo790 ; - assign _dfoo859 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo723 ; - assign _dfoo86 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo18 ; - assign _dfoo860 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo792 ; - assign _dfoo861 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo725 ; - assign _dfoo862 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo794 ; - assign _dfoo863 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo727 ; - assign _dfoo864 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo796 ; - assign _dfoo865 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo729 ; - assign _dfoo866 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo798 ; - assign _dfoo867 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo731 ; - assign _dfoo868 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo800 ; - assign _dfoo869 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo733 ; - assign _dfoo870 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo802 ; - assign _dfoo871 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo735 ; - assign _dfoo872 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo804 ; - assign _dfoo873 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo737 ; - assign _dfoo874 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo806 ; - assign _dfoo875 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo739 ; - assign _dfoo876 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo808 ; - assign _dfoo877 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo741 ; - assign _dfoo878 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo810 ; - assign _dfoo879 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo743 ; - assign _dfoo88 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo20 ; - assign _dfoo880 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo812 ; - assign _dfoo881 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo745 ; - assign _dfoo882 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo814 ; - assign _dfoo883 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo747 ; - assign _dfoo884 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo816 ; - assign _dfoo886 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo818 ; - assign _dfoo888 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo820 ; - assign _dfoo890 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo822 ; - assign _dfoo892 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo824 ; - assign _dfoo894 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo826 ; - assign _dfoo896 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo828 ; - assign _dfoo898 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo830 ; - assign _dfoo9 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo90 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo22 ; - assign _dfoo900 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo832 ; - assign _dfoo902 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo834 ; - assign _dfoo904 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo836 ; - assign _dfoo906 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo838 ; - assign _dfoo908 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo840 ; - assign _dfoo910 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo842 ; - assign _dfoo912 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo844 ; - assign _dfoo914 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo846 ; - assign _dfoo916 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo848 ; - assign _dfoo918 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo850 ; - assign _dfoo92 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo24 ; - assign _dfoo920 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo852 ; - assign _dfoo922 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo854 ; - assign _dfoo924 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo856 ; - assign _dfoo926 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo858 ; - assign _dfoo928 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo860 ; - assign _dfoo930 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo862 ; - assign _dfoo932 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo864 ; - assign _dfoo934 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo866 ; - assign _dfoo936 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo868 ; - assign _dfoo938 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo870 ; - assign _dfoo94 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo26 ; - assign _dfoo940 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo872 ; - assign _dfoo942 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo874 ; - assign _dfoo944 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo876 ; - assign _dfoo946 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo878 ; - assign _dfoo948 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo880 ; - assign _dfoo950 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo882 ; - assign _dfoo952 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo884 ; - assign _dfoo953 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo817 ; - assign _dfoo954 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo886 ; - assign _dfoo955 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo819 ; - assign _dfoo956 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo888 ; - assign _dfoo957 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo821 ; - assign _dfoo958 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo890 ; - assign _dfoo959 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo823 ; - assign _dfoo96 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo28 ; - assign _dfoo960 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo892 ; - assign _dfoo961 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo825 ; - assign _dfoo962 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo894 ; - assign _dfoo963 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo827 ; - assign _dfoo964 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo896 ; - assign _dfoo965 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo829 ; - assign _dfoo966 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo898 ; - assign _dfoo967 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo831 ; - assign _dfoo968 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo900 ; - assign _dfoo969 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo833 ; - assign _dfoo970 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo902 ; - assign _dfoo971 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo835 ; - assign _dfoo972 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo904 ; - assign _dfoo973 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo837 ; - assign _dfoo974 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo906 ; - assign _dfoo975 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo839 ; - assign _dfoo976 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo908 ; - assign _dfoo977 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo841 ; - assign _dfoo978 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo910 ; - assign _dfoo979 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo843 ; - assign _dfoo98 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo30 ; - assign _dfoo980 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo912 ; - assign _dfoo981 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo845 ; - assign _dfoo982 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo914 ; - assign _dfoo983 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo847 ; - assign _dfoo984 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo916 ; - assign _dfoo985 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo849 ; - assign _dfoo986 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo918 ; - assign _dfoo987 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo851 ; - assign _dfoo988 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo920 ; - assign _dfoo989 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo853 ; - assign _dfoo990 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo922 ; - assign _dfoo991 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo855 ; - assign _dfoo992 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo924 ; - assign _dfoo993 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo857 ; - assign _dfoo994 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo926 ; - assign _dfoo995 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo859 ; - assign _dfoo996 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo928 ; - assign _dfoo997 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo861 ; - assign _dfoo998 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo930 ; - assign _dfoo999 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo863 ; - assign a__h71312 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73317 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; - assign addr_offset__h13216 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26929 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71313 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73318 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = - addr_offset__h13216 < 64'h0000000000003000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = - addr_offset__h13216[11:7] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 = - addr_offset__h13216 < 64'h0000000000001000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 = - addr_offset__h13216[11:2] <= 10'd16 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 = - addr_offset__h13216[16:12] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 = - addr_offset__h13216 < 64'h0000000000002000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = - source_id_base__h13630 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26929[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26929[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26929[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26929 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26929[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26929[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26929[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26929[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26929[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26929[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26929[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26929[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26929[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26929[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26929[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26929[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26929[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26929[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26929[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26929[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26929[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26929 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28148 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26929 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26929[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26929[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26929[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && - m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && - m_vvrg_ie_1_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && - m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && - m_vvrg_ie_1_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && - m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && - m_vvrg_ie_1_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && - m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && - m_vvrg_ie_1_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 || - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 || - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 || - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 || - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && - m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && - m_vvrg_ie_1_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && - m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && - m_vvrg_ie_1_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && - m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && - m_vvrg_ie_1_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = - m_vrg_source_ip_16 && - !m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 || - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 || - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 || - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 ; - assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = - m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && - m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && - m_vvrg_ie_1_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && - m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && - m_vvrg_ie_1_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && - m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && - m_vvrg_ie_1_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && - m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && - m_vvrg_ie_1_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && - m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && - m_vvrg_ie_1_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && - m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && - m_vvrg_ie_1_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 || - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 || - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 || - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 || - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && - m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && - m_vvrg_ie_1_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && - m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && - m_vvrg_ie_1_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; - assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 = - m_vrg_source_prio_16 <= - (m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ; - assign max_id__h23959 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ; - assign rdata___1__h26404 = { rdata__h26202[31:0], 32'h0 } ; - assign rdata__h26202 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 64'd0 : - y_avValue_fst__h26194 ; - assign rresp__h26203 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 2'b11 : - y_avValue_snd__h26195 ; - assign source_id__h15665 = { addr_offset__h13216[4:0], 5'd31 } ; - assign source_id__h15772 = { addr_offset__h13216[4:0], 5'd30 } ; - assign source_id__h15845 = { addr_offset__h13216[4:0], 5'd29 } ; - assign source_id__h15918 = { addr_offset__h13216[4:0], 5'd28 } ; - assign source_id__h15991 = { addr_offset__h13216[4:0], 5'd27 } ; - assign source_id__h16064 = { addr_offset__h13216[4:0], 5'd26 } ; - assign source_id__h16137 = { addr_offset__h13216[4:0], 5'd25 } ; - assign source_id__h16210 = { addr_offset__h13216[4:0], 5'd24 } ; - assign source_id__h16283 = { addr_offset__h13216[4:0], 5'd23 } ; - assign source_id__h16356 = { addr_offset__h13216[4:0], 5'd22 } ; - assign source_id__h16429 = { addr_offset__h13216[4:0], 5'd21 } ; - assign source_id__h16502 = { addr_offset__h13216[4:0], 5'd20 } ; - assign source_id__h16575 = { addr_offset__h13216[4:0], 5'd19 } ; - assign source_id__h16648 = { addr_offset__h13216[4:0], 5'd18 } ; - assign source_id__h16721 = { addr_offset__h13216[4:0], 5'd17 } ; - assign source_id__h16794 = { addr_offset__h13216[4:0], 5'd16 } ; - assign source_id__h16867 = { addr_offset__h13216[4:0], 5'd15 } ; - assign source_id__h16940 = { addr_offset__h13216[4:0], 5'd14 } ; - assign source_id__h17013 = { addr_offset__h13216[4:0], 5'd13 } ; - assign source_id__h17086 = { addr_offset__h13216[4:0], 5'd12 } ; - assign source_id__h17159 = { addr_offset__h13216[4:0], 5'd11 } ; - assign source_id__h17232 = { addr_offset__h13216[4:0], 5'd10 } ; - assign source_id__h17305 = { addr_offset__h13216[4:0], 5'd9 } ; - assign source_id__h17378 = { addr_offset__h13216[4:0], 5'd8 } ; - assign source_id__h17451 = { addr_offset__h13216[4:0], 5'd7 } ; - assign source_id__h17524 = { addr_offset__h13216[4:0], 5'd6 } ; - assign source_id__h17597 = { addr_offset__h13216[4:0], 5'd5 } ; - assign source_id__h17670 = { addr_offset__h13216[4:0], 5'd4 } ; - assign source_id__h17743 = { addr_offset__h13216[4:0], 5'd3 } ; - assign source_id__h17816 = { addr_offset__h13216[4:0], 5'd2 } ; - assign source_id__h17889 = { addr_offset__h13216[4:0], 5'd1 } ; - assign source_id__h20137 = 10'd31 + source_id_base__h13630 ; - assign source_id__h20313 = 10'd30 + source_id_base__h13630 ; - assign source_id__h20421 = 10'd29 + source_id_base__h13630 ; - assign source_id__h20529 = 10'd28 + source_id_base__h13630 ; - assign source_id__h20637 = 10'd27 + source_id_base__h13630 ; - assign source_id__h20745 = 10'd26 + source_id_base__h13630 ; - assign source_id__h20853 = 10'd25 + source_id_base__h13630 ; - assign source_id__h20961 = 10'd24 + source_id_base__h13630 ; - assign source_id__h21069 = 10'd23 + source_id_base__h13630 ; - assign source_id__h21177 = 10'd22 + source_id_base__h13630 ; - assign source_id__h21285 = 10'd21 + source_id_base__h13630 ; - assign source_id__h21393 = 10'd20 + source_id_base__h13630 ; - assign source_id__h21501 = 10'd19 + source_id_base__h13630 ; - assign source_id__h21609 = 10'd18 + source_id_base__h13630 ; - assign source_id__h21717 = 10'd17 + source_id_base__h13630 ; - assign source_id__h21825 = 10'd16 + source_id_base__h13630 ; - assign source_id__h21933 = 10'd15 + source_id_base__h13630 ; - assign source_id__h22041 = 10'd14 + source_id_base__h13630 ; - assign source_id__h22149 = 10'd13 + source_id_base__h13630 ; - assign source_id__h22257 = 10'd12 + source_id_base__h13630 ; - assign source_id__h22365 = 10'd11 + source_id_base__h13630 ; - assign source_id__h22473 = 10'd10 + source_id_base__h13630 ; - assign source_id__h22581 = 10'd9 + source_id_base__h13630 ; - assign source_id__h22689 = 10'd8 + source_id_base__h13630 ; - assign source_id__h22797 = 10'd7 + source_id_base__h13630 ; - assign source_id__h22905 = 10'd6 + source_id_base__h13630 ; - assign source_id__h23013 = 10'd5 + source_id_base__h13630 ; - assign source_id__h23121 = 10'd4 + source_id_base__h13630 ; - assign source_id__h23229 = 10'd3 + source_id_base__h13630 ; - assign source_id__h23337 = 10'd2 + source_id_base__h13630 ; - assign source_id__h23445 = 10'd1 + source_id_base__h13630 ; - assign source_id__h29475 = { addr_offset__h26929[4:0], 5'd1 } ; - assign source_id__h30685 = { addr_offset__h26929[4:0], 5'd2 } ; - assign source_id__h31895 = { addr_offset__h26929[4:0], 5'd3 } ; - assign source_id__h33105 = { addr_offset__h26929[4:0], 5'd4 } ; - assign source_id__h34315 = { addr_offset__h26929[4:0], 5'd5 } ; - assign source_id__h35525 = { addr_offset__h26929[4:0], 5'd6 } ; - assign source_id__h36735 = { addr_offset__h26929[4:0], 5'd7 } ; - assign source_id__h37945 = { addr_offset__h26929[4:0], 5'd8 } ; - assign source_id__h39155 = { addr_offset__h26929[4:0], 5'd9 } ; - assign source_id__h40365 = { addr_offset__h26929[4:0], 5'd10 } ; - assign source_id__h41575 = { addr_offset__h26929[4:0], 5'd11 } ; - assign source_id__h42785 = { addr_offset__h26929[4:0], 5'd12 } ; - assign source_id__h43995 = { addr_offset__h26929[4:0], 5'd13 } ; - assign source_id__h45205 = { addr_offset__h26929[4:0], 5'd14 } ; - assign source_id__h46415 = { addr_offset__h26929[4:0], 5'd15 } ; - assign source_id__h47625 = { addr_offset__h26929[4:0], 5'd16 } ; - assign source_id__h48835 = { addr_offset__h26929[4:0], 5'd17 } ; - assign source_id__h50045 = { addr_offset__h26929[4:0], 5'd18 } ; - assign source_id__h51255 = { addr_offset__h26929[4:0], 5'd19 } ; - assign source_id__h52465 = { addr_offset__h26929[4:0], 5'd20 } ; - assign source_id__h53675 = { addr_offset__h26929[4:0], 5'd21 } ; - assign source_id__h54885 = { addr_offset__h26929[4:0], 5'd22 } ; - assign source_id__h56095 = { addr_offset__h26929[4:0], 5'd23 } ; - assign source_id__h57305 = { addr_offset__h26929[4:0], 5'd24 } ; - assign source_id__h58515 = { addr_offset__h26929[4:0], 5'd25 } ; - assign source_id__h59725 = { addr_offset__h26929[4:0], 5'd26 } ; - assign source_id__h60935 = { addr_offset__h26929[4:0], 5'd27 } ; - assign source_id__h62145 = { addr_offset__h26929[4:0], 5'd28 } ; - assign source_id__h63355 = { addr_offset__h26929[4:0], 5'd29 } ; - assign source_id__h64565 = { addr_offset__h26929[4:0], 5'd30 } ; - assign source_id__h65775 = { addr_offset__h26929[4:0], 5'd31 } ; - assign source_id__h67436 = { 5'd0, x__h67487 } ; - assign source_id_base__h13630 = { addr_offset__h13216[4:0], 5'h0 } ; - assign source_id_base__h28148 = { addr_offset__h26929[4:0], 5'h0 } ; - assign v__h13422 = { 61'd0, x__h13493 } ; - assign v__h13671 = { 32'd0, v_ip__h13674 } ; - assign v__h18144 = { 32'd0, v_ie__h18147 } ; - assign v__h23761 = { 61'd0, x__h23832 } ; - assign v__h25455 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ? - v__h25474 : - 64'd0 ; - assign v__h25474 = { 59'd0, max_id__h23959 } ; - assign v__h26934 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? - 2'b11 : - v__h27094 ; - assign v__h27094 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27107 : - v__h27942 ; - assign v__h27107 = - (addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? - 2'b0 : - 2'b10 ; - assign v__h27942 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27961 : - v__h28125 ; - assign v__h27961 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? - 2'b0 : - 2'b10 ; - assign v__h28125 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28144 : - v__h67107 ; - assign v__h28144 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? - 2'b0 : - 2'b10 ; - assign v__h67144 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - 2'b0 : - 2'b10 ; - assign v__h67432 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67476 : - 2'b10 ; - assign v__h67476 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? - 2'b0 : - 2'b10 ; - assign v_ie__h18147 = - { source_id__h20137 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h20313 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h20421 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h20529 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h20637 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h20745 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h20853 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h20961 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h21069 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h21177 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h21285 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h21393 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h21501 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h21609 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h21717 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h21825 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h21933 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h22041 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h22149 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h22257 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h22365 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h22473 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h22581 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h22689 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h22797 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h22905 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h23013 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h23121 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h23229 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h23337 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h23445 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h13674 = - { source_id__h15665 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - source_id__h15772 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - source_id__h15845 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - source_id__h15918 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - source_id__h15991 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - source_id__h16064 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - source_id__h16137 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - source_id__h16210 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - source_id__h16283 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - source_id__h16356 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - source_id__h16429 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - source_id__h16502 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - source_id__h16575 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - source_id__h16648 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - source_id__h16721 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - source_id__h16794 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - source_id__h16867 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - source_id__h16940 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - source_id__h17013 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - source_id__h17086 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - source_id__h17159 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - source_id__h17232 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - source_id__h17305 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - source_id__h17378 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - source_id__h17451 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - source_id__h17524 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - source_id__h17597 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - source_id__h17670 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - source_id__h17743 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - source_id__h17816 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - source_id__h17889 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26930 = - (addr_offset__h26929[2:0] == 3'd4) ? - m_slave_xactor_f_wr_data$D_OUT[72:41] : - m_slave_xactor_f_wr_data$D_OUT[40:9] ; - assign x__h23673 = - { addr_offset__h13216[31:16], 4'd0, addr_offset__h13216[11:0] } ; - assign x__h26361 = - (addr_offset__h13216[2:0] == 3'd4) ? - rdata___1__h26404 : - rdata__h26202 ; - assign x__h67110 = - { addr_offset__h26929[31:16], 4'd0, addr_offset__h26929[11:0] } ; - assign y_avValue_fst__h26094 = (x__h24011 == 5'd0) ? v__h25455 : 64'd0 ; - assign y_avValue_fst__h26115 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_fst__h26094 : - 64'd0 ; - assign y_avValue_fst__h26127 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - v__h23761 : - 64'd0 ; - assign y_avValue_fst__h26143 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - v__h18144 : - 64'd0 ; - assign y_avValue_fst__h26159 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - v__h13671 : - 64'd0 ; - assign y_avValue_fst__h26164 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_fst__h26143 : - y_avValue_fst__h26148 ; - assign y_avValue_fst__h26175 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - v__h13422 : - 64'd0 ; - assign y_avValue_fst__h26180 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_fst__h26159 : - y_avValue_fst__h26164 ; - assign y_avValue_fst__h26194 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_fst__h26175 : - y_avValue_fst__h26180 ; - assign y_avValue_snd__h26095 = (x__h24011 == 5'd0) ? 2'b0 : 2'b10 ; - assign y_avValue_snd__h26116 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_snd__h26095 : - 2'b10 ; - assign y_avValue_snd__h26128 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26144 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26160 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26165 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_snd__h26144 : - y_avValue_snd__h26149 ; - assign y_avValue_snd__h26176 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26181 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_snd__h26160 : - y_avValue_snd__h26165 ; - assign y_avValue_snd__h26195 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_snd__h26176 : - y_avValue_snd__h26181 ; - always@(addr_offset__h13216 or - m_vrg_source_prio_0 or - m_vrg_source_prio_1 or - m_vrg_source_prio_2 or - m_vrg_source_prio_3 or - m_vrg_source_prio_4 or - m_vrg_source_prio_5 or - m_vrg_source_prio_6 or - m_vrg_source_prio_7 or - m_vrg_source_prio_8 or - m_vrg_source_prio_9 or - m_vrg_source_prio_10 or - m_vrg_source_prio_11 or - m_vrg_source_prio_12 or - m_vrg_source_prio_13 or - m_vrg_source_prio_14 or - m_vrg_source_prio_15 or m_vrg_source_prio_16) - begin - case (addr_offset__h13216[11:2]) - 10'd0: x__h13493 = m_vrg_source_prio_0; - 10'd1: x__h13493 = m_vrg_source_prio_1; - 10'd2: x__h13493 = m_vrg_source_prio_2; - 10'd3: x__h13493 = m_vrg_source_prio_3; - 10'd4: x__h13493 = m_vrg_source_prio_4; - 10'd5: x__h13493 = m_vrg_source_prio_5; - 10'd6: x__h13493 = m_vrg_source_prio_6; - 10'd7: x__h13493 = m_vrg_source_prio_7; - 10'd8: x__h13493 = m_vrg_source_prio_8; - 10'd9: x__h13493 = m_vrg_source_prio_9; - 10'd10: x__h13493 = m_vrg_source_prio_10; - 10'd11: x__h13493 = m_vrg_source_prio_11; - 10'd12: x__h13493 = m_vrg_source_prio_12; - 10'd13: x__h13493 = m_vrg_source_prio_13; - 10'd14: x__h13493 = m_vrg_source_prio_14; - 10'd15: x__h13493 = m_vrg_source_prio_15; - 10'd16: x__h13493 = m_vrg_source_prio_16; - default: x__h13493 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_target_threshold_0 or m_vrg_target_threshold_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h23832 = m_vrg_target_threshold_0; - 5'd1: x__h23832 = m_vrg_target_threshold_1; - default: x__h23832 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h24011 = m_vrg_servicing_source_0; - 5'd1: x__h24011 = m_vrg_servicing_source_1; - default: x__h24011 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h26929 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h26929[16:12]) - 5'd0: x__h67487 = m_vrg_servicing_source_0; - 5'd1: x__h67487 = m_vrg_servicing_source_1; - default: x__h67487 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15665 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15665) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15772 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15772) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15845 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15845) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15918 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15918) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15991 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15991) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16064 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16064) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17159 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17159) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16137 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16137) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16210 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16210) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16283 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16283) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16356 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16356) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16429 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16429) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16502 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16502) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16575 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16575) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16648 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16648) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16721 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16721) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16794 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16794) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16867 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16867) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16940 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16940) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17013 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17013) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17086 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17086) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17232 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17232) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17305 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17305) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17378 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17378) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17451 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17451) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17524 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17524) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17597 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17597) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17670 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17670) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17743 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17743) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17889 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17889) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17816 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17816) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_snd__h26128 or y_avValue_snd__h26116) - begin - case (x__h23673) - 32'h00200000: y_avValue_snd__h26149 = y_avValue_snd__h26128; - 32'h00200004: y_avValue_snd__h26149 = y_avValue_snd__h26116; - default: y_avValue_snd__h26149 = 2'b10; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_0_1; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_1_1; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_0_2; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_1_2; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_0_3; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_1_3; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_0_4; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_1_4; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_0_5; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_1_5; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_0_6; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_1_6; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_0_7; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_1_7; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_0_8; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_1_8; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_0_9; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_1_9; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_0_10; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_1_10; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_0_11; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_1_11; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_0_12; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_1_12; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_0_13; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_1_13; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_0_14; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_1_14; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_0_15; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_1_15; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_0_16; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_1_16; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_fst__h26127 or y_avValue_fst__h26115) - begin - case (x__h23673) - 32'h00200000: y_avValue_fst__h26148 = y_avValue_fst__h26127; - 32'h00200004: y_avValue_fst__h26148 = y_avValue_fst__h26115; - default: y_avValue_fst__h26148 = 64'd0; - endcase - end - always@(source_id__h67436 or - m_vrg_source_busy_0 or - m_vrg_source_busy_1 or - m_vrg_source_busy_2 or - m_vrg_source_busy_3 or - m_vrg_source_busy_4 or - m_vrg_source_busy_5 or - m_vrg_source_busy_6 or - m_vrg_source_busy_7 or - m_vrg_source_busy_8 or - m_vrg_source_busy_9 or - m_vrg_source_busy_10 or - m_vrg_source_busy_11 or - m_vrg_source_busy_12 or - m_vrg_source_busy_13 or - m_vrg_source_busy_14 or - m_vrg_source_busy_15 or m_vrg_source_busy_16) - begin - case (source_id__h67436) - 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_0; - 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_1; - 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_2; - 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_3; - 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_4; - 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_5; - 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_6; - 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_7; - 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_8; - 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_9; - 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_10; - 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_11; - 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_12; - 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_13; - 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_14; - 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_15; - 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h67110 or v__h67144 or v__h67432) - begin - case (x__h67110) - 32'h00200000: v__h67107 = v__h67144; - 32'h00200004: v__h67107 = v__h67432; - default: v__h67107 = 2'b10; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_cfg_verbosity$EN) - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN; - if (m_vrg_servicing_source_0$EN) - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_0$D_IN; - if (m_vrg_servicing_source_1$EN) - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_1$D_IN; - if (m_vrg_source_busy_0$EN) - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_0$D_IN; - if (m_vrg_source_busy_1$EN) - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_1$D_IN; - if (m_vrg_source_busy_10$EN) - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_10$D_IN; - if (m_vrg_source_busy_11$EN) - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_11$D_IN; - if (m_vrg_source_busy_12$EN) - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_12$D_IN; - if (m_vrg_source_busy_13$EN) - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_13$D_IN; - if (m_vrg_source_busy_14$EN) - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_14$D_IN; - if (m_vrg_source_busy_15$EN) - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_15$D_IN; - if (m_vrg_source_busy_16$EN) - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_16$D_IN; - if (m_vrg_source_busy_2$EN) - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_2$D_IN; - if (m_vrg_source_busy_3$EN) - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_3$D_IN; - if (m_vrg_source_busy_4$EN) - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_4$D_IN; - if (m_vrg_source_busy_5$EN) - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_5$D_IN; - if (m_vrg_source_busy_6$EN) - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_6$D_IN; - if (m_vrg_source_busy_7$EN) - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_7$D_IN; - if (m_vrg_source_busy_8$EN) - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_8$D_IN; - if (m_vrg_source_busy_9$EN) - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_9$D_IN; - if (m_vrg_source_ip_0$EN) - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_0$D_IN; - if (m_vrg_source_ip_1$EN) - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_1$D_IN; - if (m_vrg_source_ip_10$EN) - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_10$D_IN; - if (m_vrg_source_ip_11$EN) - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_11$D_IN; - if (m_vrg_source_ip_12$EN) - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_12$D_IN; - if (m_vrg_source_ip_13$EN) - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_13$D_IN; - if (m_vrg_source_ip_14$EN) - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_14$D_IN; - if (m_vrg_source_ip_15$EN) - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_15$D_IN; - if (m_vrg_source_ip_16$EN) - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_16$D_IN; - if (m_vrg_source_ip_2$EN) - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_2$D_IN; - if (m_vrg_source_ip_3$EN) - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_3$D_IN; - if (m_vrg_source_ip_4$EN) - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_4$D_IN; - if (m_vrg_source_ip_5$EN) - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_5$D_IN; - if (m_vrg_source_ip_6$EN) - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_6$D_IN; - if (m_vrg_source_ip_7$EN) - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_7$D_IN; - if (m_vrg_source_ip_8$EN) - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_8$D_IN; - if (m_vrg_source_ip_9$EN) - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_9$D_IN; - if (m_vrg_source_prio_0$EN) - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_0$D_IN; - if (m_vrg_source_prio_1$EN) - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_1$D_IN; - if (m_vrg_source_prio_10$EN) - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_10$D_IN; - if (m_vrg_source_prio_11$EN) - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_11$D_IN; - if (m_vrg_source_prio_12$EN) - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_12$D_IN; - if (m_vrg_source_prio_13$EN) - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_13$D_IN; - if (m_vrg_source_prio_14$EN) - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_14$D_IN; - if (m_vrg_source_prio_15$EN) - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_15$D_IN; - if (m_vrg_source_prio_16$EN) - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_16$D_IN; - if (m_vrg_source_prio_2$EN) - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_2$D_IN; - if (m_vrg_source_prio_3$EN) - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_3$D_IN; - if (m_vrg_source_prio_4$EN) - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_4$D_IN; - if (m_vrg_source_prio_5$EN) - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_5$D_IN; - if (m_vrg_source_prio_6$EN) - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_6$D_IN; - if (m_vrg_source_prio_7$EN) - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_7$D_IN; - if (m_vrg_source_prio_8$EN) - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_8$D_IN; - if (m_vrg_source_prio_9$EN) - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_9$D_IN; - if (m_vrg_target_threshold_0$EN) - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_0$D_IN; - if (m_vrg_target_threshold_1$EN) - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_1$D_IN; - if (m_vvrg_ie_0_0$EN) - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_0$D_IN; - if (m_vvrg_ie_0_1$EN) - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_1$D_IN; - if (m_vvrg_ie_0_10$EN) - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_10$D_IN; - if (m_vvrg_ie_0_11$EN) - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_11$D_IN; - if (m_vvrg_ie_0_12$EN) - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_12$D_IN; - if (m_vvrg_ie_0_13$EN) - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_13$D_IN; - if (m_vvrg_ie_0_14$EN) - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_14$D_IN; - if (m_vvrg_ie_0_15$EN) - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_15$D_IN; - if (m_vvrg_ie_0_16$EN) - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_16$D_IN; - if (m_vvrg_ie_0_2$EN) - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_2$D_IN; - if (m_vvrg_ie_0_3$EN) - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_3$D_IN; - if (m_vvrg_ie_0_4$EN) - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_4$D_IN; - if (m_vvrg_ie_0_5$EN) - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_5$D_IN; - if (m_vvrg_ie_0_6$EN) - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_6$D_IN; - if (m_vvrg_ie_0_7$EN) - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_7$D_IN; - if (m_vvrg_ie_0_8$EN) - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_8$D_IN; - if (m_vvrg_ie_0_9$EN) - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_9$D_IN; - if (m_vvrg_ie_1_0$EN) - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_0$D_IN; - if (m_vvrg_ie_1_1$EN) - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_1$D_IN; - if (m_vvrg_ie_1_10$EN) - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_10$D_IN; - if (m_vvrg_ie_1_11$EN) - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_11$D_IN; - if (m_vvrg_ie_1_12$EN) - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_12$D_IN; - if (m_vvrg_ie_1_13$EN) - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_13$D_IN; - if (m_vvrg_ie_1_14$EN) - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_14$D_IN; - if (m_vvrg_ie_1_15$EN) - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_15$D_IN; - if (m_vvrg_ie_1_16$EN) - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_16$D_IN; - if (m_vvrg_ie_1_2$EN) - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_2$D_IN; - if (m_vvrg_ie_1_3$EN) - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_3$D_IN; - if (m_vvrg_ie_1_4$EN) - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_4$D_IN; - if (m_vvrg_ie_1_5$EN) - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_5$D_IN; - if (m_vvrg_ie_1_6$EN) - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_6$D_IN; - if (m_vvrg_ie_1_7$EN) - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_7$D_IN; - if (m_vvrg_ie_1_8$EN) - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_8$D_IN; - if (m_vvrg_ie_1_9$EN) - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_9$D_IN; - end - if (m_rg_addr_base$EN) - m_rg_addr_base <= `BSV_ASSIGNMENT_DELAY m_rg_addr_base$D_IN; - if (m_rg_addr_lim$EN) - m_rg_addr_lim <= `BSV_ASSIGNMENT_DELAY m_rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_cfg_verbosity = 4'hA; - m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - m_vrg_servicing_source_0 = 5'h0A; - m_vrg_servicing_source_1 = 5'h0A; - m_vrg_source_busy_0 = 1'h0; - m_vrg_source_busy_1 = 1'h0; - m_vrg_source_busy_10 = 1'h0; - m_vrg_source_busy_11 = 1'h0; - m_vrg_source_busy_12 = 1'h0; - m_vrg_source_busy_13 = 1'h0; - m_vrg_source_busy_14 = 1'h0; - m_vrg_source_busy_15 = 1'h0; - m_vrg_source_busy_16 = 1'h0; - m_vrg_source_busy_2 = 1'h0; - m_vrg_source_busy_3 = 1'h0; - m_vrg_source_busy_4 = 1'h0; - m_vrg_source_busy_5 = 1'h0; - m_vrg_source_busy_6 = 1'h0; - m_vrg_source_busy_7 = 1'h0; - m_vrg_source_busy_8 = 1'h0; - m_vrg_source_busy_9 = 1'h0; - m_vrg_source_ip_0 = 1'h0; - m_vrg_source_ip_1 = 1'h0; - m_vrg_source_ip_10 = 1'h0; - m_vrg_source_ip_11 = 1'h0; - m_vrg_source_ip_12 = 1'h0; - m_vrg_source_ip_13 = 1'h0; - m_vrg_source_ip_14 = 1'h0; - m_vrg_source_ip_15 = 1'h0; - m_vrg_source_ip_16 = 1'h0; - m_vrg_source_ip_2 = 1'h0; - m_vrg_source_ip_3 = 1'h0; - m_vrg_source_ip_4 = 1'h0; - m_vrg_source_ip_5 = 1'h0; - m_vrg_source_ip_6 = 1'h0; - m_vrg_source_ip_7 = 1'h0; - m_vrg_source_ip_8 = 1'h0; - m_vrg_source_ip_9 = 1'h0; - m_vrg_source_prio_0 = 3'h2; - m_vrg_source_prio_1 = 3'h2; - m_vrg_source_prio_10 = 3'h2; - m_vrg_source_prio_11 = 3'h2; - m_vrg_source_prio_12 = 3'h2; - m_vrg_source_prio_13 = 3'h2; - m_vrg_source_prio_14 = 3'h2; - m_vrg_source_prio_15 = 3'h2; - m_vrg_source_prio_16 = 3'h2; - m_vrg_source_prio_2 = 3'h2; - m_vrg_source_prio_3 = 3'h2; - m_vrg_source_prio_4 = 3'h2; - m_vrg_source_prio_5 = 3'h2; - m_vrg_source_prio_6 = 3'h2; - m_vrg_source_prio_7 = 3'h2; - m_vrg_source_prio_8 = 3'h2; - m_vrg_source_prio_9 = 3'h2; - m_vrg_target_threshold_0 = 3'h2; - m_vrg_target_threshold_1 = 3'h2; - m_vvrg_ie_0_0 = 1'h0; - m_vvrg_ie_0_1 = 1'h0; - m_vvrg_ie_0_10 = 1'h0; - m_vvrg_ie_0_11 = 1'h0; - m_vvrg_ie_0_12 = 1'h0; - m_vvrg_ie_0_13 = 1'h0; - m_vvrg_ie_0_14 = 1'h0; - m_vvrg_ie_0_15 = 1'h0; - m_vvrg_ie_0_16 = 1'h0; - m_vvrg_ie_0_2 = 1'h0; - m_vvrg_ie_0_3 = 1'h0; - m_vvrg_ie_0_4 = 1'h0; - m_vvrg_ie_0_5 = 1'h0; - m_vvrg_ie_0_6 = 1'h0; - m_vvrg_ie_0_7 = 1'h0; - m_vvrg_ie_0_8 = 1'h0; - m_vvrg_ie_0_9 = 1'h0; - m_vvrg_ie_1_0 = 1'h0; - m_vvrg_ie_1_1 = 1'h0; - m_vvrg_ie_1_10 = 1'h0; - m_vvrg_ie_1_11 = 1'h0; - m_vvrg_ie_1_12 = 1'h0; - m_vvrg_ie_1_13 = 1'h0; - m_vvrg_ie_1_14 = 1'h0; - m_vvrg_ie_1_15 = 1'h0; - m_vvrg_ie_1_16 = 1'h0; - m_vvrg_ie_1_2 = 1'h0; - m_vvrg_ie_1_3 = 1'h0; - m_vvrg_ie_1_4 = 1'h0; - m_vvrg_ie_1_5 = 1'h0; - m_vvrg_ie_1_6 = 1'h0; - m_vvrg_ie_1_7 = 1'h0; - m_vvrg_ie_1_8 = 1'h0; - m_vvrg_ie_1_9 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src IPs :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src Prios:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src busy :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71312, - m_vrg_target_threshold_0, - b__h71313, - m_vrg_servicing_source_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73317, - m_vrg_target_threshold_1, - b__h73318, - m_vrg_servicing_source_1); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - begin - v__h75676 = $stime; - #0; - end - v__h75670 = v__h75676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75670, - $signed(32'd1), - v_sources_0_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - begin - v__h75874 = $stime; - #0; - end - v__h75868 = v__h75874 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75868, - $signed(32'd2), - v_sources_1_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - begin - v__h76072 = $stime; - #0; - end - v__h76066 = v__h76072 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76066, - $signed(32'd3), - v_sources_2_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - begin - v__h76270 = $stime; - #0; - end - v__h76264 = v__h76270 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76264, - $signed(32'd4), - v_sources_3_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - begin - v__h76468 = $stime; - #0; - end - v__h76462 = v__h76468 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76462, - $signed(32'd5), - v_sources_4_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - begin - v__h76666 = $stime; - #0; - end - v__h76660 = v__h76666 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76660, - $signed(32'd6), - v_sources_5_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - begin - v__h76864 = $stime; - #0; - end - v__h76858 = v__h76864 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76858, - $signed(32'd7), - v_sources_6_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - begin - v__h77062 = $stime; - #0; - end - v__h77056 = v__h77062 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77056, - $signed(32'd8), - v_sources_7_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - begin - v__h77260 = $stime; - #0; - end - v__h77254 = v__h77260 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77254, - $signed(32'd9), - v_sources_8_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - begin - v__h77458 = $stime; - #0; - end - v__h77452 = v__h77458 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77452, - $signed(32'd10), - v_sources_9_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - begin - v__h77656 = $stime; - #0; - end - v__h77650 = v__h77656 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77650, - $signed(32'd11), - v_sources_10_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - begin - v__h77854 = $stime; - #0; - end - v__h77848 = v__h77854 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77848, - $signed(32'd12), - v_sources_11_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - begin - v__h78052 = $stime; - #0; - end - v__h78046 = v__h78052 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78046, - $signed(32'd13), - v_sources_12_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - begin - v__h78250 = $stime; - #0; - end - v__h78244 = v__h78250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78244, - $signed(32'd14), - v_sources_13_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - begin - v__h78448 = $stime; - #0; - end - v__h78442 = v__h78448 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78442, - $signed(32'd15), - v_sources_14_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - begin - v__h78646 = $stime; - #0; - end - v__h78640 = v__h78646 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78640, - $signed(32'd16), - v_sources_15_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - begin - v__h6144 = $stime; - #0; - end - v__h6138 = v__h6144 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h6138); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h13080 = $stime; - #0; - end - v__h13074 = v__h13080 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req:", v__h13074); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - begin - v__h13265 = $stime; - #0; - end - v__h13259 = v__h13265 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h13259); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - begin - v__h13463 = $stime; - #0; - end - v__h13457 = v__h13463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h13457, - addr_offset__h13216[11:2], - v__h13422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - begin - v__h13713 = $stime; - #0; - end - v__h13707 = v__h13713 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h13707, - source_id_base__h13630, - v__h13671); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - begin - v__h18186 = $stime; - #0; - end - v__h18180 = v__h18186 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h18180, - source_id_base__h13630, - v__h18144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - begin - v__h23802 = $stime; - #0; - end - v__h23796 = v__h23802 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h23796, - addr_offset__h13216[16:12], - v__h23761); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - begin - v__h25975 = $stime; - #0; - end - v__h25969 = v__h25975 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h25969, - addr_offset__h13216[16:12], - v__h25474); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - begin - v__h24056 = $stime; - #0; - end - v__h24050 = v__h24056 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h24050, - addr_offset__h13216[16:12]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Still servicing interrupt from source %0d", x__h24011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Trying to claim service for source %0d", - max_id__h23959); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Ignoring."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - begin - v__h26250 = $stime; - #0; - end - v__h26244 = v__h26250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h26244); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26463 = $stime; - #0; - end - v__h26457 = v__h26463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req", v__h26457); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", x__h26361); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", rresp__h26203); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26740 = $stime; - #0; - end - v__h26734 = v__h26740 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26734); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - begin - v__h26968 = $stime; - #0; - end - v__h26962 = v__h26968 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26962); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - begin - v__h27865 = $stime; - #0; - end - v__h27859 = v__h27865 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27859, - addr_offset__h26929[11:2], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - begin - v__h28048 = $stime; - #0; - end - v__h28042 = v__h28048 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28042, - source_id_base__h28148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - begin - v__h67030 = $stime; - #0; - end - v__h67024 = v__h67030 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67024, - addr_offset__h26929[11:7], - source_id_base__h28148, - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - begin - v__h67318 = $stime; - #0; - end - v__h67312 = v__h67318 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67312, - addr_offset__h26929[16:12], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - begin - v__h67847 = $stime; - #0; - end - v__h67841 = v__h67847 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67841, - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - begin - v__h67933 = $stime; - #0; - end - v__h67927 = v__h67933 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67927); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Completion message from target %0d to source %0d", - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Ignoring"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - begin - v__h68132 = $stime; - #0; - end - v__h68126 = v__h68132 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68126); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h68353 = $stime; - #0; - end - v__h68347 = v__h68353 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68347); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26934); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h74690 = $stime; - #0; - end - v__h74684 = v__h74690 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74684, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h74800 = $stime; - #0; - end - v__h74794 = v__h74800 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74794, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - begin - v__h74913 = $stime; - #0; - end - v__h74907 = v__h74913 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74907, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkPLIC_16_2_7 - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v deleted file mode 100644 index 570d9b06..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v +++ /dev/null @@ -1,663 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_req_reset O 1 const -// RDY_rsp_reset O 1 const -// valid O 1 -// word O 32 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_is_OP_not_OP_32 I 1 reg -// req_f3 I 3 -// req_v1 I 32 -// req_v2 I 32 -// EN_set_verbosity I 1 -// EN_req_reset I 1 unused -// EN_rsp_reset I 1 unused -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkRISCV_MBox(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_req_reset, - RDY_req_reset, - - EN_rsp_reset, - RDY_rsp_reset, - - req_is_OP_not_OP_32, - req_f3, - req_v1, - req_v2, - EN_req, - - valid, - - word); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method req_reset - input EN_req_reset; - output RDY_req_reset; - - // action method rsp_reset - input EN_rsp_reset; - output RDY_rsp_reset; - - // action method req - input req_is_OP_not_OP_32; - input [2 : 0] req_f3; - input [31 : 0] req_v1; - input [31 : 0] req_v2; - input EN_req; - - // value method valid - output valid; - - // value method word - output [31 : 0] word; - - // signals for module outputs - wire [31 : 0] word; - wire RDY_req_reset, RDY_rsp_reset, RDY_set_verbosity, valid; - - // inlined wires - wire dw_valid$whas; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register intDiv_rg_denom2 - reg [31 : 0] intDiv_rg_denom2; - reg [31 : 0] intDiv_rg_denom2$D_IN; - wire intDiv_rg_denom2$EN; - - // register intDiv_rg_denom_is_signed - reg intDiv_rg_denom_is_signed; - wire intDiv_rg_denom_is_signed$D_IN, intDiv_rg_denom_is_signed$EN; - - // register intDiv_rg_n - reg [31 : 0] intDiv_rg_n; - reg [31 : 0] intDiv_rg_n$D_IN; - wire intDiv_rg_n$EN; - - // register intDiv_rg_numer_is_signed - reg intDiv_rg_numer_is_signed; - wire intDiv_rg_numer_is_signed$D_IN, intDiv_rg_numer_is_signed$EN; - - // register intDiv_rg_quo - reg [31 : 0] intDiv_rg_quo; - reg [31 : 0] intDiv_rg_quo$D_IN; - wire intDiv_rg_quo$EN; - - // register intDiv_rg_quoIsNeg - reg intDiv_rg_quoIsNeg; - wire intDiv_rg_quoIsNeg$D_IN, intDiv_rg_quoIsNeg$EN; - - // register intDiv_rg_remIsNeg - reg intDiv_rg_remIsNeg; - wire intDiv_rg_remIsNeg$D_IN, intDiv_rg_remIsNeg$EN; - - // register intDiv_rg_state - reg [2 : 0] intDiv_rg_state; - reg [2 : 0] intDiv_rg_state$D_IN; - wire intDiv_rg_state$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_is_OP_not_OP_32 - reg rg_is_OP_not_OP_32; - wire rg_is_OP_not_OP_32$D_IN, rg_is_OP_not_OP_32$EN; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_v1 - reg [31 : 0] rg_v1; - reg [31 : 0] rg_v1$D_IN; - wire rg_v1$EN; - - // register rg_v2 - reg [31 : 0] rg_v2; - wire [31 : 0] rg_v2$D_IN; - wire rg_v2$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_intDiv_rl_loop1, - CAN_FIRE_RL_intDiv_rl_loop2, - CAN_FIRE_RL_intDiv_rl_start_div_by_zero, - CAN_FIRE_RL_intDiv_rl_start_overflow, - CAN_FIRE_RL_intDiv_rl_start_s, - CAN_FIRE_RL_rg_div_rem, - CAN_FIRE_RL_rl_mul, - CAN_FIRE_RL_rl_mul2, - CAN_FIRE_req, - CAN_FIRE_req_reset, - CAN_FIRE_rsp_reset, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_intDiv_rl_loop1, - WILL_FIRE_RL_intDiv_rl_loop2, - WILL_FIRE_RL_intDiv_rl_start_div_by_zero, - WILL_FIRE_RL_intDiv_rl_start_overflow, - WILL_FIRE_RL_intDiv_rl_start_s, - WILL_FIRE_RL_rg_div_rem, - WILL_FIRE_RL_rl_mul, - WILL_FIRE_RL_rl_mul2, - WILL_FIRE_req, - WILL_FIRE_req_reset, - WILL_FIRE_rsp_reset, - WILL_FIRE_set_verbosity; - - // inputs to muxes for submodule ports - wire [31 : 0] MUX_dw_result$wset_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_1, - MUX_intDiv_rg_denom2$write_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_3, - MUX_intDiv_rg_n$write_1__VAL_1, - MUX_intDiv_rg_n$write_1__VAL_2, - MUX_intDiv_rg_quo$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_2, - MUX_rg_v1$write_1__VAL_3, - MUX_rg_v1$write_1__VAL_4; - wire [1 : 0] MUX_rg_state$write_1__VAL_1; - wire MUX_intDiv_rg_denom2$write_1__SEL_1, - MUX_intDiv_rg_denom2$write_1__SEL_2, - MUX_intDiv_rg_quo$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_2, - MUX_intDiv_rg_state$write_1__SEL_3, - MUX_rg_v1$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h3263; - reg [31 : 0] v__h3257; - // synopsys translate_on - - // remaining internal signals - wire [127 : 0] SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113, - SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105, - _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110; - wire [63 : 0] SEXT_rg_v1____d103, rg_v1_MUL_rg_v2___d100, v1__h3150; - wire [31 : 0] _theResult___fst__h787, - _theResult___snd_fst__h782, - denom___1__h729, - numer___1__h728, - v__h3074, - v__h3132, - v__h3183, - x__h2611, - x__h2697, - x__h2767, - x__h2782, - y__h2490; - wire IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39, - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47, - rg_v1_ULT_intDiv_rg_denom2_4___d59, - rg_v1_ULT_rg_v2___d55; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method req_reset - assign RDY_req_reset = 1'd1 ; - assign CAN_FIRE_req_reset = 1'd1 ; - assign WILL_FIRE_req_reset = EN_req_reset ; - - // action method rsp_reset - assign RDY_rsp_reset = 1'd1 ; - assign CAN_FIRE_rsp_reset = 1'd1 ; - assign WILL_FIRE_rsp_reset = EN_rsp_reset ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method word - assign word = WILL_FIRE_RL_rl_mul2 ? rg_v1 : MUX_dw_result$wset_1__VAL_2 ; - - // rule RL_rl_mul2 - assign CAN_FIRE_RL_rl_mul2 = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_mul2 = CAN_FIRE_RL_rl_mul2 ; - - // rule RL_rg_div_rem - assign CAN_FIRE_RL_rg_div_rem = - rg_state == 2'd2 && intDiv_rg_state == 3'd4 ; - assign WILL_FIRE_RL_rg_div_rem = CAN_FIRE_RL_rg_div_rem ; - - // rule RL_intDiv_rl_start_div_by_zero - assign CAN_FIRE_RL_intDiv_rl_start_div_by_zero = - intDiv_rg_state == 3'd1 && rg_v2 == 32'd0 ; - assign WILL_FIRE_RL_intDiv_rl_start_div_by_zero = - CAN_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // rule RL_intDiv_rl_start_overflow - assign CAN_FIRE_RL_intDiv_rl_start_overflow = - intDiv_rg_state == 3'd1 && intDiv_rg_numer_is_signed && - rg_v1 == 32'h80000000 && - intDiv_rg_denom_is_signed && - rg_v2 == 32'hFFFFFFFF ; - assign WILL_FIRE_RL_intDiv_rl_start_overflow = - CAN_FIRE_RL_intDiv_rl_start_overflow && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_start_s - assign CAN_FIRE_RL_intDiv_rl_start_s = - intDiv_rg_state == 3'd1 && rg_v2 != 32'd0 && - (!intDiv_rg_numer_is_signed || rg_v1 != 32'h80000000 || - !intDiv_rg_denom_is_signed || - rg_v2 != 32'hFFFFFFFF) ; - assign WILL_FIRE_RL_intDiv_rl_start_s = - CAN_FIRE_RL_intDiv_rl_start_s && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_loop1 - assign CAN_FIRE_RL_intDiv_rl_loop1 = intDiv_rg_state == 3'd2 ; - assign WILL_FIRE_RL_intDiv_rl_loop1 = CAN_FIRE_RL_intDiv_rl_loop1 ; - - // rule RL_rl_mul - assign CAN_FIRE_RL_rl_mul = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_mul = rg_state == 2'd0 ; - - // rule RL_intDiv_rl_loop2 - assign CAN_FIRE_RL_intDiv_rl_loop2 = intDiv_rg_state == 3'd3 ; - assign WILL_FIRE_RL_intDiv_rl_loop2 = - CAN_FIRE_RL_intDiv_rl_loop2 && !WILL_FIRE_RL_rl_mul ; - - // inputs to muxes for submodule ports - assign MUX_intDiv_rg_denom2$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 ; - assign MUX_intDiv_rg_denom2$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 ; - assign MUX_intDiv_rg_quo$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_quoIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_intDiv_rg_state$write_1__SEL_1 = EN_req && req_f3[2] ; - assign MUX_intDiv_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 ; - assign MUX_intDiv_rg_state$write_1__SEL_3 = - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 ; - assign MUX_rg_v1$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_remIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_dw_result$wset_1__VAL_2 = rg_f3[1] ? rg_v1 : intDiv_rg_quo ; - assign MUX_intDiv_rg_denom2$write_1__VAL_1 = - { intDiv_rg_denom2[30:0], 1'd0 } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_2 = - { 1'd0, intDiv_rg_denom2[31:1] } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_3 = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - denom___1__h729 : - _theResult___snd_fst__h782 ; - assign MUX_intDiv_rg_n$write_1__VAL_1 = { intDiv_rg_n[30:0], 1'd0 } ; - assign MUX_intDiv_rg_n$write_1__VAL_2 = { 1'd0, intDiv_rg_n[31:1] } ; - assign MUX_intDiv_rg_quo$write_1__VAL_1 = - rg_v1_ULT_rg_v2___d55 ? x__h2697 : x__h2782 ; - assign MUX_rg_state$write_1__VAL_1 = req_f3[2] ? 2'd2 : 2'd0 ; - assign MUX_rg_v1$write_1__VAL_2 = - rg_v1_ULT_rg_v2___d55 ? x__h2767 : x__h2611 ; - assign MUX_rg_v1$write_1__VAL_3 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - rg_v1_MUL_rg_v2___d100[31:0] : - v__h3074 ; - assign MUX_rg_v1$write_1__VAL_4 = - intDiv_rg_numer_is_signed ? numer___1__h728 : rg_v1 ; - - // inlined wires - assign dw_valid$whas = WILL_FIRE_RL_rg_div_rem || WILL_FIRE_RL_rl_mul2 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register intDiv_rg_denom2 - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_denom2$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_denom2$write_1__VAL_2 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_intDiv_rg_denom2$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_3; - default: intDiv_rg_denom2$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_denom2$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_denom_is_signed - assign intDiv_rg_denom_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_denom_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_n - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_n$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_n$write_1__VAL_2 or WILL_FIRE_RL_intDiv_rl_start_s) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_n$D_IN = 32'd1; - default: intDiv_rg_n$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_n$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_numer_is_signed - assign intDiv_rg_numer_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_numer_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_quo - always@(MUX_intDiv_rg_quo$write_1__SEL_1 or - MUX_intDiv_rg_quo$write_1__VAL_1 or - WILL_FIRE_RL_intDiv_rl_start_overflow or - rg_v1 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_quo$write_1__SEL_1: - intDiv_rg_quo$D_IN = MUX_intDiv_rg_quo$write_1__VAL_1; - WILL_FIRE_RL_intDiv_rl_start_overflow: intDiv_rg_quo$D_IN = rg_v1; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_quo$D_IN = 32'd0; - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_quo$D_IN = 32'hFFFFFFFF; - default: intDiv_rg_quo$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_quo$EN = - MUX_intDiv_rg_quo$write_1__SEL_1 || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register intDiv_rg_quoIsNeg - assign intDiv_rg_quoIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[31] != rg_v2[31] : - IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39 ; - assign intDiv_rg_quoIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_remIsNeg - assign intDiv_rg_remIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[31] : - intDiv_rg_numer_is_signed && rg_v1[31] ; - assign intDiv_rg_remIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_state - always@(MUX_intDiv_rg_state$write_1__SEL_1 or - MUX_intDiv_rg_state$write_1__SEL_2 or - MUX_intDiv_rg_state$write_1__SEL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_overflow or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - case (1'b1) - MUX_intDiv_rg_state$write_1__SEL_1: intDiv_rg_state$D_IN = 3'd1; - MUX_intDiv_rg_state$write_1__SEL_2: intDiv_rg_state$D_IN = 3'd4; - MUX_intDiv_rg_state$write_1__SEL_3: intDiv_rg_state$D_IN = 3'd3; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_state$D_IN = 3'd2; - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_state$D_IN = 3'd4; - default: intDiv_rg_state$D_IN = 3'b010 /* unspecified value */ ; - endcase - assign intDiv_rg_state$EN = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 || - EN_req && req_f3[2] || - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_is_OP_not_OP_32 - assign rg_is_OP_not_OP_32$D_IN = req_is_OP_not_OP_32 ; - assign rg_is_OP_not_OP_32$EN = EN_req ; - - // register rg_state - assign rg_state$D_IN = EN_req ? MUX_rg_state$write_1__VAL_1 : 2'd1 ; - assign rg_state$EN = EN_req || WILL_FIRE_RL_rl_mul ; - - // register rg_v1 - always@(EN_req or - req_v1 or - MUX_rg_v1$write_1__SEL_2 or - MUX_rg_v1$write_1__VAL_2 or - WILL_FIRE_RL_rl_mul or - MUX_rg_v1$write_1__VAL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_rg_v1$write_1__VAL_4 or WILL_FIRE_RL_intDiv_rl_start_overflow) - case (1'b1) - EN_req: rg_v1$D_IN = req_v1; - MUX_rg_v1$write_1__SEL_2: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_2; - WILL_FIRE_RL_rl_mul: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_3; - WILL_FIRE_RL_intDiv_rl_start_s: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_4; - WILL_FIRE_RL_intDiv_rl_start_overflow: rg_v1$D_IN = 32'd0; - default: rg_v1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - assign rg_v1$EN = - MUX_rg_v1$write_1__SEL_2 || EN_req || WILL_FIRE_RL_rl_mul || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow ; - - // register rg_v2 - assign rg_v2$D_IN = EN_req ? req_v2 : MUX_intDiv_rg_denom2$write_1__VAL_3 ; - assign rg_v2$EN = EN_req || WILL_FIRE_RL_intDiv_rl_start_s ; - - // remaining internal signals - assign IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39 = - intDiv_rg_numer_is_signed ? - rg_v1[31] : - intDiv_rg_denom_is_signed && rg_v2[31] ; - assign SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113 = - SEXT_rg_v1____d103 * { 32'd0, rg_v2 } ; - assign SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105 = - SEXT_rg_v1____d103 * { {32{rg_v2[31]}}, rg_v2 } ; - assign SEXT_rg_v1____d103 = { {32{rg_v1[31]}}, rg_v1 } ; - assign _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110 = - v1__h3150 * { 32'd0, rg_v2 } ; - assign _theResult___fst__h787 = - intDiv_rg_denom_is_signed ? denom___1__h729 : rg_v2 ; - assign _theResult___snd_fst__h782 = - intDiv_rg_numer_is_signed ? rg_v2 : _theResult___fst__h787 ; - assign denom___1__h729 = rg_v2[31] ? -rg_v2 : rg_v2 ; - assign intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 = - intDiv_rg_denom2 <= y__h2490 ; - assign numer___1__h728 = rg_v1[31] ? x__h2767 : rg_v1 ; - assign rg_v1_MUL_rg_v2___d100 = rg_v1 * rg_v2 ; - assign rg_v1_ULT_intDiv_rg_denom2_4___d59 = rg_v1 < intDiv_rg_denom2 ; - assign rg_v1_ULT_rg_v2___d55 = rg_v1 < rg_v2 ; - assign v1__h3150 = { 32'd0, rg_v1 } ; - assign v__h3074 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b001) ? - SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105[63:32] : - v__h3132 ; - assign v__h3132 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b011) ? - _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110[63:32] : - v__h3183 ; - assign v__h3183 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b010) ? - SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113[63:32] : - 32'hFFFFFFFF ; - assign x__h2611 = rg_v1 - intDiv_rg_denom2 ; - assign x__h2697 = -intDiv_rg_quo ; - assign x__h2767 = -rg_v1 ; - assign x__h2782 = intDiv_rg_quo + intDiv_rg_n ; - assign y__h2490 = { 1'd0, rg_v1[31:1] } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (intDiv_rg_state$EN) - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY intDiv_rg_state$D_IN; - end - if (intDiv_rg_denom2$EN) - intDiv_rg_denom2 <= `BSV_ASSIGNMENT_DELAY intDiv_rg_denom2$D_IN; - if (intDiv_rg_denom_is_signed$EN) - intDiv_rg_denom_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_denom_is_signed$D_IN; - if (intDiv_rg_n$EN) intDiv_rg_n <= `BSV_ASSIGNMENT_DELAY intDiv_rg_n$D_IN; - if (intDiv_rg_numer_is_signed$EN) - intDiv_rg_numer_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_numer_is_signed$D_IN; - if (intDiv_rg_quo$EN) - intDiv_rg_quo <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quo$D_IN; - if (intDiv_rg_quoIsNeg$EN) - intDiv_rg_quoIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quoIsNeg$D_IN; - if (intDiv_rg_remIsNeg$EN) - intDiv_rg_remIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_remIsNeg$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_is_OP_not_OP_32$EN) - rg_is_OP_not_OP_32 <= `BSV_ASSIGNMENT_DELAY rg_is_OP_not_OP_32$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_v1$EN) rg_v1 <= `BSV_ASSIGNMENT_DELAY rg_v1$D_IN; - if (rg_v2$EN) rg_v2 <= `BSV_ASSIGNMENT_DELAY rg_v2$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - intDiv_rg_denom2 = 32'hAAAAAAAA; - intDiv_rg_denom_is_signed = 1'h0; - intDiv_rg_n = 32'hAAAAAAAA; - intDiv_rg_numer_is_signed = 1'h0; - intDiv_rg_quo = 32'hAAAAAAAA; - intDiv_rg_quoIsNeg = 1'h0; - intDiv_rg_remIsNeg = 1'h0; - intDiv_rg_state = 3'h2; - rg_f3 = 3'h2; - rg_is_OP_not_OP_32 = 1'h0; - rg_state = 2'h2; - rg_v1 = 32'hAAAAAAAA; - rg_v2 = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && cfg_verbosity > 4'd1) - $display(" RISCV_MBox.rl_mul"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - begin - v__h3263 = $stime; - #0; - end - v__h3257 = v__h3263 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $display("%0d: ERROR: RISCV_MBox.rl_mul: illegal f3.", v__h3257); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $display(" f3 0x%0h v1 0x%0h v2 0x%0h", rg_f3, rg_v1, rg_v2); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkRISCV_MBox - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v deleted file mode 100644 index c88e21cd..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v +++ /dev/null @@ -1,298 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// m_near_mem_io_addr_base O 64 const -// m_near_mem_io_addr_size O 64 const -// m_near_mem_io_addr_lim O 64 const -// m_plic_addr_base O 64 const -// m_plic_addr_size O 64 const -// m_plic_addr_lim O 64 const -// m_uart0_addr_base O 64 const -// m_uart0_addr_size O 64 const -// m_uart0_addr_lim O 64 const -// m_boot_rom_addr_base O 64 const -// m_boot_rom_addr_size O 64 const -// m_boot_rom_addr_lim O 64 const -// m_mem0_controller_addr_base O 64 const -// m_mem0_controller_addr_size O 64 const -// m_mem0_controller_addr_lim O 64 const -// m_tcm_addr_base O 64 const -// m_tcm_addr_size O 64 const -// m_tcm_addr_lim O 64 const -// m_is_mem_addr O 1 -// m_is_IO_addr O 1 -// m_is_near_mem_IO_addr O 1 -// m_pc_reset_value O 64 const -// m_mtvec_reset_value O 64 const -// m_nmivec_reset_value O 64 const -// CLK I 1 unused -// RST_N I 1 unused -// m_is_mem_addr_addr I 64 -// m_is_IO_addr_addr I 64 -// m_is_near_mem_IO_addr_addr I 64 -// -// Combinational paths from inputs to outputs: -// m_is_mem_addr_addr -> m_is_mem_addr -// m_is_IO_addr_addr -> m_is_IO_addr -// m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Map(CLK, - RST_N, - - m_near_mem_io_addr_base, - - m_near_mem_io_addr_size, - - m_near_mem_io_addr_lim, - - m_plic_addr_base, - - m_plic_addr_size, - - m_plic_addr_lim, - - m_uart0_addr_base, - - m_uart0_addr_size, - - m_uart0_addr_lim, - - m_boot_rom_addr_base, - - m_boot_rom_addr_size, - - m_boot_rom_addr_lim, - - m_mem0_controller_addr_base, - - m_mem0_controller_addr_size, - - m_mem0_controller_addr_lim, - - m_tcm_addr_base, - - m_tcm_addr_size, - - m_tcm_addr_lim, - - m_is_mem_addr_addr, - m_is_mem_addr, - - m_is_IO_addr_addr, - m_is_IO_addr, - - m_is_near_mem_IO_addr_addr, - m_is_near_mem_IO_addr, - - m_pc_reset_value, - - m_mtvec_reset_value, - - m_nmivec_reset_value); - input CLK; - input RST_N; - - // value method m_near_mem_io_addr_base - output [63 : 0] m_near_mem_io_addr_base; - - // value method m_near_mem_io_addr_size - output [63 : 0] m_near_mem_io_addr_size; - - // value method m_near_mem_io_addr_lim - output [63 : 0] m_near_mem_io_addr_lim; - - // value method m_plic_addr_base - output [63 : 0] m_plic_addr_base; - - // value method m_plic_addr_size - output [63 : 0] m_plic_addr_size; - - // value method m_plic_addr_lim - output [63 : 0] m_plic_addr_lim; - - // value method m_uart0_addr_base - output [63 : 0] m_uart0_addr_base; - - // value method m_uart0_addr_size - output [63 : 0] m_uart0_addr_size; - - // value method m_uart0_addr_lim - output [63 : 0] m_uart0_addr_lim; - - // value method m_boot_rom_addr_base - output [63 : 0] m_boot_rom_addr_base; - - // value method m_boot_rom_addr_size - output [63 : 0] m_boot_rom_addr_size; - - // value method m_boot_rom_addr_lim - output [63 : 0] m_boot_rom_addr_lim; - - // value method m_mem0_controller_addr_base - output [63 : 0] m_mem0_controller_addr_base; - - // value method m_mem0_controller_addr_size - output [63 : 0] m_mem0_controller_addr_size; - - // value method m_mem0_controller_addr_lim - output [63 : 0] m_mem0_controller_addr_lim; - - // value method m_tcm_addr_base - output [63 : 0] m_tcm_addr_base; - - // value method m_tcm_addr_size - output [63 : 0] m_tcm_addr_size; - - // value method m_tcm_addr_lim - output [63 : 0] m_tcm_addr_lim; - - // value method m_is_mem_addr - input [63 : 0] m_is_mem_addr_addr; - output m_is_mem_addr; - - // value method m_is_IO_addr - input [63 : 0] m_is_IO_addr_addr; - output m_is_IO_addr; - - // value method m_is_near_mem_IO_addr - input [63 : 0] m_is_near_mem_IO_addr_addr; - output m_is_near_mem_IO_addr; - - // value method m_pc_reset_value - output [63 : 0] m_pc_reset_value; - - // value method m_mtvec_reset_value - output [63 : 0] m_mtvec_reset_value; - - // value method m_nmivec_reset_value - output [63 : 0] m_nmivec_reset_value; - - // signals for module outputs - wire [63 : 0] m_boot_rom_addr_base, - m_boot_rom_addr_lim, - m_boot_rom_addr_size, - m_mem0_controller_addr_base, - m_mem0_controller_addr_lim, - m_mem0_controller_addr_size, - m_mtvec_reset_value, - m_near_mem_io_addr_base, - m_near_mem_io_addr_lim, - m_near_mem_io_addr_size, - m_nmivec_reset_value, - m_pc_reset_value, - m_plic_addr_base, - m_plic_addr_lim, - m_plic_addr_size, - m_tcm_addr_base, - m_tcm_addr_lim, - m_tcm_addr_size, - m_uart0_addr_base, - m_uart0_addr_lim, - m_uart0_addr_size; - wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; - - // value method m_near_mem_io_addr_base - assign m_near_mem_io_addr_base = 64'h0000000002000000 ; - - // value method m_near_mem_io_addr_size - assign m_near_mem_io_addr_size = 64'h000000000000C000 ; - - // value method m_near_mem_io_addr_lim - assign m_near_mem_io_addr_lim = 64'd33603584 ; - - // value method m_plic_addr_base - assign m_plic_addr_base = 64'h000000000C000000 ; - - // value method m_plic_addr_size - assign m_plic_addr_size = 64'h0000000000400000 ; - - // value method m_plic_addr_lim - assign m_plic_addr_lim = 64'd205520896 ; - - // value method m_uart0_addr_base - assign m_uart0_addr_base = 64'h00000000C0000000 ; - - // value method m_uart0_addr_size - assign m_uart0_addr_size = 64'h0000000000000080 ; - - // value method m_uart0_addr_lim - assign m_uart0_addr_lim = 64'h00000000C0000080 ; - - // value method m_boot_rom_addr_base - assign m_boot_rom_addr_base = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_size - assign m_boot_rom_addr_size = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_lim - assign m_boot_rom_addr_lim = 64'd8192 ; - - // value method m_mem0_controller_addr_base - assign m_mem0_controller_addr_base = 64'h0000000080000000 ; - - // value method m_mem0_controller_addr_size - assign m_mem0_controller_addr_size = 64'h0000000010000000 ; - - // value method m_mem0_controller_addr_lim - assign m_mem0_controller_addr_lim = 64'h0000000090000000 ; - - // value method m_tcm_addr_base - assign m_tcm_addr_base = 64'h0 ; - - // value method m_tcm_addr_size - assign m_tcm_addr_size = 64'd0 ; - - // value method m_tcm_addr_lim - assign m_tcm_addr_lim = 64'd0 ; - - // value method m_is_mem_addr - assign m_is_mem_addr = - m_is_mem_addr_addr >= 64'h0000000000001000 && - m_is_mem_addr_addr < 64'd8192 || - m_is_mem_addr_addr >= 64'h0000000080000000 && - m_is_mem_addr_addr < 64'h0000000090000000 ; - - // value method m_is_IO_addr - assign m_is_IO_addr = - m_is_IO_addr_addr >= 64'h0000000002000000 && - m_is_IO_addr_addr < 64'd33603584 || - m_is_IO_addr_addr >= 64'h000000000C000000 && - m_is_IO_addr_addr < 64'd205520896 || - m_is_IO_addr_addr >= 64'h00000000C0000000 && - m_is_IO_addr_addr < 64'h00000000C0000080 ; - - // value method m_is_near_mem_IO_addr - assign m_is_near_mem_IO_addr = - m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 && - m_is_near_mem_IO_addr_addr < 64'd33603584 ; - - // value method m_pc_reset_value - assign m_pc_reset_value = 64'h0000000000001000 ; - - // value method m_mtvec_reset_value - assign m_mtvec_reset_value = 64'h0000000000001000 ; - - // value method m_nmivec_reset_value - assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ; -endmodule // mkSoC_Map - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v deleted file mode 100644 index 42e03763..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v +++ /dev/null @@ -1,2333 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// to_raw_mem_response_put I 256 -// put_from_console_put I 8 reg -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_set_verbosity I 1 -// EN_to_raw_mem_response_put I 1 -// EN_put_from_console_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Top(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [7 : 0] get_to_console_get, status; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_set_verbosity, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule boot_rom - wire [63 : 0] boot_rom$set_addr_map_addr_base, - boot_rom$set_addr_map_addr_lim, - boot_rom$slave_araddr, - boot_rom$slave_awaddr, - boot_rom$slave_rdata, - boot_rom$slave_wdata; - wire [7 : 0] boot_rom$slave_arlen, - boot_rom$slave_awlen, - boot_rom$slave_wstrb; - wire [3 : 0] boot_rom$slave_arcache, - boot_rom$slave_arid, - boot_rom$slave_arqos, - boot_rom$slave_arregion, - boot_rom$slave_awcache, - boot_rom$slave_awid, - boot_rom$slave_awqos, - boot_rom$slave_awregion, - boot_rom$slave_bid, - boot_rom$slave_rid, - boot_rom$slave_wid; - wire [2 : 0] boot_rom$slave_arprot, - boot_rom$slave_arsize, - boot_rom$slave_awprot, - boot_rom$slave_awsize; - wire [1 : 0] boot_rom$slave_arburst, - boot_rom$slave_awburst, - boot_rom$slave_bresp, - boot_rom$slave_rresp; - wire boot_rom$EN_set_addr_map, - boot_rom$slave_arlock, - boot_rom$slave_arready, - boot_rom$slave_arvalid, - boot_rom$slave_awlock, - boot_rom$slave_awready, - boot_rom$slave_awvalid, - boot_rom$slave_bready, - boot_rom$slave_bvalid, - boot_rom$slave_rlast, - boot_rom$slave_rready, - boot_rom$slave_rvalid, - boot_rom$slave_wlast, - boot_rom$slave_wready, - boot_rom$slave_wvalid; - - // ports of submodule boot_rom_axi4_deburster - wire [63 : 0] boot_rom_axi4_deburster$from_master_araddr, - boot_rom_axi4_deburster$from_master_awaddr, - boot_rom_axi4_deburster$from_master_rdata, - boot_rom_axi4_deburster$from_master_wdata, - boot_rom_axi4_deburster$to_slave_araddr, - boot_rom_axi4_deburster$to_slave_awaddr, - boot_rom_axi4_deburster$to_slave_rdata, - boot_rom_axi4_deburster$to_slave_wdata; - wire [7 : 0] boot_rom_axi4_deburster$from_master_arlen, - boot_rom_axi4_deburster$from_master_awlen, - boot_rom_axi4_deburster$from_master_wstrb, - boot_rom_axi4_deburster$to_slave_arlen, - boot_rom_axi4_deburster$to_slave_awlen, - boot_rom_axi4_deburster$to_slave_wstrb; - wire [3 : 0] boot_rom_axi4_deburster$from_master_arcache, - boot_rom_axi4_deburster$from_master_arid, - boot_rom_axi4_deburster$from_master_arqos, - boot_rom_axi4_deburster$from_master_arregion, - boot_rom_axi4_deburster$from_master_awcache, - boot_rom_axi4_deburster$from_master_awid, - boot_rom_axi4_deburster$from_master_awqos, - boot_rom_axi4_deburster$from_master_awregion, - boot_rom_axi4_deburster$from_master_bid, - boot_rom_axi4_deburster$from_master_rid, - boot_rom_axi4_deburster$from_master_wid, - boot_rom_axi4_deburster$to_slave_arcache, - boot_rom_axi4_deburster$to_slave_arid, - boot_rom_axi4_deburster$to_slave_arqos, - boot_rom_axi4_deburster$to_slave_arregion, - boot_rom_axi4_deburster$to_slave_awcache, - boot_rom_axi4_deburster$to_slave_awid, - boot_rom_axi4_deburster$to_slave_awqos, - boot_rom_axi4_deburster$to_slave_awregion, - boot_rom_axi4_deburster$to_slave_bid, - boot_rom_axi4_deburster$to_slave_rid, - boot_rom_axi4_deburster$to_slave_wid; - wire [2 : 0] boot_rom_axi4_deburster$from_master_arprot, - boot_rom_axi4_deburster$from_master_arsize, - boot_rom_axi4_deburster$from_master_awprot, - boot_rom_axi4_deburster$from_master_awsize, - boot_rom_axi4_deburster$to_slave_arprot, - boot_rom_axi4_deburster$to_slave_arsize, - boot_rom_axi4_deburster$to_slave_awprot, - boot_rom_axi4_deburster$to_slave_awsize; - wire [1 : 0] boot_rom_axi4_deburster$from_master_arburst, - boot_rom_axi4_deburster$from_master_awburst, - boot_rom_axi4_deburster$from_master_bresp, - boot_rom_axi4_deburster$from_master_rresp, - boot_rom_axi4_deburster$to_slave_arburst, - boot_rom_axi4_deburster$to_slave_awburst, - boot_rom_axi4_deburster$to_slave_bresp, - boot_rom_axi4_deburster$to_slave_rresp; - wire boot_rom_axi4_deburster$EN_reset, - boot_rom_axi4_deburster$from_master_arlock, - boot_rom_axi4_deburster$from_master_arready, - boot_rom_axi4_deburster$from_master_arvalid, - boot_rom_axi4_deburster$from_master_awlock, - boot_rom_axi4_deburster$from_master_awready, - boot_rom_axi4_deburster$from_master_awvalid, - boot_rom_axi4_deburster$from_master_bready, - boot_rom_axi4_deburster$from_master_bvalid, - boot_rom_axi4_deburster$from_master_rlast, - boot_rom_axi4_deburster$from_master_rready, - boot_rom_axi4_deburster$from_master_rvalid, - boot_rom_axi4_deburster$from_master_wlast, - boot_rom_axi4_deburster$from_master_wready, - boot_rom_axi4_deburster$from_master_wvalid, - boot_rom_axi4_deburster$to_slave_arlock, - boot_rom_axi4_deburster$to_slave_arready, - boot_rom_axi4_deburster$to_slave_arvalid, - boot_rom_axi4_deburster$to_slave_awlock, - boot_rom_axi4_deburster$to_slave_awready, - boot_rom_axi4_deburster$to_slave_awvalid, - boot_rom_axi4_deburster$to_slave_bready, - boot_rom_axi4_deburster$to_slave_bvalid, - boot_rom_axi4_deburster$to_slave_rlast, - boot_rom_axi4_deburster$to_slave_rready, - boot_rom_axi4_deburster$to_slave_rvalid, - boot_rom_axi4_deburster$to_slave_wlast, - boot_rom_axi4_deburster$to_slave_wready, - boot_rom_axi4_deburster$to_slave_wvalid; - - // ports of submodule core - wire [63 : 0] core$cpu_dmem_master_araddr, - core$cpu_dmem_master_awaddr, - core$cpu_dmem_master_rdata, - core$cpu_dmem_master_wdata, - core$cpu_imem_master_araddr, - core$cpu_imem_master_awaddr, - core$cpu_imem_master_rdata, - core$cpu_imem_master_wdata, - core$set_verbosity_logdelay; - wire [7 : 0] core$cpu_dmem_master_arlen, - core$cpu_dmem_master_awlen, - core$cpu_dmem_master_wstrb, - core$cpu_imem_master_arlen, - core$cpu_imem_master_awlen, - core$cpu_imem_master_wstrb; - wire [3 : 0] core$cpu_dmem_master_arcache, - core$cpu_dmem_master_arid, - core$cpu_dmem_master_arqos, - core$cpu_dmem_master_arregion, - core$cpu_dmem_master_awcache, - core$cpu_dmem_master_awid, - core$cpu_dmem_master_awqos, - core$cpu_dmem_master_awregion, - core$cpu_dmem_master_bid, - core$cpu_dmem_master_rid, - core$cpu_dmem_master_wid, - core$cpu_imem_master_arcache, - core$cpu_imem_master_arid, - core$cpu_imem_master_arqos, - core$cpu_imem_master_arregion, - core$cpu_imem_master_awcache, - core$cpu_imem_master_awid, - core$cpu_imem_master_awqos, - core$cpu_imem_master_awregion, - core$cpu_imem_master_bid, - core$cpu_imem_master_rid, - core$cpu_imem_master_wid, - core$set_verbosity_verbosity; - wire [2 : 0] core$cpu_dmem_master_arprot, - core$cpu_dmem_master_arsize, - core$cpu_dmem_master_awprot, - core$cpu_dmem_master_awsize, - core$cpu_imem_master_arprot, - core$cpu_imem_master_arsize, - core$cpu_imem_master_awprot, - core$cpu_imem_master_awsize; - wire [1 : 0] core$cpu_dmem_master_arburst, - core$cpu_dmem_master_awburst, - core$cpu_dmem_master_bresp, - core$cpu_dmem_master_rresp, - core$cpu_imem_master_arburst, - core$cpu_imem_master_awburst, - core$cpu_imem_master_bresp, - core$cpu_imem_master_rresp; - wire core$EN_cpu_reset_server_request_put, - core$EN_cpu_reset_server_response_get, - core$EN_set_verbosity, - core$RDY_cpu_reset_server_request_put, - core$RDY_cpu_reset_server_response_get, - core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - core$cpu_dmem_master_arlock, - core$cpu_dmem_master_arready, - core$cpu_dmem_master_arvalid, - core$cpu_dmem_master_awlock, - core$cpu_dmem_master_awready, - core$cpu_dmem_master_awvalid, - core$cpu_dmem_master_bready, - core$cpu_dmem_master_bvalid, - core$cpu_dmem_master_rlast, - core$cpu_dmem_master_rready, - core$cpu_dmem_master_rvalid, - core$cpu_dmem_master_wlast, - core$cpu_dmem_master_wready, - core$cpu_dmem_master_wvalid, - core$cpu_imem_master_arlock, - core$cpu_imem_master_arready, - core$cpu_imem_master_arvalid, - core$cpu_imem_master_awlock, - core$cpu_imem_master_awready, - core$cpu_imem_master_awvalid, - core$cpu_imem_master_bready, - core$cpu_imem_master_bvalid, - core$cpu_imem_master_rlast, - core$cpu_imem_master_rready, - core$cpu_imem_master_rvalid, - core$cpu_imem_master_wlast, - core$cpu_imem_master_wready, - core$cpu_imem_master_wvalid, - core$cpu_reset_server_request_put, - core$nmi_req_set_not_clear; - - // ports of submodule fabric - wire [63 : 0] fabric$v_from_masters_0_araddr, - fabric$v_from_masters_0_awaddr, - fabric$v_from_masters_0_rdata, - fabric$v_from_masters_0_wdata, - fabric$v_from_masters_1_araddr, - fabric$v_from_masters_1_awaddr, - fabric$v_from_masters_1_rdata, - fabric$v_from_masters_1_wdata, - fabric$v_to_slaves_0_araddr, - fabric$v_to_slaves_0_awaddr, - fabric$v_to_slaves_0_rdata, - fabric$v_to_slaves_0_wdata, - fabric$v_to_slaves_1_araddr, - fabric$v_to_slaves_1_awaddr, - fabric$v_to_slaves_1_rdata, - fabric$v_to_slaves_1_wdata, - fabric$v_to_slaves_2_araddr, - fabric$v_to_slaves_2_awaddr, - fabric$v_to_slaves_2_rdata, - fabric$v_to_slaves_2_wdata; - wire [7 : 0] fabric$v_from_masters_0_arlen, - fabric$v_from_masters_0_awlen, - fabric$v_from_masters_0_wstrb, - fabric$v_from_masters_1_arlen, - fabric$v_from_masters_1_awlen, - fabric$v_from_masters_1_wstrb, - fabric$v_to_slaves_0_arlen, - fabric$v_to_slaves_0_awlen, - fabric$v_to_slaves_0_wstrb, - fabric$v_to_slaves_1_arlen, - fabric$v_to_slaves_1_awlen, - fabric$v_to_slaves_1_wstrb, - fabric$v_to_slaves_2_arlen, - fabric$v_to_slaves_2_awlen, - fabric$v_to_slaves_2_wstrb; - wire [3 : 0] fabric$set_verbosity_verbosity, - fabric$v_from_masters_0_arcache, - fabric$v_from_masters_0_arid, - fabric$v_from_masters_0_arqos, - fabric$v_from_masters_0_arregion, - fabric$v_from_masters_0_awcache, - fabric$v_from_masters_0_awid, - fabric$v_from_masters_0_awqos, - fabric$v_from_masters_0_awregion, - fabric$v_from_masters_0_bid, - fabric$v_from_masters_0_rid, - fabric$v_from_masters_0_wid, - fabric$v_from_masters_1_arcache, - fabric$v_from_masters_1_arid, - fabric$v_from_masters_1_arqos, - fabric$v_from_masters_1_arregion, - fabric$v_from_masters_1_awcache, - fabric$v_from_masters_1_awid, - fabric$v_from_masters_1_awqos, - fabric$v_from_masters_1_awregion, - fabric$v_from_masters_1_bid, - fabric$v_from_masters_1_rid, - fabric$v_from_masters_1_wid, - fabric$v_to_slaves_0_arcache, - fabric$v_to_slaves_0_arid, - fabric$v_to_slaves_0_arqos, - fabric$v_to_slaves_0_arregion, - fabric$v_to_slaves_0_awcache, - fabric$v_to_slaves_0_awid, - fabric$v_to_slaves_0_awqos, - fabric$v_to_slaves_0_awregion, - fabric$v_to_slaves_0_bid, - fabric$v_to_slaves_0_rid, - fabric$v_to_slaves_0_wid, - fabric$v_to_slaves_1_arcache, - fabric$v_to_slaves_1_arid, - fabric$v_to_slaves_1_arqos, - fabric$v_to_slaves_1_arregion, - fabric$v_to_slaves_1_awcache, - fabric$v_to_slaves_1_awid, - fabric$v_to_slaves_1_awqos, - fabric$v_to_slaves_1_awregion, - fabric$v_to_slaves_1_bid, - fabric$v_to_slaves_1_rid, - fabric$v_to_slaves_1_wid, - fabric$v_to_slaves_2_arcache, - fabric$v_to_slaves_2_arid, - fabric$v_to_slaves_2_arqos, - fabric$v_to_slaves_2_arregion, - fabric$v_to_slaves_2_awcache, - fabric$v_to_slaves_2_awid, - fabric$v_to_slaves_2_awqos, - fabric$v_to_slaves_2_awregion, - fabric$v_to_slaves_2_bid, - fabric$v_to_slaves_2_rid, - fabric$v_to_slaves_2_wid; - wire [2 : 0] fabric$v_from_masters_0_arprot, - fabric$v_from_masters_0_arsize, - fabric$v_from_masters_0_awprot, - fabric$v_from_masters_0_awsize, - fabric$v_from_masters_1_arprot, - fabric$v_from_masters_1_arsize, - fabric$v_from_masters_1_awprot, - fabric$v_from_masters_1_awsize, - fabric$v_to_slaves_0_arprot, - fabric$v_to_slaves_0_arsize, - fabric$v_to_slaves_0_awprot, - fabric$v_to_slaves_0_awsize, - fabric$v_to_slaves_1_arprot, - fabric$v_to_slaves_1_arsize, - fabric$v_to_slaves_1_awprot, - fabric$v_to_slaves_1_awsize, - fabric$v_to_slaves_2_arprot, - fabric$v_to_slaves_2_arsize, - fabric$v_to_slaves_2_awprot, - fabric$v_to_slaves_2_awsize; - wire [1 : 0] fabric$v_from_masters_0_arburst, - fabric$v_from_masters_0_awburst, - fabric$v_from_masters_0_bresp, - fabric$v_from_masters_0_rresp, - fabric$v_from_masters_1_arburst, - fabric$v_from_masters_1_awburst, - fabric$v_from_masters_1_bresp, - fabric$v_from_masters_1_rresp, - fabric$v_to_slaves_0_arburst, - fabric$v_to_slaves_0_awburst, - fabric$v_to_slaves_0_bresp, - fabric$v_to_slaves_0_rresp, - fabric$v_to_slaves_1_arburst, - fabric$v_to_slaves_1_awburst, - fabric$v_to_slaves_1_bresp, - fabric$v_to_slaves_1_rresp, - fabric$v_to_slaves_2_arburst, - fabric$v_to_slaves_2_awburst, - fabric$v_to_slaves_2_bresp, - fabric$v_to_slaves_2_rresp; - wire fabric$EN_reset, - fabric$EN_set_verbosity, - fabric$RDY_reset, - fabric$v_from_masters_0_arlock, - fabric$v_from_masters_0_arready, - fabric$v_from_masters_0_arvalid, - fabric$v_from_masters_0_awlock, - fabric$v_from_masters_0_awready, - fabric$v_from_masters_0_awvalid, - fabric$v_from_masters_0_bready, - fabric$v_from_masters_0_bvalid, - fabric$v_from_masters_0_rlast, - fabric$v_from_masters_0_rready, - fabric$v_from_masters_0_rvalid, - fabric$v_from_masters_0_wlast, - fabric$v_from_masters_0_wready, - fabric$v_from_masters_0_wvalid, - fabric$v_from_masters_1_arlock, - fabric$v_from_masters_1_arready, - fabric$v_from_masters_1_arvalid, - fabric$v_from_masters_1_awlock, - fabric$v_from_masters_1_awready, - fabric$v_from_masters_1_awvalid, - fabric$v_from_masters_1_bready, - fabric$v_from_masters_1_bvalid, - fabric$v_from_masters_1_rlast, - fabric$v_from_masters_1_rready, - fabric$v_from_masters_1_rvalid, - fabric$v_from_masters_1_wlast, - fabric$v_from_masters_1_wready, - fabric$v_from_masters_1_wvalid, - fabric$v_to_slaves_0_arlock, - fabric$v_to_slaves_0_arready, - fabric$v_to_slaves_0_arvalid, - fabric$v_to_slaves_0_awlock, - fabric$v_to_slaves_0_awready, - fabric$v_to_slaves_0_awvalid, - fabric$v_to_slaves_0_bready, - fabric$v_to_slaves_0_bvalid, - fabric$v_to_slaves_0_rlast, - fabric$v_to_slaves_0_rready, - fabric$v_to_slaves_0_rvalid, - fabric$v_to_slaves_0_wlast, - fabric$v_to_slaves_0_wready, - fabric$v_to_slaves_0_wvalid, - fabric$v_to_slaves_1_arlock, - fabric$v_to_slaves_1_arready, - fabric$v_to_slaves_1_arvalid, - fabric$v_to_slaves_1_awlock, - fabric$v_to_slaves_1_awready, - fabric$v_to_slaves_1_awvalid, - fabric$v_to_slaves_1_bready, - fabric$v_to_slaves_1_bvalid, - fabric$v_to_slaves_1_rlast, - fabric$v_to_slaves_1_rready, - fabric$v_to_slaves_1_rvalid, - fabric$v_to_slaves_1_wlast, - fabric$v_to_slaves_1_wready, - fabric$v_to_slaves_1_wvalid, - fabric$v_to_slaves_2_arlock, - fabric$v_to_slaves_2_arready, - fabric$v_to_slaves_2_arvalid, - fabric$v_to_slaves_2_awlock, - fabric$v_to_slaves_2_awready, - fabric$v_to_slaves_2_awvalid, - fabric$v_to_slaves_2_bready, - fabric$v_to_slaves_2_bvalid, - fabric$v_to_slaves_2_rlast, - fabric$v_to_slaves_2_rready, - fabric$v_to_slaves_2_rvalid, - fabric$v_to_slaves_2_wlast, - fabric$v_to_slaves_2_wready, - fabric$v_to_slaves_2_wvalid; - - // ports of submodule mem0_controller - wire [352 : 0] mem0_controller$to_raw_mem_request_get; - wire [255 : 0] mem0_controller$to_raw_mem_response_put; - wire [63 : 0] mem0_controller$set_addr_map_addr_base, - mem0_controller$set_addr_map_addr_lim, - mem0_controller$set_watch_tohost_tohost_addr, - mem0_controller$slave_araddr, - mem0_controller$slave_awaddr, - mem0_controller$slave_rdata, - mem0_controller$slave_wdata; - wire [7 : 0] mem0_controller$slave_arlen, - mem0_controller$slave_awlen, - mem0_controller$slave_wstrb, - mem0_controller$status; - wire [3 : 0] mem0_controller$slave_arcache, - mem0_controller$slave_arid, - mem0_controller$slave_arqos, - mem0_controller$slave_arregion, - mem0_controller$slave_awcache, - mem0_controller$slave_awid, - mem0_controller$slave_awqos, - mem0_controller$slave_awregion, - mem0_controller$slave_bid, - mem0_controller$slave_rid, - mem0_controller$slave_wid; - wire [2 : 0] mem0_controller$slave_arprot, - mem0_controller$slave_arsize, - mem0_controller$slave_awprot, - mem0_controller$slave_awsize; - wire [1 : 0] mem0_controller$slave_arburst, - mem0_controller$slave_awburst, - mem0_controller$slave_bresp, - mem0_controller$slave_rresp; - wire mem0_controller$EN_server_reset_request_put, - mem0_controller$EN_server_reset_response_get, - mem0_controller$EN_set_addr_map, - mem0_controller$EN_set_watch_tohost, - mem0_controller$EN_to_raw_mem_request_get, - mem0_controller$EN_to_raw_mem_response_put, - mem0_controller$RDY_server_reset_request_put, - mem0_controller$RDY_server_reset_response_get, - mem0_controller$RDY_set_addr_map, - mem0_controller$RDY_to_raw_mem_request_get, - mem0_controller$RDY_to_raw_mem_response_put, - mem0_controller$set_watch_tohost_watch_tohost, - mem0_controller$slave_arlock, - mem0_controller$slave_arready, - mem0_controller$slave_arvalid, - mem0_controller$slave_awlock, - mem0_controller$slave_awready, - mem0_controller$slave_awvalid, - mem0_controller$slave_bready, - mem0_controller$slave_bvalid, - mem0_controller$slave_rlast, - mem0_controller$slave_rready, - mem0_controller$slave_rvalid, - mem0_controller$slave_wlast, - mem0_controller$slave_wready, - mem0_controller$slave_wvalid; - - // ports of submodule mem0_controller_axi4_deburster - wire [63 : 0] mem0_controller_axi4_deburster$from_master_araddr, - mem0_controller_axi4_deburster$from_master_awaddr, - mem0_controller_axi4_deburster$from_master_rdata, - mem0_controller_axi4_deburster$from_master_wdata, - mem0_controller_axi4_deburster$to_slave_araddr, - mem0_controller_axi4_deburster$to_slave_awaddr, - mem0_controller_axi4_deburster$to_slave_rdata, - mem0_controller_axi4_deburster$to_slave_wdata; - wire [7 : 0] mem0_controller_axi4_deburster$from_master_arlen, - mem0_controller_axi4_deburster$from_master_awlen, - mem0_controller_axi4_deburster$from_master_wstrb, - mem0_controller_axi4_deburster$to_slave_arlen, - mem0_controller_axi4_deburster$to_slave_awlen, - mem0_controller_axi4_deburster$to_slave_wstrb; - wire [3 : 0] mem0_controller_axi4_deburster$from_master_arcache, - mem0_controller_axi4_deburster$from_master_arid, - mem0_controller_axi4_deburster$from_master_arqos, - mem0_controller_axi4_deburster$from_master_arregion, - mem0_controller_axi4_deburster$from_master_awcache, - mem0_controller_axi4_deburster$from_master_awid, - mem0_controller_axi4_deburster$from_master_awqos, - mem0_controller_axi4_deburster$from_master_awregion, - mem0_controller_axi4_deburster$from_master_bid, - mem0_controller_axi4_deburster$from_master_rid, - mem0_controller_axi4_deburster$from_master_wid, - mem0_controller_axi4_deburster$to_slave_arcache, - mem0_controller_axi4_deburster$to_slave_arid, - mem0_controller_axi4_deburster$to_slave_arqos, - mem0_controller_axi4_deburster$to_slave_arregion, - mem0_controller_axi4_deburster$to_slave_awcache, - mem0_controller_axi4_deburster$to_slave_awid, - mem0_controller_axi4_deburster$to_slave_awqos, - mem0_controller_axi4_deburster$to_slave_awregion, - mem0_controller_axi4_deburster$to_slave_bid, - mem0_controller_axi4_deburster$to_slave_rid, - mem0_controller_axi4_deburster$to_slave_wid; - wire [2 : 0] mem0_controller_axi4_deburster$from_master_arprot, - mem0_controller_axi4_deburster$from_master_arsize, - mem0_controller_axi4_deburster$from_master_awprot, - mem0_controller_axi4_deburster$from_master_awsize, - mem0_controller_axi4_deburster$to_slave_arprot, - mem0_controller_axi4_deburster$to_slave_arsize, - mem0_controller_axi4_deburster$to_slave_awprot, - mem0_controller_axi4_deburster$to_slave_awsize; - wire [1 : 0] mem0_controller_axi4_deburster$from_master_arburst, - mem0_controller_axi4_deburster$from_master_awburst, - mem0_controller_axi4_deburster$from_master_bresp, - mem0_controller_axi4_deburster$from_master_rresp, - mem0_controller_axi4_deburster$to_slave_arburst, - mem0_controller_axi4_deburster$to_slave_awburst, - mem0_controller_axi4_deburster$to_slave_bresp, - mem0_controller_axi4_deburster$to_slave_rresp; - wire mem0_controller_axi4_deburster$EN_reset, - mem0_controller_axi4_deburster$from_master_arlock, - mem0_controller_axi4_deburster$from_master_arready, - mem0_controller_axi4_deburster$from_master_arvalid, - mem0_controller_axi4_deburster$from_master_awlock, - mem0_controller_axi4_deburster$from_master_awready, - mem0_controller_axi4_deburster$from_master_awvalid, - mem0_controller_axi4_deburster$from_master_bready, - mem0_controller_axi4_deburster$from_master_bvalid, - mem0_controller_axi4_deburster$from_master_rlast, - mem0_controller_axi4_deburster$from_master_rready, - mem0_controller_axi4_deburster$from_master_rvalid, - mem0_controller_axi4_deburster$from_master_wlast, - mem0_controller_axi4_deburster$from_master_wready, - mem0_controller_axi4_deburster$from_master_wvalid, - mem0_controller_axi4_deburster$to_slave_arlock, - mem0_controller_axi4_deburster$to_slave_arready, - mem0_controller_axi4_deburster$to_slave_arvalid, - mem0_controller_axi4_deburster$to_slave_awlock, - mem0_controller_axi4_deburster$to_slave_awready, - mem0_controller_axi4_deburster$to_slave_awvalid, - mem0_controller_axi4_deburster$to_slave_bready, - mem0_controller_axi4_deburster$to_slave_bvalid, - mem0_controller_axi4_deburster$to_slave_rlast, - mem0_controller_axi4_deburster$to_slave_rready, - mem0_controller_axi4_deburster$to_slave_rvalid, - mem0_controller_axi4_deburster$to_slave_wlast, - mem0_controller_axi4_deburster$to_slave_wready, - mem0_controller_axi4_deburster$to_slave_wvalid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // ports of submodule uart0 - wire [63 : 0] uart0$set_addr_map_addr_base, - uart0$set_addr_map_addr_lim, - uart0$slave_araddr, - uart0$slave_awaddr, - uart0$slave_rdata, - uart0$slave_wdata; - wire [7 : 0] uart0$get_to_console_get, - uart0$put_from_console_put, - uart0$slave_arlen, - uart0$slave_awlen, - uart0$slave_wstrb; - wire [3 : 0] uart0$slave_arcache, - uart0$slave_arid, - uart0$slave_arqos, - uart0$slave_arregion, - uart0$slave_awcache, - uart0$slave_awid, - uart0$slave_awqos, - uart0$slave_awregion, - uart0$slave_bid, - uart0$slave_rid, - uart0$slave_wid; - wire [2 : 0] uart0$slave_arprot, - uart0$slave_arsize, - uart0$slave_awprot, - uart0$slave_awsize; - wire [1 : 0] uart0$slave_arburst, - uart0$slave_awburst, - uart0$slave_bresp, - uart0$slave_rresp; - wire uart0$EN_get_to_console_get, - uart0$EN_put_from_console_put, - uart0$EN_server_reset_request_put, - uart0$EN_server_reset_response_get, - uart0$EN_set_addr_map, - uart0$RDY_get_to_console_get, - uart0$RDY_put_from_console_put, - uart0$RDY_server_reset_request_put, - uart0$RDY_server_reset_response_get, - uart0$intr, - uart0$slave_arlock, - uart0$slave_arready, - uart0$slave_arvalid, - uart0$slave_awlock, - uart0$slave_awready, - uart0$slave_awvalid, - uart0$slave_bready, - uart0$slave_bvalid, - uart0$slave_rlast, - uart0$slave_rready, - uart0$slave_rvalid, - uart0$slave_wlast, - uart0$slave_wready, - uart0$slave_wvalid; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_connect_external_interrupt_requests, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_addr_channel_5, - CAN_FIRE_RL_rl_rd_addr_channel_6, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, - CAN_FIRE_RL_rl_rd_data_channel_5, - CAN_FIRE_RL_rl_rd_data_channel_6, - CAN_FIRE_RL_rl_reset_complete_initial, - CAN_FIRE_RL_rl_reset_start_initial, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_addr_channel_5, - CAN_FIRE_RL_rl_wr_addr_channel_6, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_data_channel_5, - CAN_FIRE_RL_rl_wr_data_channel_6, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, - CAN_FIRE_RL_rl_wr_response_channel_5, - CAN_FIRE_RL_rl_wr_response_channel_6, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_set_verbosity, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_connect_external_interrupt_requests, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_addr_channel_5, - WILL_FIRE_RL_rl_rd_addr_channel_6, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, - WILL_FIRE_RL_rl_rd_data_channel_5, - WILL_FIRE_RL_rl_rd_data_channel_6, - WILL_FIRE_RL_rl_reset_complete_initial, - WILL_FIRE_RL_rl_reset_start_initial, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_addr_channel_5, - WILL_FIRE_RL_rl_wr_addr_channel_6, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_data_channel_5, - WILL_FIRE_RL_rl_wr_data_channel_6, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, - WILL_FIRE_RL_rl_wr_response_channel_5, - WILL_FIRE_RL_rl_wr_response_channel_6, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_set_verbosity, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h11286; - reg [31 : 0] v__h11556; - reg [31 : 0] v__h11280; - reg [31 : 0] v__h11550; - // synopsys translate_on - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = mem0_controller$to_raw_mem_request_get ; - assign RDY_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign CAN_FIRE_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign CAN_FIRE_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // actionvalue method get_to_console_get - assign get_to_console_get = uart0$get_to_console_get ; - assign RDY_get_to_console_get = uart0$RDY_get_to_console_get ; - assign CAN_FIRE_get_to_console_get = uart0$RDY_get_to_console_get ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = uart0$RDY_put_from_console_put ; - assign CAN_FIRE_put_from_console_put = uart0$RDY_put_from_console_put ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method status - assign status = mem0_controller$status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule boot_rom - mkBoot_ROM boot_rom(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(boot_rom$set_addr_map_addr_base), - .set_addr_map_addr_lim(boot_rom$set_addr_map_addr_lim), - .slave_araddr(boot_rom$slave_araddr), - .slave_arburst(boot_rom$slave_arburst), - .slave_arcache(boot_rom$slave_arcache), - .slave_arid(boot_rom$slave_arid), - .slave_arlen(boot_rom$slave_arlen), - .slave_arlock(boot_rom$slave_arlock), - .slave_arprot(boot_rom$slave_arprot), - .slave_arqos(boot_rom$slave_arqos), - .slave_arregion(boot_rom$slave_arregion), - .slave_arsize(boot_rom$slave_arsize), - .slave_arvalid(boot_rom$slave_arvalid), - .slave_awaddr(boot_rom$slave_awaddr), - .slave_awburst(boot_rom$slave_awburst), - .slave_awcache(boot_rom$slave_awcache), - .slave_awid(boot_rom$slave_awid), - .slave_awlen(boot_rom$slave_awlen), - .slave_awlock(boot_rom$slave_awlock), - .slave_awprot(boot_rom$slave_awprot), - .slave_awqos(boot_rom$slave_awqos), - .slave_awregion(boot_rom$slave_awregion), - .slave_awsize(boot_rom$slave_awsize), - .slave_awvalid(boot_rom$slave_awvalid), - .slave_bready(boot_rom$slave_bready), - .slave_rready(boot_rom$slave_rready), - .slave_wdata(boot_rom$slave_wdata), - .slave_wid(boot_rom$slave_wid), - .slave_wlast(boot_rom$slave_wlast), - .slave_wstrb(boot_rom$slave_wstrb), - .slave_wvalid(boot_rom$slave_wvalid), - .EN_set_addr_map(boot_rom$EN_set_addr_map), - .RDY_set_addr_map(), - .slave_awready(boot_rom$slave_awready), - .slave_wready(boot_rom$slave_wready), - .slave_bvalid(boot_rom$slave_bvalid), - .slave_bid(boot_rom$slave_bid), - .slave_bresp(boot_rom$slave_bresp), - .slave_arready(boot_rom$slave_arready), - .slave_rvalid(boot_rom$slave_rvalid), - .slave_rid(boot_rom$slave_rid), - .slave_rdata(boot_rom$slave_rdata), - .slave_rresp(boot_rom$slave_rresp), - .slave_rlast(boot_rom$slave_rlast)); - - // submodule boot_rom_axi4_deburster - mkAXI4_Deburster_A boot_rom_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(boot_rom_axi4_deburster$from_master_araddr), - .from_master_arburst(boot_rom_axi4_deburster$from_master_arburst), - .from_master_arcache(boot_rom_axi4_deburster$from_master_arcache), - .from_master_arid(boot_rom_axi4_deburster$from_master_arid), - .from_master_arlen(boot_rom_axi4_deburster$from_master_arlen), - .from_master_arlock(boot_rom_axi4_deburster$from_master_arlock), - .from_master_arprot(boot_rom_axi4_deburster$from_master_arprot), - .from_master_arqos(boot_rom_axi4_deburster$from_master_arqos), - .from_master_arregion(boot_rom_axi4_deburster$from_master_arregion), - .from_master_arsize(boot_rom_axi4_deburster$from_master_arsize), - .from_master_arvalid(boot_rom_axi4_deburster$from_master_arvalid), - .from_master_awaddr(boot_rom_axi4_deburster$from_master_awaddr), - .from_master_awburst(boot_rom_axi4_deburster$from_master_awburst), - .from_master_awcache(boot_rom_axi4_deburster$from_master_awcache), - .from_master_awid(boot_rom_axi4_deburster$from_master_awid), - .from_master_awlen(boot_rom_axi4_deburster$from_master_awlen), - .from_master_awlock(boot_rom_axi4_deburster$from_master_awlock), - .from_master_awprot(boot_rom_axi4_deburster$from_master_awprot), - .from_master_awqos(boot_rom_axi4_deburster$from_master_awqos), - .from_master_awregion(boot_rom_axi4_deburster$from_master_awregion), - .from_master_awsize(boot_rom_axi4_deburster$from_master_awsize), - .from_master_awvalid(boot_rom_axi4_deburster$from_master_awvalid), - .from_master_bready(boot_rom_axi4_deburster$from_master_bready), - .from_master_rready(boot_rom_axi4_deburster$from_master_rready), - .from_master_wdata(boot_rom_axi4_deburster$from_master_wdata), - .from_master_wid(boot_rom_axi4_deburster$from_master_wid), - .from_master_wlast(boot_rom_axi4_deburster$from_master_wlast), - .from_master_wstrb(boot_rom_axi4_deburster$from_master_wstrb), - .from_master_wvalid(boot_rom_axi4_deburster$from_master_wvalid), - .to_slave_arready(boot_rom_axi4_deburster$to_slave_arready), - .to_slave_awready(boot_rom_axi4_deburster$to_slave_awready), - .to_slave_bid(boot_rom_axi4_deburster$to_slave_bid), - .to_slave_bresp(boot_rom_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(boot_rom_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(boot_rom_axi4_deburster$to_slave_rdata), - .to_slave_rid(boot_rom_axi4_deburster$to_slave_rid), - .to_slave_rlast(boot_rom_axi4_deburster$to_slave_rlast), - .to_slave_rresp(boot_rom_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(boot_rom_axi4_deburster$to_slave_rvalid), - .to_slave_wready(boot_rom_axi4_deburster$to_slave_wready), - .EN_reset(boot_rom_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(boot_rom_axi4_deburster$from_master_awready), - .from_master_wready(boot_rom_axi4_deburster$from_master_wready), - .from_master_bvalid(boot_rom_axi4_deburster$from_master_bvalid), - .from_master_bid(boot_rom_axi4_deburster$from_master_bid), - .from_master_bresp(boot_rom_axi4_deburster$from_master_bresp), - .from_master_arready(boot_rom_axi4_deburster$from_master_arready), - .from_master_rvalid(boot_rom_axi4_deburster$from_master_rvalid), - .from_master_rid(boot_rom_axi4_deburster$from_master_rid), - .from_master_rdata(boot_rom_axi4_deburster$from_master_rdata), - .from_master_rresp(boot_rom_axi4_deburster$from_master_rresp), - .from_master_rlast(boot_rom_axi4_deburster$from_master_rlast), - .to_slave_awvalid(boot_rom_axi4_deburster$to_slave_awvalid), - .to_slave_awid(boot_rom_axi4_deburster$to_slave_awid), - .to_slave_awaddr(boot_rom_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(boot_rom_axi4_deburster$to_slave_awlen), - .to_slave_awsize(boot_rom_axi4_deburster$to_slave_awsize), - .to_slave_awburst(boot_rom_axi4_deburster$to_slave_awburst), - .to_slave_awlock(boot_rom_axi4_deburster$to_slave_awlock), - .to_slave_awcache(boot_rom_axi4_deburster$to_slave_awcache), - .to_slave_awprot(boot_rom_axi4_deburster$to_slave_awprot), - .to_slave_awqos(boot_rom_axi4_deburster$to_slave_awqos), - .to_slave_awregion(boot_rom_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(boot_rom_axi4_deburster$to_slave_wvalid), - .to_slave_wid(boot_rom_axi4_deburster$to_slave_wid), - .to_slave_wdata(boot_rom_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(boot_rom_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(boot_rom_axi4_deburster$to_slave_wlast), - .to_slave_bready(boot_rom_axi4_deburster$to_slave_bready), - .to_slave_arvalid(boot_rom_axi4_deburster$to_slave_arvalid), - .to_slave_arid(boot_rom_axi4_deburster$to_slave_arid), - .to_slave_araddr(boot_rom_axi4_deburster$to_slave_araddr), - .to_slave_arlen(boot_rom_axi4_deburster$to_slave_arlen), - .to_slave_arsize(boot_rom_axi4_deburster$to_slave_arsize), - .to_slave_arburst(boot_rom_axi4_deburster$to_slave_arburst), - .to_slave_arlock(boot_rom_axi4_deburster$to_slave_arlock), - .to_slave_arcache(boot_rom_axi4_deburster$to_slave_arcache), - .to_slave_arprot(boot_rom_axi4_deburster$to_slave_arprot), - .to_slave_arqos(boot_rom_axi4_deburster$to_slave_arqos), - .to_slave_arregion(boot_rom_axi4_deburster$to_slave_arregion), - .to_slave_rready(boot_rom_axi4_deburster$to_slave_rready)); - - // submodule core - mkCore core(.CLK(CLK), - .RST_N(RST_N), - .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_12_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_13_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_14_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_15_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_1_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_2_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_3_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_4_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_5_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_6_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_7_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_8_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_9_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear), - .cpu_dmem_master_arready(core$cpu_dmem_master_arready), - .cpu_dmem_master_awready(core$cpu_dmem_master_awready), - .cpu_dmem_master_bid(core$cpu_dmem_master_bid), - .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), - .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata), - .cpu_dmem_master_rid(core$cpu_dmem_master_rid), - .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast), - .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), - .cpu_dmem_master_wready(core$cpu_dmem_master_wready), - .cpu_imem_master_arready(core$cpu_imem_master_arready), - .cpu_imem_master_awready(core$cpu_imem_master_awready), - .cpu_imem_master_bid(core$cpu_imem_master_bid), - .cpu_imem_master_bresp(core$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), - .cpu_imem_master_rdata(core$cpu_imem_master_rdata), - .cpu_imem_master_rid(core$cpu_imem_master_rid), - .cpu_imem_master_rlast(core$cpu_imem_master_rlast), - .cpu_imem_master_rresp(core$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), - .cpu_imem_master_wready(core$cpu_imem_master_wready), - .cpu_reset_server_request_put(core$cpu_reset_server_request_put), - .nmi_req_set_not_clear(core$nmi_req_set_not_clear), - .set_verbosity_logdelay(core$set_verbosity_logdelay), - .set_verbosity_verbosity(core$set_verbosity_verbosity), - .EN_set_verbosity(core$EN_set_verbosity), - .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get), - .RDY_set_verbosity(), - .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put), - .cpu_reset_server_response_get(), - .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), - .cpu_imem_master_awid(core$cpu_imem_master_awid), - .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr), - .cpu_imem_master_awlen(core$cpu_imem_master_awlen), - .cpu_imem_master_awsize(core$cpu_imem_master_awsize), - .cpu_imem_master_awburst(core$cpu_imem_master_awburst), - .cpu_imem_master_awlock(core$cpu_imem_master_awlock), - .cpu_imem_master_awcache(core$cpu_imem_master_awcache), - .cpu_imem_master_awprot(core$cpu_imem_master_awprot), - .cpu_imem_master_awqos(core$cpu_imem_master_awqos), - .cpu_imem_master_awregion(core$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), - .cpu_imem_master_wid(core$cpu_imem_master_wid), - .cpu_imem_master_wdata(core$cpu_imem_master_wdata), - .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb), - .cpu_imem_master_wlast(core$cpu_imem_master_wlast), - .cpu_imem_master_bready(core$cpu_imem_master_bready), - .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), - .cpu_imem_master_arid(core$cpu_imem_master_arid), - .cpu_imem_master_araddr(core$cpu_imem_master_araddr), - .cpu_imem_master_arlen(core$cpu_imem_master_arlen), - .cpu_imem_master_arsize(core$cpu_imem_master_arsize), - .cpu_imem_master_arburst(core$cpu_imem_master_arburst), - .cpu_imem_master_arlock(core$cpu_imem_master_arlock), - .cpu_imem_master_arcache(core$cpu_imem_master_arcache), - .cpu_imem_master_arprot(core$cpu_imem_master_arprot), - .cpu_imem_master_arqos(core$cpu_imem_master_arqos), - .cpu_imem_master_arregion(core$cpu_imem_master_arregion), - .cpu_imem_master_rready(core$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), - .cpu_dmem_master_awid(core$cpu_dmem_master_awid), - .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr), - .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen), - .cpu_dmem_master_awsize(core$cpu_dmem_master_awsize), - .cpu_dmem_master_awburst(core$cpu_dmem_master_awburst), - .cpu_dmem_master_awlock(core$cpu_dmem_master_awlock), - .cpu_dmem_master_awcache(core$cpu_dmem_master_awcache), - .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot), - .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos), - .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(core$cpu_dmem_master_wid), - .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata), - .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb), - .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast), - .cpu_dmem_master_bready(core$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), - .cpu_dmem_master_arid(core$cpu_dmem_master_arid), - .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr), - .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen), - .cpu_dmem_master_arsize(core$cpu_dmem_master_arsize), - .cpu_dmem_master_arburst(core$cpu_dmem_master_arburst), - .cpu_dmem_master_arlock(core$cpu_dmem_master_arlock), - .cpu_dmem_master_arcache(core$cpu_dmem_master_arcache), - .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot), - .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos), - .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion), - .cpu_dmem_master_rready(core$cpu_dmem_master_rready)); - - // submodule fabric - mkFabric_AXI4 fabric(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric$v_to_slaves_2_wready), - .EN_reset(fabric$EN_reset), - .EN_set_verbosity(fabric$EN_set_verbosity), - .RDY_reset(fabric$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric$v_to_slaves_2_rready)); - - // submodule mem0_controller - mkMem_Controller mem0_controller(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(mem0_controller$set_addr_map_addr_base), - .set_addr_map_addr_lim(mem0_controller$set_addr_map_addr_lim), - .set_watch_tohost_tohost_addr(mem0_controller$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(mem0_controller$set_watch_tohost_watch_tohost), - .slave_araddr(mem0_controller$slave_araddr), - .slave_arburst(mem0_controller$slave_arburst), - .slave_arcache(mem0_controller$slave_arcache), - .slave_arid(mem0_controller$slave_arid), - .slave_arlen(mem0_controller$slave_arlen), - .slave_arlock(mem0_controller$slave_arlock), - .slave_arprot(mem0_controller$slave_arprot), - .slave_arqos(mem0_controller$slave_arqos), - .slave_arregion(mem0_controller$slave_arregion), - .slave_arsize(mem0_controller$slave_arsize), - .slave_arvalid(mem0_controller$slave_arvalid), - .slave_awaddr(mem0_controller$slave_awaddr), - .slave_awburst(mem0_controller$slave_awburst), - .slave_awcache(mem0_controller$slave_awcache), - .slave_awid(mem0_controller$slave_awid), - .slave_awlen(mem0_controller$slave_awlen), - .slave_awlock(mem0_controller$slave_awlock), - .slave_awprot(mem0_controller$slave_awprot), - .slave_awqos(mem0_controller$slave_awqos), - .slave_awregion(mem0_controller$slave_awregion), - .slave_awsize(mem0_controller$slave_awsize), - .slave_awvalid(mem0_controller$slave_awvalid), - .slave_bready(mem0_controller$slave_bready), - .slave_rready(mem0_controller$slave_rready), - .slave_wdata(mem0_controller$slave_wdata), - .slave_wid(mem0_controller$slave_wid), - .slave_wlast(mem0_controller$slave_wlast), - .slave_wstrb(mem0_controller$slave_wstrb), - .slave_wvalid(mem0_controller$slave_wvalid), - .to_raw_mem_response_put(mem0_controller$to_raw_mem_response_put), - .EN_server_reset_request_put(mem0_controller$EN_server_reset_request_put), - .EN_server_reset_response_get(mem0_controller$EN_server_reset_response_get), - .EN_set_addr_map(mem0_controller$EN_set_addr_map), - .EN_to_raw_mem_request_get(mem0_controller$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(mem0_controller$EN_to_raw_mem_response_put), - .EN_set_watch_tohost(mem0_controller$EN_set_watch_tohost), - .RDY_server_reset_request_put(mem0_controller$RDY_server_reset_request_put), - .RDY_server_reset_response_get(mem0_controller$RDY_server_reset_response_get), - .RDY_set_addr_map(mem0_controller$RDY_set_addr_map), - .slave_awready(mem0_controller$slave_awready), - .slave_wready(mem0_controller$slave_wready), - .slave_bvalid(mem0_controller$slave_bvalid), - .slave_bid(mem0_controller$slave_bid), - .slave_bresp(mem0_controller$slave_bresp), - .slave_arready(mem0_controller$slave_arready), - .slave_rvalid(mem0_controller$slave_rvalid), - .slave_rid(mem0_controller$slave_rid), - .slave_rdata(mem0_controller$slave_rdata), - .slave_rresp(mem0_controller$slave_rresp), - .slave_rlast(mem0_controller$slave_rlast), - .to_raw_mem_request_get(mem0_controller$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(mem0_controller$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(mem0_controller$RDY_to_raw_mem_response_put), - .status(mem0_controller$status), - .RDY_set_watch_tohost()); - - // submodule mem0_controller_axi4_deburster - mkAXI4_Deburster_A mem0_controller_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(mem0_controller_axi4_deburster$from_master_araddr), - .from_master_arburst(mem0_controller_axi4_deburster$from_master_arburst), - .from_master_arcache(mem0_controller_axi4_deburster$from_master_arcache), - .from_master_arid(mem0_controller_axi4_deburster$from_master_arid), - .from_master_arlen(mem0_controller_axi4_deburster$from_master_arlen), - .from_master_arlock(mem0_controller_axi4_deburster$from_master_arlock), - .from_master_arprot(mem0_controller_axi4_deburster$from_master_arprot), - .from_master_arqos(mem0_controller_axi4_deburster$from_master_arqos), - .from_master_arregion(mem0_controller_axi4_deburster$from_master_arregion), - .from_master_arsize(mem0_controller_axi4_deburster$from_master_arsize), - .from_master_arvalid(mem0_controller_axi4_deburster$from_master_arvalid), - .from_master_awaddr(mem0_controller_axi4_deburster$from_master_awaddr), - .from_master_awburst(mem0_controller_axi4_deburster$from_master_awburst), - .from_master_awcache(mem0_controller_axi4_deburster$from_master_awcache), - .from_master_awid(mem0_controller_axi4_deburster$from_master_awid), - .from_master_awlen(mem0_controller_axi4_deburster$from_master_awlen), - .from_master_awlock(mem0_controller_axi4_deburster$from_master_awlock), - .from_master_awprot(mem0_controller_axi4_deburster$from_master_awprot), - .from_master_awqos(mem0_controller_axi4_deburster$from_master_awqos), - .from_master_awregion(mem0_controller_axi4_deburster$from_master_awregion), - .from_master_awsize(mem0_controller_axi4_deburster$from_master_awsize), - .from_master_awvalid(mem0_controller_axi4_deburster$from_master_awvalid), - .from_master_bready(mem0_controller_axi4_deburster$from_master_bready), - .from_master_rready(mem0_controller_axi4_deburster$from_master_rready), - .from_master_wdata(mem0_controller_axi4_deburster$from_master_wdata), - .from_master_wid(mem0_controller_axi4_deburster$from_master_wid), - .from_master_wlast(mem0_controller_axi4_deburster$from_master_wlast), - .from_master_wstrb(mem0_controller_axi4_deburster$from_master_wstrb), - .from_master_wvalid(mem0_controller_axi4_deburster$from_master_wvalid), - .to_slave_arready(mem0_controller_axi4_deburster$to_slave_arready), - .to_slave_awready(mem0_controller_axi4_deburster$to_slave_awready), - .to_slave_bid(mem0_controller_axi4_deburster$to_slave_bid), - .to_slave_bresp(mem0_controller_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(mem0_controller_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(mem0_controller_axi4_deburster$to_slave_rdata), - .to_slave_rid(mem0_controller_axi4_deburster$to_slave_rid), - .to_slave_rlast(mem0_controller_axi4_deburster$to_slave_rlast), - .to_slave_rresp(mem0_controller_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(mem0_controller_axi4_deburster$to_slave_rvalid), - .to_slave_wready(mem0_controller_axi4_deburster$to_slave_wready), - .EN_reset(mem0_controller_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(mem0_controller_axi4_deburster$from_master_awready), - .from_master_wready(mem0_controller_axi4_deburster$from_master_wready), - .from_master_bvalid(mem0_controller_axi4_deburster$from_master_bvalid), - .from_master_bid(mem0_controller_axi4_deburster$from_master_bid), - .from_master_bresp(mem0_controller_axi4_deburster$from_master_bresp), - .from_master_arready(mem0_controller_axi4_deburster$from_master_arready), - .from_master_rvalid(mem0_controller_axi4_deburster$from_master_rvalid), - .from_master_rid(mem0_controller_axi4_deburster$from_master_rid), - .from_master_rdata(mem0_controller_axi4_deburster$from_master_rdata), - .from_master_rresp(mem0_controller_axi4_deburster$from_master_rresp), - .from_master_rlast(mem0_controller_axi4_deburster$from_master_rlast), - .to_slave_awvalid(mem0_controller_axi4_deburster$to_slave_awvalid), - .to_slave_awid(mem0_controller_axi4_deburster$to_slave_awid), - .to_slave_awaddr(mem0_controller_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(mem0_controller_axi4_deburster$to_slave_awlen), - .to_slave_awsize(mem0_controller_axi4_deburster$to_slave_awsize), - .to_slave_awburst(mem0_controller_axi4_deburster$to_slave_awburst), - .to_slave_awlock(mem0_controller_axi4_deburster$to_slave_awlock), - .to_slave_awcache(mem0_controller_axi4_deburster$to_slave_awcache), - .to_slave_awprot(mem0_controller_axi4_deburster$to_slave_awprot), - .to_slave_awqos(mem0_controller_axi4_deburster$to_slave_awqos), - .to_slave_awregion(mem0_controller_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(mem0_controller_axi4_deburster$to_slave_wvalid), - .to_slave_wid(mem0_controller_axi4_deburster$to_slave_wid), - .to_slave_wdata(mem0_controller_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(mem0_controller_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(mem0_controller_axi4_deburster$to_slave_wlast), - .to_slave_bready(mem0_controller_axi4_deburster$to_slave_bready), - .to_slave_arvalid(mem0_controller_axi4_deburster$to_slave_arvalid), - .to_slave_arid(mem0_controller_axi4_deburster$to_slave_arid), - .to_slave_araddr(mem0_controller_axi4_deburster$to_slave_araddr), - .to_slave_arlen(mem0_controller_axi4_deburster$to_slave_arlen), - .to_slave_arsize(mem0_controller_axi4_deburster$to_slave_arsize), - .to_slave_arburst(mem0_controller_axi4_deburster$to_slave_arburst), - .to_slave_arlock(mem0_controller_axi4_deburster$to_slave_arlock), - .to_slave_arcache(mem0_controller_axi4_deburster$to_slave_arcache), - .to_slave_arprot(mem0_controller_axi4_deburster$to_slave_arprot), - .to_slave_arqos(mem0_controller_axi4_deburster$to_slave_arqos), - .to_slave_arregion(mem0_controller_axi4_deburster$to_slave_arregion), - .to_slave_rready(mem0_controller_axi4_deburster$to_slave_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule uart0 - mkUART uart0(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(uart0$put_from_console_put), - .set_addr_map_addr_base(uart0$set_addr_map_addr_base), - .set_addr_map_addr_lim(uart0$set_addr_map_addr_lim), - .slave_araddr(uart0$slave_araddr), - .slave_arburst(uart0$slave_arburst), - .slave_arcache(uart0$slave_arcache), - .slave_arid(uart0$slave_arid), - .slave_arlen(uart0$slave_arlen), - .slave_arlock(uart0$slave_arlock), - .slave_arprot(uart0$slave_arprot), - .slave_arqos(uart0$slave_arqos), - .slave_arregion(uart0$slave_arregion), - .slave_arsize(uart0$slave_arsize), - .slave_arvalid(uart0$slave_arvalid), - .slave_awaddr(uart0$slave_awaddr), - .slave_awburst(uart0$slave_awburst), - .slave_awcache(uart0$slave_awcache), - .slave_awid(uart0$slave_awid), - .slave_awlen(uart0$slave_awlen), - .slave_awlock(uart0$slave_awlock), - .slave_awprot(uart0$slave_awprot), - .slave_awqos(uart0$slave_awqos), - .slave_awregion(uart0$slave_awregion), - .slave_awsize(uart0$slave_awsize), - .slave_awvalid(uart0$slave_awvalid), - .slave_bready(uart0$slave_bready), - .slave_rready(uart0$slave_rready), - .slave_wdata(uart0$slave_wdata), - .slave_wid(uart0$slave_wid), - .slave_wlast(uart0$slave_wlast), - .slave_wstrb(uart0$slave_wstrb), - .slave_wvalid(uart0$slave_wvalid), - .EN_server_reset_request_put(uart0$EN_server_reset_request_put), - .EN_server_reset_response_get(uart0$EN_server_reset_response_get), - .EN_set_addr_map(uart0$EN_set_addr_map), - .EN_get_to_console_get(uart0$EN_get_to_console_get), - .EN_put_from_console_put(uart0$EN_put_from_console_put), - .RDY_server_reset_request_put(uart0$RDY_server_reset_request_put), - .RDY_server_reset_response_get(uart0$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .slave_awready(uart0$slave_awready), - .slave_wready(uart0$slave_wready), - .slave_bvalid(uart0$slave_bvalid), - .slave_bid(uart0$slave_bid), - .slave_bresp(uart0$slave_bresp), - .slave_arready(uart0$slave_arready), - .slave_rvalid(uart0$slave_rvalid), - .slave_rid(uart0$slave_rid), - .slave_rdata(uart0$slave_rdata), - .slave_rresp(uart0$slave_rresp), - .slave_rlast(uart0$slave_rlast), - .get_to_console_get(uart0$get_to_console_get), - .RDY_get_to_console_get(uart0$RDY_get_to_console_get), - .RDY_put_from_console_put(uart0$RDY_put_from_console_put), - .intr(uart0$intr)); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_5 - assign CAN_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - - // rule RL_rl_wr_data_channel_5 - assign CAN_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_response_channel_5 - assign CAN_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_5 - assign CAN_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - - // rule RL_rl_rd_data_channel_5 - assign CAN_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_6 - assign CAN_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - - // rule RL_rl_wr_data_channel_6 - assign CAN_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - - // rule RL_rl_wr_response_channel_6 - assign CAN_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_6 - assign CAN_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - - // rule RL_rl_rd_data_channel_6 - assign CAN_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - - // rule RL_rl_connect_external_interrupt_requests - assign CAN_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - - // rule RL_rl_reset_start_initial - assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete_initial - assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete_initial = - MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = - mem0_controller$RDY_server_reset_request_put && - uart0$RDY_server_reset_request_put && - fabric$RDY_reset && - core$RDY_cpu_reset_server_request_put && - rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && - mem0_controller$RDY_server_reset_response_get && - uart0$RDY_server_reset_response_get && - core$RDY_cpu_reset_server_response_get && - rg_state == 2'd1 ; - - // register rg_state - assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_start_initial || - WILL_FIRE_RL_rl_reset_complete_initial ; - - // submodule boot_rom - assign boot_rom$set_addr_map_addr_base = soc_map$m_boot_rom_addr_base ; - assign boot_rom$set_addr_map_addr_lim = soc_map$m_boot_rom_addr_lim ; - assign boot_rom$slave_araddr = boot_rom_axi4_deburster$to_slave_araddr ; - assign boot_rom$slave_arburst = boot_rom_axi4_deburster$to_slave_arburst ; - assign boot_rom$slave_arcache = boot_rom_axi4_deburster$to_slave_arcache ; - assign boot_rom$slave_arid = boot_rom_axi4_deburster$to_slave_arid ; - assign boot_rom$slave_arlen = boot_rom_axi4_deburster$to_slave_arlen ; - assign boot_rom$slave_arlock = boot_rom_axi4_deburster$to_slave_arlock ; - assign boot_rom$slave_arprot = boot_rom_axi4_deburster$to_slave_arprot ; - assign boot_rom$slave_arqos = boot_rom_axi4_deburster$to_slave_arqos ; - assign boot_rom$slave_arregion = boot_rom_axi4_deburster$to_slave_arregion ; - assign boot_rom$slave_arsize = boot_rom_axi4_deburster$to_slave_arsize ; - assign boot_rom$slave_arvalid = boot_rom_axi4_deburster$to_slave_arvalid ; - assign boot_rom$slave_awaddr = boot_rom_axi4_deburster$to_slave_awaddr ; - assign boot_rom$slave_awburst = boot_rom_axi4_deburster$to_slave_awburst ; - assign boot_rom$slave_awcache = boot_rom_axi4_deburster$to_slave_awcache ; - assign boot_rom$slave_awid = boot_rom_axi4_deburster$to_slave_awid ; - assign boot_rom$slave_awlen = boot_rom_axi4_deburster$to_slave_awlen ; - assign boot_rom$slave_awlock = boot_rom_axi4_deburster$to_slave_awlock ; - assign boot_rom$slave_awprot = boot_rom_axi4_deburster$to_slave_awprot ; - assign boot_rom$slave_awqos = boot_rom_axi4_deburster$to_slave_awqos ; - assign boot_rom$slave_awregion = boot_rom_axi4_deburster$to_slave_awregion ; - assign boot_rom$slave_awsize = boot_rom_axi4_deburster$to_slave_awsize ; - assign boot_rom$slave_awvalid = boot_rom_axi4_deburster$to_slave_awvalid ; - assign boot_rom$slave_bready = boot_rom_axi4_deburster$to_slave_bready ; - assign boot_rom$slave_rready = boot_rom_axi4_deburster$to_slave_rready ; - assign boot_rom$slave_wdata = boot_rom_axi4_deburster$to_slave_wdata ; - assign boot_rom$slave_wid = boot_rom_axi4_deburster$to_slave_wid ; - assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; - assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; - assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - - // submodule boot_rom_axi4_deburster - assign boot_rom_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_0_araddr ; - assign boot_rom_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_0_arburst ; - assign boot_rom_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_0_arcache ; - assign boot_rom_axi4_deburster$from_master_arid = - fabric$v_to_slaves_0_arid ; - assign boot_rom_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_0_arlen ; - assign boot_rom_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_0_arlock ; - assign boot_rom_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_0_arprot ; - assign boot_rom_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_0_arqos ; - assign boot_rom_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_0_arregion ; - assign boot_rom_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_0_arsize ; - assign boot_rom_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_0_arvalid ; - assign boot_rom_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_0_awaddr ; - assign boot_rom_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_0_awburst ; - assign boot_rom_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_0_awcache ; - assign boot_rom_axi4_deburster$from_master_awid = - fabric$v_to_slaves_0_awid ; - assign boot_rom_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_0_awlen ; - assign boot_rom_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_0_awlock ; - assign boot_rom_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_0_awprot ; - assign boot_rom_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_0_awqos ; - assign boot_rom_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_0_awregion ; - assign boot_rom_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_0_awsize ; - assign boot_rom_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_0_awvalid ; - assign boot_rom_axi4_deburster$from_master_bready = - fabric$v_to_slaves_0_bready ; - assign boot_rom_axi4_deburster$from_master_rready = - fabric$v_to_slaves_0_rready ; - assign boot_rom_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_0_wdata ; - assign boot_rom_axi4_deburster$from_master_wid = fabric$v_to_slaves_0_wid ; - assign boot_rom_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_0_wlast ; - assign boot_rom_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_0_wstrb ; - assign boot_rom_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_0_wvalid ; - assign boot_rom_axi4_deburster$to_slave_arready = boot_rom$slave_arready ; - assign boot_rom_axi4_deburster$to_slave_awready = boot_rom$slave_awready ; - assign boot_rom_axi4_deburster$to_slave_bid = boot_rom$slave_bid ; - assign boot_rom_axi4_deburster$to_slave_bresp = boot_rom$slave_bresp ; - assign boot_rom_axi4_deburster$to_slave_bvalid = boot_rom$slave_bvalid ; - assign boot_rom_axi4_deburster$to_slave_rdata = boot_rom$slave_rdata ; - assign boot_rom_axi4_deburster$to_slave_rid = boot_rom$slave_rid ; - assign boot_rom_axi4_deburster$to_slave_rlast = boot_rom$slave_rlast ; - assign boot_rom_axi4_deburster$to_slave_rresp = boot_rom$slave_rresp ; - assign boot_rom_axi4_deburster$to_slave_rvalid = boot_rom$slave_rvalid ; - assign boot_rom_axi4_deburster$to_slave_wready = boot_rom$slave_wready ; - assign boot_rom_axi4_deburster$EN_reset = 1'b0 ; - - // submodule core - assign core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = - uart0$intr ; - assign core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$cpu_dmem_master_arready = fabric$v_from_masters_1_arready ; - assign core$cpu_dmem_master_awready = fabric$v_from_masters_1_awready ; - assign core$cpu_dmem_master_bid = fabric$v_from_masters_1_bid ; - assign core$cpu_dmem_master_bresp = fabric$v_from_masters_1_bresp ; - assign core$cpu_dmem_master_bvalid = fabric$v_from_masters_1_bvalid ; - assign core$cpu_dmem_master_rdata = fabric$v_from_masters_1_rdata ; - assign core$cpu_dmem_master_rid = fabric$v_from_masters_1_rid ; - assign core$cpu_dmem_master_rlast = fabric$v_from_masters_1_rlast ; - assign core$cpu_dmem_master_rresp = fabric$v_from_masters_1_rresp ; - assign core$cpu_dmem_master_rvalid = fabric$v_from_masters_1_rvalid ; - assign core$cpu_dmem_master_wready = fabric$v_from_masters_1_wready ; - assign core$cpu_imem_master_arready = fabric$v_from_masters_0_arready ; - assign core$cpu_imem_master_awready = fabric$v_from_masters_0_awready ; - assign core$cpu_imem_master_bid = fabric$v_from_masters_0_bid ; - assign core$cpu_imem_master_bresp = fabric$v_from_masters_0_bresp ; - assign core$cpu_imem_master_bvalid = fabric$v_from_masters_0_bvalid ; - assign core$cpu_imem_master_rdata = fabric$v_from_masters_0_rdata ; - assign core$cpu_imem_master_rid = fabric$v_from_masters_0_rid ; - assign core$cpu_imem_master_rlast = fabric$v_from_masters_0_rlast ; - assign core$cpu_imem_master_rresp = fabric$v_from_masters_0_rresp ; - assign core$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ; - assign core$cpu_imem_master_wready = fabric$v_from_masters_0_wready ; - assign core$cpu_reset_server_request_put = 1'd1 ; - assign core$nmi_req_set_not_clear = 1'd0 ; - assign core$set_verbosity_logdelay = set_verbosity_logdelay ; - assign core$set_verbosity_verbosity = set_verbosity_verbosity ; - assign core$EN_set_verbosity = EN_set_verbosity ; - assign core$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; - assign core$EN_cpu_reset_server_response_get = MUX_rg_state$write_1__SEL_2 ; - - // submodule fabric - assign fabric$set_verbosity_verbosity = 4'h0 ; - assign fabric$v_from_masters_0_araddr = core$cpu_imem_master_araddr ; - assign fabric$v_from_masters_0_arburst = core$cpu_imem_master_arburst ; - assign fabric$v_from_masters_0_arcache = core$cpu_imem_master_arcache ; - assign fabric$v_from_masters_0_arid = core$cpu_imem_master_arid ; - assign fabric$v_from_masters_0_arlen = core$cpu_imem_master_arlen ; - assign fabric$v_from_masters_0_arlock = core$cpu_imem_master_arlock ; - assign fabric$v_from_masters_0_arprot = core$cpu_imem_master_arprot ; - assign fabric$v_from_masters_0_arqos = core$cpu_imem_master_arqos ; - assign fabric$v_from_masters_0_arregion = core$cpu_imem_master_arregion ; - assign fabric$v_from_masters_0_arsize = core$cpu_imem_master_arsize ; - assign fabric$v_from_masters_0_arvalid = core$cpu_imem_master_arvalid ; - assign fabric$v_from_masters_0_awaddr = core$cpu_imem_master_awaddr ; - assign fabric$v_from_masters_0_awburst = core$cpu_imem_master_awburst ; - assign fabric$v_from_masters_0_awcache = core$cpu_imem_master_awcache ; - assign fabric$v_from_masters_0_awid = core$cpu_imem_master_awid ; - assign fabric$v_from_masters_0_awlen = core$cpu_imem_master_awlen ; - assign fabric$v_from_masters_0_awlock = core$cpu_imem_master_awlock ; - assign fabric$v_from_masters_0_awprot = core$cpu_imem_master_awprot ; - assign fabric$v_from_masters_0_awqos = core$cpu_imem_master_awqos ; - assign fabric$v_from_masters_0_awregion = core$cpu_imem_master_awregion ; - assign fabric$v_from_masters_0_awsize = core$cpu_imem_master_awsize ; - assign fabric$v_from_masters_0_awvalid = core$cpu_imem_master_awvalid ; - assign fabric$v_from_masters_0_bready = core$cpu_imem_master_bready ; - assign fabric$v_from_masters_0_rready = core$cpu_imem_master_rready ; - assign fabric$v_from_masters_0_wdata = core$cpu_imem_master_wdata ; - assign fabric$v_from_masters_0_wid = core$cpu_imem_master_wid ; - assign fabric$v_from_masters_0_wlast = core$cpu_imem_master_wlast ; - assign fabric$v_from_masters_0_wstrb = core$cpu_imem_master_wstrb ; - assign fabric$v_from_masters_0_wvalid = core$cpu_imem_master_wvalid ; - assign fabric$v_from_masters_1_araddr = core$cpu_dmem_master_araddr ; - assign fabric$v_from_masters_1_arburst = core$cpu_dmem_master_arburst ; - assign fabric$v_from_masters_1_arcache = core$cpu_dmem_master_arcache ; - assign fabric$v_from_masters_1_arid = core$cpu_dmem_master_arid ; - assign fabric$v_from_masters_1_arlen = core$cpu_dmem_master_arlen ; - assign fabric$v_from_masters_1_arlock = core$cpu_dmem_master_arlock ; - assign fabric$v_from_masters_1_arprot = core$cpu_dmem_master_arprot ; - assign fabric$v_from_masters_1_arqos = core$cpu_dmem_master_arqos ; - assign fabric$v_from_masters_1_arregion = core$cpu_dmem_master_arregion ; - assign fabric$v_from_masters_1_arsize = core$cpu_dmem_master_arsize ; - assign fabric$v_from_masters_1_arvalid = core$cpu_dmem_master_arvalid ; - assign fabric$v_from_masters_1_awaddr = core$cpu_dmem_master_awaddr ; - assign fabric$v_from_masters_1_awburst = core$cpu_dmem_master_awburst ; - assign fabric$v_from_masters_1_awcache = core$cpu_dmem_master_awcache ; - assign fabric$v_from_masters_1_awid = core$cpu_dmem_master_awid ; - assign fabric$v_from_masters_1_awlen = core$cpu_dmem_master_awlen ; - assign fabric$v_from_masters_1_awlock = core$cpu_dmem_master_awlock ; - assign fabric$v_from_masters_1_awprot = core$cpu_dmem_master_awprot ; - assign fabric$v_from_masters_1_awqos = core$cpu_dmem_master_awqos ; - assign fabric$v_from_masters_1_awregion = core$cpu_dmem_master_awregion ; - assign fabric$v_from_masters_1_awsize = core$cpu_dmem_master_awsize ; - assign fabric$v_from_masters_1_awvalid = core$cpu_dmem_master_awvalid ; - assign fabric$v_from_masters_1_bready = core$cpu_dmem_master_bready ; - assign fabric$v_from_masters_1_rready = core$cpu_dmem_master_rready ; - assign fabric$v_from_masters_1_wdata = core$cpu_dmem_master_wdata ; - assign fabric$v_from_masters_1_wid = core$cpu_dmem_master_wid ; - assign fabric$v_from_masters_1_wlast = core$cpu_dmem_master_wlast ; - assign fabric$v_from_masters_1_wstrb = core$cpu_dmem_master_wstrb ; - assign fabric$v_from_masters_1_wvalid = core$cpu_dmem_master_wvalid ; - assign fabric$v_to_slaves_0_arready = - boot_rom_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_0_awready = - boot_rom_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_0_bid = boot_rom_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_0_bresp = - boot_rom_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_0_bvalid = - boot_rom_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_0_rdata = - boot_rom_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_0_rid = boot_rom_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_0_rlast = - boot_rom_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_0_rresp = - boot_rom_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_0_rvalid = - boot_rom_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_0_wready = - boot_rom_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_1_arready = - mem0_controller_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_1_awready = - mem0_controller_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_1_bid = - mem0_controller_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_1_bresp = - mem0_controller_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_1_bvalid = - mem0_controller_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_1_rdata = - mem0_controller_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_1_rid = - mem0_controller_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_1_rlast = - mem0_controller_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_1_rresp = - mem0_controller_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_1_rvalid = - mem0_controller_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_1_wready = - mem0_controller_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_2_arready = uart0$slave_arready ; - assign fabric$v_to_slaves_2_awready = uart0$slave_awready ; - assign fabric$v_to_slaves_2_bid = uart0$slave_bid ; - assign fabric$v_to_slaves_2_bresp = uart0$slave_bresp ; - assign fabric$v_to_slaves_2_bvalid = uart0$slave_bvalid ; - assign fabric$v_to_slaves_2_rdata = uart0$slave_rdata ; - assign fabric$v_to_slaves_2_rid = uart0$slave_rid ; - assign fabric$v_to_slaves_2_rlast = uart0$slave_rlast ; - assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; - assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; - assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; - assign fabric$EN_set_verbosity = 1'b0 ; - - // submodule mem0_controller - assign mem0_controller$set_addr_map_addr_base = - soc_map$m_mem0_controller_addr_base ; - assign mem0_controller$set_addr_map_addr_lim = - soc_map$m_mem0_controller_addr_lim ; - assign mem0_controller$set_watch_tohost_tohost_addr = - set_watch_tohost_tohost_addr ; - assign mem0_controller$set_watch_tohost_watch_tohost = - set_watch_tohost_watch_tohost ; - assign mem0_controller$slave_araddr = - mem0_controller_axi4_deburster$to_slave_araddr ; - assign mem0_controller$slave_arburst = - mem0_controller_axi4_deburster$to_slave_arburst ; - assign mem0_controller$slave_arcache = - mem0_controller_axi4_deburster$to_slave_arcache ; - assign mem0_controller$slave_arid = - mem0_controller_axi4_deburster$to_slave_arid ; - assign mem0_controller$slave_arlen = - mem0_controller_axi4_deburster$to_slave_arlen ; - assign mem0_controller$slave_arlock = - mem0_controller_axi4_deburster$to_slave_arlock ; - assign mem0_controller$slave_arprot = - mem0_controller_axi4_deburster$to_slave_arprot ; - assign mem0_controller$slave_arqos = - mem0_controller_axi4_deburster$to_slave_arqos ; - assign mem0_controller$slave_arregion = - mem0_controller_axi4_deburster$to_slave_arregion ; - assign mem0_controller$slave_arsize = - mem0_controller_axi4_deburster$to_slave_arsize ; - assign mem0_controller$slave_arvalid = - mem0_controller_axi4_deburster$to_slave_arvalid ; - assign mem0_controller$slave_awaddr = - mem0_controller_axi4_deburster$to_slave_awaddr ; - assign mem0_controller$slave_awburst = - mem0_controller_axi4_deburster$to_slave_awburst ; - assign mem0_controller$slave_awcache = - mem0_controller_axi4_deburster$to_slave_awcache ; - assign mem0_controller$slave_awid = - mem0_controller_axi4_deburster$to_slave_awid ; - assign mem0_controller$slave_awlen = - mem0_controller_axi4_deburster$to_slave_awlen ; - assign mem0_controller$slave_awlock = - mem0_controller_axi4_deburster$to_slave_awlock ; - assign mem0_controller$slave_awprot = - mem0_controller_axi4_deburster$to_slave_awprot ; - assign mem0_controller$slave_awqos = - mem0_controller_axi4_deburster$to_slave_awqos ; - assign mem0_controller$slave_awregion = - mem0_controller_axi4_deburster$to_slave_awregion ; - assign mem0_controller$slave_awsize = - mem0_controller_axi4_deburster$to_slave_awsize ; - assign mem0_controller$slave_awvalid = - mem0_controller_axi4_deburster$to_slave_awvalid ; - assign mem0_controller$slave_bready = - mem0_controller_axi4_deburster$to_slave_bready ; - assign mem0_controller$slave_rready = - mem0_controller_axi4_deburster$to_slave_rready ; - assign mem0_controller$slave_wdata = - mem0_controller_axi4_deburster$to_slave_wdata ; - assign mem0_controller$slave_wid = - mem0_controller_axi4_deburster$to_slave_wid ; - assign mem0_controller$slave_wlast = - mem0_controller_axi4_deburster$to_slave_wlast ; - assign mem0_controller$slave_wstrb = - mem0_controller_axi4_deburster$to_slave_wstrb ; - assign mem0_controller$slave_wvalid = - mem0_controller_axi4_deburster$to_slave_wvalid ; - assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; - assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; - assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_to_raw_mem_request_get = - EN_to_raw_mem_request_get ; - assign mem0_controller$EN_to_raw_mem_response_put = - EN_to_raw_mem_response_put ; - assign mem0_controller$EN_set_watch_tohost = EN_set_watch_tohost ; - - // submodule mem0_controller_axi4_deburster - assign mem0_controller_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_1_araddr ; - assign mem0_controller_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_1_arburst ; - assign mem0_controller_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_1_arcache ; - assign mem0_controller_axi4_deburster$from_master_arid = - fabric$v_to_slaves_1_arid ; - assign mem0_controller_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_1_arlen ; - assign mem0_controller_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_1_arlock ; - assign mem0_controller_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_1_arprot ; - assign mem0_controller_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_1_arqos ; - assign mem0_controller_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_1_arregion ; - assign mem0_controller_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_1_arsize ; - assign mem0_controller_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_1_arvalid ; - assign mem0_controller_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_1_awaddr ; - assign mem0_controller_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_1_awburst ; - assign mem0_controller_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_1_awcache ; - assign mem0_controller_axi4_deburster$from_master_awid = - fabric$v_to_slaves_1_awid ; - assign mem0_controller_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_1_awlen ; - assign mem0_controller_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_1_awlock ; - assign mem0_controller_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_1_awprot ; - assign mem0_controller_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_1_awqos ; - assign mem0_controller_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_1_awregion ; - assign mem0_controller_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_1_awsize ; - assign mem0_controller_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_1_awvalid ; - assign mem0_controller_axi4_deburster$from_master_bready = - fabric$v_to_slaves_1_bready ; - assign mem0_controller_axi4_deburster$from_master_rready = - fabric$v_to_slaves_1_rready ; - assign mem0_controller_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_1_wdata ; - assign mem0_controller_axi4_deburster$from_master_wid = - fabric$v_to_slaves_1_wid ; - assign mem0_controller_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_1_wlast ; - assign mem0_controller_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_1_wstrb ; - assign mem0_controller_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_1_wvalid ; - assign mem0_controller_axi4_deburster$to_slave_arready = - mem0_controller$slave_arready ; - assign mem0_controller_axi4_deburster$to_slave_awready = - mem0_controller$slave_awready ; - assign mem0_controller_axi4_deburster$to_slave_bid = - mem0_controller$slave_bid ; - assign mem0_controller_axi4_deburster$to_slave_bresp = - mem0_controller$slave_bresp ; - assign mem0_controller_axi4_deburster$to_slave_bvalid = - mem0_controller$slave_bvalid ; - assign mem0_controller_axi4_deburster$to_slave_rdata = - mem0_controller$slave_rdata ; - assign mem0_controller_axi4_deburster$to_slave_rid = - mem0_controller$slave_rid ; - assign mem0_controller_axi4_deburster$to_slave_rlast = - mem0_controller$slave_rlast ; - assign mem0_controller_axi4_deburster$to_slave_rresp = - mem0_controller$slave_rresp ; - assign mem0_controller_axi4_deburster$to_slave_rvalid = - mem0_controller$slave_rvalid ; - assign mem0_controller_axi4_deburster$to_slave_wready = - mem0_controller$slave_wready ; - assign mem0_controller_axi4_deburster$EN_reset = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule uart0 - assign uart0$put_from_console_put = put_from_console_put ; - assign uart0$set_addr_map_addr_base = soc_map$m_uart0_addr_base ; - assign uart0$set_addr_map_addr_lim = soc_map$m_uart0_addr_lim ; - assign uart0$slave_araddr = fabric$v_to_slaves_2_araddr ; - assign uart0$slave_arburst = fabric$v_to_slaves_2_arburst ; - assign uart0$slave_arcache = fabric$v_to_slaves_2_arcache ; - assign uart0$slave_arid = fabric$v_to_slaves_2_arid ; - assign uart0$slave_arlen = fabric$v_to_slaves_2_arlen ; - assign uart0$slave_arlock = fabric$v_to_slaves_2_arlock ; - assign uart0$slave_arprot = fabric$v_to_slaves_2_arprot ; - assign uart0$slave_arqos = fabric$v_to_slaves_2_arqos ; - assign uart0$slave_arregion = fabric$v_to_slaves_2_arregion ; - assign uart0$slave_arsize = fabric$v_to_slaves_2_arsize ; - assign uart0$slave_arvalid = fabric$v_to_slaves_2_arvalid ; - assign uart0$slave_awaddr = fabric$v_to_slaves_2_awaddr ; - assign uart0$slave_awburst = fabric$v_to_slaves_2_awburst ; - assign uart0$slave_awcache = fabric$v_to_slaves_2_awcache ; - assign uart0$slave_awid = fabric$v_to_slaves_2_awid ; - assign uart0$slave_awlen = fabric$v_to_slaves_2_awlen ; - assign uart0$slave_awlock = fabric$v_to_slaves_2_awlock ; - assign uart0$slave_awprot = fabric$v_to_slaves_2_awprot ; - assign uart0$slave_awqos = fabric$v_to_slaves_2_awqos ; - assign uart0$slave_awregion = fabric$v_to_slaves_2_awregion ; - assign uart0$slave_awsize = fabric$v_to_slaves_2_awsize ; - assign uart0$slave_awvalid = fabric$v_to_slaves_2_awvalid ; - assign uart0$slave_bready = fabric$v_to_slaves_2_bready ; - assign uart0$slave_rready = fabric$v_to_slaves_2_rready ; - assign uart0$slave_wdata = fabric$v_to_slaves_2_wdata ; - assign uart0$slave_wid = fabric$v_to_slaves_2_wid ; - assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; - assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; - assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_get_to_console_get = EN_get_to_console_get ; - assign uart0$EN_put_from_console_put = EN_put_from_console_put ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - begin - v__h11286 = $stime; - #0; - end - v__h11280 = v__h11286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - $display("%0d:%m.rl_reset_start_initial ...", v__h11280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - begin - v__h11556 = $stime; - #0; - end - v__h11550 = v__h11556 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - $display("%0d:%m.rl_reset_complete_initial", v__h11550); - end - // synopsys translate_on -endmodule // mkSoC_Top - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTLB.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTLB.v deleted file mode 100644 index 80794990..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTLB.v +++ /dev/null @@ -1,452 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_flush O 1 const -// lookup O 69 -// RDY_lookup O 1 -// RDY_insert O 1 -// CLK I 1 clock -// RST_N I 1 reset -// lookup_asid I 9 -// lookup_vpn I 20 -// insert_asid I 9 reg -// insert_vpn I 20 -// insert_pte I 32 reg -// insert_level I 2 -// insert_pte_pa I 34 reg -// EN_flush I 1 -// EN_insert I 1 -// -// Combinational paths from inputs to outputs: -// (lookup_asid, lookup_vpn) -> lookup -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTLB(CLK, - RST_N, - - EN_flush, - RDY_flush, - - lookup_asid, - lookup_vpn, - lookup, - RDY_lookup, - - insert_asid, - insert_vpn, - insert_pte, - insert_level, - insert_pte_pa, - EN_insert, - RDY_insert); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method flush - input EN_flush; - output RDY_flush; - - // value method lookup - input [8 : 0] lookup_asid; - input [19 : 0] lookup_vpn; - output [68 : 0] lookup; - output RDY_lookup; - - // action method insert - input [8 : 0] insert_asid; - input [19 : 0] insert_vpn; - input [31 : 0] insert_pte; - input [1 : 0] insert_level; - input [33 : 0] insert_pte_pa; - input EN_insert; - output RDY_insert; - - // signals for module outputs - wire [68 : 0] lookup; - wire RDY_flush, RDY_insert, RDY_lookup; - - // register rg_flushing - reg rg_flushing; - wire rg_flushing$D_IN, rg_flushing$EN; - - // register tlb0_valids_0 - reg tlb0_valids_0; - wire tlb0_valids_0$D_IN, tlb0_valids_0$EN; - - // register tlb0_valids_1 - reg tlb0_valids_1; - wire tlb0_valids_1$D_IN, tlb0_valids_1$EN; - - // register tlb0_valids_2 - reg tlb0_valids_2; - wire tlb0_valids_2$D_IN, tlb0_valids_2$EN; - - // register tlb0_valids_3 - reg tlb0_valids_3; - wire tlb0_valids_3$D_IN, tlb0_valids_3$EN; - - // register tlb1_valids_0 - reg tlb1_valids_0; - wire tlb1_valids_0$D_IN, tlb1_valids_0$EN; - - // register tlb1_valids_1 - reg tlb1_valids_1; - wire tlb1_valids_1$D_IN, tlb1_valids_1$EN; - - // register tlb1_valids_2 - reg tlb1_valids_2; - wire tlb1_valids_2$D_IN, tlb1_valids_2$EN; - - // register tlb1_valids_3 - reg tlb1_valids_3; - wire tlb1_valids_3$D_IN, tlb1_valids_3$EN; - - // ports of submodule tlb0_entries - wire [102 : 0] tlb0_entries$D_IN, tlb0_entries$D_OUT_1; - wire [1 : 0] tlb0_entries$ADDR_1, - tlb0_entries$ADDR_2, - tlb0_entries$ADDR_3, - tlb0_entries$ADDR_4, - tlb0_entries$ADDR_5, - tlb0_entries$ADDR_IN; - wire tlb0_entries$WE; - - // ports of submodule tlb1_entries - wire [92 : 0] tlb1_entries$D_IN, tlb1_entries$D_OUT_1; - wire [1 : 0] tlb1_entries$ADDR_1, - tlb1_entries$ADDR_2, - tlb1_entries$ADDR_3, - tlb1_entries$ADDR_4, - tlb1_entries$ADDR_5, - tlb1_entries$ADDR_IN; - wire tlb1_entries$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_initialize, - CAN_FIRE_flush, - CAN_FIRE_insert, - WILL_FIRE_RL_rl_initialize, - WILL_FIRE_flush, - WILL_FIRE_insert; - - // inputs to muxes for submodule ports - wire MUX_tlb0_valids_0$write_1__SEL_1, - MUX_tlb0_valids_1$write_1__SEL_1, - MUX_tlb0_valids_2$write_1__SEL_1, - MUX_tlb0_valids_3$write_1__SEL_1, - MUX_tlb1_valids_0$write_1__SEL_1, - MUX_tlb1_valids_1$write_1__SEL_1, - MUX_tlb1_valids_2$write_1__SEL_1, - MUX_tlb1_valids_3$write_1__SEL_1; - - // remaining internal signals - reg SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30, - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8; - wire [67 : 0] IF_NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb_ETC___d62; - wire [27 : 0] tag__h2330, tag__h2574; - wire [17 : 0] tag__h2210, tag__h2585; - wire NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_v_ETC___d23, - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d41, - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d33, - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d40, - tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d12, - tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d21; - - // action method flush - assign RDY_flush = 1'd1 ; - assign CAN_FIRE_flush = 1'd1 ; - assign WILL_FIRE_flush = EN_flush ; - - // value method lookup - assign lookup = - { NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_v_ETC___d23 && - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d41 || - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 && - (tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d12 || - tlb1_entries$D_OUT_1[39]) && - tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d21 && - (!SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 || - !tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d33 && - !tlb0_entries$D_OUT_1[39] || - !tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d40), - IF_NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb_ETC___d62 } ; - assign RDY_lookup = !rg_flushing ; - - // action method insert - assign RDY_insert = !rg_flushing ; - assign CAN_FIRE_insert = !rg_flushing ; - assign WILL_FIRE_insert = EN_insert ; - - // submodule tlb0_entries - RegFile #(.addr_width(32'd2), - .data_width(32'd103), - .lo(2'h0), - .hi(2'd3)) tlb0_entries(.CLK(CLK), - .ADDR_1(tlb0_entries$ADDR_1), - .ADDR_2(tlb0_entries$ADDR_2), - .ADDR_3(tlb0_entries$ADDR_3), - .ADDR_4(tlb0_entries$ADDR_4), - .ADDR_5(tlb0_entries$ADDR_5), - .ADDR_IN(tlb0_entries$ADDR_IN), - .D_IN(tlb0_entries$D_IN), - .WE(tlb0_entries$WE), - .D_OUT_1(tlb0_entries$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule tlb1_entries - RegFile #(.addr_width(32'd2), - .data_width(32'd93), - .lo(2'h0), - .hi(2'd3)) tlb1_entries(.CLK(CLK), - .ADDR_1(tlb1_entries$ADDR_1), - .ADDR_2(tlb1_entries$ADDR_2), - .ADDR_3(tlb1_entries$ADDR_3), - .ADDR_4(tlb1_entries$ADDR_4), - .ADDR_5(tlb1_entries$ADDR_5), - .ADDR_IN(tlb1_entries$ADDR_IN), - .D_IN(tlb1_entries$D_IN), - .WE(tlb1_entries$WE), - .D_OUT_1(tlb1_entries$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_initialize - assign CAN_FIRE_RL_rl_initialize = rg_flushing ; - assign WILL_FIRE_RL_rl_initialize = rg_flushing ; - - // inputs to muxes for submodule ports - assign MUX_tlb0_valids_0$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd0 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_1$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd1 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_2$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd2 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_3$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd3 && insert_level == 2'd0 ; - assign MUX_tlb1_valids_0$write_1__SEL_1 = - EN_insert && insert_vpn[11:10] == 2'd0 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_1$write_1__SEL_1 = - EN_insert && insert_vpn[11:10] == 2'd1 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_2$write_1__SEL_1 = - EN_insert && insert_vpn[11:10] == 2'd2 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_3$write_1__SEL_1 = - EN_insert && insert_vpn[11:10] == 2'd3 && insert_level == 2'd1 ; - - // register rg_flushing - assign rg_flushing$D_IN = EN_flush ; - assign rg_flushing$EN = rg_flushing || EN_flush ; - - // register tlb0_valids_0 - assign tlb0_valids_0$D_IN = MUX_tlb0_valids_0$write_1__SEL_1 ; - assign tlb0_valids_0$EN = - EN_insert && insert_vpn[1:0] == 2'd0 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_1 - assign tlb0_valids_1$D_IN = MUX_tlb0_valids_1$write_1__SEL_1 ; - assign tlb0_valids_1$EN = - EN_insert && insert_vpn[1:0] == 2'd1 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_2 - assign tlb0_valids_2$D_IN = MUX_tlb0_valids_2$write_1__SEL_1 ; - assign tlb0_valids_2$EN = - EN_insert && insert_vpn[1:0] == 2'd2 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_3 - assign tlb0_valids_3$D_IN = MUX_tlb0_valids_3$write_1__SEL_1 ; - assign tlb0_valids_3$EN = - EN_insert && insert_vpn[1:0] == 2'd3 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb1_valids_0 - assign tlb1_valids_0$D_IN = MUX_tlb1_valids_0$write_1__SEL_1 ; - assign tlb1_valids_0$EN = - EN_insert && insert_vpn[11:10] == 2'd0 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_1 - assign tlb1_valids_1$D_IN = MUX_tlb1_valids_1$write_1__SEL_1 ; - assign tlb1_valids_1$EN = - EN_insert && insert_vpn[11:10] == 2'd1 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_2 - assign tlb1_valids_2$D_IN = MUX_tlb1_valids_2$write_1__SEL_1 ; - assign tlb1_valids_2$EN = - EN_insert && insert_vpn[11:10] == 2'd2 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_3 - assign tlb1_valids_3$D_IN = MUX_tlb1_valids_3$write_1__SEL_1 ; - assign tlb1_valids_3$EN = - EN_insert && insert_vpn[11:10] == 2'd3 && insert_level == 2'd1 || - rg_flushing ; - - // submodule tlb0_entries - assign tlb0_entries$ADDR_1 = lookup_vpn[1:0] ; - assign tlb0_entries$ADDR_2 = 2'h0 ; - assign tlb0_entries$ADDR_3 = 2'h0 ; - assign tlb0_entries$ADDR_4 = 2'h0 ; - assign tlb0_entries$ADDR_5 = 2'h0 ; - assign tlb0_entries$ADDR_IN = insert_vpn[1:0] ; - assign tlb0_entries$D_IN = - { insert_asid, tag__h2574, insert_pte, insert_pte_pa } ; - assign tlb0_entries$WE = EN_insert && insert_level == 2'd0 ; - - // submodule tlb1_entries - assign tlb1_entries$ADDR_1 = lookup_vpn[11:10] ; - assign tlb1_entries$ADDR_2 = 2'h0 ; - assign tlb1_entries$ADDR_3 = 2'h0 ; - assign tlb1_entries$ADDR_4 = 2'h0 ; - assign tlb1_entries$ADDR_5 = 2'h0 ; - assign tlb1_entries$ADDR_IN = insert_vpn[11:10] ; - assign tlb1_entries$D_IN = - { insert_asid, tag__h2585, insert_pte, insert_pte_pa } ; - assign tlb1_entries$WE = EN_insert && insert_level == 2'd1 ; - - // remaining internal signals - assign IF_NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb_ETC___d62 = - (NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_v_ETC___d23 && - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d41) ? - { tlb0_entries$D_OUT_1[65:34], - 2'd0, - tlb0_entries$D_OUT_1[33:0] } : - { tlb1_entries$D_OUT_1[65:34], - 2'd1, - tlb1_entries$D_OUT_1[33:0] } ; - assign NOT_SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_v_ETC___d23 = - !SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 || - !tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d12 && - !tlb1_entries$D_OUT_1[39] || - !tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d21 ; - assign SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d41 = - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 && - (tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d33 || - tlb0_entries$D_OUT_1[39]) && - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d40 ; - assign tag__h2210 = { 10'd0, lookup_vpn[19:12] } ; - assign tag__h2330 = { 10'd0, lookup_vpn[19:2] } ; - assign tag__h2574 = { 10'd0, insert_vpn[19:2] } ; - assign tag__h2585 = { 10'd0, insert_vpn[19:12] } ; - assign tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d33 = - tlb0_entries$D_OUT_1[102:94] == lookup_asid ; - assign tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_9_1_BI_ETC___d40 = - tlb0_entries$D_OUT_1[93:66] == tag__h2330 ; - assign tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d12 = - tlb1_entries$D_OUT_1[92:84] == lookup_asid ; - assign tlb1_entries_sub_lookup_vpn_BITS_11_TO_10_0_BI_ETC___d21 = - tlb1_entries$D_OUT_1[83:66] == tag__h2210 ; - always@(lookup_vpn or - tlb1_valids_0 or tlb1_valids_1 or tlb1_valids_2 or tlb1_valids_3) - begin - case (lookup_vpn[11:10]) - 2'd0: - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 = - tlb1_valids_0; - 2'd1: - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 = - tlb1_valids_1; - 2'd2: - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 = - tlb1_valids_2; - 2'd3: - SEL_ARR_tlb1_valids_0_tlb1_valids_1_tlb1_valid_ETC___d8 = - tlb1_valids_3; - endcase - end - always@(lookup_vpn or - tlb0_valids_0 or tlb0_valids_1 or tlb0_valids_2 or tlb0_valids_3) - begin - case (lookup_vpn[1:0]) - 2'd0: - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 = - tlb0_valids_0; - 2'd1: - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 = - tlb0_valids_1; - 2'd2: - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 = - tlb0_valids_2; - 2'd3: - SEL_ARR_tlb0_valids_0_4_tlb0_valids_1_5_tlb0_v_ETC___d30 = - tlb0_valids_3; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_flushing <= `BSV_ASSIGNMENT_DELAY 1'd1; - end - else - begin - if (rg_flushing$EN) - rg_flushing <= `BSV_ASSIGNMENT_DELAY rg_flushing$D_IN; - end - if (tlb0_valids_0$EN) - tlb0_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_0$D_IN; - if (tlb0_valids_1$EN) - tlb0_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_1$D_IN; - if (tlb0_valids_2$EN) - tlb0_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_2$D_IN; - if (tlb0_valids_3$EN) - tlb0_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_3$D_IN; - if (tlb1_valids_0$EN) - tlb1_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_0$D_IN; - if (tlb1_valids_1$EN) - tlb1_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_1$D_IN; - if (tlb1_valids_2$EN) - tlb1_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_2$D_IN; - if (tlb1_valids_3$EN) - tlb1_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_flushing = 1'h0; - tlb0_valids_0 = 1'h0; - tlb0_valids_1 = 1'h0; - tlb0_valids_2 = 1'h0; - tlb0_valids_3 = 1'h0; - tlb1_valids_0 = 1'h0; - tlb1_valids_1 = 1'h0; - tlb1_valids_2 = 1'h0; - tlb1_valids_3 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkTLB - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v deleted file mode 100644 index 470d28c6..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v +++ /dev/null @@ -1,328 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// CLK I 1 clock -// RST_N I 1 reset -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTop_HW_Side(CLK, - RST_N); - input CLK; - input RST_N; - - // register rg_banner_printed - reg rg_banner_printed; - wire rg_banner_printed$D_IN, rg_banner_printed$EN; - - // register rg_console_in_poll - reg [11 : 0] rg_console_in_poll; - wire [11 : 0] rg_console_in_poll$D_IN; - wire rg_console_in_poll$EN; - - // ports of submodule mem_model - wire [352 : 0] mem_model$mem_server_request_put; - wire [255 : 0] mem_model$mem_server_response_get; - wire mem_model$EN_mem_server_request_put, - mem_model$EN_mem_server_response_get, - mem_model$RDY_mem_server_request_put, - mem_model$RDY_mem_server_response_get; - - // ports of submodule soc_top - wire [352 : 0] soc_top$to_raw_mem_request_get; - wire [255 : 0] soc_top$to_raw_mem_response_put; - wire [63 : 0] soc_top$set_verbosity_logdelay, - soc_top$set_watch_tohost_tohost_addr; - wire [7 : 0] soc_top$get_to_console_get, - soc_top$put_from_console_put, - soc_top$status; - wire [3 : 0] soc_top$set_verbosity_verbosity; - wire soc_top$EN_get_to_console_get, - soc_top$EN_put_from_console_put, - soc_top$EN_set_verbosity, - soc_top$EN_set_watch_tohost, - soc_top$EN_to_raw_mem_request_get, - soc_top$EN_to_raw_mem_response_put, - soc_top$RDY_get_to_console_get, - soc_top$RDY_put_from_console_put, - soc_top$RDY_to_raw_mem_request_get, - soc_top$RDY_to_raw_mem_response_put, - soc_top$set_watch_tohost_watch_tohost; - - // rule scheduling signals - wire CAN_FIRE_RL_memCnx_ClientServerRequest, - CAN_FIRE_RL_memCnx_ClientServerResponse, - CAN_FIRE_RL_rl_relay_console_in, - CAN_FIRE_RL_rl_relay_console_out, - CAN_FIRE_RL_rl_step0, - CAN_FIRE_RL_rl_terminate, - WILL_FIRE_RL_memCnx_ClientServerRequest, - WILL_FIRE_RL_memCnx_ClientServerResponse, - WILL_FIRE_RL_rl_relay_console_in, - WILL_FIRE_RL_rl_relay_console_out, - WILL_FIRE_RL_rl_step0, - WILL_FIRE_RL_rl_terminate; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h702; - reg [31 : 0] v__h743; - reg TASK_testplusargs___d12; - reg TASK_testplusargs___d11; - reg TASK_testplusargs___d15; - reg [63 : 0] tohost_addr__h571; - reg [31 : 0] v__h633; - reg [7 : 0] v__h941; - reg [31 : 0] v__h627; - reg [31 : 0] v__h737; - reg [31 : 0] v__h696; - // synopsys translate_on - - // submodule mem_model - mkMem_Model mem_model(.CLK(CLK), - .RST_N(RST_N), - .mem_server_request_put(mem_model$mem_server_request_put), - .EN_mem_server_request_put(mem_model$EN_mem_server_request_put), - .EN_mem_server_response_get(mem_model$EN_mem_server_response_get), - .RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put), - .mem_server_response_get(mem_model$mem_server_response_get), - .RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get)); - - // submodule soc_top - mkSoC_Top soc_top(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(soc_top$put_from_console_put), - .set_verbosity_logdelay(soc_top$set_verbosity_logdelay), - .set_verbosity_verbosity(soc_top$set_verbosity_verbosity), - .set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost), - .to_raw_mem_response_put(soc_top$to_raw_mem_response_put), - .EN_set_verbosity(soc_top$EN_set_verbosity), - .EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put), - .EN_get_to_console_get(soc_top$EN_get_to_console_get), - .EN_put_from_console_put(soc_top$EN_put_from_console_put), - .EN_set_watch_tohost(soc_top$EN_set_watch_tohost), - .RDY_set_verbosity(), - .to_raw_mem_request_get(soc_top$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put), - .get_to_console_get(soc_top$get_to_console_get), - .RDY_get_to_console_get(soc_top$RDY_get_to_console_get), - .RDY_put_from_console_put(soc_top$RDY_put_from_console_put), - .status(soc_top$status), - .RDY_set_watch_tohost()); - - // rule RL_rl_terminate - assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ; - assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ; - - // rule RL_rl_step0 - assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ; - assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ; - - // rule RL_rl_relay_console_out - assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - - // rule RL_rl_relay_console_in - assign CAN_FIRE_RL_rl_relay_console_in = - rg_console_in_poll != 12'd0 || soc_top$RDY_put_from_console_put ; - assign WILL_FIRE_RL_rl_relay_console_in = CAN_FIRE_RL_rl_relay_console_in ; - - // rule RL_memCnx_ClientServerRequest - assign CAN_FIRE_RL_memCnx_ClientServerRequest = - soc_top$RDY_to_raw_mem_request_get && - mem_model$RDY_mem_server_request_put ; - assign WILL_FIRE_RL_memCnx_ClientServerRequest = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - - // rule RL_memCnx_ClientServerResponse - assign CAN_FIRE_RL_memCnx_ClientServerResponse = - soc_top$RDY_to_raw_mem_response_put && - mem_model$RDY_mem_server_response_get ; - assign WILL_FIRE_RL_memCnx_ClientServerResponse = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // register rg_banner_printed - assign rg_banner_printed$D_IN = 1'd1 ; - assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ; - - // register rg_console_in_poll - assign rg_console_in_poll$D_IN = rg_console_in_poll + 12'd1 ; - assign rg_console_in_poll$EN = CAN_FIRE_RL_rl_relay_console_in ; - - // submodule mem_model - assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ; - assign mem_model$EN_mem_server_request_put = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign mem_model$EN_mem_server_response_get = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // submodule soc_top - assign soc_top$put_from_console_put = v__h941 ; - assign soc_top$set_verbosity_logdelay = 64'd0 ; - assign soc_top$set_verbosity_verbosity = - TASK_testplusargs___d11 ? - 4'd2 : - (TASK_testplusargs___d12 ? 4'd1 : 4'd0) ; - assign soc_top$set_watch_tohost_tohost_addr = tohost_addr__h571 ; - assign soc_top$set_watch_tohost_watch_tohost = TASK_testplusargs___d15 ; - assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ; - assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ; - assign soc_top$EN_to_raw_mem_request_get = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign soc_top$EN_to_raw_mem_response_put = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ; - assign soc_top$EN_put_from_console_put = - WILL_FIRE_RL_rl_relay_console_in && - rg_console_in_poll == 12'd0 && - v__h941 != 8'd0 ; - assign soc_top$EN_set_watch_tohost = CAN_FIRE_RL_rl_step0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_banner_printed$EN) - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN; - if (rg_console_in_poll$EN) - rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY rg_console_in_poll$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_banner_printed = 1'h0; - rg_console_in_poll = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h702 = $stime; - #0; - end - v__h696 = v__h702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $display("%0d: %m:.rl_terminate: soc_top status is 0x%0h (= 0d%0d)", - v__h696, - soc_top$status, - soc_top$status); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h743 = $stime; - #0; - end - v__h737 = v__h743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $imported_c_end_timing({ 32'd0, v__h737 }); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Bluespec RISC-V standalone system simulation v1.2"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d12 = $test$plusargs("v1"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d11 = $test$plusargs("v2"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d15 = $test$plusargs("tohost"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - tohost_addr__h571 = $imported_c_get_symbol_val("tohost"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("INFO: watch_tohost = %0d, tohost_addr = 0x%0h", - TASK_testplusargs___d15, - tohost_addr__h571); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - v__h633 = $stime; - #0; - end - v__h627 = v__h633 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) $imported_c_start_timing({ 32'd0, v__h627 }); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) - $write("%c", soc_top$get_to_console_get); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_relay_console_in && rg_console_in_poll == 12'd0) - begin - v__h941 = $imported_c_trygetchar(8'hAA); - #0; - end - end - // synopsys translate_on -endmodule // mkTop_HW_Side - diff --git a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkUART.v b/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkUART.v deleted file mode 100644 index 033775ea..00000000 --- a/builds/RV32ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkUART.v +++ /dev/null @@ -1,2925 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// intr O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// put_from_console_put I 8 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_put_from_console_put I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkUART(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - intr); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method intr - output intr; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [7 : 0] get_to_console_get; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - intr, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register cfg_verbosity - reg [7 : 0] cfg_verbosity; - wire [7 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_dll - reg [7 : 0] rg_dll; - wire [7 : 0] rg_dll$D_IN; - wire rg_dll$EN; - - // register rg_dlm - reg [7 : 0] rg_dlm; - wire [7 : 0] rg_dlm$D_IN; - wire rg_dlm$EN; - - // register rg_fcr - reg [7 : 0] rg_fcr; - wire [7 : 0] rg_fcr$D_IN; - wire rg_fcr$EN; - - // register rg_ier - reg [7 : 0] rg_ier; - wire [7 : 0] rg_ier$D_IN; - wire rg_ier$EN; - - // register rg_lcr - reg [7 : 0] rg_lcr; - wire [7 : 0] rg_lcr$D_IN; - wire rg_lcr$EN; - - // register rg_lsr - reg [7 : 0] rg_lsr; - reg [7 : 0] rg_lsr$D_IN; - wire rg_lsr$EN; - - // register rg_mcr - reg [7 : 0] rg_mcr; - wire [7 : 0] rg_mcr$D_IN; - wire rg_mcr$EN; - - // register rg_msr - reg [7 : 0] rg_msr; - wire [7 : 0] rg_msr$D_IN; - wire rg_msr$EN; - - // register rg_rbr - reg [7 : 0] rg_rbr; - wire [7 : 0] rg_rbr$D_IN; - wire rg_rbr$EN; - - // register rg_scr - reg [7 : 0] rg_scr; - wire [7 : 0] rg_scr$D_IN; - wire rg_scr$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_thr - reg [7 : 0] rg_thr; - wire [7 : 0] rg_thr$D_IN; - wire rg_thr$EN; - - // ports of submodule f_from_console - wire [7 : 0] f_from_console$D_IN, f_from_console$D_OUT; - wire f_from_console$CLR, - f_from_console$DEQ, - f_from_console$EMPTY_N, - f_from_console$ENQ, - f_from_console$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_to_console - wire [7 : 0] f_to_console$D_IN, f_to_console$D_OUT; - wire f_to_console$CLR, - f_to_console$DEQ, - f_to_console$EMPTY_N, - f_to_console$ENQ, - f_to_console$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_receive, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_receive, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_rg_lsr$write_1__VAL_3; - wire MUX_rg_lsr$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2519; - reg [31 : 0] v__h2187; - reg [31 : 0] v__h2025; - reg [31 : 0] v__h2898; - reg [31 : 0] v__h3244; - reg [31 : 0] v__h4006; - reg [31 : 0] v__h3449; - reg [31 : 0] v__h4306; - reg [31 : 0] v__h4749; - reg [31 : 0] v__h4859; - reg [31 : 0] v__h1811; - reg [31 : 0] v__h1805; - reg [31 : 0] v__h2019; - reg [31 : 0] v__h2181; - reg [31 : 0] v__h2513; - reg [31 : 0] v__h2892; - reg [31 : 0] v__h3238; - reg [31 : 0] v__h3443; - reg [31 : 0] v__h4000; - reg [31 : 0] v__h4300; - reg [31 : 0] v__h4743; - reg [31 : 0] v__h4853; - // synopsys translate_on - - // remaining internal signals - reg [7 : 0] y_avValue_snd__h2683; - wire [63 : 0] rdata__h2759, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133; - wire [7 : 0] fn_iir__h1356, - new_lsr__h4516, - x__h2797, - y_avValue_snd__h2696, - y_avValue_snd__h2709, - y_avValue_snd__h2724, - y_avValue_snd__h2738; - wire [1 : 0] rdr_rresp__h2792, - v__h3147, - v__h3395, - v__h3575, - y_avValue_fst__h2737, - y_avValue_fst__h2751; - wire NOT_cfg_verbosity_read_ULE_1_24___d125, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188, - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method get_to_console_get - assign get_to_console_get = f_to_console$D_OUT ; - assign RDY_get_to_console_get = f_to_console$EMPTY_N ; - assign CAN_FIRE_get_to_console_get = f_to_console$EMPTY_N ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = f_from_console$FULL_N ; - assign CAN_FIRE_put_from_console_put = f_from_console$FULL_N ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method intr - assign intr = !fn_iir__h1356[0] ; - - // submodule f_from_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_from_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_from_console$D_IN), - .ENQ(f_from_console$ENQ), - .DEQ(f_from_console$DEQ), - .CLR(f_from_console$CLR), - .D_OUT(f_from_console$D_OUT), - .FULL_N(f_from_console$FULL_N), - .EMPTY_N(f_from_console$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_to_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_to_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_to_console$D_IN), - .ENQ(f_to_console$ENQ), - .DEQ(f_to_console$DEQ), - .CLR(f_to_console$CLR), - .D_OUT(f_to_console$D_OUT), - .FULL_N(f_to_console$FULL_N), - .EMPTY_N(f_to_console$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 && - rg_state ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_receive - assign CAN_FIRE_RL_rl_receive = f_from_console$EMPTY_N && !rg_lsr[0] ; - assign WILL_FIRE_RL_rl_receive = - CAN_FIRE_RL_rl_receive && !WILL_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_rg_lsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 ; - assign MUX_rg_lsr$write_1__VAL_3 = { rg_lsr[7:1], 1'd0 } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 8'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_dll - assign rg_dll$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dll$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 || - WILL_FIRE_RL_rl_reset ; - - // register rg_dlm - assign rg_dlm$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dlm$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 || - WILL_FIRE_RL_rl_reset ; - - // register rg_fcr - assign rg_fcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_fcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h2 || - WILL_FIRE_RL_rl_reset ; - - // register rg_ier - assign rg_ier$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_ier$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lcr - assign rg_lcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_lcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h3 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lsr - always@(WILL_FIRE_RL_rl_reset or - WILL_FIRE_RL_rl_receive or - new_lsr__h4516 or - MUX_rg_lsr$write_1__SEL_3 or MUX_rg_lsr$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset: rg_lsr$D_IN = 8'd96; - WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h4516; - MUX_rg_lsr$write_1__SEL_3: rg_lsr$D_IN = MUX_rg_lsr$write_1__VAL_3; - default: rg_lsr$D_IN = 8'b10101010 /* unspecified value */ ; - endcase - assign rg_lsr$EN = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 || - WILL_FIRE_RL_rl_receive || - WILL_FIRE_RL_rl_reset ; - - // register rg_mcr - assign rg_mcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_mcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h4 || - WILL_FIRE_RL_rl_reset ; - - // register rg_msr - assign rg_msr$D_IN = 8'd0 ; - assign rg_msr$EN = CAN_FIRE_RL_rl_reset ; - - // register rg_rbr - assign rg_rbr$D_IN = f_from_console$D_OUT ; - assign rg_rbr$EN = WILL_FIRE_RL_rl_receive ; - - // register rg_scr - assign rg_scr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_scr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h7 || - WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = 1'd1 ; - assign rg_state$EN = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // register rg_thr - assign rg_thr$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_thr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - - // submodule f_from_console - assign f_from_console$D_IN = put_from_console_put ; - assign f_from_console$ENQ = EN_put_from_console_put ; - assign f_from_console$DEQ = WILL_FIRE_RL_rl_receive ; - assign f_from_console$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_to_console - assign f_to_console$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign f_to_console$ENQ = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - assign f_to_console$DEQ = EN_get_to_console_get ; - assign f_to_console$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h2759, - rdr_rresp__h2792, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3147 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_24___d125 = cfg_verbosity > 8'd1 ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - slave_xactor_f_wr_data$D_OUT[0] ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - !slave_xactor_f_wr_data$D_OUT[0] ; - assign fn_iir__h1356 = - (rg_ier[0] && rg_lsr[0]) ? 8'h04 : (rg_ier[1] ? 8'h02 : 8'd0) ; - assign new_lsr__h4516 = { rg_lsr[7:1], 1'd1 } ; - assign rdata__h2759 = { 56'd0, x__h2797 } ; - assign rdr_rresp__h2792 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0) ? - y_avValue_fst__h2751 : - 2'b10 ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 = - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - rg_lcr[7] ; - assign slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 = - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1] || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7] || - f_to_console$FULL_N) ; - assign v__h3147 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) ? - 2'b10 : - v__h3395 ; - assign v__h3395 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0) ? - v__h3575 : - 2'b11 ; - assign v__h3575 = y_avValue_fst__h2737 ; - assign x__h2797 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0 || - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) ? - 8'd0 : - y_avValue_snd__h2738 ; - assign y_avValue_fst__h2737 = 2'b0 ; - assign y_avValue_fst__h2751 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0) ? - y_avValue_fst__h2737 : - 2'b11 ; - assign y_avValue_snd__h2696 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - rg_lcr[7]) ? - rg_dlm : - y_avValue_snd__h2683 ; - assign y_avValue_snd__h2709 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - !rg_lcr[7]) ? - rg_ier : - y_avValue_snd__h2696 ; - assign y_avValue_snd__h2724 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - rg_lcr[7]) ? - rg_dll : - y_avValue_snd__h2709 ; - assign y_avValue_snd__h2738 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7]) ? - rg_rbr : - y_avValue_snd__h2724 ; - always@(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 or - fn_iir__h1356 or rg_lcr or rg_mcr or rg_lsr or rg_msr or rg_scr) - begin - case (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3]) - 3'h2: y_avValue_snd__h2683 = fn_iir__h1356; - 3'h3: y_avValue_snd__h2683 = rg_lcr; - 3'h4: y_avValue_snd__h2683 = rg_mcr; - 3'h5: y_avValue_snd__h2683 = rg_lsr; - 3'h6: y_avValue_snd__h2683 = rg_msr; - 3'h7: y_avValue_snd__h2683 = rg_scr; - default: y_avValue_snd__h2683 = 8'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dll <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dlm <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_fcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_ier <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lsr <= `BSV_ASSIGNMENT_DELAY 8'd96; - rg_mcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_msr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_scr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_dll$EN) rg_dll <= `BSV_ASSIGNMENT_DELAY rg_dll$D_IN; - if (rg_dlm$EN) rg_dlm <= `BSV_ASSIGNMENT_DELAY rg_dlm$D_IN; - if (rg_fcr$EN) rg_fcr <= `BSV_ASSIGNMENT_DELAY rg_fcr$D_IN; - if (rg_ier$EN) rg_ier <= `BSV_ASSIGNMENT_DELAY rg_ier$D_IN; - if (rg_lcr$EN) rg_lcr <= `BSV_ASSIGNMENT_DELAY rg_lcr$D_IN; - if (rg_lsr$EN) rg_lsr <= `BSV_ASSIGNMENT_DELAY rg_lsr$D_IN; - if (rg_mcr$EN) rg_mcr <= `BSV_ASSIGNMENT_DELAY rg_mcr$D_IN; - if (rg_msr$EN) rg_msr <= `BSV_ASSIGNMENT_DELAY rg_msr$D_IN; - if (rg_scr$EN) rg_scr <= `BSV_ASSIGNMENT_DELAY rg_scr$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_rbr$EN) rg_rbr <= `BSV_ASSIGNMENT_DELAY rg_rbr$D_IN; - if (rg_thr$EN) rg_thr <= `BSV_ASSIGNMENT_DELAY rg_thr$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 8'hAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_dll = 8'hAA; - rg_dlm = 8'hAA; - rg_fcr = 8'hAA; - rg_ier = 8'hAA; - rg_lcr = 8'hAA; - rg_lsr = 8'hAA; - rg_mcr = 8'hAA; - rg_msr = 8'hAA; - rg_rbr = 8'hAA; - rg_scr = 8'hAA; - rg_state = 1'h0; - rg_thr = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - begin - v__h2519 = $stime; - #0; - end - v__h2513 = v__h2519 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2513); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - begin - v__h2187 = $stime; - #0; - end - v__h2181 = v__h2187 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2181); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - begin - v__h2025 = $stime; - #0; - end - v__h2019 = v__h2025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: misaligned addr", - v__h2019); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h2898 = $stime; - #0; - end - v__h2892 = v__h2898 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_rd_req", v__h2892); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdata__h2759); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdr_rresp__h2792); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - begin - v__h3244 = $stime; - #0; - end - v__h3238 = v__h3244 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $display("%0d: ERROR: UART.rl_process_wr_req: misaligned addr", - v__h3238); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - begin - v__h4006 = $stime; - #0; - end - v__h4000 = v__h4006 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h4000); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - begin - v__h3449 = $stime; - #0; - end - v__h3443 = v__h3449 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h3443); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h4306 = $stime; - #0; - end - v__h4300 = v__h4306 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_wr_req", v__h4300); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", v__h3147); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h4749 = $stime; - #0; - end - v__h4743 = v__h4749 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_base 0x%0h is not 8-Byte-aligned", - v__h4743, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h4859 = $stime; - #0; - end - v__h4853 = v__h4859 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_lim 0x%0h is not 8-Byte-aligned", - v__h4853, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_receive && NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("UART_Model.rl_receive: received char 0x%0h; new_lsr = 0x%0h", - f_from_console$D_OUT, - new_lsr__h4516); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - begin - v__h1811 = $stime; - #0; - end - v__h1805 = v__h1811 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - $display("%0d: UART.rl_reset", v__h1805); - end - // synopsys translate_on -endmodule // mkUART - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v deleted file mode 100644 index 1cb3bfa4..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v +++ /dev/null @@ -1,1415 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// from_master_awready O 1 reg -// from_master_wready O 1 reg -// from_master_bvalid O 1 reg -// from_master_bid O 4 reg -// from_master_bresp O 2 reg -// from_master_arready O 1 reg -// from_master_rvalid O 1 reg -// from_master_rid O 4 reg -// from_master_rdata O 64 reg -// from_master_rresp O 2 reg -// from_master_rlast O 1 reg -// to_slave_awvalid O 1 reg -// to_slave_awid O 4 reg -// to_slave_awaddr O 64 reg -// to_slave_awlen O 8 reg -// to_slave_awsize O 3 reg -// to_slave_awburst O 2 reg -// to_slave_awlock O 1 reg -// to_slave_awcache O 4 reg -// to_slave_awprot O 3 reg -// to_slave_awqos O 4 reg -// to_slave_awregion O 4 reg -// to_slave_wvalid O 1 reg -// to_slave_wid O 4 reg -// to_slave_wdata O 64 reg -// to_slave_wstrb O 8 reg -// to_slave_wlast O 1 reg -// to_slave_bready O 1 reg -// to_slave_arvalid O 1 reg -// to_slave_arid O 4 reg -// to_slave_araddr O 64 reg -// to_slave_arlen O 8 reg -// to_slave_arsize O 3 reg -// to_slave_arburst O 2 reg -// to_slave_arlock O 1 reg -// to_slave_arcache O 4 reg -// to_slave_arprot O 3 reg -// to_slave_arqos O 4 reg -// to_slave_arregion O 4 reg -// to_slave_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// from_master_awvalid I 1 -// from_master_awid I 4 reg -// from_master_awaddr I 64 reg -// from_master_awlen I 8 reg -// from_master_awsize I 3 reg -// from_master_awburst I 2 reg -// from_master_awlock I 1 reg -// from_master_awcache I 4 reg -// from_master_awprot I 3 reg -// from_master_awqos I 4 reg -// from_master_awregion I 4 reg -// from_master_wvalid I 1 -// from_master_wid I 4 reg -// from_master_wdata I 64 reg -// from_master_wstrb I 8 reg -// from_master_wlast I 1 reg -// from_master_bready I 1 -// from_master_arvalid I 1 -// from_master_arid I 4 reg -// from_master_araddr I 64 reg -// from_master_arlen I 8 reg -// from_master_arsize I 3 reg -// from_master_arburst I 2 reg -// from_master_arlock I 1 reg -// from_master_arcache I 4 reg -// from_master_arprot I 3 reg -// from_master_arqos I 4 reg -// from_master_arregion I 4 reg -// from_master_rready I 1 -// to_slave_awready I 1 -// to_slave_wready I 1 -// to_slave_bvalid I 1 -// to_slave_bid I 4 reg -// to_slave_bresp I 2 reg -// to_slave_arready I 1 -// to_slave_rvalid I 1 -// to_slave_rid I 4 reg -// to_slave_rdata I 64 reg -// to_slave_rresp I 2 reg -// to_slave_rlast I 1 reg -// EN_reset I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkAXI4_Deburster_A(CLK, - RST_N, - - EN_reset, - RDY_reset, - - from_master_awvalid, - from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion, - - from_master_awready, - - from_master_wvalid, - from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast, - - from_master_wready, - - from_master_bvalid, - - from_master_bid, - - from_master_bresp, - - from_master_bready, - - from_master_arvalid, - from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion, - - from_master_arready, - - from_master_rvalid, - - from_master_rid, - - from_master_rdata, - - from_master_rresp, - - from_master_rlast, - - from_master_rready, - - to_slave_awvalid, - - to_slave_awid, - - to_slave_awaddr, - - to_slave_awlen, - - to_slave_awsize, - - to_slave_awburst, - - to_slave_awlock, - - to_slave_awcache, - - to_slave_awprot, - - to_slave_awqos, - - to_slave_awregion, - - to_slave_awready, - - to_slave_wvalid, - - to_slave_wid, - - to_slave_wdata, - - to_slave_wstrb, - - to_slave_wlast, - - to_slave_wready, - - to_slave_bvalid, - to_slave_bid, - to_slave_bresp, - - to_slave_bready, - - to_slave_arvalid, - - to_slave_arid, - - to_slave_araddr, - - to_slave_arlen, - - to_slave_arsize, - - to_slave_arburst, - - to_slave_arlock, - - to_slave_arcache, - - to_slave_arprot, - - to_slave_arqos, - - to_slave_arregion, - - to_slave_arready, - - to_slave_rvalid, - to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast, - - to_slave_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method from_master_m_awvalid - input from_master_awvalid; - input [3 : 0] from_master_awid; - input [63 : 0] from_master_awaddr; - input [7 : 0] from_master_awlen; - input [2 : 0] from_master_awsize; - input [1 : 0] from_master_awburst; - input from_master_awlock; - input [3 : 0] from_master_awcache; - input [2 : 0] from_master_awprot; - input [3 : 0] from_master_awqos; - input [3 : 0] from_master_awregion; - - // value method from_master_m_awready - output from_master_awready; - - // action method from_master_m_wvalid - input from_master_wvalid; - input [3 : 0] from_master_wid; - input [63 : 0] from_master_wdata; - input [7 : 0] from_master_wstrb; - input from_master_wlast; - - // value method from_master_m_wready - output from_master_wready; - - // value method from_master_m_bvalid - output from_master_bvalid; - - // value method from_master_m_bid - output [3 : 0] from_master_bid; - - // value method from_master_m_bresp - output [1 : 0] from_master_bresp; - - // value method from_master_m_buser - - // action method from_master_m_bready - input from_master_bready; - - // action method from_master_m_arvalid - input from_master_arvalid; - input [3 : 0] from_master_arid; - input [63 : 0] from_master_araddr; - input [7 : 0] from_master_arlen; - input [2 : 0] from_master_arsize; - input [1 : 0] from_master_arburst; - input from_master_arlock; - input [3 : 0] from_master_arcache; - input [2 : 0] from_master_arprot; - input [3 : 0] from_master_arqos; - input [3 : 0] from_master_arregion; - - // value method from_master_m_arready - output from_master_arready; - - // value method from_master_m_rvalid - output from_master_rvalid; - - // value method from_master_m_rid - output [3 : 0] from_master_rid; - - // value method from_master_m_rdata - output [63 : 0] from_master_rdata; - - // value method from_master_m_rresp - output [1 : 0] from_master_rresp; - - // value method from_master_m_rlast - output from_master_rlast; - - // value method from_master_m_ruser - - // action method from_master_m_rready - input from_master_rready; - - // value method to_slave_m_awvalid - output to_slave_awvalid; - - // value method to_slave_m_awid - output [3 : 0] to_slave_awid; - - // value method to_slave_m_awaddr - output [63 : 0] to_slave_awaddr; - - // value method to_slave_m_awlen - output [7 : 0] to_slave_awlen; - - // value method to_slave_m_awsize - output [2 : 0] to_slave_awsize; - - // value method to_slave_m_awburst - output [1 : 0] to_slave_awburst; - - // value method to_slave_m_awlock - output to_slave_awlock; - - // value method to_slave_m_awcache - output [3 : 0] to_slave_awcache; - - // value method to_slave_m_awprot - output [2 : 0] to_slave_awprot; - - // value method to_slave_m_awqos - output [3 : 0] to_slave_awqos; - - // value method to_slave_m_awregion - output [3 : 0] to_slave_awregion; - - // value method to_slave_m_awuser - - // action method to_slave_m_awready - input to_slave_awready; - - // value method to_slave_m_wvalid - output to_slave_wvalid; - - // value method to_slave_m_wid - output [3 : 0] to_slave_wid; - - // value method to_slave_m_wdata - output [63 : 0] to_slave_wdata; - - // value method to_slave_m_wstrb - output [7 : 0] to_slave_wstrb; - - // value method to_slave_m_wlast - output to_slave_wlast; - - // value method to_slave_m_wuser - - // action method to_slave_m_wready - input to_slave_wready; - - // action method to_slave_m_bvalid - input to_slave_bvalid; - input [3 : 0] to_slave_bid; - input [1 : 0] to_slave_bresp; - - // value method to_slave_m_bready - output to_slave_bready; - - // value method to_slave_m_arvalid - output to_slave_arvalid; - - // value method to_slave_m_arid - output [3 : 0] to_slave_arid; - - // value method to_slave_m_araddr - output [63 : 0] to_slave_araddr; - - // value method to_slave_m_arlen - output [7 : 0] to_slave_arlen; - - // value method to_slave_m_arsize - output [2 : 0] to_slave_arsize; - - // value method to_slave_m_arburst - output [1 : 0] to_slave_arburst; - - // value method to_slave_m_arlock - output to_slave_arlock; - - // value method to_slave_m_arcache - output [3 : 0] to_slave_arcache; - - // value method to_slave_m_arprot - output [2 : 0] to_slave_arprot; - - // value method to_slave_m_arqos - output [3 : 0] to_slave_arqos; - - // value method to_slave_m_arregion - output [3 : 0] to_slave_arregion; - - // value method to_slave_m_aruser - - // action method to_slave_m_arready - input to_slave_arready; - - // action method to_slave_m_rvalid - input to_slave_rvalid; - input [3 : 0] to_slave_rid; - input [63 : 0] to_slave_rdata; - input [1 : 0] to_slave_rresp; - input to_slave_rlast; - - // value method to_slave_m_rready - output to_slave_rready; - - // signals for module outputs - wire [63 : 0] from_master_rdata, - to_slave_araddr, - to_slave_awaddr, - to_slave_wdata; - wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb; - wire [3 : 0] from_master_bid, - from_master_rid, - to_slave_arcache, - to_slave_arid, - to_slave_arqos, - to_slave_arregion, - to_slave_awcache, - to_slave_awid, - to_slave_awqos, - to_slave_awregion, - to_slave_wid; - wire [2 : 0] to_slave_arprot, - to_slave_arsize, - to_slave_awprot, - to_slave_awsize; - wire [1 : 0] from_master_bresp, - from_master_rresp, - to_slave_arburst, - to_slave_awburst; - wire RDY_reset, - from_master_arready, - from_master_awready, - from_master_bvalid, - from_master_rlast, - from_master_rvalid, - from_master_wready, - to_slave_arlock, - to_slave_arvalid, - to_slave_awlock, - to_slave_awvalid, - to_slave_bready, - to_slave_rready, - to_slave_wlast, - to_slave_wvalid; - - // register m_rg_ar_beat_count - reg [7 : 0] m_rg_ar_beat_count; - wire [7 : 0] m_rg_ar_beat_count$D_IN; - wire m_rg_ar_beat_count$EN; - - // register m_rg_b_beat_count - reg [7 : 0] m_rg_b_beat_count; - wire [7 : 0] m_rg_b_beat_count$D_IN; - wire m_rg_b_beat_count$EN; - - // register m_rg_b_resp - reg [1 : 0] m_rg_b_resp; - wire [1 : 0] m_rg_b_resp$D_IN; - wire m_rg_b_resp$EN; - - // register m_rg_r_beat_count - reg [7 : 0] m_rg_r_beat_count; - wire [7 : 0] m_rg_r_beat_count$D_IN; - wire m_rg_r_beat_count$EN; - - // register m_rg_reset - reg m_rg_reset; - wire m_rg_reset$D_IN, m_rg_reset$EN; - - // register m_rg_w_beat_count - reg [7 : 0] m_rg_w_beat_count; - wire [7 : 0] m_rg_w_beat_count$D_IN; - wire m_rg_w_beat_count$EN; - - // ports of submodule m_f_r_arlen - wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT; - wire m_f_r_arlen$CLR, - m_f_r_arlen$DEQ, - m_f_r_arlen$EMPTY_N, - m_f_r_arlen$ENQ, - m_f_r_arlen$FULL_N; - - // ports of submodule m_f_w_awlen - wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT; - wire m_f_w_awlen$CLR, - m_f_w_awlen$DEQ, - m_f_w_awlen$EMPTY_N, - m_f_w_awlen$ENQ, - m_f_w_awlen$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_addr - wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN, - m_xactor_from_master_f_rd_addr$D_OUT; - wire m_xactor_from_master_f_rd_addr$CLR, - m_xactor_from_master_f_rd_addr$DEQ, - m_xactor_from_master_f_rd_addr$EMPTY_N, - m_xactor_from_master_f_rd_addr$ENQ, - m_xactor_from_master_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_data - wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN, - m_xactor_from_master_f_rd_data$D_OUT; - wire m_xactor_from_master_f_rd_data$CLR, - m_xactor_from_master_f_rd_data$DEQ, - m_xactor_from_master_f_rd_data$EMPTY_N, - m_xactor_from_master_f_rd_data$ENQ, - m_xactor_from_master_f_rd_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_addr - wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN, - m_xactor_from_master_f_wr_addr$D_OUT; - wire m_xactor_from_master_f_wr_addr$CLR, - m_xactor_from_master_f_wr_addr$DEQ, - m_xactor_from_master_f_wr_addr$EMPTY_N, - m_xactor_from_master_f_wr_addr$ENQ, - m_xactor_from_master_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_data - wire [76 : 0] m_xactor_from_master_f_wr_data$D_IN, - m_xactor_from_master_f_wr_data$D_OUT; - wire m_xactor_from_master_f_wr_data$CLR, - m_xactor_from_master_f_wr_data$DEQ, - m_xactor_from_master_f_wr_data$EMPTY_N, - m_xactor_from_master_f_wr_data$ENQ, - m_xactor_from_master_f_wr_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_resp - wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN, - m_xactor_from_master_f_wr_resp$D_OUT; - wire m_xactor_from_master_f_wr_resp$CLR, - m_xactor_from_master_f_wr_resp$DEQ, - m_xactor_from_master_f_wr_resp$EMPTY_N, - m_xactor_from_master_f_wr_resp$ENQ, - m_xactor_from_master_f_wr_resp$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_addr - wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN, - m_xactor_to_slave_f_rd_addr$D_OUT; - wire m_xactor_to_slave_f_rd_addr$CLR, - m_xactor_to_slave_f_rd_addr$DEQ, - m_xactor_to_slave_f_rd_addr$EMPTY_N, - m_xactor_to_slave_f_rd_addr$ENQ, - m_xactor_to_slave_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_data - wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN, - m_xactor_to_slave_f_rd_data$D_OUT; - wire m_xactor_to_slave_f_rd_data$CLR, - m_xactor_to_slave_f_rd_data$DEQ, - m_xactor_to_slave_f_rd_data$EMPTY_N, - m_xactor_to_slave_f_rd_data$ENQ, - m_xactor_to_slave_f_rd_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_addr - wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN, - m_xactor_to_slave_f_wr_addr$D_OUT; - wire m_xactor_to_slave_f_wr_addr$CLR, - m_xactor_to_slave_f_wr_addr$DEQ, - m_xactor_to_slave_f_wr_addr$EMPTY_N, - m_xactor_to_slave_f_wr_addr$ENQ, - m_xactor_to_slave_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_data - wire [76 : 0] m_xactor_to_slave_f_wr_data$D_IN, - m_xactor_to_slave_f_wr_data$D_OUT; - wire m_xactor_to_slave_f_wr_data$CLR, - m_xactor_to_slave_f_wr_data$DEQ, - m_xactor_to_slave_f_wr_data$EMPTY_N, - m_xactor_to_slave_f_wr_data$ENQ, - m_xactor_to_slave_f_wr_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_resp - wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN, - m_xactor_to_slave_f_wr_resp$D_OUT; - wire m_xactor_to_slave_f_wr_resp$CLR, - m_xactor_to_slave_f_wr_resp$DEQ, - m_xactor_to_slave_f_wr_resp$EMPTY_N, - m_xactor_to_slave_f_wr_resp$ENQ, - m_xactor_to_slave_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave, - CAN_FIRE_from_master_m_arvalid, - CAN_FIRE_from_master_m_awvalid, - CAN_FIRE_from_master_m_bready, - CAN_FIRE_from_master_m_rready, - CAN_FIRE_from_master_m_wvalid, - CAN_FIRE_reset, - CAN_FIRE_to_slave_m_arready, - CAN_FIRE_to_slave_m_awready, - CAN_FIRE_to_slave_m_bvalid, - CAN_FIRE_to_slave_m_rvalid, - CAN_FIRE_to_slave_m_wready, - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave, - WILL_FIRE_from_master_m_arvalid, - WILL_FIRE_from_master_m_awvalid, - WILL_FIRE_from_master_m_bready, - WILL_FIRE_from_master_m_rready, - WILL_FIRE_from_master_m_wvalid, - WILL_FIRE_reset, - WILL_FIRE_to_slave_m_arready, - WILL_FIRE_to_slave_m_awready, - WILL_FIRE_to_slave_m_bvalid, - WILL_FIRE_to_slave_m_rvalid, - WILL_FIRE_to_slave_m_wready; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2, - MUX_m_rg_b_beat_count$write_1__VAL_2, - MUX_m_rg_r_beat_count$write_1__VAL_2, - MUX_m_rg_w_beat_count$write_1__VAL_2; - wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2; - wire MUX_m_rg_b_resp$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2430; - reg [31 : 0] v__h1446; - reg [31 : 0] v__h1440; - reg [31 : 0] v__h2424; - // synopsys translate_on - - // remaining internal signals - wire [63 : 0] a_out_araddr__h2944, - a_out_awaddr__h1951, - addr___1__h2036, - addr___1__h3029; - wire [7 : 0] x__h2305, x__h2798, x__h3190, x__h3388; - wire m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95, - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51, - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106, - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35; - - // action method reset - assign RDY_reset = !m_rg_reset ; - assign CAN_FIRE_reset = !m_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method from_master_m_awvalid - assign CAN_FIRE_from_master_m_awvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_awvalid = 1'd1 ; - - // value method from_master_m_awready - assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ; - - // action method from_master_m_wvalid - assign CAN_FIRE_from_master_m_wvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_wvalid = 1'd1 ; - - // value method from_master_m_wready - assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ; - - // value method from_master_m_bvalid - assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ; - - // value method from_master_m_bid - assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ; - - // value method from_master_m_bresp - assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ; - - // action method from_master_m_bready - assign CAN_FIRE_from_master_m_bready = 1'd1 ; - assign WILL_FIRE_from_master_m_bready = 1'd1 ; - - // action method from_master_m_arvalid - assign CAN_FIRE_from_master_m_arvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_arvalid = 1'd1 ; - - // value method from_master_m_arready - assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ; - - // value method from_master_m_rvalid - assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ; - - // value method from_master_m_rid - assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ; - - // value method from_master_m_rdata - assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ; - - // value method from_master_m_rresp - assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ; - - // value method from_master_m_rlast - assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ; - - // action method from_master_m_rready - assign CAN_FIRE_from_master_m_rready = 1'd1 ; - assign WILL_FIRE_from_master_m_rready = 1'd1 ; - - // value method to_slave_m_awvalid - assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ; - - // value method to_slave_m_awid - assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ; - - // value method to_slave_m_awaddr - assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ; - - // value method to_slave_m_awlen - assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ; - - // value method to_slave_m_awsize - assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ; - - // value method to_slave_m_awburst - assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ; - - // value method to_slave_m_awlock - assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ; - - // value method to_slave_m_awcache - assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ; - - // value method to_slave_m_awprot - assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ; - - // value method to_slave_m_awqos - assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ; - - // value method to_slave_m_awregion - assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ; - - // action method to_slave_m_awready - assign CAN_FIRE_to_slave_m_awready = 1'd1 ; - assign WILL_FIRE_to_slave_m_awready = 1'd1 ; - - // value method to_slave_m_wvalid - assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ; - - // value method to_slave_m_wid - assign to_slave_wid = m_xactor_to_slave_f_wr_data$D_OUT[76:73] ; - - // value method to_slave_m_wdata - assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ; - - // value method to_slave_m_wstrb - assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ; - - // value method to_slave_m_wlast - assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ; - - // action method to_slave_m_wready - assign CAN_FIRE_to_slave_m_wready = 1'd1 ; - assign WILL_FIRE_to_slave_m_wready = 1'd1 ; - - // action method to_slave_m_bvalid - assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ; - - // value method to_slave_m_bready - assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ; - - // value method to_slave_m_arvalid - assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ; - - // value method to_slave_m_arid - assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ; - - // value method to_slave_m_araddr - assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ; - - // value method to_slave_m_arlen - assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ; - - // value method to_slave_m_arsize - assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ; - - // value method to_slave_m_arburst - assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ; - - // value method to_slave_m_arlock - assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ; - - // value method to_slave_m_arcache - assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ; - - // value method to_slave_m_arprot - assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ; - - // value method to_slave_m_arqos - assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ; - - // value method to_slave_m_arregion - assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ; - - // action method to_slave_m_arready - assign CAN_FIRE_to_slave_m_arready = 1'd1 ; - assign WILL_FIRE_to_slave_m_arready = 1'd1 ; - - // action method to_slave_m_rvalid - assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ; - - // value method to_slave_m_rready - assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ; - - // submodule m_f_r_arlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_r_arlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_r_arlen$D_IN), - .ENQ(m_f_r_arlen$ENQ), - .DEQ(m_f_r_arlen$DEQ), - .CLR(m_f_r_arlen$CLR), - .D_OUT(m_f_r_arlen$D_OUT), - .FULL_N(m_f_r_arlen$FULL_N), - .EMPTY_N(m_f_r_arlen$EMPTY_N)); - - // submodule m_f_w_awlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_w_awlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_w_awlen$D_IN), - .ENQ(m_f_w_awlen$ENQ), - .DEQ(m_f_w_awlen$DEQ), - .CLR(m_f_w_awlen$CLR), - .D_OUT(m_f_w_awlen$D_OUT), - .FULL_N(m_f_w_awlen$FULL_N), - .EMPTY_N(m_f_w_awlen$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_addr$D_IN), - .ENQ(m_xactor_from_master_f_rd_addr$ENQ), - .DEQ(m_xactor_from_master_f_rd_addr$DEQ), - .CLR(m_xactor_from_master_f_rd_addr$CLR), - .D_OUT(m_xactor_from_master_f_rd_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_data$D_IN), - .ENQ(m_xactor_from_master_f_rd_data$ENQ), - .DEQ(m_xactor_from_master_f_rd_data$DEQ), - .CLR(m_xactor_from_master_f_rd_data$CLR), - .D_OUT(m_xactor_from_master_f_rd_data$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_addr$D_IN), - .ENQ(m_xactor_from_master_f_wr_addr$ENQ), - .DEQ(m_xactor_from_master_f_wr_addr$DEQ), - .CLR(m_xactor_from_master_f_wr_addr$CLR), - .D_OUT(m_xactor_from_master_f_wr_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_data$D_IN), - .ENQ(m_xactor_from_master_f_wr_data$ENQ), - .DEQ(m_xactor_from_master_f_wr_data$DEQ), - .CLR(m_xactor_from_master_f_wr_data$CLR), - .D_OUT(m_xactor_from_master_f_wr_data$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_resp$D_IN), - .ENQ(m_xactor_from_master_f_wr_resp$ENQ), - .DEQ(m_xactor_from_master_f_wr_resp$DEQ), - .CLR(m_xactor_from_master_f_wr_resp$CLR), - .D_OUT(m_xactor_from_master_f_wr_resp$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_addr$D_IN), - .ENQ(m_xactor_to_slave_f_rd_addr$ENQ), - .DEQ(m_xactor_to_slave_f_rd_addr$DEQ), - .CLR(m_xactor_to_slave_f_rd_addr$CLR), - .D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_data$D_IN), - .ENQ(m_xactor_to_slave_f_rd_data$ENQ), - .DEQ(m_xactor_to_slave_f_rd_data$DEQ), - .CLR(m_xactor_to_slave_f_rd_data$CLR), - .D_OUT(m_xactor_to_slave_f_rd_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_addr$D_IN), - .ENQ(m_xactor_to_slave_f_wr_addr$ENQ), - .DEQ(m_xactor_to_slave_f_wr_addr$DEQ), - .CLR(m_xactor_to_slave_f_wr_addr$CLR), - .D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_data$D_IN), - .ENQ(m_xactor_to_slave_f_wr_data$ENQ), - .DEQ(m_xactor_to_slave_f_wr_data$DEQ), - .CLR(m_xactor_to_slave_f_wr_data$CLR), - .D_OUT(m_xactor_to_slave_f_wr_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_resp$D_IN), - .ENQ(m_xactor_to_slave_f_wr_resp$ENQ), - .DEQ(m_xactor_to_slave_f_wr_resp$DEQ), - .CLR(m_xactor_to_slave_f_wr_resp$CLR), - .D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave = - m_xactor_to_slave_f_wr_addr$FULL_N && - m_xactor_from_master_f_wr_addr$EMPTY_N && - m_xactor_to_slave_f_wr_data$FULL_N && - m_xactor_from_master_f_wr_data$EMPTY_N && - (m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - - // rule RL_m_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master = - m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N && - (m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 || - m_xactor_from_master_f_wr_resp$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - - // rule RL_m_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave = - m_xactor_to_slave_f_rd_addr$FULL_N && - m_xactor_from_master_f_rd_addr$EMPTY_N && - (m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - - // rule RL_m_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master = - m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N && - m_xactor_from_master_f_rd_data$FULL_N ; - assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ; - assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_b_resp$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - (m_rg_b_resp == 2'b0 && - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 || - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51) ; - assign MUX_m_rg_ar_beat_count$write_1__VAL_2 = - m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ? - x__h3190 : - 8'd0 ; - assign MUX_m_rg_b_beat_count$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - x__h2798 : - 8'd0 ; - assign MUX_m_rg_b_resp$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - 2'b0 ; - assign MUX_m_rg_r_beat_count$write_1__VAL_2 = - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ? - x__h3388 : - 8'd0 ; - assign MUX_m_rg_w_beat_count$write_1__VAL_2 = - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ? - x__h2305 : - 8'd0 ; - - // register m_rg_ar_beat_count - assign m_rg_ar_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ; - assign m_rg_ar_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ; - - // register m_rg_b_beat_count - assign m_rg_b_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ; - assign m_rg_b_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ; - - // register m_rg_b_resp - assign m_rg_b_resp$D_IN = - m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ; - assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ; - - // register m_rg_r_beat_count - assign m_rg_r_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ; - assign m_rg_r_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ; - - // register m_rg_reset - assign m_rg_reset$D_IN = !m_rg_reset ; - assign m_rg_reset$EN = m_rg_reset || EN_reset ; - - // register m_rg_w_beat_count - assign m_rg_w_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ; - assign m_rg_w_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ; - - // submodule m_f_r_arlen - assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_f_r_arlen$ENQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - m_rg_ar_beat_count == 8'd0 ; - assign m_f_r_arlen$DEQ = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master && - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ; - assign m_f_r_arlen$CLR = m_rg_reset ; - - // submodule m_f_w_awlen - assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign m_f_w_awlen$ENQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - m_rg_w_beat_count == 8'd0 ; - assign m_f_w_awlen$DEQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_f_w_awlen$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_addr - assign m_xactor_from_master_f_rd_addr$D_IN = - { from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion } ; - assign m_xactor_from_master_f_rd_addr$ENQ = - from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ; - assign m_xactor_from_master_f_rd_addr$DEQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - !m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ; - assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_data - assign m_xactor_from_master_f_rd_data$D_IN = - { m_xactor_to_slave_f_rd_data$D_OUT[70:1], - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 } ; - assign m_xactor_from_master_f_rd_data$ENQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_from_master_f_rd_data$DEQ = - from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ; - assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_addr - assign m_xactor_from_master_f_wr_addr$D_IN = - { from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion } ; - assign m_xactor_from_master_f_wr_addr$ENQ = - from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ; - assign m_xactor_from_master_f_wr_addr$DEQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ; - assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_data - assign m_xactor_from_master_f_wr_data$D_IN = - { from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast } ; - assign m_xactor_from_master_f_wr_data$ENQ = - from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ; - assign m_xactor_from_master_f_wr_data$DEQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_resp - assign m_xactor_from_master_f_wr_resp$D_IN = - { m_xactor_to_slave_f_wr_resp$D_OUT[5:2], - (m_rg_b_resp == 2'b0) ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - m_rg_b_resp } ; - assign m_xactor_from_master_f_wr_resp$ENQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_xactor_from_master_f_wr_resp$DEQ = - from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ; - assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_addr - assign m_xactor_to_slave_f_rd_addr$D_IN = - { m_xactor_from_master_f_rd_addr$D_OUT[96:93], - a_out_araddr__h2944, - 8'd0, - m_xactor_from_master_f_rd_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_rd_addr$ENQ = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - assign m_xactor_to_slave_f_rd_addr$DEQ = - m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ; - assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_data - assign m_xactor_to_slave_f_rd_data$D_IN = - { to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast } ; - assign m_xactor_to_slave_f_rd_data$ENQ = - to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ; - assign m_xactor_to_slave_f_rd_data$DEQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_addr - assign m_xactor_to_slave_f_wr_addr$D_IN = - { m_xactor_from_master_f_wr_addr$D_OUT[96:93], - a_out_awaddr__h1951, - 8'd0, - m_xactor_from_master_f_wr_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_wr_addr$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_addr$DEQ = - m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ; - assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_data - assign m_xactor_to_slave_f_wr_data$D_IN = - { m_xactor_from_master_f_wr_data$D_OUT[76:1], 1'd1 } ; - assign m_xactor_to_slave_f_wr_data$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_data$DEQ = - m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ; - assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_resp - assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ; - assign m_xactor_to_slave_f_wr_resp$ENQ = - to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ; - assign m_xactor_to_slave_f_wr_resp$DEQ = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ; - - // remaining internal signals - assign a_out_araddr__h2944 = - (m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h3029 : - m_xactor_from_master_f_rd_addr$D_OUT[92:29] ; - assign a_out_awaddr__h1951 = - (m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h2036 : - m_xactor_from_master_f_wr_addr$D_OUT[92:29] ; - assign addr___1__h2036 = - m_xactor_from_master_f_wr_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_w_beat_count } << - m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ; - assign addr___1__h3029 = - m_xactor_from_master_f_rd_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_ar_beat_count } << - m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ; - assign m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 = - m_rg_ar_beat_count < - m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 = - m_rg_b_beat_count < m_f_w_awlen$D_OUT ; - assign m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 = - m_rg_r_beat_count < m_f_r_arlen$D_OUT ; - assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 = - m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign x__h2305 = m_rg_w_beat_count + 8'd1 ; - assign x__h2798 = m_rg_b_beat_count + 8'd1 ; - assign x__h3190 = m_rg_ar_beat_count + 8'd1 ; - assign x__h3388 = m_rg_r_beat_count + 8'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0; - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (m_rg_ar_beat_count$EN) - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN; - if (m_rg_b_beat_count$EN) - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN; - if (m_rg_b_resp$EN) - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN; - if (m_rg_r_beat_count$EN) - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN; - if (m_rg_reset$EN) - m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN; - if (m_rg_w_beat_count$EN) - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_ar_beat_count = 8'hAA; - m_rg_b_beat_count = 8'hAA; - m_rg_b_resp = 2'h2; - m_rg_r_beat_count = 8'hAA; - m_rg_reset = 1'h0; - m_rg_w_beat_count = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - begin - v__h2430 = $stime; - #0; - end - v__h2424 = v__h2430 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", - v__h2424); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display(" WLAST not set on last data beat (awlen = %0d)", - m_xactor_from_master_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) - begin - v__h1446 = $stime; - #0; - end - v__h1440 = v__h1446 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) $display("%0d: %m::AXI4_Deburster.rl_reset", v__h1440); - end - // synopsys translate_on -endmodule // mkAXI4_Deburster_A - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v deleted file mode 100644 index 7b69d05e..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v +++ /dev/null @@ -1,2157 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkBoot_ROM(CLK, - RST_N, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready); - input CLK; - input RST_N; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_set_addr_map, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_module_ready - reg rg_module_ready; - wire rg_module_ready$D_IN, rg_module_ready$EN; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h808; - reg [31 : 0] v__h8928; - reg [31 : 0] v__h9221; - reg [31 : 0] v__h9331; - reg [31 : 0] v__h802; - reg [31 : 0] v__h8922; - reg [31 : 0] v__h9215; - reg [31 : 0] v__h9325; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] data64__h987; - reg [31 : 0] CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2; - wire [63 : 0] byte_addr__h705, rdata__h924; - wire [1 : 0] rdr_rresp__h957; - wire NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18, - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_module_ready - assign rg_module_ready$D_IN = 1'd1 ; - assign rg_module_ready$EN = EN_set_addr_map ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h924, - rdr_rresp__h957, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 ? - 2'b10 : - 2'b0 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = 1'b0 ; - - // remaining internal signals - assign NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 = - slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] || - slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ; - assign NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 = - slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] || - slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ; - assign byte_addr__h705 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign rdata__h924 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 64'd0 : - data64__h987 ; - assign rdr_rresp__h957 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 2'b10 : - 2'b0 ; - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16, - 64'd24, - 64'd56, - 64'd72, - 64'd80, - 64'd88, - 64'd200, - 64'd232, - 64'd312, - 64'd424, - 64'd448, - 64'd600, - 64'd728, - 64'd1136, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = 32'h0; - 64'd32: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h54040000; - 64'd40: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h88030000; - 64'd48: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h11000000; - 64'd64: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h50030000; - 64'd96, - 64'd112, - 64'd208, - 64'd224, - 64'd240, - 64'd432, - 64'd488, - 64'd872, - 64'd888: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h04000000; - 64'd104, 64'd120, 64'd504, 64'd792, 64'd920: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h02000000; - 64'd128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h16000000; - 64'd136: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h62626375; - 64'd144: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656B6970; - 64'd152: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65642D65; - 64'd160, - 64'd264, - 64'd280, - 64'd296, - 64'd336, - 64'd360, - 64'd384, - 64'd456, - 64'd552, - 64'd592, - 64'd608, - 64'd624, - 64'd672, - 64'd704, - 64'd760, - 64'd816, - 64'd840, - 64'd880: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h03000000; - 64'd168: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h26000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h732C7261; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7261622D; - 64'd192, - 64'd216, - 64'd400, - 64'd440, - 64'd496, - 64'd512, - 64'd584, - 64'd744, - 64'd752, - 64'd912: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h01000000; - 64'd248, 64'd896: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h80969800; - 64'd256: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40757063; - 64'd272: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h3F000000; - 64'd288, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4B000000; - 64'd304: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4F000000; - 64'd320: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h06000000; - 64'd328: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h63736972; - 64'd344: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h56000000; - 64'd352: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h75616D69; - 64'd368: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h60000000; - 64'd376: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h76732C76; - 64'd392: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69000000; - 64'd408: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70757272; - 64'd416: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F72746E; - 64'd464, 64'd632, 64'd712, 64'd824: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h1B000000; - 64'd472: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70632C76; - 64'd480: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00006374; - 64'd520: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h38407972; - 64'd528: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00303030; - 64'd536: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h07000000; - 64'd544: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D656D; - 64'd568: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000080; - 64'd576: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000010; - 64'd616: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h0F000000; - 64'd656: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69730063; - 64'd664: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7375622D; - 64'd680: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hA7000000; - 64'd688: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E696C63; - 64'd696, 64'd808: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h30303030; - 64'd720: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C632C76; - 64'd736: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h10000000; - 64'd776: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000002; - 64'd784: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000C00; - 64'd800: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h74726175; - 64'd832: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61303535; - 64'd856: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h000000C0; - 64'd864: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40000000; - 64'd904: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h08000000; - 64'd928: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h09000000; - 64'd936: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73736572; - 64'd944: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h2300736C; - 64'd952: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C65632D; - 64'd960: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61706D6F; - 64'd968: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D0065; - 64'd976: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656D6974; - 64'd984: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6572662D; - 64'd992: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h64007963; - 64'd1000: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79745F65; - 64'd1008: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73006765; - 64'd1016: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69720073; - 64'd1024: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00617369; - 64'd1032: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65707974; - 64'd1040: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h662D6B63; - 64'd1048: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79636E65; - 64'd1056, 64'd1072: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h72726574; - 64'd1064: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C6C6563; - 64'd1080: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h746E6F63; - 64'd1088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70007265; - 64'd1096: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7200656C; - 64'd1104: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E690073; - 64'd1112: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73747075; - 64'd1120: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65646E65; - 64'd1128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h68732D67; - default: CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00028067; - 64'd24: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80000000; - 64'd32: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hEDFE0DD0; - 64'd40: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h38000000; - 64'd48: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h28000000; - 64'd56, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h10000000; - 64'd64: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hCC000000; - 64'd72, - 64'd80, - 64'd104, - 64'd216, - 64'd296, - 64'd568, - 64'd576, - 64'd672, - 64'd680, - 64'd776, - 64'd784, - 64'd840, - 64'd856, - 64'd864, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = 32'h0; - 64'd88, 64'd256, 64'd688, 64'd800: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h01000000; - 64'd96, - 64'd112, - 64'd128, - 64'd208, - 64'd224, - 64'd240, - 64'd320, - 64'd432, - 64'd448, - 64'd488, - 64'd536, - 64'd736, - 64'd752, - 64'd872, - 64'd888, - 64'd904: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h03000000; - 64'd120, 64'd232, 64'd464: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0F000000; - 64'd136, 64'd328: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h1B000000; - 64'd144: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h732C7261; - 64'd152: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7261622D; - 64'd160, 64'd336: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000076; - 64'd168: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h12000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h62626375; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656B6970; - 64'd192: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000065; - 64'd200: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h73757063; - 64'd248: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C000000; - 64'd264, 64'd704, 64'd816: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000030; - 64'd272, 64'd288, 64'd392, 64'd600, 64'd616: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h04000000; - 64'd280: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00757063; - 64'd304: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h05000000; - 64'd312: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79616B6F; - 64'd344: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0A000000; - 64'd352: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h32337672; - 64'd360: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000073; - 64'd368, 64'd920: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0B000000; - 64'd376, 64'd472, 64'd720: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63736972; - 64'd384: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00003233; - 64'd400: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80969800; - 64'd408: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65746E69; - 64'd416: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F632D74; - 64'd424: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72656C6C; - 64'd440: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79000000; - 64'd456: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h8A000000; - 64'd480: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692D75; - 64'd496: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h9F000000; - 64'd504, 64'd512, 64'd584, 64'd608, 64'd624, 64'd792, 64'd928: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h02000000; - 64'd520: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6D656D; - 64'd528: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30303030; - 64'd544: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3F000000; - 64'd552: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00007972; - 64'd592: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00636F73; - 64'd632: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h21000000; - 64'd656: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F732D65; - 64'd664: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656C706D; - 64'd696: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30324074; - 64'd712: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0D000000; - 64'd728: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30746E69; - 64'd744, 64'd912: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAE000000; - 64'd760: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h07000000; - 64'd808: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30306340; - 64'd824: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h09000000; - 64'd832: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3631736E; - 64'd880: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hC2000000; - 64'd896: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h69000000; - 64'd936: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h64646123; - 64'd944: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C65632D; - 64'd952: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h657A6973; - 64'd960: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6300736C; - 64'd968: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C626974; - 64'd976: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h006C6564; - 64'd984: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65736162; - 64'd992: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E657571; - 64'd1000: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63697665; - 64'd1008: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72006570; - 64'd1016: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75746174; - 64'd1024: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C766373; - 64'd1032: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D756D6D; - 64'd1040: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6C6300; - 64'd1048: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75716572; - 64'd1056: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692300; - 64'd1064, 64'd1080: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D747075; - 64'd1072: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E690073; - 64'd1088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C6C6F72; - 64'd1096: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h646E6168; - 64'd1104: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65676E61; - 64'd1112: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72726574; - 64'd1120: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7478652D; - 64'd1128: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65720064; - 64'd1136: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00746669; - default: CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705 or - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 or - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2) - begin - case (byte_addr__h705) - 64'd0: data64__h987 = 64'h0202859300000297; - 64'd8: data64__h987 = 64'h0182A283F1402573; - default: data64__h987 = - { CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_module_ready$EN) - rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_module_ready = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - begin - v__h808 = $stime; - #0; - end - v__h802 = v__h808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", - v__h802); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - begin - v__h8928 = $stime; - #0; - end - v__h8922 = v__h8928 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", - v__h8922); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h9221 = $stime; - #0; - end - v__h9215 = v__h9221 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9215, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h9331 = $stime; - #0; - end - v__h9325 = v__h9331 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9325, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkBoot_ROM - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCPU.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCPU.v deleted file mode 100644 index 20b12b62..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCPU.v +++ /dev/null @@ -1,6045 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// hart0_server_reset_response_get O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_set_verbosity O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// hart0_server_reset_request_put I 1 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// nmi_req_set_not_clear I 1 -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// EN_hart0_server_reset_request_put I 1 -// EN_set_verbosity I 1 -// EN_hart0_server_reset_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> imem_master_rready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> dmem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCPU(CLK, - RST_N, - - hart0_server_reset_request_put, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - nmi_req_set_not_clear, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity); - input CLK; - input RST_N; - - // action method hart0_server_reset_request_put - input hart0_server_reset_request_put; - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // actionvalue method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, - RDY_set_verbosity, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - hart0_server_reset_response_get, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid; - - // register cfg_logdelay - reg [63 : 0] cfg_logdelay; - wire [63 : 0] cfg_logdelay$D_IN; - wire cfg_logdelay$EN; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register imem_rg_f3 - reg [2 : 0] imem_rg_f3; - wire [2 : 0] imem_rg_f3$D_IN; - wire imem_rg_f3$EN; - - // register imem_rg_instr_15_0 - reg [15 : 0] imem_rg_instr_15_0; - wire [15 : 0] imem_rg_instr_15_0$D_IN; - wire imem_rg_instr_15_0$EN; - - // register imem_rg_mstatus_MXR - reg imem_rg_mstatus_MXR; - wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN; - - // register imem_rg_pc - reg [31 : 0] imem_rg_pc; - reg [31 : 0] imem_rg_pc$D_IN; - wire imem_rg_pc$EN; - - // register imem_rg_priv - reg [1 : 0] imem_rg_priv; - wire [1 : 0] imem_rg_priv$D_IN; - wire imem_rg_priv$EN; - - // register imem_rg_satp - reg [31 : 0] imem_rg_satp; - wire [31 : 0] imem_rg_satp$D_IN; - wire imem_rg_satp$EN; - - // register imem_rg_sstatus_SUM - reg imem_rg_sstatus_SUM; - wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN; - - // register imem_rg_tval - reg [31 : 0] imem_rg_tval; - reg [31 : 0] imem_rg_tval$D_IN; - wire imem_rg_tval$EN; - - // register rg_cur_priv - reg [1 : 0] rg_cur_priv; - reg [1 : 0] rg_cur_priv$D_IN; - wire rg_cur_priv$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_next_pc - reg [31 : 0] rg_next_pc; - reg [31 : 0] rg_next_pc$D_IN; - wire rg_next_pc$EN; - - // register rg_run_on_reset - reg rg_run_on_reset; - wire rg_run_on_reset$D_IN, rg_run_on_reset$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_start_CPI_cycles - reg [63 : 0] rg_start_CPI_cycles; - wire [63 : 0] rg_start_CPI_cycles$D_IN; - wire rg_start_CPI_cycles$EN; - - // register rg_start_CPI_instrs - reg [63 : 0] rg_start_CPI_instrs; - wire [63 : 0] rg_start_CPI_instrs$D_IN; - wire rg_start_CPI_instrs$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register stage1_rg_full - reg stage1_rg_full; - reg stage1_rg_full$D_IN; - wire stage1_rg_full$EN; - - // register stage2_rg_full - reg stage2_rg_full; - reg stage2_rg_full$D_IN; - wire stage2_rg_full$EN; - - // register stage2_rg_resetting - reg stage2_rg_resetting; - wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN; - - // register stage2_rg_stage2 - reg [169 : 0] stage2_rg_stage2; - wire [169 : 0] stage2_rg_stage2$D_IN; - wire stage2_rg_stage2$EN; - - // register stage3_rg_full - reg stage3_rg_full; - reg stage3_rg_full$D_IN; - wire stage3_rg_full$EN; - - // register stage3_rg_stage3 - reg [103 : 0] stage3_rg_stage3; - wire [103 : 0] stage3_rg_stage3$D_IN; - wire stage3_rg_stage3$EN; - - // ports of submodule csr_regfile - reg [31 : 0] csr_regfile$csr_trap_actions_xtval; - reg [3 : 0] csr_regfile$csr_trap_actions_exc_code; - reg [1 : 0] csr_regfile$csr_ret_actions_from_priv; - wire [97 : 0] csr_regfile$csr_trap_actions; - wire [65 : 0] csr_regfile$csr_ret_actions; - wire [63 : 0] csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret; - wire [32 : 0] csr_regfile$read_csr; - wire [31 : 0] csr_regfile$csr_trap_actions_pc, - csr_regfile$mav_csr_write_word, - csr_regfile$read_mstatus, - csr_regfile$read_satp; - wire [27 : 0] csr_regfile$read_misa; - wire [11 : 0] csr_regfile$access_permitted_1_csr_addr, - csr_regfile$access_permitted_2_csr_addr, - csr_regfile$csr_counter_read_fault_csr_addr, - csr_regfile$mav_csr_write_csr_addr, - csr_regfile$mav_read_csr_csr_addr, - csr_regfile$read_csr_csr_addr, - csr_regfile$read_csr_port2_csr_addr; - wire [4 : 0] csr_regfile$interrupt_pending; - wire [1 : 0] csr_regfile$access_permitted_1_priv, - csr_regfile$access_permitted_2_priv, - csr_regfile$csr_counter_read_fault_priv, - csr_regfile$csr_trap_actions_from_priv, - csr_regfile$interrupt_pending_cur_priv; - wire csr_regfile$EN_csr_minstret_incr, - csr_regfile$EN_csr_ret_actions, - csr_regfile$EN_csr_trap_actions, - csr_regfile$EN_debug, - csr_regfile$EN_mav_csr_write, - csr_regfile$EN_mav_read_csr, - csr_regfile$EN_server_reset_request_put, - csr_regfile$EN_server_reset_response_get, - csr_regfile$RDY_server_reset_request_put, - csr_regfile$RDY_server_reset_response_get, - csr_regfile$access_permitted_1, - csr_regfile$access_permitted_1_read_not_write, - csr_regfile$access_permitted_2, - csr_regfile$access_permitted_2_read_not_write, - csr_regfile$csr_trap_actions_interrupt, - csr_regfile$csr_trap_actions_nmi, - csr_regfile$m_external_interrupt_req_set_not_clear, - csr_regfile$nmi_pending, - csr_regfile$nmi_req_set_not_clear, - csr_regfile$s_external_interrupt_req_set_not_clear, - csr_regfile$software_interrupt_req_set_not_clear, - csr_regfile$timer_interrupt_req_set_not_clear, - csr_regfile$wfi_resume; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule gpr_regfile - wire [31 : 0] gpr_regfile$read_rs1, - gpr_regfile$read_rs2, - gpr_regfile$write_rd_rd_val; - wire [4 : 0] gpr_regfile$read_rs1_port2_rs1, - gpr_regfile$read_rs1_rs1, - gpr_regfile$read_rs2_rs2, - gpr_regfile$write_rd_rd; - wire gpr_regfile$EN_server_reset_request_put, - gpr_regfile$EN_server_reset_response_get, - gpr_regfile$EN_write_rd, - gpr_regfile$RDY_server_reset_request_put, - gpr_regfile$RDY_server_reset_response_get; - - // ports of submodule near_mem - reg [31 : 0] near_mem$imem_req_addr; - reg [1 : 0] near_mem$dmem_req_op; - reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM; - wire [63 : 0] near_mem$dmem_master_araddr, - near_mem$dmem_master_awaddr, - near_mem$dmem_master_rdata, - near_mem$dmem_master_wdata, - near_mem$dmem_req_store_value, - near_mem$dmem_word64, - near_mem$imem_master_araddr, - near_mem$imem_master_awaddr, - near_mem$imem_master_rdata, - near_mem$imem_master_wdata; - wire [31 : 0] near_mem$dmem_req_addr, - near_mem$dmem_req_satp, - near_mem$imem_instr, - near_mem$imem_pc, - near_mem$imem_req_satp; - wire [7 : 0] near_mem$dmem_master_arlen, - near_mem$dmem_master_awlen, - near_mem$dmem_master_wstrb, - near_mem$imem_master_arlen, - near_mem$imem_master_awlen, - near_mem$imem_master_wstrb, - near_mem$server_fence_request_put; - wire [6 : 0] near_mem$dmem_req_amo_funct7; - wire [3 : 0] near_mem$dmem_exc_code, - near_mem$dmem_master_arcache, - near_mem$dmem_master_arid, - near_mem$dmem_master_arqos, - near_mem$dmem_master_arregion, - near_mem$dmem_master_awcache, - near_mem$dmem_master_awid, - near_mem$dmem_master_awqos, - near_mem$dmem_master_awregion, - near_mem$dmem_master_bid, - near_mem$dmem_master_rid, - near_mem$dmem_master_wid, - near_mem$imem_exc_code, - near_mem$imem_master_arcache, - near_mem$imem_master_arid, - near_mem$imem_master_arqos, - near_mem$imem_master_arregion, - near_mem$imem_master_awcache, - near_mem$imem_master_awid, - near_mem$imem_master_awqos, - near_mem$imem_master_awregion, - near_mem$imem_master_bid, - near_mem$imem_master_rid, - near_mem$imem_master_wid; - wire [2 : 0] near_mem$dmem_master_arprot, - near_mem$dmem_master_arsize, - near_mem$dmem_master_awprot, - near_mem$dmem_master_awsize, - near_mem$dmem_req_f3, - near_mem$imem_master_arprot, - near_mem$imem_master_arsize, - near_mem$imem_master_awprot, - near_mem$imem_master_awsize, - near_mem$imem_req_f3; - wire [1 : 0] near_mem$dmem_master_arburst, - near_mem$dmem_master_awburst, - near_mem$dmem_master_bresp, - near_mem$dmem_master_rresp, - near_mem$dmem_req_priv, - near_mem$imem_master_arburst, - near_mem$imem_master_awburst, - near_mem$imem_master_bresp, - near_mem$imem_master_rresp, - near_mem$imem_req_priv; - wire near_mem$EN_dmem_req, - near_mem$EN_imem_req, - near_mem$EN_server_fence_i_request_put, - near_mem$EN_server_fence_i_response_get, - near_mem$EN_server_fence_request_put, - near_mem$EN_server_fence_response_get, - near_mem$EN_server_reset_request_put, - near_mem$EN_server_reset_response_get, - near_mem$EN_sfence_vma, - near_mem$RDY_server_fence_i_request_put, - near_mem$RDY_server_fence_i_response_get, - near_mem$RDY_server_fence_request_put, - near_mem$RDY_server_fence_response_get, - near_mem$RDY_server_reset_request_put, - near_mem$RDY_server_reset_response_get, - near_mem$dmem_exc, - near_mem$dmem_master_arlock, - near_mem$dmem_master_arready, - near_mem$dmem_master_arvalid, - near_mem$dmem_master_awlock, - near_mem$dmem_master_awready, - near_mem$dmem_master_awvalid, - near_mem$dmem_master_bready, - near_mem$dmem_master_bvalid, - near_mem$dmem_master_rlast, - near_mem$dmem_master_rready, - near_mem$dmem_master_rvalid, - near_mem$dmem_master_wlast, - near_mem$dmem_master_wready, - near_mem$dmem_master_wvalid, - near_mem$dmem_req_mstatus_MXR, - near_mem$dmem_req_sstatus_SUM, - near_mem$dmem_valid, - near_mem$imem_exc, - near_mem$imem_is_i32_not_i16, - near_mem$imem_master_arlock, - near_mem$imem_master_arready, - near_mem$imem_master_arvalid, - near_mem$imem_master_awlock, - near_mem$imem_master_awready, - near_mem$imem_master_awvalid, - near_mem$imem_master_bready, - near_mem$imem_master_bvalid, - near_mem$imem_master_rlast, - near_mem$imem_master_rready, - near_mem$imem_master_rvalid, - near_mem$imem_master_wlast, - near_mem$imem_master_wready, - near_mem$imem_master_wvalid, - near_mem$imem_valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_pc_reset_value; - - // ports of submodule stage1_f_reset_reqs - wire stage1_f_reset_reqs$CLR, - stage1_f_reset_reqs$DEQ, - stage1_f_reset_reqs$EMPTY_N, - stage1_f_reset_reqs$ENQ, - stage1_f_reset_reqs$FULL_N; - - // ports of submodule stage1_f_reset_rsps - wire stage1_f_reset_rsps$CLR, - stage1_f_reset_rsps$DEQ, - stage1_f_reset_rsps$EMPTY_N, - stage1_f_reset_rsps$ENQ, - stage1_f_reset_rsps$FULL_N; - - // ports of submodule stage2_f_reset_reqs - wire stage2_f_reset_reqs$CLR, - stage2_f_reset_reqs$DEQ, - stage2_f_reset_reqs$EMPTY_N, - stage2_f_reset_reqs$ENQ, - stage2_f_reset_reqs$FULL_N; - - // ports of submodule stage2_f_reset_rsps - wire stage2_f_reset_rsps$CLR, - stage2_f_reset_rsps$DEQ, - stage2_f_reset_rsps$EMPTY_N, - stage2_f_reset_rsps$ENQ, - stage2_f_reset_rsps$FULL_N; - - // ports of submodule stage2_mbox - wire [31 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word; - wire [3 : 0] stage2_mbox$set_verbosity_verbosity; - wire [2 : 0] stage2_mbox$req_f3; - wire stage2_mbox$EN_req, - stage2_mbox$EN_req_reset, - stage2_mbox$EN_rsp_reset, - stage2_mbox$EN_set_verbosity, - stage2_mbox$req_is_OP_not_OP_32, - stage2_mbox$valid; - - // ports of submodule stage3_f_reset_reqs - wire stage3_f_reset_reqs$CLR, - stage3_f_reset_reqs$DEQ, - stage3_f_reset_reqs$EMPTY_N, - stage3_f_reset_reqs$ENQ, - stage3_f_reset_reqs$FULL_N; - - // ports of submodule stage3_f_reset_rsps - wire stage3_f_reset_rsps$CLR, - stage3_f_reset_rsps$DEQ, - stage3_f_reset_rsps$EMPTY_N, - stage3_f_reset_rsps$ENQ, - stage3_f_reset_rsps$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_imem_rl_assert_fail, - CAN_FIRE_RL_imem_rl_fetch_next_32b, - CAN_FIRE_RL_rl_WFI_resume, - CAN_FIRE_RL_rl_finish_FENCE, - CAN_FIRE_RL_rl_finish_FENCE_I, - CAN_FIRE_RL_rl_finish_SFENCE_VMA, - CAN_FIRE_RL_rl_pipe, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_RL_rl_reset_from_WFI, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_show_pipe, - CAN_FIRE_RL_rl_stage1_CSRR_S_or_C, - CAN_FIRE_RL_rl_stage1_CSRR_W, - CAN_FIRE_RL_rl_stage1_FENCE, - CAN_FIRE_RL_rl_stage1_FENCE_I, - CAN_FIRE_RL_rl_stage1_SFENCE_VMA, - CAN_FIRE_RL_rl_stage1_WFI, - CAN_FIRE_RL_rl_stage1_interrupt, - CAN_FIRE_RL_rl_stage1_restart_after_csrrx, - CAN_FIRE_RL_rl_stage1_trap, - CAN_FIRE_RL_rl_stage1_xRET, - CAN_FIRE_RL_rl_stage2_nonpipe, - CAN_FIRE_RL_rl_trap_fetch, - CAN_FIRE_RL_stage1_rl_reset, - CAN_FIRE_RL_stage2_rl_reset_begin, - CAN_FIRE_RL_stage2_rl_reset_end, - CAN_FIRE_RL_stage3_rl_reset, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_set_verbosity, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_imem_rl_assert_fail, - WILL_FIRE_RL_imem_rl_fetch_next_32b, - WILL_FIRE_RL_rl_WFI_resume, - WILL_FIRE_RL_rl_finish_FENCE, - WILL_FIRE_RL_rl_finish_FENCE_I, - WILL_FIRE_RL_rl_finish_SFENCE_VMA, - WILL_FIRE_RL_rl_pipe, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_RL_rl_reset_from_WFI, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_show_pipe, - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C, - WILL_FIRE_RL_rl_stage1_CSRR_W, - WILL_FIRE_RL_rl_stage1_FENCE, - WILL_FIRE_RL_rl_stage1_FENCE_I, - WILL_FIRE_RL_rl_stage1_SFENCE_VMA, - WILL_FIRE_RL_rl_stage1_WFI, - WILL_FIRE_RL_rl_stage1_interrupt, - WILL_FIRE_RL_rl_stage1_restart_after_csrrx, - WILL_FIRE_RL_rl_stage1_trap, - WILL_FIRE_RL_rl_stage1_xRET, - WILL_FIRE_RL_rl_stage2_nonpipe, - WILL_FIRE_RL_rl_trap_fetch, - WILL_FIRE_RL_stage1_rl_reset, - WILL_FIRE_RL_stage2_rl_reset_begin, - WILL_FIRE_RL_stage2_rl_reset_end, - WILL_FIRE_RL_stage3_rl_reset, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_set_verbosity, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - reg [31 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2; - wire [31 : 0] MUX_near_mem$imem_req_2__VAL_1, - MUX_near_mem$imem_req_2__VAL_2, - MUX_near_mem$imem_req_2__VAL_5; - wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1, - MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_3; - wire MUX_csr_regfile$mav_csr_write_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_3, - MUX_imem_rg_f3$write_1__SEL_1, - MUX_imem_rg_f3$write_1__SEL_2, - MUX_imem_rg_mstatus_MXR$write_1__SEL_4, - MUX_imem_rg_pc$write_1__SEL_4, - MUX_near_mem$imem_req_1__SEL_6, - MUX_rg_cur_priv$write_1__SEL_1, - MUX_rg_mstatus_MXR$write_1__SEL_1, - MUX_rg_next_pc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_11, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_4, - MUX_rg_state$write_1__SEL_6, - MUX_rg_state$write_1__SEL_7, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9, - MUX_stage1_rg_full$write_1__VAL_2, - MUX_stage2_rg_full$write_1__VAL_2; - - // remaining internal signals - reg [31 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936, - _theResult_____1_fst__h12725, - rs1_val__h17721, - x_out_bypass_rd_val__h5993, - x_out_data_to_stage2_addr__h11615, - x_out_data_to_stage2_val1__h11616, - x_out_data_to_stage3_rd_val__h5642; - reg [4 : 0] x_out_bypass_rd__h5992, x_out_data_to_stage3_rd__h5641; - reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q5, - CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12, - CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14, - CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13, - CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15, - CASE_theResult__280_BITS_31_TO_20_0b0_CASE_rg__ETC__q6, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744, - alu_outputs_exc_code__h12281; - reg [2 : 0] CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16, - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825; - reg [1 : 0] CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1, - CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2; - reg CASE_theResult__280_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11, - CASE_theResult__280_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9, - CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8, - CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628, - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132, - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141; - wire [127 : 0] csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1273; - wire [63 : 0] _theResult____h22285, - cpi__h22287, - cpifrac__h22288, - delta_CPI_cycles__h22283, - delta_CPI_instrs___1__h22320, - delta_CPI_instrs__h22284, - x__h22286; - wire [31 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869, - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d437, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d439, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d441, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d442, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d444, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d445, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d446, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d448, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d449, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d450, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d452, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d453, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d454, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d455, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d456, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d457, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d458, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d459, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d460, - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878, - _theResult_____1_fst__h12718, - _theResult_____1_fst__h12753, - _theResult____h4280, - _theResult___fst__h6320, - _theResult___fst__h6348, - _theResult___snd__h13851, - alu_outputs___1_addr__h11739, - alu_outputs___1_addr__h11760, - alu_outputs___1_addr__h11786, - alu_outputs___1_addr__h11981, - alu_outputs___1_addr__h12002, - alu_outputs___1_val1__h11890, - alu_outputs___1_val1__h11928, - alu_outputs___1_val1__h11944, - alu_outputs___1_val1__h11960, - alu_outputs___1_val1__h12242, - alu_outputs___1_val1__h12263, - branch_target__h11717, - data_to_stage2_addr__h11607, - fall_through_pc__h11571, - instr___1__h6153, - instr__h10038, - instr__h10231, - instr__h10348, - instr__h10526, - instr__h10645, - instr__h10740, - instr__h10876, - instr__h11012, - instr__h11148, - instr__h11486, - instr__h4278, - instr__h6420, - instr__h6565, - instr__h6757, - instr__h6952, - instr__h7181, - instr__h7524, - instr__h7914, - instr__h8030, - instr__h8095, - instr__h8412, - instr__h8750, - instr__h8934, - instr__h9063, - instr__h9500, - instr__h9672, - instr__h9845, - instr_out___1__h6290, - instr_out___1__h6322, - instr_out___1__h6350, - next_pc___1__h13393, - next_pc__h13391, - output_stage2___1_bypass_rd_val__h5981, - rd_val___1__h12706, - rd_val___1__h12714, - rd_val___1__h12721, - rd_val___1__h12728, - rd_val___1__h12735, - rd_val___1__h12742, - rd_val__h11528, - rd_val__h13747, - rd_val__h13799, - rd_val__h13821, - rd_val__h6105, - rs1_val__h17231, - rs1_val_bypassed__h4288, - rs2_val__h11713, - trap_info_tval__h13230, - val__h11530, - val__h6107, - value__h13281, - x_out_data_to_stage2_instr__h11612, - x_out_data_to_stage2_val2__h11617, - x_out_next_pc__h11584, - y__h18022; - wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288, - theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q4; - wire [19 : 0] imm20__h8802; - wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317, - theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q3; - wire [11 : 0] imm12__h10054, - imm12__h6421, - imm12__h6758, - imm12__h8674, - imm12__h9298, - imm12__h9513, - imm12__h9709, - offset__h7128, - theResult__280_BITS_31_TO_20__q17, - theResult__280_BITS_31_TO_25_CONCAT_theResult__ETC__q7; - wire [9 : 0] nzimm10__h9296, nzimm10__h9511; - wire [8 : 0] offset__h8039; - wire [7 : 0] offset__h6191; - wire [6 : 0] offset__h6700; - wire [5 : 0] imm6__h8672; - wire [4 : 0] offset_BITS_4_TO_0___h6689, - offset_BITS_4_TO_0___h7120, - rd__h6760, - rs1__h6759, - shamt__h11875, - x_out_data_to_stage2_rd__h11614; - wire [3 : 0] IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690, - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746, - IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723, - alu_outputs___1_exc_code__h12238, - cur_verbosity__h2985, - x_out_trap_info_exc_code__h13233; - wire [1 : 0] IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176, - IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112, - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118, - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180, - IF_stage2_rg_stage2_8_BITS_100_TO_96_48_EQ_0_7_ETC___d175, - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115; - wire IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653, - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270, - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464, - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466, - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564, - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1163, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1165, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1168, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1182, - NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d812, - NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d849, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d210, - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1090, - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101, - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109, - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469, - _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161, - csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1083, - csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088, - csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1094, - csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302, - csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308, - gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d949, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d952, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d955, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d958, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d961, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d964, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d967, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d970, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d973, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d976, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d979, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d982, - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d478, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1079, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685, - rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_EQ_0_ETC___d721, - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185, - rg_state_2_EQ_3_096_AND_stage3_rg_full_8_OR_NO_ETC___d1115, - stage2_f_reset_rsps_i_notEmpty__052_AND_stage3_ETC___d1061; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // actionvalue method hart0_server_reset_response_get - assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ; - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = near_mem$imem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = near_mem$imem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = near_mem$imem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = near_mem$imem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = near_mem$imem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = near_mem$imem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = near_mem$imem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = near_mem$imem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = near_mem$imem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = near_mem$imem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = near_mem$imem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = near_mem$imem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = near_mem$imem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = near_mem$imem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = near_mem$imem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = near_mem$imem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = near_mem$imem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = near_mem$imem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = near_mem$imem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = near_mem$imem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = near_mem$imem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = near_mem$imem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = near_mem$imem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = near_mem$imem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = near_mem$imem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = near_mem$imem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = near_mem$imem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = near_mem$imem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = near_mem$imem_master_rready ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = near_mem$dmem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = near_mem$dmem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = near_mem$dmem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = near_mem$dmem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = near_mem$dmem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = near_mem$dmem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = near_mem$dmem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = near_mem$dmem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = near_mem$dmem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = near_mem$dmem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = near_mem$dmem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = near_mem$dmem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = near_mem$dmem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = near_mem$dmem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = near_mem$dmem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = near_mem$dmem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = near_mem$dmem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = near_mem$dmem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = near_mem$dmem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = near_mem$dmem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = near_mem$dmem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = near_mem$dmem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = near_mem$dmem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = near_mem$dmem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = near_mem$dmem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = near_mem$dmem_master_rready ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // submodule csr_regfile - mkCSR_RegFile csr_regfile(.CLK(CLK), - .RST_N(RST_N), - .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr), - .access_permitted_1_priv(csr_regfile$access_permitted_1_priv), - .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write), - .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr), - .access_permitted_2_priv(csr_regfile$access_permitted_2_priv), - .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write), - .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr), - .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv), - .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv), - .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code), - .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv), - .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt), - .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi), - .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc), - .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval), - .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv), - .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear), - .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr), - .mav_csr_write_word(csr_regfile$mav_csr_write_word), - .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr), - .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear), - .read_csr_csr_addr(csr_regfile$read_csr_csr_addr), - .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr), - .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear), - .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear), - .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get), - .EN_mav_read_csr(csr_regfile$EN_mav_read_csr), - .EN_mav_csr_write(csr_regfile$EN_mav_csr_write), - .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions), - .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions), - .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr), - .EN_debug(csr_regfile$EN_debug), - .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get), - .read_csr(csr_regfile$read_csr), - .read_csr_port2(), - .mav_read_csr(), - .mav_csr_write(), - .read_misa(csr_regfile$read_misa), - .read_mstatus(csr_regfile$read_mstatus), - .read_ustatus(), - .read_satp(csr_regfile$read_satp), - .csr_trap_actions(csr_regfile$csr_trap_actions), - .RDY_csr_trap_actions(), - .csr_ret_actions(csr_regfile$csr_ret_actions), - .RDY_csr_ret_actions(), - .read_csr_minstret(csr_regfile$read_csr_minstret), - .read_csr_mcycle(csr_regfile$read_csr_mcycle), - .read_csr_mtime(), - .access_permitted_1(csr_regfile$access_permitted_1), - .access_permitted_2(csr_regfile$access_permitted_2), - .csr_counter_read_fault(), - .csr_mip_read(), - .interrupt_pending(csr_regfile$interrupt_pending), - .wfi_resume(csr_regfile$wfi_resume), - .nmi_pending(csr_regfile$nmi_pending), - .RDY_debug()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule gpr_regfile - mkGPR_RegFile gpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(gpr_regfile$read_rs1_rs1), - .read_rs2_rs2(gpr_regfile$read_rs2_rs2), - .write_rd_rd(gpr_regfile$write_rd_rd), - .write_rd_rd_val(gpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get), - .EN_write_rd(gpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get), - .read_rs1(gpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(gpr_regfile$read_rs2)); - - // submodule near_mem - mkNear_Mem near_mem(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(near_mem$dmem_master_arready), - .dmem_master_awready(near_mem$dmem_master_awready), - .dmem_master_bid(near_mem$dmem_master_bid), - .dmem_master_bresp(near_mem$dmem_master_bresp), - .dmem_master_bvalid(near_mem$dmem_master_bvalid), - .dmem_master_rdata(near_mem$dmem_master_rdata), - .dmem_master_rid(near_mem$dmem_master_rid), - .dmem_master_rlast(near_mem$dmem_master_rlast), - .dmem_master_rresp(near_mem$dmem_master_rresp), - .dmem_master_rvalid(near_mem$dmem_master_rvalid), - .dmem_master_wready(near_mem$dmem_master_wready), - .dmem_req_addr(near_mem$dmem_req_addr), - .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7), - .dmem_req_f3(near_mem$dmem_req_f3), - .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR), - .dmem_req_op(near_mem$dmem_req_op), - .dmem_req_priv(near_mem$dmem_req_priv), - .dmem_req_satp(near_mem$dmem_req_satp), - .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM), - .dmem_req_store_value(near_mem$dmem_req_store_value), - .imem_master_arready(near_mem$imem_master_arready), - .imem_master_awready(near_mem$imem_master_awready), - .imem_master_bid(near_mem$imem_master_bid), - .imem_master_bresp(near_mem$imem_master_bresp), - .imem_master_bvalid(near_mem$imem_master_bvalid), - .imem_master_rdata(near_mem$imem_master_rdata), - .imem_master_rid(near_mem$imem_master_rid), - .imem_master_rlast(near_mem$imem_master_rlast), - .imem_master_rresp(near_mem$imem_master_rresp), - .imem_master_rvalid(near_mem$imem_master_rvalid), - .imem_master_wready(near_mem$imem_master_wready), - .imem_req_addr(near_mem$imem_req_addr), - .imem_req_f3(near_mem$imem_req_f3), - .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR), - .imem_req_priv(near_mem$imem_req_priv), - .imem_req_satp(near_mem$imem_req_satp), - .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM), - .server_fence_request_put(near_mem$server_fence_request_put), - .EN_server_reset_request_put(near_mem$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem$EN_server_reset_response_get), - .EN_imem_req(near_mem$EN_imem_req), - .EN_dmem_req(near_mem$EN_dmem_req), - .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put), - .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get), - .EN_server_fence_request_put(near_mem$EN_server_fence_request_put), - .EN_server_fence_response_get(near_mem$EN_server_fence_response_get), - .EN_sfence_vma(near_mem$EN_sfence_vma), - .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get), - .imem_valid(near_mem$imem_valid), - .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16), - .imem_pc(near_mem$imem_pc), - .imem_instr(near_mem$imem_instr), - .imem_exc(near_mem$imem_exc), - .imem_exc_code(near_mem$imem_exc_code), - .imem_tval(), - .imem_master_awvalid(near_mem$imem_master_awvalid), - .imem_master_awid(near_mem$imem_master_awid), - .imem_master_awaddr(near_mem$imem_master_awaddr), - .imem_master_awlen(near_mem$imem_master_awlen), - .imem_master_awsize(near_mem$imem_master_awsize), - .imem_master_awburst(near_mem$imem_master_awburst), - .imem_master_awlock(near_mem$imem_master_awlock), - .imem_master_awcache(near_mem$imem_master_awcache), - .imem_master_awprot(near_mem$imem_master_awprot), - .imem_master_awqos(near_mem$imem_master_awqos), - .imem_master_awregion(near_mem$imem_master_awregion), - .imem_master_wvalid(near_mem$imem_master_wvalid), - .imem_master_wid(near_mem$imem_master_wid), - .imem_master_wdata(near_mem$imem_master_wdata), - .imem_master_wstrb(near_mem$imem_master_wstrb), - .imem_master_wlast(near_mem$imem_master_wlast), - .imem_master_bready(near_mem$imem_master_bready), - .imem_master_arvalid(near_mem$imem_master_arvalid), - .imem_master_arid(near_mem$imem_master_arid), - .imem_master_araddr(near_mem$imem_master_araddr), - .imem_master_arlen(near_mem$imem_master_arlen), - .imem_master_arsize(near_mem$imem_master_arsize), - .imem_master_arburst(near_mem$imem_master_arburst), - .imem_master_arlock(near_mem$imem_master_arlock), - .imem_master_arcache(near_mem$imem_master_arcache), - .imem_master_arprot(near_mem$imem_master_arprot), - .imem_master_arqos(near_mem$imem_master_arqos), - .imem_master_arregion(near_mem$imem_master_arregion), - .imem_master_rready(near_mem$imem_master_rready), - .dmem_valid(near_mem$dmem_valid), - .dmem_word64(near_mem$dmem_word64), - .dmem_st_amo_val(), - .dmem_exc(near_mem$dmem_exc), - .dmem_exc_code(near_mem$dmem_exc_code), - .dmem_master_awvalid(near_mem$dmem_master_awvalid), - .dmem_master_awid(near_mem$dmem_master_awid), - .dmem_master_awaddr(near_mem$dmem_master_awaddr), - .dmem_master_awlen(near_mem$dmem_master_awlen), - .dmem_master_awsize(near_mem$dmem_master_awsize), - .dmem_master_awburst(near_mem$dmem_master_awburst), - .dmem_master_awlock(near_mem$dmem_master_awlock), - .dmem_master_awcache(near_mem$dmem_master_awcache), - .dmem_master_awprot(near_mem$dmem_master_awprot), - .dmem_master_awqos(near_mem$dmem_master_awqos), - .dmem_master_awregion(near_mem$dmem_master_awregion), - .dmem_master_wvalid(near_mem$dmem_master_wvalid), - .dmem_master_wid(near_mem$dmem_master_wid), - .dmem_master_wdata(near_mem$dmem_master_wdata), - .dmem_master_wstrb(near_mem$dmem_master_wstrb), - .dmem_master_wlast(near_mem$dmem_master_wlast), - .dmem_master_bready(near_mem$dmem_master_bready), - .dmem_master_arvalid(near_mem$dmem_master_arvalid), - .dmem_master_arid(near_mem$dmem_master_arid), - .dmem_master_araddr(near_mem$dmem_master_araddr), - .dmem_master_arlen(near_mem$dmem_master_arlen), - .dmem_master_arsize(near_mem$dmem_master_arsize), - .dmem_master_arburst(near_mem$dmem_master_arburst), - .dmem_master_arlock(near_mem$dmem_master_arlock), - .dmem_master_arcache(near_mem$dmem_master_arcache), - .dmem_master_arprot(near_mem$dmem_master_arprot), - .dmem_master_arqos(near_mem$dmem_master_arqos), - .dmem_master_arregion(near_mem$dmem_master_arregion), - .dmem_master_rready(near_mem$dmem_master_rready), - .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put), - .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get), - .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put), - .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get), - .RDY_sfence_vma()); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(soc_map$m_pc_reset_value), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule stage1_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_reqs$ENQ), - .DEQ(stage1_f_reset_reqs$DEQ), - .CLR(stage1_f_reset_reqs$CLR), - .FULL_N(stage1_f_reset_reqs$FULL_N), - .EMPTY_N(stage1_f_reset_reqs$EMPTY_N)); - - // submodule stage1_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_rsps$ENQ), - .DEQ(stage1_f_reset_rsps$DEQ), - .CLR(stage1_f_reset_rsps$CLR), - .FULL_N(stage1_f_reset_rsps$FULL_N), - .EMPTY_N(stage1_f_reset_rsps$EMPTY_N)); - - // submodule stage2_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_reqs$ENQ), - .DEQ(stage2_f_reset_reqs$DEQ), - .CLR(stage2_f_reset_reqs$CLR), - .FULL_N(stage2_f_reset_reqs$FULL_N), - .EMPTY_N(stage2_f_reset_reqs$EMPTY_N)); - - // submodule stage2_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_rsps$ENQ), - .DEQ(stage2_f_reset_rsps$DEQ), - .CLR(stage2_f_reset_rsps$CLR), - .FULL_N(stage2_f_reset_rsps$FULL_N), - .EMPTY_N(stage2_f_reset_rsps$EMPTY_N)); - - // submodule stage2_mbox - mkRISCV_MBox stage2_mbox(.CLK(CLK), - .RST_N(RST_N), - .req_f3(stage2_mbox$req_f3), - .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32), - .req_v1(stage2_mbox$req_v1), - .req_v2(stage2_mbox$req_v2), - .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity), - .EN_set_verbosity(stage2_mbox$EN_set_verbosity), - .EN_req_reset(stage2_mbox$EN_req_reset), - .EN_rsp_reset(stage2_mbox$EN_rsp_reset), - .EN_req(stage2_mbox$EN_req), - .RDY_set_verbosity(), - .RDY_req_reset(), - .RDY_rsp_reset(), - .valid(stage2_mbox$valid), - .word(stage2_mbox$word)); - - // submodule stage3_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_reqs$ENQ), - .DEQ(stage3_f_reset_reqs$DEQ), - .CLR(stage3_f_reset_reqs$CLR), - .FULL_N(stage3_f_reset_reqs$FULL_N), - .EMPTY_N(stage3_f_reset_reqs$EMPTY_N)); - - // submodule stage3_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_rsps$ENQ), - .DEQ(stage3_f_reset_rsps$DEQ), - .CLR(stage3_f_reset_rsps$CLR), - .FULL_N(stage3_f_reset_rsps$FULL_N), - .EMPTY_N(stage3_f_reset_rsps$EMPTY_N)); - - // rule RL_rl_show_pipe - assign CAN_FIRE_RL_rl_show_pipe = - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - rg_state != 4'd0 && - rg_state != 4'd1 && - rg_state != 4'd10 ; - assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ; - - // rule RL_rl_stage2_nonpipe - assign CAN_FIRE_RL_rl_stage2_nonpipe = - rg_state == 4'd3 && !stage3_rg_full && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd3 && - (!stage1_rg_full || - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484) ; - assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ; - - // rule RL_rl_stage1_CSRR_W - assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_stage1_CSRR_S_or_C - assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_stage1_restart_after_csrrx - assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx = - CAN_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // rule RL_rl_stage1_xRET - assign CAN_FIRE_RL_rl_stage1_xRET = - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd7 || - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd8 || - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd9) ; - assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ; - - // rule RL_rl_stage1_FENCE_I - assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - - // rule RL_rl_finish_FENCE_I - assign CAN_FIRE_RL_rl_finish_FENCE_I = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_i_response_get && - rg_state == 4'd7 ; - assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ; - - // rule RL_rl_stage1_FENCE - assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - - // rule RL_rl_finish_FENCE - assign CAN_FIRE_RL_rl_finish_FENCE = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_response_get && - rg_state == 4'd8 ; - assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ; - - // rule RL_rl_stage1_SFENCE_VMA - assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - - // rule RL_rl_finish_SFENCE_VMA - assign CAN_FIRE_RL_rl_finish_SFENCE_VMA = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_finish_SFENCE_VMA = - CAN_FIRE_RL_rl_finish_SFENCE_VMA ; - - // rule RL_rl_stage1_WFI - assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - - // rule RL_rl_WFI_resume - assign CAN_FIRE_RL_rl_WFI_resume = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd10 && - csr_regfile$wfi_resume ; - assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ; - - // rule RL_rl_reset_from_WFI - assign CAN_FIRE_RL_rl_reset_from_WFI = - rg_state == 4'd10 && f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_4 ; - - // rule RL_rl_stage1_trap - assign CAN_FIRE_RL_rl_stage1_trap = - rg_state == 4'd4 || - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd11 ; - assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ; - - // rule RL_rl_trap_fetch - assign CAN_FIRE_RL_rl_trap_fetch = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd5 ; - assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; - - // rule RL_rl_stage1_interrupt - assign CAN_FIRE_RL_rl_stage1_interrupt = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - rg_state == 4'd3 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd0 && - !stage3_rg_full ; - assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ; - - // rule RL_imem_rl_assert_fail - assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ; - assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = - gpr_regfile$RDY_server_reset_response_get && - near_mem$RDY_server_reset_response_get && - csr_regfile$RDY_server_reset_response_get && - stage1_f_reset_rsps$EMPTY_N && - stage2_f_reset_rsps_i_notEmpty__052_AND_stage3_ETC___d1061 && - rg_state == 4'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_pipe - assign CAN_FIRE_RL_rl_pipe = - (csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1094 || - !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state_2_EQ_3_096_AND_stage3_rg_full_8_OR_NO_ETC___d1115 ; - assign WILL_FIRE_RL_rl_pipe = - CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = - gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043 && - rg_state == 4'd0 ; - assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ; - - // rule RL_imem_rl_fetch_next_32b - assign CAN_FIRE_RL_imem_rl_fetch_next_32b = - near_mem$imem_valid && - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] == 2'b11 ; - assign WILL_FIRE_RL_imem_rl_fetch_next_32b = - CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_stage3_rl_reset - assign CAN_FIRE_RL_stage3_rl_reset = - stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ; - - // rule RL_stage2_rl_reset_end - assign CAN_FIRE_RL_stage2_rl_reset_end = - stage2_f_reset_rsps$FULL_N && stage2_rg_resetting ; - assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ; - - // rule RL_stage2_rl_reset_begin - assign CAN_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ; - - // rule RL_stage1_rl_reset - assign CAN_FIRE_RL_stage1_rl_reset = - stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_csr_regfile$mav_csr_write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 ; - assign MUX_gpr_regfile$write_rd_1__SEL_1 = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] ; - assign MUX_gpr_regfile$write_rd_1__SEL_3 = - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - assign MUX_imem_rg_f3$write_1__SEL_1 = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ; - assign MUX_imem_rg_f3$write_1__SEL_2 = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ; - assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_imem_rg_pc$write_1__SEL_4 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_near_mem$imem_req_1__SEL_6 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_rg_cur_priv$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_mstatus_MXR$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_next_pc$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign MUX_rg_state$write_1__SEL_1 = - CAN_FIRE_RL_rl_reset_complete && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_2 = - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd2 ; - assign MUX_rg_state$write_1__SEL_3 = - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd3 ; - assign MUX_rg_state$write_1__SEL_4 = - CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ; - assign MUX_rg_state$write_1__SEL_6 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_rg_state$write_1__SEL_7 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_state$write_1__SEL_8 = - near_mem$RDY_server_fence_i_request_put && - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd5 ; - assign MUX_rg_state$write_1__SEL_9 = - near_mem$RDY_server_fence_request_put && - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd4 ; - assign MUX_rg_state$write_1__SEL_10 = - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd6 ; - assign MUX_rg_state$write_1__SEL_11 = - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd10 ; - assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 = - (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ? - csr_regfile$interrupt_pending[3:0] : - 4'd0 ; - always@(x_out_data_to_stage2_instr__h11612 or - csr_regfile$read_csr or - y__h18022 or - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220) - begin - case (x_out_data_to_stage2_instr__h11612[14:12]) - 3'b010, 3'b110: - MUX_csr_regfile$mav_csr_write_2__VAL_2 = - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220; - default: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - csr_regfile$read_csr[31:0] & y__h18022; - endcase - end - assign MUX_near_mem$imem_req_2__VAL_1 = - { soc_map$m_pc_reset_value[31:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_2 = - { x_out_next_pc__h11584[31:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[31:2], 2'b0 } ; - assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd3 : 4'd2 ; - assign MUX_rg_state$write_1__VAL_2 = - csr_regfile$access_permitted_1 ? 4'd6 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_3 = - csr_regfile$access_permitted_2 ? 4'd6 : 4'd4 ; - assign MUX_stage1_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1168 || - (csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088 || - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109) && - stage1_rg_full ; - assign MUX_stage2_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1163 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd2 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd0 ; - - // register cfg_logdelay - assign cfg_logdelay$D_IN = set_verbosity_logdelay ; - assign cfg_logdelay$EN = EN_set_verbosity ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register imem_rg_f3 - assign imem_rg_f3$D_IN = 3'b010 ; - assign imem_rg_f3$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_instr_15_0 - assign imem_rg_instr_15_0$D_IN = near_mem$imem_instr[31:16] ; - assign imem_rg_instr_15_0$EN = CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // register imem_rg_mstatus_MXR - assign imem_rg_mstatus_MXR$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_mstatus[19] : - rg_mstatus_MXR ; - assign imem_rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_pc - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h11584 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0]; - MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h11584; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_pc$D_IN = x_out_next_pc__h11584; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc; - default: imem_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_pc$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - - // register imem_rg_priv - assign imem_rg_priv$D_IN = rg_cur_priv ; - assign imem_rg_priv$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_satp - assign imem_rg_satp$D_IN = csr_regfile$read_satp ; - assign imem_rg_satp$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_sstatus_SUM - assign imem_rg_sstatus_SUM$D_IN = - WILL_FIRE_RL_rl_trap_fetch && rg_sstatus_SUM ; - assign imem_rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_tval - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h11584 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or - rg_next_pc or - WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h13393) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_tval$D_IN = soc_map$m_pc_reset_value[31:0]; - MUX_imem_rg_f3$write_1__SEL_2: - imem_rg_tval$D_IN = x_out_next_pc__h11584; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_tval$D_IN = x_out_next_pc__h11584; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - imem_rg_tval$D_IN = next_pc___1__h13393; - default: imem_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_tval$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // register rg_cur_priv - always@(MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or - csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_cur_priv$write_1__SEL_1: - rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[33:32]; - WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11; - default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_cur_priv$EN = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_mstatus[19] : - csr_regfile$csr_trap_actions[53] ; - assign rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_next_pc - always@(MUX_rg_next_pc$write_1__SEL_1 or - x_out_next_pc__h11584 or - MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h11584; - MUX_rg_cur_priv$write_1__SEL_1: - rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34]; - default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_next_pc$EN = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET ; - - // register rg_run_on_reset - assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ; - assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = - WILL_FIRE_RL_rl_stage1_interrupt && - csr_regfile$csr_trap_actions[52] ; - assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_7 ; - - // register rg_start_CPI_cycles - assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ; - assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_start_CPI_instrs - assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ; - assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_state - always@(WILL_FIRE_RL_rl_reset_complete or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_stage1_CSRR_W or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or - MUX_rg_state$write_1__VAL_3 or - WILL_FIRE_RL_rl_reset_from_WFI or - WILL_FIRE_RL_rl_reset_start or - MUX_rg_state$write_1__SEL_6 or - MUX_rg_state$write_1__SEL_7 or - WILL_FIRE_RL_rl_stage1_FENCE_I or - WILL_FIRE_RL_rl_stage1_FENCE or - WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_reset_complete: - rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_stage1_CSRR_W: - rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: - rg_state$D_IN = MUX_rg_state$write_1__VAL_3; - WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1; - MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd5; - WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd7; - WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd8; - WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd10; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_complete || - WILL_FIRE_RL_rl_stage1_CSRR_W || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C || - WILL_FIRE_RL_rl_reset_from_WFI || - WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_WFI ; - - // register stage1_rg_full - always@(WILL_FIRE_RL_stage1_rl_reset or - WILL_FIRE_RL_rl_pipe or - MUX_stage1_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or - WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_trap_fetch or - WILL_FIRE_RL_rl_stage1_trap or - WILL_FIRE_RL_rl_WFI_resume or - WILL_FIRE_RL_rl_finish_SFENCE_VMA or - WILL_FIRE_RL_rl_finish_FENCE or - WILL_FIRE_RL_rl_finish_FENCE_I or - WILL_FIRE_RL_rl_stage1_xRET or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_interrupt: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_trap_fetch: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_trap: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I: - stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_xRET: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0; - default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage1_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage1_rl_reset || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register stage2_rg_full - always@(stage2_f_reset_reqs$EMPTY_N or - WILL_FIRE_RL_rl_pipe or - MUX_stage2_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - stage2_f_reset_reqs$EMPTY_N: stage2_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage2_nonpipe: - stage2_rg_full$D_IN = 1'd0; - default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage2_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage2_nonpipe || - stage2_f_reset_reqs$EMPTY_N ; - - // register stage2_rg_resetting - assign stage2_rg_resetting$D_IN = stage2_f_reset_reqs$EMPTY_N ; - assign stage2_rg_resetting$EN = - WILL_FIRE_RL_stage2_rl_reset_end || stage2_f_reset_reqs$EMPTY_N ; - - // register stage2_rg_stage2 - assign stage2_rg_stage2$D_IN = - { rg_cur_priv, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825, - x_out_data_to_stage2_rd__h11614, - x_out_data_to_stage2_addr__h11615, - x_out_data_to_stage2_val1__h11616, - x_out_data_to_stage2_val2__h11617 } ; - assign stage2_rg_stage2$EN = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 ; - - // register stage3_rg_full - always@(WILL_FIRE_RL_stage3_rl_reset or - WILL_FIRE_RL_rl_pipe or - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 or - MUX_imem_rg_f3$write_1__SEL_1) - case (1'b1) - WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage3_rg_full$D_IN = - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2; - MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0; - default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage3_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_stage3_rl_reset ; - - // register stage3_rg_stage3 - assign stage3_rg_stage3$D_IN = - { stage2_rg_stage2[167:104], - stage2_rg_stage2[169:168], - stage2_rg_stage2[103:101] == 3'd0 || - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141, - x_out_data_to_stage3_rd__h5641, - x_out_data_to_stage3_rd_val__h5642 } ; - assign stage3_rg_stage3$EN = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd2 ; - - // submodule csr_regfile - assign csr_regfile$access_permitted_1_csr_addr = - x_out_data_to_stage2_instr__h11612[31:20] ; - assign csr_regfile$access_permitted_1_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ; - assign csr_regfile$access_permitted_2_csr_addr = - x_out_data_to_stage2_instr__h11612[31:20] ; - assign csr_regfile$access_permitted_2_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_2_read_not_write = - rs1_val__h17721 == 32'd0 ; - assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ; - assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ; - always@(IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746) - begin - case (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746) - 4'd7: csr_regfile$csr_ret_actions_from_priv = 2'b11; - 4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b01; - default: csr_regfile$csr_ret_actions_from_priv = 2'b0; - endcase - end - always@(WILL_FIRE_RL_rl_stage1_interrupt or - MUX_csr_regfile$csr_trap_actions_5__VAL_1 or - WILL_FIRE_RL_rl_stage1_trap or - x_out_trap_info_exc_code__h13233 or - WILL_FIRE_RL_rl_stage2_nonpipe or near_mem$dmem_exc_code) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_exc_code = - MUX_csr_regfile$csr_trap_actions_5__VAL_1; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h13233; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_exc_code = near_mem$dmem_exc_code; - default: csr_regfile$csr_trap_actions_exc_code = - 4'b1010 /* unspecified value */ ; - endcase - end - assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ; - assign csr_regfile$csr_trap_actions_interrupt = - WILL_FIRE_RL_rl_stage1_interrupt && !csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_nmi = - WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_pc = - WILL_FIRE_RL_rl_stage2_nonpipe ? - stage2_rg_stage2[167:136] : - imem_rg_pc ; - always@(WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_stage1_trap or - value__h13281 or WILL_FIRE_RL_rl_stage2_nonpipe or stage2_rg_stage2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_xtval = 32'd0; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_xtval = value__h13281; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_xtval = stage2_rg_stage2[95:64]; - default: csr_regfile$csr_trap_actions_xtval = - 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ; - assign csr_regfile$m_external_interrupt_req_set_not_clear = - m_external_interrupt_req_set_not_clear ; - assign csr_regfile$mav_csr_write_csr_addr = - x_out_data_to_stage2_instr__h11612[31:20] ; - assign csr_regfile$mav_csr_write_word = - MUX_csr_regfile$mav_csr_write_1__SEL_1 ? - rs1_val__h17231 : - MUX_csr_regfile$mav_csr_write_2__VAL_2 ; - assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ; - assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign csr_regfile$read_csr_csr_addr = - x_out_data_to_stage2_instr__h11612[31:20] ; - assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ; - assign csr_regfile$s_external_interrupt_req_set_not_clear = - s_external_interrupt_req_set_not_clear ; - assign csr_regfile$software_interrupt_req_set_not_clear = - software_interrupt_req_set_not_clear ; - assign csr_regfile$timer_interrupt_req_set_not_clear = - timer_interrupt_req_set_not_clear ; - assign csr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign csr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign csr_regfile$EN_mav_read_csr = 1'b0 ; - assign csr_regfile$EN_mav_csr_write = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h11612[19:15] != 5'd0 ; - assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_1 ; - assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ; - assign csr_regfile$EN_csr_minstret_incr = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd2 || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_stage1_WFI || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign csr_regfile$EN_debug = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = hart0_server_reset_request_put ; - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = - gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043 && - rg_state == 4'd0 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = rg_run_on_reset ; - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule gpr_regfile - assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign gpr_regfile$read_rs1_rs1 = _theResult____h4280[19:15] ; - assign gpr_regfile$read_rs2_rs2 = _theResult____h4280[24:20] ; - assign gpr_regfile$write_rd_rd = - MUX_gpr_regfile$write_rd_1__SEL_1 ? - stage3_rg_stage3[36:32] : - x_out_data_to_stage2_instr__h11612[11:7] ; - assign gpr_regfile$write_rd_rd_val = - (MUX_csr_regfile$mav_csr_write_1__SEL_1 || - MUX_gpr_regfile$write_rd_1__SEL_3) ? - csr_regfile$read_csr[31:0] : - stage3_rg_stage3[31:0] ; - assign gpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign gpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign gpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - - // submodule near_mem - assign near_mem$dmem_master_arready = dmem_master_arready ; - assign near_mem$dmem_master_awready = dmem_master_awready ; - assign near_mem$dmem_master_bid = dmem_master_bid ; - assign near_mem$dmem_master_bresp = dmem_master_bresp ; - assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; - assign near_mem$dmem_master_rdata = dmem_master_rdata ; - assign near_mem$dmem_master_rid = dmem_master_rid ; - assign near_mem$dmem_master_rlast = dmem_master_rlast ; - assign near_mem$dmem_master_rresp = dmem_master_rresp ; - assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; - assign near_mem$dmem_master_wready = dmem_master_wready ; - assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h11615 ; - assign near_mem$dmem_req_amo_funct7 = - x_out_data_to_stage2_val1__h11616[6:0] ; - assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h11612[14:12] ; - assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ; - always@(IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825) - begin - case (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825) - 3'd1: near_mem$dmem_req_op = 2'd0; - 3'd2: near_mem$dmem_req_op = 2'd1; - default: near_mem$dmem_req_op = 2'd2; - endcase - end - assign near_mem$dmem_req_priv = - csr_regfile$read_mstatus[17] ? - csr_regfile$read_mstatus[12:11] : - rg_cur_priv ; - assign near_mem$dmem_req_satp = csr_regfile$read_satp ; - assign near_mem$dmem_req_sstatus_SUM = 1'd0 ; - assign near_mem$dmem_req_store_value = - { 32'd0, x_out_data_to_stage2_val2__h11617 } ; - assign near_mem$imem_master_arready = imem_master_arready ; - assign near_mem$imem_master_awready = imem_master_awready ; - assign near_mem$imem_master_bid = imem_master_bid ; - assign near_mem$imem_master_bresp = imem_master_bresp ; - assign near_mem$imem_master_bvalid = imem_master_bvalid ; - assign near_mem$imem_master_rdata = imem_master_rdata ; - assign near_mem$imem_master_rid = imem_master_rid ; - assign near_mem$imem_master_rlast = imem_master_rlast ; - assign near_mem$imem_master_rresp = imem_master_rresp ; - assign near_mem$imem_master_rvalid = imem_master_rvalid ; - assign near_mem$imem_master_wready = imem_master_wready ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_near_mem$imem_req_2__VAL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - MUX_near_mem$imem_req_2__VAL_2 or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - next_pc___1__h13393 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_trap_fetch or - MUX_near_mem$imem_req_2__VAL_5 or MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1; - MUX_imem_rg_f3$write_1__SEL_2: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_addr = next_pc___1__h13393; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - default: near_mem$imem_req_addr = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_f3 = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_mstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_mstatus_MXR or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_mstatus_MXR) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_mstatus_MXR = imem_rg_mstatus_MXR; - default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_priv = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - MUX_near_mem$imem_req_1__SEL_6) ? - rg_cur_priv : - imem_rg_priv ; - assign near_mem$imem_req_satp = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? - imem_rg_satp : - csr_regfile$read_satp ; - always@(WILL_FIRE_RL_rl_trap_fetch or - rg_sstatus_SUM or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - imem_rg_sstatus_SUM or - MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_sstatus_SUM = imem_rg_sstatus_SUM; - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_sstatus_SUM = 1'd0; - default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$server_fence_request_put = - 8'b10101010 /* unspecified value */ ; - assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ; - assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ; - assign near_mem$EN_imem_req = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_imem_rl_fetch_next_32b || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_dmem_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 && - (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == - 3'd1 || - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == - 3'd2 || - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == - 3'd4) ; - assign near_mem$EN_server_fence_i_request_put = - MUX_rg_state$write_1__SEL_8 ; - assign near_mem$EN_server_fence_i_response_get = - CAN_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_9 ; - assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ; - assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_10 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule stage1_f_reset_reqs - assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage1_f_reset_rsps - assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage1_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_f_reset_reqs - assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage2_f_reset_reqs$DEQ = stage2_f_reset_reqs$EMPTY_N ; - assign stage2_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage2_f_reset_rsps - assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage2_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_mbox - assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h11612[14:12] ; - assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4280[3] ; - assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h11616 ; - assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h11617 ; - assign stage2_mbox$set_verbosity_verbosity = 4'h0 ; - assign stage2_mbox$EN_set_verbosity = 1'b0 ; - assign stage2_mbox$EN_req_reset = 1'b0 ; - assign stage2_mbox$EN_rsp_reset = 1'b0 ; - assign stage2_mbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == - 3'd3 ; - - // submodule stage3_f_reset_reqs - assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage3_f_reset_rsps - assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage3_f_reset_rsps$CLR = 1'b0 ; - - // remaining internal signals - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523 = - rs1_val_bypassed__h4288 == rs2_val__h11713 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525 = - (rs1_val_bypassed__h4288 ^ 32'h80000000) < - (rs2_val__h11713 ^ 32'h80000000) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527 = - rs1_val_bypassed__h4288 < rs2_val__h11713 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 = - (_theResult____h4280[6:0] == 7'b1100011) ? - _theResult____h4280[14:12] != 3'b0 && - _theResult____h4280[14:12] != 3'b001 && - _theResult____h4280[14:12] != 3'b100 && - _theResult____h4280[14:12] != 3'b101 && - _theResult____h4280[14:12] != 3'b110 && - _theResult____h4280[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 : - (_theResult____h4280[6:0] != 7'b0110011 || - _theResult____h4280[31:25] != 7'b0000001) && - (((_theResult____h4280[6:0] == 7'b0010011 || - _theResult____h4280[6:0] == 7'b0110011) && - (_theResult____h4280[14:12] == 3'b001 || - _theResult____h4280[14:12] == 3'b101)) ? - _theResult____h4280[25] : - CASE_theResult__280_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 = - (_theResult____h4280[6:0] == 7'b1100011) ? - _theResult____h4280[14:12] != 3'b0 && - _theResult____h4280[14:12] != 3'b001 && - _theResult____h4280[14:12] != 3'b100 && - _theResult____h4280[14:12] != 3'b101 && - _theResult____h4280[14:12] != 3'b110 && - _theResult____h4280[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 : - _theResult____h4280[6:0] != 7'b1101111 && - _theResult____h4280[6:0] != 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 = - (_theResult____h4280[6:0] == 7'b1100011) ? - (_theResult____h4280[14:12] == 3'b0 || - _theResult____h4280[14:12] == 3'b001 || - _theResult____h4280[14:12] == 3'b100 || - _theResult____h4280[14:12] == 3'b101 || - _theResult____h4280[14:12] == 3'b110 || - _theResult____h4280[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 : - _theResult____h4280[6:0] == 7'b0110011 && - _theResult____h4280[31:25] == 7'b0000001 || - (((_theResult____h4280[6:0] == 7'b0010011 || - _theResult____h4280[6:0] == 7'b0110011) && - (_theResult____h4280[14:12] == 3'b001 || - _theResult____h4280[14:12] == 3'b101)) ? - !_theResult____h4280[25] : - CASE_theResult__280_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682 = - (_theResult____h4280[6:0] == 7'b1100011) ? - (_theResult____h4280[14:12] == 3'b0 || - _theResult____h4280[14:12] == 3'b001 || - _theResult____h4280[14:12] == 3'b100 || - _theResult____h4280[14:12] == 3'b101 || - _theResult____h4280[14:12] == 3'b110 || - _theResult____h4280[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 : - _theResult____h4280[6:0] == 7'b1101111 || - _theResult____h4280[6:0] == 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937 = - ((_theResult____h4280[6:0] == 7'b0010011 || - _theResult____h4280[6:0] == 7'b0110011) && - (_theResult____h4280[14:12] == 3'b001 || - _theResult____h4280[14:12] == 3'b101)) ? - alu_outputs___1_val1__h11890 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 ; - assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564 ? - 4'd11 : - 4'd0 ; - assign IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - IF_stage2_rg_stage2_8_BITS_100_TO_96_48_EQ_0_7_ETC___d175 : - 2'd0 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653 = - _theResult____h4280[14:12] == 3'b0 && - (_theResult____h4280[6:0] != 7'b0110011 || - !_theResult____h4280[30]) || - _theResult____h4280[14:12] == 3'b0 && - _theResult____h4280[6:0] == 7'b0110011 && - _theResult____h4280[30] || - _theResult____h4280[14:12] == 3'b010 || - _theResult____h4280[14:12] == 3'b011 || - _theResult____h4280[14:12] == 3'b100 || - _theResult____h4280[14:12] == 3'b110 || - _theResult____h4280[14:12] == 3'b111 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 ? - next_pc___1__h13393 : - next_pc__h13391 ; - assign IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270 = - imem_rg_pc == csr_regfile$csr_trap_actions[97:66] ; - assign IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 = - near_mem$imem_exc ? - 4'd11 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 ; - assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220 = - csr_regfile$read_csr[31:0] | rs1_val__h17721 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d437 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:10] == 6'b100011 && - instr__h4278[6:5] == 2'b0) ? - instr__h11148 : - ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 && - instr__h4278[15:12] == 4'b1001 && - instr__h4278[11:7] == 5'd0 && - instr__h4278[6:2] == 5'd0) ? - instr__h11486 : - 32'h0) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d439 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:10] == 6'b100011 && - instr__h4278[6:5] == 2'b10) ? - instr__h10876 : - ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:10] == 6'b100011 && - instr__h4278[6:5] == 2'b01) ? - instr__h11012 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d437) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d441 = - (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308 && - instr__h4278[6:2] != 5'd0) ? - instr__h10645 : - ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:10] == 6'b100011 && - instr__h4278[6:5] == 2'b11) ? - instr__h10740 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d439) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d442 = - (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302 && - instr__h4278[6:2] != 5'd0) ? - instr__h10526 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d441 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d444 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b100 && - instr__h4278[11:10] == 2'b01 && - imm6__h8672 != 6'd0 && - !instr__h4278[12]) ? - instr__h10231 : - ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b100 && - instr__h4278[11:10] == 2'b10) ? - instr__h10348 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d442) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d445 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b100 && - instr__h4278[11:10] == 2'b0 && - imm6__h8672 != 6'd0 && - !instr__h4278[12]) ? - instr__h10038 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d444 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d446 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 && - instr__h4278[15:13] == 3'b0 && - instr__h4278[11:7] != 5'd0 && - imm6__h8672 != 6'd0 && - !instr__h4278[12]) ? - instr__h9845 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d445 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d448 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b011 && - instr__h4278[11:7] == 5'd2 && - nzimm10__h9296 != 10'd0) ? - instr__h9500 : - ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b0 && - instr__h4278[15:13] == 3'b0 && - nzimm10__h9511 != 10'd0) ? - instr__h9672 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d446) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d449 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b0 && - instr__h4278[11:7] != 5'd0 && - imm6__h8672 != 6'd0 || - csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b0 && - instr__h4278[11:7] == 5'd0 && - imm6__h8672 == 6'd0) ? - instr__h9063 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d448 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d450 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b011 && - instr__h4278[11:7] != 5'd0 && - instr__h4278[11:7] != 5'd2 && - imm6__h8672 != 6'd0) ? - instr__h8934 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d449 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d452 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b111) ? - instr__h8412 : - ((csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b010 && - instr__h4278[11:7] != 5'd0) ? - instr__h8750 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d450) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d453 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b110) ? - instr__h8095 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d452 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d454 = - (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308 && - instr__h4278[6:2] == 5'd0) ? - instr__h8030 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d453 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d455 = - (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302 && - instr__h4278[6:2] == 5'd0) ? - instr__h7914 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d454 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d456 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b001) ? - instr__h7524 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d455 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d457 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b01 && - instr__h4278[15:13] == 3'b101) ? - instr__h7181 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d456 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d458 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b0 && - instr__h4278[15:13] == 3'b110) ? - instr__h6952 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d457 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d459 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b0 && - instr__h4278[15:13] == 3'b010) ? - instr__h6757 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d458 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d460 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 && - instr__h4278[15:13] == 3'b110) ? - instr__h6565 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d459 ; - assign IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112 = - near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ; - assign IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723 = - ((rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) && - _theResult____h4280[31:20] == 12'b000100000010) ? - 4'd8 : - (rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_EQ_0_ETC___d721 ? - 4'd10 : - 4'd11) ; - assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 : - 2'd0 ; - assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 : - 2'd0 ; - assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 = - x_out_bypass_rd__h5992 == _theResult____h4280[19:15] ; - assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466 = - x_out_bypass_rd__h5992 == _theResult____h4280[24:20] ; - assign IF_stage2_rg_stage2_8_BITS_100_TO_96_48_EQ_0_7_ETC___d175 = - (stage2_rg_stage2[100:96] == 5'd0) ? - 2'd0 : - ((near_mem$dmem_valid && !near_mem$dmem_exc) ? 2'd2 : 2'd1) ; - assign IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115 = - stage2_mbox$valid ? 2'd2 : 2'd1 ; - assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564 = - (_theResult____h4280[14:12] != 3'b0 || - _theResult____h4280[6:0] == 7'b0110011 && - _theResult____h4280[30]) && - (_theResult____h4280[14:12] != 3'b0 || - _theResult____h4280[6:0] != 7'b0110011 || - !_theResult____h4280[30]) && - _theResult____h4280[14:12] != 3'b010 && - _theResult____h4280[14:12] != 3'b011 && - _theResult____h4280[14:12] != 3'b100 && - _theResult____h4280[14:12] != 3'b110 && - _theResult____h4280[14:12] != 3'b111 ; - assign NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 = - cur_verbosity__h2985 > 4'd1 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - (!stage1_rg_full || - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109) && - (!stage1_rg_full || - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd2 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd0) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd2 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd0) && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 || - !stage1_rg_full ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1163 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1165 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161) && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd2 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd0) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1168 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1165 && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 || - !stage1_rg_full) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1182 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) ; - assign NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d812 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd0 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd1 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd2 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd3 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd4 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd5 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd6 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd7 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd8 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd9 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd10 ; - assign NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d849 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 != - 3'd0 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 != - 3'd1 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 != - 3'd2 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 != - 3'd3 ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 = - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] != 2'b11) ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d210 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] == 2'b11) && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] == 2'b11) ; - assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1090 = - !near_mem$imem_valid || - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == - 2'd1 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ; - assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101 = - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469 || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) ; - assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109 = - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ; - assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469 = - !near_mem$imem_valid || - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d210 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == - 2'd1 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ; - assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878 = - { {20{theResult__280_BITS_31_TO_20__q17[11]}}, - theResult__280_BITS_31_TO_20__q17 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288 = - { {9{offset__h7128[11]}}, offset__h7128 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317 = - { {4{offset__h8039[8]}}, offset__h8039 } ; - assign _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161 = - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ; - assign _theResult_____1_fst__h12718 = - (_theResult____h4280[14:12] == 3'b0 && - _theResult____h4280[6:0] == 7'b0110011 && - _theResult____h4280[30]) ? - rd_val___1__h12714 : - _theResult_____1_fst__h12725 ; - assign _theResult_____1_fst__h12753 = - rs1_val_bypassed__h4288 & _theResult___snd__h13851 ; - assign _theResult____h22285 = - (delta_CPI_instrs__h22284 == 64'd0) ? - delta_CPI_instrs___1__h22320 : - delta_CPI_instrs__h22284 ; - assign _theResult____h4280 = x_out_data_to_stage2_instr__h11612 ; - assign _theResult___fst__h6320 = - (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11) ? - instr_out___1__h6322 : - _theResult___fst__h6348 ; - assign _theResult___fst__h6348 = - (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11) ? - instr_out___1__h6350 : - near_mem$imem_instr ; - assign _theResult___snd__h13851 = - (_theResult____h4280[6:0] == 7'b0010011) ? - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878 : - rs2_val__h11713 ; - assign alu_outputs___1_addr__h11739 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 ? - branch_target__h11717 : - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869 ; - assign alu_outputs___1_addr__h11760 = - imem_rg_pc + - { {11{theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q4[20]}}, - theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q4 } ; - assign alu_outputs___1_addr__h11786 = - { alu_outputs___1_addr__h11981[31:1], 1'd0 } ; - assign alu_outputs___1_addr__h11981 = - rs1_val_bypassed__h4288 + - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878 ; - assign alu_outputs___1_addr__h12002 = - rs1_val_bypassed__h4288 + - { {20{theResult__280_BITS_31_TO_25_CONCAT_theResult__ETC__q7[11]}}, - theResult__280_BITS_31_TO_25_CONCAT_theResult__ETC__q7 } ; - assign alu_outputs___1_exc_code__h12238 = - (_theResult____h4280[14:12] == 3'b0) ? - ((_theResult____h4280[11:7] == 5'd0 && - _theResult____h4280[19:15] == 5'd0) ? - CASE_theResult__280_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 : - 4'd2) : - 4'd2 ; - assign alu_outputs___1_val1__h11890 = - (_theResult____h4280[14:12] == 3'b001) ? - rd_val__h13747 : - (_theResult____h4280[30] ? rd_val__h13821 : rd_val__h13799) ; - assign alu_outputs___1_val1__h11928 = - (_theResult____h4280[14:12] == 3'b0 && - (_theResult____h4280[6:0] != 7'b0110011 || - !_theResult____h4280[30])) ? - rd_val___1__h12706 : - _theResult_____1_fst__h12718 ; - assign alu_outputs___1_val1__h11944 = - { _theResult____h4280[31:12], 12'h0 } ; - assign alu_outputs___1_val1__h11960 = - imem_rg_pc + alu_outputs___1_val1__h11944 ; - assign alu_outputs___1_val1__h12242 = - _theResult____h4280[14] ? - { 27'd0, _theResult____h4280[19:15] } : - rs1_val_bypassed__h4288 ; - assign alu_outputs___1_val1__h12263 = - { 25'd0, _theResult____h4280[31:25] } ; - assign branch_target__h11717 = - imem_rg_pc + - { {19{theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q3[12]}}, - theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q3 } ; - assign cpi__h22287 = x__h22286 / 64'd10 ; - assign cpifrac__h22288 = x__h22286 % 64'd10 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1083 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1079 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd2 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd0 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1094 = - csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1083 || - (csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088 || - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1090 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - stage1_rg_full ; - assign csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1273 = - delta_CPI_cycles__h22283 * 64'd10 ; - assign csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302 = - csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 && - instr__h4278[15:12] == 4'b1000 && - instr__h4278[11:7] != 5'd0 ; - assign csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308 = - csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 && - instr__h4278[15:12] == 4'b1001 && - instr__h4278[11:7] != 5'd0 ; - assign cur_verbosity__h2985 = - (csr_regfile$read_csr_minstret < cfg_logdelay) ? - 4'd0 : - cfg_verbosity ; - assign data_to_stage2_addr__h11607 = x_out_data_to_stage2_addr__h11615 ; - assign delta_CPI_cycles__h22283 = - csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ; - assign delta_CPI_instrs___1__h22320 = delta_CPI_instrs__h22284 + 64'd1 ; - assign delta_CPI_instrs__h22284 = - csr_regfile$read_csr_minstret - rg_start_CPI_instrs ; - assign fall_through_pc__h11571 = - imem_rg_pc + - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 ? - 32'd4 : - 32'd2) ; - assign gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043 = - gpr_regfile$RDY_server_reset_request_put && - near_mem$RDY_server_reset_request_put && - csr_regfile$RDY_server_reset_request_put && - f_reset_reqs$EMPTY_N && - stage1_f_reset_reqs$FULL_N && - stage2_f_reset_reqs$FULL_N && - stage3_f_reset_reqs$FULL_N ; - assign imm12__h10054 = { 7'b0100000, instr__h4278[6:2] } ; - assign imm12__h6421 = { 4'd0, offset__h6191 } ; - assign imm12__h6758 = { 5'd0, offset__h6700 } ; - assign imm12__h8674 = { {6{imm6__h8672[5]}}, imm6__h8672 } ; - assign imm12__h9298 = { {2{nzimm10__h9296[9]}}, nzimm10__h9296 } ; - assign imm12__h9513 = { 2'd0, nzimm10__h9511 } ; - assign imm12__h9709 = { 7'b0, instr__h4278[6:2] } ; - assign imm20__h8802 = { {14{imm6__h8672[5]}}, imm6__h8672 } ; - assign imm6__h8672 = { instr__h4278[12], instr__h4278[6:2] } ; - assign instr___1__h6153 = - (csr_regfile$read_misa[2] && instr__h4278[1:0] == 2'b10 && - instr__h4278[11:7] != 5'd0 && - instr__h4278[15:13] == 3'b010) ? - instr__h6420 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d460 ; - assign instr__h10038 = - { imm12__h9709, rs1__h6759, 3'b101, rs1__h6759, 7'b0010011 } ; - assign instr__h10231 = - { imm12__h10054, rs1__h6759, 3'b101, rs1__h6759, 7'b0010011 } ; - assign instr__h10348 = - { imm12__h8674, rs1__h6759, 3'b111, rs1__h6759, 7'b0010011 } ; - assign instr__h10526 = - { 7'b0, - instr__h4278[6:2], - 8'd0, - instr__h4278[11:7], - 7'b0110011 } ; - assign instr__h10645 = - { 7'b0, - instr__h4278[6:2], - instr__h4278[11:7], - 3'b0, - instr__h4278[11:7], - 7'b0110011 } ; - assign instr__h10740 = - { 7'b0, rd__h6760, rs1__h6759, 3'b111, rs1__h6759, 7'b0110011 } ; - assign instr__h10876 = - { 7'b0, rd__h6760, rs1__h6759, 3'b110, rs1__h6759, 7'b0110011 } ; - assign instr__h11012 = - { 7'b0, rd__h6760, rs1__h6759, 3'b100, rs1__h6759, 7'b0110011 } ; - assign instr__h11148 = - { 7'b0100000, - rd__h6760, - rs1__h6759, - 3'b0, - rs1__h6759, - 7'b0110011 } ; - assign instr__h11486 = - { 12'b000000000001, - instr__h4278[11:7], - 3'b0, - instr__h4278[11:7], - 7'b1110011 } ; - assign instr__h4278 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 ? - instr_out___1__h6290 : - _theResult___fst__h6320 ; - assign instr__h6420 = - { imm12__h6421, 8'd18, instr__h4278[11:7], 7'b0000011 } ; - assign instr__h6565 = - { 4'd0, - instr__h4278[8:7], - instr__h4278[12], - instr__h4278[6:2], - 8'd18, - offset_BITS_4_TO_0___h6689, - 7'b0100011 } ; - assign instr__h6757 = - { imm12__h6758, rs1__h6759, 3'b010, rd__h6760, 7'b0000011 } ; - assign instr__h6952 = - { 5'd0, - instr__h4278[5], - instr__h4278[12], - rd__h6760, - rs1__h6759, - 3'b010, - offset_BITS_4_TO_0___h7120, - 7'b0100011 } ; - assign instr__h7181 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[19:12], - 12'd111 } ; - assign instr__h7524 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[19:12], - 12'd239 } ; - assign instr__h7914 = { 12'd0, instr__h4278[11:7], 15'd103 } ; - assign instr__h8030 = { 12'd0, instr__h4278[11:7], 15'd231 } ; - assign instr__h8095 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[10:5], - 5'd0, - rs1__h6759, - 3'b0, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[11], - 7'b1100011 } ; - assign instr__h8412 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[10:5], - 5'd0, - rs1__h6759, - 3'b001, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[11], - 7'b1100011 } ; - assign instr__h8750 = - { imm12__h8674, 8'd0, instr__h4278[11:7], 7'b0010011 } ; - assign instr__h8934 = { imm20__h8802, instr__h4278[11:7], 7'b0110111 } ; - assign instr__h9063 = - { imm12__h8674, - instr__h4278[11:7], - 3'b0, - instr__h4278[11:7], - 7'b0010011 } ; - assign instr__h9500 = - { imm12__h9298, - instr__h4278[11:7], - 3'b0, - instr__h4278[11:7], - 7'b0010011 } ; - assign instr__h9672 = { imm12__h9513, 8'd16, rd__h6760, 7'b0010011 } ; - assign instr__h9845 = - { imm12__h9709, - instr__h4278[11:7], - 3'b001, - instr__h4278[11:7], - 7'b0010011 } ; - assign instr_out___1__h6290 = - { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ; - assign instr_out___1__h6322 = { 16'b0, near_mem$imem_instr[15:0] } ; - assign instr_out___1__h6350 = { 16'b0, near_mem$imem_instr[31:16] } ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d949 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd0 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d952 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd1 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d955 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd2 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d958 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd3 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d961 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd4 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d964 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd5 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d967 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd6 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d970 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd7 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d973 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd8 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d976 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd9 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d979 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd10 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d982 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd0 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd1 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd2 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd3 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd4 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd5 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd6 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd7 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd8 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd9 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd10 ; - assign near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 = - near_mem$imem_pc[31:2] == imem_rg_pc[31:2] ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] == 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d478 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 = - near_mem$imem_pc == next_pc___1__h13393 ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1079 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != - 2'd1 || - !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 && - !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d478 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != - 2'd1 || - !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 && - !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) ; - assign next_pc___1__h13393 = imem_rg_pc + 32'd2 ; - assign next_pc__h13391 = imem_rg_pc + 32'd4 ; - assign nzimm10__h9296 = - { instr__h4278[12], - instr__h4278[4:3], - instr__h4278[5], - instr__h4278[2], - instr__h4278[6], - 4'b0 } ; - assign nzimm10__h9511 = - { instr__h4278[10:7], - instr__h4278[12:11], - instr__h4278[5], - instr__h4278[6], - 2'b0 } ; - assign offset_BITS_4_TO_0___h6689 = { instr__h4278[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h7120 = - { instr__h4278[11:10], instr__h4278[6], 2'b0 } ; - assign offset__h6191 = - { instr__h4278[3:2], - instr__h4278[12], - instr__h4278[6:4], - 2'b0 } ; - assign offset__h6700 = - { instr__h4278[5], instr__h4278[12:10], instr__h4278[6], 2'b0 } ; - assign offset__h7128 = - { instr__h4278[12], - instr__h4278[8], - instr__h4278[10:9], - instr__h4278[6], - instr__h4278[7], - instr__h4278[2], - instr__h4278[11], - instr__h4278[5:3], - 1'b0 } ; - assign offset__h8039 = - { instr__h4278[12], - instr__h4278[6:5], - instr__h4278[2], - instr__h4278[11:10], - instr__h4278[4:3], - 1'b0 } ; - assign output_stage2___1_bypass_rd_val__h5981 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - ((stage2_rg_stage2[100:96] == 5'd0) ? - stage2_rg_stage2[63:32] : - near_mem$dmem_word64[31:0]) : - stage2_rg_stage2[63:32] ; - assign rd__h6760 = { 2'b01, instr__h4278[4:2] } ; - assign rd_val___1__h12706 = - rs1_val_bypassed__h4288 + _theResult___snd__h13851 ; - assign rd_val___1__h12714 = - rs1_val_bypassed__h4288 - _theResult___snd__h13851 ; - assign rd_val___1__h12721 = - ((rs1_val_bypassed__h4288 ^ 32'h80000000) < - (_theResult___snd__h13851 ^ 32'h80000000)) ? - 32'd1 : - 32'd0 ; - assign rd_val___1__h12728 = - (rs1_val_bypassed__h4288 < _theResult___snd__h13851) ? - 32'd1 : - 32'd0 ; - assign rd_val___1__h12735 = - rs1_val_bypassed__h4288 ^ _theResult___snd__h13851 ; - assign rd_val___1__h12742 = - rs1_val_bypassed__h4288 | _theResult___snd__h13851 ; - assign rd_val__h11528 = - (stage3_rg_full && stage3_rg_stage3[37] && - stage3_rg_stage3[36:32] == _theResult____h4280[24:20]) ? - stage3_rg_stage3[31:0] : - gpr_regfile$read_rs2 ; - assign rd_val__h13747 = rs1_val_bypassed__h4288 << shamt__h11875 ; - assign rd_val__h13799 = rs1_val_bypassed__h4288 >> shamt__h11875 ; - assign rd_val__h13821 = - rs1_val_bypassed__h4288 >> shamt__h11875 | - ~(32'hFFFFFFFF >> shamt__h11875) & - {32{rs1_val_bypassed__h4288[31]}} ; - assign rd_val__h6105 = - (stage3_rg_full && stage3_rg_stage3[37] && - stage3_rg_stage3[36:32] == _theResult____h4280[19:15]) ? - stage3_rg_stage3[31:0] : - gpr_regfile$read_rs1 ; - assign rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_EQ_0_ETC___d721 = - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] || - rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) && - _theResult____h4280[31:20] == 12'b000100000101 ; - assign rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 = - rg_state == 4'd3 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1182 && - !stage3_rg_full && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd0 ; - assign rg_state_2_EQ_3_096_AND_stage3_rg_full_8_OR_NO_ETC___d1115 = - rg_state == 4'd3 && - (stage3_rg_full || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd0 || - stage1_rg_full) && - (stage3_rg_full || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd3) && - (stage3_rg_full || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd0 || - !stage1_rg_full || - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101) && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd0 || - stage3_rg_full) ; - assign rs1__h6759 = { 2'b01, instr__h4278[9:7] } ; - assign rs1_val__h17231 = - (x_out_data_to_stage2_instr__h11612[14:12] == 3'b001) ? - x_out_data_to_stage2_val1__h11616 : - { 27'd0, x_out_data_to_stage2_instr__h11612[19:15] } ; - assign rs1_val_bypassed__h4288 = - (_theResult____h4280[19:15] == 5'd0) ? 32'd0 : val__h6107 ; - assign rs2_val__h11713 = - (_theResult____h4280[24:20] == 5'd0) ? 32'd0 : val__h11530 ; - assign shamt__h11875 = - (_theResult____h4280[6:0] == 7'b0010011) ? - _theResult____h4280[24:20] : - rs2_val__h11713[4:0] ; - assign stage2_f_reset_rsps_i_notEmpty__052_AND_stage3_ETC___d1061 = - stage2_f_reset_rsps$EMPTY_N && stage3_f_reset_rsps$EMPTY_N && - f_reset_rsps$FULL_N && - (!rg_run_on_reset || - !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) ; - assign theResult__280_BITS_31_TO_20__q17 = _theResult____h4280[31:20] ; - assign theResult__280_BITS_31_TO_25_CONCAT_theResult__ETC__q7 = - { _theResult____h4280[31:25], _theResult____h4280[11:7] } ; - assign theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q3 = - { _theResult____h4280[31], - _theResult____h4280[7], - _theResult____h4280[30:25], - _theResult____h4280[11:8], - 1'b0 } ; - assign theResult__280_BIT_31_CONCAT_theResult__280_BI_ETC__q4 = - { _theResult____h4280[31], - _theResult____h4280[19:12], - _theResult____h4280[20], - _theResult____h4280[30:21], - 1'b0 } ; - assign trap_info_tval__h13230 = - (_theResult____h4280[6:0] != 7'b1101111 && - _theResult____h4280[6:0] != 7'b1100111 && - (_theResult____h4280[6:0] != 7'b1110011 || - _theResult____h4280[14:12] != 3'b0 || - _theResult____h4280[11:7] != 5'd0 || - _theResult____h4280[19:15] != 5'd0 || - _theResult____h4280[31:20] != 12'b0 && - _theResult____h4280[31:20] != 12'b000000000001)) ? - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 ? - _theResult____h4280 : - { 16'd0, instr__h4278[15:0] }) : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 ; - assign val__h11530 = - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == - 2'd2 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ? - x_out_bypass_rd_val__h5993 : - rd_val__h11528 ; - assign val__h6107 = - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == - 2'd2 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464) ? - x_out_bypass_rd_val__h5993 : - rd_val__h6105 ; - assign value__h13281 = - near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h13230 ; - assign x__h22286 = - csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1273[63:0] / - _theResult____h22285 ; - assign x_out_data_to_stage2_instr__h11612 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 ? - instr___1__h6153 : - instr__h4278 ; - assign x_out_data_to_stage2_rd__h11614 = - (_theResult____h4280[6:0] == 7'b1100011) ? - 5'd0 : - _theResult____h4280[11:7] ; - assign x_out_data_to_stage2_val2__h11617 = - (_theResult____h4280[6:0] == 7'b1100011) ? - branch_target__h11717 : - rs2_val__h11713 ; - assign x_out_next_pc__h11584 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682 ? - data_to_stage2_addr__h11607 : - fall_through_pc__h11571 ; - assign x_out_trap_info_exc_code__h13233 = - near_mem$imem_exc ? - near_mem$imem_exc_code : - alu_outputs_exc_code__h12281 ; - assign y__h18022 = ~rs1_val__h17721 ; - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[103:101]) - 3'd0, 3'd1, 3'd4: - x_out_data_to_stage3_rd__h5641 = stage2_rg_stage2[100:96]; - 3'd2: x_out_data_to_stage3_rd__h5641 = 5'd0; - default: x_out_data_to_stage3_rd__h5641 = stage2_rg_stage2[100:96]; - endcase - end - always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64) - begin - case (stage2_rg_stage2[103:101]) - 3'd0: x_out_data_to_stage3_rd_val__h5642 = stage2_rg_stage2[63:32]; - 3'd1, 3'd4: - x_out_data_to_stage3_rd_val__h5642 = near_mem$dmem_word64[31:0]; - default: x_out_data_to_stage3_rd_val__h5642 = stage2_mbox$word; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[103:101]) - 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h5992 = stage2_rg_stage2[100:96]; - default: x_out_bypass_rd__h5992 = stage2_rg_stage2[100:96]; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$word or output_stage2___1_bypass_rd_val__h5981) - begin - case (stage2_rg_stage2[103:101]) - 3'd0: x_out_bypass_rd_val__h5993 = stage2_rg_stage2[63:32]; - 3'd1, 3'd4: - x_out_bypass_rd_val__h5993 = output_stage2___1_bypass_rd_val__h5981; - default: x_out_bypass_rd_val__h5993 = stage2_mbox$word; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115 or - IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112) - begin - case (stage2_rg_stage2[103:101]) - 3'd0: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 = 2'd2; - 3'd1, 3'd2, 3'd4: - CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 = - IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112; - default: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 = - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[103:101]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132 = - !near_mem$dmem_valid || near_mem$dmem_exc; - default: IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132 = - !stage2_mbox$valid; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[103:101]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141 = - near_mem$dmem_valid && !near_mem$dmem_exc; - default: IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141 = - stage2_mbox$valid; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115 or - IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176) - begin - case (stage2_rg_stage2[103:101]) - 3'd0: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 = 2'd2; - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 = - IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176; - 3'd2: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 = 2'd0; - default: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 = - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115; - endcase - end - always@(rg_cur_priv) - begin - case (rg_cur_priv) - 2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd8; - 2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd9; - default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd11; - endcase - end - always@(_theResult____h4280 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q5) - begin - case (_theResult____h4280[31:20]) - 12'b0: - CASE_theResult__280_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = - CASE_rg_cur_priv_0b0_8_0b1_9_11__q5; - 12'b000000000001: - CASE_theResult__280_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd3; - default: CASE_theResult__280_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd2; - endcase - end - always@(_theResult____h4280 or alu_outputs___1_exc_code__h12238) - begin - case (_theResult____h4280[6:0]) - 7'b0000011, - 7'b0001111, - 7'b0010011, - 7'b0010111, - 7'b0100011, - 7'b0110011, - 7'b0110111, - 7'b1100011: - alu_outputs_exc_code__h12281 = 4'd2; - 7'b1100111, 7'b1101111: alu_outputs_exc_code__h12281 = 4'd0; - 7'b1110011: - alu_outputs_exc_code__h12281 = alu_outputs___1_exc_code__h12238; - default: alu_outputs_exc_code__h12281 = 4'd2; - endcase - end - always@(_theResult____h4280 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525) - begin - case (_theResult____h4280[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - _theResult____h4280[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527; - endcase - end - always@(_theResult____h4280 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525) - begin - case (_theResult____h4280[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - _theResult____h4280[14:12] == 3'b111 && - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527; - endcase - end - always@(_theResult____h4280) - begin - case (_theResult____h4280[6:0]) - 7'b0000011: - CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4280[14:12] != 3'b0 && - _theResult____h4280[14:12] != 3'b100 && - _theResult____h4280[14:12] != 3'b001 && - _theResult____h4280[14:12] != 3'b101 && - _theResult____h4280[14:12] != 3'b010; - 7'b0100011: - CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4280[14:12] != 3'b0 && - _theResult____h4280[14:12] != 3'b001 && - _theResult____h4280[14:12] != 3'b010; - default: CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4280[6:0] != 7'b0101111 || - _theResult____h4280[31:27] != 5'b00010 && - _theResult____h4280[31:27] != 5'b00011 && - _theResult____h4280[31:27] != 5'b0 && - _theResult____h4280[31:27] != 5'b00001 && - _theResult____h4280[31:27] != 5'b01100 && - _theResult____h4280[31:27] != 5'b01000 && - _theResult____h4280[31:27] != 5'b00100 && - _theResult____h4280[31:27] != 5'b10000 && - _theResult____h4280[31:27] != 5'b11000 && - _theResult____h4280[31:27] != 5'b10100 && - _theResult____h4280[31:27] != 5'b11100 || - _theResult____h4280[14:12] != 3'b010; - endcase - end - always@(_theResult____h4280 or - CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 or - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564) - begin - case (_theResult____h4280[6:0]) - 7'b0010011, 7'b0110011: - CASE_theResult__280_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564; - default: CASE_theResult__280_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = - _theResult____h4280[6:0] != 7'b0110111 && - _theResult____h4280[6:0] != 7'b0010111 && - CASE_theResult__280_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8; - endcase - end - always@(_theResult____h4280) - begin - case (_theResult____h4280[6:0]) - 7'b0000011: - CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4280[14:12] == 3'b0 || - _theResult____h4280[14:12] == 3'b100 || - _theResult____h4280[14:12] == 3'b001 || - _theResult____h4280[14:12] == 3'b101 || - _theResult____h4280[14:12] == 3'b010; - 7'b0100011: - CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4280[14:12] == 3'b0 || - _theResult____h4280[14:12] == 3'b001 || - _theResult____h4280[14:12] == 3'b010; - default: CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4280[6:0] == 7'b0101111 && - (_theResult____h4280[31:27] == 5'b00010 || - _theResult____h4280[31:27] == 5'b00011 || - _theResult____h4280[31:27] == 5'b0 || - _theResult____h4280[31:27] == 5'b00001 || - _theResult____h4280[31:27] == 5'b01100 || - _theResult____h4280[31:27] == 5'b01000 || - _theResult____h4280[31:27] == 5'b00100 || - _theResult____h4280[31:27] == 5'b10000 || - _theResult____h4280[31:27] == 5'b11000 || - _theResult____h4280[31:27] == 5'b10100 || - _theResult____h4280[31:27] == 5'b11100) && - _theResult____h4280[14:12] == 3'b010; - endcase - end - always@(_theResult____h4280 or - CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653) - begin - case (_theResult____h4280[6:0]) - 7'b0010011, 7'b0110011: - CASE_theResult__280_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653; - default: CASE_theResult__280_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = - _theResult____h4280[6:0] == 7'b0110111 || - _theResult____h4280[6:0] == 7'b0010111 || - CASE_theResult__280_BITS_6_TO_0_0b11_theResult_ETC__q10; - endcase - end - always@(_theResult____h4280 or - rg_cur_priv or - IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723) - begin - case (_theResult____h4280[31:20]) - 12'b0, 12'b000000000001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725 = 4'd11; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725 = - (rg_cur_priv == 2'b11 && - _theResult____h4280[31:20] == 12'b001100000010) ? - 4'd7 : - IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723; - endcase - end - always@(_theResult____h4280) - begin - case (_theResult____h4280[14:12]) - 3'b0, 3'b001, 3'b010, 3'b100, 3'b101: - CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = 4'd0; - default: CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = - 4'd11; - endcase - end - always@(_theResult____h4280) - begin - case (_theResult____h4280[14:12]) - 3'b0: CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd4; - 3'b001: CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd5; - default: CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd11; - endcase - end - always@(_theResult____h4280) - begin - case (_theResult____h4280[14:12]) - 3'b0, 3'b001, 3'b010: - CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd0; - default: CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = - 4'd11; - endcase - end - always@(_theResult____h4280 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725) - begin - case (_theResult____h4280[14:12]) - 3'b0: - CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = - (_theResult____h4280[11:7] == 5'd0 && - _theResult____h4280[19:15] == 5'd0) ? - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725 : - 4'd11; - 3'b001, 3'b101: - CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd2; - 3'b010, 3'b011, 3'b110, 3'b111: - CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd3; - 3'd4: CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd11; - endcase - end - always@(_theResult____h4280 or - CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 or - CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13 or - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690 or - CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 or - CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15) - begin - case (_theResult____h4280[6:0]) - 7'b0000011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12; - 7'b0001111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - CASE_theResult__280_BITS_14_TO_12_0b0_4_0b1_5_11__q13; - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690; - 7'b0010111, 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = 4'd0; - 7'b0100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - CASE_theResult__280_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - ((_theResult____h4280[31:27] == 5'b00010 || - _theResult____h4280[31:27] == 5'b00011 || - _theResult____h4280[31:27] == 5'b0 || - _theResult____h4280[31:27] == 5'b00001 || - _theResult____h4280[31:27] == 5'b01100 || - _theResult____h4280[31:27] == 5'b01000 || - _theResult____h4280[31:27] == 5'b00100 || - _theResult____h4280[31:27] == 5'b10000 || - _theResult____h4280[31:27] == 5'b11000 || - _theResult____h4280[31:27] == 5'b10100 || - _theResult____h4280[31:27] == 5'b11100) && - _theResult____h4280[14:12] == 3'b010) ? - 4'd0 : - 4'd11; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - CASE_theResult__280_BITS_14_TO_12_0b0_IF_theRe_ETC__q15; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - 4'd11; - endcase - end - always@(_theResult____h4280 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534) - begin - case (_theResult____h4280[6:0]) - 7'b1100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 = - (_theResult____h4280[14:12] != 3'b0 && - _theResult____h4280[14:12] != 3'b001 && - _theResult____h4280[14:12] != 3'b100 && - _theResult____h4280[14:12] != 3'b101 && - _theResult____h4280[14:12] != 3'b110 && - _theResult____h4280[14:12] != 3'b111) ? - 4'd11 : - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 ? - 4'd1 : - 4'd0); - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 = 4'd1; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 = - (_theResult____h4280[6:0] == 7'b0110011 && - _theResult____h4280[31:25] == 7'b0000001) ? - 4'd0 : - (((_theResult____h4280[6:0] == 7'b0010011 || - _theResult____h4280[6:0] == 7'b0110011) && - (_theResult____h4280[14:12] == 3'b001 || - _theResult____h4280[14:12] == 3'b101)) ? - (_theResult____h4280[25] ? 4'd11 : 4'd0) : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740); - endcase - end - always@(_theResult____h4280) - begin - case (_theResult____h4280[6:0]) - 7'b0000011: - CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd1; - 7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111: - CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd0; - 7'b0100011: - CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd2; - default: CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd4; - endcase - end - always@(_theResult____h4280 or - CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16) - begin - case (_theResult____h4280[6:0]) - 7'b1100011, 7'b1100111, 7'b1101111: - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 = 3'd0; - default: IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 = - (_theResult____h4280[6:0] == 7'b0110011 && - _theResult____h4280[31:25] == 7'b0000001) ? - 3'd3 : - CASE_theResult__280_BITS_6_TO_0_0b11_1_0b10011_ETC__q16; - endcase - end - always@(_theResult____h4280 or - _theResult_____1_fst__h12753 or - rd_val___1__h12721 or - rd_val___1__h12728 or rd_val___1__h12735 or rd_val___1__h12742) - begin - case (_theResult____h4280[14:12]) - 3'b010: _theResult_____1_fst__h12725 = rd_val___1__h12721; - 3'b011: _theResult_____1_fst__h12725 = rd_val___1__h12728; - 3'b100: _theResult_____1_fst__h12725 = rd_val___1__h12735; - 3'b110: _theResult_____1_fst__h12725 = rd_val___1__h12742; - default: _theResult_____1_fst__h12725 = _theResult_____1_fst__h12753; - endcase - end - always@(_theResult____h4280 or - rs1_val_bypassed__h4288 or - alu_outputs___1_addr__h11981 or - alu_outputs___1_addr__h12002 or - alu_outputs___1_addr__h11739 or - alu_outputs___1_addr__h11786 or alu_outputs___1_addr__h11760) - begin - case (_theResult____h4280[6:0]) - 7'b0000011: - x_out_data_to_stage2_addr__h11615 = alu_outputs___1_addr__h11981; - 7'b0100011: - x_out_data_to_stage2_addr__h11615 = alu_outputs___1_addr__h12002; - 7'b1100011: - x_out_data_to_stage2_addr__h11615 = alu_outputs___1_addr__h11739; - 7'b1100111: - x_out_data_to_stage2_addr__h11615 = alu_outputs___1_addr__h11786; - 7'b1101111: - x_out_data_to_stage2_addr__h11615 = alu_outputs___1_addr__h11760; - default: x_out_data_to_stage2_addr__h11615 = rs1_val_bypassed__h4288; - endcase - end - always@(_theResult____h4280 or imem_rg_pc or data_to_stage2_addr__h11607) - begin - case (_theResult____h4280[6:0]) - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - data_to_stage2_addr__h11607; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - (_theResult____h4280[6:0] == 7'b1110011 && - _theResult____h4280[14:12] == 3'b0 && - _theResult____h4280[11:7] == 5'd0 && - _theResult____h4280[19:15] == 5'd0 && - _theResult____h4280[31:20] == 12'b000000000001) ? - imem_rg_pc : - 32'd0; - endcase - end - always@(_theResult____h4280 or - alu_outputs___1_val1__h12263 or - alu_outputs___1_val1__h11928 or - alu_outputs___1_val1__h11960 or - alu_outputs___1_val1__h11944 or alu_outputs___1_val1__h12242) - begin - case (_theResult____h4280[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 = - alu_outputs___1_val1__h11928; - 7'b0010111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 = - alu_outputs___1_val1__h11960; - 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 = - alu_outputs___1_val1__h11944; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 = - alu_outputs___1_val1__h12242; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 = - alu_outputs___1_val1__h12263; - endcase - end - always@(_theResult____h4280 or - rs1_val_bypassed__h4288 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869) - begin - case (_theResult____h4280[6:0]) - 7'b1100111, 7'b1101111: - x_out_data_to_stage2_val1__h11616 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869; - default: x_out_data_to_stage2_val1__h11616 = - (_theResult____h4280[6:0] == 7'b0110011 && - _theResult____h4280[31:25] == 7'b0000001) ? - rs1_val_bypassed__h4288 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937; - endcase - end - always@(x_out_data_to_stage2_instr__h11612 or - x_out_data_to_stage2_val1__h11616) - begin - case (x_out_data_to_stage2_instr__h11612[14:12]) - 3'b010, 3'b011: rs1_val__h17721 = x_out_data_to_stage2_val1__h11616; - default: rs1_val__h17721 = - { 27'd0, x_out_data_to_stage2_instr__h11612[19:15] }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0; - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11; - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_logdelay$EN) - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN; - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_cur_priv$EN) - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN; - if (rg_run_on_reset$EN) - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (stage1_rg_full$EN) - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN; - if (stage2_rg_full$EN) - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN; - if (stage2_rg_resetting$EN) - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY - stage2_rg_resetting$D_IN; - if (stage3_rg_full$EN) - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN; - end - if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN; - if (imem_rg_instr_15_0$EN) - imem_rg_instr_15_0 <= `BSV_ASSIGNMENT_DELAY imem_rg_instr_15_0$D_IN; - if (imem_rg_mstatus_MXR$EN) - imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN; - if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN; - if (imem_rg_priv$EN) - imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN; - if (imem_rg_satp$EN) - imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN; - if (imem_rg_sstatus_SUM$EN) - imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN; - if (imem_rg_tval$EN) - imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_start_CPI_cycles$EN) - rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN; - if (rg_start_CPI_instrs$EN) - rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN; - if (stage2_rg_stage2$EN) - stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN; - if (stage3_rg_stage3$EN) - stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_logdelay = 64'hAAAAAAAAAAAAAAAA; - cfg_verbosity = 4'hA; - imem_rg_f3 = 3'h2; - imem_rg_instr_15_0 = 16'hAAAA; - imem_rg_mstatus_MXR = 1'h0; - imem_rg_pc = 32'hAAAAAAAA; - imem_rg_priv = 2'h2; - imem_rg_satp = 32'hAAAAAAAA; - imem_rg_sstatus_SUM = 1'h0; - imem_rg_tval = 32'hAAAAAAAA; - rg_cur_priv = 2'h2; - rg_mstatus_MXR = 1'h0; - rg_next_pc = 32'hAAAAAAAA; - rg_run_on_reset = 1'h0; - rg_sstatus_SUM = 1'h0; - rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA; - rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - stage1_rg_full = 1'h0; - stage2_rg_full = 1'h0; - stage2_rg_resetting = 1'h0; - stage2_rg_stage2 = 170'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - stage3_rg_full = 1'h0; - stage3_rg_stage3 = 104'hAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - rg_cur_priv, - csr_regfile$read_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write("MStatus{", - "sd:%0d", - csr_regfile$read_mstatus[14:13] == 2'h3 || - csr_regfile$read_mstatus[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2) - $write(" sxl:%0d uxl:%0d", 2'd0, 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tsr:%0d", csr_regfile$read_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tw:%0d", csr_regfile$read_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tvm:%0d", csr_regfile$read_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mxr:%0d", csr_regfile$read_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" sum:%0d", csr_regfile$read_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mprv:%0d", csr_regfile$read_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" xs:%0d", csr_regfile$read_mstatus[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" fs:%0d", csr_regfile$read_mstatus[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mpp:%0d", csr_regfile$read_mstatus[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" spp:%0d", csr_regfile$read_mstatus[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" pies:%0d_%0d%0d", - csr_regfile$read_mstatus[7], - csr_regfile$read_mstatus[5], - csr_regfile$read_mstatus[4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" ies:%0d_%0d%0d", - csr_regfile$read_mstatus[3], - csr_regfile$read_mstatus[1], - csr_regfile$read_mstatus[0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_full || !stage3_rg_stage3[37])) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full && stage3_rg_stage3[37]) - $write("Rd %0d ", - stage3_rg_stage3[36:32], - "rd_val:%h", - stage3_rg_stage3[31:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage2: pc 0x%08h instr 0x%08h priv %0d", - stage2_rg_stage2[167:136], - stage2_rg_stage2[135:104], - stage2_rg_stage2[169:168]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write("Output_Stage2", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[167:136]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("Output_Stage2", " NONPIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write("Output_Stage2", " PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[167:136], - stage2_rg_stage2[135:104], - stage2_rg_stage2[169:168]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3 && - stage2_rg_stage2[103:101] != 3'd0 && - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3 && - (stage2_rg_stage2[103:101] == 3'd0 || - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h5641, - x_out_data_to_stage3_rd_val__h5642); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", stage2_rg_stage2[167:136]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", near_mem$dmem_exc_code); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", stage2_rg_stage2[95:64], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", stage2_rg_stage2[167:136]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", near_mem$dmem_exc_code); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", stage2_rg_stage2[95:64], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == 2'd0) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != 2'd0) - $write("Rd %0d ", x_out_bypass_rd__h5992); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != 2'd1) - $write("rd_val:%h", x_out_bypass_rd_val__h5993); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage1: pc 0x%08h instr 0x%08h priv %0d", - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write("Output_Stage1", " BUSY pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write("Output_Stage1", " NONPIPE: pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write("Output_Stage1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) - $write("Output_Stage1", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(" PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd0) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd1) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd2) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd3) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd4) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd5) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd6) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd7) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd8) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd9) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd10) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d812) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n", - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(" op_stage2:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd0) - $write("OP_Stage2_ALU"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd1) - $write("OP_Stage2_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd2) - $write("OP_Stage2_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd3) - $write("OP_Stage2_M"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d849) - $write("OP_Stage2_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(" rd:%0d\n", x_out_data_to_stage2_rd__h11614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(" addr:%h val1:%h val2:%h}", - x_out_data_to_stage2_addr__h11615, - x_out_data_to_stage2_val1__h11616, - x_out_data_to_stage2_val2__h11617); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d949) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d952) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d955) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d958) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d961) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d964) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d967) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d970) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d973) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d976) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d979) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d982) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write("'h%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write("'h%h", x_out_trap_info_exc_code__h13233); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write("'h%h", value__h13281, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484) - $write(" next_pc 0x%08h", x_out_next_pc__h11584); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[167:136], - stage2_rg_stage2[135:104], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h2985 != 4'd0) - $display(" mcause:0x%0h epc 0x%0h tval:0x%0h new pc 0x%0h, new mstatus 0x%0h", - csr_regfile$csr_trap_actions[33:2], - stage2_rg_stage2[167:136], - stage2_rg_stage2[95:64], - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[65:34]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h11612[19:15], - rs1_val__h17231, - x_out_data_to_stage2_instr__h11612[31:20], - csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h11612[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h11612[19:15], - rs1_val__h17231, - x_out_data_to_stage2_instr__h11612[31:20], - x_out_data_to_stage2_instr__h11612[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_S_or_C", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h11612[19:15], - rs1_val__h17721, - x_out_data_to_stage2_instr__h11612[31:20], - csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h11612[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h11612[19:15], - rs1_val__h17721, - x_out_data_to_stage2_instr__h11612[31:20], - x_out_data_to_stage2_instr__h11612[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h11584); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d pc:%0x cur_priv:%0d", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - x_out_next_pc__h11584, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2985 != 4'd0) - $display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d", - csr_regfile$csr_ret_actions[65:34], - csr_regfile$csr_ret_actions[31:0], - csr_regfile$csr_ret_actions[33:32]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_stage1_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h2985 != 4'd0) - $display(" WFI resume"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_from_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270) - $display("%0d: CPU.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x", - csr_regfile$read_csr_mcycle, - csr_regfile$csr_trap_actions[97:66], - x_out_data_to_stage2_instr__h11612); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270) - $display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'", - cpi__h22287, - cpifrac__h22288, - delta_CPI_cycles__h22283, - _theResult____h22285); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2985 != 4'd0) - $display("%0d: CPU.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", - csr_regfile$read_csr_mcycle, - rg_cur_priv, - csr_regfile$csr_trap_actions[33:2], - imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2985 != 4'd0) - $display(" tval:0x%0h new pc:0x%0h new mstatus:0x%0h", - value__h13281, - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[65:34]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_trap_fetch && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11612, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2985 != 4'd0) - $display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", - csr_regfile$read_csr_mcycle, - imem_rg_pc, - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[1:0], - csr_regfile$csr_trap_actions[65:34]); - if (WILL_FIRE_RL_imem_rl_assert_fail) - $display("ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False"); - if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", - soc_map$m_pc_reset_value[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h", - csr_regfile$read_csr_mcycle, - soc_map$m_pc_reset_value[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[36:32], - stage3_rg_stage3[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" S3.enq: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[167:136], - stage2_rg_stage2[135:104], - stage2_rg_stage2[169:168]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - stage2_rg_stage2[103:101] != 3'd0 && - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - (stage2_rg_stage2[103:101] == 3'd0 || - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h5641, - x_out_data_to_stage3_rd_val__h5642); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - cur_verbosity__h2985 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[167:136], - stage2_rg_stage2[135:104], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage2.enq (Data_Stage1_to_Stage2)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h11584); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $write("CPU: Bluespec RISC-V Piccolo v3.0"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) $display(" (RV32)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h2985 != 4'd0) - $display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle); - end - // synopsys translate_on -endmodule // mkCPU - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v deleted file mode 100644 index df80ca60..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v +++ /dev/null @@ -1,141 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 32 -// fav_write O 32 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 32 -// EN_reset I 1 -// EN_fav_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIE(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [31 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [31 : 0] fav_write_wordxl; - input EN_fav_write; - output [31 : 0] fav_write; - - // signals for module outputs - wire [31 : 0] fav_write, fv_read; - - // register rg_mie - reg [11 : 0] rg_mie; - wire [11 : 0] rg_mie$D_IN; - wire rg_mie$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_write, - CAN_FIRE_reset, - WILL_FIRE_fav_write, - WILL_FIRE_reset; - - // remaining internal signals - wire [11 : 0] mie__h88; - wire seie__h119, ssie__h113, stie__h116, ueie__h118, usie__h112, utie__h115; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 20'd0, rg_mie } ; - - // actionvalue method fav_write - assign fav_write = { 20'd0, mie__h88 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // register rg_mie - assign rg_mie$D_IN = EN_fav_write ? mie__h88 : 12'd0 ; - assign rg_mie$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign mie__h88 = - { fav_write_wordxl[11], - 1'b0, - seie__h119, - ueie__h118, - fav_write_wordxl[7], - 1'b0, - stie__h116, - utie__h115, - fav_write_wordxl[3], - 1'b0, - ssie__h113, - usie__h112 } ; - assign seie__h119 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssie__h113 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign stie__h116 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueie__h118 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign usie__h112 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign utie__h115 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_mie = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIE - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v deleted file mode 100644 index fb4847d7..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v +++ /dev/null @@ -1,289 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 32 -// fav_write O 32 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 32 -// m_external_interrupt_req_req I 1 reg -// s_external_interrupt_req_req I 1 reg -// software_interrupt_req_req I 1 reg -// timer_interrupt_req_req I 1 reg -// EN_reset I 1 -// EN_fav_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIP(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - m_external_interrupt_req_req, - - s_external_interrupt_req_req, - - software_interrupt_req_req, - - timer_interrupt_req_req); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [31 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [31 : 0] fav_write_wordxl; - input EN_fav_write; - output [31 : 0] fav_write; - - // action method m_external_interrupt_req - input m_external_interrupt_req_req; - - // action method s_external_interrupt_req - input s_external_interrupt_req_req; - - // action method software_interrupt_req - input software_interrupt_req_req; - - // action method timer_interrupt_req - input timer_interrupt_req_req; - - // signals for module outputs - wire [31 : 0] fav_write, fv_read; - - // register rg_meip - reg rg_meip; - wire rg_meip$D_IN, rg_meip$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_seip - reg rg_seip; - wire rg_seip$D_IN, rg_seip$EN; - - // register rg_ssip - reg rg_ssip; - wire rg_ssip$D_IN, rg_ssip$EN; - - // register rg_stip - reg rg_stip; - wire rg_stip$D_IN, rg_stip$EN; - - // register rg_ueip - reg rg_ueip; - wire rg_ueip$D_IN, rg_ueip$EN; - - // register rg_usip - reg rg_usip; - wire rg_usip$D_IN, rg_usip$EN; - - // register rg_utip - reg rg_utip; - wire rg_utip$D_IN, rg_utip$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_write, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_reset, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_fav_write, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_reset, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // remaining internal signals - wire [11 : 0] new_mip__h524, new_mip__h942; - wire seip__h558, ssip__h562, stip__h560, ueip__h559, usip__h563, utip__h561; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 20'd0, new_mip__h524 } ; - - // actionvalue method fav_write - assign fav_write = { 20'd0, new_mip__h942 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // register rg_meip - assign rg_meip$D_IN = m_external_interrupt_req_req ; - assign rg_meip$EN = 1'b1 ; - - // register rg_msip - assign rg_msip$D_IN = software_interrupt_req_req ; - assign rg_msip$EN = 1'b1 ; - - // register rg_mtip - assign rg_mtip$D_IN = timer_interrupt_req_req ; - assign rg_mtip$EN = 1'b1 ; - - // register rg_seip - assign rg_seip$D_IN = s_external_interrupt_req_req ; - assign rg_seip$EN = 1'b1 ; - - // register rg_ssip - assign rg_ssip$D_IN = !EN_reset && ssip__h562 ; - assign rg_ssip$EN = EN_fav_write || EN_reset ; - - // register rg_stip - assign rg_stip$D_IN = !EN_reset && stip__h560 ; - assign rg_stip$EN = EN_fav_write || EN_reset ; - - // register rg_ueip - assign rg_ueip$D_IN = !EN_reset && ueip__h559 ; - assign rg_ueip$EN = EN_fav_write || EN_reset ; - - // register rg_usip - assign rg_usip$D_IN = !EN_reset && usip__h563 ; - assign rg_usip$EN = EN_fav_write || EN_reset ; - - // register rg_utip - assign rg_utip$D_IN = !EN_reset && utip__h561 ; - assign rg_utip$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign new_mip__h524 = - { rg_meip, - 1'b0, - rg_seip, - rg_ueip, - rg_mtip, - 1'b0, - rg_stip, - rg_utip, - rg_msip, - 1'b0, - rg_ssip, - rg_usip } ; - assign new_mip__h942 = - { rg_meip, - 1'b0, - seip__h558, - ueip__h559, - rg_mtip, - 1'b0, - stip__h560, - utip__h561, - rg_msip, - 1'b0, - ssip__h562, - usip__h563 } ; - assign seip__h558 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssip__h562 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign stip__h560 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueip__h559 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign usip__h563 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign utip__h561 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN; - if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN; - if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN; - if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN; - if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN; - if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_meip = 1'h0; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_seip = 1'h0; - rg_ssip = 1'h0; - rg_stip = 1'h0; - rg_ueip = 1'h0; - rg_usip = 1'h0; - rg_utip = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIP - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v deleted file mode 100644 index ea518626..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v +++ /dev/null @@ -1,2419 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_csr O 33 -// read_csr_port2 O 33 -// mav_read_csr O 33 -// mav_csr_write O 32 -// read_misa O 28 const -// read_mstatus O 32 reg -// read_ustatus O 32 -// read_satp O 32 const -// csr_trap_actions O 98 -// RDY_csr_trap_actions O 1 const -// csr_ret_actions O 66 -// RDY_csr_ret_actions O 1 const -// read_csr_minstret O 64 reg -// read_csr_mcycle O 64 reg -// read_csr_mtime O 64 reg -// access_permitted_1 O 1 -// access_permitted_2 O 1 -// csr_counter_read_fault O 1 -// csr_mip_read O 32 -// interrupt_pending O 5 -// wfi_resume O 1 -// nmi_pending O 1 reg -// RDY_debug O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// read_csr_csr_addr I 12 -// read_csr_port2_csr_addr I 12 -// mav_read_csr_csr_addr I 12 -// mav_csr_write_csr_addr I 12 -// mav_csr_write_word I 32 -// csr_trap_actions_from_priv I 2 -// csr_trap_actions_pc I 32 -// csr_trap_actions_nmi I 1 -// csr_trap_actions_interrupt I 1 -// csr_trap_actions_exc_code I 4 -// csr_trap_actions_xtval I 32 -// csr_ret_actions_from_priv I 2 -// access_permitted_1_priv I 2 -// access_permitted_1_csr_addr I 12 -// access_permitted_1_read_not_write I 1 -// access_permitted_2_priv I 2 -// access_permitted_2_csr_addr I 12 -// access_permitted_2_read_not_write I 1 -// csr_counter_read_fault_priv I 2 -// csr_counter_read_fault_csr_addr I 12 -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// interrupt_pending_cur_priv I 2 -// nmi_req_set_not_clear I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_csr_minstret_incr I 1 -// EN_debug I 1 unused -// EN_mav_read_csr I 1 unused -// EN_mav_csr_write I 1 -// EN_csr_trap_actions I 1 -// EN_csr_ret_actions I 1 -// -// Combinational paths from inputs to outputs: -// read_csr_csr_addr -> read_csr -// read_csr_port2_csr_addr -> read_csr_port2 -// (access_permitted_1_priv, -// access_permitted_1_csr_addr, -// access_permitted_1_read_not_write) -> access_permitted_1 -// (access_permitted_2_priv, -// access_permitted_2_csr_addr, -// access_permitted_2_read_not_write) -> access_permitted_2 -// (csr_counter_read_fault_priv, -// csr_counter_read_fault_csr_addr) -> csr_counter_read_fault -// interrupt_pending_cur_priv -> interrupt_pending -// mav_read_csr_csr_addr -> mav_read_csr -// (mav_csr_write_csr_addr, -// mav_csr_write_word, -// EN_mav_csr_write) -> mav_csr_write -// (csr_trap_actions_from_priv, -// csr_trap_actions_nmi, -// csr_trap_actions_interrupt, -// csr_trap_actions_exc_code) -> csr_trap_actions -// csr_ret_actions_from_priv -> csr_ret_actions -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_csr_csr_addr, - read_csr, - - read_csr_port2_csr_addr, - read_csr_port2, - - mav_read_csr_csr_addr, - EN_mav_read_csr, - mav_read_csr, - - mav_csr_write_csr_addr, - mav_csr_write_word, - EN_mav_csr_write, - mav_csr_write, - - read_misa, - - read_mstatus, - - read_ustatus, - - read_satp, - - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_nmi, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval, - EN_csr_trap_actions, - csr_trap_actions, - RDY_csr_trap_actions, - - csr_ret_actions_from_priv, - EN_csr_ret_actions, - csr_ret_actions, - RDY_csr_ret_actions, - - read_csr_minstret, - - EN_csr_minstret_incr, - - read_csr_mcycle, - - read_csr_mtime, - - access_permitted_1_priv, - access_permitted_1_csr_addr, - access_permitted_1_read_not_write, - access_permitted_1, - - access_permitted_2_priv, - access_permitted_2_csr_addr, - access_permitted_2_read_not_write, - access_permitted_2, - - csr_counter_read_fault_priv, - csr_counter_read_fault_csr_addr, - csr_counter_read_fault, - - csr_mip_read, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - interrupt_pending_cur_priv, - interrupt_pending, - - wfi_resume, - - nmi_req_set_not_clear, - - nmi_pending, - - EN_debug, - RDY_debug); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_csr - input [11 : 0] read_csr_csr_addr; - output [32 : 0] read_csr; - - // value method read_csr_port2 - input [11 : 0] read_csr_port2_csr_addr; - output [32 : 0] read_csr_port2; - - // actionvalue method mav_read_csr - input [11 : 0] mav_read_csr_csr_addr; - input EN_mav_read_csr; - output [32 : 0] mav_read_csr; - - // actionvalue method mav_csr_write - input [11 : 0] mav_csr_write_csr_addr; - input [31 : 0] mav_csr_write_word; - input EN_mav_csr_write; - output [31 : 0] mav_csr_write; - - // value method read_misa - output [27 : 0] read_misa; - - // value method read_mstatus - output [31 : 0] read_mstatus; - - // value method read_ustatus - output [31 : 0] read_ustatus; - - // value method read_satp - output [31 : 0] read_satp; - - // actionvalue method csr_trap_actions - input [1 : 0] csr_trap_actions_from_priv; - input [31 : 0] csr_trap_actions_pc; - input csr_trap_actions_nmi; - input csr_trap_actions_interrupt; - input [3 : 0] csr_trap_actions_exc_code; - input [31 : 0] csr_trap_actions_xtval; - input EN_csr_trap_actions; - output [97 : 0] csr_trap_actions; - output RDY_csr_trap_actions; - - // actionvalue method csr_ret_actions - input [1 : 0] csr_ret_actions_from_priv; - input EN_csr_ret_actions; - output [65 : 0] csr_ret_actions; - output RDY_csr_ret_actions; - - // value method read_csr_minstret - output [63 : 0] read_csr_minstret; - - // action method csr_minstret_incr - input EN_csr_minstret_incr; - - // value method read_csr_mcycle - output [63 : 0] read_csr_mcycle; - - // value method read_csr_mtime - output [63 : 0] read_csr_mtime; - - // value method access_permitted_1 - input [1 : 0] access_permitted_1_priv; - input [11 : 0] access_permitted_1_csr_addr; - input access_permitted_1_read_not_write; - output access_permitted_1; - - // value method access_permitted_2 - input [1 : 0] access_permitted_2_priv; - input [11 : 0] access_permitted_2_csr_addr; - input access_permitted_2_read_not_write; - output access_permitted_2; - - // value method csr_counter_read_fault - input [1 : 0] csr_counter_read_fault_priv; - input [11 : 0] csr_counter_read_fault_csr_addr; - output csr_counter_read_fault; - - // value method csr_mip_read - output [31 : 0] csr_mip_read; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // value method interrupt_pending - input [1 : 0] interrupt_pending_cur_priv; - output [4 : 0] interrupt_pending; - - // value method wfi_resume - output wfi_resume; - - // action method nmi_req - input nmi_req_set_not_clear; - - // value method nmi_pending - output nmi_pending; - - // action method debug - input EN_debug; - output RDY_debug; - - // signals for module outputs - wire [97 : 0] csr_trap_actions; - wire [65 : 0] csr_ret_actions; - wire [63 : 0] read_csr_mcycle, read_csr_minstret, read_csr_mtime; - wire [32 : 0] mav_read_csr, read_csr, read_csr_port2; - wire [31 : 0] csr_mip_read, - mav_csr_write, - read_mstatus, - read_satp, - read_ustatus; - wire [27 : 0] read_misa; - wire [4 : 0] interrupt_pending; - wire RDY_csr_ret_actions, - RDY_csr_trap_actions, - RDY_debug, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - access_permitted_1, - access_permitted_2, - csr_counter_read_fault, - nmi_pending, - wfi_resume; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register csr_mstatus_rg_mstatus - reg [31 : 0] csr_mstatus_rg_mstatus; - reg [31 : 0] csr_mstatus_rg_mstatus$D_IN; - wire csr_mstatus_rg_mstatus$EN; - - // register rg_dcsr - reg [31 : 0] rg_dcsr; - wire [31 : 0] rg_dcsr$D_IN; - wire rg_dcsr$EN; - - // register rg_dpc - reg [31 : 0] rg_dpc; - wire [31 : 0] rg_dpc$D_IN; - wire rg_dpc$EN; - - // register rg_dscratch0 - reg [31 : 0] rg_dscratch0; - wire [31 : 0] rg_dscratch0$D_IN; - wire rg_dscratch0$EN; - - // register rg_dscratch1 - reg [31 : 0] rg_dscratch1; - wire [31 : 0] rg_dscratch1$D_IN; - wire rg_dscratch1$EN; - - // register rg_mcause - reg [4 : 0] rg_mcause; - reg [4 : 0] rg_mcause$D_IN; - wire rg_mcause$EN; - - // register rg_mcounteren - reg [2 : 0] rg_mcounteren; - wire [2 : 0] rg_mcounteren$D_IN; - wire rg_mcounteren$EN; - - // register rg_mcycle - reg [63 : 0] rg_mcycle; - wire [63 : 0] rg_mcycle$D_IN; - wire rg_mcycle$EN; - - // register rg_mepc - reg [31 : 0] rg_mepc; - wire [31 : 0] rg_mepc$D_IN; - wire rg_mepc$EN; - - // register rg_minstret - reg [63 : 0] rg_minstret; - wire [63 : 0] rg_minstret$D_IN; - wire rg_minstret$EN; - - // register rg_mscratch - reg [31 : 0] rg_mscratch; - wire [31 : 0] rg_mscratch$D_IN; - wire rg_mscratch$EN; - - // register rg_mtval - reg [31 : 0] rg_mtval; - wire [31 : 0] rg_mtval$D_IN; - wire rg_mtval$EN; - - // register rg_mtvec - reg [30 : 0] rg_mtvec; - wire [30 : 0] rg_mtvec$D_IN; - wire rg_mtvec$EN; - - // register rg_nmi - reg rg_nmi; - wire rg_nmi$D_IN, rg_nmi$EN; - - // register rg_nmi_vector - reg [31 : 0] rg_nmi_vector; - wire [31 : 0] rg_nmi_vector$D_IN; - wire rg_nmi_vector$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_tdata1 - reg [31 : 0] rg_tdata1; - wire [31 : 0] rg_tdata1$D_IN; - wire rg_tdata1$EN; - - // register rg_tdata2 - reg [31 : 0] rg_tdata2; - wire [31 : 0] rg_tdata2$D_IN; - wire rg_tdata2$EN; - - // register rg_tdata3 - reg [31 : 0] rg_tdata3; - wire [31 : 0] rg_tdata3$D_IN; - wire rg_tdata3$EN; - - // register rg_tselect - reg [31 : 0] rg_tselect; - wire [31 : 0] rg_tselect$D_IN; - wire rg_tselect$EN; - - // ports of submodule csr_mie - wire [31 : 0] csr_mie$fav_write, csr_mie$fav_write_wordxl, csr_mie$fv_read; - wire [27 : 0] csr_mie$fav_write_misa; - wire csr_mie$EN_fav_write, csr_mie$EN_reset; - - // ports of submodule csr_mip - wire [31 : 0] csr_mip$fav_write, csr_mip$fav_write_wordxl, csr_mip$fv_read; - wire [27 : 0] csr_mip$fav_write_misa; - wire csr_mip$EN_fav_write, - csr_mip$EN_reset, - csr_mip$m_external_interrupt_req_req, - csr_mip$s_external_interrupt_req_req, - csr_mip$software_interrupt_req_req, - csr_mip$timer_interrupt_req_req; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mtvec_reset_value, - soc_map$m_nmivec_reset_value; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_mcycle_incr, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_upd_minstret_csrrx, - CAN_FIRE_RL_rl_upd_minstret_incr, - CAN_FIRE_csr_minstret_incr, - CAN_FIRE_csr_ret_actions, - CAN_FIRE_csr_trap_actions, - CAN_FIRE_debug, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_mav_csr_write, - CAN_FIRE_mav_read_csr, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_rl_mcycle_incr, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_upd_minstret_csrrx, - WILL_FIRE_RL_rl_upd_minstret_incr, - WILL_FIRE_csr_minstret_incr, - WILL_FIRE_csr_ret_actions, - WILL_FIRE_csr_trap_actions, - WILL_FIRE_debug, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_mav_csr_write, - WILL_FIRE_mav_read_csr, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_rg_minstret$write_1__VAL_1, - MUX_rg_minstret$write_1__VAL_2, - MUX_rw_minstret$wset_1__VAL_1; - wire [31 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_3; - wire [30 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; - wire [4 : 0] MUX_rg_mcause$write_1__VAL_2, MUX_rg_mcause$write_1__VAL_3; - wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_2, - MUX_rg_mcause$write_1__SEL_2, - MUX_rg_mcounteren$write_1__SEL_1, - MUX_rg_mepc$write_1__SEL_1, - MUX_rg_mtval$write_1__SEL_1, - MUX_rg_mtvec$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2, - MUX_rg_tdata1$write_1__SEL_1, - MUX_rw_minstret$wset_1__SEL_1; - - // remaining internal signals - reg [31 : 0] IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765, - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571, - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217, - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394; - wire [63 : 0] x__h5306, x__h5414; - wire [33 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1064; - wire [31 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046, - _theResult___fst__h8350, - _theResult___fst__h8551, - csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039, - exc_pc___1__h7435, - exc_pc__h7171, - exc_pc__h7382, - mask__h8371, - mask__h8388, - result__h5489, - v__h4656, - v__h4718, - v__h4874, - val__h8389, - vector_offset__h7383, - wordxl1__h4173, - x__h5982, - x__h8206, - x__h8207, - x__h8370, - x__h8383, - x__h8400, - y__h8384, - y__h8401; - wire [22 : 0] fixed_up_val_23__h4214, - fixed_up_val_23__h6610, - fixed_up_val_23__h8269; - wire [5 : 0] ie_from_x__h8334, pie_from_x__h8335; - wire [3 : 0] IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1366, - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1368, - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1370, - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1372, - exc_code__h8048; - wire [1 : 0] mpp__h7476, to_y__h8550; - wire NOT_access_permitted_1_csr_addr_ULT_0xC03_065__ETC___d1151, - NOT_access_permitted_2_csr_addr_ULT_0xC03_156__ETC___d1241, - NOT_cfg_verbosity_read__27_ULE_1_28___d729, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1330, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1335, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1340, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1345, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1350, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1355, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1360, - NOT_csr_trap_actions_nmi_93_AND_csr_trap_actio_ETC___d970, - NOT_mav_csr_write_csr_addr_ULT_0xB03_74_31_AND_ETC___d742, - b__h8387, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1284, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1289, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1294, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1299, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1304, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1309, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1314, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1319, - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1021, - mav_csr_write_csr_addr_ULE_0x33F___d583, - mav_csr_write_csr_addr_ULE_0xB1F___d575, - mav_csr_write_csr_addr_ULE_0xB9F___d579, - mav_csr_write_csr_addr_ULT_0x323_82_OR_NOT_mav_ETC___d724, - mav_csr_write_csr_addr_ULT_0x323___d582, - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587, - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d638, - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d726, - mav_csr_write_csr_addr_ULT_0xB03___d574, - mav_csr_write_csr_addr_ULT_0xB83___d578; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_csr - assign read_csr = - { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hC83 && read_csr_csr_addr <= 12'hC9F || - read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'hB83 && read_csr_csr_addr <= 12'hB9F || - read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || - read_csr_csr_addr == 12'hC00 || - read_csr_csr_addr == 12'hC02 || - read_csr_csr_addr == 12'hC80 || - read_csr_csr_addr == 12'hC82 || - read_csr_csr_addr == 12'hF11 || - read_csr_csr_addr == 12'hF12 || - read_csr_csr_addr == 12'hF13 || - read_csr_csr_addr == 12'hF14 || - read_csr_csr_addr == 12'h300 || - read_csr_csr_addr == 12'h301 || - read_csr_csr_addr == 12'h304 || - read_csr_csr_addr == 12'h305 || - read_csr_csr_addr == 12'h306 || - read_csr_csr_addr == 12'h340 || - read_csr_csr_addr == 12'h341 || - read_csr_csr_addr == 12'h342 || - read_csr_csr_addr == 12'h343 || - read_csr_csr_addr == 12'h344 || - read_csr_csr_addr == 12'hB00 || - read_csr_csr_addr == 12'hB02 || - read_csr_csr_addr == 12'hB80 || - read_csr_csr_addr == 12'hB82 || - read_csr_csr_addr == 12'h7A0 || - read_csr_csr_addr == 12'h7A1 || - read_csr_csr_addr == 12'h7A2 || - read_csr_csr_addr == 12'h7A3, - (read_csr_csr_addr >= 12'hC03 && - read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hC83 && - read_csr_csr_addr <= 12'hC9F || - read_csr_csr_addr >= 12'hB03 && - read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'hB83 && - read_csr_csr_addr <= 12'hB9F || - read_csr_csr_addr >= 12'h323 && - read_csr_csr_addr <= 12'h33F) ? - 32'd0 : - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 } ; - - // value method read_csr_port2 - assign read_csr_port2 = - { read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hC83 && - read_csr_port2_csr_addr <= 12'hC9F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'hB83 && - read_csr_port2_csr_addr <= 12'hB9F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F || - read_csr_port2_csr_addr == 12'hC00 || - read_csr_port2_csr_addr == 12'hC02 || - read_csr_port2_csr_addr == 12'hC80 || - read_csr_port2_csr_addr == 12'hC82 || - read_csr_port2_csr_addr == 12'hF11 || - read_csr_port2_csr_addr == 12'hF12 || - read_csr_port2_csr_addr == 12'hF13 || - read_csr_port2_csr_addr == 12'hF14 || - read_csr_port2_csr_addr == 12'h300 || - read_csr_port2_csr_addr == 12'h301 || - read_csr_port2_csr_addr == 12'h304 || - read_csr_port2_csr_addr == 12'h305 || - read_csr_port2_csr_addr == 12'h306 || - read_csr_port2_csr_addr == 12'h340 || - read_csr_port2_csr_addr == 12'h341 || - read_csr_port2_csr_addr == 12'h342 || - read_csr_port2_csr_addr == 12'h343 || - read_csr_port2_csr_addr == 12'h344 || - read_csr_port2_csr_addr == 12'hB00 || - read_csr_port2_csr_addr == 12'hB02 || - read_csr_port2_csr_addr == 12'hB80 || - read_csr_port2_csr_addr == 12'hB82 || - read_csr_port2_csr_addr == 12'h7A0 || - read_csr_port2_csr_addr == 12'h7A1 || - read_csr_port2_csr_addr == 12'h7A2 || - read_csr_port2_csr_addr == 12'h7A3, - (read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hC83 && - read_csr_port2_csr_addr <= 12'hC9F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'hB83 && - read_csr_port2_csr_addr <= 12'hB9F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F) ? - 32'd0 : - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 } ; - - // actionvalue method mav_read_csr - assign mav_read_csr = - { mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hC83 && - mav_read_csr_csr_addr <= 12'hC9F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'hB83 && - mav_read_csr_csr_addr <= 12'hB9F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F || - mav_read_csr_csr_addr == 12'hC00 || - mav_read_csr_csr_addr == 12'hC02 || - mav_read_csr_csr_addr == 12'hC80 || - mav_read_csr_csr_addr == 12'hC82 || - mav_read_csr_csr_addr == 12'hF11 || - mav_read_csr_csr_addr == 12'hF12 || - mav_read_csr_csr_addr == 12'hF13 || - mav_read_csr_csr_addr == 12'hF14 || - mav_read_csr_csr_addr == 12'h300 || - mav_read_csr_csr_addr == 12'h301 || - mav_read_csr_csr_addr == 12'h304 || - mav_read_csr_csr_addr == 12'h305 || - mav_read_csr_csr_addr == 12'h306 || - mav_read_csr_csr_addr == 12'h340 || - mav_read_csr_csr_addr == 12'h341 || - mav_read_csr_csr_addr == 12'h342 || - mav_read_csr_csr_addr == 12'h343 || - mav_read_csr_csr_addr == 12'h344 || - mav_read_csr_csr_addr == 12'hB00 || - mav_read_csr_csr_addr == 12'hB02 || - mav_read_csr_csr_addr == 12'hB80 || - mav_read_csr_csr_addr == 12'hB82 || - mav_read_csr_csr_addr == 12'h7A0 || - mav_read_csr_csr_addr == 12'h7A1 || - mav_read_csr_csr_addr == 12'h7A2 || - mav_read_csr_csr_addr == 12'h7A3, - (mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hC83 && - mav_read_csr_csr_addr <= 12'hC9F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'hB83 && - mav_read_csr_csr_addr <= 12'hB9F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F) ? - 32'd0 : - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 } ; - assign CAN_FIRE_mav_read_csr = 1'd1 ; - assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; - - // actionvalue method mav_csr_write - assign mav_csr_write = - NOT_mav_csr_write_csr_addr_ULT_0xB03_74_31_AND_ETC___d742 ? - 32'd0 : - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 ; - assign CAN_FIRE_mav_csr_write = 1'd1 ; - assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; - - // value method read_misa - assign read_misa = 28'd68161797 ; - - // value method read_mstatus - assign read_mstatus = csr_mstatus_rg_mstatus ; - - // value method read_ustatus - assign read_ustatus = - { 27'd0, - csr_mstatus_rg_mstatus[4], - 3'd0, - csr_mstatus_rg_mstatus[0] } ; - - // value method read_satp - assign read_satp = 32'hAAAAAAAA ; - - // actionvalue method csr_trap_actions - assign csr_trap_actions = { x__h5982, x__h8206, x__h8207, 2'b11 } ; - assign RDY_csr_trap_actions = 1'd1 ; - assign CAN_FIRE_csr_trap_actions = 1'd1 ; - assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; - - // actionvalue method csr_ret_actions - assign csr_ret_actions = - { rg_mepc, - IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1064 } ; - assign RDY_csr_ret_actions = 1'd1 ; - assign CAN_FIRE_csr_ret_actions = 1'd1 ; - assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; - - // value method read_csr_minstret - assign read_csr_minstret = rg_minstret ; - - // action method csr_minstret_incr - assign CAN_FIRE_csr_minstret_incr = 1'd1 ; - assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; - - // value method read_csr_mcycle - assign read_csr_mcycle = rg_mcycle ; - - // value method read_csr_mtime - assign read_csr_mtime = rg_mcycle ; - - // value method access_permitted_1 - assign access_permitted_1 = - NOT_access_permitted_1_csr_addr_ULT_0xC03_065__ETC___d1151 && - (access_permitted_1_read_not_write || - access_permitted_1_csr_addr[11:10] != 2'b11) ; - - // value method access_permitted_2 - assign access_permitted_2 = - NOT_access_permitted_2_csr_addr_ULT_0xC03_156__ETC___d1241 && - (access_permitted_2_read_not_write || - access_permitted_2_csr_addr[11:10] != 2'b11) ; - - // value method csr_counter_read_fault - assign csr_counter_read_fault = - (csr_counter_read_fault_priv == 2'b01 || - csr_counter_read_fault_priv == 2'b0) && - (csr_counter_read_fault_csr_addr == 12'hC00 && - !rg_mcounteren[0] || - csr_counter_read_fault_csr_addr == 12'hC01 && - !rg_mcounteren[1] || - csr_counter_read_fault_csr_addr == 12'hC02 && - !rg_mcounteren[2] || - csr_counter_read_fault_csr_addr >= 12'hC03 && - csr_counter_read_fault_csr_addr <= 12'hC1F || - csr_counter_read_fault_csr_addr >= 12'hC83 && - csr_counter_read_fault_csr_addr <= 12'hC9F) ; - - // value method csr_mip_read - assign csr_mip_read = csr_mip$fv_read ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // value method interrupt_pending - assign interrupt_pending = - { csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1319, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1360 ? - 4'd4 : - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1372 } ; - - // value method wfi_resume - assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 32'd0 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // value method nmi_pending - assign nmi_pending = rg_nmi ; - - // action method debug - assign RDY_debug = 1'd1 ; - assign CAN_FIRE_debug = 1'd1 ; - assign WILL_FIRE_debug = EN_debug ; - - // submodule csr_mie - mkCSR_MIE csr_mie(.CLK(CLK), - .RST_N(RST_N), - .fav_write_misa(csr_mie$fav_write_misa), - .fav_write_wordxl(csr_mie$fav_write_wordxl), - .EN_reset(csr_mie$EN_reset), - .EN_fav_write(csr_mie$EN_fav_write), - .fv_read(csr_mie$fv_read), - .fav_write(csr_mie$fav_write)); - - // submodule csr_mip - mkCSR_MIP csr_mip(.CLK(CLK), - .RST_N(RST_N), - .fav_write_misa(csr_mip$fav_write_misa), - .fav_write_wordxl(csr_mip$fav_write_wordxl), - .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), - .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), - .software_interrupt_req_req(csr_mip$software_interrupt_req_req), - .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), - .EN_reset(csr_mip$EN_reset), - .EN_fav_write(csr_mip$EN_fav_write), - .fv_read(csr_mip$fv_read), - .fav_write(csr_mip$fav_write)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), - .m_nmivec_reset_value(soc_map$m_nmivec_reset_value)); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = !rg_state ; - assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_mcycle_incr - assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; - assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; - - // rule RL_rl_upd_minstret_csrrx - assign CAN_FIRE_RL_rl_upd_minstret_csrrx = - MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; - assign WILL_FIRE_RL_rl_upd_minstret_csrrx = - CAN_FIRE_RL_rl_upd_minstret_csrrx ; - - // rule RL_rl_upd_minstret_incr - assign CAN_FIRE_RL_rl_upd_minstret_incr = - !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; - assign WILL_FIRE_RL_rl_upd_minstret_incr = - CAN_FIRE_RL_rl_upd_minstret_incr ; - - // inputs to muxes for submodule ports - assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h300 ; - assign MUX_rg_mcause$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h342 ; - assign MUX_rg_mcounteren$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h306 ; - assign MUX_rg_mepc$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h341 ; - assign MUX_rg_mtval$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h343 ; - assign MUX_rg_mtvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h305 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; - assign MUX_rg_tdata1$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h7A1 ; - assign MUX_rw_minstret$wset_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d638 && - (mav_csr_write_csr_addr == 12'hB02 || - mav_csr_write_csr_addr == 12'hB82) ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 = - { 9'd0, fixed_up_val_23__h8269 } ; - assign MUX_rg_mcause$write_1__VAL_2 = - { mav_csr_write_word[31], mav_csr_write_word[3:0] } ; - assign MUX_rg_mcause$write_1__VAL_3 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - exc_code__h8048 } ; - assign MUX_rg_minstret$write_1__VAL_1 = - MUX_rw_minstret$wset_1__SEL_1 ? - MUX_rw_minstret$wset_1__VAL_1 : - 64'd0 ; - assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; - assign MUX_rg_mtvec$write_1__VAL_1 = - { mav_csr_write_word[31:2], mav_csr_write_word[0] } ; - assign MUX_rg_mtvec$write_1__VAL_2 = - { soc_map$m_mtvec_reset_value[31:2], - soc_map$m_mtvec_reset_value[0] } ; - assign MUX_rw_minstret$wset_1__VAL_1 = - (mav_csr_write_csr_addr == 12'hB02) ? x__h5306 : x__h5414 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register csr_mstatus_rg_mstatus - always@(WILL_FIRE_RL_rl_reset_start or - MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 or - wordxl1__h4173 or - EN_csr_ret_actions or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 or - EN_csr_trap_actions or x__h8206) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: csr_mstatus_rg_mstatus$D_IN = 32'd0; - MUX_csr_mstatus_rg_mstatus$write_1__SEL_2: - csr_mstatus_rg_mstatus$D_IN = wordxl1__h4173; - EN_csr_ret_actions: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_3; - EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = x__h8206; - default: csr_mstatus_rg_mstatus$D_IN = - 32'hAAAAAAAA /* unspecified value */ ; - endcase - assign csr_mstatus_rg_mstatus$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h300 || - EN_csr_trap_actions || - EN_csr_ret_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_dcsr - assign rg_dcsr$D_IN = 32'h0 ; - assign rg_dcsr$EN = 1'b0 ; - - // register rg_dpc - assign rg_dpc$D_IN = 32'h0 ; - assign rg_dpc$EN = 1'b0 ; - - // register rg_dscratch0 - assign rg_dscratch0$D_IN = 32'h0 ; - assign rg_dscratch0$EN = 1'b0 ; - - // register rg_dscratch1 - assign rg_dscratch1$D_IN = 32'h0 ; - assign rg_dscratch1$EN = 1'b0 ; - - // register rg_mcause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_mcause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - EN_csr_trap_actions or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; - MUX_rg_mcause$write_1__SEL_2: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; - EN_csr_trap_actions: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_mcause$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h342 || - EN_csr_trap_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcounteren - assign rg_mcounteren$D_IN = - MUX_rg_mcounteren$write_1__SEL_1 ? - mav_csr_write_word[2:0] : - 3'd0 ; - assign rg_mcounteren$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h306 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcycle - assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; - assign rg_mcycle$EN = 1'd1 ; - - // register rg_mepc - assign rg_mepc$D_IN = - MUX_rg_mepc$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_pc ; - assign rg_mepc$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h341 || - EN_csr_trap_actions ; - - // register rg_minstret - assign rg_minstret$D_IN = - WILL_FIRE_RL_rl_upd_minstret_csrrx ? - MUX_rg_minstret$write_1__VAL_1 : - MUX_rg_minstret$write_1__VAL_2 ; - assign rg_minstret$EN = - WILL_FIRE_RL_rl_upd_minstret_csrrx || - WILL_FIRE_RL_rl_upd_minstret_incr ; - - // register rg_mscratch - assign rg_mscratch$D_IN = mav_csr_write_word ; - assign rg_mscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h340 ; - - // register rg_mtval - assign rg_mtval$D_IN = - MUX_rg_mtval$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_xtval ; - assign rg_mtval$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h343 || - EN_csr_trap_actions ; - - // register rg_mtvec - assign rg_mtvec$D_IN = - MUX_rg_mtvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_mtvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h305 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_nmi - assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ; - assign rg_nmi$EN = 1'b1 ; - - // register rg_nmi_vector - assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value[31:0] ; - assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_state - assign rg_state$D_IN = !EN_server_reset_request_put ; - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata1 - assign rg_tdata1$D_IN = - MUX_rg_tdata1$write_1__SEL_1 ? result__h5489 : 32'd0 ; - assign rg_tdata1$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h7A1 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata2 - assign rg_tdata2$D_IN = mav_csr_write_word ; - assign rg_tdata2$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h7A2 ; - - // register rg_tdata3 - assign rg_tdata3$D_IN = mav_csr_write_word ; - assign rg_tdata3$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h7A3 ; - - // register rg_tselect - assign rg_tselect$D_IN = 32'd0 ; - assign rg_tselect$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h7A0 || - WILL_FIRE_RL_rl_reset_start ; - - // submodule csr_mie - assign csr_mie$fav_write_misa = 28'd68161797 ; - assign csr_mie$fav_write_wordxl = mav_csr_write_word ; - assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mie$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h304 ; - - // submodule csr_mip - assign csr_mip$fav_write_misa = 28'd68161797 ; - assign csr_mip$fav_write_wordxl = mav_csr_write_word ; - assign csr_mip$m_external_interrupt_req_req = - m_external_interrupt_req_set_not_clear ; - assign csr_mip$s_external_interrupt_req_req = - s_external_interrupt_req_set_not_clear ; - assign csr_mip$software_interrupt_req_req = - software_interrupt_req_set_not_clear ; - assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; - assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mip$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h344 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1366 = - (!csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ? - 4'd3 : - 4'd11 ; - assign IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1368 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1335 ? - 4'd9 : - (NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1330 ? - 4'd7 : - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1366) ; - assign IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1370 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1345 ? - 4'd5 : - (NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1340 ? - 4'd1 : - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1368) ; - assign IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1372 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1355 ? - 4'd0 : - (NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1350 ? - 4'd8 : - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1370) ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046 = - (csr_ret_actions_from_priv == 2'b11) ? - _theResult___fst__h8350 : - _theResult___fst__h8551 ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1064 = - (csr_ret_actions_from_priv == 2'b11) ? - { csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[12:11], - _theResult___fst__h8350 } : - { to_y__h8550, _theResult___fst__h8551 } ; - assign NOT_access_permitted_1_csr_addr_ULT_0xC03_065__ETC___d1151 = - (access_permitted_1_csr_addr >= 12'hC03 && - access_permitted_1_csr_addr <= 12'hC1F || - access_permitted_1_csr_addr >= 12'hB03 && - access_permitted_1_csr_addr <= 12'hB1F || - access_permitted_1_csr_addr >= 12'hC83 && - access_permitted_1_csr_addr <= 12'hC9F || - access_permitted_1_csr_addr >= 12'hB83 && - access_permitted_1_csr_addr <= 12'hB9F || - access_permitted_1_csr_addr >= 12'h323 && - access_permitted_1_csr_addr <= 12'h33F || - access_permitted_1_csr_addr == 12'hC00 || - access_permitted_1_csr_addr == 12'hC02 || - access_permitted_1_csr_addr == 12'hC80 || - access_permitted_1_csr_addr == 12'hC81 || - access_permitted_1_csr_addr == 12'hC82 || - access_permitted_1_csr_addr == 12'hF11 || - access_permitted_1_csr_addr == 12'hF12 || - access_permitted_1_csr_addr == 12'hF13 || - access_permitted_1_csr_addr == 12'hF14 || - access_permitted_1_csr_addr == 12'h300 || - access_permitted_1_csr_addr == 12'h301 || - access_permitted_1_csr_addr == 12'h304 || - access_permitted_1_csr_addr == 12'h305 || - access_permitted_1_csr_addr == 12'h306 || - access_permitted_1_csr_addr == 12'h340 || - access_permitted_1_csr_addr == 12'h341 || - access_permitted_1_csr_addr == 12'h342 || - access_permitted_1_csr_addr == 12'h343 || - access_permitted_1_csr_addr == 12'h344 || - access_permitted_1_csr_addr == 12'hB00 || - access_permitted_1_csr_addr == 12'hB02 || - access_permitted_1_csr_addr == 12'hB80 || - access_permitted_1_csr_addr == 12'hB82 || - access_permitted_1_csr_addr == 12'h7A0 || - access_permitted_1_csr_addr == 12'h7A1 || - access_permitted_1_csr_addr == 12'h7A2 || - access_permitted_1_csr_addr == 12'h7A3) && - access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && - (access_permitted_1_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_access_permitted_2_csr_addr_ULT_0xC03_156__ETC___d1241 = - (access_permitted_2_csr_addr >= 12'hC03 && - access_permitted_2_csr_addr <= 12'hC1F || - access_permitted_2_csr_addr >= 12'hB03 && - access_permitted_2_csr_addr <= 12'hB1F || - access_permitted_2_csr_addr >= 12'hC83 && - access_permitted_2_csr_addr <= 12'hC9F || - access_permitted_2_csr_addr >= 12'hB83 && - access_permitted_2_csr_addr <= 12'hB9F || - access_permitted_2_csr_addr >= 12'h323 && - access_permitted_2_csr_addr <= 12'h33F || - access_permitted_2_csr_addr == 12'hC00 || - access_permitted_2_csr_addr == 12'hC02 || - access_permitted_2_csr_addr == 12'hC80 || - access_permitted_2_csr_addr == 12'hC81 || - access_permitted_2_csr_addr == 12'hC82 || - access_permitted_2_csr_addr == 12'hF11 || - access_permitted_2_csr_addr == 12'hF12 || - access_permitted_2_csr_addr == 12'hF13 || - access_permitted_2_csr_addr == 12'hF14 || - access_permitted_2_csr_addr == 12'h300 || - access_permitted_2_csr_addr == 12'h301 || - access_permitted_2_csr_addr == 12'h304 || - access_permitted_2_csr_addr == 12'h305 || - access_permitted_2_csr_addr == 12'h306 || - access_permitted_2_csr_addr == 12'h340 || - access_permitted_2_csr_addr == 12'h341 || - access_permitted_2_csr_addr == 12'h342 || - access_permitted_2_csr_addr == 12'h343 || - access_permitted_2_csr_addr == 12'h344 || - access_permitted_2_csr_addr == 12'hB00 || - access_permitted_2_csr_addr == 12'hB02 || - access_permitted_2_csr_addr == 12'hB80 || - access_permitted_2_csr_addr == 12'hB82 || - access_permitted_2_csr_addr == 12'h7A0 || - access_permitted_2_csr_addr == 12'h7A1 || - access_permitted_2_csr_addr == 12'h7A2 || - access_permitted_2_csr_addr == 12'h7A3) && - access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && - (access_permitted_2_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_cfg_verbosity_read__27_ULE_1_28___d729 = cfg_verbosity > 4'd1 ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1330 = - (!csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) && - (!csr_mip$fv_read[3] || !csr_mie$fv_read[3] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1335 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1330 && - (!csr_mip$fv_read[7] || !csr_mie$fv_read[7] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1340 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1335 && - (!csr_mip$fv_read[9] || !csr_mie$fv_read[9] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1345 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1340 && - (!csr_mip$fv_read[1] || !csr_mie$fv_read[1] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1350 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1345 && - (!csr_mip$fv_read[5] || !csr_mie$fv_read[5] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1355 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1350 && - (!csr_mip$fv_read[8] || !csr_mie$fv_read[8] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1360 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1355 && - (!csr_mip$fv_read[0] || !csr_mie$fv_read[0] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_trap_actions_nmi_93_AND_csr_trap_actio_ETC___d970 = - !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8048 != 4'd0 && - exc_code__h8048 != 4'd1 && - exc_code__h8048 != 4'd2 && - exc_code__h8048 != 4'd3 && - exc_code__h8048 != 4'd4 && - exc_code__h8048 != 4'd5 && - exc_code__h8048 != 4'd6 && - exc_code__h8048 != 4'd7 && - exc_code__h8048 != 4'd8 && - exc_code__h8048 != 4'd9 && - exc_code__h8048 != 4'd10 && - exc_code__h8048 != 4'd11 ; - assign NOT_mav_csr_write_csr_addr_ULT_0xB03_74_31_AND_ETC___d742 = - !mav_csr_write_csr_addr_ULT_0xB03___d574 && - mav_csr_write_csr_addr_ULE_0xB1F___d575 || - !mav_csr_write_csr_addr_ULT_0xB83___d578 && - mav_csr_write_csr_addr_ULE_0xB9F___d579 || - !mav_csr_write_csr_addr_ULT_0x323___d582 && - mav_csr_write_csr_addr_ULE_0x33F___d583 || - mav_csr_write_csr_addr == 12'hF11 || - mav_csr_write_csr_addr == 12'hF12 || - mav_csr_write_csr_addr == 12'hF13 || - mav_csr_write_csr_addr == 12'hF14 ; - assign _theResult___fst__h8350 = - { csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[31:13], - 2'd0, - csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[10:0] } ; - assign _theResult___fst__h8551 = - { csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[31:9], - 1'd0, - csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[7:0] } ; - assign b__h8387 = - csr_mstatus_rg_mstatus[{ 3'd1, csr_ret_actions_from_priv }] ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1284 = - csr_mip$fv_read[11] && csr_mie$fv_read[11] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) || - csr_mip$fv_read[3] && csr_mie$fv_read[3] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1289 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1284 || - csr_mip$fv_read[7] && csr_mie$fv_read[7] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1294 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1289 || - csr_mip$fv_read[9] && csr_mie$fv_read[9] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1299 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1294 || - csr_mip$fv_read[1] && csr_mie$fv_read[1] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1304 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1299 || - csr_mip$fv_read[5] && csr_mie$fv_read[5] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1309 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1304 || - csr_mip$fv_read[8] && csr_mie$fv_read[8] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1314 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1309 || - csr_mip$fv_read[0] && csr_mie$fv_read[0] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1319 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1314 || - csr_mip$fv_read[4] && csr_mie$fv_read[4] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039 = - x__h8383 | mask__h8371 ; - assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1021 = - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 != 4'd0 && - exc_code__h8048 != 4'd1 && - exc_code__h8048 != 4'd2 && - exc_code__h8048 != 4'd3 && - exc_code__h8048 != 4'd4 && - exc_code__h8048 != 4'd5 && - exc_code__h8048 != 4'd6 && - exc_code__h8048 != 4'd7 && - exc_code__h8048 != 4'd8 && - exc_code__h8048 != 4'd9 && - exc_code__h8048 != 4'd11 && - exc_code__h8048 != 4'd12 && - exc_code__h8048 != 4'd13 && - exc_code__h8048 != 4'd15 ; - assign exc_code__h8048 = - csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; - assign exc_pc___1__h7435 = exc_pc__h7382 + vector_offset__h7383 ; - assign exc_pc__h7171 = { rg_mtvec[30:1], 2'd0 } ; - assign exc_pc__h7382 = - csr_trap_actions_nmi ? rg_nmi_vector : exc_pc__h7171 ; - assign fixed_up_val_23__h4214 = - { mav_csr_write_word[22:17], - 4'd0, - (mav_csr_write_word[12:11] == 2'b11) ? - mav_csr_write_word[12:11] : - 2'b0, - mav_csr_write_word[10:9], - 1'd0, - mav_csr_write_word[7:6], - 2'd0, - mav_csr_write_word[3:2], - 2'd0 } ; - assign fixed_up_val_23__h6610 = - { csr_mstatus_rg_mstatus[22:17], - 4'd0, - mpp__h7476, - csr_mstatus_rg_mstatus[10:9], - 1'd0, - csr_mstatus_rg_mstatus[3], - csr_mstatus_rg_mstatus[6], - 3'd0, - csr_mstatus_rg_mstatus[2], - 2'd0 } ; - assign fixed_up_val_23__h8269 = - { IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[22:17], - 4'd0, - (IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[12:11] == - 2'b11) ? - IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[12:11] : - 2'b0, - IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[10:9], - 1'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[7:6], - 2'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[3:2], - 2'd0 } ; - assign ie_from_x__h8334 = { 4'd0, csr_ret_actions_from_priv } ; - assign mask__h8371 = 32'd1 << pie_from_x__h8335 ; - assign mask__h8388 = 32'd1 << ie_from_x__h8334 ; - assign mav_csr_write_csr_addr_ULE_0x33F___d583 = - mav_csr_write_csr_addr <= 12'h33F ; - assign mav_csr_write_csr_addr_ULE_0xB1F___d575 = - mav_csr_write_csr_addr <= 12'hB1F ; - assign mav_csr_write_csr_addr_ULE_0xB9F___d579 = - mav_csr_write_csr_addr <= 12'hB9F ; - assign mav_csr_write_csr_addr_ULT_0x323_82_OR_NOT_mav_ETC___d724 = - (mav_csr_write_csr_addr_ULT_0x323___d582 || - !mav_csr_write_csr_addr_ULE_0x33F___d583) && - mav_csr_write_csr_addr != 12'hF11 && - mav_csr_write_csr_addr != 12'hF12 && - mav_csr_write_csr_addr != 12'hF13 && - mav_csr_write_csr_addr != 12'hF14 && - mav_csr_write_csr_addr != 12'h300 && - mav_csr_write_csr_addr != 12'h301 && - mav_csr_write_csr_addr != 12'h304 && - mav_csr_write_csr_addr != 12'h305 && - mav_csr_write_csr_addr != 12'h306 && - mav_csr_write_csr_addr != 12'h340 && - mav_csr_write_csr_addr != 12'h341 && - mav_csr_write_csr_addr != 12'h342 && - mav_csr_write_csr_addr != 12'h343 && - mav_csr_write_csr_addr != 12'h344 && - mav_csr_write_csr_addr != 12'hB00 && - mav_csr_write_csr_addr != 12'hB02 && - mav_csr_write_csr_addr != 12'hB80 && - mav_csr_write_csr_addr != 12'hB82 && - mav_csr_write_csr_addr != 12'h7A0 && - mav_csr_write_csr_addr != 12'h7A1 && - mav_csr_write_csr_addr != 12'h7A2 && - mav_csr_write_csr_addr != 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0x323___d582 = - mav_csr_write_csr_addr < 12'h323 ; - assign mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 = - (mav_csr_write_csr_addr_ULT_0xB03___d574 || - !mav_csr_write_csr_addr_ULE_0xB1F___d575) && - (mav_csr_write_csr_addr_ULT_0xB83___d578 || - !mav_csr_write_csr_addr_ULE_0xB9F___d579) && - (mav_csr_write_csr_addr_ULT_0x323___d582 || - !mav_csr_write_csr_addr_ULE_0x33F___d583) ; - assign mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d638 = - (mav_csr_write_csr_addr_ULT_0xB03___d574 || - !mav_csr_write_csr_addr_ULE_0xB1F___d575) && - (mav_csr_write_csr_addr_ULT_0xB83___d578 || - !mav_csr_write_csr_addr_ULE_0xB9F___d579) && - (mav_csr_write_csr_addr_ULT_0x323___d582 || - !mav_csr_write_csr_addr_ULE_0x33F___d583) && - mav_csr_write_csr_addr != 12'hF11 && - mav_csr_write_csr_addr != 12'hF12 && - mav_csr_write_csr_addr != 12'hF13 && - mav_csr_write_csr_addr != 12'hF14 ; - assign mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d726 = - (mav_csr_write_csr_addr_ULT_0xB03___d574 || - !mav_csr_write_csr_addr_ULE_0xB1F___d575) && - (mav_csr_write_csr_addr_ULT_0xB83___d578 || - !mav_csr_write_csr_addr_ULE_0xB9F___d579) && - mav_csr_write_csr_addr_ULT_0x323_82_OR_NOT_mav_ETC___d724 ; - assign mav_csr_write_csr_addr_ULT_0xB03___d574 = - mav_csr_write_csr_addr < 12'hB03 ; - assign mav_csr_write_csr_addr_ULT_0xB83___d578 = - mav_csr_write_csr_addr < 12'hB83 ; - assign mpp__h7476 = - (csr_trap_actions_from_priv == 2'b11) ? - csr_trap_actions_from_priv : - 2'b0 ; - assign pie_from_x__h8335 = { 4'd1, csr_ret_actions_from_priv } ; - assign result__h5489 = { 4'd0, mav_csr_write_word[27:0] } ; - assign to_y__h8550 = - { 1'b0, - csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[8] } ; - assign v__h4656 = - { mav_csr_write_word[31:2], 1'b0, mav_csr_write_word[0] } ; - assign v__h4718 = { 29'd0, mav_csr_write_word[2:0] } ; - assign v__h4874 = - { mav_csr_write_word[31], 27'd0, mav_csr_write_word[3:0] } ; - assign val__h8389 = { 31'd0, b__h8387 } << ie_from_x__h8334 ; - assign vector_offset__h7383 = { 26'd0, csr_trap_actions_exc_code, 2'd0 } ; - assign wordxl1__h4173 = { 9'd0, fixed_up_val_23__h4214 } ; - assign x__h5306 = { rg_minstret[63:32], mav_csr_write_word } ; - assign x__h5414 = { mav_csr_write_word, rg_minstret[31:0] } ; - assign x__h5982 = - (csr_trap_actions_interrupt && !csr_trap_actions_nmi && - rg_mtvec[0]) ? - exc_pc___1__h7435 : - exc_pc__h7382 ; - assign x__h8206 = { 9'd0, fixed_up_val_23__h6610 } ; - assign x__h8207 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - 27'd0, - exc_code__h8048 } ; - assign x__h8370 = x__h8400 | val__h8389 ; - assign x__h8383 = x__h8370 & y__h8384 ; - assign x__h8400 = csr_mstatus_rg_mstatus & y__h8401 ; - assign y__h8384 = ~mask__h8371 ; - assign y__h8401 = ~mask__h8388 ; - always@(read_csr_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_csr_addr) - 12'h300: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - 32'd1074794757; - 12'h304: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_mscratch; - 12'h341: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = rg_mepc; - 12'h342: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_mtval; - 12'h344: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_tselect; - 12'h7A1: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_tdata1; - 12'h7A2: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_minstret[63:32]; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = 32'd0; - default: IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_tdata3; - endcase - end - always@(read_csr_port2_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_port2_csr_addr) - 12'h300: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - 32'd1074794757; - 12'h304: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_mscratch; - 12'h341: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = rg_mepc; - 12'h342: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_mtval; - 12'h344: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_tselect; - 12'h7A1: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_tdata1; - 12'h7A2: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_minstret[63:32]; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = 32'd0; - default: IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_tdata3; - endcase - end - always@(mav_read_csr_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (mav_read_csr_csr_addr) - 12'h300: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - 32'd1074794757; - 12'h304: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - csr_mie$fv_read; - 12'h305: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_mscratch; - 12'h341: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = rg_mepc; - 12'h342: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_mtval; - 12'h344: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - csr_mip$fv_read; - 12'h7A0: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_tselect; - 12'h7A1: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_tdata1; - 12'h7A2: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_minstret[63:32]; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = 32'd0; - default: IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_tdata3; - endcase - end - always@(mav_csr_write_csr_addr or - wordxl1__h4173 or - csr_mie$fav_write or - v__h4656 or - v__h4718 or - mav_csr_write_word or - v__h4874 or csr_mip$fav_write or result__h5489) - begin - case (mav_csr_write_csr_addr) - 12'h300: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - wordxl1__h4173; - 12'h301, 12'h7A0: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = 32'd0; - 12'h304: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - csr_mie$fav_write; - 12'h305: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - v__h4656; - 12'h306: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - v__h4718; - 12'h340, - 12'h341, - 12'h343, - 12'h7A2, - 12'h7A3, - 12'hB00, - 12'hB02, - 12'hB80, - 12'hB82: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - mav_csr_write_word; - 12'h342: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - v__h4874; - 12'h344: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - csr_mip$fav_write; - 12'h7A1: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - result__h5489; - default: IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - 32'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 32'd0; - rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (csr_mstatus_rg_mstatus$EN) - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY - csr_mstatus_rg_mstatus$D_IN; - if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; - if (rg_minstret$EN) - rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; - if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; - if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; - if (rg_dscratch0$EN) - rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; - if (rg_dscratch1$EN) - rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; - if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; - if (rg_mcounteren$EN) - rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; - if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; - if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; - if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; - if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; - if (rg_nmi_vector$EN) - rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN; - if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; - if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; - if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; - if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - csr_mstatus_rg_mstatus = 32'hAAAAAAAA; - rg_dcsr = 32'hAAAAAAAA; - rg_dpc = 32'hAAAAAAAA; - rg_dscratch0 = 32'hAAAAAAAA; - rg_dscratch1 = 32'hAAAAAAAA; - rg_mcause = 5'h0A; - rg_mcounteren = 3'h2; - rg_mcycle = 64'hAAAAAAAAAAAAAAAA; - rg_mepc = 32'hAAAAAAAA; - rg_minstret = 64'hAAAAAAAAAAAAAAAA; - rg_mscratch = 32'hAAAAAAAA; - rg_mtval = 32'hAAAAAAAA; - rg_mtvec = 31'h2AAAAAAA; - rg_nmi = 1'h0; - rg_nmi_vector = 32'hAAAAAAAA; - rg_state = 1'h0; - rg_tdata1 = 32'hAAAAAAAA; - rg_tdata2 = 32'hAAAAAAAA; - rg_tdata3 = 32'hAAAAAAAA; - rg_tselect = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" priv %0d: ", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" edeleg: 0x%0h", 16'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" ideleg: 0x%0h", 12'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd10 && - rg_mcause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd11 && - rg_mcause[3:0] != 4'd12 && - rg_mcause[3:0] != 4'd13 && - rg_mcause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" status: 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" tvec: 0x%0h", { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" epc: 0x%0h", rg_mepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" tval: 0x%0h", rg_mtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" Return: new pc 0x%0h ", x__h5982); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" new mstatus:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write("MStatus{", "sd:%0d", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" tsr:%0d", csr_mstatus_rg_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" tw:%0d", csr_mstatus_rg_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" tvm:%0d", csr_mstatus_rg_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" mxr:%0d", csr_mstatus_rg_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" sum:%0d", csr_mstatus_rg_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" mprv:%0d", csr_mstatus_rg_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" xs:%0d", 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" fs:%0d", 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" mpp:%0d", mpp__h7476); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" spp:%0d", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" pies:%0d_%0d%0d", csr_mstatus_rg_mstatus[3], 1'd0, 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" ies:%0d_%0d%0d", 1'd0, 1'd0, 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" new xcause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - NOT_csr_trap_actions_nmi_93_AND_csr_trap_actio_ETC___d970) - $write("unknown interrupt Exc_Code %d", exc_code__h8048); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1021) - $write("unknown trap Exc_Code %d", exc_code__h8048); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" new priv %0d", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d726 && - NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", - rg_mcycle, - mav_csr_write_csr_addr, - mav_csr_write_word); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", - rg_mcycle, - m_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", - rg_mcycle, - s_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: CSR_RegFile: software_interrupt_req: %x", - rg_mcycle, - software_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: CSR_RegFile: timer_interrupt_req: %x", - rg_mcycle, - timer_interrupt_req_set_not_clear); - end - // synopsys translate_on -endmodule // mkCSR_RegFile - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCore.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCore.v deleted file mode 100644 index d4c0ffcf..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkCore.v +++ /dev/null @@ -1,2497 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// cpu_reset_server_response_get O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg -// cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg -// cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg -// cpu_imem_master_bready O 1 -// cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg -// cpu_imem_master_rready O 1 -// cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg -// cpu_dmem_master_awaddr O 64 reg -// cpu_dmem_master_awlen O 8 reg -// cpu_dmem_master_awsize O 3 reg -// cpu_dmem_master_awburst O 2 reg -// cpu_dmem_master_awlock O 1 reg -// cpu_dmem_master_awcache O 4 reg -// cpu_dmem_master_awprot O 3 reg -// cpu_dmem_master_awqos O 4 reg -// cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg -// cpu_dmem_master_wdata O 64 reg -// cpu_dmem_master_wstrb O 8 reg -// cpu_dmem_master_wlast O 1 reg -// cpu_dmem_master_bready O 1 reg -// cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg -// cpu_dmem_master_araddr O 64 reg -// cpu_dmem_master_arlen O 8 reg -// cpu_dmem_master_arsize O 3 reg -// cpu_dmem_master_arburst O 2 reg -// cpu_dmem_master_arlock O 1 reg -// cpu_dmem_master_arcache O 4 reg -// cpu_dmem_master_arprot O 3 reg -// cpu_dmem_master_arqos O 4 reg -// cpu_dmem_master_arregion O 4 reg -// cpu_dmem_master_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// cpu_reset_server_request_put I 1 reg -// cpu_imem_master_awready I 1 -// cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg -// cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg -// cpu_dmem_master_awready I 1 -// cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg -// cpu_dmem_master_bresp I 2 reg -// cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg -// cpu_dmem_master_rdata I 64 reg -// cpu_dmem_master_rresp I 2 reg -// cpu_dmem_master_rlast I 1 reg -// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// nmi_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCore(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - cpu_reset_server_request_put, - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, - - cpu_imem_master_awvalid, - - cpu_imem_master_awid, - - cpu_imem_master_awaddr, - - cpu_imem_master_awlen, - - cpu_imem_master_awsize, - - cpu_imem_master_awburst, - - cpu_imem_master_awlock, - - cpu_imem_master_awcache, - - cpu_imem_master_awprot, - - cpu_imem_master_awqos, - - cpu_imem_master_awregion, - - cpu_imem_master_awready, - - cpu_imem_master_wvalid, - - cpu_imem_master_wid, - - cpu_imem_master_wdata, - - cpu_imem_master_wstrb, - - cpu_imem_master_wlast, - - cpu_imem_master_wready, - - cpu_imem_master_bvalid, - cpu_imem_master_bid, - cpu_imem_master_bresp, - - cpu_imem_master_bready, - - cpu_imem_master_arvalid, - - cpu_imem_master_arid, - - cpu_imem_master_araddr, - - cpu_imem_master_arlen, - - cpu_imem_master_arsize, - - cpu_imem_master_arburst, - - cpu_imem_master_arlock, - - cpu_imem_master_arcache, - - cpu_imem_master_arprot, - - cpu_imem_master_arqos, - - cpu_imem_master_arregion, - - cpu_imem_master_arready, - - cpu_imem_master_rvalid, - cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast, - - cpu_imem_master_rready, - - cpu_dmem_master_awvalid, - - cpu_dmem_master_awid, - - cpu_dmem_master_awaddr, - - cpu_dmem_master_awlen, - - cpu_dmem_master_awsize, - - cpu_dmem_master_awburst, - - cpu_dmem_master_awlock, - - cpu_dmem_master_awcache, - - cpu_dmem_master_awprot, - - cpu_dmem_master_awqos, - - cpu_dmem_master_awregion, - - cpu_dmem_master_awready, - - cpu_dmem_master_wvalid, - - cpu_dmem_master_wid, - - cpu_dmem_master_wdata, - - cpu_dmem_master_wstrb, - - cpu_dmem_master_wlast, - - cpu_dmem_master_wready, - - cpu_dmem_master_bvalid, - cpu_dmem_master_bid, - cpu_dmem_master_bresp, - - cpu_dmem_master_bready, - - cpu_dmem_master_arvalid, - - cpu_dmem_master_arid, - - cpu_dmem_master_araddr, - - cpu_dmem_master_arlen, - - cpu_dmem_master_arsize, - - cpu_dmem_master_arburst, - - cpu_dmem_master_arlock, - - cpu_dmem_master_arcache, - - cpu_dmem_master_arprot, - - cpu_dmem_master_arqos, - - cpu_dmem_master_arregion, - - cpu_dmem_master_arready, - - cpu_dmem_master_rvalid, - cpu_dmem_master_rid, - cpu_dmem_master_rdata, - cpu_dmem_master_rresp, - cpu_dmem_master_rlast, - - cpu_dmem_master_rready, - - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - - nmi_req_set_not_clear); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method cpu_reset_server_request_put - input cpu_reset_server_request_put; - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // actionvalue method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; - - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; - - // value method cpu_imem_master_m_awaddr - output [63 : 0] cpu_imem_master_awaddr; - - // value method cpu_imem_master_m_awlen - output [7 : 0] cpu_imem_master_awlen; - - // value method cpu_imem_master_m_awsize - output [2 : 0] cpu_imem_master_awsize; - - // value method cpu_imem_master_m_awburst - output [1 : 0] cpu_imem_master_awburst; - - // value method cpu_imem_master_m_awlock - output cpu_imem_master_awlock; - - // value method cpu_imem_master_m_awcache - output [3 : 0] cpu_imem_master_awcache; - - // value method cpu_imem_master_m_awprot - output [2 : 0] cpu_imem_master_awprot; - - // value method cpu_imem_master_m_awqos - output [3 : 0] cpu_imem_master_awqos; - - // value method cpu_imem_master_m_awregion - output [3 : 0] cpu_imem_master_awregion; - - // value method cpu_imem_master_m_awuser - - // action method cpu_imem_master_m_awready - input cpu_imem_master_awready; - - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; - - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - - // value method cpu_imem_master_m_wdata - output [63 : 0] cpu_imem_master_wdata; - - // value method cpu_imem_master_m_wstrb - output [7 : 0] cpu_imem_master_wstrb; - - // value method cpu_imem_master_m_wlast - output cpu_imem_master_wlast; - - // value method cpu_imem_master_m_wuser - - // action method cpu_imem_master_m_wready - input cpu_imem_master_wready; - - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; - input [1 : 0] cpu_imem_master_bresp; - - // value method cpu_imem_master_m_bready - output cpu_imem_master_bready; - - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; - - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; - - // value method cpu_imem_master_m_araddr - output [63 : 0] cpu_imem_master_araddr; - - // value method cpu_imem_master_m_arlen - output [7 : 0] cpu_imem_master_arlen; - - // value method cpu_imem_master_m_arsize - output [2 : 0] cpu_imem_master_arsize; - - // value method cpu_imem_master_m_arburst - output [1 : 0] cpu_imem_master_arburst; - - // value method cpu_imem_master_m_arlock - output cpu_imem_master_arlock; - - // value method cpu_imem_master_m_arcache - output [3 : 0] cpu_imem_master_arcache; - - // value method cpu_imem_master_m_arprot - output [2 : 0] cpu_imem_master_arprot; - - // value method cpu_imem_master_m_arqos - output [3 : 0] cpu_imem_master_arqos; - - // value method cpu_imem_master_m_arregion - output [3 : 0] cpu_imem_master_arregion; - - // value method cpu_imem_master_m_aruser - - // action method cpu_imem_master_m_arready - input cpu_imem_master_arready; - - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; - input [63 : 0] cpu_imem_master_rdata; - input [1 : 0] cpu_imem_master_rresp; - input cpu_imem_master_rlast; - - // value method cpu_imem_master_m_rready - output cpu_imem_master_rready; - - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; - - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; - - // value method cpu_dmem_master_m_awaddr - output [63 : 0] cpu_dmem_master_awaddr; - - // value method cpu_dmem_master_m_awlen - output [7 : 0] cpu_dmem_master_awlen; - - // value method cpu_dmem_master_m_awsize - output [2 : 0] cpu_dmem_master_awsize; - - // value method cpu_dmem_master_m_awburst - output [1 : 0] cpu_dmem_master_awburst; - - // value method cpu_dmem_master_m_awlock - output cpu_dmem_master_awlock; - - // value method cpu_dmem_master_m_awcache - output [3 : 0] cpu_dmem_master_awcache; - - // value method cpu_dmem_master_m_awprot - output [2 : 0] cpu_dmem_master_awprot; - - // value method cpu_dmem_master_m_awqos - output [3 : 0] cpu_dmem_master_awqos; - - // value method cpu_dmem_master_m_awregion - output [3 : 0] cpu_dmem_master_awregion; - - // value method cpu_dmem_master_m_awuser - - // action method cpu_dmem_master_m_awready - input cpu_dmem_master_awready; - - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; - - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - - // value method cpu_dmem_master_m_wdata - output [63 : 0] cpu_dmem_master_wdata; - - // value method cpu_dmem_master_m_wstrb - output [7 : 0] cpu_dmem_master_wstrb; - - // value method cpu_dmem_master_m_wlast - output cpu_dmem_master_wlast; - - // value method cpu_dmem_master_m_wuser - - // action method cpu_dmem_master_m_wready - input cpu_dmem_master_wready; - - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; - input [1 : 0] cpu_dmem_master_bresp; - - // value method cpu_dmem_master_m_bready - output cpu_dmem_master_bready; - - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; - - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; - - // value method cpu_dmem_master_m_araddr - output [63 : 0] cpu_dmem_master_araddr; - - // value method cpu_dmem_master_m_arlen - output [7 : 0] cpu_dmem_master_arlen; - - // value method cpu_dmem_master_m_arsize - output [2 : 0] cpu_dmem_master_arsize; - - // value method cpu_dmem_master_m_arburst - output [1 : 0] cpu_dmem_master_arburst; - - // value method cpu_dmem_master_m_arlock - output cpu_dmem_master_arlock; - - // value method cpu_dmem_master_m_arcache - output [3 : 0] cpu_dmem_master_arcache; - - // value method cpu_dmem_master_m_arprot - output [2 : 0] cpu_dmem_master_arprot; - - // value method cpu_dmem_master_m_arqos - output [3 : 0] cpu_dmem_master_arqos; - - // value method cpu_dmem_master_m_arregion - output [3 : 0] cpu_dmem_master_arregion; - - // value method cpu_dmem_master_m_aruser - - // action method cpu_dmem_master_m_arready - input cpu_dmem_master_arready; - - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; - input [63 : 0] cpu_dmem_master_rdata; - input [1 : 0] cpu_dmem_master_rresp; - input cpu_dmem_master_rlast; - - // value method cpu_dmem_master_m_rready - output cpu_dmem_master_rready; - - // action method core_external_interrupt_sources_0_m_interrupt_req - input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_1_m_interrupt_req - input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_2_m_interrupt_req - input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_3_m_interrupt_req - input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_4_m_interrupt_req - input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_5_m_interrupt_req - input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_6_m_interrupt_req - input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_7_m_interrupt_req - input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_8_m_interrupt_req - input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_9_m_interrupt_req - input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_10_m_interrupt_req - input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_11_m_interrupt_req - input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_12_m_interrupt_req - input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_13_m_interrupt_req - input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_14_m_interrupt_req - input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_15_m_interrupt_req - input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // signals for module outputs - wire [63 : 0] cpu_dmem_master_araddr, - cpu_dmem_master_awaddr, - cpu_dmem_master_wdata, - cpu_imem_master_araddr, - cpu_imem_master_awaddr, - cpu_imem_master_wdata; - wire [7 : 0] cpu_dmem_master_arlen, - cpu_dmem_master_awlen, - cpu_dmem_master_wstrb, - cpu_imem_master_arlen, - cpu_imem_master_awlen, - cpu_imem_master_wstrb; - wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, - cpu_dmem_master_arqos, - cpu_dmem_master_arregion, - cpu_dmem_master_awcache, - cpu_dmem_master_awid, - cpu_dmem_master_awqos, - cpu_dmem_master_awregion, - cpu_dmem_master_wid, - cpu_imem_master_arcache, - cpu_imem_master_arid, - cpu_imem_master_arqos, - cpu_imem_master_arregion, - cpu_imem_master_awcache, - cpu_imem_master_awid, - cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; - wire [2 : 0] cpu_dmem_master_arprot, - cpu_dmem_master_arsize, - cpu_dmem_master_awprot, - cpu_dmem_master_awsize, - cpu_imem_master_arprot, - cpu_imem_master_arsize, - cpu_imem_master_awprot, - cpu_imem_master_awsize; - wire [1 : 0] cpu_dmem_master_arburst, - cpu_dmem_master_awburst, - cpu_imem_master_arburst, - cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_set_verbosity, - cpu_dmem_master_arlock, - cpu_dmem_master_arvalid, - cpu_dmem_master_awlock, - cpu_dmem_master_awvalid, - cpu_dmem_master_bready, - cpu_dmem_master_rready, - cpu_dmem_master_wlast, - cpu_dmem_master_wvalid, - cpu_imem_master_arlock, - cpu_imem_master_arvalid, - cpu_imem_master_awlock, - cpu_imem_master_awvalid, - cpu_imem_master_bready, - cpu_imem_master_rready, - cpu_imem_master_wlast, - cpu_imem_master_wvalid, - cpu_reset_server_response_get; - - // ports of submodule cpu - wire [63 : 0] cpu$dmem_master_araddr, - cpu$dmem_master_awaddr, - cpu$dmem_master_rdata, - cpu$dmem_master_wdata, - cpu$imem_master_araddr, - cpu$imem_master_awaddr, - cpu$imem_master_rdata, - cpu$imem_master_wdata, - cpu$set_verbosity_logdelay; - wire [7 : 0] cpu$dmem_master_arlen, - cpu$dmem_master_awlen, - cpu$dmem_master_wstrb, - cpu$imem_master_arlen, - cpu$imem_master_awlen, - cpu$imem_master_wstrb; - wire [3 : 0] cpu$dmem_master_arcache, - cpu$dmem_master_arid, - cpu$dmem_master_arqos, - cpu$dmem_master_arregion, - cpu$dmem_master_awcache, - cpu$dmem_master_awid, - cpu$dmem_master_awqos, - cpu$dmem_master_awregion, - cpu$dmem_master_bid, - cpu$dmem_master_rid, - cpu$dmem_master_wid, - cpu$imem_master_arcache, - cpu$imem_master_arid, - cpu$imem_master_arqos, - cpu$imem_master_arregion, - cpu$imem_master_awcache, - cpu$imem_master_awid, - cpu$imem_master_awqos, - cpu$imem_master_awregion, - cpu$imem_master_bid, - cpu$imem_master_rid, - cpu$imem_master_wid, - cpu$set_verbosity_verbosity; - wire [2 : 0] cpu$dmem_master_arprot, - cpu$dmem_master_arsize, - cpu$dmem_master_awprot, - cpu$dmem_master_awsize, - cpu$imem_master_arprot, - cpu$imem_master_arsize, - cpu$imem_master_awprot, - cpu$imem_master_awsize; - wire [1 : 0] cpu$dmem_master_arburst, - cpu$dmem_master_awburst, - cpu$dmem_master_bresp, - cpu$dmem_master_rresp, - cpu$imem_master_arburst, - cpu$imem_master_awburst, - cpu$imem_master_bresp, - cpu$imem_master_rresp; - wire cpu$EN_hart0_server_reset_request_put, - cpu$EN_hart0_server_reset_response_get, - cpu$EN_set_verbosity, - cpu$RDY_hart0_server_reset_request_put, - cpu$RDY_hart0_server_reset_response_get, - cpu$dmem_master_arlock, - cpu$dmem_master_arready, - cpu$dmem_master_arvalid, - cpu$dmem_master_awlock, - cpu$dmem_master_awready, - cpu$dmem_master_awvalid, - cpu$dmem_master_bready, - cpu$dmem_master_bvalid, - cpu$dmem_master_rlast, - cpu$dmem_master_rready, - cpu$dmem_master_rvalid, - cpu$dmem_master_wlast, - cpu$dmem_master_wready, - cpu$dmem_master_wvalid, - cpu$hart0_server_reset_request_put, - cpu$hart0_server_reset_response_get, - cpu$imem_master_arlock, - cpu$imem_master_arready, - cpu$imem_master_arvalid, - cpu$imem_master_awlock, - cpu$imem_master_awready, - cpu$imem_master_awvalid, - cpu$imem_master_bready, - cpu$imem_master_bvalid, - cpu$imem_master_rlast, - cpu$imem_master_rready, - cpu$imem_master_rvalid, - cpu$imem_master_wlast, - cpu$imem_master_wready, - cpu$imem_master_wvalid, - cpu$m_external_interrupt_req_set_not_clear, - cpu$nmi_req_set_not_clear, - cpu$s_external_interrupt_req_set_not_clear, - cpu$software_interrupt_req_set_not_clear, - cpu$timer_interrupt_req_set_not_clear; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_araddr, - fabric_2x3$v_to_slaves_2_awaddr, - fabric_2x3$v_to_slaves_2_rdata, - fabric_2x3$v_to_slaves_2_wdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb, - fabric_2x3$v_to_slaves_2_arlen, - fabric_2x3$v_to_slaves_2_awlen, - fabric_2x3$v_to_slaves_2_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_wid, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, - fabric_2x3$v_to_slaves_2_arcache, - fabric_2x3$v_to_slaves_2_arid, - fabric_2x3$v_to_slaves_2_arqos, - fabric_2x3$v_to_slaves_2_arregion, - fabric_2x3$v_to_slaves_2_awcache, - fabric_2x3$v_to_slaves_2_awid, - fabric_2x3$v_to_slaves_2_awqos, - fabric_2x3$v_to_slaves_2_awregion, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize, - fabric_2x3$v_to_slaves_2_arprot, - fabric_2x3$v_to_slaves_2_arsize, - fabric_2x3$v_to_slaves_2_awprot, - fabric_2x3$v_to_slaves_2_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_arburst, - fabric_2x3$v_to_slaves_2_awburst, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arlock, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_arvalid, - fabric_2x3$v_to_slaves_2_awlock, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_awvalid, - fabric_2x3$v_to_slaves_2_bready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rready, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wlast, - fabric_2x3$v_to_slaves_2_wready, - fabric_2x3$v_to_slaves_2_wvalid; - - // ports of submodule near_mem_io - wire [63 : 0] near_mem_io$axi4_slave_araddr, - near_mem_io$axi4_slave_awaddr, - near_mem_io$axi4_slave_rdata, - near_mem_io$axi4_slave_wdata, - near_mem_io$set_addr_map_addr_base, - near_mem_io$set_addr_map_addr_lim; - wire [7 : 0] near_mem_io$axi4_slave_arlen, - near_mem_io$axi4_slave_awlen, - near_mem_io$axi4_slave_wstrb; - wire [3 : 0] near_mem_io$axi4_slave_arcache, - near_mem_io$axi4_slave_arid, - near_mem_io$axi4_slave_arqos, - near_mem_io$axi4_slave_arregion, - near_mem_io$axi4_slave_awcache, - near_mem_io$axi4_slave_awid, - near_mem_io$axi4_slave_awqos, - near_mem_io$axi4_slave_awregion, - near_mem_io$axi4_slave_bid, - near_mem_io$axi4_slave_rid, - near_mem_io$axi4_slave_wid; - wire [2 : 0] near_mem_io$axi4_slave_arprot, - near_mem_io$axi4_slave_arsize, - near_mem_io$axi4_slave_awprot, - near_mem_io$axi4_slave_awsize; - wire [1 : 0] near_mem_io$axi4_slave_arburst, - near_mem_io$axi4_slave_awburst, - near_mem_io$axi4_slave_bresp, - near_mem_io$axi4_slave_rresp; - wire near_mem_io$EN_get_sw_interrupt_req_get, - near_mem_io$EN_get_timer_interrupt_req_get, - near_mem_io$EN_server_reset_request_put, - near_mem_io$EN_server_reset_response_get, - near_mem_io$EN_set_addr_map, - near_mem_io$RDY_get_sw_interrupt_req_get, - near_mem_io$RDY_get_timer_interrupt_req_get, - near_mem_io$RDY_server_reset_request_put, - near_mem_io$RDY_server_reset_response_get, - near_mem_io$axi4_slave_arlock, - near_mem_io$axi4_slave_arready, - near_mem_io$axi4_slave_arvalid, - near_mem_io$axi4_slave_awlock, - near_mem_io$axi4_slave_awready, - near_mem_io$axi4_slave_awvalid, - near_mem_io$axi4_slave_bready, - near_mem_io$axi4_slave_bvalid, - near_mem_io$axi4_slave_rlast, - near_mem_io$axi4_slave_rready, - near_mem_io$axi4_slave_rvalid, - near_mem_io$axi4_slave_wlast, - near_mem_io$axi4_slave_wready, - near_mem_io$axi4_slave_wvalid, - near_mem_io$get_sw_interrupt_req_get, - near_mem_io$get_timer_interrupt_req_get; - - // ports of submodule plic - wire [63 : 0] plic$axi4_slave_araddr, - plic$axi4_slave_awaddr, - plic$axi4_slave_rdata, - plic$axi4_slave_wdata, - plic$set_addr_map_addr_base, - plic$set_addr_map_addr_lim; - wire [7 : 0] plic$axi4_slave_arlen, - plic$axi4_slave_awlen, - plic$axi4_slave_wstrb; - wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, - plic$axi4_slave_arqos, - plic$axi4_slave_arregion, - plic$axi4_slave_awcache, - plic$axi4_slave_awid, - plic$axi4_slave_awqos, - plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, - plic$axi4_slave_wid, - plic$set_verbosity_verbosity; - wire [2 : 0] plic$axi4_slave_arprot, - plic$axi4_slave_arsize, - plic$axi4_slave_awprot, - plic$axi4_slave_awsize; - wire [1 : 0] plic$axi4_slave_arburst, - plic$axi4_slave_awburst, - plic$axi4_slave_bresp, - plic$axi4_slave_rresp; - wire plic$EN_server_reset_request_put, - plic$EN_server_reset_response_get, - plic$EN_set_addr_map, - plic$EN_set_verbosity, - plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, - plic$axi4_slave_arlock, - plic$axi4_slave_arready, - plic$axi4_slave_arvalid, - plic$axi4_slave_awlock, - plic$axi4_slave_awready, - plic$axi4_slave_awvalid, - plic$axi4_slave_bready, - plic$axi4_slave_bvalid, - plic$axi4_slave_rlast, - plic$axi4_slave_rready, - plic$axi4_slave_rvalid, - plic$axi4_slave_wlast, - plic$axi4_slave_wready, - plic$axi4_slave_wvalid, - plic$v_sources_0_m_interrupt_req_set_not_clear, - plic$v_sources_10_m_interrupt_req_set_not_clear, - plic$v_sources_11_m_interrupt_req_set_not_clear, - plic$v_sources_12_m_interrupt_req_set_not_clear, - plic$v_sources_13_m_interrupt_req_set_not_clear, - plic$v_sources_14_m_interrupt_req_set_not_clear, - plic$v_sources_15_m_interrupt_req_set_not_clear, - plic$v_sources_1_m_interrupt_req_set_not_clear, - plic$v_sources_2_m_interrupt_req_set_not_clear, - plic$v_sources_3_m_interrupt_req_set_not_clear, - plic$v_sources_4_m_interrupt_req_set_not_clear, - plic$v_sources_5_m_interrupt_req_set_not_clear, - plic$v_sources_6_m_interrupt_req_set_not_clear, - plic$v_sources_7_m_interrupt_req_set_not_clear, - plic$v_sources_8_m_interrupt_req_set_not_clear, - plic$v_sources_9_m_interrupt_req_set_not_clear, - plic$v_targets_0_m_eip, - plic$v_targets_1_m_eip; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_sw_interrupts, - CAN_FIRE_RL_rl_relay_timer_interrupts, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_nmi_req, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_sw_interrupts, - WILL_FIRE_RL_rl_relay_timer_interrupts, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_nmi_req, - WILL_FIRE_set_verbosity; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4310; - reg [31 : 0] v__h4551; - reg [31 : 0] v__h4304; - reg [31 : 0] v__h4545; - // synopsys translate_on - - // remaining internal signals - wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // actionvalue method cpu_reset_server_response_get - assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ; - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; - - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - - // value method cpu_imem_master_m_awid - assign cpu_imem_master_awid = cpu$imem_master_awid ; - - // value method cpu_imem_master_m_awaddr - assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; - - // value method cpu_imem_master_m_awlen - assign cpu_imem_master_awlen = cpu$imem_master_awlen ; - - // value method cpu_imem_master_m_awsize - assign cpu_imem_master_awsize = cpu$imem_master_awsize ; - - // value method cpu_imem_master_m_awburst - assign cpu_imem_master_awburst = cpu$imem_master_awburst ; - - // value method cpu_imem_master_m_awlock - assign cpu_imem_master_awlock = cpu$imem_master_awlock ; - - // value method cpu_imem_master_m_awcache - assign cpu_imem_master_awcache = cpu$imem_master_awcache ; - - // value method cpu_imem_master_m_awprot - assign cpu_imem_master_awprot = cpu$imem_master_awprot ; - - // value method cpu_imem_master_m_awqos - assign cpu_imem_master_awqos = cpu$imem_master_awqos ; - - // value method cpu_imem_master_m_awregion - assign cpu_imem_master_awregion = cpu$imem_master_awregion ; - - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; - - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; - - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = cpu$imem_master_wid ; - - // value method cpu_imem_master_m_wdata - assign cpu_imem_master_wdata = cpu$imem_master_wdata ; - - // value method cpu_imem_master_m_wstrb - assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; - - // value method cpu_imem_master_m_wlast - assign cpu_imem_master_wlast = cpu$imem_master_wlast ; - - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; - - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = cpu$imem_master_bready ; - - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; - - // value method cpu_imem_master_m_arid - assign cpu_imem_master_arid = cpu$imem_master_arid ; - - // value method cpu_imem_master_m_araddr - assign cpu_imem_master_araddr = cpu$imem_master_araddr ; - - // value method cpu_imem_master_m_arlen - assign cpu_imem_master_arlen = cpu$imem_master_arlen ; - - // value method cpu_imem_master_m_arsize - assign cpu_imem_master_arsize = cpu$imem_master_arsize ; - - // value method cpu_imem_master_m_arburst - assign cpu_imem_master_arburst = cpu$imem_master_arburst ; - - // value method cpu_imem_master_m_arlock - assign cpu_imem_master_arlock = cpu$imem_master_arlock ; - - // value method cpu_imem_master_m_arcache - assign cpu_imem_master_arcache = cpu$imem_master_arcache ; - - // value method cpu_imem_master_m_arprot - assign cpu_imem_master_arprot = cpu$imem_master_arprot ; - - // value method cpu_imem_master_m_arqos - assign cpu_imem_master_arqos = cpu$imem_master_arqos ; - - // value method cpu_imem_master_m_arregion - assign cpu_imem_master_arregion = cpu$imem_master_arregion ; - - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; - - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - - // value method cpu_imem_master_m_rready - assign cpu_imem_master_rready = cpu$imem_master_rready ; - - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; - - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; - - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; - - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; - - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; - - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; - - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; - - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; - - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; - - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; - - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; - - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; - - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; - - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; - - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; - - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; - - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; - - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; - - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; - - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; - - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; - - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; - - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; - - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; - - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; - - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; - - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; - - // action method core_external_interrupt_sources_0_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_1_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_2_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_3_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_4_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_5_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_6_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_7_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_8_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_9_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_10_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_11_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_12_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_13_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_14_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_15_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // submodule cpu - mkCPU cpu(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(cpu$dmem_master_arready), - .dmem_master_awready(cpu$dmem_master_awready), - .dmem_master_bid(cpu$dmem_master_bid), - .dmem_master_bresp(cpu$dmem_master_bresp), - .dmem_master_bvalid(cpu$dmem_master_bvalid), - .dmem_master_rdata(cpu$dmem_master_rdata), - .dmem_master_rid(cpu$dmem_master_rid), - .dmem_master_rlast(cpu$dmem_master_rlast), - .dmem_master_rresp(cpu$dmem_master_rresp), - .dmem_master_rvalid(cpu$dmem_master_rvalid), - .dmem_master_wready(cpu$dmem_master_wready), - .hart0_server_reset_request_put(cpu$hart0_server_reset_request_put), - .imem_master_arready(cpu$imem_master_arready), - .imem_master_awready(cpu$imem_master_awready), - .imem_master_bid(cpu$imem_master_bid), - .imem_master_bresp(cpu$imem_master_bresp), - .imem_master_bvalid(cpu$imem_master_bvalid), - .imem_master_rdata(cpu$imem_master_rdata), - .imem_master_rid(cpu$imem_master_rid), - .imem_master_rlast(cpu$imem_master_rlast), - .imem_master_rresp(cpu$imem_master_rresp), - .imem_master_rvalid(cpu$imem_master_rvalid), - .imem_master_wready(cpu$imem_master_wready), - .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), - .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), - .s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear), - .set_verbosity_logdelay(cpu$set_verbosity_logdelay), - .set_verbosity_verbosity(cpu$set_verbosity_verbosity), - .software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), - .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), - .EN_set_verbosity(cpu$EN_set_verbosity), - .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), - .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), - .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), - .imem_master_awvalid(cpu$imem_master_awvalid), - .imem_master_awid(cpu$imem_master_awid), - .imem_master_awaddr(cpu$imem_master_awaddr), - .imem_master_awlen(cpu$imem_master_awlen), - .imem_master_awsize(cpu$imem_master_awsize), - .imem_master_awburst(cpu$imem_master_awburst), - .imem_master_awlock(cpu$imem_master_awlock), - .imem_master_awcache(cpu$imem_master_awcache), - .imem_master_awprot(cpu$imem_master_awprot), - .imem_master_awqos(cpu$imem_master_awqos), - .imem_master_awregion(cpu$imem_master_awregion), - .imem_master_wvalid(cpu$imem_master_wvalid), - .imem_master_wid(cpu$imem_master_wid), - .imem_master_wdata(cpu$imem_master_wdata), - .imem_master_wstrb(cpu$imem_master_wstrb), - .imem_master_wlast(cpu$imem_master_wlast), - .imem_master_bready(cpu$imem_master_bready), - .imem_master_arvalid(cpu$imem_master_arvalid), - .imem_master_arid(cpu$imem_master_arid), - .imem_master_araddr(cpu$imem_master_araddr), - .imem_master_arlen(cpu$imem_master_arlen), - .imem_master_arsize(cpu$imem_master_arsize), - .imem_master_arburst(cpu$imem_master_arburst), - .imem_master_arlock(cpu$imem_master_arlock), - .imem_master_arcache(cpu$imem_master_arcache), - .imem_master_arprot(cpu$imem_master_arprot), - .imem_master_arqos(cpu$imem_master_arqos), - .imem_master_arregion(cpu$imem_master_arregion), - .imem_master_rready(cpu$imem_master_rready), - .dmem_master_awvalid(cpu$dmem_master_awvalid), - .dmem_master_awid(cpu$dmem_master_awid), - .dmem_master_awaddr(cpu$dmem_master_awaddr), - .dmem_master_awlen(cpu$dmem_master_awlen), - .dmem_master_awsize(cpu$dmem_master_awsize), - .dmem_master_awburst(cpu$dmem_master_awburst), - .dmem_master_awlock(cpu$dmem_master_awlock), - .dmem_master_awcache(cpu$dmem_master_awcache), - .dmem_master_awprot(cpu$dmem_master_awprot), - .dmem_master_awqos(cpu$dmem_master_awqos), - .dmem_master_awregion(cpu$dmem_master_awregion), - .dmem_master_wvalid(cpu$dmem_master_wvalid), - .dmem_master_wid(cpu$dmem_master_wid), - .dmem_master_wdata(cpu$dmem_master_wdata), - .dmem_master_wstrb(cpu$dmem_master_wstrb), - .dmem_master_wlast(cpu$dmem_master_wlast), - .dmem_master_bready(cpu$dmem_master_bready), - .dmem_master_arvalid(cpu$dmem_master_arvalid), - .dmem_master_arid(cpu$dmem_master_arid), - .dmem_master_araddr(cpu$dmem_master_araddr), - .dmem_master_arlen(cpu$dmem_master_arlen), - .dmem_master_arsize(cpu$dmem_master_arsize), - .dmem_master_arburst(cpu$dmem_master_arburst), - .dmem_master_arlock(cpu$dmem_master_arlock), - .dmem_master_arcache(cpu$dmem_master_arcache), - .dmem_master_arprot(cpu$dmem_master_arprot), - .dmem_master_arqos(cpu$dmem_master_arqos), - .dmem_master_arregion(cpu$dmem_master_arregion), - .dmem_master_rready(cpu$dmem_master_rready), - .RDY_set_verbosity()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(), - .v_from_masters_1_wready(), - .v_from_masters_1_bvalid(), - .v_from_masters_1_bid(), - .v_from_masters_1_bresp(), - .v_from_masters_1_arready(), - .v_from_masters_1_rvalid(), - .v_from_masters_1_rid(), - .v_from_masters_1_rdata(), - .v_from_masters_1_rresp(), - .v_from_masters_1_rlast(), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); - - // submodule near_mem_io - mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(near_mem_io$axi4_slave_araddr), - .axi4_slave_arburst(near_mem_io$axi4_slave_arburst), - .axi4_slave_arcache(near_mem_io$axi4_slave_arcache), - .axi4_slave_arid(near_mem_io$axi4_slave_arid), - .axi4_slave_arlen(near_mem_io$axi4_slave_arlen), - .axi4_slave_arlock(near_mem_io$axi4_slave_arlock), - .axi4_slave_arprot(near_mem_io$axi4_slave_arprot), - .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), - .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), - .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), - .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), - .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), - .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), - .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), - .axi4_slave_awid(near_mem_io$axi4_slave_awid), - .axi4_slave_awlen(near_mem_io$axi4_slave_awlen), - .axi4_slave_awlock(near_mem_io$axi4_slave_awlock), - .axi4_slave_awprot(near_mem_io$axi4_slave_awprot), - .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), - .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), - .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), - .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), - .axi4_slave_bready(near_mem_io$axi4_slave_bready), - .axi4_slave_rready(near_mem_io$axi4_slave_rready), - .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), - .axi4_slave_wid(near_mem_io$axi4_slave_wid), - .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), - .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), - .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), - .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), - .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), - .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), - .EN_set_addr_map(near_mem_io$EN_set_addr_map), - .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), - .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), - .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(near_mem_io$axi4_slave_awready), - .axi4_slave_wready(near_mem_io$axi4_slave_wready), - .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), - .axi4_slave_bid(near_mem_io$axi4_slave_bid), - .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), - .axi4_slave_arready(near_mem_io$axi4_slave_arready), - .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), - .axi4_slave_rid(near_mem_io$axi4_slave_rid), - .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), - .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), - .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), - .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), - .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), - .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), - .RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get)); - - // submodule plic - mkPLIC_16_2_7 plic(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(plic$axi4_slave_araddr), - .axi4_slave_arburst(plic$axi4_slave_arburst), - .axi4_slave_arcache(plic$axi4_slave_arcache), - .axi4_slave_arid(plic$axi4_slave_arid), - .axi4_slave_arlen(plic$axi4_slave_arlen), - .axi4_slave_arlock(plic$axi4_slave_arlock), - .axi4_slave_arprot(plic$axi4_slave_arprot), - .axi4_slave_arqos(plic$axi4_slave_arqos), - .axi4_slave_arregion(plic$axi4_slave_arregion), - .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), - .axi4_slave_awaddr(plic$axi4_slave_awaddr), - .axi4_slave_awburst(plic$axi4_slave_awburst), - .axi4_slave_awcache(plic$axi4_slave_awcache), - .axi4_slave_awid(plic$axi4_slave_awid), - .axi4_slave_awlen(plic$axi4_slave_awlen), - .axi4_slave_awlock(plic$axi4_slave_awlock), - .axi4_slave_awprot(plic$axi4_slave_awprot), - .axi4_slave_awqos(plic$axi4_slave_awqos), - .axi4_slave_awregion(plic$axi4_slave_awregion), - .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_bready(plic$axi4_slave_bready), - .axi4_slave_rready(plic$axi4_slave_rready), - .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), - .axi4_slave_wlast(plic$axi4_slave_wlast), - .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .set_addr_map_addr_base(plic$set_addr_map_addr_base), - .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), - .set_verbosity_verbosity(plic$set_verbosity_verbosity), - .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), - .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), - .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), - .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), - .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), - .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), - .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), - .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), - .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), - .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), - .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), - .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), - .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), - .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), - .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), - .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), - .EN_set_verbosity(plic$EN_set_verbosity), - .EN_show_PLIC_state(plic$EN_show_PLIC_state), - .EN_server_reset_request_put(plic$EN_server_reset_request_put), - .EN_server_reset_response_get(plic$EN_server_reset_response_get), - .EN_set_addr_map(plic$EN_set_addr_map), - .RDY_set_verbosity(), - .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(plic$axi4_slave_awready), - .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), - .axi4_slave_bid(plic$axi4_slave_bid), - .axi4_slave_bresp(plic$axi4_slave_bresp), - .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), - .axi4_slave_rid(plic$axi4_slave_rid), - .axi4_slave_rdata(plic$axi4_slave_rdata), - .axi4_slave_rresp(plic$axi4_slave_rresp), - .axi4_slave_rlast(plic$axi4_slave_rlast), - .v_targets_0_m_eip(plic$v_targets_0_m_eip), - .v_targets_1_m_eip(plic$v_targets_1_m_eip)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_relay_sw_interrupts - assign CAN_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // rule RL_rl_relay_timer_interrupts - assign CAN_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - - // rule RL_rl_relay_external_interrupts - assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule cpu - assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; - assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; - assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; - assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; - assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; - assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ; - assign cpu$imem_master_arready = cpu_imem_master_arready ; - assign cpu$imem_master_awready = cpu_imem_master_awready ; - assign cpu$imem_master_bid = cpu_imem_master_bid ; - assign cpu$imem_master_bresp = cpu_imem_master_bresp ; - assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; - assign cpu$imem_master_rdata = cpu_imem_master_rdata ; - assign cpu$imem_master_rid = cpu_imem_master_rid ; - assign cpu$imem_master_rlast = cpu_imem_master_rlast ; - assign cpu$imem_master_rresp = cpu_imem_master_rresp ; - assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; - assign cpu$imem_master_wready = cpu_imem_master_wready ; - assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; - assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; - assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; - assign cpu$software_interrupt_req_set_not_clear = - near_mem_io$get_sw_interrupt_req_get ; - assign cpu$timer_interrupt_req_set_not_clear = - near_mem_io$get_timer_interrupt_req_get ; - assign cpu$EN_hart0_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign cpu$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign cpu$EN_set_verbosity = EN_set_verbosity ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = cpu_reset_server_request_put ; - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ; - assign f_reset_rsps$ENQ = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; - assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; - assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; - assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; - assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; - assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; - assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; - assign fabric_2x3$v_from_masters_0_wid = cpu$dmem_master_wid ; - assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_awaddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_bready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_wdata = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wstrb = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; - assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; - - // submodule near_mem_io - assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign near_mem_io$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; - assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; - assign near_mem_io$set_addr_map_addr_base = - soc_map$m_near_mem_io_addr_base ; - assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; - assign near_mem_io$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign near_mem_io$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_set_addr_map = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_get_timer_interrupt_req_get = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign near_mem_io$EN_get_sw_interrupt_req_get = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_2_wid ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; - assign plic$set_verbosity_verbosity = 4'h0 ; - assign plic$v_sources_0_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; - assign plic$v_sources_10_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; - assign plic$v_sources_11_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; - assign plic$v_sources_12_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; - assign plic$v_sources_13_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; - assign plic$v_sources_14_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; - assign plic$v_sources_15_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; - assign plic$v_sources_1_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; - assign plic$v_sources_2_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; - assign plic$v_sources_3_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; - assign plic$v_sources_4_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; - assign plic$v_sources_5_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; - assign plic$v_sources_6_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; - assign plic$v_sources_7_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; - assign plic$v_sources_8_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; - assign plic$v_sources_9_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; - assign plic$EN_set_verbosity = 1'b0 ; - assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - cpu$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h4310 = $stime; - #0; - end - v__h4304 = v__h4310 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4304); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h4551 = $stime; - #0; - end - v__h4545 = v__h4551 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4545); - end - // synopsys translate_on -endmodule // mkCore - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric.v deleted file mode 100644 index 771fc0dc..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric.v +++ /dev/null @@ -1,8149 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 = - fabric_cfg_verbosity > 4'd1 ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - $display("%0d: %m::AXI4_Fabric.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v deleted file mode 100644 index 2e372865..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v +++ /dev/null @@ -1,7465 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_2x3(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8650; - reg [31 : 0] v__h9025; - reg [31 : 0] v__h9400; - reg [31 : 0] v__h9845; - reg [31 : 0] v__h10214; - reg [31 : 0] v__h10583; - reg [31 : 0] v__h11872; - reg [31 : 0] v__h12325; - reg [31 : 0] v__h12702; - reg [31 : 0] v__h12994; - reg [31 : 0] v__h13286; - reg [31 : 0] v__h13589; - reg [31 : 0] v__h13855; - reg [31 : 0] v__h14121; - reg [31 : 0] v__h14385; - reg [31 : 0] v__h14611; - reg [31 : 0] v__h15040; - reg [31 : 0] v__h15396; - reg [31 : 0] v__h15752; - reg [31 : 0] v__h16169; - reg [31 : 0] v__h16501; - reg [31 : 0] v__h16833; - reg [31 : 0] v__h17849; - reg [31 : 0] v__h18100; - reg [31 : 0] v__h18475; - reg [31 : 0] v__h18716; - reg [31 : 0] v__h19091; - reg [31 : 0] v__h19332; - reg [31 : 0] v__h19694; - reg [31 : 0] v__h19945; - reg [31 : 0] v__h20275; - reg [31 : 0] v__h20516; - reg [31 : 0] v__h20846; - reg [31 : 0] v__h21087; - reg [31 : 0] v__h21600; - reg [31 : 0] v__h22001; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8644; - reg [31 : 0] v__h9019; - reg [31 : 0] v__h9394; - reg [31 : 0] v__h9839; - reg [31 : 0] v__h10208; - reg [31 : 0] v__h10577; - reg [31 : 0] v__h11866; - reg [31 : 0] v__h12319; - reg [31 : 0] v__h12696; - reg [31 : 0] v__h12988; - reg [31 : 0] v__h13280; - reg [31 : 0] v__h13583; - reg [31 : 0] v__h13849; - reg [31 : 0] v__h14115; - reg [31 : 0] v__h14379; - reg [31 : 0] v__h14605; - reg [31 : 0] v__h15034; - reg [31 : 0] v__h15390; - reg [31 : 0] v__h15746; - reg [31 : 0] v__h16163; - reg [31 : 0] v__h16495; - reg [31 : 0] v__h16827; - reg [31 : 0] v__h17843; - reg [31 : 0] v__h18094; - reg [31 : 0] v__h18469; - reg [31 : 0] v__h18710; - reg [31 : 0] v__h19085; - reg [31 : 0] v__h19326; - reg [31 : 0] v__h19688; - reg [31 : 0] v__h19939; - reg [31 : 0] v__h20269; - reg [31 : 0] v__h20510; - reg [31 : 0] v__h20840; - reg [31 : 0] v__h21081; - reg [31 : 0] v__h21594; - reg [31 : 0] v__h21995; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11777, - x__h12230, - x__h17986, - x__h18612, - x__h19228, - x__h21532, - x__h21933; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - x1_avValue_rresp__h17964, - x1_avValue_rresp__h18590, - x1_avValue_rresp__h19206; - wire _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156, - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371, - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411, - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540, - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - 8'd0 : - x__h17986 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - 8'd0 : - x__h18612 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - 8'd0 : - x__h19228 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? - 8'd0 : - x__h11777 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ? - 8'd0 : - x__h12230 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ? - 8'd0 : - x__h21532 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ? - 8'd0 : - x__h21933 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - x1_avValue_rresp__h17964 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - x1_avValue_rresp__h18590 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - x1_avValue_rresp__h19206 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h17964 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18590 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19206 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11777 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12230 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h17986 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h18612 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19228 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21532 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h21933 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8650 = $stime; - #0; - end - v__h8644 = v__h8650 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8644, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9025 = $stime; - #0; - end - v__h9019 = v__h9025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9019, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9400 = $stime; - #0; - end - v__h9394 = v__h9400 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9394, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9845 = $stime; - #0; - end - v__h9839 = v__h9845 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9839, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10214 = $stime; - #0; - end - v__h10208 = v__h10214 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10208, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10583 = $stime; - #0; - end - v__h10577 = v__h10583 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10577, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h11872 = $stime; - #0; - end - v__h11866 = v__h11872 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h11866, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12325 = $stime; - #0; - end - v__h12319 = v__h12325 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12319, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12702 = $stime; - #0; - end - v__h12696 = v__h12702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12696, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h12994 = $stime; - #0; - end - v__h12988 = v__h12994 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12988, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13286 = $stime; - #0; - end - v__h13280 = v__h13286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13280, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13589 = $stime; - #0; - end - v__h13583 = v__h13589 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13583, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13855 = $stime; - #0; - end - v__h13849 = v__h13855 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13849, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14121 = $stime; - #0; - end - v__h14115 = v__h14121 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14115, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14385 = $stime; - #0; - end - v__h14379 = v__h14385 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14379, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14611 = $stime; - #0; - end - v__h14605 = v__h14611 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14605, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15040 = $stime; - #0; - end - v__h15034 = v__h15040 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15034, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15396 = $stime; - #0; - end - v__h15390 = v__h15396 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15390, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15752 = $stime; - #0; - end - v__h15746 = v__h15752 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15746, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16169 = $stime; - #0; - end - v__h16163 = v__h16169 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16163, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16501 = $stime; - #0; - end - v__h16495 = v__h16501 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16495, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16833 = $stime; - #0; - end - v__h16827 = v__h16833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16827, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h17849 = $stime; - #0; - end - v__h17843 = v__h17849 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h17843, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18100 = $stime; - #0; - end - v__h18094 = v__h18100 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18094, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18475 = $stime; - #0; - end - v__h18469 = v__h18475 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18469, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h18716 = $stime; - #0; - end - v__h18710 = v__h18716 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18710, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19091 = $stime; - #0; - end - v__h19085 = v__h19091 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19085, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19332 = $stime; - #0; - end - v__h19326 = v__h19332 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19326, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h19694 = $stime; - #0; - end - v__h19688 = v__h19694 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19688, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19945 = $stime; - #0; - end - v__h19939 = v__h19945 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19939, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20275 = $stime; - #0; - end - v__h20269 = v__h20275 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20269, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20516 = $stime; - #0; - end - v__h20510 = v__h20516 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20510, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h20846 = $stime; - #0; - end - v__h20840 = v__h20846 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20840, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21087 = $stime; - #0; - end - v__h21081 = v__h21087 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21081, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21600 = $stime; - #0; - end - v__h21594 = v__h21600 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21594, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22001 = $stime; - #0; - end - v__h21995 = v__h22001 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21995, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_2x3 - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v deleted file mode 100644 index ac19188b..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v +++ /dev/null @@ -1,8145 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_AXI4(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_AXI4 - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v deleted file mode 100644 index a238e586..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v +++ /dev/null @@ -1,249 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 32 -// read_rs1_port2 O 32 -// read_rs2 O 32 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 32 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// Combinational paths from inputs to outputs: -// read_rs1_rs1 -> read_rs1 -// read_rs1_port2_rs1 -> read_rs1_port2 -// read_rs2_rs2 -> read_rs2 -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkGPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [31 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [31 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [31 : 0] read_rs2; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [31 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [31 : 0] read_rs1, read_rs1_port2, read_rs2; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [31 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 32'd0 : regfile$D_OUT_3 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = - (read_rs1_port2_rs1 == 5'd0) ? 32'd0 : regfile$D_OUT_2 ; - - // value method read_rs2 - assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 32'd0 : regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd32), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs2_rs2 ; - assign regfile$ADDR_2 = read_rs1_port2_rs1 ; - assign regfile$ADDR_3 = read_rs1_rs1 ; - assign regfile$ADDR_4 = 5'h0 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkGPR_RegFile - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v deleted file mode 100644 index f4d13fdd..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 64 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 32 -// put_args_y_is_signed I 1 -// put_args_y I 32 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_32(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [31 : 0] put_args_x; - input put_args_y_is_signed; - input [31 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [63 : 0] result_value; - - // signals for module outputs - wire [63 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [63 : 0] m_rg_x; - wire [63 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [63 : 0] m_rg_xy; - wire [63 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [31 : 0] m_rg_y; - wire [31 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [63 : 0] xy___1__h654; - wire [31 : 0] _theResult___fst__h491, - _theResult___fst__h494, - _theResult___fst__h536, - _theResult___fst__h539, - _theResult___snd_fst__h531; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 32'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h654 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 32'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h491 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h539 : - _theResult___snd_fst__h531 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[31] != put_args_y[31] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 = - put_args_x_is_signed ? - put_args_x[31] : - put_args_y_is_signed && put_args_y[31] ; - assign _theResult___fst__h491 = - put_args_x_is_signed ? _theResult___fst__h494 : put_args_x ; - assign _theResult___fst__h494 = put_args_x[31] ? -put_args_x : put_args_x ; - assign _theResult___fst__h536 = - put_args_y_is_signed ? _theResult___fst__h539 : put_args_y ; - assign _theResult___fst__h539 = put_args_y[31] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h531 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h536 ; - assign xy___1__h654 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 64'hAAAAAAAAAAAAAAAA; - m_rg_xy = 64'hAAAAAAAAAAAAAAAA; - m_rg_y = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_32 - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v deleted file mode 100644 index 0b513191..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 128 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 64 -// put_args_y_is_signed I 1 -// put_args_y I 64 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_64(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [63 : 0] put_args_x; - input put_args_y_is_signed; - input [63 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [127 : 0] result_value; - - // signals for module outputs - wire [127 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [127 : 0] m_rg_x; - wire [127 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [127 : 0] m_rg_xy; - wire [127 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [63 : 0] m_rg_y; - wire [63 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [127 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [127 : 0] xy___1__h648; - wire [63 : 0] _theResult___fst__h488, - _theResult___fst__h491, - _theResult___fst__h533, - _theResult___fst__h536, - _theResult___snd_fst__h528; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 64'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h648 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 64'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h488 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h536 : - _theResult___snd_fst__h528 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[63] != put_args_y[63] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 = - put_args_x_is_signed ? - put_args_x[63] : - put_args_y_is_signed && put_args_y[63] ; - assign _theResult___fst__h488 = - put_args_x_is_signed ? _theResult___fst__h491 : put_args_x ; - assign _theResult___fst__h491 = put_args_x[63] ? -put_args_x : put_args_x ; - assign _theResult___fst__h533 = - put_args_y_is_signed ? _theResult___fst__h536 : put_args_y ; - assign _theResult___fst__h536 = put_args_y[63] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h528 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h533 ; - assign xy___1__h648 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_y = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_64 - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v deleted file mode 100644 index a92e69ce..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v +++ /dev/null @@ -1,6072 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// valid O 1 -// addr O 32 reg -// word64 O 64 -// st_amo_val O 64 -// exc O 1 -// exc_code O 4 reg -// RDY_server_flush_request_put O 1 reg -// RDY_server_flush_response_get O 1 -// RDY_tlb_flush O 1 const -// mem_master_awvalid O 1 -// mem_master_awid O 4 reg -// mem_master_awaddr O 64 reg -// mem_master_awlen O 8 reg -// mem_master_awsize O 3 reg -// mem_master_awburst O 2 reg -// mem_master_awlock O 1 reg -// mem_master_awcache O 4 reg -// mem_master_awprot O 3 reg -// mem_master_awqos O 4 reg -// mem_master_awregion O 4 reg -// mem_master_wvalid O 1 -// mem_master_wid O 4 reg -// mem_master_wdata O 64 reg -// mem_master_wstrb O 8 reg -// mem_master_wlast O 1 reg -// mem_master_bready O 1 -// mem_master_arvalid O 1 -// mem_master_arid O 4 reg -// mem_master_araddr O 64 reg -// mem_master_arlen O 8 reg -// mem_master_arsize O 3 reg -// mem_master_arburst O 2 reg -// mem_master_arlock O 1 reg -// mem_master_arcache O 4 reg -// mem_master_arprot O 3 reg -// mem_master_arqos O 4 reg -// mem_master_arregion O 4 reg -// mem_master_rready O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_op I 2 -// req_f3 I 3 -// req_amo_funct7 I 7 reg -// req_addr I 32 -// req_st_value I 64 -// req_priv I 2 unused -// req_sstatus_SUM I 1 unused -// req_mstatus_MXR I 1 unused -// req_satp I 32 unused -// mem_master_awready I 1 -// mem_master_wready I 1 -// mem_master_bvalid I 1 -// mem_master_bid I 4 reg -// mem_master_bresp I 2 reg -// mem_master_arready I 1 -// mem_master_rvalid I 1 -// mem_master_rid I 4 reg -// mem_master_rdata I 64 reg -// mem_master_rresp I 2 reg -// mem_master_rlast I 1 reg -// EN_set_verbosity I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// EN_server_flush_request_put I 1 -// EN_server_flush_response_get I 1 -// EN_tlb_flush I 1 unused -// -// Combinational paths from inputs to outputs: -// (mem_master_awready, mem_master_wready) -> valid -// (mem_master_awready, mem_master_wready) -> word64 -// (mem_master_awready, mem_master_wready) -> st_amo_val -// (mem_master_awready, mem_master_wready) -> mem_master_bready -// (mem_master_awready, mem_master_wready, EN_req) -> mem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMMU_Cache(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_op, - req_f3, - req_amo_funct7, - req_addr, - req_st_value, - req_priv, - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - EN_req, - - valid, - - addr, - - word64, - - st_amo_val, - - exc, - - exc_code, - - EN_server_flush_request_put, - RDY_server_flush_request_put, - - EN_server_flush_response_get, - RDY_server_flush_response_get, - - EN_tlb_flush, - RDY_tlb_flush, - - mem_master_awvalid, - - mem_master_awid, - - mem_master_awaddr, - - mem_master_awlen, - - mem_master_awsize, - - mem_master_awburst, - - mem_master_awlock, - - mem_master_awcache, - - mem_master_awprot, - - mem_master_awqos, - - mem_master_awregion, - - mem_master_awready, - - mem_master_wvalid, - - mem_master_wid, - - mem_master_wdata, - - mem_master_wstrb, - - mem_master_wlast, - - mem_master_wready, - - mem_master_bvalid, - mem_master_bid, - mem_master_bresp, - - mem_master_bready, - - mem_master_arvalid, - - mem_master_arid, - - mem_master_araddr, - - mem_master_arlen, - - mem_master_arsize, - - mem_master_arburst, - - mem_master_arlock, - - mem_master_arcache, - - mem_master_arprot, - - mem_master_arqos, - - mem_master_arregion, - - mem_master_arready, - - mem_master_rvalid, - mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast, - - mem_master_rready); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [1 : 0] req_op; - input [2 : 0] req_f3; - input [6 : 0] req_amo_funct7; - input [31 : 0] req_addr; - input [63 : 0] req_st_value; - input [1 : 0] req_priv; - input req_sstatus_SUM; - input req_mstatus_MXR; - input [31 : 0] req_satp; - input EN_req; - - // value method valid - output valid; - - // value method addr - output [31 : 0] addr; - - // value method word64 - output [63 : 0] word64; - - // value method st_amo_val - output [63 : 0] st_amo_val; - - // value method exc - output exc; - - // value method exc_code - output [3 : 0] exc_code; - - // action method server_flush_request_put - input EN_server_flush_request_put; - output RDY_server_flush_request_put; - - // action method server_flush_response_get - input EN_server_flush_response_get; - output RDY_server_flush_response_get; - - // action method tlb_flush - input EN_tlb_flush; - output RDY_tlb_flush; - - // value method mem_master_m_awvalid - output mem_master_awvalid; - - // value method mem_master_m_awid - output [3 : 0] mem_master_awid; - - // value method mem_master_m_awaddr - output [63 : 0] mem_master_awaddr; - - // value method mem_master_m_awlen - output [7 : 0] mem_master_awlen; - - // value method mem_master_m_awsize - output [2 : 0] mem_master_awsize; - - // value method mem_master_m_awburst - output [1 : 0] mem_master_awburst; - - // value method mem_master_m_awlock - output mem_master_awlock; - - // value method mem_master_m_awcache - output [3 : 0] mem_master_awcache; - - // value method mem_master_m_awprot - output [2 : 0] mem_master_awprot; - - // value method mem_master_m_awqos - output [3 : 0] mem_master_awqos; - - // value method mem_master_m_awregion - output [3 : 0] mem_master_awregion; - - // value method mem_master_m_awuser - - // action method mem_master_m_awready - input mem_master_awready; - - // value method mem_master_m_wvalid - output mem_master_wvalid; - - // value method mem_master_m_wid - output [3 : 0] mem_master_wid; - - // value method mem_master_m_wdata - output [63 : 0] mem_master_wdata; - - // value method mem_master_m_wstrb - output [7 : 0] mem_master_wstrb; - - // value method mem_master_m_wlast - output mem_master_wlast; - - // value method mem_master_m_wuser - - // action method mem_master_m_wready - input mem_master_wready; - - // action method mem_master_m_bvalid - input mem_master_bvalid; - input [3 : 0] mem_master_bid; - input [1 : 0] mem_master_bresp; - - // value method mem_master_m_bready - output mem_master_bready; - - // value method mem_master_m_arvalid - output mem_master_arvalid; - - // value method mem_master_m_arid - output [3 : 0] mem_master_arid; - - // value method mem_master_m_araddr - output [63 : 0] mem_master_araddr; - - // value method mem_master_m_arlen - output [7 : 0] mem_master_arlen; - - // value method mem_master_m_arsize - output [2 : 0] mem_master_arsize; - - // value method mem_master_m_arburst - output [1 : 0] mem_master_arburst; - - // value method mem_master_m_arlock - output mem_master_arlock; - - // value method mem_master_m_arcache - output [3 : 0] mem_master_arcache; - - // value method mem_master_m_arprot - output [2 : 0] mem_master_arprot; - - // value method mem_master_m_arqos - output [3 : 0] mem_master_arqos; - - // value method mem_master_m_arregion - output [3 : 0] mem_master_arregion; - - // value method mem_master_m_aruser - - // action method mem_master_m_arready - input mem_master_arready; - - // action method mem_master_m_rvalid - input mem_master_rvalid; - input [3 : 0] mem_master_rid; - input [63 : 0] mem_master_rdata; - input [1 : 0] mem_master_rresp; - input mem_master_rlast; - - // value method mem_master_m_rready - output mem_master_rready; - - // signals for module outputs - reg [63 : 0] word64; - wire [63 : 0] mem_master_araddr, - mem_master_awaddr, - mem_master_wdata, - st_amo_val; - wire [31 : 0] addr; - wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; - wire [3 : 0] exc_code, - mem_master_arcache, - mem_master_arid, - mem_master_arqos, - mem_master_arregion, - mem_master_awcache, - mem_master_awid, - mem_master_awqos, - mem_master_awregion, - mem_master_wid; - wire [2 : 0] mem_master_arprot, - mem_master_arsize, - mem_master_awprot, - mem_master_awsize; - wire [1 : 0] mem_master_arburst, mem_master_awburst; - wire RDY_server_flush_request_put, - RDY_server_flush_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_verbosity, - RDY_tlb_flush, - exc, - mem_master_arlock, - mem_master_arvalid, - mem_master_awlock, - mem_master_awvalid, - mem_master_bready, - mem_master_rready, - mem_master_wlast, - mem_master_wvalid, - valid; - - // inlined wires - reg [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1; - wire [10 : 0] crg_sb_to_load_delay$port0__write_1, - crg_sb_to_load_delay$port2__read; - wire [3 : 0] ctr_wr_rsps_pending_crg$port1__write_1, - ctr_wr_rsps_pending_crg$port2__read, - ctr_wr_rsps_pending_crg$port3__read; - wire crg_sb_to_load_delay$EN_port1__write, - ctr_wr_rsps_pending_crg$EN_port0__write, - ctr_wr_rsps_pending_crg$EN_port2__write, - dw_valid$whas, - master_xactor_crg_rd_addr_full$EN_port0__write, - master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port1__read, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port0__write, - master_xactor_crg_rd_data_full$EN_port1__write, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port1__read, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port0__write, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$EN_port2__write, - master_xactor_crg_wr_addr_full$port1__read, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port0__write, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$EN_port2__write, - master_xactor_crg_wr_data_full$port1__read, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read, - master_xactor_crg_wr_resp_full$EN_port0__write, - master_xactor_crg_wr_resp_full$EN_port2__write, - master_xactor_crg_wr_resp_full$port1__read, - master_xactor_crg_wr_resp_full$port2__read, - master_xactor_crg_wr_resp_full$port3__read; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_sb_to_load_delay - reg [10 : 0] crg_sb_to_load_delay; - wire [10 : 0] crg_sb_to_load_delay$D_IN; - wire crg_sb_to_load_delay$EN; - - // register ctr_wr_rsps_pending_crg - reg [3 : 0] ctr_wr_rsps_pending_crg; - wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN; - wire ctr_wr_rsps_pending_crg$EN; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - wire [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - reg [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [76 : 0] master_xactor_rg_wr_data; - reg [76 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - - // register rg_addr - reg [31 : 0] rg_addr; - wire [31 : 0] rg_addr$D_IN; - wire rg_addr$EN; - - // register rg_amo_funct7 - reg [6 : 0] rg_amo_funct7; - wire [6 : 0] rg_amo_funct7$D_IN; - wire rg_amo_funct7$EN; - - // register rg_cset_in_cache - reg [6 : 0] rg_cset_in_cache; - wire [6 : 0] rg_cset_in_cache$D_IN; - wire rg_cset_in_cache$EN; - - // register rg_error_during_refill - reg rg_error_during_refill; - wire rg_error_during_refill$D_IN, rg_error_during_refill$EN; - - // register rg_exc_code - reg [3 : 0] rg_exc_code; - reg [3 : 0] rg_exc_code$D_IN; - wire rg_exc_code$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_ld_val - reg [63 : 0] rg_ld_val; - reg [63 : 0] rg_ld_val$D_IN; - wire rg_ld_val$EN; - - // register rg_lower_word32 - reg [31 : 0] rg_lower_word32; - wire [31 : 0] rg_lower_word32$D_IN; - wire rg_lower_word32$EN; - - // register rg_lower_word32_full - reg rg_lower_word32_full; - wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN; - - // register rg_lrsc_pa - reg [31 : 0] rg_lrsc_pa; - wire [31 : 0] rg_lrsc_pa$D_IN; - wire rg_lrsc_pa$EN; - - // register rg_lrsc_valid - reg rg_lrsc_valid; - wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN; - - // register rg_op - reg [1 : 0] rg_op; - wire [1 : 0] rg_op$D_IN; - wire rg_op$EN; - - // register rg_pa - reg [31 : 0] rg_pa; - wire [31 : 0] rg_pa$D_IN; - wire rg_pa$EN; - - // register rg_pte_pa - reg [31 : 0] rg_pte_pa; - wire [31 : 0] rg_pte_pa$D_IN; - wire rg_pte_pa$EN; - - // register rg_st_amo_val - reg [63 : 0] rg_st_amo_val; - wire [63 : 0] rg_st_amo_val$D_IN; - wire rg_st_amo_val$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_word64_set_in_cache - reg [8 : 0] rg_word64_set_in_cache; - wire [8 : 0] rg_word64_set_in_cache$D_IN; - wire rg_word64_set_in_cache$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule ram_state_and_ctag_cset - wire [22 : 0] ram_state_and_ctag_cset$DIA, - ram_state_and_ctag_cset$DIB, - ram_state_and_ctag_cset$DOB; - wire [6 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB; - wire ram_state_and_ctag_cset$ENA, - ram_state_and_ctag_cset$ENB, - ram_state_and_ctag_cset$WEA, - ram_state_and_ctag_cset$WEB; - - // ports of submodule ram_word64_set - reg [63 : 0] ram_word64_set$DIB; - reg [8 : 0] ram_word64_set$ADDRB; - wire [63 : 0] ram_word64_set$DIA, ram_word64_set$DOB; - wire [8 : 0] ram_word64_set$ADDRA; - wire ram_word64_set$ENA, - ram_word64_set$ENB, - ram_word64_set$WEA, - ram_word64_set$WEB; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - wire soc_map$m_is_mem_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_ST_AMO_response, - CAN_FIRE_RL_rl_cache_refill_rsps_loop, - CAN_FIRE_RL_rl_discard_write_rsp, - CAN_FIRE_RL_rl_drive_exception_rsp, - CAN_FIRE_RL_rl_io_AMO_SC_req, - CAN_FIRE_RL_rl_io_AMO_op_req, - CAN_FIRE_RL_rl_io_AMO_read_rsp, - CAN_FIRE_RL_rl_io_read_req, - CAN_FIRE_RL_rl_io_read_rsp, - CAN_FIRE_RL_rl_io_write_req, - CAN_FIRE_RL_rl_maintain_io_read_rsp, - CAN_FIRE_RL_rl_probe_and_immed_rsp, - CAN_FIRE_RL_rl_rereq, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_shift_sb_to_load_delay, - CAN_FIRE_RL_rl_start_cache_refill, - CAN_FIRE_RL_rl_start_reset, - CAN_FIRE_mem_master_m_arready, - CAN_FIRE_mem_master_m_awready, - CAN_FIRE_mem_master_m_bvalid, - CAN_FIRE_mem_master_m_rvalid, - CAN_FIRE_mem_master_m_wready, - CAN_FIRE_req, - CAN_FIRE_server_flush_request_put, - CAN_FIRE_server_flush_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_verbosity, - CAN_FIRE_tlb_flush, - WILL_FIRE_RL_rl_ST_AMO_response, - WILL_FIRE_RL_rl_cache_refill_rsps_loop, - WILL_FIRE_RL_rl_discard_write_rsp, - WILL_FIRE_RL_rl_drive_exception_rsp, - WILL_FIRE_RL_rl_io_AMO_SC_req, - WILL_FIRE_RL_rl_io_AMO_op_req, - WILL_FIRE_RL_rl_io_AMO_read_rsp, - WILL_FIRE_RL_rl_io_read_req, - WILL_FIRE_RL_rl_io_read_rsp, - WILL_FIRE_RL_rl_io_write_req, - WILL_FIRE_RL_rl_maintain_io_read_rsp, - WILL_FIRE_RL_rl_probe_and_immed_rsp, - WILL_FIRE_RL_rl_rereq, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_shift_sb_to_load_delay, - WILL_FIRE_RL_rl_start_cache_refill, - WILL_FIRE_RL_rl_start_reset, - WILL_FIRE_mem_master_m_arready, - WILL_FIRE_mem_master_m_awready, - WILL_FIRE_mem_master_m_bvalid, - WILL_FIRE_mem_master_m_rvalid, - WILL_FIRE_mem_master_m_wready, - WILL_FIRE_req, - WILL_FIRE_server_flush_request_put, - WILL_FIRE_server_flush_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_verbosity, - WILL_FIRE_tlb_flush; - - // inputs to muxes for submodule ports - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2, - MUX_master_xactor_rg_wr_addr$write_1__VAL_1, - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - wire [76 : 0] MUX_master_xactor_rg_wr_data$write_1__VAL_1, - MUX_master_xactor_rg_wr_data$write_1__VAL_2, - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3, - MUX_ram_word64_set$a_put_3__VAL_2, - MUX_rg_ld_val$write_1__VAL_2; - wire [22 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1; - wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2, - MUX_ram_word64_set$b_put_2__VAL_4; - wire [6 : 0] MUX_rg_cset_in_cache$write_1__VAL_1; - wire [3 : 0] MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_1, - MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_4, - MUX_rg_state$write_1__VAL_8, - MUX_rg_state$write_1__VAL_9; - wire MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1, - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2, - MUX_dw_output_ld_val$wset_1__SEL_1, - MUX_dw_output_ld_val$wset_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_4, - MUX_master_xactor_rg_rd_addr$write_1__SEL_1, - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1, - MUX_ram_word64_set$a_put_1__SEL_1, - MUX_ram_word64_set$b_put_1__SEL_2, - MUX_rg_error_during_refill$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_2, - MUX_rg_exc_code$write_1__SEL_3, - MUX_rg_ld_val$write_1__SEL_2, - MUX_rg_lrsc_valid$write_1__SEL_2, - MUX_rg_state$write_1__SEL_13, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h3732; - reg [31 : 0] v__h3833; - reg [31 : 0] v__h25372; - reg [31 : 0] v__h26270; - reg [31 : 0] v__h3369; - reg [31 : 0] v__h4284; - reg [31 : 0] v__h12756; - reg [31 : 0] v__h17072; - reg [31 : 0] v__h16400; - reg [31 : 0] v__h20538; - reg [31 : 0] v__h21833; - reg [31 : 0] v__h22074; - reg [31 : 0] v__h24060; - reg [31 : 0] v__h25160; - reg [31 : 0] v__h25267; - reg [31 : 0] v__h25452; - reg [31 : 0] v__h25974; - reg [31 : 0] v__h26388; - reg [31 : 0] v__h26706; - reg [31 : 0] v__h26881; - reg [31 : 0] v__h29494; - reg [31 : 0] v__h29746; - reg [31 : 0] v__h26977; - reg [31 : 0] v__h20983; - reg [31 : 0] v__h23686; - reg [31 : 0] v__h30715; - reg [31 : 0] v__h30366; - reg [31 : 0] v__h30327; - reg [31 : 0] v__h3363; - reg [31 : 0] v__h3726; - reg [31 : 0] v__h3827; - reg [31 : 0] v__h4278; - reg [31 : 0] v__h12750; - reg [31 : 0] v__h16394; - reg [31 : 0] v__h17066; - reg [31 : 0] v__h20532; - reg [31 : 0] v__h20977; - reg [31 : 0] v__h21827; - reg [31 : 0] v__h22068; - reg [31 : 0] v__h23680; - reg [31 : 0] v__h24054; - reg [31 : 0] v__h25154; - reg [31 : 0] v__h25261; - reg [31 : 0] v__h25366; - reg [31 : 0] v__h25446; - reg [31 : 0] v__h25968; - reg [31 : 0] v__h26264; - reg [31 : 0] v__h26382; - reg [31 : 0] v__h26700; - reg [31 : 0] v__h26875; - reg [31 : 0] v__h26971; - reg [31 : 0] v__h29488; - reg [31 : 0] v__h29740; - reg [31 : 0] v__h30321; - reg [31 : 0] v__h30360; - reg [31 : 0] v__h30709; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32, - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51, - CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29, - CASE_rg_addr_BITS_2_TO_0_0x0_result4940_0x4_re_ETC__q33, - CASE_rg_addr_BITS_2_TO_0_0x0_result5005_0x4_re_ETC__q34, - CASE_rg_addr_BITS_2_TO_0_0x0_result9094_0x4_re_ETC__q49, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d670, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d803, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d662, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427, - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362, - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436, - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304, - _theResult_____2__h17631, - _theResult_____2__h27299, - ld_val__h24169, - mem_req_wr_data_wdata__h16837, - mem_req_wr_data_wdata__h20334, - mem_req_wr_data_wdata__h25770, - mem_req_wr_data_wdata__h27274, - new_ld_val__h27007, - new_value__h15491, - new_value__h5462, - w1__h17623, - w1__h27287, - w1__h27291; - reg [7 : 0] mem_req_wr_data_wstrb__h20335, mem_req_wr_data_wstrb__h27275; - reg [2 : 0] value__h26592, value__h29618; - wire [63 : 0] IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_1_EL_ETC___d273, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d804, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259, - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368, - IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d468, - _theResult___snd_fst__h16845, - _theResult___snd_fst__h20342, - _theResult___snd_fst__h25778, - _theResult___snd_fst__h27282, - cline_fabric_addr__h21036, - mem_req_wr_addr_awaddr__h20129, - mem_req_wr_addr_awaddr__h27069, - new_st_val__h17353, - new_st_val__h17635, - new_st_val__h17726, - new_st_val__h18706, - new_st_val__h18710, - new_st_val__h18714, - new_st_val__h18718, - new_st_val__h18723, - new_st_val__h18729, - new_st_val__h18734, - new_st_val__h27303, - new_st_val__h27394, - new_st_val__h29254, - new_st_val__h29258, - new_st_val__h29262, - new_st_val__h29266, - new_st_val__h29271, - new_st_val__h29277, - new_st_val__h29282, - result__h11873, - result__h11901, - result__h11929, - result__h11957, - result__h11985, - result__h12013, - result__h12041, - result__h12086, - result__h12114, - result__h12142, - result__h12170, - result__h12198, - result__h12226, - result__h12254, - result__h12282, - result__h12327, - result__h12355, - result__h12383, - result__h12411, - result__h12452, - result__h12480, - result__h12508, - result__h12536, - result__h12577, - result__h12605, - result__h12644, - result__h12672, - result__h24229, - result__h24259, - result__h24286, - result__h24313, - result__h24340, - result__h24367, - result__h24394, - result__h24421, - result__h24465, - result__h24492, - result__h24519, - result__h24546, - result__h24573, - result__h24600, - result__h24627, - result__h24654, - result__h24698, - result__h24725, - result__h24752, - result__h24779, - result__h24819, - result__h24846, - result__h24873, - result__h24900, - result__h24940, - result__h24967, - result__h25005, - result__h25032, - result__h27482, - result__h28390, - result__h28418, - result__h28446, - result__h28474, - result__h28502, - result__h28530, - result__h28558, - result__h28603, - result__h28631, - result__h28659, - result__h28687, - result__h28715, - result__h28743, - result__h28771, - result__h28799, - result__h28844, - result__h28872, - result__h28900, - result__h28928, - result__h28969, - result__h28997, - result__h29025, - result__h29053, - result__h29094, - result__h29122, - result__h29161, - result__h29189, - result__h5517, - st_val__h27019, - w1___1__h17694, - w1___1__h27362, - w2___1__h27363, - w2__h27293, - word64__h5280, - x__h13143, - y__h5553; - wire [31 : 0] cline_addr__h21035, - ld_val4169_BITS_31_TO_0__q37, - ld_val4169_BITS_63_TO_32__q44, - master_xactor_rg_rd_data_BITS_34_TO_3__q3, - master_xactor_rg_rd_data_BITS_66_TO_35__q10, - new_value462_BITS_31_TO_0__q30, - rg_st_amo_val_BITS_31_TO_0__q31, - w17287_BITS_31_TO_0__q50, - word64280_BITS_31_TO_0__q17, - word64280_BITS_63_TO_32__q24; - wire [21 : 0] pa_ctag__h5138; - wire [15 : 0] ld_val4169_BITS_15_TO_0__q36, - ld_val4169_BITS_31_TO_16__q40, - ld_val4169_BITS_47_TO_32__q43, - ld_val4169_BITS_63_TO_48__q47, - master_xactor_rg_rd_data_BITS_18_TO_3__q2, - master_xactor_rg_rd_data_BITS_34_TO_19__q6, - master_xactor_rg_rd_data_BITS_50_TO_35__q9, - master_xactor_rg_rd_data_BITS_66_TO_51__q13, - word64280_BITS_15_TO_0__q16, - word64280_BITS_31_TO_16__q20, - word64280_BITS_47_TO_32__q23, - word64280_BITS_63_TO_48__q27; - wire [7 : 0] ld_val4169_BITS_15_TO_8__q38, - ld_val4169_BITS_23_TO_16__q39, - ld_val4169_BITS_31_TO_24__q41, - ld_val4169_BITS_39_TO_32__q42, - ld_val4169_BITS_47_TO_40__q45, - ld_val4169_BITS_55_TO_48__q46, - ld_val4169_BITS_63_TO_56__q48, - ld_val4169_BITS_7_TO_0__q35, - master_xactor_rg_rd_data_BITS_10_TO_3__q1, - master_xactor_rg_rd_data_BITS_18_TO_11__q4, - master_xactor_rg_rd_data_BITS_26_TO_19__q5, - master_xactor_rg_rd_data_BITS_34_TO_27__q7, - master_xactor_rg_rd_data_BITS_42_TO_35__q8, - master_xactor_rg_rd_data_BITS_50_TO_43__q11, - master_xactor_rg_rd_data_BITS_58_TO_51__q12, - master_xactor_rg_rd_data_BITS_66_TO_59__q14, - strobe64__h20268, - strobe64__h20270, - strobe64__h20272, - strobe64__h27208, - strobe64__h27210, - strobe64__h27212, - word64280_BITS_15_TO_8__q18, - word64280_BITS_23_TO_16__q19, - word64280_BITS_31_TO_24__q21, - word64280_BITS_39_TO_32__q22, - word64280_BITS_47_TO_40__q25, - word64280_BITS_55_TO_48__q26, - word64280_BITS_63_TO_56__q28, - word64280_BITS_7_TO_0__q15; - wire [5 : 0] shift_bits__h20135, shift_bits__h27075; - wire [3 : 0] IF_rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d112, - IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d111, - access_exc_code__h2925, - b__h20937; - wire IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d80, - NOT_cfg_verbosity_read__0_ULE_1_1___d12, - NOT_cfg_verbosity_read__0_ULE_2_57___d558, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d300, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d311, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d445, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d481, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d493, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d521, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d528, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d534, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d536, - NOT_ram_state_and_ctag_cset_b_read__0_BIT_22_1_ETC___d121, - NOT_req_f3_BITS_1_TO_0_94_EQ_0b0_95_96_AND_NOT_ETC___d915, - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d107, - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448, - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d496, - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504, - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d509, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d130, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d308, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d442, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d519, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d522, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d526, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d532, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d306, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d440, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d494, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d498, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d502, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d507, - dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d82, - lrsc_result__h13133, - master_xactor_crg_rd_data_full_port1__read__54_ETC___d727, - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76, - ram_state_and_ctag_cset_b_read__0_BIT_22_1_AND_ETC___d122, - req_f3_BITS_1_TO_0_94_EQ_0b0_95_OR_req_f3_BITS_ETC___d924, - rg_addr_0_EQ_rg_lrsc_pa_9___d119, - rg_amo_funct7_8_BITS_6_TO_2_9_EQ_0b10_0_AND_NO_ETC___d294, - rg_lrsc_pa_9_EQ_rg_addr_0___d60, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d102, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d133, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d135, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d138, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d277, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d290, - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d131, - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d309, - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d443, - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d446, - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d515, - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d69, - rg_state_EQ_12_93_AND_rg_op_5_EQ_0_6_OR_rg_op__ETC___d595, - rg_state_EQ_3_3_AND_NOT_rg_op_5_EQ_0_6_4_AND_N_ETC___d92; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method addr - assign addr = rg_addr ; - - // value method word64 - always@(MUX_dw_output_ld_val$wset_1__SEL_1 or - ld_val__h24169 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h27007 or - MUX_dw_output_ld_val$wset_1__SEL_3 or - MUX_dw_output_ld_val$wset_1__VAL_3 or - MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h24169; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - word64 = new_ld_val__h27007; - MUX_dw_output_ld_val$wset_1__SEL_3: - word64 = MUX_dw_output_ld_val$wset_1__VAL_3; - MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val; - default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // value method st_amo_val - assign st_amo_val = - MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ; - - // value method exc - assign exc = rg_state == 4'd4 ; - - // value method exc_code - assign exc_code = rg_exc_code ; - - // action method server_flush_request_put - assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; - - // action method server_flush_response_get - assign RDY_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; - - // action method tlb_flush - assign RDY_tlb_flush = 1'd1 ; - assign CAN_FIRE_tlb_flush = 1'd1 ; - assign WILL_FIRE_tlb_flush = EN_tlb_flush ; - - // value method mem_master_m_awvalid - assign mem_master_awvalid = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - - // value method mem_master_m_awid - assign mem_master_awid = master_xactor_rg_wr_addr[96:93] ; - - // value method mem_master_m_awaddr - assign mem_master_awaddr = master_xactor_rg_wr_addr[92:29] ; - - // value method mem_master_m_awlen - assign mem_master_awlen = master_xactor_rg_wr_addr[28:21] ; - - // value method mem_master_m_awsize - assign mem_master_awsize = master_xactor_rg_wr_addr[20:18] ; - - // value method mem_master_m_awburst - assign mem_master_awburst = master_xactor_rg_wr_addr[17:16] ; - - // value method mem_master_m_awlock - assign mem_master_awlock = master_xactor_rg_wr_addr[15] ; - - // value method mem_master_m_awcache - assign mem_master_awcache = master_xactor_rg_wr_addr[14:11] ; - - // value method mem_master_m_awprot - assign mem_master_awprot = master_xactor_rg_wr_addr[10:8] ; - - // value method mem_master_m_awqos - assign mem_master_awqos = master_xactor_rg_wr_addr[7:4] ; - - // value method mem_master_m_awregion - assign mem_master_awregion = master_xactor_rg_wr_addr[3:0] ; - - // action method mem_master_m_awready - assign CAN_FIRE_mem_master_m_awready = 1'd1 ; - assign WILL_FIRE_mem_master_m_awready = 1'd1 ; - - // value method mem_master_m_wvalid - assign mem_master_wvalid = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - - // value method mem_master_m_wid - assign mem_master_wid = master_xactor_rg_wr_data[76:73] ; - - // value method mem_master_m_wdata - assign mem_master_wdata = master_xactor_rg_wr_data[72:9] ; - - // value method mem_master_m_wstrb - assign mem_master_wstrb = master_xactor_rg_wr_data[8:1] ; - - // value method mem_master_m_wlast - assign mem_master_wlast = master_xactor_rg_wr_data[0] ; - - // action method mem_master_m_wready - assign CAN_FIRE_mem_master_m_wready = 1'd1 ; - assign WILL_FIRE_mem_master_m_wready = 1'd1 ; - - // action method mem_master_m_bvalid - assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ; - - // value method mem_master_m_bready - assign mem_master_bready = !master_xactor_crg_wr_resp_full$port2__read ; - - // value method mem_master_m_arvalid - assign mem_master_arvalid = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - - // value method mem_master_m_arid - assign mem_master_arid = master_xactor_rg_rd_addr[96:93] ; - - // value method mem_master_m_araddr - assign mem_master_araddr = master_xactor_rg_rd_addr[92:29] ; - - // value method mem_master_m_arlen - assign mem_master_arlen = master_xactor_rg_rd_addr[28:21] ; - - // value method mem_master_m_arsize - assign mem_master_arsize = master_xactor_rg_rd_addr[20:18] ; - - // value method mem_master_m_arburst - assign mem_master_arburst = master_xactor_rg_rd_addr[17:16] ; - - // value method mem_master_m_arlock - assign mem_master_arlock = master_xactor_rg_rd_addr[15] ; - - // value method mem_master_m_arcache - assign mem_master_arcache = master_xactor_rg_rd_addr[14:11] ; - - // value method mem_master_m_arprot - assign mem_master_arprot = master_xactor_rg_rd_addr[10:8] ; - - // value method mem_master_m_arqos - assign mem_master_arqos = master_xactor_rg_rd_addr[7:4] ; - - // value method mem_master_m_arregion - assign mem_master_arregion = master_xactor_rg_rd_addr[3:0] ; - - // action method mem_master_m_arready - assign CAN_FIRE_mem_master_m_arready = 1'd1 ; - assign WILL_FIRE_mem_master_m_arready = 1'd1 ; - - // action method mem_master_m_rvalid - assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ; - - // value method mem_master_m_rready - assign mem_master_rready = !master_xactor_crg_rd_data_full$port2__read ; - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule ram_state_and_ctag_cset - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd7), - .DATA_WIDTH(32'd23), - .MEMSIZE(8'd128)) ram_state_and_ctag_cset(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_state_and_ctag_cset$ADDRA), - .ADDRB(ram_state_and_ctag_cset$ADDRB), - .DIA(ram_state_and_ctag_cset$DIA), - .DIB(ram_state_and_ctag_cset$DIB), - .WEA(ram_state_and_ctag_cset$WEA), - .WEB(ram_state_and_ctag_cset$WEB), - .ENA(ram_state_and_ctag_cset$ENA), - .ENB(ram_state_and_ctag_cset$ENB), - .DOA(), - .DOB(ram_state_and_ctag_cset$DOB)); - - // submodule ram_word64_set - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd9), - .DATA_WIDTH(32'd64), - .MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_word64_set$ADDRA), - .ADDRB(ram_word64_set$ADDRB), - .DIA(ram_word64_set$DIA), - .DIB(ram_word64_set$DIB), - .WEA(ram_word64_set$WEA), - .WEB(ram_word64_set$WEB), - .ENA(ram_word64_set$ENA), - .ENB(ram_word64_set$ENB), - .DOA(), - .DOB(ram_word64_set$DOB)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(soc_map$m_is_mem_addr), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - (rg_cset_in_cache != 7'd127 || - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) && - rg_state == 4'd1 ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // rule RL_rl_shift_sb_to_load_delay - assign CAN_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - assign WILL_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - - // rule RL_rl_rereq - assign CAN_FIRE_RL_rl_rereq = rg_state == 4'd10 ; - assign WILL_FIRE_RL_rl_rereq = - CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ; - - // rule RL_rl_ST_AMO_response - assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 4'd11 ; - assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ; - - // rule RL_rl_maintain_io_read_rsp - assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 4'd14 ; - assign WILL_FIRE_RL_rl_maintain_io_read_rsp = - CAN_FIRE_RL_rl_maintain_io_read_rsp ; - - // rule RL_rl_io_AMO_SC_req - assign CAN_FIRE_RL_rl_io_AMO_SC_req = - rg_state == 4'd12 && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_SC_req = - CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_drive_exception_rsp - assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ; - assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ; - - // rule RL_rl_start_reset - assign CAN_FIRE_RL_rl_start_reset = - f_reset_reqs$EMPTY_N && rg_state != 4'd1 ; - assign WILL_FIRE_RL_rl_start_reset = CAN_FIRE_RL_rl_start_reset ; - - // rule RL_rl_probe_and_immed_rsp - assign CAN_FIRE_RL_rl_probe_and_immed_rsp = - dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d82 && - rg_state_EQ_3_3_AND_NOT_rg_op_5_EQ_0_6_4_AND_N_ETC___d92 ; - assign WILL_FIRE_RL_rl_probe_and_immed_rsp = - CAN_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_cache_refill_rsps_loop - assign CAN_FIRE_RL_rl_cache_refill_rsps_loop = - master_xactor_crg_rd_data_full$port1__read && rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_cache_refill_rsps_loop = - CAN_FIRE_RL_rl_cache_refill_rsps_loop && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_rsp - assign CAN_FIRE_RL_rl_io_read_rsp = - master_xactor_crg_rd_data_full$port1__read && rg_state == 4'd13 ; - assign WILL_FIRE_RL_rl_io_read_rsp = - CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_write_req - assign CAN_FIRE_RL_rl_io_write_req = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - rg_state == 4'd12 && - rg_op == 2'd1 ; - assign WILL_FIRE_RL_rl_io_write_req = - CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_op_req - assign CAN_FIRE_RL_rl_io_AMO_op_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 4'd12 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] != 5'b00010 && - rg_amo_funct7[6:2] != 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_op_req = - CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_read_rsp - assign CAN_FIRE_RL_rl_io_AMO_read_rsp = - master_xactor_crg_rd_data_full_port1__read__54_ETC___d727 && - rg_state == 4'd15 ; - assign WILL_FIRE_RL_rl_io_AMO_read_rsp = - CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_cache_refill - assign CAN_FIRE_RL_rl_start_cache_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 4'd8 && - b__h20937 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_cache_refill = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_io_read_req - assign CAN_FIRE_RL_rl_io_read_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state_EQ_12_93_AND_rg_op_5_EQ_0_6_OR_rg_op__ETC___d595 ; - assign WILL_FIRE_RL_rl_io_read_req = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_discard_write_rsp - assign CAN_FIRE_RL_rl_discard_write_rsp = - b__h20937 != 4'd0 && master_xactor_crg_wr_resp_full$port1__read ; - assign WILL_FIRE_RL_rl_discard_write_rsp = - CAN_FIRE_RL_rl_discard_write_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // inputs to muxes for submodule ports - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 ; - assign MUX_dw_output_ld_val$wset_1__SEL_1 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_dw_output_ld_val$wset_1__SEL_3 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d138 ; - assign MUX_dw_output_ld_val$wset_1__SEL_4 = - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_1 = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ; - assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 = - EN_req && - req_f3_BITS_1_TO_0_94_EQ_0b0_95_OR_req_f3_BITS_ETC___d924 ; - assign MUX_ram_word64_set$a_put_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ram_word64_set$b_put_1__SEL_2 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 ; - assign MUX_rg_error_during_refill$write_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_1 = - EN_req && - NOT_req_f3_BITS_1_TO_0_94_EQ_0b0_95_96_AND_NOT_ETC___d915 ; - assign MUX_rg_exc_code$write_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_3 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_ld_val$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d300 ; - assign MUX_rg_lrsc_valid$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d133 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ; - assign MUX_rg_state$write_1__SEL_3 = - CAN_FIRE_RL_rl_start_cache_refill && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - assign MUX_rg_state$write_1__SEL_8 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 ; - assign MUX_rg_state$write_1__SEL_9 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (dmem_not_imem && !soc_map$m_is_mem_addr || - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d102 || - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d107) ; - assign MUX_rg_state$write_1__SEL_13 = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 = - ctr_wr_rsps_pending_crg + 4'd1 ; - assign MUX_dw_output_ld_val$wset_1__VAL_3 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - new_value__h5462 : - new_value__h15491 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, - mem_req_wr_addr_awaddr__h27069, - 8'd0, - value__h26592, - 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, cline_fabric_addr__h21036, 29'd7143424 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_1 = - { 4'd0, - mem_req_wr_addr_awaddr__h27069, - 8'd0, - value__h29618, - 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_2 = - { 4'd0, - mem_req_wr_addr_awaddr__h20129, - 8'd0, - value__h29618, - 18'd65536 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_1 = - { 4'd0, - mem_req_wr_data_wdata__h27274, - mem_req_wr_data_wstrb__h27275, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_2 = - { 4'd0, - IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d468, - mem_req_wr_data_wstrb__h20335, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_3 = - { 4'd0, - mem_req_wr_data_wdata__h25770, - mem_req_wr_data_wstrb__h27275, - 1'd1 } ; - assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 = { 3'd4, rg_pa[31:12] } ; - assign MUX_ram_word64_set$a_put_3__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 : - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 ; - assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ; - assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:5], 2'd0 } ; - assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 7'd1 ; - assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ; - assign MUX_rg_ld_val$write_1__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - x__h13143 : - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 ; - assign MUX_rg_state$write_1__VAL_1 = - NOT_req_f3_BITS_1_TO_0_94_EQ_0b0_95_96_AND_NOT_ETC___d915 ? - 4'd4 : - 4'd3 ; - assign MUX_rg_state$write_1__VAL_4 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? 4'd14 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_8 = - (master_xactor_rg_rd_data[2:1] != 2'b0 || - rg_error_during_refill) ? - 4'd4 : - 4'd10 ; - assign MUX_rg_state$write_1__VAL_9 = - (dmem_not_imem && !soc_map$m_is_mem_addr) ? - 4'd12 : - IF_rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d112 ; - - // inlined wires - assign dw_valid$whas = - (WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_io_read_rsp) && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d138 || - WILL_FIRE_RL_rl_drive_exception_rsp || - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign master_xactor_crg_wr_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_addr_full$port1__read = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full$port1__read && - mem_master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full$port1__read ; - assign master_xactor_crg_wr_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 || - WILL_FIRE_RL_rl_io_write_req ; - assign master_xactor_crg_wr_addr_full$port3__read = - master_xactor_crg_wr_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_data_full$port1__read = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full$port1__read && mem_master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full$port1__read ; - assign master_xactor_crg_wr_data_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 || - WILL_FIRE_RL_rl_io_write_req ; - assign master_xactor_crg_wr_data_full$port3__read = - master_xactor_crg_wr_data_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_wr_resp_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_resp_full$port1__read = - !master_xactor_crg_wr_resp_full$EN_port0__write && - master_xactor_crg_wr_resp_full ; - assign master_xactor_crg_wr_resp_full$port2__read = - !WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_crg_wr_resp_full$port1__read ; - assign master_xactor_crg_wr_resp_full$EN_port2__write = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_wr_resp_full$port3__read = - master_xactor_crg_wr_resp_full$EN_port2__write || - master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_addr_full$port1__read = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full$port1__read && - mem_master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full$port1__read ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write || - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_data_full$port1__read = - !master_xactor_crg_rd_data_full$EN_port0__write && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port1__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp || WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_cache_refill_rsps_loop ; - assign master_xactor_crg_rd_data_full$port2__read = - !master_xactor_crg_rd_data_full$EN_port1__write && - master_xactor_crg_rd_data_full$port1__read ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - mem_master_rvalid && - !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - assign ctr_wr_rsps_pending_crg$EN_port0__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 || - WILL_FIRE_RL_rl_io_write_req ; - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - WILL_FIRE_RL_rl_io_write_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - WILL_FIRE_RL_rl_io_write_req: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - default: ctr_wr_rsps_pending_crg$port0__write_1 = - 4'b1010 /* unspecified value */ ; - endcase - end - assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h20937 - 4'd1 ; - assign ctr_wr_rsps_pending_crg$port2__read = - WILL_FIRE_RL_rl_discard_write_rsp ? - ctr_wr_rsps_pending_crg$port1__write_1 : - b__h20937 ; - assign ctr_wr_rsps_pending_crg$EN_port2__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign ctr_wr_rsps_pending_crg$port3__read = - ctr_wr_rsps_pending_crg$EN_port2__write ? - 4'd0 : - ctr_wr_rsps_pending_crg$port2__read ; - assign crg_sb_to_load_delay$port0__write_1 = - { 1'd0, crg_sb_to_load_delay[10:1] } ; - assign crg_sb_to_load_delay$EN_port1__write = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d445 ; - assign crg_sb_to_load_delay$port2__read = - crg_sb_to_load_delay$EN_port1__write ? - 11'd2047 : - crg_sb_to_load_delay$port0__write_1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register crg_sb_to_load_delay - assign crg_sb_to_load_delay$D_IN = crg_sb_to_load_delay$port2__read ; - assign crg_sb_to_load_delay$EN = 1'b1 ; - - // register ctr_wr_rsps_pending_crg - assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ; - assign ctr_wr_rsps_pending_crg$EN = 1'b1 ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = - master_xactor_crg_wr_resp_full$port3__read ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - assign master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__SEL_1 ? - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 : - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ; - assign master_xactor_rg_rd_addr$EN = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - default: master_xactor_rg_wr_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_addr$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_data - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_data$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_data$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req or - MUX_master_xactor_rg_wr_data$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - default: master_xactor_rg_wr_data$D_IN = - 77'h0AAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_data$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = - { mem_master_bid, mem_master_bresp } ; - assign master_xactor_rg_wr_resp$EN = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - - // register rg_addr - assign rg_addr$D_IN = req_addr ; - assign rg_addr$EN = EN_req ; - - // register rg_amo_funct7 - assign rg_amo_funct7$D_IN = req_amo_funct7 ; - assign rg_amo_funct7$EN = EN_req ; - - // register rg_cset_in_cache - assign rg_cset_in_cache$D_IN = - WILL_FIRE_RL_rl_reset ? - MUX_rg_cset_in_cache$write_1__VAL_1 : - 7'd0 ; - assign rg_cset_in_cache$EN = - WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ; - - // register rg_error_during_refill - assign rg_error_during_refill$D_IN = - MUX_rg_error_during_refill$write_1__SEL_1 ; - assign rg_error_during_refill$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register rg_exc_code - always@(MUX_rg_exc_code$write_1__SEL_1 or - MUX_rg_exc_code$write_1__VAL_1 or - MUX_rg_exc_code$write_1__SEL_2 or - MUX_rg_exc_code$write_1__SEL_3 or - MUX_rg_error_during_refill$write_1__SEL_1 or access_exc_code__h2925) - case (1'b1) - MUX_rg_exc_code$write_1__SEL_1: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1; - MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7; - MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5; - MUX_rg_error_during_refill$write_1__SEL_1: - rg_exc_code$D_IN = access_exc_code__h2925; - default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_exc_code$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - EN_req && - NOT_req_f3_BITS_1_TO_0_94_EQ_0b0_95_96_AND_NOT_ETC___d915 ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_ld_val - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h27007 or - MUX_rg_ld_val$write_1__SEL_2 or - MUX_rg_ld_val$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_rsp or - ld_val__h24169 or WILL_FIRE_RL_rl_io_AMO_SC_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - rg_ld_val$D_IN = new_ld_val__h27007; - MUX_rg_ld_val$write_1__SEL_2: - rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h24169; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1; - default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_ld_val$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d300 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_SC_req ; - - // register rg_lower_word32 - assign rg_lower_word32$D_IN = 32'h0 ; - assign rg_lower_word32$EN = 1'b0 ; - - // register rg_lower_word32_full - assign rg_lower_word32_full$D_IN = 1'd0 ; - assign rg_lower_word32_full$EN = - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_lrsc_pa - assign rg_lrsc_pa$D_IN = rg_addr ; - assign rg_lrsc_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 ; - - // register rg_lrsc_valid - assign rg_lrsc_valid$D_IN = - MUX_rg_lrsc_valid$write_1__SEL_2 && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d135 ; - assign rg_lrsc_valid$EN = - WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d133 || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_op - assign rg_op$D_IN = req_op ; - assign rg_op$EN = EN_req ; - - // register rg_pa - assign rg_pa$D_IN = EN_req ? req_addr : rg_addr ; - assign rg_pa$EN = EN_req || WILL_FIRE_RL_rl_probe_and_immed_rsp ; - - // register rg_pte_pa - assign rg_pte_pa$D_IN = 32'h0 ; - assign rg_pte_pa$EN = 1'b0 ; - - // register rg_st_amo_val - assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h17353 ; - assign rg_st_amo_val$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d536 || - EN_req ; - - // register rg_state - always@(EN_req or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_io_read_req or - WILL_FIRE_RL_rl_start_cache_refill or - WILL_FIRE_RL_rl_io_AMO_read_rsp or - MUX_rg_state$write_1__VAL_4 or - WILL_FIRE_RL_rl_io_AMO_op_req or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_io_read_rsp or - MUX_rg_state$write_1__SEL_8 or - MUX_rg_state$write_1__VAL_8 or - MUX_rg_state$write_1__SEL_9 or - MUX_rg_state$write_1__VAL_9 or - WILL_FIRE_RL_rl_start_reset or - WILL_FIRE_RL_rl_io_AMO_SC_req or - WILL_FIRE_RL_rl_rereq or MUX_rg_state$write_1__SEL_13) - case (1'b1) - EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 4'd13; - WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_io_AMO_read_rsp: - rg_state$D_IN = MUX_rg_state$write_1__VAL_4; - WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 4'd15; - WILL_FIRE_RL_rl_io_write_req: rg_state$D_IN = 4'd11; - WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_4; - MUX_rg_state$write_1__SEL_8: rg_state$D_IN = MUX_rg_state$write_1__VAL_8; - MUX_rg_state$write_1__SEL_9: rg_state$D_IN = MUX_rg_state$write_1__VAL_9; - WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 4'd1; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_state$D_IN = 4'd11; - WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_13: rg_state$D_IN = 4'd2; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_state$EN = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 || - MUX_rg_state$write_1__SEL_9 || - WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_io_read_rsp || - EN_req || - WILL_FIRE_RL_rl_start_reset || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_io_AMO_SC_req || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_io_AMO_op_req ; - - // register rg_word64_set_in_cache - assign rg_word64_set_in_cache$D_IN = - MUX_ram_word64_set$b_put_1__SEL_2 ? - MUX_ram_word64_set$b_put_2__VAL_2 : - MUX_ram_word64_set$b_put_2__VAL_4 ; - assign rg_word64_set_in_cache$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = !EN_server_reset_request_put ; - assign f_reset_reqs$ENQ = - EN_server_reset_request_put || EN_server_flush_request_put ; - assign f_reset_reqs$DEQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ; - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign f_reset_rsps$DEQ = - EN_server_flush_response_get || EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule ram_state_and_ctag_cset - assign ram_state_and_ctag_cset$ADDRA = - WILL_FIRE_RL_rl_start_cache_refill ? - rg_addr[11:5] : - rg_cset_in_cache ; - assign ram_state_and_ctag_cset$ADDRB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - req_addr[11:5] : - rg_addr[11:5] ; - assign ram_state_and_ctag_cset$DIA = - WILL_FIRE_RL_rl_start_cache_refill ? - MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 : - 23'd2796202 ; - assign ram_state_and_ctag_cset$DIB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - 23'b01010101010101010101010 /* unspecified value */ : - 23'b01010101010101010101010 /* unspecified value */ ; - assign ram_state_and_ctag_cset$WEA = 1'd1 ; - assign ram_state_and_ctag_cset$WEB = 1'd0 ; - assign ram_state_and_ctag_cset$ENA = - WILL_FIRE_RL_rl_start_cache_refill || WILL_FIRE_RL_rl_reset ; - assign ram_state_and_ctag_cset$ENB = - EN_req && - req_f3_BITS_1_TO_0_94_EQ_0b0_95_OR_req_f3_BITS_ETC___d924 || - WILL_FIRE_RL_rl_rereq ; - - // submodule ram_word64_set - assign ram_word64_set$ADDRA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - rg_word64_set_in_cache : - rg_addr[11:3] ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - req_addr or - MUX_ram_word64_set$b_put_1__SEL_2 or - MUX_ram_word64_set$b_put_2__VAL_2 or - WILL_FIRE_RL_rl_rereq or - rg_addr or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_ram_word64_set$b_put_2__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$ADDRB = req_addr[11:3]; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2; - WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3]; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4; - default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ; - endcase - end - assign ram_word64_set$DIA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - master_xactor_rg_rd_data[66:3] : - MUX_ram_word64_set$a_put_3__VAL_2 ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - MUX_ram_word64_set$b_put_1__SEL_2 or - WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_rereq: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - default: ram_word64_set$DIB = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign ram_word64_set$WEA = 1'd1 ; - assign ram_word64_set$WEB = 1'd0 ; - assign ram_word64_set$ENA = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d311 ; - assign ram_word64_set$ENB = - EN_req && - req_f3_BITS_1_TO_0_94_EQ_0b0_95_OR_req_f3_BITS_ETC___d924 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = { 32'd0, rg_addr } ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_1_EL_ETC___d273 = - (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d804 = - (rg_addr[2:0] == 3'h0) ? ld_val__h24169 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259 = - (rg_addr[2:0] == 3'h0) ? word64__h5280 : 64'd0 ; - assign IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 = - (rg_f3 == 3'b010) ? - { {32{rg_st_amo_val_BITS_31_TO_0__q31[31]}}, - rg_st_amo_val_BITS_31_TO_0__q31 } : - rg_st_amo_val ; - assign IF_rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d112 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd8 : - IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d111 ; - assign IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d111 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - 4'd11 : - ((!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) ? - 4'd8 : - 4'd11) ; - assign IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d468 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - mem_req_wr_data_wdata__h16837 : - mem_req_wr_data_wdata__h20334 ; - assign IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d80 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d69 : - !ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read ; - assign NOT_cfg_verbosity_read__0_ULE_1_1___d12 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read__0_ULE_2_57___d558 = cfg_verbosity > 4'd2 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d300 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - rg_op != 2'd1 && ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d311 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d309 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d445 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d443 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d481 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 && - rg_addr_0_EQ_rg_lrsc_pa_9___d119 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d493 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d521 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d519 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d522 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d528 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d526 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d534 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d532 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d536 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d308 ; - assign NOT_ram_state_and_ctag_cset_b_read__0_BIT_22_1_ETC___d121 = - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - rg_addr_0_EQ_rg_lrsc_pa_9___d119 ; - assign NOT_req_f3_BITS_1_TO_0_94_EQ_0b0_95_96_AND_NOT_ETC___d915 = - req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && - (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && - (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; - assign NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d107 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) ; - assign NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d446 || - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d308) ; - assign NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d496 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d494 ; - assign NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d502 ; - assign NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d509 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d507 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d130 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - rg_addr_0_EQ_rg_lrsc_pa_9___d119 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d308 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d442 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d519 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d522 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d526 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d532 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - rg_addr_0_EQ_rg_lrsc_pa_9___d119 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d306 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d440 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d494 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d498 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d502 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d507 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign _theResult___snd_fst__h16845 = rg_st_amo_val << shift_bits__h20135 ; - assign _theResult___snd_fst__h20342 = - new_st_val__h17353 << shift_bits__h20135 ; - assign _theResult___snd_fst__h25778 = rg_st_amo_val << shift_bits__h27075 ; - assign _theResult___snd_fst__h27282 = st_val__h27019 << shift_bits__h27075 ; - assign access_exc_code__h2925 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd5 : - 4'd7) : - 4'd1 ; - assign b__h20937 = - ctr_wr_rsps_pending_crg$EN_port0__write ? - ctr_wr_rsps_pending_crg$port0__write_1 : - ctr_wr_rsps_pending_crg ; - assign cline_addr__h21035 = { rg_pa[31:5], 5'd0 } ; - assign cline_fabric_addr__h21036 = { 32'd0, cline_addr__h21035 } ; - assign dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d82 = - dmem_not_imem && !soc_map$m_is_mem_addr || rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d80 ; - assign ld_val4169_BITS_15_TO_0__q36 = ld_val__h24169[15:0] ; - assign ld_val4169_BITS_15_TO_8__q38 = ld_val__h24169[15:8] ; - assign ld_val4169_BITS_23_TO_16__q39 = ld_val__h24169[23:16] ; - assign ld_val4169_BITS_31_TO_0__q37 = ld_val__h24169[31:0] ; - assign ld_val4169_BITS_31_TO_16__q40 = ld_val__h24169[31:16] ; - assign ld_val4169_BITS_31_TO_24__q41 = ld_val__h24169[31:24] ; - assign ld_val4169_BITS_39_TO_32__q42 = ld_val__h24169[39:32] ; - assign ld_val4169_BITS_47_TO_32__q43 = ld_val__h24169[47:32] ; - assign ld_val4169_BITS_47_TO_40__q45 = ld_val__h24169[47:40] ; - assign ld_val4169_BITS_55_TO_48__q46 = ld_val__h24169[55:48] ; - assign ld_val4169_BITS_63_TO_32__q44 = ld_val__h24169[63:32] ; - assign ld_val4169_BITS_63_TO_48__q47 = ld_val__h24169[63:48] ; - assign ld_val4169_BITS_63_TO_56__q48 = ld_val__h24169[63:56] ; - assign ld_val4169_BITS_7_TO_0__q35 = ld_val__h24169[7:0] ; - assign lrsc_result__h13133 = - !rg_lrsc_valid || !rg_lrsc_pa_9_EQ_rg_addr_0___d60 ; - assign master_xactor_crg_rd_data_full_port1__read__54_ETC___d727 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; - assign master_xactor_rg_rd_data_BITS_10_TO_3__q1 = - master_xactor_rg_rd_data[10:3] ; - assign master_xactor_rg_rd_data_BITS_18_TO_11__q4 = - master_xactor_rg_rd_data[18:11] ; - assign master_xactor_rg_rd_data_BITS_18_TO_3__q2 = - master_xactor_rg_rd_data[18:3] ; - assign master_xactor_rg_rd_data_BITS_26_TO_19__q5 = - master_xactor_rg_rd_data[26:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_19__q6 = - master_xactor_rg_rd_data[34:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_27__q7 = - master_xactor_rg_rd_data[34:27] ; - assign master_xactor_rg_rd_data_BITS_34_TO_3__q3 = - master_xactor_rg_rd_data[34:3] ; - assign master_xactor_rg_rd_data_BITS_42_TO_35__q8 = - master_xactor_rg_rd_data[42:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_35__q9 = - master_xactor_rg_rd_data[50:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_43__q11 = - master_xactor_rg_rd_data[50:43] ; - assign master_xactor_rg_rd_data_BITS_58_TO_51__q12 = - master_xactor_rg_rd_data[58:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_35__q10 = - master_xactor_rg_rd_data[66:35] ; - assign master_xactor_rg_rd_data_BITS_66_TO_51__q13 = - master_xactor_rg_rd_data[66:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_59__q14 = - master_xactor_rg_rd_data[66:59] ; - assign mem_req_wr_addr_awaddr__h20129 = { 32'd0, rg_addr } ; - assign mem_req_wr_addr_awaddr__h27069 = { 32'd0, rg_pa } ; - assign new_st_val__h17353 = - (rg_f3 == 3'b010) ? - new_st_val__h17635 : - _theResult_____2__h17631 ; - assign new_st_val__h17635 = { 32'd0, _theResult_____2__h17631[31:0] } ; - assign new_st_val__h17726 = - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 + - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ; - assign new_st_val__h18706 = w1__h17623 ^ w2__h27293 ; - assign new_st_val__h18710 = w1__h17623 & w2__h27293 ; - assign new_st_val__h18714 = w1__h17623 | w2__h27293 ; - assign new_st_val__h18718 = - (w1__h17623 < w2__h27293) ? w1__h17623 : w2__h27293 ; - assign new_st_val__h18723 = - (w1__h17623 <= w2__h27293) ? w2__h27293 : w1__h17623 ; - assign new_st_val__h18729 = - ((IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 ^ - 64'h8000000000000000) < - (IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ^ - 64'h8000000000000000)) ? - w1__h17623 : - w2__h27293 ; - assign new_st_val__h18734 = - ((IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 ^ - 64'h8000000000000000) <= - (IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ^ - 64'h8000000000000000)) ? - w2__h27293 : - w1__h17623 ; - assign new_st_val__h27303 = { 32'd0, _theResult_____2__h27299[31:0] } ; - assign new_st_val__h27394 = - new_ld_val__h27007 + - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ; - assign new_st_val__h29254 = w1__h27291 ^ w2__h27293 ; - assign new_st_val__h29258 = w1__h27291 & w2__h27293 ; - assign new_st_val__h29262 = w1__h27291 | w2__h27293 ; - assign new_st_val__h29266 = - (w1__h27291 < w2__h27293) ? w1__h27291 : w2__h27293 ; - assign new_st_val__h29271 = - (w1__h27291 <= w2__h27293) ? w2__h27293 : w1__h27291 ; - assign new_st_val__h29277 = - ((new_ld_val__h27007 ^ 64'h8000000000000000) < - (IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ^ - 64'h8000000000000000)) ? - w1__h27291 : - w2__h27293 ; - assign new_st_val__h29282 = - ((new_ld_val__h27007 ^ 64'h8000000000000000) <= - (IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ^ - 64'h8000000000000000)) ? - w2__h27293 : - w1__h27291 ; - assign new_value462_BITS_31_TO_0__q30 = new_value__h5462[31:0] ; - assign pa_ctag__h5138 = { 2'd0, rg_addr[31:12] } ; - assign ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 = - ram_state_and_ctag_cset$DOB[21:0] == pa_ctag__h5138 ; - assign ram_state_and_ctag_cset_b_read__0_BIT_22_1_AND_ETC___d122 = - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - NOT_ram_state_and_ctag_cset_b_read__0_BIT_22_1_ETC___d121 ; - assign req_f3_BITS_1_TO_0_94_EQ_0b0_95_OR_req_f3_BITS_ETC___d924 = - req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || - req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || - req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; - assign result__h11873 = - { {56{word64280_BITS_15_TO_8__q18[7]}}, - word64280_BITS_15_TO_8__q18 } ; - assign result__h11901 = - { {56{word64280_BITS_23_TO_16__q19[7]}}, - word64280_BITS_23_TO_16__q19 } ; - assign result__h11929 = - { {56{word64280_BITS_31_TO_24__q21[7]}}, - word64280_BITS_31_TO_24__q21 } ; - assign result__h11957 = - { {56{word64280_BITS_39_TO_32__q22[7]}}, - word64280_BITS_39_TO_32__q22 } ; - assign result__h11985 = - { {56{word64280_BITS_47_TO_40__q25[7]}}, - word64280_BITS_47_TO_40__q25 } ; - assign result__h12013 = - { {56{word64280_BITS_55_TO_48__q26[7]}}, - word64280_BITS_55_TO_48__q26 } ; - assign result__h12041 = - { {56{word64280_BITS_63_TO_56__q28[7]}}, - word64280_BITS_63_TO_56__q28 } ; - assign result__h12086 = { 56'd0, word64__h5280[7:0] } ; - assign result__h12114 = { 56'd0, word64__h5280[15:8] } ; - assign result__h12142 = { 56'd0, word64__h5280[23:16] } ; - assign result__h12170 = { 56'd0, word64__h5280[31:24] } ; - assign result__h12198 = { 56'd0, word64__h5280[39:32] } ; - assign result__h12226 = { 56'd0, word64__h5280[47:40] } ; - assign result__h12254 = { 56'd0, word64__h5280[55:48] } ; - assign result__h12282 = { 56'd0, word64__h5280[63:56] } ; - assign result__h12327 = - { {48{word64280_BITS_15_TO_0__q16[15]}}, - word64280_BITS_15_TO_0__q16 } ; - assign result__h12355 = - { {48{word64280_BITS_31_TO_16__q20[15]}}, - word64280_BITS_31_TO_16__q20 } ; - assign result__h12383 = - { {48{word64280_BITS_47_TO_32__q23[15]}}, - word64280_BITS_47_TO_32__q23 } ; - assign result__h12411 = - { {48{word64280_BITS_63_TO_48__q27[15]}}, - word64280_BITS_63_TO_48__q27 } ; - assign result__h12452 = { 48'd0, word64__h5280[15:0] } ; - assign result__h12480 = { 48'd0, word64__h5280[31:16] } ; - assign result__h12508 = { 48'd0, word64__h5280[47:32] } ; - assign result__h12536 = { 48'd0, word64__h5280[63:48] } ; - assign result__h12577 = - { {32{word64280_BITS_31_TO_0__q17[31]}}, - word64280_BITS_31_TO_0__q17 } ; - assign result__h12605 = - { {32{word64280_BITS_63_TO_32__q24[31]}}, - word64280_BITS_63_TO_32__q24 } ; - assign result__h12644 = { 32'd0, word64__h5280[31:0] } ; - assign result__h12672 = { 32'd0, word64__h5280[63:32] } ; - assign result__h24229 = - { {56{master_xactor_rg_rd_data_BITS_10_TO_3__q1[7]}}, - master_xactor_rg_rd_data_BITS_10_TO_3__q1 } ; - assign result__h24259 = - { {56{master_xactor_rg_rd_data_BITS_18_TO_11__q4[7]}}, - master_xactor_rg_rd_data_BITS_18_TO_11__q4 } ; - assign result__h24286 = - { {56{master_xactor_rg_rd_data_BITS_26_TO_19__q5[7]}}, - master_xactor_rg_rd_data_BITS_26_TO_19__q5 } ; - assign result__h24313 = - { {56{master_xactor_rg_rd_data_BITS_34_TO_27__q7[7]}}, - master_xactor_rg_rd_data_BITS_34_TO_27__q7 } ; - assign result__h24340 = - { {56{master_xactor_rg_rd_data_BITS_42_TO_35__q8[7]}}, - master_xactor_rg_rd_data_BITS_42_TO_35__q8 } ; - assign result__h24367 = - { {56{master_xactor_rg_rd_data_BITS_50_TO_43__q11[7]}}, - master_xactor_rg_rd_data_BITS_50_TO_43__q11 } ; - assign result__h24394 = - { {56{master_xactor_rg_rd_data_BITS_58_TO_51__q12[7]}}, - master_xactor_rg_rd_data_BITS_58_TO_51__q12 } ; - assign result__h24421 = - { {56{master_xactor_rg_rd_data_BITS_66_TO_59__q14[7]}}, - master_xactor_rg_rd_data_BITS_66_TO_59__q14 } ; - assign result__h24465 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h24492 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h24519 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h24546 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h24573 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h24600 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h24627 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h24654 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h24698 = - { {48{master_xactor_rg_rd_data_BITS_18_TO_3__q2[15]}}, - master_xactor_rg_rd_data_BITS_18_TO_3__q2 } ; - assign result__h24725 = - { {48{master_xactor_rg_rd_data_BITS_34_TO_19__q6[15]}}, - master_xactor_rg_rd_data_BITS_34_TO_19__q6 } ; - assign result__h24752 = - { {48{master_xactor_rg_rd_data_BITS_50_TO_35__q9[15]}}, - master_xactor_rg_rd_data_BITS_50_TO_35__q9 } ; - assign result__h24779 = - { {48{master_xactor_rg_rd_data_BITS_66_TO_51__q13[15]}}, - master_xactor_rg_rd_data_BITS_66_TO_51__q13 } ; - assign result__h24819 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h24846 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h24873 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h24900 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h24940 = - { {32{master_xactor_rg_rd_data_BITS_34_TO_3__q3[31]}}, - master_xactor_rg_rd_data_BITS_34_TO_3__q3 } ; - assign result__h24967 = - { {32{master_xactor_rg_rd_data_BITS_66_TO_35__q10[31]}}, - master_xactor_rg_rd_data_BITS_66_TO_35__q10 } ; - assign result__h25005 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h25032 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; - assign result__h27482 = - { {56{ld_val4169_BITS_7_TO_0__q35[7]}}, - ld_val4169_BITS_7_TO_0__q35 } ; - assign result__h28390 = - { {56{ld_val4169_BITS_15_TO_8__q38[7]}}, - ld_val4169_BITS_15_TO_8__q38 } ; - assign result__h28418 = - { {56{ld_val4169_BITS_23_TO_16__q39[7]}}, - ld_val4169_BITS_23_TO_16__q39 } ; - assign result__h28446 = - { {56{ld_val4169_BITS_31_TO_24__q41[7]}}, - ld_val4169_BITS_31_TO_24__q41 } ; - assign result__h28474 = - { {56{ld_val4169_BITS_39_TO_32__q42[7]}}, - ld_val4169_BITS_39_TO_32__q42 } ; - assign result__h28502 = - { {56{ld_val4169_BITS_47_TO_40__q45[7]}}, - ld_val4169_BITS_47_TO_40__q45 } ; - assign result__h28530 = - { {56{ld_val4169_BITS_55_TO_48__q46[7]}}, - ld_val4169_BITS_55_TO_48__q46 } ; - assign result__h28558 = - { {56{ld_val4169_BITS_63_TO_56__q48[7]}}, - ld_val4169_BITS_63_TO_56__q48 } ; - assign result__h28603 = { 56'd0, ld_val__h24169[7:0] } ; - assign result__h28631 = { 56'd0, ld_val__h24169[15:8] } ; - assign result__h28659 = { 56'd0, ld_val__h24169[23:16] } ; - assign result__h28687 = { 56'd0, ld_val__h24169[31:24] } ; - assign result__h28715 = { 56'd0, ld_val__h24169[39:32] } ; - assign result__h28743 = { 56'd0, ld_val__h24169[47:40] } ; - assign result__h28771 = { 56'd0, ld_val__h24169[55:48] } ; - assign result__h28799 = { 56'd0, ld_val__h24169[63:56] } ; - assign result__h28844 = - { {48{ld_val4169_BITS_15_TO_0__q36[15]}}, - ld_val4169_BITS_15_TO_0__q36 } ; - assign result__h28872 = - { {48{ld_val4169_BITS_31_TO_16__q40[15]}}, - ld_val4169_BITS_31_TO_16__q40 } ; - assign result__h28900 = - { {48{ld_val4169_BITS_47_TO_32__q43[15]}}, - ld_val4169_BITS_47_TO_32__q43 } ; - assign result__h28928 = - { {48{ld_val4169_BITS_63_TO_48__q47[15]}}, - ld_val4169_BITS_63_TO_48__q47 } ; - assign result__h28969 = { 48'd0, ld_val__h24169[15:0] } ; - assign result__h28997 = { 48'd0, ld_val__h24169[31:16] } ; - assign result__h29025 = { 48'd0, ld_val__h24169[47:32] } ; - assign result__h29053 = { 48'd0, ld_val__h24169[63:48] } ; - assign result__h29094 = - { {32{ld_val4169_BITS_31_TO_0__q37[31]}}, - ld_val4169_BITS_31_TO_0__q37 } ; - assign result__h29122 = - { {32{ld_val4169_BITS_63_TO_32__q44[31]}}, - ld_val4169_BITS_63_TO_32__q44 } ; - assign result__h29161 = { 32'd0, ld_val__h24169[31:0] } ; - assign result__h29189 = { 32'd0, ld_val__h24169[63:32] } ; - assign result__h5517 = - { {56{word64280_BITS_7_TO_0__q15[7]}}, - word64280_BITS_7_TO_0__q15 } ; - assign rg_addr_0_EQ_rg_lrsc_pa_9___d119 = rg_addr == rg_lrsc_pa ; - assign rg_amo_funct7_8_BITS_6_TO_2_9_EQ_0b10_0_AND_NO_ETC___d294 = - rg_amo_funct7[6:2] == 5'b00010 && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) && - rg_addr_0_EQ_rg_lrsc_pa_9___d119 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_lrsc_pa_9_EQ_rg_addr_0___d60 = rg_lrsc_pa == rg_addr ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d102 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d133 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset_b_read__0_BIT_22_1_AND_ETC___d122 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d131 ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d135 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d138 = - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d135 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13133 ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d277 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d290 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d131 = - rg_op == 2'd1 && rg_addr_0_EQ_rg_lrsc_pa_9___d119 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d130 ; - assign rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d309 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d306 || - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d308 ; - assign rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d443 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d440 || - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d442 ; - assign rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d446 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) ; - assign rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d515 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13133 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d69 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13133 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read ; - assign rg_st_amo_val_BITS_31_TO_0__q31 = rg_st_amo_val[31:0] ; - assign rg_state_EQ_12_93_AND_rg_op_5_EQ_0_6_OR_rg_op__ETC___d595 = - rg_state == 4'd12 && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - b__h20937 == 4'd0 ; - assign rg_state_EQ_3_3_AND_NOT_rg_op_5_EQ_0_6_4_AND_N_ETC___d92 = - rg_state == 4'd3 && - (rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - crg_sb_to_load_delay$port0__write_1 == 11'd0) ; - assign shift_bits__h20135 = { rg_addr[2:0], 3'b0 } ; - assign shift_bits__h27075 = { rg_pa[2:0], 3'b0 } ; - assign st_val__h27019 = - (rg_f3 == 3'b010) ? - new_st_val__h27303 : - _theResult_____2__h27299 ; - assign strobe64__h20268 = 8'b00000001 << rg_addr[2:0] ; - assign strobe64__h20270 = 8'b00000011 << rg_addr[2:0] ; - assign strobe64__h20272 = 8'b00001111 << rg_addr[2:0] ; - assign strobe64__h27208 = 8'b00000001 << rg_pa[2:0] ; - assign strobe64__h27210 = 8'b00000011 << rg_pa[2:0] ; - assign strobe64__h27212 = 8'b00001111 << rg_pa[2:0] ; - assign w17287_BITS_31_TO_0__q50 = w1__h27287[31:0] ; - assign w1___1__h17694 = { 32'd0, new_value__h5462[31:0] } ; - assign w1___1__h27362 = { 32'd0, w1__h27287[31:0] } ; - assign w2___1__h27363 = { 32'd0, rg_st_amo_val[31:0] } ; - assign w2__h27293 = (rg_f3 == 3'b010) ? w2___1__h27363 : rg_st_amo_val ; - assign word64280_BITS_15_TO_0__q16 = word64__h5280[15:0] ; - assign word64280_BITS_15_TO_8__q18 = word64__h5280[15:8] ; - assign word64280_BITS_23_TO_16__q19 = word64__h5280[23:16] ; - assign word64280_BITS_31_TO_0__q17 = word64__h5280[31:0] ; - assign word64280_BITS_31_TO_16__q20 = word64__h5280[31:16] ; - assign word64280_BITS_31_TO_24__q21 = word64__h5280[31:24] ; - assign word64280_BITS_39_TO_32__q22 = word64__h5280[39:32] ; - assign word64280_BITS_47_TO_32__q23 = word64__h5280[47:32] ; - assign word64280_BITS_47_TO_40__q25 = word64__h5280[47:40] ; - assign word64280_BITS_55_TO_48__q26 = word64__h5280[55:48] ; - assign word64280_BITS_63_TO_32__q24 = word64__h5280[63:32] ; - assign word64280_BITS_63_TO_48__q27 = word64__h5280[63:48] ; - assign word64280_BITS_63_TO_56__q28 = word64__h5280[63:56] ; - assign word64280_BITS_7_TO_0__q15 = word64__h5280[7:0] ; - assign word64__h5280 = ram_word64_set$DOB & y__h5553 ; - assign x__h13143 = { 63'd0, lrsc_result__h13133 } ; - assign y__h5553 = - {64{ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76}} ; - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h26592 = 3'b0; - 2'b01: value__h26592 = 3'b001; - 2'b10: value__h26592 = 3'b010; - 2'd3: value__h26592 = 3'b011; - endcase - end - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h29618 = 3'b0; - 2'b01: value__h29618 = 3'b001; - 2'b10: value__h29618 = 3'b010; - 2'b11: value__h29618 = 3'b011; - endcase - end - always@(rg_f3 or strobe64__h27208 or strobe64__h27210 or strobe64__h27212) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h27275 = strobe64__h27208; - 2'b01: mem_req_wr_data_wstrb__h27275 = strobe64__h27210; - 2'b10: mem_req_wr_data_wstrb__h27275 = strobe64__h27212; - 2'b11: mem_req_wr_data_wstrb__h27275 = 8'b11111111; - endcase - end - always@(rg_f3 or strobe64__h20268 or strobe64__h20270 or strobe64__h20272) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h20335 = strobe64__h20268; - 2'b01: mem_req_wr_data_wstrb__h20335 = strobe64__h20270; - 2'b10: mem_req_wr_data_wstrb__h20335 = strobe64__h20272; - 2'b11: mem_req_wr_data_wstrb__h20335 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h16845) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h16837 = _theResult___snd_fst__h16845; - 2'd3: mem_req_wr_data_wdata__h16837 = rg_st_amo_val; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h25778) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h25770 = _theResult___snd_fst__h25778; - 2'd3: mem_req_wr_data_wdata__h25770 = rg_st_amo_val; - endcase - end - always@(rg_addr or - result__h12086 or - result__h12114 or - result__h12142 or - result__h12170 or - result__h12198 or - result__h12226 or result__h12254 or result__h12282) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12086; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12114; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12142; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12170; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12198; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12226; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12254; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12282; - endcase - end - always@(rg_addr or - result__h5517 or - result__h11873 or - result__h11901 or - result__h11929 or - result__h11957 or - result__h11985 or result__h12013 or result__h12041) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h5517; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h11873; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h11901; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h11929; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h11957; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h11985; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h12013; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h12041; - endcase - end - always@(rg_addr or - result__h12327 or - result__h12355 or result__h12383 or result__h12411) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 = - result__h12327; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 = - result__h12355; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 = - result__h12383; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 = - result__h12411; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 = - 64'd0; - endcase - end - always@(rg_addr or - result__h12452 or - result__h12480 or result__h12508 or result__h12536) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 = - result__h12452; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 = - result__h12480; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 = - result__h12508; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 = - result__h12536; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 = - 64'd0; - endcase - end - always@(rg_addr or result__h12644 or result__h12672) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257 = - result__h12644; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257 = - result__h12672; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257 = - 64'd0; - endcase - end - always@(rg_addr or result__h12577 or result__h12605) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29 = - result__h12577; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29 = - result__h12605; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 or - CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257) - begin - case (rg_f3) - 3'b0: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206; - 3'b001: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236; - 3'b010: - new_value__h5462 = - CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29; - 3'b011: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259; - 3'b100: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223; - 3'b101: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245; - 3'b110: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257; - 3'd7: new_value__h5462 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 or - w1___1__h17694 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257) - begin - case (rg_f3) - 3'b0: - w1__h17623 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206; - 3'b001: - w1__h17623 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236; - 3'b010: w1__h17623 = w1___1__h17694; - 3'b011: - w1__h17623 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259; - 3'b100: - w1__h17623 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223; - 3'b101: - w1__h17623 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245; - 3'b110: - w1__h17623 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257; - 3'd7: w1__h17623 = 64'd0; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 = - { ram_word64_set$DOB[63:16], rg_st_amo_val[15:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 = - { rg_st_amo_val[15:0], ram_word64_set$DOB[47:0] }; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:8], rg_st_amo_val[7:0] }; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:16], - rg_st_amo_val[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:24], - rg_st_amo_val[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:40], - rg_st_amo_val[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:56], - rg_st_amo_val[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { rg_st_amo_val[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 or - new_value462_BITS_31_TO_0__q30 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206; - 3'b001: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236; - 3'b010: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - { {32{new_value462_BITS_31_TO_0__q30[31]}}, - new_value462_BITS_31_TO_0__q30 }; - 3'b011: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259; - 3'b100: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223; - 3'b101: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245; - 3'b110: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257; - 3'd7: IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h18734 or - new_st_val__h17726 or - w2__h27293 or - new_st_val__h18706 or - new_st_val__h18714 or - new_st_val__h18710 or - new_st_val__h18729 or new_st_val__h18718 or new_st_val__h18723) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h17631 = new_st_val__h17726; - 5'b00001: _theResult_____2__h17631 = w2__h27293; - 5'b00100: _theResult_____2__h17631 = new_st_val__h18706; - 5'b01000: _theResult_____2__h17631 = new_st_val__h18714; - 5'b01100: _theResult_____2__h17631 = new_st_val__h18710; - 5'b10000: _theResult_____2__h17631 = new_st_val__h18729; - 5'b11000: _theResult_____2__h17631 = new_st_val__h18718; - 5'b11100: _theResult_____2__h17631 = new_st_val__h18723; - default: _theResult_____2__h17631 = new_st_val__h18734; - endcase - end - always@(rg_f3 or new_st_val__h17353 or _theResult___snd_fst__h20342) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h20334 = _theResult___snd_fst__h20342; - 2'd3: mem_req_wr_data_wdata__h20334 = new_st_val__h17353; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17353) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 = - { ram_word64_set$DOB[63:16], new_st_val__h17353[15:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 = - { ram_word64_set$DOB[63:32], - new_st_val__h17353[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 = - { ram_word64_set$DOB[63:48], - new_st_val__h17353[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 = - { new_st_val__h17353[15:0], ram_word64_set$DOB[47:0] }; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17353) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:8], new_st_val__h17353[7:0] }; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:16], - new_st_val__h17353[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:24], - new_st_val__h17353[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:32], - new_st_val__h17353[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:40], - new_st_val__h17353[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:48], - new_st_val__h17353[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:56], - new_st_val__h17353[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { new_st_val__h17353[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - { ram_word64_set$DOB[63:32], rg_st_amo_val[31:0] }; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - { rg_st_amo_val[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 or - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 or - rg_st_amo_val) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344; - 3'b001: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353; - 3'b010: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 = - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32; - 3'b011: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 = - rg_st_amo_val; - default: IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or - result__h24819 or - result__h24846 or result__h24873 or result__h24900) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d670 = - result__h24819; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d670 = - result__h24846; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d670 = - result__h24873; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d670 = - result__h24900; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d670 = - 64'd0; - endcase - end - always@(rg_addr or - result__h24465 or - result__h24492 or - result__h24519 or - result__h24546 or - result__h24573 or - result__h24600 or result__h24627 or result__h24654) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650 = - result__h24465; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650 = - result__h24492; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650 = - result__h24519; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650 = - result__h24546; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650 = - result__h24573; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650 = - result__h24600; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650 = - result__h24627; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650 = - result__h24654; - endcase - end - always@(rg_addr or - result__h24698 or - result__h24725 or result__h24752 or result__h24779) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d662 = - result__h24698; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d662 = - result__h24725; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d662 = - result__h24752; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d662 = - result__h24779; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d662 = - 64'd0; - endcase - end - always@(rg_addr or - result__h24229 or - result__h24259 or - result__h24286 or - result__h24313 or - result__h24340 or - result__h24367 or result__h24394 or result__h24421) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634 = - result__h24229; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634 = - result__h24259; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634 = - result__h24286; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634 = - result__h24313; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634 = - result__h24340; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634 = - result__h24367; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634 = - result__h24394; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634 = - result__h24421; - endcase - end - always@(rg_addr or result__h24940 or result__h24967) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4940_0x4_re_ETC__q33 = - result__h24940; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4940_0x4_re_ETC__q33 = - result__h24967; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4940_0x4_re_ETC__q33 = - 64'd0; - endcase - end - always@(rg_addr or result__h25005 or result__h25032) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result5005_0x4_re_ETC__q34 = - result__h25005; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result5005_0x4_re_ETC__q34 = - result__h25032; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result5005_0x4_re_ETC__q34 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d662 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4940_0x4_re_ETC__q33 or - rg_addr or - master_xactor_rg_rd_data or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d670 or - CASE_rg_addr_BITS_2_TO_0_0x0_result5005_0x4_re_ETC__q34) - begin - case (rg_f3) - 3'b0: - ld_val__h24169 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d634; - 3'b001: - ld_val__h24169 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d662; - 3'b010: - ld_val__h24169 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4940_0x4_re_ETC__q33; - 3'b011: - ld_val__h24169 = - (rg_addr[2:0] == 3'h0) ? master_xactor_rg_rd_data[66:3] : 64'd0; - 3'b100: - ld_val__h24169 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d650; - 3'b101: - ld_val__h24169 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d670; - 3'b110: - ld_val__h24169 = - CASE_rg_addr_BITS_2_TO_0_0x0_result5005_0x4_re_ETC__q34; - 3'd7: ld_val__h24169 = 64'd0; - endcase - end - always@(rg_addr or result__h29161 or result__h29189) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d803 = - result__h29161; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d803 = - result__h29189; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d803 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28969 or - result__h28997 or result__h29025 or result__h29053) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793 = - result__h28969; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793 = - result__h28997; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793 = - result__h29025; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793 = - result__h29053; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28844 or - result__h28872 or result__h28900 or result__h28928) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785 = - result__h28844; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785 = - result__h28872; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785 = - result__h28900; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785 = - result__h28928; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28603 or - result__h28631 or - result__h28659 or - result__h28687 or - result__h28715 or - result__h28743 or result__h28771 or result__h28799) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 = - result__h28603; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 = - result__h28631; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 = - result__h28659; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 = - result__h28687; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 = - result__h28715; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 = - result__h28743; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 = - result__h28771; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 = - result__h28799; - endcase - end - always@(rg_addr or - result__h27482 or - result__h28390 or - result__h28418 or - result__h28446 or - result__h28474 or - result__h28502 or result__h28530 or result__h28558) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 = - result__h27482; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 = - result__h28390; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 = - result__h28418; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 = - result__h28446; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 = - result__h28474; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 = - result__h28502; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 = - result__h28530; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 = - result__h28558; - endcase - end - always@(rg_addr or result__h29094 or result__h29122) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result9094_0x4_re_ETC__q49 = - result__h29094; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result9094_0x4_re_ETC__q49 = - result__h29122; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result9094_0x4_re_ETC__q49 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785 or - CASE_rg_addr_BITS_2_TO_0_0x0_result9094_0x4_re_ETC__q49 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d804 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d803) - begin - case (rg_f3) - 3'b0: - w1__h27287 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757; - 3'b001: - w1__h27287 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785; - 3'b010: - w1__h27287 = - CASE_rg_addr_BITS_2_TO_0_0x0_result9094_0x4_re_ETC__q49; - 3'b011: - w1__h27287 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d804; - 3'b100: - w1__h27287 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773; - 3'b101: - w1__h27287 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793; - 3'b110: - w1__h27287 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d803; - 3'd7: w1__h27287 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785 or - w1___1__h27362 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d804 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d803) - begin - case (rg_f3) - 3'b0: - w1__h27291 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757; - 3'b001: - w1__h27291 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785; - 3'b010: w1__h27291 = w1___1__h27362; - 3'b011: - w1__h27291 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d804; - 3'b100: - w1__h27291 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773; - 3'b101: - w1__h27291 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793; - 3'b110: - w1__h27291 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d803; - 3'd7: w1__h27291 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785 or - w17287_BITS_31_TO_0__q50 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d804 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d803) - begin - case (rg_f3) - 3'b0: - new_ld_val__h27007 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d757; - 3'b001: - new_ld_val__h27007 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d785; - 3'b010: - new_ld_val__h27007 = - { {32{w17287_BITS_31_TO_0__q50[31]}}, - w17287_BITS_31_TO_0__q50 }; - 3'b011: - new_ld_val__h27007 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d804; - 3'b100: - new_ld_val__h27007 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d773; - 3'b101: - new_ld_val__h27007 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d793; - 3'b110: - new_ld_val__h27007 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d803; - 3'd7: new_ld_val__h27007 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h29282 or - new_st_val__h27394 or - w2__h27293 or - new_st_val__h29254 or - new_st_val__h29262 or - new_st_val__h29258 or - new_st_val__h29277 or new_st_val__h29266 or new_st_val__h29271) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h27299 = new_st_val__h27394; - 5'b00001: _theResult_____2__h27299 = w2__h27293; - 5'b00100: _theResult_____2__h27299 = new_st_val__h29254; - 5'b01000: _theResult_____2__h27299 = new_st_val__h29262; - 5'b01100: _theResult_____2__h27299 = new_st_val__h29258; - 5'b10000: _theResult_____2__h27299 = new_st_val__h29277; - 5'b11000: _theResult_____2__h27299 = new_st_val__h29266; - 5'b11100: _theResult_____2__h27299 = new_st_val__h29271; - default: _theResult_____2__h27299 = new_st_val__h29282; - endcase - end - always@(rg_f3 or st_val__h27019 or _theResult___snd_fst__h27282) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h27274 = _theResult___snd_fst__h27282; - 2'd3: mem_req_wr_data_wdata__h27274 = st_val__h27019; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17353) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - { ram_word64_set$DOB[63:32], new_st_val__h17353[31:0] }; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - { new_st_val__h17353[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 or - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 or - new_st_val__h17353) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418; - 3'b001: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427; - 3'b010: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 = - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51; - 3'b011: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 = - new_st_val__h17353; - default: IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_1_EL_ETC___d273) - begin - case (rg_f3) - 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: - new_value__h15491 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_1_EL_ETC___d273; - 3'd7: new_value__h15491 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 7'd0; - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_sb_to_load_delay$EN) - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY - crg_sb_to_load_delay$D_IN; - if (ctr_wr_rsps_pending_crg$EN) - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY - ctr_wr_rsps_pending_crg$D_IN; - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_cset_in_cache$EN) - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN; - if (rg_lower_word32_full$EN) - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY - rg_lower_word32_full$D_IN; - if (rg_lrsc_valid$EN) - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; - if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN; - if (rg_amo_funct7$EN) - rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN; - if (rg_error_during_refill$EN) - rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY - rg_error_during_refill$D_IN; - if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN; - if (rg_lower_word32$EN) - rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN; - if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN; - if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN; - if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN; - if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN; - if (rg_st_amo_val$EN) - rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN; - if (rg_word64_set_in_cache$EN) - rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY - rg_word64_set_in_cache$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_sb_to_load_delay = 11'h2AA; - ctr_wr_rsps_pending_crg = 4'hA; - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; - rg_addr = 32'hAAAAAAAA; - rg_amo_funct7 = 7'h2A; - rg_cset_in_cache = 7'h2A; - rg_error_during_refill = 1'h0; - rg_exc_code = 4'hA; - rg_f3 = 3'h2; - rg_ld_val = 64'hAAAAAAAAAAAAAAAA; - rg_lower_word32 = 32'hAAAAAAAA; - rg_lower_word32_full = 1'h0; - rg_lrsc_pa = 32'hAAAAAAAA; - rg_lrsc_valid = 1'h0; - rg_op = 2'h2; - rg_pa = 32'hAAAAAAAA; - rg_pte_pa = 32'hAAAAAAAA; - rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - rg_word64_set_in_cache = 9'h0AA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - begin - v__h3732 = $stime; - #0; - end - v__h3726 = v__h3732 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h3726, - "D_MMU_Cache", - $signed(32'd128), - $signed(32'd1)); - else - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h3726, - "I_MMU_Cache", - $signed(32'd128), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - f_reset_reqs$D_OUT) - begin - v__h3833 = $stime; - #0; - end - v__h3827 = v__h3833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: Flushed", v__h3827, "D_MMU_Cache"); - else - $display("%0d: %s.rl_reset: Flushed", v__h3827, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_rereq && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - rg_addr[11:5], - rg_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25372 = $stime; - #0; - end - v__h25366 = v__h25372 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25366, - "D_MMU_Cache", - rg_addr, - rg_ld_val); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25366, - "I_MMU_Cache", - rg_addr, - rg_ld_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26270 = $stime; - #0; - end - v__h26264 = v__h26270 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26264, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26264, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" FAIL due to I/O address."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h3369 = $stime; - #0; - end - v__h3363 = v__h3369 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_start_reset", v__h3363, "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_reset", v__h3363, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h4284 = $stime; - #0; - end - v__h4278 = v__h4284 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h4278, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h4278, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", - pa_ctag__h5138, - rg_addr[11:5], - rg_addr[4:3], - rg_addr[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" CSet 0x%0x: (state, tag):", rg_addr[11:5]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" ("); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - ram_state_and_ctag_cset$DOB[22]) - $write("CTAG_CLEAN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !ram_state_and_ctag_cset$DOB[22]) - $write("CTAG_EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - ram_state_and_ctag_cset$DOB[22]) - $write(", 0x%0x", ram_state_and_ctag_cset$DOB[21:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !ram_state_and_ctag_cset$DOB[22]) - $write(", --"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(")"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" TLB result: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'hA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && dmem_not_imem && - !soc_map$m_is_mem_addr && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => IO_REQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d277) - begin - v__h12756 = $stime; - #0; - end - v__h12750 = v__h12756 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d277) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h12750, - "D_MMU_Cache", - rg_addr, - word64__h5280, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h12750, - "I_MMU_Cache", - rg_addr, - word64__h5280, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO LR: reserving PA 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d277) - $display(" Read-hit: addr 0x%0h word64 0x%0h", - rg_addr, - word64__h5280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d290) - $display(" Read Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7_8_BITS_6_TO_2_9_EQ_0b10_0_AND_NO_ETC___d294) - $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", - rg_lrsc_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d481) - $display(" ST: cancelling LR/SC reservation for PA", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - rg_lrsc_valid && - !rg_lrsc_pa_9_EQ_rg_addr_0___d60 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", - rg_lrsc_pa, - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !rg_lrsc_valid && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO SC: fail due to invalid LR/SC reservation"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d493) - $display(" AMO SC result = %0d", lrsc_result__h13133); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d496) - $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d496) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d496) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d496) - $write(" 0x%0x", - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d496) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d498) - $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d509) - begin - v__h17072 = $stime; - #0; - end - v__h17066 = v__h17072 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d509) - $display("%0d: ERROR: CreditCounter: overflow", v__h17066); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d509) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", mem_req_wr_addr_awaddr__h20129); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", value__h29618); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", mem_req_wr_data_wdata__h16837); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", mem_req_wr_data_wstrb__h20335); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d504) - $display(" => rl_write_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d515) - begin - v__h16400 = $stime; - #0; - end - v__h16394 = v__h16400 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d515) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h16394, - "D_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h16394, - "I_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d515) - $display(" AMO SC: Fail response for addr 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d521) - $display(" AMO Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", - rg_addr, - rg_amo_funct7, - rg_f3, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $display(" PA 0x%0h ", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $display(" Cache word64 0x%0h, load-result 0x%0h", - word64__h5280, - word64__h5280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $display(" 0x%0h op 0x%0h -> 0x%0h", - word64__h5280, - word64__h5280, - new_st_val__h17353); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(" 0x%0x", - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d528) - begin - v__h20538 = $stime; - #0; - end - v__h20532 = v__h20538 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d528) - $display("%0d: ERROR: CreditCounter: overflow", v__h20532); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d528) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", mem_req_wr_addr_awaddr__h20129); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", value__h29618); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", mem_req_wr_data_wdata__h20334); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", mem_req_wr_data_wstrb__h20335); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d524) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d534) - $display(" AMO_op: cancelling LR/SC reservation for PA", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - begin - v__h21833 = $stime; - #0; - end - v__h21827 = v__h21833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h21827, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h21827, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h22074 = $stime; - #0; - end - v__h22068 = v__h22074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h22068, - "D_MMU_Cache", - access_exc_code__h2925); - else - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h22068, - "I_MMU_Cache", - access_exc_code__h2925); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 && - (master_xactor_rg_rd_data[2:1] != 2'b0 || rg_error_during_refill) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => MODULE_EXCEPTION_RSP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !rg_error_during_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => CACHE_REREQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", - rg_word64_set_in_cache, - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write(" 0x%0x", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_57___d558) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h24060 = $stime; - #0; - end - v__h24054 = v__h24060 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h24054, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h24054, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25160 = $stime; - #0; - end - v__h25154 = v__h25160 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25154, - "D_MMU_Cache", - rg_addr, - ld_val__h24169); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25154, - "I_MMU_Cache", - rg_addr, - ld_val__h24169); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25267 = $stime; - #0; - end - v__h25261 = v__h25267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h25261, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h25261, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25452 = $stime; - #0; - end - v__h25446 = v__h25452 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h25446, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h25446, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h25974 = $stime; - #0; - end - v__h25968 = v__h25974 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h25968); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_addr_awaddr__h27069); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h29618); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wdata__h25770); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wstrb__h27275); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26388 = $stime; - #0; - end - v__h26382 = v__h26388 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h26382, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h26382, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_addr_awaddr__h27069); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h26592); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26706 = $stime; - #0; - end - v__h26700 = v__h26706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h26700, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h26700, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26881 = $stime; - #0; - end - v__h26875 = v__h26881 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26875, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26875, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h29494 = $stime; - #0; - end - v__h29488 = v__h29494 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h29488); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_addr_awaddr__h27069); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h29618); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wdata__h27274); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wstrb__h27275); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h29746 = $stime; - #0; - end - v__h29740 = v__h29746 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29740, - "D_MMU_Cache", - rg_addr, - new_ld_val__h27007); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29740, - "I_MMU_Cache", - rg_addr, - new_ld_val__h27007); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26977 = $stime; - #0; - end - v__h26971 = v__h26977 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h26971, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h26971, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h20983 = $stime; - #0; - end - v__h20977 = v__h20983 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_start_cache_refill: ", - v__h20977, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_cache_refill: ", - v__h20977, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", cline_fabric_addr__h21036); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" Victim way %0d; => CACHE_REFILL", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h23686 = $stime; - #0; - end - v__h23680 = v__h23686 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h23680, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h23680, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_addr_awaddr__h27069); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h26592); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h30715 = $stime; - #0; - end - v__h30709 = v__h30715 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $write("%0d: %s.req: op:", v__h30709, "D_MMU_Cache"); - else - $write("%0d: %s.req: op:", v__h30709, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && req_op == 2'd0) - $write("CACHE_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && req_op == 2'd1) - $write("CACHE_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_op != 2'd0 && - req_op != 2'd1) - $write("CACHE_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", - req_f3, - req_addr, - req_st_value); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b0) - $write("U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b01) - $write("S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b11) - $write("M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv != 2'b0 && - req_priv != 2'b01 && - req_priv != 2'b11) - $write("RESERVED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" amo_funct7 = 0x%0h", req_amo_funct7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && - req_f3_BITS_1_TO_0_94_EQ_0b0_95_OR_req_f3_BITS_ETC___d924 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - req_addr[11:5], - req_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h30366 = $stime; - #0; - end - v__h30360 = v__h30366 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h30360, - "D_MMU_Cache", - $unsigned(b__h20937)); - else - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h30360, - "I_MMU_Cache", - $unsigned(b__h20937)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - begin - v__h30327 = $stime; - #0; - end - v__h30321 = v__h30327 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - if (dmem_not_imem) - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h30321, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h30321, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("\n"); - end - // synopsys translate_on -endmodule // mkMMU_Cache - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v deleted file mode 100644 index f673c615..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v +++ /dev/null @@ -1,2169 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// to_raw_mem_response_put I 256 -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_to_raw_mem_response_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Controller(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [63 : 0] slave_rdata; - wire [7 : 0] status; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // inlined wires - reg [353 : 0] f_raw_mem_reqs_rv$port1__write_1; - wire [353 : 0] f_raw_mem_reqs_rv$port1__read, - f_raw_mem_reqs_rv$port2__read, - f_raw_mem_reqs_rv$port3__read; - wire [256 : 0] f_raw_mem_rsps_rv$port1__read, - f_raw_mem_rsps_rv$port1__write_1, - f_raw_mem_rsps_rv$port2__read, - f_raw_mem_rsps_rv$port3__read; - wire [170 : 0] f_reqs_rv$port1__read, - f_reqs_rv$port1__write_1, - f_reqs_rv$port2__read; - wire f_raw_mem_reqs_rv$EN_port1__write, - f_reqs_rv$EN_port0__write, - f_reqs_rv$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register f_raw_mem_reqs_rv - reg [353 : 0] f_raw_mem_reqs_rv; - wire [353 : 0] f_raw_mem_reqs_rv$D_IN; - wire f_raw_mem_reqs_rv$EN; - - // register f_raw_mem_rsps_rv - reg [256 : 0] f_raw_mem_rsps_rv; - wire [256 : 0] f_raw_mem_rsps_rv$D_IN; - wire f_raw_mem_rsps_rv$EN; - - // register f_reqs_rv - reg [170 : 0] f_reqs_rv; - wire [170 : 0] f_reqs_rv$D_IN; - wire f_reqs_rv$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_cached_clean - reg rg_cached_clean; - wire rg_cached_clean$D_IN, rg_cached_clean$EN; - - // register rg_cached_raw_mem_addr - reg [63 : 0] rg_cached_raw_mem_addr; - wire [63 : 0] rg_cached_raw_mem_addr$D_IN; - wire rg_cached_raw_mem_addr$EN; - - // register rg_cached_raw_mem_word - reg [255 : 0] rg_cached_raw_mem_word; - wire [255 : 0] rg_cached_raw_mem_word$D_IN; - wire rg_cached_raw_mem_word$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_status - reg [7 : 0] rg_status; - wire [7 : 0] rg_status$D_IN; - wire rg_status$EN; - - // register rg_tohost_addr - reg [63 : 0] rg_tohost_addr; - wire [63 : 0] rg_tohost_addr$D_IN; - wire rg_tohost_addr$EN; - - // register rg_watch_tohost - reg rg_watch_tohost; - wire rg_watch_tohost$D_IN, rg_watch_tohost$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_external_reset, - CAN_FIRE_RL_rl_invalid_rd_address, - CAN_FIRE_RL_rl_invalid_wr_address, - CAN_FIRE_RL_rl_merge_rd_req, - CAN_FIRE_RL_rl_merge_wr_req, - CAN_FIRE_RL_rl_miss_clean_req, - CAN_FIRE_RL_rl_power_on_reset, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reload, - CAN_FIRE_RL_rl_reset_reload_cache, - CAN_FIRE_RL_rl_writeback_dirty, - CAN_FIRE_RL_rl_writeback_dirty_idle, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_external_reset, - WILL_FIRE_RL_rl_invalid_rd_address, - WILL_FIRE_RL_rl_invalid_wr_address, - WILL_FIRE_RL_rl_merge_rd_req, - WILL_FIRE_RL_rl_merge_wr_req, - WILL_FIRE_RL_rl_miss_clean_req, - WILL_FIRE_RL_rl_power_on_reset, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reload, - WILL_FIRE_RL_rl_reset_reload_cache, - WILL_FIRE_RL_rl_writeback_dirty, - WILL_FIRE_RL_rl_writeback_dirty_idle, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire [353 : 0] MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1, - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - wire [255 : 0] MUX_rg_cached_raw_mem_word$write_1__VAL_1; - wire [170 : 0] MUX_f_reqs_rv$port1__write_1__VAL_1, - MUX_f_reqs_rv$port1__write_1__VAL_2; - wire [70 : 0] MUX_slave_xactor_f_rd_data$enq_1__VAL_1, - MUX_slave_xactor_f_rd_data$enq_1__VAL_2; - wire [5 : 0] MUX_slave_xactor_f_wr_resp$enq_1__VAL_1, - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2; - wire MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2538; - reg [31 : 0] v__h3481; - reg [31 : 0] v__h3974; - reg [31 : 0] v__h4443; - reg [31 : 0] v__h4706; - reg [31 : 0] v__h5425; - reg [31 : 0] v__h7622; - reg [31 : 0] v__h7823; - reg [31 : 0] v__h8335; - reg [31 : 0] v__h9119; - reg [31 : 0] v__h9714; - reg [31 : 0] v__h2853; - reg [31 : 0] v__h3193; - reg [31 : 0] v__h1743; - reg [31 : 0] v__h2088; - reg [31 : 0] v__h1737; - reg [31 : 0] v__h2082; - reg [31 : 0] v__h2532; - reg [31 : 0] v__h2847; - reg [31 : 0] v__h3187; - reg [31 : 0] v__h3475; - reg [31 : 0] v__h3968; - reg [31 : 0] v__h4437; - reg [31 : 0] v__h4700; - reg [31 : 0] v__h5419; - reg [31 : 0] v__h7616; - reg [31 : 0] v__h7817; - reg [31 : 0] v__h8329; - reg [31 : 0] v__h9113; - reg [31 : 0] v__h9708; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rdata__h5068, word64_old__h5862; - wire [63 : 0] exit_value__h7860, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1, - mask__h5867, - req_raw_mem_addr__h3314, - updated_word64__h5868, - x__h6241, - y__h6242, - y__h6243; - wire [7 : 0] SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191; - wire [4 : 0] n__h5067; - wire NOT_cfg_verbosity_read_ULE_1___d5, - NOT_cfg_verbosity_read_ULE_2_2___d33, - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279, - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128, - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123, - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126, - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135, - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284, - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131, - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = rg_state == 2'd3 ; - assign CAN_FIRE_set_addr_map = rg_state == 2'd3 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = f_raw_mem_reqs_rv[352:0] ; - assign RDY_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign CAN_FIRE_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = !f_raw_mem_rsps_rv$port1__read[256] ; - assign CAN_FIRE_to_raw_mem_response_put = - !f_raw_mem_rsps_rv$port1__read[256] ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // value method status - assign status = rg_status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset_reload_cache - assign CAN_FIRE_RL_rl_reset_reload_cache = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_reload_cache = - CAN_FIRE_RL_rl_reset_reload_cache ; - - // rule RL_rl_writeback_dirty_idle - assign CAN_FIRE_RL_rl_writeback_dirty_idle = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd3 && - !f_reqs_rv[170] && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty_idle = - CAN_FIRE_RL_rl_writeback_dirty_idle ; - - // rule RL_rl_writeback_dirty - assign CAN_FIRE_RL_rl_writeback_dirty = - !f_raw_mem_reqs_rv$port1__read[353] && f_reqs_rv[170] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty = CAN_FIRE_RL_rl_writeback_dirty ; - - // rule RL_rl_miss_clean_req - assign CAN_FIRE_RL_rl_miss_clean_req = - f_reqs_rv[170] && !f_raw_mem_reqs_rv$port1__read[353] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - rg_cached_clean ; - assign WILL_FIRE_RL_rl_miss_clean_req = - CAN_FIRE_RL_rl_miss_clean_req && - !WILL_FIRE_RL_rl_external_reset && - !EN_set_addr_map ; - - // rule RL_rl_reload - assign CAN_FIRE_RL_rl_reload = f_raw_mem_rsps_rv[256] && rg_state == 2'd2 ; - assign WILL_FIRE_RL_rl_reload = CAN_FIRE_RL_rl_reload ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_invalid_rd_address - assign CAN_FIRE_RL_rl_invalid_rd_address = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_rd_address = - CAN_FIRE_RL_rl_invalid_rd_address ; - - // rule RL_rl_invalid_wr_address - assign CAN_FIRE_RL_rl_invalid_wr_address = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_wr_address = - CAN_FIRE_RL_rl_invalid_wr_address ; - - // rule RL_rl_merge_rd_req - assign CAN_FIRE_RL_rl_merge_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && !f_reqs_rv$port1__read[170] ; - assign WILL_FIRE_RL_rl_merge_rd_req = CAN_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_merge_wr_req - assign CAN_FIRE_RL_rl_merge_wr_req = - !f_reqs_rv$port1__read[170] && slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N ; - assign WILL_FIRE_RL_rl_merge_wr_req = - CAN_FIRE_RL_rl_merge_wr_req && !WILL_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_power_on_reset - assign CAN_FIRE_RL_rl_power_on_reset = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_power_on_reset = CAN_FIRE_RL_rl_power_on_reset ; - - // rule RL_rl_external_reset - assign CAN_FIRE_RL_rl_external_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && rg_state == 2'd3 ; - assign WILL_FIRE_RL_rl_external_reset = CAN_FIRE_RL_rl_external_reset ; - - // inputs to muxes for submodule ports - assign MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - assign MUX_rg_state$write_1__SEL_1 = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - assign MUX_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 = - { 34'h3FFFFFFFF, - rg_cached_raw_mem_addr, - rg_cached_raw_mem_word } ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3 = - { 34'h2FFFFFFFF, - req_raw_mem_addr__h3314, - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_1 = - { 2'd2, slave_xactor_f_rd_addr$D_OUT, 72'hAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_2 = - { 2'd3, - slave_xactor_f_wr_addr$D_OUT, - slave_xactor_f_wr_data$D_OUT[8:1], - slave_xactor_f_wr_data$D_OUT[72:9] } ; - assign MUX_rg_cached_raw_mem_word$write_1__VAL_1 = - { (f_reqs_rv[105:104] == 2'd3) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[255:192], - (f_reqs_rv[105:104] == 2'd2) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[191:128], - (f_reqs_rv[105:104] == 2'd1) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[127:64], - (f_reqs_rv[105:104] == 2'd0) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[63:0] } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_1 = - { f_reqs_rv[168:165], rdata__h5068, 3'd1 } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_2 = - { f_reqs_rv[168:101], 3'd5 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 = - { f_reqs_rv[168:165], 2'd0 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 = - { f_reqs_rv[168:165], 2'd2 } ; - - // inlined wires - assign f_reqs_rv$EN_port0__write = - WILL_FIRE_RL_rl_invalid_wr_address || - WILL_FIRE_RL_rl_invalid_rd_address || - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs_rv$port1__read = - f_reqs_rv$EN_port0__write ? - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_reqs_rv ; - assign f_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_merge_rd_req || WILL_FIRE_RL_rl_merge_wr_req ; - assign f_reqs_rv$port1__write_1 = - WILL_FIRE_RL_rl_merge_rd_req ? - MUX_f_reqs_rv$port1__write_1__VAL_1 : - MUX_f_reqs_rv$port1__write_1__VAL_2 ; - assign f_reqs_rv$port2__read = - f_reqs_rv$EN_port1__write ? - f_reqs_rv$port1__write_1 : - f_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port1__read = - EN_to_raw_mem_request_get ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv ; - assign f_raw_mem_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_miss_clean_req ; - always@(MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 or - WILL_FIRE_RL_rl_reset_reload_cache or - WILL_FIRE_RL_rl_miss_clean_req or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1; - WILL_FIRE_RL_rl_reset_reload_cache: - f_raw_mem_reqs_rv$port1__write_1 = - 354'h2FFFFFFFF0000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_miss_clean_req: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - default: f_raw_mem_reqs_rv$port1__write_1 = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign f_raw_mem_reqs_rv$port2__read = - f_raw_mem_reqs_rv$EN_port1__write ? - f_raw_mem_reqs_rv$port1__write_1 : - f_raw_mem_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv$port2__read ; - assign f_raw_mem_rsps_rv$port1__read = - CAN_FIRE_RL_rl_reload ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv ; - assign f_raw_mem_rsps_rv$port1__write_1 = - { 1'd1, to_raw_mem_response_put } ; - assign f_raw_mem_rsps_rv$port2__read = - EN_to_raw_mem_response_put ? - f_raw_mem_rsps_rv$port1__write_1 : - f_raw_mem_rsps_rv$port1__read ; - assign f_raw_mem_rsps_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv$port2__read ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register f_raw_mem_reqs_rv - assign f_raw_mem_reqs_rv$D_IN = f_raw_mem_reqs_rv$port3__read ; - assign f_raw_mem_reqs_rv$EN = 1'b1 ; - - // register f_raw_mem_rsps_rv - assign f_raw_mem_rsps_rv$D_IN = f_raw_mem_rsps_rv$port3__read ; - assign f_raw_mem_rsps_rv$EN = 1'b1 ; - - // register f_reqs_rv - assign f_reqs_rv$D_IN = f_reqs_rv$port2__read ; - assign f_reqs_rv$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_cached_clean - assign rg_cached_clean$D_IN = !WILL_FIRE_RL_rl_process_wr_req ; - assign rg_cached_clean$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload || - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - - // register rg_cached_raw_mem_addr - assign rg_cached_raw_mem_addr$D_IN = - WILL_FIRE_RL_rl_miss_clean_req ? - req_raw_mem_addr__h3314 : - 64'd0 ; - assign rg_cached_raw_mem_addr$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_cached_raw_mem_word - assign rg_cached_raw_mem_word$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_rg_cached_raw_mem_word$write_1__VAL_1 : - f_raw_mem_rsps_rv[255:0] ; - assign rg_cached_raw_mem_word$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload ; - - // register rg_state - always@(MUX_rg_state$write_1__SEL_1 or - MUX_rg_state$write_1__SEL_2 or WILL_FIRE_RL_rl_reload) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_state$write_1__SEL_1: rg_state$D_IN = 2'd1; - MUX_rg_state$write_1__SEL_2: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reload: rg_state$D_IN = 2'd3; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset || - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_reload ; - - // register rg_status - assign rg_status$D_IN = - (WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset) ? - 8'd0 : - 8'd1 ; - assign rg_status$EN = - WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 || - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - - // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_watch_tohost ; - - // register rg_watch_tohost - assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ; - assign rg_watch_tohost$EN = EN_set_watch_tohost ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_merge_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_slave_xactor_f_rd_data$enq_1__VAL_1 : - MUX_slave_xactor_f_rd_data$enq_1__VAL_2 ; - assign slave_xactor_f_rd_data$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_invalid_rd_address ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 : - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 ; - assign slave_xactor_f_wr_resp$ENQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_invalid_wr_address ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_1 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d5 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read_ULE_2_2___d33 = cfg_verbosity > 4'd2 ; - assign NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 = - f_reqs_rv[92:90] != 3'b0 && - (f_reqs_rv[92:90] != 3'b001 || f_reqs_rv[101]) && - (f_reqs_rv[92:90] != 3'b010 || f_reqs_rv[102:101] != 2'h0) && - (f_reqs_rv[92:90] != 3'b011 || f_reqs_rv[103:101] != 3'h0) && - (f_reqs_rv[92:90] != 3'b100 || f_reqs_rv[104:101] != 4'h0) && - (f_reqs_rv[92:90] != 3'b101 || f_reqs_rv[105:101] != 5'h0) && - (f_reqs_rv[92:90] != 3'b110 || f_reqs_rv[106:101] != 6'h0) && - (f_reqs_rv[92:90] != 3'b111 || f_reqs_rv[107:101] != 7'h0) ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 = {8{f_reqs_rv[64]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212 = {8{f_reqs_rv[65]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208 = {8{f_reqs_rv[66]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205 = {8{f_reqs_rv[67]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201 = {8{f_reqs_rv[68]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198 = {8{f_reqs_rv[69]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194 = {8{f_reqs_rv[70]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191 = {8{f_reqs_rv[71]}} ; - assign exit_value__h7860 = { 1'd0, f_reqs_rv[63:1] } ; - assign f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1 = - f_reqs_rv[164:101] - rg_addr_base ; - assign f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 = - f_reqs_rv[164:101] < rg_addr_lim ; - assign f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 = - f_reqs_rv[92:90] == 3'b0 || - f_reqs_rv[92:90] == 3'b001 && !f_reqs_rv[101] || - f_reqs_rv[92:90] == 3'b010 && f_reqs_rv[102:101] == 2'h0 || - f_reqs_rv[92:90] == 3'b011 && f_reqs_rv[103:101] == 3'h0 || - f_reqs_rv[92:90] == 3'b100 && f_reqs_rv[104:101] == 4'h0 || - f_reqs_rv[92:90] == 3'b101 && f_reqs_rv[105:101] == 5'h0 || - f_reqs_rv[92:90] == 3'b110 && f_reqs_rv[106:101] == 6'h0 || - f_reqs_rv[92:90] == 3'b111 && f_reqs_rv[107:101] == 7'h0 ; - assign mask__h5867 = - { SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - assign n__h5067 = { 3'd0, f_reqs_rv[105:104] } ; - assign req_raw_mem_addr__h3314 = - { 5'd0, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1[63:5] } ; - assign rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 = - rg_addr_base <= f_reqs_rv[164:101] ; - assign rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 = - rg_cached_raw_mem_addr == req_raw_mem_addr__h3314 ; - assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 = - rg_state == 2'd3 && - (NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 || - !rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 || - !f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128) ; - assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 = - rg_state == 2'd3 && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 && - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 && - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 ; - assign rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 = - rg_watch_tohost && f_reqs_rv[164:101] == rg_tohost_addr && - f_reqs_rv[63:0] != 64'd0 ; - assign updated_word64__h5868 = x__h6241 | y__h6242 ; - assign x__h6241 = word64_old__h5862 & y__h6243 ; - assign y__h6242 = f_reqs_rv[63:0] & mask__h5867 ; - assign y__h6243 = - { ~SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - ~SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - ~SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - ~SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - ~SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - ~SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - ~SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - ~SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - always@(f_reqs_rv or rg_cached_raw_mem_word) - begin - case (f_reqs_rv[105:104]) - 2'd0: word64_old__h5862 = rg_cached_raw_mem_word[63:0]; - 2'd1: word64_old__h5862 = rg_cached_raw_mem_word[127:64]; - 2'd2: word64_old__h5862 = rg_cached_raw_mem_word[191:128]; - 2'd3: word64_old__h5862 = rg_cached_raw_mem_word[255:192]; - endcase - end - always@(n__h5067 or rg_cached_raw_mem_word) - begin - case (n__h5067) - 5'd0: rdata__h5068 = rg_cached_raw_mem_word[63:0]; - 5'd1: rdata__h5068 = rg_cached_raw_mem_word[127:64]; - 5'd2: rdata__h5068 = rg_cached_raw_mem_word[191:128]; - 5'd3: rdata__h5068 = rg_cached_raw_mem_word[255:192]; - default: rdata__h5068 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - rg_status <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000; - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (f_raw_mem_reqs_rv$EN) - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_reqs_rv$D_IN; - if (f_raw_mem_rsps_rv$EN) - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_rsps_rv$D_IN; - if (f_reqs_rv$EN) f_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_reqs_rv$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_status$EN) rg_status <= `BSV_ASSIGNMENT_DELAY rg_status$D_IN; - if (rg_tohost_addr$EN) - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; - if (rg_watch_tohost$EN) - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_cached_clean$EN) - rg_cached_clean <= `BSV_ASSIGNMENT_DELAY rg_cached_clean$D_IN; - if (rg_cached_raw_mem_addr$EN) - rg_cached_raw_mem_addr <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_addr$D_IN; - if (rg_cached_raw_mem_word$EN) - rg_cached_raw_mem_word <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_word$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - f_raw_mem_reqs_rv = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv = 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_cached_clean = 1'h0; - rg_cached_raw_mem_addr = 64'hAAAAAAAAAAAAAAAA; - rg_cached_raw_mem_word = - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state = 2'h2; - rg_status = 8'hAA; - rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; - rg_watch_tohost = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2538 = $stime; - #0; - end - v__h2532 = v__h2538 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING", - v__h2532); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3481 = $stime; - #0; - end - v__h3475 = v__h3481 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h", - v__h3475, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3974 = $stime; - #0; - end - v__h3968 = v__h3974 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h", - v__h3968, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4443 = $stime; - #0; - end - v__h4437 = v__h4443 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h", - v__h4437, - req_raw_mem_addr__h3314); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_reload: raw addr 0x%0h", - v__h4700, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", f_raw_mem_rsps_rv[255:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h5425 = $stime; - #0; - end - v__h5419 = v__h5425 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", rdata__h5068); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h7622 = $stime; - #0; - end - v__h7616 = v__h7622 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7616); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - begin - v__h7823 = $stime; - #0; - end - v__h7817 = v__h7823 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - $display("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h () data 0x%0h", - v__h7817, - f_reqs_rv[164:101], - f_reqs_rv[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] == 63'd0) - $display("PASS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] != 63'd0) - $display("FAIL %0d", exit_value__h7860); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - begin - v__h8335 = $stime; - #0; - end - v__h8329 = v__h8335 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("%0d: ERROR: Mem_Controller:", v__h8329); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" read-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" read-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - begin - v__h9119 = $stime; - #0; - end - v__h9113 = v__h9119 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("%0d: ERROR: Mem_Controller:", v__h9113); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" write-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" write-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - begin - v__h9714 = $stime; - #0; - end - v__h9708 = v__h9714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - $display("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9708, - set_addr_map_addr_base, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h2853 = $stime; - #0; - end - v__h2847 = v__h2853 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_rd_req", v__h2847); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3193 = $stime; - #0; - end - v__h3187 = v__h3193 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_wr_req", v__h3187); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h1743 = $stime; - #0; - end - v__h1737 = v__h1743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_power_on_reset", v__h1737); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2088 = $stime; - #0; - end - v__h2082 = v__h2088 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE", - v__h2082); - end - // synopsys translate_on -endmodule // mkMem_Controller - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v deleted file mode 100644 index 104c51b0..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v +++ /dev/null @@ -1,192 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_mem_server_request_put O 1 reg -// mem_server_response_get O 256 reg -// RDY_mem_server_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// mem_server_request_put I 353 -// EN_mem_server_request_put I 1 -// EN_mem_server_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Model(CLK, - RST_N, - - mem_server_request_put, - EN_mem_server_request_put, - RDY_mem_server_request_put, - - EN_mem_server_response_get, - mem_server_response_get, - RDY_mem_server_response_get); - input CLK; - input RST_N; - - // action method mem_server_request_put - input [352 : 0] mem_server_request_put; - input EN_mem_server_request_put; - output RDY_mem_server_request_put; - - // actionvalue method mem_server_response_get - input EN_mem_server_response_get; - output [255 : 0] mem_server_response_get; - output RDY_mem_server_response_get; - - // signals for module outputs - wire [255 : 0] mem_server_response_get; - wire RDY_mem_server_request_put, RDY_mem_server_response_get; - - // ports of submodule f_raw_mem_rsps - wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT; - wire f_raw_mem_rsps$CLR, - f_raw_mem_rsps$DEQ, - f_raw_mem_rsps$EMPTY_N, - f_raw_mem_rsps$ENQ, - f_raw_mem_rsps$FULL_N; - - // ports of submodule rf - wire [255 : 0] rf$D_IN, rf$D_OUT_1; - wire [63 : 0] rf$ADDR_1, - rf$ADDR_2, - rf$ADDR_3, - rf$ADDR_4, - rf$ADDR_5, - rf$ADDR_IN; - wire rf$WE; - - // rule scheduling signals - wire CAN_FIRE_mem_server_request_put, - CAN_FIRE_mem_server_response_get, - WILL_FIRE_mem_server_request_put, - WILL_FIRE_mem_server_response_get; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h371; - reg [31 : 0] v__h365; - // synopsys translate_on - - // remaining internal signals - wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2; - - // action method mem_server_request_put - assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ; - - // actionvalue method mem_server_response_get - assign mem_server_response_get = f_raw_mem_rsps$D_OUT ; - assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ; - - // submodule f_raw_mem_rsps - FIFO2 #(.width(32'd256), .guarded(32'd1)) f_raw_mem_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_raw_mem_rsps$D_IN), - .ENQ(f_raw_mem_rsps$ENQ), - .DEQ(f_raw_mem_rsps$DEQ), - .CLR(f_raw_mem_rsps$CLR), - .D_OUT(f_raw_mem_rsps$D_OUT), - .FULL_N(f_raw_mem_rsps$FULL_N), - .EMPTY_N(f_raw_mem_rsps$EMPTY_N)); - - // submodule rf - RegFileLoad #(.file("Mem.hex"), - .addr_width(32'd64), - .data_width(32'd256), - .lo(64'd0), - .hi(64'd8388607), - .binary(1'd0)) rf(.CLK(CLK), - .ADDR_1(rf$ADDR_1), - .ADDR_2(rf$ADDR_2), - .ADDR_3(rf$ADDR_3), - .ADDR_4(rf$ADDR_4), - .ADDR_5(rf$ADDR_5), - .ADDR_IN(rf$ADDR_IN), - .D_IN(rf$D_IN), - .WE(rf$WE), - .D_OUT_1(rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule f_raw_mem_rsps - assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ; - assign f_raw_mem_rsps$ENQ = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - !mem_server_request_put[352] ; - assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ; - assign f_raw_mem_rsps$CLR = 1'b0 ; - - // submodule rf - assign rf$ADDR_1 = mem_server_request_put[319:256] ; - assign rf$ADDR_2 = 64'h0 ; - assign rf$ADDR_3 = 64'h0 ; - assign rf$ADDR_4 = 64'h0 ; - assign rf$ADDR_5 = 64'h0 ; - assign rf$ADDR_IN = mem_server_request_put[319:256] ; - assign rf$D_IN = mem_server_request_put[255:0] ; - assign rf$WE = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - mem_server_request_put[352] ; - - // remaining internal signals - assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 = - mem_server_request_put[319:256] < 64'h0000000000800000 ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - begin - v__h371 = $stime; - #0; - end - v__h365 = v__h371 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)", - v__h365, - mem_server_request_put[319:256], - 64'h0000000000800000); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkMem_Model - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v deleted file mode 100644 index e774ea8f..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v +++ /dev/null @@ -1,1649 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 -// RDY_server_reset_response_get O 1 reg -// imem_valid O 1 -// imem_is_i32_not_i16 O 1 const -// imem_pc O 32 reg -// imem_instr O 32 -// imem_exc O 1 -// imem_exc_code O 4 reg -// imem_tval O 32 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_valid O 1 -// dmem_word64 O 64 -// dmem_st_amo_val O 64 -// dmem_exc O 1 -// dmem_exc_code O 4 reg -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_server_fence_i_request_put O 1 -// RDY_server_fence_i_response_get O 1 -// RDY_server_fence_request_put O 1 reg -// RDY_server_fence_response_get O 1 -// RDY_sfence_vma O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// imem_req_f3 I 3 -// imem_req_addr I 32 -// imem_req_priv I 2 unused -// imem_req_sstatus_SUM I 1 unused -// imem_req_mstatus_MXR I 1 unused -// imem_req_satp I 32 unused -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_req_op I 2 -// dmem_req_f3 I 3 -// dmem_req_amo_funct7 I 7 reg -// dmem_req_addr I 32 -// dmem_req_store_value I 64 -// dmem_req_priv I 2 unused -// dmem_req_sstatus_SUM I 1 unused -// dmem_req_mstatus_MXR I 1 unused -// dmem_req_satp I 32 unused -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// server_fence_request_put I 8 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_imem_req I 1 -// EN_dmem_req I 1 -// EN_server_fence_i_request_put I 1 -// EN_server_fence_i_response_get I 1 -// EN_server_fence_request_put I 1 -// EN_server_fence_response_get I 1 -// EN_sfence_vma I 1 unused -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_valid -// (imem_master_awready, imem_master_wready) -> imem_instr -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, imem_master_wready, EN_imem_req) -> imem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_valid -// (dmem_master_awready, dmem_master_wready) -> dmem_word64 -// (dmem_master_awready, dmem_master_wready) -> dmem_st_amo_val -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// (dmem_master_awready, dmem_master_wready, EN_dmem_req) -> dmem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - imem_req_f3, - imem_req_addr, - imem_req_priv, - imem_req_sstatus_SUM, - imem_req_mstatus_MXR, - imem_req_satp, - EN_imem_req, - - imem_valid, - - imem_is_i32_not_i16, - - imem_pc, - - imem_instr, - - imem_exc, - - imem_exc_code, - - imem_tval, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_req_op, - dmem_req_f3, - dmem_req_amo_funct7, - dmem_req_addr, - dmem_req_store_value, - dmem_req_priv, - dmem_req_sstatus_SUM, - dmem_req_mstatus_MXR, - dmem_req_satp, - EN_dmem_req, - - dmem_valid, - - dmem_word64, - - dmem_st_amo_val, - - dmem_exc, - - dmem_exc_code, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - EN_server_fence_i_request_put, - RDY_server_fence_i_request_put, - - EN_server_fence_i_response_get, - RDY_server_fence_i_response_get, - - server_fence_request_put, - EN_server_fence_request_put, - RDY_server_fence_request_put, - - EN_server_fence_response_get, - RDY_server_fence_response_get, - - EN_sfence_vma, - RDY_sfence_vma); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method imem_req - input [2 : 0] imem_req_f3; - input [31 : 0] imem_req_addr; - input [1 : 0] imem_req_priv; - input imem_req_sstatus_SUM; - input imem_req_mstatus_MXR; - input [31 : 0] imem_req_satp; - input EN_imem_req; - - // value method imem_valid - output imem_valid; - - // value method imem_is_i32_not_i16 - output imem_is_i32_not_i16; - - // value method imem_pc - output [31 : 0] imem_pc; - - // value method imem_instr - output [31 : 0] imem_instr; - - // value method imem_exc - output imem_exc; - - // value method imem_exc_code - output [3 : 0] imem_exc_code; - - // value method imem_tval - output [31 : 0] imem_tval; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // action method dmem_req - input [1 : 0] dmem_req_op; - input [2 : 0] dmem_req_f3; - input [6 : 0] dmem_req_amo_funct7; - input [31 : 0] dmem_req_addr; - input [63 : 0] dmem_req_store_value; - input [1 : 0] dmem_req_priv; - input dmem_req_sstatus_SUM; - input dmem_req_mstatus_MXR; - input [31 : 0] dmem_req_satp; - input EN_dmem_req; - - // value method dmem_valid - output dmem_valid; - - // value method dmem_word64 - output [63 : 0] dmem_word64; - - // value method dmem_st_amo_val - output [63 : 0] dmem_st_amo_val; - - // value method dmem_exc - output dmem_exc; - - // value method dmem_exc_code - output [3 : 0] dmem_exc_code; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method server_fence_i_request_put - input EN_server_fence_i_request_put; - output RDY_server_fence_i_request_put; - - // action method server_fence_i_response_get - input EN_server_fence_i_response_get; - output RDY_server_fence_i_response_get; - - // action method server_fence_request_put - input [7 : 0] server_fence_request_put; - input EN_server_fence_request_put; - output RDY_server_fence_request_put; - - // action method server_fence_response_get - input EN_server_fence_response_get; - output RDY_server_fence_response_get; - - // action method sfence_vma - input EN_sfence_vma; - output RDY_sfence_vma; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - dmem_st_amo_val, - dmem_word64, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [31 : 0] imem_instr, imem_pc, imem_tval; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_exc_code, - dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_exc_code, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_server_fence_i_request_put, - RDY_server_fence_i_response_get, - RDY_server_fence_request_put, - RDY_server_fence_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_sfence_vma, - dmem_exc, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - dmem_valid, - imem_exc, - imem_is_i32_not_i16, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid, - imem_valid; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule dcache - wire [63 : 0] dcache$mem_master_araddr, - dcache$mem_master_awaddr, - dcache$mem_master_rdata, - dcache$mem_master_wdata, - dcache$req_st_value, - dcache$st_amo_val, - dcache$word64; - wire [31 : 0] dcache$req_addr, dcache$req_satp; - wire [7 : 0] dcache$mem_master_arlen, - dcache$mem_master_awlen, - dcache$mem_master_wstrb; - wire [6 : 0] dcache$req_amo_funct7; - wire [3 : 0] dcache$exc_code, - dcache$mem_master_arcache, - dcache$mem_master_arid, - dcache$mem_master_arqos, - dcache$mem_master_arregion, - dcache$mem_master_awcache, - dcache$mem_master_awid, - dcache$mem_master_awqos, - dcache$mem_master_awregion, - dcache$mem_master_bid, - dcache$mem_master_rid, - dcache$mem_master_wid, - dcache$set_verbosity_verbosity; - wire [2 : 0] dcache$mem_master_arprot, - dcache$mem_master_arsize, - dcache$mem_master_awprot, - dcache$mem_master_awsize, - dcache$req_f3; - wire [1 : 0] dcache$mem_master_arburst, - dcache$mem_master_awburst, - dcache$mem_master_bresp, - dcache$mem_master_rresp, - dcache$req_op, - dcache$req_priv; - wire dcache$EN_req, - dcache$EN_server_flush_request_put, - dcache$EN_server_flush_response_get, - dcache$EN_server_reset_request_put, - dcache$EN_server_reset_response_get, - dcache$EN_set_verbosity, - dcache$EN_tlb_flush, - dcache$RDY_server_flush_request_put, - dcache$RDY_server_flush_response_get, - dcache$RDY_server_reset_request_put, - dcache$RDY_server_reset_response_get, - dcache$exc, - dcache$mem_master_arlock, - dcache$mem_master_arready, - dcache$mem_master_arvalid, - dcache$mem_master_awlock, - dcache$mem_master_awready, - dcache$mem_master_awvalid, - dcache$mem_master_bready, - dcache$mem_master_bvalid, - dcache$mem_master_rlast, - dcache$mem_master_rready, - dcache$mem_master_rvalid, - dcache$mem_master_wlast, - dcache$mem_master_wready, - dcache$mem_master_wvalid, - dcache$req_mstatus_MXR, - dcache$req_sstatus_SUM, - dcache$valid; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule icache - wire [63 : 0] icache$mem_master_araddr, - icache$mem_master_awaddr, - icache$mem_master_rdata, - icache$mem_master_wdata, - icache$req_st_value, - icache$word64; - wire [31 : 0] icache$addr, icache$req_addr, icache$req_satp; - wire [7 : 0] icache$mem_master_arlen, - icache$mem_master_awlen, - icache$mem_master_wstrb; - wire [6 : 0] icache$req_amo_funct7; - wire [3 : 0] icache$exc_code, - icache$mem_master_arcache, - icache$mem_master_arid, - icache$mem_master_arqos, - icache$mem_master_arregion, - icache$mem_master_awcache, - icache$mem_master_awid, - icache$mem_master_awqos, - icache$mem_master_awregion, - icache$mem_master_bid, - icache$mem_master_rid, - icache$mem_master_wid, - icache$set_verbosity_verbosity; - wire [2 : 0] icache$mem_master_arprot, - icache$mem_master_arsize, - icache$mem_master_awprot, - icache$mem_master_awsize, - icache$req_f3; - wire [1 : 0] icache$mem_master_arburst, - icache$mem_master_awburst, - icache$mem_master_bresp, - icache$mem_master_rresp, - icache$req_op, - icache$req_priv; - wire icache$EN_req, - icache$EN_server_flush_request_put, - icache$EN_server_flush_response_get, - icache$EN_server_reset_request_put, - icache$EN_server_reset_response_get, - icache$EN_set_verbosity, - icache$EN_tlb_flush, - icache$RDY_server_flush_request_put, - icache$RDY_server_flush_response_get, - icache$RDY_server_reset_request_put, - icache$RDY_server_reset_response_get, - icache$exc, - icache$mem_master_arlock, - icache$mem_master_arready, - icache$mem_master_arvalid, - icache$mem_master_awlock, - icache$mem_master_awready, - icache$mem_master_awvalid, - icache$mem_master_bready, - icache$mem_master_bvalid, - icache$mem_master_rlast, - icache$mem_master_rready, - icache$mem_master_rvalid, - icache$mem_master_wlast, - icache$mem_master_wready, - icache$mem_master_wvalid, - icache$req_mstatus_MXR, - icache$req_sstatus_SUM, - icache$valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_dmem_req, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_imem_req, - CAN_FIRE_server_fence_i_request_put, - CAN_FIRE_server_fence_i_response_get, - CAN_FIRE_server_fence_request_put, - CAN_FIRE_server_fence_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_sfence_vma, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_dmem_req, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_imem_req, - WILL_FIRE_server_fence_i_request_put, - WILL_FIRE_server_fence_i_response_get, - WILL_FIRE_server_fence_request_put, - WILL_FIRE_server_fence_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_sfence_vma; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h1675; - reg [31 : 0] v__h1826; - reg [31 : 0] v__h1669; - reg [31 : 0] v__h1820; - // synopsys translate_on - - // remaining internal signals - wire NOT_cfg_verbosity_read_ULE_1___d9; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = rg_state == 2'd2 ; - assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method imem_req - assign CAN_FIRE_imem_req = 1'd1 ; - assign WILL_FIRE_imem_req = EN_imem_req ; - - // value method imem_valid - assign imem_valid = icache$valid ; - - // value method imem_is_i32_not_i16 - assign imem_is_i32_not_i16 = 1'd1 ; - - // value method imem_pc - assign imem_pc = icache$addr ; - - // value method imem_instr - assign imem_instr = icache$word64[31:0] ; - - // value method imem_exc - assign imem_exc = icache$exc ; - - // value method imem_exc_code - assign imem_exc_code = icache$exc_code ; - - // value method imem_tval - assign imem_tval = icache$addr ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = icache$mem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = icache$mem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = icache$mem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = icache$mem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = icache$mem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = icache$mem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = icache$mem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = icache$mem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = icache$mem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = icache$mem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = icache$mem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = icache$mem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = icache$mem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = icache$mem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = icache$mem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = icache$mem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = icache$mem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = icache$mem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = icache$mem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = icache$mem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = icache$mem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = icache$mem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = icache$mem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = icache$mem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = icache$mem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = icache$mem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = icache$mem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = icache$mem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = icache$mem_master_rready ; - - // action method dmem_req - assign CAN_FIRE_dmem_req = 1'd1 ; - assign WILL_FIRE_dmem_req = EN_dmem_req ; - - // value method dmem_valid - assign dmem_valid = dcache$valid ; - - // value method dmem_word64 - assign dmem_word64 = dcache$word64 ; - - // value method dmem_st_amo_val - assign dmem_st_amo_val = dcache$st_amo_val ; - - // value method dmem_exc - assign dmem_exc = dcache$exc ; - - // value method dmem_exc_code - assign dmem_exc_code = dcache$exc_code ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = dcache$mem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = dcache$mem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = dcache$mem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = dcache$mem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = dcache$mem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = dcache$mem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = dcache$mem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = dcache$mem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = dcache$mem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = dcache$mem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = dcache$mem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = dcache$mem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = dcache$mem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = dcache$mem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = dcache$mem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = dcache$mem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = dcache$mem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = dcache$mem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = dcache$mem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = dcache$mem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = dcache$mem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = dcache$mem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = dcache$mem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = dcache$mem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = dcache$mem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = dcache$mem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = dcache$mem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = dcache$mem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = dcache$mem_master_rready ; - - // action method server_fence_i_request_put - assign RDY_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_i_request_put = - EN_server_fence_i_request_put ; - - // action method server_fence_i_response_get - assign RDY_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_i_response_get = - EN_server_fence_i_response_get ; - - // action method server_fence_request_put - assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_request_put = - dcache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ; - - // action method server_fence_response_get - assign RDY_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ; - - // action method sfence_vma - assign RDY_sfence_vma = 1'd1 ; - assign CAN_FIRE_sfence_vma = 1'd1 ; - assign WILL_FIRE_sfence_vma = EN_sfence_vma ; - - // submodule dcache - mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(dcache$mem_master_arready), - .mem_master_awready(dcache$mem_master_awready), - .mem_master_bid(dcache$mem_master_bid), - .mem_master_bresp(dcache$mem_master_bresp), - .mem_master_bvalid(dcache$mem_master_bvalid), - .mem_master_rdata(dcache$mem_master_rdata), - .mem_master_rid(dcache$mem_master_rid), - .mem_master_rlast(dcache$mem_master_rlast), - .mem_master_rresp(dcache$mem_master_rresp), - .mem_master_rvalid(dcache$mem_master_rvalid), - .mem_master_wready(dcache$mem_master_wready), - .req_addr(dcache$req_addr), - .req_amo_funct7(dcache$req_amo_funct7), - .req_f3(dcache$req_f3), - .req_mstatus_MXR(dcache$req_mstatus_MXR), - .req_op(dcache$req_op), - .req_priv(dcache$req_priv), - .req_satp(dcache$req_satp), - .req_sstatus_SUM(dcache$req_sstatus_SUM), - .req_st_value(dcache$req_st_value), - .set_verbosity_verbosity(dcache$set_verbosity_verbosity), - .EN_set_verbosity(dcache$EN_set_verbosity), - .EN_server_reset_request_put(dcache$EN_server_reset_request_put), - .EN_server_reset_response_get(dcache$EN_server_reset_response_get), - .EN_req(dcache$EN_req), - .EN_server_flush_request_put(dcache$EN_server_flush_request_put), - .EN_server_flush_response_get(dcache$EN_server_flush_response_get), - .EN_tlb_flush(dcache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), - .valid(dcache$valid), - .addr(), - .word64(dcache$word64), - .st_amo_val(dcache$st_amo_val), - .exc(dcache$exc), - .exc_code(dcache$exc_code), - .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(dcache$mem_master_awvalid), - .mem_master_awid(dcache$mem_master_awid), - .mem_master_awaddr(dcache$mem_master_awaddr), - .mem_master_awlen(dcache$mem_master_awlen), - .mem_master_awsize(dcache$mem_master_awsize), - .mem_master_awburst(dcache$mem_master_awburst), - .mem_master_awlock(dcache$mem_master_awlock), - .mem_master_awcache(dcache$mem_master_awcache), - .mem_master_awprot(dcache$mem_master_awprot), - .mem_master_awqos(dcache$mem_master_awqos), - .mem_master_awregion(dcache$mem_master_awregion), - .mem_master_wvalid(dcache$mem_master_wvalid), - .mem_master_wid(dcache$mem_master_wid), - .mem_master_wdata(dcache$mem_master_wdata), - .mem_master_wstrb(dcache$mem_master_wstrb), - .mem_master_wlast(dcache$mem_master_wlast), - .mem_master_bready(dcache$mem_master_bready), - .mem_master_arvalid(dcache$mem_master_arvalid), - .mem_master_arid(dcache$mem_master_arid), - .mem_master_araddr(dcache$mem_master_araddr), - .mem_master_arlen(dcache$mem_master_arlen), - .mem_master_arsize(dcache$mem_master_arsize), - .mem_master_arburst(dcache$mem_master_arburst), - .mem_master_arlock(dcache$mem_master_arlock), - .mem_master_arcache(dcache$mem_master_arcache), - .mem_master_arprot(dcache$mem_master_arprot), - .mem_master_arqos(dcache$mem_master_arqos), - .mem_master_arregion(dcache$mem_master_arregion), - .mem_master_rready(dcache$mem_master_rready)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule icache - mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(icache$mem_master_arready), - .mem_master_awready(icache$mem_master_awready), - .mem_master_bid(icache$mem_master_bid), - .mem_master_bresp(icache$mem_master_bresp), - .mem_master_bvalid(icache$mem_master_bvalid), - .mem_master_rdata(icache$mem_master_rdata), - .mem_master_rid(icache$mem_master_rid), - .mem_master_rlast(icache$mem_master_rlast), - .mem_master_rresp(icache$mem_master_rresp), - .mem_master_rvalid(icache$mem_master_rvalid), - .mem_master_wready(icache$mem_master_wready), - .req_addr(icache$req_addr), - .req_amo_funct7(icache$req_amo_funct7), - .req_f3(icache$req_f3), - .req_mstatus_MXR(icache$req_mstatus_MXR), - .req_op(icache$req_op), - .req_priv(icache$req_priv), - .req_satp(icache$req_satp), - .req_sstatus_SUM(icache$req_sstatus_SUM), - .req_st_value(icache$req_st_value), - .set_verbosity_verbosity(icache$set_verbosity_verbosity), - .EN_set_verbosity(icache$EN_set_verbosity), - .EN_server_reset_request_put(icache$EN_server_reset_request_put), - .EN_server_reset_response_get(icache$EN_server_reset_response_get), - .EN_req(icache$EN_req), - .EN_server_flush_request_put(icache$EN_server_flush_request_put), - .EN_server_flush_response_get(icache$EN_server_flush_response_get), - .EN_tlb_flush(icache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), - .valid(icache$valid), - .addr(icache$addr), - .word64(icache$word64), - .st_amo_val(), - .exc(icache$exc), - .exc_code(icache$exc_code), - .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(icache$mem_master_awvalid), - .mem_master_awid(icache$mem_master_awid), - .mem_master_awaddr(icache$mem_master_awaddr), - .mem_master_awlen(icache$mem_master_awlen), - .mem_master_awsize(icache$mem_master_awsize), - .mem_master_awburst(icache$mem_master_awburst), - .mem_master_awlock(icache$mem_master_awlock), - .mem_master_awcache(icache$mem_master_awcache), - .mem_master_awprot(icache$mem_master_awprot), - .mem_master_awqos(icache$mem_master_awqos), - .mem_master_awregion(icache$mem_master_awregion), - .mem_master_wvalid(icache$mem_master_wvalid), - .mem_master_wid(icache$mem_master_wid), - .mem_master_wdata(icache$mem_master_wdata), - .mem_master_wstrb(icache$mem_master_wstrb), - .mem_master_wlast(icache$mem_master_wlast), - .mem_master_bready(icache$mem_master_bready), - .mem_master_arvalid(icache$mem_master_arvalid), - .mem_master_arid(icache$mem_master_arid), - .mem_master_araddr(icache$mem_master_araddr), - .mem_master_arlen(icache$mem_master_arlen), - .mem_master_arsize(icache$mem_master_arsize), - .mem_master_arburst(icache$mem_master_arburst), - .mem_master_arlock(icache$mem_master_arlock), - .mem_master_arcache(icache$mem_master_arcache), - .mem_master_arprot(icache$mem_master_arprot), - .mem_master_arqos(icache$mem_master_arqos), - .mem_master_arregion(icache$mem_master_arregion), - .mem_master_rready(icache$mem_master_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - dcache$RDY_server_reset_request_put && - icache$RDY_server_reset_request_put && - rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && - !EN_server_fence_i_request_put ; - assign MUX_rg_state$write_1__SEL_3 = - dcache$RDY_server_reset_response_get && - icache$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - rg_state == 2'd1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete) - begin - case (1'b1) // synopsys parallel_case - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1; - WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset || - WILL_FIRE_RL_rl_reset_complete ; - - // submodule dcache - assign dcache$mem_master_arready = dmem_master_arready ; - assign dcache$mem_master_awready = dmem_master_awready ; - assign dcache$mem_master_bid = dmem_master_bid ; - assign dcache$mem_master_bresp = dmem_master_bresp ; - assign dcache$mem_master_bvalid = dmem_master_bvalid ; - assign dcache$mem_master_rdata = dmem_master_rdata ; - assign dcache$mem_master_rid = dmem_master_rid ; - assign dcache$mem_master_rlast = dmem_master_rlast ; - assign dcache$mem_master_rresp = dmem_master_rresp ; - assign dcache$mem_master_rvalid = dmem_master_rvalid ; - assign dcache$mem_master_wready = dmem_master_wready ; - assign dcache$req_addr = dmem_req_addr ; - assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ; - assign dcache$req_f3 = dmem_req_f3 ; - assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ; - assign dcache$req_op = dmem_req_op ; - assign dcache$req_priv = dmem_req_priv ; - assign dcache$req_satp = dmem_req_satp ; - assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ; - assign dcache$req_st_value = dmem_req_store_value ; - assign dcache$set_verbosity_verbosity = 4'h0 ; - assign dcache$EN_set_verbosity = 1'b0 ; - assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign dcache$EN_req = EN_dmem_req ; - assign dcache$EN_server_flush_request_put = - EN_server_fence_i_request_put || EN_server_fence_request_put ; - assign dcache$EN_server_flush_response_get = - EN_server_fence_i_response_get || EN_server_fence_response_get ; - assign dcache$EN_tlb_flush = EN_sfence_vma ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule icache - assign icache$mem_master_arready = imem_master_arready ; - assign icache$mem_master_awready = imem_master_awready ; - assign icache$mem_master_bid = imem_master_bid ; - assign icache$mem_master_bresp = imem_master_bresp ; - assign icache$mem_master_bvalid = imem_master_bvalid ; - assign icache$mem_master_rdata = imem_master_rdata ; - assign icache$mem_master_rid = imem_master_rid ; - assign icache$mem_master_rlast = imem_master_rlast ; - assign icache$mem_master_rresp = imem_master_rresp ; - assign icache$mem_master_rvalid = imem_master_rvalid ; - assign icache$mem_master_wready = imem_master_wready ; - assign icache$req_addr = imem_req_addr ; - assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ; - assign icache$req_f3 = imem_req_f3 ; - assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ; - assign icache$req_op = 2'd0 ; - assign icache$req_priv = imem_req_priv ; - assign icache$req_satp = imem_req_satp ; - assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ; - assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign icache$set_verbosity_verbosity = 4'h0 ; - assign icache$EN_set_verbosity = 1'b0 ; - assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign icache$EN_req = EN_imem_req ; - assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ; - assign icache$EN_server_flush_response_get = - EN_server_fence_i_response_get ; - assign icache$EN_tlb_flush = EN_sfence_vma ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1675 = $stime; - #0; - end - v__h1669 = v__h1675 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset", v__h1669); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1826 = $stime; - #0; - end - v__h1820 = v__h1826 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset_complete", v__h1820); - end - // synopsys translate_on -endmodule // mkNear_Mem - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v deleted file mode 100644 index 32e93584..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v +++ /dev/null @@ -1,1308 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// RDY_server_request_put O 1 reg -// server_response_get O 66 reg -// RDY_server_response_get O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// server_request_put I 137 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_server_request_put I 1 -// EN_server_response_get I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - server_request_put, - EN_server_request_put, - RDY_server_request_put, - - EN_server_response_get, - server_response_get, - RDY_server_response_get, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method server_request_put - input [136 : 0] server_request_put; - input EN_server_request_put; - output RDY_server_request_put; - - // actionvalue method server_response_get - input EN_server_response_get; - output [65 : 0] server_response_get; - output RDY_server_response_get; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [65 : 0] server_response_get; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_request_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_server_response_get, - RDY_set_addr_map, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reqs - wire [136 : 0] f_reqs$D_IN, f_reqs$D_OUT; - wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_rsps - wire [65 : 0] f_rsps$D_IN, f_rsps$D_OUT; - wire f_rsps$CLR, f_rsps$DEQ, f_rsps$EMPTY_N, f_rsps$ENQ, f_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_request_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_server_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_request_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_server_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire [65 : 0] MUX_f_rsps$enq_1__VAL_1, MUX_f_rsps$enq_1__VAL_2; - wire [63 : 0] MUX_crg_time$port1__write_1__VAL_1, - MUX_crg_timecmp$port1__write_1__VAL_1; - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8676; - reg [31 : 0] v__h8808; - reg [31 : 0] v__h1471; - reg [31 : 0] v__h1868; - reg [31 : 0] v__h2065; - reg [31 : 0] v__h1714; - reg [31 : 0] v__h2442; - reg [31 : 0] v__h7890; - reg [31 : 0] v__h8258; - reg [31 : 0] v__h8368; - reg [31 : 0] v__h8475; - reg [31 : 0] v__h1465; - reg [31 : 0] v__h1708; - reg [31 : 0] v__h1862; - reg [31 : 0] v__h2059; - reg [31 : 0] v__h2436; - reg [31 : 0] v__h7884; - reg [31 : 0] v__h8252; - reg [31 : 0] v__h8362; - reg [31 : 0] v__h8469; - reg [31 : 0] v__h8670; - reg [31 : 0] v__h8802; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rsp_rdata__h2209; - wire [63 : 0] byte_addr__h1981, - mask__h2865, - mask__h5362, - new_data__h5360, - new_time__h4107, - new_time__h6632, - new_timecmp__h2834, - new_timecmp__h5331, - old_time__h6631, - rdata__h1996, - rdata__h2020, - rdata__h2026, - x__h2876, - x__h4149, - x__h5373, - x__h6674, - y__h2877, - y__h2878, - y__h5374, - y__h5375; - wire [7 : 0] SEXT_f_reqs_first__8_BIT_0_31___d132, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_7_07___d108; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method server_request_put - assign RDY_server_request_put = f_reqs$FULL_N ; - assign CAN_FIRE_server_request_put = f_reqs$FULL_N ; - assign WILL_FIRE_server_request_put = EN_server_request_put ; - - // actionvalue method server_response_get - assign server_response_get = f_rsps$D_OUT ; - assign RDY_server_response_get = f_rsps$EMPTY_N ; - assign CAN_FIRE_server_response_get = f_rsps$EMPTY_N ; - assign WILL_FIRE_server_response_get = EN_server_response_get ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reqs - FIFO2 #(.width(32'd137), .guarded(32'd1)) f_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reqs$D_IN), - .ENQ(f_reqs$ENQ), - .DEQ(f_reqs$DEQ), - .CLR(f_reqs$CLR), - .D_OUT(f_reqs$D_OUT), - .FULL_N(f_reqs$FULL_N), - .EMPTY_N(f_reqs$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_rsps - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_rsps$D_IN), - .ENQ(f_rsps$ENQ), - .DEQ(f_rsps$DEQ), - .CLR(f_rsps$CLR), - .D_OUT(f_rsps$D_OUT), - .FULL_N(f_rsps$FULL_N), - .EMPTY_N(f_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && rg_state && - !f_reset_reqs$EMPTY_N && - f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && - (byte_addr__h1981 != 64'h0 || - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - f_sw_interrupt_req$FULL_N) && - rg_state && - !f_reset_reqs$EMPTY_N && - !f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign MUX_crg_time$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h000000000000BFF8) ? - new_time__h4107 : - new_time__h6632 ; - assign MUX_crg_timecmp$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h0000000000004000) ? - new_timecmp__h2834 : - new_timecmp__h5331 ; - assign MUX_f_rsps$enq_1__VAL_1 = - { 1'd1, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - rsp_rdata__h2209 } ; - assign MUX_f_rsps$enq_1__VAL_2 = - { 1'd0, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - 64'hAAAAAAAAAAAAAAAA } ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? - MUX_crg_time$port1__write_1__VAL_1 : - 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h6631 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - MUX_crg_timecmp$port1__write_1__VAL_1 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = MUX_rg_msip$write_1__SEL_1 && f_reqs$D_OUT[8] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reqs - assign f_reqs$D_IN = server_request_put ; - assign f_reqs$ENQ = EN_server_request_put ; - assign f_reqs$DEQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_rsps - assign f_rsps$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_f_rsps$enq_1__VAL_1 : - MUX_f_rsps$enq_1__VAL_2 ; - assign f_rsps$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_process_wr_req ; - assign f_rsps$DEQ = EN_server_response_get ; - assign f_rsps$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = f_reqs$D_OUT[8] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_f_reqs_first__8_BIT_0_31___d132 = {8{f_reqs$D_OUT[0]}} ; - assign SEXT_f_reqs_first__8_BIT_1_28___d129 = {8{f_reqs$D_OUT[1]}} ; - assign SEXT_f_reqs_first__8_BIT_2_24___d125 = {8{f_reqs$D_OUT[2]}} ; - assign SEXT_f_reqs_first__8_BIT_3_21___d122 = {8{f_reqs$D_OUT[3]}} ; - assign SEXT_f_reqs_first__8_BIT_4_17___d118 = {8{f_reqs$D_OUT[4]}} ; - assign SEXT_f_reqs_first__8_BIT_5_14___d115 = {8{f_reqs$D_OUT[5]}} ; - assign SEXT_f_reqs_first__8_BIT_6_10___d111 = {8{f_reqs$D_OUT[6]}} ; - assign SEXT_f_reqs_first__8_BIT_7_07___d108 = {8{f_reqs$D_OUT[7]}} ; - assign byte_addr__h1981 = f_reqs$D_OUT[135:72] - rg_addr_base ; - assign mask__h2865 = - { SEXT_f_reqs_first__8_BIT_7_07___d108, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign mask__h5362 = - { SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'd0 } ; - assign new_data__h5360 = { f_reqs$D_OUT[39:8], 32'h0 } ; - assign new_time__h4107 = x__h4149 | y__h2877 ; - assign new_time__h6632 = x__h6674 | y__h5374 ; - assign new_timecmp__h2834 = x__h2876 | y__h2877 ; - assign new_timecmp__h5331 = x__h5373 | y__h5374 ; - assign old_time__h6631 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata__h1996 = { 63'd0, rg_msip } ; - assign rdata__h2020 = { 32'd0, crg_timecmp[63:32] } ; - assign rdata__h2026 = { 32'd0, crg_time[63:32] } ; - assign rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 = - rg_msip == f_reqs$D_OUT[8] ; - assign x__h2876 = crg_timecmp & y__h2878 ; - assign x__h4149 = old_time__h6631 & y__h2878 ; - assign x__h5373 = crg_timecmp & y__h5375 ; - assign x__h6674 = old_time__h6631 & y__h5375 ; - assign y__h2877 = f_reqs$D_OUT[71:8] & mask__h2865 ; - assign y__h2878 = - { ~SEXT_f_reqs_first__8_BIT_7_07___d108, - ~SEXT_f_reqs_first__8_BIT_6_10___d111, - ~SEXT_f_reqs_first__8_BIT_5_14___d115, - ~SEXT_f_reqs_first__8_BIT_4_17___d118, - ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign y__h5374 = new_data__h5360 & mask__h5362 ; - assign y__h5375 = - { ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'hFFFFFFFF } ; - always@(byte_addr__h1981 or - rdata__h1996 or - crg_timecmp or rdata__h2020 or crg_time or rdata__h2026) - begin - case (byte_addr__h1981) - 64'h0: rsp_rdata__h2209 = rdata__h1996; - 64'h0000000000000004: rsp_rdata__h2209 = 64'd0; - 64'h0000000000004000: rsp_rdata__h2209 = crg_timecmp; - 64'h0000000000004004: rsp_rdata__h2209 = rdata__h2020; - 64'h000000000000BFF8: rsp_rdata__h2209 = crg_time; - 64'h000000000000BFFC: rsp_rdata__h2209 = rdata__h2026; - default: rsp_rdata__h2209 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8676 = $stime; - #0; - end - v__h8670 = v__h8676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_timer_interrupt_req: %x", - v__h8670, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8808 = $stime; - #0; - end - v__h8802 = v__h8808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_sw_interrupt_req: %x", - v__h8802, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1471 = $stime; - #0; - end - v__h1465 = v__h1471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO.rl_reset", v__h1465); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1868 = $stime; - #0; - end - v__h1862 = v__h1868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_rd_req: rg_mtip = %0d", - v__h1862, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h2065 = $stime; - #0; - end - v__h2059 = v__h2065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_rd_req: unrecognized addr", - v__h2059); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rsp_rdata__h2209, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1714 = $stime; - #0; - end - v__h1708 = v__h1714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h1708, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2442 = $stime; - #0; - end - v__h2436 = v__h2442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_wr_req: rg_mtip = %0d", - v__h2436, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", f_reqs$D_OUT[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h2834); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h2834 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h4107); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h5331); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h5331 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h6632); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h7890 = $stime; - #0; - end - v__h7884 = v__h7890 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_wr_req: unrecognized addr", - v__h7884); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 64'hAAAAAAAAAAAAAAAA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h8258 = $stime; - #0; - end - v__h8252 = v__h8258 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h8252, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h8368 = $stime; - #0; - end - v__h8362 = v__h8368 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h8362, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h8475 = $stime; - #0; - end - v__h8469 = v__h8475 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h8469, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v deleted file mode 100644 index 0883c8da..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v +++ /dev/null @@ -1,2812 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO_AXI4(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h10065; - reg [31 : 0] v__h10197; - reg [31 : 0] v__h1852; - reg [31 : 0] v__h2269; - reg [31 : 0] v__h2453; - reg [31 : 0] v__h2640; - reg [31 : 0] v__h2878; - reg [31 : 0] v__h2095; - reg [31 : 0] v__h3161; - reg [31 : 0] v__h3391; - reg [31 : 0] v__h8927; - reg [31 : 0] v__h9148; - reg [31 : 0] v__h9475; - reg [31 : 0] v__h9585; - reg [31 : 0] v__h9692; - reg [31 : 0] v__h1846; - reg [31 : 0] v__h2089; - reg [31 : 0] v__h2263; - reg [31 : 0] v__h2447; - reg [31 : 0] v__h2634; - reg [31 : 0] v__h2872; - reg [31 : 0] v__h3155; - reg [31 : 0] v__h3385; - reg [31 : 0] v__h8921; - reg [31 : 0] v__h9142; - reg [31 : 0] v__h9469; - reg [31 : 0] v__h9579; - reg [31 : 0] v__h9686; - reg [31 : 0] v__h10059; - reg [31 : 0] v__h10191; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] _theResult___fst__h2566; - reg [1 : 0] _theResult___snd__h2567, v__h3517; - wire [63 : 0] byte_addr__h2405, - byte_addr__h3353, - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190, - mask__h3798, - new_time__h5056, - new_timecmp__h3767, - old_time__h7614, - rdata___1__h2562, - x__h2751, - x__h3809, - x__h5098, - y__h3810, - y__h3811; - wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153; - wire [1 : 0] rresp__h2548, v__h3357; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108, - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53, - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102, - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? new_time__h5056 : 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h7614 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - new_timecmp__h3767 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = - MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - x__h2751, - rresp__h2548, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3357 } ; - assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 = - {8{slave_xactor_f_wr_data$D_OUT[1]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174 = - {8{slave_xactor_f_wr_data$D_OUT[2]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170 = - {8{slave_xactor_f_wr_data$D_OUT[3]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167 = - {8{slave_xactor_f_wr_data$D_OUT[4]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163 = - {8{slave_xactor_f_wr_data$D_OUT[5]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160 = - {8{slave_xactor_f_wr_data$D_OUT[6]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156 = - {8{slave_xactor_f_wr_data$D_OUT[7]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153 = - {8{slave_xactor_f_wr_data$D_OUT[8]}} ; - assign byte_addr__h2405 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign byte_addr__h3353 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190 = - new_timecmp__h3767 - old_time__h7614 ; - assign mask__h3798 = - { SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - assign new_time__h5056 = x__h5098 | y__h3810 ; - assign new_timecmp__h3767 = x__h3809 | y__h3810 ; - assign old_time__h7614 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata___1__h2562 = { 63'd0, rg_msip } ; - assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 = - rg_msip == slave_xactor_f_wr_data$D_OUT[9] ; - assign rresp__h2548 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 2'b11 : - _theResult___snd__h2567 ; - assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 = - slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 = - slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 || - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - f_sw_interrupt_req$FULL_N) ; - assign v__h3357 = - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ? - 2'b11 : - v__h3517 ; - assign x__h2751 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 64'd0 : - _theResult___fst__h2566 ; - assign x__h3809 = crg_timecmp & y__h3811 ; - assign x__h5098 = old_time__h7614 & y__h3811 ; - assign y__h3810 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3798 ; - assign y__h3811 = - { ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - always@(byte_addr__h2405) - begin - case (byte_addr__h2405) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - _theResult___snd__h2567 = 2'b0; - default: _theResult___snd__h2567 = 2'b11; - endcase - end - always@(byte_addr__h2405 or rdata___1__h2562 or crg_timecmp or crg_time) - begin - case (byte_addr__h2405) - 64'h0: _theResult___fst__h2566 = rdata___1__h2562; - 64'h0000000000000004: _theResult___fst__h2566 = 64'd0; - 64'h0000000000004000, 64'h0000000000004004: - _theResult___fst__h2566 = crg_timecmp; - 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___fst__h2566 = crg_time; - default: _theResult___fst__h2566 = 64'd0; - endcase - end - always@(byte_addr__h3353) - begin - case (byte_addr__h3353) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - v__h3517 = 2'b0; - default: v__h3517 = 2'b11; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10065 = $stime; - #0; - end - v__h10059 = v__h10065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x", - v__h10059, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10197 = $stime; - #0; - end - v__h10191 = v__h10197 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x", - v__h10191, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1852 = $stime; - #0; - end - v__h1846 = v__h1852 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1846); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2269 = $stime; - #0; - end - v__h2263 = v__h2269 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", - v__h2263, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - begin - v__h2453 = $stime; - #0; - end - v__h2447 = v__h2453 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2447); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - begin - v__h2640 = $stime; - #0; - end - v__h2634 = v__h2640 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2634); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2878 = $stime; - #0; - end - v__h2872 = v__h2878 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2872); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", x__h2751); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rresp__h2548); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2095 = $stime; - #0; - end - v__h2089 = v__h2095 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h2089, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h3161 = $stime; - #0; - end - v__h3155 = v__h3161 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", - v__h3155, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - begin - v__h3391 = $stime; - #0; - end - v__h3385 = v__h3391 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h3385); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - begin - v__h8927 = $stime; - #0; - end - v__h8921 = v__h8927 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h8921); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h9148 = $stime; - #0; - end - v__h9142 = v__h9148 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9142); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", v__h3357); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h9475 = $stime; - #0; - end - v__h9469 = v__h9475 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9469, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h9585 = $stime; - #0; - end - v__h9579 = v__h9585 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9579, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h9692 = $stime; - #0; - end - v__h9686 = v__h9692 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9686, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO_AXI4 - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v deleted file mode 100644 index f74de61e..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v +++ /dev/null @@ -1,26991 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_show_PLIC_state O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// v_targets_0_m_eip O 1 -// v_targets_1_m_eip O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// v_sources_0_m_interrupt_req_set_not_clear I 1 -// v_sources_1_m_interrupt_req_set_not_clear I 1 -// v_sources_2_m_interrupt_req_set_not_clear I 1 -// v_sources_3_m_interrupt_req_set_not_clear I 1 -// v_sources_4_m_interrupt_req_set_not_clear I 1 -// v_sources_5_m_interrupt_req_set_not_clear I 1 -// v_sources_6_m_interrupt_req_set_not_clear I 1 -// v_sources_7_m_interrupt_req_set_not_clear I 1 -// v_sources_8_m_interrupt_req_set_not_clear I 1 -// v_sources_9_m_interrupt_req_set_not_clear I 1 -// v_sources_10_m_interrupt_req_set_not_clear I 1 -// v_sources_11_m_interrupt_req_set_not_clear I 1 -// v_sources_12_m_interrupt_req_set_not_clear I 1 -// v_sources_13_m_interrupt_req_set_not_clear I 1 -// v_sources_14_m_interrupt_req_set_not_clear I 1 -// v_sources_15_m_interrupt_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_show_PLIC_state I 1 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkPLIC_16_2_7(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_show_PLIC_state, - RDY_show_PLIC_state, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - v_sources_0_m_interrupt_req_set_not_clear, - - v_sources_1_m_interrupt_req_set_not_clear, - - v_sources_2_m_interrupt_req_set_not_clear, - - v_sources_3_m_interrupt_req_set_not_clear, - - v_sources_4_m_interrupt_req_set_not_clear, - - v_sources_5_m_interrupt_req_set_not_clear, - - v_sources_6_m_interrupt_req_set_not_clear, - - v_sources_7_m_interrupt_req_set_not_clear, - - v_sources_8_m_interrupt_req_set_not_clear, - - v_sources_9_m_interrupt_req_set_not_clear, - - v_sources_10_m_interrupt_req_set_not_clear, - - v_sources_11_m_interrupt_req_set_not_clear, - - v_sources_12_m_interrupt_req_set_not_clear, - - v_sources_13_m_interrupt_req_set_not_clear, - - v_sources_14_m_interrupt_req_set_not_clear, - - v_sources_15_m_interrupt_req_set_not_clear, - - v_targets_0_m_eip, - - v_targets_1_m_eip); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method show_PLIC_state - input EN_show_PLIC_state; - output RDY_show_PLIC_state; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // action method v_sources_0_m_interrupt_req - input v_sources_0_m_interrupt_req_set_not_clear; - - // action method v_sources_1_m_interrupt_req - input v_sources_1_m_interrupt_req_set_not_clear; - - // action method v_sources_2_m_interrupt_req - input v_sources_2_m_interrupt_req_set_not_clear; - - // action method v_sources_3_m_interrupt_req - input v_sources_3_m_interrupt_req_set_not_clear; - - // action method v_sources_4_m_interrupt_req - input v_sources_4_m_interrupt_req_set_not_clear; - - // action method v_sources_5_m_interrupt_req - input v_sources_5_m_interrupt_req_set_not_clear; - - // action method v_sources_6_m_interrupt_req - input v_sources_6_m_interrupt_req_set_not_clear; - - // action method v_sources_7_m_interrupt_req - input v_sources_7_m_interrupt_req_set_not_clear; - - // action method v_sources_8_m_interrupt_req - input v_sources_8_m_interrupt_req_set_not_clear; - - // action method v_sources_9_m_interrupt_req - input v_sources_9_m_interrupt_req_set_not_clear; - - // action method v_sources_10_m_interrupt_req - input v_sources_10_m_interrupt_req_set_not_clear; - - // action method v_sources_11_m_interrupt_req - input v_sources_11_m_interrupt_req_set_not_clear; - - // action method v_sources_12_m_interrupt_req - input v_sources_12_m_interrupt_req_set_not_clear; - - // action method v_sources_13_m_interrupt_req - input v_sources_13_m_interrupt_req_set_not_clear; - - // action method v_sources_14_m_interrupt_req - input v_sources_14_m_interrupt_req_set_not_clear; - - // action method v_sources_15_m_interrupt_req - input v_sources_15_m_interrupt_req_set_not_clear; - - // value method v_targets_0_m_eip - output v_targets_0_m_eip; - - // value method v_targets_1_m_eip - output v_targets_1_m_eip; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_verbosity, - RDY_show_PLIC_state, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - v_targets_0_m_eip, - v_targets_1_m_eip; - - // register m_cfg_verbosity - reg [3 : 0] m_cfg_verbosity; - wire [3 : 0] m_cfg_verbosity$D_IN; - wire m_cfg_verbosity$EN; - - // register m_rg_addr_base - reg [63 : 0] m_rg_addr_base; - wire [63 : 0] m_rg_addr_base$D_IN; - wire m_rg_addr_base$EN; - - // register m_rg_addr_lim - reg [63 : 0] m_rg_addr_lim; - wire [63 : 0] m_rg_addr_lim$D_IN; - wire m_rg_addr_lim$EN; - - // register m_vrg_servicing_source_0 - reg [4 : 0] m_vrg_servicing_source_0; - wire [4 : 0] m_vrg_servicing_source_0$D_IN; - wire m_vrg_servicing_source_0$EN; - - // register m_vrg_servicing_source_1 - reg [4 : 0] m_vrg_servicing_source_1; - wire [4 : 0] m_vrg_servicing_source_1$D_IN; - wire m_vrg_servicing_source_1$EN; - - // register m_vrg_source_busy_0 - reg m_vrg_source_busy_0; - wire m_vrg_source_busy_0$D_IN, m_vrg_source_busy_0$EN; - - // register m_vrg_source_busy_1 - reg m_vrg_source_busy_1; - wire m_vrg_source_busy_1$D_IN, m_vrg_source_busy_1$EN; - - // register m_vrg_source_busy_10 - reg m_vrg_source_busy_10; - wire m_vrg_source_busy_10$D_IN, m_vrg_source_busy_10$EN; - - // register m_vrg_source_busy_11 - reg m_vrg_source_busy_11; - wire m_vrg_source_busy_11$D_IN, m_vrg_source_busy_11$EN; - - // register m_vrg_source_busy_12 - reg m_vrg_source_busy_12; - wire m_vrg_source_busy_12$D_IN, m_vrg_source_busy_12$EN; - - // register m_vrg_source_busy_13 - reg m_vrg_source_busy_13; - wire m_vrg_source_busy_13$D_IN, m_vrg_source_busy_13$EN; - - // register m_vrg_source_busy_14 - reg m_vrg_source_busy_14; - wire m_vrg_source_busy_14$D_IN, m_vrg_source_busy_14$EN; - - // register m_vrg_source_busy_15 - reg m_vrg_source_busy_15; - wire m_vrg_source_busy_15$D_IN, m_vrg_source_busy_15$EN; - - // register m_vrg_source_busy_16 - reg m_vrg_source_busy_16; - wire m_vrg_source_busy_16$D_IN, m_vrg_source_busy_16$EN; - - // register m_vrg_source_busy_2 - reg m_vrg_source_busy_2; - wire m_vrg_source_busy_2$D_IN, m_vrg_source_busy_2$EN; - - // register m_vrg_source_busy_3 - reg m_vrg_source_busy_3; - wire m_vrg_source_busy_3$D_IN, m_vrg_source_busy_3$EN; - - // register m_vrg_source_busy_4 - reg m_vrg_source_busy_4; - wire m_vrg_source_busy_4$D_IN, m_vrg_source_busy_4$EN; - - // register m_vrg_source_busy_5 - reg m_vrg_source_busy_5; - wire m_vrg_source_busy_5$D_IN, m_vrg_source_busy_5$EN; - - // register m_vrg_source_busy_6 - reg m_vrg_source_busy_6; - wire m_vrg_source_busy_6$D_IN, m_vrg_source_busy_6$EN; - - // register m_vrg_source_busy_7 - reg m_vrg_source_busy_7; - wire m_vrg_source_busy_7$D_IN, m_vrg_source_busy_7$EN; - - // register m_vrg_source_busy_8 - reg m_vrg_source_busy_8; - wire m_vrg_source_busy_8$D_IN, m_vrg_source_busy_8$EN; - - // register m_vrg_source_busy_9 - reg m_vrg_source_busy_9; - wire m_vrg_source_busy_9$D_IN, m_vrg_source_busy_9$EN; - - // register m_vrg_source_ip_0 - reg m_vrg_source_ip_0; - wire m_vrg_source_ip_0$D_IN, m_vrg_source_ip_0$EN; - - // register m_vrg_source_ip_1 - reg m_vrg_source_ip_1; - wire m_vrg_source_ip_1$D_IN, m_vrg_source_ip_1$EN; - - // register m_vrg_source_ip_10 - reg m_vrg_source_ip_10; - wire m_vrg_source_ip_10$D_IN, m_vrg_source_ip_10$EN; - - // register m_vrg_source_ip_11 - reg m_vrg_source_ip_11; - wire m_vrg_source_ip_11$D_IN, m_vrg_source_ip_11$EN; - - // register m_vrg_source_ip_12 - reg m_vrg_source_ip_12; - wire m_vrg_source_ip_12$D_IN, m_vrg_source_ip_12$EN; - - // register m_vrg_source_ip_13 - reg m_vrg_source_ip_13; - wire m_vrg_source_ip_13$D_IN, m_vrg_source_ip_13$EN; - - // register m_vrg_source_ip_14 - reg m_vrg_source_ip_14; - wire m_vrg_source_ip_14$D_IN, m_vrg_source_ip_14$EN; - - // register m_vrg_source_ip_15 - reg m_vrg_source_ip_15; - wire m_vrg_source_ip_15$D_IN, m_vrg_source_ip_15$EN; - - // register m_vrg_source_ip_16 - reg m_vrg_source_ip_16; - wire m_vrg_source_ip_16$D_IN, m_vrg_source_ip_16$EN; - - // register m_vrg_source_ip_2 - reg m_vrg_source_ip_2; - wire m_vrg_source_ip_2$D_IN, m_vrg_source_ip_2$EN; - - // register m_vrg_source_ip_3 - reg m_vrg_source_ip_3; - wire m_vrg_source_ip_3$D_IN, m_vrg_source_ip_3$EN; - - // register m_vrg_source_ip_4 - reg m_vrg_source_ip_4; - wire m_vrg_source_ip_4$D_IN, m_vrg_source_ip_4$EN; - - // register m_vrg_source_ip_5 - reg m_vrg_source_ip_5; - wire m_vrg_source_ip_5$D_IN, m_vrg_source_ip_5$EN; - - // register m_vrg_source_ip_6 - reg m_vrg_source_ip_6; - wire m_vrg_source_ip_6$D_IN, m_vrg_source_ip_6$EN; - - // register m_vrg_source_ip_7 - reg m_vrg_source_ip_7; - wire m_vrg_source_ip_7$D_IN, m_vrg_source_ip_7$EN; - - // register m_vrg_source_ip_8 - reg m_vrg_source_ip_8; - wire m_vrg_source_ip_8$D_IN, m_vrg_source_ip_8$EN; - - // register m_vrg_source_ip_9 - reg m_vrg_source_ip_9; - wire m_vrg_source_ip_9$D_IN, m_vrg_source_ip_9$EN; - - // register m_vrg_source_prio_0 - reg [2 : 0] m_vrg_source_prio_0; - wire [2 : 0] m_vrg_source_prio_0$D_IN; - wire m_vrg_source_prio_0$EN; - - // register m_vrg_source_prio_1 - reg [2 : 0] m_vrg_source_prio_1; - wire [2 : 0] m_vrg_source_prio_1$D_IN; - wire m_vrg_source_prio_1$EN; - - // register m_vrg_source_prio_10 - reg [2 : 0] m_vrg_source_prio_10; - wire [2 : 0] m_vrg_source_prio_10$D_IN; - wire m_vrg_source_prio_10$EN; - - // register m_vrg_source_prio_11 - reg [2 : 0] m_vrg_source_prio_11; - wire [2 : 0] m_vrg_source_prio_11$D_IN; - wire m_vrg_source_prio_11$EN; - - // register m_vrg_source_prio_12 - reg [2 : 0] m_vrg_source_prio_12; - wire [2 : 0] m_vrg_source_prio_12$D_IN; - wire m_vrg_source_prio_12$EN; - - // register m_vrg_source_prio_13 - reg [2 : 0] m_vrg_source_prio_13; - wire [2 : 0] m_vrg_source_prio_13$D_IN; - wire m_vrg_source_prio_13$EN; - - // register m_vrg_source_prio_14 - reg [2 : 0] m_vrg_source_prio_14; - wire [2 : 0] m_vrg_source_prio_14$D_IN; - wire m_vrg_source_prio_14$EN; - - // register m_vrg_source_prio_15 - reg [2 : 0] m_vrg_source_prio_15; - wire [2 : 0] m_vrg_source_prio_15$D_IN; - wire m_vrg_source_prio_15$EN; - - // register m_vrg_source_prio_16 - reg [2 : 0] m_vrg_source_prio_16; - wire [2 : 0] m_vrg_source_prio_16$D_IN; - wire m_vrg_source_prio_16$EN; - - // register m_vrg_source_prio_2 - reg [2 : 0] m_vrg_source_prio_2; - wire [2 : 0] m_vrg_source_prio_2$D_IN; - wire m_vrg_source_prio_2$EN; - - // register m_vrg_source_prio_3 - reg [2 : 0] m_vrg_source_prio_3; - wire [2 : 0] m_vrg_source_prio_3$D_IN; - wire m_vrg_source_prio_3$EN; - - // register m_vrg_source_prio_4 - reg [2 : 0] m_vrg_source_prio_4; - wire [2 : 0] m_vrg_source_prio_4$D_IN; - wire m_vrg_source_prio_4$EN; - - // register m_vrg_source_prio_5 - reg [2 : 0] m_vrg_source_prio_5; - wire [2 : 0] m_vrg_source_prio_5$D_IN; - wire m_vrg_source_prio_5$EN; - - // register m_vrg_source_prio_6 - reg [2 : 0] m_vrg_source_prio_6; - wire [2 : 0] m_vrg_source_prio_6$D_IN; - wire m_vrg_source_prio_6$EN; - - // register m_vrg_source_prio_7 - reg [2 : 0] m_vrg_source_prio_7; - wire [2 : 0] m_vrg_source_prio_7$D_IN; - wire m_vrg_source_prio_7$EN; - - // register m_vrg_source_prio_8 - reg [2 : 0] m_vrg_source_prio_8; - wire [2 : 0] m_vrg_source_prio_8$D_IN; - wire m_vrg_source_prio_8$EN; - - // register m_vrg_source_prio_9 - reg [2 : 0] m_vrg_source_prio_9; - wire [2 : 0] m_vrg_source_prio_9$D_IN; - wire m_vrg_source_prio_9$EN; - - // register m_vrg_target_threshold_0 - reg [2 : 0] m_vrg_target_threshold_0; - wire [2 : 0] m_vrg_target_threshold_0$D_IN; - wire m_vrg_target_threshold_0$EN; - - // register m_vrg_target_threshold_1 - reg [2 : 0] m_vrg_target_threshold_1; - wire [2 : 0] m_vrg_target_threshold_1$D_IN; - wire m_vrg_target_threshold_1$EN; - - // register m_vvrg_ie_0_0 - reg m_vvrg_ie_0_0; - wire m_vvrg_ie_0_0$D_IN, m_vvrg_ie_0_0$EN; - - // register m_vvrg_ie_0_1 - reg m_vvrg_ie_0_1; - wire m_vvrg_ie_0_1$D_IN, m_vvrg_ie_0_1$EN; - - // register m_vvrg_ie_0_10 - reg m_vvrg_ie_0_10; - wire m_vvrg_ie_0_10$D_IN, m_vvrg_ie_0_10$EN; - - // register m_vvrg_ie_0_11 - reg m_vvrg_ie_0_11; - wire m_vvrg_ie_0_11$D_IN, m_vvrg_ie_0_11$EN; - - // register m_vvrg_ie_0_12 - reg m_vvrg_ie_0_12; - wire m_vvrg_ie_0_12$D_IN, m_vvrg_ie_0_12$EN; - - // register m_vvrg_ie_0_13 - reg m_vvrg_ie_0_13; - wire m_vvrg_ie_0_13$D_IN, m_vvrg_ie_0_13$EN; - - // register m_vvrg_ie_0_14 - reg m_vvrg_ie_0_14; - wire m_vvrg_ie_0_14$D_IN, m_vvrg_ie_0_14$EN; - - // register m_vvrg_ie_0_15 - reg m_vvrg_ie_0_15; - wire m_vvrg_ie_0_15$D_IN, m_vvrg_ie_0_15$EN; - - // register m_vvrg_ie_0_16 - reg m_vvrg_ie_0_16; - wire m_vvrg_ie_0_16$D_IN, m_vvrg_ie_0_16$EN; - - // register m_vvrg_ie_0_2 - reg m_vvrg_ie_0_2; - wire m_vvrg_ie_0_2$D_IN, m_vvrg_ie_0_2$EN; - - // register m_vvrg_ie_0_3 - reg m_vvrg_ie_0_3; - wire m_vvrg_ie_0_3$D_IN, m_vvrg_ie_0_3$EN; - - // register m_vvrg_ie_0_4 - reg m_vvrg_ie_0_4; - wire m_vvrg_ie_0_4$D_IN, m_vvrg_ie_0_4$EN; - - // register m_vvrg_ie_0_5 - reg m_vvrg_ie_0_5; - wire m_vvrg_ie_0_5$D_IN, m_vvrg_ie_0_5$EN; - - // register m_vvrg_ie_0_6 - reg m_vvrg_ie_0_6; - wire m_vvrg_ie_0_6$D_IN, m_vvrg_ie_0_6$EN; - - // register m_vvrg_ie_0_7 - reg m_vvrg_ie_0_7; - wire m_vvrg_ie_0_7$D_IN, m_vvrg_ie_0_7$EN; - - // register m_vvrg_ie_0_8 - reg m_vvrg_ie_0_8; - wire m_vvrg_ie_0_8$D_IN, m_vvrg_ie_0_8$EN; - - // register m_vvrg_ie_0_9 - reg m_vvrg_ie_0_9; - wire m_vvrg_ie_0_9$D_IN, m_vvrg_ie_0_9$EN; - - // register m_vvrg_ie_1_0 - reg m_vvrg_ie_1_0; - wire m_vvrg_ie_1_0$D_IN, m_vvrg_ie_1_0$EN; - - // register m_vvrg_ie_1_1 - reg m_vvrg_ie_1_1; - wire m_vvrg_ie_1_1$D_IN, m_vvrg_ie_1_1$EN; - - // register m_vvrg_ie_1_10 - reg m_vvrg_ie_1_10; - wire m_vvrg_ie_1_10$D_IN, m_vvrg_ie_1_10$EN; - - // register m_vvrg_ie_1_11 - reg m_vvrg_ie_1_11; - wire m_vvrg_ie_1_11$D_IN, m_vvrg_ie_1_11$EN; - - // register m_vvrg_ie_1_12 - reg m_vvrg_ie_1_12; - wire m_vvrg_ie_1_12$D_IN, m_vvrg_ie_1_12$EN; - - // register m_vvrg_ie_1_13 - reg m_vvrg_ie_1_13; - wire m_vvrg_ie_1_13$D_IN, m_vvrg_ie_1_13$EN; - - // register m_vvrg_ie_1_14 - reg m_vvrg_ie_1_14; - wire m_vvrg_ie_1_14$D_IN, m_vvrg_ie_1_14$EN; - - // register m_vvrg_ie_1_15 - reg m_vvrg_ie_1_15; - wire m_vvrg_ie_1_15$D_IN, m_vvrg_ie_1_15$EN; - - // register m_vvrg_ie_1_16 - reg m_vvrg_ie_1_16; - wire m_vvrg_ie_1_16$D_IN, m_vvrg_ie_1_16$EN; - - // register m_vvrg_ie_1_2 - reg m_vvrg_ie_1_2; - wire m_vvrg_ie_1_2$D_IN, m_vvrg_ie_1_2$EN; - - // register m_vvrg_ie_1_3 - reg m_vvrg_ie_1_3; - wire m_vvrg_ie_1_3$D_IN, m_vvrg_ie_1_3$EN; - - // register m_vvrg_ie_1_4 - reg m_vvrg_ie_1_4; - wire m_vvrg_ie_1_4$D_IN, m_vvrg_ie_1_4$EN; - - // register m_vvrg_ie_1_5 - reg m_vvrg_ie_1_5; - wire m_vvrg_ie_1_5$D_IN, m_vvrg_ie_1_5$EN; - - // register m_vvrg_ie_1_6 - reg m_vvrg_ie_1_6; - wire m_vvrg_ie_1_6$D_IN, m_vvrg_ie_1_6$EN; - - // register m_vvrg_ie_1_7 - reg m_vvrg_ie_1_7; - wire m_vvrg_ie_1_7$D_IN, m_vvrg_ie_1_7$EN; - - // register m_vvrg_ie_1_8 - reg m_vvrg_ie_1_8; - wire m_vvrg_ie_1_8$D_IN, m_vvrg_ie_1_8$EN; - - // register m_vvrg_ie_1_9 - reg m_vvrg_ie_1_9; - wire m_vvrg_ie_1_9$D_IN, m_vvrg_ie_1_9$EN; - - // ports of submodule m_f_reset_reqs - wire m_f_reset_reqs$CLR, - m_f_reset_reqs$DEQ, - m_f_reset_reqs$EMPTY_N, - m_f_reset_reqs$ENQ, - m_f_reset_reqs$FULL_N; - - // ports of submodule m_f_reset_rsps - wire m_f_reset_rsps$CLR, - m_f_reset_rsps$DEQ, - m_f_reset_rsps$EMPTY_N, - m_f_reset_rsps$ENQ, - m_f_reset_rsps$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_addr - wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT; - wire m_slave_xactor_f_rd_addr$CLR, - m_slave_xactor_f_rd_addr$DEQ, - m_slave_xactor_f_rd_addr$EMPTY_N, - m_slave_xactor_f_rd_addr$ENQ, - m_slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_data - wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT; - wire m_slave_xactor_f_rd_data$CLR, - m_slave_xactor_f_rd_data$DEQ, - m_slave_xactor_f_rd_data$EMPTY_N, - m_slave_xactor_f_rd_data$ENQ, - m_slave_xactor_f_rd_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_addr - wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT; - wire m_slave_xactor_f_wr_addr$CLR, - m_slave_xactor_f_wr_addr$DEQ, - m_slave_xactor_f_wr_addr$EMPTY_N, - m_slave_xactor_f_wr_addr$ENQ, - m_slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; - wire m_slave_xactor_f_wr_data$CLR, - m_slave_xactor_f_wr_data$DEQ, - m_slave_xactor_f_wr_data$EMPTY_N, - m_slave_xactor_f_wr_data$ENQ, - m_slave_xactor_f_wr_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_resp - wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT; - wire m_slave_xactor_f_wr_resp$CLR, - m_slave_xactor_f_wr_resp$DEQ, - m_slave_xactor_f_wr_resp$EMPTY_N, - m_slave_xactor_f_wr_resp$ENQ, - m_slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_process_rd_req, - CAN_FIRE_RL_m_rl_process_wr_req, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_verbosity, - CAN_FIRE_show_PLIC_state, - CAN_FIRE_v_sources_0_m_interrupt_req, - CAN_FIRE_v_sources_10_m_interrupt_req, - CAN_FIRE_v_sources_11_m_interrupt_req, - CAN_FIRE_v_sources_12_m_interrupt_req, - CAN_FIRE_v_sources_13_m_interrupt_req, - CAN_FIRE_v_sources_14_m_interrupt_req, - CAN_FIRE_v_sources_15_m_interrupt_req, - CAN_FIRE_v_sources_1_m_interrupt_req, - CAN_FIRE_v_sources_2_m_interrupt_req, - CAN_FIRE_v_sources_3_m_interrupt_req, - CAN_FIRE_v_sources_4_m_interrupt_req, - CAN_FIRE_v_sources_5_m_interrupt_req, - CAN_FIRE_v_sources_6_m_interrupt_req, - CAN_FIRE_v_sources_7_m_interrupt_req, - CAN_FIRE_v_sources_8_m_interrupt_req, - CAN_FIRE_v_sources_9_m_interrupt_req, - WILL_FIRE_RL_m_rl_process_rd_req, - WILL_FIRE_RL_m_rl_process_wr_req, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_verbosity, - WILL_FIRE_show_PLIC_state, - WILL_FIRE_v_sources_0_m_interrupt_req, - WILL_FIRE_v_sources_10_m_interrupt_req, - WILL_FIRE_v_sources_11_m_interrupt_req, - WILL_FIRE_v_sources_12_m_interrupt_req, - WILL_FIRE_v_sources_13_m_interrupt_req, - WILL_FIRE_v_sources_14_m_interrupt_req, - WILL_FIRE_v_sources_15_m_interrupt_req, - WILL_FIRE_v_sources_1_m_interrupt_req, - WILL_FIRE_v_sources_2_m_interrupt_req, - WILL_FIRE_v_sources_3_m_interrupt_req, - WILL_FIRE_v_sources_4_m_interrupt_req, - WILL_FIRE_v_sources_5_m_interrupt_req, - WILL_FIRE_v_sources_6_m_interrupt_req, - WILL_FIRE_v_sources_7_m_interrupt_req, - WILL_FIRE_v_sources_8_m_interrupt_req, - WILL_FIRE_v_sources_9_m_interrupt_req; - - // inputs to muxes for submodule ports - wire MUX_m_vrg_servicing_source_0$write_1__SEL_1, - MUX_m_vrg_servicing_source_1$write_1__SEL_1, - MUX_m_vrg_source_busy_0$write_1__SEL_2, - MUX_m_vrg_source_busy_1$write_1__SEL_1, - MUX_m_vrg_source_busy_1$write_1__SEL_2, - MUX_m_vrg_source_busy_10$write_1__SEL_1, - MUX_m_vrg_source_busy_10$write_1__SEL_2, - MUX_m_vrg_source_busy_11$write_1__SEL_1, - MUX_m_vrg_source_busy_11$write_1__SEL_2, - MUX_m_vrg_source_busy_12$write_1__SEL_1, - MUX_m_vrg_source_busy_12$write_1__SEL_2, - MUX_m_vrg_source_busy_13$write_1__SEL_1, - MUX_m_vrg_source_busy_13$write_1__SEL_2, - MUX_m_vrg_source_busy_14$write_1__SEL_1, - MUX_m_vrg_source_busy_14$write_1__SEL_2, - MUX_m_vrg_source_busy_15$write_1__SEL_1, - MUX_m_vrg_source_busy_15$write_1__SEL_2, - MUX_m_vrg_source_busy_16$write_1__SEL_1, - MUX_m_vrg_source_busy_16$write_1__SEL_2, - MUX_m_vrg_source_busy_2$write_1__SEL_1, - MUX_m_vrg_source_busy_2$write_1__SEL_2, - MUX_m_vrg_source_busy_3$write_1__SEL_1, - MUX_m_vrg_source_busy_3$write_1__SEL_2, - MUX_m_vrg_source_busy_4$write_1__SEL_1, - MUX_m_vrg_source_busy_4$write_1__SEL_2, - MUX_m_vrg_source_busy_5$write_1__SEL_1, - MUX_m_vrg_source_busy_5$write_1__SEL_2, - MUX_m_vrg_source_busy_6$write_1__SEL_1, - MUX_m_vrg_source_busy_6$write_1__SEL_2, - MUX_m_vrg_source_busy_7$write_1__SEL_1, - MUX_m_vrg_source_busy_7$write_1__SEL_2, - MUX_m_vrg_source_busy_8$write_1__SEL_1, - MUX_m_vrg_source_busy_8$write_1__SEL_2, - MUX_m_vrg_source_busy_9$write_1__SEL_1, - MUX_m_vrg_source_busy_9$write_1__SEL_2, - MUX_m_vrg_source_prio_0$write_1__SEL_1, - MUX_m_vrg_source_prio_1$write_1__SEL_1, - MUX_m_vrg_source_prio_10$write_1__SEL_1, - MUX_m_vrg_source_prio_11$write_1__SEL_1, - MUX_m_vrg_source_prio_12$write_1__SEL_1, - MUX_m_vrg_source_prio_13$write_1__SEL_1, - MUX_m_vrg_source_prio_14$write_1__SEL_1, - MUX_m_vrg_source_prio_15$write_1__SEL_1, - MUX_m_vrg_source_prio_16$write_1__SEL_1, - MUX_m_vrg_source_prio_2$write_1__SEL_1, - MUX_m_vrg_source_prio_3$write_1__SEL_1, - MUX_m_vrg_source_prio_4$write_1__SEL_1, - MUX_m_vrg_source_prio_5$write_1__SEL_1, - MUX_m_vrg_source_prio_6$write_1__SEL_1, - MUX_m_vrg_source_prio_7$write_1__SEL_1, - MUX_m_vrg_source_prio_8$write_1__SEL_1, - MUX_m_vrg_source_prio_9$write_1__SEL_1, - MUX_m_vrg_target_threshold_0$write_1__SEL_1, - MUX_m_vrg_target_threshold_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__VAL_1, - MUX_m_vvrg_ie_0_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_1$write_1__VAL_1, - MUX_m_vvrg_ie_0_10$write_1__SEL_1, - MUX_m_vvrg_ie_0_10$write_1__VAL_1, - MUX_m_vvrg_ie_0_11$write_1__SEL_1, - MUX_m_vvrg_ie_0_11$write_1__VAL_1, - MUX_m_vvrg_ie_0_12$write_1__SEL_1, - MUX_m_vvrg_ie_0_12$write_1__VAL_1, - MUX_m_vvrg_ie_0_13$write_1__SEL_1, - MUX_m_vvrg_ie_0_13$write_1__VAL_1, - MUX_m_vvrg_ie_0_14$write_1__SEL_1, - MUX_m_vvrg_ie_0_14$write_1__VAL_1, - MUX_m_vvrg_ie_0_15$write_1__SEL_1, - MUX_m_vvrg_ie_0_15$write_1__VAL_1, - MUX_m_vvrg_ie_0_16$write_1__SEL_1, - MUX_m_vvrg_ie_0_16$write_1__VAL_1, - MUX_m_vvrg_ie_0_2$write_1__SEL_1, - MUX_m_vvrg_ie_0_2$write_1__VAL_1, - MUX_m_vvrg_ie_0_3$write_1__SEL_1, - MUX_m_vvrg_ie_0_3$write_1__VAL_1, - MUX_m_vvrg_ie_0_4$write_1__SEL_1, - MUX_m_vvrg_ie_0_4$write_1__VAL_1, - MUX_m_vvrg_ie_0_5$write_1__SEL_1, - MUX_m_vvrg_ie_0_5$write_1__VAL_1, - MUX_m_vvrg_ie_0_6$write_1__SEL_1, - MUX_m_vvrg_ie_0_6$write_1__VAL_1, - MUX_m_vvrg_ie_0_7$write_1__SEL_1, - MUX_m_vvrg_ie_0_7$write_1__VAL_1, - MUX_m_vvrg_ie_0_8$write_1__SEL_1, - MUX_m_vvrg_ie_0_8$write_1__VAL_1, - MUX_m_vvrg_ie_0_9$write_1__SEL_1, - MUX_m_vvrg_ie_0_9$write_1__VAL_1, - MUX_m_vvrg_ie_1_0$write_1__SEL_1, - MUX_m_vvrg_ie_1_0$write_1__VAL_1, - MUX_m_vvrg_ie_1_1$write_1__SEL_1, - MUX_m_vvrg_ie_1_1$write_1__VAL_1, - MUX_m_vvrg_ie_1_10$write_1__SEL_1, - MUX_m_vvrg_ie_1_10$write_1__VAL_1, - MUX_m_vvrg_ie_1_11$write_1__SEL_1, - MUX_m_vvrg_ie_1_11$write_1__VAL_1, - MUX_m_vvrg_ie_1_12$write_1__SEL_1, - MUX_m_vvrg_ie_1_12$write_1__VAL_1, - MUX_m_vvrg_ie_1_13$write_1__SEL_1, - MUX_m_vvrg_ie_1_13$write_1__VAL_1, - MUX_m_vvrg_ie_1_14$write_1__SEL_1, - MUX_m_vvrg_ie_1_14$write_1__VAL_1, - MUX_m_vvrg_ie_1_15$write_1__SEL_1, - MUX_m_vvrg_ie_1_15$write_1__VAL_1, - MUX_m_vvrg_ie_1_16$write_1__SEL_1, - MUX_m_vvrg_ie_1_16$write_1__VAL_1, - MUX_m_vvrg_ie_1_2$write_1__SEL_1, - MUX_m_vvrg_ie_1_2$write_1__VAL_1, - MUX_m_vvrg_ie_1_3$write_1__SEL_1, - MUX_m_vvrg_ie_1_3$write_1__VAL_1, - MUX_m_vvrg_ie_1_4$write_1__SEL_1, - MUX_m_vvrg_ie_1_4$write_1__VAL_1, - MUX_m_vvrg_ie_1_5$write_1__SEL_1, - MUX_m_vvrg_ie_1_5$write_1__VAL_1, - MUX_m_vvrg_ie_1_6$write_1__SEL_1, - MUX_m_vvrg_ie_1_6$write_1__VAL_1, - MUX_m_vvrg_ie_1_7$write_1__SEL_1, - MUX_m_vvrg_ie_1_7$write_1__VAL_1, - MUX_m_vvrg_ie_1_8$write_1__SEL_1, - MUX_m_vvrg_ie_1_8$write_1__VAL_1, - MUX_m_vvrg_ie_1_9$write_1__SEL_1, - MUX_m_vvrg_ie_1_9$write_1__VAL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h75676; - reg [31 : 0] v__h75874; - reg [31 : 0] v__h76072; - reg [31 : 0] v__h76270; - reg [31 : 0] v__h76468; - reg [31 : 0] v__h76666; - reg [31 : 0] v__h76864; - reg [31 : 0] v__h77062; - reg [31 : 0] v__h77260; - reg [31 : 0] v__h77458; - reg [31 : 0] v__h77656; - reg [31 : 0] v__h77854; - reg [31 : 0] v__h78052; - reg [31 : 0] v__h78250; - reg [31 : 0] v__h78448; - reg [31 : 0] v__h78646; - reg [31 : 0] v__h6144; - reg [31 : 0] v__h13080; - reg [31 : 0] v__h13265; - reg [31 : 0] v__h13463; - reg [31 : 0] v__h13713; - reg [31 : 0] v__h18186; - reg [31 : 0] v__h23802; - reg [31 : 0] v__h25975; - reg [31 : 0] v__h24056; - reg [31 : 0] v__h26250; - reg [31 : 0] v__h26463; - reg [31 : 0] v__h26740; - reg [31 : 0] v__h26968; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h28048; - reg [31 : 0] v__h67030; - reg [31 : 0] v__h67318; - reg [31 : 0] v__h67847; - reg [31 : 0] v__h67933; - reg [31 : 0] v__h68132; - reg [31 : 0] v__h68353; - reg [31 : 0] v__h74690; - reg [31 : 0] v__h74800; - reg [31 : 0] v__h74913; - reg [31 : 0] v__h6138; - reg [31 : 0] v__h13074; - reg [31 : 0] v__h13259; - reg [31 : 0] v__h13457; - reg [31 : 0] v__h13707; - reg [31 : 0] v__h18180; - reg [31 : 0] v__h23796; - reg [31 : 0] v__h24050; - reg [31 : 0] v__h25969; - reg [31 : 0] v__h26244; - reg [31 : 0] v__h26457; - reg [31 : 0] v__h26734; - reg [31 : 0] v__h26962; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28042; - reg [31 : 0] v__h67024; - reg [31 : 0] v__h67312; - reg [31 : 0] v__h67841; - reg [31 : 0] v__h67927; - reg [31 : 0] v__h68126; - reg [31 : 0] v__h68347; - reg [31 : 0] v__h74684; - reg [31 : 0] v__h74794; - reg [31 : 0] v__h74907; - reg [31 : 0] v__h75670; - reg [31 : 0] v__h75868; - reg [31 : 0] v__h76066; - reg [31 : 0] v__h76264; - reg [31 : 0] v__h76462; - reg [31 : 0] v__h76660; - reg [31 : 0] v__h76858; - reg [31 : 0] v__h77056; - reg [31 : 0] v__h77254; - reg [31 : 0] v__h77452; - reg [31 : 0] v__h77650; - reg [31 : 0] v__h77848; - reg [31 : 0] v__h78046; - reg [31 : 0] v__h78244; - reg [31 : 0] v__h78442; - reg [31 : 0] v__h78640; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] y_avValue_fst__h26148; - reg [4 : 0] x__h24011, x__h67487; - reg [2 : 0] x__h13493, x__h23832; - reg [1 : 0] v__h67107, y_avValue_snd__h26149; - reg CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - wire [63 : 0] addr_offset__h13216, - addr_offset__h26929, - rdata___1__h26404, - rdata__h26202, - v__h13422, - v__h13671, - v__h18144, - v__h23761, - v__h25455, - v__h25474, - x__h26361, - y_avValue_fst__h26094, - y_avValue_fst__h26115, - y_avValue_fst__h26127, - y_avValue_fst__h26143, - y_avValue_fst__h26159, - y_avValue_fst__h26164, - y_avValue_fst__h26175, - y_avValue_fst__h26180, - y_avValue_fst__h26194; - wire [31 : 0] v_ie__h18147, - v_ip__h13674, - wdata32__h26930, - x__h23673, - x__h67110; - wire [9 : 0] source_id__h15665, - source_id__h15772, - source_id__h15845, - source_id__h15918, - source_id__h15991, - source_id__h16064, - source_id__h16137, - source_id__h16210, - source_id__h16283, - source_id__h16356, - source_id__h16429, - source_id__h16502, - source_id__h16575, - source_id__h16648, - source_id__h16721, - source_id__h16794, - source_id__h16867, - source_id__h16940, - source_id__h17013, - source_id__h17086, - source_id__h17159, - source_id__h17232, - source_id__h17305, - source_id__h17378, - source_id__h17451, - source_id__h17524, - source_id__h17597, - source_id__h17670, - source_id__h17743, - source_id__h17816, - source_id__h17889, - source_id__h20137, - source_id__h20313, - source_id__h20421, - source_id__h20529, - source_id__h20637, - source_id__h20745, - source_id__h20853, - source_id__h20961, - source_id__h21069, - source_id__h21177, - source_id__h21285, - source_id__h21393, - source_id__h21501, - source_id__h21609, - source_id__h21717, - source_id__h21825, - source_id__h21933, - source_id__h22041, - source_id__h22149, - source_id__h22257, - source_id__h22365, - source_id__h22473, - source_id__h22581, - source_id__h22689, - source_id__h22797, - source_id__h22905, - source_id__h23013, - source_id__h23121, - source_id__h23229, - source_id__h23337, - source_id__h23445, - source_id__h29475, - source_id__h30685, - source_id__h31895, - source_id__h33105, - source_id__h34315, - source_id__h35525, - source_id__h36735, - source_id__h37945, - source_id__h39155, - source_id__h40365, - source_id__h41575, - source_id__h42785, - source_id__h43995, - source_id__h45205, - source_id__h46415, - source_id__h47625, - source_id__h48835, - source_id__h50045, - source_id__h51255, - source_id__h52465, - source_id__h53675, - source_id__h54885, - source_id__h56095, - source_id__h57305, - source_id__h58515, - source_id__h59725, - source_id__h60935, - source_id__h62145, - source_id__h63355, - source_id__h64565, - source_id__h65775, - source_id__h67436, - source_id_base__h13630, - source_id_base__h28148; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71313, - b__h73318, - max_id__h23959; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71312, - a__h73317; - wire [1 : 0] rresp__h26203, - v__h26934, - v__h27094, - v__h27107, - v__h27942, - v__h27961, - v__h28125, - v__h28144, - v__h67144, - v__h67432, - v__h67476, - y_avValue_snd__h26095, - y_avValue_snd__h26116, - y_avValue_snd__h26128, - y_avValue_snd__h26144, - y_avValue_snd__h26160, - y_avValue_snd__h26165, - y_avValue_snd__h26176, - y_avValue_snd__h26181, - y_avValue_snd__h26195; - wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, - NOT_m_cfg_verbosity_read_ULE_1_5___d16, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982, - NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313, - NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321, - NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329, - NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337, - NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345, - NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353, - NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361, - NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242, - NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249, - NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257, - NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265, - 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_dfoo312, - _dfoo313, - _dfoo314, - _dfoo315, - _dfoo316, - _dfoo317, - _dfoo318, - _dfoo319, - _dfoo32, - _dfoo320, - _dfoo321, - _dfoo322, - _dfoo323, - _dfoo324, - _dfoo325, - _dfoo326, - _dfoo327, - _dfoo328, - _dfoo329, - _dfoo33, - _dfoo330, - _dfoo331, - _dfoo332, - _dfoo333, - _dfoo334, - _dfoo335, - _dfoo336, - _dfoo337, - _dfoo338, - _dfoo339, - _dfoo34, - _dfoo340, - _dfoo342, - _dfoo344, - _dfoo346, - _dfoo348, - _dfoo35, - _dfoo350, - _dfoo352, - _dfoo354, - _dfoo356, - _dfoo358, - _dfoo36, - _dfoo360, - _dfoo362, - _dfoo364, - _dfoo366, - _dfoo368, - _dfoo37, - _dfoo370, - _dfoo372, - _dfoo374, - _dfoo376, - _dfoo378, - _dfoo38, - _dfoo380, - _dfoo382, - _dfoo384, - _dfoo386, - _dfoo388, - _dfoo39, - _dfoo390, - _dfoo392, - _dfoo394, - _dfoo396, - _dfoo398, - _dfoo4, - _dfoo40, - _dfoo400, - _dfoo402, - _dfoo404, - _dfoo406, - _dfoo408, - _dfoo409, - _dfoo41, - _dfoo410, - _dfoo411, - _dfoo412, - _dfoo413, - _dfoo414, - _dfoo415, - _dfoo416, - _dfoo417, - _dfoo418, - _dfoo419, - _dfoo42, - _dfoo420, - _dfoo421, - _dfoo422, - _dfoo423, - _dfoo424, - _dfoo425, - _dfoo426, - _dfoo427, - _dfoo428, - _dfoo429, - _dfoo43, - _dfoo430, - _dfoo431, - _dfoo432, - _dfoo433, - _dfoo434, - _dfoo435, - _dfoo436, - _dfoo437, - _dfoo438, - _dfoo439, - _dfoo44, - _dfoo440, - _dfoo441, - _dfoo442, - _dfoo443, - _dfoo444, - _dfoo445, - _dfoo446, - _dfoo447, - _dfoo448, - _dfoo449, - _dfoo45, - _dfoo450, - _dfoo451, - _dfoo452, - _dfoo453, - _dfoo454, - _dfoo455, - _dfoo456, - _dfoo457, - _dfoo458, - _dfoo459, - _dfoo46, - _dfoo460, - _dfoo461, - _dfoo462, - _dfoo463, - _dfoo464, - _dfoo465, - _dfoo466, - _dfoo467, - _dfoo468, - _dfoo469, - _dfoo47, - _dfoo470, - _dfoo471, - _dfoo472, - _dfoo473, - _dfoo474, - _dfoo475, - _dfoo476, - _dfoo478, - _dfoo48, - _dfoo480, - _dfoo482, - _dfoo484, - _dfoo486, - _dfoo488, - _dfoo49, - _dfoo490, - _dfoo492, - _dfoo494, - _dfoo496, - _dfoo498, - _dfoo5, - _dfoo50, - _dfoo500, - _dfoo502, - _dfoo504, - _dfoo506, - _dfoo508, - _dfoo51, - _dfoo510, - _dfoo512, - _dfoo514, - _dfoo516, - _dfoo518, - _dfoo52, - _dfoo520, - _dfoo522, - _dfoo524, - _dfoo526, - _dfoo528, - _dfoo53, - _dfoo530, - _dfoo532, - _dfoo534, - _dfoo536, - _dfoo538, - _dfoo54, - _dfoo540, - _dfoo542, - _dfoo544, - _dfoo545, - _dfoo546, - _dfoo547, - _dfoo548, - _dfoo549, - _dfoo55, - _dfoo550, - _dfoo551, - _dfoo552, - _dfoo553, - _dfoo554, - _dfoo555, - _dfoo556, - _dfoo557, - _dfoo558, - _dfoo559, - _dfoo56, - _dfoo560, - _dfoo561, - _dfoo562, - _dfoo563, - _dfoo564, - _dfoo565, - _dfoo566, - _dfoo567, - _dfoo568, - _dfoo569, - _dfoo57, - _dfoo570, - _dfoo571, - _dfoo572, - _dfoo573, - _dfoo574, - _dfoo575, - _dfoo576, - _dfoo577, - _dfoo578, - _dfoo579, - _dfoo58, - _dfoo580, - _dfoo581, - _dfoo582, - _dfoo583, - _dfoo584, - _dfoo585, - _dfoo586, - _dfoo587, - _dfoo588, - _dfoo589, - _dfoo59, - _dfoo590, - _dfoo591, - _dfoo592, - _dfoo593, - _dfoo594, - _dfoo595, - _dfoo596, - _dfoo597, - _dfoo598, - _dfoo599, - _dfoo6, - _dfoo60, - _dfoo600, - _dfoo601, - _dfoo602, - _dfoo603, - _dfoo604, - _dfoo605, - _dfoo606, - _dfoo607, - _dfoo608, - _dfoo609, - _dfoo61, - _dfoo610, - _dfoo611, - _dfoo612, - _dfoo614, - _dfoo616, - _dfoo618, - _dfoo62, - _dfoo620, - _dfoo622, - _dfoo624, - _dfoo626, - _dfoo628, - _dfoo63, - _dfoo630, - _dfoo632, - _dfoo634, - _dfoo636, - _dfoo638, - _dfoo64, - _dfoo640, - _dfoo642, - _dfoo644, - _dfoo646, - _dfoo648, - _dfoo65, - _dfoo650, - _dfoo652, - _dfoo654, - _dfoo656, - _dfoo658, - _dfoo66, - _dfoo660, - _dfoo662, - _dfoo664, - _dfoo666, - _dfoo668, - _dfoo67, - _dfoo670, - _dfoo672, - _dfoo674, - _dfoo676, - _dfoo678, - _dfoo68, - _dfoo680, - _dfoo681, - _dfoo682, - _dfoo683, - _dfoo684, - _dfoo685, - _dfoo686, - _dfoo687, - _dfoo688, - _dfoo689, - _dfoo690, - _dfoo691, - _dfoo692, - _dfoo693, - _dfoo694, - _dfoo695, - _dfoo696, - _dfoo697, - _dfoo698, - _dfoo699, - _dfoo7, - _dfoo70, - _dfoo700, - _dfoo701, - _dfoo702, - _dfoo703, - _dfoo704, - _dfoo705, - _dfoo706, - _dfoo707, - _dfoo708, - _dfoo709, - _dfoo710, - _dfoo711, - _dfoo712, - _dfoo713, - _dfoo714, - _dfoo715, - _dfoo716, - _dfoo717, - _dfoo718, - _dfoo719, - _dfoo72, - _dfoo720, - _dfoo721, - _dfoo722, - _dfoo723, - _dfoo724, - _dfoo725, - _dfoo726, - _dfoo727, - _dfoo728, - _dfoo729, - _dfoo730, - _dfoo731, - _dfoo732, - _dfoo733, - _dfoo734, - _dfoo735, - _dfoo736, - _dfoo737, - _dfoo738, - _dfoo739, - _dfoo74, - _dfoo740, - _dfoo741, - _dfoo742, - _dfoo743, - _dfoo744, - _dfoo745, - _dfoo746, - _dfoo747, - _dfoo748, - _dfoo750, - _dfoo752, - _dfoo754, - _dfoo756, - _dfoo758, - _dfoo76, - _dfoo760, - _dfoo762, - _dfoo764, - _dfoo766, - _dfoo768, - _dfoo770, - _dfoo772, - _dfoo774, - _dfoo776, - _dfoo778, - _dfoo78, - _dfoo780, - _dfoo782, - _dfoo784, - _dfoo786, - _dfoo788, - _dfoo790, - _dfoo792, - _dfoo794, - _dfoo796, - _dfoo798, - _dfoo8, - _dfoo80, - _dfoo800, - _dfoo802, - _dfoo804, - _dfoo806, - _dfoo808, - _dfoo810, - _dfoo812, - _dfoo814, - _dfoo816, - _dfoo817, - _dfoo818, - _dfoo819, - _dfoo82, - _dfoo820, - _dfoo821, - _dfoo822, - _dfoo823, - _dfoo824, - _dfoo825, - _dfoo826, - _dfoo827, - _dfoo828, - _dfoo829, - _dfoo830, - _dfoo831, - _dfoo832, - _dfoo833, - _dfoo834, - _dfoo835, - _dfoo836, - _dfoo837, - _dfoo838, - _dfoo839, - _dfoo84, - _dfoo840, - _dfoo841, - _dfoo842, - _dfoo843, - _dfoo844, - _dfoo845, - _dfoo846, - _dfoo847, - _dfoo848, - _dfoo849, - _dfoo850, - _dfoo851, - _dfoo852, - _dfoo853, - _dfoo854, - _dfoo855, - _dfoo856, - _dfoo857, - _dfoo858, - _dfoo859, - _dfoo86, - _dfoo860, - _dfoo861, - _dfoo862, - _dfoo863, - _dfoo864, - _dfoo865, - _dfoo866, - _dfoo867, - _dfoo868, - _dfoo869, - _dfoo870, - _dfoo871, - _dfoo872, - _dfoo873, - _dfoo874, - _dfoo875, - _dfoo876, - _dfoo877, - _dfoo878, - _dfoo879, - _dfoo88, - _dfoo880, - _dfoo881, - _dfoo882, - _dfoo883, - _dfoo884, - _dfoo886, - _dfoo888, - _dfoo890, - _dfoo892, - _dfoo894, - _dfoo896, - _dfoo898, - _dfoo9, - _dfoo90, - _dfoo900, - _dfoo902, - _dfoo904, - _dfoo906, - _dfoo908, - _dfoo910, - _dfoo912, - _dfoo914, - _dfoo916, - _dfoo918, - _dfoo92, - _dfoo920, - _dfoo922, - _dfoo924, - _dfoo926, - _dfoo928, - _dfoo930, - _dfoo932, - _dfoo934, - _dfoo936, - _dfoo938, - _dfoo94, - _dfoo940, - _dfoo942, - _dfoo944, - _dfoo946, - _dfoo948, - _dfoo950, - _dfoo952, - _dfoo953, - _dfoo954, - _dfoo955, - _dfoo956, - _dfoo957, - _dfoo958, - _dfoo959, - _dfoo96, - _dfoo960, - _dfoo961, - _dfoo962, - _dfoo963, - _dfoo964, - _dfoo965, - _dfoo966, - _dfoo967, - _dfoo968, - _dfoo969, - _dfoo970, - _dfoo971, - _dfoo972, - _dfoo973, - _dfoo974, - _dfoo975, - _dfoo976, - _dfoo977, - _dfoo978, - _dfoo979, - _dfoo98, - _dfoo980, - _dfoo981, - _dfoo982, - _dfoo983, - _dfoo984, - _dfoo985, - _dfoo986, - _dfoo987, - _dfoo988, - _dfoo989, - _dfoo990, - _dfoo991, - _dfoo992, - _dfoo993, - _dfoo994, - _dfoo995, - _dfoo996, - _dfoo997, - _dfoo998, - _dfoo999, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, - m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method show_PLIC_state - assign RDY_show_PLIC_state = 1'd1 ; - assign CAN_FIRE_show_PLIC_state = 1'd1 ; - assign WILL_FIRE_show_PLIC_state = EN_show_PLIC_state ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // action method v_sources_0_m_interrupt_req - assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - - // action method v_sources_1_m_interrupt_req - assign CAN_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - - // action method v_sources_2_m_interrupt_req - assign CAN_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - - // action method v_sources_3_m_interrupt_req - assign CAN_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - - // action method v_sources_4_m_interrupt_req - assign CAN_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - - // action method v_sources_5_m_interrupt_req - assign CAN_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - - // action method v_sources_6_m_interrupt_req - assign CAN_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - - // action method v_sources_7_m_interrupt_req - assign CAN_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - - // action method v_sources_8_m_interrupt_req - assign CAN_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - - // action method v_sources_9_m_interrupt_req - assign CAN_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - - // action method v_sources_10_m_interrupt_req - assign CAN_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - - // action method v_sources_11_m_interrupt_req - assign CAN_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - - // action method v_sources_12_m_interrupt_req - assign CAN_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - - // action method v_sources_13_m_interrupt_req - assign CAN_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - - // action method v_sources_14_m_interrupt_req - assign CAN_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - - // action method v_sources_15_m_interrupt_req - assign CAN_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - - // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71312 > m_vrg_target_threshold_0 ; - - // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73317 > m_vrg_target_threshold_1 ; - - // submodule m_f_reset_reqs - FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_reqs$ENQ), - .DEQ(m_f_reset_reqs$DEQ), - .CLR(m_f_reset_reqs$CLR), - .FULL_N(m_f_reset_reqs$FULL_N), - .EMPTY_N(m_f_reset_reqs$EMPTY_N)); - - // submodule m_f_reset_rsps - FIFO20 #(.guarded(32'd1)) m_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_rsps$ENQ), - .DEQ(m_f_reset_rsps$DEQ), - .CLR(m_f_reset_rsps$CLR), - .FULL_N(m_f_reset_rsps$FULL_N), - .EMPTY_N(m_f_reset_rsps$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_addr$D_IN), - .ENQ(m_slave_xactor_f_rd_addr$ENQ), - .DEQ(m_slave_xactor_f_rd_addr$DEQ), - .CLR(m_slave_xactor_f_rd_addr$CLR), - .D_OUT(m_slave_xactor_f_rd_addr$D_OUT), - .FULL_N(m_slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_data$D_IN), - .ENQ(m_slave_xactor_f_rd_data$ENQ), - .DEQ(m_slave_xactor_f_rd_data$DEQ), - .CLR(m_slave_xactor_f_rd_data$CLR), - .D_OUT(m_slave_xactor_f_rd_data$D_OUT), - .FULL_N(m_slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_addr$D_IN), - .ENQ(m_slave_xactor_f_wr_addr$ENQ), - .DEQ(m_slave_xactor_f_wr_addr$DEQ), - .CLR(m_slave_xactor_f_wr_addr$CLR), - .D_OUT(m_slave_xactor_f_wr_addr$D_OUT), - .FULL_N(m_slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_data$D_IN), - .ENQ(m_slave_xactor_f_wr_data$ENQ), - .DEQ(m_slave_xactor_f_wr_data$DEQ), - .CLR(m_slave_xactor_f_wr_data$CLR), - .D_OUT(m_slave_xactor_f_wr_data$D_OUT), - .FULL_N(m_slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_resp$D_IN), - .ENQ(m_slave_xactor_f_wr_resp$ENQ), - .DEQ(m_slave_xactor_f_wr_resp$DEQ), - .CLR(m_slave_xactor_f_wr_resp$CLR), - .D_OUT(m_slave_xactor_f_wr_resp$D_OUT), - .FULL_N(m_slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = - m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - - // rule RL_m_rl_process_rd_req - assign CAN_FIRE_RL_m_rl_process_rd_req = - m_slave_xactor_f_rd_addr$EMPTY_N && - m_slave_xactor_f_rd_data$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - - // rule RL_m_rl_process_wr_req - assign CAN_FIRE_RL_m_rl_process_wr_req = - m_slave_xactor_f_wr_addr$EMPTY_N && - m_slave_xactor_f_wr_data$EMPTY_N && - m_slave_xactor_f_wr_resp$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_wr_req = - CAN_FIRE_RL_m_rl_process_wr_req && - !WILL_FIRE_RL_m_rl_process_rd_req ; - - // inputs to muxes for submodule ports - assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; - assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; - assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; - assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; - assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; - assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; - assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; - assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; - assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; - assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; - assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; - assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; - assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; - assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; - assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; - assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; - assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; - assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; - assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; - assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; - assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ; - assign MUX_m_vvrg_ie_0_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ; - assign MUX_m_vvrg_ie_0_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ; - assign MUX_m_vvrg_ie_0_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ; - assign MUX_m_vvrg_ie_0_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ; - assign MUX_m_vvrg_ie_0_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ; - assign MUX_m_vvrg_ie_0_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ; - assign MUX_m_vvrg_ie_0_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ; - assign MUX_m_vvrg_ie_0_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ; - assign MUX_m_vvrg_ie_0_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ; - assign MUX_m_vvrg_ie_0_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ; - assign MUX_m_vvrg_ie_0_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ; - assign MUX_m_vvrg_ie_0_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ; - assign MUX_m_vvrg_ie_0_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ; - assign MUX_m_vvrg_ie_0_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ; - assign MUX_m_vvrg_ie_0_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ; - assign MUX_m_vvrg_ie_1_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ; - assign MUX_m_vvrg_ie_1_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ; - assign MUX_m_vvrg_ie_1_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ; - assign MUX_m_vvrg_ie_1_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ; - assign MUX_m_vvrg_ie_1_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ; - assign MUX_m_vvrg_ie_1_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ; - assign MUX_m_vvrg_ie_1_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ; - assign MUX_m_vvrg_ie_1_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ; - assign MUX_m_vvrg_ie_1_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ; - assign MUX_m_vvrg_ie_1_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ; - assign MUX_m_vvrg_ie_1_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ; - assign MUX_m_vvrg_ie_1_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ; - assign MUX_m_vvrg_ie_1_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ; - assign MUX_m_vvrg_ie_1_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ; - assign MUX_m_vvrg_ie_1_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ; - assign MUX_m_vvrg_ie_1_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ; - assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; - assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2040 ; - assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2038 ; - assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2020 ; - assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2018 ; - assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2016 ; - assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2014 ; - assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2012 ; - assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2010 ; - assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2008 ; - assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2036 ; - assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2034 ; - assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2032 ; - assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2030 ; - assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2028 ; - assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2026 ; - assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2024 ; - assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2022 ; - assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2006 ; - assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2004 ; - assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1986 ; - assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1984 ; - assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1982 ; - assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1980 ; - assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1978 ; - assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1976 ; - assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1974 ; - assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2002 ; - assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2000 ; - assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1998 ; - assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1996 ; - assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1994 ; - assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1992 ; - assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1990 ; - assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1988 ; - - // register m_cfg_verbosity - assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign m_cfg_verbosity$EN = EN_set_verbosity ; - - // register m_rg_addr_base - assign m_rg_addr_base$D_IN = set_addr_map_addr_base ; - assign m_rg_addr_base$EN = EN_set_addr_map ; - - // register m_rg_addr_lim - assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign m_rg_addr_lim$EN = EN_set_addr_map ; - - // register m_vrg_servicing_source_0 - assign m_vrg_servicing_source_0$D_IN = - MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_servicing_source_1 - assign m_vrg_servicing_source_1$D_IN = - MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_0 - assign m_vrg_source_busy_0$D_IN = - !MUX_m_vrg_source_busy_0$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_1 - assign m_vrg_source_busy_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_10 - assign m_vrg_source_busy_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_11 - assign m_vrg_source_busy_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_12 - assign m_vrg_source_busy_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_13 - assign m_vrg_source_busy_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_14 - assign m_vrg_source_busy_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_15 - assign m_vrg_source_busy_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_16 - assign m_vrg_source_busy_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_2 - assign m_vrg_source_busy_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_3 - assign m_vrg_source_busy_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_4 - assign m_vrg_source_busy_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_5 - assign m_vrg_source_busy_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_6 - assign m_vrg_source_busy_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_7 - assign m_vrg_source_busy_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_8 - assign m_vrg_source_busy_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_9 - assign m_vrg_source_busy_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_0 - assign m_vrg_source_ip_0$D_IN = 1'd0 ; - assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_1 - assign m_vrg_source_ip_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_0_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_1$EN = - !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_10 - assign m_vrg_source_ip_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_9_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_10$EN = - !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_11 - assign m_vrg_source_ip_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_10_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_11$EN = - !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_12 - assign m_vrg_source_ip_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_11_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_12$EN = - !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_13 - assign m_vrg_source_ip_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_12_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_13$EN = - !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_14 - assign m_vrg_source_ip_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_13_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_14$EN = - !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_15 - assign m_vrg_source_ip_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_14_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_15$EN = - !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_16 - assign m_vrg_source_ip_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_15_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_16$EN = - !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_2 - assign m_vrg_source_ip_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_1_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_2$EN = - !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_3 - assign m_vrg_source_ip_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_2_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_3$EN = - !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_4 - assign m_vrg_source_ip_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_3_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_4$EN = - !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_5 - assign m_vrg_source_ip_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_4_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_5$EN = - !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_6 - assign m_vrg_source_ip_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_5_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_6$EN = - !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_7 - assign m_vrg_source_ip_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_6_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_7$EN = - !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_8 - assign m_vrg_source_ip_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_7_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_8$EN = - !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_9 - assign m_vrg_source_ip_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_8_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_9$EN = - !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_0 - assign m_vrg_source_prio_0$D_IN = - MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_1 - assign m_vrg_source_prio_1$D_IN = - MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_10 - assign m_vrg_source_prio_10$D_IN = - MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_11 - assign m_vrg_source_prio_11$D_IN = - MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_12 - assign m_vrg_source_prio_12$D_IN = - MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_13 - assign m_vrg_source_prio_13$D_IN = - MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_14 - assign m_vrg_source_prio_14$D_IN = - MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_15 - assign m_vrg_source_prio_15$D_IN = - MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_16 - assign m_vrg_source_prio_16$D_IN = - MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_2 - assign m_vrg_source_prio_2$D_IN = - MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_3 - assign m_vrg_source_prio_3$D_IN = - MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_4 - assign m_vrg_source_prio_4$D_IN = - MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_5 - assign m_vrg_source_prio_5$D_IN = - MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_6 - assign m_vrg_source_prio_6$D_IN = - MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_7 - assign m_vrg_source_prio_7$D_IN = - MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_8 - assign m_vrg_source_prio_8$D_IN = - MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_9 - assign m_vrg_source_prio_9$D_IN = - MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_0 - assign m_vrg_target_threshold_0$D_IN = - MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_1 - assign m_vrg_target_threshold_1$D_IN = - MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_0 - assign m_vvrg_ie_0_0$D_IN = - MUX_m_vvrg_ie_0_0$write_1__SEL_1 && - MUX_m_vvrg_ie_0_0$write_1__VAL_1 ; - assign m_vvrg_ie_0_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_1 - assign m_vvrg_ie_0_1$D_IN = - MUX_m_vvrg_ie_0_1$write_1__SEL_1 && - MUX_m_vvrg_ie_0_1$write_1__VAL_1 ; - assign m_vvrg_ie_0_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_10 - assign m_vvrg_ie_0_10$D_IN = - MUX_m_vvrg_ie_0_10$write_1__SEL_1 && - MUX_m_vvrg_ie_0_10$write_1__VAL_1 ; - assign m_vvrg_ie_0_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_11 - assign m_vvrg_ie_0_11$D_IN = - MUX_m_vvrg_ie_0_11$write_1__SEL_1 && - MUX_m_vvrg_ie_0_11$write_1__VAL_1 ; - assign m_vvrg_ie_0_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_12 - assign m_vvrg_ie_0_12$D_IN = - MUX_m_vvrg_ie_0_12$write_1__SEL_1 && - MUX_m_vvrg_ie_0_12$write_1__VAL_1 ; - assign m_vvrg_ie_0_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_13 - assign m_vvrg_ie_0_13$D_IN = - MUX_m_vvrg_ie_0_13$write_1__SEL_1 && - MUX_m_vvrg_ie_0_13$write_1__VAL_1 ; - assign m_vvrg_ie_0_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_14 - assign m_vvrg_ie_0_14$D_IN = - MUX_m_vvrg_ie_0_14$write_1__SEL_1 && - MUX_m_vvrg_ie_0_14$write_1__VAL_1 ; - assign m_vvrg_ie_0_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_15 - assign m_vvrg_ie_0_15$D_IN = - MUX_m_vvrg_ie_0_15$write_1__SEL_1 && - MUX_m_vvrg_ie_0_15$write_1__VAL_1 ; - assign m_vvrg_ie_0_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_16 - assign m_vvrg_ie_0_16$D_IN = - MUX_m_vvrg_ie_0_16$write_1__SEL_1 && - MUX_m_vvrg_ie_0_16$write_1__VAL_1 ; - assign m_vvrg_ie_0_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_2 - assign m_vvrg_ie_0_2$D_IN = - MUX_m_vvrg_ie_0_2$write_1__SEL_1 && - MUX_m_vvrg_ie_0_2$write_1__VAL_1 ; - assign m_vvrg_ie_0_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_3 - assign m_vvrg_ie_0_3$D_IN = - MUX_m_vvrg_ie_0_3$write_1__SEL_1 && - MUX_m_vvrg_ie_0_3$write_1__VAL_1 ; - assign m_vvrg_ie_0_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_4 - assign m_vvrg_ie_0_4$D_IN = - MUX_m_vvrg_ie_0_4$write_1__SEL_1 && - MUX_m_vvrg_ie_0_4$write_1__VAL_1 ; - assign m_vvrg_ie_0_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_5 - assign m_vvrg_ie_0_5$D_IN = - MUX_m_vvrg_ie_0_5$write_1__SEL_1 && - MUX_m_vvrg_ie_0_5$write_1__VAL_1 ; - assign m_vvrg_ie_0_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_6 - assign m_vvrg_ie_0_6$D_IN = - MUX_m_vvrg_ie_0_6$write_1__SEL_1 && - MUX_m_vvrg_ie_0_6$write_1__VAL_1 ; - assign m_vvrg_ie_0_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_7 - assign m_vvrg_ie_0_7$D_IN = - MUX_m_vvrg_ie_0_7$write_1__SEL_1 && - MUX_m_vvrg_ie_0_7$write_1__VAL_1 ; - assign m_vvrg_ie_0_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_8 - assign m_vvrg_ie_0_8$D_IN = - MUX_m_vvrg_ie_0_8$write_1__SEL_1 && - MUX_m_vvrg_ie_0_8$write_1__VAL_1 ; - assign m_vvrg_ie_0_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_9 - assign m_vvrg_ie_0_9$D_IN = - MUX_m_vvrg_ie_0_9$write_1__SEL_1 && - MUX_m_vvrg_ie_0_9$write_1__VAL_1 ; - assign m_vvrg_ie_0_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_0 - assign m_vvrg_ie_1_0$D_IN = - MUX_m_vvrg_ie_1_0$write_1__SEL_1 && - MUX_m_vvrg_ie_1_0$write_1__VAL_1 ; - assign m_vvrg_ie_1_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_1 - assign m_vvrg_ie_1_1$D_IN = - MUX_m_vvrg_ie_1_1$write_1__SEL_1 && - MUX_m_vvrg_ie_1_1$write_1__VAL_1 ; - assign m_vvrg_ie_1_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_10 - assign m_vvrg_ie_1_10$D_IN = - MUX_m_vvrg_ie_1_10$write_1__SEL_1 && - MUX_m_vvrg_ie_1_10$write_1__VAL_1 ; - assign m_vvrg_ie_1_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_11 - assign m_vvrg_ie_1_11$D_IN = - MUX_m_vvrg_ie_1_11$write_1__SEL_1 && - MUX_m_vvrg_ie_1_11$write_1__VAL_1 ; - assign m_vvrg_ie_1_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_12 - assign m_vvrg_ie_1_12$D_IN = - MUX_m_vvrg_ie_1_12$write_1__SEL_1 && - MUX_m_vvrg_ie_1_12$write_1__VAL_1 ; - assign m_vvrg_ie_1_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_13 - assign m_vvrg_ie_1_13$D_IN = - MUX_m_vvrg_ie_1_13$write_1__SEL_1 && - MUX_m_vvrg_ie_1_13$write_1__VAL_1 ; - assign m_vvrg_ie_1_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_14 - assign m_vvrg_ie_1_14$D_IN = - MUX_m_vvrg_ie_1_14$write_1__SEL_1 && - MUX_m_vvrg_ie_1_14$write_1__VAL_1 ; - assign m_vvrg_ie_1_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_15 - assign m_vvrg_ie_1_15$D_IN = - MUX_m_vvrg_ie_1_15$write_1__SEL_1 && - MUX_m_vvrg_ie_1_15$write_1__VAL_1 ; - assign m_vvrg_ie_1_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_16 - assign m_vvrg_ie_1_16$D_IN = - MUX_m_vvrg_ie_1_16$write_1__SEL_1 && - MUX_m_vvrg_ie_1_16$write_1__VAL_1 ; - assign m_vvrg_ie_1_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_2 - assign m_vvrg_ie_1_2$D_IN = - MUX_m_vvrg_ie_1_2$write_1__SEL_1 && - MUX_m_vvrg_ie_1_2$write_1__VAL_1 ; - assign m_vvrg_ie_1_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_3 - assign m_vvrg_ie_1_3$D_IN = - MUX_m_vvrg_ie_1_3$write_1__SEL_1 && - MUX_m_vvrg_ie_1_3$write_1__VAL_1 ; - assign m_vvrg_ie_1_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_4 - assign m_vvrg_ie_1_4$D_IN = - MUX_m_vvrg_ie_1_4$write_1__SEL_1 && - MUX_m_vvrg_ie_1_4$write_1__VAL_1 ; - assign m_vvrg_ie_1_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_5 - assign m_vvrg_ie_1_5$D_IN = - MUX_m_vvrg_ie_1_5$write_1__SEL_1 && - MUX_m_vvrg_ie_1_5$write_1__VAL_1 ; - assign m_vvrg_ie_1_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_6 - assign m_vvrg_ie_1_6$D_IN = - MUX_m_vvrg_ie_1_6$write_1__SEL_1 && - MUX_m_vvrg_ie_1_6$write_1__VAL_1 ; - assign m_vvrg_ie_1_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_7 - assign m_vvrg_ie_1_7$D_IN = - MUX_m_vvrg_ie_1_7$write_1__SEL_1 && - MUX_m_vvrg_ie_1_7$write_1__VAL_1 ; - assign m_vvrg_ie_1_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_8 - assign m_vvrg_ie_1_8$D_IN = - MUX_m_vvrg_ie_1_8$write_1__SEL_1 && - MUX_m_vvrg_ie_1_8$write_1__VAL_1 ; - assign m_vvrg_ie_1_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_9 - assign m_vvrg_ie_1_9$D_IN = - MUX_m_vvrg_ie_1_9$write_1__SEL_1 && - MUX_m_vvrg_ie_1_9$write_1__VAL_1 ; - assign m_vvrg_ie_1_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 || - WILL_FIRE_RL_m_rl_reset ; - - // submodule m_f_reset_reqs - assign m_f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign m_f_reset_reqs$DEQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_reqs$CLR = 1'b0 ; - - // submodule m_f_reset_rsps - assign m_f_reset_rsps$ENQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign m_f_reset_rsps$CLR = 1'b0 ; - - // submodule m_slave_xactor_f_rd_addr - assign m_slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign m_slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ; - assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_rd_data - assign m_slave_xactor_f_rd_data$D_IN = - { m_slave_xactor_f_rd_addr$D_OUT[96:93], - x__h26361, - rresp__h26203, - 1'd1 } ; - assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ; - assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_addr - assign m_slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign m_slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ; - assign m_slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_data - assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign m_slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; - assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_resp - assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26934 } ; - assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; - assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ; - - // remaining internal signals - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 : - ((x__h23673 == 32'h00200000) ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 : - x__h23673 != 32'h00200004 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 || - x__h24011 != 5'd0) ; - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - addr_offset__h13216[11:2] == 10'd0 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 : - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67110 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67110 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26929[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 = - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - 5'd2 : - (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ; - assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200000 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30685 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31895 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33105 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34315 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35525 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36735 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37945 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39155 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40365 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41575 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42785 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43995 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45205 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46415 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47625 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48835 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50045 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51255 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52465 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53675 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54885 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56095 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57305 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58515 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59725 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60935 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62145 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63355 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64565 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65775 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29475 <= 10'd16 ; - assign NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313 = - !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321 = - !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_11 != - v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329 = - !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_12 != - v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337 = - !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_13 != - v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345 = - !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_14 != - v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353 = - !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_15 != - v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361 = - !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_16 != - v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242 = - !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249 = - !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257 = - !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265 = - !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273 = - !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281 = - !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289 = - !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297 = - !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305 = - !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; - assign _dfoo1 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo10 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo100 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo32 ; - assign _dfoo1000 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo932 ; - assign _dfoo1001 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo865 ; - assign _dfoo1002 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo934 ; - assign _dfoo1003 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo867 ; - assign _dfoo1004 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo936 ; - assign _dfoo1005 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo869 ; - assign _dfoo1006 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo938 ; - assign _dfoo1007 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo871 ; - assign _dfoo1008 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo940 ; - assign _dfoo1009 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo873 ; - assign _dfoo1010 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo942 ; - assign _dfoo1011 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo875 ; - assign _dfoo1012 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo944 ; - assign _dfoo1013 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo877 ; - assign _dfoo1014 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo946 ; - assign _dfoo1015 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo879 ; - assign _dfoo1016 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo948 ; - assign _dfoo1017 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo881 ; - assign _dfoo1018 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo950 ; - assign _dfoo1019 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo883 ; - assign _dfoo102 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo34 ; - assign _dfoo1020 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo952 ; - assign _dfoo1022 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo954 ; - assign _dfoo1024 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo956 ; - assign _dfoo1026 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo958 ; - assign _dfoo1028 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo960 ; - assign _dfoo1030 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo962 ; - assign _dfoo1032 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo964 ; - assign _dfoo1034 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo966 ; - assign _dfoo1036 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo968 ; - assign _dfoo1038 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo970 ; - assign _dfoo104 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo36 ; - assign _dfoo1040 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo972 ; - assign _dfoo1042 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo974 ; - assign _dfoo1044 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo976 ; - assign _dfoo1046 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo978 ; - assign _dfoo1048 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo980 ; - assign _dfoo1050 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo982 ; - assign _dfoo1052 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo984 ; - assign _dfoo1054 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo986 ; - assign _dfoo1056 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo988 ; - assign _dfoo1058 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo990 ; - assign _dfoo106 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo38 ; - assign _dfoo1060 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo992 ; - assign _dfoo1062 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo994 ; - assign _dfoo1064 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo996 ; - assign _dfoo1066 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo998 ; - assign _dfoo1068 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1000 ; - assign _dfoo1070 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1002 ; - assign _dfoo1072 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1004 ; - assign _dfoo1074 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1006 ; - assign _dfoo1076 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1008 ; - assign _dfoo1078 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1010 ; - assign _dfoo108 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo40 ; - assign _dfoo1080 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1012 ; - assign _dfoo1082 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1014 ; - assign _dfoo1084 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1016 ; - assign _dfoo1086 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1018 ; - assign _dfoo1088 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1020 ; - assign _dfoo1089 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo953 ; - assign _dfoo1090 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1022 ; - assign _dfoo1091 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo955 ; - assign _dfoo1092 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1024 ; - assign _dfoo1093 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo957 ; - assign _dfoo1094 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1026 ; - assign _dfoo1095 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo959 ; - assign _dfoo1096 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1028 ; - assign _dfoo1097 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo961 ; - assign _dfoo1098 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1030 ; - assign _dfoo1099 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo963 ; - assign _dfoo11 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo110 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo42 ; - assign _dfoo1100 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1032 ; - assign _dfoo1101 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo965 ; - assign _dfoo1102 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1034 ; - assign _dfoo1103 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo967 ; - assign _dfoo1104 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1036 ; - assign _dfoo1105 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo969 ; - assign _dfoo1106 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1038 ; - assign _dfoo1107 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo971 ; - assign _dfoo1108 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1040 ; - assign _dfoo1109 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo973 ; - assign _dfoo1110 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1042 ; - assign _dfoo1111 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo975 ; - assign _dfoo1112 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1044 ; - assign _dfoo1113 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo977 ; - assign _dfoo1114 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1046 ; - assign _dfoo1115 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo979 ; - assign _dfoo1116 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1048 ; - assign _dfoo1117 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo981 ; - assign _dfoo1118 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1050 ; - assign _dfoo1119 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo983 ; - assign _dfoo112 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo44 ; - assign _dfoo1120 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1052 ; - assign _dfoo1121 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo985 ; - assign _dfoo1122 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1054 ; - assign _dfoo1123 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo987 ; - assign _dfoo1124 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1056 ; - assign _dfoo1125 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo989 ; - assign _dfoo1126 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1058 ; - assign _dfoo1127 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo991 ; - assign _dfoo1128 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1060 ; - assign _dfoo1129 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo993 ; - assign _dfoo1130 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1062 ; - assign _dfoo1131 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo995 ; - assign _dfoo1132 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1064 ; - assign _dfoo1133 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo997 ; - assign _dfoo1134 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1066 ; - assign _dfoo1135 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo999 ; - assign _dfoo1136 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1068 ; - assign _dfoo1137 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1001 ; - assign _dfoo1138 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1070 ; - assign _dfoo1139 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1003 ; - assign _dfoo114 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo46 ; - assign _dfoo1140 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1072 ; - assign _dfoo1141 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1005 ; - assign _dfoo1142 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1074 ; - assign _dfoo1143 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1007 ; - assign _dfoo1144 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1076 ; - assign _dfoo1145 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1009 ; - assign _dfoo1146 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1078 ; - assign _dfoo1147 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1011 ; - assign _dfoo1148 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1080 ; - assign _dfoo1149 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1013 ; - assign _dfoo1150 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1082 ; - assign _dfoo1151 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1015 ; - assign _dfoo1152 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1084 ; - assign _dfoo1153 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1017 ; - assign _dfoo1154 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1086 ; - assign _dfoo1155 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1019 ; - assign _dfoo1156 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1088 ; - assign _dfoo1158 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1090 ; - assign _dfoo116 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo48 ; - assign _dfoo1160 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1092 ; - assign _dfoo1162 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1094 ; - assign _dfoo1164 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1096 ; - assign _dfoo1166 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1098 ; - assign _dfoo1168 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1100 ; - assign _dfoo1170 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1102 ; - assign _dfoo1172 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1104 ; - assign _dfoo1174 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1106 ; - assign _dfoo1176 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1108 ; - assign _dfoo1178 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1110 ; - assign _dfoo118 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo50 ; - assign _dfoo1180 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1112 ; - assign _dfoo1182 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1114 ; - assign _dfoo1184 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1116 ; - assign _dfoo1186 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1118 ; - assign _dfoo1188 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1120 ; - assign _dfoo1190 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1122 ; - assign _dfoo1192 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1124 ; - assign _dfoo1194 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1126 ; - assign _dfoo1196 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1128 ; - assign _dfoo1198 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1130 ; - assign _dfoo12 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo120 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo52 ; - assign _dfoo1200 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1132 ; - assign _dfoo1202 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1134 ; - assign _dfoo1204 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1136 ; - assign _dfoo1206 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1138 ; - assign _dfoo1208 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1140 ; - assign _dfoo1210 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1142 ; - assign _dfoo1212 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1144 ; - assign _dfoo1214 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1146 ; - assign _dfoo1216 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1148 ; - assign _dfoo1218 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1150 ; - assign _dfoo122 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo54 ; - assign _dfoo1220 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1152 ; - assign _dfoo1222 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1154 ; - assign _dfoo1224 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1156 ; - assign _dfoo1225 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1089 ; - assign _dfoo1226 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1158 ; - assign _dfoo1227 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1091 ; - assign _dfoo1228 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1160 ; - assign _dfoo1229 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1093 ; - assign _dfoo1230 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1162 ; - assign _dfoo1231 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1095 ; - assign _dfoo1232 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1164 ; - assign _dfoo1233 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1097 ; - assign _dfoo1234 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1166 ; - assign _dfoo1235 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1099 ; - assign _dfoo1236 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1168 ; - assign _dfoo1237 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1101 ; - assign _dfoo1238 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1170 ; - assign _dfoo1239 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1103 ; - assign _dfoo124 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo56 ; - assign _dfoo1240 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1172 ; - assign _dfoo1241 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1105 ; - assign _dfoo1242 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1174 ; - assign _dfoo1243 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1107 ; - assign _dfoo1244 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1176 ; - assign _dfoo1245 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1109 ; - assign _dfoo1246 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1178 ; - assign _dfoo1247 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1111 ; - assign _dfoo1248 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1180 ; - assign _dfoo1249 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1113 ; - assign _dfoo1250 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1182 ; - assign _dfoo1251 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1115 ; - assign _dfoo1252 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1184 ; - assign _dfoo1253 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1117 ; - assign _dfoo1254 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1186 ; - assign _dfoo1255 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1119 ; - assign _dfoo1256 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1188 ; - assign _dfoo1257 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1121 ; - assign _dfoo1258 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1190 ; - assign _dfoo1259 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1123 ; - assign _dfoo126 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo58 ; - assign _dfoo1260 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1192 ; - assign _dfoo1261 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1125 ; - assign _dfoo1262 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1194 ; - assign _dfoo1263 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1127 ; - assign _dfoo1264 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1196 ; - assign _dfoo1265 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1129 ; - assign _dfoo1266 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1198 ; - assign _dfoo1267 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1131 ; - assign _dfoo1268 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1200 ; - assign _dfoo1269 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1133 ; - assign _dfoo1270 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1202 ; - assign _dfoo1271 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1135 ; - assign _dfoo1272 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1204 ; - assign _dfoo1273 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1137 ; - assign _dfoo1274 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1206 ; - assign _dfoo1275 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1139 ; - assign _dfoo1276 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1208 ; - assign _dfoo1277 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1141 ; - assign _dfoo1278 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1210 ; - assign _dfoo1279 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1143 ; - assign _dfoo128 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo60 ; - assign _dfoo1280 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1212 ; - assign _dfoo1281 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1145 ; - assign _dfoo1282 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1214 ; - assign _dfoo1283 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1147 ; - assign _dfoo1284 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1216 ; - assign _dfoo1285 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1149 ; - assign _dfoo1286 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1218 ; - assign _dfoo1287 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1151 ; - assign _dfoo1288 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1220 ; - assign _dfoo1289 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1153 ; - assign _dfoo1290 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1222 ; - assign _dfoo1291 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1155 ; - assign _dfoo1292 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1224 ; - assign _dfoo1294 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1226 ; - assign _dfoo1296 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1228 ; - assign _dfoo1298 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1230 ; - assign _dfoo13 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo130 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo62 ; - assign _dfoo1300 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1232 ; - assign _dfoo1302 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1234 ; - assign _dfoo1304 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1236 ; - assign _dfoo1306 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1238 ; - assign _dfoo1308 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1240 ; - assign _dfoo1310 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1242 ; - assign _dfoo1312 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1244 ; - assign _dfoo1314 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1246 ; - assign _dfoo1316 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1248 ; - assign _dfoo1318 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1250 ; - assign _dfoo132 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo64 ; - assign _dfoo1320 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1252 ; - assign _dfoo1322 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1254 ; - assign _dfoo1324 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1256 ; - assign _dfoo1326 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1258 ; - assign _dfoo1328 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1260 ; - assign _dfoo1330 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1262 ; - assign _dfoo1332 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1264 ; - assign _dfoo1334 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1266 ; - assign _dfoo1336 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1268 ; - assign _dfoo1338 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1270 ; - assign _dfoo134 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo66 ; - assign _dfoo1340 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1272 ; - assign _dfoo1342 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1274 ; - assign _dfoo1344 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1276 ; - assign _dfoo1346 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1278 ; - assign _dfoo1348 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1280 ; - assign _dfoo1350 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1282 ; - assign _dfoo1352 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1284 ; - assign _dfoo1354 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1286 ; - assign _dfoo1356 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1288 ; - assign _dfoo1358 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1290 ; - assign _dfoo136 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo68 ; - assign _dfoo1360 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1292 ; - assign _dfoo1361 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1225 ; - assign _dfoo1362 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1294 ; - assign _dfoo1363 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1227 ; - assign _dfoo1364 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1296 ; - assign _dfoo1365 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1229 ; - assign _dfoo1366 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1298 ; - assign _dfoo1367 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1231 ; - assign _dfoo1368 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1300 ; - assign _dfoo1369 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1233 ; - assign _dfoo137 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo1 ; - assign _dfoo1370 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1302 ; - assign _dfoo1371 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1235 ; - assign _dfoo1372 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1304 ; - assign _dfoo1373 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1237 ; - assign _dfoo1374 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1306 ; - assign _dfoo1375 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1239 ; - assign _dfoo1376 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1308 ; - assign _dfoo1377 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1241 ; - assign _dfoo1378 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1310 ; - assign _dfoo1379 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1243 ; - assign _dfoo138 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo70 ; - assign _dfoo1380 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1312 ; - assign _dfoo1381 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1245 ; - assign _dfoo1382 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1314 ; - assign _dfoo1383 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1247 ; - assign _dfoo1384 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1316 ; - assign _dfoo1385 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1249 ; - assign _dfoo1386 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1318 ; - assign _dfoo1387 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1251 ; - assign _dfoo1388 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1320 ; - assign _dfoo1389 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1253 ; - assign _dfoo139 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo3 ; - assign _dfoo1390 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1322 ; - assign _dfoo1391 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1255 ; - assign _dfoo1392 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1324 ; - assign _dfoo1393 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1257 ; - assign _dfoo1394 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1326 ; - assign _dfoo1395 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1259 ; - assign _dfoo1396 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1328 ; - assign _dfoo1397 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1261 ; - assign _dfoo1398 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1330 ; - assign _dfoo1399 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1263 ; - assign _dfoo14 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo140 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo72 ; - assign _dfoo1400 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1332 ; - assign _dfoo1401 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1265 ; - assign _dfoo1402 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1334 ; - assign _dfoo1403 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1267 ; - assign _dfoo1404 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1336 ; - assign _dfoo1405 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1269 ; - assign _dfoo1406 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1338 ; - assign _dfoo1407 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1271 ; - assign _dfoo1408 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1340 ; - assign _dfoo1409 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1273 ; - assign _dfoo141 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo5 ; - assign _dfoo1410 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1342 ; - assign _dfoo1411 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1275 ; - assign _dfoo1412 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1344 ; - assign _dfoo1413 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1277 ; - assign _dfoo1414 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1346 ; - assign _dfoo1415 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1279 ; - assign _dfoo1416 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1348 ; - assign _dfoo1417 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1281 ; - assign _dfoo1418 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1350 ; - assign _dfoo1419 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1283 ; - assign _dfoo142 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo74 ; - assign _dfoo1420 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1352 ; - assign _dfoo1421 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1285 ; - assign _dfoo1422 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1354 ; - assign _dfoo1423 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1287 ; - assign _dfoo1424 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1356 ; - assign _dfoo1425 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1289 ; - assign _dfoo1426 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1358 ; - assign _dfoo1427 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1291 ; - assign _dfoo1428 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1360 ; - assign _dfoo143 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo7 ; - assign _dfoo1430 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1362 ; - assign _dfoo1432 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1364 ; - assign _dfoo1434 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1366 ; - assign _dfoo1436 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1368 ; - assign _dfoo1438 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1370 ; - assign _dfoo144 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo76 ; - assign _dfoo1440 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1372 ; - assign _dfoo1442 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1374 ; - assign _dfoo1444 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1376 ; - assign _dfoo1446 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1378 ; - assign _dfoo1448 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1380 ; - assign _dfoo145 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo9 ; - assign _dfoo1450 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1382 ; - assign _dfoo1452 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1384 ; - assign _dfoo1454 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1386 ; - assign _dfoo1456 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1388 ; - assign _dfoo1458 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1390 ; - assign _dfoo146 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo78 ; - assign _dfoo1460 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1392 ; - assign _dfoo1462 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1394 ; - assign _dfoo1464 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1396 ; - assign _dfoo1466 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1398 ; - assign _dfoo1468 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1400 ; - assign _dfoo147 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo11 ; - assign _dfoo1470 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1402 ; - assign _dfoo1472 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1404 ; - assign _dfoo1474 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1406 ; - assign _dfoo1476 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1408 ; - assign _dfoo1478 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1410 ; - assign _dfoo148 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo80 ; - assign _dfoo1480 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1412 ; - assign _dfoo1482 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1414 ; - assign _dfoo1484 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1416 ; - assign _dfoo1486 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1418 ; - assign _dfoo1488 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1420 ; - assign _dfoo149 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo13 ; - assign _dfoo1490 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1422 ; - assign _dfoo1492 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1424 ; - assign _dfoo1494 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1426 ; - assign _dfoo1496 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1428 ; - assign _dfoo1497 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1361 ; - assign _dfoo1498 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1430 ; - assign _dfoo1499 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1363 ; - assign _dfoo15 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo150 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo82 ; - assign _dfoo1500 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1432 ; - assign _dfoo1501 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1365 ; - assign _dfoo1502 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1434 ; - assign _dfoo1503 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1367 ; - assign _dfoo1504 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1436 ; - assign _dfoo1505 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1369 ; - assign _dfoo1506 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1438 ; - assign _dfoo1507 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1371 ; - assign _dfoo1508 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1440 ; - assign _dfoo1509 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1373 ; - assign _dfoo151 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo15 ; - assign _dfoo1510 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1442 ; - assign _dfoo1511 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1375 ; - assign _dfoo1512 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1444 ; - assign _dfoo1513 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1377 ; - assign _dfoo1514 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1446 ; - assign _dfoo1515 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1379 ; - assign _dfoo1516 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1448 ; - assign _dfoo1517 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1381 ; - assign _dfoo1518 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1450 ; - assign _dfoo1519 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1383 ; - assign _dfoo152 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo84 ; - assign _dfoo1520 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1452 ; - assign _dfoo1521 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1385 ; - assign _dfoo1522 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1454 ; - assign _dfoo1523 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1387 ; - assign _dfoo1524 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1456 ; - assign _dfoo1525 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1389 ; - assign _dfoo1526 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1458 ; - assign _dfoo1527 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1391 ; - assign _dfoo1528 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1460 ; - assign _dfoo1529 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1393 ; - assign _dfoo153 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo17 ; - assign _dfoo1530 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1462 ; - assign _dfoo1531 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1395 ; - assign _dfoo1532 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1464 ; - assign _dfoo1533 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1397 ; - assign _dfoo1534 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1466 ; - assign _dfoo1535 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1399 ; - assign _dfoo1536 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1468 ; - assign _dfoo1537 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1401 ; - assign _dfoo1538 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1470 ; - assign _dfoo1539 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1403 ; - assign _dfoo154 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo86 ; - assign _dfoo1540 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1472 ; - assign _dfoo1541 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1405 ; - assign _dfoo1542 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1474 ; - assign _dfoo1543 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1407 ; - assign _dfoo1544 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1476 ; - assign _dfoo1545 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1409 ; - assign _dfoo1546 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1478 ; - assign _dfoo1547 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1411 ; - assign _dfoo1548 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1480 ; - assign _dfoo1549 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1413 ; - assign _dfoo155 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo19 ; - assign _dfoo1550 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1482 ; - assign _dfoo1551 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1415 ; - assign _dfoo1552 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1484 ; - assign _dfoo1553 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1417 ; - assign _dfoo1554 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1486 ; - assign _dfoo1555 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1419 ; - assign _dfoo1556 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1488 ; - assign _dfoo1557 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1421 ; - assign _dfoo1558 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1490 ; - assign _dfoo1559 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1423 ; - assign _dfoo156 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo88 ; - assign _dfoo1560 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1492 ; - assign _dfoo1561 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1425 ; - assign _dfoo1562 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1494 ; - assign _dfoo1563 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1427 ; - assign _dfoo1564 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1496 ; - assign _dfoo1566 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1498 ; - assign _dfoo1568 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1500 ; - assign _dfoo157 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo21 ; - assign _dfoo1570 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1502 ; - assign _dfoo1572 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1504 ; - assign _dfoo1574 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1506 ; - assign _dfoo1576 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1508 ; - assign _dfoo1578 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1510 ; - assign _dfoo158 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo90 ; - assign _dfoo1580 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1512 ; - assign _dfoo1582 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1514 ; - assign _dfoo1584 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1516 ; - assign _dfoo1586 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1518 ; - assign _dfoo1588 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1520 ; - assign _dfoo159 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo23 ; - assign _dfoo1590 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1522 ; - assign _dfoo1592 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1524 ; - assign _dfoo1594 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1526 ; - assign _dfoo1596 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1528 ; - assign _dfoo1598 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1530 ; - assign _dfoo16 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo160 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo92 ; - assign _dfoo1600 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1532 ; - assign _dfoo1602 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1534 ; - assign _dfoo1604 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1536 ; - assign _dfoo1606 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1538 ; - assign _dfoo1608 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1540 ; - assign _dfoo161 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo25 ; - assign _dfoo1610 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1542 ; - assign _dfoo1612 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1544 ; - assign _dfoo1614 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1546 ; - assign _dfoo1616 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1548 ; - assign _dfoo1618 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1550 ; - assign _dfoo162 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo94 ; - assign _dfoo1620 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1552 ; - assign _dfoo1622 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1554 ; - assign _dfoo1624 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1556 ; - assign _dfoo1626 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1558 ; - assign _dfoo1628 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1560 ; - assign _dfoo163 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo27 ; - assign _dfoo1630 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1562 ; - assign _dfoo1632 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1564 ; - assign _dfoo1633 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1497 ; - assign _dfoo1634 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1566 ; - assign _dfoo1635 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1499 ; - assign _dfoo1636 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1568 ; - assign _dfoo1637 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1501 ; - assign _dfoo1638 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1570 ; - assign _dfoo1639 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1503 ; - assign _dfoo164 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo96 ; - assign _dfoo1640 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1572 ; - assign _dfoo1641 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1505 ; - assign _dfoo1642 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1574 ; - assign _dfoo1643 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1507 ; - assign _dfoo1644 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1576 ; - assign _dfoo1645 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1509 ; - assign _dfoo1646 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1578 ; - assign _dfoo1647 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1511 ; - assign _dfoo1648 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1580 ; - assign _dfoo1649 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1513 ; - assign _dfoo165 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo29 ; - assign _dfoo1650 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1582 ; - assign _dfoo1651 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1515 ; - assign _dfoo1652 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1584 ; - assign _dfoo1653 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1517 ; - assign _dfoo1654 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1586 ; - assign _dfoo1655 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1519 ; - assign _dfoo1656 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1588 ; - assign _dfoo1657 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1521 ; - assign _dfoo1658 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1590 ; - assign _dfoo1659 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1523 ; - assign _dfoo166 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo98 ; - assign _dfoo1660 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1592 ; - assign _dfoo1661 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1525 ; - assign _dfoo1662 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1594 ; - assign _dfoo1663 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1527 ; - assign _dfoo1664 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1596 ; - assign _dfoo1665 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1529 ; - assign _dfoo1666 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1598 ; - assign _dfoo1667 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1531 ; - assign _dfoo1668 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1600 ; - assign _dfoo1669 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1533 ; - assign _dfoo167 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo31 ; - assign _dfoo1670 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1602 ; - assign _dfoo1671 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1535 ; - assign _dfoo1672 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1604 ; - assign _dfoo1673 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1537 ; - assign _dfoo1674 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1606 ; - assign _dfoo1675 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1539 ; - assign _dfoo1676 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1608 ; - assign _dfoo1677 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1541 ; - assign _dfoo1678 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1610 ; - assign _dfoo1679 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1543 ; - assign _dfoo168 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo100 ; - assign _dfoo1680 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1612 ; - assign _dfoo1681 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1545 ; - assign _dfoo1682 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1614 ; - assign _dfoo1683 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1547 ; - assign _dfoo1684 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1616 ; - assign _dfoo1685 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1549 ; - assign _dfoo1686 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1618 ; - assign _dfoo1687 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1551 ; - assign _dfoo1688 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1620 ; - assign _dfoo1689 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1553 ; - assign _dfoo169 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo33 ; - assign _dfoo1690 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1622 ; - assign _dfoo1691 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1555 ; - assign _dfoo1692 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1624 ; - assign _dfoo1693 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1557 ; - assign _dfoo1694 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1626 ; - assign _dfoo1695 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1559 ; - assign _dfoo1696 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1628 ; - assign _dfoo1697 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1561 ; - assign _dfoo1698 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1630 ; - assign _dfoo1699 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1563 ; - assign _dfoo17 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo170 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo102 ; - assign _dfoo1700 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1632 ; - assign _dfoo1702 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1634 ; - assign _dfoo1704 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1636 ; - assign _dfoo1706 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1638 ; - assign _dfoo1708 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1640 ; - assign _dfoo171 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo35 ; - assign _dfoo1710 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1642 ; - assign _dfoo1712 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1644 ; - assign _dfoo1714 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1646 ; - assign _dfoo1716 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1648 ; - assign _dfoo1718 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1650 ; - assign _dfoo172 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo104 ; - assign _dfoo1720 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1652 ; - assign _dfoo1722 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1654 ; - assign _dfoo1724 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1656 ; - assign _dfoo1726 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1658 ; - assign _dfoo1728 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1660 ; - assign _dfoo173 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo37 ; - assign _dfoo1730 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1662 ; - assign _dfoo1732 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1664 ; - assign _dfoo1734 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1666 ; - assign _dfoo1736 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1668 ; - assign _dfoo1738 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1670 ; - assign _dfoo174 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo106 ; - assign _dfoo1740 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1672 ; - assign _dfoo1742 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1674 ; - assign _dfoo1744 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1676 ; - assign _dfoo1746 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1678 ; - assign _dfoo1748 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1680 ; - assign _dfoo175 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo39 ; - assign _dfoo1750 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1682 ; - assign _dfoo1752 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1684 ; - assign _dfoo1754 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1686 ; - assign _dfoo1756 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1688 ; - assign _dfoo1758 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1690 ; - assign _dfoo176 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo108 ; - assign _dfoo1760 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1692 ; - assign _dfoo1762 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1694 ; - assign _dfoo1764 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1696 ; - assign _dfoo1766 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1698 ; - assign _dfoo1768 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1700 ; - assign _dfoo1769 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1633 ; - assign _dfoo177 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo41 ; - assign _dfoo1770 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1702 ; - assign _dfoo1771 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1635 ; - assign _dfoo1772 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1704 ; - assign _dfoo1773 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1637 ; - assign _dfoo1774 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1706 ; - assign _dfoo1775 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1639 ; - assign _dfoo1776 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1708 ; - assign _dfoo1777 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1641 ; - assign _dfoo1778 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1710 ; - assign _dfoo1779 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1643 ; - assign _dfoo178 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo110 ; - assign _dfoo1780 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1712 ; - assign _dfoo1781 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1645 ; - assign _dfoo1782 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1714 ; - assign _dfoo1783 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1647 ; - assign _dfoo1784 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1716 ; - assign _dfoo1785 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1649 ; - assign _dfoo1786 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1718 ; - assign _dfoo1787 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1651 ; - assign _dfoo1788 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1720 ; - assign _dfoo1789 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1653 ; - assign _dfoo179 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo43 ; - assign _dfoo1790 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1722 ; - assign _dfoo1791 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1655 ; - assign _dfoo1792 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1724 ; - assign _dfoo1793 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1657 ; - assign _dfoo1794 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1726 ; - assign _dfoo1795 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1659 ; - assign _dfoo1796 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1728 ; - assign _dfoo1797 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1661 ; - assign _dfoo1798 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1730 ; - assign _dfoo1799 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1663 ; - assign _dfoo18 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo180 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo112 ; - assign _dfoo1800 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1732 ; - assign _dfoo1801 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1665 ; - assign _dfoo1802 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1734 ; - assign _dfoo1803 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1667 ; - assign _dfoo1804 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1736 ; - assign _dfoo1805 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1669 ; - assign _dfoo1806 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1738 ; - assign _dfoo1807 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1671 ; - assign _dfoo1808 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1740 ; - assign _dfoo1809 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1673 ; - assign _dfoo181 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo45 ; - assign _dfoo1810 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1742 ; - assign _dfoo1811 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1675 ; - assign _dfoo1812 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1744 ; - assign _dfoo1813 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1677 ; - assign _dfoo1814 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1746 ; - assign _dfoo1815 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1679 ; - assign _dfoo1816 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1748 ; - assign _dfoo1817 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1681 ; - assign _dfoo1818 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1750 ; - assign _dfoo1819 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1683 ; - assign _dfoo182 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo114 ; - assign _dfoo1820 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1752 ; - assign _dfoo1821 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1685 ; - assign _dfoo1822 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1754 ; - assign _dfoo1823 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1687 ; - assign _dfoo1824 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1756 ; - assign _dfoo1825 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1689 ; - assign _dfoo1826 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1758 ; - assign _dfoo1827 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1691 ; - assign _dfoo1828 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1760 ; - assign _dfoo1829 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1693 ; - assign _dfoo183 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo47 ; - assign _dfoo1830 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1762 ; - assign _dfoo1831 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1695 ; - assign _dfoo1832 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1764 ; - assign _dfoo1833 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1697 ; - assign _dfoo1834 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1766 ; - assign _dfoo1835 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1699 ; - assign _dfoo1836 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1768 ; - assign _dfoo1838 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1770 ; - assign _dfoo184 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo116 ; - assign _dfoo1840 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1772 ; - assign _dfoo1842 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1774 ; - assign _dfoo1844 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1776 ; - assign _dfoo1846 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1778 ; - assign _dfoo1848 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1780 ; - assign _dfoo185 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo49 ; - assign _dfoo1850 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1782 ; - assign _dfoo1852 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1784 ; - assign _dfoo1854 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1786 ; - assign _dfoo1856 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1788 ; - assign _dfoo1858 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1790 ; - assign _dfoo186 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo118 ; - assign _dfoo1860 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1792 ; - assign _dfoo1862 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1794 ; - assign _dfoo1864 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1796 ; - assign _dfoo1866 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1798 ; - assign _dfoo1868 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1800 ; - assign _dfoo187 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo51 ; - assign _dfoo1870 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1802 ; - assign _dfoo1872 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1804 ; - assign _dfoo1874 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1806 ; - assign _dfoo1876 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1808 ; - assign _dfoo1878 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1810 ; - assign _dfoo188 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo120 ; - assign _dfoo1880 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1812 ; - assign _dfoo1882 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1814 ; - assign _dfoo1884 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1816 ; - assign _dfoo1886 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1818 ; - assign _dfoo1888 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1820 ; - assign _dfoo189 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo53 ; - assign _dfoo1890 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1822 ; - assign _dfoo1892 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1824 ; - assign _dfoo1894 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1826 ; - assign _dfoo1896 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1828 ; - assign _dfoo1898 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1830 ; - assign _dfoo19 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo190 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo122 ; - assign _dfoo1900 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1832 ; - assign _dfoo1902 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1834 ; - assign _dfoo1904 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1836 ; - assign _dfoo1905 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1769 ; - assign _dfoo1906 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1838 ; - assign _dfoo1907 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1771 ; - assign _dfoo1908 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1840 ; - assign _dfoo1909 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1773 ; - assign _dfoo191 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo55 ; - assign _dfoo1910 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1842 ; - assign _dfoo1911 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1775 ; - assign _dfoo1912 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1844 ; - assign _dfoo1913 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1777 ; - assign _dfoo1914 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1846 ; - assign _dfoo1915 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1779 ; - assign _dfoo1916 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1848 ; - assign _dfoo1917 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1781 ; - assign _dfoo1918 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1850 ; - assign _dfoo1919 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1783 ; - assign _dfoo192 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo124 ; - assign _dfoo1920 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1852 ; - assign _dfoo1921 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1785 ; - assign _dfoo1922 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1854 ; - assign _dfoo1923 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1787 ; - assign _dfoo1924 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1856 ; - assign _dfoo1925 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1789 ; - assign _dfoo1926 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1858 ; - assign _dfoo1927 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1791 ; - assign _dfoo1928 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1860 ; - assign _dfoo1929 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1793 ; - assign _dfoo193 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo57 ; - assign _dfoo1930 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1862 ; - assign _dfoo1931 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1795 ; - assign _dfoo1932 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1864 ; - assign _dfoo1933 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1797 ; - assign _dfoo1934 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1866 ; - assign _dfoo1935 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1799 ; - assign _dfoo1936 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1868 ; - assign _dfoo1937 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1801 ; - assign _dfoo1938 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1870 ; - assign _dfoo1939 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1803 ; - assign _dfoo194 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo126 ; - assign _dfoo1940 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1872 ; - assign _dfoo1941 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1805 ; - assign _dfoo1942 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1874 ; - assign _dfoo1943 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1807 ; - assign _dfoo1944 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1876 ; - assign _dfoo1945 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1809 ; - assign _dfoo1946 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1878 ; - assign _dfoo1947 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1811 ; - assign _dfoo1948 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1880 ; - assign _dfoo1949 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1813 ; - assign _dfoo195 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo59 ; - assign _dfoo1950 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1882 ; - assign _dfoo1951 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1815 ; - assign _dfoo1952 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1884 ; - assign _dfoo1953 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1817 ; - assign _dfoo1954 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1886 ; - assign _dfoo1955 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1819 ; - assign _dfoo1956 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1888 ; - assign _dfoo1957 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1821 ; - assign _dfoo1958 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1890 ; - assign _dfoo1959 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1823 ; - assign _dfoo196 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo128 ; - assign _dfoo1960 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1892 ; - assign _dfoo1961 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1825 ; - assign _dfoo1962 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1894 ; - assign _dfoo1963 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1827 ; - assign _dfoo1964 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1896 ; - assign _dfoo1965 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1829 ; - assign _dfoo1966 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1898 ; - assign _dfoo1967 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1831 ; - assign _dfoo1968 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1900 ; - assign _dfoo1969 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1833 ; - assign _dfoo197 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo61 ; - assign _dfoo1970 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1902 ; - assign _dfoo1971 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1835 ; - assign _dfoo1972 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1904 ; - assign _dfoo1974 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1906 ; - assign _dfoo1976 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1908 ; - assign _dfoo1978 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1910 ; - assign _dfoo198 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo130 ; - assign _dfoo1980 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1912 ; - assign _dfoo1982 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1914 ; - assign _dfoo1984 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1916 ; - assign _dfoo1986 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1918 ; - assign _dfoo1988 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1920 ; - assign _dfoo199 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo63 ; - assign _dfoo1990 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1922 ; - assign _dfoo1992 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1924 ; - assign _dfoo1994 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1926 ; - assign _dfoo1996 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1928 ; - assign _dfoo1998 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1930 ; - assign _dfoo2 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo20 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo200 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo132 ; - assign _dfoo2000 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1932 ; - assign _dfoo2002 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1934 ; - assign _dfoo2004 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1936 ; - assign _dfoo2006 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1938 ; - assign _dfoo2008 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1940 ; - assign _dfoo201 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo65 ; - assign _dfoo2010 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1942 ; - assign _dfoo2012 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1944 ; - assign _dfoo2014 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1946 ; - assign _dfoo2016 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1948 ; - assign _dfoo2018 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1950 ; - assign _dfoo202 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo134 ; - assign _dfoo2020 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1952 ; - assign _dfoo2022 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1954 ; - assign _dfoo2024 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1956 ; - assign _dfoo2026 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1958 ; - assign _dfoo2028 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1960 ; - assign _dfoo203 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo67 ; - assign _dfoo2030 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1962 ; - assign _dfoo2032 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1964 ; - assign _dfoo2034 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1966 ; - assign _dfoo2036 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1968 ; - assign _dfoo2038 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1970 ; - assign _dfoo204 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo136 ; - assign _dfoo2040 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1972 ; - assign _dfoo2041 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1905 ; - assign _dfoo2043 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1907 ; - assign _dfoo2045 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1909 ; - assign _dfoo2047 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1911 ; - assign _dfoo2049 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1913 ; - assign _dfoo2051 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1915 ; - assign _dfoo2053 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1917 ; - assign _dfoo2055 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1919 ; - assign _dfoo2057 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1921 ; - assign _dfoo2059 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1923 ; - assign _dfoo206 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo138 ; - assign _dfoo2061 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1925 ; - assign _dfoo2063 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1927 ; - assign _dfoo2065 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1929 ; - assign _dfoo2067 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1931 ; - assign _dfoo2069 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1933 ; - assign _dfoo2071 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1935 ; - assign _dfoo2073 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1937 ; - assign _dfoo2075 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1939 ; - assign _dfoo2077 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1941 ; - assign _dfoo2079 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1943 ; - assign _dfoo208 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo140 ; - assign _dfoo2081 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1945 ; - assign _dfoo2083 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1947 ; - assign _dfoo2085 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1949 ; - assign _dfoo2087 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1951 ; - assign _dfoo2089 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1953 ; - assign _dfoo2091 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1955 ; - assign _dfoo2093 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1957 ; - assign _dfoo2095 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1959 ; - assign _dfoo2097 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1961 ; - assign _dfoo2099 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1963 ; - assign _dfoo21 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo210 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo142 ; - assign _dfoo2101 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1965 ; - assign _dfoo2103 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1967 ; - assign _dfoo2105 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1969 ; - assign _dfoo2107 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1971 ; - assign _dfoo212 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo144 ; - assign _dfoo214 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo146 ; - assign _dfoo216 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo148 ; - assign _dfoo218 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo150 ; - assign _dfoo22 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo220 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo152 ; - assign _dfoo222 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo154 ; - assign _dfoo224 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo156 ; - assign _dfoo226 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo158 ; - assign _dfoo228 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo160 ; - assign _dfoo23 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo230 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo162 ; - assign _dfoo232 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo164 ; - assign _dfoo234 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo166 ; - assign _dfoo236 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo168 ; - assign _dfoo238 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo170 ; - assign _dfoo24 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo240 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo172 ; - assign _dfoo242 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo174 ; - assign _dfoo244 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo176 ; - assign _dfoo246 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo178 ; - assign _dfoo248 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo180 ; - assign _dfoo25 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo250 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo182 ; - assign _dfoo252 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo184 ; - assign _dfoo254 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo186 ; - assign _dfoo256 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo188 ; - assign _dfoo258 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo190 ; - assign _dfoo26 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo260 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo192 ; - assign _dfoo262 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo194 ; - assign _dfoo264 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo196 ; - assign _dfoo266 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo198 ; - assign _dfoo268 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo200 ; - assign _dfoo27 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo270 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo202 ; - assign _dfoo272 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo204 ; - assign _dfoo273 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo137 ; - assign _dfoo274 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo206 ; - assign _dfoo275 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo139 ; - assign _dfoo276 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo208 ; - assign _dfoo277 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo141 ; - assign _dfoo278 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo210 ; - assign _dfoo279 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo143 ; - assign _dfoo28 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo280 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo212 ; - assign _dfoo281 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo145 ; - assign _dfoo282 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo214 ; - assign _dfoo283 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo147 ; - assign _dfoo284 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo216 ; - assign _dfoo285 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo149 ; - assign _dfoo286 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo218 ; - assign _dfoo287 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo151 ; - assign _dfoo288 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo220 ; - assign _dfoo289 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo153 ; - assign _dfoo29 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo290 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo222 ; - assign _dfoo291 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo155 ; - assign _dfoo292 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo224 ; - assign _dfoo293 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo157 ; - assign _dfoo294 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo226 ; - assign _dfoo295 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo159 ; - assign _dfoo296 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo228 ; - assign _dfoo297 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo161 ; - assign _dfoo298 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo230 ; - assign _dfoo299 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo163 ; - assign _dfoo3 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo30 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo300 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo232 ; - assign _dfoo301 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo165 ; - assign _dfoo302 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo234 ; - assign _dfoo303 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo167 ; - assign _dfoo304 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo236 ; - assign _dfoo305 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo169 ; - assign _dfoo306 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo238 ; - assign _dfoo307 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo171 ; - assign _dfoo308 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo240 ; - assign _dfoo309 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo173 ; - assign _dfoo31 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo310 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo242 ; - assign _dfoo311 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo175 ; - assign _dfoo312 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo244 ; - assign _dfoo313 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo177 ; - assign _dfoo314 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo246 ; - assign _dfoo315 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo179 ; - assign _dfoo316 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo248 ; - assign _dfoo317 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo181 ; - assign _dfoo318 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo250 ; - assign _dfoo319 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo183 ; - assign _dfoo32 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo320 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo252 ; - assign _dfoo321 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo185 ; - assign _dfoo322 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo254 ; - assign _dfoo323 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo187 ; - assign _dfoo324 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo256 ; - assign _dfoo325 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo189 ; - assign _dfoo326 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo258 ; - assign _dfoo327 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo191 ; - assign _dfoo328 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo260 ; - assign _dfoo329 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo193 ; - assign _dfoo33 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo330 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo262 ; - assign _dfoo331 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo195 ; - assign _dfoo332 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo264 ; - assign _dfoo333 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo197 ; - assign _dfoo334 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo266 ; - assign _dfoo335 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo199 ; - assign _dfoo336 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo268 ; - assign _dfoo337 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo201 ; - assign _dfoo338 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo270 ; - assign _dfoo339 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo203 ; - assign _dfoo34 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo340 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo272 ; - assign _dfoo342 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo274 ; - assign _dfoo344 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo276 ; - assign _dfoo346 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo278 ; - assign _dfoo348 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo280 ; - assign _dfoo35 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo350 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo282 ; - assign _dfoo352 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo284 ; - assign _dfoo354 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo286 ; - assign _dfoo356 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo288 ; - assign _dfoo358 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo290 ; - assign _dfoo36 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo360 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo292 ; - assign _dfoo362 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo294 ; - assign _dfoo364 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo296 ; - assign _dfoo366 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo298 ; - assign _dfoo368 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo300 ; - assign _dfoo37 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo370 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo302 ; - assign _dfoo372 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo304 ; - assign _dfoo374 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo306 ; - assign _dfoo376 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo308 ; - assign _dfoo378 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo310 ; - assign _dfoo38 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo380 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo312 ; - assign _dfoo382 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo314 ; - assign _dfoo384 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo316 ; - assign _dfoo386 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo318 ; - assign _dfoo388 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo320 ; - assign _dfoo39 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo390 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo322 ; - assign _dfoo392 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo324 ; - assign _dfoo394 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo326 ; - assign _dfoo396 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo328 ; - assign _dfoo398 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo330 ; - assign _dfoo4 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo40 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo400 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo332 ; - assign _dfoo402 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo334 ; - assign _dfoo404 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo336 ; - assign _dfoo406 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo338 ; - assign _dfoo408 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo340 ; - assign _dfoo409 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo273 ; - assign _dfoo41 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo410 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo342 ; - assign _dfoo411 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo275 ; - assign _dfoo412 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo344 ; - assign _dfoo413 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo277 ; - assign _dfoo414 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo346 ; - assign _dfoo415 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo279 ; - assign _dfoo416 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo348 ; - assign _dfoo417 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo281 ; - assign _dfoo418 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo350 ; - assign _dfoo419 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo283 ; - assign _dfoo42 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo420 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo352 ; - assign _dfoo421 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo285 ; - assign _dfoo422 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo354 ; - assign _dfoo423 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo287 ; - assign _dfoo424 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo356 ; - assign _dfoo425 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo289 ; - assign _dfoo426 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo358 ; - assign _dfoo427 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo291 ; - assign _dfoo428 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo360 ; - assign _dfoo429 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo293 ; - assign _dfoo43 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo430 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo362 ; - assign _dfoo431 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo295 ; - assign _dfoo432 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo364 ; - assign _dfoo433 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo297 ; - assign _dfoo434 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo366 ; - assign _dfoo435 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo299 ; - assign _dfoo436 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo368 ; - assign _dfoo437 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo301 ; - assign _dfoo438 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo370 ; - assign _dfoo439 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo303 ; - assign _dfoo44 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo440 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo372 ; - assign _dfoo441 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo305 ; - assign _dfoo442 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo374 ; - assign _dfoo443 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo307 ; - assign _dfoo444 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo376 ; - assign _dfoo445 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo309 ; - assign _dfoo446 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo378 ; - assign _dfoo447 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo311 ; - assign _dfoo448 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo380 ; - assign _dfoo449 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo313 ; - assign _dfoo45 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo450 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo382 ; - assign _dfoo451 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo315 ; - assign _dfoo452 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo384 ; - assign _dfoo453 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo317 ; - assign _dfoo454 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo386 ; - assign _dfoo455 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo319 ; - assign _dfoo456 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo388 ; - assign _dfoo457 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo321 ; - assign _dfoo458 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo390 ; - assign _dfoo459 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo323 ; - assign _dfoo46 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo460 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo392 ; - assign _dfoo461 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo325 ; - assign _dfoo462 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo394 ; - assign _dfoo463 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo327 ; - assign _dfoo464 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo396 ; - assign _dfoo465 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo329 ; - assign _dfoo466 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo398 ; - assign _dfoo467 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo331 ; - assign _dfoo468 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo400 ; - assign _dfoo469 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo333 ; - assign _dfoo47 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo470 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo402 ; - assign _dfoo471 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo335 ; - assign _dfoo472 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo404 ; - assign _dfoo473 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo337 ; - assign _dfoo474 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo406 ; - assign _dfoo475 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo339 ; - assign _dfoo476 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo408 ; - assign _dfoo478 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo410 ; - assign _dfoo48 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo480 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo412 ; - assign _dfoo482 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo414 ; - assign _dfoo484 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo416 ; - assign _dfoo486 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo418 ; - assign _dfoo488 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo420 ; - assign _dfoo49 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo490 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo422 ; - assign _dfoo492 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo424 ; - assign _dfoo494 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo426 ; - assign _dfoo496 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo428 ; - assign _dfoo498 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo430 ; - assign _dfoo5 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo50 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo500 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo432 ; - assign _dfoo502 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo434 ; - assign _dfoo504 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo436 ; - assign _dfoo506 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo438 ; - assign _dfoo508 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo440 ; - assign _dfoo51 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo510 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo442 ; - assign _dfoo512 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo444 ; - assign _dfoo514 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo446 ; - assign _dfoo516 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo448 ; - assign _dfoo518 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo450 ; - assign _dfoo52 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo520 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo452 ; - assign _dfoo522 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo454 ; - assign _dfoo524 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo456 ; - assign _dfoo526 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo458 ; - assign _dfoo528 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo460 ; - assign _dfoo53 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo530 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo462 ; - assign _dfoo532 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo464 ; - assign _dfoo534 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo466 ; - assign _dfoo536 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo468 ; - assign _dfoo538 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo470 ; - assign _dfoo54 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo540 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo472 ; - assign _dfoo542 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo474 ; - assign _dfoo544 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo476 ; - assign _dfoo545 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo409 ; - assign _dfoo546 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo478 ; - assign _dfoo547 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo411 ; - assign _dfoo548 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo480 ; - assign _dfoo549 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo413 ; - assign _dfoo55 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo550 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo482 ; - assign _dfoo551 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo415 ; - assign _dfoo552 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo484 ; - assign _dfoo553 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo417 ; - assign _dfoo554 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo486 ; - assign _dfoo555 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo419 ; - assign _dfoo556 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo488 ; - assign _dfoo557 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo421 ; - assign _dfoo558 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo490 ; - assign _dfoo559 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo423 ; - assign _dfoo56 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo560 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo492 ; - assign _dfoo561 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo425 ; - assign _dfoo562 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo494 ; - assign _dfoo563 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo427 ; - assign _dfoo564 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo496 ; - assign _dfoo565 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo429 ; - assign _dfoo566 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo498 ; - assign _dfoo567 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo431 ; - assign _dfoo568 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo500 ; - assign _dfoo569 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo433 ; - assign _dfoo57 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo570 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo502 ; - assign _dfoo571 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo435 ; - assign _dfoo572 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo504 ; - assign _dfoo573 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo437 ; - assign _dfoo574 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo506 ; - assign _dfoo575 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo439 ; - assign _dfoo576 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo508 ; - assign _dfoo577 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo441 ; - assign _dfoo578 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo510 ; - assign _dfoo579 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo443 ; - assign _dfoo58 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo580 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo512 ; - assign _dfoo581 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo445 ; - assign _dfoo582 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo514 ; - assign _dfoo583 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo447 ; - assign _dfoo584 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo516 ; - assign _dfoo585 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo449 ; - assign _dfoo586 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo518 ; - assign _dfoo587 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo451 ; - assign _dfoo588 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo520 ; - assign _dfoo589 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo453 ; - assign _dfoo59 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo590 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo522 ; - assign _dfoo591 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo455 ; - assign _dfoo592 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo524 ; - assign _dfoo593 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo457 ; - assign _dfoo594 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo526 ; - assign _dfoo595 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo459 ; - assign _dfoo596 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo528 ; - assign _dfoo597 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo461 ; - assign _dfoo598 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo530 ; - assign _dfoo599 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo463 ; - assign _dfoo6 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo60 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo600 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo532 ; - assign _dfoo601 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo465 ; - assign _dfoo602 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo534 ; - assign _dfoo603 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo467 ; - assign _dfoo604 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo536 ; - assign _dfoo605 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo469 ; - assign _dfoo606 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo538 ; - assign _dfoo607 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo471 ; - assign _dfoo608 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo540 ; - assign _dfoo609 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo473 ; - assign _dfoo61 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo610 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo542 ; - assign _dfoo611 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo475 ; - assign _dfoo612 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo544 ; - assign _dfoo614 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo546 ; - assign _dfoo616 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo548 ; - assign _dfoo618 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo550 ; - assign _dfoo62 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo620 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo552 ; - assign _dfoo622 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo554 ; - assign _dfoo624 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo556 ; - assign _dfoo626 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo558 ; - assign _dfoo628 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo560 ; - assign _dfoo63 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo630 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo562 ; - assign _dfoo632 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo564 ; - assign _dfoo634 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo566 ; - assign _dfoo636 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo568 ; - assign _dfoo638 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo570 ; - assign _dfoo64 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo640 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo572 ; - assign _dfoo642 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo574 ; - assign _dfoo644 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo576 ; - assign _dfoo646 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo578 ; - assign _dfoo648 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo580 ; - assign _dfoo65 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo650 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo582 ; - assign _dfoo652 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo584 ; - assign _dfoo654 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo586 ; - assign _dfoo656 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo588 ; - assign _dfoo658 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo590 ; - assign _dfoo66 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo660 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo592 ; - assign _dfoo662 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo594 ; - assign _dfoo664 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo596 ; - assign _dfoo666 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo598 ; - assign _dfoo668 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo600 ; - assign _dfoo67 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo670 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo602 ; - assign _dfoo672 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo604 ; - assign _dfoo674 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo606 ; - assign _dfoo676 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo608 ; - assign _dfoo678 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo610 ; - assign _dfoo68 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo680 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo612 ; - assign _dfoo681 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo545 ; - assign _dfoo682 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo614 ; - assign _dfoo683 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo547 ; - assign _dfoo684 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo616 ; - assign _dfoo685 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo549 ; - assign _dfoo686 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo618 ; - assign _dfoo687 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo551 ; - assign _dfoo688 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo620 ; - assign _dfoo689 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo553 ; - assign _dfoo690 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo622 ; - assign _dfoo691 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo555 ; - assign _dfoo692 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo624 ; - assign _dfoo693 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo557 ; - assign _dfoo694 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo626 ; - assign _dfoo695 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo559 ; - assign _dfoo696 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo628 ; - assign _dfoo697 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo561 ; - assign _dfoo698 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo630 ; - assign _dfoo699 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo563 ; - assign _dfoo7 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo70 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo2 ; - assign _dfoo700 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo632 ; - assign _dfoo701 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo565 ; - assign _dfoo702 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo634 ; - assign _dfoo703 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo567 ; - assign _dfoo704 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo636 ; - assign _dfoo705 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo569 ; - assign _dfoo706 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo638 ; - assign _dfoo707 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo571 ; - assign _dfoo708 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo640 ; - assign _dfoo709 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo573 ; - assign _dfoo710 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo642 ; - assign _dfoo711 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo575 ; - assign _dfoo712 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo644 ; - assign _dfoo713 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo577 ; - assign _dfoo714 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo646 ; - assign _dfoo715 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo579 ; - assign _dfoo716 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo648 ; - assign _dfoo717 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo581 ; - assign _dfoo718 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo650 ; - assign _dfoo719 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo583 ; - assign _dfoo72 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo4 ; - assign _dfoo720 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo652 ; - assign _dfoo721 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo585 ; - assign _dfoo722 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo654 ; - assign _dfoo723 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo587 ; - assign _dfoo724 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo656 ; - assign _dfoo725 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo589 ; - assign _dfoo726 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo658 ; - assign _dfoo727 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo591 ; - assign _dfoo728 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo660 ; - assign _dfoo729 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo593 ; - assign _dfoo730 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo662 ; - assign _dfoo731 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo595 ; - assign _dfoo732 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo664 ; - assign _dfoo733 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo597 ; - assign _dfoo734 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo666 ; - assign _dfoo735 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo599 ; - assign _dfoo736 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo668 ; - assign _dfoo737 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo601 ; - assign _dfoo738 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo670 ; - assign _dfoo739 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo603 ; - assign _dfoo74 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo6 ; - assign _dfoo740 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo672 ; - assign _dfoo741 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo605 ; - assign _dfoo742 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo674 ; - assign _dfoo743 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo607 ; - assign _dfoo744 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo676 ; - assign _dfoo745 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo609 ; - assign _dfoo746 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo678 ; - assign _dfoo747 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo611 ; - assign _dfoo748 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo680 ; - assign _dfoo750 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo682 ; - assign _dfoo752 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo684 ; - assign _dfoo754 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo686 ; - assign _dfoo756 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo688 ; - assign _dfoo758 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo690 ; - assign _dfoo76 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo8 ; - assign _dfoo760 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo692 ; - assign _dfoo762 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo694 ; - assign _dfoo764 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo696 ; - assign _dfoo766 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo698 ; - assign _dfoo768 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo700 ; - assign _dfoo770 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo702 ; - assign _dfoo772 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo704 ; - assign _dfoo774 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo706 ; - assign _dfoo776 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo708 ; - assign _dfoo778 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo710 ; - assign _dfoo78 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo10 ; - assign _dfoo780 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo712 ; - assign _dfoo782 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo714 ; - assign _dfoo784 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo716 ; - assign _dfoo786 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo718 ; - assign _dfoo788 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo720 ; - assign _dfoo790 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo722 ; - assign _dfoo792 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo724 ; - assign _dfoo794 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo726 ; - assign _dfoo796 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo728 ; - assign _dfoo798 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo730 ; - assign _dfoo8 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo80 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo12 ; - assign _dfoo800 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo732 ; - assign _dfoo802 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo734 ; - assign _dfoo804 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo736 ; - assign _dfoo806 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo738 ; - assign _dfoo808 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo740 ; - assign _dfoo810 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo742 ; - assign _dfoo812 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo744 ; - assign _dfoo814 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo746 ; - assign _dfoo816 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo748 ; - assign _dfoo817 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo681 ; - assign _dfoo818 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo750 ; - assign _dfoo819 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo683 ; - assign _dfoo82 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo14 ; - assign _dfoo820 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo752 ; - assign _dfoo821 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo685 ; - assign _dfoo822 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo754 ; - assign _dfoo823 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo687 ; - assign _dfoo824 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo756 ; - assign _dfoo825 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo689 ; - assign _dfoo826 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo758 ; - assign _dfoo827 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo691 ; - assign _dfoo828 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo760 ; - assign _dfoo829 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo693 ; - assign _dfoo830 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo762 ; - assign _dfoo831 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo695 ; - assign _dfoo832 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo764 ; - assign _dfoo833 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo697 ; - assign _dfoo834 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo766 ; - assign _dfoo835 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo699 ; - assign _dfoo836 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo768 ; - assign _dfoo837 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo701 ; - assign _dfoo838 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo770 ; - assign _dfoo839 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo703 ; - assign _dfoo84 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo16 ; - assign _dfoo840 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo772 ; - assign _dfoo841 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo705 ; - assign _dfoo842 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo774 ; - assign _dfoo843 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo707 ; - assign _dfoo844 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo776 ; - assign _dfoo845 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo709 ; - assign _dfoo846 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo778 ; - assign _dfoo847 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo711 ; - assign _dfoo848 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo780 ; - assign _dfoo849 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo713 ; - assign _dfoo850 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo782 ; - assign _dfoo851 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo715 ; - assign _dfoo852 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo784 ; - assign _dfoo853 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo717 ; - assign _dfoo854 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo786 ; - assign _dfoo855 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo719 ; - assign _dfoo856 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo788 ; - assign _dfoo857 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo721 ; - assign _dfoo858 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo790 ; - assign _dfoo859 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo723 ; - assign _dfoo86 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo18 ; - assign _dfoo860 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo792 ; - assign _dfoo861 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo725 ; - assign _dfoo862 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo794 ; - assign _dfoo863 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo727 ; - assign _dfoo864 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo796 ; - assign _dfoo865 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo729 ; - assign _dfoo866 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo798 ; - assign _dfoo867 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo731 ; - assign _dfoo868 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo800 ; - assign _dfoo869 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo733 ; - assign _dfoo870 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo802 ; - assign _dfoo871 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo735 ; - assign _dfoo872 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo804 ; - assign _dfoo873 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo737 ; - assign _dfoo874 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo806 ; - assign _dfoo875 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo739 ; - assign _dfoo876 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo808 ; - assign _dfoo877 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo741 ; - assign _dfoo878 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo810 ; - assign _dfoo879 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo743 ; - assign _dfoo88 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo20 ; - assign _dfoo880 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo812 ; - assign _dfoo881 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo745 ; - assign _dfoo882 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo814 ; - assign _dfoo883 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo747 ; - assign _dfoo884 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo816 ; - assign _dfoo886 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo818 ; - assign _dfoo888 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo820 ; - assign _dfoo890 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo822 ; - assign _dfoo892 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo824 ; - assign _dfoo894 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo826 ; - assign _dfoo896 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo828 ; - assign _dfoo898 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo830 ; - assign _dfoo9 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo90 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo22 ; - assign _dfoo900 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo832 ; - assign _dfoo902 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo834 ; - assign _dfoo904 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo836 ; - assign _dfoo906 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo838 ; - assign _dfoo908 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo840 ; - assign _dfoo910 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo842 ; - assign _dfoo912 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo844 ; - assign _dfoo914 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo846 ; - assign _dfoo916 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo848 ; - assign _dfoo918 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo850 ; - assign _dfoo92 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo24 ; - assign _dfoo920 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo852 ; - assign _dfoo922 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo854 ; - assign _dfoo924 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo856 ; - assign _dfoo926 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo858 ; - assign _dfoo928 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo860 ; - assign _dfoo930 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo862 ; - assign _dfoo932 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo864 ; - assign _dfoo934 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo866 ; - assign _dfoo936 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo868 ; - assign _dfoo938 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo870 ; - assign _dfoo94 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo26 ; - assign _dfoo940 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo872 ; - assign _dfoo942 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo874 ; - assign _dfoo944 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo876 ; - assign _dfoo946 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo878 ; - assign _dfoo948 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo880 ; - assign _dfoo950 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo882 ; - assign _dfoo952 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo884 ; - assign _dfoo953 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo817 ; - assign _dfoo954 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo886 ; - assign _dfoo955 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo819 ; - assign _dfoo956 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo888 ; - assign _dfoo957 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo821 ; - assign _dfoo958 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo890 ; - assign _dfoo959 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo823 ; - assign _dfoo96 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo28 ; - assign _dfoo960 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo892 ; - assign _dfoo961 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo825 ; - assign _dfoo962 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo894 ; - assign _dfoo963 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo827 ; - assign _dfoo964 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo896 ; - assign _dfoo965 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo829 ; - assign _dfoo966 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo898 ; - assign _dfoo967 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo831 ; - assign _dfoo968 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo900 ; - assign _dfoo969 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo833 ; - assign _dfoo970 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo902 ; - assign _dfoo971 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo835 ; - assign _dfoo972 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo904 ; - assign _dfoo973 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo837 ; - assign _dfoo974 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo906 ; - assign _dfoo975 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo839 ; - assign _dfoo976 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo908 ; - assign _dfoo977 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo841 ; - assign _dfoo978 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo910 ; - assign _dfoo979 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo843 ; - assign _dfoo98 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo30 ; - assign _dfoo980 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo912 ; - assign _dfoo981 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo845 ; - assign _dfoo982 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo914 ; - assign _dfoo983 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo847 ; - assign _dfoo984 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo916 ; - assign _dfoo985 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo849 ; - assign _dfoo986 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo918 ; - assign _dfoo987 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo851 ; - assign _dfoo988 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo920 ; - assign _dfoo989 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo853 ; - assign _dfoo990 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo922 ; - assign _dfoo991 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo855 ; - assign _dfoo992 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo924 ; - assign _dfoo993 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo857 ; - assign _dfoo994 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo926 ; - assign _dfoo995 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo859 ; - assign _dfoo996 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo928 ; - assign _dfoo997 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo861 ; - assign _dfoo998 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo930 ; - assign _dfoo999 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo863 ; - assign a__h71312 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73317 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; - assign addr_offset__h13216 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26929 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71313 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73318 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = - addr_offset__h13216 < 64'h0000000000003000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = - addr_offset__h13216[11:7] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 = - addr_offset__h13216 < 64'h0000000000001000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 = - addr_offset__h13216[11:2] <= 10'd16 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 = - addr_offset__h13216[16:12] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 = - addr_offset__h13216 < 64'h0000000000002000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = - source_id_base__h13630 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26929[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26929[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26929[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26929 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26929[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26929[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26929[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26929[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26929[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26929[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26929[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26929[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26929[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26929[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26929[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26929[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26929[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26929[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26929[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26929[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26929[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26929 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28148 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26929 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26929[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26929[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26929[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && - m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && - m_vvrg_ie_1_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && - m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && - m_vvrg_ie_1_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && - m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && - m_vvrg_ie_1_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && - m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && - m_vvrg_ie_1_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 || - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 || - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 || - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 || - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && - m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && - m_vvrg_ie_1_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && - m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && - m_vvrg_ie_1_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && - m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && - m_vvrg_ie_1_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = - m_vrg_source_ip_16 && - !m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 || - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 || - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 || - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 ; - assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = - m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && - m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && - m_vvrg_ie_1_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && - m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && - m_vvrg_ie_1_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && - m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && - m_vvrg_ie_1_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && - m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && - m_vvrg_ie_1_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && - m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && - m_vvrg_ie_1_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && - m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && - m_vvrg_ie_1_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 || - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 || - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 || - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 || - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && - m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && - m_vvrg_ie_1_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && - m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && - m_vvrg_ie_1_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; - assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 = - m_vrg_source_prio_16 <= - (m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ; - assign max_id__h23959 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ; - assign rdata___1__h26404 = { rdata__h26202[31:0], 32'h0 } ; - assign rdata__h26202 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 64'd0 : - y_avValue_fst__h26194 ; - assign rresp__h26203 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 2'b11 : - y_avValue_snd__h26195 ; - assign source_id__h15665 = { addr_offset__h13216[4:0], 5'd31 } ; - assign source_id__h15772 = { addr_offset__h13216[4:0], 5'd30 } ; - assign source_id__h15845 = { addr_offset__h13216[4:0], 5'd29 } ; - assign source_id__h15918 = { addr_offset__h13216[4:0], 5'd28 } ; - assign source_id__h15991 = { addr_offset__h13216[4:0], 5'd27 } ; - assign source_id__h16064 = { addr_offset__h13216[4:0], 5'd26 } ; - assign source_id__h16137 = { addr_offset__h13216[4:0], 5'd25 } ; - assign source_id__h16210 = { addr_offset__h13216[4:0], 5'd24 } ; - assign source_id__h16283 = { addr_offset__h13216[4:0], 5'd23 } ; - assign source_id__h16356 = { addr_offset__h13216[4:0], 5'd22 } ; - assign source_id__h16429 = { addr_offset__h13216[4:0], 5'd21 } ; - assign source_id__h16502 = { addr_offset__h13216[4:0], 5'd20 } ; - assign source_id__h16575 = { addr_offset__h13216[4:0], 5'd19 } ; - assign source_id__h16648 = { addr_offset__h13216[4:0], 5'd18 } ; - assign source_id__h16721 = { addr_offset__h13216[4:0], 5'd17 } ; - assign source_id__h16794 = { addr_offset__h13216[4:0], 5'd16 } ; - assign source_id__h16867 = { addr_offset__h13216[4:0], 5'd15 } ; - assign source_id__h16940 = { addr_offset__h13216[4:0], 5'd14 } ; - assign source_id__h17013 = { addr_offset__h13216[4:0], 5'd13 } ; - assign source_id__h17086 = { addr_offset__h13216[4:0], 5'd12 } ; - assign source_id__h17159 = { addr_offset__h13216[4:0], 5'd11 } ; - assign source_id__h17232 = { addr_offset__h13216[4:0], 5'd10 } ; - assign source_id__h17305 = { addr_offset__h13216[4:0], 5'd9 } ; - assign source_id__h17378 = { addr_offset__h13216[4:0], 5'd8 } ; - assign source_id__h17451 = { addr_offset__h13216[4:0], 5'd7 } ; - assign source_id__h17524 = { addr_offset__h13216[4:0], 5'd6 } ; - assign source_id__h17597 = { addr_offset__h13216[4:0], 5'd5 } ; - assign source_id__h17670 = { addr_offset__h13216[4:0], 5'd4 } ; - assign source_id__h17743 = { addr_offset__h13216[4:0], 5'd3 } ; - assign source_id__h17816 = { addr_offset__h13216[4:0], 5'd2 } ; - assign source_id__h17889 = { addr_offset__h13216[4:0], 5'd1 } ; - assign source_id__h20137 = 10'd31 + source_id_base__h13630 ; - assign source_id__h20313 = 10'd30 + source_id_base__h13630 ; - assign source_id__h20421 = 10'd29 + source_id_base__h13630 ; - assign source_id__h20529 = 10'd28 + source_id_base__h13630 ; - assign source_id__h20637 = 10'd27 + source_id_base__h13630 ; - assign source_id__h20745 = 10'd26 + source_id_base__h13630 ; - assign source_id__h20853 = 10'd25 + source_id_base__h13630 ; - assign source_id__h20961 = 10'd24 + source_id_base__h13630 ; - assign source_id__h21069 = 10'd23 + source_id_base__h13630 ; - assign source_id__h21177 = 10'd22 + source_id_base__h13630 ; - assign source_id__h21285 = 10'd21 + source_id_base__h13630 ; - assign source_id__h21393 = 10'd20 + source_id_base__h13630 ; - assign source_id__h21501 = 10'd19 + source_id_base__h13630 ; - assign source_id__h21609 = 10'd18 + source_id_base__h13630 ; - assign source_id__h21717 = 10'd17 + source_id_base__h13630 ; - assign source_id__h21825 = 10'd16 + source_id_base__h13630 ; - assign source_id__h21933 = 10'd15 + source_id_base__h13630 ; - assign source_id__h22041 = 10'd14 + source_id_base__h13630 ; - assign source_id__h22149 = 10'd13 + source_id_base__h13630 ; - assign source_id__h22257 = 10'd12 + source_id_base__h13630 ; - assign source_id__h22365 = 10'd11 + source_id_base__h13630 ; - assign source_id__h22473 = 10'd10 + source_id_base__h13630 ; - assign source_id__h22581 = 10'd9 + source_id_base__h13630 ; - assign source_id__h22689 = 10'd8 + source_id_base__h13630 ; - assign source_id__h22797 = 10'd7 + source_id_base__h13630 ; - assign source_id__h22905 = 10'd6 + source_id_base__h13630 ; - assign source_id__h23013 = 10'd5 + source_id_base__h13630 ; - assign source_id__h23121 = 10'd4 + source_id_base__h13630 ; - assign source_id__h23229 = 10'd3 + source_id_base__h13630 ; - assign source_id__h23337 = 10'd2 + source_id_base__h13630 ; - assign source_id__h23445 = 10'd1 + source_id_base__h13630 ; - assign source_id__h29475 = { addr_offset__h26929[4:0], 5'd1 } ; - assign source_id__h30685 = { addr_offset__h26929[4:0], 5'd2 } ; - assign source_id__h31895 = { addr_offset__h26929[4:0], 5'd3 } ; - assign source_id__h33105 = { addr_offset__h26929[4:0], 5'd4 } ; - assign source_id__h34315 = { addr_offset__h26929[4:0], 5'd5 } ; - assign source_id__h35525 = { addr_offset__h26929[4:0], 5'd6 } ; - assign source_id__h36735 = { addr_offset__h26929[4:0], 5'd7 } ; - assign source_id__h37945 = { addr_offset__h26929[4:0], 5'd8 } ; - assign source_id__h39155 = { addr_offset__h26929[4:0], 5'd9 } ; - assign source_id__h40365 = { addr_offset__h26929[4:0], 5'd10 } ; - assign source_id__h41575 = { addr_offset__h26929[4:0], 5'd11 } ; - assign source_id__h42785 = { addr_offset__h26929[4:0], 5'd12 } ; - assign source_id__h43995 = { addr_offset__h26929[4:0], 5'd13 } ; - assign source_id__h45205 = { addr_offset__h26929[4:0], 5'd14 } ; - assign source_id__h46415 = { addr_offset__h26929[4:0], 5'd15 } ; - assign source_id__h47625 = { addr_offset__h26929[4:0], 5'd16 } ; - assign source_id__h48835 = { addr_offset__h26929[4:0], 5'd17 } ; - assign source_id__h50045 = { addr_offset__h26929[4:0], 5'd18 } ; - assign source_id__h51255 = { addr_offset__h26929[4:0], 5'd19 } ; - assign source_id__h52465 = { addr_offset__h26929[4:0], 5'd20 } ; - assign source_id__h53675 = { addr_offset__h26929[4:0], 5'd21 } ; - assign source_id__h54885 = { addr_offset__h26929[4:0], 5'd22 } ; - assign source_id__h56095 = { addr_offset__h26929[4:0], 5'd23 } ; - assign source_id__h57305 = { addr_offset__h26929[4:0], 5'd24 } ; - assign source_id__h58515 = { addr_offset__h26929[4:0], 5'd25 } ; - assign source_id__h59725 = { addr_offset__h26929[4:0], 5'd26 } ; - assign source_id__h60935 = { addr_offset__h26929[4:0], 5'd27 } ; - assign source_id__h62145 = { addr_offset__h26929[4:0], 5'd28 } ; - assign source_id__h63355 = { addr_offset__h26929[4:0], 5'd29 } ; - assign source_id__h64565 = { addr_offset__h26929[4:0], 5'd30 } ; - assign source_id__h65775 = { addr_offset__h26929[4:0], 5'd31 } ; - assign source_id__h67436 = { 5'd0, x__h67487 } ; - assign source_id_base__h13630 = { addr_offset__h13216[4:0], 5'h0 } ; - assign source_id_base__h28148 = { addr_offset__h26929[4:0], 5'h0 } ; - assign v__h13422 = { 61'd0, x__h13493 } ; - assign v__h13671 = { 32'd0, v_ip__h13674 } ; - assign v__h18144 = { 32'd0, v_ie__h18147 } ; - assign v__h23761 = { 61'd0, x__h23832 } ; - assign v__h25455 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ? - v__h25474 : - 64'd0 ; - assign v__h25474 = { 59'd0, max_id__h23959 } ; - assign v__h26934 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? - 2'b11 : - v__h27094 ; - assign v__h27094 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27107 : - v__h27942 ; - assign v__h27107 = - (addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? - 2'b0 : - 2'b10 ; - assign v__h27942 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27961 : - v__h28125 ; - assign v__h27961 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? - 2'b0 : - 2'b10 ; - assign v__h28125 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28144 : - v__h67107 ; - assign v__h28144 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? - 2'b0 : - 2'b10 ; - assign v__h67144 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - 2'b0 : - 2'b10 ; - assign v__h67432 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67476 : - 2'b10 ; - assign v__h67476 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? - 2'b0 : - 2'b10 ; - assign v_ie__h18147 = - { source_id__h20137 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h20313 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h20421 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h20529 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h20637 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h20745 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h20853 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h20961 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h21069 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h21177 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h21285 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h21393 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h21501 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h21609 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h21717 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h21825 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h21933 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h22041 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h22149 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h22257 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h22365 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h22473 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h22581 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h22689 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h22797 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h22905 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h23013 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h23121 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h23229 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h23337 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h23445 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h13674 = - { source_id__h15665 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - source_id__h15772 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - source_id__h15845 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - source_id__h15918 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - source_id__h15991 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - source_id__h16064 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - source_id__h16137 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - source_id__h16210 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - source_id__h16283 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - source_id__h16356 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - source_id__h16429 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - source_id__h16502 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - source_id__h16575 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - source_id__h16648 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - source_id__h16721 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - source_id__h16794 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - source_id__h16867 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - source_id__h16940 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - source_id__h17013 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - source_id__h17086 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - source_id__h17159 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - source_id__h17232 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - source_id__h17305 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - source_id__h17378 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - source_id__h17451 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - source_id__h17524 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - source_id__h17597 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - source_id__h17670 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - source_id__h17743 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - source_id__h17816 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - source_id__h17889 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26930 = - (addr_offset__h26929[2:0] == 3'd4) ? - m_slave_xactor_f_wr_data$D_OUT[72:41] : - m_slave_xactor_f_wr_data$D_OUT[40:9] ; - assign x__h23673 = - { addr_offset__h13216[31:16], 4'd0, addr_offset__h13216[11:0] } ; - assign x__h26361 = - (addr_offset__h13216[2:0] == 3'd4) ? - rdata___1__h26404 : - rdata__h26202 ; - assign x__h67110 = - { addr_offset__h26929[31:16], 4'd0, addr_offset__h26929[11:0] } ; - assign y_avValue_fst__h26094 = (x__h24011 == 5'd0) ? v__h25455 : 64'd0 ; - assign y_avValue_fst__h26115 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_fst__h26094 : - 64'd0 ; - assign y_avValue_fst__h26127 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - v__h23761 : - 64'd0 ; - assign y_avValue_fst__h26143 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - v__h18144 : - 64'd0 ; - assign y_avValue_fst__h26159 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - v__h13671 : - 64'd0 ; - assign y_avValue_fst__h26164 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_fst__h26143 : - y_avValue_fst__h26148 ; - assign y_avValue_fst__h26175 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - v__h13422 : - 64'd0 ; - assign y_avValue_fst__h26180 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_fst__h26159 : - y_avValue_fst__h26164 ; - assign y_avValue_fst__h26194 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_fst__h26175 : - y_avValue_fst__h26180 ; - assign y_avValue_snd__h26095 = (x__h24011 == 5'd0) ? 2'b0 : 2'b10 ; - assign y_avValue_snd__h26116 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_snd__h26095 : - 2'b10 ; - assign y_avValue_snd__h26128 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26144 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26160 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26165 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_snd__h26144 : - y_avValue_snd__h26149 ; - assign y_avValue_snd__h26176 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26181 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_snd__h26160 : - y_avValue_snd__h26165 ; - assign y_avValue_snd__h26195 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_snd__h26176 : - y_avValue_snd__h26181 ; - always@(addr_offset__h13216 or - m_vrg_source_prio_0 or - m_vrg_source_prio_1 or - m_vrg_source_prio_2 or - m_vrg_source_prio_3 or - m_vrg_source_prio_4 or - m_vrg_source_prio_5 or - m_vrg_source_prio_6 or - m_vrg_source_prio_7 or - m_vrg_source_prio_8 or - m_vrg_source_prio_9 or - m_vrg_source_prio_10 or - m_vrg_source_prio_11 or - m_vrg_source_prio_12 or - m_vrg_source_prio_13 or - m_vrg_source_prio_14 or - m_vrg_source_prio_15 or m_vrg_source_prio_16) - begin - case (addr_offset__h13216[11:2]) - 10'd0: x__h13493 = m_vrg_source_prio_0; - 10'd1: x__h13493 = m_vrg_source_prio_1; - 10'd2: x__h13493 = m_vrg_source_prio_2; - 10'd3: x__h13493 = m_vrg_source_prio_3; - 10'd4: x__h13493 = m_vrg_source_prio_4; - 10'd5: x__h13493 = m_vrg_source_prio_5; - 10'd6: x__h13493 = m_vrg_source_prio_6; - 10'd7: x__h13493 = m_vrg_source_prio_7; - 10'd8: x__h13493 = m_vrg_source_prio_8; - 10'd9: x__h13493 = m_vrg_source_prio_9; - 10'd10: x__h13493 = m_vrg_source_prio_10; - 10'd11: x__h13493 = m_vrg_source_prio_11; - 10'd12: x__h13493 = m_vrg_source_prio_12; - 10'd13: x__h13493 = m_vrg_source_prio_13; - 10'd14: x__h13493 = m_vrg_source_prio_14; - 10'd15: x__h13493 = m_vrg_source_prio_15; - 10'd16: x__h13493 = m_vrg_source_prio_16; - default: x__h13493 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_target_threshold_0 or m_vrg_target_threshold_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h23832 = m_vrg_target_threshold_0; - 5'd1: x__h23832 = m_vrg_target_threshold_1; - default: x__h23832 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h24011 = m_vrg_servicing_source_0; - 5'd1: x__h24011 = m_vrg_servicing_source_1; - default: x__h24011 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h26929 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h26929[16:12]) - 5'd0: x__h67487 = m_vrg_servicing_source_0; - 5'd1: x__h67487 = m_vrg_servicing_source_1; - default: x__h67487 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15665 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15665) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15772 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15772) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15845 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15845) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15918 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15918) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15991 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15991) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16064 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16064) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17159 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17159) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16137 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16137) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16210 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16210) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16283 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16283) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16356 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16356) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16429 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16429) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16502 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16502) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16575 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16575) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16648 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16648) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16721 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16721) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16794 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16794) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16867 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16867) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16940 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16940) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17013 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17013) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17086 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17086) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17232 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17232) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17305 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17305) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17378 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17378) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17451 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17451) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17524 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17524) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17597 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17597) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17670 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17670) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17743 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17743) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17889 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17889) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17816 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17816) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_snd__h26128 or y_avValue_snd__h26116) - begin - case (x__h23673) - 32'h00200000: y_avValue_snd__h26149 = y_avValue_snd__h26128; - 32'h00200004: y_avValue_snd__h26149 = y_avValue_snd__h26116; - default: y_avValue_snd__h26149 = 2'b10; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_0_1; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_1_1; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_0_2; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_1_2; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_0_3; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_1_3; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_0_4; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_1_4; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_0_5; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_1_5; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_0_6; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_1_6; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_0_7; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_1_7; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_0_8; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_1_8; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_0_9; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_1_9; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_0_10; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_1_10; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_0_11; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_1_11; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_0_12; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_1_12; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_0_13; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_1_13; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_0_14; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_1_14; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_0_15; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_1_15; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_0_16; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_1_16; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_fst__h26127 or y_avValue_fst__h26115) - begin - case (x__h23673) - 32'h00200000: y_avValue_fst__h26148 = y_avValue_fst__h26127; - 32'h00200004: y_avValue_fst__h26148 = y_avValue_fst__h26115; - default: y_avValue_fst__h26148 = 64'd0; - endcase - end - always@(source_id__h67436 or - m_vrg_source_busy_0 or - m_vrg_source_busy_1 or - m_vrg_source_busy_2 or - m_vrg_source_busy_3 or - m_vrg_source_busy_4 or - m_vrg_source_busy_5 or - m_vrg_source_busy_6 or - m_vrg_source_busy_7 or - m_vrg_source_busy_8 or - m_vrg_source_busy_9 or - m_vrg_source_busy_10 or - m_vrg_source_busy_11 or - m_vrg_source_busy_12 or - m_vrg_source_busy_13 or - m_vrg_source_busy_14 or - m_vrg_source_busy_15 or m_vrg_source_busy_16) - begin - case (source_id__h67436) - 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_0; - 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_1; - 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_2; - 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_3; - 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_4; - 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_5; - 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_6; - 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_7; - 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_8; - 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_9; - 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_10; - 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_11; - 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_12; - 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_13; - 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_14; - 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_15; - 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h67110 or v__h67144 or v__h67432) - begin - case (x__h67110) - 32'h00200000: v__h67107 = v__h67144; - 32'h00200004: v__h67107 = v__h67432; - default: v__h67107 = 2'b10; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_cfg_verbosity$EN) - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN; - if (m_vrg_servicing_source_0$EN) - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_0$D_IN; - if (m_vrg_servicing_source_1$EN) - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_1$D_IN; - if (m_vrg_source_busy_0$EN) - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_0$D_IN; - if (m_vrg_source_busy_1$EN) - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_1$D_IN; - if (m_vrg_source_busy_10$EN) - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_10$D_IN; - if (m_vrg_source_busy_11$EN) - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_11$D_IN; - if (m_vrg_source_busy_12$EN) - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_12$D_IN; - if (m_vrg_source_busy_13$EN) - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_13$D_IN; - if (m_vrg_source_busy_14$EN) - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_14$D_IN; - if (m_vrg_source_busy_15$EN) - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_15$D_IN; - if (m_vrg_source_busy_16$EN) - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_16$D_IN; - if (m_vrg_source_busy_2$EN) - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_2$D_IN; - if (m_vrg_source_busy_3$EN) - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_3$D_IN; - if (m_vrg_source_busy_4$EN) - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_4$D_IN; - if (m_vrg_source_busy_5$EN) - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_5$D_IN; - if (m_vrg_source_busy_6$EN) - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_6$D_IN; - if (m_vrg_source_busy_7$EN) - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_7$D_IN; - if (m_vrg_source_busy_8$EN) - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_8$D_IN; - if (m_vrg_source_busy_9$EN) - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_9$D_IN; - if (m_vrg_source_ip_0$EN) - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_0$D_IN; - if (m_vrg_source_ip_1$EN) - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_1$D_IN; - if (m_vrg_source_ip_10$EN) - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_10$D_IN; - if (m_vrg_source_ip_11$EN) - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_11$D_IN; - if (m_vrg_source_ip_12$EN) - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_12$D_IN; - if (m_vrg_source_ip_13$EN) - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_13$D_IN; - if (m_vrg_source_ip_14$EN) - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_14$D_IN; - if (m_vrg_source_ip_15$EN) - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_15$D_IN; - if (m_vrg_source_ip_16$EN) - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_16$D_IN; - if (m_vrg_source_ip_2$EN) - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_2$D_IN; - if (m_vrg_source_ip_3$EN) - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_3$D_IN; - if (m_vrg_source_ip_4$EN) - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_4$D_IN; - if (m_vrg_source_ip_5$EN) - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_5$D_IN; - if (m_vrg_source_ip_6$EN) - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_6$D_IN; - if (m_vrg_source_ip_7$EN) - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_7$D_IN; - if (m_vrg_source_ip_8$EN) - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_8$D_IN; - if (m_vrg_source_ip_9$EN) - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_9$D_IN; - if (m_vrg_source_prio_0$EN) - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_0$D_IN; - if (m_vrg_source_prio_1$EN) - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_1$D_IN; - if (m_vrg_source_prio_10$EN) - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_10$D_IN; - if (m_vrg_source_prio_11$EN) - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_11$D_IN; - if (m_vrg_source_prio_12$EN) - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_12$D_IN; - if (m_vrg_source_prio_13$EN) - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_13$D_IN; - if (m_vrg_source_prio_14$EN) - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_14$D_IN; - if (m_vrg_source_prio_15$EN) - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_15$D_IN; - if (m_vrg_source_prio_16$EN) - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_16$D_IN; - if (m_vrg_source_prio_2$EN) - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_2$D_IN; - if (m_vrg_source_prio_3$EN) - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_3$D_IN; - if (m_vrg_source_prio_4$EN) - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_4$D_IN; - if (m_vrg_source_prio_5$EN) - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_5$D_IN; - if (m_vrg_source_prio_6$EN) - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_6$D_IN; - if (m_vrg_source_prio_7$EN) - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_7$D_IN; - if (m_vrg_source_prio_8$EN) - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_8$D_IN; - if (m_vrg_source_prio_9$EN) - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_9$D_IN; - if (m_vrg_target_threshold_0$EN) - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_0$D_IN; - if (m_vrg_target_threshold_1$EN) - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_1$D_IN; - if (m_vvrg_ie_0_0$EN) - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_0$D_IN; - if (m_vvrg_ie_0_1$EN) - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_1$D_IN; - if (m_vvrg_ie_0_10$EN) - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_10$D_IN; - if (m_vvrg_ie_0_11$EN) - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_11$D_IN; - if (m_vvrg_ie_0_12$EN) - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_12$D_IN; - if (m_vvrg_ie_0_13$EN) - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_13$D_IN; - if (m_vvrg_ie_0_14$EN) - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_14$D_IN; - if (m_vvrg_ie_0_15$EN) - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_15$D_IN; - if (m_vvrg_ie_0_16$EN) - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_16$D_IN; - if (m_vvrg_ie_0_2$EN) - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_2$D_IN; - if (m_vvrg_ie_0_3$EN) - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_3$D_IN; - if (m_vvrg_ie_0_4$EN) - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_4$D_IN; - if (m_vvrg_ie_0_5$EN) - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_5$D_IN; - if (m_vvrg_ie_0_6$EN) - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_6$D_IN; - if (m_vvrg_ie_0_7$EN) - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_7$D_IN; - if (m_vvrg_ie_0_8$EN) - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_8$D_IN; - if (m_vvrg_ie_0_9$EN) - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_9$D_IN; - if (m_vvrg_ie_1_0$EN) - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_0$D_IN; - if (m_vvrg_ie_1_1$EN) - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_1$D_IN; - if (m_vvrg_ie_1_10$EN) - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_10$D_IN; - if (m_vvrg_ie_1_11$EN) - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_11$D_IN; - if (m_vvrg_ie_1_12$EN) - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_12$D_IN; - if (m_vvrg_ie_1_13$EN) - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_13$D_IN; - if (m_vvrg_ie_1_14$EN) - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_14$D_IN; - if (m_vvrg_ie_1_15$EN) - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_15$D_IN; - if (m_vvrg_ie_1_16$EN) - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_16$D_IN; - if (m_vvrg_ie_1_2$EN) - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_2$D_IN; - if (m_vvrg_ie_1_3$EN) - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_3$D_IN; - if (m_vvrg_ie_1_4$EN) - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_4$D_IN; - if (m_vvrg_ie_1_5$EN) - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_5$D_IN; - if (m_vvrg_ie_1_6$EN) - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_6$D_IN; - if (m_vvrg_ie_1_7$EN) - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_7$D_IN; - if (m_vvrg_ie_1_8$EN) - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_8$D_IN; - if (m_vvrg_ie_1_9$EN) - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_9$D_IN; - end - if (m_rg_addr_base$EN) - m_rg_addr_base <= `BSV_ASSIGNMENT_DELAY m_rg_addr_base$D_IN; - if (m_rg_addr_lim$EN) - m_rg_addr_lim <= `BSV_ASSIGNMENT_DELAY m_rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_cfg_verbosity = 4'hA; - m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - m_vrg_servicing_source_0 = 5'h0A; - m_vrg_servicing_source_1 = 5'h0A; - m_vrg_source_busy_0 = 1'h0; - m_vrg_source_busy_1 = 1'h0; - m_vrg_source_busy_10 = 1'h0; - m_vrg_source_busy_11 = 1'h0; - m_vrg_source_busy_12 = 1'h0; - m_vrg_source_busy_13 = 1'h0; - m_vrg_source_busy_14 = 1'h0; - m_vrg_source_busy_15 = 1'h0; - m_vrg_source_busy_16 = 1'h0; - m_vrg_source_busy_2 = 1'h0; - m_vrg_source_busy_3 = 1'h0; - m_vrg_source_busy_4 = 1'h0; - m_vrg_source_busy_5 = 1'h0; - m_vrg_source_busy_6 = 1'h0; - m_vrg_source_busy_7 = 1'h0; - m_vrg_source_busy_8 = 1'h0; - m_vrg_source_busy_9 = 1'h0; - m_vrg_source_ip_0 = 1'h0; - m_vrg_source_ip_1 = 1'h0; - m_vrg_source_ip_10 = 1'h0; - m_vrg_source_ip_11 = 1'h0; - m_vrg_source_ip_12 = 1'h0; - m_vrg_source_ip_13 = 1'h0; - m_vrg_source_ip_14 = 1'h0; - m_vrg_source_ip_15 = 1'h0; - m_vrg_source_ip_16 = 1'h0; - m_vrg_source_ip_2 = 1'h0; - m_vrg_source_ip_3 = 1'h0; - m_vrg_source_ip_4 = 1'h0; - m_vrg_source_ip_5 = 1'h0; - m_vrg_source_ip_6 = 1'h0; - m_vrg_source_ip_7 = 1'h0; - m_vrg_source_ip_8 = 1'h0; - m_vrg_source_ip_9 = 1'h0; - m_vrg_source_prio_0 = 3'h2; - m_vrg_source_prio_1 = 3'h2; - m_vrg_source_prio_10 = 3'h2; - m_vrg_source_prio_11 = 3'h2; - m_vrg_source_prio_12 = 3'h2; - m_vrg_source_prio_13 = 3'h2; - m_vrg_source_prio_14 = 3'h2; - m_vrg_source_prio_15 = 3'h2; - m_vrg_source_prio_16 = 3'h2; - m_vrg_source_prio_2 = 3'h2; - m_vrg_source_prio_3 = 3'h2; - m_vrg_source_prio_4 = 3'h2; - m_vrg_source_prio_5 = 3'h2; - m_vrg_source_prio_6 = 3'h2; - m_vrg_source_prio_7 = 3'h2; - m_vrg_source_prio_8 = 3'h2; - m_vrg_source_prio_9 = 3'h2; - m_vrg_target_threshold_0 = 3'h2; - m_vrg_target_threshold_1 = 3'h2; - m_vvrg_ie_0_0 = 1'h0; - m_vvrg_ie_0_1 = 1'h0; - m_vvrg_ie_0_10 = 1'h0; - m_vvrg_ie_0_11 = 1'h0; - m_vvrg_ie_0_12 = 1'h0; - m_vvrg_ie_0_13 = 1'h0; - m_vvrg_ie_0_14 = 1'h0; - m_vvrg_ie_0_15 = 1'h0; - m_vvrg_ie_0_16 = 1'h0; - m_vvrg_ie_0_2 = 1'h0; - m_vvrg_ie_0_3 = 1'h0; - m_vvrg_ie_0_4 = 1'h0; - m_vvrg_ie_0_5 = 1'h0; - m_vvrg_ie_0_6 = 1'h0; - m_vvrg_ie_0_7 = 1'h0; - m_vvrg_ie_0_8 = 1'h0; - m_vvrg_ie_0_9 = 1'h0; - m_vvrg_ie_1_0 = 1'h0; - m_vvrg_ie_1_1 = 1'h0; - m_vvrg_ie_1_10 = 1'h0; - m_vvrg_ie_1_11 = 1'h0; - m_vvrg_ie_1_12 = 1'h0; - m_vvrg_ie_1_13 = 1'h0; - m_vvrg_ie_1_14 = 1'h0; - m_vvrg_ie_1_15 = 1'h0; - m_vvrg_ie_1_16 = 1'h0; - m_vvrg_ie_1_2 = 1'h0; - m_vvrg_ie_1_3 = 1'h0; - m_vvrg_ie_1_4 = 1'h0; - m_vvrg_ie_1_5 = 1'h0; - m_vvrg_ie_1_6 = 1'h0; - m_vvrg_ie_1_7 = 1'h0; - m_vvrg_ie_1_8 = 1'h0; - m_vvrg_ie_1_9 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src IPs :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src Prios:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src busy :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71312, - m_vrg_target_threshold_0, - b__h71313, - m_vrg_servicing_source_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73317, - m_vrg_target_threshold_1, - b__h73318, - m_vrg_servicing_source_1); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - begin - v__h75676 = $stime; - #0; - end - v__h75670 = v__h75676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75670, - $signed(32'd1), - v_sources_0_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - begin - v__h75874 = $stime; - #0; - end - v__h75868 = v__h75874 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75868, - $signed(32'd2), - v_sources_1_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - begin - v__h76072 = $stime; - #0; - end - v__h76066 = v__h76072 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76066, - $signed(32'd3), - v_sources_2_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - begin - v__h76270 = $stime; - #0; - end - v__h76264 = v__h76270 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76264, - $signed(32'd4), - v_sources_3_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - begin - v__h76468 = $stime; - #0; - end - v__h76462 = v__h76468 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76462, - $signed(32'd5), - v_sources_4_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - begin - v__h76666 = $stime; - #0; - end - v__h76660 = v__h76666 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76660, - $signed(32'd6), - v_sources_5_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - begin - v__h76864 = $stime; - #0; - end - v__h76858 = v__h76864 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76858, - $signed(32'd7), - v_sources_6_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - begin - v__h77062 = $stime; - #0; - end - v__h77056 = v__h77062 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77056, - $signed(32'd8), - v_sources_7_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - begin - v__h77260 = $stime; - #0; - end - v__h77254 = v__h77260 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77254, - $signed(32'd9), - v_sources_8_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - begin - v__h77458 = $stime; - #0; - end - v__h77452 = v__h77458 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77452, - $signed(32'd10), - v_sources_9_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - begin - v__h77656 = $stime; - #0; - end - v__h77650 = v__h77656 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77650, - $signed(32'd11), - v_sources_10_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - begin - v__h77854 = $stime; - #0; - end - v__h77848 = v__h77854 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77848, - $signed(32'd12), - v_sources_11_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - begin - v__h78052 = $stime; - #0; - end - v__h78046 = v__h78052 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78046, - $signed(32'd13), - v_sources_12_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - begin - v__h78250 = $stime; - #0; - end - v__h78244 = v__h78250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78244, - $signed(32'd14), - v_sources_13_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - begin - v__h78448 = $stime; - #0; - end - v__h78442 = v__h78448 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78442, - $signed(32'd15), - v_sources_14_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - begin - v__h78646 = $stime; - #0; - end - v__h78640 = v__h78646 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78640, - $signed(32'd16), - v_sources_15_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - begin - v__h6144 = $stime; - #0; - end - v__h6138 = v__h6144 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h6138); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h13080 = $stime; - #0; - end - v__h13074 = v__h13080 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req:", v__h13074); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - begin - v__h13265 = $stime; - #0; - end - v__h13259 = v__h13265 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h13259); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - begin - v__h13463 = $stime; - #0; - end - v__h13457 = v__h13463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h13457, - addr_offset__h13216[11:2], - v__h13422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - begin - v__h13713 = $stime; - #0; - end - v__h13707 = v__h13713 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h13707, - source_id_base__h13630, - v__h13671); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - begin - v__h18186 = $stime; - #0; - end - v__h18180 = v__h18186 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h18180, - source_id_base__h13630, - v__h18144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - begin - v__h23802 = $stime; - #0; - end - v__h23796 = v__h23802 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h23796, - addr_offset__h13216[16:12], - v__h23761); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - begin - v__h25975 = $stime; - #0; - end - v__h25969 = v__h25975 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h25969, - addr_offset__h13216[16:12], - v__h25474); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - begin - v__h24056 = $stime; - #0; - end - v__h24050 = v__h24056 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h24050, - addr_offset__h13216[16:12]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Still servicing interrupt from source %0d", x__h24011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Trying to claim service for source %0d", - max_id__h23959); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Ignoring."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - begin - v__h26250 = $stime; - #0; - end - v__h26244 = v__h26250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h26244); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26463 = $stime; - #0; - end - v__h26457 = v__h26463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req", v__h26457); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", x__h26361); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", rresp__h26203); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26740 = $stime; - #0; - end - v__h26734 = v__h26740 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26734); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - begin - v__h26968 = $stime; - #0; - end - v__h26962 = v__h26968 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26962); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - begin - v__h27865 = $stime; - #0; - end - v__h27859 = v__h27865 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27859, - addr_offset__h26929[11:2], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - begin - v__h28048 = $stime; - #0; - end - v__h28042 = v__h28048 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28042, - source_id_base__h28148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - begin - v__h67030 = $stime; - #0; - end - v__h67024 = v__h67030 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67024, - addr_offset__h26929[11:7], - source_id_base__h28148, - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - begin - v__h67318 = $stime; - #0; - end - v__h67312 = v__h67318 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67312, - addr_offset__h26929[16:12], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - begin - v__h67847 = $stime; - #0; - end - v__h67841 = v__h67847 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67841, - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - begin - v__h67933 = $stime; - #0; - end - v__h67927 = v__h67933 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67927); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Completion message from target %0d to source %0d", - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Ignoring"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - begin - v__h68132 = $stime; - #0; - end - v__h68126 = v__h68132 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68126); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h68353 = $stime; - #0; - end - v__h68347 = v__h68353 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68347); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26934); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h74690 = $stime; - #0; - end - v__h74684 = v__h74690 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74684, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h74800 = $stime; - #0; - end - v__h74794 = v__h74800 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74794, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - begin - v__h74913 = $stime; - #0; - end - v__h74907 = v__h74913 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74907, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkPLIC_16_2_7 - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v deleted file mode 100644 index 570d9b06..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v +++ /dev/null @@ -1,663 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_req_reset O 1 const -// RDY_rsp_reset O 1 const -// valid O 1 -// word O 32 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_is_OP_not_OP_32 I 1 reg -// req_f3 I 3 -// req_v1 I 32 -// req_v2 I 32 -// EN_set_verbosity I 1 -// EN_req_reset I 1 unused -// EN_rsp_reset I 1 unused -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkRISCV_MBox(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_req_reset, - RDY_req_reset, - - EN_rsp_reset, - RDY_rsp_reset, - - req_is_OP_not_OP_32, - req_f3, - req_v1, - req_v2, - EN_req, - - valid, - - word); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method req_reset - input EN_req_reset; - output RDY_req_reset; - - // action method rsp_reset - input EN_rsp_reset; - output RDY_rsp_reset; - - // action method req - input req_is_OP_not_OP_32; - input [2 : 0] req_f3; - input [31 : 0] req_v1; - input [31 : 0] req_v2; - input EN_req; - - // value method valid - output valid; - - // value method word - output [31 : 0] word; - - // signals for module outputs - wire [31 : 0] word; - wire RDY_req_reset, RDY_rsp_reset, RDY_set_verbosity, valid; - - // inlined wires - wire dw_valid$whas; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register intDiv_rg_denom2 - reg [31 : 0] intDiv_rg_denom2; - reg [31 : 0] intDiv_rg_denom2$D_IN; - wire intDiv_rg_denom2$EN; - - // register intDiv_rg_denom_is_signed - reg intDiv_rg_denom_is_signed; - wire intDiv_rg_denom_is_signed$D_IN, intDiv_rg_denom_is_signed$EN; - - // register intDiv_rg_n - reg [31 : 0] intDiv_rg_n; - reg [31 : 0] intDiv_rg_n$D_IN; - wire intDiv_rg_n$EN; - - // register intDiv_rg_numer_is_signed - reg intDiv_rg_numer_is_signed; - wire intDiv_rg_numer_is_signed$D_IN, intDiv_rg_numer_is_signed$EN; - - // register intDiv_rg_quo - reg [31 : 0] intDiv_rg_quo; - reg [31 : 0] intDiv_rg_quo$D_IN; - wire intDiv_rg_quo$EN; - - // register intDiv_rg_quoIsNeg - reg intDiv_rg_quoIsNeg; - wire intDiv_rg_quoIsNeg$D_IN, intDiv_rg_quoIsNeg$EN; - - // register intDiv_rg_remIsNeg - reg intDiv_rg_remIsNeg; - wire intDiv_rg_remIsNeg$D_IN, intDiv_rg_remIsNeg$EN; - - // register intDiv_rg_state - reg [2 : 0] intDiv_rg_state; - reg [2 : 0] intDiv_rg_state$D_IN; - wire intDiv_rg_state$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_is_OP_not_OP_32 - reg rg_is_OP_not_OP_32; - wire rg_is_OP_not_OP_32$D_IN, rg_is_OP_not_OP_32$EN; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_v1 - reg [31 : 0] rg_v1; - reg [31 : 0] rg_v1$D_IN; - wire rg_v1$EN; - - // register rg_v2 - reg [31 : 0] rg_v2; - wire [31 : 0] rg_v2$D_IN; - wire rg_v2$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_intDiv_rl_loop1, - CAN_FIRE_RL_intDiv_rl_loop2, - CAN_FIRE_RL_intDiv_rl_start_div_by_zero, - CAN_FIRE_RL_intDiv_rl_start_overflow, - CAN_FIRE_RL_intDiv_rl_start_s, - CAN_FIRE_RL_rg_div_rem, - CAN_FIRE_RL_rl_mul, - CAN_FIRE_RL_rl_mul2, - CAN_FIRE_req, - CAN_FIRE_req_reset, - CAN_FIRE_rsp_reset, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_intDiv_rl_loop1, - WILL_FIRE_RL_intDiv_rl_loop2, - WILL_FIRE_RL_intDiv_rl_start_div_by_zero, - WILL_FIRE_RL_intDiv_rl_start_overflow, - WILL_FIRE_RL_intDiv_rl_start_s, - WILL_FIRE_RL_rg_div_rem, - WILL_FIRE_RL_rl_mul, - WILL_FIRE_RL_rl_mul2, - WILL_FIRE_req, - WILL_FIRE_req_reset, - WILL_FIRE_rsp_reset, - WILL_FIRE_set_verbosity; - - // inputs to muxes for submodule ports - wire [31 : 0] MUX_dw_result$wset_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_1, - MUX_intDiv_rg_denom2$write_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_3, - MUX_intDiv_rg_n$write_1__VAL_1, - MUX_intDiv_rg_n$write_1__VAL_2, - MUX_intDiv_rg_quo$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_2, - MUX_rg_v1$write_1__VAL_3, - MUX_rg_v1$write_1__VAL_4; - wire [1 : 0] MUX_rg_state$write_1__VAL_1; - wire MUX_intDiv_rg_denom2$write_1__SEL_1, - MUX_intDiv_rg_denom2$write_1__SEL_2, - MUX_intDiv_rg_quo$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_2, - MUX_intDiv_rg_state$write_1__SEL_3, - MUX_rg_v1$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h3263; - reg [31 : 0] v__h3257; - // synopsys translate_on - - // remaining internal signals - wire [127 : 0] SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113, - SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105, - _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110; - wire [63 : 0] SEXT_rg_v1____d103, rg_v1_MUL_rg_v2___d100, v1__h3150; - wire [31 : 0] _theResult___fst__h787, - _theResult___snd_fst__h782, - denom___1__h729, - numer___1__h728, - v__h3074, - v__h3132, - v__h3183, - x__h2611, - x__h2697, - x__h2767, - x__h2782, - y__h2490; - wire IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39, - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47, - rg_v1_ULT_intDiv_rg_denom2_4___d59, - rg_v1_ULT_rg_v2___d55; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method req_reset - assign RDY_req_reset = 1'd1 ; - assign CAN_FIRE_req_reset = 1'd1 ; - assign WILL_FIRE_req_reset = EN_req_reset ; - - // action method rsp_reset - assign RDY_rsp_reset = 1'd1 ; - assign CAN_FIRE_rsp_reset = 1'd1 ; - assign WILL_FIRE_rsp_reset = EN_rsp_reset ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method word - assign word = WILL_FIRE_RL_rl_mul2 ? rg_v1 : MUX_dw_result$wset_1__VAL_2 ; - - // rule RL_rl_mul2 - assign CAN_FIRE_RL_rl_mul2 = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_mul2 = CAN_FIRE_RL_rl_mul2 ; - - // rule RL_rg_div_rem - assign CAN_FIRE_RL_rg_div_rem = - rg_state == 2'd2 && intDiv_rg_state == 3'd4 ; - assign WILL_FIRE_RL_rg_div_rem = CAN_FIRE_RL_rg_div_rem ; - - // rule RL_intDiv_rl_start_div_by_zero - assign CAN_FIRE_RL_intDiv_rl_start_div_by_zero = - intDiv_rg_state == 3'd1 && rg_v2 == 32'd0 ; - assign WILL_FIRE_RL_intDiv_rl_start_div_by_zero = - CAN_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // rule RL_intDiv_rl_start_overflow - assign CAN_FIRE_RL_intDiv_rl_start_overflow = - intDiv_rg_state == 3'd1 && intDiv_rg_numer_is_signed && - rg_v1 == 32'h80000000 && - intDiv_rg_denom_is_signed && - rg_v2 == 32'hFFFFFFFF ; - assign WILL_FIRE_RL_intDiv_rl_start_overflow = - CAN_FIRE_RL_intDiv_rl_start_overflow && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_start_s - assign CAN_FIRE_RL_intDiv_rl_start_s = - intDiv_rg_state == 3'd1 && rg_v2 != 32'd0 && - (!intDiv_rg_numer_is_signed || rg_v1 != 32'h80000000 || - !intDiv_rg_denom_is_signed || - rg_v2 != 32'hFFFFFFFF) ; - assign WILL_FIRE_RL_intDiv_rl_start_s = - CAN_FIRE_RL_intDiv_rl_start_s && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_loop1 - assign CAN_FIRE_RL_intDiv_rl_loop1 = intDiv_rg_state == 3'd2 ; - assign WILL_FIRE_RL_intDiv_rl_loop1 = CAN_FIRE_RL_intDiv_rl_loop1 ; - - // rule RL_rl_mul - assign CAN_FIRE_RL_rl_mul = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_mul = rg_state == 2'd0 ; - - // rule RL_intDiv_rl_loop2 - assign CAN_FIRE_RL_intDiv_rl_loop2 = intDiv_rg_state == 3'd3 ; - assign WILL_FIRE_RL_intDiv_rl_loop2 = - CAN_FIRE_RL_intDiv_rl_loop2 && !WILL_FIRE_RL_rl_mul ; - - // inputs to muxes for submodule ports - assign MUX_intDiv_rg_denom2$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 ; - assign MUX_intDiv_rg_denom2$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 ; - assign MUX_intDiv_rg_quo$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_quoIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_intDiv_rg_state$write_1__SEL_1 = EN_req && req_f3[2] ; - assign MUX_intDiv_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 ; - assign MUX_intDiv_rg_state$write_1__SEL_3 = - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 ; - assign MUX_rg_v1$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_remIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_dw_result$wset_1__VAL_2 = rg_f3[1] ? rg_v1 : intDiv_rg_quo ; - assign MUX_intDiv_rg_denom2$write_1__VAL_1 = - { intDiv_rg_denom2[30:0], 1'd0 } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_2 = - { 1'd0, intDiv_rg_denom2[31:1] } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_3 = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - denom___1__h729 : - _theResult___snd_fst__h782 ; - assign MUX_intDiv_rg_n$write_1__VAL_1 = { intDiv_rg_n[30:0], 1'd0 } ; - assign MUX_intDiv_rg_n$write_1__VAL_2 = { 1'd0, intDiv_rg_n[31:1] } ; - assign MUX_intDiv_rg_quo$write_1__VAL_1 = - rg_v1_ULT_rg_v2___d55 ? x__h2697 : x__h2782 ; - assign MUX_rg_state$write_1__VAL_1 = req_f3[2] ? 2'd2 : 2'd0 ; - assign MUX_rg_v1$write_1__VAL_2 = - rg_v1_ULT_rg_v2___d55 ? x__h2767 : x__h2611 ; - assign MUX_rg_v1$write_1__VAL_3 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - rg_v1_MUL_rg_v2___d100[31:0] : - v__h3074 ; - assign MUX_rg_v1$write_1__VAL_4 = - intDiv_rg_numer_is_signed ? numer___1__h728 : rg_v1 ; - - // inlined wires - assign dw_valid$whas = WILL_FIRE_RL_rg_div_rem || WILL_FIRE_RL_rl_mul2 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register intDiv_rg_denom2 - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_denom2$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_denom2$write_1__VAL_2 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_intDiv_rg_denom2$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_3; - default: intDiv_rg_denom2$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_denom2$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_denom_is_signed - assign intDiv_rg_denom_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_denom_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_n - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_n$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_n$write_1__VAL_2 or WILL_FIRE_RL_intDiv_rl_start_s) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_n$D_IN = 32'd1; - default: intDiv_rg_n$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_n$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_numer_is_signed - assign intDiv_rg_numer_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_numer_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_quo - always@(MUX_intDiv_rg_quo$write_1__SEL_1 or - MUX_intDiv_rg_quo$write_1__VAL_1 or - WILL_FIRE_RL_intDiv_rl_start_overflow or - rg_v1 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_quo$write_1__SEL_1: - intDiv_rg_quo$D_IN = MUX_intDiv_rg_quo$write_1__VAL_1; - WILL_FIRE_RL_intDiv_rl_start_overflow: intDiv_rg_quo$D_IN = rg_v1; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_quo$D_IN = 32'd0; - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_quo$D_IN = 32'hFFFFFFFF; - default: intDiv_rg_quo$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_quo$EN = - MUX_intDiv_rg_quo$write_1__SEL_1 || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register intDiv_rg_quoIsNeg - assign intDiv_rg_quoIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[31] != rg_v2[31] : - IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39 ; - assign intDiv_rg_quoIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_remIsNeg - assign intDiv_rg_remIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[31] : - intDiv_rg_numer_is_signed && rg_v1[31] ; - assign intDiv_rg_remIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_state - always@(MUX_intDiv_rg_state$write_1__SEL_1 or - MUX_intDiv_rg_state$write_1__SEL_2 or - MUX_intDiv_rg_state$write_1__SEL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_overflow or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - case (1'b1) - MUX_intDiv_rg_state$write_1__SEL_1: intDiv_rg_state$D_IN = 3'd1; - MUX_intDiv_rg_state$write_1__SEL_2: intDiv_rg_state$D_IN = 3'd4; - MUX_intDiv_rg_state$write_1__SEL_3: intDiv_rg_state$D_IN = 3'd3; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_state$D_IN = 3'd2; - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_state$D_IN = 3'd4; - default: intDiv_rg_state$D_IN = 3'b010 /* unspecified value */ ; - endcase - assign intDiv_rg_state$EN = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 || - EN_req && req_f3[2] || - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_is_OP_not_OP_32 - assign rg_is_OP_not_OP_32$D_IN = req_is_OP_not_OP_32 ; - assign rg_is_OP_not_OP_32$EN = EN_req ; - - // register rg_state - assign rg_state$D_IN = EN_req ? MUX_rg_state$write_1__VAL_1 : 2'd1 ; - assign rg_state$EN = EN_req || WILL_FIRE_RL_rl_mul ; - - // register rg_v1 - always@(EN_req or - req_v1 or - MUX_rg_v1$write_1__SEL_2 or - MUX_rg_v1$write_1__VAL_2 or - WILL_FIRE_RL_rl_mul or - MUX_rg_v1$write_1__VAL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_rg_v1$write_1__VAL_4 or WILL_FIRE_RL_intDiv_rl_start_overflow) - case (1'b1) - EN_req: rg_v1$D_IN = req_v1; - MUX_rg_v1$write_1__SEL_2: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_2; - WILL_FIRE_RL_rl_mul: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_3; - WILL_FIRE_RL_intDiv_rl_start_s: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_4; - WILL_FIRE_RL_intDiv_rl_start_overflow: rg_v1$D_IN = 32'd0; - default: rg_v1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - assign rg_v1$EN = - MUX_rg_v1$write_1__SEL_2 || EN_req || WILL_FIRE_RL_rl_mul || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow ; - - // register rg_v2 - assign rg_v2$D_IN = EN_req ? req_v2 : MUX_intDiv_rg_denom2$write_1__VAL_3 ; - assign rg_v2$EN = EN_req || WILL_FIRE_RL_intDiv_rl_start_s ; - - // remaining internal signals - assign IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39 = - intDiv_rg_numer_is_signed ? - rg_v1[31] : - intDiv_rg_denom_is_signed && rg_v2[31] ; - assign SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113 = - SEXT_rg_v1____d103 * { 32'd0, rg_v2 } ; - assign SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105 = - SEXT_rg_v1____d103 * { {32{rg_v2[31]}}, rg_v2 } ; - assign SEXT_rg_v1____d103 = { {32{rg_v1[31]}}, rg_v1 } ; - assign _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110 = - v1__h3150 * { 32'd0, rg_v2 } ; - assign _theResult___fst__h787 = - intDiv_rg_denom_is_signed ? denom___1__h729 : rg_v2 ; - assign _theResult___snd_fst__h782 = - intDiv_rg_numer_is_signed ? rg_v2 : _theResult___fst__h787 ; - assign denom___1__h729 = rg_v2[31] ? -rg_v2 : rg_v2 ; - assign intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 = - intDiv_rg_denom2 <= y__h2490 ; - assign numer___1__h728 = rg_v1[31] ? x__h2767 : rg_v1 ; - assign rg_v1_MUL_rg_v2___d100 = rg_v1 * rg_v2 ; - assign rg_v1_ULT_intDiv_rg_denom2_4___d59 = rg_v1 < intDiv_rg_denom2 ; - assign rg_v1_ULT_rg_v2___d55 = rg_v1 < rg_v2 ; - assign v1__h3150 = { 32'd0, rg_v1 } ; - assign v__h3074 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b001) ? - SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105[63:32] : - v__h3132 ; - assign v__h3132 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b011) ? - _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110[63:32] : - v__h3183 ; - assign v__h3183 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b010) ? - SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113[63:32] : - 32'hFFFFFFFF ; - assign x__h2611 = rg_v1 - intDiv_rg_denom2 ; - assign x__h2697 = -intDiv_rg_quo ; - assign x__h2767 = -rg_v1 ; - assign x__h2782 = intDiv_rg_quo + intDiv_rg_n ; - assign y__h2490 = { 1'd0, rg_v1[31:1] } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (intDiv_rg_state$EN) - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY intDiv_rg_state$D_IN; - end - if (intDiv_rg_denom2$EN) - intDiv_rg_denom2 <= `BSV_ASSIGNMENT_DELAY intDiv_rg_denom2$D_IN; - if (intDiv_rg_denom_is_signed$EN) - intDiv_rg_denom_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_denom_is_signed$D_IN; - if (intDiv_rg_n$EN) intDiv_rg_n <= `BSV_ASSIGNMENT_DELAY intDiv_rg_n$D_IN; - if (intDiv_rg_numer_is_signed$EN) - intDiv_rg_numer_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_numer_is_signed$D_IN; - if (intDiv_rg_quo$EN) - intDiv_rg_quo <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quo$D_IN; - if (intDiv_rg_quoIsNeg$EN) - intDiv_rg_quoIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quoIsNeg$D_IN; - if (intDiv_rg_remIsNeg$EN) - intDiv_rg_remIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_remIsNeg$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_is_OP_not_OP_32$EN) - rg_is_OP_not_OP_32 <= `BSV_ASSIGNMENT_DELAY rg_is_OP_not_OP_32$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_v1$EN) rg_v1 <= `BSV_ASSIGNMENT_DELAY rg_v1$D_IN; - if (rg_v2$EN) rg_v2 <= `BSV_ASSIGNMENT_DELAY rg_v2$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - intDiv_rg_denom2 = 32'hAAAAAAAA; - intDiv_rg_denom_is_signed = 1'h0; - intDiv_rg_n = 32'hAAAAAAAA; - intDiv_rg_numer_is_signed = 1'h0; - intDiv_rg_quo = 32'hAAAAAAAA; - intDiv_rg_quoIsNeg = 1'h0; - intDiv_rg_remIsNeg = 1'h0; - intDiv_rg_state = 3'h2; - rg_f3 = 3'h2; - rg_is_OP_not_OP_32 = 1'h0; - rg_state = 2'h2; - rg_v1 = 32'hAAAAAAAA; - rg_v2 = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && cfg_verbosity > 4'd1) - $display(" RISCV_MBox.rl_mul"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - begin - v__h3263 = $stime; - #0; - end - v__h3257 = v__h3263 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $display("%0d: ERROR: RISCV_MBox.rl_mul: illegal f3.", v__h3257); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $display(" f3 0x%0h v1 0x%0h v2 0x%0h", rg_f3, rg_v1, rg_v2); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkRISCV_MBox - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v deleted file mode 100644 index c88e21cd..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v +++ /dev/null @@ -1,298 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// m_near_mem_io_addr_base O 64 const -// m_near_mem_io_addr_size O 64 const -// m_near_mem_io_addr_lim O 64 const -// m_plic_addr_base O 64 const -// m_plic_addr_size O 64 const -// m_plic_addr_lim O 64 const -// m_uart0_addr_base O 64 const -// m_uart0_addr_size O 64 const -// m_uart0_addr_lim O 64 const -// m_boot_rom_addr_base O 64 const -// m_boot_rom_addr_size O 64 const -// m_boot_rom_addr_lim O 64 const -// m_mem0_controller_addr_base O 64 const -// m_mem0_controller_addr_size O 64 const -// m_mem0_controller_addr_lim O 64 const -// m_tcm_addr_base O 64 const -// m_tcm_addr_size O 64 const -// m_tcm_addr_lim O 64 const -// m_is_mem_addr O 1 -// m_is_IO_addr O 1 -// m_is_near_mem_IO_addr O 1 -// m_pc_reset_value O 64 const -// m_mtvec_reset_value O 64 const -// m_nmivec_reset_value O 64 const -// CLK I 1 unused -// RST_N I 1 unused -// m_is_mem_addr_addr I 64 -// m_is_IO_addr_addr I 64 -// m_is_near_mem_IO_addr_addr I 64 -// -// Combinational paths from inputs to outputs: -// m_is_mem_addr_addr -> m_is_mem_addr -// m_is_IO_addr_addr -> m_is_IO_addr -// m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Map(CLK, - RST_N, - - m_near_mem_io_addr_base, - - m_near_mem_io_addr_size, - - m_near_mem_io_addr_lim, - - m_plic_addr_base, - - m_plic_addr_size, - - m_plic_addr_lim, - - m_uart0_addr_base, - - m_uart0_addr_size, - - m_uart0_addr_lim, - - m_boot_rom_addr_base, - - m_boot_rom_addr_size, - - m_boot_rom_addr_lim, - - m_mem0_controller_addr_base, - - m_mem0_controller_addr_size, - - m_mem0_controller_addr_lim, - - m_tcm_addr_base, - - m_tcm_addr_size, - - m_tcm_addr_lim, - - m_is_mem_addr_addr, - m_is_mem_addr, - - m_is_IO_addr_addr, - m_is_IO_addr, - - m_is_near_mem_IO_addr_addr, - m_is_near_mem_IO_addr, - - m_pc_reset_value, - - m_mtvec_reset_value, - - m_nmivec_reset_value); - input CLK; - input RST_N; - - // value method m_near_mem_io_addr_base - output [63 : 0] m_near_mem_io_addr_base; - - // value method m_near_mem_io_addr_size - output [63 : 0] m_near_mem_io_addr_size; - - // value method m_near_mem_io_addr_lim - output [63 : 0] m_near_mem_io_addr_lim; - - // value method m_plic_addr_base - output [63 : 0] m_plic_addr_base; - - // value method m_plic_addr_size - output [63 : 0] m_plic_addr_size; - - // value method m_plic_addr_lim - output [63 : 0] m_plic_addr_lim; - - // value method m_uart0_addr_base - output [63 : 0] m_uart0_addr_base; - - // value method m_uart0_addr_size - output [63 : 0] m_uart0_addr_size; - - // value method m_uart0_addr_lim - output [63 : 0] m_uart0_addr_lim; - - // value method m_boot_rom_addr_base - output [63 : 0] m_boot_rom_addr_base; - - // value method m_boot_rom_addr_size - output [63 : 0] m_boot_rom_addr_size; - - // value method m_boot_rom_addr_lim - output [63 : 0] m_boot_rom_addr_lim; - - // value method m_mem0_controller_addr_base - output [63 : 0] m_mem0_controller_addr_base; - - // value method m_mem0_controller_addr_size - output [63 : 0] m_mem0_controller_addr_size; - - // value method m_mem0_controller_addr_lim - output [63 : 0] m_mem0_controller_addr_lim; - - // value method m_tcm_addr_base - output [63 : 0] m_tcm_addr_base; - - // value method m_tcm_addr_size - output [63 : 0] m_tcm_addr_size; - - // value method m_tcm_addr_lim - output [63 : 0] m_tcm_addr_lim; - - // value method m_is_mem_addr - input [63 : 0] m_is_mem_addr_addr; - output m_is_mem_addr; - - // value method m_is_IO_addr - input [63 : 0] m_is_IO_addr_addr; - output m_is_IO_addr; - - // value method m_is_near_mem_IO_addr - input [63 : 0] m_is_near_mem_IO_addr_addr; - output m_is_near_mem_IO_addr; - - // value method m_pc_reset_value - output [63 : 0] m_pc_reset_value; - - // value method m_mtvec_reset_value - output [63 : 0] m_mtvec_reset_value; - - // value method m_nmivec_reset_value - output [63 : 0] m_nmivec_reset_value; - - // signals for module outputs - wire [63 : 0] m_boot_rom_addr_base, - m_boot_rom_addr_lim, - m_boot_rom_addr_size, - m_mem0_controller_addr_base, - m_mem0_controller_addr_lim, - m_mem0_controller_addr_size, - m_mtvec_reset_value, - m_near_mem_io_addr_base, - m_near_mem_io_addr_lim, - m_near_mem_io_addr_size, - m_nmivec_reset_value, - m_pc_reset_value, - m_plic_addr_base, - m_plic_addr_lim, - m_plic_addr_size, - m_tcm_addr_base, - m_tcm_addr_lim, - m_tcm_addr_size, - m_uart0_addr_base, - m_uart0_addr_lim, - m_uart0_addr_size; - wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; - - // value method m_near_mem_io_addr_base - assign m_near_mem_io_addr_base = 64'h0000000002000000 ; - - // value method m_near_mem_io_addr_size - assign m_near_mem_io_addr_size = 64'h000000000000C000 ; - - // value method m_near_mem_io_addr_lim - assign m_near_mem_io_addr_lim = 64'd33603584 ; - - // value method m_plic_addr_base - assign m_plic_addr_base = 64'h000000000C000000 ; - - // value method m_plic_addr_size - assign m_plic_addr_size = 64'h0000000000400000 ; - - // value method m_plic_addr_lim - assign m_plic_addr_lim = 64'd205520896 ; - - // value method m_uart0_addr_base - assign m_uart0_addr_base = 64'h00000000C0000000 ; - - // value method m_uart0_addr_size - assign m_uart0_addr_size = 64'h0000000000000080 ; - - // value method m_uart0_addr_lim - assign m_uart0_addr_lim = 64'h00000000C0000080 ; - - // value method m_boot_rom_addr_base - assign m_boot_rom_addr_base = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_size - assign m_boot_rom_addr_size = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_lim - assign m_boot_rom_addr_lim = 64'd8192 ; - - // value method m_mem0_controller_addr_base - assign m_mem0_controller_addr_base = 64'h0000000080000000 ; - - // value method m_mem0_controller_addr_size - assign m_mem0_controller_addr_size = 64'h0000000010000000 ; - - // value method m_mem0_controller_addr_lim - assign m_mem0_controller_addr_lim = 64'h0000000090000000 ; - - // value method m_tcm_addr_base - assign m_tcm_addr_base = 64'h0 ; - - // value method m_tcm_addr_size - assign m_tcm_addr_size = 64'd0 ; - - // value method m_tcm_addr_lim - assign m_tcm_addr_lim = 64'd0 ; - - // value method m_is_mem_addr - assign m_is_mem_addr = - m_is_mem_addr_addr >= 64'h0000000000001000 && - m_is_mem_addr_addr < 64'd8192 || - m_is_mem_addr_addr >= 64'h0000000080000000 && - m_is_mem_addr_addr < 64'h0000000090000000 ; - - // value method m_is_IO_addr - assign m_is_IO_addr = - m_is_IO_addr_addr >= 64'h0000000002000000 && - m_is_IO_addr_addr < 64'd33603584 || - m_is_IO_addr_addr >= 64'h000000000C000000 && - m_is_IO_addr_addr < 64'd205520896 || - m_is_IO_addr_addr >= 64'h00000000C0000000 && - m_is_IO_addr_addr < 64'h00000000C0000080 ; - - // value method m_is_near_mem_IO_addr - assign m_is_near_mem_IO_addr = - m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 && - m_is_near_mem_IO_addr_addr < 64'd33603584 ; - - // value method m_pc_reset_value - assign m_pc_reset_value = 64'h0000000000001000 ; - - // value method m_mtvec_reset_value - assign m_mtvec_reset_value = 64'h0000000000001000 ; - - // value method m_nmivec_reset_value - assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ; -endmodule // mkSoC_Map - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v deleted file mode 100644 index 42e03763..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v +++ /dev/null @@ -1,2333 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// to_raw_mem_response_put I 256 -// put_from_console_put I 8 reg -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_set_verbosity I 1 -// EN_to_raw_mem_response_put I 1 -// EN_put_from_console_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Top(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [7 : 0] get_to_console_get, status; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_set_verbosity, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule boot_rom - wire [63 : 0] boot_rom$set_addr_map_addr_base, - boot_rom$set_addr_map_addr_lim, - boot_rom$slave_araddr, - boot_rom$slave_awaddr, - boot_rom$slave_rdata, - boot_rom$slave_wdata; - wire [7 : 0] boot_rom$slave_arlen, - boot_rom$slave_awlen, - boot_rom$slave_wstrb; - wire [3 : 0] boot_rom$slave_arcache, - boot_rom$slave_arid, - boot_rom$slave_arqos, - boot_rom$slave_arregion, - boot_rom$slave_awcache, - boot_rom$slave_awid, - boot_rom$slave_awqos, - boot_rom$slave_awregion, - boot_rom$slave_bid, - boot_rom$slave_rid, - boot_rom$slave_wid; - wire [2 : 0] boot_rom$slave_arprot, - boot_rom$slave_arsize, - boot_rom$slave_awprot, - boot_rom$slave_awsize; - wire [1 : 0] boot_rom$slave_arburst, - boot_rom$slave_awburst, - boot_rom$slave_bresp, - boot_rom$slave_rresp; - wire boot_rom$EN_set_addr_map, - boot_rom$slave_arlock, - boot_rom$slave_arready, - boot_rom$slave_arvalid, - boot_rom$slave_awlock, - boot_rom$slave_awready, - boot_rom$slave_awvalid, - boot_rom$slave_bready, - boot_rom$slave_bvalid, - boot_rom$slave_rlast, - boot_rom$slave_rready, - boot_rom$slave_rvalid, - boot_rom$slave_wlast, - boot_rom$slave_wready, - boot_rom$slave_wvalid; - - // ports of submodule boot_rom_axi4_deburster - wire [63 : 0] boot_rom_axi4_deburster$from_master_araddr, - boot_rom_axi4_deburster$from_master_awaddr, - boot_rom_axi4_deburster$from_master_rdata, - boot_rom_axi4_deburster$from_master_wdata, - boot_rom_axi4_deburster$to_slave_araddr, - boot_rom_axi4_deburster$to_slave_awaddr, - boot_rom_axi4_deburster$to_slave_rdata, - boot_rom_axi4_deburster$to_slave_wdata; - wire [7 : 0] boot_rom_axi4_deburster$from_master_arlen, - boot_rom_axi4_deburster$from_master_awlen, - boot_rom_axi4_deburster$from_master_wstrb, - boot_rom_axi4_deburster$to_slave_arlen, - boot_rom_axi4_deburster$to_slave_awlen, - boot_rom_axi4_deburster$to_slave_wstrb; - wire [3 : 0] boot_rom_axi4_deburster$from_master_arcache, - boot_rom_axi4_deburster$from_master_arid, - boot_rom_axi4_deburster$from_master_arqos, - boot_rom_axi4_deburster$from_master_arregion, - boot_rom_axi4_deburster$from_master_awcache, - boot_rom_axi4_deburster$from_master_awid, - boot_rom_axi4_deburster$from_master_awqos, - boot_rom_axi4_deburster$from_master_awregion, - boot_rom_axi4_deburster$from_master_bid, - boot_rom_axi4_deburster$from_master_rid, - boot_rom_axi4_deburster$from_master_wid, - boot_rom_axi4_deburster$to_slave_arcache, - boot_rom_axi4_deburster$to_slave_arid, - boot_rom_axi4_deburster$to_slave_arqos, - boot_rom_axi4_deburster$to_slave_arregion, - boot_rom_axi4_deburster$to_slave_awcache, - boot_rom_axi4_deburster$to_slave_awid, - boot_rom_axi4_deburster$to_slave_awqos, - boot_rom_axi4_deburster$to_slave_awregion, - boot_rom_axi4_deburster$to_slave_bid, - boot_rom_axi4_deburster$to_slave_rid, - boot_rom_axi4_deburster$to_slave_wid; - wire [2 : 0] boot_rom_axi4_deburster$from_master_arprot, - boot_rom_axi4_deburster$from_master_arsize, - boot_rom_axi4_deburster$from_master_awprot, - boot_rom_axi4_deburster$from_master_awsize, - boot_rom_axi4_deburster$to_slave_arprot, - boot_rom_axi4_deburster$to_slave_arsize, - boot_rom_axi4_deburster$to_slave_awprot, - boot_rom_axi4_deburster$to_slave_awsize; - wire [1 : 0] boot_rom_axi4_deburster$from_master_arburst, - boot_rom_axi4_deburster$from_master_awburst, - boot_rom_axi4_deburster$from_master_bresp, - boot_rom_axi4_deburster$from_master_rresp, - boot_rom_axi4_deburster$to_slave_arburst, - boot_rom_axi4_deburster$to_slave_awburst, - boot_rom_axi4_deburster$to_slave_bresp, - boot_rom_axi4_deburster$to_slave_rresp; - wire boot_rom_axi4_deburster$EN_reset, - boot_rom_axi4_deburster$from_master_arlock, - boot_rom_axi4_deburster$from_master_arready, - boot_rom_axi4_deburster$from_master_arvalid, - boot_rom_axi4_deburster$from_master_awlock, - boot_rom_axi4_deburster$from_master_awready, - boot_rom_axi4_deburster$from_master_awvalid, - boot_rom_axi4_deburster$from_master_bready, - boot_rom_axi4_deburster$from_master_bvalid, - boot_rom_axi4_deburster$from_master_rlast, - boot_rom_axi4_deburster$from_master_rready, - boot_rom_axi4_deburster$from_master_rvalid, - boot_rom_axi4_deburster$from_master_wlast, - boot_rom_axi4_deburster$from_master_wready, - boot_rom_axi4_deburster$from_master_wvalid, - boot_rom_axi4_deburster$to_slave_arlock, - boot_rom_axi4_deburster$to_slave_arready, - boot_rom_axi4_deburster$to_slave_arvalid, - boot_rom_axi4_deburster$to_slave_awlock, - boot_rom_axi4_deburster$to_slave_awready, - boot_rom_axi4_deburster$to_slave_awvalid, - boot_rom_axi4_deburster$to_slave_bready, - boot_rom_axi4_deburster$to_slave_bvalid, - boot_rom_axi4_deburster$to_slave_rlast, - boot_rom_axi4_deburster$to_slave_rready, - boot_rom_axi4_deburster$to_slave_rvalid, - boot_rom_axi4_deburster$to_slave_wlast, - boot_rom_axi4_deburster$to_slave_wready, - boot_rom_axi4_deburster$to_slave_wvalid; - - // ports of submodule core - wire [63 : 0] core$cpu_dmem_master_araddr, - core$cpu_dmem_master_awaddr, - core$cpu_dmem_master_rdata, - core$cpu_dmem_master_wdata, - core$cpu_imem_master_araddr, - core$cpu_imem_master_awaddr, - core$cpu_imem_master_rdata, - core$cpu_imem_master_wdata, - core$set_verbosity_logdelay; - wire [7 : 0] core$cpu_dmem_master_arlen, - core$cpu_dmem_master_awlen, - core$cpu_dmem_master_wstrb, - core$cpu_imem_master_arlen, - core$cpu_imem_master_awlen, - core$cpu_imem_master_wstrb; - wire [3 : 0] core$cpu_dmem_master_arcache, - core$cpu_dmem_master_arid, - core$cpu_dmem_master_arqos, - core$cpu_dmem_master_arregion, - core$cpu_dmem_master_awcache, - core$cpu_dmem_master_awid, - core$cpu_dmem_master_awqos, - core$cpu_dmem_master_awregion, - core$cpu_dmem_master_bid, - core$cpu_dmem_master_rid, - core$cpu_dmem_master_wid, - core$cpu_imem_master_arcache, - core$cpu_imem_master_arid, - core$cpu_imem_master_arqos, - core$cpu_imem_master_arregion, - core$cpu_imem_master_awcache, - core$cpu_imem_master_awid, - core$cpu_imem_master_awqos, - core$cpu_imem_master_awregion, - core$cpu_imem_master_bid, - core$cpu_imem_master_rid, - core$cpu_imem_master_wid, - core$set_verbosity_verbosity; - wire [2 : 0] core$cpu_dmem_master_arprot, - core$cpu_dmem_master_arsize, - core$cpu_dmem_master_awprot, - core$cpu_dmem_master_awsize, - core$cpu_imem_master_arprot, - core$cpu_imem_master_arsize, - core$cpu_imem_master_awprot, - core$cpu_imem_master_awsize; - wire [1 : 0] core$cpu_dmem_master_arburst, - core$cpu_dmem_master_awburst, - core$cpu_dmem_master_bresp, - core$cpu_dmem_master_rresp, - core$cpu_imem_master_arburst, - core$cpu_imem_master_awburst, - core$cpu_imem_master_bresp, - core$cpu_imem_master_rresp; - wire core$EN_cpu_reset_server_request_put, - core$EN_cpu_reset_server_response_get, - core$EN_set_verbosity, - core$RDY_cpu_reset_server_request_put, - core$RDY_cpu_reset_server_response_get, - core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - core$cpu_dmem_master_arlock, - core$cpu_dmem_master_arready, - core$cpu_dmem_master_arvalid, - core$cpu_dmem_master_awlock, - core$cpu_dmem_master_awready, - core$cpu_dmem_master_awvalid, - core$cpu_dmem_master_bready, - core$cpu_dmem_master_bvalid, - core$cpu_dmem_master_rlast, - core$cpu_dmem_master_rready, - core$cpu_dmem_master_rvalid, - core$cpu_dmem_master_wlast, - core$cpu_dmem_master_wready, - core$cpu_dmem_master_wvalid, - core$cpu_imem_master_arlock, - core$cpu_imem_master_arready, - core$cpu_imem_master_arvalid, - core$cpu_imem_master_awlock, - core$cpu_imem_master_awready, - core$cpu_imem_master_awvalid, - core$cpu_imem_master_bready, - core$cpu_imem_master_bvalid, - core$cpu_imem_master_rlast, - core$cpu_imem_master_rready, - core$cpu_imem_master_rvalid, - core$cpu_imem_master_wlast, - core$cpu_imem_master_wready, - core$cpu_imem_master_wvalid, - core$cpu_reset_server_request_put, - core$nmi_req_set_not_clear; - - // ports of submodule fabric - wire [63 : 0] fabric$v_from_masters_0_araddr, - fabric$v_from_masters_0_awaddr, - fabric$v_from_masters_0_rdata, - fabric$v_from_masters_0_wdata, - fabric$v_from_masters_1_araddr, - fabric$v_from_masters_1_awaddr, - fabric$v_from_masters_1_rdata, - fabric$v_from_masters_1_wdata, - fabric$v_to_slaves_0_araddr, - fabric$v_to_slaves_0_awaddr, - fabric$v_to_slaves_0_rdata, - fabric$v_to_slaves_0_wdata, - fabric$v_to_slaves_1_araddr, - fabric$v_to_slaves_1_awaddr, - fabric$v_to_slaves_1_rdata, - fabric$v_to_slaves_1_wdata, - fabric$v_to_slaves_2_araddr, - fabric$v_to_slaves_2_awaddr, - fabric$v_to_slaves_2_rdata, - fabric$v_to_slaves_2_wdata; - wire [7 : 0] fabric$v_from_masters_0_arlen, - fabric$v_from_masters_0_awlen, - fabric$v_from_masters_0_wstrb, - fabric$v_from_masters_1_arlen, - fabric$v_from_masters_1_awlen, - fabric$v_from_masters_1_wstrb, - fabric$v_to_slaves_0_arlen, - fabric$v_to_slaves_0_awlen, - fabric$v_to_slaves_0_wstrb, - fabric$v_to_slaves_1_arlen, - fabric$v_to_slaves_1_awlen, - fabric$v_to_slaves_1_wstrb, - fabric$v_to_slaves_2_arlen, - fabric$v_to_slaves_2_awlen, - fabric$v_to_slaves_2_wstrb; - wire [3 : 0] fabric$set_verbosity_verbosity, - fabric$v_from_masters_0_arcache, - fabric$v_from_masters_0_arid, - fabric$v_from_masters_0_arqos, - fabric$v_from_masters_0_arregion, - fabric$v_from_masters_0_awcache, - fabric$v_from_masters_0_awid, - fabric$v_from_masters_0_awqos, - fabric$v_from_masters_0_awregion, - fabric$v_from_masters_0_bid, - fabric$v_from_masters_0_rid, - fabric$v_from_masters_0_wid, - fabric$v_from_masters_1_arcache, - fabric$v_from_masters_1_arid, - fabric$v_from_masters_1_arqos, - fabric$v_from_masters_1_arregion, - fabric$v_from_masters_1_awcache, - fabric$v_from_masters_1_awid, - fabric$v_from_masters_1_awqos, - fabric$v_from_masters_1_awregion, - fabric$v_from_masters_1_bid, - fabric$v_from_masters_1_rid, - fabric$v_from_masters_1_wid, - fabric$v_to_slaves_0_arcache, - fabric$v_to_slaves_0_arid, - fabric$v_to_slaves_0_arqos, - fabric$v_to_slaves_0_arregion, - fabric$v_to_slaves_0_awcache, - fabric$v_to_slaves_0_awid, - fabric$v_to_slaves_0_awqos, - fabric$v_to_slaves_0_awregion, - fabric$v_to_slaves_0_bid, - fabric$v_to_slaves_0_rid, - fabric$v_to_slaves_0_wid, - fabric$v_to_slaves_1_arcache, - fabric$v_to_slaves_1_arid, - fabric$v_to_slaves_1_arqos, - fabric$v_to_slaves_1_arregion, - fabric$v_to_slaves_1_awcache, - fabric$v_to_slaves_1_awid, - fabric$v_to_slaves_1_awqos, - fabric$v_to_slaves_1_awregion, - fabric$v_to_slaves_1_bid, - fabric$v_to_slaves_1_rid, - fabric$v_to_slaves_1_wid, - fabric$v_to_slaves_2_arcache, - fabric$v_to_slaves_2_arid, - fabric$v_to_slaves_2_arqos, - fabric$v_to_slaves_2_arregion, - fabric$v_to_slaves_2_awcache, - fabric$v_to_slaves_2_awid, - fabric$v_to_slaves_2_awqos, - fabric$v_to_slaves_2_awregion, - fabric$v_to_slaves_2_bid, - fabric$v_to_slaves_2_rid, - fabric$v_to_slaves_2_wid; - wire [2 : 0] fabric$v_from_masters_0_arprot, - fabric$v_from_masters_0_arsize, - fabric$v_from_masters_0_awprot, - fabric$v_from_masters_0_awsize, - fabric$v_from_masters_1_arprot, - fabric$v_from_masters_1_arsize, - fabric$v_from_masters_1_awprot, - fabric$v_from_masters_1_awsize, - fabric$v_to_slaves_0_arprot, - fabric$v_to_slaves_0_arsize, - fabric$v_to_slaves_0_awprot, - fabric$v_to_slaves_0_awsize, - fabric$v_to_slaves_1_arprot, - fabric$v_to_slaves_1_arsize, - fabric$v_to_slaves_1_awprot, - fabric$v_to_slaves_1_awsize, - fabric$v_to_slaves_2_arprot, - fabric$v_to_slaves_2_arsize, - fabric$v_to_slaves_2_awprot, - fabric$v_to_slaves_2_awsize; - wire [1 : 0] fabric$v_from_masters_0_arburst, - fabric$v_from_masters_0_awburst, - fabric$v_from_masters_0_bresp, - fabric$v_from_masters_0_rresp, - fabric$v_from_masters_1_arburst, - fabric$v_from_masters_1_awburst, - fabric$v_from_masters_1_bresp, - fabric$v_from_masters_1_rresp, - fabric$v_to_slaves_0_arburst, - fabric$v_to_slaves_0_awburst, - fabric$v_to_slaves_0_bresp, - fabric$v_to_slaves_0_rresp, - fabric$v_to_slaves_1_arburst, - fabric$v_to_slaves_1_awburst, - fabric$v_to_slaves_1_bresp, - fabric$v_to_slaves_1_rresp, - fabric$v_to_slaves_2_arburst, - fabric$v_to_slaves_2_awburst, - fabric$v_to_slaves_2_bresp, - fabric$v_to_slaves_2_rresp; - wire fabric$EN_reset, - fabric$EN_set_verbosity, - fabric$RDY_reset, - fabric$v_from_masters_0_arlock, - fabric$v_from_masters_0_arready, - fabric$v_from_masters_0_arvalid, - fabric$v_from_masters_0_awlock, - fabric$v_from_masters_0_awready, - fabric$v_from_masters_0_awvalid, - fabric$v_from_masters_0_bready, - fabric$v_from_masters_0_bvalid, - fabric$v_from_masters_0_rlast, - fabric$v_from_masters_0_rready, - fabric$v_from_masters_0_rvalid, - fabric$v_from_masters_0_wlast, - fabric$v_from_masters_0_wready, - fabric$v_from_masters_0_wvalid, - fabric$v_from_masters_1_arlock, - fabric$v_from_masters_1_arready, - fabric$v_from_masters_1_arvalid, - fabric$v_from_masters_1_awlock, - fabric$v_from_masters_1_awready, - fabric$v_from_masters_1_awvalid, - fabric$v_from_masters_1_bready, - fabric$v_from_masters_1_bvalid, - fabric$v_from_masters_1_rlast, - fabric$v_from_masters_1_rready, - fabric$v_from_masters_1_rvalid, - fabric$v_from_masters_1_wlast, - fabric$v_from_masters_1_wready, - fabric$v_from_masters_1_wvalid, - fabric$v_to_slaves_0_arlock, - fabric$v_to_slaves_0_arready, - fabric$v_to_slaves_0_arvalid, - fabric$v_to_slaves_0_awlock, - fabric$v_to_slaves_0_awready, - fabric$v_to_slaves_0_awvalid, - fabric$v_to_slaves_0_bready, - fabric$v_to_slaves_0_bvalid, - fabric$v_to_slaves_0_rlast, - fabric$v_to_slaves_0_rready, - fabric$v_to_slaves_0_rvalid, - fabric$v_to_slaves_0_wlast, - fabric$v_to_slaves_0_wready, - fabric$v_to_slaves_0_wvalid, - fabric$v_to_slaves_1_arlock, - fabric$v_to_slaves_1_arready, - fabric$v_to_slaves_1_arvalid, - fabric$v_to_slaves_1_awlock, - fabric$v_to_slaves_1_awready, - fabric$v_to_slaves_1_awvalid, - fabric$v_to_slaves_1_bready, - fabric$v_to_slaves_1_bvalid, - fabric$v_to_slaves_1_rlast, - fabric$v_to_slaves_1_rready, - fabric$v_to_slaves_1_rvalid, - fabric$v_to_slaves_1_wlast, - fabric$v_to_slaves_1_wready, - fabric$v_to_slaves_1_wvalid, - fabric$v_to_slaves_2_arlock, - fabric$v_to_slaves_2_arready, - fabric$v_to_slaves_2_arvalid, - fabric$v_to_slaves_2_awlock, - fabric$v_to_slaves_2_awready, - fabric$v_to_slaves_2_awvalid, - fabric$v_to_slaves_2_bready, - fabric$v_to_slaves_2_bvalid, - fabric$v_to_slaves_2_rlast, - fabric$v_to_slaves_2_rready, - fabric$v_to_slaves_2_rvalid, - fabric$v_to_slaves_2_wlast, - fabric$v_to_slaves_2_wready, - fabric$v_to_slaves_2_wvalid; - - // ports of submodule mem0_controller - wire [352 : 0] mem0_controller$to_raw_mem_request_get; - wire [255 : 0] mem0_controller$to_raw_mem_response_put; - wire [63 : 0] mem0_controller$set_addr_map_addr_base, - mem0_controller$set_addr_map_addr_lim, - mem0_controller$set_watch_tohost_tohost_addr, - mem0_controller$slave_araddr, - mem0_controller$slave_awaddr, - mem0_controller$slave_rdata, - mem0_controller$slave_wdata; - wire [7 : 0] mem0_controller$slave_arlen, - mem0_controller$slave_awlen, - mem0_controller$slave_wstrb, - mem0_controller$status; - wire [3 : 0] mem0_controller$slave_arcache, - mem0_controller$slave_arid, - mem0_controller$slave_arqos, - mem0_controller$slave_arregion, - mem0_controller$slave_awcache, - mem0_controller$slave_awid, - mem0_controller$slave_awqos, - mem0_controller$slave_awregion, - mem0_controller$slave_bid, - mem0_controller$slave_rid, - mem0_controller$slave_wid; - wire [2 : 0] mem0_controller$slave_arprot, - mem0_controller$slave_arsize, - mem0_controller$slave_awprot, - mem0_controller$slave_awsize; - wire [1 : 0] mem0_controller$slave_arburst, - mem0_controller$slave_awburst, - mem0_controller$slave_bresp, - mem0_controller$slave_rresp; - wire mem0_controller$EN_server_reset_request_put, - mem0_controller$EN_server_reset_response_get, - mem0_controller$EN_set_addr_map, - mem0_controller$EN_set_watch_tohost, - mem0_controller$EN_to_raw_mem_request_get, - mem0_controller$EN_to_raw_mem_response_put, - mem0_controller$RDY_server_reset_request_put, - mem0_controller$RDY_server_reset_response_get, - mem0_controller$RDY_set_addr_map, - mem0_controller$RDY_to_raw_mem_request_get, - mem0_controller$RDY_to_raw_mem_response_put, - mem0_controller$set_watch_tohost_watch_tohost, - mem0_controller$slave_arlock, - mem0_controller$slave_arready, - mem0_controller$slave_arvalid, - mem0_controller$slave_awlock, - mem0_controller$slave_awready, - mem0_controller$slave_awvalid, - mem0_controller$slave_bready, - mem0_controller$slave_bvalid, - mem0_controller$slave_rlast, - mem0_controller$slave_rready, - mem0_controller$slave_rvalid, - mem0_controller$slave_wlast, - mem0_controller$slave_wready, - mem0_controller$slave_wvalid; - - // ports of submodule mem0_controller_axi4_deburster - wire [63 : 0] mem0_controller_axi4_deburster$from_master_araddr, - mem0_controller_axi4_deburster$from_master_awaddr, - mem0_controller_axi4_deburster$from_master_rdata, - mem0_controller_axi4_deburster$from_master_wdata, - mem0_controller_axi4_deburster$to_slave_araddr, - mem0_controller_axi4_deburster$to_slave_awaddr, - mem0_controller_axi4_deburster$to_slave_rdata, - mem0_controller_axi4_deburster$to_slave_wdata; - wire [7 : 0] mem0_controller_axi4_deburster$from_master_arlen, - mem0_controller_axi4_deburster$from_master_awlen, - mem0_controller_axi4_deburster$from_master_wstrb, - mem0_controller_axi4_deburster$to_slave_arlen, - mem0_controller_axi4_deburster$to_slave_awlen, - mem0_controller_axi4_deburster$to_slave_wstrb; - wire [3 : 0] mem0_controller_axi4_deburster$from_master_arcache, - mem0_controller_axi4_deburster$from_master_arid, - mem0_controller_axi4_deburster$from_master_arqos, - mem0_controller_axi4_deburster$from_master_arregion, - mem0_controller_axi4_deburster$from_master_awcache, - mem0_controller_axi4_deburster$from_master_awid, - mem0_controller_axi4_deburster$from_master_awqos, - mem0_controller_axi4_deburster$from_master_awregion, - mem0_controller_axi4_deburster$from_master_bid, - mem0_controller_axi4_deburster$from_master_rid, - mem0_controller_axi4_deburster$from_master_wid, - mem0_controller_axi4_deburster$to_slave_arcache, - mem0_controller_axi4_deburster$to_slave_arid, - mem0_controller_axi4_deburster$to_slave_arqos, - mem0_controller_axi4_deburster$to_slave_arregion, - mem0_controller_axi4_deburster$to_slave_awcache, - mem0_controller_axi4_deburster$to_slave_awid, - mem0_controller_axi4_deburster$to_slave_awqos, - mem0_controller_axi4_deburster$to_slave_awregion, - mem0_controller_axi4_deburster$to_slave_bid, - mem0_controller_axi4_deburster$to_slave_rid, - mem0_controller_axi4_deburster$to_slave_wid; - wire [2 : 0] mem0_controller_axi4_deburster$from_master_arprot, - mem0_controller_axi4_deburster$from_master_arsize, - mem0_controller_axi4_deburster$from_master_awprot, - mem0_controller_axi4_deburster$from_master_awsize, - mem0_controller_axi4_deburster$to_slave_arprot, - mem0_controller_axi4_deburster$to_slave_arsize, - mem0_controller_axi4_deburster$to_slave_awprot, - mem0_controller_axi4_deburster$to_slave_awsize; - wire [1 : 0] mem0_controller_axi4_deburster$from_master_arburst, - mem0_controller_axi4_deburster$from_master_awburst, - mem0_controller_axi4_deburster$from_master_bresp, - mem0_controller_axi4_deburster$from_master_rresp, - mem0_controller_axi4_deburster$to_slave_arburst, - mem0_controller_axi4_deburster$to_slave_awburst, - mem0_controller_axi4_deburster$to_slave_bresp, - mem0_controller_axi4_deburster$to_slave_rresp; - wire mem0_controller_axi4_deburster$EN_reset, - mem0_controller_axi4_deburster$from_master_arlock, - mem0_controller_axi4_deburster$from_master_arready, - mem0_controller_axi4_deburster$from_master_arvalid, - mem0_controller_axi4_deburster$from_master_awlock, - mem0_controller_axi4_deburster$from_master_awready, - mem0_controller_axi4_deburster$from_master_awvalid, - mem0_controller_axi4_deburster$from_master_bready, - mem0_controller_axi4_deburster$from_master_bvalid, - mem0_controller_axi4_deburster$from_master_rlast, - mem0_controller_axi4_deburster$from_master_rready, - mem0_controller_axi4_deburster$from_master_rvalid, - mem0_controller_axi4_deburster$from_master_wlast, - mem0_controller_axi4_deburster$from_master_wready, - mem0_controller_axi4_deburster$from_master_wvalid, - mem0_controller_axi4_deburster$to_slave_arlock, - mem0_controller_axi4_deburster$to_slave_arready, - mem0_controller_axi4_deburster$to_slave_arvalid, - mem0_controller_axi4_deburster$to_slave_awlock, - mem0_controller_axi4_deburster$to_slave_awready, - mem0_controller_axi4_deburster$to_slave_awvalid, - mem0_controller_axi4_deburster$to_slave_bready, - mem0_controller_axi4_deburster$to_slave_bvalid, - mem0_controller_axi4_deburster$to_slave_rlast, - mem0_controller_axi4_deburster$to_slave_rready, - mem0_controller_axi4_deburster$to_slave_rvalid, - mem0_controller_axi4_deburster$to_slave_wlast, - mem0_controller_axi4_deburster$to_slave_wready, - mem0_controller_axi4_deburster$to_slave_wvalid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // ports of submodule uart0 - wire [63 : 0] uart0$set_addr_map_addr_base, - uart0$set_addr_map_addr_lim, - uart0$slave_araddr, - uart0$slave_awaddr, - uart0$slave_rdata, - uart0$slave_wdata; - wire [7 : 0] uart0$get_to_console_get, - uart0$put_from_console_put, - uart0$slave_arlen, - uart0$slave_awlen, - uart0$slave_wstrb; - wire [3 : 0] uart0$slave_arcache, - uart0$slave_arid, - uart0$slave_arqos, - uart0$slave_arregion, - uart0$slave_awcache, - uart0$slave_awid, - uart0$slave_awqos, - uart0$slave_awregion, - uart0$slave_bid, - uart0$slave_rid, - uart0$slave_wid; - wire [2 : 0] uart0$slave_arprot, - uart0$slave_arsize, - uart0$slave_awprot, - uart0$slave_awsize; - wire [1 : 0] uart0$slave_arburst, - uart0$slave_awburst, - uart0$slave_bresp, - uart0$slave_rresp; - wire uart0$EN_get_to_console_get, - uart0$EN_put_from_console_put, - uart0$EN_server_reset_request_put, - uart0$EN_server_reset_response_get, - uart0$EN_set_addr_map, - uart0$RDY_get_to_console_get, - uart0$RDY_put_from_console_put, - uart0$RDY_server_reset_request_put, - uart0$RDY_server_reset_response_get, - uart0$intr, - uart0$slave_arlock, - uart0$slave_arready, - uart0$slave_arvalid, - uart0$slave_awlock, - uart0$slave_awready, - uart0$slave_awvalid, - uart0$slave_bready, - uart0$slave_bvalid, - uart0$slave_rlast, - uart0$slave_rready, - uart0$slave_rvalid, - uart0$slave_wlast, - uart0$slave_wready, - uart0$slave_wvalid; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_connect_external_interrupt_requests, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_addr_channel_5, - CAN_FIRE_RL_rl_rd_addr_channel_6, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, - CAN_FIRE_RL_rl_rd_data_channel_5, - CAN_FIRE_RL_rl_rd_data_channel_6, - CAN_FIRE_RL_rl_reset_complete_initial, - CAN_FIRE_RL_rl_reset_start_initial, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_addr_channel_5, - CAN_FIRE_RL_rl_wr_addr_channel_6, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_data_channel_5, - CAN_FIRE_RL_rl_wr_data_channel_6, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, - CAN_FIRE_RL_rl_wr_response_channel_5, - CAN_FIRE_RL_rl_wr_response_channel_6, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_set_verbosity, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_connect_external_interrupt_requests, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_addr_channel_5, - WILL_FIRE_RL_rl_rd_addr_channel_6, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, - WILL_FIRE_RL_rl_rd_data_channel_5, - WILL_FIRE_RL_rl_rd_data_channel_6, - WILL_FIRE_RL_rl_reset_complete_initial, - WILL_FIRE_RL_rl_reset_start_initial, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_addr_channel_5, - WILL_FIRE_RL_rl_wr_addr_channel_6, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_data_channel_5, - WILL_FIRE_RL_rl_wr_data_channel_6, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, - WILL_FIRE_RL_rl_wr_response_channel_5, - WILL_FIRE_RL_rl_wr_response_channel_6, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_set_verbosity, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h11286; - reg [31 : 0] v__h11556; - reg [31 : 0] v__h11280; - reg [31 : 0] v__h11550; - // synopsys translate_on - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = mem0_controller$to_raw_mem_request_get ; - assign RDY_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign CAN_FIRE_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign CAN_FIRE_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // actionvalue method get_to_console_get - assign get_to_console_get = uart0$get_to_console_get ; - assign RDY_get_to_console_get = uart0$RDY_get_to_console_get ; - assign CAN_FIRE_get_to_console_get = uart0$RDY_get_to_console_get ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = uart0$RDY_put_from_console_put ; - assign CAN_FIRE_put_from_console_put = uart0$RDY_put_from_console_put ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method status - assign status = mem0_controller$status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule boot_rom - mkBoot_ROM boot_rom(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(boot_rom$set_addr_map_addr_base), - .set_addr_map_addr_lim(boot_rom$set_addr_map_addr_lim), - .slave_araddr(boot_rom$slave_araddr), - .slave_arburst(boot_rom$slave_arburst), - .slave_arcache(boot_rom$slave_arcache), - .slave_arid(boot_rom$slave_arid), - .slave_arlen(boot_rom$slave_arlen), - .slave_arlock(boot_rom$slave_arlock), - .slave_arprot(boot_rom$slave_arprot), - .slave_arqos(boot_rom$slave_arqos), - .slave_arregion(boot_rom$slave_arregion), - .slave_arsize(boot_rom$slave_arsize), - .slave_arvalid(boot_rom$slave_arvalid), - .slave_awaddr(boot_rom$slave_awaddr), - .slave_awburst(boot_rom$slave_awburst), - .slave_awcache(boot_rom$slave_awcache), - .slave_awid(boot_rom$slave_awid), - .slave_awlen(boot_rom$slave_awlen), - .slave_awlock(boot_rom$slave_awlock), - .slave_awprot(boot_rom$slave_awprot), - .slave_awqos(boot_rom$slave_awqos), - .slave_awregion(boot_rom$slave_awregion), - .slave_awsize(boot_rom$slave_awsize), - .slave_awvalid(boot_rom$slave_awvalid), - .slave_bready(boot_rom$slave_bready), - .slave_rready(boot_rom$slave_rready), - .slave_wdata(boot_rom$slave_wdata), - .slave_wid(boot_rom$slave_wid), - .slave_wlast(boot_rom$slave_wlast), - .slave_wstrb(boot_rom$slave_wstrb), - .slave_wvalid(boot_rom$slave_wvalid), - .EN_set_addr_map(boot_rom$EN_set_addr_map), - .RDY_set_addr_map(), - .slave_awready(boot_rom$slave_awready), - .slave_wready(boot_rom$slave_wready), - .slave_bvalid(boot_rom$slave_bvalid), - .slave_bid(boot_rom$slave_bid), - .slave_bresp(boot_rom$slave_bresp), - .slave_arready(boot_rom$slave_arready), - .slave_rvalid(boot_rom$slave_rvalid), - .slave_rid(boot_rom$slave_rid), - .slave_rdata(boot_rom$slave_rdata), - .slave_rresp(boot_rom$slave_rresp), - .slave_rlast(boot_rom$slave_rlast)); - - // submodule boot_rom_axi4_deburster - mkAXI4_Deburster_A boot_rom_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(boot_rom_axi4_deburster$from_master_araddr), - .from_master_arburst(boot_rom_axi4_deburster$from_master_arburst), - .from_master_arcache(boot_rom_axi4_deburster$from_master_arcache), - .from_master_arid(boot_rom_axi4_deburster$from_master_arid), - .from_master_arlen(boot_rom_axi4_deburster$from_master_arlen), - .from_master_arlock(boot_rom_axi4_deburster$from_master_arlock), - .from_master_arprot(boot_rom_axi4_deburster$from_master_arprot), - .from_master_arqos(boot_rom_axi4_deburster$from_master_arqos), - .from_master_arregion(boot_rom_axi4_deburster$from_master_arregion), - .from_master_arsize(boot_rom_axi4_deburster$from_master_arsize), - .from_master_arvalid(boot_rom_axi4_deburster$from_master_arvalid), - .from_master_awaddr(boot_rom_axi4_deburster$from_master_awaddr), - .from_master_awburst(boot_rom_axi4_deburster$from_master_awburst), - .from_master_awcache(boot_rom_axi4_deburster$from_master_awcache), - .from_master_awid(boot_rom_axi4_deburster$from_master_awid), - .from_master_awlen(boot_rom_axi4_deburster$from_master_awlen), - .from_master_awlock(boot_rom_axi4_deburster$from_master_awlock), - .from_master_awprot(boot_rom_axi4_deburster$from_master_awprot), - .from_master_awqos(boot_rom_axi4_deburster$from_master_awqos), - .from_master_awregion(boot_rom_axi4_deburster$from_master_awregion), - .from_master_awsize(boot_rom_axi4_deburster$from_master_awsize), - .from_master_awvalid(boot_rom_axi4_deburster$from_master_awvalid), - .from_master_bready(boot_rom_axi4_deburster$from_master_bready), - .from_master_rready(boot_rom_axi4_deburster$from_master_rready), - .from_master_wdata(boot_rom_axi4_deburster$from_master_wdata), - .from_master_wid(boot_rom_axi4_deburster$from_master_wid), - .from_master_wlast(boot_rom_axi4_deburster$from_master_wlast), - .from_master_wstrb(boot_rom_axi4_deburster$from_master_wstrb), - .from_master_wvalid(boot_rom_axi4_deburster$from_master_wvalid), - .to_slave_arready(boot_rom_axi4_deburster$to_slave_arready), - .to_slave_awready(boot_rom_axi4_deburster$to_slave_awready), - .to_slave_bid(boot_rom_axi4_deburster$to_slave_bid), - .to_slave_bresp(boot_rom_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(boot_rom_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(boot_rom_axi4_deburster$to_slave_rdata), - .to_slave_rid(boot_rom_axi4_deburster$to_slave_rid), - .to_slave_rlast(boot_rom_axi4_deburster$to_slave_rlast), - .to_slave_rresp(boot_rom_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(boot_rom_axi4_deburster$to_slave_rvalid), - .to_slave_wready(boot_rom_axi4_deburster$to_slave_wready), - .EN_reset(boot_rom_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(boot_rom_axi4_deburster$from_master_awready), - .from_master_wready(boot_rom_axi4_deburster$from_master_wready), - .from_master_bvalid(boot_rom_axi4_deburster$from_master_bvalid), - .from_master_bid(boot_rom_axi4_deburster$from_master_bid), - .from_master_bresp(boot_rom_axi4_deburster$from_master_bresp), - .from_master_arready(boot_rom_axi4_deburster$from_master_arready), - .from_master_rvalid(boot_rom_axi4_deburster$from_master_rvalid), - .from_master_rid(boot_rom_axi4_deburster$from_master_rid), - .from_master_rdata(boot_rom_axi4_deburster$from_master_rdata), - .from_master_rresp(boot_rom_axi4_deburster$from_master_rresp), - .from_master_rlast(boot_rom_axi4_deburster$from_master_rlast), - .to_slave_awvalid(boot_rom_axi4_deburster$to_slave_awvalid), - .to_slave_awid(boot_rom_axi4_deburster$to_slave_awid), - .to_slave_awaddr(boot_rom_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(boot_rom_axi4_deburster$to_slave_awlen), - .to_slave_awsize(boot_rom_axi4_deburster$to_slave_awsize), - .to_slave_awburst(boot_rom_axi4_deburster$to_slave_awburst), - .to_slave_awlock(boot_rom_axi4_deburster$to_slave_awlock), - .to_slave_awcache(boot_rom_axi4_deburster$to_slave_awcache), - .to_slave_awprot(boot_rom_axi4_deburster$to_slave_awprot), - .to_slave_awqos(boot_rom_axi4_deburster$to_slave_awqos), - .to_slave_awregion(boot_rom_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(boot_rom_axi4_deburster$to_slave_wvalid), - .to_slave_wid(boot_rom_axi4_deburster$to_slave_wid), - .to_slave_wdata(boot_rom_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(boot_rom_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(boot_rom_axi4_deburster$to_slave_wlast), - .to_slave_bready(boot_rom_axi4_deburster$to_slave_bready), - .to_slave_arvalid(boot_rom_axi4_deburster$to_slave_arvalid), - .to_slave_arid(boot_rom_axi4_deburster$to_slave_arid), - .to_slave_araddr(boot_rom_axi4_deburster$to_slave_araddr), - .to_slave_arlen(boot_rom_axi4_deburster$to_slave_arlen), - .to_slave_arsize(boot_rom_axi4_deburster$to_slave_arsize), - .to_slave_arburst(boot_rom_axi4_deburster$to_slave_arburst), - .to_slave_arlock(boot_rom_axi4_deburster$to_slave_arlock), - .to_slave_arcache(boot_rom_axi4_deburster$to_slave_arcache), - .to_slave_arprot(boot_rom_axi4_deburster$to_slave_arprot), - .to_slave_arqos(boot_rom_axi4_deburster$to_slave_arqos), - .to_slave_arregion(boot_rom_axi4_deburster$to_slave_arregion), - .to_slave_rready(boot_rom_axi4_deburster$to_slave_rready)); - - // submodule core - mkCore core(.CLK(CLK), - .RST_N(RST_N), - .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_12_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_13_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_14_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_15_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_1_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_2_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_3_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_4_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_5_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_6_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_7_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_8_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_9_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear), - .cpu_dmem_master_arready(core$cpu_dmem_master_arready), - .cpu_dmem_master_awready(core$cpu_dmem_master_awready), - .cpu_dmem_master_bid(core$cpu_dmem_master_bid), - .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), - .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata), - .cpu_dmem_master_rid(core$cpu_dmem_master_rid), - .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast), - .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), - .cpu_dmem_master_wready(core$cpu_dmem_master_wready), - .cpu_imem_master_arready(core$cpu_imem_master_arready), - .cpu_imem_master_awready(core$cpu_imem_master_awready), - .cpu_imem_master_bid(core$cpu_imem_master_bid), - .cpu_imem_master_bresp(core$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), - .cpu_imem_master_rdata(core$cpu_imem_master_rdata), - .cpu_imem_master_rid(core$cpu_imem_master_rid), - .cpu_imem_master_rlast(core$cpu_imem_master_rlast), - .cpu_imem_master_rresp(core$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), - .cpu_imem_master_wready(core$cpu_imem_master_wready), - .cpu_reset_server_request_put(core$cpu_reset_server_request_put), - .nmi_req_set_not_clear(core$nmi_req_set_not_clear), - .set_verbosity_logdelay(core$set_verbosity_logdelay), - .set_verbosity_verbosity(core$set_verbosity_verbosity), - .EN_set_verbosity(core$EN_set_verbosity), - .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get), - .RDY_set_verbosity(), - .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put), - .cpu_reset_server_response_get(), - .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), - .cpu_imem_master_awid(core$cpu_imem_master_awid), - .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr), - .cpu_imem_master_awlen(core$cpu_imem_master_awlen), - .cpu_imem_master_awsize(core$cpu_imem_master_awsize), - .cpu_imem_master_awburst(core$cpu_imem_master_awburst), - .cpu_imem_master_awlock(core$cpu_imem_master_awlock), - .cpu_imem_master_awcache(core$cpu_imem_master_awcache), - .cpu_imem_master_awprot(core$cpu_imem_master_awprot), - .cpu_imem_master_awqos(core$cpu_imem_master_awqos), - .cpu_imem_master_awregion(core$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), - .cpu_imem_master_wid(core$cpu_imem_master_wid), - .cpu_imem_master_wdata(core$cpu_imem_master_wdata), - .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb), - .cpu_imem_master_wlast(core$cpu_imem_master_wlast), - .cpu_imem_master_bready(core$cpu_imem_master_bready), - .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), - .cpu_imem_master_arid(core$cpu_imem_master_arid), - .cpu_imem_master_araddr(core$cpu_imem_master_araddr), - .cpu_imem_master_arlen(core$cpu_imem_master_arlen), - .cpu_imem_master_arsize(core$cpu_imem_master_arsize), - .cpu_imem_master_arburst(core$cpu_imem_master_arburst), - .cpu_imem_master_arlock(core$cpu_imem_master_arlock), - .cpu_imem_master_arcache(core$cpu_imem_master_arcache), - .cpu_imem_master_arprot(core$cpu_imem_master_arprot), - .cpu_imem_master_arqos(core$cpu_imem_master_arqos), - .cpu_imem_master_arregion(core$cpu_imem_master_arregion), - .cpu_imem_master_rready(core$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), - .cpu_dmem_master_awid(core$cpu_dmem_master_awid), - .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr), - .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen), - .cpu_dmem_master_awsize(core$cpu_dmem_master_awsize), - .cpu_dmem_master_awburst(core$cpu_dmem_master_awburst), - .cpu_dmem_master_awlock(core$cpu_dmem_master_awlock), - .cpu_dmem_master_awcache(core$cpu_dmem_master_awcache), - .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot), - .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos), - .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(core$cpu_dmem_master_wid), - .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata), - .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb), - .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast), - .cpu_dmem_master_bready(core$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), - .cpu_dmem_master_arid(core$cpu_dmem_master_arid), - .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr), - .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen), - .cpu_dmem_master_arsize(core$cpu_dmem_master_arsize), - .cpu_dmem_master_arburst(core$cpu_dmem_master_arburst), - .cpu_dmem_master_arlock(core$cpu_dmem_master_arlock), - .cpu_dmem_master_arcache(core$cpu_dmem_master_arcache), - .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot), - .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos), - .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion), - .cpu_dmem_master_rready(core$cpu_dmem_master_rready)); - - // submodule fabric - mkFabric_AXI4 fabric(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric$v_to_slaves_2_wready), - .EN_reset(fabric$EN_reset), - .EN_set_verbosity(fabric$EN_set_verbosity), - .RDY_reset(fabric$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric$v_to_slaves_2_rready)); - - // submodule mem0_controller - mkMem_Controller mem0_controller(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(mem0_controller$set_addr_map_addr_base), - .set_addr_map_addr_lim(mem0_controller$set_addr_map_addr_lim), - .set_watch_tohost_tohost_addr(mem0_controller$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(mem0_controller$set_watch_tohost_watch_tohost), - .slave_araddr(mem0_controller$slave_araddr), - .slave_arburst(mem0_controller$slave_arburst), - .slave_arcache(mem0_controller$slave_arcache), - .slave_arid(mem0_controller$slave_arid), - .slave_arlen(mem0_controller$slave_arlen), - .slave_arlock(mem0_controller$slave_arlock), - .slave_arprot(mem0_controller$slave_arprot), - .slave_arqos(mem0_controller$slave_arqos), - .slave_arregion(mem0_controller$slave_arregion), - .slave_arsize(mem0_controller$slave_arsize), - .slave_arvalid(mem0_controller$slave_arvalid), - .slave_awaddr(mem0_controller$slave_awaddr), - .slave_awburst(mem0_controller$slave_awburst), - .slave_awcache(mem0_controller$slave_awcache), - .slave_awid(mem0_controller$slave_awid), - .slave_awlen(mem0_controller$slave_awlen), - .slave_awlock(mem0_controller$slave_awlock), - .slave_awprot(mem0_controller$slave_awprot), - .slave_awqos(mem0_controller$slave_awqos), - .slave_awregion(mem0_controller$slave_awregion), - .slave_awsize(mem0_controller$slave_awsize), - .slave_awvalid(mem0_controller$slave_awvalid), - .slave_bready(mem0_controller$slave_bready), - .slave_rready(mem0_controller$slave_rready), - .slave_wdata(mem0_controller$slave_wdata), - .slave_wid(mem0_controller$slave_wid), - .slave_wlast(mem0_controller$slave_wlast), - .slave_wstrb(mem0_controller$slave_wstrb), - .slave_wvalid(mem0_controller$slave_wvalid), - .to_raw_mem_response_put(mem0_controller$to_raw_mem_response_put), - .EN_server_reset_request_put(mem0_controller$EN_server_reset_request_put), - .EN_server_reset_response_get(mem0_controller$EN_server_reset_response_get), - .EN_set_addr_map(mem0_controller$EN_set_addr_map), - .EN_to_raw_mem_request_get(mem0_controller$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(mem0_controller$EN_to_raw_mem_response_put), - .EN_set_watch_tohost(mem0_controller$EN_set_watch_tohost), - .RDY_server_reset_request_put(mem0_controller$RDY_server_reset_request_put), - .RDY_server_reset_response_get(mem0_controller$RDY_server_reset_response_get), - .RDY_set_addr_map(mem0_controller$RDY_set_addr_map), - .slave_awready(mem0_controller$slave_awready), - .slave_wready(mem0_controller$slave_wready), - .slave_bvalid(mem0_controller$slave_bvalid), - .slave_bid(mem0_controller$slave_bid), - .slave_bresp(mem0_controller$slave_bresp), - .slave_arready(mem0_controller$slave_arready), - .slave_rvalid(mem0_controller$slave_rvalid), - .slave_rid(mem0_controller$slave_rid), - .slave_rdata(mem0_controller$slave_rdata), - .slave_rresp(mem0_controller$slave_rresp), - .slave_rlast(mem0_controller$slave_rlast), - .to_raw_mem_request_get(mem0_controller$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(mem0_controller$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(mem0_controller$RDY_to_raw_mem_response_put), - .status(mem0_controller$status), - .RDY_set_watch_tohost()); - - // submodule mem0_controller_axi4_deburster - mkAXI4_Deburster_A mem0_controller_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(mem0_controller_axi4_deburster$from_master_araddr), - .from_master_arburst(mem0_controller_axi4_deburster$from_master_arburst), - .from_master_arcache(mem0_controller_axi4_deburster$from_master_arcache), - .from_master_arid(mem0_controller_axi4_deburster$from_master_arid), - .from_master_arlen(mem0_controller_axi4_deburster$from_master_arlen), - .from_master_arlock(mem0_controller_axi4_deburster$from_master_arlock), - .from_master_arprot(mem0_controller_axi4_deburster$from_master_arprot), - .from_master_arqos(mem0_controller_axi4_deburster$from_master_arqos), - .from_master_arregion(mem0_controller_axi4_deburster$from_master_arregion), - .from_master_arsize(mem0_controller_axi4_deburster$from_master_arsize), - .from_master_arvalid(mem0_controller_axi4_deburster$from_master_arvalid), - .from_master_awaddr(mem0_controller_axi4_deburster$from_master_awaddr), - .from_master_awburst(mem0_controller_axi4_deburster$from_master_awburst), - .from_master_awcache(mem0_controller_axi4_deburster$from_master_awcache), - .from_master_awid(mem0_controller_axi4_deburster$from_master_awid), - .from_master_awlen(mem0_controller_axi4_deburster$from_master_awlen), - .from_master_awlock(mem0_controller_axi4_deburster$from_master_awlock), - .from_master_awprot(mem0_controller_axi4_deburster$from_master_awprot), - .from_master_awqos(mem0_controller_axi4_deburster$from_master_awqos), - .from_master_awregion(mem0_controller_axi4_deburster$from_master_awregion), - .from_master_awsize(mem0_controller_axi4_deburster$from_master_awsize), - .from_master_awvalid(mem0_controller_axi4_deburster$from_master_awvalid), - .from_master_bready(mem0_controller_axi4_deburster$from_master_bready), - .from_master_rready(mem0_controller_axi4_deburster$from_master_rready), - .from_master_wdata(mem0_controller_axi4_deburster$from_master_wdata), - .from_master_wid(mem0_controller_axi4_deburster$from_master_wid), - .from_master_wlast(mem0_controller_axi4_deburster$from_master_wlast), - .from_master_wstrb(mem0_controller_axi4_deburster$from_master_wstrb), - .from_master_wvalid(mem0_controller_axi4_deburster$from_master_wvalid), - .to_slave_arready(mem0_controller_axi4_deburster$to_slave_arready), - .to_slave_awready(mem0_controller_axi4_deburster$to_slave_awready), - .to_slave_bid(mem0_controller_axi4_deburster$to_slave_bid), - .to_slave_bresp(mem0_controller_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(mem0_controller_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(mem0_controller_axi4_deburster$to_slave_rdata), - .to_slave_rid(mem0_controller_axi4_deburster$to_slave_rid), - .to_slave_rlast(mem0_controller_axi4_deburster$to_slave_rlast), - .to_slave_rresp(mem0_controller_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(mem0_controller_axi4_deburster$to_slave_rvalid), - .to_slave_wready(mem0_controller_axi4_deburster$to_slave_wready), - .EN_reset(mem0_controller_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(mem0_controller_axi4_deburster$from_master_awready), - .from_master_wready(mem0_controller_axi4_deburster$from_master_wready), - .from_master_bvalid(mem0_controller_axi4_deburster$from_master_bvalid), - .from_master_bid(mem0_controller_axi4_deburster$from_master_bid), - .from_master_bresp(mem0_controller_axi4_deburster$from_master_bresp), - .from_master_arready(mem0_controller_axi4_deburster$from_master_arready), - .from_master_rvalid(mem0_controller_axi4_deburster$from_master_rvalid), - .from_master_rid(mem0_controller_axi4_deburster$from_master_rid), - .from_master_rdata(mem0_controller_axi4_deburster$from_master_rdata), - .from_master_rresp(mem0_controller_axi4_deburster$from_master_rresp), - .from_master_rlast(mem0_controller_axi4_deburster$from_master_rlast), - .to_slave_awvalid(mem0_controller_axi4_deburster$to_slave_awvalid), - .to_slave_awid(mem0_controller_axi4_deburster$to_slave_awid), - .to_slave_awaddr(mem0_controller_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(mem0_controller_axi4_deburster$to_slave_awlen), - .to_slave_awsize(mem0_controller_axi4_deburster$to_slave_awsize), - .to_slave_awburst(mem0_controller_axi4_deburster$to_slave_awburst), - .to_slave_awlock(mem0_controller_axi4_deburster$to_slave_awlock), - .to_slave_awcache(mem0_controller_axi4_deburster$to_slave_awcache), - .to_slave_awprot(mem0_controller_axi4_deburster$to_slave_awprot), - .to_slave_awqos(mem0_controller_axi4_deburster$to_slave_awqos), - .to_slave_awregion(mem0_controller_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(mem0_controller_axi4_deburster$to_slave_wvalid), - .to_slave_wid(mem0_controller_axi4_deburster$to_slave_wid), - .to_slave_wdata(mem0_controller_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(mem0_controller_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(mem0_controller_axi4_deburster$to_slave_wlast), - .to_slave_bready(mem0_controller_axi4_deburster$to_slave_bready), - .to_slave_arvalid(mem0_controller_axi4_deburster$to_slave_arvalid), - .to_slave_arid(mem0_controller_axi4_deburster$to_slave_arid), - .to_slave_araddr(mem0_controller_axi4_deburster$to_slave_araddr), - .to_slave_arlen(mem0_controller_axi4_deburster$to_slave_arlen), - .to_slave_arsize(mem0_controller_axi4_deburster$to_slave_arsize), - .to_slave_arburst(mem0_controller_axi4_deburster$to_slave_arburst), - .to_slave_arlock(mem0_controller_axi4_deburster$to_slave_arlock), - .to_slave_arcache(mem0_controller_axi4_deburster$to_slave_arcache), - .to_slave_arprot(mem0_controller_axi4_deburster$to_slave_arprot), - .to_slave_arqos(mem0_controller_axi4_deburster$to_slave_arqos), - .to_slave_arregion(mem0_controller_axi4_deburster$to_slave_arregion), - .to_slave_rready(mem0_controller_axi4_deburster$to_slave_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule uart0 - mkUART uart0(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(uart0$put_from_console_put), - .set_addr_map_addr_base(uart0$set_addr_map_addr_base), - .set_addr_map_addr_lim(uart0$set_addr_map_addr_lim), - .slave_araddr(uart0$slave_araddr), - .slave_arburst(uart0$slave_arburst), - .slave_arcache(uart0$slave_arcache), - .slave_arid(uart0$slave_arid), - .slave_arlen(uart0$slave_arlen), - .slave_arlock(uart0$slave_arlock), - .slave_arprot(uart0$slave_arprot), - .slave_arqos(uart0$slave_arqos), - .slave_arregion(uart0$slave_arregion), - .slave_arsize(uart0$slave_arsize), - .slave_arvalid(uart0$slave_arvalid), - .slave_awaddr(uart0$slave_awaddr), - .slave_awburst(uart0$slave_awburst), - .slave_awcache(uart0$slave_awcache), - .slave_awid(uart0$slave_awid), - .slave_awlen(uart0$slave_awlen), - .slave_awlock(uart0$slave_awlock), - .slave_awprot(uart0$slave_awprot), - .slave_awqos(uart0$slave_awqos), - .slave_awregion(uart0$slave_awregion), - .slave_awsize(uart0$slave_awsize), - .slave_awvalid(uart0$slave_awvalid), - .slave_bready(uart0$slave_bready), - .slave_rready(uart0$slave_rready), - .slave_wdata(uart0$slave_wdata), - .slave_wid(uart0$slave_wid), - .slave_wlast(uart0$slave_wlast), - .slave_wstrb(uart0$slave_wstrb), - .slave_wvalid(uart0$slave_wvalid), - .EN_server_reset_request_put(uart0$EN_server_reset_request_put), - .EN_server_reset_response_get(uart0$EN_server_reset_response_get), - .EN_set_addr_map(uart0$EN_set_addr_map), - .EN_get_to_console_get(uart0$EN_get_to_console_get), - .EN_put_from_console_put(uart0$EN_put_from_console_put), - .RDY_server_reset_request_put(uart0$RDY_server_reset_request_put), - .RDY_server_reset_response_get(uart0$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .slave_awready(uart0$slave_awready), - .slave_wready(uart0$slave_wready), - .slave_bvalid(uart0$slave_bvalid), - .slave_bid(uart0$slave_bid), - .slave_bresp(uart0$slave_bresp), - .slave_arready(uart0$slave_arready), - .slave_rvalid(uart0$slave_rvalid), - .slave_rid(uart0$slave_rid), - .slave_rdata(uart0$slave_rdata), - .slave_rresp(uart0$slave_rresp), - .slave_rlast(uart0$slave_rlast), - .get_to_console_get(uart0$get_to_console_get), - .RDY_get_to_console_get(uart0$RDY_get_to_console_get), - .RDY_put_from_console_put(uart0$RDY_put_from_console_put), - .intr(uart0$intr)); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_5 - assign CAN_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - - // rule RL_rl_wr_data_channel_5 - assign CAN_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_response_channel_5 - assign CAN_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_5 - assign CAN_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - - // rule RL_rl_rd_data_channel_5 - assign CAN_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_6 - assign CAN_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - - // rule RL_rl_wr_data_channel_6 - assign CAN_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - - // rule RL_rl_wr_response_channel_6 - assign CAN_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_6 - assign CAN_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - - // rule RL_rl_rd_data_channel_6 - assign CAN_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - - // rule RL_rl_connect_external_interrupt_requests - assign CAN_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - - // rule RL_rl_reset_start_initial - assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete_initial - assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete_initial = - MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = - mem0_controller$RDY_server_reset_request_put && - uart0$RDY_server_reset_request_put && - fabric$RDY_reset && - core$RDY_cpu_reset_server_request_put && - rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && - mem0_controller$RDY_server_reset_response_get && - uart0$RDY_server_reset_response_get && - core$RDY_cpu_reset_server_response_get && - rg_state == 2'd1 ; - - // register rg_state - assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_start_initial || - WILL_FIRE_RL_rl_reset_complete_initial ; - - // submodule boot_rom - assign boot_rom$set_addr_map_addr_base = soc_map$m_boot_rom_addr_base ; - assign boot_rom$set_addr_map_addr_lim = soc_map$m_boot_rom_addr_lim ; - assign boot_rom$slave_araddr = boot_rom_axi4_deburster$to_slave_araddr ; - assign boot_rom$slave_arburst = boot_rom_axi4_deburster$to_slave_arburst ; - assign boot_rom$slave_arcache = boot_rom_axi4_deburster$to_slave_arcache ; - assign boot_rom$slave_arid = boot_rom_axi4_deburster$to_slave_arid ; - assign boot_rom$slave_arlen = boot_rom_axi4_deburster$to_slave_arlen ; - assign boot_rom$slave_arlock = boot_rom_axi4_deburster$to_slave_arlock ; - assign boot_rom$slave_arprot = boot_rom_axi4_deburster$to_slave_arprot ; - assign boot_rom$slave_arqos = boot_rom_axi4_deburster$to_slave_arqos ; - assign boot_rom$slave_arregion = boot_rom_axi4_deburster$to_slave_arregion ; - assign boot_rom$slave_arsize = boot_rom_axi4_deburster$to_slave_arsize ; - assign boot_rom$slave_arvalid = boot_rom_axi4_deburster$to_slave_arvalid ; - assign boot_rom$slave_awaddr = boot_rom_axi4_deburster$to_slave_awaddr ; - assign boot_rom$slave_awburst = boot_rom_axi4_deburster$to_slave_awburst ; - assign boot_rom$slave_awcache = boot_rom_axi4_deburster$to_slave_awcache ; - assign boot_rom$slave_awid = boot_rom_axi4_deburster$to_slave_awid ; - assign boot_rom$slave_awlen = boot_rom_axi4_deburster$to_slave_awlen ; - assign boot_rom$slave_awlock = boot_rom_axi4_deburster$to_slave_awlock ; - assign boot_rom$slave_awprot = boot_rom_axi4_deburster$to_slave_awprot ; - assign boot_rom$slave_awqos = boot_rom_axi4_deburster$to_slave_awqos ; - assign boot_rom$slave_awregion = boot_rom_axi4_deburster$to_slave_awregion ; - assign boot_rom$slave_awsize = boot_rom_axi4_deburster$to_slave_awsize ; - assign boot_rom$slave_awvalid = boot_rom_axi4_deburster$to_slave_awvalid ; - assign boot_rom$slave_bready = boot_rom_axi4_deburster$to_slave_bready ; - assign boot_rom$slave_rready = boot_rom_axi4_deburster$to_slave_rready ; - assign boot_rom$slave_wdata = boot_rom_axi4_deburster$to_slave_wdata ; - assign boot_rom$slave_wid = boot_rom_axi4_deburster$to_slave_wid ; - assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; - assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; - assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - - // submodule boot_rom_axi4_deburster - assign boot_rom_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_0_araddr ; - assign boot_rom_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_0_arburst ; - assign boot_rom_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_0_arcache ; - assign boot_rom_axi4_deburster$from_master_arid = - fabric$v_to_slaves_0_arid ; - assign boot_rom_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_0_arlen ; - assign boot_rom_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_0_arlock ; - assign boot_rom_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_0_arprot ; - assign boot_rom_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_0_arqos ; - assign boot_rom_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_0_arregion ; - assign boot_rom_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_0_arsize ; - assign boot_rom_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_0_arvalid ; - assign boot_rom_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_0_awaddr ; - assign boot_rom_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_0_awburst ; - assign boot_rom_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_0_awcache ; - assign boot_rom_axi4_deburster$from_master_awid = - fabric$v_to_slaves_0_awid ; - assign boot_rom_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_0_awlen ; - assign boot_rom_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_0_awlock ; - assign boot_rom_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_0_awprot ; - assign boot_rom_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_0_awqos ; - assign boot_rom_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_0_awregion ; - assign boot_rom_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_0_awsize ; - assign boot_rom_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_0_awvalid ; - assign boot_rom_axi4_deburster$from_master_bready = - fabric$v_to_slaves_0_bready ; - assign boot_rom_axi4_deburster$from_master_rready = - fabric$v_to_slaves_0_rready ; - assign boot_rom_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_0_wdata ; - assign boot_rom_axi4_deburster$from_master_wid = fabric$v_to_slaves_0_wid ; - assign boot_rom_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_0_wlast ; - assign boot_rom_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_0_wstrb ; - assign boot_rom_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_0_wvalid ; - assign boot_rom_axi4_deburster$to_slave_arready = boot_rom$slave_arready ; - assign boot_rom_axi4_deburster$to_slave_awready = boot_rom$slave_awready ; - assign boot_rom_axi4_deburster$to_slave_bid = boot_rom$slave_bid ; - assign boot_rom_axi4_deburster$to_slave_bresp = boot_rom$slave_bresp ; - assign boot_rom_axi4_deburster$to_slave_bvalid = boot_rom$slave_bvalid ; - assign boot_rom_axi4_deburster$to_slave_rdata = boot_rom$slave_rdata ; - assign boot_rom_axi4_deburster$to_slave_rid = boot_rom$slave_rid ; - assign boot_rom_axi4_deburster$to_slave_rlast = boot_rom$slave_rlast ; - assign boot_rom_axi4_deburster$to_slave_rresp = boot_rom$slave_rresp ; - assign boot_rom_axi4_deburster$to_slave_rvalid = boot_rom$slave_rvalid ; - assign boot_rom_axi4_deburster$to_slave_wready = boot_rom$slave_wready ; - assign boot_rom_axi4_deburster$EN_reset = 1'b0 ; - - // submodule core - assign core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = - uart0$intr ; - assign core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$cpu_dmem_master_arready = fabric$v_from_masters_1_arready ; - assign core$cpu_dmem_master_awready = fabric$v_from_masters_1_awready ; - assign core$cpu_dmem_master_bid = fabric$v_from_masters_1_bid ; - assign core$cpu_dmem_master_bresp = fabric$v_from_masters_1_bresp ; - assign core$cpu_dmem_master_bvalid = fabric$v_from_masters_1_bvalid ; - assign core$cpu_dmem_master_rdata = fabric$v_from_masters_1_rdata ; - assign core$cpu_dmem_master_rid = fabric$v_from_masters_1_rid ; - assign core$cpu_dmem_master_rlast = fabric$v_from_masters_1_rlast ; - assign core$cpu_dmem_master_rresp = fabric$v_from_masters_1_rresp ; - assign core$cpu_dmem_master_rvalid = fabric$v_from_masters_1_rvalid ; - assign core$cpu_dmem_master_wready = fabric$v_from_masters_1_wready ; - assign core$cpu_imem_master_arready = fabric$v_from_masters_0_arready ; - assign core$cpu_imem_master_awready = fabric$v_from_masters_0_awready ; - assign core$cpu_imem_master_bid = fabric$v_from_masters_0_bid ; - assign core$cpu_imem_master_bresp = fabric$v_from_masters_0_bresp ; - assign core$cpu_imem_master_bvalid = fabric$v_from_masters_0_bvalid ; - assign core$cpu_imem_master_rdata = fabric$v_from_masters_0_rdata ; - assign core$cpu_imem_master_rid = fabric$v_from_masters_0_rid ; - assign core$cpu_imem_master_rlast = fabric$v_from_masters_0_rlast ; - assign core$cpu_imem_master_rresp = fabric$v_from_masters_0_rresp ; - assign core$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ; - assign core$cpu_imem_master_wready = fabric$v_from_masters_0_wready ; - assign core$cpu_reset_server_request_put = 1'd1 ; - assign core$nmi_req_set_not_clear = 1'd0 ; - assign core$set_verbosity_logdelay = set_verbosity_logdelay ; - assign core$set_verbosity_verbosity = set_verbosity_verbosity ; - assign core$EN_set_verbosity = EN_set_verbosity ; - assign core$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; - assign core$EN_cpu_reset_server_response_get = MUX_rg_state$write_1__SEL_2 ; - - // submodule fabric - assign fabric$set_verbosity_verbosity = 4'h0 ; - assign fabric$v_from_masters_0_araddr = core$cpu_imem_master_araddr ; - assign fabric$v_from_masters_0_arburst = core$cpu_imem_master_arburst ; - assign fabric$v_from_masters_0_arcache = core$cpu_imem_master_arcache ; - assign fabric$v_from_masters_0_arid = core$cpu_imem_master_arid ; - assign fabric$v_from_masters_0_arlen = core$cpu_imem_master_arlen ; - assign fabric$v_from_masters_0_arlock = core$cpu_imem_master_arlock ; - assign fabric$v_from_masters_0_arprot = core$cpu_imem_master_arprot ; - assign fabric$v_from_masters_0_arqos = core$cpu_imem_master_arqos ; - assign fabric$v_from_masters_0_arregion = core$cpu_imem_master_arregion ; - assign fabric$v_from_masters_0_arsize = core$cpu_imem_master_arsize ; - assign fabric$v_from_masters_0_arvalid = core$cpu_imem_master_arvalid ; - assign fabric$v_from_masters_0_awaddr = core$cpu_imem_master_awaddr ; - assign fabric$v_from_masters_0_awburst = core$cpu_imem_master_awburst ; - assign fabric$v_from_masters_0_awcache = core$cpu_imem_master_awcache ; - assign fabric$v_from_masters_0_awid = core$cpu_imem_master_awid ; - assign fabric$v_from_masters_0_awlen = core$cpu_imem_master_awlen ; - assign fabric$v_from_masters_0_awlock = core$cpu_imem_master_awlock ; - assign fabric$v_from_masters_0_awprot = core$cpu_imem_master_awprot ; - assign fabric$v_from_masters_0_awqos = core$cpu_imem_master_awqos ; - assign fabric$v_from_masters_0_awregion = core$cpu_imem_master_awregion ; - assign fabric$v_from_masters_0_awsize = core$cpu_imem_master_awsize ; - assign fabric$v_from_masters_0_awvalid = core$cpu_imem_master_awvalid ; - assign fabric$v_from_masters_0_bready = core$cpu_imem_master_bready ; - assign fabric$v_from_masters_0_rready = core$cpu_imem_master_rready ; - assign fabric$v_from_masters_0_wdata = core$cpu_imem_master_wdata ; - assign fabric$v_from_masters_0_wid = core$cpu_imem_master_wid ; - assign fabric$v_from_masters_0_wlast = core$cpu_imem_master_wlast ; - assign fabric$v_from_masters_0_wstrb = core$cpu_imem_master_wstrb ; - assign fabric$v_from_masters_0_wvalid = core$cpu_imem_master_wvalid ; - assign fabric$v_from_masters_1_araddr = core$cpu_dmem_master_araddr ; - assign fabric$v_from_masters_1_arburst = core$cpu_dmem_master_arburst ; - assign fabric$v_from_masters_1_arcache = core$cpu_dmem_master_arcache ; - assign fabric$v_from_masters_1_arid = core$cpu_dmem_master_arid ; - assign fabric$v_from_masters_1_arlen = core$cpu_dmem_master_arlen ; - assign fabric$v_from_masters_1_arlock = core$cpu_dmem_master_arlock ; - assign fabric$v_from_masters_1_arprot = core$cpu_dmem_master_arprot ; - assign fabric$v_from_masters_1_arqos = core$cpu_dmem_master_arqos ; - assign fabric$v_from_masters_1_arregion = core$cpu_dmem_master_arregion ; - assign fabric$v_from_masters_1_arsize = core$cpu_dmem_master_arsize ; - assign fabric$v_from_masters_1_arvalid = core$cpu_dmem_master_arvalid ; - assign fabric$v_from_masters_1_awaddr = core$cpu_dmem_master_awaddr ; - assign fabric$v_from_masters_1_awburst = core$cpu_dmem_master_awburst ; - assign fabric$v_from_masters_1_awcache = core$cpu_dmem_master_awcache ; - assign fabric$v_from_masters_1_awid = core$cpu_dmem_master_awid ; - assign fabric$v_from_masters_1_awlen = core$cpu_dmem_master_awlen ; - assign fabric$v_from_masters_1_awlock = core$cpu_dmem_master_awlock ; - assign fabric$v_from_masters_1_awprot = core$cpu_dmem_master_awprot ; - assign fabric$v_from_masters_1_awqos = core$cpu_dmem_master_awqos ; - assign fabric$v_from_masters_1_awregion = core$cpu_dmem_master_awregion ; - assign fabric$v_from_masters_1_awsize = core$cpu_dmem_master_awsize ; - assign fabric$v_from_masters_1_awvalid = core$cpu_dmem_master_awvalid ; - assign fabric$v_from_masters_1_bready = core$cpu_dmem_master_bready ; - assign fabric$v_from_masters_1_rready = core$cpu_dmem_master_rready ; - assign fabric$v_from_masters_1_wdata = core$cpu_dmem_master_wdata ; - assign fabric$v_from_masters_1_wid = core$cpu_dmem_master_wid ; - assign fabric$v_from_masters_1_wlast = core$cpu_dmem_master_wlast ; - assign fabric$v_from_masters_1_wstrb = core$cpu_dmem_master_wstrb ; - assign fabric$v_from_masters_1_wvalid = core$cpu_dmem_master_wvalid ; - assign fabric$v_to_slaves_0_arready = - boot_rom_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_0_awready = - boot_rom_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_0_bid = boot_rom_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_0_bresp = - boot_rom_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_0_bvalid = - boot_rom_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_0_rdata = - boot_rom_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_0_rid = boot_rom_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_0_rlast = - boot_rom_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_0_rresp = - boot_rom_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_0_rvalid = - boot_rom_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_0_wready = - boot_rom_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_1_arready = - mem0_controller_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_1_awready = - mem0_controller_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_1_bid = - mem0_controller_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_1_bresp = - mem0_controller_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_1_bvalid = - mem0_controller_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_1_rdata = - mem0_controller_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_1_rid = - mem0_controller_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_1_rlast = - mem0_controller_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_1_rresp = - mem0_controller_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_1_rvalid = - mem0_controller_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_1_wready = - mem0_controller_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_2_arready = uart0$slave_arready ; - assign fabric$v_to_slaves_2_awready = uart0$slave_awready ; - assign fabric$v_to_slaves_2_bid = uart0$slave_bid ; - assign fabric$v_to_slaves_2_bresp = uart0$slave_bresp ; - assign fabric$v_to_slaves_2_bvalid = uart0$slave_bvalid ; - assign fabric$v_to_slaves_2_rdata = uart0$slave_rdata ; - assign fabric$v_to_slaves_2_rid = uart0$slave_rid ; - assign fabric$v_to_slaves_2_rlast = uart0$slave_rlast ; - assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; - assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; - assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; - assign fabric$EN_set_verbosity = 1'b0 ; - - // submodule mem0_controller - assign mem0_controller$set_addr_map_addr_base = - soc_map$m_mem0_controller_addr_base ; - assign mem0_controller$set_addr_map_addr_lim = - soc_map$m_mem0_controller_addr_lim ; - assign mem0_controller$set_watch_tohost_tohost_addr = - set_watch_tohost_tohost_addr ; - assign mem0_controller$set_watch_tohost_watch_tohost = - set_watch_tohost_watch_tohost ; - assign mem0_controller$slave_araddr = - mem0_controller_axi4_deburster$to_slave_araddr ; - assign mem0_controller$slave_arburst = - mem0_controller_axi4_deburster$to_slave_arburst ; - assign mem0_controller$slave_arcache = - mem0_controller_axi4_deburster$to_slave_arcache ; - assign mem0_controller$slave_arid = - mem0_controller_axi4_deburster$to_slave_arid ; - assign mem0_controller$slave_arlen = - mem0_controller_axi4_deburster$to_slave_arlen ; - assign mem0_controller$slave_arlock = - mem0_controller_axi4_deburster$to_slave_arlock ; - assign mem0_controller$slave_arprot = - mem0_controller_axi4_deburster$to_slave_arprot ; - assign mem0_controller$slave_arqos = - mem0_controller_axi4_deburster$to_slave_arqos ; - assign mem0_controller$slave_arregion = - mem0_controller_axi4_deburster$to_slave_arregion ; - assign mem0_controller$slave_arsize = - mem0_controller_axi4_deburster$to_slave_arsize ; - assign mem0_controller$slave_arvalid = - mem0_controller_axi4_deburster$to_slave_arvalid ; - assign mem0_controller$slave_awaddr = - mem0_controller_axi4_deburster$to_slave_awaddr ; - assign mem0_controller$slave_awburst = - mem0_controller_axi4_deburster$to_slave_awburst ; - assign mem0_controller$slave_awcache = - mem0_controller_axi4_deburster$to_slave_awcache ; - assign mem0_controller$slave_awid = - mem0_controller_axi4_deburster$to_slave_awid ; - assign mem0_controller$slave_awlen = - mem0_controller_axi4_deburster$to_slave_awlen ; - assign mem0_controller$slave_awlock = - mem0_controller_axi4_deburster$to_slave_awlock ; - assign mem0_controller$slave_awprot = - mem0_controller_axi4_deburster$to_slave_awprot ; - assign mem0_controller$slave_awqos = - mem0_controller_axi4_deburster$to_slave_awqos ; - assign mem0_controller$slave_awregion = - mem0_controller_axi4_deburster$to_slave_awregion ; - assign mem0_controller$slave_awsize = - mem0_controller_axi4_deburster$to_slave_awsize ; - assign mem0_controller$slave_awvalid = - mem0_controller_axi4_deburster$to_slave_awvalid ; - assign mem0_controller$slave_bready = - mem0_controller_axi4_deburster$to_slave_bready ; - assign mem0_controller$slave_rready = - mem0_controller_axi4_deburster$to_slave_rready ; - assign mem0_controller$slave_wdata = - mem0_controller_axi4_deburster$to_slave_wdata ; - assign mem0_controller$slave_wid = - mem0_controller_axi4_deburster$to_slave_wid ; - assign mem0_controller$slave_wlast = - mem0_controller_axi4_deburster$to_slave_wlast ; - assign mem0_controller$slave_wstrb = - mem0_controller_axi4_deburster$to_slave_wstrb ; - assign mem0_controller$slave_wvalid = - mem0_controller_axi4_deburster$to_slave_wvalid ; - assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; - assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; - assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_to_raw_mem_request_get = - EN_to_raw_mem_request_get ; - assign mem0_controller$EN_to_raw_mem_response_put = - EN_to_raw_mem_response_put ; - assign mem0_controller$EN_set_watch_tohost = EN_set_watch_tohost ; - - // submodule mem0_controller_axi4_deburster - assign mem0_controller_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_1_araddr ; - assign mem0_controller_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_1_arburst ; - assign mem0_controller_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_1_arcache ; - assign mem0_controller_axi4_deburster$from_master_arid = - fabric$v_to_slaves_1_arid ; - assign mem0_controller_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_1_arlen ; - assign mem0_controller_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_1_arlock ; - assign mem0_controller_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_1_arprot ; - assign mem0_controller_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_1_arqos ; - assign mem0_controller_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_1_arregion ; - assign mem0_controller_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_1_arsize ; - assign mem0_controller_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_1_arvalid ; - assign mem0_controller_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_1_awaddr ; - assign mem0_controller_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_1_awburst ; - assign mem0_controller_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_1_awcache ; - assign mem0_controller_axi4_deburster$from_master_awid = - fabric$v_to_slaves_1_awid ; - assign mem0_controller_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_1_awlen ; - assign mem0_controller_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_1_awlock ; - assign mem0_controller_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_1_awprot ; - assign mem0_controller_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_1_awqos ; - assign mem0_controller_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_1_awregion ; - assign mem0_controller_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_1_awsize ; - assign mem0_controller_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_1_awvalid ; - assign mem0_controller_axi4_deburster$from_master_bready = - fabric$v_to_slaves_1_bready ; - assign mem0_controller_axi4_deburster$from_master_rready = - fabric$v_to_slaves_1_rready ; - assign mem0_controller_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_1_wdata ; - assign mem0_controller_axi4_deburster$from_master_wid = - fabric$v_to_slaves_1_wid ; - assign mem0_controller_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_1_wlast ; - assign mem0_controller_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_1_wstrb ; - assign mem0_controller_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_1_wvalid ; - assign mem0_controller_axi4_deburster$to_slave_arready = - mem0_controller$slave_arready ; - assign mem0_controller_axi4_deburster$to_slave_awready = - mem0_controller$slave_awready ; - assign mem0_controller_axi4_deburster$to_slave_bid = - mem0_controller$slave_bid ; - assign mem0_controller_axi4_deburster$to_slave_bresp = - mem0_controller$slave_bresp ; - assign mem0_controller_axi4_deburster$to_slave_bvalid = - mem0_controller$slave_bvalid ; - assign mem0_controller_axi4_deburster$to_slave_rdata = - mem0_controller$slave_rdata ; - assign mem0_controller_axi4_deburster$to_slave_rid = - mem0_controller$slave_rid ; - assign mem0_controller_axi4_deburster$to_slave_rlast = - mem0_controller$slave_rlast ; - assign mem0_controller_axi4_deburster$to_slave_rresp = - mem0_controller$slave_rresp ; - assign mem0_controller_axi4_deburster$to_slave_rvalid = - mem0_controller$slave_rvalid ; - assign mem0_controller_axi4_deburster$to_slave_wready = - mem0_controller$slave_wready ; - assign mem0_controller_axi4_deburster$EN_reset = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule uart0 - assign uart0$put_from_console_put = put_from_console_put ; - assign uart0$set_addr_map_addr_base = soc_map$m_uart0_addr_base ; - assign uart0$set_addr_map_addr_lim = soc_map$m_uart0_addr_lim ; - assign uart0$slave_araddr = fabric$v_to_slaves_2_araddr ; - assign uart0$slave_arburst = fabric$v_to_slaves_2_arburst ; - assign uart0$slave_arcache = fabric$v_to_slaves_2_arcache ; - assign uart0$slave_arid = fabric$v_to_slaves_2_arid ; - assign uart0$slave_arlen = fabric$v_to_slaves_2_arlen ; - assign uart0$slave_arlock = fabric$v_to_slaves_2_arlock ; - assign uart0$slave_arprot = fabric$v_to_slaves_2_arprot ; - assign uart0$slave_arqos = fabric$v_to_slaves_2_arqos ; - assign uart0$slave_arregion = fabric$v_to_slaves_2_arregion ; - assign uart0$slave_arsize = fabric$v_to_slaves_2_arsize ; - assign uart0$slave_arvalid = fabric$v_to_slaves_2_arvalid ; - assign uart0$slave_awaddr = fabric$v_to_slaves_2_awaddr ; - assign uart0$slave_awburst = fabric$v_to_slaves_2_awburst ; - assign uart0$slave_awcache = fabric$v_to_slaves_2_awcache ; - assign uart0$slave_awid = fabric$v_to_slaves_2_awid ; - assign uart0$slave_awlen = fabric$v_to_slaves_2_awlen ; - assign uart0$slave_awlock = fabric$v_to_slaves_2_awlock ; - assign uart0$slave_awprot = fabric$v_to_slaves_2_awprot ; - assign uart0$slave_awqos = fabric$v_to_slaves_2_awqos ; - assign uart0$slave_awregion = fabric$v_to_slaves_2_awregion ; - assign uart0$slave_awsize = fabric$v_to_slaves_2_awsize ; - assign uart0$slave_awvalid = fabric$v_to_slaves_2_awvalid ; - assign uart0$slave_bready = fabric$v_to_slaves_2_bready ; - assign uart0$slave_rready = fabric$v_to_slaves_2_rready ; - assign uart0$slave_wdata = fabric$v_to_slaves_2_wdata ; - assign uart0$slave_wid = fabric$v_to_slaves_2_wid ; - assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; - assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; - assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_get_to_console_get = EN_get_to_console_get ; - assign uart0$EN_put_from_console_put = EN_put_from_console_put ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - begin - v__h11286 = $stime; - #0; - end - v__h11280 = v__h11286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - $display("%0d:%m.rl_reset_start_initial ...", v__h11280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - begin - v__h11556 = $stime; - #0; - end - v__h11550 = v__h11556 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - $display("%0d:%m.rl_reset_complete_initial", v__h11550); - end - // synopsys translate_on -endmodule // mkSoC_Top - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v deleted file mode 100644 index a195f14f..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v +++ /dev/null @@ -1,255 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// CLK I 1 clock -// RST_N I 1 reset -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTop_HW_Side(CLK, - RST_N); - input CLK; - input RST_N; - - // register rg_banner_printed - reg rg_banner_printed; - wire rg_banner_printed$D_IN, rg_banner_printed$EN; - - // ports of submodule mem_model - wire [352 : 0] mem_model$mem_server_request_put; - wire [255 : 0] mem_model$mem_server_response_get; - wire mem_model$EN_mem_server_request_put, - mem_model$EN_mem_server_response_get, - mem_model$RDY_mem_server_request_put, - mem_model$RDY_mem_server_response_get; - - // ports of submodule soc_top - wire [352 : 0] soc_top$to_raw_mem_request_get; - wire [255 : 0] soc_top$to_raw_mem_response_put; - wire [63 : 0] soc_top$set_verbosity_logdelay, - soc_top$set_watch_tohost_tohost_addr; - wire [7 : 0] soc_top$get_to_console_get, - soc_top$put_from_console_put, - soc_top$status; - wire [3 : 0] soc_top$set_verbosity_verbosity; - wire soc_top$EN_get_to_console_get, - soc_top$EN_put_from_console_put, - soc_top$EN_set_verbosity, - soc_top$EN_set_watch_tohost, - soc_top$EN_to_raw_mem_request_get, - soc_top$EN_to_raw_mem_response_put, - soc_top$RDY_get_to_console_get, - soc_top$RDY_to_raw_mem_request_get, - soc_top$RDY_to_raw_mem_response_put, - soc_top$set_watch_tohost_watch_tohost; - - // rule scheduling signals - wire CAN_FIRE_RL_memCnx_ClientServerRequest, - CAN_FIRE_RL_memCnx_ClientServerResponse, - CAN_FIRE_RL_rl_relay_console_out, - CAN_FIRE_RL_rl_step0, - CAN_FIRE_RL_rl_terminate, - WILL_FIRE_RL_memCnx_ClientServerRequest, - WILL_FIRE_RL_memCnx_ClientServerResponse, - WILL_FIRE_RL_rl_relay_console_out, - WILL_FIRE_RL_rl_step0, - WILL_FIRE_RL_rl_terminate; - - // declarations used by system tasks - // synopsys translate_off - reg TASK_testplusargs___d12; - reg TASK_testplusargs___d11; - reg [31 : 0] v__h536; - reg [31 : 0] v__h530; - // synopsys translate_on - - // submodule mem_model - mkMem_Model mem_model(.CLK(CLK), - .RST_N(RST_N), - .mem_server_request_put(mem_model$mem_server_request_put), - .EN_mem_server_request_put(mem_model$EN_mem_server_request_put), - .EN_mem_server_response_get(mem_model$EN_mem_server_response_get), - .RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put), - .mem_server_response_get(mem_model$mem_server_response_get), - .RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get)); - - // submodule soc_top - mkSoC_Top soc_top(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(soc_top$put_from_console_put), - .set_verbosity_logdelay(soc_top$set_verbosity_logdelay), - .set_verbosity_verbosity(soc_top$set_verbosity_verbosity), - .set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost), - .to_raw_mem_response_put(soc_top$to_raw_mem_response_put), - .EN_set_verbosity(soc_top$EN_set_verbosity), - .EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put), - .EN_get_to_console_get(soc_top$EN_get_to_console_get), - .EN_put_from_console_put(soc_top$EN_put_from_console_put), - .EN_set_watch_tohost(soc_top$EN_set_watch_tohost), - .RDY_set_verbosity(), - .to_raw_mem_request_get(soc_top$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put), - .get_to_console_get(soc_top$get_to_console_get), - .RDY_get_to_console_get(soc_top$RDY_get_to_console_get), - .RDY_put_from_console_put(), - .status(soc_top$status), - .RDY_set_watch_tohost()); - - // rule RL_rl_step0 - assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ; - assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ; - - // rule RL_rl_terminate - assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ; - assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ; - - // rule RL_rl_relay_console_out - assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - - // rule RL_memCnx_ClientServerRequest - assign CAN_FIRE_RL_memCnx_ClientServerRequest = - soc_top$RDY_to_raw_mem_request_get && - mem_model$RDY_mem_server_request_put ; - assign WILL_FIRE_RL_memCnx_ClientServerRequest = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - - // rule RL_memCnx_ClientServerResponse - assign CAN_FIRE_RL_memCnx_ClientServerResponse = - soc_top$RDY_to_raw_mem_response_put && - mem_model$RDY_mem_server_response_get ; - assign WILL_FIRE_RL_memCnx_ClientServerResponse = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // register rg_banner_printed - assign rg_banner_printed$D_IN = 1'd1 ; - assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ; - - // submodule mem_model - assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ; - assign mem_model$EN_mem_server_request_put = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign mem_model$EN_mem_server_response_get = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // submodule soc_top - assign soc_top$put_from_console_put = 8'h0 ; - assign soc_top$set_verbosity_logdelay = 64'd0 ; - assign soc_top$set_verbosity_verbosity = - TASK_testplusargs___d11 ? - 4'd2 : - (TASK_testplusargs___d12 ? 4'd1 : 4'd0) ; - assign soc_top$set_watch_tohost_tohost_addr = 64'h0 ; - assign soc_top$set_watch_tohost_watch_tohost = 1'b0 ; - assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ; - assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ; - assign soc_top$EN_to_raw_mem_request_get = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign soc_top$EN_to_raw_mem_response_put = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ; - assign soc_top$EN_put_from_console_put = 1'b0 ; - assign soc_top$EN_set_watch_tohost = 1'b0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_banner_printed$EN) - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_banner_printed = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Bluespec RISC-V standalone system simulation v1.2"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d12 = $test$plusargs("v1"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d11 = $test$plusargs("v2"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h536 = $stime; - #0; - end - v__h530 = v__h536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $display("%0d: %m.rl_terminate: soc_top status is 0x%0h (= 0d%0d)", - v__h530, - soc_top$status, - soc_top$status); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) - $write("%c", soc_top$get_to_console_get); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001); - end - // synopsys translate_on -endmodule // mkTop_HW_Side - diff --git a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkUART.v b/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkUART.v deleted file mode 100644 index 033775ea..00000000 --- a/builds/RV32ACIMU_Piccolo_iverilog/Verilog_RTL/mkUART.v +++ /dev/null @@ -1,2925 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// intr O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// put_from_console_put I 8 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_put_from_console_put I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkUART(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - intr); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method intr - output intr; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [7 : 0] get_to_console_get; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - intr, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register cfg_verbosity - reg [7 : 0] cfg_verbosity; - wire [7 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_dll - reg [7 : 0] rg_dll; - wire [7 : 0] rg_dll$D_IN; - wire rg_dll$EN; - - // register rg_dlm - reg [7 : 0] rg_dlm; - wire [7 : 0] rg_dlm$D_IN; - wire rg_dlm$EN; - - // register rg_fcr - reg [7 : 0] rg_fcr; - wire [7 : 0] rg_fcr$D_IN; - wire rg_fcr$EN; - - // register rg_ier - reg [7 : 0] rg_ier; - wire [7 : 0] rg_ier$D_IN; - wire rg_ier$EN; - - // register rg_lcr - reg [7 : 0] rg_lcr; - wire [7 : 0] rg_lcr$D_IN; - wire rg_lcr$EN; - - // register rg_lsr - reg [7 : 0] rg_lsr; - reg [7 : 0] rg_lsr$D_IN; - wire rg_lsr$EN; - - // register rg_mcr - reg [7 : 0] rg_mcr; - wire [7 : 0] rg_mcr$D_IN; - wire rg_mcr$EN; - - // register rg_msr - reg [7 : 0] rg_msr; - wire [7 : 0] rg_msr$D_IN; - wire rg_msr$EN; - - // register rg_rbr - reg [7 : 0] rg_rbr; - wire [7 : 0] rg_rbr$D_IN; - wire rg_rbr$EN; - - // register rg_scr - reg [7 : 0] rg_scr; - wire [7 : 0] rg_scr$D_IN; - wire rg_scr$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_thr - reg [7 : 0] rg_thr; - wire [7 : 0] rg_thr$D_IN; - wire rg_thr$EN; - - // ports of submodule f_from_console - wire [7 : 0] f_from_console$D_IN, f_from_console$D_OUT; - wire f_from_console$CLR, - f_from_console$DEQ, - f_from_console$EMPTY_N, - f_from_console$ENQ, - f_from_console$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_to_console - wire [7 : 0] f_to_console$D_IN, f_to_console$D_OUT; - wire f_to_console$CLR, - f_to_console$DEQ, - f_to_console$EMPTY_N, - f_to_console$ENQ, - f_to_console$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_receive, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_receive, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_rg_lsr$write_1__VAL_3; - wire MUX_rg_lsr$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2519; - reg [31 : 0] v__h2187; - reg [31 : 0] v__h2025; - reg [31 : 0] v__h2898; - reg [31 : 0] v__h3244; - reg [31 : 0] v__h4006; - reg [31 : 0] v__h3449; - reg [31 : 0] v__h4306; - reg [31 : 0] v__h4749; - reg [31 : 0] v__h4859; - reg [31 : 0] v__h1811; - reg [31 : 0] v__h1805; - reg [31 : 0] v__h2019; - reg [31 : 0] v__h2181; - reg [31 : 0] v__h2513; - reg [31 : 0] v__h2892; - reg [31 : 0] v__h3238; - reg [31 : 0] v__h3443; - reg [31 : 0] v__h4000; - reg [31 : 0] v__h4300; - reg [31 : 0] v__h4743; - reg [31 : 0] v__h4853; - // synopsys translate_on - - // remaining internal signals - reg [7 : 0] y_avValue_snd__h2683; - wire [63 : 0] rdata__h2759, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133; - wire [7 : 0] fn_iir__h1356, - new_lsr__h4516, - x__h2797, - y_avValue_snd__h2696, - y_avValue_snd__h2709, - y_avValue_snd__h2724, - y_avValue_snd__h2738; - wire [1 : 0] rdr_rresp__h2792, - v__h3147, - v__h3395, - v__h3575, - y_avValue_fst__h2737, - y_avValue_fst__h2751; - wire NOT_cfg_verbosity_read_ULE_1_24___d125, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188, - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method get_to_console_get - assign get_to_console_get = f_to_console$D_OUT ; - assign RDY_get_to_console_get = f_to_console$EMPTY_N ; - assign CAN_FIRE_get_to_console_get = f_to_console$EMPTY_N ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = f_from_console$FULL_N ; - assign CAN_FIRE_put_from_console_put = f_from_console$FULL_N ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method intr - assign intr = !fn_iir__h1356[0] ; - - // submodule f_from_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_from_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_from_console$D_IN), - .ENQ(f_from_console$ENQ), - .DEQ(f_from_console$DEQ), - .CLR(f_from_console$CLR), - .D_OUT(f_from_console$D_OUT), - .FULL_N(f_from_console$FULL_N), - .EMPTY_N(f_from_console$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_to_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_to_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_to_console$D_IN), - .ENQ(f_to_console$ENQ), - .DEQ(f_to_console$DEQ), - .CLR(f_to_console$CLR), - .D_OUT(f_to_console$D_OUT), - .FULL_N(f_to_console$FULL_N), - .EMPTY_N(f_to_console$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 && - rg_state ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_receive - assign CAN_FIRE_RL_rl_receive = f_from_console$EMPTY_N && !rg_lsr[0] ; - assign WILL_FIRE_RL_rl_receive = - CAN_FIRE_RL_rl_receive && !WILL_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_rg_lsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 ; - assign MUX_rg_lsr$write_1__VAL_3 = { rg_lsr[7:1], 1'd0 } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 8'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_dll - assign rg_dll$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dll$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 || - WILL_FIRE_RL_rl_reset ; - - // register rg_dlm - assign rg_dlm$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dlm$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 || - WILL_FIRE_RL_rl_reset ; - - // register rg_fcr - assign rg_fcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_fcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h2 || - WILL_FIRE_RL_rl_reset ; - - // register rg_ier - assign rg_ier$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_ier$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lcr - assign rg_lcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_lcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h3 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lsr - always@(WILL_FIRE_RL_rl_reset or - WILL_FIRE_RL_rl_receive or - new_lsr__h4516 or - MUX_rg_lsr$write_1__SEL_3 or MUX_rg_lsr$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset: rg_lsr$D_IN = 8'd96; - WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h4516; - MUX_rg_lsr$write_1__SEL_3: rg_lsr$D_IN = MUX_rg_lsr$write_1__VAL_3; - default: rg_lsr$D_IN = 8'b10101010 /* unspecified value */ ; - endcase - assign rg_lsr$EN = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 || - WILL_FIRE_RL_rl_receive || - WILL_FIRE_RL_rl_reset ; - - // register rg_mcr - assign rg_mcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_mcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h4 || - WILL_FIRE_RL_rl_reset ; - - // register rg_msr - assign rg_msr$D_IN = 8'd0 ; - assign rg_msr$EN = CAN_FIRE_RL_rl_reset ; - - // register rg_rbr - assign rg_rbr$D_IN = f_from_console$D_OUT ; - assign rg_rbr$EN = WILL_FIRE_RL_rl_receive ; - - // register rg_scr - assign rg_scr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_scr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h7 || - WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = 1'd1 ; - assign rg_state$EN = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // register rg_thr - assign rg_thr$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_thr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - - // submodule f_from_console - assign f_from_console$D_IN = put_from_console_put ; - assign f_from_console$ENQ = EN_put_from_console_put ; - assign f_from_console$DEQ = WILL_FIRE_RL_rl_receive ; - assign f_from_console$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_to_console - assign f_to_console$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign f_to_console$ENQ = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - assign f_to_console$DEQ = EN_get_to_console_get ; - assign f_to_console$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h2759, - rdr_rresp__h2792, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3147 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_24___d125 = cfg_verbosity > 8'd1 ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - slave_xactor_f_wr_data$D_OUT[0] ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - !slave_xactor_f_wr_data$D_OUT[0] ; - assign fn_iir__h1356 = - (rg_ier[0] && rg_lsr[0]) ? 8'h04 : (rg_ier[1] ? 8'h02 : 8'd0) ; - assign new_lsr__h4516 = { rg_lsr[7:1], 1'd1 } ; - assign rdata__h2759 = { 56'd0, x__h2797 } ; - assign rdr_rresp__h2792 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0) ? - y_avValue_fst__h2751 : - 2'b10 ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 = - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - rg_lcr[7] ; - assign slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 = - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1] || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7] || - f_to_console$FULL_N) ; - assign v__h3147 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) ? - 2'b10 : - v__h3395 ; - assign v__h3395 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0) ? - v__h3575 : - 2'b11 ; - assign v__h3575 = y_avValue_fst__h2737 ; - assign x__h2797 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0 || - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) ? - 8'd0 : - y_avValue_snd__h2738 ; - assign y_avValue_fst__h2737 = 2'b0 ; - assign y_avValue_fst__h2751 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0) ? - y_avValue_fst__h2737 : - 2'b11 ; - assign y_avValue_snd__h2696 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - rg_lcr[7]) ? - rg_dlm : - y_avValue_snd__h2683 ; - assign y_avValue_snd__h2709 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - !rg_lcr[7]) ? - rg_ier : - y_avValue_snd__h2696 ; - assign y_avValue_snd__h2724 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - rg_lcr[7]) ? - rg_dll : - y_avValue_snd__h2709 ; - assign y_avValue_snd__h2738 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7]) ? - rg_rbr : - y_avValue_snd__h2724 ; - always@(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 or - fn_iir__h1356 or rg_lcr or rg_mcr or rg_lsr or rg_msr or rg_scr) - begin - case (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3]) - 3'h2: y_avValue_snd__h2683 = fn_iir__h1356; - 3'h3: y_avValue_snd__h2683 = rg_lcr; - 3'h4: y_avValue_snd__h2683 = rg_mcr; - 3'h5: y_avValue_snd__h2683 = rg_lsr; - 3'h6: y_avValue_snd__h2683 = rg_msr; - 3'h7: y_avValue_snd__h2683 = rg_scr; - default: y_avValue_snd__h2683 = 8'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dll <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dlm <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_fcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_ier <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lsr <= `BSV_ASSIGNMENT_DELAY 8'd96; - rg_mcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_msr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_scr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_dll$EN) rg_dll <= `BSV_ASSIGNMENT_DELAY rg_dll$D_IN; - if (rg_dlm$EN) rg_dlm <= `BSV_ASSIGNMENT_DELAY rg_dlm$D_IN; - if (rg_fcr$EN) rg_fcr <= `BSV_ASSIGNMENT_DELAY rg_fcr$D_IN; - if (rg_ier$EN) rg_ier <= `BSV_ASSIGNMENT_DELAY rg_ier$D_IN; - if (rg_lcr$EN) rg_lcr <= `BSV_ASSIGNMENT_DELAY rg_lcr$D_IN; - if (rg_lsr$EN) rg_lsr <= `BSV_ASSIGNMENT_DELAY rg_lsr$D_IN; - if (rg_mcr$EN) rg_mcr <= `BSV_ASSIGNMENT_DELAY rg_mcr$D_IN; - if (rg_msr$EN) rg_msr <= `BSV_ASSIGNMENT_DELAY rg_msr$D_IN; - if (rg_scr$EN) rg_scr <= `BSV_ASSIGNMENT_DELAY rg_scr$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_rbr$EN) rg_rbr <= `BSV_ASSIGNMENT_DELAY rg_rbr$D_IN; - if (rg_thr$EN) rg_thr <= `BSV_ASSIGNMENT_DELAY rg_thr$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 8'hAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_dll = 8'hAA; - rg_dlm = 8'hAA; - rg_fcr = 8'hAA; - rg_ier = 8'hAA; - rg_lcr = 8'hAA; - rg_lsr = 8'hAA; - rg_mcr = 8'hAA; - rg_msr = 8'hAA; - rg_rbr = 8'hAA; - rg_scr = 8'hAA; - rg_state = 1'h0; - rg_thr = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - begin - v__h2519 = $stime; - #0; - end - v__h2513 = v__h2519 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2513); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - begin - v__h2187 = $stime; - #0; - end - v__h2181 = v__h2187 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2181); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - begin - v__h2025 = $stime; - #0; - end - v__h2019 = v__h2025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: misaligned addr", - v__h2019); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h2898 = $stime; - #0; - end - v__h2892 = v__h2898 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_rd_req", v__h2892); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdata__h2759); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdr_rresp__h2792); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - begin - v__h3244 = $stime; - #0; - end - v__h3238 = v__h3244 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $display("%0d: ERROR: UART.rl_process_wr_req: misaligned addr", - v__h3238); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - begin - v__h4006 = $stime; - #0; - end - v__h4000 = v__h4006 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h4000); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - begin - v__h3449 = $stime; - #0; - end - v__h3443 = v__h3449 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h3443); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h4306 = $stime; - #0; - end - v__h4300 = v__h4306 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_wr_req", v__h4300); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", v__h3147); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h4749 = $stime; - #0; - end - v__h4743 = v__h4749 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_base 0x%0h is not 8-Byte-aligned", - v__h4743, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h4859 = $stime; - #0; - end - v__h4853 = v__h4859 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_lim 0x%0h is not 8-Byte-aligned", - v__h4853, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_receive && NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("UART_Model.rl_receive: received char 0x%0h; new_lsr = 0x%0h", - f_from_console$D_OUT, - new_lsr__h4516); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - begin - v__h1811 = $stime; - #0; - end - v__h1805 = v__h1811 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - $display("%0d: UART.rl_reset", v__h1805); - end - // synopsys translate_on -endmodule // mkUART - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v deleted file mode 100644 index 7cb306e0..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v +++ /dev/null @@ -1,1389 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// from_master_awready O 1 reg -// from_master_wready O 1 reg -// from_master_bvalid O 1 reg -// from_master_bid O 4 reg -// from_master_bresp O 2 reg -// from_master_arready O 1 reg -// from_master_rvalid O 1 reg -// from_master_rid O 4 reg -// from_master_rdata O 64 reg -// from_master_rresp O 2 reg -// from_master_rlast O 1 reg -// to_slave_awvalid O 1 reg -// to_slave_awid O 4 reg -// to_slave_awaddr O 64 reg -// to_slave_awlen O 8 reg -// to_slave_awsize O 3 reg -// to_slave_awburst O 2 reg -// to_slave_awlock O 1 reg -// to_slave_awcache O 4 reg -// to_slave_awprot O 3 reg -// to_slave_awqos O 4 reg -// to_slave_awregion O 4 reg -// to_slave_wvalid O 1 reg -// to_slave_wdata O 64 reg -// to_slave_wstrb O 8 reg -// to_slave_wlast O 1 reg -// to_slave_bready O 1 reg -// to_slave_arvalid O 1 reg -// to_slave_arid O 4 reg -// to_slave_araddr O 64 reg -// to_slave_arlen O 8 reg -// to_slave_arsize O 3 reg -// to_slave_arburst O 2 reg -// to_slave_arlock O 1 reg -// to_slave_arcache O 4 reg -// to_slave_arprot O 3 reg -// to_slave_arqos O 4 reg -// to_slave_arregion O 4 reg -// to_slave_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// from_master_awvalid I 1 -// from_master_awid I 4 reg -// from_master_awaddr I 64 reg -// from_master_awlen I 8 reg -// from_master_awsize I 3 reg -// from_master_awburst I 2 reg -// from_master_awlock I 1 reg -// from_master_awcache I 4 reg -// from_master_awprot I 3 reg -// from_master_awqos I 4 reg -// from_master_awregion I 4 reg -// from_master_wvalid I 1 -// from_master_wdata I 64 reg -// from_master_wstrb I 8 reg -// from_master_wlast I 1 reg -// from_master_bready I 1 -// from_master_arvalid I 1 -// from_master_arid I 4 reg -// from_master_araddr I 64 reg -// from_master_arlen I 8 reg -// from_master_arsize I 3 reg -// from_master_arburst I 2 reg -// from_master_arlock I 1 reg -// from_master_arcache I 4 reg -// from_master_arprot I 3 reg -// from_master_arqos I 4 reg -// from_master_arregion I 4 reg -// from_master_rready I 1 -// to_slave_awready I 1 -// to_slave_wready I 1 -// to_slave_bvalid I 1 -// to_slave_bid I 4 reg -// to_slave_bresp I 2 reg -// to_slave_arready I 1 -// to_slave_rvalid I 1 -// to_slave_rid I 4 reg -// to_slave_rdata I 64 reg -// to_slave_rresp I 2 reg -// to_slave_rlast I 1 reg -// EN_reset I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkAXI4_Deburster_A(CLK, - RST_N, - - EN_reset, - RDY_reset, - - from_master_awvalid, - from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion, - - from_master_awready, - - from_master_wvalid, - from_master_wdata, - from_master_wstrb, - from_master_wlast, - - from_master_wready, - - from_master_bvalid, - - from_master_bid, - - from_master_bresp, - - from_master_bready, - - from_master_arvalid, - from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion, - - from_master_arready, - - from_master_rvalid, - - from_master_rid, - - from_master_rdata, - - from_master_rresp, - - from_master_rlast, - - from_master_rready, - - to_slave_awvalid, - - to_slave_awid, - - to_slave_awaddr, - - to_slave_awlen, - - to_slave_awsize, - - to_slave_awburst, - - to_slave_awlock, - - to_slave_awcache, - - to_slave_awprot, - - to_slave_awqos, - - to_slave_awregion, - - to_slave_awready, - - to_slave_wvalid, - - to_slave_wdata, - - to_slave_wstrb, - - to_slave_wlast, - - to_slave_wready, - - to_slave_bvalid, - to_slave_bid, - to_slave_bresp, - - to_slave_bready, - - to_slave_arvalid, - - to_slave_arid, - - to_slave_araddr, - - to_slave_arlen, - - to_slave_arsize, - - to_slave_arburst, - - to_slave_arlock, - - to_slave_arcache, - - to_slave_arprot, - - to_slave_arqos, - - to_slave_arregion, - - to_slave_arready, - - to_slave_rvalid, - to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast, - - to_slave_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method from_master_m_awvalid - input from_master_awvalid; - input [3 : 0] from_master_awid; - input [63 : 0] from_master_awaddr; - input [7 : 0] from_master_awlen; - input [2 : 0] from_master_awsize; - input [1 : 0] from_master_awburst; - input from_master_awlock; - input [3 : 0] from_master_awcache; - input [2 : 0] from_master_awprot; - input [3 : 0] from_master_awqos; - input [3 : 0] from_master_awregion; - - // value method from_master_m_awready - output from_master_awready; - - // action method from_master_m_wvalid - input from_master_wvalid; - input [63 : 0] from_master_wdata; - input [7 : 0] from_master_wstrb; - input from_master_wlast; - - // value method from_master_m_wready - output from_master_wready; - - // value method from_master_m_bvalid - output from_master_bvalid; - - // value method from_master_m_bid - output [3 : 0] from_master_bid; - - // value method from_master_m_bresp - output [1 : 0] from_master_bresp; - - // value method from_master_m_buser - - // action method from_master_m_bready - input from_master_bready; - - // action method from_master_m_arvalid - input from_master_arvalid; - input [3 : 0] from_master_arid; - input [63 : 0] from_master_araddr; - input [7 : 0] from_master_arlen; - input [2 : 0] from_master_arsize; - input [1 : 0] from_master_arburst; - input from_master_arlock; - input [3 : 0] from_master_arcache; - input [2 : 0] from_master_arprot; - input [3 : 0] from_master_arqos; - input [3 : 0] from_master_arregion; - - // value method from_master_m_arready - output from_master_arready; - - // value method from_master_m_rvalid - output from_master_rvalid; - - // value method from_master_m_rid - output [3 : 0] from_master_rid; - - // value method from_master_m_rdata - output [63 : 0] from_master_rdata; - - // value method from_master_m_rresp - output [1 : 0] from_master_rresp; - - // value method from_master_m_rlast - output from_master_rlast; - - // value method from_master_m_ruser - - // action method from_master_m_rready - input from_master_rready; - - // value method to_slave_m_awvalid - output to_slave_awvalid; - - // value method to_slave_m_awid - output [3 : 0] to_slave_awid; - - // value method to_slave_m_awaddr - output [63 : 0] to_slave_awaddr; - - // value method to_slave_m_awlen - output [7 : 0] to_slave_awlen; - - // value method to_slave_m_awsize - output [2 : 0] to_slave_awsize; - - // value method to_slave_m_awburst - output [1 : 0] to_slave_awburst; - - // value method to_slave_m_awlock - output to_slave_awlock; - - // value method to_slave_m_awcache - output [3 : 0] to_slave_awcache; - - // value method to_slave_m_awprot - output [2 : 0] to_slave_awprot; - - // value method to_slave_m_awqos - output [3 : 0] to_slave_awqos; - - // value method to_slave_m_awregion - output [3 : 0] to_slave_awregion; - - // value method to_slave_m_awuser - - // action method to_slave_m_awready - input to_slave_awready; - - // value method to_slave_m_wvalid - output to_slave_wvalid; - - // value method to_slave_m_wdata - output [63 : 0] to_slave_wdata; - - // value method to_slave_m_wstrb - output [7 : 0] to_slave_wstrb; - - // value method to_slave_m_wlast - output to_slave_wlast; - - // value method to_slave_m_wuser - - // action method to_slave_m_wready - input to_slave_wready; - - // action method to_slave_m_bvalid - input to_slave_bvalid; - input [3 : 0] to_slave_bid; - input [1 : 0] to_slave_bresp; - - // value method to_slave_m_bready - output to_slave_bready; - - // value method to_slave_m_arvalid - output to_slave_arvalid; - - // value method to_slave_m_arid - output [3 : 0] to_slave_arid; - - // value method to_slave_m_araddr - output [63 : 0] to_slave_araddr; - - // value method to_slave_m_arlen - output [7 : 0] to_slave_arlen; - - // value method to_slave_m_arsize - output [2 : 0] to_slave_arsize; - - // value method to_slave_m_arburst - output [1 : 0] to_slave_arburst; - - // value method to_slave_m_arlock - output to_slave_arlock; - - // value method to_slave_m_arcache - output [3 : 0] to_slave_arcache; - - // value method to_slave_m_arprot - output [2 : 0] to_slave_arprot; - - // value method to_slave_m_arqos - output [3 : 0] to_slave_arqos; - - // value method to_slave_m_arregion - output [3 : 0] to_slave_arregion; - - // value method to_slave_m_aruser - - // action method to_slave_m_arready - input to_slave_arready; - - // action method to_slave_m_rvalid - input to_slave_rvalid; - input [3 : 0] to_slave_rid; - input [63 : 0] to_slave_rdata; - input [1 : 0] to_slave_rresp; - input to_slave_rlast; - - // value method to_slave_m_rready - output to_slave_rready; - - // signals for module outputs - wire [63 : 0] from_master_rdata, - to_slave_araddr, - to_slave_awaddr, - to_slave_wdata; - wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb; - wire [3 : 0] from_master_bid, - from_master_rid, - to_slave_arcache, - to_slave_arid, - to_slave_arqos, - to_slave_arregion, - to_slave_awcache, - to_slave_awid, - to_slave_awqos, - to_slave_awregion; - wire [2 : 0] to_slave_arprot, - to_slave_arsize, - to_slave_awprot, - to_slave_awsize; - wire [1 : 0] from_master_bresp, - from_master_rresp, - to_slave_arburst, - to_slave_awburst; - wire RDY_reset, - from_master_arready, - from_master_awready, - from_master_bvalid, - from_master_rlast, - from_master_rvalid, - from_master_wready, - to_slave_arlock, - to_slave_arvalid, - to_slave_awlock, - to_slave_awvalid, - to_slave_bready, - to_slave_rready, - to_slave_wlast, - to_slave_wvalid; - - // register m_rg_ar_beat_count - reg [7 : 0] m_rg_ar_beat_count; - wire [7 : 0] m_rg_ar_beat_count$D_IN; - wire m_rg_ar_beat_count$EN; - - // register m_rg_b_beat_count - reg [7 : 0] m_rg_b_beat_count; - wire [7 : 0] m_rg_b_beat_count$D_IN; - wire m_rg_b_beat_count$EN; - - // register m_rg_b_resp - reg [1 : 0] m_rg_b_resp; - wire [1 : 0] m_rg_b_resp$D_IN; - wire m_rg_b_resp$EN; - - // register m_rg_r_beat_count - reg [7 : 0] m_rg_r_beat_count; - wire [7 : 0] m_rg_r_beat_count$D_IN; - wire m_rg_r_beat_count$EN; - - // register m_rg_reset - reg m_rg_reset; - wire m_rg_reset$D_IN, m_rg_reset$EN; - - // register m_rg_w_beat_count - reg [7 : 0] m_rg_w_beat_count; - wire [7 : 0] m_rg_w_beat_count$D_IN; - wire m_rg_w_beat_count$EN; - - // ports of submodule m_f_r_arlen - wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT; - wire m_f_r_arlen$CLR, - m_f_r_arlen$DEQ, - m_f_r_arlen$EMPTY_N, - m_f_r_arlen$ENQ, - m_f_r_arlen$FULL_N; - - // ports of submodule m_f_w_awlen - wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT; - wire m_f_w_awlen$CLR, - m_f_w_awlen$DEQ, - m_f_w_awlen$EMPTY_N, - m_f_w_awlen$ENQ, - m_f_w_awlen$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_addr - wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN, - m_xactor_from_master_f_rd_addr$D_OUT; - wire m_xactor_from_master_f_rd_addr$CLR, - m_xactor_from_master_f_rd_addr$DEQ, - m_xactor_from_master_f_rd_addr$EMPTY_N, - m_xactor_from_master_f_rd_addr$ENQ, - m_xactor_from_master_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_data - wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN, - m_xactor_from_master_f_rd_data$D_OUT; - wire m_xactor_from_master_f_rd_data$CLR, - m_xactor_from_master_f_rd_data$DEQ, - m_xactor_from_master_f_rd_data$EMPTY_N, - m_xactor_from_master_f_rd_data$ENQ, - m_xactor_from_master_f_rd_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_addr - wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN, - m_xactor_from_master_f_wr_addr$D_OUT; - wire m_xactor_from_master_f_wr_addr$CLR, - m_xactor_from_master_f_wr_addr$DEQ, - m_xactor_from_master_f_wr_addr$EMPTY_N, - m_xactor_from_master_f_wr_addr$ENQ, - m_xactor_from_master_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_data - wire [72 : 0] m_xactor_from_master_f_wr_data$D_IN, - m_xactor_from_master_f_wr_data$D_OUT; - wire m_xactor_from_master_f_wr_data$CLR, - m_xactor_from_master_f_wr_data$DEQ, - m_xactor_from_master_f_wr_data$EMPTY_N, - m_xactor_from_master_f_wr_data$ENQ, - m_xactor_from_master_f_wr_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_resp - wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN, - m_xactor_from_master_f_wr_resp$D_OUT; - wire m_xactor_from_master_f_wr_resp$CLR, - m_xactor_from_master_f_wr_resp$DEQ, - m_xactor_from_master_f_wr_resp$EMPTY_N, - m_xactor_from_master_f_wr_resp$ENQ, - m_xactor_from_master_f_wr_resp$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_addr - wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN, - m_xactor_to_slave_f_rd_addr$D_OUT; - wire m_xactor_to_slave_f_rd_addr$CLR, - m_xactor_to_slave_f_rd_addr$DEQ, - m_xactor_to_slave_f_rd_addr$EMPTY_N, - m_xactor_to_slave_f_rd_addr$ENQ, - m_xactor_to_slave_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_data - wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN, - m_xactor_to_slave_f_rd_data$D_OUT; - wire m_xactor_to_slave_f_rd_data$CLR, - m_xactor_to_slave_f_rd_data$DEQ, - m_xactor_to_slave_f_rd_data$EMPTY_N, - m_xactor_to_slave_f_rd_data$ENQ, - m_xactor_to_slave_f_rd_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_addr - wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN, - m_xactor_to_slave_f_wr_addr$D_OUT; - wire m_xactor_to_slave_f_wr_addr$CLR, - m_xactor_to_slave_f_wr_addr$DEQ, - m_xactor_to_slave_f_wr_addr$EMPTY_N, - m_xactor_to_slave_f_wr_addr$ENQ, - m_xactor_to_slave_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_data - wire [72 : 0] m_xactor_to_slave_f_wr_data$D_IN, - m_xactor_to_slave_f_wr_data$D_OUT; - wire m_xactor_to_slave_f_wr_data$CLR, - m_xactor_to_slave_f_wr_data$DEQ, - m_xactor_to_slave_f_wr_data$EMPTY_N, - m_xactor_to_slave_f_wr_data$ENQ, - m_xactor_to_slave_f_wr_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_resp - wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN, - m_xactor_to_slave_f_wr_resp$D_OUT; - wire m_xactor_to_slave_f_wr_resp$CLR, - m_xactor_to_slave_f_wr_resp$DEQ, - m_xactor_to_slave_f_wr_resp$EMPTY_N, - m_xactor_to_slave_f_wr_resp$ENQ, - m_xactor_to_slave_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave, - CAN_FIRE_from_master_m_arvalid, - CAN_FIRE_from_master_m_awvalid, - CAN_FIRE_from_master_m_bready, - CAN_FIRE_from_master_m_rready, - CAN_FIRE_from_master_m_wvalid, - CAN_FIRE_reset, - CAN_FIRE_to_slave_m_arready, - CAN_FIRE_to_slave_m_awready, - CAN_FIRE_to_slave_m_bvalid, - CAN_FIRE_to_slave_m_rvalid, - CAN_FIRE_to_slave_m_wready, - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave, - WILL_FIRE_from_master_m_arvalid, - WILL_FIRE_from_master_m_awvalid, - WILL_FIRE_from_master_m_bready, - WILL_FIRE_from_master_m_rready, - WILL_FIRE_from_master_m_wvalid, - WILL_FIRE_reset, - WILL_FIRE_to_slave_m_arready, - WILL_FIRE_to_slave_m_awready, - WILL_FIRE_to_slave_m_bvalid, - WILL_FIRE_to_slave_m_rvalid, - WILL_FIRE_to_slave_m_wready; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2, - MUX_m_rg_b_beat_count$write_1__VAL_2, - MUX_m_rg_r_beat_count$write_1__VAL_2, - MUX_m_rg_w_beat_count$write_1__VAL_2; - wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2; - wire MUX_m_rg_b_resp$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2422; - reg [31 : 0] v__h1446; - reg [31 : 0] v__h1440; - reg [31 : 0] v__h2416; - // synopsys translate_on - - // remaining internal signals - wire [63 : 0] a_out_araddr__h2934, - a_out_awaddr__h1951, - addr___1__h2036, - addr___1__h3019; - wire [7 : 0] x__h2297, x__h2788, x__h3180, x__h3378; - wire m_rg_ar_beat_count_2_ULT_m_xactor_from_master__ETC___d94, - m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50, - m_rg_r_beat_count_03_ULT_m_f_r_arlen_first__04___d105, - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35; - - // action method reset - assign RDY_reset = !m_rg_reset ; - assign CAN_FIRE_reset = !m_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method from_master_m_awvalid - assign CAN_FIRE_from_master_m_awvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_awvalid = 1'd1 ; - - // value method from_master_m_awready - assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ; - - // action method from_master_m_wvalid - assign CAN_FIRE_from_master_m_wvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_wvalid = 1'd1 ; - - // value method from_master_m_wready - assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ; - - // value method from_master_m_bvalid - assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ; - - // value method from_master_m_bid - assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ; - - // value method from_master_m_bresp - assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ; - - // action method from_master_m_bready - assign CAN_FIRE_from_master_m_bready = 1'd1 ; - assign WILL_FIRE_from_master_m_bready = 1'd1 ; - - // action method from_master_m_arvalid - assign CAN_FIRE_from_master_m_arvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_arvalid = 1'd1 ; - - // value method from_master_m_arready - assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ; - - // value method from_master_m_rvalid - assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ; - - // value method from_master_m_rid - assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ; - - // value method from_master_m_rdata - assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ; - - // value method from_master_m_rresp - assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ; - - // value method from_master_m_rlast - assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ; - - // action method from_master_m_rready - assign CAN_FIRE_from_master_m_rready = 1'd1 ; - assign WILL_FIRE_from_master_m_rready = 1'd1 ; - - // value method to_slave_m_awvalid - assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ; - - // value method to_slave_m_awid - assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ; - - // value method to_slave_m_awaddr - assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ; - - // value method to_slave_m_awlen - assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ; - - // value method to_slave_m_awsize - assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ; - - // value method to_slave_m_awburst - assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ; - - // value method to_slave_m_awlock - assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ; - - // value method to_slave_m_awcache - assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ; - - // value method to_slave_m_awprot - assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ; - - // value method to_slave_m_awqos - assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ; - - // value method to_slave_m_awregion - assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ; - - // action method to_slave_m_awready - assign CAN_FIRE_to_slave_m_awready = 1'd1 ; - assign WILL_FIRE_to_slave_m_awready = 1'd1 ; - - // value method to_slave_m_wvalid - assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ; - - // value method to_slave_m_wdata - assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ; - - // value method to_slave_m_wstrb - assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ; - - // value method to_slave_m_wlast - assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ; - - // action method to_slave_m_wready - assign CAN_FIRE_to_slave_m_wready = 1'd1 ; - assign WILL_FIRE_to_slave_m_wready = 1'd1 ; - - // action method to_slave_m_bvalid - assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ; - - // value method to_slave_m_bready - assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ; - - // value method to_slave_m_arvalid - assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ; - - // value method to_slave_m_arid - assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ; - - // value method to_slave_m_araddr - assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ; - - // value method to_slave_m_arlen - assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ; - - // value method to_slave_m_arsize - assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ; - - // value method to_slave_m_arburst - assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ; - - // value method to_slave_m_arlock - assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ; - - // value method to_slave_m_arcache - assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ; - - // value method to_slave_m_arprot - assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ; - - // value method to_slave_m_arqos - assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ; - - // value method to_slave_m_arregion - assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ; - - // action method to_slave_m_arready - assign CAN_FIRE_to_slave_m_arready = 1'd1 ; - assign WILL_FIRE_to_slave_m_arready = 1'd1 ; - - // action method to_slave_m_rvalid - assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ; - - // value method to_slave_m_rready - assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ; - - // submodule m_f_r_arlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_r_arlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_r_arlen$D_IN), - .ENQ(m_f_r_arlen$ENQ), - .DEQ(m_f_r_arlen$DEQ), - .CLR(m_f_r_arlen$CLR), - .D_OUT(m_f_r_arlen$D_OUT), - .FULL_N(m_f_r_arlen$FULL_N), - .EMPTY_N(m_f_r_arlen$EMPTY_N)); - - // submodule m_f_w_awlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_w_awlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_w_awlen$D_IN), - .ENQ(m_f_w_awlen$ENQ), - .DEQ(m_f_w_awlen$DEQ), - .CLR(m_f_w_awlen$CLR), - .D_OUT(m_f_w_awlen$D_OUT), - .FULL_N(m_f_w_awlen$FULL_N), - .EMPTY_N(m_f_w_awlen$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_addr$D_IN), - .ENQ(m_xactor_from_master_f_rd_addr$ENQ), - .DEQ(m_xactor_from_master_f_rd_addr$DEQ), - .CLR(m_xactor_from_master_f_rd_addr$CLR), - .D_OUT(m_xactor_from_master_f_rd_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_data$D_IN), - .ENQ(m_xactor_from_master_f_rd_data$ENQ), - .DEQ(m_xactor_from_master_f_rd_data$DEQ), - .CLR(m_xactor_from_master_f_rd_data$CLR), - .D_OUT(m_xactor_from_master_f_rd_data$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_addr$D_IN), - .ENQ(m_xactor_from_master_f_wr_addr$ENQ), - .DEQ(m_xactor_from_master_f_wr_addr$DEQ), - .CLR(m_xactor_from_master_f_wr_addr$CLR), - .D_OUT(m_xactor_from_master_f_wr_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_data$D_IN), - .ENQ(m_xactor_from_master_f_wr_data$ENQ), - .DEQ(m_xactor_from_master_f_wr_data$DEQ), - .CLR(m_xactor_from_master_f_wr_data$CLR), - .D_OUT(m_xactor_from_master_f_wr_data$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_resp$D_IN), - .ENQ(m_xactor_from_master_f_wr_resp$ENQ), - .DEQ(m_xactor_from_master_f_wr_resp$DEQ), - .CLR(m_xactor_from_master_f_wr_resp$CLR), - .D_OUT(m_xactor_from_master_f_wr_resp$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_addr$D_IN), - .ENQ(m_xactor_to_slave_f_rd_addr$ENQ), - .DEQ(m_xactor_to_slave_f_rd_addr$DEQ), - .CLR(m_xactor_to_slave_f_rd_addr$CLR), - .D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_data$D_IN), - .ENQ(m_xactor_to_slave_f_rd_data$ENQ), - .DEQ(m_xactor_to_slave_f_rd_data$DEQ), - .CLR(m_xactor_to_slave_f_rd_data$CLR), - .D_OUT(m_xactor_to_slave_f_rd_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_addr$D_IN), - .ENQ(m_xactor_to_slave_f_wr_addr$ENQ), - .DEQ(m_xactor_to_slave_f_wr_addr$DEQ), - .CLR(m_xactor_to_slave_f_wr_addr$CLR), - .D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_data$D_IN), - .ENQ(m_xactor_to_slave_f_wr_data$ENQ), - .DEQ(m_xactor_to_slave_f_wr_data$DEQ), - .CLR(m_xactor_to_slave_f_wr_data$CLR), - .D_OUT(m_xactor_to_slave_f_wr_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_resp$D_IN), - .ENQ(m_xactor_to_slave_f_wr_resp$ENQ), - .DEQ(m_xactor_to_slave_f_wr_resp$DEQ), - .CLR(m_xactor_to_slave_f_wr_resp$CLR), - .D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave = - m_xactor_to_slave_f_wr_addr$FULL_N && - m_xactor_from_master_f_wr_addr$EMPTY_N && - m_xactor_to_slave_f_wr_data$FULL_N && - m_xactor_from_master_f_wr_data$EMPTY_N && - (m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - - // rule RL_m_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master = - m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N && - (m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 || - m_xactor_from_master_f_wr_resp$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - - // rule RL_m_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave = - m_xactor_to_slave_f_rd_addr$FULL_N && - m_xactor_from_master_f_rd_addr$EMPTY_N && - (m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - - // rule RL_m_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master = - m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N && - m_xactor_from_master_f_rd_data$FULL_N ; - assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ; - assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_b_resp$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - (m_rg_b_resp == 2'b0 && - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 || - !m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50) ; - assign MUX_m_rg_ar_beat_count$write_1__VAL_2 = - m_rg_ar_beat_count_2_ULT_m_xactor_from_master__ETC___d94 ? - x__h3180 : - 8'd0 ; - assign MUX_m_rg_b_beat_count$write_1__VAL_2 = - m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 ? - x__h2788 : - 8'd0 ; - assign MUX_m_rg_b_resp$write_1__VAL_2 = - m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - 2'b0 ; - assign MUX_m_rg_r_beat_count$write_1__VAL_2 = - m_rg_r_beat_count_03_ULT_m_f_r_arlen_first__04___d105 ? - x__h3378 : - 8'd0 ; - assign MUX_m_rg_w_beat_count$write_1__VAL_2 = - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ? - x__h2297 : - 8'd0 ; - - // register m_rg_ar_beat_count - assign m_rg_ar_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ; - assign m_rg_ar_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ; - - // register m_rg_b_beat_count - assign m_rg_b_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ; - assign m_rg_b_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ; - - // register m_rg_b_resp - assign m_rg_b_resp$D_IN = - m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ; - assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ; - - // register m_rg_r_beat_count - assign m_rg_r_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ; - assign m_rg_r_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ; - - // register m_rg_reset - assign m_rg_reset$D_IN = !m_rg_reset ; - assign m_rg_reset$EN = m_rg_reset || EN_reset ; - - // register m_rg_w_beat_count - assign m_rg_w_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ; - assign m_rg_w_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ; - - // submodule m_f_r_arlen - assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_f_r_arlen$ENQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - m_rg_ar_beat_count == 8'd0 ; - assign m_f_r_arlen$DEQ = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master && - !m_rg_r_beat_count_03_ULT_m_f_r_arlen_first__04___d105 ; - assign m_f_r_arlen$CLR = m_rg_reset ; - - // submodule m_f_w_awlen - assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign m_f_w_awlen$ENQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - m_rg_w_beat_count == 8'd0 ; - assign m_f_w_awlen$DEQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 ; - assign m_f_w_awlen$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_addr - assign m_xactor_from_master_f_rd_addr$D_IN = - { from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion } ; - assign m_xactor_from_master_f_rd_addr$ENQ = - from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ; - assign m_xactor_from_master_f_rd_addr$DEQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - !m_rg_ar_beat_count_2_ULT_m_xactor_from_master__ETC___d94 ; - assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_data - assign m_xactor_from_master_f_rd_data$D_IN = - { m_xactor_to_slave_f_rd_data$D_OUT[70:1], - !m_rg_r_beat_count_03_ULT_m_f_r_arlen_first__04___d105 } ; - assign m_xactor_from_master_f_rd_data$ENQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_from_master_f_rd_data$DEQ = - from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ; - assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_addr - assign m_xactor_from_master_f_wr_addr$D_IN = - { from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion } ; - assign m_xactor_from_master_f_wr_addr$ENQ = - from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ; - assign m_xactor_from_master_f_wr_addr$DEQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ; - assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_data - assign m_xactor_from_master_f_wr_data$D_IN = - { from_master_wdata, from_master_wstrb, from_master_wlast } ; - assign m_xactor_from_master_f_wr_data$ENQ = - from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ; - assign m_xactor_from_master_f_wr_data$DEQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_resp - assign m_xactor_from_master_f_wr_resp$D_IN = - { m_xactor_to_slave_f_wr_resp$D_OUT[5:2], - (m_rg_b_resp == 2'b0) ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - m_rg_b_resp } ; - assign m_xactor_from_master_f_wr_resp$ENQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 ; - assign m_xactor_from_master_f_wr_resp$DEQ = - from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ; - assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_addr - assign m_xactor_to_slave_f_rd_addr$D_IN = - { m_xactor_from_master_f_rd_addr$D_OUT[96:93], - a_out_araddr__h2934, - 8'd0, - m_xactor_from_master_f_rd_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_rd_addr$ENQ = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - assign m_xactor_to_slave_f_rd_addr$DEQ = - m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ; - assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_data - assign m_xactor_to_slave_f_rd_data$D_IN = - { to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast } ; - assign m_xactor_to_slave_f_rd_data$ENQ = - to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ; - assign m_xactor_to_slave_f_rd_data$DEQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_addr - assign m_xactor_to_slave_f_wr_addr$D_IN = - { m_xactor_from_master_f_wr_addr$D_OUT[96:93], - a_out_awaddr__h1951, - 8'd0, - m_xactor_from_master_f_wr_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_wr_addr$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_addr$DEQ = - m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ; - assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_data - assign m_xactor_to_slave_f_wr_data$D_IN = - { m_xactor_from_master_f_wr_data$D_OUT[72:1], 1'd1 } ; - assign m_xactor_to_slave_f_wr_data$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_data$DEQ = - m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ; - assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_resp - assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ; - assign m_xactor_to_slave_f_wr_resp$ENQ = - to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ; - assign m_xactor_to_slave_f_wr_resp$DEQ = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ; - - // remaining internal signals - assign a_out_araddr__h2934 = - (m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h3019 : - m_xactor_from_master_f_rd_addr$D_OUT[92:29] ; - assign a_out_awaddr__h1951 = - (m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h2036 : - m_xactor_from_master_f_wr_addr$D_OUT[92:29] ; - assign addr___1__h2036 = - m_xactor_from_master_f_wr_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_w_beat_count } << - m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ; - assign addr___1__h3019 = - m_xactor_from_master_f_rd_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_ar_beat_count } << - m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ; - assign m_rg_ar_beat_count_2_ULT_m_xactor_from_master__ETC___d94 = - m_rg_ar_beat_count < - m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_rg_b_beat_count_8_ULT_m_f_w_awlen_first__9___d50 = - m_rg_b_beat_count < m_f_w_awlen$D_OUT ; - assign m_rg_r_beat_count_03_ULT_m_f_r_arlen_first__04___d105 = - m_rg_r_beat_count < m_f_r_arlen$D_OUT ; - assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 = - m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign x__h2297 = m_rg_w_beat_count + 8'd1 ; - assign x__h2788 = m_rg_b_beat_count + 8'd1 ; - assign x__h3180 = m_rg_ar_beat_count + 8'd1 ; - assign x__h3378 = m_rg_r_beat_count + 8'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0; - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (m_rg_ar_beat_count$EN) - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN; - if (m_rg_b_beat_count$EN) - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN; - if (m_rg_b_resp$EN) - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN; - if (m_rg_r_beat_count$EN) - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN; - if (m_rg_reset$EN) - m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN; - if (m_rg_w_beat_count$EN) - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_ar_beat_count = 8'hAA; - m_rg_b_beat_count = 8'hAA; - m_rg_b_resp = 2'h2; - m_rg_r_beat_count = 8'hAA; - m_rg_reset = 1'h0; - m_rg_w_beat_count = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - begin - v__h2422 = $stime; - #0; - end - v__h2416 = v__h2422 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", - v__h2416); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display(" WLAST not set on last data beat (awlen = %0d)", - m_xactor_from_master_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) - begin - v__h1446 = $stime; - #0; - end - v__h1440 = v__h1446 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) $display("%0d: %m::AXI4_Deburster.rl_reset", v__h1440); - end - // synopsys translate_on -endmodule // mkAXI4_Deburster_A - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v deleted file mode 100644 index 7b137037..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v +++ /dev/null @@ -1,2154 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkBoot_ROM(CLK, - RST_N, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready); - input CLK; - input RST_N; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_set_addr_map, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_module_ready - reg rg_module_ready; - wire rg_module_ready$D_IN, rg_module_ready$EN; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [72 : 0] slave_xactor_f_wr_data$D_IN; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h808; - reg [31 : 0] v__h8925; - reg [31 : 0] v__h9218; - reg [31 : 0] v__h9328; - reg [31 : 0] v__h802; - reg [31 : 0] v__h8919; - reg [31 : 0] v__h9212; - reg [31 : 0] v__h9322; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] data64__h987; - reg [31 : 0] CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2; - wire [63 : 0] byte_addr__h705, rdata__h924; - wire [1 : 0] rdr_rresp__h957; - wire NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18, - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_module_ready - assign rg_module_ready$D_IN = 1'd1 ; - assign rg_module_ready$EN = EN_set_addr_map ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h924, - rdr_rresp__h957, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 ? - 2'b10 : - 2'b0 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = 1'b0 ; - - // remaining internal signals - assign NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 = - slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] || - slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ; - assign NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 = - slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] || - slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ; - assign byte_addr__h705 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign rdata__h924 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 64'd0 : - data64__h987 ; - assign rdr_rresp__h957 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 2'b10 : - 2'b0 ; - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16, - 64'd24, - 64'd56, - 64'd72, - 64'd80, - 64'd88, - 64'd200, - 64'd232, - 64'd312, - 64'd424, - 64'd448, - 64'd600, - 64'd728, - 64'd1136, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = 32'h0; - 64'd32: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h54040000; - 64'd40: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h88030000; - 64'd48: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h11000000; - 64'd64: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h50030000; - 64'd96, - 64'd112, - 64'd208, - 64'd224, - 64'd240, - 64'd432, - 64'd488, - 64'd872, - 64'd888: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h04000000; - 64'd104, 64'd120, 64'd504, 64'd792, 64'd920: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h02000000; - 64'd128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h16000000; - 64'd136: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h62626375; - 64'd144: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656B6970; - 64'd152: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65642D65; - 64'd160, - 64'd264, - 64'd280, - 64'd296, - 64'd336, - 64'd360, - 64'd384, - 64'd456, - 64'd552, - 64'd592, - 64'd608, - 64'd624, - 64'd672, - 64'd704, - 64'd760, - 64'd816, - 64'd840, - 64'd880: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h03000000; - 64'd168: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h26000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h732C7261; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7261622D; - 64'd192, - 64'd216, - 64'd400, - 64'd440, - 64'd496, - 64'd512, - 64'd584, - 64'd744, - 64'd752, - 64'd912: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h01000000; - 64'd248, 64'd896: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h80969800; - 64'd256: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40757063; - 64'd272: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h3F000000; - 64'd288, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4B000000; - 64'd304: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4F000000; - 64'd320: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h06000000; - 64'd328: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h63736972; - 64'd344: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h56000000; - 64'd352: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h75616D69; - 64'd368: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h60000000; - 64'd376: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h76732C76; - 64'd392: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69000000; - 64'd408: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70757272; - 64'd416: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F72746E; - 64'd464, 64'd632, 64'd712, 64'd824: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h1B000000; - 64'd472: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70632C76; - 64'd480: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00006374; - 64'd520: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h38407972; - 64'd528: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00303030; - 64'd536: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h07000000; - 64'd544: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D656D; - 64'd568: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000080; - 64'd576: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000010; - 64'd616: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h0F000000; - 64'd656: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69730063; - 64'd664: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7375622D; - 64'd680: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hA7000000; - 64'd688: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E696C63; - 64'd696, 64'd808: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h30303030; - 64'd720: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C632C76; - 64'd736: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h10000000; - 64'd776: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000002; - 64'd784: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000C00; - 64'd800: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h74726175; - 64'd832: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61303535; - 64'd856: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h000000C0; - 64'd864: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40000000; - 64'd904: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h08000000; - 64'd928: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h09000000; - 64'd936: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73736572; - 64'd944: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h2300736C; - 64'd952: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C65632D; - 64'd960: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61706D6F; - 64'd968: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D0065; - 64'd976: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656D6974; - 64'd984: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6572662D; - 64'd992: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h64007963; - 64'd1000: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79745F65; - 64'd1008: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73006765; - 64'd1016: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69720073; - 64'd1024: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00617369; - 64'd1032: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65707974; - 64'd1040: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h662D6B63; - 64'd1048: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79636E65; - 64'd1056, 64'd1072: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h72726574; - 64'd1064: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C6C6563; - 64'd1080: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h746E6F63; - 64'd1088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70007265; - 64'd1096: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7200656C; - 64'd1104: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E690073; - 64'd1112: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73747075; - 64'd1120: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65646E65; - 64'd1128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h68732D67; - default: CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00028067; - 64'd24: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80000000; - 64'd32: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hEDFE0DD0; - 64'd40: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h38000000; - 64'd48: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h28000000; - 64'd56, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h10000000; - 64'd64: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hCC000000; - 64'd72, - 64'd80, - 64'd104, - 64'd216, - 64'd296, - 64'd568, - 64'd576, - 64'd672, - 64'd680, - 64'd776, - 64'd784, - 64'd840, - 64'd856, - 64'd864, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = 32'h0; - 64'd88, 64'd256, 64'd688, 64'd800: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h01000000; - 64'd96, - 64'd112, - 64'd128, - 64'd208, - 64'd224, - 64'd240, - 64'd320, - 64'd432, - 64'd448, - 64'd488, - 64'd536, - 64'd736, - 64'd752, - 64'd872, - 64'd888, - 64'd904: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h03000000; - 64'd120, 64'd232, 64'd464: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0F000000; - 64'd136, 64'd328: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h1B000000; - 64'd144: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h732C7261; - 64'd152: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7261622D; - 64'd160, 64'd336: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000076; - 64'd168: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h12000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h62626375; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656B6970; - 64'd192: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000065; - 64'd200: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h73757063; - 64'd248: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C000000; - 64'd264, 64'd704, 64'd816: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000030; - 64'd272, 64'd288, 64'd392, 64'd600, 64'd616: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h04000000; - 64'd280: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00757063; - 64'd304: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h05000000; - 64'd312: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79616B6F; - 64'd344: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0A000000; - 64'd352: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h32337672; - 64'd360: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000073; - 64'd368, 64'd920: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0B000000; - 64'd376, 64'd472, 64'd720: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63736972; - 64'd384: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00003233; - 64'd400: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80969800; - 64'd408: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65746E69; - 64'd416: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F632D74; - 64'd424: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72656C6C; - 64'd440: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79000000; - 64'd456: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h8A000000; - 64'd480: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692D75; - 64'd496: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h9F000000; - 64'd504, 64'd512, 64'd584, 64'd608, 64'd624, 64'd792, 64'd928: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h02000000; - 64'd520: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6D656D; - 64'd528: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30303030; - 64'd544: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3F000000; - 64'd552: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00007972; - 64'd592: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00636F73; - 64'd632: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h21000000; - 64'd656: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F732D65; - 64'd664: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656C706D; - 64'd696: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30324074; - 64'd712: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0D000000; - 64'd728: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30746E69; - 64'd744, 64'd912: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAE000000; - 64'd760: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h07000000; - 64'd808: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30306340; - 64'd824: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h09000000; - 64'd832: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3631736E; - 64'd880: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hC2000000; - 64'd896: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h69000000; - 64'd936: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h64646123; - 64'd944: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C65632D; - 64'd952: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h657A6973; - 64'd960: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6300736C; - 64'd968: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C626974; - 64'd976: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h006C6564; - 64'd984: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65736162; - 64'd992: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E657571; - 64'd1000: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63697665; - 64'd1008: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72006570; - 64'd1016: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75746174; - 64'd1024: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C766373; - 64'd1032: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D756D6D; - 64'd1040: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6C6300; - 64'd1048: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75716572; - 64'd1056: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692300; - 64'd1064, 64'd1080: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D747075; - 64'd1072: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E690073; - 64'd1088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C6C6F72; - 64'd1096: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h646E6168; - 64'd1104: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65676E61; - 64'd1112: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72726574; - 64'd1120: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7478652D; - 64'd1128: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65720064; - 64'd1136: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00746669; - default: CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705 or - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 or - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2) - begin - case (byte_addr__h705) - 64'd0: data64__h987 = 64'h0202859300000297; - 64'd8: data64__h987 = 64'h0182A283F1402573; - default: data64__h987 = - { CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_module_ready$EN) - rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_module_ready = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - begin - v__h808 = $stime; - #0; - end - v__h802 = v__h808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", - v__h802); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - begin - v__h8925 = $stime; - #0; - end - v__h8919 = v__h8925 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", - v__h8919); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h9218 = $stime; - #0; - end - v__h9212 = v__h9218 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9212, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h9328 = $stime; - #0; - end - v__h9322 = v__h9328 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9322, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkBoot_ROM - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCPU.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCPU.v deleted file mode 100644 index ea51bddb..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCPU.v +++ /dev/null @@ -1,6021 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// hart0_server_reset_response_get O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_set_verbosity O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// hart0_server_reset_request_put I 1 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// nmi_req_set_not_clear I 1 -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// EN_hart0_server_reset_request_put I 1 -// EN_set_verbosity I 1 -// EN_hart0_server_reset_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> imem_master_rready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> dmem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCPU(CLK, - RST_N, - - hart0_server_reset_request_put, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - nmi_req_set_not_clear, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity); - input CLK; - input RST_N; - - // action method hart0_server_reset_request_put - input hart0_server_reset_request_put; - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // actionvalue method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, - RDY_set_verbosity, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - hart0_server_reset_response_get, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid; - - // register cfg_logdelay - reg [63 : 0] cfg_logdelay; - wire [63 : 0] cfg_logdelay$D_IN; - wire cfg_logdelay$EN; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register imem_rg_f3 - reg [2 : 0] imem_rg_f3; - wire [2 : 0] imem_rg_f3$D_IN; - wire imem_rg_f3$EN; - - // register imem_rg_instr_15_0 - reg [15 : 0] imem_rg_instr_15_0; - wire [15 : 0] imem_rg_instr_15_0$D_IN; - wire imem_rg_instr_15_0$EN; - - // register imem_rg_mstatus_MXR - reg imem_rg_mstatus_MXR; - wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN; - - // register imem_rg_pc - reg [31 : 0] imem_rg_pc; - reg [31 : 0] imem_rg_pc$D_IN; - wire imem_rg_pc$EN; - - // register imem_rg_priv - reg [1 : 0] imem_rg_priv; - wire [1 : 0] imem_rg_priv$D_IN; - wire imem_rg_priv$EN; - - // register imem_rg_satp - reg [31 : 0] imem_rg_satp; - wire [31 : 0] imem_rg_satp$D_IN; - wire imem_rg_satp$EN; - - // register imem_rg_sstatus_SUM - reg imem_rg_sstatus_SUM; - wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN; - - // register imem_rg_tval - reg [31 : 0] imem_rg_tval; - reg [31 : 0] imem_rg_tval$D_IN; - wire imem_rg_tval$EN; - - // register rg_cur_priv - reg [1 : 0] rg_cur_priv; - reg [1 : 0] rg_cur_priv$D_IN; - wire rg_cur_priv$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_next_pc - reg [31 : 0] rg_next_pc; - reg [31 : 0] rg_next_pc$D_IN; - wire rg_next_pc$EN; - - // register rg_run_on_reset - reg rg_run_on_reset; - wire rg_run_on_reset$D_IN, rg_run_on_reset$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_start_CPI_cycles - reg [63 : 0] rg_start_CPI_cycles; - wire [63 : 0] rg_start_CPI_cycles$D_IN; - wire rg_start_CPI_cycles$EN; - - // register rg_start_CPI_instrs - reg [63 : 0] rg_start_CPI_instrs; - wire [63 : 0] rg_start_CPI_instrs$D_IN; - wire rg_start_CPI_instrs$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register stage1_rg_full - reg stage1_rg_full; - reg stage1_rg_full$D_IN; - wire stage1_rg_full$EN; - - // register stage2_rg_full - reg stage2_rg_full; - reg stage2_rg_full$D_IN; - wire stage2_rg_full$EN; - - // register stage2_rg_resetting - reg stage2_rg_resetting; - wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN; - - // register stage2_rg_stage2 - reg [169 : 0] stage2_rg_stage2; - wire [169 : 0] stage2_rg_stage2$D_IN; - wire stage2_rg_stage2$EN; - - // register stage3_rg_full - reg stage3_rg_full; - reg stage3_rg_full$D_IN; - wire stage3_rg_full$EN; - - // register stage3_rg_stage3 - reg [103 : 0] stage3_rg_stage3; - wire [103 : 0] stage3_rg_stage3$D_IN; - wire stage3_rg_stage3$EN; - - // ports of submodule csr_regfile - reg [31 : 0] csr_regfile$csr_trap_actions_xtval; - reg [3 : 0] csr_regfile$csr_trap_actions_exc_code; - reg [1 : 0] csr_regfile$csr_ret_actions_from_priv; - wire [97 : 0] csr_regfile$csr_trap_actions; - wire [65 : 0] csr_regfile$csr_ret_actions; - wire [63 : 0] csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret; - wire [32 : 0] csr_regfile$read_csr; - wire [31 : 0] csr_regfile$csr_trap_actions_pc, - csr_regfile$mav_csr_write_word, - csr_regfile$read_mstatus, - csr_regfile$read_satp; - wire [27 : 0] csr_regfile$read_misa; - wire [11 : 0] csr_regfile$access_permitted_1_csr_addr, - csr_regfile$access_permitted_2_csr_addr, - csr_regfile$csr_counter_read_fault_csr_addr, - csr_regfile$mav_csr_write_csr_addr, - csr_regfile$mav_read_csr_csr_addr, - csr_regfile$read_csr_csr_addr, - csr_regfile$read_csr_port2_csr_addr; - wire [4 : 0] csr_regfile$interrupt_pending; - wire [1 : 0] csr_regfile$access_permitted_1_priv, - csr_regfile$access_permitted_2_priv, - csr_regfile$csr_counter_read_fault_priv, - csr_regfile$csr_trap_actions_from_priv, - csr_regfile$interrupt_pending_cur_priv; - wire csr_regfile$EN_csr_minstret_incr, - csr_regfile$EN_csr_ret_actions, - csr_regfile$EN_csr_trap_actions, - csr_regfile$EN_debug, - csr_regfile$EN_mav_csr_write, - csr_regfile$EN_mav_read_csr, - csr_regfile$EN_server_reset_request_put, - csr_regfile$EN_server_reset_response_get, - csr_regfile$RDY_server_reset_request_put, - csr_regfile$RDY_server_reset_response_get, - csr_regfile$access_permitted_1, - csr_regfile$access_permitted_1_read_not_write, - csr_regfile$access_permitted_2, - csr_regfile$access_permitted_2_read_not_write, - csr_regfile$csr_trap_actions_interrupt, - csr_regfile$csr_trap_actions_nmi, - csr_regfile$m_external_interrupt_req_set_not_clear, - csr_regfile$nmi_pending, - csr_regfile$nmi_req_set_not_clear, - csr_regfile$s_external_interrupt_req_set_not_clear, - csr_regfile$software_interrupt_req_set_not_clear, - csr_regfile$timer_interrupt_req_set_not_clear, - csr_regfile$wfi_resume; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule gpr_regfile - wire [31 : 0] gpr_regfile$read_rs1, - gpr_regfile$read_rs2, - gpr_regfile$write_rd_rd_val; - wire [4 : 0] gpr_regfile$read_rs1_port2_rs1, - gpr_regfile$read_rs1_rs1, - gpr_regfile$read_rs2_rs2, - gpr_regfile$write_rd_rd; - wire gpr_regfile$EN_server_reset_request_put, - gpr_regfile$EN_server_reset_response_get, - gpr_regfile$EN_write_rd, - gpr_regfile$RDY_server_reset_request_put, - gpr_regfile$RDY_server_reset_response_get; - - // ports of submodule near_mem - reg [31 : 0] near_mem$imem_req_addr; - reg [1 : 0] near_mem$dmem_req_op; - reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM; - wire [63 : 0] near_mem$dmem_master_araddr, - near_mem$dmem_master_awaddr, - near_mem$dmem_master_rdata, - near_mem$dmem_master_wdata, - near_mem$dmem_req_store_value, - near_mem$dmem_word64, - near_mem$imem_master_araddr, - near_mem$imem_master_awaddr, - near_mem$imem_master_rdata, - near_mem$imem_master_wdata; - wire [31 : 0] near_mem$dmem_req_addr, - near_mem$dmem_req_satp, - near_mem$imem_instr, - near_mem$imem_pc, - near_mem$imem_req_satp; - wire [7 : 0] near_mem$dmem_master_arlen, - near_mem$dmem_master_awlen, - near_mem$dmem_master_wstrb, - near_mem$imem_master_arlen, - near_mem$imem_master_awlen, - near_mem$imem_master_wstrb, - near_mem$server_fence_request_put; - wire [6 : 0] near_mem$dmem_req_amo_funct7; - wire [3 : 0] near_mem$dmem_exc_code, - near_mem$dmem_master_arcache, - near_mem$dmem_master_arid, - near_mem$dmem_master_arqos, - near_mem$dmem_master_arregion, - near_mem$dmem_master_awcache, - near_mem$dmem_master_awid, - near_mem$dmem_master_awqos, - near_mem$dmem_master_awregion, - near_mem$dmem_master_bid, - near_mem$dmem_master_rid, - near_mem$imem_exc_code, - near_mem$imem_master_arcache, - near_mem$imem_master_arid, - near_mem$imem_master_arqos, - near_mem$imem_master_arregion, - near_mem$imem_master_awcache, - near_mem$imem_master_awid, - near_mem$imem_master_awqos, - near_mem$imem_master_awregion, - near_mem$imem_master_bid, - near_mem$imem_master_rid; - wire [2 : 0] near_mem$dmem_master_arprot, - near_mem$dmem_master_arsize, - near_mem$dmem_master_awprot, - near_mem$dmem_master_awsize, - near_mem$dmem_req_f3, - near_mem$imem_master_arprot, - near_mem$imem_master_arsize, - near_mem$imem_master_awprot, - near_mem$imem_master_awsize, - near_mem$imem_req_f3; - wire [1 : 0] near_mem$dmem_master_arburst, - near_mem$dmem_master_awburst, - near_mem$dmem_master_bresp, - near_mem$dmem_master_rresp, - near_mem$dmem_req_priv, - near_mem$imem_master_arburst, - near_mem$imem_master_awburst, - near_mem$imem_master_bresp, - near_mem$imem_master_rresp, - near_mem$imem_req_priv; - wire near_mem$EN_dmem_req, - near_mem$EN_imem_req, - near_mem$EN_server_fence_i_request_put, - near_mem$EN_server_fence_i_response_get, - near_mem$EN_server_fence_request_put, - near_mem$EN_server_fence_response_get, - near_mem$EN_server_reset_request_put, - near_mem$EN_server_reset_response_get, - near_mem$EN_sfence_vma, - near_mem$RDY_server_fence_i_request_put, - near_mem$RDY_server_fence_i_response_get, - near_mem$RDY_server_fence_request_put, - near_mem$RDY_server_fence_response_get, - near_mem$RDY_server_reset_request_put, - near_mem$RDY_server_reset_response_get, - near_mem$dmem_exc, - near_mem$dmem_master_arlock, - near_mem$dmem_master_arready, - near_mem$dmem_master_arvalid, - near_mem$dmem_master_awlock, - near_mem$dmem_master_awready, - near_mem$dmem_master_awvalid, - near_mem$dmem_master_bready, - near_mem$dmem_master_bvalid, - near_mem$dmem_master_rlast, - near_mem$dmem_master_rready, - near_mem$dmem_master_rvalid, - near_mem$dmem_master_wlast, - near_mem$dmem_master_wready, - near_mem$dmem_master_wvalid, - near_mem$dmem_req_mstatus_MXR, - near_mem$dmem_req_sstatus_SUM, - near_mem$dmem_valid, - near_mem$imem_exc, - near_mem$imem_is_i32_not_i16, - near_mem$imem_master_arlock, - near_mem$imem_master_arready, - near_mem$imem_master_arvalid, - near_mem$imem_master_awlock, - near_mem$imem_master_awready, - near_mem$imem_master_awvalid, - near_mem$imem_master_bready, - near_mem$imem_master_bvalid, - near_mem$imem_master_rlast, - near_mem$imem_master_rready, - near_mem$imem_master_rvalid, - near_mem$imem_master_wlast, - near_mem$imem_master_wready, - near_mem$imem_master_wvalid, - near_mem$imem_valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_pc_reset_value; - - // ports of submodule stage1_f_reset_reqs - wire stage1_f_reset_reqs$CLR, - stage1_f_reset_reqs$DEQ, - stage1_f_reset_reqs$EMPTY_N, - stage1_f_reset_reqs$ENQ, - stage1_f_reset_reqs$FULL_N; - - // ports of submodule stage1_f_reset_rsps - wire stage1_f_reset_rsps$CLR, - stage1_f_reset_rsps$DEQ, - stage1_f_reset_rsps$EMPTY_N, - stage1_f_reset_rsps$ENQ, - stage1_f_reset_rsps$FULL_N; - - // ports of submodule stage2_f_reset_reqs - wire stage2_f_reset_reqs$CLR, - stage2_f_reset_reqs$DEQ, - stage2_f_reset_reqs$EMPTY_N, - stage2_f_reset_reqs$ENQ, - stage2_f_reset_reqs$FULL_N; - - // ports of submodule stage2_f_reset_rsps - wire stage2_f_reset_rsps$CLR, - stage2_f_reset_rsps$DEQ, - stage2_f_reset_rsps$EMPTY_N, - stage2_f_reset_rsps$ENQ, - stage2_f_reset_rsps$FULL_N; - - // ports of submodule stage2_mbox - wire [31 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word; - wire [3 : 0] stage2_mbox$set_verbosity_verbosity; - wire [2 : 0] stage2_mbox$req_f3; - wire stage2_mbox$EN_req, - stage2_mbox$EN_req_reset, - stage2_mbox$EN_rsp_reset, - stage2_mbox$EN_set_verbosity, - stage2_mbox$req_is_OP_not_OP_32, - stage2_mbox$valid; - - // ports of submodule stage3_f_reset_reqs - wire stage3_f_reset_reqs$CLR, - stage3_f_reset_reqs$DEQ, - stage3_f_reset_reqs$EMPTY_N, - stage3_f_reset_reqs$ENQ, - stage3_f_reset_reqs$FULL_N; - - // ports of submodule stage3_f_reset_rsps - wire stage3_f_reset_rsps$CLR, - stage3_f_reset_rsps$DEQ, - stage3_f_reset_rsps$EMPTY_N, - stage3_f_reset_rsps$ENQ, - stage3_f_reset_rsps$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_imem_rl_assert_fail, - CAN_FIRE_RL_imem_rl_fetch_next_32b, - CAN_FIRE_RL_rl_WFI_resume, - CAN_FIRE_RL_rl_finish_FENCE, - CAN_FIRE_RL_rl_finish_FENCE_I, - CAN_FIRE_RL_rl_finish_SFENCE_VMA, - CAN_FIRE_RL_rl_pipe, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_RL_rl_reset_from_WFI, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_show_pipe, - CAN_FIRE_RL_rl_stage1_CSRR_S_or_C, - CAN_FIRE_RL_rl_stage1_CSRR_W, - CAN_FIRE_RL_rl_stage1_FENCE, - CAN_FIRE_RL_rl_stage1_FENCE_I, - CAN_FIRE_RL_rl_stage1_SFENCE_VMA, - CAN_FIRE_RL_rl_stage1_WFI, - CAN_FIRE_RL_rl_stage1_interrupt, - CAN_FIRE_RL_rl_stage1_restart_after_csrrx, - CAN_FIRE_RL_rl_stage1_trap, - CAN_FIRE_RL_rl_stage1_xRET, - CAN_FIRE_RL_rl_stage2_nonpipe, - CAN_FIRE_RL_rl_trap_fetch, - CAN_FIRE_RL_stage1_rl_reset, - CAN_FIRE_RL_stage2_rl_reset_begin, - CAN_FIRE_RL_stage2_rl_reset_end, - CAN_FIRE_RL_stage3_rl_reset, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_set_verbosity, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_imem_rl_assert_fail, - WILL_FIRE_RL_imem_rl_fetch_next_32b, - WILL_FIRE_RL_rl_WFI_resume, - WILL_FIRE_RL_rl_finish_FENCE, - WILL_FIRE_RL_rl_finish_FENCE_I, - WILL_FIRE_RL_rl_finish_SFENCE_VMA, - WILL_FIRE_RL_rl_pipe, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_RL_rl_reset_from_WFI, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_show_pipe, - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C, - WILL_FIRE_RL_rl_stage1_CSRR_W, - WILL_FIRE_RL_rl_stage1_FENCE, - WILL_FIRE_RL_rl_stage1_FENCE_I, - WILL_FIRE_RL_rl_stage1_SFENCE_VMA, - WILL_FIRE_RL_rl_stage1_WFI, - WILL_FIRE_RL_rl_stage1_interrupt, - WILL_FIRE_RL_rl_stage1_restart_after_csrrx, - WILL_FIRE_RL_rl_stage1_trap, - WILL_FIRE_RL_rl_stage1_xRET, - WILL_FIRE_RL_rl_stage2_nonpipe, - WILL_FIRE_RL_rl_trap_fetch, - WILL_FIRE_RL_stage1_rl_reset, - WILL_FIRE_RL_stage2_rl_reset_begin, - WILL_FIRE_RL_stage2_rl_reset_end, - WILL_FIRE_RL_stage3_rl_reset, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_set_verbosity, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - reg [31 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2; - wire [31 : 0] MUX_near_mem$imem_req_2__VAL_1, - MUX_near_mem$imem_req_2__VAL_2, - MUX_near_mem$imem_req_2__VAL_5; - wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1, - MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_3; - wire MUX_csr_regfile$mav_csr_write_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_3, - MUX_imem_rg_f3$write_1__SEL_1, - MUX_imem_rg_f3$write_1__SEL_2, - MUX_imem_rg_mstatus_MXR$write_1__SEL_4, - MUX_imem_rg_pc$write_1__SEL_4, - MUX_near_mem$imem_req_1__SEL_6, - MUX_rg_cur_priv$write_1__SEL_1, - MUX_rg_mstatus_MXR$write_1__SEL_1, - MUX_rg_next_pc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_11, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_4, - MUX_rg_state$write_1__SEL_6, - MUX_rg_state$write_1__SEL_7, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9, - MUX_stage1_rg_full$write_1__VAL_2, - MUX_stage2_rg_full$write_1__VAL_2; - - // remaining internal signals - reg [31 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936, - _theResult_____1_fst__h12709, - rs1_val__h17705, - x_out_bypass_rd_val__h5977, - x_out_data_to_stage2_addr__h11599, - x_out_data_to_stage2_val1__h11600, - x_out_data_to_stage3_rd_val__h5626; - reg [4 : 0] x_out_bypass_rd__h5976, x_out_data_to_stage3_rd__h5625; - reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q5, - CASE_theResult__264_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12, - CASE_theResult__264_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14, - CASE_theResult__264_BITS_14_TO_12_0b0_4_0b1_5_11__q13, - CASE_theResult__264_BITS_14_TO_12_0b0_IF_theRe_ETC__q15, - CASE_theResult__264_BITS_31_TO_20_0b0_CASE_rg__ETC__q6, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744, - alu_outputs_exc_code__h12265; - reg [2 : 0] CASE_theResult__264_BITS_6_TO_0_0b11_1_0b10011_ETC__q16, - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825; - reg [1 : 0] CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1, - CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2; - reg CASE_theResult__264_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11, - CASE_theResult__264_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9, - CASE_theResult__264_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8, - CASE_theResult__264_BITS_6_TO_0_0b11_theResult_ETC__q10, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628, - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132, - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141; - wire [127 : 0] csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1273; - wire [63 : 0] _theResult____h22269, - cpi__h22271, - cpifrac__h22272, - delta_CPI_cycles__h22267, - delta_CPI_instrs___1__h22304, - delta_CPI_instrs__h22268, - x__h22270; - wire [31 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869, - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d437, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d439, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d441, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d442, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d444, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d445, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d446, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d448, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d449, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d450, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d452, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d453, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d454, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d455, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d456, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d457, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d458, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d459, - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d460, - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878, - _theResult_____1_fst__h12702, - _theResult_____1_fst__h12737, - _theResult____h4264, - _theResult___fst__h6304, - _theResult___fst__h6332, - _theResult___snd__h13835, - alu_outputs___1_addr__h11723, - alu_outputs___1_addr__h11744, - alu_outputs___1_addr__h11770, - alu_outputs___1_addr__h11965, - alu_outputs___1_addr__h11986, - alu_outputs___1_val1__h11874, - alu_outputs___1_val1__h11912, - alu_outputs___1_val1__h11928, - alu_outputs___1_val1__h11944, - alu_outputs___1_val1__h12226, - alu_outputs___1_val1__h12247, - branch_target__h11701, - data_to_stage2_addr__h11591, - fall_through_pc__h11555, - instr___1__h6137, - instr__h10022, - instr__h10215, - instr__h10332, - instr__h10510, - instr__h10629, - instr__h10724, - instr__h10860, - instr__h10996, - instr__h11132, - instr__h11470, - instr__h4262, - instr__h6404, - instr__h6549, - instr__h6741, - instr__h6936, - instr__h7165, - instr__h7508, - instr__h7898, - instr__h8014, - instr__h8079, - instr__h8396, - instr__h8734, - instr__h8918, - instr__h9047, - instr__h9484, - instr__h9656, - instr__h9829, - instr_out___1__h6274, - instr_out___1__h6306, - instr_out___1__h6334, - next_pc___1__h13377, - next_pc__h13375, - output_stage2___1_bypass_rd_val__h5965, - rd_val___1__h12690, - rd_val___1__h12698, - rd_val___1__h12705, - rd_val___1__h12712, - rd_val___1__h12719, - rd_val___1__h12726, - rd_val__h11512, - rd_val__h13731, - rd_val__h13783, - rd_val__h13805, - rd_val__h6089, - rs1_val__h17215, - rs1_val_bypassed__h4272, - rs2_val__h11697, - trap_info_tval__h13214, - val__h11514, - val__h6091, - value__h13265, - x_out_data_to_stage2_instr__h11596, - x_out_data_to_stage2_val2__h11601, - x_out_next_pc__h11568, - y__h18006; - wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288, - theResult__264_BIT_31_CONCAT_theResult__264_BI_ETC__q4; - wire [19 : 0] imm20__h8786; - wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317, - theResult__264_BIT_31_CONCAT_theResult__264_BI_ETC__q3; - wire [11 : 0] imm12__h10038, - imm12__h6405, - imm12__h6742, - imm12__h8658, - imm12__h9282, - imm12__h9497, - imm12__h9693, - offset__h7112, - theResult__264_BITS_31_TO_20__q17, - theResult__264_BITS_31_TO_25_CONCAT_theResult__ETC__q7; - wire [9 : 0] nzimm10__h9280, nzimm10__h9495; - wire [8 : 0] offset__h8023; - wire [7 : 0] offset__h6175; - wire [6 : 0] offset__h6684; - wire [5 : 0] imm6__h8656; - wire [4 : 0] offset_BITS_4_TO_0___h6673, - offset_BITS_4_TO_0___h7104, - rd__h6744, - rs1__h6743, - shamt__h11859, - x_out_data_to_stage2_rd__h11598; - wire [3 : 0] IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690, - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746, - IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723, - alu_outputs___1_exc_code__h12222, - cur_verbosity__h2969, - x_out_trap_info_exc_code__h13217; - wire [1 : 0] IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176, - IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112, - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118, - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180, - IF_stage2_rg_stage2_8_BITS_100_TO_96_48_EQ_0_7_ETC___d175, - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115; - wire IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653, - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270, - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464, - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466, - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564, - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1163, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1165, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1168, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1182, - NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d812, - NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d849, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d210, - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1090, - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101, - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109, - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469, - _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161, - csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1083, - csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088, - csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1094, - csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302, - csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308, - gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d949, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d952, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d955, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d958, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d961, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d964, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d967, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d970, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d973, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d976, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d979, - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d982, - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d478, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1079, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685, - rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_EQ_0_ETC___d721, - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185, - rg_state_2_EQ_3_096_AND_stage3_rg_full_8_OR_NO_ETC___d1115, - stage2_f_reset_rsps_i_notEmpty__052_AND_stage3_ETC___d1061; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // actionvalue method hart0_server_reset_response_get - assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ; - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = near_mem$imem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = near_mem$imem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = near_mem$imem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = near_mem$imem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = near_mem$imem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = near_mem$imem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = near_mem$imem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = near_mem$imem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = near_mem$imem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = near_mem$imem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = near_mem$imem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = near_mem$imem_master_wvalid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = near_mem$imem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = near_mem$imem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = near_mem$imem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = near_mem$imem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = near_mem$imem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = near_mem$imem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = near_mem$imem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = near_mem$imem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = near_mem$imem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = near_mem$imem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = near_mem$imem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = near_mem$imem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = near_mem$imem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = near_mem$imem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = near_mem$imem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = near_mem$imem_master_rready ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = near_mem$dmem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = near_mem$dmem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = near_mem$dmem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = near_mem$dmem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = near_mem$dmem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = near_mem$dmem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = near_mem$dmem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = near_mem$dmem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = near_mem$dmem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = near_mem$dmem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = near_mem$dmem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = near_mem$dmem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = near_mem$dmem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = near_mem$dmem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = near_mem$dmem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = near_mem$dmem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = near_mem$dmem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = near_mem$dmem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = near_mem$dmem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = near_mem$dmem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = near_mem$dmem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = near_mem$dmem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = near_mem$dmem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = near_mem$dmem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = near_mem$dmem_master_rready ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // submodule csr_regfile - mkCSR_RegFile csr_regfile(.CLK(CLK), - .RST_N(RST_N), - .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr), - .access_permitted_1_priv(csr_regfile$access_permitted_1_priv), - .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write), - .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr), - .access_permitted_2_priv(csr_regfile$access_permitted_2_priv), - .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write), - .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr), - .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv), - .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv), - .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code), - .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv), - .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt), - .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi), - .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc), - .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval), - .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv), - .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear), - .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr), - .mav_csr_write_word(csr_regfile$mav_csr_write_word), - .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr), - .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear), - .read_csr_csr_addr(csr_regfile$read_csr_csr_addr), - .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr), - .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear), - .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear), - .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get), - .EN_mav_read_csr(csr_regfile$EN_mav_read_csr), - .EN_mav_csr_write(csr_regfile$EN_mav_csr_write), - .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions), - .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions), - .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr), - .EN_debug(csr_regfile$EN_debug), - .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get), - .read_csr(csr_regfile$read_csr), - .read_csr_port2(), - .mav_read_csr(), - .mav_csr_write(), - .read_misa(csr_regfile$read_misa), - .read_mstatus(csr_regfile$read_mstatus), - .read_ustatus(), - .read_satp(csr_regfile$read_satp), - .csr_trap_actions(csr_regfile$csr_trap_actions), - .RDY_csr_trap_actions(), - .csr_ret_actions(csr_regfile$csr_ret_actions), - .RDY_csr_ret_actions(), - .read_csr_minstret(csr_regfile$read_csr_minstret), - .read_csr_mcycle(csr_regfile$read_csr_mcycle), - .read_csr_mtime(), - .access_permitted_1(csr_regfile$access_permitted_1), - .access_permitted_2(csr_regfile$access_permitted_2), - .csr_counter_read_fault(), - .csr_mip_read(), - .interrupt_pending(csr_regfile$interrupt_pending), - .wfi_resume(csr_regfile$wfi_resume), - .nmi_pending(csr_regfile$nmi_pending), - .RDY_debug()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule gpr_regfile - mkGPR_RegFile gpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(gpr_regfile$read_rs1_rs1), - .read_rs2_rs2(gpr_regfile$read_rs2_rs2), - .write_rd_rd(gpr_regfile$write_rd_rd), - .write_rd_rd_val(gpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get), - .EN_write_rd(gpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get), - .read_rs1(gpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(gpr_regfile$read_rs2)); - - // submodule near_mem - mkNear_Mem near_mem(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(near_mem$dmem_master_arready), - .dmem_master_awready(near_mem$dmem_master_awready), - .dmem_master_bid(near_mem$dmem_master_bid), - .dmem_master_bresp(near_mem$dmem_master_bresp), - .dmem_master_bvalid(near_mem$dmem_master_bvalid), - .dmem_master_rdata(near_mem$dmem_master_rdata), - .dmem_master_rid(near_mem$dmem_master_rid), - .dmem_master_rlast(near_mem$dmem_master_rlast), - .dmem_master_rresp(near_mem$dmem_master_rresp), - .dmem_master_rvalid(near_mem$dmem_master_rvalid), - .dmem_master_wready(near_mem$dmem_master_wready), - .dmem_req_addr(near_mem$dmem_req_addr), - .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7), - .dmem_req_f3(near_mem$dmem_req_f3), - .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR), - .dmem_req_op(near_mem$dmem_req_op), - .dmem_req_priv(near_mem$dmem_req_priv), - .dmem_req_satp(near_mem$dmem_req_satp), - .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM), - .dmem_req_store_value(near_mem$dmem_req_store_value), - .imem_master_arready(near_mem$imem_master_arready), - .imem_master_awready(near_mem$imem_master_awready), - .imem_master_bid(near_mem$imem_master_bid), - .imem_master_bresp(near_mem$imem_master_bresp), - .imem_master_bvalid(near_mem$imem_master_bvalid), - .imem_master_rdata(near_mem$imem_master_rdata), - .imem_master_rid(near_mem$imem_master_rid), - .imem_master_rlast(near_mem$imem_master_rlast), - .imem_master_rresp(near_mem$imem_master_rresp), - .imem_master_rvalid(near_mem$imem_master_rvalid), - .imem_master_wready(near_mem$imem_master_wready), - .imem_req_addr(near_mem$imem_req_addr), - .imem_req_f3(near_mem$imem_req_f3), - .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR), - .imem_req_priv(near_mem$imem_req_priv), - .imem_req_satp(near_mem$imem_req_satp), - .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM), - .server_fence_request_put(near_mem$server_fence_request_put), - .EN_server_reset_request_put(near_mem$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem$EN_server_reset_response_get), - .EN_imem_req(near_mem$EN_imem_req), - .EN_dmem_req(near_mem$EN_dmem_req), - .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put), - .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get), - .EN_server_fence_request_put(near_mem$EN_server_fence_request_put), - .EN_server_fence_response_get(near_mem$EN_server_fence_response_get), - .EN_sfence_vma(near_mem$EN_sfence_vma), - .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get), - .imem_valid(near_mem$imem_valid), - .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16), - .imem_pc(near_mem$imem_pc), - .imem_instr(near_mem$imem_instr), - .imem_exc(near_mem$imem_exc), - .imem_exc_code(near_mem$imem_exc_code), - .imem_tval(), - .imem_master_awvalid(near_mem$imem_master_awvalid), - .imem_master_awid(near_mem$imem_master_awid), - .imem_master_awaddr(near_mem$imem_master_awaddr), - .imem_master_awlen(near_mem$imem_master_awlen), - .imem_master_awsize(near_mem$imem_master_awsize), - .imem_master_awburst(near_mem$imem_master_awburst), - .imem_master_awlock(near_mem$imem_master_awlock), - .imem_master_awcache(near_mem$imem_master_awcache), - .imem_master_awprot(near_mem$imem_master_awprot), - .imem_master_awqos(near_mem$imem_master_awqos), - .imem_master_awregion(near_mem$imem_master_awregion), - .imem_master_wvalid(near_mem$imem_master_wvalid), - .imem_master_wdata(near_mem$imem_master_wdata), - .imem_master_wstrb(near_mem$imem_master_wstrb), - .imem_master_wlast(near_mem$imem_master_wlast), - .imem_master_bready(near_mem$imem_master_bready), - .imem_master_arvalid(near_mem$imem_master_arvalid), - .imem_master_arid(near_mem$imem_master_arid), - .imem_master_araddr(near_mem$imem_master_araddr), - .imem_master_arlen(near_mem$imem_master_arlen), - .imem_master_arsize(near_mem$imem_master_arsize), - .imem_master_arburst(near_mem$imem_master_arburst), - .imem_master_arlock(near_mem$imem_master_arlock), - .imem_master_arcache(near_mem$imem_master_arcache), - .imem_master_arprot(near_mem$imem_master_arprot), - .imem_master_arqos(near_mem$imem_master_arqos), - .imem_master_arregion(near_mem$imem_master_arregion), - .imem_master_rready(near_mem$imem_master_rready), - .dmem_valid(near_mem$dmem_valid), - .dmem_word64(near_mem$dmem_word64), - .dmem_st_amo_val(), - .dmem_exc(near_mem$dmem_exc), - .dmem_exc_code(near_mem$dmem_exc_code), - .dmem_master_awvalid(near_mem$dmem_master_awvalid), - .dmem_master_awid(near_mem$dmem_master_awid), - .dmem_master_awaddr(near_mem$dmem_master_awaddr), - .dmem_master_awlen(near_mem$dmem_master_awlen), - .dmem_master_awsize(near_mem$dmem_master_awsize), - .dmem_master_awburst(near_mem$dmem_master_awburst), - .dmem_master_awlock(near_mem$dmem_master_awlock), - .dmem_master_awcache(near_mem$dmem_master_awcache), - .dmem_master_awprot(near_mem$dmem_master_awprot), - .dmem_master_awqos(near_mem$dmem_master_awqos), - .dmem_master_awregion(near_mem$dmem_master_awregion), - .dmem_master_wvalid(near_mem$dmem_master_wvalid), - .dmem_master_wdata(near_mem$dmem_master_wdata), - .dmem_master_wstrb(near_mem$dmem_master_wstrb), - .dmem_master_wlast(near_mem$dmem_master_wlast), - .dmem_master_bready(near_mem$dmem_master_bready), - .dmem_master_arvalid(near_mem$dmem_master_arvalid), - .dmem_master_arid(near_mem$dmem_master_arid), - .dmem_master_araddr(near_mem$dmem_master_araddr), - .dmem_master_arlen(near_mem$dmem_master_arlen), - .dmem_master_arsize(near_mem$dmem_master_arsize), - .dmem_master_arburst(near_mem$dmem_master_arburst), - .dmem_master_arlock(near_mem$dmem_master_arlock), - .dmem_master_arcache(near_mem$dmem_master_arcache), - .dmem_master_arprot(near_mem$dmem_master_arprot), - .dmem_master_arqos(near_mem$dmem_master_arqos), - .dmem_master_arregion(near_mem$dmem_master_arregion), - .dmem_master_rready(near_mem$dmem_master_rready), - .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put), - .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get), - .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put), - .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get), - .RDY_sfence_vma()); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(soc_map$m_pc_reset_value), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule stage1_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_reqs$ENQ), - .DEQ(stage1_f_reset_reqs$DEQ), - .CLR(stage1_f_reset_reqs$CLR), - .FULL_N(stage1_f_reset_reqs$FULL_N), - .EMPTY_N(stage1_f_reset_reqs$EMPTY_N)); - - // submodule stage1_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_rsps$ENQ), - .DEQ(stage1_f_reset_rsps$DEQ), - .CLR(stage1_f_reset_rsps$CLR), - .FULL_N(stage1_f_reset_rsps$FULL_N), - .EMPTY_N(stage1_f_reset_rsps$EMPTY_N)); - - // submodule stage2_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_reqs$ENQ), - .DEQ(stage2_f_reset_reqs$DEQ), - .CLR(stage2_f_reset_reqs$CLR), - .FULL_N(stage2_f_reset_reqs$FULL_N), - .EMPTY_N(stage2_f_reset_reqs$EMPTY_N)); - - // submodule stage2_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_rsps$ENQ), - .DEQ(stage2_f_reset_rsps$DEQ), - .CLR(stage2_f_reset_rsps$CLR), - .FULL_N(stage2_f_reset_rsps$FULL_N), - .EMPTY_N(stage2_f_reset_rsps$EMPTY_N)); - - // submodule stage2_mbox - mkRISCV_MBox stage2_mbox(.CLK(CLK), - .RST_N(RST_N), - .req_f3(stage2_mbox$req_f3), - .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32), - .req_v1(stage2_mbox$req_v1), - .req_v2(stage2_mbox$req_v2), - .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity), - .EN_set_verbosity(stage2_mbox$EN_set_verbosity), - .EN_req_reset(stage2_mbox$EN_req_reset), - .EN_rsp_reset(stage2_mbox$EN_rsp_reset), - .EN_req(stage2_mbox$EN_req), - .RDY_set_verbosity(), - .RDY_req_reset(), - .RDY_rsp_reset(), - .valid(stage2_mbox$valid), - .word(stage2_mbox$word)); - - // submodule stage3_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_reqs$ENQ), - .DEQ(stage3_f_reset_reqs$DEQ), - .CLR(stage3_f_reset_reqs$CLR), - .FULL_N(stage3_f_reset_reqs$FULL_N), - .EMPTY_N(stage3_f_reset_reqs$EMPTY_N)); - - // submodule stage3_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_rsps$ENQ), - .DEQ(stage3_f_reset_rsps$DEQ), - .CLR(stage3_f_reset_rsps$CLR), - .FULL_N(stage3_f_reset_rsps$FULL_N), - .EMPTY_N(stage3_f_reset_rsps$EMPTY_N)); - - // rule RL_rl_show_pipe - assign CAN_FIRE_RL_rl_show_pipe = - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - rg_state != 4'd0 && - rg_state != 4'd1 && - rg_state != 4'd10 ; - assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ; - - // rule RL_rl_stage2_nonpipe - assign CAN_FIRE_RL_rl_stage2_nonpipe = - rg_state == 4'd3 && !stage3_rg_full && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd3 && - (!stage1_rg_full || - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484) ; - assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ; - - // rule RL_rl_stage1_CSRR_W - assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_stage1_CSRR_S_or_C - assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_stage1_restart_after_csrrx - assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx = - CAN_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // rule RL_rl_stage1_xRET - assign CAN_FIRE_RL_rl_stage1_xRET = - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd7 || - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd8 || - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd9) ; - assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ; - - // rule RL_rl_stage1_FENCE_I - assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - - // rule RL_rl_finish_FENCE_I - assign CAN_FIRE_RL_rl_finish_FENCE_I = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_i_response_get && - rg_state == 4'd7 ; - assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ; - - // rule RL_rl_stage1_FENCE - assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - - // rule RL_rl_finish_FENCE - assign CAN_FIRE_RL_rl_finish_FENCE = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_response_get && - rg_state == 4'd8 ; - assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ; - - // rule RL_rl_stage1_SFENCE_VMA - assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - - // rule RL_rl_finish_SFENCE_VMA - assign CAN_FIRE_RL_rl_finish_SFENCE_VMA = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_finish_SFENCE_VMA = - CAN_FIRE_RL_rl_finish_SFENCE_VMA ; - - // rule RL_rl_stage1_WFI - assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - - // rule RL_rl_WFI_resume - assign CAN_FIRE_RL_rl_WFI_resume = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd10 && - csr_regfile$wfi_resume ; - assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ; - - // rule RL_rl_reset_from_WFI - assign CAN_FIRE_RL_rl_reset_from_WFI = - rg_state == 4'd10 && f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_4 ; - - // rule RL_rl_stage1_trap - assign CAN_FIRE_RL_rl_stage1_trap = - rg_state == 4'd4 || - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd11 ; - assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ; - - // rule RL_rl_trap_fetch - assign CAN_FIRE_RL_rl_trap_fetch = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd5 ; - assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; - - // rule RL_rl_stage1_interrupt - assign CAN_FIRE_RL_rl_stage1_interrupt = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - rg_state == 4'd3 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd0 && - !stage3_rg_full ; - assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ; - - // rule RL_imem_rl_assert_fail - assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ; - assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = - gpr_regfile$RDY_server_reset_response_get && - near_mem$RDY_server_reset_response_get && - csr_regfile$RDY_server_reset_response_get && - stage1_f_reset_rsps$EMPTY_N && - stage2_f_reset_rsps_i_notEmpty__052_AND_stage3_ETC___d1061 && - rg_state == 4'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_pipe - assign CAN_FIRE_RL_rl_pipe = - (csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1094 || - !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state_2_EQ_3_096_AND_stage3_rg_full_8_OR_NO_ETC___d1115 ; - assign WILL_FIRE_RL_rl_pipe = - CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = - gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043 && - rg_state == 4'd0 ; - assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ; - - // rule RL_imem_rl_fetch_next_32b - assign CAN_FIRE_RL_imem_rl_fetch_next_32b = - near_mem$imem_valid && - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] == 2'b11 ; - assign WILL_FIRE_RL_imem_rl_fetch_next_32b = - CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_stage3_rl_reset - assign CAN_FIRE_RL_stage3_rl_reset = - stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ; - - // rule RL_stage2_rl_reset_end - assign CAN_FIRE_RL_stage2_rl_reset_end = - stage2_f_reset_rsps$FULL_N && stage2_rg_resetting ; - assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ; - - // rule RL_stage2_rl_reset_begin - assign CAN_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ; - - // rule RL_stage1_rl_reset - assign CAN_FIRE_RL_stage1_rl_reset = - stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_csr_regfile$mav_csr_write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 ; - assign MUX_gpr_regfile$write_rd_1__SEL_1 = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] ; - assign MUX_gpr_regfile$write_rd_1__SEL_3 = - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - assign MUX_imem_rg_f3$write_1__SEL_1 = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ; - assign MUX_imem_rg_f3$write_1__SEL_2 = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 ; - assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_imem_rg_pc$write_1__SEL_4 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_near_mem$imem_req_1__SEL_6 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_rg_cur_priv$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_mstatus_MXR$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_next_pc$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign MUX_rg_state$write_1__SEL_1 = - CAN_FIRE_RL_rl_reset_complete && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_2 = - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd2 ; - assign MUX_rg_state$write_1__SEL_3 = - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd3 ; - assign MUX_rg_state$write_1__SEL_4 = - CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ; - assign MUX_rg_state$write_1__SEL_6 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_rg_state$write_1__SEL_7 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_state$write_1__SEL_8 = - near_mem$RDY_server_fence_i_request_put && - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd5 ; - assign MUX_rg_state$write_1__SEL_9 = - near_mem$RDY_server_fence_request_put && - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd4 ; - assign MUX_rg_state$write_1__SEL_10 = - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd6 ; - assign MUX_rg_state$write_1__SEL_11 = - rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd10 ; - assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 = - (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ? - csr_regfile$interrupt_pending[3:0] : - 4'd0 ; - always@(x_out_data_to_stage2_instr__h11596 or - csr_regfile$read_csr or - y__h18006 or - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220) - begin - case (x_out_data_to_stage2_instr__h11596[14:12]) - 3'b010, 3'b110: - MUX_csr_regfile$mav_csr_write_2__VAL_2 = - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220; - default: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - csr_regfile$read_csr[31:0] & y__h18006; - endcase - end - assign MUX_near_mem$imem_req_2__VAL_1 = - { soc_map$m_pc_reset_value[31:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_2 = - { x_out_next_pc__h11568[31:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[31:2], 2'b0 } ; - assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd3 : 4'd2 ; - assign MUX_rg_state$write_1__VAL_2 = - csr_regfile$access_permitted_1 ? 4'd6 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_3 = - csr_regfile$access_permitted_2 ? 4'd6 : 4'd4 ; - assign MUX_stage1_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1168 || - (csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088 || - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109) && - stage1_rg_full ; - assign MUX_stage2_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1163 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd2 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd0 ; - - // register cfg_logdelay - assign cfg_logdelay$D_IN = set_verbosity_logdelay ; - assign cfg_logdelay$EN = EN_set_verbosity ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register imem_rg_f3 - assign imem_rg_f3$D_IN = 3'b010 ; - assign imem_rg_f3$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_instr_15_0 - assign imem_rg_instr_15_0$D_IN = near_mem$imem_instr[31:16] ; - assign imem_rg_instr_15_0$EN = CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // register imem_rg_mstatus_MXR - assign imem_rg_mstatus_MXR$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_mstatus[19] : - rg_mstatus_MXR ; - assign imem_rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_pc - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h11568 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0]; - MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h11568; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_pc$D_IN = x_out_next_pc__h11568; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc; - default: imem_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_pc$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - - // register imem_rg_priv - assign imem_rg_priv$D_IN = rg_cur_priv ; - assign imem_rg_priv$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_satp - assign imem_rg_satp$D_IN = csr_regfile$read_satp ; - assign imem_rg_satp$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_sstatus_SUM - assign imem_rg_sstatus_SUM$D_IN = - WILL_FIRE_RL_rl_trap_fetch && rg_sstatus_SUM ; - assign imem_rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_tval - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h11568 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or - rg_next_pc or - WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h13377) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_tval$D_IN = soc_map$m_pc_reset_value[31:0]; - MUX_imem_rg_f3$write_1__SEL_2: - imem_rg_tval$D_IN = x_out_next_pc__h11568; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_tval$D_IN = x_out_next_pc__h11568; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - imem_rg_tval$D_IN = next_pc___1__h13377; - default: imem_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_tval$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // register rg_cur_priv - always@(MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or - csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_cur_priv$write_1__SEL_1: - rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[33:32]; - WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11; - default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_cur_priv$EN = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_mstatus[19] : - csr_regfile$csr_trap_actions[53] ; - assign rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_next_pc - always@(MUX_rg_next_pc$write_1__SEL_1 or - x_out_next_pc__h11568 or - MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h11568; - MUX_rg_cur_priv$write_1__SEL_1: - rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34]; - default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_next_pc$EN = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET ; - - // register rg_run_on_reset - assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ; - assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = - WILL_FIRE_RL_rl_stage1_interrupt && - csr_regfile$csr_trap_actions[52] ; - assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_7 ; - - // register rg_start_CPI_cycles - assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ; - assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_start_CPI_instrs - assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ; - assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_state - always@(WILL_FIRE_RL_rl_reset_complete or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_stage1_CSRR_W or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or - MUX_rg_state$write_1__VAL_3 or - WILL_FIRE_RL_rl_reset_from_WFI or - WILL_FIRE_RL_rl_reset_start or - MUX_rg_state$write_1__SEL_6 or - MUX_rg_state$write_1__SEL_7 or - WILL_FIRE_RL_rl_stage1_FENCE_I or - WILL_FIRE_RL_rl_stage1_FENCE or - WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_reset_complete: - rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_stage1_CSRR_W: - rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: - rg_state$D_IN = MUX_rg_state$write_1__VAL_3; - WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1; - MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd5; - WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd7; - WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd8; - WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd10; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_complete || - WILL_FIRE_RL_rl_stage1_CSRR_W || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C || - WILL_FIRE_RL_rl_reset_from_WFI || - WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_WFI ; - - // register stage1_rg_full - always@(WILL_FIRE_RL_stage1_rl_reset or - WILL_FIRE_RL_rl_pipe or - MUX_stage1_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or - WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_trap_fetch or - WILL_FIRE_RL_rl_stage1_trap or - WILL_FIRE_RL_rl_WFI_resume or - WILL_FIRE_RL_rl_finish_SFENCE_VMA or - WILL_FIRE_RL_rl_finish_FENCE or - WILL_FIRE_RL_rl_finish_FENCE_I or - WILL_FIRE_RL_rl_stage1_xRET or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_interrupt: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_trap_fetch: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_trap: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I: - stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_xRET: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0; - default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage1_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage1_rl_reset || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register stage2_rg_full - always@(stage2_f_reset_reqs$EMPTY_N or - WILL_FIRE_RL_rl_pipe or - MUX_stage2_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - stage2_f_reset_reqs$EMPTY_N: stage2_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage2_nonpipe: - stage2_rg_full$D_IN = 1'd0; - default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage2_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage2_nonpipe || - stage2_f_reset_reqs$EMPTY_N ; - - // register stage2_rg_resetting - assign stage2_rg_resetting$D_IN = stage2_f_reset_reqs$EMPTY_N ; - assign stage2_rg_resetting$EN = - WILL_FIRE_RL_stage2_rl_reset_end || stage2_f_reset_reqs$EMPTY_N ; - - // register stage2_rg_stage2 - assign stage2_rg_stage2$D_IN = - { rg_cur_priv, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825, - x_out_data_to_stage2_rd__h11598, - x_out_data_to_stage2_addr__h11599, - x_out_data_to_stage2_val1__h11600, - x_out_data_to_stage2_val2__h11601 } ; - assign stage2_rg_stage2$EN = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 ; - - // register stage3_rg_full - always@(WILL_FIRE_RL_stage3_rl_reset or - WILL_FIRE_RL_rl_pipe or - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 or - MUX_imem_rg_f3$write_1__SEL_1) - case (1'b1) - WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage3_rg_full$D_IN = - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2; - MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0; - default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage3_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_stage3_rl_reset ; - - // register stage3_rg_stage3 - assign stage3_rg_stage3$D_IN = - { stage2_rg_stage2[167:104], - stage2_rg_stage2[169:168], - stage2_rg_stage2[103:101] == 3'd0 || - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141, - x_out_data_to_stage3_rd__h5625, - x_out_data_to_stage3_rd_val__h5626 } ; - assign stage3_rg_stage3$EN = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd2 ; - - // submodule csr_regfile - assign csr_regfile$access_permitted_1_csr_addr = - x_out_data_to_stage2_instr__h11596[31:20] ; - assign csr_regfile$access_permitted_1_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ; - assign csr_regfile$access_permitted_2_csr_addr = - x_out_data_to_stage2_instr__h11596[31:20] ; - assign csr_regfile$access_permitted_2_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_2_read_not_write = - rs1_val__h17705 == 32'd0 ; - assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ; - assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ; - always@(IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746) - begin - case (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746) - 4'd7: csr_regfile$csr_ret_actions_from_priv = 2'b11; - 4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b01; - default: csr_regfile$csr_ret_actions_from_priv = 2'b0; - endcase - end - always@(WILL_FIRE_RL_rl_stage1_interrupt or - MUX_csr_regfile$csr_trap_actions_5__VAL_1 or - WILL_FIRE_RL_rl_stage1_trap or - x_out_trap_info_exc_code__h13217 or - WILL_FIRE_RL_rl_stage2_nonpipe or near_mem$dmem_exc_code) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_exc_code = - MUX_csr_regfile$csr_trap_actions_5__VAL_1; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h13217; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_exc_code = near_mem$dmem_exc_code; - default: csr_regfile$csr_trap_actions_exc_code = - 4'b1010 /* unspecified value */ ; - endcase - end - assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ; - assign csr_regfile$csr_trap_actions_interrupt = - WILL_FIRE_RL_rl_stage1_interrupt && !csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_nmi = - WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_pc = - WILL_FIRE_RL_rl_stage2_nonpipe ? - stage2_rg_stage2[167:136] : - imem_rg_pc ; - always@(WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_stage1_trap or - value__h13265 or WILL_FIRE_RL_rl_stage2_nonpipe or stage2_rg_stage2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_xtval = 32'd0; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_xtval = value__h13265; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_xtval = stage2_rg_stage2[95:64]; - default: csr_regfile$csr_trap_actions_xtval = - 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ; - assign csr_regfile$m_external_interrupt_req_set_not_clear = - m_external_interrupt_req_set_not_clear ; - assign csr_regfile$mav_csr_write_csr_addr = - x_out_data_to_stage2_instr__h11596[31:20] ; - assign csr_regfile$mav_csr_write_word = - MUX_csr_regfile$mav_csr_write_1__SEL_1 ? - rs1_val__h17215 : - MUX_csr_regfile$mav_csr_write_2__VAL_2 ; - assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ; - assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign csr_regfile$read_csr_csr_addr = - x_out_data_to_stage2_instr__h11596[31:20] ; - assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ; - assign csr_regfile$s_external_interrupt_req_set_not_clear = - s_external_interrupt_req_set_not_clear ; - assign csr_regfile$software_interrupt_req_set_not_clear = - software_interrupt_req_set_not_clear ; - assign csr_regfile$timer_interrupt_req_set_not_clear = - timer_interrupt_req_set_not_clear ; - assign csr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign csr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign csr_regfile$EN_mav_read_csr = 1'b0 ; - assign csr_regfile$EN_mav_csr_write = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h11596[19:15] != 5'd0 ; - assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_1 ; - assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ; - assign csr_regfile$EN_csr_minstret_incr = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd2 || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_stage1_WFI || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign csr_regfile$EN_debug = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = hart0_server_reset_request_put ; - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = - gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043 && - rg_state == 4'd0 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = rg_run_on_reset ; - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule gpr_regfile - assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign gpr_regfile$read_rs1_rs1 = _theResult____h4264[19:15] ; - assign gpr_regfile$read_rs2_rs2 = _theResult____h4264[24:20] ; - assign gpr_regfile$write_rd_rd = - MUX_gpr_regfile$write_rd_1__SEL_1 ? - stage3_rg_stage3[36:32] : - x_out_data_to_stage2_instr__h11596[11:7] ; - assign gpr_regfile$write_rd_rd_val = - (MUX_csr_regfile$mav_csr_write_1__SEL_1 || - MUX_gpr_regfile$write_rd_1__SEL_3) ? - csr_regfile$read_csr[31:0] : - stage3_rg_stage3[31:0] ; - assign gpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign gpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign gpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - - // submodule near_mem - assign near_mem$dmem_master_arready = dmem_master_arready ; - assign near_mem$dmem_master_awready = dmem_master_awready ; - assign near_mem$dmem_master_bid = dmem_master_bid ; - assign near_mem$dmem_master_bresp = dmem_master_bresp ; - assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; - assign near_mem$dmem_master_rdata = dmem_master_rdata ; - assign near_mem$dmem_master_rid = dmem_master_rid ; - assign near_mem$dmem_master_rlast = dmem_master_rlast ; - assign near_mem$dmem_master_rresp = dmem_master_rresp ; - assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; - assign near_mem$dmem_master_wready = dmem_master_wready ; - assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h11599 ; - assign near_mem$dmem_req_amo_funct7 = - x_out_data_to_stage2_val1__h11600[6:0] ; - assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h11596[14:12] ; - assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ; - always@(IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825) - begin - case (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825) - 3'd1: near_mem$dmem_req_op = 2'd0; - 3'd2: near_mem$dmem_req_op = 2'd1; - default: near_mem$dmem_req_op = 2'd2; - endcase - end - assign near_mem$dmem_req_priv = - csr_regfile$read_mstatus[17] ? - csr_regfile$read_mstatus[12:11] : - rg_cur_priv ; - assign near_mem$dmem_req_satp = csr_regfile$read_satp ; - assign near_mem$dmem_req_sstatus_SUM = 1'd0 ; - assign near_mem$dmem_req_store_value = - { 32'd0, x_out_data_to_stage2_val2__h11601 } ; - assign near_mem$imem_master_arready = imem_master_arready ; - assign near_mem$imem_master_awready = imem_master_awready ; - assign near_mem$imem_master_bid = imem_master_bid ; - assign near_mem$imem_master_bresp = imem_master_bresp ; - assign near_mem$imem_master_bvalid = imem_master_bvalid ; - assign near_mem$imem_master_rdata = imem_master_rdata ; - assign near_mem$imem_master_rid = imem_master_rid ; - assign near_mem$imem_master_rlast = imem_master_rlast ; - assign near_mem$imem_master_rresp = imem_master_rresp ; - assign near_mem$imem_master_rvalid = imem_master_rvalid ; - assign near_mem$imem_master_wready = imem_master_wready ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_near_mem$imem_req_2__VAL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - MUX_near_mem$imem_req_2__VAL_2 or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - next_pc___1__h13377 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_trap_fetch or - MUX_near_mem$imem_req_2__VAL_5 or MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1; - MUX_imem_rg_f3$write_1__SEL_2: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_addr = next_pc___1__h13377; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - default: near_mem$imem_req_addr = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_f3 = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_mstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_mstatus_MXR or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_mstatus_MXR) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_mstatus_MXR = imem_rg_mstatus_MXR; - default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_priv = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - MUX_near_mem$imem_req_1__SEL_6) ? - rg_cur_priv : - imem_rg_priv ; - assign near_mem$imem_req_satp = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? - imem_rg_satp : - csr_regfile$read_satp ; - always@(WILL_FIRE_RL_rl_trap_fetch or - rg_sstatus_SUM or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - imem_rg_sstatus_SUM or - MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_sstatus_SUM = imem_rg_sstatus_SUM; - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_sstatus_SUM = 1'd0; - default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$server_fence_request_put = - 8'b10101010 /* unspecified value */ ; - assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ; - assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ; - assign near_mem$EN_imem_req = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 || - WILL_FIRE_RL_imem_rl_fetch_next_32b || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_dmem_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 && - (IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == - 3'd1 || - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == - 3'd2 || - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == - 3'd4) ; - assign near_mem$EN_server_fence_i_request_put = - MUX_rg_state$write_1__SEL_8 ; - assign near_mem$EN_server_fence_i_response_get = - CAN_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_9 ; - assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ; - assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_10 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule stage1_f_reset_reqs - assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage1_f_reset_rsps - assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage1_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_f_reset_reqs - assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage2_f_reset_reqs$DEQ = stage2_f_reset_reqs$EMPTY_N ; - assign stage2_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage2_f_reset_rsps - assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage2_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_mbox - assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h11596[14:12] ; - assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4264[3] ; - assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h11600 ; - assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h11601 ; - assign stage2_mbox$set_verbosity_verbosity = 4'h0 ; - assign stage2_mbox$EN_set_verbosity = 1'b0 ; - assign stage2_mbox$EN_req_reset = 1'b0 ; - assign stage2_mbox$EN_rsp_reset = 1'b0 ; - assign stage2_mbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == - 3'd3 ; - - // submodule stage3_f_reset_reqs - assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage3_f_reset_rsps - assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage3_f_reset_rsps$CLR = 1'b0 ; - - // remaining internal signals - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523 = - rs1_val_bypassed__h4272 == rs2_val__h11697 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525 = - (rs1_val_bypassed__h4272 ^ 32'h80000000) < - (rs2_val__h11697 ^ 32'h80000000) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527 = - rs1_val_bypassed__h4272 < rs2_val__h11697 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 = - (_theResult____h4264[6:0] == 7'b1100011) ? - _theResult____h4264[14:12] != 3'b0 && - _theResult____h4264[14:12] != 3'b001 && - _theResult____h4264[14:12] != 3'b100 && - _theResult____h4264[14:12] != 3'b101 && - _theResult____h4264[14:12] != 3'b110 && - _theResult____h4264[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 : - (_theResult____h4264[6:0] != 7'b0110011 || - _theResult____h4264[31:25] != 7'b0000001) && - (((_theResult____h4264[6:0] == 7'b0010011 || - _theResult____h4264[6:0] == 7'b0110011) && - (_theResult____h4264[14:12] == 3'b001 || - _theResult____h4264[14:12] == 3'b101)) ? - _theResult____h4264[25] : - CASE_theResult__264_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 = - (_theResult____h4264[6:0] == 7'b1100011) ? - _theResult____h4264[14:12] != 3'b0 && - _theResult____h4264[14:12] != 3'b001 && - _theResult____h4264[14:12] != 3'b100 && - _theResult____h4264[14:12] != 3'b101 && - _theResult____h4264[14:12] != 3'b110 && - _theResult____h4264[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 : - _theResult____h4264[6:0] != 7'b1101111 && - _theResult____h4264[6:0] != 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 = - (_theResult____h4264[6:0] == 7'b1100011) ? - (_theResult____h4264[14:12] == 3'b0 || - _theResult____h4264[14:12] == 3'b001 || - _theResult____h4264[14:12] == 3'b100 || - _theResult____h4264[14:12] == 3'b101 || - _theResult____h4264[14:12] == 3'b110 || - _theResult____h4264[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 : - _theResult____h4264[6:0] == 7'b0110011 && - _theResult____h4264[31:25] == 7'b0000001 || - (((_theResult____h4264[6:0] == 7'b0010011 || - _theResult____h4264[6:0] == 7'b0110011) && - (_theResult____h4264[14:12] == 3'b001 || - _theResult____h4264[14:12] == 3'b101)) ? - !_theResult____h4264[25] : - CASE_theResult__264_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682 = - (_theResult____h4264[6:0] == 7'b1100011) ? - (_theResult____h4264[14:12] == 3'b0 || - _theResult____h4264[14:12] == 3'b001 || - _theResult____h4264[14:12] == 3'b100 || - _theResult____h4264[14:12] == 3'b101 || - _theResult____h4264[14:12] == 3'b110 || - _theResult____h4264[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 : - _theResult____h4264[6:0] == 7'b1101111 || - _theResult____h4264[6:0] == 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937 = - ((_theResult____h4264[6:0] == 7'b0010011 || - _theResult____h4264[6:0] == 7'b0110011) && - (_theResult____h4264[14:12] == 3'b001 || - _theResult____h4264[14:12] == 3'b101)) ? - alu_outputs___1_val1__h11874 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 ; - assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564 ? - 4'd11 : - 4'd0 ; - assign IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - IF_stage2_rg_stage2_8_BITS_100_TO_96_48_EQ_0_7_ETC___d175 : - 2'd0 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653 = - _theResult____h4264[14:12] == 3'b0 && - (_theResult____h4264[6:0] != 7'b0110011 || - !_theResult____h4264[30]) || - _theResult____h4264[14:12] == 3'b0 && - _theResult____h4264[6:0] == 7'b0110011 && - _theResult____h4264[30] || - _theResult____h4264[14:12] == 3'b010 || - _theResult____h4264[14:12] == 3'b011 || - _theResult____h4264[14:12] == 3'b100 || - _theResult____h4264[14:12] == 3'b110 || - _theResult____h4264[14:12] == 3'b111 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 ? - next_pc___1__h13377 : - next_pc__h13375 ; - assign IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270 = - imem_rg_pc == csr_regfile$csr_trap_actions[97:66] ; - assign IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 = - near_mem$imem_exc ? - 4'd11 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 ; - assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1220 = - csr_regfile$read_csr[31:0] | rs1_val__h17705 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d437 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:10] == 6'b100011 && - instr__h4262[6:5] == 2'b0) ? - instr__h11132 : - ((csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b10 && - instr__h4262[15:12] == 4'b1001 && - instr__h4262[11:7] == 5'd0 && - instr__h4262[6:2] == 5'd0) ? - instr__h11470 : - 32'h0) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d439 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:10] == 6'b100011 && - instr__h4262[6:5] == 2'b10) ? - instr__h10860 : - ((csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:10] == 6'b100011 && - instr__h4262[6:5] == 2'b01) ? - instr__h10996 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d437) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d441 = - (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308 && - instr__h4262[6:2] != 5'd0) ? - instr__h10629 : - ((csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:10] == 6'b100011 && - instr__h4262[6:5] == 2'b11) ? - instr__h10724 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d439) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d442 = - (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302 && - instr__h4262[6:2] != 5'd0) ? - instr__h10510 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d441 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d444 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b100 && - instr__h4262[11:10] == 2'b01 && - imm6__h8656 != 6'd0 && - !instr__h4262[12]) ? - instr__h10215 : - ((csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b100 && - instr__h4262[11:10] == 2'b10) ? - instr__h10332 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d442) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d445 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b100 && - instr__h4262[11:10] == 2'b0 && - imm6__h8656 != 6'd0 && - !instr__h4262[12]) ? - instr__h10022 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d444 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d446 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b10 && - instr__h4262[15:13] == 3'b0 && - instr__h4262[11:7] != 5'd0 && - imm6__h8656 != 6'd0 && - !instr__h4262[12]) ? - instr__h9829 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d445 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d448 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b011 && - instr__h4262[11:7] == 5'd2 && - nzimm10__h9280 != 10'd0) ? - instr__h9484 : - ((csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b0 && - instr__h4262[15:13] == 3'b0 && - nzimm10__h9495 != 10'd0) ? - instr__h9656 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d446) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d449 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b0 && - instr__h4262[11:7] != 5'd0 && - imm6__h8656 != 6'd0 || - csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b0 && - instr__h4262[11:7] == 5'd0 && - imm6__h8656 == 6'd0) ? - instr__h9047 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d448 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d450 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b011 && - instr__h4262[11:7] != 5'd0 && - instr__h4262[11:7] != 5'd2 && - imm6__h8656 != 6'd0) ? - instr__h8918 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d449 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d452 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b111) ? - instr__h8396 : - ((csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b010 && - instr__h4262[11:7] != 5'd0) ? - instr__h8734 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d450) ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d453 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b110) ? - instr__h8079 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d452 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d454 = - (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308 && - instr__h4262[6:2] == 5'd0) ? - instr__h8014 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d453 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d455 = - (csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302 && - instr__h4262[6:2] == 5'd0) ? - instr__h7898 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d454 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d456 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b001) ? - instr__h7508 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d455 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d457 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b01 && - instr__h4262[15:13] == 3'b101) ? - instr__h7165 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d456 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d458 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b0 && - instr__h4262[15:13] == 3'b110) ? - instr__h6936 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d457 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d459 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b0 && - instr__h4262[15:13] == 3'b010) ? - instr__h6741 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d458 ; - assign IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d460 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b10 && - instr__h4262[15:13] == 3'b110) ? - instr__h6549 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d459 ; - assign IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112 = - near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ; - assign IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723 = - ((rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) && - _theResult____h4264[31:20] == 12'b000100000010) ? - 4'd8 : - (rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_EQ_0_ETC___d721 ? - 4'd10 : - 4'd11) ; - assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 : - 2'd0 ; - assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 : - 2'd0 ; - assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 = - x_out_bypass_rd__h5976 == _theResult____h4264[19:15] ; - assign IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466 = - x_out_bypass_rd__h5976 == _theResult____h4264[24:20] ; - assign IF_stage2_rg_stage2_8_BITS_100_TO_96_48_EQ_0_7_ETC___d175 = - (stage2_rg_stage2[100:96] == 5'd0) ? - 2'd0 : - ((near_mem$dmem_valid && !near_mem$dmem_exc) ? 2'd2 : 2'd1) ; - assign IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115 = - stage2_mbox$valid ? 2'd2 : 2'd1 ; - assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564 = - (_theResult____h4264[14:12] != 3'b0 || - _theResult____h4264[6:0] == 7'b0110011 && - _theResult____h4264[30]) && - (_theResult____h4264[14:12] != 3'b0 || - _theResult____h4264[6:0] != 7'b0110011 || - !_theResult____h4264[30]) && - _theResult____h4264[14:12] != 3'b010 && - _theResult____h4264[14:12] != 3'b011 && - _theResult____h4264[14:12] != 3'b100 && - _theResult____h4264[14:12] != 3'b110 && - _theResult____h4264[14:12] != 3'b111 ; - assign NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 = - cur_verbosity__h2969 > 4'd1 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - (!stage1_rg_full || - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109) && - (!stage1_rg_full || - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd2 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd0) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1130 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd2 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd0) && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 || - !stage1_rg_full ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1163 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1165 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161) && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd2 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd0) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1168 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1165 && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 || - !stage1_rg_full) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1182 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) ; - assign NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d812 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd0 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd1 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd2 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd3 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd4 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd5 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd6 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd7 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd8 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd9 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd10 ; - assign NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d849 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 != - 3'd0 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 != - 3'd1 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 != - 3'd2 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 != - 3'd3 ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 = - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] != 2'b11) ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d210 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] == 2'b11) && - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] == 2'b11) ; - assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1090 = - !near_mem$imem_valid || - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == - 2'd1 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ; - assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101 = - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469 || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) ; - assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1109 = - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ; - assign NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469 = - !near_mem$imem_valid || - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d210 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == - 2'd1 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ; - assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878 = - { {20{theResult__264_BITS_31_TO_20__q17[11]}}, - theResult__264_BITS_31_TO_20__q17 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288 = - { {9{offset__h7112[11]}}, offset__h7112 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317 = - { {4{offset__h8023[8]}}, offset__h8023 } ; - assign _0_OR_0_OR_near_mem_imem_exc__85_OR_IF_IF_NOT_n_ETC___d1161 = - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633 ; - assign _theResult_____1_fst__h12702 = - (_theResult____h4264[14:12] == 3'b0 && - _theResult____h4264[6:0] == 7'b0110011 && - _theResult____h4264[30]) ? - rd_val___1__h12698 : - _theResult_____1_fst__h12709 ; - assign _theResult_____1_fst__h12737 = - rs1_val_bypassed__h4272 & _theResult___snd__h13835 ; - assign _theResult____h22269 = - (delta_CPI_instrs__h22268 == 64'd0) ? - delta_CPI_instrs___1__h22304 : - delta_CPI_instrs__h22268 ; - assign _theResult____h4264 = x_out_data_to_stage2_instr__h11596 ; - assign _theResult___fst__h6304 = - (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11) ? - instr_out___1__h6306 : - _theResult___fst__h6332 ; - assign _theResult___fst__h6332 = - (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11) ? - instr_out___1__h6334 : - near_mem$imem_instr ; - assign _theResult___snd__h13835 = - (_theResult____h4264[6:0] == 7'b0010011) ? - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878 : - rs2_val__h11697 ; - assign alu_outputs___1_addr__h11723 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 ? - branch_target__h11701 : - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869 ; - assign alu_outputs___1_addr__h11744 = - imem_rg_pc + - { {11{theResult__264_BIT_31_CONCAT_theResult__264_BI_ETC__q4[20]}}, - theResult__264_BIT_31_CONCAT_theResult__264_BI_ETC__q4 } ; - assign alu_outputs___1_addr__h11770 = - { alu_outputs___1_addr__h11965[31:1], 1'd0 } ; - assign alu_outputs___1_addr__h11965 = - rs1_val_bypassed__h4272 + - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d878 ; - assign alu_outputs___1_addr__h11986 = - rs1_val_bypassed__h4272 + - { {20{theResult__264_BITS_31_TO_25_CONCAT_theResult__ETC__q7[11]}}, - theResult__264_BITS_31_TO_25_CONCAT_theResult__ETC__q7 } ; - assign alu_outputs___1_exc_code__h12222 = - (_theResult____h4264[14:12] == 3'b0) ? - ((_theResult____h4264[11:7] == 5'd0 && - _theResult____h4264[19:15] == 5'd0) ? - CASE_theResult__264_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 : - 4'd2) : - 4'd2 ; - assign alu_outputs___1_val1__h11874 = - (_theResult____h4264[14:12] == 3'b001) ? - rd_val__h13731 : - (_theResult____h4264[30] ? rd_val__h13805 : rd_val__h13783) ; - assign alu_outputs___1_val1__h11912 = - (_theResult____h4264[14:12] == 3'b0 && - (_theResult____h4264[6:0] != 7'b0110011 || - !_theResult____h4264[30])) ? - rd_val___1__h12690 : - _theResult_____1_fst__h12702 ; - assign alu_outputs___1_val1__h11928 = - { _theResult____h4264[31:12], 12'h0 } ; - assign alu_outputs___1_val1__h11944 = - imem_rg_pc + alu_outputs___1_val1__h11928 ; - assign alu_outputs___1_val1__h12226 = - _theResult____h4264[14] ? - { 27'd0, _theResult____h4264[19:15] } : - rs1_val_bypassed__h4272 ; - assign alu_outputs___1_val1__h12247 = - { 25'd0, _theResult____h4264[31:25] } ; - assign branch_target__h11701 = - imem_rg_pc + - { {19{theResult__264_BIT_31_CONCAT_theResult__264_BI_ETC__q3[12]}}, - theResult__264_BIT_31_CONCAT_theResult__264_BI_ETC__q3 } ; - assign cpi__h22271 = x__h22270 / 64'd10 ; - assign cpifrac__h22272 = x__h22270 % 64'd10 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1083 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1079 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1080 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd2 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd0 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1094 = - csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1083 || - (csr_regfile_interrupt_pending_rg_cur_priv_3_07_ETC___d1088 || - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1090 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - stage1_rg_full ; - assign csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1273 = - delta_CPI_cycles__h22267 * 64'd10 ; - assign csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d302 = - csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b10 && - instr__h4262[15:12] == 4'b1000 && - instr__h4262[11:7] != 5'd0 ; - assign csr_regfile_read_misa__0_BIT_2_12_AND_IF_near__ETC___d308 = - csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b10 && - instr__h4262[15:12] == 4'b1001 && - instr__h4262[11:7] != 5'd0 ; - assign cur_verbosity__h2969 = - (csr_regfile$read_csr_minstret < cfg_logdelay) ? - 4'd0 : - cfg_verbosity ; - assign data_to_stage2_addr__h11591 = x_out_data_to_stage2_addr__h11599 ; - assign delta_CPI_cycles__h22267 = - csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ; - assign delta_CPI_instrs___1__h22304 = delta_CPI_instrs__h22268 + 64'd1 ; - assign delta_CPI_instrs__h22268 = - csr_regfile$read_csr_minstret - rg_start_CPI_instrs ; - assign fall_through_pc__h11555 = - imem_rg_pc + - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 ? - 32'd4 : - 32'd2) ; - assign gpr_regfile_RDY_server_reset_request_put__031__ETC___d1043 = - gpr_regfile$RDY_server_reset_request_put && - near_mem$RDY_server_reset_request_put && - csr_regfile$RDY_server_reset_request_put && - f_reset_reqs$EMPTY_N && - stage1_f_reset_reqs$FULL_N && - stage2_f_reset_reqs$FULL_N && - stage3_f_reset_reqs$FULL_N ; - assign imm12__h10038 = { 7'b0100000, instr__h4262[6:2] } ; - assign imm12__h6405 = { 4'd0, offset__h6175 } ; - assign imm12__h6742 = { 5'd0, offset__h6684 } ; - assign imm12__h8658 = { {6{imm6__h8656[5]}}, imm6__h8656 } ; - assign imm12__h9282 = { {2{nzimm10__h9280[9]}}, nzimm10__h9280 } ; - assign imm12__h9497 = { 2'd0, nzimm10__h9495 } ; - assign imm12__h9693 = { 7'b0, instr__h4262[6:2] } ; - assign imm20__h8786 = { {14{imm6__h8656[5]}}, imm6__h8656 } ; - assign imm6__h8656 = { instr__h4262[12], instr__h4262[6:2] } ; - assign instr___1__h6137 = - (csr_regfile$read_misa[2] && instr__h4262[1:0] == 2'b10 && - instr__h4262[11:7] != 5'd0 && - instr__h4262[15:13] == 3'b010) ? - instr__h6404 : - IF_csr_regfile_read_misa__0_BIT_2_12_AND_IF_ne_ETC___d460 ; - assign instr__h10022 = - { imm12__h9693, rs1__h6743, 3'b101, rs1__h6743, 7'b0010011 } ; - assign instr__h10215 = - { imm12__h10038, rs1__h6743, 3'b101, rs1__h6743, 7'b0010011 } ; - assign instr__h10332 = - { imm12__h8658, rs1__h6743, 3'b111, rs1__h6743, 7'b0010011 } ; - assign instr__h10510 = - { 7'b0, - instr__h4262[6:2], - 8'd0, - instr__h4262[11:7], - 7'b0110011 } ; - assign instr__h10629 = - { 7'b0, - instr__h4262[6:2], - instr__h4262[11:7], - 3'b0, - instr__h4262[11:7], - 7'b0110011 } ; - assign instr__h10724 = - { 7'b0, rd__h6744, rs1__h6743, 3'b111, rs1__h6743, 7'b0110011 } ; - assign instr__h10860 = - { 7'b0, rd__h6744, rs1__h6743, 3'b110, rs1__h6743, 7'b0110011 } ; - assign instr__h10996 = - { 7'b0, rd__h6744, rs1__h6743, 3'b100, rs1__h6743, 7'b0110011 } ; - assign instr__h11132 = - { 7'b0100000, - rd__h6744, - rs1__h6743, - 3'b0, - rs1__h6743, - 7'b0110011 } ; - assign instr__h11470 = - { 12'b000000000001, - instr__h4262[11:7], - 3'b0, - instr__h4262[11:7], - 7'b1110011 } ; - assign instr__h4262 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 ? - instr_out___1__h6274 : - _theResult___fst__h6304 ; - assign instr__h6404 = - { imm12__h6405, 8'd18, instr__h4262[11:7], 7'b0000011 } ; - assign instr__h6549 = - { 4'd0, - instr__h4262[8:7], - instr__h4262[12], - instr__h4262[6:2], - 8'd18, - offset_BITS_4_TO_0___h6673, - 7'b0100011 } ; - assign instr__h6741 = - { imm12__h6742, rs1__h6743, 3'b010, rd__h6744, 7'b0000011 } ; - assign instr__h6936 = - { 5'd0, - instr__h4262[5], - instr__h4262[12], - rd__h6744, - rs1__h6743, - 3'b010, - offset_BITS_4_TO_0___h7104, - 7'b0100011 } ; - assign instr__h7165 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[19:12], - 12'd111 } ; - assign instr__h7508 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d288[19:12], - 12'd239 } ; - assign instr__h7898 = { 12'd0, instr__h4262[11:7], 15'd103 } ; - assign instr__h8014 = { 12'd0, instr__h4262[11:7], 15'd231 } ; - assign instr__h8079 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[10:5], - 5'd0, - rs1__h6743, - 3'b0, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[11], - 7'b1100011 } ; - assign instr__h8396 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[10:5], - 5'd0, - rs1__h6743, - 3'b001, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[11], - 7'b1100011 } ; - assign instr__h8734 = - { imm12__h8658, 8'd0, instr__h4262[11:7], 7'b0010011 } ; - assign instr__h8918 = { imm20__h8786, instr__h4262[11:7], 7'b0110111 } ; - assign instr__h9047 = - { imm12__h8658, - instr__h4262[11:7], - 3'b0, - instr__h4262[11:7], - 7'b0010011 } ; - assign instr__h9484 = - { imm12__h9282, - instr__h4262[11:7], - 3'b0, - instr__h4262[11:7], - 7'b0010011 } ; - assign instr__h9656 = { imm12__h9497, 8'd16, rd__h6744, 7'b0010011 } ; - assign instr__h9829 = - { imm12__h9693, - instr__h4262[11:7], - 3'b001, - instr__h4262[11:7], - 7'b0010011 } ; - assign instr_out___1__h6274 = - { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ; - assign instr_out___1__h6306 = { 16'b0, near_mem$imem_instr[15:0] } ; - assign instr_out___1__h6334 = { 16'b0, near_mem$imem_instr[31:16] } ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d949 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd0 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d952 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd1 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d955 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd2 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d958 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd3 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d961 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd4 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d964 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd5 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d967 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd6 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d970 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd7 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d973 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd8 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d976 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd9 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d979 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == - 4'd10 ; - assign near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d982 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd0 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd1 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd2 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd3 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd4 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd5 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd6 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd7 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd8 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd9 && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 != - 4'd10 ; - assign near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 = - near_mem$imem_pc[31:2] == imem_rg_pc[31:2] ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] == 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d478 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11 || - near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 = - near_mem$imem_pc == next_pc___1__h13377 ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1079 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d197 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != - 2'd1 || - !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 && - !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d478 && - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != - 2'd1 || - !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464 && - !IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d622 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d633) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) ; - assign next_pc___1__h13377 = imem_rg_pc + 32'd2 ; - assign next_pc__h13375 = imem_rg_pc + 32'd4 ; - assign nzimm10__h9280 = - { instr__h4262[12], - instr__h4262[4:3], - instr__h4262[5], - instr__h4262[2], - instr__h4262[6], - 4'b0 } ; - assign nzimm10__h9495 = - { instr__h4262[10:7], - instr__h4262[12:11], - instr__h4262[5], - instr__h4262[6], - 2'b0 } ; - assign offset_BITS_4_TO_0___h6673 = { instr__h4262[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h7104 = - { instr__h4262[11:10], instr__h4262[6], 2'b0 } ; - assign offset__h6175 = - { instr__h4262[3:2], - instr__h4262[12], - instr__h4262[6:4], - 2'b0 } ; - assign offset__h6684 = - { instr__h4262[5], instr__h4262[12:10], instr__h4262[6], 2'b0 } ; - assign offset__h7112 = - { instr__h4262[12], - instr__h4262[8], - instr__h4262[10:9], - instr__h4262[6], - instr__h4262[7], - instr__h4262[2], - instr__h4262[11], - instr__h4262[5:3], - 1'b0 } ; - assign offset__h8023 = - { instr__h4262[12], - instr__h4262[6:5], - instr__h4262[2], - instr__h4262[11:10], - instr__h4262[4:3], - 1'b0 } ; - assign output_stage2___1_bypass_rd_val__h5965 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - ((stage2_rg_stage2[100:96] == 5'd0) ? - stage2_rg_stage2[63:32] : - near_mem$dmem_word64[31:0]) : - stage2_rg_stage2[63:32] ; - assign rd__h6744 = { 2'b01, instr__h4262[4:2] } ; - assign rd_val___1__h12690 = - rs1_val_bypassed__h4272 + _theResult___snd__h13835 ; - assign rd_val___1__h12698 = - rs1_val_bypassed__h4272 - _theResult___snd__h13835 ; - assign rd_val___1__h12705 = - ((rs1_val_bypassed__h4272 ^ 32'h80000000) < - (_theResult___snd__h13835 ^ 32'h80000000)) ? - 32'd1 : - 32'd0 ; - assign rd_val___1__h12712 = - (rs1_val_bypassed__h4272 < _theResult___snd__h13835) ? - 32'd1 : - 32'd0 ; - assign rd_val___1__h12719 = - rs1_val_bypassed__h4272 ^ _theResult___snd__h13835 ; - assign rd_val___1__h12726 = - rs1_val_bypassed__h4272 | _theResult___snd__h13835 ; - assign rd_val__h11512 = - (stage3_rg_full && stage3_rg_stage3[37] && - stage3_rg_stage3[36:32] == _theResult____h4264[24:20]) ? - stage3_rg_stage3[31:0] : - gpr_regfile$read_rs2 ; - assign rd_val__h13731 = rs1_val_bypassed__h4272 << shamt__h11859 ; - assign rd_val__h13783 = rs1_val_bypassed__h4272 >> shamt__h11859 ; - assign rd_val__h13805 = - rs1_val_bypassed__h4272 >> shamt__h11859 | - ~(32'hFFFFFFFF >> shamt__h11859) & - {32{rs1_val_bypassed__h4272[31]}} ; - assign rd_val__h6089 = - (stage3_rg_full && stage3_rg_stage3[37] && - stage3_rg_stage3[36:32] == _theResult____h4264[19:15]) ? - stage3_rg_stage3[31:0] : - gpr_regfile$read_rs1 ; - assign rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_EQ_0_ETC___d721 = - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] || - rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) && - _theResult____h4264[31:20] == 12'b000100000101 ; - assign rg_state_2_EQ_3_096_AND_NOT_csr_regfile_interr_ETC___d1185 = - rg_state == 4'd3 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1182 && - !stage3_rg_full && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == - 2'd0 ; - assign rg_state_2_EQ_3_096_AND_stage3_rg_full_8_OR_NO_ETC___d1115 = - rg_state == 4'd3 && - (stage3_rg_full || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd0 || - stage1_rg_full) && - (stage3_rg_full || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd3) && - (stage3_rg_full || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd0 || - !stage1_rg_full || - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d1101) && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 || - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != - 2'd0 || - stage3_rg_full) ; - assign rs1__h6743 = { 2'b01, instr__h4262[9:7] } ; - assign rs1_val__h17215 = - (x_out_data_to_stage2_instr__h11596[14:12] == 3'b001) ? - x_out_data_to_stage2_val1__h11600 : - { 27'd0, x_out_data_to_stage2_instr__h11596[19:15] } ; - assign rs1_val_bypassed__h4272 = - (_theResult____h4264[19:15] == 5'd0) ? 32'd0 : val__h6091 ; - assign rs2_val__h11697 = - (_theResult____h4264[24:20] == 5'd0) ? 32'd0 : val__h11514 ; - assign shamt__h11859 = - (_theResult____h4264[6:0] == 7'b0010011) ? - _theResult____h4264[24:20] : - rs2_val__h11697[4:0] ; - assign stage2_f_reset_rsps_i_notEmpty__052_AND_stage3_ETC___d1061 = - stage2_f_reset_rsps$EMPTY_N && stage3_f_reset_rsps$EMPTY_N && - f_reset_rsps$FULL_N && - (!rg_run_on_reset || - !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) ; - assign theResult__264_BITS_31_TO_20__q17 = _theResult____h4264[31:20] ; - assign theResult__264_BITS_31_TO_25_CONCAT_theResult__ETC__q7 = - { _theResult____h4264[31:25], _theResult____h4264[11:7] } ; - assign theResult__264_BIT_31_CONCAT_theResult__264_BI_ETC__q3 = - { _theResult____h4264[31], - _theResult____h4264[7], - _theResult____h4264[30:25], - _theResult____h4264[11:8], - 1'b0 } ; - assign theResult__264_BIT_31_CONCAT_theResult__264_BI_ETC__q4 = - { _theResult____h4264[31], - _theResult____h4264[19:12], - _theResult____h4264[20], - _theResult____h4264[30:21], - 1'b0 } ; - assign trap_info_tval__h13214 = - (_theResult____h4264[6:0] != 7'b1101111 && - _theResult____h4264[6:0] != 7'b1100111 && - (_theResult____h4264[6:0] != 7'b1110011 || - _theResult____h4264[14:12] != 3'b0 || - _theResult____h4264[11:7] != 5'd0 || - _theResult____h4264[19:15] != 5'd0 || - _theResult____h4264[31:20] != 12'b0 && - _theResult____h4264[31:20] != 12'b000000000001)) ? - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_OR__ETC___d476 ? - _theResult____h4264 : - { 16'd0, instr__h4262[15:0] }) : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 ; - assign val__h11514 = - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == - 2'd2 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d466) ? - x_out_bypass_rd_val__h5977 : - rd_val__h11512 ; - assign val__h6091 = - (IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == - 2'd2 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d464) ? - x_out_bypass_rd_val__h5977 : - rd_val__h6089 ; - assign value__h13265 = - near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h13214 ; - assign x__h22270 = - csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1273[63:0] / - _theResult____h22269 ; - assign x_out_data_to_stage2_instr__h11596 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_97_ETC___d205 ? - instr___1__h6137 : - instr__h4262 ; - assign x_out_data_to_stage2_rd__h11598 = - (_theResult____h4264[6:0] == 7'b1100011) ? - 5'd0 : - _theResult____h4264[11:7] ; - assign x_out_data_to_stage2_val2__h11601 = - (_theResult____h4264[6:0] == 7'b1100011) ? - branch_target__h11701 : - rs2_val__h11697 ; - assign x_out_next_pc__h11568 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682 ? - data_to_stage2_addr__h11591 : - fall_through_pc__h11555 ; - assign x_out_trap_info_exc_code__h13217 = - near_mem$imem_exc ? - near_mem$imem_exc_code : - alu_outputs_exc_code__h12265 ; - assign y__h18006 = ~rs1_val__h17705 ; - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[103:101]) - 3'd0, 3'd1, 3'd4: - x_out_data_to_stage3_rd__h5625 = stage2_rg_stage2[100:96]; - 3'd2: x_out_data_to_stage3_rd__h5625 = 5'd0; - default: x_out_data_to_stage3_rd__h5625 = stage2_rg_stage2[100:96]; - endcase - end - always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64) - begin - case (stage2_rg_stage2[103:101]) - 3'd0: x_out_data_to_stage3_rd_val__h5626 = stage2_rg_stage2[63:32]; - 3'd1, 3'd4: - x_out_data_to_stage3_rd_val__h5626 = near_mem$dmem_word64[31:0]; - default: x_out_data_to_stage3_rd_val__h5626 = stage2_mbox$word; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[103:101]) - 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h5976 = stage2_rg_stage2[100:96]; - default: x_out_bypass_rd__h5976 = stage2_rg_stage2[100:96]; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$word or output_stage2___1_bypass_rd_val__h5965) - begin - case (stage2_rg_stage2[103:101]) - 3'd0: x_out_bypass_rd_val__h5977 = stage2_rg_stage2[63:32]; - 3'd1, 3'd4: - x_out_bypass_rd_val__h5977 = output_stage2___1_bypass_rd_val__h5965; - default: x_out_bypass_rd_val__h5977 = stage2_mbox$word; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115 or - IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112) - begin - case (stage2_rg_stage2[103:101]) - 3'd0: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 = 2'd2; - 3'd1, 3'd2, 3'd4: - CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 = - IF_near_mem_dmem_valid__09_THEN_IF_near_mem_dm_ETC___d112; - default: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q1 = - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[103:101]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132 = - !near_mem$dmem_valid || near_mem$dmem_exc; - default: IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132 = - !stage2_mbox$valid; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[103:101]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141 = - near_mem$dmem_valid && !near_mem$dmem_exc; - default: IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141 = - stage2_mbox$valid; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115 or - IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176) - begin - case (stage2_rg_stage2[103:101]) - 3'd0: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 = 2'd2; - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 = - IF_NOT_near_mem_dmem_valid__09_28_OR_NOT_near__ETC___d176; - 3'd2: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 = 2'd0; - default: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q2 = - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_3_5_ETC___d115; - endcase - end - always@(rg_cur_priv) - begin - case (rg_cur_priv) - 2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd8; - 2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd9; - default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd11; - endcase - end - always@(_theResult____h4264 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q5) - begin - case (_theResult____h4264[31:20]) - 12'b0: - CASE_theResult__264_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = - CASE_rg_cur_priv_0b0_8_0b1_9_11__q5; - 12'b000000000001: - CASE_theResult__264_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd3; - default: CASE_theResult__264_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd2; - endcase - end - always@(_theResult____h4264 or alu_outputs___1_exc_code__h12222) - begin - case (_theResult____h4264[6:0]) - 7'b0000011, - 7'b0001111, - 7'b0010011, - 7'b0010111, - 7'b0100011, - 7'b0110011, - 7'b0110111, - 7'b1100011: - alu_outputs_exc_code__h12265 = 4'd2; - 7'b1100111, 7'b1101111: alu_outputs_exc_code__h12265 = 4'd0; - 7'b1110011: - alu_outputs_exc_code__h12265 = alu_outputs___1_exc_code__h12222; - default: alu_outputs_exc_code__h12265 = 4'd2; - endcase - end - always@(_theResult____h4264 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525) - begin - case (_theResult____h4264[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - _theResult____h4264[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527; - endcase - end - always@(_theResult____h4264 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525) - begin - case (_theResult____h4264[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d523; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d525; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 = - _theResult____h4264[14:12] == 3'b111 && - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d527; - endcase - end - always@(_theResult____h4264) - begin - case (_theResult____h4264[6:0]) - 7'b0000011: - CASE_theResult__264_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4264[14:12] != 3'b0 && - _theResult____h4264[14:12] != 3'b100 && - _theResult____h4264[14:12] != 3'b001 && - _theResult____h4264[14:12] != 3'b101 && - _theResult____h4264[14:12] != 3'b010; - 7'b0100011: - CASE_theResult__264_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4264[14:12] != 3'b0 && - _theResult____h4264[14:12] != 3'b001 && - _theResult____h4264[14:12] != 3'b010; - default: CASE_theResult__264_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4264[6:0] != 7'b0101111 || - _theResult____h4264[31:27] != 5'b00010 && - _theResult____h4264[31:27] != 5'b00011 && - _theResult____h4264[31:27] != 5'b0 && - _theResult____h4264[31:27] != 5'b00001 && - _theResult____h4264[31:27] != 5'b01100 && - _theResult____h4264[31:27] != 5'b01000 && - _theResult____h4264[31:27] != 5'b00100 && - _theResult____h4264[31:27] != 5'b10000 && - _theResult____h4264[31:27] != 5'b11000 && - _theResult____h4264[31:27] != 5'b10100 && - _theResult____h4264[31:27] != 5'b11100 || - _theResult____h4264[14:12] != 3'b010; - endcase - end - always@(_theResult____h4264 or - CASE_theResult__264_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 or - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564) - begin - case (_theResult____h4264[6:0]) - 7'b0010011, 7'b0110011: - CASE_theResult__264_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d564; - default: CASE_theResult__264_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = - _theResult____h4264[6:0] != 7'b0110111 && - _theResult____h4264[6:0] != 7'b0010111 && - CASE_theResult__264_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8; - endcase - end - always@(_theResult____h4264) - begin - case (_theResult____h4264[6:0]) - 7'b0000011: - CASE_theResult__264_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4264[14:12] == 3'b0 || - _theResult____h4264[14:12] == 3'b100 || - _theResult____h4264[14:12] == 3'b001 || - _theResult____h4264[14:12] == 3'b101 || - _theResult____h4264[14:12] == 3'b010; - 7'b0100011: - CASE_theResult__264_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4264[14:12] == 3'b0 || - _theResult____h4264[14:12] == 3'b001 || - _theResult____h4264[14:12] == 3'b010; - default: CASE_theResult__264_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4264[6:0] == 7'b0101111 && - (_theResult____h4264[31:27] == 5'b00010 || - _theResult____h4264[31:27] == 5'b00011 || - _theResult____h4264[31:27] == 5'b0 || - _theResult____h4264[31:27] == 5'b00001 || - _theResult____h4264[31:27] == 5'b01100 || - _theResult____h4264[31:27] == 5'b01000 || - _theResult____h4264[31:27] == 5'b00100 || - _theResult____h4264[31:27] == 5'b10000 || - _theResult____h4264[31:27] == 5'b11000 || - _theResult____h4264[31:27] == 5'b10100 || - _theResult____h4264[31:27] == 5'b11100) && - _theResult____h4264[14:12] == 3'b010; - endcase - end - always@(_theResult____h4264 or - CASE_theResult__264_BITS_6_TO_0_0b11_theResult_ETC__q10 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653) - begin - case (_theResult____h4264[6:0]) - 7'b0010011, 7'b0110011: - CASE_theResult__264_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d653; - default: CASE_theResult__264_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = - _theResult____h4264[6:0] == 7'b0110111 || - _theResult____h4264[6:0] == 7'b0010111 || - CASE_theResult__264_BITS_6_TO_0_0b11_theResult_ETC__q10; - endcase - end - always@(_theResult____h4264 or - rg_cur_priv or - IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723) - begin - case (_theResult____h4264[31:20]) - 12'b0, 12'b000000000001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725 = 4'd11; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725 = - (rg_cur_priv == 2'b11 && - _theResult____h4264[31:20] == 12'b001100000010) ? - 4'd7 : - IF_rg_cur_priv_3_EQ_0b11_04_OR_rg_cur_priv_3_E_ETC___d723; - endcase - end - always@(_theResult____h4264) - begin - case (_theResult____h4264[14:12]) - 3'b0, 3'b001, 3'b010, 3'b100, 3'b101: - CASE_theResult__264_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = 4'd0; - default: CASE_theResult__264_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = - 4'd11; - endcase - end - always@(_theResult____h4264) - begin - case (_theResult____h4264[14:12]) - 3'b0: CASE_theResult__264_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd4; - 3'b001: CASE_theResult__264_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd5; - default: CASE_theResult__264_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd11; - endcase - end - always@(_theResult____h4264) - begin - case (_theResult____h4264[14:12]) - 3'b0, 3'b001, 3'b010: - CASE_theResult__264_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd0; - default: CASE_theResult__264_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = - 4'd11; - endcase - end - always@(_theResult____h4264 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725) - begin - case (_theResult____h4264[14:12]) - 3'b0: - CASE_theResult__264_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = - (_theResult____h4264[11:7] == 5'd0 && - _theResult____h4264[19:15] == 5'd0) ? - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d725 : - 4'd11; - 3'b001, 3'b101: - CASE_theResult__264_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd2; - 3'b010, 3'b011, 3'b110, 3'b111: - CASE_theResult__264_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd3; - 3'd4: CASE_theResult__264_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd11; - endcase - end - always@(_theResult____h4264 or - CASE_theResult__264_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 or - CASE_theResult__264_BITS_14_TO_12_0b0_4_0b1_5_11__q13 or - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690 or - CASE_theResult__264_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 or - CASE_theResult__264_BITS_14_TO_12_0b0_IF_theRe_ETC__q15) - begin - case (_theResult____h4264[6:0]) - 7'b0000011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - CASE_theResult__264_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12; - 7'b0001111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - CASE_theResult__264_BITS_14_TO_12_0b0_4_0b1_5_11__q13; - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d690; - 7'b0010111, 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = 4'd0; - 7'b0100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - CASE_theResult__264_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - ((_theResult____h4264[31:27] == 5'b00010 || - _theResult____h4264[31:27] == 5'b00011 || - _theResult____h4264[31:27] == 5'b0 || - _theResult____h4264[31:27] == 5'b00001 || - _theResult____h4264[31:27] == 5'b01100 || - _theResult____h4264[31:27] == 5'b01000 || - _theResult____h4264[31:27] == 5'b00100 || - _theResult____h4264[31:27] == 5'b10000 || - _theResult____h4264[31:27] == 5'b11000 || - _theResult____h4264[31:27] == 5'b10100 || - _theResult____h4264[31:27] == 5'b11100) && - _theResult____h4264[14:12] == 3'b010) ? - 4'd0 : - 4'd11; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - CASE_theResult__264_BITS_14_TO_12_0b0_IF_theRe_ETC__q15; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 = - 4'd11; - endcase - end - always@(_theResult____h4264 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534) - begin - case (_theResult____h4264[6:0]) - 7'b1100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 = - (_theResult____h4264[14:12] != 3'b0 && - _theResult____h4264[14:12] != 3'b001 && - _theResult____h4264[14:12] != 3'b100 && - _theResult____h4264[14:12] != 3'b101 && - _theResult____h4264[14:12] != 3'b110 && - _theResult____h4264[14:12] != 3'b111) ? - 4'd11 : - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d534 ? - 4'd1 : - 4'd0); - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 = 4'd1; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d744 = - (_theResult____h4264[6:0] == 7'b0110011 && - _theResult____h4264[31:25] == 7'b0000001) ? - 4'd0 : - (((_theResult____h4264[6:0] == 7'b0010011 || - _theResult____h4264[6:0] == 7'b0110011) && - (_theResult____h4264[14:12] == 3'b001 || - _theResult____h4264[14:12] == 3'b101)) ? - (_theResult____h4264[25] ? 4'd11 : 4'd0) : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d740); - endcase - end - always@(_theResult____h4264) - begin - case (_theResult____h4264[6:0]) - 7'b0000011: - CASE_theResult__264_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd1; - 7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111: - CASE_theResult__264_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd0; - 7'b0100011: - CASE_theResult__264_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd2; - default: CASE_theResult__264_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd4; - endcase - end - always@(_theResult____h4264 or - CASE_theResult__264_BITS_6_TO_0_0b11_1_0b10011_ETC__q16) - begin - case (_theResult____h4264[6:0]) - 7'b1100011, 7'b1100111, 7'b1101111: - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 = 3'd0; - default: IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 = - (_theResult____h4264[6:0] == 7'b0110011 && - _theResult____h4264[31:25] == 7'b0000001) ? - 3'd3 : - CASE_theResult__264_BITS_6_TO_0_0b11_1_0b10011_ETC__q16; - endcase - end - always@(_theResult____h4264 or - _theResult_____1_fst__h12737 or - rd_val___1__h12705 or - rd_val___1__h12712 or rd_val___1__h12719 or rd_val___1__h12726) - begin - case (_theResult____h4264[14:12]) - 3'b010: _theResult_____1_fst__h12709 = rd_val___1__h12705; - 3'b011: _theResult_____1_fst__h12709 = rd_val___1__h12712; - 3'b100: _theResult_____1_fst__h12709 = rd_val___1__h12719; - 3'b110: _theResult_____1_fst__h12709 = rd_val___1__h12726; - default: _theResult_____1_fst__h12709 = _theResult_____1_fst__h12737; - endcase - end - always@(_theResult____h4264 or - rs1_val_bypassed__h4272 or - alu_outputs___1_addr__h11965 or - alu_outputs___1_addr__h11986 or - alu_outputs___1_addr__h11723 or - alu_outputs___1_addr__h11770 or alu_outputs___1_addr__h11744) - begin - case (_theResult____h4264[6:0]) - 7'b0000011: - x_out_data_to_stage2_addr__h11599 = alu_outputs___1_addr__h11965; - 7'b0100011: - x_out_data_to_stage2_addr__h11599 = alu_outputs___1_addr__h11986; - 7'b1100011: - x_out_data_to_stage2_addr__h11599 = alu_outputs___1_addr__h11723; - 7'b1100111: - x_out_data_to_stage2_addr__h11599 = alu_outputs___1_addr__h11770; - 7'b1101111: - x_out_data_to_stage2_addr__h11599 = alu_outputs___1_addr__h11744; - default: x_out_data_to_stage2_addr__h11599 = rs1_val_bypassed__h4272; - endcase - end - always@(_theResult____h4264 or imem_rg_pc or data_to_stage2_addr__h11591) - begin - case (_theResult____h4264[6:0]) - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - data_to_stage2_addr__h11591; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - (_theResult____h4264[6:0] == 7'b1110011 && - _theResult____h4264[14:12] == 3'b0 && - _theResult____h4264[11:7] == 5'd0 && - _theResult____h4264[19:15] == 5'd0 && - _theResult____h4264[31:20] == 12'b000000000001) ? - imem_rg_pc : - 32'd0; - endcase - end - always@(_theResult____h4264 or - alu_outputs___1_val1__h12247 or - alu_outputs___1_val1__h11912 or - alu_outputs___1_val1__h11944 or - alu_outputs___1_val1__h11928 or alu_outputs___1_val1__h12226) - begin - case (_theResult____h4264[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 = - alu_outputs___1_val1__h11912; - 7'b0010111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 = - alu_outputs___1_val1__h11944; - 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 = - alu_outputs___1_val1__h11928; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 = - alu_outputs___1_val1__h12226; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d936 = - alu_outputs___1_val1__h12247; - endcase - end - always@(_theResult____h4264 or - rs1_val_bypassed__h4272 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869) - begin - case (_theResult____h4264[6:0]) - 7'b1100111, 7'b1101111: - x_out_data_to_stage2_val1__h11600 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d869; - default: x_out_data_to_stage2_val1__h11600 = - (_theResult____h4264[6:0] == 7'b0110011 && - _theResult____h4264[31:25] == 7'b0000001) ? - rs1_val_bypassed__h4272 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d937; - endcase - end - always@(x_out_data_to_stage2_instr__h11596 or - x_out_data_to_stage2_val1__h11600) - begin - case (x_out_data_to_stage2_instr__h11596[14:12]) - 3'b010, 3'b011: rs1_val__h17705 = x_out_data_to_stage2_val1__h11600; - default: rs1_val__h17705 = - { 27'd0, x_out_data_to_stage2_instr__h11596[19:15] }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0; - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11; - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_logdelay$EN) - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN; - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_cur_priv$EN) - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN; - if (rg_run_on_reset$EN) - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (stage1_rg_full$EN) - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN; - if (stage2_rg_full$EN) - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN; - if (stage2_rg_resetting$EN) - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY - stage2_rg_resetting$D_IN; - if (stage3_rg_full$EN) - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN; - end - if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN; - if (imem_rg_instr_15_0$EN) - imem_rg_instr_15_0 <= `BSV_ASSIGNMENT_DELAY imem_rg_instr_15_0$D_IN; - if (imem_rg_mstatus_MXR$EN) - imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN; - if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN; - if (imem_rg_priv$EN) - imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN; - if (imem_rg_satp$EN) - imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN; - if (imem_rg_sstatus_SUM$EN) - imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN; - if (imem_rg_tval$EN) - imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_start_CPI_cycles$EN) - rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN; - if (rg_start_CPI_instrs$EN) - rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN; - if (stage2_rg_stage2$EN) - stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN; - if (stage3_rg_stage3$EN) - stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_logdelay = 64'hAAAAAAAAAAAAAAAA; - cfg_verbosity = 4'hA; - imem_rg_f3 = 3'h2; - imem_rg_instr_15_0 = 16'hAAAA; - imem_rg_mstatus_MXR = 1'h0; - imem_rg_pc = 32'hAAAAAAAA; - imem_rg_priv = 2'h2; - imem_rg_satp = 32'hAAAAAAAA; - imem_rg_sstatus_SUM = 1'h0; - imem_rg_tval = 32'hAAAAAAAA; - rg_cur_priv = 2'h2; - rg_mstatus_MXR = 1'h0; - rg_next_pc = 32'hAAAAAAAA; - rg_run_on_reset = 1'h0; - rg_sstatus_SUM = 1'h0; - rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA; - rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - stage1_rg_full = 1'h0; - stage2_rg_full = 1'h0; - stage2_rg_resetting = 1'h0; - stage2_rg_stage2 = 170'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - stage3_rg_full = 1'h0; - stage3_rg_stage3 = 104'hAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - rg_cur_priv, - csr_regfile$read_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write("MStatus{", - "sd:%0d", - csr_regfile$read_mstatus[14:13] == 2'h3 || - csr_regfile$read_mstatus[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2) - $write(" sxl:%0d uxl:%0d", 2'd0, 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tsr:%0d", csr_regfile$read_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tw:%0d", csr_regfile$read_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tvm:%0d", csr_regfile$read_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mxr:%0d", csr_regfile$read_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" sum:%0d", csr_regfile$read_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mprv:%0d", csr_regfile$read_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" xs:%0d", csr_regfile$read_mstatus[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" fs:%0d", csr_regfile$read_mstatus[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mpp:%0d", csr_regfile$read_mstatus[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" spp:%0d", csr_regfile$read_mstatus[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" pies:%0d_%0d%0d", - csr_regfile$read_mstatus[7], - csr_regfile$read_mstatus[5], - csr_regfile$read_mstatus[4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" ies:%0d_%0d%0d", - csr_regfile$read_mstatus[3], - csr_regfile$read_mstatus[1], - csr_regfile$read_mstatus[0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_full || !stage3_rg_stage3[37])) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full && stage3_rg_stage3[37]) - $write("Rd %0d ", - stage3_rg_stage3[36:32], - "rd_val:%h", - stage3_rg_stage3[31:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage2: pc 0x%08h instr 0x%08h priv %0d", - stage2_rg_stage2[167:136], - stage2_rg_stage2[135:104], - stage2_rg_stage2[169:168]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write("Output_Stage2", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[167:136]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("Output_Stage2", " NONPIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write("Output_Stage2", " PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[167:136], - stage2_rg_stage2[135:104], - stage2_rg_stage2[169:168]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3 && - stage2_rg_stage2[103:101] != 3'd0 && - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3 && - (stage2_rg_stage2[103:101] == 3'd0 || - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h5625, - x_out_data_to_stage3_rd_val__h5626); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", stage2_rg_stage2[167:136]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", near_mem$dmem_exc_code); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", stage2_rg_stage2[95:64], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", stage2_rg_stage2[167:136]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", near_mem$dmem_exc_code); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd3) - $write("'h%h", stage2_rg_stage2[95:64], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd1 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == 2'd0) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != 2'd0) - $write("Rd %0d ", x_out_bypass_rd__h5976); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != 2'd0 && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d180 != 2'd1) - $write("rd_val:%h", x_out_bypass_rd_val__h5977); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage1: pc 0x%08h instr 0x%08h priv %0d", - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write("Output_Stage1", " BUSY pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write("Output_Stage1", " NONPIPE: pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write("Output_Stage1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) - $write("Output_Stage1", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(" PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd0) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd1) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd2) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd3) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd4) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd5) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd6) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd7) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd8) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd9) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d746 == 4'd10) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d812) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n", - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(" op_stage2:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd0) - $write("OP_Stage2_ALU"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd1) - $write("OP_Stage2_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd2) - $write("OP_Stage2_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d680 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d682) && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d825 == 3'd3) - $write("OP_Stage2_M"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - NOT_near_mem_imem_exc__85_38_AND_IF_IF_NOT_nea_ETC___d849) - $write("OP_Stage2_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(" rd:%0d\n", x_out_data_to_stage2_rd__h11598); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(" addr:%h val1:%h val2:%h}", - x_out_data_to_stage2_addr__h11599, - x_out_data_to_stage2_val1__h11600, - x_out_data_to_stage2_val2__h11601); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d949) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d952) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d955) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d958) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d961) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d964) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d967) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d970) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d973) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d976) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d979) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484 && - near_mem_imem_exc__85_OR_IF_IF_NOT_near_mem_im_ETC___d982) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write("'h%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write("'h%h", x_out_trap_info_exc_code__h13217); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d636) - $write("'h%h", value__h13265, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d685) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_96_OR_NOT_near_mem_ime_ETC___d469) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d484) - $write(" next_pc 0x%08h", x_out_next_pc__h11568); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[167:136], - stage2_rg_stage2[135:104], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h2969 != 4'd0) - $display(" mcause:0x%0h epc 0x%0h tval:0x%0h new pc 0x%0h, new mstatus 0x%0h", - csr_regfile$csr_trap_actions[33:2], - stage2_rg_stage2[167:136], - stage2_rg_stage2[95:64], - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[65:34]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h11596[19:15], - rs1_val__h17215, - x_out_data_to_stage2_instr__h11596[31:20], - csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h11596[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h11596[19:15], - rs1_val__h17215, - x_out_data_to_stage2_instr__h11596[31:20], - x_out_data_to_stage2_instr__h11596[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_S_or_C", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h11596[19:15], - rs1_val__h17705, - x_out_data_to_stage2_instr__h11596[31:20], - csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h11596[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h11596[19:15], - rs1_val__h17705, - x_out_data_to_stage2_instr__h11596[31:20], - x_out_data_to_stage2_instr__h11596[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h11568); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d pc:%0x cur_priv:%0d", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - x_out_next_pc__h11568, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2969 != 4'd0) - $display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d", - csr_regfile$csr_ret_actions[65:34], - csr_regfile$csr_ret_actions[31:0], - csr_regfile$csr_ret_actions[33:32]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_stage1_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h2969 != 4'd0) - $display(" WFI resume"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_from_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270) - $display("%0d: CPU.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x", - csr_regfile$read_csr_mcycle, - csr_regfile$csr_trap_actions[97:66], - x_out_data_to_stage2_instr__h11596); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270) - $display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'", - cpi__h22271, - cpifrac__h22272, - delta_CPI_cycles__h22267, - _theResult____h22269); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_94_95_OR_NOT_near_mem_im_ETC___d1270) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2969 != 4'd0) - $display("%0d: CPU.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", - csr_regfile$read_csr_mcycle, - rg_cur_priv, - csr_regfile$csr_trap_actions[33:2], - imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2969 != 4'd0) - $display(" tval:0x%0h new pc:0x%0h new mstatus:0x%0h", - value__h13265, - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[65:34]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_trap_fetch && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h11596, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2969 != 4'd0) - $display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", - csr_regfile$read_csr_mcycle, - imem_rg_pc, - csr_regfile$csr_trap_actions[97:66], - csr_regfile$csr_trap_actions[1:0], - csr_regfile$csr_trap_actions[65:34]); - if (WILL_FIRE_RL_imem_rl_assert_fail) - $display("ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False"); - if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", - soc_map$m_pc_reset_value[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h", - csr_regfile$read_csr_mcycle, - soc_map$m_pc_reset_value[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[36:32], - stage3_rg_stage3[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" S3.enq: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[167:136], - stage2_rg_stage2[135:104], - stage2_rg_stage2[169:168]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - stage2_rg_stage2[103:101] != 3'd0 && - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d132) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - (stage2_rg_stage2[103:101] == 3'd0 || - IF_stage2_rg_stage2_8_BITS_103_TO_101_9_EQ_1_1_ETC___d141)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h5625, - x_out_data_to_stage3_rd_val__h5626); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_7_THEN_IF_stage2_rg_stage2_8_ETC___d118 == 2'd2 && - cur_verbosity__h2969 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[167:136], - stage2_rg_stage2[135:104], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1133 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage2.enq (Data_Stage1_to_Stage2)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1112 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1154 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h11568); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $write("CPU: Bluespec RISC-V Piccolo v3.0"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) $display(" (RV32)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h2969 != 4'd0) - $display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle); - end - // synopsys translate_on -endmodule // mkCPU - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v deleted file mode 100644 index df80ca60..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v +++ /dev/null @@ -1,141 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 32 -// fav_write O 32 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 32 -// EN_reset I 1 -// EN_fav_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIE(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [31 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [31 : 0] fav_write_wordxl; - input EN_fav_write; - output [31 : 0] fav_write; - - // signals for module outputs - wire [31 : 0] fav_write, fv_read; - - // register rg_mie - reg [11 : 0] rg_mie; - wire [11 : 0] rg_mie$D_IN; - wire rg_mie$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_write, - CAN_FIRE_reset, - WILL_FIRE_fav_write, - WILL_FIRE_reset; - - // remaining internal signals - wire [11 : 0] mie__h88; - wire seie__h119, ssie__h113, stie__h116, ueie__h118, usie__h112, utie__h115; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 20'd0, rg_mie } ; - - // actionvalue method fav_write - assign fav_write = { 20'd0, mie__h88 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // register rg_mie - assign rg_mie$D_IN = EN_fav_write ? mie__h88 : 12'd0 ; - assign rg_mie$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign mie__h88 = - { fav_write_wordxl[11], - 1'b0, - seie__h119, - ueie__h118, - fav_write_wordxl[7], - 1'b0, - stie__h116, - utie__h115, - fav_write_wordxl[3], - 1'b0, - ssie__h113, - usie__h112 } ; - assign seie__h119 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssie__h113 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign stie__h116 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueie__h118 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign usie__h112 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign utie__h115 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_mie = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIE - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v deleted file mode 100644 index fb4847d7..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v +++ /dev/null @@ -1,289 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 32 -// fav_write O 32 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 32 -// m_external_interrupt_req_req I 1 reg -// s_external_interrupt_req_req I 1 reg -// software_interrupt_req_req I 1 reg -// timer_interrupt_req_req I 1 reg -// EN_reset I 1 -// EN_fav_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIP(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - m_external_interrupt_req_req, - - s_external_interrupt_req_req, - - software_interrupt_req_req, - - timer_interrupt_req_req); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [31 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [31 : 0] fav_write_wordxl; - input EN_fav_write; - output [31 : 0] fav_write; - - // action method m_external_interrupt_req - input m_external_interrupt_req_req; - - // action method s_external_interrupt_req - input s_external_interrupt_req_req; - - // action method software_interrupt_req - input software_interrupt_req_req; - - // action method timer_interrupt_req - input timer_interrupt_req_req; - - // signals for module outputs - wire [31 : 0] fav_write, fv_read; - - // register rg_meip - reg rg_meip; - wire rg_meip$D_IN, rg_meip$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_seip - reg rg_seip; - wire rg_seip$D_IN, rg_seip$EN; - - // register rg_ssip - reg rg_ssip; - wire rg_ssip$D_IN, rg_ssip$EN; - - // register rg_stip - reg rg_stip; - wire rg_stip$D_IN, rg_stip$EN; - - // register rg_ueip - reg rg_ueip; - wire rg_ueip$D_IN, rg_ueip$EN; - - // register rg_usip - reg rg_usip; - wire rg_usip$D_IN, rg_usip$EN; - - // register rg_utip - reg rg_utip; - wire rg_utip$D_IN, rg_utip$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_write, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_reset, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_fav_write, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_reset, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // remaining internal signals - wire [11 : 0] new_mip__h524, new_mip__h942; - wire seip__h558, ssip__h562, stip__h560, ueip__h559, usip__h563, utip__h561; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 20'd0, new_mip__h524 } ; - - // actionvalue method fav_write - assign fav_write = { 20'd0, new_mip__h942 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // register rg_meip - assign rg_meip$D_IN = m_external_interrupt_req_req ; - assign rg_meip$EN = 1'b1 ; - - // register rg_msip - assign rg_msip$D_IN = software_interrupt_req_req ; - assign rg_msip$EN = 1'b1 ; - - // register rg_mtip - assign rg_mtip$D_IN = timer_interrupt_req_req ; - assign rg_mtip$EN = 1'b1 ; - - // register rg_seip - assign rg_seip$D_IN = s_external_interrupt_req_req ; - assign rg_seip$EN = 1'b1 ; - - // register rg_ssip - assign rg_ssip$D_IN = !EN_reset && ssip__h562 ; - assign rg_ssip$EN = EN_fav_write || EN_reset ; - - // register rg_stip - assign rg_stip$D_IN = !EN_reset && stip__h560 ; - assign rg_stip$EN = EN_fav_write || EN_reset ; - - // register rg_ueip - assign rg_ueip$D_IN = !EN_reset && ueip__h559 ; - assign rg_ueip$EN = EN_fav_write || EN_reset ; - - // register rg_usip - assign rg_usip$D_IN = !EN_reset && usip__h563 ; - assign rg_usip$EN = EN_fav_write || EN_reset ; - - // register rg_utip - assign rg_utip$D_IN = !EN_reset && utip__h561 ; - assign rg_utip$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign new_mip__h524 = - { rg_meip, - 1'b0, - rg_seip, - rg_ueip, - rg_mtip, - 1'b0, - rg_stip, - rg_utip, - rg_msip, - 1'b0, - rg_ssip, - rg_usip } ; - assign new_mip__h942 = - { rg_meip, - 1'b0, - seip__h558, - ueip__h559, - rg_mtip, - 1'b0, - stip__h560, - utip__h561, - rg_msip, - 1'b0, - ssip__h562, - usip__h563 } ; - assign seip__h558 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssip__h562 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign stip__h560 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueip__h559 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign usip__h563 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign utip__h561 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN; - if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN; - if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN; - if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN; - if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN; - if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_meip = 1'h0; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_seip = 1'h0; - rg_ssip = 1'h0; - rg_stip = 1'h0; - rg_ueip = 1'h0; - rg_usip = 1'h0; - rg_utip = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIP - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v deleted file mode 100644 index ea518626..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v +++ /dev/null @@ -1,2419 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_csr O 33 -// read_csr_port2 O 33 -// mav_read_csr O 33 -// mav_csr_write O 32 -// read_misa O 28 const -// read_mstatus O 32 reg -// read_ustatus O 32 -// read_satp O 32 const -// csr_trap_actions O 98 -// RDY_csr_trap_actions O 1 const -// csr_ret_actions O 66 -// RDY_csr_ret_actions O 1 const -// read_csr_minstret O 64 reg -// read_csr_mcycle O 64 reg -// read_csr_mtime O 64 reg -// access_permitted_1 O 1 -// access_permitted_2 O 1 -// csr_counter_read_fault O 1 -// csr_mip_read O 32 -// interrupt_pending O 5 -// wfi_resume O 1 -// nmi_pending O 1 reg -// RDY_debug O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// read_csr_csr_addr I 12 -// read_csr_port2_csr_addr I 12 -// mav_read_csr_csr_addr I 12 -// mav_csr_write_csr_addr I 12 -// mav_csr_write_word I 32 -// csr_trap_actions_from_priv I 2 -// csr_trap_actions_pc I 32 -// csr_trap_actions_nmi I 1 -// csr_trap_actions_interrupt I 1 -// csr_trap_actions_exc_code I 4 -// csr_trap_actions_xtval I 32 -// csr_ret_actions_from_priv I 2 -// access_permitted_1_priv I 2 -// access_permitted_1_csr_addr I 12 -// access_permitted_1_read_not_write I 1 -// access_permitted_2_priv I 2 -// access_permitted_2_csr_addr I 12 -// access_permitted_2_read_not_write I 1 -// csr_counter_read_fault_priv I 2 -// csr_counter_read_fault_csr_addr I 12 -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// interrupt_pending_cur_priv I 2 -// nmi_req_set_not_clear I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_csr_minstret_incr I 1 -// EN_debug I 1 unused -// EN_mav_read_csr I 1 unused -// EN_mav_csr_write I 1 -// EN_csr_trap_actions I 1 -// EN_csr_ret_actions I 1 -// -// Combinational paths from inputs to outputs: -// read_csr_csr_addr -> read_csr -// read_csr_port2_csr_addr -> read_csr_port2 -// (access_permitted_1_priv, -// access_permitted_1_csr_addr, -// access_permitted_1_read_not_write) -> access_permitted_1 -// (access_permitted_2_priv, -// access_permitted_2_csr_addr, -// access_permitted_2_read_not_write) -> access_permitted_2 -// (csr_counter_read_fault_priv, -// csr_counter_read_fault_csr_addr) -> csr_counter_read_fault -// interrupt_pending_cur_priv -> interrupt_pending -// mav_read_csr_csr_addr -> mav_read_csr -// (mav_csr_write_csr_addr, -// mav_csr_write_word, -// EN_mav_csr_write) -> mav_csr_write -// (csr_trap_actions_from_priv, -// csr_trap_actions_nmi, -// csr_trap_actions_interrupt, -// csr_trap_actions_exc_code) -> csr_trap_actions -// csr_ret_actions_from_priv -> csr_ret_actions -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_csr_csr_addr, - read_csr, - - read_csr_port2_csr_addr, - read_csr_port2, - - mav_read_csr_csr_addr, - EN_mav_read_csr, - mav_read_csr, - - mav_csr_write_csr_addr, - mav_csr_write_word, - EN_mav_csr_write, - mav_csr_write, - - read_misa, - - read_mstatus, - - read_ustatus, - - read_satp, - - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_nmi, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval, - EN_csr_trap_actions, - csr_trap_actions, - RDY_csr_trap_actions, - - csr_ret_actions_from_priv, - EN_csr_ret_actions, - csr_ret_actions, - RDY_csr_ret_actions, - - read_csr_minstret, - - EN_csr_minstret_incr, - - read_csr_mcycle, - - read_csr_mtime, - - access_permitted_1_priv, - access_permitted_1_csr_addr, - access_permitted_1_read_not_write, - access_permitted_1, - - access_permitted_2_priv, - access_permitted_2_csr_addr, - access_permitted_2_read_not_write, - access_permitted_2, - - csr_counter_read_fault_priv, - csr_counter_read_fault_csr_addr, - csr_counter_read_fault, - - csr_mip_read, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - interrupt_pending_cur_priv, - interrupt_pending, - - wfi_resume, - - nmi_req_set_not_clear, - - nmi_pending, - - EN_debug, - RDY_debug); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_csr - input [11 : 0] read_csr_csr_addr; - output [32 : 0] read_csr; - - // value method read_csr_port2 - input [11 : 0] read_csr_port2_csr_addr; - output [32 : 0] read_csr_port2; - - // actionvalue method mav_read_csr - input [11 : 0] mav_read_csr_csr_addr; - input EN_mav_read_csr; - output [32 : 0] mav_read_csr; - - // actionvalue method mav_csr_write - input [11 : 0] mav_csr_write_csr_addr; - input [31 : 0] mav_csr_write_word; - input EN_mav_csr_write; - output [31 : 0] mav_csr_write; - - // value method read_misa - output [27 : 0] read_misa; - - // value method read_mstatus - output [31 : 0] read_mstatus; - - // value method read_ustatus - output [31 : 0] read_ustatus; - - // value method read_satp - output [31 : 0] read_satp; - - // actionvalue method csr_trap_actions - input [1 : 0] csr_trap_actions_from_priv; - input [31 : 0] csr_trap_actions_pc; - input csr_trap_actions_nmi; - input csr_trap_actions_interrupt; - input [3 : 0] csr_trap_actions_exc_code; - input [31 : 0] csr_trap_actions_xtval; - input EN_csr_trap_actions; - output [97 : 0] csr_trap_actions; - output RDY_csr_trap_actions; - - // actionvalue method csr_ret_actions - input [1 : 0] csr_ret_actions_from_priv; - input EN_csr_ret_actions; - output [65 : 0] csr_ret_actions; - output RDY_csr_ret_actions; - - // value method read_csr_minstret - output [63 : 0] read_csr_minstret; - - // action method csr_minstret_incr - input EN_csr_minstret_incr; - - // value method read_csr_mcycle - output [63 : 0] read_csr_mcycle; - - // value method read_csr_mtime - output [63 : 0] read_csr_mtime; - - // value method access_permitted_1 - input [1 : 0] access_permitted_1_priv; - input [11 : 0] access_permitted_1_csr_addr; - input access_permitted_1_read_not_write; - output access_permitted_1; - - // value method access_permitted_2 - input [1 : 0] access_permitted_2_priv; - input [11 : 0] access_permitted_2_csr_addr; - input access_permitted_2_read_not_write; - output access_permitted_2; - - // value method csr_counter_read_fault - input [1 : 0] csr_counter_read_fault_priv; - input [11 : 0] csr_counter_read_fault_csr_addr; - output csr_counter_read_fault; - - // value method csr_mip_read - output [31 : 0] csr_mip_read; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // value method interrupt_pending - input [1 : 0] interrupt_pending_cur_priv; - output [4 : 0] interrupt_pending; - - // value method wfi_resume - output wfi_resume; - - // action method nmi_req - input nmi_req_set_not_clear; - - // value method nmi_pending - output nmi_pending; - - // action method debug - input EN_debug; - output RDY_debug; - - // signals for module outputs - wire [97 : 0] csr_trap_actions; - wire [65 : 0] csr_ret_actions; - wire [63 : 0] read_csr_mcycle, read_csr_minstret, read_csr_mtime; - wire [32 : 0] mav_read_csr, read_csr, read_csr_port2; - wire [31 : 0] csr_mip_read, - mav_csr_write, - read_mstatus, - read_satp, - read_ustatus; - wire [27 : 0] read_misa; - wire [4 : 0] interrupt_pending; - wire RDY_csr_ret_actions, - RDY_csr_trap_actions, - RDY_debug, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - access_permitted_1, - access_permitted_2, - csr_counter_read_fault, - nmi_pending, - wfi_resume; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register csr_mstatus_rg_mstatus - reg [31 : 0] csr_mstatus_rg_mstatus; - reg [31 : 0] csr_mstatus_rg_mstatus$D_IN; - wire csr_mstatus_rg_mstatus$EN; - - // register rg_dcsr - reg [31 : 0] rg_dcsr; - wire [31 : 0] rg_dcsr$D_IN; - wire rg_dcsr$EN; - - // register rg_dpc - reg [31 : 0] rg_dpc; - wire [31 : 0] rg_dpc$D_IN; - wire rg_dpc$EN; - - // register rg_dscratch0 - reg [31 : 0] rg_dscratch0; - wire [31 : 0] rg_dscratch0$D_IN; - wire rg_dscratch0$EN; - - // register rg_dscratch1 - reg [31 : 0] rg_dscratch1; - wire [31 : 0] rg_dscratch1$D_IN; - wire rg_dscratch1$EN; - - // register rg_mcause - reg [4 : 0] rg_mcause; - reg [4 : 0] rg_mcause$D_IN; - wire rg_mcause$EN; - - // register rg_mcounteren - reg [2 : 0] rg_mcounteren; - wire [2 : 0] rg_mcounteren$D_IN; - wire rg_mcounteren$EN; - - // register rg_mcycle - reg [63 : 0] rg_mcycle; - wire [63 : 0] rg_mcycle$D_IN; - wire rg_mcycle$EN; - - // register rg_mepc - reg [31 : 0] rg_mepc; - wire [31 : 0] rg_mepc$D_IN; - wire rg_mepc$EN; - - // register rg_minstret - reg [63 : 0] rg_minstret; - wire [63 : 0] rg_minstret$D_IN; - wire rg_minstret$EN; - - // register rg_mscratch - reg [31 : 0] rg_mscratch; - wire [31 : 0] rg_mscratch$D_IN; - wire rg_mscratch$EN; - - // register rg_mtval - reg [31 : 0] rg_mtval; - wire [31 : 0] rg_mtval$D_IN; - wire rg_mtval$EN; - - // register rg_mtvec - reg [30 : 0] rg_mtvec; - wire [30 : 0] rg_mtvec$D_IN; - wire rg_mtvec$EN; - - // register rg_nmi - reg rg_nmi; - wire rg_nmi$D_IN, rg_nmi$EN; - - // register rg_nmi_vector - reg [31 : 0] rg_nmi_vector; - wire [31 : 0] rg_nmi_vector$D_IN; - wire rg_nmi_vector$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_tdata1 - reg [31 : 0] rg_tdata1; - wire [31 : 0] rg_tdata1$D_IN; - wire rg_tdata1$EN; - - // register rg_tdata2 - reg [31 : 0] rg_tdata2; - wire [31 : 0] rg_tdata2$D_IN; - wire rg_tdata2$EN; - - // register rg_tdata3 - reg [31 : 0] rg_tdata3; - wire [31 : 0] rg_tdata3$D_IN; - wire rg_tdata3$EN; - - // register rg_tselect - reg [31 : 0] rg_tselect; - wire [31 : 0] rg_tselect$D_IN; - wire rg_tselect$EN; - - // ports of submodule csr_mie - wire [31 : 0] csr_mie$fav_write, csr_mie$fav_write_wordxl, csr_mie$fv_read; - wire [27 : 0] csr_mie$fav_write_misa; - wire csr_mie$EN_fav_write, csr_mie$EN_reset; - - // ports of submodule csr_mip - wire [31 : 0] csr_mip$fav_write, csr_mip$fav_write_wordxl, csr_mip$fv_read; - wire [27 : 0] csr_mip$fav_write_misa; - wire csr_mip$EN_fav_write, - csr_mip$EN_reset, - csr_mip$m_external_interrupt_req_req, - csr_mip$s_external_interrupt_req_req, - csr_mip$software_interrupt_req_req, - csr_mip$timer_interrupt_req_req; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mtvec_reset_value, - soc_map$m_nmivec_reset_value; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_mcycle_incr, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_upd_minstret_csrrx, - CAN_FIRE_RL_rl_upd_minstret_incr, - CAN_FIRE_csr_minstret_incr, - CAN_FIRE_csr_ret_actions, - CAN_FIRE_csr_trap_actions, - CAN_FIRE_debug, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_mav_csr_write, - CAN_FIRE_mav_read_csr, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_rl_mcycle_incr, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_upd_minstret_csrrx, - WILL_FIRE_RL_rl_upd_minstret_incr, - WILL_FIRE_csr_minstret_incr, - WILL_FIRE_csr_ret_actions, - WILL_FIRE_csr_trap_actions, - WILL_FIRE_debug, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_mav_csr_write, - WILL_FIRE_mav_read_csr, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_rg_minstret$write_1__VAL_1, - MUX_rg_minstret$write_1__VAL_2, - MUX_rw_minstret$wset_1__VAL_1; - wire [31 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_3; - wire [30 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; - wire [4 : 0] MUX_rg_mcause$write_1__VAL_2, MUX_rg_mcause$write_1__VAL_3; - wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_2, - MUX_rg_mcause$write_1__SEL_2, - MUX_rg_mcounteren$write_1__SEL_1, - MUX_rg_mepc$write_1__SEL_1, - MUX_rg_mtval$write_1__SEL_1, - MUX_rg_mtvec$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2, - MUX_rg_tdata1$write_1__SEL_1, - MUX_rw_minstret$wset_1__SEL_1; - - // remaining internal signals - reg [31 : 0] IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765, - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571, - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217, - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394; - wire [63 : 0] x__h5306, x__h5414; - wire [33 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1064; - wire [31 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046, - _theResult___fst__h8350, - _theResult___fst__h8551, - csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039, - exc_pc___1__h7435, - exc_pc__h7171, - exc_pc__h7382, - mask__h8371, - mask__h8388, - result__h5489, - v__h4656, - v__h4718, - v__h4874, - val__h8389, - vector_offset__h7383, - wordxl1__h4173, - x__h5982, - x__h8206, - x__h8207, - x__h8370, - x__h8383, - x__h8400, - y__h8384, - y__h8401; - wire [22 : 0] fixed_up_val_23__h4214, - fixed_up_val_23__h6610, - fixed_up_val_23__h8269; - wire [5 : 0] ie_from_x__h8334, pie_from_x__h8335; - wire [3 : 0] IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1366, - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1368, - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1370, - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1372, - exc_code__h8048; - wire [1 : 0] mpp__h7476, to_y__h8550; - wire NOT_access_permitted_1_csr_addr_ULT_0xC03_065__ETC___d1151, - NOT_access_permitted_2_csr_addr_ULT_0xC03_156__ETC___d1241, - NOT_cfg_verbosity_read__27_ULE_1_28___d729, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1330, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1335, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1340, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1345, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1350, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1355, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1360, - NOT_csr_trap_actions_nmi_93_AND_csr_trap_actio_ETC___d970, - NOT_mav_csr_write_csr_addr_ULT_0xB03_74_31_AND_ETC___d742, - b__h8387, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1284, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1289, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1294, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1299, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1304, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1309, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1314, - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1319, - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1021, - mav_csr_write_csr_addr_ULE_0x33F___d583, - mav_csr_write_csr_addr_ULE_0xB1F___d575, - mav_csr_write_csr_addr_ULE_0xB9F___d579, - mav_csr_write_csr_addr_ULT_0x323_82_OR_NOT_mav_ETC___d724, - mav_csr_write_csr_addr_ULT_0x323___d582, - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587, - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d638, - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d726, - mav_csr_write_csr_addr_ULT_0xB03___d574, - mav_csr_write_csr_addr_ULT_0xB83___d578; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_csr - assign read_csr = - { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hC83 && read_csr_csr_addr <= 12'hC9F || - read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'hB83 && read_csr_csr_addr <= 12'hB9F || - read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || - read_csr_csr_addr == 12'hC00 || - read_csr_csr_addr == 12'hC02 || - read_csr_csr_addr == 12'hC80 || - read_csr_csr_addr == 12'hC82 || - read_csr_csr_addr == 12'hF11 || - read_csr_csr_addr == 12'hF12 || - read_csr_csr_addr == 12'hF13 || - read_csr_csr_addr == 12'hF14 || - read_csr_csr_addr == 12'h300 || - read_csr_csr_addr == 12'h301 || - read_csr_csr_addr == 12'h304 || - read_csr_csr_addr == 12'h305 || - read_csr_csr_addr == 12'h306 || - read_csr_csr_addr == 12'h340 || - read_csr_csr_addr == 12'h341 || - read_csr_csr_addr == 12'h342 || - read_csr_csr_addr == 12'h343 || - read_csr_csr_addr == 12'h344 || - read_csr_csr_addr == 12'hB00 || - read_csr_csr_addr == 12'hB02 || - read_csr_csr_addr == 12'hB80 || - read_csr_csr_addr == 12'hB82 || - read_csr_csr_addr == 12'h7A0 || - read_csr_csr_addr == 12'h7A1 || - read_csr_csr_addr == 12'h7A2 || - read_csr_csr_addr == 12'h7A3, - (read_csr_csr_addr >= 12'hC03 && - read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hC83 && - read_csr_csr_addr <= 12'hC9F || - read_csr_csr_addr >= 12'hB03 && - read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'hB83 && - read_csr_csr_addr <= 12'hB9F || - read_csr_csr_addr >= 12'h323 && - read_csr_csr_addr <= 12'h33F) ? - 32'd0 : - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 } ; - - // value method read_csr_port2 - assign read_csr_port2 = - { read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hC83 && - read_csr_port2_csr_addr <= 12'hC9F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'hB83 && - read_csr_port2_csr_addr <= 12'hB9F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F || - read_csr_port2_csr_addr == 12'hC00 || - read_csr_port2_csr_addr == 12'hC02 || - read_csr_port2_csr_addr == 12'hC80 || - read_csr_port2_csr_addr == 12'hC82 || - read_csr_port2_csr_addr == 12'hF11 || - read_csr_port2_csr_addr == 12'hF12 || - read_csr_port2_csr_addr == 12'hF13 || - read_csr_port2_csr_addr == 12'hF14 || - read_csr_port2_csr_addr == 12'h300 || - read_csr_port2_csr_addr == 12'h301 || - read_csr_port2_csr_addr == 12'h304 || - read_csr_port2_csr_addr == 12'h305 || - read_csr_port2_csr_addr == 12'h306 || - read_csr_port2_csr_addr == 12'h340 || - read_csr_port2_csr_addr == 12'h341 || - read_csr_port2_csr_addr == 12'h342 || - read_csr_port2_csr_addr == 12'h343 || - read_csr_port2_csr_addr == 12'h344 || - read_csr_port2_csr_addr == 12'hB00 || - read_csr_port2_csr_addr == 12'hB02 || - read_csr_port2_csr_addr == 12'hB80 || - read_csr_port2_csr_addr == 12'hB82 || - read_csr_port2_csr_addr == 12'h7A0 || - read_csr_port2_csr_addr == 12'h7A1 || - read_csr_port2_csr_addr == 12'h7A2 || - read_csr_port2_csr_addr == 12'h7A3, - (read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hC83 && - read_csr_port2_csr_addr <= 12'hC9F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'hB83 && - read_csr_port2_csr_addr <= 12'hB9F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F) ? - 32'd0 : - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 } ; - - // actionvalue method mav_read_csr - assign mav_read_csr = - { mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hC83 && - mav_read_csr_csr_addr <= 12'hC9F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'hB83 && - mav_read_csr_csr_addr <= 12'hB9F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F || - mav_read_csr_csr_addr == 12'hC00 || - mav_read_csr_csr_addr == 12'hC02 || - mav_read_csr_csr_addr == 12'hC80 || - mav_read_csr_csr_addr == 12'hC82 || - mav_read_csr_csr_addr == 12'hF11 || - mav_read_csr_csr_addr == 12'hF12 || - mav_read_csr_csr_addr == 12'hF13 || - mav_read_csr_csr_addr == 12'hF14 || - mav_read_csr_csr_addr == 12'h300 || - mav_read_csr_csr_addr == 12'h301 || - mav_read_csr_csr_addr == 12'h304 || - mav_read_csr_csr_addr == 12'h305 || - mav_read_csr_csr_addr == 12'h306 || - mav_read_csr_csr_addr == 12'h340 || - mav_read_csr_csr_addr == 12'h341 || - mav_read_csr_csr_addr == 12'h342 || - mav_read_csr_csr_addr == 12'h343 || - mav_read_csr_csr_addr == 12'h344 || - mav_read_csr_csr_addr == 12'hB00 || - mav_read_csr_csr_addr == 12'hB02 || - mav_read_csr_csr_addr == 12'hB80 || - mav_read_csr_csr_addr == 12'hB82 || - mav_read_csr_csr_addr == 12'h7A0 || - mav_read_csr_csr_addr == 12'h7A1 || - mav_read_csr_csr_addr == 12'h7A2 || - mav_read_csr_csr_addr == 12'h7A3, - (mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hC83 && - mav_read_csr_csr_addr <= 12'hC9F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'hB83 && - mav_read_csr_csr_addr <= 12'hB9F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F) ? - 32'd0 : - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 } ; - assign CAN_FIRE_mav_read_csr = 1'd1 ; - assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; - - // actionvalue method mav_csr_write - assign mav_csr_write = - NOT_mav_csr_write_csr_addr_ULT_0xB03_74_31_AND_ETC___d742 ? - 32'd0 : - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 ; - assign CAN_FIRE_mav_csr_write = 1'd1 ; - assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; - - // value method read_misa - assign read_misa = 28'd68161797 ; - - // value method read_mstatus - assign read_mstatus = csr_mstatus_rg_mstatus ; - - // value method read_ustatus - assign read_ustatus = - { 27'd0, - csr_mstatus_rg_mstatus[4], - 3'd0, - csr_mstatus_rg_mstatus[0] } ; - - // value method read_satp - assign read_satp = 32'hAAAAAAAA ; - - // actionvalue method csr_trap_actions - assign csr_trap_actions = { x__h5982, x__h8206, x__h8207, 2'b11 } ; - assign RDY_csr_trap_actions = 1'd1 ; - assign CAN_FIRE_csr_trap_actions = 1'd1 ; - assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; - - // actionvalue method csr_ret_actions - assign csr_ret_actions = - { rg_mepc, - IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1064 } ; - assign RDY_csr_ret_actions = 1'd1 ; - assign CAN_FIRE_csr_ret_actions = 1'd1 ; - assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; - - // value method read_csr_minstret - assign read_csr_minstret = rg_minstret ; - - // action method csr_minstret_incr - assign CAN_FIRE_csr_minstret_incr = 1'd1 ; - assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; - - // value method read_csr_mcycle - assign read_csr_mcycle = rg_mcycle ; - - // value method read_csr_mtime - assign read_csr_mtime = rg_mcycle ; - - // value method access_permitted_1 - assign access_permitted_1 = - NOT_access_permitted_1_csr_addr_ULT_0xC03_065__ETC___d1151 && - (access_permitted_1_read_not_write || - access_permitted_1_csr_addr[11:10] != 2'b11) ; - - // value method access_permitted_2 - assign access_permitted_2 = - NOT_access_permitted_2_csr_addr_ULT_0xC03_156__ETC___d1241 && - (access_permitted_2_read_not_write || - access_permitted_2_csr_addr[11:10] != 2'b11) ; - - // value method csr_counter_read_fault - assign csr_counter_read_fault = - (csr_counter_read_fault_priv == 2'b01 || - csr_counter_read_fault_priv == 2'b0) && - (csr_counter_read_fault_csr_addr == 12'hC00 && - !rg_mcounteren[0] || - csr_counter_read_fault_csr_addr == 12'hC01 && - !rg_mcounteren[1] || - csr_counter_read_fault_csr_addr == 12'hC02 && - !rg_mcounteren[2] || - csr_counter_read_fault_csr_addr >= 12'hC03 && - csr_counter_read_fault_csr_addr <= 12'hC1F || - csr_counter_read_fault_csr_addr >= 12'hC83 && - csr_counter_read_fault_csr_addr <= 12'hC9F) ; - - // value method csr_mip_read - assign csr_mip_read = csr_mip$fv_read ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // value method interrupt_pending - assign interrupt_pending = - { csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1319, - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1360 ? - 4'd4 : - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1372 } ; - - // value method wfi_resume - assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 32'd0 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // value method nmi_pending - assign nmi_pending = rg_nmi ; - - // action method debug - assign RDY_debug = 1'd1 ; - assign CAN_FIRE_debug = 1'd1 ; - assign WILL_FIRE_debug = EN_debug ; - - // submodule csr_mie - mkCSR_MIE csr_mie(.CLK(CLK), - .RST_N(RST_N), - .fav_write_misa(csr_mie$fav_write_misa), - .fav_write_wordxl(csr_mie$fav_write_wordxl), - .EN_reset(csr_mie$EN_reset), - .EN_fav_write(csr_mie$EN_fav_write), - .fv_read(csr_mie$fv_read), - .fav_write(csr_mie$fav_write)); - - // submodule csr_mip - mkCSR_MIP csr_mip(.CLK(CLK), - .RST_N(RST_N), - .fav_write_misa(csr_mip$fav_write_misa), - .fav_write_wordxl(csr_mip$fav_write_wordxl), - .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), - .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), - .software_interrupt_req_req(csr_mip$software_interrupt_req_req), - .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), - .EN_reset(csr_mip$EN_reset), - .EN_fav_write(csr_mip$EN_fav_write), - .fv_read(csr_mip$fv_read), - .fav_write(csr_mip$fav_write)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), - .m_nmivec_reset_value(soc_map$m_nmivec_reset_value)); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = !rg_state ; - assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_mcycle_incr - assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; - assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; - - // rule RL_rl_upd_minstret_csrrx - assign CAN_FIRE_RL_rl_upd_minstret_csrrx = - MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; - assign WILL_FIRE_RL_rl_upd_minstret_csrrx = - CAN_FIRE_RL_rl_upd_minstret_csrrx ; - - // rule RL_rl_upd_minstret_incr - assign CAN_FIRE_RL_rl_upd_minstret_incr = - !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; - assign WILL_FIRE_RL_rl_upd_minstret_incr = - CAN_FIRE_RL_rl_upd_minstret_incr ; - - // inputs to muxes for submodule ports - assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h300 ; - assign MUX_rg_mcause$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h342 ; - assign MUX_rg_mcounteren$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h306 ; - assign MUX_rg_mepc$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h341 ; - assign MUX_rg_mtval$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h343 ; - assign MUX_rg_mtvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h305 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; - assign MUX_rg_tdata1$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h7A1 ; - assign MUX_rw_minstret$wset_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d638 && - (mav_csr_write_csr_addr == 12'hB02 || - mav_csr_write_csr_addr == 12'hB82) ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 = - { 9'd0, fixed_up_val_23__h8269 } ; - assign MUX_rg_mcause$write_1__VAL_2 = - { mav_csr_write_word[31], mav_csr_write_word[3:0] } ; - assign MUX_rg_mcause$write_1__VAL_3 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - exc_code__h8048 } ; - assign MUX_rg_minstret$write_1__VAL_1 = - MUX_rw_minstret$wset_1__SEL_1 ? - MUX_rw_minstret$wset_1__VAL_1 : - 64'd0 ; - assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; - assign MUX_rg_mtvec$write_1__VAL_1 = - { mav_csr_write_word[31:2], mav_csr_write_word[0] } ; - assign MUX_rg_mtvec$write_1__VAL_2 = - { soc_map$m_mtvec_reset_value[31:2], - soc_map$m_mtvec_reset_value[0] } ; - assign MUX_rw_minstret$wset_1__VAL_1 = - (mav_csr_write_csr_addr == 12'hB02) ? x__h5306 : x__h5414 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register csr_mstatus_rg_mstatus - always@(WILL_FIRE_RL_rl_reset_start or - MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 or - wordxl1__h4173 or - EN_csr_ret_actions or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 or - EN_csr_trap_actions or x__h8206) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: csr_mstatus_rg_mstatus$D_IN = 32'd0; - MUX_csr_mstatus_rg_mstatus$write_1__SEL_2: - csr_mstatus_rg_mstatus$D_IN = wordxl1__h4173; - EN_csr_ret_actions: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_3; - EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = x__h8206; - default: csr_mstatus_rg_mstatus$D_IN = - 32'hAAAAAAAA /* unspecified value */ ; - endcase - assign csr_mstatus_rg_mstatus$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h300 || - EN_csr_trap_actions || - EN_csr_ret_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_dcsr - assign rg_dcsr$D_IN = 32'h0 ; - assign rg_dcsr$EN = 1'b0 ; - - // register rg_dpc - assign rg_dpc$D_IN = 32'h0 ; - assign rg_dpc$EN = 1'b0 ; - - // register rg_dscratch0 - assign rg_dscratch0$D_IN = 32'h0 ; - assign rg_dscratch0$EN = 1'b0 ; - - // register rg_dscratch1 - assign rg_dscratch1$D_IN = 32'h0 ; - assign rg_dscratch1$EN = 1'b0 ; - - // register rg_mcause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_mcause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - EN_csr_trap_actions or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; - MUX_rg_mcause$write_1__SEL_2: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; - EN_csr_trap_actions: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_mcause$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h342 || - EN_csr_trap_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcounteren - assign rg_mcounteren$D_IN = - MUX_rg_mcounteren$write_1__SEL_1 ? - mav_csr_write_word[2:0] : - 3'd0 ; - assign rg_mcounteren$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h306 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcycle - assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; - assign rg_mcycle$EN = 1'd1 ; - - // register rg_mepc - assign rg_mepc$D_IN = - MUX_rg_mepc$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_pc ; - assign rg_mepc$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h341 || - EN_csr_trap_actions ; - - // register rg_minstret - assign rg_minstret$D_IN = - WILL_FIRE_RL_rl_upd_minstret_csrrx ? - MUX_rg_minstret$write_1__VAL_1 : - MUX_rg_minstret$write_1__VAL_2 ; - assign rg_minstret$EN = - WILL_FIRE_RL_rl_upd_minstret_csrrx || - WILL_FIRE_RL_rl_upd_minstret_incr ; - - // register rg_mscratch - assign rg_mscratch$D_IN = mav_csr_write_word ; - assign rg_mscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h340 ; - - // register rg_mtval - assign rg_mtval$D_IN = - MUX_rg_mtval$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_xtval ; - assign rg_mtval$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h343 || - EN_csr_trap_actions ; - - // register rg_mtvec - assign rg_mtvec$D_IN = - MUX_rg_mtvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_mtvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h305 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_nmi - assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ; - assign rg_nmi$EN = 1'b1 ; - - // register rg_nmi_vector - assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value[31:0] ; - assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_state - assign rg_state$D_IN = !EN_server_reset_request_put ; - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata1 - assign rg_tdata1$D_IN = - MUX_rg_tdata1$write_1__SEL_1 ? result__h5489 : 32'd0 ; - assign rg_tdata1$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h7A1 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata2 - assign rg_tdata2$D_IN = mav_csr_write_word ; - assign rg_tdata2$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h7A2 ; - - // register rg_tdata3 - assign rg_tdata3$D_IN = mav_csr_write_word ; - assign rg_tdata3$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h7A3 ; - - // register rg_tselect - assign rg_tselect$D_IN = 32'd0 ; - assign rg_tselect$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h7A0 || - WILL_FIRE_RL_rl_reset_start ; - - // submodule csr_mie - assign csr_mie$fav_write_misa = 28'd68161797 ; - assign csr_mie$fav_write_wordxl = mav_csr_write_word ; - assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mie$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h304 ; - - // submodule csr_mip - assign csr_mip$fav_write_misa = 28'd68161797 ; - assign csr_mip$fav_write_wordxl = mav_csr_write_word ; - assign csr_mip$m_external_interrupt_req_req = - m_external_interrupt_req_set_not_clear ; - assign csr_mip$s_external_interrupt_req_req = - s_external_interrupt_req_set_not_clear ; - assign csr_mip$software_interrupt_req_req = - software_interrupt_req_set_not_clear ; - assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; - assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mip$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 && - mav_csr_write_csr_addr == 12'h344 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1366 = - (!csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ? - 4'd3 : - 4'd11 ; - assign IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1368 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1335 ? - 4'd9 : - (NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1330 ? - 4'd7 : - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1366) ; - assign IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1370 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1345 ? - 4'd5 : - (NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1340 ? - 4'd1 : - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1368) ; - assign IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1372 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1355 ? - 4'd0 : - (NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1350 ? - 4'd8 : - IF_NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_N_ETC___d1370) ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046 = - (csr_ret_actions_from_priv == 2'b11) ? - _theResult___fst__h8350 : - _theResult___fst__h8551 ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1064 = - (csr_ret_actions_from_priv == 2'b11) ? - { csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[12:11], - _theResult___fst__h8350 } : - { to_y__h8550, _theResult___fst__h8551 } ; - assign NOT_access_permitted_1_csr_addr_ULT_0xC03_065__ETC___d1151 = - (access_permitted_1_csr_addr >= 12'hC03 && - access_permitted_1_csr_addr <= 12'hC1F || - access_permitted_1_csr_addr >= 12'hB03 && - access_permitted_1_csr_addr <= 12'hB1F || - access_permitted_1_csr_addr >= 12'hC83 && - access_permitted_1_csr_addr <= 12'hC9F || - access_permitted_1_csr_addr >= 12'hB83 && - access_permitted_1_csr_addr <= 12'hB9F || - access_permitted_1_csr_addr >= 12'h323 && - access_permitted_1_csr_addr <= 12'h33F || - access_permitted_1_csr_addr == 12'hC00 || - access_permitted_1_csr_addr == 12'hC02 || - access_permitted_1_csr_addr == 12'hC80 || - access_permitted_1_csr_addr == 12'hC81 || - access_permitted_1_csr_addr == 12'hC82 || - access_permitted_1_csr_addr == 12'hF11 || - access_permitted_1_csr_addr == 12'hF12 || - access_permitted_1_csr_addr == 12'hF13 || - access_permitted_1_csr_addr == 12'hF14 || - access_permitted_1_csr_addr == 12'h300 || - access_permitted_1_csr_addr == 12'h301 || - access_permitted_1_csr_addr == 12'h304 || - access_permitted_1_csr_addr == 12'h305 || - access_permitted_1_csr_addr == 12'h306 || - access_permitted_1_csr_addr == 12'h340 || - access_permitted_1_csr_addr == 12'h341 || - access_permitted_1_csr_addr == 12'h342 || - access_permitted_1_csr_addr == 12'h343 || - access_permitted_1_csr_addr == 12'h344 || - access_permitted_1_csr_addr == 12'hB00 || - access_permitted_1_csr_addr == 12'hB02 || - access_permitted_1_csr_addr == 12'hB80 || - access_permitted_1_csr_addr == 12'hB82 || - access_permitted_1_csr_addr == 12'h7A0 || - access_permitted_1_csr_addr == 12'h7A1 || - access_permitted_1_csr_addr == 12'h7A2 || - access_permitted_1_csr_addr == 12'h7A3) && - access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && - (access_permitted_1_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_access_permitted_2_csr_addr_ULT_0xC03_156__ETC___d1241 = - (access_permitted_2_csr_addr >= 12'hC03 && - access_permitted_2_csr_addr <= 12'hC1F || - access_permitted_2_csr_addr >= 12'hB03 && - access_permitted_2_csr_addr <= 12'hB1F || - access_permitted_2_csr_addr >= 12'hC83 && - access_permitted_2_csr_addr <= 12'hC9F || - access_permitted_2_csr_addr >= 12'hB83 && - access_permitted_2_csr_addr <= 12'hB9F || - access_permitted_2_csr_addr >= 12'h323 && - access_permitted_2_csr_addr <= 12'h33F || - access_permitted_2_csr_addr == 12'hC00 || - access_permitted_2_csr_addr == 12'hC02 || - access_permitted_2_csr_addr == 12'hC80 || - access_permitted_2_csr_addr == 12'hC81 || - access_permitted_2_csr_addr == 12'hC82 || - access_permitted_2_csr_addr == 12'hF11 || - access_permitted_2_csr_addr == 12'hF12 || - access_permitted_2_csr_addr == 12'hF13 || - access_permitted_2_csr_addr == 12'hF14 || - access_permitted_2_csr_addr == 12'h300 || - access_permitted_2_csr_addr == 12'h301 || - access_permitted_2_csr_addr == 12'h304 || - access_permitted_2_csr_addr == 12'h305 || - access_permitted_2_csr_addr == 12'h306 || - access_permitted_2_csr_addr == 12'h340 || - access_permitted_2_csr_addr == 12'h341 || - access_permitted_2_csr_addr == 12'h342 || - access_permitted_2_csr_addr == 12'h343 || - access_permitted_2_csr_addr == 12'h344 || - access_permitted_2_csr_addr == 12'hB00 || - access_permitted_2_csr_addr == 12'hB02 || - access_permitted_2_csr_addr == 12'hB80 || - access_permitted_2_csr_addr == 12'hB82 || - access_permitted_2_csr_addr == 12'h7A0 || - access_permitted_2_csr_addr == 12'h7A1 || - access_permitted_2_csr_addr == 12'h7A2 || - access_permitted_2_csr_addr == 12'h7A3) && - access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && - (access_permitted_2_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_cfg_verbosity_read__27_ULE_1_28___d729 = cfg_verbosity > 4'd1 ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1330 = - (!csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) && - (!csr_mip$fv_read[3] || !csr_mie$fv_read[3] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1335 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1330 && - (!csr_mip$fv_read[7] || !csr_mie$fv_read[7] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1340 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1335 && - (!csr_mip$fv_read[9] || !csr_mie$fv_read[9] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1345 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1340 && - (!csr_mip$fv_read[1] || !csr_mie$fv_read[1] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1350 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1345 && - (!csr_mip$fv_read[5] || !csr_mie$fv_read[5] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1355 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1350 && - (!csr_mip$fv_read[8] || !csr_mie$fv_read[8] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1360 = - NOT_csr_mip_fv_read__91_BIT_11_273_320_OR_NOT__ETC___d1355 && - (!csr_mip$fv_read[0] || !csr_mie$fv_read[0] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_trap_actions_nmi_93_AND_csr_trap_actio_ETC___d970 = - !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8048 != 4'd0 && - exc_code__h8048 != 4'd1 && - exc_code__h8048 != 4'd2 && - exc_code__h8048 != 4'd3 && - exc_code__h8048 != 4'd4 && - exc_code__h8048 != 4'd5 && - exc_code__h8048 != 4'd6 && - exc_code__h8048 != 4'd7 && - exc_code__h8048 != 4'd8 && - exc_code__h8048 != 4'd9 && - exc_code__h8048 != 4'd10 && - exc_code__h8048 != 4'd11 ; - assign NOT_mav_csr_write_csr_addr_ULT_0xB03_74_31_AND_ETC___d742 = - !mav_csr_write_csr_addr_ULT_0xB03___d574 && - mav_csr_write_csr_addr_ULE_0xB1F___d575 || - !mav_csr_write_csr_addr_ULT_0xB83___d578 && - mav_csr_write_csr_addr_ULE_0xB9F___d579 || - !mav_csr_write_csr_addr_ULT_0x323___d582 && - mav_csr_write_csr_addr_ULE_0x33F___d583 || - mav_csr_write_csr_addr == 12'hF11 || - mav_csr_write_csr_addr == 12'hF12 || - mav_csr_write_csr_addr == 12'hF13 || - mav_csr_write_csr_addr == 12'hF14 ; - assign _theResult___fst__h8350 = - { csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[31:13], - 2'd0, - csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[10:0] } ; - assign _theResult___fst__h8551 = - { csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[31:9], - 1'd0, - csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[7:0] } ; - assign b__h8387 = - csr_mstatus_rg_mstatus[{ 3'd1, csr_ret_actions_from_priv }] ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1284 = - csr_mip$fv_read[11] && csr_mie$fv_read[11] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) || - csr_mip$fv_read[3] && csr_mie$fv_read[3] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1289 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1284 || - csr_mip$fv_read[7] && csr_mie$fv_read[7] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1294 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1289 || - csr_mip$fv_read[9] && csr_mie$fv_read[9] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1299 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1294 || - csr_mip$fv_read[1] && csr_mie$fv_read[1] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1304 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1299 || - csr_mip$fv_read[5] && csr_mie$fv_read[5] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1309 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1304 || - csr_mip$fv_read[8] && csr_mie$fv_read[8] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1314 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1309 || - csr_mip$fv_read[0] && csr_mie$fv_read[0] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1319 = - csr_mip_fv_read__91_BIT_11_273_AND_csr_mie_fv__ETC___d1314 || - csr_mip$fv_read[4] && csr_mie$fv_read[4] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039 = - x__h8383 | mask__h8371 ; - assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1021 = - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 != 4'd0 && - exc_code__h8048 != 4'd1 && - exc_code__h8048 != 4'd2 && - exc_code__h8048 != 4'd3 && - exc_code__h8048 != 4'd4 && - exc_code__h8048 != 4'd5 && - exc_code__h8048 != 4'd6 && - exc_code__h8048 != 4'd7 && - exc_code__h8048 != 4'd8 && - exc_code__h8048 != 4'd9 && - exc_code__h8048 != 4'd11 && - exc_code__h8048 != 4'd12 && - exc_code__h8048 != 4'd13 && - exc_code__h8048 != 4'd15 ; - assign exc_code__h8048 = - csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; - assign exc_pc___1__h7435 = exc_pc__h7382 + vector_offset__h7383 ; - assign exc_pc__h7171 = { rg_mtvec[30:1], 2'd0 } ; - assign exc_pc__h7382 = - csr_trap_actions_nmi ? rg_nmi_vector : exc_pc__h7171 ; - assign fixed_up_val_23__h4214 = - { mav_csr_write_word[22:17], - 4'd0, - (mav_csr_write_word[12:11] == 2'b11) ? - mav_csr_write_word[12:11] : - 2'b0, - mav_csr_write_word[10:9], - 1'd0, - mav_csr_write_word[7:6], - 2'd0, - mav_csr_write_word[3:2], - 2'd0 } ; - assign fixed_up_val_23__h6610 = - { csr_mstatus_rg_mstatus[22:17], - 4'd0, - mpp__h7476, - csr_mstatus_rg_mstatus[10:9], - 1'd0, - csr_mstatus_rg_mstatus[3], - csr_mstatus_rg_mstatus[6], - 3'd0, - csr_mstatus_rg_mstatus[2], - 2'd0 } ; - assign fixed_up_val_23__h8269 = - { IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[22:17], - 4'd0, - (IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[12:11] == - 2'b11) ? - IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[12:11] : - 2'b0, - IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[10:9], - 1'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[7:6], - 2'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_025_THEN__ETC___d1046[3:2], - 2'd0 } ; - assign ie_from_x__h8334 = { 4'd0, csr_ret_actions_from_priv } ; - assign mask__h8371 = 32'd1 << pie_from_x__h8335 ; - assign mask__h8388 = 32'd1 << ie_from_x__h8334 ; - assign mav_csr_write_csr_addr_ULE_0x33F___d583 = - mav_csr_write_csr_addr <= 12'h33F ; - assign mav_csr_write_csr_addr_ULE_0xB1F___d575 = - mav_csr_write_csr_addr <= 12'hB1F ; - assign mav_csr_write_csr_addr_ULE_0xB9F___d579 = - mav_csr_write_csr_addr <= 12'hB9F ; - assign mav_csr_write_csr_addr_ULT_0x323_82_OR_NOT_mav_ETC___d724 = - (mav_csr_write_csr_addr_ULT_0x323___d582 || - !mav_csr_write_csr_addr_ULE_0x33F___d583) && - mav_csr_write_csr_addr != 12'hF11 && - mav_csr_write_csr_addr != 12'hF12 && - mav_csr_write_csr_addr != 12'hF13 && - mav_csr_write_csr_addr != 12'hF14 && - mav_csr_write_csr_addr != 12'h300 && - mav_csr_write_csr_addr != 12'h301 && - mav_csr_write_csr_addr != 12'h304 && - mav_csr_write_csr_addr != 12'h305 && - mav_csr_write_csr_addr != 12'h306 && - mav_csr_write_csr_addr != 12'h340 && - mav_csr_write_csr_addr != 12'h341 && - mav_csr_write_csr_addr != 12'h342 && - mav_csr_write_csr_addr != 12'h343 && - mav_csr_write_csr_addr != 12'h344 && - mav_csr_write_csr_addr != 12'hB00 && - mav_csr_write_csr_addr != 12'hB02 && - mav_csr_write_csr_addr != 12'hB80 && - mav_csr_write_csr_addr != 12'hB82 && - mav_csr_write_csr_addr != 12'h7A0 && - mav_csr_write_csr_addr != 12'h7A1 && - mav_csr_write_csr_addr != 12'h7A2 && - mav_csr_write_csr_addr != 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0x323___d582 = - mav_csr_write_csr_addr < 12'h323 ; - assign mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d587 = - (mav_csr_write_csr_addr_ULT_0xB03___d574 || - !mav_csr_write_csr_addr_ULE_0xB1F___d575) && - (mav_csr_write_csr_addr_ULT_0xB83___d578 || - !mav_csr_write_csr_addr_ULE_0xB9F___d579) && - (mav_csr_write_csr_addr_ULT_0x323___d582 || - !mav_csr_write_csr_addr_ULE_0x33F___d583) ; - assign mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d638 = - (mav_csr_write_csr_addr_ULT_0xB03___d574 || - !mav_csr_write_csr_addr_ULE_0xB1F___d575) && - (mav_csr_write_csr_addr_ULT_0xB83___d578 || - !mav_csr_write_csr_addr_ULE_0xB9F___d579) && - (mav_csr_write_csr_addr_ULT_0x323___d582 || - !mav_csr_write_csr_addr_ULE_0x33F___d583) && - mav_csr_write_csr_addr != 12'hF11 && - mav_csr_write_csr_addr != 12'hF12 && - mav_csr_write_csr_addr != 12'hF13 && - mav_csr_write_csr_addr != 12'hF14 ; - assign mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d726 = - (mav_csr_write_csr_addr_ULT_0xB03___d574 || - !mav_csr_write_csr_addr_ULE_0xB1F___d575) && - (mav_csr_write_csr_addr_ULT_0xB83___d578 || - !mav_csr_write_csr_addr_ULE_0xB9F___d579) && - mav_csr_write_csr_addr_ULT_0x323_82_OR_NOT_mav_ETC___d724 ; - assign mav_csr_write_csr_addr_ULT_0xB03___d574 = - mav_csr_write_csr_addr < 12'hB03 ; - assign mav_csr_write_csr_addr_ULT_0xB83___d578 = - mav_csr_write_csr_addr < 12'hB83 ; - assign mpp__h7476 = - (csr_trap_actions_from_priv == 2'b11) ? - csr_trap_actions_from_priv : - 2'b0 ; - assign pie_from_x__h8335 = { 4'd1, csr_ret_actions_from_priv } ; - assign result__h5489 = { 4'd0, mav_csr_write_word[27:0] } ; - assign to_y__h8550 = - { 1'b0, - csr_mstatus_rg_mstatus_76_AND_INV_1_SL_0_CONCA_ETC___d1039[8] } ; - assign v__h4656 = - { mav_csr_write_word[31:2], 1'b0, mav_csr_write_word[0] } ; - assign v__h4718 = { 29'd0, mav_csr_write_word[2:0] } ; - assign v__h4874 = - { mav_csr_write_word[31], 27'd0, mav_csr_write_word[3:0] } ; - assign val__h8389 = { 31'd0, b__h8387 } << ie_from_x__h8334 ; - assign vector_offset__h7383 = { 26'd0, csr_trap_actions_exc_code, 2'd0 } ; - assign wordxl1__h4173 = { 9'd0, fixed_up_val_23__h4214 } ; - assign x__h5306 = { rg_minstret[63:32], mav_csr_write_word } ; - assign x__h5414 = { mav_csr_write_word, rg_minstret[31:0] } ; - assign x__h5982 = - (csr_trap_actions_interrupt && !csr_trap_actions_nmi && - rg_mtvec[0]) ? - exc_pc___1__h7435 : - exc_pc__h7382 ; - assign x__h8206 = { 9'd0, fixed_up_val_23__h6610 } ; - assign x__h8207 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - 27'd0, - exc_code__h8048 } ; - assign x__h8370 = x__h8400 | val__h8389 ; - assign x__h8383 = x__h8370 & y__h8384 ; - assign x__h8400 = csr_mstatus_rg_mstatus & y__h8401 ; - assign y__h8384 = ~mask__h8371 ; - assign y__h8401 = ~mask__h8388 ; - always@(read_csr_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_csr_addr) - 12'h300: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - 32'd1074794757; - 12'h304: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_mscratch; - 12'h341: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = rg_mepc; - 12'h342: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_mtval; - 12'h344: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_tselect; - 12'h7A1: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_tdata1; - 12'h7A2: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_minstret[63:32]; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = 32'd0; - default: IF_read_csr_csr_addr_EQ_0xC00_9_THEN_rg_mcycle_ETC___d217 = - rg_tdata3; - endcase - end - always@(read_csr_port2_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_port2_csr_addr) - 12'h300: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - 32'd1074794757; - 12'h304: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_mscratch; - 12'h341: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = rg_mepc; - 12'h342: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_mtval; - 12'h344: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_tselect; - 12'h7A1: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_tdata1; - 12'h7A2: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_minstret[63:32]; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = 32'd0; - default: IF_read_csr_port2_csr_addr_EQ_0xC00_40_THEN_rg_ETC___d394 = - rg_tdata3; - endcase - end - always@(mav_read_csr_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (mav_read_csr_csr_addr) - 12'h300: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - 32'd1074794757; - 12'h304: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - csr_mie$fv_read; - 12'h305: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - { 29'd0, rg_mcounteren }; - 12'h340: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_mscratch; - 12'h341: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = rg_mepc; - 12'h342: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - { rg_mcause[4], 27'd0, rg_mcause[3:0] }; - 12'h343: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_mtval; - 12'h344: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - csr_mip$fv_read; - 12'h7A0: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_tselect; - 12'h7A1: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_tdata1; - 12'h7A2: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_mcycle[31:0]; - 12'hB02, 12'hC02: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_minstret[31:0]; - 12'hB80, 12'hC80: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_mcycle[63:32]; - 12'hB82, 12'hC82: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_minstret[63:32]; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = 32'd0; - default: IF_mav_read_csr_csr_addr_EQ_0xC00_17_THEN_rg_m_ETC___d571 = - rg_tdata3; - endcase - end - always@(mav_csr_write_csr_addr or - wordxl1__h4173 or - csr_mie$fav_write or - v__h4656 or - v__h4718 or - mav_csr_write_word or - v__h4874 or csr_mip$fav_write or result__h5489) - begin - case (mav_csr_write_csr_addr) - 12'h300: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - wordxl1__h4173; - 12'h301, 12'h7A0: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = 32'd0; - 12'h304: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - csr_mie$fav_write; - 12'h305: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - v__h4656; - 12'h306: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - v__h4718; - 12'h340, - 12'h341, - 12'h343, - 12'h7A2, - 12'h7A3, - 12'hB00, - 12'hB02, - 12'hB80, - 12'hB82: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - mav_csr_write_word; - 12'h342: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - v__h4874; - 12'h344: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - csr_mip$fav_write; - 12'h7A1: - IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - result__h5489; - default: IF_mav_csr_write_csr_addr_EQ_0x300_88_THEN_0_C_ETC___d765 = - 32'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 32'd0; - rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (csr_mstatus_rg_mstatus$EN) - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY - csr_mstatus_rg_mstatus$D_IN; - if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; - if (rg_minstret$EN) - rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; - if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; - if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; - if (rg_dscratch0$EN) - rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; - if (rg_dscratch1$EN) - rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; - if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; - if (rg_mcounteren$EN) - rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; - if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; - if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; - if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; - if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; - if (rg_nmi_vector$EN) - rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN; - if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; - if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; - if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; - if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - csr_mstatus_rg_mstatus = 32'hAAAAAAAA; - rg_dcsr = 32'hAAAAAAAA; - rg_dpc = 32'hAAAAAAAA; - rg_dscratch0 = 32'hAAAAAAAA; - rg_dscratch1 = 32'hAAAAAAAA; - rg_mcause = 5'h0A; - rg_mcounteren = 3'h2; - rg_mcycle = 64'hAAAAAAAAAAAAAAAA; - rg_mepc = 32'hAAAAAAAA; - rg_minstret = 64'hAAAAAAAAAAAAAAAA; - rg_mscratch = 32'hAAAAAAAA; - rg_mtval = 32'hAAAAAAAA; - rg_mtvec = 31'h2AAAAAAA; - rg_nmi = 1'h0; - rg_nmi_vector = 32'hAAAAAAAA; - rg_state = 1'h0; - rg_tdata1 = 32'hAAAAAAAA; - rg_tdata2 = 32'hAAAAAAAA; - rg_tdata3 = 32'hAAAAAAAA; - rg_tselect = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" priv %0d: ", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" edeleg: 0x%0h", 16'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" ideleg: 0x%0h", 12'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd10 && - rg_mcause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd11 && - rg_mcause[3:0] != 4'd12 && - rg_mcause[3:0] != 4'd13 && - rg_mcause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" status: 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" tvec: 0x%0h", { rg_mtvec[30:1], 1'b0, rg_mtvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" epc: 0x%0h", rg_mepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" tval: 0x%0h", rg_mtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" Return: new pc 0x%0h ", x__h5982); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" new mstatus:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write("MStatus{", "sd:%0d", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" tsr:%0d", csr_mstatus_rg_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" tw:%0d", csr_mstatus_rg_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" tvm:%0d", csr_mstatus_rg_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" mxr:%0d", csr_mstatus_rg_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" sum:%0d", csr_mstatus_rg_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" mprv:%0d", csr_mstatus_rg_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" xs:%0d", 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" fs:%0d", 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" mpp:%0d", mpp__h7476); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" spp:%0d", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" pies:%0d_%0d%0d", csr_mstatus_rg_mstatus[3], 1'd0, 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" ies:%0d_%0d%0d", 1'd0, 1'd0, 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" new xcause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8048 == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - NOT_csr_trap_actions_nmi_93_AND_csr_trap_actio_ETC___d970) - $write("unknown interrupt Exc_Code %d", exc_code__h8048); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8048 == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729 && - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1021) - $write("unknown trap Exc_Code %d", exc_code__h8048); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $write(" new priv %0d", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_74_OR_NOT_mav_ETC___d726 && - NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", - rg_mcycle, - mav_csr_write_csr_addr, - mav_csr_write_word); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", - rg_mcycle, - m_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", - rg_mcycle, - s_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: CSR_RegFile: software_interrupt_req: %x", - rg_mcycle, - software_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__27_ULE_1_28___d729) - $display("%0d: CSR_RegFile: timer_interrupt_req: %x", - rg_mcycle, - timer_interrupt_req_set_not_clear); - end - // synopsys translate_on -endmodule // mkCSR_RegFile - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCore.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCore.v deleted file mode 100644 index a67d6dff..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkCore.v +++ /dev/null @@ -1,2455 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// cpu_reset_server_response_get O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg -// cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg -// cpu_imem_master_wvalid O 1 -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg -// cpu_imem_master_bready O 1 -// cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg -// cpu_imem_master_rready O 1 -// cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg -// cpu_dmem_master_awaddr O 64 reg -// cpu_dmem_master_awlen O 8 reg -// cpu_dmem_master_awsize O 3 reg -// cpu_dmem_master_awburst O 2 reg -// cpu_dmem_master_awlock O 1 reg -// cpu_dmem_master_awcache O 4 reg -// cpu_dmem_master_awprot O 3 reg -// cpu_dmem_master_awqos O 4 reg -// cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wdata O 64 reg -// cpu_dmem_master_wstrb O 8 reg -// cpu_dmem_master_wlast O 1 reg -// cpu_dmem_master_bready O 1 reg -// cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg -// cpu_dmem_master_araddr O 64 reg -// cpu_dmem_master_arlen O 8 reg -// cpu_dmem_master_arsize O 3 reg -// cpu_dmem_master_arburst O 2 reg -// cpu_dmem_master_arlock O 1 reg -// cpu_dmem_master_arcache O 4 reg -// cpu_dmem_master_arprot O 3 reg -// cpu_dmem_master_arqos O 4 reg -// cpu_dmem_master_arregion O 4 reg -// cpu_dmem_master_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// cpu_reset_server_request_put I 1 reg -// cpu_imem_master_awready I 1 -// cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg -// cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg -// cpu_dmem_master_awready I 1 -// cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg -// cpu_dmem_master_bresp I 2 reg -// cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg -// cpu_dmem_master_rdata I 64 reg -// cpu_dmem_master_rresp I 2 reg -// cpu_dmem_master_rlast I 1 reg -// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// nmi_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCore(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - cpu_reset_server_request_put, - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, - - cpu_imem_master_awvalid, - - cpu_imem_master_awid, - - cpu_imem_master_awaddr, - - cpu_imem_master_awlen, - - cpu_imem_master_awsize, - - cpu_imem_master_awburst, - - cpu_imem_master_awlock, - - cpu_imem_master_awcache, - - cpu_imem_master_awprot, - - cpu_imem_master_awqos, - - cpu_imem_master_awregion, - - cpu_imem_master_awready, - - cpu_imem_master_wvalid, - - cpu_imem_master_wdata, - - cpu_imem_master_wstrb, - - cpu_imem_master_wlast, - - cpu_imem_master_wready, - - cpu_imem_master_bvalid, - cpu_imem_master_bid, - cpu_imem_master_bresp, - - cpu_imem_master_bready, - - cpu_imem_master_arvalid, - - cpu_imem_master_arid, - - cpu_imem_master_araddr, - - cpu_imem_master_arlen, - - cpu_imem_master_arsize, - - cpu_imem_master_arburst, - - cpu_imem_master_arlock, - - cpu_imem_master_arcache, - - cpu_imem_master_arprot, - - cpu_imem_master_arqos, - - cpu_imem_master_arregion, - - cpu_imem_master_arready, - - cpu_imem_master_rvalid, - cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast, - - cpu_imem_master_rready, - - cpu_dmem_master_awvalid, - - cpu_dmem_master_awid, - - cpu_dmem_master_awaddr, - - cpu_dmem_master_awlen, - - cpu_dmem_master_awsize, - - cpu_dmem_master_awburst, - - cpu_dmem_master_awlock, - - cpu_dmem_master_awcache, - - cpu_dmem_master_awprot, - - cpu_dmem_master_awqos, - - cpu_dmem_master_awregion, - - cpu_dmem_master_awready, - - cpu_dmem_master_wvalid, - - cpu_dmem_master_wdata, - - cpu_dmem_master_wstrb, - - cpu_dmem_master_wlast, - - cpu_dmem_master_wready, - - cpu_dmem_master_bvalid, - cpu_dmem_master_bid, - cpu_dmem_master_bresp, - - cpu_dmem_master_bready, - - cpu_dmem_master_arvalid, - - cpu_dmem_master_arid, - - cpu_dmem_master_araddr, - - cpu_dmem_master_arlen, - - cpu_dmem_master_arsize, - - cpu_dmem_master_arburst, - - cpu_dmem_master_arlock, - - cpu_dmem_master_arcache, - - cpu_dmem_master_arprot, - - cpu_dmem_master_arqos, - - cpu_dmem_master_arregion, - - cpu_dmem_master_arready, - - cpu_dmem_master_rvalid, - cpu_dmem_master_rid, - cpu_dmem_master_rdata, - cpu_dmem_master_rresp, - cpu_dmem_master_rlast, - - cpu_dmem_master_rready, - - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - - nmi_req_set_not_clear); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method cpu_reset_server_request_put - input cpu_reset_server_request_put; - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // actionvalue method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; - - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; - - // value method cpu_imem_master_m_awaddr - output [63 : 0] cpu_imem_master_awaddr; - - // value method cpu_imem_master_m_awlen - output [7 : 0] cpu_imem_master_awlen; - - // value method cpu_imem_master_m_awsize - output [2 : 0] cpu_imem_master_awsize; - - // value method cpu_imem_master_m_awburst - output [1 : 0] cpu_imem_master_awburst; - - // value method cpu_imem_master_m_awlock - output cpu_imem_master_awlock; - - // value method cpu_imem_master_m_awcache - output [3 : 0] cpu_imem_master_awcache; - - // value method cpu_imem_master_m_awprot - output [2 : 0] cpu_imem_master_awprot; - - // value method cpu_imem_master_m_awqos - output [3 : 0] cpu_imem_master_awqos; - - // value method cpu_imem_master_m_awregion - output [3 : 0] cpu_imem_master_awregion; - - // value method cpu_imem_master_m_awuser - - // action method cpu_imem_master_m_awready - input cpu_imem_master_awready; - - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; - - // value method cpu_imem_master_m_wdata - output [63 : 0] cpu_imem_master_wdata; - - // value method cpu_imem_master_m_wstrb - output [7 : 0] cpu_imem_master_wstrb; - - // value method cpu_imem_master_m_wlast - output cpu_imem_master_wlast; - - // value method cpu_imem_master_m_wuser - - // action method cpu_imem_master_m_wready - input cpu_imem_master_wready; - - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; - input [1 : 0] cpu_imem_master_bresp; - - // value method cpu_imem_master_m_bready - output cpu_imem_master_bready; - - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; - - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; - - // value method cpu_imem_master_m_araddr - output [63 : 0] cpu_imem_master_araddr; - - // value method cpu_imem_master_m_arlen - output [7 : 0] cpu_imem_master_arlen; - - // value method cpu_imem_master_m_arsize - output [2 : 0] cpu_imem_master_arsize; - - // value method cpu_imem_master_m_arburst - output [1 : 0] cpu_imem_master_arburst; - - // value method cpu_imem_master_m_arlock - output cpu_imem_master_arlock; - - // value method cpu_imem_master_m_arcache - output [3 : 0] cpu_imem_master_arcache; - - // value method cpu_imem_master_m_arprot - output [2 : 0] cpu_imem_master_arprot; - - // value method cpu_imem_master_m_arqos - output [3 : 0] cpu_imem_master_arqos; - - // value method cpu_imem_master_m_arregion - output [3 : 0] cpu_imem_master_arregion; - - // value method cpu_imem_master_m_aruser - - // action method cpu_imem_master_m_arready - input cpu_imem_master_arready; - - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; - input [63 : 0] cpu_imem_master_rdata; - input [1 : 0] cpu_imem_master_rresp; - input cpu_imem_master_rlast; - - // value method cpu_imem_master_m_rready - output cpu_imem_master_rready; - - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; - - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; - - // value method cpu_dmem_master_m_awaddr - output [63 : 0] cpu_dmem_master_awaddr; - - // value method cpu_dmem_master_m_awlen - output [7 : 0] cpu_dmem_master_awlen; - - // value method cpu_dmem_master_m_awsize - output [2 : 0] cpu_dmem_master_awsize; - - // value method cpu_dmem_master_m_awburst - output [1 : 0] cpu_dmem_master_awburst; - - // value method cpu_dmem_master_m_awlock - output cpu_dmem_master_awlock; - - // value method cpu_dmem_master_m_awcache - output [3 : 0] cpu_dmem_master_awcache; - - // value method cpu_dmem_master_m_awprot - output [2 : 0] cpu_dmem_master_awprot; - - // value method cpu_dmem_master_m_awqos - output [3 : 0] cpu_dmem_master_awqos; - - // value method cpu_dmem_master_m_awregion - output [3 : 0] cpu_dmem_master_awregion; - - // value method cpu_dmem_master_m_awuser - - // action method cpu_dmem_master_m_awready - input cpu_dmem_master_awready; - - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; - - // value method cpu_dmem_master_m_wdata - output [63 : 0] cpu_dmem_master_wdata; - - // value method cpu_dmem_master_m_wstrb - output [7 : 0] cpu_dmem_master_wstrb; - - // value method cpu_dmem_master_m_wlast - output cpu_dmem_master_wlast; - - // value method cpu_dmem_master_m_wuser - - // action method cpu_dmem_master_m_wready - input cpu_dmem_master_wready; - - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; - input [1 : 0] cpu_dmem_master_bresp; - - // value method cpu_dmem_master_m_bready - output cpu_dmem_master_bready; - - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; - - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; - - // value method cpu_dmem_master_m_araddr - output [63 : 0] cpu_dmem_master_araddr; - - // value method cpu_dmem_master_m_arlen - output [7 : 0] cpu_dmem_master_arlen; - - // value method cpu_dmem_master_m_arsize - output [2 : 0] cpu_dmem_master_arsize; - - // value method cpu_dmem_master_m_arburst - output [1 : 0] cpu_dmem_master_arburst; - - // value method cpu_dmem_master_m_arlock - output cpu_dmem_master_arlock; - - // value method cpu_dmem_master_m_arcache - output [3 : 0] cpu_dmem_master_arcache; - - // value method cpu_dmem_master_m_arprot - output [2 : 0] cpu_dmem_master_arprot; - - // value method cpu_dmem_master_m_arqos - output [3 : 0] cpu_dmem_master_arqos; - - // value method cpu_dmem_master_m_arregion - output [3 : 0] cpu_dmem_master_arregion; - - // value method cpu_dmem_master_m_aruser - - // action method cpu_dmem_master_m_arready - input cpu_dmem_master_arready; - - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; - input [63 : 0] cpu_dmem_master_rdata; - input [1 : 0] cpu_dmem_master_rresp; - input cpu_dmem_master_rlast; - - // value method cpu_dmem_master_m_rready - output cpu_dmem_master_rready; - - // action method core_external_interrupt_sources_0_m_interrupt_req - input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_1_m_interrupt_req - input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_2_m_interrupt_req - input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_3_m_interrupt_req - input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_4_m_interrupt_req - input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_5_m_interrupt_req - input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_6_m_interrupt_req - input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_7_m_interrupt_req - input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_8_m_interrupt_req - input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_9_m_interrupt_req - input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_10_m_interrupt_req - input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_11_m_interrupt_req - input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_12_m_interrupt_req - input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_13_m_interrupt_req - input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_14_m_interrupt_req - input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_15_m_interrupt_req - input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // signals for module outputs - wire [63 : 0] cpu_dmem_master_araddr, - cpu_dmem_master_awaddr, - cpu_dmem_master_wdata, - cpu_imem_master_araddr, - cpu_imem_master_awaddr, - cpu_imem_master_wdata; - wire [7 : 0] cpu_dmem_master_arlen, - cpu_dmem_master_awlen, - cpu_dmem_master_wstrb, - cpu_imem_master_arlen, - cpu_imem_master_awlen, - cpu_imem_master_wstrb; - wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, - cpu_dmem_master_arqos, - cpu_dmem_master_arregion, - cpu_dmem_master_awcache, - cpu_dmem_master_awid, - cpu_dmem_master_awqos, - cpu_dmem_master_awregion, - cpu_imem_master_arcache, - cpu_imem_master_arid, - cpu_imem_master_arqos, - cpu_imem_master_arregion, - cpu_imem_master_awcache, - cpu_imem_master_awid, - cpu_imem_master_awqos, - cpu_imem_master_awregion; - wire [2 : 0] cpu_dmem_master_arprot, - cpu_dmem_master_arsize, - cpu_dmem_master_awprot, - cpu_dmem_master_awsize, - cpu_imem_master_arprot, - cpu_imem_master_arsize, - cpu_imem_master_awprot, - cpu_imem_master_awsize; - wire [1 : 0] cpu_dmem_master_arburst, - cpu_dmem_master_awburst, - cpu_imem_master_arburst, - cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_set_verbosity, - cpu_dmem_master_arlock, - cpu_dmem_master_arvalid, - cpu_dmem_master_awlock, - cpu_dmem_master_awvalid, - cpu_dmem_master_bready, - cpu_dmem_master_rready, - cpu_dmem_master_wlast, - cpu_dmem_master_wvalid, - cpu_imem_master_arlock, - cpu_imem_master_arvalid, - cpu_imem_master_awlock, - cpu_imem_master_awvalid, - cpu_imem_master_bready, - cpu_imem_master_rready, - cpu_imem_master_wlast, - cpu_imem_master_wvalid, - cpu_reset_server_response_get; - - // ports of submodule cpu - wire [63 : 0] cpu$dmem_master_araddr, - cpu$dmem_master_awaddr, - cpu$dmem_master_rdata, - cpu$dmem_master_wdata, - cpu$imem_master_araddr, - cpu$imem_master_awaddr, - cpu$imem_master_rdata, - cpu$imem_master_wdata, - cpu$set_verbosity_logdelay; - wire [7 : 0] cpu$dmem_master_arlen, - cpu$dmem_master_awlen, - cpu$dmem_master_wstrb, - cpu$imem_master_arlen, - cpu$imem_master_awlen, - cpu$imem_master_wstrb; - wire [3 : 0] cpu$dmem_master_arcache, - cpu$dmem_master_arid, - cpu$dmem_master_arqos, - cpu$dmem_master_arregion, - cpu$dmem_master_awcache, - cpu$dmem_master_awid, - cpu$dmem_master_awqos, - cpu$dmem_master_awregion, - cpu$dmem_master_bid, - cpu$dmem_master_rid, - cpu$imem_master_arcache, - cpu$imem_master_arid, - cpu$imem_master_arqos, - cpu$imem_master_arregion, - cpu$imem_master_awcache, - cpu$imem_master_awid, - cpu$imem_master_awqos, - cpu$imem_master_awregion, - cpu$imem_master_bid, - cpu$imem_master_rid, - cpu$set_verbosity_verbosity; - wire [2 : 0] cpu$dmem_master_arprot, - cpu$dmem_master_arsize, - cpu$dmem_master_awprot, - cpu$dmem_master_awsize, - cpu$imem_master_arprot, - cpu$imem_master_arsize, - cpu$imem_master_awprot, - cpu$imem_master_awsize; - wire [1 : 0] cpu$dmem_master_arburst, - cpu$dmem_master_awburst, - cpu$dmem_master_bresp, - cpu$dmem_master_rresp, - cpu$imem_master_arburst, - cpu$imem_master_awburst, - cpu$imem_master_bresp, - cpu$imem_master_rresp; - wire cpu$EN_hart0_server_reset_request_put, - cpu$EN_hart0_server_reset_response_get, - cpu$EN_set_verbosity, - cpu$RDY_hart0_server_reset_request_put, - cpu$RDY_hart0_server_reset_response_get, - cpu$dmem_master_arlock, - cpu$dmem_master_arready, - cpu$dmem_master_arvalid, - cpu$dmem_master_awlock, - cpu$dmem_master_awready, - cpu$dmem_master_awvalid, - cpu$dmem_master_bready, - cpu$dmem_master_bvalid, - cpu$dmem_master_rlast, - cpu$dmem_master_rready, - cpu$dmem_master_rvalid, - cpu$dmem_master_wlast, - cpu$dmem_master_wready, - cpu$dmem_master_wvalid, - cpu$hart0_server_reset_request_put, - cpu$hart0_server_reset_response_get, - cpu$imem_master_arlock, - cpu$imem_master_arready, - cpu$imem_master_arvalid, - cpu$imem_master_awlock, - cpu$imem_master_awready, - cpu$imem_master_awvalid, - cpu$imem_master_bready, - cpu$imem_master_bvalid, - cpu$imem_master_rlast, - cpu$imem_master_rready, - cpu$imem_master_rvalid, - cpu$imem_master_wlast, - cpu$imem_master_wready, - cpu$imem_master_wvalid, - cpu$m_external_interrupt_req_set_not_clear, - cpu$nmi_req_set_not_clear, - cpu$s_external_interrupt_req_set_not_clear, - cpu$software_interrupt_req_set_not_clear, - cpu$timer_interrupt_req_set_not_clear; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_araddr, - fabric_2x3$v_to_slaves_2_awaddr, - fabric_2x3$v_to_slaves_2_rdata, - fabric_2x3$v_to_slaves_2_wdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb, - fabric_2x3$v_to_slaves_2_arlen, - fabric_2x3$v_to_slaves_2_awlen, - fabric_2x3$v_to_slaves_2_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_2_arcache, - fabric_2x3$v_to_slaves_2_arid, - fabric_2x3$v_to_slaves_2_arqos, - fabric_2x3$v_to_slaves_2_arregion, - fabric_2x3$v_to_slaves_2_awcache, - fabric_2x3$v_to_slaves_2_awid, - fabric_2x3$v_to_slaves_2_awqos, - fabric_2x3$v_to_slaves_2_awregion, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize, - fabric_2x3$v_to_slaves_2_arprot, - fabric_2x3$v_to_slaves_2_arsize, - fabric_2x3$v_to_slaves_2_awprot, - fabric_2x3$v_to_slaves_2_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_arburst, - fabric_2x3$v_to_slaves_2_awburst, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arlock, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_arvalid, - fabric_2x3$v_to_slaves_2_awlock, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_awvalid, - fabric_2x3$v_to_slaves_2_bready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rready, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wlast, - fabric_2x3$v_to_slaves_2_wready, - fabric_2x3$v_to_slaves_2_wvalid; - - // ports of submodule near_mem_io - wire [63 : 0] near_mem_io$axi4_slave_araddr, - near_mem_io$axi4_slave_awaddr, - near_mem_io$axi4_slave_rdata, - near_mem_io$axi4_slave_wdata, - near_mem_io$set_addr_map_addr_base, - near_mem_io$set_addr_map_addr_lim; - wire [7 : 0] near_mem_io$axi4_slave_arlen, - near_mem_io$axi4_slave_awlen, - near_mem_io$axi4_slave_wstrb; - wire [3 : 0] near_mem_io$axi4_slave_arcache, - near_mem_io$axi4_slave_arid, - near_mem_io$axi4_slave_arqos, - near_mem_io$axi4_slave_arregion, - near_mem_io$axi4_slave_awcache, - near_mem_io$axi4_slave_awid, - near_mem_io$axi4_slave_awqos, - near_mem_io$axi4_slave_awregion, - near_mem_io$axi4_slave_bid, - near_mem_io$axi4_slave_rid; - wire [2 : 0] near_mem_io$axi4_slave_arprot, - near_mem_io$axi4_slave_arsize, - near_mem_io$axi4_slave_awprot, - near_mem_io$axi4_slave_awsize; - wire [1 : 0] near_mem_io$axi4_slave_arburst, - near_mem_io$axi4_slave_awburst, - near_mem_io$axi4_slave_bresp, - near_mem_io$axi4_slave_rresp; - wire near_mem_io$EN_get_sw_interrupt_req_get, - near_mem_io$EN_get_timer_interrupt_req_get, - near_mem_io$EN_server_reset_request_put, - near_mem_io$EN_server_reset_response_get, - near_mem_io$EN_set_addr_map, - near_mem_io$RDY_get_sw_interrupt_req_get, - near_mem_io$RDY_get_timer_interrupt_req_get, - near_mem_io$RDY_server_reset_request_put, - near_mem_io$RDY_server_reset_response_get, - near_mem_io$axi4_slave_arlock, - near_mem_io$axi4_slave_arready, - near_mem_io$axi4_slave_arvalid, - near_mem_io$axi4_slave_awlock, - near_mem_io$axi4_slave_awready, - near_mem_io$axi4_slave_awvalid, - near_mem_io$axi4_slave_bready, - near_mem_io$axi4_slave_bvalid, - near_mem_io$axi4_slave_rlast, - near_mem_io$axi4_slave_rready, - near_mem_io$axi4_slave_rvalid, - near_mem_io$axi4_slave_wlast, - near_mem_io$axi4_slave_wready, - near_mem_io$axi4_slave_wvalid, - near_mem_io$get_sw_interrupt_req_get, - near_mem_io$get_timer_interrupt_req_get; - - // ports of submodule plic - wire [63 : 0] plic$axi4_slave_araddr, - plic$axi4_slave_awaddr, - plic$axi4_slave_rdata, - plic$axi4_slave_wdata, - plic$set_addr_map_addr_base, - plic$set_addr_map_addr_lim; - wire [7 : 0] plic$axi4_slave_arlen, - plic$axi4_slave_awlen, - plic$axi4_slave_wstrb; - wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, - plic$axi4_slave_arqos, - plic$axi4_slave_arregion, - plic$axi4_slave_awcache, - plic$axi4_slave_awid, - plic$axi4_slave_awqos, - plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, - plic$set_verbosity_verbosity; - wire [2 : 0] plic$axi4_slave_arprot, - plic$axi4_slave_arsize, - plic$axi4_slave_awprot, - plic$axi4_slave_awsize; - wire [1 : 0] plic$axi4_slave_arburst, - plic$axi4_slave_awburst, - plic$axi4_slave_bresp, - plic$axi4_slave_rresp; - wire plic$EN_server_reset_request_put, - plic$EN_server_reset_response_get, - plic$EN_set_addr_map, - plic$EN_set_verbosity, - plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, - plic$axi4_slave_arlock, - plic$axi4_slave_arready, - plic$axi4_slave_arvalid, - plic$axi4_slave_awlock, - plic$axi4_slave_awready, - plic$axi4_slave_awvalid, - plic$axi4_slave_bready, - plic$axi4_slave_bvalid, - plic$axi4_slave_rlast, - plic$axi4_slave_rready, - plic$axi4_slave_rvalid, - plic$axi4_slave_wlast, - plic$axi4_slave_wready, - plic$axi4_slave_wvalid, - plic$v_sources_0_m_interrupt_req_set_not_clear, - plic$v_sources_10_m_interrupt_req_set_not_clear, - plic$v_sources_11_m_interrupt_req_set_not_clear, - plic$v_sources_12_m_interrupt_req_set_not_clear, - plic$v_sources_13_m_interrupt_req_set_not_clear, - plic$v_sources_14_m_interrupt_req_set_not_clear, - plic$v_sources_15_m_interrupt_req_set_not_clear, - plic$v_sources_1_m_interrupt_req_set_not_clear, - plic$v_sources_2_m_interrupt_req_set_not_clear, - plic$v_sources_3_m_interrupt_req_set_not_clear, - plic$v_sources_4_m_interrupt_req_set_not_clear, - plic$v_sources_5_m_interrupt_req_set_not_clear, - plic$v_sources_6_m_interrupt_req_set_not_clear, - plic$v_sources_7_m_interrupt_req_set_not_clear, - plic$v_sources_8_m_interrupt_req_set_not_clear, - plic$v_sources_9_m_interrupt_req_set_not_clear, - plic$v_targets_0_m_eip, - plic$v_targets_1_m_eip; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_sw_interrupts, - CAN_FIRE_RL_rl_relay_timer_interrupts, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_nmi_req, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_sw_interrupts, - WILL_FIRE_RL_rl_relay_timer_interrupts, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_nmi_req, - WILL_FIRE_set_verbosity; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4238; - reg [31 : 0] v__h4479; - reg [31 : 0] v__h4232; - reg [31 : 0] v__h4473; - // synopsys translate_on - - // remaining internal signals - wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // actionvalue method cpu_reset_server_response_get - assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ; - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; - - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - - // value method cpu_imem_master_m_awid - assign cpu_imem_master_awid = cpu$imem_master_awid ; - - // value method cpu_imem_master_m_awaddr - assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; - - // value method cpu_imem_master_m_awlen - assign cpu_imem_master_awlen = cpu$imem_master_awlen ; - - // value method cpu_imem_master_m_awsize - assign cpu_imem_master_awsize = cpu$imem_master_awsize ; - - // value method cpu_imem_master_m_awburst - assign cpu_imem_master_awburst = cpu$imem_master_awburst ; - - // value method cpu_imem_master_m_awlock - assign cpu_imem_master_awlock = cpu$imem_master_awlock ; - - // value method cpu_imem_master_m_awcache - assign cpu_imem_master_awcache = cpu$imem_master_awcache ; - - // value method cpu_imem_master_m_awprot - assign cpu_imem_master_awprot = cpu$imem_master_awprot ; - - // value method cpu_imem_master_m_awqos - assign cpu_imem_master_awqos = cpu$imem_master_awqos ; - - // value method cpu_imem_master_m_awregion - assign cpu_imem_master_awregion = cpu$imem_master_awregion ; - - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; - - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; - - // value method cpu_imem_master_m_wdata - assign cpu_imem_master_wdata = cpu$imem_master_wdata ; - - // value method cpu_imem_master_m_wstrb - assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; - - // value method cpu_imem_master_m_wlast - assign cpu_imem_master_wlast = cpu$imem_master_wlast ; - - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; - - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = cpu$imem_master_bready ; - - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; - - // value method cpu_imem_master_m_arid - assign cpu_imem_master_arid = cpu$imem_master_arid ; - - // value method cpu_imem_master_m_araddr - assign cpu_imem_master_araddr = cpu$imem_master_araddr ; - - // value method cpu_imem_master_m_arlen - assign cpu_imem_master_arlen = cpu$imem_master_arlen ; - - // value method cpu_imem_master_m_arsize - assign cpu_imem_master_arsize = cpu$imem_master_arsize ; - - // value method cpu_imem_master_m_arburst - assign cpu_imem_master_arburst = cpu$imem_master_arburst ; - - // value method cpu_imem_master_m_arlock - assign cpu_imem_master_arlock = cpu$imem_master_arlock ; - - // value method cpu_imem_master_m_arcache - assign cpu_imem_master_arcache = cpu$imem_master_arcache ; - - // value method cpu_imem_master_m_arprot - assign cpu_imem_master_arprot = cpu$imem_master_arprot ; - - // value method cpu_imem_master_m_arqos - assign cpu_imem_master_arqos = cpu$imem_master_arqos ; - - // value method cpu_imem_master_m_arregion - assign cpu_imem_master_arregion = cpu$imem_master_arregion ; - - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; - - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - - // value method cpu_imem_master_m_rready - assign cpu_imem_master_rready = cpu$imem_master_rready ; - - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; - - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; - - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; - - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; - - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; - - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; - - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; - - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; - - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; - - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; - - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; - - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; - - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; - - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; - - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; - - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; - - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; - - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; - - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; - - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; - - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; - - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; - - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; - - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; - - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; - - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; - - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; - - // action method core_external_interrupt_sources_0_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_1_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_2_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_3_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_4_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_5_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_6_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_7_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_8_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_9_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_10_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_11_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_12_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_13_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_14_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_15_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // submodule cpu - mkCPU cpu(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(cpu$dmem_master_arready), - .dmem_master_awready(cpu$dmem_master_awready), - .dmem_master_bid(cpu$dmem_master_bid), - .dmem_master_bresp(cpu$dmem_master_bresp), - .dmem_master_bvalid(cpu$dmem_master_bvalid), - .dmem_master_rdata(cpu$dmem_master_rdata), - .dmem_master_rid(cpu$dmem_master_rid), - .dmem_master_rlast(cpu$dmem_master_rlast), - .dmem_master_rresp(cpu$dmem_master_rresp), - .dmem_master_rvalid(cpu$dmem_master_rvalid), - .dmem_master_wready(cpu$dmem_master_wready), - .hart0_server_reset_request_put(cpu$hart0_server_reset_request_put), - .imem_master_arready(cpu$imem_master_arready), - .imem_master_awready(cpu$imem_master_awready), - .imem_master_bid(cpu$imem_master_bid), - .imem_master_bresp(cpu$imem_master_bresp), - .imem_master_bvalid(cpu$imem_master_bvalid), - .imem_master_rdata(cpu$imem_master_rdata), - .imem_master_rid(cpu$imem_master_rid), - .imem_master_rlast(cpu$imem_master_rlast), - .imem_master_rresp(cpu$imem_master_rresp), - .imem_master_rvalid(cpu$imem_master_rvalid), - .imem_master_wready(cpu$imem_master_wready), - .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), - .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), - .s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear), - .set_verbosity_logdelay(cpu$set_verbosity_logdelay), - .set_verbosity_verbosity(cpu$set_verbosity_verbosity), - .software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), - .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), - .EN_set_verbosity(cpu$EN_set_verbosity), - .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), - .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), - .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), - .imem_master_awvalid(cpu$imem_master_awvalid), - .imem_master_awid(cpu$imem_master_awid), - .imem_master_awaddr(cpu$imem_master_awaddr), - .imem_master_awlen(cpu$imem_master_awlen), - .imem_master_awsize(cpu$imem_master_awsize), - .imem_master_awburst(cpu$imem_master_awburst), - .imem_master_awlock(cpu$imem_master_awlock), - .imem_master_awcache(cpu$imem_master_awcache), - .imem_master_awprot(cpu$imem_master_awprot), - .imem_master_awqos(cpu$imem_master_awqos), - .imem_master_awregion(cpu$imem_master_awregion), - .imem_master_wvalid(cpu$imem_master_wvalid), - .imem_master_wdata(cpu$imem_master_wdata), - .imem_master_wstrb(cpu$imem_master_wstrb), - .imem_master_wlast(cpu$imem_master_wlast), - .imem_master_bready(cpu$imem_master_bready), - .imem_master_arvalid(cpu$imem_master_arvalid), - .imem_master_arid(cpu$imem_master_arid), - .imem_master_araddr(cpu$imem_master_araddr), - .imem_master_arlen(cpu$imem_master_arlen), - .imem_master_arsize(cpu$imem_master_arsize), - .imem_master_arburst(cpu$imem_master_arburst), - .imem_master_arlock(cpu$imem_master_arlock), - .imem_master_arcache(cpu$imem_master_arcache), - .imem_master_arprot(cpu$imem_master_arprot), - .imem_master_arqos(cpu$imem_master_arqos), - .imem_master_arregion(cpu$imem_master_arregion), - .imem_master_rready(cpu$imem_master_rready), - .dmem_master_awvalid(cpu$dmem_master_awvalid), - .dmem_master_awid(cpu$dmem_master_awid), - .dmem_master_awaddr(cpu$dmem_master_awaddr), - .dmem_master_awlen(cpu$dmem_master_awlen), - .dmem_master_awsize(cpu$dmem_master_awsize), - .dmem_master_awburst(cpu$dmem_master_awburst), - .dmem_master_awlock(cpu$dmem_master_awlock), - .dmem_master_awcache(cpu$dmem_master_awcache), - .dmem_master_awprot(cpu$dmem_master_awprot), - .dmem_master_awqos(cpu$dmem_master_awqos), - .dmem_master_awregion(cpu$dmem_master_awregion), - .dmem_master_wvalid(cpu$dmem_master_wvalid), - .dmem_master_wdata(cpu$dmem_master_wdata), - .dmem_master_wstrb(cpu$dmem_master_wstrb), - .dmem_master_wlast(cpu$dmem_master_wlast), - .dmem_master_bready(cpu$dmem_master_bready), - .dmem_master_arvalid(cpu$dmem_master_arvalid), - .dmem_master_arid(cpu$dmem_master_arid), - .dmem_master_araddr(cpu$dmem_master_araddr), - .dmem_master_arlen(cpu$dmem_master_arlen), - .dmem_master_arsize(cpu$dmem_master_arsize), - .dmem_master_arburst(cpu$dmem_master_arburst), - .dmem_master_arlock(cpu$dmem_master_arlock), - .dmem_master_arcache(cpu$dmem_master_arcache), - .dmem_master_arprot(cpu$dmem_master_arprot), - .dmem_master_arqos(cpu$dmem_master_arqos), - .dmem_master_arregion(cpu$dmem_master_arregion), - .dmem_master_rready(cpu$dmem_master_rready), - .RDY_set_verbosity()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(), - .v_from_masters_1_wready(), - .v_from_masters_1_bvalid(), - .v_from_masters_1_bid(), - .v_from_masters_1_bresp(), - .v_from_masters_1_arready(), - .v_from_masters_1_rvalid(), - .v_from_masters_1_rid(), - .v_from_masters_1_rdata(), - .v_from_masters_1_rresp(), - .v_from_masters_1_rlast(), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); - - // submodule near_mem_io - mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(near_mem_io$axi4_slave_araddr), - .axi4_slave_arburst(near_mem_io$axi4_slave_arburst), - .axi4_slave_arcache(near_mem_io$axi4_slave_arcache), - .axi4_slave_arid(near_mem_io$axi4_slave_arid), - .axi4_slave_arlen(near_mem_io$axi4_slave_arlen), - .axi4_slave_arlock(near_mem_io$axi4_slave_arlock), - .axi4_slave_arprot(near_mem_io$axi4_slave_arprot), - .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), - .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), - .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), - .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), - .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), - .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), - .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), - .axi4_slave_awid(near_mem_io$axi4_slave_awid), - .axi4_slave_awlen(near_mem_io$axi4_slave_awlen), - .axi4_slave_awlock(near_mem_io$axi4_slave_awlock), - .axi4_slave_awprot(near_mem_io$axi4_slave_awprot), - .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), - .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), - .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), - .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), - .axi4_slave_bready(near_mem_io$axi4_slave_bready), - .axi4_slave_rready(near_mem_io$axi4_slave_rready), - .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), - .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), - .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), - .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), - .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), - .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), - .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), - .EN_set_addr_map(near_mem_io$EN_set_addr_map), - .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), - .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), - .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(near_mem_io$axi4_slave_awready), - .axi4_slave_wready(near_mem_io$axi4_slave_wready), - .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), - .axi4_slave_bid(near_mem_io$axi4_slave_bid), - .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), - .axi4_slave_arready(near_mem_io$axi4_slave_arready), - .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), - .axi4_slave_rid(near_mem_io$axi4_slave_rid), - .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), - .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), - .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), - .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), - .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), - .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), - .RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get)); - - // submodule plic - mkPLIC_16_2_7 plic(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(plic$axi4_slave_araddr), - .axi4_slave_arburst(plic$axi4_slave_arburst), - .axi4_slave_arcache(plic$axi4_slave_arcache), - .axi4_slave_arid(plic$axi4_slave_arid), - .axi4_slave_arlen(plic$axi4_slave_arlen), - .axi4_slave_arlock(plic$axi4_slave_arlock), - .axi4_slave_arprot(plic$axi4_slave_arprot), - .axi4_slave_arqos(plic$axi4_slave_arqos), - .axi4_slave_arregion(plic$axi4_slave_arregion), - .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), - .axi4_slave_awaddr(plic$axi4_slave_awaddr), - .axi4_slave_awburst(plic$axi4_slave_awburst), - .axi4_slave_awcache(plic$axi4_slave_awcache), - .axi4_slave_awid(plic$axi4_slave_awid), - .axi4_slave_awlen(plic$axi4_slave_awlen), - .axi4_slave_awlock(plic$axi4_slave_awlock), - .axi4_slave_awprot(plic$axi4_slave_awprot), - .axi4_slave_awqos(plic$axi4_slave_awqos), - .axi4_slave_awregion(plic$axi4_slave_awregion), - .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_bready(plic$axi4_slave_bready), - .axi4_slave_rready(plic$axi4_slave_rready), - .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wlast(plic$axi4_slave_wlast), - .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .set_addr_map_addr_base(plic$set_addr_map_addr_base), - .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), - .set_verbosity_verbosity(plic$set_verbosity_verbosity), - .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), - .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), - .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), - .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), - .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), - .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), - .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), - .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), - .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), - .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), - .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), - .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), - .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), - .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), - .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), - .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), - .EN_set_verbosity(plic$EN_set_verbosity), - .EN_show_PLIC_state(plic$EN_show_PLIC_state), - .EN_server_reset_request_put(plic$EN_server_reset_request_put), - .EN_server_reset_response_get(plic$EN_server_reset_response_get), - .EN_set_addr_map(plic$EN_set_addr_map), - .RDY_set_verbosity(), - .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(plic$axi4_slave_awready), - .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), - .axi4_slave_bid(plic$axi4_slave_bid), - .axi4_slave_bresp(plic$axi4_slave_bresp), - .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), - .axi4_slave_rid(plic$axi4_slave_rid), - .axi4_slave_rdata(plic$axi4_slave_rdata), - .axi4_slave_rresp(plic$axi4_slave_rresp), - .axi4_slave_rlast(plic$axi4_slave_rlast), - .v_targets_0_m_eip(plic$v_targets_0_m_eip), - .v_targets_1_m_eip(plic$v_targets_1_m_eip)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_relay_sw_interrupts - assign CAN_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // rule RL_rl_relay_timer_interrupts - assign CAN_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - - // rule RL_rl_relay_external_interrupts - assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule cpu - assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; - assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; - assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; - assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; - assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; - assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ; - assign cpu$imem_master_arready = cpu_imem_master_arready ; - assign cpu$imem_master_awready = cpu_imem_master_awready ; - assign cpu$imem_master_bid = cpu_imem_master_bid ; - assign cpu$imem_master_bresp = cpu_imem_master_bresp ; - assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; - assign cpu$imem_master_rdata = cpu_imem_master_rdata ; - assign cpu$imem_master_rid = cpu_imem_master_rid ; - assign cpu$imem_master_rlast = cpu_imem_master_rlast ; - assign cpu$imem_master_rresp = cpu_imem_master_rresp ; - assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; - assign cpu$imem_master_wready = cpu_imem_master_wready ; - assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; - assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; - assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; - assign cpu$software_interrupt_req_set_not_clear = - near_mem_io$get_sw_interrupt_req_get ; - assign cpu$timer_interrupt_req_set_not_clear = - near_mem_io$get_timer_interrupt_req_get ; - assign cpu$EN_hart0_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign cpu$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign cpu$EN_set_verbosity = EN_set_verbosity ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = cpu_reset_server_request_put ; - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ; - assign f_reset_rsps$ENQ = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; - assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; - assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; - assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; - assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; - assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; - assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; - assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_awaddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_bready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_wdata = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wstrb = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; - assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; - - // submodule near_mem_io - assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; - assign near_mem_io$set_addr_map_addr_base = - soc_map$m_near_mem_io_addr_base ; - assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; - assign near_mem_io$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign near_mem_io$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_set_addr_map = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_get_timer_interrupt_req_get = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign near_mem_io$EN_get_sw_interrupt_req_get = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; - assign plic$set_verbosity_verbosity = 4'h0 ; - assign plic$v_sources_0_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; - assign plic$v_sources_10_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; - assign plic$v_sources_11_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; - assign plic$v_sources_12_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; - assign plic$v_sources_13_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; - assign plic$v_sources_14_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; - assign plic$v_sources_15_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; - assign plic$v_sources_1_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; - assign plic$v_sources_2_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; - assign plic$v_sources_3_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; - assign plic$v_sources_4_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; - assign plic$v_sources_5_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; - assign plic$v_sources_6_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; - assign plic$v_sources_7_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; - assign plic$v_sources_8_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; - assign plic$v_sources_9_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; - assign plic$EN_set_verbosity = 1'b0 ; - assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - cpu$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h4238 = $stime; - #0; - end - v__h4232 = v__h4238 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4232); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h4479 = $stime; - #0; - end - v__h4473 = v__h4479 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4473); - end - // synopsys translate_on -endmodule // mkCore - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric.v deleted file mode 100644 index 771fc0dc..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric.v +++ /dev/null @@ -1,8149 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 = - fabric_cfg_verbosity > 4'd1 ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - $display("%0d: %m::AXI4_Fabric.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v deleted file mode 100644 index 6f003677..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v +++ /dev/null @@ -1,7404 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_2x3(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8650; - reg [31 : 0] v__h9025; - reg [31 : 0] v__h9400; - reg [31 : 0] v__h9845; - reg [31 : 0] v__h10214; - reg [31 : 0] v__h10583; - reg [31 : 0] v__h11855; - reg [31 : 0] v__h12298; - reg [31 : 0] v__h12673; - reg [31 : 0] v__h12965; - reg [31 : 0] v__h13257; - reg [31 : 0] v__h13560; - reg [31 : 0] v__h13826; - reg [31 : 0] v__h14092; - reg [31 : 0] v__h14356; - reg [31 : 0] v__h14582; - reg [31 : 0] v__h15011; - reg [31 : 0] v__h15367; - reg [31 : 0] v__h15723; - reg [31 : 0] v__h16140; - reg [31 : 0] v__h16472; - reg [31 : 0] v__h16804; - reg [31 : 0] v__h17820; - reg [31 : 0] v__h18071; - reg [31 : 0] v__h18446; - reg [31 : 0] v__h18687; - reg [31 : 0] v__h19062; - reg [31 : 0] v__h19303; - reg [31 : 0] v__h19665; - reg [31 : 0] v__h19916; - reg [31 : 0] v__h20246; - reg [31 : 0] v__h20487; - reg [31 : 0] v__h20817; - reg [31 : 0] v__h21058; - reg [31 : 0] v__h21571; - reg [31 : 0] v__h21972; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8644; - reg [31 : 0] v__h9019; - reg [31 : 0] v__h9394; - reg [31 : 0] v__h9839; - reg [31 : 0] v__h10208; - reg [31 : 0] v__h10577; - reg [31 : 0] v__h11849; - reg [31 : 0] v__h12292; - reg [31 : 0] v__h12667; - reg [31 : 0] v__h12959; - reg [31 : 0] v__h13251; - reg [31 : 0] v__h13554; - reg [31 : 0] v__h13820; - reg [31 : 0] v__h14086; - reg [31 : 0] v__h14350; - reg [31 : 0] v__h14576; - reg [31 : 0] v__h15005; - reg [31 : 0] v__h15361; - reg [31 : 0] v__h15717; - reg [31 : 0] v__h16134; - reg [31 : 0] v__h16466; - reg [31 : 0] v__h16798; - reg [31 : 0] v__h17814; - reg [31 : 0] v__h18065; - reg [31 : 0] v__h18440; - reg [31 : 0] v__h18681; - reg [31 : 0] v__h19056; - reg [31 : 0] v__h19297; - reg [31 : 0] v__h19659; - reg [31 : 0] v__h19910; - reg [31 : 0] v__h20240; - reg [31 : 0] v__h20481; - reg [31 : 0] v__h20811; - reg [31 : 0] v__h21052; - reg [31 : 0] v__h21565; - reg [31 : 0] v__h21966; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11760, - x__h12203, - x__h17957, - x__h18583, - x__h19199, - x__h21503, - x__h21904; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, - IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, - IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, - x1_avValue_rresp__h17935, - x1_avValue_rresp__h18561, - x1_avValue_rresp__h19177; - wire _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, - fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155, - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369, - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409, - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448, - fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520, - fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538, - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d273, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d323, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d273 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d273 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d273 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d323 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d323 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d323 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ? - 8'd0 : - x__h17957 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ? - 8'd0 : - x__h18583 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ? - 8'd0 : - x__h19199 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? - 8'd0 : - x__h11760 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ? - 8'd0 : - x__h12203 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ? - 8'd0 : - x__h21503 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ? - 8'd0 : - x__h21904 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396 = - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 ? - x1_avValue_rresp__h17935 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435 = - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 ? - x1_avValue_rresp__h18561 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474 = - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 ? - x1_avValue_rresp__h19177 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__49_AND_fabri_ETC___d155 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d275 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d280 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d325 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d273 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d323 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d278 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d328 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h17935 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18561 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19177 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11760 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12203 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h17957 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h18583 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19199 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21503 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h21904 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8650 = $stime; - #0; - end - v__h8644 = v__h8650 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8644, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9025 = $stime; - #0; - end - v__h9019 = v__h9025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9019, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9400 = $stime; - #0; - end - v__h9394 = v__h9400 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9394, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9845 = $stime; - #0; - end - v__h9839 = v__h9845 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9839, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10214 = $stime; - #0; - end - v__h10208 = v__h10214 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10208, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10583 = $stime; - #0; - end - v__h10577 = v__h10583 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10577, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h11855 = $stime; - #0; - end - v__h11849 = v__h11855 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h11849, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12298 = $stime; - #0; - end - v__h12292 = v__h12298 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12292, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_61_EQ_fabric_v_f_w_ETC___d163 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12673 = $stime; - #0; - end - v__h12667 = v__h12673 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12667, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h12965 = $stime; - #0; - end - v__h12959 = v__h12965 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12959, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13257 = $stime; - #0; - end - v__h13251 = v__h13257 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13251, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13560 = $stime; - #0; - end - v__h13554 = v__h13560 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13554, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13826 = $stime; - #0; - end - v__h13820 = v__h13826 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13820, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14092 = $stime; - #0; - end - v__h14086 = v__h14092 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14086, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14356 = $stime; - #0; - end - v__h14350 = v__h14356 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14350, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14582 = $stime; - #0; - end - v__h14576 = v__h14582 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14576, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15011 = $stime; - #0; - end - v__h15005 = v__h15011 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15005, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15367 = $stime; - #0; - end - v__h15361 = v__h15367 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15361, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15723 = $stime; - #0; - end - v__h15717 = v__h15723 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15717, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16140 = $stime; - #0; - end - v__h16134 = v__h16140 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16134, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16472 = $stime; - #0; - end - v__h16466 = v__h16472 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16466, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16804 = $stime; - #0; - end - v__h16798 = v__h16804 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16798, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h17820 = $stime; - #0; - end - v__h17814 = v__h17820 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h17814, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18071 = $stime; - #0; - end - v__h18065 = v__h18071 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18065, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18446 = $stime; - #0; - end - v__h18440 = v__h18446 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18440, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h18687 = $stime; - #0; - end - v__h18681 = v__h18687 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18681, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19062 = $stime; - #0; - end - v__h19056 = v__h19062 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19056, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19303 = $stime; - #0; - end - v__h19297 = v__h19303 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19297, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h19665 = $stime; - #0; - end - v__h19659 = v__h19665 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19659, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_rd_ETC___d369 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19916 = $stime; - #0; - end - v__h19910 = v__h19916 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19910, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20246 = $stime; - #0; - end - v__h20240 = v__h20246 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20240, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_rd_ETC___d409 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20487 = $stime; - #0; - end - v__h20481 = v__h20487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20481, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h20817 = $stime; - #0; - end - v__h20811 = v__h20817 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20811, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_rd_ETC___d448 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21058 = $stime; - #0; - end - v__h21052 = v__h21058 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21052, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21571 = $stime; - #0; - end - v__h21565 = v__h21571 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21565, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_18_EQ_fabric_v__ETC___d520) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21972 = $stime; - #0; - end - v__h21966 = v__h21972 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21966, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_36_EQ_fabric_v__ETC___d538) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_2x3 - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v deleted file mode 100644 index 02f0fd52..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v +++ /dev/null @@ -1,8084 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_AXI4(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11189; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12057; - reg [31 : 0] v__h12500; - reg [31 : 0] v__h12875; - reg [31 : 0] v__h13167; - reg [31 : 0] v__h13459; - reg [31 : 0] v__h13762; - reg [31 : 0] v__h14028; - reg [31 : 0] v__h14294; - reg [31 : 0] v__h14558; - reg [31 : 0] v__h14784; - reg [31 : 0] v__h15238; - reg [31 : 0] v__h15619; - reg [31 : 0] v__h16000; - reg [31 : 0] v__h16442; - reg [31 : 0] v__h16799; - reg [31 : 0] v__h17156; - reg [31 : 0] v__h17507; - reg [31 : 0] v__h17808; - reg [31 : 0] v__h18216; - reg [31 : 0] v__h18467; - reg [31 : 0] v__h18842; - reg [31 : 0] v__h19083; - reg [31 : 0] v__h19458; - reg [31 : 0] v__h19699; - reg [31 : 0] v__h20061; - reg [31 : 0] v__h20312; - reg [31 : 0] v__h20642; - reg [31 : 0] v__h20883; - reg [31 : 0] v__h21213; - reg [31 : 0] v__h21454; - reg [31 : 0] v__h21967; - reg [31 : 0] v__h22368; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11183; - reg [31 : 0] v__h11587; - reg [31 : 0] v__h12051; - reg [31 : 0] v__h12494; - reg [31 : 0] v__h12869; - reg [31 : 0] v__h13161; - reg [31 : 0] v__h13453; - reg [31 : 0] v__h13756; - reg [31 : 0] v__h14022; - reg [31 : 0] v__h14288; - reg [31 : 0] v__h14552; - reg [31 : 0] v__h14778; - reg [31 : 0] v__h15232; - reg [31 : 0] v__h15613; - reg [31 : 0] v__h15994; - reg [31 : 0] v__h16436; - reg [31 : 0] v__h16793; - reg [31 : 0] v__h17150; - reg [31 : 0] v__h17501; - reg [31 : 0] v__h17802; - reg [31 : 0] v__h18210; - reg [31 : 0] v__h18461; - reg [31 : 0] v__h18836; - reg [31 : 0] v__h19077; - reg [31 : 0] v__h19452; - reg [31 : 0] v__h19693; - reg [31 : 0] v__h20055; - reg [31 : 0] v__h20306; - reg [31 : 0] v__h20636; - reg [31 : 0] v__h20877; - reg [31 : 0] v__h21207; - reg [31 : 0] v__h21448; - reg [31 : 0] v__h21961; - reg [31 : 0] v__h22362; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11962, - x__h12405, - x__h18353, - x__h18979, - x__h19595, - x__h21899, - x__h22300; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498, - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537, - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396, - x1_avValue_rresp__h18331, - x1_avValue_rresp__h18957, - x1_avValue_rresp__h19573; - wire NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d439, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d457, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__03_AND_fabri_ETC___d209, - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471, - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511, - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__03_AND_fabri_ETC___d209 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d439 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d457 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 ? - 8'd0 : - x__h18353 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 ? - 8'd0 : - x__h18979 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 ? - 8'd0 : - x__h19595 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11962 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 ? - 8'd0 : - x__h12405 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ? - 8'd0 : - x__h21899 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ? - 8'd0 : - x__h22300 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 ? - x1_avValue_rresp__h18331 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 ? - x1_avValue_rresp__h18957 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 ? - x1_avValue_rresp__h19573 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d340 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d396 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387) ? - 2'd0 : - 2'd2) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d439 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d457 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__03_AND_fabri_ETC___d209 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d337 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d327 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d328 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d330 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d331 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d334 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d393 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d383 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d384 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d386 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d387 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d390 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d333 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d389 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18331 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18957 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19573 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11962 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12405 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18353 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h18979 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19595 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21899 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22300 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h11189 = $stime; - #0; - end - v__h11183 = v__h11189 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11183, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h11593 = $stime; - #0; - end - v__h11587 = v__h11593 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11587, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12057 = $stime; - #0; - end - v__h12051 = v__h12057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12051, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12500 = $stime; - #0; - end - v__h12494 = v__h12500 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12494, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_15_EQ_fabric_v_f_w_ETC___d217 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12875 = $stime; - #0; - end - v__h12869 = v__h12875 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12869, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13167 = $stime; - #0; - end - v__h13161 = v__h13167 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13161, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13459 = $stime; - #0; - end - v__h13453 = v__h13459 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13453, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13762 = $stime; - #0; - end - v__h13756 = v__h13762 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13756, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14028 = $stime; - #0; - end - v__h14022 = v__h14028 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14022, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14294 = $stime; - #0; - end - v__h14288 = v__h14294 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14288, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14558 = $stime; - #0; - end - v__h14552 = v__h14558 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14552, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14784 = $stime; - #0; - end - v__h14778 = v__h14784 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14778, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15238 = $stime; - #0; - end - v__h15232 = v__h15238 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15232, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15619 = $stime; - #0; - end - v__h15613 = v__h15619 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15613, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16000 = $stime; - #0; - end - v__h15994 = v__h16000 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15994, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16442 = $stime; - #0; - end - v__h16436 = v__h16442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16436, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16799 = $stime; - #0; - end - v__h16793 = v__h16799 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16793, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17156 = $stime; - #0; - end - v__h17150 = v__h17156 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17150, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h17507 = $stime; - #0; - end - v__h17501 = v__h17507 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17501, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17808 = $stime; - #0; - end - v__h17802 = v__h17808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17802, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18216 = $stime; - #0; - end - v__h18210 = v__h18216 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18210, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18467 = $stime; - #0; - end - v__h18461 = v__h18467 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18461, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18842 = $stime; - #0; - end - v__h18836 = v__h18842 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18836, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19083 = $stime; - #0; - end - v__h19077 = v__h19083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19458 = $stime; - #0; - end - v__h19452 = v__h19458 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19452, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19699 = $stime; - #0; - end - v__h19693 = v__h19699 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19693, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20061 = $stime; - #0; - end - v__h20055 = v__h20061 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20055, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d471 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20312 = $stime; - #0; - end - v__h20306 = v__h20312 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20306, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d498); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20642 = $stime; - #0; - end - v__h20636 = v__h20642 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20636, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d511 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20883 = $stime; - #0; - end - v__h20877 = v__h20883 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20877, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d537); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21213 = $stime; - #0; - end - v__h21207 = v__h21213 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h21207, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d550 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21454 = $stime; - #0; - end - v__h21448 = v__h21454 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21448, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d576); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21967 = $stime; - #0; - end - v__h21961 = v__h21967 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21961, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22368 = $stime; - #0; - end - v__h22362 = v__h22368 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h22362, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_AXI4 - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v deleted file mode 100644 index a238e586..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v +++ /dev/null @@ -1,249 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 32 -// read_rs1_port2 O 32 -// read_rs2 O 32 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 32 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// Combinational paths from inputs to outputs: -// read_rs1_rs1 -> read_rs1 -// read_rs1_port2_rs1 -> read_rs1_port2 -// read_rs2_rs2 -> read_rs2 -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkGPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [31 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [31 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [31 : 0] read_rs2; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [31 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [31 : 0] read_rs1, read_rs1_port2, read_rs2; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [31 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 32'd0 : regfile$D_OUT_3 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = - (read_rs1_port2_rs1 == 5'd0) ? 32'd0 : regfile$D_OUT_2 ; - - // value method read_rs2 - assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 32'd0 : regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd32), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs2_rs2 ; - assign regfile$ADDR_2 = read_rs1_port2_rs1 ; - assign regfile$ADDR_3 = read_rs1_rs1 ; - assign regfile$ADDR_4 = 5'h0 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkGPR_RegFile - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v deleted file mode 100644 index f4d13fdd..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 64 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 32 -// put_args_y_is_signed I 1 -// put_args_y I 32 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_32(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [31 : 0] put_args_x; - input put_args_y_is_signed; - input [31 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [63 : 0] result_value; - - // signals for module outputs - wire [63 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [63 : 0] m_rg_x; - wire [63 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [63 : 0] m_rg_xy; - wire [63 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [31 : 0] m_rg_y; - wire [31 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [63 : 0] xy___1__h654; - wire [31 : 0] _theResult___fst__h491, - _theResult___fst__h494, - _theResult___fst__h536, - _theResult___fst__h539, - _theResult___snd_fst__h531; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 32'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h654 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 32'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h491 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h539 : - _theResult___snd_fst__h531 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[31] != put_args_y[31] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 = - put_args_x_is_signed ? - put_args_x[31] : - put_args_y_is_signed && put_args_y[31] ; - assign _theResult___fst__h491 = - put_args_x_is_signed ? _theResult___fst__h494 : put_args_x ; - assign _theResult___fst__h494 = put_args_x[31] ? -put_args_x : put_args_x ; - assign _theResult___fst__h536 = - put_args_y_is_signed ? _theResult___fst__h539 : put_args_y ; - assign _theResult___fst__h539 = put_args_y[31] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h531 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h536 ; - assign xy___1__h654 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 64'hAAAAAAAAAAAAAAAA; - m_rg_xy = 64'hAAAAAAAAAAAAAAAA; - m_rg_y = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_32 - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v deleted file mode 100644 index 0b513191..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 128 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 64 -// put_args_y_is_signed I 1 -// put_args_y I 64 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_64(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [63 : 0] put_args_x; - input put_args_y_is_signed; - input [63 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [127 : 0] result_value; - - // signals for module outputs - wire [127 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [127 : 0] m_rg_x; - wire [127 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [127 : 0] m_rg_xy; - wire [127 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [63 : 0] m_rg_y; - wire [63 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [127 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [127 : 0] xy___1__h648; - wire [63 : 0] _theResult___fst__h488, - _theResult___fst__h491, - _theResult___fst__h533, - _theResult___fst__h536, - _theResult___snd_fst__h528; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 64'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h648 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 64'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h488 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h536 : - _theResult___snd_fst__h528 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[63] != put_args_y[63] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 = - put_args_x_is_signed ? - put_args_x[63] : - put_args_y_is_signed && put_args_y[63] ; - assign _theResult___fst__h488 = - put_args_x_is_signed ? _theResult___fst__h491 : put_args_x ; - assign _theResult___fst__h491 = put_args_x[63] ? -put_args_x : put_args_x ; - assign _theResult___fst__h533 = - put_args_y_is_signed ? _theResult___fst__h536 : put_args_y ; - assign _theResult___fst__h536 = put_args_y[63] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h528 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h533 ; - assign xy___1__h648 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_y = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_64 - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v deleted file mode 100644 index ce344560..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v +++ /dev/null @@ -1,6023 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// valid O 1 -// addr O 32 reg -// word64 O 64 -// st_amo_val O 64 -// exc O 1 -// exc_code O 4 reg -// RDY_server_flush_request_put O 1 reg -// RDY_server_flush_response_get O 1 -// RDY_tlb_flush O 1 const -// mem_master_awvalid O 1 -// mem_master_awid O 4 reg -// mem_master_awaddr O 64 reg -// mem_master_awlen O 8 reg -// mem_master_awsize O 3 reg -// mem_master_awburst O 2 reg -// mem_master_awlock O 1 reg -// mem_master_awcache O 4 reg -// mem_master_awprot O 3 reg -// mem_master_awqos O 4 reg -// mem_master_awregion O 4 reg -// mem_master_wvalid O 1 -// mem_master_wdata O 64 reg -// mem_master_wstrb O 8 reg -// mem_master_wlast O 1 reg -// mem_master_bready O 1 -// mem_master_arvalid O 1 -// mem_master_arid O 4 reg -// mem_master_araddr O 64 reg -// mem_master_arlen O 8 reg -// mem_master_arsize O 3 reg -// mem_master_arburst O 2 reg -// mem_master_arlock O 1 reg -// mem_master_arcache O 4 reg -// mem_master_arprot O 3 reg -// mem_master_arqos O 4 reg -// mem_master_arregion O 4 reg -// mem_master_rready O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_op I 2 -// req_f3 I 3 -// req_amo_funct7 I 7 reg -// req_addr I 32 -// req_st_value I 64 -// req_priv I 2 unused -// req_sstatus_SUM I 1 unused -// req_mstatus_MXR I 1 unused -// req_satp I 32 unused -// mem_master_awready I 1 -// mem_master_wready I 1 -// mem_master_bvalid I 1 -// mem_master_bid I 4 reg -// mem_master_bresp I 2 reg -// mem_master_arready I 1 -// mem_master_rvalid I 1 -// mem_master_rid I 4 reg -// mem_master_rdata I 64 reg -// mem_master_rresp I 2 reg -// mem_master_rlast I 1 reg -// EN_set_verbosity I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// EN_server_flush_request_put I 1 -// EN_server_flush_response_get I 1 -// EN_tlb_flush I 1 unused -// -// Combinational paths from inputs to outputs: -// (mem_master_awready, mem_master_wready) -> valid -// (mem_master_awready, mem_master_wready) -> word64 -// (mem_master_awready, mem_master_wready) -> st_amo_val -// (mem_master_awready, mem_master_wready) -> mem_master_bready -// (mem_master_awready, mem_master_wready, EN_req) -> mem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMMU_Cache(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_op, - req_f3, - req_amo_funct7, - req_addr, - req_st_value, - req_priv, - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - EN_req, - - valid, - - addr, - - word64, - - st_amo_val, - - exc, - - exc_code, - - EN_server_flush_request_put, - RDY_server_flush_request_put, - - EN_server_flush_response_get, - RDY_server_flush_response_get, - - EN_tlb_flush, - RDY_tlb_flush, - - mem_master_awvalid, - - mem_master_awid, - - mem_master_awaddr, - - mem_master_awlen, - - mem_master_awsize, - - mem_master_awburst, - - mem_master_awlock, - - mem_master_awcache, - - mem_master_awprot, - - mem_master_awqos, - - mem_master_awregion, - - mem_master_awready, - - mem_master_wvalid, - - mem_master_wdata, - - mem_master_wstrb, - - mem_master_wlast, - - mem_master_wready, - - mem_master_bvalid, - mem_master_bid, - mem_master_bresp, - - mem_master_bready, - - mem_master_arvalid, - - mem_master_arid, - - mem_master_araddr, - - mem_master_arlen, - - mem_master_arsize, - - mem_master_arburst, - - mem_master_arlock, - - mem_master_arcache, - - mem_master_arprot, - - mem_master_arqos, - - mem_master_arregion, - - mem_master_arready, - - mem_master_rvalid, - mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast, - - mem_master_rready); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [1 : 0] req_op; - input [2 : 0] req_f3; - input [6 : 0] req_amo_funct7; - input [31 : 0] req_addr; - input [63 : 0] req_st_value; - input [1 : 0] req_priv; - input req_sstatus_SUM; - input req_mstatus_MXR; - input [31 : 0] req_satp; - input EN_req; - - // value method valid - output valid; - - // value method addr - output [31 : 0] addr; - - // value method word64 - output [63 : 0] word64; - - // value method st_amo_val - output [63 : 0] st_amo_val; - - // value method exc - output exc; - - // value method exc_code - output [3 : 0] exc_code; - - // action method server_flush_request_put - input EN_server_flush_request_put; - output RDY_server_flush_request_put; - - // action method server_flush_response_get - input EN_server_flush_response_get; - output RDY_server_flush_response_get; - - // action method tlb_flush - input EN_tlb_flush; - output RDY_tlb_flush; - - // value method mem_master_m_awvalid - output mem_master_awvalid; - - // value method mem_master_m_awid - output [3 : 0] mem_master_awid; - - // value method mem_master_m_awaddr - output [63 : 0] mem_master_awaddr; - - // value method mem_master_m_awlen - output [7 : 0] mem_master_awlen; - - // value method mem_master_m_awsize - output [2 : 0] mem_master_awsize; - - // value method mem_master_m_awburst - output [1 : 0] mem_master_awburst; - - // value method mem_master_m_awlock - output mem_master_awlock; - - // value method mem_master_m_awcache - output [3 : 0] mem_master_awcache; - - // value method mem_master_m_awprot - output [2 : 0] mem_master_awprot; - - // value method mem_master_m_awqos - output [3 : 0] mem_master_awqos; - - // value method mem_master_m_awregion - output [3 : 0] mem_master_awregion; - - // value method mem_master_m_awuser - - // action method mem_master_m_awready - input mem_master_awready; - - // value method mem_master_m_wvalid - output mem_master_wvalid; - - // value method mem_master_m_wdata - output [63 : 0] mem_master_wdata; - - // value method mem_master_m_wstrb - output [7 : 0] mem_master_wstrb; - - // value method mem_master_m_wlast - output mem_master_wlast; - - // value method mem_master_m_wuser - - // action method mem_master_m_wready - input mem_master_wready; - - // action method mem_master_m_bvalid - input mem_master_bvalid; - input [3 : 0] mem_master_bid; - input [1 : 0] mem_master_bresp; - - // value method mem_master_m_bready - output mem_master_bready; - - // value method mem_master_m_arvalid - output mem_master_arvalid; - - // value method mem_master_m_arid - output [3 : 0] mem_master_arid; - - // value method mem_master_m_araddr - output [63 : 0] mem_master_araddr; - - // value method mem_master_m_arlen - output [7 : 0] mem_master_arlen; - - // value method mem_master_m_arsize - output [2 : 0] mem_master_arsize; - - // value method mem_master_m_arburst - output [1 : 0] mem_master_arburst; - - // value method mem_master_m_arlock - output mem_master_arlock; - - // value method mem_master_m_arcache - output [3 : 0] mem_master_arcache; - - // value method mem_master_m_arprot - output [2 : 0] mem_master_arprot; - - // value method mem_master_m_arqos - output [3 : 0] mem_master_arqos; - - // value method mem_master_m_arregion - output [3 : 0] mem_master_arregion; - - // value method mem_master_m_aruser - - // action method mem_master_m_arready - input mem_master_arready; - - // action method mem_master_m_rvalid - input mem_master_rvalid; - input [3 : 0] mem_master_rid; - input [63 : 0] mem_master_rdata; - input [1 : 0] mem_master_rresp; - input mem_master_rlast; - - // value method mem_master_m_rready - output mem_master_rready; - - // signals for module outputs - reg [63 : 0] word64; - wire [63 : 0] mem_master_araddr, - mem_master_awaddr, - mem_master_wdata, - st_amo_val; - wire [31 : 0] addr; - wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; - wire [3 : 0] exc_code, - mem_master_arcache, - mem_master_arid, - mem_master_arqos, - mem_master_arregion, - mem_master_awcache, - mem_master_awid, - mem_master_awqos, - mem_master_awregion; - wire [2 : 0] mem_master_arprot, - mem_master_arsize, - mem_master_awprot, - mem_master_awsize; - wire [1 : 0] mem_master_arburst, mem_master_awburst; - wire RDY_server_flush_request_put, - RDY_server_flush_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_verbosity, - RDY_tlb_flush, - exc, - mem_master_arlock, - mem_master_arvalid, - mem_master_awlock, - mem_master_awvalid, - mem_master_bready, - mem_master_rready, - mem_master_wlast, - mem_master_wvalid, - valid; - - // inlined wires - reg [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1; - wire [10 : 0] crg_sb_to_load_delay$port0__write_1, - crg_sb_to_load_delay$port2__read; - wire [3 : 0] ctr_wr_rsps_pending_crg$port1__write_1, - ctr_wr_rsps_pending_crg$port2__read, - ctr_wr_rsps_pending_crg$port3__read; - wire crg_sb_to_load_delay$EN_port1__write, - ctr_wr_rsps_pending_crg$EN_port0__write, - ctr_wr_rsps_pending_crg$EN_port2__write, - dw_valid$whas, - master_xactor_crg_rd_addr_full$EN_port0__write, - master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port1__read, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port0__write, - master_xactor_crg_rd_data_full$EN_port1__write, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port1__read, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port0__write, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$EN_port2__write, - master_xactor_crg_wr_addr_full$port1__read, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port0__write, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$EN_port2__write, - master_xactor_crg_wr_data_full$port1__read, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read, - master_xactor_crg_wr_resp_full$EN_port0__write, - master_xactor_crg_wr_resp_full$EN_port2__write, - master_xactor_crg_wr_resp_full$port1__read, - master_xactor_crg_wr_resp_full$port2__read, - master_xactor_crg_wr_resp_full$port3__read; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_sb_to_load_delay - reg [10 : 0] crg_sb_to_load_delay; - wire [10 : 0] crg_sb_to_load_delay$D_IN; - wire crg_sb_to_load_delay$EN; - - // register ctr_wr_rsps_pending_crg - reg [3 : 0] ctr_wr_rsps_pending_crg; - wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN; - wire ctr_wr_rsps_pending_crg$EN; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - wire [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - reg [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [72 : 0] master_xactor_rg_wr_data; - reg [72 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - - // register rg_addr - reg [31 : 0] rg_addr; - wire [31 : 0] rg_addr$D_IN; - wire rg_addr$EN; - - // register rg_amo_funct7 - reg [6 : 0] rg_amo_funct7; - wire [6 : 0] rg_amo_funct7$D_IN; - wire rg_amo_funct7$EN; - - // register rg_cset_in_cache - reg [6 : 0] rg_cset_in_cache; - wire [6 : 0] rg_cset_in_cache$D_IN; - wire rg_cset_in_cache$EN; - - // register rg_error_during_refill - reg rg_error_during_refill; - wire rg_error_during_refill$D_IN, rg_error_during_refill$EN; - - // register rg_exc_code - reg [3 : 0] rg_exc_code; - reg [3 : 0] rg_exc_code$D_IN; - wire rg_exc_code$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_ld_val - reg [63 : 0] rg_ld_val; - reg [63 : 0] rg_ld_val$D_IN; - wire rg_ld_val$EN; - - // register rg_lower_word32 - reg [31 : 0] rg_lower_word32; - wire [31 : 0] rg_lower_word32$D_IN; - wire rg_lower_word32$EN; - - // register rg_lower_word32_full - reg rg_lower_word32_full; - wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN; - - // register rg_lrsc_pa - reg [31 : 0] rg_lrsc_pa; - wire [31 : 0] rg_lrsc_pa$D_IN; - wire rg_lrsc_pa$EN; - - // register rg_lrsc_valid - reg rg_lrsc_valid; - wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN; - - // register rg_op - reg [1 : 0] rg_op; - wire [1 : 0] rg_op$D_IN; - wire rg_op$EN; - - // register rg_pa - reg [31 : 0] rg_pa; - wire [31 : 0] rg_pa$D_IN; - wire rg_pa$EN; - - // register rg_pte_pa - reg [31 : 0] rg_pte_pa; - wire [31 : 0] rg_pte_pa$D_IN; - wire rg_pte_pa$EN; - - // register rg_st_amo_val - reg [63 : 0] rg_st_amo_val; - wire [63 : 0] rg_st_amo_val$D_IN; - wire rg_st_amo_val$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_word64_set_in_cache - reg [8 : 0] rg_word64_set_in_cache; - wire [8 : 0] rg_word64_set_in_cache$D_IN; - wire rg_word64_set_in_cache$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule ram_state_and_ctag_cset - wire [22 : 0] ram_state_and_ctag_cset$DIA, - ram_state_and_ctag_cset$DIB, - ram_state_and_ctag_cset$DOB; - wire [6 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB; - wire ram_state_and_ctag_cset$ENA, - ram_state_and_ctag_cset$ENB, - ram_state_and_ctag_cset$WEA, - ram_state_and_ctag_cset$WEB; - - // ports of submodule ram_word64_set - reg [63 : 0] ram_word64_set$DIB; - reg [8 : 0] ram_word64_set$ADDRB; - wire [63 : 0] ram_word64_set$DIA, ram_word64_set$DOB; - wire [8 : 0] ram_word64_set$ADDRA; - wire ram_word64_set$ENA, - ram_word64_set$ENB, - ram_word64_set$WEA, - ram_word64_set$WEB; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - wire soc_map$m_is_mem_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_ST_AMO_response, - CAN_FIRE_RL_rl_cache_refill_rsps_loop, - CAN_FIRE_RL_rl_discard_write_rsp, - CAN_FIRE_RL_rl_drive_exception_rsp, - CAN_FIRE_RL_rl_io_AMO_SC_req, - CAN_FIRE_RL_rl_io_AMO_op_req, - CAN_FIRE_RL_rl_io_AMO_read_rsp, - CAN_FIRE_RL_rl_io_read_req, - CAN_FIRE_RL_rl_io_read_rsp, - CAN_FIRE_RL_rl_io_write_req, - CAN_FIRE_RL_rl_maintain_io_read_rsp, - CAN_FIRE_RL_rl_probe_and_immed_rsp, - CAN_FIRE_RL_rl_rereq, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_shift_sb_to_load_delay, - CAN_FIRE_RL_rl_start_cache_refill, - CAN_FIRE_RL_rl_start_reset, - CAN_FIRE_mem_master_m_arready, - CAN_FIRE_mem_master_m_awready, - CAN_FIRE_mem_master_m_bvalid, - CAN_FIRE_mem_master_m_rvalid, - CAN_FIRE_mem_master_m_wready, - CAN_FIRE_req, - CAN_FIRE_server_flush_request_put, - CAN_FIRE_server_flush_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_verbosity, - CAN_FIRE_tlb_flush, - WILL_FIRE_RL_rl_ST_AMO_response, - WILL_FIRE_RL_rl_cache_refill_rsps_loop, - WILL_FIRE_RL_rl_discard_write_rsp, - WILL_FIRE_RL_rl_drive_exception_rsp, - WILL_FIRE_RL_rl_io_AMO_SC_req, - WILL_FIRE_RL_rl_io_AMO_op_req, - WILL_FIRE_RL_rl_io_AMO_read_rsp, - WILL_FIRE_RL_rl_io_read_req, - WILL_FIRE_RL_rl_io_read_rsp, - WILL_FIRE_RL_rl_io_write_req, - WILL_FIRE_RL_rl_maintain_io_read_rsp, - WILL_FIRE_RL_rl_probe_and_immed_rsp, - WILL_FIRE_RL_rl_rereq, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_shift_sb_to_load_delay, - WILL_FIRE_RL_rl_start_cache_refill, - WILL_FIRE_RL_rl_start_reset, - WILL_FIRE_mem_master_m_arready, - WILL_FIRE_mem_master_m_awready, - WILL_FIRE_mem_master_m_bvalid, - WILL_FIRE_mem_master_m_rvalid, - WILL_FIRE_mem_master_m_wready, - WILL_FIRE_req, - WILL_FIRE_server_flush_request_put, - WILL_FIRE_server_flush_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_verbosity, - WILL_FIRE_tlb_flush; - - // inputs to muxes for submodule ports - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2, - MUX_master_xactor_rg_wr_addr$write_1__VAL_1, - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - wire [72 : 0] MUX_master_xactor_rg_wr_data$write_1__VAL_1, - MUX_master_xactor_rg_wr_data$write_1__VAL_2, - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3, - MUX_ram_word64_set$a_put_3__VAL_2, - MUX_rg_ld_val$write_1__VAL_2; - wire [22 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1; - wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2, - MUX_ram_word64_set$b_put_2__VAL_4; - wire [6 : 0] MUX_rg_cset_in_cache$write_1__VAL_1; - wire [3 : 0] MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_1, - MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_4, - MUX_rg_state$write_1__VAL_8, - MUX_rg_state$write_1__VAL_9; - wire MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1, - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2, - MUX_dw_output_ld_val$wset_1__SEL_1, - MUX_dw_output_ld_val$wset_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_4, - MUX_master_xactor_rg_rd_addr$write_1__SEL_1, - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1, - MUX_ram_word64_set$a_put_1__SEL_1, - MUX_ram_word64_set$b_put_1__SEL_2, - MUX_rg_error_during_refill$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_2, - MUX_rg_exc_code$write_1__SEL_3, - MUX_rg_ld_val$write_1__SEL_2, - MUX_rg_lrsc_valid$write_1__SEL_2, - MUX_rg_state$write_1__SEL_13, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h3732; - reg [31 : 0] v__h3833; - reg [31 : 0] v__h25367; - reg [31 : 0] v__h26263; - reg [31 : 0] v__h3369; - reg [31 : 0] v__h4284; - reg [31 : 0] v__h12756; - reg [31 : 0] v__h17070; - reg [31 : 0] v__h16400; - reg [31 : 0] v__h20534; - reg [31 : 0] v__h21828; - reg [31 : 0] v__h22069; - reg [31 : 0] v__h24055; - reg [31 : 0] v__h25155; - reg [31 : 0] v__h25262; - reg [31 : 0] v__h25447; - reg [31 : 0] v__h25968; - reg [31 : 0] v__h26381; - reg [31 : 0] v__h26699; - reg [31 : 0] v__h26874; - reg [31 : 0] v__h29486; - reg [31 : 0] v__h29737; - reg [31 : 0] v__h26970; - reg [31 : 0] v__h20978; - reg [31 : 0] v__h23681; - reg [31 : 0] v__h30705; - reg [31 : 0] v__h30357; - reg [31 : 0] v__h30318; - reg [31 : 0] v__h3363; - reg [31 : 0] v__h3726; - reg [31 : 0] v__h3827; - reg [31 : 0] v__h4278; - reg [31 : 0] v__h12750; - reg [31 : 0] v__h16394; - reg [31 : 0] v__h17064; - reg [31 : 0] v__h20528; - reg [31 : 0] v__h20972; - reg [31 : 0] v__h21822; - reg [31 : 0] v__h22063; - reg [31 : 0] v__h23675; - reg [31 : 0] v__h24049; - reg [31 : 0] v__h25149; - reg [31 : 0] v__h25256; - reg [31 : 0] v__h25361; - reg [31 : 0] v__h25441; - reg [31 : 0] v__h25962; - reg [31 : 0] v__h26257; - reg [31 : 0] v__h26375; - reg [31 : 0] v__h26693; - reg [31 : 0] v__h26868; - reg [31 : 0] v__h26964; - reg [31 : 0] v__h29480; - reg [31 : 0] v__h29731; - reg [31 : 0] v__h30312; - reg [31 : 0] v__h30351; - reg [31 : 0] v__h30699; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32, - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51, - CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29, - CASE_rg_addr_BITS_2_TO_0_0x0_result4935_0x4_re_ETC__q33, - CASE_rg_addr_BITS_2_TO_0_0x0_result5000_0x4_re_ETC__q34, - CASE_rg_addr_BITS_2_TO_0_0x0_result9087_0x4_re_ETC__q49, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d669, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d802, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d661, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427, - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362, - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436, - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304, - _theResult_____2__h17628, - _theResult_____2__h27292, - ld_val__h24164, - mem_req_wr_data_wdata__h16836, - mem_req_wr_data_wdata__h20331, - mem_req_wr_data_wdata__h25765, - mem_req_wr_data_wdata__h27267, - new_ld_val__h27000, - new_value__h15491, - new_value__h5462, - w1__h17620, - w1__h27280, - w1__h27284; - reg [7 : 0] mem_req_wr_data_wstrb__h20332, mem_req_wr_data_wstrb__h27268; - reg [2 : 0] value__h26585, value__h29610; - wire [63 : 0] IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_1_EL_ETC___d273, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d803, - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259, - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368, - IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d468, - _theResult___snd_fst__h16844, - _theResult___snd_fst__h20339, - _theResult___snd_fst__h25773, - _theResult___snd_fst__h27275, - cline_fabric_addr__h21031, - mem_req_wr_addr_awaddr__h20126, - mem_req_wr_addr_awaddr__h27062, - new_st_val__h17350, - new_st_val__h17632, - new_st_val__h17723, - new_st_val__h18703, - new_st_val__h18707, - new_st_val__h18711, - new_st_val__h18715, - new_st_val__h18720, - new_st_val__h18726, - new_st_val__h18731, - new_st_val__h27296, - new_st_val__h27387, - new_st_val__h29247, - new_st_val__h29251, - new_st_val__h29255, - new_st_val__h29259, - new_st_val__h29264, - new_st_val__h29270, - new_st_val__h29275, - result__h11873, - result__h11901, - result__h11929, - result__h11957, - result__h11985, - result__h12013, - result__h12041, - result__h12086, - result__h12114, - result__h12142, - result__h12170, - result__h12198, - result__h12226, - result__h12254, - result__h12282, - result__h12327, - result__h12355, - result__h12383, - result__h12411, - result__h12452, - result__h12480, - result__h12508, - result__h12536, - result__h12577, - result__h12605, - result__h12644, - result__h12672, - result__h24224, - result__h24254, - result__h24281, - result__h24308, - result__h24335, - result__h24362, - result__h24389, - result__h24416, - result__h24460, - result__h24487, - result__h24514, - result__h24541, - result__h24568, - result__h24595, - result__h24622, - result__h24649, - result__h24693, - result__h24720, - result__h24747, - result__h24774, - result__h24814, - result__h24841, - result__h24868, - result__h24895, - result__h24935, - result__h24962, - result__h25000, - result__h25027, - result__h27475, - result__h28383, - result__h28411, - result__h28439, - result__h28467, - result__h28495, - result__h28523, - result__h28551, - result__h28596, - result__h28624, - result__h28652, - result__h28680, - result__h28708, - result__h28736, - result__h28764, - result__h28792, - result__h28837, - result__h28865, - result__h28893, - result__h28921, - result__h28962, - result__h28990, - result__h29018, - result__h29046, - result__h29087, - result__h29115, - result__h29154, - result__h29182, - result__h5517, - st_val__h27012, - w1___1__h17691, - w1___1__h27355, - w2___1__h27356, - w2__h27286, - word64__h5280, - x__h13143, - y__h5553; - wire [31 : 0] cline_addr__h21030, - ld_val4164_BITS_31_TO_0__q37, - ld_val4164_BITS_63_TO_32__q44, - master_xactor_rg_rd_data_BITS_34_TO_3__q2, - master_xactor_rg_rd_data_BITS_66_TO_35__q10, - new_value462_BITS_31_TO_0__q30, - rg_st_amo_val_BITS_31_TO_0__q31, - w17280_BITS_31_TO_0__q50, - word64280_BITS_31_TO_0__q17, - word64280_BITS_63_TO_32__q24; - wire [21 : 0] pa_ctag__h5138; - wire [15 : 0] ld_val4164_BITS_15_TO_0__q36, - ld_val4164_BITS_31_TO_16__q40, - ld_val4164_BITS_47_TO_32__q43, - ld_val4164_BITS_63_TO_48__q47, - master_xactor_rg_rd_data_BITS_18_TO_3__q3, - master_xactor_rg_rd_data_BITS_34_TO_19__q6, - master_xactor_rg_rd_data_BITS_50_TO_35__q9, - master_xactor_rg_rd_data_BITS_66_TO_51__q13, - word64280_BITS_15_TO_0__q16, - word64280_BITS_31_TO_16__q20, - word64280_BITS_47_TO_32__q23, - word64280_BITS_63_TO_48__q27; - wire [7 : 0] ld_val4164_BITS_15_TO_8__q38, - ld_val4164_BITS_23_TO_16__q39, - ld_val4164_BITS_31_TO_24__q41, - ld_val4164_BITS_39_TO_32__q42, - ld_val4164_BITS_47_TO_40__q45, - ld_val4164_BITS_55_TO_48__q46, - ld_val4164_BITS_63_TO_56__q48, - ld_val4164_BITS_7_TO_0__q35, - master_xactor_rg_rd_data_BITS_10_TO_3__q1, - master_xactor_rg_rd_data_BITS_18_TO_11__q4, - master_xactor_rg_rd_data_BITS_26_TO_19__q5, - master_xactor_rg_rd_data_BITS_34_TO_27__q7, - master_xactor_rg_rd_data_BITS_42_TO_35__q8, - master_xactor_rg_rd_data_BITS_50_TO_43__q11, - master_xactor_rg_rd_data_BITS_58_TO_51__q12, - master_xactor_rg_rd_data_BITS_66_TO_59__q14, - strobe64__h20265, - strobe64__h20267, - strobe64__h20269, - strobe64__h27201, - strobe64__h27203, - strobe64__h27205, - word64280_BITS_15_TO_8__q18, - word64280_BITS_23_TO_16__q19, - word64280_BITS_31_TO_24__q21, - word64280_BITS_39_TO_32__q22, - word64280_BITS_47_TO_40__q25, - word64280_BITS_55_TO_48__q26, - word64280_BITS_63_TO_56__q28, - word64280_BITS_7_TO_0__q15; - wire [5 : 0] shift_bits__h20132, shift_bits__h27068; - wire [3 : 0] IF_rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d112, - IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d111, - access_exc_code__h2925, - b__h20932; - wire IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d80, - NOT_cfg_verbosity_read__0_ULE_1_1___d12, - NOT_cfg_verbosity_read__0_ULE_2_56___d557, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d300, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d311, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d445, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d480, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d492, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d520, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d527, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d533, - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d535, - NOT_ram_state_and_ctag_cset_b_read__0_BIT_22_1_ETC___d121, - NOT_req_f3_BITS_1_TO_0_93_EQ_0b0_94_95_AND_NOT_ETC___d914, - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d107, - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448, - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d495, - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503, - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d508, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d130, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d308, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d442, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d518, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d521, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d525, - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d531, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d306, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d440, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d493, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d497, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d501, - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d506, - dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d82, - lrsc_result__h13133, - master_xactor_crg_rd_data_full_port1__read__53_ETC___d726, - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76, - ram_state_and_ctag_cset_b_read__0_BIT_22_1_AND_ETC___d122, - req_f3_BITS_1_TO_0_93_EQ_0b0_94_OR_req_f3_BITS_ETC___d923, - rg_addr_0_EQ_rg_lrsc_pa_9___d119, - rg_amo_funct7_8_BITS_6_TO_2_9_EQ_0b10_0_AND_NO_ETC___d294, - rg_lrsc_pa_9_EQ_rg_addr_0___d60, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d102, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d133, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d135, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d138, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d277, - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d290, - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d131, - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d309, - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d443, - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d446, - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d514, - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d69, - rg_state_EQ_12_92_AND_rg_op_5_EQ_0_6_OR_rg_op__ETC___d594, - rg_state_EQ_3_3_AND_NOT_rg_op_5_EQ_0_6_4_AND_N_ETC___d92; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method addr - assign addr = rg_addr ; - - // value method word64 - always@(MUX_dw_output_ld_val$wset_1__SEL_1 or - ld_val__h24164 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h27000 or - MUX_dw_output_ld_val$wset_1__SEL_3 or - MUX_dw_output_ld_val$wset_1__VAL_3 or - MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h24164; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - word64 = new_ld_val__h27000; - MUX_dw_output_ld_val$wset_1__SEL_3: - word64 = MUX_dw_output_ld_val$wset_1__VAL_3; - MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val; - default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // value method st_amo_val - assign st_amo_val = - MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ; - - // value method exc - assign exc = rg_state == 4'd4 ; - - // value method exc_code - assign exc_code = rg_exc_code ; - - // action method server_flush_request_put - assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; - - // action method server_flush_response_get - assign RDY_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; - - // action method tlb_flush - assign RDY_tlb_flush = 1'd1 ; - assign CAN_FIRE_tlb_flush = 1'd1 ; - assign WILL_FIRE_tlb_flush = EN_tlb_flush ; - - // value method mem_master_m_awvalid - assign mem_master_awvalid = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - - // value method mem_master_m_awid - assign mem_master_awid = master_xactor_rg_wr_addr[96:93] ; - - // value method mem_master_m_awaddr - assign mem_master_awaddr = master_xactor_rg_wr_addr[92:29] ; - - // value method mem_master_m_awlen - assign mem_master_awlen = master_xactor_rg_wr_addr[28:21] ; - - // value method mem_master_m_awsize - assign mem_master_awsize = master_xactor_rg_wr_addr[20:18] ; - - // value method mem_master_m_awburst - assign mem_master_awburst = master_xactor_rg_wr_addr[17:16] ; - - // value method mem_master_m_awlock - assign mem_master_awlock = master_xactor_rg_wr_addr[15] ; - - // value method mem_master_m_awcache - assign mem_master_awcache = master_xactor_rg_wr_addr[14:11] ; - - // value method mem_master_m_awprot - assign mem_master_awprot = master_xactor_rg_wr_addr[10:8] ; - - // value method mem_master_m_awqos - assign mem_master_awqos = master_xactor_rg_wr_addr[7:4] ; - - // value method mem_master_m_awregion - assign mem_master_awregion = master_xactor_rg_wr_addr[3:0] ; - - // action method mem_master_m_awready - assign CAN_FIRE_mem_master_m_awready = 1'd1 ; - assign WILL_FIRE_mem_master_m_awready = 1'd1 ; - - // value method mem_master_m_wvalid - assign mem_master_wvalid = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - - // value method mem_master_m_wdata - assign mem_master_wdata = master_xactor_rg_wr_data[72:9] ; - - // value method mem_master_m_wstrb - assign mem_master_wstrb = master_xactor_rg_wr_data[8:1] ; - - // value method mem_master_m_wlast - assign mem_master_wlast = master_xactor_rg_wr_data[0] ; - - // action method mem_master_m_wready - assign CAN_FIRE_mem_master_m_wready = 1'd1 ; - assign WILL_FIRE_mem_master_m_wready = 1'd1 ; - - // action method mem_master_m_bvalid - assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ; - - // value method mem_master_m_bready - assign mem_master_bready = !master_xactor_crg_wr_resp_full$port2__read ; - - // value method mem_master_m_arvalid - assign mem_master_arvalid = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - - // value method mem_master_m_arid - assign mem_master_arid = master_xactor_rg_rd_addr[96:93] ; - - // value method mem_master_m_araddr - assign mem_master_araddr = master_xactor_rg_rd_addr[92:29] ; - - // value method mem_master_m_arlen - assign mem_master_arlen = master_xactor_rg_rd_addr[28:21] ; - - // value method mem_master_m_arsize - assign mem_master_arsize = master_xactor_rg_rd_addr[20:18] ; - - // value method mem_master_m_arburst - assign mem_master_arburst = master_xactor_rg_rd_addr[17:16] ; - - // value method mem_master_m_arlock - assign mem_master_arlock = master_xactor_rg_rd_addr[15] ; - - // value method mem_master_m_arcache - assign mem_master_arcache = master_xactor_rg_rd_addr[14:11] ; - - // value method mem_master_m_arprot - assign mem_master_arprot = master_xactor_rg_rd_addr[10:8] ; - - // value method mem_master_m_arqos - assign mem_master_arqos = master_xactor_rg_rd_addr[7:4] ; - - // value method mem_master_m_arregion - assign mem_master_arregion = master_xactor_rg_rd_addr[3:0] ; - - // action method mem_master_m_arready - assign CAN_FIRE_mem_master_m_arready = 1'd1 ; - assign WILL_FIRE_mem_master_m_arready = 1'd1 ; - - // action method mem_master_m_rvalid - assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ; - - // value method mem_master_m_rready - assign mem_master_rready = !master_xactor_crg_rd_data_full$port2__read ; - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule ram_state_and_ctag_cset - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd7), - .DATA_WIDTH(32'd23), - .MEMSIZE(8'd128)) ram_state_and_ctag_cset(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_state_and_ctag_cset$ADDRA), - .ADDRB(ram_state_and_ctag_cset$ADDRB), - .DIA(ram_state_and_ctag_cset$DIA), - .DIB(ram_state_and_ctag_cset$DIB), - .WEA(ram_state_and_ctag_cset$WEA), - .WEB(ram_state_and_ctag_cset$WEB), - .ENA(ram_state_and_ctag_cset$ENA), - .ENB(ram_state_and_ctag_cset$ENB), - .DOA(), - .DOB(ram_state_and_ctag_cset$DOB)); - - // submodule ram_word64_set - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd9), - .DATA_WIDTH(32'd64), - .MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_word64_set$ADDRA), - .ADDRB(ram_word64_set$ADDRB), - .DIA(ram_word64_set$DIA), - .DIB(ram_word64_set$DIB), - .WEA(ram_word64_set$WEA), - .WEB(ram_word64_set$WEB), - .ENA(ram_word64_set$ENA), - .ENB(ram_word64_set$ENB), - .DOA(), - .DOB(ram_word64_set$DOB)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(soc_map$m_is_mem_addr), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - (rg_cset_in_cache != 7'd127 || - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) && - rg_state == 4'd1 ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // rule RL_rl_shift_sb_to_load_delay - assign CAN_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - assign WILL_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - - // rule RL_rl_rereq - assign CAN_FIRE_RL_rl_rereq = rg_state == 4'd10 ; - assign WILL_FIRE_RL_rl_rereq = - CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ; - - // rule RL_rl_ST_AMO_response - assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 4'd11 ; - assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ; - - // rule RL_rl_maintain_io_read_rsp - assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 4'd14 ; - assign WILL_FIRE_RL_rl_maintain_io_read_rsp = - CAN_FIRE_RL_rl_maintain_io_read_rsp ; - - // rule RL_rl_io_AMO_SC_req - assign CAN_FIRE_RL_rl_io_AMO_SC_req = - rg_state == 4'd12 && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_SC_req = - CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_drive_exception_rsp - assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ; - assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ; - - // rule RL_rl_start_reset - assign CAN_FIRE_RL_rl_start_reset = - f_reset_reqs$EMPTY_N && rg_state != 4'd1 ; - assign WILL_FIRE_RL_rl_start_reset = CAN_FIRE_RL_rl_start_reset ; - - // rule RL_rl_probe_and_immed_rsp - assign CAN_FIRE_RL_rl_probe_and_immed_rsp = - dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d82 && - rg_state_EQ_3_3_AND_NOT_rg_op_5_EQ_0_6_4_AND_N_ETC___d92 ; - assign WILL_FIRE_RL_rl_probe_and_immed_rsp = - CAN_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_cache_refill_rsps_loop - assign CAN_FIRE_RL_rl_cache_refill_rsps_loop = - master_xactor_crg_rd_data_full$port1__read && rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_cache_refill_rsps_loop = - CAN_FIRE_RL_rl_cache_refill_rsps_loop && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_rsp - assign CAN_FIRE_RL_rl_io_read_rsp = - master_xactor_crg_rd_data_full$port1__read && rg_state == 4'd13 ; - assign WILL_FIRE_RL_rl_io_read_rsp = - CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_write_req - assign CAN_FIRE_RL_rl_io_write_req = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - rg_state == 4'd12 && - rg_op == 2'd1 ; - assign WILL_FIRE_RL_rl_io_write_req = - CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_op_req - assign CAN_FIRE_RL_rl_io_AMO_op_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 4'd12 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] != 5'b00010 && - rg_amo_funct7[6:2] != 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_op_req = - CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_read_rsp - assign CAN_FIRE_RL_rl_io_AMO_read_rsp = - master_xactor_crg_rd_data_full_port1__read__53_ETC___d726 && - rg_state == 4'd15 ; - assign WILL_FIRE_RL_rl_io_AMO_read_rsp = - CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_cache_refill - assign CAN_FIRE_RL_rl_start_cache_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 4'd8 && - b__h20932 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_cache_refill = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_io_read_req - assign CAN_FIRE_RL_rl_io_read_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state_EQ_12_92_AND_rg_op_5_EQ_0_6_OR_rg_op__ETC___d594 ; - assign WILL_FIRE_RL_rl_io_read_req = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_discard_write_rsp - assign CAN_FIRE_RL_rl_discard_write_rsp = - b__h20932 != 4'd0 && master_xactor_crg_wr_resp_full$port1__read ; - assign WILL_FIRE_RL_rl_discard_write_rsp = - CAN_FIRE_RL_rl_discard_write_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // inputs to muxes for submodule ports - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 ; - assign MUX_dw_output_ld_val$wset_1__SEL_1 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_dw_output_ld_val$wset_1__SEL_3 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d138 ; - assign MUX_dw_output_ld_val$wset_1__SEL_4 = - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_1 = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ; - assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 = - EN_req && - req_f3_BITS_1_TO_0_93_EQ_0b0_94_OR_req_f3_BITS_ETC___d923 ; - assign MUX_ram_word64_set$a_put_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ram_word64_set$b_put_1__SEL_2 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 ; - assign MUX_rg_error_during_refill$write_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_1 = - EN_req && - NOT_req_f3_BITS_1_TO_0_93_EQ_0b0_94_95_AND_NOT_ETC___d914 ; - assign MUX_rg_exc_code$write_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_3 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_ld_val$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d300 ; - assign MUX_rg_lrsc_valid$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d133 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ; - assign MUX_rg_state$write_1__SEL_3 = - CAN_FIRE_RL_rl_start_cache_refill && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - assign MUX_rg_state$write_1__SEL_8 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 ; - assign MUX_rg_state$write_1__SEL_9 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (dmem_not_imem && !soc_map$m_is_mem_addr || - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d102 || - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d107) ; - assign MUX_rg_state$write_1__SEL_13 = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 = - ctr_wr_rsps_pending_crg + 4'd1 ; - assign MUX_dw_output_ld_val$wset_1__VAL_3 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - new_value__h5462 : - new_value__h15491 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, - mem_req_wr_addr_awaddr__h27062, - 8'd0, - value__h26585, - 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, cline_fabric_addr__h21031, 29'd7143424 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_1 = - { 4'd0, - mem_req_wr_addr_awaddr__h27062, - 8'd0, - value__h29610, - 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_2 = - { 4'd0, - mem_req_wr_addr_awaddr__h20126, - 8'd0, - value__h29610, - 18'd65536 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_1 = - { mem_req_wr_data_wdata__h27267, - mem_req_wr_data_wstrb__h27268, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_2 = - { IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d468, - mem_req_wr_data_wstrb__h20332, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_3 = - { mem_req_wr_data_wdata__h25765, - mem_req_wr_data_wstrb__h27268, - 1'd1 } ; - assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 = { 3'd4, rg_pa[31:12] } ; - assign MUX_ram_word64_set$a_put_3__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 : - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 ; - assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ; - assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:5], 2'd0 } ; - assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 7'd1 ; - assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ; - assign MUX_rg_ld_val$write_1__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - x__h13143 : - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 ; - assign MUX_rg_state$write_1__VAL_1 = - NOT_req_f3_BITS_1_TO_0_93_EQ_0b0_94_95_AND_NOT_ETC___d914 ? - 4'd4 : - 4'd3 ; - assign MUX_rg_state$write_1__VAL_4 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? 4'd14 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_8 = - (master_xactor_rg_rd_data[2:1] != 2'b0 || - rg_error_during_refill) ? - 4'd4 : - 4'd10 ; - assign MUX_rg_state$write_1__VAL_9 = - (dmem_not_imem && !soc_map$m_is_mem_addr) ? - 4'd12 : - IF_rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d112 ; - - // inlined wires - assign dw_valid$whas = - (WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_io_read_rsp) && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d138 || - WILL_FIRE_RL_rl_drive_exception_rsp || - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign master_xactor_crg_wr_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_addr_full$port1__read = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full$port1__read && - mem_master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full$port1__read ; - assign master_xactor_crg_wr_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 || - WILL_FIRE_RL_rl_io_write_req ; - assign master_xactor_crg_wr_addr_full$port3__read = - master_xactor_crg_wr_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_data_full$port1__read = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full$port1__read && mem_master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full$port1__read ; - assign master_xactor_crg_wr_data_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 || - WILL_FIRE_RL_rl_io_write_req ; - assign master_xactor_crg_wr_data_full$port3__read = - master_xactor_crg_wr_data_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_wr_resp_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_resp_full$port1__read = - !master_xactor_crg_wr_resp_full$EN_port0__write && - master_xactor_crg_wr_resp_full ; - assign master_xactor_crg_wr_resp_full$port2__read = - !WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_crg_wr_resp_full$port1__read ; - assign master_xactor_crg_wr_resp_full$EN_port2__write = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_wr_resp_full$port3__read = - master_xactor_crg_wr_resp_full$EN_port2__write || - master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_addr_full$port1__read = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full$port1__read && - mem_master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full$port1__read ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write || - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_data_full$port1__read = - !master_xactor_crg_rd_data_full$EN_port0__write && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port1__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp || WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_cache_refill_rsps_loop ; - assign master_xactor_crg_rd_data_full$port2__read = - !master_xactor_crg_rd_data_full$EN_port1__write && - master_xactor_crg_rd_data_full$port1__read ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - mem_master_rvalid && - !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - assign ctr_wr_rsps_pending_crg$EN_port0__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 || - WILL_FIRE_RL_rl_io_write_req ; - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - WILL_FIRE_RL_rl_io_write_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - WILL_FIRE_RL_rl_io_write_req: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - default: ctr_wr_rsps_pending_crg$port0__write_1 = - 4'b1010 /* unspecified value */ ; - endcase - end - assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h20932 - 4'd1 ; - assign ctr_wr_rsps_pending_crg$port2__read = - WILL_FIRE_RL_rl_discard_write_rsp ? - ctr_wr_rsps_pending_crg$port1__write_1 : - b__h20932 ; - assign ctr_wr_rsps_pending_crg$EN_port2__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign ctr_wr_rsps_pending_crg$port3__read = - ctr_wr_rsps_pending_crg$EN_port2__write ? - 4'd0 : - ctr_wr_rsps_pending_crg$port2__read ; - assign crg_sb_to_load_delay$port0__write_1 = - { 1'd0, crg_sb_to_load_delay[10:1] } ; - assign crg_sb_to_load_delay$EN_port1__write = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d445 ; - assign crg_sb_to_load_delay$port2__read = - crg_sb_to_load_delay$EN_port1__write ? - 11'd2047 : - crg_sb_to_load_delay$port0__write_1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register crg_sb_to_load_delay - assign crg_sb_to_load_delay$D_IN = crg_sb_to_load_delay$port2__read ; - assign crg_sb_to_load_delay$EN = 1'b1 ; - - // register ctr_wr_rsps_pending_crg - assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ; - assign ctr_wr_rsps_pending_crg$EN = 1'b1 ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = - master_xactor_crg_wr_resp_full$port3__read ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - assign master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__SEL_1 ? - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 : - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ; - assign master_xactor_rg_rd_addr$EN = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - default: master_xactor_rg_wr_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_addr$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_data - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_data$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_data$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req or - MUX_master_xactor_rg_wr_data$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - default: master_xactor_rg_wr_data$D_IN = - 73'h0AAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_data$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = - { mem_master_bid, mem_master_bresp } ; - assign master_xactor_rg_wr_resp$EN = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - - // register rg_addr - assign rg_addr$D_IN = req_addr ; - assign rg_addr$EN = EN_req ; - - // register rg_amo_funct7 - assign rg_amo_funct7$D_IN = req_amo_funct7 ; - assign rg_amo_funct7$EN = EN_req ; - - // register rg_cset_in_cache - assign rg_cset_in_cache$D_IN = - WILL_FIRE_RL_rl_reset ? - MUX_rg_cset_in_cache$write_1__VAL_1 : - 7'd0 ; - assign rg_cset_in_cache$EN = - WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ; - - // register rg_error_during_refill - assign rg_error_during_refill$D_IN = - MUX_rg_error_during_refill$write_1__SEL_1 ; - assign rg_error_during_refill$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register rg_exc_code - always@(MUX_rg_exc_code$write_1__SEL_1 or - MUX_rg_exc_code$write_1__VAL_1 or - MUX_rg_exc_code$write_1__SEL_2 or - MUX_rg_exc_code$write_1__SEL_3 or - MUX_rg_error_during_refill$write_1__SEL_1 or access_exc_code__h2925) - case (1'b1) - MUX_rg_exc_code$write_1__SEL_1: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1; - MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7; - MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5; - MUX_rg_error_during_refill$write_1__SEL_1: - rg_exc_code$D_IN = access_exc_code__h2925; - default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_exc_code$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - EN_req && - NOT_req_f3_BITS_1_TO_0_93_EQ_0b0_94_95_AND_NOT_ETC___d914 ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_ld_val - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h27000 or - MUX_rg_ld_val$write_1__SEL_2 or - MUX_rg_ld_val$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_rsp or - ld_val__h24164 or WILL_FIRE_RL_rl_io_AMO_SC_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - rg_ld_val$D_IN = new_ld_val__h27000; - MUX_rg_ld_val$write_1__SEL_2: - rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h24164; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1; - default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_ld_val$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d300 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_SC_req ; - - // register rg_lower_word32 - assign rg_lower_word32$D_IN = 32'h0 ; - assign rg_lower_word32$EN = 1'b0 ; - - // register rg_lower_word32_full - assign rg_lower_word32_full$D_IN = 1'd0 ; - assign rg_lower_word32_full$EN = - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_lrsc_pa - assign rg_lrsc_pa$D_IN = rg_addr ; - assign rg_lrsc_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 ; - - // register rg_lrsc_valid - assign rg_lrsc_valid$D_IN = - MUX_rg_lrsc_valid$write_1__SEL_2 && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d135 ; - assign rg_lrsc_valid$EN = - WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d133 || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_op - assign rg_op$D_IN = req_op ; - assign rg_op$EN = EN_req ; - - // register rg_pa - assign rg_pa$D_IN = EN_req ? req_addr : rg_addr ; - assign rg_pa$EN = EN_req || WILL_FIRE_RL_rl_probe_and_immed_rsp ; - - // register rg_pte_pa - assign rg_pte_pa$D_IN = 32'h0 ; - assign rg_pte_pa$EN = 1'b0 ; - - // register rg_st_amo_val - assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h17350 ; - assign rg_st_amo_val$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d535 || - EN_req ; - - // register rg_state - always@(EN_req or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_io_read_req or - WILL_FIRE_RL_rl_start_cache_refill or - WILL_FIRE_RL_rl_io_AMO_read_rsp or - MUX_rg_state$write_1__VAL_4 or - WILL_FIRE_RL_rl_io_AMO_op_req or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_io_read_rsp or - MUX_rg_state$write_1__SEL_8 or - MUX_rg_state$write_1__VAL_8 or - MUX_rg_state$write_1__SEL_9 or - MUX_rg_state$write_1__VAL_9 or - WILL_FIRE_RL_rl_start_reset or - WILL_FIRE_RL_rl_io_AMO_SC_req or - WILL_FIRE_RL_rl_rereq or MUX_rg_state$write_1__SEL_13) - case (1'b1) - EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 4'd13; - WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_io_AMO_read_rsp: - rg_state$D_IN = MUX_rg_state$write_1__VAL_4; - WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 4'd15; - WILL_FIRE_RL_rl_io_write_req: rg_state$D_IN = 4'd11; - WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_4; - MUX_rg_state$write_1__SEL_8: rg_state$D_IN = MUX_rg_state$write_1__VAL_8; - MUX_rg_state$write_1__SEL_9: rg_state$D_IN = MUX_rg_state$write_1__VAL_9; - WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 4'd1; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_state$D_IN = 4'd11; - WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_13: rg_state$D_IN = 4'd2; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_state$EN = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 || - MUX_rg_state$write_1__SEL_9 || - WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_io_read_rsp || - EN_req || - WILL_FIRE_RL_rl_start_reset || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_io_AMO_SC_req || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_io_AMO_op_req ; - - // register rg_word64_set_in_cache - assign rg_word64_set_in_cache$D_IN = - MUX_ram_word64_set$b_put_1__SEL_2 ? - MUX_ram_word64_set$b_put_2__VAL_2 : - MUX_ram_word64_set$b_put_2__VAL_4 ; - assign rg_word64_set_in_cache$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = !EN_server_reset_request_put ; - assign f_reset_reqs$ENQ = - EN_server_reset_request_put || EN_server_flush_request_put ; - assign f_reset_reqs$DEQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ; - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 ; - assign f_reset_rsps$DEQ = - EN_server_flush_response_get || EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule ram_state_and_ctag_cset - assign ram_state_and_ctag_cset$ADDRA = - WILL_FIRE_RL_rl_start_cache_refill ? - rg_addr[11:5] : - rg_cset_in_cache ; - assign ram_state_and_ctag_cset$ADDRB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - req_addr[11:5] : - rg_addr[11:5] ; - assign ram_state_and_ctag_cset$DIA = - WILL_FIRE_RL_rl_start_cache_refill ? - MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 : - 23'd2796202 ; - assign ram_state_and_ctag_cset$DIB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - 23'b01010101010101010101010 /* unspecified value */ : - 23'b01010101010101010101010 /* unspecified value */ ; - assign ram_state_and_ctag_cset$WEA = 1'd1 ; - assign ram_state_and_ctag_cset$WEB = 1'd0 ; - assign ram_state_and_ctag_cset$ENA = - WILL_FIRE_RL_rl_start_cache_refill || WILL_FIRE_RL_rl_reset ; - assign ram_state_and_ctag_cset$ENB = - EN_req && - req_f3_BITS_1_TO_0_93_EQ_0b0_94_OR_req_f3_BITS_ETC___d923 || - WILL_FIRE_RL_rl_rereq ; - - // submodule ram_word64_set - assign ram_word64_set$ADDRA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - rg_word64_set_in_cache : - rg_addr[11:3] ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - req_addr or - MUX_ram_word64_set$b_put_1__SEL_2 or - MUX_ram_word64_set$b_put_2__VAL_2 or - WILL_FIRE_RL_rl_rereq or - rg_addr or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_ram_word64_set$b_put_2__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$ADDRB = req_addr[11:3]; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2; - WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3]; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4; - default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ; - endcase - end - assign ram_word64_set$DIA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - master_xactor_rg_rd_data[66:3] : - MUX_ram_word64_set$a_put_3__VAL_2 ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - MUX_ram_word64_set$b_put_1__SEL_2 or - WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_rereq: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - default: ram_word64_set$DIB = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign ram_word64_set$WEA = 1'd1 ; - assign ram_word64_set$WEB = 1'd0 ; - assign ram_word64_set$ENA = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d311 ; - assign ram_word64_set$ENB = - EN_req && - req_f3_BITS_1_TO_0_93_EQ_0b0_94_OR_req_f3_BITS_ETC___d923 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] != 2'd3 || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = { 32'd0, rg_addr } ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_1_EL_ETC___d273 = - (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d803 = - (rg_addr[2:0] == 3'h0) ? ld_val__h24164 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259 = - (rg_addr[2:0] == 3'h0) ? word64__h5280 : 64'd0 ; - assign IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 = - (rg_f3 == 3'b010) ? - { {32{rg_st_amo_val_BITS_31_TO_0__q31[31]}}, - rg_st_amo_val_BITS_31_TO_0__q31 } : - rg_st_amo_val ; - assign IF_rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d112 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd8 : - IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d111 ; - assign IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d111 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - 4'd11 : - ((!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) ? - 4'd8 : - 4'd11) ; - assign IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d468 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - mem_req_wr_data_wdata__h16836 : - mem_req_wr_data_wdata__h20331 ; - assign IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d80 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d69 : - !ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read ; - assign NOT_cfg_verbosity_read__0_ULE_1_1___d12 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read__0_ULE_2_56___d557 = cfg_verbosity > 4'd2 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d300 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - rg_op != 2'd1 && ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d311 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d309 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d445 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d443 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d480 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 && - rg_addr_0_EQ_rg_lrsc_pa_9___d119 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d492 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d520 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d518 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d521 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d527 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d525 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d533 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d531 ; - assign NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d535 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d308 ; - assign NOT_ram_state_and_ctag_cset_b_read__0_BIT_22_1_ETC___d121 = - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - rg_addr_0_EQ_rg_lrsc_pa_9___d119 ; - assign NOT_req_f3_BITS_1_TO_0_93_EQ_0b0_94_95_AND_NOT_ETC___d914 = - req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && - (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && - (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; - assign NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d107 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) ; - assign NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d448 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d446 || - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d308) ; - assign NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d495 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d493 ; - assign NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d501 ; - assign NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d508 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d506 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d130 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - rg_addr_0_EQ_rg_lrsc_pa_9___d119 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d308 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d442 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d518 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d521 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d525 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d531 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - rg_addr_0_EQ_rg_lrsc_pa_9___d119 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d306 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d440 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d493 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d497 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d501 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d506 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign _theResult___snd_fst__h16844 = rg_st_amo_val << shift_bits__h20132 ; - assign _theResult___snd_fst__h20339 = - new_st_val__h17350 << shift_bits__h20132 ; - assign _theResult___snd_fst__h25773 = rg_st_amo_val << shift_bits__h27068 ; - assign _theResult___snd_fst__h27275 = st_val__h27012 << shift_bits__h27068 ; - assign access_exc_code__h2925 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd5 : - 4'd7) : - 4'd1 ; - assign b__h20932 = - ctr_wr_rsps_pending_crg$EN_port0__write ? - ctr_wr_rsps_pending_crg$port0__write_1 : - ctr_wr_rsps_pending_crg ; - assign cline_addr__h21030 = { rg_pa[31:5], 5'd0 } ; - assign cline_fabric_addr__h21031 = { 32'd0, cline_addr__h21030 } ; - assign dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_0__ETC___d82 = - dmem_not_imem && !soc_map$m_is_mem_addr || rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - IF_rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_ETC___d80 ; - assign ld_val4164_BITS_15_TO_0__q36 = ld_val__h24164[15:0] ; - assign ld_val4164_BITS_15_TO_8__q38 = ld_val__h24164[15:8] ; - assign ld_val4164_BITS_23_TO_16__q39 = ld_val__h24164[23:16] ; - assign ld_val4164_BITS_31_TO_0__q37 = ld_val__h24164[31:0] ; - assign ld_val4164_BITS_31_TO_16__q40 = ld_val__h24164[31:16] ; - assign ld_val4164_BITS_31_TO_24__q41 = ld_val__h24164[31:24] ; - assign ld_val4164_BITS_39_TO_32__q42 = ld_val__h24164[39:32] ; - assign ld_val4164_BITS_47_TO_32__q43 = ld_val__h24164[47:32] ; - assign ld_val4164_BITS_47_TO_40__q45 = ld_val__h24164[47:40] ; - assign ld_val4164_BITS_55_TO_48__q46 = ld_val__h24164[55:48] ; - assign ld_val4164_BITS_63_TO_32__q44 = ld_val__h24164[63:32] ; - assign ld_val4164_BITS_63_TO_48__q47 = ld_val__h24164[63:48] ; - assign ld_val4164_BITS_63_TO_56__q48 = ld_val__h24164[63:56] ; - assign ld_val4164_BITS_7_TO_0__q35 = ld_val__h24164[7:0] ; - assign lrsc_result__h13133 = - !rg_lrsc_valid || !rg_lrsc_pa_9_EQ_rg_addr_0___d60 ; - assign master_xactor_crg_rd_data_full_port1__read__53_ETC___d726 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; - assign master_xactor_rg_rd_data_BITS_10_TO_3__q1 = - master_xactor_rg_rd_data[10:3] ; - assign master_xactor_rg_rd_data_BITS_18_TO_11__q4 = - master_xactor_rg_rd_data[18:11] ; - assign master_xactor_rg_rd_data_BITS_18_TO_3__q3 = - master_xactor_rg_rd_data[18:3] ; - assign master_xactor_rg_rd_data_BITS_26_TO_19__q5 = - master_xactor_rg_rd_data[26:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_19__q6 = - master_xactor_rg_rd_data[34:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_27__q7 = - master_xactor_rg_rd_data[34:27] ; - assign master_xactor_rg_rd_data_BITS_34_TO_3__q2 = - master_xactor_rg_rd_data[34:3] ; - assign master_xactor_rg_rd_data_BITS_42_TO_35__q8 = - master_xactor_rg_rd_data[42:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_35__q9 = - master_xactor_rg_rd_data[50:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_43__q11 = - master_xactor_rg_rd_data[50:43] ; - assign master_xactor_rg_rd_data_BITS_58_TO_51__q12 = - master_xactor_rg_rd_data[58:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_35__q10 = - master_xactor_rg_rd_data[66:35] ; - assign master_xactor_rg_rd_data_BITS_66_TO_51__q13 = - master_xactor_rg_rd_data[66:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_59__q14 = - master_xactor_rg_rd_data[66:59] ; - assign mem_req_wr_addr_awaddr__h20126 = { 32'd0, rg_addr } ; - assign mem_req_wr_addr_awaddr__h27062 = { 32'd0, rg_pa } ; - assign new_st_val__h17350 = - (rg_f3 == 3'b010) ? - new_st_val__h17632 : - _theResult_____2__h17628 ; - assign new_st_val__h17632 = { 32'd0, _theResult_____2__h17628[31:0] } ; - assign new_st_val__h17723 = - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 + - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ; - assign new_st_val__h18703 = w1__h17620 ^ w2__h27286 ; - assign new_st_val__h18707 = w1__h17620 & w2__h27286 ; - assign new_st_val__h18711 = w1__h17620 | w2__h27286 ; - assign new_st_val__h18715 = - (w1__h17620 < w2__h27286) ? w1__h17620 : w2__h27286 ; - assign new_st_val__h18720 = - (w1__h17620 <= w2__h27286) ? w2__h27286 : w1__h17620 ; - assign new_st_val__h18726 = - ((IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 ^ - 64'h8000000000000000) < - (IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ^ - 64'h8000000000000000)) ? - w1__h17620 : - w2__h27286 ; - assign new_st_val__h18731 = - ((IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 ^ - 64'h8000000000000000) <= - (IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ^ - 64'h8000000000000000)) ? - w2__h27286 : - w1__h17620 ; - assign new_st_val__h27296 = { 32'd0, _theResult_____2__h27292[31:0] } ; - assign new_st_val__h27387 = - new_ld_val__h27000 + - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ; - assign new_st_val__h29247 = w1__h27284 ^ w2__h27286 ; - assign new_st_val__h29251 = w1__h27284 & w2__h27286 ; - assign new_st_val__h29255 = w1__h27284 | w2__h27286 ; - assign new_st_val__h29259 = - (w1__h27284 < w2__h27286) ? w1__h27284 : w2__h27286 ; - assign new_st_val__h29264 = - (w1__h27284 <= w2__h27286) ? w2__h27286 : w1__h27284 ; - assign new_st_val__h29270 = - ((new_ld_val__h27000 ^ 64'h8000000000000000) < - (IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ^ - 64'h8000000000000000)) ? - w1__h27284 : - w2__h27286 ; - assign new_st_val__h29275 = - ((new_ld_val__h27000 ^ 64'h8000000000000000) <= - (IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_rg_st_amo_val_ETC___d368 ^ - 64'h8000000000000000)) ? - w2__h27286 : - w1__h27284 ; - assign new_value462_BITS_31_TO_0__q30 = new_value__h5462[31:0] ; - assign pa_ctag__h5138 = { 2'd0, rg_addr[31:12] } ; - assign ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 = - ram_state_and_ctag_cset$DOB[21:0] == pa_ctag__h5138 ; - assign ram_state_and_ctag_cset_b_read__0_BIT_22_1_AND_ETC___d122 = - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - NOT_ram_state_and_ctag_cset_b_read__0_BIT_22_1_ETC___d121 ; - assign req_f3_BITS_1_TO_0_93_EQ_0b0_94_OR_req_f3_BITS_ETC___d923 = - req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || - req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || - req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; - assign result__h11873 = - { {56{word64280_BITS_15_TO_8__q18[7]}}, - word64280_BITS_15_TO_8__q18 } ; - assign result__h11901 = - { {56{word64280_BITS_23_TO_16__q19[7]}}, - word64280_BITS_23_TO_16__q19 } ; - assign result__h11929 = - { {56{word64280_BITS_31_TO_24__q21[7]}}, - word64280_BITS_31_TO_24__q21 } ; - assign result__h11957 = - { {56{word64280_BITS_39_TO_32__q22[7]}}, - word64280_BITS_39_TO_32__q22 } ; - assign result__h11985 = - { {56{word64280_BITS_47_TO_40__q25[7]}}, - word64280_BITS_47_TO_40__q25 } ; - assign result__h12013 = - { {56{word64280_BITS_55_TO_48__q26[7]}}, - word64280_BITS_55_TO_48__q26 } ; - assign result__h12041 = - { {56{word64280_BITS_63_TO_56__q28[7]}}, - word64280_BITS_63_TO_56__q28 } ; - assign result__h12086 = { 56'd0, word64__h5280[7:0] } ; - assign result__h12114 = { 56'd0, word64__h5280[15:8] } ; - assign result__h12142 = { 56'd0, word64__h5280[23:16] } ; - assign result__h12170 = { 56'd0, word64__h5280[31:24] } ; - assign result__h12198 = { 56'd0, word64__h5280[39:32] } ; - assign result__h12226 = { 56'd0, word64__h5280[47:40] } ; - assign result__h12254 = { 56'd0, word64__h5280[55:48] } ; - assign result__h12282 = { 56'd0, word64__h5280[63:56] } ; - assign result__h12327 = - { {48{word64280_BITS_15_TO_0__q16[15]}}, - word64280_BITS_15_TO_0__q16 } ; - assign result__h12355 = - { {48{word64280_BITS_31_TO_16__q20[15]}}, - word64280_BITS_31_TO_16__q20 } ; - assign result__h12383 = - { {48{word64280_BITS_47_TO_32__q23[15]}}, - word64280_BITS_47_TO_32__q23 } ; - assign result__h12411 = - { {48{word64280_BITS_63_TO_48__q27[15]}}, - word64280_BITS_63_TO_48__q27 } ; - assign result__h12452 = { 48'd0, word64__h5280[15:0] } ; - assign result__h12480 = { 48'd0, word64__h5280[31:16] } ; - assign result__h12508 = { 48'd0, word64__h5280[47:32] } ; - assign result__h12536 = { 48'd0, word64__h5280[63:48] } ; - assign result__h12577 = - { {32{word64280_BITS_31_TO_0__q17[31]}}, - word64280_BITS_31_TO_0__q17 } ; - assign result__h12605 = - { {32{word64280_BITS_63_TO_32__q24[31]}}, - word64280_BITS_63_TO_32__q24 } ; - assign result__h12644 = { 32'd0, word64__h5280[31:0] } ; - assign result__h12672 = { 32'd0, word64__h5280[63:32] } ; - assign result__h24224 = - { {56{master_xactor_rg_rd_data_BITS_10_TO_3__q1[7]}}, - master_xactor_rg_rd_data_BITS_10_TO_3__q1 } ; - assign result__h24254 = - { {56{master_xactor_rg_rd_data_BITS_18_TO_11__q4[7]}}, - master_xactor_rg_rd_data_BITS_18_TO_11__q4 } ; - assign result__h24281 = - { {56{master_xactor_rg_rd_data_BITS_26_TO_19__q5[7]}}, - master_xactor_rg_rd_data_BITS_26_TO_19__q5 } ; - assign result__h24308 = - { {56{master_xactor_rg_rd_data_BITS_34_TO_27__q7[7]}}, - master_xactor_rg_rd_data_BITS_34_TO_27__q7 } ; - assign result__h24335 = - { {56{master_xactor_rg_rd_data_BITS_42_TO_35__q8[7]}}, - master_xactor_rg_rd_data_BITS_42_TO_35__q8 } ; - assign result__h24362 = - { {56{master_xactor_rg_rd_data_BITS_50_TO_43__q11[7]}}, - master_xactor_rg_rd_data_BITS_50_TO_43__q11 } ; - assign result__h24389 = - { {56{master_xactor_rg_rd_data_BITS_58_TO_51__q12[7]}}, - master_xactor_rg_rd_data_BITS_58_TO_51__q12 } ; - assign result__h24416 = - { {56{master_xactor_rg_rd_data_BITS_66_TO_59__q14[7]}}, - master_xactor_rg_rd_data_BITS_66_TO_59__q14 } ; - assign result__h24460 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h24487 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h24514 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h24541 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h24568 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h24595 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h24622 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h24649 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h24693 = - { {48{master_xactor_rg_rd_data_BITS_18_TO_3__q3[15]}}, - master_xactor_rg_rd_data_BITS_18_TO_3__q3 } ; - assign result__h24720 = - { {48{master_xactor_rg_rd_data_BITS_34_TO_19__q6[15]}}, - master_xactor_rg_rd_data_BITS_34_TO_19__q6 } ; - assign result__h24747 = - { {48{master_xactor_rg_rd_data_BITS_50_TO_35__q9[15]}}, - master_xactor_rg_rd_data_BITS_50_TO_35__q9 } ; - assign result__h24774 = - { {48{master_xactor_rg_rd_data_BITS_66_TO_51__q13[15]}}, - master_xactor_rg_rd_data_BITS_66_TO_51__q13 } ; - assign result__h24814 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h24841 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h24868 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h24895 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h24935 = - { {32{master_xactor_rg_rd_data_BITS_34_TO_3__q2[31]}}, - master_xactor_rg_rd_data_BITS_34_TO_3__q2 } ; - assign result__h24962 = - { {32{master_xactor_rg_rd_data_BITS_66_TO_35__q10[31]}}, - master_xactor_rg_rd_data_BITS_66_TO_35__q10 } ; - assign result__h25000 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h25027 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; - assign result__h27475 = - { {56{ld_val4164_BITS_7_TO_0__q35[7]}}, - ld_val4164_BITS_7_TO_0__q35 } ; - assign result__h28383 = - { {56{ld_val4164_BITS_15_TO_8__q38[7]}}, - ld_val4164_BITS_15_TO_8__q38 } ; - assign result__h28411 = - { {56{ld_val4164_BITS_23_TO_16__q39[7]}}, - ld_val4164_BITS_23_TO_16__q39 } ; - assign result__h28439 = - { {56{ld_val4164_BITS_31_TO_24__q41[7]}}, - ld_val4164_BITS_31_TO_24__q41 } ; - assign result__h28467 = - { {56{ld_val4164_BITS_39_TO_32__q42[7]}}, - ld_val4164_BITS_39_TO_32__q42 } ; - assign result__h28495 = - { {56{ld_val4164_BITS_47_TO_40__q45[7]}}, - ld_val4164_BITS_47_TO_40__q45 } ; - assign result__h28523 = - { {56{ld_val4164_BITS_55_TO_48__q46[7]}}, - ld_val4164_BITS_55_TO_48__q46 } ; - assign result__h28551 = - { {56{ld_val4164_BITS_63_TO_56__q48[7]}}, - ld_val4164_BITS_63_TO_56__q48 } ; - assign result__h28596 = { 56'd0, ld_val__h24164[7:0] } ; - assign result__h28624 = { 56'd0, ld_val__h24164[15:8] } ; - assign result__h28652 = { 56'd0, ld_val__h24164[23:16] } ; - assign result__h28680 = { 56'd0, ld_val__h24164[31:24] } ; - assign result__h28708 = { 56'd0, ld_val__h24164[39:32] } ; - assign result__h28736 = { 56'd0, ld_val__h24164[47:40] } ; - assign result__h28764 = { 56'd0, ld_val__h24164[55:48] } ; - assign result__h28792 = { 56'd0, ld_val__h24164[63:56] } ; - assign result__h28837 = - { {48{ld_val4164_BITS_15_TO_0__q36[15]}}, - ld_val4164_BITS_15_TO_0__q36 } ; - assign result__h28865 = - { {48{ld_val4164_BITS_31_TO_16__q40[15]}}, - ld_val4164_BITS_31_TO_16__q40 } ; - assign result__h28893 = - { {48{ld_val4164_BITS_47_TO_32__q43[15]}}, - ld_val4164_BITS_47_TO_32__q43 } ; - assign result__h28921 = - { {48{ld_val4164_BITS_63_TO_48__q47[15]}}, - ld_val4164_BITS_63_TO_48__q47 } ; - assign result__h28962 = { 48'd0, ld_val__h24164[15:0] } ; - assign result__h28990 = { 48'd0, ld_val__h24164[31:16] } ; - assign result__h29018 = { 48'd0, ld_val__h24164[47:32] } ; - assign result__h29046 = { 48'd0, ld_val__h24164[63:48] } ; - assign result__h29087 = - { {32{ld_val4164_BITS_31_TO_0__q37[31]}}, - ld_val4164_BITS_31_TO_0__q37 } ; - assign result__h29115 = - { {32{ld_val4164_BITS_63_TO_32__q44[31]}}, - ld_val4164_BITS_63_TO_32__q44 } ; - assign result__h29154 = { 32'd0, ld_val__h24164[31:0] } ; - assign result__h29182 = { 32'd0, ld_val__h24164[63:32] } ; - assign result__h5517 = - { {56{word64280_BITS_7_TO_0__q15[7]}}, - word64280_BITS_7_TO_0__q15 } ; - assign rg_addr_0_EQ_rg_lrsc_pa_9___d119 = rg_addr == rg_lrsc_pa ; - assign rg_amo_funct7_8_BITS_6_TO_2_9_EQ_0b10_0_AND_NO_ETC___d294 = - rg_amo_funct7[6:2] == 5'b00010 && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) && - rg_addr_0_EQ_rg_lrsc_pa_9___d119 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_lrsc_pa_9_EQ_rg_addr_0___d60 = rg_lrsc_pa == rg_addr ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d102 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d133 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset_b_read__0_BIT_22_1_AND_ETC___d122 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d131 ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d135 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d138 = - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d135 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13133 ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d277 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d290 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[22] || - !ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d131 = - rg_op == 2'd1 && rg_addr_0_EQ_rg_lrsc_pa_9___d119 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d130 ; - assign rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d309 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d306 || - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d308 ; - assign rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d443 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d440 || - NOT_rg_op_5_EQ_1_3_27_AND_NOT_rg_op_5_EQ_2_7_5_ETC___d442 ; - assign rg_op_5_EQ_1_3_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d446 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_9_EQ_rg_addr_0___d60) ; - assign rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d514 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13133 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d69 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13133 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read ; - assign rg_st_amo_val_BITS_31_TO_0__q31 = rg_st_amo_val[31:0] ; - assign rg_state_EQ_12_92_AND_rg_op_5_EQ_0_6_OR_rg_op__ETC___d594 = - rg_state == 4'd12 && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - b__h20932 == 4'd0 ; - assign rg_state_EQ_3_3_AND_NOT_rg_op_5_EQ_0_6_4_AND_N_ETC___d92 = - rg_state == 4'd3 && - (rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - crg_sb_to_load_delay$port0__write_1 == 11'd0) ; - assign shift_bits__h20132 = { rg_addr[2:0], 3'b0 } ; - assign shift_bits__h27068 = { rg_pa[2:0], 3'b0 } ; - assign st_val__h27012 = - (rg_f3 == 3'b010) ? - new_st_val__h27296 : - _theResult_____2__h27292 ; - assign strobe64__h20265 = 8'b00000001 << rg_addr[2:0] ; - assign strobe64__h20267 = 8'b00000011 << rg_addr[2:0] ; - assign strobe64__h20269 = 8'b00001111 << rg_addr[2:0] ; - assign strobe64__h27201 = 8'b00000001 << rg_pa[2:0] ; - assign strobe64__h27203 = 8'b00000011 << rg_pa[2:0] ; - assign strobe64__h27205 = 8'b00001111 << rg_pa[2:0] ; - assign w17280_BITS_31_TO_0__q50 = w1__h27280[31:0] ; - assign w1___1__h17691 = { 32'd0, new_value__h5462[31:0] } ; - assign w1___1__h27355 = { 32'd0, w1__h27280[31:0] } ; - assign w2___1__h27356 = { 32'd0, rg_st_amo_val[31:0] } ; - assign w2__h27286 = (rg_f3 == 3'b010) ? w2___1__h27356 : rg_st_amo_val ; - assign word64280_BITS_15_TO_0__q16 = word64__h5280[15:0] ; - assign word64280_BITS_15_TO_8__q18 = word64__h5280[15:8] ; - assign word64280_BITS_23_TO_16__q19 = word64__h5280[23:16] ; - assign word64280_BITS_31_TO_0__q17 = word64__h5280[31:0] ; - assign word64280_BITS_31_TO_16__q20 = word64__h5280[31:16] ; - assign word64280_BITS_31_TO_24__q21 = word64__h5280[31:24] ; - assign word64280_BITS_39_TO_32__q22 = word64__h5280[39:32] ; - assign word64280_BITS_47_TO_32__q23 = word64__h5280[47:32] ; - assign word64280_BITS_47_TO_40__q25 = word64__h5280[47:40] ; - assign word64280_BITS_55_TO_48__q26 = word64__h5280[55:48] ; - assign word64280_BITS_63_TO_32__q24 = word64__h5280[63:32] ; - assign word64280_BITS_63_TO_48__q27 = word64__h5280[63:48] ; - assign word64280_BITS_63_TO_56__q28 = word64__h5280[63:56] ; - assign word64280_BITS_7_TO_0__q15 = word64__h5280[7:0] ; - assign word64__h5280 = ram_word64_set$DOB & y__h5553 ; - assign x__h13143 = { 63'd0, lrsc_result__h13133 } ; - assign y__h5553 = - {64{ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76}} ; - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h26585 = 3'b0; - 2'b01: value__h26585 = 3'b001; - 2'b10: value__h26585 = 3'b010; - 2'd3: value__h26585 = 3'b011; - endcase - end - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h29610 = 3'b0; - 2'b01: value__h29610 = 3'b001; - 2'b10: value__h29610 = 3'b010; - 2'b11: value__h29610 = 3'b011; - endcase - end - always@(rg_f3 or strobe64__h27201 or strobe64__h27203 or strobe64__h27205) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h27268 = strobe64__h27201; - 2'b01: mem_req_wr_data_wstrb__h27268 = strobe64__h27203; - 2'b10: mem_req_wr_data_wstrb__h27268 = strobe64__h27205; - 2'b11: mem_req_wr_data_wstrb__h27268 = 8'b11111111; - endcase - end - always@(rg_f3 or strobe64__h20265 or strobe64__h20267 or strobe64__h20269) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h20332 = strobe64__h20265; - 2'b01: mem_req_wr_data_wstrb__h20332 = strobe64__h20267; - 2'b10: mem_req_wr_data_wstrb__h20332 = strobe64__h20269; - 2'b11: mem_req_wr_data_wstrb__h20332 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h16844) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h16836 = _theResult___snd_fst__h16844; - 2'd3: mem_req_wr_data_wdata__h16836 = rg_st_amo_val; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h25773) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h25765 = _theResult___snd_fst__h25773; - 2'd3: mem_req_wr_data_wdata__h25765 = rg_st_amo_val; - endcase - end - always@(rg_addr or - result__h5517 or - result__h11873 or - result__h11901 or - result__h11929 or - result__h11957 or - result__h11985 or result__h12013 or result__h12041) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h5517; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h11873; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h11901; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h11929; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h11957; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h11985; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h12013; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 = - result__h12041; - endcase - end - always@(rg_addr or - result__h12086 or - result__h12114 or - result__h12142 or - result__h12170 or - result__h12198 or - result__h12226 or result__h12254 or result__h12282) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12086; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12114; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12142; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12170; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12198; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12226; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12254; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 = - result__h12282; - endcase - end - always@(rg_addr or - result__h12327 or - result__h12355 or result__h12383 or result__h12411) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 = - result__h12327; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 = - result__h12355; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 = - result__h12383; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 = - result__h12411; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 = - 64'd0; - endcase - end - always@(rg_addr or - result__h12452 or - result__h12480 or result__h12508 or result__h12536) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 = - result__h12452; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 = - result__h12480; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 = - result__h12508; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 = - result__h12536; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 = - 64'd0; - endcase - end - always@(rg_addr or result__h12644 or result__h12672) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257 = - result__h12644; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257 = - result__h12672; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257 = - 64'd0; - endcase - end - always@(rg_addr or result__h12577 or result__h12605) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29 = - result__h12577; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29 = - result__h12605; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 or - CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257) - begin - case (rg_f3) - 3'b0: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206; - 3'b001: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236; - 3'b010: - new_value__h5462 = - CASE_rg_addr_BITS_2_TO_0_0x0_result2577_0x4_re_ETC__q29; - 3'b011: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259; - 3'b100: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223; - 3'b101: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245; - 3'b110: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257; - 3'd7: new_value__h5462 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 or - w1___1__h17691 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257) - begin - case (rg_f3) - 3'b0: - w1__h17620 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206; - 3'b001: - w1__h17620 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236; - 3'b010: w1__h17620 = w1___1__h17691; - 3'b011: - w1__h17620 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259; - 3'b100: - w1__h17620 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223; - 3'b101: - w1__h17620 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245; - 3'b110: - w1__h17620 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257; - 3'd7: w1__h17620 = 64'd0; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 = - { ram_word64_set$DOB[63:16], rg_st_amo_val[15:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 = - { rg_st_amo_val[15:0], ram_word64_set$DOB[47:0] }; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:8], rg_st_amo_val[7:0] }; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:16], - rg_st_amo_val[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:24], - rg_st_amo_val[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:40], - rg_st_amo_val[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { ram_word64_set$DOB[63:56], - rg_st_amo_val[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 = - { rg_st_amo_val[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236 or - new_value462_BITS_31_TO_0__q30 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d206; - 3'b001: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d236; - 3'b010: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - { {32{new_value462_BITS_31_TO_0__q30[31]}}, - new_value462_BITS_31_TO_0__q30 }; - 3'b011: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d259; - 3'b100: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d223; - 3'b101: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d245; - 3'b110: - IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d257; - 3'd7: IF_rg_f3_40_EQ_0b10_46_THEN_SEXT_IF_rg_f3_40_E_ETC___d304 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h18731 or - new_st_val__h17723 or - w2__h27286 or - new_st_val__h18703 or - new_st_val__h18711 or - new_st_val__h18707 or - new_st_val__h18726 or new_st_val__h18715 or new_st_val__h18720) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h17628 = new_st_val__h17723; - 5'b00001: _theResult_____2__h17628 = w2__h27286; - 5'b00100: _theResult_____2__h17628 = new_st_val__h18703; - 5'b01000: _theResult_____2__h17628 = new_st_val__h18711; - 5'b01100: _theResult_____2__h17628 = new_st_val__h18707; - 5'b10000: _theResult_____2__h17628 = new_st_val__h18726; - 5'b11000: _theResult_____2__h17628 = new_st_val__h18715; - 5'b11100: _theResult_____2__h17628 = new_st_val__h18720; - default: _theResult_____2__h17628 = new_st_val__h18731; - endcase - end - always@(rg_f3 or new_st_val__h17350 or _theResult___snd_fst__h20339) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h20331 = _theResult___snd_fst__h20339; - 2'd3: mem_req_wr_data_wdata__h20331 = new_st_val__h17350; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17350) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 = - { ram_word64_set$DOB[63:16], new_st_val__h17350[15:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 = - { ram_word64_set$DOB[63:32], - new_st_val__h17350[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 = - { ram_word64_set$DOB[63:48], - new_st_val__h17350[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 = - { new_st_val__h17350[15:0], ram_word64_set$DOB[47:0] }; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17350) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:8], new_st_val__h17350[7:0] }; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:16], - new_st_val__h17350[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:24], - new_st_val__h17350[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:32], - new_st_val__h17350[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:40], - new_st_val__h17350[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:48], - new_st_val__h17350[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { ram_word64_set$DOB[63:56], - new_st_val__h17350[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 = - { new_st_val__h17350[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - { ram_word64_set$DOB[63:32], rg_st_amo_val[31:0] }; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - { rg_st_amo_val[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353 or - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 or - rg_st_amo_val) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d344; - 3'b001: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d353; - 3'b010: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 = - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32; - 3'b011: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 = - rg_st_amo_val; - default: IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or - result__h24814 or - result__h24841 or result__h24868 or result__h24895) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d669 = - result__h24814; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d669 = - result__h24841; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d669 = - result__h24868; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d669 = - result__h24895; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d669 = - 64'd0; - endcase - end - always@(rg_addr or - result__h24460 or - result__h24487 or - result__h24514 or - result__h24541 or - result__h24568 or - result__h24595 or result__h24622 or result__h24649) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649 = - result__h24460; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649 = - result__h24487; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649 = - result__h24514; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649 = - result__h24541; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649 = - result__h24568; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649 = - result__h24595; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649 = - result__h24622; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649 = - result__h24649; - endcase - end - always@(rg_addr or - result__h24693 or - result__h24720 or result__h24747 or result__h24774) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d661 = - result__h24693; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d661 = - result__h24720; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d661 = - result__h24747; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d661 = - result__h24774; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d661 = - 64'd0; - endcase - end - always@(rg_addr or - result__h24224 or - result__h24254 or - result__h24281 or - result__h24308 or - result__h24335 or - result__h24362 or result__h24389 or result__h24416) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633 = - result__h24224; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633 = - result__h24254; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633 = - result__h24281; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633 = - result__h24308; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633 = - result__h24335; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633 = - result__h24362; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633 = - result__h24389; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633 = - result__h24416; - endcase - end - always@(rg_addr or result__h24935 or result__h24962) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4935_0x4_re_ETC__q33 = - result__h24935; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4935_0x4_re_ETC__q33 = - result__h24962; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4935_0x4_re_ETC__q33 = - 64'd0; - endcase - end - always@(rg_addr or result__h25000 or result__h25027) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result5000_0x4_re_ETC__q34 = - result__h25000; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result5000_0x4_re_ETC__q34 = - result__h25027; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result5000_0x4_re_ETC__q34 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d661 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4935_0x4_re_ETC__q33 or - rg_addr or - master_xactor_rg_rd_data or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d669 or - CASE_rg_addr_BITS_2_TO_0_0x0_result5000_0x4_re_ETC__q34) - begin - case (rg_f3) - 3'b0: - ld_val__h24164 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d633; - 3'b001: - ld_val__h24164 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d661; - 3'b010: - ld_val__h24164 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4935_0x4_re_ETC__q33; - 3'b011: - ld_val__h24164 = - (rg_addr[2:0] == 3'h0) ? master_xactor_rg_rd_data[66:3] : 64'd0; - 3'b100: - ld_val__h24164 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d649; - 3'b101: - ld_val__h24164 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d669; - 3'b110: - ld_val__h24164 = - CASE_rg_addr_BITS_2_TO_0_0x0_result5000_0x4_re_ETC__q34; - 3'd7: ld_val__h24164 = 64'd0; - endcase - end - always@(rg_addr or result__h29154 or result__h29182) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d802 = - result__h29154; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d802 = - result__h29182; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d802 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28962 or - result__h28990 or result__h29018 or result__h29046) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792 = - result__h28962; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792 = - result__h28990; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792 = - result__h29018; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792 = - result__h29046; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28837 or - result__h28865 or result__h28893 or result__h28921) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784 = - result__h28837; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784 = - result__h28865; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784 = - result__h28893; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784 = - result__h28921; - default: IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28596 or - result__h28624 or - result__h28652 or - result__h28680 or - result__h28708 or - result__h28736 or result__h28764 or result__h28792) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 = - result__h28596; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 = - result__h28624; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 = - result__h28652; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 = - result__h28680; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 = - result__h28708; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 = - result__h28736; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 = - result__h28764; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 = - result__h28792; - endcase - end - always@(rg_addr or - result__h27475 or - result__h28383 or - result__h28411 or - result__h28439 or - result__h28467 or - result__h28495 or result__h28523 or result__h28551) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 = - result__h27475; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 = - result__h28383; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 = - result__h28411; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 = - result__h28439; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 = - result__h28467; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 = - result__h28495; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 = - result__h28523; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 = - result__h28551; - endcase - end - always@(rg_addr or result__h29087 or result__h29115) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result9087_0x4_re_ETC__q49 = - result__h29087; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result9087_0x4_re_ETC__q49 = - result__h29115; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result9087_0x4_re_ETC__q49 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784 or - CASE_rg_addr_BITS_2_TO_0_0x0_result9087_0x4_re_ETC__q49 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d803 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d802) - begin - case (rg_f3) - 3'b0: - w1__h27280 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756; - 3'b001: - w1__h27280 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784; - 3'b010: - w1__h27280 = - CASE_rg_addr_BITS_2_TO_0_0x0_result9087_0x4_re_ETC__q49; - 3'b011: - w1__h27280 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d803; - 3'b100: - w1__h27280 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772; - 3'b101: - w1__h27280 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792; - 3'b110: - w1__h27280 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d802; - 3'd7: w1__h27280 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784 or - w1___1__h27355 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d803 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d802) - begin - case (rg_f3) - 3'b0: - w1__h27284 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756; - 3'b001: - w1__h27284 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784; - 3'b010: w1__h27284 = w1___1__h27355; - 3'b011: - w1__h27284 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d803; - 3'b100: - w1__h27284 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772; - 3'b101: - w1__h27284 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792; - 3'b110: - w1__h27284 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d802; - 3'd7: w1__h27284 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784 or - w17280_BITS_31_TO_0__q50 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d803 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d802) - begin - case (rg_f3) - 3'b0: - new_ld_val__h27000 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d756; - 3'b001: - new_ld_val__h27000 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_SEXT_ETC___d784; - 3'b010: - new_ld_val__h27000 = - { {32{w17280_BITS_31_TO_0__q50[31]}}, - w17280_BITS_31_TO_0__q50 }; - 3'b011: - new_ld_val__h27000 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_IF_r_ETC___d803; - 3'b100: - new_ld_val__h27000 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d772; - 3'b101: - new_ld_val__h27000 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d792; - 3'b110: - new_ld_val__h27000 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_0_CO_ETC___d802; - 3'd7: new_ld_val__h27000 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h29275 or - new_st_val__h27387 or - w2__h27286 or - new_st_val__h29247 or - new_st_val__h29255 or - new_st_val__h29251 or - new_st_val__h29270 or new_st_val__h29259 or new_st_val__h29264) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h27292 = new_st_val__h27387; - 5'b00001: _theResult_____2__h27292 = w2__h27286; - 5'b00100: _theResult_____2__h27292 = new_st_val__h29247; - 5'b01000: _theResult_____2__h27292 = new_st_val__h29255; - 5'b01100: _theResult_____2__h27292 = new_st_val__h29251; - 5'b10000: _theResult_____2__h27292 = new_st_val__h29270; - 5'b11000: _theResult_____2__h27292 = new_st_val__h29259; - 5'b11100: _theResult_____2__h27292 = new_st_val__h29264; - default: _theResult_____2__h27292 = new_st_val__h29275; - endcase - end - always@(rg_f3 or st_val__h27012 or _theResult___snd_fst__h27275) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h27267 = _theResult___snd_fst__h27275; - 2'd3: mem_req_wr_data_wdata__h27267 = st_val__h27012; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17350) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - { ram_word64_set$DOB[63:32], new_st_val__h17350[31:0] }; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - { new_st_val__h17350[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418 or - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427 or - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 or - new_st_val__h17350) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d418; - 3'b001: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_ram__ETC___d427; - 3'b010: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 = - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51; - 3'b011: - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 = - new_st_val__h17350; - default: IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_1_EL_ETC___d273) - begin - case (rg_f3) - 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: - new_value__h15491 = - IF_rg_addr_0_BITS_2_TO_0_8_EQ_0x0_42_THEN_1_EL_ETC___d273; - 3'd7: new_value__h15491 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 7'd0; - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_sb_to_load_delay$EN) - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY - crg_sb_to_load_delay$D_IN; - if (ctr_wr_rsps_pending_crg$EN) - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY - ctr_wr_rsps_pending_crg$D_IN; - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_cset_in_cache$EN) - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN; - if (rg_lower_word32_full$EN) - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY - rg_lower_word32_full$D_IN; - if (rg_lrsc_valid$EN) - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; - if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN; - if (rg_amo_funct7$EN) - rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN; - if (rg_error_during_refill$EN) - rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY - rg_error_during_refill$D_IN; - if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN; - if (rg_lower_word32$EN) - rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN; - if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN; - if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN; - if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN; - if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN; - if (rg_st_amo_val$EN) - rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN; - if (rg_word64_set_in_cache$EN) - rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY - rg_word64_set_in_cache$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_sb_to_load_delay = 11'h2AA; - ctr_wr_rsps_pending_crg = 4'hA; - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; - rg_addr = 32'hAAAAAAAA; - rg_amo_funct7 = 7'h2A; - rg_cset_in_cache = 7'h2A; - rg_error_during_refill = 1'h0; - rg_exc_code = 4'hA; - rg_f3 = 3'h2; - rg_ld_val = 64'hAAAAAAAAAAAAAAAA; - rg_lower_word32 = 32'hAAAAAAAA; - rg_lower_word32_full = 1'h0; - rg_lrsc_pa = 32'hAAAAAAAA; - rg_lrsc_valid = 1'h0; - rg_op = 2'h2; - rg_pa = 32'hAAAAAAAA; - rg_pte_pa = 32'hAAAAAAAA; - rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - rg_word64_set_in_cache = 9'h0AA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - begin - v__h3732 = $stime; - #0; - end - v__h3726 = v__h3732 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h3726, - "D_MMU_Cache", - $signed(32'd128), - $signed(32'd1)); - else - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h3726, - "I_MMU_Cache", - $signed(32'd128), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - f_reset_reqs$D_OUT) - begin - v__h3833 = $stime; - #0; - end - v__h3827 = v__h3833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 7'd127 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: Flushed", v__h3827, "D_MMU_Cache"); - else - $display("%0d: %s.rl_reset: Flushed", v__h3827, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_rereq && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - rg_addr[11:5], - rg_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25367 = $stime; - #0; - end - v__h25361 = v__h25367 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25361, - "D_MMU_Cache", - rg_addr, - rg_ld_val); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25361, - "I_MMU_Cache", - rg_addr, - rg_ld_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26263 = $stime; - #0; - end - v__h26257 = v__h26263 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26257, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26257, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" FAIL due to I/O address."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h3369 = $stime; - #0; - end - v__h3363 = v__h3369 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_start_reset", v__h3363, "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_reset", v__h3363, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h4284 = $stime; - #0; - end - v__h4278 = v__h4284 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h4278, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h4278, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", - pa_ctag__h5138, - rg_addr[11:5], - rg_addr[4:3], - rg_addr[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" CSet 0x%0x: (state, tag):", rg_addr[11:5]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" ("); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - ram_state_and_ctag_cset$DOB[22]) - $write("CTAG_CLEAN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !ram_state_and_ctag_cset$DOB[22]) - $write("CTAG_EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - ram_state_and_ctag_cset$DOB[22]) - $write(", 0x%0x", ram_state_and_ctag_cset$DOB[21:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !ram_state_and_ctag_cset$DOB[22]) - $write(", --"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(")"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" TLB result: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'hA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && dmem_not_imem && - !soc_map$m_is_mem_addr && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => IO_REQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d277) - begin - v__h12756 = $stime; - #0; - end - v__h12750 = v__h12756 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d277) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h12750, - "D_MMU_Cache", - rg_addr, - word64__h5280, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h12750, - "I_MMU_Cache", - rg_addr, - word64__h5280, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[22] && - ram_state_and_ctag_cset_b_read__0_BITS_21_TO_0_ETC___d76 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO LR: reserving PA 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d277) - $display(" Read-hit: addr 0x%0h word64 0x%0h", - rg_addr, - word64__h5280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_0_6_OR_rg_op_5_EQ_2_7_AND_rg_amo_fu_ETC___d290) - $display(" Read Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7_8_BITS_6_TO_2_9_EQ_0b10_0_AND_NO_ETC___d294) - $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", - rg_lrsc_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d480) - $display(" ST: cancelling LR/SC reservation for PA", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - rg_lrsc_valid && - !rg_lrsc_pa_9_EQ_rg_addr_0___d60 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", - rg_lrsc_pa, - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !rg_lrsc_valid && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO SC: fail due to invalid LR/SC reservation"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d492) - $display(" AMO SC result = %0d", lrsc_result__h13133); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d495) - $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d495) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d495) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d495) - $write(" 0x%0x", - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d362); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d495) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_5_EQ_2_7_5_OR_NOT_rg_amo_funct7_8_BI_ETC___d497) - $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d508) - begin - v__h17070 = $stime; - #0; - end - v__h17064 = v__h17070 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d508) - $display("%0d: ERROR: CreditCounter: overflow", v__h17064); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d508) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", mem_req_wr_addr_awaddr__h20126); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", value__h29610); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", mem_req_wr_data_wdata__h16836); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", mem_req_wr_data_wstrb__h20332); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_5_EQ_0_6_4_AND_NOT_rg_op_5_EQ_2_7_5__ETC___d503) - $display(" => rl_write_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d514) - begin - v__h16400 = $stime; - #0; - end - v__h16394 = v__h16400 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d514) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h16394, - "D_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h16394, - "I_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_5_EQ_2_7_AND_rg_amo_funct7_8_BITS_6_TO_2_ETC___d514) - $display(" AMO SC: Fail response for addr 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d520) - $display(" AMO Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", - rg_addr, - rg_amo_funct7, - rg_f3, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $display(" PA 0x%0h ", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $display(" Cache word64 0x%0h, load-result 0x%0h", - word64__h5280, - word64__h5280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $display(" 0x%0h op 0x%0h -> 0x%0h", - word64__h5280, - word64__h5280, - new_st_val__h17350); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_addr[4:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(" 0x%0x", - IF_rg_f3_40_EQ_0b0_41_THEN_IF_rg_addr_0_BITS_2_ETC___d436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d527) - begin - v__h20534 = $stime; - #0; - end - v__h20528 = v__h20534 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d527) - $display("%0d: ERROR: CreditCounter: overflow", v__h20528); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d527) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", mem_req_wr_addr_awaddr__h20126); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", value__h29610); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", mem_req_wr_data_wdata__h20331); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", mem_req_wr_data_wstrb__h20332); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d523) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_15_OR_soc_map_m_is_mem_addr__ETC___d533) - $display(" AMO_op: cancelling LR/SC reservation for PA", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - begin - v__h21828 = $stime; - #0; - end - v__h21822 = v__h21828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h21822, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h21822, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h22069 = $stime; - #0; - end - v__h22063 = v__h22069 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h22063, - "D_MMU_Cache", - access_exc_code__h2925); - else - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h22063, - "I_MMU_Cache", - access_exc_code__h2925); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 && - (master_xactor_rg_rd_data[2:1] != 2'b0 || rg_error_during_refill) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => MODULE_EXCEPTION_RSP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[1:0] == 2'd3 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !rg_error_during_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => CACHE_REREQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", - rg_word64_set_in_cache, - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:5], - rg_word64_set_in_cache[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write(" 0x%0x", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_56___d557) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h24055 = $stime; - #0; - end - v__h24049 = v__h24055 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h24049, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h24049, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25155 = $stime; - #0; - end - v__h25149 = v__h25155 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25149, - "D_MMU_Cache", - rg_addr, - ld_val__h24164); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25149, - "I_MMU_Cache", - rg_addr, - ld_val__h24164); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25262 = $stime; - #0; - end - v__h25256 = v__h25262 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h25256, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h25256, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25447 = $stime; - #0; - end - v__h25441 = v__h25447 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h25441, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h25441, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h25968 = $stime; - #0; - end - v__h25962 = v__h25968 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h25962); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_addr_awaddr__h27062); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h29610); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wdata__h25765); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wstrb__h27268); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26381 = $stime; - #0; - end - v__h26375 = v__h26381 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h26375, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h26375, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_addr_awaddr__h27062); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h26585); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26699 = $stime; - #0; - end - v__h26693 = v__h26699 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h26693, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h26693, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26874 = $stime; - #0; - end - v__h26868 = v__h26874 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26868, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26868, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h29486 = $stime; - #0; - end - v__h29480 = v__h29486 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h29480); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_addr_awaddr__h27062); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h29610); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wdata__h27267); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wstrb__h27268); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h29737 = $stime; - #0; - end - v__h29731 = v__h29737 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29731, - "D_MMU_Cache", - rg_addr, - new_ld_val__h27000); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29731, - "I_MMU_Cache", - rg_addr, - new_ld_val__h27000); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26970 = $stime; - #0; - end - v__h26964 = v__h26970 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h26964, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h26964, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h20978 = $stime; - #0; - end - v__h20972 = v__h20978 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_start_cache_refill: ", - v__h20972, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_cache_refill: ", - v__h20972, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", cline_fabric_addr__h21031); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" Victim way %0d; => CACHE_REFILL", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h23681 = $stime; - #0; - end - v__h23675 = v__h23681 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h23675, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h23675, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_addr_awaddr__h27062); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h26585); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h30705 = $stime; - #0; - end - v__h30699 = v__h30705 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $write("%0d: %s.req: op:", v__h30699, "D_MMU_Cache"); - else - $write("%0d: %s.req: op:", v__h30699, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && req_op == 2'd0) - $write("CACHE_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && req_op == 2'd1) - $write("CACHE_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_op != 2'd0 && - req_op != 2'd1) - $write("CACHE_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", - req_f3, - req_addr, - req_st_value); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b0) - $write("U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b01) - $write("S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b11) - $write("M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv != 2'b0 && - req_priv != 2'b01 && - req_priv != 2'b11) - $write("RESERVED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" amo_funct7 = 0x%0h", req_amo_funct7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && - req_f3_BITS_1_TO_0_93_EQ_0b0_94_OR_req_f3_BITS_ETC___d923 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - req_addr[11:5], - req_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h30357 = $stime; - #0; - end - v__h30351 = v__h30357 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h30351, - "D_MMU_Cache", - $unsigned(b__h20932)); - else - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h30351, - "I_MMU_Cache", - $unsigned(b__h20932)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - begin - v__h30318 = $stime; - #0; - end - v__h30312 = v__h30318 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - if (dmem_not_imem) - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h30312, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h30312, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("\n"); - end - // synopsys translate_on -endmodule // mkMMU_Cache - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v deleted file mode 100644 index 21869c75..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v +++ /dev/null @@ -1,2158 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// to_raw_mem_response_put I 256 -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_to_raw_mem_response_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Controller(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [63 : 0] slave_rdata; - wire [7 : 0] status; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // inlined wires - reg [353 : 0] f_raw_mem_reqs_rv$port1__write_1; - wire [353 : 0] f_raw_mem_reqs_rv$port1__read, - f_raw_mem_reqs_rv$port2__read, - f_raw_mem_reqs_rv$port3__read; - wire [256 : 0] f_raw_mem_rsps_rv$port1__read, - f_raw_mem_rsps_rv$port1__write_1, - f_raw_mem_rsps_rv$port2__read, - f_raw_mem_rsps_rv$port3__read; - wire [170 : 0] f_reqs_rv$port1__read, - f_reqs_rv$port1__write_1, - f_reqs_rv$port2__read; - wire f_raw_mem_reqs_rv$EN_port1__write, - f_reqs_rv$EN_port0__write, - f_reqs_rv$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register f_raw_mem_reqs_rv - reg [353 : 0] f_raw_mem_reqs_rv; - wire [353 : 0] f_raw_mem_reqs_rv$D_IN; - wire f_raw_mem_reqs_rv$EN; - - // register f_raw_mem_rsps_rv - reg [256 : 0] f_raw_mem_rsps_rv; - wire [256 : 0] f_raw_mem_rsps_rv$D_IN; - wire f_raw_mem_rsps_rv$EN; - - // register f_reqs_rv - reg [170 : 0] f_reqs_rv; - wire [170 : 0] f_reqs_rv$D_IN; - wire f_reqs_rv$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_cached_clean - reg rg_cached_clean; - wire rg_cached_clean$D_IN, rg_cached_clean$EN; - - // register rg_cached_raw_mem_addr - reg [63 : 0] rg_cached_raw_mem_addr; - wire [63 : 0] rg_cached_raw_mem_addr$D_IN; - wire rg_cached_raw_mem_addr$EN; - - // register rg_cached_raw_mem_word - reg [255 : 0] rg_cached_raw_mem_word; - wire [255 : 0] rg_cached_raw_mem_word$D_IN; - wire rg_cached_raw_mem_word$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_status - reg [7 : 0] rg_status; - wire [7 : 0] rg_status$D_IN; - wire rg_status$EN; - - // register rg_tohost_addr - reg [63 : 0] rg_tohost_addr; - wire [63 : 0] rg_tohost_addr$D_IN; - wire rg_tohost_addr$EN; - - // register rg_watch_tohost - reg rg_watch_tohost; - wire rg_watch_tohost$D_IN, rg_watch_tohost$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_external_reset, - CAN_FIRE_RL_rl_invalid_rd_address, - CAN_FIRE_RL_rl_invalid_wr_address, - CAN_FIRE_RL_rl_merge_rd_req, - CAN_FIRE_RL_rl_merge_wr_req, - CAN_FIRE_RL_rl_miss_clean_req, - CAN_FIRE_RL_rl_power_on_reset, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reload, - CAN_FIRE_RL_rl_reset_reload_cache, - CAN_FIRE_RL_rl_writeback_dirty, - CAN_FIRE_RL_rl_writeback_dirty_idle, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_external_reset, - WILL_FIRE_RL_rl_invalid_rd_address, - WILL_FIRE_RL_rl_invalid_wr_address, - WILL_FIRE_RL_rl_merge_rd_req, - WILL_FIRE_RL_rl_merge_wr_req, - WILL_FIRE_RL_rl_miss_clean_req, - WILL_FIRE_RL_rl_power_on_reset, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reload, - WILL_FIRE_RL_rl_reset_reload_cache, - WILL_FIRE_RL_rl_writeback_dirty, - WILL_FIRE_RL_rl_writeback_dirty_idle, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire [353 : 0] MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1, - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - wire [255 : 0] MUX_rg_cached_raw_mem_word$write_1__VAL_1; - wire [170 : 0] MUX_f_reqs_rv$port1__write_1__VAL_1, - MUX_f_reqs_rv$port1__write_1__VAL_2; - wire [70 : 0] MUX_slave_xactor_f_rd_data$enq_1__VAL_1, - MUX_slave_xactor_f_rd_data$enq_1__VAL_2; - wire [5 : 0] MUX_slave_xactor_f_wr_resp$enq_1__VAL_1, - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2; - wire MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2538; - reg [31 : 0] v__h3474; - reg [31 : 0] v__h3967; - reg [31 : 0] v__h4436; - reg [31 : 0] v__h4699; - reg [31 : 0] v__h5418; - reg [31 : 0] v__h7615; - reg [31 : 0] v__h7816; - reg [31 : 0] v__h8328; - reg [31 : 0] v__h9112; - reg [31 : 0] v__h9707; - reg [31 : 0] v__h2853; - reg [31 : 0] v__h3188; - reg [31 : 0] v__h1743; - reg [31 : 0] v__h2088; - reg [31 : 0] v__h1737; - reg [31 : 0] v__h2082; - reg [31 : 0] v__h2532; - reg [31 : 0] v__h2847; - reg [31 : 0] v__h3182; - reg [31 : 0] v__h3468; - reg [31 : 0] v__h3961; - reg [31 : 0] v__h4430; - reg [31 : 0] v__h4693; - reg [31 : 0] v__h5412; - reg [31 : 0] v__h7609; - reg [31 : 0] v__h7810; - reg [31 : 0] v__h8322; - reg [31 : 0] v__h9106; - reg [31 : 0] v__h9701; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rdata__h5061, word64_old__h5855; - wire [63 : 0] exit_value__h7853, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1, - mask__h5860, - req_raw_mem_addr__h3307, - updated_word64__h5861, - x__h6234, - y__h6235, - y__h6236; - wire [7 : 0] SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214, - SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211, - SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207, - SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204, - SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200, - SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197, - SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193, - SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190; - wire [4 : 0] n__h5060; - wire NOT_cfg_verbosity_read_ULE_1___d5, - NOT_cfg_verbosity_read_ULE_2_2___d33, - NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278, - f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127, - f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122, - rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125, - rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134, - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283, - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130, - rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = rg_state == 2'd3 ; - assign CAN_FIRE_set_addr_map = rg_state == 2'd3 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = f_raw_mem_reqs_rv[352:0] ; - assign RDY_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign CAN_FIRE_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = !f_raw_mem_rsps_rv$port1__read[256] ; - assign CAN_FIRE_to_raw_mem_response_put = - !f_raw_mem_rsps_rv$port1__read[256] ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // value method status - assign status = rg_status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset_reload_cache - assign CAN_FIRE_RL_rl_reset_reload_cache = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_reload_cache = - CAN_FIRE_RL_rl_reset_reload_cache ; - - // rule RL_rl_writeback_dirty_idle - assign CAN_FIRE_RL_rl_writeback_dirty_idle = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd3 && - !f_reqs_rv[170] && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty_idle = - CAN_FIRE_RL_rl_writeback_dirty_idle ; - - // rule RL_rl_writeback_dirty - assign CAN_FIRE_RL_rl_writeback_dirty = - !f_raw_mem_reqs_rv$port1__read[353] && f_reqs_rv[170] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 && - !rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty = CAN_FIRE_RL_rl_writeback_dirty ; - - // rule RL_rl_miss_clean_req - assign CAN_FIRE_RL_rl_miss_clean_req = - f_reqs_rv[170] && !f_raw_mem_reqs_rv$port1__read[353] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 && - !rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 && - rg_cached_clean ; - assign WILL_FIRE_RL_rl_miss_clean_req = - CAN_FIRE_RL_rl_miss_clean_req && - !WILL_FIRE_RL_rl_external_reset && - !EN_set_addr_map ; - - // rule RL_rl_reload - assign CAN_FIRE_RL_rl_reload = f_raw_mem_rsps_rv[256] && rg_state == 2'd2 ; - assign WILL_FIRE_RL_rl_reload = CAN_FIRE_RL_rl_reload ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 && - rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 && - rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_invalid_rd_address - assign CAN_FIRE_RL_rl_invalid_rd_address = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_rd_address = - CAN_FIRE_RL_rl_invalid_rd_address ; - - // rule RL_rl_invalid_wr_address - assign CAN_FIRE_RL_rl_invalid_wr_address = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_wr_address = - CAN_FIRE_RL_rl_invalid_wr_address ; - - // rule RL_rl_merge_rd_req - assign CAN_FIRE_RL_rl_merge_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && !f_reqs_rv$port1__read[170] ; - assign WILL_FIRE_RL_rl_merge_rd_req = CAN_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_merge_wr_req - assign CAN_FIRE_RL_rl_merge_wr_req = - !f_reqs_rv$port1__read[170] && slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N ; - assign WILL_FIRE_RL_rl_merge_wr_req = - CAN_FIRE_RL_rl_merge_wr_req && !WILL_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_power_on_reset - assign CAN_FIRE_RL_rl_power_on_reset = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_power_on_reset = CAN_FIRE_RL_rl_power_on_reset ; - - // rule RL_rl_external_reset - assign CAN_FIRE_RL_rl_external_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && rg_state == 2'd3 ; - assign WILL_FIRE_RL_rl_external_reset = CAN_FIRE_RL_rl_external_reset ; - - // inputs to muxes for submodule ports - assign MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - assign MUX_rg_state$write_1__SEL_1 = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - assign MUX_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 = - { 34'h3FFFFFFFF, - rg_cached_raw_mem_addr, - rg_cached_raw_mem_word } ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3 = - { 34'h2FFFFFFFF, - req_raw_mem_addr__h3307, - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_1 = - { 2'd2, slave_xactor_f_rd_addr$D_OUT, 72'hAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_2 = - { 2'd3, - slave_xactor_f_wr_addr$D_OUT, - slave_xactor_f_wr_data$D_OUT[8:1], - slave_xactor_f_wr_data$D_OUT[72:9] } ; - assign MUX_rg_cached_raw_mem_word$write_1__VAL_1 = - { (f_reqs_rv[105:104] == 2'd3) ? - updated_word64__h5861 : - rg_cached_raw_mem_word[255:192], - (f_reqs_rv[105:104] == 2'd2) ? - updated_word64__h5861 : - rg_cached_raw_mem_word[191:128], - (f_reqs_rv[105:104] == 2'd1) ? - updated_word64__h5861 : - rg_cached_raw_mem_word[127:64], - (f_reqs_rv[105:104] == 2'd0) ? - updated_word64__h5861 : - rg_cached_raw_mem_word[63:0] } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_1 = - { f_reqs_rv[168:165], rdata__h5061, 3'd1 } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_2 = - { f_reqs_rv[168:101], 3'd5 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 = - { f_reqs_rv[168:165], 2'd0 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 = - { f_reqs_rv[168:165], 2'd2 } ; - - // inlined wires - assign f_reqs_rv$EN_port0__write = - WILL_FIRE_RL_rl_invalid_wr_address || - WILL_FIRE_RL_rl_invalid_rd_address || - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs_rv$port1__read = - f_reqs_rv$EN_port0__write ? - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_reqs_rv ; - assign f_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_merge_rd_req || WILL_FIRE_RL_rl_merge_wr_req ; - assign f_reqs_rv$port1__write_1 = - WILL_FIRE_RL_rl_merge_rd_req ? - MUX_f_reqs_rv$port1__write_1__VAL_1 : - MUX_f_reqs_rv$port1__write_1__VAL_2 ; - assign f_reqs_rv$port2__read = - f_reqs_rv$EN_port1__write ? - f_reqs_rv$port1__write_1 : - f_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port1__read = - EN_to_raw_mem_request_get ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv ; - assign f_raw_mem_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_miss_clean_req ; - always@(MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 or - WILL_FIRE_RL_rl_reset_reload_cache or - WILL_FIRE_RL_rl_miss_clean_req or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1; - WILL_FIRE_RL_rl_reset_reload_cache: - f_raw_mem_reqs_rv$port1__write_1 = - 354'h2FFFFFFFF0000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_miss_clean_req: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - default: f_raw_mem_reqs_rv$port1__write_1 = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign f_raw_mem_reqs_rv$port2__read = - f_raw_mem_reqs_rv$EN_port1__write ? - f_raw_mem_reqs_rv$port1__write_1 : - f_raw_mem_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv$port2__read ; - assign f_raw_mem_rsps_rv$port1__read = - CAN_FIRE_RL_rl_reload ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv ; - assign f_raw_mem_rsps_rv$port1__write_1 = - { 1'd1, to_raw_mem_response_put } ; - assign f_raw_mem_rsps_rv$port2__read = - EN_to_raw_mem_response_put ? - f_raw_mem_rsps_rv$port1__write_1 : - f_raw_mem_rsps_rv$port1__read ; - assign f_raw_mem_rsps_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv$port2__read ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register f_raw_mem_reqs_rv - assign f_raw_mem_reqs_rv$D_IN = f_raw_mem_reqs_rv$port3__read ; - assign f_raw_mem_reqs_rv$EN = 1'b1 ; - - // register f_raw_mem_rsps_rv - assign f_raw_mem_rsps_rv$D_IN = f_raw_mem_rsps_rv$port3__read ; - assign f_raw_mem_rsps_rv$EN = 1'b1 ; - - // register f_reqs_rv - assign f_reqs_rv$D_IN = f_reqs_rv$port2__read ; - assign f_reqs_rv$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_cached_clean - assign rg_cached_clean$D_IN = !WILL_FIRE_RL_rl_process_wr_req ; - assign rg_cached_clean$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload || - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - - // register rg_cached_raw_mem_addr - assign rg_cached_raw_mem_addr$D_IN = - WILL_FIRE_RL_rl_miss_clean_req ? - req_raw_mem_addr__h3307 : - 64'd0 ; - assign rg_cached_raw_mem_addr$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_cached_raw_mem_word - assign rg_cached_raw_mem_word$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_rg_cached_raw_mem_word$write_1__VAL_1 : - f_raw_mem_rsps_rv[255:0] ; - assign rg_cached_raw_mem_word$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload ; - - // register rg_state - always@(MUX_rg_state$write_1__SEL_1 or - MUX_rg_state$write_1__SEL_2 or WILL_FIRE_RL_rl_reload) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_state$write_1__SEL_1: rg_state$D_IN = 2'd1; - MUX_rg_state$write_1__SEL_2: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reload: rg_state$D_IN = 2'd3; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset || - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_reload ; - - // register rg_status - assign rg_status$D_IN = - (WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset) ? - 8'd0 : - 8'd1 ; - assign rg_status$EN = - WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 || - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - - // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_watch_tohost ; - - // register rg_watch_tohost - assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ; - assign rg_watch_tohost$EN = EN_set_watch_tohost ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_merge_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_slave_xactor_f_rd_data$enq_1__VAL_1 : - MUX_slave_xactor_f_rd_data$enq_1__VAL_2 ; - assign slave_xactor_f_rd_data$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_invalid_rd_address ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 : - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 ; - assign slave_xactor_f_wr_resp$ENQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_invalid_wr_address ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_1 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d5 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read_ULE_2_2___d33 = cfg_verbosity > 4'd2 ; - assign NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278 = - f_reqs_rv[92:90] != 3'b0 && - (f_reqs_rv[92:90] != 3'b001 || f_reqs_rv[101]) && - (f_reqs_rv[92:90] != 3'b010 || f_reqs_rv[102:101] != 2'h0) && - (f_reqs_rv[92:90] != 3'b011 || f_reqs_rv[103:101] != 3'h0) && - (f_reqs_rv[92:90] != 3'b100 || f_reqs_rv[104:101] != 4'h0) && - (f_reqs_rv[92:90] != 3'b101 || f_reqs_rv[105:101] != 5'h0) && - (f_reqs_rv[92:90] != 3'b110 || f_reqs_rv[106:101] != 6'h0) && - (f_reqs_rv[92:90] != 3'b111 || f_reqs_rv[107:101] != 7'h0) ; - assign SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214 = {8{f_reqs_rv[64]}} ; - assign SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211 = {8{f_reqs_rv[65]}} ; - assign SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207 = {8{f_reqs_rv[66]}} ; - assign SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204 = {8{f_reqs_rv[67]}} ; - assign SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200 = {8{f_reqs_rv[68]}} ; - assign SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197 = {8{f_reqs_rv[69]}} ; - assign SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193 = {8{f_reqs_rv[70]}} ; - assign SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190 = {8{f_reqs_rv[71]}} ; - assign exit_value__h7853 = { 1'd0, f_reqs_rv[63:1] } ; - assign f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1 = - f_reqs_rv[164:101] - rg_addr_base ; - assign f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127 = - f_reqs_rv[164:101] < rg_addr_lim ; - assign f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122 = - f_reqs_rv[92:90] == 3'b0 || - f_reqs_rv[92:90] == 3'b001 && !f_reqs_rv[101] || - f_reqs_rv[92:90] == 3'b010 && f_reqs_rv[102:101] == 2'h0 || - f_reqs_rv[92:90] == 3'b011 && f_reqs_rv[103:101] == 3'h0 || - f_reqs_rv[92:90] == 3'b100 && f_reqs_rv[104:101] == 4'h0 || - f_reqs_rv[92:90] == 3'b101 && f_reqs_rv[105:101] == 5'h0 || - f_reqs_rv[92:90] == 3'b110 && f_reqs_rv[106:101] == 6'h0 || - f_reqs_rv[92:90] == 3'b111 && f_reqs_rv[107:101] == 7'h0 ; - assign mask__h5860 = - { SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190, - SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193, - SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197, - SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200, - SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204, - SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207, - SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211, - SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214 } ; - assign n__h5060 = { 3'd0, f_reqs_rv[105:104] } ; - assign req_raw_mem_addr__h3307 = - { 5'd0, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1[63:5] } ; - assign rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125 = - rg_addr_base <= f_reqs_rv[164:101] ; - assign rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 = - rg_cached_raw_mem_addr == req_raw_mem_addr__h3307 ; - assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283 = - rg_state == 2'd3 && - (NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278 || - !rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125 || - !f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127) ; - assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 = - rg_state == 2'd3 && - f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122 && - rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125 && - f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127 ; - assign rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 = - rg_watch_tohost && f_reqs_rv[164:101] == rg_tohost_addr && - f_reqs_rv[63:0] != 64'd0 ; - assign updated_word64__h5861 = x__h6234 | y__h6235 ; - assign x__h6234 = word64_old__h5855 & y__h6236 ; - assign y__h6235 = f_reqs_rv[63:0] & mask__h5860 ; - assign y__h6236 = - { ~SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190, - ~SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193, - ~SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197, - ~SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200, - ~SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204, - ~SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207, - ~SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211, - ~SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214 } ; - always@(f_reqs_rv or rg_cached_raw_mem_word) - begin - case (f_reqs_rv[105:104]) - 2'd0: word64_old__h5855 = rg_cached_raw_mem_word[63:0]; - 2'd1: word64_old__h5855 = rg_cached_raw_mem_word[127:64]; - 2'd2: word64_old__h5855 = rg_cached_raw_mem_word[191:128]; - 2'd3: word64_old__h5855 = rg_cached_raw_mem_word[255:192]; - endcase - end - always@(n__h5060 or rg_cached_raw_mem_word) - begin - case (n__h5060) - 5'd0: rdata__h5061 = rg_cached_raw_mem_word[63:0]; - 5'd1: rdata__h5061 = rg_cached_raw_mem_word[127:64]; - 5'd2: rdata__h5061 = rg_cached_raw_mem_word[191:128]; - 5'd3: rdata__h5061 = rg_cached_raw_mem_word[255:192]; - default: rdata__h5061 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - rg_status <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000; - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (f_raw_mem_reqs_rv$EN) - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_reqs_rv$D_IN; - if (f_raw_mem_rsps_rv$EN) - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_rsps_rv$D_IN; - if (f_reqs_rv$EN) f_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_reqs_rv$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_status$EN) rg_status <= `BSV_ASSIGNMENT_DELAY rg_status$D_IN; - if (rg_tohost_addr$EN) - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; - if (rg_watch_tohost$EN) - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_cached_clean$EN) - rg_cached_clean <= `BSV_ASSIGNMENT_DELAY rg_cached_clean$D_IN; - if (rg_cached_raw_mem_addr$EN) - rg_cached_raw_mem_addr <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_addr$D_IN; - if (rg_cached_raw_mem_word$EN) - rg_cached_raw_mem_word <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_word$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - f_raw_mem_reqs_rv = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv = 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_cached_clean = 1'h0; - rg_cached_raw_mem_addr = 64'hAAAAAAAAAAAAAAAA; - rg_cached_raw_mem_word = - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state = 2'h2; - rg_status = 8'hAA; - rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; - rg_watch_tohost = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2538 = $stime; - #0; - end - v__h2532 = v__h2538 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING", - v__h2532); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3474 = $stime; - #0; - end - v__h3468 = v__h3474 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h", - v__h3468, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3967 = $stime; - #0; - end - v__h3961 = v__h3967 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h", - v__h3961, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4436 = $stime; - #0; - end - v__h4430 = v__h4436 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h", - v__h4430, - req_raw_mem_addr__h3307); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4699 = $stime; - #0; - end - v__h4693 = v__h4699 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_reload: raw addr 0x%0h", - v__h4693, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", f_raw_mem_rsps_rv[255:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h5418 = $stime; - #0; - end - v__h5412 = v__h5418 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5412); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", rdata__h5061); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h7615 = $stime; - #0; - end - v__h7609 = v__h7615 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7609); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242) - begin - v__h7816 = $stime; - #0; - end - v__h7810 = v__h7816 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242) - $display("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h () data 0x%0h", - v__h7810, - f_reqs_rv[164:101], - f_reqs_rv[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 && - f_reqs_rv[63:1] == 63'd0) - $display("PASS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 && - f_reqs_rv[63:1] != 63'd0) - $display("FAIL %0d", exit_value__h7853); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - begin - v__h8328 = $stime; - #0; - end - v__h8322 = v__h8328 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("%0d: ERROR: Mem_Controller:", v__h8322); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278) - $display(" read-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122) - $display(" read-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - begin - v__h9112 = $stime; - #0; - end - v__h9106 = v__h9112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("%0d: ERROR: Mem_Controller:", v__h9106); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278) - $display(" write-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122) - $display(" write-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - begin - v__h9707 = $stime; - #0; - end - v__h9701 = v__h9707 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - $display("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9701, - set_addr_map_addr_base, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h2853 = $stime; - #0; - end - v__h2847 = v__h2853 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_rd_req", v__h2847); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3188 = $stime; - #0; - end - v__h3182 = v__h3188 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_wr_req", v__h3182); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h1743 = $stime; - #0; - end - v__h1737 = v__h1743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_power_on_reset", v__h1737); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2088 = $stime; - #0; - end - v__h2082 = v__h2088 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE", - v__h2082); - end - // synopsys translate_on -endmodule // mkMem_Controller - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v deleted file mode 100644 index 104c51b0..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v +++ /dev/null @@ -1,192 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_mem_server_request_put O 1 reg -// mem_server_response_get O 256 reg -// RDY_mem_server_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// mem_server_request_put I 353 -// EN_mem_server_request_put I 1 -// EN_mem_server_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Model(CLK, - RST_N, - - mem_server_request_put, - EN_mem_server_request_put, - RDY_mem_server_request_put, - - EN_mem_server_response_get, - mem_server_response_get, - RDY_mem_server_response_get); - input CLK; - input RST_N; - - // action method mem_server_request_put - input [352 : 0] mem_server_request_put; - input EN_mem_server_request_put; - output RDY_mem_server_request_put; - - // actionvalue method mem_server_response_get - input EN_mem_server_response_get; - output [255 : 0] mem_server_response_get; - output RDY_mem_server_response_get; - - // signals for module outputs - wire [255 : 0] mem_server_response_get; - wire RDY_mem_server_request_put, RDY_mem_server_response_get; - - // ports of submodule f_raw_mem_rsps - wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT; - wire f_raw_mem_rsps$CLR, - f_raw_mem_rsps$DEQ, - f_raw_mem_rsps$EMPTY_N, - f_raw_mem_rsps$ENQ, - f_raw_mem_rsps$FULL_N; - - // ports of submodule rf - wire [255 : 0] rf$D_IN, rf$D_OUT_1; - wire [63 : 0] rf$ADDR_1, - rf$ADDR_2, - rf$ADDR_3, - rf$ADDR_4, - rf$ADDR_5, - rf$ADDR_IN; - wire rf$WE; - - // rule scheduling signals - wire CAN_FIRE_mem_server_request_put, - CAN_FIRE_mem_server_response_get, - WILL_FIRE_mem_server_request_put, - WILL_FIRE_mem_server_response_get; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h371; - reg [31 : 0] v__h365; - // synopsys translate_on - - // remaining internal signals - wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2; - - // action method mem_server_request_put - assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ; - - // actionvalue method mem_server_response_get - assign mem_server_response_get = f_raw_mem_rsps$D_OUT ; - assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ; - - // submodule f_raw_mem_rsps - FIFO2 #(.width(32'd256), .guarded(32'd1)) f_raw_mem_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_raw_mem_rsps$D_IN), - .ENQ(f_raw_mem_rsps$ENQ), - .DEQ(f_raw_mem_rsps$DEQ), - .CLR(f_raw_mem_rsps$CLR), - .D_OUT(f_raw_mem_rsps$D_OUT), - .FULL_N(f_raw_mem_rsps$FULL_N), - .EMPTY_N(f_raw_mem_rsps$EMPTY_N)); - - // submodule rf - RegFileLoad #(.file("Mem.hex"), - .addr_width(32'd64), - .data_width(32'd256), - .lo(64'd0), - .hi(64'd8388607), - .binary(1'd0)) rf(.CLK(CLK), - .ADDR_1(rf$ADDR_1), - .ADDR_2(rf$ADDR_2), - .ADDR_3(rf$ADDR_3), - .ADDR_4(rf$ADDR_4), - .ADDR_5(rf$ADDR_5), - .ADDR_IN(rf$ADDR_IN), - .D_IN(rf$D_IN), - .WE(rf$WE), - .D_OUT_1(rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule f_raw_mem_rsps - assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ; - assign f_raw_mem_rsps$ENQ = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - !mem_server_request_put[352] ; - assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ; - assign f_raw_mem_rsps$CLR = 1'b0 ; - - // submodule rf - assign rf$ADDR_1 = mem_server_request_put[319:256] ; - assign rf$ADDR_2 = 64'h0 ; - assign rf$ADDR_3 = 64'h0 ; - assign rf$ADDR_4 = 64'h0 ; - assign rf$ADDR_5 = 64'h0 ; - assign rf$ADDR_IN = mem_server_request_put[319:256] ; - assign rf$D_IN = mem_server_request_put[255:0] ; - assign rf$WE = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - mem_server_request_put[352] ; - - // remaining internal signals - assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 = - mem_server_request_put[319:256] < 64'h0000000000800000 ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - begin - v__h371 = $stime; - #0; - end - v__h365 = v__h371 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)", - v__h365, - mem_server_request_put[319:256], - 64'h0000000000800000); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkMem_Model - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v deleted file mode 100644 index c04787bb..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v +++ /dev/null @@ -1,1625 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 -// RDY_server_reset_response_get O 1 reg -// imem_valid O 1 -// imem_is_i32_not_i16 O 1 const -// imem_pc O 32 reg -// imem_instr O 32 -// imem_exc O 1 -// imem_exc_code O 4 reg -// imem_tval O 32 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_valid O 1 -// dmem_word64 O 64 -// dmem_st_amo_val O 64 -// dmem_exc O 1 -// dmem_exc_code O 4 reg -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_server_fence_i_request_put O 1 -// RDY_server_fence_i_response_get O 1 -// RDY_server_fence_request_put O 1 reg -// RDY_server_fence_response_get O 1 -// RDY_sfence_vma O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// imem_req_f3 I 3 -// imem_req_addr I 32 -// imem_req_priv I 2 unused -// imem_req_sstatus_SUM I 1 unused -// imem_req_mstatus_MXR I 1 unused -// imem_req_satp I 32 unused -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_req_op I 2 -// dmem_req_f3 I 3 -// dmem_req_amo_funct7 I 7 reg -// dmem_req_addr I 32 -// dmem_req_store_value I 64 -// dmem_req_priv I 2 unused -// dmem_req_sstatus_SUM I 1 unused -// dmem_req_mstatus_MXR I 1 unused -// dmem_req_satp I 32 unused -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// server_fence_request_put I 8 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_imem_req I 1 -// EN_dmem_req I 1 -// EN_server_fence_i_request_put I 1 -// EN_server_fence_i_response_get I 1 -// EN_server_fence_request_put I 1 -// EN_server_fence_response_get I 1 -// EN_sfence_vma I 1 unused -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_valid -// (imem_master_awready, imem_master_wready) -> imem_instr -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, imem_master_wready, EN_imem_req) -> imem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_valid -// (dmem_master_awready, dmem_master_wready) -> dmem_word64 -// (dmem_master_awready, dmem_master_wready) -> dmem_st_amo_val -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// (dmem_master_awready, dmem_master_wready, EN_dmem_req) -> dmem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - imem_req_f3, - imem_req_addr, - imem_req_priv, - imem_req_sstatus_SUM, - imem_req_mstatus_MXR, - imem_req_satp, - EN_imem_req, - - imem_valid, - - imem_is_i32_not_i16, - - imem_pc, - - imem_instr, - - imem_exc, - - imem_exc_code, - - imem_tval, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_req_op, - dmem_req_f3, - dmem_req_amo_funct7, - dmem_req_addr, - dmem_req_store_value, - dmem_req_priv, - dmem_req_sstatus_SUM, - dmem_req_mstatus_MXR, - dmem_req_satp, - EN_dmem_req, - - dmem_valid, - - dmem_word64, - - dmem_st_amo_val, - - dmem_exc, - - dmem_exc_code, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - EN_server_fence_i_request_put, - RDY_server_fence_i_request_put, - - EN_server_fence_i_response_get, - RDY_server_fence_i_response_get, - - server_fence_request_put, - EN_server_fence_request_put, - RDY_server_fence_request_put, - - EN_server_fence_response_get, - RDY_server_fence_response_get, - - EN_sfence_vma, - RDY_sfence_vma); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method imem_req - input [2 : 0] imem_req_f3; - input [31 : 0] imem_req_addr; - input [1 : 0] imem_req_priv; - input imem_req_sstatus_SUM; - input imem_req_mstatus_MXR; - input [31 : 0] imem_req_satp; - input EN_imem_req; - - // value method imem_valid - output imem_valid; - - // value method imem_is_i32_not_i16 - output imem_is_i32_not_i16; - - // value method imem_pc - output [31 : 0] imem_pc; - - // value method imem_instr - output [31 : 0] imem_instr; - - // value method imem_exc - output imem_exc; - - // value method imem_exc_code - output [3 : 0] imem_exc_code; - - // value method imem_tval - output [31 : 0] imem_tval; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // action method dmem_req - input [1 : 0] dmem_req_op; - input [2 : 0] dmem_req_f3; - input [6 : 0] dmem_req_amo_funct7; - input [31 : 0] dmem_req_addr; - input [63 : 0] dmem_req_store_value; - input [1 : 0] dmem_req_priv; - input dmem_req_sstatus_SUM; - input dmem_req_mstatus_MXR; - input [31 : 0] dmem_req_satp; - input EN_dmem_req; - - // value method dmem_valid - output dmem_valid; - - // value method dmem_word64 - output [63 : 0] dmem_word64; - - // value method dmem_st_amo_val - output [63 : 0] dmem_st_amo_val; - - // value method dmem_exc - output dmem_exc; - - // value method dmem_exc_code - output [3 : 0] dmem_exc_code; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method server_fence_i_request_put - input EN_server_fence_i_request_put; - output RDY_server_fence_i_request_put; - - // action method server_fence_i_response_get - input EN_server_fence_i_response_get; - output RDY_server_fence_i_response_get; - - // action method server_fence_request_put - input [7 : 0] server_fence_request_put; - input EN_server_fence_request_put; - output RDY_server_fence_request_put; - - // action method server_fence_response_get - input EN_server_fence_response_get; - output RDY_server_fence_response_get; - - // action method sfence_vma - input EN_sfence_vma; - output RDY_sfence_vma; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - dmem_st_amo_val, - dmem_word64, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [31 : 0] imem_instr, imem_pc, imem_tval; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_exc_code, - dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - imem_exc_code, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_server_fence_i_request_put, - RDY_server_fence_i_response_get, - RDY_server_fence_request_put, - RDY_server_fence_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_sfence_vma, - dmem_exc, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - dmem_valid, - imem_exc, - imem_is_i32_not_i16, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid, - imem_valid; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule dcache - wire [63 : 0] dcache$mem_master_araddr, - dcache$mem_master_awaddr, - dcache$mem_master_rdata, - dcache$mem_master_wdata, - dcache$req_st_value, - dcache$st_amo_val, - dcache$word64; - wire [31 : 0] dcache$req_addr, dcache$req_satp; - wire [7 : 0] dcache$mem_master_arlen, - dcache$mem_master_awlen, - dcache$mem_master_wstrb; - wire [6 : 0] dcache$req_amo_funct7; - wire [3 : 0] dcache$exc_code, - dcache$mem_master_arcache, - dcache$mem_master_arid, - dcache$mem_master_arqos, - dcache$mem_master_arregion, - dcache$mem_master_awcache, - dcache$mem_master_awid, - dcache$mem_master_awqos, - dcache$mem_master_awregion, - dcache$mem_master_bid, - dcache$mem_master_rid, - dcache$set_verbosity_verbosity; - wire [2 : 0] dcache$mem_master_arprot, - dcache$mem_master_arsize, - dcache$mem_master_awprot, - dcache$mem_master_awsize, - dcache$req_f3; - wire [1 : 0] dcache$mem_master_arburst, - dcache$mem_master_awburst, - dcache$mem_master_bresp, - dcache$mem_master_rresp, - dcache$req_op, - dcache$req_priv; - wire dcache$EN_req, - dcache$EN_server_flush_request_put, - dcache$EN_server_flush_response_get, - dcache$EN_server_reset_request_put, - dcache$EN_server_reset_response_get, - dcache$EN_set_verbosity, - dcache$EN_tlb_flush, - dcache$RDY_server_flush_request_put, - dcache$RDY_server_flush_response_get, - dcache$RDY_server_reset_request_put, - dcache$RDY_server_reset_response_get, - dcache$exc, - dcache$mem_master_arlock, - dcache$mem_master_arready, - dcache$mem_master_arvalid, - dcache$mem_master_awlock, - dcache$mem_master_awready, - dcache$mem_master_awvalid, - dcache$mem_master_bready, - dcache$mem_master_bvalid, - dcache$mem_master_rlast, - dcache$mem_master_rready, - dcache$mem_master_rvalid, - dcache$mem_master_wlast, - dcache$mem_master_wready, - dcache$mem_master_wvalid, - dcache$req_mstatus_MXR, - dcache$req_sstatus_SUM, - dcache$valid; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule icache - wire [63 : 0] icache$mem_master_araddr, - icache$mem_master_awaddr, - icache$mem_master_rdata, - icache$mem_master_wdata, - icache$req_st_value, - icache$word64; - wire [31 : 0] icache$addr, icache$req_addr, icache$req_satp; - wire [7 : 0] icache$mem_master_arlen, - icache$mem_master_awlen, - icache$mem_master_wstrb; - wire [6 : 0] icache$req_amo_funct7; - wire [3 : 0] icache$exc_code, - icache$mem_master_arcache, - icache$mem_master_arid, - icache$mem_master_arqos, - icache$mem_master_arregion, - icache$mem_master_awcache, - icache$mem_master_awid, - icache$mem_master_awqos, - icache$mem_master_awregion, - icache$mem_master_bid, - icache$mem_master_rid, - icache$set_verbosity_verbosity; - wire [2 : 0] icache$mem_master_arprot, - icache$mem_master_arsize, - icache$mem_master_awprot, - icache$mem_master_awsize, - icache$req_f3; - wire [1 : 0] icache$mem_master_arburst, - icache$mem_master_awburst, - icache$mem_master_bresp, - icache$mem_master_rresp, - icache$req_op, - icache$req_priv; - wire icache$EN_req, - icache$EN_server_flush_request_put, - icache$EN_server_flush_response_get, - icache$EN_server_reset_request_put, - icache$EN_server_reset_response_get, - icache$EN_set_verbosity, - icache$EN_tlb_flush, - icache$RDY_server_flush_request_put, - icache$RDY_server_flush_response_get, - icache$RDY_server_reset_request_put, - icache$RDY_server_reset_response_get, - icache$exc, - icache$mem_master_arlock, - icache$mem_master_arready, - icache$mem_master_arvalid, - icache$mem_master_awlock, - icache$mem_master_awready, - icache$mem_master_awvalid, - icache$mem_master_bready, - icache$mem_master_bvalid, - icache$mem_master_rlast, - icache$mem_master_rready, - icache$mem_master_rvalid, - icache$mem_master_wlast, - icache$mem_master_wready, - icache$mem_master_wvalid, - icache$req_mstatus_MXR, - icache$req_sstatus_SUM, - icache$valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_dmem_req, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_imem_req, - CAN_FIRE_server_fence_i_request_put, - CAN_FIRE_server_fence_i_response_get, - CAN_FIRE_server_fence_request_put, - CAN_FIRE_server_fence_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_sfence_vma, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_dmem_req, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_imem_req, - WILL_FIRE_server_fence_i_request_put, - WILL_FIRE_server_fence_i_response_get, - WILL_FIRE_server_fence_request_put, - WILL_FIRE_server_fence_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_sfence_vma; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h1659; - reg [31 : 0] v__h1810; - reg [31 : 0] v__h1653; - reg [31 : 0] v__h1804; - // synopsys translate_on - - // remaining internal signals - wire NOT_cfg_verbosity_read_ULE_1___d9; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = rg_state == 2'd2 ; - assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method imem_req - assign CAN_FIRE_imem_req = 1'd1 ; - assign WILL_FIRE_imem_req = EN_imem_req ; - - // value method imem_valid - assign imem_valid = icache$valid ; - - // value method imem_is_i32_not_i16 - assign imem_is_i32_not_i16 = 1'd1 ; - - // value method imem_pc - assign imem_pc = icache$addr ; - - // value method imem_instr - assign imem_instr = icache$word64[31:0] ; - - // value method imem_exc - assign imem_exc = icache$exc ; - - // value method imem_exc_code - assign imem_exc_code = icache$exc_code ; - - // value method imem_tval - assign imem_tval = icache$addr ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = icache$mem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = icache$mem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = icache$mem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = icache$mem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = icache$mem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = icache$mem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = icache$mem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = icache$mem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = icache$mem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = icache$mem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = icache$mem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = icache$mem_master_wvalid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = icache$mem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = icache$mem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = icache$mem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = icache$mem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = icache$mem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = icache$mem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = icache$mem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = icache$mem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = icache$mem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = icache$mem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = icache$mem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = icache$mem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = icache$mem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = icache$mem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = icache$mem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = icache$mem_master_rready ; - - // action method dmem_req - assign CAN_FIRE_dmem_req = 1'd1 ; - assign WILL_FIRE_dmem_req = EN_dmem_req ; - - // value method dmem_valid - assign dmem_valid = dcache$valid ; - - // value method dmem_word64 - assign dmem_word64 = dcache$word64 ; - - // value method dmem_st_amo_val - assign dmem_st_amo_val = dcache$st_amo_val ; - - // value method dmem_exc - assign dmem_exc = dcache$exc ; - - // value method dmem_exc_code - assign dmem_exc_code = dcache$exc_code ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = dcache$mem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = dcache$mem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = dcache$mem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = dcache$mem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = dcache$mem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = dcache$mem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = dcache$mem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = dcache$mem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = dcache$mem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = dcache$mem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = dcache$mem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = dcache$mem_master_wvalid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = dcache$mem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = dcache$mem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = dcache$mem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = dcache$mem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = dcache$mem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = dcache$mem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = dcache$mem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = dcache$mem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = dcache$mem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = dcache$mem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = dcache$mem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = dcache$mem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = dcache$mem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = dcache$mem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = dcache$mem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = dcache$mem_master_rready ; - - // action method server_fence_i_request_put - assign RDY_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_i_request_put = - EN_server_fence_i_request_put ; - - // action method server_fence_i_response_get - assign RDY_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_i_response_get = - EN_server_fence_i_response_get ; - - // action method server_fence_request_put - assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_request_put = - dcache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ; - - // action method server_fence_response_get - assign RDY_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ; - - // action method sfence_vma - assign RDY_sfence_vma = 1'd1 ; - assign CAN_FIRE_sfence_vma = 1'd1 ; - assign WILL_FIRE_sfence_vma = EN_sfence_vma ; - - // submodule dcache - mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(dcache$mem_master_arready), - .mem_master_awready(dcache$mem_master_awready), - .mem_master_bid(dcache$mem_master_bid), - .mem_master_bresp(dcache$mem_master_bresp), - .mem_master_bvalid(dcache$mem_master_bvalid), - .mem_master_rdata(dcache$mem_master_rdata), - .mem_master_rid(dcache$mem_master_rid), - .mem_master_rlast(dcache$mem_master_rlast), - .mem_master_rresp(dcache$mem_master_rresp), - .mem_master_rvalid(dcache$mem_master_rvalid), - .mem_master_wready(dcache$mem_master_wready), - .req_addr(dcache$req_addr), - .req_amo_funct7(dcache$req_amo_funct7), - .req_f3(dcache$req_f3), - .req_mstatus_MXR(dcache$req_mstatus_MXR), - .req_op(dcache$req_op), - .req_priv(dcache$req_priv), - .req_satp(dcache$req_satp), - .req_sstatus_SUM(dcache$req_sstatus_SUM), - .req_st_value(dcache$req_st_value), - .set_verbosity_verbosity(dcache$set_verbosity_verbosity), - .EN_set_verbosity(dcache$EN_set_verbosity), - .EN_server_reset_request_put(dcache$EN_server_reset_request_put), - .EN_server_reset_response_get(dcache$EN_server_reset_response_get), - .EN_req(dcache$EN_req), - .EN_server_flush_request_put(dcache$EN_server_flush_request_put), - .EN_server_flush_response_get(dcache$EN_server_flush_response_get), - .EN_tlb_flush(dcache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), - .valid(dcache$valid), - .addr(), - .word64(dcache$word64), - .st_amo_val(dcache$st_amo_val), - .exc(dcache$exc), - .exc_code(dcache$exc_code), - .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(dcache$mem_master_awvalid), - .mem_master_awid(dcache$mem_master_awid), - .mem_master_awaddr(dcache$mem_master_awaddr), - .mem_master_awlen(dcache$mem_master_awlen), - .mem_master_awsize(dcache$mem_master_awsize), - .mem_master_awburst(dcache$mem_master_awburst), - .mem_master_awlock(dcache$mem_master_awlock), - .mem_master_awcache(dcache$mem_master_awcache), - .mem_master_awprot(dcache$mem_master_awprot), - .mem_master_awqos(dcache$mem_master_awqos), - .mem_master_awregion(dcache$mem_master_awregion), - .mem_master_wvalid(dcache$mem_master_wvalid), - .mem_master_wdata(dcache$mem_master_wdata), - .mem_master_wstrb(dcache$mem_master_wstrb), - .mem_master_wlast(dcache$mem_master_wlast), - .mem_master_bready(dcache$mem_master_bready), - .mem_master_arvalid(dcache$mem_master_arvalid), - .mem_master_arid(dcache$mem_master_arid), - .mem_master_araddr(dcache$mem_master_araddr), - .mem_master_arlen(dcache$mem_master_arlen), - .mem_master_arsize(dcache$mem_master_arsize), - .mem_master_arburst(dcache$mem_master_arburst), - .mem_master_arlock(dcache$mem_master_arlock), - .mem_master_arcache(dcache$mem_master_arcache), - .mem_master_arprot(dcache$mem_master_arprot), - .mem_master_arqos(dcache$mem_master_arqos), - .mem_master_arregion(dcache$mem_master_arregion), - .mem_master_rready(dcache$mem_master_rready)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule icache - mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(icache$mem_master_arready), - .mem_master_awready(icache$mem_master_awready), - .mem_master_bid(icache$mem_master_bid), - .mem_master_bresp(icache$mem_master_bresp), - .mem_master_bvalid(icache$mem_master_bvalid), - .mem_master_rdata(icache$mem_master_rdata), - .mem_master_rid(icache$mem_master_rid), - .mem_master_rlast(icache$mem_master_rlast), - .mem_master_rresp(icache$mem_master_rresp), - .mem_master_rvalid(icache$mem_master_rvalid), - .mem_master_wready(icache$mem_master_wready), - .req_addr(icache$req_addr), - .req_amo_funct7(icache$req_amo_funct7), - .req_f3(icache$req_f3), - .req_mstatus_MXR(icache$req_mstatus_MXR), - .req_op(icache$req_op), - .req_priv(icache$req_priv), - .req_satp(icache$req_satp), - .req_sstatus_SUM(icache$req_sstatus_SUM), - .req_st_value(icache$req_st_value), - .set_verbosity_verbosity(icache$set_verbosity_verbosity), - .EN_set_verbosity(icache$EN_set_verbosity), - .EN_server_reset_request_put(icache$EN_server_reset_request_put), - .EN_server_reset_response_get(icache$EN_server_reset_response_get), - .EN_req(icache$EN_req), - .EN_server_flush_request_put(icache$EN_server_flush_request_put), - .EN_server_flush_response_get(icache$EN_server_flush_response_get), - .EN_tlb_flush(icache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), - .valid(icache$valid), - .addr(icache$addr), - .word64(icache$word64), - .st_amo_val(), - .exc(icache$exc), - .exc_code(icache$exc_code), - .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(icache$mem_master_awvalid), - .mem_master_awid(icache$mem_master_awid), - .mem_master_awaddr(icache$mem_master_awaddr), - .mem_master_awlen(icache$mem_master_awlen), - .mem_master_awsize(icache$mem_master_awsize), - .mem_master_awburst(icache$mem_master_awburst), - .mem_master_awlock(icache$mem_master_awlock), - .mem_master_awcache(icache$mem_master_awcache), - .mem_master_awprot(icache$mem_master_awprot), - .mem_master_awqos(icache$mem_master_awqos), - .mem_master_awregion(icache$mem_master_awregion), - .mem_master_wvalid(icache$mem_master_wvalid), - .mem_master_wdata(icache$mem_master_wdata), - .mem_master_wstrb(icache$mem_master_wstrb), - .mem_master_wlast(icache$mem_master_wlast), - .mem_master_bready(icache$mem_master_bready), - .mem_master_arvalid(icache$mem_master_arvalid), - .mem_master_arid(icache$mem_master_arid), - .mem_master_araddr(icache$mem_master_araddr), - .mem_master_arlen(icache$mem_master_arlen), - .mem_master_arsize(icache$mem_master_arsize), - .mem_master_arburst(icache$mem_master_arburst), - .mem_master_arlock(icache$mem_master_arlock), - .mem_master_arcache(icache$mem_master_arcache), - .mem_master_arprot(icache$mem_master_arprot), - .mem_master_arqos(icache$mem_master_arqos), - .mem_master_arregion(icache$mem_master_arregion), - .mem_master_rready(icache$mem_master_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - dcache$RDY_server_reset_request_put && - icache$RDY_server_reset_request_put && - rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && - !EN_server_fence_i_request_put ; - assign MUX_rg_state$write_1__SEL_3 = - dcache$RDY_server_reset_response_get && - icache$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - rg_state == 2'd1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete) - begin - case (1'b1) // synopsys parallel_case - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1; - WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset || - WILL_FIRE_RL_rl_reset_complete ; - - // submodule dcache - assign dcache$mem_master_arready = dmem_master_arready ; - assign dcache$mem_master_awready = dmem_master_awready ; - assign dcache$mem_master_bid = dmem_master_bid ; - assign dcache$mem_master_bresp = dmem_master_bresp ; - assign dcache$mem_master_bvalid = dmem_master_bvalid ; - assign dcache$mem_master_rdata = dmem_master_rdata ; - assign dcache$mem_master_rid = dmem_master_rid ; - assign dcache$mem_master_rlast = dmem_master_rlast ; - assign dcache$mem_master_rresp = dmem_master_rresp ; - assign dcache$mem_master_rvalid = dmem_master_rvalid ; - assign dcache$mem_master_wready = dmem_master_wready ; - assign dcache$req_addr = dmem_req_addr ; - assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ; - assign dcache$req_f3 = dmem_req_f3 ; - assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ; - assign dcache$req_op = dmem_req_op ; - assign dcache$req_priv = dmem_req_priv ; - assign dcache$req_satp = dmem_req_satp ; - assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ; - assign dcache$req_st_value = dmem_req_store_value ; - assign dcache$set_verbosity_verbosity = 4'h0 ; - assign dcache$EN_set_verbosity = 1'b0 ; - assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign dcache$EN_req = EN_dmem_req ; - assign dcache$EN_server_flush_request_put = - EN_server_fence_i_request_put || EN_server_fence_request_put ; - assign dcache$EN_server_flush_response_get = - EN_server_fence_i_response_get || EN_server_fence_response_get ; - assign dcache$EN_tlb_flush = EN_sfence_vma ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule icache - assign icache$mem_master_arready = imem_master_arready ; - assign icache$mem_master_awready = imem_master_awready ; - assign icache$mem_master_bid = imem_master_bid ; - assign icache$mem_master_bresp = imem_master_bresp ; - assign icache$mem_master_bvalid = imem_master_bvalid ; - assign icache$mem_master_rdata = imem_master_rdata ; - assign icache$mem_master_rid = imem_master_rid ; - assign icache$mem_master_rlast = imem_master_rlast ; - assign icache$mem_master_rresp = imem_master_rresp ; - assign icache$mem_master_rvalid = imem_master_rvalid ; - assign icache$mem_master_wready = imem_master_wready ; - assign icache$req_addr = imem_req_addr ; - assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ; - assign icache$req_f3 = imem_req_f3 ; - assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ; - assign icache$req_op = 2'd0 ; - assign icache$req_priv = imem_req_priv ; - assign icache$req_satp = imem_req_satp ; - assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ; - assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign icache$set_verbosity_verbosity = 4'h0 ; - assign icache$EN_set_verbosity = 1'b0 ; - assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign icache$EN_req = EN_imem_req ; - assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ; - assign icache$EN_server_flush_response_get = - EN_server_fence_i_response_get ; - assign icache$EN_tlb_flush = EN_sfence_vma ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1659 = $stime; - #0; - end - v__h1653 = v__h1659 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset", v__h1653); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1810 = $stime; - #0; - end - v__h1804 = v__h1810 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset_complete", v__h1804); - end - // synopsys translate_on -endmodule // mkNear_Mem - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v deleted file mode 100644 index 32e93584..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v +++ /dev/null @@ -1,1308 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// RDY_server_request_put O 1 reg -// server_response_get O 66 reg -// RDY_server_response_get O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// server_request_put I 137 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_server_request_put I 1 -// EN_server_response_get I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - server_request_put, - EN_server_request_put, - RDY_server_request_put, - - EN_server_response_get, - server_response_get, - RDY_server_response_get, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method server_request_put - input [136 : 0] server_request_put; - input EN_server_request_put; - output RDY_server_request_put; - - // actionvalue method server_response_get - input EN_server_response_get; - output [65 : 0] server_response_get; - output RDY_server_response_get; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [65 : 0] server_response_get; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_request_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_server_response_get, - RDY_set_addr_map, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reqs - wire [136 : 0] f_reqs$D_IN, f_reqs$D_OUT; - wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_rsps - wire [65 : 0] f_rsps$D_IN, f_rsps$D_OUT; - wire f_rsps$CLR, f_rsps$DEQ, f_rsps$EMPTY_N, f_rsps$ENQ, f_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_request_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_server_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_request_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_server_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire [65 : 0] MUX_f_rsps$enq_1__VAL_1, MUX_f_rsps$enq_1__VAL_2; - wire [63 : 0] MUX_crg_time$port1__write_1__VAL_1, - MUX_crg_timecmp$port1__write_1__VAL_1; - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8676; - reg [31 : 0] v__h8808; - reg [31 : 0] v__h1471; - reg [31 : 0] v__h1868; - reg [31 : 0] v__h2065; - reg [31 : 0] v__h1714; - reg [31 : 0] v__h2442; - reg [31 : 0] v__h7890; - reg [31 : 0] v__h8258; - reg [31 : 0] v__h8368; - reg [31 : 0] v__h8475; - reg [31 : 0] v__h1465; - reg [31 : 0] v__h1708; - reg [31 : 0] v__h1862; - reg [31 : 0] v__h2059; - reg [31 : 0] v__h2436; - reg [31 : 0] v__h7884; - reg [31 : 0] v__h8252; - reg [31 : 0] v__h8362; - reg [31 : 0] v__h8469; - reg [31 : 0] v__h8670; - reg [31 : 0] v__h8802; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rsp_rdata__h2209; - wire [63 : 0] byte_addr__h1981, - mask__h2865, - mask__h5362, - new_data__h5360, - new_time__h4107, - new_time__h6632, - new_timecmp__h2834, - new_timecmp__h5331, - old_time__h6631, - rdata__h1996, - rdata__h2020, - rdata__h2026, - x__h2876, - x__h4149, - x__h5373, - x__h6674, - y__h2877, - y__h2878, - y__h5374, - y__h5375; - wire [7 : 0] SEXT_f_reqs_first__8_BIT_0_31___d132, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_7_07___d108; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method server_request_put - assign RDY_server_request_put = f_reqs$FULL_N ; - assign CAN_FIRE_server_request_put = f_reqs$FULL_N ; - assign WILL_FIRE_server_request_put = EN_server_request_put ; - - // actionvalue method server_response_get - assign server_response_get = f_rsps$D_OUT ; - assign RDY_server_response_get = f_rsps$EMPTY_N ; - assign CAN_FIRE_server_response_get = f_rsps$EMPTY_N ; - assign WILL_FIRE_server_response_get = EN_server_response_get ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reqs - FIFO2 #(.width(32'd137), .guarded(32'd1)) f_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reqs$D_IN), - .ENQ(f_reqs$ENQ), - .DEQ(f_reqs$DEQ), - .CLR(f_reqs$CLR), - .D_OUT(f_reqs$D_OUT), - .FULL_N(f_reqs$FULL_N), - .EMPTY_N(f_reqs$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_rsps - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_rsps$D_IN), - .ENQ(f_rsps$ENQ), - .DEQ(f_rsps$DEQ), - .CLR(f_rsps$CLR), - .D_OUT(f_rsps$D_OUT), - .FULL_N(f_rsps$FULL_N), - .EMPTY_N(f_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && rg_state && - !f_reset_reqs$EMPTY_N && - f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && - (byte_addr__h1981 != 64'h0 || - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - f_sw_interrupt_req$FULL_N) && - rg_state && - !f_reset_reqs$EMPTY_N && - !f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign MUX_crg_time$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h000000000000BFF8) ? - new_time__h4107 : - new_time__h6632 ; - assign MUX_crg_timecmp$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h0000000000004000) ? - new_timecmp__h2834 : - new_timecmp__h5331 ; - assign MUX_f_rsps$enq_1__VAL_1 = - { 1'd1, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - rsp_rdata__h2209 } ; - assign MUX_f_rsps$enq_1__VAL_2 = - { 1'd0, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - 64'hAAAAAAAAAAAAAAAA } ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? - MUX_crg_time$port1__write_1__VAL_1 : - 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h6631 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - MUX_crg_timecmp$port1__write_1__VAL_1 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = MUX_rg_msip$write_1__SEL_1 && f_reqs$D_OUT[8] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reqs - assign f_reqs$D_IN = server_request_put ; - assign f_reqs$ENQ = EN_server_request_put ; - assign f_reqs$DEQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_rsps - assign f_rsps$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_f_rsps$enq_1__VAL_1 : - MUX_f_rsps$enq_1__VAL_2 ; - assign f_rsps$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_process_wr_req ; - assign f_rsps$DEQ = EN_server_response_get ; - assign f_rsps$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = f_reqs$D_OUT[8] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_f_reqs_first__8_BIT_0_31___d132 = {8{f_reqs$D_OUT[0]}} ; - assign SEXT_f_reqs_first__8_BIT_1_28___d129 = {8{f_reqs$D_OUT[1]}} ; - assign SEXT_f_reqs_first__8_BIT_2_24___d125 = {8{f_reqs$D_OUT[2]}} ; - assign SEXT_f_reqs_first__8_BIT_3_21___d122 = {8{f_reqs$D_OUT[3]}} ; - assign SEXT_f_reqs_first__8_BIT_4_17___d118 = {8{f_reqs$D_OUT[4]}} ; - assign SEXT_f_reqs_first__8_BIT_5_14___d115 = {8{f_reqs$D_OUT[5]}} ; - assign SEXT_f_reqs_first__8_BIT_6_10___d111 = {8{f_reqs$D_OUT[6]}} ; - assign SEXT_f_reqs_first__8_BIT_7_07___d108 = {8{f_reqs$D_OUT[7]}} ; - assign byte_addr__h1981 = f_reqs$D_OUT[135:72] - rg_addr_base ; - assign mask__h2865 = - { SEXT_f_reqs_first__8_BIT_7_07___d108, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign mask__h5362 = - { SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'd0 } ; - assign new_data__h5360 = { f_reqs$D_OUT[39:8], 32'h0 } ; - assign new_time__h4107 = x__h4149 | y__h2877 ; - assign new_time__h6632 = x__h6674 | y__h5374 ; - assign new_timecmp__h2834 = x__h2876 | y__h2877 ; - assign new_timecmp__h5331 = x__h5373 | y__h5374 ; - assign old_time__h6631 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata__h1996 = { 63'd0, rg_msip } ; - assign rdata__h2020 = { 32'd0, crg_timecmp[63:32] } ; - assign rdata__h2026 = { 32'd0, crg_time[63:32] } ; - assign rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 = - rg_msip == f_reqs$D_OUT[8] ; - assign x__h2876 = crg_timecmp & y__h2878 ; - assign x__h4149 = old_time__h6631 & y__h2878 ; - assign x__h5373 = crg_timecmp & y__h5375 ; - assign x__h6674 = old_time__h6631 & y__h5375 ; - assign y__h2877 = f_reqs$D_OUT[71:8] & mask__h2865 ; - assign y__h2878 = - { ~SEXT_f_reqs_first__8_BIT_7_07___d108, - ~SEXT_f_reqs_first__8_BIT_6_10___d111, - ~SEXT_f_reqs_first__8_BIT_5_14___d115, - ~SEXT_f_reqs_first__8_BIT_4_17___d118, - ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign y__h5374 = new_data__h5360 & mask__h5362 ; - assign y__h5375 = - { ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'hFFFFFFFF } ; - always@(byte_addr__h1981 or - rdata__h1996 or - crg_timecmp or rdata__h2020 or crg_time or rdata__h2026) - begin - case (byte_addr__h1981) - 64'h0: rsp_rdata__h2209 = rdata__h1996; - 64'h0000000000000004: rsp_rdata__h2209 = 64'd0; - 64'h0000000000004000: rsp_rdata__h2209 = crg_timecmp; - 64'h0000000000004004: rsp_rdata__h2209 = rdata__h2020; - 64'h000000000000BFF8: rsp_rdata__h2209 = crg_time; - 64'h000000000000BFFC: rsp_rdata__h2209 = rdata__h2026; - default: rsp_rdata__h2209 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8676 = $stime; - #0; - end - v__h8670 = v__h8676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_timer_interrupt_req: %x", - v__h8670, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8808 = $stime; - #0; - end - v__h8802 = v__h8808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_sw_interrupt_req: %x", - v__h8802, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1471 = $stime; - #0; - end - v__h1465 = v__h1471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO.rl_reset", v__h1465); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1868 = $stime; - #0; - end - v__h1862 = v__h1868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_rd_req: rg_mtip = %0d", - v__h1862, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h2065 = $stime; - #0; - end - v__h2059 = v__h2065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_rd_req: unrecognized addr", - v__h2059); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rsp_rdata__h2209, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1714 = $stime; - #0; - end - v__h1708 = v__h1714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h1708, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2442 = $stime; - #0; - end - v__h2436 = v__h2442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_wr_req: rg_mtip = %0d", - v__h2436, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", f_reqs$D_OUT[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h2834); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h2834 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h4107); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h5331); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h5331 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h6632); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h7890 = $stime; - #0; - end - v__h7884 = v__h7890 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_wr_req: unrecognized addr", - v__h7884); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 64'hAAAAAAAAAAAAAAAA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h8258 = $stime; - #0; - end - v__h8252 = v__h8258 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h8252, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h8368 = $stime; - #0; - end - v__h8362 = v__h8368 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h8362, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h8475 = $stime; - #0; - end - v__h8469 = v__h8475 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h8469, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v deleted file mode 100644 index fc8cf99e..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v +++ /dev/null @@ -1,2762 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO_AXI4(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h10050; - reg [31 : 0] v__h10182; - reg [31 : 0] v__h1852; - reg [31 : 0] v__h2269; - reg [31 : 0] v__h2453; - reg [31 : 0] v__h2640; - reg [31 : 0] v__h2878; - reg [31 : 0] v__h2095; - reg [31 : 0] v__h3158; - reg [31 : 0] v__h3384; - reg [31 : 0] v__h8918; - reg [31 : 0] v__h9137; - reg [31 : 0] v__h9462; - reg [31 : 0] v__h9572; - reg [31 : 0] v__h9679; - reg [31 : 0] v__h1846; - reg [31 : 0] v__h2089; - reg [31 : 0] v__h2263; - reg [31 : 0] v__h2447; - reg [31 : 0] v__h2634; - reg [31 : 0] v__h2872; - reg [31 : 0] v__h3152; - reg [31 : 0] v__h3378; - reg [31 : 0] v__h8912; - reg [31 : 0] v__h9131; - reg [31 : 0] v__h9456; - reg [31 : 0] v__h9566; - reg [31 : 0] v__h9673; - reg [31 : 0] v__h10044; - reg [31 : 0] v__h10176; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] _theResult___fst__h2566; - reg [1 : 0] _theResult___snd__h2567, v__h3508; - wire [63 : 0] byte_addr__h2405, - byte_addr__h3346, - crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189, - mask__h3789, - new_time__h5047, - new_timecmp__h3758, - old_time__h7605, - rdata___1__h2562, - x__h2751, - x__h3800, - x__h5089, - y__h3801, - y__h3802; - wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155, - SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152; - wire [1 : 0] rresp__h2548, v__h3350; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108, - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53, - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102, - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h000000000000BFF8 || - byte_addr__h3346 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h0000000000004000 || - byte_addr__h3346 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h000000000000BFF8 || - byte_addr__h3346 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? new_time__h5047 : 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h7605 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h0000000000004000 || - byte_addr__h3346 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - new_timecmp__h3758 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = - MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - x__h2751, - rresp__h2548, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3350 } ; - assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 = - {8{slave_xactor_f_wr_data$D_OUT[1]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173 = - {8{slave_xactor_f_wr_data$D_OUT[2]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169 = - {8{slave_xactor_f_wr_data$D_OUT[3]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166 = - {8{slave_xactor_f_wr_data$D_OUT[4]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162 = - {8{slave_xactor_f_wr_data$D_OUT[5]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159 = - {8{slave_xactor_f_wr_data$D_OUT[6]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155 = - {8{slave_xactor_f_wr_data$D_OUT[7]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152 = - {8{slave_xactor_f_wr_data$D_OUT[8]}} ; - assign byte_addr__h2405 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign byte_addr__h3346 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189 = - new_timecmp__h3758 - old_time__h7605 ; - assign mask__h3789 = - { SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173, - SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 } ; - assign new_time__h5047 = x__h5089 | y__h3801 ; - assign new_timecmp__h3758 = x__h3800 | y__h3801 ; - assign old_time__h7605 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata___1__h2562 = { 63'd0, rg_msip } ; - assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 = - rg_msip == slave_xactor_f_wr_data$D_OUT[9] ; - assign rresp__h2548 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 2'b11 : - _theResult___snd__h2567 ; - assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 = - slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 = - slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 || - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - f_sw_interrupt_req$FULL_N) ; - assign v__h3350 = - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ? - 2'b11 : - v__h3508 ; - assign x__h2751 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 64'd0 : - _theResult___fst__h2566 ; - assign x__h3800 = crg_timecmp & y__h3802 ; - assign x__h5089 = old_time__h7605 & y__h3802 ; - assign y__h3801 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3789 ; - assign y__h3802 = - { ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 } ; - always@(byte_addr__h2405) - begin - case (byte_addr__h2405) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - _theResult___snd__h2567 = 2'b0; - default: _theResult___snd__h2567 = 2'b11; - endcase - end - always@(byte_addr__h2405 or rdata___1__h2562 or crg_timecmp or crg_time) - begin - case (byte_addr__h2405) - 64'h0: _theResult___fst__h2566 = rdata___1__h2562; - 64'h0000000000000004: _theResult___fst__h2566 = 64'd0; - 64'h0000000000004000, 64'h0000000000004004: - _theResult___fst__h2566 = crg_timecmp; - 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___fst__h2566 = crg_time; - default: _theResult___fst__h2566 = 64'd0; - endcase - end - always@(byte_addr__h3346) - begin - case (byte_addr__h3346) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - v__h3508 = 2'b0; - default: v__h3508 = 2'b11; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10050 = $stime; - #0; - end - v__h10044 = v__h10050 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x", - v__h10044, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10182 = $stime; - #0; - end - v__h10176 = v__h10182 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x", - v__h10176, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1852 = $stime; - #0; - end - v__h1846 = v__h1852 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1846); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2269 = $stime; - #0; - end - v__h2263 = v__h2269 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", - v__h2263, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - begin - v__h2453 = $stime; - #0; - end - v__h2447 = v__h2453 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2447); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - begin - v__h2640 = $stime; - #0; - end - v__h2634 = v__h2640 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2634); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2878 = $stime; - #0; - end - v__h2872 = v__h2878 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2872); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", x__h2751); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rresp__h2548); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2095 = $stime; - #0; - end - v__h2089 = v__h2095 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h2089, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h3158 = $stime; - #0; - end - v__h3152 = v__h3158 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", - v__h3152, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - begin - v__h3384 = $stime; - #0; - end - v__h3378 = v__h3384 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h3378); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3758); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7605); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7605); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5047); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3758); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7605); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7605); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5047); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - begin - v__h8918 = $stime; - #0; - end - v__h8912 = v__h8918 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h8912); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h9137 = $stime; - #0; - end - v__h9131 = v__h9137 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9131); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", v__h3350); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h9462 = $stime; - #0; - end - v__h9456 = v__h9462 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9456, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h9572 = $stime; - #0; - end - v__h9566 = v__h9572 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9566, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h9679 = $stime; - #0; - end - v__h9673 = v__h9679 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9673, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO_AXI4 - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v deleted file mode 100644 index 5dd601d7..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v +++ /dev/null @@ -1,26951 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_show_PLIC_state O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// v_targets_0_m_eip O 1 -// v_targets_1_m_eip O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// v_sources_0_m_interrupt_req_set_not_clear I 1 -// v_sources_1_m_interrupt_req_set_not_clear I 1 -// v_sources_2_m_interrupt_req_set_not_clear I 1 -// v_sources_3_m_interrupt_req_set_not_clear I 1 -// v_sources_4_m_interrupt_req_set_not_clear I 1 -// v_sources_5_m_interrupt_req_set_not_clear I 1 -// v_sources_6_m_interrupt_req_set_not_clear I 1 -// v_sources_7_m_interrupt_req_set_not_clear I 1 -// v_sources_8_m_interrupt_req_set_not_clear I 1 -// v_sources_9_m_interrupt_req_set_not_clear I 1 -// v_sources_10_m_interrupt_req_set_not_clear I 1 -// v_sources_11_m_interrupt_req_set_not_clear I 1 -// v_sources_12_m_interrupt_req_set_not_clear I 1 -// v_sources_13_m_interrupt_req_set_not_clear I 1 -// v_sources_14_m_interrupt_req_set_not_clear I 1 -// v_sources_15_m_interrupt_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_show_PLIC_state I 1 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkPLIC_16_2_7(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_show_PLIC_state, - RDY_show_PLIC_state, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - v_sources_0_m_interrupt_req_set_not_clear, - - v_sources_1_m_interrupt_req_set_not_clear, - - v_sources_2_m_interrupt_req_set_not_clear, - - v_sources_3_m_interrupt_req_set_not_clear, - - v_sources_4_m_interrupt_req_set_not_clear, - - v_sources_5_m_interrupt_req_set_not_clear, - - v_sources_6_m_interrupt_req_set_not_clear, - - v_sources_7_m_interrupt_req_set_not_clear, - - v_sources_8_m_interrupt_req_set_not_clear, - - v_sources_9_m_interrupt_req_set_not_clear, - - v_sources_10_m_interrupt_req_set_not_clear, - - v_sources_11_m_interrupt_req_set_not_clear, - - v_sources_12_m_interrupt_req_set_not_clear, - - v_sources_13_m_interrupt_req_set_not_clear, - - v_sources_14_m_interrupt_req_set_not_clear, - - v_sources_15_m_interrupt_req_set_not_clear, - - v_targets_0_m_eip, - - v_targets_1_m_eip); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method show_PLIC_state - input EN_show_PLIC_state; - output RDY_show_PLIC_state; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // action method v_sources_0_m_interrupt_req - input v_sources_0_m_interrupt_req_set_not_clear; - - // action method v_sources_1_m_interrupt_req - input v_sources_1_m_interrupt_req_set_not_clear; - - // action method v_sources_2_m_interrupt_req - input v_sources_2_m_interrupt_req_set_not_clear; - - // action method v_sources_3_m_interrupt_req - input v_sources_3_m_interrupt_req_set_not_clear; - - // action method v_sources_4_m_interrupt_req - input v_sources_4_m_interrupt_req_set_not_clear; - - // action method v_sources_5_m_interrupt_req - input v_sources_5_m_interrupt_req_set_not_clear; - - // action method v_sources_6_m_interrupt_req - input v_sources_6_m_interrupt_req_set_not_clear; - - // action method v_sources_7_m_interrupt_req - input v_sources_7_m_interrupt_req_set_not_clear; - - // action method v_sources_8_m_interrupt_req - input v_sources_8_m_interrupt_req_set_not_clear; - - // action method v_sources_9_m_interrupt_req - input v_sources_9_m_interrupt_req_set_not_clear; - - // action method v_sources_10_m_interrupt_req - input v_sources_10_m_interrupt_req_set_not_clear; - - // action method v_sources_11_m_interrupt_req - input v_sources_11_m_interrupt_req_set_not_clear; - - // action method v_sources_12_m_interrupt_req - input v_sources_12_m_interrupt_req_set_not_clear; - - // action method v_sources_13_m_interrupt_req - input v_sources_13_m_interrupt_req_set_not_clear; - - // action method v_sources_14_m_interrupt_req - input v_sources_14_m_interrupt_req_set_not_clear; - - // action method v_sources_15_m_interrupt_req - input v_sources_15_m_interrupt_req_set_not_clear; - - // value method v_targets_0_m_eip - output v_targets_0_m_eip; - - // value method v_targets_1_m_eip - output v_targets_1_m_eip; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_verbosity, - RDY_show_PLIC_state, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - v_targets_0_m_eip, - v_targets_1_m_eip; - - // register m_cfg_verbosity - reg [3 : 0] m_cfg_verbosity; - wire [3 : 0] m_cfg_verbosity$D_IN; - wire m_cfg_verbosity$EN; - - // register m_rg_addr_base - reg [63 : 0] m_rg_addr_base; - wire [63 : 0] m_rg_addr_base$D_IN; - wire m_rg_addr_base$EN; - - // register m_rg_addr_lim - reg [63 : 0] m_rg_addr_lim; - wire [63 : 0] m_rg_addr_lim$D_IN; - wire m_rg_addr_lim$EN; - - // register m_vrg_servicing_source_0 - reg [4 : 0] m_vrg_servicing_source_0; - wire [4 : 0] m_vrg_servicing_source_0$D_IN; - wire m_vrg_servicing_source_0$EN; - - // register m_vrg_servicing_source_1 - reg [4 : 0] m_vrg_servicing_source_1; - wire [4 : 0] m_vrg_servicing_source_1$D_IN; - wire m_vrg_servicing_source_1$EN; - - // register m_vrg_source_busy_0 - reg m_vrg_source_busy_0; - wire m_vrg_source_busy_0$D_IN, m_vrg_source_busy_0$EN; - - // register m_vrg_source_busy_1 - reg m_vrg_source_busy_1; - wire m_vrg_source_busy_1$D_IN, m_vrg_source_busy_1$EN; - - // register m_vrg_source_busy_10 - reg m_vrg_source_busy_10; - wire m_vrg_source_busy_10$D_IN, m_vrg_source_busy_10$EN; - - // register m_vrg_source_busy_11 - reg m_vrg_source_busy_11; - wire m_vrg_source_busy_11$D_IN, m_vrg_source_busy_11$EN; - - // register m_vrg_source_busy_12 - reg m_vrg_source_busy_12; - wire m_vrg_source_busy_12$D_IN, m_vrg_source_busy_12$EN; - - // register m_vrg_source_busy_13 - reg m_vrg_source_busy_13; - wire m_vrg_source_busy_13$D_IN, m_vrg_source_busy_13$EN; - - // register m_vrg_source_busy_14 - reg m_vrg_source_busy_14; - wire m_vrg_source_busy_14$D_IN, m_vrg_source_busy_14$EN; - - // register m_vrg_source_busy_15 - reg m_vrg_source_busy_15; - wire m_vrg_source_busy_15$D_IN, m_vrg_source_busy_15$EN; - - // register m_vrg_source_busy_16 - reg m_vrg_source_busy_16; - wire m_vrg_source_busy_16$D_IN, m_vrg_source_busy_16$EN; - - // register m_vrg_source_busy_2 - reg m_vrg_source_busy_2; - wire m_vrg_source_busy_2$D_IN, m_vrg_source_busy_2$EN; - - // register m_vrg_source_busy_3 - reg m_vrg_source_busy_3; - wire m_vrg_source_busy_3$D_IN, m_vrg_source_busy_3$EN; - - // register m_vrg_source_busy_4 - reg m_vrg_source_busy_4; - wire m_vrg_source_busy_4$D_IN, m_vrg_source_busy_4$EN; - - // register m_vrg_source_busy_5 - reg m_vrg_source_busy_5; - wire m_vrg_source_busy_5$D_IN, m_vrg_source_busy_5$EN; - - // register m_vrg_source_busy_6 - reg m_vrg_source_busy_6; - wire m_vrg_source_busy_6$D_IN, m_vrg_source_busy_6$EN; - - // register m_vrg_source_busy_7 - reg m_vrg_source_busy_7; - wire m_vrg_source_busy_7$D_IN, m_vrg_source_busy_7$EN; - - // register m_vrg_source_busy_8 - reg m_vrg_source_busy_8; - wire m_vrg_source_busy_8$D_IN, m_vrg_source_busy_8$EN; - - // register m_vrg_source_busy_9 - reg m_vrg_source_busy_9; - wire m_vrg_source_busy_9$D_IN, m_vrg_source_busy_9$EN; - - // register m_vrg_source_ip_0 - reg m_vrg_source_ip_0; - wire m_vrg_source_ip_0$D_IN, m_vrg_source_ip_0$EN; - - // register m_vrg_source_ip_1 - reg m_vrg_source_ip_1; - wire m_vrg_source_ip_1$D_IN, m_vrg_source_ip_1$EN; - - // register m_vrg_source_ip_10 - reg m_vrg_source_ip_10; - wire m_vrg_source_ip_10$D_IN, m_vrg_source_ip_10$EN; - - // register m_vrg_source_ip_11 - reg m_vrg_source_ip_11; - wire m_vrg_source_ip_11$D_IN, m_vrg_source_ip_11$EN; - - // register m_vrg_source_ip_12 - reg m_vrg_source_ip_12; - wire m_vrg_source_ip_12$D_IN, m_vrg_source_ip_12$EN; - - // register m_vrg_source_ip_13 - reg m_vrg_source_ip_13; - wire m_vrg_source_ip_13$D_IN, m_vrg_source_ip_13$EN; - - // register m_vrg_source_ip_14 - reg m_vrg_source_ip_14; - wire m_vrg_source_ip_14$D_IN, m_vrg_source_ip_14$EN; - - // register m_vrg_source_ip_15 - reg m_vrg_source_ip_15; - wire m_vrg_source_ip_15$D_IN, m_vrg_source_ip_15$EN; - - // register m_vrg_source_ip_16 - reg m_vrg_source_ip_16; - wire m_vrg_source_ip_16$D_IN, m_vrg_source_ip_16$EN; - - // register m_vrg_source_ip_2 - reg m_vrg_source_ip_2; - wire m_vrg_source_ip_2$D_IN, m_vrg_source_ip_2$EN; - - // register m_vrg_source_ip_3 - reg m_vrg_source_ip_3; - wire m_vrg_source_ip_3$D_IN, m_vrg_source_ip_3$EN; - - // register m_vrg_source_ip_4 - reg m_vrg_source_ip_4; - wire m_vrg_source_ip_4$D_IN, m_vrg_source_ip_4$EN; - - // register m_vrg_source_ip_5 - reg m_vrg_source_ip_5; - wire m_vrg_source_ip_5$D_IN, m_vrg_source_ip_5$EN; - - // register m_vrg_source_ip_6 - reg m_vrg_source_ip_6; - wire m_vrg_source_ip_6$D_IN, m_vrg_source_ip_6$EN; - - // register m_vrg_source_ip_7 - reg m_vrg_source_ip_7; - wire m_vrg_source_ip_7$D_IN, m_vrg_source_ip_7$EN; - - // register m_vrg_source_ip_8 - reg m_vrg_source_ip_8; - wire m_vrg_source_ip_8$D_IN, m_vrg_source_ip_8$EN; - - // register m_vrg_source_ip_9 - reg m_vrg_source_ip_9; - wire m_vrg_source_ip_9$D_IN, m_vrg_source_ip_9$EN; - - // register m_vrg_source_prio_0 - reg [2 : 0] m_vrg_source_prio_0; - wire [2 : 0] m_vrg_source_prio_0$D_IN; - wire m_vrg_source_prio_0$EN; - - // register m_vrg_source_prio_1 - reg [2 : 0] m_vrg_source_prio_1; - wire [2 : 0] m_vrg_source_prio_1$D_IN; - wire m_vrg_source_prio_1$EN; - - // register m_vrg_source_prio_10 - reg [2 : 0] m_vrg_source_prio_10; - wire [2 : 0] m_vrg_source_prio_10$D_IN; - wire m_vrg_source_prio_10$EN; - - // register m_vrg_source_prio_11 - reg [2 : 0] m_vrg_source_prio_11; - wire [2 : 0] m_vrg_source_prio_11$D_IN; - wire m_vrg_source_prio_11$EN; - - // register m_vrg_source_prio_12 - reg [2 : 0] m_vrg_source_prio_12; - wire [2 : 0] m_vrg_source_prio_12$D_IN; - wire m_vrg_source_prio_12$EN; - - // register m_vrg_source_prio_13 - reg [2 : 0] m_vrg_source_prio_13; - wire [2 : 0] m_vrg_source_prio_13$D_IN; - wire m_vrg_source_prio_13$EN; - - // register m_vrg_source_prio_14 - reg [2 : 0] m_vrg_source_prio_14; - wire [2 : 0] m_vrg_source_prio_14$D_IN; - wire m_vrg_source_prio_14$EN; - - // register m_vrg_source_prio_15 - reg [2 : 0] m_vrg_source_prio_15; - wire [2 : 0] m_vrg_source_prio_15$D_IN; - wire m_vrg_source_prio_15$EN; - - // register m_vrg_source_prio_16 - reg [2 : 0] m_vrg_source_prio_16; - wire [2 : 0] m_vrg_source_prio_16$D_IN; - wire m_vrg_source_prio_16$EN; - - // register m_vrg_source_prio_2 - reg [2 : 0] m_vrg_source_prio_2; - wire [2 : 0] m_vrg_source_prio_2$D_IN; - wire m_vrg_source_prio_2$EN; - - // register m_vrg_source_prio_3 - reg [2 : 0] m_vrg_source_prio_3; - wire [2 : 0] m_vrg_source_prio_3$D_IN; - wire m_vrg_source_prio_3$EN; - - // register m_vrg_source_prio_4 - reg [2 : 0] m_vrg_source_prio_4; - wire [2 : 0] m_vrg_source_prio_4$D_IN; - wire m_vrg_source_prio_4$EN; - - // register m_vrg_source_prio_5 - reg [2 : 0] m_vrg_source_prio_5; - wire [2 : 0] m_vrg_source_prio_5$D_IN; - wire m_vrg_source_prio_5$EN; - - // register m_vrg_source_prio_6 - reg [2 : 0] m_vrg_source_prio_6; - wire [2 : 0] m_vrg_source_prio_6$D_IN; - wire m_vrg_source_prio_6$EN; - - // register m_vrg_source_prio_7 - reg [2 : 0] m_vrg_source_prio_7; - wire [2 : 0] m_vrg_source_prio_7$D_IN; - wire m_vrg_source_prio_7$EN; - - // register m_vrg_source_prio_8 - reg [2 : 0] m_vrg_source_prio_8; - wire [2 : 0] m_vrg_source_prio_8$D_IN; - wire m_vrg_source_prio_8$EN; - - // register m_vrg_source_prio_9 - reg [2 : 0] m_vrg_source_prio_9; - wire [2 : 0] m_vrg_source_prio_9$D_IN; - wire m_vrg_source_prio_9$EN; - - // register m_vrg_target_threshold_0 - reg [2 : 0] m_vrg_target_threshold_0; - wire [2 : 0] m_vrg_target_threshold_0$D_IN; - wire m_vrg_target_threshold_0$EN; - - // register m_vrg_target_threshold_1 - reg [2 : 0] m_vrg_target_threshold_1; - wire [2 : 0] m_vrg_target_threshold_1$D_IN; - wire m_vrg_target_threshold_1$EN; - - // register m_vvrg_ie_0_0 - reg m_vvrg_ie_0_0; - wire m_vvrg_ie_0_0$D_IN, m_vvrg_ie_0_0$EN; - - // register m_vvrg_ie_0_1 - reg m_vvrg_ie_0_1; - wire m_vvrg_ie_0_1$D_IN, m_vvrg_ie_0_1$EN; - - // register m_vvrg_ie_0_10 - reg m_vvrg_ie_0_10; - wire m_vvrg_ie_0_10$D_IN, m_vvrg_ie_0_10$EN; - - // register m_vvrg_ie_0_11 - reg m_vvrg_ie_0_11; - wire m_vvrg_ie_0_11$D_IN, m_vvrg_ie_0_11$EN; - - // register m_vvrg_ie_0_12 - reg m_vvrg_ie_0_12; - wire m_vvrg_ie_0_12$D_IN, m_vvrg_ie_0_12$EN; - - // register m_vvrg_ie_0_13 - reg m_vvrg_ie_0_13; - wire m_vvrg_ie_0_13$D_IN, m_vvrg_ie_0_13$EN; - - // register m_vvrg_ie_0_14 - reg m_vvrg_ie_0_14; - wire m_vvrg_ie_0_14$D_IN, m_vvrg_ie_0_14$EN; - - // register m_vvrg_ie_0_15 - reg m_vvrg_ie_0_15; - wire m_vvrg_ie_0_15$D_IN, m_vvrg_ie_0_15$EN; - - // register m_vvrg_ie_0_16 - reg m_vvrg_ie_0_16; - wire m_vvrg_ie_0_16$D_IN, m_vvrg_ie_0_16$EN; - - // register m_vvrg_ie_0_2 - reg m_vvrg_ie_0_2; - wire m_vvrg_ie_0_2$D_IN, m_vvrg_ie_0_2$EN; - - // register m_vvrg_ie_0_3 - reg m_vvrg_ie_0_3; - wire m_vvrg_ie_0_3$D_IN, m_vvrg_ie_0_3$EN; - - // register m_vvrg_ie_0_4 - reg m_vvrg_ie_0_4; - wire m_vvrg_ie_0_4$D_IN, m_vvrg_ie_0_4$EN; - - // register m_vvrg_ie_0_5 - reg m_vvrg_ie_0_5; - wire m_vvrg_ie_0_5$D_IN, m_vvrg_ie_0_5$EN; - - // register m_vvrg_ie_0_6 - reg m_vvrg_ie_0_6; - wire m_vvrg_ie_0_6$D_IN, m_vvrg_ie_0_6$EN; - - // register m_vvrg_ie_0_7 - reg m_vvrg_ie_0_7; - wire m_vvrg_ie_0_7$D_IN, m_vvrg_ie_0_7$EN; - - // register m_vvrg_ie_0_8 - reg m_vvrg_ie_0_8; - wire m_vvrg_ie_0_8$D_IN, m_vvrg_ie_0_8$EN; - - // register m_vvrg_ie_0_9 - reg m_vvrg_ie_0_9; - wire m_vvrg_ie_0_9$D_IN, m_vvrg_ie_0_9$EN; - - // register m_vvrg_ie_1_0 - reg m_vvrg_ie_1_0; - wire m_vvrg_ie_1_0$D_IN, m_vvrg_ie_1_0$EN; - - // register m_vvrg_ie_1_1 - reg m_vvrg_ie_1_1; - wire m_vvrg_ie_1_1$D_IN, m_vvrg_ie_1_1$EN; - - // register m_vvrg_ie_1_10 - reg m_vvrg_ie_1_10; - wire m_vvrg_ie_1_10$D_IN, m_vvrg_ie_1_10$EN; - - // register m_vvrg_ie_1_11 - reg m_vvrg_ie_1_11; - wire m_vvrg_ie_1_11$D_IN, m_vvrg_ie_1_11$EN; - - // register m_vvrg_ie_1_12 - reg m_vvrg_ie_1_12; - wire m_vvrg_ie_1_12$D_IN, m_vvrg_ie_1_12$EN; - - // register m_vvrg_ie_1_13 - reg m_vvrg_ie_1_13; - wire m_vvrg_ie_1_13$D_IN, m_vvrg_ie_1_13$EN; - - // register m_vvrg_ie_1_14 - reg m_vvrg_ie_1_14; - wire m_vvrg_ie_1_14$D_IN, m_vvrg_ie_1_14$EN; - - // register m_vvrg_ie_1_15 - reg m_vvrg_ie_1_15; - wire m_vvrg_ie_1_15$D_IN, m_vvrg_ie_1_15$EN; - - // register m_vvrg_ie_1_16 - reg m_vvrg_ie_1_16; - wire m_vvrg_ie_1_16$D_IN, m_vvrg_ie_1_16$EN; - - // register m_vvrg_ie_1_2 - reg m_vvrg_ie_1_2; - wire m_vvrg_ie_1_2$D_IN, m_vvrg_ie_1_2$EN; - - // register m_vvrg_ie_1_3 - reg m_vvrg_ie_1_3; - wire m_vvrg_ie_1_3$D_IN, m_vvrg_ie_1_3$EN; - - // register m_vvrg_ie_1_4 - reg m_vvrg_ie_1_4; - wire m_vvrg_ie_1_4$D_IN, m_vvrg_ie_1_4$EN; - - // register m_vvrg_ie_1_5 - reg m_vvrg_ie_1_5; - wire m_vvrg_ie_1_5$D_IN, m_vvrg_ie_1_5$EN; - - // register m_vvrg_ie_1_6 - reg m_vvrg_ie_1_6; - wire m_vvrg_ie_1_6$D_IN, m_vvrg_ie_1_6$EN; - - // register m_vvrg_ie_1_7 - reg m_vvrg_ie_1_7; - wire m_vvrg_ie_1_7$D_IN, m_vvrg_ie_1_7$EN; - - // register m_vvrg_ie_1_8 - reg m_vvrg_ie_1_8; - wire m_vvrg_ie_1_8$D_IN, m_vvrg_ie_1_8$EN; - - // register m_vvrg_ie_1_9 - reg m_vvrg_ie_1_9; - wire m_vvrg_ie_1_9$D_IN, m_vvrg_ie_1_9$EN; - - // ports of submodule m_f_reset_reqs - wire m_f_reset_reqs$CLR, - m_f_reset_reqs$DEQ, - m_f_reset_reqs$EMPTY_N, - m_f_reset_reqs$ENQ, - m_f_reset_reqs$FULL_N; - - // ports of submodule m_f_reset_rsps - wire m_f_reset_rsps$CLR, - m_f_reset_rsps$DEQ, - m_f_reset_rsps$EMPTY_N, - m_f_reset_rsps$ENQ, - m_f_reset_rsps$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_addr - wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT; - wire m_slave_xactor_f_rd_addr$CLR, - m_slave_xactor_f_rd_addr$DEQ, - m_slave_xactor_f_rd_addr$EMPTY_N, - m_slave_xactor_f_rd_addr$ENQ, - m_slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_data - wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT; - wire m_slave_xactor_f_rd_data$CLR, - m_slave_xactor_f_rd_data$DEQ, - m_slave_xactor_f_rd_data$EMPTY_N, - m_slave_xactor_f_rd_data$ENQ, - m_slave_xactor_f_rd_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_addr - wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT; - wire m_slave_xactor_f_wr_addr$CLR, - m_slave_xactor_f_wr_addr$DEQ, - m_slave_xactor_f_wr_addr$EMPTY_N, - m_slave_xactor_f_wr_addr$ENQ, - m_slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_data - wire [72 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; - wire m_slave_xactor_f_wr_data$CLR, - m_slave_xactor_f_wr_data$DEQ, - m_slave_xactor_f_wr_data$EMPTY_N, - m_slave_xactor_f_wr_data$ENQ, - m_slave_xactor_f_wr_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_resp - wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT; - wire m_slave_xactor_f_wr_resp$CLR, - m_slave_xactor_f_wr_resp$DEQ, - m_slave_xactor_f_wr_resp$EMPTY_N, - m_slave_xactor_f_wr_resp$ENQ, - m_slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_process_rd_req, - CAN_FIRE_RL_m_rl_process_wr_req, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_verbosity, - CAN_FIRE_show_PLIC_state, - CAN_FIRE_v_sources_0_m_interrupt_req, - CAN_FIRE_v_sources_10_m_interrupt_req, - CAN_FIRE_v_sources_11_m_interrupt_req, - CAN_FIRE_v_sources_12_m_interrupt_req, - CAN_FIRE_v_sources_13_m_interrupt_req, - CAN_FIRE_v_sources_14_m_interrupt_req, - CAN_FIRE_v_sources_15_m_interrupt_req, - CAN_FIRE_v_sources_1_m_interrupt_req, - CAN_FIRE_v_sources_2_m_interrupt_req, - CAN_FIRE_v_sources_3_m_interrupt_req, - CAN_FIRE_v_sources_4_m_interrupt_req, - CAN_FIRE_v_sources_5_m_interrupt_req, - CAN_FIRE_v_sources_6_m_interrupt_req, - CAN_FIRE_v_sources_7_m_interrupt_req, - CAN_FIRE_v_sources_8_m_interrupt_req, - CAN_FIRE_v_sources_9_m_interrupt_req, - WILL_FIRE_RL_m_rl_process_rd_req, - WILL_FIRE_RL_m_rl_process_wr_req, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_verbosity, - WILL_FIRE_show_PLIC_state, - WILL_FIRE_v_sources_0_m_interrupt_req, - WILL_FIRE_v_sources_10_m_interrupt_req, - WILL_FIRE_v_sources_11_m_interrupt_req, - WILL_FIRE_v_sources_12_m_interrupt_req, - WILL_FIRE_v_sources_13_m_interrupt_req, - WILL_FIRE_v_sources_14_m_interrupt_req, - WILL_FIRE_v_sources_15_m_interrupt_req, - WILL_FIRE_v_sources_1_m_interrupt_req, - WILL_FIRE_v_sources_2_m_interrupt_req, - WILL_FIRE_v_sources_3_m_interrupt_req, - WILL_FIRE_v_sources_4_m_interrupt_req, - WILL_FIRE_v_sources_5_m_interrupt_req, - WILL_FIRE_v_sources_6_m_interrupt_req, - WILL_FIRE_v_sources_7_m_interrupt_req, - WILL_FIRE_v_sources_8_m_interrupt_req, - WILL_FIRE_v_sources_9_m_interrupt_req; - - // inputs to muxes for submodule ports - wire MUX_m_vrg_servicing_source_0$write_1__SEL_1, - MUX_m_vrg_servicing_source_1$write_1__SEL_1, - MUX_m_vrg_source_busy_0$write_1__SEL_2, - MUX_m_vrg_source_busy_1$write_1__SEL_1, - MUX_m_vrg_source_busy_1$write_1__SEL_2, - MUX_m_vrg_source_busy_10$write_1__SEL_1, - MUX_m_vrg_source_busy_10$write_1__SEL_2, - MUX_m_vrg_source_busy_11$write_1__SEL_1, - MUX_m_vrg_source_busy_11$write_1__SEL_2, - MUX_m_vrg_source_busy_12$write_1__SEL_1, - MUX_m_vrg_source_busy_12$write_1__SEL_2, - MUX_m_vrg_source_busy_13$write_1__SEL_1, - MUX_m_vrg_source_busy_13$write_1__SEL_2, - MUX_m_vrg_source_busy_14$write_1__SEL_1, - MUX_m_vrg_source_busy_14$write_1__SEL_2, - MUX_m_vrg_source_busy_15$write_1__SEL_1, - MUX_m_vrg_source_busy_15$write_1__SEL_2, - MUX_m_vrg_source_busy_16$write_1__SEL_1, - MUX_m_vrg_source_busy_16$write_1__SEL_2, - MUX_m_vrg_source_busy_2$write_1__SEL_1, - MUX_m_vrg_source_busy_2$write_1__SEL_2, - MUX_m_vrg_source_busy_3$write_1__SEL_1, - MUX_m_vrg_source_busy_3$write_1__SEL_2, - MUX_m_vrg_source_busy_4$write_1__SEL_1, - MUX_m_vrg_source_busy_4$write_1__SEL_2, - MUX_m_vrg_source_busy_5$write_1__SEL_1, - MUX_m_vrg_source_busy_5$write_1__SEL_2, - MUX_m_vrg_source_busy_6$write_1__SEL_1, - MUX_m_vrg_source_busy_6$write_1__SEL_2, - MUX_m_vrg_source_busy_7$write_1__SEL_1, - MUX_m_vrg_source_busy_7$write_1__SEL_2, - MUX_m_vrg_source_busy_8$write_1__SEL_1, - MUX_m_vrg_source_busy_8$write_1__SEL_2, - MUX_m_vrg_source_busy_9$write_1__SEL_1, - MUX_m_vrg_source_busy_9$write_1__SEL_2, - MUX_m_vrg_source_prio_0$write_1__SEL_1, - MUX_m_vrg_source_prio_1$write_1__SEL_1, - MUX_m_vrg_source_prio_10$write_1__SEL_1, - MUX_m_vrg_source_prio_11$write_1__SEL_1, - MUX_m_vrg_source_prio_12$write_1__SEL_1, - MUX_m_vrg_source_prio_13$write_1__SEL_1, - MUX_m_vrg_source_prio_14$write_1__SEL_1, - MUX_m_vrg_source_prio_15$write_1__SEL_1, - MUX_m_vrg_source_prio_16$write_1__SEL_1, - MUX_m_vrg_source_prio_2$write_1__SEL_1, - MUX_m_vrg_source_prio_3$write_1__SEL_1, - MUX_m_vrg_source_prio_4$write_1__SEL_1, - MUX_m_vrg_source_prio_5$write_1__SEL_1, - MUX_m_vrg_source_prio_6$write_1__SEL_1, - MUX_m_vrg_source_prio_7$write_1__SEL_1, - MUX_m_vrg_source_prio_8$write_1__SEL_1, - MUX_m_vrg_source_prio_9$write_1__SEL_1, - MUX_m_vrg_target_threshold_0$write_1__SEL_1, - MUX_m_vrg_target_threshold_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__VAL_1, - MUX_m_vvrg_ie_0_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_1$write_1__VAL_1, - MUX_m_vvrg_ie_0_10$write_1__SEL_1, - MUX_m_vvrg_ie_0_10$write_1__VAL_1, - MUX_m_vvrg_ie_0_11$write_1__SEL_1, - MUX_m_vvrg_ie_0_11$write_1__VAL_1, - MUX_m_vvrg_ie_0_12$write_1__SEL_1, - MUX_m_vvrg_ie_0_12$write_1__VAL_1, - MUX_m_vvrg_ie_0_13$write_1__SEL_1, - MUX_m_vvrg_ie_0_13$write_1__VAL_1, - MUX_m_vvrg_ie_0_14$write_1__SEL_1, - MUX_m_vvrg_ie_0_14$write_1__VAL_1, - MUX_m_vvrg_ie_0_15$write_1__SEL_1, - MUX_m_vvrg_ie_0_15$write_1__VAL_1, - MUX_m_vvrg_ie_0_16$write_1__SEL_1, - MUX_m_vvrg_ie_0_16$write_1__VAL_1, - MUX_m_vvrg_ie_0_2$write_1__SEL_1, - MUX_m_vvrg_ie_0_2$write_1__VAL_1, - MUX_m_vvrg_ie_0_3$write_1__SEL_1, - MUX_m_vvrg_ie_0_3$write_1__VAL_1, - MUX_m_vvrg_ie_0_4$write_1__SEL_1, - MUX_m_vvrg_ie_0_4$write_1__VAL_1, - MUX_m_vvrg_ie_0_5$write_1__SEL_1, - MUX_m_vvrg_ie_0_5$write_1__VAL_1, - MUX_m_vvrg_ie_0_6$write_1__SEL_1, - MUX_m_vvrg_ie_0_6$write_1__VAL_1, - MUX_m_vvrg_ie_0_7$write_1__SEL_1, - MUX_m_vvrg_ie_0_7$write_1__VAL_1, - MUX_m_vvrg_ie_0_8$write_1__SEL_1, - MUX_m_vvrg_ie_0_8$write_1__VAL_1, - MUX_m_vvrg_ie_0_9$write_1__SEL_1, - MUX_m_vvrg_ie_0_9$write_1__VAL_1, - MUX_m_vvrg_ie_1_0$write_1__SEL_1, - MUX_m_vvrg_ie_1_0$write_1__VAL_1, - MUX_m_vvrg_ie_1_1$write_1__SEL_1, - MUX_m_vvrg_ie_1_1$write_1__VAL_1, - MUX_m_vvrg_ie_1_10$write_1__SEL_1, - MUX_m_vvrg_ie_1_10$write_1__VAL_1, - MUX_m_vvrg_ie_1_11$write_1__SEL_1, - MUX_m_vvrg_ie_1_11$write_1__VAL_1, - MUX_m_vvrg_ie_1_12$write_1__SEL_1, - MUX_m_vvrg_ie_1_12$write_1__VAL_1, - MUX_m_vvrg_ie_1_13$write_1__SEL_1, - MUX_m_vvrg_ie_1_13$write_1__VAL_1, - MUX_m_vvrg_ie_1_14$write_1__SEL_1, - MUX_m_vvrg_ie_1_14$write_1__VAL_1, - MUX_m_vvrg_ie_1_15$write_1__SEL_1, - MUX_m_vvrg_ie_1_15$write_1__VAL_1, - MUX_m_vvrg_ie_1_16$write_1__SEL_1, - MUX_m_vvrg_ie_1_16$write_1__VAL_1, - MUX_m_vvrg_ie_1_2$write_1__SEL_1, - MUX_m_vvrg_ie_1_2$write_1__VAL_1, - MUX_m_vvrg_ie_1_3$write_1__SEL_1, - MUX_m_vvrg_ie_1_3$write_1__VAL_1, - MUX_m_vvrg_ie_1_4$write_1__SEL_1, - MUX_m_vvrg_ie_1_4$write_1__VAL_1, - MUX_m_vvrg_ie_1_5$write_1__SEL_1, - MUX_m_vvrg_ie_1_5$write_1__VAL_1, - MUX_m_vvrg_ie_1_6$write_1__SEL_1, - MUX_m_vvrg_ie_1_6$write_1__VAL_1, - MUX_m_vvrg_ie_1_7$write_1__SEL_1, - MUX_m_vvrg_ie_1_7$write_1__VAL_1, - MUX_m_vvrg_ie_1_8$write_1__SEL_1, - MUX_m_vvrg_ie_1_8$write_1__VAL_1, - MUX_m_vvrg_ie_1_9$write_1__SEL_1, - MUX_m_vvrg_ie_1_9$write_1__VAL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h75661; - reg [31 : 0] v__h75859; - reg [31 : 0] v__h76057; - reg [31 : 0] v__h76255; - reg [31 : 0] v__h76453; - reg [31 : 0] v__h76651; - reg [31 : 0] v__h76849; - reg [31 : 0] v__h77047; - reg [31 : 0] v__h77245; - reg [31 : 0] v__h77443; - reg [31 : 0] v__h77641; - reg [31 : 0] v__h77839; - reg [31 : 0] v__h78037; - reg [31 : 0] v__h78235; - reg [31 : 0] v__h78433; - reg [31 : 0] v__h78631; - reg [31 : 0] v__h6144; - reg [31 : 0] v__h13080; - reg [31 : 0] v__h13265; - reg [31 : 0] v__h13463; - reg [31 : 0] v__h13713; - reg [31 : 0] v__h18186; - reg [31 : 0] v__h23802; - reg [31 : 0] v__h25975; - reg [31 : 0] v__h24056; - reg [31 : 0] v__h26250; - reg [31 : 0] v__h26463; - reg [31 : 0] v__h26737; - reg [31 : 0] v__h26961; - reg [31 : 0] v__h27856; - reg [31 : 0] v__h28039; - reg [31 : 0] v__h67021; - reg [31 : 0] v__h67309; - reg [31 : 0] v__h67838; - reg [31 : 0] v__h67924; - reg [31 : 0] v__h68123; - reg [31 : 0] v__h68342; - reg [31 : 0] v__h74677; - reg [31 : 0] v__h74787; - reg [31 : 0] v__h74900; - reg [31 : 0] v__h6138; - reg [31 : 0] v__h13074; - reg [31 : 0] v__h13259; - reg [31 : 0] v__h13457; - reg [31 : 0] v__h13707; - reg [31 : 0] v__h18180; - reg [31 : 0] v__h23796; - reg [31 : 0] v__h24050; - reg [31 : 0] v__h25969; - reg [31 : 0] v__h26244; - reg [31 : 0] v__h26457; - reg [31 : 0] v__h26731; - reg [31 : 0] v__h26955; - reg [31 : 0] v__h27850; - reg [31 : 0] v__h28033; - reg [31 : 0] v__h67015; - reg [31 : 0] v__h67303; - reg [31 : 0] v__h67832; - reg [31 : 0] v__h67918; - reg [31 : 0] v__h68117; - reg [31 : 0] v__h68336; - reg [31 : 0] v__h74671; - reg [31 : 0] v__h74781; - reg [31 : 0] v__h74894; - reg [31 : 0] v__h75655; - reg [31 : 0] v__h75853; - reg [31 : 0] v__h76051; - reg [31 : 0] v__h76249; - reg [31 : 0] v__h76447; - reg [31 : 0] v__h76645; - reg [31 : 0] v__h76843; - reg [31 : 0] v__h77041; - reg [31 : 0] v__h77239; - reg [31 : 0] v__h77437; - reg [31 : 0] v__h77635; - reg [31 : 0] v__h77833; - reg [31 : 0] v__h78031; - reg [31 : 0] v__h78229; - reg [31 : 0] v__h78427; - reg [31 : 0] v__h78625; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] y_avValue_fst__h26148; - reg [4 : 0] x__h24011, x__h67478; - reg [2 : 0] x__h13493, x__h23832; - reg [1 : 0] v__h67098, y_avValue_snd__h26149; - reg CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - wire [63 : 0] addr_offset__h13216, - addr_offset__h26922, - rdata___1__h26404, - rdata__h26202, - v__h13422, - v__h13671, - v__h18144, - v__h23761, - v__h25455, - v__h25474, - x__h26361, - y_avValue_fst__h26094, - y_avValue_fst__h26115, - y_avValue_fst__h26127, - y_avValue_fst__h26143, - y_avValue_fst__h26159, - y_avValue_fst__h26164, - y_avValue_fst__h26175, - y_avValue_fst__h26180, - y_avValue_fst__h26194; - wire [31 : 0] v_ie__h18147, - v_ip__h13674, - wdata32__h26923, - x__h23673, - x__h67101; - wire [9 : 0] source_id__h15665, - source_id__h15772, - source_id__h15845, - source_id__h15918, - source_id__h15991, - source_id__h16064, - source_id__h16137, - source_id__h16210, - source_id__h16283, - source_id__h16356, - source_id__h16429, - source_id__h16502, - source_id__h16575, - source_id__h16648, - source_id__h16721, - source_id__h16794, - source_id__h16867, - source_id__h16940, - source_id__h17013, - source_id__h17086, - source_id__h17159, - source_id__h17232, - source_id__h17305, - source_id__h17378, - source_id__h17451, - source_id__h17524, - source_id__h17597, - source_id__h17670, - source_id__h17743, - source_id__h17816, - source_id__h17889, - source_id__h20137, - source_id__h20313, - source_id__h20421, - source_id__h20529, - source_id__h20637, - source_id__h20745, - source_id__h20853, - source_id__h20961, - source_id__h21069, - source_id__h21177, - source_id__h21285, - source_id__h21393, - source_id__h21501, - source_id__h21609, - source_id__h21717, - source_id__h21825, - source_id__h21933, - source_id__h22041, - source_id__h22149, - source_id__h22257, - source_id__h22365, - source_id__h22473, - source_id__h22581, - source_id__h22689, - source_id__h22797, - source_id__h22905, - source_id__h23013, - source_id__h23121, - source_id__h23229, - source_id__h23337, - source_id__h23445, - source_id__h29466, - source_id__h30676, - source_id__h31886, - source_id__h33096, - source_id__h34306, - source_id__h35516, - source_id__h36726, - source_id__h37936, - source_id__h39146, - source_id__h40356, - source_id__h41566, - source_id__h42776, - source_id__h43986, - source_id__h45196, - source_id__h46406, - source_id__h47616, - source_id__h48826, - source_id__h50036, - source_id__h51246, - source_id__h52456, - source_id__h53666, - source_id__h54876, - source_id__h56086, - source_id__h57296, - source_id__h58506, - source_id__h59716, - source_id__h60926, - source_id__h62136, - source_id__h63346, - source_id__h64556, - source_id__h65766, - source_id__h67427, - source_id_base__h13630, - source_id_base__h28139; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71300, - b__h73305, - max_id__h23959; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71299, - a__h73304; - wire [1 : 0] rresp__h26203, - v__h26927, - v__h27085, - v__h27098, - v__h27933, - v__h27952, - v__h28116, - v__h28135, - v__h67135, - v__h67423, - v__h67467, - y_avValue_snd__h26095, - y_avValue_snd__h26116, - y_avValue_snd__h26128, - y_avValue_snd__h26144, - y_avValue_snd__h26160, - y_avValue_snd__h26165, - y_avValue_snd__h26176, - y_avValue_snd__h26181, - y_avValue_snd__h26195; - wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990, - NOT_m_cfg_verbosity_read_ULE_1_5___d16, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981, - NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311, - NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319, - NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327, - NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335, - NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343, - NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351, - NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359, - NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240, - NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247, - NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255, - NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263, - NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271, - NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279, - NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287, - NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295, - NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303, - _dfoo1, - _dfoo10, - _dfoo100, - _dfoo1000, - _dfoo1001, - _dfoo1002, - _dfoo1003, - _dfoo1004, - _dfoo1005, - _dfoo1006, - _dfoo1007, - _dfoo1008, - _dfoo1009, - _dfoo1010, - _dfoo1011, - _dfoo1012, - _dfoo1013, - _dfoo1014, - _dfoo1015, - _dfoo1016, - _dfoo1017, - _dfoo1018, - _dfoo1019, - _dfoo102, - _dfoo1020, - _dfoo1022, - _dfoo1024, - _dfoo1026, - _dfoo1028, - _dfoo1030, - _dfoo1032, - _dfoo1034, - _dfoo1036, - _dfoo1038, - _dfoo104, - _dfoo1040, - _dfoo1042, - _dfoo1044, - _dfoo1046, - _dfoo1048, - _dfoo1050, - _dfoo1052, - _dfoo1054, - _dfoo1056, - _dfoo1058, - _dfoo106, - _dfoo1060, - _dfoo1062, - _dfoo1064, - _dfoo1066, - _dfoo1068, - _dfoo1070, - _dfoo1072, - _dfoo1074, - _dfoo1076, - _dfoo1078, - _dfoo108, - _dfoo1080, - _dfoo1082, - _dfoo1084, - _dfoo1086, - _dfoo1088, - _dfoo1089, - _dfoo1090, - _dfoo1091, - _dfoo1092, - _dfoo1093, - _dfoo1094, - _dfoo1095, - _dfoo1096, - _dfoo1097, - _dfoo1098, - _dfoo1099, - _dfoo11, - _dfoo110, - _dfoo1100, - _dfoo1101, - _dfoo1102, - _dfoo1103, - _dfoo1104, - _dfoo1105, - _dfoo1106, - _dfoo1107, - _dfoo1108, - _dfoo1109, - _dfoo1110, - _dfoo1111, - _dfoo1112, - _dfoo1113, - _dfoo1114, - _dfoo1115, - _dfoo1116, - _dfoo1117, - _dfoo1118, - _dfoo1119, - _dfoo112, - _dfoo1120, - _dfoo1121, - _dfoo1122, - _dfoo1123, - _dfoo1124, - _dfoo1125, - _dfoo1126, - _dfoo1127, - _dfoo1128, - _dfoo1129, - _dfoo1130, - _dfoo1131, - _dfoo1132, - _dfoo1133, - _dfoo1134, - _dfoo1135, - _dfoo1136, - _dfoo1137, - _dfoo1138, - _dfoo1139, - _dfoo114, - _dfoo1140, - _dfoo1141, - _dfoo1142, - _dfoo1143, - _dfoo1144, - _dfoo1145, - _dfoo1146, - _dfoo1147, - _dfoo1148, - _dfoo1149, - _dfoo1150, - _dfoo1151, - _dfoo1152, - _dfoo1153, - _dfoo1154, - _dfoo1155, - _dfoo1156, - _dfoo1158, - _dfoo116, - _dfoo1160, - _dfoo1162, - _dfoo1164, - _dfoo1166, - _dfoo1168, - _dfoo1170, - _dfoo1172, - _dfoo1174, - _dfoo1176, - _dfoo1178, - _dfoo118, - _dfoo1180, - _dfoo1182, - _dfoo1184, - _dfoo1186, - _dfoo1188, - _dfoo1190, - _dfoo1192, - _dfoo1194, - _dfoo1196, - _dfoo1198, - _dfoo12, - _dfoo120, - _dfoo1200, - _dfoo1202, - _dfoo1204, - _dfoo1206, - _dfoo1208, - _dfoo1210, - _dfoo1212, - _dfoo1214, - _dfoo1216, - _dfoo1218, - _dfoo122, - _dfoo1220, - _dfoo1222, - _dfoo1224, - _dfoo1225, - _dfoo1226, - _dfoo1227, - _dfoo1228, - _dfoo1229, - _dfoo1230, - _dfoo1231, - _dfoo1232, - _dfoo1233, - _dfoo1234, - _dfoo1235, - _dfoo1236, - _dfoo1237, - _dfoo1238, - _dfoo1239, - _dfoo124, - _dfoo1240, - _dfoo1241, - _dfoo1242, - _dfoo1243, - _dfoo1244, - _dfoo1245, - _dfoo1246, - _dfoo1247, - _dfoo1248, - _dfoo1249, - _dfoo1250, - _dfoo1251, - _dfoo1252, - _dfoo1253, - _dfoo1254, - _dfoo1255, - _dfoo1256, - _dfoo1257, - _dfoo1258, - _dfoo1259, - _dfoo126, - _dfoo1260, - _dfoo1261, - _dfoo1262, - _dfoo1263, - _dfoo1264, - _dfoo1265, - _dfoo1266, - _dfoo1267, - _dfoo1268, - _dfoo1269, - _dfoo1270, - _dfoo1271, - _dfoo1272, - _dfoo1273, - _dfoo1274, - _dfoo1275, - _dfoo1276, - _dfoo1277, - _dfoo1278, - _dfoo1279, - _dfoo128, - _dfoo1280, - _dfoo1281, - _dfoo1282, - _dfoo1283, - _dfoo1284, - _dfoo1285, - _dfoo1286, - _dfoo1287, - _dfoo1288, - _dfoo1289, - _dfoo1290, - _dfoo1291, - _dfoo1292, - _dfoo1294, - _dfoo1296, - _dfoo1298, - _dfoo13, - _dfoo130, - _dfoo1300, - _dfoo1302, - _dfoo1304, - _dfoo1306, - _dfoo1308, - _dfoo1310, - _dfoo1312, - _dfoo1314, - _dfoo1316, - _dfoo1318, - _dfoo132, - _dfoo1320, - _dfoo1322, - _dfoo1324, - _dfoo1326, - _dfoo1328, - _dfoo1330, - _dfoo1332, - _dfoo1334, - _dfoo1336, - _dfoo1338, - _dfoo134, - _dfoo1340, - _dfoo1342, - _dfoo1344, - _dfoo1346, - _dfoo1348, - _dfoo1350, - _dfoo1352, - _dfoo1354, - _dfoo1356, - _dfoo1358, - _dfoo136, - _dfoo1360, - _dfoo1361, - _dfoo1362, - _dfoo1363, - _dfoo1364, - _dfoo1365, - _dfoo1366, - _dfoo1367, - _dfoo1368, - _dfoo1369, - _dfoo137, - _dfoo1370, - _dfoo1371, - _dfoo1372, - _dfoo1373, - _dfoo1374, - _dfoo1375, - _dfoo1376, - _dfoo1377, - _dfoo1378, - _dfoo1379, - _dfoo138, - _dfoo1380, - _dfoo1381, - _dfoo1382, - _dfoo1383, - _dfoo1384, - _dfoo1385, - _dfoo1386, - _dfoo1387, - _dfoo1388, - _dfoo1389, - _dfoo139, - _dfoo1390, - _dfoo1391, - _dfoo1392, - _dfoo1393, - _dfoo1394, - _dfoo1395, - _dfoo1396, - _dfoo1397, - _dfoo1398, - _dfoo1399, - _dfoo14, - _dfoo140, - _dfoo1400, - _dfoo1401, - _dfoo1402, - _dfoo1403, - _dfoo1404, - _dfoo1405, - _dfoo1406, - _dfoo1407, - _dfoo1408, - _dfoo1409, - _dfoo141, - _dfoo1410, - _dfoo1411, - _dfoo1412, - _dfoo1413, - _dfoo1414, - _dfoo1415, - _dfoo1416, - _dfoo1417, - _dfoo1418, - _dfoo1419, - _dfoo142, - _dfoo1420, - _dfoo1421, - _dfoo1422, - _dfoo1423, - _dfoo1424, - _dfoo1425, - _dfoo1426, - _dfoo1427, - _dfoo1428, - _dfoo143, - _dfoo1430, - _dfoo1432, - _dfoo1434, - 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m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, - m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method show_PLIC_state - assign RDY_show_PLIC_state = 1'd1 ; - assign CAN_FIRE_show_PLIC_state = 1'd1 ; - assign WILL_FIRE_show_PLIC_state = EN_show_PLIC_state ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // action method v_sources_0_m_interrupt_req - assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - - // action method v_sources_1_m_interrupt_req - assign CAN_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - - // action method v_sources_2_m_interrupt_req - assign CAN_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - - // action method v_sources_3_m_interrupt_req - assign CAN_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - - // action method v_sources_4_m_interrupt_req - assign CAN_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - - // action method v_sources_5_m_interrupt_req - assign CAN_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - - // action method v_sources_6_m_interrupt_req - assign CAN_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - - // action method v_sources_7_m_interrupt_req - assign CAN_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - - // action method v_sources_8_m_interrupt_req - assign CAN_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - - // action method v_sources_9_m_interrupt_req - assign CAN_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - - // action method v_sources_10_m_interrupt_req - assign CAN_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - - // action method v_sources_11_m_interrupt_req - assign CAN_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - - // action method v_sources_12_m_interrupt_req - assign CAN_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - - // action method v_sources_13_m_interrupt_req - assign CAN_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - - // action method v_sources_14_m_interrupt_req - assign CAN_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - - // action method v_sources_15_m_interrupt_req - assign CAN_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - - // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71299 > m_vrg_target_threshold_0 ; - - // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73304 > m_vrg_target_threshold_1 ; - - // submodule m_f_reset_reqs - FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_reqs$ENQ), - .DEQ(m_f_reset_reqs$DEQ), - .CLR(m_f_reset_reqs$CLR), - .FULL_N(m_f_reset_reqs$FULL_N), - .EMPTY_N(m_f_reset_reqs$EMPTY_N)); - - // submodule m_f_reset_rsps - FIFO20 #(.guarded(32'd1)) m_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_rsps$ENQ), - .DEQ(m_f_reset_rsps$DEQ), - .CLR(m_f_reset_rsps$CLR), - .FULL_N(m_f_reset_rsps$FULL_N), - .EMPTY_N(m_f_reset_rsps$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_addr$D_IN), - .ENQ(m_slave_xactor_f_rd_addr$ENQ), - .DEQ(m_slave_xactor_f_rd_addr$DEQ), - .CLR(m_slave_xactor_f_rd_addr$CLR), - .D_OUT(m_slave_xactor_f_rd_addr$D_OUT), - .FULL_N(m_slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_data$D_IN), - .ENQ(m_slave_xactor_f_rd_data$ENQ), - .DEQ(m_slave_xactor_f_rd_data$DEQ), - .CLR(m_slave_xactor_f_rd_data$CLR), - .D_OUT(m_slave_xactor_f_rd_data$D_OUT), - .FULL_N(m_slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_addr$D_IN), - .ENQ(m_slave_xactor_f_wr_addr$ENQ), - .DEQ(m_slave_xactor_f_wr_addr$DEQ), - .CLR(m_slave_xactor_f_wr_addr$CLR), - .D_OUT(m_slave_xactor_f_wr_addr$D_OUT), - .FULL_N(m_slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_data$D_IN), - .ENQ(m_slave_xactor_f_wr_data$ENQ), - .DEQ(m_slave_xactor_f_wr_data$DEQ), - .CLR(m_slave_xactor_f_wr_data$CLR), - .D_OUT(m_slave_xactor_f_wr_data$D_OUT), - .FULL_N(m_slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_resp$D_IN), - .ENQ(m_slave_xactor_f_wr_resp$ENQ), - .DEQ(m_slave_xactor_f_wr_resp$DEQ), - .CLR(m_slave_xactor_f_wr_resp$CLR), - .D_OUT(m_slave_xactor_f_wr_resp$D_OUT), - .FULL_N(m_slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = - m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - - // rule RL_m_rl_process_rd_req - assign CAN_FIRE_RL_m_rl_process_rd_req = - m_slave_xactor_f_rd_addr$EMPTY_N && - m_slave_xactor_f_rd_data$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - - // rule RL_m_rl_process_wr_req - assign CAN_FIRE_RL_m_rl_process_wr_req = - m_slave_xactor_f_wr_addr$EMPTY_N && - m_slave_xactor_f_wr_data$EMPTY_N && - m_slave_xactor_f_wr_resp$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_wr_req = - CAN_FIRE_RL_m_rl_process_wr_req && - !WILL_FIRE_RL_m_rl_process_rd_req ; - - // inputs to muxes for submodule ports - assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; - assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26922[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 ; - assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 ; - assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 ; - assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 ; - assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 ; - assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 ; - assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 ; - assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 ; - assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 ; - assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 ; - assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 ; - assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 ; - assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 ; - assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 ; - assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 ; - assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 ; - assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 ; - assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 ; - assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 ; - assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; - assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ; - assign MUX_m_vvrg_ie_0_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ; - assign MUX_m_vvrg_ie_0_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ; - assign MUX_m_vvrg_ie_0_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ; - assign MUX_m_vvrg_ie_0_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ; - assign MUX_m_vvrg_ie_0_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ; - assign MUX_m_vvrg_ie_0_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ; - assign MUX_m_vvrg_ie_0_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ; - assign MUX_m_vvrg_ie_0_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ; - assign MUX_m_vvrg_ie_0_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ; - assign MUX_m_vvrg_ie_0_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ; - assign MUX_m_vvrg_ie_0_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ; - assign MUX_m_vvrg_ie_0_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ; - assign MUX_m_vvrg_ie_0_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ; - assign MUX_m_vvrg_ie_0_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ; - assign MUX_m_vvrg_ie_0_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ; - assign MUX_m_vvrg_ie_1_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ; - assign MUX_m_vvrg_ie_1_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ; - assign MUX_m_vvrg_ie_1_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ; - assign MUX_m_vvrg_ie_1_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ; - assign MUX_m_vvrg_ie_1_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ; - assign MUX_m_vvrg_ie_1_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ; - assign MUX_m_vvrg_ie_1_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ; - assign MUX_m_vvrg_ie_1_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ; - assign MUX_m_vvrg_ie_1_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ; - assign MUX_m_vvrg_ie_1_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ; - assign MUX_m_vvrg_ie_1_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ; - assign MUX_m_vvrg_ie_1_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ; - assign MUX_m_vvrg_ie_1_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ; - assign MUX_m_vvrg_ie_1_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ; - assign MUX_m_vvrg_ie_1_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ; - assign MUX_m_vvrg_ie_1_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ; - assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; - assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28139 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2040 ; - assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28139 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2038 ; - assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28139 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2020 ; - assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28139 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2018 ; - assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28139 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2016 ; - assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28139 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2014 ; - assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28139 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2012 ; - assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28139 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2010 ; - assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28139 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2008 ; - assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28139 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2036 ; - assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28139 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2034 ; - assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28139 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2032 ; - assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28139 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2030 ; - assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28139 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2028 ; - assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28139 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2026 ; - assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28139 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2024 ; - assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28139 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26923[0] : - _dfoo2022 ; - assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28139 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo2006 ; - assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28139 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo2004 ; - assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28139 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1986 ; - assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28139 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1984 ; - assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28139 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1982 ; - assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28139 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1980 ; - assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28139 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1978 ; - assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28139 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1976 ; - assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28139 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1974 ; - assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28139 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo2002 ; - assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28139 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo2000 ; - assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28139 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1998 ; - assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28139 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1996 ; - assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28139 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1994 ; - assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28139 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1992 ; - assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28139 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1990 ; - assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28139 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26923[0] : - _dfoo1988 ; - - // register m_cfg_verbosity - assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign m_cfg_verbosity$EN = EN_set_verbosity ; - - // register m_rg_addr_base - assign m_rg_addr_base$D_IN = set_addr_map_addr_base ; - assign m_rg_addr_base$EN = EN_set_addr_map ; - - // register m_rg_addr_lim - assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign m_rg_addr_lim$EN = EN_set_addr_map ; - - // register m_vrg_servicing_source_0 - assign m_vrg_servicing_source_0$D_IN = - MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26922[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_servicing_source_1 - assign m_vrg_servicing_source_1$D_IN = - MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26922[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_0 - assign m_vrg_source_busy_0$D_IN = - !MUX_m_vrg_source_busy_0$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_1 - assign m_vrg_source_busy_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_10 - assign m_vrg_source_busy_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_11 - assign m_vrg_source_busy_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_12 - assign m_vrg_source_busy_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_13 - assign m_vrg_source_busy_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_14 - assign m_vrg_source_busy_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_15 - assign m_vrg_source_busy_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_16 - assign m_vrg_source_busy_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67427 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_2 - assign m_vrg_source_busy_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_3 - assign m_vrg_source_busy_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_4 - assign m_vrg_source_busy_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_5 - assign m_vrg_source_busy_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_6 - assign m_vrg_source_busy_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_7 - assign m_vrg_source_busy_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_8 - assign m_vrg_source_busy_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_9 - assign m_vrg_source_busy_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67427 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_0 - assign m_vrg_source_ip_0$D_IN = 1'd0 ; - assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_1 - assign m_vrg_source_ip_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_0_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_1$EN = - !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_10 - assign m_vrg_source_ip_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_9_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_10$EN = - !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_11 - assign m_vrg_source_ip_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_10_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_11$EN = - !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_12 - assign m_vrg_source_ip_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_11_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_12$EN = - !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_13 - assign m_vrg_source_ip_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_12_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_13$EN = - !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_14 - assign m_vrg_source_ip_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_13_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_14$EN = - !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_15 - assign m_vrg_source_ip_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_14_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_15$EN = - !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_16 - assign m_vrg_source_ip_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_15_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_16$EN = - !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_2 - assign m_vrg_source_ip_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_1_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_2$EN = - !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_3 - assign m_vrg_source_ip_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_2_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_3$EN = - !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_4 - assign m_vrg_source_ip_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_3_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_4$EN = - !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_5 - assign m_vrg_source_ip_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_4_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_5$EN = - !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_6 - assign m_vrg_source_ip_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_5_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_6$EN = - !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_7 - assign m_vrg_source_ip_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_6_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_7$EN = - !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_8 - assign m_vrg_source_ip_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_7_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_8$EN = - !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_9 - assign m_vrg_source_ip_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_8_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_9$EN = - !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_0 - assign m_vrg_source_prio_0$D_IN = - MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26922[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_1 - assign m_vrg_source_prio_1$D_IN = - MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_10 - assign m_vrg_source_prio_10$D_IN = - MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_11 - assign m_vrg_source_prio_11$D_IN = - MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_12 - assign m_vrg_source_prio_12$D_IN = - MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_13 - assign m_vrg_source_prio_13$D_IN = - MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_14 - assign m_vrg_source_prio_14$D_IN = - MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_15 - assign m_vrg_source_prio_15$D_IN = - MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_16 - assign m_vrg_source_prio_16$D_IN = - MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_2 - assign m_vrg_source_prio_2$D_IN = - MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_3 - assign m_vrg_source_prio_3$D_IN = - MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_4 - assign m_vrg_source_prio_4$D_IN = - MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_5 - assign m_vrg_source_prio_5$D_IN = - MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_6 - assign m_vrg_source_prio_6$D_IN = - MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_7 - assign m_vrg_source_prio_7$D_IN = - MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_8 - assign m_vrg_source_prio_8$D_IN = - MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_9 - assign m_vrg_source_prio_9$D_IN = - MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd0 ; - assign m_vrg_source_prio_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_0 - assign m_vrg_target_threshold_0$D_IN = - MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_1 - assign m_vrg_target_threshold_1$D_IN = - MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26923[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_0 - assign m_vvrg_ie_0_0$D_IN = - MUX_m_vvrg_ie_0_0$write_1__SEL_1 && - MUX_m_vvrg_ie_0_0$write_1__VAL_1 ; - assign m_vvrg_ie_0_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_1 - assign m_vvrg_ie_0_1$D_IN = - MUX_m_vvrg_ie_0_1$write_1__SEL_1 && - MUX_m_vvrg_ie_0_1$write_1__VAL_1 ; - assign m_vvrg_ie_0_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_10 - assign m_vvrg_ie_0_10$D_IN = - MUX_m_vvrg_ie_0_10$write_1__SEL_1 && - MUX_m_vvrg_ie_0_10$write_1__VAL_1 ; - assign m_vvrg_ie_0_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_11 - assign m_vvrg_ie_0_11$D_IN = - MUX_m_vvrg_ie_0_11$write_1__SEL_1 && - MUX_m_vvrg_ie_0_11$write_1__VAL_1 ; - assign m_vvrg_ie_0_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_12 - assign m_vvrg_ie_0_12$D_IN = - MUX_m_vvrg_ie_0_12$write_1__SEL_1 && - MUX_m_vvrg_ie_0_12$write_1__VAL_1 ; - assign m_vvrg_ie_0_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_13 - assign m_vvrg_ie_0_13$D_IN = - MUX_m_vvrg_ie_0_13$write_1__SEL_1 && - MUX_m_vvrg_ie_0_13$write_1__VAL_1 ; - assign m_vvrg_ie_0_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_14 - assign m_vvrg_ie_0_14$D_IN = - MUX_m_vvrg_ie_0_14$write_1__SEL_1 && - MUX_m_vvrg_ie_0_14$write_1__VAL_1 ; - assign m_vvrg_ie_0_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_15 - assign m_vvrg_ie_0_15$D_IN = - MUX_m_vvrg_ie_0_15$write_1__SEL_1 && - MUX_m_vvrg_ie_0_15$write_1__VAL_1 ; - assign m_vvrg_ie_0_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_16 - assign m_vvrg_ie_0_16$D_IN = - MUX_m_vvrg_ie_0_16$write_1__SEL_1 && - MUX_m_vvrg_ie_0_16$write_1__VAL_1 ; - assign m_vvrg_ie_0_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_2 - assign m_vvrg_ie_0_2$D_IN = - MUX_m_vvrg_ie_0_2$write_1__SEL_1 && - MUX_m_vvrg_ie_0_2$write_1__VAL_1 ; - assign m_vvrg_ie_0_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_3 - assign m_vvrg_ie_0_3$D_IN = - MUX_m_vvrg_ie_0_3$write_1__SEL_1 && - MUX_m_vvrg_ie_0_3$write_1__VAL_1 ; - assign m_vvrg_ie_0_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_4 - assign m_vvrg_ie_0_4$D_IN = - MUX_m_vvrg_ie_0_4$write_1__SEL_1 && - MUX_m_vvrg_ie_0_4$write_1__VAL_1 ; - assign m_vvrg_ie_0_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_5 - assign m_vvrg_ie_0_5$D_IN = - MUX_m_vvrg_ie_0_5$write_1__SEL_1 && - MUX_m_vvrg_ie_0_5$write_1__VAL_1 ; - assign m_vvrg_ie_0_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_6 - assign m_vvrg_ie_0_6$D_IN = - MUX_m_vvrg_ie_0_6$write_1__SEL_1 && - MUX_m_vvrg_ie_0_6$write_1__VAL_1 ; - assign m_vvrg_ie_0_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_7 - assign m_vvrg_ie_0_7$D_IN = - MUX_m_vvrg_ie_0_7$write_1__SEL_1 && - MUX_m_vvrg_ie_0_7$write_1__VAL_1 ; - assign m_vvrg_ie_0_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_8 - assign m_vvrg_ie_0_8$D_IN = - MUX_m_vvrg_ie_0_8$write_1__SEL_1 && - MUX_m_vvrg_ie_0_8$write_1__VAL_1 ; - assign m_vvrg_ie_0_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_9 - assign m_vvrg_ie_0_9$D_IN = - MUX_m_vvrg_ie_0_9$write_1__SEL_1 && - MUX_m_vvrg_ie_0_9$write_1__VAL_1 ; - assign m_vvrg_ie_0_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_0 - assign m_vvrg_ie_1_0$D_IN = - MUX_m_vvrg_ie_1_0$write_1__SEL_1 && - MUX_m_vvrg_ie_1_0$write_1__VAL_1 ; - assign m_vvrg_ie_1_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_1 - assign m_vvrg_ie_1_1$D_IN = - MUX_m_vvrg_ie_1_1$write_1__SEL_1 && - MUX_m_vvrg_ie_1_1$write_1__VAL_1 ; - assign m_vvrg_ie_1_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_10 - assign m_vvrg_ie_1_10$D_IN = - MUX_m_vvrg_ie_1_10$write_1__SEL_1 && - MUX_m_vvrg_ie_1_10$write_1__VAL_1 ; - assign m_vvrg_ie_1_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_11 - assign m_vvrg_ie_1_11$D_IN = - MUX_m_vvrg_ie_1_11$write_1__SEL_1 && - MUX_m_vvrg_ie_1_11$write_1__VAL_1 ; - assign m_vvrg_ie_1_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_12 - assign m_vvrg_ie_1_12$D_IN = - MUX_m_vvrg_ie_1_12$write_1__SEL_1 && - MUX_m_vvrg_ie_1_12$write_1__VAL_1 ; - assign m_vvrg_ie_1_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_13 - assign m_vvrg_ie_1_13$D_IN = - MUX_m_vvrg_ie_1_13$write_1__SEL_1 && - MUX_m_vvrg_ie_1_13$write_1__VAL_1 ; - assign m_vvrg_ie_1_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_14 - assign m_vvrg_ie_1_14$D_IN = - MUX_m_vvrg_ie_1_14$write_1__SEL_1 && - MUX_m_vvrg_ie_1_14$write_1__VAL_1 ; - assign m_vvrg_ie_1_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_15 - assign m_vvrg_ie_1_15$D_IN = - MUX_m_vvrg_ie_1_15$write_1__SEL_1 && - MUX_m_vvrg_ie_1_15$write_1__VAL_1 ; - assign m_vvrg_ie_1_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_16 - assign m_vvrg_ie_1_16$D_IN = - MUX_m_vvrg_ie_1_16$write_1__SEL_1 && - MUX_m_vvrg_ie_1_16$write_1__VAL_1 ; - assign m_vvrg_ie_1_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_2 - assign m_vvrg_ie_1_2$D_IN = - MUX_m_vvrg_ie_1_2$write_1__SEL_1 && - MUX_m_vvrg_ie_1_2$write_1__VAL_1 ; - assign m_vvrg_ie_1_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_3 - assign m_vvrg_ie_1_3$D_IN = - MUX_m_vvrg_ie_1_3$write_1__SEL_1 && - MUX_m_vvrg_ie_1_3$write_1__VAL_1 ; - assign m_vvrg_ie_1_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_4 - assign m_vvrg_ie_1_4$D_IN = - MUX_m_vvrg_ie_1_4$write_1__SEL_1 && - MUX_m_vvrg_ie_1_4$write_1__VAL_1 ; - assign m_vvrg_ie_1_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_5 - assign m_vvrg_ie_1_5$D_IN = - MUX_m_vvrg_ie_1_5$write_1__SEL_1 && - MUX_m_vvrg_ie_1_5$write_1__VAL_1 ; - assign m_vvrg_ie_1_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_6 - assign m_vvrg_ie_1_6$D_IN = - MUX_m_vvrg_ie_1_6$write_1__SEL_1 && - MUX_m_vvrg_ie_1_6$write_1__VAL_1 ; - assign m_vvrg_ie_1_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_7 - assign m_vvrg_ie_1_7$D_IN = - MUX_m_vvrg_ie_1_7$write_1__SEL_1 && - MUX_m_vvrg_ie_1_7$write_1__VAL_1 ; - assign m_vvrg_ie_1_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_8 - assign m_vvrg_ie_1_8$D_IN = - MUX_m_vvrg_ie_1_8$write_1__SEL_1 && - MUX_m_vvrg_ie_1_8$write_1__VAL_1 ; - assign m_vvrg_ie_1_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_9 - assign m_vvrg_ie_1_9$D_IN = - MUX_m_vvrg_ie_1_9$write_1__SEL_1 && - MUX_m_vvrg_ie_1_9$write_1__VAL_1 ; - assign m_vvrg_ie_1_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 || - WILL_FIRE_RL_m_rl_reset ; - - // submodule m_f_reset_reqs - assign m_f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign m_f_reset_reqs$DEQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_reqs$CLR = 1'b0 ; - - // submodule m_f_reset_rsps - assign m_f_reset_rsps$ENQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign m_f_reset_rsps$CLR = 1'b0 ; - - // submodule m_slave_xactor_f_rd_addr - assign m_slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign m_slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ; - assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_rd_data - assign m_slave_xactor_f_rd_data$D_IN = - { m_slave_xactor_f_rd_addr$D_OUT[96:93], - x__h26361, - rresp__h26203, - 1'd1 } ; - assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ; - assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_addr - assign m_slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign m_slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ; - assign m_slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_data - assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; - assign m_slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; - assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_resp - assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26927 } ; - assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; - assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ; - - // remaining internal signals - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 : - ((x__h23673 == 32'h00200000) ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 : - x__h23673 != 32'h00200004 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 || - x__h24011 != 5'd0) ; - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - addr_offset__h13216[11:2] == 10'd0 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 : - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 : - ((x__h67101 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 : - x__h67101 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 || - !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? - addr_offset__h26922[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 = - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - 5'd2 : - (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ; - assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200000 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h30676 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h31886 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h33096 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h34306 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h35516 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h36726 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h37936 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h39146 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h40356 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h41566 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h42776 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h43986 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h45196 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h46406 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h47616 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h48826 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h50036 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h51246 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h52456 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h53666 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h54876 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h56086 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h57296 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h58506 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h59716 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h60926 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h62136 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h63346 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h64556 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h65766 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67101 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67101 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67101 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67101 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67101 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && - !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - addr_offset__h26922[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h29466 <= 10'd16 ; - assign NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311 = - !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319 = - !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_11 != - v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327 = - !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_12 != - v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335 = - !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_13 != - v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343 = - !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_14 != - v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351 = - !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_15 != - v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359 = - !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_16 != - v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240 = - !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247 = - !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255 = - !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263 = - !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271 = - !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279 = - !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287 = - !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295 = - !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303 = - !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; - assign _dfoo1 = - source_id__h64556 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo10 = - (source_id__h64556 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo100 = - (source_id__h63346 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo32 ; - assign _dfoo1000 = - (source_id__h47616 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo932 ; - assign _dfoo1001 = - source_id__h47616 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo865 ; - assign _dfoo1002 = - (source_id__h47616 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo934 ; - assign _dfoo1003 = - source_id__h47616 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo867 ; - assign _dfoo1004 = - (source_id__h47616 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo936 ; - assign _dfoo1005 = - source_id__h47616 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo869 ; - assign _dfoo1006 = - (source_id__h47616 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo938 ; - assign _dfoo1007 = - source_id__h47616 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo871 ; - assign _dfoo1008 = - (source_id__h47616 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo940 ; - assign _dfoo1009 = - source_id__h47616 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo873 ; - assign _dfoo1010 = - (source_id__h47616 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo942 ; - assign _dfoo1011 = - source_id__h47616 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo875 ; - assign _dfoo1012 = - (source_id__h47616 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo944 ; - assign _dfoo1013 = - source_id__h47616 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo877 ; - assign _dfoo1014 = - (source_id__h47616 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo946 ; - assign _dfoo1015 = - source_id__h47616 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo879 ; - assign _dfoo1016 = - (source_id__h47616 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo948 ; - assign _dfoo1017 = - source_id__h47616 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo881 ; - assign _dfoo1018 = - (source_id__h47616 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo950 ; - assign _dfoo1019 = - source_id__h47616 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo883 ; - assign _dfoo102 = - (source_id__h63346 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo34 ; - assign _dfoo1020 = - (source_id__h47616 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo952 ; - assign _dfoo1022 = - (source_id__h46406 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo954 ; - assign _dfoo1024 = - (source_id__h46406 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo956 ; - assign _dfoo1026 = - (source_id__h46406 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo958 ; - assign _dfoo1028 = - (source_id__h46406 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo960 ; - assign _dfoo1030 = - (source_id__h46406 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo962 ; - assign _dfoo1032 = - (source_id__h46406 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo964 ; - assign _dfoo1034 = - (source_id__h46406 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo966 ; - assign _dfoo1036 = - (source_id__h46406 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo968 ; - assign _dfoo1038 = - (source_id__h46406 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo970 ; - assign _dfoo104 = - (source_id__h63346 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo36 ; - assign _dfoo1040 = - (source_id__h46406 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo972 ; - assign _dfoo1042 = - (source_id__h46406 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo974 ; - assign _dfoo1044 = - (source_id__h46406 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo976 ; - assign _dfoo1046 = - (source_id__h46406 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo978 ; - assign _dfoo1048 = - (source_id__h46406 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo980 ; - assign _dfoo1050 = - (source_id__h46406 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo982 ; - assign _dfoo1052 = - (source_id__h46406 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo984 ; - assign _dfoo1054 = - (source_id__h46406 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo986 ; - assign _dfoo1056 = - (source_id__h46406 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo988 ; - assign _dfoo1058 = - (source_id__h46406 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo990 ; - assign _dfoo106 = - (source_id__h63346 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo38 ; - assign _dfoo1060 = - (source_id__h46406 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo992 ; - assign _dfoo1062 = - (source_id__h46406 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo994 ; - assign _dfoo1064 = - (source_id__h46406 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo996 ; - assign _dfoo1066 = - (source_id__h46406 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo998 ; - assign _dfoo1068 = - (source_id__h46406 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1000 ; - assign _dfoo1070 = - (source_id__h46406 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1002 ; - assign _dfoo1072 = - (source_id__h46406 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1004 ; - assign _dfoo1074 = - (source_id__h46406 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1006 ; - assign _dfoo1076 = - (source_id__h46406 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1008 ; - assign _dfoo1078 = - (source_id__h46406 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1010 ; - assign _dfoo108 = - (source_id__h63346 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo40 ; - assign _dfoo1080 = - (source_id__h46406 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1012 ; - assign _dfoo1082 = - (source_id__h46406 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1014 ; - assign _dfoo1084 = - (source_id__h46406 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1016 ; - assign _dfoo1086 = - (source_id__h46406 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1018 ; - assign _dfoo1088 = - (source_id__h46406 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26923[15] : - _dfoo1020 ; - assign _dfoo1089 = - source_id__h45196 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo953 ; - assign _dfoo1090 = - (source_id__h45196 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1022 ; - assign _dfoo1091 = - source_id__h45196 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo955 ; - assign _dfoo1092 = - (source_id__h45196 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1024 ; - assign _dfoo1093 = - source_id__h45196 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo957 ; - assign _dfoo1094 = - (source_id__h45196 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1026 ; - assign _dfoo1095 = - source_id__h45196 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo959 ; - assign _dfoo1096 = - (source_id__h45196 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1028 ; - assign _dfoo1097 = - source_id__h45196 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo961 ; - assign _dfoo1098 = - (source_id__h45196 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1030 ; - assign _dfoo1099 = - source_id__h45196 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo963 ; - assign _dfoo11 = - source_id__h64556 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo110 = - (source_id__h63346 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo42 ; - assign _dfoo1100 = - (source_id__h45196 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1032 ; - assign _dfoo1101 = - source_id__h45196 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo965 ; - assign _dfoo1102 = - (source_id__h45196 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1034 ; - assign _dfoo1103 = - source_id__h45196 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo967 ; - assign _dfoo1104 = - (source_id__h45196 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1036 ; - assign _dfoo1105 = - source_id__h45196 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo969 ; - assign _dfoo1106 = - (source_id__h45196 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1038 ; - assign _dfoo1107 = - source_id__h45196 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo971 ; - assign _dfoo1108 = - (source_id__h45196 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1040 ; - assign _dfoo1109 = - source_id__h45196 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo973 ; - assign _dfoo1110 = - (source_id__h45196 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1042 ; - assign _dfoo1111 = - source_id__h45196 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo975 ; - assign _dfoo1112 = - (source_id__h45196 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1044 ; - assign _dfoo1113 = - source_id__h45196 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo977 ; - assign _dfoo1114 = - (source_id__h45196 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1046 ; - assign _dfoo1115 = - source_id__h45196 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo979 ; - assign _dfoo1116 = - (source_id__h45196 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1048 ; - assign _dfoo1117 = - source_id__h45196 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo981 ; - assign _dfoo1118 = - (source_id__h45196 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1050 ; - assign _dfoo1119 = - source_id__h45196 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo983 ; - assign _dfoo112 = - (source_id__h63346 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo44 ; - assign _dfoo1120 = - (source_id__h45196 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1052 ; - assign _dfoo1121 = - source_id__h45196 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo985 ; - assign _dfoo1122 = - (source_id__h45196 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1054 ; - assign _dfoo1123 = - source_id__h45196 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo987 ; - assign _dfoo1124 = - (source_id__h45196 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1056 ; - assign _dfoo1125 = - source_id__h45196 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo989 ; - assign _dfoo1126 = - (source_id__h45196 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1058 ; - assign _dfoo1127 = - source_id__h45196 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo991 ; - assign _dfoo1128 = - (source_id__h45196 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1060 ; - assign _dfoo1129 = - source_id__h45196 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo993 ; - assign _dfoo1130 = - (source_id__h45196 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1062 ; - assign _dfoo1131 = - source_id__h45196 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo995 ; - assign _dfoo1132 = - (source_id__h45196 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1064 ; - assign _dfoo1133 = - source_id__h45196 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo997 ; - assign _dfoo1134 = - (source_id__h45196 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1066 ; - assign _dfoo1135 = - source_id__h45196 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo999 ; - assign _dfoo1136 = - (source_id__h45196 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1068 ; - assign _dfoo1137 = - source_id__h45196 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo1001 ; - assign _dfoo1138 = - (source_id__h45196 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1070 ; - assign _dfoo1139 = - source_id__h45196 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo1003 ; - assign _dfoo114 = - (source_id__h63346 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo46 ; - assign _dfoo1140 = - (source_id__h45196 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1072 ; - assign _dfoo1141 = - source_id__h45196 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo1005 ; - assign _dfoo1142 = - (source_id__h45196 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1074 ; - assign _dfoo1143 = - source_id__h45196 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo1007 ; - assign _dfoo1144 = - (source_id__h45196 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1076 ; - assign _dfoo1145 = - source_id__h45196 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo1009 ; - assign _dfoo1146 = - (source_id__h45196 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1078 ; - assign _dfoo1147 = - source_id__h45196 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo1011 ; - assign _dfoo1148 = - (source_id__h45196 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1080 ; - assign _dfoo1149 = - source_id__h45196 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo1013 ; - assign _dfoo1150 = - (source_id__h45196 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1082 ; - assign _dfoo1151 = - source_id__h45196 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo1015 ; - assign _dfoo1152 = - (source_id__h45196 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1084 ; - assign _dfoo1153 = - source_id__h45196 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo1017 ; - assign _dfoo1154 = - (source_id__h45196 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1086 ; - assign _dfoo1155 = - source_id__h45196 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46406 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || - _dfoo1019 ; - assign _dfoo1156 = - (source_id__h45196 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26923[14] : - _dfoo1088 ; - assign _dfoo1158 = - (source_id__h43986 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1090 ; - assign _dfoo116 = - (source_id__h63346 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo48 ; - assign _dfoo1160 = - (source_id__h43986 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1092 ; - assign _dfoo1162 = - (source_id__h43986 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1094 ; - assign _dfoo1164 = - (source_id__h43986 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1096 ; - assign _dfoo1166 = - (source_id__h43986 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1098 ; - assign _dfoo1168 = - (source_id__h43986 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1100 ; - assign _dfoo1170 = - (source_id__h43986 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1102 ; - assign _dfoo1172 = - (source_id__h43986 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1104 ; - assign _dfoo1174 = - (source_id__h43986 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1106 ; - assign _dfoo1176 = - (source_id__h43986 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1108 ; - assign _dfoo1178 = - (source_id__h43986 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1110 ; - assign _dfoo118 = - (source_id__h63346 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo50 ; - assign _dfoo1180 = - (source_id__h43986 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1112 ; - assign _dfoo1182 = - (source_id__h43986 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1114 ; - assign _dfoo1184 = - (source_id__h43986 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1116 ; - assign _dfoo1186 = - (source_id__h43986 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1118 ; - assign _dfoo1188 = - (source_id__h43986 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1120 ; - assign _dfoo1190 = - (source_id__h43986 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1122 ; - assign _dfoo1192 = - (source_id__h43986 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1124 ; - assign _dfoo1194 = - (source_id__h43986 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1126 ; - assign _dfoo1196 = - (source_id__h43986 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1128 ; - assign _dfoo1198 = - (source_id__h43986 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1130 ; - assign _dfoo12 = - (source_id__h64556 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo120 = - (source_id__h63346 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo52 ; - assign _dfoo1200 = - (source_id__h43986 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1132 ; - assign _dfoo1202 = - (source_id__h43986 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1134 ; - assign _dfoo1204 = - (source_id__h43986 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1136 ; - assign _dfoo1206 = - (source_id__h43986 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1138 ; - assign _dfoo1208 = - (source_id__h43986 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1140 ; - assign _dfoo1210 = - (source_id__h43986 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1142 ; - assign _dfoo1212 = - (source_id__h43986 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1144 ; - assign _dfoo1214 = - (source_id__h43986 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1146 ; - assign _dfoo1216 = - (source_id__h43986 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1148 ; - assign _dfoo1218 = - (source_id__h43986 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1150 ; - assign _dfoo122 = - (source_id__h63346 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo54 ; - assign _dfoo1220 = - (source_id__h43986 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1152 ; - assign _dfoo1222 = - (source_id__h43986 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1154 ; - assign _dfoo1224 = - (source_id__h43986 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26923[13] : - _dfoo1156 ; - assign _dfoo1225 = - source_id__h42776 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1089 ; - assign _dfoo1226 = - (source_id__h42776 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1158 ; - assign _dfoo1227 = - source_id__h42776 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1091 ; - assign _dfoo1228 = - (source_id__h42776 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1160 ; - assign _dfoo1229 = - source_id__h42776 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1093 ; - assign _dfoo1230 = - (source_id__h42776 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1162 ; - assign _dfoo1231 = - source_id__h42776 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1095 ; - assign _dfoo1232 = - (source_id__h42776 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1164 ; - assign _dfoo1233 = - source_id__h42776 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1097 ; - assign _dfoo1234 = - (source_id__h42776 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1166 ; - assign _dfoo1235 = - source_id__h42776 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1099 ; - assign _dfoo1236 = - (source_id__h42776 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1168 ; - assign _dfoo1237 = - source_id__h42776 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1101 ; - assign _dfoo1238 = - (source_id__h42776 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1170 ; - assign _dfoo1239 = - source_id__h42776 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1103 ; - assign _dfoo124 = - (source_id__h63346 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo56 ; - assign _dfoo1240 = - (source_id__h42776 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1172 ; - assign _dfoo1241 = - source_id__h42776 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1105 ; - assign _dfoo1242 = - (source_id__h42776 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1174 ; - assign _dfoo1243 = - source_id__h42776 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1107 ; - assign _dfoo1244 = - (source_id__h42776 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1176 ; - assign _dfoo1245 = - source_id__h42776 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1109 ; - assign _dfoo1246 = - (source_id__h42776 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1178 ; - assign _dfoo1247 = - source_id__h42776 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1111 ; - assign _dfoo1248 = - (source_id__h42776 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1180 ; - assign _dfoo1249 = - source_id__h42776 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1113 ; - assign _dfoo1250 = - (source_id__h42776 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1182 ; - assign _dfoo1251 = - source_id__h42776 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1115 ; - assign _dfoo1252 = - (source_id__h42776 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1184 ; - assign _dfoo1253 = - source_id__h42776 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1117 ; - assign _dfoo1254 = - (source_id__h42776 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1186 ; - assign _dfoo1255 = - source_id__h42776 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1119 ; - assign _dfoo1256 = - (source_id__h42776 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1188 ; - assign _dfoo1257 = - source_id__h42776 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1121 ; - assign _dfoo1258 = - (source_id__h42776 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1190 ; - assign _dfoo1259 = - source_id__h42776 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1123 ; - assign _dfoo126 = - (source_id__h63346 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo58 ; - assign _dfoo1260 = - (source_id__h42776 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1192 ; - assign _dfoo1261 = - source_id__h42776 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1125 ; - assign _dfoo1262 = - (source_id__h42776 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1194 ; - assign _dfoo1263 = - source_id__h42776 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1127 ; - assign _dfoo1264 = - (source_id__h42776 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1196 ; - assign _dfoo1265 = - source_id__h42776 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1129 ; - assign _dfoo1266 = - (source_id__h42776 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1198 ; - assign _dfoo1267 = - source_id__h42776 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1131 ; - assign _dfoo1268 = - (source_id__h42776 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1200 ; - assign _dfoo1269 = - source_id__h42776 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1133 ; - assign _dfoo1270 = - (source_id__h42776 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1202 ; - assign _dfoo1271 = - source_id__h42776 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1135 ; - assign _dfoo1272 = - (source_id__h42776 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1204 ; - assign _dfoo1273 = - source_id__h42776 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1137 ; - assign _dfoo1274 = - (source_id__h42776 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1206 ; - assign _dfoo1275 = - source_id__h42776 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1139 ; - assign _dfoo1276 = - (source_id__h42776 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1208 ; - assign _dfoo1277 = - source_id__h42776 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1141 ; - assign _dfoo1278 = - (source_id__h42776 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1210 ; - assign _dfoo1279 = - source_id__h42776 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1143 ; - assign _dfoo128 = - (source_id__h63346 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo60 ; - assign _dfoo1280 = - (source_id__h42776 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1212 ; - assign _dfoo1281 = - source_id__h42776 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1145 ; - assign _dfoo1282 = - (source_id__h42776 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1214 ; - assign _dfoo1283 = - source_id__h42776 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1147 ; - assign _dfoo1284 = - (source_id__h42776 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1216 ; - assign _dfoo1285 = - source_id__h42776 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1149 ; - assign _dfoo1286 = - (source_id__h42776 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1218 ; - assign _dfoo1287 = - source_id__h42776 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1151 ; - assign _dfoo1288 = - (source_id__h42776 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1220 ; - assign _dfoo1289 = - source_id__h42776 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1153 ; - assign _dfoo1290 = - (source_id__h42776 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1222 ; - assign _dfoo1291 = - source_id__h42776 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43986 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || - _dfoo1155 ; - assign _dfoo1292 = - (source_id__h42776 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26923[12] : - _dfoo1224 ; - assign _dfoo1294 = - (source_id__h41566 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1226 ; - assign _dfoo1296 = - (source_id__h41566 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1228 ; - assign _dfoo1298 = - (source_id__h41566 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1230 ; - assign _dfoo13 = - source_id__h64556 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo130 = - (source_id__h63346 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo62 ; - assign _dfoo1300 = - (source_id__h41566 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1232 ; - assign _dfoo1302 = - (source_id__h41566 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1234 ; - assign _dfoo1304 = - (source_id__h41566 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1236 ; - assign _dfoo1306 = - (source_id__h41566 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1238 ; - assign _dfoo1308 = - (source_id__h41566 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1240 ; - assign _dfoo1310 = - (source_id__h41566 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1242 ; - assign _dfoo1312 = - (source_id__h41566 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1244 ; - assign _dfoo1314 = - (source_id__h41566 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1246 ; - assign _dfoo1316 = - (source_id__h41566 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1248 ; - assign _dfoo1318 = - (source_id__h41566 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1250 ; - assign _dfoo132 = - (source_id__h63346 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo64 ; - assign _dfoo1320 = - (source_id__h41566 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1252 ; - assign _dfoo1322 = - (source_id__h41566 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1254 ; - assign _dfoo1324 = - (source_id__h41566 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1256 ; - assign _dfoo1326 = - (source_id__h41566 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1258 ; - assign _dfoo1328 = - (source_id__h41566 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1260 ; - assign _dfoo1330 = - (source_id__h41566 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1262 ; - assign _dfoo1332 = - (source_id__h41566 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1264 ; - assign _dfoo1334 = - (source_id__h41566 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1266 ; - assign _dfoo1336 = - (source_id__h41566 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1268 ; - assign _dfoo1338 = - (source_id__h41566 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1270 ; - assign _dfoo134 = - (source_id__h63346 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo66 ; - assign _dfoo1340 = - (source_id__h41566 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1272 ; - assign _dfoo1342 = - (source_id__h41566 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1274 ; - assign _dfoo1344 = - (source_id__h41566 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1276 ; - assign _dfoo1346 = - (source_id__h41566 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1278 ; - assign _dfoo1348 = - (source_id__h41566 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1280 ; - assign _dfoo1350 = - (source_id__h41566 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1282 ; - assign _dfoo1352 = - (source_id__h41566 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1284 ; - assign _dfoo1354 = - (source_id__h41566 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1286 ; - assign _dfoo1356 = - (source_id__h41566 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1288 ; - assign _dfoo1358 = - (source_id__h41566 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1290 ; - assign _dfoo136 = - (source_id__h63346 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo68 ; - assign _dfoo1360 = - (source_id__h41566 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26923[11] : - _dfoo1292 ; - assign _dfoo1361 = - source_id__h40356 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1225 ; - assign _dfoo1362 = - (source_id__h40356 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1294 ; - assign _dfoo1363 = - source_id__h40356 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1227 ; - assign _dfoo1364 = - (source_id__h40356 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1296 ; - assign _dfoo1365 = - source_id__h40356 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1229 ; - assign _dfoo1366 = - (source_id__h40356 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1298 ; - assign _dfoo1367 = - source_id__h40356 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1231 ; - assign _dfoo1368 = - (source_id__h40356 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1300 ; - assign _dfoo1369 = - source_id__h40356 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1233 ; - assign _dfoo137 = - source_id__h62136 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo1 ; - assign _dfoo1370 = - (source_id__h40356 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1302 ; - assign _dfoo1371 = - source_id__h40356 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1235 ; - assign _dfoo1372 = - (source_id__h40356 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1304 ; - assign _dfoo1373 = - source_id__h40356 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1237 ; - assign _dfoo1374 = - (source_id__h40356 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1306 ; - assign _dfoo1375 = - source_id__h40356 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1239 ; - assign _dfoo1376 = - (source_id__h40356 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1308 ; - assign _dfoo1377 = - source_id__h40356 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1241 ; - assign _dfoo1378 = - (source_id__h40356 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1310 ; - assign _dfoo1379 = - source_id__h40356 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1243 ; - assign _dfoo138 = - (source_id__h62136 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo70 ; - assign _dfoo1380 = - (source_id__h40356 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1312 ; - assign _dfoo1381 = - source_id__h40356 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1245 ; - assign _dfoo1382 = - (source_id__h40356 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1314 ; - assign _dfoo1383 = - source_id__h40356 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1247 ; - assign _dfoo1384 = - (source_id__h40356 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1316 ; - assign _dfoo1385 = - source_id__h40356 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1249 ; - assign _dfoo1386 = - (source_id__h40356 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1318 ; - assign _dfoo1387 = - source_id__h40356 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1251 ; - assign _dfoo1388 = - (source_id__h40356 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1320 ; - assign _dfoo1389 = - source_id__h40356 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1253 ; - assign _dfoo139 = - source_id__h62136 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo3 ; - assign _dfoo1390 = - (source_id__h40356 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1322 ; - assign _dfoo1391 = - source_id__h40356 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1255 ; - assign _dfoo1392 = - (source_id__h40356 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1324 ; - assign _dfoo1393 = - source_id__h40356 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1257 ; - assign _dfoo1394 = - (source_id__h40356 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1326 ; - assign _dfoo1395 = - source_id__h40356 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1259 ; - assign _dfoo1396 = - (source_id__h40356 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1328 ; - assign _dfoo1397 = - source_id__h40356 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1261 ; - assign _dfoo1398 = - (source_id__h40356 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1330 ; - assign _dfoo1399 = - source_id__h40356 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1263 ; - assign _dfoo14 = - (source_id__h64556 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo140 = - (source_id__h62136 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo72 ; - assign _dfoo1400 = - (source_id__h40356 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1332 ; - assign _dfoo1401 = - source_id__h40356 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1265 ; - assign _dfoo1402 = - (source_id__h40356 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1334 ; - assign _dfoo1403 = - source_id__h40356 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1267 ; - assign _dfoo1404 = - (source_id__h40356 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1336 ; - assign _dfoo1405 = - source_id__h40356 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1269 ; - assign _dfoo1406 = - (source_id__h40356 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1338 ; - assign _dfoo1407 = - source_id__h40356 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1271 ; - assign _dfoo1408 = - (source_id__h40356 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1340 ; - assign _dfoo1409 = - source_id__h40356 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1273 ; - assign _dfoo141 = - source_id__h62136 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo5 ; - assign _dfoo1410 = - (source_id__h40356 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1342 ; - assign _dfoo1411 = - source_id__h40356 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1275 ; - assign _dfoo1412 = - (source_id__h40356 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1344 ; - assign _dfoo1413 = - source_id__h40356 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1277 ; - assign _dfoo1414 = - (source_id__h40356 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1346 ; - assign _dfoo1415 = - source_id__h40356 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1279 ; - assign _dfoo1416 = - (source_id__h40356 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1348 ; - assign _dfoo1417 = - source_id__h40356 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1281 ; - assign _dfoo1418 = - (source_id__h40356 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1350 ; - assign _dfoo1419 = - source_id__h40356 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1283 ; - assign _dfoo142 = - (source_id__h62136 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo74 ; - assign _dfoo1420 = - (source_id__h40356 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1352 ; - assign _dfoo1421 = - source_id__h40356 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1285 ; - assign _dfoo1422 = - (source_id__h40356 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1354 ; - assign _dfoo1423 = - source_id__h40356 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1287 ; - assign _dfoo1424 = - (source_id__h40356 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1356 ; - assign _dfoo1425 = - source_id__h40356 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1289 ; - assign _dfoo1426 = - (source_id__h40356 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1358 ; - assign _dfoo1427 = - source_id__h40356 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41566 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || - _dfoo1291 ; - assign _dfoo1428 = - (source_id__h40356 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26923[10] : - _dfoo1360 ; - assign _dfoo143 = - source_id__h62136 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo7 ; - assign _dfoo1430 = - (source_id__h39146 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1362 ; - assign _dfoo1432 = - (source_id__h39146 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1364 ; - assign _dfoo1434 = - (source_id__h39146 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1366 ; - assign _dfoo1436 = - (source_id__h39146 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1368 ; - assign _dfoo1438 = - (source_id__h39146 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1370 ; - assign _dfoo144 = - (source_id__h62136 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo76 ; - assign _dfoo1440 = - (source_id__h39146 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1372 ; - assign _dfoo1442 = - (source_id__h39146 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1374 ; - assign _dfoo1444 = - (source_id__h39146 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1376 ; - assign _dfoo1446 = - (source_id__h39146 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1378 ; - assign _dfoo1448 = - (source_id__h39146 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1380 ; - assign _dfoo145 = - source_id__h62136 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo9 ; - assign _dfoo1450 = - (source_id__h39146 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1382 ; - assign _dfoo1452 = - (source_id__h39146 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1384 ; - assign _dfoo1454 = - (source_id__h39146 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1386 ; - assign _dfoo1456 = - (source_id__h39146 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1388 ; - assign _dfoo1458 = - (source_id__h39146 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1390 ; - assign _dfoo146 = - (source_id__h62136 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo78 ; - assign _dfoo1460 = - (source_id__h39146 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1392 ; - assign _dfoo1462 = - (source_id__h39146 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1394 ; - assign _dfoo1464 = - (source_id__h39146 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1396 ; - assign _dfoo1466 = - (source_id__h39146 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1398 ; - assign _dfoo1468 = - (source_id__h39146 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1400 ; - assign _dfoo147 = - source_id__h62136 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo11 ; - assign _dfoo1470 = - (source_id__h39146 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1402 ; - assign _dfoo1472 = - (source_id__h39146 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1404 ; - assign _dfoo1474 = - (source_id__h39146 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1406 ; - assign _dfoo1476 = - (source_id__h39146 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1408 ; - assign _dfoo1478 = - (source_id__h39146 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1410 ; - assign _dfoo148 = - (source_id__h62136 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo80 ; - assign _dfoo1480 = - (source_id__h39146 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1412 ; - assign _dfoo1482 = - (source_id__h39146 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1414 ; - assign _dfoo1484 = - (source_id__h39146 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1416 ; - assign _dfoo1486 = - (source_id__h39146 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1418 ; - assign _dfoo1488 = - (source_id__h39146 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1420 ; - assign _dfoo149 = - source_id__h62136 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo13 ; - assign _dfoo1490 = - (source_id__h39146 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1422 ; - assign _dfoo1492 = - (source_id__h39146 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1424 ; - assign _dfoo1494 = - (source_id__h39146 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1426 ; - assign _dfoo1496 = - (source_id__h39146 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26923[9] : - _dfoo1428 ; - assign _dfoo1497 = - source_id__h37936 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1361 ; - assign _dfoo1498 = - (source_id__h37936 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1430 ; - assign _dfoo1499 = - source_id__h37936 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1363 ; - assign _dfoo15 = - source_id__h64556 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo150 = - (source_id__h62136 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo82 ; - assign _dfoo1500 = - (source_id__h37936 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1432 ; - assign _dfoo1501 = - source_id__h37936 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1365 ; - assign _dfoo1502 = - (source_id__h37936 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1434 ; - assign _dfoo1503 = - source_id__h37936 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1367 ; - assign _dfoo1504 = - (source_id__h37936 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1436 ; - assign _dfoo1505 = - source_id__h37936 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1369 ; - assign _dfoo1506 = - (source_id__h37936 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1438 ; - assign _dfoo1507 = - source_id__h37936 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1371 ; - assign _dfoo1508 = - (source_id__h37936 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1440 ; - assign _dfoo1509 = - source_id__h37936 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1373 ; - assign _dfoo151 = - source_id__h62136 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo15 ; - assign _dfoo1510 = - (source_id__h37936 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1442 ; - assign _dfoo1511 = - source_id__h37936 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1375 ; - assign _dfoo1512 = - (source_id__h37936 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1444 ; - assign _dfoo1513 = - source_id__h37936 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1377 ; - assign _dfoo1514 = - (source_id__h37936 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1446 ; - assign _dfoo1515 = - source_id__h37936 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1379 ; - assign _dfoo1516 = - (source_id__h37936 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1448 ; - assign _dfoo1517 = - source_id__h37936 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1381 ; - assign _dfoo1518 = - (source_id__h37936 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1450 ; - assign _dfoo1519 = - source_id__h37936 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1383 ; - assign _dfoo152 = - (source_id__h62136 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo84 ; - assign _dfoo1520 = - (source_id__h37936 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1452 ; - assign _dfoo1521 = - source_id__h37936 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1385 ; - assign _dfoo1522 = - (source_id__h37936 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1454 ; - assign _dfoo1523 = - source_id__h37936 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1387 ; - assign _dfoo1524 = - (source_id__h37936 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1456 ; - assign _dfoo1525 = - source_id__h37936 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1389 ; - assign _dfoo1526 = - (source_id__h37936 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1458 ; - assign _dfoo1527 = - source_id__h37936 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1391 ; - assign _dfoo1528 = - (source_id__h37936 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1460 ; - assign _dfoo1529 = - source_id__h37936 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1393 ; - assign _dfoo153 = - source_id__h62136 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo17 ; - assign _dfoo1530 = - (source_id__h37936 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1462 ; - assign _dfoo1531 = - source_id__h37936 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1395 ; - assign _dfoo1532 = - (source_id__h37936 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1464 ; - assign _dfoo1533 = - source_id__h37936 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1397 ; - assign _dfoo1534 = - (source_id__h37936 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1466 ; - assign _dfoo1535 = - source_id__h37936 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1399 ; - assign _dfoo1536 = - (source_id__h37936 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1468 ; - assign _dfoo1537 = - source_id__h37936 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1401 ; - assign _dfoo1538 = - (source_id__h37936 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1470 ; - assign _dfoo1539 = - source_id__h37936 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1403 ; - assign _dfoo154 = - (source_id__h62136 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo86 ; - assign _dfoo1540 = - (source_id__h37936 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1472 ; - assign _dfoo1541 = - source_id__h37936 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1405 ; - assign _dfoo1542 = - (source_id__h37936 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1474 ; - assign _dfoo1543 = - source_id__h37936 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1407 ; - assign _dfoo1544 = - (source_id__h37936 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1476 ; - assign _dfoo1545 = - source_id__h37936 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1409 ; - assign _dfoo1546 = - (source_id__h37936 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1478 ; - assign _dfoo1547 = - source_id__h37936 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1411 ; - assign _dfoo1548 = - (source_id__h37936 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1480 ; - assign _dfoo1549 = - source_id__h37936 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1413 ; - assign _dfoo155 = - source_id__h62136 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo19 ; - assign _dfoo1550 = - (source_id__h37936 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1482 ; - assign _dfoo1551 = - source_id__h37936 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1415 ; - assign _dfoo1552 = - (source_id__h37936 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1484 ; - assign _dfoo1553 = - source_id__h37936 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1417 ; - assign _dfoo1554 = - (source_id__h37936 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1486 ; - assign _dfoo1555 = - source_id__h37936 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1419 ; - assign _dfoo1556 = - (source_id__h37936 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1488 ; - assign _dfoo1557 = - source_id__h37936 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1421 ; - assign _dfoo1558 = - (source_id__h37936 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1490 ; - assign _dfoo1559 = - source_id__h37936 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1423 ; - assign _dfoo156 = - (source_id__h62136 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo88 ; - assign _dfoo1560 = - (source_id__h37936 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1492 ; - assign _dfoo1561 = - source_id__h37936 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1425 ; - assign _dfoo1562 = - (source_id__h37936 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1494 ; - assign _dfoo1563 = - source_id__h37936 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39146 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || - _dfoo1427 ; - assign _dfoo1564 = - (source_id__h37936 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26923[8] : - _dfoo1496 ; - assign _dfoo1566 = - (source_id__h36726 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1498 ; - assign _dfoo1568 = - (source_id__h36726 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1500 ; - assign _dfoo157 = - source_id__h62136 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo21 ; - assign _dfoo1570 = - (source_id__h36726 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1502 ; - assign _dfoo1572 = - (source_id__h36726 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1504 ; - assign _dfoo1574 = - (source_id__h36726 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1506 ; - assign _dfoo1576 = - (source_id__h36726 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1508 ; - assign _dfoo1578 = - (source_id__h36726 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1510 ; - assign _dfoo158 = - (source_id__h62136 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo90 ; - assign _dfoo1580 = - (source_id__h36726 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1512 ; - assign _dfoo1582 = - (source_id__h36726 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1514 ; - assign _dfoo1584 = - (source_id__h36726 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1516 ; - assign _dfoo1586 = - (source_id__h36726 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1518 ; - assign _dfoo1588 = - (source_id__h36726 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1520 ; - assign _dfoo159 = - source_id__h62136 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo23 ; - assign _dfoo1590 = - (source_id__h36726 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1522 ; - assign _dfoo1592 = - (source_id__h36726 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1524 ; - assign _dfoo1594 = - (source_id__h36726 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1526 ; - assign _dfoo1596 = - (source_id__h36726 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1528 ; - assign _dfoo1598 = - (source_id__h36726 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1530 ; - assign _dfoo16 = - (source_id__h64556 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo160 = - (source_id__h62136 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo92 ; - assign _dfoo1600 = - (source_id__h36726 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1532 ; - assign _dfoo1602 = - (source_id__h36726 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1534 ; - assign _dfoo1604 = - (source_id__h36726 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1536 ; - assign _dfoo1606 = - (source_id__h36726 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1538 ; - assign _dfoo1608 = - (source_id__h36726 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1540 ; - assign _dfoo161 = - source_id__h62136 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo25 ; - assign _dfoo1610 = - (source_id__h36726 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1542 ; - assign _dfoo1612 = - (source_id__h36726 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1544 ; - assign _dfoo1614 = - (source_id__h36726 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1546 ; - assign _dfoo1616 = - (source_id__h36726 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1548 ; - assign _dfoo1618 = - (source_id__h36726 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1550 ; - assign _dfoo162 = - (source_id__h62136 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo94 ; - assign _dfoo1620 = - (source_id__h36726 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1552 ; - assign _dfoo1622 = - (source_id__h36726 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1554 ; - assign _dfoo1624 = - (source_id__h36726 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1556 ; - assign _dfoo1626 = - (source_id__h36726 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1558 ; - assign _dfoo1628 = - (source_id__h36726 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1560 ; - assign _dfoo163 = - source_id__h62136 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo27 ; - assign _dfoo1630 = - (source_id__h36726 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1562 ; - assign _dfoo1632 = - (source_id__h36726 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26923[7] : - _dfoo1564 ; - assign _dfoo1633 = - source_id__h35516 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1497 ; - assign _dfoo1634 = - (source_id__h35516 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1566 ; - assign _dfoo1635 = - source_id__h35516 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1499 ; - assign _dfoo1636 = - (source_id__h35516 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1568 ; - assign _dfoo1637 = - source_id__h35516 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1501 ; - assign _dfoo1638 = - (source_id__h35516 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1570 ; - assign _dfoo1639 = - source_id__h35516 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1503 ; - assign _dfoo164 = - (source_id__h62136 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo96 ; - assign _dfoo1640 = - (source_id__h35516 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1572 ; - assign _dfoo1641 = - source_id__h35516 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1505 ; - assign _dfoo1642 = - (source_id__h35516 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1574 ; - assign _dfoo1643 = - source_id__h35516 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1507 ; - assign _dfoo1644 = - (source_id__h35516 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1576 ; - assign _dfoo1645 = - source_id__h35516 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1509 ; - assign _dfoo1646 = - (source_id__h35516 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1578 ; - assign _dfoo1647 = - source_id__h35516 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1511 ; - assign _dfoo1648 = - (source_id__h35516 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1580 ; - assign _dfoo1649 = - source_id__h35516 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1513 ; - assign _dfoo165 = - source_id__h62136 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo29 ; - assign _dfoo1650 = - (source_id__h35516 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1582 ; - assign _dfoo1651 = - source_id__h35516 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1515 ; - assign _dfoo1652 = - (source_id__h35516 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1584 ; - assign _dfoo1653 = - source_id__h35516 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1517 ; - assign _dfoo1654 = - (source_id__h35516 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1586 ; - assign _dfoo1655 = - source_id__h35516 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1519 ; - assign _dfoo1656 = - (source_id__h35516 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1588 ; - assign _dfoo1657 = - source_id__h35516 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1521 ; - assign _dfoo1658 = - (source_id__h35516 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1590 ; - assign _dfoo1659 = - source_id__h35516 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1523 ; - assign _dfoo166 = - (source_id__h62136 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo98 ; - assign _dfoo1660 = - (source_id__h35516 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1592 ; - assign _dfoo1661 = - source_id__h35516 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1525 ; - assign _dfoo1662 = - (source_id__h35516 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1594 ; - assign _dfoo1663 = - source_id__h35516 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1527 ; - assign _dfoo1664 = - (source_id__h35516 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1596 ; - assign _dfoo1665 = - source_id__h35516 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1529 ; - assign _dfoo1666 = - (source_id__h35516 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1598 ; - assign _dfoo1667 = - source_id__h35516 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1531 ; - assign _dfoo1668 = - (source_id__h35516 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1600 ; - assign _dfoo1669 = - source_id__h35516 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1533 ; - assign _dfoo167 = - source_id__h62136 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo31 ; - assign _dfoo1670 = - (source_id__h35516 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1602 ; - assign _dfoo1671 = - source_id__h35516 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1535 ; - assign _dfoo1672 = - (source_id__h35516 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1604 ; - assign _dfoo1673 = - source_id__h35516 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1537 ; - assign _dfoo1674 = - (source_id__h35516 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1606 ; - assign _dfoo1675 = - source_id__h35516 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1539 ; - assign _dfoo1676 = - (source_id__h35516 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1608 ; - assign _dfoo1677 = - source_id__h35516 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1541 ; - assign _dfoo1678 = - (source_id__h35516 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1610 ; - assign _dfoo1679 = - source_id__h35516 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1543 ; - assign _dfoo168 = - (source_id__h62136 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo100 ; - assign _dfoo1680 = - (source_id__h35516 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1612 ; - assign _dfoo1681 = - source_id__h35516 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1545 ; - assign _dfoo1682 = - (source_id__h35516 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1614 ; - assign _dfoo1683 = - source_id__h35516 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1547 ; - assign _dfoo1684 = - (source_id__h35516 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1616 ; - assign _dfoo1685 = - source_id__h35516 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1549 ; - assign _dfoo1686 = - (source_id__h35516 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1618 ; - assign _dfoo1687 = - source_id__h35516 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1551 ; - assign _dfoo1688 = - (source_id__h35516 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1620 ; - assign _dfoo1689 = - source_id__h35516 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1553 ; - assign _dfoo169 = - source_id__h62136 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo33 ; - assign _dfoo1690 = - (source_id__h35516 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1622 ; - assign _dfoo1691 = - source_id__h35516 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1555 ; - assign _dfoo1692 = - (source_id__h35516 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1624 ; - assign _dfoo1693 = - source_id__h35516 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1557 ; - assign _dfoo1694 = - (source_id__h35516 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1626 ; - assign _dfoo1695 = - source_id__h35516 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1559 ; - assign _dfoo1696 = - (source_id__h35516 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1628 ; - assign _dfoo1697 = - source_id__h35516 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1561 ; - assign _dfoo1698 = - (source_id__h35516 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1630 ; - assign _dfoo1699 = - source_id__h35516 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36726 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || - _dfoo1563 ; - assign _dfoo17 = - source_id__h64556 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo170 = - (source_id__h62136 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo102 ; - assign _dfoo1700 = - (source_id__h35516 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26923[6] : - _dfoo1632 ; - assign _dfoo1702 = - (source_id__h34306 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1634 ; - assign _dfoo1704 = - (source_id__h34306 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1636 ; - assign _dfoo1706 = - (source_id__h34306 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1638 ; - assign _dfoo1708 = - (source_id__h34306 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1640 ; - assign _dfoo171 = - source_id__h62136 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo35 ; - assign _dfoo1710 = - (source_id__h34306 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1642 ; - assign _dfoo1712 = - (source_id__h34306 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1644 ; - assign _dfoo1714 = - (source_id__h34306 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1646 ; - assign _dfoo1716 = - (source_id__h34306 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1648 ; - assign _dfoo1718 = - (source_id__h34306 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1650 ; - assign _dfoo172 = - (source_id__h62136 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo104 ; - assign _dfoo1720 = - (source_id__h34306 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1652 ; - assign _dfoo1722 = - (source_id__h34306 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1654 ; - assign _dfoo1724 = - (source_id__h34306 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1656 ; - assign _dfoo1726 = - (source_id__h34306 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1658 ; - assign _dfoo1728 = - (source_id__h34306 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1660 ; - assign _dfoo173 = - source_id__h62136 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo37 ; - assign _dfoo1730 = - (source_id__h34306 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1662 ; - assign _dfoo1732 = - (source_id__h34306 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1664 ; - assign _dfoo1734 = - (source_id__h34306 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1666 ; - assign _dfoo1736 = - (source_id__h34306 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1668 ; - assign _dfoo1738 = - (source_id__h34306 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1670 ; - assign _dfoo174 = - (source_id__h62136 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo106 ; - assign _dfoo1740 = - (source_id__h34306 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1672 ; - assign _dfoo1742 = - (source_id__h34306 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1674 ; - assign _dfoo1744 = - (source_id__h34306 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1676 ; - assign _dfoo1746 = - (source_id__h34306 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1678 ; - assign _dfoo1748 = - (source_id__h34306 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1680 ; - assign _dfoo175 = - source_id__h62136 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo39 ; - assign _dfoo1750 = - (source_id__h34306 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1682 ; - assign _dfoo1752 = - (source_id__h34306 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1684 ; - assign _dfoo1754 = - (source_id__h34306 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1686 ; - assign _dfoo1756 = - (source_id__h34306 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1688 ; - assign _dfoo1758 = - (source_id__h34306 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1690 ; - assign _dfoo176 = - (source_id__h62136 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo108 ; - assign _dfoo1760 = - (source_id__h34306 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1692 ; - assign _dfoo1762 = - (source_id__h34306 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1694 ; - assign _dfoo1764 = - (source_id__h34306 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1696 ; - assign _dfoo1766 = - (source_id__h34306 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1698 ; - assign _dfoo1768 = - (source_id__h34306 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26923[5] : - _dfoo1700 ; - assign _dfoo1769 = - source_id__h33096 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1633 ; - assign _dfoo177 = - source_id__h62136 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo41 ; - assign _dfoo1770 = - (source_id__h33096 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1702 ; - assign _dfoo1771 = - source_id__h33096 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1635 ; - assign _dfoo1772 = - (source_id__h33096 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1704 ; - assign _dfoo1773 = - source_id__h33096 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1637 ; - assign _dfoo1774 = - (source_id__h33096 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1706 ; - assign _dfoo1775 = - source_id__h33096 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1639 ; - assign _dfoo1776 = - (source_id__h33096 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1708 ; - assign _dfoo1777 = - source_id__h33096 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1641 ; - assign _dfoo1778 = - (source_id__h33096 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1710 ; - assign _dfoo1779 = - source_id__h33096 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1643 ; - assign _dfoo178 = - (source_id__h62136 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo110 ; - assign _dfoo1780 = - (source_id__h33096 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1712 ; - assign _dfoo1781 = - source_id__h33096 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1645 ; - assign _dfoo1782 = - (source_id__h33096 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1714 ; - assign _dfoo1783 = - source_id__h33096 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1647 ; - assign _dfoo1784 = - (source_id__h33096 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1716 ; - assign _dfoo1785 = - source_id__h33096 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1649 ; - assign _dfoo1786 = - (source_id__h33096 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1718 ; - assign _dfoo1787 = - source_id__h33096 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1651 ; - assign _dfoo1788 = - (source_id__h33096 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1720 ; - assign _dfoo1789 = - source_id__h33096 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1653 ; - assign _dfoo179 = - source_id__h62136 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo43 ; - assign _dfoo1790 = - (source_id__h33096 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1722 ; - assign _dfoo1791 = - source_id__h33096 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1655 ; - assign _dfoo1792 = - (source_id__h33096 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1724 ; - assign _dfoo1793 = - source_id__h33096 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1657 ; - assign _dfoo1794 = - (source_id__h33096 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1726 ; - assign _dfoo1795 = - source_id__h33096 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1659 ; - assign _dfoo1796 = - (source_id__h33096 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1728 ; - assign _dfoo1797 = - source_id__h33096 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1661 ; - assign _dfoo1798 = - (source_id__h33096 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1730 ; - assign _dfoo1799 = - source_id__h33096 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1663 ; - assign _dfoo18 = - (source_id__h64556 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo180 = - (source_id__h62136 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo112 ; - assign _dfoo1800 = - (source_id__h33096 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1732 ; - assign _dfoo1801 = - source_id__h33096 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1665 ; - assign _dfoo1802 = - (source_id__h33096 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1734 ; - assign _dfoo1803 = - source_id__h33096 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1667 ; - assign _dfoo1804 = - (source_id__h33096 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1736 ; - assign _dfoo1805 = - source_id__h33096 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1669 ; - assign _dfoo1806 = - (source_id__h33096 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1738 ; - assign _dfoo1807 = - source_id__h33096 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1671 ; - assign _dfoo1808 = - (source_id__h33096 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1740 ; - assign _dfoo1809 = - source_id__h33096 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1673 ; - assign _dfoo181 = - source_id__h62136 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo45 ; - assign _dfoo1810 = - (source_id__h33096 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1742 ; - assign _dfoo1811 = - source_id__h33096 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1675 ; - assign _dfoo1812 = - (source_id__h33096 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1744 ; - assign _dfoo1813 = - source_id__h33096 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1677 ; - assign _dfoo1814 = - (source_id__h33096 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1746 ; - assign _dfoo1815 = - source_id__h33096 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1679 ; - assign _dfoo1816 = - (source_id__h33096 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1748 ; - assign _dfoo1817 = - source_id__h33096 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1681 ; - assign _dfoo1818 = - (source_id__h33096 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1750 ; - assign _dfoo1819 = - source_id__h33096 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1683 ; - assign _dfoo182 = - (source_id__h62136 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo114 ; - assign _dfoo1820 = - (source_id__h33096 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1752 ; - assign _dfoo1821 = - source_id__h33096 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1685 ; - assign _dfoo1822 = - (source_id__h33096 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1754 ; - assign _dfoo1823 = - source_id__h33096 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1687 ; - assign _dfoo1824 = - (source_id__h33096 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1756 ; - assign _dfoo1825 = - source_id__h33096 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1689 ; - assign _dfoo1826 = - (source_id__h33096 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1758 ; - assign _dfoo1827 = - source_id__h33096 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1691 ; - assign _dfoo1828 = - (source_id__h33096 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1760 ; - assign _dfoo1829 = - source_id__h33096 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1693 ; - assign _dfoo183 = - source_id__h62136 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo47 ; - assign _dfoo1830 = - (source_id__h33096 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1762 ; - assign _dfoo1831 = - source_id__h33096 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1695 ; - assign _dfoo1832 = - (source_id__h33096 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1764 ; - assign _dfoo1833 = - source_id__h33096 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1697 ; - assign _dfoo1834 = - (source_id__h33096 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1766 ; - assign _dfoo1835 = - source_id__h33096 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34306 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || - _dfoo1699 ; - assign _dfoo1836 = - (source_id__h33096 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26923[4] : - _dfoo1768 ; - assign _dfoo1838 = - (source_id__h31886 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1770 ; - assign _dfoo184 = - (source_id__h62136 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo116 ; - assign _dfoo1840 = - (source_id__h31886 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1772 ; - assign _dfoo1842 = - (source_id__h31886 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1774 ; - assign _dfoo1844 = - (source_id__h31886 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1776 ; - assign _dfoo1846 = - (source_id__h31886 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1778 ; - assign _dfoo1848 = - (source_id__h31886 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1780 ; - assign _dfoo185 = - source_id__h62136 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo49 ; - assign _dfoo1850 = - (source_id__h31886 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1782 ; - assign _dfoo1852 = - (source_id__h31886 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1784 ; - assign _dfoo1854 = - (source_id__h31886 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1786 ; - assign _dfoo1856 = - (source_id__h31886 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1788 ; - assign _dfoo1858 = - (source_id__h31886 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1790 ; - assign _dfoo186 = - (source_id__h62136 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo118 ; - assign _dfoo1860 = - (source_id__h31886 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1792 ; - assign _dfoo1862 = - (source_id__h31886 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1794 ; - assign _dfoo1864 = - (source_id__h31886 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1796 ; - assign _dfoo1866 = - (source_id__h31886 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1798 ; - assign _dfoo1868 = - (source_id__h31886 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1800 ; - assign _dfoo187 = - source_id__h62136 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo51 ; - assign _dfoo1870 = - (source_id__h31886 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1802 ; - assign _dfoo1872 = - (source_id__h31886 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1804 ; - assign _dfoo1874 = - (source_id__h31886 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1806 ; - assign _dfoo1876 = - (source_id__h31886 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1808 ; - assign _dfoo1878 = - (source_id__h31886 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1810 ; - assign _dfoo188 = - (source_id__h62136 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo120 ; - assign _dfoo1880 = - (source_id__h31886 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1812 ; - assign _dfoo1882 = - (source_id__h31886 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1814 ; - assign _dfoo1884 = - (source_id__h31886 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1816 ; - assign _dfoo1886 = - (source_id__h31886 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1818 ; - assign _dfoo1888 = - (source_id__h31886 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1820 ; - assign _dfoo189 = - source_id__h62136 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo53 ; - assign _dfoo1890 = - (source_id__h31886 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1822 ; - assign _dfoo1892 = - (source_id__h31886 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1824 ; - assign _dfoo1894 = - (source_id__h31886 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1826 ; - assign _dfoo1896 = - (source_id__h31886 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1828 ; - assign _dfoo1898 = - (source_id__h31886 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1830 ; - assign _dfoo19 = - source_id__h64556 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo190 = - (source_id__h62136 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo122 ; - assign _dfoo1900 = - (source_id__h31886 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1832 ; - assign _dfoo1902 = - (source_id__h31886 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1834 ; - assign _dfoo1904 = - (source_id__h31886 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26923[3] : - _dfoo1836 ; - assign _dfoo1905 = - source_id__h30676 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1769 ; - assign _dfoo1906 = - (source_id__h30676 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1838 ; - assign _dfoo1907 = - source_id__h30676 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1771 ; - assign _dfoo1908 = - (source_id__h30676 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1840 ; - assign _dfoo1909 = - source_id__h30676 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1773 ; - assign _dfoo191 = - source_id__h62136 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo55 ; - assign _dfoo1910 = - (source_id__h30676 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1842 ; - assign _dfoo1911 = - source_id__h30676 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1775 ; - assign _dfoo1912 = - (source_id__h30676 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1844 ; - assign _dfoo1913 = - source_id__h30676 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1777 ; - assign _dfoo1914 = - (source_id__h30676 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1846 ; - assign _dfoo1915 = - source_id__h30676 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1779 ; - assign _dfoo1916 = - (source_id__h30676 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1848 ; - assign _dfoo1917 = - source_id__h30676 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1781 ; - assign _dfoo1918 = - (source_id__h30676 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1850 ; - assign _dfoo1919 = - source_id__h30676 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1783 ; - assign _dfoo192 = - (source_id__h62136 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo124 ; - assign _dfoo1920 = - (source_id__h30676 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1852 ; - assign _dfoo1921 = - source_id__h30676 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1785 ; - assign _dfoo1922 = - (source_id__h30676 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1854 ; - assign _dfoo1923 = - source_id__h30676 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1787 ; - assign _dfoo1924 = - (source_id__h30676 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1856 ; - assign _dfoo1925 = - source_id__h30676 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1789 ; - assign _dfoo1926 = - (source_id__h30676 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1858 ; - assign _dfoo1927 = - source_id__h30676 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1791 ; - assign _dfoo1928 = - (source_id__h30676 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1860 ; - assign _dfoo1929 = - source_id__h30676 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1793 ; - assign _dfoo193 = - source_id__h62136 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo57 ; - assign _dfoo1930 = - (source_id__h30676 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1862 ; - assign _dfoo1931 = - source_id__h30676 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1795 ; - assign _dfoo1932 = - (source_id__h30676 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1864 ; - assign _dfoo1933 = - source_id__h30676 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1797 ; - assign _dfoo1934 = - (source_id__h30676 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1866 ; - assign _dfoo1935 = - source_id__h30676 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1799 ; - assign _dfoo1936 = - (source_id__h30676 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1868 ; - assign _dfoo1937 = - source_id__h30676 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1801 ; - assign _dfoo1938 = - (source_id__h30676 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1870 ; - assign _dfoo1939 = - source_id__h30676 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1803 ; - assign _dfoo194 = - (source_id__h62136 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo126 ; - assign _dfoo1940 = - (source_id__h30676 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1872 ; - assign _dfoo1941 = - source_id__h30676 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1805 ; - assign _dfoo1942 = - (source_id__h30676 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1874 ; - assign _dfoo1943 = - source_id__h30676 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1807 ; - assign _dfoo1944 = - (source_id__h30676 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1876 ; - assign _dfoo1945 = - source_id__h30676 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1809 ; - assign _dfoo1946 = - (source_id__h30676 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1878 ; - assign _dfoo1947 = - source_id__h30676 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1811 ; - assign _dfoo1948 = - (source_id__h30676 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1880 ; - assign _dfoo1949 = - source_id__h30676 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1813 ; - assign _dfoo195 = - source_id__h62136 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo59 ; - assign _dfoo1950 = - (source_id__h30676 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1882 ; - assign _dfoo1951 = - source_id__h30676 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1815 ; - assign _dfoo1952 = - (source_id__h30676 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1884 ; - assign _dfoo1953 = - source_id__h30676 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1817 ; - assign _dfoo1954 = - (source_id__h30676 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1886 ; - assign _dfoo1955 = - source_id__h30676 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1819 ; - assign _dfoo1956 = - (source_id__h30676 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1888 ; - assign _dfoo1957 = - source_id__h30676 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1821 ; - assign _dfoo1958 = - (source_id__h30676 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1890 ; - assign _dfoo1959 = - source_id__h30676 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1823 ; - assign _dfoo196 = - (source_id__h62136 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo128 ; - assign _dfoo1960 = - (source_id__h30676 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1892 ; - assign _dfoo1961 = - source_id__h30676 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1825 ; - assign _dfoo1962 = - (source_id__h30676 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1894 ; - assign _dfoo1963 = - source_id__h30676 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1827 ; - assign _dfoo1964 = - (source_id__h30676 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1896 ; - assign _dfoo1965 = - source_id__h30676 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1829 ; - assign _dfoo1966 = - (source_id__h30676 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1898 ; - assign _dfoo1967 = - source_id__h30676 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1831 ; - assign _dfoo1968 = - (source_id__h30676 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1900 ; - assign _dfoo1969 = - source_id__h30676 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1833 ; - assign _dfoo197 = - source_id__h62136 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo61 ; - assign _dfoo1970 = - (source_id__h30676 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1902 ; - assign _dfoo1971 = - source_id__h30676 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31886 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || - _dfoo1835 ; - assign _dfoo1972 = - (source_id__h30676 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26923[2] : - _dfoo1904 ; - assign _dfoo1974 = - (source_id__h29466 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1906 ; - assign _dfoo1976 = - (source_id__h29466 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1908 ; - assign _dfoo1978 = - (source_id__h29466 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1910 ; - assign _dfoo198 = - (source_id__h62136 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo130 ; - assign _dfoo1980 = - (source_id__h29466 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1912 ; - assign _dfoo1982 = - (source_id__h29466 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1914 ; - assign _dfoo1984 = - (source_id__h29466 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1916 ; - assign _dfoo1986 = - (source_id__h29466 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1918 ; - assign _dfoo1988 = - (source_id__h29466 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1920 ; - assign _dfoo199 = - source_id__h62136 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo63 ; - assign _dfoo1990 = - (source_id__h29466 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1922 ; - assign _dfoo1992 = - (source_id__h29466 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1924 ; - assign _dfoo1994 = - (source_id__h29466 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1926 ; - assign _dfoo1996 = - (source_id__h29466 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1928 ; - assign _dfoo1998 = - (source_id__h29466 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1930 ; - assign _dfoo2 = - (source_id__h64556 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo20 = - (source_id__h64556 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo200 = - (source_id__h62136 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo132 ; - assign _dfoo2000 = - (source_id__h29466 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1932 ; - assign _dfoo2002 = - (source_id__h29466 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1934 ; - assign _dfoo2004 = - (source_id__h29466 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1936 ; - assign _dfoo2006 = - (source_id__h29466 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1938 ; - assign _dfoo2008 = - (source_id__h29466 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1940 ; - assign _dfoo201 = - source_id__h62136 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo65 ; - assign _dfoo2010 = - (source_id__h29466 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1942 ; - assign _dfoo2012 = - (source_id__h29466 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1944 ; - assign _dfoo2014 = - (source_id__h29466 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1946 ; - assign _dfoo2016 = - (source_id__h29466 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1948 ; - assign _dfoo2018 = - (source_id__h29466 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1950 ; - assign _dfoo202 = - (source_id__h62136 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo134 ; - assign _dfoo2020 = - (source_id__h29466 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1952 ; - assign _dfoo2022 = - (source_id__h29466 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1954 ; - assign _dfoo2024 = - (source_id__h29466 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1956 ; - assign _dfoo2026 = - (source_id__h29466 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1958 ; - assign _dfoo2028 = - (source_id__h29466 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1960 ; - assign _dfoo203 = - source_id__h62136 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63346 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || - _dfoo67 ; - assign _dfoo2030 = - (source_id__h29466 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1962 ; - assign _dfoo2032 = - (source_id__h29466 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1964 ; - assign _dfoo2034 = - (source_id__h29466 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1966 ; - assign _dfoo2036 = - (source_id__h29466 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1968 ; - assign _dfoo2038 = - (source_id__h29466 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1970 ; - assign _dfoo204 = - (source_id__h62136 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26923[28] : - _dfoo136 ; - assign _dfoo2040 = - (source_id__h29466 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26923[1] : - _dfoo1972 ; - assign _dfoo2041 = - source_id_base__h28139 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1905 ; - assign _dfoo2043 = - source_id_base__h28139 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1907 ; - assign _dfoo2045 = - source_id_base__h28139 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1909 ; - assign _dfoo2047 = - source_id_base__h28139 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1911 ; - assign _dfoo2049 = - source_id_base__h28139 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1913 ; - assign _dfoo2051 = - source_id_base__h28139 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1915 ; - assign _dfoo2053 = - source_id_base__h28139 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1917 ; - assign _dfoo2055 = - source_id_base__h28139 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1919 ; - assign _dfoo2057 = - source_id_base__h28139 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1921 ; - assign _dfoo2059 = - source_id_base__h28139 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1923 ; - assign _dfoo206 = - (source_id__h60926 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo138 ; - assign _dfoo2061 = - source_id_base__h28139 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1925 ; - assign _dfoo2063 = - source_id_base__h28139 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1927 ; - assign _dfoo2065 = - source_id_base__h28139 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1929 ; - assign _dfoo2067 = - source_id_base__h28139 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1931 ; - assign _dfoo2069 = - source_id_base__h28139 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1933 ; - assign _dfoo2071 = - source_id_base__h28139 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1935 ; - assign _dfoo2073 = - source_id_base__h28139 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29466 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1937 ; - assign _dfoo2075 = - source_id_base__h28139 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1939 ; - assign _dfoo2077 = - source_id_base__h28139 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1941 ; - assign _dfoo2079 = - source_id_base__h28139 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1943 ; - assign _dfoo208 = - (source_id__h60926 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo140 ; - assign _dfoo2081 = - source_id_base__h28139 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1945 ; - assign _dfoo2083 = - source_id_base__h28139 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1947 ; - assign _dfoo2085 = - source_id_base__h28139 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1949 ; - assign _dfoo2087 = - source_id_base__h28139 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1951 ; - assign _dfoo2089 = - source_id_base__h28139 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1953 ; - assign _dfoo2091 = - source_id_base__h28139 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1955 ; - assign _dfoo2093 = - source_id_base__h28139 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1957 ; - assign _dfoo2095 = - source_id_base__h28139 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1959 ; - assign _dfoo2097 = - source_id_base__h28139 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1961 ; - assign _dfoo2099 = - source_id_base__h28139 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1963 ; - assign _dfoo21 = - source_id__h64556 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo210 = - (source_id__h60926 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo142 ; - assign _dfoo2101 = - source_id_base__h28139 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1965 ; - assign _dfoo2103 = - source_id_base__h28139 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1967 ; - assign _dfoo2105 = - source_id_base__h28139 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1969 ; - assign _dfoo2107 = - source_id_base__h28139 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29466 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || - _dfoo1971 ; - assign _dfoo212 = - (source_id__h60926 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo144 ; - assign _dfoo214 = - (source_id__h60926 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo146 ; - assign _dfoo216 = - (source_id__h60926 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo148 ; - assign _dfoo218 = - (source_id__h60926 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo150 ; - assign _dfoo22 = - (source_id__h64556 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo220 = - (source_id__h60926 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo152 ; - assign _dfoo222 = - (source_id__h60926 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo154 ; - assign _dfoo224 = - (source_id__h60926 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo156 ; - assign _dfoo226 = - (source_id__h60926 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo158 ; - assign _dfoo228 = - (source_id__h60926 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo160 ; - assign _dfoo23 = - source_id__h64556 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo230 = - (source_id__h60926 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo162 ; - assign _dfoo232 = - (source_id__h60926 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo164 ; - assign _dfoo234 = - (source_id__h60926 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo166 ; - assign _dfoo236 = - (source_id__h60926 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo168 ; - assign _dfoo238 = - (source_id__h60926 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo170 ; - assign _dfoo24 = - (source_id__h64556 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo240 = - (source_id__h60926 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo172 ; - assign _dfoo242 = - (source_id__h60926 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo174 ; - assign _dfoo244 = - (source_id__h60926 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo176 ; - assign _dfoo246 = - (source_id__h60926 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo178 ; - assign _dfoo248 = - (source_id__h60926 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo180 ; - assign _dfoo25 = - source_id__h64556 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo250 = - (source_id__h60926 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo182 ; - assign _dfoo252 = - (source_id__h60926 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo184 ; - assign _dfoo254 = - (source_id__h60926 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo186 ; - assign _dfoo256 = - (source_id__h60926 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo188 ; - assign _dfoo258 = - (source_id__h60926 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo190 ; - assign _dfoo26 = - (source_id__h64556 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo260 = - (source_id__h60926 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo192 ; - assign _dfoo262 = - (source_id__h60926 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo194 ; - assign _dfoo264 = - (source_id__h60926 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo196 ; - assign _dfoo266 = - (source_id__h60926 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo198 ; - assign _dfoo268 = - (source_id__h60926 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo200 ; - assign _dfoo27 = - source_id__h64556 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo270 = - (source_id__h60926 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo202 ; - assign _dfoo272 = - (source_id__h60926 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26923[27] : - _dfoo204 ; - assign _dfoo273 = - source_id__h59716 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo137 ; - assign _dfoo274 = - (source_id__h59716 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo206 ; - assign _dfoo275 = - source_id__h59716 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo139 ; - assign _dfoo276 = - (source_id__h59716 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo208 ; - assign _dfoo277 = - source_id__h59716 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo141 ; - assign _dfoo278 = - (source_id__h59716 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo210 ; - assign _dfoo279 = - source_id__h59716 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo143 ; - assign _dfoo28 = - (source_id__h64556 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo280 = - (source_id__h59716 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo212 ; - assign _dfoo281 = - source_id__h59716 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo145 ; - assign _dfoo282 = - (source_id__h59716 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo214 ; - assign _dfoo283 = - source_id__h59716 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo147 ; - assign _dfoo284 = - (source_id__h59716 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo216 ; - assign _dfoo285 = - source_id__h59716 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo149 ; - assign _dfoo286 = - (source_id__h59716 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo218 ; - assign _dfoo287 = - source_id__h59716 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo151 ; - assign _dfoo288 = - (source_id__h59716 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo220 ; - assign _dfoo289 = - source_id__h59716 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo153 ; - assign _dfoo29 = - source_id__h64556 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo290 = - (source_id__h59716 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo222 ; - assign _dfoo291 = - source_id__h59716 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo155 ; - assign _dfoo292 = - (source_id__h59716 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo224 ; - assign _dfoo293 = - source_id__h59716 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo157 ; - assign _dfoo294 = - (source_id__h59716 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo226 ; - assign _dfoo295 = - source_id__h59716 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo159 ; - assign _dfoo296 = - (source_id__h59716 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo228 ; - assign _dfoo297 = - source_id__h59716 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo161 ; - assign _dfoo298 = - (source_id__h59716 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo230 ; - assign _dfoo299 = - source_id__h59716 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo163 ; - assign _dfoo3 = - source_id__h64556 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo30 = - (source_id__h64556 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo300 = - (source_id__h59716 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo232 ; - assign _dfoo301 = - source_id__h59716 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo165 ; - assign _dfoo302 = - (source_id__h59716 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo234 ; - assign _dfoo303 = - source_id__h59716 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo167 ; - assign _dfoo304 = - (source_id__h59716 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo236 ; - assign _dfoo305 = - source_id__h59716 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo169 ; - assign _dfoo306 = - (source_id__h59716 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo238 ; - assign _dfoo307 = - source_id__h59716 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo171 ; - assign _dfoo308 = - (source_id__h59716 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo240 ; - assign _dfoo309 = - source_id__h59716 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo173 ; - assign _dfoo31 = - source_id__h64556 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo310 = - (source_id__h59716 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo242 ; - assign _dfoo311 = - source_id__h59716 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo175 ; - assign _dfoo312 = - (source_id__h59716 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo244 ; - assign _dfoo313 = - source_id__h59716 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo177 ; - assign _dfoo314 = - (source_id__h59716 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo246 ; - assign _dfoo315 = - source_id__h59716 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo179 ; - assign _dfoo316 = - (source_id__h59716 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo248 ; - assign _dfoo317 = - source_id__h59716 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo181 ; - assign _dfoo318 = - (source_id__h59716 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo250 ; - assign _dfoo319 = - source_id__h59716 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo183 ; - assign _dfoo32 = - (source_id__h64556 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo320 = - (source_id__h59716 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo252 ; - assign _dfoo321 = - source_id__h59716 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo185 ; - assign _dfoo322 = - (source_id__h59716 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo254 ; - assign _dfoo323 = - source_id__h59716 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo187 ; - assign _dfoo324 = - (source_id__h59716 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo256 ; - assign _dfoo325 = - source_id__h59716 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo189 ; - assign _dfoo326 = - (source_id__h59716 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo258 ; - assign _dfoo327 = - source_id__h59716 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo191 ; - assign _dfoo328 = - (source_id__h59716 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo260 ; - assign _dfoo329 = - source_id__h59716 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo193 ; - assign _dfoo33 = - source_id__h64556 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo330 = - (source_id__h59716 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo262 ; - assign _dfoo331 = - source_id__h59716 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo195 ; - assign _dfoo332 = - (source_id__h59716 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo264 ; - assign _dfoo333 = - source_id__h59716 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo197 ; - assign _dfoo334 = - (source_id__h59716 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo266 ; - assign _dfoo335 = - source_id__h59716 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo199 ; - assign _dfoo336 = - (source_id__h59716 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo268 ; - assign _dfoo337 = - source_id__h59716 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo201 ; - assign _dfoo338 = - (source_id__h59716 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo270 ; - assign _dfoo339 = - source_id__h59716 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60926 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || - _dfoo203 ; - assign _dfoo34 = - (source_id__h64556 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo340 = - (source_id__h59716 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26923[26] : - _dfoo272 ; - assign _dfoo342 = - (source_id__h58506 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo274 ; - assign _dfoo344 = - (source_id__h58506 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo276 ; - assign _dfoo346 = - (source_id__h58506 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo278 ; - assign _dfoo348 = - (source_id__h58506 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo280 ; - assign _dfoo35 = - source_id__h64556 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo350 = - (source_id__h58506 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo282 ; - assign _dfoo352 = - (source_id__h58506 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo284 ; - assign _dfoo354 = - (source_id__h58506 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo286 ; - assign _dfoo356 = - (source_id__h58506 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo288 ; - assign _dfoo358 = - (source_id__h58506 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo290 ; - assign _dfoo36 = - (source_id__h64556 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo360 = - (source_id__h58506 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo292 ; - assign _dfoo362 = - (source_id__h58506 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo294 ; - assign _dfoo364 = - (source_id__h58506 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo296 ; - assign _dfoo366 = - (source_id__h58506 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo298 ; - assign _dfoo368 = - (source_id__h58506 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo300 ; - assign _dfoo37 = - source_id__h64556 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo370 = - (source_id__h58506 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo302 ; - assign _dfoo372 = - (source_id__h58506 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo304 ; - assign _dfoo374 = - (source_id__h58506 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo306 ; - assign _dfoo376 = - (source_id__h58506 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo308 ; - assign _dfoo378 = - (source_id__h58506 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo310 ; - assign _dfoo38 = - (source_id__h64556 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo380 = - (source_id__h58506 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo312 ; - assign _dfoo382 = - (source_id__h58506 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo314 ; - assign _dfoo384 = - (source_id__h58506 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo316 ; - assign _dfoo386 = - (source_id__h58506 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo318 ; - assign _dfoo388 = - (source_id__h58506 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo320 ; - assign _dfoo39 = - source_id__h64556 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo390 = - (source_id__h58506 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo322 ; - assign _dfoo392 = - (source_id__h58506 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo324 ; - assign _dfoo394 = - (source_id__h58506 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo326 ; - assign _dfoo396 = - (source_id__h58506 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo328 ; - assign _dfoo398 = - (source_id__h58506 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo330 ; - assign _dfoo4 = - (source_id__h64556 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo40 = - (source_id__h64556 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo400 = - (source_id__h58506 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo332 ; - assign _dfoo402 = - (source_id__h58506 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo334 ; - assign _dfoo404 = - (source_id__h58506 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo336 ; - assign _dfoo406 = - (source_id__h58506 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo338 ; - assign _dfoo408 = - (source_id__h58506 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26923[25] : - _dfoo340 ; - assign _dfoo409 = - source_id__h57296 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo273 ; - assign _dfoo41 = - source_id__h64556 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo410 = - (source_id__h57296 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo342 ; - assign _dfoo411 = - source_id__h57296 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo275 ; - assign _dfoo412 = - (source_id__h57296 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo344 ; - assign _dfoo413 = - source_id__h57296 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo277 ; - assign _dfoo414 = - (source_id__h57296 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo346 ; - assign _dfoo415 = - source_id__h57296 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo279 ; - assign _dfoo416 = - (source_id__h57296 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo348 ; - assign _dfoo417 = - source_id__h57296 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo281 ; - assign _dfoo418 = - (source_id__h57296 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo350 ; - assign _dfoo419 = - source_id__h57296 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo283 ; - assign _dfoo42 = - (source_id__h64556 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo420 = - (source_id__h57296 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo352 ; - assign _dfoo421 = - source_id__h57296 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo285 ; - assign _dfoo422 = - (source_id__h57296 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo354 ; - assign _dfoo423 = - source_id__h57296 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo287 ; - assign _dfoo424 = - (source_id__h57296 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo356 ; - assign _dfoo425 = - source_id__h57296 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo289 ; - assign _dfoo426 = - (source_id__h57296 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo358 ; - assign _dfoo427 = - source_id__h57296 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo291 ; - assign _dfoo428 = - (source_id__h57296 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo360 ; - assign _dfoo429 = - source_id__h57296 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo293 ; - assign _dfoo43 = - source_id__h64556 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo430 = - (source_id__h57296 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo362 ; - assign _dfoo431 = - source_id__h57296 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo295 ; - assign _dfoo432 = - (source_id__h57296 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo364 ; - assign _dfoo433 = - source_id__h57296 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo297 ; - assign _dfoo434 = - (source_id__h57296 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo366 ; - assign _dfoo435 = - source_id__h57296 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo299 ; - assign _dfoo436 = - (source_id__h57296 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo368 ; - assign _dfoo437 = - source_id__h57296 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo301 ; - assign _dfoo438 = - (source_id__h57296 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo370 ; - assign _dfoo439 = - source_id__h57296 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo303 ; - assign _dfoo44 = - (source_id__h64556 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo440 = - (source_id__h57296 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo372 ; - assign _dfoo441 = - source_id__h57296 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo305 ; - assign _dfoo442 = - (source_id__h57296 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo374 ; - assign _dfoo443 = - source_id__h57296 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo307 ; - assign _dfoo444 = - (source_id__h57296 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo376 ; - assign _dfoo445 = - source_id__h57296 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo309 ; - assign _dfoo446 = - (source_id__h57296 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo378 ; - assign _dfoo447 = - source_id__h57296 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo311 ; - assign _dfoo448 = - (source_id__h57296 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo380 ; - assign _dfoo449 = - source_id__h57296 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo313 ; - assign _dfoo45 = - source_id__h64556 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo450 = - (source_id__h57296 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo382 ; - assign _dfoo451 = - source_id__h57296 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo315 ; - assign _dfoo452 = - (source_id__h57296 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo384 ; - assign _dfoo453 = - source_id__h57296 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo317 ; - assign _dfoo454 = - (source_id__h57296 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo386 ; - assign _dfoo455 = - source_id__h57296 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo319 ; - assign _dfoo456 = - (source_id__h57296 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo388 ; - assign _dfoo457 = - source_id__h57296 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo321 ; - assign _dfoo458 = - (source_id__h57296 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo390 ; - assign _dfoo459 = - source_id__h57296 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo323 ; - assign _dfoo46 = - (source_id__h64556 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo460 = - (source_id__h57296 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo392 ; - assign _dfoo461 = - source_id__h57296 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo325 ; - assign _dfoo462 = - (source_id__h57296 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo394 ; - assign _dfoo463 = - source_id__h57296 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo327 ; - assign _dfoo464 = - (source_id__h57296 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo396 ; - assign _dfoo465 = - source_id__h57296 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo329 ; - assign _dfoo466 = - (source_id__h57296 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo398 ; - assign _dfoo467 = - source_id__h57296 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo331 ; - assign _dfoo468 = - (source_id__h57296 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo400 ; - assign _dfoo469 = - source_id__h57296 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo333 ; - assign _dfoo47 = - source_id__h64556 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo470 = - (source_id__h57296 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo402 ; - assign _dfoo471 = - source_id__h57296 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo335 ; - assign _dfoo472 = - (source_id__h57296 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo404 ; - assign _dfoo473 = - source_id__h57296 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo337 ; - assign _dfoo474 = - (source_id__h57296 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo406 ; - assign _dfoo475 = - source_id__h57296 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58506 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || - _dfoo339 ; - assign _dfoo476 = - (source_id__h57296 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26923[24] : - _dfoo408 ; - assign _dfoo478 = - (source_id__h56086 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo410 ; - assign _dfoo48 = - (source_id__h64556 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo480 = - (source_id__h56086 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo412 ; - assign _dfoo482 = - (source_id__h56086 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo414 ; - assign _dfoo484 = - (source_id__h56086 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo416 ; - assign _dfoo486 = - (source_id__h56086 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo418 ; - assign _dfoo488 = - (source_id__h56086 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo420 ; - assign _dfoo49 = - source_id__h64556 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo490 = - (source_id__h56086 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo422 ; - assign _dfoo492 = - (source_id__h56086 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo424 ; - assign _dfoo494 = - (source_id__h56086 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo426 ; - assign _dfoo496 = - (source_id__h56086 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo428 ; - assign _dfoo498 = - (source_id__h56086 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo430 ; - assign _dfoo5 = - source_id__h64556 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo50 = - (source_id__h64556 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo500 = - (source_id__h56086 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo432 ; - assign _dfoo502 = - (source_id__h56086 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo434 ; - assign _dfoo504 = - (source_id__h56086 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo436 ; - assign _dfoo506 = - (source_id__h56086 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo438 ; - assign _dfoo508 = - (source_id__h56086 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo440 ; - assign _dfoo51 = - source_id__h64556 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo510 = - (source_id__h56086 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo442 ; - assign _dfoo512 = - (source_id__h56086 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo444 ; - assign _dfoo514 = - (source_id__h56086 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo446 ; - assign _dfoo516 = - (source_id__h56086 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo448 ; - assign _dfoo518 = - (source_id__h56086 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo450 ; - assign _dfoo52 = - (source_id__h64556 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo520 = - (source_id__h56086 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo452 ; - assign _dfoo522 = - (source_id__h56086 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo454 ; - assign _dfoo524 = - (source_id__h56086 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo456 ; - assign _dfoo526 = - (source_id__h56086 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo458 ; - assign _dfoo528 = - (source_id__h56086 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo460 ; - assign _dfoo53 = - source_id__h64556 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo530 = - (source_id__h56086 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo462 ; - assign _dfoo532 = - (source_id__h56086 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo464 ; - assign _dfoo534 = - (source_id__h56086 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo466 ; - assign _dfoo536 = - (source_id__h56086 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo468 ; - assign _dfoo538 = - (source_id__h56086 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo470 ; - assign _dfoo54 = - (source_id__h64556 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo540 = - (source_id__h56086 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo472 ; - assign _dfoo542 = - (source_id__h56086 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo474 ; - assign _dfoo544 = - (source_id__h56086 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26923[23] : - _dfoo476 ; - assign _dfoo545 = - source_id__h54876 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo409 ; - assign _dfoo546 = - (source_id__h54876 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo478 ; - assign _dfoo547 = - source_id__h54876 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo411 ; - assign _dfoo548 = - (source_id__h54876 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo480 ; - assign _dfoo549 = - source_id__h54876 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo413 ; - assign _dfoo55 = - source_id__h64556 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo550 = - (source_id__h54876 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo482 ; - assign _dfoo551 = - source_id__h54876 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo415 ; - assign _dfoo552 = - (source_id__h54876 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo484 ; - assign _dfoo553 = - source_id__h54876 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo417 ; - assign _dfoo554 = - (source_id__h54876 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo486 ; - assign _dfoo555 = - source_id__h54876 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo419 ; - assign _dfoo556 = - (source_id__h54876 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo488 ; - assign _dfoo557 = - source_id__h54876 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo421 ; - assign _dfoo558 = - (source_id__h54876 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo490 ; - assign _dfoo559 = - source_id__h54876 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo423 ; - assign _dfoo56 = - (source_id__h64556 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo560 = - (source_id__h54876 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo492 ; - assign _dfoo561 = - source_id__h54876 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo425 ; - assign _dfoo562 = - (source_id__h54876 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo494 ; - assign _dfoo563 = - source_id__h54876 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo427 ; - assign _dfoo564 = - (source_id__h54876 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo496 ; - assign _dfoo565 = - source_id__h54876 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo429 ; - assign _dfoo566 = - (source_id__h54876 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo498 ; - assign _dfoo567 = - source_id__h54876 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo431 ; - assign _dfoo568 = - (source_id__h54876 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo500 ; - assign _dfoo569 = - source_id__h54876 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo433 ; - assign _dfoo57 = - source_id__h64556 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo570 = - (source_id__h54876 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo502 ; - assign _dfoo571 = - source_id__h54876 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo435 ; - assign _dfoo572 = - (source_id__h54876 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo504 ; - assign _dfoo573 = - source_id__h54876 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo437 ; - assign _dfoo574 = - (source_id__h54876 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo506 ; - assign _dfoo575 = - source_id__h54876 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo439 ; - assign _dfoo576 = - (source_id__h54876 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo508 ; - assign _dfoo577 = - source_id__h54876 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo441 ; - assign _dfoo578 = - (source_id__h54876 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo510 ; - assign _dfoo579 = - source_id__h54876 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo443 ; - assign _dfoo58 = - (source_id__h64556 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo580 = - (source_id__h54876 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo512 ; - assign _dfoo581 = - source_id__h54876 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo445 ; - assign _dfoo582 = - (source_id__h54876 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo514 ; - assign _dfoo583 = - source_id__h54876 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo447 ; - assign _dfoo584 = - (source_id__h54876 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo516 ; - assign _dfoo585 = - source_id__h54876 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo449 ; - assign _dfoo586 = - (source_id__h54876 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo518 ; - assign _dfoo587 = - source_id__h54876 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo451 ; - assign _dfoo588 = - (source_id__h54876 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo520 ; - assign _dfoo589 = - source_id__h54876 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo453 ; - assign _dfoo59 = - source_id__h64556 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo590 = - (source_id__h54876 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo522 ; - assign _dfoo591 = - source_id__h54876 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo455 ; - assign _dfoo592 = - (source_id__h54876 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo524 ; - assign _dfoo593 = - source_id__h54876 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo457 ; - assign _dfoo594 = - (source_id__h54876 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo526 ; - assign _dfoo595 = - source_id__h54876 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo459 ; - assign _dfoo596 = - (source_id__h54876 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo528 ; - assign _dfoo597 = - source_id__h54876 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo461 ; - assign _dfoo598 = - (source_id__h54876 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo530 ; - assign _dfoo599 = - source_id__h54876 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo463 ; - assign _dfoo6 = - (source_id__h64556 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo60 = - (source_id__h64556 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo600 = - (source_id__h54876 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo532 ; - assign _dfoo601 = - source_id__h54876 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo465 ; - assign _dfoo602 = - (source_id__h54876 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo534 ; - assign _dfoo603 = - source_id__h54876 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo467 ; - assign _dfoo604 = - (source_id__h54876 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo536 ; - assign _dfoo605 = - source_id__h54876 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo469 ; - assign _dfoo606 = - (source_id__h54876 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo538 ; - assign _dfoo607 = - source_id__h54876 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo471 ; - assign _dfoo608 = - (source_id__h54876 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo540 ; - assign _dfoo609 = - source_id__h54876 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo473 ; - assign _dfoo61 = - source_id__h64556 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo610 = - (source_id__h54876 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo542 ; - assign _dfoo611 = - source_id__h54876 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56086 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || - _dfoo475 ; - assign _dfoo612 = - (source_id__h54876 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26923[22] : - _dfoo544 ; - assign _dfoo614 = - (source_id__h53666 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo546 ; - assign _dfoo616 = - (source_id__h53666 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo548 ; - assign _dfoo618 = - (source_id__h53666 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo550 ; - assign _dfoo62 = - (source_id__h64556 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo620 = - (source_id__h53666 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo552 ; - assign _dfoo622 = - (source_id__h53666 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo554 ; - assign _dfoo624 = - (source_id__h53666 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo556 ; - assign _dfoo626 = - (source_id__h53666 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo558 ; - assign _dfoo628 = - (source_id__h53666 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo560 ; - assign _dfoo63 = - source_id__h64556 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo630 = - (source_id__h53666 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo562 ; - assign _dfoo632 = - (source_id__h53666 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo564 ; - assign _dfoo634 = - (source_id__h53666 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo566 ; - assign _dfoo636 = - (source_id__h53666 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo568 ; - assign _dfoo638 = - (source_id__h53666 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo570 ; - assign _dfoo64 = - (source_id__h64556 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo640 = - (source_id__h53666 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo572 ; - assign _dfoo642 = - (source_id__h53666 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo574 ; - assign _dfoo644 = - (source_id__h53666 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo576 ; - assign _dfoo646 = - (source_id__h53666 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo578 ; - assign _dfoo648 = - (source_id__h53666 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo580 ; - assign _dfoo65 = - source_id__h64556 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo650 = - (source_id__h53666 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo582 ; - assign _dfoo652 = - (source_id__h53666 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo584 ; - assign _dfoo654 = - (source_id__h53666 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo586 ; - assign _dfoo656 = - (source_id__h53666 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo588 ; - assign _dfoo658 = - (source_id__h53666 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo590 ; - assign _dfoo66 = - (source_id__h64556 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo660 = - (source_id__h53666 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo592 ; - assign _dfoo662 = - (source_id__h53666 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo594 ; - assign _dfoo664 = - (source_id__h53666 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo596 ; - assign _dfoo666 = - (source_id__h53666 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo598 ; - assign _dfoo668 = - (source_id__h53666 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo600 ; - assign _dfoo67 = - source_id__h64556 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo670 = - (source_id__h53666 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo602 ; - assign _dfoo672 = - (source_id__h53666 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo604 ; - assign _dfoo674 = - (source_id__h53666 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo606 ; - assign _dfoo676 = - (source_id__h53666 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo608 ; - assign _dfoo678 = - (source_id__h53666 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo610 ; - assign _dfoo68 = - (source_id__h64556 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo680 = - (source_id__h53666 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26923[21] : - _dfoo612 ; - assign _dfoo681 = - source_id__h52456 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo545 ; - assign _dfoo682 = - (source_id__h52456 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo614 ; - assign _dfoo683 = - source_id__h52456 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo547 ; - assign _dfoo684 = - (source_id__h52456 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo616 ; - assign _dfoo685 = - source_id__h52456 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo549 ; - assign _dfoo686 = - (source_id__h52456 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo618 ; - assign _dfoo687 = - source_id__h52456 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo551 ; - assign _dfoo688 = - (source_id__h52456 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo620 ; - assign _dfoo689 = - source_id__h52456 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo553 ; - assign _dfoo690 = - (source_id__h52456 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo622 ; - assign _dfoo691 = - source_id__h52456 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo555 ; - assign _dfoo692 = - (source_id__h52456 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo624 ; - assign _dfoo693 = - source_id__h52456 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo557 ; - assign _dfoo694 = - (source_id__h52456 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo626 ; - assign _dfoo695 = - source_id__h52456 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo559 ; - assign _dfoo696 = - (source_id__h52456 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo628 ; - assign _dfoo697 = - source_id__h52456 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo561 ; - assign _dfoo698 = - (source_id__h52456 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo630 ; - assign _dfoo699 = - source_id__h52456 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo563 ; - assign _dfoo7 = - source_id__h64556 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo70 = - (source_id__h63346 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo2 ; - assign _dfoo700 = - (source_id__h52456 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo632 ; - assign _dfoo701 = - source_id__h52456 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo565 ; - assign _dfoo702 = - (source_id__h52456 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo634 ; - assign _dfoo703 = - source_id__h52456 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo567 ; - assign _dfoo704 = - (source_id__h52456 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo636 ; - assign _dfoo705 = - source_id__h52456 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo569 ; - assign _dfoo706 = - (source_id__h52456 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo638 ; - assign _dfoo707 = - source_id__h52456 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo571 ; - assign _dfoo708 = - (source_id__h52456 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo640 ; - assign _dfoo709 = - source_id__h52456 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo573 ; - assign _dfoo710 = - (source_id__h52456 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo642 ; - assign _dfoo711 = - source_id__h52456 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo575 ; - assign _dfoo712 = - (source_id__h52456 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo644 ; - assign _dfoo713 = - source_id__h52456 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo577 ; - assign _dfoo714 = - (source_id__h52456 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo646 ; - assign _dfoo715 = - source_id__h52456 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo579 ; - assign _dfoo716 = - (source_id__h52456 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo648 ; - assign _dfoo717 = - source_id__h52456 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo581 ; - assign _dfoo718 = - (source_id__h52456 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo650 ; - assign _dfoo719 = - source_id__h52456 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo583 ; - assign _dfoo72 = - (source_id__h63346 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo4 ; - assign _dfoo720 = - (source_id__h52456 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo652 ; - assign _dfoo721 = - source_id__h52456 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo585 ; - assign _dfoo722 = - (source_id__h52456 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo654 ; - assign _dfoo723 = - source_id__h52456 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo587 ; - assign _dfoo724 = - (source_id__h52456 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo656 ; - assign _dfoo725 = - source_id__h52456 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo589 ; - assign _dfoo726 = - (source_id__h52456 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo658 ; - assign _dfoo727 = - source_id__h52456 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo591 ; - assign _dfoo728 = - (source_id__h52456 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo660 ; - assign _dfoo729 = - source_id__h52456 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo593 ; - assign _dfoo730 = - (source_id__h52456 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo662 ; - assign _dfoo731 = - source_id__h52456 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo595 ; - assign _dfoo732 = - (source_id__h52456 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo664 ; - assign _dfoo733 = - source_id__h52456 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo597 ; - assign _dfoo734 = - (source_id__h52456 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo666 ; - assign _dfoo735 = - source_id__h52456 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo599 ; - assign _dfoo736 = - (source_id__h52456 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo668 ; - assign _dfoo737 = - source_id__h52456 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo601 ; - assign _dfoo738 = - (source_id__h52456 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo670 ; - assign _dfoo739 = - source_id__h52456 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo603 ; - assign _dfoo74 = - (source_id__h63346 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo6 ; - assign _dfoo740 = - (source_id__h52456 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo672 ; - assign _dfoo741 = - source_id__h52456 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo605 ; - assign _dfoo742 = - (source_id__h52456 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo674 ; - assign _dfoo743 = - source_id__h52456 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo607 ; - assign _dfoo744 = - (source_id__h52456 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo676 ; - assign _dfoo745 = - source_id__h52456 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo609 ; - assign _dfoo746 = - (source_id__h52456 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo678 ; - assign _dfoo747 = - source_id__h52456 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53666 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || - _dfoo611 ; - assign _dfoo748 = - (source_id__h52456 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26923[20] : - _dfoo680 ; - assign _dfoo750 = - (source_id__h51246 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo682 ; - assign _dfoo752 = - (source_id__h51246 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo684 ; - assign _dfoo754 = - (source_id__h51246 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo686 ; - assign _dfoo756 = - (source_id__h51246 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo688 ; - assign _dfoo758 = - (source_id__h51246 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo690 ; - assign _dfoo76 = - (source_id__h63346 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo8 ; - assign _dfoo760 = - (source_id__h51246 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo692 ; - assign _dfoo762 = - (source_id__h51246 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo694 ; - assign _dfoo764 = - (source_id__h51246 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo696 ; - assign _dfoo766 = - (source_id__h51246 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo698 ; - assign _dfoo768 = - (source_id__h51246 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo700 ; - assign _dfoo770 = - (source_id__h51246 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo702 ; - assign _dfoo772 = - (source_id__h51246 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo704 ; - assign _dfoo774 = - (source_id__h51246 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo706 ; - assign _dfoo776 = - (source_id__h51246 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo708 ; - assign _dfoo778 = - (source_id__h51246 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo710 ; - assign _dfoo78 = - (source_id__h63346 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo10 ; - assign _dfoo780 = - (source_id__h51246 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo712 ; - assign _dfoo782 = - (source_id__h51246 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo714 ; - assign _dfoo784 = - (source_id__h51246 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo716 ; - assign _dfoo786 = - (source_id__h51246 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo718 ; - assign _dfoo788 = - (source_id__h51246 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo720 ; - assign _dfoo790 = - (source_id__h51246 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo722 ; - assign _dfoo792 = - (source_id__h51246 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo724 ; - assign _dfoo794 = - (source_id__h51246 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo726 ; - assign _dfoo796 = - (source_id__h51246 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo728 ; - assign _dfoo798 = - (source_id__h51246 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo730 ; - assign _dfoo8 = - (source_id__h64556 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26923[30] : - wdata32__h26923[31] ; - assign _dfoo80 = - (source_id__h63346 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo12 ; - assign _dfoo800 = - (source_id__h51246 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo732 ; - assign _dfoo802 = - (source_id__h51246 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo734 ; - assign _dfoo804 = - (source_id__h51246 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo736 ; - assign _dfoo806 = - (source_id__h51246 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo738 ; - assign _dfoo808 = - (source_id__h51246 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo740 ; - assign _dfoo810 = - (source_id__h51246 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo742 ; - assign _dfoo812 = - (source_id__h51246 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo744 ; - assign _dfoo814 = - (source_id__h51246 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo746 ; - assign _dfoo816 = - (source_id__h51246 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26923[19] : - _dfoo748 ; - assign _dfoo817 = - source_id__h50036 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo681 ; - assign _dfoo818 = - (source_id__h50036 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo750 ; - assign _dfoo819 = - source_id__h50036 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo683 ; - assign _dfoo82 = - (source_id__h63346 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo14 ; - assign _dfoo820 = - (source_id__h50036 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo752 ; - assign _dfoo821 = - source_id__h50036 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo685 ; - assign _dfoo822 = - (source_id__h50036 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo754 ; - assign _dfoo823 = - source_id__h50036 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo687 ; - assign _dfoo824 = - (source_id__h50036 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo756 ; - assign _dfoo825 = - source_id__h50036 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo689 ; - assign _dfoo826 = - (source_id__h50036 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo758 ; - assign _dfoo827 = - source_id__h50036 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo691 ; - assign _dfoo828 = - (source_id__h50036 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo760 ; - assign _dfoo829 = - source_id__h50036 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo693 ; - assign _dfoo830 = - (source_id__h50036 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo762 ; - assign _dfoo831 = - source_id__h50036 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo695 ; - assign _dfoo832 = - (source_id__h50036 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo764 ; - assign _dfoo833 = - source_id__h50036 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo697 ; - assign _dfoo834 = - (source_id__h50036 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo766 ; - assign _dfoo835 = - source_id__h50036 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo699 ; - assign _dfoo836 = - (source_id__h50036 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo768 ; - assign _dfoo837 = - source_id__h50036 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo701 ; - assign _dfoo838 = - (source_id__h50036 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo770 ; - assign _dfoo839 = - source_id__h50036 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo703 ; - assign _dfoo84 = - (source_id__h63346 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo16 ; - assign _dfoo840 = - (source_id__h50036 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo772 ; - assign _dfoo841 = - source_id__h50036 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo705 ; - assign _dfoo842 = - (source_id__h50036 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo774 ; - assign _dfoo843 = - source_id__h50036 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo707 ; - assign _dfoo844 = - (source_id__h50036 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo776 ; - assign _dfoo845 = - source_id__h50036 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo709 ; - assign _dfoo846 = - (source_id__h50036 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo778 ; - assign _dfoo847 = - source_id__h50036 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo711 ; - assign _dfoo848 = - (source_id__h50036 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo780 ; - assign _dfoo849 = - source_id__h50036 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo713 ; - assign _dfoo850 = - (source_id__h50036 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo782 ; - assign _dfoo851 = - source_id__h50036 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo715 ; - assign _dfoo852 = - (source_id__h50036 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo784 ; - assign _dfoo853 = - source_id__h50036 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo717 ; - assign _dfoo854 = - (source_id__h50036 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo786 ; - assign _dfoo855 = - source_id__h50036 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo719 ; - assign _dfoo856 = - (source_id__h50036 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo788 ; - assign _dfoo857 = - source_id__h50036 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo721 ; - assign _dfoo858 = - (source_id__h50036 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo790 ; - assign _dfoo859 = - source_id__h50036 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo723 ; - assign _dfoo86 = - (source_id__h63346 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo18 ; - assign _dfoo860 = - (source_id__h50036 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo792 ; - assign _dfoo861 = - source_id__h50036 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo725 ; - assign _dfoo862 = - (source_id__h50036 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo794 ; - assign _dfoo863 = - source_id__h50036 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo727 ; - assign _dfoo864 = - (source_id__h50036 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo796 ; - assign _dfoo865 = - source_id__h50036 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo729 ; - assign _dfoo866 = - (source_id__h50036 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo798 ; - assign _dfoo867 = - source_id__h50036 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo731 ; - assign _dfoo868 = - (source_id__h50036 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo800 ; - assign _dfoo869 = - source_id__h50036 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo733 ; - assign _dfoo870 = - (source_id__h50036 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo802 ; - assign _dfoo871 = - source_id__h50036 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo735 ; - assign _dfoo872 = - (source_id__h50036 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo804 ; - assign _dfoo873 = - source_id__h50036 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo737 ; - assign _dfoo874 = - (source_id__h50036 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo806 ; - assign _dfoo875 = - source_id__h50036 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo739 ; - assign _dfoo876 = - (source_id__h50036 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo808 ; - assign _dfoo877 = - source_id__h50036 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo741 ; - assign _dfoo878 = - (source_id__h50036 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo810 ; - assign _dfoo879 = - source_id__h50036 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo743 ; - assign _dfoo88 = - (source_id__h63346 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo20 ; - assign _dfoo880 = - (source_id__h50036 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo812 ; - assign _dfoo881 = - source_id__h50036 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo745 ; - assign _dfoo882 = - (source_id__h50036 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo814 ; - assign _dfoo883 = - source_id__h50036 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51246 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || - _dfoo747 ; - assign _dfoo884 = - (source_id__h50036 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26923[18] : - _dfoo816 ; - assign _dfoo886 = - (source_id__h48826 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo818 ; - assign _dfoo888 = - (source_id__h48826 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo820 ; - assign _dfoo890 = - (source_id__h48826 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo822 ; - assign _dfoo892 = - (source_id__h48826 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo824 ; - assign _dfoo894 = - (source_id__h48826 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo826 ; - assign _dfoo896 = - (source_id__h48826 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo828 ; - assign _dfoo898 = - (source_id__h48826 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo830 ; - assign _dfoo9 = - source_id__h64556 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65766 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; - assign _dfoo90 = - (source_id__h63346 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo22 ; - assign _dfoo900 = - (source_id__h48826 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo832 ; - assign _dfoo902 = - (source_id__h48826 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo834 ; - assign _dfoo904 = - (source_id__h48826 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo836 ; - assign _dfoo906 = - (source_id__h48826 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo838 ; - assign _dfoo908 = - (source_id__h48826 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo840 ; - assign _dfoo910 = - (source_id__h48826 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo842 ; - assign _dfoo912 = - (source_id__h48826 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo844 ; - assign _dfoo914 = - (source_id__h48826 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo846 ; - assign _dfoo916 = - (source_id__h48826 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo848 ; - assign _dfoo918 = - (source_id__h48826 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo850 ; - assign _dfoo92 = - (source_id__h63346 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo24 ; - assign _dfoo920 = - (source_id__h48826 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo852 ; - assign _dfoo922 = - (source_id__h48826 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo854 ; - assign _dfoo924 = - (source_id__h48826 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo856 ; - assign _dfoo926 = - (source_id__h48826 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo858 ; - assign _dfoo928 = - (source_id__h48826 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo860 ; - assign _dfoo930 = - (source_id__h48826 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo862 ; - assign _dfoo932 = - (source_id__h48826 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo864 ; - assign _dfoo934 = - (source_id__h48826 == 10'd9 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo866 ; - assign _dfoo936 = - (source_id__h48826 == 10'd8 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo868 ; - assign _dfoo938 = - (source_id__h48826 == 10'd7 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo870 ; - assign _dfoo94 = - (source_id__h63346 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo26 ; - assign _dfoo940 = - (source_id__h48826 == 10'd6 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo872 ; - assign _dfoo942 = - (source_id__h48826 == 10'd5 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo874 ; - assign _dfoo944 = - (source_id__h48826 == 10'd4 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo876 ; - assign _dfoo946 = - (source_id__h48826 == 10'd3 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo878 ; - assign _dfoo948 = - (source_id__h48826 == 10'd2 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo880 ; - assign _dfoo950 = - (source_id__h48826 == 10'd1 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo882 ; - assign _dfoo952 = - (source_id__h48826 == 10'd0 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26923[17] : - _dfoo884 ; - assign _dfoo953 = - source_id__h47616 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo817 ; - assign _dfoo954 = - (source_id__h47616 == 10'd16 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo886 ; - assign _dfoo955 = - source_id__h47616 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo819 ; - assign _dfoo956 = - (source_id__h47616 == 10'd15 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo888 ; - assign _dfoo957 = - source_id__h47616 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo821 ; - assign _dfoo958 = - (source_id__h47616 == 10'd14 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo890 ; - assign _dfoo959 = - source_id__h47616 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo823 ; - assign _dfoo96 = - (source_id__h63346 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo28 ; - assign _dfoo960 = - (source_id__h47616 == 10'd13 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo892 ; - assign _dfoo961 = - source_id__h47616 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo825 ; - assign _dfoo962 = - (source_id__h47616 == 10'd12 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo894 ; - assign _dfoo963 = - source_id__h47616 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo827 ; - assign _dfoo964 = - (source_id__h47616 == 10'd11 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo896 ; - assign _dfoo965 = - source_id__h47616 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo829 ; - assign _dfoo966 = - (source_id__h47616 == 10'd10 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo898 ; - assign _dfoo967 = - source_id__h47616 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo831 ; - assign _dfoo968 = - (source_id__h47616 == 10'd9 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo900 ; - assign _dfoo969 = - source_id__h47616 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo833 ; - assign _dfoo970 = - (source_id__h47616 == 10'd8 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo902 ; - assign _dfoo971 = - source_id__h47616 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo835 ; - assign _dfoo972 = - (source_id__h47616 == 10'd7 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo904 ; - assign _dfoo973 = - source_id__h47616 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo837 ; - assign _dfoo974 = - (source_id__h47616 == 10'd6 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo906 ; - assign _dfoo975 = - source_id__h47616 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo839 ; - assign _dfoo976 = - (source_id__h47616 == 10'd5 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo908 ; - assign _dfoo977 = - source_id__h47616 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo841 ; - assign _dfoo978 = - (source_id__h47616 == 10'd4 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo910 ; - assign _dfoo979 = - source_id__h47616 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo843 ; - assign _dfoo98 = - (source_id__h63346 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26923[29] : - _dfoo30 ; - assign _dfoo980 = - (source_id__h47616 == 10'd3 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo912 ; - assign _dfoo981 = - source_id__h47616 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo845 ; - assign _dfoo982 = - (source_id__h47616 == 10'd2 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo914 ; - assign _dfoo983 = - source_id__h47616 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo847 ; - assign _dfoo984 = - (source_id__h47616 == 10'd1 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo916 ; - assign _dfoo985 = - source_id__h47616 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo849 ; - assign _dfoo986 = - (source_id__h47616 == 10'd0 && - addr_offset__h26922[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo918 ; - assign _dfoo987 = - source_id__h47616 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo851 ; - assign _dfoo988 = - (source_id__h47616 == 10'd16 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo920 ; - assign _dfoo989 = - source_id__h47616 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo853 ; - assign _dfoo990 = - (source_id__h47616 == 10'd15 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo922 ; - assign _dfoo991 = - source_id__h47616 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo855 ; - assign _dfoo992 = - (source_id__h47616 == 10'd14 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo924 ; - assign _dfoo993 = - source_id__h47616 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo857 ; - assign _dfoo994 = - (source_id__h47616 == 10'd13 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo926 ; - assign _dfoo995 = - source_id__h47616 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo859 ; - assign _dfoo996 = - (source_id__h47616 == 10'd12 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo928 ; - assign _dfoo997 = - source_id__h47616 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo861 ; - assign _dfoo998 = - (source_id__h47616 == 10'd11 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26923[16] : - _dfoo930 ; - assign _dfoo999 = - source_id__h47616 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48826 == 10'd10 && - addr_offset__h26922[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || - _dfoo863 ; - assign a__h71299 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 ; - assign a__h73304 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 ; - assign addr_offset__h13216 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26922 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71300 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 ; - assign b__h73305 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = - addr_offset__h13216 < 64'h0000000000003000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = - addr_offset__h13216[11:7] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 = - addr_offset__h13216 < 64'h0000000000001000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 = - addr_offset__h13216[11:2] <= 10'd16 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 = - addr_offset__h13216[16:12] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 = - addr_offset__h13216 < 64'h0000000000002000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = - source_id_base__h13630 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 = - addr_offset__h26922[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 = - addr_offset__h26922[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 = - addr_offset__h26922[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 = - addr_offset__h26922 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 = - addr_offset__h26922[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 = - addr_offset__h26922[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 = - addr_offset__h26922[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 = - addr_offset__h26922[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 = - addr_offset__h26922[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 = - addr_offset__h26922[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 = - addr_offset__h26922[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 = - addr_offset__h26922[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 = - addr_offset__h26922[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 = - addr_offset__h26922[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 = - addr_offset__h26922[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 = - addr_offset__h26922[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 = - addr_offset__h26922[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 = - addr_offset__h26922[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 = - addr_offset__h26922[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 = - addr_offset__h26922[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 = - addr_offset__h26922[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - addr_offset__h26922[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 = - addr_offset__h26922 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 = - source_id_base__h28139 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 = - addr_offset__h26922 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26922[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 = - addr_offset__h26922[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 = - addr_offset__h26922[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 && - m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 && - m_vvrg_ie_1_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 && - m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 && - m_vvrg_ie_1_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 && - m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 && - m_vvrg_ie_1_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 && - m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 && - m_vvrg_ie_1_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 || - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 || - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 || - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 || - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 && - m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 && - m_vvrg_ie_1_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 && - m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 && - m_vvrg_ie_1_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 && - m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 && - m_vvrg_ie_1_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = - m_vrg_source_ip_16 && - !m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 || - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 || - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 || - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 ; - assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = - m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 && - m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 && - m_vvrg_ie_1_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 && - m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 && - m_vvrg_ie_1_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 && - m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 && - m_vvrg_ie_1_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 && - m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 && - m_vvrg_ie_1_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 && - m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 && - m_vvrg_ie_1_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 && - m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 && - m_vvrg_ie_1_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 || - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 || - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 || - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 || - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 && - m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 && - m_vvrg_ie_1_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 && - m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 && - m_vvrg_ie_1_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; - assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 = - m_vrg_source_prio_16 <= - (m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ; - assign max_id__h23959 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ; - assign rdata___1__h26404 = { rdata__h26202[31:0], 32'h0 } ; - assign rdata__h26202 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 64'd0 : - y_avValue_fst__h26194 ; - assign rresp__h26203 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 2'b11 : - y_avValue_snd__h26195 ; - assign source_id__h15665 = { addr_offset__h13216[4:0], 5'd31 } ; - assign source_id__h15772 = { addr_offset__h13216[4:0], 5'd30 } ; - assign source_id__h15845 = { addr_offset__h13216[4:0], 5'd29 } ; - assign source_id__h15918 = { addr_offset__h13216[4:0], 5'd28 } ; - assign source_id__h15991 = { addr_offset__h13216[4:0], 5'd27 } ; - assign source_id__h16064 = { addr_offset__h13216[4:0], 5'd26 } ; - assign source_id__h16137 = { addr_offset__h13216[4:0], 5'd25 } ; - assign source_id__h16210 = { addr_offset__h13216[4:0], 5'd24 } ; - assign source_id__h16283 = { addr_offset__h13216[4:0], 5'd23 } ; - assign source_id__h16356 = { addr_offset__h13216[4:0], 5'd22 } ; - assign source_id__h16429 = { addr_offset__h13216[4:0], 5'd21 } ; - assign source_id__h16502 = { addr_offset__h13216[4:0], 5'd20 } ; - assign source_id__h16575 = { addr_offset__h13216[4:0], 5'd19 } ; - assign source_id__h16648 = { addr_offset__h13216[4:0], 5'd18 } ; - assign source_id__h16721 = { addr_offset__h13216[4:0], 5'd17 } ; - assign source_id__h16794 = { addr_offset__h13216[4:0], 5'd16 } ; - assign source_id__h16867 = { addr_offset__h13216[4:0], 5'd15 } ; - assign source_id__h16940 = { addr_offset__h13216[4:0], 5'd14 } ; - assign source_id__h17013 = { addr_offset__h13216[4:0], 5'd13 } ; - assign source_id__h17086 = { addr_offset__h13216[4:0], 5'd12 } ; - assign source_id__h17159 = { addr_offset__h13216[4:0], 5'd11 } ; - assign source_id__h17232 = { addr_offset__h13216[4:0], 5'd10 } ; - assign source_id__h17305 = { addr_offset__h13216[4:0], 5'd9 } ; - assign source_id__h17378 = { addr_offset__h13216[4:0], 5'd8 } ; - assign source_id__h17451 = { addr_offset__h13216[4:0], 5'd7 } ; - assign source_id__h17524 = { addr_offset__h13216[4:0], 5'd6 } ; - assign source_id__h17597 = { addr_offset__h13216[4:0], 5'd5 } ; - assign source_id__h17670 = { addr_offset__h13216[4:0], 5'd4 } ; - assign source_id__h17743 = { addr_offset__h13216[4:0], 5'd3 } ; - assign source_id__h17816 = { addr_offset__h13216[4:0], 5'd2 } ; - assign source_id__h17889 = { addr_offset__h13216[4:0], 5'd1 } ; - assign source_id__h20137 = 10'd31 + source_id_base__h13630 ; - assign source_id__h20313 = 10'd30 + source_id_base__h13630 ; - assign source_id__h20421 = 10'd29 + source_id_base__h13630 ; - assign source_id__h20529 = 10'd28 + source_id_base__h13630 ; - assign source_id__h20637 = 10'd27 + source_id_base__h13630 ; - assign source_id__h20745 = 10'd26 + source_id_base__h13630 ; - assign source_id__h20853 = 10'd25 + source_id_base__h13630 ; - assign source_id__h20961 = 10'd24 + source_id_base__h13630 ; - assign source_id__h21069 = 10'd23 + source_id_base__h13630 ; - assign source_id__h21177 = 10'd22 + source_id_base__h13630 ; - assign source_id__h21285 = 10'd21 + source_id_base__h13630 ; - assign source_id__h21393 = 10'd20 + source_id_base__h13630 ; - assign source_id__h21501 = 10'd19 + source_id_base__h13630 ; - assign source_id__h21609 = 10'd18 + source_id_base__h13630 ; - assign source_id__h21717 = 10'd17 + source_id_base__h13630 ; - assign source_id__h21825 = 10'd16 + source_id_base__h13630 ; - assign source_id__h21933 = 10'd15 + source_id_base__h13630 ; - assign source_id__h22041 = 10'd14 + source_id_base__h13630 ; - assign source_id__h22149 = 10'd13 + source_id_base__h13630 ; - assign source_id__h22257 = 10'd12 + source_id_base__h13630 ; - assign source_id__h22365 = 10'd11 + source_id_base__h13630 ; - assign source_id__h22473 = 10'd10 + source_id_base__h13630 ; - assign source_id__h22581 = 10'd9 + source_id_base__h13630 ; - assign source_id__h22689 = 10'd8 + source_id_base__h13630 ; - assign source_id__h22797 = 10'd7 + source_id_base__h13630 ; - assign source_id__h22905 = 10'd6 + source_id_base__h13630 ; - assign source_id__h23013 = 10'd5 + source_id_base__h13630 ; - assign source_id__h23121 = 10'd4 + source_id_base__h13630 ; - assign source_id__h23229 = 10'd3 + source_id_base__h13630 ; - assign source_id__h23337 = 10'd2 + source_id_base__h13630 ; - assign source_id__h23445 = 10'd1 + source_id_base__h13630 ; - assign source_id__h29466 = { addr_offset__h26922[4:0], 5'd1 } ; - assign source_id__h30676 = { addr_offset__h26922[4:0], 5'd2 } ; - assign source_id__h31886 = { addr_offset__h26922[4:0], 5'd3 } ; - assign source_id__h33096 = { addr_offset__h26922[4:0], 5'd4 } ; - assign source_id__h34306 = { addr_offset__h26922[4:0], 5'd5 } ; - assign source_id__h35516 = { addr_offset__h26922[4:0], 5'd6 } ; - assign source_id__h36726 = { addr_offset__h26922[4:0], 5'd7 } ; - assign source_id__h37936 = { addr_offset__h26922[4:0], 5'd8 } ; - assign source_id__h39146 = { addr_offset__h26922[4:0], 5'd9 } ; - assign source_id__h40356 = { addr_offset__h26922[4:0], 5'd10 } ; - assign source_id__h41566 = { addr_offset__h26922[4:0], 5'd11 } ; - assign source_id__h42776 = { addr_offset__h26922[4:0], 5'd12 } ; - assign source_id__h43986 = { addr_offset__h26922[4:0], 5'd13 } ; - assign source_id__h45196 = { addr_offset__h26922[4:0], 5'd14 } ; - assign source_id__h46406 = { addr_offset__h26922[4:0], 5'd15 } ; - assign source_id__h47616 = { addr_offset__h26922[4:0], 5'd16 } ; - assign source_id__h48826 = { addr_offset__h26922[4:0], 5'd17 } ; - assign source_id__h50036 = { addr_offset__h26922[4:0], 5'd18 } ; - assign source_id__h51246 = { addr_offset__h26922[4:0], 5'd19 } ; - assign source_id__h52456 = { addr_offset__h26922[4:0], 5'd20 } ; - assign source_id__h53666 = { addr_offset__h26922[4:0], 5'd21 } ; - assign source_id__h54876 = { addr_offset__h26922[4:0], 5'd22 } ; - assign source_id__h56086 = { addr_offset__h26922[4:0], 5'd23 } ; - assign source_id__h57296 = { addr_offset__h26922[4:0], 5'd24 } ; - assign source_id__h58506 = { addr_offset__h26922[4:0], 5'd25 } ; - assign source_id__h59716 = { addr_offset__h26922[4:0], 5'd26 } ; - assign source_id__h60926 = { addr_offset__h26922[4:0], 5'd27 } ; - assign source_id__h62136 = { addr_offset__h26922[4:0], 5'd28 } ; - assign source_id__h63346 = { addr_offset__h26922[4:0], 5'd29 } ; - assign source_id__h64556 = { addr_offset__h26922[4:0], 5'd30 } ; - assign source_id__h65766 = { addr_offset__h26922[4:0], 5'd31 } ; - assign source_id__h67427 = { 5'd0, x__h67478 } ; - assign source_id_base__h13630 = { addr_offset__h13216[4:0], 5'h0 } ; - assign source_id_base__h28139 = { addr_offset__h26922[4:0], 5'h0 } ; - assign v__h13422 = { 61'd0, x__h13493 } ; - assign v__h13671 = { 32'd0, v_ip__h13674 } ; - assign v__h18144 = { 32'd0, v_ie__h18147 } ; - assign v__h23761 = { 61'd0, x__h23832 } ; - assign v__h25455 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ? - v__h25474 : - 64'd0 ; - assign v__h25474 = { 59'd0, max_id__h23959 } ; - assign v__h26927 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 ? - 2'b11 : - v__h27085 ; - assign v__h27085 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? - v__h27098 : - v__h27933 ; - assign v__h27098 = - (addr_offset__h26922[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848) ? - 2'b0 : - 2'b10 ; - assign v__h27933 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899) ? - v__h27952 : - v__h28116 ; - assign v__h27952 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 ? - 2'b0 : - 2'b10 ; - assign v__h28116 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913) ? - v__h28135 : - v__h67098 ; - assign v__h28135 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - 2'b0 : - 2'b10 ; - assign v__h67135 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? - 2'b0 : - 2'b10 ; - assign v__h67423 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? - v__h67467 : - 2'b10 ; - assign v__h67467 = - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ? - 2'b0 : - 2'b10 ; - assign v_ie__h18147 = - { source_id__h20137 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h20313 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h20421 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h20529 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h20637 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h20745 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h20853 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h20961 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h21069 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h21177 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h21285 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h21393 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h21501 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h21609 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h21717 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h21825 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h21933 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h22041 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h22149 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h22257 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h22365 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h22473 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h22581 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h22689 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h22797 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h22905 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h23013 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h23121 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h23229 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h23337 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h23445 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h13674 = - { source_id__h15665 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - source_id__h15772 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - source_id__h15845 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - source_id__h15918 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - source_id__h15991 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - source_id__h16064 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - source_id__h16137 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - source_id__h16210 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - source_id__h16283 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - source_id__h16356 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - source_id__h16429 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - source_id__h16502 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - source_id__h16575 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - source_id__h16648 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - source_id__h16721 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - source_id__h16794 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - source_id__h16867 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - source_id__h16940 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - source_id__h17013 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - source_id__h17086 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - source_id__h17159 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - source_id__h17232 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - source_id__h17305 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - source_id__h17378 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - source_id__h17451 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - source_id__h17524 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - source_id__h17597 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - source_id__h17670 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - source_id__h17743 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - source_id__h17816 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - source_id__h17889 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26923 = - (addr_offset__h26922[2:0] == 3'd4) ? - m_slave_xactor_f_wr_data$D_OUT[72:41] : - m_slave_xactor_f_wr_data$D_OUT[40:9] ; - assign x__h23673 = - { addr_offset__h13216[31:16], 4'd0, addr_offset__h13216[11:0] } ; - assign x__h26361 = - (addr_offset__h13216[2:0] == 3'd4) ? - rdata___1__h26404 : - rdata__h26202 ; - assign x__h67101 = - { addr_offset__h26922[31:16], 4'd0, addr_offset__h26922[11:0] } ; - assign y_avValue_fst__h26094 = (x__h24011 == 5'd0) ? v__h25455 : 64'd0 ; - assign y_avValue_fst__h26115 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_fst__h26094 : - 64'd0 ; - assign y_avValue_fst__h26127 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - v__h23761 : - 64'd0 ; - assign y_avValue_fst__h26143 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - v__h18144 : - 64'd0 ; - assign y_avValue_fst__h26159 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - v__h13671 : - 64'd0 ; - assign y_avValue_fst__h26164 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_fst__h26143 : - y_avValue_fst__h26148 ; - assign y_avValue_fst__h26175 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - v__h13422 : - 64'd0 ; - assign y_avValue_fst__h26180 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_fst__h26159 : - y_avValue_fst__h26164 ; - assign y_avValue_fst__h26194 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_fst__h26175 : - y_avValue_fst__h26180 ; - assign y_avValue_snd__h26095 = (x__h24011 == 5'd0) ? 2'b0 : 2'b10 ; - assign y_avValue_snd__h26116 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_snd__h26095 : - 2'b10 ; - assign y_avValue_snd__h26128 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26144 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26160 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26165 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_snd__h26144 : - y_avValue_snd__h26149 ; - assign y_avValue_snd__h26176 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26181 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_snd__h26160 : - y_avValue_snd__h26165 ; - assign y_avValue_snd__h26195 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_snd__h26176 : - y_avValue_snd__h26181 ; - always@(addr_offset__h13216 or - m_vrg_source_prio_0 or - m_vrg_source_prio_1 or - m_vrg_source_prio_2 or - m_vrg_source_prio_3 or - m_vrg_source_prio_4 or - m_vrg_source_prio_5 or - m_vrg_source_prio_6 or - m_vrg_source_prio_7 or - m_vrg_source_prio_8 or - m_vrg_source_prio_9 or - m_vrg_source_prio_10 or - m_vrg_source_prio_11 or - m_vrg_source_prio_12 or - m_vrg_source_prio_13 or - m_vrg_source_prio_14 or - m_vrg_source_prio_15 or m_vrg_source_prio_16) - begin - case (addr_offset__h13216[11:2]) - 10'd0: x__h13493 = m_vrg_source_prio_0; - 10'd1: x__h13493 = m_vrg_source_prio_1; - 10'd2: x__h13493 = m_vrg_source_prio_2; - 10'd3: x__h13493 = m_vrg_source_prio_3; - 10'd4: x__h13493 = m_vrg_source_prio_4; - 10'd5: x__h13493 = m_vrg_source_prio_5; - 10'd6: x__h13493 = m_vrg_source_prio_6; - 10'd7: x__h13493 = m_vrg_source_prio_7; - 10'd8: x__h13493 = m_vrg_source_prio_8; - 10'd9: x__h13493 = m_vrg_source_prio_9; - 10'd10: x__h13493 = m_vrg_source_prio_10; - 10'd11: x__h13493 = m_vrg_source_prio_11; - 10'd12: x__h13493 = m_vrg_source_prio_12; - 10'd13: x__h13493 = m_vrg_source_prio_13; - 10'd14: x__h13493 = m_vrg_source_prio_14; - 10'd15: x__h13493 = m_vrg_source_prio_15; - 10'd16: x__h13493 = m_vrg_source_prio_16; - default: x__h13493 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_target_threshold_0 or m_vrg_target_threshold_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h23832 = m_vrg_target_threshold_0; - 5'd1: x__h23832 = m_vrg_target_threshold_1; - default: x__h23832 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h24011 = m_vrg_servicing_source_0; - 5'd1: x__h24011 = m_vrg_servicing_source_1; - default: x__h24011 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h26922 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h26922[16:12]) - 5'd0: x__h67478 = m_vrg_servicing_source_0; - 5'd1: x__h67478 = m_vrg_servicing_source_1; - default: x__h67478 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15665 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15665) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15772 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15772) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15845 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15845) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15918 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15918) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15991 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15991) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16064 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16064) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17159 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17159) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16137 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16137) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16210 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16210) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16283 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16283) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16356 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16356) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16429 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16429) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16502 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16502) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16575 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16575) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16648 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16648) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16721 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16721) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16794 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16794) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16867 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16867) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16940 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16940) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17013 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17013) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17086 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17086) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17232 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17232) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17305 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17305) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17378 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17378) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17451 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17451) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17524 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17524) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17597 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17597) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17670 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17670) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17743 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17743) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17889 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17889) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17816 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17816) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_snd__h26128 or y_avValue_snd__h26116) - begin - case (x__h23673) - 32'h00200000: y_avValue_snd__h26149 = y_avValue_snd__h26128; - 32'h00200004: y_avValue_snd__h26149 = y_avValue_snd__h26116; - default: y_avValue_snd__h26149 = 2'b10; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_0_1; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_1_1; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_0_2; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_1_2; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_0_3; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_1_3; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_0_4; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_1_4; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_0_5; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_1_5; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_0_6; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_1_6; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_0_7; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_1_7; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_0_8; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_1_8; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_0_9; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_1_9; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_0_10; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_1_10; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_0_11; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_1_11; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_0_12; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_1_12; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_0_13; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_1_13; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_0_14; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_1_14; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_0_15; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_1_15; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_0_16; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_1_16; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_fst__h26127 or y_avValue_fst__h26115) - begin - case (x__h23673) - 32'h00200000: y_avValue_fst__h26148 = y_avValue_fst__h26127; - 32'h00200004: y_avValue_fst__h26148 = y_avValue_fst__h26115; - default: y_avValue_fst__h26148 = 64'd0; - endcase - end - always@(source_id__h67427 or - m_vrg_source_busy_0 or - m_vrg_source_busy_1 or - m_vrg_source_busy_2 or - m_vrg_source_busy_3 or - m_vrg_source_busy_4 or - m_vrg_source_busy_5 or - m_vrg_source_busy_6 or - m_vrg_source_busy_7 or - m_vrg_source_busy_8 or - m_vrg_source_busy_9 or - m_vrg_source_busy_10 or - m_vrg_source_busy_11 or - m_vrg_source_busy_12 or - m_vrg_source_busy_13 or - m_vrg_source_busy_14 or - m_vrg_source_busy_15 or m_vrg_source_busy_16) - begin - case (source_id__h67427) - 10'd0: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_0; - 10'd1: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_1; - 10'd2: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_2; - 10'd3: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_3; - 10'd4: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_4; - 10'd5: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_5; - 10'd6: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_6; - 10'd7: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_7; - 10'd8: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_8; - 10'd9: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_9; - 10'd10: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_10; - 10'd11: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_11; - 10'd12: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_12; - 10'd13: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_13; - 10'd14: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_14; - 10'd15: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_15; - 10'd16: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h67101 or v__h67135 or v__h67423) - begin - case (x__h67101) - 32'h00200000: v__h67098 = v__h67135; - 32'h00200004: v__h67098 = v__h67423; - default: v__h67098 = 2'b10; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_cfg_verbosity$EN) - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN; - if (m_vrg_servicing_source_0$EN) - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_0$D_IN; - if (m_vrg_servicing_source_1$EN) - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_1$D_IN; - if (m_vrg_source_busy_0$EN) - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_0$D_IN; - if (m_vrg_source_busy_1$EN) - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_1$D_IN; - if (m_vrg_source_busy_10$EN) - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_10$D_IN; - if (m_vrg_source_busy_11$EN) - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_11$D_IN; - if (m_vrg_source_busy_12$EN) - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_12$D_IN; - if (m_vrg_source_busy_13$EN) - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_13$D_IN; - if (m_vrg_source_busy_14$EN) - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_14$D_IN; - if (m_vrg_source_busy_15$EN) - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_15$D_IN; - if (m_vrg_source_busy_16$EN) - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_16$D_IN; - if (m_vrg_source_busy_2$EN) - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_2$D_IN; - if (m_vrg_source_busy_3$EN) - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_3$D_IN; - if (m_vrg_source_busy_4$EN) - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_4$D_IN; - if (m_vrg_source_busy_5$EN) - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_5$D_IN; - if (m_vrg_source_busy_6$EN) - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_6$D_IN; - if (m_vrg_source_busy_7$EN) - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_7$D_IN; - if (m_vrg_source_busy_8$EN) - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_8$D_IN; - if (m_vrg_source_busy_9$EN) - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_9$D_IN; - if (m_vrg_source_ip_0$EN) - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_0$D_IN; - if (m_vrg_source_ip_1$EN) - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_1$D_IN; - if (m_vrg_source_ip_10$EN) - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_10$D_IN; - if (m_vrg_source_ip_11$EN) - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_11$D_IN; - if (m_vrg_source_ip_12$EN) - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_12$D_IN; - if (m_vrg_source_ip_13$EN) - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_13$D_IN; - if (m_vrg_source_ip_14$EN) - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_14$D_IN; - if (m_vrg_source_ip_15$EN) - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_15$D_IN; - if (m_vrg_source_ip_16$EN) - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_16$D_IN; - if (m_vrg_source_ip_2$EN) - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_2$D_IN; - if (m_vrg_source_ip_3$EN) - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_3$D_IN; - if (m_vrg_source_ip_4$EN) - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_4$D_IN; - if (m_vrg_source_ip_5$EN) - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_5$D_IN; - if (m_vrg_source_ip_6$EN) - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_6$D_IN; - if (m_vrg_source_ip_7$EN) - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_7$D_IN; - if (m_vrg_source_ip_8$EN) - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_8$D_IN; - if (m_vrg_source_ip_9$EN) - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_9$D_IN; - if (m_vrg_source_prio_0$EN) - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_0$D_IN; - if (m_vrg_source_prio_1$EN) - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_1$D_IN; - if (m_vrg_source_prio_10$EN) - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_10$D_IN; - if (m_vrg_source_prio_11$EN) - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_11$D_IN; - if (m_vrg_source_prio_12$EN) - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_12$D_IN; - if (m_vrg_source_prio_13$EN) - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_13$D_IN; - if (m_vrg_source_prio_14$EN) - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_14$D_IN; - if (m_vrg_source_prio_15$EN) - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_15$D_IN; - if (m_vrg_source_prio_16$EN) - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_16$D_IN; - if (m_vrg_source_prio_2$EN) - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_2$D_IN; - if (m_vrg_source_prio_3$EN) - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_3$D_IN; - if (m_vrg_source_prio_4$EN) - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_4$D_IN; - if (m_vrg_source_prio_5$EN) - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_5$D_IN; - if (m_vrg_source_prio_6$EN) - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_6$D_IN; - if (m_vrg_source_prio_7$EN) - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_7$D_IN; - if (m_vrg_source_prio_8$EN) - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_8$D_IN; - if (m_vrg_source_prio_9$EN) - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_9$D_IN; - if (m_vrg_target_threshold_0$EN) - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_0$D_IN; - if (m_vrg_target_threshold_1$EN) - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_1$D_IN; - if (m_vvrg_ie_0_0$EN) - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_0$D_IN; - if (m_vvrg_ie_0_1$EN) - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_1$D_IN; - if (m_vvrg_ie_0_10$EN) - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_10$D_IN; - if (m_vvrg_ie_0_11$EN) - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_11$D_IN; - if (m_vvrg_ie_0_12$EN) - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_12$D_IN; - if (m_vvrg_ie_0_13$EN) - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_13$D_IN; - if (m_vvrg_ie_0_14$EN) - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_14$D_IN; - if (m_vvrg_ie_0_15$EN) - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_15$D_IN; - if (m_vvrg_ie_0_16$EN) - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_16$D_IN; - if (m_vvrg_ie_0_2$EN) - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_2$D_IN; - if (m_vvrg_ie_0_3$EN) - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_3$D_IN; - if (m_vvrg_ie_0_4$EN) - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_4$D_IN; - if (m_vvrg_ie_0_5$EN) - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_5$D_IN; - if (m_vvrg_ie_0_6$EN) - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_6$D_IN; - if (m_vvrg_ie_0_7$EN) - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_7$D_IN; - if (m_vvrg_ie_0_8$EN) - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_8$D_IN; - if (m_vvrg_ie_0_9$EN) - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_9$D_IN; - if (m_vvrg_ie_1_0$EN) - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_0$D_IN; - if (m_vvrg_ie_1_1$EN) - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_1$D_IN; - if (m_vvrg_ie_1_10$EN) - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_10$D_IN; - if (m_vvrg_ie_1_11$EN) - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_11$D_IN; - if (m_vvrg_ie_1_12$EN) - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_12$D_IN; - if (m_vvrg_ie_1_13$EN) - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_13$D_IN; - if (m_vvrg_ie_1_14$EN) - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_14$D_IN; - if (m_vvrg_ie_1_15$EN) - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_15$D_IN; - if (m_vvrg_ie_1_16$EN) - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_16$D_IN; - if (m_vvrg_ie_1_2$EN) - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_2$D_IN; - if (m_vvrg_ie_1_3$EN) - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_3$D_IN; - if (m_vvrg_ie_1_4$EN) - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_4$D_IN; - if (m_vvrg_ie_1_5$EN) - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_5$D_IN; - if (m_vvrg_ie_1_6$EN) - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_6$D_IN; - if (m_vvrg_ie_1_7$EN) - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_7$D_IN; - if (m_vvrg_ie_1_8$EN) - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_8$D_IN; - if (m_vvrg_ie_1_9$EN) - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_9$D_IN; - end - if (m_rg_addr_base$EN) - m_rg_addr_base <= `BSV_ASSIGNMENT_DELAY m_rg_addr_base$D_IN; - if (m_rg_addr_lim$EN) - m_rg_addr_lim <= `BSV_ASSIGNMENT_DELAY m_rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_cfg_verbosity = 4'hA; - m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - m_vrg_servicing_source_0 = 5'h0A; - m_vrg_servicing_source_1 = 5'h0A; - m_vrg_source_busy_0 = 1'h0; - m_vrg_source_busy_1 = 1'h0; - m_vrg_source_busy_10 = 1'h0; - m_vrg_source_busy_11 = 1'h0; - m_vrg_source_busy_12 = 1'h0; - m_vrg_source_busy_13 = 1'h0; - m_vrg_source_busy_14 = 1'h0; - m_vrg_source_busy_15 = 1'h0; - m_vrg_source_busy_16 = 1'h0; - m_vrg_source_busy_2 = 1'h0; - m_vrg_source_busy_3 = 1'h0; - m_vrg_source_busy_4 = 1'h0; - m_vrg_source_busy_5 = 1'h0; - m_vrg_source_busy_6 = 1'h0; - m_vrg_source_busy_7 = 1'h0; - m_vrg_source_busy_8 = 1'h0; - m_vrg_source_busy_9 = 1'h0; - m_vrg_source_ip_0 = 1'h0; - m_vrg_source_ip_1 = 1'h0; - m_vrg_source_ip_10 = 1'h0; - m_vrg_source_ip_11 = 1'h0; - m_vrg_source_ip_12 = 1'h0; - m_vrg_source_ip_13 = 1'h0; - m_vrg_source_ip_14 = 1'h0; - m_vrg_source_ip_15 = 1'h0; - m_vrg_source_ip_16 = 1'h0; - m_vrg_source_ip_2 = 1'h0; - m_vrg_source_ip_3 = 1'h0; - m_vrg_source_ip_4 = 1'h0; - m_vrg_source_ip_5 = 1'h0; - m_vrg_source_ip_6 = 1'h0; - m_vrg_source_ip_7 = 1'h0; - m_vrg_source_ip_8 = 1'h0; - m_vrg_source_ip_9 = 1'h0; - m_vrg_source_prio_0 = 3'h2; - m_vrg_source_prio_1 = 3'h2; - m_vrg_source_prio_10 = 3'h2; - m_vrg_source_prio_11 = 3'h2; - m_vrg_source_prio_12 = 3'h2; - m_vrg_source_prio_13 = 3'h2; - m_vrg_source_prio_14 = 3'h2; - m_vrg_source_prio_15 = 3'h2; - m_vrg_source_prio_16 = 3'h2; - m_vrg_source_prio_2 = 3'h2; - m_vrg_source_prio_3 = 3'h2; - m_vrg_source_prio_4 = 3'h2; - m_vrg_source_prio_5 = 3'h2; - m_vrg_source_prio_6 = 3'h2; - m_vrg_source_prio_7 = 3'h2; - m_vrg_source_prio_8 = 3'h2; - m_vrg_source_prio_9 = 3'h2; - m_vrg_target_threshold_0 = 3'h2; - m_vrg_target_threshold_1 = 3'h2; - m_vvrg_ie_0_0 = 1'h0; - m_vvrg_ie_0_1 = 1'h0; - m_vvrg_ie_0_10 = 1'h0; - m_vvrg_ie_0_11 = 1'h0; - m_vvrg_ie_0_12 = 1'h0; - m_vvrg_ie_0_13 = 1'h0; - m_vvrg_ie_0_14 = 1'h0; - m_vvrg_ie_0_15 = 1'h0; - m_vvrg_ie_0_16 = 1'h0; - m_vvrg_ie_0_2 = 1'h0; - m_vvrg_ie_0_3 = 1'h0; - m_vvrg_ie_0_4 = 1'h0; - m_vvrg_ie_0_5 = 1'h0; - m_vvrg_ie_0_6 = 1'h0; - m_vvrg_ie_0_7 = 1'h0; - m_vvrg_ie_0_8 = 1'h0; - m_vvrg_ie_0_9 = 1'h0; - m_vvrg_ie_1_0 = 1'h0; - m_vvrg_ie_1_1 = 1'h0; - m_vvrg_ie_1_10 = 1'h0; - m_vvrg_ie_1_11 = 1'h0; - m_vvrg_ie_1_12 = 1'h0; - m_vvrg_ie_1_13 = 1'h0; - m_vvrg_ie_1_14 = 1'h0; - m_vvrg_ie_1_15 = 1'h0; - m_vvrg_ie_1_16 = 1'h0; - m_vvrg_ie_1_2 = 1'h0; - m_vvrg_ie_1_3 = 1'h0; - m_vvrg_ie_1_4 = 1'h0; - m_vvrg_ie_1_5 = 1'h0; - m_vvrg_ie_1_6 = 1'h0; - m_vvrg_ie_1_7 = 1'h0; - m_vvrg_ie_1_8 = 1'h0; - m_vvrg_ie_1_9 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src IPs :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src Prios:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src busy :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71299, - m_vrg_target_threshold_0, - b__h71300, - m_vrg_servicing_source_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73304, - m_vrg_target_threshold_1, - b__h73305, - m_vrg_servicing_source_1); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240) - begin - v__h75661 = $stime; - #0; - end - v__h75655 = v__h75661 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75655, - $signed(32'd1), - v_sources_0_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247) - begin - v__h75859 = $stime; - #0; - end - v__h75853 = v__h75859 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75853, - $signed(32'd2), - v_sources_1_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255) - begin - v__h76057 = $stime; - #0; - end - v__h76051 = v__h76057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76051, - $signed(32'd3), - v_sources_2_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263) - begin - v__h76255 = $stime; - #0; - end - v__h76249 = v__h76255 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76249, - $signed(32'd4), - v_sources_3_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271) - begin - v__h76453 = $stime; - #0; - end - v__h76447 = v__h76453 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76447, - $signed(32'd5), - v_sources_4_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279) - begin - v__h76651 = $stime; - #0; - end - v__h76645 = v__h76651 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76645, - $signed(32'd6), - v_sources_5_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287) - begin - v__h76849 = $stime; - #0; - end - v__h76843 = v__h76849 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76843, - $signed(32'd7), - v_sources_6_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295) - begin - v__h77047 = $stime; - #0; - end - v__h77041 = v__h77047 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77041, - $signed(32'd8), - v_sources_7_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303) - begin - v__h77245 = $stime; - #0; - end - v__h77239 = v__h77245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77239, - $signed(32'd9), - v_sources_8_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311) - begin - v__h77443 = $stime; - #0; - end - v__h77437 = v__h77443 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77437, - $signed(32'd10), - v_sources_9_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319) - begin - v__h77641 = $stime; - #0; - end - v__h77635 = v__h77641 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77635, - $signed(32'd11), - v_sources_10_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327) - begin - v__h77839 = $stime; - #0; - end - v__h77833 = v__h77839 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77833, - $signed(32'd12), - v_sources_11_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335) - begin - v__h78037 = $stime; - #0; - end - v__h78031 = v__h78037 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78031, - $signed(32'd13), - v_sources_12_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343) - begin - v__h78235 = $stime; - #0; - end - v__h78229 = v__h78235 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78229, - $signed(32'd14), - v_sources_13_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351) - begin - v__h78433 = $stime; - #0; - end - v__h78427 = v__h78433 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78427, - $signed(32'd15), - v_sources_14_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359) - begin - v__h78631 = $stime; - #0; - end - v__h78625 = v__h78631 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78625, - $signed(32'd16), - v_sources_15_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - begin - v__h6144 = $stime; - #0; - end - v__h6138 = v__h6144 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h6138); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h13080 = $stime; - #0; - end - v__h13074 = v__h13080 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req:", v__h13074); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - begin - v__h13265 = $stime; - #0; - end - v__h13259 = v__h13265 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h13259); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - begin - v__h13463 = $stime; - #0; - end - v__h13457 = v__h13463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h13457, - addr_offset__h13216[11:2], - v__h13422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - begin - v__h13713 = $stime; - #0; - end - v__h13707 = v__h13713 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h13707, - source_id_base__h13630, - v__h13671); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - begin - v__h18186 = $stime; - #0; - end - v__h18180 = v__h18186 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h18180, - source_id_base__h13630, - v__h18144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - begin - v__h23802 = $stime; - #0; - end - v__h23796 = v__h23802 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h23796, - addr_offset__h13216[16:12], - v__h23761); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - begin - v__h25975 = $stime; - #0; - end - v__h25969 = v__h25975 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h25969, - addr_offset__h13216[16:12], - v__h25474); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - begin - v__h24056 = $stime; - #0; - end - v__h24050 = v__h24056 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h24050, - addr_offset__h13216[16:12]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Still servicing interrupt from source %0d", x__h24011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Trying to claim service for source %0d", - max_id__h23959); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Ignoring."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - begin - v__h26250 = $stime; - #0; - end - v__h26244 = v__h26250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h26244); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26463 = $stime; - #0; - end - v__h26457 = v__h26463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req", v__h26457); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", x__h26361); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", rresp__h26203); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26737 = $stime; - #0; - end - v__h26731 = v__h26737 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26731); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - begin - v__h26961 = $stime; - #0; - end - v__h26955 = v__h26961 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26955); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) - begin - v__h27856 = $stime; - #0; - end - v__h27850 = v__h27856 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) - $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27850, - addr_offset__h26922[11:2], - wdata32__h26923); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) - begin - v__h28039 = $stime; - #0; - end - v__h28033 = v__h28039 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) - $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28033, - source_id_base__h28139); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) - begin - v__h67021 = $stime; - #0; - end - v__h67015 = v__h67021 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) - $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67015, - addr_offset__h26922[11:7], - source_id_base__h28139, - wdata32__h26923); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) - begin - v__h67309 = $stime; - #0; - end - v__h67303 = v__h67309 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) - $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67303, - addr_offset__h26922[16:12], - wdata32__h26923); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) - begin - v__h67838 = $stime; - #0; - end - v__h67832 = v__h67838 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) - $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67832, - addr_offset__h26922[16:12], - source_id__h67427); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) - begin - v__h67924 = $stime; - #0; - end - v__h67918 = v__h67924 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) - $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67918); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) - $display(" Completion message from target %0d to source %0d", - addr_offset__h26922[16:12], - source_id__h67427); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) - $display(" Ignoring"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - begin - v__h68123 = $stime; - #0; - end - v__h68117 = v__h68123 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68117); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h68342 = $stime; - #0; - end - v__h68336 = v__h68342 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68336); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26927); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h74677 = $stime; - #0; - end - v__h74671 = v__h74677 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74671, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h74787 = $stime; - #0; - end - v__h74781 = v__h74787 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74781, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - begin - v__h74900 = $stime; - #0; - end - v__h74894 = v__h74900 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74894, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkPLIC_16_2_7 - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v deleted file mode 100644 index 570d9b06..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v +++ /dev/null @@ -1,663 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_req_reset O 1 const -// RDY_rsp_reset O 1 const -// valid O 1 -// word O 32 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_is_OP_not_OP_32 I 1 reg -// req_f3 I 3 -// req_v1 I 32 -// req_v2 I 32 -// EN_set_verbosity I 1 -// EN_req_reset I 1 unused -// EN_rsp_reset I 1 unused -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkRISCV_MBox(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_req_reset, - RDY_req_reset, - - EN_rsp_reset, - RDY_rsp_reset, - - req_is_OP_not_OP_32, - req_f3, - req_v1, - req_v2, - EN_req, - - valid, - - word); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method req_reset - input EN_req_reset; - output RDY_req_reset; - - // action method rsp_reset - input EN_rsp_reset; - output RDY_rsp_reset; - - // action method req - input req_is_OP_not_OP_32; - input [2 : 0] req_f3; - input [31 : 0] req_v1; - input [31 : 0] req_v2; - input EN_req; - - // value method valid - output valid; - - // value method word - output [31 : 0] word; - - // signals for module outputs - wire [31 : 0] word; - wire RDY_req_reset, RDY_rsp_reset, RDY_set_verbosity, valid; - - // inlined wires - wire dw_valid$whas; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register intDiv_rg_denom2 - reg [31 : 0] intDiv_rg_denom2; - reg [31 : 0] intDiv_rg_denom2$D_IN; - wire intDiv_rg_denom2$EN; - - // register intDiv_rg_denom_is_signed - reg intDiv_rg_denom_is_signed; - wire intDiv_rg_denom_is_signed$D_IN, intDiv_rg_denom_is_signed$EN; - - // register intDiv_rg_n - reg [31 : 0] intDiv_rg_n; - reg [31 : 0] intDiv_rg_n$D_IN; - wire intDiv_rg_n$EN; - - // register intDiv_rg_numer_is_signed - reg intDiv_rg_numer_is_signed; - wire intDiv_rg_numer_is_signed$D_IN, intDiv_rg_numer_is_signed$EN; - - // register intDiv_rg_quo - reg [31 : 0] intDiv_rg_quo; - reg [31 : 0] intDiv_rg_quo$D_IN; - wire intDiv_rg_quo$EN; - - // register intDiv_rg_quoIsNeg - reg intDiv_rg_quoIsNeg; - wire intDiv_rg_quoIsNeg$D_IN, intDiv_rg_quoIsNeg$EN; - - // register intDiv_rg_remIsNeg - reg intDiv_rg_remIsNeg; - wire intDiv_rg_remIsNeg$D_IN, intDiv_rg_remIsNeg$EN; - - // register intDiv_rg_state - reg [2 : 0] intDiv_rg_state; - reg [2 : 0] intDiv_rg_state$D_IN; - wire intDiv_rg_state$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_is_OP_not_OP_32 - reg rg_is_OP_not_OP_32; - wire rg_is_OP_not_OP_32$D_IN, rg_is_OP_not_OP_32$EN; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_v1 - reg [31 : 0] rg_v1; - reg [31 : 0] rg_v1$D_IN; - wire rg_v1$EN; - - // register rg_v2 - reg [31 : 0] rg_v2; - wire [31 : 0] rg_v2$D_IN; - wire rg_v2$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_intDiv_rl_loop1, - CAN_FIRE_RL_intDiv_rl_loop2, - CAN_FIRE_RL_intDiv_rl_start_div_by_zero, - CAN_FIRE_RL_intDiv_rl_start_overflow, - CAN_FIRE_RL_intDiv_rl_start_s, - CAN_FIRE_RL_rg_div_rem, - CAN_FIRE_RL_rl_mul, - CAN_FIRE_RL_rl_mul2, - CAN_FIRE_req, - CAN_FIRE_req_reset, - CAN_FIRE_rsp_reset, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_intDiv_rl_loop1, - WILL_FIRE_RL_intDiv_rl_loop2, - WILL_FIRE_RL_intDiv_rl_start_div_by_zero, - WILL_FIRE_RL_intDiv_rl_start_overflow, - WILL_FIRE_RL_intDiv_rl_start_s, - WILL_FIRE_RL_rg_div_rem, - WILL_FIRE_RL_rl_mul, - WILL_FIRE_RL_rl_mul2, - WILL_FIRE_req, - WILL_FIRE_req_reset, - WILL_FIRE_rsp_reset, - WILL_FIRE_set_verbosity; - - // inputs to muxes for submodule ports - wire [31 : 0] MUX_dw_result$wset_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_1, - MUX_intDiv_rg_denom2$write_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_3, - MUX_intDiv_rg_n$write_1__VAL_1, - MUX_intDiv_rg_n$write_1__VAL_2, - MUX_intDiv_rg_quo$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_2, - MUX_rg_v1$write_1__VAL_3, - MUX_rg_v1$write_1__VAL_4; - wire [1 : 0] MUX_rg_state$write_1__VAL_1; - wire MUX_intDiv_rg_denom2$write_1__SEL_1, - MUX_intDiv_rg_denom2$write_1__SEL_2, - MUX_intDiv_rg_quo$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_2, - MUX_intDiv_rg_state$write_1__SEL_3, - MUX_rg_v1$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h3263; - reg [31 : 0] v__h3257; - // synopsys translate_on - - // remaining internal signals - wire [127 : 0] SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113, - SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105, - _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110; - wire [63 : 0] SEXT_rg_v1____d103, rg_v1_MUL_rg_v2___d100, v1__h3150; - wire [31 : 0] _theResult___fst__h787, - _theResult___snd_fst__h782, - denom___1__h729, - numer___1__h728, - v__h3074, - v__h3132, - v__h3183, - x__h2611, - x__h2697, - x__h2767, - x__h2782, - y__h2490; - wire IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39, - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47, - rg_v1_ULT_intDiv_rg_denom2_4___d59, - rg_v1_ULT_rg_v2___d55; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method req_reset - assign RDY_req_reset = 1'd1 ; - assign CAN_FIRE_req_reset = 1'd1 ; - assign WILL_FIRE_req_reset = EN_req_reset ; - - // action method rsp_reset - assign RDY_rsp_reset = 1'd1 ; - assign CAN_FIRE_rsp_reset = 1'd1 ; - assign WILL_FIRE_rsp_reset = EN_rsp_reset ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method word - assign word = WILL_FIRE_RL_rl_mul2 ? rg_v1 : MUX_dw_result$wset_1__VAL_2 ; - - // rule RL_rl_mul2 - assign CAN_FIRE_RL_rl_mul2 = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_mul2 = CAN_FIRE_RL_rl_mul2 ; - - // rule RL_rg_div_rem - assign CAN_FIRE_RL_rg_div_rem = - rg_state == 2'd2 && intDiv_rg_state == 3'd4 ; - assign WILL_FIRE_RL_rg_div_rem = CAN_FIRE_RL_rg_div_rem ; - - // rule RL_intDiv_rl_start_div_by_zero - assign CAN_FIRE_RL_intDiv_rl_start_div_by_zero = - intDiv_rg_state == 3'd1 && rg_v2 == 32'd0 ; - assign WILL_FIRE_RL_intDiv_rl_start_div_by_zero = - CAN_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // rule RL_intDiv_rl_start_overflow - assign CAN_FIRE_RL_intDiv_rl_start_overflow = - intDiv_rg_state == 3'd1 && intDiv_rg_numer_is_signed && - rg_v1 == 32'h80000000 && - intDiv_rg_denom_is_signed && - rg_v2 == 32'hFFFFFFFF ; - assign WILL_FIRE_RL_intDiv_rl_start_overflow = - CAN_FIRE_RL_intDiv_rl_start_overflow && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_start_s - assign CAN_FIRE_RL_intDiv_rl_start_s = - intDiv_rg_state == 3'd1 && rg_v2 != 32'd0 && - (!intDiv_rg_numer_is_signed || rg_v1 != 32'h80000000 || - !intDiv_rg_denom_is_signed || - rg_v2 != 32'hFFFFFFFF) ; - assign WILL_FIRE_RL_intDiv_rl_start_s = - CAN_FIRE_RL_intDiv_rl_start_s && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_loop1 - assign CAN_FIRE_RL_intDiv_rl_loop1 = intDiv_rg_state == 3'd2 ; - assign WILL_FIRE_RL_intDiv_rl_loop1 = CAN_FIRE_RL_intDiv_rl_loop1 ; - - // rule RL_rl_mul - assign CAN_FIRE_RL_rl_mul = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_mul = rg_state == 2'd0 ; - - // rule RL_intDiv_rl_loop2 - assign CAN_FIRE_RL_intDiv_rl_loop2 = intDiv_rg_state == 3'd3 ; - assign WILL_FIRE_RL_intDiv_rl_loop2 = - CAN_FIRE_RL_intDiv_rl_loop2 && !WILL_FIRE_RL_rl_mul ; - - // inputs to muxes for submodule ports - assign MUX_intDiv_rg_denom2$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 ; - assign MUX_intDiv_rg_denom2$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 ; - assign MUX_intDiv_rg_quo$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_quoIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_intDiv_rg_state$write_1__SEL_1 = EN_req && req_f3[2] ; - assign MUX_intDiv_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 ; - assign MUX_intDiv_rg_state$write_1__SEL_3 = - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 ; - assign MUX_rg_v1$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_remIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_dw_result$wset_1__VAL_2 = rg_f3[1] ? rg_v1 : intDiv_rg_quo ; - assign MUX_intDiv_rg_denom2$write_1__VAL_1 = - { intDiv_rg_denom2[30:0], 1'd0 } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_2 = - { 1'd0, intDiv_rg_denom2[31:1] } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_3 = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - denom___1__h729 : - _theResult___snd_fst__h782 ; - assign MUX_intDiv_rg_n$write_1__VAL_1 = { intDiv_rg_n[30:0], 1'd0 } ; - assign MUX_intDiv_rg_n$write_1__VAL_2 = { 1'd0, intDiv_rg_n[31:1] } ; - assign MUX_intDiv_rg_quo$write_1__VAL_1 = - rg_v1_ULT_rg_v2___d55 ? x__h2697 : x__h2782 ; - assign MUX_rg_state$write_1__VAL_1 = req_f3[2] ? 2'd2 : 2'd0 ; - assign MUX_rg_v1$write_1__VAL_2 = - rg_v1_ULT_rg_v2___d55 ? x__h2767 : x__h2611 ; - assign MUX_rg_v1$write_1__VAL_3 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - rg_v1_MUL_rg_v2___d100[31:0] : - v__h3074 ; - assign MUX_rg_v1$write_1__VAL_4 = - intDiv_rg_numer_is_signed ? numer___1__h728 : rg_v1 ; - - // inlined wires - assign dw_valid$whas = WILL_FIRE_RL_rg_div_rem || WILL_FIRE_RL_rl_mul2 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register intDiv_rg_denom2 - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_denom2$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_denom2$write_1__VAL_2 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_intDiv_rg_denom2$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_3; - default: intDiv_rg_denom2$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_denom2$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_denom_is_signed - assign intDiv_rg_denom_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_denom_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_n - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_n$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_n$write_1__VAL_2 or WILL_FIRE_RL_intDiv_rl_start_s) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_n$D_IN = 32'd1; - default: intDiv_rg_n$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_n$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_numer_is_signed - assign intDiv_rg_numer_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_numer_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_quo - always@(MUX_intDiv_rg_quo$write_1__SEL_1 or - MUX_intDiv_rg_quo$write_1__VAL_1 or - WILL_FIRE_RL_intDiv_rl_start_overflow or - rg_v1 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_quo$write_1__SEL_1: - intDiv_rg_quo$D_IN = MUX_intDiv_rg_quo$write_1__VAL_1; - WILL_FIRE_RL_intDiv_rl_start_overflow: intDiv_rg_quo$D_IN = rg_v1; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_quo$D_IN = 32'd0; - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_quo$D_IN = 32'hFFFFFFFF; - default: intDiv_rg_quo$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_quo$EN = - MUX_intDiv_rg_quo$write_1__SEL_1 || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register intDiv_rg_quoIsNeg - assign intDiv_rg_quoIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[31] != rg_v2[31] : - IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39 ; - assign intDiv_rg_quoIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_remIsNeg - assign intDiv_rg_remIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[31] : - intDiv_rg_numer_is_signed && rg_v1[31] ; - assign intDiv_rg_remIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_state - always@(MUX_intDiv_rg_state$write_1__SEL_1 or - MUX_intDiv_rg_state$write_1__SEL_2 or - MUX_intDiv_rg_state$write_1__SEL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_overflow or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - case (1'b1) - MUX_intDiv_rg_state$write_1__SEL_1: intDiv_rg_state$D_IN = 3'd1; - MUX_intDiv_rg_state$write_1__SEL_2: intDiv_rg_state$D_IN = 3'd4; - MUX_intDiv_rg_state$write_1__SEL_3: intDiv_rg_state$D_IN = 3'd3; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_state$D_IN = 3'd2; - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_state$D_IN = 3'd4; - default: intDiv_rg_state$D_IN = 3'b010 /* unspecified value */ ; - endcase - assign intDiv_rg_state$EN = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 || - EN_req && req_f3[2] || - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_is_OP_not_OP_32 - assign rg_is_OP_not_OP_32$D_IN = req_is_OP_not_OP_32 ; - assign rg_is_OP_not_OP_32$EN = EN_req ; - - // register rg_state - assign rg_state$D_IN = EN_req ? MUX_rg_state$write_1__VAL_1 : 2'd1 ; - assign rg_state$EN = EN_req || WILL_FIRE_RL_rl_mul ; - - // register rg_v1 - always@(EN_req or - req_v1 or - MUX_rg_v1$write_1__SEL_2 or - MUX_rg_v1$write_1__VAL_2 or - WILL_FIRE_RL_rl_mul or - MUX_rg_v1$write_1__VAL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_rg_v1$write_1__VAL_4 or WILL_FIRE_RL_intDiv_rl_start_overflow) - case (1'b1) - EN_req: rg_v1$D_IN = req_v1; - MUX_rg_v1$write_1__SEL_2: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_2; - WILL_FIRE_RL_rl_mul: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_3; - WILL_FIRE_RL_intDiv_rl_start_s: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_4; - WILL_FIRE_RL_intDiv_rl_start_overflow: rg_v1$D_IN = 32'd0; - default: rg_v1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; - endcase - assign rg_v1$EN = - MUX_rg_v1$write_1__SEL_2 || EN_req || WILL_FIRE_RL_rl_mul || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow ; - - // register rg_v2 - assign rg_v2$D_IN = EN_req ? req_v2 : MUX_intDiv_rg_denom2$write_1__VAL_3 ; - assign rg_v2$EN = EN_req || WILL_FIRE_RL_intDiv_rl_start_s ; - - // remaining internal signals - assign IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_31_ETC___d39 = - intDiv_rg_numer_is_signed ? - rg_v1[31] : - intDiv_rg_denom_is_signed && rg_v2[31] ; - assign SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113 = - SEXT_rg_v1____d103 * { 32'd0, rg_v2 } ; - assign SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105 = - SEXT_rg_v1____d103 * { {32{rg_v2[31]}}, rg_v2 } ; - assign SEXT_rg_v1____d103 = { {32{rg_v1[31]}}, rg_v1 } ; - assign _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110 = - v1__h3150 * { 32'd0, rg_v2 } ; - assign _theResult___fst__h787 = - intDiv_rg_denom_is_signed ? denom___1__h729 : rg_v2 ; - assign _theResult___snd_fst__h782 = - intDiv_rg_numer_is_signed ? rg_v2 : _theResult___fst__h787 ; - assign denom___1__h729 = rg_v2[31] ? -rg_v2 : rg_v2 ; - assign intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_31__ETC___d47 = - intDiv_rg_denom2 <= y__h2490 ; - assign numer___1__h728 = rg_v1[31] ? x__h2767 : rg_v1 ; - assign rg_v1_MUL_rg_v2___d100 = rg_v1 * rg_v2 ; - assign rg_v1_ULT_intDiv_rg_denom2_4___d59 = rg_v1 < intDiv_rg_denom2 ; - assign rg_v1_ULT_rg_v2___d55 = rg_v1 < rg_v2 ; - assign v1__h3150 = { 32'd0, rg_v1 } ; - assign v__h3074 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b001) ? - SEXT_rg_v1__03_MUL_SEXT_rg_v2__04___d105[63:32] : - v__h3132 ; - assign v__h3132 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b011) ? - _0_CONCAT_rg_v1_08_MUL_0_CONCAT_rg_v2_09___d110[63:32] : - v__h3183 ; - assign v__h3183 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b010) ? - SEXT_rg_v1__03_MUL_0_CONCAT_rg_v2_09___d113[63:32] : - 32'hFFFFFFFF ; - assign x__h2611 = rg_v1 - intDiv_rg_denom2 ; - assign x__h2697 = -intDiv_rg_quo ; - assign x__h2767 = -rg_v1 ; - assign x__h2782 = intDiv_rg_quo + intDiv_rg_n ; - assign y__h2490 = { 1'd0, rg_v1[31:1] } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (intDiv_rg_state$EN) - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY intDiv_rg_state$D_IN; - end - if (intDiv_rg_denom2$EN) - intDiv_rg_denom2 <= `BSV_ASSIGNMENT_DELAY intDiv_rg_denom2$D_IN; - if (intDiv_rg_denom_is_signed$EN) - intDiv_rg_denom_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_denom_is_signed$D_IN; - if (intDiv_rg_n$EN) intDiv_rg_n <= `BSV_ASSIGNMENT_DELAY intDiv_rg_n$D_IN; - if (intDiv_rg_numer_is_signed$EN) - intDiv_rg_numer_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_numer_is_signed$D_IN; - if (intDiv_rg_quo$EN) - intDiv_rg_quo <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quo$D_IN; - if (intDiv_rg_quoIsNeg$EN) - intDiv_rg_quoIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quoIsNeg$D_IN; - if (intDiv_rg_remIsNeg$EN) - intDiv_rg_remIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_remIsNeg$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_is_OP_not_OP_32$EN) - rg_is_OP_not_OP_32 <= `BSV_ASSIGNMENT_DELAY rg_is_OP_not_OP_32$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_v1$EN) rg_v1 <= `BSV_ASSIGNMENT_DELAY rg_v1$D_IN; - if (rg_v2$EN) rg_v2 <= `BSV_ASSIGNMENT_DELAY rg_v2$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - intDiv_rg_denom2 = 32'hAAAAAAAA; - intDiv_rg_denom_is_signed = 1'h0; - intDiv_rg_n = 32'hAAAAAAAA; - intDiv_rg_numer_is_signed = 1'h0; - intDiv_rg_quo = 32'hAAAAAAAA; - intDiv_rg_quoIsNeg = 1'h0; - intDiv_rg_remIsNeg = 1'h0; - intDiv_rg_state = 3'h2; - rg_f3 = 3'h2; - rg_is_OP_not_OP_32 = 1'h0; - rg_state = 2'h2; - rg_v1 = 32'hAAAAAAAA; - rg_v2 = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && cfg_verbosity > 4'd1) - $display(" RISCV_MBox.rl_mul"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - begin - v__h3263 = $stime; - #0; - end - v__h3257 = v__h3263 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $display("%0d: ERROR: RISCV_MBox.rl_mul: illegal f3.", v__h3257); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $display(" f3 0x%0h v1 0x%0h v2 0x%0h", rg_f3, rg_v1, rg_v2); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && - (!rg_is_OP_not_OP_32 || - rg_f3 != 3'b0 && rg_f3 != 3'b001 && rg_f3 != 3'b011 && - rg_f3 != 3'b010)) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkRISCV_MBox - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v deleted file mode 100644 index c88e21cd..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v +++ /dev/null @@ -1,298 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// m_near_mem_io_addr_base O 64 const -// m_near_mem_io_addr_size O 64 const -// m_near_mem_io_addr_lim O 64 const -// m_plic_addr_base O 64 const -// m_plic_addr_size O 64 const -// m_plic_addr_lim O 64 const -// m_uart0_addr_base O 64 const -// m_uart0_addr_size O 64 const -// m_uart0_addr_lim O 64 const -// m_boot_rom_addr_base O 64 const -// m_boot_rom_addr_size O 64 const -// m_boot_rom_addr_lim O 64 const -// m_mem0_controller_addr_base O 64 const -// m_mem0_controller_addr_size O 64 const -// m_mem0_controller_addr_lim O 64 const -// m_tcm_addr_base O 64 const -// m_tcm_addr_size O 64 const -// m_tcm_addr_lim O 64 const -// m_is_mem_addr O 1 -// m_is_IO_addr O 1 -// m_is_near_mem_IO_addr O 1 -// m_pc_reset_value O 64 const -// m_mtvec_reset_value O 64 const -// m_nmivec_reset_value O 64 const -// CLK I 1 unused -// RST_N I 1 unused -// m_is_mem_addr_addr I 64 -// m_is_IO_addr_addr I 64 -// m_is_near_mem_IO_addr_addr I 64 -// -// Combinational paths from inputs to outputs: -// m_is_mem_addr_addr -> m_is_mem_addr -// m_is_IO_addr_addr -> m_is_IO_addr -// m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Map(CLK, - RST_N, - - m_near_mem_io_addr_base, - - m_near_mem_io_addr_size, - - m_near_mem_io_addr_lim, - - m_plic_addr_base, - - m_plic_addr_size, - - m_plic_addr_lim, - - m_uart0_addr_base, - - m_uart0_addr_size, - - m_uart0_addr_lim, - - m_boot_rom_addr_base, - - m_boot_rom_addr_size, - - m_boot_rom_addr_lim, - - m_mem0_controller_addr_base, - - m_mem0_controller_addr_size, - - m_mem0_controller_addr_lim, - - m_tcm_addr_base, - - m_tcm_addr_size, - - m_tcm_addr_lim, - - m_is_mem_addr_addr, - m_is_mem_addr, - - m_is_IO_addr_addr, - m_is_IO_addr, - - m_is_near_mem_IO_addr_addr, - m_is_near_mem_IO_addr, - - m_pc_reset_value, - - m_mtvec_reset_value, - - m_nmivec_reset_value); - input CLK; - input RST_N; - - // value method m_near_mem_io_addr_base - output [63 : 0] m_near_mem_io_addr_base; - - // value method m_near_mem_io_addr_size - output [63 : 0] m_near_mem_io_addr_size; - - // value method m_near_mem_io_addr_lim - output [63 : 0] m_near_mem_io_addr_lim; - - // value method m_plic_addr_base - output [63 : 0] m_plic_addr_base; - - // value method m_plic_addr_size - output [63 : 0] m_plic_addr_size; - - // value method m_plic_addr_lim - output [63 : 0] m_plic_addr_lim; - - // value method m_uart0_addr_base - output [63 : 0] m_uart0_addr_base; - - // value method m_uart0_addr_size - output [63 : 0] m_uart0_addr_size; - - // value method m_uart0_addr_lim - output [63 : 0] m_uart0_addr_lim; - - // value method m_boot_rom_addr_base - output [63 : 0] m_boot_rom_addr_base; - - // value method m_boot_rom_addr_size - output [63 : 0] m_boot_rom_addr_size; - - // value method m_boot_rom_addr_lim - output [63 : 0] m_boot_rom_addr_lim; - - // value method m_mem0_controller_addr_base - output [63 : 0] m_mem0_controller_addr_base; - - // value method m_mem0_controller_addr_size - output [63 : 0] m_mem0_controller_addr_size; - - // value method m_mem0_controller_addr_lim - output [63 : 0] m_mem0_controller_addr_lim; - - // value method m_tcm_addr_base - output [63 : 0] m_tcm_addr_base; - - // value method m_tcm_addr_size - output [63 : 0] m_tcm_addr_size; - - // value method m_tcm_addr_lim - output [63 : 0] m_tcm_addr_lim; - - // value method m_is_mem_addr - input [63 : 0] m_is_mem_addr_addr; - output m_is_mem_addr; - - // value method m_is_IO_addr - input [63 : 0] m_is_IO_addr_addr; - output m_is_IO_addr; - - // value method m_is_near_mem_IO_addr - input [63 : 0] m_is_near_mem_IO_addr_addr; - output m_is_near_mem_IO_addr; - - // value method m_pc_reset_value - output [63 : 0] m_pc_reset_value; - - // value method m_mtvec_reset_value - output [63 : 0] m_mtvec_reset_value; - - // value method m_nmivec_reset_value - output [63 : 0] m_nmivec_reset_value; - - // signals for module outputs - wire [63 : 0] m_boot_rom_addr_base, - m_boot_rom_addr_lim, - m_boot_rom_addr_size, - m_mem0_controller_addr_base, - m_mem0_controller_addr_lim, - m_mem0_controller_addr_size, - m_mtvec_reset_value, - m_near_mem_io_addr_base, - m_near_mem_io_addr_lim, - m_near_mem_io_addr_size, - m_nmivec_reset_value, - m_pc_reset_value, - m_plic_addr_base, - m_plic_addr_lim, - m_plic_addr_size, - m_tcm_addr_base, - m_tcm_addr_lim, - m_tcm_addr_size, - m_uart0_addr_base, - m_uart0_addr_lim, - m_uart0_addr_size; - wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; - - // value method m_near_mem_io_addr_base - assign m_near_mem_io_addr_base = 64'h0000000002000000 ; - - // value method m_near_mem_io_addr_size - assign m_near_mem_io_addr_size = 64'h000000000000C000 ; - - // value method m_near_mem_io_addr_lim - assign m_near_mem_io_addr_lim = 64'd33603584 ; - - // value method m_plic_addr_base - assign m_plic_addr_base = 64'h000000000C000000 ; - - // value method m_plic_addr_size - assign m_plic_addr_size = 64'h0000000000400000 ; - - // value method m_plic_addr_lim - assign m_plic_addr_lim = 64'd205520896 ; - - // value method m_uart0_addr_base - assign m_uart0_addr_base = 64'h00000000C0000000 ; - - // value method m_uart0_addr_size - assign m_uart0_addr_size = 64'h0000000000000080 ; - - // value method m_uart0_addr_lim - assign m_uart0_addr_lim = 64'h00000000C0000080 ; - - // value method m_boot_rom_addr_base - assign m_boot_rom_addr_base = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_size - assign m_boot_rom_addr_size = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_lim - assign m_boot_rom_addr_lim = 64'd8192 ; - - // value method m_mem0_controller_addr_base - assign m_mem0_controller_addr_base = 64'h0000000080000000 ; - - // value method m_mem0_controller_addr_size - assign m_mem0_controller_addr_size = 64'h0000000010000000 ; - - // value method m_mem0_controller_addr_lim - assign m_mem0_controller_addr_lim = 64'h0000000090000000 ; - - // value method m_tcm_addr_base - assign m_tcm_addr_base = 64'h0 ; - - // value method m_tcm_addr_size - assign m_tcm_addr_size = 64'd0 ; - - // value method m_tcm_addr_lim - assign m_tcm_addr_lim = 64'd0 ; - - // value method m_is_mem_addr - assign m_is_mem_addr = - m_is_mem_addr_addr >= 64'h0000000000001000 && - m_is_mem_addr_addr < 64'd8192 || - m_is_mem_addr_addr >= 64'h0000000080000000 && - m_is_mem_addr_addr < 64'h0000000090000000 ; - - // value method m_is_IO_addr - assign m_is_IO_addr = - m_is_IO_addr_addr >= 64'h0000000002000000 && - m_is_IO_addr_addr < 64'd33603584 || - m_is_IO_addr_addr >= 64'h000000000C000000 && - m_is_IO_addr_addr < 64'd205520896 || - m_is_IO_addr_addr >= 64'h00000000C0000000 && - m_is_IO_addr_addr < 64'h00000000C0000080 ; - - // value method m_is_near_mem_IO_addr - assign m_is_near_mem_IO_addr = - m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 && - m_is_near_mem_IO_addr_addr < 64'd33603584 ; - - // value method m_pc_reset_value - assign m_pc_reset_value = 64'h0000000000001000 ; - - // value method m_mtvec_reset_value - assign m_mtvec_reset_value = 64'h0000000000001000 ; - - // value method m_nmivec_reset_value - assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ; -endmodule // mkSoC_Map - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v deleted file mode 100644 index e83eb2fd..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v +++ /dev/null @@ -1,2296 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// to_raw_mem_response_put I 256 -// put_from_console_put I 8 reg -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_set_verbosity I 1 -// EN_to_raw_mem_response_put I 1 -// EN_put_from_console_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Top(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [7 : 0] get_to_console_get, status; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_set_verbosity, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule boot_rom - wire [63 : 0] boot_rom$set_addr_map_addr_base, - boot_rom$set_addr_map_addr_lim, - boot_rom$slave_araddr, - boot_rom$slave_awaddr, - boot_rom$slave_rdata, - boot_rom$slave_wdata; - wire [7 : 0] boot_rom$slave_arlen, - boot_rom$slave_awlen, - boot_rom$slave_wstrb; - wire [3 : 0] boot_rom$slave_arcache, - boot_rom$slave_arid, - boot_rom$slave_arqos, - boot_rom$slave_arregion, - boot_rom$slave_awcache, - boot_rom$slave_awid, - boot_rom$slave_awqos, - boot_rom$slave_awregion, - boot_rom$slave_bid, - boot_rom$slave_rid; - wire [2 : 0] boot_rom$slave_arprot, - boot_rom$slave_arsize, - boot_rom$slave_awprot, - boot_rom$slave_awsize; - wire [1 : 0] boot_rom$slave_arburst, - boot_rom$slave_awburst, - boot_rom$slave_bresp, - boot_rom$slave_rresp; - wire boot_rom$EN_set_addr_map, - boot_rom$slave_arlock, - boot_rom$slave_arready, - boot_rom$slave_arvalid, - boot_rom$slave_awlock, - boot_rom$slave_awready, - boot_rom$slave_awvalid, - boot_rom$slave_bready, - boot_rom$slave_bvalid, - boot_rom$slave_rlast, - boot_rom$slave_rready, - boot_rom$slave_rvalid, - boot_rom$slave_wlast, - boot_rom$slave_wready, - boot_rom$slave_wvalid; - - // ports of submodule boot_rom_axi4_deburster - wire [63 : 0] boot_rom_axi4_deburster$from_master_araddr, - boot_rom_axi4_deburster$from_master_awaddr, - boot_rom_axi4_deburster$from_master_rdata, - boot_rom_axi4_deburster$from_master_wdata, - boot_rom_axi4_deburster$to_slave_araddr, - boot_rom_axi4_deburster$to_slave_awaddr, - boot_rom_axi4_deburster$to_slave_rdata, - boot_rom_axi4_deburster$to_slave_wdata; - wire [7 : 0] boot_rom_axi4_deburster$from_master_arlen, - boot_rom_axi4_deburster$from_master_awlen, - boot_rom_axi4_deburster$from_master_wstrb, - boot_rom_axi4_deburster$to_slave_arlen, - boot_rom_axi4_deburster$to_slave_awlen, - boot_rom_axi4_deburster$to_slave_wstrb; - wire [3 : 0] boot_rom_axi4_deburster$from_master_arcache, - boot_rom_axi4_deburster$from_master_arid, - boot_rom_axi4_deburster$from_master_arqos, - boot_rom_axi4_deburster$from_master_arregion, - boot_rom_axi4_deburster$from_master_awcache, - boot_rom_axi4_deburster$from_master_awid, - boot_rom_axi4_deburster$from_master_awqos, - boot_rom_axi4_deburster$from_master_awregion, - boot_rom_axi4_deburster$from_master_bid, - boot_rom_axi4_deburster$from_master_rid, - boot_rom_axi4_deburster$to_slave_arcache, - boot_rom_axi4_deburster$to_slave_arid, - boot_rom_axi4_deburster$to_slave_arqos, - boot_rom_axi4_deburster$to_slave_arregion, - boot_rom_axi4_deburster$to_slave_awcache, - boot_rom_axi4_deburster$to_slave_awid, - boot_rom_axi4_deburster$to_slave_awqos, - boot_rom_axi4_deburster$to_slave_awregion, - boot_rom_axi4_deburster$to_slave_bid, - boot_rom_axi4_deburster$to_slave_rid; - wire [2 : 0] boot_rom_axi4_deburster$from_master_arprot, - boot_rom_axi4_deburster$from_master_arsize, - boot_rom_axi4_deburster$from_master_awprot, - boot_rom_axi4_deburster$from_master_awsize, - boot_rom_axi4_deburster$to_slave_arprot, - boot_rom_axi4_deburster$to_slave_arsize, - boot_rom_axi4_deburster$to_slave_awprot, - boot_rom_axi4_deburster$to_slave_awsize; - wire [1 : 0] boot_rom_axi4_deburster$from_master_arburst, - boot_rom_axi4_deburster$from_master_awburst, - boot_rom_axi4_deburster$from_master_bresp, - boot_rom_axi4_deburster$from_master_rresp, - boot_rom_axi4_deburster$to_slave_arburst, - boot_rom_axi4_deburster$to_slave_awburst, - boot_rom_axi4_deburster$to_slave_bresp, - boot_rom_axi4_deburster$to_slave_rresp; - wire boot_rom_axi4_deburster$EN_reset, - boot_rom_axi4_deburster$from_master_arlock, - boot_rom_axi4_deburster$from_master_arready, - boot_rom_axi4_deburster$from_master_arvalid, - boot_rom_axi4_deburster$from_master_awlock, - boot_rom_axi4_deburster$from_master_awready, - boot_rom_axi4_deburster$from_master_awvalid, - boot_rom_axi4_deburster$from_master_bready, - boot_rom_axi4_deburster$from_master_bvalid, - boot_rom_axi4_deburster$from_master_rlast, - boot_rom_axi4_deburster$from_master_rready, - boot_rom_axi4_deburster$from_master_rvalid, - boot_rom_axi4_deburster$from_master_wlast, - boot_rom_axi4_deburster$from_master_wready, - boot_rom_axi4_deburster$from_master_wvalid, - boot_rom_axi4_deburster$to_slave_arlock, - boot_rom_axi4_deburster$to_slave_arready, - boot_rom_axi4_deburster$to_slave_arvalid, - boot_rom_axi4_deburster$to_slave_awlock, - boot_rom_axi4_deburster$to_slave_awready, - boot_rom_axi4_deburster$to_slave_awvalid, - boot_rom_axi4_deburster$to_slave_bready, - boot_rom_axi4_deburster$to_slave_bvalid, - boot_rom_axi4_deburster$to_slave_rlast, - boot_rom_axi4_deburster$to_slave_rready, - boot_rom_axi4_deburster$to_slave_rvalid, - boot_rom_axi4_deburster$to_slave_wlast, - boot_rom_axi4_deburster$to_slave_wready, - boot_rom_axi4_deburster$to_slave_wvalid; - - // ports of submodule core - wire [63 : 0] core$cpu_dmem_master_araddr, - core$cpu_dmem_master_awaddr, - core$cpu_dmem_master_rdata, - core$cpu_dmem_master_wdata, - core$cpu_imem_master_araddr, - core$cpu_imem_master_awaddr, - core$cpu_imem_master_rdata, - core$cpu_imem_master_wdata, - core$set_verbosity_logdelay; - wire [7 : 0] core$cpu_dmem_master_arlen, - core$cpu_dmem_master_awlen, - core$cpu_dmem_master_wstrb, - core$cpu_imem_master_arlen, - core$cpu_imem_master_awlen, - core$cpu_imem_master_wstrb; - wire [3 : 0] core$cpu_dmem_master_arcache, - core$cpu_dmem_master_arid, - core$cpu_dmem_master_arqos, - core$cpu_dmem_master_arregion, - core$cpu_dmem_master_awcache, - core$cpu_dmem_master_awid, - core$cpu_dmem_master_awqos, - core$cpu_dmem_master_awregion, - core$cpu_dmem_master_bid, - core$cpu_dmem_master_rid, - core$cpu_imem_master_arcache, - core$cpu_imem_master_arid, - core$cpu_imem_master_arqos, - core$cpu_imem_master_arregion, - core$cpu_imem_master_awcache, - core$cpu_imem_master_awid, - core$cpu_imem_master_awqos, - core$cpu_imem_master_awregion, - core$cpu_imem_master_bid, - core$cpu_imem_master_rid, - core$set_verbosity_verbosity; - wire [2 : 0] core$cpu_dmem_master_arprot, - core$cpu_dmem_master_arsize, - core$cpu_dmem_master_awprot, - core$cpu_dmem_master_awsize, - core$cpu_imem_master_arprot, - core$cpu_imem_master_arsize, - core$cpu_imem_master_awprot, - core$cpu_imem_master_awsize; - wire [1 : 0] core$cpu_dmem_master_arburst, - core$cpu_dmem_master_awburst, - core$cpu_dmem_master_bresp, - core$cpu_dmem_master_rresp, - core$cpu_imem_master_arburst, - core$cpu_imem_master_awburst, - core$cpu_imem_master_bresp, - core$cpu_imem_master_rresp; - wire core$EN_cpu_reset_server_request_put, - core$EN_cpu_reset_server_response_get, - core$EN_set_verbosity, - core$RDY_cpu_reset_server_request_put, - core$RDY_cpu_reset_server_response_get, - core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - core$cpu_dmem_master_arlock, - core$cpu_dmem_master_arready, - core$cpu_dmem_master_arvalid, - core$cpu_dmem_master_awlock, - core$cpu_dmem_master_awready, - core$cpu_dmem_master_awvalid, - core$cpu_dmem_master_bready, - core$cpu_dmem_master_bvalid, - core$cpu_dmem_master_rlast, - core$cpu_dmem_master_rready, - core$cpu_dmem_master_rvalid, - core$cpu_dmem_master_wlast, - core$cpu_dmem_master_wready, - core$cpu_dmem_master_wvalid, - core$cpu_imem_master_arlock, - core$cpu_imem_master_arready, - core$cpu_imem_master_arvalid, - core$cpu_imem_master_awlock, - core$cpu_imem_master_awready, - core$cpu_imem_master_awvalid, - core$cpu_imem_master_bready, - core$cpu_imem_master_bvalid, - core$cpu_imem_master_rlast, - core$cpu_imem_master_rready, - core$cpu_imem_master_rvalid, - core$cpu_imem_master_wlast, - core$cpu_imem_master_wready, - core$cpu_imem_master_wvalid, - core$cpu_reset_server_request_put, - core$nmi_req_set_not_clear; - - // ports of submodule fabric - wire [63 : 0] fabric$v_from_masters_0_araddr, - fabric$v_from_masters_0_awaddr, - fabric$v_from_masters_0_rdata, - fabric$v_from_masters_0_wdata, - fabric$v_from_masters_1_araddr, - fabric$v_from_masters_1_awaddr, - fabric$v_from_masters_1_rdata, - fabric$v_from_masters_1_wdata, - fabric$v_to_slaves_0_araddr, - fabric$v_to_slaves_0_awaddr, - fabric$v_to_slaves_0_rdata, - fabric$v_to_slaves_0_wdata, - fabric$v_to_slaves_1_araddr, - fabric$v_to_slaves_1_awaddr, - fabric$v_to_slaves_1_rdata, - fabric$v_to_slaves_1_wdata, - fabric$v_to_slaves_2_araddr, - fabric$v_to_slaves_2_awaddr, - fabric$v_to_slaves_2_rdata, - fabric$v_to_slaves_2_wdata; - wire [7 : 0] fabric$v_from_masters_0_arlen, - fabric$v_from_masters_0_awlen, - fabric$v_from_masters_0_wstrb, - fabric$v_from_masters_1_arlen, - fabric$v_from_masters_1_awlen, - fabric$v_from_masters_1_wstrb, - fabric$v_to_slaves_0_arlen, - fabric$v_to_slaves_0_awlen, - fabric$v_to_slaves_0_wstrb, - fabric$v_to_slaves_1_arlen, - fabric$v_to_slaves_1_awlen, - fabric$v_to_slaves_1_wstrb, - fabric$v_to_slaves_2_arlen, - fabric$v_to_slaves_2_awlen, - fabric$v_to_slaves_2_wstrb; - wire [3 : 0] fabric$set_verbosity_verbosity, - fabric$v_from_masters_0_arcache, - fabric$v_from_masters_0_arid, - fabric$v_from_masters_0_arqos, - fabric$v_from_masters_0_arregion, - fabric$v_from_masters_0_awcache, - fabric$v_from_masters_0_awid, - fabric$v_from_masters_0_awqos, - fabric$v_from_masters_0_awregion, - fabric$v_from_masters_0_bid, - fabric$v_from_masters_0_rid, - fabric$v_from_masters_1_arcache, - fabric$v_from_masters_1_arid, - fabric$v_from_masters_1_arqos, - fabric$v_from_masters_1_arregion, - fabric$v_from_masters_1_awcache, - fabric$v_from_masters_1_awid, - fabric$v_from_masters_1_awqos, - fabric$v_from_masters_1_awregion, - fabric$v_from_masters_1_bid, - fabric$v_from_masters_1_rid, - fabric$v_to_slaves_0_arcache, - fabric$v_to_slaves_0_arid, - fabric$v_to_slaves_0_arqos, - fabric$v_to_slaves_0_arregion, - fabric$v_to_slaves_0_awcache, - fabric$v_to_slaves_0_awid, - fabric$v_to_slaves_0_awqos, - fabric$v_to_slaves_0_awregion, - fabric$v_to_slaves_0_bid, - fabric$v_to_slaves_0_rid, - fabric$v_to_slaves_1_arcache, - fabric$v_to_slaves_1_arid, - fabric$v_to_slaves_1_arqos, - fabric$v_to_slaves_1_arregion, - fabric$v_to_slaves_1_awcache, - fabric$v_to_slaves_1_awid, - fabric$v_to_slaves_1_awqos, - fabric$v_to_slaves_1_awregion, - fabric$v_to_slaves_1_bid, - fabric$v_to_slaves_1_rid, - fabric$v_to_slaves_2_arcache, - fabric$v_to_slaves_2_arid, - fabric$v_to_slaves_2_arqos, - fabric$v_to_slaves_2_arregion, - fabric$v_to_slaves_2_awcache, - fabric$v_to_slaves_2_awid, - fabric$v_to_slaves_2_awqos, - fabric$v_to_slaves_2_awregion, - fabric$v_to_slaves_2_bid, - fabric$v_to_slaves_2_rid; - wire [2 : 0] fabric$v_from_masters_0_arprot, - fabric$v_from_masters_0_arsize, - fabric$v_from_masters_0_awprot, - fabric$v_from_masters_0_awsize, - fabric$v_from_masters_1_arprot, - fabric$v_from_masters_1_arsize, - fabric$v_from_masters_1_awprot, - fabric$v_from_masters_1_awsize, - fabric$v_to_slaves_0_arprot, - fabric$v_to_slaves_0_arsize, - fabric$v_to_slaves_0_awprot, - fabric$v_to_slaves_0_awsize, - fabric$v_to_slaves_1_arprot, - fabric$v_to_slaves_1_arsize, - fabric$v_to_slaves_1_awprot, - fabric$v_to_slaves_1_awsize, - fabric$v_to_slaves_2_arprot, - fabric$v_to_slaves_2_arsize, - fabric$v_to_slaves_2_awprot, - fabric$v_to_slaves_2_awsize; - wire [1 : 0] fabric$v_from_masters_0_arburst, - fabric$v_from_masters_0_awburst, - fabric$v_from_masters_0_bresp, - fabric$v_from_masters_0_rresp, - fabric$v_from_masters_1_arburst, - fabric$v_from_masters_1_awburst, - fabric$v_from_masters_1_bresp, - fabric$v_from_masters_1_rresp, - fabric$v_to_slaves_0_arburst, - fabric$v_to_slaves_0_awburst, - fabric$v_to_slaves_0_bresp, - fabric$v_to_slaves_0_rresp, - fabric$v_to_slaves_1_arburst, - fabric$v_to_slaves_1_awburst, - fabric$v_to_slaves_1_bresp, - fabric$v_to_slaves_1_rresp, - fabric$v_to_slaves_2_arburst, - fabric$v_to_slaves_2_awburst, - fabric$v_to_slaves_2_bresp, - fabric$v_to_slaves_2_rresp; - wire fabric$EN_reset, - fabric$EN_set_verbosity, - fabric$RDY_reset, - fabric$v_from_masters_0_arlock, - fabric$v_from_masters_0_arready, - fabric$v_from_masters_0_arvalid, - fabric$v_from_masters_0_awlock, - fabric$v_from_masters_0_awready, - fabric$v_from_masters_0_awvalid, - fabric$v_from_masters_0_bready, - fabric$v_from_masters_0_bvalid, - fabric$v_from_masters_0_rlast, - fabric$v_from_masters_0_rready, - fabric$v_from_masters_0_rvalid, - fabric$v_from_masters_0_wlast, - fabric$v_from_masters_0_wready, - fabric$v_from_masters_0_wvalid, - fabric$v_from_masters_1_arlock, - fabric$v_from_masters_1_arready, - fabric$v_from_masters_1_arvalid, - fabric$v_from_masters_1_awlock, - fabric$v_from_masters_1_awready, - fabric$v_from_masters_1_awvalid, - fabric$v_from_masters_1_bready, - fabric$v_from_masters_1_bvalid, - fabric$v_from_masters_1_rlast, - fabric$v_from_masters_1_rready, - fabric$v_from_masters_1_rvalid, - fabric$v_from_masters_1_wlast, - fabric$v_from_masters_1_wready, - fabric$v_from_masters_1_wvalid, - fabric$v_to_slaves_0_arlock, - fabric$v_to_slaves_0_arready, - fabric$v_to_slaves_0_arvalid, - fabric$v_to_slaves_0_awlock, - fabric$v_to_slaves_0_awready, - fabric$v_to_slaves_0_awvalid, - fabric$v_to_slaves_0_bready, - fabric$v_to_slaves_0_bvalid, - fabric$v_to_slaves_0_rlast, - fabric$v_to_slaves_0_rready, - fabric$v_to_slaves_0_rvalid, - fabric$v_to_slaves_0_wlast, - fabric$v_to_slaves_0_wready, - fabric$v_to_slaves_0_wvalid, - fabric$v_to_slaves_1_arlock, - fabric$v_to_slaves_1_arready, - fabric$v_to_slaves_1_arvalid, - fabric$v_to_slaves_1_awlock, - fabric$v_to_slaves_1_awready, - fabric$v_to_slaves_1_awvalid, - fabric$v_to_slaves_1_bready, - fabric$v_to_slaves_1_bvalid, - fabric$v_to_slaves_1_rlast, - fabric$v_to_slaves_1_rready, - fabric$v_to_slaves_1_rvalid, - fabric$v_to_slaves_1_wlast, - fabric$v_to_slaves_1_wready, - fabric$v_to_slaves_1_wvalid, - fabric$v_to_slaves_2_arlock, - fabric$v_to_slaves_2_arready, - fabric$v_to_slaves_2_arvalid, - fabric$v_to_slaves_2_awlock, - fabric$v_to_slaves_2_awready, - fabric$v_to_slaves_2_awvalid, - fabric$v_to_slaves_2_bready, - fabric$v_to_slaves_2_bvalid, - fabric$v_to_slaves_2_rlast, - fabric$v_to_slaves_2_rready, - fabric$v_to_slaves_2_rvalid, - fabric$v_to_slaves_2_wlast, - fabric$v_to_slaves_2_wready, - fabric$v_to_slaves_2_wvalid; - - // ports of submodule mem0_controller - wire [352 : 0] mem0_controller$to_raw_mem_request_get; - wire [255 : 0] mem0_controller$to_raw_mem_response_put; - wire [63 : 0] mem0_controller$set_addr_map_addr_base, - mem0_controller$set_addr_map_addr_lim, - mem0_controller$set_watch_tohost_tohost_addr, - mem0_controller$slave_araddr, - mem0_controller$slave_awaddr, - mem0_controller$slave_rdata, - mem0_controller$slave_wdata; - wire [7 : 0] mem0_controller$slave_arlen, - mem0_controller$slave_awlen, - mem0_controller$slave_wstrb, - mem0_controller$status; - wire [3 : 0] mem0_controller$slave_arcache, - mem0_controller$slave_arid, - mem0_controller$slave_arqos, - mem0_controller$slave_arregion, - mem0_controller$slave_awcache, - mem0_controller$slave_awid, - mem0_controller$slave_awqos, - mem0_controller$slave_awregion, - mem0_controller$slave_bid, - mem0_controller$slave_rid; - wire [2 : 0] mem0_controller$slave_arprot, - mem0_controller$slave_arsize, - mem0_controller$slave_awprot, - mem0_controller$slave_awsize; - wire [1 : 0] mem0_controller$slave_arburst, - mem0_controller$slave_awburst, - mem0_controller$slave_bresp, - mem0_controller$slave_rresp; - wire mem0_controller$EN_server_reset_request_put, - mem0_controller$EN_server_reset_response_get, - mem0_controller$EN_set_addr_map, - mem0_controller$EN_set_watch_tohost, - mem0_controller$EN_to_raw_mem_request_get, - mem0_controller$EN_to_raw_mem_response_put, - mem0_controller$RDY_server_reset_request_put, - mem0_controller$RDY_server_reset_response_get, - mem0_controller$RDY_set_addr_map, - mem0_controller$RDY_to_raw_mem_request_get, - mem0_controller$RDY_to_raw_mem_response_put, - mem0_controller$set_watch_tohost_watch_tohost, - mem0_controller$slave_arlock, - mem0_controller$slave_arready, - mem0_controller$slave_arvalid, - mem0_controller$slave_awlock, - mem0_controller$slave_awready, - mem0_controller$slave_awvalid, - mem0_controller$slave_bready, - mem0_controller$slave_bvalid, - mem0_controller$slave_rlast, - mem0_controller$slave_rready, - mem0_controller$slave_rvalid, - mem0_controller$slave_wlast, - mem0_controller$slave_wready, - mem0_controller$slave_wvalid; - - // ports of submodule mem0_controller_axi4_deburster - wire [63 : 0] mem0_controller_axi4_deburster$from_master_araddr, - mem0_controller_axi4_deburster$from_master_awaddr, - mem0_controller_axi4_deburster$from_master_rdata, - mem0_controller_axi4_deburster$from_master_wdata, - mem0_controller_axi4_deburster$to_slave_araddr, - mem0_controller_axi4_deburster$to_slave_awaddr, - mem0_controller_axi4_deburster$to_slave_rdata, - mem0_controller_axi4_deburster$to_slave_wdata; - wire [7 : 0] mem0_controller_axi4_deburster$from_master_arlen, - mem0_controller_axi4_deburster$from_master_awlen, - mem0_controller_axi4_deburster$from_master_wstrb, - mem0_controller_axi4_deburster$to_slave_arlen, - mem0_controller_axi4_deburster$to_slave_awlen, - mem0_controller_axi4_deburster$to_slave_wstrb; - wire [3 : 0] mem0_controller_axi4_deburster$from_master_arcache, - mem0_controller_axi4_deburster$from_master_arid, - mem0_controller_axi4_deburster$from_master_arqos, - mem0_controller_axi4_deburster$from_master_arregion, - mem0_controller_axi4_deburster$from_master_awcache, - mem0_controller_axi4_deburster$from_master_awid, - mem0_controller_axi4_deburster$from_master_awqos, - mem0_controller_axi4_deburster$from_master_awregion, - mem0_controller_axi4_deburster$from_master_bid, - mem0_controller_axi4_deburster$from_master_rid, - mem0_controller_axi4_deburster$to_slave_arcache, - mem0_controller_axi4_deburster$to_slave_arid, - mem0_controller_axi4_deburster$to_slave_arqos, - mem0_controller_axi4_deburster$to_slave_arregion, - mem0_controller_axi4_deburster$to_slave_awcache, - mem0_controller_axi4_deburster$to_slave_awid, - mem0_controller_axi4_deburster$to_slave_awqos, - mem0_controller_axi4_deburster$to_slave_awregion, - mem0_controller_axi4_deburster$to_slave_bid, - mem0_controller_axi4_deburster$to_slave_rid; - wire [2 : 0] mem0_controller_axi4_deburster$from_master_arprot, - mem0_controller_axi4_deburster$from_master_arsize, - mem0_controller_axi4_deburster$from_master_awprot, - mem0_controller_axi4_deburster$from_master_awsize, - mem0_controller_axi4_deburster$to_slave_arprot, - mem0_controller_axi4_deburster$to_slave_arsize, - mem0_controller_axi4_deburster$to_slave_awprot, - mem0_controller_axi4_deburster$to_slave_awsize; - wire [1 : 0] mem0_controller_axi4_deburster$from_master_arburst, - mem0_controller_axi4_deburster$from_master_awburst, - mem0_controller_axi4_deburster$from_master_bresp, - mem0_controller_axi4_deburster$from_master_rresp, - mem0_controller_axi4_deburster$to_slave_arburst, - mem0_controller_axi4_deburster$to_slave_awburst, - mem0_controller_axi4_deburster$to_slave_bresp, - mem0_controller_axi4_deburster$to_slave_rresp; - wire mem0_controller_axi4_deburster$EN_reset, - mem0_controller_axi4_deburster$from_master_arlock, - mem0_controller_axi4_deburster$from_master_arready, - mem0_controller_axi4_deburster$from_master_arvalid, - mem0_controller_axi4_deburster$from_master_awlock, - mem0_controller_axi4_deburster$from_master_awready, - mem0_controller_axi4_deburster$from_master_awvalid, - mem0_controller_axi4_deburster$from_master_bready, - mem0_controller_axi4_deburster$from_master_bvalid, - mem0_controller_axi4_deburster$from_master_rlast, - mem0_controller_axi4_deburster$from_master_rready, - mem0_controller_axi4_deburster$from_master_rvalid, - mem0_controller_axi4_deburster$from_master_wlast, - mem0_controller_axi4_deburster$from_master_wready, - mem0_controller_axi4_deburster$from_master_wvalid, - mem0_controller_axi4_deburster$to_slave_arlock, - mem0_controller_axi4_deburster$to_slave_arready, - mem0_controller_axi4_deburster$to_slave_arvalid, - mem0_controller_axi4_deburster$to_slave_awlock, - mem0_controller_axi4_deburster$to_slave_awready, - mem0_controller_axi4_deburster$to_slave_awvalid, - mem0_controller_axi4_deburster$to_slave_bready, - mem0_controller_axi4_deburster$to_slave_bvalid, - mem0_controller_axi4_deburster$to_slave_rlast, - mem0_controller_axi4_deburster$to_slave_rready, - mem0_controller_axi4_deburster$to_slave_rvalid, - mem0_controller_axi4_deburster$to_slave_wlast, - mem0_controller_axi4_deburster$to_slave_wready, - mem0_controller_axi4_deburster$to_slave_wvalid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // ports of submodule uart0 - wire [63 : 0] uart0$set_addr_map_addr_base, - uart0$set_addr_map_addr_lim, - uart0$slave_araddr, - uart0$slave_awaddr, - uart0$slave_rdata, - uart0$slave_wdata; - wire [7 : 0] uart0$get_to_console_get, - uart0$put_from_console_put, - uart0$slave_arlen, - uart0$slave_awlen, - uart0$slave_wstrb; - wire [3 : 0] uart0$slave_arcache, - uart0$slave_arid, - uart0$slave_arqos, - uart0$slave_arregion, - uart0$slave_awcache, - uart0$slave_awid, - uart0$slave_awqos, - uart0$slave_awregion, - uart0$slave_bid, - uart0$slave_rid; - wire [2 : 0] uart0$slave_arprot, - uart0$slave_arsize, - uart0$slave_awprot, - uart0$slave_awsize; - wire [1 : 0] uart0$slave_arburst, - uart0$slave_awburst, - uart0$slave_bresp, - uart0$slave_rresp; - wire uart0$EN_get_to_console_get, - uart0$EN_put_from_console_put, - uart0$EN_server_reset_request_put, - uart0$EN_server_reset_response_get, - uart0$EN_set_addr_map, - uart0$RDY_get_to_console_get, - uart0$RDY_put_from_console_put, - uart0$RDY_server_reset_request_put, - uart0$RDY_server_reset_response_get, - uart0$intr, - uart0$slave_arlock, - uart0$slave_arready, - uart0$slave_arvalid, - uart0$slave_awlock, - uart0$slave_awready, - uart0$slave_awvalid, - uart0$slave_bready, - uart0$slave_bvalid, - uart0$slave_rlast, - uart0$slave_rready, - uart0$slave_rvalid, - uart0$slave_wlast, - uart0$slave_wready, - uart0$slave_wvalid; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_connect_external_interrupt_requests, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_addr_channel_5, - CAN_FIRE_RL_rl_rd_addr_channel_6, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, - CAN_FIRE_RL_rl_rd_data_channel_5, - CAN_FIRE_RL_rl_rd_data_channel_6, - CAN_FIRE_RL_rl_reset_complete_initial, - CAN_FIRE_RL_rl_reset_start_initial, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_addr_channel_5, - CAN_FIRE_RL_rl_wr_addr_channel_6, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_data_channel_5, - CAN_FIRE_RL_rl_wr_data_channel_6, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, - CAN_FIRE_RL_rl_wr_response_channel_5, - CAN_FIRE_RL_rl_wr_response_channel_6, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_set_verbosity, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_connect_external_interrupt_requests, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_addr_channel_5, - WILL_FIRE_RL_rl_rd_addr_channel_6, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, - WILL_FIRE_RL_rl_rd_data_channel_5, - WILL_FIRE_RL_rl_rd_data_channel_6, - WILL_FIRE_RL_rl_reset_complete_initial, - WILL_FIRE_RL_rl_reset_start_initial, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_addr_channel_5, - WILL_FIRE_RL_rl_wr_addr_channel_6, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_data_channel_5, - WILL_FIRE_RL_rl_wr_data_channel_6, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, - WILL_FIRE_RL_rl_wr_response_channel_5, - WILL_FIRE_RL_rl_wr_response_channel_6, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_set_verbosity, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h11111; - reg [31 : 0] v__h11381; - reg [31 : 0] v__h11105; - reg [31 : 0] v__h11375; - // synopsys translate_on - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = mem0_controller$to_raw_mem_request_get ; - assign RDY_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign CAN_FIRE_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign CAN_FIRE_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // actionvalue method get_to_console_get - assign get_to_console_get = uart0$get_to_console_get ; - assign RDY_get_to_console_get = uart0$RDY_get_to_console_get ; - assign CAN_FIRE_get_to_console_get = uart0$RDY_get_to_console_get ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = uart0$RDY_put_from_console_put ; - assign CAN_FIRE_put_from_console_put = uart0$RDY_put_from_console_put ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method status - assign status = mem0_controller$status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule boot_rom - mkBoot_ROM boot_rom(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(boot_rom$set_addr_map_addr_base), - .set_addr_map_addr_lim(boot_rom$set_addr_map_addr_lim), - .slave_araddr(boot_rom$slave_araddr), - .slave_arburst(boot_rom$slave_arburst), - .slave_arcache(boot_rom$slave_arcache), - .slave_arid(boot_rom$slave_arid), - .slave_arlen(boot_rom$slave_arlen), - .slave_arlock(boot_rom$slave_arlock), - .slave_arprot(boot_rom$slave_arprot), - .slave_arqos(boot_rom$slave_arqos), - .slave_arregion(boot_rom$slave_arregion), - .slave_arsize(boot_rom$slave_arsize), - .slave_arvalid(boot_rom$slave_arvalid), - .slave_awaddr(boot_rom$slave_awaddr), - .slave_awburst(boot_rom$slave_awburst), - .slave_awcache(boot_rom$slave_awcache), - .slave_awid(boot_rom$slave_awid), - .slave_awlen(boot_rom$slave_awlen), - .slave_awlock(boot_rom$slave_awlock), - .slave_awprot(boot_rom$slave_awprot), - .slave_awqos(boot_rom$slave_awqos), - .slave_awregion(boot_rom$slave_awregion), - .slave_awsize(boot_rom$slave_awsize), - .slave_awvalid(boot_rom$slave_awvalid), - .slave_bready(boot_rom$slave_bready), - .slave_rready(boot_rom$slave_rready), - .slave_wdata(boot_rom$slave_wdata), - .slave_wlast(boot_rom$slave_wlast), - .slave_wstrb(boot_rom$slave_wstrb), - .slave_wvalid(boot_rom$slave_wvalid), - .EN_set_addr_map(boot_rom$EN_set_addr_map), - .RDY_set_addr_map(), - .slave_awready(boot_rom$slave_awready), - .slave_wready(boot_rom$slave_wready), - .slave_bvalid(boot_rom$slave_bvalid), - .slave_bid(boot_rom$slave_bid), - .slave_bresp(boot_rom$slave_bresp), - .slave_arready(boot_rom$slave_arready), - .slave_rvalid(boot_rom$slave_rvalid), - .slave_rid(boot_rom$slave_rid), - .slave_rdata(boot_rom$slave_rdata), - .slave_rresp(boot_rom$slave_rresp), - .slave_rlast(boot_rom$slave_rlast)); - - // submodule boot_rom_axi4_deburster - mkAXI4_Deburster_A boot_rom_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(boot_rom_axi4_deburster$from_master_araddr), - .from_master_arburst(boot_rom_axi4_deburster$from_master_arburst), - .from_master_arcache(boot_rom_axi4_deburster$from_master_arcache), - .from_master_arid(boot_rom_axi4_deburster$from_master_arid), - .from_master_arlen(boot_rom_axi4_deburster$from_master_arlen), - .from_master_arlock(boot_rom_axi4_deburster$from_master_arlock), - .from_master_arprot(boot_rom_axi4_deburster$from_master_arprot), - .from_master_arqos(boot_rom_axi4_deburster$from_master_arqos), - .from_master_arregion(boot_rom_axi4_deburster$from_master_arregion), - .from_master_arsize(boot_rom_axi4_deburster$from_master_arsize), - .from_master_arvalid(boot_rom_axi4_deburster$from_master_arvalid), - .from_master_awaddr(boot_rom_axi4_deburster$from_master_awaddr), - .from_master_awburst(boot_rom_axi4_deburster$from_master_awburst), - .from_master_awcache(boot_rom_axi4_deburster$from_master_awcache), - .from_master_awid(boot_rom_axi4_deburster$from_master_awid), - .from_master_awlen(boot_rom_axi4_deburster$from_master_awlen), - .from_master_awlock(boot_rom_axi4_deburster$from_master_awlock), - .from_master_awprot(boot_rom_axi4_deburster$from_master_awprot), - .from_master_awqos(boot_rom_axi4_deburster$from_master_awqos), - .from_master_awregion(boot_rom_axi4_deburster$from_master_awregion), - .from_master_awsize(boot_rom_axi4_deburster$from_master_awsize), - .from_master_awvalid(boot_rom_axi4_deburster$from_master_awvalid), - .from_master_bready(boot_rom_axi4_deburster$from_master_bready), - .from_master_rready(boot_rom_axi4_deburster$from_master_rready), - .from_master_wdata(boot_rom_axi4_deburster$from_master_wdata), - .from_master_wlast(boot_rom_axi4_deburster$from_master_wlast), - .from_master_wstrb(boot_rom_axi4_deburster$from_master_wstrb), - .from_master_wvalid(boot_rom_axi4_deburster$from_master_wvalid), - .to_slave_arready(boot_rom_axi4_deburster$to_slave_arready), - .to_slave_awready(boot_rom_axi4_deburster$to_slave_awready), - .to_slave_bid(boot_rom_axi4_deburster$to_slave_bid), - .to_slave_bresp(boot_rom_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(boot_rom_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(boot_rom_axi4_deburster$to_slave_rdata), - .to_slave_rid(boot_rom_axi4_deburster$to_slave_rid), - .to_slave_rlast(boot_rom_axi4_deburster$to_slave_rlast), - .to_slave_rresp(boot_rom_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(boot_rom_axi4_deburster$to_slave_rvalid), - .to_slave_wready(boot_rom_axi4_deburster$to_slave_wready), - .EN_reset(boot_rom_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(boot_rom_axi4_deburster$from_master_awready), - .from_master_wready(boot_rom_axi4_deburster$from_master_wready), - .from_master_bvalid(boot_rom_axi4_deburster$from_master_bvalid), - .from_master_bid(boot_rom_axi4_deburster$from_master_bid), - .from_master_bresp(boot_rom_axi4_deburster$from_master_bresp), - .from_master_arready(boot_rom_axi4_deburster$from_master_arready), - .from_master_rvalid(boot_rom_axi4_deburster$from_master_rvalid), - .from_master_rid(boot_rom_axi4_deburster$from_master_rid), - .from_master_rdata(boot_rom_axi4_deburster$from_master_rdata), - .from_master_rresp(boot_rom_axi4_deburster$from_master_rresp), - .from_master_rlast(boot_rom_axi4_deburster$from_master_rlast), - .to_slave_awvalid(boot_rom_axi4_deburster$to_slave_awvalid), - .to_slave_awid(boot_rom_axi4_deburster$to_slave_awid), - .to_slave_awaddr(boot_rom_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(boot_rom_axi4_deburster$to_slave_awlen), - .to_slave_awsize(boot_rom_axi4_deburster$to_slave_awsize), - .to_slave_awburst(boot_rom_axi4_deburster$to_slave_awburst), - .to_slave_awlock(boot_rom_axi4_deburster$to_slave_awlock), - .to_slave_awcache(boot_rom_axi4_deburster$to_slave_awcache), - .to_slave_awprot(boot_rom_axi4_deburster$to_slave_awprot), - .to_slave_awqos(boot_rom_axi4_deburster$to_slave_awqos), - .to_slave_awregion(boot_rom_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(boot_rom_axi4_deburster$to_slave_wvalid), - .to_slave_wdata(boot_rom_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(boot_rom_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(boot_rom_axi4_deburster$to_slave_wlast), - .to_slave_bready(boot_rom_axi4_deburster$to_slave_bready), - .to_slave_arvalid(boot_rom_axi4_deburster$to_slave_arvalid), - .to_slave_arid(boot_rom_axi4_deburster$to_slave_arid), - .to_slave_araddr(boot_rom_axi4_deburster$to_slave_araddr), - .to_slave_arlen(boot_rom_axi4_deburster$to_slave_arlen), - .to_slave_arsize(boot_rom_axi4_deburster$to_slave_arsize), - .to_slave_arburst(boot_rom_axi4_deburster$to_slave_arburst), - .to_slave_arlock(boot_rom_axi4_deburster$to_slave_arlock), - .to_slave_arcache(boot_rom_axi4_deburster$to_slave_arcache), - .to_slave_arprot(boot_rom_axi4_deburster$to_slave_arprot), - .to_slave_arqos(boot_rom_axi4_deburster$to_slave_arqos), - .to_slave_arregion(boot_rom_axi4_deburster$to_slave_arregion), - .to_slave_rready(boot_rom_axi4_deburster$to_slave_rready)); - - // submodule core - mkCore core(.CLK(CLK), - .RST_N(RST_N), - .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_12_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_13_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_14_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_15_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_1_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_2_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_3_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_4_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_5_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_6_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_7_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_8_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_9_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear), - .cpu_dmem_master_arready(core$cpu_dmem_master_arready), - .cpu_dmem_master_awready(core$cpu_dmem_master_awready), - .cpu_dmem_master_bid(core$cpu_dmem_master_bid), - .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), - .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata), - .cpu_dmem_master_rid(core$cpu_dmem_master_rid), - .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast), - .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), - .cpu_dmem_master_wready(core$cpu_dmem_master_wready), - .cpu_imem_master_arready(core$cpu_imem_master_arready), - .cpu_imem_master_awready(core$cpu_imem_master_awready), - .cpu_imem_master_bid(core$cpu_imem_master_bid), - .cpu_imem_master_bresp(core$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), - .cpu_imem_master_rdata(core$cpu_imem_master_rdata), - .cpu_imem_master_rid(core$cpu_imem_master_rid), - .cpu_imem_master_rlast(core$cpu_imem_master_rlast), - .cpu_imem_master_rresp(core$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), - .cpu_imem_master_wready(core$cpu_imem_master_wready), - .cpu_reset_server_request_put(core$cpu_reset_server_request_put), - .nmi_req_set_not_clear(core$nmi_req_set_not_clear), - .set_verbosity_logdelay(core$set_verbosity_logdelay), - .set_verbosity_verbosity(core$set_verbosity_verbosity), - .EN_set_verbosity(core$EN_set_verbosity), - .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get), - .RDY_set_verbosity(), - .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put), - .cpu_reset_server_response_get(), - .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), - .cpu_imem_master_awid(core$cpu_imem_master_awid), - .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr), - .cpu_imem_master_awlen(core$cpu_imem_master_awlen), - .cpu_imem_master_awsize(core$cpu_imem_master_awsize), - .cpu_imem_master_awburst(core$cpu_imem_master_awburst), - .cpu_imem_master_awlock(core$cpu_imem_master_awlock), - .cpu_imem_master_awcache(core$cpu_imem_master_awcache), - .cpu_imem_master_awprot(core$cpu_imem_master_awprot), - .cpu_imem_master_awqos(core$cpu_imem_master_awqos), - .cpu_imem_master_awregion(core$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), - .cpu_imem_master_wdata(core$cpu_imem_master_wdata), - .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb), - .cpu_imem_master_wlast(core$cpu_imem_master_wlast), - .cpu_imem_master_bready(core$cpu_imem_master_bready), - .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), - .cpu_imem_master_arid(core$cpu_imem_master_arid), - .cpu_imem_master_araddr(core$cpu_imem_master_araddr), - .cpu_imem_master_arlen(core$cpu_imem_master_arlen), - .cpu_imem_master_arsize(core$cpu_imem_master_arsize), - .cpu_imem_master_arburst(core$cpu_imem_master_arburst), - .cpu_imem_master_arlock(core$cpu_imem_master_arlock), - .cpu_imem_master_arcache(core$cpu_imem_master_arcache), - .cpu_imem_master_arprot(core$cpu_imem_master_arprot), - .cpu_imem_master_arqos(core$cpu_imem_master_arqos), - .cpu_imem_master_arregion(core$cpu_imem_master_arregion), - .cpu_imem_master_rready(core$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), - .cpu_dmem_master_awid(core$cpu_dmem_master_awid), - .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr), - .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen), - .cpu_dmem_master_awsize(core$cpu_dmem_master_awsize), - .cpu_dmem_master_awburst(core$cpu_dmem_master_awburst), - .cpu_dmem_master_awlock(core$cpu_dmem_master_awlock), - .cpu_dmem_master_awcache(core$cpu_dmem_master_awcache), - .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot), - .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos), - .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), - .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata), - .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb), - .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast), - .cpu_dmem_master_bready(core$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), - .cpu_dmem_master_arid(core$cpu_dmem_master_arid), - .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr), - .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen), - .cpu_dmem_master_arsize(core$cpu_dmem_master_arsize), - .cpu_dmem_master_arburst(core$cpu_dmem_master_arburst), - .cpu_dmem_master_arlock(core$cpu_dmem_master_arlock), - .cpu_dmem_master_arcache(core$cpu_dmem_master_arcache), - .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot), - .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos), - .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion), - .cpu_dmem_master_rready(core$cpu_dmem_master_rready)); - - // submodule fabric - mkFabric_AXI4 fabric(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric$v_from_masters_0_wdata), - .v_from_masters_0_wlast(fabric$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric$v_from_masters_1_wdata), - .v_from_masters_1_wlast(fabric$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric$v_to_slaves_2_wready), - .EN_reset(fabric$EN_reset), - .EN_set_verbosity(fabric$EN_set_verbosity), - .RDY_reset(fabric$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric$v_to_slaves_0_wvalid), - .v_to_slaves_0_wdata(fabric$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric$v_to_slaves_1_wvalid), - .v_to_slaves_1_wdata(fabric$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric$v_to_slaves_2_wvalid), - .v_to_slaves_2_wdata(fabric$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric$v_to_slaves_2_rready)); - - // submodule mem0_controller - mkMem_Controller mem0_controller(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(mem0_controller$set_addr_map_addr_base), - .set_addr_map_addr_lim(mem0_controller$set_addr_map_addr_lim), - .set_watch_tohost_tohost_addr(mem0_controller$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(mem0_controller$set_watch_tohost_watch_tohost), - .slave_araddr(mem0_controller$slave_araddr), - .slave_arburst(mem0_controller$slave_arburst), - .slave_arcache(mem0_controller$slave_arcache), - .slave_arid(mem0_controller$slave_arid), - .slave_arlen(mem0_controller$slave_arlen), - .slave_arlock(mem0_controller$slave_arlock), - .slave_arprot(mem0_controller$slave_arprot), - .slave_arqos(mem0_controller$slave_arqos), - .slave_arregion(mem0_controller$slave_arregion), - .slave_arsize(mem0_controller$slave_arsize), - .slave_arvalid(mem0_controller$slave_arvalid), - .slave_awaddr(mem0_controller$slave_awaddr), - .slave_awburst(mem0_controller$slave_awburst), - .slave_awcache(mem0_controller$slave_awcache), - .slave_awid(mem0_controller$slave_awid), - .slave_awlen(mem0_controller$slave_awlen), - .slave_awlock(mem0_controller$slave_awlock), - .slave_awprot(mem0_controller$slave_awprot), - .slave_awqos(mem0_controller$slave_awqos), - .slave_awregion(mem0_controller$slave_awregion), - .slave_awsize(mem0_controller$slave_awsize), - .slave_awvalid(mem0_controller$slave_awvalid), - .slave_bready(mem0_controller$slave_bready), - .slave_rready(mem0_controller$slave_rready), - .slave_wdata(mem0_controller$slave_wdata), - .slave_wlast(mem0_controller$slave_wlast), - .slave_wstrb(mem0_controller$slave_wstrb), - .slave_wvalid(mem0_controller$slave_wvalid), - .to_raw_mem_response_put(mem0_controller$to_raw_mem_response_put), - .EN_server_reset_request_put(mem0_controller$EN_server_reset_request_put), - .EN_server_reset_response_get(mem0_controller$EN_server_reset_response_get), - .EN_set_addr_map(mem0_controller$EN_set_addr_map), - .EN_to_raw_mem_request_get(mem0_controller$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(mem0_controller$EN_to_raw_mem_response_put), - .EN_set_watch_tohost(mem0_controller$EN_set_watch_tohost), - .RDY_server_reset_request_put(mem0_controller$RDY_server_reset_request_put), - .RDY_server_reset_response_get(mem0_controller$RDY_server_reset_response_get), - .RDY_set_addr_map(mem0_controller$RDY_set_addr_map), - .slave_awready(mem0_controller$slave_awready), - .slave_wready(mem0_controller$slave_wready), - .slave_bvalid(mem0_controller$slave_bvalid), - .slave_bid(mem0_controller$slave_bid), - .slave_bresp(mem0_controller$slave_bresp), - .slave_arready(mem0_controller$slave_arready), - .slave_rvalid(mem0_controller$slave_rvalid), - .slave_rid(mem0_controller$slave_rid), - .slave_rdata(mem0_controller$slave_rdata), - .slave_rresp(mem0_controller$slave_rresp), - .slave_rlast(mem0_controller$slave_rlast), - .to_raw_mem_request_get(mem0_controller$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(mem0_controller$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(mem0_controller$RDY_to_raw_mem_response_put), - .status(mem0_controller$status), - .RDY_set_watch_tohost()); - - // submodule mem0_controller_axi4_deburster - mkAXI4_Deburster_A mem0_controller_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(mem0_controller_axi4_deburster$from_master_araddr), - .from_master_arburst(mem0_controller_axi4_deburster$from_master_arburst), - .from_master_arcache(mem0_controller_axi4_deburster$from_master_arcache), - .from_master_arid(mem0_controller_axi4_deburster$from_master_arid), - .from_master_arlen(mem0_controller_axi4_deburster$from_master_arlen), - .from_master_arlock(mem0_controller_axi4_deburster$from_master_arlock), - .from_master_arprot(mem0_controller_axi4_deburster$from_master_arprot), - .from_master_arqos(mem0_controller_axi4_deburster$from_master_arqos), - .from_master_arregion(mem0_controller_axi4_deburster$from_master_arregion), - .from_master_arsize(mem0_controller_axi4_deburster$from_master_arsize), - .from_master_arvalid(mem0_controller_axi4_deburster$from_master_arvalid), - .from_master_awaddr(mem0_controller_axi4_deburster$from_master_awaddr), - .from_master_awburst(mem0_controller_axi4_deburster$from_master_awburst), - .from_master_awcache(mem0_controller_axi4_deburster$from_master_awcache), - .from_master_awid(mem0_controller_axi4_deburster$from_master_awid), - .from_master_awlen(mem0_controller_axi4_deburster$from_master_awlen), - .from_master_awlock(mem0_controller_axi4_deburster$from_master_awlock), - .from_master_awprot(mem0_controller_axi4_deburster$from_master_awprot), - .from_master_awqos(mem0_controller_axi4_deburster$from_master_awqos), - .from_master_awregion(mem0_controller_axi4_deburster$from_master_awregion), - .from_master_awsize(mem0_controller_axi4_deburster$from_master_awsize), - .from_master_awvalid(mem0_controller_axi4_deburster$from_master_awvalid), - .from_master_bready(mem0_controller_axi4_deburster$from_master_bready), - .from_master_rready(mem0_controller_axi4_deburster$from_master_rready), - .from_master_wdata(mem0_controller_axi4_deburster$from_master_wdata), - .from_master_wlast(mem0_controller_axi4_deburster$from_master_wlast), - .from_master_wstrb(mem0_controller_axi4_deburster$from_master_wstrb), - .from_master_wvalid(mem0_controller_axi4_deburster$from_master_wvalid), - .to_slave_arready(mem0_controller_axi4_deburster$to_slave_arready), - .to_slave_awready(mem0_controller_axi4_deburster$to_slave_awready), - .to_slave_bid(mem0_controller_axi4_deburster$to_slave_bid), - .to_slave_bresp(mem0_controller_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(mem0_controller_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(mem0_controller_axi4_deburster$to_slave_rdata), - .to_slave_rid(mem0_controller_axi4_deburster$to_slave_rid), - .to_slave_rlast(mem0_controller_axi4_deburster$to_slave_rlast), - .to_slave_rresp(mem0_controller_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(mem0_controller_axi4_deburster$to_slave_rvalid), - .to_slave_wready(mem0_controller_axi4_deburster$to_slave_wready), - .EN_reset(mem0_controller_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(mem0_controller_axi4_deburster$from_master_awready), - .from_master_wready(mem0_controller_axi4_deburster$from_master_wready), - .from_master_bvalid(mem0_controller_axi4_deburster$from_master_bvalid), - .from_master_bid(mem0_controller_axi4_deburster$from_master_bid), - .from_master_bresp(mem0_controller_axi4_deburster$from_master_bresp), - .from_master_arready(mem0_controller_axi4_deburster$from_master_arready), - .from_master_rvalid(mem0_controller_axi4_deburster$from_master_rvalid), - .from_master_rid(mem0_controller_axi4_deburster$from_master_rid), - .from_master_rdata(mem0_controller_axi4_deburster$from_master_rdata), - .from_master_rresp(mem0_controller_axi4_deburster$from_master_rresp), - .from_master_rlast(mem0_controller_axi4_deburster$from_master_rlast), - .to_slave_awvalid(mem0_controller_axi4_deburster$to_slave_awvalid), - .to_slave_awid(mem0_controller_axi4_deburster$to_slave_awid), - .to_slave_awaddr(mem0_controller_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(mem0_controller_axi4_deburster$to_slave_awlen), - .to_slave_awsize(mem0_controller_axi4_deburster$to_slave_awsize), - .to_slave_awburst(mem0_controller_axi4_deburster$to_slave_awburst), - .to_slave_awlock(mem0_controller_axi4_deburster$to_slave_awlock), - .to_slave_awcache(mem0_controller_axi4_deburster$to_slave_awcache), - .to_slave_awprot(mem0_controller_axi4_deburster$to_slave_awprot), - .to_slave_awqos(mem0_controller_axi4_deburster$to_slave_awqos), - .to_slave_awregion(mem0_controller_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(mem0_controller_axi4_deburster$to_slave_wvalid), - .to_slave_wdata(mem0_controller_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(mem0_controller_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(mem0_controller_axi4_deburster$to_slave_wlast), - .to_slave_bready(mem0_controller_axi4_deburster$to_slave_bready), - .to_slave_arvalid(mem0_controller_axi4_deburster$to_slave_arvalid), - .to_slave_arid(mem0_controller_axi4_deburster$to_slave_arid), - .to_slave_araddr(mem0_controller_axi4_deburster$to_slave_araddr), - .to_slave_arlen(mem0_controller_axi4_deburster$to_slave_arlen), - .to_slave_arsize(mem0_controller_axi4_deburster$to_slave_arsize), - .to_slave_arburst(mem0_controller_axi4_deburster$to_slave_arburst), - .to_slave_arlock(mem0_controller_axi4_deburster$to_slave_arlock), - .to_slave_arcache(mem0_controller_axi4_deburster$to_slave_arcache), - .to_slave_arprot(mem0_controller_axi4_deburster$to_slave_arprot), - .to_slave_arqos(mem0_controller_axi4_deburster$to_slave_arqos), - .to_slave_arregion(mem0_controller_axi4_deburster$to_slave_arregion), - .to_slave_rready(mem0_controller_axi4_deburster$to_slave_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule uart0 - mkUART uart0(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(uart0$put_from_console_put), - .set_addr_map_addr_base(uart0$set_addr_map_addr_base), - .set_addr_map_addr_lim(uart0$set_addr_map_addr_lim), - .slave_araddr(uart0$slave_araddr), - .slave_arburst(uart0$slave_arburst), - .slave_arcache(uart0$slave_arcache), - .slave_arid(uart0$slave_arid), - .slave_arlen(uart0$slave_arlen), - .slave_arlock(uart0$slave_arlock), - .slave_arprot(uart0$slave_arprot), - .slave_arqos(uart0$slave_arqos), - .slave_arregion(uart0$slave_arregion), - .slave_arsize(uart0$slave_arsize), - .slave_arvalid(uart0$slave_arvalid), - .slave_awaddr(uart0$slave_awaddr), - .slave_awburst(uart0$slave_awburst), - .slave_awcache(uart0$slave_awcache), - .slave_awid(uart0$slave_awid), - .slave_awlen(uart0$slave_awlen), - .slave_awlock(uart0$slave_awlock), - .slave_awprot(uart0$slave_awprot), - .slave_awqos(uart0$slave_awqos), - .slave_awregion(uart0$slave_awregion), - .slave_awsize(uart0$slave_awsize), - .slave_awvalid(uart0$slave_awvalid), - .slave_bready(uart0$slave_bready), - .slave_rready(uart0$slave_rready), - .slave_wdata(uart0$slave_wdata), - .slave_wlast(uart0$slave_wlast), - .slave_wstrb(uart0$slave_wstrb), - .slave_wvalid(uart0$slave_wvalid), - .EN_server_reset_request_put(uart0$EN_server_reset_request_put), - .EN_server_reset_response_get(uart0$EN_server_reset_response_get), - .EN_set_addr_map(uart0$EN_set_addr_map), - .EN_get_to_console_get(uart0$EN_get_to_console_get), - .EN_put_from_console_put(uart0$EN_put_from_console_put), - .RDY_server_reset_request_put(uart0$RDY_server_reset_request_put), - .RDY_server_reset_response_get(uart0$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .slave_awready(uart0$slave_awready), - .slave_wready(uart0$slave_wready), - .slave_bvalid(uart0$slave_bvalid), - .slave_bid(uart0$slave_bid), - .slave_bresp(uart0$slave_bresp), - .slave_arready(uart0$slave_arready), - .slave_rvalid(uart0$slave_rvalid), - .slave_rid(uart0$slave_rid), - .slave_rdata(uart0$slave_rdata), - .slave_rresp(uart0$slave_rresp), - .slave_rlast(uart0$slave_rlast), - .get_to_console_get(uart0$get_to_console_get), - .RDY_get_to_console_get(uart0$RDY_get_to_console_get), - .RDY_put_from_console_put(uart0$RDY_put_from_console_put), - .intr(uart0$intr)); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_5 - assign CAN_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - - // rule RL_rl_wr_data_channel_5 - assign CAN_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_response_channel_5 - assign CAN_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_5 - assign CAN_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - - // rule RL_rl_rd_data_channel_5 - assign CAN_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_6 - assign CAN_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - - // rule RL_rl_wr_data_channel_6 - assign CAN_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - - // rule RL_rl_wr_response_channel_6 - assign CAN_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_6 - assign CAN_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - - // rule RL_rl_rd_data_channel_6 - assign CAN_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - - // rule RL_rl_connect_external_interrupt_requests - assign CAN_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - - // rule RL_rl_reset_start_initial - assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete_initial - assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete_initial = - MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = - mem0_controller$RDY_server_reset_request_put && - uart0$RDY_server_reset_request_put && - fabric$RDY_reset && - core$RDY_cpu_reset_server_request_put && - rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && - mem0_controller$RDY_server_reset_response_get && - uart0$RDY_server_reset_response_get && - core$RDY_cpu_reset_server_response_get && - rg_state == 2'd1 ; - - // register rg_state - assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_start_initial || - WILL_FIRE_RL_rl_reset_complete_initial ; - - // submodule boot_rom - assign boot_rom$set_addr_map_addr_base = soc_map$m_boot_rom_addr_base ; - assign boot_rom$set_addr_map_addr_lim = soc_map$m_boot_rom_addr_lim ; - assign boot_rom$slave_araddr = boot_rom_axi4_deburster$to_slave_araddr ; - assign boot_rom$slave_arburst = boot_rom_axi4_deburster$to_slave_arburst ; - assign boot_rom$slave_arcache = boot_rom_axi4_deburster$to_slave_arcache ; - assign boot_rom$slave_arid = boot_rom_axi4_deburster$to_slave_arid ; - assign boot_rom$slave_arlen = boot_rom_axi4_deburster$to_slave_arlen ; - assign boot_rom$slave_arlock = boot_rom_axi4_deburster$to_slave_arlock ; - assign boot_rom$slave_arprot = boot_rom_axi4_deburster$to_slave_arprot ; - assign boot_rom$slave_arqos = boot_rom_axi4_deburster$to_slave_arqos ; - assign boot_rom$slave_arregion = boot_rom_axi4_deburster$to_slave_arregion ; - assign boot_rom$slave_arsize = boot_rom_axi4_deburster$to_slave_arsize ; - assign boot_rom$slave_arvalid = boot_rom_axi4_deburster$to_slave_arvalid ; - assign boot_rom$slave_awaddr = boot_rom_axi4_deburster$to_slave_awaddr ; - assign boot_rom$slave_awburst = boot_rom_axi4_deburster$to_slave_awburst ; - assign boot_rom$slave_awcache = boot_rom_axi4_deburster$to_slave_awcache ; - assign boot_rom$slave_awid = boot_rom_axi4_deburster$to_slave_awid ; - assign boot_rom$slave_awlen = boot_rom_axi4_deburster$to_slave_awlen ; - assign boot_rom$slave_awlock = boot_rom_axi4_deburster$to_slave_awlock ; - assign boot_rom$slave_awprot = boot_rom_axi4_deburster$to_slave_awprot ; - assign boot_rom$slave_awqos = boot_rom_axi4_deburster$to_slave_awqos ; - assign boot_rom$slave_awregion = boot_rom_axi4_deburster$to_slave_awregion ; - assign boot_rom$slave_awsize = boot_rom_axi4_deburster$to_slave_awsize ; - assign boot_rom$slave_awvalid = boot_rom_axi4_deburster$to_slave_awvalid ; - assign boot_rom$slave_bready = boot_rom_axi4_deburster$to_slave_bready ; - assign boot_rom$slave_rready = boot_rom_axi4_deburster$to_slave_rready ; - assign boot_rom$slave_wdata = boot_rom_axi4_deburster$to_slave_wdata ; - assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; - assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; - assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - - // submodule boot_rom_axi4_deburster - assign boot_rom_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_0_araddr ; - assign boot_rom_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_0_arburst ; - assign boot_rom_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_0_arcache ; - assign boot_rom_axi4_deburster$from_master_arid = - fabric$v_to_slaves_0_arid ; - assign boot_rom_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_0_arlen ; - assign boot_rom_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_0_arlock ; - assign boot_rom_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_0_arprot ; - assign boot_rom_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_0_arqos ; - assign boot_rom_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_0_arregion ; - assign boot_rom_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_0_arsize ; - assign boot_rom_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_0_arvalid ; - assign boot_rom_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_0_awaddr ; - assign boot_rom_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_0_awburst ; - assign boot_rom_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_0_awcache ; - assign boot_rom_axi4_deburster$from_master_awid = - fabric$v_to_slaves_0_awid ; - assign boot_rom_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_0_awlen ; - assign boot_rom_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_0_awlock ; - assign boot_rom_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_0_awprot ; - assign boot_rom_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_0_awqos ; - assign boot_rom_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_0_awregion ; - assign boot_rom_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_0_awsize ; - assign boot_rom_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_0_awvalid ; - assign boot_rom_axi4_deburster$from_master_bready = - fabric$v_to_slaves_0_bready ; - assign boot_rom_axi4_deburster$from_master_rready = - fabric$v_to_slaves_0_rready ; - assign boot_rom_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_0_wdata ; - assign boot_rom_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_0_wlast ; - assign boot_rom_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_0_wstrb ; - assign boot_rom_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_0_wvalid ; - assign boot_rom_axi4_deburster$to_slave_arready = boot_rom$slave_arready ; - assign boot_rom_axi4_deburster$to_slave_awready = boot_rom$slave_awready ; - assign boot_rom_axi4_deburster$to_slave_bid = boot_rom$slave_bid ; - assign boot_rom_axi4_deburster$to_slave_bresp = boot_rom$slave_bresp ; - assign boot_rom_axi4_deburster$to_slave_bvalid = boot_rom$slave_bvalid ; - assign boot_rom_axi4_deburster$to_slave_rdata = boot_rom$slave_rdata ; - assign boot_rom_axi4_deburster$to_slave_rid = boot_rom$slave_rid ; - assign boot_rom_axi4_deburster$to_slave_rlast = boot_rom$slave_rlast ; - assign boot_rom_axi4_deburster$to_slave_rresp = boot_rom$slave_rresp ; - assign boot_rom_axi4_deburster$to_slave_rvalid = boot_rom$slave_rvalid ; - assign boot_rom_axi4_deburster$to_slave_wready = boot_rom$slave_wready ; - assign boot_rom_axi4_deburster$EN_reset = 1'b0 ; - - // submodule core - assign core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = - uart0$intr ; - assign core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$cpu_dmem_master_arready = fabric$v_from_masters_1_arready ; - assign core$cpu_dmem_master_awready = fabric$v_from_masters_1_awready ; - assign core$cpu_dmem_master_bid = fabric$v_from_masters_1_bid ; - assign core$cpu_dmem_master_bresp = fabric$v_from_masters_1_bresp ; - assign core$cpu_dmem_master_bvalid = fabric$v_from_masters_1_bvalid ; - assign core$cpu_dmem_master_rdata = fabric$v_from_masters_1_rdata ; - assign core$cpu_dmem_master_rid = fabric$v_from_masters_1_rid ; - assign core$cpu_dmem_master_rlast = fabric$v_from_masters_1_rlast ; - assign core$cpu_dmem_master_rresp = fabric$v_from_masters_1_rresp ; - assign core$cpu_dmem_master_rvalid = fabric$v_from_masters_1_rvalid ; - assign core$cpu_dmem_master_wready = fabric$v_from_masters_1_wready ; - assign core$cpu_imem_master_arready = fabric$v_from_masters_0_arready ; - assign core$cpu_imem_master_awready = fabric$v_from_masters_0_awready ; - assign core$cpu_imem_master_bid = fabric$v_from_masters_0_bid ; - assign core$cpu_imem_master_bresp = fabric$v_from_masters_0_bresp ; - assign core$cpu_imem_master_bvalid = fabric$v_from_masters_0_bvalid ; - assign core$cpu_imem_master_rdata = fabric$v_from_masters_0_rdata ; - assign core$cpu_imem_master_rid = fabric$v_from_masters_0_rid ; - assign core$cpu_imem_master_rlast = fabric$v_from_masters_0_rlast ; - assign core$cpu_imem_master_rresp = fabric$v_from_masters_0_rresp ; - assign core$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ; - assign core$cpu_imem_master_wready = fabric$v_from_masters_0_wready ; - assign core$cpu_reset_server_request_put = 1'd1 ; - assign core$nmi_req_set_not_clear = 1'd0 ; - assign core$set_verbosity_logdelay = set_verbosity_logdelay ; - assign core$set_verbosity_verbosity = set_verbosity_verbosity ; - assign core$EN_set_verbosity = EN_set_verbosity ; - assign core$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; - assign core$EN_cpu_reset_server_response_get = MUX_rg_state$write_1__SEL_2 ; - - // submodule fabric - assign fabric$set_verbosity_verbosity = 4'h0 ; - assign fabric$v_from_masters_0_araddr = core$cpu_imem_master_araddr ; - assign fabric$v_from_masters_0_arburst = core$cpu_imem_master_arburst ; - assign fabric$v_from_masters_0_arcache = core$cpu_imem_master_arcache ; - assign fabric$v_from_masters_0_arid = core$cpu_imem_master_arid ; - assign fabric$v_from_masters_0_arlen = core$cpu_imem_master_arlen ; - assign fabric$v_from_masters_0_arlock = core$cpu_imem_master_arlock ; - assign fabric$v_from_masters_0_arprot = core$cpu_imem_master_arprot ; - assign fabric$v_from_masters_0_arqos = core$cpu_imem_master_arqos ; - assign fabric$v_from_masters_0_arregion = core$cpu_imem_master_arregion ; - assign fabric$v_from_masters_0_arsize = core$cpu_imem_master_arsize ; - assign fabric$v_from_masters_0_arvalid = core$cpu_imem_master_arvalid ; - assign fabric$v_from_masters_0_awaddr = core$cpu_imem_master_awaddr ; - assign fabric$v_from_masters_0_awburst = core$cpu_imem_master_awburst ; - assign fabric$v_from_masters_0_awcache = core$cpu_imem_master_awcache ; - assign fabric$v_from_masters_0_awid = core$cpu_imem_master_awid ; - assign fabric$v_from_masters_0_awlen = core$cpu_imem_master_awlen ; - assign fabric$v_from_masters_0_awlock = core$cpu_imem_master_awlock ; - assign fabric$v_from_masters_0_awprot = core$cpu_imem_master_awprot ; - assign fabric$v_from_masters_0_awqos = core$cpu_imem_master_awqos ; - assign fabric$v_from_masters_0_awregion = core$cpu_imem_master_awregion ; - assign fabric$v_from_masters_0_awsize = core$cpu_imem_master_awsize ; - assign fabric$v_from_masters_0_awvalid = core$cpu_imem_master_awvalid ; - assign fabric$v_from_masters_0_bready = core$cpu_imem_master_bready ; - assign fabric$v_from_masters_0_rready = core$cpu_imem_master_rready ; - assign fabric$v_from_masters_0_wdata = core$cpu_imem_master_wdata ; - assign fabric$v_from_masters_0_wlast = core$cpu_imem_master_wlast ; - assign fabric$v_from_masters_0_wstrb = core$cpu_imem_master_wstrb ; - assign fabric$v_from_masters_0_wvalid = core$cpu_imem_master_wvalid ; - assign fabric$v_from_masters_1_araddr = core$cpu_dmem_master_araddr ; - assign fabric$v_from_masters_1_arburst = core$cpu_dmem_master_arburst ; - assign fabric$v_from_masters_1_arcache = core$cpu_dmem_master_arcache ; - assign fabric$v_from_masters_1_arid = core$cpu_dmem_master_arid ; - assign fabric$v_from_masters_1_arlen = core$cpu_dmem_master_arlen ; - assign fabric$v_from_masters_1_arlock = core$cpu_dmem_master_arlock ; - assign fabric$v_from_masters_1_arprot = core$cpu_dmem_master_arprot ; - assign fabric$v_from_masters_1_arqos = core$cpu_dmem_master_arqos ; - assign fabric$v_from_masters_1_arregion = core$cpu_dmem_master_arregion ; - assign fabric$v_from_masters_1_arsize = core$cpu_dmem_master_arsize ; - assign fabric$v_from_masters_1_arvalid = core$cpu_dmem_master_arvalid ; - assign fabric$v_from_masters_1_awaddr = core$cpu_dmem_master_awaddr ; - assign fabric$v_from_masters_1_awburst = core$cpu_dmem_master_awburst ; - assign fabric$v_from_masters_1_awcache = core$cpu_dmem_master_awcache ; - assign fabric$v_from_masters_1_awid = core$cpu_dmem_master_awid ; - assign fabric$v_from_masters_1_awlen = core$cpu_dmem_master_awlen ; - assign fabric$v_from_masters_1_awlock = core$cpu_dmem_master_awlock ; - assign fabric$v_from_masters_1_awprot = core$cpu_dmem_master_awprot ; - assign fabric$v_from_masters_1_awqos = core$cpu_dmem_master_awqos ; - assign fabric$v_from_masters_1_awregion = core$cpu_dmem_master_awregion ; - assign fabric$v_from_masters_1_awsize = core$cpu_dmem_master_awsize ; - assign fabric$v_from_masters_1_awvalid = core$cpu_dmem_master_awvalid ; - assign fabric$v_from_masters_1_bready = core$cpu_dmem_master_bready ; - assign fabric$v_from_masters_1_rready = core$cpu_dmem_master_rready ; - assign fabric$v_from_masters_1_wdata = core$cpu_dmem_master_wdata ; - assign fabric$v_from_masters_1_wlast = core$cpu_dmem_master_wlast ; - assign fabric$v_from_masters_1_wstrb = core$cpu_dmem_master_wstrb ; - assign fabric$v_from_masters_1_wvalid = core$cpu_dmem_master_wvalid ; - assign fabric$v_to_slaves_0_arready = - boot_rom_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_0_awready = - boot_rom_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_0_bid = boot_rom_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_0_bresp = - boot_rom_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_0_bvalid = - boot_rom_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_0_rdata = - boot_rom_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_0_rid = boot_rom_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_0_rlast = - boot_rom_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_0_rresp = - boot_rom_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_0_rvalid = - boot_rom_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_0_wready = - boot_rom_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_1_arready = - mem0_controller_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_1_awready = - mem0_controller_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_1_bid = - mem0_controller_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_1_bresp = - mem0_controller_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_1_bvalid = - mem0_controller_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_1_rdata = - mem0_controller_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_1_rid = - mem0_controller_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_1_rlast = - mem0_controller_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_1_rresp = - mem0_controller_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_1_rvalid = - mem0_controller_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_1_wready = - mem0_controller_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_2_arready = uart0$slave_arready ; - assign fabric$v_to_slaves_2_awready = uart0$slave_awready ; - assign fabric$v_to_slaves_2_bid = uart0$slave_bid ; - assign fabric$v_to_slaves_2_bresp = uart0$slave_bresp ; - assign fabric$v_to_slaves_2_bvalid = uart0$slave_bvalid ; - assign fabric$v_to_slaves_2_rdata = uart0$slave_rdata ; - assign fabric$v_to_slaves_2_rid = uart0$slave_rid ; - assign fabric$v_to_slaves_2_rlast = uart0$slave_rlast ; - assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; - assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; - assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; - assign fabric$EN_set_verbosity = 1'b0 ; - - // submodule mem0_controller - assign mem0_controller$set_addr_map_addr_base = - soc_map$m_mem0_controller_addr_base ; - assign mem0_controller$set_addr_map_addr_lim = - soc_map$m_mem0_controller_addr_lim ; - assign mem0_controller$set_watch_tohost_tohost_addr = - set_watch_tohost_tohost_addr ; - assign mem0_controller$set_watch_tohost_watch_tohost = - set_watch_tohost_watch_tohost ; - assign mem0_controller$slave_araddr = - mem0_controller_axi4_deburster$to_slave_araddr ; - assign mem0_controller$slave_arburst = - mem0_controller_axi4_deburster$to_slave_arburst ; - assign mem0_controller$slave_arcache = - mem0_controller_axi4_deburster$to_slave_arcache ; - assign mem0_controller$slave_arid = - mem0_controller_axi4_deburster$to_slave_arid ; - assign mem0_controller$slave_arlen = - mem0_controller_axi4_deburster$to_slave_arlen ; - assign mem0_controller$slave_arlock = - mem0_controller_axi4_deburster$to_slave_arlock ; - assign mem0_controller$slave_arprot = - mem0_controller_axi4_deburster$to_slave_arprot ; - assign mem0_controller$slave_arqos = - mem0_controller_axi4_deburster$to_slave_arqos ; - assign mem0_controller$slave_arregion = - mem0_controller_axi4_deburster$to_slave_arregion ; - assign mem0_controller$slave_arsize = - mem0_controller_axi4_deburster$to_slave_arsize ; - assign mem0_controller$slave_arvalid = - mem0_controller_axi4_deburster$to_slave_arvalid ; - assign mem0_controller$slave_awaddr = - mem0_controller_axi4_deburster$to_slave_awaddr ; - assign mem0_controller$slave_awburst = - mem0_controller_axi4_deburster$to_slave_awburst ; - assign mem0_controller$slave_awcache = - mem0_controller_axi4_deburster$to_slave_awcache ; - assign mem0_controller$slave_awid = - mem0_controller_axi4_deburster$to_slave_awid ; - assign mem0_controller$slave_awlen = - mem0_controller_axi4_deburster$to_slave_awlen ; - assign mem0_controller$slave_awlock = - mem0_controller_axi4_deburster$to_slave_awlock ; - assign mem0_controller$slave_awprot = - mem0_controller_axi4_deburster$to_slave_awprot ; - assign mem0_controller$slave_awqos = - mem0_controller_axi4_deburster$to_slave_awqos ; - assign mem0_controller$slave_awregion = - mem0_controller_axi4_deburster$to_slave_awregion ; - assign mem0_controller$slave_awsize = - mem0_controller_axi4_deburster$to_slave_awsize ; - assign mem0_controller$slave_awvalid = - mem0_controller_axi4_deburster$to_slave_awvalid ; - assign mem0_controller$slave_bready = - mem0_controller_axi4_deburster$to_slave_bready ; - assign mem0_controller$slave_rready = - mem0_controller_axi4_deburster$to_slave_rready ; - assign mem0_controller$slave_wdata = - mem0_controller_axi4_deburster$to_slave_wdata ; - assign mem0_controller$slave_wlast = - mem0_controller_axi4_deburster$to_slave_wlast ; - assign mem0_controller$slave_wstrb = - mem0_controller_axi4_deburster$to_slave_wstrb ; - assign mem0_controller$slave_wvalid = - mem0_controller_axi4_deburster$to_slave_wvalid ; - assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; - assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; - assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_to_raw_mem_request_get = - EN_to_raw_mem_request_get ; - assign mem0_controller$EN_to_raw_mem_response_put = - EN_to_raw_mem_response_put ; - assign mem0_controller$EN_set_watch_tohost = EN_set_watch_tohost ; - - // submodule mem0_controller_axi4_deburster - assign mem0_controller_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_1_araddr ; - assign mem0_controller_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_1_arburst ; - assign mem0_controller_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_1_arcache ; - assign mem0_controller_axi4_deburster$from_master_arid = - fabric$v_to_slaves_1_arid ; - assign mem0_controller_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_1_arlen ; - assign mem0_controller_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_1_arlock ; - assign mem0_controller_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_1_arprot ; - assign mem0_controller_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_1_arqos ; - assign mem0_controller_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_1_arregion ; - assign mem0_controller_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_1_arsize ; - assign mem0_controller_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_1_arvalid ; - assign mem0_controller_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_1_awaddr ; - assign mem0_controller_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_1_awburst ; - assign mem0_controller_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_1_awcache ; - assign mem0_controller_axi4_deburster$from_master_awid = - fabric$v_to_slaves_1_awid ; - assign mem0_controller_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_1_awlen ; - assign mem0_controller_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_1_awlock ; - assign mem0_controller_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_1_awprot ; - assign mem0_controller_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_1_awqos ; - assign mem0_controller_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_1_awregion ; - assign mem0_controller_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_1_awsize ; - assign mem0_controller_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_1_awvalid ; - assign mem0_controller_axi4_deburster$from_master_bready = - fabric$v_to_slaves_1_bready ; - assign mem0_controller_axi4_deburster$from_master_rready = - fabric$v_to_slaves_1_rready ; - assign mem0_controller_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_1_wdata ; - assign mem0_controller_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_1_wlast ; - assign mem0_controller_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_1_wstrb ; - assign mem0_controller_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_1_wvalid ; - assign mem0_controller_axi4_deburster$to_slave_arready = - mem0_controller$slave_arready ; - assign mem0_controller_axi4_deburster$to_slave_awready = - mem0_controller$slave_awready ; - assign mem0_controller_axi4_deburster$to_slave_bid = - mem0_controller$slave_bid ; - assign mem0_controller_axi4_deburster$to_slave_bresp = - mem0_controller$slave_bresp ; - assign mem0_controller_axi4_deburster$to_slave_bvalid = - mem0_controller$slave_bvalid ; - assign mem0_controller_axi4_deburster$to_slave_rdata = - mem0_controller$slave_rdata ; - assign mem0_controller_axi4_deburster$to_slave_rid = - mem0_controller$slave_rid ; - assign mem0_controller_axi4_deburster$to_slave_rlast = - mem0_controller$slave_rlast ; - assign mem0_controller_axi4_deburster$to_slave_rresp = - mem0_controller$slave_rresp ; - assign mem0_controller_axi4_deburster$to_slave_rvalid = - mem0_controller$slave_rvalid ; - assign mem0_controller_axi4_deburster$to_slave_wready = - mem0_controller$slave_wready ; - assign mem0_controller_axi4_deburster$EN_reset = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule uart0 - assign uart0$put_from_console_put = put_from_console_put ; - assign uart0$set_addr_map_addr_base = soc_map$m_uart0_addr_base ; - assign uart0$set_addr_map_addr_lim = soc_map$m_uart0_addr_lim ; - assign uart0$slave_araddr = fabric$v_to_slaves_2_araddr ; - assign uart0$slave_arburst = fabric$v_to_slaves_2_arburst ; - assign uart0$slave_arcache = fabric$v_to_slaves_2_arcache ; - assign uart0$slave_arid = fabric$v_to_slaves_2_arid ; - assign uart0$slave_arlen = fabric$v_to_slaves_2_arlen ; - assign uart0$slave_arlock = fabric$v_to_slaves_2_arlock ; - assign uart0$slave_arprot = fabric$v_to_slaves_2_arprot ; - assign uart0$slave_arqos = fabric$v_to_slaves_2_arqos ; - assign uart0$slave_arregion = fabric$v_to_slaves_2_arregion ; - assign uart0$slave_arsize = fabric$v_to_slaves_2_arsize ; - assign uart0$slave_arvalid = fabric$v_to_slaves_2_arvalid ; - assign uart0$slave_awaddr = fabric$v_to_slaves_2_awaddr ; - assign uart0$slave_awburst = fabric$v_to_slaves_2_awburst ; - assign uart0$slave_awcache = fabric$v_to_slaves_2_awcache ; - assign uart0$slave_awid = fabric$v_to_slaves_2_awid ; - assign uart0$slave_awlen = fabric$v_to_slaves_2_awlen ; - assign uart0$slave_awlock = fabric$v_to_slaves_2_awlock ; - assign uart0$slave_awprot = fabric$v_to_slaves_2_awprot ; - assign uart0$slave_awqos = fabric$v_to_slaves_2_awqos ; - assign uart0$slave_awregion = fabric$v_to_slaves_2_awregion ; - assign uart0$slave_awsize = fabric$v_to_slaves_2_awsize ; - assign uart0$slave_awvalid = fabric$v_to_slaves_2_awvalid ; - assign uart0$slave_bready = fabric$v_to_slaves_2_bready ; - assign uart0$slave_rready = fabric$v_to_slaves_2_rready ; - assign uart0$slave_wdata = fabric$v_to_slaves_2_wdata ; - assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; - assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; - assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_get_to_console_get = EN_get_to_console_get ; - assign uart0$EN_put_from_console_put = EN_put_from_console_put ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - begin - v__h11111 = $stime; - #0; - end - v__h11105 = v__h11111 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - $display("%0d:%m.rl_reset_start_initial ...", v__h11105); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - begin - v__h11381 = $stime; - #0; - end - v__h11375 = v__h11381 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - $display("%0d:%m.rl_reset_complete_initial", v__h11375); - end - // synopsys translate_on -endmodule // mkSoC_Top - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v deleted file mode 100644 index 470d28c6..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v +++ /dev/null @@ -1,328 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// CLK I 1 clock -// RST_N I 1 reset -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTop_HW_Side(CLK, - RST_N); - input CLK; - input RST_N; - - // register rg_banner_printed - reg rg_banner_printed; - wire rg_banner_printed$D_IN, rg_banner_printed$EN; - - // register rg_console_in_poll - reg [11 : 0] rg_console_in_poll; - wire [11 : 0] rg_console_in_poll$D_IN; - wire rg_console_in_poll$EN; - - // ports of submodule mem_model - wire [352 : 0] mem_model$mem_server_request_put; - wire [255 : 0] mem_model$mem_server_response_get; - wire mem_model$EN_mem_server_request_put, - mem_model$EN_mem_server_response_get, - mem_model$RDY_mem_server_request_put, - mem_model$RDY_mem_server_response_get; - - // ports of submodule soc_top - wire [352 : 0] soc_top$to_raw_mem_request_get; - wire [255 : 0] soc_top$to_raw_mem_response_put; - wire [63 : 0] soc_top$set_verbosity_logdelay, - soc_top$set_watch_tohost_tohost_addr; - wire [7 : 0] soc_top$get_to_console_get, - soc_top$put_from_console_put, - soc_top$status; - wire [3 : 0] soc_top$set_verbosity_verbosity; - wire soc_top$EN_get_to_console_get, - soc_top$EN_put_from_console_put, - soc_top$EN_set_verbosity, - soc_top$EN_set_watch_tohost, - soc_top$EN_to_raw_mem_request_get, - soc_top$EN_to_raw_mem_response_put, - soc_top$RDY_get_to_console_get, - soc_top$RDY_put_from_console_put, - soc_top$RDY_to_raw_mem_request_get, - soc_top$RDY_to_raw_mem_response_put, - soc_top$set_watch_tohost_watch_tohost; - - // rule scheduling signals - wire CAN_FIRE_RL_memCnx_ClientServerRequest, - CAN_FIRE_RL_memCnx_ClientServerResponse, - CAN_FIRE_RL_rl_relay_console_in, - CAN_FIRE_RL_rl_relay_console_out, - CAN_FIRE_RL_rl_step0, - CAN_FIRE_RL_rl_terminate, - WILL_FIRE_RL_memCnx_ClientServerRequest, - WILL_FIRE_RL_memCnx_ClientServerResponse, - WILL_FIRE_RL_rl_relay_console_in, - WILL_FIRE_RL_rl_relay_console_out, - WILL_FIRE_RL_rl_step0, - WILL_FIRE_RL_rl_terminate; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h702; - reg [31 : 0] v__h743; - reg TASK_testplusargs___d12; - reg TASK_testplusargs___d11; - reg TASK_testplusargs___d15; - reg [63 : 0] tohost_addr__h571; - reg [31 : 0] v__h633; - reg [7 : 0] v__h941; - reg [31 : 0] v__h627; - reg [31 : 0] v__h737; - reg [31 : 0] v__h696; - // synopsys translate_on - - // submodule mem_model - mkMem_Model mem_model(.CLK(CLK), - .RST_N(RST_N), - .mem_server_request_put(mem_model$mem_server_request_put), - .EN_mem_server_request_put(mem_model$EN_mem_server_request_put), - .EN_mem_server_response_get(mem_model$EN_mem_server_response_get), - .RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put), - .mem_server_response_get(mem_model$mem_server_response_get), - .RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get)); - - // submodule soc_top - mkSoC_Top soc_top(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(soc_top$put_from_console_put), - .set_verbosity_logdelay(soc_top$set_verbosity_logdelay), - .set_verbosity_verbosity(soc_top$set_verbosity_verbosity), - .set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost), - .to_raw_mem_response_put(soc_top$to_raw_mem_response_put), - .EN_set_verbosity(soc_top$EN_set_verbosity), - .EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put), - .EN_get_to_console_get(soc_top$EN_get_to_console_get), - .EN_put_from_console_put(soc_top$EN_put_from_console_put), - .EN_set_watch_tohost(soc_top$EN_set_watch_tohost), - .RDY_set_verbosity(), - .to_raw_mem_request_get(soc_top$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put), - .get_to_console_get(soc_top$get_to_console_get), - .RDY_get_to_console_get(soc_top$RDY_get_to_console_get), - .RDY_put_from_console_put(soc_top$RDY_put_from_console_put), - .status(soc_top$status), - .RDY_set_watch_tohost()); - - // rule RL_rl_terminate - assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ; - assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ; - - // rule RL_rl_step0 - assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ; - assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ; - - // rule RL_rl_relay_console_out - assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - - // rule RL_rl_relay_console_in - assign CAN_FIRE_RL_rl_relay_console_in = - rg_console_in_poll != 12'd0 || soc_top$RDY_put_from_console_put ; - assign WILL_FIRE_RL_rl_relay_console_in = CAN_FIRE_RL_rl_relay_console_in ; - - // rule RL_memCnx_ClientServerRequest - assign CAN_FIRE_RL_memCnx_ClientServerRequest = - soc_top$RDY_to_raw_mem_request_get && - mem_model$RDY_mem_server_request_put ; - assign WILL_FIRE_RL_memCnx_ClientServerRequest = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - - // rule RL_memCnx_ClientServerResponse - assign CAN_FIRE_RL_memCnx_ClientServerResponse = - soc_top$RDY_to_raw_mem_response_put && - mem_model$RDY_mem_server_response_get ; - assign WILL_FIRE_RL_memCnx_ClientServerResponse = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // register rg_banner_printed - assign rg_banner_printed$D_IN = 1'd1 ; - assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ; - - // register rg_console_in_poll - assign rg_console_in_poll$D_IN = rg_console_in_poll + 12'd1 ; - assign rg_console_in_poll$EN = CAN_FIRE_RL_rl_relay_console_in ; - - // submodule mem_model - assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ; - assign mem_model$EN_mem_server_request_put = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign mem_model$EN_mem_server_response_get = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // submodule soc_top - assign soc_top$put_from_console_put = v__h941 ; - assign soc_top$set_verbosity_logdelay = 64'd0 ; - assign soc_top$set_verbosity_verbosity = - TASK_testplusargs___d11 ? - 4'd2 : - (TASK_testplusargs___d12 ? 4'd1 : 4'd0) ; - assign soc_top$set_watch_tohost_tohost_addr = tohost_addr__h571 ; - assign soc_top$set_watch_tohost_watch_tohost = TASK_testplusargs___d15 ; - assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ; - assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ; - assign soc_top$EN_to_raw_mem_request_get = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign soc_top$EN_to_raw_mem_response_put = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ; - assign soc_top$EN_put_from_console_put = - WILL_FIRE_RL_rl_relay_console_in && - rg_console_in_poll == 12'd0 && - v__h941 != 8'd0 ; - assign soc_top$EN_set_watch_tohost = CAN_FIRE_RL_rl_step0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_banner_printed$EN) - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN; - if (rg_console_in_poll$EN) - rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY rg_console_in_poll$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_banner_printed = 1'h0; - rg_console_in_poll = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h702 = $stime; - #0; - end - v__h696 = v__h702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $display("%0d: %m:.rl_terminate: soc_top status is 0x%0h (= 0d%0d)", - v__h696, - soc_top$status, - soc_top$status); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h743 = $stime; - #0; - end - v__h737 = v__h743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $imported_c_end_timing({ 32'd0, v__h737 }); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Bluespec RISC-V standalone system simulation v1.2"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d12 = $test$plusargs("v1"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d11 = $test$plusargs("v2"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d15 = $test$plusargs("tohost"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - tohost_addr__h571 = $imported_c_get_symbol_val("tohost"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("INFO: watch_tohost = %0d, tohost_addr = 0x%0h", - TASK_testplusargs___d15, - tohost_addr__h571); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - v__h633 = $stime; - #0; - end - v__h627 = v__h633 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) $imported_c_start_timing({ 32'd0, v__h627 }); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) - $write("%c", soc_top$get_to_console_get); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_relay_console_in && rg_console_in_poll == 12'd0) - begin - v__h941 = $imported_c_trygetchar(8'hAA); - #0; - end - end - // synopsys translate_on -endmodule // mkTop_HW_Side - diff --git a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkUART.v b/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkUART.v deleted file mode 100644 index 21bb7515..00000000 --- a/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkUART.v +++ /dev/null @@ -1,2872 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// intr O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// put_from_console_put I 8 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_put_from_console_put I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkUART(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - intr); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method intr - output intr; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [7 : 0] get_to_console_get; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - intr, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register cfg_verbosity - reg [7 : 0] cfg_verbosity; - wire [7 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_dll - reg [7 : 0] rg_dll; - wire [7 : 0] rg_dll$D_IN; - wire rg_dll$EN; - - // register rg_dlm - reg [7 : 0] rg_dlm; - wire [7 : 0] rg_dlm$D_IN; - wire rg_dlm$EN; - - // register rg_fcr - reg [7 : 0] rg_fcr; - wire [7 : 0] rg_fcr$D_IN; - wire rg_fcr$EN; - - // register rg_ier - reg [7 : 0] rg_ier; - wire [7 : 0] rg_ier$D_IN; - wire rg_ier$EN; - - // register rg_lcr - reg [7 : 0] rg_lcr; - wire [7 : 0] rg_lcr$D_IN; - wire rg_lcr$EN; - - // register rg_lsr - reg [7 : 0] rg_lsr; - reg [7 : 0] rg_lsr$D_IN; - wire rg_lsr$EN; - - // register rg_mcr - reg [7 : 0] rg_mcr; - wire [7 : 0] rg_mcr$D_IN; - wire rg_mcr$EN; - - // register rg_msr - reg [7 : 0] rg_msr; - wire [7 : 0] rg_msr$D_IN; - wire rg_msr$EN; - - // register rg_rbr - reg [7 : 0] rg_rbr; - wire [7 : 0] rg_rbr$D_IN; - wire rg_rbr$EN; - - // register rg_scr - reg [7 : 0] rg_scr; - wire [7 : 0] rg_scr$D_IN; - wire rg_scr$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_thr - reg [7 : 0] rg_thr; - wire [7 : 0] rg_thr$D_IN; - wire rg_thr$EN; - - // ports of submodule f_from_console - wire [7 : 0] f_from_console$D_IN, f_from_console$D_OUT; - wire f_from_console$CLR, - f_from_console$DEQ, - f_from_console$EMPTY_N, - f_from_console$ENQ, - f_from_console$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_to_console - wire [7 : 0] f_to_console$D_IN, f_to_console$D_OUT; - wire f_to_console$CLR, - f_to_console$DEQ, - f_to_console$EMPTY_N, - f_to_console$ENQ, - f_to_console$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_receive, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_receive, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_rg_lsr$write_1__VAL_3; - wire MUX_rg_lsr$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2519; - reg [31 : 0] v__h2187; - reg [31 : 0] v__h2025; - reg [31 : 0] v__h2898; - reg [31 : 0] v__h3239; - reg [31 : 0] v__h3997; - reg [31 : 0] v__h3442; - reg [31 : 0] v__h4295; - reg [31 : 0] v__h4736; - reg [31 : 0] v__h4846; - reg [31 : 0] v__h1811; - reg [31 : 0] v__h1805; - reg [31 : 0] v__h2019; - reg [31 : 0] v__h2181; - reg [31 : 0] v__h2513; - reg [31 : 0] v__h2892; - reg [31 : 0] v__h3233; - reg [31 : 0] v__h3436; - reg [31 : 0] v__h3991; - reg [31 : 0] v__h4289; - reg [31 : 0] v__h4730; - reg [31 : 0] v__h4840; - // synopsys translate_on - - // remaining internal signals - reg [7 : 0] y_avValue_snd__h2683; - wire [63 : 0] rdata__h2759, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133; - wire [7 : 0] fn_iir__h1356, - new_lsr__h4503, - x__h2797, - y_avValue_snd__h2696, - y_avValue_snd__h2709, - y_avValue_snd__h2724, - y_avValue_snd__h2738; - wire [1 : 0] rdr_rresp__h2792, - v__h3144, - v__h3388, - v__h3566, - y_avValue_fst__h2737, - y_avValue_fst__h2751; - wire NOT_cfg_verbosity_read_ULE_1_24___d125, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d230, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d241, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d176, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d180, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d184, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d187, - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method get_to_console_get - assign get_to_console_get = f_to_console$D_OUT ; - assign RDY_get_to_console_get = f_to_console$EMPTY_N ; - assign CAN_FIRE_get_to_console_get = f_to_console$EMPTY_N ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = f_from_console$FULL_N ; - assign CAN_FIRE_put_from_console_put = f_from_console$FULL_N ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method intr - assign intr = !fn_iir__h1356[0] ; - - // submodule f_from_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_from_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_from_console$D_IN), - .ENQ(f_from_console$ENQ), - .DEQ(f_from_console$DEQ), - .CLR(f_from_console$CLR), - .D_OUT(f_from_console$D_OUT), - .FULL_N(f_from_console$FULL_N), - .EMPTY_N(f_from_console$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_to_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_to_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_to_console$D_IN), - .ENQ(f_to_console$ENQ), - .DEQ(f_to_console$DEQ), - .CLR(f_to_console$CLR), - .D_OUT(f_to_console$D_OUT), - .FULL_N(f_to_console$FULL_N), - .EMPTY_N(f_to_console$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 && - rg_state ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_receive - assign CAN_FIRE_RL_rl_receive = f_from_console$EMPTY_N && !rg_lsr[0] ; - assign WILL_FIRE_RL_rl_receive = - CAN_FIRE_RL_rl_receive && !WILL_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_rg_lsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 ; - assign MUX_rg_lsr$write_1__VAL_3 = { rg_lsr[7:1], 1'd0 } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 8'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_dll - assign rg_dll$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dll$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d180 || - WILL_FIRE_RL_rl_reset ; - - // register rg_dlm - assign rg_dlm$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dlm$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d187 || - WILL_FIRE_RL_rl_reset ; - - // register rg_fcr - assign rg_fcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_fcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h2 || - WILL_FIRE_RL_rl_reset ; - - // register rg_ier - assign rg_ier$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_ier$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d184 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lcr - assign rg_lcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_lcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h3 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lsr - always@(WILL_FIRE_RL_rl_reset or - WILL_FIRE_RL_rl_receive or - new_lsr__h4503 or - MUX_rg_lsr$write_1__SEL_3 or MUX_rg_lsr$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset: rg_lsr$D_IN = 8'd96; - WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h4503; - MUX_rg_lsr$write_1__SEL_3: rg_lsr$D_IN = MUX_rg_lsr$write_1__VAL_3; - default: rg_lsr$D_IN = 8'b10101010 /* unspecified value */ ; - endcase - assign rg_lsr$EN = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 || - WILL_FIRE_RL_rl_receive || - WILL_FIRE_RL_rl_reset ; - - // register rg_mcr - assign rg_mcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_mcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h4 || - WILL_FIRE_RL_rl_reset ; - - // register rg_msr - assign rg_msr$D_IN = 8'd0 ; - assign rg_msr$EN = CAN_FIRE_RL_rl_reset ; - - // register rg_rbr - assign rg_rbr$D_IN = f_from_console$D_OUT ; - assign rg_rbr$EN = WILL_FIRE_RL_rl_receive ; - - // register rg_scr - assign rg_scr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_scr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h7 || - WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = 1'd1 ; - assign rg_state$EN = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // register rg_thr - assign rg_thr$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_thr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d176 ; - - // submodule f_from_console - assign f_from_console$D_IN = put_from_console_put ; - assign f_from_console$ENQ = EN_put_from_console_put ; - assign f_from_console$DEQ = WILL_FIRE_RL_rl_receive ; - assign f_from_console$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_to_console - assign f_to_console$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign f_to_console$ENQ = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d176 ; - assign f_to_console$DEQ = EN_get_to_console_get ; - assign f_to_console$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h2759, - rdr_rresp__h2792, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3144 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_24___d125 = cfg_verbosity > 8'd1 ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d230 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - slave_xactor_f_wr_data$D_OUT[0] ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d241 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - !slave_xactor_f_wr_data$D_OUT[0] ; - assign fn_iir__h1356 = - (rg_ier[0] && rg_lsr[0]) ? 8'h04 : (rg_ier[1] ? 8'h02 : 8'd0) ; - assign new_lsr__h4503 = { rg_lsr[7:1], 1'd1 } ; - assign rdata__h2759 = { 56'd0, x__h2797 } ; - assign rdr_rresp__h2792 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0) ? - y_avValue_fst__h2751 : - 2'b10 ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 = - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d176 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d180 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d184 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d187 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - rg_lcr[7] ; - assign slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 = - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1] || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7] || - f_to_console$FULL_N) ; - assign v__h3144 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) ? - 2'b10 : - v__h3388 ; - assign v__h3388 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0) ? - v__h3566 : - 2'b11 ; - assign v__h3566 = y_avValue_fst__h2737 ; - assign x__h2797 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0 || - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) ? - 8'd0 : - y_avValue_snd__h2738 ; - assign y_avValue_fst__h2737 = 2'b0 ; - assign y_avValue_fst__h2751 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0) ? - y_avValue_fst__h2737 : - 2'b11 ; - assign y_avValue_snd__h2696 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - rg_lcr[7]) ? - rg_dlm : - y_avValue_snd__h2683 ; - assign y_avValue_snd__h2709 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - !rg_lcr[7]) ? - rg_ier : - y_avValue_snd__h2696 ; - assign y_avValue_snd__h2724 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - rg_lcr[7]) ? - rg_dll : - y_avValue_snd__h2709 ; - assign y_avValue_snd__h2738 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7]) ? - rg_rbr : - y_avValue_snd__h2724 ; - always@(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 or - fn_iir__h1356 or rg_lcr or rg_mcr or rg_lsr or rg_msr or rg_scr) - begin - case (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3]) - 3'h2: y_avValue_snd__h2683 = fn_iir__h1356; - 3'h3: y_avValue_snd__h2683 = rg_lcr; - 3'h4: y_avValue_snd__h2683 = rg_mcr; - 3'h5: y_avValue_snd__h2683 = rg_lsr; - 3'h6: y_avValue_snd__h2683 = rg_msr; - 3'h7: y_avValue_snd__h2683 = rg_scr; - default: y_avValue_snd__h2683 = 8'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dll <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dlm <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_fcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_ier <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lsr <= `BSV_ASSIGNMENT_DELAY 8'd96; - rg_mcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_msr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_scr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_dll$EN) rg_dll <= `BSV_ASSIGNMENT_DELAY rg_dll$D_IN; - if (rg_dlm$EN) rg_dlm <= `BSV_ASSIGNMENT_DELAY rg_dlm$D_IN; - if (rg_fcr$EN) rg_fcr <= `BSV_ASSIGNMENT_DELAY rg_fcr$D_IN; - if (rg_ier$EN) rg_ier <= `BSV_ASSIGNMENT_DELAY rg_ier$D_IN; - if (rg_lcr$EN) rg_lcr <= `BSV_ASSIGNMENT_DELAY rg_lcr$D_IN; - if (rg_lsr$EN) rg_lsr <= `BSV_ASSIGNMENT_DELAY rg_lsr$D_IN; - if (rg_mcr$EN) rg_mcr <= `BSV_ASSIGNMENT_DELAY rg_mcr$D_IN; - if (rg_msr$EN) rg_msr <= `BSV_ASSIGNMENT_DELAY rg_msr$D_IN; - if (rg_scr$EN) rg_scr <= `BSV_ASSIGNMENT_DELAY rg_scr$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_rbr$EN) rg_rbr <= `BSV_ASSIGNMENT_DELAY rg_rbr$D_IN; - if (rg_thr$EN) rg_thr <= `BSV_ASSIGNMENT_DELAY rg_thr$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 8'hAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_dll = 8'hAA; - rg_dlm = 8'hAA; - rg_fcr = 8'hAA; - rg_ier = 8'hAA; - rg_lcr = 8'hAA; - rg_lsr = 8'hAA; - rg_mcr = 8'hAA; - rg_msr = 8'hAA; - rg_rbr = 8'hAA; - rg_scr = 8'hAA; - rg_state = 1'h0; - rg_thr = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - begin - v__h2519 = $stime; - #0; - end - v__h2513 = v__h2519 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2513); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - begin - v__h2187 = $stime; - #0; - end - v__h2181 = v__h2187 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2181); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - begin - v__h2025 = $stime; - #0; - end - v__h2019 = v__h2025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: misaligned addr", - v__h2019); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h2898 = $stime; - #0; - end - v__h2892 = v__h2898 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_rd_req", v__h2892); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdata__h2759); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdr_rresp__h2792); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - begin - v__h3239 = $stime; - #0; - end - v__h3233 = v__h3239 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $display("%0d: ERROR: UART.rl_process_wr_req: misaligned addr", - v__h3233); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - begin - v__h3997 = $stime; - #0; - end - v__h3991 = v__h3997 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h3991); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d230) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d241) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - begin - v__h3442 = $stime; - #0; - end - v__h3436 = v__h3442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h3436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h4295 = $stime; - #0; - end - v__h4289 = v__h4295 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_wr_req", v__h4289); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", v__h3144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h4736 = $stime; - #0; - end - v__h4730 = v__h4736 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_base 0x%0h is not 8-Byte-aligned", - v__h4730, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h4846 = $stime; - #0; - end - v__h4840 = v__h4846 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_lim 0x%0h is not 8-Byte-aligned", - v__h4840, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_receive && NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("UART_Model.rl_receive: received char 0x%0h; new_lsr = 0x%0h", - f_from_console$D_OUT, - new_lsr__h4503); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - begin - v__h1811 = $stime; - #0; - end - v__h1805 = v__h1811 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - $display("%0d: UART.rl_reset", v__h1805); - end - // synopsys translate_on -endmodule // mkUART - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v deleted file mode 100644 index 1cb3bfa4..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v +++ /dev/null @@ -1,1415 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// from_master_awready O 1 reg -// from_master_wready O 1 reg -// from_master_bvalid O 1 reg -// from_master_bid O 4 reg -// from_master_bresp O 2 reg -// from_master_arready O 1 reg -// from_master_rvalid O 1 reg -// from_master_rid O 4 reg -// from_master_rdata O 64 reg -// from_master_rresp O 2 reg -// from_master_rlast O 1 reg -// to_slave_awvalid O 1 reg -// to_slave_awid O 4 reg -// to_slave_awaddr O 64 reg -// to_slave_awlen O 8 reg -// to_slave_awsize O 3 reg -// to_slave_awburst O 2 reg -// to_slave_awlock O 1 reg -// to_slave_awcache O 4 reg -// to_slave_awprot O 3 reg -// to_slave_awqos O 4 reg -// to_slave_awregion O 4 reg -// to_slave_wvalid O 1 reg -// to_slave_wid O 4 reg -// to_slave_wdata O 64 reg -// to_slave_wstrb O 8 reg -// to_slave_wlast O 1 reg -// to_slave_bready O 1 reg -// to_slave_arvalid O 1 reg -// to_slave_arid O 4 reg -// to_slave_araddr O 64 reg -// to_slave_arlen O 8 reg -// to_slave_arsize O 3 reg -// to_slave_arburst O 2 reg -// to_slave_arlock O 1 reg -// to_slave_arcache O 4 reg -// to_slave_arprot O 3 reg -// to_slave_arqos O 4 reg -// to_slave_arregion O 4 reg -// to_slave_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// from_master_awvalid I 1 -// from_master_awid I 4 reg -// from_master_awaddr I 64 reg -// from_master_awlen I 8 reg -// from_master_awsize I 3 reg -// from_master_awburst I 2 reg -// from_master_awlock I 1 reg -// from_master_awcache I 4 reg -// from_master_awprot I 3 reg -// from_master_awqos I 4 reg -// from_master_awregion I 4 reg -// from_master_wvalid I 1 -// from_master_wid I 4 reg -// from_master_wdata I 64 reg -// from_master_wstrb I 8 reg -// from_master_wlast I 1 reg -// from_master_bready I 1 -// from_master_arvalid I 1 -// from_master_arid I 4 reg -// from_master_araddr I 64 reg -// from_master_arlen I 8 reg -// from_master_arsize I 3 reg -// from_master_arburst I 2 reg -// from_master_arlock I 1 reg -// from_master_arcache I 4 reg -// from_master_arprot I 3 reg -// from_master_arqos I 4 reg -// from_master_arregion I 4 reg -// from_master_rready I 1 -// to_slave_awready I 1 -// to_slave_wready I 1 -// to_slave_bvalid I 1 -// to_slave_bid I 4 reg -// to_slave_bresp I 2 reg -// to_slave_arready I 1 -// to_slave_rvalid I 1 -// to_slave_rid I 4 reg -// to_slave_rdata I 64 reg -// to_slave_rresp I 2 reg -// to_slave_rlast I 1 reg -// EN_reset I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkAXI4_Deburster_A(CLK, - RST_N, - - EN_reset, - RDY_reset, - - from_master_awvalid, - from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion, - - from_master_awready, - - from_master_wvalid, - from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast, - - from_master_wready, - - from_master_bvalid, - - from_master_bid, - - from_master_bresp, - - from_master_bready, - - from_master_arvalid, - from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion, - - from_master_arready, - - from_master_rvalid, - - from_master_rid, - - from_master_rdata, - - from_master_rresp, - - from_master_rlast, - - from_master_rready, - - to_slave_awvalid, - - to_slave_awid, - - to_slave_awaddr, - - to_slave_awlen, - - to_slave_awsize, - - to_slave_awburst, - - to_slave_awlock, - - to_slave_awcache, - - to_slave_awprot, - - to_slave_awqos, - - to_slave_awregion, - - to_slave_awready, - - to_slave_wvalid, - - to_slave_wid, - - to_slave_wdata, - - to_slave_wstrb, - - to_slave_wlast, - - to_slave_wready, - - to_slave_bvalid, - to_slave_bid, - to_slave_bresp, - - to_slave_bready, - - to_slave_arvalid, - - to_slave_arid, - - to_slave_araddr, - - to_slave_arlen, - - to_slave_arsize, - - to_slave_arburst, - - to_slave_arlock, - - to_slave_arcache, - - to_slave_arprot, - - to_slave_arqos, - - to_slave_arregion, - - to_slave_arready, - - to_slave_rvalid, - to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast, - - to_slave_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method from_master_m_awvalid - input from_master_awvalid; - input [3 : 0] from_master_awid; - input [63 : 0] from_master_awaddr; - input [7 : 0] from_master_awlen; - input [2 : 0] from_master_awsize; - input [1 : 0] from_master_awburst; - input from_master_awlock; - input [3 : 0] from_master_awcache; - input [2 : 0] from_master_awprot; - input [3 : 0] from_master_awqos; - input [3 : 0] from_master_awregion; - - // value method from_master_m_awready - output from_master_awready; - - // action method from_master_m_wvalid - input from_master_wvalid; - input [3 : 0] from_master_wid; - input [63 : 0] from_master_wdata; - input [7 : 0] from_master_wstrb; - input from_master_wlast; - - // value method from_master_m_wready - output from_master_wready; - - // value method from_master_m_bvalid - output from_master_bvalid; - - // value method from_master_m_bid - output [3 : 0] from_master_bid; - - // value method from_master_m_bresp - output [1 : 0] from_master_bresp; - - // value method from_master_m_buser - - // action method from_master_m_bready - input from_master_bready; - - // action method from_master_m_arvalid - input from_master_arvalid; - input [3 : 0] from_master_arid; - input [63 : 0] from_master_araddr; - input [7 : 0] from_master_arlen; - input [2 : 0] from_master_arsize; - input [1 : 0] from_master_arburst; - input from_master_arlock; - input [3 : 0] from_master_arcache; - input [2 : 0] from_master_arprot; - input [3 : 0] from_master_arqos; - input [3 : 0] from_master_arregion; - - // value method from_master_m_arready - output from_master_arready; - - // value method from_master_m_rvalid - output from_master_rvalid; - - // value method from_master_m_rid - output [3 : 0] from_master_rid; - - // value method from_master_m_rdata - output [63 : 0] from_master_rdata; - - // value method from_master_m_rresp - output [1 : 0] from_master_rresp; - - // value method from_master_m_rlast - output from_master_rlast; - - // value method from_master_m_ruser - - // action method from_master_m_rready - input from_master_rready; - - // value method to_slave_m_awvalid - output to_slave_awvalid; - - // value method to_slave_m_awid - output [3 : 0] to_slave_awid; - - // value method to_slave_m_awaddr - output [63 : 0] to_slave_awaddr; - - // value method to_slave_m_awlen - output [7 : 0] to_slave_awlen; - - // value method to_slave_m_awsize - output [2 : 0] to_slave_awsize; - - // value method to_slave_m_awburst - output [1 : 0] to_slave_awburst; - - // value method to_slave_m_awlock - output to_slave_awlock; - - // value method to_slave_m_awcache - output [3 : 0] to_slave_awcache; - - // value method to_slave_m_awprot - output [2 : 0] to_slave_awprot; - - // value method to_slave_m_awqos - output [3 : 0] to_slave_awqos; - - // value method to_slave_m_awregion - output [3 : 0] to_slave_awregion; - - // value method to_slave_m_awuser - - // action method to_slave_m_awready - input to_slave_awready; - - // value method to_slave_m_wvalid - output to_slave_wvalid; - - // value method to_slave_m_wid - output [3 : 0] to_slave_wid; - - // value method to_slave_m_wdata - output [63 : 0] to_slave_wdata; - - // value method to_slave_m_wstrb - output [7 : 0] to_slave_wstrb; - - // value method to_slave_m_wlast - output to_slave_wlast; - - // value method to_slave_m_wuser - - // action method to_slave_m_wready - input to_slave_wready; - - // action method to_slave_m_bvalid - input to_slave_bvalid; - input [3 : 0] to_slave_bid; - input [1 : 0] to_slave_bresp; - - // value method to_slave_m_bready - output to_slave_bready; - - // value method to_slave_m_arvalid - output to_slave_arvalid; - - // value method to_slave_m_arid - output [3 : 0] to_slave_arid; - - // value method to_slave_m_araddr - output [63 : 0] to_slave_araddr; - - // value method to_slave_m_arlen - output [7 : 0] to_slave_arlen; - - // value method to_slave_m_arsize - output [2 : 0] to_slave_arsize; - - // value method to_slave_m_arburst - output [1 : 0] to_slave_arburst; - - // value method to_slave_m_arlock - output to_slave_arlock; - - // value method to_slave_m_arcache - output [3 : 0] to_slave_arcache; - - // value method to_slave_m_arprot - output [2 : 0] to_slave_arprot; - - // value method to_slave_m_arqos - output [3 : 0] to_slave_arqos; - - // value method to_slave_m_arregion - output [3 : 0] to_slave_arregion; - - // value method to_slave_m_aruser - - // action method to_slave_m_arready - input to_slave_arready; - - // action method to_slave_m_rvalid - input to_slave_rvalid; - input [3 : 0] to_slave_rid; - input [63 : 0] to_slave_rdata; - input [1 : 0] to_slave_rresp; - input to_slave_rlast; - - // value method to_slave_m_rready - output to_slave_rready; - - // signals for module outputs - wire [63 : 0] from_master_rdata, - to_slave_araddr, - to_slave_awaddr, - to_slave_wdata; - wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb; - wire [3 : 0] from_master_bid, - from_master_rid, - to_slave_arcache, - to_slave_arid, - to_slave_arqos, - to_slave_arregion, - to_slave_awcache, - to_slave_awid, - to_slave_awqos, - to_slave_awregion, - to_slave_wid; - wire [2 : 0] to_slave_arprot, - to_slave_arsize, - to_slave_awprot, - to_slave_awsize; - wire [1 : 0] from_master_bresp, - from_master_rresp, - to_slave_arburst, - to_slave_awburst; - wire RDY_reset, - from_master_arready, - from_master_awready, - from_master_bvalid, - from_master_rlast, - from_master_rvalid, - from_master_wready, - to_slave_arlock, - to_slave_arvalid, - to_slave_awlock, - to_slave_awvalid, - to_slave_bready, - to_slave_rready, - to_slave_wlast, - to_slave_wvalid; - - // register m_rg_ar_beat_count - reg [7 : 0] m_rg_ar_beat_count; - wire [7 : 0] m_rg_ar_beat_count$D_IN; - wire m_rg_ar_beat_count$EN; - - // register m_rg_b_beat_count - reg [7 : 0] m_rg_b_beat_count; - wire [7 : 0] m_rg_b_beat_count$D_IN; - wire m_rg_b_beat_count$EN; - - // register m_rg_b_resp - reg [1 : 0] m_rg_b_resp; - wire [1 : 0] m_rg_b_resp$D_IN; - wire m_rg_b_resp$EN; - - // register m_rg_r_beat_count - reg [7 : 0] m_rg_r_beat_count; - wire [7 : 0] m_rg_r_beat_count$D_IN; - wire m_rg_r_beat_count$EN; - - // register m_rg_reset - reg m_rg_reset; - wire m_rg_reset$D_IN, m_rg_reset$EN; - - // register m_rg_w_beat_count - reg [7 : 0] m_rg_w_beat_count; - wire [7 : 0] m_rg_w_beat_count$D_IN; - wire m_rg_w_beat_count$EN; - - // ports of submodule m_f_r_arlen - wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT; - wire m_f_r_arlen$CLR, - m_f_r_arlen$DEQ, - m_f_r_arlen$EMPTY_N, - m_f_r_arlen$ENQ, - m_f_r_arlen$FULL_N; - - // ports of submodule m_f_w_awlen - wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT; - wire m_f_w_awlen$CLR, - m_f_w_awlen$DEQ, - m_f_w_awlen$EMPTY_N, - m_f_w_awlen$ENQ, - m_f_w_awlen$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_addr - wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN, - m_xactor_from_master_f_rd_addr$D_OUT; - wire m_xactor_from_master_f_rd_addr$CLR, - m_xactor_from_master_f_rd_addr$DEQ, - m_xactor_from_master_f_rd_addr$EMPTY_N, - m_xactor_from_master_f_rd_addr$ENQ, - m_xactor_from_master_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_data - wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN, - m_xactor_from_master_f_rd_data$D_OUT; - wire m_xactor_from_master_f_rd_data$CLR, - m_xactor_from_master_f_rd_data$DEQ, - m_xactor_from_master_f_rd_data$EMPTY_N, - m_xactor_from_master_f_rd_data$ENQ, - m_xactor_from_master_f_rd_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_addr - wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN, - m_xactor_from_master_f_wr_addr$D_OUT; - wire m_xactor_from_master_f_wr_addr$CLR, - m_xactor_from_master_f_wr_addr$DEQ, - m_xactor_from_master_f_wr_addr$EMPTY_N, - m_xactor_from_master_f_wr_addr$ENQ, - m_xactor_from_master_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_data - wire [76 : 0] m_xactor_from_master_f_wr_data$D_IN, - m_xactor_from_master_f_wr_data$D_OUT; - wire m_xactor_from_master_f_wr_data$CLR, - m_xactor_from_master_f_wr_data$DEQ, - m_xactor_from_master_f_wr_data$EMPTY_N, - m_xactor_from_master_f_wr_data$ENQ, - m_xactor_from_master_f_wr_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_resp - wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN, - m_xactor_from_master_f_wr_resp$D_OUT; - wire m_xactor_from_master_f_wr_resp$CLR, - m_xactor_from_master_f_wr_resp$DEQ, - m_xactor_from_master_f_wr_resp$EMPTY_N, - m_xactor_from_master_f_wr_resp$ENQ, - m_xactor_from_master_f_wr_resp$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_addr - wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN, - m_xactor_to_slave_f_rd_addr$D_OUT; - wire m_xactor_to_slave_f_rd_addr$CLR, - m_xactor_to_slave_f_rd_addr$DEQ, - m_xactor_to_slave_f_rd_addr$EMPTY_N, - m_xactor_to_slave_f_rd_addr$ENQ, - m_xactor_to_slave_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_data - wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN, - m_xactor_to_slave_f_rd_data$D_OUT; - wire m_xactor_to_slave_f_rd_data$CLR, - m_xactor_to_slave_f_rd_data$DEQ, - m_xactor_to_slave_f_rd_data$EMPTY_N, - m_xactor_to_slave_f_rd_data$ENQ, - m_xactor_to_slave_f_rd_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_addr - wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN, - m_xactor_to_slave_f_wr_addr$D_OUT; - wire m_xactor_to_slave_f_wr_addr$CLR, - m_xactor_to_slave_f_wr_addr$DEQ, - m_xactor_to_slave_f_wr_addr$EMPTY_N, - m_xactor_to_slave_f_wr_addr$ENQ, - m_xactor_to_slave_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_data - wire [76 : 0] m_xactor_to_slave_f_wr_data$D_IN, - m_xactor_to_slave_f_wr_data$D_OUT; - wire m_xactor_to_slave_f_wr_data$CLR, - m_xactor_to_slave_f_wr_data$DEQ, - m_xactor_to_slave_f_wr_data$EMPTY_N, - m_xactor_to_slave_f_wr_data$ENQ, - m_xactor_to_slave_f_wr_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_resp - wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN, - m_xactor_to_slave_f_wr_resp$D_OUT; - wire m_xactor_to_slave_f_wr_resp$CLR, - m_xactor_to_slave_f_wr_resp$DEQ, - m_xactor_to_slave_f_wr_resp$EMPTY_N, - m_xactor_to_slave_f_wr_resp$ENQ, - m_xactor_to_slave_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave, - CAN_FIRE_from_master_m_arvalid, - CAN_FIRE_from_master_m_awvalid, - CAN_FIRE_from_master_m_bready, - CAN_FIRE_from_master_m_rready, - CAN_FIRE_from_master_m_wvalid, - CAN_FIRE_reset, - CAN_FIRE_to_slave_m_arready, - CAN_FIRE_to_slave_m_awready, - CAN_FIRE_to_slave_m_bvalid, - CAN_FIRE_to_slave_m_rvalid, - CAN_FIRE_to_slave_m_wready, - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave, - WILL_FIRE_from_master_m_arvalid, - WILL_FIRE_from_master_m_awvalid, - WILL_FIRE_from_master_m_bready, - WILL_FIRE_from_master_m_rready, - WILL_FIRE_from_master_m_wvalid, - WILL_FIRE_reset, - WILL_FIRE_to_slave_m_arready, - WILL_FIRE_to_slave_m_awready, - WILL_FIRE_to_slave_m_bvalid, - WILL_FIRE_to_slave_m_rvalid, - WILL_FIRE_to_slave_m_wready; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2, - MUX_m_rg_b_beat_count$write_1__VAL_2, - MUX_m_rg_r_beat_count$write_1__VAL_2, - MUX_m_rg_w_beat_count$write_1__VAL_2; - wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2; - wire MUX_m_rg_b_resp$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2430; - reg [31 : 0] v__h1446; - reg [31 : 0] v__h1440; - reg [31 : 0] v__h2424; - // synopsys translate_on - - // remaining internal signals - wire [63 : 0] a_out_araddr__h2944, - a_out_awaddr__h1951, - addr___1__h2036, - addr___1__h3029; - wire [7 : 0] x__h2305, x__h2798, x__h3190, x__h3388; - wire m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95, - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51, - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106, - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35; - - // action method reset - assign RDY_reset = !m_rg_reset ; - assign CAN_FIRE_reset = !m_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method from_master_m_awvalid - assign CAN_FIRE_from_master_m_awvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_awvalid = 1'd1 ; - - // value method from_master_m_awready - assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ; - - // action method from_master_m_wvalid - assign CAN_FIRE_from_master_m_wvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_wvalid = 1'd1 ; - - // value method from_master_m_wready - assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ; - - // value method from_master_m_bvalid - assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ; - - // value method from_master_m_bid - assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ; - - // value method from_master_m_bresp - assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ; - - // action method from_master_m_bready - assign CAN_FIRE_from_master_m_bready = 1'd1 ; - assign WILL_FIRE_from_master_m_bready = 1'd1 ; - - // action method from_master_m_arvalid - assign CAN_FIRE_from_master_m_arvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_arvalid = 1'd1 ; - - // value method from_master_m_arready - assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ; - - // value method from_master_m_rvalid - assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ; - - // value method from_master_m_rid - assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ; - - // value method from_master_m_rdata - assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ; - - // value method from_master_m_rresp - assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ; - - // value method from_master_m_rlast - assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ; - - // action method from_master_m_rready - assign CAN_FIRE_from_master_m_rready = 1'd1 ; - assign WILL_FIRE_from_master_m_rready = 1'd1 ; - - // value method to_slave_m_awvalid - assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ; - - // value method to_slave_m_awid - assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ; - - // value method to_slave_m_awaddr - assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ; - - // value method to_slave_m_awlen - assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ; - - // value method to_slave_m_awsize - assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ; - - // value method to_slave_m_awburst - assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ; - - // value method to_slave_m_awlock - assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ; - - // value method to_slave_m_awcache - assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ; - - // value method to_slave_m_awprot - assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ; - - // value method to_slave_m_awqos - assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ; - - // value method to_slave_m_awregion - assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ; - - // action method to_slave_m_awready - assign CAN_FIRE_to_slave_m_awready = 1'd1 ; - assign WILL_FIRE_to_slave_m_awready = 1'd1 ; - - // value method to_slave_m_wvalid - assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ; - - // value method to_slave_m_wid - assign to_slave_wid = m_xactor_to_slave_f_wr_data$D_OUT[76:73] ; - - // value method to_slave_m_wdata - assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ; - - // value method to_slave_m_wstrb - assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ; - - // value method to_slave_m_wlast - assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ; - - // action method to_slave_m_wready - assign CAN_FIRE_to_slave_m_wready = 1'd1 ; - assign WILL_FIRE_to_slave_m_wready = 1'd1 ; - - // action method to_slave_m_bvalid - assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ; - - // value method to_slave_m_bready - assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ; - - // value method to_slave_m_arvalid - assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ; - - // value method to_slave_m_arid - assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ; - - // value method to_slave_m_araddr - assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ; - - // value method to_slave_m_arlen - assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ; - - // value method to_slave_m_arsize - assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ; - - // value method to_slave_m_arburst - assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ; - - // value method to_slave_m_arlock - assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ; - - // value method to_slave_m_arcache - assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ; - - // value method to_slave_m_arprot - assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ; - - // value method to_slave_m_arqos - assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ; - - // value method to_slave_m_arregion - assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ; - - // action method to_slave_m_arready - assign CAN_FIRE_to_slave_m_arready = 1'd1 ; - assign WILL_FIRE_to_slave_m_arready = 1'd1 ; - - // action method to_slave_m_rvalid - assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ; - - // value method to_slave_m_rready - assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ; - - // submodule m_f_r_arlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_r_arlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_r_arlen$D_IN), - .ENQ(m_f_r_arlen$ENQ), - .DEQ(m_f_r_arlen$DEQ), - .CLR(m_f_r_arlen$CLR), - .D_OUT(m_f_r_arlen$D_OUT), - .FULL_N(m_f_r_arlen$FULL_N), - .EMPTY_N(m_f_r_arlen$EMPTY_N)); - - // submodule m_f_w_awlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_w_awlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_w_awlen$D_IN), - .ENQ(m_f_w_awlen$ENQ), - .DEQ(m_f_w_awlen$DEQ), - .CLR(m_f_w_awlen$CLR), - .D_OUT(m_f_w_awlen$D_OUT), - .FULL_N(m_f_w_awlen$FULL_N), - .EMPTY_N(m_f_w_awlen$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_addr$D_IN), - .ENQ(m_xactor_from_master_f_rd_addr$ENQ), - .DEQ(m_xactor_from_master_f_rd_addr$DEQ), - .CLR(m_xactor_from_master_f_rd_addr$CLR), - .D_OUT(m_xactor_from_master_f_rd_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_data$D_IN), - .ENQ(m_xactor_from_master_f_rd_data$ENQ), - .DEQ(m_xactor_from_master_f_rd_data$DEQ), - .CLR(m_xactor_from_master_f_rd_data$CLR), - .D_OUT(m_xactor_from_master_f_rd_data$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_addr$D_IN), - .ENQ(m_xactor_from_master_f_wr_addr$ENQ), - .DEQ(m_xactor_from_master_f_wr_addr$DEQ), - .CLR(m_xactor_from_master_f_wr_addr$CLR), - .D_OUT(m_xactor_from_master_f_wr_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_data$D_IN), - .ENQ(m_xactor_from_master_f_wr_data$ENQ), - .DEQ(m_xactor_from_master_f_wr_data$DEQ), - .CLR(m_xactor_from_master_f_wr_data$CLR), - .D_OUT(m_xactor_from_master_f_wr_data$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_resp$D_IN), - .ENQ(m_xactor_from_master_f_wr_resp$ENQ), - .DEQ(m_xactor_from_master_f_wr_resp$DEQ), - .CLR(m_xactor_from_master_f_wr_resp$CLR), - .D_OUT(m_xactor_from_master_f_wr_resp$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_addr$D_IN), - .ENQ(m_xactor_to_slave_f_rd_addr$ENQ), - .DEQ(m_xactor_to_slave_f_rd_addr$DEQ), - .CLR(m_xactor_to_slave_f_rd_addr$CLR), - .D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_data$D_IN), - .ENQ(m_xactor_to_slave_f_rd_data$ENQ), - .DEQ(m_xactor_to_slave_f_rd_data$DEQ), - .CLR(m_xactor_to_slave_f_rd_data$CLR), - .D_OUT(m_xactor_to_slave_f_rd_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_addr$D_IN), - .ENQ(m_xactor_to_slave_f_wr_addr$ENQ), - .DEQ(m_xactor_to_slave_f_wr_addr$DEQ), - .CLR(m_xactor_to_slave_f_wr_addr$CLR), - .D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_data$D_IN), - .ENQ(m_xactor_to_slave_f_wr_data$ENQ), - .DEQ(m_xactor_to_slave_f_wr_data$DEQ), - .CLR(m_xactor_to_slave_f_wr_data$CLR), - .D_OUT(m_xactor_to_slave_f_wr_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_resp$D_IN), - .ENQ(m_xactor_to_slave_f_wr_resp$ENQ), - .DEQ(m_xactor_to_slave_f_wr_resp$DEQ), - .CLR(m_xactor_to_slave_f_wr_resp$CLR), - .D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave = - m_xactor_to_slave_f_wr_addr$FULL_N && - m_xactor_from_master_f_wr_addr$EMPTY_N && - m_xactor_to_slave_f_wr_data$FULL_N && - m_xactor_from_master_f_wr_data$EMPTY_N && - (m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - - // rule RL_m_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master = - m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N && - (m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 || - m_xactor_from_master_f_wr_resp$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - - // rule RL_m_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave = - m_xactor_to_slave_f_rd_addr$FULL_N && - m_xactor_from_master_f_rd_addr$EMPTY_N && - (m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - - // rule RL_m_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master = - m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N && - m_xactor_from_master_f_rd_data$FULL_N ; - assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ; - assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_b_resp$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - (m_rg_b_resp == 2'b0 && - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 || - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51) ; - assign MUX_m_rg_ar_beat_count$write_1__VAL_2 = - m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ? - x__h3190 : - 8'd0 ; - assign MUX_m_rg_b_beat_count$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - x__h2798 : - 8'd0 ; - assign MUX_m_rg_b_resp$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - 2'b0 ; - assign MUX_m_rg_r_beat_count$write_1__VAL_2 = - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ? - x__h3388 : - 8'd0 ; - assign MUX_m_rg_w_beat_count$write_1__VAL_2 = - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ? - x__h2305 : - 8'd0 ; - - // register m_rg_ar_beat_count - assign m_rg_ar_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ; - assign m_rg_ar_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ; - - // register m_rg_b_beat_count - assign m_rg_b_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ; - assign m_rg_b_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ; - - // register m_rg_b_resp - assign m_rg_b_resp$D_IN = - m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ; - assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ; - - // register m_rg_r_beat_count - assign m_rg_r_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ; - assign m_rg_r_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ; - - // register m_rg_reset - assign m_rg_reset$D_IN = !m_rg_reset ; - assign m_rg_reset$EN = m_rg_reset || EN_reset ; - - // register m_rg_w_beat_count - assign m_rg_w_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ; - assign m_rg_w_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ; - - // submodule m_f_r_arlen - assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_f_r_arlen$ENQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - m_rg_ar_beat_count == 8'd0 ; - assign m_f_r_arlen$DEQ = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master && - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ; - assign m_f_r_arlen$CLR = m_rg_reset ; - - // submodule m_f_w_awlen - assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign m_f_w_awlen$ENQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - m_rg_w_beat_count == 8'd0 ; - assign m_f_w_awlen$DEQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_f_w_awlen$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_addr - assign m_xactor_from_master_f_rd_addr$D_IN = - { from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion } ; - assign m_xactor_from_master_f_rd_addr$ENQ = - from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ; - assign m_xactor_from_master_f_rd_addr$DEQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - !m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ; - assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_data - assign m_xactor_from_master_f_rd_data$D_IN = - { m_xactor_to_slave_f_rd_data$D_OUT[70:1], - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 } ; - assign m_xactor_from_master_f_rd_data$ENQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_from_master_f_rd_data$DEQ = - from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ; - assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_addr - assign m_xactor_from_master_f_wr_addr$D_IN = - { from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion } ; - assign m_xactor_from_master_f_wr_addr$ENQ = - from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ; - assign m_xactor_from_master_f_wr_addr$DEQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ; - assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_data - assign m_xactor_from_master_f_wr_data$D_IN = - { from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast } ; - assign m_xactor_from_master_f_wr_data$ENQ = - from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ; - assign m_xactor_from_master_f_wr_data$DEQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_resp - assign m_xactor_from_master_f_wr_resp$D_IN = - { m_xactor_to_slave_f_wr_resp$D_OUT[5:2], - (m_rg_b_resp == 2'b0) ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - m_rg_b_resp } ; - assign m_xactor_from_master_f_wr_resp$ENQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_xactor_from_master_f_wr_resp$DEQ = - from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ; - assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_addr - assign m_xactor_to_slave_f_rd_addr$D_IN = - { m_xactor_from_master_f_rd_addr$D_OUT[96:93], - a_out_araddr__h2944, - 8'd0, - m_xactor_from_master_f_rd_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_rd_addr$ENQ = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - assign m_xactor_to_slave_f_rd_addr$DEQ = - m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ; - assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_data - assign m_xactor_to_slave_f_rd_data$D_IN = - { to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast } ; - assign m_xactor_to_slave_f_rd_data$ENQ = - to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ; - assign m_xactor_to_slave_f_rd_data$DEQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_addr - assign m_xactor_to_slave_f_wr_addr$D_IN = - { m_xactor_from_master_f_wr_addr$D_OUT[96:93], - a_out_awaddr__h1951, - 8'd0, - m_xactor_from_master_f_wr_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_wr_addr$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_addr$DEQ = - m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ; - assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_data - assign m_xactor_to_slave_f_wr_data$D_IN = - { m_xactor_from_master_f_wr_data$D_OUT[76:1], 1'd1 } ; - assign m_xactor_to_slave_f_wr_data$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_data$DEQ = - m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ; - assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_resp - assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ; - assign m_xactor_to_slave_f_wr_resp$ENQ = - to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ; - assign m_xactor_to_slave_f_wr_resp$DEQ = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ; - - // remaining internal signals - assign a_out_araddr__h2944 = - (m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h3029 : - m_xactor_from_master_f_rd_addr$D_OUT[92:29] ; - assign a_out_awaddr__h1951 = - (m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h2036 : - m_xactor_from_master_f_wr_addr$D_OUT[92:29] ; - assign addr___1__h2036 = - m_xactor_from_master_f_wr_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_w_beat_count } << - m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ; - assign addr___1__h3029 = - m_xactor_from_master_f_rd_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_ar_beat_count } << - m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ; - assign m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 = - m_rg_ar_beat_count < - m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 = - m_rg_b_beat_count < m_f_w_awlen$D_OUT ; - assign m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 = - m_rg_r_beat_count < m_f_r_arlen$D_OUT ; - assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 = - m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign x__h2305 = m_rg_w_beat_count + 8'd1 ; - assign x__h2798 = m_rg_b_beat_count + 8'd1 ; - assign x__h3190 = m_rg_ar_beat_count + 8'd1 ; - assign x__h3388 = m_rg_r_beat_count + 8'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0; - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (m_rg_ar_beat_count$EN) - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN; - if (m_rg_b_beat_count$EN) - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN; - if (m_rg_b_resp$EN) - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN; - if (m_rg_r_beat_count$EN) - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN; - if (m_rg_reset$EN) - m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN; - if (m_rg_w_beat_count$EN) - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_ar_beat_count = 8'hAA; - m_rg_b_beat_count = 8'hAA; - m_rg_b_resp = 2'h2; - m_rg_r_beat_count = 8'hAA; - m_rg_reset = 1'h0; - m_rg_w_beat_count = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - begin - v__h2430 = $stime; - #0; - end - v__h2424 = v__h2430 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", - v__h2424); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display(" WLAST not set on last data beat (awlen = %0d)", - m_xactor_from_master_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) - begin - v__h1446 = $stime; - #0; - end - v__h1440 = v__h1446 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) $display("%0d: %m::AXI4_Deburster.rl_reset", v__h1440); - end - // synopsys translate_on -endmodule // mkAXI4_Deburster_A - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v deleted file mode 100644 index 41b42457..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v +++ /dev/null @@ -1,2157 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkBoot_ROM(CLK, - RST_N, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready); - input CLK; - input RST_N; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_set_addr_map, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_module_ready - reg rg_module_ready; - wire rg_module_ready$D_IN, rg_module_ready$EN; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h808; - reg [31 : 0] v__h8928; - reg [31 : 0] v__h9221; - reg [31 : 0] v__h9331; - reg [31 : 0] v__h802; - reg [31 : 0] v__h8922; - reg [31 : 0] v__h9215; - reg [31 : 0] v__h9325; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] data64__h987; - reg [31 : 0] CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2; - wire [63 : 0] byte_addr__h705, rdata__h924; - wire [1 : 0] rdr_rresp__h957; - wire NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18, - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_module_ready - assign rg_module_ready$D_IN = 1'd1 ; - assign rg_module_ready$EN = EN_set_addr_map ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h924, - rdr_rresp__h957, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 ? - 2'b10 : - 2'b0 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = 1'b0 ; - - // remaining internal signals - assign NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 = - slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] || - slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ; - assign NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 = - slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] || - slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ; - assign byte_addr__h705 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign rdata__h924 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 64'd0 : - data64__h987 ; - assign rdr_rresp__h957 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 2'b10 : - 2'b0 ; - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16, - 64'd24, - 64'd56, - 64'd72, - 64'd80, - 64'd88, - 64'd200, - 64'd232, - 64'd312, - 64'd424, - 64'd448, - 64'd600, - 64'd728, - 64'd1136, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = 32'h0; - 64'd32: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h54040000; - 64'd40: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h88030000; - 64'd48: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h11000000; - 64'd64: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h50030000; - 64'd96, - 64'd112, - 64'd208, - 64'd224, - 64'd240, - 64'd432, - 64'd488, - 64'd872, - 64'd888: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h04000000; - 64'd104, 64'd120, 64'd504, 64'd792, 64'd920: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h02000000; - 64'd128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h16000000; - 64'd136: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h62626375; - 64'd144: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656B6970; - 64'd152: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65642D65; - 64'd160, - 64'd264, - 64'd280, - 64'd296, - 64'd336, - 64'd360, - 64'd384, - 64'd456, - 64'd552, - 64'd592, - 64'd608, - 64'd624, - 64'd672, - 64'd704, - 64'd760, - 64'd816, - 64'd840, - 64'd880: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h03000000; - 64'd168: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h26000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h732C7261; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7261622D; - 64'd192, - 64'd216, - 64'd400, - 64'd440, - 64'd496, - 64'd512, - 64'd584, - 64'd744, - 64'd752, - 64'd912: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h01000000; - 64'd248, 64'd896: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h80969800; - 64'd256: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40757063; - 64'd272: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h3F000000; - 64'd288, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4B000000; - 64'd304: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4F000000; - 64'd320: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h06000000; - 64'd328: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h63736972; - 64'd344: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h56000000; - 64'd352: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h75616D69; - 64'd368: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h60000000; - 64'd376: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h76732C76; - 64'd392: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69000000; - 64'd408: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70757272; - 64'd416: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F72746E; - 64'd464, 64'd632, 64'd712, 64'd824: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h1B000000; - 64'd472: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70632C76; - 64'd480: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00006374; - 64'd520: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h38407972; - 64'd528: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00303030; - 64'd536: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h07000000; - 64'd544: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D656D; - 64'd568: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000080; - 64'd576: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000010; - 64'd616: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h0F000000; - 64'd656: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69730063; - 64'd664: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7375622D; - 64'd680: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hA7000000; - 64'd688: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E696C63; - 64'd696, 64'd808: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h30303030; - 64'd720: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C632C76; - 64'd736: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h10000000; - 64'd776: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000002; - 64'd784: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000C00; - 64'd800: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h74726175; - 64'd832: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61303535; - 64'd856: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h000000C0; - 64'd864: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40000000; - 64'd904: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h08000000; - 64'd928: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h09000000; - 64'd936: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73736572; - 64'd944: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h2300736C; - 64'd952: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C65632D; - 64'd960: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61706D6F; - 64'd968: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D0065; - 64'd976: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656D6974; - 64'd984: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6572662D; - 64'd992: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h64007963; - 64'd1000: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79745F65; - 64'd1008: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73006765; - 64'd1016: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69720073; - 64'd1024: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00617369; - 64'd1032: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65707974; - 64'd1040: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h662D6B63; - 64'd1048: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79636E65; - 64'd1056, 64'd1072: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h72726574; - 64'd1064: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C6C6563; - 64'd1080: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h746E6F63; - 64'd1088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70007265; - 64'd1096: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7200656C; - 64'd1104: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E690073; - 64'd1112: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73747075; - 64'd1120: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65646E65; - 64'd1128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h68732D67; - default: CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00028067; - 64'd24: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80000000; - 64'd32: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hEDFE0DD0; - 64'd40: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h38000000; - 64'd48: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h28000000; - 64'd56, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h10000000; - 64'd64: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hCC000000; - 64'd72, - 64'd80, - 64'd104, - 64'd216, - 64'd296, - 64'd568, - 64'd576, - 64'd672, - 64'd680, - 64'd776, - 64'd784, - 64'd840, - 64'd856, - 64'd864, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = 32'h0; - 64'd88, 64'd256, 64'd688, 64'd800: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h01000000; - 64'd96, - 64'd112, - 64'd128, - 64'd208, - 64'd224, - 64'd240, - 64'd320, - 64'd432, - 64'd448, - 64'd488, - 64'd536, - 64'd736, - 64'd752, - 64'd872, - 64'd888, - 64'd904: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h03000000; - 64'd120, 64'd232, 64'd464: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0F000000; - 64'd136, 64'd328: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h1B000000; - 64'd144: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h732C7261; - 64'd152: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7261622D; - 64'd160, 64'd336: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000076; - 64'd168: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h12000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h62626375; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656B6970; - 64'd192: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000065; - 64'd200: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h73757063; - 64'd248: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C000000; - 64'd264, 64'd704, 64'd816: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000030; - 64'd272, 64'd288, 64'd392, 64'd600, 64'd616: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h04000000; - 64'd280: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00757063; - 64'd304: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h05000000; - 64'd312: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79616B6F; - 64'd344: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0A000000; - 64'd352: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h34367672; - 64'd360: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000073; - 64'd368, 64'd920: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0B000000; - 64'd376, 64'd472, 64'd720: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63736972; - 64'd384: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00003933; - 64'd400: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80969800; - 64'd408: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65746E69; - 64'd416: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F632D74; - 64'd424: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72656C6C; - 64'd440: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79000000; - 64'd456: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h8A000000; - 64'd480: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692D75; - 64'd496: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h9F000000; - 64'd504, 64'd512, 64'd584, 64'd608, 64'd624, 64'd792, 64'd928: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h02000000; - 64'd520: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6D656D; - 64'd528: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30303030; - 64'd544: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3F000000; - 64'd552: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00007972; - 64'd592: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00636F73; - 64'd632: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h21000000; - 64'd656: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F732D65; - 64'd664: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656C706D; - 64'd696: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30324074; - 64'd712: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0D000000; - 64'd728: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30746E69; - 64'd744, 64'd912: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAE000000; - 64'd760: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h07000000; - 64'd808: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30306340; - 64'd824: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h09000000; - 64'd832: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3631736E; - 64'd880: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hC2000000; - 64'd896: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h69000000; - 64'd936: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h64646123; - 64'd944: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C65632D; - 64'd952: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h657A6973; - 64'd960: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6300736C; - 64'd968: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C626974; - 64'd976: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h006C6564; - 64'd984: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65736162; - 64'd992: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E657571; - 64'd1000: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63697665; - 64'd1008: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72006570; - 64'd1016: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75746174; - 64'd1024: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C766373; - 64'd1032: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D756D6D; - 64'd1040: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6C6300; - 64'd1048: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75716572; - 64'd1056: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692300; - 64'd1064, 64'd1080: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D747075; - 64'd1072: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E690073; - 64'd1088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C6C6F72; - 64'd1096: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h646E6168; - 64'd1104: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65676E61; - 64'd1112: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72726574; - 64'd1120: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7478652D; - 64'd1128: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65720064; - 64'd1136: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00746669; - default: CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705 or - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 or - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2) - begin - case (byte_addr__h705) - 64'd0: data64__h987 = 64'h0202859300000297; - 64'd8: data64__h987 = 64'h0182B283F1402573; - default: data64__h987 = - { CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_module_ready$EN) - rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_module_ready = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - begin - v__h808 = $stime; - #0; - end - v__h802 = v__h808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", - v__h802); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - begin - v__h8928 = $stime; - #0; - end - v__h8922 = v__h8928 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", - v__h8922); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h9221 = $stime; - #0; - end - v__h9215 = v__h9221 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9215, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h9331 = $stime; - #0; - end - v__h9325 = v__h9331 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9325, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkBoot_ROM - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCPU.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCPU.v deleted file mode 100644 index 82110d98..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCPU.v +++ /dev/null @@ -1,7287 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// hart0_server_reset_response_get O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_set_verbosity O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// hart0_server_reset_request_put I 1 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// nmi_req_set_not_clear I 1 -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// EN_hart0_server_reset_request_put I 1 -// EN_set_verbosity I 1 -// EN_hart0_server_reset_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// imem_master_arready, -// dmem_master_awready, -// dmem_master_wready) -> imem_master_rready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready, -// dmem_master_arready) -> dmem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCPU(CLK, - RST_N, - - hart0_server_reset_request_put, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - nmi_req_set_not_clear, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity); - input CLK; - input RST_N; - - // action method hart0_server_reset_request_put - input hart0_server_reset_request_put; - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // actionvalue method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, - RDY_set_verbosity, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - hart0_server_reset_response_get, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid; - - // register cfg_logdelay - reg [63 : 0] cfg_logdelay; - wire [63 : 0] cfg_logdelay$D_IN; - wire cfg_logdelay$EN; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register imem_rg_f3 - reg [2 : 0] imem_rg_f3; - wire [2 : 0] imem_rg_f3$D_IN; - wire imem_rg_f3$EN; - - // register imem_rg_instr_15_0 - reg [15 : 0] imem_rg_instr_15_0; - wire [15 : 0] imem_rg_instr_15_0$D_IN; - wire imem_rg_instr_15_0$EN; - - // register imem_rg_mstatus_MXR - reg imem_rg_mstatus_MXR; - wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN; - - // register imem_rg_pc - reg [63 : 0] imem_rg_pc; - reg [63 : 0] imem_rg_pc$D_IN; - wire imem_rg_pc$EN; - - // register imem_rg_priv - reg [1 : 0] imem_rg_priv; - wire [1 : 0] imem_rg_priv$D_IN; - wire imem_rg_priv$EN; - - // register imem_rg_satp - reg [63 : 0] imem_rg_satp; - wire [63 : 0] imem_rg_satp$D_IN; - wire imem_rg_satp$EN; - - // register imem_rg_sstatus_SUM - reg imem_rg_sstatus_SUM; - wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN; - - // register imem_rg_tval - reg [63 : 0] imem_rg_tval; - reg [63 : 0] imem_rg_tval$D_IN; - wire imem_rg_tval$EN; - - // register rg_cur_priv - reg [1 : 0] rg_cur_priv; - reg [1 : 0] rg_cur_priv$D_IN; - wire rg_cur_priv$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_next_pc - reg [63 : 0] rg_next_pc; - reg [63 : 0] rg_next_pc$D_IN; - wire rg_next_pc$EN; - - // register rg_run_on_reset - reg rg_run_on_reset; - wire rg_run_on_reset$D_IN, rg_run_on_reset$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_start_CPI_cycles - reg [63 : 0] rg_start_CPI_cycles; - wire [63 : 0] rg_start_CPI_cycles$D_IN; - wire rg_start_CPI_cycles$EN; - - // register rg_start_CPI_instrs - reg [63 : 0] rg_start_CPI_instrs; - wire [63 : 0] rg_start_CPI_instrs$D_IN; - wire rg_start_CPI_instrs$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register stage1_rg_full - reg stage1_rg_full; - reg stage1_rg_full$D_IN; - wire stage1_rg_full$EN; - - // register stage2_rg_full - reg stage2_rg_full; - reg stage2_rg_full$D_IN; - wire stage2_rg_full$EN; - - // register stage2_rg_resetting - reg stage2_rg_resetting; - wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN; - - // register stage2_rg_stage2 - reg [365 : 0] stage2_rg_stage2; - wire [365 : 0] stage2_rg_stage2$D_IN; - wire stage2_rg_stage2$EN; - - // register stage3_rg_full - reg stage3_rg_full; - reg stage3_rg_full$D_IN; - wire stage3_rg_full$EN; - - // register stage3_rg_stage3 - reg [174 : 0] stage3_rg_stage3; - wire [174 : 0] stage3_rg_stage3$D_IN; - wire stage3_rg_stage3$EN; - - // ports of submodule csr_regfile - reg [63 : 0] csr_regfile$csr_trap_actions_xtval; - reg [3 : 0] csr_regfile$csr_trap_actions_exc_code; - reg [1 : 0] csr_regfile$csr_ret_actions_from_priv; - wire [193 : 0] csr_regfile$csr_trap_actions; - wire [129 : 0] csr_regfile$csr_ret_actions; - wire [64 : 0] csr_regfile$read_csr; - wire [63 : 0] csr_regfile$csr_trap_actions_pc, - csr_regfile$mav_csr_write_word, - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - csr_regfile$read_mstatus, - csr_regfile$read_satp, - csr_regfile$read_sstatus; - wire [27 : 0] csr_regfile$read_misa; - wire [11 : 0] csr_regfile$access_permitted_1_csr_addr, - csr_regfile$access_permitted_2_csr_addr, - csr_regfile$csr_counter_read_fault_csr_addr, - csr_regfile$mav_csr_write_csr_addr, - csr_regfile$mav_read_csr_csr_addr, - csr_regfile$read_csr_csr_addr, - csr_regfile$read_csr_port2_csr_addr; - wire [4 : 0] csr_regfile$interrupt_pending, - csr_regfile$ma_update_fcsr_fflags_flags; - wire [2 : 0] csr_regfile$read_frm; - wire [1 : 0] csr_regfile$access_permitted_1_priv, - csr_regfile$access_permitted_2_priv, - csr_regfile$csr_counter_read_fault_priv, - csr_regfile$csr_trap_actions_from_priv, - csr_regfile$interrupt_pending_cur_priv, - csr_regfile$ma_update_mstatus_fs_fs; - wire csr_regfile$EN_csr_minstret_incr, - csr_regfile$EN_csr_ret_actions, - csr_regfile$EN_csr_trap_actions, - csr_regfile$EN_debug, - csr_regfile$EN_ma_update_fcsr_fflags, - csr_regfile$EN_ma_update_mstatus_fs, - csr_regfile$EN_mav_csr_write, - csr_regfile$EN_mav_read_csr, - csr_regfile$EN_server_reset_request_put, - csr_regfile$EN_server_reset_response_get, - csr_regfile$RDY_server_reset_request_put, - csr_regfile$RDY_server_reset_response_get, - csr_regfile$access_permitted_1, - csr_regfile$access_permitted_1_read_not_write, - csr_regfile$access_permitted_2, - csr_regfile$access_permitted_2_read_not_write, - csr_regfile$csr_trap_actions_interrupt, - csr_regfile$csr_trap_actions_nmi, - csr_regfile$m_external_interrupt_req_set_not_clear, - csr_regfile$nmi_pending, - csr_regfile$nmi_req_set_not_clear, - csr_regfile$s_external_interrupt_req_set_not_clear, - csr_regfile$software_interrupt_req_set_not_clear, - csr_regfile$timer_interrupt_req_set_not_clear, - csr_regfile$wfi_resume; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fpr_regfile - wire [63 : 0] fpr_regfile$read_rs1, - fpr_regfile$read_rs2, - fpr_regfile$read_rs3, - fpr_regfile$write_rd_rd_val; - wire [4 : 0] fpr_regfile$read_rs1_port2_rs1, - fpr_regfile$read_rs1_rs1, - fpr_regfile$read_rs2_rs2, - fpr_regfile$read_rs3_rs3, - fpr_regfile$write_rd_rd; - wire fpr_regfile$EN_server_reset_request_put, - fpr_regfile$EN_server_reset_response_get, - fpr_regfile$EN_write_rd, - fpr_regfile$RDY_server_reset_request_put, - fpr_regfile$RDY_server_reset_response_get; - - // ports of submodule gpr_regfile - wire [63 : 0] gpr_regfile$read_rs1, - gpr_regfile$read_rs2, - gpr_regfile$write_rd_rd_val; - wire [4 : 0] gpr_regfile$read_rs1_port2_rs1, - gpr_regfile$read_rs1_rs1, - gpr_regfile$read_rs2_rs2, - gpr_regfile$write_rd_rd; - wire gpr_regfile$EN_server_reset_request_put, - gpr_regfile$EN_server_reset_response_get, - gpr_regfile$EN_write_rd, - gpr_regfile$RDY_server_reset_request_put, - gpr_regfile$RDY_server_reset_response_get; - - // ports of submodule near_mem - reg [63 : 0] near_mem$imem_req_addr; - reg [1 : 0] near_mem$dmem_req_op; - reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM; - wire [63 : 0] near_mem$dmem_master_araddr, - near_mem$dmem_master_awaddr, - near_mem$dmem_master_rdata, - near_mem$dmem_master_wdata, - near_mem$dmem_req_addr, - near_mem$dmem_req_satp, - near_mem$dmem_req_store_value, - near_mem$dmem_word64, - near_mem$imem_master_araddr, - near_mem$imem_master_awaddr, - near_mem$imem_master_rdata, - near_mem$imem_master_wdata, - near_mem$imem_pc, - near_mem$imem_req_satp; - wire [31 : 0] near_mem$imem_instr; - wire [7 : 0] near_mem$dmem_master_arlen, - near_mem$dmem_master_awlen, - near_mem$dmem_master_wstrb, - near_mem$imem_master_arlen, - near_mem$imem_master_awlen, - near_mem$imem_master_wstrb, - near_mem$server_fence_request_put; - wire [6 : 0] near_mem$dmem_req_amo_funct7; - wire [3 : 0] near_mem$dmem_exc_code, - near_mem$dmem_master_arcache, - near_mem$dmem_master_arid, - near_mem$dmem_master_arqos, - near_mem$dmem_master_arregion, - near_mem$dmem_master_awcache, - near_mem$dmem_master_awid, - near_mem$dmem_master_awqos, - near_mem$dmem_master_awregion, - near_mem$dmem_master_bid, - near_mem$dmem_master_rid, - near_mem$dmem_master_wid, - near_mem$imem_exc_code, - near_mem$imem_master_arcache, - near_mem$imem_master_arid, - near_mem$imem_master_arqos, - near_mem$imem_master_arregion, - near_mem$imem_master_awcache, - near_mem$imem_master_awid, - near_mem$imem_master_awqos, - near_mem$imem_master_awregion, - near_mem$imem_master_bid, - near_mem$imem_master_rid, - near_mem$imem_master_wid; - wire [2 : 0] near_mem$dmem_master_arprot, - near_mem$dmem_master_arsize, - near_mem$dmem_master_awprot, - near_mem$dmem_master_awsize, - near_mem$dmem_req_f3, - near_mem$imem_master_arprot, - near_mem$imem_master_arsize, - near_mem$imem_master_awprot, - near_mem$imem_master_awsize, - near_mem$imem_req_f3; - wire [1 : 0] near_mem$dmem_master_arburst, - near_mem$dmem_master_awburst, - near_mem$dmem_master_bresp, - near_mem$dmem_master_rresp, - near_mem$dmem_req_priv, - near_mem$imem_master_arburst, - near_mem$imem_master_awburst, - near_mem$imem_master_bresp, - near_mem$imem_master_rresp, - near_mem$imem_req_priv; - wire near_mem$EN_dmem_req, - near_mem$EN_imem_req, - near_mem$EN_server_fence_i_request_put, - near_mem$EN_server_fence_i_response_get, - near_mem$EN_server_fence_request_put, - near_mem$EN_server_fence_response_get, - near_mem$EN_server_reset_request_put, - near_mem$EN_server_reset_response_get, - near_mem$EN_sfence_vma, - near_mem$RDY_server_fence_i_request_put, - near_mem$RDY_server_fence_i_response_get, - near_mem$RDY_server_fence_request_put, - near_mem$RDY_server_fence_response_get, - near_mem$RDY_server_reset_request_put, - near_mem$RDY_server_reset_response_get, - near_mem$dmem_exc, - near_mem$dmem_master_arlock, - near_mem$dmem_master_arready, - near_mem$dmem_master_arvalid, - near_mem$dmem_master_awlock, - near_mem$dmem_master_awready, - near_mem$dmem_master_awvalid, - near_mem$dmem_master_bready, - near_mem$dmem_master_bvalid, - near_mem$dmem_master_rlast, - near_mem$dmem_master_rready, - near_mem$dmem_master_rvalid, - near_mem$dmem_master_wlast, - near_mem$dmem_master_wready, - near_mem$dmem_master_wvalid, - near_mem$dmem_req_mstatus_MXR, - near_mem$dmem_req_sstatus_SUM, - near_mem$dmem_valid, - near_mem$imem_exc, - near_mem$imem_is_i32_not_i16, - near_mem$imem_master_arlock, - near_mem$imem_master_arready, - near_mem$imem_master_arvalid, - near_mem$imem_master_awlock, - near_mem$imem_master_awready, - near_mem$imem_master_awvalid, - near_mem$imem_master_bready, - near_mem$imem_master_bvalid, - near_mem$imem_master_rlast, - near_mem$imem_master_rready, - near_mem$imem_master_rvalid, - near_mem$imem_master_wlast, - near_mem$imem_master_wready, - near_mem$imem_master_wvalid, - near_mem$imem_valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_pc_reset_value; - - // ports of submodule stage1_f_reset_reqs - wire stage1_f_reset_reqs$CLR, - stage1_f_reset_reqs$DEQ, - stage1_f_reset_reqs$EMPTY_N, - stage1_f_reset_reqs$ENQ, - stage1_f_reset_reqs$FULL_N; - - // ports of submodule stage1_f_reset_rsps - wire stage1_f_reset_rsps$CLR, - stage1_f_reset_rsps$DEQ, - stage1_f_reset_rsps$EMPTY_N, - stage1_f_reset_rsps$ENQ, - stage1_f_reset_rsps$FULL_N; - - // ports of submodule stage2_f_reset_reqs - wire stage2_f_reset_reqs$CLR, - stage2_f_reset_reqs$DEQ, - stage2_f_reset_reqs$EMPTY_N, - stage2_f_reset_reqs$ENQ, - stage2_f_reset_reqs$FULL_N; - - // ports of submodule stage2_f_reset_rsps - wire stage2_f_reset_rsps$CLR, - stage2_f_reset_rsps$DEQ, - stage2_f_reset_rsps$EMPTY_N, - stage2_f_reset_rsps$ENQ, - stage2_f_reset_rsps$FULL_N; - - // ports of submodule stage2_fbox - wire [63 : 0] stage2_fbox$req_v1, - stage2_fbox$req_v2, - stage2_fbox$req_v3, - stage2_fbox$word_fst; - wire [6 : 0] stage2_fbox$req_f7, stage2_fbox$req_opcode; - wire [4 : 0] stage2_fbox$req_rs2, stage2_fbox$word_snd; - wire [2 : 0] stage2_fbox$req_rm; - wire stage2_fbox$EN_req, - stage2_fbox$EN_server_reset_request_put, - stage2_fbox$EN_server_reset_response_get, - stage2_fbox$RDY_server_reset_request_put, - stage2_fbox$RDY_server_reset_response_get, - stage2_fbox$valid; - - // ports of submodule stage2_mbox - wire [63 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word; - wire [3 : 0] stage2_mbox$set_verbosity_verbosity; - wire [2 : 0] stage2_mbox$req_f3; - wire stage2_mbox$EN_req, - stage2_mbox$EN_req_reset, - stage2_mbox$EN_rsp_reset, - stage2_mbox$EN_set_verbosity, - stage2_mbox$req_is_OP_not_OP_32, - stage2_mbox$valid; - - // ports of submodule stage3_f_reset_reqs - wire stage3_f_reset_reqs$CLR, - stage3_f_reset_reqs$DEQ, - stage3_f_reset_reqs$EMPTY_N, - stage3_f_reset_reqs$ENQ, - stage3_f_reset_reqs$FULL_N; - - // ports of submodule stage3_f_reset_rsps - wire stage3_f_reset_rsps$CLR, - stage3_f_reset_rsps$DEQ, - stage3_f_reset_rsps$EMPTY_N, - stage3_f_reset_rsps$ENQ, - stage3_f_reset_rsps$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_imem_rl_assert_fail, - CAN_FIRE_RL_imem_rl_fetch_next_32b, - CAN_FIRE_RL_rl_WFI_resume, - CAN_FIRE_RL_rl_finish_FENCE, - CAN_FIRE_RL_rl_finish_FENCE_I, - CAN_FIRE_RL_rl_finish_SFENCE_VMA, - CAN_FIRE_RL_rl_pipe, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_RL_rl_reset_from_WFI, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_show_pipe, - CAN_FIRE_RL_rl_stage1_CSRR_S_or_C, - CAN_FIRE_RL_rl_stage1_CSRR_W, - CAN_FIRE_RL_rl_stage1_FENCE, - CAN_FIRE_RL_rl_stage1_FENCE_I, - CAN_FIRE_RL_rl_stage1_SFENCE_VMA, - CAN_FIRE_RL_rl_stage1_WFI, - CAN_FIRE_RL_rl_stage1_interrupt, - CAN_FIRE_RL_rl_stage1_restart_after_csrrx, - CAN_FIRE_RL_rl_stage1_trap, - CAN_FIRE_RL_rl_stage1_xRET, - CAN_FIRE_RL_rl_stage2_nonpipe, - CAN_FIRE_RL_rl_trap_fetch, - CAN_FIRE_RL_stage1_rl_reset, - CAN_FIRE_RL_stage2_rl_reset_begin, - CAN_FIRE_RL_stage2_rl_reset_end, - CAN_FIRE_RL_stage3_rl_reset, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_set_verbosity, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_imem_rl_assert_fail, - WILL_FIRE_RL_imem_rl_fetch_next_32b, - WILL_FIRE_RL_rl_WFI_resume, - WILL_FIRE_RL_rl_finish_FENCE, - WILL_FIRE_RL_rl_finish_FENCE_I, - WILL_FIRE_RL_rl_finish_SFENCE_VMA, - WILL_FIRE_RL_rl_pipe, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_RL_rl_reset_from_WFI, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_show_pipe, - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C, - WILL_FIRE_RL_rl_stage1_CSRR_W, - WILL_FIRE_RL_rl_stage1_FENCE, - WILL_FIRE_RL_rl_stage1_FENCE_I, - WILL_FIRE_RL_rl_stage1_SFENCE_VMA, - WILL_FIRE_RL_rl_stage1_WFI, - WILL_FIRE_RL_rl_stage1_interrupt, - WILL_FIRE_RL_rl_stage1_restart_after_csrrx, - WILL_FIRE_RL_rl_stage1_trap, - WILL_FIRE_RL_rl_stage1_xRET, - WILL_FIRE_RL_rl_stage2_nonpipe, - WILL_FIRE_RL_rl_trap_fetch, - WILL_FIRE_RL_stage1_rl_reset, - WILL_FIRE_RL_stage2_rl_reset_begin, - WILL_FIRE_RL_stage2_rl_reset_end, - WILL_FIRE_RL_stage3_rl_reset, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_set_verbosity, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - reg [63 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2; - wire [63 : 0] MUX_near_mem$imem_req_2__VAL_1, - MUX_near_mem$imem_req_2__VAL_2, - MUX_near_mem$imem_req_2__VAL_5; - wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1, - MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_3; - wire MUX_csr_regfile$mav_csr_write_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_2, - MUX_gpr_regfile$write_rd_1__SEL_3, - MUX_imem_rg_f3$write_1__SEL_1, - MUX_imem_rg_f3$write_1__SEL_2, - MUX_imem_rg_mstatus_MXR$write_1__SEL_4, - MUX_imem_rg_pc$write_1__SEL_4, - MUX_near_mem$imem_req_1__SEL_6, - MUX_rg_cur_priv$write_1__SEL_1, - MUX_rg_mstatus_MXR$write_1__SEL_1, - MUX_rg_next_pc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_11, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_4, - MUX_rg_state$write_1__SEL_6, - MUX_rg_state$write_1__SEL_7, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9, - MUX_stage1_rg_full$write_1__VAL_2, - MUX_stage2_rg_full$write_1__VAL_2; - - // remaining internal signals - reg [63 : 0] CASE_theResult__607_BITS_6_TO_0_0b100011_alu_o_ETC__q23, - CASE_theResult__607_BITS_6_TO_0_0b1100111_data_ETC__q22, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557, - _theResult_____1_fst__h16245, - alu_outputs___1_val1__h15039, - rs1_val__h23782, - value__h6429, - value__h6490, - x_out_bypass_rd_val__h6725, - x_out_data_to_stage2_addr__h14648, - x_out_data_to_stage2_val1__h14649, - x_out_data_to_stage3_rd_val__h6250, - x_out_fbypass_rd_val__h6874; - reg [4 : 0] x_out_bypass_rd__h6724, - x_out_data_to_stage2_rd__h14647, - x_out_data_to_stage3_fpr_flags__h6249, - x_out_data_to_stage3_rd__h6246, - x_out_fbypass_rd__h6873; - reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q15, - CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17, - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18, - CASE_theResult__607_BITS_31_TO_20_0b0_CASE_rg__ETC__q16, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1260, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1285, - alu_outputs_exc_code__h15680, - x_out_trap_info_exc_code__h6466; - reg [2 : 0] CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373; - reg [1 : 0] CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1, - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2, - CASE_stage2_rg_stage2_BITS_267_TO_265_1_IF_NOT_ETC__q3; - reg CASE_theResult__607_BITS_6_TO_0_0b1000011_NOT__ETC__q11, - CASE_theResult__607_BITS_6_TO_0_0b1000011_theR_ETC__q13, - CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12, - CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697, - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153, - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163, - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198, - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d232; - wire [127 : 0] csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d2005; - wire [63 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1558, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1559, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1576, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1432, - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1952, - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1441, - _theResult_____1_fst__h16238, - _theResult_____1_fst__h16273, - _theResult_____1_fst_rd_val__h6703, - _theResult_____1_snd_fst_rd_val__h6859, - _theResult_____2_fst_rd_val__h6700, - _theResult_____2_snd_rd_val__h6856, - _theResult____h28496, - _theResult___fst__h16363, - _theResult___fst__h16370, - _theResult___fst__h16490, - _theResult___fst_rd_val__h6714, - _theResult___snd__h18728, - _theResult___snd_rd_val__h6865, - alu_outputs___1_addr__h14775, - alu_outputs___1_addr__h14799, - alu_outputs___1_addr__h14828, - alu_outputs___1_addr__h15117, - alu_outputs___1_addr__h15141, - alu_outputs___1_val1__h14946, - alu_outputs___1_val1__h14987, - alu_outputs___1_val1__h15013, - alu_outputs___1_val1__h15058, - alu_outputs___1_val1__h15077, - alu_outputs___1_val1__h15428, - alu_outputs___1_val1__h15452, - alu_outputs___1_val1__h15653, - alu_outputs___1_val2__h15143, - branch_target__h14754, - cpi__h28498, - cpifrac__h28499, - data_to_stage2_addr__h14637, - data_to_stage3_rd_val__h6144, - delta_CPI_cycles__h28494, - delta_CPI_instrs___1__h28531, - delta_CPI_instrs__h28495, - fall_through_pc__h14598, - frs1_val_bypassed__h4626, - frs2_val_bypassed__h4631, - next_pc___1__h18221, - next_pc__h18219, - rd_val___1__h16226, - rd_val___1__h16234, - rd_val___1__h16241, - rd_val___1__h16248, - rd_val___1__h16255, - rd_val___1__h16262, - rd_val___1__h18759, - rd_val___1__h18790, - rd_val___1__h18844, - rd_val___1__h18873, - rd_val___1__h18927, - rd_val___1__h18975, - rd_val___1__h18981, - rd_val___1__h19026, - rd_val__h14531, - rd_val__h14574, - rd_val__h18622, - rd_val__h18674, - rd_val__h18696, - rd_val__h19313, - rd_val__h19369, - rd_val__h19422, - rs1_val__h23289, - rs1_val_bypassed__h4615, - rs2_val_bypassed__h4621, - trap_info_tval__h18051, - val__h14533, - val__h14576, - value__h18109, - x__h28497, - x_out_data_to_stage2_val2__h14650, - x_out_data_to_stage2_val3__h14651, - x_out_next_pc__h14611, - y__h24086; - wire [31 : 0] IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d599, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d601, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d603, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d604, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d605, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d607, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d608, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d609, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d611, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d613, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d614, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d616, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d617, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d618, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d619, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d620, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d621, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d622, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d623, - _theResult____h4607, - _theResult___fst__h7200, - _theResult___fst__h7228, - alu_outputs___1_addr5117_BITS_31_TO_0__q21, - instr___1__h7021, - instr__h10146, - instr__h10318, - instr__h10487, - instr__h10676, - instr__h10865, - instr__h10982, - instr__h11160, - instr__h11279, - instr__h11374, - instr__h11510, - instr__h11646, - instr__h11782, - instr__h11920, - instr__h12058, - instr__h12216, - instr__h12312, - instr__h12465, - instr__h12664, - instr__h12815, - instr__h13854, - instr__h14007, - instr__h14206, - instr__h14357, - instr__h4605, - instr__h7300, - instr__h7445, - instr__h7637, - instr__h7832, - instr__h8061, - instr__h8515, - instr__h8631, - instr__h8696, - instr__h9013, - instr__h9351, - instr__h9535, - instr__h9664, - instr__h9891, - instr_out___1__h7170, - instr_out___1__h7202, - instr_out___1__h7230, - rs1_val_bypassed615_BITS_31_TO_0_MINUS_rs2_val_ETC__q10, - rs1_val_bypassed615_BITS_31_TO_0_PLUS_rs2_val__ETC__q9, - rs1_val_bypassed615_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8, - rs1_val_bypassed615_BITS_31_TO_0__q7, - tmp__h18872, - v32__h15047, - x__h18793, - x__h18847, - x__h18984, - x__h19029, - x_out_data_to_stage2_instr__h14645; - wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401, - theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q5; - wire [19 : 0] imm20__h9403; - wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426, - theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q4; - wire [11 : 0] imm12__h10159, - imm12__h10355, - imm12__h10692, - imm12__h12313, - imm12__h12665, - imm12__h7301, - imm12__h7638, - imm12__h9275, - imm12__h9944, - offset__h8008, - theResult__607_BITS_31_TO_20__q20, - theResult__607_BITS_31_TO_25_CONCAT_theResult__ETC__q6; - wire [9 : 0] funct10__h15025, nzimm10__h10157, nzimm10__h9942; - wire [8 : 0] offset__h12227, offset__h8640; - wire [7 : 0] offset__h12599, offset__h7071; - wire [6 : 0] offset__h7580; - wire [5 : 0] imm6__h9273, shamt__h14931; - wire [4 : 0] offset_BITS_4_TO_0___h12940, - offset_BITS_4_TO_0___h7569, - offset_BITS_4_TO_0___h8000, - rd__h7640, - rs1__h7639; - wire [3 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1220, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1224, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1262, - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1214, - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1270, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287, - IF_rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7__ETC___d1258, - alu_outputs___1_exc_code__h15424, - cur_verbosity__h3134, - x_out_trap_info_exc_code__h18054; - wire [2 : 0] rm__h15556, x_out_data_to_stage2_rounding_mode__h14653; - wire [1 : 0] IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d258, - IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d284, - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289, - IF_near_mem_dmem_valid__25_AND_NOT_near_mem_dm_ETC___d256, - IF_near_mem_dmem_valid__25_THEN_IF_near_mem_dm_ETC___d128, - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132, - IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130, - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137, - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265, - sxl__h5045, - uxl__h5046; - wire IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1750, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1043, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1050, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1235, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d2002, - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627, - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629, - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d733, - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1824, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1895, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1897, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1900, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1914, - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1190, - NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1353, - NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1403, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1760, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1771, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1779, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632, - _0_OR_0_OR_near_mem_imem_exc__48_OR_IF_IF_NOT_n_ETC___d1893, - csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1753, - csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1758, - csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1764, - csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d411, - csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d417, - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d1000, - fpr_regfile_RDY_server_reset_request_put__697__ETC___d1709, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1603, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1606, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1609, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1612, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1615, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1618, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1621, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1624, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1627, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1630, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1633, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1636, - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d639, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d641, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1749, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647, - rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7_EQ__ETC___d1256, - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917, - rg_state_6_EQ_3_766_AND_stage3_rg_full_6_OR_NO_ETC___d1785, - stage2_f_reset_rsps_i_notEmpty__720_AND_stage3_ETC___d1729, - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d672, - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d680; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // actionvalue method hart0_server_reset_response_get - assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ; - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = near_mem$imem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = near_mem$imem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = near_mem$imem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = near_mem$imem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = near_mem$imem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = near_mem$imem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = near_mem$imem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = near_mem$imem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = near_mem$imem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = near_mem$imem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = near_mem$imem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = near_mem$imem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = near_mem$imem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = near_mem$imem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = near_mem$imem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = near_mem$imem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = near_mem$imem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = near_mem$imem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = near_mem$imem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = near_mem$imem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = near_mem$imem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = near_mem$imem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = near_mem$imem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = near_mem$imem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = near_mem$imem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = near_mem$imem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = near_mem$imem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = near_mem$imem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = near_mem$imem_master_rready ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = near_mem$dmem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = near_mem$dmem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = near_mem$dmem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = near_mem$dmem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = near_mem$dmem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = near_mem$dmem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = near_mem$dmem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = near_mem$dmem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = near_mem$dmem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = near_mem$dmem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = near_mem$dmem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = near_mem$dmem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = near_mem$dmem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = near_mem$dmem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = near_mem$dmem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = near_mem$dmem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = near_mem$dmem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = near_mem$dmem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = near_mem$dmem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = near_mem$dmem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = near_mem$dmem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = near_mem$dmem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = near_mem$dmem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = near_mem$dmem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = near_mem$dmem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = near_mem$dmem_master_rready ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // submodule csr_regfile - mkCSR_RegFile csr_regfile(.CLK(CLK), - .RST_N(RST_N), - .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr), - .access_permitted_1_priv(csr_regfile$access_permitted_1_priv), - .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write), - .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr), - .access_permitted_2_priv(csr_regfile$access_permitted_2_priv), - .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write), - .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr), - .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv), - .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv), - .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code), - .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv), - .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt), - .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi), - .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc), - .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval), - .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv), - .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear), - .ma_update_fcsr_fflags_flags(csr_regfile$ma_update_fcsr_fflags_flags), - .ma_update_mstatus_fs_fs(csr_regfile$ma_update_mstatus_fs_fs), - .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr), - .mav_csr_write_word(csr_regfile$mav_csr_write_word), - .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr), - .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear), - .read_csr_csr_addr(csr_regfile$read_csr_csr_addr), - .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr), - .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear), - .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear), - .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get), - .EN_mav_read_csr(csr_regfile$EN_mav_read_csr), - .EN_mav_csr_write(csr_regfile$EN_mav_csr_write), - .EN_ma_update_fcsr_fflags(csr_regfile$EN_ma_update_fcsr_fflags), - .EN_ma_update_mstatus_fs(csr_regfile$EN_ma_update_mstatus_fs), - .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions), - .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions), - .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr), - .EN_debug(csr_regfile$EN_debug), - .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get), - .read_csr(csr_regfile$read_csr), - .read_csr_port2(), - .mav_read_csr(), - .mav_csr_write(), - .read_frm(csr_regfile$read_frm), - .read_misa(csr_regfile$read_misa), - .read_mstatus(csr_regfile$read_mstatus), - .read_sstatus(csr_regfile$read_sstatus), - .read_ustatus(), - .read_satp(csr_regfile$read_satp), - .csr_trap_actions(csr_regfile$csr_trap_actions), - .RDY_csr_trap_actions(), - .csr_ret_actions(csr_regfile$csr_ret_actions), - .RDY_csr_ret_actions(), - .read_csr_minstret(csr_regfile$read_csr_minstret), - .read_csr_mcycle(csr_regfile$read_csr_mcycle), - .read_csr_mtime(), - .access_permitted_1(csr_regfile$access_permitted_1), - .access_permitted_2(csr_regfile$access_permitted_2), - .csr_counter_read_fault(), - .csr_mip_read(), - .interrupt_pending(csr_regfile$interrupt_pending), - .wfi_resume(csr_regfile$wfi_resume), - .nmi_pending(csr_regfile$nmi_pending), - .RDY_debug()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fpr_regfile - mkFPR_RegFile fpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(fpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(fpr_regfile$read_rs1_rs1), - .read_rs2_rs2(fpr_regfile$read_rs2_rs2), - .read_rs3_rs3(fpr_regfile$read_rs3_rs3), - .write_rd_rd(fpr_regfile$write_rd_rd), - .write_rd_rd_val(fpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(fpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(fpr_regfile$EN_server_reset_response_get), - .EN_write_rd(fpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(fpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fpr_regfile$RDY_server_reset_response_get), - .read_rs1(fpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(fpr_regfile$read_rs2), - .read_rs3(fpr_regfile$read_rs3)); - - // submodule gpr_regfile - mkGPR_RegFile gpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(gpr_regfile$read_rs1_rs1), - .read_rs2_rs2(gpr_regfile$read_rs2_rs2), - .write_rd_rd(gpr_regfile$write_rd_rd), - .write_rd_rd_val(gpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get), - .EN_write_rd(gpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get), - .read_rs1(gpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(gpr_regfile$read_rs2)); - - // submodule near_mem - mkNear_Mem near_mem(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(near_mem$dmem_master_arready), - .dmem_master_awready(near_mem$dmem_master_awready), - .dmem_master_bid(near_mem$dmem_master_bid), - .dmem_master_bresp(near_mem$dmem_master_bresp), - .dmem_master_bvalid(near_mem$dmem_master_bvalid), - .dmem_master_rdata(near_mem$dmem_master_rdata), - .dmem_master_rid(near_mem$dmem_master_rid), - .dmem_master_rlast(near_mem$dmem_master_rlast), - .dmem_master_rresp(near_mem$dmem_master_rresp), - .dmem_master_rvalid(near_mem$dmem_master_rvalid), - .dmem_master_wready(near_mem$dmem_master_wready), - .dmem_req_addr(near_mem$dmem_req_addr), - .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7), - .dmem_req_f3(near_mem$dmem_req_f3), - .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR), - .dmem_req_op(near_mem$dmem_req_op), - .dmem_req_priv(near_mem$dmem_req_priv), - .dmem_req_satp(near_mem$dmem_req_satp), - .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM), - .dmem_req_store_value(near_mem$dmem_req_store_value), - .imem_master_arready(near_mem$imem_master_arready), - .imem_master_awready(near_mem$imem_master_awready), - .imem_master_bid(near_mem$imem_master_bid), - .imem_master_bresp(near_mem$imem_master_bresp), - .imem_master_bvalid(near_mem$imem_master_bvalid), - .imem_master_rdata(near_mem$imem_master_rdata), - .imem_master_rid(near_mem$imem_master_rid), - .imem_master_rlast(near_mem$imem_master_rlast), - .imem_master_rresp(near_mem$imem_master_rresp), - .imem_master_rvalid(near_mem$imem_master_rvalid), - .imem_master_wready(near_mem$imem_master_wready), - .imem_req_addr(near_mem$imem_req_addr), - .imem_req_f3(near_mem$imem_req_f3), - .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR), - .imem_req_priv(near_mem$imem_req_priv), - .imem_req_satp(near_mem$imem_req_satp), - .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM), - .server_fence_request_put(near_mem$server_fence_request_put), - .EN_server_reset_request_put(near_mem$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem$EN_server_reset_response_get), - .EN_imem_req(near_mem$EN_imem_req), - .EN_dmem_req(near_mem$EN_dmem_req), - .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put), - .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get), - .EN_server_fence_request_put(near_mem$EN_server_fence_request_put), - .EN_server_fence_response_get(near_mem$EN_server_fence_response_get), - .EN_sfence_vma(near_mem$EN_sfence_vma), - .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get), - .imem_valid(near_mem$imem_valid), - .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16), - .imem_pc(near_mem$imem_pc), - .imem_instr(near_mem$imem_instr), - .imem_exc(near_mem$imem_exc), - .imem_exc_code(near_mem$imem_exc_code), - .imem_tval(), - .imem_master_awvalid(near_mem$imem_master_awvalid), - .imem_master_awid(near_mem$imem_master_awid), - .imem_master_awaddr(near_mem$imem_master_awaddr), - .imem_master_awlen(near_mem$imem_master_awlen), - .imem_master_awsize(near_mem$imem_master_awsize), - .imem_master_awburst(near_mem$imem_master_awburst), - .imem_master_awlock(near_mem$imem_master_awlock), - .imem_master_awcache(near_mem$imem_master_awcache), - .imem_master_awprot(near_mem$imem_master_awprot), - .imem_master_awqos(near_mem$imem_master_awqos), - .imem_master_awregion(near_mem$imem_master_awregion), - .imem_master_wvalid(near_mem$imem_master_wvalid), - .imem_master_wid(near_mem$imem_master_wid), - .imem_master_wdata(near_mem$imem_master_wdata), - .imem_master_wstrb(near_mem$imem_master_wstrb), - .imem_master_wlast(near_mem$imem_master_wlast), - .imem_master_bready(near_mem$imem_master_bready), - .imem_master_arvalid(near_mem$imem_master_arvalid), - .imem_master_arid(near_mem$imem_master_arid), - .imem_master_araddr(near_mem$imem_master_araddr), - .imem_master_arlen(near_mem$imem_master_arlen), - .imem_master_arsize(near_mem$imem_master_arsize), - .imem_master_arburst(near_mem$imem_master_arburst), - .imem_master_arlock(near_mem$imem_master_arlock), - .imem_master_arcache(near_mem$imem_master_arcache), - .imem_master_arprot(near_mem$imem_master_arprot), - .imem_master_arqos(near_mem$imem_master_arqos), - .imem_master_arregion(near_mem$imem_master_arregion), - .imem_master_rready(near_mem$imem_master_rready), - .dmem_valid(near_mem$dmem_valid), - .dmem_word64(near_mem$dmem_word64), - .dmem_st_amo_val(), - .dmem_exc(near_mem$dmem_exc), - .dmem_exc_code(near_mem$dmem_exc_code), - .dmem_master_awvalid(near_mem$dmem_master_awvalid), - .dmem_master_awid(near_mem$dmem_master_awid), - .dmem_master_awaddr(near_mem$dmem_master_awaddr), - .dmem_master_awlen(near_mem$dmem_master_awlen), - .dmem_master_awsize(near_mem$dmem_master_awsize), - .dmem_master_awburst(near_mem$dmem_master_awburst), - .dmem_master_awlock(near_mem$dmem_master_awlock), - .dmem_master_awcache(near_mem$dmem_master_awcache), - .dmem_master_awprot(near_mem$dmem_master_awprot), - .dmem_master_awqos(near_mem$dmem_master_awqos), - .dmem_master_awregion(near_mem$dmem_master_awregion), - .dmem_master_wvalid(near_mem$dmem_master_wvalid), - .dmem_master_wid(near_mem$dmem_master_wid), - .dmem_master_wdata(near_mem$dmem_master_wdata), - .dmem_master_wstrb(near_mem$dmem_master_wstrb), - .dmem_master_wlast(near_mem$dmem_master_wlast), - .dmem_master_bready(near_mem$dmem_master_bready), - .dmem_master_arvalid(near_mem$dmem_master_arvalid), - .dmem_master_arid(near_mem$dmem_master_arid), - .dmem_master_araddr(near_mem$dmem_master_araddr), - .dmem_master_arlen(near_mem$dmem_master_arlen), - .dmem_master_arsize(near_mem$dmem_master_arsize), - .dmem_master_arburst(near_mem$dmem_master_arburst), - .dmem_master_arlock(near_mem$dmem_master_arlock), - .dmem_master_arcache(near_mem$dmem_master_arcache), - .dmem_master_arprot(near_mem$dmem_master_arprot), - .dmem_master_arqos(near_mem$dmem_master_arqos), - .dmem_master_arregion(near_mem$dmem_master_arregion), - .dmem_master_rready(near_mem$dmem_master_rready), - .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put), - .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get), - .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put), - .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get), - .RDY_sfence_vma()); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(soc_map$m_pc_reset_value), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule stage1_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_reqs$ENQ), - .DEQ(stage1_f_reset_reqs$DEQ), - .CLR(stage1_f_reset_reqs$CLR), - .FULL_N(stage1_f_reset_reqs$FULL_N), - .EMPTY_N(stage1_f_reset_reqs$EMPTY_N)); - - // submodule stage1_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_rsps$ENQ), - .DEQ(stage1_f_reset_rsps$DEQ), - .CLR(stage1_f_reset_rsps$CLR), - .FULL_N(stage1_f_reset_rsps$FULL_N), - .EMPTY_N(stage1_f_reset_rsps$EMPTY_N)); - - // submodule stage2_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_reqs$ENQ), - .DEQ(stage2_f_reset_reqs$DEQ), - .CLR(stage2_f_reset_reqs$CLR), - .FULL_N(stage2_f_reset_reqs$FULL_N), - .EMPTY_N(stage2_f_reset_reqs$EMPTY_N)); - - // submodule stage2_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_rsps$ENQ), - .DEQ(stage2_f_reset_rsps$DEQ), - .CLR(stage2_f_reset_rsps$CLR), - .FULL_N(stage2_f_reset_rsps$FULL_N), - .EMPTY_N(stage2_f_reset_rsps$EMPTY_N)); - - // submodule stage2_fbox - mkFBox_Top stage2_fbox(.CLK(CLK), - .RST_N(RST_N), - .req_f7(stage2_fbox$req_f7), - .req_opcode(stage2_fbox$req_opcode), - .req_rm(stage2_fbox$req_rm), - .req_rs2(stage2_fbox$req_rs2), - .req_v1(stage2_fbox$req_v1), - .req_v2(stage2_fbox$req_v2), - .req_v3(stage2_fbox$req_v3), - .EN_server_reset_request_put(stage2_fbox$EN_server_reset_request_put), - .EN_server_reset_response_get(stage2_fbox$EN_server_reset_response_get), - .EN_req(stage2_fbox$EN_req), - .RDY_server_reset_request_put(stage2_fbox$RDY_server_reset_request_put), - .RDY_server_reset_response_get(stage2_fbox$RDY_server_reset_response_get), - .valid(stage2_fbox$valid), - .word_fst(stage2_fbox$word_fst), - .word_snd(stage2_fbox$word_snd)); - - // submodule stage2_mbox - mkRISCV_MBox stage2_mbox(.CLK(CLK), - .RST_N(RST_N), - .req_f3(stage2_mbox$req_f3), - .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32), - .req_v1(stage2_mbox$req_v1), - .req_v2(stage2_mbox$req_v2), - .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity), - .EN_set_verbosity(stage2_mbox$EN_set_verbosity), - .EN_req_reset(stage2_mbox$EN_req_reset), - .EN_rsp_reset(stage2_mbox$EN_rsp_reset), - .EN_req(stage2_mbox$EN_req), - .RDY_set_verbosity(), - .RDY_req_reset(), - .RDY_rsp_reset(), - .valid(stage2_mbox$valid), - .word(stage2_mbox$word)); - - // submodule stage3_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_reqs$ENQ), - .DEQ(stage3_f_reset_reqs$DEQ), - .CLR(stage3_f_reset_reqs$CLR), - .FULL_N(stage3_f_reset_reqs$FULL_N), - .EMPTY_N(stage3_f_reset_reqs$EMPTY_N)); - - // submodule stage3_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_rsps$ENQ), - .DEQ(stage3_f_reset_rsps$DEQ), - .CLR(stage3_f_reset_rsps$CLR), - .FULL_N(stage3_f_reset_rsps$FULL_N), - .EMPTY_N(stage3_f_reset_rsps$EMPTY_N)); - - // rule RL_rl_show_pipe - assign CAN_FIRE_RL_rl_show_pipe = - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - rg_state != 4'd0 && - rg_state != 4'd1 && - rg_state != 4'd10 ; - assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ; - - // rule RL_rl_stage2_nonpipe - assign CAN_FIRE_RL_rl_stage2_nonpipe = - rg_state == 4'd3 && !stage3_rg_full && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd3 && - (!stage1_rg_full || - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647) ; - assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ; - - // rule RL_rl_stage1_CSRR_W - assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_stage1_CSRR_S_or_C - assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_stage1_restart_after_csrrx - assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx = - CAN_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // rule RL_rl_stage1_xRET - assign CAN_FIRE_RL_rl_stage1_xRET = - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd7 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd8 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd9) ; - assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ; - - // rule RL_rl_stage1_FENCE_I - assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - - // rule RL_rl_finish_FENCE_I - assign CAN_FIRE_RL_rl_finish_FENCE_I = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_i_response_get && - rg_state == 4'd7 ; - assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ; - - // rule RL_rl_stage1_FENCE - assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - - // rule RL_rl_finish_FENCE - assign CAN_FIRE_RL_rl_finish_FENCE = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_response_get && - rg_state == 4'd8 ; - assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ; - - // rule RL_rl_finish_SFENCE_VMA - assign CAN_FIRE_RL_rl_finish_SFENCE_VMA = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_finish_SFENCE_VMA = - CAN_FIRE_RL_rl_finish_SFENCE_VMA ; - - // rule RL_rl_stage1_WFI - assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - - // rule RL_rl_WFI_resume - assign CAN_FIRE_RL_rl_WFI_resume = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd10 && - csr_regfile$wfi_resume ; - assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ; - - // rule RL_rl_reset_from_WFI - assign CAN_FIRE_RL_rl_reset_from_WFI = - rg_state == 4'd10 && f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_4 ; - - // rule RL_rl_stage1_trap - assign CAN_FIRE_RL_rl_stage1_trap = - rg_state == 4'd4 || - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd11 ; - assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ; - - // rule RL_rl_trap_fetch - assign CAN_FIRE_RL_rl_trap_fetch = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd5 ; - assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; - - // rule RL_rl_stage1_interrupt - assign CAN_FIRE_RL_rl_stage1_interrupt = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - rg_state == 4'd3 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1750 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd0 && - !stage3_rg_full ; - assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ; - - // rule RL_imem_rl_assert_fail - assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ; - assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = - gpr_regfile$RDY_server_reset_response_get && - fpr_regfile$RDY_server_reset_response_get && - near_mem$RDY_server_reset_response_get && - csr_regfile$RDY_server_reset_response_get && - stage1_f_reset_rsps$EMPTY_N && - stage2_f_reset_rsps_i_notEmpty__720_AND_stage3_ETC___d1729 && - rg_state == 4'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_pipe - assign CAN_FIRE_RL_rl_pipe = - (csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1764 || - !near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state_6_EQ_3_766_AND_stage3_rg_full_6_OR_NO_ETC___d1785 ; - assign WILL_FIRE_RL_rl_pipe = - CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_rl_stage1_SFENCE_VMA - assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = - gpr_regfile$RDY_server_reset_request_put && - fpr_regfile_RDY_server_reset_request_put__697__ETC___d1709 && - rg_state == 4'd0 ; - assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ; - - // rule RL_imem_rl_fetch_next_32b - assign CAN_FIRE_RL_imem_rl_fetch_next_32b = - near_mem$imem_valid && - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] == 2'b11 ; - assign WILL_FIRE_RL_imem_rl_fetch_next_32b = - CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_stage3_rl_reset - assign CAN_FIRE_RL_stage3_rl_reset = - stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ; - - // rule RL_stage2_rl_reset_end - assign CAN_FIRE_RL_stage2_rl_reset_end = - stage2_fbox$RDY_server_reset_response_get && - stage2_f_reset_rsps$FULL_N && - stage2_rg_resetting ; - assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ; - - // rule RL_stage2_rl_reset_begin - assign CAN_FIRE_RL_stage2_rl_reset_begin = - stage2_fbox$RDY_server_reset_request_put && - stage2_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_stage2_rl_reset_begin = - CAN_FIRE_RL_stage2_rl_reset_begin ; - - // rule RL_stage1_rl_reset - assign CAN_FIRE_RL_stage1_rl_reset = - stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_csr_regfile$mav_csr_write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 ; - assign MUX_gpr_regfile$write_rd_1__SEL_2 = - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - assign MUX_gpr_regfile$write_rd_1__SEL_3 = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - !stage3_rg_stage3[69] ; - assign MUX_imem_rg_f3$write_1__SEL_1 = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ; - assign MUX_imem_rg_f3$write_1__SEL_2 = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 ; - assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_imem_rg_pc$write_1__SEL_4 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_near_mem$imem_req_1__SEL_6 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_rg_cur_priv$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_mstatus_MXR$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_next_pc$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign MUX_rg_state$write_1__SEL_1 = - CAN_FIRE_RL_rl_reset_complete && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_2 = - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd2 ; - assign MUX_rg_state$write_1__SEL_3 = - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd3 ; - assign MUX_rg_state$write_1__SEL_4 = - CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ; - assign MUX_rg_state$write_1__SEL_6 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_rg_state$write_1__SEL_7 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_state$write_1__SEL_8 = - near_mem$RDY_server_fence_i_request_put && - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd5 ; - assign MUX_rg_state$write_1__SEL_9 = - near_mem$RDY_server_fence_request_put && - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd4 ; - assign MUX_rg_state$write_1__SEL_10 = - CAN_FIRE_RL_rl_stage1_SFENCE_VMA && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_11 = - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd10 ; - assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 = - (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ? - csr_regfile$interrupt_pending[3:0] : - 4'd0 ; - always@(x_out_data_to_stage2_instr__h14645 or - csr_regfile$read_csr or - y__h24086 or - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1952) - begin - case (x_out_data_to_stage2_instr__h14645[14:12]) - 3'b010, 3'b110: - MUX_csr_regfile$mav_csr_write_2__VAL_2 = - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1952; - default: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - csr_regfile$read_csr[63:0] & y__h24086; - endcase - end - assign MUX_near_mem$imem_req_2__VAL_1 = - { soc_map$m_pc_reset_value[63:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_2 = - { x_out_next_pc__h14611[63:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[63:2], 2'b0 } ; - assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd3 : 4'd2 ; - assign MUX_rg_state$write_1__VAL_2 = - csr_regfile$access_permitted_1 ? 4'd6 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_3 = - csr_regfile$access_permitted_2 ? 4'd6 : 4'd4 ; - assign MUX_stage1_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1900 || - (csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1758 || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1779) && - stage1_rg_full ; - assign MUX_stage2_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1895 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd2 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd0 ; - - // register cfg_logdelay - assign cfg_logdelay$D_IN = set_verbosity_logdelay ; - assign cfg_logdelay$EN = EN_set_verbosity ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register imem_rg_f3 - assign imem_rg_f3$D_IN = 3'b010 ; - assign imem_rg_f3$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_instr_15_0 - assign imem_rg_instr_15_0$D_IN = near_mem$imem_instr[31:16] ; - assign imem_rg_instr_15_0$EN = CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // register imem_rg_mstatus_MXR - assign imem_rg_mstatus_MXR$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_mstatus[19] : - rg_mstatus_MXR ; - assign imem_rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_pc - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h14611 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_pc$D_IN = soc_map$m_pc_reset_value; - MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h14611; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_pc$D_IN = x_out_next_pc__h14611; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc; - default: imem_rg_pc$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_pc$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - - // register imem_rg_priv - assign imem_rg_priv$D_IN = rg_cur_priv ; - assign imem_rg_priv$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_satp - assign imem_rg_satp$D_IN = csr_regfile$read_satp ; - assign imem_rg_satp$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_sstatus_SUM - assign imem_rg_sstatus_SUM$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_sstatus[18] : - rg_sstatus_SUM ; - assign imem_rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_tval - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h14611 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or - rg_next_pc or - WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h18221) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_tval$D_IN = soc_map$m_pc_reset_value; - MUX_imem_rg_f3$write_1__SEL_2: - imem_rg_tval$D_IN = x_out_next_pc__h14611; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_tval$D_IN = x_out_next_pc__h14611; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - imem_rg_tval$D_IN = next_pc___1__h18221; - default: imem_rg_tval$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_tval$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // register rg_cur_priv - always@(MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or - csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_cur_priv$write_1__SEL_1: - rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[65:64]; - WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11; - default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_cur_priv$EN = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_mstatus[19] : - csr_regfile$csr_trap_actions[85] ; - assign rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_next_pc - always@(MUX_rg_next_pc$write_1__SEL_1 or - x_out_next_pc__h14611 or - MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h14611; - MUX_rg_cur_priv$write_1__SEL_1: - rg_next_pc$D_IN = csr_regfile$csr_trap_actions[193:130]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_next_pc$D_IN = csr_regfile$csr_ret_actions[129:66]; - default: rg_next_pc$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_next_pc$EN = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET ; - - // register rg_run_on_reset - assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ; - assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_sstatus[18] : - csr_regfile$csr_trap_actions[84] ; - assign rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_start_CPI_cycles - assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ; - assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_start_CPI_instrs - assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ; - assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_state - always@(WILL_FIRE_RL_rl_reset_complete or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_stage1_CSRR_W or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or - MUX_rg_state$write_1__VAL_3 or - WILL_FIRE_RL_rl_reset_from_WFI or - WILL_FIRE_RL_rl_reset_start or - MUX_rg_state$write_1__SEL_6 or - MUX_rg_state$write_1__SEL_7 or - WILL_FIRE_RL_rl_stage1_FENCE_I or - WILL_FIRE_RL_rl_stage1_FENCE or - WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_reset_complete: - rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_stage1_CSRR_W: - rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: - rg_state$D_IN = MUX_rg_state$write_1__VAL_3; - WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1; - MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd5; - WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd7; - WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd8; - WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd10; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_complete || - WILL_FIRE_RL_rl_stage1_CSRR_W || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C || - WILL_FIRE_RL_rl_reset_from_WFI || - WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_WFI ; - - // register stage1_rg_full - always@(WILL_FIRE_RL_stage1_rl_reset or - WILL_FIRE_RL_rl_pipe or - MUX_stage1_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or - WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_trap_fetch or - WILL_FIRE_RL_rl_stage1_trap or - WILL_FIRE_RL_rl_WFI_resume or - WILL_FIRE_RL_rl_finish_SFENCE_VMA or - WILL_FIRE_RL_rl_finish_FENCE or - WILL_FIRE_RL_rl_finish_FENCE_I or - WILL_FIRE_RL_rl_stage1_xRET or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_interrupt: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_trap_fetch: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_trap: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I: - stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_xRET: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0; - default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage1_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage1_rl_reset || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register stage2_rg_full - always@(WILL_FIRE_RL_stage2_rl_reset_begin or - WILL_FIRE_RL_rl_pipe or - MUX_stage2_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage2_rl_reset_begin: stage2_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage2_nonpipe: - stage2_rg_full$D_IN = 1'd0; - default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage2_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage2_rl_reset_begin ; - - // register stage2_rg_resetting - assign stage2_rg_resetting$D_IN = WILL_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_rg_resetting$EN = - WILL_FIRE_RL_stage2_rl_reset_end || - WILL_FIRE_RL_stage2_rl_reset_begin ; - - // register stage2_rg_stage2 - assign stage2_rg_stage2$D_IN = - { rg_cur_priv, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373, - x_out_data_to_stage2_rd__h14647, - x_out_data_to_stage2_addr__h14648, - x_out_data_to_stage2_val1__h14649, - x_out_data_to_stage2_val2__h14650, - x_out_data_to_stage2_val3__h14651, - _theResult____h4607[6:0] == 7'b0000111 || - (_theResult____h4607[6:0] == 7'b1010011 || - _theResult____h4607[6:0] == 7'b1000011 || - _theResult____h4607[6:0] == 7'b1000111 || - _theResult____h4607[6:0] == 7'b1001011 || - _theResult____h4607[6:0] == 7'b1001111) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd3) && - _theResult____h4607[31:25] != 7'h71 && - _theResult____h4607[31:25] != 7'h51 && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd3) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd1) && - _theResult____h4607[31:25] != 7'h70 && - _theResult____h4607[31:25] != 7'h50, - x_out_data_to_stage2_rounding_mode__h14653 } ; - assign stage2_rg_stage2$EN = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 ; - - // register stage3_rg_full - always@(WILL_FIRE_RL_stage3_rl_reset or - WILL_FIRE_RL_rl_pipe or - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 or - MUX_imem_rg_f3$write_1__SEL_1) - case (1'b1) - WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage3_rg_full$D_IN = - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2; - MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0; - default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage3_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_stage3_rl_reset ; - - // register stage3_rg_stage3 - assign stage3_rg_stage3$D_IN = - { stage2_rg_stage2[363:268], - stage2_rg_stage2[365:364], - stage2_rg_stage2[267:265] == 3'd0 || - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163, - x_out_data_to_stage3_rd__h6246, - stage2_rg_stage2[267:265] != 3'd0 && - stage2_rg_stage2[267:265] != 3'd1 && - stage2_rg_stage2[267:265] != 3'd4 && - stage2_rg_stage2[267:265] != 3'd2 && - stage2_rg_stage2[267:265] != 3'd3, - stage2_rg_stage2[267:265] != 3'd0 && - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198, - x_out_data_to_stage3_fpr_flags__h6249, - x_out_data_to_stage3_rd_val__h6250 } ; - assign stage3_rg_stage3$EN = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd2 ; - - // submodule csr_regfile - assign csr_regfile$access_permitted_1_csr_addr = - x_out_data_to_stage2_instr__h14645[31:20] ; - assign csr_regfile$access_permitted_1_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ; - assign csr_regfile$access_permitted_2_csr_addr = - x_out_data_to_stage2_instr__h14645[31:20] ; - assign csr_regfile$access_permitted_2_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_2_read_not_write = - rs1_val__h23782 == 64'd0 ; - assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ; - assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ; - always@(IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287) - begin - case (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287) - 4'd7: csr_regfile$csr_ret_actions_from_priv = 2'b11; - 4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b01; - default: csr_regfile$csr_ret_actions_from_priv = 2'b0; - endcase - end - always@(WILL_FIRE_RL_rl_stage1_interrupt or - MUX_csr_regfile$csr_trap_actions_5__VAL_1 or - WILL_FIRE_RL_rl_stage1_trap or - x_out_trap_info_exc_code__h18054 or - WILL_FIRE_RL_rl_stage2_nonpipe or x_out_trap_info_exc_code__h6466) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_exc_code = - MUX_csr_regfile$csr_trap_actions_5__VAL_1; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h18054; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h6466; - default: csr_regfile$csr_trap_actions_exc_code = - 4'b1010 /* unspecified value */ ; - endcase - end - assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ; - assign csr_regfile$csr_trap_actions_interrupt = - WILL_FIRE_RL_rl_stage1_interrupt && !csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_nmi = - WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_pc = - (WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap) ? - imem_rg_pc : - value__h6429 ; - always@(WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_stage1_trap or - value__h18109 or WILL_FIRE_RL_rl_stage2_nonpipe or value__h6490) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_xtval = 64'd0; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_xtval = value__h18109; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_xtval = value__h6490; - default: csr_regfile$csr_trap_actions_xtval = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ; - assign csr_regfile$m_external_interrupt_req_set_not_clear = - m_external_interrupt_req_set_not_clear ; - assign csr_regfile$ma_update_fcsr_fflags_flags = stage3_rg_stage3[68:64] ; - assign csr_regfile$ma_update_mstatus_fs_fs = 2'h3 ; - assign csr_regfile$mav_csr_write_csr_addr = - x_out_data_to_stage2_instr__h14645[31:20] ; - assign csr_regfile$mav_csr_write_word = - MUX_csr_regfile$mav_csr_write_1__SEL_1 ? - rs1_val__h23289 : - MUX_csr_regfile$mav_csr_write_2__VAL_2 ; - assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ; - assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign csr_regfile$read_csr_csr_addr = - x_out_data_to_stage2_instr__h14645[31:20] ; - assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ; - assign csr_regfile$s_external_interrupt_req_set_not_clear = - s_external_interrupt_req_set_not_clear ; - assign csr_regfile$software_interrupt_req_set_not_clear = - software_interrupt_req_set_not_clear ; - assign csr_regfile$timer_interrupt_req_set_not_clear = - timer_interrupt_req_set_not_clear ; - assign csr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign csr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign csr_regfile$EN_mav_read_csr = 1'b0 ; - assign csr_regfile$EN_mav_csr_write = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h14645[19:15] != 5'd0 ; - assign csr_regfile$EN_ma_update_fcsr_fflags = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - stage3_rg_stage3[70] ; - assign csr_regfile$EN_ma_update_mstatus_fs = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - (stage3_rg_stage3[70] || stage3_rg_stage3[69]) ; - assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_1 ; - assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ; - assign csr_regfile$EN_csr_minstret_incr = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd2 || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_stage1_WFI || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign csr_regfile$EN_debug = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = hart0_server_reset_request_put ; - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = - gpr_regfile$RDY_server_reset_request_put && - fpr_regfile_RDY_server_reset_request_put__697__ETC___d1709 && - rg_state == 4'd0 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = rg_run_on_reset ; - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fpr_regfile - assign fpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign fpr_regfile$read_rs1_rs1 = _theResult____h4607[19:15] ; - assign fpr_regfile$read_rs2_rs2 = _theResult____h4607[24:20] ; - assign fpr_regfile$read_rs3_rs3 = _theResult____h4607[31:27] ; - assign fpr_regfile$write_rd_rd = stage3_rg_stage3[75:71] ; - assign fpr_regfile$write_rd_rd_val = stage3_rg_stage3[63:0] ; - assign fpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign fpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign fpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - stage3_rg_stage3[69] ; - - // submodule gpr_regfile - assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign gpr_regfile$read_rs1_rs1 = _theResult____h4607[19:15] ; - assign gpr_regfile$read_rs2_rs2 = _theResult____h4607[24:20] ; - assign gpr_regfile$write_rd_rd = - MUX_gpr_regfile$write_rd_1__SEL_3 ? - stage3_rg_stage3[75:71] : - x_out_data_to_stage2_instr__h14645[11:7] ; - assign gpr_regfile$write_rd_rd_val = - (MUX_csr_regfile$mav_csr_write_1__SEL_1 || - MUX_gpr_regfile$write_rd_1__SEL_2) ? - csr_regfile$read_csr[63:0] : - stage3_rg_stage3[63:0] ; - assign gpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign gpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign gpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - !stage3_rg_stage3[69] ; - - // submodule near_mem - assign near_mem$dmem_master_arready = dmem_master_arready ; - assign near_mem$dmem_master_awready = dmem_master_awready ; - assign near_mem$dmem_master_bid = dmem_master_bid ; - assign near_mem$dmem_master_bresp = dmem_master_bresp ; - assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; - assign near_mem$dmem_master_rdata = dmem_master_rdata ; - assign near_mem$dmem_master_rid = dmem_master_rid ; - assign near_mem$dmem_master_rlast = dmem_master_rlast ; - assign near_mem$dmem_master_rresp = dmem_master_rresp ; - assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; - assign near_mem$dmem_master_wready = dmem_master_wready ; - assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h14648 ; - assign near_mem$dmem_req_amo_funct7 = - x_out_data_to_stage2_val1__h14649[6:0] ; - assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h14645[14:12] ; - assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ; - always@(IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373) - begin - case (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373) - 3'd1: near_mem$dmem_req_op = 2'd0; - 3'd2: near_mem$dmem_req_op = 2'd1; - default: near_mem$dmem_req_op = 2'd2; - endcase - end - assign near_mem$dmem_req_priv = - csr_regfile$read_mstatus[17] ? - csr_regfile$read_mstatus[12:11] : - rg_cur_priv ; - assign near_mem$dmem_req_satp = csr_regfile$read_satp ; - assign near_mem$dmem_req_sstatus_SUM = csr_regfile$read_sstatus[18] ; - assign near_mem$dmem_req_store_value = x_out_data_to_stage2_val2__h14650 ; - assign near_mem$imem_master_arready = imem_master_arready ; - assign near_mem$imem_master_awready = imem_master_awready ; - assign near_mem$imem_master_bid = imem_master_bid ; - assign near_mem$imem_master_bresp = imem_master_bresp ; - assign near_mem$imem_master_bvalid = imem_master_bvalid ; - assign near_mem$imem_master_rdata = imem_master_rdata ; - assign near_mem$imem_master_rid = imem_master_rid ; - assign near_mem$imem_master_rlast = imem_master_rlast ; - assign near_mem$imem_master_rresp = imem_master_rresp ; - assign near_mem$imem_master_rvalid = imem_master_rvalid ; - assign near_mem$imem_master_wready = imem_master_wready ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_near_mem$imem_req_2__VAL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - MUX_near_mem$imem_req_2__VAL_2 or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - next_pc___1__h18221 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_trap_fetch or - MUX_near_mem$imem_req_2__VAL_5 or MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1; - MUX_imem_rg_f3$write_1__SEL_2: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_addr = next_pc___1__h18221; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - default: near_mem$imem_req_addr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_f3 = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_mstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_mstatus_MXR or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_mstatus_MXR) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_mstatus_MXR = imem_rg_mstatus_MXR; - default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_priv = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - MUX_near_mem$imem_req_1__SEL_6) ? - rg_cur_priv : - imem_rg_priv ; - assign near_mem$imem_req_satp = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? - imem_rg_satp : - csr_regfile$read_satp ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_sstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_sstatus_SUM or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_sstatus_SUM) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_sstatus_SUM = csr_regfile$read_sstatus[18]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_sstatus_SUM = imem_rg_sstatus_SUM; - default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$server_fence_request_put = - 8'b10101010 /* unspecified value */ ; - assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ; - assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ; - assign near_mem$EN_imem_req = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_imem_rl_fetch_next_32b || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_dmem_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 && - (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == - 3'd1 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == - 3'd2 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == - 3'd4) ; - assign near_mem$EN_server_fence_i_request_put = - MUX_rg_state$write_1__SEL_8 ; - assign near_mem$EN_server_fence_i_response_get = - CAN_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_9 ; - assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ; - assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_10 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule stage1_f_reset_reqs - assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage1_f_reset_rsps - assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage1_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_f_reset_reqs - assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage2_f_reset_reqs$DEQ = CAN_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage2_f_reset_rsps - assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage2_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_fbox - assign stage2_fbox$req_f7 = x_out_data_to_stage2_instr__h14645[31:25] ; - assign stage2_fbox$req_opcode = x_out_data_to_stage2_instr__h14645[6:0] ; - assign stage2_fbox$req_rm = x_out_data_to_stage2_rounding_mode__h14653 ; - assign stage2_fbox$req_rs2 = x_out_data_to_stage2_instr__h14645[24:20] ; - assign stage2_fbox$req_v1 = x_out_data_to_stage2_val1__h14649 ; - assign stage2_fbox$req_v2 = x_out_data_to_stage2_val2__h14650 ; - assign stage2_fbox$req_v3 = x_out_data_to_stage2_val3__h14651 ; - assign stage2_fbox$EN_server_reset_request_put = - CAN_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_fbox$EN_server_reset_response_get = - CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_fbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == - 3'd5 ; - - // submodule stage2_mbox - assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h14645[14:12] ; - assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4607[3] ; - assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h14649 ; - assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h14650 ; - assign stage2_mbox$set_verbosity_verbosity = 4'h0 ; - assign stage2_mbox$EN_set_verbosity = 1'b0 ; - assign stage2_mbox$EN_req_reset = 1'b0 ; - assign stage2_mbox$EN_rsp_reset = 1'b0 ; - assign stage2_mbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == - 3'd3 ; - - // submodule stage3_f_reset_reqs - assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage3_f_reset_rsps - assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage3_f_reset_rsps$CLR = 1'b0 ; - - // remaining internal signals - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 = - (_theResult____h4607[6:0] == 7'b1100011) ? - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 : - _theResult____h4607[6:0] == 7'b1101111 || - _theResult____h4607[6:0] == 7'b1100111 || - (_theResult____h4607[6:0] != 7'b0110011 || - _theResult____h4607[31:25] != 7'b0000001) && - (_theResult____h4607[6:0] != 7'b0111011 || - _theResult____h4607[31:25] != 7'b0000001) && - (_theResult____h4607[6:0] != 7'b0010011 && - _theResult____h4607[6:0] != 7'b0110011 || - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b101) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026 = - (_theResult____h4607[6:0] == 7'b1100011) ? - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 : - _theResult____h4607[6:0] != 7'b1101111 && - _theResult____h4607[6:0] != 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 = - (_theResult____h4607[6:0] == 7'b1100011) ? - (_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 : - _theResult____h4607[6:0] != 7'b1101111 && - _theResult____h4607[6:0] != 7'b1100111 && - (IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1043 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207 = - (_theResult____h4607[6:0] == 7'b1100011) ? - (_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 : - _theResult____h4607[6:0] == 7'b1101111 || - _theResult____h4607[6:0] == 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1220 = - ((_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b011) && - (_theResult____h4607[6:0] != 7'b0000111 || - csr_regfile$read_mstatus[14:13] != 2'h0)) ? - 4'd0 : - 4'd11 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1224 = - ((_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011) && - (_theResult____h4607[6:0] != 7'b0100111 || - csr_regfile$read_mstatus[14:13] != 2'h0)) ? - 4'd0 : - 4'd11 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1262 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1235 ? - 4'd6 : - ((_theResult____h4607[11:7] == 5'd0 && - _theResult____h4607[19:15] == 5'd0) ? - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1260 : - 4'd11) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1558 = - ((_theResult____h4607[6:0] == 7'b0010011 || - _theResult____h4607[6:0] == 7'b0110011) && - (_theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101)) ? - alu_outputs___1_val1__h14946 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1559 = - ((_theResult____h4607[6:0] == 7'b0110011 || - _theResult____h4607[6:0] == 7'b0111011) && - _theResult____h4607[31:25] == 7'b0000001) ? - rs1_val_bypassed__h4615 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1558 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1576 = - ((_theResult____h4607[6:0] == 7'b0110011 || - _theResult____h4607[6:0] == 7'b0111011) && - _theResult____h4607[31:25] == 7'b0000001) ? - rs2_val_bypassed__h4621 : - CASE_theResult__607_BITS_6_TO_0_0b100011_alu_o_ETC__q23 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1750 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - rs1_val_bypassed__h4615 == rs2_val_bypassed__h4621 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688 = - (rs1_val_bypassed__h4615 ^ 64'h8000000000000000) < - (rs2_val_bypassed__h4621 ^ 64'h8000000000000000) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690 = - rs1_val_bypassed__h4615 < rs2_val_bypassed__h4621 ; - assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1214 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d733 ? - 4'd11 : - 4'd0 ; - assign IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1270 = - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1190 ? - 4'd0 : - 4'd11 ; - assign IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d258 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - ((stage2_rg_stage2[3] || stage2_rg_stage2[264:260] == 5'd0) ? - 2'd0 : - IF_near_mem_dmem_valid__25_AND_NOT_near_mem_dm_ETC___d256) : - 2'd0 ; - assign IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d284 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - (stage2_rg_stage2[3] ? - IF_near_mem_dmem_valid__25_AND_NOT_near_mem_dm_ETC___d256 : - 2'd0) : - 2'd0 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1043 = - _theResult____h4607[6:0] == 7'b0110011 && - _theResult____h4607[31:25] == 7'b0000001 || - _theResult____h4607[6:0] == 7'b0111011 && - _theResult____h4607[31:25] == 7'b0000001 || - (_theResult____h4607[6:0] == 7'b0010011 || - _theResult____h4607[6:0] == 7'b0110011) && - (_theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101) ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1050 = - _theResult____h4607[14:12] == 3'b0 && - (_theResult____h4607[6:0] != 7'b0110011 || - !_theResult____h4607[30]) || - _theResult____h4607[14:12] == 3'b0 && - _theResult____h4607[6:0] == 7'b0110011 && - _theResult____h4607[30] || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b111 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1235 = - _theResult____h4607[11:7] == 5'd0 && - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) && - _theResult____h4607[31:25] == 7'b0001001 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1432 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 ? - next_pc___1__h18221 : - next_pc__h18219 ; - assign IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 = - near_mem$imem_exc ? - 4'd11 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1285 ; - assign IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d2002 = - imem_rg_pc == csr_regfile$csr_trap_actions[193:130] ; - assign IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 = - (!stage2_rg_full || stage2_rg_stage2[267:265] == 3'd0) ? - 2'd0 : - CASE_stage2_rg_stage2_BITS_267_TO_265_1_IF_NOT_ETC__q3 ; - assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1952 = - csr_regfile$read_csr[63:0] | rs1_val__h23782 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b001) ? - instr__h14206 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b101) ? - instr__h14357 : - 32'h0) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:13] == 3'b101) ? - instr__h14007 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[11:7] != 5'd0 && - instr__h4605[15:13] == 3'b001 && - csr_regfile$read_misa[3]) ? - instr__h13854 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b111) ? - instr__h12815 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b011) ? - instr__h12664 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:13] == 3'b111) ? - instr__h12465 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:12] == 4'b1001 && - instr__h4605[11:7] == 5'd0 && - instr__h4605[6:2] == 5'd0) ? - instr__h12216 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[11:7] != 5'd0 && - instr__h4605[15:13] == 3'b011) ? - instr__h12312 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d599 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100111 && - instr__h4605[6:5] == 2'b01) ? - instr__h11920 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100111 && - instr__h4605[6:5] == 2'b0) ? - instr__h12058 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d601 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100011 && - instr__h4605[6:5] == 2'b01) ? - instr__h11646 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100011 && - instr__h4605[6:5] == 2'b0) ? - instr__h11782 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d599) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d603 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100011 && - instr__h4605[6:5] == 2'b11) ? - instr__h11374 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100011 && - instr__h4605[6:5] == 2'b10) ? - instr__h11510 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d601) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d604 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d417 && - instr__h4605[6:2] != 5'd0) ? - instr__h11279 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d603 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d605 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d411 && - instr__h4605[6:2] != 5'd0) ? - instr__h11160 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d604 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d607 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b100 && - instr__h4605[11:10] == 2'b01 && - imm6__h9273 != 6'd0) ? - instr__h10865 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b100 && - instr__h4605[11:10] == 2'b10) ? - instr__h10982 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d605) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d608 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b100 && - instr__h4605[11:10] == 2'b0 && - imm6__h9273 != 6'd0) ? - instr__h10676 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d607 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d609 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:13] == 3'b0 && - instr__h4605[11:7] != 5'd0 && - imm6__h9273 != 6'd0) ? - instr__h10487 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d608 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d611 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b011 && - instr__h4605[11:7] == 5'd2 && - nzimm10__h9942 != 10'd0) ? - instr__h10146 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b0 && - nzimm10__h10157 != 10'd0) ? - instr__h10318 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d609) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d613 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b0 && - instr__h4605[11:7] != 5'd0 && - imm6__h9273 != 6'd0 || - csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b0 && - instr__h4605[11:7] == 5'd0 && - imm6__h9273 == 6'd0) ? - instr__h9664 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b001 && - instr__h4605[11:7] != 5'd0) ? - instr__h9891 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d611) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d614 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b011 && - instr__h4605[11:7] != 5'd0 && - instr__h4605[11:7] != 5'd2 && - imm6__h9273 != 6'd0) ? - instr__h9535 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d613 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d616 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b111) ? - instr__h9013 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b010 && - instr__h4605[11:7] != 5'd0) ? - instr__h9351 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d614) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d617 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b110) ? - instr__h8696 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d616 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d618 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d417 && - instr__h4605[6:2] == 5'd0) ? - instr__h8631 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d617 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d619 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d411 && - instr__h4605[6:2] == 5'd0) ? - instr__h8515 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d618 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d620 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b101) ? - instr__h8061 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d619 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d621 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b110) ? - instr__h7832 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d620 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d622 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b010) ? - instr__h7637 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d621 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d623 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:13] == 3'b110) ? - instr__h7445 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d622 ; - assign IF_near_mem_dmem_valid__25_AND_NOT_near_mem_dm_ETC___d256 = - (near_mem$dmem_valid && !near_mem$dmem_exc) ? 2'd2 : 2'd1 ; - assign IF_near_mem_dmem_valid__25_THEN_IF_near_mem_dm_ETC___d128 = - near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ; - assign IF_rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7__ETC___d1258 = - ((rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) && - _theResult____h4607[31:20] == 12'b000100000010) ? - 4'd8 : - (rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7_EQ__ETC___d1256 ? - 4'd10 : - 4'd11) ; - assign IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132 = - stage2_fbox$valid ? 2'd2 : 2'd1 ; - assign IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130 = - stage2_mbox$valid ? 2'd2 : 2'd1 ; - assign IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1 : - 2'd0 ; - assign IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 : - 2'd0 ; - assign IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627 = - x_out_bypass_rd__h6724 == _theResult____h4607[19:15] ; - assign IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629 = - x_out_bypass_rd__h6724 == _theResult____h4607[24:20] ; - assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d733 = - (_theResult____h4607[14:12] != 3'b0 || - _theResult____h4607[6:0] == 7'b0110011 && - _theResult____h4607[30]) && - (_theResult____h4607[14:12] != 3'b0 || - _theResult____h4607[6:0] != 7'b0110011 || - !_theResult____h4607[30]) && - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b011 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b111 ; - assign NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 = - cur_verbosity__h3134 > 4'd1 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - (!stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1779) && - (!stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1771) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1824 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1824 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd2 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd0) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1824 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd2 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd0) && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210 || - !stage1_rg_full ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1895 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__48_OR_IF_IF_NOT_n_ETC___d1893) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1897 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__48_OR_IF_IF_NOT_n_ETC___d1893) && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd2 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd0) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1900 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1897 && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210 || - !stage1_rg_full) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1914 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) ; - assign NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1190 = - csr_regfile$read_mstatus[14:13] != 2'h0 && - CASE_theResult__607_BITS_6_TO_0_0b1000011_theR_ETC__q13 && - ((_theResult____h4607[14:12] == 3'b111) ? - csr_regfile$read_frm != 3'b101 && - csr_regfile$read_frm != 3'b110 && - csr_regfile$read_frm != 3'b111 : - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b110) ; - assign NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1353 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd4 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd5 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd6 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd7 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd8 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd9 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd10 ; - assign NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1403 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 != - 3'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 != - 3'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 != - 3'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 != - 3'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 != - 3'd4 ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 = - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] != 2'b11) ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] == 2'b11) && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] == 2'b11) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1760 = - !near_mem$imem_valid || - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == - 2'd1 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1771 = - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632 || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1779 = - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026 ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632 = - !near_mem$imem_valid || - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == - 2'd1 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629) ; - assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1441 = - { {52{theResult__607_BITS_31_TO_20__q20[11]}}, - theResult__607_BITS_31_TO_20__q20 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401 = - { {9{offset__h8008[11]}}, offset__h8008 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426 = - { {4{offset__h8640[8]}}, offset__h8640 } ; - assign _0_OR_0_OR_near_mem_imem_exc__48_OR_IF_IF_NOT_n_ETC___d1893 = - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026 ; - assign _theResult_____1_fst__h16238 = - (_theResult____h4607[14:12] == 3'b0 && - _theResult____h4607[6:0] == 7'b0110011 && - _theResult____h4607[30]) ? - rd_val___1__h16234 : - _theResult_____1_fst__h16245 ; - assign _theResult_____1_fst__h16273 = - rs1_val_bypassed__h4615 & _theResult___snd__h18728 ; - assign _theResult_____1_fst_rd_val__h6703 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - _theResult_____2_fst_rd_val__h6700 : - stage2_rg_stage2[195:132] ; - assign _theResult_____1_snd_fst_rd_val__h6859 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - _theResult_____2_snd_rd_val__h6856 : - stage2_rg_stage2[195:132] ; - assign _theResult_____2_fst_rd_val__h6700 = - (stage2_rg_stage2[3] || stage2_rg_stage2[264:260] == 5'd0) ? - stage2_rg_stage2[195:132] : - near_mem$dmem_word64 ; - assign _theResult_____2_snd_rd_val__h6856 = - stage2_rg_stage2[3] ? - data_to_stage3_rd_val__h6144 : - stage2_rg_stage2[195:132] ; - assign _theResult____h28496 = - (delta_CPI_instrs__h28495 == 64'd0) ? - delta_CPI_instrs___1__h28531 : - delta_CPI_instrs__h28495 ; - assign _theResult____h4607 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 ? - instr___1__h7021 : - instr__h4605 ; - assign _theResult___fst__h16363 = - (_theResult____h4607[14:12] == 3'b001 && - !_theResult____h4607[25]) ? - rd_val___1__h18790 : - _theResult___fst__h16370 ; - assign _theResult___fst__h16370 = - _theResult____h4607[30] ? - rd_val___1__h18873 : - rd_val___1__h18844 ; - assign _theResult___fst__h16490 = - { {32{rs1_val_bypassed615_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8[31]}}, - rs1_val_bypassed615_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8 } ; - assign _theResult___fst__h7200 = - (near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11) ? - instr_out___1__h7202 : - _theResult___fst__h7228 ; - assign _theResult___fst__h7228 = - (near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11) ? - instr_out___1__h7230 : - near_mem$imem_instr ; - assign _theResult___fst_rd_val__h6714 = - stage2_rg_stage2[3] ? - stage2_rg_stage2[195:132] : - stage2_fbox$word_fst ; - assign _theResult___snd__h18728 = - (_theResult____h4607[6:0] == 7'b0010011) ? - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1441 : - rs2_val_bypassed__h4621 ; - assign _theResult___snd_rd_val__h6865 = - stage2_rg_stage2[3] ? - stage2_fbox$word_fst : - stage2_rg_stage2[195:132] ; - assign alu_outputs___1_addr5117_BITS_31_TO_0__q21 = - alu_outputs___1_addr__h15117[31:0] ; - assign alu_outputs___1_addr__h14775 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 ? - branch_target__h14754 : - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1432 ; - assign alu_outputs___1_addr__h14799 = - imem_rg_pc + - { {43{theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q5[20]}}, - theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q5 } ; - assign alu_outputs___1_addr__h14828 = - { alu_outputs___1_addr__h15117[63:1], 1'd0 } ; - assign alu_outputs___1_addr__h15117 = - rs1_val_bypassed__h4615 + - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1441 ; - assign alu_outputs___1_addr__h15141 = - rs1_val_bypassed__h4615 + - { {52{theResult__607_BITS_31_TO_25_CONCAT_theResult__ETC__q6[11]}}, - theResult__607_BITS_31_TO_25_CONCAT_theResult__ETC__q6 } ; - assign alu_outputs___1_exc_code__h15424 = - (_theResult____h4607[14:12] == 3'b0) ? - (IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1235 ? - 4'd2 : - ((_theResult____h4607[11:7] == 5'd0 && - _theResult____h4607[19:15] == 5'd0) ? - CASE_theResult__607_BITS_31_TO_20_0b0_CASE_rg__ETC__q16 : - 4'd2)) : - 4'd2 ; - assign alu_outputs___1_val1__h14946 = - (_theResult____h4607[14:12] == 3'b001) ? - rd_val__h18622 : - (_theResult____h4607[30] ? rd_val__h18696 : rd_val__h18674) ; - assign alu_outputs___1_val1__h14987 = - (_theResult____h4607[14:12] == 3'b0 && - (_theResult____h4607[6:0] != 7'b0110011 || - !_theResult____h4607[30])) ? - rd_val___1__h16226 : - _theResult_____1_fst__h16238 ; - assign alu_outputs___1_val1__h15013 = - (_theResult____h4607[14:12] == 3'b0) ? - rd_val___1__h18759 : - _theResult___fst__h16363 ; - assign alu_outputs___1_val1__h15058 = - { {32{v32__h15047[31]}}, v32__h15047 } ; - assign alu_outputs___1_val1__h15077 = - imem_rg_pc + alu_outputs___1_val1__h15058 ; - assign alu_outputs___1_val1__h15428 = - _theResult____h4607[14] ? - { 59'd0, _theResult____h4607[19:15] } : - rs1_val_bypassed__h4615 ; - assign alu_outputs___1_val1__h15452 = - { 57'd0, _theResult____h4607[31:25] } ; - assign alu_outputs___1_val1__h15653 = - (_theResult____h4607[6:0] == 7'b1010011 && - (_theResult____h4607[31:25] == 7'h69 && - (_theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2 || - _theResult____h4607[24:20] == 5'd3) || - _theResult____h4607[31:25] == 7'h79 || - _theResult____h4607[31:25] == 7'h68 && - (_theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2 || - _theResult____h4607[24:20] == 5'd3) || - _theResult____h4607[31:25] == 7'h78)) ? - rs1_val_bypassed__h4615 : - frs1_val_bypassed__h4626 ; - assign alu_outputs___1_val2__h15143 = - (_theResult____h4607[6:0] == 7'b0100111) ? - frs2_val_bypassed__h4631 : - rs2_val_bypassed__h4621 ; - assign branch_target__h14754 = - imem_rg_pc + - { {51{theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q4[12]}}, - theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q4 } ; - assign cpi__h28498 = x__h28497 / 64'd10 ; - assign cpifrac__h28499 = x__h28497 % 64'd10 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1753 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1749 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1750 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1758 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd2 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd0 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1764 = - csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1753 || - (csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1758 || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1760 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - stage1_rg_full ; - assign csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d2005 = - delta_CPI_cycles__h28494 * 64'd10 ; - assign csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d411 = - csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:12] == 4'b1000 && - instr__h4605[11:7] != 5'd0 ; - assign csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d417 = - csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:12] == 4'b1001 && - instr__h4605[11:7] != 5'd0 ; - assign csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d1000 = - csr_regfile$read_mstatus[14:13] == 2'h0 || - CASE_theResult__607_BITS_6_TO_0_0b1000011_NOT__ETC__q11 || - ((_theResult____h4607[14:12] == 3'b111) ? - csr_regfile$read_frm == 3'b101 || - csr_regfile$read_frm == 3'b110 || - csr_regfile$read_frm == 3'b111 : - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b110) ; - assign cur_verbosity__h3134 = - (csr_regfile$read_csr_minstret < cfg_logdelay) ? - 4'd0 : - cfg_verbosity ; - assign data_to_stage2_addr__h14637 = x_out_data_to_stage2_addr__h14648 ; - assign data_to_stage3_rd_val__h6144 = - stage2_rg_stage2[3] ? - ((stage2_rg_stage2[282:280] == 3'b010) ? - { 32'hFFFFFFFF, near_mem$dmem_word64[31:0] } : - near_mem$dmem_word64) : - near_mem$dmem_word64 ; - assign delta_CPI_cycles__h28494 = - csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ; - assign delta_CPI_instrs___1__h28531 = delta_CPI_instrs__h28495 + 64'd1 ; - assign delta_CPI_instrs__h28495 = - csr_regfile$read_csr_minstret - rg_start_CPI_instrs ; - assign fall_through_pc__h14598 = - imem_rg_pc + - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d639 ? - 64'd4 : - 64'd2) ; - assign fpr_regfile_RDY_server_reset_request_put__697__ETC___d1709 = - fpr_regfile$RDY_server_reset_request_put && - near_mem$RDY_server_reset_request_put && - csr_regfile$RDY_server_reset_request_put && - f_reset_reqs$EMPTY_N && - stage1_f_reset_reqs$FULL_N && - stage2_f_reset_reqs$FULL_N && - stage3_f_reset_reqs$FULL_N ; - assign frs1_val_bypassed__h4626 = - (IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6873 == _theResult____h4607[19:15]) ? - x_out_fbypass_rd_val__h6874 : - rd_val__h19313 ; - assign frs2_val_bypassed__h4631 = - (IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6873 == _theResult____h4607[24:20]) ? - x_out_fbypass_rd_val__h6874 : - rd_val__h19369 ; - assign funct10__h15025 = - { _theResult____h4607[31:25], _theResult____h4607[14:12] } ; - assign imm12__h10159 = { 2'd0, nzimm10__h10157 } ; - assign imm12__h10355 = { 6'b0, imm6__h9273 } ; - assign imm12__h10692 = { 6'b010000, imm6__h9273 } ; - assign imm12__h12313 = { 3'd0, offset__h12227 } ; - assign imm12__h12665 = { 4'd0, offset__h12599 } ; - assign imm12__h7301 = { 4'd0, offset__h7071 } ; - assign imm12__h7638 = { 5'd0, offset__h7580 } ; - assign imm12__h9275 = { {6{imm6__h9273[5]}}, imm6__h9273 } ; - assign imm12__h9944 = { {2{nzimm10__h9942[9]}}, nzimm10__h9942 } ; - assign imm20__h9403 = { {14{imm6__h9273[5]}}, imm6__h9273 } ; - assign imm6__h9273 = { instr__h4605[12], instr__h4605[6:2] } ; - assign instr___1__h7021 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[11:7] != 5'd0 && - instr__h4605[15:13] == 3'b010) ? - instr__h7300 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d623 ; - assign instr__h10146 = - { imm12__h9944, - instr__h4605[11:7], - 3'b0, - instr__h4605[11:7], - 7'b0010011 } ; - assign instr__h10318 = { imm12__h10159, 8'd16, rd__h7640, 7'b0010011 } ; - assign instr__h10487 = - { imm12__h10355, - instr__h4605[11:7], - 3'b001, - instr__h4605[11:7], - 7'b0010011 } ; - assign instr__h10676 = - { imm12__h10355, rs1__h7639, 3'b101, rs1__h7639, 7'b0010011 } ; - assign instr__h10865 = - { imm12__h10692, rs1__h7639, 3'b101, rs1__h7639, 7'b0010011 } ; - assign instr__h10982 = - { imm12__h9275, rs1__h7639, 3'b111, rs1__h7639, 7'b0010011 } ; - assign instr__h11160 = - { 7'b0, - instr__h4605[6:2], - 8'd0, - instr__h4605[11:7], - 7'b0110011 } ; - assign instr__h11279 = - { 7'b0, - instr__h4605[6:2], - instr__h4605[11:7], - 3'b0, - instr__h4605[11:7], - 7'b0110011 } ; - assign instr__h11374 = - { 7'b0, rd__h7640, rs1__h7639, 3'b111, rs1__h7639, 7'b0110011 } ; - assign instr__h11510 = - { 7'b0, rd__h7640, rs1__h7639, 3'b110, rs1__h7639, 7'b0110011 } ; - assign instr__h11646 = - { 7'b0, rd__h7640, rs1__h7639, 3'b100, rs1__h7639, 7'b0110011 } ; - assign instr__h11782 = - { 7'b0100000, - rd__h7640, - rs1__h7639, - 3'b0, - rs1__h7639, - 7'b0110011 } ; - assign instr__h11920 = - { 7'b0, rd__h7640, rs1__h7639, 3'b0, rs1__h7639, 7'b0111011 } ; - assign instr__h12058 = - { 7'b0100000, - rd__h7640, - rs1__h7639, - 3'b0, - rs1__h7639, - 7'b0111011 } ; - assign instr__h12216 = - { 12'b000000000001, - instr__h4605[11:7], - 3'b0, - instr__h4605[11:7], - 7'b1110011 } ; - assign instr__h12312 = - { imm12__h12313, 8'd19, instr__h4605[11:7], 7'b0000011 } ; - assign instr__h12465 = - { 3'd0, - instr__h4605[9:7], - instr__h4605[12], - instr__h4605[6:2], - 8'd19, - offset_BITS_4_TO_0___h12940, - 7'b0100011 } ; - assign instr__h12664 = - { imm12__h12665, rs1__h7639, 3'b011, rd__h7640, 7'b0000011 } ; - assign instr__h12815 = - { 4'd0, - instr__h4605[6:5], - instr__h4605[12], - rd__h7640, - rs1__h7639, - 3'b011, - offset_BITS_4_TO_0___h12940, - 7'b0100011 } ; - assign instr__h13854 = - { imm12__h12313, 8'd19, instr__h4605[11:7], 7'b0000111 } ; - assign instr__h14007 = - { 3'd0, - instr__h4605[9:7], - instr__h4605[12], - instr__h4605[6:2], - 8'd19, - offset_BITS_4_TO_0___h12940, - 7'b0100111 } ; - assign instr__h14206 = - { imm12__h12665, rs1__h7639, 3'b011, rd__h7640, 7'b0000111 } ; - assign instr__h14357 = - { 4'd0, - instr__h4605[6:5], - instr__h4605[12], - rd__h7640, - rs1__h7639, - 3'b011, - offset_BITS_4_TO_0___h12940, - 7'b0100111 } ; - assign instr__h4605 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 ? - instr_out___1__h7170 : - _theResult___fst__h7200 ; - assign instr__h7300 = - { imm12__h7301, 8'd18, instr__h4605[11:7], 7'b0000011 } ; - assign instr__h7445 = - { 4'd0, - instr__h4605[8:7], - instr__h4605[12], - instr__h4605[6:2], - 8'd18, - offset_BITS_4_TO_0___h7569, - 7'b0100011 } ; - assign instr__h7637 = - { imm12__h7638, rs1__h7639, 3'b010, rd__h7640, 7'b0000011 } ; - assign instr__h7832 = - { 5'd0, - instr__h4605[5], - instr__h4605[12], - rd__h7640, - rs1__h7639, - 3'b010, - offset_BITS_4_TO_0___h8000, - 7'b0100011 } ; - assign instr__h8061 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401[19:12], - 12'd111 } ; - assign instr__h8515 = { 12'd0, instr__h4605[11:7], 15'd103 } ; - assign instr__h8631 = { 12'd0, instr__h4605[11:7], 15'd231 } ; - assign instr__h8696 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[10:5], - 5'd0, - rs1__h7639, - 3'b0, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[11], - 7'b1100011 } ; - assign instr__h9013 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[10:5], - 5'd0, - rs1__h7639, - 3'b001, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[11], - 7'b1100011 } ; - assign instr__h9351 = - { imm12__h9275, 8'd0, instr__h4605[11:7], 7'b0010011 } ; - assign instr__h9535 = { imm20__h9403, instr__h4605[11:7], 7'b0110111 } ; - assign instr__h9664 = - { imm12__h9275, - instr__h4605[11:7], - 3'b0, - instr__h4605[11:7], - 7'b0010011 } ; - assign instr__h9891 = - { imm12__h9275, - instr__h4605[11:7], - 3'b0, - instr__h4605[11:7], - 7'b0011011 } ; - assign instr_out___1__h7170 = - { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ; - assign instr_out___1__h7202 = { 16'b0, near_mem$imem_instr[15:0] } ; - assign instr_out___1__h7230 = { 16'b0, near_mem$imem_instr[31:16] } ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1603 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd0 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1606 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd1 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1609 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd2 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1612 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd3 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1615 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd4 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1618 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd5 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1621 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd6 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1624 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd7 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1627 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd8 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1630 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd9 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1633 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd10 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1636 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd4 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd5 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd6 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd7 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd8 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd9 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd10 ; - assign near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 = - near_mem$imem_pc[63:2] == imem_rg_pc[63:2] ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d639 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] == 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d641 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d639 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 = - near_mem$imem_pc == next_pc___1__h18221 ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1749 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 != - 2'd1 || - !IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627 && - !IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d641 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 != - 2'd1 || - !IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627 && - !IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629) ; - assign next_pc___1__h18221 = imem_rg_pc + 64'd2 ; - assign next_pc__h18219 = imem_rg_pc + 64'd4 ; - assign nzimm10__h10157 = - { instr__h4605[10:7], - instr__h4605[12:11], - instr__h4605[5], - instr__h4605[6], - 2'b0 } ; - assign nzimm10__h9942 = - { instr__h4605[12], - instr__h4605[4:3], - instr__h4605[5], - instr__h4605[2], - instr__h4605[6], - 4'b0 } ; - assign offset_BITS_4_TO_0___h12940 = { instr__h4605[11:10], 3'b0 } ; - assign offset_BITS_4_TO_0___h7569 = { instr__h4605[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h8000 = - { instr__h4605[11:10], instr__h4605[6], 2'b0 } ; - assign offset__h12227 = - { instr__h4605[4:2], - instr__h4605[12], - instr__h4605[6:5], - 3'b0 } ; - assign offset__h12599 = { instr__h4605[6:5], instr__h4605[12:10], 3'b0 } ; - assign offset__h7071 = - { instr__h4605[3:2], - instr__h4605[12], - instr__h4605[6:4], - 2'b0 } ; - assign offset__h7580 = - { instr__h4605[5], instr__h4605[12:10], instr__h4605[6], 2'b0 } ; - assign offset__h8008 = - { instr__h4605[12], - instr__h4605[8], - instr__h4605[10:9], - instr__h4605[6], - instr__h4605[7], - instr__h4605[2], - instr__h4605[11], - instr__h4605[5:3], - 1'b0 } ; - assign offset__h8640 = - { instr__h4605[12], - instr__h4605[6:5], - instr__h4605[2], - instr__h4605[11:10], - instr__h4605[4:3], - 1'b0 } ; - assign rd__h7640 = { 2'b01, instr__h4605[4:2] } ; - assign rd_val___1__h16226 = - rs1_val_bypassed__h4615 + _theResult___snd__h18728 ; - assign rd_val___1__h16234 = - rs1_val_bypassed__h4615 - _theResult___snd__h18728 ; - assign rd_val___1__h16241 = - ((rs1_val_bypassed__h4615 ^ 64'h8000000000000000) < - (_theResult___snd__h18728 ^ 64'h8000000000000000)) ? - 64'd1 : - 64'd0 ; - assign rd_val___1__h16248 = - (rs1_val_bypassed__h4615 < _theResult___snd__h18728) ? - 64'd1 : - 64'd0 ; - assign rd_val___1__h16255 = - rs1_val_bypassed__h4615 ^ _theResult___snd__h18728 ; - assign rd_val___1__h16262 = - rs1_val_bypassed__h4615 | _theResult___snd__h18728 ; - assign rd_val___1__h18759 = - { {32{alu_outputs___1_addr5117_BITS_31_TO_0__q21[31]}}, - alu_outputs___1_addr5117_BITS_31_TO_0__q21 } ; - assign rd_val___1__h18790 = { {32{x__h18793[31]}}, x__h18793 } ; - assign rd_val___1__h18844 = { {32{x__h18847[31]}}, x__h18847 } ; - assign rd_val___1__h18873 = { {32{tmp__h18872[31]}}, tmp__h18872 } ; - assign rd_val___1__h18927 = - { {32{rs1_val_bypassed615_BITS_31_TO_0_PLUS_rs2_val__ETC__q9[31]}}, - rs1_val_bypassed615_BITS_31_TO_0_PLUS_rs2_val__ETC__q9 } ; - assign rd_val___1__h18975 = - { {32{rs1_val_bypassed615_BITS_31_TO_0_MINUS_rs2_val_ETC__q10[31]}}, - rs1_val_bypassed615_BITS_31_TO_0_MINUS_rs2_val_ETC__q10 } ; - assign rd_val___1__h18981 = { {32{x__h18984[31]}}, x__h18984 } ; - assign rd_val___1__h19026 = { {32{x__h19029[31]}}, x__h19029 } ; - assign rd_val__h14531 = - (!stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d672) ? - stage3_rg_stage3[63:0] : - gpr_regfile$read_rs1 ; - assign rd_val__h14574 = - (!stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d680) ? - stage3_rg_stage3[63:0] : - gpr_regfile$read_rs2 ; - assign rd_val__h18622 = rs1_val_bypassed__h4615 << shamt__h14931 ; - assign rd_val__h18674 = rs1_val_bypassed__h4615 >> shamt__h14931 ; - assign rd_val__h18696 = - rs1_val_bypassed__h4615 >> shamt__h14931 | - ~(64'hFFFFFFFFFFFFFFFF >> shamt__h14931) & - {64{rs1_val_bypassed__h4615[63]}} ; - assign rd_val__h19313 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d672) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs1 ; - assign rd_val__h19369 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d680) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs2 ; - assign rd_val__h19422 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3[75:71] == _theResult____h4607[31:27]) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs3 ; - assign rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7_EQ__ETC___d1256 = - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] || - rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) && - _theResult____h4607[31:20] == 12'b000100000101 ; - assign rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 = - rg_state == 4'd3 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1914 && - !stage3_rg_full && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd0 ; - assign rg_state_6_EQ_3_766_AND_stage3_rg_full_6_OR_NO_ETC___d1785 = - rg_state == 4'd3 && - (stage3_rg_full || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd0 || - stage1_rg_full) && - (stage3_rg_full || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd3) && - (stage3_rg_full || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd0 || - !stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1771) && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd0 || - stage3_rg_full) ; - assign rm__h15556 = x_out_data_to_stage2_rounding_mode__h14653 ; - assign rs1__h7639 = { 2'b01, instr__h4605[9:7] } ; - assign rs1_val__h23289 = - (x_out_data_to_stage2_instr__h14645[14:12] == 3'b001) ? - x_out_data_to_stage2_val1__h14649 : - { 59'd0, x_out_data_to_stage2_instr__h14645[19:15] } ; - assign rs1_val_bypassed615_BITS_31_TO_0_MINUS_rs2_val_ETC__q10 = - rs1_val_bypassed__h4615[31:0] - rs2_val_bypassed__h4621[31:0] ; - assign rs1_val_bypassed615_BITS_31_TO_0_PLUS_rs2_val__ETC__q9 = - rs1_val_bypassed__h4615[31:0] + rs2_val_bypassed__h4621[31:0] ; - assign rs1_val_bypassed615_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8 = - rs1_val_bypassed__h4615[31:0] >> rs2_val_bypassed__h4621[4:0] | - ~(32'hFFFFFFFF >> rs2_val_bypassed__h4621[4:0]) & - {32{rs1_val_bypassed615_BITS_31_TO_0__q7[31]}} ; - assign rs1_val_bypassed615_BITS_31_TO_0__q7 = - rs1_val_bypassed__h4615[31:0] ; - assign rs1_val_bypassed__h4615 = - (_theResult____h4607[19:15] == 5'd0) ? 64'd0 : val__h14533 ; - assign rs2_val_bypassed__h4621 = - (_theResult____h4607[24:20] == 5'd0) ? 64'd0 : val__h14576 ; - assign shamt__h14931 = - (_theResult____h4607[6:0] == 7'b0010011) ? - _theResult____h4607[25:20] : - rs2_val_bypassed__h4621[5:0] ; - assign stage2_f_reset_rsps_i_notEmpty__720_AND_stage3_ETC___d1729 = - stage2_f_reset_rsps$EMPTY_N && stage3_f_reset_rsps$EMPTY_N && - f_reset_rsps$FULL_N && - (!rg_run_on_reset || - !near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) ; - assign stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d672 = - stage3_rg_stage3[75:71] == _theResult____h4607[19:15] ; - assign stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d680 = - stage3_rg_stage3[75:71] == _theResult____h4607[24:20] ; - assign sxl__h5045 = - (csr_regfile$read_misa[27:26] == 2'd2) ? - csr_regfile$read_mstatus[35:34] : - 2'd0 ; - assign theResult__607_BITS_31_TO_20__q20 = _theResult____h4607[31:20] ; - assign theResult__607_BITS_31_TO_25_CONCAT_theResult__ETC__q6 = - { _theResult____h4607[31:25], _theResult____h4607[11:7] } ; - assign theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q4 = - { _theResult____h4607[31], - _theResult____h4607[7], - _theResult____h4607[30:25], - _theResult____h4607[11:8], - 1'b0 } ; - assign theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q5 = - { _theResult____h4607[31], - _theResult____h4607[19:12], - _theResult____h4607[20], - _theResult____h4607[30:21], - 1'b0 } ; - assign tmp__h18872 = - rs1_val_bypassed__h4615[31:0] >> _theResult____h4607[24:20] | - ~(32'hFFFFFFFF >> _theResult____h4607[24:20]) & - {32{rs1_val_bypassed615_BITS_31_TO_0__q7[31]}} ; - assign trap_info_tval__h18051 = - (_theResult____h4607[6:0] != 7'b1101111 && - _theResult____h4607[6:0] != 7'b1100111 && - (_theResult____h4607[6:0] != 7'b1110011 || - _theResult____h4607[14:12] != 3'b0 || - _theResult____h4607[11:7] != 5'd0 || - _theResult____h4607[19:15] != 5'd0 || - _theResult____h4607[31:20] != 12'b0 && - _theResult____h4607[31:20] != 12'b000000000001)) ? - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d639 ? - { 32'd0, _theResult____h4607 } : - { 48'd0, instr__h4605[15:0] }) : - CASE_theResult__607_BITS_6_TO_0_0b1100111_data_ETC__q22 ; - assign uxl__h5046 = - (csr_regfile$read_misa[27:26] == 2'd2) ? - csr_regfile$read_mstatus[33:32] : - 2'd0 ; - assign v32__h15047 = { _theResult____h4607[31:12], 12'h0 } ; - assign val__h14533 = - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == - 2'd2 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627) ? - x_out_bypass_rd_val__h6725 : - rd_val__h14531 ; - assign val__h14576 = - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == - 2'd2 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629) ? - x_out_bypass_rd_val__h6725 : - rd_val__h14574 ; - assign value__h18109 = - near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h18051 ; - assign x__h18793 = - rs1_val_bypassed__h4615[31:0] << _theResult____h4607[24:20] ; - assign x__h18847 = - rs1_val_bypassed__h4615[31:0] >> _theResult____h4607[24:20] ; - assign x__h18984 = - rs1_val_bypassed__h4615[31:0] << rs2_val_bypassed__h4621[4:0] ; - assign x__h19029 = - rs1_val_bypassed__h4615[31:0] >> rs2_val_bypassed__h4621[4:0] ; - assign x__h28497 = - csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d2005[63:0] / - _theResult____h28496 ; - assign x_out_data_to_stage2_instr__h14645 = _theResult____h4607 ; - assign x_out_data_to_stage2_rounding_mode__h14653 = - (_theResult____h4607[14:12] == 3'b111) ? - csr_regfile$read_frm : - _theResult____h4607[14:12] ; - assign x_out_data_to_stage2_val2__h14650 = - (_theResult____h4607[6:0] == 7'b1100011) ? - branch_target__h14754 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1576 ; - assign x_out_data_to_stage2_val3__h14651 = - (IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6873 == _theResult____h4607[31:27]) ? - x_out_fbypass_rd_val__h6874 : - rd_val__h19422 ; - assign x_out_next_pc__h14611 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207 ? - data_to_stage2_addr__h14637 : - fall_through_pc__h14598 ; - assign x_out_trap_info_exc_code__h18054 = - near_mem$imem_exc ? - near_mem$imem_exc_code : - alu_outputs_exc_code__h15680 ; - assign y__h24086 = ~rs1_val__h23782 ; - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd2, 3'd4: value__h6429 = stage2_rg_stage2[363:300]; - default: value__h6429 = stage2_rg_stage2[363:300]; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_exc_code) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd2, 3'd4: - x_out_trap_info_exc_code__h6466 = near_mem$dmem_exc_code; - default: x_out_trap_info_exc_code__h6466 = 4'd2; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd2, 3'd4: value__h6490 = stage2_rg_stage2[259:196]; - default: value__h6490 = 64'd0; - endcase - end - always@(stage2_rg_stage2 or stage2_fbox$word_snd) - begin - case (stage2_rg_stage2[267:265]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - x_out_data_to_stage3_fpr_flags__h6249 = 5'd0; - default: x_out_data_to_stage3_fpr_flags__h6249 = stage2_fbox$word_snd; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[267:265]) - 3'd0, 3'd1, 3'd4: - x_out_data_to_stage3_rd__h6246 = stage2_rg_stage2[264:260]; - 3'd2: x_out_data_to_stage3_rd__h6246 = 5'd0; - default: x_out_data_to_stage3_rd__h6246 = stage2_rg_stage2[264:260]; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[267:265]) - 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h6724 = stage2_rg_stage2[264:260]; - default: x_out_bypass_rd__h6724 = stage2_rg_stage2[264:260]; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd4: x_out_fbypass_rd__h6873 = stage2_rg_stage2[264:260]; - default: x_out_fbypass_rd__h6873 = stage2_rg_stage2[264:260]; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$word_fst or - data_to_stage3_rd_val__h6144 or stage2_mbox$word) - begin - case (stage2_rg_stage2[267:265]) - 3'd0: x_out_data_to_stage3_rd_val__h6250 = stage2_rg_stage2[195:132]; - 3'd1, 3'd4: - x_out_data_to_stage3_rd_val__h6250 = data_to_stage3_rd_val__h6144; - 3'd3: x_out_data_to_stage3_rd_val__h6250 = stage2_mbox$word; - default: x_out_data_to_stage3_rd_val__h6250 = stage2_fbox$word_fst; - endcase - end - always@(stage2_rg_stage2 or - _theResult___fst_rd_val__h6714 or - _theResult_____1_fst_rd_val__h6703 or stage2_mbox$word) - begin - case (stage2_rg_stage2[267:265]) - 3'd0: x_out_bypass_rd_val__h6725 = stage2_rg_stage2[195:132]; - 3'd1, 3'd4: - x_out_bypass_rd_val__h6725 = _theResult_____1_fst_rd_val__h6703; - 3'd3: x_out_bypass_rd_val__h6725 = stage2_mbox$word; - default: x_out_bypass_rd_val__h6725 = _theResult___fst_rd_val__h6714; - endcase - end - always@(stage2_rg_stage2 or - _theResult___snd_rd_val__h6865 or - _theResult_____1_snd_fst_rd_val__h6859) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd4: - x_out_fbypass_rd_val__h6874 = - _theResult_____1_snd_fst_rd_val__h6859; - default: x_out_fbypass_rd_val__h6874 = _theResult___snd_rd_val__h6865; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132 or - IF_near_mem_dmem_valid__25_THEN_IF_near_mem_dm_ETC___d128 or - IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130) - begin - case (stage2_rg_stage2[267:265]) - 3'd0: CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1 = 2'd2; - 3'd1, 3'd2, 3'd4: - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1 = - IF_near_mem_dmem_valid__25_THEN_IF_near_mem_dm_ETC___d128; - 3'd3: - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1 = - IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130; - default: CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1 = - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$valid or - near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153 = - !near_mem$dmem_valid || near_mem$dmem_exc; - 3'd3: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153 = - !stage2_mbox$valid; - default: IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153 = - !stage2_fbox$valid; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$valid or - near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163 = - near_mem$dmem_valid && !near_mem$dmem_exc; - 3'd3: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163 = - stage2_mbox$valid; - default: IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163 = - stage2_fbox$valid; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd4: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) && - stage2_rg_stage2[3]; - default: IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198 = - stage2_rg_stage2[267:265] != 3'd2 && - stage2_rg_stage2[267:265] != 3'd3 && - stage2_rg_stage2[3]; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd4: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d232 = - near_mem$dmem_valid && near_mem$dmem_exc || - !stage2_rg_stage2[3]; - default: IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d232 = - stage2_rg_stage2[267:265] == 3'd2 || - stage2_rg_stage2[267:265] == 3'd3 || - !stage2_rg_stage2[3]; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132 or - IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d258 or - IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130) - begin - case (stage2_rg_stage2[267:265]) - 3'd0: CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 = 2'd2; - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 = - IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d258; - 3'd2: CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 = 2'd0; - 3'd3: - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 = - IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130; - default: CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 = - stage2_rg_stage2[3] ? - 2'd0 : - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132 or - IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d284) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_267_TO_265_1_IF_NOT_ETC__q3 = - IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d284; - 3'd2, 3'd3: - CASE_stage2_rg_stage2_BITS_267_TO_265_1_IF_NOT_ETC__q3 = 2'd0; - default: CASE_stage2_rg_stage2_BITS_267_TO_265_1_IF_NOT_ETC__q3 = - stage2_rg_stage2[3] ? - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132 : - 2'd0; - endcase - end - always@(_theResult____h4607) - begin - case (_theResult____h4607[6:0]) - 7'b0000011, - 7'b0000111, - 7'b0010011, - 7'b0010111, - 7'b0011011, - 7'b0110011, - 7'b0110111, - 7'b0111011, - 7'b1100111, - 7'b1101111: - x_out_data_to_stage2_rd__h14647 = _theResult____h4607[11:7]; - 7'b1100011: x_out_data_to_stage2_rd__h14647 = 5'd0; - default: x_out_data_to_stage2_rd__h14647 = _theResult____h4607[11:7]; - endcase - end - always@(funct10__h15025 or - _theResult___fst__h16490 or - rd_val___1__h18927 or - rd_val___1__h18981 or rd_val___1__h19026 or rd_val___1__h18975) - begin - case (funct10__h15025) - 10'b0: alu_outputs___1_val1__h15039 = rd_val___1__h18927; - 10'b0000000001: alu_outputs___1_val1__h15039 = rd_val___1__h18981; - 10'b0000000101: alu_outputs___1_val1__h15039 = rd_val___1__h19026; - 10'b0100000000: alu_outputs___1_val1__h15039 = rd_val___1__h18975; - default: alu_outputs___1_val1__h15039 = _theResult___fst__h16490; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) - begin - case (_theResult____h4607[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - _theResult____h4607[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) - begin - case (_theResult____h4607[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - _theResult____h4607[14:12] == 3'b111 && - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690; - endcase - end - always@(_theResult____h4607 or rm__h15556) - begin - case (_theResult____h4607[6:0]) - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111: - CASE_theResult__607_BITS_6_TO_0_0b1000011_NOT__ETC__q11 = - _theResult____h4607[26:25] != 2'b0 && - _theResult____h4607[26:25] != 2'b01; - default: CASE_theResult__607_BITS_6_TO_0_0b1000011_NOT__ETC__q11 = - _theResult____h4607[31:25] != 7'h0 && - _theResult____h4607[31:25] != 7'h04 && - _theResult____h4607[31:25] != 7'h08 && - _theResult____h4607[31:25] != 7'h0C && - _theResult____h4607[31:25] != 7'h2C && - (_theResult____h4607[31:25] != 7'h10 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h10 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h10 || - rm__h15556 != 3'd2) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd3) && - (_theResult____h4607[31:25] != 7'h68 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h68 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h68 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h68 || - _theResult____h4607[24:20] != 5'd3) && - (_theResult____h4607[31:25] != 7'h14 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h14 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h50 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h50 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h50 || - rm__h15556 != 3'd2) && - (_theResult____h4607[31:25] != 7'h70 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h78 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h70 || - rm__h15556 != 3'd1) && - _theResult____h4607[31:25] != 7'b0000001 && - _theResult____h4607[31:25] != 7'h05 && - _theResult____h4607[31:25] != 7'b0001001 && - _theResult____h4607[31:25] != 7'h0D && - _theResult____h4607[31:25] != 7'h2D && - (_theResult____h4607[31:25] != 7'h11 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h11 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h11 || - rm__h15556 != 3'd2) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd3) && - (_theResult____h4607[31:25] != 7'h69 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h69 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h69 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h69 || - _theResult____h4607[24:20] != 5'd3) && - (_theResult____h4607[31:25] != 7'h21 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h20 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h15 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h15 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h51 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h51 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h51 || - rm__h15556 != 3'd2) && - (_theResult____h4607[31:25] != 7'h71 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h79 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h71 || - rm__h15556 != 3'd1); - endcase - end - always@(_theResult____h4607 or - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d1000 or - csr_regfile$read_mstatus) - begin - case (_theResult____h4607[6:0]) - 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004 = - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b011 || - csr_regfile$read_mstatus[14:13] == 2'h0; - 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004 = - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b011 || - csr_regfile$read_mstatus[14:13] == 2'h0; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004 = - _theResult____h4607[31:27] != 5'b00010 && - _theResult____h4607[31:27] != 5'b00011 && - _theResult____h4607[31:27] != 5'b0 && - _theResult____h4607[31:27] != 5'b00001 && - _theResult____h4607[31:27] != 5'b01100 && - _theResult____h4607[31:27] != 5'b01000 && - _theResult____h4607[31:27] != 5'b00100 && - _theResult____h4607[31:27] != 5'b10000 && - _theResult____h4607[31:27] != 5'b11000 && - _theResult____h4607[31:27] != 5'b10100 && - _theResult____h4607[31:27] != 5'b11100 || - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b011; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004 = - _theResult____h4607[6:0] != 7'b1010011 && - _theResult____h4607[6:0] != 7'b1000011 && - _theResult____h4607[6:0] != 7'b1000111 && - _theResult____h4607[6:0] != 7'b1001011 && - _theResult____h4607[6:0] != 7'b1001111 || - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d1000; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004) - begin - case (_theResult____h4607[6:0]) - 7'b0000011: - CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b011; - 7'b0100011: - CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b011; - default: CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4607[6:0] == 7'b0001111 || - _theResult____h4607[6:0] == 7'b1110011 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004; - endcase - end - always@(_theResult____h4607 or - CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 or - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d733 or - funct10__h15025) - begin - case (_theResult____h4607[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d733; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012 = - _theResult____h4607[14:12] != 3'b0 && - (_theResult____h4607[14:12] != 3'b001 || - _theResult____h4607[25]) && - (_theResult____h4607[14:12] != 3'b101 || - _theResult____h4607[25]); - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012 = - funct10__h15025 != 10'b0 && funct10__h15025 != 10'b0100000000 && - funct10__h15025 != 10'b0000000001 && - funct10__h15025 != 10'b0000000101 && - funct10__h15025 != 10'b0100000101; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012 = - _theResult____h4607[6:0] != 7'b0110111 && - _theResult____h4607[6:0] != 7'b0010111 && - CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12; - endcase - end - always@(_theResult____h4607 or rm__h15556) - begin - case (_theResult____h4607[6:0]) - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111: - CASE_theResult__607_BITS_6_TO_0_0b1000011_theR_ETC__q13 = - _theResult____h4607[26:25] == 2'b0 || - _theResult____h4607[26:25] == 2'b01; - default: CASE_theResult__607_BITS_6_TO_0_0b1000011_theR_ETC__q13 = - _theResult____h4607[31:25] == 7'h0 || - _theResult____h4607[31:25] == 7'h04 || - _theResult____h4607[31:25] == 7'h08 || - _theResult____h4607[31:25] == 7'h0C || - _theResult____h4607[31:25] == 7'h2C || - _theResult____h4607[31:25] == 7'h10 && - (rm__h15556 == 3'd0 || rm__h15556 == 3'd1 || - rm__h15556 == 3'd2) || - _theResult____h4607[31:25] == 7'h60 && - _theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[31:25] == 7'h60 && - (_theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2 || - _theResult____h4607[24:20] == 5'd3) || - _theResult____h4607[31:25] == 7'h68 && - (_theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2) || - _theResult____h4607[31:25] == 7'h68 && - _theResult____h4607[24:20] == 5'd3 || - _theResult____h4607[31:25] == 7'h14 && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h14 && - rm__h15556 == 3'd1 || - _theResult____h4607[31:25] == 7'h50 && - (rm__h15556 == 3'd0 || rm__h15556 == 3'd1) || - _theResult____h4607[31:25] == 7'h50 && - rm__h15556 == 3'd2 || - (_theResult____h4607[31:25] == 7'h70 || - _theResult____h4607[31:25] == 7'h78) && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h70 && - rm__h15556 == 3'd1 || - _theResult____h4607[31:25] == 7'b0000001 || - _theResult____h4607[31:25] == 7'h05 || - _theResult____h4607[31:25] == 7'b0001001 || - _theResult____h4607[31:25] == 7'h0D || - _theResult____h4607[31:25] == 7'h2D || - _theResult____h4607[31:25] == 7'h11 && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h11 && - (rm__h15556 == 3'd1 || rm__h15556 == 3'd2) || - _theResult____h4607[31:25] == 7'h61 && - _theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[31:25] == 7'h61 && - (_theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2 || - _theResult____h4607[24:20] == 5'd3) || - _theResult____h4607[31:25] == 7'h69 && - (_theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2) || - _theResult____h4607[31:25] == 7'h69 && - _theResult____h4607[24:20] == 5'd3 || - _theResult____h4607[31:25] == 7'h21 && - _theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[31:25] == 7'h20 && - _theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[31:25] == 7'h15 && - (rm__h15556 == 3'd0 || rm__h15556 == 3'd1) || - _theResult____h4607[31:25] == 7'h51 && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h51 && - (rm__h15556 == 3'd1 || rm__h15556 == 3'd2) || - _theResult____h4607[31:25] == 7'h71 && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h79 && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h71 && rm__h15556 == 3'd1; - endcase - end - always@(_theResult____h4607 or - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1190 or - csr_regfile$read_mstatus) - begin - case (_theResult____h4607[6:0]) - 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194 = - (_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b011) && - csr_regfile$read_mstatus[14:13] != 2'h0; - 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194 = - (_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011) && - csr_regfile$read_mstatus[14:13] != 2'h0; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194 = - (_theResult____h4607[31:27] == 5'b00010 || - _theResult____h4607[31:27] == 5'b00011 || - _theResult____h4607[31:27] == 5'b0 || - _theResult____h4607[31:27] == 5'b00001 || - _theResult____h4607[31:27] == 5'b01100 || - _theResult____h4607[31:27] == 5'b01000 || - _theResult____h4607[31:27] == 5'b00100 || - _theResult____h4607[31:27] == 5'b10000 || - _theResult____h4607[31:27] == 5'b11000 || - _theResult____h4607[31:27] == 5'b10100 || - _theResult____h4607[31:27] == 5'b11100) && - (_theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011); - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194 = - (_theResult____h4607[6:0] == 7'b1010011 || - _theResult____h4607[6:0] == 7'b1000011 || - _theResult____h4607[6:0] == 7'b1000111 || - _theResult____h4607[6:0] == 7'b1001011 || - _theResult____h4607[6:0] == 7'b1001111) && - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1190; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194) - begin - case (_theResult____h4607[6:0]) - 7'b0000011: - CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14 = - _theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b011; - 7'b0100011: - CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14 = - _theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011; - default: CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14 = - _theResult____h4607[6:0] != 7'b0001111 && - _theResult____h4607[6:0] != 7'b1110011 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194; - endcase - end - always@(_theResult____h4607 or - CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1050 or - funct10__h15025) - begin - case (_theResult____h4607[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1050; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202 = - _theResult____h4607[14:12] == 3'b0 || - (_theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101) && - !_theResult____h4607[25]; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202 = - funct10__h15025 == 10'b0 || funct10__h15025 == 10'b0100000000 || - funct10__h15025 == 10'b0000000001 || - funct10__h15025 == 10'b0000000101 || - funct10__h15025 == 10'b0100000101; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202 = - _theResult____h4607[6:0] == 7'b0110111 || - _theResult____h4607[6:0] == 7'b0010111 || - CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14; - endcase - end - always@(rg_cur_priv) - begin - case (rg_cur_priv) - 2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd8; - 2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd9; - default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd11; - endcase - end - always@(_theResult____h4607 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q15) - begin - case (_theResult____h4607[31:20]) - 12'b0: - CASE_theResult__607_BITS_31_TO_20_0b0_CASE_rg__ETC__q16 = - CASE_rg_cur_priv_0b0_8_0b1_9_11__q15; - 12'b000000000001: - CASE_theResult__607_BITS_31_TO_20_0b0_CASE_rg__ETC__q16 = 4'd3; - default: CASE_theResult__607_BITS_31_TO_20_0b0_CASE_rg__ETC__q16 = 4'd2; - endcase - end - always@(_theResult____h4607 or alu_outputs___1_exc_code__h15424) - begin - case (_theResult____h4607[6:0]) - 7'b0000011, - 7'b0001111, - 7'b0010011, - 7'b0010111, - 7'b0011011, - 7'b0100011, - 7'b0110011, - 7'b0110111, - 7'b0111011, - 7'b1100011: - alu_outputs_exc_code__h15680 = 4'd2; - 7'b1100111, 7'b1101111: alu_outputs_exc_code__h15680 = 4'd0; - 7'b1110011: - alu_outputs_exc_code__h15680 = alu_outputs___1_exc_code__h15424; - default: alu_outputs_exc_code__h15680 = 4'd2; - endcase - end - always@(_theResult____h4607 or - rg_cur_priv or - IF_rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7__ETC___d1258) - begin - case (_theResult____h4607[31:20]) - 12'b0, 12'b000000000001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1260 = 4'd11; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1260 = - (rg_cur_priv == 2'b11 && - _theResult____h4607[31:20] == 12'b001100000010) ? - 4'd7 : - IF_rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7__ETC___d1258; - endcase - end - always@(_theResult____h4607) - begin - case (_theResult____h4607[14:12]) - 3'b0: CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17 = 4'd4; - 3'b001: CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17 = 4'd5; - default: CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17 = 4'd11; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1262) - begin - case (_theResult____h4607[14:12]) - 3'b0: - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1262; - 3'b001, 3'b101: - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18 = 4'd2; - 3'b010, 3'b011, 3'b110, 3'b111: - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18 = 4'd3; - 3'd4: CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18 = 4'd11; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1220 or - CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17 or - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1214 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1224 or - funct10__h15025 or - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1270 or - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18) - begin - case (_theResult____h4607[6:0]) - 7'b0000011, 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1220; - 7'b0001111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17; - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1214; - 7'b0010111, 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = 4'd0; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - (_theResult____h4607[14:12] != 3'b0 && - (_theResult____h4607[14:12] != 3'b001 || - _theResult____h4607[25]) && - (_theResult____h4607[14:12] != 3'b101 || - _theResult____h4607[25])) ? - 4'd11 : - 4'd0; - 7'b0100011, 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1224; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - ((_theResult____h4607[31:27] == 5'b00010 || - _theResult____h4607[31:27] == 5'b00011 || - _theResult____h4607[31:27] == 5'b0 || - _theResult____h4607[31:27] == 5'b00001 || - _theResult____h4607[31:27] == 5'b01100 || - _theResult____h4607[31:27] == 5'b01000 || - _theResult____h4607[31:27] == 5'b00100 || - _theResult____h4607[31:27] == 5'b10000 || - _theResult____h4607[31:27] == 5'b11000 || - _theResult____h4607[31:27] == 5'b10100 || - _theResult____h4607[31:27] == 5'b11100) && - (_theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011)) ? - 4'd0 : - 4'd11; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - (funct10__h15025 != 10'b0 && - funct10__h15025 != 10'b0100000000 && - funct10__h15025 != 10'b0000000001 && - funct10__h15025 != 10'b0000000101 && - funct10__h15025 != 10'b0100000101) ? - 4'd11 : - 4'd0; - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111, 7'b1010011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1270; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - 4'd11; - endcase - end - always@(_theResult____h4607 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1043 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697) - begin - case (_theResult____h4607[6:0]) - 7'b1100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1285 = - (_theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b111) ? - 4'd11 : - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 ? - 4'd1 : - 4'd0); - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1285 = 4'd1; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1285 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1043 ? - 4'd0 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282; - endcase - end - always@(_theResult____h4607) - begin - case (_theResult____h4607[6:0]) - 7'b0000011, 7'b0000111: - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19 = 3'd1; - 7'b0010011, 7'b0010111, 7'b0011011, 7'b0110011, 7'b0110111, 7'b0111011: - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19 = 3'd0; - 7'b0100011, 7'b0100111: - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19 = 3'd2; - 7'b0101111: - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19 = 3'd4; - default: CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19 = 3'd5; - endcase - end - always@(_theResult____h4607 or - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19) - begin - case (_theResult____h4607[6:0]) - 7'b1100011, 7'b1100111, 7'b1101111: - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 = 3'd0; - default: IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 = - ((_theResult____h4607[6:0] == 7'b0110011 || - _theResult____h4607[6:0] == 7'b0111011) && - _theResult____h4607[31:25] == 7'b0000001) ? - 3'd3 : - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19; - endcase - end - always@(_theResult____h4607 or - _theResult_____1_fst__h16273 or - rd_val___1__h16241 or - rd_val___1__h16248 or rd_val___1__h16255 or rd_val___1__h16262) - begin - case (_theResult____h4607[14:12]) - 3'b010: _theResult_____1_fst__h16245 = rd_val___1__h16241; - 3'b011: _theResult_____1_fst__h16245 = rd_val___1__h16248; - 3'b100: _theResult_____1_fst__h16245 = rd_val___1__h16255; - 3'b110: _theResult_____1_fst__h16245 = rd_val___1__h16262; - default: _theResult_____1_fst__h16245 = _theResult_____1_fst__h16273; - endcase - end - always@(_theResult____h4607 or - alu_outputs___1_addr__h15141 or - alu_outputs___1_addr__h15117 or - rs1_val_bypassed__h4615 or - alu_outputs___1_addr__h14775 or - alu_outputs___1_addr__h14828 or alu_outputs___1_addr__h14799) - begin - case (_theResult____h4607[6:0]) - 7'b0000011, 7'b0000111: - x_out_data_to_stage2_addr__h14648 = alu_outputs___1_addr__h15117; - 7'b0100011: - x_out_data_to_stage2_addr__h14648 = alu_outputs___1_addr__h15141; - 7'b0101111: x_out_data_to_stage2_addr__h14648 = rs1_val_bypassed__h4615; - 7'b1100011: - x_out_data_to_stage2_addr__h14648 = alu_outputs___1_addr__h14775; - 7'b1100111: - x_out_data_to_stage2_addr__h14648 = alu_outputs___1_addr__h14828; - 7'b1101111: - x_out_data_to_stage2_addr__h14648 = alu_outputs___1_addr__h14799; - default: x_out_data_to_stage2_addr__h14648 = - alu_outputs___1_addr__h15141; - endcase - end - always@(_theResult____h4607 or imem_rg_pc or data_to_stage2_addr__h14637) - begin - case (_theResult____h4607[6:0]) - 7'b1100111, 7'b1101111: - CASE_theResult__607_BITS_6_TO_0_0b1100111_data_ETC__q22 = - data_to_stage2_addr__h14637; - default: CASE_theResult__607_BITS_6_TO_0_0b1100111_data_ETC__q22 = - (_theResult____h4607[6:0] == 7'b1110011 && - _theResult____h4607[14:12] == 3'b0 && - _theResult____h4607[11:7] == 5'd0 && - _theResult____h4607[19:15] == 5'd0 && - _theResult____h4607[31:20] == 12'b000000000001) ? - imem_rg_pc : - 64'd0; - endcase - end - always@(_theResult____h4607 or - frs2_val_bypassed__h4631 or - alu_outputs___1_val2__h15143 or rs2_val_bypassed__h4621) - begin - case (_theResult____h4607[6:0]) - 7'b0100011, 7'b0100111: - CASE_theResult__607_BITS_6_TO_0_0b100011_alu_o_ETC__q23 = - alu_outputs___1_val2__h15143; - 7'b0101111: - CASE_theResult__607_BITS_6_TO_0_0b100011_alu_o_ETC__q23 = - rs2_val_bypassed__h4621; - default: CASE_theResult__607_BITS_6_TO_0_0b100011_alu_o_ETC__q23 = - frs2_val_bypassed__h4631; - endcase - end - always@(_theResult____h4607 or - alu_outputs___1_val1__h15653 or - alu_outputs___1_val1__h14987 or - alu_outputs___1_val1__h15077 or - alu_outputs___1_val1__h15013 or - alu_outputs___1_val1__h15452 or - alu_outputs___1_val1__h15058 or - alu_outputs___1_val1__h15039 or alu_outputs___1_val1__h15428) - begin - case (_theResult____h4607[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h14987; - 7'b0010111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15077; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15013; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15452; - 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15058; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15039; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15428; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15653; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1559 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1432) - begin - case (_theResult____h4607[6:0]) - 7'b1100111, 7'b1101111: - x_out_data_to_stage2_val1__h14649 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1432; - default: x_out_data_to_stage2_val1__h14649 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1559; - endcase - end - always@(x_out_data_to_stage2_instr__h14645 or - x_out_data_to_stage2_val1__h14649) - begin - case (x_out_data_to_stage2_instr__h14645[14:12]) - 3'b010, 3'b011: rs1_val__h23782 = x_out_data_to_stage2_val1__h14649; - default: rs1_val__h23782 = - { 59'd0, x_out_data_to_stage2_instr__h14645[19:15] }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0; - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11; - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_logdelay$EN) - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN; - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_cur_priv$EN) - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN; - if (rg_run_on_reset$EN) - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (stage1_rg_full$EN) - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN; - if (stage2_rg_full$EN) - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN; - if (stage2_rg_resetting$EN) - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY - stage2_rg_resetting$D_IN; - if (stage3_rg_full$EN) - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN; - end - if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN; - if (imem_rg_instr_15_0$EN) - imem_rg_instr_15_0 <= `BSV_ASSIGNMENT_DELAY imem_rg_instr_15_0$D_IN; - if (imem_rg_mstatus_MXR$EN) - imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN; - if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN; - if (imem_rg_priv$EN) - imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN; - if (imem_rg_satp$EN) - imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN; - if (imem_rg_sstatus_SUM$EN) - imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN; - if (imem_rg_tval$EN) - imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_start_CPI_cycles$EN) - rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN; - if (rg_start_CPI_instrs$EN) - rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN; - if (stage2_rg_stage2$EN) - stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN; - if (stage3_rg_stage3$EN) - stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_logdelay = 64'hAAAAAAAAAAAAAAAA; - cfg_verbosity = 4'hA; - imem_rg_f3 = 3'h2; - imem_rg_instr_15_0 = 16'hAAAA; - imem_rg_mstatus_MXR = 1'h0; - imem_rg_pc = 64'hAAAAAAAAAAAAAAAA; - imem_rg_priv = 2'h2; - imem_rg_satp = 64'hAAAAAAAAAAAAAAAA; - imem_rg_sstatus_SUM = 1'h0; - imem_rg_tval = 64'hAAAAAAAAAAAAAAAA; - rg_cur_priv = 2'h2; - rg_mstatus_MXR = 1'h0; - rg_next_pc = 64'hAAAAAAAAAAAAAAAA; - rg_run_on_reset = 1'h0; - rg_sstatus_SUM = 1'h0; - rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA; - rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - stage1_rg_full = 1'h0; - stage2_rg_full = 1'h0; - stage2_rg_resetting = 1'h0; - stage2_rg_stage2 = - 366'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - stage3_rg_full = 1'h0; - stage3_rg_stage3 = 175'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - rg_cur_priv, - csr_regfile$read_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write("MStatus{", - "sd:%0d", - csr_regfile$read_mstatus[14:13] == 2'h3 || - csr_regfile$read_mstatus[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2) - $write(" sxl:%0d uxl:%0d", sxl__h5045, uxl__h5046); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tsr:%0d", csr_regfile$read_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tw:%0d", csr_regfile$read_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tvm:%0d", csr_regfile$read_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mxr:%0d", csr_regfile$read_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" sum:%0d", csr_regfile$read_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mprv:%0d", csr_regfile$read_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" xs:%0d", csr_regfile$read_mstatus[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" fs:%0d", csr_regfile$read_mstatus[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mpp:%0d", csr_regfile$read_mstatus[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" spp:%0d", csr_regfile$read_mstatus[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" pies:%0d_%0d%0d", - csr_regfile$read_mstatus[7], - csr_regfile$read_mstatus[5], - csr_regfile$read_mstatus[4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" ies:%0d_%0d%0d", - csr_regfile$read_mstatus[3], - csr_regfile$read_mstatus[1], - csr_regfile$read_mstatus[0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("Rd %0d ", stage3_rg_stage3[75:71]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("rd_val:%h", stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write("FRd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("FRd %0d ", stage3_rg_stage3[75:71]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("frd_val:%h", stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage2: pc 0x%08h instr 0x%08h priv %0d", - stage2_rg_stage2[363:300], - stage2_rg_stage2[299:268], - stage2_rg_stage2[365:364]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write("Output_Stage2", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[363:300]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("Output_Stage2", " NONPIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write("Output_Stage2", " PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[363:300], - stage2_rg_stage2[299:268], - stage2_rg_stage2[365:364]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - stage2_rg_stage2[267:265] != 3'd0 && - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - (stage2_rg_stage2[267:265] == 3'd0 || - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - stage2_rg_stage2[267:265] != 3'd0 && - stage2_rg_stage2[267:265] != 3'd1 && - stage2_rg_stage2[267:265] != 3'd4 && - stage2_rg_stage2[267:265] != 3'd2 && - stage2_rg_stage2[267:265] != 3'd3) - $write(" fflags: %05b", - "'h%h", - x_out_data_to_stage3_fpr_flags__h6249); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - (stage2_rg_stage2[267:265] == 3'd0 || - stage2_rg_stage2[267:265] == 3'd1 || - stage2_rg_stage2[267:265] == 3'd4 || - stage2_rg_stage2[267:265] == 3'd2 || - stage2_rg_stage2[267:265] == 3'd3)) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - stage2_rg_stage2[267:265] != 3'd0 && - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198) - $write(" frd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6246, - x_out_data_to_stage3_rd_val__h6250); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - (stage2_rg_stage2[267:265] == 3'd0 || - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d232)) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6246, - x_out_data_to_stage3_rd_val__h6250); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", value__h6429); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", x_out_trap_info_exc_code__h6466); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", value__h6490, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", value__h6429); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", x_out_trap_info_exc_code__h6466); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", value__h6490, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == 2'd0) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 != 2'd0) - $write("Rd %0d ", x_out_bypass_rd__h6724); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 != 2'd1) - $write("rd_val:%h", x_out_bypass_rd_val__h6725); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == 2'd0) - $write("FRd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 != 2'd0) - $write("FRd %0d ", x_out_fbypass_rd__h6873); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 != 2'd0 && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 != 2'd1) - $write("frd_val:%h", x_out_fbypass_rd_val__h6874); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage1: pc 0x%08h instr 0x%08h priv %0d", - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write("Output_Stage1", " BUSY pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write("Output_Stage1", " NONPIPE: pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write("Output_Stage1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) - $write("Output_Stage1", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(" PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd0) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd1) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd2) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd3) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd4) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd5) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd6) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd7) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd8) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd9) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd10) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1353) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n", - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(" op_stage2:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == 3'd0) - $write("OP_Stage2_ALU"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == 3'd1) - $write("OP_Stage2_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == 3'd2) - $write("OP_Stage2_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == 3'd3) - $write("OP_Stage2_M"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == 3'd4) - $write("OP_Stage2_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1403) - $write("OP_Stage2_FD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(" rd:%0d\n", x_out_data_to_stage2_rd__h14647); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(" addr:%h val1:%h val2:%h val3:%h}", - x_out_data_to_stage2_addr__h14648, - x_out_data_to_stage2_val1__h14649, - x_out_data_to_stage2_val2__h14650, - x_out_data_to_stage2_val3__h14651); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1603) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1606) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1609) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1612) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1615) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1618) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1621) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1624) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1627) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1630) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1633) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1636) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write("'h%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write("'h%h", x_out_trap_info_exc_code__h18054); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write("'h%h", value__h18109, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647) - $write(" next_pc 0x%08h", x_out_next_pc__h14611); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - value__h6429, - stage2_rg_stage2[299:268], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3134 != 4'd0) - $display(" mcause:0x%0h epc 0x%0h tval:0x%0h new pc 0x%0h, new mstatus 0x%0h", - csr_regfile$csr_trap_actions[65:2], - value__h6429, - value__h6490, - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[129:66]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h14645[19:15], - rs1_val__h23289, - x_out_data_to_stage2_instr__h14645[31:20], - csr_regfile$read_csr[63:0], - x_out_data_to_stage2_instr__h14645[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h14645[19:15], - rs1_val__h23289, - x_out_data_to_stage2_instr__h14645[31:20], - x_out_data_to_stage2_instr__h14645[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_CSRR_S_or_C", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h14645[19:15], - rs1_val__h23782, - x_out_data_to_stage2_instr__h14645[31:20], - csr_regfile$read_csr[63:0], - x_out_data_to_stage2_instr__h14645[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h14645[19:15], - rs1_val__h23782, - x_out_data_to_stage2_instr__h14645[31:20], - x_out_data_to_stage2_instr__h14645[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h14611); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d pc:%0x cur_priv:%0d", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - x_out_next_pc__h14611, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3134 != 4'd0) - $display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d", - csr_regfile$csr_ret_actions[129:66], - csr_regfile$csr_ret_actions[63:0], - csr_regfile$csr_ret_actions[65:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_stage1_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h3134 != 4'd0) - $display(" WFI resume"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_from_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d2002) - $display("%0d: CPU.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x", - csr_regfile$read_csr_mcycle, - csr_regfile$csr_trap_actions[193:130], - x_out_data_to_stage2_instr__h14645); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d2002) - $display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'", - cpi__h28498, - cpifrac__h28499, - delta_CPI_cycles__h28494, - _theResult____h28496); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d2002) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3134 != 4'd0) - $display("%0d: CPU.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", - csr_regfile$read_csr_mcycle, - rg_cur_priv, - csr_regfile$csr_trap_actions[65:2], - imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3134 != 4'd0) - $display(" tval:0x%0h new pc:0x%0h new mstatus:0x%0h", - value__h18109, - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[129:66]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_trap_fetch && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3134 != 4'd0) - $display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", - csr_regfile$read_csr_mcycle, - imem_rg_pc, - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[1:0], - csr_regfile$csr_trap_actions[129:66]); - if (WILL_FIRE_RL_imem_rl_assert_fail) - $display("ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False"); - if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", soc_map$m_pc_reset_value); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h", - csr_regfile$read_csr_mcycle, - soc_map$m_pc_reset_value); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage3_rg_stage3[69]) - $display(" S3.fa_deq: write FRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[75:71], - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - !stage3_rg_stage3[69]) - $display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[75:71], - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write(" S3.enq: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[363:300], - stage2_rg_stage2[299:268], - stage2_rg_stage2[365:364]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[267:265] != 3'd0 && - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[267:265] == 3'd0 || - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[267:265] != 3'd0 && - stage2_rg_stage2[267:265] != 3'd1 && - stage2_rg_stage2[267:265] != 3'd4 && - stage2_rg_stage2[267:265] != 3'd2 && - stage2_rg_stage2[267:265] != 3'd3) - $write(" fflags: %05b", - "'h%h", - x_out_data_to_stage3_fpr_flags__h6249); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[267:265] == 3'd0 || - stage2_rg_stage2[267:265] == 3'd1 || - stage2_rg_stage2[267:265] == 3'd4 || - stage2_rg_stage2[267:265] == 3'd2 || - stage2_rg_stage2[267:265] == 3'd3)) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[267:265] != 3'd0 && - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198) - $write(" frd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6246, - x_out_data_to_stage3_rd_val__h6250); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[267:265] == 3'd0 || - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d232)) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6246, - x_out_data_to_stage3_rd_val__h6250); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[363:300], - stage2_rg_stage2[299:268], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage2.enq (Data_Stage1_to_Stage2)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h14611); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $write("CPU: Bluespec RISC-V Piccolo v3.0"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) $display(" (RV64)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h3134 != 4'd0) - $display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle); - end - // synopsys translate_on -endmodule // mkCPU - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v deleted file mode 100644 index 5a849419..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v +++ /dev/null @@ -1,228 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 64 -// fav_write O 64 -// fv_sie_read O 64 -// fav_sie_write O 64 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 64 -// fav_sie_write_misa I 28 -// fav_sie_write_wordxl I 64 -// EN_reset I 1 -// EN_fav_write I 1 -// EN_fav_sie_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// (fav_sie_write_misa, fav_sie_write_wordxl) -> fav_sie_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIE(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - fv_sie_read, - - fav_sie_write_misa, - fav_sie_write_wordxl, - EN_fav_sie_write, - fav_sie_write); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [63 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [63 : 0] fav_write_wordxl; - input EN_fav_write; - output [63 : 0] fav_write; - - // value method fv_sie_read - output [63 : 0] fv_sie_read; - - // actionvalue method fav_sie_write - input [27 : 0] fav_sie_write_misa; - input [63 : 0] fav_sie_write_wordxl; - input EN_fav_sie_write; - output [63 : 0] fav_sie_write; - - // signals for module outputs - wire [63 : 0] fav_sie_write, fav_write, fv_read, fv_sie_read; - - // register rg_mie - reg [11 : 0] rg_mie; - reg [11 : 0] rg_mie$D_IN; - wire rg_mie$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_sie_write, - CAN_FIRE_fav_write, - CAN_FIRE_reset, - WILL_FIRE_fav_sie_write, - WILL_FIRE_fav_write, - WILL_FIRE_reset; - - // inputs to muxes for submodule ports - wire [11 : 0] MUX_rg_mie$write_1__VAL_3; - - // remaining internal signals - wire [11 : 0] mie__h92, x__h458, x__h883; - wire seie__h123, - seie__h544, - ssie__h117, - ssie__h538, - stie__h120, - stie__h541, - ueie__h122, - ueie__h543, - usie__h116, - usie__h537, - utie__h119, - utie__h540; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 52'd0, rg_mie } ; - - // actionvalue method fav_write - assign fav_write = { 52'd0, mie__h92 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // value method fv_sie_read - assign fv_sie_read = { 52'd0, x__h458 } ; - - // actionvalue method fav_sie_write - assign fav_sie_write = { 52'd0, x__h883 } ; - assign CAN_FIRE_fav_sie_write = 1'd1 ; - assign WILL_FIRE_fav_sie_write = EN_fav_sie_write ; - - // inputs to muxes for submodule ports - assign MUX_rg_mie$write_1__VAL_3 = - { rg_mie[11], - 1'b0, - seie__h544, - ueie__h543, - rg_mie[7], - 1'b0, - stie__h541, - utie__h540, - rg_mie[3], - 1'b0, - ssie__h538, - usie__h537 } ; - - // register rg_mie - always@(EN_fav_write or - mie__h92 or - EN_reset or EN_fav_sie_write or MUX_rg_mie$write_1__VAL_3) - case (1'b1) - EN_fav_write: rg_mie$D_IN = mie__h92; - EN_reset: rg_mie$D_IN = 12'd0; - EN_fav_sie_write: rg_mie$D_IN = MUX_rg_mie$write_1__VAL_3; - default: rg_mie$D_IN = 12'b101010101010 /* unspecified value */ ; - endcase - assign rg_mie$EN = EN_fav_write || EN_fav_sie_write || EN_reset ; - - // remaining internal signals - assign mie__h92 = - { fav_write_wordxl[11], - 1'b0, - seie__h123, - ueie__h122, - fav_write_wordxl[7], - 1'b0, - stie__h120, - utie__h119, - fav_write_wordxl[3], - 1'b0, - ssie__h117, - usie__h116 } ; - assign seie__h123 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign seie__h544 = fav_sie_write_misa[18] && fav_sie_write_wordxl[9] ; - assign ssie__h117 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign ssie__h538 = fav_sie_write_misa[18] && fav_sie_write_wordxl[1] ; - assign stie__h120 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign stie__h541 = fav_sie_write_misa[18] && fav_sie_write_wordxl[5] ; - assign ueie__h122 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign ueie__h543 = fav_sie_write_misa[13] && fav_sie_write_wordxl[8] ; - assign usie__h116 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign usie__h537 = fav_sie_write_misa[13] && fav_sie_write_wordxl[0] ; - assign utie__h119 = fav_write_misa[13] && fav_write_wordxl[4] ; - assign utie__h540 = fav_sie_write_misa[13] && fav_sie_write_wordxl[4] ; - assign x__h458 = - { 2'd0, rg_mie[9:8], 2'd0, rg_mie[5:4], 2'd0, rg_mie[1:0] } ; - assign x__h883 = - { 2'd0, - seie__h544, - ueie__h543, - 2'd0, - stie__h541, - utie__h540, - 2'd0, - ssie__h538, - usie__h537 } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_mie = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIE - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v deleted file mode 100644 index 6ba79983..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v +++ /dev/null @@ -1,374 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 64 -// fav_write O 64 -// fv_sip_read O 64 -// fav_sip_write O 64 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 64 -// fav_sip_write_misa I 28 -// fav_sip_write_wordxl I 64 -// m_external_interrupt_req_req I 1 reg -// s_external_interrupt_req_req I 1 reg -// software_interrupt_req_req I 1 reg -// timer_interrupt_req_req I 1 reg -// EN_reset I 1 -// EN_fav_write I 1 -// EN_fav_sip_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// (fav_sip_write_misa, fav_sip_write_wordxl) -> fav_sip_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIP(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - fv_sip_read, - - fav_sip_write_misa, - fav_sip_write_wordxl, - EN_fav_sip_write, - fav_sip_write, - - m_external_interrupt_req_req, - - s_external_interrupt_req_req, - - software_interrupt_req_req, - - timer_interrupt_req_req); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [63 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [63 : 0] fav_write_wordxl; - input EN_fav_write; - output [63 : 0] fav_write; - - // value method fv_sip_read - output [63 : 0] fv_sip_read; - - // actionvalue method fav_sip_write - input [27 : 0] fav_sip_write_misa; - input [63 : 0] fav_sip_write_wordxl; - input EN_fav_sip_write; - output [63 : 0] fav_sip_write; - - // action method m_external_interrupt_req - input m_external_interrupt_req_req; - - // action method s_external_interrupt_req - input s_external_interrupt_req_req; - - // action method software_interrupt_req - input software_interrupt_req_req; - - // action method timer_interrupt_req - input timer_interrupt_req_req; - - // signals for module outputs - wire [63 : 0] fav_sip_write, fav_write, fv_read, fv_sip_read; - - // register rg_meip - reg rg_meip; - wire rg_meip$D_IN, rg_meip$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_seip - reg rg_seip; - wire rg_seip$D_IN, rg_seip$EN; - - // register rg_ssip - reg rg_ssip; - reg rg_ssip$D_IN; - wire rg_ssip$EN; - - // register rg_stip - reg rg_stip; - wire rg_stip$D_IN, rg_stip$EN; - - // register rg_ueip - reg rg_ueip; - reg rg_ueip$D_IN; - wire rg_ueip$EN; - - // register rg_usip - reg rg_usip; - reg rg_usip$D_IN; - wire rg_usip$EN; - - // register rg_utip - reg rg_utip; - wire rg_utip$D_IN, rg_utip$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_sip_write, - CAN_FIRE_fav_write, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_reset, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_fav_sip_write, - WILL_FIRE_fav_write, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_reset, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // remaining internal signals - wire [11 : 0] new_mip__h528, new_mip__h946; - wire seip__h562, - ssip__h566, - ssip__h986, - stip__h564, - ueip__h563, - ueip__h985, - usip__h567, - usip__h987, - utip__h565; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 52'd0, new_mip__h528 } ; - - // actionvalue method fav_write - assign fav_write = { 52'd0, new_mip__h946 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // value method fv_sip_read - assign fv_sip_read = - { 54'd0, - rg_seip, - rg_ueip, - 2'b0, - rg_stip, - rg_utip, - 2'b0, - rg_ssip, - rg_usip } ; - - // actionvalue method fav_sip_write - assign fav_sip_write = - { 54'd0, - rg_seip, - ueip__h985, - 2'b0, - rg_stip, - rg_utip, - 2'b0, - ssip__h986, - usip__h987 } ; - assign CAN_FIRE_fav_sip_write = 1'd1 ; - assign WILL_FIRE_fav_sip_write = EN_fav_sip_write ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // register rg_meip - assign rg_meip$D_IN = m_external_interrupt_req_req ; - assign rg_meip$EN = 1'b1 ; - - // register rg_msip - assign rg_msip$D_IN = software_interrupt_req_req ; - assign rg_msip$EN = 1'b1 ; - - // register rg_mtip - assign rg_mtip$D_IN = timer_interrupt_req_req ; - assign rg_mtip$EN = 1'b1 ; - - // register rg_seip - assign rg_seip$D_IN = s_external_interrupt_req_req ; - assign rg_seip$EN = 1'b1 ; - - // register rg_ssip - always@(EN_reset or - EN_fav_write or ssip__h566 or EN_fav_sip_write or ssip__h986) - case (1'b1) - EN_reset: rg_ssip$D_IN = 1'd0; - EN_fav_write: rg_ssip$D_IN = ssip__h566; - EN_fav_sip_write: rg_ssip$D_IN = ssip__h986; - default: rg_ssip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_ssip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_stip - assign rg_stip$D_IN = !EN_reset && stip__h564 ; - assign rg_stip$EN = EN_fav_write || EN_reset ; - - // register rg_ueip - always@(EN_reset or - EN_fav_write or ueip__h563 or EN_fav_sip_write or ueip__h985) - case (1'b1) - EN_reset: rg_ueip$D_IN = 1'd0; - EN_fav_write: rg_ueip$D_IN = ueip__h563; - EN_fav_sip_write: rg_ueip$D_IN = ueip__h985; - default: rg_ueip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_ueip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_usip - always@(EN_reset or - EN_fav_write or usip__h567 or EN_fav_sip_write or usip__h987) - case (1'b1) - EN_reset: rg_usip$D_IN = 1'd0; - EN_fav_write: rg_usip$D_IN = usip__h567; - EN_fav_sip_write: rg_usip$D_IN = usip__h987; - default: rg_usip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_usip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_utip - assign rg_utip$D_IN = !EN_reset && utip__h565 ; - assign rg_utip$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign new_mip__h528 = - { rg_meip, - 1'b0, - rg_seip, - rg_ueip, - rg_mtip, - 1'b0, - rg_stip, - rg_utip, - rg_msip, - 1'b0, - rg_ssip, - rg_usip } ; - assign new_mip__h946 = - { rg_meip, - 1'b0, - seip__h562, - ueip__h563, - rg_mtip, - 1'b0, - stip__h564, - utip__h565, - rg_msip, - 1'b0, - ssip__h566, - usip__h567 } ; - assign seip__h562 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssip__h566 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign ssip__h986 = fav_sip_write_misa[18] && fav_sip_write_wordxl[1] ; - assign stip__h564 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueip__h563 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign ueip__h985 = fav_sip_write_misa[13] && fav_sip_write_wordxl[8] ; - assign usip__h567 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign usip__h987 = fav_sip_write_misa[13] && fav_sip_write_wordxl[0] ; - assign utip__h565 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN; - if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN; - if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN; - if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN; - if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN; - if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_meip = 1'h0; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_seip = 1'h0; - rg_ssip = 1'h0; - rg_stip = 1'h0; - rg_ueip = 1'h0; - rg_usip = 1'h0; - rg_utip = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIP - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v deleted file mode 100644 index 78196620..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v +++ /dev/null @@ -1,3658 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_csr O 65 -// read_csr_port2 O 65 -// mav_read_csr O 65 -// mav_csr_write O 64 -// read_frm O 3 reg -// read_misa O 28 const -// read_mstatus O 64 reg -// read_sstatus O 64 -// read_ustatus O 64 -// read_satp O 64 reg -// csr_trap_actions O 194 -// RDY_csr_trap_actions O 1 const -// csr_ret_actions O 130 -// RDY_csr_ret_actions O 1 const -// read_csr_minstret O 64 reg -// read_csr_mcycle O 64 reg -// read_csr_mtime O 64 reg -// access_permitted_1 O 1 -// access_permitted_2 O 1 -// csr_counter_read_fault O 1 -// csr_mip_read O 64 -// interrupt_pending O 5 -// wfi_resume O 1 -// nmi_pending O 1 reg -// RDY_debug O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// read_csr_csr_addr I 12 -// read_csr_port2_csr_addr I 12 -// mav_read_csr_csr_addr I 12 -// mav_csr_write_csr_addr I 12 -// mav_csr_write_word I 64 -// ma_update_fcsr_fflags_flags I 5 -// ma_update_mstatus_fs_fs I 2 -// csr_trap_actions_from_priv I 2 -// csr_trap_actions_pc I 64 -// csr_trap_actions_nmi I 1 -// csr_trap_actions_interrupt I 1 -// csr_trap_actions_exc_code I 4 -// csr_trap_actions_xtval I 64 -// csr_ret_actions_from_priv I 2 -// access_permitted_1_priv I 2 -// access_permitted_1_csr_addr I 12 -// access_permitted_1_read_not_write I 1 -// access_permitted_2_priv I 2 -// access_permitted_2_csr_addr I 12 -// access_permitted_2_read_not_write I 1 -// csr_counter_read_fault_priv I 2 -// csr_counter_read_fault_csr_addr I 12 -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// interrupt_pending_cur_priv I 2 -// nmi_req_set_not_clear I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_ma_update_fcsr_fflags I 1 -// EN_ma_update_mstatus_fs I 1 -// EN_csr_minstret_incr I 1 -// EN_debug I 1 unused -// EN_mav_read_csr I 1 unused -// EN_mav_csr_write I 1 -// EN_csr_trap_actions I 1 -// EN_csr_ret_actions I 1 -// -// Combinational paths from inputs to outputs: -// read_csr_csr_addr -> read_csr -// read_csr_port2_csr_addr -> read_csr_port2 -// (access_permitted_1_priv, -// access_permitted_1_csr_addr, -// access_permitted_1_read_not_write) -> access_permitted_1 -// (access_permitted_2_priv, -// access_permitted_2_csr_addr, -// access_permitted_2_read_not_write) -> access_permitted_2 -// (csr_counter_read_fault_priv, -// csr_counter_read_fault_csr_addr) -> csr_counter_read_fault -// interrupt_pending_cur_priv -> interrupt_pending -// mav_read_csr_csr_addr -> mav_read_csr -// (mav_csr_write_csr_addr, -// mav_csr_write_word, -// EN_mav_csr_write) -> mav_csr_write -// (csr_trap_actions_from_priv, -// csr_trap_actions_nmi, -// csr_trap_actions_interrupt, -// csr_trap_actions_exc_code) -> csr_trap_actions -// csr_ret_actions_from_priv -> csr_ret_actions -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_csr_csr_addr, - read_csr, - - read_csr_port2_csr_addr, - read_csr_port2, - - mav_read_csr_csr_addr, - EN_mav_read_csr, - mav_read_csr, - - mav_csr_write_csr_addr, - mav_csr_write_word, - EN_mav_csr_write, - mav_csr_write, - - read_frm, - - ma_update_fcsr_fflags_flags, - EN_ma_update_fcsr_fflags, - - ma_update_mstatus_fs_fs, - EN_ma_update_mstatus_fs, - - read_misa, - - read_mstatus, - - read_sstatus, - - read_ustatus, - - read_satp, - - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_nmi, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval, - EN_csr_trap_actions, - csr_trap_actions, - RDY_csr_trap_actions, - - csr_ret_actions_from_priv, - EN_csr_ret_actions, - csr_ret_actions, - RDY_csr_ret_actions, - - read_csr_minstret, - - EN_csr_minstret_incr, - - read_csr_mcycle, - - read_csr_mtime, - - access_permitted_1_priv, - access_permitted_1_csr_addr, - access_permitted_1_read_not_write, - access_permitted_1, - - access_permitted_2_priv, - access_permitted_2_csr_addr, - access_permitted_2_read_not_write, - access_permitted_2, - - csr_counter_read_fault_priv, - csr_counter_read_fault_csr_addr, - csr_counter_read_fault, - - csr_mip_read, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - interrupt_pending_cur_priv, - interrupt_pending, - - wfi_resume, - - nmi_req_set_not_clear, - - nmi_pending, - - EN_debug, - RDY_debug); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_csr - input [11 : 0] read_csr_csr_addr; - output [64 : 0] read_csr; - - // value method read_csr_port2 - input [11 : 0] read_csr_port2_csr_addr; - output [64 : 0] read_csr_port2; - - // actionvalue method mav_read_csr - input [11 : 0] mav_read_csr_csr_addr; - input EN_mav_read_csr; - output [64 : 0] mav_read_csr; - - // actionvalue method mav_csr_write - input [11 : 0] mav_csr_write_csr_addr; - input [63 : 0] mav_csr_write_word; - input EN_mav_csr_write; - output [63 : 0] mav_csr_write; - - // value method read_frm - output [2 : 0] read_frm; - - // action method ma_update_fcsr_fflags - input [4 : 0] ma_update_fcsr_fflags_flags; - input EN_ma_update_fcsr_fflags; - - // action method ma_update_mstatus_fs - input [1 : 0] ma_update_mstatus_fs_fs; - input EN_ma_update_mstatus_fs; - - // value method read_misa - output [27 : 0] read_misa; - - // value method read_mstatus - output [63 : 0] read_mstatus; - - // value method read_sstatus - output [63 : 0] read_sstatus; - - // value method read_ustatus - output [63 : 0] read_ustatus; - - // value method read_satp - output [63 : 0] read_satp; - - // actionvalue method csr_trap_actions - input [1 : 0] csr_trap_actions_from_priv; - input [63 : 0] csr_trap_actions_pc; - input csr_trap_actions_nmi; - input csr_trap_actions_interrupt; - input [3 : 0] csr_trap_actions_exc_code; - input [63 : 0] csr_trap_actions_xtval; - input EN_csr_trap_actions; - output [193 : 0] csr_trap_actions; - output RDY_csr_trap_actions; - - // actionvalue method csr_ret_actions - input [1 : 0] csr_ret_actions_from_priv; - input EN_csr_ret_actions; - output [129 : 0] csr_ret_actions; - output RDY_csr_ret_actions; - - // value method read_csr_minstret - output [63 : 0] read_csr_minstret; - - // action method csr_minstret_incr - input EN_csr_minstret_incr; - - // value method read_csr_mcycle - output [63 : 0] read_csr_mcycle; - - // value method read_csr_mtime - output [63 : 0] read_csr_mtime; - - // value method access_permitted_1 - input [1 : 0] access_permitted_1_priv; - input [11 : 0] access_permitted_1_csr_addr; - input access_permitted_1_read_not_write; - output access_permitted_1; - - // value method access_permitted_2 - input [1 : 0] access_permitted_2_priv; - input [11 : 0] access_permitted_2_csr_addr; - input access_permitted_2_read_not_write; - output access_permitted_2; - - // value method csr_counter_read_fault - input [1 : 0] csr_counter_read_fault_priv; - input [11 : 0] csr_counter_read_fault_csr_addr; - output csr_counter_read_fault; - - // value method csr_mip_read - output [63 : 0] csr_mip_read; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // value method interrupt_pending - input [1 : 0] interrupt_pending_cur_priv; - output [4 : 0] interrupt_pending; - - // value method wfi_resume - output wfi_resume; - - // action method nmi_req - input nmi_req_set_not_clear; - - // value method nmi_pending - output nmi_pending; - - // action method debug - input EN_debug; - output RDY_debug; - - // signals for module outputs - wire [193 : 0] csr_trap_actions; - wire [129 : 0] csr_ret_actions; - wire [64 : 0] mav_read_csr, read_csr, read_csr_port2; - wire [63 : 0] csr_mip_read, - mav_csr_write, - read_csr_mcycle, - read_csr_minstret, - read_csr_mtime, - read_mstatus, - read_satp, - read_sstatus, - read_ustatus; - wire [27 : 0] read_misa; - wire [4 : 0] interrupt_pending; - wire [2 : 0] read_frm; - wire RDY_csr_ret_actions, - RDY_csr_trap_actions, - RDY_debug, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - access_permitted_1, - access_permitted_2, - csr_counter_read_fault, - nmi_pending, - wfi_resume; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register csr_mstatus_rg_mstatus - reg [63 : 0] csr_mstatus_rg_mstatus; - reg [63 : 0] csr_mstatus_rg_mstatus$D_IN; - wire csr_mstatus_rg_mstatus$EN; - - // register rg_dcsr - reg [31 : 0] rg_dcsr; - wire [31 : 0] rg_dcsr$D_IN; - wire rg_dcsr$EN; - - // register rg_dpc - reg [63 : 0] rg_dpc; - wire [63 : 0] rg_dpc$D_IN; - wire rg_dpc$EN; - - // register rg_dscratch0 - reg [63 : 0] rg_dscratch0; - wire [63 : 0] rg_dscratch0$D_IN; - wire rg_dscratch0$EN; - - // register rg_dscratch1 - reg [63 : 0] rg_dscratch1; - wire [63 : 0] rg_dscratch1$D_IN; - wire rg_dscratch1$EN; - - // register rg_fflags - reg [4 : 0] rg_fflags; - reg [4 : 0] rg_fflags$D_IN; - wire rg_fflags$EN; - - // register rg_frm - reg [2 : 0] rg_frm; - wire [2 : 0] rg_frm$D_IN; - wire rg_frm$EN; - - // register rg_mcause - reg [4 : 0] rg_mcause; - reg [4 : 0] rg_mcause$D_IN; - wire rg_mcause$EN; - - // register rg_mcounteren - reg [2 : 0] rg_mcounteren; - wire [2 : 0] rg_mcounteren$D_IN; - wire rg_mcounteren$EN; - - // register rg_mcycle - reg [63 : 0] rg_mcycle; - wire [63 : 0] rg_mcycle$D_IN; - wire rg_mcycle$EN; - - // register rg_medeleg - reg [15 : 0] rg_medeleg; - wire [15 : 0] rg_medeleg$D_IN; - wire rg_medeleg$EN; - - // register rg_mepc - reg [63 : 0] rg_mepc; - wire [63 : 0] rg_mepc$D_IN; - wire rg_mepc$EN; - - // register rg_mideleg - reg [11 : 0] rg_mideleg; - wire [11 : 0] rg_mideleg$D_IN; - wire rg_mideleg$EN; - - // register rg_minstret - reg [63 : 0] rg_minstret; - wire [63 : 0] rg_minstret$D_IN; - wire rg_minstret$EN; - - // register rg_mscratch - reg [63 : 0] rg_mscratch; - wire [63 : 0] rg_mscratch$D_IN; - wire rg_mscratch$EN; - - // register rg_mtval - reg [63 : 0] rg_mtval; - wire [63 : 0] rg_mtval$D_IN; - wire rg_mtval$EN; - - // register rg_mtvec - reg [62 : 0] rg_mtvec; - wire [62 : 0] rg_mtvec$D_IN; - wire rg_mtvec$EN; - - // register rg_nmi - reg rg_nmi; - wire rg_nmi$D_IN, rg_nmi$EN; - - // register rg_nmi_vector - reg [63 : 0] rg_nmi_vector; - wire [63 : 0] rg_nmi_vector$D_IN; - wire rg_nmi_vector$EN; - - // register rg_satp - reg [63 : 0] rg_satp; - wire [63 : 0] rg_satp$D_IN; - wire rg_satp$EN; - - // register rg_scause - reg [4 : 0] rg_scause; - reg [4 : 0] rg_scause$D_IN; - wire rg_scause$EN; - - // register rg_sepc - reg [63 : 0] rg_sepc; - wire [63 : 0] rg_sepc$D_IN; - wire rg_sepc$EN; - - // register rg_sscratch - reg [63 : 0] rg_sscratch; - wire [63 : 0] rg_sscratch$D_IN; - wire rg_sscratch$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_stval - reg [63 : 0] rg_stval; - wire [63 : 0] rg_stval$D_IN; - wire rg_stval$EN; - - // register rg_stvec - reg [62 : 0] rg_stvec; - wire [62 : 0] rg_stvec$D_IN; - wire rg_stvec$EN; - - // register rg_tdata1 - reg [63 : 0] rg_tdata1; - wire [63 : 0] rg_tdata1$D_IN; - wire rg_tdata1$EN; - - // register rg_tdata2 - reg [63 : 0] rg_tdata2; - wire [63 : 0] rg_tdata2$D_IN; - wire rg_tdata2$EN; - - // register rg_tdata3 - reg [63 : 0] rg_tdata3; - wire [63 : 0] rg_tdata3$D_IN; - wire rg_tdata3$EN; - - // register rg_tselect - reg [63 : 0] rg_tselect; - wire [63 : 0] rg_tselect$D_IN; - wire rg_tselect$EN; - - // ports of submodule csr_mie - wire [63 : 0] csr_mie$fav_sie_write, - csr_mie$fav_sie_write_wordxl, - csr_mie$fav_write, - csr_mie$fav_write_wordxl, - csr_mie$fv_read, - csr_mie$fv_sie_read; - wire [27 : 0] csr_mie$fav_sie_write_misa, csr_mie$fav_write_misa; - wire csr_mie$EN_fav_sie_write, csr_mie$EN_fav_write, csr_mie$EN_reset; - - // ports of submodule csr_mip - wire [63 : 0] csr_mip$fav_sip_write, - csr_mip$fav_sip_write_wordxl, - csr_mip$fav_write, - csr_mip$fav_write_wordxl, - csr_mip$fv_read, - csr_mip$fv_sip_read; - wire [27 : 0] csr_mip$fav_sip_write_misa, csr_mip$fav_write_misa; - wire csr_mip$EN_fav_sip_write, - csr_mip$EN_fav_write, - csr_mip$EN_reset, - csr_mip$m_external_interrupt_req_req, - csr_mip$s_external_interrupt_req_req, - csr_mip$software_interrupt_req_req, - csr_mip$timer_interrupt_req_req; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mtvec_reset_value, - soc_map$m_nmivec_reset_value; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_mcycle_incr, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_upd_minstret_csrrx, - CAN_FIRE_RL_rl_upd_minstret_incr, - CAN_FIRE_csr_minstret_incr, - CAN_FIRE_csr_ret_actions, - CAN_FIRE_csr_trap_actions, - CAN_FIRE_debug, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_ma_update_fcsr_fflags, - CAN_FIRE_ma_update_mstatus_fs, - CAN_FIRE_mav_csr_write, - CAN_FIRE_mav_read_csr, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_rl_mcycle_incr, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_upd_minstret_csrrx, - WILL_FIRE_RL_rl_upd_minstret_incr, - WILL_FIRE_csr_minstret_incr, - WILL_FIRE_csr_ret_actions, - WILL_FIRE_csr_trap_actions, - WILL_FIRE_debug, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_ma_update_fcsr_fflags, - WILL_FIRE_ma_update_mstatus_fs, - WILL_FIRE_mav_csr_write, - WILL_FIRE_mav_read_csr, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_2, - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4, - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5, - MUX_rg_minstret$write_1__VAL_1, - MUX_rg_minstret$write_1__VAL_2; - wire [62 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; - wire [15 : 0] MUX_rg_medeleg$write_1__VAL_1; - wire [4 : 0] MUX_rg_fflags$write_1__VAL_3, - MUX_rg_mcause$write_1__VAL_2, - MUX_rg_mcause$write_1__VAL_3; - wire [2 : 0] MUX_rg_frm$write_1__VAL_1; - wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_5, - MUX_rg_fflags$write_1__SEL_2, - MUX_rg_frm$write_1__SEL_1, - MUX_rg_mcause$write_1__SEL_2, - MUX_rg_mcause$write_1__SEL_3, - MUX_rg_mcounteren$write_1__SEL_1, - MUX_rg_medeleg$write_1__SEL_1, - MUX_rg_mideleg$write_1__SEL_1, - MUX_rg_mtvec$write_1__SEL_1, - MUX_rg_satp$write_1__SEL_1, - MUX_rg_scause$write_1__SEL_2, - MUX_rg_scause$write_1__SEL_3, - MUX_rg_sepc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2, - MUX_rg_stval$write_1__SEL_1, - MUX_rg_stvec$write_1__SEL_1, - MUX_rg_tdata1$write_1__SEL_1, - MUX_rw_minstret$wset_1__SEL_1; - - // remaining internal signals - reg [63 : 0] IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731, - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291, - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511, - y_avValue_fst__h9500; - reg [61 : 0] CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1; - reg CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2, - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742, - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845; - wire [63 : 0] IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275, - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477, - _theResult___fst__h13593, - _theResult___fst__h13794, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267, - exc_pc___1__h12586, - exc_pc__h12512, - mask__h11532, - mask__h11549, - mask__h13614, - mask__h13631, - result__h9129, - v__h11328, - v__h5882, - v__h6026, - v__h6140, - v__h7518, - v__h7554, - v__h8224, - v__h8286, - v__h8442, - val__h11533, - val__h11550, - val__h13632, - vector_offset__h12513, - wordxl1__h7649, - x__h10300, - x__h11531, - x__h11544, - x__h11561, - x__h13437, - x__h13438, - x__h13613, - x__h13626, - x__h13643, - y__h11545, - y__h11562, - y__h13627, - y__h13644, - y_avValue_fst__h12469, - y_avValue_fst__h12486, - y_avValue_snd_snd__h12559; - wire [22 : 0] fixed_up_val_23__h11372, - fixed_up_val_23__h13500, - fixed_up_val_23__h6191, - fixed_up_val_23__h7690, - fixed_up_val_23__h9712; - wire [5 : 0] ie_from_x__h13577, - ie_to_x__h11449, - pie_from_x__h13578, - pie_to_x__h11450; - wire [3 : 0] IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923, - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925, - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926, - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928, - exc_code__h13279; - wire [1 : 0] IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, - _theResult____h15189, - _theResult____h15401, - _theResult____h15613, - _theResult____h15825, - _theResult____h16037, - _theResult____h16249, - _theResult____h16461, - _theResult____h16673, - _theResult____h16885, - _theResult___fst__h11461, - new_priv__h11323, - to_y__h13793; - wire NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598, - NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701, - NOT_cfg_verbosity_read__42_ULE_1_43___d944, - NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910, - NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848, - NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875, - NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902, - NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883, - NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856, - NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892, - NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865, - NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901, - NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874, - NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402, - b__h11548, - b__h13630, - csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821, - csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745, - csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811, - csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788, - csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755, - csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832, - csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799, - csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766, - csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810, - csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777, - csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301, - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453, - deleg_bit___1__h11470, - deleg_bit___1__h11485, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817, - mav_csr_write_csr_addr_ULE_0x33F___d739, - mav_csr_write_csr_addr_ULE_0xB1F___d735, - mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940, - mav_csr_write_csr_addr_ULT_0x323___d738, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861, - mav_csr_write_csr_addr_ULT_0xB03___d734, - sd__h11371, - sd__h13499, - sd__h7689, - sd__h9711; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_csr - assign read_csr = - { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || - read_csr_csr_addr == 12'h001 || - read_csr_csr_addr == 12'h002 || - read_csr_csr_addr == 12'h003 || - read_csr_csr_addr == 12'hC00 || - read_csr_csr_addr == 12'hC02 || - read_csr_csr_addr == 12'h100 || - read_csr_csr_addr == 12'h102 || - read_csr_csr_addr == 12'h103 || - read_csr_csr_addr == 12'h104 || - read_csr_csr_addr == 12'h105 || - read_csr_csr_addr == 12'h106 || - read_csr_csr_addr == 12'h140 || - read_csr_csr_addr == 12'h141 || - read_csr_csr_addr == 12'h142 || - read_csr_csr_addr == 12'h143 || - read_csr_csr_addr == 12'h144 || - read_csr_csr_addr == 12'h180 || - read_csr_csr_addr == 12'h302 || - read_csr_csr_addr == 12'h303 || - read_csr_csr_addr == 12'hF11 || - read_csr_csr_addr == 12'hF12 || - read_csr_csr_addr == 12'hF13 || - read_csr_csr_addr == 12'hF14 || - read_csr_csr_addr == 12'h300 || - read_csr_csr_addr == 12'h301 || - read_csr_csr_addr == 12'h304 || - read_csr_csr_addr == 12'h305 || - read_csr_csr_addr == 12'h306 || - read_csr_csr_addr == 12'h340 || - read_csr_csr_addr == 12'h341 || - read_csr_csr_addr == 12'h342 || - read_csr_csr_addr == 12'h343 || - read_csr_csr_addr == 12'h344 || - read_csr_csr_addr == 12'hB00 || - read_csr_csr_addr == 12'hB02 || - read_csr_csr_addr == 12'h7A0 || - read_csr_csr_addr == 12'h7A1 || - read_csr_csr_addr == 12'h7A2 || - read_csr_csr_addr == 12'h7A3, - (read_csr_csr_addr >= 12'hC03 && - read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hB03 && - read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'h323 && - read_csr_csr_addr <= 12'h33F) ? - 64'd0 : - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 } ; - - // value method read_csr_port2 - assign read_csr_port2 = - { read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F || - read_csr_port2_csr_addr == 12'h001 || - read_csr_port2_csr_addr == 12'h002 || - read_csr_port2_csr_addr == 12'h003 || - read_csr_port2_csr_addr == 12'hC00 || - read_csr_port2_csr_addr == 12'hC02 || - read_csr_port2_csr_addr == 12'h100 || - read_csr_port2_csr_addr == 12'h102 || - read_csr_port2_csr_addr == 12'h103 || - read_csr_port2_csr_addr == 12'h104 || - read_csr_port2_csr_addr == 12'h105 || - read_csr_port2_csr_addr == 12'h106 || - read_csr_port2_csr_addr == 12'h140 || - read_csr_port2_csr_addr == 12'h141 || - read_csr_port2_csr_addr == 12'h142 || - read_csr_port2_csr_addr == 12'h143 || - read_csr_port2_csr_addr == 12'h144 || - read_csr_port2_csr_addr == 12'h180 || - read_csr_port2_csr_addr == 12'h302 || - read_csr_port2_csr_addr == 12'h303 || - read_csr_port2_csr_addr == 12'hF11 || - read_csr_port2_csr_addr == 12'hF12 || - read_csr_port2_csr_addr == 12'hF13 || - read_csr_port2_csr_addr == 12'hF14 || - read_csr_port2_csr_addr == 12'h300 || - read_csr_port2_csr_addr == 12'h301 || - read_csr_port2_csr_addr == 12'h304 || - read_csr_port2_csr_addr == 12'h305 || - read_csr_port2_csr_addr == 12'h306 || - read_csr_port2_csr_addr == 12'h340 || - read_csr_port2_csr_addr == 12'h341 || - read_csr_port2_csr_addr == 12'h342 || - read_csr_port2_csr_addr == 12'h343 || - read_csr_port2_csr_addr == 12'h344 || - read_csr_port2_csr_addr == 12'hB00 || - read_csr_port2_csr_addr == 12'hB02 || - read_csr_port2_csr_addr == 12'h7A0 || - read_csr_port2_csr_addr == 12'h7A1 || - read_csr_port2_csr_addr == 12'h7A2 || - read_csr_port2_csr_addr == 12'h7A3, - (read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F) ? - 64'd0 : - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 } ; - - // actionvalue method mav_read_csr - assign mav_read_csr = - { mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F || - mav_read_csr_csr_addr == 12'h001 || - mav_read_csr_csr_addr == 12'h002 || - mav_read_csr_csr_addr == 12'h003 || - mav_read_csr_csr_addr == 12'hC00 || - mav_read_csr_csr_addr == 12'hC02 || - mav_read_csr_csr_addr == 12'h100 || - mav_read_csr_csr_addr == 12'h102 || - mav_read_csr_csr_addr == 12'h103 || - mav_read_csr_csr_addr == 12'h104 || - mav_read_csr_csr_addr == 12'h105 || - mav_read_csr_csr_addr == 12'h106 || - mav_read_csr_csr_addr == 12'h140 || - mav_read_csr_csr_addr == 12'h141 || - mav_read_csr_csr_addr == 12'h142 || - mav_read_csr_csr_addr == 12'h143 || - mav_read_csr_csr_addr == 12'h144 || - mav_read_csr_csr_addr == 12'h180 || - mav_read_csr_csr_addr == 12'h302 || - mav_read_csr_csr_addr == 12'h303 || - mav_read_csr_csr_addr == 12'hF11 || - mav_read_csr_csr_addr == 12'hF12 || - mav_read_csr_csr_addr == 12'hF13 || - mav_read_csr_csr_addr == 12'hF14 || - mav_read_csr_csr_addr == 12'h300 || - mav_read_csr_csr_addr == 12'h301 || - mav_read_csr_csr_addr == 12'h304 || - mav_read_csr_csr_addr == 12'h305 || - mav_read_csr_csr_addr == 12'h306 || - mav_read_csr_csr_addr == 12'h340 || - mav_read_csr_csr_addr == 12'h341 || - mav_read_csr_csr_addr == 12'h342 || - mav_read_csr_csr_addr == 12'h343 || - mav_read_csr_csr_addr == 12'h344 || - mav_read_csr_csr_addr == 12'hB00 || - mav_read_csr_csr_addr == 12'hB02 || - mav_read_csr_csr_addr == 12'h7A0 || - mav_read_csr_csr_addr == 12'h7A1 || - mav_read_csr_csr_addr == 12'h7A2 || - mav_read_csr_csr_addr == 12'h7A3, - (mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F) ? - 64'd0 : - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 } ; - assign CAN_FIRE_mav_read_csr = 1'd1 ; - assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; - - // actionvalue method mav_csr_write - assign mav_csr_write = - (!mav_csr_write_csr_addr_ULT_0xB03___d734 && - mav_csr_write_csr_addr_ULE_0xB1F___d735 || - !mav_csr_write_csr_addr_ULT_0x323___d738 && - mav_csr_write_csr_addr_ULE_0x33F___d739) ? - 64'd0 : - y_avValue_fst__h9500 ; - assign CAN_FIRE_mav_csr_write = 1'd1 ; - assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; - - // value method read_frm - assign read_frm = rg_frm ; - - // action method ma_update_fcsr_fflags - assign CAN_FIRE_ma_update_fcsr_fflags = 1'd1 ; - assign WILL_FIRE_ma_update_fcsr_fflags = EN_ma_update_fcsr_fflags ; - - // action method ma_update_mstatus_fs - assign CAN_FIRE_ma_update_mstatus_fs = 1'd1 ; - assign WILL_FIRE_ma_update_mstatus_fs = EN_ma_update_mstatus_fs ; - - // value method read_misa - assign read_misa = 28'd135532845 ; - - // value method read_mstatus - assign read_mstatus = csr_mstatus_rg_mstatus ; - - // value method read_sstatus - assign read_sstatus = - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] } ; - - // value method read_ustatus - assign read_ustatus = - { 59'd0, - csr_mstatus_rg_mstatus[4], - 3'd0, - csr_mstatus_rg_mstatus[0] } ; - - // value method read_satp - assign read_satp = rg_satp ; - - // actionvalue method csr_trap_actions - assign csr_trap_actions = - { x__h10300, x__h13437, x__h13438, new_priv__h11323 } ; - assign RDY_csr_trap_actions = 1'd1 ; - assign CAN_FIRE_csr_trap_actions = 1'd1 ; - assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; - - // actionvalue method csr_ret_actions - assign csr_ret_actions = - (csr_ret_actions_from_priv == 2'b11) ? - { rg_mepc, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[12:11], - _theResult___fst__h13593 } : - { rg_sepc, to_y__h13793, _theResult___fst__h13794 } ; - assign RDY_csr_ret_actions = 1'd1 ; - assign CAN_FIRE_csr_ret_actions = 1'd1 ; - assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; - - // value method read_csr_minstret - assign read_csr_minstret = rg_minstret ; - - // action method csr_minstret_incr - assign CAN_FIRE_csr_minstret_incr = 1'd1 ; - assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; - - // value method read_csr_mcycle - assign read_csr_mcycle = rg_mcycle ; - - // value method read_csr_mtime - assign read_csr_mtime = rg_mcycle ; - - // value method access_permitted_1 - assign access_permitted_1 = - NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598 && - (access_permitted_1_read_not_write || - access_permitted_1_csr_addr[11:10] != 2'b11) ; - - // value method access_permitted_2 - assign access_permitted_2 = - NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701 && - (access_permitted_2_read_not_write || - access_permitted_2_csr_addr[11:10] != 2'b11) ; - - // value method csr_counter_read_fault - assign csr_counter_read_fault = - (csr_counter_read_fault_priv == 2'b01 || - csr_counter_read_fault_priv == 2'b0) && - (csr_counter_read_fault_csr_addr == 12'hC00 && - !rg_mcounteren[0] || - csr_counter_read_fault_csr_addr == 12'hC01 && - !rg_mcounteren[1] || - csr_counter_read_fault_csr_addr == 12'hC02 && - !rg_mcounteren[2] || - csr_counter_read_fault_csr_addr >= 12'hC03 && - csr_counter_read_fault_csr_addr <= 12'hC1F) ; - - // value method csr_mip_read - assign csr_mip_read = csr_mip$fv_read ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // value method interrupt_pending - assign interrupt_pending = - { csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811 || - csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821 || - csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832, - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928 } ; - - // value method wfi_resume - assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 64'd0 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // value method nmi_pending - assign nmi_pending = rg_nmi ; - - // action method debug - assign RDY_debug = 1'd1 ; - assign CAN_FIRE_debug = 1'd1 ; - assign WILL_FIRE_debug = EN_debug ; - - // submodule csr_mie - mkCSR_MIE csr_mie(.CLK(CLK), - .RST_N(RST_N), - .fav_sie_write_misa(csr_mie$fav_sie_write_misa), - .fav_sie_write_wordxl(csr_mie$fav_sie_write_wordxl), - .fav_write_misa(csr_mie$fav_write_misa), - .fav_write_wordxl(csr_mie$fav_write_wordxl), - .EN_reset(csr_mie$EN_reset), - .EN_fav_write(csr_mie$EN_fav_write), - .EN_fav_sie_write(csr_mie$EN_fav_sie_write), - .fv_read(csr_mie$fv_read), - .fav_write(csr_mie$fav_write), - .fv_sie_read(csr_mie$fv_sie_read), - .fav_sie_write(csr_mie$fav_sie_write)); - - // submodule csr_mip - mkCSR_MIP csr_mip(.CLK(CLK), - .RST_N(RST_N), - .fav_sip_write_misa(csr_mip$fav_sip_write_misa), - .fav_sip_write_wordxl(csr_mip$fav_sip_write_wordxl), - .fav_write_misa(csr_mip$fav_write_misa), - .fav_write_wordxl(csr_mip$fav_write_wordxl), - .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), - .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), - .software_interrupt_req_req(csr_mip$software_interrupt_req_req), - .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), - .EN_reset(csr_mip$EN_reset), - .EN_fav_write(csr_mip$EN_fav_write), - .EN_fav_sip_write(csr_mip$EN_fav_sip_write), - .fv_read(csr_mip$fv_read), - .fav_write(csr_mip$fav_write), - .fv_sip_read(csr_mip$fv_sip_read), - .fav_sip_write(csr_mip$fav_sip_write)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), - .m_nmivec_reset_value(soc_map$m_nmivec_reset_value)); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = !rg_state ; - assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_mcycle_incr - assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; - assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; - - // rule RL_rl_upd_minstret_csrrx - assign CAN_FIRE_RL_rl_upd_minstret_csrrx = - MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; - assign WILL_FIRE_RL_rl_upd_minstret_csrrx = - CAN_FIRE_RL_rl_upd_minstret_csrrx ; - - // rule RL_rl_upd_minstret_incr - assign CAN_FIRE_RL_rl_upd_minstret_incr = - !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; - assign WILL_FIRE_RL_rl_upd_minstret_incr = - CAN_FIRE_RL_rl_upd_minstret_incr ; - - // inputs to muxes for submodule ports - assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 ; - assign MUX_rg_fflags$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 ; - assign MUX_rg_frm$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 ; - assign MUX_rg_mcause$write_1__SEL_2 = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) ; - assign MUX_rg_mcause$write_1__SEL_3 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 ; - assign MUX_rg_mcounteren$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 ; - assign MUX_rg_medeleg$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 ; - assign MUX_rg_mideleg$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 ; - assign MUX_rg_mtvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 ; - assign MUX_rg_satp$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 ; - assign MUX_rg_scause$write_1__SEL_2 = - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h11323 == 2'b01 ; - assign MUX_rg_scause$write_1__SEL_3 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 ; - assign MUX_rg_sepc$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; - assign MUX_rg_stval$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 ; - assign MUX_rg_stvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 ; - assign MUX_rg_tdata1$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 ; - assign MUX_rw_minstret$wset_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851 ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 = - { sd__h13499, 40'd5120, fixed_up_val_23__h13500 } ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 = - { sd__h9711, 40'd5120, fixed_up_val_23__h9712 } ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_5 = - { sd__h7689, - 40'd5120, - (mav_csr_write_csr_addr == 12'h100) ? - fixed_up_val_23__h6191 : - fixed_up_val_23__h7690 } ; - assign MUX_rg_fflags$write_1__VAL_3 = - rg_fflags | ma_update_fcsr_fflags_flags ; - assign MUX_rg_frm$write_1__VAL_1 = - (mav_csr_write_csr_addr == 12'h002) ? - mav_csr_write_word[2:0] : - mav_csr_write_word[7:5] ; - assign MUX_rg_mcause$write_1__VAL_2 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - exc_code__h13279 } ; - assign MUX_rg_mcause$write_1__VAL_3 = - { mav_csr_write_word[63], mav_csr_write_word[3:0] } ; - assign MUX_rg_medeleg$write_1__VAL_1 = - { mav_csr_write_word[15], - 1'd0, - mav_csr_write_word[13:12], - 2'd0, - mav_csr_write_word[9:0] } ; - assign MUX_rg_minstret$write_1__VAL_1 = - MUX_rw_minstret$wset_1__SEL_1 ? mav_csr_write_word : 64'd0 ; - assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; - assign MUX_rg_mtvec$write_1__VAL_1 = - { mav_csr_write_word[63:2], mav_csr_write_word[0] } ; - assign MUX_rg_mtvec$write_1__VAL_2 = - { soc_map$m_mtvec_reset_value[63:2], - soc_map$m_mtvec_reset_value[0] } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register csr_mstatus_rg_mstatus - always@(WILL_FIRE_RL_rl_reset_start or - EN_csr_ret_actions or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 or - EN_csr_trap_actions or - v__h11328 or - EN_ma_update_mstatus_fs or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 or - MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: - csr_mstatus_rg_mstatus$D_IN = 64'h0000000A00002000; - EN_csr_ret_actions: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_2; - EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = v__h11328; - EN_ma_update_mstatus_fs: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4; - MUX_csr_mstatus_rg_mstatus$write_1__SEL_5: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5; - default: csr_mstatus_rg_mstatus$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign csr_mstatus_rg_mstatus$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 || - EN_csr_trap_actions || - EN_ma_update_mstatus_fs || - EN_csr_ret_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_dcsr - assign rg_dcsr$D_IN = 32'h0 ; - assign rg_dcsr$EN = 1'b0 ; - - // register rg_dpc - assign rg_dpc$D_IN = 64'h0 ; - assign rg_dpc$EN = 1'b0 ; - - // register rg_dscratch0 - assign rg_dscratch0$D_IN = 64'h0 ; - assign rg_dscratch0$EN = 1'b0 ; - - // register rg_dscratch1 - assign rg_dscratch1$D_IN = 64'h0 ; - assign rg_dscratch1$EN = 1'b0 ; - - // register rg_fflags - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_fflags$write_1__SEL_2 or - mav_csr_write_word or - EN_ma_update_fcsr_fflags or MUX_rg_fflags$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_fflags$D_IN = 5'd0; - MUX_rg_fflags$write_1__SEL_2: rg_fflags$D_IN = mav_csr_write_word[4:0]; - EN_ma_update_fcsr_fflags: rg_fflags$D_IN = MUX_rg_fflags$write_1__VAL_3; - default: rg_fflags$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_fflags$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 || - EN_ma_update_fcsr_fflags || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_frm - assign rg_frm$D_IN = - MUX_rg_frm$write_1__SEL_1 ? MUX_rg_frm$write_1__VAL_1 : 3'd0 ; - assign rg_frm$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_mcause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - MUX_rg_mcause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; - MUX_rg_mcause$write_1__SEL_2: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; - MUX_rg_mcause$write_1__SEL_3: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_mcause$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcounteren - assign rg_mcounteren$D_IN = - MUX_rg_mcounteren$write_1__SEL_1 ? - mav_csr_write_word[2:0] : - 3'd0 ; - assign rg_mcounteren$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcycle - assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; - assign rg_mcycle$EN = 1'd1 ; - - // register rg_medeleg - assign rg_medeleg$D_IN = - MUX_rg_medeleg$write_1__SEL_1 ? - MUX_rg_medeleg$write_1__VAL_1 : - 16'd0 ; - assign rg_medeleg$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mepc - assign rg_mepc$D_IN = - MUX_rg_mcause$write_1__SEL_2 ? - csr_trap_actions_pc : - mav_csr_write_word ; - assign rg_mepc$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841 ; - - // register rg_mideleg - assign rg_mideleg$D_IN = - MUX_rg_mideleg$write_1__SEL_1 ? - mav_csr_write_word[11:0] : - 12'd0 ; - assign rg_mideleg$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_minstret - assign rg_minstret$D_IN = - WILL_FIRE_RL_rl_upd_minstret_csrrx ? - MUX_rg_minstret$write_1__VAL_1 : - MUX_rg_minstret$write_1__VAL_2 ; - assign rg_minstret$EN = - WILL_FIRE_RL_rl_upd_minstret_csrrx || - WILL_FIRE_RL_rl_upd_minstret_incr ; - - // register rg_mscratch - assign rg_mscratch$D_IN = mav_csr_write_word ; - assign rg_mscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 ; - - // register rg_mtval - assign rg_mtval$D_IN = - MUX_rg_mcause$write_1__SEL_2 ? - csr_trap_actions_xtval : - mav_csr_write_word ; - assign rg_mtval$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845 ; - - // register rg_mtvec - assign rg_mtvec$D_IN = - MUX_rg_mtvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_mtvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_nmi - assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ; - assign rg_nmi$EN = 1'b1 ; - - // register rg_nmi_vector - assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value ; - assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_satp - assign rg_satp$D_IN = - MUX_rg_satp$write_1__SEL_1 ? mav_csr_write_word : 64'd0 ; - assign rg_satp$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_scause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_scause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - MUX_rg_scause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_scause$D_IN = 5'd0; - MUX_rg_scause$write_1__SEL_2: - rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_2; - MUX_rg_scause$write_1__SEL_3: - rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_scause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_scause$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h11323 == 2'b01 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_sepc - assign rg_sepc$D_IN = - MUX_rg_sepc$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_pc ; - assign rg_sepc$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h11323 == 2'b01 ; - - // register rg_sscratch - assign rg_sscratch$D_IN = mav_csr_write_word ; - assign rg_sscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808 ; - - // register rg_state - assign rg_state$D_IN = !EN_server_reset_request_put ; - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; - - // register rg_stval - assign rg_stval$D_IN = - MUX_rg_stval$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_xtval ; - assign rg_stval$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h11323 == 2'b01 ; - - // register rg_stvec - assign rg_stvec$D_IN = - MUX_rg_stvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_stvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata1 - assign rg_tdata1$D_IN = - MUX_rg_tdata1$write_1__SEL_1 ? result__h9129 : 64'd0 ; - assign rg_tdata1$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata2 - assign rg_tdata2$D_IN = mav_csr_write_word ; - assign rg_tdata2$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859 ; - - // register rg_tdata3 - assign rg_tdata3$D_IN = mav_csr_write_word ; - assign rg_tdata3$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861 ; - - // register rg_tselect - assign rg_tselect$D_IN = 64'd0 ; - assign rg_tselect$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853 || - WILL_FIRE_RL_rl_reset_start ; - - // submodule csr_mie - assign csr_mie$fav_sie_write_misa = 28'd135532845 ; - assign csr_mie$fav_sie_write_wordxl = mav_csr_write_word ; - assign csr_mie$fav_write_misa = 28'd135532845 ; - assign csr_mie$fav_write_wordxl = mav_csr_write_word ; - assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mie$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833 ; - assign csr_mie$EN_fav_sie_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801 ; - - // submodule csr_mip - assign csr_mip$fav_sip_write_misa = 28'd135532845 ; - assign csr_mip$fav_sip_write_wordxl = mav_csr_write_word ; - assign csr_mip$fav_write_misa = 28'd135532845 ; - assign csr_mip$fav_write_wordxl = mav_csr_write_word ; - assign csr_mip$m_external_interrupt_req_req = - m_external_interrupt_req_set_not_clear ; - assign csr_mip$s_external_interrupt_req_req = - s_external_interrupt_req_set_not_clear ; - assign csr_mip$software_interrupt_req_req = - software_interrupt_req_set_not_clear ; - assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; - assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mip$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847 ; - assign csr_mip$EN_fav_sip_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275 = - (new_priv__h11323 == 2'b11) ? - { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[63:13], - csr_trap_actions_from_priv, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[10:0] } : - { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[63:9], - csr_trap_actions_from_priv[0], - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[7:0] } ; - assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923 = - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && - NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 && - NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865) ? - 4'd9 : - ((NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && - NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856) ? - 4'd7 : - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 ? - 4'd3 : - 4'd11)) ; - assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925 = - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && - NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883) ? - 4'd5 : - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 ? - 4'd1 : - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923) ; - assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926 = - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && - NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 && - NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892) ? - 4'd8 : - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925 ; - assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928 = - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 && - NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910) ? - 4'd4 : - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 ? - 4'd0 : - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926) ; - assign IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774 = - (csr_mstatus_rg_mstatus[12:11] == 2'b10) ? - 2'b01 : - csr_mstatus_rg_mstatus[12:11] ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477 = - (csr_ret_actions_from_priv == 2'b11) ? - _theResult___fst__h13593 : - _theResult___fst__h13794 ; - assign NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598 = - (access_permitted_1_csr_addr >= 12'hC03 && - access_permitted_1_csr_addr <= 12'hC1F || - access_permitted_1_csr_addr >= 12'hB03 && - access_permitted_1_csr_addr <= 12'hB1F || - access_permitted_1_csr_addr >= 12'h323 && - access_permitted_1_csr_addr <= 12'h33F || - access_permitted_1_csr_addr == 12'h001 || - access_permitted_1_csr_addr == 12'h002 || - access_permitted_1_csr_addr == 12'h003 || - access_permitted_1_csr_addr == 12'hC00 || - access_permitted_1_csr_addr == 12'hC02 || - access_permitted_1_csr_addr == 12'h100 || - access_permitted_1_csr_addr == 12'h102 || - access_permitted_1_csr_addr == 12'h103 || - access_permitted_1_csr_addr == 12'h104 || - access_permitted_1_csr_addr == 12'h105 || - access_permitted_1_csr_addr == 12'h106 || - access_permitted_1_csr_addr == 12'h140 || - access_permitted_1_csr_addr == 12'h141 || - access_permitted_1_csr_addr == 12'h142 || - access_permitted_1_csr_addr == 12'h143 || - access_permitted_1_csr_addr == 12'h144 || - access_permitted_1_csr_addr == 12'h180 || - access_permitted_1_csr_addr == 12'h302 || - access_permitted_1_csr_addr == 12'h303 || - access_permitted_1_csr_addr == 12'hF11 || - access_permitted_1_csr_addr == 12'hF12 || - access_permitted_1_csr_addr == 12'hF13 || - access_permitted_1_csr_addr == 12'hF14 || - access_permitted_1_csr_addr == 12'h300 || - access_permitted_1_csr_addr == 12'h301 || - access_permitted_1_csr_addr == 12'h304 || - access_permitted_1_csr_addr == 12'h305 || - access_permitted_1_csr_addr == 12'h306 || - access_permitted_1_csr_addr == 12'h340 || - access_permitted_1_csr_addr == 12'h341 || - access_permitted_1_csr_addr == 12'h342 || - access_permitted_1_csr_addr == 12'h343 || - access_permitted_1_csr_addr == 12'h344 || - access_permitted_1_csr_addr == 12'hB00 || - access_permitted_1_csr_addr == 12'hB02 || - access_permitted_1_csr_addr == 12'h7A0 || - access_permitted_1_csr_addr == 12'h7A1 || - access_permitted_1_csr_addr == 12'h7A2 || - access_permitted_1_csr_addr == 12'h7A3) && - access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && - (access_permitted_1_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701 = - (access_permitted_2_csr_addr >= 12'hC03 && - access_permitted_2_csr_addr <= 12'hC1F || - access_permitted_2_csr_addr >= 12'hB03 && - access_permitted_2_csr_addr <= 12'hB1F || - access_permitted_2_csr_addr >= 12'h323 && - access_permitted_2_csr_addr <= 12'h33F || - access_permitted_2_csr_addr == 12'h001 || - access_permitted_2_csr_addr == 12'h002 || - access_permitted_2_csr_addr == 12'h003 || - access_permitted_2_csr_addr == 12'hC00 || - access_permitted_2_csr_addr == 12'hC02 || - access_permitted_2_csr_addr == 12'h100 || - access_permitted_2_csr_addr == 12'h102 || - access_permitted_2_csr_addr == 12'h103 || - access_permitted_2_csr_addr == 12'h104 || - access_permitted_2_csr_addr == 12'h105 || - access_permitted_2_csr_addr == 12'h106 || - access_permitted_2_csr_addr == 12'h140 || - access_permitted_2_csr_addr == 12'h141 || - access_permitted_2_csr_addr == 12'h142 || - access_permitted_2_csr_addr == 12'h143 || - access_permitted_2_csr_addr == 12'h144 || - access_permitted_2_csr_addr == 12'h180 || - access_permitted_2_csr_addr == 12'h302 || - access_permitted_2_csr_addr == 12'h303 || - access_permitted_2_csr_addr == 12'hF11 || - access_permitted_2_csr_addr == 12'hF12 || - access_permitted_2_csr_addr == 12'hF13 || - access_permitted_2_csr_addr == 12'hF14 || - access_permitted_2_csr_addr == 12'h300 || - access_permitted_2_csr_addr == 12'h301 || - access_permitted_2_csr_addr == 12'h304 || - access_permitted_2_csr_addr == 12'h305 || - access_permitted_2_csr_addr == 12'h306 || - access_permitted_2_csr_addr == 12'h340 || - access_permitted_2_csr_addr == 12'h341 || - access_permitted_2_csr_addr == 12'h342 || - access_permitted_2_csr_addr == 12'h343 || - access_permitted_2_csr_addr == 12'h344 || - access_permitted_2_csr_addr == 12'hB00 || - access_permitted_2_csr_addr == 12'hB02 || - access_permitted_2_csr_addr == 12'h7A0 || - access_permitted_2_csr_addr == 12'h7A1 || - access_permitted_2_csr_addr == 12'h7A2 || - access_permitted_2_csr_addr == 12'h7A3) && - access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && - (access_permitted_2_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_cfg_verbosity_read__42_ULE_1_43___d944 = cfg_verbosity > 4'd1 ; - assign NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910 = - !csr_mip$fv_read[0] || !csr_mie$fv_read[0] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 = - !csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 = - NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && - NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 && - NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865 && - NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874 ; - assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 = - NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && - NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 && - NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892 && - NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901 ; - assign NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 = - !csr_mip$fv_read[1] || !csr_mie$fv_read[1] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 = - !csr_mip$fv_read[3] || !csr_mie$fv_read[3] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892 = - !csr_mip$fv_read[5] || !csr_mie$fv_read[5] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865 = - !csr_mip$fv_read[7] || !csr_mie$fv_read[7] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901 = - !csr_mip$fv_read[8] || !csr_mie$fv_read[8] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874 = - !csr_mip$fv_read[9] || !csr_mie$fv_read[9] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402 = - !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h13279 != 4'd0 && - exc_code__h13279 != 4'd1 && - exc_code__h13279 != 4'd2 && - exc_code__h13279 != 4'd3 && - exc_code__h13279 != 4'd4 && - exc_code__h13279 != 4'd5 && - exc_code__h13279 != 4'd6 && - exc_code__h13279 != 4'd7 && - exc_code__h13279 != 4'd8 && - exc_code__h13279 != 4'd9 && - exc_code__h13279 != 4'd10 && - exc_code__h13279 != 4'd11 ; - assign _theResult____h15189 = rg_mideleg[11] ? 2'b01 : 2'b11 ; - assign _theResult____h15401 = rg_mideleg[3] ? 2'b01 : 2'b11 ; - assign _theResult____h15613 = rg_mideleg[7] ? 2'b01 : 2'b11 ; - assign _theResult____h15825 = rg_mideleg[9] ? 2'b01 : 2'b11 ; - assign _theResult____h16037 = rg_mideleg[1] ? 2'b01 : 2'b11 ; - assign _theResult____h16249 = rg_mideleg[5] ? 2'b01 : 2'b11 ; - assign _theResult____h16461 = rg_mideleg[8] ? 2'b01 : 2'b11 ; - assign _theResult____h16673 = rg_mideleg[0] ? 2'b01 : 2'b11 ; - assign _theResult____h16885 = rg_mideleg[4] ? 2'b01 : 2'b11 ; - assign _theResult___fst__h11461 = - (csr_trap_actions_interrupt ? - deleg_bit___1__h11470 : - deleg_bit___1__h11485) ? - 2'b01 : - 2'b11 ; - assign _theResult___fst__h13593 = - { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[63:13], - 2'd0, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[10:0] } ; - assign _theResult___fst__h13794 = - { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[63:9], - 1'd0, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[7:0] } ; - assign b__h11548 = csr_mstatus_rg_mstatus[ie_to_x__h11449] ; - assign b__h13630 = csr_mstatus_rg_mstatus[pie_from_x__h13578] ; - assign csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821 = - csr_mip$fv_read[0] && csr_mie$fv_read[0] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745 = - csr_mip$fv_read[11] && csr_mie$fv_read[11] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811 = - csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745 || - csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755 || - csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766 || - csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777 || - csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788 || - csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799 || - csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810 ; - assign csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788 = - csr_mip$fv_read[1] && csr_mie$fv_read[1] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755 = - csr_mip$fv_read[3] && csr_mie$fv_read[3] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832 = - csr_mip$fv_read[4] && csr_mie$fv_read[4] && - (interrupt_pending_cur_priv < _theResult____h16885 || - interrupt_pending_cur_priv == _theResult____h16885 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799 = - csr_mip$fv_read[5] && csr_mie$fv_read[5] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766 = - csr_mip$fv_read[7] && csr_mie$fv_read[7] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810 = - csr_mip$fv_read[8] && csr_mie$fv_read[8] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777 = - csr_mip$fv_read[9] && csr_mie$fv_read[9] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470 = - x__h13626 | mask__h13614 ; - assign csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267 = - x__h11544 | val__h11533 ; - assign csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301 = - csr_trap_actions_interrupt && !csr_trap_actions_nmi && - CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 ; - assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453 = - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 != 4'd0 && - exc_code__h13279 != 4'd1 && - exc_code__h13279 != 4'd2 && - exc_code__h13279 != 4'd3 && - exc_code__h13279 != 4'd4 && - exc_code__h13279 != 4'd5 && - exc_code__h13279 != 4'd6 && - exc_code__h13279 != 4'd7 && - exc_code__h13279 != 4'd8 && - exc_code__h13279 != 4'd9 && - exc_code__h13279 != 4'd11 && - exc_code__h13279 != 4'd12 && - exc_code__h13279 != 4'd13 && - exc_code__h13279 != 4'd15 ; - assign deleg_bit___1__h11470 = rg_mideleg[csr_trap_actions_exc_code] ; - assign deleg_bit___1__h11485 = rg_medeleg[csr_trap_actions_exc_code] ; - assign exc_code__h13279 = - csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; - assign exc_pc___1__h12586 = exc_pc__h12512 + vector_offset__h12513 ; - assign exc_pc__h12512 = - csr_trap_actions_nmi ? - rg_nmi_vector : - y_avValue_snd_snd__h12559 ; - assign fixed_up_val_23__h11372 = - { IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[22:17], - 2'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13], - (IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[12:11] == - 2'b10) ? - 2'b01 : - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[12:11], - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[10:5], - 1'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[3:1], - 1'd0 } ; - assign fixed_up_val_23__h13500 = - { IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[22:17], - 2'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[14:13], - (IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[12:11] == - 2'b10) ? - 2'b01 : - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[12:11], - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[10:5], - 1'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[3:1], - 1'd0 } ; - assign fixed_up_val_23__h6191 = - { csr_mstatus_rg_mstatus[22:20], - mav_csr_write_word[19:18], - csr_mstatus_rg_mstatus[17], - 2'd0, - mav_csr_write_word[14:13], - IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, - csr_mstatus_rg_mstatus[10:9], - mav_csr_write_word[8], - csr_mstatus_rg_mstatus[7:6], - mav_csr_write_word[5], - 1'd0, - csr_mstatus_rg_mstatus[3:2], - mav_csr_write_word[1], - 1'd0 } ; - assign fixed_up_val_23__h7690 = - { mav_csr_write_word[22:17], - 2'd0, - mav_csr_write_word[14:13], - (mav_csr_write_word[12:11] == 2'b10) ? - 2'b01 : - mav_csr_write_word[12:11], - mav_csr_write_word[10:5], - 1'd0, - mav_csr_write_word[3:1], - 1'd0 } ; - assign fixed_up_val_23__h9712 = - { csr_mstatus_rg_mstatus[22:17], - 2'd0, - ma_update_mstatus_fs_fs, - IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, - csr_mstatus_rg_mstatus[10:5], - 1'd0, - csr_mstatus_rg_mstatus[3:1], - 1'd0 } ; - assign ie_from_x__h13577 = { 4'd0, csr_ret_actions_from_priv } ; - assign ie_to_x__h11449 = { 4'd0, new_priv__h11323 } ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 = - interrupt_pending_cur_priv == _theResult____h15189 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 = - interrupt_pending_cur_priv == _theResult____h15401 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 = - interrupt_pending_cur_priv == _theResult____h15613 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 = - interrupt_pending_cur_priv == _theResult____h15825 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 = - interrupt_pending_cur_priv == _theResult____h16037 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 = - interrupt_pending_cur_priv == _theResult____h16249 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 = - interrupt_pending_cur_priv == _theResult____h16461 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 = - interrupt_pending_cur_priv == _theResult____h16673 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 = - interrupt_pending_cur_priv < _theResult____h15189 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 = - interrupt_pending_cur_priv < _theResult____h15401 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 = - interrupt_pending_cur_priv < _theResult____h15613 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 = - interrupt_pending_cur_priv < _theResult____h15825 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 = - interrupt_pending_cur_priv < _theResult____h16037 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 = - interrupt_pending_cur_priv < _theResult____h16249 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 = - interrupt_pending_cur_priv < _theResult____h16461 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 = - interrupt_pending_cur_priv < _theResult____h16673 ; - assign mask__h11532 = 64'd1 << ie_to_x__h11449 ; - assign mask__h11549 = 64'd1 << pie_to_x__h11450 ; - assign mask__h13614 = 64'd1 << pie_from_x__h13578 ; - assign mask__h13631 = 64'd1 << ie_from_x__h13577 ; - assign mav_csr_write_csr_addr_ULE_0x33F___d739 = - mav_csr_write_csr_addr <= 12'h33F ; - assign mav_csr_write_csr_addr_ULE_0xB1F___d735 = - mav_csr_write_csr_addr <= 12'hB1F ; - assign mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940 = - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr != 12'h001 && - mav_csr_write_csr_addr != 12'h002 && - mav_csr_write_csr_addr != 12'h003 && - mav_csr_write_csr_addr != 12'h100 && - mav_csr_write_csr_addr != 12'h102 && - mav_csr_write_csr_addr != 12'h103 && - mav_csr_write_csr_addr != 12'h104 && - mav_csr_write_csr_addr != 12'h105 && - mav_csr_write_csr_addr != 12'h106 && - mav_csr_write_csr_addr != 12'h140 && - mav_csr_write_csr_addr != 12'h141 && - mav_csr_write_csr_addr != 12'h142 && - mav_csr_write_csr_addr != 12'h143 && - mav_csr_write_csr_addr != 12'h144 && - mav_csr_write_csr_addr != 12'h180 && - mav_csr_write_csr_addr != 12'h302 && - mav_csr_write_csr_addr != 12'h303 && - mav_csr_write_csr_addr != 12'hF11 && - mav_csr_write_csr_addr != 12'hF12 && - mav_csr_write_csr_addr != 12'hF13 && - mav_csr_write_csr_addr != 12'hF14 && - mav_csr_write_csr_addr != 12'h300 && - mav_csr_write_csr_addr != 12'h301 && - mav_csr_write_csr_addr != 12'h304 && - mav_csr_write_csr_addr != 12'h305 && - mav_csr_write_csr_addr != 12'h306 && - mav_csr_write_csr_addr != 12'h340 && - mav_csr_write_csr_addr != 12'h341 && - mav_csr_write_csr_addr != 12'h342 && - mav_csr_write_csr_addr != 12'h343 && - mav_csr_write_csr_addr != 12'h344 && - mav_csr_write_csr_addr != 12'hB00 && - mav_csr_write_csr_addr != 12'hB02 && - mav_csr_write_csr_addr != 12'h7A0 && - mav_csr_write_csr_addr != 12'h7A1 && - mav_csr_write_csr_addr != 12'h7A2 && - mav_csr_write_csr_addr != 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0x323___d738 = - mav_csr_write_csr_addr < 12'h323 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - (mav_csr_write_csr_addr == 12'h001 || - mav_csr_write_csr_addr == 12'h003) ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - (mav_csr_write_csr_addr == 12'h002 || - mav_csr_write_csr_addr == 12'h003) ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - (mav_csr_write_csr_addr == 12'h100 || - mav_csr_write_csr_addr == 12'h300) ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h104 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h105 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h140 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h141 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h142 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h143 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h144 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h180 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h302 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h303 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h304 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h305 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h306 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h340 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h341 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h342 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h343 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h344 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'hB02 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h7A0 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h7A1 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h7A2 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0xB03___d734 = - mav_csr_write_csr_addr < 12'hB03 ; - assign new_priv__h11323 = - csr_trap_actions_nmi ? - 2'b11 : - ((csr_trap_actions_from_priv == 2'b11) ? - csr_trap_actions_from_priv : - _theResult___fst__h11461) ; - assign pie_from_x__h13578 = { 4'd1, csr_ret_actions_from_priv } ; - assign pie_to_x__h11450 = { 4'd1, new_priv__h11323 } ; - assign result__h9129 = { 4'd0, mav_csr_write_word[59:0] } ; - assign sd__h11371 = - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13] == - 2'h3 ; - assign sd__h13499 = - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[14:13] == - 2'h3 ; - assign sd__h7689 = mav_csr_write_word[14:13] == 2'h3 ; - assign sd__h9711 = ma_update_mstatus_fs_fs == 2'h3 ; - assign to_y__h13793 = - { 1'b0, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[8] } ; - assign v__h11328 = { sd__h11371, 40'd5120, fixed_up_val_23__h11372 } ; - assign v__h5882 = { 59'd0, mav_csr_write_word[4:0] } ; - assign v__h6026 = { 56'd0, mav_csr_write_word[7:0] } ; - assign v__h6140 = - { sd__h7689, - 43'd8192, - mav_csr_write_word[19:18], - 3'd0, - mav_csr_write_word[14:13], - 4'd0, - mav_csr_write_word[8], - 2'd0, - mav_csr_write_word[5], - 3'd0, - mav_csr_write_word[1], - 1'd0 } ; - assign v__h7518 = - { 48'd0, - mav_csr_write_word[15], - 1'd0, - mav_csr_write_word[13:12], - 2'd0, - mav_csr_write_word[9:0] } ; - assign v__h7554 = { 52'd0, mav_csr_write_word[11:0] } ; - assign v__h8224 = - { mav_csr_write_word[63:2], 1'b0, mav_csr_write_word[0] } ; - assign v__h8286 = { 61'd0, mav_csr_write_word[2:0] } ; - assign v__h8442 = - { mav_csr_write_word[63], 59'd0, mav_csr_write_word[3:0] } ; - assign val__h11533 = 64'd0 << ie_to_x__h11449 ; - assign val__h11550 = { 63'd0, b__h11548 } << pie_to_x__h11450 ; - assign val__h13632 = { 63'd0, b__h13630 } << ie_from_x__h13577 ; - assign vector_offset__h12513 = { 58'd0, csr_trap_actions_exc_code, 2'd0 } ; - assign wordxl1__h7649 = { sd__h7689, 40'd5120, fixed_up_val_23__h7690 } ; - assign x__h10300 = - csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301 ? - exc_pc___1__h12586 : - exc_pc__h12512 ; - assign x__h11531 = x__h11561 | val__h11550 ; - assign x__h11544 = x__h11531 & y__h11545 ; - assign x__h11561 = csr_mstatus_rg_mstatus & y__h11562 ; - assign x__h13437 = - (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) ? - v__h11328 : - y_avValue_fst__h12486 ; - assign x__h13438 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - 59'd0, - exc_code__h13279 } ; - assign x__h13613 = x__h13643 | val__h13632 ; - assign x__h13626 = x__h13613 & y__h13627 ; - assign x__h13643 = csr_mstatus_rg_mstatus & y__h13644 ; - assign y__h11545 = ~mask__h11532 ; - assign y__h11562 = ~mask__h11549 ; - assign y__h13627 = ~mask__h13614 ; - assign y__h13644 = ~mask__h13631 ; - assign y_avValue_fst__h12469 = - { sd__h11371, - 43'd8192, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[19:18], - 3'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13], - 4'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[8], - 2'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[5], - 3'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[1], - 1'd0 } ; - assign y_avValue_fst__h12486 = - (new_priv__h11323 == 2'b01) ? y_avValue_fst__h12469 : v__h11328 ; - assign y_avValue_snd_snd__h12559 = - { CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1, - 2'd0 } ; - always@(mav_csr_write_csr_addr or - v__h5882 or - v__h8286 or - v__h6026 or - v__h6140 or - csr_mie$fav_sie_write or - v__h8224 or - mav_csr_write_word or - v__h8442 or - csr_mip$fav_sip_write or - wordxl1__h7649 or - v__h7518 or - v__h7554 or csr_mie$fav_write or csr_mip$fav_write or result__h9129) - begin - case (mav_csr_write_csr_addr) - 12'h001: y_avValue_fst__h9500 = v__h5882; - 12'h002, 12'h306: y_avValue_fst__h9500 = v__h8286; - 12'h003: y_avValue_fst__h9500 = v__h6026; - 12'h100: y_avValue_fst__h9500 = v__h6140; - 12'h102, - 12'h103, - 12'h106, - 12'h301, - 12'h7A0, - 12'hF11, - 12'hF12, - 12'hF13, - 12'hF14: - y_avValue_fst__h9500 = 64'd0; - 12'h104: y_avValue_fst__h9500 = csr_mie$fav_sie_write; - 12'h105, 12'h305: y_avValue_fst__h9500 = v__h8224; - 12'h140, - 12'h141, - 12'h143, - 12'h180, - 12'h340, - 12'h341, - 12'h343, - 12'h7A2, - 12'h7A3, - 12'hB00, - 12'hB02: - y_avValue_fst__h9500 = mav_csr_write_word; - 12'h142, 12'h342: y_avValue_fst__h9500 = v__h8442; - 12'h144: y_avValue_fst__h9500 = csr_mip$fav_sip_write; - 12'h300: y_avValue_fst__h9500 = wordxl1__h7649; - 12'h302: y_avValue_fst__h9500 = v__h7518; - 12'h303: y_avValue_fst__h9500 = v__h7554; - 12'h304: y_avValue_fst__h9500 = csr_mie$fav_write; - 12'h344: y_avValue_fst__h9500 = csr_mip$fav_write; - 12'h7A1: y_avValue_fst__h9500 = result__h9129; - default: y_avValue_fst__h9500 = 64'd0; - endcase - end - always@(new_priv__h11323 or rg_mtvec or rg_stvec) - begin - case (new_priv__h11323) - 2'b01: - CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = - rg_stvec[62:1]; - 2'b11: - CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = - rg_mtvec[62:1]; - default: CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = - rg_mtvec[62:1]; - endcase - end - always@(new_priv__h11323 or rg_mtvec or rg_stvec) - begin - case (new_priv__h11323) - 2'b01: - CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_stvec[0]; - 2'b11: - CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_mtvec[0]; - default: CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_mtvec[0]; - endcase - end - always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) - begin - case (interrupt_pending_cur_priv) - 2'b0: - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = - csr_mstatus_rg_mstatus[0]; - 2'b01: - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = - csr_mstatus_rg_mstatus[1]; - default: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = - interrupt_pending_cur_priv == 2'b11 && - csr_mstatus_rg_mstatus[3]; - endcase - end - always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) - begin - case (interrupt_pending_cur_priv) - 2'b0: - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = - !csr_mstatus_rg_mstatus[0]; - 2'b01: - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = - !csr_mstatus_rg_mstatus[1]; - default: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = - interrupt_pending_cur_priv != 2'b11 || - !csr_mstatus_rg_mstatus[3]; - endcase - end - always@(read_csr_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_csr_addr) - 12'h001: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 59'd0, rg_fflags }; - 12'h002: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 61'd0, rg_frm }; - 12'h003: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 56'd0, rg_frm, rg_fflags }; - 12'h100: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = 64'd0; - 12'h104: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - csr_mie$fv_sie_read; - 12'h105: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { rg_stvec[62:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_sscratch; - 12'h141: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_sepc; - 12'h142: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { rg_scause[4], 59'd0, rg_scause[3:0] }; - 12'h143: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_stval; - 12'h144: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - csr_mip$fv_sip_read; - 12'h180: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_satp; - 12'h300: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - 64'h800000000014112D; - 12'h302: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 48'd0, rg_medeleg }; - 12'h303: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 52'd0, rg_mideleg }; - 12'h304: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_mscratch; - 12'h341: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mepc; - 12'h342: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_mtval; - 12'h344: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_tselect; - 12'h7A1: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_tdata1; - 12'h7A2: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_minstret; - default: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_tdata3; - endcase - end - always@(read_csr_port2_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_port2_csr_addr) - 12'h001: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 59'd0, rg_fflags }; - 12'h002: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 61'd0, rg_frm }; - 12'h003: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 56'd0, rg_frm, rg_fflags }; - 12'h100: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = 64'd0; - 12'h104: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - csr_mie$fv_sie_read; - 12'h105: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { rg_stvec[62:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_sscratch; - 12'h141: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_sepc; - 12'h142: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { rg_scause[4], 59'd0, rg_scause[3:0] }; - 12'h143: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_stval; - 12'h144: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - csr_mip$fv_sip_read; - 12'h180: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_satp; - 12'h300: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - 64'h800000000014112D; - 12'h302: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 48'd0, rg_medeleg }; - 12'h303: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 52'd0, rg_mideleg }; - 12'h304: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_mscratch; - 12'h341: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mepc; - 12'h342: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_mtval; - 12'h344: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_tselect; - 12'h7A1: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_tdata1; - 12'h7A2: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_minstret; - default: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_tdata3; - endcase - end - always@(mav_read_csr_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (mav_read_csr_csr_addr) - 12'h001: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 59'd0, rg_fflags }; - 12'h002: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 61'd0, rg_frm }; - 12'h003: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 56'd0, rg_frm, rg_fflags }; - 12'h100: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = 64'd0; - 12'h104: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - csr_mie$fv_sie_read; - 12'h105: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { rg_stvec[62:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_sscratch; - 12'h141: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_sepc; - 12'h142: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { rg_scause[4], 59'd0, rg_scause[3:0] }; - 12'h143: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_stval; - 12'h144: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - csr_mip$fv_sip_read; - 12'h180: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_satp; - 12'h300: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - 64'h800000000014112D; - 12'h302: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 48'd0, rg_medeleg }; - 12'h303: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 52'd0, rg_mideleg }; - 12'h304: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - csr_mie$fv_read; - 12'h305: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_mscratch; - 12'h341: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mepc; - 12'h342: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_mtval; - 12'h344: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - csr_mip$fv_read; - 12'h7A0: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_tselect; - 12'h7A1: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_tdata1; - 12'h7A2: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_minstret; - default: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_tdata3; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 64'h0000000A00002000; - rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (csr_mstatus_rg_mstatus$EN) - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY - csr_mstatus_rg_mstatus$D_IN; - if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; - if (rg_minstret$EN) - rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; - if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; - if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; - if (rg_dscratch0$EN) - rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; - if (rg_dscratch1$EN) - rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; - if (rg_fflags$EN) rg_fflags <= `BSV_ASSIGNMENT_DELAY rg_fflags$D_IN; - if (rg_frm$EN) rg_frm <= `BSV_ASSIGNMENT_DELAY rg_frm$D_IN; - if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; - if (rg_mcounteren$EN) - rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; - if (rg_medeleg$EN) rg_medeleg <= `BSV_ASSIGNMENT_DELAY rg_medeleg$D_IN; - if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; - if (rg_mideleg$EN) rg_mideleg <= `BSV_ASSIGNMENT_DELAY rg_mideleg$D_IN; - if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; - if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; - if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; - if (rg_nmi_vector$EN) - rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN; - if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; - if (rg_scause$EN) rg_scause <= `BSV_ASSIGNMENT_DELAY rg_scause$D_IN; - if (rg_sepc$EN) rg_sepc <= `BSV_ASSIGNMENT_DELAY rg_sepc$D_IN; - if (rg_sscratch$EN) rg_sscratch <= `BSV_ASSIGNMENT_DELAY rg_sscratch$D_IN; - if (rg_stval$EN) rg_stval <= `BSV_ASSIGNMENT_DELAY rg_stval$D_IN; - if (rg_stvec$EN) rg_stvec <= `BSV_ASSIGNMENT_DELAY rg_stvec$D_IN; - if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; - if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; - if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; - if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - csr_mstatus_rg_mstatus = 64'hAAAAAAAAAAAAAAAA; - rg_dcsr = 32'hAAAAAAAA; - rg_dpc = 64'hAAAAAAAAAAAAAAAA; - rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA; - rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA; - rg_fflags = 5'h0A; - rg_frm = 3'h2; - rg_mcause = 5'h0A; - rg_mcounteren = 3'h2; - rg_mcycle = 64'hAAAAAAAAAAAAAAAA; - rg_medeleg = 16'hAAAA; - rg_mepc = 64'hAAAAAAAAAAAAAAAA; - rg_mideleg = 12'hAAA; - rg_minstret = 64'hAAAAAAAAAAAAAAAA; - rg_mscratch = 64'hAAAAAAAAAAAAAAAA; - rg_mtval = 64'hAAAAAAAAAAAAAAAA; - rg_mtvec = 63'h2AAAAAAAAAAAAAAA; - rg_nmi = 1'h0; - rg_nmi_vector = 64'hAAAAAAAAAAAAAAAA; - rg_satp = 64'hAAAAAAAAAAAAAAAA; - rg_scause = 5'h0A; - rg_sepc = 64'hAAAAAAAAAAAAAAAA; - rg_sscratch = 64'hAAAAAAAAAAAAAAAA; - rg_state = 1'h0; - rg_stval = 64'hAAAAAAAAAAAAAAAA; - rg_stvec = 63'h2AAAAAAAAAAAAAAA; - rg_tdata1 = 64'hAAAAAAAAAAAAAAAA; - rg_tdata2 = 64'hAAAAAAAAAAAAAAAA; - rg_tdata3 = 64'hAAAAAAAAAAAAAAAA; - rg_tselect = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) - $display("sstatus = 0x%0h", - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("sip = 0x%0h", csr_mip$fv_sip_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("sie = 0x%0h", csr_mie$fv_sie_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mav_csr_write && - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940 && - NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", - rg_mcycle, - mav_csr_write_csr_addr, - mav_csr_write_word); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" priv %0d: ", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" edeleg: 0x%0h", 16'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ideleg: 0x%0h", 12'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] != 4'd0 && - rg_scause[3:0] != 4'd1 && - rg_scause[3:0] != 4'd2 && - rg_scause[3:0] != 4'd3 && - rg_scause[3:0] != 4'd4 && - rg_scause[3:0] != 4'd5 && - rg_scause[3:0] != 4'd6 && - rg_scause[3:0] != 4'd7 && - rg_scause[3:0] != 4'd8 && - rg_scause[3:0] != 4'd9 && - rg_scause[3:0] != 4'd10 && - rg_scause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_scause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] != 4'd0 && - rg_scause[3:0] != 4'd1 && - rg_scause[3:0] != 4'd2 && - rg_scause[3:0] != 4'd3 && - rg_scause[3:0] != 4'd4 && - rg_scause[3:0] != 4'd5 && - rg_scause[3:0] != 4'd6 && - rg_scause[3:0] != 4'd7 && - rg_scause[3:0] != 4'd8 && - rg_scause[3:0] != 4'd9 && - rg_scause[3:0] != 4'd11 && - rg_scause[3:0] != 4'd12 && - rg_scause[3:0] != 4'd13 && - rg_scause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_scause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" status: 0x%0h", - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tvec: 0x%0h", { rg_stvec[62:1], 1'b0, rg_stvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" epc: 0x%0h", rg_sepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tval: 0x%0h", rg_stval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" priv %0d: ", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" edeleg: 0x%0h", rg_medeleg); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ideleg: 0x%0h", rg_mideleg); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd10 && - rg_mcause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd11 && - rg_mcause[3:0] != 4'd12 && - rg_mcause[3:0] != 4'd13 && - rg_mcause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" status: 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tvec: 0x%0h", { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" epc: 0x%0h", rg_mepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tval: 0x%0h", rg_mtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" Return: new pc 0x%0h ", x__h10300); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" new mstatus:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write("MStatus{", - "sd:%0d", - x__h13437[14:13] == 2'h3 || x__h13437[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" sxl:%0d uxl:%0d", x__h13437[35:34], x__h13437[33:32]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tsr:%0d", x__h13437[22]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tw:%0d", x__h13437[21]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tvm:%0d", x__h13437[20]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" mxr:%0d", x__h13437[19]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" sum:%0d", x__h13437[18]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" mprv:%0d", x__h13437[17]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" xs:%0d", x__h13437[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" fs:%0d", x__h13437[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" mpp:%0d", x__h13437[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" spp:%0d", x__h13437[8]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" pies:%0d_%0d%0d", x__h13437[7], x__h13437[5], x__h13437[4]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ies:%0d_%0d%0d", x__h13437[3], x__h13437[1], x__h13437[0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" new xcause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402) - $write("unknown interrupt Exc_Code %d", exc_code__h13279); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453) - $write("unknown trap Exc_Code %d", exc_code__h13279); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" new priv %0d", new_priv__h11323); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", - rg_mcycle, - m_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", - rg_mcycle, - s_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: CSR_RegFile: timer_interrupt_req: %x", - rg_mcycle, - timer_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: CSR_RegFile: software_interrupt_req: %x", - rg_mcycle, - software_interrupt_req_set_not_clear); - end - // synopsys translate_on -endmodule // mkCSR_RegFile - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCore.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCore.v deleted file mode 100644 index 5178628a..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkCore.v +++ /dev/null @@ -1,2499 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// cpu_reset_server_response_get O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg -// cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg -// cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg -// cpu_imem_master_bready O 1 -// cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg -// cpu_imem_master_rready O 1 -// cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg -// cpu_dmem_master_awaddr O 64 reg -// cpu_dmem_master_awlen O 8 reg -// cpu_dmem_master_awsize O 3 reg -// cpu_dmem_master_awburst O 2 reg -// cpu_dmem_master_awlock O 1 reg -// cpu_dmem_master_awcache O 4 reg -// cpu_dmem_master_awprot O 3 reg -// cpu_dmem_master_awqos O 4 reg -// cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg -// cpu_dmem_master_wdata O 64 reg -// cpu_dmem_master_wstrb O 8 reg -// cpu_dmem_master_wlast O 1 reg -// cpu_dmem_master_bready O 1 reg -// cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg -// cpu_dmem_master_araddr O 64 reg -// cpu_dmem_master_arlen O 8 reg -// cpu_dmem_master_arsize O 3 reg -// cpu_dmem_master_arburst O 2 reg -// cpu_dmem_master_arlock O 1 reg -// cpu_dmem_master_arcache O 4 reg -// cpu_dmem_master_arprot O 3 reg -// cpu_dmem_master_arqos O 4 reg -// cpu_dmem_master_arregion O 4 reg -// cpu_dmem_master_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// cpu_reset_server_request_put I 1 reg -// cpu_imem_master_awready I 1 -// cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg -// cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg -// cpu_dmem_master_awready I 1 -// cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg -// cpu_dmem_master_bresp I 2 reg -// cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg -// cpu_dmem_master_rdata I 64 reg -// cpu_dmem_master_rresp I 2 reg -// cpu_dmem_master_rlast I 1 reg -// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// nmi_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (cpu_imem_master_awready, -// cpu_imem_master_wready, -// cpu_imem_master_arready) -> cpu_imem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCore(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - cpu_reset_server_request_put, - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, - - cpu_imem_master_awvalid, - - cpu_imem_master_awid, - - cpu_imem_master_awaddr, - - cpu_imem_master_awlen, - - cpu_imem_master_awsize, - - cpu_imem_master_awburst, - - cpu_imem_master_awlock, - - cpu_imem_master_awcache, - - cpu_imem_master_awprot, - - cpu_imem_master_awqos, - - cpu_imem_master_awregion, - - cpu_imem_master_awready, - - cpu_imem_master_wvalid, - - cpu_imem_master_wid, - - cpu_imem_master_wdata, - - cpu_imem_master_wstrb, - - cpu_imem_master_wlast, - - cpu_imem_master_wready, - - cpu_imem_master_bvalid, - cpu_imem_master_bid, - cpu_imem_master_bresp, - - cpu_imem_master_bready, - - cpu_imem_master_arvalid, - - cpu_imem_master_arid, - - cpu_imem_master_araddr, - - cpu_imem_master_arlen, - - cpu_imem_master_arsize, - - cpu_imem_master_arburst, - - cpu_imem_master_arlock, - - cpu_imem_master_arcache, - - cpu_imem_master_arprot, - - cpu_imem_master_arqos, - - cpu_imem_master_arregion, - - cpu_imem_master_arready, - - cpu_imem_master_rvalid, - cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast, - - cpu_imem_master_rready, - - cpu_dmem_master_awvalid, - - cpu_dmem_master_awid, - - cpu_dmem_master_awaddr, - - cpu_dmem_master_awlen, - - cpu_dmem_master_awsize, - - cpu_dmem_master_awburst, - - cpu_dmem_master_awlock, - - cpu_dmem_master_awcache, - - cpu_dmem_master_awprot, - - cpu_dmem_master_awqos, - - cpu_dmem_master_awregion, - - cpu_dmem_master_awready, - - cpu_dmem_master_wvalid, - - cpu_dmem_master_wid, - - cpu_dmem_master_wdata, - - cpu_dmem_master_wstrb, - - cpu_dmem_master_wlast, - - cpu_dmem_master_wready, - - cpu_dmem_master_bvalid, - cpu_dmem_master_bid, - cpu_dmem_master_bresp, - - cpu_dmem_master_bready, - - cpu_dmem_master_arvalid, - - cpu_dmem_master_arid, - - cpu_dmem_master_araddr, - - cpu_dmem_master_arlen, - - cpu_dmem_master_arsize, - - cpu_dmem_master_arburst, - - cpu_dmem_master_arlock, - - cpu_dmem_master_arcache, - - cpu_dmem_master_arprot, - - cpu_dmem_master_arqos, - - cpu_dmem_master_arregion, - - cpu_dmem_master_arready, - - cpu_dmem_master_rvalid, - cpu_dmem_master_rid, - cpu_dmem_master_rdata, - cpu_dmem_master_rresp, - cpu_dmem_master_rlast, - - cpu_dmem_master_rready, - - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - - nmi_req_set_not_clear); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method cpu_reset_server_request_put - input cpu_reset_server_request_put; - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // actionvalue method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; - - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; - - // value method cpu_imem_master_m_awaddr - output [63 : 0] cpu_imem_master_awaddr; - - // value method cpu_imem_master_m_awlen - output [7 : 0] cpu_imem_master_awlen; - - // value method cpu_imem_master_m_awsize - output [2 : 0] cpu_imem_master_awsize; - - // value method cpu_imem_master_m_awburst - output [1 : 0] cpu_imem_master_awburst; - - // value method cpu_imem_master_m_awlock - output cpu_imem_master_awlock; - - // value method cpu_imem_master_m_awcache - output [3 : 0] cpu_imem_master_awcache; - - // value method cpu_imem_master_m_awprot - output [2 : 0] cpu_imem_master_awprot; - - // value method cpu_imem_master_m_awqos - output [3 : 0] cpu_imem_master_awqos; - - // value method cpu_imem_master_m_awregion - output [3 : 0] cpu_imem_master_awregion; - - // value method cpu_imem_master_m_awuser - - // action method cpu_imem_master_m_awready - input cpu_imem_master_awready; - - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; - - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - - // value method cpu_imem_master_m_wdata - output [63 : 0] cpu_imem_master_wdata; - - // value method cpu_imem_master_m_wstrb - output [7 : 0] cpu_imem_master_wstrb; - - // value method cpu_imem_master_m_wlast - output cpu_imem_master_wlast; - - // value method cpu_imem_master_m_wuser - - // action method cpu_imem_master_m_wready - input cpu_imem_master_wready; - - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; - input [1 : 0] cpu_imem_master_bresp; - - // value method cpu_imem_master_m_bready - output cpu_imem_master_bready; - - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; - - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; - - // value method cpu_imem_master_m_araddr - output [63 : 0] cpu_imem_master_araddr; - - // value method cpu_imem_master_m_arlen - output [7 : 0] cpu_imem_master_arlen; - - // value method cpu_imem_master_m_arsize - output [2 : 0] cpu_imem_master_arsize; - - // value method cpu_imem_master_m_arburst - output [1 : 0] cpu_imem_master_arburst; - - // value method cpu_imem_master_m_arlock - output cpu_imem_master_arlock; - - // value method cpu_imem_master_m_arcache - output [3 : 0] cpu_imem_master_arcache; - - // value method cpu_imem_master_m_arprot - output [2 : 0] cpu_imem_master_arprot; - - // value method cpu_imem_master_m_arqos - output [3 : 0] cpu_imem_master_arqos; - - // value method cpu_imem_master_m_arregion - output [3 : 0] cpu_imem_master_arregion; - - // value method cpu_imem_master_m_aruser - - // action method cpu_imem_master_m_arready - input cpu_imem_master_arready; - - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; - input [63 : 0] cpu_imem_master_rdata; - input [1 : 0] cpu_imem_master_rresp; - input cpu_imem_master_rlast; - - // value method cpu_imem_master_m_rready - output cpu_imem_master_rready; - - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; - - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; - - // value method cpu_dmem_master_m_awaddr - output [63 : 0] cpu_dmem_master_awaddr; - - // value method cpu_dmem_master_m_awlen - output [7 : 0] cpu_dmem_master_awlen; - - // value method cpu_dmem_master_m_awsize - output [2 : 0] cpu_dmem_master_awsize; - - // value method cpu_dmem_master_m_awburst - output [1 : 0] cpu_dmem_master_awburst; - - // value method cpu_dmem_master_m_awlock - output cpu_dmem_master_awlock; - - // value method cpu_dmem_master_m_awcache - output [3 : 0] cpu_dmem_master_awcache; - - // value method cpu_dmem_master_m_awprot - output [2 : 0] cpu_dmem_master_awprot; - - // value method cpu_dmem_master_m_awqos - output [3 : 0] cpu_dmem_master_awqos; - - // value method cpu_dmem_master_m_awregion - output [3 : 0] cpu_dmem_master_awregion; - - // value method cpu_dmem_master_m_awuser - - // action method cpu_dmem_master_m_awready - input cpu_dmem_master_awready; - - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; - - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - - // value method cpu_dmem_master_m_wdata - output [63 : 0] cpu_dmem_master_wdata; - - // value method cpu_dmem_master_m_wstrb - output [7 : 0] cpu_dmem_master_wstrb; - - // value method cpu_dmem_master_m_wlast - output cpu_dmem_master_wlast; - - // value method cpu_dmem_master_m_wuser - - // action method cpu_dmem_master_m_wready - input cpu_dmem_master_wready; - - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; - input [1 : 0] cpu_dmem_master_bresp; - - // value method cpu_dmem_master_m_bready - output cpu_dmem_master_bready; - - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; - - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; - - // value method cpu_dmem_master_m_araddr - output [63 : 0] cpu_dmem_master_araddr; - - // value method cpu_dmem_master_m_arlen - output [7 : 0] cpu_dmem_master_arlen; - - // value method cpu_dmem_master_m_arsize - output [2 : 0] cpu_dmem_master_arsize; - - // value method cpu_dmem_master_m_arburst - output [1 : 0] cpu_dmem_master_arburst; - - // value method cpu_dmem_master_m_arlock - output cpu_dmem_master_arlock; - - // value method cpu_dmem_master_m_arcache - output [3 : 0] cpu_dmem_master_arcache; - - // value method cpu_dmem_master_m_arprot - output [2 : 0] cpu_dmem_master_arprot; - - // value method cpu_dmem_master_m_arqos - output [3 : 0] cpu_dmem_master_arqos; - - // value method cpu_dmem_master_m_arregion - output [3 : 0] cpu_dmem_master_arregion; - - // value method cpu_dmem_master_m_aruser - - // action method cpu_dmem_master_m_arready - input cpu_dmem_master_arready; - - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; - input [63 : 0] cpu_dmem_master_rdata; - input [1 : 0] cpu_dmem_master_rresp; - input cpu_dmem_master_rlast; - - // value method cpu_dmem_master_m_rready - output cpu_dmem_master_rready; - - // action method core_external_interrupt_sources_0_m_interrupt_req - input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_1_m_interrupt_req - input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_2_m_interrupt_req - input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_3_m_interrupt_req - input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_4_m_interrupt_req - input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_5_m_interrupt_req - input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_6_m_interrupt_req - input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_7_m_interrupt_req - input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_8_m_interrupt_req - input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_9_m_interrupt_req - input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_10_m_interrupt_req - input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_11_m_interrupt_req - input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_12_m_interrupt_req - input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_13_m_interrupt_req - input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_14_m_interrupt_req - input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_15_m_interrupt_req - input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // signals for module outputs - wire [63 : 0] cpu_dmem_master_araddr, - cpu_dmem_master_awaddr, - cpu_dmem_master_wdata, - cpu_imem_master_araddr, - cpu_imem_master_awaddr, - cpu_imem_master_wdata; - wire [7 : 0] cpu_dmem_master_arlen, - cpu_dmem_master_awlen, - cpu_dmem_master_wstrb, - cpu_imem_master_arlen, - cpu_imem_master_awlen, - cpu_imem_master_wstrb; - wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, - cpu_dmem_master_arqos, - cpu_dmem_master_arregion, - cpu_dmem_master_awcache, - cpu_dmem_master_awid, - cpu_dmem_master_awqos, - cpu_dmem_master_awregion, - cpu_dmem_master_wid, - cpu_imem_master_arcache, - cpu_imem_master_arid, - cpu_imem_master_arqos, - cpu_imem_master_arregion, - cpu_imem_master_awcache, - cpu_imem_master_awid, - cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; - wire [2 : 0] cpu_dmem_master_arprot, - cpu_dmem_master_arsize, - cpu_dmem_master_awprot, - cpu_dmem_master_awsize, - cpu_imem_master_arprot, - cpu_imem_master_arsize, - cpu_imem_master_awprot, - cpu_imem_master_awsize; - wire [1 : 0] cpu_dmem_master_arburst, - cpu_dmem_master_awburst, - cpu_imem_master_arburst, - cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_set_verbosity, - cpu_dmem_master_arlock, - cpu_dmem_master_arvalid, - cpu_dmem_master_awlock, - cpu_dmem_master_awvalid, - cpu_dmem_master_bready, - cpu_dmem_master_rready, - cpu_dmem_master_wlast, - cpu_dmem_master_wvalid, - cpu_imem_master_arlock, - cpu_imem_master_arvalid, - cpu_imem_master_awlock, - cpu_imem_master_awvalid, - cpu_imem_master_bready, - cpu_imem_master_rready, - cpu_imem_master_wlast, - cpu_imem_master_wvalid, - cpu_reset_server_response_get; - - // ports of submodule cpu - wire [63 : 0] cpu$dmem_master_araddr, - cpu$dmem_master_awaddr, - cpu$dmem_master_rdata, - cpu$dmem_master_wdata, - cpu$imem_master_araddr, - cpu$imem_master_awaddr, - cpu$imem_master_rdata, - cpu$imem_master_wdata, - cpu$set_verbosity_logdelay; - wire [7 : 0] cpu$dmem_master_arlen, - cpu$dmem_master_awlen, - cpu$dmem_master_wstrb, - cpu$imem_master_arlen, - cpu$imem_master_awlen, - cpu$imem_master_wstrb; - wire [3 : 0] cpu$dmem_master_arcache, - cpu$dmem_master_arid, - cpu$dmem_master_arqos, - cpu$dmem_master_arregion, - cpu$dmem_master_awcache, - cpu$dmem_master_awid, - cpu$dmem_master_awqos, - cpu$dmem_master_awregion, - cpu$dmem_master_bid, - cpu$dmem_master_rid, - cpu$dmem_master_wid, - cpu$imem_master_arcache, - cpu$imem_master_arid, - cpu$imem_master_arqos, - cpu$imem_master_arregion, - cpu$imem_master_awcache, - cpu$imem_master_awid, - cpu$imem_master_awqos, - cpu$imem_master_awregion, - cpu$imem_master_bid, - cpu$imem_master_rid, - cpu$imem_master_wid, - cpu$set_verbosity_verbosity; - wire [2 : 0] cpu$dmem_master_arprot, - cpu$dmem_master_arsize, - cpu$dmem_master_awprot, - cpu$dmem_master_awsize, - cpu$imem_master_arprot, - cpu$imem_master_arsize, - cpu$imem_master_awprot, - cpu$imem_master_awsize; - wire [1 : 0] cpu$dmem_master_arburst, - cpu$dmem_master_awburst, - cpu$dmem_master_bresp, - cpu$dmem_master_rresp, - cpu$imem_master_arburst, - cpu$imem_master_awburst, - cpu$imem_master_bresp, - cpu$imem_master_rresp; - wire cpu$EN_hart0_server_reset_request_put, - cpu$EN_hart0_server_reset_response_get, - cpu$EN_set_verbosity, - cpu$RDY_hart0_server_reset_request_put, - cpu$RDY_hart0_server_reset_response_get, - cpu$dmem_master_arlock, - cpu$dmem_master_arready, - cpu$dmem_master_arvalid, - cpu$dmem_master_awlock, - cpu$dmem_master_awready, - cpu$dmem_master_awvalid, - cpu$dmem_master_bready, - cpu$dmem_master_bvalid, - cpu$dmem_master_rlast, - cpu$dmem_master_rready, - cpu$dmem_master_rvalid, - cpu$dmem_master_wlast, - cpu$dmem_master_wready, - cpu$dmem_master_wvalid, - cpu$hart0_server_reset_request_put, - cpu$hart0_server_reset_response_get, - cpu$imem_master_arlock, - cpu$imem_master_arready, - cpu$imem_master_arvalid, - cpu$imem_master_awlock, - cpu$imem_master_awready, - cpu$imem_master_awvalid, - cpu$imem_master_bready, - cpu$imem_master_bvalid, - cpu$imem_master_rlast, - cpu$imem_master_rready, - cpu$imem_master_rvalid, - cpu$imem_master_wlast, - cpu$imem_master_wready, - cpu$imem_master_wvalid, - cpu$m_external_interrupt_req_set_not_clear, - cpu$nmi_req_set_not_clear, - cpu$s_external_interrupt_req_set_not_clear, - cpu$software_interrupt_req_set_not_clear, - cpu$timer_interrupt_req_set_not_clear; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_araddr, - fabric_2x3$v_to_slaves_2_awaddr, - fabric_2x3$v_to_slaves_2_rdata, - fabric_2x3$v_to_slaves_2_wdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb, - fabric_2x3$v_to_slaves_2_arlen, - fabric_2x3$v_to_slaves_2_awlen, - fabric_2x3$v_to_slaves_2_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_wid, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, - fabric_2x3$v_to_slaves_2_arcache, - fabric_2x3$v_to_slaves_2_arid, - fabric_2x3$v_to_slaves_2_arqos, - fabric_2x3$v_to_slaves_2_arregion, - fabric_2x3$v_to_slaves_2_awcache, - fabric_2x3$v_to_slaves_2_awid, - fabric_2x3$v_to_slaves_2_awqos, - fabric_2x3$v_to_slaves_2_awregion, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize, - fabric_2x3$v_to_slaves_2_arprot, - fabric_2x3$v_to_slaves_2_arsize, - fabric_2x3$v_to_slaves_2_awprot, - fabric_2x3$v_to_slaves_2_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_arburst, - fabric_2x3$v_to_slaves_2_awburst, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arlock, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_arvalid, - fabric_2x3$v_to_slaves_2_awlock, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_awvalid, - fabric_2x3$v_to_slaves_2_bready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rready, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wlast, - fabric_2x3$v_to_slaves_2_wready, - fabric_2x3$v_to_slaves_2_wvalid; - - // ports of submodule near_mem_io - wire [63 : 0] near_mem_io$axi4_slave_araddr, - near_mem_io$axi4_slave_awaddr, - near_mem_io$axi4_slave_rdata, - near_mem_io$axi4_slave_wdata, - near_mem_io$set_addr_map_addr_base, - near_mem_io$set_addr_map_addr_lim; - wire [7 : 0] near_mem_io$axi4_slave_arlen, - near_mem_io$axi4_slave_awlen, - near_mem_io$axi4_slave_wstrb; - wire [3 : 0] near_mem_io$axi4_slave_arcache, - near_mem_io$axi4_slave_arid, - near_mem_io$axi4_slave_arqos, - near_mem_io$axi4_slave_arregion, - near_mem_io$axi4_slave_awcache, - near_mem_io$axi4_slave_awid, - near_mem_io$axi4_slave_awqos, - near_mem_io$axi4_slave_awregion, - near_mem_io$axi4_slave_bid, - near_mem_io$axi4_slave_rid, - near_mem_io$axi4_slave_wid; - wire [2 : 0] near_mem_io$axi4_slave_arprot, - near_mem_io$axi4_slave_arsize, - near_mem_io$axi4_slave_awprot, - near_mem_io$axi4_slave_awsize; - wire [1 : 0] near_mem_io$axi4_slave_arburst, - near_mem_io$axi4_slave_awburst, - near_mem_io$axi4_slave_bresp, - near_mem_io$axi4_slave_rresp; - wire near_mem_io$EN_get_sw_interrupt_req_get, - near_mem_io$EN_get_timer_interrupt_req_get, - near_mem_io$EN_server_reset_request_put, - near_mem_io$EN_server_reset_response_get, - near_mem_io$EN_set_addr_map, - near_mem_io$RDY_get_sw_interrupt_req_get, - near_mem_io$RDY_get_timer_interrupt_req_get, - near_mem_io$RDY_server_reset_request_put, - near_mem_io$RDY_server_reset_response_get, - near_mem_io$axi4_slave_arlock, - near_mem_io$axi4_slave_arready, - near_mem_io$axi4_slave_arvalid, - near_mem_io$axi4_slave_awlock, - near_mem_io$axi4_slave_awready, - near_mem_io$axi4_slave_awvalid, - near_mem_io$axi4_slave_bready, - near_mem_io$axi4_slave_bvalid, - near_mem_io$axi4_slave_rlast, - near_mem_io$axi4_slave_rready, - near_mem_io$axi4_slave_rvalid, - near_mem_io$axi4_slave_wlast, - near_mem_io$axi4_slave_wready, - near_mem_io$axi4_slave_wvalid, - near_mem_io$get_sw_interrupt_req_get, - near_mem_io$get_timer_interrupt_req_get; - - // ports of submodule plic - wire [63 : 0] plic$axi4_slave_araddr, - plic$axi4_slave_awaddr, - plic$axi4_slave_rdata, - plic$axi4_slave_wdata, - plic$set_addr_map_addr_base, - plic$set_addr_map_addr_lim; - wire [7 : 0] plic$axi4_slave_arlen, - plic$axi4_slave_awlen, - plic$axi4_slave_wstrb; - wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, - plic$axi4_slave_arqos, - plic$axi4_slave_arregion, - plic$axi4_slave_awcache, - plic$axi4_slave_awid, - plic$axi4_slave_awqos, - plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, - plic$axi4_slave_wid, - plic$set_verbosity_verbosity; - wire [2 : 0] plic$axi4_slave_arprot, - plic$axi4_slave_arsize, - plic$axi4_slave_awprot, - plic$axi4_slave_awsize; - wire [1 : 0] plic$axi4_slave_arburst, - plic$axi4_slave_awburst, - plic$axi4_slave_bresp, - plic$axi4_slave_rresp; - wire plic$EN_server_reset_request_put, - plic$EN_server_reset_response_get, - plic$EN_set_addr_map, - plic$EN_set_verbosity, - plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, - plic$axi4_slave_arlock, - plic$axi4_slave_arready, - plic$axi4_slave_arvalid, - plic$axi4_slave_awlock, - plic$axi4_slave_awready, - plic$axi4_slave_awvalid, - plic$axi4_slave_bready, - plic$axi4_slave_bvalid, - plic$axi4_slave_rlast, - plic$axi4_slave_rready, - plic$axi4_slave_rvalid, - plic$axi4_slave_wlast, - plic$axi4_slave_wready, - plic$axi4_slave_wvalid, - plic$v_sources_0_m_interrupt_req_set_not_clear, - plic$v_sources_10_m_interrupt_req_set_not_clear, - plic$v_sources_11_m_interrupt_req_set_not_clear, - plic$v_sources_12_m_interrupt_req_set_not_clear, - plic$v_sources_13_m_interrupt_req_set_not_clear, - plic$v_sources_14_m_interrupt_req_set_not_clear, - plic$v_sources_15_m_interrupt_req_set_not_clear, - plic$v_sources_1_m_interrupt_req_set_not_clear, - plic$v_sources_2_m_interrupt_req_set_not_clear, - plic$v_sources_3_m_interrupt_req_set_not_clear, - plic$v_sources_4_m_interrupt_req_set_not_clear, - plic$v_sources_5_m_interrupt_req_set_not_clear, - plic$v_sources_6_m_interrupt_req_set_not_clear, - plic$v_sources_7_m_interrupt_req_set_not_clear, - plic$v_sources_8_m_interrupt_req_set_not_clear, - plic$v_sources_9_m_interrupt_req_set_not_clear, - plic$v_targets_0_m_eip, - plic$v_targets_1_m_eip; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_sw_interrupts, - CAN_FIRE_RL_rl_relay_timer_interrupts, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_nmi_req, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_sw_interrupts, - WILL_FIRE_RL_rl_relay_timer_interrupts, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_nmi_req, - WILL_FIRE_set_verbosity; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4310; - reg [31 : 0] v__h4551; - reg [31 : 0] v__h4304; - reg [31 : 0] v__h4545; - // synopsys translate_on - - // remaining internal signals - wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // actionvalue method cpu_reset_server_response_get - assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ; - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; - - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - - // value method cpu_imem_master_m_awid - assign cpu_imem_master_awid = cpu$imem_master_awid ; - - // value method cpu_imem_master_m_awaddr - assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; - - // value method cpu_imem_master_m_awlen - assign cpu_imem_master_awlen = cpu$imem_master_awlen ; - - // value method cpu_imem_master_m_awsize - assign cpu_imem_master_awsize = cpu$imem_master_awsize ; - - // value method cpu_imem_master_m_awburst - assign cpu_imem_master_awburst = cpu$imem_master_awburst ; - - // value method cpu_imem_master_m_awlock - assign cpu_imem_master_awlock = cpu$imem_master_awlock ; - - // value method cpu_imem_master_m_awcache - assign cpu_imem_master_awcache = cpu$imem_master_awcache ; - - // value method cpu_imem_master_m_awprot - assign cpu_imem_master_awprot = cpu$imem_master_awprot ; - - // value method cpu_imem_master_m_awqos - assign cpu_imem_master_awqos = cpu$imem_master_awqos ; - - // value method cpu_imem_master_m_awregion - assign cpu_imem_master_awregion = cpu$imem_master_awregion ; - - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; - - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; - - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = cpu$imem_master_wid ; - - // value method cpu_imem_master_m_wdata - assign cpu_imem_master_wdata = cpu$imem_master_wdata ; - - // value method cpu_imem_master_m_wstrb - assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; - - // value method cpu_imem_master_m_wlast - assign cpu_imem_master_wlast = cpu$imem_master_wlast ; - - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; - - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = cpu$imem_master_bready ; - - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; - - // value method cpu_imem_master_m_arid - assign cpu_imem_master_arid = cpu$imem_master_arid ; - - // value method cpu_imem_master_m_araddr - assign cpu_imem_master_araddr = cpu$imem_master_araddr ; - - // value method cpu_imem_master_m_arlen - assign cpu_imem_master_arlen = cpu$imem_master_arlen ; - - // value method cpu_imem_master_m_arsize - assign cpu_imem_master_arsize = cpu$imem_master_arsize ; - - // value method cpu_imem_master_m_arburst - assign cpu_imem_master_arburst = cpu$imem_master_arburst ; - - // value method cpu_imem_master_m_arlock - assign cpu_imem_master_arlock = cpu$imem_master_arlock ; - - // value method cpu_imem_master_m_arcache - assign cpu_imem_master_arcache = cpu$imem_master_arcache ; - - // value method cpu_imem_master_m_arprot - assign cpu_imem_master_arprot = cpu$imem_master_arprot ; - - // value method cpu_imem_master_m_arqos - assign cpu_imem_master_arqos = cpu$imem_master_arqos ; - - // value method cpu_imem_master_m_arregion - assign cpu_imem_master_arregion = cpu$imem_master_arregion ; - - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; - - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - - // value method cpu_imem_master_m_rready - assign cpu_imem_master_rready = cpu$imem_master_rready ; - - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; - - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; - - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; - - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; - - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; - - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; - - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; - - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; - - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; - - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; - - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; - - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; - - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; - - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; - - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; - - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; - - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; - - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; - - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; - - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; - - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; - - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; - - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; - - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; - - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; - - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; - - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; - - // action method core_external_interrupt_sources_0_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_1_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_2_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_3_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_4_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_5_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_6_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_7_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_8_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_9_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_10_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_11_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_12_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_13_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_14_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_15_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // submodule cpu - mkCPU cpu(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(cpu$dmem_master_arready), - .dmem_master_awready(cpu$dmem_master_awready), - .dmem_master_bid(cpu$dmem_master_bid), - .dmem_master_bresp(cpu$dmem_master_bresp), - .dmem_master_bvalid(cpu$dmem_master_bvalid), - .dmem_master_rdata(cpu$dmem_master_rdata), - .dmem_master_rid(cpu$dmem_master_rid), - .dmem_master_rlast(cpu$dmem_master_rlast), - .dmem_master_rresp(cpu$dmem_master_rresp), - .dmem_master_rvalid(cpu$dmem_master_rvalid), - .dmem_master_wready(cpu$dmem_master_wready), - .hart0_server_reset_request_put(cpu$hart0_server_reset_request_put), - .imem_master_arready(cpu$imem_master_arready), - .imem_master_awready(cpu$imem_master_awready), - .imem_master_bid(cpu$imem_master_bid), - .imem_master_bresp(cpu$imem_master_bresp), - .imem_master_bvalid(cpu$imem_master_bvalid), - .imem_master_rdata(cpu$imem_master_rdata), - .imem_master_rid(cpu$imem_master_rid), - .imem_master_rlast(cpu$imem_master_rlast), - .imem_master_rresp(cpu$imem_master_rresp), - .imem_master_rvalid(cpu$imem_master_rvalid), - .imem_master_wready(cpu$imem_master_wready), - .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), - .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), - .s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear), - .set_verbosity_logdelay(cpu$set_verbosity_logdelay), - .set_verbosity_verbosity(cpu$set_verbosity_verbosity), - .software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), - .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), - .EN_set_verbosity(cpu$EN_set_verbosity), - .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), - .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), - .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), - .imem_master_awvalid(cpu$imem_master_awvalid), - .imem_master_awid(cpu$imem_master_awid), - .imem_master_awaddr(cpu$imem_master_awaddr), - .imem_master_awlen(cpu$imem_master_awlen), - .imem_master_awsize(cpu$imem_master_awsize), - .imem_master_awburst(cpu$imem_master_awburst), - .imem_master_awlock(cpu$imem_master_awlock), - .imem_master_awcache(cpu$imem_master_awcache), - .imem_master_awprot(cpu$imem_master_awprot), - .imem_master_awqos(cpu$imem_master_awqos), - .imem_master_awregion(cpu$imem_master_awregion), - .imem_master_wvalid(cpu$imem_master_wvalid), - .imem_master_wid(cpu$imem_master_wid), - .imem_master_wdata(cpu$imem_master_wdata), - .imem_master_wstrb(cpu$imem_master_wstrb), - .imem_master_wlast(cpu$imem_master_wlast), - .imem_master_bready(cpu$imem_master_bready), - .imem_master_arvalid(cpu$imem_master_arvalid), - .imem_master_arid(cpu$imem_master_arid), - .imem_master_araddr(cpu$imem_master_araddr), - .imem_master_arlen(cpu$imem_master_arlen), - .imem_master_arsize(cpu$imem_master_arsize), - .imem_master_arburst(cpu$imem_master_arburst), - .imem_master_arlock(cpu$imem_master_arlock), - .imem_master_arcache(cpu$imem_master_arcache), - .imem_master_arprot(cpu$imem_master_arprot), - .imem_master_arqos(cpu$imem_master_arqos), - .imem_master_arregion(cpu$imem_master_arregion), - .imem_master_rready(cpu$imem_master_rready), - .dmem_master_awvalid(cpu$dmem_master_awvalid), - .dmem_master_awid(cpu$dmem_master_awid), - .dmem_master_awaddr(cpu$dmem_master_awaddr), - .dmem_master_awlen(cpu$dmem_master_awlen), - .dmem_master_awsize(cpu$dmem_master_awsize), - .dmem_master_awburst(cpu$dmem_master_awburst), - .dmem_master_awlock(cpu$dmem_master_awlock), - .dmem_master_awcache(cpu$dmem_master_awcache), - .dmem_master_awprot(cpu$dmem_master_awprot), - .dmem_master_awqos(cpu$dmem_master_awqos), - .dmem_master_awregion(cpu$dmem_master_awregion), - .dmem_master_wvalid(cpu$dmem_master_wvalid), - .dmem_master_wid(cpu$dmem_master_wid), - .dmem_master_wdata(cpu$dmem_master_wdata), - .dmem_master_wstrb(cpu$dmem_master_wstrb), - .dmem_master_wlast(cpu$dmem_master_wlast), - .dmem_master_bready(cpu$dmem_master_bready), - .dmem_master_arvalid(cpu$dmem_master_arvalid), - .dmem_master_arid(cpu$dmem_master_arid), - .dmem_master_araddr(cpu$dmem_master_araddr), - .dmem_master_arlen(cpu$dmem_master_arlen), - .dmem_master_arsize(cpu$dmem_master_arsize), - .dmem_master_arburst(cpu$dmem_master_arburst), - .dmem_master_arlock(cpu$dmem_master_arlock), - .dmem_master_arcache(cpu$dmem_master_arcache), - .dmem_master_arprot(cpu$dmem_master_arprot), - .dmem_master_arqos(cpu$dmem_master_arqos), - .dmem_master_arregion(cpu$dmem_master_arregion), - .dmem_master_rready(cpu$dmem_master_rready), - .RDY_set_verbosity()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(), - .v_from_masters_1_wready(), - .v_from_masters_1_bvalid(), - .v_from_masters_1_bid(), - .v_from_masters_1_bresp(), - .v_from_masters_1_arready(), - .v_from_masters_1_rvalid(), - .v_from_masters_1_rid(), - .v_from_masters_1_rdata(), - .v_from_masters_1_rresp(), - .v_from_masters_1_rlast(), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); - - // submodule near_mem_io - mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(near_mem_io$axi4_slave_araddr), - .axi4_slave_arburst(near_mem_io$axi4_slave_arburst), - .axi4_slave_arcache(near_mem_io$axi4_slave_arcache), - .axi4_slave_arid(near_mem_io$axi4_slave_arid), - .axi4_slave_arlen(near_mem_io$axi4_slave_arlen), - .axi4_slave_arlock(near_mem_io$axi4_slave_arlock), - .axi4_slave_arprot(near_mem_io$axi4_slave_arprot), - .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), - .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), - .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), - .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), - .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), - .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), - .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), - .axi4_slave_awid(near_mem_io$axi4_slave_awid), - .axi4_slave_awlen(near_mem_io$axi4_slave_awlen), - .axi4_slave_awlock(near_mem_io$axi4_slave_awlock), - .axi4_slave_awprot(near_mem_io$axi4_slave_awprot), - .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), - .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), - .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), - .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), - .axi4_slave_bready(near_mem_io$axi4_slave_bready), - .axi4_slave_rready(near_mem_io$axi4_slave_rready), - .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), - .axi4_slave_wid(near_mem_io$axi4_slave_wid), - .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), - .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), - .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), - .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), - .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), - .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), - .EN_set_addr_map(near_mem_io$EN_set_addr_map), - .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), - .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), - .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(near_mem_io$axi4_slave_awready), - .axi4_slave_wready(near_mem_io$axi4_slave_wready), - .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), - .axi4_slave_bid(near_mem_io$axi4_slave_bid), - .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), - .axi4_slave_arready(near_mem_io$axi4_slave_arready), - .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), - .axi4_slave_rid(near_mem_io$axi4_slave_rid), - .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), - .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), - .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), - .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), - .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), - .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), - .RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get)); - - // submodule plic - mkPLIC_16_2_7 plic(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(plic$axi4_slave_araddr), - .axi4_slave_arburst(plic$axi4_slave_arburst), - .axi4_slave_arcache(plic$axi4_slave_arcache), - .axi4_slave_arid(plic$axi4_slave_arid), - .axi4_slave_arlen(plic$axi4_slave_arlen), - .axi4_slave_arlock(plic$axi4_slave_arlock), - .axi4_slave_arprot(plic$axi4_slave_arprot), - .axi4_slave_arqos(plic$axi4_slave_arqos), - .axi4_slave_arregion(plic$axi4_slave_arregion), - .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), - .axi4_slave_awaddr(plic$axi4_slave_awaddr), - .axi4_slave_awburst(plic$axi4_slave_awburst), - .axi4_slave_awcache(plic$axi4_slave_awcache), - .axi4_slave_awid(plic$axi4_slave_awid), - .axi4_slave_awlen(plic$axi4_slave_awlen), - .axi4_slave_awlock(plic$axi4_slave_awlock), - .axi4_slave_awprot(plic$axi4_slave_awprot), - .axi4_slave_awqos(plic$axi4_slave_awqos), - .axi4_slave_awregion(plic$axi4_slave_awregion), - .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_bready(plic$axi4_slave_bready), - .axi4_slave_rready(plic$axi4_slave_rready), - .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), - .axi4_slave_wlast(plic$axi4_slave_wlast), - .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .set_addr_map_addr_base(plic$set_addr_map_addr_base), - .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), - .set_verbosity_verbosity(plic$set_verbosity_verbosity), - .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), - .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), - .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), - .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), - .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), - .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), - .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), - .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), - .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), - .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), - .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), - .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), - .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), - .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), - .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), - .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), - .EN_set_verbosity(plic$EN_set_verbosity), - .EN_show_PLIC_state(plic$EN_show_PLIC_state), - .EN_server_reset_request_put(plic$EN_server_reset_request_put), - .EN_server_reset_response_get(plic$EN_server_reset_response_get), - .EN_set_addr_map(plic$EN_set_addr_map), - .RDY_set_verbosity(), - .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(plic$axi4_slave_awready), - .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), - .axi4_slave_bid(plic$axi4_slave_bid), - .axi4_slave_bresp(plic$axi4_slave_bresp), - .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), - .axi4_slave_rid(plic$axi4_slave_rid), - .axi4_slave_rdata(plic$axi4_slave_rdata), - .axi4_slave_rresp(plic$axi4_slave_rresp), - .axi4_slave_rlast(plic$axi4_slave_rlast), - .v_targets_0_m_eip(plic$v_targets_0_m_eip), - .v_targets_1_m_eip(plic$v_targets_1_m_eip)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_relay_sw_interrupts - assign CAN_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // rule RL_rl_relay_timer_interrupts - assign CAN_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - - // rule RL_rl_relay_external_interrupts - assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule cpu - assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; - assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; - assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; - assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; - assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; - assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ; - assign cpu$imem_master_arready = cpu_imem_master_arready ; - assign cpu$imem_master_awready = cpu_imem_master_awready ; - assign cpu$imem_master_bid = cpu_imem_master_bid ; - assign cpu$imem_master_bresp = cpu_imem_master_bresp ; - assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; - assign cpu$imem_master_rdata = cpu_imem_master_rdata ; - assign cpu$imem_master_rid = cpu_imem_master_rid ; - assign cpu$imem_master_rlast = cpu_imem_master_rlast ; - assign cpu$imem_master_rresp = cpu_imem_master_rresp ; - assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; - assign cpu$imem_master_wready = cpu_imem_master_wready ; - assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; - assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; - assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; - assign cpu$software_interrupt_req_set_not_clear = - near_mem_io$get_sw_interrupt_req_get ; - assign cpu$timer_interrupt_req_set_not_clear = - near_mem_io$get_timer_interrupt_req_get ; - assign cpu$EN_hart0_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign cpu$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign cpu$EN_set_verbosity = EN_set_verbosity ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = cpu_reset_server_request_put ; - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ; - assign f_reset_rsps$ENQ = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; - assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; - assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; - assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; - assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; - assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; - assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; - assign fabric_2x3$v_from_masters_0_wid = cpu$dmem_master_wid ; - assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_awaddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_bready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_wdata = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wstrb = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; - assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; - - // submodule near_mem_io - assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign near_mem_io$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; - assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; - assign near_mem_io$set_addr_map_addr_base = - soc_map$m_near_mem_io_addr_base ; - assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; - assign near_mem_io$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign near_mem_io$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_set_addr_map = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_get_timer_interrupt_req_get = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign near_mem_io$EN_get_sw_interrupt_req_get = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_2_wid ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; - assign plic$set_verbosity_verbosity = 4'h0 ; - assign plic$v_sources_0_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; - assign plic$v_sources_10_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; - assign plic$v_sources_11_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; - assign plic$v_sources_12_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; - assign plic$v_sources_13_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; - assign plic$v_sources_14_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; - assign plic$v_sources_15_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; - assign plic$v_sources_1_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; - assign plic$v_sources_2_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; - assign plic$v_sources_3_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; - assign plic$v_sources_4_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; - assign plic$v_sources_5_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; - assign plic$v_sources_6_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; - assign plic$v_sources_7_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; - assign plic$v_sources_8_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; - assign plic$v_sources_9_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; - assign plic$EN_set_verbosity = 1'b0 ; - assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - cpu$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h4310 = $stime; - #0; - end - v__h4304 = v__h4310 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4304); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h4551 = $stime; - #0; - end - v__h4545 = v__h4551 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4545); - end - // synopsys translate_on -endmodule // mkCore - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Core.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Core.v deleted file mode 100644 index 127765e3..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Core.v +++ /dev/null @@ -1,12093 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// valid O 1 -// word_fst O 64 -// word_snd O 5 -// CLK I 1 clock -// RST_N I 1 reset -// req_opcode I 7 -// req_f7 I 7 -// req_rm I 3 -// req_rs2 I 5 -// req_v1 I 64 -// req_v2 I 64 -// req_v3 I 64 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFBox_Core(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_opcode, - req_f7, - req_rm, - req_rs2, - req_v1, - req_v2, - req_v3, - EN_req, - - valid, - - word_fst, - - word_snd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [6 : 0] req_opcode; - input [6 : 0] req_f7; - input [2 : 0] req_rm; - input [4 : 0] req_rs2; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input [63 : 0] req_v3; - input EN_req; - - // value method valid - output valid; - - // value method word_fst - output [63 : 0] word_fst; - - // value method word_snd - output [4 : 0] word_snd; - - // signals for module outputs - wire [63 : 0] word_fst; - wire [4 : 0] word_snd; - wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid; - - // inlined wires - wire [68 : 0] dw_result$wget; - wire dw_valid$wget, dw_valid$whas; - - // register requestR - reg [214 : 0] requestR; - wire [214 : 0] requestR$D_IN; - wire requestR$EN; - - // register resultR - reg [69 : 0] resultR; - reg [69 : 0] resultR$D_IN; - wire resultR$EN; - - // register stateR - reg [1 : 0] stateR; - reg [1 : 0] stateR$D_IN; - wire stateR$EN; - - // ports of submodule fpu - reg [201 : 0] fpu$server_core_request_put; - wire [69 : 0] fpu$server_core_response_get; - wire fpu$EN_server_core_request_put, - fpu$EN_server_core_response_get, - fpu$EN_server_reset_request_put, - fpu$EN_server_reset_response_get, - fpu$RDY_server_core_request_put, - fpu$RDY_server_core_response_get, - fpu$RDY_server_reset_request_put, - fpu$RDY_server_reset_response_get; - - // ports of submodule frmFpuF - wire frmFpuF$CLR, frmFpuF$DEQ, frmFpuF$D_IN, frmFpuF$ENQ; - - // ports of submodule resetReqsF - wire resetReqsF$CLR, - resetReqsF$DEQ, - resetReqsF$EMPTY_N, - resetReqsF$ENQ, - resetReqsF$FULL_N; - - // ports of submodule resetRspsF - wire resetRspsF$CLR, - resetRspsF$DEQ, - resetRspsF$EMPTY_N, - resetRspsF$ENQ, - resetRspsF$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_doFADD_D, - CAN_FIRE_RL_doFADD_S, - CAN_FIRE_RL_doFCLASS_D, - CAN_FIRE_RL_doFCLASS_S, - CAN_FIRE_RL_doFCVT_D_L, - CAN_FIRE_RL_doFCVT_D_LU, - CAN_FIRE_RL_doFCVT_D_S, - CAN_FIRE_RL_doFCVT_D_W, - CAN_FIRE_RL_doFCVT_D_WU, - CAN_FIRE_RL_doFCVT_LU_D, - CAN_FIRE_RL_doFCVT_LU_S, - CAN_FIRE_RL_doFCVT_L_D, - CAN_FIRE_RL_doFCVT_L_S, - CAN_FIRE_RL_doFCVT_S_D, - CAN_FIRE_RL_doFCVT_S_L, - CAN_FIRE_RL_doFCVT_S_LU, - CAN_FIRE_RL_doFCVT_S_W, - CAN_FIRE_RL_doFCVT_S_WU, - CAN_FIRE_RL_doFCVT_WU_D, - CAN_FIRE_RL_doFCVT_WU_S, - CAN_FIRE_RL_doFCVT_W_D, - CAN_FIRE_RL_doFCVT_W_S, - CAN_FIRE_RL_doFDIV_D, - CAN_FIRE_RL_doFDIV_S, - CAN_FIRE_RL_doFEQ_D, - CAN_FIRE_RL_doFEQ_S, - CAN_FIRE_RL_doFLE_D, - CAN_FIRE_RL_doFLE_S, - CAN_FIRE_RL_doFLT_D, - CAN_FIRE_RL_doFLT_S, - CAN_FIRE_RL_doFMADD_D, - CAN_FIRE_RL_doFMADD_S, - CAN_FIRE_RL_doFMAX_D, - CAN_FIRE_RL_doFMAX_S, - CAN_FIRE_RL_doFMIN_D, - CAN_FIRE_RL_doFMIN_S, - CAN_FIRE_RL_doFMSUB_D, - CAN_FIRE_RL_doFMSUB_S, - CAN_FIRE_RL_doFMUL_D, - CAN_FIRE_RL_doFMUL_S, - CAN_FIRE_RL_doFMV_D_X, - CAN_FIRE_RL_doFMV_W_X, - CAN_FIRE_RL_doFMV_X_D, - CAN_FIRE_RL_doFMV_X_W, - CAN_FIRE_RL_doFNMADD_D, - CAN_FIRE_RL_doFNMADD_S, - CAN_FIRE_RL_doFNMSUB_D, - CAN_FIRE_RL_doFNMSUB_S, - CAN_FIRE_RL_doFSGNJN_D, - CAN_FIRE_RL_doFSGNJN_S, - CAN_FIRE_RL_doFSGNJX_D, - CAN_FIRE_RL_doFSGNJX_S, - CAN_FIRE_RL_doFSGNJ_D, - CAN_FIRE_RL_doFSGNJ_S, - CAN_FIRE_RL_doFSQRT_D, - CAN_FIRE_RL_doFSQRT_S, - CAN_FIRE_RL_doFSUB_D, - CAN_FIRE_RL_doFSUB_S, - CAN_FIRE_RL_rl_drive_fpu_result, - CAN_FIRE_RL_rl_get_fpu_result, - CAN_FIRE_RL_rl_reset_begin, - CAN_FIRE_RL_rl_reset_end, - CAN_FIRE_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_RL_doFADD_D, - WILL_FIRE_RL_doFADD_S, - WILL_FIRE_RL_doFCLASS_D, - WILL_FIRE_RL_doFCLASS_S, - WILL_FIRE_RL_doFCVT_D_L, - WILL_FIRE_RL_doFCVT_D_LU, - WILL_FIRE_RL_doFCVT_D_S, - WILL_FIRE_RL_doFCVT_D_W, - WILL_FIRE_RL_doFCVT_D_WU, - WILL_FIRE_RL_doFCVT_LU_D, - WILL_FIRE_RL_doFCVT_LU_S, - WILL_FIRE_RL_doFCVT_L_D, - WILL_FIRE_RL_doFCVT_L_S, - WILL_FIRE_RL_doFCVT_S_D, - WILL_FIRE_RL_doFCVT_S_L, - WILL_FIRE_RL_doFCVT_S_LU, - WILL_FIRE_RL_doFCVT_S_W, - WILL_FIRE_RL_doFCVT_S_WU, - WILL_FIRE_RL_doFCVT_WU_D, - WILL_FIRE_RL_doFCVT_WU_S, - WILL_FIRE_RL_doFCVT_W_D, - WILL_FIRE_RL_doFCVT_W_S, - WILL_FIRE_RL_doFDIV_D, - WILL_FIRE_RL_doFDIV_S, - WILL_FIRE_RL_doFEQ_D, - WILL_FIRE_RL_doFEQ_S, - WILL_FIRE_RL_doFLE_D, - WILL_FIRE_RL_doFLE_S, - WILL_FIRE_RL_doFLT_D, - WILL_FIRE_RL_doFLT_S, - WILL_FIRE_RL_doFMADD_D, - WILL_FIRE_RL_doFMADD_S, - WILL_FIRE_RL_doFMAX_D, - WILL_FIRE_RL_doFMAX_S, - WILL_FIRE_RL_doFMIN_D, - WILL_FIRE_RL_doFMIN_S, - WILL_FIRE_RL_doFMSUB_D, - WILL_FIRE_RL_doFMSUB_S, - WILL_FIRE_RL_doFMUL_D, - WILL_FIRE_RL_doFMUL_S, - WILL_FIRE_RL_doFMV_D_X, - WILL_FIRE_RL_doFMV_W_X, - WILL_FIRE_RL_doFMV_X_D, - WILL_FIRE_RL_doFMV_X_W, - WILL_FIRE_RL_doFNMADD_D, - WILL_FIRE_RL_doFNMADD_S, - WILL_FIRE_RL_doFNMSUB_D, - WILL_FIRE_RL_doFNMSUB_S, - WILL_FIRE_RL_doFSGNJN_D, - WILL_FIRE_RL_doFSGNJN_S, - WILL_FIRE_RL_doFSGNJX_D, - WILL_FIRE_RL_doFSGNJX_S, - WILL_FIRE_RL_doFSGNJ_D, - WILL_FIRE_RL_doFSGNJ_S, - WILL_FIRE_RL_doFSQRT_D, - WILL_FIRE_RL_doFSQRT_S, - WILL_FIRE_RL_doFSUB_D, - WILL_FIRE_RL_doFSUB_S, - WILL_FIRE_RL_rl_drive_fpu_result, - WILL_FIRE_RL_rl_get_fpu_result, - WILL_FIRE_RL_rl_reset_begin, - WILL_FIRE_RL_rl_reset_end, - WILL_FIRE_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // inputs to muxes for submodule ports - wire [214 : 0] MUX_requestR$write_1__VAL_2; - wire [201 : 0] MUX_fpu$server_core_request_put_1__VAL_1, - MUX_fpu$server_core_request_put_1__VAL_10, - MUX_fpu$server_core_request_put_1__VAL_11, - MUX_fpu$server_core_request_put_1__VAL_12, - MUX_fpu$server_core_request_put_1__VAL_13, - MUX_fpu$server_core_request_put_1__VAL_14, - MUX_fpu$server_core_request_put_1__VAL_15, - MUX_fpu$server_core_request_put_1__VAL_16, - MUX_fpu$server_core_request_put_1__VAL_17, - MUX_fpu$server_core_request_put_1__VAL_18, - MUX_fpu$server_core_request_put_1__VAL_2, - MUX_fpu$server_core_request_put_1__VAL_3, - MUX_fpu$server_core_request_put_1__VAL_4, - MUX_fpu$server_core_request_put_1__VAL_5, - MUX_fpu$server_core_request_put_1__VAL_6, - MUX_fpu$server_core_request_put_1__VAL_7, - MUX_fpu$server_core_request_put_1__VAL_8, - MUX_fpu$server_core_request_put_1__VAL_9; - wire [69 : 0] MUX_resultR$write_1__VAL_10, - MUX_resultR$write_1__VAL_11, - MUX_resultR$write_1__VAL_12, - MUX_resultR$write_1__VAL_13, - MUX_resultR$write_1__VAL_14, - MUX_resultR$write_1__VAL_15, - MUX_resultR$write_1__VAL_16, - MUX_resultR$write_1__VAL_17, - MUX_resultR$write_1__VAL_18, - MUX_resultR$write_1__VAL_19, - MUX_resultR$write_1__VAL_20, - MUX_resultR$write_1__VAL_21, - MUX_resultR$write_1__VAL_22, - MUX_resultR$write_1__VAL_23, - MUX_resultR$write_1__VAL_24, - MUX_resultR$write_1__VAL_25, - MUX_resultR$write_1__VAL_26, - MUX_resultR$write_1__VAL_27, - MUX_resultR$write_1__VAL_28, - MUX_resultR$write_1__VAL_29, - MUX_resultR$write_1__VAL_3, - MUX_resultR$write_1__VAL_30, - MUX_resultR$write_1__VAL_31, - MUX_resultR$write_1__VAL_32, - MUX_resultR$write_1__VAL_33, - MUX_resultR$write_1__VAL_34, - MUX_resultR$write_1__VAL_35, - MUX_resultR$write_1__VAL_36, - MUX_resultR$write_1__VAL_37, - MUX_resultR$write_1__VAL_38, - MUX_resultR$write_1__VAL_39, - MUX_resultR$write_1__VAL_4, - MUX_resultR$write_1__VAL_40, - MUX_resultR$write_1__VAL_41, - MUX_resultR$write_1__VAL_42, - MUX_resultR$write_1__VAL_43, - MUX_resultR$write_1__VAL_5, - MUX_resultR$write_1__VAL_7, - MUX_resultR$write_1__VAL_8, - MUX_resultR$write_1__VAL_9; - wire [68 : 0] MUX_dw_result$wset_1__VAL_1; - wire MUX_dw_result$wset_1__SEL_1; - - // remaining internal signals - reg [51 : 0] CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q88, - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q89, - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q75, - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q76, - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q104, - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q105, - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q100, - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q101, - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q110, - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q111, - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q108, - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q109, - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q168, - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q169, - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q170, - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q171, - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q172, - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q173, - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q90, - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q91, - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q79, - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q80, - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030; - reg [22 : 0] CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q132, - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q133, - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q134, - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q135, - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q18, - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q19, - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q20, - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q21, - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q36, - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q37, - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q136, - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q137, - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q34, - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q35, - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q138, - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q139, - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q61, - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q62, - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q59, - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q60, - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q48, - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q49, - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q50, - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q51, - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569; - reg [10 : 0] CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_theR_ETC__q86, - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_x019_ETC__q87, - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_theR_ETC__q73, - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_x055_ETC__q74, - CASE_guard3135_0b0_0_0b1_0_0b10_out_exp3754_0b_ETC__q103, - CASE_guard3135_0b0_0_0b1_theResult___exp3751_0_ETC__q102, - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_theR_ETC__q98, - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_x388_ETC__q99, - CASE_guard4092_0b0_0_0b1_0_0b10_out_exp4711_0b_ETC__q29, - CASE_guard4092_0b0_0_0b1_theResult___exp4708_0_ETC__q30, - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_theR_ETC__q106, - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_x483_ETC__q107, - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q156, - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q157, - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q158, - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q159, - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q160, - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q161, - CASE_guard9455_0b0_0_0b1_0_0b10_out_exp0074_0b_ETC__q83, - CASE_guard9455_0b0_0_0b1_theResult___exp0071_0_ETC__q84, - CASE_guard9814_0b0_0_0b1_0_0b10_out_exp0433_0b_ETC__q78, - CASE_guard9814_0b0_0_0b1_theResult___exp0430_0_ETC__q77, - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard4092_ETC__q31, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard9455_ETC__q85, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951; - reg [7 : 0] CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q124, - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q125, - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q128, - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q129, - CASE_guard2228_0b0_0_0b1_0_0b10_out_exp2647_0b_ETC__q15, - CASE_guard2228_0b0_0_0b1_theResult___exp2644_0_ETC__q14, - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_theRe_ETC__q16, - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_x2773_ETC__q17, - CASE_guard2795_0b0_0_0b1_0_0b10_out_exp3211_0b_ETC__q26, - CASE_guard2795_0b0_0_0b1_theResult___exp3208_0_ETC__q27, - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q126, - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q127, - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_theRe_ETC__q32, - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_x3336_ETC__q33, - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q130, - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q131, - CASE_guard5283_0b0_0_0b1_0_0b10_out_exp5699_0b_ETC__q54, - CASE_guard5283_0b0_0_0b1_theResult___exp5696_0_ETC__q55, - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_theRe_ETC__q57, - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_x5824_ETC__q58, - CASE_guard9167_0b0_0_0b1_0_0b10_out_exp9583_0b_ETC__q45, - CASE_guard9167_0b0_0_0b1_theResult___exp9580_0_ETC__q44, - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_theRe_ETC__q46, - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_x9709_ETC__q47, - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard2795_ETC__q28, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5283_ETC__q56, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528; - reg [2 : 0] IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50; - reg CASE_guard0544_0b0_requestR_BIT_159_0b1_reques_ETC__q71, - CASE_guard10454_0b0_requestR_BIT_191_0b1_reque_ETC__q140, - CASE_guard19189_0b0_requestR_BIT_191_0b1_reque_ETC__q142, - CASE_guard2228_0b0_requestR_BIT_191_0b1_reques_ETC__q10, - CASE_guard2758_0b0_requestR_BIT_191_0b1_reques_ETC__q12, - CASE_guard28178_0b0_requestR_BIT_191_0b1_reque_ETC__q144, - CASE_guard3135_0b0_requestR_BIT_191_0b1_reques_ETC__q94, - CASE_guard37042_0b0_requestR_BIT_191_0b1_reque_ETC__q146, - CASE_guard3865_0b0_requestR_BIT_191_0b1_reques_ETC__q96, - CASE_guard60150_0b0_requestR_BITS_191_TO_160_E_ETC__q162, - CASE_guard69458_0b0_requestR_BITS_191_TO_160_E_ETC__q164, - CASE_guard78525_0b0_requestR_BITS_191_TO_160_E_ETC__q166, - CASE_guard9167_0b0_requestR_BIT_159_0b1_reques_ETC__q40, - CASE_guard9694_0b0_requestR_BIT_159_0b1_reques_ETC__q42, - CASE_guard9814_0b0_requestR_BIT_159_0b1_reques_ETC__q69, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q13, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q141, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q143, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q145, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q147, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q163, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q165, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q167, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q41, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q43, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q70, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q72, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q95, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q97; - wire [117 : 0] IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114, - b__h96173, - x__h97073, - x__h98317; - wire [88 : 0] IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705, - b__h36962, - x__h37862, - x__h39123; - wire [85 : 0] IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629, - b__h71539, - x__h72215, - x__h73238; - wire [64 : 0] _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - _theResult_____2__h36897, - _theResult_____2__h96108, - out1___1__h37613, - out1___1__h96824; - wire [63 : 0] IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2052, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2067, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1764, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1822, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2051, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2053, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2066, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2068, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2132, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2133, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1760, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1762, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1820, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3169, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3171, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3223, - IF_requestR_3_BITS_126_TO_116_167_EQ_2047_168__ETC___d5215, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d3225, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5228, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5294, - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d3173, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1693, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1824, - IF_requestR_3_BIT_191_47_THEN_9223372036854775_ETC___d3110, - res___1__h204227, - res___1__h204665, - res___1__h204675, - res___1__h204694, - res___1__h50292, - res___1__h50528, - res___1__h50538, - res___1__h50557, - res__h146185, - res__h187935, - res__h192322, - res__h196815, - res__h199464, - res__h202104, - res__h203926, - res__h204710, - res__h204864, - res__h42283, - res__h42520, - res__h47670, - res__h49098, - res__h50112, - res__h50573, - sfd___3__h12218, - sfd___3__h22785, - sfd__h2613, - x__h13699, - x__h147233, - x__h188904, - x__h193397, - x__h197786, - x__h200426, - x__h202248, - x__h204207, - x__h204831, - x__h2341, - x__h2422, - x__h24232, - x__h2500, - x__h2592, - x__h30632, - x__h36719, - x__h38702, - x__h39389, - x__h40910, - x__h41604, - x__h44183, - x__h46653, - x__h46718, - x__h46800, - x__h48228, - x__h49242, - x__h50272, - x__h51579, - x__h51645, - x__h51713, - x__h51788, - x__h61681, - x__h71293, - x__h72814, - x__h73505, - x__h85002, - x__h95930, - x__h97896, - x__h98583; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q114, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q151, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q119, - IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q148, - IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q154, - IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q116, - IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q122, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852, - _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d4575, - _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_608__ETC___d3744, - _theResult____h110444, - _theResult____h128168, - _theResult____h169448, - _theResult___snd__h118562, - _theResult___snd__h118573, - _theResult___snd__h118575, - _theResult___snd__h118585, - _theResult___snd__h118591, - _theResult___snd__h118614, - _theResult___snd__h127188, - _theResult___snd__h127190, - _theResult___snd__h127197, - _theResult___snd__h127203, - _theResult___snd__h127226, - _theResult___snd__h136415, - _theResult___snd__h136426, - _theResult___snd__h136428, - _theResult___snd__h136438, - _theResult___snd__h136444, - _theResult___snd__h136467, - _theResult___snd__h145065, - _theResult___snd__h145079, - _theResult___snd__h145085, - _theResult___snd__h145103, - _theResult___snd__h168062, - _theResult___snd__h168064, - _theResult___snd__h168071, - _theResult___snd__h168077, - _theResult___snd__h168100, - _theResult___snd__h177695, - _theResult___snd__h177706, - _theResult___snd__h177708, - _theResult___snd__h177718, - _theResult___snd__h177724, - _theResult___snd__h177747, - _theResult___snd__h186461, - _theResult___snd__h186475, - _theResult___snd__h186481, - _theResult___snd__h186499, - b__h39635, - result__h128781, - result__h170061, - sfd__h102814, - sfdin__h118545, - sfdin__h136398, - sfdin__h177678, - x__h128876, - x__h170156, - x__h40311, - x__h41334; - wire [54 : 0] sfd___3__h59804, sfd___3__h69445, sfd__h51803, sfd__h61693; - wire [53 : 0] sfd__h168129, - sfd__h177776, - sfd__h186534, - sfd__h59831, - sfd__h60574, - sfd__h69472, - sfd__h70214, - sfd__h83152, - sfd__h83895, - sfd__h94109, - sfd__h94851, - value__h71541; - wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5005, - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5007, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4978, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4980, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5024, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5026, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2370, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2372, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2388, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2390, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2901, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2903, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2919, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2921, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5037, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2398, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2580, - _theResult___fst_sfd__h153039, - _theResult___fst_sfd__h168865, - _theResult___fst_sfd__h168868, - _theResult___fst_sfd__h178512, - _theResult___fst_sfd__h178515, - _theResult___fst_sfd__h187294, - _theResult___fst_sfd__h187297, - _theResult___fst_sfd__h187306, - _theResult___fst_sfd__h187312, - _theResult___fst_sfd__h60528, - _theResult___fst_sfd__h61284, - _theResult___fst_sfd__h61287, - _theResult___fst_sfd__h70168, - _theResult___fst_sfd__h70923, - _theResult___fst_sfd__h70926, - _theResult___fst_sfd__h83849, - _theResult___fst_sfd__h84605, - _theResult___fst_sfd__h84608, - _theResult___fst_sfd__h94805, - _theResult___fst_sfd__h95560, - _theResult___fst_sfd__h95563, - _theResult___fst_sfd__h99110, - _theResult___sfd__h168767, - _theResult___sfd__h178414, - _theResult___sfd__h187196, - _theResult___sfd__h60431, - _theResult___sfd__h61187, - _theResult___sfd__h70072, - _theResult___sfd__h70827, - _theResult___sfd__h83752, - _theResult___sfd__h84508, - _theResult___sfd__h94709, - _theResult___sfd__h95464, - _theResult___snd_fst_sfd__h149185, - _theResult___snd_fst_sfd__h168871, - _theResult___snd_fst_sfd__h187300, - _theResult___snd_fst_sfd__h61290, - _theResult___snd_fst_sfd__h70929, - _theResult___snd_fst_sfd__h84611, - _theResult___snd_fst_sfd__h95566, - out___1_sfd__h147299, - out_sfd__h168770, - out_sfd__h178417, - out_sfd__h187199, - out_sfd__h60434, - out_sfd__h61190, - out_sfd__h70075, - out_sfd__h70830, - out_sfd__h83755, - out_sfd__h84511, - out_sfd__h94712, - out_sfd__h95467, - value__h98653; - wire [32 : 0] _theResult_____2__h39570, - _theResult_____2__h71474, - out1___1__h40062, - out1___1__h71966; - wire [31 : 0] IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2048, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2061, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2063, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1911, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1964, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2049, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2064, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1907, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1909, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1962, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2684, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2686, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2745, - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2046, - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2060, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d2747, - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d2688, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1848, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1966, - IF_requestR_3_BIT_191_47_THEN_2147483648_ELSE__ETC___d2617, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - requestR_BITS_159_TO_128__q1, - sfd___3__h29157, - sfd___3__h35273, - sfd__h24253, - x__h146191, - x__h2348, - x__h24238, - x__h2429, - x__h2507, - x__h2598, - x__h39392, - x__h40913, - x__h71296, - x__h72817; - wire [30 : 0] IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29; - wire [24 : 0] sfd__h118643, - sfd__h12245, - sfd__h127255, - sfd__h12788, - sfd__h136496, - sfd__h145138, - sfd__h22812, - sfd__h23351, - sfd__h29184, - sfd__h29724, - sfd__h35300, - sfd__h35839, - value__h36964; - wire [23 : 0] NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2654, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3139, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196; - wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4146, - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4148, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4192, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4194, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4165, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4167, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4211, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4213, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1402, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1404, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1420, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1422, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d545, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d547, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d563, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d565, - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d4224, - _theResult___fst_sfd__h110427, - _theResult___fst_sfd__h119176, - _theResult___fst_sfd__h119179, - _theResult___fst_sfd__h12742, - _theResult___fst_sfd__h127788, - _theResult___fst_sfd__h127791, - _theResult___fst_sfd__h13295, - _theResult___fst_sfd__h13298, - _theResult___fst_sfd__h137029, - _theResult___fst_sfd__h137032, - _theResult___fst_sfd__h145695, - _theResult___fst_sfd__h145698, - _theResult___fst_sfd__h145707, - _theResult___fst_sfd__h145713, - _theResult___fst_sfd__h147557, - _theResult___fst_sfd__h23305, - _theResult___fst_sfd__h23857, - _theResult___fst_sfd__h23860, - _theResult___fst_sfd__h29678, - _theResult___fst_sfd__h30231, - _theResult___fst_sfd__h30234, - _theResult___fst_sfd__h35793, - _theResult___fst_sfd__h36345, - _theResult___fst_sfd__h36348, - _theResult___sfd__h119078, - _theResult___sfd__h12645, - _theResult___sfd__h127690, - _theResult___sfd__h13198, - _theResult___sfd__h136931, - _theResult___sfd__h145597, - _theResult___sfd__h23209, - _theResult___sfd__h23761, - _theResult___sfd__h29581, - _theResult___sfd__h30134, - _theResult___sfd__h35697, - _theResult___sfd__h36249, - _theResult___snd_fst_sfd__h102768, - _theResult___snd_fst_sfd__h127794, - _theResult___snd_fst_sfd__h13301, - _theResult___snd_fst_sfd__h145701, - _theResult___snd_fst_sfd__h23863, - _theResult___snd_fst_sfd__h30237, - _theResult___snd_fst_sfd__h36351, - out_sfd__h119081, - out_sfd__h12648, - out_sfd__h127693, - out_sfd__h13201, - out_sfd__h136934, - out_sfd__h145600, - out_sfd__h23212, - out_sfd__h23764, - out_sfd__h29584, - out_sfd__h30137, - out_sfd__h35700, - out_sfd__h36252, - sV1_sfd__h1213, - sV2_sfd__h1316, - value__h147302; - wire [19 : 0] NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1730, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1877, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935; - wire [11 : 0] IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d4891, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150, - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737, - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3306, - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d4571, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4425, - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_608_ETC___d3740, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960, - x__h128909, - x__h170189, - x__h60559, - x__h70199, - x__h83880, - x__h94836; - wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4876, - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4878, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4551, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4553, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4945, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4947, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2321, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2347, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2349, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2852, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2878, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2880, - IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d2890, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q153, - _theResult___exp__h168766, - _theResult___exp__h178413, - _theResult___exp__h187195, - _theResult___exp__h60430, - _theResult___exp__h61186, - _theResult___exp__h70071, - _theResult___exp__h70826, - _theResult___exp__h83751, - _theResult___exp__h84507, - _theResult___exp__h94708, - _theResult___exp__h95463, - _theResult___fst_exp__h153038, - _theResult___fst_exp__h168102, - _theResult___fst_exp__h168108, - _theResult___fst_exp__h168111, - _theResult___fst_exp__h168864, - _theResult___fst_exp__h168867, - _theResult___fst_exp__h177684, - _theResult___fst_exp__h177749, - _theResult___fst_exp__h177755, - _theResult___fst_exp__h177758, - _theResult___fst_exp__h178511, - _theResult___fst_exp__h178514, - _theResult___fst_exp__h186467, - _theResult___fst_exp__h186506, - _theResult___fst_exp__h186512, - _theResult___fst_exp__h186515, - _theResult___fst_exp__h187293, - _theResult___fst_exp__h187296, - _theResult___fst_exp__h187305, - _theResult___fst_exp__h187308, - _theResult___fst_exp__h60527, - _theResult___fst_exp__h61283, - _theResult___fst_exp__h61286, - _theResult___fst_exp__h70167, - _theResult___fst_exp__h70922, - _theResult___fst_exp__h70925, - _theResult___fst_exp__h83848, - _theResult___fst_exp__h84604, - _theResult___fst_exp__h84607, - _theResult___fst_exp__h94804, - _theResult___fst_exp__h95559, - _theResult___fst_exp__h95562, - _theResult___snd_fst_exp__h168870, - _theResult___snd_fst_exp__h187299, - _theResult___snd_fst_exp__h61289, - _theResult___snd_fst_exp__h61292, - _theResult___snd_fst_exp__h61295, - _theResult___snd_fst_exp__h70928, - _theResult___snd_fst_exp__h70931, - _theResult___snd_fst_exp__h70934, - _theResult___snd_fst_exp__h84610, - _theResult___snd_fst_exp__h84613, - _theResult___snd_fst_exp__h84616, - _theResult___snd_fst_exp__h95565, - _theResult___snd_fst_exp__h95568, - _theResult___snd_fst_exp__h95571, - din_inc___2_exp__h187331, - din_inc___2_exp__h187361, - din_inc___2_exp__h187385, - din_inc___2_exp__h61329, - din_inc___2_exp__h70964, - din_inc___2_exp__h84650, - din_inc___2_exp__h95601, - out_exp__h168769, - out_exp__h178416, - out_exp__h187198, - out_exp__h60433, - out_exp__h61189, - out_exp__h70074, - out_exp__h70829, - out_exp__h83754, - out_exp__h84510, - out_exp__h94711, - out_exp__h95466, - requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620, - x__h147243; - wire [8 : 0] IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4058, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923, - x__h12773, - x__h23336, - x__h29709, - x__h35824; - wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3599, - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3601, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4043, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4045, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3716, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3718, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4112, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4114, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1353, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1379, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1381, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d496, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d522, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d524, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1391, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1613, - IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d534, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696, - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q121, - _theResult___exp__h119077, - _theResult___exp__h12644, - _theResult___exp__h127689, - _theResult___exp__h13197, - _theResult___exp__h136930, - _theResult___exp__h145596, - _theResult___exp__h23208, - _theResult___exp__h23760, - _theResult___exp__h29580, - _theResult___exp__h30133, - _theResult___exp__h35696, - _theResult___exp__h36248, - _theResult___fst_exp__h110426, - _theResult___fst_exp__h118551, - _theResult___fst_exp__h118616, - _theResult___fst_exp__h118622, - _theResult___fst_exp__h118625, - _theResult___fst_exp__h119175, - _theResult___fst_exp__h119178, - _theResult___fst_exp__h127228, - _theResult___fst_exp__h127234, - _theResult___fst_exp__h127237, - _theResult___fst_exp__h12741, - _theResult___fst_exp__h127787, - _theResult___fst_exp__h127790, - _theResult___fst_exp__h13294, - _theResult___fst_exp__h13297, - _theResult___fst_exp__h136404, - _theResult___fst_exp__h136469, - _theResult___fst_exp__h136475, - _theResult___fst_exp__h136478, - _theResult___fst_exp__h137028, - _theResult___fst_exp__h137031, - _theResult___fst_exp__h145071, - _theResult___fst_exp__h145110, - _theResult___fst_exp__h145116, - _theResult___fst_exp__h145119, - _theResult___fst_exp__h145694, - _theResult___fst_exp__h145697, - _theResult___fst_exp__h145706, - _theResult___fst_exp__h145709, - _theResult___fst_exp__h23304, - _theResult___fst_exp__h23856, - _theResult___fst_exp__h23859, - _theResult___fst_exp__h29677, - _theResult___fst_exp__h30230, - _theResult___fst_exp__h30233, - _theResult___fst_exp__h35792, - _theResult___fst_exp__h36344, - _theResult___fst_exp__h36347, - _theResult___snd_fst_exp__h127793, - _theResult___snd_fst_exp__h13300, - _theResult___snd_fst_exp__h13303, - _theResult___snd_fst_exp__h13306, - _theResult___snd_fst_exp__h145700, - _theResult___snd_fst_exp__h23862, - _theResult___snd_fst_exp__h23865, - _theResult___snd_fst_exp__h23868, - _theResult___snd_fst_exp__h30236, - _theResult___snd_fst_exp__h30239, - _theResult___snd_fst_exp__h30242, - _theResult___snd_fst_exp__h36350, - _theResult___snd_fst_exp__h36353, - _theResult___snd_fst_exp__h36356, - din_inc___2_exp__h13340, - din_inc___2_exp__h145728, - din_inc___2_exp__h145752, - din_inc___2_exp__h145782, - din_inc___2_exp__h145806, - din_inc___2_exp__h23898, - din_inc___2_exp__h30276, - din_inc___2_exp__h36386, - out_exp__h119080, - out_exp__h12647, - out_exp__h127692, - out_exp__h13200, - out_exp__h136933, - out_exp__h145599, - out_exp__h23211, - out_exp__h23763, - out_exp__h29583, - out_exp__h30136, - out_exp__h35699, - out_exp__h36251, - sV1_exp__h1212, - sV2_exp__h1315, - x__h98593; - wire [6 : 0] IF_IF_requestR_3_BIT_191_47_THEN_NEG_requestR__ETC___d404, - IF_requestR_3_BIT_191_47_THEN_0_ELSE_IF_reques_ETC___d920; - wire [5 : 0] IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d3540, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d4817, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d3984, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1270, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d2241, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1524, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d2455; - wire [4 : 0] _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294, - x__h13466, - x__h146306, - x__h188037, - x__h192454, - x__h202123, - x__h24002, - x__h30402, - x__h36490, - x__h38500, - x__h39201, - x__h40708, - x__h41412, - x__h43644, - x__h49117, - x__h61451, - x__h71064, - x__h72612, - x__h73316, - x__h84772, - x__h95701, - x__h97694, - x__h98395; - wire [1 : 0] IF_sfd___32218_BIT_10_THEN_2_ELSE_0__q9, - IF_sfd___32218_BIT_11_THEN_2_ELSE_0__q8, - IF_sfd___32218_BIT_39_THEN_2_ELSE_0__q7, - IF_sfd___32218_BIT_40_THEN_2_ELSE_0__q6, - IF_sfd___32785_BIT_10_THEN_2_ELSE_0__q25, - IF_sfd___32785_BIT_11_THEN_2_ELSE_0__q24, - IF_sfd___32785_BIT_39_THEN_2_ELSE_0__q23, - IF_sfd___32785_BIT_40_THEN_2_ELSE_0__q22, - IF_sfd___35273_BIT_7_THEN_2_ELSE_0__q53, - IF_sfd___35273_BIT_8_THEN_2_ELSE_0__q52, - IF_sfd___39157_BIT_7_THEN_2_ELSE_0__q39, - IF_sfd___39157_BIT_8_THEN_2_ELSE_0__q38, - IF_sfd___39445_BIT_1_THEN_2_ELSE_0__q82, - IF_sfd___39445_BIT_2_THEN_2_ELSE_0__q81, - IF_sfd___39804_BIT_1_THEN_2_ELSE_0__q68, - IF_sfd___39804_BIT_2_THEN_2_ELSE_0__q67, - IF_sfdin18545_BIT_33_THEN_2_ELSE_0__q115, - IF_sfdin36398_BIT_33_THEN_2_ELSE_0__q120, - IF_sfdin77678_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd27188_BIT_33_THEN_2_ELSE_0__q117, - IF_theResult___snd45065_BIT_33_THEN_2_ELSE_0__q123, - IF_theResult___snd68062_BIT_4_THEN_2_ELSE_0__q149, - IF_theResult___snd86461_BIT_4_THEN_2_ELSE_0__q155, - IF_x0311_BIT_24_THEN_2_ELSE_0__q65, - IF_x1334_BIT_24_THEN_2_ELSE_0__q66, - IF_x2215_BIT_53_THEN_2_ELSE_0__q92, - IF_x3238_BIT_53_THEN_2_ELSE_0__q93, - IF_x7073_BIT_53_THEN_2_ELSE_0__q112, - IF_x7862_BIT_24_THEN_2_ELSE_0__q63, - IF_x8317_BIT_53_THEN_2_ELSE_0__q113, - IF_x9123_BIT_24_THEN_2_ELSE_0__q64, - guard__h110454, - guard__h119189, - guard__h12228, - guard__h12758, - guard__h128178, - guard__h137042, - guard__h160150, - guard__h169458, - guard__h178525, - guard__h22795, - guard__h23321, - guard__h29167, - guard__h29694, - guard__h35283, - guard__h35809, - guard__h36895, - guard__h37673, - guard__h38902, - guard__h39568, - guard__h40122, - guard__h41113, - guard__h59814, - guard__h60544, - guard__h69455, - guard__h70184, - guard__h71472, - guard__h72026, - guard__h73017, - guard__h83135, - guard__h83865, - guard__h94092, - guard__h94821, - guard__h96106, - guard__h96884, - guard__h98096; - wire IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_9_ETC___d4244, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1331, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1481, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2300, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2415, - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1668, - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d2597, - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2831, - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2948, - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d474, - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d656, - IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d1128, - IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d3100, - IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d5061, - IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d5069, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5073, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5108, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5111, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5118, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5132, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5144, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5156, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1785, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1927, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2710, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3188, - IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d2301, - IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d5053, - IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2041, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5071, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5130, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5142, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5154, - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4262, - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4340, - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4353, - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4366, - IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d2021, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4264, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4315, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4326, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4342, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4355, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4368, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1831, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1842, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1974, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1985, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2007, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2017, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2030, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2032, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2035, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2037, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2055, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2088, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2099, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2103, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1722, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1754, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1814, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1869, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1901, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1956, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2646, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2678, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2739, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3131, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3163, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3217, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1472, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1475, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1484, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2939, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2942, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2951, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d647, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d650, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d659, - IF_requestR_3_BIT_191_47_THEN_NOT_requestR_3_B_ETC___d5208, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1733, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1795, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1880, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1937, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2657, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2720, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3142, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3198, - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4334, - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4362, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1774, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1836, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1919, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1979, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2044, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2045, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2098, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2104, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2120, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470, - NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d1278, - NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d2781, - NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d412, - NOT_requestR_3_BITS_159_TO_128_139_EQ_0_140_14_ETC___d1660, - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2699, - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2762, - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3180, - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3239, - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5212, - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5273, - NOT_requestR_3_BITS_190_TO_180_608_ULT_request_ETC___d5252, - NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d2102, - NOT_requestR_3_BIT_158_31_32_AND_NOT_requestR__ETC___d822, - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843, - NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d1013, - NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d3048, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570, - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738, - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d3542, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d4819, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d3986, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4499, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4892, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d3664, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4059, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4297, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4322, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4349, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926, - guard__h128776, - guard__h170056, - requestR_3_BITS_126_TO_116_167_EQ_0_181_AND_re_ETC___d5188, - requestR_3_BITS_179_TO_128_610_ULE_requestR_3__ETC___d5200, - requestR_3_BITS_179_TO_128_610_ULT_requestR_3__ETC___d5205, - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5184, - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5256, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2757, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2768, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3234, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3245, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5176, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5221, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5241, - requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199, - requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5197, - requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5251, - requestR_3_BITS_190_TO_180_608_ULT_requestR_3__ETC___d5204, - requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NOT_r_ETC___d856, - requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d2043, - requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077, - requestR_3_BIT_159_6_OR_requestR_3_BIT_158_31__ETC___d1671, - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1119, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1122, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1131, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3091, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3094, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3103; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = resetReqsF$FULL_N ; - assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas && dw_valid$wget ; - - // value method word_fst - assign word_fst = dw_result$wget[68:5] ; - - // value method word_snd - assign word_snd = dw_result$wget[4:0] ; - - // submodule fpu - mkFPU fpu(.CLK(CLK), - .RST_N(RST_N), - .server_core_request_put(fpu$server_core_request_put), - .EN_server_core_request_put(fpu$EN_server_core_request_put), - .EN_server_core_response_get(fpu$EN_server_core_response_get), - .EN_server_reset_request_put(fpu$EN_server_reset_request_put), - .EN_server_reset_response_get(fpu$EN_server_reset_response_get), - .RDY_server_core_request_put(fpu$RDY_server_core_request_put), - .server_core_response_get(fpu$server_core_response_get), - .RDY_server_core_response_get(fpu$RDY_server_core_response_get), - .RDY_server_reset_request_put(fpu$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fpu$RDY_server_reset_response_get)); - - // submodule frmFpuF - FIFO2 #(.width(32'd1), .guarded(32'd1)) frmFpuF(.RST(RST_N), - .CLK(CLK), - .D_IN(frmFpuF$D_IN), - .ENQ(frmFpuF$ENQ), - .DEQ(frmFpuF$DEQ), - .CLR(frmFpuF$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N()); - - // submodule resetReqsF - FIFO20 #(.guarded(32'd1)) resetReqsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetReqsF$ENQ), - .DEQ(resetReqsF$DEQ), - .CLR(resetReqsF$CLR), - .FULL_N(resetReqsF$FULL_N), - .EMPTY_N(resetReqsF$EMPTY_N)); - - // submodule resetRspsF - FIFO20 #(.guarded(32'd1)) resetRspsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetRspsF$ENQ), - .DEQ(resetRspsF$DEQ), - .CLR(resetRspsF$CLR), - .FULL_N(resetRspsF$FULL_N), - .EMPTY_N(resetRspsF$EMPTY_N)); - - // rule RL_rl_reset_end - assign CAN_FIRE_RL_rl_reset_end = - fpu$RDY_server_reset_response_get && resetRspsF$FULL_N && - stateR == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_end = CAN_FIRE_RL_rl_reset_end ; - - // rule RL_doFADD_S - assign CAN_FIRE_RL_doFADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0 ; - assign WILL_FIRE_RL_doFADD_S = CAN_FIRE_RL_doFADD_S ; - - // rule RL_doFSUB_S - assign CAN_FIRE_RL_doFSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h04 ; - assign WILL_FIRE_RL_doFSUB_S = CAN_FIRE_RL_doFSUB_S ; - - // rule RL_doFMUL_S - assign CAN_FIRE_RL_doFMUL_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h08 ; - assign WILL_FIRE_RL_doFMUL_S = CAN_FIRE_RL_doFMUL_S ; - - // rule RL_doFMADD_S - assign CAN_FIRE_RL_doFMADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000011 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFMADD_S = CAN_FIRE_RL_doFMADD_S ; - - // rule RL_doFMSUB_S - assign CAN_FIRE_RL_doFMSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000111 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFMSUB_S = CAN_FIRE_RL_doFMSUB_S ; - - // rule RL_doFNMADD_S - assign CAN_FIRE_RL_doFNMADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001111 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFNMADD_S = CAN_FIRE_RL_doFNMADD_S ; - - // rule RL_doFNMSUB_S - assign CAN_FIRE_RL_doFNMSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001011 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFNMSUB_S = CAN_FIRE_RL_doFNMSUB_S ; - - // rule RL_doFDIV_S - assign CAN_FIRE_RL_doFDIV_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0C ; - assign WILL_FIRE_RL_doFDIV_S = CAN_FIRE_RL_doFDIV_S ; - - // rule RL_doFSQRT_S - assign CAN_FIRE_RL_doFSQRT_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h2C ; - assign WILL_FIRE_RL_doFSQRT_S = CAN_FIRE_RL_doFSQRT_S ; - - // rule RL_doFSGNJ_S - assign CAN_FIRE_RL_doFSGNJ_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFSGNJ_S = CAN_FIRE_RL_doFSGNJ_S ; - - // rule RL_doFSGNJN_S - assign CAN_FIRE_RL_doFSGNJN_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFSGNJN_S = CAN_FIRE_RL_doFSGNJN_S ; - - // rule RL_doFSGNJX_S - assign CAN_FIRE_RL_doFSGNJX_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFSGNJX_S = CAN_FIRE_RL_doFSGNJX_S ; - - // rule RL_doFCVT_S_L - assign CAN_FIRE_RL_doFCVT_S_L = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd2 ; - assign WILL_FIRE_RL_doFCVT_S_L = CAN_FIRE_RL_doFCVT_S_L ; - - // rule RL_doFCVT_S_LU - assign CAN_FIRE_RL_doFCVT_S_LU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd3 ; - assign WILL_FIRE_RL_doFCVT_S_LU = CAN_FIRE_RL_doFCVT_S_LU ; - - // rule RL_doFCVT_S_W - assign CAN_FIRE_RL_doFCVT_S_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_S_W = CAN_FIRE_RL_doFCVT_S_W ; - - // rule RL_doFCVT_S_WU - assign CAN_FIRE_RL_doFCVT_S_WU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_S_WU = CAN_FIRE_RL_doFCVT_S_WU ; - - // rule RL_doFCVT_L_S - assign CAN_FIRE_RL_doFCVT_L_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd2 ; - assign WILL_FIRE_RL_doFCVT_L_S = CAN_FIRE_RL_doFCVT_L_S ; - - // rule RL_doFCVT_LU_S - assign CAN_FIRE_RL_doFCVT_LU_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd3 ; - assign WILL_FIRE_RL_doFCVT_LU_S = CAN_FIRE_RL_doFCVT_LU_S ; - - // rule RL_doFCVT_W_S - assign CAN_FIRE_RL_doFCVT_W_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_W_S = CAN_FIRE_RL_doFCVT_W_S ; - - // rule RL_doFCVT_WU_S - assign CAN_FIRE_RL_doFCVT_WU_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_WU_S = CAN_FIRE_RL_doFCVT_WU_S ; - - // rule RL_doFMIN_S - assign CAN_FIRE_RL_doFMIN_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h14 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMIN_S = CAN_FIRE_RL_doFMIN_S ; - - // rule RL_doFMAX_S - assign CAN_FIRE_RL_doFMAX_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h14 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFMAX_S = CAN_FIRE_RL_doFMAX_S ; - - // rule RL_doFMV_W_X - assign CAN_FIRE_RL_doFMV_W_X = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h78 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_W_X = CAN_FIRE_RL_doFMV_W_X ; - - // rule RL_doFMV_X_W - assign CAN_FIRE_RL_doFMV_X_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h70 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_X_W = CAN_FIRE_RL_doFMV_X_W ; - - // rule RL_doFEQ_S - assign CAN_FIRE_RL_doFEQ_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFEQ_S = CAN_FIRE_RL_doFEQ_S ; - - // rule RL_doFLT_S - assign CAN_FIRE_RL_doFLT_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFLT_S = CAN_FIRE_RL_doFLT_S ; - - // rule RL_doFLE_S - assign CAN_FIRE_RL_doFLE_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFLE_S = CAN_FIRE_RL_doFLE_S ; - - // rule RL_doFCLASS_S - assign CAN_FIRE_RL_doFCLASS_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h70 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFCLASS_S = CAN_FIRE_RL_doFCLASS_S ; - - // rule RL_doFADD_D - assign CAN_FIRE_RL_doFADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h01 ; - assign WILL_FIRE_RL_doFADD_D = CAN_FIRE_RL_doFADD_D ; - - // rule RL_doFSUB_D - assign CAN_FIRE_RL_doFSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h05 ; - assign WILL_FIRE_RL_doFSUB_D = CAN_FIRE_RL_doFSUB_D ; - - // rule RL_doFMUL_D - assign CAN_FIRE_RL_doFMUL_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h09 ; - assign WILL_FIRE_RL_doFMUL_D = CAN_FIRE_RL_doFMUL_D ; - - // rule RL_doFMADD_D - assign CAN_FIRE_RL_doFMADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000011 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFMADD_D = CAN_FIRE_RL_doFMADD_D ; - - // rule RL_doFMSUB_D - assign CAN_FIRE_RL_doFMSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000111 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFMSUB_D = CAN_FIRE_RL_doFMSUB_D ; - - // rule RL_doFNMADD_D - assign CAN_FIRE_RL_doFNMADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001111 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFNMADD_D = CAN_FIRE_RL_doFNMADD_D ; - - // rule RL_doFNMSUB_D - assign CAN_FIRE_RL_doFNMSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001011 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFNMSUB_D = CAN_FIRE_RL_doFNMSUB_D ; - - // rule RL_doFDIV_D - assign CAN_FIRE_RL_doFDIV_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0D ; - assign WILL_FIRE_RL_doFDIV_D = CAN_FIRE_RL_doFDIV_D ; - - // rule RL_doFSQRT_D - assign CAN_FIRE_RL_doFSQRT_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h2D ; - assign WILL_FIRE_RL_doFSQRT_D = CAN_FIRE_RL_doFSQRT_D ; - - // rule RL_doFSGNJ_D - assign CAN_FIRE_RL_doFSGNJ_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFSGNJ_D = CAN_FIRE_RL_doFSGNJ_D ; - - // rule RL_doFSGNJN_D - assign CAN_FIRE_RL_doFSGNJN_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFSGNJN_D = CAN_FIRE_RL_doFSGNJN_D ; - - // rule RL_doFSGNJX_D - assign CAN_FIRE_RL_doFSGNJX_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFSGNJX_D = CAN_FIRE_RL_doFSGNJX_D ; - - // rule RL_doFCVT_D_W - assign CAN_FIRE_RL_doFCVT_D_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_D_W = CAN_FIRE_RL_doFCVT_D_W ; - - // rule RL_doFCVT_D_WU - assign CAN_FIRE_RL_doFCVT_D_WU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_D_WU = CAN_FIRE_RL_doFCVT_D_WU ; - - // rule RL_doFCVT_W_D - assign CAN_FIRE_RL_doFCVT_W_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_W_D = CAN_FIRE_RL_doFCVT_W_D ; - - // rule RL_doFCVT_WU_D - assign CAN_FIRE_RL_doFCVT_WU_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_WU_D = CAN_FIRE_RL_doFCVT_WU_D ; - - // rule RL_doFCVT_D_L - assign CAN_FIRE_RL_doFCVT_D_L = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd2 ; - assign WILL_FIRE_RL_doFCVT_D_L = CAN_FIRE_RL_doFCVT_D_L ; - - // rule RL_doFCVT_D_LU - assign CAN_FIRE_RL_doFCVT_D_LU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd3 ; - assign WILL_FIRE_RL_doFCVT_D_LU = CAN_FIRE_RL_doFCVT_D_LU ; - - // rule RL_doFCVT_L_D - assign CAN_FIRE_RL_doFCVT_L_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd2 ; - assign WILL_FIRE_RL_doFCVT_L_D = CAN_FIRE_RL_doFCVT_L_D ; - - // rule RL_doFCVT_LU_D - assign CAN_FIRE_RL_doFCVT_LU_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd3 ; - assign WILL_FIRE_RL_doFCVT_LU_D = CAN_FIRE_RL_doFCVT_LU_D ; - - // rule RL_doFCVT_S_D - assign CAN_FIRE_RL_doFCVT_S_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h20 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_S_D = CAN_FIRE_RL_doFCVT_S_D ; - - // rule RL_doFCVT_D_S - assign CAN_FIRE_RL_doFCVT_D_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h21 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_D_S = CAN_FIRE_RL_doFCVT_D_S ; - - // rule RL_doFMIN_D - assign CAN_FIRE_RL_doFMIN_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h15 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMIN_D = CAN_FIRE_RL_doFMIN_D ; - - // rule RL_doFMAX_D - assign CAN_FIRE_RL_doFMAX_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h15 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFMAX_D = CAN_FIRE_RL_doFMAX_D ; - - // rule RL_doFEQ_D - assign CAN_FIRE_RL_doFEQ_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFEQ_D = CAN_FIRE_RL_doFEQ_D ; - - // rule RL_doFLT_D - assign CAN_FIRE_RL_doFLT_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFLT_D = CAN_FIRE_RL_doFLT_D ; - - // rule RL_doFLE_D - assign CAN_FIRE_RL_doFLE_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFLE_D = CAN_FIRE_RL_doFLE_D ; - - // rule RL_doFMV_D_X - assign CAN_FIRE_RL_doFMV_D_X = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h79 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_D_X = CAN_FIRE_RL_doFMV_D_X ; - - // rule RL_doFMV_X_D - assign CAN_FIRE_RL_doFMV_X_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h71 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_X_D = CAN_FIRE_RL_doFMV_X_D ; - - // rule RL_doFCLASS_D - assign CAN_FIRE_RL_doFCLASS_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h71 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFCLASS_D = CAN_FIRE_RL_doFCLASS_D ; - - // rule RL_rl_get_fpu_result - assign CAN_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ; - assign WILL_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ; - - // rule RL_rl_drive_fpu_result - assign CAN_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ; - assign WILL_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ; - - // rule RL_rl_reset_begin - assign CAN_FIRE_RL_rl_reset_begin = - fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_begin = CAN_FIRE_RL_rl_reset_begin ; - - // inputs to muxes for submodule ports - assign MUX_dw_result$wset_1__SEL_1 = - fpu$RDY_server_core_response_get && stateR == 2'd2 ; - assign MUX_dw_result$wset_1__VAL_1 = - { x__h204831, fpu$server_core_response_get[4:0] } ; - assign MUX_fpu$server_core_request_put_1__VAL_1 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd0 } ; - assign MUX_fpu$server_core_request_put_1__VAL_2 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd1 } ; - assign MUX_fpu$server_core_request_put_1__VAL_3 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd2 } ; - assign MUX_fpu$server_core_request_put_1__VAL_4 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd5 } ; - assign MUX_fpu$server_core_request_put_1__VAL_5 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd6 } ; - assign MUX_fpu$server_core_request_put_1__VAL_6 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd7 } ; - assign MUX_fpu$server_core_request_put_1__VAL_7 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd8 } ; - assign MUX_fpu$server_core_request_put_1__VAL_8 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd3 } ; - assign MUX_fpu$server_core_request_put_1__VAL_9 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 130'h15555555555555554AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd4 } ; - assign MUX_fpu$server_core_request_put_1__VAL_10 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd0 } ; - assign MUX_fpu$server_core_request_put_1__VAL_11 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd1 } ; - assign MUX_fpu$server_core_request_put_1__VAL_12 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd2 } ; - assign MUX_fpu$server_core_request_put_1__VAL_13 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd5 } ; - assign MUX_fpu$server_core_request_put_1__VAL_14 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd6 } ; - assign MUX_fpu$server_core_request_put_1__VAL_15 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd7 } ; - assign MUX_fpu$server_core_request_put_1__VAL_16 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd8 } ; - assign MUX_fpu$server_core_request_put_1__VAL_17 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd3 } ; - assign MUX_fpu$server_core_request_put_1__VAL_18 = - { 1'd0, - requestR[191:128], - 130'h15555555555555554AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd4 } ; - assign MUX_requestR$write_1__VAL_2 = - { 1'd1, - req_opcode, - req_f7, - req_rs2, - req_rm, - req_v1, - req_v2, - req_v3 } ; - assign MUX_resultR$write_1__VAL_3 = - { 1'd1, x__h204831, fpu$server_core_response_get[4:0] } ; - assign MUX_resultR$write_1__VAL_4 = { 1'd1, x__h204207, 5'd0 } ; - assign MUX_resultR$write_1__VAL_5 = { 1'd1, requestR[191:128], 5'd0 } ; - assign MUX_resultR$write_1__VAL_7 = { 1'd1, x__h202248, x__h202123 } ; - assign MUX_resultR$write_1__VAL_8 = { 1'd1, x__h200426, x__h202123 } ; - assign MUX_resultR$write_1__VAL_9 = { 1'd1, x__h197786, x__h192454 } ; - assign MUX_resultR$write_1__VAL_10 = { 1'd1, x__h193397, x__h192454 } ; - assign MUX_resultR$write_1__VAL_11 = { 1'd1, x__h188904, x__h192454 } ; - assign MUX_resultR$write_1__VAL_12 = { 1'd1, x__h147233, x__h188037 } ; - assign MUX_resultR$write_1__VAL_13 = { 1'd1, x__h98583, x__h146306 } ; - assign MUX_resultR$write_1__VAL_14 = { 1'd1, x__h97896, x__h98395 } ; - assign MUX_resultR$write_1__VAL_15 = { 1'd1, x__h95930, x__h97694 } ; - assign MUX_resultR$write_1__VAL_16 = { 1'd1, x__h85002, x__h95701 } ; - assign MUX_resultR$write_1__VAL_17 = { 1'd1, x__h73505, x__h84772 } ; - assign MUX_resultR$write_1__VAL_18 = { 1'd1, x__h72814, x__h73316 } ; - assign MUX_resultR$write_1__VAL_19 = { 1'd1, x__h71293, x__h72612 } ; - assign MUX_resultR$write_1__VAL_20 = { 1'd1, x__h61681, x__h71064 } ; - assign MUX_resultR$write_1__VAL_21 = { 1'd1, x__h51788, x__h61451 } ; - assign MUX_resultR$write_1__VAL_22 = { 1'd1, x__h51713, 5'd0 } ; - assign MUX_resultR$write_1__VAL_23 = { 1'd1, x__h51645, 5'd0 } ; - assign MUX_resultR$write_1__VAL_24 = { 1'd1, x__h51579, 5'd0 } ; - assign MUX_resultR$write_1__VAL_25 = { 1'd1, x__h50272, 5'd0 } ; - assign MUX_resultR$write_1__VAL_26 = { 1'd1, x__h49242, x__h49117 } ; - assign MUX_resultR$write_1__VAL_27 = { 1'd1, x__h48228, x__h49117 } ; - assign MUX_resultR$write_1__VAL_28 = { 1'd1, x__h46800, x__h43644 } ; - assign MUX_resultR$write_1__VAL_29 = { 1'd1, x__h46718, 5'd0 } ; - assign MUX_resultR$write_1__VAL_30 = { 1'd1, x__h46653, 5'd0 } ; - assign MUX_resultR$write_1__VAL_31 = { 1'd1, x__h44183, x__h43644 } ; - assign MUX_resultR$write_1__VAL_32 = { 1'd1, x__h41604, x__h43644 } ; - assign MUX_resultR$write_1__VAL_33 = { 1'd1, x__h40910, x__h41412 } ; - assign MUX_resultR$write_1__VAL_34 = { 1'd1, x__h39389, x__h40708 } ; - assign MUX_resultR$write_1__VAL_35 = { 1'd1, x__h38702, x__h39201 } ; - assign MUX_resultR$write_1__VAL_36 = { 1'd1, x__h36719, x__h38500 } ; - assign MUX_resultR$write_1__VAL_37 = { 1'd1, x__h30632, x__h36490 } ; - assign MUX_resultR$write_1__VAL_38 = { 1'd1, x__h24232, x__h30402 } ; - assign MUX_resultR$write_1__VAL_39 = { 1'd1, x__h13699, x__h24002 } ; - assign MUX_resultR$write_1__VAL_40 = { 1'd1, x__h2592, x__h13466 } ; - assign MUX_resultR$write_1__VAL_41 = { 1'd1, x__h2500, 5'd0 } ; - assign MUX_resultR$write_1__VAL_42 = { 1'd1, x__h2422, 5'd0 } ; - assign MUX_resultR$write_1__VAL_43 = { 1'd1, x__h2341, 5'd0 } ; - - // inlined wires - assign dw_valid$wget = !WILL_FIRE_RL_rl_drive_fpu_result || resultR[69] ; - assign dw_valid$whas = - WILL_FIRE_RL_rl_drive_fpu_result || - WILL_FIRE_RL_rl_get_fpu_result ; - assign dw_result$wget = - WILL_FIRE_RL_rl_get_fpu_result ? - MUX_dw_result$wset_1__VAL_1 : - resultR[68:0] ; - - // register requestR - assign requestR$D_IN = - WILL_FIRE_RL_rl_reset_begin ? - 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - MUX_requestR$write_1__VAL_2 ; - assign requestR$EN = WILL_FIRE_RL_rl_reset_begin || EN_req ; - - // register resultR - always@(WILL_FIRE_RL_rl_reset_begin or - EN_req or - WILL_FIRE_RL_rl_get_fpu_result or - MUX_resultR$write_1__VAL_3 or - WILL_FIRE_RL_doFCLASS_D or - MUX_resultR$write_1__VAL_4 or - WILL_FIRE_RL_doFMV_X_D or - MUX_resultR$write_1__VAL_5 or - WILL_FIRE_RL_doFMV_D_X or - WILL_FIRE_RL_doFLE_D or - MUX_resultR$write_1__VAL_7 or - WILL_FIRE_RL_doFLT_D or - MUX_resultR$write_1__VAL_8 or - WILL_FIRE_RL_doFEQ_D or - MUX_resultR$write_1__VAL_9 or - WILL_FIRE_RL_doFMAX_D or - MUX_resultR$write_1__VAL_10 or - WILL_FIRE_RL_doFMIN_D or - MUX_resultR$write_1__VAL_11 or - WILL_FIRE_RL_doFCVT_D_S or - MUX_resultR$write_1__VAL_12 or - WILL_FIRE_RL_doFCVT_S_D or - MUX_resultR$write_1__VAL_13 or - WILL_FIRE_RL_doFCVT_LU_D or - MUX_resultR$write_1__VAL_14 or - WILL_FIRE_RL_doFCVT_L_D or - MUX_resultR$write_1__VAL_15 or - WILL_FIRE_RL_doFCVT_D_LU or - MUX_resultR$write_1__VAL_16 or - WILL_FIRE_RL_doFCVT_D_L or - MUX_resultR$write_1__VAL_17 or - WILL_FIRE_RL_doFCVT_WU_D or - MUX_resultR$write_1__VAL_18 or - WILL_FIRE_RL_doFCVT_W_D or - MUX_resultR$write_1__VAL_19 or - WILL_FIRE_RL_doFCVT_D_WU or - MUX_resultR$write_1__VAL_20 or - WILL_FIRE_RL_doFCVT_D_W or - MUX_resultR$write_1__VAL_21 or - WILL_FIRE_RL_doFSGNJX_D or - MUX_resultR$write_1__VAL_22 or - WILL_FIRE_RL_doFSGNJN_D or - MUX_resultR$write_1__VAL_23 or - WILL_FIRE_RL_doFSGNJ_D or - MUX_resultR$write_1__VAL_24 or - WILL_FIRE_RL_doFCLASS_S or - MUX_resultR$write_1__VAL_25 or - WILL_FIRE_RL_doFLE_S or - MUX_resultR$write_1__VAL_26 or - WILL_FIRE_RL_doFLT_S or - MUX_resultR$write_1__VAL_27 or - WILL_FIRE_RL_doFEQ_S or - MUX_resultR$write_1__VAL_28 or - WILL_FIRE_RL_doFMV_X_W or - MUX_resultR$write_1__VAL_29 or - WILL_FIRE_RL_doFMV_W_X or - MUX_resultR$write_1__VAL_30 or - WILL_FIRE_RL_doFMAX_S or - MUX_resultR$write_1__VAL_31 or - WILL_FIRE_RL_doFMIN_S or - MUX_resultR$write_1__VAL_32 or - WILL_FIRE_RL_doFCVT_WU_S or - MUX_resultR$write_1__VAL_33 or - WILL_FIRE_RL_doFCVT_W_S or - MUX_resultR$write_1__VAL_34 or - WILL_FIRE_RL_doFCVT_LU_S or - MUX_resultR$write_1__VAL_35 or - WILL_FIRE_RL_doFCVT_L_S or - MUX_resultR$write_1__VAL_36 or - WILL_FIRE_RL_doFCVT_S_WU or - MUX_resultR$write_1__VAL_37 or - WILL_FIRE_RL_doFCVT_S_W or - MUX_resultR$write_1__VAL_38 or - WILL_FIRE_RL_doFCVT_S_LU or - MUX_resultR$write_1__VAL_39 or - WILL_FIRE_RL_doFCVT_S_L or - MUX_resultR$write_1__VAL_40 or - WILL_FIRE_RL_doFSGNJX_S or - MUX_resultR$write_1__VAL_41 or - WILL_FIRE_RL_doFSGNJN_S or - MUX_resultR$write_1__VAL_42 or - WILL_FIRE_RL_doFSGNJ_S or MUX_resultR$write_1__VAL_43) - case (1'b1) - WILL_FIRE_RL_rl_reset_begin || EN_req: - resultR$D_IN = 70'h0AAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_get_fpu_result: resultR$D_IN = MUX_resultR$write_1__VAL_3; - WILL_FIRE_RL_doFCLASS_D: resultR$D_IN = MUX_resultR$write_1__VAL_4; - WILL_FIRE_RL_doFMV_X_D: resultR$D_IN = MUX_resultR$write_1__VAL_5; - WILL_FIRE_RL_doFMV_D_X: resultR$D_IN = MUX_resultR$write_1__VAL_5; - WILL_FIRE_RL_doFLE_D: resultR$D_IN = MUX_resultR$write_1__VAL_7; - WILL_FIRE_RL_doFLT_D: resultR$D_IN = MUX_resultR$write_1__VAL_8; - WILL_FIRE_RL_doFEQ_D: resultR$D_IN = MUX_resultR$write_1__VAL_9; - WILL_FIRE_RL_doFMAX_D: resultR$D_IN = MUX_resultR$write_1__VAL_10; - WILL_FIRE_RL_doFMIN_D: resultR$D_IN = MUX_resultR$write_1__VAL_11; - WILL_FIRE_RL_doFCVT_D_S: resultR$D_IN = MUX_resultR$write_1__VAL_12; - WILL_FIRE_RL_doFCVT_S_D: resultR$D_IN = MUX_resultR$write_1__VAL_13; - WILL_FIRE_RL_doFCVT_LU_D: resultR$D_IN = MUX_resultR$write_1__VAL_14; - WILL_FIRE_RL_doFCVT_L_D: resultR$D_IN = MUX_resultR$write_1__VAL_15; - WILL_FIRE_RL_doFCVT_D_LU: resultR$D_IN = MUX_resultR$write_1__VAL_16; - WILL_FIRE_RL_doFCVT_D_L: resultR$D_IN = MUX_resultR$write_1__VAL_17; - WILL_FIRE_RL_doFCVT_WU_D: resultR$D_IN = MUX_resultR$write_1__VAL_18; - WILL_FIRE_RL_doFCVT_W_D: resultR$D_IN = MUX_resultR$write_1__VAL_19; - WILL_FIRE_RL_doFCVT_D_WU: resultR$D_IN = MUX_resultR$write_1__VAL_20; - WILL_FIRE_RL_doFCVT_D_W: resultR$D_IN = MUX_resultR$write_1__VAL_21; - WILL_FIRE_RL_doFSGNJX_D: resultR$D_IN = MUX_resultR$write_1__VAL_22; - WILL_FIRE_RL_doFSGNJN_D: resultR$D_IN = MUX_resultR$write_1__VAL_23; - WILL_FIRE_RL_doFSGNJ_D: resultR$D_IN = MUX_resultR$write_1__VAL_24; - WILL_FIRE_RL_doFCLASS_S: resultR$D_IN = MUX_resultR$write_1__VAL_25; - WILL_FIRE_RL_doFLE_S: resultR$D_IN = MUX_resultR$write_1__VAL_26; - WILL_FIRE_RL_doFLT_S: resultR$D_IN = MUX_resultR$write_1__VAL_27; - WILL_FIRE_RL_doFEQ_S: resultR$D_IN = MUX_resultR$write_1__VAL_28; - WILL_FIRE_RL_doFMV_X_W: resultR$D_IN = MUX_resultR$write_1__VAL_29; - WILL_FIRE_RL_doFMV_W_X: resultR$D_IN = MUX_resultR$write_1__VAL_30; - WILL_FIRE_RL_doFMAX_S: resultR$D_IN = MUX_resultR$write_1__VAL_31; - WILL_FIRE_RL_doFMIN_S: resultR$D_IN = MUX_resultR$write_1__VAL_32; - WILL_FIRE_RL_doFCVT_WU_S: resultR$D_IN = MUX_resultR$write_1__VAL_33; - WILL_FIRE_RL_doFCVT_W_S: resultR$D_IN = MUX_resultR$write_1__VAL_34; - WILL_FIRE_RL_doFCVT_LU_S: resultR$D_IN = MUX_resultR$write_1__VAL_35; - WILL_FIRE_RL_doFCVT_L_S: resultR$D_IN = MUX_resultR$write_1__VAL_36; - WILL_FIRE_RL_doFCVT_S_WU: resultR$D_IN = MUX_resultR$write_1__VAL_37; - WILL_FIRE_RL_doFCVT_S_W: resultR$D_IN = MUX_resultR$write_1__VAL_38; - WILL_FIRE_RL_doFCVT_S_LU: resultR$D_IN = MUX_resultR$write_1__VAL_39; - WILL_FIRE_RL_doFCVT_S_L: resultR$D_IN = MUX_resultR$write_1__VAL_40; - WILL_FIRE_RL_doFSGNJX_S: resultR$D_IN = MUX_resultR$write_1__VAL_41; - WILL_FIRE_RL_doFSGNJN_S: resultR$D_IN = MUX_resultR$write_1__VAL_42; - WILL_FIRE_RL_doFSGNJ_S: resultR$D_IN = MUX_resultR$write_1__VAL_43; - default: resultR$D_IN = 70'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign resultR$EN = - WILL_FIRE_RL_rl_reset_begin || EN_req || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFSGNJ_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFCVT_S_L || - WILL_FIRE_RL_doFCVT_S_LU || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_L_S || - WILL_FIRE_RL_doFCVT_LU_S || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFLE_S || - WILL_FIRE_RL_doFCLASS_S || - WILL_FIRE_RL_doFSGNJ_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_D_L || - WILL_FIRE_RL_doFCVT_D_LU || - WILL_FIRE_RL_doFCVT_L_D || - WILL_FIRE_RL_doFCVT_LU_D || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_rl_get_fpu_result ; - - // register stateR - always@(WILL_FIRE_RL_rl_reset_begin or - EN_req or - WILL_FIRE_RL_rl_get_fpu_result or - WILL_FIRE_RL_doFCLASS_D or - WILL_FIRE_RL_doFMV_X_D or - WILL_FIRE_RL_doFMV_D_X or - WILL_FIRE_RL_doFLE_D or - WILL_FIRE_RL_doFLT_D or - WILL_FIRE_RL_doFEQ_D or - WILL_FIRE_RL_doFMAX_D or - WILL_FIRE_RL_doFMIN_D or - WILL_FIRE_RL_doFCVT_D_S or - WILL_FIRE_RL_doFCVT_S_D or - WILL_FIRE_RL_doFCVT_LU_D or - WILL_FIRE_RL_doFCVT_L_D or - WILL_FIRE_RL_doFCVT_D_LU or - WILL_FIRE_RL_doFCVT_D_L or - WILL_FIRE_RL_doFCVT_WU_D or - WILL_FIRE_RL_doFCVT_W_D or - WILL_FIRE_RL_doFCVT_D_WU or - WILL_FIRE_RL_doFCVT_D_W or - WILL_FIRE_RL_doFSGNJX_D or - WILL_FIRE_RL_doFSGNJN_D or - WILL_FIRE_RL_doFSGNJ_D or - WILL_FIRE_RL_doFSQRT_D or - WILL_FIRE_RL_doFDIV_D or - WILL_FIRE_RL_doFNMSUB_D or - WILL_FIRE_RL_doFNMADD_D or - WILL_FIRE_RL_doFMSUB_D or - WILL_FIRE_RL_doFMADD_D or - WILL_FIRE_RL_doFMUL_D or - WILL_FIRE_RL_doFSUB_D or - WILL_FIRE_RL_doFADD_D or - WILL_FIRE_RL_doFCLASS_S or - WILL_FIRE_RL_doFLE_S or - WILL_FIRE_RL_doFLT_S or - WILL_FIRE_RL_doFEQ_S or - WILL_FIRE_RL_doFMV_X_W or - WILL_FIRE_RL_doFMV_W_X or - WILL_FIRE_RL_doFMAX_S or - WILL_FIRE_RL_doFMIN_S or - WILL_FIRE_RL_doFCVT_WU_S or - WILL_FIRE_RL_doFCVT_W_S or - WILL_FIRE_RL_doFCVT_LU_S or - WILL_FIRE_RL_doFCVT_L_S or - WILL_FIRE_RL_doFCVT_S_WU or - WILL_FIRE_RL_doFCVT_S_W or - WILL_FIRE_RL_doFCVT_S_LU or - WILL_FIRE_RL_doFCVT_S_L or - WILL_FIRE_RL_doFSGNJX_S or - WILL_FIRE_RL_doFSGNJN_S or - WILL_FIRE_RL_doFSGNJ_S or - WILL_FIRE_RL_doFSQRT_S or - WILL_FIRE_RL_doFDIV_S or - WILL_FIRE_RL_doFNMSUB_S or - WILL_FIRE_RL_doFNMADD_S or - WILL_FIRE_RL_doFMSUB_S or - WILL_FIRE_RL_doFMADD_S or - WILL_FIRE_RL_doFMUL_S or - WILL_FIRE_RL_doFSUB_S or - WILL_FIRE_RL_doFADD_S or WILL_FIRE_RL_rl_reset_end) - case (1'b1) - WILL_FIRE_RL_rl_reset_begin: stateR$D_IN = 2'd0; - EN_req: stateR$D_IN = 2'd1; - WILL_FIRE_RL_rl_get_fpu_result || WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_LU_D || - WILL_FIRE_RL_doFCVT_L_D || - WILL_FIRE_RL_doFCVT_D_LU || - WILL_FIRE_RL_doFCVT_D_L || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJ_D: - stateR$D_IN = 2'd3; - WILL_FIRE_RL_doFSQRT_D || WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFADD_D: - stateR$D_IN = 2'd2; - WILL_FIRE_RL_doFCLASS_S || WILL_FIRE_RL_doFLE_S || WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_LU_S || - WILL_FIRE_RL_doFCVT_L_S || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFCVT_S_LU || - WILL_FIRE_RL_doFCVT_S_L || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJ_S: - stateR$D_IN = 2'd3; - WILL_FIRE_RL_doFSQRT_S || WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFADD_S: - stateR$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_end: stateR$D_IN = 2'd1; - default: stateR$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign stateR$EN = - WILL_FIRE_RL_rl_reset_begin || WILL_FIRE_RL_rl_reset_end || - EN_req || - WILL_FIRE_RL_doFSQRT_D || - WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFADD_D || - WILL_FIRE_RL_doFSQRT_S || - WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFADD_S || - WILL_FIRE_RL_rl_get_fpu_result || - WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_LU_D || - WILL_FIRE_RL_doFCVT_L_D || - WILL_FIRE_RL_doFCVT_D_LU || - WILL_FIRE_RL_doFCVT_D_L || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJ_D || - WILL_FIRE_RL_doFCLASS_S || - WILL_FIRE_RL_doFLE_S || - WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_LU_S || - WILL_FIRE_RL_doFCVT_L_S || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFCVT_S_LU || - WILL_FIRE_RL_doFCVT_S_L || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJ_S ; - - // submodule fpu - always@(WILL_FIRE_RL_doFADD_S or - MUX_fpu$server_core_request_put_1__VAL_1 or - WILL_FIRE_RL_doFSUB_S or - MUX_fpu$server_core_request_put_1__VAL_2 or - WILL_FIRE_RL_doFMUL_S or - MUX_fpu$server_core_request_put_1__VAL_3 or - WILL_FIRE_RL_doFMADD_S or - MUX_fpu$server_core_request_put_1__VAL_4 or - WILL_FIRE_RL_doFMSUB_S or - MUX_fpu$server_core_request_put_1__VAL_5 or - WILL_FIRE_RL_doFNMADD_S or - MUX_fpu$server_core_request_put_1__VAL_6 or - WILL_FIRE_RL_doFNMSUB_S or - MUX_fpu$server_core_request_put_1__VAL_7 or - WILL_FIRE_RL_doFDIV_S or - MUX_fpu$server_core_request_put_1__VAL_8 or - WILL_FIRE_RL_doFSQRT_S or - MUX_fpu$server_core_request_put_1__VAL_9 or - WILL_FIRE_RL_doFADD_D or - MUX_fpu$server_core_request_put_1__VAL_10 or - WILL_FIRE_RL_doFSUB_D or - MUX_fpu$server_core_request_put_1__VAL_11 or - WILL_FIRE_RL_doFMUL_D or - MUX_fpu$server_core_request_put_1__VAL_12 or - WILL_FIRE_RL_doFMADD_D or - MUX_fpu$server_core_request_put_1__VAL_13 or - WILL_FIRE_RL_doFMSUB_D or - MUX_fpu$server_core_request_put_1__VAL_14 or - WILL_FIRE_RL_doFNMADD_D or - MUX_fpu$server_core_request_put_1__VAL_15 or - WILL_FIRE_RL_doFNMSUB_D or - MUX_fpu$server_core_request_put_1__VAL_16 or - WILL_FIRE_RL_doFDIV_D or - MUX_fpu$server_core_request_put_1__VAL_17 or - WILL_FIRE_RL_doFSQRT_D or MUX_fpu$server_core_request_put_1__VAL_18) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_doFADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_1; - WILL_FIRE_RL_doFSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_2; - WILL_FIRE_RL_doFMUL_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_3; - WILL_FIRE_RL_doFMADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_4; - WILL_FIRE_RL_doFMSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_5; - WILL_FIRE_RL_doFNMADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_6; - WILL_FIRE_RL_doFNMSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_7; - WILL_FIRE_RL_doFDIV_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_8; - WILL_FIRE_RL_doFSQRT_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_9; - WILL_FIRE_RL_doFADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_10; - WILL_FIRE_RL_doFSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_11; - WILL_FIRE_RL_doFMUL_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_12; - WILL_FIRE_RL_doFMADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_13; - WILL_FIRE_RL_doFMSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_14; - WILL_FIRE_RL_doFNMADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_15; - WILL_FIRE_RL_doFNMSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_16; - WILL_FIRE_RL_doFDIV_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_17; - WILL_FIRE_RL_doFSQRT_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_18; - default: fpu$server_core_request_put = - 202'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fpu$EN_server_core_request_put = - WILL_FIRE_RL_doFADD_S || WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFSQRT_S || - WILL_FIRE_RL_doFADD_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFSQRT_D ; - assign fpu$EN_server_core_response_get = MUX_dw_result$wset_1__SEL_1 ; - assign fpu$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_begin ; - assign fpu$EN_server_reset_response_get = CAN_FIRE_RL_rl_reset_end ; - - // submodule frmFpuF - assign frmFpuF$D_IN = 1'b0 ; - assign frmFpuF$ENQ = 1'b0 ; - assign frmFpuF$DEQ = 1'b0 ; - assign frmFpuF$CLR = CAN_FIRE_RL_rl_reset_begin ; - - // submodule resetReqsF - assign resetReqsF$ENQ = EN_server_reset_request_put ; - assign resetReqsF$DEQ = - fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ; - assign resetReqsF$CLR = 1'b0 ; - - // submodule resetRspsF - assign resetRspsF$ENQ = - fpu$RDY_server_reset_response_get && resetRspsF$FULL_N && - stateR == 2'd0 ; - assign resetRspsF$DEQ = EN_server_reset_response_get ; - assign resetRspsF$CLR = 1'b0 ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q114 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d3542 ? - _theResult___snd__h118614 : - _theResult____h110444 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q151 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d4819 ? - _theResult___snd__h177747 : - _theResult____h169448 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q119 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d3986 ? - _theResult___snd__h136467 : - _theResult____h128168 ; - assign IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q148 = - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4499 ? - _theResult___snd__h168100 : - 57'd0 ; - assign IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q154 = - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4892 ? - _theResult___snd__h168100 : - _theResult___snd__h186499 ; - assign IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q116 = - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d3664 ? - _theResult___snd__h127226 : - 57'd0 ; - assign IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q122 = - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4059 ? - _theResult___snd__h127226 : - _theResult___snd__h145103 ; - assign IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_9_ETC___d4244 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - ((_theResult___fst_exp__h118551 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10454_0b0_requestR_BIT_191_0b1_reque_ETC__q140 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q141)) : - ((_theResult___fst_exp__h127237 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard19189_0b0_requestR_BIT_191_0b1_reque_ETC__q142 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q143)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1331 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9167_0b0_requestR_BIT_159_0b1_reques_ETC__q40 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q41) : - ((x__h29709[7:0] == 8'd255) ? - requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9694_0b0_requestR_BIT_159_0b1_reques_ETC__q42 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q43)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1481 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 ? - guard__h29167 != 2'b0 : - x__h29709[7:0] != 8'd255 && guard__h29694 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2300 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9814_0b0_requestR_BIT_159_0b1_reques_ETC__q69 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q70) : - ((x__h60559[10:0] == 11'd2047) ? - requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard0544_0b0_requestR_BIT_159_0b1_reques_ETC__q71 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q72)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2415 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 ? - guard__h59814 != 2'b0 : - x__h60559[10:0] != 11'd2047 && guard__h60544 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1668 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530 ? - guard__h35283 != 2'b0 : - x__h35824[7:0] != 8'd255 && guard__h35809 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d2597 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461 ? - guard__h69455 != 2'b0 : - x__h70199[10:0] != 11'd2047 && guard__h70184 != 2'b0 ; - assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2831 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3135_0b0_requestR_BIT_191_0b1_reques_ETC__q94 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q95) : - ((x__h83880[10:0] == 11'd2047) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3865_0b0_requestR_BIT_191_0b1_reques_ETC__q96 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q97)) ; - assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2948 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 ? - guard__h83135 != 2'b0 : - x__h83880[10:0] != 11'd2047 && guard__h83865 != 2'b0 ; - assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d474 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2228_0b0_requestR_BIT_191_0b1_reques_ETC__q10 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11) : - ((x__h12773[7:0] == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2758_0b0_requestR_BIT_191_0b1_reques_ETC__q12 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q13)) ; - assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d656 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 ? - guard__h12228 != 2'b0 : - x__h12773[7:0] != 8'd255 && guard__h12758 != 2'b0 ; - assign IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d1128 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926 ? - guard__h22795 != 2'b0 : - x__h23336[7:0] != 8'd255 && guard__h23321 != 2'b0 ; - assign IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d3100 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963 ? - guard__h94092 != 2'b0 : - x__h94836[10:0] != 11'd2047 && guard__h94821 != 2'b0 ; - assign IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d3540 = - (_theResult____h110444[56] ? - 6'd0 : - (_theResult____h110444[55] ? - 6'd1 : - (_theResult____h110444[54] ? - 6'd2 : - (_theResult____h110444[53] ? - 6'd3 : - (_theResult____h110444[52] ? - 6'd4 : - (_theResult____h110444[51] ? - 6'd5 : - (_theResult____h110444[50] ? - 6'd6 : - (_theResult____h110444[49] ? - 6'd7 : - (_theResult____h110444[48] ? - 6'd8 : - (_theResult____h110444[47] ? - 6'd9 : - (_theResult____h110444[46] ? - 6'd10 : - (_theResult____h110444[45] ? - 6'd11 : - (_theResult____h110444[44] ? - 6'd12 : - (_theResult____h110444[43] ? - 6'd13 : - (_theResult____h110444[42] ? - 6'd14 : - (_theResult____h110444[41] ? - 6'd15 : - (_theResult____h110444[40] ? - 6'd16 : - (_theResult____h110444[39] ? - 6'd17 : - (_theResult____h110444[38] ? - 6'd18 : - (_theResult____h110444[37] ? - 6'd19 : - (_theResult____h110444[36] ? - 6'd20 : - (_theResult____h110444[35] ? - 6'd21 : - (_theResult____h110444[34] ? - 6'd22 : - (_theResult____h110444[33] ? - 6'd23 : - (_theResult____h110444[32] ? - 6'd24 : - (_theResult____h110444[31] ? - 6'd25 : - (_theResult____h110444[30] ? - 6'd26 : - (_theResult____h110444[29] ? - 6'd27 : - (_theResult____h110444[28] ? - 6'd28 : - (_theResult____h110444[27] ? - 6'd29 : - (_theResult____h110444[26] ? - 6'd30 : - (_theResult____h110444[25] ? - 6'd31 : - (_theResult____h110444[24] ? - 6'd32 : - (_theResult____h110444[23] ? - 6'd33 : - (_theResult____h110444[22] ? - 6'd34 : - (_theResult____h110444[21] ? - 6'd35 : - (_theResult____h110444[20] ? - 6'd36 : - (_theResult____h110444[19] ? - 6'd37 : - (_theResult____h110444[18] ? - 6'd38 : - (_theResult____h110444[17] ? - 6'd39 : - (_theResult____h110444[16] ? - 6'd40 : - (_theResult____h110444[15] ? - 6'd41 : - (_theResult____h110444[14] ? - 6'd42 : - (_theResult____h110444[13] ? - 6'd43 : - (_theResult____h110444[12] ? - 6'd44 : - (_theResult____h110444[11] ? - 6'd45 : - (_theResult____h110444[10] ? - 6'd46 : - (_theResult____h110444[9] ? - 6'd47 : - (_theResult____h110444[8] ? - 6'd48 : - (_theResult____h110444[7] ? - 6'd49 : - (_theResult____h110444[6] ? - 6'd50 : - (_theResult____h110444[5] ? - 6'd51 : - (_theResult____h110444[4] ? - 6'd52 : - (_theResult____h110444[3] ? - 6'd53 : - (_theResult____h110444[2] ? - 6'd54 : - (_theResult____h110444[1] ? - 6'd55 : - (_theResult____h110444[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d4817 = - (_theResult____h169448[56] ? - 6'd0 : - (_theResult____h169448[55] ? - 6'd1 : - (_theResult____h169448[54] ? - 6'd2 : - (_theResult____h169448[53] ? - 6'd3 : - (_theResult____h169448[52] ? - 6'd4 : - (_theResult____h169448[51] ? - 6'd5 : - (_theResult____h169448[50] ? - 6'd6 : - (_theResult____h169448[49] ? - 6'd7 : - (_theResult____h169448[48] ? - 6'd8 : - (_theResult____h169448[47] ? - 6'd9 : - (_theResult____h169448[46] ? - 6'd10 : - (_theResult____h169448[45] ? - 6'd11 : - (_theResult____h169448[44] ? - 6'd12 : - (_theResult____h169448[43] ? - 6'd13 : - (_theResult____h169448[42] ? - 6'd14 : - (_theResult____h169448[41] ? - 6'd15 : - (_theResult____h169448[40] ? - 6'd16 : - (_theResult____h169448[39] ? - 6'd17 : - (_theResult____h169448[38] ? - 6'd18 : - (_theResult____h169448[37] ? - 6'd19 : - (_theResult____h169448[36] ? - 6'd20 : - (_theResult____h169448[35] ? - 6'd21 : - (_theResult____h169448[34] ? - 6'd22 : - (_theResult____h169448[33] ? - 6'd23 : - (_theResult____h169448[32] ? - 6'd24 : - (_theResult____h169448[31] ? - 6'd25 : - (_theResult____h169448[30] ? - 6'd26 : - (_theResult____h169448[29] ? - 6'd27 : - (_theResult____h169448[28] ? - 6'd28 : - (_theResult____h169448[27] ? - 6'd29 : - (_theResult____h169448[26] ? - 6'd30 : - (_theResult____h169448[25] ? - 6'd31 : - (_theResult____h169448[24] ? - 6'd32 : - (_theResult____h169448[23] ? - 6'd33 : - (_theResult____h169448[22] ? - 6'd34 : - (_theResult____h169448[21] ? - 6'd35 : - (_theResult____h169448[20] ? - 6'd36 : - (_theResult____h169448[19] ? - 6'd37 : - (_theResult____h169448[18] ? - 6'd38 : - (_theResult____h169448[17] ? - 6'd39 : - (_theResult____h169448[16] ? - 6'd40 : - (_theResult____h169448[15] ? - 6'd41 : - (_theResult____h169448[14] ? - 6'd42 : - (_theResult____h169448[13] ? - 6'd43 : - (_theResult____h169448[12] ? - 6'd44 : - (_theResult____h169448[11] ? - 6'd45 : - (_theResult____h169448[10] ? - 6'd46 : - (_theResult____h169448[9] ? - 6'd47 : - (_theResult____h169448[8] ? - 6'd48 : - (_theResult____h169448[7] ? - 6'd49 : - (_theResult____h169448[6] ? - 6'd50 : - (_theResult____h169448[5] ? - 6'd51 : - (_theResult____h169448[4] ? - 6'd52 : - (_theResult____h169448[3] ? - 6'd53 : - (_theResult____h169448[2] ? - 6'd54 : - (_theResult____h169448[1] ? - 6'd55 : - (_theResult____h169448[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d3984 = - (_theResult____h128168[56] ? - 6'd0 : - (_theResult____h128168[55] ? - 6'd1 : - (_theResult____h128168[54] ? - 6'd2 : - (_theResult____h128168[53] ? - 6'd3 : - (_theResult____h128168[52] ? - 6'd4 : - (_theResult____h128168[51] ? - 6'd5 : - (_theResult____h128168[50] ? - 6'd6 : - (_theResult____h128168[49] ? - 6'd7 : - (_theResult____h128168[48] ? - 6'd8 : - (_theResult____h128168[47] ? - 6'd9 : - (_theResult____h128168[46] ? - 6'd10 : - (_theResult____h128168[45] ? - 6'd11 : - (_theResult____h128168[44] ? - 6'd12 : - (_theResult____h128168[43] ? - 6'd13 : - (_theResult____h128168[42] ? - 6'd14 : - (_theResult____h128168[41] ? - 6'd15 : - (_theResult____h128168[40] ? - 6'd16 : - (_theResult____h128168[39] ? - 6'd17 : - (_theResult____h128168[38] ? - 6'd18 : - (_theResult____h128168[37] ? - 6'd19 : - (_theResult____h128168[36] ? - 6'd20 : - (_theResult____h128168[35] ? - 6'd21 : - (_theResult____h128168[34] ? - 6'd22 : - (_theResult____h128168[33] ? - 6'd23 : - (_theResult____h128168[32] ? - 6'd24 : - (_theResult____h128168[31] ? - 6'd25 : - (_theResult____h128168[30] ? - 6'd26 : - (_theResult____h128168[29] ? - 6'd27 : - (_theResult____h128168[28] ? - 6'd28 : - (_theResult____h128168[27] ? - 6'd29 : - (_theResult____h128168[26] ? - 6'd30 : - (_theResult____h128168[25] ? - 6'd31 : - (_theResult____h128168[24] ? - 6'd32 : - (_theResult____h128168[23] ? - 6'd33 : - (_theResult____h128168[22] ? - 6'd34 : - (_theResult____h128168[21] ? - 6'd35 : - (_theResult____h128168[20] ? - 6'd36 : - (_theResult____h128168[19] ? - 6'd37 : - (_theResult____h128168[18] ? - 6'd38 : - (_theResult____h128168[17] ? - 6'd39 : - (_theResult____h128168[16] ? - 6'd40 : - (_theResult____h128168[15] ? - 6'd41 : - (_theResult____h128168[14] ? - 6'd42 : - (_theResult____h128168[13] ? - 6'd43 : - (_theResult____h128168[12] ? - 6'd44 : - (_theResult____h128168[11] ? - 6'd45 : - (_theResult____h128168[10] ? - 6'd46 : - (_theResult____h128168[9] ? - 6'd47 : - (_theResult____h128168[8] ? - 6'd48 : - (_theResult____h128168[7] ? - 6'd49 : - (_theResult____h128168[6] ? - 6'd50 : - (_theResult____h128168[5] ? - 6'd51 : - (_theResult____h128168[4] ? - 6'd52 : - (_theResult____h128168[3] ? - 6'd53 : - (_theResult____h128168[2] ? - 6'd54 : - (_theResult____h128168[1] ? - 6'd55 : - (_theResult____h128168[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d5061 = - (_theResult___fst_exp__h177684 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard69458_0b0_requestR_BITS_191_TO_160_E_ETC__q164 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q165) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3599 = - (guard__h110454 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h118551 : - _theResult___exp__h119077 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3601 = - (guard__h110454 == 2'b0) ? - _theResult___fst_exp__h118551 : - (requestR[191] ? - _theResult___exp__h119077 : - _theResult___fst_exp__h118551) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4146 = - (guard__h110454 == 2'b0 || requestR[191]) ? - sfdin__h118545[56:34] : - _theResult___sfd__h119078 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4148 = - (guard__h110454 == 2'b0) ? - sfdin__h118545[56:34] : - (requestR[191] ? - _theResult___sfd__h119078 : - sfdin__h118545[56:34]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4876 = - (guard__h169458 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h177684 : - _theResult___exp__h178413 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4878 = - (guard__h169458 == 2'b0) ? - _theResult___fst_exp__h177684 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h178413 : - _theResult___fst_exp__h177684) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5005 = - (guard__h169458 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - sfdin__h177678[56:5] : - _theResult___sfd__h178414 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5007 = - (guard__h169458 == 2'b0) ? - sfdin__h177678[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h178414 : - sfdin__h177678[56:5]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4043 = - (guard__h128178 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h136404 : - _theResult___exp__h136930 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4045 = - (guard__h128178 == 2'b0) ? - _theResult___fst_exp__h136404 : - (requestR[191] ? - _theResult___exp__h136930 : - _theResult___fst_exp__h136404) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4192 = - (guard__h128178 == 2'b0 || requestR[191]) ? - sfdin__h136398[56:34] : - _theResult___sfd__h136931 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4194 = - (guard__h128178 == 2'b0) ? - sfdin__h136398[56:34] : - (requestR[191] ? - _theResult___sfd__h136931 : - sfdin__h136398[56:34]) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4551 = - (guard__h160150 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h168111 : - _theResult___exp__h168766 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4553 = - (guard__h160150 == 2'b0) ? - _theResult___fst_exp__h168111 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h168766 : - _theResult___fst_exp__h168111) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4945 = - (guard__h178525 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h186515 : - _theResult___exp__h187195 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4947 = - (guard__h178525 == 2'b0) ? - _theResult___fst_exp__h186515 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h187195 : - _theResult___fst_exp__h186515) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4978 = - (guard__h160150 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___snd__h168062[56:5] : - _theResult___sfd__h168767 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4980 = - (guard__h160150 == 2'b0) ? - _theResult___snd__h168062[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h168767 : - _theResult___snd__h168062[56:5]) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5024 = - (guard__h178525 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___snd__h186461[56:5] : - _theResult___sfd__h187196 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5026 = - (guard__h178525 == 2'b0) ? - _theResult___snd__h186461[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h187196 : - _theResult___snd__h186461[56:5]) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3716 = - (guard__h119189 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h127237 : - _theResult___exp__h127689 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3718 = - (guard__h119189 == 2'b0) ? - _theResult___fst_exp__h127237 : - (requestR[191] ? - _theResult___exp__h127689 : - _theResult___fst_exp__h127237) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4112 = - (guard__h137042 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h145119 : - _theResult___exp__h145596 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4114 = - (guard__h137042 == 2'b0) ? - _theResult___fst_exp__h145119 : - (requestR[191] ? - _theResult___exp__h145596 : - _theResult___fst_exp__h145119) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4165 = - (guard__h119189 == 2'b0 || requestR[191]) ? - _theResult___snd__h127188[56:34] : - _theResult___sfd__h127690 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4167 = - (guard__h119189 == 2'b0) ? - _theResult___snd__h127188[56:34] : - (requestR[191] ? - _theResult___sfd__h127690 : - _theResult___snd__h127188[56:34]) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4211 = - (guard__h137042 == 2'b0 || requestR[191]) ? - _theResult___snd__h145065[56:34] : - _theResult___sfd__h145597 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4213 = - (guard__h137042 == 2'b0) ? - _theResult___snd__h145065[56:34] : - (requestR[191] ? - _theResult___sfd__h145597 : - _theResult___snd__h145065[56:34]) ; - assign IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d5069 = - (_theResult___fst_exp__h186515 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard78525_0b0_requestR_BITS_191_TO_160_E_ETC__q166 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q167) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1353 = - (guard__h29167 == 2'b0) ? - 8'd0 : - (requestR[159] ? _theResult___exp__h29580 : 8'd0) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1379 = - (guard__h29694 == 2'b0 || requestR[159]) ? - x__h29709[7:0] : - _theResult___exp__h30133 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1381 = - (guard__h29694 == 2'b0) ? - x__h29709[7:0] : - (requestR[159] ? _theResult___exp__h30133 : x__h29709[7:0]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1402 = - (guard__h29167 == 2'b0 || requestR[159]) ? - sfd___3__h29157[31:9] : - _theResult___sfd__h29581 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1404 = - (guard__h29167 == 2'b0) ? - sfd___3__h29157[31:9] : - (requestR[159] ? - _theResult___sfd__h29581 : - sfd___3__h29157[31:9]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1420 = - (guard__h29694 == 2'b0 || requestR[159]) ? - sfd___3__h29157[30:8] : - _theResult___sfd__h30134 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1422 = - (guard__h29694 == 2'b0) ? - sfd___3__h29157[30:8] : - (requestR[159] ? - _theResult___sfd__h30134 : - sfd___3__h29157[30:8]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2321 = - (guard__h59814 == 2'b0) ? - 11'd0 : - (requestR[159] ? _theResult___exp__h60430 : 11'd0) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2347 = - (guard__h60544 == 2'b0 || requestR[159]) ? - x__h60559[10:0] : - _theResult___exp__h61186 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2349 = - (guard__h60544 == 2'b0) ? - x__h60559[10:0] : - (requestR[159] ? _theResult___exp__h61186 : x__h60559[10:0]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2370 = - (guard__h59814 == 2'b0 || requestR[159]) ? - sfd___3__h59804[54:3] : - _theResult___sfd__h60431 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2372 = - (guard__h59814 == 2'b0) ? - sfd___3__h59804[54:3] : - (requestR[159] ? - _theResult___sfd__h60431 : - sfd___3__h59804[54:3]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2388 = - (guard__h60544 == 2'b0 || requestR[159]) ? - sfd___3__h59804[53:2] : - _theResult___sfd__h61187 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2390 = - (guard__h60544 == 2'b0) ? - sfd___3__h59804[53:2] : - (requestR[159] ? - _theResult___sfd__h61187 : - sfd___3__h59804[53:2]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2852 = - (guard__h83135 == 2'b0) ? - 11'd0 : - (requestR[191] ? _theResult___exp__h83751 : 11'd0) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2878 = - (guard__h83865 == 2'b0 || requestR[191]) ? - x__h83880[10:0] : - _theResult___exp__h84507 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2880 = - (guard__h83865 == 2'b0) ? - x__h83880[10:0] : - (requestR[191] ? _theResult___exp__h84507 : x__h83880[10:0]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2901 = - (guard__h83135 == 2'b0 || requestR[191]) ? - sfd___3__h12218[63:12] : - _theResult___sfd__h83752 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2903 = - (guard__h83135 == 2'b0) ? - sfd___3__h12218[63:12] : - (requestR[191] ? - _theResult___sfd__h83752 : - sfd___3__h12218[63:12]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2919 = - (guard__h83865 == 2'b0 || requestR[191]) ? - sfd___3__h12218[62:11] : - _theResult___sfd__h84508 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2921 = - (guard__h83865 == 2'b0) ? - sfd___3__h12218[62:11] : - (requestR[191] ? - _theResult___sfd__h84508 : - sfd___3__h12218[62:11]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d496 = - (guard__h12228 == 2'b0) ? - 8'd0 : - (requestR[191] ? _theResult___exp__h12644 : 8'd0) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d522 = - (guard__h12758 == 2'b0 || requestR[191]) ? - x__h12773[7:0] : - _theResult___exp__h13197 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d524 = - (guard__h12758 == 2'b0) ? - x__h12773[7:0] : - (requestR[191] ? _theResult___exp__h13197 : x__h12773[7:0]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d545 = - (guard__h12228 == 2'b0 || requestR[191]) ? - sfd___3__h12218[63:41] : - _theResult___sfd__h12645 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d547 = - (guard__h12228 == 2'b0) ? - sfd___3__h12218[63:41] : - (requestR[191] ? - _theResult___sfd__h12645 : - sfd___3__h12218[63:41]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d563 = - (guard__h12758 == 2'b0 || requestR[191]) ? - sfd___3__h12218[62:40] : - _theResult___sfd__h13198 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d565 = - (guard__h12758 == 2'b0) ? - sfd___3__h12218[62:40] : - (requestR[191] ? - _theResult___sfd__h13198 : - sfd___3__h12218[62:40]) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2048 = - (sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316[22] || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2017) ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - (IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d2021 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2046) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2052 = - (sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316 != 23'd0 && - !sV2_sfd__h1316[22]) ? - res__h42520 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2051 ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2061 = - IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d2021 ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2060 ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2063 = - (sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316[22]) ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - (IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2017 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2061) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2067 = - (sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316 != 23'd0 && - !sV2_sfd__h1316[22]) ? - res__h42520 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2066 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1764 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1693 : - ((sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - 64'd0 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1762) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1822 = - (sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - 64'd0 : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793[19] ? - 64'hFFFFFFFFFFFFFFFF : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1820) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1911 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1848 : - ((sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - 32'd0 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1909) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1964 = - (sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - 32'd0 : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935[19] ? - 32'hFFFFFFFF : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1962) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2049 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22]) ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2048 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2051 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22] && - sV2_exp__h1315 == 8'd255 && - sV2_sfd__h1316[22]) ? - 64'hFFFFFFFF7FC00000 : - { 32'hFFFFFFFF, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2049 } ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2053 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22]) ? - res__h42283 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2052 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2064 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22]) ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2063 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2066 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22] && - sV2_exp__h1315 == 8'd255 && - sV2_sfd__h1316[22]) ? - 64'hFFFFFFFF7FC00000 : - { 32'hFFFFFFFF, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2064 } ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2068 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22]) ? - res__h42283 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2067 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2132 = - (sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - res___1__h50538 : - ((sV1_exp__h1212 == 8'd0) ? res___1__h50557 : res__h50573) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2133 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0) ? - res___1__h50528 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2132 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 = - ((sV1_exp__h1212 == 8'd0) ? - (sV1_sfd__h1213[22] ? - 6'd2 : - (sV1_sfd__h1213[21] ? - 6'd3 : - (sV1_sfd__h1213[20] ? - 6'd4 : - (sV1_sfd__h1213[19] ? - 6'd5 : - (sV1_sfd__h1213[18] ? - 6'd6 : - (sV1_sfd__h1213[17] ? - 6'd7 : - (sV1_sfd__h1213[16] ? - 6'd8 : - (sV1_sfd__h1213[15] ? - 6'd9 : - (sV1_sfd__h1213[14] ? - 6'd10 : - (sV1_sfd__h1213[13] ? - 6'd11 : - (sV1_sfd__h1213[12] ? - 6'd12 : - (sV1_sfd__h1213[11] ? - 6'd13 : - (sV1_sfd__h1213[10] ? - 6'd14 : - (sV1_sfd__h1213[9] ? - 6'd15 : - (sV1_sfd__h1213[8] ? - 6'd16 : - (sV1_sfd__h1213[7] ? - 6'd17 : - (sV1_sfd__h1213[6] ? - 6'd18 : - (sV1_sfd__h1213[5] ? - 6'd19 : - (sV1_sfd__h1213[4] ? - 6'd20 : - (sV1_sfd__h1213[3] ? - 6'd21 : - (sV1_sfd__h1213[2] ? - 6'd22 : - (sV1_sfd__h1213[1] ? - 6'd23 : - (sV1_sfd__h1213[0] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5037 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0) ? - _theResult___snd_fst_sfd__h149185 : - _theResult___fst_sfd__h187312 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5073 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - (sV1_exp__h1212 == 8'd255 || sV1_exp__h1212 == 8'd0) && - sV1_sfd__h1213 == 23'd0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((sV1_exp__h1212 == 8'd0) ? - IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d5053 : - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5071) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5108 = - (sV1_exp__h1212 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 && - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087[4] : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 && - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104[4] ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5111 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0) ? - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22] : - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5108 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5118 = - (sV1_exp__h1212 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 && - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087[3] : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 && - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104[3] ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5132 = - (sV1_exp__h1212 == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 || - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087[2] : - !SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 || - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5130 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5144 = - (sV1_exp__h1212 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 && - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 || - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087[1]) : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 && - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5142 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5156 = - (sV1_exp__h1212 == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 || - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087[0] : - !SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 || - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5154 ; - assign IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1270 = - sfd__h24253[31] ? - 6'd0 : - (sfd__h24253[30] ? - 6'd1 : - (sfd__h24253[29] ? - 6'd2 : - (sfd__h24253[28] ? - 6'd3 : - (sfd__h24253[27] ? - 6'd4 : - (sfd__h24253[26] ? - 6'd5 : - (sfd__h24253[25] ? - 6'd6 : - (sfd__h24253[24] ? - 6'd7 : - (sfd__h24253[23] ? - 6'd8 : - (sfd__h24253[22] ? - 6'd9 : - (sfd__h24253[21] ? - 6'd10 : - (sfd__h24253[20] ? - 6'd11 : - (sfd__h24253[19] ? - 6'd12 : - (sfd__h24253[18] ? - 6'd13 : - (sfd__h24253[17] ? - 6'd14 : - (sfd__h24253[16] ? - 6'd15 : - (sfd__h24253[15] ? - 6'd16 : - (sfd__h24253[14] ? - 6'd17 : - (sfd__h24253[13] ? - 6'd18 : - (sfd__h24253[12] ? - 6'd19 : - (sfd__h24253[11] ? - 6'd20 : - (sfd__h24253[10] ? - 6'd21 : - (sfd__h24253[9] ? - 6'd22 : - (sfd__h24253[8] ? - 6'd23 : - (sfd__h24253[7] ? - 6'd24 : - (sfd__h24253[6] ? - 6'd25 : - (sfd__h24253[5] ? - 6'd26 : - (sfd__h24253[4] ? - 6'd27 : - (sfd__h24253[3] ? - 6'd28 : - (sfd__h24253[2] ? - 6'd29 : - (sfd__h24253[1] ? - 6'd30 : - (sfd__h24253[0] ? - 6'd31 : - 6'd32))))))))))))))))))))))))))))))) ; - assign IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d2241 = - sfd__h24253[31] ? - 6'd0 : - (sfd__h24253[30] ? - 6'd1 : - (sfd__h24253[29] ? - 6'd2 : - (sfd__h24253[28] ? - 6'd3 : - (sfd__h24253[27] ? - 6'd4 : - (sfd__h24253[26] ? - 6'd5 : - (sfd__h24253[25] ? - 6'd6 : - (sfd__h24253[24] ? - 6'd7 : - (sfd__h24253[23] ? - 6'd8 : - (sfd__h24253[22] ? - 6'd9 : - (sfd__h24253[21] ? - 6'd10 : - (sfd__h24253[20] ? - 6'd11 : - (sfd__h24253[19] ? - 6'd12 : - (sfd__h24253[18] ? - 6'd13 : - (sfd__h24253[17] ? - 6'd14 : - (sfd__h24253[16] ? - 6'd15 : - (sfd__h24253[15] ? - 6'd16 : - (sfd__h24253[14] ? - 6'd17 : - (sfd__h24253[13] ? - 6'd18 : - (sfd__h24253[12] ? - 6'd19 : - (sfd__h24253[11] ? - 6'd20 : - (sfd__h24253[10] ? - 6'd21 : - (sfd__h24253[9] ? - 6'd22 : - (sfd__h24253[8] ? - 6'd23 : - (sfd__h24253[7] ? - 6'd24 : - (sfd__h24253[6] ? - 6'd25 : - (sfd__h24253[5] ? - 6'd26 : - (sfd__h24253[4] ? - 6'd27 : - (sfd__h24253[3] ? - 6'd28 : - (sfd__h24253[2] ? - 6'd29 : - (sfd__h24253[1] ? - 6'd30 : - (sfd__h24253[0] ? - 6'd31 : - 6'd55))))))))))))))))))))))))))))))) ; - assign IF_IF_requestR_3_BIT_191_47_THEN_NEG_requestR__ETC___d404 = - sfd__h2613[63] ? - 7'd0 : - (sfd__h2613[62] ? - 7'd1 : - (sfd__h2613[61] ? - 7'd2 : - (sfd__h2613[60] ? - 7'd3 : - (sfd__h2613[59] ? - 7'd4 : - (sfd__h2613[58] ? - 7'd5 : - (sfd__h2613[57] ? - 7'd6 : - (sfd__h2613[56] ? - 7'd7 : - (sfd__h2613[55] ? - 7'd8 : - (sfd__h2613[54] ? - 7'd9 : - (sfd__h2613[53] ? - 7'd10 : - (sfd__h2613[52] ? - 7'd11 : - (sfd__h2613[51] ? - 7'd12 : - (sfd__h2613[50] ? - 7'd13 : - (sfd__h2613[49] ? - 7'd14 : - (sfd__h2613[48] ? - 7'd15 : - (sfd__h2613[47] ? - 7'd16 : - (sfd__h2613[46] ? - 7'd17 : - (sfd__h2613[45] ? - 7'd18 : - (sfd__h2613[44] ? - 7'd19 : - (sfd__h2613[43] ? - 7'd20 : - (sfd__h2613[42] ? - 7'd21 : - (sfd__h2613[41] ? - 7'd22 : - (sfd__h2613[40] ? - 7'd23 : - (sfd__h2613[39] ? - 7'd24 : - (sfd__h2613[38] ? - 7'd25 : - (sfd__h2613[37] ? - 7'd26 : - (sfd__h2613[36] ? - 7'd27 : - (sfd__h2613[35] ? - 7'd28 : - (sfd__h2613[34] ? - 7'd29 : - (sfd__h2613[33] ? - 7'd30 : - (sfd__h2613[32] ? - 7'd31 : - (sfd__h2613[31] ? - 7'd32 : - (sfd__h2613[30] ? - 7'd33 : - (sfd__h2613[29] ? - 7'd34 : - (sfd__h2613[28] ? - 7'd35 : - (sfd__h2613[27] ? - 7'd36 : - (sfd__h2613[26] ? - 7'd37 : - (sfd__h2613[25] ? - 7'd38 : - (sfd__h2613[24] ? - 7'd39 : - (sfd__h2613[23] ? - 7'd40 : - (sfd__h2613[22] ? - 7'd41 : - (sfd__h2613[21] ? - 7'd42 : - (sfd__h2613[20] ? - 7'd43 : - (sfd__h2613[19] ? - 7'd44 : - (sfd__h2613[18] ? - 7'd45 : - (sfd__h2613[17] ? - 7'd46 : - (sfd__h2613[16] ? - 7'd47 : - (sfd__h2613[15] ? - 7'd48 : - (sfd__h2613[14] ? - 7'd49 : - (sfd__h2613[13] ? - 7'd50 : - (sfd__h2613[12] ? - 7'd51 : - (sfd__h2613[11] ? - 7'd52 : - (sfd__h2613[10] ? - 7'd53 : - (sfd__h2613[9] ? - 7'd54 : - (sfd__h2613[8] ? - 7'd55 : - (sfd__h2613[7] ? - 7'd56 : - (sfd__h2613[6] ? - 7'd57 : - (sfd__h2613[5] ? - 7'd58 : - (sfd__h2613[4] ? - 7'd59 : - (sfd__h2613[3] ? - 7'd60 : - (sfd__h2613[2] ? - 7'd61 : - (sfd__h2613[1] ? - 7'd62 : - (sfd__h2613[0] ? - 7'd63 : - 7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1760 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1733 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1754 ? - ((x__h37862[88:25] == 64'h7FFFFFFFFFFFFFFF) ? - x__h37862[88:25] : - x__h37862[88:25] + 64'd1) : - x__h37862[88:25]) : - 64'd0 ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1762 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048513) ? - ((_theResult_____2__h36897[64:63] == 2'b11) ? - _theResult_____2__h36897[63:0] : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1693) : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731[19] ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1693 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1760) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1785 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048513) ? - _theResult_____2__h36897[64:63] == 2'b11 && - guard__h36895 != 2'd0 : - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1733 || - guard__h37673 != 2'd0) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1820 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1795 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1814 ? - ((x__h39123[88:25] == 64'hFFFFFFFFFFFFFFFF) ? - x__h39123[88:25] : - x__h39123[88:25] + 64'd1) : - x__h39123[88:25]) : - 64'd0 ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1907 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1880 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1901 ? - ((x__h40311[56:25] == 32'h7FFFFFFF) ? - x__h40311[56:25] : - x__h40311[56:25] + 32'd1) : - x__h40311[56:25]) : - 32'd0 ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1909 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048545) ? - ((_theResult_____2__h39570[32:31] == 2'b11) ? - _theResult_____2__h39570[31:0] : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1848) : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878[19] ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1848 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1907) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1927 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048545) ? - _theResult_____2__h39570[32:31] == 2'b11 && - guard__h39568 != 2'd0 : - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1880 || - guard__h40122 != 2'd0) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1962 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1937 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1956 ? - ((x__h41334[56:25] == 32'hFFFFFFFF) ? - x__h41334[56:25] : - x__h41334[56:25] + 32'd1) : - x__h41334[56:25]) : - 32'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2684 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2657 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2678 ? - ((x__h72215[85:54] == 32'h7FFFFFFF) ? - x__h72215[85:54] : - x__h72215[85:54] + 32'd1) : - x__h72215[85:54]) : - 32'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2686 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777185) ? - ((_theResult_____2__h71474[32:31] == 2'b11) ? - _theResult_____2__h71474[31:0] : - IF_requestR_3_BIT_191_47_THEN_2147483648_ELSE__ETC___d2617) : - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655[23] ? - IF_requestR_3_BIT_191_47_THEN_2147483648_ELSE__ETC___d2617 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2684) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2710 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777185) ? - _theResult_____2__h71474[32:31] == 2'b11 && - guard__h71472 != 2'd0 : - !NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2657 || - guard__h72026 != 2'd0) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2745 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2720 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2739 ? - ((x__h73238[85:54] == 32'hFFFFFFFF) ? - x__h73238[85:54] : - x__h73238[85:54] + 32'd1) : - x__h73238[85:54]) : - 32'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3169 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3142 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3163 ? - ((x__h97073[117:54] == 64'h7FFFFFFFFFFFFFFF) ? - x__h97073[117:54] : - x__h97073[117:54] + 64'd1) : - x__h97073[117:54]) : - 64'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3171 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777153) ? - ((_theResult_____2__h96108[64:63] == 2'b11) ? - _theResult_____2__h96108[63:0] : - IF_requestR_3_BIT_191_47_THEN_9223372036854775_ETC___d3110) : - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140[23] ? - IF_requestR_3_BIT_191_47_THEN_9223372036854775_ETC___d3110 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3169) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3188 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777153) ? - _theResult_____2__h96108[64:63] == 2'b11 && - guard__h96106 != 2'd0 : - !NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3142 || - guard__h96884 != 2'd0) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3223 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3198 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3217 ? - ((x__h98317[117:54] == 64'hFFFFFFFFFFFFFFFF) ? - x__h98317[117:54] : - x__h98317[117:54] + 64'd1) : - x__h98317[117:54]) : - 64'd0 ; - assign IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d2301 = - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247) ? - requestR[159] : - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2300 ; - assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d5053 = - (!_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 || - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 || - _theResult___fst_exp__h168111 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard60150_0b0_requestR_BITS_191_TO_160_E_ETC__q162 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q163) ; - assign IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2046 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2045 ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 ; - assign IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2060 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2045 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2041 = - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2030 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2032 : - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2035 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 && - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2037 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d4891 = - ((SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q153[10], - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q153 }) - - 12'd3074 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5071 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 ? - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d5061 : - IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d5069) : - requestR[191:160] == 32'hFFFFFFFF && requestR[159] ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5130 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104[2] : - _theResult___fst_exp__h187296 == 11'd2047 && - _theResult___fst_sfd__h187297 == 52'd0 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5142 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104[1] : - _theResult___fst_exp__h186515 == 11'd0 && - guard__h178525 != 2'b0 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5154 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104[0] : - _theResult___fst_exp__h186515 != 11'd2047 && - guard__h178525 != 2'b0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4058 = - ((SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q121[7], - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q121 }) - - 9'd386 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4262 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - ((_theResult___fst_exp__h136404 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard28178_0b0_requestR_BIT_191_0b1_reque_ETC__q144 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q145)) : - ((_theResult___fst_exp__h145119 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard37042_0b0_requestR_BIT_191_0b1_reque_ETC__q146 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q147)) ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4340 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311[2] : - _theResult___fst_exp__h145697 == 8'd255 && - _theResult___fst_sfd__h145698 == 23'd0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4353 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311[1] : - _theResult___fst_exp__h145119 == 8'd0 && - guard__h137042 != 2'b0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4366 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311[0] : - _theResult___fst_exp__h145119 != 8'd255 && - guard__h137042 != 2'b0 ; - assign IF_requestR_3_BITS_126_TO_116_167_EQ_2047_168__ETC___d5215 = - (requestR[126:116] == 11'd2047 && requestR[115] || - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5184) ? - requestR[191:128] : - (requestR_3_BITS_126_TO_116_167_EQ_0_181_AND_re_ETC___d5188 ? - requestR[127:64] : - res__h192322) ; - assign IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d2021 = - sV2_exp__h1315 == 8'd0 && sV2_sfd__h1316 == 23'd0 && - requestR[127:96] == 32'hFFFFFFFF && - requestR[95] && - sV1_exp__h1212 == 8'd0 && - sV1_sfd__h1213 == 23'd0 && - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ; - assign IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1391 = - (requestR[159:128] == 32'd0 || - !sfd__h24253[31] && !sfd__h24253[30] && !sfd__h24253[29] && - !sfd__h24253[28] && - !sfd__h24253[27] && - !sfd__h24253[26] && - !sfd__h24253[25] && - !sfd__h24253[24] && - !sfd__h24253[23] && - !sfd__h24253[22] && - !sfd__h24253[21] && - !sfd__h24253[20] && - !sfd__h24253[19] && - !sfd__h24253[18] && - !sfd__h24253[17] && - !sfd__h24253[16] && - !sfd__h24253[15] && - !sfd__h24253[14] && - !sfd__h24253[13] && - !sfd__h24253[12] && - !sfd__h24253[11] && - !sfd__h24253[10] && - !sfd__h24253[9] && - !sfd__h24253[8] && - !sfd__h24253[7] && - !sfd__h24253[6] && - !sfd__h24253[5] && - !sfd__h24253[4] && - !sfd__h24253[3] && - !sfd__h24253[2] && - !sfd__h24253[1] && - !sfd__h24253[0]) ? - 8'd0 : - _theResult___snd_fst_exp__h30242 ; - assign IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1613 = - (requestR[159:128] == 32'd0 || - !requestR[159] && - NOT_requestR_3_BIT_158_31_32_AND_NOT_requestR__ETC___d822) ? - 8'd0 : - _theResult___snd_fst_exp__h36356 ; - assign IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2398 = - (requestR[159:128] == 32'd0 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247) ? - 52'd0 : - _theResult___snd_fst_sfd__h61290 ; - assign IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2580 = - (requestR[159:128] == 32'd0 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 || - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460) ? - 52'd0 : - _theResult___snd_fst_sfd__h70929 ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d2747 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 32'd0 : - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718[23] ? - 32'hFFFFFFFF : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2745) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d3225 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 64'd0 : - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196[23] ? - 64'hFFFFFFFFFFFFFFFF : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3223) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5228 = - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5184 ? - requestR[127:64] : - (requestR_3_BITS_126_TO_116_167_EQ_0_181_AND_re_ETC___d5188 ? - requestR[191:128] : - res__h196815) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5294 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - res___1__h204675 : - ((requestR[190:180] == 11'd0) ? - res___1__h204694 : - res__h204710) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 = - ((requestR[190:180] == 11'd0) ? - (requestR[179] ? - 6'd2 : - (requestR[178] ? - 6'd3 : - (requestR[177] ? - 6'd4 : - (requestR[176] ? - 6'd5 : - (requestR[175] ? - 6'd6 : - (requestR[174] ? - 6'd7 : - (requestR[173] ? - 6'd8 : - (requestR[172] ? - 6'd9 : - (requestR[171] ? - 6'd10 : - (requestR[170] ? - 6'd11 : - (requestR[169] ? - 6'd12 : - (requestR[168] ? - 6'd13 : - (requestR[167] ? - 6'd14 : - (requestR[166] ? - 6'd15 : - (requestR[165] ? - 6'd16 : - (requestR[164] ? - 6'd17 : - (requestR[163] ? - 6'd18 : - (requestR[162] ? - 6'd19 : - (requestR[161] ? - 6'd20 : - (requestR[160] ? - 6'd21 : - (requestR[159] ? - 6'd22 : - (requestR[158] ? - 6'd23 : - (requestR[157] ? - 6'd24 : - (requestR[156] ? - 6'd25 : - (requestR[155] ? - 6'd26 : - (requestR[154] ? - 6'd27 : - (requestR[153] ? - 6'd28 : - (requestR[152] ? - 6'd29 : - (requestR[151] ? - 6'd30 : - (requestR[150] ? - 6'd31 : - (requestR[149] ? - 6'd32 : - (requestR[148] ? - 6'd33 : - (requestR[147] ? - 6'd34 : - (requestR[146] ? - 6'd35 : - (requestR[145] ? - 6'd36 : - (requestR[144] ? - 6'd37 : - (requestR[143] ? - 6'd38 : - (requestR[142] ? - 6'd39 : - (requestR[141] ? - 6'd40 : - (requestR[140] ? - 6'd41 : - (requestR[139] ? - 6'd42 : - (requestR[138] ? - 6'd43 : - (requestR[137] ? - 6'd44 : - (requestR[136] ? - 6'd45 : - (requestR[135] ? - 6'd46 : - (requestR[134] ? - 6'd47 : - (requestR[133] ? - 6'd48 : - (requestR[132] ? - 6'd49 : - (requestR[131] ? - 6'd50 : - (requestR[130] ? - 6'd51 : - (requestR[129] ? - 6'd52 : - (requestR[128] ? - 6'd53 : - 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4264 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 ? - IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_9_ETC___d4244 : - requestR[191]) : - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 ? - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4262 : - requestR[191]) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4315 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4297 : - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 && - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311[4] ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4326 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4322 : - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 && - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311[3] ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4342 = - (requestR[190:180] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4334 : - !SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 || - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4340 ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4355 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4349 : - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 && - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4353 ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4368 = - (requestR[190:180] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4362 : - !SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 || - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4366 ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d2688 = - (requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0) ? - IF_requestR_3_BIT_191_47_THEN_2147483648_ELSE__ETC___d2617 : - ((requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 32'd0 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2686) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d3173 = - (requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0) ? - IF_requestR_3_BIT_191_47_THEN_9223372036854775_ETC___d3110 : - ((requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 64'd0 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3171) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d4224 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - _theResult___snd_fst_sfd__h102768 : - _theResult___fst_sfd__h145713 ; - assign IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d2890 = - (requestR[191:128] == 64'd0 || - !sfd__h2613[63] && !sfd__h2613[62] && !sfd__h2613[61] && - !sfd__h2613[60] && - !sfd__h2613[59] && - !sfd__h2613[58] && - !sfd__h2613[57] && - !sfd__h2613[56] && - !sfd__h2613[55] && - !sfd__h2613[54] && - !sfd__h2613[53] && - !sfd__h2613[52] && - !sfd__h2613[51] && - !sfd__h2613[50] && - !sfd__h2613[49] && - !sfd__h2613[48] && - !sfd__h2613[47] && - !sfd__h2613[46] && - !sfd__h2613[45] && - !sfd__h2613[44] && - !sfd__h2613[43] && - !sfd__h2613[42] && - !sfd__h2613[41] && - !sfd__h2613[40] && - !sfd__h2613[39] && - !sfd__h2613[38] && - !sfd__h2613[37] && - !sfd__h2613[36] && - !sfd__h2613[35] && - !sfd__h2613[34] && - !sfd__h2613[33] && - !sfd__h2613[32] && - !sfd__h2613[31] && - !sfd__h2613[30] && - !sfd__h2613[29] && - !sfd__h2613[28] && - !sfd__h2613[27] && - !sfd__h2613[26] && - !sfd__h2613[25] && - !sfd__h2613[24] && - !sfd__h2613[23] && - !sfd__h2613[22] && - !sfd__h2613[21] && - !sfd__h2613[20] && - !sfd__h2613[19] && - !sfd__h2613[18] && - !sfd__h2613[17] && - !sfd__h2613[16] && - !sfd__h2613[15] && - !sfd__h2613[14] && - !sfd__h2613[13] && - !sfd__h2613[12] && - !sfd__h2613[11] && - !sfd__h2613[10] && - !sfd__h2613[9] && - !sfd__h2613[8] && - !sfd__h2613[7] && - !sfd__h2613[6] && - !sfd__h2613[5] && - !sfd__h2613[4] && - !sfd__h2613[3] && - !sfd__h2613[2] && - !sfd__h2613[1] && - !sfd__h2613[0]) ? - 11'd0 : - _theResult___snd_fst_exp__h84616 ; - assign IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d534 = - (requestR[191:128] == 64'd0 || - !sfd__h2613[63] && !sfd__h2613[62] && !sfd__h2613[61] && - !sfd__h2613[60] && - !sfd__h2613[59] && - !sfd__h2613[58] && - !sfd__h2613[57] && - !sfd__h2613[56] && - !sfd__h2613[55] && - !sfd__h2613[54] && - !sfd__h2613[53] && - !sfd__h2613[52] && - !sfd__h2613[51] && - !sfd__h2613[50] && - !sfd__h2613[49] && - !sfd__h2613[48] && - !sfd__h2613[47] && - !sfd__h2613[46] && - !sfd__h2613[45] && - !sfd__h2613[44] && - !sfd__h2613[43] && - !sfd__h2613[42] && - !sfd__h2613[41] && - !sfd__h2613[40] && - !sfd__h2613[39] && - !sfd__h2613[38] && - !sfd__h2613[37] && - !sfd__h2613[36] && - !sfd__h2613[35] && - !sfd__h2613[34] && - !sfd__h2613[33] && - !sfd__h2613[32] && - !sfd__h2613[31] && - !sfd__h2613[30] && - !sfd__h2613[29] && - !sfd__h2613[28] && - !sfd__h2613[27] && - !sfd__h2613[26] && - !sfd__h2613[25] && - !sfd__h2613[24] && - !sfd__h2613[23] && - !sfd__h2613[22] && - !sfd__h2613[21] && - !sfd__h2613[20] && - !sfd__h2613[19] && - !sfd__h2613[18] && - !sfd__h2613[17] && - !sfd__h2613[16] && - !sfd__h2613[15] && - !sfd__h2613[14] && - !sfd__h2613[13] && - !sfd__h2613[12] && - !sfd__h2613[11] && - !sfd__h2613[10] && - !sfd__h2613[9] && - !sfd__h2613[8] && - !sfd__h2613[7] && - !sfd__h2613[6] && - !sfd__h2613[5] && - !sfd__h2613[4] && - !sfd__h2613[3] && - !sfd__h2613[2] && - !sfd__h2613[1] && - !sfd__h2613[0]) ? - 8'd0 : - _theResult___snd_fst_exp__h13306 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692 = - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) && - sV1_exp__h1212 == 8'd255 && - sV1_sfd__h1213 == 23'd0 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1693 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'h8000000000000000 : - 64'h7FFFFFFFFFFFFFFF ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696 = - sV1_exp__h1212 - 8'd127 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - -b__h36962 : - b__h36962 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1824 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd0 : - ((sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0) ? - 64'hFFFFFFFFFFFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1822) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1831 = - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0 || - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1795 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1814 && - x__h39123[88:25] == 64'hFFFFFFFFFFFFFFFF) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1842 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1831, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1836 } == - 5'd0 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1831 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1848 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 32'h80000000 : - 32'h7FFFFFFF ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - -b__h39635 : - b__h39635 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1966 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 32'd0 : - ((sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0) ? - 32'hFFFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1964) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1974 = - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0 || - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1937 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1956 && - x__h41334[56:25] == 32'hFFFFFFFF) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1985 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1974, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1979 } == - 5'd0 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1974 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2007 = - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22] && - sV2_exp__h1315 == 8'd255 && - sV2_sfd__h1316 != 23'd0 && - !sV2_sfd__h1316[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2017 = - sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159] && - sV2_exp__h1315 == 8'd0 && - sV2_sfd__h1316 == 23'd0 && - (requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2030 = - sV1_exp__h1212 < sV2_exp__h1315 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 = - sV1_exp__h1212 == sV2_exp__h1315 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2032 = - sV1_sfd__h1213 < sV2_sfd__h1316 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2035 = - sV1_exp__h1212 <= sV2_exp__h1315 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2037 = - sV1_sfd__h1213 <= sV2_sfd__h1316 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2055 = - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22] || - sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316 != 23'd0 && - !sV2_sfd__h1316[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2088 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2055 || - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22] || - sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2099 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2035 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2037) && - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2030 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 || - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2032) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2103 = - sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0 && - sV2_exp__h1315 == 8'd0 && - sV2_sfd__h1316 == 23'd0 || - NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d2102 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[158:128] : - 31'h7FC00000 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1722 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h36895 == 2'b10) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[24] : - guard__h36895 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h36895 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[88] && - guard__h36895 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1754 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h37673 == 2'b10) ? - x__h37862[25] : - guard__h37673 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h37673 != 2'd0 : - requestR[194:192] == 3'h1 && x__h37862[88] && - guard__h37673 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1814 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h38902 == 2'b10) ? - x__h39123[25] : - guard__h38902 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h38902 != 2'd0 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1869 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h39568 == 2'b10) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[24] : - guard__h39568 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h39568 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[56] && - guard__h39568 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1901 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h40122 == 2'b10) ? - x__h40311[25] : - guard__h40122 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h40122 != 2'd0 : - requestR[194:192] == 3'h1 && x__h40311[56] && - guard__h40122 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1956 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h41113 == 2'b10) ? - x__h41334[25] : - guard__h41113 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h41113 != 2'd0 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2646 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h71472 == 2'b10) ? - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[53] : - guard__h71472 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h71472 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[85] && - guard__h71472 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2678 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h72026 == 2'b10) ? - x__h72215[54] : - guard__h72026 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h72026 != 2'd0 : - requestR[194:192] == 3'h1 && x__h72215[85] && - guard__h72026 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2739 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h73017 == 2'b10) ? - x__h73238[54] : - guard__h73017 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h73017 != 2'd0 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3131 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h96106 == 2'b10) ? - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[53] : - guard__h96106 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h96106 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[117] && - guard__h96106 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3163 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h96884 == 2'b10) ? - x__h97073[54] : - guard__h96884 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h96884 != 2'd0 : - requestR[194:192] == 3'h1 && x__h97073[117] && - guard__h96884 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3217 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h98096 == 2'b10) ? - x__h98317[54] : - guard__h98096 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h98096 != 2'd0 ; - assign IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1524 = - requestR[159] ? - 6'd0 : - (requestR[158] ? - 6'd1 : - (requestR[157] ? - 6'd2 : - (requestR[156] ? - 6'd3 : - (requestR[155] ? - 6'd4 : - (requestR[154] ? - 6'd5 : - (requestR[153] ? - 6'd6 : - (requestR[152] ? - 6'd7 : - (requestR[151] ? - 6'd8 : - (requestR[150] ? - 6'd9 : - (requestR[149] ? - 6'd10 : - (requestR[148] ? - 6'd11 : - (requestR[147] ? - 6'd12 : - (requestR[146] ? - 6'd13 : - (requestR[145] ? - 6'd14 : - (requestR[144] ? - 6'd15 : - (requestR[143] ? - 6'd16 : - (requestR[142] ? - 6'd17 : - (requestR[141] ? - 6'd18 : - (requestR[140] ? - 6'd19 : - (requestR[139] ? - 6'd20 : - (requestR[138] ? - 6'd21 : - (requestR[137] ? - 6'd22 : - (requestR[136] ? - 6'd23 : - (requestR[135] ? - 6'd24 : - (requestR[134] ? - 6'd25 : - (requestR[133] ? - 6'd26 : - (requestR[132] ? - 6'd27 : - (requestR[131] ? - 6'd28 : - (requestR[130] ? - 6'd29 : - (requestR[129] ? - 6'd30 : - (requestR[128] ? - 6'd31 : - 6'd32))))))))))))))))))))))))))))))) ; - assign IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d2455 = - requestR[159] ? - 6'd0 : - (requestR[158] ? - 6'd1 : - (requestR[157] ? - 6'd2 : - (requestR[156] ? - 6'd3 : - (requestR[155] ? - 6'd4 : - (requestR[154] ? - 6'd5 : - (requestR[153] ? - 6'd6 : - (requestR[152] ? - 6'd7 : - (requestR[151] ? - 6'd8 : - (requestR[150] ? - 6'd9 : - (requestR[149] ? - 6'd10 : - (requestR[148] ? - 6'd11 : - (requestR[147] ? - 6'd12 : - (requestR[146] ? - 6'd13 : - (requestR[145] ? - 6'd14 : - (requestR[144] ? - 6'd15 : - (requestR[143] ? - 6'd16 : - (requestR[142] ? - 6'd17 : - (requestR[141] ? - 6'd18 : - (requestR[140] ? - 6'd19 : - (requestR[139] ? - 6'd20 : - (requestR[138] ? - 6'd21 : - (requestR[137] ? - 6'd22 : - (requestR[136] ? - 6'd23 : - (requestR[135] ? - 6'd24 : - (requestR[134] ? - 6'd25 : - (requestR[133] ? - 6'd26 : - (requestR[132] ? - 6'd27 : - (requestR[131] ? - 6'd28 : - (requestR[130] ? - 6'd29 : - (requestR[129] ? - 6'd30 : - (requestR[128] ? - 6'd31 : - 6'd55))))))))))))))))))))))))))))))) ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1472 = - (sfd__h24253[31] || sfd__h24253[30] || sfd__h24253[29] || - sfd__h24253[28] || - sfd__h24253[27] || - sfd__h24253[26] || - sfd__h24253[25] || - sfd__h24253[24] || - sfd__h24253[23] || - sfd__h24253[22] || - sfd__h24253[21] || - sfd__h24253[20] || - sfd__h24253[19] || - sfd__h24253[18] || - sfd__h24253[17] || - sfd__h24253[16] || - sfd__h24253[15] || - sfd__h24253[14] || - sfd__h24253[13] || - sfd__h24253[12] || - sfd__h24253[11] || - sfd__h24253[10] || - sfd__h24253[9] || - sfd__h24253[8] || - sfd__h24253[7] || - sfd__h24253[6] || - sfd__h24253[5] || - sfd__h24253[4] || - sfd__h24253[3] || - sfd__h24253[2] || - sfd__h24253[1] || - sfd__h24253[0]) && - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 && - _theResult___fst_exp__h30233 == 8'd255 && - _theResult___fst_sfd__h30234 == 23'd0) ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1475 = - (sfd__h24253[31] || sfd__h24253[30] || sfd__h24253[29] || - sfd__h24253[28] || - sfd__h24253[27] || - sfd__h24253[26] || - sfd__h24253[25] || - sfd__h24253[24] || - sfd__h24253[23] || - sfd__h24253[22] || - sfd__h24253[21] || - sfd__h24253[20] || - sfd__h24253[19] || - sfd__h24253[18] || - sfd__h24253[17] || - sfd__h24253[16] || - sfd__h24253[15] || - sfd__h24253[14] || - sfd__h24253[13] || - sfd__h24253[12] || - sfd__h24253[11] || - sfd__h24253[10] || - sfd__h24253[9] || - sfd__h24253[8] || - sfd__h24253[7] || - sfd__h24253[6] || - sfd__h24253[5] || - sfd__h24253[4] || - sfd__h24253[3] || - sfd__h24253[2] || - sfd__h24253[1] || - sfd__h24253[0]) && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1484 = - (sfd__h24253[31] || sfd__h24253[30] || sfd__h24253[29] || - sfd__h24253[28] || - sfd__h24253[27] || - sfd__h24253[26] || - sfd__h24253[25] || - sfd__h24253[24] || - sfd__h24253[23] || - sfd__h24253[22] || - sfd__h24253[21] || - sfd__h24253[20] || - sfd__h24253[19] || - sfd__h24253[18] || - sfd__h24253[17] || - sfd__h24253[16] || - sfd__h24253[15] || - sfd__h24253[14] || - sfd__h24253[13] || - sfd__h24253[12] || - sfd__h24253[11] || - sfd__h24253[10] || - sfd__h24253[9] || - sfd__h24253[8] || - sfd__h24253[7] || - sfd__h24253[6] || - sfd__h24253[5] || - sfd__h24253[4] || - sfd__h24253[3] || - sfd__h24253[2] || - sfd__h24253[1] || - sfd__h24253[0]) && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 && - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1481 ; - assign IF_requestR_3_BIT_191_47_THEN_0_ELSE_IF_reques_ETC___d920 = - requestR[191] ? - 7'd0 : - (requestR[190] ? - 7'd1 : - (requestR[189] ? - 7'd2 : - (requestR[188] ? - 7'd3 : - (requestR[187] ? - 7'd4 : - (requestR[186] ? - 7'd5 : - (requestR[185] ? - 7'd6 : - (requestR[184] ? - 7'd7 : - (requestR[183] ? - 7'd8 : - (requestR[182] ? - 7'd9 : - (requestR[181] ? - 7'd10 : - (requestR[180] ? - 7'd11 : - (requestR[179] ? - 7'd12 : - (requestR[178] ? - 7'd13 : - (requestR[177] ? - 7'd14 : - (requestR[176] ? - 7'd15 : - (requestR[175] ? - 7'd16 : - (requestR[174] ? - 7'd17 : - (requestR[173] ? - 7'd18 : - (requestR[172] ? - 7'd19 : - (requestR[171] ? - 7'd20 : - (requestR[170] ? - 7'd21 : - (requestR[169] ? - 7'd22 : - (requestR[168] ? - 7'd23 : - (requestR[167] ? - 7'd24 : - (requestR[166] ? - 7'd25 : - (requestR[165] ? - 7'd26 : - (requestR[164] ? - 7'd27 : - (requestR[163] ? - 7'd28 : - (requestR[162] ? - 7'd29 : - (requestR[161] ? - 7'd30 : - (requestR[160] ? - 7'd31 : - (requestR[159] ? - 7'd32 : - (requestR[158] ? - 7'd33 : - (requestR[157] ? - 7'd34 : - (requestR[156] ? - 7'd35 : - (requestR[155] ? - 7'd36 : - (requestR[154] ? - 7'd37 : - (requestR[153] ? - 7'd38 : - (requestR[152] ? - 7'd39 : - (requestR[151] ? - 7'd40 : - (requestR[150] ? - 7'd41 : - (requestR[149] ? - 7'd42 : - (requestR[148] ? - 7'd43 : - (requestR[147] ? - 7'd44 : - (requestR[146] ? - 7'd45 : - (requestR[145] ? - 7'd46 : - (requestR[144] ? - 7'd47 : - (requestR[143] ? - 7'd48 : - (requestR[142] ? - 7'd49 : - (requestR[141] ? - 7'd50 : - (requestR[140] ? - 7'd51 : - (requestR[139] ? - 7'd52 : - (requestR[138] ? - 7'd53 : - (requestR[137] ? - 7'd54 : - (requestR[136] ? - 7'd55 : - (requestR[135] ? - 7'd56 : - (requestR[134] ? - 7'd57 : - (requestR[133] ? - 7'd58 : - (requestR[132] ? - 7'd59 : - (requestR[131] ? - 7'd60 : - (requestR[130] ? - 7'd61 : - (requestR[129] ? - 7'd62 : - (requestR[128] ? - 7'd63 : - 7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ; - assign IF_requestR_3_BIT_191_47_THEN_2147483648_ELSE__ETC___d2617 = - requestR[191] ? 32'h80000000 : 32'h7FFFFFFF ; - assign IF_requestR_3_BIT_191_47_THEN_9223372036854775_ETC___d3110 = - requestR[191] ? 64'h8000000000000000 : 64'h7FFFFFFFFFFFFFFF ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629 = - requestR[191] ? -b__h71539 : b__h71539 ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114 = - requestR[191] ? -b__h96173 : b__h96173 ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2939 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - (!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 || - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 && - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 && - _theResult___fst_exp__h84607 == 11'd2047 && - _theResult___fst_sfd__h84608 == 52'd0) ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2942 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2951 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 && - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 && - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2948 ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d647 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - (!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 || - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 && - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 && - _theResult___fst_exp__h13297 == 8'd255 && - _theResult___fst_sfd__h13298 == 23'd0) ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d650 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d659 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 && - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 && - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d656 ; - assign IF_requestR_3_BIT_191_47_THEN_NOT_requestR_3_B_ETC___d5208 = - requestR[191] ? - !requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5197 || - requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 && - !requestR_3_BITS_179_TO_128_610_ULE_requestR_3__ETC___d5200 : - requestR_3_BITS_190_TO_180_608_ULT_requestR_3__ETC___d5204 || - requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 && - requestR_3_BITS_179_TO_128_610_ULT_requestR_3__ETC___d5205 ; - assign IF_sfd___32218_BIT_10_THEN_2_ELSE_0__q9 = - sfd___3__h12218[10] ? 2'd2 : 2'd0 ; - assign IF_sfd___32218_BIT_11_THEN_2_ELSE_0__q8 = - sfd___3__h12218[11] ? 2'd2 : 2'd0 ; - assign IF_sfd___32218_BIT_39_THEN_2_ELSE_0__q7 = - sfd___3__h12218[39] ? 2'd2 : 2'd0 ; - assign IF_sfd___32218_BIT_40_THEN_2_ELSE_0__q6 = - sfd___3__h12218[40] ? 2'd2 : 2'd0 ; - assign IF_sfd___32785_BIT_10_THEN_2_ELSE_0__q25 = - sfd___3__h22785[10] ? 2'd2 : 2'd0 ; - assign IF_sfd___32785_BIT_11_THEN_2_ELSE_0__q24 = - sfd___3__h22785[11] ? 2'd2 : 2'd0 ; - assign IF_sfd___32785_BIT_39_THEN_2_ELSE_0__q23 = - sfd___3__h22785[39] ? 2'd2 : 2'd0 ; - assign IF_sfd___32785_BIT_40_THEN_2_ELSE_0__q22 = - sfd___3__h22785[40] ? 2'd2 : 2'd0 ; - assign IF_sfd___35273_BIT_7_THEN_2_ELSE_0__q53 = - sfd___3__h35273[7] ? 2'd2 : 2'd0 ; - assign IF_sfd___35273_BIT_8_THEN_2_ELSE_0__q52 = - sfd___3__h35273[8] ? 2'd2 : 2'd0 ; - assign IF_sfd___39157_BIT_7_THEN_2_ELSE_0__q39 = - sfd___3__h29157[7] ? 2'd2 : 2'd0 ; - assign IF_sfd___39157_BIT_8_THEN_2_ELSE_0__q38 = - sfd___3__h29157[8] ? 2'd2 : 2'd0 ; - assign IF_sfd___39445_BIT_1_THEN_2_ELSE_0__q82 = - sfd___3__h69445[1] ? 2'd2 : 2'd0 ; - assign IF_sfd___39445_BIT_2_THEN_2_ELSE_0__q81 = - sfd___3__h69445[2] ? 2'd2 : 2'd0 ; - assign IF_sfd___39804_BIT_1_THEN_2_ELSE_0__q68 = - sfd___3__h59804[1] ? 2'd2 : 2'd0 ; - assign IF_sfd___39804_BIT_2_THEN_2_ELSE_0__q67 = - sfd___3__h59804[2] ? 2'd2 : 2'd0 ; - assign IF_sfdin18545_BIT_33_THEN_2_ELSE_0__q115 = - sfdin__h118545[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin36398_BIT_33_THEN_2_ELSE_0__q120 = - sfdin__h136398[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin77678_BIT_4_THEN_2_ELSE_0__q152 = - sfdin__h177678[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd27188_BIT_33_THEN_2_ELSE_0__q117 = - _theResult___snd__h127188[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd45065_BIT_33_THEN_2_ELSE_0__q123 = - _theResult___snd__h145065[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd68062_BIT_4_THEN_2_ELSE_0__q149 = - _theResult___snd__h168062[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd86461_BIT_4_THEN_2_ELSE_0__q155 = - _theResult___snd__h186461[4] ? 2'd2 : 2'd0 ; - assign IF_x0311_BIT_24_THEN_2_ELSE_0__q65 = x__h40311[24] ? 2'd2 : 2'd0 ; - assign IF_x1334_BIT_24_THEN_2_ELSE_0__q66 = x__h41334[24] ? 2'd2 : 2'd0 ; - assign IF_x2215_BIT_53_THEN_2_ELSE_0__q92 = x__h72215[53] ? 2'd2 : 2'd0 ; - assign IF_x3238_BIT_53_THEN_2_ELSE_0__q93 = x__h73238[53] ? 2'd2 : 2'd0 ; - assign IF_x7073_BIT_53_THEN_2_ELSE_0__q112 = x__h97073[53] ? 2'd2 : 2'd0 ; - assign IF_x7862_BIT_24_THEN_2_ELSE_0__q63 = x__h37862[24] ? 2'd2 : 2'd0 ; - assign IF_x8317_BIT_53_THEN_2_ELSE_0__q113 = x__h98317[53] ? 2'd2 : 2'd0 ; - assign IF_x9123_BIT_24_THEN_2_ELSE_0__q64 = x__h39123[24] ? 2'd2 : 2'd0 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 = - -{ {12{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696[7]}}, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696 } ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1730 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 + - 20'd64 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1730 - - 20'd2 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1733 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731 ^ - 20'h80000) <= - 20'd524352 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1730 - - 20'd1 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1795 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793 ^ - 20'h80000) <= - 20'd524352 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1877 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 + - 20'd32 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1877 - - 20'd2 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1880 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878 ^ - 20'h80000) <= - 20'd524320 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1877 - - 20'd1 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1937 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935 ^ - 20'h80000) <= - 20'd524320 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 = - -{ {13{requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620[10]}}, - requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620 } ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2654 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 + - 24'd32 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2654 - - 24'd2 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2657 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655 ^ - 24'h800000) <= - 24'd8388640 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2654 - - 24'd1 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2720 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718 ^ - 24'h800000) <= - 24'd8388640 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3139 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 + - 24'd64 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3139 - - 24'd2 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3142 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140 ^ - 24'h800000) <= - 24'd8388672 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3139 - - 24'd1 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3198 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196 ^ - 24'h800000) <= - 24'd8388672 ; - assign NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4334 = - !_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 || - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282[2] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4362 = - !_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 || - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282[0] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294[0]) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1774 = - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - ((NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048513) ? - _theResult_____2__h36897[64:63] != 2'b11 : - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1733 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1754 && - x__h37862[88:25] == 64'h7FFFFFFFFFFFFFFF) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1836 = - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1795 || - guard__h38902 != 2'd0) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1919 = - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - ((NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048545) ? - _theResult_____2__h39570[32:31] != 2'b11 : - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1880 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1901 && - x__h40311[56:25] == 32'h7FFFFFFF) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1979 = - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1937 || - guard__h41113 != 2'd0) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2044 = - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0 || - sV2_exp__h1315 != 8'd0 || - sV2_sfd__h1316 != 23'd0) && - requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d2043 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2045 = - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV2_exp__h1315 != 8'd255 || sV2_sfd__h1316 == 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2044 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2098 = - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2030 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 || - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2032) && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2035 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2037) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2104 = - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV2_exp__h1315 != 8'd255 || sV2_sfd__h1316 == 23'd0) && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2103 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2120 = - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV2_exp__h1315 != 8'd255 || sV2_sfd__h1316 == 23'd0) && - (requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d2043 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2103) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470 = - !sV1_sfd__h1213[21] && !sV1_sfd__h1213[20] && - !sV1_sfd__h1213[19] && - !sV1_sfd__h1213[18] && - !sV1_sfd__h1213[17] && - !sV1_sfd__h1213[16] && - !sV1_sfd__h1213[15] && - !sV1_sfd__h1213[14] && - !sV1_sfd__h1213[13] && - !sV1_sfd__h1213[12] && - !sV1_sfd__h1213[11] && - !sV1_sfd__h1213[10] && - !sV1_sfd__h1213[9] && - !sV1_sfd__h1213[8] && - !sV1_sfd__h1213[7] && - !sV1_sfd__h1213[6] && - !sV1_sfd__h1213[5] && - !sV1_sfd__h1213[4] && - !sV1_sfd__h1213[3] && - !sV1_sfd__h1213[2] && - !sV1_sfd__h1213[1] && - !sV1_sfd__h1213[0] ; - assign NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d1278 = - !sfd__h24253[31] && !sfd__h24253[30] && !sfd__h24253[29] && - !sfd__h24253[28] && - !sfd__h24253[27] && - !sfd__h24253[26] && - !sfd__h24253[25] && - !sfd__h24253[24] && - !sfd__h24253[23] && - !sfd__h24253[22] && - !sfd__h24253[21] && - !sfd__h24253[20] && - !sfd__h24253[19] && - !sfd__h24253[18] && - !sfd__h24253[17] && - !sfd__h24253[16] && - !sfd__h24253[15] && - !sfd__h24253[14] && - !sfd__h24253[13] && - !sfd__h24253[12] && - !sfd__h24253[11] && - !sfd__h24253[10] && - !sfd__h24253[9] && - !sfd__h24253[8] && - !sfd__h24253[7] && - !sfd__h24253[6] && - !sfd__h24253[5] && - !sfd__h24253[4] && - !sfd__h24253[3] && - !sfd__h24253[2] && - !sfd__h24253[1] && - !sfd__h24253[0] || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 ; - assign NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d2781 = - !sfd__h2613[63] && !sfd__h2613[62] && !sfd__h2613[61] && - !sfd__h2613[60] && - !sfd__h2613[59] && - !sfd__h2613[58] && - !sfd__h2613[57] && - !sfd__h2613[56] && - !sfd__h2613[55] && - !sfd__h2613[54] && - !sfd__h2613[53] && - !sfd__h2613[52] && - !sfd__h2613[51] && - !sfd__h2613[50] && - !sfd__h2613[49] && - !sfd__h2613[48] && - !sfd__h2613[47] && - !sfd__h2613[46] && - !sfd__h2613[45] && - !sfd__h2613[44] && - !sfd__h2613[43] && - !sfd__h2613[42] && - !sfd__h2613[41] && - !sfd__h2613[40] && - !sfd__h2613[39] && - !sfd__h2613[38] && - !sfd__h2613[37] && - !sfd__h2613[36] && - !sfd__h2613[35] && - !sfd__h2613[34] && - !sfd__h2613[33] && - !sfd__h2613[32] && - !sfd__h2613[31] && - !sfd__h2613[30] && - !sfd__h2613[29] && - !sfd__h2613[28] && - !sfd__h2613[27] && - !sfd__h2613[26] && - !sfd__h2613[25] && - !sfd__h2613[24] && - !sfd__h2613[23] && - !sfd__h2613[22] && - !sfd__h2613[21] && - !sfd__h2613[20] && - !sfd__h2613[19] && - !sfd__h2613[18] && - !sfd__h2613[17] && - !sfd__h2613[16] && - !sfd__h2613[15] && - !sfd__h2613[14] && - !sfd__h2613[13] && - !sfd__h2613[12] && - !sfd__h2613[11] && - !sfd__h2613[10] && - !sfd__h2613[9] && - !sfd__h2613[8] && - !sfd__h2613[7] && - !sfd__h2613[6] && - !sfd__h2613[5] && - !sfd__h2613[4] && - !sfd__h2613[3] && - !sfd__h2613[2] && - !sfd__h2613[1] && - !sfd__h2613[0] || - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 || - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 ; - assign NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d412 = - !sfd__h2613[63] && !sfd__h2613[62] && !sfd__h2613[61] && - !sfd__h2613[60] && - !sfd__h2613[59] && - !sfd__h2613[58] && - !sfd__h2613[57] && - !sfd__h2613[56] && - !sfd__h2613[55] && - !sfd__h2613[54] && - !sfd__h2613[53] && - !sfd__h2613[52] && - !sfd__h2613[51] && - !sfd__h2613[50] && - !sfd__h2613[49] && - !sfd__h2613[48] && - !sfd__h2613[47] && - !sfd__h2613[46] && - !sfd__h2613[45] && - !sfd__h2613[44] && - !sfd__h2613[43] && - !sfd__h2613[42] && - !sfd__h2613[41] && - !sfd__h2613[40] && - !sfd__h2613[39] && - !sfd__h2613[38] && - !sfd__h2613[37] && - !sfd__h2613[36] && - !sfd__h2613[35] && - !sfd__h2613[34] && - !sfd__h2613[33] && - !sfd__h2613[32] && - !sfd__h2613[31] && - !sfd__h2613[30] && - !sfd__h2613[29] && - !sfd__h2613[28] && - !sfd__h2613[27] && - !sfd__h2613[26] && - !sfd__h2613[25] && - !sfd__h2613[24] && - !sfd__h2613[23] && - !sfd__h2613[22] && - !sfd__h2613[21] && - !sfd__h2613[20] && - !sfd__h2613[19] && - !sfd__h2613[18] && - !sfd__h2613[17] && - !sfd__h2613[16] && - !sfd__h2613[15] && - !sfd__h2613[14] && - !sfd__h2613[13] && - !sfd__h2613[12] && - !sfd__h2613[11] && - !sfd__h2613[10] && - !sfd__h2613[9] && - !sfd__h2613[8] && - !sfd__h2613[7] && - !sfd__h2613[6] && - !sfd__h2613[5] && - !sfd__h2613[4] && - !sfd__h2613[3] && - !sfd__h2613[2] && - !sfd__h2613[1] && - !sfd__h2613[0] || - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 || - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 ; - assign NOT_requestR_3_BITS_159_TO_128_139_EQ_0_140_14_ETC___d1660 = - requestR[159:128] != 32'd0 && - (requestR[159] || - requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077) && - (!_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530 && - _theResult___fst_exp__h36347 == 8'd255 && - _theResult___fst_sfd__h36348 == 23'd0) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2699 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - ((NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777185) ? - _theResult_____2__h71474[32:31] != 2'b11 : - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2657 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2678 && - x__h72215[85:54] == 32'h7FFFFFFF) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2762 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - !NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2720 || - guard__h73017 != 2'd0) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3180 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - ((NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777153) ? - _theResult_____2__h96108[64:63] != 2'b11 : - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3142 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3163 && - x__h97073[117:54] == 64'h7FFFFFFFFFFFFFFF) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3239 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - !NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3198 || - guard__h98096 != 2'd0) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5212 = - (requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0 || - requestR[126:116] != 11'd0 || - requestR[115:64] != 52'd0) && - (requestR[191] && !requestR[127] || - (requestR[191] || !requestR[127]) && - IF_requestR_3_BIT_191_47_THEN_NOT_requestR_3_B_ETC___d5208) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5273 = - (requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - (requestR[191] && !requestR[127] || - (requestR[191] || !requestR[127]) && - IF_requestR_3_BIT_191_47_THEN_NOT_requestR_3_B_ETC___d5208 || - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5256) ; - assign NOT_requestR_3_BITS_190_TO_180_608_ULT_request_ETC___d5252 = - !requestR_3_BITS_190_TO_180_608_ULT_requestR_3__ETC___d5204 && - (!requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 || - !requestR_3_BITS_179_TO_128_610_ULT_requestR_3__ETC___d5205) && - requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5197 && - (!requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 || - requestR_3_BITS_179_TO_128_610_ULE_requestR_3__ETC___d5200) ; - assign NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d2102 = - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159] || - requestR[127:96] == 32'hFFFFFFFF && requestR[95]) && - (requestR[191:160] == 32'hFFFFFFFF && requestR[159] || - requestR[127:96] != 32'hFFFFFFFF || - !requestR[95]) && - ((requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ? - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2098 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2099) ; - assign NOT_requestR_3_BIT_158_31_32_AND_NOT_requestR__ETC___d822 = - !requestR[158] && !requestR[157] && !requestR[156] && - !requestR[155] && - !requestR[154] && - !requestR[153] && - !requestR[152] && - !requestR[151] && - !requestR[150] && - !requestR[149] && - !requestR[148] && - !requestR[147] && - !requestR[146] && - !requestR[145] && - !requestR[144] && - !requestR[143] && - !requestR[142] && - !requestR[141] && - !requestR[140] && - !requestR[139] && - !requestR[138] && - !requestR[137] && - !requestR[136] && - !requestR[135] && - !requestR[134] && - !requestR[133] && - !requestR[132] && - !requestR[131] && - !requestR[130] && - !requestR[129] && - !requestR[128] ; - assign NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 = - !requestR[179] && !requestR[178] && !requestR[177] && - !requestR[176] && - !requestR[175] && - !requestR[174] && - !requestR[173] && - !requestR[172] && - !requestR[171] && - !requestR[170] && - !requestR[169] && - !requestR[168] && - !requestR[167] && - !requestR[166] && - !requestR[165] && - !requestR[164] && - !requestR[163] && - !requestR[162] && - !requestR[161] && - !requestR[160] && - !requestR[159] && - NOT_requestR_3_BIT_158_31_32_AND_NOT_requestR__ETC___d822 ; - assign NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d1013 = - !requestR[191] && !requestR[190] && !requestR[189] && - !requestR[188] && - !requestR[187] && - !requestR[186] && - !requestR[185] && - !requestR[184] && - !requestR[183] && - !requestR[182] && - !requestR[181] && - !requestR[180] && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 || - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 || - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 ; - assign NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d3048 = - !requestR[191] && !requestR[190] && !requestR[189] && - !requestR[188] && - !requestR[187] && - !requestR[186] && - !requestR[185] && - !requestR[184] && - !requestR[183] && - !requestR[182] && - !requestR[181] && - !requestR[180] && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 || - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 || - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568 = - { {4{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696[7]}}, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696 } ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568 + - 12'd1023 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q153 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150[10:0] - - 11'd1023 ; - assign SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737 = - { requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620[10], - requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620 } ; - assign SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 = - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 = - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737 + - 12'd127 ; - assign SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q121 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118[7:0] - - 8'd127 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d3542 = - ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d3540 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282 = - { 3'd0, - _theResult___fst_exp__h118551 == 8'd0 && - (sfdin__h118545[56:34] == 23'd0 || guard__h110454 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h119178 == 8'd255 && - _theResult___fst_sfd__h119179 == 23'd0, - 1'd0, - _theResult___fst_exp__h118551 != 8'd255 && - guard__h110454 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d4819 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d4817 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104 = - { 3'd0, - _theResult___fst_exp__h177684 == 11'd0 && - (sfdin__h177678[56:5] == 52'd0 || guard__h169458 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h178514 == 11'd2047 && - _theResult___fst_sfd__h178515 == 52'd0, - 1'd0, - _theResult___fst_exp__h177684 != 11'd2047 && - guard__h169458 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d3986 = - ({ 3'd0, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d3984 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311 = - { 3'd0, - _theResult___fst_exp__h136404 == 8'd0 && - (sfdin__h136398[56:34] == 23'd0 || guard__h128178 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h137031 == 8'd255 && - _theResult___fst_sfd__h137032 == 23'd0, - 1'd0, - _theResult___fst_exp__h136404 != 8'd255 && - guard__h128178 != 2'b0 } ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4499 = - ({ 6'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4892 = - ({ 6'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 } ^ - 12'h800) <= - (IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d4891 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087 = - { 3'd0, - _theResult___fst_exp__h168111 == 11'd0 && - guard__h160150 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h168867 == 11'd2047 && - _theResult___fst_sfd__h168868 == 52'd0, - 1'd0, - _theResult___fst_exp__h168111 != 11'd2047 && - guard__h160150 != 2'b0 } ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d3664 = - ({ 3'd0, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4059 = - ({ 3'd0, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 } ^ - 9'h100) <= - (IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4058 ^ - 9'h100) ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294 = - { 3'd0, - _theResult___fst_exp__h127237 == 8'd0 && - guard__h119189 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h127790 == 8'd255 && - _theResult___fst_sfd__h127791 == 23'd0, - 1'd0, - _theResult___fst_exp__h127237 != 8'd255 && - guard__h119189 != 2'b0 } ; - assign _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d4575 = - b__h39635 >> - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d4571 ; - assign _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_608__ETC___d3744 = - sfd__h102814 >> - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_608_ETC___d3740 ; - assign _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78 = - { 33'h1AAAAAAAA, - requestR[63:32] == 32'hFFFFFFFF && requestR[31], - (requestR[63:32] == 32'hFFFFFFFF) ? - requestR[30:0] : - 31'h7FC00000 } ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3306 = - 12'd3074 - - { 6'd0, - requestR[179] ? - 6'd0 : - (requestR[178] ? - 6'd1 : - (requestR[177] ? - 6'd2 : - (requestR[176] ? - 6'd3 : - (requestR[175] ? - 6'd4 : - (requestR[174] ? - 6'd5 : - (requestR[173] ? - 6'd6 : - (requestR[172] ? - 6'd7 : - (requestR[171] ? - 6'd8 : - (requestR[170] ? - 6'd9 : - (requestR[169] ? - 6'd10 : - (requestR[168] ? - 6'd11 : - (requestR[167] ? - 6'd12 : - (requestR[166] ? - 6'd13 : - (requestR[165] ? - 6'd14 : - (requestR[164] ? - 6'd15 : - (requestR[163] ? - 6'd16 : - (requestR[162] ? - 6'd17 : - (requestR[161] ? - 6'd18 : - (requestR[160] ? - 6'd19 : - (requestR[159] ? - 6'd20 : - (requestR[158] ? - 6'd21 : - (requestR[157] ? - 6'd22 : - (requestR[156] ? - 6'd23 : - (requestR[155] ? - 6'd24 : - (requestR[154] ? - 6'd25 : - (requestR[153] ? - 6'd26 : - (requestR[152] ? - 6'd27 : - (requestR[151] ? - 6'd28 : - (requestR[150] ? - 6'd29 : - (requestR[149] ? - 6'd30 : - (requestR[148] ? - 6'd31 : - (requestR[147] ? - 6'd32 : - (requestR[146] ? - 6'd33 : - (requestR[145] ? - 6'd34 : - (requestR[144] ? - 6'd35 : - (requestR[143] ? - 6'd36 : - (requestR[142] ? - 6'd37 : - (requestR[141] ? - 6'd38 : - (requestR[140] ? - 6'd39 : - (requestR[139] ? - 6'd40 : - (requestR[138] ? - 6'd41 : - (requestR[137] ? - 6'd42 : - (requestR[136] ? - 6'd43 : - (requestR[135] ? - 6'd44 : - (requestR[134] ? - 6'd45 : - (requestR[133] ? - 6'd46 : - (requestR[132] ? - 6'd47 : - (requestR[131] ? - 6'd48 : - (requestR[130] ? - 6'd49 : - (requestR[129] ? - 6'd50 : - (requestR[128] ? - 6'd51 : - 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 = - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3306 ^ - 12'h800) <= - 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 = - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3306 ^ - 12'h800) < - 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4297 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282[4] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294[4]) ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4322 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282[3] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294[3]) ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4349 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282[1] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294[1]) ; - assign _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d4571 = - 12'd3074 - - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273 = - (9'd32 - - { 3'd0, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1270 }) - - 9'd1 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273 ^ - 9'h100) <= - 9'd383 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273 ^ - 9'h100) < - 9'd107 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273 ^ - 9'h100) < - 9'd130 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244 = - (12'd32 - - { 6'd0, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d2241 }) - - 12'd1 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244 ^ - 12'h800) <= - 12'd3071 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244 ^ - 12'h800) < - 12'd974 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244 ^ - 12'h800) < - 12'd1026 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527 = - (9'd32 - - { 3'd0, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1524 }) - - 9'd1 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527 ^ - 9'h100) <= - 9'd383 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527 ^ - 9'h100) < - 9'd107 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527 ^ - 9'h100) < - 9'd130 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458 = - (12'd32 - - { 6'd0, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d2455 }) - - 12'd1 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458 ^ - 12'h800) <= - 12'd3071 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458 ^ - 12'h800) < - 12'd974 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4425 = - 12'd3970 - - { 7'd0, - sV1_sfd__h1213[22] ? - 5'd0 : - (sV1_sfd__h1213[21] ? - 5'd1 : - (sV1_sfd__h1213[20] ? - 5'd2 : - (sV1_sfd__h1213[19] ? - 5'd3 : - (sV1_sfd__h1213[18] ? - 5'd4 : - (sV1_sfd__h1213[17] ? - 5'd5 : - (sV1_sfd__h1213[16] ? - 5'd6 : - (sV1_sfd__h1213[15] ? - 5'd7 : - (sV1_sfd__h1213[14] ? - 5'd8 : - (sV1_sfd__h1213[13] ? - 5'd9 : - (sV1_sfd__h1213[12] ? - 5'd10 : - (sV1_sfd__h1213[11] ? - 5'd11 : - (sV1_sfd__h1213[10] ? - 5'd12 : - (sV1_sfd__h1213[9] ? - 5'd13 : - (sV1_sfd__h1213[8] ? - 5'd14 : - (sV1_sfd__h1213[7] ? - 5'd15 : - (sV1_sfd__h1213[6] ? - 5'd16 : - (sV1_sfd__h1213[5] ? - 5'd17 : - (sV1_sfd__h1213[4] ? - 5'd18 : - (sV1_sfd__h1213[3] ? - 5'd19 : - (sV1_sfd__h1213[2] ? - 5'd20 : - (sV1_sfd__h1213[1] ? - 5'd21 : - (sV1_sfd__h1213[0] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 = - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4425 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 = - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4425 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_608_ETC___d3740 = - 12'd3970 - - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776 = - (12'd64 - - { 5'd0, - IF_IF_requestR_3_BIT_191_47_THEN_NEG_requestR__ETC___d404 }) - - 12'd1 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776 ^ - 12'h800) <= - 12'd3071 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776 ^ - 12'h800) < - 12'd974 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776 ^ - 12'h800) < - 12'd1026 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407 = - (9'd64 - - { 2'd0, - IF_IF_requestR_3_BIT_191_47_THEN_NEG_requestR__ETC___d404 }) - - 9'd1 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407 ^ - 9'h100) <= - 9'd383 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407 ^ - 9'h100) < - 9'd107 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407 ^ - 9'h100) < - 9'd130 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960 = - (12'd64 - - { 5'd0, - IF_requestR_3_BIT_191_47_THEN_0_ELSE_IF_reques_ETC___d920 }) - - 12'd1 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960 ^ - 12'h800) <= - 12'd3071 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960 ^ - 12'h800) < - 12'd974 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960 ^ - 12'h800) < - 12'd1026 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923 = - (9'd64 - - { 2'd0, - IF_requestR_3_BIT_191_47_THEN_0_ELSE_IF_reques_ETC___d920 }) - - 9'd1 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923 ^ - 9'h100) <= - 9'd383 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923 ^ - 9'h100) < - 9'd107 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923 ^ - 9'h100) < - 9'd130 ; - assign _theResult_____2__h36897 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1722 ? - out1___1__h37613 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[88:24] ; - assign _theResult_____2__h39570 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1869 ? - out1___1__h40062 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[56:24] ; - assign _theResult_____2__h71474 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2646 ? - out1___1__h71966 : - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[85:53] ; - assign _theResult_____2__h96108 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3131 ? - out1___1__h96824 : - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[117:53] ; - assign _theResult____h110444 = - (value__h71541 == 54'd0) ? sfd__h102814 : 57'd1 ; - assign _theResult____h128168 = - ((_3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_608_ETC___d3740 ^ - 12'h800) < - 12'd2105) ? - result__h128781 : - _theResult____h110444 ; - assign _theResult____h169448 = - ((_3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d4571 ^ - 12'h800) < - 12'd2105) ? - result__h170061 : - ((value__h36964 == 25'd0) ? b__h39635 : 57'd1) ; - assign _theResult___exp__h119077 = - sfd__h118643[24] ? - ((_theResult___fst_exp__h118551 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h145728) : - ((_theResult___fst_exp__h118551 == 8'd0 && - sfd__h118643[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h118551) ; - assign _theResult___exp__h12644 = - (sfd__h12245[24] || sfd__h12245[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h127689 = - sfd__h127255[24] ? - ((_theResult___fst_exp__h127237 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h145752) : - ((_theResult___fst_exp__h127237 == 8'd0 && - sfd__h127255[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h127237) ; - assign _theResult___exp__h13197 = - sfd__h12788[24] ? - ((x__h12773[7:0] == 8'd254) ? - 8'd255 : - din_inc___2_exp__h13340) : - ((x__h12773[7:0] == 8'd0 && sfd__h12788[24:23] == 2'b01) ? - 8'd1 : - x__h12773[7:0]) ; - assign _theResult___exp__h136930 = - sfd__h136496[24] ? - ((_theResult___fst_exp__h136404 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h145782) : - ((_theResult___fst_exp__h136404 == 8'd0 && - sfd__h136496[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h136404) ; - assign _theResult___exp__h145596 = - sfd__h145138[24] ? - ((_theResult___fst_exp__h145119 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h145806) : - ((_theResult___fst_exp__h145119 == 8'd0 && - sfd__h145138[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h145119) ; - assign _theResult___exp__h168766 = - sfd__h168129[53] ? - ((_theResult___fst_exp__h168111 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h187331) : - ((_theResult___fst_exp__h168111 == 11'd0 && - sfd__h168129[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h168111) ; - assign _theResult___exp__h178413 = - sfd__h177776[53] ? - ((_theResult___fst_exp__h177684 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h187361) : - ((_theResult___fst_exp__h177684 == 11'd0 && - sfd__h177776[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h177684) ; - assign _theResult___exp__h187195 = - sfd__h186534[53] ? - ((_theResult___fst_exp__h186515 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h187385) : - ((_theResult___fst_exp__h186515 == 11'd0 && - sfd__h186534[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h186515) ; - assign _theResult___exp__h23208 = - (sfd__h22812[24] || sfd__h22812[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h23760 = - sfd__h23351[24] ? - ((x__h23336[7:0] == 8'd254) ? - 8'd255 : - din_inc___2_exp__h23898) : - ((x__h23336[7:0] == 8'd0 && sfd__h23351[24:23] == 2'b01) ? - 8'd1 : - x__h23336[7:0]) ; - assign _theResult___exp__h29580 = - (sfd__h29184[24] || sfd__h29184[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h30133 = - sfd__h29724[24] ? - ((x__h29709[7:0] == 8'd254) ? - 8'd255 : - din_inc___2_exp__h30276) : - ((x__h29709[7:0] == 8'd0 && sfd__h29724[24:23] == 2'b01) ? - 8'd1 : - x__h29709[7:0]) ; - assign _theResult___exp__h35696 = - (sfd__h35300[24] || sfd__h35300[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h36248 = - sfd__h35839[24] ? - ((x__h35824[7:0] == 8'd254) ? - 8'd255 : - din_inc___2_exp__h36386) : - ((x__h35824[7:0] == 8'd0 && sfd__h35839[24:23] == 2'b01) ? - 8'd1 : - x__h35824[7:0]) ; - assign _theResult___exp__h60430 = - (sfd__h59831[53] || sfd__h59831[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h61186 = - sfd__h60574[53] ? - ((x__h60559[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h61329) : - ((x__h60559[10:0] == 11'd0 && sfd__h60574[53:52] == 2'b01) ? - 11'd1 : - x__h60559[10:0]) ; - assign _theResult___exp__h70071 = - (sfd__h69472[53] || sfd__h69472[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h70826 = - sfd__h70214[53] ? - ((x__h70199[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h70964) : - ((x__h70199[10:0] == 11'd0 && sfd__h70214[53:52] == 2'b01) ? - 11'd1 : - x__h70199[10:0]) ; - assign _theResult___exp__h83751 = - (sfd__h83152[53] || sfd__h83152[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h84507 = - sfd__h83895[53] ? - ((x__h83880[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h84650) : - ((x__h83880[10:0] == 11'd0 && sfd__h83895[53:52] == 2'b01) ? - 11'd1 : - x__h83880[10:0]) ; - assign _theResult___exp__h94708 = - (sfd__h94109[53] || sfd__h94109[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h95463 = - sfd__h94851[53] ? - ((x__h94836[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h95601) : - ((x__h94836[10:0] == 11'd0 && sfd__h94851[53:52] == 2'b01) ? - 11'd1 : - x__h94836[10:0]) ; - assign _theResult___fst_exp__h110426 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 8'd255 : - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 ; - assign _theResult___fst_exp__h118551 = - _theResult____h110444[56] ? - 8'd2 : - _theResult___fst_exp__h118625 ; - assign _theResult___fst_exp__h118616 = - 8'd0 - - { 2'd0, - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d3540 } ; - assign _theResult___fst_exp__h118622 = - (!_theResult____h110444[56] && !_theResult____h110444[55] && - !_theResult____h110444[54] && - !_theResult____h110444[53] && - !_theResult____h110444[52] && - !_theResult____h110444[51] && - !_theResult____h110444[50] && - !_theResult____h110444[49] && - !_theResult____h110444[48] && - !_theResult____h110444[47] && - !_theResult____h110444[46] && - !_theResult____h110444[45] && - !_theResult____h110444[44] && - !_theResult____h110444[43] && - !_theResult____h110444[42] && - !_theResult____h110444[41] && - !_theResult____h110444[40] && - !_theResult____h110444[39] && - !_theResult____h110444[38] && - !_theResult____h110444[37] && - !_theResult____h110444[36] && - !_theResult____h110444[35] && - !_theResult____h110444[34] && - !_theResult____h110444[33] && - !_theResult____h110444[32] && - !_theResult____h110444[31] && - !_theResult____h110444[30] && - !_theResult____h110444[29] && - !_theResult____h110444[28] && - !_theResult____h110444[27] && - !_theResult____h110444[26] && - !_theResult____h110444[25] && - !_theResult____h110444[24] && - !_theResult____h110444[23] && - !_theResult____h110444[22] && - !_theResult____h110444[21] && - !_theResult____h110444[20] && - !_theResult____h110444[19] && - !_theResult____h110444[18] && - !_theResult____h110444[17] && - !_theResult____h110444[16] && - !_theResult____h110444[15] && - !_theResult____h110444[14] && - !_theResult____h110444[13] && - !_theResult____h110444[12] && - !_theResult____h110444[11] && - !_theResult____h110444[10] && - !_theResult____h110444[9] && - !_theResult____h110444[8] && - !_theResult____h110444[7] && - !_theResult____h110444[6] && - !_theResult____h110444[5] && - !_theResult____h110444[4] && - !_theResult____h110444[3] && - !_theResult____h110444[2] && - !_theResult____h110444[1] && - !_theResult____h110444[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d3542) ? - 8'd0 : - _theResult___fst_exp__h118616 ; - assign _theResult___fst_exp__h118625 = - (!_theResult____h110444[56] && _theResult____h110444[55]) ? - 8'd1 : - _theResult___fst_exp__h118622 ; - assign _theResult___fst_exp__h119175 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q125 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 ; - assign _theResult___fst_exp__h119178 = - (_theResult___fst_exp__h118551 == 8'd255) ? - _theResult___fst_exp__h118551 : - _theResult___fst_exp__h119175 ; - assign _theResult___fst_exp__h127228 = - 8'd129 - - { 2'd0, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 } ; - assign _theResult___fst_exp__h127234 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 || - !_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d3664) ? - 8'd0 : - _theResult___fst_exp__h127228 ; - assign _theResult___fst_exp__h127237 = - (requestR[190:180] == 11'd0) ? - _theResult___fst_exp__h127234 : - 8'd129 ; - assign _theResult___fst_exp__h12741 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2228_0b0_0_0b1_0_0b10_out_exp2647_0b_ETC__q15 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499 ; - assign _theResult___fst_exp__h127787 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q129 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 ; - assign _theResult___fst_exp__h127790 = - (_theResult___fst_exp__h127237 == 8'd255) ? - _theResult___fst_exp__h127237 : - _theResult___fst_exp__h127787 ; - assign _theResult___fst_exp__h13294 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_x2773_ETC__q17 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 ; - assign _theResult___fst_exp__h13297 = - (x__h12773[7:0] == 8'd255) ? - x__h12773[7:0] : - _theResult___fst_exp__h13294 ; - assign _theResult___fst_exp__h136404 = - _theResult____h128168[56] ? - 8'd2 : - _theResult___fst_exp__h136478 ; - assign _theResult___fst_exp__h136469 = - 8'd0 - - { 2'd0, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d3984 } ; - assign _theResult___fst_exp__h136475 = - (!_theResult____h128168[56] && !_theResult____h128168[55] && - !_theResult____h128168[54] && - !_theResult____h128168[53] && - !_theResult____h128168[52] && - !_theResult____h128168[51] && - !_theResult____h128168[50] && - !_theResult____h128168[49] && - !_theResult____h128168[48] && - !_theResult____h128168[47] && - !_theResult____h128168[46] && - !_theResult____h128168[45] && - !_theResult____h128168[44] && - !_theResult____h128168[43] && - !_theResult____h128168[42] && - !_theResult____h128168[41] && - !_theResult____h128168[40] && - !_theResult____h128168[39] && - !_theResult____h128168[38] && - !_theResult____h128168[37] && - !_theResult____h128168[36] && - !_theResult____h128168[35] && - !_theResult____h128168[34] && - !_theResult____h128168[33] && - !_theResult____h128168[32] && - !_theResult____h128168[31] && - !_theResult____h128168[30] && - !_theResult____h128168[29] && - !_theResult____h128168[28] && - !_theResult____h128168[27] && - !_theResult____h128168[26] && - !_theResult____h128168[25] && - !_theResult____h128168[24] && - !_theResult____h128168[23] && - !_theResult____h128168[22] && - !_theResult____h128168[21] && - !_theResult____h128168[20] && - !_theResult____h128168[19] && - !_theResult____h128168[18] && - !_theResult____h128168[17] && - !_theResult____h128168[16] && - !_theResult____h128168[15] && - !_theResult____h128168[14] && - !_theResult____h128168[13] && - !_theResult____h128168[12] && - !_theResult____h128168[11] && - !_theResult____h128168[10] && - !_theResult____h128168[9] && - !_theResult____h128168[8] && - !_theResult____h128168[7] && - !_theResult____h128168[6] && - !_theResult____h128168[5] && - !_theResult____h128168[4] && - !_theResult____h128168[3] && - !_theResult____h128168[2] && - !_theResult____h128168[1] && - !_theResult____h128168[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d3986) ? - 8'd0 : - _theResult___fst_exp__h136469 ; - assign _theResult___fst_exp__h136478 = - (!_theResult____h128168[56] && _theResult____h128168[55]) ? - 8'd1 : - _theResult___fst_exp__h136475 ; - assign _theResult___fst_exp__h137028 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q127 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 ; - assign _theResult___fst_exp__h137031 = - (_theResult___fst_exp__h136404 == 8'd255) ? - _theResult___fst_exp__h136404 : - _theResult___fst_exp__h137028 ; - assign _theResult___fst_exp__h145071 = - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118[7:0] == - 8'd0) ? - 8'd1 : - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118[7:0] ; - assign _theResult___fst_exp__h145110 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118[7:0] - - { 2'd0, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 } ; - assign _theResult___fst_exp__h145116 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 || - !_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4059) ? - 8'd0 : - _theResult___fst_exp__h145110 ; - assign _theResult___fst_exp__h145119 = - (requestR[190:180] == 11'd0) ? - _theResult___fst_exp__h145116 : - _theResult___fst_exp__h145071 ; - assign _theResult___fst_exp__h145694 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q131 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 ; - assign _theResult___fst_exp__h145697 = - (_theResult___fst_exp__h145119 == 8'd255) ? - _theResult___fst_exp__h145119 : - _theResult___fst_exp__h145694 ; - assign _theResult___fst_exp__h145706 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 ? - _theResult___snd_fst_exp__h127793 : - _theResult___fst_exp__h110426) : - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 ? - _theResult___snd_fst_exp__h145700 : - _theResult___fst_exp__h110426) ; - assign _theResult___fst_exp__h145709 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 8'd0 : - _theResult___fst_exp__h145706 ; - assign _theResult___fst_exp__h153038 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 11'd2047 : - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 ; - assign _theResult___fst_exp__h168102 = - 11'd897 - - { 5'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 } ; - assign _theResult___fst_exp__h168108 = - (sV1_exp__h1212 == 8'd0 && !sV1_sfd__h1213[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470 || - !_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4499) ? - 11'd0 : - _theResult___fst_exp__h168102 ; - assign _theResult___fst_exp__h168111 = - (sV1_exp__h1212 == 8'd0) ? - _theResult___fst_exp__h168108 : - 11'd897 ; - assign _theResult___fst_exp__h168864 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q157 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 ; - assign _theResult___fst_exp__h168867 = - (_theResult___fst_exp__h168111 == 11'd2047) ? - _theResult___fst_exp__h168111 : - _theResult___fst_exp__h168864 ; - assign _theResult___fst_exp__h177684 = - _theResult____h169448[56] ? - 11'd2 : - _theResult___fst_exp__h177758 ; - assign _theResult___fst_exp__h177749 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d4817 } ; - assign _theResult___fst_exp__h177755 = - (!_theResult____h169448[56] && !_theResult____h169448[55] && - !_theResult____h169448[54] && - !_theResult____h169448[53] && - !_theResult____h169448[52] && - !_theResult____h169448[51] && - !_theResult____h169448[50] && - !_theResult____h169448[49] && - !_theResult____h169448[48] && - !_theResult____h169448[47] && - !_theResult____h169448[46] && - !_theResult____h169448[45] && - !_theResult____h169448[44] && - !_theResult____h169448[43] && - !_theResult____h169448[42] && - !_theResult____h169448[41] && - !_theResult____h169448[40] && - !_theResult____h169448[39] && - !_theResult____h169448[38] && - !_theResult____h169448[37] && - !_theResult____h169448[36] && - !_theResult____h169448[35] && - !_theResult____h169448[34] && - !_theResult____h169448[33] && - !_theResult____h169448[32] && - !_theResult____h169448[31] && - !_theResult____h169448[30] && - !_theResult____h169448[29] && - !_theResult____h169448[28] && - !_theResult____h169448[27] && - !_theResult____h169448[26] && - !_theResult____h169448[25] && - !_theResult____h169448[24] && - !_theResult____h169448[23] && - !_theResult____h169448[22] && - !_theResult____h169448[21] && - !_theResult____h169448[20] && - !_theResult____h169448[19] && - !_theResult____h169448[18] && - !_theResult____h169448[17] && - !_theResult____h169448[16] && - !_theResult____h169448[15] && - !_theResult____h169448[14] && - !_theResult____h169448[13] && - !_theResult____h169448[12] && - !_theResult____h169448[11] && - !_theResult____h169448[10] && - !_theResult____h169448[9] && - !_theResult____h169448[8] && - !_theResult____h169448[7] && - !_theResult____h169448[6] && - !_theResult____h169448[5] && - !_theResult____h169448[4] && - !_theResult____h169448[3] && - !_theResult____h169448[2] && - !_theResult____h169448[1] && - !_theResult____h169448[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d4819) ? - 11'd0 : - _theResult___fst_exp__h177749 ; - assign _theResult___fst_exp__h177758 = - (!_theResult____h169448[56] && _theResult____h169448[55]) ? - 11'd1 : - _theResult___fst_exp__h177755 ; - assign _theResult___fst_exp__h178511 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q159 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 ; - assign _theResult___fst_exp__h178514 = - (_theResult___fst_exp__h177684 == 11'd2047) ? - _theResult___fst_exp__h177684 : - _theResult___fst_exp__h178511 ; - assign _theResult___fst_exp__h186467 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150[10:0] == - 11'd0) ? - 11'd1 : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150[10:0] ; - assign _theResult___fst_exp__h186506 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150[10:0] - - { 5'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 } ; - assign _theResult___fst_exp__h186512 = - (sV1_exp__h1212 == 8'd0 && !sV1_sfd__h1213[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470 || - !_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4892) ? - 11'd0 : - _theResult___fst_exp__h186506 ; - assign _theResult___fst_exp__h186515 = - (sV1_exp__h1212 == 8'd0) ? - _theResult___fst_exp__h186512 : - _theResult___fst_exp__h186467 ; - assign _theResult___fst_exp__h187293 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q161 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 ; - assign _theResult___fst_exp__h187296 = - (_theResult___fst_exp__h186515 == 11'd2047) ? - _theResult___fst_exp__h186515 : - _theResult___fst_exp__h187293 ; - assign _theResult___fst_exp__h187305 = - (sV1_exp__h1212 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 ? - _theResult___snd_fst_exp__h168870 : - _theResult___fst_exp__h153038) : - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 ? - _theResult___snd_fst_exp__h187299 : - _theResult___fst_exp__h153038) ; - assign _theResult___fst_exp__h187308 = - (sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h187305 ; - assign _theResult___fst_exp__h23304 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2795_0b0_0_0b1_0_0b10_out_exp3211_0b_ETC__q26 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard2795_ETC__q28 ; - assign _theResult___fst_exp__h23856 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_x3336_ETC__q33 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004 ; - assign _theResult___fst_exp__h23859 = - (x__h23336[7:0] == 8'd255) ? - x__h23336[7:0] : - _theResult___fst_exp__h23856 ; - assign _theResult___fst_exp__h29677 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9167_0b0_0_0b1_0_0b10_out_exp9583_0b_ETC__q45 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356 ; - assign _theResult___fst_exp__h30230 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_x9709_ETC__q47 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 ; - assign _theResult___fst_exp__h30233 = - (x__h29709[7:0] == 8'd255) ? - x__h29709[7:0] : - _theResult___fst_exp__h30230 ; - assign _theResult___fst_exp__h35792 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5283_0b0_0_0b1_0_0b10_out_exp5699_0b_ETC__q54 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5283_ETC__q56 ; - assign _theResult___fst_exp__h36344 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_x5824_ETC__q58 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607 ; - assign _theResult___fst_exp__h36347 = - (x__h35824[7:0] == 8'd255) ? - x__h35824[7:0] : - _theResult___fst_exp__h36344 ; - assign _theResult___fst_exp__h60527 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9814_0b0_0_0b1_0_0b10_out_exp0433_0b_ETC__q78 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324 ; - assign _theResult___fst_exp__h61283 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_x055_ETC__q74 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 ; - assign _theResult___fst_exp__h61286 = - (x__h60559[10:0] == 11'd2047) ? - x__h60559[10:0] : - _theResult___fst_exp__h61283 ; - assign _theResult___fst_exp__h70167 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9455_0b0_0_0b1_0_0b10_out_exp0074_0b_ETC__q83 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard9455_ETC__q85 ; - assign _theResult___fst_exp__h70922 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_x019_ETC__q87 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539 ; - assign _theResult___fst_exp__h70925 = - (x__h70199[10:0] == 11'd2047) ? - x__h70199[10:0] : - _theResult___fst_exp__h70922 ; - assign _theResult___fst_exp__h83848 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3135_0b0_0_0b1_0_0b10_out_exp3754_0b_ETC__q103 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855 ; - assign _theResult___fst_exp__h84604 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_x388_ETC__q99 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 ; - assign _theResult___fst_exp__h84607 = - (x__h83880[10:0] == 11'd2047) ? - x__h83880[10:0] : - _theResult___fst_exp__h84604 ; - assign _theResult___fst_exp__h94804 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4092_0b0_0_0b1_0_0b10_out_exp4711_0b_ETC__q29 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard4092_ETC__q31 ; - assign _theResult___fst_exp__h95559 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_x483_ETC__q107 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039 ; - assign _theResult___fst_exp__h95562 = - (x__h94836[10:0] == 11'd2047) ? - x__h94836[10:0] : - _theResult___fst_exp__h95559 ; - assign _theResult___fst_sfd__h110427 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 23'd0 : - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 ; - assign _theResult___fst_sfd__h119176 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q133 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 ; - assign _theResult___fst_sfd__h119179 = - (_theResult___fst_exp__h118551 == 8'd255) ? - sfdin__h118545[56:34] : - _theResult___fst_sfd__h119176 ; - assign _theResult___fst_sfd__h12742 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q19 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 ; - assign _theResult___fst_sfd__h127788 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q135 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 ; - assign _theResult___fst_sfd__h127791 = - (_theResult___fst_exp__h127237 == 8'd255) ? - _theResult___snd__h127188[56:34] : - _theResult___fst_sfd__h127788 ; - assign _theResult___fst_sfd__h13295 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q21 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 ; - assign _theResult___fst_sfd__h13298 = - (x__h12773[7:0] == 8'd255) ? - sfd___3__h12218[62:40] : - _theResult___fst_sfd__h13295 ; - assign _theResult___fst_sfd__h137029 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q137 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 ; - assign _theResult___fst_sfd__h137032 = - (_theResult___fst_exp__h136404 == 8'd255) ? - sfdin__h136398[56:34] : - _theResult___fst_sfd__h137029 ; - assign _theResult___fst_sfd__h145695 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q139 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 ; - assign _theResult___fst_sfd__h145698 = - (_theResult___fst_exp__h145119 == 8'd255) ? - _theResult___snd__h145065[56:34] : - _theResult___fst_sfd__h145695 ; - assign _theResult___fst_sfd__h145707 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 ? - _theResult___snd_fst_sfd__h127794 : - _theResult___fst_sfd__h110427) : - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 ? - _theResult___snd_fst_sfd__h145701 : - _theResult___fst_sfd__h110427) ; - assign _theResult___fst_sfd__h145713 = - ((requestR[190:180] == 11'd2047 || requestR[190:180] == 11'd0) && - requestR[179:128] == 52'd0) ? - 23'd0 : - _theResult___fst_sfd__h145707 ; - assign _theResult___fst_sfd__h147557 = { 1'd1, sV1_sfd__h1213[21:0] } ; - assign _theResult___fst_sfd__h153039 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 52'd0 : - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 ; - assign _theResult___fst_sfd__h168865 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q169 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 ; - assign _theResult___fst_sfd__h168868 = - (_theResult___fst_exp__h168111 == 11'd2047) ? - _theResult___snd__h168062[56:5] : - _theResult___fst_sfd__h168865 ; - assign _theResult___fst_sfd__h178512 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q171 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 ; - assign _theResult___fst_sfd__h178515 = - (_theResult___fst_exp__h177684 == 11'd2047) ? - sfdin__h177678[56:5] : - _theResult___fst_sfd__h178512 ; - assign _theResult___fst_sfd__h187294 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q173 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 ; - assign _theResult___fst_sfd__h187297 = - (_theResult___fst_exp__h186515 == 11'd2047) ? - _theResult___snd__h186461[56:5] : - _theResult___fst_sfd__h187294 ; - assign _theResult___fst_sfd__h187306 = - (sV1_exp__h1212 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 ? - _theResult___snd_fst_sfd__h168871 : - _theResult___fst_sfd__h153039) : - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 ? - _theResult___snd_fst_sfd__h187300 : - _theResult___fst_sfd__h153039) ; - assign _theResult___fst_sfd__h187312 = - ((sV1_exp__h1212 == 8'd255 || sV1_exp__h1212 == 8'd0) && - sV1_sfd__h1213 == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h187306 ; - assign _theResult___fst_sfd__h23305 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q37 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027 ; - assign _theResult___fst_sfd__h23857 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q35 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042 ; - assign _theResult___fst_sfd__h23860 = - (x__h23336[7:0] == 8'd255) ? - sfd___3__h22785[62:40] : - _theResult___fst_sfd__h23857 ; - assign _theResult___fst_sfd__h29678 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q49 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 ; - assign _theResult___fst_sfd__h30231 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q51 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 ; - assign _theResult___fst_sfd__h30234 = - (x__h29709[7:0] == 8'd255) ? - sfd___3__h29157[30:8] : - _theResult___fst_sfd__h30231 ; - assign _theResult___fst_sfd__h35793 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q62 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630 ; - assign _theResult___fst_sfd__h36345 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q60 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645 ; - assign _theResult___fst_sfd__h36348 = - (x__h35824[7:0] == 8'd255) ? - sfd___3__h35273[30:8] : - _theResult___fst_sfd__h36345 ; - assign _theResult___fst_sfd__h60528 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q80 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 ; - assign _theResult___fst_sfd__h61284 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q76 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 ; - assign _theResult___fst_sfd__h61287 = - (x__h60559[10:0] == 11'd2047) ? - sfd___3__h59804[53:2] : - _theResult___fst_sfd__h61284 ; - assign _theResult___fst_sfd__h70168 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q91 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561 ; - assign _theResult___fst_sfd__h70923 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q89 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576 ; - assign _theResult___fst_sfd__h70926 = - (x__h70199[10:0] == 11'd2047) ? - sfd___3__h69445[53:2] : - _theResult___fst_sfd__h70923 ; - assign _theResult___fst_sfd__h83849 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q105 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 ; - assign _theResult___fst_sfd__h84605 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q101 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 ; - assign _theResult___fst_sfd__h84608 = - (x__h83880[10:0] == 11'd2047) ? - sfd___3__h12218[62:11] : - _theResult___fst_sfd__h84605 ; - assign _theResult___fst_sfd__h94805 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q111 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062 ; - assign _theResult___fst_sfd__h95560 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q109 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077 ; - assign _theResult___fst_sfd__h95563 = - (x__h94836[10:0] == 11'd2047) ? - sfd___3__h22785[62:11] : - _theResult___fst_sfd__h95560 ; - assign _theResult___fst_sfd__h99110 = { 1'd1, requestR[178:128] } ; - assign _theResult___sfd__h119078 = - sfd__h118643[24] ? - ((_theResult___fst_exp__h118551 == 8'd254) ? - 23'd0 : - sfd__h118643[23:1]) : - sfd__h118643[22:0] ; - assign _theResult___sfd__h12645 = - sfd__h12245[24] ? sfd__h12245[23:1] : sfd__h12245[22:0] ; - assign _theResult___sfd__h127690 = - sfd__h127255[24] ? - ((_theResult___fst_exp__h127237 == 8'd254) ? - 23'd0 : - sfd__h127255[23:1]) : - sfd__h127255[22:0] ; - assign _theResult___sfd__h13198 = - sfd__h12788[24] ? - ((x__h12773[7:0] == 8'd254) ? 23'd0 : sfd__h12788[23:1]) : - sfd__h12788[22:0] ; - assign _theResult___sfd__h136931 = - sfd__h136496[24] ? - ((_theResult___fst_exp__h136404 == 8'd254) ? - 23'd0 : - sfd__h136496[23:1]) : - sfd__h136496[22:0] ; - assign _theResult___sfd__h145597 = - sfd__h145138[24] ? - ((_theResult___fst_exp__h145119 == 8'd254) ? - 23'd0 : - sfd__h145138[23:1]) : - sfd__h145138[22:0] ; - assign _theResult___sfd__h168767 = - sfd__h168129[53] ? - ((_theResult___fst_exp__h168111 == 11'd2046) ? - 52'd0 : - sfd__h168129[52:1]) : - sfd__h168129[51:0] ; - assign _theResult___sfd__h178414 = - sfd__h177776[53] ? - ((_theResult___fst_exp__h177684 == 11'd2046) ? - 52'd0 : - sfd__h177776[52:1]) : - sfd__h177776[51:0] ; - assign _theResult___sfd__h187196 = - sfd__h186534[53] ? - ((_theResult___fst_exp__h186515 == 11'd2046) ? - 52'd0 : - sfd__h186534[52:1]) : - sfd__h186534[51:0] ; - assign _theResult___sfd__h23209 = - sfd__h22812[24] ? sfd__h22812[23:1] : sfd__h22812[22:0] ; - assign _theResult___sfd__h23761 = - sfd__h23351[24] ? - ((x__h23336[7:0] == 8'd254) ? 23'd0 : sfd__h23351[23:1]) : - sfd__h23351[22:0] ; - assign _theResult___sfd__h29581 = - sfd__h29184[24] ? sfd__h29184[23:1] : sfd__h29184[22:0] ; - assign _theResult___sfd__h30134 = - sfd__h29724[24] ? - ((x__h29709[7:0] == 8'd254) ? 23'd0 : sfd__h29724[23:1]) : - sfd__h29724[22:0] ; - assign _theResult___sfd__h35697 = - sfd__h35300[24] ? sfd__h35300[23:1] : sfd__h35300[22:0] ; - assign _theResult___sfd__h36249 = - sfd__h35839[24] ? - ((x__h35824[7:0] == 8'd254) ? 23'd0 : sfd__h35839[23:1]) : - sfd__h35839[22:0] ; - assign _theResult___sfd__h60431 = - sfd__h59831[53] ? sfd__h59831[52:1] : sfd__h59831[51:0] ; - assign _theResult___sfd__h61187 = - sfd__h60574[53] ? - ((x__h60559[10:0] == 11'd2046) ? 52'd0 : sfd__h60574[52:1]) : - sfd__h60574[51:0] ; - assign _theResult___sfd__h70072 = - sfd__h69472[53] ? sfd__h69472[52:1] : sfd__h69472[51:0] ; - assign _theResult___sfd__h70827 = - sfd__h70214[53] ? - ((x__h70199[10:0] == 11'd2046) ? 52'd0 : sfd__h70214[52:1]) : - sfd__h70214[51:0] ; - assign _theResult___sfd__h83752 = - sfd__h83152[53] ? sfd__h83152[52:1] : sfd__h83152[51:0] ; - assign _theResult___sfd__h84508 = - sfd__h83895[53] ? - ((x__h83880[10:0] == 11'd2046) ? 52'd0 : sfd__h83895[52:1]) : - sfd__h83895[51:0] ; - assign _theResult___sfd__h94709 = - sfd__h94109[53] ? sfd__h94109[52:1] : sfd__h94109[51:0] ; - assign _theResult___sfd__h95464 = - sfd__h94851[53] ? - ((x__h94836[10:0] == 11'd2046) ? 52'd0 : sfd__h94851[52:1]) : - sfd__h94851[51:0] ; - assign _theResult___snd__h118562 = { _theResult____h110444[55:0], 1'd0 } ; - assign _theResult___snd__h118573 = - (!_theResult____h110444[56] && _theResult____h110444[55]) ? - _theResult___snd__h118575 : - _theResult___snd__h118585 ; - assign _theResult___snd__h118575 = { _theResult____h110444[54:0], 2'd0 } ; - assign _theResult___snd__h118585 = - (!_theResult____h110444[56] && !_theResult____h110444[55] && - !_theResult____h110444[54] && - !_theResult____h110444[53] && - !_theResult____h110444[52] && - !_theResult____h110444[51] && - !_theResult____h110444[50] && - !_theResult____h110444[49] && - !_theResult____h110444[48] && - !_theResult____h110444[47] && - !_theResult____h110444[46] && - !_theResult____h110444[45] && - !_theResult____h110444[44] && - !_theResult____h110444[43] && - !_theResult____h110444[42] && - !_theResult____h110444[41] && - !_theResult____h110444[40] && - !_theResult____h110444[39] && - !_theResult____h110444[38] && - !_theResult____h110444[37] && - !_theResult____h110444[36] && - !_theResult____h110444[35] && - !_theResult____h110444[34] && - !_theResult____h110444[33] && - !_theResult____h110444[32] && - !_theResult____h110444[31] && - !_theResult____h110444[30] && - !_theResult____h110444[29] && - !_theResult____h110444[28] && - !_theResult____h110444[27] && - !_theResult____h110444[26] && - !_theResult____h110444[25] && - !_theResult____h110444[24] && - !_theResult____h110444[23] && - !_theResult____h110444[22] && - !_theResult____h110444[21] && - !_theResult____h110444[20] && - !_theResult____h110444[19] && - !_theResult____h110444[18] && - !_theResult____h110444[17] && - !_theResult____h110444[16] && - !_theResult____h110444[15] && - !_theResult____h110444[14] && - !_theResult____h110444[13] && - !_theResult____h110444[12] && - !_theResult____h110444[11] && - !_theResult____h110444[10] && - !_theResult____h110444[9] && - !_theResult____h110444[8] && - !_theResult____h110444[7] && - !_theResult____h110444[6] && - !_theResult____h110444[5] && - !_theResult____h110444[4] && - !_theResult____h110444[3] && - !_theResult____h110444[2] && - !_theResult____h110444[1] && - !_theResult____h110444[0]) ? - _theResult____h110444 : - _theResult___snd__h118591 ; - assign _theResult___snd__h118591 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q114[54:0], - 2'd0 } ; - assign _theResult___snd__h118614 = - _theResult____h110444 << - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d3540 ; - assign _theResult___snd__h127188 = - (requestR[190:180] == 11'd0) ? - _theResult___snd__h127197 : - _theResult___snd__h127190 ; - assign _theResult___snd__h127190 = { requestR[179:128], 5'd0 } ; - assign _theResult___snd__h127197 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843) ? - sfd__h102814 : - _theResult___snd__h127203 ; - assign _theResult___snd__h127203 = - { IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q116[54:0], - 2'd0 } ; - assign _theResult___snd__h127226 = - sfd__h102814 << - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 ; - assign _theResult___snd__h136415 = { _theResult____h128168[55:0], 1'd0 } ; - assign _theResult___snd__h136426 = - (!_theResult____h128168[56] && _theResult____h128168[55]) ? - _theResult___snd__h136428 : - _theResult___snd__h136438 ; - assign _theResult___snd__h136428 = { _theResult____h128168[54:0], 2'd0 } ; - assign _theResult___snd__h136438 = - (!_theResult____h128168[56] && !_theResult____h128168[55] && - !_theResult____h128168[54] && - !_theResult____h128168[53] && - !_theResult____h128168[52] && - !_theResult____h128168[51] && - !_theResult____h128168[50] && - !_theResult____h128168[49] && - !_theResult____h128168[48] && - !_theResult____h128168[47] && - !_theResult____h128168[46] && - !_theResult____h128168[45] && - !_theResult____h128168[44] && - !_theResult____h128168[43] && - !_theResult____h128168[42] && - !_theResult____h128168[41] && - !_theResult____h128168[40] && - !_theResult____h128168[39] && - !_theResult____h128168[38] && - !_theResult____h128168[37] && - !_theResult____h128168[36] && - !_theResult____h128168[35] && - !_theResult____h128168[34] && - !_theResult____h128168[33] && - !_theResult____h128168[32] && - !_theResult____h128168[31] && - !_theResult____h128168[30] && - !_theResult____h128168[29] && - !_theResult____h128168[28] && - !_theResult____h128168[27] && - !_theResult____h128168[26] && - !_theResult____h128168[25] && - !_theResult____h128168[24] && - !_theResult____h128168[23] && - !_theResult____h128168[22] && - !_theResult____h128168[21] && - !_theResult____h128168[20] && - !_theResult____h128168[19] && - !_theResult____h128168[18] && - !_theResult____h128168[17] && - !_theResult____h128168[16] && - !_theResult____h128168[15] && - !_theResult____h128168[14] && - !_theResult____h128168[13] && - !_theResult____h128168[12] && - !_theResult____h128168[11] && - !_theResult____h128168[10] && - !_theResult____h128168[9] && - !_theResult____h128168[8] && - !_theResult____h128168[7] && - !_theResult____h128168[6] && - !_theResult____h128168[5] && - !_theResult____h128168[4] && - !_theResult____h128168[3] && - !_theResult____h128168[2] && - !_theResult____h128168[1] && - !_theResult____h128168[0]) ? - _theResult____h128168 : - _theResult___snd__h136444 ; - assign _theResult___snd__h136444 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q119[54:0], - 2'd0 } ; - assign _theResult___snd__h136467 = - _theResult____h128168 << - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d3984 ; - assign _theResult___snd__h145065 = - (requestR[190:180] == 11'd0) ? - _theResult___snd__h145079 : - _theResult___snd__h127190 ; - assign _theResult___snd__h145079 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843) ? - sfd__h102814 : - _theResult___snd__h145085 ; - assign _theResult___snd__h145085 = - { IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q122[54:0], - 2'd0 } ; - assign _theResult___snd__h145103 = - sfd__h102814 << - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4058 ; - assign _theResult___snd__h168062 = - (sV1_exp__h1212 == 8'd0) ? - _theResult___snd__h168071 : - _theResult___snd__h168064 ; - assign _theResult___snd__h168064 = { sV1_sfd__h1213, 34'd0 } ; - assign _theResult___snd__h168071 = - (sV1_exp__h1212 == 8'd0 && !sV1_sfd__h1213[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470) ? - b__h39635 : - _theResult___snd__h168077 ; - assign _theResult___snd__h168077 = - { IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q148[54:0], - 2'd0 } ; - assign _theResult___snd__h168100 = - b__h39635 << - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 ; - assign _theResult___snd__h177695 = { _theResult____h169448[55:0], 1'd0 } ; - assign _theResult___snd__h177706 = - (!_theResult____h169448[56] && _theResult____h169448[55]) ? - _theResult___snd__h177708 : - _theResult___snd__h177718 ; - assign _theResult___snd__h177708 = { _theResult____h169448[54:0], 2'd0 } ; - assign _theResult___snd__h177718 = - (!_theResult____h169448[56] && !_theResult____h169448[55] && - !_theResult____h169448[54] && - !_theResult____h169448[53] && - !_theResult____h169448[52] && - !_theResult____h169448[51] && - !_theResult____h169448[50] && - !_theResult____h169448[49] && - !_theResult____h169448[48] && - !_theResult____h169448[47] && - !_theResult____h169448[46] && - !_theResult____h169448[45] && - !_theResult____h169448[44] && - !_theResult____h169448[43] && - !_theResult____h169448[42] && - !_theResult____h169448[41] && - !_theResult____h169448[40] && - !_theResult____h169448[39] && - !_theResult____h169448[38] && - !_theResult____h169448[37] && - !_theResult____h169448[36] && - !_theResult____h169448[35] && - !_theResult____h169448[34] && - !_theResult____h169448[33] && - !_theResult____h169448[32] && - !_theResult____h169448[31] && - !_theResult____h169448[30] && - !_theResult____h169448[29] && - !_theResult____h169448[28] && - !_theResult____h169448[27] && - !_theResult____h169448[26] && - !_theResult____h169448[25] && - !_theResult____h169448[24] && - !_theResult____h169448[23] && - !_theResult____h169448[22] && - !_theResult____h169448[21] && - !_theResult____h169448[20] && - !_theResult____h169448[19] && - !_theResult____h169448[18] && - !_theResult____h169448[17] && - !_theResult____h169448[16] && - !_theResult____h169448[15] && - !_theResult____h169448[14] && - !_theResult____h169448[13] && - !_theResult____h169448[12] && - !_theResult____h169448[11] && - !_theResult____h169448[10] && - !_theResult____h169448[9] && - !_theResult____h169448[8] && - !_theResult____h169448[7] && - !_theResult____h169448[6] && - !_theResult____h169448[5] && - !_theResult____h169448[4] && - !_theResult____h169448[3] && - !_theResult____h169448[2] && - !_theResult____h169448[1] && - !_theResult____h169448[0]) ? - _theResult____h169448 : - _theResult___snd__h177724 ; - assign _theResult___snd__h177724 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q151[54:0], - 2'd0 } ; - assign _theResult___snd__h177747 = - _theResult____h169448 << - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d4817 ; - assign _theResult___snd__h186461 = - (sV1_exp__h1212 == 8'd0) ? - _theResult___snd__h186475 : - _theResult___snd__h168064 ; - assign _theResult___snd__h186475 = - (sV1_exp__h1212 == 8'd0 && !sV1_sfd__h1213[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470) ? - b__h39635 : - _theResult___snd__h186481 ; - assign _theResult___snd__h186481 = - { IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q154[54:0], - 2'd0 } ; - assign _theResult___snd__h186499 = - b__h39635 << - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d4891 ; - assign _theResult___snd_fst_exp__h127793 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _theResult___fst_exp__h119178 : - _theResult___fst_exp__h127790 ; - assign _theResult___snd_fst_exp__h13300 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 ? - _theResult___fst_exp__h12741 : - _theResult___fst_exp__h13297 ; - assign _theResult___snd_fst_exp__h13303 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 ? - 8'd0 : - _theResult___snd_fst_exp__h13300 ; - assign _theResult___snd_fst_exp__h13306 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 ? - _theResult___snd_fst_exp__h13303 : - 8'd255 ; - assign _theResult___snd_fst_exp__h145700 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - _theResult___fst_exp__h137031 : - _theResult___fst_exp__h145697 ; - assign _theResult___snd_fst_exp__h168870 = - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 ? - 11'd0 : - _theResult___fst_exp__h168867 ; - assign _theResult___snd_fst_exp__h187299 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - _theResult___fst_exp__h178514 : - _theResult___fst_exp__h187296 ; - assign _theResult___snd_fst_exp__h23862 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926 ? - _theResult___fst_exp__h23304 : - _theResult___fst_exp__h23859 ; - assign _theResult___snd_fst_exp__h23865 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 ? - 8'd0 : - _theResult___snd_fst_exp__h23862 ; - assign _theResult___snd_fst_exp__h23868 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 ? - _theResult___snd_fst_exp__h23865 : - 8'd255 ; - assign _theResult___snd_fst_exp__h30236 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 ? - _theResult___fst_exp__h29677 : - _theResult___fst_exp__h30233 ; - assign _theResult___snd_fst_exp__h30239 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 ? - 8'd0 : - _theResult___snd_fst_exp__h30236 ; - assign _theResult___snd_fst_exp__h30242 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 ? - _theResult___snd_fst_exp__h30239 : - 8'd255 ; - assign _theResult___snd_fst_exp__h36350 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530 ? - _theResult___fst_exp__h35792 : - _theResult___fst_exp__h36347 ; - assign _theResult___snd_fst_exp__h36353 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529 ? - 8'd0 : - _theResult___snd_fst_exp__h36350 ; - assign _theResult___snd_fst_exp__h36356 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 ? - _theResult___snd_fst_exp__h36353 : - 8'd255 ; - assign _theResult___snd_fst_exp__h61289 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 ? - _theResult___fst_exp__h60527 : - _theResult___fst_exp__h61286 ; - assign _theResult___snd_fst_exp__h61292 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247 ? - 11'd0 : - _theResult___snd_fst_exp__h61289 ; - assign _theResult___snd_fst_exp__h61295 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 ? - _theResult___snd_fst_exp__h61292 : - 11'd2047 ; - assign _theResult___snd_fst_exp__h70928 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461 ? - _theResult___fst_exp__h70167 : - _theResult___fst_exp__h70925 ; - assign _theResult___snd_fst_exp__h70931 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460 ? - 11'd0 : - _theResult___snd_fst_exp__h70928 ; - assign _theResult___snd_fst_exp__h70934 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 ? - _theResult___snd_fst_exp__h70931 : - 11'd2047 ; - assign _theResult___snd_fst_exp__h84610 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 ? - _theResult___fst_exp__h83848 : - _theResult___fst_exp__h84607 ; - assign _theResult___snd_fst_exp__h84613 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 ? - 11'd0 : - _theResult___snd_fst_exp__h84610 ; - assign _theResult___snd_fst_exp__h84616 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 ? - _theResult___snd_fst_exp__h84613 : - 11'd2047 ; - assign _theResult___snd_fst_exp__h95565 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963 ? - _theResult___fst_exp__h94804 : - _theResult___fst_exp__h95562 ; - assign _theResult___snd_fst_exp__h95568 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 ? - 11'd0 : - _theResult___snd_fst_exp__h95565 ; - assign _theResult___snd_fst_exp__h95571 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 ? - _theResult___snd_fst_exp__h95568 : - 11'd2047 ; - assign _theResult___snd_fst_sfd__h102768 = - (value__h98653[51:29] == 23'd0) ? - 23'd2097152 : - value__h98653[51:29] ; - assign _theResult___snd_fst_sfd__h127794 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _theResult___fst_sfd__h119179 : - _theResult___fst_sfd__h127791 ; - assign _theResult___snd_fst_sfd__h13301 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 ? - _theResult___fst_sfd__h12742 : - _theResult___fst_sfd__h13298 ; - assign _theResult___snd_fst_sfd__h145701 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - _theResult___fst_sfd__h137032 : - _theResult___fst_sfd__h145698 ; - assign _theResult___snd_fst_sfd__h149185 = - (value__h147302 == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h147299 ; - assign _theResult___snd_fst_sfd__h168871 = - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 ? - 52'd0 : - _theResult___fst_sfd__h168868 ; - assign _theResult___snd_fst_sfd__h187300 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - _theResult___fst_sfd__h178515 : - _theResult___fst_sfd__h187297 ; - assign _theResult___snd_fst_sfd__h23863 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926 ? - _theResult___fst_sfd__h23305 : - _theResult___fst_sfd__h23860 ; - assign _theResult___snd_fst_sfd__h30237 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 ? - _theResult___fst_sfd__h29678 : - _theResult___fst_sfd__h30234 ; - assign _theResult___snd_fst_sfd__h36351 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530 ? - _theResult___fst_sfd__h35793 : - _theResult___fst_sfd__h36348 ; - assign _theResult___snd_fst_sfd__h61290 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 ? - _theResult___fst_sfd__h60528 : - _theResult___fst_sfd__h61287 ; - assign _theResult___snd_fst_sfd__h70929 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461 ? - _theResult___fst_sfd__h70168 : - _theResult___fst_sfd__h70926 ; - assign _theResult___snd_fst_sfd__h84611 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 ? - _theResult___fst_sfd__h83849 : - _theResult___fst_sfd__h84608 ; - assign _theResult___snd_fst_sfd__h95566 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963 ? - _theResult___fst_sfd__h94805 : - _theResult___fst_sfd__h95563 ; - assign b__h36962 = { value__h36964, 64'd0 } ; - assign b__h39635 = { value__h36964, 32'd0 } ; - assign b__h71539 = { value__h71541, 32'd0 } ; - assign b__h96173 = { value__h71541, 64'd0 } ; - assign din_inc___2_exp__h13340 = x__h12773[7:0] + 8'd1 ; - assign din_inc___2_exp__h145728 = _theResult___fst_exp__h118551 + 8'd1 ; - assign din_inc___2_exp__h145752 = _theResult___fst_exp__h127237 + 8'd1 ; - assign din_inc___2_exp__h145782 = _theResult___fst_exp__h136404 + 8'd1 ; - assign din_inc___2_exp__h145806 = _theResult___fst_exp__h145119 + 8'd1 ; - assign din_inc___2_exp__h187331 = _theResult___fst_exp__h168111 + 11'd1 ; - assign din_inc___2_exp__h187361 = _theResult___fst_exp__h177684 + 11'd1 ; - assign din_inc___2_exp__h187385 = _theResult___fst_exp__h186515 + 11'd1 ; - assign din_inc___2_exp__h23898 = x__h23336[7:0] + 8'd1 ; - assign din_inc___2_exp__h30276 = x__h29709[7:0] + 8'd1 ; - assign din_inc___2_exp__h36386 = x__h35824[7:0] + 8'd1 ; - assign din_inc___2_exp__h61329 = x__h60559[10:0] + 11'd1 ; - assign din_inc___2_exp__h70964 = x__h70199[10:0] + 11'd1 ; - assign din_inc___2_exp__h84650 = x__h83880[10:0] + 11'd1 ; - assign din_inc___2_exp__h95601 = x__h94836[10:0] + 11'd1 ; - assign guard__h110454 = - { IF_sfdin18545_BIT_33_THEN_2_ELSE_0__q115[1], - { sfdin__h118545[32:0], 23'd0 } != 56'd0 } ; - assign guard__h119189 = - { IF_theResult___snd27188_BIT_33_THEN_2_ELSE_0__q117[1], - { _theResult___snd__h127188[32:0], 23'd0 } != 56'd0 } ; - assign guard__h12228 = - { IF_sfd___32218_BIT_40_THEN_2_ELSE_0__q6[1], - { sfd___3__h12218[39:0], 23'd0 } != 63'd0 } ; - assign guard__h12758 = - { IF_sfd___32218_BIT_39_THEN_2_ELSE_0__q7[1], - { sfd___3__h12218[38:0], 24'd0 } != 63'd0 } ; - assign guard__h128178 = - { IF_sfdin36398_BIT_33_THEN_2_ELSE_0__q120[1], - { sfdin__h136398[32:0], 23'd0 } != 56'd0 } ; - assign guard__h128776 = x__h128876 != 57'd0 ; - assign guard__h137042 = - { IF_theResult___snd45065_BIT_33_THEN_2_ELSE_0__q123[1], - { _theResult___snd__h145065[32:0], 23'd0 } != 56'd0 } ; - assign guard__h160150 = - { IF_theResult___snd68062_BIT_4_THEN_2_ELSE_0__q149[1], - { _theResult___snd__h168062[3:0], 52'd0 } != 56'd0 } ; - assign guard__h169458 = - { IF_sfdin77678_BIT_4_THEN_2_ELSE_0__q152[1], - { sfdin__h177678[3:0], 52'd0 } != 56'd0 } ; - assign guard__h170056 = x__h170156 != 57'd0 ; - assign guard__h178525 = - { IF_theResult___snd86461_BIT_4_THEN_2_ELSE_0__q155[1], - { _theResult___snd__h186461[3:0], 52'd0 } != 56'd0 } ; - assign guard__h22795 = - { IF_sfd___32785_BIT_40_THEN_2_ELSE_0__q22[1], - { sfd___3__h22785[39:0], 23'd0 } != 63'd0 } ; - assign guard__h23321 = - { IF_sfd___32785_BIT_39_THEN_2_ELSE_0__q23[1], - { sfd___3__h22785[38:0], 24'd0 } != 63'd0 } ; - assign guard__h29167 = - { IF_sfd___39157_BIT_8_THEN_2_ELSE_0__q38[1], - { sfd___3__h29157[7:0], 23'd0 } != 31'd0 } ; - assign guard__h29694 = - { IF_sfd___39157_BIT_7_THEN_2_ELSE_0__q39[1], - { sfd___3__h29157[6:0], 24'd0 } != 31'd0 } ; - assign guard__h35283 = - { IF_sfd___35273_BIT_8_THEN_2_ELSE_0__q52[1], - { sfd___3__h35273[7:0], 23'd0 } != 31'd0 } ; - assign guard__h35809 = - { IF_sfd___35273_BIT_7_THEN_2_ELSE_0__q53[1], - { sfd___3__h35273[6:0], 24'd0 } != 31'd0 } ; - assign guard__h36895 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[23], - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[22:0], - 65'd0 } != - 88'd0 } ; - assign guard__h37673 = - { IF_x7862_BIT_24_THEN_2_ELSE_0__q63[1], - { x__h37862[23:0], 64'd0 } != 88'd0 } ; - assign guard__h38902 = - { IF_x9123_BIT_24_THEN_2_ELSE_0__q64[1], - { x__h39123[23:0], 64'd0 } != 88'd0 } ; - assign guard__h39568 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[23], - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[22:0], - 33'd0 } != - 56'd0 } ; - assign guard__h40122 = - { IF_x0311_BIT_24_THEN_2_ELSE_0__q65[1], - { x__h40311[23:0], 32'd0 } != 56'd0 } ; - assign guard__h41113 = - { IF_x1334_BIT_24_THEN_2_ELSE_0__q66[1], - { x__h41334[23:0], 32'd0 } != 56'd0 } ; - assign guard__h59814 = - { IF_sfd___39804_BIT_2_THEN_2_ELSE_0__q67[1], - { sfd___3__h59804[1:0], 52'd0 } != 54'd0 } ; - assign guard__h60544 = - { IF_sfd___39804_BIT_1_THEN_2_ELSE_0__q68[1], - { sfd___3__h59804[0], 53'd0 } != 54'd0 } ; - assign guard__h69455 = - { IF_sfd___39445_BIT_2_THEN_2_ELSE_0__q81[1], - { sfd___3__h69445[1:0], 52'd0 } != 54'd0 } ; - assign guard__h70184 = - { IF_sfd___39445_BIT_1_THEN_2_ELSE_0__q82[1], - { sfd___3__h69445[0], 53'd0 } != 54'd0 } ; - assign guard__h71472 = - { IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[52], - { IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[51:0], - 33'd0 } != - 85'd0 } ; - assign guard__h72026 = - { IF_x2215_BIT_53_THEN_2_ELSE_0__q92[1], - { x__h72215[52:0], 32'd0 } != 85'd0 } ; - assign guard__h73017 = - { IF_x3238_BIT_53_THEN_2_ELSE_0__q93[1], - { x__h73238[52:0], 32'd0 } != 85'd0 } ; - assign guard__h83135 = - { IF_sfd___32218_BIT_11_THEN_2_ELSE_0__q8[1], - { sfd___3__h12218[10:0], 52'd0 } != 63'd0 } ; - assign guard__h83865 = - { IF_sfd___32218_BIT_10_THEN_2_ELSE_0__q9[1], - { sfd___3__h12218[9:0], 53'd0 } != 63'd0 } ; - assign guard__h94092 = - { IF_sfd___32785_BIT_11_THEN_2_ELSE_0__q24[1], - { sfd___3__h22785[10:0], 52'd0 } != 63'd0 } ; - assign guard__h94821 = - { IF_sfd___32785_BIT_10_THEN_2_ELSE_0__q25[1], - { sfd___3__h22785[9:0], 53'd0 } != 63'd0 } ; - assign guard__h96106 = - { IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[52], - { IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[51:0], - 65'd0 } != - 117'd0 } ; - assign guard__h96884 = - { IF_x7073_BIT_53_THEN_2_ELSE_0__q112[1], - { x__h97073[52:0], 64'd0 } != 117'd0 } ; - assign guard__h98096 = - { IF_x8317_BIT_53_THEN_2_ELSE_0__q113[1], - { x__h98317[52:0], 64'd0 } != 117'd0 } ; - assign out1___1__h37613 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[88:24] + - 65'd1 ; - assign out1___1__h40062 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[56:24] + - 33'd1 ; - assign out1___1__h71966 = - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[85:53] + - 33'd1 ; - assign out1___1__h96824 = - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[117:53] + - 65'd1 ; - assign out___1_sfd__h147299 = { value__h147302, 29'd0 } ; - assign out_exp__h119080 = - sfdin__h118545[34] ? - _theResult___exp__h119077 : - _theResult___fst_exp__h118551 ; - assign out_exp__h12647 = - sfd___3__h12218[41] ? _theResult___exp__h12644 : 8'd0 ; - assign out_exp__h127692 = - _theResult___snd__h127188[34] ? - _theResult___exp__h127689 : - _theResult___fst_exp__h127237 ; - assign out_exp__h13200 = - sfd___3__h12218[40] ? _theResult___exp__h13197 : x__h12773[7:0] ; - assign out_exp__h136933 = - sfdin__h136398[34] ? - _theResult___exp__h136930 : - _theResult___fst_exp__h136404 ; - assign out_exp__h145599 = - _theResult___snd__h145065[34] ? - _theResult___exp__h145596 : - _theResult___fst_exp__h145119 ; - assign out_exp__h168769 = - _theResult___snd__h168062[5] ? - _theResult___exp__h168766 : - _theResult___fst_exp__h168111 ; - assign out_exp__h178416 = - sfdin__h177678[5] ? - _theResult___exp__h178413 : - _theResult___fst_exp__h177684 ; - assign out_exp__h187198 = - _theResult___snd__h186461[5] ? - _theResult___exp__h187195 : - _theResult___fst_exp__h186515 ; - assign out_exp__h23211 = - sfd___3__h22785[41] ? _theResult___exp__h23208 : 8'd0 ; - assign out_exp__h23763 = - sfd___3__h22785[40] ? _theResult___exp__h23760 : x__h23336[7:0] ; - assign out_exp__h29583 = - sfd___3__h29157[9] ? _theResult___exp__h29580 : 8'd0 ; - assign out_exp__h30136 = - sfd___3__h29157[8] ? _theResult___exp__h30133 : x__h29709[7:0] ; - assign out_exp__h35699 = - sfd___3__h35273[9] ? _theResult___exp__h35696 : 8'd0 ; - assign out_exp__h36251 = - sfd___3__h35273[8] ? _theResult___exp__h36248 : x__h35824[7:0] ; - assign out_exp__h60433 = - sfd___3__h59804[3] ? _theResult___exp__h60430 : 11'd0 ; - assign out_exp__h61189 = - sfd___3__h59804[2] ? _theResult___exp__h61186 : x__h60559[10:0] ; - assign out_exp__h70074 = - sfd___3__h69445[3] ? _theResult___exp__h70071 : 11'd0 ; - assign out_exp__h70829 = - sfd___3__h69445[2] ? _theResult___exp__h70826 : x__h70199[10:0] ; - assign out_exp__h83754 = - sfd___3__h12218[12] ? _theResult___exp__h83751 : 11'd0 ; - assign out_exp__h84510 = - sfd___3__h12218[11] ? - _theResult___exp__h84507 : - x__h83880[10:0] ; - assign out_exp__h94711 = - sfd___3__h22785[12] ? _theResult___exp__h94708 : 11'd0 ; - assign out_exp__h95466 = - sfd___3__h22785[11] ? - _theResult___exp__h95463 : - x__h94836[10:0] ; - assign out_sfd__h119081 = - sfdin__h118545[34] ? - _theResult___sfd__h119078 : - sfdin__h118545[56:34] ; - assign out_sfd__h12648 = - sfd___3__h12218[41] ? - _theResult___sfd__h12645 : - sfd___3__h12218[63:41] ; - assign out_sfd__h127693 = - _theResult___snd__h127188[34] ? - _theResult___sfd__h127690 : - _theResult___snd__h127188[56:34] ; - assign out_sfd__h13201 = - sfd___3__h12218[40] ? - _theResult___sfd__h13198 : - sfd___3__h12218[62:40] ; - assign out_sfd__h136934 = - sfdin__h136398[34] ? - _theResult___sfd__h136931 : - sfdin__h136398[56:34] ; - assign out_sfd__h145600 = - _theResult___snd__h145065[34] ? - _theResult___sfd__h145597 : - _theResult___snd__h145065[56:34] ; - assign out_sfd__h168770 = - _theResult___snd__h168062[5] ? - _theResult___sfd__h168767 : - _theResult___snd__h168062[56:5] ; - assign out_sfd__h178417 = - sfdin__h177678[5] ? - _theResult___sfd__h178414 : - sfdin__h177678[56:5] ; - assign out_sfd__h187199 = - _theResult___snd__h186461[5] ? - _theResult___sfd__h187196 : - _theResult___snd__h186461[56:5] ; - assign out_sfd__h23212 = - sfd___3__h22785[41] ? - _theResult___sfd__h23209 : - sfd___3__h22785[63:41] ; - assign out_sfd__h23764 = - sfd___3__h22785[40] ? - _theResult___sfd__h23761 : - sfd___3__h22785[62:40] ; - assign out_sfd__h29584 = - sfd___3__h29157[9] ? - _theResult___sfd__h29581 : - sfd___3__h29157[31:9] ; - assign out_sfd__h30137 = - sfd___3__h29157[8] ? - _theResult___sfd__h30134 : - sfd___3__h29157[30:8] ; - assign out_sfd__h35700 = - sfd___3__h35273[9] ? - _theResult___sfd__h35697 : - sfd___3__h35273[31:9] ; - assign out_sfd__h36252 = - sfd___3__h35273[8] ? - _theResult___sfd__h36249 : - sfd___3__h35273[30:8] ; - assign out_sfd__h60434 = - sfd___3__h59804[3] ? - _theResult___sfd__h60431 : - sfd___3__h59804[54:3] ; - assign out_sfd__h61190 = - sfd___3__h59804[2] ? - _theResult___sfd__h61187 : - sfd___3__h59804[53:2] ; - assign out_sfd__h70075 = - sfd___3__h69445[3] ? - _theResult___sfd__h70072 : - sfd___3__h69445[54:3] ; - assign out_sfd__h70830 = - sfd___3__h69445[2] ? - _theResult___sfd__h70827 : - sfd___3__h69445[53:2] ; - assign out_sfd__h83755 = - sfd___3__h12218[12] ? - _theResult___sfd__h83752 : - sfd___3__h12218[63:12] ; - assign out_sfd__h84511 = - sfd___3__h12218[11] ? - _theResult___sfd__h84508 : - sfd___3__h12218[62:11] ; - assign out_sfd__h94712 = - sfd___3__h22785[12] ? - _theResult___sfd__h94709 : - sfd___3__h22785[63:12] ; - assign out_sfd__h95467 = - sfd___3__h22785[11] ? - _theResult___sfd__h95464 : - sfd___3__h22785[62:11] ; - assign requestR_3_BITS_126_TO_116_167_EQ_0_181_AND_re_ETC___d5188 = - requestR[126:116] == 11'd0 && requestR[115:64] == 52'd0 && - requestR[127] && - requestR[190:180] == 11'd0 && - requestR[179:128] == 52'd0 && - !requestR[191] ; - assign requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 = - { requestR[127:96] == 32'hFFFFFFFF && requestR[95], - (requestR[127:96] == 32'hFFFFFFFF) ? - requestR[94:64] : - 31'h7FC00000 } ; - assign requestR_3_BITS_179_TO_128_610_ULE_requestR_3__ETC___d5200 = - requestR[179:128] <= requestR[115:64] ; - assign requestR_3_BITS_179_TO_128_610_ULT_requestR_3__ETC___d5205 = - requestR[179:128] < requestR[115:64] ; - assign requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5184 = - requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 && - requestR[191] && - requestR[126:116] == 11'd0 && - requestR[115:64] == 52'd0 && - !requestR[127] ; - assign requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5256 = - requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 && - requestR[126:116] == 11'd0 && - requestR[115:64] == 52'd0 || - (!requestR[191] || requestR[127]) && - (requestR[191] || !requestR[127]) && - (requestR[191] ? - requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5251 : - NOT_requestR_3_BITS_190_TO_180_608_ULT_request_ETC___d5252) ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2757 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2720 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2739 && - x__h73238[85:54] == 32'hFFFFFFFF) ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2768 = - { requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2757, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2762 } == - 5'd0 || - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2757 ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3234 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3198 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3217 && - x__h98317[117:54] == 64'hFFFFFFFFFFFFFFFF) ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3245 = - { requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3234, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3239 } == - 5'd0 || - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3234 ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5176 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115] ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5221 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179] || - requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0 && - !requestR[115] ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5241 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5221 || - requestR[190:180] == 11'd2047 && requestR[179] || - requestR[126:116] == 11'd2047 && requestR[115] ; - assign requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 = - requestR[190:180] == requestR[126:116] ; - assign requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620 = - requestR[190:180] - 11'd1023 ; - assign requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5197 = - requestR[190:180] <= requestR[126:116] ; - assign requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5251 = - requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5197 && - (!requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 || - requestR_3_BITS_179_TO_128_610_ULE_requestR_3__ETC___d5200) && - !requestR_3_BITS_190_TO_180_608_ULT_requestR_3__ETC___d5204 && - (!requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 || - !requestR_3_BITS_179_TO_128_610_ULT_requestR_3__ETC___d5205) ; - assign requestR_3_BITS_190_TO_180_608_ULT_requestR_3__ETC___d5204 = - requestR[190:180] < requestR[126:116] ; - assign requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NOT_r_ETC___d856 = - requestR[191:128] == 64'd0 || - !requestR[191] && !requestR[190] && !requestR[189] && - !requestR[188] && - !requestR[187] && - !requestR[186] && - !requestR[185] && - !requestR[184] && - !requestR[183] && - !requestR[182] && - !requestR[181] && - !requestR[180] && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 ; - assign requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d2043 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159] && - (requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) || - (requestR[191:160] == 32'hFFFFFFFF && requestR[159] || - requestR[127:96] != 32'hFFFFFFFF || - !requestR[95]) && - IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2041 ; - assign requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077 = - requestR[158] || requestR[157] || requestR[156] || - requestR[155] || - requestR[154] || - requestR[153] || - requestR[152] || - requestR[151] || - requestR[150] || - requestR[149] || - requestR[148] || - requestR[147] || - requestR[146] || - requestR[145] || - requestR[144] || - requestR[143] || - requestR[142] || - requestR[141] || - requestR[140] || - requestR[139] || - requestR[138] || - requestR[137] || - requestR[136] || - requestR[135] || - requestR[134] || - requestR[133] || - requestR[132] || - requestR[131] || - requestR[130] || - requestR[129] || - requestR[128] ; - assign requestR_3_BIT_159_6_OR_requestR_3_BIT_158_31__ETC___d1671 = - (requestR[159] || - requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077) && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529 && - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1668 ; - assign requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098 = - requestR[179] || requestR[178] || requestR[177] || - requestR[176] || - requestR[175] || - requestR[174] || - requestR[173] || - requestR[172] || - requestR[171] || - requestR[170] || - requestR[169] || - requestR[168] || - requestR[167] || - requestR[166] || - requestR[165] || - requestR[164] || - requestR[163] || - requestR[162] || - requestR[161] || - requestR[160] || - requestR[159] || - requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077 ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1119 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - (!_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 || - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 && - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926 && - _theResult___fst_exp__h23859 == 8'd255 && - _theResult___fst_sfd__h23860 == 23'd0) ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1122 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1131 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 && - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 && - IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d1128 ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3091 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - (!_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 || - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 && - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963 && - _theResult___fst_exp__h95562 == 11'd2047 && - _theResult___fst_sfd__h95563 == 52'd0) ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3094 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3103 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 && - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 && - IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d3100 ; - assign requestR_BITS_159_TO_128__q1 = requestR[159:128] ; - assign res___1__h204227 = - (requestR[190:180] == 11'd2047 && requestR[179]) ? - 64'd512 : - 64'd256 ; - assign res___1__h204665 = requestR[191] ? 64'd1 : 64'd128 ; - assign res___1__h204675 = requestR[191] ? 64'd8 : 64'd16 ; - assign res___1__h204694 = requestR[191] ? 64'd4 : 64'd32 ; - assign res___1__h50292 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22]) ? - 64'd512 : - 64'd256 ; - assign res___1__h50528 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd1 : - 64'd128 ; - assign res___1__h50538 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd8 : - 64'd16 ; - assign res___1__h50557 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd4 : - 64'd32 ; - assign res__h146185 = { 32'hFFFFFFFF, x__h146191 } ; - assign res__h187935 = - { IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5073, - x__h147243, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5037 } ; - assign res__h192322 = - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5212 ? - requestR[191:128] : - requestR[127:64] ; - assign res__h196815 = - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5212 ? - requestR[127:64] : - requestR[191:128] ; - assign res__h199464 = - ((requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5256) ? - 64'd1 : - 64'd0 ; - assign res__h202104 = - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5212 ? - 64'd1 : - 64'd0 ; - assign res__h203926 = - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5273 ? - 64'd1 : - 64'd0 ; - assign res__h204710 = requestR[191] ? 64'd2 : 64'd64 ; - assign res__h204864 = { 32'hFFFFFFFF, fpu$server_core_response_get[36:5] } ; - assign res__h42283 = - { 32'hFFFFFFFF, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 } ; - assign res__h42520 = - { 32'hFFFFFFFF, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign res__h47670 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2104 ? - 64'd1 : - 64'd0 ; - assign res__h49098 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2045 ? - 64'd1 : - 64'd0 ; - assign res__h50112 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2120 ? - 64'd1 : - 64'd0 ; - assign res__h50573 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd2 : - 64'd64 ; - assign result__h128781 = - { _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_608__ETC___d3744[56:1], - _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_608__ETC___d3744[0] | - guard__h128776 } ; - assign result__h170061 = - { _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d4575[56:1], - _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d4575[0] | - guard__h170056 } ; - assign sV1_exp__h1212 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[158:151] : - 8'd255 ; - assign sV1_sfd__h1213 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[150:128] : - 23'd4194304 ; - assign sV2_exp__h1315 = - (requestR[127:96] == 32'hFFFFFFFF) ? requestR[94:87] : 8'd255 ; - assign sV2_sfd__h1316 = - (requestR[127:96] == 32'hFFFFFFFF) ? - requestR[86:64] : - 23'd4194304 ; - assign sfd___3__h12218 = - sfd__h2613 << - IF_IF_requestR_3_BIT_191_47_THEN_NEG_requestR__ETC___d404 ; - assign sfd___3__h22785 = - requestR[191:128] << - IF_requestR_3_BIT_191_47_THEN_0_ELSE_IF_reques_ETC___d920 ; - assign sfd___3__h29157 = - sfd__h24253 << - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1270 ; - assign sfd___3__h35273 = - requestR[159:128] << - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1524 ; - assign sfd___3__h59804 = - sfd__h51803 << - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d2241 ; - assign sfd___3__h69445 = - sfd__h61693 << - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d2455 ; - assign sfd__h102814 = { value__h71541, 3'd0 } ; - assign sfd__h118643 = - { 1'b0, - _theResult___fst_exp__h118551 != 8'd0, - sfdin__h118545[56:34] } + - 25'd1 ; - assign sfd__h12245 = { 2'd0, sfd___3__h12218[63:41] } + 25'd1 ; - assign sfd__h127255 = - { 1'b0, - _theResult___fst_exp__h127237 != 8'd0, - _theResult___snd__h127188[56:34] } + - 25'd1 ; - assign sfd__h12788 = - { 1'b0, x__h12773[7:0] != 8'd0, sfd___3__h12218[62:40] } + - 25'd1 ; - assign sfd__h136496 = - { 1'b0, - _theResult___fst_exp__h136404 != 8'd0, - sfdin__h136398[56:34] } + - 25'd1 ; - assign sfd__h145138 = - { 1'b0, - _theResult___fst_exp__h145119 != 8'd0, - _theResult___snd__h145065[56:34] } + - 25'd1 ; - assign sfd__h168129 = - { 1'b0, - _theResult___fst_exp__h168111 != 11'd0, - _theResult___snd__h168062[56:5] } + - 54'd1 ; - assign sfd__h177776 = - { 1'b0, - _theResult___fst_exp__h177684 != 11'd0, - sfdin__h177678[56:5] } + - 54'd1 ; - assign sfd__h186534 = - { 1'b0, - _theResult___fst_exp__h186515 != 11'd0, - _theResult___snd__h186461[56:5] } + - 54'd1 ; - assign sfd__h22812 = { 2'd0, sfd___3__h22785[63:41] } + 25'd1 ; - assign sfd__h23351 = - { 1'b0, x__h23336[7:0] != 8'd0, sfd___3__h22785[62:40] } + - 25'd1 ; - assign sfd__h24253 = - requestR[159] ? -requestR[159:128] : requestR[159:128] ; - assign sfd__h2613 = requestR[191] ? -requestR[191:128] : requestR[191:128] ; - assign sfd__h29184 = { 2'd0, sfd___3__h29157[31:9] } + 25'd1 ; - assign sfd__h29724 = - { 1'b0, x__h29709[7:0] != 8'd0, sfd___3__h29157[30:8] } + 25'd1 ; - assign sfd__h35300 = { 2'd0, sfd___3__h35273[31:9] } + 25'd1 ; - assign sfd__h35839 = - { 1'b0, x__h35824[7:0] != 8'd0, sfd___3__h35273[30:8] } + 25'd1 ; - assign sfd__h51803 = { sfd__h24253, 23'd0 } ; - assign sfd__h59831 = { 2'd0, sfd___3__h59804[54:3] } + 54'd1 ; - assign sfd__h60574 = - { 1'b0, x__h60559[10:0] != 11'd0, sfd___3__h59804[53:2] } + - 54'd1 ; - assign sfd__h61693 = { requestR[159:128], 23'd0 } ; - assign sfd__h69472 = { 2'd0, sfd___3__h69445[54:3] } + 54'd1 ; - assign sfd__h70214 = - { 1'b0, x__h70199[10:0] != 11'd0, sfd___3__h69445[53:2] } + - 54'd1 ; - assign sfd__h83152 = { 2'd0, sfd___3__h12218[63:12] } + 54'd1 ; - assign sfd__h83895 = - { 1'b0, x__h83880[10:0] != 11'd0, sfd___3__h12218[62:11] } + - 54'd1 ; - assign sfd__h94109 = { 2'd0, sfd___3__h22785[63:12] } + 54'd1 ; - assign sfd__h94851 = - { 1'b0, x__h94836[10:0] != 11'd0, sfd___3__h22785[62:11] } + - 54'd1 ; - assign sfdin__h118545 = - _theResult____h110444[56] ? - _theResult___snd__h118562 : - _theResult___snd__h118573 ; - assign sfdin__h136398 = - _theResult____h128168[56] ? - _theResult___snd__h136415 : - _theResult___snd__h136426 ; - assign sfdin__h177678 = - _theResult____h169448[56] ? - _theResult___snd__h177695 : - _theResult___snd__h177706 ; - assign value__h147302 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22]) ? - _theResult___fst_sfd__h147557 : - sV1_sfd__h1213 ; - assign value__h36964 = { 1'b0, sV1_exp__h1212 != 8'd0, sV1_sfd__h1213 } ; - assign value__h71541 = - { 1'b0, requestR[190:180] != 11'd0, requestR[179:128] } ; - assign value__h98653 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179]) ? - _theResult___fst_sfd__h99110 : - requestR[179:128] ; - assign x__h12773 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407 + - 9'd127 ; - assign x__h128876 = sfd__h102814 << x__h128909 ; - assign x__h128909 = - 12'd57 - - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_608_ETC___d3740 ; - assign x__h13466 = - { 2'd0, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d647, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d650, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d659 } ; - assign x__h13699 = - { 33'h1FFFFFFFE, - requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NOT_r_ETC___d856 ? - 8'd0 : - _theResult___snd_fst_exp__h23868, - (requestR[191:128] == 64'd0 || - NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d1013) ? - 23'd0 : - _theResult___snd_fst_sfd__h23863 } ; - assign x__h146191 = - { (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - (requestR[190:180] == 11'd2047 || - requestR[190:180] == 11'd0) && - requestR[179:128] == 52'd0) ? - requestR[191] : - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4264, - x__h98593, - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d4224 } ; - assign x__h146306 = - { (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179] : - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4315, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4326, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4342, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4355, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4368 } ; - assign x__h147233 = - (x__h147243 == 11'd2047 && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5037[51]) ? - 64'h7FF8000000000000 : - res__h187935 ; - assign x__h147243 = - (sV1_exp__h1212 == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h187308 ; - assign x__h170156 = b__h39635 << x__h170189 ; - assign x__h170189 = - 12'd57 - - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d4571 ; - assign x__h188037 = - { IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5111, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5118, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5132, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5144, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5156 } ; - assign x__h188904 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5176 ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115]) ? - requestR[191:128] : - ((requestR[190:180] == 11'd2047 && requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115]) ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && requestR[179]) ? - requestR[127:64] : - IF_requestR_3_BITS_126_TO_116_167_EQ_2047_168__ETC___d5215)))) ; - assign x__h192454 = - { requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5221, - 4'd0 } ; - assign x__h193397 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5176 ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115]) ? - requestR[191:128] : - ((requestR[190:180] == 11'd2047 && requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115]) ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && requestR[115]) ? - requestR[191:128] : - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5228))))) ; - assign x__h197786 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5241 ? - 64'd0 : - res__h199464 ; - assign x__h200426 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5241 ? - 64'd0 : - res__h202104 ; - assign x__h202123 = - { requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0, - 4'd0 } ; - assign x__h202248 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5241 ? - 64'd0 : - res__h203926 ; - assign x__h204207 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - res___1__h204227 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - res___1__h204665 : - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5294) ; - assign x__h204831 = - fpu$server_core_response_get[69] ? - res__h204864 : - fpu$server_core_response_get[68:5] ; - assign x__h23336 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923 + - 9'd127 ; - assign x__h2341 = { 32'hFFFFFFFF, x__h2348 } ; - assign x__h2348 = - { requestR[127:96] == 32'hFFFFFFFF && requestR[95], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h24002 = - { 2'd0, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1119, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1122, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1131 } ; - assign x__h2422 = { 32'hFFFFFFFF, x__h2429 } ; - assign x__h24232 = { 32'hFFFFFFFF, x__h24238 } ; - assign x__h24238 = - { requestR[159:128] != 32'd0 && - (NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d1278 ? - requestR[159] : - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1331), - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1391, - (requestR[159:128] == 32'd0 || - NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d1278) ? - 23'd0 : - _theResult___snd_fst_sfd__h30237 } ; - assign x__h2429 = - { requestR[127:96] != 32'hFFFFFFFF || !requestR[95], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h2500 = { 32'hFFFFFFFF, x__h2507 } ; - assign x__h2507 = - { (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) != - (requestR[127:96] == 32'hFFFFFFFF && requestR[95]), - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h2592 = { 32'hFFFFFFFF, x__h2598 } ; - assign x__h2598 = - { requestR[191:128] != 64'd0 && - (NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d412 ? - requestR[191] : - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d474), - IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d534, - (requestR[191:128] == 64'd0 || - NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d412) ? - 23'd0 : - _theResult___snd_fst_sfd__h13301 } ; - assign x__h29709 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273 + - 9'd127 ; - assign x__h30402 = - { 2'd0, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1472, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1475, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1484 } ; - assign x__h30632 = - { 33'h1FFFFFFFE, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1613, - (requestR[159:128] == 32'd0 || - !requestR[159] && - NOT_requestR_3_BIT_158_31_32_AND_NOT_requestR__ETC___d822 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 || - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529) ? - 23'd0 : - _theResult___snd_fst_sfd__h36351 } ; - assign x__h35824 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527 + - 9'd127 ; - assign x__h36490 = - { 2'd0, - NOT_requestR_3_BITS_159_TO_128_139_EQ_0_140_14_ETC___d1660, - requestR[159:128] != 32'd0 && - (requestR[159] || - requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077) && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529, - requestR[159:128] != 32'd0 && - requestR_3_BIT_159_6_OR_requestR_3_BIT_158_31__ETC___d1671 } ; - assign x__h36719 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692 ? - 64'h7FFFFFFFFFFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1764 ; - assign x__h37862 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705 >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731 | - ~(89'h1FFFFFFFFFFFFFFFFFFFFFF >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731) & - {89{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[88]}} ; - assign x__h38500 = - { sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0 || - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1774, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1785 } ; - assign x__h38702 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692 ? - 64'hFFFFFFFFFFFFFFFF : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1824 ; - assign x__h39123 = - { sV1_exp__h1212 != 8'd0, sV1_sfd__h1213, 65'd0 } >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793 ; - assign x__h39201 = - { (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1842 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1831, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1836 } ; - assign x__h39389 = { {32{x__h39392[31]}}, x__h39392 } ; - assign x__h39392 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692 ? - 32'h7FFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1911 ; - assign x__h40311 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852 >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878 | - ~(57'h1FFFFFFFFFFFFFF >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878) & - {57{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[56]}} ; - assign x__h40708 = - { sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0 || - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1919, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1927 } ; - assign x__h40910 = { {32{x__h40913[31]}}, x__h40913 } ; - assign x__h40913 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692 ? - 32'hFFFFFFFF : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1966 ; - assign x__h41334 = - { sV1_exp__h1212 != 8'd0, sV1_sfd__h1213, 33'd0 } >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935 ; - assign x__h41412 = - { (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1985 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1974, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1979 } ; - assign x__h41604 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2007 ? - 64'hFFFFFFFF7FC00000 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2053 ; - assign x__h43644 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2055, - 4'd0 } ; - assign x__h44183 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2007 ? - 64'hFFFFFFFF7FC00000 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2068 ; - assign x__h46653 = { 32'hFFFFFFFF, requestR[159:128] } ; - assign x__h46718 = - { {32{requestR_BITS_159_TO_128__q1[31]}}, - requestR_BITS_159_TO_128__q1 } ; - assign x__h46800 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2088 ? - 64'd0 : - res__h47670 ; - assign x__h48228 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2088 ? - 64'd0 : - res__h49098 ; - assign x__h49117 = - { sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316 != 23'd0, - 4'd0 } ; - assign x__h49242 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2088 ? - 64'd0 : - res__h50112 ; - assign x__h50272 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0) ? - res___1__h50292 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2133 ; - assign x__h51579 = { requestR[127], requestR[190:128] } ; - assign x__h51645 = { !requestR[127], requestR[190:128] } ; - assign x__h51713 = { requestR[191] != requestR[127], requestR[190:128] } ; - assign x__h51788 = - { requestR[159:128] != 32'd0 && - IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d2301, - (requestR[159:128] == 32'd0) ? - 11'd0 : - _theResult___snd_fst_exp__h61295, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2398 } ; - assign x__h60559 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244 + - 12'd1023 ; - assign x__h61451 = - { 2'd0, - requestR[159:128] != 32'd0 && - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 && - _theResult___fst_exp__h61286 == 11'd2047 && - _theResult___fst_sfd__h61287 == 52'd0), - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247, - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247 && - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2415 } ; - assign x__h61681 = - { 1'd0, - (requestR[159:128] == 32'd0) ? - 11'd0 : - _theResult___snd_fst_exp__h70934, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2580 } ; - assign x__h70199 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458 + - 12'd1023 ; - assign x__h71064 = - { 2'd0, - requestR[159:128] != 32'd0 && - (!_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461 && - _theResult___fst_exp__h70925 == 11'd2047 && - _theResult___fst_sfd__h70926 == 52'd0), - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460, - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460 && - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d2597 } ; - assign x__h71293 = { {32{x__h71296[31]}}, x__h71296 } ; - assign x__h71296 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'h7FFFFFFF : - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d2688 ; - assign x__h72215 = - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629 >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655 | - ~(86'h3FFFFFFFFFFFFFFFFFFFFF >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655) & - {86{IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[85]}} ; - assign x__h72612 = - { requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2699, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2710 } ; - assign x__h72814 = { {32{x__h72817[31]}}, x__h72817 } ; - assign x__h72817 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'hFFFFFFFF : - (requestR[191] ? - 32'd0 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'hFFFFFFFF : - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d2747)) ; - assign x__h73238 = - { requestR[190:180] != 11'd0, requestR[179:128], 33'd0 } >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718 ; - assign x__h73316 = - { requestR[191] ? - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2768 : - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2757, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2762 } ; - assign x__h73505 = - { requestR[191:128] != 64'd0 && - (NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d2781 ? - requestR[191] : - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2831), - IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d2890, - (requestR[191:128] == 64'd0 || - NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d2781) ? - 52'd0 : - _theResult___snd_fst_sfd__h84611 } ; - assign x__h83880 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776 + - 12'd1023 ; - assign x__h84772 = - { 2'd0, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2939, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2942, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2951 } ; - assign x__h85002 = - { 1'd0, - requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NOT_r_ETC___d856 ? - 11'd0 : - _theResult___snd_fst_exp__h95571, - (requestR[191:128] == 64'd0 || - NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d3048) ? - 52'd0 : - _theResult___snd_fst_sfd__h95566 } ; - assign x__h94836 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960 + - 12'd1023 ; - assign x__h95701 = - { 2'd0, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3091, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3094, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3103 } ; - assign x__h95930 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 64'h7FFFFFFFFFFFFFFF : - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d3173 ; - assign x__h97073 = - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114 >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140 | - ~(118'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFF >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140) & - {118{IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[117]}} ; - assign x__h97694 = - { requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3180, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3188 } ; - assign x__h97896 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 64'hFFFFFFFFFFFFFFFF : - (requestR[191] ? - 64'd0 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 64'hFFFFFFFFFFFFFFFF : - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d3225)) ; - assign x__h98317 = - { requestR[190:180] != 11'd0, requestR[179:128], 65'd0 } >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196 ; - assign x__h98395 = - { requestR[191] ? - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3245 : - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3234, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3239 } ; - assign x__h98583 = - (x__h98593 == 8'd255 && - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d4224[22]) ? - 64'hFFFFFFFF7FC00000 : - res__h146185 ; - assign x__h98593 = - (requestR[190:180] == 11'd2047) ? - 8'd255 : - _theResult___fst_exp__h145709 ; - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd254; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = - requestR[191] ? 8'd255 : 8'd254; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = - requestR[191] ? 8'd254 : 8'd255; - default: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - 23'd8388607; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - requestR[191] ? 23'd0 : 23'd8388607; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - requestR[191] ? 23'd8388607 : 23'd0; - default: CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = 23'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd2046; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 11'd2047 : - 11'd2046; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 11'd2046 : - 11'd2047; - default: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - 52'hFFFFFFFFFFFFF; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 52'hFFFFFFFFFFFFF : - 52'd0; - default: CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = 52'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h0: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = - requestR[194:192]; - 3'h1: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd4; - 3'h2: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd3; - 3'h3: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd2; - 3'h4: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd1; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = - 3'd0; - endcase - end - always@(guard__h12228 or requestR) - begin - case (guard__h12228) - 2'b0, 2'b01, 2'b10: - CASE_guard2228_0b0_requestR_BIT_191_0b1_reques_ETC__q10 = - requestR[191]; - 2'd3: - CASE_guard2228_0b0_requestR_BIT_191_0b1_reques_ETC__q10 = - guard__h12228 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h12228) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - (guard__h12228 == 2'b0) ? - requestR[191] : - (guard__h12228 == 2'b01 || guard__h12228 == 2'b10 || - guard__h12228 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h12758 or requestR) - begin - case (guard__h12758) - 2'b0, 2'b01, 2'b10: - CASE_guard2758_0b0_requestR_BIT_191_0b1_reques_ETC__q12 = - requestR[191]; - 2'd3: - CASE_guard2758_0b0_requestR_BIT_191_0b1_reques_ETC__q12 = - guard__h12758 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h12758) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q13 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q13 = - (guard__h12758 == 2'b0) ? - requestR[191] : - (guard__h12758 == 2'b01 || guard__h12758 == 2'b10 || - guard__h12758 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q13 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h12228 or _theResult___exp__h12644) - begin - case (guard__h12228) - 2'b0: CASE_guard2228_0b0_0_0b1_theResult___exp2644_0_ETC__q14 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard2228_0b0_0_0b1_theResult___exp2644_0_ETC__q14 = - _theResult___exp__h12644; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d496 or - guard__h12228 or - _theResult___exp__h12644 or - CASE_guard2228_0b0_0_0b1_theResult___exp2644_0_ETC__q14) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d496; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499 = - (guard__h12228 == 2'b0 || requestR[191]) ? - 8'd0 : - _theResult___exp__h12644; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499 = - CASE_guard2228_0b0_0_0b1_theResult___exp2644_0_ETC__q14; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499 = - 8'd0; - endcase - end - always@(guard__h12228 or out_exp__h12647 or _theResult___exp__h12644) - begin - case (guard__h12228) - 2'b0, 2'b01: - CASE_guard2228_0b0_0_0b1_0_0b10_out_exp2647_0b_ETC__q15 = 8'd0; - 2'b10: - CASE_guard2228_0b0_0_0b1_0_0b10_out_exp2647_0b_ETC__q15 = - out_exp__h12647; - 2'b11: - CASE_guard2228_0b0_0_0b1_0_0b10_out_exp2647_0b_ETC__q15 = - _theResult___exp__h12644; - endcase - end - always@(guard__h12758 or x__h12773 or _theResult___exp__h13197) - begin - case (guard__h12758) - 2'b0: - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_theRe_ETC__q16 = - x__h12773[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_theRe_ETC__q16 = - _theResult___exp__h13197; - endcase - end - always@(requestR or - x__h12773 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d524 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d522 or - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_theRe_ETC__q16) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 = - x__h12773[7:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d524; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d522; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 = - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_theRe_ETC__q16; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 = - 8'd0; - endcase - end - always@(guard__h12758 or - x__h12773 or out_exp__h13200 or _theResult___exp__h13197) - begin - case (guard__h12758) - 2'b0, 2'b01: - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_x2773_ETC__q17 = - x__h12773[7:0]; - 2'b10: - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_x2773_ETC__q17 = - out_exp__h13200; - 2'b11: - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_x2773_ETC__q17 = - _theResult___exp__h13197; - endcase - end - always@(guard__h12228 or sfd___3__h12218 or _theResult___sfd__h12645) - begin - case (guard__h12228) - 2'b0: - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q18 = - sfd___3__h12218[63:41]; - 2'b01, 2'b10, 2'b11: - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q18 = - _theResult___sfd__h12645; - endcase - end - always@(requestR or - sfd___3__h12218 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d547 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d545 or - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q18) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 = - sfd___3__h12218[63:41]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d547; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d545; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 = - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q18; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 = - 23'd0; - endcase - end - always@(guard__h12228 or - sfd___3__h12218 or out_sfd__h12648 or _theResult___sfd__h12645) - begin - case (guard__h12228) - 2'b0, 2'b01: - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q19 = - sfd___3__h12218[63:41]; - 2'b10: - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q19 = - out_sfd__h12648; - 2'b11: - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q19 = - _theResult___sfd__h12645; - endcase - end - always@(guard__h12758 or sfd___3__h12218 or _theResult___sfd__h13198) - begin - case (guard__h12758) - 2'b0: - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q20 = - sfd___3__h12218[62:40]; - 2'b01, 2'b10, 2'b11: - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q20 = - _theResult___sfd__h13198; - endcase - end - always@(requestR or - sfd___3__h12218 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d565 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d563 or - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q20) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 = - sfd___3__h12218[62:40]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d565; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d563; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 = - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q20; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 = - 23'd0; - endcase - end - always@(guard__h12758 or - sfd___3__h12218 or out_sfd__h13201 or _theResult___sfd__h13198) - begin - case (guard__h12758) - 2'b0, 2'b01: - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q21 = - sfd___3__h12218[62:40]; - 2'b10: - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q21 = - out_sfd__h13201; - 2'b11: - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q21 = - _theResult___sfd__h13198; - endcase - end - always@(guard__h22795 or out_exp__h23211 or _theResult___exp__h23208) - begin - case (guard__h22795) - 2'b0, 2'b01: - CASE_guard2795_0b0_0_0b1_0_0b10_out_exp3211_0b_ETC__q26 = 8'd0; - 2'b10: - CASE_guard2795_0b0_0_0b1_0_0b10_out_exp3211_0b_ETC__q26 = - out_exp__h23211; - 2'b11: - CASE_guard2795_0b0_0_0b1_0_0b10_out_exp3211_0b_ETC__q26 = - _theResult___exp__h23208; - endcase - end - always@(guard__h22795 or _theResult___exp__h23208) - begin - case (guard__h22795) - 2'b0: CASE_guard2795_0b0_0_0b1_theResult___exp3208_0_ETC__q27 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard2795_0b0_0_0b1_theResult___exp3208_0_ETC__q27 = - _theResult___exp__h23208; - endcase - end - always@(requestR or - guard__h22795 or - _theResult___exp__h23208 or - CASE_guard2795_0b0_0_0b1_theResult___exp3208_0_ETC__q27) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard2795_ETC__q28 = - (guard__h22795 == 2'b0) ? 8'd0 : _theResult___exp__h23208; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard2795_ETC__q28 = - CASE_guard2795_0b0_0_0b1_theResult___exp3208_0_ETC__q27; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard2795_ETC__q28 = 8'd0; - endcase - end - always@(guard__h94092 or out_exp__h94711 or _theResult___exp__h94708) - begin - case (guard__h94092) - 2'b0, 2'b01: - CASE_guard4092_0b0_0_0b1_0_0b10_out_exp4711_0b_ETC__q29 = 11'd0; - 2'b10: - CASE_guard4092_0b0_0_0b1_0_0b10_out_exp4711_0b_ETC__q29 = - out_exp__h94711; - 2'b11: - CASE_guard4092_0b0_0_0b1_0_0b10_out_exp4711_0b_ETC__q29 = - _theResult___exp__h94708; - endcase - end - always@(guard__h94092 or _theResult___exp__h94708) - begin - case (guard__h94092) - 2'b0: CASE_guard4092_0b0_0_0b1_theResult___exp4708_0_ETC__q30 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard4092_0b0_0_0b1_theResult___exp4708_0_ETC__q30 = - _theResult___exp__h94708; - endcase - end - always@(requestR or - guard__h94092 or - _theResult___exp__h94708 or - CASE_guard4092_0b0_0_0b1_theResult___exp4708_0_ETC__q30) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard4092_ETC__q31 = - (guard__h94092 == 2'b0) ? 11'd0 : _theResult___exp__h94708; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard4092_ETC__q31 = - CASE_guard4092_0b0_0_0b1_theResult___exp4708_0_ETC__q30; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard4092_ETC__q31 = - 11'd0; - endcase - end - always@(guard__h23321 or x__h23336 or _theResult___exp__h23760) - begin - case (guard__h23321) - 2'b0: - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_theRe_ETC__q32 = - x__h23336[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_theRe_ETC__q32 = - _theResult___exp__h23760; - endcase - end - always@(requestR or - x__h23336 or - guard__h23321 or - _theResult___exp__h23760 or - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_theRe_ETC__q32) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004 = - x__h23336[7:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004 = - (guard__h23321 == 2'b0) ? - x__h23336[7:0] : - _theResult___exp__h23760; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004 = - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_theRe_ETC__q32; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004 = - 8'd0; - endcase - end - always@(guard__h23321 or - x__h23336 or out_exp__h23763 or _theResult___exp__h23760) - begin - case (guard__h23321) - 2'b0, 2'b01: - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_x3336_ETC__q33 = - x__h23336[7:0]; - 2'b10: - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_x3336_ETC__q33 = - out_exp__h23763; - 2'b11: - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_x3336_ETC__q33 = - _theResult___exp__h23760; - endcase - end - always@(guard__h23321 or sfd___3__h22785 or _theResult___sfd__h23761) - begin - case (guard__h23321) - 2'b0: - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q34 = - sfd___3__h22785[62:40]; - 2'b01, 2'b10, 2'b11: - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q34 = - _theResult___sfd__h23761; - endcase - end - always@(requestR or - sfd___3__h22785 or - guard__h23321 or - _theResult___sfd__h23761 or - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q34) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042 = - sfd___3__h22785[62:40]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042 = - (guard__h23321 == 2'b0) ? - sfd___3__h22785[62:40] : - _theResult___sfd__h23761; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042 = - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q34; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042 = - 23'd0; - endcase - end - always@(guard__h23321 or - sfd___3__h22785 or out_sfd__h23764 or _theResult___sfd__h23761) - begin - case (guard__h23321) - 2'b0, 2'b01: - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q35 = - sfd___3__h22785[62:40]; - 2'b10: - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q35 = - out_sfd__h23764; - 2'b11: - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q35 = - _theResult___sfd__h23761; - endcase - end - always@(guard__h22795 or sfd___3__h22785 or _theResult___sfd__h23209) - begin - case (guard__h22795) - 2'b0: - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q36 = - sfd___3__h22785[63:41]; - 2'b01, 2'b10, 2'b11: - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q36 = - _theResult___sfd__h23209; - endcase - end - always@(requestR or - sfd___3__h22785 or - guard__h22795 or - _theResult___sfd__h23209 or - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q36) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027 = - sfd___3__h22785[63:41]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027 = - (guard__h22795 == 2'b0) ? - sfd___3__h22785[63:41] : - _theResult___sfd__h23209; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027 = - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q36; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027 = - 23'd0; - endcase - end - always@(guard__h22795 or - sfd___3__h22785 or out_sfd__h23212 or _theResult___sfd__h23209) - begin - case (guard__h22795) - 2'b0, 2'b01: - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q37 = - sfd___3__h22785[63:41]; - 2'b10: - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q37 = - out_sfd__h23212; - 2'b11: - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q37 = - _theResult___sfd__h23209; - endcase - end - always@(guard__h29167 or requestR) - begin - case (guard__h29167) - 2'b0, 2'b01, 2'b10: - CASE_guard9167_0b0_requestR_BIT_159_0b1_reques_ETC__q40 = - requestR[159]; - 2'd3: - CASE_guard9167_0b0_requestR_BIT_159_0b1_reques_ETC__q40 = - guard__h29167 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h29167) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q41 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q41 = - (guard__h29167 == 2'b0) ? - requestR[159] : - (guard__h29167 == 2'b01 || guard__h29167 == 2'b10 || - guard__h29167 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q41 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h29694 or requestR) - begin - case (guard__h29694) - 2'b0, 2'b01, 2'b10: - CASE_guard9694_0b0_requestR_BIT_159_0b1_reques_ETC__q42 = - requestR[159]; - 2'd3: - CASE_guard9694_0b0_requestR_BIT_159_0b1_reques_ETC__q42 = - guard__h29694 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h29694) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q43 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q43 = - (guard__h29694 == 2'b0) ? - requestR[159] : - (guard__h29694 == 2'b01 || guard__h29694 == 2'b10 || - guard__h29694 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q43 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h29167 or _theResult___exp__h29580) - begin - case (guard__h29167) - 2'b0: CASE_guard9167_0b0_0_0b1_theResult___exp9580_0_ETC__q44 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard9167_0b0_0_0b1_theResult___exp9580_0_ETC__q44 = - _theResult___exp__h29580; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1353 or - guard__h29167 or - _theResult___exp__h29580 or - CASE_guard9167_0b0_0_0b1_theResult___exp9580_0_ETC__q44) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1353; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356 = - (guard__h29167 == 2'b0 || requestR[159]) ? - 8'd0 : - _theResult___exp__h29580; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356 = - CASE_guard9167_0b0_0_0b1_theResult___exp9580_0_ETC__q44; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356 = - 8'd0; - endcase - end - always@(guard__h29167 or out_exp__h29583 or _theResult___exp__h29580) - begin - case (guard__h29167) - 2'b0, 2'b01: - CASE_guard9167_0b0_0_0b1_0_0b10_out_exp9583_0b_ETC__q45 = 8'd0; - 2'b10: - CASE_guard9167_0b0_0_0b1_0_0b10_out_exp9583_0b_ETC__q45 = - out_exp__h29583; - 2'b11: - CASE_guard9167_0b0_0_0b1_0_0b10_out_exp9583_0b_ETC__q45 = - _theResult___exp__h29580; - endcase - end - always@(guard__h29694 or x__h29709 or _theResult___exp__h30133) - begin - case (guard__h29694) - 2'b0: - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_theRe_ETC__q46 = - x__h29709[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_theRe_ETC__q46 = - _theResult___exp__h30133; - endcase - end - always@(requestR or - x__h29709 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1381 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1379 or - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_theRe_ETC__q46) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 = - x__h29709[7:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1381; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1379; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 = - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_theRe_ETC__q46; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 = - 8'd0; - endcase - end - always@(guard__h29694 or - x__h29709 or out_exp__h30136 or _theResult___exp__h30133) - begin - case (guard__h29694) - 2'b0, 2'b01: - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_x9709_ETC__q47 = - x__h29709[7:0]; - 2'b10: - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_x9709_ETC__q47 = - out_exp__h30136; - 2'b11: - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_x9709_ETC__q47 = - _theResult___exp__h30133; - endcase - end - always@(guard__h29167 or sfd___3__h29157 or _theResult___sfd__h29581) - begin - case (guard__h29167) - 2'b0: - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q48 = - sfd___3__h29157[31:9]; - 2'b01, 2'b10, 2'b11: - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q48 = - _theResult___sfd__h29581; - endcase - end - always@(requestR or - sfd___3__h29157 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1404 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1402 or - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q48) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 = - sfd___3__h29157[31:9]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1404; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1402; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 = - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q48; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 = - 23'd0; - endcase - end - always@(guard__h29167 or - sfd___3__h29157 or out_sfd__h29584 or _theResult___sfd__h29581) - begin - case (guard__h29167) - 2'b0, 2'b01: - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q49 = - sfd___3__h29157[31:9]; - 2'b10: - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q49 = - out_sfd__h29584; - 2'b11: - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q49 = - _theResult___sfd__h29581; - endcase - end - always@(guard__h29694 or sfd___3__h29157 or _theResult___sfd__h30134) - begin - case (guard__h29694) - 2'b0: - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q50 = - sfd___3__h29157[30:8]; - 2'b01, 2'b10, 2'b11: - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q50 = - _theResult___sfd__h30134; - endcase - end - always@(requestR or - sfd___3__h29157 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1422 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1420 or - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q50) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 = - sfd___3__h29157[30:8]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1422; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1420; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 = - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q50; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 = - 23'd0; - endcase - end - always@(guard__h29694 or - sfd___3__h29157 or out_sfd__h30137 or _theResult___sfd__h30134) - begin - case (guard__h29694) - 2'b0, 2'b01: - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q51 = - sfd___3__h29157[30:8]; - 2'b10: - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q51 = - out_sfd__h30137; - 2'b11: - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q51 = - _theResult___sfd__h30134; - endcase - end - always@(guard__h35283 or out_exp__h35699 or _theResult___exp__h35696) - begin - case (guard__h35283) - 2'b0, 2'b01: - CASE_guard5283_0b0_0_0b1_0_0b10_out_exp5699_0b_ETC__q54 = 8'd0; - 2'b10: - CASE_guard5283_0b0_0_0b1_0_0b10_out_exp5699_0b_ETC__q54 = - out_exp__h35699; - 2'b11: - CASE_guard5283_0b0_0_0b1_0_0b10_out_exp5699_0b_ETC__q54 = - _theResult___exp__h35696; - endcase - end - always@(guard__h35283 or _theResult___exp__h35696) - begin - case (guard__h35283) - 2'b0: CASE_guard5283_0b0_0_0b1_theResult___exp5696_0_ETC__q55 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard5283_0b0_0_0b1_theResult___exp5696_0_ETC__q55 = - _theResult___exp__h35696; - endcase - end - always@(requestR or - guard__h35283 or - _theResult___exp__h35696 or - CASE_guard5283_0b0_0_0b1_theResult___exp5696_0_ETC__q55) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5283_ETC__q56 = - (guard__h35283 == 2'b0) ? 8'd0 : _theResult___exp__h35696; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5283_ETC__q56 = - CASE_guard5283_0b0_0_0b1_theResult___exp5696_0_ETC__q55; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard5283_ETC__q56 = 8'd0; - endcase - end - always@(guard__h35809 or x__h35824 or _theResult___exp__h36248) - begin - case (guard__h35809) - 2'b0: - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_theRe_ETC__q57 = - x__h35824[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_theRe_ETC__q57 = - _theResult___exp__h36248; - endcase - end - always@(requestR or - x__h35824 or - guard__h35809 or - _theResult___exp__h36248 or - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_theRe_ETC__q57) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607 = - x__h35824[7:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607 = - (guard__h35809 == 2'b0) ? - x__h35824[7:0] : - _theResult___exp__h36248; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607 = - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_theRe_ETC__q57; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607 = - 8'd0; - endcase - end - always@(guard__h35809 or - x__h35824 or out_exp__h36251 or _theResult___exp__h36248) - begin - case (guard__h35809) - 2'b0, 2'b01: - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_x5824_ETC__q58 = - x__h35824[7:0]; - 2'b10: - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_x5824_ETC__q58 = - out_exp__h36251; - 2'b11: - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_x5824_ETC__q58 = - _theResult___exp__h36248; - endcase - end - always@(guard__h35809 or sfd___3__h35273 or _theResult___sfd__h36249) - begin - case (guard__h35809) - 2'b0: - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q59 = - sfd___3__h35273[30:8]; - 2'b01, 2'b10, 2'b11: - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q59 = - _theResult___sfd__h36249; - endcase - end - always@(requestR or - sfd___3__h35273 or - guard__h35809 or - _theResult___sfd__h36249 or - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q59) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645 = - sfd___3__h35273[30:8]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645 = - (guard__h35809 == 2'b0) ? - sfd___3__h35273[30:8] : - _theResult___sfd__h36249; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645 = - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q59; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645 = - 23'd0; - endcase - end - always@(guard__h35809 or - sfd___3__h35273 or out_sfd__h36252 or _theResult___sfd__h36249) - begin - case (guard__h35809) - 2'b0, 2'b01: - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q60 = - sfd___3__h35273[30:8]; - 2'b10: - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q60 = - out_sfd__h36252; - 2'b11: - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q60 = - _theResult___sfd__h36249; - endcase - end - always@(guard__h35283 or sfd___3__h35273 or _theResult___sfd__h35697) - begin - case (guard__h35283) - 2'b0: - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q61 = - sfd___3__h35273[31:9]; - 2'b01, 2'b10, 2'b11: - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q61 = - _theResult___sfd__h35697; - endcase - end - always@(requestR or - sfd___3__h35273 or - guard__h35283 or - _theResult___sfd__h35697 or - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q61) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630 = - sfd___3__h35273[31:9]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630 = - (guard__h35283 == 2'b0) ? - sfd___3__h35273[31:9] : - _theResult___sfd__h35697; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630 = - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q61; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630 = - 23'd0; - endcase - end - always@(guard__h35283 or - sfd___3__h35273 or out_sfd__h35700 or _theResult___sfd__h35697) - begin - case (guard__h35283) - 2'b0, 2'b01: - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q62 = - sfd___3__h35273[31:9]; - 2'b10: - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q62 = - out_sfd__h35700; - 2'b11: - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q62 = - _theResult___sfd__h35697; - endcase - end - always@(guard__h59814 or requestR) - begin - case (guard__h59814) - 2'b0, 2'b01, 2'b10: - CASE_guard9814_0b0_requestR_BIT_159_0b1_reques_ETC__q69 = - requestR[159]; - 2'd3: - CASE_guard9814_0b0_requestR_BIT_159_0b1_reques_ETC__q69 = - guard__h59814 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h59814) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q70 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q70 = - (guard__h59814 == 2'b0) ? - requestR[159] : - (guard__h59814 == 2'b01 || guard__h59814 == 2'b10 || - guard__h59814 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q70 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h60544 or requestR) - begin - case (guard__h60544) - 2'b0, 2'b01, 2'b10: - CASE_guard0544_0b0_requestR_BIT_159_0b1_reques_ETC__q71 = - requestR[159]; - 2'd3: - CASE_guard0544_0b0_requestR_BIT_159_0b1_reques_ETC__q71 = - guard__h60544 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h60544) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q72 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q72 = - (guard__h60544 == 2'b0) ? - requestR[159] : - (guard__h60544 == 2'b01 || guard__h60544 == 2'b10 || - guard__h60544 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q72 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h60544 or x__h60559 or _theResult___exp__h61186) - begin - case (guard__h60544) - 2'b0: - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_theR_ETC__q73 = - x__h60559[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_theR_ETC__q73 = - _theResult___exp__h61186; - endcase - end - always@(requestR or - x__h60559 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2349 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2347 or - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_theR_ETC__q73) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 = - x__h60559[10:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2349; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2347; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 = - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_theR_ETC__q73; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 = - 11'd0; - endcase - end - always@(guard__h60544 or - x__h60559 or out_exp__h61189 or _theResult___exp__h61186) - begin - case (guard__h60544) - 2'b0, 2'b01: - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_x055_ETC__q74 = - x__h60559[10:0]; - 2'b10: - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_x055_ETC__q74 = - out_exp__h61189; - 2'b11: - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_x055_ETC__q74 = - _theResult___exp__h61186; - endcase - end - always@(guard__h60544 or sfd___3__h59804 or _theResult___sfd__h61187) - begin - case (guard__h60544) - 2'b0: - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q75 = - sfd___3__h59804[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q75 = - _theResult___sfd__h61187; - endcase - end - always@(requestR or - sfd___3__h59804 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2390 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2388 or - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q75) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 = - sfd___3__h59804[53:2]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2390; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2388; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 = - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q75; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 = - 52'd0; - endcase - end - always@(guard__h60544 or - sfd___3__h59804 or out_sfd__h61190 or _theResult___sfd__h61187) - begin - case (guard__h60544) - 2'b0, 2'b01: - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q76 = - sfd___3__h59804[53:2]; - 2'b10: - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q76 = - out_sfd__h61190; - 2'b11: - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q76 = - _theResult___sfd__h61187; - endcase - end - always@(guard__h59814 or _theResult___exp__h60430) - begin - case (guard__h59814) - 2'b0: CASE_guard9814_0b0_0_0b1_theResult___exp0430_0_ETC__q77 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard9814_0b0_0_0b1_theResult___exp0430_0_ETC__q77 = - _theResult___exp__h60430; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2321 or - guard__h59814 or - _theResult___exp__h60430 or - CASE_guard9814_0b0_0_0b1_theResult___exp0430_0_ETC__q77) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2321; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324 = - (guard__h59814 == 2'b0 || requestR[159]) ? - 11'd0 : - _theResult___exp__h60430; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324 = - CASE_guard9814_0b0_0_0b1_theResult___exp0430_0_ETC__q77; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324 = - 11'd0; - endcase - end - always@(guard__h59814 or out_exp__h60433 or _theResult___exp__h60430) - begin - case (guard__h59814) - 2'b0, 2'b01: - CASE_guard9814_0b0_0_0b1_0_0b10_out_exp0433_0b_ETC__q78 = 11'd0; - 2'b10: - CASE_guard9814_0b0_0_0b1_0_0b10_out_exp0433_0b_ETC__q78 = - out_exp__h60433; - 2'b11: - CASE_guard9814_0b0_0_0b1_0_0b10_out_exp0433_0b_ETC__q78 = - _theResult___exp__h60430; - endcase - end - always@(guard__h59814 or sfd___3__h59804 or _theResult___sfd__h60431) - begin - case (guard__h59814) - 2'b0: - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q79 = - sfd___3__h59804[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q79 = - _theResult___sfd__h60431; - endcase - end - always@(requestR or - sfd___3__h59804 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2372 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2370 or - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q79) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 = - sfd___3__h59804[54:3]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2372; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2370; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 = - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q79; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 = - 52'd0; - endcase - end - always@(guard__h59814 or - sfd___3__h59804 or out_sfd__h60434 or _theResult___sfd__h60431) - begin - case (guard__h59814) - 2'b0, 2'b01: - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q80 = - sfd___3__h59804[54:3]; - 2'b10: - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q80 = - out_sfd__h60434; - 2'b11: - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q80 = - _theResult___sfd__h60431; - endcase - end - always@(guard__h69455 or out_exp__h70074 or _theResult___exp__h70071) - begin - case (guard__h69455) - 2'b0, 2'b01: - CASE_guard9455_0b0_0_0b1_0_0b10_out_exp0074_0b_ETC__q83 = 11'd0; - 2'b10: - CASE_guard9455_0b0_0_0b1_0_0b10_out_exp0074_0b_ETC__q83 = - out_exp__h70074; - 2'b11: - CASE_guard9455_0b0_0_0b1_0_0b10_out_exp0074_0b_ETC__q83 = - _theResult___exp__h70071; - endcase - end - always@(guard__h69455 or _theResult___exp__h70071) - begin - case (guard__h69455) - 2'b0: CASE_guard9455_0b0_0_0b1_theResult___exp0071_0_ETC__q84 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard9455_0b0_0_0b1_theResult___exp0071_0_ETC__q84 = - _theResult___exp__h70071; - endcase - end - always@(requestR or - guard__h69455 or - _theResult___exp__h70071 or - CASE_guard9455_0b0_0_0b1_theResult___exp0071_0_ETC__q84) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard9455_ETC__q85 = - (guard__h69455 == 2'b0) ? 11'd0 : _theResult___exp__h70071; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard9455_ETC__q85 = - CASE_guard9455_0b0_0_0b1_theResult___exp0071_0_ETC__q84; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard9455_ETC__q85 = - 11'd0; - endcase - end - always@(guard__h70184 or x__h70199 or _theResult___exp__h70826) - begin - case (guard__h70184) - 2'b0: - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_theR_ETC__q86 = - x__h70199[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_theR_ETC__q86 = - _theResult___exp__h70826; - endcase - end - always@(requestR or - x__h70199 or - guard__h70184 or - _theResult___exp__h70826 or - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_theR_ETC__q86) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539 = - x__h70199[10:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539 = - (guard__h70184 == 2'b0) ? - x__h70199[10:0] : - _theResult___exp__h70826; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539 = - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_theR_ETC__q86; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539 = - 11'd0; - endcase - end - always@(guard__h70184 or - x__h70199 or out_exp__h70829 or _theResult___exp__h70826) - begin - case (guard__h70184) - 2'b0, 2'b01: - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_x019_ETC__q87 = - x__h70199[10:0]; - 2'b10: - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_x019_ETC__q87 = - out_exp__h70829; - 2'b11: - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_x019_ETC__q87 = - _theResult___exp__h70826; - endcase - end - always@(guard__h70184 or sfd___3__h69445 or _theResult___sfd__h70827) - begin - case (guard__h70184) - 2'b0: - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q88 = - sfd___3__h69445[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q88 = - _theResult___sfd__h70827; - endcase - end - always@(requestR or - sfd___3__h69445 or - guard__h70184 or - _theResult___sfd__h70827 or - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q88) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576 = - sfd___3__h69445[53:2]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576 = - (guard__h70184 == 2'b0) ? - sfd___3__h69445[53:2] : - _theResult___sfd__h70827; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576 = - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q88; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576 = - 52'd0; - endcase - end - always@(guard__h70184 or - sfd___3__h69445 or out_sfd__h70830 or _theResult___sfd__h70827) - begin - case (guard__h70184) - 2'b0, 2'b01: - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q89 = - sfd___3__h69445[53:2]; - 2'b10: - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q89 = - out_sfd__h70830; - 2'b11: - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q89 = - _theResult___sfd__h70827; - endcase - end - always@(guard__h69455 or sfd___3__h69445 or _theResult___sfd__h70072) - begin - case (guard__h69455) - 2'b0: - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q90 = - sfd___3__h69445[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q90 = - _theResult___sfd__h70072; - endcase - end - always@(requestR or - sfd___3__h69445 or - guard__h69455 or - _theResult___sfd__h70072 or - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q90) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561 = - sfd___3__h69445[54:3]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561 = - (guard__h69455 == 2'b0) ? - sfd___3__h69445[54:3] : - _theResult___sfd__h70072; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561 = - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q90; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561 = - 52'd0; - endcase - end - always@(guard__h69455 or - sfd___3__h69445 or out_sfd__h70075 or _theResult___sfd__h70072) - begin - case (guard__h69455) - 2'b0, 2'b01: - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q91 = - sfd___3__h69445[54:3]; - 2'b10: - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q91 = - out_sfd__h70075; - 2'b11: - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q91 = - _theResult___sfd__h70072; - endcase - end - always@(guard__h83135 or requestR) - begin - case (guard__h83135) - 2'b0, 2'b01, 2'b10: - CASE_guard3135_0b0_requestR_BIT_191_0b1_reques_ETC__q94 = - requestR[191]; - 2'd3: - CASE_guard3135_0b0_requestR_BIT_191_0b1_reques_ETC__q94 = - guard__h83135 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h83135) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q95 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q95 = - (guard__h83135 == 2'b0) ? - requestR[191] : - (guard__h83135 == 2'b01 || guard__h83135 == 2'b10 || - guard__h83135 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q95 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h83865 or requestR) - begin - case (guard__h83865) - 2'b0, 2'b01, 2'b10: - CASE_guard3865_0b0_requestR_BIT_191_0b1_reques_ETC__q96 = - requestR[191]; - 2'd3: - CASE_guard3865_0b0_requestR_BIT_191_0b1_reques_ETC__q96 = - guard__h83865 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h83865) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q97 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q97 = - (guard__h83865 == 2'b0) ? - requestR[191] : - (guard__h83865 == 2'b01 || guard__h83865 == 2'b10 || - guard__h83865 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q97 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h83865 or x__h83880 or _theResult___exp__h84507) - begin - case (guard__h83865) - 2'b0: - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_theR_ETC__q98 = - x__h83880[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_theR_ETC__q98 = - _theResult___exp__h84507; - endcase - end - always@(requestR or - x__h83880 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2880 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2878 or - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_theR_ETC__q98) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 = - x__h83880[10:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2880; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2878; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 = - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_theR_ETC__q98; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 = - 11'd0; - endcase - end - always@(guard__h83865 or - x__h83880 or out_exp__h84510 or _theResult___exp__h84507) - begin - case (guard__h83865) - 2'b0, 2'b01: - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_x388_ETC__q99 = - x__h83880[10:0]; - 2'b10: - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_x388_ETC__q99 = - out_exp__h84510; - 2'b11: - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_x388_ETC__q99 = - _theResult___exp__h84507; - endcase - end - always@(guard__h83865 or sfd___3__h12218 or _theResult___sfd__h84508) - begin - case (guard__h83865) - 2'b0: - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q100 = - sfd___3__h12218[62:11]; - 2'b01, 2'b10, 2'b11: - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q100 = - _theResult___sfd__h84508; - endcase - end - always@(requestR or - sfd___3__h12218 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2921 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2919 or - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q100) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 = - sfd___3__h12218[62:11]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2921; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2919; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 = - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q100; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 = - 52'd0; - endcase - end - always@(guard__h83865 or - sfd___3__h12218 or out_sfd__h84511 or _theResult___sfd__h84508) - begin - case (guard__h83865) - 2'b0, 2'b01: - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q101 = - sfd___3__h12218[62:11]; - 2'b10: - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q101 = - out_sfd__h84511; - 2'b11: - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q101 = - _theResult___sfd__h84508; - endcase - end - always@(guard__h83135 or _theResult___exp__h83751) - begin - case (guard__h83135) - 2'b0: CASE_guard3135_0b0_0_0b1_theResult___exp3751_0_ETC__q102 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard3135_0b0_0_0b1_theResult___exp3751_0_ETC__q102 = - _theResult___exp__h83751; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2852 or - guard__h83135 or - _theResult___exp__h83751 or - CASE_guard3135_0b0_0_0b1_theResult___exp3751_0_ETC__q102) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2852; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855 = - (guard__h83135 == 2'b0 || requestR[191]) ? - 11'd0 : - _theResult___exp__h83751; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855 = - CASE_guard3135_0b0_0_0b1_theResult___exp3751_0_ETC__q102; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855 = - 11'd0; - endcase - end - always@(guard__h83135 or out_exp__h83754 or _theResult___exp__h83751) - begin - case (guard__h83135) - 2'b0, 2'b01: - CASE_guard3135_0b0_0_0b1_0_0b10_out_exp3754_0b_ETC__q103 = 11'd0; - 2'b10: - CASE_guard3135_0b0_0_0b1_0_0b10_out_exp3754_0b_ETC__q103 = - out_exp__h83754; - 2'b11: - CASE_guard3135_0b0_0_0b1_0_0b10_out_exp3754_0b_ETC__q103 = - _theResult___exp__h83751; - endcase - end - always@(guard__h83135 or sfd___3__h12218 or _theResult___sfd__h83752) - begin - case (guard__h83135) - 2'b0: - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q104 = - sfd___3__h12218[63:12]; - 2'b01, 2'b10, 2'b11: - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q104 = - _theResult___sfd__h83752; - endcase - end - always@(requestR or - sfd___3__h12218 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2903 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2901 or - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q104) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 = - sfd___3__h12218[63:12]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2903; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2901; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 = - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q104; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 = - 52'd0; - endcase - end - always@(guard__h83135 or - sfd___3__h12218 or out_sfd__h83755 or _theResult___sfd__h83752) - begin - case (guard__h83135) - 2'b0, 2'b01: - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q105 = - sfd___3__h12218[63:12]; - 2'b10: - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q105 = - out_sfd__h83755; - 2'b11: - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q105 = - _theResult___sfd__h83752; - endcase - end - always@(guard__h94821 or x__h94836 or _theResult___exp__h95463) - begin - case (guard__h94821) - 2'b0: - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_theR_ETC__q106 = - x__h94836[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_theR_ETC__q106 = - _theResult___exp__h95463; - endcase - end - always@(requestR or - x__h94836 or - guard__h94821 or - _theResult___exp__h95463 or - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_theR_ETC__q106) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039 = - x__h94836[10:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039 = - (guard__h94821 == 2'b0) ? - x__h94836[10:0] : - _theResult___exp__h95463; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039 = - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_theR_ETC__q106; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039 = - 11'd0; - endcase - end - always@(guard__h94821 or - x__h94836 or out_exp__h95466 or _theResult___exp__h95463) - begin - case (guard__h94821) - 2'b0, 2'b01: - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_x483_ETC__q107 = - x__h94836[10:0]; - 2'b10: - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_x483_ETC__q107 = - out_exp__h95466; - 2'b11: - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_x483_ETC__q107 = - _theResult___exp__h95463; - endcase - end - always@(guard__h94821 or sfd___3__h22785 or _theResult___sfd__h95464) - begin - case (guard__h94821) - 2'b0: - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q108 = - sfd___3__h22785[62:11]; - 2'b01, 2'b10, 2'b11: - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q108 = - _theResult___sfd__h95464; - endcase - end - always@(requestR or - sfd___3__h22785 or - guard__h94821 or - _theResult___sfd__h95464 or - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q108) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077 = - sfd___3__h22785[62:11]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077 = - (guard__h94821 == 2'b0) ? - sfd___3__h22785[62:11] : - _theResult___sfd__h95464; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077 = - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q108; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077 = - 52'd0; - endcase - end - always@(guard__h94821 or - sfd___3__h22785 or out_sfd__h95467 or _theResult___sfd__h95464) - begin - case (guard__h94821) - 2'b0, 2'b01: - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q109 = - sfd___3__h22785[62:11]; - 2'b10: - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q109 = - out_sfd__h95467; - 2'b11: - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q109 = - _theResult___sfd__h95464; - endcase - end - always@(guard__h94092 or sfd___3__h22785 or _theResult___sfd__h94709) - begin - case (guard__h94092) - 2'b0: - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q110 = - sfd___3__h22785[63:12]; - 2'b01, 2'b10, 2'b11: - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q110 = - _theResult___sfd__h94709; - endcase - end - always@(requestR or - sfd___3__h22785 or - guard__h94092 or - _theResult___sfd__h94709 or - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q110) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062 = - sfd___3__h22785[63:12]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062 = - (guard__h94092 == 2'b0) ? - sfd___3__h22785[63:12] : - _theResult___sfd__h94709; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062 = - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q110; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062 = - 52'd0; - endcase - end - always@(guard__h94092 or - sfd___3__h22785 or out_sfd__h94712 or _theResult___sfd__h94709) - begin - case (guard__h94092) - 2'b0, 2'b01: - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q111 = - sfd___3__h22785[63:12]; - 2'b10: - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q111 = - out_sfd__h94712; - 2'b11: - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q111 = - _theResult___sfd__h94709; - endcase - end - always@(guard__h110454 or - _theResult___fst_exp__h118551 or _theResult___exp__h119077) - begin - case (guard__h110454) - 2'b0: - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q124 = - _theResult___fst_exp__h118551; - 2'b01, 2'b10, 2'b11: - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q124 = - _theResult___exp__h119077; - endcase - end - always@(requestR or - _theResult___fst_exp__h118551 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3601 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3599 or - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q124) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 = - _theResult___fst_exp__h118551; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3601; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3599; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 = - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q124; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 = - 8'd0; - endcase - end - always@(guard__h110454 or - _theResult___fst_exp__h118551 or - out_exp__h119080 or _theResult___exp__h119077) - begin - case (guard__h110454) - 2'b0, 2'b01: - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q125 = - _theResult___fst_exp__h118551; - 2'b10: - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q125 = - out_exp__h119080; - 2'b11: - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q125 = - _theResult___exp__h119077; - endcase - end - always@(guard__h128178 or - _theResult___fst_exp__h136404 or _theResult___exp__h136930) - begin - case (guard__h128178) - 2'b0: - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q126 = - _theResult___fst_exp__h136404; - 2'b01, 2'b10, 2'b11: - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q126 = - _theResult___exp__h136930; - endcase - end - always@(requestR or - _theResult___fst_exp__h136404 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4045 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4043 or - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q126) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 = - _theResult___fst_exp__h136404; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4045; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4043; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 = - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q126; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 = - 8'd0; - endcase - end - always@(guard__h128178 or - _theResult___fst_exp__h136404 or - out_exp__h136933 or _theResult___exp__h136930) - begin - case (guard__h128178) - 2'b0, 2'b01: - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q127 = - _theResult___fst_exp__h136404; - 2'b10: - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q127 = - out_exp__h136933; - 2'b11: - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q127 = - _theResult___exp__h136930; - endcase - end - always@(guard__h119189 or - _theResult___fst_exp__h127237 or _theResult___exp__h127689) - begin - case (guard__h119189) - 2'b0: - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q128 = - _theResult___fst_exp__h127237; - 2'b01, 2'b10, 2'b11: - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q128 = - _theResult___exp__h127689; - endcase - end - always@(requestR or - _theResult___fst_exp__h127237 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3718 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3716 or - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q128) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 = - _theResult___fst_exp__h127237; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3718; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3716; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 = - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q128; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 = - 8'd0; - endcase - end - always@(guard__h119189 or - _theResult___fst_exp__h127237 or - out_exp__h127692 or _theResult___exp__h127689) - begin - case (guard__h119189) - 2'b0, 2'b01: - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q129 = - _theResult___fst_exp__h127237; - 2'b10: - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q129 = - out_exp__h127692; - 2'b11: - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q129 = - _theResult___exp__h127689; - endcase - end - always@(guard__h137042 or - _theResult___fst_exp__h145119 or _theResult___exp__h145596) - begin - case (guard__h137042) - 2'b0: - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q130 = - _theResult___fst_exp__h145119; - 2'b01, 2'b10, 2'b11: - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q130 = - _theResult___exp__h145596; - endcase - end - always@(requestR or - _theResult___fst_exp__h145119 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4114 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4112 or - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q130) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 = - _theResult___fst_exp__h145119; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4114; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4112; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 = - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q130; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 = - 8'd0; - endcase - end - always@(guard__h137042 or - _theResult___fst_exp__h145119 or - out_exp__h145599 or _theResult___exp__h145596) - begin - case (guard__h137042) - 2'b0, 2'b01: - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q131 = - _theResult___fst_exp__h145119; - 2'b10: - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q131 = - out_exp__h145599; - 2'b11: - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q131 = - _theResult___exp__h145596; - endcase - end - always@(guard__h110454 or sfdin__h118545 or _theResult___sfd__h119078) - begin - case (guard__h110454) - 2'b0: - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q132 = - sfdin__h118545[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q132 = - _theResult___sfd__h119078; - endcase - end - always@(requestR or - sfdin__h118545 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4148 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4146 or - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q132) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 = - sfdin__h118545[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4148; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4146; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 = - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q132; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 = - 23'd0; - endcase - end - always@(guard__h110454 or - sfdin__h118545 or out_sfd__h119081 or _theResult___sfd__h119078) - begin - case (guard__h110454) - 2'b0, 2'b01: - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q133 = - sfdin__h118545[56:34]; - 2'b10: - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q133 = - out_sfd__h119081; - 2'b11: - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q133 = - _theResult___sfd__h119078; - endcase - end - always@(guard__h119189 or - _theResult___snd__h127188 or _theResult___sfd__h127690) - begin - case (guard__h119189) - 2'b0: - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q134 = - _theResult___snd__h127188[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q134 = - _theResult___sfd__h127690; - endcase - end - always@(requestR or - _theResult___snd__h127188 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4167 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4165 or - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q134) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 = - _theResult___snd__h127188[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4167; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4165; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 = - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q134; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 = - 23'd0; - endcase - end - always@(guard__h119189 or - _theResult___snd__h127188 or - out_sfd__h127693 or _theResult___sfd__h127690) - begin - case (guard__h119189) - 2'b0, 2'b01: - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q135 = - _theResult___snd__h127188[56:34]; - 2'b10: - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q135 = - out_sfd__h127693; - 2'b11: - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q135 = - _theResult___sfd__h127690; - endcase - end - always@(guard__h128178 or sfdin__h136398 or _theResult___sfd__h136931) - begin - case (guard__h128178) - 2'b0: - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q136 = - sfdin__h136398[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q136 = - _theResult___sfd__h136931; - endcase - end - always@(requestR or - sfdin__h136398 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4194 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4192 or - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q136) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 = - sfdin__h136398[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4194; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4192; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 = - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q136; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 = - 23'd0; - endcase - end - always@(guard__h128178 or - sfdin__h136398 or out_sfd__h136934 or _theResult___sfd__h136931) - begin - case (guard__h128178) - 2'b0, 2'b01: - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q137 = - sfdin__h136398[56:34]; - 2'b10: - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q137 = - out_sfd__h136934; - 2'b11: - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q137 = - _theResult___sfd__h136931; - endcase - end - always@(guard__h137042 or - _theResult___snd__h145065 or _theResult___sfd__h145597) - begin - case (guard__h137042) - 2'b0: - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q138 = - _theResult___snd__h145065[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q138 = - _theResult___sfd__h145597; - endcase - end - always@(requestR or - _theResult___snd__h145065 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4213 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4211 or - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q138) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 = - _theResult___snd__h145065[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4213; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4211; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 = - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q138; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 = - 23'd0; - endcase - end - always@(guard__h137042 or - _theResult___snd__h145065 or - out_sfd__h145600 or _theResult___sfd__h145597) - begin - case (guard__h137042) - 2'b0, 2'b01: - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q139 = - _theResult___snd__h145065[56:34]; - 2'b10: - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q139 = - out_sfd__h145600; - 2'b11: - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q139 = - _theResult___sfd__h145597; - endcase - end - always@(guard__h110454 or requestR) - begin - case (guard__h110454) - 2'b0, 2'b01, 2'b10: - CASE_guard10454_0b0_requestR_BIT_191_0b1_reque_ETC__q140 = - requestR[191]; - 2'd3: - CASE_guard10454_0b0_requestR_BIT_191_0b1_reque_ETC__q140 = - guard__h110454 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h110454) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q141 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q141 = - (guard__h110454 == 2'b0) ? - requestR[191] : - (guard__h110454 == 2'b01 || guard__h110454 == 2'b10 || - guard__h110454 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q141 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h119189 or requestR) - begin - case (guard__h119189) - 2'b0, 2'b01, 2'b10: - CASE_guard19189_0b0_requestR_BIT_191_0b1_reque_ETC__q142 = - requestR[191]; - 2'd3: - CASE_guard19189_0b0_requestR_BIT_191_0b1_reque_ETC__q142 = - guard__h119189 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h119189) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q143 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q143 = - (guard__h119189 == 2'b0) ? - requestR[191] : - (guard__h119189 == 2'b01 || guard__h119189 == 2'b10 || - guard__h119189 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q143 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h128178 or requestR) - begin - case (guard__h128178) - 2'b0, 2'b01, 2'b10: - CASE_guard28178_0b0_requestR_BIT_191_0b1_reque_ETC__q144 = - requestR[191]; - 2'd3: - CASE_guard28178_0b0_requestR_BIT_191_0b1_reque_ETC__q144 = - guard__h128178 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h128178) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q145 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q145 = - (guard__h128178 == 2'b0) ? - requestR[191] : - (guard__h128178 == 2'b01 || guard__h128178 == 2'b10 || - guard__h128178 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q145 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h137042 or requestR) - begin - case (guard__h137042) - 2'b0, 2'b01, 2'b10: - CASE_guard37042_0b0_requestR_BIT_191_0b1_reque_ETC__q146 = - requestR[191]; - 2'd3: - CASE_guard37042_0b0_requestR_BIT_191_0b1_reque_ETC__q146 = - guard__h137042 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h137042) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q147 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q147 = - (guard__h137042 == 2'b0) ? - requestR[191] : - (guard__h137042 == 2'b01 || guard__h137042 == 2'b10 || - guard__h137042 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q147 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h160150 or - _theResult___fst_exp__h168111 or _theResult___exp__h168766) - begin - case (guard__h160150) - 2'b0: - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q156 = - _theResult___fst_exp__h168111; - 2'b01, 2'b10, 2'b11: - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q156 = - _theResult___exp__h168766; - endcase - end - always@(requestR or - _theResult___fst_exp__h168111 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4553 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4551 or - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q156) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 = - _theResult___fst_exp__h168111; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4553; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4551; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 = - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q156; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 = - 11'd0; - endcase - end - always@(guard__h160150 or - _theResult___fst_exp__h168111 or - out_exp__h168769 or _theResult___exp__h168766) - begin - case (guard__h160150) - 2'b0, 2'b01: - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q157 = - _theResult___fst_exp__h168111; - 2'b10: - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q157 = - out_exp__h168769; - 2'b11: - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q157 = - _theResult___exp__h168766; - endcase - end - always@(guard__h169458 or - _theResult___fst_exp__h177684 or _theResult___exp__h178413) - begin - case (guard__h169458) - 2'b0: - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q158 = - _theResult___fst_exp__h177684; - 2'b01, 2'b10, 2'b11: - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q158 = - _theResult___exp__h178413; - endcase - end - always@(requestR or - _theResult___fst_exp__h177684 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4878 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4876 or - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q158) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 = - _theResult___fst_exp__h177684; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4878; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4876; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 = - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q158; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 = - 11'd0; - endcase - end - always@(guard__h169458 or - _theResult___fst_exp__h177684 or - out_exp__h178416 or _theResult___exp__h178413) - begin - case (guard__h169458) - 2'b0, 2'b01: - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q159 = - _theResult___fst_exp__h177684; - 2'b10: - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q159 = - out_exp__h178416; - 2'b11: - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q159 = - _theResult___exp__h178413; - endcase - end - always@(guard__h178525 or - _theResult___fst_exp__h186515 or _theResult___exp__h187195) - begin - case (guard__h178525) - 2'b0: - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q160 = - _theResult___fst_exp__h186515; - 2'b01, 2'b10, 2'b11: - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q160 = - _theResult___exp__h187195; - endcase - end - always@(requestR or - _theResult___fst_exp__h186515 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4947 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4945 or - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q160) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 = - _theResult___fst_exp__h186515; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4947; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4945; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 = - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q160; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 = - 11'd0; - endcase - end - always@(guard__h178525 or - _theResult___fst_exp__h186515 or - out_exp__h187198 or _theResult___exp__h187195) - begin - case (guard__h178525) - 2'b0, 2'b01: - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q161 = - _theResult___fst_exp__h186515; - 2'b10: - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q161 = - out_exp__h187198; - 2'b11: - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q161 = - _theResult___exp__h187195; - endcase - end - always@(guard__h160150 or requestR) - begin - case (guard__h160150) - 2'b0, 2'b01, 2'b10: - CASE_guard60150_0b0_requestR_BITS_191_TO_160_E_ETC__q162 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard60150_0b0_requestR_BITS_191_TO_160_E_ETC__q162 = - guard__h160150 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h160150) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q163 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q163 = - (guard__h160150 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h160150 == 2'b01 || guard__h160150 == 2'b10 || - guard__h160150 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q163 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h169458 or requestR) - begin - case (guard__h169458) - 2'b0, 2'b01, 2'b10: - CASE_guard69458_0b0_requestR_BITS_191_TO_160_E_ETC__q164 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard69458_0b0_requestR_BITS_191_TO_160_E_ETC__q164 = - guard__h169458 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h169458) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q165 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q165 = - (guard__h169458 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h169458 == 2'b01 || guard__h169458 == 2'b10 || - guard__h169458 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q165 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h178525 or requestR) - begin - case (guard__h178525) - 2'b0, 2'b01, 2'b10: - CASE_guard78525_0b0_requestR_BITS_191_TO_160_E_ETC__q166 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard78525_0b0_requestR_BITS_191_TO_160_E_ETC__q166 = - guard__h178525 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h178525) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q167 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q167 = - (guard__h178525 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h178525 == 2'b01 || guard__h178525 == 2'b10 || - guard__h178525 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q167 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h160150 or - _theResult___snd__h168062 or _theResult___sfd__h168767) - begin - case (guard__h160150) - 2'b0: - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q168 = - _theResult___snd__h168062[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q168 = - _theResult___sfd__h168767; - endcase - end - always@(requestR or - _theResult___snd__h168062 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4980 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4978 or - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q168) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 = - _theResult___snd__h168062[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4980; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4978; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 = - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q168; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 = - 52'd0; - endcase - end - always@(guard__h160150 or - _theResult___snd__h168062 or - out_sfd__h168770 or _theResult___sfd__h168767) - begin - case (guard__h160150) - 2'b0, 2'b01: - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q169 = - _theResult___snd__h168062[56:5]; - 2'b10: - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q169 = - out_sfd__h168770; - 2'b11: - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q169 = - _theResult___sfd__h168767; - endcase - end - always@(guard__h169458 or sfdin__h177678 or _theResult___sfd__h178414) - begin - case (guard__h169458) - 2'b0: - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q170 = - sfdin__h177678[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q170 = - _theResult___sfd__h178414; - endcase - end - always@(requestR or - sfdin__h177678 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5007 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5005 or - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q170) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 = - sfdin__h177678[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5007; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5005; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 = - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q170; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 = - 52'd0; - endcase - end - always@(guard__h169458 or - sfdin__h177678 or out_sfd__h178417 or _theResult___sfd__h178414) - begin - case (guard__h169458) - 2'b0, 2'b01: - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q171 = - sfdin__h177678[56:5]; - 2'b10: - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q171 = - out_sfd__h178417; - 2'b11: - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q171 = - _theResult___sfd__h178414; - endcase - end - always@(guard__h178525 or - _theResult___snd__h186461 or _theResult___sfd__h187196) - begin - case (guard__h178525) - 2'b0: - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q172 = - _theResult___snd__h186461[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q172 = - _theResult___sfd__h187196; - endcase - end - always@(requestR or - _theResult___snd__h186461 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5026 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5024 or - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q172) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 = - _theResult___snd__h186461[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5026; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5024; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 = - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q172; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 = - 52'd0; - endcase - end - always@(guard__h178525 or - _theResult___snd__h186461 or - out_sfd__h187199 or _theResult___sfd__h187196) - begin - case (guard__h178525) - 2'b0, 2'b01: - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q173 = - _theResult___snd__h186461[56:5]; - 2'b10: - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q173 = - out_sfd__h187199; - 2'b11: - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q173 = - _theResult___sfd__h187196; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - stateR <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (stateR$EN) stateR <= `BSV_ASSIGNMENT_DELAY stateR$D_IN; - end - if (requestR$EN) requestR <= `BSV_ASSIGNMENT_DELAY requestR$D_IN; - if (resultR$EN) resultR <= `BSV_ASSIGNMENT_DELAY resultR$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - requestR = 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - resultR = 70'h2AAAAAAAAAAAAAAAAA; - stateR = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkFBox_Core - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Top.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Top.v deleted file mode 100644 index 916b8699..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFBox_Top.v +++ /dev/null @@ -1,184 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// valid O 1 -// word_fst O 64 -// word_snd O 5 -// CLK I 1 clock -// RST_N I 1 reset -// req_opcode I 7 -// req_f7 I 7 -// req_rm I 3 -// req_rs2 I 5 -// req_v1 I 64 -// req_v2 I 64 -// req_v3 I 64 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFBox_Top(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_opcode, - req_f7, - req_rm, - req_rs2, - req_v1, - req_v2, - req_v3, - EN_req, - - valid, - - word_fst, - - word_snd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [6 : 0] req_opcode; - input [6 : 0] req_f7; - input [2 : 0] req_rm; - input [4 : 0] req_rs2; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input [63 : 0] req_v3; - input EN_req; - - // value method valid - output valid; - - // value method word_fst - output [63 : 0] word_fst; - - // value method word_snd - output [4 : 0] word_snd; - - // signals for module outputs - wire [63 : 0] word_fst; - wire [4 : 0] word_snd; - wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid; - - // ports of submodule fbox_core - wire [63 : 0] fbox_core$req_v1, - fbox_core$req_v2, - fbox_core$req_v3, - fbox_core$word_fst; - wire [6 : 0] fbox_core$req_f7, fbox_core$req_opcode; - wire [4 : 0] fbox_core$req_rs2, fbox_core$word_snd; - wire [2 : 0] fbox_core$req_rm; - wire fbox_core$EN_req, - fbox_core$EN_server_reset_request_put, - fbox_core$EN_server_reset_response_get, - fbox_core$RDY_server_reset_request_put, - fbox_core$RDY_server_reset_response_get, - fbox_core$valid; - - // rule scheduling signals - wire CAN_FIRE_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = - fbox_core$RDY_server_reset_request_put ; - assign CAN_FIRE_server_reset_request_put = - fbox_core$RDY_server_reset_request_put ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - fbox_core$RDY_server_reset_response_get ; - assign CAN_FIRE_server_reset_response_get = - fbox_core$RDY_server_reset_response_get ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = fbox_core$valid ; - - // value method word_fst - assign word_fst = fbox_core$word_fst ; - - // value method word_snd - assign word_snd = fbox_core$word_snd ; - - // submodule fbox_core - mkFBox_Core fbox_core(.CLK(CLK), - .RST_N(RST_N), - .req_f7(fbox_core$req_f7), - .req_opcode(fbox_core$req_opcode), - .req_rm(fbox_core$req_rm), - .req_rs2(fbox_core$req_rs2), - .req_v1(fbox_core$req_v1), - .req_v2(fbox_core$req_v2), - .req_v3(fbox_core$req_v3), - .EN_server_reset_request_put(fbox_core$EN_server_reset_request_put), - .EN_server_reset_response_get(fbox_core$EN_server_reset_response_get), - .EN_req(fbox_core$EN_req), - .RDY_server_reset_request_put(fbox_core$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fbox_core$RDY_server_reset_response_get), - .valid(fbox_core$valid), - .word_fst(fbox_core$word_fst), - .word_snd(fbox_core$word_snd)); - - // submodule fbox_core - assign fbox_core$req_f7 = req_f7 ; - assign fbox_core$req_opcode = req_opcode ; - assign fbox_core$req_rm = req_rm ; - assign fbox_core$req_rs2 = req_rs2 ; - assign fbox_core$req_v1 = req_v1 ; - assign fbox_core$req_v2 = req_v2 ; - assign fbox_core$req_v3 = req_v3 ; - assign fbox_core$EN_server_reset_request_put = EN_server_reset_request_put ; - assign fbox_core$EN_server_reset_response_get = - EN_server_reset_response_get ; - assign fbox_core$EN_req = EN_req ; -endmodule // mkFBox_Top - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPR_RegFile.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPR_RegFile.v deleted file mode 100644 index ae1589d4..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPR_RegFile.v +++ /dev/null @@ -1,258 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 64 -// read_rs1_port2 O 64 -// read_rs2 O 64 -// read_rs3 O 64 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// read_rs3_rs3 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - read_rs3_rs3, - read_rs3, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [63 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [63 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [63 : 0] read_rs2; - - // value method read_rs3 - input [4 : 0] read_rs3_rs3; - output [63 : 0] read_rs3; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [63 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [63 : 0] read_rs1, read_rs1_port2, read_rs2, read_rs3; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [63 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3, - regfile$D_OUT_4; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = regfile$D_OUT_4 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = regfile$D_OUT_3 ; - - // value method read_rs2 - assign read_rs2 = regfile$D_OUT_2 ; - - // value method read_rs3 - assign read_rs3 = regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd64), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(regfile$D_OUT_4), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs3_rs3 ; - assign regfile$ADDR_2 = read_rs2_rs2 ; - assign regfile$ADDR_3 = read_rs1_port2_rs1 ; - assign regfile$ADDR_4 = read_rs1_rs1 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkFPR_RegFile - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPU.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPU.v deleted file mode 100644 index ec7dfc10..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFPU.v +++ /dev/null @@ -1,12705 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_core_request_put O 1 reg -// server_core_response_get O 70 reg -// RDY_server_core_response_get O 1 reg -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// server_core_request_put I 202 reg -// EN_server_core_request_put I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_server_core_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFPU(CLK, - RST_N, - - server_core_request_put, - EN_server_core_request_put, - RDY_server_core_request_put, - - EN_server_core_response_get, - server_core_response_get, - RDY_server_core_response_get, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get); - input CLK; - input RST_N; - - // action method server_core_request_put - input [201 : 0] server_core_request_put; - input EN_server_core_request_put; - output RDY_server_core_request_put; - - // actionvalue method server_core_response_get - input EN_server_core_response_get; - output [69 : 0] server_core_response_get; - output RDY_server_core_response_get; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // signals for module outputs - wire [69 : 0] server_core_response_get; - wire RDY_server_core_request_put, - RDY_server_core_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get; - - // inlined wires - reg [68 : 0] resWire$wget; - wire crg_done$EN_port0__write, - crg_done$EN_port1__write, - crg_done$port1__read, - crg_done$port2__read, - crg_done_1$EN_port0__write, - crg_done_1$EN_port1__write, - crg_done_1$port1__read, - crg_done_1$port2__read, - resWire$whas; - - // register crg_done - reg crg_done; - wire crg_done$D_IN, crg_done$EN; - - // register crg_done_1 - reg crg_done_1; - wire crg_done_1$D_IN, crg_done_1$EN; - - // register rg_b - reg [115 : 0] rg_b; - wire [115 : 0] rg_b$D_IN; - wire rg_b$EN; - - // register rg_busy - reg rg_busy; - wire rg_busy$D_IN, rg_busy$EN; - - // register rg_busy_1 - reg rg_busy_1; - wire rg_busy_1$D_IN, rg_busy_1$EN; - - // register rg_d - reg [57 : 0] rg_d; - wire [57 : 0] rg_d$D_IN; - wire rg_d$EN; - - // register rg_index - reg [5 : 0] rg_index; - wire [5 : 0] rg_index$D_IN; - wire rg_index$EN; - - // register rg_index_1 - reg [5 : 0] rg_index_1; - wire [5 : 0] rg_index_1$D_IN; - wire rg_index_1$EN; - - // register rg_q - reg [57 : 0] rg_q; - wire [57 : 0] rg_q$D_IN; - wire rg_q$EN; - - // register rg_r - reg [115 : 0] rg_r; - wire [115 : 0] rg_r$D_IN; - wire rg_r$EN; - - // register rg_r_1 - reg [115 : 0] rg_r_1; - wire [115 : 0] rg_r_1$D_IN; - wire rg_r_1$EN; - - // register rg_res - reg [116 : 0] rg_res; - wire [116 : 0] rg_res$D_IN; - wire rg_res$EN; - - // register rg_s - reg [115 : 0] rg_s; - wire [115 : 0] rg_s$D_IN; - wire rg_s$EN; - - // ports of submodule fpu_div64_fOperands_S0 - wire [130 : 0] fpu_div64_fOperands_S0$D_IN, fpu_div64_fOperands_S0$D_OUT; - wire fpu_div64_fOperands_S0$CLR, - fpu_div64_fOperands_S0$DEQ, - fpu_div64_fOperands_S0$EMPTY_N, - fpu_div64_fOperands_S0$ENQ, - fpu_div64_fOperands_S0$FULL_N; - - // ports of submodule fpu_div64_fResult_S5 - wire [68 : 0] fpu_div64_fResult_S5$D_IN, fpu_div64_fResult_S5$D_OUT; - wire fpu_div64_fResult_S5$CLR, - fpu_div64_fResult_S5$DEQ, - fpu_div64_fResult_S5$EMPTY_N, - fpu_div64_fResult_S5$ENQ, - fpu_div64_fResult_S5$FULL_N; - - // ports of submodule fpu_div64_fState_S1 - wire [318 : 0] fpu_div64_fState_S1$D_IN, fpu_div64_fState_S1$D_OUT; - wire fpu_div64_fState_S1$CLR, - fpu_div64_fState_S1$DEQ, - fpu_div64_fState_S1$EMPTY_N, - fpu_div64_fState_S1$ENQ, - fpu_div64_fState_S1$FULL_N; - - // ports of submodule fpu_div64_fState_S2 - wire [147 : 0] fpu_div64_fState_S2$D_IN, fpu_div64_fState_S2$D_OUT; - wire fpu_div64_fState_S2$CLR, - fpu_div64_fState_S2$DEQ, - fpu_div64_fState_S2$EMPTY_N, - fpu_div64_fState_S2$ENQ, - fpu_div64_fState_S2$FULL_N; - - // ports of submodule fpu_div64_fState_S3 - wire [194 : 0] fpu_div64_fState_S3$D_IN, fpu_div64_fState_S3$D_OUT; - wire fpu_div64_fState_S3$CLR, - fpu_div64_fState_S3$DEQ, - fpu_div64_fState_S3$EMPTY_N, - fpu_div64_fState_S3$ENQ, - fpu_div64_fState_S3$FULL_N; - - // ports of submodule fpu_div64_fState_S4 - wire [138 : 0] fpu_div64_fState_S4$D_IN, fpu_div64_fState_S4$D_OUT; - wire fpu_div64_fState_S4$CLR, - fpu_div64_fState_S4$DEQ, - fpu_div64_fState_S4$EMPTY_N, - fpu_div64_fState_S4$ENQ, - fpu_div64_fState_S4$FULL_N; - - // ports of submodule fpu_madd_fOperand_S0 - wire [195 : 0] fpu_madd_fOperand_S0$D_IN, fpu_madd_fOperand_S0$D_OUT; - wire fpu_madd_fOperand_S0$CLR, - fpu_madd_fOperand_S0$DEQ, - fpu_madd_fOperand_S0$EMPTY_N, - fpu_madd_fOperand_S0$ENQ, - fpu_madd_fOperand_S0$FULL_N; - - // ports of submodule fpu_madd_fProd_S2 - wire [105 : 0] fpu_madd_fProd_S2$D_IN, fpu_madd_fProd_S2$D_OUT; - wire fpu_madd_fProd_S2$CLR, - fpu_madd_fProd_S2$DEQ, - fpu_madd_fProd_S2$EMPTY_N, - fpu_madd_fProd_S2$ENQ, - fpu_madd_fProd_S2$FULL_N; - - // ports of submodule fpu_madd_fProd_S3 - wire [105 : 0] fpu_madd_fProd_S3$D_IN, fpu_madd_fProd_S3$D_OUT; - wire fpu_madd_fProd_S3$CLR, - fpu_madd_fProd_S3$DEQ, - fpu_madd_fProd_S3$EMPTY_N, - fpu_madd_fProd_S3$ENQ, - fpu_madd_fProd_S3$FULL_N; - - // ports of submodule fpu_madd_fResult_S9 - wire [68 : 0] fpu_madd_fResult_S9$D_IN, fpu_madd_fResult_S9$D_OUT; - wire fpu_madd_fResult_S9$CLR, - fpu_madd_fResult_S9$DEQ, - fpu_madd_fResult_S9$EMPTY_N, - fpu_madd_fResult_S9$ENQ, - fpu_madd_fResult_S9$FULL_N; - - // ports of submodule fpu_madd_fState_S1 - wire [257 : 0] fpu_madd_fState_S1$D_IN, fpu_madd_fState_S1$D_OUT; - wire fpu_madd_fState_S1$CLR, - fpu_madd_fState_S1$DEQ, - fpu_madd_fState_S1$EMPTY_N, - fpu_madd_fState_S1$ENQ, - fpu_madd_fState_S1$FULL_N; - - // ports of submodule fpu_madd_fState_S2 - wire [151 : 0] fpu_madd_fState_S2$D_IN, fpu_madd_fState_S2$D_OUT; - wire fpu_madd_fState_S2$CLR, - fpu_madd_fState_S2$DEQ, - fpu_madd_fState_S2$EMPTY_N, - fpu_madd_fState_S2$ENQ, - fpu_madd_fState_S2$FULL_N; - - // ports of submodule fpu_madd_fState_S3 - wire [151 : 0] fpu_madd_fState_S3$D_IN, fpu_madd_fState_S3$D_OUT; - wire fpu_madd_fState_S3$CLR, - fpu_madd_fState_S3$DEQ, - fpu_madd_fState_S3$EMPTY_N, - fpu_madd_fState_S3$ENQ, - fpu_madd_fState_S3$FULL_N; - - // ports of submodule fpu_madd_fState_S4 - wire [203 : 0] fpu_madd_fState_S4$D_IN, fpu_madd_fState_S4$D_OUT; - wire fpu_madd_fState_S4$CLR, - fpu_madd_fState_S4$DEQ, - fpu_madd_fState_S4$EMPTY_N, - fpu_madd_fState_S4$ENQ, - fpu_madd_fState_S4$FULL_N; - - // ports of submodule fpu_madd_fState_S5 - wire [215 : 0] fpu_madd_fState_S5$D_IN, fpu_madd_fState_S5$D_OUT; - wire fpu_madd_fState_S5$CLR, - fpu_madd_fState_S5$DEQ, - fpu_madd_fState_S5$EMPTY_N, - fpu_madd_fState_S5$ENQ, - fpu_madd_fState_S5$FULL_N; - - // ports of submodule fpu_madd_fState_S6 - wire [202 : 0] fpu_madd_fState_S6$D_IN, fpu_madd_fState_S6$D_OUT; - wire fpu_madd_fState_S6$CLR, - fpu_madd_fState_S6$DEQ, - fpu_madd_fState_S6$EMPTY_N, - fpu_madd_fState_S6$ENQ, - fpu_madd_fState_S6$FULL_N; - - // ports of submodule fpu_madd_fState_S7 - wire [202 : 0] fpu_madd_fState_S7$D_IN, fpu_madd_fState_S7$D_OUT; - wire fpu_madd_fState_S7$CLR, - fpu_madd_fState_S7$DEQ, - fpu_madd_fState_S7$EMPTY_N, - fpu_madd_fState_S7$ENQ, - fpu_madd_fState_S7$FULL_N; - - // ports of submodule fpu_madd_fState_S8 - wire [140 : 0] fpu_madd_fState_S8$D_IN, fpu_madd_fState_S8$D_OUT; - wire fpu_madd_fState_S8$CLR, - fpu_madd_fState_S8$DEQ, - fpu_madd_fState_S8$EMPTY_N, - fpu_madd_fState_S8$ENQ, - fpu_madd_fState_S8$FULL_N; - - // ports of submodule fpu_sqr64_fOperand_S0 - wire [66 : 0] fpu_sqr64_fOperand_S0$D_IN, fpu_sqr64_fOperand_S0$D_OUT; - wire fpu_sqr64_fOperand_S0$CLR, - fpu_sqr64_fOperand_S0$DEQ, - fpu_sqr64_fOperand_S0$EMPTY_N, - fpu_sqr64_fOperand_S0$ENQ, - fpu_sqr64_fOperand_S0$FULL_N; - - // ports of submodule fpu_sqr64_fResult_S5 - wire [68 : 0] fpu_sqr64_fResult_S5$D_IN, fpu_sqr64_fResult_S5$D_OUT; - wire fpu_sqr64_fResult_S5$CLR, - fpu_sqr64_fResult_S5$DEQ, - fpu_sqr64_fResult_S5$EMPTY_N, - fpu_sqr64_fResult_S5$ENQ, - fpu_sqr64_fResult_S5$FULL_N; - - // ports of submodule fpu_sqr64_fState_S1 - wire [194 : 0] fpu_sqr64_fState_S1$D_IN, fpu_sqr64_fState_S1$D_OUT; - wire fpu_sqr64_fState_S1$CLR, - fpu_sqr64_fState_S1$DEQ, - fpu_sqr64_fState_S1$EMPTY_N, - fpu_sqr64_fState_S1$ENQ, - fpu_sqr64_fState_S1$FULL_N; - - // ports of submodule fpu_sqr64_fState_S2 - wire [136 : 0] fpu_sqr64_fState_S2$D_IN, fpu_sqr64_fState_S2$D_OUT; - wire fpu_sqr64_fState_S2$CLR, - fpu_sqr64_fState_S2$DEQ, - fpu_sqr64_fState_S2$EMPTY_N, - fpu_sqr64_fState_S2$ENQ, - fpu_sqr64_fState_S2$FULL_N; - - // ports of submodule fpu_sqr64_fState_S3 - wire [195 : 0] fpu_sqr64_fState_S3$D_IN, fpu_sqr64_fState_S3$D_OUT; - wire fpu_sqr64_fState_S3$CLR, - fpu_sqr64_fState_S3$DEQ, - fpu_sqr64_fState_S3$EMPTY_N, - fpu_sqr64_fState_S3$ENQ, - fpu_sqr64_fState_S3$FULL_N; - - // ports of submodule fpu_sqr64_fState_S4 - wire [138 : 0] fpu_sqr64_fState_S4$D_IN, fpu_sqr64_fState_S4$D_OUT; - wire fpu_sqr64_fState_S4$CLR, - fpu_sqr64_fState_S4$DEQ, - fpu_sqr64_fState_S4$EMPTY_N, - fpu_sqr64_fState_S4$ENQ, - fpu_sqr64_fState_S4$FULL_N; - - // ports of submodule iFifo - wire [201 : 0] iFifo$D_IN, iFifo$D_OUT; - wire iFifo$CLR, iFifo$DEQ, iFifo$EMPTY_N, iFifo$ENQ, iFifo$FULL_N; - - // ports of submodule isDoubleFifo - wire isDoubleFifo$CLR, - isDoubleFifo$DEQ, - isDoubleFifo$D_IN, - isDoubleFifo$D_OUT, - isDoubleFifo$EMPTY_N, - isDoubleFifo$ENQ, - isDoubleFifo$FULL_N; - - // ports of submodule isNegateFifo - wire isNegateFifo$CLR, - isNegateFifo$DEQ, - isNegateFifo$D_IN, - isNegateFifo$D_OUT, - isNegateFifo$EMPTY_N, - isNegateFifo$ENQ, - isNegateFifo$FULL_N; - - // ports of submodule oFifo - wire [69 : 0] oFifo$D_IN, oFifo$D_OUT; - wire oFifo$CLR, oFifo$DEQ, oFifo$EMPTY_N, oFifo$ENQ, oFifo$FULL_N; - - // ports of submodule resetReqsF - wire resetReqsF$CLR, - resetReqsF$DEQ, - resetReqsF$EMPTY_N, - resetReqsF$ENQ, - resetReqsF$FULL_N; - - // ports of submodule resetRspsF - wire resetRspsF$CLR, - resetRspsF$DEQ, - resetRspsF$EMPTY_N, - resetRspsF$ENQ, - resetRspsF$FULL_N; - - // ports of submodule rmdFifo - wire [2 : 0] rmdFifo$D_IN, rmdFifo$D_OUT; - wire rmdFifo$CLR, rmdFifo$DEQ, rmdFifo$EMPTY_N, rmdFifo$ENQ, rmdFifo$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_fpu_div64_s1_stage, - CAN_FIRE_RL_fpu_div64_s2_stage, - CAN_FIRE_RL_fpu_div64_s3_stage, - CAN_FIRE_RL_fpu_div64_s4_stage, - CAN_FIRE_RL_fpu_div64_s5_stage, - CAN_FIRE_RL_fpu_madd_s1_stage, - CAN_FIRE_RL_fpu_madd_s2_stage, - CAN_FIRE_RL_fpu_madd_s3_stage, - CAN_FIRE_RL_fpu_madd_s4_stage, - CAN_FIRE_RL_fpu_madd_s5_stage, - CAN_FIRE_RL_fpu_madd_s6_stage, - CAN_FIRE_RL_fpu_madd_s7_stage, - CAN_FIRE_RL_fpu_madd_s8_stage, - CAN_FIRE_RL_fpu_madd_s9_stage, - CAN_FIRE_RL_fpu_sqr64_s1_stage, - CAN_FIRE_RL_fpu_sqr64_s2_stage, - CAN_FIRE_RL_fpu_sqr64_s3_stage, - CAN_FIRE_RL_fpu_sqr64_s4_stage, - CAN_FIRE_RL_fpu_sqr64_s5_stage, - CAN_FIRE_RL_getResDiv, - CAN_FIRE_RL_getResMAdd, - CAN_FIRE_RL_getResSqr, - CAN_FIRE_RL_passResult, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_start_op, - CAN_FIRE_RL_work, - CAN_FIRE_RL_work_1, - CAN_FIRE___me_check_22, - CAN_FIRE___me_check_23, - CAN_FIRE_server_core_request_put, - CAN_FIRE_server_core_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_RL_fpu_div64_s1_stage, - WILL_FIRE_RL_fpu_div64_s2_stage, - WILL_FIRE_RL_fpu_div64_s3_stage, - WILL_FIRE_RL_fpu_div64_s4_stage, - WILL_FIRE_RL_fpu_div64_s5_stage, - WILL_FIRE_RL_fpu_madd_s1_stage, - WILL_FIRE_RL_fpu_madd_s2_stage, - WILL_FIRE_RL_fpu_madd_s3_stage, - WILL_FIRE_RL_fpu_madd_s4_stage, - WILL_FIRE_RL_fpu_madd_s5_stage, - WILL_FIRE_RL_fpu_madd_s6_stage, - WILL_FIRE_RL_fpu_madd_s7_stage, - WILL_FIRE_RL_fpu_madd_s8_stage, - WILL_FIRE_RL_fpu_madd_s9_stage, - WILL_FIRE_RL_fpu_sqr64_s1_stage, - WILL_FIRE_RL_fpu_sqr64_s2_stage, - WILL_FIRE_RL_fpu_sqr64_s3_stage, - WILL_FIRE_RL_fpu_sqr64_s4_stage, - WILL_FIRE_RL_fpu_sqr64_s5_stage, - WILL_FIRE_RL_getResDiv, - WILL_FIRE_RL_getResMAdd, - WILL_FIRE_RL_getResSqr, - WILL_FIRE_RL_passResult, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_start_op, - WILL_FIRE_RL_work, - WILL_FIRE_RL_work_1, - WILL_FIRE___me_check_22, - WILL_FIRE___me_check_23, - WILL_FIRE_server_core_request_put, - WILL_FIRE_server_core_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // inputs to muxes for submodule ports - wire [116 : 0] MUX_rg_res$write_1__VAL_2; - wire [115 : 0] MUX_rg_b$write_1__VAL_1, - MUX_rg_b$write_1__VAL_2, - MUX_rg_r$write_1__VAL_1, - MUX_rg_r$write_1__VAL_2, - MUX_rg_r_1$write_1__VAL_2, - MUX_rg_s$write_1__VAL_1, - MUX_rg_s$write_1__VAL_2; - wire [57 : 0] MUX_rg_d$write_1__VAL_1, MUX_rg_q$write_1__VAL_2; - wire [5 : 0] MUX_rg_index$write_1__VAL_2, MUX_rg_index_1$write_1__VAL_2; - wire MUX_crg_done$port1__write_1__SEL_1, - MUX_crg_done$port1__write_1__SEL_2, - MUX_crg_done_1$port1__write_1__SEL_1, - MUX_crg_done_1$port1__write_1__SEL_2; - - // remaining internal signals - reg [63 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183, - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177, - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623; - reg [62 : 0] CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131, - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179; - reg [51 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4, - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110, - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111, - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112, - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113, - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75, - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76, - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77, - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78, - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79, - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80, - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48, - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49, - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50, - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51, - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52, - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53, - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108, - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109, - _theResult___fst_sfd__h142620, - _theResult___fst_sfd__h148292, - _theResult___fst_sfd__h164060, - _theResult___fst_sfd__h173650, - _theResult___fst_sfd__h182402, - _theResult___fst_sfd__h186932, - _theResult___fst_sfd__h19468, - _theResult___fst_sfd__h19957, - _theResult___fst_sfd__h202698, - _theResult___fst_sfd__h212288, - _theResult___fst_sfd__h221040, - _theResult___fst_sfd__h225871, - _theResult___fst_sfd__h241637, - _theResult___fst_sfd__h251227, - _theResult___fst_sfd__h259979, - _theResult___fst_sfd__h43554, - _theResult___fst_sfd__h95988; - reg [22 : 0] CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162, - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163, - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160, - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161, - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164, - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165, - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166, - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167, - _theResult___fst_sfd__h269560, - _theResult___fst_sfd__h278281, - _theResult___fst_sfd__h286863, - _theResult___fst_sfd__h296047, - _theResult___fst_sfd__h304683; - reg [10 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22, - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104, - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105, - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106, - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107, - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69, - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70, - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71, - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72, - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73, - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74, - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42, - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43, - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44, - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45, - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46, - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47, - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102, - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103, - _theResult___fst_exp__h142619, - _theResult___fst_exp__h148291, - _theResult___fst_exp__h164059, - _theResult___fst_exp__h173649, - _theResult___fst_exp__h182401, - _theResult___fst_exp__h186931, - _theResult___fst_exp__h19467, - _theResult___fst_exp__h202697, - _theResult___fst_exp__h212287, - _theResult___fst_exp__h221039, - _theResult___fst_exp__h225870, - _theResult___fst_exp__h241636, - _theResult___fst_exp__h251226, - _theResult___fst_exp__h259978, - _theResult___fst_exp__h43553, - _theResult___fst_exp__h95987; - reg [7 : 0] CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154, - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155, - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152, - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153, - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156, - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157, - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158, - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159, - _theResult___fst_exp__h269559, - _theResult___fst_exp__h278280, - _theResult___fst_exp__h286862, - _theResult___fst_exp__h296046, - _theResult___fst_exp__h304682; - reg CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9, - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126, - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178, - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122, - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116, - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124, - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118, - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87, - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81, - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89, - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83, - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91, - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85, - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54, - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56, - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145, - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144, - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58, - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147, - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146, - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149, - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148, - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120, - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114, - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151, - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348, - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028, - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418; - wire [194 : 0] IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212; - wire [139 : 0] IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595; - wire [118 : 0] IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959; - wire [115 : 0] IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83, - IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22, - IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72, - _theResult___fst__h1476, - _theResult___fst__h1515, - _theResult___fst__h1600, - _theResult___snd_fst__h1478, - _theResult___snd_fst__h1517, - _theResult___snd_fst__h1602, - _theResult___snd_snd__h1649, - _theResult___snd_snd__h1715, - _theResult___snd_snd_snd__h1481, - _theResult___snd_snd_snd__h1520, - _theResult___snd_snd_snd__h1605, - b___1__h77160, - b__h1608, - b__h1712, - b__h32583, - r__h1659, - r__h1663, - r__h1724, - r__h1753, - s__h1658, - s__h1723, - sum__h1606, - sum__h1710, - value__h32541, - x__h85931; - wire [113 : 0] x__h31426; - wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24, - _theResult___fst__h116827, - _theResult___snd__h130966, - _theResult___snd__h130980, - _theResult___snd__h130982, - _theResult___snd__h130994, - _theResult___snd__h131000, - _theResult___snd__h131018, - _theResult___snd__h131023, - fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012, - sfdBC__h115662, - sfdin__h130943, - x__h116896; - wire [68 : 0] IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081; - wire [63 : 0] IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612, - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330, - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555, - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618, - IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657, - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452, - fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936; - wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980, - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065, - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552; - wire [58 : 0] IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19, - _theResult___snd__h94767, - _theResult___snd__h94782, - _theResult___snd__h94784, - _theResult___snd__h94797, - _theResult___snd__h94803, - _theResult___snd__h94821, - _theResult___snd__h94826, - result__h85925, - sfdin__h94744, - x__h86149; - wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12, - IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14, - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10, - _theResult____h32523, - _theResult___snd__h34715, - _theResult___snd__h42350, - _theResult___snd__h42365, - _theResult___snd__h42367, - _theResult___snd__h42380, - _theResult___snd__h42386, - _theResult___snd__h42404, - _theResult___snd__h42409, - _theResult___snd_snd_snd__h33963, - result__h32617, - result__h32648, - result__h32823, - rg_q_PLUS_NEG_INV_rg_q_59_60___d561, - sfd___1__h60702, - sfd__h44951, - sfd__h44953, - sfdin__h34118, - sfdin__h42327, - x__h32762, - x__h33052, - x__h60693; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139, - IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29, - IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100, - IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93, - IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33, - IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40, - IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60, - IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67, - IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135, - IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038, - _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038, - _theResult____h164614, - _theResult____h203252, - _theResult____h242191, - _theResult____h269577, - _theResult____h287214, - _theResult___snd__h141392, - _theResult___snd__h141406, - _theResult___snd__h141408, - _theResult___snd__h141420, - _theResult___snd__h141426, - _theResult___snd__h141444, - _theResult___snd__h141449, - _theResult___snd__h163287, - _theResult___snd__h163289, - _theResult___snd__h163296, - _theResult___snd__h163302, - _theResult___snd__h163325, - _theResult___snd__h172863, - _theResult___snd__h172874, - _theResult___snd__h172876, - _theResult___snd__h172886, - _theResult___snd__h172892, - _theResult___snd__h172915, - _theResult___snd__h181599, - _theResult___snd__h181613, - _theResult___snd__h181619, - _theResult___snd__h181637, - _theResult___snd__h201925, - _theResult___snd__h201927, - _theResult___snd__h201934, - _theResult___snd__h201940, - _theResult___snd__h201963, - _theResult___snd__h211501, - _theResult___snd__h211512, - _theResult___snd__h211514, - _theResult___snd__h211524, - _theResult___snd__h211530, - _theResult___snd__h211553, - _theResult___snd__h220237, - _theResult___snd__h220251, - _theResult___snd__h220257, - _theResult___snd__h220275, - _theResult___snd__h240864, - _theResult___snd__h240866, - _theResult___snd__h240873, - _theResult___snd__h240879, - _theResult___snd__h240902, - _theResult___snd__h250440, - _theResult___snd__h250451, - _theResult___snd__h250453, - _theResult___snd__h250463, - _theResult___snd__h250469, - _theResult___snd__h250492, - _theResult___snd__h259176, - _theResult___snd__h259190, - _theResult___snd__h259196, - _theResult___snd__h259214, - _theResult___snd__h277697, - _theResult___snd__h277708, - _theResult___snd__h277710, - _theResult___snd__h277720, - _theResult___snd__h277726, - _theResult___snd__h277749, - _theResult___snd__h286293, - _theResult___snd__h286295, - _theResult___snd__h286302, - _theResult___snd__h286308, - _theResult___snd__h286331, - _theResult___snd__h295463, - _theResult___snd__h295474, - _theResult___snd__h295476, - _theResult___snd__h295486, - _theResult___snd__h295492, - _theResult___snd__h295515, - _theResult___snd__h304083, - _theResult___snd__h304097, - _theResult___snd__h304103, - _theResult___snd__h304121, - fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615, - guard__h132367, - result__h132372, - result__h165227, - result__h203865, - result__h242804, - result__h287827, - sfdA__h131577, - sfdBC__h131578, - sfd__h133119, - sfd__h144536, - sfd__h183176, - sfd__h222115, - sfd__h261975, - sfdin__h141369, - sfdin__h172846, - sfdin__h211484, - sfdin__h250423, - sfdin__h277680, - sfdin__h295446, - value__h32661, - x__h131940, - x__h131944, - x__h132359, - x__h132871, - x__h132880, - x__h165324, - x__h203962, - x__h242901, - x__h287924, - x__h31487; - wire [53 : 0] sfd__h142040, - sfd__h163354, - sfd__h172944, - sfd__h181672, - sfd__h201992, - sfd__h211582, - sfd__h220310, - sfd__h240931, - sfd__h250521, - sfd__h259249, - sfd__h42982, - sfd__h95416, - value__h270197, - value__h31429, - value__h53174; - wire [52 : 0] sfdA__h2035, - sfdA__h2039, - sfdB__h2036, - sfdB__h2041, - x__h114243, - x__h114255; - wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450, - _theResult___fst_sfd__h164063, - _theResult___fst_sfd__h173653, - _theResult___fst_sfd__h182405, - _theResult___fst_sfd__h182414, - _theResult___fst_sfd__h182420, - _theResult___fst_sfd__h202701, - _theResult___fst_sfd__h212291, - _theResult___fst_sfd__h221043, - _theResult___fst_sfd__h221052, - _theResult___fst_sfd__h221058, - _theResult___fst_sfd__h241640, - _theResult___fst_sfd__h251230, - _theResult___fst_sfd__h259982, - _theResult___fst_sfd__h259991, - _theResult___fst_sfd__h259997, - _theResult___fst_sfd__h43557, - _theResult___fst_sfd__h95991, - _theResult___fst_sfd__h96608, - _theResult___sfd__h142542, - _theResult___sfd__h163982, - _theResult___sfd__h173572, - _theResult___sfd__h182324, - _theResult___sfd__h202620, - _theResult___sfd__h212210, - _theResult___sfd__h220962, - _theResult___sfd__h241559, - _theResult___sfd__h251149, - _theResult___sfd__h259901, - _theResult___sfd__h43476, - _theResult___sfd__h95910, - _theResult___snd_fst_sfd__h144486, - _theResult___snd_fst_sfd__h164066, - _theResult___snd_fst_sfd__h182408, - _theResult___snd_fst_sfd__h183126, - _theResult___snd_fst_sfd__h202704, - _theResult___snd_fst_sfd__h221046, - _theResult___snd_fst_sfd__h222065, - _theResult___snd_fst_sfd__h241643, - _theResult___snd_fst_sfd__h259985, - _theResult___snd_fst_sfd__h31362, - out___1_sfd__h144235, - out___1_sfd__h182875, - out___1_sfd__h221814, - out_sfd__h142545, - out_sfd__h163985, - out_sfd__h173575, - out_sfd__h182327, - out_sfd__h202623, - out_sfd__h212213, - out_sfd__h220965, - out_sfd__h241562, - out_sfd__h251152, - out_sfd__h259904, - out_sfd__h43479, - out_sfd__h95913, - sfd__h18934, - sfd__h18937, - sfd__h45004, - sfd__h99402, - sfd__h99405, - sfd__h99408; - wire [24 : 0] sfd__h277778, - sfd__h286360, - sfd__h295544, - sfd__h304156, - value__h148923, - value__h187561, - value__h226500; - wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576, - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643, - _theResult___fst_sfd__h278284, - _theResult___fst_sfd__h286866, - _theResult___fst_sfd__h296050, - _theResult___fst_sfd__h304686, - _theResult___fst_sfd__h304695, - _theResult___fst_sfd__h304701, - _theResult___sfd__h278203, - _theResult___sfd__h286785, - _theResult___sfd__h295969, - _theResult___sfd__h304605, - _theResult___snd_fst_sfd__h261925, - _theResult___snd_fst_sfd__h286869, - _theResult___snd_fst_sfd__h304689, - out_sfd__h278206, - out_sfd__h286788, - out_sfd__h295972, - out_sfd__h304608, - sfd__h304707; - wire [12 : 0] IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352, - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568, - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195, - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007, - value__h130883, - value__h141307, - value__h31374, - value__h31550, - x__h116929, - x__h132471, - x__h52551, - x__h52569; - wire [11 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106, - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331, - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668, - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17, - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389, - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531, - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809, - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326, - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683, - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034, - x__h165357, - x__h203995, - x__h242934, - x__h287957; - wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433, - IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011, - IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66, - _theResult___exp__h142541, - _theResult___exp__h163981, - _theResult___exp__h173571, - _theResult___exp__h182323, - _theResult___exp__h202619, - _theResult___exp__h212209, - _theResult___exp__h220961, - _theResult___exp__h241558, - _theResult___exp__h251148, - _theResult___exp__h259900, - _theResult___exp__h43475, - _theResult___exp__h95909, - _theResult___fst__h31322, - _theResult___fst_exp__h130949, - _theResult___fst_exp__h130952, - _theResult___fst_exp__h130971, - _theResult___fst_exp__h130986, - _theResult___fst_exp__h131025, - _theResult___fst_exp__h131031, - _theResult___fst_exp__h131034, - _theResult___fst_exp__h141375, - _theResult___fst_exp__h141378, - _theResult___fst_exp__h141397, - _theResult___fst_exp__h141412, - _theResult___fst_exp__h141451, - _theResult___fst_exp__h141457, - _theResult___fst_exp__h141460, - _theResult___fst_exp__h163327, - _theResult___fst_exp__h163333, - _theResult___fst_exp__h163336, - _theResult___fst_exp__h164062, - _theResult___fst_exp__h172852, - _theResult___fst_exp__h172917, - _theResult___fst_exp__h172923, - _theResult___fst_exp__h172926, - _theResult___fst_exp__h173652, - _theResult___fst_exp__h181605, - _theResult___fst_exp__h181644, - _theResult___fst_exp__h181650, - _theResult___fst_exp__h181653, - _theResult___fst_exp__h182404, - _theResult___fst_exp__h182413, - _theResult___fst_exp__h182416, - _theResult___fst_exp__h201965, - _theResult___fst_exp__h201971, - _theResult___fst_exp__h201974, - _theResult___fst_exp__h202700, - _theResult___fst_exp__h211490, - _theResult___fst_exp__h211555, - _theResult___fst_exp__h211561, - _theResult___fst_exp__h211564, - _theResult___fst_exp__h212290, - _theResult___fst_exp__h220243, - _theResult___fst_exp__h220282, - _theResult___fst_exp__h220288, - _theResult___fst_exp__h220291, - _theResult___fst_exp__h221042, - _theResult___fst_exp__h221051, - _theResult___fst_exp__h221054, - _theResult___fst_exp__h240904, - _theResult___fst_exp__h240910, - _theResult___fst_exp__h240913, - _theResult___fst_exp__h241639, - _theResult___fst_exp__h250429, - _theResult___fst_exp__h250494, - _theResult___fst_exp__h250500, - _theResult___fst_exp__h250503, - _theResult___fst_exp__h251229, - _theResult___fst_exp__h259182, - _theResult___fst_exp__h259221, - _theResult___fst_exp__h259227, - _theResult___fst_exp__h259230, - _theResult___fst_exp__h259981, - _theResult___fst_exp__h259990, - _theResult___fst_exp__h259993, - _theResult___fst_exp__h42284, - _theResult___fst_exp__h42287, - _theResult___fst_exp__h42290, - _theResult___fst_exp__h42333, - _theResult___fst_exp__h42336, - _theResult___fst_exp__h42356, - _theResult___fst_exp__h42372, - _theResult___fst_exp__h42411, - _theResult___fst_exp__h42417, - _theResult___fst_exp__h42420, - _theResult___fst_exp__h43556, - _theResult___fst_exp__h94750, - _theResult___fst_exp__h94753, - _theResult___fst_exp__h94773, - _theResult___fst_exp__h94789, - _theResult___fst_exp__h94828, - _theResult___fst_exp__h94834, - _theResult___fst_exp__h94837, - _theResult___fst_exp__h95990, - _theResult___snd_fst_exp__h164065, - _theResult___snd_fst_exp__h182407, - _theResult___snd_fst_exp__h202703, - _theResult___snd_fst_exp__h221045, - _theResult___snd_fst_exp__h241642, - _theResult___snd_fst_exp__h259984, - _theResult___snd_fst_exp__h31334, - _theResult___snd_fst_exp__h31337, - _theResult___snd_fst_exp__h31361, - din_exp30866_MINUS_1023__q23, - din_exp__h130866, - din_inc___2_exp__h142626, - din_inc___2_exp__h182469, - din_inc___2_exp__h182504, - din_inc___2_exp__h182530, - din_inc___2_exp__h221107, - din_inc___2_exp__h221142, - din_inc___2_exp__h221168, - din_inc___2_exp__h260046, - din_inc___2_exp__h260081, - din_inc___2_exp__h260107, - din_inc___2_exp__h43566, - din_inc___2_exp__h96000, - fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7, - fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8, - fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128, - fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129, - fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27, - fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26, - fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16, - fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18, - out_exp__h142544, - out_exp__h163984, - out_exp__h173574, - out_exp__h182326, - out_exp__h202622, - out_exp__h212212, - out_exp__h220964, - out_exp__h241561, - out_exp__h251151, - out_exp__h259903, - out_exp__h43478, - out_exp__h95912, - resWirewget_BITS_67_TO_57_MINUS_1023__q137, - theResult___fst_exp2290_MINUS_1023__q11, - value41307_BITS_10_TO_0_MINUS_1023__q28, - x__h31541, - x__h32769, - x__h96539; - wire [8 : 0] IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332; - wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448, - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141, - _theResult___exp__h278202, - _theResult___exp__h286784, - _theResult___exp__h295968, - _theResult___exp__h304604, - _theResult___fst_exp__h277686, - _theResult___fst_exp__h277751, - _theResult___fst_exp__h277757, - _theResult___fst_exp__h277760, - _theResult___fst_exp__h278283, - _theResult___fst_exp__h286333, - _theResult___fst_exp__h286339, - _theResult___fst_exp__h286342, - _theResult___fst_exp__h286865, - _theResult___fst_exp__h295452, - _theResult___fst_exp__h295517, - _theResult___fst_exp__h295523, - _theResult___fst_exp__h295526, - _theResult___fst_exp__h296049, - _theResult___fst_exp__h304089, - _theResult___fst_exp__h304128, - _theResult___fst_exp__h304134, - _theResult___fst_exp__h304137, - _theResult___fst_exp__h304685, - _theResult___fst_exp__h304694, - _theResult___fst_exp__h304697, - _theResult___snd_fst_exp__h286868, - _theResult___snd_fst_exp__h304688, - din_inc___2_exp__h304723, - din_inc___2_exp__h304749, - din_inc___2_exp__h304784, - din_inc___2_exp__h304810, - exp__h304706, - iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95, - iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35, - iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62, - out_exp__h278205, - out_exp__h286787, - out_exp__h295971, - out_exp__h304607; - wire [6 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460, - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342, - x__h85465; - wire [5 : 0] IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982, - b__h11457, - b__h4039, - x__h60732; - wire [4 : 0] IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926, - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921, - IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688, - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501, - fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942, - fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043, - resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768; - wire [2 : 0] IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523; - wire [1 : 0] IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98, - IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13, - IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25, - IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30, - IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20, - IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65, - IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38, - IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134, - IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140, - IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94, - IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143, - IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101, - IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61, - IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68, - IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34, - IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41, - IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136, - _theResult___snd_fst__h131051, - _theResult___snd_fst__h141477, - _theResult___snd_fst__h42439, - _theResult___snd_fst__h94856, - _theResult___snd_snd__h131371, - _theResult___snd_snd_snd__h131369, - guardBC__h115666, - guard__h133123, - guard__h155375, - guard__h164624, - guard__h173663, - guard__h194013, - guard__h203262, - guard__h212301, - guard__h232952, - guard__h242201, - guard__h251240, - guard__h269587, - guard__h278294, - guard__h287224, - guard__h296060, - guard__h33946, - guard__h86435, - x__h131406, - x__h141760, - x__h42705, - x__h95138; - wire IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025, - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374, - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422, - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521, - IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610, - IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85, - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56, - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44, - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728, - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756, - NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946, - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400, - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481, - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488, - NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923, - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584, - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244, - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955, - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730, - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280, - _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463, - _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883, - _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904, - _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633, - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759, - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107, - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273, - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624, - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984, - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685, - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498, - fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359, - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405, - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857, - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926, - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004, - guard__h165222, - guard__h203860, - guard__h242799, - guard__h287822, - rg_index_1_4_PLUS_1_6_ULE_58___d37, - rg_index_1_4_ULE_58___d38, - rg_index_PLUS_1_ULE_57___d6, - rg_index_ULE_57___d7, - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63, - sfdlsb__h116825, - sfdlsb__h32643, - value_BIT_52___h53270; - - // action method server_core_request_put - assign RDY_server_core_request_put = iFifo$FULL_N ; - assign CAN_FIRE_server_core_request_put = iFifo$FULL_N ; - assign WILL_FIRE_server_core_request_put = EN_server_core_request_put ; - - // actionvalue method server_core_response_get - assign server_core_response_get = oFifo$D_OUT ; - assign RDY_server_core_response_get = oFifo$EMPTY_N ; - assign CAN_FIRE_server_core_response_get = oFifo$EMPTY_N ; - assign WILL_FIRE_server_core_response_get = EN_server_core_response_get ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = resetReqsF$FULL_N ; - assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // submodule fpu_div64_fOperands_S0 - FIFOL1 #(.width(32'd131)) fpu_div64_fOperands_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fOperands_S0$D_IN), - .ENQ(fpu_div64_fOperands_S0$ENQ), - .DEQ(fpu_div64_fOperands_S0$DEQ), - .CLR(fpu_div64_fOperands_S0$CLR), - .D_OUT(fpu_div64_fOperands_S0$D_OUT), - .FULL_N(fpu_div64_fOperands_S0$FULL_N), - .EMPTY_N(fpu_div64_fOperands_S0$EMPTY_N)); - - // submodule fpu_div64_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_div64_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fResult_S5$D_IN), - .ENQ(fpu_div64_fResult_S5$ENQ), - .DEQ(fpu_div64_fResult_S5$DEQ), - .CLR(fpu_div64_fResult_S5$CLR), - .D_OUT(fpu_div64_fResult_S5$D_OUT), - .FULL_N(fpu_div64_fResult_S5$FULL_N), - .EMPTY_N(fpu_div64_fResult_S5$EMPTY_N)); - - // submodule fpu_div64_fState_S1 - FIFOL1 #(.width(32'd319)) fpu_div64_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S1$D_IN), - .ENQ(fpu_div64_fState_S1$ENQ), - .DEQ(fpu_div64_fState_S1$DEQ), - .CLR(fpu_div64_fState_S1$CLR), - .D_OUT(fpu_div64_fState_S1$D_OUT), - .FULL_N(fpu_div64_fState_S1$FULL_N), - .EMPTY_N(fpu_div64_fState_S1$EMPTY_N)); - - // submodule fpu_div64_fState_S2 - FIFOL1 #(.width(32'd148)) fpu_div64_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S2$D_IN), - .ENQ(fpu_div64_fState_S2$ENQ), - .DEQ(fpu_div64_fState_S2$DEQ), - .CLR(fpu_div64_fState_S2$CLR), - .D_OUT(fpu_div64_fState_S2$D_OUT), - .FULL_N(fpu_div64_fState_S2$FULL_N), - .EMPTY_N(fpu_div64_fState_S2$EMPTY_N)); - - // submodule fpu_div64_fState_S3 - FIFOL1 #(.width(32'd195)) fpu_div64_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S3$D_IN), - .ENQ(fpu_div64_fState_S3$ENQ), - .DEQ(fpu_div64_fState_S3$DEQ), - .CLR(fpu_div64_fState_S3$CLR), - .D_OUT(fpu_div64_fState_S3$D_OUT), - .FULL_N(fpu_div64_fState_S3$FULL_N), - .EMPTY_N(fpu_div64_fState_S3$EMPTY_N)); - - // submodule fpu_div64_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_div64_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S4$D_IN), - .ENQ(fpu_div64_fState_S4$ENQ), - .DEQ(fpu_div64_fState_S4$DEQ), - .CLR(fpu_div64_fState_S4$CLR), - .D_OUT(fpu_div64_fState_S4$D_OUT), - .FULL_N(fpu_div64_fState_S4$FULL_N), - .EMPTY_N(fpu_div64_fState_S4$EMPTY_N)); - - // submodule fpu_madd_fOperand_S0 - FIFOL1 #(.width(32'd196)) fpu_madd_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fOperand_S0$D_IN), - .ENQ(fpu_madd_fOperand_S0$ENQ), - .DEQ(fpu_madd_fOperand_S0$DEQ), - .CLR(fpu_madd_fOperand_S0$CLR), - .D_OUT(fpu_madd_fOperand_S0$D_OUT), - .FULL_N(fpu_madd_fOperand_S0$FULL_N), - .EMPTY_N(fpu_madd_fOperand_S0$EMPTY_N)); - - // submodule fpu_madd_fProd_S2 - FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fProd_S2$D_IN), - .ENQ(fpu_madd_fProd_S2$ENQ), - .DEQ(fpu_madd_fProd_S2$DEQ), - .CLR(fpu_madd_fProd_S2$CLR), - .D_OUT(fpu_madd_fProd_S2$D_OUT), - .FULL_N(fpu_madd_fProd_S2$FULL_N), - .EMPTY_N(fpu_madd_fProd_S2$EMPTY_N)); - - // submodule fpu_madd_fProd_S3 - FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fProd_S3$D_IN), - .ENQ(fpu_madd_fProd_S3$ENQ), - .DEQ(fpu_madd_fProd_S3$DEQ), - .CLR(fpu_madd_fProd_S3$CLR), - .D_OUT(fpu_madd_fProd_S3$D_OUT), - .FULL_N(fpu_madd_fProd_S3$FULL_N), - .EMPTY_N(fpu_madd_fProd_S3$EMPTY_N)); - - // submodule fpu_madd_fResult_S9 - FIFOL1 #(.width(32'd69)) fpu_madd_fResult_S9(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fResult_S9$D_IN), - .ENQ(fpu_madd_fResult_S9$ENQ), - .DEQ(fpu_madd_fResult_S9$DEQ), - .CLR(fpu_madd_fResult_S9$CLR), - .D_OUT(fpu_madd_fResult_S9$D_OUT), - .FULL_N(fpu_madd_fResult_S9$FULL_N), - .EMPTY_N(fpu_madd_fResult_S9$EMPTY_N)); - - // submodule fpu_madd_fState_S1 - FIFOL1 #(.width(32'd258)) fpu_madd_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S1$D_IN), - .ENQ(fpu_madd_fState_S1$ENQ), - .DEQ(fpu_madd_fState_S1$DEQ), - .CLR(fpu_madd_fState_S1$CLR), - .D_OUT(fpu_madd_fState_S1$D_OUT), - .FULL_N(fpu_madd_fState_S1$FULL_N), - .EMPTY_N(fpu_madd_fState_S1$EMPTY_N)); - - // submodule fpu_madd_fState_S2 - FIFOL1 #(.width(32'd152)) fpu_madd_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S2$D_IN), - .ENQ(fpu_madd_fState_S2$ENQ), - .DEQ(fpu_madd_fState_S2$DEQ), - .CLR(fpu_madd_fState_S2$CLR), - .D_OUT(fpu_madd_fState_S2$D_OUT), - .FULL_N(fpu_madd_fState_S2$FULL_N), - .EMPTY_N(fpu_madd_fState_S2$EMPTY_N)); - - // submodule fpu_madd_fState_S3 - FIFOL1 #(.width(32'd152)) fpu_madd_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S3$D_IN), - .ENQ(fpu_madd_fState_S3$ENQ), - .DEQ(fpu_madd_fState_S3$DEQ), - .CLR(fpu_madd_fState_S3$CLR), - .D_OUT(fpu_madd_fState_S3$D_OUT), - .FULL_N(fpu_madd_fState_S3$FULL_N), - .EMPTY_N(fpu_madd_fState_S3$EMPTY_N)); - - // submodule fpu_madd_fState_S4 - FIFOL1 #(.width(32'd204)) fpu_madd_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S4$D_IN), - .ENQ(fpu_madd_fState_S4$ENQ), - .DEQ(fpu_madd_fState_S4$DEQ), - .CLR(fpu_madd_fState_S4$CLR), - .D_OUT(fpu_madd_fState_S4$D_OUT), - .FULL_N(fpu_madd_fState_S4$FULL_N), - .EMPTY_N(fpu_madd_fState_S4$EMPTY_N)); - - // submodule fpu_madd_fState_S5 - FIFOL1 #(.width(32'd216)) fpu_madd_fState_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S5$D_IN), - .ENQ(fpu_madd_fState_S5$ENQ), - .DEQ(fpu_madd_fState_S5$DEQ), - .CLR(fpu_madd_fState_S5$CLR), - .D_OUT(fpu_madd_fState_S5$D_OUT), - .FULL_N(fpu_madd_fState_S5$FULL_N), - .EMPTY_N(fpu_madd_fState_S5$EMPTY_N)); - - // submodule fpu_madd_fState_S6 - FIFOL1 #(.width(32'd203)) fpu_madd_fState_S6(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S6$D_IN), - .ENQ(fpu_madd_fState_S6$ENQ), - .DEQ(fpu_madd_fState_S6$DEQ), - .CLR(fpu_madd_fState_S6$CLR), - .D_OUT(fpu_madd_fState_S6$D_OUT), - .FULL_N(fpu_madd_fState_S6$FULL_N), - .EMPTY_N(fpu_madd_fState_S6$EMPTY_N)); - - // submodule fpu_madd_fState_S7 - FIFOL1 #(.width(32'd203)) fpu_madd_fState_S7(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S7$D_IN), - .ENQ(fpu_madd_fState_S7$ENQ), - .DEQ(fpu_madd_fState_S7$DEQ), - .CLR(fpu_madd_fState_S7$CLR), - .D_OUT(fpu_madd_fState_S7$D_OUT), - .FULL_N(fpu_madd_fState_S7$FULL_N), - .EMPTY_N(fpu_madd_fState_S7$EMPTY_N)); - - // submodule fpu_madd_fState_S8 - FIFOL1 #(.width(32'd141)) fpu_madd_fState_S8(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S8$D_IN), - .ENQ(fpu_madd_fState_S8$ENQ), - .DEQ(fpu_madd_fState_S8$DEQ), - .CLR(fpu_madd_fState_S8$CLR), - .D_OUT(fpu_madd_fState_S8$D_OUT), - .FULL_N(fpu_madd_fState_S8$FULL_N), - .EMPTY_N(fpu_madd_fState_S8$EMPTY_N)); - - // submodule fpu_sqr64_fOperand_S0 - FIFOL1 #(.width(32'd67)) fpu_sqr64_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fOperand_S0$D_IN), - .ENQ(fpu_sqr64_fOperand_S0$ENQ), - .DEQ(fpu_sqr64_fOperand_S0$DEQ), - .CLR(fpu_sqr64_fOperand_S0$CLR), - .D_OUT(fpu_sqr64_fOperand_S0$D_OUT), - .FULL_N(fpu_sqr64_fOperand_S0$FULL_N), - .EMPTY_N(fpu_sqr64_fOperand_S0$EMPTY_N)); - - // submodule fpu_sqr64_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_sqr64_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fResult_S5$D_IN), - .ENQ(fpu_sqr64_fResult_S5$ENQ), - .DEQ(fpu_sqr64_fResult_S5$DEQ), - .CLR(fpu_sqr64_fResult_S5$CLR), - .D_OUT(fpu_sqr64_fResult_S5$D_OUT), - .FULL_N(fpu_sqr64_fResult_S5$FULL_N), - .EMPTY_N(fpu_sqr64_fResult_S5$EMPTY_N)); - - // submodule fpu_sqr64_fState_S1 - FIFOL1 #(.width(32'd195)) fpu_sqr64_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S1$D_IN), - .ENQ(fpu_sqr64_fState_S1$ENQ), - .DEQ(fpu_sqr64_fState_S1$DEQ), - .CLR(fpu_sqr64_fState_S1$CLR), - .D_OUT(fpu_sqr64_fState_S1$D_OUT), - .FULL_N(fpu_sqr64_fState_S1$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S1$EMPTY_N)); - - // submodule fpu_sqr64_fState_S2 - FIFOL1 #(.width(32'd137)) fpu_sqr64_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S2$D_IN), - .ENQ(fpu_sqr64_fState_S2$ENQ), - .DEQ(fpu_sqr64_fState_S2$DEQ), - .CLR(fpu_sqr64_fState_S2$CLR), - .D_OUT(fpu_sqr64_fState_S2$D_OUT), - .FULL_N(fpu_sqr64_fState_S2$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S2$EMPTY_N)); - - // submodule fpu_sqr64_fState_S3 - FIFOL1 #(.width(32'd196)) fpu_sqr64_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S3$D_IN), - .ENQ(fpu_sqr64_fState_S3$ENQ), - .DEQ(fpu_sqr64_fState_S3$DEQ), - .CLR(fpu_sqr64_fState_S3$CLR), - .D_OUT(fpu_sqr64_fState_S3$D_OUT), - .FULL_N(fpu_sqr64_fState_S3$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S3$EMPTY_N)); - - // submodule fpu_sqr64_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_sqr64_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S4$D_IN), - .ENQ(fpu_sqr64_fState_S4$ENQ), - .DEQ(fpu_sqr64_fState_S4$DEQ), - .CLR(fpu_sqr64_fState_S4$CLR), - .D_OUT(fpu_sqr64_fState_S4$D_OUT), - .FULL_N(fpu_sqr64_fState_S4$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S4$EMPTY_N)); - - // submodule iFifo - FIFO2 #(.width(32'd202), .guarded(32'd1)) iFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(iFifo$D_IN), - .ENQ(iFifo$ENQ), - .DEQ(iFifo$DEQ), - .CLR(iFifo$CLR), - .D_OUT(iFifo$D_OUT), - .FULL_N(iFifo$FULL_N), - .EMPTY_N(iFifo$EMPTY_N)); - - // submodule isDoubleFifo - FIFO2 #(.width(32'd1), .guarded(32'd1)) isDoubleFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(isDoubleFifo$D_IN), - .ENQ(isDoubleFifo$ENQ), - .DEQ(isDoubleFifo$DEQ), - .CLR(isDoubleFifo$CLR), - .D_OUT(isDoubleFifo$D_OUT), - .FULL_N(isDoubleFifo$FULL_N), - .EMPTY_N(isDoubleFifo$EMPTY_N)); - - // submodule isNegateFifo - FIFO2 #(.width(32'd1), .guarded(32'd1)) isNegateFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(isNegateFifo$D_IN), - .ENQ(isNegateFifo$ENQ), - .DEQ(isNegateFifo$DEQ), - .CLR(isNegateFifo$CLR), - .D_OUT(isNegateFifo$D_OUT), - .FULL_N(isNegateFifo$FULL_N), - .EMPTY_N(isNegateFifo$EMPTY_N)); - - // submodule oFifo - FIFO2 #(.width(32'd70), .guarded(32'd1)) oFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(oFifo$D_IN), - .ENQ(oFifo$ENQ), - .DEQ(oFifo$DEQ), - .CLR(oFifo$CLR), - .D_OUT(oFifo$D_OUT), - .FULL_N(oFifo$FULL_N), - .EMPTY_N(oFifo$EMPTY_N)); - - // submodule resetReqsF - FIFO20 #(.guarded(32'd1)) resetReqsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetReqsF$ENQ), - .DEQ(resetReqsF$DEQ), - .CLR(resetReqsF$CLR), - .FULL_N(resetReqsF$FULL_N), - .EMPTY_N(resetReqsF$EMPTY_N)); - - // submodule resetRspsF - FIFO20 #(.guarded(32'd1)) resetRspsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetRspsF$ENQ), - .DEQ(resetRspsF$DEQ), - .CLR(resetRspsF$CLR), - .FULL_N(resetRspsF$FULL_N), - .EMPTY_N(resetRspsF$EMPTY_N)); - - // submodule rmdFifo - FIFO2 #(.width(32'd3), .guarded(32'd1)) rmdFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rmdFifo$D_IN), - .ENQ(rmdFifo$ENQ), - .DEQ(rmdFifo$DEQ), - .CLR(rmdFifo$CLR), - .D_OUT(rmdFifo$D_OUT), - .FULL_N(rmdFifo$FULL_N), - .EMPTY_N(rmdFifo$EMPTY_N)); - - // rule RL_getResDiv - assign CAN_FIRE_RL_getResDiv = fpu_div64_fResult_S5$EMPTY_N ; - assign WILL_FIRE_RL_getResDiv = fpu_div64_fResult_S5$EMPTY_N ; - - // rule RL_getResSqr - assign CAN_FIRE_RL_getResSqr = fpu_sqr64_fResult_S5$EMPTY_N ; - assign WILL_FIRE_RL_getResSqr = fpu_sqr64_fResult_S5$EMPTY_N ; - - // rule RL_getResMAdd - assign CAN_FIRE_RL_getResMAdd = fpu_madd_fResult_S9$EMPTY_N ; - assign WILL_FIRE_RL_getResMAdd = fpu_madd_fResult_S9$EMPTY_N ; - - // rule __me_check_22 - assign CAN_FIRE___me_check_22 = 1'b1 ; - assign WILL_FIRE___me_check_22 = 1'b1 ; - - // rule __me_check_23 - assign CAN_FIRE___me_check_23 = 1'b1 ; - assign WILL_FIRE___me_check_23 = 1'b1 ; - - // rule RL_passResult - assign CAN_FIRE_RL_passResult = - isDoubleFifo$EMPTY_N && isNegateFifo$EMPTY_N && - rmdFifo$EMPTY_N && - oFifo$FULL_N && - resWire$whas ; - assign WILL_FIRE_RL_passResult = CAN_FIRE_RL_passResult ; - - // rule RL_fpu_div64_s5_stage - assign CAN_FIRE_RL_fpu_div64_s5_stage = - fpu_div64_fState_S4$EMPTY_N && fpu_div64_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s5_stage = CAN_FIRE_RL_fpu_div64_s5_stage ; - - // rule RL_fpu_div64_s4_stage - assign CAN_FIRE_RL_fpu_div64_s4_stage = - fpu_div64_fState_S3$EMPTY_N && fpu_div64_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s4_stage = CAN_FIRE_RL_fpu_div64_s4_stage ; - - // rule RL_fpu_div64_s3_stage - assign CAN_FIRE_RL_fpu_div64_s3_stage = - fpu_div64_fState_S2$EMPTY_N && fpu_div64_fState_S3$FULL_N && - (fpu_div64_fState_S2$D_OUT[147] || crg_done) ; - assign WILL_FIRE_RL_fpu_div64_s3_stage = CAN_FIRE_RL_fpu_div64_s3_stage ; - - // rule RL_work - assign CAN_FIRE_RL_work = rg_busy ; - assign WILL_FIRE_RL_work = rg_busy ; - - // rule RL_fpu_div64_s2_stage - assign CAN_FIRE_RL_fpu_div64_s2_stage = - fpu_div64_fState_S1$EMPTY_N && fpu_div64_fState_S2$FULL_N && - (fpu_div64_fState_S1$D_OUT[318] || !rg_busy) ; - assign WILL_FIRE_RL_fpu_div64_s2_stage = - CAN_FIRE_RL_fpu_div64_s2_stage && !rg_busy ; - - // rule RL_fpu_div64_s1_stage - assign CAN_FIRE_RL_fpu_div64_s1_stage = - fpu_div64_fOperands_S0$EMPTY_N && fpu_div64_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s1_stage = CAN_FIRE_RL_fpu_div64_s1_stage ; - - // rule RL_fpu_sqr64_s5_stage - assign CAN_FIRE_RL_fpu_sqr64_s5_stage = - fpu_sqr64_fState_S4$EMPTY_N && fpu_sqr64_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s5_stage = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - - // rule RL_fpu_sqr64_s4_stage - assign CAN_FIRE_RL_fpu_sqr64_s4_stage = - fpu_sqr64_fState_S3$EMPTY_N && fpu_sqr64_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s4_stage = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - - // rule RL_fpu_sqr64_s3_stage - assign CAN_FIRE_RL_fpu_sqr64_s3_stage = - fpu_sqr64_fState_S2$EMPTY_N && fpu_sqr64_fState_S3$FULL_N && - (fpu_sqr64_fState_S2$D_OUT[136] || crg_done_1) ; - assign WILL_FIRE_RL_fpu_sqr64_s3_stage = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - - // rule RL_work_1 - assign CAN_FIRE_RL_work_1 = rg_busy_1 ; - assign WILL_FIRE_RL_work_1 = rg_busy_1 ; - - // rule RL_fpu_sqr64_s2_stage - assign CAN_FIRE_RL_fpu_sqr64_s2_stage = - fpu_sqr64_fState_S1$EMPTY_N && fpu_sqr64_fState_S2$FULL_N && - (fpu_sqr64_fState_S1$D_OUT[194] || !rg_busy_1) ; - assign WILL_FIRE_RL_fpu_sqr64_s2_stage = - CAN_FIRE_RL_fpu_sqr64_s2_stage && !rg_busy_1 ; - - // rule RL_fpu_sqr64_s1_stage - assign CAN_FIRE_RL_fpu_sqr64_s1_stage = - fpu_sqr64_fOperand_S0$EMPTY_N && fpu_sqr64_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s1_stage = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - - // rule RL_fpu_madd_s9_stage - assign CAN_FIRE_RL_fpu_madd_s9_stage = - fpu_madd_fState_S8$EMPTY_N && fpu_madd_fResult_S9$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s9_stage = CAN_FIRE_RL_fpu_madd_s9_stage ; - - // rule RL_fpu_madd_s8_stage - assign CAN_FIRE_RL_fpu_madd_s8_stage = - fpu_madd_fState_S7$EMPTY_N && fpu_madd_fState_S8$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s8_stage = CAN_FIRE_RL_fpu_madd_s8_stage ; - - // rule RL_fpu_madd_s7_stage - assign CAN_FIRE_RL_fpu_madd_s7_stage = - fpu_madd_fState_S6$EMPTY_N && fpu_madd_fState_S7$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s7_stage = CAN_FIRE_RL_fpu_madd_s7_stage ; - - // rule RL_fpu_madd_s6_stage - assign CAN_FIRE_RL_fpu_madd_s6_stage = - fpu_madd_fState_S5$EMPTY_N && fpu_madd_fState_S6$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s6_stage = CAN_FIRE_RL_fpu_madd_s6_stage ; - - // rule RL_fpu_madd_s5_stage - assign CAN_FIRE_RL_fpu_madd_s5_stage = - fpu_madd_fState_S4$EMPTY_N && fpu_madd_fState_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s5_stage = CAN_FIRE_RL_fpu_madd_s5_stage ; - - // rule RL_fpu_madd_s4_stage - assign CAN_FIRE_RL_fpu_madd_s4_stage = - fpu_madd_fState_S3$EMPTY_N && fpu_madd_fProd_S3$EMPTY_N && - fpu_madd_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s4_stage = CAN_FIRE_RL_fpu_madd_s4_stage ; - - // rule RL_fpu_madd_s3_stage - assign CAN_FIRE_RL_fpu_madd_s3_stage = - fpu_madd_fState_S2$EMPTY_N && fpu_madd_fProd_S2$EMPTY_N && - fpu_madd_fProd_S3$FULL_N && - fpu_madd_fState_S3$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s3_stage = CAN_FIRE_RL_fpu_madd_s3_stage ; - - // rule RL_fpu_madd_s2_stage - assign CAN_FIRE_RL_fpu_madd_s2_stage = - fpu_madd_fState_S1$EMPTY_N && fpu_madd_fProd_S2$FULL_N && - fpu_madd_fState_S2$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s2_stage = CAN_FIRE_RL_fpu_madd_s2_stage ; - - // rule RL_fpu_madd_s1_stage - assign CAN_FIRE_RL_fpu_madd_s1_stage = - fpu_madd_fOperand_S0$EMPTY_N && fpu_madd_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s1_stage = CAN_FIRE_RL_fpu_madd_s1_stage ; - - // rule RL_start_op - assign CAN_FIRE_RL_start_op = - iFifo$EMPTY_N && isDoubleFifo$FULL_N && isNegateFifo$FULL_N && - rmdFifo$FULL_N && - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 ; - assign WILL_FIRE_RL_start_op = CAN_FIRE_RL_start_op ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = resetReqsF$EMPTY_N && resetRspsF$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_crg_done$port1__write_1__SEL_1 = rg_busy && rg_index == 6'd28 ; - assign MUX_crg_done$port1__write_1__SEL_2 = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - assign MUX_crg_done_1$port1__write_1__SEL_1 = - rg_busy_1 && rg_index_1 == 6'd29 ; - assign MUX_crg_done_1$port1__write_1__SEL_2 = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - assign MUX_rg_b$write_1__VAL_1 = - fpu_sqr64_fState_S1$D_OUT[57] ? - 116'h40000000000000000000000000000 : - b___1__h77160 ; - assign MUX_rg_b$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___fst__h1476 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign MUX_rg_d$write_1__VAL_1 = - { 1'd0, fpu_div64_fState_S1$D_OUT[67:11] } ; - assign MUX_rg_index$write_1__VAL_2 = rg_index + 6'd1 ; - assign MUX_rg_index_1$write_1__VAL_2 = rg_index_1 + 6'd1 ; - assign MUX_rg_q$write_1__VAL_2 = - rg_index_PLUS_1_ULE_57___d6 ? - { IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14[56:0], - !IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] } : - IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 ; - assign MUX_rg_r$write_1__VAL_1 = - { 2'd0, fpu_div64_fState_S1$D_OUT[181:68] } ; - assign MUX_rg_r$write_1__VAL_2 = - rg_index_PLUS_1_ULE_57___d6 ? - (IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] ? - { IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0], - 1'd0 } + - b__h32583 : - { IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0], - 1'd0 } - - b__h32583) : - IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 ; - assign MUX_rg_r_1$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___snd_snd_snd__h1481 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 ; - assign MUX_rg_res$write_1__VAL_2 = - { rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44 || - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0 : - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44, - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 } ; - assign MUX_rg_s$write_1__VAL_1 = - { fpu_sqr64_fState_S1$D_OUT[57:0], 58'd0 } ; - assign MUX_rg_s$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___snd_fst__h1478 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 ; - - // inlined wires - always@(fpu_div64_fResult_S5$EMPTY_N or - fpu_div64_fResult_S5$D_OUT or - fpu_sqr64_fResult_S5$EMPTY_N or - fpu_sqr64_fResult_S5$D_OUT or - fpu_madd_fResult_S9$EMPTY_N or fpu_madd_fResult_S9$D_OUT) - begin - case (1'b1) // synopsys parallel_case - fpu_div64_fResult_S5$EMPTY_N: resWire$wget = fpu_div64_fResult_S5$D_OUT; - fpu_sqr64_fResult_S5$EMPTY_N: resWire$wget = fpu_sqr64_fResult_S5$D_OUT; - fpu_madd_fResult_S9$EMPTY_N: resWire$wget = fpu_madd_fResult_S9$D_OUT; - default: resWire$wget = 69'h0AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign resWire$whas = - fpu_div64_fResult_S5$EMPTY_N || fpu_sqr64_fResult_S5$EMPTY_N || - fpu_madd_fResult_S9$EMPTY_N ; - assign crg_done$EN_port0__write = - WILL_FIRE_RL_fpu_div64_s3_stage && - !fpu_div64_fState_S2$D_OUT[147] ; - assign crg_done$port1__read = !crg_done$EN_port0__write && crg_done ; - assign crg_done$EN_port1__write = - rg_busy && rg_index == 6'd28 || - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - assign crg_done$port2__read = - crg_done$EN_port1__write ? - MUX_crg_done$port1__write_1__SEL_1 : - crg_done$port1__read ; - assign crg_done_1$EN_port0__write = - WILL_FIRE_RL_fpu_sqr64_s3_stage && - !fpu_sqr64_fState_S2$D_OUT[136] ; - assign crg_done_1$port1__read = !crg_done_1$EN_port0__write && crg_done_1 ; - assign crg_done_1$EN_port1__write = - rg_busy_1 && rg_index_1 == 6'd29 || - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - assign crg_done_1$port2__read = - crg_done_1$EN_port1__write ? - MUX_crg_done_1$port1__write_1__SEL_1 : - crg_done_1$port1__read ; - - // register crg_done - assign crg_done$D_IN = crg_done$port2__read ; - assign crg_done$EN = 1'b1 ; - - // register crg_done_1 - assign crg_done_1$D_IN = crg_done_1$port2__read ; - assign crg_done_1$EN = 1'b1 ; - - // register rg_b - assign rg_b$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - MUX_rg_b$write_1__VAL_1 : - MUX_rg_b$write_1__VAL_2 ; - assign rg_b$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_busy - assign rg_busy$D_IN = !MUX_crg_done$port1__write_1__SEL_1 ; - assign rg_busy$EN = - rg_busy && rg_index == 6'd28 || - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - - // register rg_busy_1 - assign rg_busy_1$D_IN = !MUX_crg_done_1$port1__write_1__SEL_1 ; - assign rg_busy_1$EN = - rg_busy_1 && rg_index_1 == 6'd29 || - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - - // register rg_d - assign rg_d$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - MUX_rg_d$write_1__VAL_1 : - rg_d ; - assign rg_d$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_index - assign rg_index$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - 6'd0 : - MUX_rg_index$write_1__VAL_2 ; - assign rg_index$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_index_1 - assign rg_index_1$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 6'd0 : - MUX_rg_index_1$write_1__VAL_2 ; - assign rg_index_1$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_q - assign rg_q$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - 58'd0 : - MUX_rg_q$write_1__VAL_2 ; - assign rg_q$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_r - assign rg_r$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - MUX_rg_r$write_1__VAL_1 : - MUX_rg_r$write_1__VAL_2 ; - assign rg_r$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_r_1 - assign rg_r_1$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 116'd0 : - MUX_rg_r_1$write_1__VAL_2 ; - assign rg_r_1$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_res - assign rg_res$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - MUX_rg_res$write_1__VAL_2 ; - assign rg_res$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_s - assign rg_s$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - MUX_rg_s$write_1__VAL_1 : - MUX_rg_s$write_1__VAL_2 ; - assign rg_s$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // submodule fpu_div64_fOperands_S0 - assign fpu_div64_fOperands_S0$D_IN = - { IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330, - iFifo$D_OUT[6:4] } ; - assign fpu_div64_fOperands_S0$ENQ = - WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd3 ; - assign fpu_div64_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_div64_s1_stage ; - assign fpu_div64_fOperands_S0$CLR = 1'b0 ; - - // submodule fpu_div64_fResult_S5 - assign fpu_div64_fResult_S5$D_IN = - fpu_div64_fState_S4$D_OUT[138] ? - fpu_div64_fState_S4$D_OUT[137:69] : - { (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[65:2] : - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173, - fpu_div64_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h43556 == 11'd2047 && - _theResult___fst_sfd__h43557 == 52'd0, - 1'd0, - fpu_div64_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_div64_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_div64_fResult_S5$ENQ = CAN_FIRE_RL_fpu_div64_s5_stage ; - assign fpu_div64_fResult_S5$DEQ = fpu_div64_fResult_S5$EMPTY_N ; - assign fpu_div64_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S1 - assign fpu_div64_fState_S1$D_IN = - { fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363, - (fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118]) ? - { fpu_div64_fOperands_S0$D_OUT[130:119], sfd__h18934 } : - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455, - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0), - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - !IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488, - fpu_div64_fOperands_S0$D_OUT[2:0], - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405, - _theResult___snd_fst_exp__h31361, - _theResult___snd_fst_sfd__h31362, - x__h31426, - x__h31487, - x__h31541 } ; - assign fpu_div64_fState_S1$ENQ = CAN_FIRE_RL_fpu_div64_s1_stage ; - assign fpu_div64_fState_S1$DEQ = WILL_FIRE_RL_fpu_div64_s2_stage ; - assign fpu_div64_fState_S1$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S2 - assign fpu_div64_fState_S2$D_IN = - { fpu_div64_fState_S1$D_OUT[318:182], - fpu_div64_fState_S1$D_OUT[10:0] } ; - assign fpu_div64_fState_S2$ENQ = WILL_FIRE_RL_fpu_div64_s2_stage ; - assign fpu_div64_fState_S2$DEQ = CAN_FIRE_RL_fpu_div64_s3_stage ; - assign fpu_div64_fState_S2$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S3 - assign fpu_div64_fState_S3$D_IN = - { fpu_div64_fState_S2$D_OUT[147:11], x__h33052 } ; - assign fpu_div64_fState_S3$ENQ = CAN_FIRE_RL_fpu_div64_s3_stage ; - assign fpu_div64_fState_S3$DEQ = CAN_FIRE_RL_fpu_div64_s4_stage ; - assign fpu_div64_fState_S3$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S4 - assign fpu_div64_fState_S4$D_IN = - { (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[194] : - fpu_div64_fState_S3$D_OUT[194], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - fpu_div64_fState_S3$D_OUT[193:130] : - { CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174, - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 }) : - fpu_div64_fState_S3$D_OUT[193:130], - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926, - fpu_div64_fState_S3$D_OUT[124:122], - fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936, - x__h42705 } ; - assign fpu_div64_fState_S4$ENQ = CAN_FIRE_RL_fpu_div64_s4_stage ; - assign fpu_div64_fState_S4$DEQ = CAN_FIRE_RL_fpu_div64_s5_stage ; - assign fpu_div64_fState_S4$CLR = 1'b0 ; - - // submodule fpu_madd_fOperand_S0 - assign fpu_madd_fOperand_S0$D_IN = - { iFifo$D_OUT[3:0] != 4'd2, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623, - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176, - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177, - iFifo$D_OUT[6:4] } ; - assign fpu_madd_fOperand_S0$ENQ = - WILL_FIRE_RL_start_op && - (iFifo$D_OUT[3:0] == 4'd0 || iFifo$D_OUT[3:0] == 4'd1 || - iFifo$D_OUT[3:0] == 4'd2 || - iFifo$D_OUT[3:0] == 4'd5 || - iFifo$D_OUT[3:0] == 4'd6 || - iFifo$D_OUT[3:0] == 4'd7 || - iFifo$D_OUT[3:0] == 4'd8) ; - assign fpu_madd_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_madd_s1_stage ; - assign fpu_madd_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_madd_fProd_S2 - assign fpu_madd_fProd_S2$D_IN = - fpu_madd_fState_S1$D_OUT[105:53] * - fpu_madd_fState_S1$D_OUT[52:0] ; - assign fpu_madd_fProd_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fProd_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fProd_S2$CLR = 1'b0 ; - - // submodule fpu_madd_fProd_S3 - assign fpu_madd_fProd_S3$D_IN = fpu_madd_fProd_S2$D_OUT ; - assign fpu_madd_fProd_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fProd_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fProd_S3$CLR = 1'b0 ; - - // submodule fpu_madd_fResult_S9 - assign fpu_madd_fResult_S9$D_IN = - fpu_madd_fState_S8$D_OUT[140] ? - fpu_madd_fState_S8$D_OUT[139:71] : - IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 ; - assign fpu_madd_fResult_S9$ENQ = CAN_FIRE_RL_fpu_madd_s9_stage ; - assign fpu_madd_fResult_S9$DEQ = fpu_madd_fResult_S9$EMPTY_N ; - assign fpu_madd_fResult_S9$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S1 - assign fpu_madd_fState_S1$D_IN = - { x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54] || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947, - 4'd0, - fpu_madd_fOperand_S0$D_OUT[2:0], - fpu_madd_fOperand_S0$D_OUT[195], - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911, - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 } ; - assign fpu_madd_fState_S1$ENQ = CAN_FIRE_RL_fpu_madd_s1_stage ; - assign fpu_madd_fState_S1$DEQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fState_S1$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S2 - assign fpu_madd_fState_S2$D_IN = fpu_madd_fState_S1$D_OUT[257:106] ; - assign fpu_madd_fState_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fState_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fState_S2$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S3 - assign fpu_madd_fState_S3$D_IN = fpu_madd_fState_S2$D_OUT ; - assign fpu_madd_fState_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fState_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fState_S3$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S4 - assign fpu_madd_fState_S4$D_IN = - { fpu_madd_fState_S3$D_OUT[151:87], - IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525, - fpu_madd_fState_S3$D_OUT[81:14], - !fpu_madd_fState_S3$D_OUT[151] && fpu_madd_fState_S3$D_OUT[13], - fpu_madd_fState_S3$D_OUT[151] ? - 63'd0 : - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536, - x__h131406 } ; - assign fpu_madd_fState_S4$ENQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fState_S4$DEQ = CAN_FIRE_RL_fpu_madd_s5_stage ; - assign fpu_madd_fState_S4$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S5 - assign fpu_madd_fState_S5$D_IN = - { fpu_madd_fState_S4$D_OUT[203:130], - fpu_madd_fState_S4$D_OUT[129] != fpu_madd_fState_S4$D_OUT[65], - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - fpu_madd_fState_S4$D_OUT[65] : - fpu_madd_fState_S4$D_OUT[129], - IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 } ; - assign fpu_madd_fState_S5$ENQ = CAN_FIRE_RL_fpu_madd_s5_stage ; - assign fpu_madd_fState_S5$DEQ = CAN_FIRE_RL_fpu_madd_s6_stage ; - assign fpu_madd_fState_S5$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S6 - assign fpu_madd_fState_S6$D_IN = - { fpu_madd_fState_S5$D_OUT[215:127], - fpu_madd_fState_S5$D_OUT[113:57], - x__h132359 } ; - assign fpu_madd_fState_S6$ENQ = CAN_FIRE_RL_fpu_madd_s6_stage ; - assign fpu_madd_fState_S6$DEQ = CAN_FIRE_RL_fpu_madd_s7_stage ; - assign fpu_madd_fState_S6$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S7 - assign fpu_madd_fState_S7$D_IN = - { fpu_madd_fState_S6$D_OUT[202:114], x__h132871, x__h132880 } ; - assign fpu_madd_fState_S7$ENQ = CAN_FIRE_RL_fpu_madd_s7_stage ; - assign fpu_madd_fState_S7$DEQ = CAN_FIRE_RL_fpu_madd_s8_stage ; - assign fpu_madd_fState_S7$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S8 - assign fpu_madd_fState_S8$D_IN = - { fpu_madd_fState_S7$D_OUT[202:138], - fpu_madd_fState_S7$D_OUT[202] ? - fpu_madd_fState_S7$D_OUT[137:133] : - fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942, - fpu_madd_fState_S7$D_OUT[132:129], - !fpu_madd_fState_S7$D_OUT[202] && - fpu_madd_fState_S7$D_OUT[127], - fpu_madd_fState_S7$D_OUT[202] ? - 63'd0 : - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952, - x__h141760, - fpu_madd_fState_S7$D_OUT[128] } ; - assign fpu_madd_fState_S8$ENQ = CAN_FIRE_RL_fpu_madd_s8_stage ; - assign fpu_madd_fState_S8$DEQ = CAN_FIRE_RL_fpu_madd_s9_stage ; - assign fpu_madd_fState_S8$CLR = 1'b0 ; - - // submodule fpu_sqr64_fOperand_S0 - assign fpu_sqr64_fOperand_S0$D_IN = - { IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - iFifo$D_OUT[6:4] } ; - assign fpu_sqr64_fOperand_S0$ENQ = - WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd4 ; - assign fpu_sqr64_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - assign fpu_sqr64_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_sqr64_fResult_S5 - assign fpu_sqr64_fResult_S5$D_IN = - fpu_sqr64_fState_S4$D_OUT[138] ? - fpu_sqr64_fState_S4$D_OUT[137:69] : - { (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[65:2] : - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183, - fpu_sqr64_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h95990 == 11'd2047 && - _theResult___fst_sfd__h95991 == 52'd0, - 1'd0, - fpu_sqr64_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_sqr64_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_sqr64_fResult_S5$ENQ = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - assign fpu_sqr64_fResult_S5$DEQ = fpu_sqr64_fResult_S5$EMPTY_N ; - assign fpu_sqr64_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S1 - assign fpu_sqr64_fState_S1$D_IN = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_sqr64_fOperand_S0$D_OUT[54]) ? - { 1'd1, - fpu_sqr64_fOperand_S0$D_OUT[66:55], - sfd__h45004, - 130'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212 ; - assign fpu_sqr64_fState_S1$ENQ = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - assign fpu_sqr64_fState_S1$DEQ = WILL_FIRE_RL_fpu_sqr64_s2_stage ; - assign fpu_sqr64_fState_S1$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S2 - assign fpu_sqr64_fState_S2$D_IN = fpu_sqr64_fState_S1$D_OUT[194:58] ; - assign fpu_sqr64_fState_S2$ENQ = WILL_FIRE_RL_fpu_sqr64_s2_stage ; - assign fpu_sqr64_fState_S2$DEQ = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - assign fpu_sqr64_fState_S2$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S3 - assign fpu_sqr64_fState_S3$D_IN = { fpu_sqr64_fState_S2$D_OUT, x__h86149 } ; - assign fpu_sqr64_fState_S3$ENQ = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - assign fpu_sqr64_fState_S3$DEQ = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - assign fpu_sqr64_fState_S3$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S4 - assign fpu_sqr64_fState_S4$D_IN = - { fpu_sqr64_fState_S3$D_OUT[195:131], - fpu_sqr64_fState_S3$D_OUT[195] && - fpu_sqr64_fState_S3$D_OUT[130], - fpu_sqr64_fState_S3$D_OUT[195] && - fpu_sqr64_fState_S3$D_OUT[129], - IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671, - fpu_sqr64_fState_S3$D_OUT[125:122], - fpu_sqr64_fState_S3$D_OUT[195] ? - fpu_sqr64_fState_S3$D_OUT[121:59] : - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678, - x__h95138 } ; - assign fpu_sqr64_fState_S4$ENQ = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - assign fpu_sqr64_fState_S4$DEQ = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - assign fpu_sqr64_fState_S4$CLR = 1'b0 ; - - // submodule iFifo - assign iFifo$D_IN = server_core_request_put ; - assign iFifo$ENQ = EN_server_core_request_put ; - assign iFifo$DEQ = CAN_FIRE_RL_start_op ; - assign iFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule isDoubleFifo - assign isDoubleFifo$D_IN = !iFifo$D_OUT[201] ; - assign isDoubleFifo$ENQ = CAN_FIRE_RL_start_op ; - assign isDoubleFifo$DEQ = CAN_FIRE_RL_passResult ; - assign isDoubleFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule isNegateFifo - assign isNegateFifo$D_IN = - iFifo$D_OUT[3:0] == 4'd7 || iFifo$D_OUT[3:0] == 4'd8 ; - assign isNegateFifo$ENQ = CAN_FIRE_RL_start_op ; - assign isNegateFifo$DEQ = CAN_FIRE_RL_passResult ; - assign isNegateFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule oFifo - assign oFifo$D_IN = - { !isDoubleFifo$D_OUT, - IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657, - isDoubleFifo$D_OUT ? - resWire$wget[4:0] : - resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 } ; - assign oFifo$ENQ = CAN_FIRE_RL_passResult ; - assign oFifo$DEQ = EN_server_core_response_get ; - assign oFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule resetReqsF - assign resetReqsF$ENQ = EN_server_reset_request_put ; - assign resetReqsF$DEQ = CAN_FIRE_RL_rl_reset ; - assign resetReqsF$CLR = 1'b0 ; - - // submodule resetRspsF - assign resetRspsF$ENQ = CAN_FIRE_RL_rl_reset ; - assign resetRspsF$DEQ = EN_server_reset_response_get ; - assign resetRspsF$CLR = 1'b0 ; - - // submodule rmdFifo - assign rmdFifo$D_IN = iFifo$D_OUT[6:4] ; - assign rmdFifo$ENQ = CAN_FIRE_RL_start_op ; - assign rmdFifo$DEQ = CAN_FIRE_RL_passResult ; - assign rmdFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 ? - _theResult___snd__h277749 : - _theResult____h269577 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 ? - _theResult___snd__h172915 : - _theResult____h164614 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 ? - _theResult___snd__h250492 : - _theResult____h242191 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 ? - _theResult___snd__h211553 : - _theResult____h203252 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 ? - _theResult___snd__h295515 : - _theResult____h287214 ; - assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24 = - _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 ? - _theResult___snd__h131023 : - _theResult___snd__h131018 ; - assign IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12 = - _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883 ? - _theResult___snd__h42409 : - _theResult___snd__h42404 ; - assign IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29 = - _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 ? - _theResult___snd__h141449 : - _theResult___snd__h141444 ; - assign IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19 = - _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633 ? - _theResult___snd__h94826 : - _theResult___snd__h94821 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100 = - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 ? - _theResult___snd__h201963 : - _theResult___snd__h220275 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93 = - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 ? - _theResult___snd__h201963 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33 = - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 ? - _theResult___snd__h163325 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40 = - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 ? - _theResult___snd__h163325 : - _theResult___snd__h181637 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60 = - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 ? - _theResult___snd__h240902 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67 = - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 ? - _theResult___snd__h240902 : - _theResult___snd__h259214 ; - assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135 = - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 ? - _theResult___snd__h286331 : - 57'd0 ; - assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142 = - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 ? - _theResult___snd__h286331 : - _theResult___snd__h304121 ; - assign IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h43566, sfd__h42982[52:1] }) : - { IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977, - sfd__h42982[51:0] } ; - assign IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h142626, sfd__h142040[52:1] }) : - { IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986, - sfd__h142040[51:0] } ; - assign IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h96000, sfd__h95416[52:1] }) : - { IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721, - sfd__h95416[51:0] } ; - assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - ((_theResult___fst_exp__h277686 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823) : - ((_theResult___fst_exp__h286342 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023) ; - assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - ((_theResult___fst_exp__h277686 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388) : - ((_theResult___fst_exp__h286342 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[168] : - ((_theResult___fst_exp__h163336 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[38] : - ((_theResult___fst_exp__h240913 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 && - iFifo$D_OUT[6:4] != 3'd2 && - iFifo$D_OUT[6:4] != 3'd3 && - iFifo$D_OUT[6:4] != 3'd4 || - !iFifo$D_OUT[38] : - ((_theResult___fst_exp__h240913 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[103] : - ((_theResult___fst_exp__h201974 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 && - iFifo$D_OUT[6:4] != 3'd2 && - iFifo$D_OUT[6:4] != 3'd3 && - iFifo$D_OUT[6:4] != 3'd4 || - !iFifo$D_OUT[103] : - ((_theResult___fst_exp__h201974 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121) ; - assign IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 = - (_theResult____h269577[56] ? - 6'd0 : - (_theResult____h269577[55] ? - 6'd1 : - (_theResult____h269577[54] ? - 6'd2 : - (_theResult____h269577[53] ? - 6'd3 : - (_theResult____h269577[52] ? - 6'd4 : - (_theResult____h269577[51] ? - 6'd5 : - (_theResult____h269577[50] ? - 6'd6 : - (_theResult____h269577[49] ? - 6'd7 : - (_theResult____h269577[48] ? - 6'd8 : - (_theResult____h269577[47] ? - 6'd9 : - (_theResult____h269577[46] ? - 6'd10 : - (_theResult____h269577[45] ? - 6'd11 : - (_theResult____h269577[44] ? - 6'd12 : - (_theResult____h269577[43] ? - 6'd13 : - (_theResult____h269577[42] ? - 6'd14 : - (_theResult____h269577[41] ? - 6'd15 : - (_theResult____h269577[40] ? - 6'd16 : - (_theResult____h269577[39] ? - 6'd17 : - (_theResult____h269577[38] ? - 6'd18 : - (_theResult____h269577[37] ? - 6'd19 : - (_theResult____h269577[36] ? - 6'd20 : - (_theResult____h269577[35] ? - 6'd21 : - (_theResult____h269577[34] ? - 6'd22 : - (_theResult____h269577[33] ? - 6'd23 : - (_theResult____h269577[32] ? - 6'd24 : - (_theResult____h269577[31] ? - 6'd25 : - (_theResult____h269577[30] ? - 6'd26 : - (_theResult____h269577[29] ? - 6'd27 : - (_theResult____h269577[28] ? - 6'd28 : - (_theResult____h269577[27] ? - 6'd29 : - (_theResult____h269577[26] ? - 6'd30 : - (_theResult____h269577[25] ? - 6'd31 : - (_theResult____h269577[24] ? - 6'd32 : - (_theResult____h269577[23] ? - 6'd33 : - (_theResult____h269577[22] ? - 6'd34 : - (_theResult____h269577[21] ? - 6'd35 : - (_theResult____h269577[20] ? - 6'd36 : - (_theResult____h269577[19] ? - 6'd37 : - (_theResult____h269577[18] ? - 6'd38 : - (_theResult____h269577[17] ? - 6'd39 : - (_theResult____h269577[16] ? - 6'd40 : - (_theResult____h269577[15] ? - 6'd41 : - (_theResult____h269577[14] ? - 6'd42 : - (_theResult____h269577[13] ? - 6'd43 : - (_theResult____h269577[12] ? - 6'd44 : - (_theResult____h269577[11] ? - 6'd45 : - (_theResult____h269577[10] ? - 6'd46 : - (_theResult____h269577[9] ? - 6'd47 : - (_theResult____h269577[8] ? - 6'd48 : - (_theResult____h269577[7] ? - 6'd49 : - (_theResult____h269577[6] ? - 6'd50 : - (_theResult____h269577[5] ? - 6'd51 : - (_theResult____h269577[4] ? - 6'd52 : - (_theResult____h269577[3] ? - 6'd53 : - (_theResult____h269577[2] ? - 6'd54 : - (_theResult____h269577[1] ? - 6'd55 : - (_theResult____h269577[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 = - (_theResult____h203252[56] ? - 6'd0 : - (_theResult____h203252[55] ? - 6'd1 : - (_theResult____h203252[54] ? - 6'd2 : - (_theResult____h203252[53] ? - 6'd3 : - (_theResult____h203252[52] ? - 6'd4 : - (_theResult____h203252[51] ? - 6'd5 : - (_theResult____h203252[50] ? - 6'd6 : - (_theResult____h203252[49] ? - 6'd7 : - (_theResult____h203252[48] ? - 6'd8 : - (_theResult____h203252[47] ? - 6'd9 : - (_theResult____h203252[46] ? - 6'd10 : - (_theResult____h203252[45] ? - 6'd11 : - (_theResult____h203252[44] ? - 6'd12 : - (_theResult____h203252[43] ? - 6'd13 : - (_theResult____h203252[42] ? - 6'd14 : - (_theResult____h203252[41] ? - 6'd15 : - (_theResult____h203252[40] ? - 6'd16 : - (_theResult____h203252[39] ? - 6'd17 : - (_theResult____h203252[38] ? - 6'd18 : - (_theResult____h203252[37] ? - 6'd19 : - (_theResult____h203252[36] ? - 6'd20 : - (_theResult____h203252[35] ? - 6'd21 : - (_theResult____h203252[34] ? - 6'd22 : - (_theResult____h203252[33] ? - 6'd23 : - (_theResult____h203252[32] ? - 6'd24 : - (_theResult____h203252[31] ? - 6'd25 : - (_theResult____h203252[30] ? - 6'd26 : - (_theResult____h203252[29] ? - 6'd27 : - (_theResult____h203252[28] ? - 6'd28 : - (_theResult____h203252[27] ? - 6'd29 : - (_theResult____h203252[26] ? - 6'd30 : - (_theResult____h203252[25] ? - 6'd31 : - (_theResult____h203252[24] ? - 6'd32 : - (_theResult____h203252[23] ? - 6'd33 : - (_theResult____h203252[22] ? - 6'd34 : - (_theResult____h203252[21] ? - 6'd35 : - (_theResult____h203252[20] ? - 6'd36 : - (_theResult____h203252[19] ? - 6'd37 : - (_theResult____h203252[18] ? - 6'd38 : - (_theResult____h203252[17] ? - 6'd39 : - (_theResult____h203252[16] ? - 6'd40 : - (_theResult____h203252[15] ? - 6'd41 : - (_theResult____h203252[14] ? - 6'd42 : - (_theResult____h203252[13] ? - 6'd43 : - (_theResult____h203252[12] ? - 6'd44 : - (_theResult____h203252[11] ? - 6'd45 : - (_theResult____h203252[10] ? - 6'd46 : - (_theResult____h203252[9] ? - 6'd47 : - (_theResult____h203252[8] ? - 6'd48 : - (_theResult____h203252[7] ? - 6'd49 : - (_theResult____h203252[6] ? - 6'd50 : - (_theResult____h203252[5] ? - 6'd51 : - (_theResult____h203252[4] ? - 6'd52 : - (_theResult____h203252[3] ? - 6'd53 : - (_theResult____h203252[2] ? - 6'd54 : - (_theResult____h203252[1] ? - 6'd55 : - (_theResult____h203252[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 = - (_theResult____h164614[56] ? - 6'd0 : - (_theResult____h164614[55] ? - 6'd1 : - (_theResult____h164614[54] ? - 6'd2 : - (_theResult____h164614[53] ? - 6'd3 : - (_theResult____h164614[52] ? - 6'd4 : - (_theResult____h164614[51] ? - 6'd5 : - (_theResult____h164614[50] ? - 6'd6 : - (_theResult____h164614[49] ? - 6'd7 : - (_theResult____h164614[48] ? - 6'd8 : - (_theResult____h164614[47] ? - 6'd9 : - (_theResult____h164614[46] ? - 6'd10 : - (_theResult____h164614[45] ? - 6'd11 : - (_theResult____h164614[44] ? - 6'd12 : - (_theResult____h164614[43] ? - 6'd13 : - (_theResult____h164614[42] ? - 6'd14 : - (_theResult____h164614[41] ? - 6'd15 : - (_theResult____h164614[40] ? - 6'd16 : - (_theResult____h164614[39] ? - 6'd17 : - (_theResult____h164614[38] ? - 6'd18 : - (_theResult____h164614[37] ? - 6'd19 : - (_theResult____h164614[36] ? - 6'd20 : - (_theResult____h164614[35] ? - 6'd21 : - (_theResult____h164614[34] ? - 6'd22 : - (_theResult____h164614[33] ? - 6'd23 : - (_theResult____h164614[32] ? - 6'd24 : - (_theResult____h164614[31] ? - 6'd25 : - (_theResult____h164614[30] ? - 6'd26 : - (_theResult____h164614[29] ? - 6'd27 : - (_theResult____h164614[28] ? - 6'd28 : - (_theResult____h164614[27] ? - 6'd29 : - (_theResult____h164614[26] ? - 6'd30 : - (_theResult____h164614[25] ? - 6'd31 : - (_theResult____h164614[24] ? - 6'd32 : - (_theResult____h164614[23] ? - 6'd33 : - (_theResult____h164614[22] ? - 6'd34 : - (_theResult____h164614[21] ? - 6'd35 : - (_theResult____h164614[20] ? - 6'd36 : - (_theResult____h164614[19] ? - 6'd37 : - (_theResult____h164614[18] ? - 6'd38 : - (_theResult____h164614[17] ? - 6'd39 : - (_theResult____h164614[16] ? - 6'd40 : - (_theResult____h164614[15] ? - 6'd41 : - (_theResult____h164614[14] ? - 6'd42 : - (_theResult____h164614[13] ? - 6'd43 : - (_theResult____h164614[12] ? - 6'd44 : - (_theResult____h164614[11] ? - 6'd45 : - (_theResult____h164614[10] ? - 6'd46 : - (_theResult____h164614[9] ? - 6'd47 : - (_theResult____h164614[8] ? - 6'd48 : - (_theResult____h164614[7] ? - 6'd49 : - (_theResult____h164614[6] ? - 6'd50 : - (_theResult____h164614[5] ? - 6'd51 : - (_theResult____h164614[4] ? - 6'd52 : - (_theResult____h164614[3] ? - 6'd53 : - (_theResult____h164614[2] ? - 6'd54 : - (_theResult____h164614[1] ? - 6'd55 : - (_theResult____h164614[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 = - (_theResult____h242191[56] ? - 6'd0 : - (_theResult____h242191[55] ? - 6'd1 : - (_theResult____h242191[54] ? - 6'd2 : - (_theResult____h242191[53] ? - 6'd3 : - (_theResult____h242191[52] ? - 6'd4 : - (_theResult____h242191[51] ? - 6'd5 : - (_theResult____h242191[50] ? - 6'd6 : - (_theResult____h242191[49] ? - 6'd7 : - (_theResult____h242191[48] ? - 6'd8 : - (_theResult____h242191[47] ? - 6'd9 : - (_theResult____h242191[46] ? - 6'd10 : - (_theResult____h242191[45] ? - 6'd11 : - (_theResult____h242191[44] ? - 6'd12 : - (_theResult____h242191[43] ? - 6'd13 : - (_theResult____h242191[42] ? - 6'd14 : - (_theResult____h242191[41] ? - 6'd15 : - (_theResult____h242191[40] ? - 6'd16 : - (_theResult____h242191[39] ? - 6'd17 : - (_theResult____h242191[38] ? - 6'd18 : - (_theResult____h242191[37] ? - 6'd19 : - (_theResult____h242191[36] ? - 6'd20 : - (_theResult____h242191[35] ? - 6'd21 : - (_theResult____h242191[34] ? - 6'd22 : - (_theResult____h242191[33] ? - 6'd23 : - (_theResult____h242191[32] ? - 6'd24 : - (_theResult____h242191[31] ? - 6'd25 : - (_theResult____h242191[30] ? - 6'd26 : - (_theResult____h242191[29] ? - 6'd27 : - (_theResult____h242191[28] ? - 6'd28 : - (_theResult____h242191[27] ? - 6'd29 : - (_theResult____h242191[26] ? - 6'd30 : - (_theResult____h242191[25] ? - 6'd31 : - (_theResult____h242191[24] ? - 6'd32 : - (_theResult____h242191[23] ? - 6'd33 : - (_theResult____h242191[22] ? - 6'd34 : - (_theResult____h242191[21] ? - 6'd35 : - (_theResult____h242191[20] ? - 6'd36 : - (_theResult____h242191[19] ? - 6'd37 : - (_theResult____h242191[18] ? - 6'd38 : - (_theResult____h242191[17] ? - 6'd39 : - (_theResult____h242191[16] ? - 6'd40 : - (_theResult____h242191[15] ? - 6'd41 : - (_theResult____h242191[14] ? - 6'd42 : - (_theResult____h242191[13] ? - 6'd43 : - (_theResult____h242191[12] ? - 6'd44 : - (_theResult____h242191[11] ? - 6'd45 : - (_theResult____h242191[10] ? - 6'd46 : - (_theResult____h242191[9] ? - 6'd47 : - (_theResult____h242191[8] ? - 6'd48 : - (_theResult____h242191[7] ? - 6'd49 : - (_theResult____h242191[6] ? - 6'd50 : - (_theResult____h242191[5] ? - 6'd51 : - (_theResult____h242191[4] ? - 6'd52 : - (_theResult____h242191[3] ? - 6'd53 : - (_theResult____h242191[2] ? - 6'd54 : - (_theResult____h242191[1] ? - 6'd55 : - (_theResult____h242191[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 = - (_theResult____h287214[56] ? - 6'd0 : - (_theResult____h287214[55] ? - 6'd1 : - (_theResult____h287214[54] ? - 6'd2 : - (_theResult____h287214[53] ? - 6'd3 : - (_theResult____h287214[52] ? - 6'd4 : - (_theResult____h287214[51] ? - 6'd5 : - (_theResult____h287214[50] ? - 6'd6 : - (_theResult____h287214[49] ? - 6'd7 : - (_theResult____h287214[48] ? - 6'd8 : - (_theResult____h287214[47] ? - 6'd9 : - (_theResult____h287214[46] ? - 6'd10 : - (_theResult____h287214[45] ? - 6'd11 : - (_theResult____h287214[44] ? - 6'd12 : - (_theResult____h287214[43] ? - 6'd13 : - (_theResult____h287214[42] ? - 6'd14 : - (_theResult____h287214[41] ? - 6'd15 : - (_theResult____h287214[40] ? - 6'd16 : - (_theResult____h287214[39] ? - 6'd17 : - (_theResult____h287214[38] ? - 6'd18 : - (_theResult____h287214[37] ? - 6'd19 : - (_theResult____h287214[36] ? - 6'd20 : - (_theResult____h287214[35] ? - 6'd21 : - (_theResult____h287214[34] ? - 6'd22 : - (_theResult____h287214[33] ? - 6'd23 : - (_theResult____h287214[32] ? - 6'd24 : - (_theResult____h287214[31] ? - 6'd25 : - (_theResult____h287214[30] ? - 6'd26 : - (_theResult____h287214[29] ? - 6'd27 : - (_theResult____h287214[28] ? - 6'd28 : - (_theResult____h287214[27] ? - 6'd29 : - (_theResult____h287214[26] ? - 6'd30 : - (_theResult____h287214[25] ? - 6'd31 : - (_theResult____h287214[24] ? - 6'd32 : - (_theResult____h287214[23] ? - 6'd33 : - (_theResult____h287214[22] ? - 6'd34 : - (_theResult____h287214[21] ? - 6'd35 : - (_theResult____h287214[20] ? - 6'd36 : - (_theResult____h287214[19] ? - 6'd37 : - (_theResult____h287214[18] ? - 6'd38 : - (_theResult____h287214[17] ? - 6'd39 : - (_theResult____h287214[16] ? - 6'd40 : - (_theResult____h287214[15] ? - 6'd41 : - (_theResult____h287214[14] ? - 6'd42 : - (_theResult____h287214[13] ? - 6'd43 : - (_theResult____h287214[12] ? - 6'd44 : - (_theResult____h287214[11] ? - 6'd45 : - (_theResult____h287214[10] ? - 6'd46 : - (_theResult____h287214[9] ? - 6'd47 : - (_theResult____h287214[8] ? - 6'd48 : - (_theResult____h287214[7] ? - 6'd49 : - (_theResult____h287214[6] ? - 6'd50 : - (_theResult____h287214[5] ? - 6'd51 : - (_theResult____h287214[4] ? - 6'd52 : - (_theResult____h287214[3] ? - 6'd53 : - (_theResult____h287214[2] ? - 6'd54 : - (_theResult____h287214[1] ? - 6'd55 : - (_theResult____h287214[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 = - (din_exp__h130866 == 11'd0) ? - 12'd3074 : - { din_exp30866_MINUS_1023__q23[10], - din_exp30866_MINUS_1023__q23 } ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 = - (sfdBC__h115662[105] ? - 7'd0 : - (sfdBC__h115662[104] ? - 7'd1 : - (sfdBC__h115662[103] ? - 7'd2 : - (sfdBC__h115662[102] ? - 7'd3 : - (sfdBC__h115662[101] ? - 7'd4 : - (sfdBC__h115662[100] ? - 7'd5 : - (sfdBC__h115662[99] ? - 7'd6 : - (sfdBC__h115662[98] ? - 7'd7 : - (sfdBC__h115662[97] ? - 7'd8 : - (sfdBC__h115662[96] ? - 7'd9 : - (sfdBC__h115662[95] ? - 7'd10 : - (sfdBC__h115662[94] ? - 7'd11 : - (sfdBC__h115662[93] ? - 7'd12 : - (sfdBC__h115662[92] ? - 7'd13 : - (sfdBC__h115662[91] ? - 7'd14 : - (sfdBC__h115662[90] ? - 7'd15 : - (sfdBC__h115662[89] ? - 7'd16 : - (sfdBC__h115662[88] ? - 7'd17 : - (sfdBC__h115662[87] ? - 7'd18 : - (sfdBC__h115662[86] ? - 7'd19 : - (sfdBC__h115662[85] ? - 7'd20 : - (sfdBC__h115662[84] ? - 7'd21 : - (sfdBC__h115662[83] ? - 7'd22 : - (sfdBC__h115662[82] ? - 7'd23 : - (sfdBC__h115662[81] ? - 7'd24 : - (sfdBC__h115662[80] ? - 7'd25 : - (sfdBC__h115662[79] ? - 7'd26 : - (sfdBC__h115662[78] ? - 7'd27 : - (sfdBC__h115662[77] ? - 7'd28 : - (sfdBC__h115662[76] ? - 7'd29 : - (sfdBC__h115662[75] ? - 7'd30 : - (sfdBC__h115662[74] ? - 7'd31 : - (sfdBC__h115662[73] ? - 7'd32 : - (sfdBC__h115662[72] ? - 7'd33 : - (sfdBC__h115662[71] ? - 7'd34 : - (sfdBC__h115662[70] ? - 7'd35 : - (sfdBC__h115662[69] ? - 7'd36 : - (sfdBC__h115662[68] ? - 7'd37 : - (sfdBC__h115662[67] ? - 7'd38 : - (sfdBC__h115662[66] ? - 7'd39 : - (sfdBC__h115662[65] ? - 7'd40 : - (sfdBC__h115662[64] ? - 7'd41 : - (sfdBC__h115662[63] ? - 7'd42 : - (sfdBC__h115662[62] ? - 7'd43 : - (sfdBC__h115662[61] ? - 7'd44 : - (sfdBC__h115662[60] ? - 7'd45 : - (sfdBC__h115662[59] ? - 7'd46 : - (sfdBC__h115662[58] ? - 7'd47 : - (sfdBC__h115662[57] ? - 7'd48 : - (sfdBC__h115662[56] ? - 7'd49 : - (sfdBC__h115662[55] ? - 7'd50 : - (sfdBC__h115662[54] ? - 7'd51 : - (sfdBC__h115662[53] ? - 7'd52 : - (sfdBC__h115662[52] ? - 7'd53 : - (sfdBC__h115662[51] ? - 7'd54 : - (sfdBC__h115662[50] ? - 7'd55 : - (sfdBC__h115662[49] ? - 7'd56 : - (sfdBC__h115662[48] ? - 7'd57 : - (sfdBC__h115662[47] ? - 7'd58 : - (sfdBC__h115662[46] ? - 7'd59 : - (sfdBC__h115662[45] ? - 7'd60 : - (sfdBC__h115662[44] ? - 7'd61 : - (sfdBC__h115662[43] ? - 7'd62 : - (sfdBC__h115662[42] ? - 7'd63 : - (sfdBC__h115662[41] ? - 7'd64 : - (sfdBC__h115662[40] ? - 7'd65 : - (sfdBC__h115662[39] ? - 7'd66 : - (sfdBC__h115662[38] ? - 7'd67 : - (sfdBC__h115662[37] ? - 7'd68 : - (sfdBC__h115662[36] ? - 7'd69 : - (sfdBC__h115662[35] ? - 7'd70 : - (sfdBC__h115662[34] ? - 7'd71 : - (sfdBC__h115662[33] ? - 7'd72 : - (sfdBC__h115662[32] ? - 7'd73 : - (sfdBC__h115662[31] ? - 7'd74 : - (sfdBC__h115662[30] ? - 7'd75 : - (sfdBC__h115662[29] ? - 7'd76 : - (sfdBC__h115662[28] ? - 7'd77 : - (sfdBC__h115662[27] ? - 7'd78 : - (sfdBC__h115662[26] ? - 7'd79 : - (sfdBC__h115662[25] ? - 7'd80 : - (sfdBC__h115662[24] ? - 7'd81 : - (sfdBC__h115662[23] ? - 7'd82 : - (sfdBC__h115662[22] ? - 7'd83 : - (sfdBC__h115662[21] ? - 7'd84 : - (sfdBC__h115662[20] ? - 7'd85 : - (sfdBC__h115662[19] ? - 7'd86 : - (sfdBC__h115662[18] ? - 7'd87 : - (sfdBC__h115662[17] ? - 7'd88 : - (sfdBC__h115662[16] ? - 7'd89 : - (sfdBC__h115662[15] ? - 7'd90 : - (sfdBC__h115662[14] ? - 7'd91 : - (sfdBC__h115662[13] ? - 7'd92 : - (sfdBC__h115662[12] ? - 7'd93 : - (sfdBC__h115662[11] ? - 7'd94 : - (sfdBC__h115662[10] ? - 7'd95 : - (sfdBC__h115662[9] ? - 7'd96 : - (sfdBC__h115662[8] ? - 7'd97 : - (sfdBC__h115662[7] ? - 7'd98 : - (sfdBC__h115662[6] ? - 7'd99 : - (sfdBC__h115662[5] ? - 7'd100 : - (sfdBC__h115662[4] ? - 7'd101 : - (sfdBC__h115662[3] ? - 7'd102 : - (sfdBC__h115662[2] ? - 7'd103 : - (sfdBC__h115662[1] ? - 7'd104 : - (sfdBC__h115662[0] ? - 7'd105 : - 7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 = - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 - - 12'd3074 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h130949, sfdin__h130943[105:54] } ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 = - (guard__h269587 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h277686 : - _theResult___exp__h278202 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 = - (guard__h269587 == 2'b0) ? - _theResult___fst_exp__h277686 : - (resWire$wget[68] ? - _theResult___exp__h278202 : - _theResult___fst_exp__h277686) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 = - (guard__h269587 == 2'b0 || resWire$wget[68]) ? - sfdin__h277680[56:34] : - _theResult___sfd__h278203 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 = - (guard__h269587 == 2'b0) ? - sfdin__h277680[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h278203 : - sfdin__h277680[56:34]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 = - (guard__h164624 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h172852 : - _theResult___exp__h173571 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 = - (guard__h164624 == 2'b0) ? - _theResult___fst_exp__h172852 : - (iFifo$D_OUT[168] ? - _theResult___exp__h173571 : - _theResult___fst_exp__h172852) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 = - (guard__h164624 == 2'b0 || iFifo$D_OUT[168]) ? - sfdin__h172846[56:5] : - _theResult___sfd__h173572 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 = - (guard__h164624 == 2'b0) ? - sfdin__h172846[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h173572 : - sfdin__h172846[56:5]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 = - (guard__h242201 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h250429 : - _theResult___exp__h251148 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 = - (guard__h242201 == 2'b0) ? - _theResult___fst_exp__h250429 : - (iFifo$D_OUT[38] ? - _theResult___exp__h251148 : - _theResult___fst_exp__h250429) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 = - (guard__h242201 == 2'b0 || iFifo$D_OUT[38]) ? - sfdin__h250423[56:5] : - _theResult___sfd__h251149 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 = - (guard__h242201 == 2'b0) ? - sfdin__h250423[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h251149 : - sfdin__h250423[56:5]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 = - (guard__h203262 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h211490 : - _theResult___exp__h212209 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 = - (guard__h203262 == 2'b0) ? - _theResult___fst_exp__h211490 : - (iFifo$D_OUT[103] ? - _theResult___exp__h212209 : - _theResult___fst_exp__h211490) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 = - (guard__h203262 == 2'b0 || iFifo$D_OUT[103]) ? - sfdin__h211484[56:5] : - _theResult___sfd__h212210 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 = - (guard__h203262 == 2'b0) ? - sfdin__h211484[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h212210 : - sfdin__h211484[56:5]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 = - (guard__h287224 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h295452 : - _theResult___exp__h295968 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 = - (guard__h287224 == 2'b0) ? - _theResult___fst_exp__h295452 : - (resWire$wget[68] ? - _theResult___exp__h295968 : - _theResult___fst_exp__h295452) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 = - (guard__h287224 == 2'b0 || resWire$wget[68]) ? - sfdin__h295446[56:34] : - _theResult___sfd__h295969 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 = - (guard__h287224 == 2'b0) ? - sfdin__h295446[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h295969 : - sfdin__h295446[56:34]) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 = - (guard__h194013 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h201974 : - _theResult___exp__h202619 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 = - (guard__h194013 == 2'b0) ? - _theResult___fst_exp__h201974 : - (iFifo$D_OUT[103] ? - _theResult___exp__h202619 : - _theResult___fst_exp__h201974) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 = - (guard__h212301 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h220291 : - _theResult___exp__h220961 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 = - (guard__h212301 == 2'b0) ? - _theResult___fst_exp__h220291 : - (iFifo$D_OUT[103] ? - _theResult___exp__h220961 : - _theResult___fst_exp__h220291) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 = - (guard__h194013 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___snd__h201925[56:5] : - _theResult___sfd__h202620 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 = - (guard__h194013 == 2'b0) ? - _theResult___snd__h201925[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h202620 : - _theResult___snd__h201925[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 = - (guard__h212301 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___snd__h220237[56:5] : - _theResult___sfd__h220962 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 = - (guard__h212301 == 2'b0) ? - _theResult___snd__h220237[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h220962 : - _theResult___snd__h220237[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 = - (guard__h155375 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h163336 : - _theResult___exp__h163981 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 = - (guard__h155375 == 2'b0) ? - _theResult___fst_exp__h163336 : - (iFifo$D_OUT[168] ? - _theResult___exp__h163981 : - _theResult___fst_exp__h163336) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 = - (guard__h173663 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h181653 : - _theResult___exp__h182323 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 = - (guard__h173663 == 2'b0) ? - _theResult___fst_exp__h181653 : - (iFifo$D_OUT[168] ? - _theResult___exp__h182323 : - _theResult___fst_exp__h181653) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 = - (guard__h155375 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___snd__h163287[56:5] : - _theResult___sfd__h163982 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 = - (guard__h155375 == 2'b0) ? - _theResult___snd__h163287[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h163982 : - _theResult___snd__h163287[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 = - (guard__h173663 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___snd__h181599[56:5] : - _theResult___sfd__h182324 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 = - (guard__h173663 == 2'b0) ? - _theResult___snd__h181599[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h182324 : - _theResult___snd__h181599[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 = - (guard__h232952 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h240913 : - _theResult___exp__h241558 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 = - (guard__h232952 == 2'b0) ? - _theResult___fst_exp__h240913 : - (iFifo$D_OUT[38] ? - _theResult___exp__h241558 : - _theResult___fst_exp__h240913) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 = - (guard__h251240 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h259230 : - _theResult___exp__h259900 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 = - (guard__h251240 == 2'b0) ? - _theResult___fst_exp__h259230 : - (iFifo$D_OUT[38] ? - _theResult___exp__h259900 : - _theResult___fst_exp__h259230) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 = - (guard__h232952 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___snd__h240864[56:5] : - _theResult___sfd__h241559 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 = - (guard__h232952 == 2'b0) ? - _theResult___snd__h240864[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h241559 : - _theResult___snd__h240864[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 = - (guard__h251240 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___snd__h259176[56:5] : - _theResult___sfd__h259901 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 = - (guard__h251240 == 2'b0) ? - _theResult___snd__h259176[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h259901 : - _theResult___snd__h259176[56:5]) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 = - (guard__h278294 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h286342 : - _theResult___exp__h286784 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 = - (guard__h278294 == 2'b0) ? - _theResult___fst_exp__h286342 : - (resWire$wget[68] ? - _theResult___exp__h286784 : - _theResult___fst_exp__h286342) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 = - (guard__h296060 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h304137 : - _theResult___exp__h304604 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 = - (guard__h296060 == 2'b0) ? - _theResult___fst_exp__h304137 : - (resWire$wget[68] ? - _theResult___exp__h304604 : - _theResult___fst_exp__h304137) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 = - (guard__h278294 == 2'b0 || resWire$wget[68]) ? - _theResult___snd__h286293[56:34] : - _theResult___sfd__h286785 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 = - (guard__h278294 == 2'b0) ? - _theResult___snd__h286293[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h286785 : - _theResult___snd__h286293[56:34]) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 = - (guard__h296060 == 2'b0 || resWire$wget[68]) ? - _theResult___snd__h304083[56:34] : - _theResult___sfd__h304605 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 = - (guard__h296060 == 2'b0) ? - _theResult___snd__h304083[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h304605 : - _theResult___snd__h304083[56:34]) ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 12'd3074 : - { theResult___fst_exp2290_MINUS_1023__q11[10], - theResult___fst_exp2290_MINUS_1023__q11 } ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 = - (sfdin__h34118[57] ? - 6'd0 : - (sfdin__h34118[56] ? - 6'd1 : - (sfdin__h34118[55] ? - 6'd2 : - (sfdin__h34118[54] ? - 6'd3 : - (sfdin__h34118[53] ? - 6'd4 : - (sfdin__h34118[52] ? - 6'd5 : - (sfdin__h34118[51] ? - 6'd6 : - (sfdin__h34118[50] ? - 6'd7 : - (sfdin__h34118[49] ? - 6'd8 : - (sfdin__h34118[48] ? - 6'd9 : - (sfdin__h34118[47] ? - 6'd10 : - (sfdin__h34118[46] ? - 6'd11 : - (sfdin__h34118[45] ? - 6'd12 : - (sfdin__h34118[44] ? - 6'd13 : - (sfdin__h34118[43] ? - 6'd14 : - (sfdin__h34118[42] ? - 6'd15 : - (sfdin__h34118[41] ? - 6'd16 : - (sfdin__h34118[40] ? - 6'd17 : - (sfdin__h34118[39] ? - 6'd18 : - (sfdin__h34118[38] ? - 6'd19 : - (sfdin__h34118[37] ? - 6'd20 : - (sfdin__h34118[36] ? - 6'd21 : - (sfdin__h34118[35] ? - 6'd22 : - (sfdin__h34118[34] ? - 6'd23 : - (sfdin__h34118[33] ? - 6'd24 : - (sfdin__h34118[32] ? - 6'd25 : - (sfdin__h34118[31] ? - 6'd26 : - (sfdin__h34118[30] ? - 6'd27 : - (sfdin__h34118[29] ? - 6'd28 : - (sfdin__h34118[28] ? - 6'd29 : - (sfdin__h34118[27] ? - 6'd30 : - (sfdin__h34118[26] ? - 6'd31 : - (sfdin__h34118[25] ? - 6'd32 : - (sfdin__h34118[24] ? - 6'd33 : - (sfdin__h34118[23] ? - 6'd34 : - (sfdin__h34118[22] ? - 6'd35 : - (sfdin__h34118[21] ? - 6'd36 : - (sfdin__h34118[20] ? - 6'd37 : - (sfdin__h34118[19] ? - 6'd38 : - (sfdin__h34118[18] ? - 6'd39 : - (sfdin__h34118[17] ? - 6'd40 : - (sfdin__h34118[16] ? - 6'd41 : - (sfdin__h34118[15] ? - 6'd42 : - (sfdin__h34118[14] ? - 6'd43 : - (sfdin__h34118[13] ? - 6'd44 : - (sfdin__h34118[12] ? - 6'd45 : - (sfdin__h34118[11] ? - 6'd46 : - (sfdin__h34118[10] ? - 6'd47 : - (sfdin__h34118[9] ? - 6'd48 : - (sfdin__h34118[8] ? - 6'd49 : - (sfdin__h34118[7] ? - 6'd50 : - (sfdin__h34118[6] ? - 6'd51 : - (sfdin__h34118[5] ? - 6'd52 : - (sfdin__h34118[4] ? - 6'd53 : - (sfdin__h34118[3] ? - 6'd54 : - (sfdin__h34118[2] ? - 6'd55 : - (sfdin__h34118[1] ? - 6'd56 : - (sfdin__h34118[0] ? - 6'd57 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 = - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 - - 12'd3074 ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926 = - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 ? - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921 : - { fpu_div64_fState_S3$D_OUT[129:128], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[127] : - fpu_div64_fState_S3$D_OUT[127], - fpu_div64_fState_S3$D_OUT[126], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[125] : - fpu_div64_fState_S3$D_OUT[125] } ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h42333, sfdin__h42327[57:6] } ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 == 52'd0) ? - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194] : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ? - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 : - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194]) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 == 52'd0) ? - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ? - 63'h7FF0000000000000 : - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936 = - (x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51]) ? - { fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 } : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118]) ? - fpu_madd_fOperand_S0$D_OUT[130:67] : - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54]) ? - fpu_madd_fOperand_S0$D_OUT[66:3] : - { NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 })) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51]) ? - { fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - x__h96539, - sfd__h99402 } : - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 ; - assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 = - (sfd__h133119[56] ? - 6'd0 : - (sfd__h133119[55] ? - 6'd1 : - (sfd__h133119[54] ? - 6'd2 : - (sfd__h133119[53] ? - 6'd3 : - (sfd__h133119[52] ? - 6'd4 : - (sfd__h133119[51] ? - 6'd5 : - (sfd__h133119[50] ? - 6'd6 : - (sfd__h133119[49] ? - 6'd7 : - (sfd__h133119[48] ? - 6'd8 : - (sfd__h133119[47] ? - 6'd9 : - (sfd__h133119[46] ? - 6'd10 : - (sfd__h133119[45] ? - 6'd11 : - (sfd__h133119[44] ? - 6'd12 : - (sfd__h133119[43] ? - 6'd13 : - (sfd__h133119[42] ? - 6'd14 : - (sfd__h133119[41] ? - 6'd15 : - (sfd__h133119[40] ? - 6'd16 : - (sfd__h133119[39] ? - 6'd17 : - (sfd__h133119[38] ? - 6'd18 : - (sfd__h133119[37] ? - 6'd19 : - (sfd__h133119[36] ? - 6'd20 : - (sfd__h133119[35] ? - 6'd21 : - (sfd__h133119[34] ? - 6'd22 : - (sfd__h133119[33] ? - 6'd23 : - (sfd__h133119[32] ? - 6'd24 : - (sfd__h133119[31] ? - 6'd25 : - (sfd__h133119[30] ? - 6'd26 : - (sfd__h133119[29] ? - 6'd27 : - (sfd__h133119[28] ? - 6'd28 : - (sfd__h133119[27] ? - 6'd29 : - (sfd__h133119[26] ? - 6'd30 : - (sfd__h133119[25] ? - 6'd31 : - (sfd__h133119[24] ? - 6'd32 : - (sfd__h133119[23] ? - 6'd33 : - (sfd__h133119[22] ? - 6'd34 : - (sfd__h133119[21] ? - 6'd35 : - (sfd__h133119[20] ? - 6'd36 : - (sfd__h133119[19] ? - 6'd37 : - (sfd__h133119[18] ? - 6'd38 : - (sfd__h133119[17] ? - 6'd39 : - (sfd__h133119[16] ? - 6'd40 : - (sfd__h133119[15] ? - 6'd41 : - (sfd__h133119[14] ? - 6'd42 : - (sfd__h133119[13] ? - 6'd43 : - (sfd__h133119[12] ? - 6'd44 : - (sfd__h133119[11] ? - 6'd45 : - (sfd__h133119[10] ? - 6'd46 : - (sfd__h133119[9] ? - 6'd47 : - (sfd__h133119[8] ? - 6'd48 : - (sfd__h133119[7] ? - 6'd49 : - (sfd__h133119[6] ? - 6'd50 : - (sfd__h133119[5] ? - 6'd51 : - (sfd__h133119[4] ? - 6'd52 : - (sfd__h133119[3] ? - 6'd53 : - (sfd__h133119[2] ? - 6'd54 : - (sfd__h133119[1] ? - 6'd55 : - (sfd__h133119[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h141375, sfdin__h141369[56:5] } ; - assign IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - ((IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73) : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 ; - assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503 = - (!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ? - fpu_madd_fState_S3$D_OUT[86] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[4] ; - assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506 = - (!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ? - fpu_madd_fState_S3$D_OUT[85] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[3] ; - assign IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 = - { NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 : - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 - - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 : - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 - - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563, - x__h131940, - x__h131944 } ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 = - ((SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99[10], - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - ((_theResult___fst_exp__h211490 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117) : - ((_theResult___fst_exp__h220291 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119) ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - ((_theResult___fst_exp__h211490 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123) : - ((_theResult___fst_exp__h220291 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125) ; - assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 = - ((SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39[10], - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - ((_theResult___fst_exp__h172852 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57) : - ((_theResult___fst_exp__h181653 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59) ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 = - ((SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66[10], - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - ((_theResult___fst_exp__h250429 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84) : - ((_theResult___fst_exp__h259230 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86) ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - ((_theResult___fst_exp__h250429 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90) : - ((_theResult___fst_exp__h259230 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 = - ((SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141[7], - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 }) - - 9'd386 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - ((_theResult___fst_exp__h295452 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324) : - ((_theResult___fst_exp__h304137 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - ((_theResult___fst_exp__h295452 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409) : - ((_theResult___fst_exp__h304137 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[2] : - _theResult___fst_exp__h304685 == 8'd255 && - _theResult___fst_sfd__h304686 == 23'd0 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[1] : - _theResult___fst_exp__h304137 == 8'd0 && - guard__h296060 != 2'b0 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[0] : - _theResult___fst_exp__h304137 != 8'd255 && - guard__h296060 != 2'b0 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 = - (((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7[10]}}, - fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7 }) - - { 7'd0, b__h4039 }) - - (((fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8[10]}}, - fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8 }) - - { 7'd0, b__h11457 }) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) <= - 13'd5120 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) < - 13'd3020 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) < - 13'd3074 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401) ? - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 : - CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0) ? - 11'd2047 : - ((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353) ? - 11'd0 : - _theResult___fst_exp__h19467) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401) ? - 52'd0 : - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ? - _theResult___fst_sfd__h19957 : - _theResult___fst_sfd__h19468) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54]) ? - { fpu_div64_fOperands_S0$D_OUT[66:55], sfd__h18937 } : - ((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118]) ? - fpu_div64_fOperands_S0$D_OUT[130:67] : - ((fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54]) ? - fpu_div64_fOperands_S0$D_OUT[66:3] : - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452)) ; - assign IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] == 2'b0 && - !fpu_div64_fState_S3$D_OUT[194] : - !fpu_div64_fState_S3$D_OUT[194] ; - assign IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921 = - ((fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - { fpu_div64_fState_S3$D_OUT[129:128], - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[127], - fpu_div64_fState_S3$D_OUT[126], - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[125] } : - fpu_div64_fState_S3$D_OUT[129:125]) | - { 2'd0, - sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023, - _theResult___fst_exp__h42336 == 11'd0 && guard__h33946 != 2'd0, - sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023 } ; - assign IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h42982[53:52] == 2'b01) ? - 11'd1 : - fpu_div64_fState_S4$D_OUT[64:54] ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 = - (fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 && - !fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ? - 63'h7FF8000000000000 : - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 = - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118]) ? - { fpu_madd_fOperand_S0$D_OUT[130:119], sfd__h99405 } : - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54]) ? - { fpu_madd_fOperand_S0$D_OUT[66:55], sfd__h99408 } : - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936) ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 = - { ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128[10]}}, - fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 }) + - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129[10]}}, - fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 }), - x__h114243, - x__h114255 } ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54] || - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 || - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[193:131] : - 63'd0 ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 && - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54] || - NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fProd_S3$D_OUT != 106'd0 || - fpu_madd_fState_S3$D_OUT[83] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[1] ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fProd_S3$D_OUT != 106'd0 || - fpu_madd_fState_S3$D_OUT[82] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[0] ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - (fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - 63'd0 : - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534) : - 63'h7FEFFFFFFFFFFFFF ; - assign IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525 = - fpu_madd_fState_S3$D_OUT[151] ? - fpu_madd_fState_S3$D_OUT[86:82] : - { IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 } ; - assign IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 = - (fpu_madd_fState_S4$D_OUT[128:118] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27[10]}}, - fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27 } ; - assign IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 = - (fpu_madd_fState_S4$D_OUT[64:54] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26[10]}}, - fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26 } ; - assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 = - (value__h141307[10:0] == 11'd0) ? - 12'd3074 : - { value41307_BITS_10_TO_0_MINUS_1023__q28[10], - value41307_BITS_10_TO_0_MINUS_1023__q28 } ; - assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 = - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 - - 12'd3074 ; - assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 = - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd0 && - sfd__h142040[53:52] == 2'b01) ? - 11'd1 : - fpu_madd_fState_S8$D_OUT[65:55] ; - assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 = - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[65:55] : - _theResult___fst_exp__h142619 ; - assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060 = - (fpu_madd_fState_S8$D_OUT[67] && - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 == - 11'd0 && - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h142620) == - 52'd0 && - !fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043[0] && - fpu_madd_fState_S8$D_OUT[0]) ? - fpu_madd_fState_S8$D_OUT[70:68] == 3'd3 : - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[66] : - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127) ; - assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 = - { IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060, - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[65:3] : - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132, - fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 } ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0) ? - (fpu_sqr64_fOperand_S0$D_OUT[54] ? - 6'd2 : - (fpu_sqr64_fOperand_S0$D_OUT[53] ? - 6'd3 : - (fpu_sqr64_fOperand_S0$D_OUT[52] ? - 6'd4 : - (fpu_sqr64_fOperand_S0$D_OUT[51] ? - 6'd5 : - (fpu_sqr64_fOperand_S0$D_OUT[50] ? - 6'd6 : - (fpu_sqr64_fOperand_S0$D_OUT[49] ? - 6'd7 : - (fpu_sqr64_fOperand_S0$D_OUT[48] ? - 6'd8 : - (fpu_sqr64_fOperand_S0$D_OUT[47] ? - 6'd9 : - (fpu_sqr64_fOperand_S0$D_OUT[46] ? - 6'd10 : - (fpu_sqr64_fOperand_S0$D_OUT[45] ? - 6'd11 : - (fpu_sqr64_fOperand_S0$D_OUT[44] ? - 6'd12 : - (fpu_sqr64_fOperand_S0$D_OUT[43] ? - 6'd13 : - (fpu_sqr64_fOperand_S0$D_OUT[42] ? - 6'd14 : - (fpu_sqr64_fOperand_S0$D_OUT[41] ? - 6'd15 : - (fpu_sqr64_fOperand_S0$D_OUT[40] ? - 6'd16 : - (fpu_sqr64_fOperand_S0$D_OUT[39] ? - 6'd17 : - (fpu_sqr64_fOperand_S0$D_OUT[38] ? - 6'd18 : - (fpu_sqr64_fOperand_S0$D_OUT[37] ? - 6'd19 : - (fpu_sqr64_fOperand_S0$D_OUT[36] ? - 6'd20 : - (fpu_sqr64_fOperand_S0$D_OUT[35] ? - 6'd21 : - (fpu_sqr64_fOperand_S0$D_OUT[34] ? - 6'd22 : - (fpu_sqr64_fOperand_S0$D_OUT[33] ? - 6'd23 : - (fpu_sqr64_fOperand_S0$D_OUT[32] ? - 6'd24 : - (fpu_sqr64_fOperand_S0$D_OUT[31] ? - 6'd25 : - (fpu_sqr64_fOperand_S0$D_OUT[30] ? - 6'd26 : - (fpu_sqr64_fOperand_S0$D_OUT[29] ? - 6'd27 : - (fpu_sqr64_fOperand_S0$D_OUT[28] ? - 6'd28 : - (fpu_sqr64_fOperand_S0$D_OUT[27] ? - 6'd29 : - (fpu_sqr64_fOperand_S0$D_OUT[26] ? - 6'd30 : - (fpu_sqr64_fOperand_S0$D_OUT[25] ? - 6'd31 : - (fpu_sqr64_fOperand_S0$D_OUT[24] ? - 6'd32 : - (fpu_sqr64_fOperand_S0$D_OUT[23] ? - 6'd33 : - (fpu_sqr64_fOperand_S0$D_OUT[22] ? - 6'd34 : - (fpu_sqr64_fOperand_S0$D_OUT[21] ? - 6'd35 : - (fpu_sqr64_fOperand_S0$D_OUT[20] ? - 6'd36 : - (fpu_sqr64_fOperand_S0$D_OUT[19] ? - 6'd37 : - (fpu_sqr64_fOperand_S0$D_OUT[18] ? - 6'd38 : - (fpu_sqr64_fOperand_S0$D_OUT[17] ? - 6'd39 : - (fpu_sqr64_fOperand_S0$D_OUT[16] ? - 6'd40 : - (fpu_sqr64_fOperand_S0$D_OUT[15] ? - 6'd41 : - (fpu_sqr64_fOperand_S0$D_OUT[14] ? - 6'd42 : - (fpu_sqr64_fOperand_S0$D_OUT[13] ? - 6'd43 : - (fpu_sqr64_fOperand_S0$D_OUT[12] ? - 6'd44 : - (fpu_sqr64_fOperand_S0$D_OUT[11] ? - 6'd45 : - (fpu_sqr64_fOperand_S0$D_OUT[10] ? - 6'd46 : - (fpu_sqr64_fOperand_S0$D_OUT[9] ? - 6'd47 : - (fpu_sqr64_fOperand_S0$D_OUT[8] ? - 6'd48 : - (fpu_sqr64_fOperand_S0$D_OUT[7] ? - 6'd49 : - (fpu_sqr64_fOperand_S0$D_OUT[6] ? - 6'd50 : - (fpu_sqr64_fOperand_S0$D_OUT[5] ? - 6'd51 : - (fpu_sqr64_fOperand_S0$D_OUT[4] ? - 6'd52 : - (fpu_sqr64_fOperand_S0$D_OUT[3] ? - 6'd53 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1 ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195 = - ((fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16[10]}}, - fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16 }) - - { 7'd0, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 } ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212 = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54] || - fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] == 52'd0 && - !fpu_sqr64_fOperand_S0$D_OUT[66]) ? - { 1'd1, - fpu_sqr64_fOperand_S0$D_OUT[66:3], - 130'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - (fpu_sqr64_fOperand_S0$D_OUT[66] ? - 195'h5FFE00000000000020AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - { 70'h155555555555555540, - fpu_sqr64_fOperand_S0$D_OUT[2:0], - fpu_sqr64_fOperand_S0$D_OUT[66], - x__h52551[10:0], - fpu_sqr64_fOperand_S0$D_OUT[54:3], - x__h60693 }) ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195[12:1] ; - assign IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 = - (fpu_sqr64_fState_S1$D_OUT[57] ? - 7'd0 : - (fpu_sqr64_fState_S1$D_OUT[56] ? - 7'd1 : - (fpu_sqr64_fState_S1$D_OUT[55] ? - 7'd2 : - (fpu_sqr64_fState_S1$D_OUT[54] ? - 7'd3 : - (fpu_sqr64_fState_S1$D_OUT[53] ? - 7'd4 : - (fpu_sqr64_fState_S1$D_OUT[52] ? - 7'd5 : - (fpu_sqr64_fState_S1$D_OUT[51] ? - 7'd6 : - (fpu_sqr64_fState_S1$D_OUT[50] ? - 7'd7 : - (fpu_sqr64_fState_S1$D_OUT[49] ? - 7'd8 : - (fpu_sqr64_fState_S1$D_OUT[48] ? - 7'd9 : - (fpu_sqr64_fState_S1$D_OUT[47] ? - 7'd10 : - (fpu_sqr64_fState_S1$D_OUT[46] ? - 7'd11 : - (fpu_sqr64_fState_S1$D_OUT[45] ? - 7'd12 : - (fpu_sqr64_fState_S1$D_OUT[44] ? - 7'd13 : - (fpu_sqr64_fState_S1$D_OUT[43] ? - 7'd14 : - (fpu_sqr64_fState_S1$D_OUT[42] ? - 7'd15 : - (fpu_sqr64_fState_S1$D_OUT[41] ? - 7'd16 : - (fpu_sqr64_fState_S1$D_OUT[40] ? - 7'd17 : - (fpu_sqr64_fState_S1$D_OUT[39] ? - 7'd18 : - (fpu_sqr64_fState_S1$D_OUT[38] ? - 7'd19 : - (fpu_sqr64_fState_S1$D_OUT[37] ? - 7'd20 : - (fpu_sqr64_fState_S1$D_OUT[36] ? - 7'd21 : - (fpu_sqr64_fState_S1$D_OUT[35] ? - 7'd22 : - (fpu_sqr64_fState_S1$D_OUT[34] ? - 7'd23 : - (fpu_sqr64_fState_S1$D_OUT[33] ? - 7'd24 : - (fpu_sqr64_fState_S1$D_OUT[32] ? - 7'd25 : - (fpu_sqr64_fState_S1$D_OUT[31] ? - 7'd26 : - (fpu_sqr64_fState_S1$D_OUT[30] ? - 7'd27 : - (fpu_sqr64_fState_S1$D_OUT[29] ? - 7'd28 : - (fpu_sqr64_fState_S1$D_OUT[28] ? - 7'd29 : - (fpu_sqr64_fState_S1$D_OUT[27] ? - 7'd30 : - (fpu_sqr64_fState_S1$D_OUT[26] ? - 7'd31 : - (fpu_sqr64_fState_S1$D_OUT[25] ? - 7'd32 : - (fpu_sqr64_fState_S1$D_OUT[24] ? - 7'd33 : - (fpu_sqr64_fState_S1$D_OUT[23] ? - 7'd34 : - (fpu_sqr64_fState_S1$D_OUT[22] ? - 7'd35 : - (fpu_sqr64_fState_S1$D_OUT[21] ? - 7'd36 : - (fpu_sqr64_fState_S1$D_OUT[20] ? - 7'd37 : - (fpu_sqr64_fState_S1$D_OUT[19] ? - 7'd38 : - (fpu_sqr64_fState_S1$D_OUT[18] ? - 7'd39 : - (fpu_sqr64_fState_S1$D_OUT[17] ? - 7'd40 : - (fpu_sqr64_fState_S1$D_OUT[16] ? - 7'd41 : - (fpu_sqr64_fState_S1$D_OUT[15] ? - 7'd42 : - (fpu_sqr64_fState_S1$D_OUT[14] ? - 7'd43 : - (fpu_sqr64_fState_S1$D_OUT[13] ? - 7'd44 : - (fpu_sqr64_fState_S1$D_OUT[12] ? - 7'd45 : - (fpu_sqr64_fState_S1$D_OUT[11] ? - 7'd46 : - (fpu_sqr64_fState_S1$D_OUT[10] ? - 7'd47 : - (fpu_sqr64_fState_S1$D_OUT[9] ? - 7'd48 : - (fpu_sqr64_fState_S1$D_OUT[8] ? - 7'd49 : - (fpu_sqr64_fState_S1$D_OUT[7] ? - 7'd50 : - (fpu_sqr64_fState_S1$D_OUT[6] ? - 7'd51 : - (fpu_sqr64_fState_S1$D_OUT[5] ? - 7'd52 : - (fpu_sqr64_fState_S1$D_OUT[4] ? - 7'd53 : - (fpu_sqr64_fState_S1$D_OUT[3] ? - 7'd54 : - (fpu_sqr64_fState_S1$D_OUT[2] ? - 7'd55 : - (fpu_sqr64_fState_S1$D_OUT[1] ? - 7'd56 : - (fpu_sqr64_fState_S1$D_OUT[0] ? - 7'd57 : - 7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 12'd3074 : - { fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18[10], - fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18 } ; - assign IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 = - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 - - 12'd3074 ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671 = - fpu_sqr64_fState_S3$D_OUT[195] ? - fpu_sqr64_fState_S3$D_OUT[128:126] : - { fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023, - _theResult___fst_exp__h94753 == 11'd0 && - guard__h86435 != 2'd0, - fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023 } ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h94750, sfdin__h94744[58:7] } ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 = - (fpu_sqr64_fState_S3$D_OUT[58] ? - 6'd0 : - (fpu_sqr64_fState_S3$D_OUT[57] ? - 6'd1 : - (fpu_sqr64_fState_S3$D_OUT[56] ? - 6'd2 : - (fpu_sqr64_fState_S3$D_OUT[55] ? - 6'd3 : - (fpu_sqr64_fState_S3$D_OUT[54] ? - 6'd4 : - (fpu_sqr64_fState_S3$D_OUT[53] ? - 6'd5 : - (fpu_sqr64_fState_S3$D_OUT[52] ? - 6'd6 : - (fpu_sqr64_fState_S3$D_OUT[51] ? - 6'd7 : - (fpu_sqr64_fState_S3$D_OUT[50] ? - 6'd8 : - (fpu_sqr64_fState_S3$D_OUT[49] ? - 6'd9 : - (fpu_sqr64_fState_S3$D_OUT[48] ? - 6'd10 : - (fpu_sqr64_fState_S3$D_OUT[47] ? - 6'd11 : - (fpu_sqr64_fState_S3$D_OUT[46] ? - 6'd12 : - (fpu_sqr64_fState_S3$D_OUT[45] ? - 6'd13 : - (fpu_sqr64_fState_S3$D_OUT[44] ? - 6'd14 : - (fpu_sqr64_fState_S3$D_OUT[43] ? - 6'd15 : - (fpu_sqr64_fState_S3$D_OUT[42] ? - 6'd16 : - (fpu_sqr64_fState_S3$D_OUT[41] ? - 6'd17 : - (fpu_sqr64_fState_S3$D_OUT[40] ? - 6'd18 : - (fpu_sqr64_fState_S3$D_OUT[39] ? - 6'd19 : - (fpu_sqr64_fState_S3$D_OUT[38] ? - 6'd20 : - (fpu_sqr64_fState_S3$D_OUT[37] ? - 6'd21 : - (fpu_sqr64_fState_S3$D_OUT[36] ? - 6'd22 : - (fpu_sqr64_fState_S3$D_OUT[35] ? - 6'd23 : - (fpu_sqr64_fState_S3$D_OUT[34] ? - 6'd24 : - (fpu_sqr64_fState_S3$D_OUT[33] ? - 6'd25 : - (fpu_sqr64_fState_S3$D_OUT[32] ? - 6'd26 : - (fpu_sqr64_fState_S3$D_OUT[31] ? - 6'd27 : - (fpu_sqr64_fState_S3$D_OUT[30] ? - 6'd28 : - (fpu_sqr64_fState_S3$D_OUT[29] ? - 6'd29 : - (fpu_sqr64_fState_S3$D_OUT[28] ? - 6'd30 : - (fpu_sqr64_fState_S3$D_OUT[27] ? - 6'd31 : - (fpu_sqr64_fState_S3$D_OUT[26] ? - 6'd32 : - (fpu_sqr64_fState_S3$D_OUT[25] ? - 6'd33 : - (fpu_sqr64_fState_S3$D_OUT[24] ? - 6'd34 : - (fpu_sqr64_fState_S3$D_OUT[23] ? - 6'd35 : - (fpu_sqr64_fState_S3$D_OUT[22] ? - 6'd36 : - (fpu_sqr64_fState_S3$D_OUT[21] ? - 6'd37 : - (fpu_sqr64_fState_S3$D_OUT[20] ? - 6'd38 : - (fpu_sqr64_fState_S3$D_OUT[19] ? - 6'd39 : - (fpu_sqr64_fState_S3$D_OUT[18] ? - 6'd40 : - (fpu_sqr64_fState_S3$D_OUT[17] ? - 6'd41 : - (fpu_sqr64_fState_S3$D_OUT[16] ? - 6'd42 : - (fpu_sqr64_fState_S3$D_OUT[15] ? - 6'd43 : - (fpu_sqr64_fState_S3$D_OUT[14] ? - 6'd44 : - (fpu_sqr64_fState_S3$D_OUT[13] ? - 6'd45 : - (fpu_sqr64_fState_S3$D_OUT[12] ? - 6'd46 : - (fpu_sqr64_fState_S3$D_OUT[11] ? - 6'd47 : - (fpu_sqr64_fState_S3$D_OUT[10] ? - 6'd48 : - (fpu_sqr64_fState_S3$D_OUT[9] ? - 6'd49 : - (fpu_sqr64_fState_S3$D_OUT[8] ? - 6'd50 : - (fpu_sqr64_fState_S3$D_OUT[7] ? - 6'd51 : - (fpu_sqr64_fState_S3$D_OUT[6] ? - 6'd52 : - (fpu_sqr64_fState_S3$D_OUT[5] ? - 6'd53 : - (fpu_sqr64_fState_S3$D_OUT[4] ? - 6'd54 : - (fpu_sqr64_fState_S3$D_OUT[3] ? - 6'd55 : - (fpu_sqr64_fState_S3$D_OUT[2] ? - 6'd56 : - (fpu_sqr64_fState_S3$D_OUT[1] ? - 6'd57 : - (fpu_sqr64_fState_S3$D_OUT[0] ? - 6'd58 : - 6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h95416[53:52] == 2'b01) ? - 11'd1 : - fpu_sqr64_fState_S4$D_OUT[64:54] ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 = - ((iFifo$D_OUT[102:95] == 8'd0) ? - (iFifo$D_OUT[94] ? - 6'd2 : - (iFifo$D_OUT[93] ? - 6'd3 : - (iFifo$D_OUT[92] ? - 6'd4 : - (iFifo$D_OUT[91] ? - 6'd5 : - (iFifo$D_OUT[90] ? - 6'd6 : - (iFifo$D_OUT[89] ? - 6'd7 : - (iFifo$D_OUT[88] ? - 6'd8 : - (iFifo$D_OUT[87] ? - 6'd9 : - (iFifo$D_OUT[86] ? - 6'd10 : - (iFifo$D_OUT[85] ? - 6'd11 : - (iFifo$D_OUT[84] ? - 6'd12 : - (iFifo$D_OUT[83] ? - 6'd13 : - (iFifo$D_OUT[82] ? - 6'd14 : - (iFifo$D_OUT[81] ? - 6'd15 : - (iFifo$D_OUT[80] ? - 6'd16 : - (iFifo$D_OUT[79] ? - 6'd17 : - (iFifo$D_OUT[78] ? - 6'd18 : - (iFifo$D_OUT[77] ? - 6'd19 : - (iFifo$D_OUT[76] ? - 6'd20 : - (iFifo$D_OUT[75] ? - 6'd21 : - (iFifo$D_OUT[74] ? - 6'd22 : - (iFifo$D_OUT[73] ? - 6'd23 : - (iFifo$D_OUT[72] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 = - { (iFifo$D_OUT[102:95] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h221054, - (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0) ? - _theResult___snd_fst_sfd__h183126 : - _theResult___fst_sfd__h221058 } ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 = - { (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0 || - (iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - iFifo$D_OUT[103] : - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 = - { (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0 || - (iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - !iFifo$D_OUT[103] : - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 = - ((iFifo$D_OUT[167:160] == 8'd0) ? - (iFifo$D_OUT[159] ? - 6'd2 : - (iFifo$D_OUT[158] ? - 6'd3 : - (iFifo$D_OUT[157] ? - 6'd4 : - (iFifo$D_OUT[156] ? - 6'd5 : - (iFifo$D_OUT[155] ? - 6'd6 : - (iFifo$D_OUT[154] ? - 6'd7 : - (iFifo$D_OUT[153] ? - 6'd8 : - (iFifo$D_OUT[152] ? - 6'd9 : - (iFifo$D_OUT[151] ? - 6'd10 : - (iFifo$D_OUT[150] ? - 6'd11 : - (iFifo$D_OUT[149] ? - 6'd12 : - (iFifo$D_OUT[148] ? - 6'd13 : - (iFifo$D_OUT[147] ? - 6'd14 : - (iFifo$D_OUT[146] ? - 6'd15 : - (iFifo$D_OUT[145] ? - 6'd16 : - (iFifo$D_OUT[144] ? - 6'd17 : - (iFifo$D_OUT[143] ? - 6'd18 : - (iFifo$D_OUT[142] ? - 6'd19 : - (iFifo$D_OUT[141] ? - 6'd20 : - (iFifo$D_OUT[140] ? - 6'd21 : - (iFifo$D_OUT[139] ? - 6'd22 : - (iFifo$D_OUT[138] ? - 6'd23 : - (iFifo$D_OUT[137] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 = - { (iFifo$D_OUT[167:160] == 8'd255 && - iFifo$D_OUT[159:137] != 23'd0 || - (iFifo$D_OUT[167:160] == 8'd255 || - iFifo$D_OUT[167:160] == 8'd0) && - iFifo$D_OUT[159:137] == 23'd0) ? - iFifo$D_OUT[168] : - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665, - (iFifo$D_OUT[167:160] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h182416, - (iFifo$D_OUT[167:160] == 8'd255 && - iFifo$D_OUT[159:137] != 23'd0) ? - _theResult___snd_fst_sfd__h144486 : - _theResult___fst_sfd__h182420 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 = - ((iFifo$D_OUT[37:30] == 8'd0) ? - (iFifo$D_OUT[29] ? - 6'd2 : - (iFifo$D_OUT[28] ? - 6'd3 : - (iFifo$D_OUT[27] ? - 6'd4 : - (iFifo$D_OUT[26] ? - 6'd5 : - (iFifo$D_OUT[25] ? - 6'd6 : - (iFifo$D_OUT[24] ? - 6'd7 : - (iFifo$D_OUT[23] ? - 6'd8 : - (iFifo$D_OUT[22] ? - 6'd9 : - (iFifo$D_OUT[21] ? - 6'd10 : - (iFifo$D_OUT[20] ? - 6'd11 : - (iFifo$D_OUT[19] ? - 6'd12 : - (iFifo$D_OUT[18] ? - 6'd13 : - (iFifo$D_OUT[17] ? - 6'd14 : - (iFifo$D_OUT[16] ? - 6'd15 : - (iFifo$D_OUT[15] ? - 6'd16 : - (iFifo$D_OUT[14] ? - 6'd17 : - (iFifo$D_OUT[13] ? - 6'd18 : - (iFifo$D_OUT[12] ? - 6'd19 : - (iFifo$D_OUT[11] ? - 6'd20 : - (iFifo$D_OUT[10] ? - 6'd21 : - (iFifo$D_OUT[9] ? - 6'd22 : - (iFifo$D_OUT[8] ? - 6'd23 : - (iFifo$D_OUT[7] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 = - { (iFifo$D_OUT[37:30] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h259993, - (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0) ? - _theResult___snd_fst_sfd__h222065 : - _theResult___fst_sfd__h259997 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 = - { (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 || - (iFifo$D_OUT[37:30] == 8'd255 || - iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - iFifo$D_OUT[38] : - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 = - { (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 || - (iFifo$D_OUT[37:30] == 8'd255 || - iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - !iFifo$D_OUT[38] : - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ; - assign IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 = - iFifo$D_OUT[136] ? - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 : - iFifo$D_OUT[135:72] ; - assign IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 = - iFifo$D_OUT[201] ? - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 : - iFifo$D_OUT[200:137] ; - assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555 = - iFifo$D_OUT[71] ? - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 : - iFifo$D_OUT[70:7] ; - assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 = - iFifo$D_OUT[71] ? - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 : - { iFifo$D_OUT[71] || !iFifo$D_OUT[70], iFifo$D_OUT[69:7] } ; - assign IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657 = - isDoubleFifo$D_OUT ? - { isNegateFifo$D_OUT ^ resWire$wget[68], resWire$wget[67:5] } : - { 32'hAAAAAAAA, - IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424, - exp__h304706, - sfd__h304707 } ; - assign IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424 = - isNegateFifo$D_OUT ? - ((resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0 || - (resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - !resWire$wget[68] : - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377) : - ((resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0 || - (resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - resWire$wget[68] : - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 = - ((resWire$wget[67:57] == 11'd0) ? - (resWire$wget[56] ? - 6'd2 : - (resWire$wget[55] ? - 6'd3 : - (resWire$wget[54] ? - 6'd4 : - (resWire$wget[53] ? - 6'd5 : - (resWire$wget[52] ? - 6'd6 : - (resWire$wget[51] ? - 6'd7 : - (resWire$wget[50] ? - 6'd8 : - (resWire$wget[49] ? - 6'd9 : - (resWire$wget[48] ? - 6'd10 : - (resWire$wget[47] ? - 6'd11 : - (resWire$wget[46] ? - 6'd12 : - (resWire$wget[45] ? - 6'd13 : - (resWire$wget[44] ? - 6'd14 : - (resWire$wget[43] ? - 6'd15 : - (resWire$wget[42] ? - 6'd16 : - (resWire$wget[41] ? - 6'd17 : - (resWire$wget[40] ? - 6'd18 : - (resWire$wget[39] ? - 6'd19 : - (resWire$wget[38] ? - 6'd20 : - (resWire$wget[37] ? - 6'd21 : - (resWire$wget[36] ? - 6'd22 : - (resWire$wget[35] ? - 6'd23 : - (resWire$wget[34] ? - 6'd24 : - (resWire$wget[33] ? - 6'd25 : - (resWire$wget[32] ? - 6'd26 : - (resWire$wget[31] ? - 6'd27 : - (resWire$wget[30] ? - 6'd28 : - (resWire$wget[29] ? - 6'd29 : - (resWire$wget[28] ? - 6'd30 : - (resWire$wget[27] ? - 6'd31 : - (resWire$wget[26] ? - 6'd32 : - (resWire$wget[25] ? - 6'd33 : - (resWire$wget[24] ? - 6'd34 : - (resWire$wget[23] ? - 6'd35 : - (resWire$wget[22] ? - 6'd36 : - (resWire$wget[21] ? - 6'd37 : - (resWire$wget[20] ? - 6'd38 : - (resWire$wget[19] ? - 6'd39 : - (resWire$wget[18] ? - 6'd40 : - (resWire$wget[17] ? - 6'd41 : - (resWire$wget[16] ? - 6'd42 : - (resWire$wget[15] ? - 6'd43 : - (resWire$wget[14] ? - 6'd44 : - (resWire$wget[13] ? - 6'd45 : - (resWire$wget[12] ? - 6'd46 : - (resWire$wget[11] ? - 6'd47 : - (resWire$wget[10] ? - 6'd48 : - (resWire$wget[9] ? - 6'd49 : - (resWire$wget[8] ? - 6'd50 : - (resWire$wget[7] ? - 6'd51 : - (resWire$wget[6] ? - 6'd52 : - (resWire$wget[5] ? - 6'd53 : - 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[4] ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[3] ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736 = - (resWire$wget[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 : - !SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 || - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 = - (resWire$wget[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 : - !SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 || - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 = - rg_index_1_4_ULE_58___d38 ? _theResult___fst__h1515 : rg_b ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 = - rg_index_1_4_ULE_58___d38 ? - _theResult___snd_snd_snd__h1520 : - rg_r_1 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 = - rg_index_1_4_ULE_58___d38 ? - IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72 : - rg_res[115:0] ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 = - rg_index_1_4_ULE_58___d38 ? _theResult___snd_fst__h1517 : rg_s ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 < - sum__h1710 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 = - rg_index_1_4_ULE_58___d38 ? - rg_b != 116'd0 && !rg_res[116] : - !rg_res[116] ; - assign IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44 = - rg_index_1_4_ULE_58___d38 ? - rg_b == 116'd0 || rg_res[116] : - rg_res[116] ; - assign IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 = - rg_index_ULE_57___d7 ? - (rg_r[115] ? - { rg_r[114:0], 1'd0 } + b__h32583 : - { rg_r[114:0], 1'd0 } - b__h32583) : - rg_r ; - assign IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 = - rg_index_ULE_57___d7 ? { rg_q[56:0], !rg_r[115] } : rg_q ; - assign IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10 = - rg_r[115] ? - rg_q_PLUS_NEG_INV_rg_q_59_60___d561 - 58'd1 : - rg_q_PLUS_NEG_INV_rg_q_59_60___d561 ; - assign IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72 = - rg_res[116] ? - rg_res[115:0] : - ((rg_b == 116'd0) ? rg_r_1 : rg_res[115:0]) ; - assign IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98 = - sfdin__h211484[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13 = - sfdin__h42327[5] ? 2'd2 : 2'd0 ; - assign IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25 = - sfdin__h130943[53] ? 2'd2 : 2'd0 ; - assign IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30 = - sfdin__h141369[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20 = - sfdin__h94744[6] ? 2'd2 : 2'd0 ; - assign IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65 = - sfdin__h250423[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38 = - sfdin__h172846[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134 = - sfdin__h277680[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140 = - sfdin__h295446[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94 = - _theResult___snd__h201925[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143 = - _theResult___snd__h304083[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101 = - _theResult___snd__h220237[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61 = - _theResult___snd__h240864[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68 = - _theResult___snd__h259176[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34 = - _theResult___snd__h163287[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41 = - _theResult___snd__h181599[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136 = - _theResult___snd__h286293[33] ? 2'd2 : 2'd0 ; - assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 = - !_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 || - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[2] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 = - !_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 || - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[0] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[0]) ; - assign NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 = - (x__h96539 != 11'd2047 || !_theResult___fst_sfd__h96608[51]) && - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - !fpu_madd_fOperand_S0$D_OUT[118]) && - (fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - !fpu_madd_fOperand_S0$D_OUT[54]) && - (fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 && - !fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 = - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452 = - { NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 && - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436 ? - 52'h8000000000000 : - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450 } ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481 = - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 && - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488 = - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (!IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355) ; - assign NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923 = - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) && - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) && - (x__h96539 != 11'd2047 || - _theResult___fst_sfd__h96608 != 52'd0 || - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0) && - (fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) || - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) && - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 ; - assign NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 = - fpu_madd_fOperand_S0$D_OUT[130] != - fpu_madd_fOperand_S0$D_OUT[66] ; - assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510 = - !fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - (fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fState_S3$D_OUT[84] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[2]) ; - assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 = - { NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 : - fpu_madd_fState_S3$D_OUT[83], - !fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 } ; - assign NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 = - !fpu_madd_fState_S4$D_OUT[130] || - (IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 ^ - 13'h1000) > - (IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 ^ - 13'h1000) || - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 == - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 && - sfdBC__h131578 > sfdA__h131577 ; - assign NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 = - !iFifo$D_OUT[158] && !iFifo$D_OUT[157] && !iFifo$D_OUT[156] && - !iFifo$D_OUT[155] && - !iFifo$D_OUT[154] && - !iFifo$D_OUT[153] && - !iFifo$D_OUT[152] && - !iFifo$D_OUT[151] && - !iFifo$D_OUT[150] && - !iFifo$D_OUT[149] && - !iFifo$D_OUT[148] && - !iFifo$D_OUT[147] && - !iFifo$D_OUT[146] && - !iFifo$D_OUT[145] && - !iFifo$D_OUT[144] && - !iFifo$D_OUT[143] && - !iFifo$D_OUT[142] && - !iFifo$D_OUT[141] && - !iFifo$D_OUT[140] && - !iFifo$D_OUT[139] && - !iFifo$D_OUT[138] && - !iFifo$D_OUT[137] ; - assign NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 = - !iFifo$D_OUT[28] && !iFifo$D_OUT[27] && !iFifo$D_OUT[26] && - !iFifo$D_OUT[25] && - !iFifo$D_OUT[24] && - !iFifo$D_OUT[23] && - !iFifo$D_OUT[22] && - !iFifo$D_OUT[21] && - !iFifo$D_OUT[20] && - !iFifo$D_OUT[19] && - !iFifo$D_OUT[18] && - !iFifo$D_OUT[17] && - !iFifo$D_OUT[16] && - !iFifo$D_OUT[15] && - !iFifo$D_OUT[14] && - !iFifo$D_OUT[13] && - !iFifo$D_OUT[12] && - !iFifo$D_OUT[11] && - !iFifo$D_OUT[10] && - !iFifo$D_OUT[9] && - !iFifo$D_OUT[8] && - !iFifo$D_OUT[7] ; - assign NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 = - !iFifo$D_OUT[93] && !iFifo$D_OUT[92] && !iFifo$D_OUT[91] && - !iFifo$D_OUT[90] && - !iFifo$D_OUT[89] && - !iFifo$D_OUT[88] && - !iFifo$D_OUT[87] && - !iFifo$D_OUT[86] && - !iFifo$D_OUT[85] && - !iFifo$D_OUT[84] && - !iFifo$D_OUT[83] && - !iFifo$D_OUT[82] && - !iFifo$D_OUT[81] && - !iFifo$D_OUT[80] && - !iFifo$D_OUT[79] && - !iFifo$D_OUT[78] && - !iFifo$D_OUT[77] && - !iFifo$D_OUT[76] && - !iFifo$D_OUT[75] && - !iFifo$D_OUT[74] && - !iFifo$D_OUT[73] && - !iFifo$D_OUT[72] ; - assign NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 = - !resWire$wget[56] && !resWire$wget[55] && !resWire$wget[54] && - !resWire$wget[53] && - !resWire$wget[52] && - !resWire$wget[51] && - !resWire$wget[50] && - !resWire$wget[49] && - !resWire$wget[48] && - !resWire$wget[47] && - !resWire$wget[46] && - !resWire$wget[45] && - !resWire$wget[44] && - !resWire$wget[43] && - !resWire$wget[42] && - !resWire$wget[41] && - !resWire$wget[40] && - !resWire$wget[39] && - !resWire$wget[38] && - !resWire$wget[37] && - !resWire$wget[36] && - !resWire$wget[35] && - !resWire$wget[34] && - !resWire$wget[33] && - !resWire$wget[32] && - !resWire$wget[31] && - !resWire$wget[30] && - !resWire$wget[29] && - !resWire$wget[28] && - !resWire$wget[27] && - !resWire$wget[26] && - !resWire$wget[25] && - !resWire$wget[24] && - !resWire$wget[23] && - !resWire$wget[22] && - !resWire$wget[21] && - !resWire$wget[20] && - !resWire$wget[19] && - !resWire$wget[18] && - !resWire$wget[17] && - !resWire$wget[16] && - !resWire$wget[15] && - !resWire$wget[14] && - !resWire$wget[13] && - !resWire$wget[12] && - !resWire$wget[11] && - !resWire$wget[10] && - !resWire$wget[9] && - !resWire$wget[8] && - !resWire$wget[7] && - !resWire$wget[6] && - !resWire$wget[5] ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 = - { {4{iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95[7]}}, - iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 } ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] - - 11'd1023 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 = - { {4{iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35[7]}}, - iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 } ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] - - 11'd1023 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 = - { {4{iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62[7]}}, - iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 } ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] - - 11'd1023 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 = - { resWirewget_BITS_67_TO_57_MINUS_1023__q137[10], - resWirewget_BITS_67_TO_57_MINUS_1023__q137 } ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 + - 12'd127 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] - - 8'd127 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 = - ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676 = - { 3'd0, - _theResult___fst_exp__h277686 == 8'd0 && - (sfdin__h277680[56:34] == 23'd0 || guard__h269587 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h278283 == 8'd255 && - _theResult___fst_sfd__h278284 == 23'd0, - 1'd0, - _theResult___fst_exp__h277686 != 8'd255 && - guard__h269587 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 = - ({ 3'd0, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705 = - { 3'd0, - _theResult___fst_exp__h295452 == 8'd0 && - (sfdin__h295446[56:34] == 23'd0 || guard__h287224 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h296049 == 8'd255 && - _theResult___fst_sfd__h296050 == 23'd0, - 1'd0, - _theResult___fst_exp__h295452 != 8'd255 && - guard__h287224 != 2'b0 } ; - assign _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 = - ({ 5'd0, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ^ - 12'h800) <= - (IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883 = - ({ 6'd0, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 } ^ - 12'h800) <= - (IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 = - ({ 6'd0, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ^ - 12'h800) <= - (IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ^ - 12'h800) ; - assign _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633 = - ({ 6'd0, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 } ^ - 12'h800) <= - (IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 = - ({ 6'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 = - ({ 6'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 = - ({ 6'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 = - ({ 6'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 = - ({ 6'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 = - ({ 6'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ^ - 12'h800) ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 = - ({ 3'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 = - ({ 3'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^ - 9'h100) <= - (IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ^ - 9'h100) ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688 = - { 3'd0, - _theResult___fst_exp__h286342 == 8'd0 && - guard__h278294 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h286865 == 8'd255 && - _theResult___fst_sfd__h286866 == 23'd0, - 1'd0, - _theResult___fst_exp__h286342 != 8'd255 && - guard__h278294 != 2'b0 } ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813 = - sfd__h183176 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330 = - sfd__h144536 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038 = - sfd__h222115 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ; - assign _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038 = - sfd__h261975 >> - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 = - 12'd3074 - - { 6'd0, - resWire$wget[56] ? - 6'd0 : - (resWire$wget[55] ? - 6'd1 : - (resWire$wget[54] ? - 6'd2 : - (resWire$wget[53] ? - 6'd3 : - (resWire$wget[52] ? - 6'd4 : - (resWire$wget[51] ? - 6'd5 : - (resWire$wget[50] ? - 6'd6 : - (resWire$wget[49] ? - 6'd7 : - (resWire$wget[48] ? - 6'd8 : - (resWire$wget[47] ? - 6'd9 : - (resWire$wget[46] ? - 6'd10 : - (resWire$wget[45] ? - 6'd11 : - (resWire$wget[44] ? - 6'd12 : - (resWire$wget[43] ? - 6'd13 : - (resWire$wget[42] ? - 6'd14 : - (resWire$wget[41] ? - 6'd15 : - (resWire$wget[40] ? - 6'd16 : - (resWire$wget[39] ? - 6'd17 : - (resWire$wget[38] ? - 6'd18 : - (resWire$wget[37] ? - 6'd19 : - (resWire$wget[36] ? - 6'd20 : - (resWire$wget[35] ? - 6'd21 : - (resWire$wget[34] ? - 6'd22 : - (resWire$wget[33] ? - 6'd23 : - (resWire$wget[32] ? - 6'd24 : - (resWire$wget[31] ? - 6'd25 : - (resWire$wget[30] ? - 6'd26 : - (resWire$wget[29] ? - 6'd27 : - (resWire$wget[28] ? - 6'd28 : - (resWire$wget[27] ? - 6'd29 : - (resWire$wget[26] ? - 6'd30 : - (resWire$wget[25] ? - 6'd31 : - (resWire$wget[24] ? - 6'd32 : - (resWire$wget[23] ? - 6'd33 : - (resWire$wget[22] ? - 6'd34 : - (resWire$wget[21] ? - 6'd35 : - (resWire$wget[20] ? - 6'd36 : - (resWire$wget[19] ? - 6'd37 : - (resWire$wget[18] ? - 6'd38 : - (resWire$wget[17] ? - 6'd39 : - (resWire$wget[16] ? - 6'd40 : - (resWire$wget[15] ? - 6'd41 : - (resWire$wget[14] ? - 6'd42 : - (resWire$wget[13] ? - 6'd43 : - (resWire$wget[12] ? - 6'd44 : - (resWire$wget[11] ? - 6'd45 : - (resWire$wget[10] ? - 6'd46 : - (resWire$wget[9] ? - 6'd47 : - (resWire$wget[8] ? - 6'd48 : - (resWire$wget[7] ? - 6'd49 : - (resWire$wget[6] ? - 6'd50 : - (resWire$wget[5] ? - 6'd51 : - 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 = - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^ - 12'h800) <= - 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 = - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^ - 12'h800) < - 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[4] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[4]) ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[3] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[3]) ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[1] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[1]) ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[159] ? - 5'd0 : - (iFifo$D_OUT[158] ? - 5'd1 : - (iFifo$D_OUT[157] ? - 5'd2 : - (iFifo$D_OUT[156] ? - 5'd3 : - (iFifo$D_OUT[155] ? - 5'd4 : - (iFifo$D_OUT[154] ? - 5'd5 : - (iFifo$D_OUT[153] ? - 5'd6 : - (iFifo$D_OUT[152] ? - 5'd7 : - (iFifo$D_OUT[151] ? - 5'd8 : - (iFifo$D_OUT[150] ? - 5'd9 : - (iFifo$D_OUT[149] ? - 5'd10 : - (iFifo$D_OUT[148] ? - 5'd11 : - (iFifo$D_OUT[147] ? - 5'd12 : - (iFifo$D_OUT[146] ? - 5'd13 : - (iFifo$D_OUT[145] ? - 5'd14 : - (iFifo$D_OUT[144] ? - 5'd15 : - (iFifo$D_OUT[143] ? - 5'd16 : - (iFifo$D_OUT[142] ? - 5'd17 : - (iFifo$D_OUT[141] ? - 5'd18 : - (iFifo$D_OUT[140] ? - 5'd19 : - (iFifo$D_OUT[139] ? - 5'd20 : - (iFifo$D_OUT[138] ? - 5'd21 : - (iFifo$D_OUT[137] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[29] ? - 5'd0 : - (iFifo$D_OUT[28] ? - 5'd1 : - (iFifo$D_OUT[27] ? - 5'd2 : - (iFifo$D_OUT[26] ? - 5'd3 : - (iFifo$D_OUT[25] ? - 5'd4 : - (iFifo$D_OUT[24] ? - 5'd5 : - (iFifo$D_OUT[23] ? - 5'd6 : - (iFifo$D_OUT[22] ? - 5'd7 : - (iFifo$D_OUT[21] ? - 5'd8 : - (iFifo$D_OUT[20] ? - 5'd9 : - (iFifo$D_OUT[19] ? - 5'd10 : - (iFifo$D_OUT[18] ? - 5'd11 : - (iFifo$D_OUT[17] ? - 5'd12 : - (iFifo$D_OUT[16] ? - 5'd13 : - (iFifo$D_OUT[15] ? - 5'd14 : - (iFifo$D_OUT[14] ? - 5'd15 : - (iFifo$D_OUT[13] ? - 5'd16 : - (iFifo$D_OUT[12] ? - 5'd17 : - (iFifo$D_OUT[11] ? - 5'd18 : - (iFifo$D_OUT[10] ? - 5'd19 : - (iFifo$D_OUT[9] ? - 5'd20 : - (iFifo$D_OUT[8] ? - 5'd21 : - (iFifo$D_OUT[7] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[94] ? - 5'd0 : - (iFifo$D_OUT[93] ? - 5'd1 : - (iFifo$D_OUT[92] ? - 5'd2 : - (iFifo$D_OUT[91] ? - 5'd3 : - (iFifo$D_OUT[90] ? - 5'd4 : - (iFifo$D_OUT[89] ? - 5'd5 : - (iFifo$D_OUT[88] ? - 5'd6 : - (iFifo$D_OUT[87] ? - 5'd7 : - (iFifo$D_OUT[86] ? - 5'd8 : - (iFifo$D_OUT[85] ? - 5'd9 : - (iFifo$D_OUT[84] ? - 5'd10 : - (iFifo$D_OUT[83] ? - 5'd11 : - (iFifo$D_OUT[82] ? - 5'd12 : - (iFifo$D_OUT[81] ? - 5'd13 : - (iFifo$D_OUT[80] ? - 5'd14 : - (iFifo$D_OUT[79] ? - 5'd15 : - (iFifo$D_OUT[78] ? - 5'd16 : - (iFifo$D_OUT[77] ? - 5'd17 : - (iFifo$D_OUT[76] ? - 5'd18 : - (iFifo$D_OUT[75] ? - 5'd19 : - (iFifo$D_OUT[74] ? - 5'd20 : - (iFifo$D_OUT[73] ? - 5'd21 : - (iFifo$D_OUT[72] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 = - 12'd3970 - - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ; - assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 = - 13'd7170 - fpu_madd_fState_S3$D_OUT[12:0] ; - assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 = - (_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ^ - 13'h1000) <= - 13'd4096 ; - assign _theResult____h164614 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ^ - 12'h800) < - 12'd2105) ? - result__h165227 : - ((value__h148923 == 25'd0) ? sfd__h144536 : 57'd1) ; - assign _theResult____h203252 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ^ - 12'h800) < - 12'd2105) ? - result__h203865 : - ((value__h187561 == 25'd0) ? sfd__h183176 : 57'd1) ; - assign _theResult____h242191 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ^ - 12'h800) < - 12'd2105) ? - result__h242804 : - ((value__h226500 == 25'd0) ? sfd__h222115 : 57'd1) ; - assign _theResult____h269577 = - (value__h270197 == 54'd0) ? sfd__h261975 : 57'd1 ; - assign _theResult____h287214 = - ((_3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ^ - 12'h800) < - 12'd2105) ? - result__h287827 : - _theResult____h269577 ; - assign _theResult____h32523 = - (fpu_div64_fState_S2$D_OUT[10:0] < 11'd58) ? - result__h32648 : - result__h32823 ; - assign _theResult___exp__h142541 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h142626) : - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 ; - assign _theResult___exp__h163981 = - sfd__h163354[53] ? - ((_theResult___fst_exp__h163336 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182469) : - ((_theResult___fst_exp__h163336 == 11'd0 && - sfd__h163354[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h163336) ; - assign _theResult___exp__h173571 = - sfd__h172944[53] ? - ((_theResult___fst_exp__h172852 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182504) : - ((_theResult___fst_exp__h172852 == 11'd0 && - sfd__h172944[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h172852) ; - assign _theResult___exp__h182323 = - sfd__h181672[53] ? - ((_theResult___fst_exp__h181653 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182530) : - ((_theResult___fst_exp__h181653 == 11'd0 && - sfd__h181672[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h181653) ; - assign _theResult___exp__h202619 = - sfd__h201992[53] ? - ((_theResult___fst_exp__h201974 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221107) : - ((_theResult___fst_exp__h201974 == 11'd0 && - sfd__h201992[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h201974) ; - assign _theResult___exp__h212209 = - sfd__h211582[53] ? - ((_theResult___fst_exp__h211490 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221142) : - ((_theResult___fst_exp__h211490 == 11'd0 && - sfd__h211582[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h211490) ; - assign _theResult___exp__h220961 = - sfd__h220310[53] ? - ((_theResult___fst_exp__h220291 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221168) : - ((_theResult___fst_exp__h220291 == 11'd0 && - sfd__h220310[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h220291) ; - assign _theResult___exp__h241558 = - sfd__h240931[53] ? - ((_theResult___fst_exp__h240913 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260046) : - ((_theResult___fst_exp__h240913 == 11'd0 && - sfd__h240931[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h240913) ; - assign _theResult___exp__h251148 = - sfd__h250521[53] ? - ((_theResult___fst_exp__h250429 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260081) : - ((_theResult___fst_exp__h250429 == 11'd0 && - sfd__h250521[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h250429) ; - assign _theResult___exp__h259900 = - sfd__h259249[53] ? - ((_theResult___fst_exp__h259230 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260107) : - ((_theResult___fst_exp__h259230 == 11'd0 && - sfd__h259249[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h259230) ; - assign _theResult___exp__h278202 = - sfd__h277778[24] ? - ((_theResult___fst_exp__h277686 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304723) : - ((_theResult___fst_exp__h277686 == 8'd0 && - sfd__h277778[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h277686) ; - assign _theResult___exp__h286784 = - sfd__h286360[24] ? - ((_theResult___fst_exp__h286342 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304749) : - ((_theResult___fst_exp__h286342 == 8'd0 && - sfd__h286360[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h286342) ; - assign _theResult___exp__h295968 = - sfd__h295544[24] ? - ((_theResult___fst_exp__h295452 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304784) : - ((_theResult___fst_exp__h295452 == 8'd0 && - sfd__h295544[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h295452) ; - assign _theResult___exp__h304604 = - sfd__h304156[24] ? - ((_theResult___fst_exp__h304137 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304810) : - ((_theResult___fst_exp__h304137 == 8'd0 && - sfd__h304156[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h304137) ; - assign _theResult___exp__h43475 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h43566) : - IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977 ; - assign _theResult___exp__h95909 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h96000) : - IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721 ; - assign _theResult___fst__h116827 = - { fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[105:1], - fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[0] | - sfdlsb__h116825 } ; - assign _theResult___fst__h1476 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___fst__h1600 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign _theResult___fst__h1515 = - (rg_res[116] || rg_b == 116'd0) ? rg_b : b__h1608 ; - assign _theResult___fst__h1600 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 : - b__h1712 ; - assign _theResult___fst__h31322 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499 ? - value__h31550[10:0] : - 11'd0 ; - assign _theResult___fst_exp__h130949 = - sfdBC__h115662[105] ? - _theResult___fst_exp__h130971 : - _theResult___fst_exp__h131034 ; - assign _theResult___fst_exp__h130952 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h130949 ; - assign _theResult___fst_exp__h130971 = - (din_exp__h130866 == 11'd0) ? 11'd2 : din_exp__h130866 + 11'd1 ; - assign _theResult___fst_exp__h130986 = - (din_exp__h130866 == 11'd0) ? 11'd1 : din_exp__h130866 ; - assign _theResult___fst_exp__h131025 = - din_exp__h130866 - - { 4'd0, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ; - assign _theResult___fst_exp__h131031 = - (!sfdBC__h115662[105] && !sfdBC__h115662[104] && - !sfdBC__h115662[103] && - !sfdBC__h115662[102] && - !sfdBC__h115662[101] && - !sfdBC__h115662[100] && - !sfdBC__h115662[99] && - !sfdBC__h115662[98] && - !sfdBC__h115662[97] && - !sfdBC__h115662[96] && - !sfdBC__h115662[95] && - !sfdBC__h115662[94] && - !sfdBC__h115662[93] && - !sfdBC__h115662[92] && - !sfdBC__h115662[91] && - !sfdBC__h115662[90] && - !sfdBC__h115662[89] && - !sfdBC__h115662[88] && - !sfdBC__h115662[87] && - !sfdBC__h115662[86] && - !sfdBC__h115662[85] && - !sfdBC__h115662[84] && - !sfdBC__h115662[83] && - !sfdBC__h115662[82] && - !sfdBC__h115662[81] && - !sfdBC__h115662[80] && - !sfdBC__h115662[79] && - !sfdBC__h115662[78] && - !sfdBC__h115662[77] && - !sfdBC__h115662[76] && - !sfdBC__h115662[75] && - !sfdBC__h115662[74] && - !sfdBC__h115662[73] && - !sfdBC__h115662[72] && - !sfdBC__h115662[71] && - !sfdBC__h115662[70] && - !sfdBC__h115662[69] && - !sfdBC__h115662[68] && - !sfdBC__h115662[67] && - !sfdBC__h115662[66] && - !sfdBC__h115662[65] && - !sfdBC__h115662[64] && - !sfdBC__h115662[63] && - !sfdBC__h115662[62] && - !sfdBC__h115662[61] && - !sfdBC__h115662[60] && - !sfdBC__h115662[59] && - !sfdBC__h115662[58] && - !sfdBC__h115662[57] && - !sfdBC__h115662[56] && - !sfdBC__h115662[55] && - !sfdBC__h115662[54] && - !sfdBC__h115662[53] && - !sfdBC__h115662[52] && - !sfdBC__h115662[51] && - !sfdBC__h115662[50] && - !sfdBC__h115662[49] && - !sfdBC__h115662[48] && - !sfdBC__h115662[47] && - !sfdBC__h115662[46] && - !sfdBC__h115662[45] && - !sfdBC__h115662[44] && - !sfdBC__h115662[43] && - !sfdBC__h115662[42] && - !sfdBC__h115662[41] && - !sfdBC__h115662[40] && - !sfdBC__h115662[39] && - !sfdBC__h115662[38] && - !sfdBC__h115662[37] && - !sfdBC__h115662[36] && - !sfdBC__h115662[35] && - !sfdBC__h115662[34] && - !sfdBC__h115662[33] && - !sfdBC__h115662[32] && - !sfdBC__h115662[31] && - !sfdBC__h115662[30] && - !sfdBC__h115662[29] && - !sfdBC__h115662[28] && - !sfdBC__h115662[27] && - !sfdBC__h115662[26] && - !sfdBC__h115662[25] && - !sfdBC__h115662[24] && - !sfdBC__h115662[23] && - !sfdBC__h115662[22] && - !sfdBC__h115662[21] && - !sfdBC__h115662[20] && - !sfdBC__h115662[19] && - !sfdBC__h115662[18] && - !sfdBC__h115662[17] && - !sfdBC__h115662[16] && - !sfdBC__h115662[15] && - !sfdBC__h115662[14] && - !sfdBC__h115662[13] && - !sfdBC__h115662[12] && - !sfdBC__h115662[11] && - !sfdBC__h115662[10] && - !sfdBC__h115662[9] && - !sfdBC__h115662[8] && - !sfdBC__h115662[7] && - !sfdBC__h115662[6] && - !sfdBC__h115662[5] && - !sfdBC__h115662[4] && - !sfdBC__h115662[3] && - !sfdBC__h115662[2] && - !sfdBC__h115662[1] && - !sfdBC__h115662[0] || - !_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463) ? - 11'd0 : - _theResult___fst_exp__h131025 ; - assign _theResult___fst_exp__h131034 = - (!sfdBC__h115662[105] && sfdBC__h115662[104]) ? - _theResult___fst_exp__h130986 : - _theResult___fst_exp__h131031 ; - assign _theResult___fst_exp__h141375 = - sfd__h133119[56] ? - _theResult___fst_exp__h141397 : - _theResult___fst_exp__h141460 ; - assign _theResult___fst_exp__h141378 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h141375 ; - assign _theResult___fst_exp__h141397 = - (value__h141307[10:0] == 11'd0) ? - 11'd2 : - value__h141307[10:0] + 11'd1 ; - assign _theResult___fst_exp__h141412 = - (value__h141307[10:0] == 11'd0) ? 11'd1 : value__h141307[10:0] ; - assign _theResult___fst_exp__h141451 = - value__h141307[10:0] - - { 5'd0, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ; - assign _theResult___fst_exp__h141457 = - (!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] && - !sfd__h133119[53] && - !sfd__h133119[52] && - !sfd__h133119[51] && - !sfd__h133119[50] && - !sfd__h133119[49] && - !sfd__h133119[48] && - !sfd__h133119[47] && - !sfd__h133119[46] && - !sfd__h133119[45] && - !sfd__h133119[44] && - !sfd__h133119[43] && - !sfd__h133119[42] && - !sfd__h133119[41] && - !sfd__h133119[40] && - !sfd__h133119[39] && - !sfd__h133119[38] && - !sfd__h133119[37] && - !sfd__h133119[36] && - !sfd__h133119[35] && - !sfd__h133119[34] && - !sfd__h133119[33] && - !sfd__h133119[32] && - !sfd__h133119[31] && - !sfd__h133119[30] && - !sfd__h133119[29] && - !sfd__h133119[28] && - !sfd__h133119[27] && - !sfd__h133119[26] && - !sfd__h133119[25] && - !sfd__h133119[24] && - !sfd__h133119[23] && - !sfd__h133119[22] && - !sfd__h133119[21] && - !sfd__h133119[20] && - !sfd__h133119[19] && - !sfd__h133119[18] && - !sfd__h133119[17] && - !sfd__h133119[16] && - !sfd__h133119[15] && - !sfd__h133119[14] && - !sfd__h133119[13] && - !sfd__h133119[12] && - !sfd__h133119[11] && - !sfd__h133119[10] && - !sfd__h133119[9] && - !sfd__h133119[8] && - !sfd__h133119[7] && - !sfd__h133119[6] && - !sfd__h133119[5] && - !sfd__h133119[4] && - !sfd__h133119[3] && - !sfd__h133119[2] && - !sfd__h133119[1] && - !sfd__h133119[0] || - !_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904) ? - 11'd0 : - _theResult___fst_exp__h141451 ; - assign _theResult___fst_exp__h141460 = - (!sfd__h133119[56] && sfd__h133119[55]) ? - _theResult___fst_exp__h141412 : - _theResult___fst_exp__h141457 ; - assign _theResult___fst_exp__h163327 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ; - assign _theResult___fst_exp__h163333 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 || - !_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273) ? - 11'd0 : - _theResult___fst_exp__h163327 ; - assign _theResult___fst_exp__h163336 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___fst_exp__h163333 : - 11'd897 ; - assign _theResult___fst_exp__h164062 = - (_theResult___fst_exp__h163336 == 11'd2047) ? - _theResult___fst_exp__h163336 : - _theResult___fst_exp__h164059 ; - assign _theResult___fst_exp__h172852 = - _theResult____h164614[56] ? - 11'd2 : - _theResult___fst_exp__h172926 ; - assign _theResult___fst_exp__h172917 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ; - assign _theResult___fst_exp__h172923 = - (!_theResult____h164614[56] && !_theResult____h164614[55] && - !_theResult____h164614[54] && - !_theResult____h164614[53] && - !_theResult____h164614[52] && - !_theResult____h164614[51] && - !_theResult____h164614[50] && - !_theResult____h164614[49] && - !_theResult____h164614[48] && - !_theResult____h164614[47] && - !_theResult____h164614[46] && - !_theResult____h164614[45] && - !_theResult____h164614[44] && - !_theResult____h164614[43] && - !_theResult____h164614[42] && - !_theResult____h164614[41] && - !_theResult____h164614[40] && - !_theResult____h164614[39] && - !_theResult____h164614[38] && - !_theResult____h164614[37] && - !_theResult____h164614[36] && - !_theResult____h164614[35] && - !_theResult____h164614[34] && - !_theResult____h164614[33] && - !_theResult____h164614[32] && - !_theResult____h164614[31] && - !_theResult____h164614[30] && - !_theResult____h164614[29] && - !_theResult____h164614[28] && - !_theResult____h164614[27] && - !_theResult____h164614[26] && - !_theResult____h164614[25] && - !_theResult____h164614[24] && - !_theResult____h164614[23] && - !_theResult____h164614[22] && - !_theResult____h164614[21] && - !_theResult____h164614[20] && - !_theResult____h164614[19] && - !_theResult____h164614[18] && - !_theResult____h164614[17] && - !_theResult____h164614[16] && - !_theResult____h164614[15] && - !_theResult____h164614[14] && - !_theResult____h164614[13] && - !_theResult____h164614[12] && - !_theResult____h164614[11] && - !_theResult____h164614[10] && - !_theResult____h164614[9] && - !_theResult____h164614[8] && - !_theResult____h164614[7] && - !_theResult____h164614[6] && - !_theResult____h164614[5] && - !_theResult____h164614[4] && - !_theResult____h164614[3] && - !_theResult____h164614[2] && - !_theResult____h164614[1] && - !_theResult____h164614[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574) ? - 11'd0 : - _theResult___fst_exp__h172917 ; - assign _theResult___fst_exp__h172926 = - (!_theResult____h164614[56] && _theResult____h164614[55]) ? - 11'd1 : - _theResult___fst_exp__h172923 ; - assign _theResult___fst_exp__h173652 = - (_theResult___fst_exp__h172852 == 11'd2047) ? - _theResult___fst_exp__h172852 : - _theResult___fst_exp__h173649 ; - assign _theResult___fst_exp__h181605 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] ; - assign _theResult___fst_exp__h181644 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ; - assign _theResult___fst_exp__h181650 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 || - !_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624) ? - 11'd0 : - _theResult___fst_exp__h181644 ; - assign _theResult___fst_exp__h181653 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___fst_exp__h181650 : - _theResult___fst_exp__h181605 ; - assign _theResult___fst_exp__h182404 = - (_theResult___fst_exp__h181653 == 11'd2047) ? - _theResult___fst_exp__h181653 : - _theResult___fst_exp__h182401 ; - assign _theResult___fst_exp__h182413 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - _theResult___snd_fst_exp__h164065 : - _theResult___fst_exp__h148291) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - _theResult___snd_fst_exp__h182407 : - _theResult___fst_exp__h148291) ; - assign _theResult___fst_exp__h182416 = - (iFifo$D_OUT[167:160] == 8'd0 && iFifo$D_OUT[159:137] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h182413 ; - assign _theResult___fst_exp__h201965 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ; - assign _theResult___fst_exp__h201971 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 || - !_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759) ? - 11'd0 : - _theResult___fst_exp__h201965 ; - assign _theResult___fst_exp__h201974 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___fst_exp__h201971 : - 11'd897 ; - assign _theResult___fst_exp__h202700 = - (_theResult___fst_exp__h201974 == 11'd2047) ? - _theResult___fst_exp__h201974 : - _theResult___fst_exp__h202697 ; - assign _theResult___fst_exp__h211490 = - _theResult____h203252[56] ? - 11'd2 : - _theResult___fst_exp__h211564 ; - assign _theResult___fst_exp__h211555 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ; - assign _theResult___fst_exp__h211561 = - (!_theResult____h203252[56] && !_theResult____h203252[55] && - !_theResult____h203252[54] && - !_theResult____h203252[53] && - !_theResult____h203252[52] && - !_theResult____h203252[51] && - !_theResult____h203252[50] && - !_theResult____h203252[49] && - !_theResult____h203252[48] && - !_theResult____h203252[47] && - !_theResult____h203252[46] && - !_theResult____h203252[45] && - !_theResult____h203252[44] && - !_theResult____h203252[43] && - !_theResult____h203252[42] && - !_theResult____h203252[41] && - !_theResult____h203252[40] && - !_theResult____h203252[39] && - !_theResult____h203252[38] && - !_theResult____h203252[37] && - !_theResult____h203252[36] && - !_theResult____h203252[35] && - !_theResult____h203252[34] && - !_theResult____h203252[33] && - !_theResult____h203252[32] && - !_theResult____h203252[31] && - !_theResult____h203252[30] && - !_theResult____h203252[29] && - !_theResult____h203252[28] && - !_theResult____h203252[27] && - !_theResult____h203252[26] && - !_theResult____h203252[25] && - !_theResult____h203252[24] && - !_theResult____h203252[23] && - !_theResult____h203252[22] && - !_theResult____h203252[21] && - !_theResult____h203252[20] && - !_theResult____h203252[19] && - !_theResult____h203252[18] && - !_theResult____h203252[17] && - !_theResult____h203252[16] && - !_theResult____h203252[15] && - !_theResult____h203252[14] && - !_theResult____h203252[13] && - !_theResult____h203252[12] && - !_theResult____h203252[11] && - !_theResult____h203252[10] && - !_theResult____h203252[9] && - !_theResult____h203252[8] && - !_theResult____h203252[7] && - !_theResult____h203252[6] && - !_theResult____h203252[5] && - !_theResult____h203252[4] && - !_theResult____h203252[3] && - !_theResult____h203252[2] && - !_theResult____h203252[1] && - !_theResult____h203252[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057) ? - 11'd0 : - _theResult___fst_exp__h211555 ; - assign _theResult___fst_exp__h211564 = - (!_theResult____h203252[56] && _theResult____h203252[55]) ? - 11'd1 : - _theResult___fst_exp__h211561 ; - assign _theResult___fst_exp__h212290 = - (_theResult___fst_exp__h211490 == 11'd2047) ? - _theResult___fst_exp__h211490 : - _theResult___fst_exp__h212287 ; - assign _theResult___fst_exp__h220243 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] ; - assign _theResult___fst_exp__h220282 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ; - assign _theResult___fst_exp__h220288 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 || - !_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107) ? - 11'd0 : - _theResult___fst_exp__h220282 ; - assign _theResult___fst_exp__h220291 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___fst_exp__h220288 : - _theResult___fst_exp__h220243 ; - assign _theResult___fst_exp__h221042 = - (_theResult___fst_exp__h220291 == 11'd2047) ? - _theResult___fst_exp__h220291 : - _theResult___fst_exp__h221039 ; - assign _theResult___fst_exp__h221051 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - _theResult___snd_fst_exp__h202703 : - _theResult___fst_exp__h186931) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - _theResult___snd_fst_exp__h221045 : - _theResult___fst_exp__h186931) ; - assign _theResult___fst_exp__h221054 = - (iFifo$D_OUT[102:95] == 8'd0 && iFifo$D_OUT[94:72] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h221051 ; - assign _theResult___fst_exp__h240904 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ; - assign _theResult___fst_exp__h240910 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 || - !_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984) ? - 11'd0 : - _theResult___fst_exp__h240904 ; - assign _theResult___fst_exp__h240913 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___fst_exp__h240910 : - 11'd897 ; - assign _theResult___fst_exp__h241639 = - (_theResult___fst_exp__h240913 == 11'd2047) ? - _theResult___fst_exp__h240913 : - _theResult___fst_exp__h241636 ; - assign _theResult___fst_exp__h250429 = - _theResult____h242191[56] ? - 11'd2 : - _theResult___fst_exp__h250503 ; - assign _theResult___fst_exp__h250494 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ; - assign _theResult___fst_exp__h250500 = - (!_theResult____h242191[56] && !_theResult____h242191[55] && - !_theResult____h242191[54] && - !_theResult____h242191[53] && - !_theResult____h242191[52] && - !_theResult____h242191[51] && - !_theResult____h242191[50] && - !_theResult____h242191[49] && - !_theResult____h242191[48] && - !_theResult____h242191[47] && - !_theResult____h242191[46] && - !_theResult____h242191[45] && - !_theResult____h242191[44] && - !_theResult____h242191[43] && - !_theResult____h242191[42] && - !_theResult____h242191[41] && - !_theResult____h242191[40] && - !_theResult____h242191[39] && - !_theResult____h242191[38] && - !_theResult____h242191[37] && - !_theResult____h242191[36] && - !_theResult____h242191[35] && - !_theResult____h242191[34] && - !_theResult____h242191[33] && - !_theResult____h242191[32] && - !_theResult____h242191[31] && - !_theResult____h242191[30] && - !_theResult____h242191[29] && - !_theResult____h242191[28] && - !_theResult____h242191[27] && - !_theResult____h242191[26] && - !_theResult____h242191[25] && - !_theResult____h242191[24] && - !_theResult____h242191[23] && - !_theResult____h242191[22] && - !_theResult____h242191[21] && - !_theResult____h242191[20] && - !_theResult____h242191[19] && - !_theResult____h242191[18] && - !_theResult____h242191[17] && - !_theResult____h242191[16] && - !_theResult____h242191[15] && - !_theResult____h242191[14] && - !_theResult____h242191[13] && - !_theResult____h242191[12] && - !_theResult____h242191[11] && - !_theResult____h242191[10] && - !_theResult____h242191[9] && - !_theResult____h242191[8] && - !_theResult____h242191[7] && - !_theResult____h242191[6] && - !_theResult____h242191[5] && - !_theResult____h242191[4] && - !_theResult____h242191[3] && - !_theResult____h242191[2] && - !_theResult____h242191[1] && - !_theResult____h242191[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282) ? - 11'd0 : - _theResult___fst_exp__h250494 ; - assign _theResult___fst_exp__h250503 = - (!_theResult____h242191[56] && _theResult____h242191[55]) ? - 11'd1 : - _theResult___fst_exp__h250500 ; - assign _theResult___fst_exp__h251229 = - (_theResult___fst_exp__h250429 == 11'd2047) ? - _theResult___fst_exp__h250429 : - _theResult___fst_exp__h251226 ; - assign _theResult___fst_exp__h259182 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] ; - assign _theResult___fst_exp__h259221 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ; - assign _theResult___fst_exp__h259227 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 || - !_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332) ? - 11'd0 : - _theResult___fst_exp__h259221 ; - assign _theResult___fst_exp__h259230 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___fst_exp__h259227 : - _theResult___fst_exp__h259182 ; - assign _theResult___fst_exp__h259981 = - (_theResult___fst_exp__h259230 == 11'd2047) ? - _theResult___fst_exp__h259230 : - _theResult___fst_exp__h259978 ; - assign _theResult___fst_exp__h259990 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - _theResult___snd_fst_exp__h241642 : - _theResult___fst_exp__h225870) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - _theResult___snd_fst_exp__h259984 : - _theResult___fst_exp__h225870) ; - assign _theResult___fst_exp__h259993 = - (iFifo$D_OUT[37:30] == 8'd0 && iFifo$D_OUT[29:7] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h259990 ; - assign _theResult___fst_exp__h277686 = - _theResult____h269577[56] ? - 8'd2 : - _theResult___fst_exp__h277760 ; - assign _theResult___fst_exp__h277751 = - 8'd0 - - { 2'd0, - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ; - assign _theResult___fst_exp__h277757 = - (!_theResult____h269577[56] && !_theResult____h269577[55] && - !_theResult____h269577[54] && - !_theResult____h269577[53] && - !_theResult____h269577[52] && - !_theResult____h269577[51] && - !_theResult____h269577[50] && - !_theResult____h269577[49] && - !_theResult____h269577[48] && - !_theResult____h269577[47] && - !_theResult____h269577[46] && - !_theResult____h269577[45] && - !_theResult____h269577[44] && - !_theResult____h269577[43] && - !_theResult____h269577[42] && - !_theResult____h269577[41] && - !_theResult____h269577[40] && - !_theResult____h269577[39] && - !_theResult____h269577[38] && - !_theResult____h269577[37] && - !_theResult____h269577[36] && - !_theResult____h269577[35] && - !_theResult____h269577[34] && - !_theResult____h269577[33] && - !_theResult____h269577[32] && - !_theResult____h269577[31] && - !_theResult____h269577[30] && - !_theResult____h269577[29] && - !_theResult____h269577[28] && - !_theResult____h269577[27] && - !_theResult____h269577[26] && - !_theResult____h269577[25] && - !_theResult____h269577[24] && - !_theResult____h269577[23] && - !_theResult____h269577[22] && - !_theResult____h269577[21] && - !_theResult____h269577[20] && - !_theResult____h269577[19] && - !_theResult____h269577[18] && - !_theResult____h269577[17] && - !_theResult____h269577[16] && - !_theResult____h269577[15] && - !_theResult____h269577[14] && - !_theResult____h269577[13] && - !_theResult____h269577[12] && - !_theResult____h269577[11] && - !_theResult____h269577[10] && - !_theResult____h269577[9] && - !_theResult____h269577[8] && - !_theResult____h269577[7] && - !_theResult____h269577[6] && - !_theResult____h269577[5] && - !_theResult____h269577[4] && - !_theResult____h269577[3] && - !_theResult____h269577[2] && - !_theResult____h269577[1] && - !_theResult____h269577[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769) ? - 8'd0 : - _theResult___fst_exp__h277751 ; - assign _theResult___fst_exp__h277760 = - (!_theResult____h269577[56] && _theResult____h269577[55]) ? - 8'd1 : - _theResult___fst_exp__h277757 ; - assign _theResult___fst_exp__h278283 = - (_theResult___fst_exp__h277686 == 8'd255) ? - _theResult___fst_exp__h277686 : - _theResult___fst_exp__h278280 ; - assign _theResult___fst_exp__h286333 = - 8'd129 - - { 2'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ; - assign _theResult___fst_exp__h286339 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 || - !_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984) ? - 8'd0 : - _theResult___fst_exp__h286333 ; - assign _theResult___fst_exp__h286342 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___fst_exp__h286339 : - 8'd129 ; - assign _theResult___fst_exp__h286865 = - (_theResult___fst_exp__h286342 == 8'd255) ? - _theResult___fst_exp__h286342 : - _theResult___fst_exp__h286862 ; - assign _theResult___fst_exp__h295452 = - _theResult____h287214[56] ? - 8'd2 : - _theResult___fst_exp__h295526 ; - assign _theResult___fst_exp__h295517 = - 8'd0 - - { 2'd0, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ; - assign _theResult___fst_exp__h295523 = - (!_theResult____h287214[56] && !_theResult____h287214[55] && - !_theResult____h287214[54] && - !_theResult____h287214[53] && - !_theResult____h287214[52] && - !_theResult____h287214[51] && - !_theResult____h287214[50] && - !_theResult____h287214[49] && - !_theResult____h287214[48] && - !_theResult____h287214[47] && - !_theResult____h287214[46] && - !_theResult____h287214[45] && - !_theResult____h287214[44] && - !_theResult____h287214[43] && - !_theResult____h287214[42] && - !_theResult____h287214[41] && - !_theResult____h287214[40] && - !_theResult____h287214[39] && - !_theResult____h287214[38] && - !_theResult____h287214[37] && - !_theResult____h287214[36] && - !_theResult____h287214[35] && - !_theResult____h287214[34] && - !_theResult____h287214[33] && - !_theResult____h287214[32] && - !_theResult____h287214[31] && - !_theResult____h287214[30] && - !_theResult____h287214[29] && - !_theResult____h287214[28] && - !_theResult____h287214[27] && - !_theResult____h287214[26] && - !_theResult____h287214[25] && - !_theResult____h287214[24] && - !_theResult____h287214[23] && - !_theResult____h287214[22] && - !_theResult____h287214[21] && - !_theResult____h287214[20] && - !_theResult____h287214[19] && - !_theResult____h287214[18] && - !_theResult____h287214[17] && - !_theResult____h287214[16] && - !_theResult____h287214[15] && - !_theResult____h287214[14] && - !_theResult____h287214[13] && - !_theResult____h287214[12] && - !_theResult____h287214[11] && - !_theResult____h287214[10] && - !_theResult____h287214[9] && - !_theResult____h287214[8] && - !_theResult____h287214[7] && - !_theResult____h287214[6] && - !_theResult____h287214[5] && - !_theResult____h287214[4] && - !_theResult____h287214[3] && - !_theResult____h287214[2] && - !_theResult____h287214[1] && - !_theResult____h287214[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280) ? - 8'd0 : - _theResult___fst_exp__h295517 ; - assign _theResult___fst_exp__h295526 = - (!_theResult____h287214[56] && _theResult____h287214[55]) ? - 8'd1 : - _theResult___fst_exp__h295523 ; - assign _theResult___fst_exp__h296049 = - (_theResult___fst_exp__h295452 == 8'd255) ? - _theResult___fst_exp__h295452 : - _theResult___fst_exp__h296046 ; - assign _theResult___fst_exp__h304089 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] == - 8'd0) ? - 8'd1 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] ; - assign _theResult___fst_exp__h304128 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] - - { 2'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ; - assign _theResult___fst_exp__h304134 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 || - !_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333) ? - 8'd0 : - _theResult___fst_exp__h304128 ; - assign _theResult___fst_exp__h304137 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___fst_exp__h304134 : - _theResult___fst_exp__h304089 ; - assign _theResult___fst_exp__h304685 = - (_theResult___fst_exp__h304137 == 8'd255) ? - _theResult___fst_exp__h304137 : - _theResult___fst_exp__h304682 ; - assign _theResult___fst_exp__h304694 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - _theResult___snd_fst_exp__h286868 : - _theResult___fst_exp__h269559) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - _theResult___snd_fst_exp__h304688 : - _theResult___fst_exp__h269559) ; - assign _theResult___fst_exp__h304697 = - (resWire$wget[67:57] == 11'd0 && resWire$wget[56:5] == 52'd0) ? - 8'd0 : - _theResult___fst_exp__h304694 ; - assign _theResult___fst_exp__h42284 = - fpu_div64_fState_S3$D_OUT[120:110] - 11'd1 ; - assign _theResult___fst_exp__h42287 = - (fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___fst_exp__h42284 : - 11'd2046 ; - assign _theResult___fst_exp__h42290 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___fst_exp__h42287 : - fpu_div64_fState_S3$D_OUT[120:110] ; - assign _theResult___fst_exp__h42333 = - sfdin__h34118[57] ? - _theResult___fst_exp__h42356 : - _theResult___fst_exp__h42420 ; - assign _theResult___fst_exp__h42336 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h42333 ; - assign _theResult___fst_exp__h42356 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 11'd2 : - _theResult___fst_exp__h42290 + 11'd1 ; - assign _theResult___fst_exp__h42372 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 11'd1 : - _theResult___fst_exp__h42290 ; - assign _theResult___fst_exp__h42411 = - _theResult___fst_exp__h42290 - - { 5'd0, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 } ; - assign _theResult___fst_exp__h42417 = - (!sfdin__h34118[57] && !sfdin__h34118[56] && - !sfdin__h34118[55] && - !sfdin__h34118[54] && - !sfdin__h34118[53] && - !sfdin__h34118[52] && - !sfdin__h34118[51] && - !sfdin__h34118[50] && - !sfdin__h34118[49] && - !sfdin__h34118[48] && - !sfdin__h34118[47] && - !sfdin__h34118[46] && - !sfdin__h34118[45] && - !sfdin__h34118[44] && - !sfdin__h34118[43] && - !sfdin__h34118[42] && - !sfdin__h34118[41] && - !sfdin__h34118[40] && - !sfdin__h34118[39] && - !sfdin__h34118[38] && - !sfdin__h34118[37] && - !sfdin__h34118[36] && - !sfdin__h34118[35] && - !sfdin__h34118[34] && - !sfdin__h34118[33] && - !sfdin__h34118[32] && - !sfdin__h34118[31] && - !sfdin__h34118[30] && - !sfdin__h34118[29] && - !sfdin__h34118[28] && - !sfdin__h34118[27] && - !sfdin__h34118[26] && - !sfdin__h34118[25] && - !sfdin__h34118[24] && - !sfdin__h34118[23] && - !sfdin__h34118[22] && - !sfdin__h34118[21] && - !sfdin__h34118[20] && - !sfdin__h34118[19] && - !sfdin__h34118[18] && - !sfdin__h34118[17] && - !sfdin__h34118[16] && - !sfdin__h34118[15] && - !sfdin__h34118[14] && - !sfdin__h34118[13] && - !sfdin__h34118[12] && - !sfdin__h34118[11] && - !sfdin__h34118[10] && - !sfdin__h34118[9] && - !sfdin__h34118[8] && - !sfdin__h34118[7] && - !sfdin__h34118[6] && - !sfdin__h34118[5] && - !sfdin__h34118[4] && - !sfdin__h34118[3] && - !sfdin__h34118[2] && - !sfdin__h34118[1] && - !sfdin__h34118[0] || - !_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883) ? - 11'd0 : - _theResult___fst_exp__h42411 ; - assign _theResult___fst_exp__h42420 = - (!sfdin__h34118[57] && sfdin__h34118[56]) ? - _theResult___fst_exp__h42372 : - _theResult___fst_exp__h42417 ; - assign _theResult___fst_exp__h43556 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h43553 ; - assign _theResult___fst_exp__h94750 = - fpu_sqr64_fState_S3$D_OUT[58] ? - _theResult___fst_exp__h94773 : - _theResult___fst_exp__h94837 ; - assign _theResult___fst_exp__h94753 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h94750 ; - assign _theResult___fst_exp__h94773 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd2 : - fpu_sqr64_fState_S3$D_OUT[121:111] + 11'd1 ; - assign _theResult___fst_exp__h94789 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd1 : - fpu_sqr64_fState_S3$D_OUT[121:111] ; - assign _theResult___fst_exp__h94828 = - fpu_sqr64_fState_S3$D_OUT[121:111] - - { 5'd0, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 } ; - assign _theResult___fst_exp__h94834 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - !fpu_sqr64_fState_S3$D_OUT[57] && - !fpu_sqr64_fState_S3$D_OUT[56] && - !fpu_sqr64_fState_S3$D_OUT[55] && - !fpu_sqr64_fState_S3$D_OUT[54] && - !fpu_sqr64_fState_S3$D_OUT[53] && - !fpu_sqr64_fState_S3$D_OUT[52] && - !fpu_sqr64_fState_S3$D_OUT[51] && - !fpu_sqr64_fState_S3$D_OUT[50] && - !fpu_sqr64_fState_S3$D_OUT[49] && - !fpu_sqr64_fState_S3$D_OUT[48] && - !fpu_sqr64_fState_S3$D_OUT[47] && - !fpu_sqr64_fState_S3$D_OUT[46] && - !fpu_sqr64_fState_S3$D_OUT[45] && - !fpu_sqr64_fState_S3$D_OUT[44] && - !fpu_sqr64_fState_S3$D_OUT[43] && - !fpu_sqr64_fState_S3$D_OUT[42] && - !fpu_sqr64_fState_S3$D_OUT[41] && - !fpu_sqr64_fState_S3$D_OUT[40] && - !fpu_sqr64_fState_S3$D_OUT[39] && - !fpu_sqr64_fState_S3$D_OUT[38] && - !fpu_sqr64_fState_S3$D_OUT[37] && - !fpu_sqr64_fState_S3$D_OUT[36] && - !fpu_sqr64_fState_S3$D_OUT[35] && - !fpu_sqr64_fState_S3$D_OUT[34] && - !fpu_sqr64_fState_S3$D_OUT[33] && - !fpu_sqr64_fState_S3$D_OUT[32] && - !fpu_sqr64_fState_S3$D_OUT[31] && - !fpu_sqr64_fState_S3$D_OUT[30] && - !fpu_sqr64_fState_S3$D_OUT[29] && - !fpu_sqr64_fState_S3$D_OUT[28] && - !fpu_sqr64_fState_S3$D_OUT[27] && - !fpu_sqr64_fState_S3$D_OUT[26] && - !fpu_sqr64_fState_S3$D_OUT[25] && - !fpu_sqr64_fState_S3$D_OUT[24] && - !fpu_sqr64_fState_S3$D_OUT[23] && - !fpu_sqr64_fState_S3$D_OUT[22] && - !fpu_sqr64_fState_S3$D_OUT[21] && - !fpu_sqr64_fState_S3$D_OUT[20] && - !fpu_sqr64_fState_S3$D_OUT[19] && - !fpu_sqr64_fState_S3$D_OUT[18] && - !fpu_sqr64_fState_S3$D_OUT[17] && - !fpu_sqr64_fState_S3$D_OUT[16] && - !fpu_sqr64_fState_S3$D_OUT[15] && - !fpu_sqr64_fState_S3$D_OUT[14] && - !fpu_sqr64_fState_S3$D_OUT[13] && - !fpu_sqr64_fState_S3$D_OUT[12] && - !fpu_sqr64_fState_S3$D_OUT[11] && - !fpu_sqr64_fState_S3$D_OUT[10] && - !fpu_sqr64_fState_S3$D_OUT[9] && - !fpu_sqr64_fState_S3$D_OUT[8] && - !fpu_sqr64_fState_S3$D_OUT[7] && - !fpu_sqr64_fState_S3$D_OUT[6] && - !fpu_sqr64_fState_S3$D_OUT[5] && - !fpu_sqr64_fState_S3$D_OUT[4] && - !fpu_sqr64_fState_S3$D_OUT[3] && - !fpu_sqr64_fState_S3$D_OUT[2] && - !fpu_sqr64_fState_S3$D_OUT[1] && - !fpu_sqr64_fState_S3$D_OUT[0] || - !_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633) ? - 11'd0 : - _theResult___fst_exp__h94828 ; - assign _theResult___fst_exp__h94837 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - fpu_sqr64_fState_S3$D_OUT[57]) ? - _theResult___fst_exp__h94789 : - _theResult___fst_exp__h94834 ; - assign _theResult___fst_exp__h95990 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h95987 ; - assign _theResult___fst_sfd__h164063 = - (_theResult___fst_exp__h163336 == 11'd2047) ? - _theResult___snd__h163287[56:5] : - _theResult___fst_sfd__h164060 ; - assign _theResult___fst_sfd__h173653 = - (_theResult___fst_exp__h172852 == 11'd2047) ? - sfdin__h172846[56:5] : - _theResult___fst_sfd__h173650 ; - assign _theResult___fst_sfd__h182405 = - (_theResult___fst_exp__h181653 == 11'd2047) ? - _theResult___snd__h181599[56:5] : - _theResult___fst_sfd__h182402 ; - assign _theResult___fst_sfd__h182414 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - _theResult___snd_fst_sfd__h164066 : - _theResult___fst_sfd__h148292) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - _theResult___snd_fst_sfd__h182408 : - _theResult___fst_sfd__h148292) ; - assign _theResult___fst_sfd__h182420 = - ((iFifo$D_OUT[167:160] == 8'd255 || - iFifo$D_OUT[167:160] == 8'd0) && - iFifo$D_OUT[159:137] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h182414 ; - assign _theResult___fst_sfd__h202701 = - (_theResult___fst_exp__h201974 == 11'd2047) ? - _theResult___snd__h201925[56:5] : - _theResult___fst_sfd__h202698 ; - assign _theResult___fst_sfd__h212291 = - (_theResult___fst_exp__h211490 == 11'd2047) ? - sfdin__h211484[56:5] : - _theResult___fst_sfd__h212288 ; - assign _theResult___fst_sfd__h221043 = - (_theResult___fst_exp__h220291 == 11'd2047) ? - _theResult___snd__h220237[56:5] : - _theResult___fst_sfd__h221040 ; - assign _theResult___fst_sfd__h221052 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - _theResult___snd_fst_sfd__h202704 : - _theResult___fst_sfd__h186932) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - _theResult___snd_fst_sfd__h221046 : - _theResult___fst_sfd__h186932) ; - assign _theResult___fst_sfd__h221058 = - ((iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h221052 ; - assign _theResult___fst_sfd__h241640 = - (_theResult___fst_exp__h240913 == 11'd2047) ? - _theResult___snd__h240864[56:5] : - _theResult___fst_sfd__h241637 ; - assign _theResult___fst_sfd__h251230 = - (_theResult___fst_exp__h250429 == 11'd2047) ? - sfdin__h250423[56:5] : - _theResult___fst_sfd__h251227 ; - assign _theResult___fst_sfd__h259982 = - (_theResult___fst_exp__h259230 == 11'd2047) ? - _theResult___snd__h259176[56:5] : - _theResult___fst_sfd__h259979 ; - assign _theResult___fst_sfd__h259991 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - _theResult___snd_fst_sfd__h241643 : - _theResult___fst_sfd__h225871) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - _theResult___snd_fst_sfd__h259985 : - _theResult___fst_sfd__h225871) ; - assign _theResult___fst_sfd__h259997 = - ((iFifo$D_OUT[37:30] == 8'd255 || iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h259991 ; - assign _theResult___fst_sfd__h278284 = - (_theResult___fst_exp__h277686 == 8'd255) ? - sfdin__h277680[56:34] : - _theResult___fst_sfd__h278281 ; - assign _theResult___fst_sfd__h286866 = - (_theResult___fst_exp__h286342 == 8'd255) ? - _theResult___snd__h286293[56:34] : - _theResult___fst_sfd__h286863 ; - assign _theResult___fst_sfd__h296050 = - (_theResult___fst_exp__h295452 == 8'd255) ? - sfdin__h295446[56:34] : - _theResult___fst_sfd__h296047 ; - assign _theResult___fst_sfd__h304686 = - (_theResult___fst_exp__h304137 == 8'd255) ? - _theResult___snd__h304083[56:34] : - _theResult___fst_sfd__h304683 ; - assign _theResult___fst_sfd__h304695 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - _theResult___snd_fst_sfd__h286869 : - _theResult___fst_sfd__h269560) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - _theResult___snd_fst_sfd__h304689 : - _theResult___fst_sfd__h269560) ; - assign _theResult___fst_sfd__h304701 = - ((resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - 23'd0 : - _theResult___fst_sfd__h304695 ; - assign _theResult___fst_sfd__h43557 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h43554 ; - assign _theResult___fst_sfd__h95991 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h95988 ; - assign _theResult___fst_sfd__h96608 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[182:131] : - 52'd0 ; - assign _theResult___sfd__h142542 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 52'd0 : - sfd__h142040[52:1]) : - sfd__h142040[51:0] ; - assign _theResult___sfd__h163982 = - sfd__h163354[53] ? - ((_theResult___fst_exp__h163336 == 11'd2046) ? - 52'd0 : - sfd__h163354[52:1]) : - sfd__h163354[51:0] ; - assign _theResult___sfd__h173572 = - sfd__h172944[53] ? - ((_theResult___fst_exp__h172852 == 11'd2046) ? - 52'd0 : - sfd__h172944[52:1]) : - sfd__h172944[51:0] ; - assign _theResult___sfd__h182324 = - sfd__h181672[53] ? - ((_theResult___fst_exp__h181653 == 11'd2046) ? - 52'd0 : - sfd__h181672[52:1]) : - sfd__h181672[51:0] ; - assign _theResult___sfd__h202620 = - sfd__h201992[53] ? - ((_theResult___fst_exp__h201974 == 11'd2046) ? - 52'd0 : - sfd__h201992[52:1]) : - sfd__h201992[51:0] ; - assign _theResult___sfd__h212210 = - sfd__h211582[53] ? - ((_theResult___fst_exp__h211490 == 11'd2046) ? - 52'd0 : - sfd__h211582[52:1]) : - sfd__h211582[51:0] ; - assign _theResult___sfd__h220962 = - sfd__h220310[53] ? - ((_theResult___fst_exp__h220291 == 11'd2046) ? - 52'd0 : - sfd__h220310[52:1]) : - sfd__h220310[51:0] ; - assign _theResult___sfd__h241559 = - sfd__h240931[53] ? - ((_theResult___fst_exp__h240913 == 11'd2046) ? - 52'd0 : - sfd__h240931[52:1]) : - sfd__h240931[51:0] ; - assign _theResult___sfd__h251149 = - sfd__h250521[53] ? - ((_theResult___fst_exp__h250429 == 11'd2046) ? - 52'd0 : - sfd__h250521[52:1]) : - sfd__h250521[51:0] ; - assign _theResult___sfd__h259901 = - sfd__h259249[53] ? - ((_theResult___fst_exp__h259230 == 11'd2046) ? - 52'd0 : - sfd__h259249[52:1]) : - sfd__h259249[51:0] ; - assign _theResult___sfd__h278203 = - sfd__h277778[24] ? - ((_theResult___fst_exp__h277686 == 8'd254) ? - 23'd0 : - sfd__h277778[23:1]) : - sfd__h277778[22:0] ; - assign _theResult___sfd__h286785 = - sfd__h286360[24] ? - ((_theResult___fst_exp__h286342 == 8'd254) ? - 23'd0 : - sfd__h286360[23:1]) : - sfd__h286360[22:0] ; - assign _theResult___sfd__h295969 = - sfd__h295544[24] ? - ((_theResult___fst_exp__h295452 == 8'd254) ? - 23'd0 : - sfd__h295544[23:1]) : - sfd__h295544[22:0] ; - assign _theResult___sfd__h304605 = - sfd__h304156[24] ? - ((_theResult___fst_exp__h304137 == 8'd254) ? - 23'd0 : - sfd__h304156[23:1]) : - sfd__h304156[22:0] ; - assign _theResult___sfd__h43476 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h42982[52:1]) : - sfd__h42982[51:0] ; - assign _theResult___sfd__h95910 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h95416[52:1]) : - sfd__h95416[51:0] ; - assign _theResult___snd__h130966 = { sfdBC__h115662[104:0], 1'd0 } ; - assign _theResult___snd__h130980 = - (!sfdBC__h115662[105] && sfdBC__h115662[104]) ? - _theResult___snd__h130982 : - _theResult___snd__h130994 ; - assign _theResult___snd__h130982 = { sfdBC__h115662[103:0], 2'd0 } ; - assign _theResult___snd__h130994 = - (!sfdBC__h115662[105] && !sfdBC__h115662[104] && - !sfdBC__h115662[103] && - !sfdBC__h115662[102] && - !sfdBC__h115662[101] && - !sfdBC__h115662[100] && - !sfdBC__h115662[99] && - !sfdBC__h115662[98] && - !sfdBC__h115662[97] && - !sfdBC__h115662[96] && - !sfdBC__h115662[95] && - !sfdBC__h115662[94] && - !sfdBC__h115662[93] && - !sfdBC__h115662[92] && - !sfdBC__h115662[91] && - !sfdBC__h115662[90] && - !sfdBC__h115662[89] && - !sfdBC__h115662[88] && - !sfdBC__h115662[87] && - !sfdBC__h115662[86] && - !sfdBC__h115662[85] && - !sfdBC__h115662[84] && - !sfdBC__h115662[83] && - !sfdBC__h115662[82] && - !sfdBC__h115662[81] && - !sfdBC__h115662[80] && - !sfdBC__h115662[79] && - !sfdBC__h115662[78] && - !sfdBC__h115662[77] && - !sfdBC__h115662[76] && - !sfdBC__h115662[75] && - !sfdBC__h115662[74] && - !sfdBC__h115662[73] && - !sfdBC__h115662[72] && - !sfdBC__h115662[71] && - !sfdBC__h115662[70] && - !sfdBC__h115662[69] && - !sfdBC__h115662[68] && - !sfdBC__h115662[67] && - !sfdBC__h115662[66] && - !sfdBC__h115662[65] && - !sfdBC__h115662[64] && - !sfdBC__h115662[63] && - !sfdBC__h115662[62] && - !sfdBC__h115662[61] && - !sfdBC__h115662[60] && - !sfdBC__h115662[59] && - !sfdBC__h115662[58] && - !sfdBC__h115662[57] && - !sfdBC__h115662[56] && - !sfdBC__h115662[55] && - !sfdBC__h115662[54] && - !sfdBC__h115662[53] && - !sfdBC__h115662[52] && - !sfdBC__h115662[51] && - !sfdBC__h115662[50] && - !sfdBC__h115662[49] && - !sfdBC__h115662[48] && - !sfdBC__h115662[47] && - !sfdBC__h115662[46] && - !sfdBC__h115662[45] && - !sfdBC__h115662[44] && - !sfdBC__h115662[43] && - !sfdBC__h115662[42] && - !sfdBC__h115662[41] && - !sfdBC__h115662[40] && - !sfdBC__h115662[39] && - !sfdBC__h115662[38] && - !sfdBC__h115662[37] && - !sfdBC__h115662[36] && - !sfdBC__h115662[35] && - !sfdBC__h115662[34] && - !sfdBC__h115662[33] && - !sfdBC__h115662[32] && - !sfdBC__h115662[31] && - !sfdBC__h115662[30] && - !sfdBC__h115662[29] && - !sfdBC__h115662[28] && - !sfdBC__h115662[27] && - !sfdBC__h115662[26] && - !sfdBC__h115662[25] && - !sfdBC__h115662[24] && - !sfdBC__h115662[23] && - !sfdBC__h115662[22] && - !sfdBC__h115662[21] && - !sfdBC__h115662[20] && - !sfdBC__h115662[19] && - !sfdBC__h115662[18] && - !sfdBC__h115662[17] && - !sfdBC__h115662[16] && - !sfdBC__h115662[15] && - !sfdBC__h115662[14] && - !sfdBC__h115662[13] && - !sfdBC__h115662[12] && - !sfdBC__h115662[11] && - !sfdBC__h115662[10] && - !sfdBC__h115662[9] && - !sfdBC__h115662[8] && - !sfdBC__h115662[7] && - !sfdBC__h115662[6] && - !sfdBC__h115662[5] && - !sfdBC__h115662[4] && - !sfdBC__h115662[3] && - !sfdBC__h115662[2] && - !sfdBC__h115662[1] && - !sfdBC__h115662[0]) ? - sfdBC__h115662 : - _theResult___snd__h131000 ; - assign _theResult___snd__h131000 = - { IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24[103:0], - 2'd0 } ; - assign _theResult___snd__h131018 = - sfdBC__h115662 << - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ; - assign _theResult___snd__h131023 = - sfdBC__h115662 << - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 ; - assign _theResult___snd__h141392 = { sfd__h133119[55:0], 1'd0 } ; - assign _theResult___snd__h141406 = - (!sfd__h133119[56] && sfd__h133119[55]) ? - _theResult___snd__h141408 : - _theResult___snd__h141420 ; - assign _theResult___snd__h141408 = { sfd__h133119[54:0], 2'd0 } ; - assign _theResult___snd__h141420 = - (!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] && - !sfd__h133119[53] && - !sfd__h133119[52] && - !sfd__h133119[51] && - !sfd__h133119[50] && - !sfd__h133119[49] && - !sfd__h133119[48] && - !sfd__h133119[47] && - !sfd__h133119[46] && - !sfd__h133119[45] && - !sfd__h133119[44] && - !sfd__h133119[43] && - !sfd__h133119[42] && - !sfd__h133119[41] && - !sfd__h133119[40] && - !sfd__h133119[39] && - !sfd__h133119[38] && - !sfd__h133119[37] && - !sfd__h133119[36] && - !sfd__h133119[35] && - !sfd__h133119[34] && - !sfd__h133119[33] && - !sfd__h133119[32] && - !sfd__h133119[31] && - !sfd__h133119[30] && - !sfd__h133119[29] && - !sfd__h133119[28] && - !sfd__h133119[27] && - !sfd__h133119[26] && - !sfd__h133119[25] && - !sfd__h133119[24] && - !sfd__h133119[23] && - !sfd__h133119[22] && - !sfd__h133119[21] && - !sfd__h133119[20] && - !sfd__h133119[19] && - !sfd__h133119[18] && - !sfd__h133119[17] && - !sfd__h133119[16] && - !sfd__h133119[15] && - !sfd__h133119[14] && - !sfd__h133119[13] && - !sfd__h133119[12] && - !sfd__h133119[11] && - !sfd__h133119[10] && - !sfd__h133119[9] && - !sfd__h133119[8] && - !sfd__h133119[7] && - !sfd__h133119[6] && - !sfd__h133119[5] && - !sfd__h133119[4] && - !sfd__h133119[3] && - !sfd__h133119[2] && - !sfd__h133119[1] && - !sfd__h133119[0]) ? - sfd__h133119 : - _theResult___snd__h141426 ; - assign _theResult___snd__h141426 = - { IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29[54:0], - 2'd0 } ; - assign _theResult___snd__h141444 = - sfd__h133119 << - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ; - assign _theResult___snd__h141449 = - sfd__h133119 << - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 ; - assign _theResult___snd__h163287 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___snd__h163296 : - _theResult___snd__h163289 ; - assign _theResult___snd__h163289 = { iFifo$D_OUT[159:137], 34'd0 } ; - assign _theResult___snd__h163296 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ? - sfd__h144536 : - _theResult___snd__h163302 ; - assign _theResult___snd__h163302 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33[54:0], - 2'd0 } ; - assign _theResult___snd__h163325 = - sfd__h144536 << - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 ; - assign _theResult___snd__h172863 = { _theResult____h164614[55:0], 1'd0 } ; - assign _theResult___snd__h172874 = - (!_theResult____h164614[56] && _theResult____h164614[55]) ? - _theResult___snd__h172876 : - _theResult___snd__h172886 ; - assign _theResult___snd__h172876 = { _theResult____h164614[54:0], 2'd0 } ; - assign _theResult___snd__h172886 = - (!_theResult____h164614[56] && !_theResult____h164614[55] && - !_theResult____h164614[54] && - !_theResult____h164614[53] && - !_theResult____h164614[52] && - !_theResult____h164614[51] && - !_theResult____h164614[50] && - !_theResult____h164614[49] && - !_theResult____h164614[48] && - !_theResult____h164614[47] && - !_theResult____h164614[46] && - !_theResult____h164614[45] && - !_theResult____h164614[44] && - !_theResult____h164614[43] && - !_theResult____h164614[42] && - !_theResult____h164614[41] && - !_theResult____h164614[40] && - !_theResult____h164614[39] && - !_theResult____h164614[38] && - !_theResult____h164614[37] && - !_theResult____h164614[36] && - !_theResult____h164614[35] && - !_theResult____h164614[34] && - !_theResult____h164614[33] && - !_theResult____h164614[32] && - !_theResult____h164614[31] && - !_theResult____h164614[30] && - !_theResult____h164614[29] && - !_theResult____h164614[28] && - !_theResult____h164614[27] && - !_theResult____h164614[26] && - !_theResult____h164614[25] && - !_theResult____h164614[24] && - !_theResult____h164614[23] && - !_theResult____h164614[22] && - !_theResult____h164614[21] && - !_theResult____h164614[20] && - !_theResult____h164614[19] && - !_theResult____h164614[18] && - !_theResult____h164614[17] && - !_theResult____h164614[16] && - !_theResult____h164614[15] && - !_theResult____h164614[14] && - !_theResult____h164614[13] && - !_theResult____h164614[12] && - !_theResult____h164614[11] && - !_theResult____h164614[10] && - !_theResult____h164614[9] && - !_theResult____h164614[8] && - !_theResult____h164614[7] && - !_theResult____h164614[6] && - !_theResult____h164614[5] && - !_theResult____h164614[4] && - !_theResult____h164614[3] && - !_theResult____h164614[2] && - !_theResult____h164614[1] && - !_theResult____h164614[0]) ? - _theResult____h164614 : - _theResult___snd__h172892 ; - assign _theResult___snd__h172892 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37[54:0], - 2'd0 } ; - assign _theResult___snd__h172915 = - _theResult____h164614 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 ; - assign _theResult___snd__h181599 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___snd__h181613 : - _theResult___snd__h163289 ; - assign _theResult___snd__h181613 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ? - sfd__h144536 : - _theResult___snd__h181619 ; - assign _theResult___snd__h181619 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40[54:0], - 2'd0 } ; - assign _theResult___snd__h181637 = - sfd__h144536 << - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ; - assign _theResult___snd__h201925 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___snd__h201934 : - _theResult___snd__h201927 ; - assign _theResult___snd__h201927 = { iFifo$D_OUT[94:72], 34'd0 } ; - assign _theResult___snd__h201934 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ? - sfd__h183176 : - _theResult___snd__h201940 ; - assign _theResult___snd__h201940 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93[54:0], - 2'd0 } ; - assign _theResult___snd__h201963 = - sfd__h183176 << - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 ; - assign _theResult___snd__h211501 = { _theResult____h203252[55:0], 1'd0 } ; - assign _theResult___snd__h211512 = - (!_theResult____h203252[56] && _theResult____h203252[55]) ? - _theResult___snd__h211514 : - _theResult___snd__h211524 ; - assign _theResult___snd__h211514 = { _theResult____h203252[54:0], 2'd0 } ; - assign _theResult___snd__h211524 = - (!_theResult____h203252[56] && !_theResult____h203252[55] && - !_theResult____h203252[54] && - !_theResult____h203252[53] && - !_theResult____h203252[52] && - !_theResult____h203252[51] && - !_theResult____h203252[50] && - !_theResult____h203252[49] && - !_theResult____h203252[48] && - !_theResult____h203252[47] && - !_theResult____h203252[46] && - !_theResult____h203252[45] && - !_theResult____h203252[44] && - !_theResult____h203252[43] && - !_theResult____h203252[42] && - !_theResult____h203252[41] && - !_theResult____h203252[40] && - !_theResult____h203252[39] && - !_theResult____h203252[38] && - !_theResult____h203252[37] && - !_theResult____h203252[36] && - !_theResult____h203252[35] && - !_theResult____h203252[34] && - !_theResult____h203252[33] && - !_theResult____h203252[32] && - !_theResult____h203252[31] && - !_theResult____h203252[30] && - !_theResult____h203252[29] && - !_theResult____h203252[28] && - !_theResult____h203252[27] && - !_theResult____h203252[26] && - !_theResult____h203252[25] && - !_theResult____h203252[24] && - !_theResult____h203252[23] && - !_theResult____h203252[22] && - !_theResult____h203252[21] && - !_theResult____h203252[20] && - !_theResult____h203252[19] && - !_theResult____h203252[18] && - !_theResult____h203252[17] && - !_theResult____h203252[16] && - !_theResult____h203252[15] && - !_theResult____h203252[14] && - !_theResult____h203252[13] && - !_theResult____h203252[12] && - !_theResult____h203252[11] && - !_theResult____h203252[10] && - !_theResult____h203252[9] && - !_theResult____h203252[8] && - !_theResult____h203252[7] && - !_theResult____h203252[6] && - !_theResult____h203252[5] && - !_theResult____h203252[4] && - !_theResult____h203252[3] && - !_theResult____h203252[2] && - !_theResult____h203252[1] && - !_theResult____h203252[0]) ? - _theResult____h203252 : - _theResult___snd__h211530 ; - assign _theResult___snd__h211530 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97[54:0], - 2'd0 } ; - assign _theResult___snd__h211553 = - _theResult____h203252 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 ; - assign _theResult___snd__h220237 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___snd__h220251 : - _theResult___snd__h201927 ; - assign _theResult___snd__h220251 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ? - sfd__h183176 : - _theResult___snd__h220257 ; - assign _theResult___snd__h220257 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100[54:0], - 2'd0 } ; - assign _theResult___snd__h220275 = - sfd__h183176 << - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ; - assign _theResult___snd__h240864 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___snd__h240873 : - _theResult___snd__h240866 ; - assign _theResult___snd__h240866 = { iFifo$D_OUT[29:7], 34'd0 } ; - assign _theResult___snd__h240873 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ? - sfd__h222115 : - _theResult___snd__h240879 ; - assign _theResult___snd__h240879 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60[54:0], - 2'd0 } ; - assign _theResult___snd__h240902 = - sfd__h222115 << - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 ; - assign _theResult___snd__h250440 = { _theResult____h242191[55:0], 1'd0 } ; - assign _theResult___snd__h250451 = - (!_theResult____h242191[56] && _theResult____h242191[55]) ? - _theResult___snd__h250453 : - _theResult___snd__h250463 ; - assign _theResult___snd__h250453 = { _theResult____h242191[54:0], 2'd0 } ; - assign _theResult___snd__h250463 = - (!_theResult____h242191[56] && !_theResult____h242191[55] && - !_theResult____h242191[54] && - !_theResult____h242191[53] && - !_theResult____h242191[52] && - !_theResult____h242191[51] && - !_theResult____h242191[50] && - !_theResult____h242191[49] && - !_theResult____h242191[48] && - !_theResult____h242191[47] && - !_theResult____h242191[46] && - !_theResult____h242191[45] && - !_theResult____h242191[44] && - !_theResult____h242191[43] && - !_theResult____h242191[42] && - !_theResult____h242191[41] && - !_theResult____h242191[40] && - !_theResult____h242191[39] && - !_theResult____h242191[38] && - !_theResult____h242191[37] && - !_theResult____h242191[36] && - !_theResult____h242191[35] && - !_theResult____h242191[34] && - !_theResult____h242191[33] && - !_theResult____h242191[32] && - !_theResult____h242191[31] && - !_theResult____h242191[30] && - !_theResult____h242191[29] && - !_theResult____h242191[28] && - !_theResult____h242191[27] && - !_theResult____h242191[26] && - !_theResult____h242191[25] && - !_theResult____h242191[24] && - !_theResult____h242191[23] && - !_theResult____h242191[22] && - !_theResult____h242191[21] && - !_theResult____h242191[20] && - !_theResult____h242191[19] && - !_theResult____h242191[18] && - !_theResult____h242191[17] && - !_theResult____h242191[16] && - !_theResult____h242191[15] && - !_theResult____h242191[14] && - !_theResult____h242191[13] && - !_theResult____h242191[12] && - !_theResult____h242191[11] && - !_theResult____h242191[10] && - !_theResult____h242191[9] && - !_theResult____h242191[8] && - !_theResult____h242191[7] && - !_theResult____h242191[6] && - !_theResult____h242191[5] && - !_theResult____h242191[4] && - !_theResult____h242191[3] && - !_theResult____h242191[2] && - !_theResult____h242191[1] && - !_theResult____h242191[0]) ? - _theResult____h242191 : - _theResult___snd__h250469 ; - assign _theResult___snd__h250469 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64[54:0], - 2'd0 } ; - assign _theResult___snd__h250492 = - _theResult____h242191 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 ; - assign _theResult___snd__h259176 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___snd__h259190 : - _theResult___snd__h240866 ; - assign _theResult___snd__h259190 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ? - sfd__h222115 : - _theResult___snd__h259196 ; - assign _theResult___snd__h259196 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67[54:0], - 2'd0 } ; - assign _theResult___snd__h259214 = - sfd__h222115 << - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ; - assign _theResult___snd__h277697 = { _theResult____h269577[55:0], 1'd0 } ; - assign _theResult___snd__h277708 = - (!_theResult____h269577[56] && _theResult____h269577[55]) ? - _theResult___snd__h277710 : - _theResult___snd__h277720 ; - assign _theResult___snd__h277710 = { _theResult____h269577[54:0], 2'd0 } ; - assign _theResult___snd__h277720 = - (!_theResult____h269577[56] && !_theResult____h269577[55] && - !_theResult____h269577[54] && - !_theResult____h269577[53] && - !_theResult____h269577[52] && - !_theResult____h269577[51] && - !_theResult____h269577[50] && - !_theResult____h269577[49] && - !_theResult____h269577[48] && - !_theResult____h269577[47] && - !_theResult____h269577[46] && - !_theResult____h269577[45] && - !_theResult____h269577[44] && - !_theResult____h269577[43] && - !_theResult____h269577[42] && - !_theResult____h269577[41] && - !_theResult____h269577[40] && - !_theResult____h269577[39] && - !_theResult____h269577[38] && - !_theResult____h269577[37] && - !_theResult____h269577[36] && - !_theResult____h269577[35] && - !_theResult____h269577[34] && - !_theResult____h269577[33] && - !_theResult____h269577[32] && - !_theResult____h269577[31] && - !_theResult____h269577[30] && - !_theResult____h269577[29] && - !_theResult____h269577[28] && - !_theResult____h269577[27] && - !_theResult____h269577[26] && - !_theResult____h269577[25] && - !_theResult____h269577[24] && - !_theResult____h269577[23] && - !_theResult____h269577[22] && - !_theResult____h269577[21] && - !_theResult____h269577[20] && - !_theResult____h269577[19] && - !_theResult____h269577[18] && - !_theResult____h269577[17] && - !_theResult____h269577[16] && - !_theResult____h269577[15] && - !_theResult____h269577[14] && - !_theResult____h269577[13] && - !_theResult____h269577[12] && - !_theResult____h269577[11] && - !_theResult____h269577[10] && - !_theResult____h269577[9] && - !_theResult____h269577[8] && - !_theResult____h269577[7] && - !_theResult____h269577[6] && - !_theResult____h269577[5] && - !_theResult____h269577[4] && - !_theResult____h269577[3] && - !_theResult____h269577[2] && - !_theResult____h269577[1] && - !_theResult____h269577[0]) ? - _theResult____h269577 : - _theResult___snd__h277726 ; - assign _theResult___snd__h277726 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133[54:0], - 2'd0 } ; - assign _theResult___snd__h277749 = - _theResult____h269577 << - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 ; - assign _theResult___snd__h286293 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___snd__h286302 : - _theResult___snd__h286295 ; - assign _theResult___snd__h286295 = { resWire$wget[56:5], 5'd0 } ; - assign _theResult___snd__h286302 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ? - sfd__h261975 : - _theResult___snd__h286308 ; - assign _theResult___snd__h286308 = - { IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135[54:0], - 2'd0 } ; - assign _theResult___snd__h286331 = - sfd__h261975 << - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 ; - assign _theResult___snd__h295463 = { _theResult____h287214[55:0], 1'd0 } ; - assign _theResult___snd__h295474 = - (!_theResult____h287214[56] && _theResult____h287214[55]) ? - _theResult___snd__h295476 : - _theResult___snd__h295486 ; - assign _theResult___snd__h295476 = { _theResult____h287214[54:0], 2'd0 } ; - assign _theResult___snd__h295486 = - (!_theResult____h287214[56] && !_theResult____h287214[55] && - !_theResult____h287214[54] && - !_theResult____h287214[53] && - !_theResult____h287214[52] && - !_theResult____h287214[51] && - !_theResult____h287214[50] && - !_theResult____h287214[49] && - !_theResult____h287214[48] && - !_theResult____h287214[47] && - !_theResult____h287214[46] && - !_theResult____h287214[45] && - !_theResult____h287214[44] && - !_theResult____h287214[43] && - !_theResult____h287214[42] && - !_theResult____h287214[41] && - !_theResult____h287214[40] && - !_theResult____h287214[39] && - !_theResult____h287214[38] && - !_theResult____h287214[37] && - !_theResult____h287214[36] && - !_theResult____h287214[35] && - !_theResult____h287214[34] && - !_theResult____h287214[33] && - !_theResult____h287214[32] && - !_theResult____h287214[31] && - !_theResult____h287214[30] && - !_theResult____h287214[29] && - !_theResult____h287214[28] && - !_theResult____h287214[27] && - !_theResult____h287214[26] && - !_theResult____h287214[25] && - !_theResult____h287214[24] && - !_theResult____h287214[23] && - !_theResult____h287214[22] && - !_theResult____h287214[21] && - !_theResult____h287214[20] && - !_theResult____h287214[19] && - !_theResult____h287214[18] && - !_theResult____h287214[17] && - !_theResult____h287214[16] && - !_theResult____h287214[15] && - !_theResult____h287214[14] && - !_theResult____h287214[13] && - !_theResult____h287214[12] && - !_theResult____h287214[11] && - !_theResult____h287214[10] && - !_theResult____h287214[9] && - !_theResult____h287214[8] && - !_theResult____h287214[7] && - !_theResult____h287214[6] && - !_theResult____h287214[5] && - !_theResult____h287214[4] && - !_theResult____h287214[3] && - !_theResult____h287214[2] && - !_theResult____h287214[1] && - !_theResult____h287214[0]) ? - _theResult____h287214 : - _theResult___snd__h295492 ; - assign _theResult___snd__h295492 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139[54:0], - 2'd0 } ; - assign _theResult___snd__h295515 = - _theResult____h287214 << - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 ; - assign _theResult___snd__h304083 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___snd__h304097 : - _theResult___snd__h286295 ; - assign _theResult___snd__h304097 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ? - sfd__h261975 : - _theResult___snd__h304103 ; - assign _theResult___snd__h304103 = - { IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142[54:0], - 2'd0 } ; - assign _theResult___snd__h304121 = - sfd__h261975 << - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ; - assign _theResult___snd__h34715 = - { fpu_div64_fState_S3$D_OUT[56:0], 1'd0 } ; - assign _theResult___snd__h42350 = { sfdin__h34118[56:0], 1'd0 } ; - assign _theResult___snd__h42365 = - (!sfdin__h34118[57] && sfdin__h34118[56]) ? - _theResult___snd__h42367 : - _theResult___snd__h42380 ; - assign _theResult___snd__h42367 = { sfdin__h34118[55:0], 2'd0 } ; - assign _theResult___snd__h42380 = - (!sfdin__h34118[57] && !sfdin__h34118[56] && - !sfdin__h34118[55] && - !sfdin__h34118[54] && - !sfdin__h34118[53] && - !sfdin__h34118[52] && - !sfdin__h34118[51] && - !sfdin__h34118[50] && - !sfdin__h34118[49] && - !sfdin__h34118[48] && - !sfdin__h34118[47] && - !sfdin__h34118[46] && - !sfdin__h34118[45] && - !sfdin__h34118[44] && - !sfdin__h34118[43] && - !sfdin__h34118[42] && - !sfdin__h34118[41] && - !sfdin__h34118[40] && - !sfdin__h34118[39] && - !sfdin__h34118[38] && - !sfdin__h34118[37] && - !sfdin__h34118[36] && - !sfdin__h34118[35] && - !sfdin__h34118[34] && - !sfdin__h34118[33] && - !sfdin__h34118[32] && - !sfdin__h34118[31] && - !sfdin__h34118[30] && - !sfdin__h34118[29] && - !sfdin__h34118[28] && - !sfdin__h34118[27] && - !sfdin__h34118[26] && - !sfdin__h34118[25] && - !sfdin__h34118[24] && - !sfdin__h34118[23] && - !sfdin__h34118[22] && - !sfdin__h34118[21] && - !sfdin__h34118[20] && - !sfdin__h34118[19] && - !sfdin__h34118[18] && - !sfdin__h34118[17] && - !sfdin__h34118[16] && - !sfdin__h34118[15] && - !sfdin__h34118[14] && - !sfdin__h34118[13] && - !sfdin__h34118[12] && - !sfdin__h34118[11] && - !sfdin__h34118[10] && - !sfdin__h34118[9] && - !sfdin__h34118[8] && - !sfdin__h34118[7] && - !sfdin__h34118[6] && - !sfdin__h34118[5] && - !sfdin__h34118[4] && - !sfdin__h34118[3] && - !sfdin__h34118[2] && - !sfdin__h34118[1] && - !sfdin__h34118[0]) ? - sfdin__h34118 : - _theResult___snd__h42386 ; - assign _theResult___snd__h42386 = - { IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12[55:0], - 2'd0 } ; - assign _theResult___snd__h42404 = - sfdin__h34118 << - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 ; - assign _theResult___snd__h42409 = - sfdin__h34118 << - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 ; - assign _theResult___snd__h94767 = - { fpu_sqr64_fState_S3$D_OUT[57:0], 1'd0 } ; - assign _theResult___snd__h94782 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - fpu_sqr64_fState_S3$D_OUT[57]) ? - _theResult___snd__h94784 : - _theResult___snd__h94797 ; - assign _theResult___snd__h94784 = - { fpu_sqr64_fState_S3$D_OUT[56:0], 2'd0 } ; - assign _theResult___snd__h94797 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - !fpu_sqr64_fState_S3$D_OUT[57] && - !fpu_sqr64_fState_S3$D_OUT[56] && - !fpu_sqr64_fState_S3$D_OUT[55] && - !fpu_sqr64_fState_S3$D_OUT[54] && - !fpu_sqr64_fState_S3$D_OUT[53] && - !fpu_sqr64_fState_S3$D_OUT[52] && - !fpu_sqr64_fState_S3$D_OUT[51] && - !fpu_sqr64_fState_S3$D_OUT[50] && - !fpu_sqr64_fState_S3$D_OUT[49] && - !fpu_sqr64_fState_S3$D_OUT[48] && - !fpu_sqr64_fState_S3$D_OUT[47] && - !fpu_sqr64_fState_S3$D_OUT[46] && - !fpu_sqr64_fState_S3$D_OUT[45] && - !fpu_sqr64_fState_S3$D_OUT[44] && - !fpu_sqr64_fState_S3$D_OUT[43] && - !fpu_sqr64_fState_S3$D_OUT[42] && - !fpu_sqr64_fState_S3$D_OUT[41] && - !fpu_sqr64_fState_S3$D_OUT[40] && - !fpu_sqr64_fState_S3$D_OUT[39] && - !fpu_sqr64_fState_S3$D_OUT[38] && - !fpu_sqr64_fState_S3$D_OUT[37] && - !fpu_sqr64_fState_S3$D_OUT[36] && - !fpu_sqr64_fState_S3$D_OUT[35] && - !fpu_sqr64_fState_S3$D_OUT[34] && - !fpu_sqr64_fState_S3$D_OUT[33] && - !fpu_sqr64_fState_S3$D_OUT[32] && - !fpu_sqr64_fState_S3$D_OUT[31] && - !fpu_sqr64_fState_S3$D_OUT[30] && - !fpu_sqr64_fState_S3$D_OUT[29] && - !fpu_sqr64_fState_S3$D_OUT[28] && - !fpu_sqr64_fState_S3$D_OUT[27] && - !fpu_sqr64_fState_S3$D_OUT[26] && - !fpu_sqr64_fState_S3$D_OUT[25] && - !fpu_sqr64_fState_S3$D_OUT[24] && - !fpu_sqr64_fState_S3$D_OUT[23] && - !fpu_sqr64_fState_S3$D_OUT[22] && - !fpu_sqr64_fState_S3$D_OUT[21] && - !fpu_sqr64_fState_S3$D_OUT[20] && - !fpu_sqr64_fState_S3$D_OUT[19] && - !fpu_sqr64_fState_S3$D_OUT[18] && - !fpu_sqr64_fState_S3$D_OUT[17] && - !fpu_sqr64_fState_S3$D_OUT[16] && - !fpu_sqr64_fState_S3$D_OUT[15] && - !fpu_sqr64_fState_S3$D_OUT[14] && - !fpu_sqr64_fState_S3$D_OUT[13] && - !fpu_sqr64_fState_S3$D_OUT[12] && - !fpu_sqr64_fState_S3$D_OUT[11] && - !fpu_sqr64_fState_S3$D_OUT[10] && - !fpu_sqr64_fState_S3$D_OUT[9] && - !fpu_sqr64_fState_S3$D_OUT[8] && - !fpu_sqr64_fState_S3$D_OUT[7] && - !fpu_sqr64_fState_S3$D_OUT[6] && - !fpu_sqr64_fState_S3$D_OUT[5] && - !fpu_sqr64_fState_S3$D_OUT[4] && - !fpu_sqr64_fState_S3$D_OUT[3] && - !fpu_sqr64_fState_S3$D_OUT[2] && - !fpu_sqr64_fState_S3$D_OUT[1] && - !fpu_sqr64_fState_S3$D_OUT[0]) ? - fpu_sqr64_fState_S3$D_OUT[58:0] : - _theResult___snd__h94803 ; - assign _theResult___snd__h94803 = - { IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19[56:0], - 2'd0 } ; - assign _theResult___snd__h94821 = - fpu_sqr64_fState_S3$D_OUT[58:0] << - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 ; - assign _theResult___snd__h94826 = - fpu_sqr64_fState_S3$D_OUT[58:0] << - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 ; - assign _theResult___snd_fst__h131051 = - { IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25[1], - { sfdin__h130943[52:0], 52'd0 } != 105'd0 } ; - assign _theResult___snd_fst__h141477 = - { IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30[1], - { sfdin__h141369[3:0], 52'd0 } != 56'd0 } ; - assign _theResult___snd_fst__h1478 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___snd_fst__h1602 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 ; - assign _theResult___snd_fst__h1517 = - (rg_res[116] || rg_b == 116'd0 || - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63) ? - rg_s : - s__h1658 ; - assign _theResult___snd_fst__h1602 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0 || - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 : - s__h1723 ; - assign _theResult___snd_fst__h42439 = - { IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13[1], - { sfdin__h42327[4:0], 52'd0 } != 57'd0 } ; - assign _theResult___snd_fst__h94856 = - { IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20[1], - { sfdin__h94744[5:0], 52'd0 } != 58'd0 } ; - assign _theResult___snd_fst_exp__h164065 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - 11'd0 : - _theResult___fst_exp__h164062 ; - assign _theResult___snd_fst_exp__h182407 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - _theResult___fst_exp__h173652 : - _theResult___fst_exp__h182404 ; - assign _theResult___snd_fst_exp__h202703 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - 11'd0 : - _theResult___fst_exp__h202700 ; - assign _theResult___snd_fst_exp__h221045 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - _theResult___fst_exp__h212290 : - _theResult___fst_exp__h221042 ; - assign _theResult___snd_fst_exp__h241642 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - 11'd0 : - _theResult___fst_exp__h241639 ; - assign _theResult___snd_fst_exp__h259984 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - _theResult___fst_exp__h251229 : - _theResult___fst_exp__h259981 ; - assign _theResult___snd_fst_exp__h286868 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _theResult___fst_exp__h278283 : - _theResult___fst_exp__h286865 ; - assign _theResult___snd_fst_exp__h304688 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _theResult___fst_exp__h296049 : - _theResult___fst_exp__h304685 ; - assign _theResult___snd_fst_exp__h31334 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499) ? - 11'd0 : - value__h31374[10:0] ; - assign _theResult___snd_fst_exp__h31337 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ? - _theResult___snd_fst_exp__h31334 : - 11'd2046 ; - assign _theResult___snd_fst_exp__h31361 = - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 ? - 11'd0 : - _theResult___snd_fst_exp__h31337 ; - assign _theResult___snd_fst_sfd__h144486 = - (iFifo$D_OUT[159:137] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h144235 ; - assign _theResult___snd_fst_sfd__h164066 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - 52'd0 : - _theResult___fst_sfd__h164063 ; - assign _theResult___snd_fst_sfd__h182408 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - _theResult___fst_sfd__h173653 : - _theResult___fst_sfd__h182405 ; - assign _theResult___snd_fst_sfd__h183126 = - (iFifo$D_OUT[94:72] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h182875 ; - assign _theResult___snd_fst_sfd__h202704 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - 52'd0 : - _theResult___fst_sfd__h202701 ; - assign _theResult___snd_fst_sfd__h221046 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - _theResult___fst_sfd__h212291 : - _theResult___fst_sfd__h221043 ; - assign _theResult___snd_fst_sfd__h222065 = - (iFifo$D_OUT[29:7] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h221814 ; - assign _theResult___snd_fst_sfd__h241643 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - 52'd0 : - _theResult___fst_sfd__h241640 ; - assign _theResult___snd_fst_sfd__h259985 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - _theResult___fst_sfd__h251230 : - _theResult___fst_sfd__h259982 ; - assign _theResult___snd_fst_sfd__h261925 = - (resWire$wget[56:34] == 23'd0) ? - 23'd2097152 : - resWire$wget[56:34] ; - assign _theResult___snd_fst_sfd__h286869 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _theResult___fst_sfd__h278284 : - _theResult___fst_sfd__h286866 ; - assign _theResult___snd_fst_sfd__h304689 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _theResult___fst_sfd__h296050 : - _theResult___fst_sfd__h304686 ; - assign _theResult___snd_fst_sfd__h31362 = - (fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353) ? - 52'd0 : - 52'hFFFFFFFFFFFFF ; - assign _theResult___snd_snd__h131371 = - (fpu_madd_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ; - assign _theResult___snd_snd__h1649 = - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63 ? r__h1663 : r__h1659 ; - assign _theResult___snd_snd__h1715 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85 ? - r__h1753 : - r__h1724 ; - assign _theResult___snd_snd_snd__h131369 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - _theResult___snd_snd__h131371 : - guardBC__h115666 ; - assign _theResult___snd_snd_snd__h1481 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___snd_snd_snd__h1605 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 ; - assign _theResult___snd_snd_snd__h1520 = - (rg_res[116] || rg_b == 116'd0) ? - rg_r_1 : - _theResult___snd_snd__h1649 ; - assign _theResult___snd_snd_snd__h1605 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 : - _theResult___snd_snd__h1715 ; - assign _theResult___snd_snd_snd__h33963 = - (fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___snd__h34715 : - fpu_div64_fState_S3$D_OUT[57:0] ; - assign b___1__h77160 = 116'h40000000000000000000000000000 >> x__h85465 ; - assign b__h11457 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0) ? - (fpu_div64_fOperands_S0$D_OUT[54] ? - 6'd1 : - (fpu_div64_fOperands_S0$D_OUT[53] ? - 6'd2 : - (fpu_div64_fOperands_S0$D_OUT[52] ? - 6'd3 : - (fpu_div64_fOperands_S0$D_OUT[51] ? - 6'd4 : - (fpu_div64_fOperands_S0$D_OUT[50] ? - 6'd5 : - (fpu_div64_fOperands_S0$D_OUT[49] ? - 6'd6 : - (fpu_div64_fOperands_S0$D_OUT[48] ? - 6'd7 : - (fpu_div64_fOperands_S0$D_OUT[47] ? - 6'd8 : - (fpu_div64_fOperands_S0$D_OUT[46] ? - 6'd9 : - (fpu_div64_fOperands_S0$D_OUT[45] ? - 6'd10 : - (fpu_div64_fOperands_S0$D_OUT[44] ? - 6'd11 : - (fpu_div64_fOperands_S0$D_OUT[43] ? - 6'd12 : - (fpu_div64_fOperands_S0$D_OUT[42] ? - 6'd13 : - (fpu_div64_fOperands_S0$D_OUT[41] ? - 6'd14 : - (fpu_div64_fOperands_S0$D_OUT[40] ? - 6'd15 : - (fpu_div64_fOperands_S0$D_OUT[39] ? - 6'd16 : - (fpu_div64_fOperands_S0$D_OUT[38] ? - 6'd17 : - (fpu_div64_fOperands_S0$D_OUT[37] ? - 6'd18 : - (fpu_div64_fOperands_S0$D_OUT[36] ? - 6'd19 : - (fpu_div64_fOperands_S0$D_OUT[35] ? - 6'd20 : - (fpu_div64_fOperands_S0$D_OUT[34] ? - 6'd21 : - (fpu_div64_fOperands_S0$D_OUT[33] ? - 6'd22 : - (fpu_div64_fOperands_S0$D_OUT[32] ? - 6'd23 : - (fpu_div64_fOperands_S0$D_OUT[31] ? - 6'd24 : - (fpu_div64_fOperands_S0$D_OUT[30] ? - 6'd25 : - (fpu_div64_fOperands_S0$D_OUT[29] ? - 6'd26 : - (fpu_div64_fOperands_S0$D_OUT[28] ? - 6'd27 : - (fpu_div64_fOperands_S0$D_OUT[27] ? - 6'd28 : - (fpu_div64_fOperands_S0$D_OUT[26] ? - 6'd29 : - (fpu_div64_fOperands_S0$D_OUT[25] ? - 6'd30 : - (fpu_div64_fOperands_S0$D_OUT[24] ? - 6'd31 : - (fpu_div64_fOperands_S0$D_OUT[23] ? - 6'd32 : - (fpu_div64_fOperands_S0$D_OUT[22] ? - 6'd33 : - (fpu_div64_fOperands_S0$D_OUT[21] ? - 6'd34 : - (fpu_div64_fOperands_S0$D_OUT[20] ? - 6'd35 : - (fpu_div64_fOperands_S0$D_OUT[19] ? - 6'd36 : - (fpu_div64_fOperands_S0$D_OUT[18] ? - 6'd37 : - (fpu_div64_fOperands_S0$D_OUT[17] ? - 6'd38 : - (fpu_div64_fOperands_S0$D_OUT[16] ? - 6'd39 : - (fpu_div64_fOperands_S0$D_OUT[15] ? - 6'd40 : - (fpu_div64_fOperands_S0$D_OUT[14] ? - 6'd41 : - (fpu_div64_fOperands_S0$D_OUT[13] ? - 6'd42 : - (fpu_div64_fOperands_S0$D_OUT[12] ? - 6'd43 : - (fpu_div64_fOperands_S0$D_OUT[11] ? - 6'd44 : - (fpu_div64_fOperands_S0$D_OUT[10] ? - 6'd45 : - (fpu_div64_fOperands_S0$D_OUT[9] ? - 6'd46 : - (fpu_div64_fOperands_S0$D_OUT[8] ? - 6'd47 : - (fpu_div64_fOperands_S0$D_OUT[7] ? - 6'd48 : - (fpu_div64_fOperands_S0$D_OUT[6] ? - 6'd49 : - (fpu_div64_fOperands_S0$D_OUT[5] ? - 6'd50 : - (fpu_div64_fOperands_S0$D_OUT[4] ? - 6'd51 : - (fpu_div64_fOperands_S0$D_OUT[3] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign b__h1608 = { 2'd0, rg_b[115:2] } ; - assign b__h1712 = - { 2'd0, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49[115:2] } ; - assign b__h32583 = { rg_d, 58'd0 } ; - assign b__h4039 = - (fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0) ? - (fpu_div64_fOperands_S0$D_OUT[118] ? - 6'd1 : - (fpu_div64_fOperands_S0$D_OUT[117] ? - 6'd2 : - (fpu_div64_fOperands_S0$D_OUT[116] ? - 6'd3 : - (fpu_div64_fOperands_S0$D_OUT[115] ? - 6'd4 : - (fpu_div64_fOperands_S0$D_OUT[114] ? - 6'd5 : - (fpu_div64_fOperands_S0$D_OUT[113] ? - 6'd6 : - (fpu_div64_fOperands_S0$D_OUT[112] ? - 6'd7 : - (fpu_div64_fOperands_S0$D_OUT[111] ? - 6'd8 : - (fpu_div64_fOperands_S0$D_OUT[110] ? - 6'd9 : - (fpu_div64_fOperands_S0$D_OUT[109] ? - 6'd10 : - (fpu_div64_fOperands_S0$D_OUT[108] ? - 6'd11 : - (fpu_div64_fOperands_S0$D_OUT[107] ? - 6'd12 : - (fpu_div64_fOperands_S0$D_OUT[106] ? - 6'd13 : - (fpu_div64_fOperands_S0$D_OUT[105] ? - 6'd14 : - (fpu_div64_fOperands_S0$D_OUT[104] ? - 6'd15 : - (fpu_div64_fOperands_S0$D_OUT[103] ? - 6'd16 : - (fpu_div64_fOperands_S0$D_OUT[102] ? - 6'd17 : - (fpu_div64_fOperands_S0$D_OUT[101] ? - 6'd18 : - (fpu_div64_fOperands_S0$D_OUT[100] ? - 6'd19 : - (fpu_div64_fOperands_S0$D_OUT[99] ? - 6'd20 : - (fpu_div64_fOperands_S0$D_OUT[98] ? - 6'd21 : - (fpu_div64_fOperands_S0$D_OUT[97] ? - 6'd22 : - (fpu_div64_fOperands_S0$D_OUT[96] ? - 6'd23 : - (fpu_div64_fOperands_S0$D_OUT[95] ? - 6'd24 : - (fpu_div64_fOperands_S0$D_OUT[94] ? - 6'd25 : - (fpu_div64_fOperands_S0$D_OUT[93] ? - 6'd26 : - (fpu_div64_fOperands_S0$D_OUT[92] ? - 6'd27 : - (fpu_div64_fOperands_S0$D_OUT[91] ? - 6'd28 : - (fpu_div64_fOperands_S0$D_OUT[90] ? - 6'd29 : - (fpu_div64_fOperands_S0$D_OUT[89] ? - 6'd30 : - (fpu_div64_fOperands_S0$D_OUT[88] ? - 6'd31 : - (fpu_div64_fOperands_S0$D_OUT[87] ? - 6'd32 : - (fpu_div64_fOperands_S0$D_OUT[86] ? - 6'd33 : - (fpu_div64_fOperands_S0$D_OUT[85] ? - 6'd34 : - (fpu_div64_fOperands_S0$D_OUT[84] ? - 6'd35 : - (fpu_div64_fOperands_S0$D_OUT[83] ? - 6'd36 : - (fpu_div64_fOperands_S0$D_OUT[82] ? - 6'd37 : - (fpu_div64_fOperands_S0$D_OUT[81] ? - 6'd38 : - (fpu_div64_fOperands_S0$D_OUT[80] ? - 6'd39 : - (fpu_div64_fOperands_S0$D_OUT[79] ? - 6'd40 : - (fpu_div64_fOperands_S0$D_OUT[78] ? - 6'd41 : - (fpu_div64_fOperands_S0$D_OUT[77] ? - 6'd42 : - (fpu_div64_fOperands_S0$D_OUT[76] ? - 6'd43 : - (fpu_div64_fOperands_S0$D_OUT[75] ? - 6'd44 : - (fpu_div64_fOperands_S0$D_OUT[74] ? - 6'd45 : - (fpu_div64_fOperands_S0$D_OUT[73] ? - 6'd46 : - (fpu_div64_fOperands_S0$D_OUT[72] ? - 6'd47 : - (fpu_div64_fOperands_S0$D_OUT[71] ? - 6'd48 : - (fpu_div64_fOperands_S0$D_OUT[70] ? - 6'd49 : - (fpu_div64_fOperands_S0$D_OUT[69] ? - 6'd50 : - (fpu_div64_fOperands_S0$D_OUT[68] ? - 6'd51 : - (fpu_div64_fOperands_S0$D_OUT[67] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign din_exp30866_MINUS_1023__q23 = din_exp__h130866 - 11'd1023 ; - assign din_exp__h130866 = - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ? - value__h130883[10:0] : - 11'd0 ; - assign din_inc___2_exp__h142626 = fpu_madd_fState_S8$D_OUT[65:55] + 11'd1 ; - assign din_inc___2_exp__h182469 = _theResult___fst_exp__h163336 + 11'd1 ; - assign din_inc___2_exp__h182504 = _theResult___fst_exp__h172852 + 11'd1 ; - assign din_inc___2_exp__h182530 = _theResult___fst_exp__h181653 + 11'd1 ; - assign din_inc___2_exp__h221107 = _theResult___fst_exp__h201974 + 11'd1 ; - assign din_inc___2_exp__h221142 = _theResult___fst_exp__h211490 + 11'd1 ; - assign din_inc___2_exp__h221168 = _theResult___fst_exp__h220291 + 11'd1 ; - assign din_inc___2_exp__h260046 = _theResult___fst_exp__h240913 + 11'd1 ; - assign din_inc___2_exp__h260081 = _theResult___fst_exp__h250429 + 11'd1 ; - assign din_inc___2_exp__h260107 = _theResult___fst_exp__h259230 + 11'd1 ; - assign din_inc___2_exp__h304723 = _theResult___fst_exp__h277686 + 8'd1 ; - assign din_inc___2_exp__h304749 = _theResult___fst_exp__h286342 + 8'd1 ; - assign din_inc___2_exp__h304784 = _theResult___fst_exp__h295452 + 8'd1 ; - assign din_inc___2_exp__h304810 = _theResult___fst_exp__h304137 + 8'd1 ; - assign din_inc___2_exp__h43566 = fpu_div64_fState_S4$D_OUT[64:54] + 11'd1 ; - assign din_inc___2_exp__h96000 = fpu_sqr64_fState_S4$D_OUT[64:54] + 11'd1 ; - assign exp__h304706 = - (resWire$wget[67:57] == 11'd2047) ? - 8'd255 : - _theResult___fst_exp__h304697 ; - assign fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7 = - fpu_div64_fOperands_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8 = - fpu_div64_fOperands_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401 ; - assign fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359 = - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - !IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ; - assign fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 = - fpu_div64_fOperands_S0$D_OUT[130] == - fpu_div64_fOperands_S0$D_OUT[66] ; - assign fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936 = - { fpu_div64_fState_S3$D_OUT[121], - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 ? - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929 : - ((fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - { _theResult___fst_exp__h42284, - fpu_div64_fState_S3$D_OUT[109:58] } : - 63'h7FEFFFFFFFFFFFFF) : - fpu_div64_fState_S3$D_OUT[120:58]) } ; - assign fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 = - fpu_madd_fOperand_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 = - fpu_madd_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 = - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 || - x__h96539 == 11'd0 && _theResult___fst_sfd__h96608 == 52'd0 && - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) && - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 ; - assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 = - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 = - (fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194]) == - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 ; - assign fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012 = - fpu_madd_fProd_S3$D_OUT >> - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ; - assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 = - (fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ; - assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 = - (fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ; - assign fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501 = - fpu_madd_fState_S3$D_OUT[86:82] | - { 2'd0, - sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023, - _theResult___fst_exp__h130952 == 11'd0 && - guardBC__h115666 != 2'd0, - sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023 } ; - assign fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27 = - fpu_madd_fState_S4$D_OUT[128:118] - 11'd1023 ; - assign fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26 = - fpu_madd_fState_S4$D_OUT[64:54] - 11'd1023 ; - assign fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615 = - fpu_madd_fState_S5$D_OUT[56:0] >> - fpu_madd_fState_S5$D_OUT[126:114] ; - assign fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942 = - fpu_madd_fState_S7$D_OUT[137:133] | - { 2'd0, - sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023, - _theResult___fst_exp__h141378 == 11'd0 && - guard__h133123 != 2'd0, - sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023 } ; - assign fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 = - fpu_madd_fState_S8$D_OUT[75:71] | - { 2'd0, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 == - 11'd2047 && - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h142620) == - 52'd0, - 1'd0, - fpu_madd_fState_S8$D_OUT[65:55] != 11'd2047 && - fpu_madd_fState_S8$D_OUT[2:1] != 2'b0 } ; - assign fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16 = - fpu_sqr64_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18 = - fpu_sqr64_fState_S3$D_OUT[121:111] - 11'd1023 ; - assign guardBC__h115666 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h131051 ; - assign guard__h132367 = fpu_madd_fState_S5$D_OUT[56:0] << x__h132471 ; - assign guard__h133123 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h141477 ; - assign guard__h155375 = - { IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34[1], - { _theResult___snd__h163287[3:0], 52'd0 } != 56'd0 } ; - assign guard__h164624 = - { IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38[1], - { sfdin__h172846[3:0], 52'd0 } != 56'd0 } ; - assign guard__h165222 = x__h165324 != 57'd0 ; - assign guard__h173663 = - { IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41[1], - { _theResult___snd__h181599[3:0], 52'd0 } != 56'd0 } ; - assign guard__h194013 = - { IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94[1], - { _theResult___snd__h201925[3:0], 52'd0 } != 56'd0 } ; - assign guard__h203262 = - { IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98[1], - { sfdin__h211484[3:0], 52'd0 } != 56'd0 } ; - assign guard__h203860 = x__h203962 != 57'd0 ; - assign guard__h212301 = - { IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h220237[3:0], 52'd0 } != 56'd0 } ; - assign guard__h232952 = - { IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61[1], - { _theResult___snd__h240864[3:0], 52'd0 } != 56'd0 } ; - assign guard__h242201 = - { IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65[1], - { sfdin__h250423[3:0], 52'd0 } != 56'd0 } ; - assign guard__h242799 = x__h242901 != 57'd0 ; - assign guard__h251240 = - { IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68[1], - { _theResult___snd__h259176[3:0], 52'd0 } != 56'd0 } ; - assign guard__h269587 = - { IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134[1], - { sfdin__h277680[32:0], 23'd0 } != 56'd0 } ; - assign guard__h278294 = - { IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136[1], - { _theResult___snd__h286293[32:0], 23'd0 } != 56'd0 } ; - assign guard__h287224 = - { IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140[1], - { sfdin__h295446[32:0], 23'd0 } != 56'd0 } ; - assign guard__h287822 = x__h287924 != 57'd0 ; - assign guard__h296060 = - { IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143[1], - { _theResult___snd__h304083[32:0], 23'd0 } != 56'd0 } ; - assign guard__h33946 = x__h42705 ; - assign guard__h86435 = x__h95138 ; - assign iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 = - iFifo$D_OUT[102:95] - 8'd127 ; - assign iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 = - iFifo$D_OUT[167:160] - 8'd127 ; - assign iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 = - iFifo$D_OUT[37:30] - 8'd127 ; - assign out___1_sfd__h144235 = { iFifo$D_OUT[159:137], 29'd0 } ; - assign out___1_sfd__h182875 = { iFifo$D_OUT[94:72], 29'd0 } ; - assign out___1_sfd__h221814 = { iFifo$D_OUT[29:7], 29'd0 } ; - assign out_exp__h142544 = - fpu_madd_fState_S8$D_OUT[3] ? - _theResult___exp__h142541 : - fpu_madd_fState_S8$D_OUT[65:55] ; - assign out_exp__h163984 = - _theResult___snd__h163287[5] ? - _theResult___exp__h163981 : - _theResult___fst_exp__h163336 ; - assign out_exp__h173574 = - sfdin__h172846[5] ? - _theResult___exp__h173571 : - _theResult___fst_exp__h172852 ; - assign out_exp__h182326 = - _theResult___snd__h181599[5] ? - _theResult___exp__h182323 : - _theResult___fst_exp__h181653 ; - assign out_exp__h202622 = - _theResult___snd__h201925[5] ? - _theResult___exp__h202619 : - _theResult___fst_exp__h201974 ; - assign out_exp__h212212 = - sfdin__h211484[5] ? - _theResult___exp__h212209 : - _theResult___fst_exp__h211490 ; - assign out_exp__h220964 = - _theResult___snd__h220237[5] ? - _theResult___exp__h220961 : - _theResult___fst_exp__h220291 ; - assign out_exp__h241561 = - _theResult___snd__h240864[5] ? - _theResult___exp__h241558 : - _theResult___fst_exp__h240913 ; - assign out_exp__h251151 = - sfdin__h250423[5] ? - _theResult___exp__h251148 : - _theResult___fst_exp__h250429 ; - assign out_exp__h259903 = - _theResult___snd__h259176[5] ? - _theResult___exp__h259900 : - _theResult___fst_exp__h259230 ; - assign out_exp__h278205 = - sfdin__h277680[34] ? - _theResult___exp__h278202 : - _theResult___fst_exp__h277686 ; - assign out_exp__h286787 = - _theResult___snd__h286293[34] ? - _theResult___exp__h286784 : - _theResult___fst_exp__h286342 ; - assign out_exp__h295971 = - sfdin__h295446[34] ? - _theResult___exp__h295968 : - _theResult___fst_exp__h295452 ; - assign out_exp__h304607 = - _theResult___snd__h304083[34] ? - _theResult___exp__h304604 : - _theResult___fst_exp__h304137 ; - assign out_exp__h43478 = - fpu_div64_fState_S4$D_OUT[2] ? - _theResult___exp__h43475 : - fpu_div64_fState_S4$D_OUT[64:54] ; - assign out_exp__h95912 = - fpu_sqr64_fState_S4$D_OUT[2] ? - _theResult___exp__h95909 : - fpu_sqr64_fState_S4$D_OUT[64:54] ; - assign out_sfd__h142545 = - fpu_madd_fState_S8$D_OUT[3] ? - _theResult___sfd__h142542 : - fpu_madd_fState_S8$D_OUT[54:3] ; - assign out_sfd__h163985 = - _theResult___snd__h163287[5] ? - _theResult___sfd__h163982 : - _theResult___snd__h163287[56:5] ; - assign out_sfd__h173575 = - sfdin__h172846[5] ? - _theResult___sfd__h173572 : - sfdin__h172846[56:5] ; - assign out_sfd__h182327 = - _theResult___snd__h181599[5] ? - _theResult___sfd__h182324 : - _theResult___snd__h181599[56:5] ; - assign out_sfd__h202623 = - _theResult___snd__h201925[5] ? - _theResult___sfd__h202620 : - _theResult___snd__h201925[56:5] ; - assign out_sfd__h212213 = - sfdin__h211484[5] ? - _theResult___sfd__h212210 : - sfdin__h211484[56:5] ; - assign out_sfd__h220965 = - _theResult___snd__h220237[5] ? - _theResult___sfd__h220962 : - _theResult___snd__h220237[56:5] ; - assign out_sfd__h241562 = - _theResult___snd__h240864[5] ? - _theResult___sfd__h241559 : - _theResult___snd__h240864[56:5] ; - assign out_sfd__h251152 = - sfdin__h250423[5] ? - _theResult___sfd__h251149 : - sfdin__h250423[56:5] ; - assign out_sfd__h259904 = - _theResult___snd__h259176[5] ? - _theResult___sfd__h259901 : - _theResult___snd__h259176[56:5] ; - assign out_sfd__h278206 = - sfdin__h277680[34] ? - _theResult___sfd__h278203 : - sfdin__h277680[56:34] ; - assign out_sfd__h286788 = - _theResult___snd__h286293[34] ? - _theResult___sfd__h286785 : - _theResult___snd__h286293[56:34] ; - assign out_sfd__h295972 = - sfdin__h295446[34] ? - _theResult___sfd__h295969 : - sfdin__h295446[56:34] ; - assign out_sfd__h304608 = - _theResult___snd__h304083[34] ? - _theResult___sfd__h304605 : - _theResult___snd__h304083[56:34] ; - assign out_sfd__h43479 = - fpu_div64_fState_S4$D_OUT[2] ? - _theResult___sfd__h43476 : - fpu_div64_fState_S4$D_OUT[53:2] ; - assign out_sfd__h95913 = - fpu_sqr64_fState_S4$D_OUT[2] ? - _theResult___sfd__h95910 : - fpu_sqr64_fState_S4$D_OUT[53:2] ; - assign r__h1659 = r__h1663 + rg_b ; - assign r__h1663 = { 1'd0, rg_r_1[115:1] } ; - assign r__h1724 = - r__h1753 + - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign r__h1753 = - { 1'd0, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69[115:1] } ; - assign resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 = - resWire$wget[4:0] | - { (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 } ; - assign resWirewget_BITS_67_TO_57_MINUS_1023__q137 = - resWire$wget[67:57] - 11'd1023 ; - assign result__h132372 = - { fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[56:1], - fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[0] | - guard__h132367 != 57'd0 } ; - assign result__h165227 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[0] | - guard__h165222 } ; - assign result__h203865 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[0] | - guard__h203860 } ; - assign result__h242804 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[0] | - guard__h242799 } ; - assign result__h287827 = - { _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[56:1], - _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[0] | - guard__h287822 } ; - assign result__h32617 = { _theResult____h32523[57:1], 1'd1 } ; - assign result__h32648 = - { 1'd0, - value__h32661[56:1], - value__h32661[0] | sfdlsb__h32643 } ; - assign result__h32823 = - (IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] == - 57'd0) ? - 58'd0 : - 58'd1 ; - assign result__h85925 = { x__h85931[58:1], 1'd1 } ; - assign rg_index_1_4_PLUS_1_6_ULE_58___d37 = rg_index_1 + 6'd1 <= 6'd58 ; - assign rg_index_1_4_ULE_58___d38 = rg_index_1 <= 6'd58 ; - assign rg_index_PLUS_1_ULE_57___d6 = rg_index + 6'd1 <= 6'd57 ; - assign rg_index_ULE_57___d7 = rg_index <= 6'd57 ; - assign rg_q_PLUS_NEG_INV_rg_q_59_60___d561 = rg_q + -(~rg_q) ; - assign rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63 = rg_s < sum__h1606 ; - assign s__h1658 = rg_s - sum__h1606 ; - assign s__h1723 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 - - sum__h1710 ; - assign sfdA__h131577 = - { 1'b0, - fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } ; - assign sfdA__h2035 = - { fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0, - fpu_div64_fOperands_S0$D_OUT[118:67] } ; - assign sfdA__h2039 = sfdA__h2035 << b__h4039 ; - assign sfdBC__h115662 = - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ? - fpu_madd_fProd_S3$D_OUT : - _theResult___fst__h116827 ; - assign sfdBC__h131578 = - { 1'b0, - fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } ; - assign sfdB__h2036 = - { fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0, - fpu_div64_fOperands_S0$D_OUT[54:3] } ; - assign sfdB__h2041 = sfdB__h2036 << b__h11457 ; - assign sfd___1__h60702 = { 1'd0, sfd__h44953[57:1] } ; - assign sfd__h133119 = - fpu_madd_fState_S7$D_OUT[128] ? - fpu_madd_fState_S7$D_OUT[56:0] : - fpu_madd_fState_S7$D_OUT[113:57] ; - assign sfd__h142040 = - { 1'b0, - fpu_madd_fState_S8$D_OUT[65:55] != 11'd0, - fpu_madd_fState_S8$D_OUT[54:3] } + - 54'd1 ; - assign sfd__h144536 = { value__h148923, 32'd0 } ; - assign sfd__h163354 = - { 1'b0, - _theResult___fst_exp__h163336 != 11'd0, - _theResult___snd__h163287[56:5] } + - 54'd1 ; - assign sfd__h172944 = - { 1'b0, - _theResult___fst_exp__h172852 != 11'd0, - sfdin__h172846[56:5] } + - 54'd1 ; - assign sfd__h181672 = - { 1'b0, - _theResult___fst_exp__h181653 != 11'd0, - _theResult___snd__h181599[56:5] } + - 54'd1 ; - assign sfd__h183176 = { value__h187561, 32'd0 } ; - assign sfd__h18934 = { 1'd1, fpu_div64_fOperands_S0$D_OUT[117:67] } ; - assign sfd__h18937 = { 1'd1, fpu_div64_fOperands_S0$D_OUT[53:3] } ; - assign sfd__h201992 = - { 1'b0, - _theResult___fst_exp__h201974 != 11'd0, - _theResult___snd__h201925[56:5] } + - 54'd1 ; - assign sfd__h211582 = - { 1'b0, - _theResult___fst_exp__h211490 != 11'd0, - sfdin__h211484[56:5] } + - 54'd1 ; - assign sfd__h220310 = - { 1'b0, - _theResult___fst_exp__h220291 != 11'd0, - _theResult___snd__h220237[56:5] } + - 54'd1 ; - assign sfd__h222115 = { value__h226500, 32'd0 } ; - assign sfd__h240931 = - { 1'b0, - _theResult___fst_exp__h240913 != 11'd0, - _theResult___snd__h240864[56:5] } + - 54'd1 ; - assign sfd__h250521 = - { 1'b0, - _theResult___fst_exp__h250429 != 11'd0, - sfdin__h250423[56:5] } + - 54'd1 ; - assign sfd__h259249 = - { 1'b0, - _theResult___fst_exp__h259230 != 11'd0, - _theResult___snd__h259176[56:5] } + - 54'd1 ; - assign sfd__h261975 = { value__h270197, 3'd0 } ; - assign sfd__h277778 = - { 1'b0, - _theResult___fst_exp__h277686 != 8'd0, - sfdin__h277680[56:34] } + - 25'd1 ; - assign sfd__h286360 = - { 1'b0, - _theResult___fst_exp__h286342 != 8'd0, - _theResult___snd__h286293[56:34] } + - 25'd1 ; - assign sfd__h295544 = - { 1'b0, - _theResult___fst_exp__h295452 != 8'd0, - sfdin__h295446[56:34] } + - 25'd1 ; - assign sfd__h304156 = - { 1'b0, - _theResult___fst_exp__h304137 != 8'd0, - _theResult___snd__h304083[56:34] } + - 25'd1 ; - assign sfd__h304707 = - (resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h261925 : - _theResult___fst_sfd__h304701 ; - assign sfd__h42982 = - { 1'b0, - fpu_div64_fState_S4$D_OUT[64:54] != 11'd0, - fpu_div64_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfd__h44951 = { value__h53174, 4'd0 } ; - assign sfd__h44953 = sfd__h44951 << x__h60732 ; - assign sfd__h45004 = { 1'd1, fpu_sqr64_fOperand_S0$D_OUT[53:3] } ; - assign sfd__h95416 = - { 1'b0, - fpu_sqr64_fState_S4$D_OUT[64:54] != 11'd0, - fpu_sqr64_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfd__h99402 = { 1'd1, _theResult___fst_sfd__h96608[50:0] } ; - assign sfd__h99405 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[117:67] } ; - assign sfd__h99408 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[53:3] } ; - assign sfdin__h130943 = - sfdBC__h115662[105] ? - _theResult___snd__h130966 : - _theResult___snd__h130980 ; - assign sfdin__h141369 = - sfd__h133119[56] ? - _theResult___snd__h141392 : - _theResult___snd__h141406 ; - assign sfdin__h172846 = - _theResult____h164614[56] ? - _theResult___snd__h172863 : - _theResult___snd__h172874 ; - assign sfdin__h211484 = - _theResult____h203252[56] ? - _theResult___snd__h211501 : - _theResult___snd__h211512 ; - assign sfdin__h250423 = - _theResult____h242191[56] ? - _theResult___snd__h250440 : - _theResult___snd__h250451 ; - assign sfdin__h277680 = - _theResult____h269577[56] ? - _theResult___snd__h277697 : - _theResult___snd__h277708 ; - assign sfdin__h295446 = - _theResult____h287214[56] ? - _theResult___snd__h295463 : - _theResult___snd__h295474 ; - assign sfdin__h34118 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___snd_snd_snd__h33963 : - fpu_div64_fState_S3$D_OUT[57:0] ; - assign sfdin__h42327 = - sfdin__h34118[57] ? - _theResult___snd__h42350 : - _theResult___snd__h42365 ; - assign sfdin__h94744 = - fpu_sqr64_fState_S3$D_OUT[58] ? - _theResult___snd__h94767 : - _theResult___snd__h94782 ; - assign sfdlsb__h116825 = x__h116896 != 106'd0 ; - assign sfdlsb__h32643 = x__h32762 != 58'd0 ; - assign sum__h1606 = rg_r_1 + rg_b ; - assign sum__h1710 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 + - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign theResult___fst_exp2290_MINUS_1023__q11 = - _theResult___fst_exp__h42290 - 11'd1023 ; - assign value41307_BITS_10_TO_0_MINUS_1023__q28 = - value__h141307[10:0] - 11'd1023 ; - assign value_BIT_52___h53270 = fpu_sqr64_fOperand_S0$D_OUT[65:55] != 11'd0 ; - assign value__h130883 = fpu_madd_fState_S3$D_OUT[12:0] + 13'd1023 ; - assign value__h141307 = fpu_madd_fState_S7$D_OUT[126:114] + 13'd1023 ; - assign value__h148923 = - { 1'b0, iFifo$D_OUT[167:160] != 8'd0, iFifo$D_OUT[159:137] } ; - assign value__h187561 = - { 1'b0, iFifo$D_OUT[102:95] != 8'd0, iFifo$D_OUT[94:72] } ; - assign value__h226500 = - { 1'b0, iFifo$D_OUT[37:30] != 8'd0, iFifo$D_OUT[29:7] } ; - assign value__h270197 = - { 1'b0, resWire$wget[67:57] != 11'd0, resWire$wget[56:5] } ; - assign value__h31374 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 + - 13'd1023 ; - assign value__h31429 = { 1'b0, sfdA__h2039 } ; - assign value__h31550 = - 13'd7170 - - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ; - assign value__h32541 = rg_r[115] ? rg_r + b__h32583 : rg_r ; - assign value__h32661 = - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] >> - fpu_div64_fState_S2$D_OUT[10:0] ; - assign value__h53174 = - { 1'b0, - value_BIT_52___h53270, - fpu_sqr64_fOperand_S0$D_OUT[54:3] } ; - assign x__h114243 = - { fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0, - fpu_madd_fOperand_S0$D_OUT[118:67] } ; - assign x__h114255 = - { fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0, - fpu_madd_fOperand_S0$D_OUT[54:3] } ; - assign x__h116896 = fpu_madd_fProd_S3$D_OUT << x__h116929 ; - assign x__h116929 = - 13'd106 - - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ; - assign x__h131406 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - _theResult___snd_snd_snd__h131369 : - 2'd3 ; - assign x__h131940 = - { 1'b0, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - { fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } : - { fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } } ; - assign x__h131944 = - { 1'b0, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - { fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } : - { fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } } ; - assign x__h132359 = - fpu_madd_fState_S5$D_OUT[215] ? - fpu_madd_fState_S5$D_OUT[56:0] : - (((fpu_madd_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ? - result__h132372 : - ((fpu_madd_fState_S5$D_OUT[56:0] == 57'd0) ? - fpu_madd_fState_S5$D_OUT[56:0] : - 57'd1)) ; - assign x__h132471 = 13'd57 - fpu_madd_fState_S5$D_OUT[126:114] ; - assign x__h132871 = - fpu_madd_fState_S6$D_OUT[113:57] + - fpu_madd_fState_S6$D_OUT[56:0] ; - assign x__h132880 = - fpu_madd_fState_S6$D_OUT[113:57] - - fpu_madd_fState_S6$D_OUT[56:0] ; - assign x__h141760 = fpu_madd_fState_S7$D_OUT[202] ? 2'd0 : guard__h133123 ; - assign x__h165324 = sfd__h144536 << x__h165357 ; - assign x__h165357 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ; - assign x__h203962 = sfd__h183176 << x__h203995 ; - assign x__h203995 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ; - assign x__h242901 = sfd__h222115 << x__h242934 ; - assign x__h242934 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ; - assign x__h287924 = sfd__h261975 << x__h287957 ; - assign x__h287957 = - 12'd57 - - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ; - assign x__h31426 = { value__h31429, 60'd0 } ; - assign x__h31487 = { sfdB__h2041, 4'b0 } ; - assign x__h31541 = - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363 ? - 11'd0 : - _theResult___fst__h31322 ; - assign x__h32762 = - { 1'd0, - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] } << - x__h32769 ; - assign x__h32769 = 11'd58 - fpu_div64_fState_S2$D_OUT[10:0] ; - assign x__h33052 = - (value__h32541[114:58] == 57'd0) ? - _theResult____h32523 : - result__h32617 ; - assign x__h42705 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h42439 ; - assign x__h52551 = x__h52569 + 13'd1024 ; - assign x__h52569 = - { IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17[11], - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17 } ; - assign x__h60693 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195[0] ? - sfd__h44953 : - sfd___1__h60702 ; - assign x__h60732 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 - - 6'd1 ; - assign x__h85465 = - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342[0] ? - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 + - 7'd1 : - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 ; - assign x__h85931 = rg_res[116] ? rg_res[115:0] : 116'd0 ; - assign x__h86149 = (rg_s == 116'd0) ? x__h85931[58:0] : result__h85925 ; - assign x__h95138 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h94856 ; - assign x__h96539 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[193:183] : - 11'd0 ; - always@(fpu_div64_fState_S4$D_OUT or - out_sfd__h43479 or _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - fpu_div64_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - out_sfd__h43479; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - _theResult___sfd__h43476; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 = - fpu_div64_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 = - _theResult___sfd__h43476; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 or - _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h43554 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1; - 3'd1: - _theResult___fst_sfd__h43554 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2; - 3'd2: - _theResult___fst_sfd__h43554 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[53:2] : - _theResult___sfd__h43476; - 3'd3: - _theResult___fst_sfd__h43554 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[53:2] : - (fpu_div64_fState_S4$D_OUT[65] ? - _theResult___sfd__h43476 : - fpu_div64_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h43554 = fpu_div64_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h43554 = 52'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - out_sfd__h95913 or _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - fpu_sqr64_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - out_sfd__h95913; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - _theResult___sfd__h95910; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 = - fpu_sqr64_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 = - _theResult___sfd__h95910; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 or - _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h95988 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3; - 3'd1: - _theResult___fst_sfd__h95988 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4; - 3'd2: - _theResult___fst_sfd__h95988 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - _theResult___sfd__h95910; - 3'd3: - _theResult___fst_sfd__h95988 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - _theResult___sfd__h95910 : - fpu_sqr64_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h95988 = fpu_sqr64_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h95988 = 52'd0; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - out_sfd__h142545 or _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - fpu_madd_fState_S8$D_OUT[54:3]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - out_sfd__h142545; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - _theResult___sfd__h142542; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 = - fpu_madd_fState_S8$D_OUT[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 = - _theResult___sfd__h142542; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 or - _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_sfd__h142620 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5; - 3'd1: - _theResult___fst_sfd__h142620 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6; - 3'd2: - _theResult___fst_sfd__h142620 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___sfd__h142542; - 3'd3: - _theResult___fst_sfd__h142620 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[54:3] : - (fpu_madd_fState_S8$D_OUT[66] ? - _theResult___sfd__h142542 : - fpu_madd_fState_S8$D_OUT[54:3]); - 3'd4: _theResult___fst_sfd__h142620 = fpu_madd_fState_S8$D_OUT[54:3]; - default: _theResult___fst_sfd__h142620 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h148291 = 11'd2047; - 3'd2: - _theResult___fst_exp__h148291 = - iFifo$D_OUT[168] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h148291 = - iFifo$D_OUT[168] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h148291 = 11'd2046; - default: _theResult___fst_exp__h148291 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h148292 = 52'd0; - 3'd2: - _theResult___fst_sfd__h148292 = - iFifo$D_OUT[168] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h148292 = - iFifo$D_OUT[168] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h148292 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h148292 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h186931 = 11'd2047; - 3'd2: - _theResult___fst_exp__h186931 = - iFifo$D_OUT[103] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h186931 = - iFifo$D_OUT[103] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h186931 = 11'd2046; - default: _theResult___fst_exp__h186931 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h225870 = 11'd2047; - 3'd2: - _theResult___fst_exp__h225870 = - iFifo$D_OUT[38] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h225870 = - iFifo$D_OUT[38] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h225870 = 11'd2046; - default: _theResult___fst_exp__h225870 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h186932 = 52'd0; - 3'd2: - _theResult___fst_sfd__h186932 = - iFifo$D_OUT[103] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h186932 = - iFifo$D_OUT[103] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h186932 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h186932 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h225871 = 52'd0; - 3'd2: - _theResult___fst_sfd__h225871 = - iFifo$D_OUT[38] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h225871 = - iFifo$D_OUT[38] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h225871 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h225871 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_exp__h19467 = 11'd2047; - 3'd2: - _theResult___fst_exp__h19467 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 11'd2047 : - 11'd2046; - 3'd3: - _theResult___fst_exp__h19467 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 11'd2046 : - 11'd2047; - 3'd4: _theResult___fst_exp__h19467 = 11'd2046; - default: _theResult___fst_exp__h19467 = 11'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_sfd__h19468 = 52'd0; - 3'd2: - _theResult___fst_sfd__h19468 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'd3: - _theResult___fst_sfd__h19468 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'hFFFFFFFFFFFFF : - 52'd0; - 3'd4: _theResult___fst_sfd__h19468 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h19468 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0: _theResult___fst_sfd__h19957 = 52'd0; - 3'd1: _theResult___fst_sfd__h19957 = 52'd1; - 3'd2: - _theResult___fst_sfd__h19957 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd1 : - 52'd0; - 3'd3: - _theResult___fst_sfd__h19957 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd0 : - 52'd1; - default: _theResult___fst_sfd__h19957 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 = - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405; - default: CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 = - fpu_div64_fOperands_S0$D_OUT[2:0] == 3'd4 && - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - out_exp__h43478 or _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - fpu_div64_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - out_exp__h43478; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - _theResult___exp__h43475; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 = - fpu_div64_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 = - _theResult___exp__h43475; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 or - _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h43553 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14; - 3'd1: - _theResult___fst_exp__h43553 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15; - 3'd2: - _theResult___fst_exp__h43553 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[64:54] : - _theResult___exp__h43475; - 3'd3: - _theResult___fst_exp__h43553 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[64:54] : - (fpu_div64_fState_S4$D_OUT[65] ? - _theResult___exp__h43475 : - fpu_div64_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h43553 = fpu_div64_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h43553 = 11'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - out_exp__h95912 or _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - fpu_sqr64_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - out_exp__h95912; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - _theResult___exp__h95909; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 = - fpu_sqr64_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 = - _theResult___exp__h95909; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 or - _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h95987 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21; - 3'd1: - _theResult___fst_exp__h95987 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22; - 3'd2: - _theResult___fst_exp__h95987 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - _theResult___exp__h95909; - 3'd3: - _theResult___fst_exp__h95987 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - _theResult___exp__h95909 : - fpu_sqr64_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h95987 = fpu_sqr64_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h95987 = 11'd0; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - out_exp__h142544 or _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - fpu_madd_fState_S8$D_OUT[65:55]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - out_exp__h142544; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - _theResult___exp__h142541; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 = - fpu_madd_fState_S8$D_OUT[65:55]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 = - _theResult___exp__h142541; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 or - _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_exp__h142619 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31; - 3'd1: - _theResult___fst_exp__h142619 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32; - 3'd2: - _theResult___fst_exp__h142619 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[65:55] : - _theResult___exp__h142541; - 3'd3: - _theResult___fst_exp__h142619 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[65:55] : - (fpu_madd_fState_S8$D_OUT[66] ? - _theResult___exp__h142541 : - fpu_madd_fState_S8$D_OUT[65:55]); - 3'd4: _theResult___fst_exp__h142619 = fpu_madd_fState_S8$D_OUT[65:55]; - default: _theResult___fst_exp__h142619 = 11'd0; - endcase - end - always@(guard__h155375 or - _theResult___fst_exp__h163336 or - out_exp__h163984 or _theResult___exp__h163981) - begin - case (guard__h155375) - 2'b0, 2'b01: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - _theResult___fst_exp__h163336; - 2'b10: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - out_exp__h163984; - 2'b11: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - _theResult___exp__h163981; - endcase - end - always@(guard__h155375 or - _theResult___fst_exp__h163336 or _theResult___exp__h163981) - begin - case (guard__h155375) - 2'b0: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 = - _theResult___fst_exp__h163336; - 2'b01, 2'b10, 2'b11: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 = - _theResult___exp__h163981; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 or - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 or - _theResult___fst_exp__h163336) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h164059 = - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42; - 3'd1: - _theResult___fst_exp__h164059 = - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43; - 3'd2: - _theResult___fst_exp__h164059 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690; - 3'd3: - _theResult___fst_exp__h164059 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692; - 3'd4: _theResult___fst_exp__h164059 = _theResult___fst_exp__h163336; - default: _theResult___fst_exp__h164059 = 11'd0; - endcase - end - always@(guard__h164624 or - _theResult___fst_exp__h172852 or - out_exp__h173574 or _theResult___exp__h173571) - begin - case (guard__h164624) - 2'b0, 2'b01: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - _theResult___fst_exp__h172852; - 2'b10: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - out_exp__h173574; - 2'b11: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - _theResult___exp__h173571; - endcase - end - always@(guard__h164624 or - _theResult___fst_exp__h172852 or _theResult___exp__h173571) - begin - case (guard__h164624) - 2'b0: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 = - _theResult___fst_exp__h172852; - 2'b01, 2'b10, 2'b11: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 = - _theResult___exp__h173571; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 or - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 or - _theResult___fst_exp__h172852) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h173649 = - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44; - 3'd1: - _theResult___fst_exp__h173649 = - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45; - 3'd2: - _theResult___fst_exp__h173649 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729; - 3'd3: - _theResult___fst_exp__h173649 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731; - 3'd4: _theResult___fst_exp__h173649 = _theResult___fst_exp__h172852; - default: _theResult___fst_exp__h173649 = 11'd0; - endcase - end - always@(guard__h173663 or - _theResult___fst_exp__h181653 or - out_exp__h182326 or _theResult___exp__h182323) - begin - case (guard__h173663) - 2'b0, 2'b01: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - _theResult___fst_exp__h181653; - 2'b10: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - out_exp__h182326; - 2'b11: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - _theResult___exp__h182323; - endcase - end - always@(guard__h173663 or - _theResult___fst_exp__h181653 or _theResult___exp__h182323) - begin - case (guard__h173663) - 2'b0: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 = - _theResult___fst_exp__h181653; - 2'b01, 2'b10, 2'b11: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 = - _theResult___exp__h182323; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 or - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 or - _theResult___fst_exp__h181653) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h182401 = - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46; - 3'd1: - _theResult___fst_exp__h182401 = - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47; - 3'd2: - _theResult___fst_exp__h182401 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760; - 3'd3: - _theResult___fst_exp__h182401 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762; - 3'd4: _theResult___fst_exp__h182401 = _theResult___fst_exp__h181653; - default: _theResult___fst_exp__h182401 = 11'd0; - endcase - end - always@(guard__h155375 or - _theResult___snd__h163287 or - out_sfd__h163985 or _theResult___sfd__h163982) - begin - case (guard__h155375) - 2'b0, 2'b01: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - _theResult___snd__h163287[56:5]; - 2'b10: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - out_sfd__h163985; - 2'b11: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - _theResult___sfd__h163982; - endcase - end - always@(guard__h155375 or - _theResult___snd__h163287 or _theResult___sfd__h163982) - begin - case (guard__h155375) - 2'b0: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 = - _theResult___snd__h163287[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 = - _theResult___sfd__h163982; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 or - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 or - _theResult___snd__h163287) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h164060 = - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48; - 3'd1: - _theResult___fst_sfd__h164060 = - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49; - 3'd2: - _theResult___fst_sfd__h164060 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786; - 3'd3: - _theResult___fst_sfd__h164060 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788; - 3'd4: _theResult___fst_sfd__h164060 = _theResult___snd__h163287[56:5]; - default: _theResult___fst_sfd__h164060 = 52'd0; - endcase - end - always@(guard__h164624 or - sfdin__h172846 or out_sfd__h173575 or _theResult___sfd__h173572) - begin - case (guard__h164624) - 2'b0, 2'b01: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - sfdin__h172846[56:5]; - 2'b10: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - out_sfd__h173575; - 2'b11: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - _theResult___sfd__h173572; - endcase - end - always@(guard__h164624 or sfdin__h172846 or _theResult___sfd__h173572) - begin - case (guard__h164624) - 2'b0: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 = - sfdin__h172846[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 = - _theResult___sfd__h173572; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 or - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 or - sfdin__h172846) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h173650 = - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50; - 3'd1: - _theResult___fst_sfd__h173650 = - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51; - 3'd2: - _theResult___fst_sfd__h173650 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813; - 3'd3: - _theResult___fst_sfd__h173650 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815; - 3'd4: _theResult___fst_sfd__h173650 = sfdin__h172846[56:5]; - default: _theResult___fst_sfd__h173650 = 52'd0; - endcase - end - always@(guard__h173663 or - _theResult___snd__h181599 or - out_sfd__h182327 or _theResult___sfd__h182324) - begin - case (guard__h173663) - 2'b0, 2'b01: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - _theResult___snd__h181599[56:5]; - 2'b10: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - out_sfd__h182327; - 2'b11: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - _theResult___sfd__h182324; - endcase - end - always@(guard__h173663 or - _theResult___snd__h181599 or _theResult___sfd__h182324) - begin - case (guard__h173663) - 2'b0: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 = - _theResult___snd__h181599[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 = - _theResult___sfd__h182324; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 or - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 or - _theResult___snd__h181599) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h182402 = - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52; - 3'd1: - _theResult___fst_sfd__h182402 = - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53; - 3'd2: - _theResult___fst_sfd__h182402 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832; - 3'd3: - _theResult___fst_sfd__h182402 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834; - 3'd4: _theResult___fst_sfd__h182402 = _theResult___snd__h181599[56:5]; - default: _theResult___fst_sfd__h182402 = 52'd0; - endcase - end - always@(guard__h155375 or iFifo$D_OUT) - begin - case (guard__h155375) - 2'b0, 2'b01, 2'b10: - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 = - guard__h155375 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 or - guard__h155375) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - (guard__h155375 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h155375 == 2'b01 || guard__h155375 == 2'b10 || - guard__h155375 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 = - iFifo$D_OUT[168]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h164624 or iFifo$D_OUT) - begin - case (guard__h164624) - 2'b0, 2'b01, 2'b10: - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 = - guard__h164624 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 or - guard__h164624) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - (guard__h164624 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h164624 == 2'b01 || guard__h164624 == 2'b10 || - guard__h164624 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h173663 or iFifo$D_OUT) - begin - case (guard__h173663) - 2'b0, 2'b01, 2'b10: - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 = - guard__h173663 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 or - guard__h173663) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - (guard__h173663 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h173663 == 2'b01 || guard__h173663 == 2'b10 || - guard__h173663 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h232952 or - _theResult___fst_exp__h240913 or - out_exp__h241561 or _theResult___exp__h241558) - begin - case (guard__h232952) - 2'b0, 2'b01: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - _theResult___fst_exp__h240913; - 2'b10: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - out_exp__h241561; - 2'b11: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - _theResult___exp__h241558; - endcase - end - always@(guard__h232952 or - _theResult___fst_exp__h240913 or _theResult___exp__h241558) - begin - case (guard__h232952) - 2'b0: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 = - _theResult___fst_exp__h240913; - 2'b01, 2'b10, 2'b11: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 = - _theResult___exp__h241558; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 or - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 or - _theResult___fst_exp__h240913) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h241636 = - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69; - 3'd1: - _theResult___fst_exp__h241636 = - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70; - 3'd2: - _theResult___fst_exp__h241636 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398; - 3'd3: - _theResult___fst_exp__h241636 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400; - 3'd4: _theResult___fst_exp__h241636 = _theResult___fst_exp__h240913; - default: _theResult___fst_exp__h241636 = 11'd0; - endcase - end - always@(guard__h242201 or - _theResult___fst_exp__h250429 or - out_exp__h251151 or _theResult___exp__h251148) - begin - case (guard__h242201) - 2'b0, 2'b01: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - _theResult___fst_exp__h250429; - 2'b10: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - out_exp__h251151; - 2'b11: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - _theResult___exp__h251148; - endcase - end - always@(guard__h242201 or - _theResult___fst_exp__h250429 or _theResult___exp__h251148) - begin - case (guard__h242201) - 2'b0: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 = - _theResult___fst_exp__h250429; - 2'b01, 2'b10, 2'b11: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 = - _theResult___exp__h251148; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 or - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 or - _theResult___fst_exp__h250429) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h251226 = - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71; - 3'd1: - _theResult___fst_exp__h251226 = - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72; - 3'd2: - _theResult___fst_exp__h251226 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436; - 3'd3: - _theResult___fst_exp__h251226 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438; - 3'd4: _theResult___fst_exp__h251226 = _theResult___fst_exp__h250429; - default: _theResult___fst_exp__h251226 = 11'd0; - endcase - end - always@(guard__h251240 or - _theResult___fst_exp__h259230 or - out_exp__h259903 or _theResult___exp__h259900) - begin - case (guard__h251240) - 2'b0, 2'b01: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - _theResult___fst_exp__h259230; - 2'b10: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - out_exp__h259903; - 2'b11: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - _theResult___exp__h259900; - endcase - end - always@(guard__h251240 or - _theResult___fst_exp__h259230 or _theResult___exp__h259900) - begin - case (guard__h251240) - 2'b0: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 = - _theResult___fst_exp__h259230; - 2'b01, 2'b10, 2'b11: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 = - _theResult___exp__h259900; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 or - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 or - _theResult___fst_exp__h259230) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h259978 = - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73; - 3'd1: - _theResult___fst_exp__h259978 = - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74; - 3'd2: - _theResult___fst_exp__h259978 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467; - 3'd3: - _theResult___fst_exp__h259978 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469; - 3'd4: _theResult___fst_exp__h259978 = _theResult___fst_exp__h259230; - default: _theResult___fst_exp__h259978 = 11'd0; - endcase - end - always@(guard__h232952 or - _theResult___snd__h240864 or - out_sfd__h241562 or _theResult___sfd__h241559) - begin - case (guard__h232952) - 2'b0, 2'b01: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - _theResult___snd__h240864[56:5]; - 2'b10: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - out_sfd__h241562; - 2'b11: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - _theResult___sfd__h241559; - endcase - end - always@(guard__h232952 or - _theResult___snd__h240864 or _theResult___sfd__h241559) - begin - case (guard__h232952) - 2'b0: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 = - _theResult___snd__h240864[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 = - _theResult___sfd__h241559; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 or - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 or - _theResult___snd__h240864) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h241637 = - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75; - 3'd1: - _theResult___fst_sfd__h241637 = - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76; - 3'd2: - _theResult___fst_sfd__h241637 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493; - 3'd3: - _theResult___fst_sfd__h241637 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495; - 3'd4: _theResult___fst_sfd__h241637 = _theResult___snd__h240864[56:5]; - default: _theResult___fst_sfd__h241637 = 52'd0; - endcase - end - always@(guard__h242201 or - sfdin__h250423 or out_sfd__h251152 or _theResult___sfd__h251149) - begin - case (guard__h242201) - 2'b0, 2'b01: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - sfdin__h250423[56:5]; - 2'b10: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - out_sfd__h251152; - 2'b11: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - _theResult___sfd__h251149; - endcase - end - always@(guard__h242201 or sfdin__h250423 or _theResult___sfd__h251149) - begin - case (guard__h242201) - 2'b0: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 = - sfdin__h250423[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 = - _theResult___sfd__h251149; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 or - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 or - sfdin__h250423) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h251227 = - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77; - 3'd1: - _theResult___fst_sfd__h251227 = - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78; - 3'd2: - _theResult___fst_sfd__h251227 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519; - 3'd3: - _theResult___fst_sfd__h251227 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521; - 3'd4: _theResult___fst_sfd__h251227 = sfdin__h250423[56:5]; - default: _theResult___fst_sfd__h251227 = 52'd0; - endcase - end - always@(guard__h251240 or - _theResult___snd__h259176 or - out_sfd__h259904 or _theResult___sfd__h259901) - begin - case (guard__h251240) - 2'b0, 2'b01: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - _theResult___snd__h259176[56:5]; - 2'b10: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - out_sfd__h259904; - 2'b11: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - _theResult___sfd__h259901; - endcase - end - always@(guard__h251240 or - _theResult___snd__h259176 or _theResult___sfd__h259901) - begin - case (guard__h251240) - 2'b0: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 = - _theResult___snd__h259176[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 = - _theResult___sfd__h259901; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 or - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 or - _theResult___snd__h259176) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h259979 = - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79; - 3'd1: - _theResult___fst_sfd__h259979 = - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80; - 3'd2: - _theResult___fst_sfd__h259979 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538; - 3'd3: - _theResult___fst_sfd__h259979 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540; - 3'd4: _theResult___fst_sfd__h259979 = _theResult___snd__h259176[56:5]; - default: _theResult___fst_sfd__h259979 = 52'd0; - endcase - end - always@(guard__h232952 or iFifo$D_OUT) - begin - case (guard__h232952) - 2'b0, 2'b01, 2'b10: - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 = - guard__h232952 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 or - guard__h232952) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - (guard__h232952 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h232952 == 2'b01 || guard__h232952 == 2'b10 || - guard__h232952 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 = - iFifo$D_OUT[38]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h242201 or iFifo$D_OUT) - begin - case (guard__h242201) - 2'b0, 2'b01, 2'b10: - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 = - guard__h242201 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 or - guard__h242201) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - (guard__h242201 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h242201 == 2'b01 || guard__h242201 == 2'b10 || - guard__h242201 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h251240 or iFifo$D_OUT) - begin - case (guard__h251240) - 2'b0, 2'b01, 2'b10: - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 = - guard__h251240 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 or - guard__h251240) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - (guard__h251240 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h251240 == 2'b01 || guard__h251240 == 2'b10 || - guard__h251240 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h232952 or iFifo$D_OUT) - begin - case (guard__h232952) - 2'b0, 2'b01, 2'b10: - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 = - guard__h232952 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 or - guard__h232952) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - (guard__h232952 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h232952 != 2'b01 && guard__h232952 != 2'b10 && - guard__h232952 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h242201 or iFifo$D_OUT) - begin - case (guard__h242201) - 2'b0, 2'b01, 2'b10: - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 = - guard__h242201 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 or - guard__h242201) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - (guard__h242201 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h242201 != 2'b01 && guard__h242201 != 2'b10 && - guard__h242201 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h251240 or iFifo$D_OUT) - begin - case (guard__h251240) - 2'b0, 2'b01, 2'b10: - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 = - guard__h251240 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 or - guard__h251240) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - (guard__h251240 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h251240 != 2'b01 && guard__h251240 != 2'b10 && - guard__h251240 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 = - !iFifo$D_OUT[38]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h194013 or - _theResult___fst_exp__h201974 or - out_exp__h202622 or _theResult___exp__h202619) - begin - case (guard__h194013) - 2'b0, 2'b01: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - _theResult___fst_exp__h201974; - 2'b10: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - out_exp__h202622; - 2'b11: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - _theResult___exp__h202619; - endcase - end - always@(guard__h194013 or - _theResult___fst_exp__h201974 or _theResult___exp__h202619) - begin - case (guard__h194013) - 2'b0: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 = - _theResult___fst_exp__h201974; - 2'b01, 2'b10, 2'b11: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 = - _theResult___exp__h202619; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 or - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 or - _theResult___fst_exp__h201974) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h202697 = - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102; - 3'd1: - _theResult___fst_exp__h202697 = - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103; - 3'd2: - _theResult___fst_exp__h202697 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173; - 3'd3: - _theResult___fst_exp__h202697 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175; - 3'd4: _theResult___fst_exp__h202697 = _theResult___fst_exp__h201974; - default: _theResult___fst_exp__h202697 = 11'd0; - endcase - end - always@(guard__h203262 or - _theResult___fst_exp__h211490 or - out_exp__h212212 or _theResult___exp__h212209) - begin - case (guard__h203262) - 2'b0, 2'b01: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - _theResult___fst_exp__h211490; - 2'b10: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - out_exp__h212212; - 2'b11: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - _theResult___exp__h212209; - endcase - end - always@(guard__h203262 or - _theResult___fst_exp__h211490 or _theResult___exp__h212209) - begin - case (guard__h203262) - 2'b0: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 = - _theResult___fst_exp__h211490; - 2'b01, 2'b10, 2'b11: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 = - _theResult___exp__h212209; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 or - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 or - _theResult___fst_exp__h211490) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h212287 = - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104; - 3'd1: - _theResult___fst_exp__h212287 = - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105; - 3'd2: - _theResult___fst_exp__h212287 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211; - 3'd3: - _theResult___fst_exp__h212287 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213; - 3'd4: _theResult___fst_exp__h212287 = _theResult___fst_exp__h211490; - default: _theResult___fst_exp__h212287 = 11'd0; - endcase - end - always@(guard__h212301 or - _theResult___fst_exp__h220291 or - out_exp__h220964 or _theResult___exp__h220961) - begin - case (guard__h212301) - 2'b0, 2'b01: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - _theResult___fst_exp__h220291; - 2'b10: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - out_exp__h220964; - 2'b11: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - _theResult___exp__h220961; - endcase - end - always@(guard__h212301 or - _theResult___fst_exp__h220291 or _theResult___exp__h220961) - begin - case (guard__h212301) - 2'b0: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 = - _theResult___fst_exp__h220291; - 2'b01, 2'b10, 2'b11: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 = - _theResult___exp__h220961; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 or - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 or - _theResult___fst_exp__h220291) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h221039 = - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106; - 3'd1: - _theResult___fst_exp__h221039 = - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107; - 3'd2: - _theResult___fst_exp__h221039 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242; - 3'd3: - _theResult___fst_exp__h221039 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244; - 3'd4: _theResult___fst_exp__h221039 = _theResult___fst_exp__h220291; - default: _theResult___fst_exp__h221039 = 11'd0; - endcase - end - always@(guard__h194013 or - _theResult___snd__h201925 or - out_sfd__h202623 or _theResult___sfd__h202620) - begin - case (guard__h194013) - 2'b0, 2'b01: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - _theResult___snd__h201925[56:5]; - 2'b10: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - out_sfd__h202623; - 2'b11: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - _theResult___sfd__h202620; - endcase - end - always@(guard__h194013 or - _theResult___snd__h201925 or _theResult___sfd__h202620) - begin - case (guard__h194013) - 2'b0: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 = - _theResult___snd__h201925[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 = - _theResult___sfd__h202620; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 or - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 or - _theResult___snd__h201925) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h202698 = - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108; - 3'd1: - _theResult___fst_sfd__h202698 = - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109; - 3'd2: - _theResult___fst_sfd__h202698 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268; - 3'd3: - _theResult___fst_sfd__h202698 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270; - 3'd4: _theResult___fst_sfd__h202698 = _theResult___snd__h201925[56:5]; - default: _theResult___fst_sfd__h202698 = 52'd0; - endcase - end - always@(guard__h203262 or - sfdin__h211484 or out_sfd__h212213 or _theResult___sfd__h212210) - begin - case (guard__h203262) - 2'b0, 2'b01: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - sfdin__h211484[56:5]; - 2'b10: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - out_sfd__h212213; - 2'b11: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - _theResult___sfd__h212210; - endcase - end - always@(guard__h203262 or sfdin__h211484 or _theResult___sfd__h212210) - begin - case (guard__h203262) - 2'b0: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 = - sfdin__h211484[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 = - _theResult___sfd__h212210; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 or - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 or - sfdin__h211484) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h212288 = - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110; - 3'd1: - _theResult___fst_sfd__h212288 = - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111; - 3'd2: - _theResult___fst_sfd__h212288 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294; - 3'd3: - _theResult___fst_sfd__h212288 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296; - 3'd4: _theResult___fst_sfd__h212288 = sfdin__h211484[56:5]; - default: _theResult___fst_sfd__h212288 = 52'd0; - endcase - end - always@(guard__h212301 or - _theResult___snd__h220237 or - out_sfd__h220965 or _theResult___sfd__h220962) - begin - case (guard__h212301) - 2'b0, 2'b01: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - _theResult___snd__h220237[56:5]; - 2'b10: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - out_sfd__h220965; - 2'b11: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - _theResult___sfd__h220962; - endcase - end - always@(guard__h212301 or - _theResult___snd__h220237 or _theResult___sfd__h220962) - begin - case (guard__h212301) - 2'b0: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 = - _theResult___snd__h220237[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 = - _theResult___sfd__h220962; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 or - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 or - _theResult___snd__h220237) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h221040 = - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112; - 3'd1: - _theResult___fst_sfd__h221040 = - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113; - 3'd2: - _theResult___fst_sfd__h221040 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313; - 3'd3: - _theResult___fst_sfd__h221040 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315; - 3'd4: _theResult___fst_sfd__h221040 = _theResult___snd__h220237[56:5]; - default: _theResult___fst_sfd__h221040 = 52'd0; - endcase - end - always@(guard__h194013 or iFifo$D_OUT) - begin - case (guard__h194013) - 2'b0, 2'b01, 2'b10: - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 = - guard__h194013 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 or - guard__h194013) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - (guard__h194013 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h194013 == 2'b01 || guard__h194013 == 2'b10 || - guard__h194013 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 = - iFifo$D_OUT[103]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h203262 or iFifo$D_OUT) - begin - case (guard__h203262) - 2'b0, 2'b01, 2'b10: - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 = - guard__h203262 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 or - guard__h203262) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - (guard__h203262 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h203262 == 2'b01 || guard__h203262 == 2'b10 || - guard__h203262 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h212301 or iFifo$D_OUT) - begin - case (guard__h212301) - 2'b0, 2'b01, 2'b10: - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 = - guard__h212301 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 or - guard__h212301) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - (guard__h212301 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h212301 == 2'b01 || guard__h212301 == 2'b10 || - guard__h212301 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h194013 or iFifo$D_OUT) - begin - case (guard__h194013) - 2'b0, 2'b01, 2'b10: - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 = - guard__h194013 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 or - guard__h194013) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - (guard__h194013 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h194013 != 2'b01 && guard__h194013 != 2'b10 && - guard__h194013 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 = - !iFifo$D_OUT[103]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(guard__h203262 or iFifo$D_OUT) - begin - case (guard__h203262) - 2'b0, 2'b01, 2'b10: - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 = - guard__h203262 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 or - guard__h203262) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - (guard__h203262 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h203262 != 2'b01 && guard__h203262 != 2'b10 && - guard__h203262 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(guard__h212301 or iFifo$D_OUT) - begin - case (guard__h212301) - 2'b0, 2'b01, 2'b10: - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 = - guard__h212301 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 or - guard__h212301) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - (guard__h212301 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h212301 != 2'b01 && guard__h212301 != 2'b10 && - guard__h212301 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(fpu_madd_fState_S8$D_OUT) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 = - fpu_madd_fState_S8$D_OUT[66]; - 2'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 = - fpu_madd_fState_S8$D_OUT[2:1] == 2'b11 && - fpu_madd_fState_S8$D_OUT[66]; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126; - 3'd1: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[66] : - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b01 || - fpu_madd_fState_S8$D_OUT[2:1] == 2'b10 || - fpu_madd_fState_S8$D_OUT[2:1] == 2'b11) && - fpu_madd_fState_S8$D_OUT[66]; - 3'd2, 3'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - fpu_madd_fState_S8$D_OUT[66]; - default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - fpu_madd_fState_S8$D_OUT[70:68] == 3'd4 && - fpu_madd_fState_S8$D_OUT[66]; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 or - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848; - 4'd5, 4'd7: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555; - 4'd6: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618; - default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - fpu_madd_fState_S8$D_OUT[3] ? - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 : - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 = - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 = - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130; - 3'd1: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131; - 3'd2: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[65:3] : - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - 3'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[65:3] : - (fpu_madd_fState_S8$D_OUT[66] ? - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 : - fpu_madd_fState_S8$D_OUT[65:3]); - 3'd4: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - fpu_madd_fState_S8$D_OUT[65:3]; - default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - 63'd0; - endcase - end - always@(iFifo$D_OUT or - fpu_madd_fOperand_S0$FULL_N or - fpu_div64_fOperands_S0$FULL_N or fpu_sqr64_fOperand_S0$FULL_N) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1, 4'd2, 4'd5, 4'd6, 4'd7: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_madd_fOperand_S0$FULL_N; - 4'd3: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_div64_fOperands_S0$FULL_N; - 4'd4: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_sqr64_fOperand_S0$FULL_N; - default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - iFifo$D_OUT[3:0] != 4'd8 || fpu_madd_fOperand_S0$FULL_N; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1: _theResult___fst_exp__h269559 = 8'd255; - 3'd2: - _theResult___fst_exp__h269559 = resWire$wget[68] ? 8'd254 : 8'd255; - 3'd3: - _theResult___fst_exp__h269559 = resWire$wget[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h269559 = 8'd254; - default: _theResult___fst_exp__h269559 = 8'd0; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1: _theResult___fst_sfd__h269560 = 23'd0; - 3'd2: - _theResult___fst_sfd__h269560 = - resWire$wget[68] ? 23'd8388607 : 23'd0; - 3'd3: - _theResult___fst_sfd__h269560 = - resWire$wget[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h269560 = 23'd8388607; - default: _theResult___fst_sfd__h269560 = 23'd0; - endcase - end - always@(guard__h269587 or resWire$wget) - begin - case (guard__h269587) - 2'b0, 2'b01, 2'b10: - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 = - resWire$wget[68]; - 2'd3: - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 = - guard__h269587 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 or - guard__h269587) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - (guard__h269587 == 2'b0) ? - resWire$wget[68] : - (guard__h269587 == 2'b01 || guard__h269587 == 2'b10 || - guard__h269587 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h269587 or resWire$wget) - begin - case (guard__h269587) - 2'b0, 2'b01, 2'b10: - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 = - !resWire$wget[68]; - 2'd3: - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 = - guard__h269587 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 or - guard__h269587) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - (guard__h269587 == 2'b0) ? - !resWire$wget[68] : - guard__h269587 != 2'b01 && guard__h269587 != 2'b10 && - guard__h269587 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h278294 or resWire$wget) - begin - case (guard__h278294) - 2'b0, 2'b01, 2'b10: - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 = - resWire$wget[68]; - 2'd3: - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 = - guard__h278294 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 or - guard__h278294) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - (guard__h278294 == 2'b0) ? - resWire$wget[68] : - (guard__h278294 == 2'b01 || guard__h278294 == 2'b10 || - guard__h278294 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h278294 or resWire$wget) - begin - case (guard__h278294) - 2'b0, 2'b01, 2'b10: - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 = - !resWire$wget[68]; - 2'd3: - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 = - guard__h278294 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 or - guard__h278294) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - (guard__h278294 == 2'b0) ? - !resWire$wget[68] : - guard__h278294 != 2'b01 && guard__h278294 != 2'b10 && - guard__h278294 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h287224 or resWire$wget) - begin - case (guard__h287224) - 2'b0, 2'b01, 2'b10: - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 = - resWire$wget[68]; - 2'd3: - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 = - guard__h287224 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 or - guard__h287224) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - (guard__h287224 == 2'b0) ? - resWire$wget[68] : - (guard__h287224 == 2'b01 || guard__h287224 == 2'b10 || - guard__h287224 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h287224 or resWire$wget) - begin - case (guard__h287224) - 2'b0, 2'b01, 2'b10: - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 = - !resWire$wget[68]; - 2'd3: - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 = - guard__h287224 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 or - guard__h287224) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - (guard__h287224 == 2'b0) ? - !resWire$wget[68] : - guard__h287224 != 2'b01 && guard__h287224 != 2'b10 && - guard__h287224 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h296060 or resWire$wget) - begin - case (guard__h296060) - 2'b0, 2'b01, 2'b10: - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 = - resWire$wget[68]; - 2'd3: - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 = - guard__h296060 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 or - guard__h296060) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - (guard__h296060 == 2'b0) ? - resWire$wget[68] : - (guard__h296060 == 2'b01 || guard__h296060 == 2'b10 || - guard__h296060 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h296060 or resWire$wget) - begin - case (guard__h296060) - 2'b0, 2'b01, 2'b10: - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 = - !resWire$wget[68]; - 2'd3: - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 = - guard__h296060 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 or - guard__h296060) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - (guard__h296060 == 2'b0) ? - !resWire$wget[68] : - guard__h296060 != 2'b01 && guard__h296060 != 2'b10 && - guard__h296060 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h278294 or - _theResult___fst_exp__h286342 or - out_exp__h286787 or _theResult___exp__h286784) - begin - case (guard__h278294) - 2'b0, 2'b01: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - _theResult___fst_exp__h286342; - 2'b10: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - out_exp__h286787; - 2'b11: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - _theResult___exp__h286784; - endcase - end - always@(guard__h278294 or - _theResult___fst_exp__h286342 or _theResult___exp__h286784) - begin - case (guard__h278294) - 2'b0: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 = - _theResult___fst_exp__h286342; - 2'b01, 2'b10, 2'b11: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 = - _theResult___exp__h286784; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 or - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 or - _theResult___fst_exp__h286342) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h286862 = - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152; - 3'd1: - _theResult___fst_exp__h286862 = - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153; - 3'd2: - _theResult___fst_exp__h286862 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479; - 3'd3: - _theResult___fst_exp__h286862 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481; - 3'd4: _theResult___fst_exp__h286862 = _theResult___fst_exp__h286342; - default: _theResult___fst_exp__h286862 = 8'd0; - endcase - end - always@(guard__h269587 or - _theResult___fst_exp__h277686 or - out_exp__h278205 or _theResult___exp__h278202) - begin - case (guard__h269587) - 2'b0, 2'b01: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - _theResult___fst_exp__h277686; - 2'b10: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - out_exp__h278205; - 2'b11: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - _theResult___exp__h278202; - endcase - end - always@(guard__h269587 or - _theResult___fst_exp__h277686 or _theResult___exp__h278202) - begin - case (guard__h269587) - 2'b0: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 = - _theResult___fst_exp__h277686; - 2'b01, 2'b10, 2'b11: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 = - _theResult___exp__h278202; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 or - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 or - _theResult___fst_exp__h277686) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h278280 = - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154; - 3'd1: - _theResult___fst_exp__h278280 = - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155; - 3'd2: - _theResult___fst_exp__h278280 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448; - 3'd3: - _theResult___fst_exp__h278280 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450; - 3'd4: _theResult___fst_exp__h278280 = _theResult___fst_exp__h277686; - default: _theResult___fst_exp__h278280 = 8'd0; - endcase - end - always@(guard__h287224 or - _theResult___fst_exp__h295452 or - out_exp__h295971 or _theResult___exp__h295968) - begin - case (guard__h287224) - 2'b0, 2'b01: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - _theResult___fst_exp__h295452; - 2'b10: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - out_exp__h295971; - 2'b11: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - _theResult___exp__h295968; - endcase - end - always@(guard__h287224 or - _theResult___fst_exp__h295452 or _theResult___exp__h295968) - begin - case (guard__h287224) - 2'b0: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 = - _theResult___fst_exp__h295452; - 2'b01, 2'b10, 2'b11: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 = - _theResult___exp__h295968; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 or - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 or - _theResult___fst_exp__h295452) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h296046 = - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156; - 3'd1: - _theResult___fst_exp__h296046 = - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157; - 3'd2: - _theResult___fst_exp__h296046 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518; - 3'd3: - _theResult___fst_exp__h296046 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520; - 3'd4: _theResult___fst_exp__h296046 = _theResult___fst_exp__h295452; - default: _theResult___fst_exp__h296046 = 8'd0; - endcase - end - always@(guard__h296060 or - _theResult___fst_exp__h304137 or - out_exp__h304607 or _theResult___exp__h304604) - begin - case (guard__h296060) - 2'b0, 2'b01: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - _theResult___fst_exp__h304137; - 2'b10: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - out_exp__h304607; - 2'b11: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - _theResult___exp__h304604; - endcase - end - always@(guard__h296060 or - _theResult___fst_exp__h304137 or _theResult___exp__h304604) - begin - case (guard__h296060) - 2'b0: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 = - _theResult___fst_exp__h304137; - 2'b01, 2'b10, 2'b11: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 = - _theResult___exp__h304604; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 or - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 or - _theResult___fst_exp__h304137) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h304682 = - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158; - 3'd1: - _theResult___fst_exp__h304682 = - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159; - 3'd2: - _theResult___fst_exp__h304682 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549; - 3'd3: - _theResult___fst_exp__h304682 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551; - 3'd4: _theResult___fst_exp__h304682 = _theResult___fst_exp__h304137; - default: _theResult___fst_exp__h304682 = 8'd0; - endcase - end - always@(guard__h278294 or - _theResult___snd__h286293 or - out_sfd__h286788 or _theResult___sfd__h286785) - begin - case (guard__h278294) - 2'b0, 2'b01: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - _theResult___snd__h286293[56:34]; - 2'b10: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - out_sfd__h286788; - 2'b11: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - _theResult___sfd__h286785; - endcase - end - always@(guard__h278294 or - _theResult___snd__h286293 or _theResult___sfd__h286785) - begin - case (guard__h278294) - 2'b0: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 = - _theResult___snd__h286293[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 = - _theResult___sfd__h286785; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 or - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 or - _theResult___snd__h286293) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h286863 = - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160; - 3'd1: - _theResult___fst_sfd__h286863 = - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161; - 3'd2: - _theResult___fst_sfd__h286863 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595; - 3'd3: - _theResult___fst_sfd__h286863 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597; - 3'd4: _theResult___fst_sfd__h286863 = _theResult___snd__h286293[56:34]; - default: _theResult___fst_sfd__h286863 = 23'd0; - endcase - end - always@(guard__h269587 or - sfdin__h277680 or out_sfd__h278206 or _theResult___sfd__h278203) - begin - case (guard__h269587) - 2'b0, 2'b01: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - sfdin__h277680[56:34]; - 2'b10: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - out_sfd__h278206; - 2'b11: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - _theResult___sfd__h278203; - endcase - end - always@(guard__h269587 or sfdin__h277680 or _theResult___sfd__h278203) - begin - case (guard__h269587) - 2'b0: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 = - sfdin__h277680[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 = - _theResult___sfd__h278203; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 or - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 or - sfdin__h277680) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h278281 = - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162; - 3'd1: - _theResult___fst_sfd__h278281 = - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163; - 3'd2: - _theResult___fst_sfd__h278281 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576; - 3'd3: - _theResult___fst_sfd__h278281 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578; - 3'd4: _theResult___fst_sfd__h278281 = sfdin__h277680[56:34]; - default: _theResult___fst_sfd__h278281 = 23'd0; - endcase - end - always@(guard__h287224 or - sfdin__h295446 or out_sfd__h295972 or _theResult___sfd__h295969) - begin - case (guard__h287224) - 2'b0, 2'b01: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - sfdin__h295446[56:34]; - 2'b10: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - out_sfd__h295972; - 2'b11: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - _theResult___sfd__h295969; - endcase - end - always@(guard__h287224 or sfdin__h295446 or _theResult___sfd__h295969) - begin - case (guard__h287224) - 2'b0: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 = - sfdin__h295446[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 = - _theResult___sfd__h295969; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 or - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 or - sfdin__h295446) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h296047 = - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164; - 3'd1: - _theResult___fst_sfd__h296047 = - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165; - 3'd2: - _theResult___fst_sfd__h296047 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622; - 3'd3: - _theResult___fst_sfd__h296047 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624; - 3'd4: _theResult___fst_sfd__h296047 = sfdin__h295446[56:34]; - default: _theResult___fst_sfd__h296047 = 23'd0; - endcase - end - always@(guard__h296060 or - _theResult___snd__h304083 or - out_sfd__h304608 or _theResult___sfd__h304605) - begin - case (guard__h296060) - 2'b0, 2'b01: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - _theResult___snd__h304083[56:34]; - 2'b10: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - out_sfd__h304608; - 2'b11: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - _theResult___sfd__h304605; - endcase - end - always@(guard__h296060 or - _theResult___snd__h304083 or _theResult___sfd__h304605) - begin - case (guard__h296060) - 2'b0: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 = - _theResult___snd__h304083[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 = - _theResult___sfd__h304605; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 or - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 or - _theResult___snd__h304083) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h304683 = - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166; - 3'd1: - _theResult___fst_sfd__h304683 = - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167; - 3'd2: - _theResult___fst_sfd__h304683 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641; - 3'd3: - _theResult___fst_sfd__h304683 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643; - 3'd4: _theResult___fst_sfd__h304683 = _theResult___snd__h304083[56:34]; - default: _theResult___fst_sfd__h304683 = 23'd0; - endcase - end - always@(fpu_div64_fState_S4$D_OUT) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 = - fpu_div64_fState_S4$D_OUT[65]; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 = - fpu_div64_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_div64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - 3'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[64:2] : - (fpu_div64_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 : - fpu_div64_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - fpu_div64_fState_S4$D_OUT[64:2]; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - 63'd0; - endcase - end - always@(fpu_div64_fState_S4$D_OUT) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 = - fpu_div64_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 = - fpu_div64_fState_S4$D_OUT[1:0] == 2'b11 && - fpu_div64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - fpu_div64_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - fpu_div64_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 : - fpu_div64_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 = - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 or - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - { CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 }; - 3'd1: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[65:2] : - { (fpu_div64_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_div64_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_div64_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_div64_fState_S4$D_OUT[65], - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 }; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - { CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 }; - endcase - end - always@(fpu_div64_fState_S3$D_OUT) - begin - case (fpu_div64_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174 = - fpu_div64_fState_S3$D_OUT[121]; - default: CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174 = - fpu_div64_fState_S3$D_OUT[124:122] == 3'd4 && - fpu_div64_fState_S3$D_OUT[121]; - endcase - end - always@(fpu_div64_fState_S3$D_OUT) - begin - case (fpu_div64_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'h7FF0000000000000; - 3'd2: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - fpu_div64_fState_S3$D_OUT[121] ? - 63'h7FEFFFFFFFFFFFFF : - 63'h7FF0000000000000; - 3'd3: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - fpu_div64_fState_S3$D_OUT[121] ? - 63'h7FF0000000000000 : - 63'h7FEFFFFFFFFFFFFF; - 3'd4: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'h7FEFFFFFFFFFFFFF; - default: CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'd0; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 or - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378) - begin - case (iFifo$D_OUT[3:0]) - 4'd0: - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330; - 4'd1: - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - iFifo$D_OUT[136] ? - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 : - { iFifo$D_OUT[136] || !iFifo$D_OUT[135], - iFifo$D_OUT[134:72] }; - default: CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1: - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 = - 64'h3FF0000000000000; - default: CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 = - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 = - fpu_sqr64_fState_S4$D_OUT[65]; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 = - fpu_sqr64_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_sqr64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - 3'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[64:2] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 : - fpu_sqr64_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - fpu_sqr64_fState_S4$D_OUT[64:2]; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - 63'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 = - fpu_sqr64_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 = - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b11 && - fpu_sqr64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - fpu_sqr64_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - fpu_sqr64_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 : - fpu_sqr64_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 = - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - { CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 }; - 3'd1: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[65:2] : - { (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_sqr64_fState_S4$D_OUT[65], - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 }; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - { CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - crg_done <= `BSV_ASSIGNMENT_DELAY 1'd0; - crg_done_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (crg_done$EN) crg_done <= `BSV_ASSIGNMENT_DELAY crg_done$D_IN; - if (crg_done_1$EN) - crg_done_1 <= `BSV_ASSIGNMENT_DELAY crg_done_1$D_IN; - if (rg_busy$EN) rg_busy <= `BSV_ASSIGNMENT_DELAY rg_busy$D_IN; - if (rg_busy_1$EN) rg_busy_1 <= `BSV_ASSIGNMENT_DELAY rg_busy_1$D_IN; - end - if (rg_b$EN) rg_b <= `BSV_ASSIGNMENT_DELAY rg_b$D_IN; - if (rg_d$EN) rg_d <= `BSV_ASSIGNMENT_DELAY rg_d$D_IN; - if (rg_index$EN) rg_index <= `BSV_ASSIGNMENT_DELAY rg_index$D_IN; - if (rg_index_1$EN) rg_index_1 <= `BSV_ASSIGNMENT_DELAY rg_index_1$D_IN; - if (rg_q$EN) rg_q <= `BSV_ASSIGNMENT_DELAY rg_q$D_IN; - if (rg_r$EN) rg_r <= `BSV_ASSIGNMENT_DELAY rg_r$D_IN; - if (rg_r_1$EN) rg_r_1 <= `BSV_ASSIGNMENT_DELAY rg_r_1$D_IN; - if (rg_res$EN) rg_res <= `BSV_ASSIGNMENT_DELAY rg_res$D_IN; - if (rg_s$EN) rg_s <= `BSV_ASSIGNMENT_DELAY rg_s$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - crg_done = 1'h0; - crg_done_1 = 1'h0; - rg_b = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_busy = 1'h0; - rg_busy_1 = 1'h0; - rg_d = 58'h2AAAAAAAAAAAAAA; - rg_index = 6'h2A; - rg_index_1 = 6'h2A; - rg_q = 58'h2AAAAAAAAAAAAAA; - rg_r = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_r_1 = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_res = 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_s = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (fpu_div64_fResult_S5$EMPTY_N && fpu_madd_fResult_S9$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 29: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResDiv] and\n [RL_getResMAdd] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fpu_div64_fResult_S5$EMPTY_N && fpu_sqr64_fResult_S5$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 29: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResDiv] and [RL_getResSqr]\n ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fpu_sqr64_fResult_S5$EMPTY_N && fpu_madd_fResult_S9$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 40: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResSqr] and\n [RL_getResMAdd] ) fired in the same clock cycle.\n"); - end - // synopsys translate_on -endmodule // mkFPU - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric.v deleted file mode 100644 index 771fc0dc..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric.v +++ /dev/null @@ -1,8149 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 = - fabric_cfg_verbosity > 4'd1 ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - $display("%0d: %m::AXI4_Fabric.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v deleted file mode 100644 index 8c7d9af3..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v +++ /dev/null @@ -1,7465 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_2x3(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8650; - reg [31 : 0] v__h9025; - reg [31 : 0] v__h9400; - reg [31 : 0] v__h9845; - reg [31 : 0] v__h10214; - reg [31 : 0] v__h10583; - reg [31 : 0] v__h11872; - reg [31 : 0] v__h12325; - reg [31 : 0] v__h12702; - reg [31 : 0] v__h12994; - reg [31 : 0] v__h13286; - reg [31 : 0] v__h13589; - reg [31 : 0] v__h13855; - reg [31 : 0] v__h14121; - reg [31 : 0] v__h14385; - reg [31 : 0] v__h14611; - reg [31 : 0] v__h15040; - reg [31 : 0] v__h15396; - reg [31 : 0] v__h15752; - reg [31 : 0] v__h16169; - reg [31 : 0] v__h16501; - reg [31 : 0] v__h16833; - reg [31 : 0] v__h17849; - reg [31 : 0] v__h18100; - reg [31 : 0] v__h18475; - reg [31 : 0] v__h18716; - reg [31 : 0] v__h19091; - reg [31 : 0] v__h19332; - reg [31 : 0] v__h19694; - reg [31 : 0] v__h19945; - reg [31 : 0] v__h20275; - reg [31 : 0] v__h20516; - reg [31 : 0] v__h20846; - reg [31 : 0] v__h21087; - reg [31 : 0] v__h21600; - reg [31 : 0] v__h22001; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8644; - reg [31 : 0] v__h9019; - reg [31 : 0] v__h9394; - reg [31 : 0] v__h9839; - reg [31 : 0] v__h10208; - reg [31 : 0] v__h10577; - reg [31 : 0] v__h11866; - reg [31 : 0] v__h12319; - reg [31 : 0] v__h12696; - reg [31 : 0] v__h12988; - reg [31 : 0] v__h13280; - reg [31 : 0] v__h13583; - reg [31 : 0] v__h13849; - reg [31 : 0] v__h14115; - reg [31 : 0] v__h14379; - reg [31 : 0] v__h14605; - reg [31 : 0] v__h15034; - reg [31 : 0] v__h15390; - reg [31 : 0] v__h15746; - reg [31 : 0] v__h16163; - reg [31 : 0] v__h16495; - reg [31 : 0] v__h16827; - reg [31 : 0] v__h17843; - reg [31 : 0] v__h18094; - reg [31 : 0] v__h18469; - reg [31 : 0] v__h18710; - reg [31 : 0] v__h19085; - reg [31 : 0] v__h19326; - reg [31 : 0] v__h19688; - reg [31 : 0] v__h19939; - reg [31 : 0] v__h20269; - reg [31 : 0] v__h20510; - reg [31 : 0] v__h20840; - reg [31 : 0] v__h21081; - reg [31 : 0] v__h21594; - reg [31 : 0] v__h21995; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11777, - x__h12230, - x__h17986, - x__h18612, - x__h19228, - x__h21532, - x__h21933; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - x1_avValue_rresp__h17964, - x1_avValue_rresp__h18590, - x1_avValue_rresp__h19206; - wire _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156, - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371, - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411, - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540, - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - 8'd0 : - x__h17986 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - 8'd0 : - x__h18612 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - 8'd0 : - x__h19228 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? - 8'd0 : - x__h11777 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ? - 8'd0 : - x__h12230 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ? - 8'd0 : - x__h21532 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ? - 8'd0 : - x__h21933 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - x1_avValue_rresp__h17964 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - x1_avValue_rresp__h18590 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - x1_avValue_rresp__h19206 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h17964 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18590 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19206 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11777 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12230 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h17986 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h18612 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19228 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21532 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h21933 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8650 = $stime; - #0; - end - v__h8644 = v__h8650 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8644, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9025 = $stime; - #0; - end - v__h9019 = v__h9025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9019, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9400 = $stime; - #0; - end - v__h9394 = v__h9400 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9394, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9845 = $stime; - #0; - end - v__h9839 = v__h9845 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9839, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10214 = $stime; - #0; - end - v__h10208 = v__h10214 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10208, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10583 = $stime; - #0; - end - v__h10577 = v__h10583 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10577, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h11872 = $stime; - #0; - end - v__h11866 = v__h11872 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h11866, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12325 = $stime; - #0; - end - v__h12319 = v__h12325 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12319, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12702 = $stime; - #0; - end - v__h12696 = v__h12702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12696, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h12994 = $stime; - #0; - end - v__h12988 = v__h12994 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12988, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13286 = $stime; - #0; - end - v__h13280 = v__h13286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13280, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13589 = $stime; - #0; - end - v__h13583 = v__h13589 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13583, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13855 = $stime; - #0; - end - v__h13849 = v__h13855 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13849, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14121 = $stime; - #0; - end - v__h14115 = v__h14121 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14115, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14385 = $stime; - #0; - end - v__h14379 = v__h14385 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14379, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14611 = $stime; - #0; - end - v__h14605 = v__h14611 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14605, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15040 = $stime; - #0; - end - v__h15034 = v__h15040 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15034, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15396 = $stime; - #0; - end - v__h15390 = v__h15396 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15390, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15752 = $stime; - #0; - end - v__h15746 = v__h15752 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15746, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16169 = $stime; - #0; - end - v__h16163 = v__h16169 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16163, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16501 = $stime; - #0; - end - v__h16495 = v__h16501 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16495, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16833 = $stime; - #0; - end - v__h16827 = v__h16833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16827, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h17849 = $stime; - #0; - end - v__h17843 = v__h17849 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h17843, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18100 = $stime; - #0; - end - v__h18094 = v__h18100 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18094, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18475 = $stime; - #0; - end - v__h18469 = v__h18475 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18469, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h18716 = $stime; - #0; - end - v__h18710 = v__h18716 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18710, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19091 = $stime; - #0; - end - v__h19085 = v__h19091 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19085, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19332 = $stime; - #0; - end - v__h19326 = v__h19332 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19326, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h19694 = $stime; - #0; - end - v__h19688 = v__h19694 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19688, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19945 = $stime; - #0; - end - v__h19939 = v__h19945 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19939, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20275 = $stime; - #0; - end - v__h20269 = v__h20275 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20269, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20516 = $stime; - #0; - end - v__h20510 = v__h20516 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20510, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h20846 = $stime; - #0; - end - v__h20840 = v__h20846 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20840, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21087 = $stime; - #0; - end - v__h21081 = v__h21087 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21081, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21600 = $stime; - #0; - end - v__h21594 = v__h21600 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21594, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22001 = $stime; - #0; - end - v__h21995 = v__h22001 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21995, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_2x3 - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v deleted file mode 100644 index ac19188b..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v +++ /dev/null @@ -1,8145 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_AXI4(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_AXI4 - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v deleted file mode 100644 index 5d5bbfb6..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v +++ /dev/null @@ -1,249 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 64 -// read_rs1_port2 O 64 -// read_rs2 O 64 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// Combinational paths from inputs to outputs: -// read_rs1_rs1 -> read_rs1 -// read_rs1_port2_rs1 -> read_rs1_port2 -// read_rs2_rs2 -> read_rs2 -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkGPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [63 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [63 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [63 : 0] read_rs2; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [63 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [63 : 0] read_rs1, read_rs1_port2, read_rs2; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [63 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_3 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = - (read_rs1_port2_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_2 ; - - // value method read_rs2 - assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 64'd0 : regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd64), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs2_rs2 ; - assign regfile$ADDR_2 = read_rs1_port2_rs1 ; - assign regfile$ADDR_3 = read_rs1_rs1 ; - assign regfile$ADDR_4 = 5'h0 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkGPR_RegFile - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v deleted file mode 100644 index f4d13fdd..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 64 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 32 -// put_args_y_is_signed I 1 -// put_args_y I 32 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_32(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [31 : 0] put_args_x; - input put_args_y_is_signed; - input [31 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [63 : 0] result_value; - - // signals for module outputs - wire [63 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [63 : 0] m_rg_x; - wire [63 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [63 : 0] m_rg_xy; - wire [63 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [31 : 0] m_rg_y; - wire [31 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [63 : 0] xy___1__h654; - wire [31 : 0] _theResult___fst__h491, - _theResult___fst__h494, - _theResult___fst__h536, - _theResult___fst__h539, - _theResult___snd_fst__h531; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 32'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h654 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 32'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h491 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h539 : - _theResult___snd_fst__h531 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[31] != put_args_y[31] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 = - put_args_x_is_signed ? - put_args_x[31] : - put_args_y_is_signed && put_args_y[31] ; - assign _theResult___fst__h491 = - put_args_x_is_signed ? _theResult___fst__h494 : put_args_x ; - assign _theResult___fst__h494 = put_args_x[31] ? -put_args_x : put_args_x ; - assign _theResult___fst__h536 = - put_args_y_is_signed ? _theResult___fst__h539 : put_args_y ; - assign _theResult___fst__h539 = put_args_y[31] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h531 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h536 ; - assign xy___1__h654 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 64'hAAAAAAAAAAAAAAAA; - m_rg_xy = 64'hAAAAAAAAAAAAAAAA; - m_rg_y = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_32 - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v deleted file mode 100644 index 0b513191..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 128 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 64 -// put_args_y_is_signed I 1 -// put_args_y I 64 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_64(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [63 : 0] put_args_x; - input put_args_y_is_signed; - input [63 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [127 : 0] result_value; - - // signals for module outputs - wire [127 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [127 : 0] m_rg_x; - wire [127 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [127 : 0] m_rg_xy; - wire [127 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [63 : 0] m_rg_y; - wire [63 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [127 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [127 : 0] xy___1__h648; - wire [63 : 0] _theResult___fst__h488, - _theResult___fst__h491, - _theResult___fst__h533, - _theResult___fst__h536, - _theResult___snd_fst__h528; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 64'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h648 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 64'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h488 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h536 : - _theResult___snd_fst__h528 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[63] != put_args_y[63] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 = - put_args_x_is_signed ? - put_args_x[63] : - put_args_y_is_signed && put_args_y[63] ; - assign _theResult___fst__h488 = - put_args_x_is_signed ? _theResult___fst__h491 : put_args_x ; - assign _theResult___fst__h491 = put_args_x[63] ? -put_args_x : put_args_x ; - assign _theResult___fst__h533 = - put_args_y_is_signed ? _theResult___fst__h536 : put_args_y ; - assign _theResult___fst__h536 = put_args_y[63] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h528 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h533 ; - assign xy___1__h648 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_y = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_64 - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v deleted file mode 100644 index 1a96d7e7..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v +++ /dev/null @@ -1,8179 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// valid O 1 -// addr O 64 reg -// word64 O 64 -// st_amo_val O 64 -// exc O 1 -// exc_code O 4 reg -// RDY_server_flush_request_put O 1 reg -// RDY_server_flush_response_get O 1 -// RDY_tlb_flush O 1 const -// mem_master_awvalid O 1 -// mem_master_awid O 4 reg -// mem_master_awaddr O 64 reg -// mem_master_awlen O 8 reg -// mem_master_awsize O 3 reg -// mem_master_awburst O 2 reg -// mem_master_awlock O 1 reg -// mem_master_awcache O 4 reg -// mem_master_awprot O 3 reg -// mem_master_awqos O 4 reg -// mem_master_awregion O 4 reg -// mem_master_wvalid O 1 -// mem_master_wid O 4 reg -// mem_master_wdata O 64 reg -// mem_master_wstrb O 8 reg -// mem_master_wlast O 1 reg -// mem_master_bready O 1 -// mem_master_arvalid O 1 -// mem_master_arid O 4 reg -// mem_master_araddr O 64 reg -// mem_master_arlen O 8 reg -// mem_master_arsize O 3 reg -// mem_master_arburst O 2 reg -// mem_master_arlock O 1 reg -// mem_master_arcache O 4 reg -// mem_master_arprot O 3 reg -// mem_master_arqos O 4 reg -// mem_master_arregion O 4 reg -// mem_master_rready O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_op I 2 -// req_f3 I 3 -// req_amo_funct7 I 7 reg -// req_addr I 64 -// req_st_value I 64 -// req_priv I 2 reg -// req_sstatus_SUM I 1 reg -// req_mstatus_MXR I 1 reg -// req_satp I 64 reg -// mem_master_awready I 1 -// mem_master_wready I 1 -// mem_master_bvalid I 1 -// mem_master_bid I 4 reg -// mem_master_bresp I 2 reg -// mem_master_arready I 1 -// mem_master_rvalid I 1 -// mem_master_rid I 4 reg -// mem_master_rdata I 64 reg -// mem_master_rresp I 2 reg -// mem_master_rlast I 1 reg -// EN_set_verbosity I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// EN_server_flush_request_put I 1 -// EN_server_flush_response_get I 1 -// EN_tlb_flush I 1 -// -// Combinational paths from inputs to outputs: -// (mem_master_awready, mem_master_wready) -> valid -// (mem_master_awready, mem_master_wready) -> word64 -// (mem_master_awready, mem_master_wready) -> st_amo_val -// (mem_master_awready, mem_master_wready) -> mem_master_bready -// (mem_master_awready, -// mem_master_wready, -// mem_master_arready, -// EN_req) -> mem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMMU_Cache(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_op, - req_f3, - req_amo_funct7, - req_addr, - req_st_value, - req_priv, - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - EN_req, - - valid, - - addr, - - word64, - - st_amo_val, - - exc, - - exc_code, - - EN_server_flush_request_put, - RDY_server_flush_request_put, - - EN_server_flush_response_get, - RDY_server_flush_response_get, - - EN_tlb_flush, - RDY_tlb_flush, - - mem_master_awvalid, - - mem_master_awid, - - mem_master_awaddr, - - mem_master_awlen, - - mem_master_awsize, - - mem_master_awburst, - - mem_master_awlock, - - mem_master_awcache, - - mem_master_awprot, - - mem_master_awqos, - - mem_master_awregion, - - mem_master_awready, - - mem_master_wvalid, - - mem_master_wid, - - mem_master_wdata, - - mem_master_wstrb, - - mem_master_wlast, - - mem_master_wready, - - mem_master_bvalid, - mem_master_bid, - mem_master_bresp, - - mem_master_bready, - - mem_master_arvalid, - - mem_master_arid, - - mem_master_araddr, - - mem_master_arlen, - - mem_master_arsize, - - mem_master_arburst, - - mem_master_arlock, - - mem_master_arcache, - - mem_master_arprot, - - mem_master_arqos, - - mem_master_arregion, - - mem_master_arready, - - mem_master_rvalid, - mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast, - - mem_master_rready); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [1 : 0] req_op; - input [2 : 0] req_f3; - input [6 : 0] req_amo_funct7; - input [63 : 0] req_addr; - input [63 : 0] req_st_value; - input [1 : 0] req_priv; - input req_sstatus_SUM; - input req_mstatus_MXR; - input [63 : 0] req_satp; - input EN_req; - - // value method valid - output valid; - - // value method addr - output [63 : 0] addr; - - // value method word64 - output [63 : 0] word64; - - // value method st_amo_val - output [63 : 0] st_amo_val; - - // value method exc - output exc; - - // value method exc_code - output [3 : 0] exc_code; - - // action method server_flush_request_put - input EN_server_flush_request_put; - output RDY_server_flush_request_put; - - // action method server_flush_response_get - input EN_server_flush_response_get; - output RDY_server_flush_response_get; - - // action method tlb_flush - input EN_tlb_flush; - output RDY_tlb_flush; - - // value method mem_master_m_awvalid - output mem_master_awvalid; - - // value method mem_master_m_awid - output [3 : 0] mem_master_awid; - - // value method mem_master_m_awaddr - output [63 : 0] mem_master_awaddr; - - // value method mem_master_m_awlen - output [7 : 0] mem_master_awlen; - - // value method mem_master_m_awsize - output [2 : 0] mem_master_awsize; - - // value method mem_master_m_awburst - output [1 : 0] mem_master_awburst; - - // value method mem_master_m_awlock - output mem_master_awlock; - - // value method mem_master_m_awcache - output [3 : 0] mem_master_awcache; - - // value method mem_master_m_awprot - output [2 : 0] mem_master_awprot; - - // value method mem_master_m_awqos - output [3 : 0] mem_master_awqos; - - // value method mem_master_m_awregion - output [3 : 0] mem_master_awregion; - - // value method mem_master_m_awuser - - // action method mem_master_m_awready - input mem_master_awready; - - // value method mem_master_m_wvalid - output mem_master_wvalid; - - // value method mem_master_m_wid - output [3 : 0] mem_master_wid; - - // value method mem_master_m_wdata - output [63 : 0] mem_master_wdata; - - // value method mem_master_m_wstrb - output [7 : 0] mem_master_wstrb; - - // value method mem_master_m_wlast - output mem_master_wlast; - - // value method mem_master_m_wuser - - // action method mem_master_m_wready - input mem_master_wready; - - // action method mem_master_m_bvalid - input mem_master_bvalid; - input [3 : 0] mem_master_bid; - input [1 : 0] mem_master_bresp; - - // value method mem_master_m_bready - output mem_master_bready; - - // value method mem_master_m_arvalid - output mem_master_arvalid; - - // value method mem_master_m_arid - output [3 : 0] mem_master_arid; - - // value method mem_master_m_araddr - output [63 : 0] mem_master_araddr; - - // value method mem_master_m_arlen - output [7 : 0] mem_master_arlen; - - // value method mem_master_m_arsize - output [2 : 0] mem_master_arsize; - - // value method mem_master_m_arburst - output [1 : 0] mem_master_arburst; - - // value method mem_master_m_arlock - output mem_master_arlock; - - // value method mem_master_m_arcache - output [3 : 0] mem_master_arcache; - - // value method mem_master_m_arprot - output [2 : 0] mem_master_arprot; - - // value method mem_master_m_arqos - output [3 : 0] mem_master_arqos; - - // value method mem_master_m_arregion - output [3 : 0] mem_master_arregion; - - // value method mem_master_m_aruser - - // action method mem_master_m_arready - input mem_master_arready; - - // action method mem_master_m_rvalid - input mem_master_rvalid; - input [3 : 0] mem_master_rid; - input [63 : 0] mem_master_rdata; - input [1 : 0] mem_master_rresp; - input mem_master_rlast; - - // value method mem_master_m_rready - output mem_master_rready; - - // signals for module outputs - reg [63 : 0] word64; - wire [63 : 0] addr, - mem_master_araddr, - mem_master_awaddr, - mem_master_wdata, - st_amo_val; - wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; - wire [3 : 0] exc_code, - mem_master_arcache, - mem_master_arid, - mem_master_arqos, - mem_master_arregion, - mem_master_awcache, - mem_master_awid, - mem_master_awqos, - mem_master_awregion, - mem_master_wid; - wire [2 : 0] mem_master_arprot, - mem_master_arsize, - mem_master_awprot, - mem_master_awsize; - wire [1 : 0] mem_master_arburst, mem_master_awburst; - wire RDY_server_flush_request_put, - RDY_server_flush_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_verbosity, - RDY_tlb_flush, - exc, - mem_master_arlock, - mem_master_arvalid, - mem_master_awlock, - mem_master_awvalid, - mem_master_bready, - mem_master_rready, - mem_master_wlast, - mem_master_wvalid, - valid; - - // inlined wires - reg [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1; - wire [10 : 0] crg_sb_to_load_delay$port0__write_1, - crg_sb_to_load_delay$port2__read; - wire [3 : 0] ctr_wr_rsps_pending_crg$port1__write_1, - ctr_wr_rsps_pending_crg$port2__read, - ctr_wr_rsps_pending_crg$port3__read; - wire crg_sb_to_load_delay$EN_port1__write, - ctr_wr_rsps_pending_crg$EN_port0__write, - ctr_wr_rsps_pending_crg$EN_port2__write, - dw_valid$whas, - master_xactor_crg_rd_addr_full$EN_port0__write, - master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port1__read, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port0__write, - master_xactor_crg_rd_data_full$EN_port1__write, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port1__read, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port0__write, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$EN_port2__write, - master_xactor_crg_wr_addr_full$port1__read, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port0__write, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$EN_port2__write, - master_xactor_crg_wr_data_full$port1__read, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read, - master_xactor_crg_wr_resp_full$EN_port0__write, - master_xactor_crg_wr_resp_full$EN_port2__write, - master_xactor_crg_wr_resp_full$port1__read, - master_xactor_crg_wr_resp_full$port2__read, - master_xactor_crg_wr_resp_full$port3__read; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_sb_to_load_delay - reg [10 : 0] crg_sb_to_load_delay; - wire [10 : 0] crg_sb_to_load_delay$D_IN; - wire crg_sb_to_load_delay$EN; - - // register ctr_wr_rsps_pending_crg - reg [3 : 0] ctr_wr_rsps_pending_crg; - wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN; - wire ctr_wr_rsps_pending_crg$EN; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - reg [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - reg [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [76 : 0] master_xactor_rg_wr_data; - reg [76 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - - // register rg_addr - reg [63 : 0] rg_addr; - wire [63 : 0] rg_addr$D_IN; - wire rg_addr$EN; - - // register rg_amo_funct7 - reg [6 : 0] rg_amo_funct7; - wire [6 : 0] rg_amo_funct7$D_IN; - wire rg_amo_funct7$EN; - - // register rg_cset_in_cache - reg [5 : 0] rg_cset_in_cache; - wire [5 : 0] rg_cset_in_cache$D_IN; - wire rg_cset_in_cache$EN; - - // register rg_error_during_refill - reg rg_error_during_refill; - wire rg_error_during_refill$D_IN, rg_error_during_refill$EN; - - // register rg_exc_code - reg [3 : 0] rg_exc_code; - reg [3 : 0] rg_exc_code$D_IN; - wire rg_exc_code$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_ld_val - reg [63 : 0] rg_ld_val; - reg [63 : 0] rg_ld_val$D_IN; - wire rg_ld_val$EN; - - // register rg_lower_word32 - reg [31 : 0] rg_lower_word32; - wire [31 : 0] rg_lower_word32$D_IN; - wire rg_lower_word32$EN; - - // register rg_lower_word32_full - reg rg_lower_word32_full; - wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN; - - // register rg_lrsc_pa - reg [63 : 0] rg_lrsc_pa; - wire [63 : 0] rg_lrsc_pa$D_IN; - wire rg_lrsc_pa$EN; - - // register rg_lrsc_valid - reg rg_lrsc_valid; - wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_op - reg [1 : 0] rg_op; - wire [1 : 0] rg_op$D_IN; - wire rg_op$EN; - - // register rg_pa - reg [63 : 0] rg_pa; - wire [63 : 0] rg_pa$D_IN; - wire rg_pa$EN; - - // register rg_priv - reg [1 : 0] rg_priv; - wire [1 : 0] rg_priv$D_IN; - wire rg_priv$EN; - - // register rg_pte_pa - reg [63 : 0] rg_pte_pa; - reg [63 : 0] rg_pte_pa$D_IN; - wire rg_pte_pa$EN; - - // register rg_satp - reg [63 : 0] rg_satp; - wire [63 : 0] rg_satp$D_IN; - wire rg_satp$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_st_amo_val - reg [63 : 0] rg_st_amo_val; - wire [63 : 0] rg_st_amo_val$D_IN; - wire rg_st_amo_val$EN; - - // register rg_state - reg [4 : 0] rg_state; - reg [4 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_word64_set_in_cache - reg [8 : 0] rg_word64_set_in_cache; - wire [8 : 0] rg_word64_set_in_cache$D_IN; - wire rg_word64_set_in_cache$EN; - - // ports of submodule f_pte_writebacks - wire [127 : 0] f_pte_writebacks$D_IN, f_pte_writebacks$D_OUT; - wire f_pte_writebacks$CLR, - f_pte_writebacks$DEQ, - f_pte_writebacks$EMPTY_N, - f_pte_writebacks$ENQ, - f_pte_writebacks$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule ram_state_and_ctag_cset - wire [52 : 0] ram_state_and_ctag_cset$DIA, - ram_state_and_ctag_cset$DIB, - ram_state_and_ctag_cset$DOB; - wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB; - wire ram_state_and_ctag_cset$ENA, - ram_state_and_ctag_cset$ENB, - ram_state_and_ctag_cset$WEA, - ram_state_and_ctag_cset$WEB; - - // ports of submodule ram_word64_set - reg [63 : 0] ram_word64_set$DIB; - reg [8 : 0] ram_word64_set$ADDRB; - wire [63 : 0] ram_word64_set$DIA, ram_word64_set$DOB; - wire [8 : 0] ram_word64_set$ADDRA; - wire ram_word64_set$ENA, - ram_word64_set$ENB, - ram_word64_set$WEA, - ram_word64_set$WEB; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - wire soc_map$m_is_mem_addr; - - // ports of submodule tlb - reg [1 : 0] tlb$insert_level; - wire [130 : 0] tlb$lookup; - wire [63 : 0] tlb$insert_pte, tlb$insert_pte_pa; - wire [26 : 0] tlb$insert_vpn, tlb$lookup_vpn; - wire [15 : 0] tlb$insert_asid, tlb$lookup_asid; - wire tlb$EN_flush, tlb$EN_insert, tlb$RDY_insert, tlb$RDY_lookup; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_ST_AMO_response, - CAN_FIRE_RL_rl_cache_refill_rsps_loop, - CAN_FIRE_RL_rl_discard_write_rsp, - CAN_FIRE_RL_rl_drive_exception_rsp, - CAN_FIRE_RL_rl_io_AMO_SC_req, - CAN_FIRE_RL_rl_io_AMO_op_req, - CAN_FIRE_RL_rl_io_AMO_read_rsp, - CAN_FIRE_RL_rl_io_read_req, - CAN_FIRE_RL_rl_io_read_rsp, - CAN_FIRE_RL_rl_io_write_req, - CAN_FIRE_RL_rl_maintain_io_read_rsp, - CAN_FIRE_RL_rl_probe_and_immed_rsp, - CAN_FIRE_RL_rl_ptw_level_0, - CAN_FIRE_RL_rl_ptw_level_1, - CAN_FIRE_RL_rl_ptw_level_2, - CAN_FIRE_RL_rl_rereq, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_shift_sb_to_load_delay, - CAN_FIRE_RL_rl_start_cache_refill, - CAN_FIRE_RL_rl_start_reset, - CAN_FIRE_RL_rl_start_tlb_refill, - CAN_FIRE_RL_rl_writeback_updated_PTE, - CAN_FIRE_mem_master_m_arready, - CAN_FIRE_mem_master_m_awready, - CAN_FIRE_mem_master_m_bvalid, - CAN_FIRE_mem_master_m_rvalid, - CAN_FIRE_mem_master_m_wready, - CAN_FIRE_req, - CAN_FIRE_server_flush_request_put, - CAN_FIRE_server_flush_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_verbosity, - CAN_FIRE_tlb_flush, - WILL_FIRE_RL_rl_ST_AMO_response, - WILL_FIRE_RL_rl_cache_refill_rsps_loop, - WILL_FIRE_RL_rl_discard_write_rsp, - WILL_FIRE_RL_rl_drive_exception_rsp, - WILL_FIRE_RL_rl_io_AMO_SC_req, - WILL_FIRE_RL_rl_io_AMO_op_req, - WILL_FIRE_RL_rl_io_AMO_read_rsp, - WILL_FIRE_RL_rl_io_read_req, - WILL_FIRE_RL_rl_io_read_rsp, - WILL_FIRE_RL_rl_io_write_req, - WILL_FIRE_RL_rl_maintain_io_read_rsp, - WILL_FIRE_RL_rl_probe_and_immed_rsp, - WILL_FIRE_RL_rl_ptw_level_0, - WILL_FIRE_RL_rl_ptw_level_1, - WILL_FIRE_RL_rl_ptw_level_2, - WILL_FIRE_RL_rl_rereq, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_shift_sb_to_load_delay, - WILL_FIRE_RL_rl_start_cache_refill, - WILL_FIRE_RL_rl_start_reset, - WILL_FIRE_RL_rl_start_tlb_refill, - WILL_FIRE_RL_rl_writeback_updated_PTE, - WILL_FIRE_mem_master_m_arready, - WILL_FIRE_mem_master_m_awready, - WILL_FIRE_mem_master_m_bvalid, - WILL_FIRE_mem_master_m_rvalid, - WILL_FIRE_mem_master_m_wready, - WILL_FIRE_req, - WILL_FIRE_server_flush_request_put, - WILL_FIRE_server_flush_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_verbosity, - WILL_FIRE_tlb_flush; - - // inputs to muxes for submodule ports - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2, - MUX_master_xactor_rg_rd_addr$write_1__VAL_3, - MUX_master_xactor_rg_rd_addr$write_1__VAL_4, - MUX_master_xactor_rg_rd_addr$write_1__VAL_5, - MUX_master_xactor_rg_wr_addr$write_1__VAL_1, - MUX_master_xactor_rg_wr_addr$write_1__VAL_2, - MUX_master_xactor_rg_wr_addr$write_1__VAL_4; - wire [76 : 0] MUX_master_xactor_rg_wr_data$write_1__VAL_1, - MUX_master_xactor_rg_wr_data$write_1__VAL_2, - MUX_master_xactor_rg_wr_data$write_1__VAL_3, - MUX_master_xactor_rg_wr_data$write_1__VAL_4; - wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3, - MUX_ram_word64_set$a_put_3__VAL_2, - MUX_rg_ld_val$write_1__VAL_2; - wire [52 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1; - wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2, - MUX_ram_word64_set$b_put_2__VAL_4; - wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1; - wire [4 : 0] MUX_rg_state$write_1__VAL_10, - MUX_rg_state$write_1__VAL_11, - MUX_rg_state$write_1__VAL_12, - MUX_rg_state$write_1__VAL_13, - MUX_rg_state$write_1__VAL_14, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_6; - wire [3 : 0] MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_6; - wire MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2, - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_1, - MUX_dw_output_ld_val$wset_1__SEL_2, - MUX_dw_output_ld_val$wset_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_4, - MUX_master_xactor_rg_rd_addr$write_1__SEL_1, - MUX_master_xactor_rg_rd_addr$write_1__SEL_2, - MUX_master_xactor_rg_rd_addr$write_1__SEL_3, - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1, - MUX_ram_word64_set$a_put_1__SEL_1, - MUX_ram_word64_set$b_put_1__SEL_2, - MUX_rg_error_during_refill$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_2, - MUX_rg_exc_code$write_1__SEL_3, - MUX_rg_exc_code$write_1__SEL_5, - MUX_rg_exc_code$write_1__SEL_6, - MUX_rg_exc_code$write_1__SEL_7, - MUX_rg_exc_code$write_1__SEL_8, - MUX_rg_ld_val$write_1__SEL_2, - MUX_rg_lrsc_valid$write_1__SEL_2, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_14, - MUX_rg_state$write_1__SEL_18, - MUX_rg_state$write_1__SEL_3, - MUX_tlb$insert_1__SEL_1, - MUX_tlb$insert_1__SEL_2, - MUX_tlb$insert_1__SEL_3, - MUX_tlb$insert_1__SEL_4; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4708; - reg [31 : 0] v__h4809; - reg [31 : 0] v__h30746; - reg [31 : 0] v__h31644; - reg [31 : 0] v__h4339; - reg [31 : 0] v__h5262; - reg [31 : 0] v__h14971; - reg [31 : 0] v__h19190; - reg [31 : 0] v__h18615; - reg [31 : 0] v__h22626; - reg [31 : 0] v__h24225; - reg [31 : 0] v__h23982; - reg [31 : 0] v__h24536; - reg [31 : 0] v__h24648; - reg [31 : 0] v__h24154; - reg [31 : 0] v__h25282; - reg [31 : 0] v__h25042; - reg [31 : 0] v__h25705; - reg [31 : 0] v__h25593; - reg [31 : 0] v__h25211; - reg [31 : 0] v__h26177; - reg [31 : 0] v__h26248; - reg [31 : 0] v__h26330; - reg [31 : 0] v__h26106; - reg [31 : 0] v__h27239; - reg [31 : 0] v__h27461; - reg [31 : 0] v__h29434; - reg [31 : 0] v__h30534; - reg [31 : 0] v__h30641; - reg [31 : 0] v__h30826; - reg [31 : 0] v__h31348; - reg [31 : 0] v__h31762; - reg [31 : 0] v__h3705; - reg [31 : 0] v__h32080; - reg [31 : 0] v__h32255; - reg [31 : 0] v__h34868; - reg [31 : 0] v__h35120; - reg [31 : 0] v__h32351; - reg [31 : 0] v__h23262; - reg [31 : 0] v__h26457; - reg [31 : 0] v__h29060; - reg [31 : 0] v__h36090; - reg [31 : 0] v__h37244; - reg [31 : 0] v__h35740; - reg [31 : 0] v__h35701; - reg [31 : 0] v__h3699; - reg [31 : 0] v__h4333; - reg [31 : 0] v__h4702; - reg [31 : 0] v__h4803; - reg [31 : 0] v__h5256; - reg [31 : 0] v__h14965; - reg [31 : 0] v__h18609; - reg [31 : 0] v__h19184; - reg [31 : 0] v__h22620; - reg [31 : 0] v__h23256; - reg [31 : 0] v__h23976; - reg [31 : 0] v__h24148; - reg [31 : 0] v__h24219; - reg [31 : 0] v__h24530; - reg [31 : 0] v__h24642; - reg [31 : 0] v__h25036; - reg [31 : 0] v__h25205; - reg [31 : 0] v__h25276; - reg [31 : 0] v__h25587; - reg [31 : 0] v__h25699; - reg [31 : 0] v__h26100; - reg [31 : 0] v__h26171; - reg [31 : 0] v__h26242; - reg [31 : 0] v__h26324; - reg [31 : 0] v__h26451; - reg [31 : 0] v__h27233; - reg [31 : 0] v__h27455; - reg [31 : 0] v__h29054; - reg [31 : 0] v__h29428; - reg [31 : 0] v__h30528; - reg [31 : 0] v__h30635; - reg [31 : 0] v__h30740; - reg [31 : 0] v__h30820; - reg [31 : 0] v__h31342; - reg [31 : 0] v__h31638; - reg [31 : 0] v__h31756; - reg [31 : 0] v__h32074; - reg [31 : 0] v__h32249; - reg [31 : 0] v__h32345; - reg [31 : 0] v__h34862; - reg [31 : 0] v__h35114; - reg [31 : 0] v__h35695; - reg [31 : 0] v__h35734; - reg [31 : 0] v__h36084; - reg [31 : 0] v__h37238; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34, - CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35, - CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50, - CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30, - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33, - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755, - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630, - _theResult_____2__h19719, - _theResult_____2__h32673, - _theResult___fst__h6654, - ld_val__h29543, - mem_req_wr_data_wdata__h18986, - mem_req_wr_data_wdata__h22422, - mem_req_wr_data_wdata__h31144, - mem_req_wr_data_wdata__h32648, - new_ld_val__h32381, - new_value__h17706, - new_value__h7679, - w1__h19711, - w1__h32661, - w1__h32665; - reg [7 : 0] mem_req_wr_data_wstrb__h18987, mem_req_wr_data_wstrb__h32649; - reg [2 : 0] value__h31966, value__h34992; - reg CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211, - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245, - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297; - wire [63 : 0] IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563, - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694, - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d787, - _theResult___fst__h6279, - _theResult___fst__h6350, - _theResult___snd_fst__h18994, - _theResult___snd_fst__h22430, - _theResult___snd_fst__h31152, - _theResult___snd_fst__h32656, - _theResult___snd_fst__h6281, - _theResult___snd_fst__h6352, - _theResult___snd_fst__h6883, - cline_fabric_addr__h26510, - lev_0_pte_pa__h25314, - lev_0_pte_pa_w64_fa__h25316, - lev_1_PTN_pa__h24255, - lev_1_pte_pa__h24257, - lev_1_pte_pa_w64_fa__h24259, - lev_2_pte_pa__h23315, - lev_2_pte_pa_w64_fa__h23317, - new_st_val__h19441, - new_st_val__h19723, - new_st_val__h19814, - new_st_val__h20794, - new_st_val__h20798, - new_st_val__h20802, - new_st_val__h20806, - new_st_val__h20811, - new_st_val__h20817, - new_st_val__h20822, - new_st_val__h32677, - new_st_val__h32768, - new_st_val__h34628, - new_st_val__h34632, - new_st_val__h34636, - new_st_val__h34640, - new_st_val__h34645, - new_st_val__h34651, - new_st_val__h34656, - pa___1__h6660, - pa___1__h6709, - pa___1__h6778, - pte___1__h6932, - pte___1__h6960, - pte___2__h6652, - result__h14088, - result__h14116, - result__h14144, - result__h14172, - result__h14200, - result__h14228, - result__h14256, - result__h14301, - result__h14329, - result__h14357, - result__h14385, - result__h14413, - result__h14441, - result__h14469, - result__h14497, - result__h14542, - result__h14570, - result__h14598, - result__h14626, - result__h14667, - result__h14695, - result__h14723, - result__h14751, - result__h14792, - result__h14820, - result__h14859, - result__h14887, - result__h29603, - result__h29633, - result__h29660, - result__h29687, - result__h29714, - result__h29741, - result__h29768, - result__h29795, - result__h29839, - result__h29866, - result__h29893, - result__h29920, - result__h29947, - result__h29974, - result__h30001, - result__h30028, - result__h30072, - result__h30099, - result__h30126, - result__h30153, - result__h30193, - result__h30220, - result__h30247, - result__h30274, - result__h30314, - result__h30341, - result__h30379, - result__h30406, - result__h32856, - result__h33764, - result__h33792, - result__h33820, - result__h33848, - result__h33876, - result__h33904, - result__h33932, - result__h33977, - result__h34005, - result__h34033, - result__h34061, - result__h34089, - result__h34117, - result__h34145, - result__h34173, - result__h34218, - result__h34246, - result__h34274, - result__h34302, - result__h34343, - result__h34371, - result__h34399, - result__h34427, - result__h34468, - result__h34496, - result__h34535, - result__h34563, - result__h7732, - satp_pa__h2470, - st_val__h32393, - value__h6977, - vpn_0_pa__h25313, - vpn_1_pa__h24256, - vpn_2_pa__h23314, - w1___1__h19782, - w1___1__h32736, - w2___1__h32737, - w2__h32667, - word64__h7498, - x1_avValue_pa__h6190, - x__h15358, - y__h7768; - wire [55 : 0] x__h24360, x__h5382, x__h6663, x__h6712, x__h6781; - wire [31 : 0] ld_val9543_BITS_31_TO_0__q38, - ld_val9543_BITS_63_TO_32__q45, - master_xactor_rg_rd_data_BITS_34_TO_3__q2, - master_xactor_rg_rd_data_BITS_66_TO_35__q10, - new_value679_BITS_31_TO_0__q31, - rg_st_amo_val_BITS_31_TO_0__q32, - w12661_BITS_31_TO_0__q51, - word64498_BITS_31_TO_0__q17, - word64498_BITS_63_TO_32__q24; - wire [15 : 0] ld_val9543_BITS_15_TO_0__q37, - ld_val9543_BITS_31_TO_16__q41, - ld_val9543_BITS_47_TO_32__q44, - ld_val9543_BITS_63_TO_48__q48, - master_xactor_rg_rd_data_BITS_18_TO_3__q3, - master_xactor_rg_rd_data_BITS_34_TO_19__q6, - master_xactor_rg_rd_data_BITS_50_TO_35__q9, - master_xactor_rg_rd_data_BITS_66_TO_51__q13, - word64498_BITS_15_TO_0__q16, - word64498_BITS_31_TO_16__q20, - word64498_BITS_47_TO_32__q23, - word64498_BITS_63_TO_48__q27; - wire [7 : 0] ld_val9543_BITS_15_TO_8__q39, - ld_val9543_BITS_23_TO_16__q40, - ld_val9543_BITS_31_TO_24__q42, - ld_val9543_BITS_39_TO_32__q43, - ld_val9543_BITS_47_TO_40__q46, - ld_val9543_BITS_55_TO_48__q47, - ld_val9543_BITS_63_TO_56__q49, - ld_val9543_BITS_7_TO_0__q36, - master_xactor_rg_rd_data_BITS_10_TO_3__q1, - master_xactor_rg_rd_data_BITS_18_TO_11__q4, - master_xactor_rg_rd_data_BITS_26_TO_19__q5, - master_xactor_rg_rd_data_BITS_34_TO_27__q7, - master_xactor_rg_rd_data_BITS_42_TO_35__q8, - master_xactor_rg_rd_data_BITS_50_TO_43__q11, - master_xactor_rg_rd_data_BITS_58_TO_51__q12, - master_xactor_rg_rd_data_BITS_66_TO_59__q14, - strobe64__h18920, - strobe64__h18922, - strobe64__h18924, - strobe64__h32582, - strobe64__h32584, - strobe64__h32586, - word64498_BITS_15_TO_8__q18, - word64498_BITS_23_TO_16__q19, - word64498_BITS_31_TO_24__q21, - word64498_BITS_39_TO_32__q22, - word64498_BITS_47_TO_40__q25, - word64498_BITS_55_TO_48__q26, - word64498_BITS_63_TO_56__q28, - word64498_BITS_7_TO_0__q15; - wire [5 : 0] shift_bits__h18787, shift_bits__h32449; - wire [4 : 0] IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d399, - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d398, - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d401; - wire [3 : 0] access_exc_code__h3151, - b__h23216, - exc_code___1__h6552, - x1_avValue_exc_code__h6191; - wire IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217, - IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d305, - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d304, - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435, - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284, - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289, - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d292, - NOT_cfg_verbosity_read__8_ULE_2_060___d1061, - NOT_cfg_verbosity_read__8_ULT_2_05___d406, - NOT_dmem_not_imem_01_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d341, - NOT_dmem_not_imem_01_OR_NOT_rg_op_6_EQ_0_7_8_A_ETC___d108, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d624, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d637, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d764, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d798, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d816, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d855, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d860, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d866, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d874, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d878, - NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d921, - NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d984, - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928, - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990, - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199, - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d437, - NOT_req_f3_BITS_1_TO_0_389_EQ_0b0_390_391_AND__ETC___d1410, - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294, - NOT_rg_op_6_EQ_0_7_8_AND_NOT_rg_op_6_EQ_2_9_0__ETC___d392, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d446, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d761, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d853, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d858, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d864, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d872, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d632, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d759, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d819, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d825, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d831, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d837, - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348, - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371, - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d409, - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d583, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d142, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d307, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d353, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d368, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d421, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d428, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d431, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d458, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d597, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d604, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d610, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d616, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d639, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d766, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d771, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d800, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d806, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d812, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d818, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d823, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d829, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d835, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d841, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d849, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d857, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d876, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d880, - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123, - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139, - cfg_verbosity_read__8_ULE_1___d19, - dmem_not_imem_AND_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_ETC___d343, - dmem_not_imem_OR_NOT_rg_op_6_EQ_0_7_8_AND_NOT__ETC___d100, - lrsc_result__h15348, - master_xactor_crg_rd_data_full_port1__read__96_ETC___d1222, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975, - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178, - ram_state_and_ctag_cset_b_read__73_BIT_52_74_A_ETC___d438, - req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419, - rg_amo_funct7_1_BITS_6_TO_2_2_EQ_0b10_3_AND_NO_ETC___d613, - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d387, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d424, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d449, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d588, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d607, - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d447, - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d635, - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d762, - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d767, - rg_op_6_EQ_2_9_AND_rg_amo_funct7_1_BITS_6_TO_2_ETC___d248, - rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117, - rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d309, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d356, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d395, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417, - rg_priv_9_ULE_0b1___d60, - rg_state_3_EQ_13_088_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d1090, - rg_state_3_EQ_3_12_AND_NOT_rg_op_6_EQ_0_7_8_AN_ETC___d316, - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106, - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350, - y__h6478; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method addr - assign addr = rg_addr ; - - // value method word64 - always@(MUX_dw_output_ld_val$wset_1__SEL_1 or - ld_val__h29543 or - MUX_dw_output_ld_val$wset_1__SEL_2 or - new_ld_val__h32381 or - MUX_dw_output_ld_val$wset_1__SEL_3 or - MUX_dw_output_ld_val$wset_1__VAL_3 or - MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h29543; - MUX_dw_output_ld_val$wset_1__SEL_2: word64 = new_ld_val__h32381; - MUX_dw_output_ld_val$wset_1__SEL_3: - word64 = MUX_dw_output_ld_val$wset_1__VAL_3; - MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val; - default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // value method st_amo_val - assign st_amo_val = - MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ; - - // value method exc - assign exc = rg_state == 5'd4 ; - - // value method exc_code - assign exc_code = rg_exc_code ; - - // action method server_flush_request_put - assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; - - // action method server_flush_response_get - assign RDY_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; - - // action method tlb_flush - assign RDY_tlb_flush = 1'd1 ; - assign CAN_FIRE_tlb_flush = 1'd1 ; - assign WILL_FIRE_tlb_flush = EN_tlb_flush ; - - // value method mem_master_m_awvalid - assign mem_master_awvalid = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - - // value method mem_master_m_awid - assign mem_master_awid = master_xactor_rg_wr_addr[96:93] ; - - // value method mem_master_m_awaddr - assign mem_master_awaddr = master_xactor_rg_wr_addr[92:29] ; - - // value method mem_master_m_awlen - assign mem_master_awlen = master_xactor_rg_wr_addr[28:21] ; - - // value method mem_master_m_awsize - assign mem_master_awsize = master_xactor_rg_wr_addr[20:18] ; - - // value method mem_master_m_awburst - assign mem_master_awburst = master_xactor_rg_wr_addr[17:16] ; - - // value method mem_master_m_awlock - assign mem_master_awlock = master_xactor_rg_wr_addr[15] ; - - // value method mem_master_m_awcache - assign mem_master_awcache = master_xactor_rg_wr_addr[14:11] ; - - // value method mem_master_m_awprot - assign mem_master_awprot = master_xactor_rg_wr_addr[10:8] ; - - // value method mem_master_m_awqos - assign mem_master_awqos = master_xactor_rg_wr_addr[7:4] ; - - // value method mem_master_m_awregion - assign mem_master_awregion = master_xactor_rg_wr_addr[3:0] ; - - // action method mem_master_m_awready - assign CAN_FIRE_mem_master_m_awready = 1'd1 ; - assign WILL_FIRE_mem_master_m_awready = 1'd1 ; - - // value method mem_master_m_wvalid - assign mem_master_wvalid = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - - // value method mem_master_m_wid - assign mem_master_wid = master_xactor_rg_wr_data[76:73] ; - - // value method mem_master_m_wdata - assign mem_master_wdata = master_xactor_rg_wr_data[72:9] ; - - // value method mem_master_m_wstrb - assign mem_master_wstrb = master_xactor_rg_wr_data[8:1] ; - - // value method mem_master_m_wlast - assign mem_master_wlast = master_xactor_rg_wr_data[0] ; - - // action method mem_master_m_wready - assign CAN_FIRE_mem_master_m_wready = 1'd1 ; - assign WILL_FIRE_mem_master_m_wready = 1'd1 ; - - // action method mem_master_m_bvalid - assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ; - - // value method mem_master_m_bready - assign mem_master_bready = !master_xactor_crg_wr_resp_full$port2__read ; - - // value method mem_master_m_arvalid - assign mem_master_arvalid = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - - // value method mem_master_m_arid - assign mem_master_arid = master_xactor_rg_rd_addr[96:93] ; - - // value method mem_master_m_araddr - assign mem_master_araddr = master_xactor_rg_rd_addr[92:29] ; - - // value method mem_master_m_arlen - assign mem_master_arlen = master_xactor_rg_rd_addr[28:21] ; - - // value method mem_master_m_arsize - assign mem_master_arsize = master_xactor_rg_rd_addr[20:18] ; - - // value method mem_master_m_arburst - assign mem_master_arburst = master_xactor_rg_rd_addr[17:16] ; - - // value method mem_master_m_arlock - assign mem_master_arlock = master_xactor_rg_rd_addr[15] ; - - // value method mem_master_m_arcache - assign mem_master_arcache = master_xactor_rg_rd_addr[14:11] ; - - // value method mem_master_m_arprot - assign mem_master_arprot = master_xactor_rg_rd_addr[10:8] ; - - // value method mem_master_m_arqos - assign mem_master_arqos = master_xactor_rg_rd_addr[7:4] ; - - // value method mem_master_m_arregion - assign mem_master_arregion = master_xactor_rg_rd_addr[3:0] ; - - // action method mem_master_m_arready - assign CAN_FIRE_mem_master_m_arready = 1'd1 ; - assign WILL_FIRE_mem_master_m_arready = 1'd1 ; - - // action method mem_master_m_rvalid - assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ; - - // value method mem_master_m_rready - assign mem_master_rready = !master_xactor_crg_rd_data_full$port2__read ; - - // submodule f_pte_writebacks - FIFO2 #(.width(32'd128), .guarded(32'd1)) f_pte_writebacks(.RST(RST_N), - .CLK(CLK), - .D_IN(f_pte_writebacks$D_IN), - .ENQ(f_pte_writebacks$ENQ), - .DEQ(f_pte_writebacks$DEQ), - .CLR(f_pte_writebacks$CLR), - .D_OUT(f_pte_writebacks$D_OUT), - .FULL_N(f_pte_writebacks$FULL_N), - .EMPTY_N(f_pte_writebacks$EMPTY_N)); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule ram_state_and_ctag_cset - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd6), - .DATA_WIDTH(32'd53), - .MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_state_and_ctag_cset$ADDRA), - .ADDRB(ram_state_and_ctag_cset$ADDRB), - .DIA(ram_state_and_ctag_cset$DIA), - .DIB(ram_state_and_ctag_cset$DIB), - .WEA(ram_state_and_ctag_cset$WEA), - .WEB(ram_state_and_ctag_cset$WEB), - .ENA(ram_state_and_ctag_cset$ENA), - .ENB(ram_state_and_ctag_cset$ENB), - .DOA(), - .DOB(ram_state_and_ctag_cset$DOB)); - - // submodule ram_word64_set - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd9), - .DATA_WIDTH(32'd64), - .MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_word64_set$ADDRA), - .ADDRB(ram_word64_set$ADDRB), - .DIA(ram_word64_set$DIA), - .DIB(ram_word64_set$DIB), - .WEA(ram_word64_set$WEA), - .WEB(ram_word64_set$WEB), - .ENA(ram_word64_set$ENA), - .ENB(ram_word64_set$ENB), - .DOA(), - .DOB(ram_word64_set$DOB)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(soc_map$m_is_mem_addr), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule tlb - mkTLB #(.dmem_not_imem(dmem_not_imem)) tlb(.CLK(CLK), - .RST_N(RST_N), - .insert_asid(tlb$insert_asid), - .insert_level(tlb$insert_level), - .insert_pte(tlb$insert_pte), - .insert_pte_pa(tlb$insert_pte_pa), - .insert_vpn(tlb$insert_vpn), - .lookup_asid(tlb$lookup_asid), - .lookup_vpn(tlb$lookup_vpn), - .EN_flush(tlb$EN_flush), - .EN_insert(tlb$EN_insert), - .RDY_flush(), - .lookup(tlb$lookup), - .RDY_lookup(tlb$RDY_lookup), - .RDY_insert(tlb$RDY_insert)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - (rg_cset_in_cache != 6'd63 || - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) && - rg_state == 5'd1 ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // rule RL_rl_shift_sb_to_load_delay - assign CAN_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - assign WILL_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - - // rule RL_rl_rereq - assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ; - assign WILL_FIRE_RL_rl_rereq = - CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ; - - // rule RL_rl_ST_AMO_response - assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ; - assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ; - - // rule RL_rl_maintain_io_read_rsp - assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ; - assign WILL_FIRE_RL_rl_maintain_io_read_rsp = - CAN_FIRE_RL_rl_maintain_io_read_rsp ; - - // rule RL_rl_io_AMO_SC_req - assign CAN_FIRE_RL_rl_io_AMO_SC_req = - rg_state == 5'd13 && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_SC_req = - CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_drive_exception_rsp - assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ; - assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ; - - // rule RL_rl_start_reset - assign CAN_FIRE_RL_rl_start_reset = - f_reset_reqs$EMPTY_N && rg_state != 5'd1 ; - assign WILL_FIRE_RL_rl_start_reset = CAN_FIRE_RL_rl_start_reset ; - - // rule RL_rl_probe_and_immed_rsp - assign CAN_FIRE_RL_rl_probe_and_immed_rsp = - (cfg_verbosity_read__8_ULE_1___d19 || tlb$RDY_lookup) && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$RDY_lookup) && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d309 && - rg_state_3_EQ_3_12_AND_NOT_rg_op_6_EQ_0_7_8_AN_ETC___d316 ; - assign WILL_FIRE_RL_rl_probe_and_immed_rsp = - CAN_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_ptw_level_2 - assign CAN_FIRE_RL_rl_ptw_level_2 = - master_xactor_crg_rd_data_full$port1__read && - NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d921 && - rg_state == 5'd6 ; - assign WILL_FIRE_RL_rl_ptw_level_2 = - CAN_FIRE_RL_rl_ptw_level_2 && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_ptw_level_1 - assign CAN_FIRE_RL_rl_ptw_level_1 = - master_xactor_crg_rd_data_full$port1__read && - NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d984 && - rg_state == 5'd7 ; - assign WILL_FIRE_RL_rl_ptw_level_1 = - CAN_FIRE_RL_rl_ptw_level_1 && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_ptw_level_0 - assign CAN_FIRE_RL_rl_ptw_level_0 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - !master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4] || - tlb$RDY_insert) && - rg_state == 5'd8 ; - assign WILL_FIRE_RL_rl_ptw_level_0 = - CAN_FIRE_RL_rl_ptw_level_0 && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_cache_refill_rsps_loop - assign CAN_FIRE_RL_rl_cache_refill_rsps_loop = - master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd10 ; - assign WILL_FIRE_RL_rl_cache_refill_rsps_loop = - CAN_FIRE_RL_rl_cache_refill_rsps_loop && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_rsp - assign CAN_FIRE_RL_rl_io_read_rsp = - master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd14 ; - assign WILL_FIRE_RL_rl_io_read_rsp = - CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_write_req - assign CAN_FIRE_RL_rl_io_write_req = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - rg_state == 5'd13 && - rg_op == 2'd1 ; - assign WILL_FIRE_RL_rl_io_write_req = - CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_op_req - assign CAN_FIRE_RL_rl_io_AMO_op_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 5'd13 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] != 5'b00010 && - rg_amo_funct7[6:2] != 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_op_req = - CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_writeback_updated_PTE - assign CAN_FIRE_RL_rl_writeback_updated_PTE = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - f_pte_writebacks$EMPTY_N ; - assign WILL_FIRE_RL_rl_writeback_updated_PTE = - CAN_FIRE_RL_rl_writeback_updated_PTE && - !WILL_FIRE_RL_rl_io_AMO_read_rsp && - !WILL_FIRE_RL_rl_io_write_req && - !WILL_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_read_rsp - assign CAN_FIRE_RL_rl_io_AMO_read_rsp = - master_xactor_crg_rd_data_full_port1__read__96_ETC___d1222 && - rg_state == 5'd16 ; - assign WILL_FIRE_RL_rl_io_AMO_read_rsp = - CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_tlb_refill - assign CAN_FIRE_RL_rl_start_tlb_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 5'd5 && - b__h23216 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_tlb_refill = - CAN_FIRE_RL_rl_start_tlb_refill && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_cache_refill - assign CAN_FIRE_RL_rl_start_cache_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 5'd9 && - b__h23216 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_cache_refill = - CAN_FIRE_RL_rl_start_cache_refill && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_req - assign CAN_FIRE_RL_rl_io_read_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state_3_EQ_13_088_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d1090 ; - assign WILL_FIRE_RL_rl_io_read_req = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_discard_write_rsp - assign CAN_FIRE_RL_rl_discard_write_rsp = - b__h23216 != 4'd0 && master_xactor_crg_wr_resp_full$port1__read ; - assign WILL_FIRE_RL_rl_discard_write_rsp = - CAN_FIRE_RL_rl_discard_write_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // inputs to muxes for submodule ports - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3 = - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign MUX_dw_output_ld_val$wset_1__SEL_1 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_dw_output_ld_val$wset_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_dw_output_ld_val$wset_1__SEL_3 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459 ; - assign MUX_dw_output_ld_val$wset_1__SEL_4 = - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_1 = - WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_2 = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_3 = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ; - assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 = - EN_req && - req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419 ; - assign MUX_ram_word64_set$a_put_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ram_word64_set$b_put_1__SEL_2 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 ; - assign MUX_rg_error_during_refill$write_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_1 = - EN_req && - NOT_req_f3_BITS_1_TO_0_389_EQ_0b0_390_391_AND__ETC___d1410 ; - assign MUX_rg_exc_code$write_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_3 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_5 = - WILL_FIRE_RL_rl_ptw_level_0 && - (!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - !master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4] || - master_xactor_rg_rd_data[2:1] != 2'b0) ; - assign MUX_rg_exc_code$write_1__SEL_6 = - WILL_FIRE_RL_rl_ptw_level_1 && - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990 ; - assign MUX_rg_exc_code$write_1__SEL_7 = - WILL_FIRE_RL_rl_ptw_level_2 && - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928 ; - assign MUX_rg_exc_code$write_1__SEL_8 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ; - assign MUX_rg_ld_val$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626 ; - assign MUX_rg_lrsc_valid$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452 ; - assign MUX_rg_state$write_1__SEL_3 = - CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ; - assign MUX_rg_state$write_1__SEL_10 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 ; - assign MUX_rg_state$write_1__SEL_14 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396 ; - assign MUX_rg_state$write_1__SEL_18 = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign MUX_tlb$insert_1__SEL_1 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 ; - assign MUX_tlb$insert_1__SEL_2 = - WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971 ; - assign MUX_tlb$insert_1__SEL_3 = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006 ; - assign MUX_tlb$insert_1__SEL_4 = - WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 = - ctr_wr_rsps_pending_crg + 4'd1 ; - assign MUX_dw_output_ld_val$wset_1__VAL_3 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - new_value__h7679 : - new_value__h17706 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, lev_1_pte_pa_w64_fa__h24259, 29'd851968 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, lev_0_pte_pa_w64_fa__h25316, 29'd851968 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_3 = - { 4'd0, rg_pa, 8'd0, value__h31966, 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_4 = - { 4'd0, lev_2_pte_pa_w64_fa__h23317, 29'd851968 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_5 = - { 4'd0, cline_fabric_addr__h26510, 29'd15532032 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_1 = - { 4'd0, rg_pa, 8'd0, value__h34992, 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_2 = - { 4'd0, x1_avValue_pa__h6190, 8'd0, value__h34992, 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_4 = - { 4'd0, f_pte_writebacks$D_OUT[127:64], 29'd851968 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_1 = - { 4'd0, - mem_req_wr_data_wdata__h32648, - mem_req_wr_data_wstrb__h32649, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_2 = - { 4'd0, - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d787, - mem_req_wr_data_wstrb__h18987, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_3 = - { 4'd0, f_pte_writebacks$D_OUT[63:0], 9'd511 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_4 = - { 4'd0, - mem_req_wr_data_wdata__h31144, - mem_req_wr_data_wstrb__h32649, - 1'd1 } ; - assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 = { 1'd1, rg_pa[63:12] } ; - assign MUX_ram_word64_set$a_put_3__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 : - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 ; - assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ; - assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ; - assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ; - assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ; - assign MUX_rg_exc_code$write_1__VAL_6 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - exc_code___1__h6552 : - access_exc_code__h3151 ; - assign MUX_rg_ld_val$write_1__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - x__h15358 : - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 ; - assign MUX_rg_state$write_1__VAL_2 = - NOT_req_f3_BITS_1_TO_0_389_EQ_0b0_390_391_AND__ETC___d1410 ? - 5'd4 : - 5'd3 ; - assign MUX_rg_state$write_1__VAL_6 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? 5'd15 : 5'd4 ; - assign MUX_rg_state$write_1__VAL_10 = - (master_xactor_rg_rd_data[2:1] != 2'b0 || - rg_error_during_refill) ? - 5'd4 : - 5'd11 ; - assign MUX_rg_state$write_1__VAL_11 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - ((!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && - master_xactor_rg_rd_data[5] || - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4]) ? - 5'd4 : - 5'd11) : - 5'd4 ; - assign MUX_rg_state$write_1__VAL_12 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - ((!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && - master_xactor_rg_rd_data[5]) ? - 5'd4 : - ((!master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4]) ? - 5'd8 : - ((master_xactor_rg_rd_data[21:13] == 9'd0) ? - 5'd11 : - 5'd4))) : - 5'd4 ; - assign MUX_rg_state$write_1__VAL_13 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - ((!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && - master_xactor_rg_rd_data[5]) ? - 5'd4 : - ((!master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4]) ? - 5'd7 : - ((master_xactor_rg_rd_data[30:22] != 9'd0 || - master_xactor_rg_rd_data[21:13] != 9'd0) ? - 5'd4 : - 5'd11))) : - 5'd4 ; - assign MUX_rg_state$write_1__VAL_14 = - (rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - !tlb$lookup[130]) ? - 5'd5 : - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d401 ; - - // inlined wires - assign dw_valid$whas = - (WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_read_rsp) && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459 || - WILL_FIRE_RL_rl_drive_exception_rsp || - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign master_xactor_crg_wr_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_addr_full$port1__read = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full$port1__read && - mem_master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full$port1__read ; - assign master_xactor_crg_wr_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign master_xactor_crg_wr_addr_full$port3__read = - master_xactor_crg_wr_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_data_full$port1__read = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full$port1__read && mem_master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full$port1__read ; - assign master_xactor_crg_wr_data_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign master_xactor_crg_wr_data_full$port3__read = - master_xactor_crg_wr_data_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_wr_resp_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_resp_full$port1__read = - !master_xactor_crg_wr_resp_full$EN_port0__write && - master_xactor_crg_wr_resp_full ; - assign master_xactor_crg_wr_resp_full$port2__read = - !WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_crg_wr_resp_full$port1__read ; - assign master_xactor_crg_wr_resp_full$EN_port2__write = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_wr_resp_full$port3__read = - master_xactor_crg_wr_resp_full$EN_port2__write || - master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_addr_full$port1__read = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full$port1__read && - mem_master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full$port1__read ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - (WILL_FIRE_RL_rl_ptw_level_1 || WILL_FIRE_RL_rl_ptw_level_2) && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] || - WILL_FIRE_RL_rl_io_AMO_op_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_tlb_refill ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_data_full$port1__read = - !master_xactor_crg_rd_data_full$EN_port0__write && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port1__write = - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_cache_refill_rsps_loop || - WILL_FIRE_RL_rl_ptw_level_0 || - WILL_FIRE_RL_rl_ptw_level_1 || - WILL_FIRE_RL_rl_ptw_level_2 || - WILL_FIRE_RL_rl_io_AMO_read_rsp ; - assign master_xactor_crg_rd_data_full$port2__read = - !master_xactor_crg_rd_data_full$EN_port1__write && - master_xactor_crg_rd_data_full$port1__read ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - mem_master_rvalid && - !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - assign ctr_wr_rsps_pending_crg$EN_port0__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - always@(MUX_dw_output_ld_val$wset_1__SEL_2 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_2: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - default: ctr_wr_rsps_pending_crg$port0__write_1 = - 4'b1010 /* unspecified value */ ; - endcase - end - assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h23216 - 4'd1 ; - assign ctr_wr_rsps_pending_crg$port2__read = - WILL_FIRE_RL_rl_discard_write_rsp ? - ctr_wr_rsps_pending_crg$port1__write_1 : - b__h23216 ; - assign ctr_wr_rsps_pending_crg$EN_port2__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign ctr_wr_rsps_pending_crg$port3__read = - ctr_wr_rsps_pending_crg$EN_port2__write ? - 4'd0 : - ctr_wr_rsps_pending_crg$port2__read ; - assign crg_sb_to_load_delay$port0__write_1 = - { 1'd0, crg_sb_to_load_delay[10:1] } ; - assign crg_sb_to_load_delay$EN_port1__write = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d766 ; - assign crg_sb_to_load_delay$port2__read = - crg_sb_to_load_delay$EN_port1__write ? - 11'd2047 : - crg_sb_to_load_delay$port0__write_1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register crg_sb_to_load_delay - assign crg_sb_to_load_delay$D_IN = crg_sb_to_load_delay$port2__read ; - assign crg_sb_to_load_delay$EN = 1'b1 ; - - // register ctr_wr_rsps_pending_crg - assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ; - assign ctr_wr_rsps_pending_crg$EN = 1'b1 ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = - master_xactor_crg_wr_resp_full$port3__read ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - always@(MUX_master_xactor_rg_rd_addr$write_1__SEL_1 or - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 or - MUX_master_xactor_rg_rd_addr$write_1__SEL_2 or - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 or - MUX_master_xactor_rg_rd_addr$write_1__SEL_3 or - MUX_master_xactor_rg_rd_addr$write_1__VAL_3 or - WILL_FIRE_RL_rl_start_tlb_refill or - MUX_master_xactor_rg_rd_addr$write_1__VAL_4 or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_master_xactor_rg_rd_addr$write_1__VAL_5) - begin - case (1'b1) // synopsys parallel_case - MUX_master_xactor_rg_rd_addr$write_1__SEL_1: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_1; - MUX_master_xactor_rg_rd_addr$write_1__SEL_2: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_2; - MUX_master_xactor_rg_rd_addr$write_1__SEL_3: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_3; - WILL_FIRE_RL_rl_start_tlb_refill: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_4; - WILL_FIRE_RL_rl_start_cache_refill: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_5; - default: master_xactor_rg_rd_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_rd_addr$EN = - WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] || - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] || - WILL_FIRE_RL_rl_io_AMO_op_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_tlb_refill || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - always@(MUX_dw_output_ld_val$wset_1__SEL_2 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_writeback_updated_PTE or - MUX_master_xactor_rg_wr_addr$write_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_2: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - WILL_FIRE_RL_rl_writeback_updated_PTE: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_4; - default: master_xactor_rg_wr_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_addr$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - - // register master_xactor_rg_wr_data - always@(MUX_dw_output_ld_val$wset_1__SEL_2 or - MUX_master_xactor_rg_wr_data$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_data$write_1__VAL_2 or - WILL_FIRE_RL_rl_writeback_updated_PTE or - MUX_master_xactor_rg_wr_data$write_1__VAL_3 or - WILL_FIRE_RL_rl_io_write_req or - MUX_master_xactor_rg_wr_data$write_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_2: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_2; - WILL_FIRE_RL_rl_writeback_updated_PTE: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_4; - default: master_xactor_rg_wr_data$D_IN = - 77'h0AAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_data$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 || - WILL_FIRE_RL_rl_writeback_updated_PTE || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = - { mem_master_bid, mem_master_bresp } ; - assign master_xactor_rg_wr_resp$EN = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - - // register rg_addr - assign rg_addr$D_IN = req_addr ; - assign rg_addr$EN = EN_req ; - - // register rg_amo_funct7 - assign rg_amo_funct7$D_IN = req_amo_funct7 ; - assign rg_amo_funct7$EN = EN_req ; - - // register rg_cset_in_cache - assign rg_cset_in_cache$D_IN = - WILL_FIRE_RL_rl_reset ? - MUX_rg_cset_in_cache$write_1__VAL_1 : - 6'd0 ; - assign rg_cset_in_cache$EN = - WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ; - - // register rg_error_during_refill - assign rg_error_during_refill$D_IN = - MUX_rg_error_during_refill$write_1__SEL_1 ; - assign rg_error_during_refill$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register rg_exc_code - always@(MUX_rg_exc_code$write_1__SEL_1 or - MUX_rg_exc_code$write_1__VAL_1 or - MUX_rg_exc_code$write_1__SEL_2 or - MUX_rg_exc_code$write_1__SEL_3 or - MUX_rg_error_during_refill$write_1__SEL_1 or - access_exc_code__h3151 or - MUX_rg_exc_code$write_1__SEL_5 or - MUX_rg_exc_code$write_1__VAL_6 or - MUX_rg_exc_code$write_1__SEL_6 or - MUX_rg_exc_code$write_1__SEL_7 or - MUX_rg_exc_code$write_1__SEL_8 or x1_avValue_exc_code__h6191) - case (1'b1) - MUX_rg_exc_code$write_1__SEL_1: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1; - MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7; - MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5; - MUX_rg_error_during_refill$write_1__SEL_1: - rg_exc_code$D_IN = access_exc_code__h3151; - MUX_rg_exc_code$write_1__SEL_5: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_6; - MUX_rg_exc_code$write_1__SEL_6: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_6; - MUX_rg_exc_code$write_1__SEL_7: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_6; - MUX_rg_exc_code$write_1__SEL_8: - rg_exc_code$D_IN = x1_avValue_exc_code__h6191; - default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_exc_code$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - EN_req && - NOT_req_f3_BITS_1_TO_0_389_EQ_0b0_390_391_AND__ETC___d1410 || - WILL_FIRE_RL_rl_ptw_level_2 && - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928 || - WILL_FIRE_RL_rl_ptw_level_1 && - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990 || - WILL_FIRE_RL_rl_ptw_level_0 && - (!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - !master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4] || - master_xactor_rg_rd_data[2:1] != 2'b0) ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_ld_val - always@(MUX_dw_output_ld_val$wset_1__SEL_2 or - new_ld_val__h32381 or - MUX_rg_ld_val$write_1__SEL_2 or - MUX_rg_ld_val$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_rsp or - ld_val__h29543 or WILL_FIRE_RL_rl_io_AMO_SC_req) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_2: rg_ld_val$D_IN = new_ld_val__h32381; - MUX_rg_ld_val$write_1__SEL_2: - rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h29543; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1; - default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_ld_val$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_SC_req ; - - // register rg_lower_word32 - assign rg_lower_word32$D_IN = 32'h0 ; - assign rg_lower_word32$EN = 1'b0 ; - - // register rg_lower_word32_full - assign rg_lower_word32_full$D_IN = 1'd0 ; - assign rg_lower_word32_full$EN = - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_lrsc_pa - assign rg_lrsc_pa$D_IN = soc_map$m_is_mem_addr_addr ; - assign rg_lrsc_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d597 ; - - // register rg_lrsc_valid - assign rg_lrsc_valid$D_IN = - MUX_rg_lrsc_valid$write_1__SEL_2 && - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453 ; - assign rg_lrsc_valid$EN = - WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452 || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = req_mstatus_MXR ; - assign rg_mstatus_MXR$EN = EN_req ; - - // register rg_op - assign rg_op$D_IN = req_op ; - assign rg_op$EN = EN_req ; - - // register rg_pa - assign rg_pa$D_IN = EN_req ? req_addr : soc_map$m_is_mem_addr_addr ; - assign rg_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d421 || - EN_req ; - - // register rg_priv - assign rg_priv$D_IN = req_priv ; - assign rg_priv$EN = EN_req ; - - // register rg_pte_pa - always@(MUX_master_xactor_rg_rd_addr$write_1__SEL_1 or - lev_1_pte_pa__h24257 or - MUX_master_xactor_rg_rd_addr$write_1__SEL_2 or - lev_0_pte_pa__h25314 or - WILL_FIRE_RL_rl_start_tlb_refill or lev_2_pte_pa__h23315) - begin - case (1'b1) // synopsys parallel_case - MUX_master_xactor_rg_rd_addr$write_1__SEL_1: - rg_pte_pa$D_IN = lev_1_pte_pa__h24257; - MUX_master_xactor_rg_rd_addr$write_1__SEL_2: - rg_pte_pa$D_IN = lev_0_pte_pa__h25314; - WILL_FIRE_RL_rl_start_tlb_refill: rg_pte_pa$D_IN = lev_2_pte_pa__h23315; - default: rg_pte_pa$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_pte_pa$EN = - WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] || - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] || - WILL_FIRE_RL_rl_start_tlb_refill ; - - // register rg_satp - assign rg_satp$D_IN = req_satp ; - assign rg_satp$EN = EN_req ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = req_sstatus_SUM ; - assign rg_sstatus_SUM$EN = EN_req ; - - // register rg_st_amo_val - assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h19441 ; - assign rg_st_amo_val$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d880 || - EN_req ; - - // register rg_state - always@(EN_tlb_flush or - EN_req or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_req or - WILL_FIRE_RL_rl_start_cache_refill or - WILL_FIRE_RL_rl_start_tlb_refill or - WILL_FIRE_RL_rl_io_AMO_read_rsp or - MUX_rg_state$write_1__VAL_6 or - WILL_FIRE_RL_rl_io_AMO_op_req or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_io_read_rsp or - MUX_rg_state$write_1__SEL_10 or - MUX_rg_state$write_1__VAL_10 or - WILL_FIRE_RL_rl_ptw_level_0 or - MUX_rg_state$write_1__VAL_11 or - WILL_FIRE_RL_rl_ptw_level_1 or - MUX_rg_state$write_1__VAL_12 or - WILL_FIRE_RL_rl_ptw_level_2 or - MUX_rg_state$write_1__VAL_13 or - MUX_rg_state$write_1__SEL_14 or - MUX_rg_state$write_1__VAL_14 or - WILL_FIRE_RL_rl_start_reset or - WILL_FIRE_RL_rl_io_AMO_SC_req or - WILL_FIRE_RL_rl_rereq or MUX_rg_state$write_1__SEL_18) - case (1'b1) - EN_tlb_flush: rg_state$D_IN = 5'd2; - EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14; - WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10; - WILL_FIRE_RL_rl_start_tlb_refill: rg_state$D_IN = 5'd6; - WILL_FIRE_RL_rl_io_AMO_read_rsp: - rg_state$D_IN = MUX_rg_state$write_1__VAL_6; - WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16; - WILL_FIRE_RL_rl_io_write_req: rg_state$D_IN = 5'd12; - WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_6; - MUX_rg_state$write_1__SEL_10: - rg_state$D_IN = MUX_rg_state$write_1__VAL_10; - WILL_FIRE_RL_rl_ptw_level_0: rg_state$D_IN = MUX_rg_state$write_1__VAL_11; - WILL_FIRE_RL_rl_ptw_level_1: rg_state$D_IN = MUX_rg_state$write_1__VAL_12; - WILL_FIRE_RL_rl_ptw_level_2: rg_state$D_IN = MUX_rg_state$write_1__VAL_13; - MUX_rg_state$write_1__SEL_14: - rg_state$D_IN = MUX_rg_state$write_1__VAL_14; - WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_state$D_IN = 5'd12; - WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3; - MUX_rg_state$write_1__SEL_18: rg_state$D_IN = 5'd2; - default: rg_state$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_state$EN = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_ptw_level_2 || - WILL_FIRE_RL_rl_ptw_level_1 || - WILL_FIRE_RL_rl_ptw_level_0 || - EN_req || - WILL_FIRE_RL_rl_start_reset || - EN_tlb_flush || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_tlb_refill || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_io_AMO_SC_req || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_io_AMO_op_req ; - - // register rg_word64_set_in_cache - assign rg_word64_set_in_cache$D_IN = - MUX_ram_word64_set$b_put_1__SEL_2 ? - MUX_ram_word64_set$b_put_2__VAL_2 : - MUX_ram_word64_set$b_put_2__VAL_4 ; - assign rg_word64_set_in_cache$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule f_pte_writebacks - assign f_pte_writebacks$D_IN = { tlb$lookup[63:0], value__h6977 } ; - assign f_pte_writebacks$ENQ = MUX_tlb$insert_1__SEL_1 ; - assign f_pte_writebacks$DEQ = WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign f_pte_writebacks$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = !EN_server_reset_request_put ; - assign f_reset_reqs$ENQ = - EN_server_reset_request_put || EN_server_flush_request_put ; - assign f_reset_reqs$DEQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ; - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign f_reset_rsps$DEQ = - EN_server_flush_response_get || EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule ram_state_and_ctag_cset - assign ram_state_and_ctag_cset$ADDRA = - WILL_FIRE_RL_rl_start_cache_refill ? - rg_addr[11:6] : - rg_cset_in_cache ; - assign ram_state_and_ctag_cset$ADDRB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - req_addr[11:6] : - rg_addr[11:6] ; - assign ram_state_and_ctag_cset$DIA = - WILL_FIRE_RL_rl_start_cache_refill ? - MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 : - 53'h0AAAAAAAAAAAAA ; - assign ram_state_and_ctag_cset$DIB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - 53'h0AAAAAAAAAAAAA /* unspecified value */ : - 53'h0AAAAAAAAAAAAA /* unspecified value */ ; - assign ram_state_and_ctag_cset$WEA = 1'd1 ; - assign ram_state_and_ctag_cset$WEB = 1'd0 ; - assign ram_state_and_ctag_cset$ENA = - WILL_FIRE_RL_rl_start_cache_refill || WILL_FIRE_RL_rl_reset ; - assign ram_state_and_ctag_cset$ENB = - EN_req && - req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419 || - WILL_FIRE_RL_rl_rereq ; - - // submodule ram_word64_set - assign ram_word64_set$ADDRA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - rg_word64_set_in_cache : - rg_addr[11:3] ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - req_addr or - MUX_ram_word64_set$b_put_1__SEL_2 or - MUX_ram_word64_set$b_put_2__VAL_2 or - WILL_FIRE_RL_rl_rereq or - rg_addr or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_ram_word64_set$b_put_2__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$ADDRB = req_addr[11:3]; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2; - WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3]; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4; - default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ; - endcase - end - assign ram_word64_set$DIA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - master_xactor_rg_rd_data[66:3] : - MUX_ram_word64_set$a_put_3__VAL_2 ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - MUX_ram_word64_set$b_put_1__SEL_2 or - WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_rereq: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - default: ram_word64_set$DIB = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign ram_word64_set$WEA = 1'd1 ; - assign ram_word64_set$WEB = 1'd0 ; - assign ram_word64_set$ENA = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d639 ; - assign ram_word64_set$ENB = - EN_req && - req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = - (rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8) ? - _theResult___fst__h6279 : - rg_addr ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule tlb - assign tlb$insert_asid = rg_satp[59:44] ; - always@(MUX_tlb$insert_1__SEL_1 or - tlb$lookup or - MUX_tlb$insert_1__SEL_2 or - MUX_tlb$insert_1__SEL_3 or MUX_tlb$insert_1__SEL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_tlb$insert_1__SEL_1: tlb$insert_level = tlb$lookup[65:64]; - MUX_tlb$insert_1__SEL_2: tlb$insert_level = 2'd2; - MUX_tlb$insert_1__SEL_3: tlb$insert_level = 2'd1; - MUX_tlb$insert_1__SEL_4: tlb$insert_level = 2'd0; - default: tlb$insert_level = 2'b10 /* unspecified value */ ; - endcase - end - assign tlb$insert_pte = - (MUX_tlb$insert_1__SEL_2 || MUX_tlb$insert_1__SEL_3 || - MUX_tlb$insert_1__SEL_4) ? - master_xactor_rg_rd_data[66:3] : - value__h6977 ; - assign tlb$insert_pte_pa = - MUX_tlb$insert_1__SEL_1 ? tlb$lookup[63:0] : rg_pte_pa ; - assign tlb$insert_vpn = rg_addr[38:12] ; - assign tlb$lookup_asid = rg_satp[59:44] ; - assign tlb$lookup_vpn = rg_addr[38:12] ; - assign tlb$EN_flush = WILL_FIRE_RL_rl_start_reset || EN_tlb_flush ; - assign tlb$EN_insert = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 || - WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971 || - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006 || - WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) ; - - // remaining internal signals - assign IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293 = - (x1_avValue_pa__h6190[2:0] == 3'h0) ? - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 : - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d292 ; - assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577 = - (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299 = - (rg_addr[2:0] == 3'h0) ? ld_val__h29543 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217 = - (rg_addr[2:0] == 3'h0) ? - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 : - rg_addr[2:0] != 3'h4 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 ; - assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 = - (rg_addr[2:0] == 3'h0) ? word64__h7498 : 64'd0 ; - assign IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 = - (rg_f3 == 3'b010) ? - { {32{rg_st_amo_val_BITS_31_TO_0__q32[31]}}, - rg_st_amo_val_BITS_31_TO_0__q32 } : - rg_st_amo_val ; - assign IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d305 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - !ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 || - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 : - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d304 ; - assign IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d399 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 5'd9 : - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d398 ; - assign IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d304 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - rg_op_6_EQ_2_9_AND_rg_amo_funct7_1_BITS_6_TO_2_ETC___d248 : - !ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 && - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 && - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 ; - assign IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d398 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - 5'd12 : - ((!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) ? - 5'd9 : - 5'd12) ; - assign IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d787 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - mem_req_wr_data_wdata__h18986 : - mem_req_wr_data_wdata__h22422 ; - assign IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d401 = - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ? - 5'd4 : - ((dmem_not_imem && !soc_map$m_is_mem_addr) ? - 5'd13 : - IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d399) ; - assign IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 = - x1_avValue_pa__h6190 == rg_lrsc_pa ; - assign NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284 = - x1_avValue_pa__h6190[2:0] != 3'h7 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289 = - x1_avValue_pa__h6190[2:0] != 3'h6 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d292 = - x1_avValue_pa__h6190[2:0] != 3'h4 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_cfg_verbosity_read__8_ULE_2_060___d1061 = cfg_verbosity > 4'd2 ; - assign NOT_cfg_verbosity_read__8_ULT_2_05___d406 = cfg_verbosity >= 4'd2 ; - assign NOT_dmem_not_imem_01_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d341 = - !dmem_not_imem && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb$lookup[69] ; - assign NOT_dmem_not_imem_01_OR_NOT_rg_op_6_EQ_0_7_8_A_ETC___d108 = - !dmem_not_imem || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - !tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d624 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - rg_op != 2'd1 && ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d637 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d635 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d764 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d762 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d798 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d816 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d855 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d853 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d860 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d858 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d866 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d864 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d874 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d872 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d878 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634 ; - assign NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d921 = - master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - ((!master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4]) ? - !master_xactor_crg_rd_addr_full$port2__read : - master_xactor_rg_rd_data[30:22] != 9'd0 || - master_xactor_rg_rd_data[21:13] != 9'd0 || - tlb$RDY_insert) ; - assign NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d984 = - master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - ((!master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4]) ? - !master_xactor_crg_rd_addr_full$port2__read : - master_xactor_rg_rd_data[21:13] != 9'd0 || tlb$RDY_insert) ; - assign NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928 = - !master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - (master_xactor_rg_rd_data[30:22] != 9'd0 || - master_xactor_rg_rd_data[21:13] != 9'd0) || - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990 = - !master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[21:13] != 9'd0 || - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 = - !ram_state_and_ctag_cset$DOB[52] || !rg_priv_9_ULE_0b1___d60 || - rg_satp[63:60] != 4'd8 || - tlb$RDY_lookup ; - assign NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d437 = - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 ; - assign NOT_req_f3_BITS_1_TO_0_389_EQ_0b0_390_391_AND__ETC___d1410 = - req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && - (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && - (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; - assign NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294 = - rg_f3 != 3'b011 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_rg_op_6_EQ_0_7_8_AND_NOT_rg_op_6_EQ_2_9_0__ETC___d392 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d446 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d761 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d853 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d858 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d864 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d872 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d632 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d759 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d819 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d825 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d831 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d837 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348 = - (rg_priv != 2'b0 || tlb$lookup[70]) && - (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) && - (NOT_dmem_not_imem_01_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d341 || - dmem_not_imem_AND_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_ETC___d343 || - dmem_not_imem && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - tlb$lookup[68]) ; - assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371 = - (rg_priv != 2'b0 || tlb$lookup[70]) && - (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) && - dmem_not_imem && - tlb$lookup[68] ; - assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d409 = - (rg_priv != 2'b0 || tlb$lookup[70]) && - (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) && - tlb$lookup[72] && - !pte___2__h6652[7] && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ; - assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d583 = - (rg_priv != 2'b0 || tlb$lookup[70]) && - (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) && - (!dmem_not_imem && tlb$lookup[69] || - dmem_not_imem && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106) ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d142 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d307 = - (NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d142 || - tlb$RDY_insert && tlb$RDY_lookup && f_pte_writebacks$FULL_N) && - (dmem_not_imem && !soc_map$m_is_mem_addr || - IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d305) ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d353 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130] && - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348 && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d368 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348 && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d421 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d428 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - (rg_priv != 2'b0 || tlb$lookup[70]) && - (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) && - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d424 && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d431 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d428 && - dmem_not_imem && - !soc_map$m_is_mem_addr && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d449 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d458 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15348) ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d458 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d583 && - tlb$lookup[72] ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d588 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d597 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d604 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d610 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d607 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d616 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7_1_BITS_6_TO_2_2_EQ_0b10_3_AND_NO_ETC___d613 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371 && - tlb$lookup[72] && - tlb$lookup[73] ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d624 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d639 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d637 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d766 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d764 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d771 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d767 || - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634) ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d771 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d800 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d798 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d806 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - rg_lrsc_valid && - !rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d812 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !rg_lrsc_valid && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d818 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d816 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d823 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d819 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d823 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d829 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d825 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d835 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d831 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d835 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d841 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d837 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d841 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d849 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15348 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d849 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d857 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d855 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d860 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d866 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d876 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d874 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d880 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d878 ; - assign NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123 = - !tlb$lookup[72] || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - !tlb$lookup[73] ; - assign NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139 = - !tlb$lookup[72] || !tlb$lookup[73] || pte___2__h6652[7] || - rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ; - assign _theResult___fst__h6279 = - tlb$lookup[130] ? _theResult___fst__h6350 : rg_addr ; - assign _theResult___fst__h6350 = - (rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) ? - rg_addr : - _theResult___fst__h6654 ; - assign _theResult___snd_fst__h18994 = rg_st_amo_val << shift_bits__h18787 ; - assign _theResult___snd_fst__h22430 = - new_st_val__h19441 << shift_bits__h18787 ; - assign _theResult___snd_fst__h31152 = rg_st_amo_val << shift_bits__h32449 ; - assign _theResult___snd_fst__h32656 = st_val__h32393 << shift_bits__h32449 ; - assign _theResult___snd_fst__h6281 = - tlb$lookup[130] ? - _theResult___snd_fst__h6352 : - tlb$lookup[129:66] ; - assign _theResult___snd_fst__h6352 = - (rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) ? - tlb$lookup[129:66] : - _theResult___snd_fst__h6883 ; - assign _theResult___snd_fst__h6883 = - (!pte___2__h6652[7] && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010)) ? - pte___1__h6960 : - pte___2__h6652 ; - assign access_exc_code__h3151 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd5 : - 4'd7) : - 4'd1 ; - assign b__h23216 = - ctr_wr_rsps_pending_crg$EN_port0__write ? - ctr_wr_rsps_pending_crg$port0__write_1 : - ctr_wr_rsps_pending_crg ; - assign cfg_verbosity_read__8_ULE_1___d19 = cfg_verbosity <= 4'd1 ; - assign cline_fabric_addr__h26510 = { rg_pa[63:6], 6'd0 } ; - assign dmem_not_imem_AND_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_ETC___d343 = - dmem_not_imem && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 ; - assign dmem_not_imem_OR_NOT_rg_op_6_EQ_0_7_8_AND_NOT__ETC___d100 = - dmem_not_imem || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - !tlb$lookup[69] ; - assign exc_code___1__h6552 = x1_avValue_exc_code__h6191 ; - assign ld_val9543_BITS_15_TO_0__q37 = ld_val__h29543[15:0] ; - assign ld_val9543_BITS_15_TO_8__q39 = ld_val__h29543[15:8] ; - assign ld_val9543_BITS_23_TO_16__q40 = ld_val__h29543[23:16] ; - assign ld_val9543_BITS_31_TO_0__q38 = ld_val__h29543[31:0] ; - assign ld_val9543_BITS_31_TO_16__q41 = ld_val__h29543[31:16] ; - assign ld_val9543_BITS_31_TO_24__q42 = ld_val__h29543[31:24] ; - assign ld_val9543_BITS_39_TO_32__q43 = ld_val__h29543[39:32] ; - assign ld_val9543_BITS_47_TO_32__q44 = ld_val__h29543[47:32] ; - assign ld_val9543_BITS_47_TO_40__q46 = ld_val__h29543[47:40] ; - assign ld_val9543_BITS_55_TO_48__q47 = ld_val__h29543[55:48] ; - assign ld_val9543_BITS_63_TO_32__q45 = ld_val__h29543[63:32] ; - assign ld_val9543_BITS_63_TO_48__q48 = ld_val__h29543[63:48] ; - assign ld_val9543_BITS_63_TO_56__q49 = ld_val__h29543[63:56] ; - assign ld_val9543_BITS_7_TO_0__q36 = ld_val__h29543[7:0] ; - assign lev_0_pte_pa__h25314 = lev_1_PTN_pa__h24255 + vpn_0_pa__h25313 ; - assign lev_0_pte_pa_w64_fa__h25316 = { lev_0_pte_pa__h25314[63:3], 3'b0 } ; - assign lev_1_PTN_pa__h24255 = { 8'd0, x__h24360 } ; - assign lev_1_pte_pa__h24257 = lev_1_PTN_pa__h24255 + vpn_1_pa__h24256 ; - assign lev_1_pte_pa_w64_fa__h24259 = { lev_1_pte_pa__h24257[63:3], 3'b0 } ; - assign lev_2_pte_pa__h23315 = satp_pa__h2470 + vpn_2_pa__h23314 ; - assign lev_2_pte_pa_w64_fa__h23317 = { lev_2_pte_pa__h23315[63:3], 3'b0 } ; - assign lrsc_result__h15348 = - !rg_lrsc_valid || - !rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234 ; - assign master_xactor_crg_rd_data_full_port1__read__96_ETC___d1222 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[21:13] == 9'd0 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[21:13] == 9'd0 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[21:13] != 9'd0 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - (!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5]) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - (master_xactor_rg_rd_data[30:22] != 9'd0 || - master_xactor_rg_rd_data[21:13] != 9'd0) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[30:22] == 9'd0 && - master_xactor_rg_rd_data[21:13] == 9'd0 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[30:22] == 9'd0 && - master_xactor_rg_rd_data[21:13] == 9'd0 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_BITS_10_TO_3__q1 = - master_xactor_rg_rd_data[10:3] ; - assign master_xactor_rg_rd_data_BITS_18_TO_11__q4 = - master_xactor_rg_rd_data[18:11] ; - assign master_xactor_rg_rd_data_BITS_18_TO_3__q3 = - master_xactor_rg_rd_data[18:3] ; - assign master_xactor_rg_rd_data_BITS_26_TO_19__q5 = - master_xactor_rg_rd_data[26:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_19__q6 = - master_xactor_rg_rd_data[34:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_27__q7 = - master_xactor_rg_rd_data[34:27] ; - assign master_xactor_rg_rd_data_BITS_34_TO_3__q2 = - master_xactor_rg_rd_data[34:3] ; - assign master_xactor_rg_rd_data_BITS_42_TO_35__q8 = - master_xactor_rg_rd_data[42:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_35__q9 = - master_xactor_rg_rd_data[50:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_43__q11 = - master_xactor_rg_rd_data[50:43] ; - assign master_xactor_rg_rd_data_BITS_58_TO_51__q12 = - master_xactor_rg_rd_data[58:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_35__q10 = - master_xactor_rg_rd_data[66:35] ; - assign master_xactor_rg_rd_data_BITS_66_TO_51__q13 = - master_xactor_rg_rd_data[66:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_59__q14 = - master_xactor_rg_rd_data[66:59] ; - assign new_st_val__h19441 = - (rg_f3 == 3'b010) ? - new_st_val__h19723 : - _theResult_____2__h19719 ; - assign new_st_val__h19723 = { 32'd0, _theResult_____2__h19719[31:0] } ; - assign new_st_val__h19814 = - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 + - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ; - assign new_st_val__h20794 = w1__h19711 ^ w2__h32667 ; - assign new_st_val__h20798 = w1__h19711 & w2__h32667 ; - assign new_st_val__h20802 = w1__h19711 | w2__h32667 ; - assign new_st_val__h20806 = - (w1__h19711 < w2__h32667) ? w1__h19711 : w2__h32667 ; - assign new_st_val__h20811 = - (w1__h19711 <= w2__h32667) ? w2__h32667 : w1__h19711 ; - assign new_st_val__h20817 = - ((IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 ^ - 64'h8000000000000000) < - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^ - 64'h8000000000000000)) ? - w1__h19711 : - w2__h32667 ; - assign new_st_val__h20822 = - ((IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 ^ - 64'h8000000000000000) <= - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^ - 64'h8000000000000000)) ? - w2__h32667 : - w1__h19711 ; - assign new_st_val__h32677 = { 32'd0, _theResult_____2__h32673[31:0] } ; - assign new_st_val__h32768 = - new_ld_val__h32381 + - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ; - assign new_st_val__h34628 = w1__h32665 ^ w2__h32667 ; - assign new_st_val__h34632 = w1__h32665 & w2__h32667 ; - assign new_st_val__h34636 = w1__h32665 | w2__h32667 ; - assign new_st_val__h34640 = - (w1__h32665 < w2__h32667) ? w1__h32665 : w2__h32667 ; - assign new_st_val__h34645 = - (w1__h32665 <= w2__h32667) ? w2__h32667 : w1__h32665 ; - assign new_st_val__h34651 = - ((new_ld_val__h32381 ^ 64'h8000000000000000) < - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^ - 64'h8000000000000000)) ? - w1__h32665 : - w2__h32667 ; - assign new_st_val__h34656 = - ((new_ld_val__h32381 ^ 64'h8000000000000000) <= - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^ - 64'h8000000000000000)) ? - w2__h32667 : - w1__h32665 ; - assign new_value679_BITS_31_TO_0__q31 = new_value__h7679[31:0] ; - assign pa___1__h6660 = { 8'd0, x__h6663 } ; - assign pa___1__h6709 = { 8'd0, x__h6712 } ; - assign pa___1__h6778 = { 8'd0, x__h6781 } ; - assign pte___1__h6932 = { tlb$lookup[129:73], 1'd1, tlb$lookup[71:66] } ; - assign pte___1__h6960 = - { pte___2__h6652[63:8], 1'd1, pte___2__h6652[6:0] } ; - assign pte___2__h6652 = - tlb$lookup[72] ? tlb$lookup[129:66] : pte___1__h6932 ; - assign ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 = - ram_state_and_ctag_cset$DOB[51:0] == - x1_avValue_pa__h6190[63:12] ; - assign ram_state_and_ctag_cset_b_read__73_BIT_52_74_A_ETC___d438 = - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d437 ; - assign req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419 = - req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || - req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || - req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; - assign result__h14088 = - { {56{word64498_BITS_15_TO_8__q18[7]}}, - word64498_BITS_15_TO_8__q18 } ; - assign result__h14116 = - { {56{word64498_BITS_23_TO_16__q19[7]}}, - word64498_BITS_23_TO_16__q19 } ; - assign result__h14144 = - { {56{word64498_BITS_31_TO_24__q21[7]}}, - word64498_BITS_31_TO_24__q21 } ; - assign result__h14172 = - { {56{word64498_BITS_39_TO_32__q22[7]}}, - word64498_BITS_39_TO_32__q22 } ; - assign result__h14200 = - { {56{word64498_BITS_47_TO_40__q25[7]}}, - word64498_BITS_47_TO_40__q25 } ; - assign result__h14228 = - { {56{word64498_BITS_55_TO_48__q26[7]}}, - word64498_BITS_55_TO_48__q26 } ; - assign result__h14256 = - { {56{word64498_BITS_63_TO_56__q28[7]}}, - word64498_BITS_63_TO_56__q28 } ; - assign result__h14301 = { 56'd0, word64__h7498[7:0] } ; - assign result__h14329 = { 56'd0, word64__h7498[15:8] } ; - assign result__h14357 = { 56'd0, word64__h7498[23:16] } ; - assign result__h14385 = { 56'd0, word64__h7498[31:24] } ; - assign result__h14413 = { 56'd0, word64__h7498[39:32] } ; - assign result__h14441 = { 56'd0, word64__h7498[47:40] } ; - assign result__h14469 = { 56'd0, word64__h7498[55:48] } ; - assign result__h14497 = { 56'd0, word64__h7498[63:56] } ; - assign result__h14542 = - { {48{word64498_BITS_15_TO_0__q16[15]}}, - word64498_BITS_15_TO_0__q16 } ; - assign result__h14570 = - { {48{word64498_BITS_31_TO_16__q20[15]}}, - word64498_BITS_31_TO_16__q20 } ; - assign result__h14598 = - { {48{word64498_BITS_47_TO_32__q23[15]}}, - word64498_BITS_47_TO_32__q23 } ; - assign result__h14626 = - { {48{word64498_BITS_63_TO_48__q27[15]}}, - word64498_BITS_63_TO_48__q27 } ; - assign result__h14667 = { 48'd0, word64__h7498[15:0] } ; - assign result__h14695 = { 48'd0, word64__h7498[31:16] } ; - assign result__h14723 = { 48'd0, word64__h7498[47:32] } ; - assign result__h14751 = { 48'd0, word64__h7498[63:48] } ; - assign result__h14792 = - { {32{word64498_BITS_31_TO_0__q17[31]}}, - word64498_BITS_31_TO_0__q17 } ; - assign result__h14820 = - { {32{word64498_BITS_63_TO_32__q24[31]}}, - word64498_BITS_63_TO_32__q24 } ; - assign result__h14859 = { 32'd0, word64__h7498[31:0] } ; - assign result__h14887 = { 32'd0, word64__h7498[63:32] } ; - assign result__h29603 = - { {56{master_xactor_rg_rd_data_BITS_10_TO_3__q1[7]}}, - master_xactor_rg_rd_data_BITS_10_TO_3__q1 } ; - assign result__h29633 = - { {56{master_xactor_rg_rd_data_BITS_18_TO_11__q4[7]}}, - master_xactor_rg_rd_data_BITS_18_TO_11__q4 } ; - assign result__h29660 = - { {56{master_xactor_rg_rd_data_BITS_26_TO_19__q5[7]}}, - master_xactor_rg_rd_data_BITS_26_TO_19__q5 } ; - assign result__h29687 = - { {56{master_xactor_rg_rd_data_BITS_34_TO_27__q7[7]}}, - master_xactor_rg_rd_data_BITS_34_TO_27__q7 } ; - assign result__h29714 = - { {56{master_xactor_rg_rd_data_BITS_42_TO_35__q8[7]}}, - master_xactor_rg_rd_data_BITS_42_TO_35__q8 } ; - assign result__h29741 = - { {56{master_xactor_rg_rd_data_BITS_50_TO_43__q11[7]}}, - master_xactor_rg_rd_data_BITS_50_TO_43__q11 } ; - assign result__h29768 = - { {56{master_xactor_rg_rd_data_BITS_58_TO_51__q12[7]}}, - master_xactor_rg_rd_data_BITS_58_TO_51__q12 } ; - assign result__h29795 = - { {56{master_xactor_rg_rd_data_BITS_66_TO_59__q14[7]}}, - master_xactor_rg_rd_data_BITS_66_TO_59__q14 } ; - assign result__h29839 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h29866 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h29893 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h29920 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h29947 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h29974 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h30001 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h30028 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h30072 = - { {48{master_xactor_rg_rd_data_BITS_18_TO_3__q3[15]}}, - master_xactor_rg_rd_data_BITS_18_TO_3__q3 } ; - assign result__h30099 = - { {48{master_xactor_rg_rd_data_BITS_34_TO_19__q6[15]}}, - master_xactor_rg_rd_data_BITS_34_TO_19__q6 } ; - assign result__h30126 = - { {48{master_xactor_rg_rd_data_BITS_50_TO_35__q9[15]}}, - master_xactor_rg_rd_data_BITS_50_TO_35__q9 } ; - assign result__h30153 = - { {48{master_xactor_rg_rd_data_BITS_66_TO_51__q13[15]}}, - master_xactor_rg_rd_data_BITS_66_TO_51__q13 } ; - assign result__h30193 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h30220 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h30247 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h30274 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h30314 = - { {32{master_xactor_rg_rd_data_BITS_34_TO_3__q2[31]}}, - master_xactor_rg_rd_data_BITS_34_TO_3__q2 } ; - assign result__h30341 = - { {32{master_xactor_rg_rd_data_BITS_66_TO_35__q10[31]}}, - master_xactor_rg_rd_data_BITS_66_TO_35__q10 } ; - assign result__h30379 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h30406 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; - assign result__h32856 = - { {56{ld_val9543_BITS_7_TO_0__q36[7]}}, - ld_val9543_BITS_7_TO_0__q36 } ; - assign result__h33764 = - { {56{ld_val9543_BITS_15_TO_8__q39[7]}}, - ld_val9543_BITS_15_TO_8__q39 } ; - assign result__h33792 = - { {56{ld_val9543_BITS_23_TO_16__q40[7]}}, - ld_val9543_BITS_23_TO_16__q40 } ; - assign result__h33820 = - { {56{ld_val9543_BITS_31_TO_24__q42[7]}}, - ld_val9543_BITS_31_TO_24__q42 } ; - assign result__h33848 = - { {56{ld_val9543_BITS_39_TO_32__q43[7]}}, - ld_val9543_BITS_39_TO_32__q43 } ; - assign result__h33876 = - { {56{ld_val9543_BITS_47_TO_40__q46[7]}}, - ld_val9543_BITS_47_TO_40__q46 } ; - assign result__h33904 = - { {56{ld_val9543_BITS_55_TO_48__q47[7]}}, - ld_val9543_BITS_55_TO_48__q47 } ; - assign result__h33932 = - { {56{ld_val9543_BITS_63_TO_56__q49[7]}}, - ld_val9543_BITS_63_TO_56__q49 } ; - assign result__h33977 = { 56'd0, ld_val__h29543[7:0] } ; - assign result__h34005 = { 56'd0, ld_val__h29543[15:8] } ; - assign result__h34033 = { 56'd0, ld_val__h29543[23:16] } ; - assign result__h34061 = { 56'd0, ld_val__h29543[31:24] } ; - assign result__h34089 = { 56'd0, ld_val__h29543[39:32] } ; - assign result__h34117 = { 56'd0, ld_val__h29543[47:40] } ; - assign result__h34145 = { 56'd0, ld_val__h29543[55:48] } ; - assign result__h34173 = { 56'd0, ld_val__h29543[63:56] } ; - assign result__h34218 = - { {48{ld_val9543_BITS_15_TO_0__q37[15]}}, - ld_val9543_BITS_15_TO_0__q37 } ; - assign result__h34246 = - { {48{ld_val9543_BITS_31_TO_16__q41[15]}}, - ld_val9543_BITS_31_TO_16__q41 } ; - assign result__h34274 = - { {48{ld_val9543_BITS_47_TO_32__q44[15]}}, - ld_val9543_BITS_47_TO_32__q44 } ; - assign result__h34302 = - { {48{ld_val9543_BITS_63_TO_48__q48[15]}}, - ld_val9543_BITS_63_TO_48__q48 } ; - assign result__h34343 = { 48'd0, ld_val__h29543[15:0] } ; - assign result__h34371 = { 48'd0, ld_val__h29543[31:16] } ; - assign result__h34399 = { 48'd0, ld_val__h29543[47:32] } ; - assign result__h34427 = { 48'd0, ld_val__h29543[63:48] } ; - assign result__h34468 = - { {32{ld_val9543_BITS_31_TO_0__q38[31]}}, - ld_val9543_BITS_31_TO_0__q38 } ; - assign result__h34496 = - { {32{ld_val9543_BITS_63_TO_32__q45[31]}}, - ld_val9543_BITS_63_TO_32__q45 } ; - assign result__h34535 = { 32'd0, ld_val__h29543[31:0] } ; - assign result__h34563 = { 32'd0, ld_val__h29543[63:32] } ; - assign result__h7732 = - { {56{word64498_BITS_7_TO_0__q15[7]}}, - word64498_BITS_7_TO_0__q15 } ; - assign rg_amo_funct7_1_BITS_6_TO_2_2_EQ_0b10_3_AND_NO_ETC___d613 = - rg_amo_funct7[6:2] == 5'b00010 && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234 = - rg_lrsc_pa == x1_avValue_pa__h6190 ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d387 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d424 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - tlb$lookup[68] ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d449 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset_b_read__73_BIT_52_74_A_ETC___d438 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d447 ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d588 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d607 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d447 = - rg_op == 2'd1 && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d446 ; - assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d635 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d632 || - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634 ; - assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d762 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d759 || - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d761 ; - assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d767 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) ; - assign rg_op_6_EQ_2_9_AND_rg_amo_funct7_1_BITS_6_TO_2_ETC___d248 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15348 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 ; - assign rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 = - rg_priv == 2'b0 && !tlb$lookup[70] || - rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM || - dmem_not_imem_OR_NOT_rg_op_6_EQ_0_7_8_AND_NOT__ETC___d100 && - NOT_dmem_not_imem_01_OR_NOT_rg_op_6_EQ_0_7_8_A_ETC___d108 && - (!dmem_not_imem || rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - !tlb$lookup[68]) ; - assign rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130 = - rg_priv == 2'b0 && !tlb$lookup[70] || - rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM || - !dmem_not_imem || - !tlb$lookup[68] ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - tlb$lookup[130] && - (rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d309 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - !tlb$lookup[130] || - (rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ? - tlb$RDY_lookup : - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d307) ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d356 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - (rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) && - tlb$lookup[130] ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - tlb$lookup[130] && - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371 && - tlb$lookup[72] && - tlb$lookup[73] && - !pte___2__h6652[7] && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d395 = - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 || - dmem_not_imem && !soc_map$m_is_mem_addr || - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d387 || - NOT_rg_op_6_EQ_0_7_8_AND_NOT_rg_op_6_EQ_2_9_0__ETC___d392 ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - !tlb$lookup[130] || - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d395 ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - tlb$lookup[130] && - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d409 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406 && - dmem_not_imem && - tlb$lookup[68] && - tlb$lookup[73] ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417 = - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406 && - (!dmem_not_imem || !tlb$lookup[68] || !tlb$lookup[73]) ; - assign rg_priv_9_ULE_0b1___d60 = rg_priv <= 2'b01 ; - assign rg_st_amo_val_BITS_31_TO_0__q32 = rg_st_amo_val[31:0] ; - assign rg_state_3_EQ_13_088_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d1090 = - rg_state == 5'd13 && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - b__h23216 == 4'd0 ; - assign rg_state_3_EQ_3_12_AND_NOT_rg_op_6_EQ_0_7_8_AN_ETC___d316 = - rg_state == 5'd3 && - (rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - crg_sb_to_load_delay$port0__write_1 == 11'd0) ; - assign satp_pa__h2470 = { 8'd0, x__h5382 } ; - assign shift_bits__h18787 = { x1_avValue_pa__h6190[2:0], 3'b0 } ; - assign shift_bits__h32449 = { rg_pa[2:0], 3'b0 } ; - assign st_val__h32393 = - (rg_f3 == 3'b010) ? - new_st_val__h32677 : - _theResult_____2__h32673 ; - assign strobe64__h18920 = 8'b00000001 << x1_avValue_pa__h6190[2:0] ; - assign strobe64__h18922 = 8'b00000011 << x1_avValue_pa__h6190[2:0] ; - assign strobe64__h18924 = 8'b00001111 << x1_avValue_pa__h6190[2:0] ; - assign strobe64__h32582 = 8'b00000001 << rg_pa[2:0] ; - assign strobe64__h32584 = 8'b00000011 << rg_pa[2:0] ; - assign strobe64__h32586 = 8'b00001111 << rg_pa[2:0] ; - assign tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 = - tlb$lookup[67] | y__h6478 ; - assign tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 = - tlb$lookup[72] && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - tlb$lookup[73]) ; - assign value__h6977 = - (rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8) ? - _theResult___snd_fst__h6281 : - tlb$lookup[129:66] ; - assign vpn_0_pa__h25313 = { 52'd0, rg_addr[20:12], 3'd0 } ; - assign vpn_1_pa__h24256 = { 52'd0, rg_addr[29:21], 3'd0 } ; - assign vpn_2_pa__h23314 = { 52'd0, rg_addr[38:30], 3'd0 } ; - assign w12661_BITS_31_TO_0__q51 = w1__h32661[31:0] ; - assign w1___1__h19782 = { 32'd0, new_value__h7679[31:0] } ; - assign w1___1__h32736 = { 32'd0, w1__h32661[31:0] } ; - assign w2___1__h32737 = { 32'd0, rg_st_amo_val[31:0] } ; - assign w2__h32667 = (rg_f3 == 3'b010) ? w2___1__h32737 : rg_st_amo_val ; - assign word64498_BITS_15_TO_0__q16 = word64__h7498[15:0] ; - assign word64498_BITS_15_TO_8__q18 = word64__h7498[15:8] ; - assign word64498_BITS_23_TO_16__q19 = word64__h7498[23:16] ; - assign word64498_BITS_31_TO_0__q17 = word64__h7498[31:0] ; - assign word64498_BITS_31_TO_16__q20 = word64__h7498[31:16] ; - assign word64498_BITS_31_TO_24__q21 = word64__h7498[31:24] ; - assign word64498_BITS_39_TO_32__q22 = word64__h7498[39:32] ; - assign word64498_BITS_47_TO_32__q23 = word64__h7498[47:32] ; - assign word64498_BITS_47_TO_40__q25 = word64__h7498[47:40] ; - assign word64498_BITS_55_TO_48__q26 = word64__h7498[55:48] ; - assign word64498_BITS_63_TO_32__q24 = word64__h7498[63:32] ; - assign word64498_BITS_63_TO_48__q27 = word64__h7498[63:48] ; - assign word64498_BITS_63_TO_56__q28 = word64__h7498[63:56] ; - assign word64498_BITS_7_TO_0__q15 = word64__h7498[7:0] ; - assign word64__h7498 = ram_word64_set$DOB & y__h7768 ; - assign x1_avValue_exc_code__h6191 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd13 : - 4'd15) : - 4'd12 ; - assign x1_avValue_pa__h6190 = soc_map$m_is_mem_addr_addr ; - assign x__h15358 = { 63'd0, lrsc_result__h15348 } ; - assign x__h24360 = { master_xactor_rg_rd_data[56:13], 12'b0 } ; - assign x__h5382 = { rg_satp[43:0], 12'b0 } ; - assign x__h6663 = { tlb$lookup[119:76], rg_addr[11:0] } ; - assign x__h6712 = { tlb$lookup[119:85], rg_addr[20:0] } ; - assign x__h6781 = { tlb$lookup[119:94], rg_addr[29:0] } ; - assign y__h6478 = rg_mstatus_MXR & tlb$lookup[69] ; - assign y__h7768 = - {64{ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178}} ; - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h31966 = 3'b0; - 2'b01: value__h31966 = 3'b001; - 2'b10: value__h31966 = 3'b010; - 2'd3: value__h31966 = 3'b011; - endcase - end - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h34992 = 3'b0; - 2'b01: value__h34992 = 3'b001; - 2'b10: value__h34992 = 3'b010; - 2'b11: value__h34992 = 3'b011; - endcase - end - always@(tlb$lookup or - rg_addr or pa___1__h6660 or pa___1__h6709 or pa___1__h6778) - begin - case (tlb$lookup[65:64]) - 2'd0: _theResult___fst__h6654 = pa___1__h6660; - 2'd1: _theResult___fst__h6654 = pa___1__h6709; - 2'd2: _theResult___fst__h6654 = pa___1__h6778; - 2'd3: _theResult___fst__h6654 = rg_addr; - endcase - end - always@(rg_f3 or strobe64__h32582 or strobe64__h32584 or strobe64__h32586) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h32649 = strobe64__h32582; - 2'b01: mem_req_wr_data_wstrb__h32649 = strobe64__h32584; - 2'b10: mem_req_wr_data_wstrb__h32649 = strobe64__h32586; - 2'b11: mem_req_wr_data_wstrb__h32649 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h31152) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h31144 = _theResult___snd_fst__h31152; - 2'd3: mem_req_wr_data_wdata__h31144 = rg_st_amo_val; - endcase - end - always@(rg_f3 or strobe64__h18920 or strobe64__h18922 or strobe64__h18924) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h18987 = strobe64__h18920; - 2'b01: mem_req_wr_data_wstrb__h18987 = strobe64__h18922; - 2'b10: mem_req_wr_data_wstrb__h18987 = strobe64__h18924; - 2'b11: mem_req_wr_data_wstrb__h18987 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h18994) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h18986 = _theResult___snd_fst__h18994; - 2'd3: mem_req_wr_data_wdata__h18986 = rg_st_amo_val; - endcase - end - always@(rg_f3 or rg_priv_9_ULE_0b1___d60 or rg_satp or tlb$RDY_lookup) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01: - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$RDY_lookup; - default: IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 = - rg_f3[1:0] != 2'b10 || !rg_priv_9_ULE_0b1___d60 || - rg_satp[63:60] != 4'd8 || - tlb$RDY_lookup; - endcase - end - always@(rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199) - begin - case (rg_addr[2:0]) - 3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 = - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199; - 3'd7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 = - rg_addr[2:0] != 3'h7 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199; - endcase - end - always@(rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199) - begin - case (rg_addr[2:0]) - 3'h0, 3'h2, 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 = - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 = - rg_addr[2:0] != 3'h6 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199; - endcase - end - always@(rg_f3 or - rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217) - begin - case (rg_f3) - 3'b0, 3'b100: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203; - 3'b001, 3'b101: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211; - 3'b010, 3'b110: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217; - default: IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - rg_f3 != 3'b011 || rg_addr[2:0] != 3'h0 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199; - endcase - end - always@(rg_amo_funct7 or - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225) - begin - case (rg_amo_funct7[6:2]) - 5'b0, 5'b00100, 5'b01000, 5'b01100, 5'b10000, 5'b11000, 5'b11100: - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 = - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225; - default: CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 = - rg_amo_funct7[6:2] != 5'b10100 || - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225; - endcase - end - always@(x1_avValue_pa__h6190 or - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284 or - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285 = - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29; - 3'd7: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285 = - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284; - endcase - end - always@(x1_avValue_pa__h6190 or - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289 or - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0, 3'h2, 3'h4: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290 = - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29; - default: IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290 = - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289; - endcase - end - always@(rg_f3 or - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294 or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285 or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290 or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 = - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294; - endcase - end - always@(rg_addr or - result__h7732 or - result__h14088 or - result__h14116 or - result__h14144 or - result__h14172 or - result__h14200 or result__h14228 or result__h14256) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h7732; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14088; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14116; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14144; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14172; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14200; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14228; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14256; - endcase - end - always@(rg_addr or - result__h14301 or - result__h14329 or - result__h14357 or - result__h14385 or - result__h14413 or - result__h14441 or result__h14469 or result__h14497) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14301; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14329; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14357; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14385; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14413; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14441; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14469; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14497; - endcase - end - always@(rg_addr or - result__h14542 or - result__h14570 or result__h14598 or result__h14626) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 = - result__h14542; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 = - result__h14570; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 = - result__h14598; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 = - result__h14626; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 = - 64'd0; - endcase - end - always@(rg_addr or - result__h14667 or - result__h14695 or result__h14723 or result__h14751) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 = - result__h14667; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 = - result__h14695; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 = - result__h14723; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 = - result__h14751; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 = - 64'd0; - endcase - end - always@(rg_addr or result__h14859 or result__h14887) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562 = - result__h14859; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562 = - result__h14887; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562 = - 64'd0; - endcase - end - always@(rg_addr or result__h14792 or result__h14820) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30 = - result__h14792; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30 = - result__h14820; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562) - begin - case (rg_f3) - 3'b0: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516; - 3'b001: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544; - 3'b010: - new_value__h7679 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30; - 3'b011: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563; - 3'b100: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532; - 3'b101: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552; - 3'b110: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562; - 3'd7: new_value__h7679 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 or - w1___1__h19782 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562) - begin - case (rg_f3) - 3'b0: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516; - 3'b001: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544; - 3'b010: w1__h19711 = w1___1__h19782; - 3'b011: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563; - 3'b100: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532; - 3'b101: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552; - 3'b110: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562; - 3'd7: w1__h19711 = 64'd0; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 = - { ram_word64_set$DOB[63:16], rg_st_amo_val[15:0] }; - 3'h2: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 = - { rg_st_amo_val[15:0], ram_word64_set$DOB[47:0] }; - default: IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 = - ram_word64_set$DOB; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:8], rg_st_amo_val[7:0] }; - 3'h1: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:16], - rg_st_amo_val[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:24], - rg_st_amo_val[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:40], - rg_st_amo_val[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:56], - rg_st_amo_val[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { rg_st_amo_val[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 or - new_value679_BITS_31_TO_0__q31 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516; - 3'b001: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544; - 3'b010: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - { {32{new_value679_BITS_31_TO_0__q31[31]}}, - new_value679_BITS_31_TO_0__q31 }; - 3'b011: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563; - 3'b100: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532; - 3'b101: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552; - 3'b110: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562; - 3'd7: IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h20822 or - new_st_val__h19814 or - w2__h32667 or - new_st_val__h20794 or - new_st_val__h20802 or - new_st_val__h20798 or - new_st_val__h20817 or new_st_val__h20806 or new_st_val__h20811) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h19719 = new_st_val__h19814; - 5'b00001: _theResult_____2__h19719 = w2__h32667; - 5'b00100: _theResult_____2__h19719 = new_st_val__h20794; - 5'b01000: _theResult_____2__h19719 = new_st_val__h20802; - 5'b01100: _theResult_____2__h19719 = new_st_val__h20798; - 5'b10000: _theResult_____2__h19719 = new_st_val__h20817; - 5'b11000: _theResult_____2__h19719 = new_st_val__h20806; - 5'b11100: _theResult_____2__h19719 = new_st_val__h20811; - default: _theResult_____2__h19719 = new_st_val__h20822; - endcase - end - always@(rg_f3 or new_st_val__h19441 or _theResult___snd_fst__h22430) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h22422 = _theResult___snd_fst__h22430; - 2'd3: mem_req_wr_data_wdata__h22422 = new_st_val__h19441; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or new_st_val__h19441) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 = - { ram_word64_set$DOB[63:16], new_st_val__h19441[15:0] }; - 3'h2: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 = - { ram_word64_set$DOB[63:32], - new_st_val__h19441[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 = - { ram_word64_set$DOB[63:48], - new_st_val__h19441[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 = - { new_st_val__h19441[15:0], ram_word64_set$DOB[47:0] }; - default: IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 = - ram_word64_set$DOB; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or new_st_val__h19441) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:8], new_st_val__h19441[7:0] }; - 3'h1: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:16], - new_st_val__h19441[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:24], - new_st_val__h19441[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:32], - new_st_val__h19441[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:40], - new_st_val__h19441[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:48], - new_st_val__h19441[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:56], - new_st_val__h19441[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { new_st_val__h19441[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - { ram_word64_set$DOB[63:32], rg_st_amo_val[31:0] }; - 3'h4: - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - { rg_st_amo_val[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 or - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33 or - rg_st_amo_val) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 = - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33; - 3'b011: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 = - rg_st_amo_val; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or - result__h30193 or - result__h30220 or result__h30247 or result__h30274) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 = - result__h30193; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 = - result__h30220; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 = - result__h30247; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 = - result__h30274; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 = - 64'd0; - endcase - end - always@(rg_addr or - result__h30072 or - result__h30099 or result__h30126 or result__h30153) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 = - result__h30072; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 = - result__h30099; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 = - result__h30126; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 = - result__h30153; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 = - 64'd0; - endcase - end - always@(rg_addr or - result__h29839 or - result__h29866 or - result__h29893 or - result__h29920 or - result__h29947 or - result__h29974 or result__h30001 or result__h30028) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29839; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29866; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29893; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29920; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29947; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29974; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h30001; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h30028; - endcase - end - always@(rg_addr or - result__h29603 or - result__h29633 or - result__h29660 or - result__h29687 or - result__h29714 or - result__h29741 or result__h29768 or result__h29795) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29603; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29633; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29660; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29687; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29714; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29741; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29768; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29795; - endcase - end - always@(rg_addr or result__h30314 or result__h30341) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34 = - result__h30314; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34 = - result__h30341; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34 = - 64'd0; - endcase - end - always@(rg_addr or result__h30379 or result__h30406) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35 = - result__h30379; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35 = - result__h30406; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 or - CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34 or - rg_addr or - master_xactor_rg_rd_data or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 or - CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35) - begin - case (rg_f3) - 3'b0: - ld_val__h29543 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128; - 3'b001: - ld_val__h29543 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156; - 3'b010: - ld_val__h29543 = - CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34; - 3'b011: - ld_val__h29543 = - (rg_addr[2:0] == 3'h0) ? master_xactor_rg_rd_data[66:3] : 64'd0; - 3'b100: - ld_val__h29543 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144; - 3'b101: - ld_val__h29543 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164; - 3'b110: - ld_val__h29543 = - CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35; - 3'd7: ld_val__h29543 = 64'd0; - endcase - end - always@(rg_addr or result__h34535 or result__h34563) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 = - result__h34535; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 = - result__h34563; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 = - 64'd0; - endcase - end - always@(rg_addr or - result__h34343 or - result__h34371 or result__h34399 or result__h34427) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 = - result__h34343; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 = - result__h34371; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 = - result__h34399; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 = - result__h34427; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 = - 64'd0; - endcase - end - always@(rg_addr or - result__h34218 or - result__h34246 or result__h34274 or result__h34302) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 = - result__h34218; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 = - result__h34246; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 = - result__h34274; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 = - result__h34302; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 = - 64'd0; - endcase - end - always@(rg_addr or - result__h32856 or - result__h33764 or - result__h33792 or - result__h33820 or - result__h33848 or - result__h33876 or result__h33904 or result__h33932) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h32856; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33764; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33792; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33820; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33848; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33876; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33904; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33932; - endcase - end - always@(rg_addr or - result__h33977 or - result__h34005 or - result__h34033 or - result__h34061 or - result__h34089 or - result__h34117 or result__h34145 or result__h34173) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h33977; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34005; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34033; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34061; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34089; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34117; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34145; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34173; - endcase - end - always@(rg_addr or result__h34468 or result__h34496) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50 = - result__h34468; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50 = - result__h34496; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298) - begin - case (rg_f3) - 3'b0: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252; - 3'b001: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280; - 3'b010: - w1__h32661 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50; - 3'b011: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299; - 3'b100: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268; - 3'b101: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288; - 3'b110: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298; - 3'd7: w1__h32661 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 or - w1___1__h32736 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298) - begin - case (rg_f3) - 3'b0: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252; - 3'b001: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280; - 3'b010: w1__h32665 = w1___1__h32736; - 3'b011: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299; - 3'b100: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268; - 3'b101: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288; - 3'b110: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298; - 3'd7: w1__h32665 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 or - w12661_BITS_31_TO_0__q51 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298) - begin - case (rg_f3) - 3'b0: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252; - 3'b001: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280; - 3'b010: - new_ld_val__h32381 = - { {32{w12661_BITS_31_TO_0__q51[31]}}, - w12661_BITS_31_TO_0__q51 }; - 3'b011: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299; - 3'b100: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268; - 3'b101: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288; - 3'b110: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298; - 3'd7: new_ld_val__h32381 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h34656 or - new_st_val__h32768 or - w2__h32667 or - new_st_val__h34628 or - new_st_val__h34636 or - new_st_val__h34632 or - new_st_val__h34651 or new_st_val__h34640 or new_st_val__h34645) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h32673 = new_st_val__h32768; - 5'b00001: _theResult_____2__h32673 = w2__h32667; - 5'b00100: _theResult_____2__h32673 = new_st_val__h34628; - 5'b01000: _theResult_____2__h32673 = new_st_val__h34636; - 5'b01100: _theResult_____2__h32673 = new_st_val__h34632; - 5'b10000: _theResult_____2__h32673 = new_st_val__h34651; - 5'b11000: _theResult_____2__h32673 = new_st_val__h34640; - 5'b11100: _theResult_____2__h32673 = new_st_val__h34645; - default: _theResult_____2__h32673 = new_st_val__h34656; - endcase - end - always@(rg_f3 or st_val__h32393 or _theResult___snd_fst__h32656) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h32648 = _theResult___snd_fst__h32656; - 2'd3: mem_req_wr_data_wdata__h32648 = st_val__h32393; - endcase - end - always@(rg_f3 or IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577) - begin - case (rg_f3) - 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: - new_value__h17706 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577; - 3'd7: new_value__h17706 = 64'd0; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or new_st_val__h19441) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - { ram_word64_set$DOB[63:32], new_st_val__h19441[31:0] }; - 3'h4: - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - { new_st_val__h19441[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 or - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52 or - new_st_val__h19441) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 = - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52; - 3'b011: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 = - new_st_val__h19441; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 = - ram_word64_set$DOB; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0; - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_sb_to_load_delay$EN) - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY - crg_sb_to_load_delay$D_IN; - if (ctr_wr_rsps_pending_crg$EN) - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY - ctr_wr_rsps_pending_crg$D_IN; - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_cset_in_cache$EN) - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN; - if (rg_lower_word32_full$EN) - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY - rg_lower_word32_full$D_IN; - if (rg_lrsc_valid$EN) - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; - if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN; - if (rg_amo_funct7$EN) - rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN; - if (rg_error_during_refill$EN) - rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY - rg_error_during_refill$D_IN; - if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN; - if (rg_lower_word32$EN) - rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN; - if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN; - if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN; - if (rg_priv$EN) rg_priv <= `BSV_ASSIGNMENT_DELAY rg_priv$D_IN; - if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN; - if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_st_amo_val$EN) - rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN; - if (rg_word64_set_in_cache$EN) - rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY - rg_word64_set_in_cache$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_sb_to_load_delay = 11'h2AA; - ctr_wr_rsps_pending_crg = 4'hA; - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; - rg_addr = 64'hAAAAAAAAAAAAAAAA; - rg_amo_funct7 = 7'h2A; - rg_cset_in_cache = 6'h2A; - rg_error_during_refill = 1'h0; - rg_exc_code = 4'hA; - rg_f3 = 3'h2; - rg_ld_val = 64'hAAAAAAAAAAAAAAAA; - rg_lower_word32 = 32'hAAAAAAAA; - rg_lower_word32_full = 1'h0; - rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA; - rg_lrsc_valid = 1'h0; - rg_mstatus_MXR = 1'h0; - rg_op = 2'h2; - rg_pa = 64'hAAAAAAAAAAAAAAAA; - rg_priv = 2'h2; - rg_pte_pa = 64'hAAAAAAAAAAAAAAAA; - rg_satp = 64'hAAAAAAAAAAAAAAAA; - rg_sstatus_SUM = 1'h0; - rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; - rg_state = 5'h0A; - rg_word64_set_in_cache = 9'h0AA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - begin - v__h4708 = $stime; - #0; - end - v__h4702 = v__h4708 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h4702, - "D_MMU_Cache", - $signed(32'd64), - $signed(32'd1)); - else - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h4702, - "I_MMU_Cache", - $signed(32'd64), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - !cfg_verbosity_read__8_ULE_1___d19 && - f_reset_reqs$D_OUT) - begin - v__h4809 = $stime; - #0; - end - v__h4803 = v__h4809 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - !cfg_verbosity_read__8_ULE_1___d19 && - f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: Flushed", v__h4803, "D_MMU_Cache"); - else - $display("%0d: %s.rl_reset: Flushed", v__h4803, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_rereq && !cfg_verbosity_read__8_ULE_1___d19) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - rg_addr[11:6], - rg_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h30746 = $stime; - #0; - end - v__h30740 = v__h30746 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h30740, - "D_MMU_Cache", - rg_addr, - rg_ld_val); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h30740, - "I_MMU_Cache", - rg_addr, - rg_ld_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h31644 = $stime; - #0; - end - v__h31638 = v__h31644 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h31638, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h31638, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19) - $display(" FAIL due to I/O address."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h4339 = $stime; - #0; - end - v__h4333 = v__h4339 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_start_reset", v__h4333, "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_reset", v__h4333, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h5262 = $stime; - #0; - end - v__h5256 = v__h5262 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h5256, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h5256, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - rg_satp[63:60] != 4'd0) - $display(" Priv:%0d SATP:{mode %0d asid %0h pa %0h} VA:%0h.%0h.%0h", - rg_priv, - rg_satp[63:60], - rg_satp[59:44], - satp_pa__h2470, - rg_addr[29:21], - rg_addr[20:12], - rg_addr[11:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", - rg_addr[63:12], - rg_addr[11:6], - rg_addr[5:3], - rg_addr[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" CSet 0x%0x: (state, tag):", rg_addr[11:6]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" ("); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - ram_state_and_ctag_cset$DOB[52]) - $write("CTAG_CLEAN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - !ram_state_and_ctag_cset$DOB[52]) - $write("CTAG_EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - ram_state_and_ctag_cset$DOB[52]) - $write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - !ram_state_and_ctag_cset$DOB[52]) - $write(", --"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(")"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" TLB result: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d353) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d356) - $write("VM_XLATE_EXCEPTION"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - rg_priv_9_ULE_0b1___d60 && - rg_satp[63:60] == 4'd8 && - !tlb$lookup[130]) - $write("VM_XLATE_TLB_MISS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", x1_avValue_exc_code__h6191); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "pte_modified: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d368) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", value__h6977, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $display(" fa_record_pte_A_D_updates:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("TLB_Lookup_Result { ", "hit: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", tlb$lookup[129:66]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pte_level: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", tlb$lookup[65:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pte_pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", tlb$lookup[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417) - $write("VM_XLATE_EXCEPTION"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", x1_avValue_exc_code__h6191); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pte_modified: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", value__h6977, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d431) - $display(" => IO_REQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591) - begin - v__h14971 = $stime; - #0; - end - v__h14965 = v__h14971 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h14965, - "D_MMU_Cache", - rg_addr, - word64__h7498, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h14965, - "I_MMU_Cache", - rg_addr, - word64__h7498, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d604) - $display(" AMO LR: reserving PA 0x%0h", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591) - $display(" Read-hit: addr 0x%0h word64 0x%0h", - rg_addr, - word64__h7498); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d610) - $display(" Read Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d616) - $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", - rg_lrsc_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d800) - $display(" ST: cancelling LR/SC reservation for PA", - x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d806) - $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", - rg_lrsc_pa, - x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d812) - $display(" AMO SC: fail due to invalid LR/SC reservation"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d818) - $display(" AMO SC result = %0d", lrsc_result__h15348); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824) - $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", - x1_avValue_pa__h6190, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824) - $write(" 0x%0x", - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d829) - $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", - x1_avValue_pa__h6190, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842) - begin - v__h19190 = $stime; - #0; - end - v__h19184 = v__h19190 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842) - $display("%0d: ERROR: CreditCounter: overflow", v__h19184); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", value__h34992); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", mem_req_wr_data_wdata__h18986); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", mem_req_wr_data_wstrb__h18987); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $display(" => rl_write_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850) - begin - v__h18615 = $stime; - #0; - end - v__h18609 = v__h18615 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h18609, - "D_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h18609, - "I_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850) - $display(" AMO SC: Fail response for addr 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d857) - $display(" AMO Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", - rg_addr, - rg_amo_funct7, - rg_f3, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $display(" PA 0x%0h ", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $display(" Cache word64 0x%0h, load-result 0x%0h", - word64__h7498, - word64__h7498); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $display(" 0x%0h op 0x%0h -> 0x%0h", - word64__h7498, - word64__h7498, - new_st_val__h19441); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(" 0x%0x", - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868) - begin - v__h22626 = $stime; - #0; - end - v__h22620 = v__h22626 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868) - $display("%0d: ERROR: CreditCounter: overflow", v__h22620); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", value__h34992); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", mem_req_wr_data_wdata__h22422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", mem_req_wr_data_wstrb__h18987); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d876) - $display(" AMO_op: cancelling LR/SC reservation for PA", - x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - begin - v__h24225 = $stime; - #0; - end - v__h24219 = v__h24225 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h24219, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - else - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h24219, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - begin - v__h23982 = $stime; - #0; - end - v__h23976 = v__h23982 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - if (dmem_not_imem) - $display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1", - v__h23976, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1", - v__h23976, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $display(" Req for level 1 PTE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", lev_1_pte_pa_w64_fa__h24259); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963) - begin - v__h24536 = $stime; - #0; - end - v__h24530 = v__h24536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h", - v__h24530, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h", - v__h24530, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - (master_xactor_rg_rd_data[30:22] != 9'd0 || - master_xactor_rg_rd_data[21:13] != 9'd0)) - $display(" Invalid PTE: PPN[1] or PPN[0] is not zero; page fault %0d", - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975) - begin - v__h24648 = $stime; - #0; - end - v__h24642 = v__h24648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage", - v__h24642, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage", - v__h24642, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975) - $display(" Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h24255); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h24154 = $stime; - #0; - end - v__h24148 = v__h24154 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h24148, - "D_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - else - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h24148, - "I_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - begin - v__h25282 = $stime; - #0; - end - v__h25276 = v__h25282 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h25276, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h25276, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - begin - v__h25042 = $stime; - #0; - end - v__h25036 = v__h25042 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - if (dmem_not_imem) - $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0", - v__h25036, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0", - v__h25036, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $display(" Req for level 0 PTE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", lev_0_pte_pa_w64_fa__h25316); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010) - begin - v__h25705 = $stime; - #0; - end - v__h25699 = v__h25705 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage", - v__h25699, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage", - v__h25699, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010) - $display(" Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h24255); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016) - begin - v__h25593 = $stime; - #0; - end - v__h25587 = v__h25593 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h", - v__h25587, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h", - v__h25587, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[21:13] != 9'd0) - $display(" Invalid PTE: PPN [0] is not zero; page fault %0d", - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h25211 = $stime; - #0; - end - v__h25205 = v__h25211 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h25205, - "D_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h25205, - "I_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - begin - v__h26177 = $stime; - #0; - end - v__h26171 = v__h26177 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h26171, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h26171, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - begin - v__h26248 = $stime; - #0; - end - v__h26242 = v__h26248 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d", - v__h26242, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d", - v__h26242, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041) - begin - v__h26330 = $stime; - #0; - end - v__h26324 = v__h26330 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE", - v__h26324, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE", - v__h26324, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041) - $display(" Addr Space page pa: 0x%0h", lev_1_PTN_pa__h24255); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h26106 = $stime; - #0; - end - v__h26100 = v__h26106 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h26100, - "D_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h26100, - "I_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - begin - v__h27239 = $stime; - #0; - end - v__h27233 = v__h27239 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h27233, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h27233, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h27461 = $stime; - #0; - end - v__h27455 = v__h27461 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h27455, - "D_MMU_Cache", - access_exc_code__h3151); - else - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h27455, - "I_MMU_Cache", - access_exc_code__h3151); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 && - (master_xactor_rg_rd_data[2:1] != 2'b0 || rg_error_during_refill) && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" => MODULE_EXCEPTION_RSP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !rg_error_during_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" => CACHE_REREQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", - rg_word64_set_in_cache, - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(" 0x%0x", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h29434 = $stime; - #0; - end - v__h29428 = v__h29434 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h29428, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h29428, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h30534 = $stime; - #0; - end - v__h30528 = v__h30534 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h30528, - "D_MMU_Cache", - rg_addr, - ld_val__h29543); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h30528, - "I_MMU_Cache", - rg_addr, - ld_val__h29543); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h30641 = $stime; - #0; - end - v__h30635 = v__h30641 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h30635, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h30635, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h30826 = $stime; - #0; - end - v__h30820 = v__h30826 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h30820, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h30820, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h31348 = $stime; - #0; - end - v__h31342 = v__h31348 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h31342); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", value__h34992); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", mem_req_wr_data_wdata__h31144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", mem_req_wr_data_wstrb__h32649); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h31762 = $stime; - #0; - end - v__h31756 = v__h31762 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h31756, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h31756, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", value__h31966); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h3705 = $stime; - #0; - end - v__h3699 = v__h3705 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h3699); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", f_pte_writebacks$D_OUT[127:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", f_pte_writebacks$D_OUT[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd255); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h32080 = $stime; - #0; - end - v__h32074 = v__h32080 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h32074, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h32074, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h32255 = $stime; - #0; - end - v__h32249 = v__h32255 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h32249, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h32249, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h34868 = $stime; - #0; - end - v__h34862 = v__h34868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h34862); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", value__h34992); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", mem_req_wr_data_wdata__h32648); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", mem_req_wr_data_wstrb__h32649); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h35120 = $stime; - #0; - end - v__h35114 = v__h35120 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h35114, - "D_MMU_Cache", - rg_addr, - new_ld_val__h32381); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h35114, - "I_MMU_Cache", - rg_addr, - new_ld_val__h32381); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h32351 = $stime; - #0; - end - v__h32345 = v__h32351 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h32345, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h32345, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h23262 = $stime; - #0; - end - v__h23256 = v__h23262 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE", - v__h23256, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE", - v__h23256, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", lev_2_pte_pa_w64_fa__h23317); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h26457 = $stime; - #0; - end - v__h26451 = v__h26457 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_start_cache_refill: ", - v__h26451, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_cache_refill: ", - v__h26451, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", cline_fabric_addr__h26510); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd7); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" Victim way %0d; => CACHE_REFILL", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h29060 = $stime; - #0; - end - v__h29054 = v__h29060 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h29054, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h29054, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", value__h31966); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h36090 = $stime; - #0; - end - v__h36084 = v__h36090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $write("%0d: %s.req: op:", v__h36084, "D_MMU_Cache"); - else - $write("%0d: %s.req: op:", v__h36084, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_op == 2'd0) - $write("CACHE_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_op == 2'd1) - $write("CACHE_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_op != 2'd0 && - req_op != 2'd1) - $write("CACHE_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", - req_f3, - req_addr, - req_st_value); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv == 2'b0) - $write("U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv == 2'b01) - $write("S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv == 2'b11) - $write("M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv != 2'b0 && - req_priv != 2'b01 && - req_priv != 2'b11) - $write("RESERVED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19) - $display(" amo_funct7 = 0x%0h", req_amo_funct7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && - req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419 && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - req_addr[11:6], - req_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_tlb_flush && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h37244 = $stime; - #0; - end - v__h37238 = v__h37244 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_tlb_flush && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.tlb_flush", v__h37238, "D_MMU_Cache"); - else - $display("%0d: %s.tlb_flush", v__h37238, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h35740 = $stime; - #0; - end - v__h35734 = v__h35740 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h35734, - "D_MMU_Cache", - $unsigned(b__h23216)); - else - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h35734, - "I_MMU_Cache", - $unsigned(b__h23216)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - begin - v__h35701 = $stime; - #0; - end - v__h35695 = v__h35701 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - if (dmem_not_imem) - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h35695, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h35695, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("\n"); - end - // synopsys translate_on -endmodule // mkMMU_Cache - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v deleted file mode 100644 index f673c615..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v +++ /dev/null @@ -1,2169 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// to_raw_mem_response_put I 256 -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_to_raw_mem_response_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Controller(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [63 : 0] slave_rdata; - wire [7 : 0] status; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // inlined wires - reg [353 : 0] f_raw_mem_reqs_rv$port1__write_1; - wire [353 : 0] f_raw_mem_reqs_rv$port1__read, - f_raw_mem_reqs_rv$port2__read, - f_raw_mem_reqs_rv$port3__read; - wire [256 : 0] f_raw_mem_rsps_rv$port1__read, - f_raw_mem_rsps_rv$port1__write_1, - f_raw_mem_rsps_rv$port2__read, - f_raw_mem_rsps_rv$port3__read; - wire [170 : 0] f_reqs_rv$port1__read, - f_reqs_rv$port1__write_1, - f_reqs_rv$port2__read; - wire f_raw_mem_reqs_rv$EN_port1__write, - f_reqs_rv$EN_port0__write, - f_reqs_rv$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register f_raw_mem_reqs_rv - reg [353 : 0] f_raw_mem_reqs_rv; - wire [353 : 0] f_raw_mem_reqs_rv$D_IN; - wire f_raw_mem_reqs_rv$EN; - - // register f_raw_mem_rsps_rv - reg [256 : 0] f_raw_mem_rsps_rv; - wire [256 : 0] f_raw_mem_rsps_rv$D_IN; - wire f_raw_mem_rsps_rv$EN; - - // register f_reqs_rv - reg [170 : 0] f_reqs_rv; - wire [170 : 0] f_reqs_rv$D_IN; - wire f_reqs_rv$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_cached_clean - reg rg_cached_clean; - wire rg_cached_clean$D_IN, rg_cached_clean$EN; - - // register rg_cached_raw_mem_addr - reg [63 : 0] rg_cached_raw_mem_addr; - wire [63 : 0] rg_cached_raw_mem_addr$D_IN; - wire rg_cached_raw_mem_addr$EN; - - // register rg_cached_raw_mem_word - reg [255 : 0] rg_cached_raw_mem_word; - wire [255 : 0] rg_cached_raw_mem_word$D_IN; - wire rg_cached_raw_mem_word$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_status - reg [7 : 0] rg_status; - wire [7 : 0] rg_status$D_IN; - wire rg_status$EN; - - // register rg_tohost_addr - reg [63 : 0] rg_tohost_addr; - wire [63 : 0] rg_tohost_addr$D_IN; - wire rg_tohost_addr$EN; - - // register rg_watch_tohost - reg rg_watch_tohost; - wire rg_watch_tohost$D_IN, rg_watch_tohost$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_external_reset, - CAN_FIRE_RL_rl_invalid_rd_address, - CAN_FIRE_RL_rl_invalid_wr_address, - CAN_FIRE_RL_rl_merge_rd_req, - CAN_FIRE_RL_rl_merge_wr_req, - CAN_FIRE_RL_rl_miss_clean_req, - CAN_FIRE_RL_rl_power_on_reset, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reload, - CAN_FIRE_RL_rl_reset_reload_cache, - CAN_FIRE_RL_rl_writeback_dirty, - CAN_FIRE_RL_rl_writeback_dirty_idle, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_external_reset, - WILL_FIRE_RL_rl_invalid_rd_address, - WILL_FIRE_RL_rl_invalid_wr_address, - WILL_FIRE_RL_rl_merge_rd_req, - WILL_FIRE_RL_rl_merge_wr_req, - WILL_FIRE_RL_rl_miss_clean_req, - WILL_FIRE_RL_rl_power_on_reset, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reload, - WILL_FIRE_RL_rl_reset_reload_cache, - WILL_FIRE_RL_rl_writeback_dirty, - WILL_FIRE_RL_rl_writeback_dirty_idle, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire [353 : 0] MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1, - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - wire [255 : 0] MUX_rg_cached_raw_mem_word$write_1__VAL_1; - wire [170 : 0] MUX_f_reqs_rv$port1__write_1__VAL_1, - MUX_f_reqs_rv$port1__write_1__VAL_2; - wire [70 : 0] MUX_slave_xactor_f_rd_data$enq_1__VAL_1, - MUX_slave_xactor_f_rd_data$enq_1__VAL_2; - wire [5 : 0] MUX_slave_xactor_f_wr_resp$enq_1__VAL_1, - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2; - wire MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2538; - reg [31 : 0] v__h3481; - reg [31 : 0] v__h3974; - reg [31 : 0] v__h4443; - reg [31 : 0] v__h4706; - reg [31 : 0] v__h5425; - reg [31 : 0] v__h7622; - reg [31 : 0] v__h7823; - reg [31 : 0] v__h8335; - reg [31 : 0] v__h9119; - reg [31 : 0] v__h9714; - reg [31 : 0] v__h2853; - reg [31 : 0] v__h3193; - reg [31 : 0] v__h1743; - reg [31 : 0] v__h2088; - reg [31 : 0] v__h1737; - reg [31 : 0] v__h2082; - reg [31 : 0] v__h2532; - reg [31 : 0] v__h2847; - reg [31 : 0] v__h3187; - reg [31 : 0] v__h3475; - reg [31 : 0] v__h3968; - reg [31 : 0] v__h4437; - reg [31 : 0] v__h4700; - reg [31 : 0] v__h5419; - reg [31 : 0] v__h7616; - reg [31 : 0] v__h7817; - reg [31 : 0] v__h8329; - reg [31 : 0] v__h9113; - reg [31 : 0] v__h9708; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rdata__h5068, word64_old__h5862; - wire [63 : 0] exit_value__h7860, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1, - mask__h5867, - req_raw_mem_addr__h3314, - updated_word64__h5868, - x__h6241, - y__h6242, - y__h6243; - wire [7 : 0] SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191; - wire [4 : 0] n__h5067; - wire NOT_cfg_verbosity_read_ULE_1___d5, - NOT_cfg_verbosity_read_ULE_2_2___d33, - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279, - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128, - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123, - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126, - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135, - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284, - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131, - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = rg_state == 2'd3 ; - assign CAN_FIRE_set_addr_map = rg_state == 2'd3 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = f_raw_mem_reqs_rv[352:0] ; - assign RDY_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign CAN_FIRE_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = !f_raw_mem_rsps_rv$port1__read[256] ; - assign CAN_FIRE_to_raw_mem_response_put = - !f_raw_mem_rsps_rv$port1__read[256] ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // value method status - assign status = rg_status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset_reload_cache - assign CAN_FIRE_RL_rl_reset_reload_cache = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_reload_cache = - CAN_FIRE_RL_rl_reset_reload_cache ; - - // rule RL_rl_writeback_dirty_idle - assign CAN_FIRE_RL_rl_writeback_dirty_idle = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd3 && - !f_reqs_rv[170] && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty_idle = - CAN_FIRE_RL_rl_writeback_dirty_idle ; - - // rule RL_rl_writeback_dirty - assign CAN_FIRE_RL_rl_writeback_dirty = - !f_raw_mem_reqs_rv$port1__read[353] && f_reqs_rv[170] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty = CAN_FIRE_RL_rl_writeback_dirty ; - - // rule RL_rl_miss_clean_req - assign CAN_FIRE_RL_rl_miss_clean_req = - f_reqs_rv[170] && !f_raw_mem_reqs_rv$port1__read[353] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - rg_cached_clean ; - assign WILL_FIRE_RL_rl_miss_clean_req = - CAN_FIRE_RL_rl_miss_clean_req && - !WILL_FIRE_RL_rl_external_reset && - !EN_set_addr_map ; - - // rule RL_rl_reload - assign CAN_FIRE_RL_rl_reload = f_raw_mem_rsps_rv[256] && rg_state == 2'd2 ; - assign WILL_FIRE_RL_rl_reload = CAN_FIRE_RL_rl_reload ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_invalid_rd_address - assign CAN_FIRE_RL_rl_invalid_rd_address = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_rd_address = - CAN_FIRE_RL_rl_invalid_rd_address ; - - // rule RL_rl_invalid_wr_address - assign CAN_FIRE_RL_rl_invalid_wr_address = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_wr_address = - CAN_FIRE_RL_rl_invalid_wr_address ; - - // rule RL_rl_merge_rd_req - assign CAN_FIRE_RL_rl_merge_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && !f_reqs_rv$port1__read[170] ; - assign WILL_FIRE_RL_rl_merge_rd_req = CAN_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_merge_wr_req - assign CAN_FIRE_RL_rl_merge_wr_req = - !f_reqs_rv$port1__read[170] && slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N ; - assign WILL_FIRE_RL_rl_merge_wr_req = - CAN_FIRE_RL_rl_merge_wr_req && !WILL_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_power_on_reset - assign CAN_FIRE_RL_rl_power_on_reset = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_power_on_reset = CAN_FIRE_RL_rl_power_on_reset ; - - // rule RL_rl_external_reset - assign CAN_FIRE_RL_rl_external_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && rg_state == 2'd3 ; - assign WILL_FIRE_RL_rl_external_reset = CAN_FIRE_RL_rl_external_reset ; - - // inputs to muxes for submodule ports - assign MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - assign MUX_rg_state$write_1__SEL_1 = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - assign MUX_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 = - { 34'h3FFFFFFFF, - rg_cached_raw_mem_addr, - rg_cached_raw_mem_word } ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3 = - { 34'h2FFFFFFFF, - req_raw_mem_addr__h3314, - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_1 = - { 2'd2, slave_xactor_f_rd_addr$D_OUT, 72'hAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_2 = - { 2'd3, - slave_xactor_f_wr_addr$D_OUT, - slave_xactor_f_wr_data$D_OUT[8:1], - slave_xactor_f_wr_data$D_OUT[72:9] } ; - assign MUX_rg_cached_raw_mem_word$write_1__VAL_1 = - { (f_reqs_rv[105:104] == 2'd3) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[255:192], - (f_reqs_rv[105:104] == 2'd2) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[191:128], - (f_reqs_rv[105:104] == 2'd1) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[127:64], - (f_reqs_rv[105:104] == 2'd0) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[63:0] } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_1 = - { f_reqs_rv[168:165], rdata__h5068, 3'd1 } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_2 = - { f_reqs_rv[168:101], 3'd5 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 = - { f_reqs_rv[168:165], 2'd0 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 = - { f_reqs_rv[168:165], 2'd2 } ; - - // inlined wires - assign f_reqs_rv$EN_port0__write = - WILL_FIRE_RL_rl_invalid_wr_address || - WILL_FIRE_RL_rl_invalid_rd_address || - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs_rv$port1__read = - f_reqs_rv$EN_port0__write ? - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_reqs_rv ; - assign f_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_merge_rd_req || WILL_FIRE_RL_rl_merge_wr_req ; - assign f_reqs_rv$port1__write_1 = - WILL_FIRE_RL_rl_merge_rd_req ? - MUX_f_reqs_rv$port1__write_1__VAL_1 : - MUX_f_reqs_rv$port1__write_1__VAL_2 ; - assign f_reqs_rv$port2__read = - f_reqs_rv$EN_port1__write ? - f_reqs_rv$port1__write_1 : - f_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port1__read = - EN_to_raw_mem_request_get ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv ; - assign f_raw_mem_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_miss_clean_req ; - always@(MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 or - WILL_FIRE_RL_rl_reset_reload_cache or - WILL_FIRE_RL_rl_miss_clean_req or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1; - WILL_FIRE_RL_rl_reset_reload_cache: - f_raw_mem_reqs_rv$port1__write_1 = - 354'h2FFFFFFFF0000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_miss_clean_req: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - default: f_raw_mem_reqs_rv$port1__write_1 = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign f_raw_mem_reqs_rv$port2__read = - f_raw_mem_reqs_rv$EN_port1__write ? - f_raw_mem_reqs_rv$port1__write_1 : - f_raw_mem_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv$port2__read ; - assign f_raw_mem_rsps_rv$port1__read = - CAN_FIRE_RL_rl_reload ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv ; - assign f_raw_mem_rsps_rv$port1__write_1 = - { 1'd1, to_raw_mem_response_put } ; - assign f_raw_mem_rsps_rv$port2__read = - EN_to_raw_mem_response_put ? - f_raw_mem_rsps_rv$port1__write_1 : - f_raw_mem_rsps_rv$port1__read ; - assign f_raw_mem_rsps_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv$port2__read ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register f_raw_mem_reqs_rv - assign f_raw_mem_reqs_rv$D_IN = f_raw_mem_reqs_rv$port3__read ; - assign f_raw_mem_reqs_rv$EN = 1'b1 ; - - // register f_raw_mem_rsps_rv - assign f_raw_mem_rsps_rv$D_IN = f_raw_mem_rsps_rv$port3__read ; - assign f_raw_mem_rsps_rv$EN = 1'b1 ; - - // register f_reqs_rv - assign f_reqs_rv$D_IN = f_reqs_rv$port2__read ; - assign f_reqs_rv$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_cached_clean - assign rg_cached_clean$D_IN = !WILL_FIRE_RL_rl_process_wr_req ; - assign rg_cached_clean$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload || - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - - // register rg_cached_raw_mem_addr - assign rg_cached_raw_mem_addr$D_IN = - WILL_FIRE_RL_rl_miss_clean_req ? - req_raw_mem_addr__h3314 : - 64'd0 ; - assign rg_cached_raw_mem_addr$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_cached_raw_mem_word - assign rg_cached_raw_mem_word$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_rg_cached_raw_mem_word$write_1__VAL_1 : - f_raw_mem_rsps_rv[255:0] ; - assign rg_cached_raw_mem_word$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload ; - - // register rg_state - always@(MUX_rg_state$write_1__SEL_1 or - MUX_rg_state$write_1__SEL_2 or WILL_FIRE_RL_rl_reload) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_state$write_1__SEL_1: rg_state$D_IN = 2'd1; - MUX_rg_state$write_1__SEL_2: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reload: rg_state$D_IN = 2'd3; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset || - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_reload ; - - // register rg_status - assign rg_status$D_IN = - (WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset) ? - 8'd0 : - 8'd1 ; - assign rg_status$EN = - WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 || - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - - // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_watch_tohost ; - - // register rg_watch_tohost - assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ; - assign rg_watch_tohost$EN = EN_set_watch_tohost ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_merge_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_slave_xactor_f_rd_data$enq_1__VAL_1 : - MUX_slave_xactor_f_rd_data$enq_1__VAL_2 ; - assign slave_xactor_f_rd_data$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_invalid_rd_address ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 : - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 ; - assign slave_xactor_f_wr_resp$ENQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_invalid_wr_address ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_1 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d5 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read_ULE_2_2___d33 = cfg_verbosity > 4'd2 ; - assign NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 = - f_reqs_rv[92:90] != 3'b0 && - (f_reqs_rv[92:90] != 3'b001 || f_reqs_rv[101]) && - (f_reqs_rv[92:90] != 3'b010 || f_reqs_rv[102:101] != 2'h0) && - (f_reqs_rv[92:90] != 3'b011 || f_reqs_rv[103:101] != 3'h0) && - (f_reqs_rv[92:90] != 3'b100 || f_reqs_rv[104:101] != 4'h0) && - (f_reqs_rv[92:90] != 3'b101 || f_reqs_rv[105:101] != 5'h0) && - (f_reqs_rv[92:90] != 3'b110 || f_reqs_rv[106:101] != 6'h0) && - (f_reqs_rv[92:90] != 3'b111 || f_reqs_rv[107:101] != 7'h0) ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 = {8{f_reqs_rv[64]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212 = {8{f_reqs_rv[65]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208 = {8{f_reqs_rv[66]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205 = {8{f_reqs_rv[67]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201 = {8{f_reqs_rv[68]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198 = {8{f_reqs_rv[69]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194 = {8{f_reqs_rv[70]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191 = {8{f_reqs_rv[71]}} ; - assign exit_value__h7860 = { 1'd0, f_reqs_rv[63:1] } ; - assign f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1 = - f_reqs_rv[164:101] - rg_addr_base ; - assign f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 = - f_reqs_rv[164:101] < rg_addr_lim ; - assign f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 = - f_reqs_rv[92:90] == 3'b0 || - f_reqs_rv[92:90] == 3'b001 && !f_reqs_rv[101] || - f_reqs_rv[92:90] == 3'b010 && f_reqs_rv[102:101] == 2'h0 || - f_reqs_rv[92:90] == 3'b011 && f_reqs_rv[103:101] == 3'h0 || - f_reqs_rv[92:90] == 3'b100 && f_reqs_rv[104:101] == 4'h0 || - f_reqs_rv[92:90] == 3'b101 && f_reqs_rv[105:101] == 5'h0 || - f_reqs_rv[92:90] == 3'b110 && f_reqs_rv[106:101] == 6'h0 || - f_reqs_rv[92:90] == 3'b111 && f_reqs_rv[107:101] == 7'h0 ; - assign mask__h5867 = - { SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - assign n__h5067 = { 3'd0, f_reqs_rv[105:104] } ; - assign req_raw_mem_addr__h3314 = - { 5'd0, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1[63:5] } ; - assign rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 = - rg_addr_base <= f_reqs_rv[164:101] ; - assign rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 = - rg_cached_raw_mem_addr == req_raw_mem_addr__h3314 ; - assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 = - rg_state == 2'd3 && - (NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 || - !rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 || - !f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128) ; - assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 = - rg_state == 2'd3 && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 && - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 && - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 ; - assign rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 = - rg_watch_tohost && f_reqs_rv[164:101] == rg_tohost_addr && - f_reqs_rv[63:0] != 64'd0 ; - assign updated_word64__h5868 = x__h6241 | y__h6242 ; - assign x__h6241 = word64_old__h5862 & y__h6243 ; - assign y__h6242 = f_reqs_rv[63:0] & mask__h5867 ; - assign y__h6243 = - { ~SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - ~SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - ~SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - ~SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - ~SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - ~SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - ~SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - ~SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - always@(f_reqs_rv or rg_cached_raw_mem_word) - begin - case (f_reqs_rv[105:104]) - 2'd0: word64_old__h5862 = rg_cached_raw_mem_word[63:0]; - 2'd1: word64_old__h5862 = rg_cached_raw_mem_word[127:64]; - 2'd2: word64_old__h5862 = rg_cached_raw_mem_word[191:128]; - 2'd3: word64_old__h5862 = rg_cached_raw_mem_word[255:192]; - endcase - end - always@(n__h5067 or rg_cached_raw_mem_word) - begin - case (n__h5067) - 5'd0: rdata__h5068 = rg_cached_raw_mem_word[63:0]; - 5'd1: rdata__h5068 = rg_cached_raw_mem_word[127:64]; - 5'd2: rdata__h5068 = rg_cached_raw_mem_word[191:128]; - 5'd3: rdata__h5068 = rg_cached_raw_mem_word[255:192]; - default: rdata__h5068 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - rg_status <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000; - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (f_raw_mem_reqs_rv$EN) - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_reqs_rv$D_IN; - if (f_raw_mem_rsps_rv$EN) - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_rsps_rv$D_IN; - if (f_reqs_rv$EN) f_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_reqs_rv$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_status$EN) rg_status <= `BSV_ASSIGNMENT_DELAY rg_status$D_IN; - if (rg_tohost_addr$EN) - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; - if (rg_watch_tohost$EN) - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_cached_clean$EN) - rg_cached_clean <= `BSV_ASSIGNMENT_DELAY rg_cached_clean$D_IN; - if (rg_cached_raw_mem_addr$EN) - rg_cached_raw_mem_addr <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_addr$D_IN; - if (rg_cached_raw_mem_word$EN) - rg_cached_raw_mem_word <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_word$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - f_raw_mem_reqs_rv = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv = 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_cached_clean = 1'h0; - rg_cached_raw_mem_addr = 64'hAAAAAAAAAAAAAAAA; - rg_cached_raw_mem_word = - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state = 2'h2; - rg_status = 8'hAA; - rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; - rg_watch_tohost = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2538 = $stime; - #0; - end - v__h2532 = v__h2538 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING", - v__h2532); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3481 = $stime; - #0; - end - v__h3475 = v__h3481 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h", - v__h3475, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3974 = $stime; - #0; - end - v__h3968 = v__h3974 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h", - v__h3968, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4443 = $stime; - #0; - end - v__h4437 = v__h4443 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h", - v__h4437, - req_raw_mem_addr__h3314); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_reload: raw addr 0x%0h", - v__h4700, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", f_raw_mem_rsps_rv[255:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h5425 = $stime; - #0; - end - v__h5419 = v__h5425 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", rdata__h5068); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h7622 = $stime; - #0; - end - v__h7616 = v__h7622 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7616); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - begin - v__h7823 = $stime; - #0; - end - v__h7817 = v__h7823 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - $display("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h () data 0x%0h", - v__h7817, - f_reqs_rv[164:101], - f_reqs_rv[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] == 63'd0) - $display("PASS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] != 63'd0) - $display("FAIL %0d", exit_value__h7860); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - begin - v__h8335 = $stime; - #0; - end - v__h8329 = v__h8335 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("%0d: ERROR: Mem_Controller:", v__h8329); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" read-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" read-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - begin - v__h9119 = $stime; - #0; - end - v__h9113 = v__h9119 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("%0d: ERROR: Mem_Controller:", v__h9113); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" write-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" write-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - begin - v__h9714 = $stime; - #0; - end - v__h9708 = v__h9714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - $display("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9708, - set_addr_map_addr_base, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h2853 = $stime; - #0; - end - v__h2847 = v__h2853 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_rd_req", v__h2847); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3193 = $stime; - #0; - end - v__h3187 = v__h3193 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_wr_req", v__h3187); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h1743 = $stime; - #0; - end - v__h1737 = v__h1743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_power_on_reset", v__h1737); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2088 = $stime; - #0; - end - v__h2082 = v__h2088 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE", - v__h2082); - end - // synopsys translate_on -endmodule // mkMem_Controller - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v deleted file mode 100644 index 104c51b0..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v +++ /dev/null @@ -1,192 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_mem_server_request_put O 1 reg -// mem_server_response_get O 256 reg -// RDY_mem_server_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// mem_server_request_put I 353 -// EN_mem_server_request_put I 1 -// EN_mem_server_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Model(CLK, - RST_N, - - mem_server_request_put, - EN_mem_server_request_put, - RDY_mem_server_request_put, - - EN_mem_server_response_get, - mem_server_response_get, - RDY_mem_server_response_get); - input CLK; - input RST_N; - - // action method mem_server_request_put - input [352 : 0] mem_server_request_put; - input EN_mem_server_request_put; - output RDY_mem_server_request_put; - - // actionvalue method mem_server_response_get - input EN_mem_server_response_get; - output [255 : 0] mem_server_response_get; - output RDY_mem_server_response_get; - - // signals for module outputs - wire [255 : 0] mem_server_response_get; - wire RDY_mem_server_request_put, RDY_mem_server_response_get; - - // ports of submodule f_raw_mem_rsps - wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT; - wire f_raw_mem_rsps$CLR, - f_raw_mem_rsps$DEQ, - f_raw_mem_rsps$EMPTY_N, - f_raw_mem_rsps$ENQ, - f_raw_mem_rsps$FULL_N; - - // ports of submodule rf - wire [255 : 0] rf$D_IN, rf$D_OUT_1; - wire [63 : 0] rf$ADDR_1, - rf$ADDR_2, - rf$ADDR_3, - rf$ADDR_4, - rf$ADDR_5, - rf$ADDR_IN; - wire rf$WE; - - // rule scheduling signals - wire CAN_FIRE_mem_server_request_put, - CAN_FIRE_mem_server_response_get, - WILL_FIRE_mem_server_request_put, - WILL_FIRE_mem_server_response_get; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h371; - reg [31 : 0] v__h365; - // synopsys translate_on - - // remaining internal signals - wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2; - - // action method mem_server_request_put - assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ; - - // actionvalue method mem_server_response_get - assign mem_server_response_get = f_raw_mem_rsps$D_OUT ; - assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ; - - // submodule f_raw_mem_rsps - FIFO2 #(.width(32'd256), .guarded(32'd1)) f_raw_mem_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_raw_mem_rsps$D_IN), - .ENQ(f_raw_mem_rsps$ENQ), - .DEQ(f_raw_mem_rsps$DEQ), - .CLR(f_raw_mem_rsps$CLR), - .D_OUT(f_raw_mem_rsps$D_OUT), - .FULL_N(f_raw_mem_rsps$FULL_N), - .EMPTY_N(f_raw_mem_rsps$EMPTY_N)); - - // submodule rf - RegFileLoad #(.file("Mem.hex"), - .addr_width(32'd64), - .data_width(32'd256), - .lo(64'd0), - .hi(64'd8388607), - .binary(1'd0)) rf(.CLK(CLK), - .ADDR_1(rf$ADDR_1), - .ADDR_2(rf$ADDR_2), - .ADDR_3(rf$ADDR_3), - .ADDR_4(rf$ADDR_4), - .ADDR_5(rf$ADDR_5), - .ADDR_IN(rf$ADDR_IN), - .D_IN(rf$D_IN), - .WE(rf$WE), - .D_OUT_1(rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule f_raw_mem_rsps - assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ; - assign f_raw_mem_rsps$ENQ = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - !mem_server_request_put[352] ; - assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ; - assign f_raw_mem_rsps$CLR = 1'b0 ; - - // submodule rf - assign rf$ADDR_1 = mem_server_request_put[319:256] ; - assign rf$ADDR_2 = 64'h0 ; - assign rf$ADDR_3 = 64'h0 ; - assign rf$ADDR_4 = 64'h0 ; - assign rf$ADDR_5 = 64'h0 ; - assign rf$ADDR_IN = mem_server_request_put[319:256] ; - assign rf$D_IN = mem_server_request_put[255:0] ; - assign rf$WE = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - mem_server_request_put[352] ; - - // remaining internal signals - assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 = - mem_server_request_put[319:256] < 64'h0000000000800000 ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - begin - v__h371 = $stime; - #0; - end - v__h365 = v__h371 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)", - v__h365, - mem_server_request_put[319:256], - 64'h0000000000800000); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkMem_Model - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v deleted file mode 100644 index 4c587b57..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v +++ /dev/null @@ -1,1660 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 -// RDY_server_reset_response_get O 1 reg -// imem_valid O 1 -// imem_is_i32_not_i16 O 1 const -// imem_pc O 64 reg -// imem_instr O 32 -// imem_exc O 1 -// imem_exc_code O 4 reg -// imem_tval O 64 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_valid O 1 -// dmem_word64 O 64 -// dmem_st_amo_val O 64 -// dmem_exc O 1 -// dmem_exc_code O 4 reg -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_server_fence_i_request_put O 1 -// RDY_server_fence_i_response_get O 1 -// RDY_server_fence_request_put O 1 reg -// RDY_server_fence_response_get O 1 -// RDY_sfence_vma O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// imem_req_f3 I 3 -// imem_req_addr I 64 -// imem_req_priv I 2 reg -// imem_req_sstatus_SUM I 1 reg -// imem_req_mstatus_MXR I 1 reg -// imem_req_satp I 64 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_req_op I 2 -// dmem_req_f3 I 3 -// dmem_req_amo_funct7 I 7 reg -// dmem_req_addr I 64 -// dmem_req_store_value I 64 -// dmem_req_priv I 2 reg -// dmem_req_sstatus_SUM I 1 reg -// dmem_req_mstatus_MXR I 1 reg -// dmem_req_satp I 64 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// server_fence_request_put I 8 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_imem_req I 1 -// EN_dmem_req I 1 -// EN_server_fence_i_request_put I 1 -// EN_server_fence_i_response_get I 1 -// EN_server_fence_request_put I 1 -// EN_server_fence_response_get I 1 -// EN_sfence_vma I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_valid -// (imem_master_awready, imem_master_wready) -> imem_instr -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// imem_master_arready, -// EN_imem_req) -> imem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_valid -// (dmem_master_awready, dmem_master_wready) -> dmem_word64 -// (dmem_master_awready, dmem_master_wready) -> dmem_st_amo_val -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// (dmem_master_awready, -// dmem_master_wready, -// dmem_master_arready, -// EN_dmem_req) -> dmem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - imem_req_f3, - imem_req_addr, - imem_req_priv, - imem_req_sstatus_SUM, - imem_req_mstatus_MXR, - imem_req_satp, - EN_imem_req, - - imem_valid, - - imem_is_i32_not_i16, - - imem_pc, - - imem_instr, - - imem_exc, - - imem_exc_code, - - imem_tval, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_req_op, - dmem_req_f3, - dmem_req_amo_funct7, - dmem_req_addr, - dmem_req_store_value, - dmem_req_priv, - dmem_req_sstatus_SUM, - dmem_req_mstatus_MXR, - dmem_req_satp, - EN_dmem_req, - - dmem_valid, - - dmem_word64, - - dmem_st_amo_val, - - dmem_exc, - - dmem_exc_code, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - EN_server_fence_i_request_put, - RDY_server_fence_i_request_put, - - EN_server_fence_i_response_get, - RDY_server_fence_i_response_get, - - server_fence_request_put, - EN_server_fence_request_put, - RDY_server_fence_request_put, - - EN_server_fence_response_get, - RDY_server_fence_response_get, - - EN_sfence_vma, - RDY_sfence_vma); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method imem_req - input [2 : 0] imem_req_f3; - input [63 : 0] imem_req_addr; - input [1 : 0] imem_req_priv; - input imem_req_sstatus_SUM; - input imem_req_mstatus_MXR; - input [63 : 0] imem_req_satp; - input EN_imem_req; - - // value method imem_valid - output imem_valid; - - // value method imem_is_i32_not_i16 - output imem_is_i32_not_i16; - - // value method imem_pc - output [63 : 0] imem_pc; - - // value method imem_instr - output [31 : 0] imem_instr; - - // value method imem_exc - output imem_exc; - - // value method imem_exc_code - output [3 : 0] imem_exc_code; - - // value method imem_tval - output [63 : 0] imem_tval; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // action method dmem_req - input [1 : 0] dmem_req_op; - input [2 : 0] dmem_req_f3; - input [6 : 0] dmem_req_amo_funct7; - input [63 : 0] dmem_req_addr; - input [63 : 0] dmem_req_store_value; - input [1 : 0] dmem_req_priv; - input dmem_req_sstatus_SUM; - input dmem_req_mstatus_MXR; - input [63 : 0] dmem_req_satp; - input EN_dmem_req; - - // value method dmem_valid - output dmem_valid; - - // value method dmem_word64 - output [63 : 0] dmem_word64; - - // value method dmem_st_amo_val - output [63 : 0] dmem_st_amo_val; - - // value method dmem_exc - output dmem_exc; - - // value method dmem_exc_code - output [3 : 0] dmem_exc_code; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method server_fence_i_request_put - input EN_server_fence_i_request_put; - output RDY_server_fence_i_request_put; - - // action method server_fence_i_response_get - input EN_server_fence_i_response_get; - output RDY_server_fence_i_response_get; - - // action method server_fence_request_put - input [7 : 0] server_fence_request_put; - input EN_server_fence_request_put; - output RDY_server_fence_request_put; - - // action method server_fence_response_get - input EN_server_fence_response_get; - output RDY_server_fence_response_get; - - // action method sfence_vma - input EN_sfence_vma; - output RDY_sfence_vma; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - dmem_st_amo_val, - dmem_word64, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata, - imem_pc, - imem_tval; - wire [31 : 0] imem_instr; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_exc_code, - dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_exc_code, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_server_fence_i_request_put, - RDY_server_fence_i_response_get, - RDY_server_fence_request_put, - RDY_server_fence_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_sfence_vma, - dmem_exc, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - dmem_valid, - imem_exc, - imem_is_i32_not_i16, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid, - imem_valid; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule dcache - wire [63 : 0] dcache$mem_master_araddr, - dcache$mem_master_awaddr, - dcache$mem_master_rdata, - dcache$mem_master_wdata, - dcache$req_addr, - dcache$req_satp, - dcache$req_st_value, - dcache$st_amo_val, - dcache$word64; - wire [7 : 0] dcache$mem_master_arlen, - dcache$mem_master_awlen, - dcache$mem_master_wstrb; - wire [6 : 0] dcache$req_amo_funct7; - wire [3 : 0] dcache$exc_code, - dcache$mem_master_arcache, - dcache$mem_master_arid, - dcache$mem_master_arqos, - dcache$mem_master_arregion, - dcache$mem_master_awcache, - dcache$mem_master_awid, - dcache$mem_master_awqos, - dcache$mem_master_awregion, - dcache$mem_master_bid, - dcache$mem_master_rid, - dcache$mem_master_wid, - dcache$set_verbosity_verbosity; - wire [2 : 0] dcache$mem_master_arprot, - dcache$mem_master_arsize, - dcache$mem_master_awprot, - dcache$mem_master_awsize, - dcache$req_f3; - wire [1 : 0] dcache$mem_master_arburst, - dcache$mem_master_awburst, - dcache$mem_master_bresp, - dcache$mem_master_rresp, - dcache$req_op, - dcache$req_priv; - wire dcache$EN_req, - dcache$EN_server_flush_request_put, - dcache$EN_server_flush_response_get, - dcache$EN_server_reset_request_put, - dcache$EN_server_reset_response_get, - dcache$EN_set_verbosity, - dcache$EN_tlb_flush, - dcache$RDY_server_flush_request_put, - dcache$RDY_server_flush_response_get, - dcache$RDY_server_reset_request_put, - dcache$RDY_server_reset_response_get, - dcache$exc, - dcache$mem_master_arlock, - dcache$mem_master_arready, - dcache$mem_master_arvalid, - dcache$mem_master_awlock, - dcache$mem_master_awready, - dcache$mem_master_awvalid, - dcache$mem_master_bready, - dcache$mem_master_bvalid, - dcache$mem_master_rlast, - dcache$mem_master_rready, - dcache$mem_master_rvalid, - dcache$mem_master_wlast, - dcache$mem_master_wready, - dcache$mem_master_wvalid, - dcache$req_mstatus_MXR, - dcache$req_sstatus_SUM, - dcache$valid; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule icache - wire [63 : 0] icache$addr, - icache$mem_master_araddr, - icache$mem_master_awaddr, - icache$mem_master_rdata, - icache$mem_master_wdata, - icache$req_addr, - icache$req_satp, - icache$req_st_value, - icache$word64; - wire [7 : 0] icache$mem_master_arlen, - icache$mem_master_awlen, - icache$mem_master_wstrb; - wire [6 : 0] icache$req_amo_funct7; - wire [3 : 0] icache$exc_code, - icache$mem_master_arcache, - icache$mem_master_arid, - icache$mem_master_arqos, - icache$mem_master_arregion, - icache$mem_master_awcache, - icache$mem_master_awid, - icache$mem_master_awqos, - icache$mem_master_awregion, - icache$mem_master_bid, - icache$mem_master_rid, - icache$mem_master_wid, - icache$set_verbosity_verbosity; - wire [2 : 0] icache$mem_master_arprot, - icache$mem_master_arsize, - icache$mem_master_awprot, - icache$mem_master_awsize, - icache$req_f3; - wire [1 : 0] icache$mem_master_arburst, - icache$mem_master_awburst, - icache$mem_master_bresp, - icache$mem_master_rresp, - icache$req_op, - icache$req_priv; - wire icache$EN_req, - icache$EN_server_flush_request_put, - icache$EN_server_flush_response_get, - icache$EN_server_reset_request_put, - icache$EN_server_reset_response_get, - icache$EN_set_verbosity, - icache$EN_tlb_flush, - icache$RDY_server_flush_request_put, - icache$RDY_server_flush_response_get, - icache$RDY_server_reset_request_put, - icache$RDY_server_reset_response_get, - icache$exc, - icache$mem_master_arlock, - icache$mem_master_arready, - icache$mem_master_arvalid, - icache$mem_master_awlock, - icache$mem_master_awready, - icache$mem_master_awvalid, - icache$mem_master_bready, - icache$mem_master_bvalid, - icache$mem_master_rlast, - icache$mem_master_rready, - icache$mem_master_rvalid, - icache$mem_master_wlast, - icache$mem_master_wready, - icache$mem_master_wvalid, - icache$req_mstatus_MXR, - icache$req_sstatus_SUM, - icache$valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_dmem_req, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_imem_req, - CAN_FIRE_server_fence_i_request_put, - CAN_FIRE_server_fence_i_response_get, - CAN_FIRE_server_fence_request_put, - CAN_FIRE_server_fence_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_sfence_vma, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_dmem_req, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_imem_req, - WILL_FIRE_server_fence_i_request_put, - WILL_FIRE_server_fence_i_response_get, - WILL_FIRE_server_fence_request_put, - WILL_FIRE_server_fence_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_sfence_vma; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h1675; - reg [31 : 0] v__h1826; - reg [31 : 0] v__h1669; - reg [31 : 0] v__h1820; - // synopsys translate_on - - // remaining internal signals - wire NOT_cfg_verbosity_read_ULE_1___d9; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = rg_state == 2'd2 ; - assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method imem_req - assign CAN_FIRE_imem_req = 1'd1 ; - assign WILL_FIRE_imem_req = EN_imem_req ; - - // value method imem_valid - assign imem_valid = icache$valid ; - - // value method imem_is_i32_not_i16 - assign imem_is_i32_not_i16 = 1'd1 ; - - // value method imem_pc - assign imem_pc = icache$addr ; - - // value method imem_instr - assign imem_instr = icache$word64[31:0] ; - - // value method imem_exc - assign imem_exc = icache$exc ; - - // value method imem_exc_code - assign imem_exc_code = icache$exc_code ; - - // value method imem_tval - assign imem_tval = icache$addr ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = icache$mem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = icache$mem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = icache$mem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = icache$mem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = icache$mem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = icache$mem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = icache$mem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = icache$mem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = icache$mem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = icache$mem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = icache$mem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = icache$mem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = icache$mem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = icache$mem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = icache$mem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = icache$mem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = icache$mem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = icache$mem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = icache$mem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = icache$mem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = icache$mem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = icache$mem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = icache$mem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = icache$mem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = icache$mem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = icache$mem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = icache$mem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = icache$mem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = icache$mem_master_rready ; - - // action method dmem_req - assign CAN_FIRE_dmem_req = 1'd1 ; - assign WILL_FIRE_dmem_req = EN_dmem_req ; - - // value method dmem_valid - assign dmem_valid = dcache$valid ; - - // value method dmem_word64 - assign dmem_word64 = dcache$word64 ; - - // value method dmem_st_amo_val - assign dmem_st_amo_val = dcache$st_amo_val ; - - // value method dmem_exc - assign dmem_exc = dcache$exc ; - - // value method dmem_exc_code - assign dmem_exc_code = dcache$exc_code ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = dcache$mem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = dcache$mem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = dcache$mem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = dcache$mem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = dcache$mem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = dcache$mem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = dcache$mem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = dcache$mem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = dcache$mem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = dcache$mem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = dcache$mem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = dcache$mem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = dcache$mem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = dcache$mem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = dcache$mem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = dcache$mem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = dcache$mem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = dcache$mem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = dcache$mem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = dcache$mem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = dcache$mem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = dcache$mem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = dcache$mem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = dcache$mem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = dcache$mem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = dcache$mem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = dcache$mem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = dcache$mem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = dcache$mem_master_rready ; - - // action method server_fence_i_request_put - assign RDY_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_i_request_put = - EN_server_fence_i_request_put ; - - // action method server_fence_i_response_get - assign RDY_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_i_response_get = - EN_server_fence_i_response_get ; - - // action method server_fence_request_put - assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_request_put = - dcache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ; - - // action method server_fence_response_get - assign RDY_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ; - - // action method sfence_vma - assign RDY_sfence_vma = 1'd1 ; - assign CAN_FIRE_sfence_vma = 1'd1 ; - assign WILL_FIRE_sfence_vma = EN_sfence_vma ; - - // submodule dcache - mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(dcache$mem_master_arready), - .mem_master_awready(dcache$mem_master_awready), - .mem_master_bid(dcache$mem_master_bid), - .mem_master_bresp(dcache$mem_master_bresp), - .mem_master_bvalid(dcache$mem_master_bvalid), - .mem_master_rdata(dcache$mem_master_rdata), - .mem_master_rid(dcache$mem_master_rid), - .mem_master_rlast(dcache$mem_master_rlast), - .mem_master_rresp(dcache$mem_master_rresp), - .mem_master_rvalid(dcache$mem_master_rvalid), - .mem_master_wready(dcache$mem_master_wready), - .req_addr(dcache$req_addr), - .req_amo_funct7(dcache$req_amo_funct7), - .req_f3(dcache$req_f3), - .req_mstatus_MXR(dcache$req_mstatus_MXR), - .req_op(dcache$req_op), - .req_priv(dcache$req_priv), - .req_satp(dcache$req_satp), - .req_sstatus_SUM(dcache$req_sstatus_SUM), - .req_st_value(dcache$req_st_value), - .set_verbosity_verbosity(dcache$set_verbosity_verbosity), - .EN_set_verbosity(dcache$EN_set_verbosity), - .EN_server_reset_request_put(dcache$EN_server_reset_request_put), - .EN_server_reset_response_get(dcache$EN_server_reset_response_get), - .EN_req(dcache$EN_req), - .EN_server_flush_request_put(dcache$EN_server_flush_request_put), - .EN_server_flush_response_get(dcache$EN_server_flush_response_get), - .EN_tlb_flush(dcache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), - .valid(dcache$valid), - .addr(), - .word64(dcache$word64), - .st_amo_val(dcache$st_amo_val), - .exc(dcache$exc), - .exc_code(dcache$exc_code), - .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(dcache$mem_master_awvalid), - .mem_master_awid(dcache$mem_master_awid), - .mem_master_awaddr(dcache$mem_master_awaddr), - .mem_master_awlen(dcache$mem_master_awlen), - .mem_master_awsize(dcache$mem_master_awsize), - .mem_master_awburst(dcache$mem_master_awburst), - .mem_master_awlock(dcache$mem_master_awlock), - .mem_master_awcache(dcache$mem_master_awcache), - .mem_master_awprot(dcache$mem_master_awprot), - .mem_master_awqos(dcache$mem_master_awqos), - .mem_master_awregion(dcache$mem_master_awregion), - .mem_master_wvalid(dcache$mem_master_wvalid), - .mem_master_wid(dcache$mem_master_wid), - .mem_master_wdata(dcache$mem_master_wdata), - .mem_master_wstrb(dcache$mem_master_wstrb), - .mem_master_wlast(dcache$mem_master_wlast), - .mem_master_bready(dcache$mem_master_bready), - .mem_master_arvalid(dcache$mem_master_arvalid), - .mem_master_arid(dcache$mem_master_arid), - .mem_master_araddr(dcache$mem_master_araddr), - .mem_master_arlen(dcache$mem_master_arlen), - .mem_master_arsize(dcache$mem_master_arsize), - .mem_master_arburst(dcache$mem_master_arburst), - .mem_master_arlock(dcache$mem_master_arlock), - .mem_master_arcache(dcache$mem_master_arcache), - .mem_master_arprot(dcache$mem_master_arprot), - .mem_master_arqos(dcache$mem_master_arqos), - .mem_master_arregion(dcache$mem_master_arregion), - .mem_master_rready(dcache$mem_master_rready)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule icache - mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(icache$mem_master_arready), - .mem_master_awready(icache$mem_master_awready), - .mem_master_bid(icache$mem_master_bid), - .mem_master_bresp(icache$mem_master_bresp), - .mem_master_bvalid(icache$mem_master_bvalid), - .mem_master_rdata(icache$mem_master_rdata), - .mem_master_rid(icache$mem_master_rid), - .mem_master_rlast(icache$mem_master_rlast), - .mem_master_rresp(icache$mem_master_rresp), - .mem_master_rvalid(icache$mem_master_rvalid), - .mem_master_wready(icache$mem_master_wready), - .req_addr(icache$req_addr), - .req_amo_funct7(icache$req_amo_funct7), - .req_f3(icache$req_f3), - .req_mstatus_MXR(icache$req_mstatus_MXR), - .req_op(icache$req_op), - .req_priv(icache$req_priv), - .req_satp(icache$req_satp), - .req_sstatus_SUM(icache$req_sstatus_SUM), - .req_st_value(icache$req_st_value), - .set_verbosity_verbosity(icache$set_verbosity_verbosity), - .EN_set_verbosity(icache$EN_set_verbosity), - .EN_server_reset_request_put(icache$EN_server_reset_request_put), - .EN_server_reset_response_get(icache$EN_server_reset_response_get), - .EN_req(icache$EN_req), - .EN_server_flush_request_put(icache$EN_server_flush_request_put), - .EN_server_flush_response_get(icache$EN_server_flush_response_get), - .EN_tlb_flush(icache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), - .valid(icache$valid), - .addr(icache$addr), - .word64(icache$word64), - .st_amo_val(), - .exc(icache$exc), - .exc_code(icache$exc_code), - .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(icache$mem_master_awvalid), - .mem_master_awid(icache$mem_master_awid), - .mem_master_awaddr(icache$mem_master_awaddr), - .mem_master_awlen(icache$mem_master_awlen), - .mem_master_awsize(icache$mem_master_awsize), - .mem_master_awburst(icache$mem_master_awburst), - .mem_master_awlock(icache$mem_master_awlock), - .mem_master_awcache(icache$mem_master_awcache), - .mem_master_awprot(icache$mem_master_awprot), - .mem_master_awqos(icache$mem_master_awqos), - .mem_master_awregion(icache$mem_master_awregion), - .mem_master_wvalid(icache$mem_master_wvalid), - .mem_master_wid(icache$mem_master_wid), - .mem_master_wdata(icache$mem_master_wdata), - .mem_master_wstrb(icache$mem_master_wstrb), - .mem_master_wlast(icache$mem_master_wlast), - .mem_master_bready(icache$mem_master_bready), - .mem_master_arvalid(icache$mem_master_arvalid), - .mem_master_arid(icache$mem_master_arid), - .mem_master_araddr(icache$mem_master_araddr), - .mem_master_arlen(icache$mem_master_arlen), - .mem_master_arsize(icache$mem_master_arsize), - .mem_master_arburst(icache$mem_master_arburst), - .mem_master_arlock(icache$mem_master_arlock), - .mem_master_arcache(icache$mem_master_arcache), - .mem_master_arprot(icache$mem_master_arprot), - .mem_master_arqos(icache$mem_master_arqos), - .mem_master_arregion(icache$mem_master_arregion), - .mem_master_rready(icache$mem_master_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - dcache$RDY_server_reset_request_put && - icache$RDY_server_reset_request_put && - rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && - !EN_server_fence_i_request_put ; - assign MUX_rg_state$write_1__SEL_3 = - dcache$RDY_server_reset_response_get && - icache$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - rg_state == 2'd1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete) - begin - case (1'b1) // synopsys parallel_case - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1; - WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset || - WILL_FIRE_RL_rl_reset_complete ; - - // submodule dcache - assign dcache$mem_master_arready = dmem_master_arready ; - assign dcache$mem_master_awready = dmem_master_awready ; - assign dcache$mem_master_bid = dmem_master_bid ; - assign dcache$mem_master_bresp = dmem_master_bresp ; - assign dcache$mem_master_bvalid = dmem_master_bvalid ; - assign dcache$mem_master_rdata = dmem_master_rdata ; - assign dcache$mem_master_rid = dmem_master_rid ; - assign dcache$mem_master_rlast = dmem_master_rlast ; - assign dcache$mem_master_rresp = dmem_master_rresp ; - assign dcache$mem_master_rvalid = dmem_master_rvalid ; - assign dcache$mem_master_wready = dmem_master_wready ; - assign dcache$req_addr = dmem_req_addr ; - assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ; - assign dcache$req_f3 = dmem_req_f3 ; - assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ; - assign dcache$req_op = dmem_req_op ; - assign dcache$req_priv = dmem_req_priv ; - assign dcache$req_satp = dmem_req_satp ; - assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ; - assign dcache$req_st_value = dmem_req_store_value ; - assign dcache$set_verbosity_verbosity = 4'h0 ; - assign dcache$EN_set_verbosity = 1'b0 ; - assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign dcache$EN_req = EN_dmem_req ; - assign dcache$EN_server_flush_request_put = - EN_server_fence_i_request_put || EN_server_fence_request_put ; - assign dcache$EN_server_flush_response_get = - EN_server_fence_i_response_get || EN_server_fence_response_get ; - assign dcache$EN_tlb_flush = EN_sfence_vma ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule icache - assign icache$mem_master_arready = imem_master_arready ; - assign icache$mem_master_awready = imem_master_awready ; - assign icache$mem_master_bid = imem_master_bid ; - assign icache$mem_master_bresp = imem_master_bresp ; - assign icache$mem_master_bvalid = imem_master_bvalid ; - assign icache$mem_master_rdata = imem_master_rdata ; - assign icache$mem_master_rid = imem_master_rid ; - assign icache$mem_master_rlast = imem_master_rlast ; - assign icache$mem_master_rresp = imem_master_rresp ; - assign icache$mem_master_rvalid = imem_master_rvalid ; - assign icache$mem_master_wready = imem_master_wready ; - assign icache$req_addr = imem_req_addr ; - assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ; - assign icache$req_f3 = imem_req_f3 ; - assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ; - assign icache$req_op = 2'd0 ; - assign icache$req_priv = imem_req_priv ; - assign icache$req_satp = imem_req_satp ; - assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ; - assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign icache$set_verbosity_verbosity = 4'h0 ; - assign icache$EN_set_verbosity = 1'b0 ; - assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign icache$EN_req = EN_imem_req ; - assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ; - assign icache$EN_server_flush_response_get = - EN_server_fence_i_response_get ; - assign icache$EN_tlb_flush = EN_sfence_vma ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1675 = $stime; - #0; - end - v__h1669 = v__h1675 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset", v__h1669); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1826 = $stime; - #0; - end - v__h1820 = v__h1826 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset_complete", v__h1820); - end - // synopsys translate_on -endmodule // mkNear_Mem - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v deleted file mode 100644 index 32e93584..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v +++ /dev/null @@ -1,1308 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// RDY_server_request_put O 1 reg -// server_response_get O 66 reg -// RDY_server_response_get O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// server_request_put I 137 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_server_request_put I 1 -// EN_server_response_get I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - server_request_put, - EN_server_request_put, - RDY_server_request_put, - - EN_server_response_get, - server_response_get, - RDY_server_response_get, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method server_request_put - input [136 : 0] server_request_put; - input EN_server_request_put; - output RDY_server_request_put; - - // actionvalue method server_response_get - input EN_server_response_get; - output [65 : 0] server_response_get; - output RDY_server_response_get; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [65 : 0] server_response_get; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_request_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_server_response_get, - RDY_set_addr_map, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reqs - wire [136 : 0] f_reqs$D_IN, f_reqs$D_OUT; - wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_rsps - wire [65 : 0] f_rsps$D_IN, f_rsps$D_OUT; - wire f_rsps$CLR, f_rsps$DEQ, f_rsps$EMPTY_N, f_rsps$ENQ, f_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_request_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_server_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_request_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_server_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire [65 : 0] MUX_f_rsps$enq_1__VAL_1, MUX_f_rsps$enq_1__VAL_2; - wire [63 : 0] MUX_crg_time$port1__write_1__VAL_1, - MUX_crg_timecmp$port1__write_1__VAL_1; - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8676; - reg [31 : 0] v__h8808; - reg [31 : 0] v__h1471; - reg [31 : 0] v__h1868; - reg [31 : 0] v__h2065; - reg [31 : 0] v__h1714; - reg [31 : 0] v__h2442; - reg [31 : 0] v__h7890; - reg [31 : 0] v__h8258; - reg [31 : 0] v__h8368; - reg [31 : 0] v__h8475; - reg [31 : 0] v__h1465; - reg [31 : 0] v__h1708; - reg [31 : 0] v__h1862; - reg [31 : 0] v__h2059; - reg [31 : 0] v__h2436; - reg [31 : 0] v__h7884; - reg [31 : 0] v__h8252; - reg [31 : 0] v__h8362; - reg [31 : 0] v__h8469; - reg [31 : 0] v__h8670; - reg [31 : 0] v__h8802; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rsp_rdata__h2209; - wire [63 : 0] byte_addr__h1981, - mask__h2865, - mask__h5362, - new_data__h5360, - new_time__h4107, - new_time__h6632, - new_timecmp__h2834, - new_timecmp__h5331, - old_time__h6631, - rdata__h1996, - rdata__h2020, - rdata__h2026, - x__h2876, - x__h4149, - x__h5373, - x__h6674, - y__h2877, - y__h2878, - y__h5374, - y__h5375; - wire [7 : 0] SEXT_f_reqs_first__8_BIT_0_31___d132, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_7_07___d108; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method server_request_put - assign RDY_server_request_put = f_reqs$FULL_N ; - assign CAN_FIRE_server_request_put = f_reqs$FULL_N ; - assign WILL_FIRE_server_request_put = EN_server_request_put ; - - // actionvalue method server_response_get - assign server_response_get = f_rsps$D_OUT ; - assign RDY_server_response_get = f_rsps$EMPTY_N ; - assign CAN_FIRE_server_response_get = f_rsps$EMPTY_N ; - assign WILL_FIRE_server_response_get = EN_server_response_get ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reqs - FIFO2 #(.width(32'd137), .guarded(32'd1)) f_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reqs$D_IN), - .ENQ(f_reqs$ENQ), - .DEQ(f_reqs$DEQ), - .CLR(f_reqs$CLR), - .D_OUT(f_reqs$D_OUT), - .FULL_N(f_reqs$FULL_N), - .EMPTY_N(f_reqs$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_rsps - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_rsps$D_IN), - .ENQ(f_rsps$ENQ), - .DEQ(f_rsps$DEQ), - .CLR(f_rsps$CLR), - .D_OUT(f_rsps$D_OUT), - .FULL_N(f_rsps$FULL_N), - .EMPTY_N(f_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && rg_state && - !f_reset_reqs$EMPTY_N && - f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && - (byte_addr__h1981 != 64'h0 || - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - f_sw_interrupt_req$FULL_N) && - rg_state && - !f_reset_reqs$EMPTY_N && - !f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign MUX_crg_time$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h000000000000BFF8) ? - new_time__h4107 : - new_time__h6632 ; - assign MUX_crg_timecmp$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h0000000000004000) ? - new_timecmp__h2834 : - new_timecmp__h5331 ; - assign MUX_f_rsps$enq_1__VAL_1 = - { 1'd1, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - rsp_rdata__h2209 } ; - assign MUX_f_rsps$enq_1__VAL_2 = - { 1'd0, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - 64'hAAAAAAAAAAAAAAAA } ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? - MUX_crg_time$port1__write_1__VAL_1 : - 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h6631 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - MUX_crg_timecmp$port1__write_1__VAL_1 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = MUX_rg_msip$write_1__SEL_1 && f_reqs$D_OUT[8] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reqs - assign f_reqs$D_IN = server_request_put ; - assign f_reqs$ENQ = EN_server_request_put ; - assign f_reqs$DEQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_rsps - assign f_rsps$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_f_rsps$enq_1__VAL_1 : - MUX_f_rsps$enq_1__VAL_2 ; - assign f_rsps$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_process_wr_req ; - assign f_rsps$DEQ = EN_server_response_get ; - assign f_rsps$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = f_reqs$D_OUT[8] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_f_reqs_first__8_BIT_0_31___d132 = {8{f_reqs$D_OUT[0]}} ; - assign SEXT_f_reqs_first__8_BIT_1_28___d129 = {8{f_reqs$D_OUT[1]}} ; - assign SEXT_f_reqs_first__8_BIT_2_24___d125 = {8{f_reqs$D_OUT[2]}} ; - assign SEXT_f_reqs_first__8_BIT_3_21___d122 = {8{f_reqs$D_OUT[3]}} ; - assign SEXT_f_reqs_first__8_BIT_4_17___d118 = {8{f_reqs$D_OUT[4]}} ; - assign SEXT_f_reqs_first__8_BIT_5_14___d115 = {8{f_reqs$D_OUT[5]}} ; - assign SEXT_f_reqs_first__8_BIT_6_10___d111 = {8{f_reqs$D_OUT[6]}} ; - assign SEXT_f_reqs_first__8_BIT_7_07___d108 = {8{f_reqs$D_OUT[7]}} ; - assign byte_addr__h1981 = f_reqs$D_OUT[135:72] - rg_addr_base ; - assign mask__h2865 = - { SEXT_f_reqs_first__8_BIT_7_07___d108, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign mask__h5362 = - { SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'd0 } ; - assign new_data__h5360 = { f_reqs$D_OUT[39:8], 32'h0 } ; - assign new_time__h4107 = x__h4149 | y__h2877 ; - assign new_time__h6632 = x__h6674 | y__h5374 ; - assign new_timecmp__h2834 = x__h2876 | y__h2877 ; - assign new_timecmp__h5331 = x__h5373 | y__h5374 ; - assign old_time__h6631 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata__h1996 = { 63'd0, rg_msip } ; - assign rdata__h2020 = { 32'd0, crg_timecmp[63:32] } ; - assign rdata__h2026 = { 32'd0, crg_time[63:32] } ; - assign rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 = - rg_msip == f_reqs$D_OUT[8] ; - assign x__h2876 = crg_timecmp & y__h2878 ; - assign x__h4149 = old_time__h6631 & y__h2878 ; - assign x__h5373 = crg_timecmp & y__h5375 ; - assign x__h6674 = old_time__h6631 & y__h5375 ; - assign y__h2877 = f_reqs$D_OUT[71:8] & mask__h2865 ; - assign y__h2878 = - { ~SEXT_f_reqs_first__8_BIT_7_07___d108, - ~SEXT_f_reqs_first__8_BIT_6_10___d111, - ~SEXT_f_reqs_first__8_BIT_5_14___d115, - ~SEXT_f_reqs_first__8_BIT_4_17___d118, - ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign y__h5374 = new_data__h5360 & mask__h5362 ; - assign y__h5375 = - { ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'hFFFFFFFF } ; - always@(byte_addr__h1981 or - rdata__h1996 or - crg_timecmp or rdata__h2020 or crg_time or rdata__h2026) - begin - case (byte_addr__h1981) - 64'h0: rsp_rdata__h2209 = rdata__h1996; - 64'h0000000000000004: rsp_rdata__h2209 = 64'd0; - 64'h0000000000004000: rsp_rdata__h2209 = crg_timecmp; - 64'h0000000000004004: rsp_rdata__h2209 = rdata__h2020; - 64'h000000000000BFF8: rsp_rdata__h2209 = crg_time; - 64'h000000000000BFFC: rsp_rdata__h2209 = rdata__h2026; - default: rsp_rdata__h2209 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8676 = $stime; - #0; - end - v__h8670 = v__h8676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_timer_interrupt_req: %x", - v__h8670, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8808 = $stime; - #0; - end - v__h8802 = v__h8808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_sw_interrupt_req: %x", - v__h8802, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1471 = $stime; - #0; - end - v__h1465 = v__h1471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO.rl_reset", v__h1465); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1868 = $stime; - #0; - end - v__h1862 = v__h1868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_rd_req: rg_mtip = %0d", - v__h1862, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h2065 = $stime; - #0; - end - v__h2059 = v__h2065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_rd_req: unrecognized addr", - v__h2059); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rsp_rdata__h2209, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1714 = $stime; - #0; - end - v__h1708 = v__h1714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h1708, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2442 = $stime; - #0; - end - v__h2436 = v__h2442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_wr_req: rg_mtip = %0d", - v__h2436, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", f_reqs$D_OUT[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h2834); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h2834 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h4107); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h5331); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h5331 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h6632); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h7890 = $stime; - #0; - end - v__h7884 = v__h7890 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_wr_req: unrecognized addr", - v__h7884); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 64'hAAAAAAAAAAAAAAAA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h8258 = $stime; - #0; - end - v__h8252 = v__h8258 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h8252, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h8368 = $stime; - #0; - end - v__h8362 = v__h8368 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h8362, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h8475 = $stime; - #0; - end - v__h8469 = v__h8475 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h8469, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v deleted file mode 100644 index 0883c8da..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v +++ /dev/null @@ -1,2812 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO_AXI4(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h10065; - reg [31 : 0] v__h10197; - reg [31 : 0] v__h1852; - reg [31 : 0] v__h2269; - reg [31 : 0] v__h2453; - reg [31 : 0] v__h2640; - reg [31 : 0] v__h2878; - reg [31 : 0] v__h2095; - reg [31 : 0] v__h3161; - reg [31 : 0] v__h3391; - reg [31 : 0] v__h8927; - reg [31 : 0] v__h9148; - reg [31 : 0] v__h9475; - reg [31 : 0] v__h9585; - reg [31 : 0] v__h9692; - reg [31 : 0] v__h1846; - reg [31 : 0] v__h2089; - reg [31 : 0] v__h2263; - reg [31 : 0] v__h2447; - reg [31 : 0] v__h2634; - reg [31 : 0] v__h2872; - reg [31 : 0] v__h3155; - reg [31 : 0] v__h3385; - reg [31 : 0] v__h8921; - reg [31 : 0] v__h9142; - reg [31 : 0] v__h9469; - reg [31 : 0] v__h9579; - reg [31 : 0] v__h9686; - reg [31 : 0] v__h10059; - reg [31 : 0] v__h10191; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] _theResult___fst__h2566; - reg [1 : 0] _theResult___snd__h2567, v__h3517; - wire [63 : 0] byte_addr__h2405, - byte_addr__h3353, - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190, - mask__h3798, - new_time__h5056, - new_timecmp__h3767, - old_time__h7614, - rdata___1__h2562, - x__h2751, - x__h3809, - x__h5098, - y__h3810, - y__h3811; - wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153; - wire [1 : 0] rresp__h2548, v__h3357; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108, - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53, - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102, - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? new_time__h5056 : 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h7614 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - new_timecmp__h3767 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = - MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - x__h2751, - rresp__h2548, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3357 } ; - assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 = - {8{slave_xactor_f_wr_data$D_OUT[1]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174 = - {8{slave_xactor_f_wr_data$D_OUT[2]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170 = - {8{slave_xactor_f_wr_data$D_OUT[3]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167 = - {8{slave_xactor_f_wr_data$D_OUT[4]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163 = - {8{slave_xactor_f_wr_data$D_OUT[5]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160 = - {8{slave_xactor_f_wr_data$D_OUT[6]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156 = - {8{slave_xactor_f_wr_data$D_OUT[7]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153 = - {8{slave_xactor_f_wr_data$D_OUT[8]}} ; - assign byte_addr__h2405 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign byte_addr__h3353 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190 = - new_timecmp__h3767 - old_time__h7614 ; - assign mask__h3798 = - { SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - assign new_time__h5056 = x__h5098 | y__h3810 ; - assign new_timecmp__h3767 = x__h3809 | y__h3810 ; - assign old_time__h7614 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata___1__h2562 = { 63'd0, rg_msip } ; - assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 = - rg_msip == slave_xactor_f_wr_data$D_OUT[9] ; - assign rresp__h2548 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 2'b11 : - _theResult___snd__h2567 ; - assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 = - slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 = - slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 || - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - f_sw_interrupt_req$FULL_N) ; - assign v__h3357 = - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ? - 2'b11 : - v__h3517 ; - assign x__h2751 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 64'd0 : - _theResult___fst__h2566 ; - assign x__h3809 = crg_timecmp & y__h3811 ; - assign x__h5098 = old_time__h7614 & y__h3811 ; - assign y__h3810 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3798 ; - assign y__h3811 = - { ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - always@(byte_addr__h2405) - begin - case (byte_addr__h2405) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - _theResult___snd__h2567 = 2'b0; - default: _theResult___snd__h2567 = 2'b11; - endcase - end - always@(byte_addr__h2405 or rdata___1__h2562 or crg_timecmp or crg_time) - begin - case (byte_addr__h2405) - 64'h0: _theResult___fst__h2566 = rdata___1__h2562; - 64'h0000000000000004: _theResult___fst__h2566 = 64'd0; - 64'h0000000000004000, 64'h0000000000004004: - _theResult___fst__h2566 = crg_timecmp; - 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___fst__h2566 = crg_time; - default: _theResult___fst__h2566 = 64'd0; - endcase - end - always@(byte_addr__h3353) - begin - case (byte_addr__h3353) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - v__h3517 = 2'b0; - default: v__h3517 = 2'b11; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10065 = $stime; - #0; - end - v__h10059 = v__h10065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x", - v__h10059, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10197 = $stime; - #0; - end - v__h10191 = v__h10197 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x", - v__h10191, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1852 = $stime; - #0; - end - v__h1846 = v__h1852 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1846); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2269 = $stime; - #0; - end - v__h2263 = v__h2269 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", - v__h2263, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - begin - v__h2453 = $stime; - #0; - end - v__h2447 = v__h2453 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2447); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - begin - v__h2640 = $stime; - #0; - end - v__h2634 = v__h2640 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2634); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2878 = $stime; - #0; - end - v__h2872 = v__h2878 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2872); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", x__h2751); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rresp__h2548); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2095 = $stime; - #0; - end - v__h2089 = v__h2095 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h2089, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h3161 = $stime; - #0; - end - v__h3155 = v__h3161 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", - v__h3155, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - begin - v__h3391 = $stime; - #0; - end - v__h3385 = v__h3391 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h3385); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - begin - v__h8927 = $stime; - #0; - end - v__h8921 = v__h8927 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h8921); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h9148 = $stime; - #0; - end - v__h9142 = v__h9148 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9142); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", v__h3357); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h9475 = $stime; - #0; - end - v__h9469 = v__h9475 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9469, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h9585 = $stime; - #0; - end - v__h9579 = v__h9585 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9579, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h9692 = $stime; - #0; - end - v__h9686 = v__h9692 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9686, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO_AXI4 - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v deleted file mode 100644 index f74de61e..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v +++ /dev/null @@ -1,26991 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_show_PLIC_state O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// v_targets_0_m_eip O 1 -// v_targets_1_m_eip O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// v_sources_0_m_interrupt_req_set_not_clear I 1 -// v_sources_1_m_interrupt_req_set_not_clear I 1 -// v_sources_2_m_interrupt_req_set_not_clear I 1 -// v_sources_3_m_interrupt_req_set_not_clear I 1 -// v_sources_4_m_interrupt_req_set_not_clear I 1 -// v_sources_5_m_interrupt_req_set_not_clear I 1 -// v_sources_6_m_interrupt_req_set_not_clear I 1 -// v_sources_7_m_interrupt_req_set_not_clear I 1 -// v_sources_8_m_interrupt_req_set_not_clear I 1 -// v_sources_9_m_interrupt_req_set_not_clear I 1 -// v_sources_10_m_interrupt_req_set_not_clear I 1 -// v_sources_11_m_interrupt_req_set_not_clear I 1 -// v_sources_12_m_interrupt_req_set_not_clear I 1 -// v_sources_13_m_interrupt_req_set_not_clear I 1 -// v_sources_14_m_interrupt_req_set_not_clear I 1 -// v_sources_15_m_interrupt_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_show_PLIC_state I 1 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkPLIC_16_2_7(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_show_PLIC_state, - RDY_show_PLIC_state, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - v_sources_0_m_interrupt_req_set_not_clear, - - v_sources_1_m_interrupt_req_set_not_clear, - - v_sources_2_m_interrupt_req_set_not_clear, - - v_sources_3_m_interrupt_req_set_not_clear, - - v_sources_4_m_interrupt_req_set_not_clear, - - v_sources_5_m_interrupt_req_set_not_clear, - - v_sources_6_m_interrupt_req_set_not_clear, - - v_sources_7_m_interrupt_req_set_not_clear, - - v_sources_8_m_interrupt_req_set_not_clear, - - v_sources_9_m_interrupt_req_set_not_clear, - - v_sources_10_m_interrupt_req_set_not_clear, - - v_sources_11_m_interrupt_req_set_not_clear, - - v_sources_12_m_interrupt_req_set_not_clear, - - v_sources_13_m_interrupt_req_set_not_clear, - - v_sources_14_m_interrupt_req_set_not_clear, - - v_sources_15_m_interrupt_req_set_not_clear, - - v_targets_0_m_eip, - - v_targets_1_m_eip); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method show_PLIC_state - input EN_show_PLIC_state; - output RDY_show_PLIC_state; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // action method v_sources_0_m_interrupt_req - input v_sources_0_m_interrupt_req_set_not_clear; - - // action method v_sources_1_m_interrupt_req - input v_sources_1_m_interrupt_req_set_not_clear; - - // action method v_sources_2_m_interrupt_req - input v_sources_2_m_interrupt_req_set_not_clear; - - // action method v_sources_3_m_interrupt_req - input v_sources_3_m_interrupt_req_set_not_clear; - - // action method v_sources_4_m_interrupt_req - input v_sources_4_m_interrupt_req_set_not_clear; - - // action method v_sources_5_m_interrupt_req - input v_sources_5_m_interrupt_req_set_not_clear; - - // action method v_sources_6_m_interrupt_req - input v_sources_6_m_interrupt_req_set_not_clear; - - // action method v_sources_7_m_interrupt_req - input v_sources_7_m_interrupt_req_set_not_clear; - - // action method v_sources_8_m_interrupt_req - input v_sources_8_m_interrupt_req_set_not_clear; - - // action method v_sources_9_m_interrupt_req - input v_sources_9_m_interrupt_req_set_not_clear; - - // action method v_sources_10_m_interrupt_req - input v_sources_10_m_interrupt_req_set_not_clear; - - // action method v_sources_11_m_interrupt_req - input v_sources_11_m_interrupt_req_set_not_clear; - - // action method v_sources_12_m_interrupt_req - input v_sources_12_m_interrupt_req_set_not_clear; - - // action method v_sources_13_m_interrupt_req - input v_sources_13_m_interrupt_req_set_not_clear; - - // action method v_sources_14_m_interrupt_req - input v_sources_14_m_interrupt_req_set_not_clear; - - // action method v_sources_15_m_interrupt_req - input v_sources_15_m_interrupt_req_set_not_clear; - - // value method v_targets_0_m_eip - output v_targets_0_m_eip; - - // value method v_targets_1_m_eip - output v_targets_1_m_eip; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_verbosity, - RDY_show_PLIC_state, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - v_targets_0_m_eip, - v_targets_1_m_eip; - - // register m_cfg_verbosity - reg [3 : 0] m_cfg_verbosity; - wire [3 : 0] m_cfg_verbosity$D_IN; - wire m_cfg_verbosity$EN; - - // register m_rg_addr_base - reg [63 : 0] m_rg_addr_base; - wire [63 : 0] m_rg_addr_base$D_IN; - wire m_rg_addr_base$EN; - - // register m_rg_addr_lim - reg [63 : 0] m_rg_addr_lim; - wire [63 : 0] m_rg_addr_lim$D_IN; - wire m_rg_addr_lim$EN; - - // register m_vrg_servicing_source_0 - reg [4 : 0] m_vrg_servicing_source_0; - wire [4 : 0] m_vrg_servicing_source_0$D_IN; - wire m_vrg_servicing_source_0$EN; - - // register m_vrg_servicing_source_1 - reg [4 : 0] m_vrg_servicing_source_1; - wire [4 : 0] m_vrg_servicing_source_1$D_IN; - wire m_vrg_servicing_source_1$EN; - - // register m_vrg_source_busy_0 - reg m_vrg_source_busy_0; - wire m_vrg_source_busy_0$D_IN, m_vrg_source_busy_0$EN; - - // register m_vrg_source_busy_1 - reg m_vrg_source_busy_1; - wire m_vrg_source_busy_1$D_IN, m_vrg_source_busy_1$EN; - - // register m_vrg_source_busy_10 - reg m_vrg_source_busy_10; - wire m_vrg_source_busy_10$D_IN, m_vrg_source_busy_10$EN; - - // register m_vrg_source_busy_11 - reg m_vrg_source_busy_11; - wire m_vrg_source_busy_11$D_IN, m_vrg_source_busy_11$EN; - - // register m_vrg_source_busy_12 - reg m_vrg_source_busy_12; - wire m_vrg_source_busy_12$D_IN, m_vrg_source_busy_12$EN; - - // register m_vrg_source_busy_13 - reg m_vrg_source_busy_13; - wire m_vrg_source_busy_13$D_IN, m_vrg_source_busy_13$EN; - - // register m_vrg_source_busy_14 - reg m_vrg_source_busy_14; - wire m_vrg_source_busy_14$D_IN, m_vrg_source_busy_14$EN; - - // register m_vrg_source_busy_15 - reg m_vrg_source_busy_15; - wire m_vrg_source_busy_15$D_IN, m_vrg_source_busy_15$EN; - - // register m_vrg_source_busy_16 - reg m_vrg_source_busy_16; - wire m_vrg_source_busy_16$D_IN, m_vrg_source_busy_16$EN; - - // register m_vrg_source_busy_2 - reg m_vrg_source_busy_2; - wire m_vrg_source_busy_2$D_IN, m_vrg_source_busy_2$EN; - - // register m_vrg_source_busy_3 - reg m_vrg_source_busy_3; - wire m_vrg_source_busy_3$D_IN, m_vrg_source_busy_3$EN; - - // register m_vrg_source_busy_4 - reg m_vrg_source_busy_4; - wire m_vrg_source_busy_4$D_IN, m_vrg_source_busy_4$EN; - - // register m_vrg_source_busy_5 - reg m_vrg_source_busy_5; - wire m_vrg_source_busy_5$D_IN, m_vrg_source_busy_5$EN; - - // register m_vrg_source_busy_6 - reg m_vrg_source_busy_6; - wire m_vrg_source_busy_6$D_IN, m_vrg_source_busy_6$EN; - - // register m_vrg_source_busy_7 - reg m_vrg_source_busy_7; - wire m_vrg_source_busy_7$D_IN, m_vrg_source_busy_7$EN; - - // register m_vrg_source_busy_8 - reg m_vrg_source_busy_8; - wire m_vrg_source_busy_8$D_IN, m_vrg_source_busy_8$EN; - - // register m_vrg_source_busy_9 - reg m_vrg_source_busy_9; - wire m_vrg_source_busy_9$D_IN, m_vrg_source_busy_9$EN; - - // register m_vrg_source_ip_0 - reg m_vrg_source_ip_0; - wire m_vrg_source_ip_0$D_IN, m_vrg_source_ip_0$EN; - - // register m_vrg_source_ip_1 - reg m_vrg_source_ip_1; - wire m_vrg_source_ip_1$D_IN, m_vrg_source_ip_1$EN; - - // register m_vrg_source_ip_10 - reg m_vrg_source_ip_10; - wire m_vrg_source_ip_10$D_IN, m_vrg_source_ip_10$EN; - - // register m_vrg_source_ip_11 - reg m_vrg_source_ip_11; - wire m_vrg_source_ip_11$D_IN, m_vrg_source_ip_11$EN; - - // register m_vrg_source_ip_12 - reg m_vrg_source_ip_12; - wire m_vrg_source_ip_12$D_IN, m_vrg_source_ip_12$EN; - - // register m_vrg_source_ip_13 - reg m_vrg_source_ip_13; - wire m_vrg_source_ip_13$D_IN, m_vrg_source_ip_13$EN; - - // register m_vrg_source_ip_14 - reg m_vrg_source_ip_14; - wire m_vrg_source_ip_14$D_IN, m_vrg_source_ip_14$EN; - - // register m_vrg_source_ip_15 - reg m_vrg_source_ip_15; - wire m_vrg_source_ip_15$D_IN, m_vrg_source_ip_15$EN; - - // register m_vrg_source_ip_16 - reg m_vrg_source_ip_16; - wire m_vrg_source_ip_16$D_IN, m_vrg_source_ip_16$EN; - - // register m_vrg_source_ip_2 - reg m_vrg_source_ip_2; - wire m_vrg_source_ip_2$D_IN, m_vrg_source_ip_2$EN; - - // register m_vrg_source_ip_3 - reg m_vrg_source_ip_3; - wire m_vrg_source_ip_3$D_IN, m_vrg_source_ip_3$EN; - - // register m_vrg_source_ip_4 - reg m_vrg_source_ip_4; - wire m_vrg_source_ip_4$D_IN, m_vrg_source_ip_4$EN; - - // register m_vrg_source_ip_5 - reg m_vrg_source_ip_5; - wire m_vrg_source_ip_5$D_IN, m_vrg_source_ip_5$EN; - - // register m_vrg_source_ip_6 - reg m_vrg_source_ip_6; - wire m_vrg_source_ip_6$D_IN, m_vrg_source_ip_6$EN; - - // register m_vrg_source_ip_7 - reg m_vrg_source_ip_7; - wire m_vrg_source_ip_7$D_IN, m_vrg_source_ip_7$EN; - - // register m_vrg_source_ip_8 - reg m_vrg_source_ip_8; - wire m_vrg_source_ip_8$D_IN, m_vrg_source_ip_8$EN; - - // register m_vrg_source_ip_9 - reg m_vrg_source_ip_9; - wire m_vrg_source_ip_9$D_IN, m_vrg_source_ip_9$EN; - - // register m_vrg_source_prio_0 - reg [2 : 0] m_vrg_source_prio_0; - wire [2 : 0] m_vrg_source_prio_0$D_IN; - wire m_vrg_source_prio_0$EN; - - // register m_vrg_source_prio_1 - reg [2 : 0] m_vrg_source_prio_1; - wire [2 : 0] m_vrg_source_prio_1$D_IN; - wire m_vrg_source_prio_1$EN; - - // register m_vrg_source_prio_10 - reg [2 : 0] m_vrg_source_prio_10; - wire [2 : 0] m_vrg_source_prio_10$D_IN; - wire m_vrg_source_prio_10$EN; - - // register m_vrg_source_prio_11 - reg [2 : 0] m_vrg_source_prio_11; - wire [2 : 0] m_vrg_source_prio_11$D_IN; - wire m_vrg_source_prio_11$EN; - - // register m_vrg_source_prio_12 - reg [2 : 0] m_vrg_source_prio_12; - wire [2 : 0] m_vrg_source_prio_12$D_IN; - wire m_vrg_source_prio_12$EN; - - // register m_vrg_source_prio_13 - reg [2 : 0] m_vrg_source_prio_13; - wire [2 : 0] m_vrg_source_prio_13$D_IN; - wire m_vrg_source_prio_13$EN; - - // register m_vrg_source_prio_14 - reg [2 : 0] m_vrg_source_prio_14; - wire [2 : 0] m_vrg_source_prio_14$D_IN; - wire m_vrg_source_prio_14$EN; - - // register m_vrg_source_prio_15 - reg [2 : 0] m_vrg_source_prio_15; - wire [2 : 0] m_vrg_source_prio_15$D_IN; - wire m_vrg_source_prio_15$EN; - - // register m_vrg_source_prio_16 - reg [2 : 0] m_vrg_source_prio_16; - wire [2 : 0] m_vrg_source_prio_16$D_IN; - wire m_vrg_source_prio_16$EN; - - // register m_vrg_source_prio_2 - reg [2 : 0] m_vrg_source_prio_2; - wire [2 : 0] m_vrg_source_prio_2$D_IN; - wire m_vrg_source_prio_2$EN; - - // register m_vrg_source_prio_3 - reg [2 : 0] m_vrg_source_prio_3; - wire [2 : 0] m_vrg_source_prio_3$D_IN; - wire m_vrg_source_prio_3$EN; - - // register m_vrg_source_prio_4 - reg [2 : 0] m_vrg_source_prio_4; - wire [2 : 0] m_vrg_source_prio_4$D_IN; - wire m_vrg_source_prio_4$EN; - - // register m_vrg_source_prio_5 - reg [2 : 0] m_vrg_source_prio_5; - wire [2 : 0] m_vrg_source_prio_5$D_IN; - wire m_vrg_source_prio_5$EN; - - // register m_vrg_source_prio_6 - reg [2 : 0] m_vrg_source_prio_6; - wire [2 : 0] m_vrg_source_prio_6$D_IN; - wire m_vrg_source_prio_6$EN; - - // register m_vrg_source_prio_7 - reg [2 : 0] m_vrg_source_prio_7; - wire [2 : 0] m_vrg_source_prio_7$D_IN; - wire m_vrg_source_prio_7$EN; - - // register m_vrg_source_prio_8 - reg [2 : 0] m_vrg_source_prio_8; - wire [2 : 0] m_vrg_source_prio_8$D_IN; - wire m_vrg_source_prio_8$EN; - - // register m_vrg_source_prio_9 - reg [2 : 0] m_vrg_source_prio_9; - wire [2 : 0] m_vrg_source_prio_9$D_IN; - wire m_vrg_source_prio_9$EN; - - // register m_vrg_target_threshold_0 - reg [2 : 0] m_vrg_target_threshold_0; - wire [2 : 0] m_vrg_target_threshold_0$D_IN; - wire m_vrg_target_threshold_0$EN; - - // register m_vrg_target_threshold_1 - reg [2 : 0] m_vrg_target_threshold_1; - wire [2 : 0] m_vrg_target_threshold_1$D_IN; - wire m_vrg_target_threshold_1$EN; - - // register m_vvrg_ie_0_0 - reg m_vvrg_ie_0_0; - wire m_vvrg_ie_0_0$D_IN, m_vvrg_ie_0_0$EN; - - // register m_vvrg_ie_0_1 - reg m_vvrg_ie_0_1; - wire m_vvrg_ie_0_1$D_IN, m_vvrg_ie_0_1$EN; - - // register m_vvrg_ie_0_10 - reg m_vvrg_ie_0_10; - wire m_vvrg_ie_0_10$D_IN, m_vvrg_ie_0_10$EN; - - // register m_vvrg_ie_0_11 - reg m_vvrg_ie_0_11; - wire m_vvrg_ie_0_11$D_IN, m_vvrg_ie_0_11$EN; - - // register m_vvrg_ie_0_12 - reg m_vvrg_ie_0_12; - wire m_vvrg_ie_0_12$D_IN, m_vvrg_ie_0_12$EN; - - // register m_vvrg_ie_0_13 - reg m_vvrg_ie_0_13; - wire m_vvrg_ie_0_13$D_IN, m_vvrg_ie_0_13$EN; - - // register m_vvrg_ie_0_14 - reg m_vvrg_ie_0_14; - wire m_vvrg_ie_0_14$D_IN, m_vvrg_ie_0_14$EN; - - // register m_vvrg_ie_0_15 - reg m_vvrg_ie_0_15; - wire m_vvrg_ie_0_15$D_IN, m_vvrg_ie_0_15$EN; - - // register m_vvrg_ie_0_16 - reg m_vvrg_ie_0_16; - wire m_vvrg_ie_0_16$D_IN, m_vvrg_ie_0_16$EN; - - // register m_vvrg_ie_0_2 - reg m_vvrg_ie_0_2; - wire m_vvrg_ie_0_2$D_IN, m_vvrg_ie_0_2$EN; - - // register m_vvrg_ie_0_3 - reg m_vvrg_ie_0_3; - wire m_vvrg_ie_0_3$D_IN, m_vvrg_ie_0_3$EN; - - // register m_vvrg_ie_0_4 - reg m_vvrg_ie_0_4; - wire m_vvrg_ie_0_4$D_IN, m_vvrg_ie_0_4$EN; - - // register m_vvrg_ie_0_5 - reg m_vvrg_ie_0_5; - wire m_vvrg_ie_0_5$D_IN, m_vvrg_ie_0_5$EN; - - // register m_vvrg_ie_0_6 - reg m_vvrg_ie_0_6; - wire m_vvrg_ie_0_6$D_IN, m_vvrg_ie_0_6$EN; - - // register m_vvrg_ie_0_7 - reg m_vvrg_ie_0_7; - wire m_vvrg_ie_0_7$D_IN, m_vvrg_ie_0_7$EN; - - // register m_vvrg_ie_0_8 - reg m_vvrg_ie_0_8; - wire m_vvrg_ie_0_8$D_IN, m_vvrg_ie_0_8$EN; - - // register m_vvrg_ie_0_9 - reg m_vvrg_ie_0_9; - wire m_vvrg_ie_0_9$D_IN, m_vvrg_ie_0_9$EN; - - // register m_vvrg_ie_1_0 - reg m_vvrg_ie_1_0; - wire m_vvrg_ie_1_0$D_IN, m_vvrg_ie_1_0$EN; - - // register m_vvrg_ie_1_1 - reg m_vvrg_ie_1_1; - wire m_vvrg_ie_1_1$D_IN, m_vvrg_ie_1_1$EN; - - // register m_vvrg_ie_1_10 - reg m_vvrg_ie_1_10; - wire m_vvrg_ie_1_10$D_IN, m_vvrg_ie_1_10$EN; - - // register m_vvrg_ie_1_11 - reg m_vvrg_ie_1_11; - wire m_vvrg_ie_1_11$D_IN, m_vvrg_ie_1_11$EN; - - // register m_vvrg_ie_1_12 - reg m_vvrg_ie_1_12; - wire m_vvrg_ie_1_12$D_IN, m_vvrg_ie_1_12$EN; - - // register m_vvrg_ie_1_13 - reg m_vvrg_ie_1_13; - wire m_vvrg_ie_1_13$D_IN, m_vvrg_ie_1_13$EN; - - // register m_vvrg_ie_1_14 - reg m_vvrg_ie_1_14; - wire m_vvrg_ie_1_14$D_IN, m_vvrg_ie_1_14$EN; - - // register m_vvrg_ie_1_15 - reg m_vvrg_ie_1_15; - wire m_vvrg_ie_1_15$D_IN, m_vvrg_ie_1_15$EN; - - // register m_vvrg_ie_1_16 - reg m_vvrg_ie_1_16; - wire m_vvrg_ie_1_16$D_IN, m_vvrg_ie_1_16$EN; - - // register m_vvrg_ie_1_2 - reg m_vvrg_ie_1_2; - wire m_vvrg_ie_1_2$D_IN, m_vvrg_ie_1_2$EN; - - // register m_vvrg_ie_1_3 - reg m_vvrg_ie_1_3; - wire m_vvrg_ie_1_3$D_IN, m_vvrg_ie_1_3$EN; - - // register m_vvrg_ie_1_4 - reg m_vvrg_ie_1_4; - wire m_vvrg_ie_1_4$D_IN, m_vvrg_ie_1_4$EN; - - // register m_vvrg_ie_1_5 - reg m_vvrg_ie_1_5; - wire m_vvrg_ie_1_5$D_IN, m_vvrg_ie_1_5$EN; - - // register m_vvrg_ie_1_6 - reg m_vvrg_ie_1_6; - wire m_vvrg_ie_1_6$D_IN, m_vvrg_ie_1_6$EN; - - // register m_vvrg_ie_1_7 - reg m_vvrg_ie_1_7; - wire m_vvrg_ie_1_7$D_IN, m_vvrg_ie_1_7$EN; - - // register m_vvrg_ie_1_8 - reg m_vvrg_ie_1_8; - wire m_vvrg_ie_1_8$D_IN, m_vvrg_ie_1_8$EN; - - // register m_vvrg_ie_1_9 - reg m_vvrg_ie_1_9; - wire m_vvrg_ie_1_9$D_IN, m_vvrg_ie_1_9$EN; - - // ports of submodule m_f_reset_reqs - wire m_f_reset_reqs$CLR, - m_f_reset_reqs$DEQ, - m_f_reset_reqs$EMPTY_N, - m_f_reset_reqs$ENQ, - m_f_reset_reqs$FULL_N; - - // ports of submodule m_f_reset_rsps - wire m_f_reset_rsps$CLR, - m_f_reset_rsps$DEQ, - m_f_reset_rsps$EMPTY_N, - m_f_reset_rsps$ENQ, - m_f_reset_rsps$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_addr - wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT; - wire m_slave_xactor_f_rd_addr$CLR, - m_slave_xactor_f_rd_addr$DEQ, - m_slave_xactor_f_rd_addr$EMPTY_N, - m_slave_xactor_f_rd_addr$ENQ, - m_slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_data - wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT; - wire m_slave_xactor_f_rd_data$CLR, - m_slave_xactor_f_rd_data$DEQ, - m_slave_xactor_f_rd_data$EMPTY_N, - m_slave_xactor_f_rd_data$ENQ, - m_slave_xactor_f_rd_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_addr - wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT; - wire m_slave_xactor_f_wr_addr$CLR, - m_slave_xactor_f_wr_addr$DEQ, - m_slave_xactor_f_wr_addr$EMPTY_N, - m_slave_xactor_f_wr_addr$ENQ, - m_slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; - wire m_slave_xactor_f_wr_data$CLR, - m_slave_xactor_f_wr_data$DEQ, - m_slave_xactor_f_wr_data$EMPTY_N, - m_slave_xactor_f_wr_data$ENQ, - m_slave_xactor_f_wr_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_resp - wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT; - wire m_slave_xactor_f_wr_resp$CLR, - m_slave_xactor_f_wr_resp$DEQ, - m_slave_xactor_f_wr_resp$EMPTY_N, - m_slave_xactor_f_wr_resp$ENQ, - m_slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_process_rd_req, - CAN_FIRE_RL_m_rl_process_wr_req, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_verbosity, - CAN_FIRE_show_PLIC_state, - CAN_FIRE_v_sources_0_m_interrupt_req, - CAN_FIRE_v_sources_10_m_interrupt_req, - CAN_FIRE_v_sources_11_m_interrupt_req, - CAN_FIRE_v_sources_12_m_interrupt_req, - CAN_FIRE_v_sources_13_m_interrupt_req, - CAN_FIRE_v_sources_14_m_interrupt_req, - CAN_FIRE_v_sources_15_m_interrupt_req, - CAN_FIRE_v_sources_1_m_interrupt_req, - CAN_FIRE_v_sources_2_m_interrupt_req, - CAN_FIRE_v_sources_3_m_interrupt_req, - CAN_FIRE_v_sources_4_m_interrupt_req, - CAN_FIRE_v_sources_5_m_interrupt_req, - CAN_FIRE_v_sources_6_m_interrupt_req, - CAN_FIRE_v_sources_7_m_interrupt_req, - CAN_FIRE_v_sources_8_m_interrupt_req, - CAN_FIRE_v_sources_9_m_interrupt_req, - WILL_FIRE_RL_m_rl_process_rd_req, - WILL_FIRE_RL_m_rl_process_wr_req, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_verbosity, - WILL_FIRE_show_PLIC_state, - WILL_FIRE_v_sources_0_m_interrupt_req, - WILL_FIRE_v_sources_10_m_interrupt_req, - WILL_FIRE_v_sources_11_m_interrupt_req, - WILL_FIRE_v_sources_12_m_interrupt_req, - WILL_FIRE_v_sources_13_m_interrupt_req, - WILL_FIRE_v_sources_14_m_interrupt_req, - WILL_FIRE_v_sources_15_m_interrupt_req, - WILL_FIRE_v_sources_1_m_interrupt_req, - WILL_FIRE_v_sources_2_m_interrupt_req, - WILL_FIRE_v_sources_3_m_interrupt_req, - WILL_FIRE_v_sources_4_m_interrupt_req, - WILL_FIRE_v_sources_5_m_interrupt_req, - WILL_FIRE_v_sources_6_m_interrupt_req, - WILL_FIRE_v_sources_7_m_interrupt_req, - WILL_FIRE_v_sources_8_m_interrupt_req, - WILL_FIRE_v_sources_9_m_interrupt_req; - - // inputs to muxes for submodule ports - wire MUX_m_vrg_servicing_source_0$write_1__SEL_1, - MUX_m_vrg_servicing_source_1$write_1__SEL_1, - MUX_m_vrg_source_busy_0$write_1__SEL_2, - MUX_m_vrg_source_busy_1$write_1__SEL_1, - MUX_m_vrg_source_busy_1$write_1__SEL_2, - MUX_m_vrg_source_busy_10$write_1__SEL_1, - MUX_m_vrg_source_busy_10$write_1__SEL_2, - MUX_m_vrg_source_busy_11$write_1__SEL_1, - MUX_m_vrg_source_busy_11$write_1__SEL_2, - MUX_m_vrg_source_busy_12$write_1__SEL_1, - MUX_m_vrg_source_busy_12$write_1__SEL_2, - MUX_m_vrg_source_busy_13$write_1__SEL_1, - MUX_m_vrg_source_busy_13$write_1__SEL_2, - MUX_m_vrg_source_busy_14$write_1__SEL_1, - MUX_m_vrg_source_busy_14$write_1__SEL_2, - MUX_m_vrg_source_busy_15$write_1__SEL_1, - MUX_m_vrg_source_busy_15$write_1__SEL_2, - MUX_m_vrg_source_busy_16$write_1__SEL_1, - MUX_m_vrg_source_busy_16$write_1__SEL_2, - MUX_m_vrg_source_busy_2$write_1__SEL_1, - MUX_m_vrg_source_busy_2$write_1__SEL_2, - MUX_m_vrg_source_busy_3$write_1__SEL_1, - MUX_m_vrg_source_busy_3$write_1__SEL_2, - MUX_m_vrg_source_busy_4$write_1__SEL_1, - MUX_m_vrg_source_busy_4$write_1__SEL_2, - MUX_m_vrg_source_busy_5$write_1__SEL_1, - MUX_m_vrg_source_busy_5$write_1__SEL_2, - MUX_m_vrg_source_busy_6$write_1__SEL_1, - MUX_m_vrg_source_busy_6$write_1__SEL_2, - MUX_m_vrg_source_busy_7$write_1__SEL_1, - MUX_m_vrg_source_busy_7$write_1__SEL_2, - MUX_m_vrg_source_busy_8$write_1__SEL_1, - MUX_m_vrg_source_busy_8$write_1__SEL_2, - MUX_m_vrg_source_busy_9$write_1__SEL_1, - MUX_m_vrg_source_busy_9$write_1__SEL_2, - MUX_m_vrg_source_prio_0$write_1__SEL_1, - MUX_m_vrg_source_prio_1$write_1__SEL_1, - MUX_m_vrg_source_prio_10$write_1__SEL_1, - MUX_m_vrg_source_prio_11$write_1__SEL_1, - MUX_m_vrg_source_prio_12$write_1__SEL_1, - MUX_m_vrg_source_prio_13$write_1__SEL_1, - MUX_m_vrg_source_prio_14$write_1__SEL_1, - MUX_m_vrg_source_prio_15$write_1__SEL_1, - MUX_m_vrg_source_prio_16$write_1__SEL_1, - MUX_m_vrg_source_prio_2$write_1__SEL_1, - MUX_m_vrg_source_prio_3$write_1__SEL_1, - MUX_m_vrg_source_prio_4$write_1__SEL_1, - MUX_m_vrg_source_prio_5$write_1__SEL_1, - MUX_m_vrg_source_prio_6$write_1__SEL_1, - MUX_m_vrg_source_prio_7$write_1__SEL_1, - MUX_m_vrg_source_prio_8$write_1__SEL_1, - MUX_m_vrg_source_prio_9$write_1__SEL_1, - MUX_m_vrg_target_threshold_0$write_1__SEL_1, - MUX_m_vrg_target_threshold_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__VAL_1, - MUX_m_vvrg_ie_0_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_1$write_1__VAL_1, - MUX_m_vvrg_ie_0_10$write_1__SEL_1, - MUX_m_vvrg_ie_0_10$write_1__VAL_1, - MUX_m_vvrg_ie_0_11$write_1__SEL_1, - MUX_m_vvrg_ie_0_11$write_1__VAL_1, - MUX_m_vvrg_ie_0_12$write_1__SEL_1, - MUX_m_vvrg_ie_0_12$write_1__VAL_1, - MUX_m_vvrg_ie_0_13$write_1__SEL_1, - MUX_m_vvrg_ie_0_13$write_1__VAL_1, - MUX_m_vvrg_ie_0_14$write_1__SEL_1, - MUX_m_vvrg_ie_0_14$write_1__VAL_1, - MUX_m_vvrg_ie_0_15$write_1__SEL_1, - MUX_m_vvrg_ie_0_15$write_1__VAL_1, - MUX_m_vvrg_ie_0_16$write_1__SEL_1, - MUX_m_vvrg_ie_0_16$write_1__VAL_1, - MUX_m_vvrg_ie_0_2$write_1__SEL_1, - MUX_m_vvrg_ie_0_2$write_1__VAL_1, - MUX_m_vvrg_ie_0_3$write_1__SEL_1, - MUX_m_vvrg_ie_0_3$write_1__VAL_1, - MUX_m_vvrg_ie_0_4$write_1__SEL_1, - MUX_m_vvrg_ie_0_4$write_1__VAL_1, - MUX_m_vvrg_ie_0_5$write_1__SEL_1, - MUX_m_vvrg_ie_0_5$write_1__VAL_1, - MUX_m_vvrg_ie_0_6$write_1__SEL_1, - MUX_m_vvrg_ie_0_6$write_1__VAL_1, - MUX_m_vvrg_ie_0_7$write_1__SEL_1, - MUX_m_vvrg_ie_0_7$write_1__VAL_1, - MUX_m_vvrg_ie_0_8$write_1__SEL_1, - MUX_m_vvrg_ie_0_8$write_1__VAL_1, - MUX_m_vvrg_ie_0_9$write_1__SEL_1, - MUX_m_vvrg_ie_0_9$write_1__VAL_1, - MUX_m_vvrg_ie_1_0$write_1__SEL_1, - MUX_m_vvrg_ie_1_0$write_1__VAL_1, - MUX_m_vvrg_ie_1_1$write_1__SEL_1, - MUX_m_vvrg_ie_1_1$write_1__VAL_1, - MUX_m_vvrg_ie_1_10$write_1__SEL_1, - MUX_m_vvrg_ie_1_10$write_1__VAL_1, - MUX_m_vvrg_ie_1_11$write_1__SEL_1, - MUX_m_vvrg_ie_1_11$write_1__VAL_1, - MUX_m_vvrg_ie_1_12$write_1__SEL_1, - MUX_m_vvrg_ie_1_12$write_1__VAL_1, - MUX_m_vvrg_ie_1_13$write_1__SEL_1, - MUX_m_vvrg_ie_1_13$write_1__VAL_1, - MUX_m_vvrg_ie_1_14$write_1__SEL_1, - MUX_m_vvrg_ie_1_14$write_1__VAL_1, - MUX_m_vvrg_ie_1_15$write_1__SEL_1, - MUX_m_vvrg_ie_1_15$write_1__VAL_1, - MUX_m_vvrg_ie_1_16$write_1__SEL_1, - MUX_m_vvrg_ie_1_16$write_1__VAL_1, - MUX_m_vvrg_ie_1_2$write_1__SEL_1, - MUX_m_vvrg_ie_1_2$write_1__VAL_1, - MUX_m_vvrg_ie_1_3$write_1__SEL_1, - MUX_m_vvrg_ie_1_3$write_1__VAL_1, - MUX_m_vvrg_ie_1_4$write_1__SEL_1, - MUX_m_vvrg_ie_1_4$write_1__VAL_1, - MUX_m_vvrg_ie_1_5$write_1__SEL_1, - MUX_m_vvrg_ie_1_5$write_1__VAL_1, - MUX_m_vvrg_ie_1_6$write_1__SEL_1, - MUX_m_vvrg_ie_1_6$write_1__VAL_1, - MUX_m_vvrg_ie_1_7$write_1__SEL_1, - MUX_m_vvrg_ie_1_7$write_1__VAL_1, - MUX_m_vvrg_ie_1_8$write_1__SEL_1, - MUX_m_vvrg_ie_1_8$write_1__VAL_1, - MUX_m_vvrg_ie_1_9$write_1__SEL_1, - MUX_m_vvrg_ie_1_9$write_1__VAL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h75676; - reg [31 : 0] v__h75874; - reg [31 : 0] v__h76072; - reg [31 : 0] v__h76270; - reg [31 : 0] v__h76468; - reg [31 : 0] v__h76666; - reg [31 : 0] v__h76864; - reg [31 : 0] v__h77062; - reg [31 : 0] v__h77260; - reg [31 : 0] v__h77458; - reg [31 : 0] v__h77656; - reg [31 : 0] v__h77854; - reg [31 : 0] v__h78052; - reg [31 : 0] v__h78250; - reg [31 : 0] v__h78448; - reg [31 : 0] v__h78646; - reg [31 : 0] v__h6144; - reg [31 : 0] v__h13080; - reg [31 : 0] v__h13265; - reg [31 : 0] v__h13463; - reg [31 : 0] v__h13713; - reg [31 : 0] v__h18186; - reg [31 : 0] v__h23802; - reg [31 : 0] v__h25975; - reg [31 : 0] v__h24056; - reg [31 : 0] v__h26250; - reg [31 : 0] v__h26463; - reg [31 : 0] v__h26740; - reg [31 : 0] v__h26968; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h28048; - reg [31 : 0] v__h67030; - reg [31 : 0] v__h67318; - reg [31 : 0] v__h67847; - reg [31 : 0] v__h67933; - reg [31 : 0] v__h68132; - reg [31 : 0] v__h68353; - reg [31 : 0] v__h74690; - reg [31 : 0] v__h74800; - reg [31 : 0] v__h74913; - reg [31 : 0] v__h6138; - reg [31 : 0] v__h13074; - reg [31 : 0] v__h13259; - reg [31 : 0] v__h13457; - reg [31 : 0] v__h13707; - reg [31 : 0] v__h18180; - reg [31 : 0] v__h23796; - reg [31 : 0] v__h24050; - reg [31 : 0] v__h25969; - reg [31 : 0] v__h26244; - reg [31 : 0] v__h26457; - reg [31 : 0] v__h26734; - reg [31 : 0] v__h26962; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28042; - reg [31 : 0] v__h67024; - reg [31 : 0] v__h67312; - reg [31 : 0] v__h67841; - reg [31 : 0] v__h67927; - reg [31 : 0] v__h68126; - reg [31 : 0] v__h68347; - reg [31 : 0] v__h74684; - reg [31 : 0] v__h74794; - reg [31 : 0] v__h74907; - reg [31 : 0] v__h75670; - reg [31 : 0] v__h75868; - reg [31 : 0] v__h76066; - reg [31 : 0] v__h76264; - reg [31 : 0] v__h76462; - reg [31 : 0] v__h76660; - reg [31 : 0] v__h76858; - reg [31 : 0] v__h77056; - reg [31 : 0] v__h77254; - reg [31 : 0] v__h77452; - reg [31 : 0] v__h77650; - reg [31 : 0] v__h77848; - reg [31 : 0] v__h78046; - reg [31 : 0] v__h78244; - reg [31 : 0] v__h78442; - reg [31 : 0] v__h78640; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] y_avValue_fst__h26148; - reg [4 : 0] x__h24011, x__h67487; - reg [2 : 0] x__h13493, x__h23832; - reg [1 : 0] v__h67107, y_avValue_snd__h26149; - reg CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - wire [63 : 0] addr_offset__h13216, - addr_offset__h26929, - rdata___1__h26404, - rdata__h26202, - v__h13422, - v__h13671, - v__h18144, - v__h23761, - v__h25455, - v__h25474, - x__h26361, - y_avValue_fst__h26094, - y_avValue_fst__h26115, - y_avValue_fst__h26127, - y_avValue_fst__h26143, - y_avValue_fst__h26159, - y_avValue_fst__h26164, - y_avValue_fst__h26175, - y_avValue_fst__h26180, - y_avValue_fst__h26194; - wire [31 : 0] v_ie__h18147, - v_ip__h13674, - wdata32__h26930, - x__h23673, - x__h67110; - wire [9 : 0] source_id__h15665, - source_id__h15772, - source_id__h15845, - source_id__h15918, - source_id__h15991, - source_id__h16064, - source_id__h16137, - source_id__h16210, - source_id__h16283, - source_id__h16356, - source_id__h16429, - source_id__h16502, - source_id__h16575, - source_id__h16648, - source_id__h16721, - source_id__h16794, - source_id__h16867, - source_id__h16940, - source_id__h17013, - source_id__h17086, - source_id__h17159, - source_id__h17232, - source_id__h17305, - source_id__h17378, - source_id__h17451, - source_id__h17524, - source_id__h17597, - source_id__h17670, - source_id__h17743, - source_id__h17816, - source_id__h17889, - source_id__h20137, - source_id__h20313, - source_id__h20421, - source_id__h20529, - source_id__h20637, - source_id__h20745, - source_id__h20853, - source_id__h20961, - source_id__h21069, - source_id__h21177, - source_id__h21285, - source_id__h21393, - source_id__h21501, - source_id__h21609, - source_id__h21717, - source_id__h21825, - source_id__h21933, - source_id__h22041, - source_id__h22149, - source_id__h22257, - source_id__h22365, - source_id__h22473, - source_id__h22581, - source_id__h22689, - source_id__h22797, - source_id__h22905, - source_id__h23013, - source_id__h23121, - source_id__h23229, - source_id__h23337, - source_id__h23445, - source_id__h29475, - source_id__h30685, - source_id__h31895, - source_id__h33105, - source_id__h34315, - source_id__h35525, - source_id__h36735, - source_id__h37945, - source_id__h39155, - source_id__h40365, - source_id__h41575, - source_id__h42785, - source_id__h43995, - source_id__h45205, - source_id__h46415, - source_id__h47625, - source_id__h48835, - source_id__h50045, - source_id__h51255, - source_id__h52465, - source_id__h53675, - source_id__h54885, - source_id__h56095, - source_id__h57305, - source_id__h58515, - source_id__h59725, - source_id__h60935, - source_id__h62145, - source_id__h63355, - source_id__h64565, - source_id__h65775, - source_id__h67436, - source_id_base__h13630, - source_id_base__h28148; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71313, - b__h73318, - max_id__h23959; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71312, - a__h73317; - wire [1 : 0] rresp__h26203, - v__h26934, - v__h27094, - v__h27107, - v__h27942, - v__h27961, - v__h28125, - v__h28144, - v__h67144, - v__h67432, - v__h67476, - y_avValue_snd__h26095, - y_avValue_snd__h26116, - y_avValue_snd__h26128, - y_avValue_snd__h26144, - y_avValue_snd__h26160, - y_avValue_snd__h26165, - y_avValue_snd__h26176, - y_avValue_snd__h26181, - y_avValue_snd__h26195; - wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, - NOT_m_cfg_verbosity_read_ULE_1_5___d16, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - 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m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, - m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method show_PLIC_state - assign RDY_show_PLIC_state = 1'd1 ; - assign CAN_FIRE_show_PLIC_state = 1'd1 ; - assign WILL_FIRE_show_PLIC_state = EN_show_PLIC_state ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // action method v_sources_0_m_interrupt_req - assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - - // action method v_sources_1_m_interrupt_req - assign CAN_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - - // action method v_sources_2_m_interrupt_req - assign CAN_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - - // action method v_sources_3_m_interrupt_req - assign CAN_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - - // action method v_sources_4_m_interrupt_req - assign CAN_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - - // action method v_sources_5_m_interrupt_req - assign CAN_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - - // action method v_sources_6_m_interrupt_req - assign CAN_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - - // action method v_sources_7_m_interrupt_req - assign CAN_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - - // action method v_sources_8_m_interrupt_req - assign CAN_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - - // action method v_sources_9_m_interrupt_req - assign CAN_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - - // action method v_sources_10_m_interrupt_req - assign CAN_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - - // action method v_sources_11_m_interrupt_req - assign CAN_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - - // action method v_sources_12_m_interrupt_req - assign CAN_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - - // action method v_sources_13_m_interrupt_req - assign CAN_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - - // action method v_sources_14_m_interrupt_req - assign CAN_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - - // action method v_sources_15_m_interrupt_req - assign CAN_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - - // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71312 > m_vrg_target_threshold_0 ; - - // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73317 > m_vrg_target_threshold_1 ; - - // submodule m_f_reset_reqs - FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_reqs$ENQ), - .DEQ(m_f_reset_reqs$DEQ), - .CLR(m_f_reset_reqs$CLR), - .FULL_N(m_f_reset_reqs$FULL_N), - .EMPTY_N(m_f_reset_reqs$EMPTY_N)); - - // submodule m_f_reset_rsps - FIFO20 #(.guarded(32'd1)) m_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_rsps$ENQ), - .DEQ(m_f_reset_rsps$DEQ), - .CLR(m_f_reset_rsps$CLR), - .FULL_N(m_f_reset_rsps$FULL_N), - .EMPTY_N(m_f_reset_rsps$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_addr$D_IN), - .ENQ(m_slave_xactor_f_rd_addr$ENQ), - .DEQ(m_slave_xactor_f_rd_addr$DEQ), - .CLR(m_slave_xactor_f_rd_addr$CLR), - .D_OUT(m_slave_xactor_f_rd_addr$D_OUT), - .FULL_N(m_slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_data$D_IN), - .ENQ(m_slave_xactor_f_rd_data$ENQ), - .DEQ(m_slave_xactor_f_rd_data$DEQ), - .CLR(m_slave_xactor_f_rd_data$CLR), - .D_OUT(m_slave_xactor_f_rd_data$D_OUT), - .FULL_N(m_slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_addr$D_IN), - .ENQ(m_slave_xactor_f_wr_addr$ENQ), - .DEQ(m_slave_xactor_f_wr_addr$DEQ), - .CLR(m_slave_xactor_f_wr_addr$CLR), - .D_OUT(m_slave_xactor_f_wr_addr$D_OUT), - .FULL_N(m_slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_data$D_IN), - .ENQ(m_slave_xactor_f_wr_data$ENQ), - .DEQ(m_slave_xactor_f_wr_data$DEQ), - .CLR(m_slave_xactor_f_wr_data$CLR), - .D_OUT(m_slave_xactor_f_wr_data$D_OUT), - .FULL_N(m_slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_resp$D_IN), - .ENQ(m_slave_xactor_f_wr_resp$ENQ), - .DEQ(m_slave_xactor_f_wr_resp$DEQ), - .CLR(m_slave_xactor_f_wr_resp$CLR), - .D_OUT(m_slave_xactor_f_wr_resp$D_OUT), - .FULL_N(m_slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = - m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - - // rule RL_m_rl_process_rd_req - assign CAN_FIRE_RL_m_rl_process_rd_req = - m_slave_xactor_f_rd_addr$EMPTY_N && - m_slave_xactor_f_rd_data$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - - // rule RL_m_rl_process_wr_req - assign CAN_FIRE_RL_m_rl_process_wr_req = - m_slave_xactor_f_wr_addr$EMPTY_N && - m_slave_xactor_f_wr_data$EMPTY_N && - m_slave_xactor_f_wr_resp$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_wr_req = - CAN_FIRE_RL_m_rl_process_wr_req && - !WILL_FIRE_RL_m_rl_process_rd_req ; - - // inputs to muxes for submodule ports - assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; - assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; - assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; - assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; - assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; - assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; - assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; - assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; - assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; - assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; - assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; - assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; - assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; - assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; - assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; - assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; - assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; - assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; - assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; - assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; - assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ; - assign MUX_m_vvrg_ie_0_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ; - assign MUX_m_vvrg_ie_0_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ; - assign MUX_m_vvrg_ie_0_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ; - assign MUX_m_vvrg_ie_0_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ; - assign MUX_m_vvrg_ie_0_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ; - assign MUX_m_vvrg_ie_0_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ; - assign MUX_m_vvrg_ie_0_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ; - assign MUX_m_vvrg_ie_0_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ; - assign MUX_m_vvrg_ie_0_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ; - assign MUX_m_vvrg_ie_0_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ; - assign MUX_m_vvrg_ie_0_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ; - assign MUX_m_vvrg_ie_0_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ; - assign MUX_m_vvrg_ie_0_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ; - assign MUX_m_vvrg_ie_0_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ; - assign MUX_m_vvrg_ie_0_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ; - assign MUX_m_vvrg_ie_1_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ; - assign MUX_m_vvrg_ie_1_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ; - assign MUX_m_vvrg_ie_1_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ; - assign MUX_m_vvrg_ie_1_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ; - assign MUX_m_vvrg_ie_1_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ; - assign MUX_m_vvrg_ie_1_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ; - assign MUX_m_vvrg_ie_1_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ; - assign MUX_m_vvrg_ie_1_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ; - assign MUX_m_vvrg_ie_1_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ; - assign MUX_m_vvrg_ie_1_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ; - assign MUX_m_vvrg_ie_1_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ; - assign MUX_m_vvrg_ie_1_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ; - assign MUX_m_vvrg_ie_1_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ; - assign MUX_m_vvrg_ie_1_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ; - assign MUX_m_vvrg_ie_1_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ; - assign MUX_m_vvrg_ie_1_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ; - assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; - assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2040 ; - assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2038 ; - assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2020 ; - assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2018 ; - assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2016 ; - assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2014 ; - assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2012 ; - assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2010 ; - assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2008 ; - assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2036 ; - assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2034 ; - assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2032 ; - assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2030 ; - assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2028 ; - assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2026 ; - assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2024 ; - assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2022 ; - assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2006 ; - assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2004 ; - assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1986 ; - assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1984 ; - assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1982 ; - assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1980 ; - assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1978 ; - assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1976 ; - assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1974 ; - assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2002 ; - assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2000 ; - assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1998 ; - assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1996 ; - assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1994 ; - assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1992 ; - assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1990 ; - assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1988 ; - - // register m_cfg_verbosity - assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign m_cfg_verbosity$EN = EN_set_verbosity ; - - // register m_rg_addr_base - assign m_rg_addr_base$D_IN = set_addr_map_addr_base ; - assign m_rg_addr_base$EN = EN_set_addr_map ; - - // register m_rg_addr_lim - assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign m_rg_addr_lim$EN = EN_set_addr_map ; - - // register m_vrg_servicing_source_0 - assign m_vrg_servicing_source_0$D_IN = - MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_servicing_source_1 - assign m_vrg_servicing_source_1$D_IN = - MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_0 - assign m_vrg_source_busy_0$D_IN = - !MUX_m_vrg_source_busy_0$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_1 - assign m_vrg_source_busy_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_10 - assign m_vrg_source_busy_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_11 - assign m_vrg_source_busy_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_12 - assign m_vrg_source_busy_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_13 - assign m_vrg_source_busy_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_14 - assign m_vrg_source_busy_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_15 - assign m_vrg_source_busy_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_16 - assign m_vrg_source_busy_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_2 - assign m_vrg_source_busy_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_3 - assign m_vrg_source_busy_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_4 - assign m_vrg_source_busy_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_5 - assign m_vrg_source_busy_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_6 - assign m_vrg_source_busy_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_7 - assign m_vrg_source_busy_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_8 - assign m_vrg_source_busy_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_9 - assign m_vrg_source_busy_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_0 - assign m_vrg_source_ip_0$D_IN = 1'd0 ; - assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_1 - assign m_vrg_source_ip_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_0_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_1$EN = - !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_10 - assign m_vrg_source_ip_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_9_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_10$EN = - !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_11 - assign m_vrg_source_ip_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_10_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_11$EN = - !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_12 - assign m_vrg_source_ip_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_11_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_12$EN = - !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_13 - assign m_vrg_source_ip_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_12_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_13$EN = - !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_14 - assign m_vrg_source_ip_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_13_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_14$EN = - !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_15 - assign m_vrg_source_ip_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_14_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_15$EN = - !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_16 - assign m_vrg_source_ip_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_15_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_16$EN = - !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_2 - assign m_vrg_source_ip_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_1_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_2$EN = - !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_3 - assign m_vrg_source_ip_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_2_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_3$EN = - !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_4 - assign m_vrg_source_ip_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_3_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_4$EN = - !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_5 - assign m_vrg_source_ip_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_4_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_5$EN = - !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_6 - assign m_vrg_source_ip_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_5_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_6$EN = - !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_7 - assign m_vrg_source_ip_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_6_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_7$EN = - !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_8 - assign m_vrg_source_ip_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_7_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_8$EN = - !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_9 - assign m_vrg_source_ip_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_8_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_9$EN = - !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_0 - assign m_vrg_source_prio_0$D_IN = - MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_1 - assign m_vrg_source_prio_1$D_IN = - MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_10 - assign m_vrg_source_prio_10$D_IN = - MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_11 - assign m_vrg_source_prio_11$D_IN = - MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_12 - assign m_vrg_source_prio_12$D_IN = - MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_13 - assign m_vrg_source_prio_13$D_IN = - MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_14 - assign m_vrg_source_prio_14$D_IN = - MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_15 - assign m_vrg_source_prio_15$D_IN = - MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_16 - assign m_vrg_source_prio_16$D_IN = - MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_2 - assign m_vrg_source_prio_2$D_IN = - MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_3 - assign m_vrg_source_prio_3$D_IN = - MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_4 - assign m_vrg_source_prio_4$D_IN = - MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_5 - assign m_vrg_source_prio_5$D_IN = - MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_6 - assign m_vrg_source_prio_6$D_IN = - MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_7 - assign m_vrg_source_prio_7$D_IN = - MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_8 - assign m_vrg_source_prio_8$D_IN = - MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_9 - assign m_vrg_source_prio_9$D_IN = - MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_0 - assign m_vrg_target_threshold_0$D_IN = - MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_1 - assign m_vrg_target_threshold_1$D_IN = - MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_0 - assign m_vvrg_ie_0_0$D_IN = - MUX_m_vvrg_ie_0_0$write_1__SEL_1 && - MUX_m_vvrg_ie_0_0$write_1__VAL_1 ; - assign m_vvrg_ie_0_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_1 - assign m_vvrg_ie_0_1$D_IN = - MUX_m_vvrg_ie_0_1$write_1__SEL_1 && - MUX_m_vvrg_ie_0_1$write_1__VAL_1 ; - assign m_vvrg_ie_0_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_10 - assign m_vvrg_ie_0_10$D_IN = - MUX_m_vvrg_ie_0_10$write_1__SEL_1 && - MUX_m_vvrg_ie_0_10$write_1__VAL_1 ; - assign m_vvrg_ie_0_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_11 - assign m_vvrg_ie_0_11$D_IN = - MUX_m_vvrg_ie_0_11$write_1__SEL_1 && - MUX_m_vvrg_ie_0_11$write_1__VAL_1 ; - assign m_vvrg_ie_0_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_12 - assign m_vvrg_ie_0_12$D_IN = - MUX_m_vvrg_ie_0_12$write_1__SEL_1 && - MUX_m_vvrg_ie_0_12$write_1__VAL_1 ; - assign m_vvrg_ie_0_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_13 - assign m_vvrg_ie_0_13$D_IN = - MUX_m_vvrg_ie_0_13$write_1__SEL_1 && - MUX_m_vvrg_ie_0_13$write_1__VAL_1 ; - assign m_vvrg_ie_0_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_14 - assign m_vvrg_ie_0_14$D_IN = - MUX_m_vvrg_ie_0_14$write_1__SEL_1 && - MUX_m_vvrg_ie_0_14$write_1__VAL_1 ; - assign m_vvrg_ie_0_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_15 - assign m_vvrg_ie_0_15$D_IN = - MUX_m_vvrg_ie_0_15$write_1__SEL_1 && - MUX_m_vvrg_ie_0_15$write_1__VAL_1 ; - assign m_vvrg_ie_0_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_16 - assign m_vvrg_ie_0_16$D_IN = - MUX_m_vvrg_ie_0_16$write_1__SEL_1 && - MUX_m_vvrg_ie_0_16$write_1__VAL_1 ; - assign m_vvrg_ie_0_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_2 - assign m_vvrg_ie_0_2$D_IN = - MUX_m_vvrg_ie_0_2$write_1__SEL_1 && - MUX_m_vvrg_ie_0_2$write_1__VAL_1 ; - assign m_vvrg_ie_0_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_3 - assign m_vvrg_ie_0_3$D_IN = - MUX_m_vvrg_ie_0_3$write_1__SEL_1 && - MUX_m_vvrg_ie_0_3$write_1__VAL_1 ; - assign m_vvrg_ie_0_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_4 - assign m_vvrg_ie_0_4$D_IN = - MUX_m_vvrg_ie_0_4$write_1__SEL_1 && - MUX_m_vvrg_ie_0_4$write_1__VAL_1 ; - assign m_vvrg_ie_0_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_5 - assign m_vvrg_ie_0_5$D_IN = - MUX_m_vvrg_ie_0_5$write_1__SEL_1 && - MUX_m_vvrg_ie_0_5$write_1__VAL_1 ; - assign m_vvrg_ie_0_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_6 - assign m_vvrg_ie_0_6$D_IN = - MUX_m_vvrg_ie_0_6$write_1__SEL_1 && - MUX_m_vvrg_ie_0_6$write_1__VAL_1 ; - assign m_vvrg_ie_0_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_7 - assign m_vvrg_ie_0_7$D_IN = - MUX_m_vvrg_ie_0_7$write_1__SEL_1 && - MUX_m_vvrg_ie_0_7$write_1__VAL_1 ; - assign m_vvrg_ie_0_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_8 - assign m_vvrg_ie_0_8$D_IN = - MUX_m_vvrg_ie_0_8$write_1__SEL_1 && - MUX_m_vvrg_ie_0_8$write_1__VAL_1 ; - assign m_vvrg_ie_0_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_9 - assign m_vvrg_ie_0_9$D_IN = - MUX_m_vvrg_ie_0_9$write_1__SEL_1 && - MUX_m_vvrg_ie_0_9$write_1__VAL_1 ; - assign m_vvrg_ie_0_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_0 - assign m_vvrg_ie_1_0$D_IN = - MUX_m_vvrg_ie_1_0$write_1__SEL_1 && - MUX_m_vvrg_ie_1_0$write_1__VAL_1 ; - assign m_vvrg_ie_1_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_1 - assign m_vvrg_ie_1_1$D_IN = - MUX_m_vvrg_ie_1_1$write_1__SEL_1 && - MUX_m_vvrg_ie_1_1$write_1__VAL_1 ; - assign m_vvrg_ie_1_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_10 - assign m_vvrg_ie_1_10$D_IN = - MUX_m_vvrg_ie_1_10$write_1__SEL_1 && - MUX_m_vvrg_ie_1_10$write_1__VAL_1 ; - assign m_vvrg_ie_1_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_11 - assign m_vvrg_ie_1_11$D_IN = - MUX_m_vvrg_ie_1_11$write_1__SEL_1 && - MUX_m_vvrg_ie_1_11$write_1__VAL_1 ; - assign m_vvrg_ie_1_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_12 - assign m_vvrg_ie_1_12$D_IN = - MUX_m_vvrg_ie_1_12$write_1__SEL_1 && - MUX_m_vvrg_ie_1_12$write_1__VAL_1 ; - assign m_vvrg_ie_1_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_13 - assign m_vvrg_ie_1_13$D_IN = - MUX_m_vvrg_ie_1_13$write_1__SEL_1 && - MUX_m_vvrg_ie_1_13$write_1__VAL_1 ; - assign m_vvrg_ie_1_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_14 - assign m_vvrg_ie_1_14$D_IN = - MUX_m_vvrg_ie_1_14$write_1__SEL_1 && - MUX_m_vvrg_ie_1_14$write_1__VAL_1 ; - assign m_vvrg_ie_1_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_15 - assign m_vvrg_ie_1_15$D_IN = - MUX_m_vvrg_ie_1_15$write_1__SEL_1 && - MUX_m_vvrg_ie_1_15$write_1__VAL_1 ; - assign m_vvrg_ie_1_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_16 - assign m_vvrg_ie_1_16$D_IN = - MUX_m_vvrg_ie_1_16$write_1__SEL_1 && - MUX_m_vvrg_ie_1_16$write_1__VAL_1 ; - assign m_vvrg_ie_1_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_2 - assign m_vvrg_ie_1_2$D_IN = - MUX_m_vvrg_ie_1_2$write_1__SEL_1 && - MUX_m_vvrg_ie_1_2$write_1__VAL_1 ; - assign m_vvrg_ie_1_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_3 - assign m_vvrg_ie_1_3$D_IN = - MUX_m_vvrg_ie_1_3$write_1__SEL_1 && - MUX_m_vvrg_ie_1_3$write_1__VAL_1 ; - assign m_vvrg_ie_1_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_4 - assign m_vvrg_ie_1_4$D_IN = - MUX_m_vvrg_ie_1_4$write_1__SEL_1 && - MUX_m_vvrg_ie_1_4$write_1__VAL_1 ; - assign m_vvrg_ie_1_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_5 - assign m_vvrg_ie_1_5$D_IN = - MUX_m_vvrg_ie_1_5$write_1__SEL_1 && - MUX_m_vvrg_ie_1_5$write_1__VAL_1 ; - assign m_vvrg_ie_1_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_6 - assign m_vvrg_ie_1_6$D_IN = - MUX_m_vvrg_ie_1_6$write_1__SEL_1 && - MUX_m_vvrg_ie_1_6$write_1__VAL_1 ; - assign m_vvrg_ie_1_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_7 - assign m_vvrg_ie_1_7$D_IN = - MUX_m_vvrg_ie_1_7$write_1__SEL_1 && - MUX_m_vvrg_ie_1_7$write_1__VAL_1 ; - assign m_vvrg_ie_1_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_8 - assign m_vvrg_ie_1_8$D_IN = - MUX_m_vvrg_ie_1_8$write_1__SEL_1 && - MUX_m_vvrg_ie_1_8$write_1__VAL_1 ; - assign m_vvrg_ie_1_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_9 - assign m_vvrg_ie_1_9$D_IN = - MUX_m_vvrg_ie_1_9$write_1__SEL_1 && - MUX_m_vvrg_ie_1_9$write_1__VAL_1 ; - assign m_vvrg_ie_1_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 || - WILL_FIRE_RL_m_rl_reset ; - - // submodule m_f_reset_reqs - assign m_f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign m_f_reset_reqs$DEQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_reqs$CLR = 1'b0 ; - - // submodule m_f_reset_rsps - assign m_f_reset_rsps$ENQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign m_f_reset_rsps$CLR = 1'b0 ; - - // submodule m_slave_xactor_f_rd_addr - assign m_slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign m_slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ; - assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_rd_data - assign m_slave_xactor_f_rd_data$D_IN = - { m_slave_xactor_f_rd_addr$D_OUT[96:93], - x__h26361, - rresp__h26203, - 1'd1 } ; - assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ; - assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_addr - assign m_slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign m_slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ; - assign m_slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_data - assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign m_slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; - assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_resp - assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26934 } ; - assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; - assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ; - - // remaining internal signals - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 : - ((x__h23673 == 32'h00200000) ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 : - x__h23673 != 32'h00200004 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 || - x__h24011 != 5'd0) ; - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - addr_offset__h13216[11:2] == 10'd0 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 : - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67110 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67110 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26929[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 = - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - 5'd2 : - (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ; - assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200000 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30685 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31895 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33105 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34315 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35525 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36735 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37945 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39155 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40365 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41575 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42785 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43995 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45205 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46415 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47625 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48835 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50045 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51255 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52465 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53675 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54885 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56095 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57305 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58515 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59725 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60935 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62145 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63355 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64565 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65775 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29475 <= 10'd16 ; - assign NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313 = - !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321 = - !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_11 != - v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329 = - !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_12 != - v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337 = - !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_13 != - v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345 = - !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_14 != - v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353 = - !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_15 != - v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361 = - !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_16 != - v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242 = - !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249 = - !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257 = - !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265 = - !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273 = - !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281 = - !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289 = - !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297 = - !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305 = - !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; - assign _dfoo1 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo10 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo100 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo32 ; - assign _dfoo1000 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo932 ; - assign _dfoo1001 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo865 ; - assign _dfoo1002 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo934 ; - assign _dfoo1003 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo867 ; - assign _dfoo1004 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo936 ; - assign _dfoo1005 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo869 ; - assign _dfoo1006 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo938 ; - assign _dfoo1007 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo871 ; - assign _dfoo1008 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo940 ; - assign _dfoo1009 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo873 ; - assign _dfoo1010 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo942 ; - assign _dfoo1011 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo875 ; - assign _dfoo1012 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo944 ; - assign _dfoo1013 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo877 ; - assign _dfoo1014 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo946 ; - assign _dfoo1015 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo879 ; - assign _dfoo1016 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo948 ; - assign _dfoo1017 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo881 ; - assign _dfoo1018 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo950 ; - assign _dfoo1019 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo883 ; - assign _dfoo102 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo34 ; - assign _dfoo1020 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo952 ; - assign _dfoo1022 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo954 ; - assign _dfoo1024 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo956 ; - assign _dfoo1026 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo958 ; - assign _dfoo1028 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo960 ; - assign _dfoo1030 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo962 ; - assign _dfoo1032 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo964 ; - assign _dfoo1034 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo966 ; - assign _dfoo1036 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo968 ; - assign _dfoo1038 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo970 ; - assign _dfoo104 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo36 ; - assign _dfoo1040 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo972 ; - assign _dfoo1042 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo974 ; - assign _dfoo1044 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo976 ; - assign _dfoo1046 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo978 ; - assign _dfoo1048 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo980 ; - assign _dfoo1050 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo982 ; - assign _dfoo1052 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo984 ; - assign _dfoo1054 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo986 ; - assign _dfoo1056 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo988 ; - assign _dfoo1058 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo990 ; - assign _dfoo106 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo38 ; - assign _dfoo1060 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo992 ; - assign _dfoo1062 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo994 ; - assign _dfoo1064 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo996 ; - assign _dfoo1066 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo998 ; - assign _dfoo1068 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1000 ; - assign _dfoo1070 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1002 ; - assign _dfoo1072 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1004 ; - assign _dfoo1074 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1006 ; - assign _dfoo1076 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1008 ; - assign _dfoo1078 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1010 ; - assign _dfoo108 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo40 ; - assign _dfoo1080 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1012 ; - assign _dfoo1082 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1014 ; - assign _dfoo1084 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1016 ; - assign _dfoo1086 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1018 ; - assign _dfoo1088 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1020 ; - assign _dfoo1089 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo953 ; - assign _dfoo1090 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1022 ; - assign _dfoo1091 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo955 ; - assign _dfoo1092 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1024 ; - assign _dfoo1093 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo957 ; - assign _dfoo1094 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1026 ; - assign _dfoo1095 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo959 ; - assign _dfoo1096 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1028 ; - assign _dfoo1097 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo961 ; - assign _dfoo1098 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1030 ; - assign _dfoo1099 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo963 ; - assign _dfoo11 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo110 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo42 ; - assign _dfoo1100 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1032 ; - assign _dfoo1101 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo965 ; - assign _dfoo1102 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1034 ; - assign _dfoo1103 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo967 ; - assign _dfoo1104 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1036 ; - assign _dfoo1105 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo969 ; - assign _dfoo1106 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1038 ; - assign _dfoo1107 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo971 ; - assign _dfoo1108 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1040 ; - assign _dfoo1109 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo973 ; - assign _dfoo1110 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1042 ; - assign _dfoo1111 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo975 ; - assign _dfoo1112 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1044 ; - assign _dfoo1113 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo977 ; - assign _dfoo1114 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1046 ; - assign _dfoo1115 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo979 ; - assign _dfoo1116 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1048 ; - assign _dfoo1117 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo981 ; - assign _dfoo1118 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1050 ; - assign _dfoo1119 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo983 ; - assign _dfoo112 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo44 ; - assign _dfoo1120 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1052 ; - assign _dfoo1121 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo985 ; - assign _dfoo1122 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1054 ; - assign _dfoo1123 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo987 ; - assign _dfoo1124 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1056 ; - assign _dfoo1125 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo989 ; - assign _dfoo1126 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1058 ; - assign _dfoo1127 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo991 ; - assign _dfoo1128 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1060 ; - assign _dfoo1129 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo993 ; - assign _dfoo1130 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1062 ; - assign _dfoo1131 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo995 ; - assign _dfoo1132 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1064 ; - assign _dfoo1133 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo997 ; - assign _dfoo1134 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1066 ; - assign _dfoo1135 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo999 ; - assign _dfoo1136 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1068 ; - assign _dfoo1137 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1001 ; - assign _dfoo1138 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1070 ; - assign _dfoo1139 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1003 ; - assign _dfoo114 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo46 ; - assign _dfoo1140 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1072 ; - assign _dfoo1141 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1005 ; - assign _dfoo1142 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1074 ; - assign _dfoo1143 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1007 ; - assign _dfoo1144 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1076 ; - assign _dfoo1145 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1009 ; - assign _dfoo1146 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1078 ; - assign _dfoo1147 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1011 ; - assign _dfoo1148 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1080 ; - assign _dfoo1149 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1013 ; - assign _dfoo1150 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1082 ; - assign _dfoo1151 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1015 ; - assign _dfoo1152 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1084 ; - assign _dfoo1153 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1017 ; - assign _dfoo1154 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1086 ; - assign _dfoo1155 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1019 ; - assign _dfoo1156 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1088 ; - assign _dfoo1158 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1090 ; - assign _dfoo116 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo48 ; - assign _dfoo1160 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1092 ; - assign _dfoo1162 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1094 ; - assign _dfoo1164 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1096 ; - assign _dfoo1166 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1098 ; - assign _dfoo1168 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1100 ; - assign _dfoo1170 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1102 ; - assign _dfoo1172 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1104 ; - assign _dfoo1174 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1106 ; - assign _dfoo1176 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1108 ; - assign _dfoo1178 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1110 ; - assign _dfoo118 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo50 ; - assign _dfoo1180 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1112 ; - assign _dfoo1182 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1114 ; - assign _dfoo1184 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1116 ; - assign _dfoo1186 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1118 ; - assign _dfoo1188 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1120 ; - assign _dfoo1190 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1122 ; - assign _dfoo1192 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1124 ; - assign _dfoo1194 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1126 ; - assign _dfoo1196 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1128 ; - assign _dfoo1198 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1130 ; - assign _dfoo12 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo120 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo52 ; - assign _dfoo1200 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1132 ; - assign _dfoo1202 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1134 ; - assign _dfoo1204 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1136 ; - assign _dfoo1206 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1138 ; - assign _dfoo1208 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1140 ; - assign _dfoo1210 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1142 ; - assign _dfoo1212 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1144 ; - assign _dfoo1214 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1146 ; - assign _dfoo1216 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1148 ; - assign _dfoo1218 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1150 ; - assign _dfoo122 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo54 ; - assign _dfoo1220 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1152 ; - assign _dfoo1222 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1154 ; - assign _dfoo1224 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1156 ; - assign _dfoo1225 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1089 ; - assign _dfoo1226 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1158 ; - assign _dfoo1227 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1091 ; - assign _dfoo1228 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1160 ; - assign _dfoo1229 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1093 ; - assign _dfoo1230 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1162 ; - assign _dfoo1231 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1095 ; - assign _dfoo1232 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1164 ; - assign _dfoo1233 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1097 ; - assign _dfoo1234 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1166 ; - assign _dfoo1235 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1099 ; - assign _dfoo1236 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1168 ; - assign _dfoo1237 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1101 ; - assign _dfoo1238 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1170 ; - assign _dfoo1239 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1103 ; - assign _dfoo124 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo56 ; - assign _dfoo1240 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1172 ; - assign _dfoo1241 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1105 ; - assign _dfoo1242 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1174 ; - assign _dfoo1243 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1107 ; - assign _dfoo1244 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1176 ; - assign _dfoo1245 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1109 ; - assign _dfoo1246 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1178 ; - assign _dfoo1247 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1111 ; - assign _dfoo1248 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1180 ; - assign _dfoo1249 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1113 ; - assign _dfoo1250 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1182 ; - assign _dfoo1251 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1115 ; - assign _dfoo1252 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1184 ; - assign _dfoo1253 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1117 ; - assign _dfoo1254 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1186 ; - assign _dfoo1255 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1119 ; - assign _dfoo1256 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1188 ; - assign _dfoo1257 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1121 ; - assign _dfoo1258 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1190 ; - assign _dfoo1259 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1123 ; - assign _dfoo126 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo58 ; - assign _dfoo1260 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1192 ; - assign _dfoo1261 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1125 ; - assign _dfoo1262 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1194 ; - assign _dfoo1263 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1127 ; - assign _dfoo1264 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1196 ; - assign _dfoo1265 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1129 ; - assign _dfoo1266 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1198 ; - assign _dfoo1267 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1131 ; - assign _dfoo1268 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1200 ; - assign _dfoo1269 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1133 ; - assign _dfoo1270 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1202 ; - assign _dfoo1271 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1135 ; - assign _dfoo1272 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1204 ; - assign _dfoo1273 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1137 ; - assign _dfoo1274 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1206 ; - assign _dfoo1275 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1139 ; - assign _dfoo1276 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1208 ; - assign _dfoo1277 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1141 ; - assign _dfoo1278 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1210 ; - assign _dfoo1279 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1143 ; - assign _dfoo128 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo60 ; - assign _dfoo1280 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1212 ; - assign _dfoo1281 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1145 ; - assign _dfoo1282 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1214 ; - assign _dfoo1283 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1147 ; - assign _dfoo1284 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1216 ; - assign _dfoo1285 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1149 ; - assign _dfoo1286 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1218 ; - assign _dfoo1287 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1151 ; - assign _dfoo1288 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1220 ; - assign _dfoo1289 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1153 ; - assign _dfoo1290 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1222 ; - assign _dfoo1291 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1155 ; - assign _dfoo1292 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1224 ; - assign _dfoo1294 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1226 ; - assign _dfoo1296 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1228 ; - assign _dfoo1298 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1230 ; - assign _dfoo13 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo130 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo62 ; - assign _dfoo1300 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1232 ; - assign _dfoo1302 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1234 ; - assign _dfoo1304 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1236 ; - assign _dfoo1306 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1238 ; - assign _dfoo1308 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1240 ; - assign _dfoo1310 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1242 ; - assign _dfoo1312 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1244 ; - assign _dfoo1314 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1246 ; - assign _dfoo1316 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1248 ; - assign _dfoo1318 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1250 ; - assign _dfoo132 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo64 ; - assign _dfoo1320 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1252 ; - assign _dfoo1322 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1254 ; - assign _dfoo1324 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1256 ; - assign _dfoo1326 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1258 ; - assign _dfoo1328 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1260 ; - assign _dfoo1330 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1262 ; - assign _dfoo1332 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1264 ; - assign _dfoo1334 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1266 ; - assign _dfoo1336 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1268 ; - assign _dfoo1338 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1270 ; - assign _dfoo134 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo66 ; - assign _dfoo1340 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1272 ; - assign _dfoo1342 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1274 ; - assign _dfoo1344 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1276 ; - assign _dfoo1346 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1278 ; - assign _dfoo1348 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1280 ; - assign _dfoo1350 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1282 ; - assign _dfoo1352 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1284 ; - assign _dfoo1354 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1286 ; - assign _dfoo1356 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1288 ; - assign _dfoo1358 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1290 ; - assign _dfoo136 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo68 ; - assign _dfoo1360 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1292 ; - assign _dfoo1361 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1225 ; - assign _dfoo1362 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1294 ; - assign _dfoo1363 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1227 ; - assign _dfoo1364 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1296 ; - assign _dfoo1365 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1229 ; - assign _dfoo1366 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1298 ; - assign _dfoo1367 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1231 ; - assign _dfoo1368 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1300 ; - assign _dfoo1369 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1233 ; - assign _dfoo137 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo1 ; - assign _dfoo1370 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1302 ; - assign _dfoo1371 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1235 ; - assign _dfoo1372 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1304 ; - assign _dfoo1373 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1237 ; - assign _dfoo1374 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1306 ; - assign _dfoo1375 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1239 ; - assign _dfoo1376 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1308 ; - assign _dfoo1377 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1241 ; - assign _dfoo1378 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1310 ; - assign _dfoo1379 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1243 ; - assign _dfoo138 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo70 ; - assign _dfoo1380 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1312 ; - assign _dfoo1381 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1245 ; - assign _dfoo1382 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1314 ; - assign _dfoo1383 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1247 ; - assign _dfoo1384 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1316 ; - assign _dfoo1385 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1249 ; - assign _dfoo1386 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1318 ; - assign _dfoo1387 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1251 ; - assign _dfoo1388 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1320 ; - assign _dfoo1389 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1253 ; - assign _dfoo139 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo3 ; - assign _dfoo1390 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1322 ; - assign _dfoo1391 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1255 ; - assign _dfoo1392 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1324 ; - assign _dfoo1393 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1257 ; - assign _dfoo1394 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1326 ; - assign _dfoo1395 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1259 ; - assign _dfoo1396 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1328 ; - assign _dfoo1397 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1261 ; - assign _dfoo1398 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1330 ; - assign _dfoo1399 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1263 ; - assign _dfoo14 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo140 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo72 ; - assign _dfoo1400 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1332 ; - assign _dfoo1401 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1265 ; - assign _dfoo1402 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1334 ; - assign _dfoo1403 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1267 ; - assign _dfoo1404 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1336 ; - assign _dfoo1405 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1269 ; - assign _dfoo1406 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1338 ; - assign _dfoo1407 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1271 ; - assign _dfoo1408 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1340 ; - assign _dfoo1409 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1273 ; - assign _dfoo141 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo5 ; - assign _dfoo1410 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1342 ; - assign _dfoo1411 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1275 ; - assign _dfoo1412 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1344 ; - assign _dfoo1413 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1277 ; - assign _dfoo1414 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1346 ; - assign _dfoo1415 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1279 ; - assign _dfoo1416 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1348 ; - assign _dfoo1417 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1281 ; - assign _dfoo1418 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1350 ; - assign _dfoo1419 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1283 ; - assign _dfoo142 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo74 ; - assign _dfoo1420 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1352 ; - assign _dfoo1421 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1285 ; - assign _dfoo1422 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1354 ; - assign _dfoo1423 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1287 ; - assign _dfoo1424 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1356 ; - assign _dfoo1425 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1289 ; - assign _dfoo1426 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1358 ; - assign _dfoo1427 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1291 ; - assign _dfoo1428 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1360 ; - assign _dfoo143 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo7 ; - assign _dfoo1430 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1362 ; - assign _dfoo1432 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1364 ; - assign _dfoo1434 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1366 ; - assign _dfoo1436 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1368 ; - assign _dfoo1438 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1370 ; - assign _dfoo144 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo76 ; - assign _dfoo1440 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1372 ; - assign _dfoo1442 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1374 ; - assign _dfoo1444 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1376 ; - assign _dfoo1446 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1378 ; - assign _dfoo1448 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1380 ; - assign _dfoo145 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo9 ; - assign _dfoo1450 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1382 ; - assign _dfoo1452 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1384 ; - assign _dfoo1454 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1386 ; - assign _dfoo1456 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1388 ; - assign _dfoo1458 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1390 ; - assign _dfoo146 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo78 ; - assign _dfoo1460 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1392 ; - assign _dfoo1462 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1394 ; - assign _dfoo1464 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1396 ; - assign _dfoo1466 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1398 ; - assign _dfoo1468 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1400 ; - assign _dfoo147 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo11 ; - assign _dfoo1470 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1402 ; - assign _dfoo1472 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1404 ; - assign _dfoo1474 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1406 ; - assign _dfoo1476 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1408 ; - assign _dfoo1478 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1410 ; - assign _dfoo148 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo80 ; - assign _dfoo1480 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1412 ; - assign _dfoo1482 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1414 ; - assign _dfoo1484 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1416 ; - assign _dfoo1486 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1418 ; - assign _dfoo1488 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1420 ; - assign _dfoo149 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo13 ; - assign _dfoo1490 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1422 ; - assign _dfoo1492 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1424 ; - assign _dfoo1494 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1426 ; - assign _dfoo1496 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1428 ; - assign _dfoo1497 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1361 ; - assign _dfoo1498 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1430 ; - assign _dfoo1499 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1363 ; - assign _dfoo15 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo150 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo82 ; - assign _dfoo1500 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1432 ; - assign _dfoo1501 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1365 ; - assign _dfoo1502 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1434 ; - assign _dfoo1503 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1367 ; - assign _dfoo1504 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1436 ; - assign _dfoo1505 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1369 ; - assign _dfoo1506 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1438 ; - assign _dfoo1507 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1371 ; - assign _dfoo1508 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1440 ; - assign _dfoo1509 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1373 ; - assign _dfoo151 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo15 ; - assign _dfoo1510 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1442 ; - assign _dfoo1511 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1375 ; - assign _dfoo1512 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1444 ; - assign _dfoo1513 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1377 ; - assign _dfoo1514 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1446 ; - assign _dfoo1515 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1379 ; - assign _dfoo1516 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1448 ; - assign _dfoo1517 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1381 ; - assign _dfoo1518 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1450 ; - assign _dfoo1519 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1383 ; - assign _dfoo152 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo84 ; - assign _dfoo1520 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1452 ; - assign _dfoo1521 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1385 ; - assign _dfoo1522 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1454 ; - assign _dfoo1523 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1387 ; - assign _dfoo1524 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1456 ; - assign _dfoo1525 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1389 ; - assign _dfoo1526 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1458 ; - assign _dfoo1527 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1391 ; - assign _dfoo1528 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1460 ; - assign _dfoo1529 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1393 ; - assign _dfoo153 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo17 ; - assign _dfoo1530 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1462 ; - assign _dfoo1531 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1395 ; - assign _dfoo1532 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1464 ; - assign _dfoo1533 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1397 ; - assign _dfoo1534 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1466 ; - assign _dfoo1535 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1399 ; - assign _dfoo1536 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1468 ; - assign _dfoo1537 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1401 ; - assign _dfoo1538 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1470 ; - assign _dfoo1539 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1403 ; - assign _dfoo154 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo86 ; - assign _dfoo1540 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1472 ; - assign _dfoo1541 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1405 ; - assign _dfoo1542 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1474 ; - assign _dfoo1543 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1407 ; - assign _dfoo1544 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1476 ; - assign _dfoo1545 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1409 ; - assign _dfoo1546 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1478 ; - assign _dfoo1547 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1411 ; - assign _dfoo1548 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1480 ; - assign _dfoo1549 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1413 ; - assign _dfoo155 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo19 ; - assign _dfoo1550 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1482 ; - assign _dfoo1551 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1415 ; - assign _dfoo1552 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1484 ; - assign _dfoo1553 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1417 ; - assign _dfoo1554 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1486 ; - assign _dfoo1555 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1419 ; - assign _dfoo1556 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1488 ; - assign _dfoo1557 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1421 ; - assign _dfoo1558 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1490 ; - assign _dfoo1559 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1423 ; - assign _dfoo156 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo88 ; - assign _dfoo1560 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1492 ; - assign _dfoo1561 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1425 ; - assign _dfoo1562 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1494 ; - assign _dfoo1563 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1427 ; - assign _dfoo1564 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1496 ; - assign _dfoo1566 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1498 ; - assign _dfoo1568 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1500 ; - assign _dfoo157 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo21 ; - assign _dfoo1570 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1502 ; - assign _dfoo1572 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1504 ; - assign _dfoo1574 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1506 ; - assign _dfoo1576 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1508 ; - assign _dfoo1578 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1510 ; - assign _dfoo158 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo90 ; - assign _dfoo1580 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1512 ; - assign _dfoo1582 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1514 ; - assign _dfoo1584 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1516 ; - assign _dfoo1586 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1518 ; - assign _dfoo1588 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1520 ; - assign _dfoo159 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo23 ; - assign _dfoo1590 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1522 ; - assign _dfoo1592 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1524 ; - assign _dfoo1594 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1526 ; - assign _dfoo1596 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1528 ; - assign _dfoo1598 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1530 ; - assign _dfoo16 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo160 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo92 ; - assign _dfoo1600 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1532 ; - assign _dfoo1602 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1534 ; - assign _dfoo1604 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1536 ; - assign _dfoo1606 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1538 ; - assign _dfoo1608 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1540 ; - assign _dfoo161 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo25 ; - assign _dfoo1610 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1542 ; - assign _dfoo1612 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1544 ; - assign _dfoo1614 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1546 ; - assign _dfoo1616 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1548 ; - assign _dfoo1618 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1550 ; - assign _dfoo162 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo94 ; - assign _dfoo1620 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1552 ; - assign _dfoo1622 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1554 ; - assign _dfoo1624 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1556 ; - assign _dfoo1626 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1558 ; - assign _dfoo1628 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1560 ; - assign _dfoo163 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo27 ; - assign _dfoo1630 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1562 ; - assign _dfoo1632 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1564 ; - assign _dfoo1633 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1497 ; - assign _dfoo1634 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1566 ; - assign _dfoo1635 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1499 ; - assign _dfoo1636 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1568 ; - assign _dfoo1637 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1501 ; - assign _dfoo1638 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1570 ; - assign _dfoo1639 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1503 ; - assign _dfoo164 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo96 ; - assign _dfoo1640 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1572 ; - assign _dfoo1641 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1505 ; - assign _dfoo1642 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1574 ; - assign _dfoo1643 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1507 ; - assign _dfoo1644 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1576 ; - assign _dfoo1645 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1509 ; - assign _dfoo1646 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1578 ; - assign _dfoo1647 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1511 ; - assign _dfoo1648 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1580 ; - assign _dfoo1649 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1513 ; - assign _dfoo165 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo29 ; - assign _dfoo1650 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1582 ; - assign _dfoo1651 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1515 ; - assign _dfoo1652 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1584 ; - assign _dfoo1653 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1517 ; - assign _dfoo1654 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1586 ; - assign _dfoo1655 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1519 ; - assign _dfoo1656 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1588 ; - assign _dfoo1657 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1521 ; - assign _dfoo1658 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1590 ; - assign _dfoo1659 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1523 ; - assign _dfoo166 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo98 ; - assign _dfoo1660 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1592 ; - assign _dfoo1661 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1525 ; - assign _dfoo1662 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1594 ; - assign _dfoo1663 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1527 ; - assign _dfoo1664 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1596 ; - assign _dfoo1665 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1529 ; - assign _dfoo1666 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1598 ; - assign _dfoo1667 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1531 ; - assign _dfoo1668 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1600 ; - assign _dfoo1669 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1533 ; - assign _dfoo167 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo31 ; - assign _dfoo1670 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1602 ; - assign _dfoo1671 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1535 ; - assign _dfoo1672 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1604 ; - assign _dfoo1673 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1537 ; - assign _dfoo1674 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1606 ; - assign _dfoo1675 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1539 ; - assign _dfoo1676 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1608 ; - assign _dfoo1677 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1541 ; - assign _dfoo1678 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1610 ; - assign _dfoo1679 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1543 ; - assign _dfoo168 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo100 ; - assign _dfoo1680 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1612 ; - assign _dfoo1681 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1545 ; - assign _dfoo1682 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1614 ; - assign _dfoo1683 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1547 ; - assign _dfoo1684 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1616 ; - assign _dfoo1685 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1549 ; - assign _dfoo1686 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1618 ; - assign _dfoo1687 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1551 ; - assign _dfoo1688 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1620 ; - assign _dfoo1689 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1553 ; - assign _dfoo169 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo33 ; - assign _dfoo1690 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1622 ; - assign _dfoo1691 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1555 ; - assign _dfoo1692 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1624 ; - assign _dfoo1693 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1557 ; - assign _dfoo1694 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1626 ; - assign _dfoo1695 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1559 ; - assign _dfoo1696 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1628 ; - assign _dfoo1697 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1561 ; - assign _dfoo1698 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1630 ; - assign _dfoo1699 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1563 ; - assign _dfoo17 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo170 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo102 ; - assign _dfoo1700 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1632 ; - assign _dfoo1702 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1634 ; - assign _dfoo1704 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1636 ; - assign _dfoo1706 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1638 ; - assign _dfoo1708 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1640 ; - assign _dfoo171 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo35 ; - assign _dfoo1710 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1642 ; - assign _dfoo1712 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1644 ; - assign _dfoo1714 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1646 ; - assign _dfoo1716 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1648 ; - assign _dfoo1718 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1650 ; - assign _dfoo172 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo104 ; - assign _dfoo1720 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1652 ; - assign _dfoo1722 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1654 ; - assign _dfoo1724 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1656 ; - assign _dfoo1726 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1658 ; - assign _dfoo1728 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1660 ; - assign _dfoo173 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo37 ; - assign _dfoo1730 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1662 ; - assign _dfoo1732 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1664 ; - assign _dfoo1734 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1666 ; - assign _dfoo1736 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1668 ; - assign _dfoo1738 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1670 ; - assign _dfoo174 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo106 ; - assign _dfoo1740 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1672 ; - assign _dfoo1742 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1674 ; - assign _dfoo1744 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1676 ; - assign _dfoo1746 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1678 ; - assign _dfoo1748 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1680 ; - assign _dfoo175 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo39 ; - assign _dfoo1750 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1682 ; - assign _dfoo1752 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1684 ; - assign _dfoo1754 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1686 ; - assign _dfoo1756 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1688 ; - assign _dfoo1758 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1690 ; - assign _dfoo176 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo108 ; - assign _dfoo1760 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1692 ; - assign _dfoo1762 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1694 ; - assign _dfoo1764 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1696 ; - assign _dfoo1766 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1698 ; - assign _dfoo1768 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1700 ; - assign _dfoo1769 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1633 ; - assign _dfoo177 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo41 ; - assign _dfoo1770 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1702 ; - assign _dfoo1771 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1635 ; - assign _dfoo1772 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1704 ; - assign _dfoo1773 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1637 ; - assign _dfoo1774 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1706 ; - assign _dfoo1775 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1639 ; - assign _dfoo1776 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1708 ; - assign _dfoo1777 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1641 ; - assign _dfoo1778 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1710 ; - assign _dfoo1779 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1643 ; - assign _dfoo178 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo110 ; - assign _dfoo1780 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1712 ; - assign _dfoo1781 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1645 ; - assign _dfoo1782 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1714 ; - assign _dfoo1783 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1647 ; - assign _dfoo1784 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1716 ; - assign _dfoo1785 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1649 ; - assign _dfoo1786 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1718 ; - assign _dfoo1787 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1651 ; - assign _dfoo1788 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1720 ; - assign _dfoo1789 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1653 ; - assign _dfoo179 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo43 ; - assign _dfoo1790 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1722 ; - assign _dfoo1791 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1655 ; - assign _dfoo1792 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1724 ; - assign _dfoo1793 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1657 ; - assign _dfoo1794 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1726 ; - assign _dfoo1795 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1659 ; - assign _dfoo1796 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1728 ; - assign _dfoo1797 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1661 ; - assign _dfoo1798 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1730 ; - assign _dfoo1799 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1663 ; - assign _dfoo18 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo180 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo112 ; - assign _dfoo1800 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1732 ; - assign _dfoo1801 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1665 ; - assign _dfoo1802 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1734 ; - assign _dfoo1803 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1667 ; - assign _dfoo1804 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1736 ; - assign _dfoo1805 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1669 ; - assign _dfoo1806 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1738 ; - assign _dfoo1807 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1671 ; - assign _dfoo1808 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1740 ; - assign _dfoo1809 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1673 ; - assign _dfoo181 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo45 ; - assign _dfoo1810 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1742 ; - assign _dfoo1811 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1675 ; - assign _dfoo1812 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1744 ; - assign _dfoo1813 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1677 ; - assign _dfoo1814 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1746 ; - assign _dfoo1815 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1679 ; - assign _dfoo1816 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1748 ; - assign _dfoo1817 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1681 ; - assign _dfoo1818 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1750 ; - assign _dfoo1819 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1683 ; - assign _dfoo182 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo114 ; - assign _dfoo1820 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1752 ; - assign _dfoo1821 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1685 ; - assign _dfoo1822 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1754 ; - assign _dfoo1823 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1687 ; - assign _dfoo1824 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1756 ; - assign _dfoo1825 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1689 ; - assign _dfoo1826 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1758 ; - assign _dfoo1827 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1691 ; - assign _dfoo1828 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1760 ; - assign _dfoo1829 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1693 ; - assign _dfoo183 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo47 ; - assign _dfoo1830 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1762 ; - assign _dfoo1831 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1695 ; - assign _dfoo1832 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1764 ; - assign _dfoo1833 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1697 ; - assign _dfoo1834 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1766 ; - assign _dfoo1835 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1699 ; - assign _dfoo1836 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1768 ; - assign _dfoo1838 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1770 ; - assign _dfoo184 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo116 ; - assign _dfoo1840 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1772 ; - assign _dfoo1842 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1774 ; - assign _dfoo1844 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1776 ; - assign _dfoo1846 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1778 ; - assign _dfoo1848 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1780 ; - assign _dfoo185 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo49 ; - assign _dfoo1850 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1782 ; - assign _dfoo1852 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1784 ; - assign _dfoo1854 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1786 ; - assign _dfoo1856 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1788 ; - assign _dfoo1858 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1790 ; - assign _dfoo186 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo118 ; - assign _dfoo1860 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1792 ; - assign _dfoo1862 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1794 ; - assign _dfoo1864 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1796 ; - assign _dfoo1866 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1798 ; - assign _dfoo1868 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1800 ; - assign _dfoo187 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo51 ; - assign _dfoo1870 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1802 ; - assign _dfoo1872 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1804 ; - assign _dfoo1874 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1806 ; - assign _dfoo1876 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1808 ; - assign _dfoo1878 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1810 ; - assign _dfoo188 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo120 ; - assign _dfoo1880 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1812 ; - assign _dfoo1882 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1814 ; - assign _dfoo1884 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1816 ; - assign _dfoo1886 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1818 ; - assign _dfoo1888 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1820 ; - assign _dfoo189 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo53 ; - assign _dfoo1890 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1822 ; - assign _dfoo1892 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1824 ; - assign _dfoo1894 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1826 ; - assign _dfoo1896 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1828 ; - assign _dfoo1898 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1830 ; - assign _dfoo19 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo190 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo122 ; - assign _dfoo1900 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1832 ; - assign _dfoo1902 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1834 ; - assign _dfoo1904 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1836 ; - assign _dfoo1905 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1769 ; - assign _dfoo1906 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1838 ; - assign _dfoo1907 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1771 ; - assign _dfoo1908 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1840 ; - assign _dfoo1909 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1773 ; - assign _dfoo191 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo55 ; - assign _dfoo1910 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1842 ; - assign _dfoo1911 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1775 ; - assign _dfoo1912 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1844 ; - assign _dfoo1913 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1777 ; - assign _dfoo1914 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1846 ; - assign _dfoo1915 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1779 ; - assign _dfoo1916 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1848 ; - assign _dfoo1917 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1781 ; - assign _dfoo1918 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1850 ; - assign _dfoo1919 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1783 ; - assign _dfoo192 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo124 ; - assign _dfoo1920 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1852 ; - assign _dfoo1921 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1785 ; - assign _dfoo1922 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1854 ; - assign _dfoo1923 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1787 ; - assign _dfoo1924 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1856 ; - assign _dfoo1925 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1789 ; - assign _dfoo1926 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1858 ; - assign _dfoo1927 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1791 ; - assign _dfoo1928 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1860 ; - assign _dfoo1929 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1793 ; - assign _dfoo193 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo57 ; - assign _dfoo1930 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1862 ; - assign _dfoo1931 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1795 ; - assign _dfoo1932 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1864 ; - assign _dfoo1933 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1797 ; - assign _dfoo1934 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1866 ; - assign _dfoo1935 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1799 ; - assign _dfoo1936 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1868 ; - assign _dfoo1937 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1801 ; - assign _dfoo1938 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1870 ; - assign _dfoo1939 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1803 ; - assign _dfoo194 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo126 ; - assign _dfoo1940 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1872 ; - assign _dfoo1941 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1805 ; - assign _dfoo1942 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1874 ; - assign _dfoo1943 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1807 ; - assign _dfoo1944 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1876 ; - assign _dfoo1945 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1809 ; - assign _dfoo1946 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1878 ; - assign _dfoo1947 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1811 ; - assign _dfoo1948 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1880 ; - assign _dfoo1949 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1813 ; - assign _dfoo195 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo59 ; - assign _dfoo1950 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1882 ; - assign _dfoo1951 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1815 ; - assign _dfoo1952 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1884 ; - assign _dfoo1953 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1817 ; - assign _dfoo1954 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1886 ; - assign _dfoo1955 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1819 ; - assign _dfoo1956 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1888 ; - assign _dfoo1957 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1821 ; - assign _dfoo1958 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1890 ; - assign _dfoo1959 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1823 ; - assign _dfoo196 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo128 ; - assign _dfoo1960 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1892 ; - assign _dfoo1961 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1825 ; - assign _dfoo1962 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1894 ; - assign _dfoo1963 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1827 ; - assign _dfoo1964 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1896 ; - assign _dfoo1965 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1829 ; - assign _dfoo1966 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1898 ; - assign _dfoo1967 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1831 ; - assign _dfoo1968 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1900 ; - assign _dfoo1969 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1833 ; - assign _dfoo197 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo61 ; - assign _dfoo1970 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1902 ; - assign _dfoo1971 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1835 ; - assign _dfoo1972 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1904 ; - assign _dfoo1974 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1906 ; - assign _dfoo1976 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1908 ; - assign _dfoo1978 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1910 ; - assign _dfoo198 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo130 ; - assign _dfoo1980 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1912 ; - assign _dfoo1982 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1914 ; - assign _dfoo1984 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1916 ; - assign _dfoo1986 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1918 ; - assign _dfoo1988 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1920 ; - assign _dfoo199 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo63 ; - assign _dfoo1990 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1922 ; - assign _dfoo1992 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1924 ; - assign _dfoo1994 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1926 ; - assign _dfoo1996 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1928 ; - assign _dfoo1998 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1930 ; - assign _dfoo2 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo20 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo200 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo132 ; - assign _dfoo2000 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1932 ; - assign _dfoo2002 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1934 ; - assign _dfoo2004 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1936 ; - assign _dfoo2006 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1938 ; - assign _dfoo2008 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1940 ; - assign _dfoo201 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo65 ; - assign _dfoo2010 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1942 ; - assign _dfoo2012 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1944 ; - assign _dfoo2014 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1946 ; - assign _dfoo2016 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1948 ; - assign _dfoo2018 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1950 ; - assign _dfoo202 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo134 ; - assign _dfoo2020 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1952 ; - assign _dfoo2022 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1954 ; - assign _dfoo2024 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1956 ; - assign _dfoo2026 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1958 ; - assign _dfoo2028 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1960 ; - assign _dfoo203 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo67 ; - assign _dfoo2030 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1962 ; - assign _dfoo2032 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1964 ; - assign _dfoo2034 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1966 ; - assign _dfoo2036 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1968 ; - assign _dfoo2038 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1970 ; - assign _dfoo204 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo136 ; - assign _dfoo2040 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1972 ; - assign _dfoo2041 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1905 ; - assign _dfoo2043 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1907 ; - assign _dfoo2045 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1909 ; - assign _dfoo2047 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1911 ; - assign _dfoo2049 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1913 ; - assign _dfoo2051 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1915 ; - assign _dfoo2053 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1917 ; - assign _dfoo2055 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1919 ; - assign _dfoo2057 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1921 ; - assign _dfoo2059 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1923 ; - assign _dfoo206 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo138 ; - assign _dfoo2061 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1925 ; - assign _dfoo2063 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1927 ; - assign _dfoo2065 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1929 ; - assign _dfoo2067 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1931 ; - assign _dfoo2069 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1933 ; - assign _dfoo2071 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1935 ; - assign _dfoo2073 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1937 ; - assign _dfoo2075 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1939 ; - assign _dfoo2077 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1941 ; - assign _dfoo2079 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1943 ; - assign _dfoo208 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo140 ; - assign _dfoo2081 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1945 ; - assign _dfoo2083 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1947 ; - assign _dfoo2085 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1949 ; - assign _dfoo2087 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1951 ; - assign _dfoo2089 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1953 ; - assign _dfoo2091 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1955 ; - assign _dfoo2093 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1957 ; - assign _dfoo2095 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1959 ; - assign _dfoo2097 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1961 ; - assign _dfoo2099 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1963 ; - assign _dfoo21 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo210 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo142 ; - assign _dfoo2101 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1965 ; - assign _dfoo2103 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1967 ; - assign _dfoo2105 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1969 ; - assign _dfoo2107 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1971 ; - assign _dfoo212 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo144 ; - assign _dfoo214 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo146 ; - assign _dfoo216 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo148 ; - assign _dfoo218 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo150 ; - assign _dfoo22 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo220 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo152 ; - assign _dfoo222 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo154 ; - assign _dfoo224 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo156 ; - assign _dfoo226 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo158 ; - assign _dfoo228 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo160 ; - assign _dfoo23 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo230 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo162 ; - assign _dfoo232 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo164 ; - assign _dfoo234 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo166 ; - assign _dfoo236 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo168 ; - assign _dfoo238 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo170 ; - assign _dfoo24 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo240 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo172 ; - assign _dfoo242 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo174 ; - assign _dfoo244 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo176 ; - assign _dfoo246 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo178 ; - assign _dfoo248 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo180 ; - assign _dfoo25 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo250 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo182 ; - assign _dfoo252 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo184 ; - assign _dfoo254 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo186 ; - assign _dfoo256 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo188 ; - assign _dfoo258 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo190 ; - assign _dfoo26 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo260 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo192 ; - assign _dfoo262 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo194 ; - assign _dfoo264 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo196 ; - assign _dfoo266 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo198 ; - assign _dfoo268 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo200 ; - assign _dfoo27 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo270 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo202 ; - assign _dfoo272 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo204 ; - assign _dfoo273 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo137 ; - assign _dfoo274 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo206 ; - assign _dfoo275 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo139 ; - assign _dfoo276 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo208 ; - assign _dfoo277 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo141 ; - assign _dfoo278 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo210 ; - assign _dfoo279 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo143 ; - assign _dfoo28 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo280 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo212 ; - assign _dfoo281 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo145 ; - assign _dfoo282 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo214 ; - assign _dfoo283 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo147 ; - assign _dfoo284 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo216 ; - assign _dfoo285 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo149 ; - assign _dfoo286 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo218 ; - assign _dfoo287 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo151 ; - assign _dfoo288 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo220 ; - assign _dfoo289 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo153 ; - assign _dfoo29 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo290 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo222 ; - assign _dfoo291 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo155 ; - assign _dfoo292 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo224 ; - assign _dfoo293 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo157 ; - assign _dfoo294 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo226 ; - assign _dfoo295 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo159 ; - assign _dfoo296 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo228 ; - assign _dfoo297 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo161 ; - assign _dfoo298 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo230 ; - assign _dfoo299 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo163 ; - assign _dfoo3 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo30 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo300 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo232 ; - assign _dfoo301 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo165 ; - assign _dfoo302 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo234 ; - assign _dfoo303 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo167 ; - assign _dfoo304 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo236 ; - assign _dfoo305 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo169 ; - assign _dfoo306 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo238 ; - assign _dfoo307 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo171 ; - assign _dfoo308 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo240 ; - assign _dfoo309 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo173 ; - assign _dfoo31 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo310 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo242 ; - assign _dfoo311 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo175 ; - assign _dfoo312 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo244 ; - assign _dfoo313 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo177 ; - assign _dfoo314 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo246 ; - assign _dfoo315 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo179 ; - assign _dfoo316 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo248 ; - assign _dfoo317 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo181 ; - assign _dfoo318 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo250 ; - assign _dfoo319 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo183 ; - assign _dfoo32 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo320 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo252 ; - assign _dfoo321 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo185 ; - assign _dfoo322 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo254 ; - assign _dfoo323 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo187 ; - assign _dfoo324 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo256 ; - assign _dfoo325 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo189 ; - assign _dfoo326 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo258 ; - assign _dfoo327 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo191 ; - assign _dfoo328 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo260 ; - assign _dfoo329 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo193 ; - assign _dfoo33 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo330 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo262 ; - assign _dfoo331 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo195 ; - assign _dfoo332 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo264 ; - assign _dfoo333 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo197 ; - assign _dfoo334 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo266 ; - assign _dfoo335 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo199 ; - assign _dfoo336 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo268 ; - assign _dfoo337 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo201 ; - assign _dfoo338 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo270 ; - assign _dfoo339 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo203 ; - assign _dfoo34 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo340 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo272 ; - assign _dfoo342 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo274 ; - assign _dfoo344 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo276 ; - assign _dfoo346 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo278 ; - assign _dfoo348 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo280 ; - assign _dfoo35 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo350 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo282 ; - assign _dfoo352 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo284 ; - assign _dfoo354 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo286 ; - assign _dfoo356 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo288 ; - assign _dfoo358 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo290 ; - assign _dfoo36 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo360 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo292 ; - assign _dfoo362 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo294 ; - assign _dfoo364 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo296 ; - assign _dfoo366 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo298 ; - assign _dfoo368 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo300 ; - assign _dfoo37 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo370 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo302 ; - assign _dfoo372 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo304 ; - assign _dfoo374 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo306 ; - assign _dfoo376 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo308 ; - assign _dfoo378 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo310 ; - assign _dfoo38 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo380 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo312 ; - assign _dfoo382 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo314 ; - assign _dfoo384 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo316 ; - assign _dfoo386 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo318 ; - assign _dfoo388 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo320 ; - assign _dfoo39 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo390 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo322 ; - assign _dfoo392 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo324 ; - assign _dfoo394 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo326 ; - assign _dfoo396 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo328 ; - assign _dfoo398 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo330 ; - assign _dfoo4 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo40 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo400 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo332 ; - assign _dfoo402 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo334 ; - assign _dfoo404 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo336 ; - assign _dfoo406 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo338 ; - assign _dfoo408 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo340 ; - assign _dfoo409 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo273 ; - assign _dfoo41 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo410 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo342 ; - assign _dfoo411 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo275 ; - assign _dfoo412 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo344 ; - assign _dfoo413 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo277 ; - assign _dfoo414 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo346 ; - assign _dfoo415 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo279 ; - assign _dfoo416 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo348 ; - assign _dfoo417 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo281 ; - assign _dfoo418 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo350 ; - assign _dfoo419 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo283 ; - assign _dfoo42 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo420 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo352 ; - assign _dfoo421 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo285 ; - assign _dfoo422 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo354 ; - assign _dfoo423 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo287 ; - assign _dfoo424 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo356 ; - assign _dfoo425 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo289 ; - assign _dfoo426 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo358 ; - assign _dfoo427 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo291 ; - assign _dfoo428 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo360 ; - assign _dfoo429 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo293 ; - assign _dfoo43 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo430 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo362 ; - assign _dfoo431 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo295 ; - assign _dfoo432 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo364 ; - assign _dfoo433 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo297 ; - assign _dfoo434 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo366 ; - assign _dfoo435 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo299 ; - assign _dfoo436 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo368 ; - assign _dfoo437 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo301 ; - assign _dfoo438 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo370 ; - assign _dfoo439 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo303 ; - assign _dfoo44 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo440 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo372 ; - assign _dfoo441 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo305 ; - assign _dfoo442 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo374 ; - assign _dfoo443 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo307 ; - assign _dfoo444 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo376 ; - assign _dfoo445 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo309 ; - assign _dfoo446 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo378 ; - assign _dfoo447 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo311 ; - assign _dfoo448 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo380 ; - assign _dfoo449 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo313 ; - assign _dfoo45 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo450 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo382 ; - assign _dfoo451 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo315 ; - assign _dfoo452 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo384 ; - assign _dfoo453 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo317 ; - assign _dfoo454 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo386 ; - assign _dfoo455 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo319 ; - assign _dfoo456 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo388 ; - assign _dfoo457 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo321 ; - assign _dfoo458 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo390 ; - assign _dfoo459 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo323 ; - assign _dfoo46 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo460 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo392 ; - assign _dfoo461 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo325 ; - assign _dfoo462 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo394 ; - assign _dfoo463 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo327 ; - assign _dfoo464 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo396 ; - assign _dfoo465 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo329 ; - assign _dfoo466 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo398 ; - assign _dfoo467 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo331 ; - assign _dfoo468 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo400 ; - assign _dfoo469 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo333 ; - assign _dfoo47 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo470 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo402 ; - assign _dfoo471 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo335 ; - assign _dfoo472 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo404 ; - assign _dfoo473 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo337 ; - assign _dfoo474 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo406 ; - assign _dfoo475 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo339 ; - assign _dfoo476 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo408 ; - assign _dfoo478 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo410 ; - assign _dfoo48 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo480 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo412 ; - assign _dfoo482 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo414 ; - assign _dfoo484 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo416 ; - assign _dfoo486 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo418 ; - assign _dfoo488 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo420 ; - assign _dfoo49 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo490 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo422 ; - assign _dfoo492 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo424 ; - assign _dfoo494 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo426 ; - assign _dfoo496 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo428 ; - assign _dfoo498 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo430 ; - assign _dfoo5 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo50 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo500 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo432 ; - assign _dfoo502 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo434 ; - assign _dfoo504 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo436 ; - assign _dfoo506 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo438 ; - assign _dfoo508 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo440 ; - assign _dfoo51 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo510 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo442 ; - assign _dfoo512 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo444 ; - assign _dfoo514 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo446 ; - assign _dfoo516 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo448 ; - assign _dfoo518 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo450 ; - assign _dfoo52 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo520 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo452 ; - assign _dfoo522 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo454 ; - assign _dfoo524 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo456 ; - assign _dfoo526 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo458 ; - assign _dfoo528 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo460 ; - assign _dfoo53 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo530 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo462 ; - assign _dfoo532 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo464 ; - assign _dfoo534 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo466 ; - assign _dfoo536 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo468 ; - assign _dfoo538 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo470 ; - assign _dfoo54 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo540 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo472 ; - assign _dfoo542 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo474 ; - assign _dfoo544 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo476 ; - assign _dfoo545 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo409 ; - assign _dfoo546 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo478 ; - assign _dfoo547 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo411 ; - assign _dfoo548 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo480 ; - assign _dfoo549 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo413 ; - assign _dfoo55 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo550 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo482 ; - assign _dfoo551 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo415 ; - assign _dfoo552 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo484 ; - assign _dfoo553 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo417 ; - assign _dfoo554 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo486 ; - assign _dfoo555 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo419 ; - assign _dfoo556 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo488 ; - assign _dfoo557 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo421 ; - assign _dfoo558 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo490 ; - assign _dfoo559 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo423 ; - assign _dfoo56 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo560 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo492 ; - assign _dfoo561 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo425 ; - assign _dfoo562 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo494 ; - assign _dfoo563 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo427 ; - assign _dfoo564 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo496 ; - assign _dfoo565 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo429 ; - assign _dfoo566 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo498 ; - assign _dfoo567 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo431 ; - assign _dfoo568 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo500 ; - assign _dfoo569 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo433 ; - assign _dfoo57 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo570 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo502 ; - assign _dfoo571 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo435 ; - assign _dfoo572 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo504 ; - assign _dfoo573 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo437 ; - assign _dfoo574 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo506 ; - assign _dfoo575 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo439 ; - assign _dfoo576 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo508 ; - assign _dfoo577 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo441 ; - assign _dfoo578 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo510 ; - assign _dfoo579 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo443 ; - assign _dfoo58 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo580 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo512 ; - assign _dfoo581 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo445 ; - assign _dfoo582 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo514 ; - assign _dfoo583 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo447 ; - assign _dfoo584 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo516 ; - assign _dfoo585 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo449 ; - assign _dfoo586 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo518 ; - assign _dfoo587 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo451 ; - assign _dfoo588 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo520 ; - assign _dfoo589 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo453 ; - assign _dfoo59 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo590 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo522 ; - assign _dfoo591 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo455 ; - assign _dfoo592 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo524 ; - assign _dfoo593 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo457 ; - assign _dfoo594 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo526 ; - assign _dfoo595 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo459 ; - assign _dfoo596 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo528 ; - assign _dfoo597 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo461 ; - assign _dfoo598 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo530 ; - assign _dfoo599 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo463 ; - assign _dfoo6 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo60 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo600 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo532 ; - assign _dfoo601 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo465 ; - assign _dfoo602 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo534 ; - assign _dfoo603 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo467 ; - assign _dfoo604 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo536 ; - assign _dfoo605 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo469 ; - assign _dfoo606 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo538 ; - assign _dfoo607 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo471 ; - assign _dfoo608 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo540 ; - assign _dfoo609 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo473 ; - assign _dfoo61 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo610 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo542 ; - assign _dfoo611 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo475 ; - assign _dfoo612 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo544 ; - assign _dfoo614 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo546 ; - assign _dfoo616 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo548 ; - assign _dfoo618 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo550 ; - assign _dfoo62 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo620 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo552 ; - assign _dfoo622 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo554 ; - assign _dfoo624 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo556 ; - assign _dfoo626 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo558 ; - assign _dfoo628 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo560 ; - assign _dfoo63 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo630 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo562 ; - assign _dfoo632 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo564 ; - assign _dfoo634 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo566 ; - assign _dfoo636 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo568 ; - assign _dfoo638 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo570 ; - assign _dfoo64 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo640 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo572 ; - assign _dfoo642 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo574 ; - assign _dfoo644 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo576 ; - assign _dfoo646 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo578 ; - assign _dfoo648 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo580 ; - assign _dfoo65 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo650 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo582 ; - assign _dfoo652 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo584 ; - assign _dfoo654 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo586 ; - assign _dfoo656 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo588 ; - assign _dfoo658 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo590 ; - assign _dfoo66 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo660 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo592 ; - assign _dfoo662 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo594 ; - assign _dfoo664 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo596 ; - assign _dfoo666 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo598 ; - assign _dfoo668 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo600 ; - assign _dfoo67 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo670 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo602 ; - assign _dfoo672 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo604 ; - assign _dfoo674 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo606 ; - assign _dfoo676 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo608 ; - assign _dfoo678 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo610 ; - assign _dfoo68 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo680 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo612 ; - assign _dfoo681 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo545 ; - assign _dfoo682 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo614 ; - assign _dfoo683 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo547 ; - assign _dfoo684 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo616 ; - assign _dfoo685 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo549 ; - assign _dfoo686 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo618 ; - assign _dfoo687 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo551 ; - assign _dfoo688 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo620 ; - assign _dfoo689 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo553 ; - assign _dfoo690 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo622 ; - assign _dfoo691 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo555 ; - assign _dfoo692 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo624 ; - assign _dfoo693 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo557 ; - assign _dfoo694 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo626 ; - assign _dfoo695 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo559 ; - assign _dfoo696 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo628 ; - assign _dfoo697 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo561 ; - assign _dfoo698 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo630 ; - assign _dfoo699 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo563 ; - assign _dfoo7 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo70 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo2 ; - assign _dfoo700 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo632 ; - assign _dfoo701 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo565 ; - assign _dfoo702 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo634 ; - assign _dfoo703 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo567 ; - assign _dfoo704 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo636 ; - assign _dfoo705 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo569 ; - assign _dfoo706 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo638 ; - assign _dfoo707 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo571 ; - assign _dfoo708 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo640 ; - assign _dfoo709 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo573 ; - assign _dfoo710 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo642 ; - assign _dfoo711 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo575 ; - assign _dfoo712 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo644 ; - assign _dfoo713 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo577 ; - assign _dfoo714 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo646 ; - assign _dfoo715 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo579 ; - assign _dfoo716 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo648 ; - assign _dfoo717 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo581 ; - assign _dfoo718 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo650 ; - assign _dfoo719 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo583 ; - assign _dfoo72 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo4 ; - assign _dfoo720 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo652 ; - assign _dfoo721 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo585 ; - assign _dfoo722 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo654 ; - assign _dfoo723 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo587 ; - assign _dfoo724 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo656 ; - assign _dfoo725 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo589 ; - assign _dfoo726 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo658 ; - assign _dfoo727 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo591 ; - assign _dfoo728 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo660 ; - assign _dfoo729 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo593 ; - assign _dfoo730 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo662 ; - assign _dfoo731 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo595 ; - assign _dfoo732 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo664 ; - assign _dfoo733 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo597 ; - assign _dfoo734 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo666 ; - assign _dfoo735 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo599 ; - assign _dfoo736 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo668 ; - assign _dfoo737 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo601 ; - assign _dfoo738 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo670 ; - assign _dfoo739 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo603 ; - assign _dfoo74 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo6 ; - assign _dfoo740 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo672 ; - assign _dfoo741 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo605 ; - assign _dfoo742 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo674 ; - assign _dfoo743 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo607 ; - assign _dfoo744 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo676 ; - assign _dfoo745 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo609 ; - assign _dfoo746 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo678 ; - assign _dfoo747 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo611 ; - assign _dfoo748 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo680 ; - assign _dfoo750 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo682 ; - assign _dfoo752 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo684 ; - assign _dfoo754 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo686 ; - assign _dfoo756 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo688 ; - assign _dfoo758 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo690 ; - assign _dfoo76 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo8 ; - assign _dfoo760 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo692 ; - assign _dfoo762 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo694 ; - assign _dfoo764 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo696 ; - assign _dfoo766 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo698 ; - assign _dfoo768 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo700 ; - assign _dfoo770 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo702 ; - assign _dfoo772 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo704 ; - assign _dfoo774 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo706 ; - assign _dfoo776 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo708 ; - assign _dfoo778 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo710 ; - assign _dfoo78 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo10 ; - assign _dfoo780 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo712 ; - assign _dfoo782 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo714 ; - assign _dfoo784 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo716 ; - assign _dfoo786 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo718 ; - assign _dfoo788 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo720 ; - assign _dfoo790 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo722 ; - assign _dfoo792 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo724 ; - assign _dfoo794 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo726 ; - assign _dfoo796 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo728 ; - assign _dfoo798 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo730 ; - assign _dfoo8 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo80 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo12 ; - assign _dfoo800 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo732 ; - assign _dfoo802 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo734 ; - assign _dfoo804 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo736 ; - assign _dfoo806 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo738 ; - assign _dfoo808 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo740 ; - assign _dfoo810 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo742 ; - assign _dfoo812 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo744 ; - assign _dfoo814 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo746 ; - assign _dfoo816 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo748 ; - assign _dfoo817 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo681 ; - assign _dfoo818 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo750 ; - assign _dfoo819 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo683 ; - assign _dfoo82 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo14 ; - assign _dfoo820 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo752 ; - assign _dfoo821 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo685 ; - assign _dfoo822 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo754 ; - assign _dfoo823 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo687 ; - assign _dfoo824 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo756 ; - assign _dfoo825 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo689 ; - assign _dfoo826 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo758 ; - assign _dfoo827 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo691 ; - assign _dfoo828 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo760 ; - assign _dfoo829 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo693 ; - assign _dfoo830 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo762 ; - assign _dfoo831 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo695 ; - assign _dfoo832 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo764 ; - assign _dfoo833 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo697 ; - assign _dfoo834 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo766 ; - assign _dfoo835 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo699 ; - assign _dfoo836 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo768 ; - assign _dfoo837 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo701 ; - assign _dfoo838 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo770 ; - assign _dfoo839 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo703 ; - assign _dfoo84 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo16 ; - assign _dfoo840 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo772 ; - assign _dfoo841 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo705 ; - assign _dfoo842 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo774 ; - assign _dfoo843 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo707 ; - assign _dfoo844 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo776 ; - assign _dfoo845 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo709 ; - assign _dfoo846 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo778 ; - assign _dfoo847 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo711 ; - assign _dfoo848 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo780 ; - assign _dfoo849 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo713 ; - assign _dfoo850 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo782 ; - assign _dfoo851 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo715 ; - assign _dfoo852 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo784 ; - assign _dfoo853 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo717 ; - assign _dfoo854 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo786 ; - assign _dfoo855 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo719 ; - assign _dfoo856 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo788 ; - assign _dfoo857 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo721 ; - assign _dfoo858 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo790 ; - assign _dfoo859 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo723 ; - assign _dfoo86 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo18 ; - assign _dfoo860 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo792 ; - assign _dfoo861 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo725 ; - assign _dfoo862 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo794 ; - assign _dfoo863 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo727 ; - assign _dfoo864 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo796 ; - assign _dfoo865 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo729 ; - assign _dfoo866 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo798 ; - assign _dfoo867 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo731 ; - assign _dfoo868 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo800 ; - assign _dfoo869 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo733 ; - assign _dfoo870 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo802 ; - assign _dfoo871 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo735 ; - assign _dfoo872 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo804 ; - assign _dfoo873 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo737 ; - assign _dfoo874 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo806 ; - assign _dfoo875 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo739 ; - assign _dfoo876 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo808 ; - assign _dfoo877 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo741 ; - assign _dfoo878 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo810 ; - assign _dfoo879 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo743 ; - assign _dfoo88 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo20 ; - assign _dfoo880 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo812 ; - assign _dfoo881 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo745 ; - assign _dfoo882 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo814 ; - assign _dfoo883 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo747 ; - assign _dfoo884 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo816 ; - assign _dfoo886 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo818 ; - assign _dfoo888 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo820 ; - assign _dfoo890 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo822 ; - assign _dfoo892 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo824 ; - assign _dfoo894 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo826 ; - assign _dfoo896 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo828 ; - assign _dfoo898 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo830 ; - assign _dfoo9 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo90 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo22 ; - assign _dfoo900 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo832 ; - assign _dfoo902 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo834 ; - assign _dfoo904 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo836 ; - assign _dfoo906 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo838 ; - assign _dfoo908 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo840 ; - assign _dfoo910 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo842 ; - assign _dfoo912 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo844 ; - assign _dfoo914 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo846 ; - assign _dfoo916 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo848 ; - assign _dfoo918 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo850 ; - assign _dfoo92 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo24 ; - assign _dfoo920 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo852 ; - assign _dfoo922 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo854 ; - assign _dfoo924 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo856 ; - assign _dfoo926 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo858 ; - assign _dfoo928 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo860 ; - assign _dfoo930 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo862 ; - assign _dfoo932 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo864 ; - assign _dfoo934 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo866 ; - assign _dfoo936 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo868 ; - assign _dfoo938 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo870 ; - assign _dfoo94 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo26 ; - assign _dfoo940 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo872 ; - assign _dfoo942 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo874 ; - assign _dfoo944 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo876 ; - assign _dfoo946 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo878 ; - assign _dfoo948 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo880 ; - assign _dfoo950 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo882 ; - assign _dfoo952 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo884 ; - assign _dfoo953 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo817 ; - assign _dfoo954 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo886 ; - assign _dfoo955 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo819 ; - assign _dfoo956 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo888 ; - assign _dfoo957 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo821 ; - assign _dfoo958 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo890 ; - assign _dfoo959 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo823 ; - assign _dfoo96 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo28 ; - assign _dfoo960 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo892 ; - assign _dfoo961 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo825 ; - assign _dfoo962 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo894 ; - assign _dfoo963 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo827 ; - assign _dfoo964 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo896 ; - assign _dfoo965 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo829 ; - assign _dfoo966 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo898 ; - assign _dfoo967 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo831 ; - assign _dfoo968 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo900 ; - assign _dfoo969 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo833 ; - assign _dfoo970 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo902 ; - assign _dfoo971 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo835 ; - assign _dfoo972 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo904 ; - assign _dfoo973 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo837 ; - assign _dfoo974 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo906 ; - assign _dfoo975 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo839 ; - assign _dfoo976 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo908 ; - assign _dfoo977 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo841 ; - assign _dfoo978 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo910 ; - assign _dfoo979 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo843 ; - assign _dfoo98 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo30 ; - assign _dfoo980 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo912 ; - assign _dfoo981 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo845 ; - assign _dfoo982 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo914 ; - assign _dfoo983 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo847 ; - assign _dfoo984 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo916 ; - assign _dfoo985 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo849 ; - assign _dfoo986 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo918 ; - assign _dfoo987 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo851 ; - assign _dfoo988 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo920 ; - assign _dfoo989 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo853 ; - assign _dfoo990 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo922 ; - assign _dfoo991 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo855 ; - assign _dfoo992 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo924 ; - assign _dfoo993 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo857 ; - assign _dfoo994 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo926 ; - assign _dfoo995 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo859 ; - assign _dfoo996 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo928 ; - assign _dfoo997 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo861 ; - assign _dfoo998 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo930 ; - assign _dfoo999 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo863 ; - assign a__h71312 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73317 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; - assign addr_offset__h13216 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26929 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71313 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73318 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = - addr_offset__h13216 < 64'h0000000000003000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = - addr_offset__h13216[11:7] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 = - addr_offset__h13216 < 64'h0000000000001000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 = - addr_offset__h13216[11:2] <= 10'd16 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 = - addr_offset__h13216[16:12] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 = - addr_offset__h13216 < 64'h0000000000002000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = - source_id_base__h13630 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26929[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26929[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26929[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26929 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26929[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26929[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26929[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26929[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26929[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26929[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26929[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26929[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26929[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26929[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26929[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26929[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26929[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26929[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26929[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26929[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26929[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26929 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28148 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26929 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26929[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26929[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26929[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && - m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && - m_vvrg_ie_1_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && - m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && - m_vvrg_ie_1_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && - m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && - m_vvrg_ie_1_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && - m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && - m_vvrg_ie_1_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 || - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 || - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 || - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 || - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && - m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && - m_vvrg_ie_1_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && - m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && - m_vvrg_ie_1_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && - m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && - m_vvrg_ie_1_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = - m_vrg_source_ip_16 && - !m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 || - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 || - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 || - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 ; - assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = - m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && - m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && - m_vvrg_ie_1_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && - m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && - m_vvrg_ie_1_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && - m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && - m_vvrg_ie_1_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && - m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && - m_vvrg_ie_1_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && - m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && - m_vvrg_ie_1_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && - m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && - m_vvrg_ie_1_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 || - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 || - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 || - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 || - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && - m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && - m_vvrg_ie_1_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && - m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && - m_vvrg_ie_1_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; - assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 = - m_vrg_source_prio_16 <= - (m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ; - assign max_id__h23959 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ; - assign rdata___1__h26404 = { rdata__h26202[31:0], 32'h0 } ; - assign rdata__h26202 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 64'd0 : - y_avValue_fst__h26194 ; - assign rresp__h26203 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 2'b11 : - y_avValue_snd__h26195 ; - assign source_id__h15665 = { addr_offset__h13216[4:0], 5'd31 } ; - assign source_id__h15772 = { addr_offset__h13216[4:0], 5'd30 } ; - assign source_id__h15845 = { addr_offset__h13216[4:0], 5'd29 } ; - assign source_id__h15918 = { addr_offset__h13216[4:0], 5'd28 } ; - assign source_id__h15991 = { addr_offset__h13216[4:0], 5'd27 } ; - assign source_id__h16064 = { addr_offset__h13216[4:0], 5'd26 } ; - assign source_id__h16137 = { addr_offset__h13216[4:0], 5'd25 } ; - assign source_id__h16210 = { addr_offset__h13216[4:0], 5'd24 } ; - assign source_id__h16283 = { addr_offset__h13216[4:0], 5'd23 } ; - assign source_id__h16356 = { addr_offset__h13216[4:0], 5'd22 } ; - assign source_id__h16429 = { addr_offset__h13216[4:0], 5'd21 } ; - assign source_id__h16502 = { addr_offset__h13216[4:0], 5'd20 } ; - assign source_id__h16575 = { addr_offset__h13216[4:0], 5'd19 } ; - assign source_id__h16648 = { addr_offset__h13216[4:0], 5'd18 } ; - assign source_id__h16721 = { addr_offset__h13216[4:0], 5'd17 } ; - assign source_id__h16794 = { addr_offset__h13216[4:0], 5'd16 } ; - assign source_id__h16867 = { addr_offset__h13216[4:0], 5'd15 } ; - assign source_id__h16940 = { addr_offset__h13216[4:0], 5'd14 } ; - assign source_id__h17013 = { addr_offset__h13216[4:0], 5'd13 } ; - assign source_id__h17086 = { addr_offset__h13216[4:0], 5'd12 } ; - assign source_id__h17159 = { addr_offset__h13216[4:0], 5'd11 } ; - assign source_id__h17232 = { addr_offset__h13216[4:0], 5'd10 } ; - assign source_id__h17305 = { addr_offset__h13216[4:0], 5'd9 } ; - assign source_id__h17378 = { addr_offset__h13216[4:0], 5'd8 } ; - assign source_id__h17451 = { addr_offset__h13216[4:0], 5'd7 } ; - assign source_id__h17524 = { addr_offset__h13216[4:0], 5'd6 } ; - assign source_id__h17597 = { addr_offset__h13216[4:0], 5'd5 } ; - assign source_id__h17670 = { addr_offset__h13216[4:0], 5'd4 } ; - assign source_id__h17743 = { addr_offset__h13216[4:0], 5'd3 } ; - assign source_id__h17816 = { addr_offset__h13216[4:0], 5'd2 } ; - assign source_id__h17889 = { addr_offset__h13216[4:0], 5'd1 } ; - assign source_id__h20137 = 10'd31 + source_id_base__h13630 ; - assign source_id__h20313 = 10'd30 + source_id_base__h13630 ; - assign source_id__h20421 = 10'd29 + source_id_base__h13630 ; - assign source_id__h20529 = 10'd28 + source_id_base__h13630 ; - assign source_id__h20637 = 10'd27 + source_id_base__h13630 ; - assign source_id__h20745 = 10'd26 + source_id_base__h13630 ; - assign source_id__h20853 = 10'd25 + source_id_base__h13630 ; - assign source_id__h20961 = 10'd24 + source_id_base__h13630 ; - assign source_id__h21069 = 10'd23 + source_id_base__h13630 ; - assign source_id__h21177 = 10'd22 + source_id_base__h13630 ; - assign source_id__h21285 = 10'd21 + source_id_base__h13630 ; - assign source_id__h21393 = 10'd20 + source_id_base__h13630 ; - assign source_id__h21501 = 10'd19 + source_id_base__h13630 ; - assign source_id__h21609 = 10'd18 + source_id_base__h13630 ; - assign source_id__h21717 = 10'd17 + source_id_base__h13630 ; - assign source_id__h21825 = 10'd16 + source_id_base__h13630 ; - assign source_id__h21933 = 10'd15 + source_id_base__h13630 ; - assign source_id__h22041 = 10'd14 + source_id_base__h13630 ; - assign source_id__h22149 = 10'd13 + source_id_base__h13630 ; - assign source_id__h22257 = 10'd12 + source_id_base__h13630 ; - assign source_id__h22365 = 10'd11 + source_id_base__h13630 ; - assign source_id__h22473 = 10'd10 + source_id_base__h13630 ; - assign source_id__h22581 = 10'd9 + source_id_base__h13630 ; - assign source_id__h22689 = 10'd8 + source_id_base__h13630 ; - assign source_id__h22797 = 10'd7 + source_id_base__h13630 ; - assign source_id__h22905 = 10'd6 + source_id_base__h13630 ; - assign source_id__h23013 = 10'd5 + source_id_base__h13630 ; - assign source_id__h23121 = 10'd4 + source_id_base__h13630 ; - assign source_id__h23229 = 10'd3 + source_id_base__h13630 ; - assign source_id__h23337 = 10'd2 + source_id_base__h13630 ; - assign source_id__h23445 = 10'd1 + source_id_base__h13630 ; - assign source_id__h29475 = { addr_offset__h26929[4:0], 5'd1 } ; - assign source_id__h30685 = { addr_offset__h26929[4:0], 5'd2 } ; - assign source_id__h31895 = { addr_offset__h26929[4:0], 5'd3 } ; - assign source_id__h33105 = { addr_offset__h26929[4:0], 5'd4 } ; - assign source_id__h34315 = { addr_offset__h26929[4:0], 5'd5 } ; - assign source_id__h35525 = { addr_offset__h26929[4:0], 5'd6 } ; - assign source_id__h36735 = { addr_offset__h26929[4:0], 5'd7 } ; - assign source_id__h37945 = { addr_offset__h26929[4:0], 5'd8 } ; - assign source_id__h39155 = { addr_offset__h26929[4:0], 5'd9 } ; - assign source_id__h40365 = { addr_offset__h26929[4:0], 5'd10 } ; - assign source_id__h41575 = { addr_offset__h26929[4:0], 5'd11 } ; - assign source_id__h42785 = { addr_offset__h26929[4:0], 5'd12 } ; - assign source_id__h43995 = { addr_offset__h26929[4:0], 5'd13 } ; - assign source_id__h45205 = { addr_offset__h26929[4:0], 5'd14 } ; - assign source_id__h46415 = { addr_offset__h26929[4:0], 5'd15 } ; - assign source_id__h47625 = { addr_offset__h26929[4:0], 5'd16 } ; - assign source_id__h48835 = { addr_offset__h26929[4:0], 5'd17 } ; - assign source_id__h50045 = { addr_offset__h26929[4:0], 5'd18 } ; - assign source_id__h51255 = { addr_offset__h26929[4:0], 5'd19 } ; - assign source_id__h52465 = { addr_offset__h26929[4:0], 5'd20 } ; - assign source_id__h53675 = { addr_offset__h26929[4:0], 5'd21 } ; - assign source_id__h54885 = { addr_offset__h26929[4:0], 5'd22 } ; - assign source_id__h56095 = { addr_offset__h26929[4:0], 5'd23 } ; - assign source_id__h57305 = { addr_offset__h26929[4:0], 5'd24 } ; - assign source_id__h58515 = { addr_offset__h26929[4:0], 5'd25 } ; - assign source_id__h59725 = { addr_offset__h26929[4:0], 5'd26 } ; - assign source_id__h60935 = { addr_offset__h26929[4:0], 5'd27 } ; - assign source_id__h62145 = { addr_offset__h26929[4:0], 5'd28 } ; - assign source_id__h63355 = { addr_offset__h26929[4:0], 5'd29 } ; - assign source_id__h64565 = { addr_offset__h26929[4:0], 5'd30 } ; - assign source_id__h65775 = { addr_offset__h26929[4:0], 5'd31 } ; - assign source_id__h67436 = { 5'd0, x__h67487 } ; - assign source_id_base__h13630 = { addr_offset__h13216[4:0], 5'h0 } ; - assign source_id_base__h28148 = { addr_offset__h26929[4:0], 5'h0 } ; - assign v__h13422 = { 61'd0, x__h13493 } ; - assign v__h13671 = { 32'd0, v_ip__h13674 } ; - assign v__h18144 = { 32'd0, v_ie__h18147 } ; - assign v__h23761 = { 61'd0, x__h23832 } ; - assign v__h25455 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ? - v__h25474 : - 64'd0 ; - assign v__h25474 = { 59'd0, max_id__h23959 } ; - assign v__h26934 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? - 2'b11 : - v__h27094 ; - assign v__h27094 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27107 : - v__h27942 ; - assign v__h27107 = - (addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? - 2'b0 : - 2'b10 ; - assign v__h27942 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27961 : - v__h28125 ; - assign v__h27961 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? - 2'b0 : - 2'b10 ; - assign v__h28125 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28144 : - v__h67107 ; - assign v__h28144 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? - 2'b0 : - 2'b10 ; - assign v__h67144 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - 2'b0 : - 2'b10 ; - assign v__h67432 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67476 : - 2'b10 ; - assign v__h67476 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? - 2'b0 : - 2'b10 ; - assign v_ie__h18147 = - { source_id__h20137 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h20313 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h20421 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h20529 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h20637 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h20745 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h20853 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h20961 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h21069 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h21177 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h21285 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h21393 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h21501 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h21609 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h21717 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h21825 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h21933 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h22041 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h22149 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h22257 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h22365 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h22473 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h22581 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h22689 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h22797 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h22905 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h23013 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h23121 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h23229 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h23337 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h23445 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h13674 = - { source_id__h15665 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - source_id__h15772 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - source_id__h15845 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - source_id__h15918 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - source_id__h15991 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - source_id__h16064 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - source_id__h16137 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - source_id__h16210 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - source_id__h16283 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - source_id__h16356 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - source_id__h16429 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - source_id__h16502 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - source_id__h16575 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - source_id__h16648 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - source_id__h16721 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - source_id__h16794 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - source_id__h16867 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - source_id__h16940 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - source_id__h17013 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - source_id__h17086 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - source_id__h17159 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - source_id__h17232 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - source_id__h17305 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - source_id__h17378 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - source_id__h17451 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - source_id__h17524 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - source_id__h17597 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - source_id__h17670 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - source_id__h17743 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - source_id__h17816 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - source_id__h17889 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26930 = - (addr_offset__h26929[2:0] == 3'd4) ? - m_slave_xactor_f_wr_data$D_OUT[72:41] : - m_slave_xactor_f_wr_data$D_OUT[40:9] ; - assign x__h23673 = - { addr_offset__h13216[31:16], 4'd0, addr_offset__h13216[11:0] } ; - assign x__h26361 = - (addr_offset__h13216[2:0] == 3'd4) ? - rdata___1__h26404 : - rdata__h26202 ; - assign x__h67110 = - { addr_offset__h26929[31:16], 4'd0, addr_offset__h26929[11:0] } ; - assign y_avValue_fst__h26094 = (x__h24011 == 5'd0) ? v__h25455 : 64'd0 ; - assign y_avValue_fst__h26115 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_fst__h26094 : - 64'd0 ; - assign y_avValue_fst__h26127 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - v__h23761 : - 64'd0 ; - assign y_avValue_fst__h26143 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - v__h18144 : - 64'd0 ; - assign y_avValue_fst__h26159 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - v__h13671 : - 64'd0 ; - assign y_avValue_fst__h26164 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_fst__h26143 : - y_avValue_fst__h26148 ; - assign y_avValue_fst__h26175 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - v__h13422 : - 64'd0 ; - assign y_avValue_fst__h26180 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_fst__h26159 : - y_avValue_fst__h26164 ; - assign y_avValue_fst__h26194 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_fst__h26175 : - y_avValue_fst__h26180 ; - assign y_avValue_snd__h26095 = (x__h24011 == 5'd0) ? 2'b0 : 2'b10 ; - assign y_avValue_snd__h26116 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_snd__h26095 : - 2'b10 ; - assign y_avValue_snd__h26128 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26144 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26160 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26165 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_snd__h26144 : - y_avValue_snd__h26149 ; - assign y_avValue_snd__h26176 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26181 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_snd__h26160 : - y_avValue_snd__h26165 ; - assign y_avValue_snd__h26195 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_snd__h26176 : - y_avValue_snd__h26181 ; - always@(addr_offset__h13216 or - m_vrg_source_prio_0 or - m_vrg_source_prio_1 or - m_vrg_source_prio_2 or - m_vrg_source_prio_3 or - m_vrg_source_prio_4 or - m_vrg_source_prio_5 or - m_vrg_source_prio_6 or - m_vrg_source_prio_7 or - m_vrg_source_prio_8 or - m_vrg_source_prio_9 or - m_vrg_source_prio_10 or - m_vrg_source_prio_11 or - m_vrg_source_prio_12 or - m_vrg_source_prio_13 or - m_vrg_source_prio_14 or - m_vrg_source_prio_15 or m_vrg_source_prio_16) - begin - case (addr_offset__h13216[11:2]) - 10'd0: x__h13493 = m_vrg_source_prio_0; - 10'd1: x__h13493 = m_vrg_source_prio_1; - 10'd2: x__h13493 = m_vrg_source_prio_2; - 10'd3: x__h13493 = m_vrg_source_prio_3; - 10'd4: x__h13493 = m_vrg_source_prio_4; - 10'd5: x__h13493 = m_vrg_source_prio_5; - 10'd6: x__h13493 = m_vrg_source_prio_6; - 10'd7: x__h13493 = m_vrg_source_prio_7; - 10'd8: x__h13493 = m_vrg_source_prio_8; - 10'd9: x__h13493 = m_vrg_source_prio_9; - 10'd10: x__h13493 = m_vrg_source_prio_10; - 10'd11: x__h13493 = m_vrg_source_prio_11; - 10'd12: x__h13493 = m_vrg_source_prio_12; - 10'd13: x__h13493 = m_vrg_source_prio_13; - 10'd14: x__h13493 = m_vrg_source_prio_14; - 10'd15: x__h13493 = m_vrg_source_prio_15; - 10'd16: x__h13493 = m_vrg_source_prio_16; - default: x__h13493 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_target_threshold_0 or m_vrg_target_threshold_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h23832 = m_vrg_target_threshold_0; - 5'd1: x__h23832 = m_vrg_target_threshold_1; - default: x__h23832 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h24011 = m_vrg_servicing_source_0; - 5'd1: x__h24011 = m_vrg_servicing_source_1; - default: x__h24011 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h26929 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h26929[16:12]) - 5'd0: x__h67487 = m_vrg_servicing_source_0; - 5'd1: x__h67487 = m_vrg_servicing_source_1; - default: x__h67487 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15665 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15665) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15772 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15772) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15845 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15845) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15918 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15918) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15991 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15991) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16064 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16064) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17159 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17159) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16137 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16137) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16210 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16210) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16283 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16283) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16356 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16356) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16429 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16429) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16502 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16502) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16575 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16575) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16648 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16648) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16721 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16721) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16794 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16794) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16867 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16867) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16940 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16940) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17013 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17013) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17086 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17086) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17232 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17232) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17305 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17305) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17378 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17378) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17451 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17451) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17524 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17524) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17597 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17597) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17670 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17670) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17743 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17743) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17889 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17889) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17816 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17816) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_snd__h26128 or y_avValue_snd__h26116) - begin - case (x__h23673) - 32'h00200000: y_avValue_snd__h26149 = y_avValue_snd__h26128; - 32'h00200004: y_avValue_snd__h26149 = y_avValue_snd__h26116; - default: y_avValue_snd__h26149 = 2'b10; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_0_1; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_1_1; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_0_2; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_1_2; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_0_3; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_1_3; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_0_4; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_1_4; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_0_5; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_1_5; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_0_6; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_1_6; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_0_7; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_1_7; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_0_8; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_1_8; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_0_9; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_1_9; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_0_10; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_1_10; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_0_11; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_1_11; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_0_12; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_1_12; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_0_13; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_1_13; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_0_14; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_1_14; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_0_15; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_1_15; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_0_16; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_1_16; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_fst__h26127 or y_avValue_fst__h26115) - begin - case (x__h23673) - 32'h00200000: y_avValue_fst__h26148 = y_avValue_fst__h26127; - 32'h00200004: y_avValue_fst__h26148 = y_avValue_fst__h26115; - default: y_avValue_fst__h26148 = 64'd0; - endcase - end - always@(source_id__h67436 or - m_vrg_source_busy_0 or - m_vrg_source_busy_1 or - m_vrg_source_busy_2 or - m_vrg_source_busy_3 or - m_vrg_source_busy_4 or - m_vrg_source_busy_5 or - m_vrg_source_busy_6 or - m_vrg_source_busy_7 or - m_vrg_source_busy_8 or - m_vrg_source_busy_9 or - m_vrg_source_busy_10 or - m_vrg_source_busy_11 or - m_vrg_source_busy_12 or - m_vrg_source_busy_13 or - m_vrg_source_busy_14 or - m_vrg_source_busy_15 or m_vrg_source_busy_16) - begin - case (source_id__h67436) - 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_0; - 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_1; - 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_2; - 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_3; - 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_4; - 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_5; - 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_6; - 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_7; - 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_8; - 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_9; - 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_10; - 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_11; - 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_12; - 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_13; - 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_14; - 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_15; - 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h67110 or v__h67144 or v__h67432) - begin - case (x__h67110) - 32'h00200000: v__h67107 = v__h67144; - 32'h00200004: v__h67107 = v__h67432; - default: v__h67107 = 2'b10; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_cfg_verbosity$EN) - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN; - if (m_vrg_servicing_source_0$EN) - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_0$D_IN; - if (m_vrg_servicing_source_1$EN) - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_1$D_IN; - if (m_vrg_source_busy_0$EN) - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_0$D_IN; - if (m_vrg_source_busy_1$EN) - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_1$D_IN; - if (m_vrg_source_busy_10$EN) - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_10$D_IN; - if (m_vrg_source_busy_11$EN) - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_11$D_IN; - if (m_vrg_source_busy_12$EN) - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_12$D_IN; - if (m_vrg_source_busy_13$EN) - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_13$D_IN; - if (m_vrg_source_busy_14$EN) - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_14$D_IN; - if (m_vrg_source_busy_15$EN) - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_15$D_IN; - if (m_vrg_source_busy_16$EN) - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_16$D_IN; - if (m_vrg_source_busy_2$EN) - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_2$D_IN; - if (m_vrg_source_busy_3$EN) - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_3$D_IN; - if (m_vrg_source_busy_4$EN) - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_4$D_IN; - if (m_vrg_source_busy_5$EN) - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_5$D_IN; - if (m_vrg_source_busy_6$EN) - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_6$D_IN; - if (m_vrg_source_busy_7$EN) - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_7$D_IN; - if (m_vrg_source_busy_8$EN) - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_8$D_IN; - if (m_vrg_source_busy_9$EN) - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_9$D_IN; - if (m_vrg_source_ip_0$EN) - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_0$D_IN; - if (m_vrg_source_ip_1$EN) - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_1$D_IN; - if (m_vrg_source_ip_10$EN) - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_10$D_IN; - if (m_vrg_source_ip_11$EN) - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_11$D_IN; - if (m_vrg_source_ip_12$EN) - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_12$D_IN; - if (m_vrg_source_ip_13$EN) - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_13$D_IN; - if (m_vrg_source_ip_14$EN) - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_14$D_IN; - if (m_vrg_source_ip_15$EN) - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_15$D_IN; - if (m_vrg_source_ip_16$EN) - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_16$D_IN; - if (m_vrg_source_ip_2$EN) - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_2$D_IN; - if (m_vrg_source_ip_3$EN) - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_3$D_IN; - if (m_vrg_source_ip_4$EN) - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_4$D_IN; - if (m_vrg_source_ip_5$EN) - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_5$D_IN; - if (m_vrg_source_ip_6$EN) - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_6$D_IN; - if (m_vrg_source_ip_7$EN) - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_7$D_IN; - if (m_vrg_source_ip_8$EN) - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_8$D_IN; - if (m_vrg_source_ip_9$EN) - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_9$D_IN; - if (m_vrg_source_prio_0$EN) - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_0$D_IN; - if (m_vrg_source_prio_1$EN) - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_1$D_IN; - if (m_vrg_source_prio_10$EN) - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_10$D_IN; - if (m_vrg_source_prio_11$EN) - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_11$D_IN; - if (m_vrg_source_prio_12$EN) - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_12$D_IN; - if (m_vrg_source_prio_13$EN) - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_13$D_IN; - if (m_vrg_source_prio_14$EN) - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_14$D_IN; - if (m_vrg_source_prio_15$EN) - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_15$D_IN; - if (m_vrg_source_prio_16$EN) - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_16$D_IN; - if (m_vrg_source_prio_2$EN) - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_2$D_IN; - if (m_vrg_source_prio_3$EN) - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_3$D_IN; - if (m_vrg_source_prio_4$EN) - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_4$D_IN; - if (m_vrg_source_prio_5$EN) - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_5$D_IN; - if (m_vrg_source_prio_6$EN) - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_6$D_IN; - if (m_vrg_source_prio_7$EN) - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_7$D_IN; - if (m_vrg_source_prio_8$EN) - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_8$D_IN; - if (m_vrg_source_prio_9$EN) - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_9$D_IN; - if (m_vrg_target_threshold_0$EN) - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_0$D_IN; - if (m_vrg_target_threshold_1$EN) - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_1$D_IN; - if (m_vvrg_ie_0_0$EN) - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_0$D_IN; - if (m_vvrg_ie_0_1$EN) - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_1$D_IN; - if (m_vvrg_ie_0_10$EN) - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_10$D_IN; - if (m_vvrg_ie_0_11$EN) - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_11$D_IN; - if (m_vvrg_ie_0_12$EN) - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_12$D_IN; - if (m_vvrg_ie_0_13$EN) - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_13$D_IN; - if (m_vvrg_ie_0_14$EN) - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_14$D_IN; - if (m_vvrg_ie_0_15$EN) - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_15$D_IN; - if (m_vvrg_ie_0_16$EN) - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_16$D_IN; - if (m_vvrg_ie_0_2$EN) - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_2$D_IN; - if (m_vvrg_ie_0_3$EN) - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_3$D_IN; - if (m_vvrg_ie_0_4$EN) - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_4$D_IN; - if (m_vvrg_ie_0_5$EN) - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_5$D_IN; - if (m_vvrg_ie_0_6$EN) - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_6$D_IN; - if (m_vvrg_ie_0_7$EN) - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_7$D_IN; - if (m_vvrg_ie_0_8$EN) - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_8$D_IN; - if (m_vvrg_ie_0_9$EN) - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_9$D_IN; - if (m_vvrg_ie_1_0$EN) - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_0$D_IN; - if (m_vvrg_ie_1_1$EN) - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_1$D_IN; - if (m_vvrg_ie_1_10$EN) - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_10$D_IN; - if (m_vvrg_ie_1_11$EN) - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_11$D_IN; - if (m_vvrg_ie_1_12$EN) - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_12$D_IN; - if (m_vvrg_ie_1_13$EN) - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_13$D_IN; - if (m_vvrg_ie_1_14$EN) - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_14$D_IN; - if (m_vvrg_ie_1_15$EN) - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_15$D_IN; - if (m_vvrg_ie_1_16$EN) - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_16$D_IN; - if (m_vvrg_ie_1_2$EN) - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_2$D_IN; - if (m_vvrg_ie_1_3$EN) - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_3$D_IN; - if (m_vvrg_ie_1_4$EN) - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_4$D_IN; - if (m_vvrg_ie_1_5$EN) - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_5$D_IN; - if (m_vvrg_ie_1_6$EN) - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_6$D_IN; - if (m_vvrg_ie_1_7$EN) - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_7$D_IN; - if (m_vvrg_ie_1_8$EN) - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_8$D_IN; - if (m_vvrg_ie_1_9$EN) - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_9$D_IN; - end - if (m_rg_addr_base$EN) - m_rg_addr_base <= `BSV_ASSIGNMENT_DELAY m_rg_addr_base$D_IN; - if (m_rg_addr_lim$EN) - m_rg_addr_lim <= `BSV_ASSIGNMENT_DELAY m_rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_cfg_verbosity = 4'hA; - m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - m_vrg_servicing_source_0 = 5'h0A; - m_vrg_servicing_source_1 = 5'h0A; - m_vrg_source_busy_0 = 1'h0; - m_vrg_source_busy_1 = 1'h0; - m_vrg_source_busy_10 = 1'h0; - m_vrg_source_busy_11 = 1'h0; - m_vrg_source_busy_12 = 1'h0; - m_vrg_source_busy_13 = 1'h0; - m_vrg_source_busy_14 = 1'h0; - m_vrg_source_busy_15 = 1'h0; - m_vrg_source_busy_16 = 1'h0; - m_vrg_source_busy_2 = 1'h0; - m_vrg_source_busy_3 = 1'h0; - m_vrg_source_busy_4 = 1'h0; - m_vrg_source_busy_5 = 1'h0; - m_vrg_source_busy_6 = 1'h0; - m_vrg_source_busy_7 = 1'h0; - m_vrg_source_busy_8 = 1'h0; - m_vrg_source_busy_9 = 1'h0; - m_vrg_source_ip_0 = 1'h0; - m_vrg_source_ip_1 = 1'h0; - m_vrg_source_ip_10 = 1'h0; - m_vrg_source_ip_11 = 1'h0; - m_vrg_source_ip_12 = 1'h0; - m_vrg_source_ip_13 = 1'h0; - m_vrg_source_ip_14 = 1'h0; - m_vrg_source_ip_15 = 1'h0; - m_vrg_source_ip_16 = 1'h0; - m_vrg_source_ip_2 = 1'h0; - m_vrg_source_ip_3 = 1'h0; - m_vrg_source_ip_4 = 1'h0; - m_vrg_source_ip_5 = 1'h0; - m_vrg_source_ip_6 = 1'h0; - m_vrg_source_ip_7 = 1'h0; - m_vrg_source_ip_8 = 1'h0; - m_vrg_source_ip_9 = 1'h0; - m_vrg_source_prio_0 = 3'h2; - m_vrg_source_prio_1 = 3'h2; - m_vrg_source_prio_10 = 3'h2; - m_vrg_source_prio_11 = 3'h2; - m_vrg_source_prio_12 = 3'h2; - m_vrg_source_prio_13 = 3'h2; - m_vrg_source_prio_14 = 3'h2; - m_vrg_source_prio_15 = 3'h2; - m_vrg_source_prio_16 = 3'h2; - m_vrg_source_prio_2 = 3'h2; - m_vrg_source_prio_3 = 3'h2; - m_vrg_source_prio_4 = 3'h2; - m_vrg_source_prio_5 = 3'h2; - m_vrg_source_prio_6 = 3'h2; - m_vrg_source_prio_7 = 3'h2; - m_vrg_source_prio_8 = 3'h2; - m_vrg_source_prio_9 = 3'h2; - m_vrg_target_threshold_0 = 3'h2; - m_vrg_target_threshold_1 = 3'h2; - m_vvrg_ie_0_0 = 1'h0; - m_vvrg_ie_0_1 = 1'h0; - m_vvrg_ie_0_10 = 1'h0; - m_vvrg_ie_0_11 = 1'h0; - m_vvrg_ie_0_12 = 1'h0; - m_vvrg_ie_0_13 = 1'h0; - m_vvrg_ie_0_14 = 1'h0; - m_vvrg_ie_0_15 = 1'h0; - m_vvrg_ie_0_16 = 1'h0; - m_vvrg_ie_0_2 = 1'h0; - m_vvrg_ie_0_3 = 1'h0; - m_vvrg_ie_0_4 = 1'h0; - m_vvrg_ie_0_5 = 1'h0; - m_vvrg_ie_0_6 = 1'h0; - m_vvrg_ie_0_7 = 1'h0; - m_vvrg_ie_0_8 = 1'h0; - m_vvrg_ie_0_9 = 1'h0; - m_vvrg_ie_1_0 = 1'h0; - m_vvrg_ie_1_1 = 1'h0; - m_vvrg_ie_1_10 = 1'h0; - m_vvrg_ie_1_11 = 1'h0; - m_vvrg_ie_1_12 = 1'h0; - m_vvrg_ie_1_13 = 1'h0; - m_vvrg_ie_1_14 = 1'h0; - m_vvrg_ie_1_15 = 1'h0; - m_vvrg_ie_1_16 = 1'h0; - m_vvrg_ie_1_2 = 1'h0; - m_vvrg_ie_1_3 = 1'h0; - m_vvrg_ie_1_4 = 1'h0; - m_vvrg_ie_1_5 = 1'h0; - m_vvrg_ie_1_6 = 1'h0; - m_vvrg_ie_1_7 = 1'h0; - m_vvrg_ie_1_8 = 1'h0; - m_vvrg_ie_1_9 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src IPs :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src Prios:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src busy :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71312, - m_vrg_target_threshold_0, - b__h71313, - m_vrg_servicing_source_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73317, - m_vrg_target_threshold_1, - b__h73318, - m_vrg_servicing_source_1); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - begin - v__h75676 = $stime; - #0; - end - v__h75670 = v__h75676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75670, - $signed(32'd1), - v_sources_0_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - begin - v__h75874 = $stime; - #0; - end - v__h75868 = v__h75874 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75868, - $signed(32'd2), - v_sources_1_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - begin - v__h76072 = $stime; - #0; - end - v__h76066 = v__h76072 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76066, - $signed(32'd3), - v_sources_2_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - begin - v__h76270 = $stime; - #0; - end - v__h76264 = v__h76270 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76264, - $signed(32'd4), - v_sources_3_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - begin - v__h76468 = $stime; - #0; - end - v__h76462 = v__h76468 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76462, - $signed(32'd5), - v_sources_4_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - begin - v__h76666 = $stime; - #0; - end - v__h76660 = v__h76666 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76660, - $signed(32'd6), - v_sources_5_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - begin - v__h76864 = $stime; - #0; - end - v__h76858 = v__h76864 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76858, - $signed(32'd7), - v_sources_6_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - begin - v__h77062 = $stime; - #0; - end - v__h77056 = v__h77062 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77056, - $signed(32'd8), - v_sources_7_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - begin - v__h77260 = $stime; - #0; - end - v__h77254 = v__h77260 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77254, - $signed(32'd9), - v_sources_8_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - begin - v__h77458 = $stime; - #0; - end - v__h77452 = v__h77458 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77452, - $signed(32'd10), - v_sources_9_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - begin - v__h77656 = $stime; - #0; - end - v__h77650 = v__h77656 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77650, - $signed(32'd11), - v_sources_10_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - begin - v__h77854 = $stime; - #0; - end - v__h77848 = v__h77854 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77848, - $signed(32'd12), - v_sources_11_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - begin - v__h78052 = $stime; - #0; - end - v__h78046 = v__h78052 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78046, - $signed(32'd13), - v_sources_12_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - begin - v__h78250 = $stime; - #0; - end - v__h78244 = v__h78250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78244, - $signed(32'd14), - v_sources_13_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - begin - v__h78448 = $stime; - #0; - end - v__h78442 = v__h78448 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78442, - $signed(32'd15), - v_sources_14_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - begin - v__h78646 = $stime; - #0; - end - v__h78640 = v__h78646 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78640, - $signed(32'd16), - v_sources_15_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - begin - v__h6144 = $stime; - #0; - end - v__h6138 = v__h6144 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h6138); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h13080 = $stime; - #0; - end - v__h13074 = v__h13080 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req:", v__h13074); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - begin - v__h13265 = $stime; - #0; - end - v__h13259 = v__h13265 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h13259); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - begin - v__h13463 = $stime; - #0; - end - v__h13457 = v__h13463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h13457, - addr_offset__h13216[11:2], - v__h13422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - begin - v__h13713 = $stime; - #0; - end - v__h13707 = v__h13713 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h13707, - source_id_base__h13630, - v__h13671); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - begin - v__h18186 = $stime; - #0; - end - v__h18180 = v__h18186 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h18180, - source_id_base__h13630, - v__h18144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - begin - v__h23802 = $stime; - #0; - end - v__h23796 = v__h23802 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h23796, - addr_offset__h13216[16:12], - v__h23761); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - begin - v__h25975 = $stime; - #0; - end - v__h25969 = v__h25975 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h25969, - addr_offset__h13216[16:12], - v__h25474); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - begin - v__h24056 = $stime; - #0; - end - v__h24050 = v__h24056 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h24050, - addr_offset__h13216[16:12]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Still servicing interrupt from source %0d", x__h24011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Trying to claim service for source %0d", - max_id__h23959); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Ignoring."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - begin - v__h26250 = $stime; - #0; - end - v__h26244 = v__h26250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h26244); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26463 = $stime; - #0; - end - v__h26457 = v__h26463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req", v__h26457); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", x__h26361); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", rresp__h26203); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26740 = $stime; - #0; - end - v__h26734 = v__h26740 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26734); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - begin - v__h26968 = $stime; - #0; - end - v__h26962 = v__h26968 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26962); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - begin - v__h27865 = $stime; - #0; - end - v__h27859 = v__h27865 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27859, - addr_offset__h26929[11:2], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - begin - v__h28048 = $stime; - #0; - end - v__h28042 = v__h28048 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28042, - source_id_base__h28148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - begin - v__h67030 = $stime; - #0; - end - v__h67024 = v__h67030 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67024, - addr_offset__h26929[11:7], - source_id_base__h28148, - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - begin - v__h67318 = $stime; - #0; - end - v__h67312 = v__h67318 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67312, - addr_offset__h26929[16:12], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - begin - v__h67847 = $stime; - #0; - end - v__h67841 = v__h67847 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67841, - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - begin - v__h67933 = $stime; - #0; - end - v__h67927 = v__h67933 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67927); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Completion message from target %0d to source %0d", - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Ignoring"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - begin - v__h68132 = $stime; - #0; - end - v__h68126 = v__h68132 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68126); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h68353 = $stime; - #0; - end - v__h68347 = v__h68353 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68347); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26934); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h74690 = $stime; - #0; - end - v__h74684 = v__h74690 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74684, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h74800 = $stime; - #0; - end - v__h74794 = v__h74800 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74794, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - begin - v__h74913 = $stime; - #0; - end - v__h74907 = v__h74913 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74907, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkPLIC_16_2_7 - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v deleted file mode 100644 index f852a5f3..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v +++ /dev/null @@ -1,734 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_req_reset O 1 const -// RDY_rsp_reset O 1 const -// valid O 1 -// word O 64 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_is_OP_not_OP_32 I 1 -// req_f3 I 3 -// req_v1 I 64 -// req_v2 I 64 -// EN_set_verbosity I 1 -// EN_req_reset I 1 unused -// EN_rsp_reset I 1 unused -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkRISCV_MBox(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_req_reset, - RDY_req_reset, - - EN_rsp_reset, - RDY_rsp_reset, - - req_is_OP_not_OP_32, - req_f3, - req_v1, - req_v2, - EN_req, - - valid, - - word); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method req_reset - input EN_req_reset; - output RDY_req_reset; - - // action method rsp_reset - input EN_rsp_reset; - output RDY_rsp_reset; - - // action method req - input req_is_OP_not_OP_32; - input [2 : 0] req_f3; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input EN_req; - - // value method valid - output valid; - - // value method word - output [63 : 0] word; - - // signals for module outputs - wire [63 : 0] word; - wire RDY_req_reset, RDY_rsp_reset, RDY_set_verbosity, valid; - - // inlined wires - wire dw_valid$whas; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register intDiv_rg_denom2 - reg [63 : 0] intDiv_rg_denom2; - reg [63 : 0] intDiv_rg_denom2$D_IN; - wire intDiv_rg_denom2$EN; - - // register intDiv_rg_denom_is_signed - reg intDiv_rg_denom_is_signed; - wire intDiv_rg_denom_is_signed$D_IN, intDiv_rg_denom_is_signed$EN; - - // register intDiv_rg_n - reg [63 : 0] intDiv_rg_n; - reg [63 : 0] intDiv_rg_n$D_IN; - wire intDiv_rg_n$EN; - - // register intDiv_rg_numer_is_signed - reg intDiv_rg_numer_is_signed; - wire intDiv_rg_numer_is_signed$D_IN, intDiv_rg_numer_is_signed$EN; - - // register intDiv_rg_quo - reg [63 : 0] intDiv_rg_quo; - reg [63 : 0] intDiv_rg_quo$D_IN; - wire intDiv_rg_quo$EN; - - // register intDiv_rg_quoIsNeg - reg intDiv_rg_quoIsNeg; - wire intDiv_rg_quoIsNeg$D_IN, intDiv_rg_quoIsNeg$EN; - - // register intDiv_rg_remIsNeg - reg intDiv_rg_remIsNeg; - wire intDiv_rg_remIsNeg$D_IN, intDiv_rg_remIsNeg$EN; - - // register intDiv_rg_state - reg [2 : 0] intDiv_rg_state; - reg [2 : 0] intDiv_rg_state$D_IN; - wire intDiv_rg_state$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_is_OP_not_OP_32 - reg rg_is_OP_not_OP_32; - wire rg_is_OP_not_OP_32$D_IN, rg_is_OP_not_OP_32$EN; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_v1 - reg [63 : 0] rg_v1; - reg [63 : 0] rg_v1$D_IN; - wire rg_v1$EN; - - // register rg_v2 - reg [63 : 0] rg_v2; - wire [63 : 0] rg_v2$D_IN; - wire rg_v2$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_intDiv_rl_loop1, - CAN_FIRE_RL_intDiv_rl_loop2, - CAN_FIRE_RL_intDiv_rl_start_div_by_zero, - CAN_FIRE_RL_intDiv_rl_start_overflow, - CAN_FIRE_RL_intDiv_rl_start_s, - CAN_FIRE_RL_rg_div_rem, - CAN_FIRE_RL_rl_mul, - CAN_FIRE_RL_rl_mul2, - CAN_FIRE_req, - CAN_FIRE_req_reset, - CAN_FIRE_rsp_reset, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_intDiv_rl_loop1, - WILL_FIRE_RL_intDiv_rl_loop2, - WILL_FIRE_RL_intDiv_rl_start_div_by_zero, - WILL_FIRE_RL_intDiv_rl_start_overflow, - WILL_FIRE_RL_intDiv_rl_start_s, - WILL_FIRE_RL_rg_div_rem, - WILL_FIRE_RL_rl_mul, - WILL_FIRE_RL_rl_mul2, - WILL_FIRE_req, - WILL_FIRE_req_reset, - WILL_FIRE_rsp_reset, - WILL_FIRE_set_verbosity; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_dw_result$wset_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_1, - MUX_intDiv_rg_denom2$write_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_3, - MUX_intDiv_rg_n$write_1__VAL_1, - MUX_intDiv_rg_n$write_1__VAL_2, - MUX_intDiv_rg_quo$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_2, - MUX_rg_v1$write_1__VAL_3, - MUX_rg_v1$write_1__VAL_4, - MUX_rg_v2$write_1__VAL_1; - wire [1 : 0] MUX_rg_state$write_1__VAL_1; - wire MUX_intDiv_rg_denom2$write_1__SEL_1, - MUX_intDiv_rg_denom2$write_1__SEL_2, - MUX_intDiv_rg_quo$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_2, - MUX_intDiv_rg_state$write_1__SEL_3, - MUX_rg_v1$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4706; - reg [31 : 0] v__h4700; - // synopsys translate_on - - // remaining internal signals - wire [255 : 0] SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118, - SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110, - _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115; - wire [127 : 0] SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125, - SEXT_rg_v1____d108, - rg_v1_MUL_rg_v2___d105, - v1__h4494; - wire [63 : 0] IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138, - _theResult___fst__h5162, - _theResult___fst__h5192, - _theResult___fst__h5218, - _theResult___fst__h787, - _theResult___snd__h5163, - _theResult___snd__h5193, - _theResult___snd__h5219, - _theResult___snd_fst__h782, - denom___1__h729, - numer___1__h728, - result___1__h4957, - v__h4418, - v__h4476, - v__h4527, - v__h4583, - v__h4600, - x__h3955, - x__h4041, - x__h4111, - x__h4126, - y__h3834; - wire [31 : 0] IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3, - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6, - req_v1_BITS_31_TO_0__q1, - req_v2_BITS_31_TO_0__q2, - rg_v1_BITS_31_TO_0__q4, - rg_v2_BITS_31_TO_0__q5; - wire IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39, - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47, - rg_v1_ULT_intDiv_rg_denom2_4___d59, - rg_v1_ULT_rg_v2___d55; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method req_reset - assign RDY_req_reset = 1'd1 ; - assign CAN_FIRE_req_reset = 1'd1 ; - assign WILL_FIRE_req_reset = EN_req_reset ; - - // action method rsp_reset - assign RDY_rsp_reset = 1'd1 ; - assign CAN_FIRE_rsp_reset = 1'd1 ; - assign WILL_FIRE_rsp_reset = EN_rsp_reset ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method word - assign word = WILL_FIRE_RL_rl_mul2 ? rg_v1 : MUX_dw_result$wset_1__VAL_2 ; - - // rule RL_rl_mul2 - assign CAN_FIRE_RL_rl_mul2 = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_mul2 = CAN_FIRE_RL_rl_mul2 ; - - // rule RL_rg_div_rem - assign CAN_FIRE_RL_rg_div_rem = - rg_state == 2'd2 && intDiv_rg_state == 3'd4 ; - assign WILL_FIRE_RL_rg_div_rem = CAN_FIRE_RL_rg_div_rem ; - - // rule RL_intDiv_rl_start_div_by_zero - assign CAN_FIRE_RL_intDiv_rl_start_div_by_zero = - intDiv_rg_state == 3'd1 && rg_v2 == 64'd0 ; - assign WILL_FIRE_RL_intDiv_rl_start_div_by_zero = - CAN_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // rule RL_intDiv_rl_start_overflow - assign CAN_FIRE_RL_intDiv_rl_start_overflow = - intDiv_rg_state == 3'd1 && intDiv_rg_numer_is_signed && - rg_v1 == 64'h8000000000000000 && - intDiv_rg_denom_is_signed && - rg_v2 == 64'hFFFFFFFFFFFFFFFF ; - assign WILL_FIRE_RL_intDiv_rl_start_overflow = - CAN_FIRE_RL_intDiv_rl_start_overflow && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_start_s - assign CAN_FIRE_RL_intDiv_rl_start_s = - intDiv_rg_state == 3'd1 && rg_v2 != 64'd0 && - (!intDiv_rg_numer_is_signed || rg_v1 != 64'h8000000000000000 || - !intDiv_rg_denom_is_signed || - rg_v2 != 64'hFFFFFFFFFFFFFFFF) ; - assign WILL_FIRE_RL_intDiv_rl_start_s = - CAN_FIRE_RL_intDiv_rl_start_s && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_loop1 - assign CAN_FIRE_RL_intDiv_rl_loop1 = intDiv_rg_state == 3'd2 ; - assign WILL_FIRE_RL_intDiv_rl_loop1 = CAN_FIRE_RL_intDiv_rl_loop1 ; - - // rule RL_rl_mul - assign CAN_FIRE_RL_rl_mul = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_mul = rg_state == 2'd0 ; - - // rule RL_intDiv_rl_loop2 - assign CAN_FIRE_RL_intDiv_rl_loop2 = intDiv_rg_state == 3'd3 ; - assign WILL_FIRE_RL_intDiv_rl_loop2 = - CAN_FIRE_RL_intDiv_rl_loop2 && !WILL_FIRE_RL_rl_mul ; - - // inputs to muxes for submodule ports - assign MUX_intDiv_rg_denom2$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ; - assign MUX_intDiv_rg_denom2$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 ; - assign MUX_intDiv_rg_quo$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_quoIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_intDiv_rg_state$write_1__SEL_1 = EN_req && req_f3[2] ; - assign MUX_intDiv_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 ; - assign MUX_intDiv_rg_state$write_1__SEL_3 = - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ; - assign MUX_rg_v1$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_remIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_dw_result$wset_1__VAL_2 = - rg_is_OP_not_OP_32 ? - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138 : - result___1__h4957 ; - assign MUX_intDiv_rg_denom2$write_1__VAL_1 = - { intDiv_rg_denom2[62:0], 1'd0 } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_2 = - { 1'd0, intDiv_rg_denom2[63:1] } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_3 = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - denom___1__h729 : - _theResult___snd_fst__h782 ; - assign MUX_intDiv_rg_n$write_1__VAL_1 = { intDiv_rg_n[62:0], 1'd0 } ; - assign MUX_intDiv_rg_n$write_1__VAL_2 = { 1'd0, intDiv_rg_n[63:1] } ; - assign MUX_intDiv_rg_quo$write_1__VAL_1 = - rg_v1_ULT_rg_v2___d55 ? x__h4041 : x__h4126 ; - assign MUX_rg_state$write_1__VAL_1 = req_f3[2] ? 2'd2 : 2'd0 ; - assign MUX_rg_v1$write_1__VAL_1 = - req_is_OP_not_OP_32 ? req_v1 : _theResult___fst__h5162 ; - assign MUX_rg_v1$write_1__VAL_2 = - rg_v1_ULT_rg_v2___d55 ? x__h4111 : x__h3955 ; - assign MUX_rg_v1$write_1__VAL_3 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - rg_v1_MUL_rg_v2___d105[63:0] : - v__h4418 ; - assign MUX_rg_v1$write_1__VAL_4 = - intDiv_rg_numer_is_signed ? numer___1__h728 : rg_v1 ; - assign MUX_rg_v2$write_1__VAL_1 = - req_is_OP_not_OP_32 ? req_v2 : _theResult___snd__h5163 ; - - // inlined wires - assign dw_valid$whas = WILL_FIRE_RL_rg_div_rem || WILL_FIRE_RL_rl_mul2 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register intDiv_rg_denom2 - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_denom2$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_denom2$write_1__VAL_2 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_intDiv_rg_denom2$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_3; - default: intDiv_rg_denom2$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_denom2$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_denom_is_signed - assign intDiv_rg_denom_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_denom_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_n - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_n$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_n$write_1__VAL_2 or WILL_FIRE_RL_intDiv_rl_start_s) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_n$D_IN = 64'd1; - default: intDiv_rg_n$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_n$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_numer_is_signed - assign intDiv_rg_numer_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_numer_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_quo - always@(MUX_intDiv_rg_quo$write_1__SEL_1 or - MUX_intDiv_rg_quo$write_1__VAL_1 or - WILL_FIRE_RL_intDiv_rl_start_overflow or - rg_v1 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_quo$write_1__SEL_1: - intDiv_rg_quo$D_IN = MUX_intDiv_rg_quo$write_1__VAL_1; - WILL_FIRE_RL_intDiv_rl_start_overflow: intDiv_rg_quo$D_IN = rg_v1; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_quo$D_IN = 64'd0; - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_quo$D_IN = 64'hFFFFFFFFFFFFFFFF; - default: intDiv_rg_quo$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_quo$EN = - MUX_intDiv_rg_quo$write_1__SEL_1 || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register intDiv_rg_quoIsNeg - assign intDiv_rg_quoIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[63] != rg_v2[63] : - IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39 ; - assign intDiv_rg_quoIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_remIsNeg - assign intDiv_rg_remIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[63] : - intDiv_rg_numer_is_signed && rg_v1[63] ; - assign intDiv_rg_remIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_state - always@(MUX_intDiv_rg_state$write_1__SEL_1 or - MUX_intDiv_rg_state$write_1__SEL_2 or - MUX_intDiv_rg_state$write_1__SEL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_overflow or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - case (1'b1) - MUX_intDiv_rg_state$write_1__SEL_1: intDiv_rg_state$D_IN = 3'd1; - MUX_intDiv_rg_state$write_1__SEL_2: intDiv_rg_state$D_IN = 3'd4; - MUX_intDiv_rg_state$write_1__SEL_3: intDiv_rg_state$D_IN = 3'd3; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_state$D_IN = 3'd2; - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_state$D_IN = 3'd4; - default: intDiv_rg_state$D_IN = 3'b010 /* unspecified value */ ; - endcase - assign intDiv_rg_state$EN = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 || - EN_req && req_f3[2] || - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_is_OP_not_OP_32 - assign rg_is_OP_not_OP_32$D_IN = req_is_OP_not_OP_32 ; - assign rg_is_OP_not_OP_32$EN = EN_req ; - - // register rg_state - assign rg_state$D_IN = EN_req ? MUX_rg_state$write_1__VAL_1 : 2'd1 ; - assign rg_state$EN = EN_req || WILL_FIRE_RL_rl_mul ; - - // register rg_v1 - always@(EN_req or - MUX_rg_v1$write_1__VAL_1 or - MUX_rg_v1$write_1__SEL_2 or - MUX_rg_v1$write_1__VAL_2 or - WILL_FIRE_RL_rl_mul or - MUX_rg_v1$write_1__VAL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_rg_v1$write_1__VAL_4 or WILL_FIRE_RL_intDiv_rl_start_overflow) - case (1'b1) - EN_req: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_1; - MUX_rg_v1$write_1__SEL_2: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_2; - WILL_FIRE_RL_rl_mul: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_3; - WILL_FIRE_RL_intDiv_rl_start_s: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_4; - WILL_FIRE_RL_intDiv_rl_start_overflow: rg_v1$D_IN = 64'd0; - default: rg_v1$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign rg_v1$EN = - MUX_rg_v1$write_1__SEL_2 || WILL_FIRE_RL_rl_mul || EN_req || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow ; - - // register rg_v2 - assign rg_v2$D_IN = - EN_req ? - MUX_rg_v2$write_1__VAL_1 : - MUX_intDiv_rg_denom2$write_1__VAL_3 ; - assign rg_v2$EN = EN_req || WILL_FIRE_RL_intDiv_rl_start_s ; - - // remaining internal signals - assign IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39 = - intDiv_rg_numer_is_signed ? - rg_v1[63] : - intDiv_rg_denom_is_signed && rg_v2[63] ; - assign IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138 = - rg_f3[1] ? rg_v1 : intDiv_rg_quo ; - assign IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3 = - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138[31:0] ; - assign SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125 = - { {32{rg_v1_BITS_31_TO_0__q4[31]}}, rg_v1_BITS_31_TO_0__q4 } * - { {32{rg_v2_BITS_31_TO_0__q5[31]}}, rg_v2_BITS_31_TO_0__q5 } ; - assign SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6 = - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125[31:0] ; - assign SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118 = - SEXT_rg_v1____d108 * { 64'd0, rg_v2 } ; - assign SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110 = - SEXT_rg_v1____d108 * { {64{rg_v2[63]}}, rg_v2 } ; - assign SEXT_rg_v1____d108 = { {64{rg_v1[63]}}, rg_v1 } ; - assign _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115 = - v1__h4494 * { 64'd0, rg_v2 } ; - assign _theResult___fst__h5162 = - req_f3[0] ? _theResult___fst__h5218 : _theResult___fst__h5192 ; - assign _theResult___fst__h5192 = - { {32{req_v1_BITS_31_TO_0__q1[31]}}, req_v1_BITS_31_TO_0__q1 } ; - assign _theResult___fst__h5218 = { 32'd0, req_v1[31:0] } ; - assign _theResult___fst__h787 = - intDiv_rg_denom_is_signed ? denom___1__h729 : rg_v2 ; - assign _theResult___snd__h5163 = - req_f3[0] ? _theResult___snd__h5219 : _theResult___snd__h5193 ; - assign _theResult___snd__h5193 = - { {32{req_v2_BITS_31_TO_0__q2[31]}}, req_v2_BITS_31_TO_0__q2 } ; - assign _theResult___snd__h5219 = { 32'd0, req_v2[31:0] } ; - assign _theResult___snd_fst__h782 = - intDiv_rg_numer_is_signed ? rg_v2 : _theResult___fst__h787 ; - assign denom___1__h729 = rg_v2[63] ? -rg_v2 : rg_v2 ; - assign intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 = - intDiv_rg_denom2 <= y__h3834 ; - assign numer___1__h728 = rg_v1[63] ? x__h4111 : rg_v1 ; - assign req_v1_BITS_31_TO_0__q1 = req_v1[31:0] ; - assign req_v2_BITS_31_TO_0__q2 = req_v2[31:0] ; - assign result___1__h4957 = - { {32{IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3[31]}}, - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3 } ; - assign rg_v1_BITS_31_TO_0__q4 = rg_v1[31:0] ; - assign rg_v1_MUL_rg_v2___d105 = rg_v1 * rg_v2 ; - assign rg_v1_ULT_intDiv_rg_denom2_4___d59 = rg_v1 < intDiv_rg_denom2 ; - assign rg_v1_ULT_rg_v2___d55 = rg_v1 < rg_v2 ; - assign rg_v2_BITS_31_TO_0__q5 = rg_v2[31:0] ; - assign v1__h4494 = { 64'd0, rg_v1 } ; - assign v__h4418 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b001) ? - SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110[127:64] : - v__h4476 ; - assign v__h4476 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b011) ? - _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115[127:64] : - v__h4527 ; - assign v__h4527 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b010) ? - SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118[127:64] : - v__h4583 ; - assign v__h4583 = - (!rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - v__h4600 : - 64'hFFFFFFFFFFFFFFFF ; - assign v__h4600 = - { {32{SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6[31]}}, - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6 } ; - assign x__h3955 = rg_v1 - intDiv_rg_denom2 ; - assign x__h4041 = -intDiv_rg_quo ; - assign x__h4111 = -rg_v1 ; - assign x__h4126 = intDiv_rg_quo + intDiv_rg_n ; - assign y__h3834 = { 1'd0, rg_v1[63:1] } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (intDiv_rg_state$EN) - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY intDiv_rg_state$D_IN; - end - if (intDiv_rg_denom2$EN) - intDiv_rg_denom2 <= `BSV_ASSIGNMENT_DELAY intDiv_rg_denom2$D_IN; - if (intDiv_rg_denom_is_signed$EN) - intDiv_rg_denom_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_denom_is_signed$D_IN; - if (intDiv_rg_n$EN) intDiv_rg_n <= `BSV_ASSIGNMENT_DELAY intDiv_rg_n$D_IN; - if (intDiv_rg_numer_is_signed$EN) - intDiv_rg_numer_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_numer_is_signed$D_IN; - if (intDiv_rg_quo$EN) - intDiv_rg_quo <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quo$D_IN; - if (intDiv_rg_quoIsNeg$EN) - intDiv_rg_quoIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quoIsNeg$D_IN; - if (intDiv_rg_remIsNeg$EN) - intDiv_rg_remIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_remIsNeg$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_is_OP_not_OP_32$EN) - rg_is_OP_not_OP_32 <= `BSV_ASSIGNMENT_DELAY rg_is_OP_not_OP_32$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_v1$EN) rg_v1 <= `BSV_ASSIGNMENT_DELAY rg_v1$D_IN; - if (rg_v2$EN) rg_v2 <= `BSV_ASSIGNMENT_DELAY rg_v2$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - intDiv_rg_denom2 = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_denom_is_signed = 1'h0; - intDiv_rg_n = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_numer_is_signed = 1'h0; - intDiv_rg_quo = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_quoIsNeg = 1'h0; - intDiv_rg_remIsNeg = 1'h0; - intDiv_rg_state = 3'h2; - rg_f3 = 3'h2; - rg_is_OP_not_OP_32 = 1'h0; - rg_state = 2'h2; - rg_v1 = 64'hAAAAAAAAAAAAAAAA; - rg_v2 = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && cfg_verbosity > 4'd1) - $display(" RISCV_MBox.rl_mul"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $display("%0d: ERROR: RISCV_MBox.rl_mul: illegal f3.", v__h4700); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $display(" f3 0x%0h v1 0x%0h v2 0x%0h", rg_f3, rg_v1, rg_v2); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkRISCV_MBox - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v deleted file mode 100644 index c88e21cd..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v +++ /dev/null @@ -1,298 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// m_near_mem_io_addr_base O 64 const -// m_near_mem_io_addr_size O 64 const -// m_near_mem_io_addr_lim O 64 const -// m_plic_addr_base O 64 const -// m_plic_addr_size O 64 const -// m_plic_addr_lim O 64 const -// m_uart0_addr_base O 64 const -// m_uart0_addr_size O 64 const -// m_uart0_addr_lim O 64 const -// m_boot_rom_addr_base O 64 const -// m_boot_rom_addr_size O 64 const -// m_boot_rom_addr_lim O 64 const -// m_mem0_controller_addr_base O 64 const -// m_mem0_controller_addr_size O 64 const -// m_mem0_controller_addr_lim O 64 const -// m_tcm_addr_base O 64 const -// m_tcm_addr_size O 64 const -// m_tcm_addr_lim O 64 const -// m_is_mem_addr O 1 -// m_is_IO_addr O 1 -// m_is_near_mem_IO_addr O 1 -// m_pc_reset_value O 64 const -// m_mtvec_reset_value O 64 const -// m_nmivec_reset_value O 64 const -// CLK I 1 unused -// RST_N I 1 unused -// m_is_mem_addr_addr I 64 -// m_is_IO_addr_addr I 64 -// m_is_near_mem_IO_addr_addr I 64 -// -// Combinational paths from inputs to outputs: -// m_is_mem_addr_addr -> m_is_mem_addr -// m_is_IO_addr_addr -> m_is_IO_addr -// m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Map(CLK, - RST_N, - - m_near_mem_io_addr_base, - - m_near_mem_io_addr_size, - - m_near_mem_io_addr_lim, - - m_plic_addr_base, - - m_plic_addr_size, - - m_plic_addr_lim, - - m_uart0_addr_base, - - m_uart0_addr_size, - - m_uart0_addr_lim, - - m_boot_rom_addr_base, - - m_boot_rom_addr_size, - - m_boot_rom_addr_lim, - - m_mem0_controller_addr_base, - - m_mem0_controller_addr_size, - - m_mem0_controller_addr_lim, - - m_tcm_addr_base, - - m_tcm_addr_size, - - m_tcm_addr_lim, - - m_is_mem_addr_addr, - m_is_mem_addr, - - m_is_IO_addr_addr, - m_is_IO_addr, - - m_is_near_mem_IO_addr_addr, - m_is_near_mem_IO_addr, - - m_pc_reset_value, - - m_mtvec_reset_value, - - m_nmivec_reset_value); - input CLK; - input RST_N; - - // value method m_near_mem_io_addr_base - output [63 : 0] m_near_mem_io_addr_base; - - // value method m_near_mem_io_addr_size - output [63 : 0] m_near_mem_io_addr_size; - - // value method m_near_mem_io_addr_lim - output [63 : 0] m_near_mem_io_addr_lim; - - // value method m_plic_addr_base - output [63 : 0] m_plic_addr_base; - - // value method m_plic_addr_size - output [63 : 0] m_plic_addr_size; - - // value method m_plic_addr_lim - output [63 : 0] m_plic_addr_lim; - - // value method m_uart0_addr_base - output [63 : 0] m_uart0_addr_base; - - // value method m_uart0_addr_size - output [63 : 0] m_uart0_addr_size; - - // value method m_uart0_addr_lim - output [63 : 0] m_uart0_addr_lim; - - // value method m_boot_rom_addr_base - output [63 : 0] m_boot_rom_addr_base; - - // value method m_boot_rom_addr_size - output [63 : 0] m_boot_rom_addr_size; - - // value method m_boot_rom_addr_lim - output [63 : 0] m_boot_rom_addr_lim; - - // value method m_mem0_controller_addr_base - output [63 : 0] m_mem0_controller_addr_base; - - // value method m_mem0_controller_addr_size - output [63 : 0] m_mem0_controller_addr_size; - - // value method m_mem0_controller_addr_lim - output [63 : 0] m_mem0_controller_addr_lim; - - // value method m_tcm_addr_base - output [63 : 0] m_tcm_addr_base; - - // value method m_tcm_addr_size - output [63 : 0] m_tcm_addr_size; - - // value method m_tcm_addr_lim - output [63 : 0] m_tcm_addr_lim; - - // value method m_is_mem_addr - input [63 : 0] m_is_mem_addr_addr; - output m_is_mem_addr; - - // value method m_is_IO_addr - input [63 : 0] m_is_IO_addr_addr; - output m_is_IO_addr; - - // value method m_is_near_mem_IO_addr - input [63 : 0] m_is_near_mem_IO_addr_addr; - output m_is_near_mem_IO_addr; - - // value method m_pc_reset_value - output [63 : 0] m_pc_reset_value; - - // value method m_mtvec_reset_value - output [63 : 0] m_mtvec_reset_value; - - // value method m_nmivec_reset_value - output [63 : 0] m_nmivec_reset_value; - - // signals for module outputs - wire [63 : 0] m_boot_rom_addr_base, - m_boot_rom_addr_lim, - m_boot_rom_addr_size, - m_mem0_controller_addr_base, - m_mem0_controller_addr_lim, - m_mem0_controller_addr_size, - m_mtvec_reset_value, - m_near_mem_io_addr_base, - m_near_mem_io_addr_lim, - m_near_mem_io_addr_size, - m_nmivec_reset_value, - m_pc_reset_value, - m_plic_addr_base, - m_plic_addr_lim, - m_plic_addr_size, - m_tcm_addr_base, - m_tcm_addr_lim, - m_tcm_addr_size, - m_uart0_addr_base, - m_uart0_addr_lim, - m_uart0_addr_size; - wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; - - // value method m_near_mem_io_addr_base - assign m_near_mem_io_addr_base = 64'h0000000002000000 ; - - // value method m_near_mem_io_addr_size - assign m_near_mem_io_addr_size = 64'h000000000000C000 ; - - // value method m_near_mem_io_addr_lim - assign m_near_mem_io_addr_lim = 64'd33603584 ; - - // value method m_plic_addr_base - assign m_plic_addr_base = 64'h000000000C000000 ; - - // value method m_plic_addr_size - assign m_plic_addr_size = 64'h0000000000400000 ; - - // value method m_plic_addr_lim - assign m_plic_addr_lim = 64'd205520896 ; - - // value method m_uart0_addr_base - assign m_uart0_addr_base = 64'h00000000C0000000 ; - - // value method m_uart0_addr_size - assign m_uart0_addr_size = 64'h0000000000000080 ; - - // value method m_uart0_addr_lim - assign m_uart0_addr_lim = 64'h00000000C0000080 ; - - // value method m_boot_rom_addr_base - assign m_boot_rom_addr_base = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_size - assign m_boot_rom_addr_size = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_lim - assign m_boot_rom_addr_lim = 64'd8192 ; - - // value method m_mem0_controller_addr_base - assign m_mem0_controller_addr_base = 64'h0000000080000000 ; - - // value method m_mem0_controller_addr_size - assign m_mem0_controller_addr_size = 64'h0000000010000000 ; - - // value method m_mem0_controller_addr_lim - assign m_mem0_controller_addr_lim = 64'h0000000090000000 ; - - // value method m_tcm_addr_base - assign m_tcm_addr_base = 64'h0 ; - - // value method m_tcm_addr_size - assign m_tcm_addr_size = 64'd0 ; - - // value method m_tcm_addr_lim - assign m_tcm_addr_lim = 64'd0 ; - - // value method m_is_mem_addr - assign m_is_mem_addr = - m_is_mem_addr_addr >= 64'h0000000000001000 && - m_is_mem_addr_addr < 64'd8192 || - m_is_mem_addr_addr >= 64'h0000000080000000 && - m_is_mem_addr_addr < 64'h0000000090000000 ; - - // value method m_is_IO_addr - assign m_is_IO_addr = - m_is_IO_addr_addr >= 64'h0000000002000000 && - m_is_IO_addr_addr < 64'd33603584 || - m_is_IO_addr_addr >= 64'h000000000C000000 && - m_is_IO_addr_addr < 64'd205520896 || - m_is_IO_addr_addr >= 64'h00000000C0000000 && - m_is_IO_addr_addr < 64'h00000000C0000080 ; - - // value method m_is_near_mem_IO_addr - assign m_is_near_mem_IO_addr = - m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 && - m_is_near_mem_IO_addr_addr < 64'd33603584 ; - - // value method m_pc_reset_value - assign m_pc_reset_value = 64'h0000000000001000 ; - - // value method m_mtvec_reset_value - assign m_mtvec_reset_value = 64'h0000000000001000 ; - - // value method m_nmivec_reset_value - assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ; -endmodule // mkSoC_Map - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v deleted file mode 100644 index 42e03763..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v +++ /dev/null @@ -1,2333 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// to_raw_mem_response_put I 256 -// put_from_console_put I 8 reg -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_set_verbosity I 1 -// EN_to_raw_mem_response_put I 1 -// EN_put_from_console_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Top(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [7 : 0] get_to_console_get, status; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_set_verbosity, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule boot_rom - wire [63 : 0] boot_rom$set_addr_map_addr_base, - boot_rom$set_addr_map_addr_lim, - boot_rom$slave_araddr, - boot_rom$slave_awaddr, - boot_rom$slave_rdata, - boot_rom$slave_wdata; - wire [7 : 0] boot_rom$slave_arlen, - boot_rom$slave_awlen, - boot_rom$slave_wstrb; - wire [3 : 0] boot_rom$slave_arcache, - boot_rom$slave_arid, - boot_rom$slave_arqos, - boot_rom$slave_arregion, - boot_rom$slave_awcache, - boot_rom$slave_awid, - boot_rom$slave_awqos, - boot_rom$slave_awregion, - boot_rom$slave_bid, - boot_rom$slave_rid, - boot_rom$slave_wid; - wire [2 : 0] boot_rom$slave_arprot, - boot_rom$slave_arsize, - boot_rom$slave_awprot, - boot_rom$slave_awsize; - wire [1 : 0] boot_rom$slave_arburst, - boot_rom$slave_awburst, - boot_rom$slave_bresp, - boot_rom$slave_rresp; - wire boot_rom$EN_set_addr_map, - boot_rom$slave_arlock, - boot_rom$slave_arready, - boot_rom$slave_arvalid, - boot_rom$slave_awlock, - boot_rom$slave_awready, - boot_rom$slave_awvalid, - boot_rom$slave_bready, - boot_rom$slave_bvalid, - boot_rom$slave_rlast, - boot_rom$slave_rready, - boot_rom$slave_rvalid, - boot_rom$slave_wlast, - boot_rom$slave_wready, - boot_rom$slave_wvalid; - - // ports of submodule boot_rom_axi4_deburster - wire [63 : 0] boot_rom_axi4_deburster$from_master_araddr, - boot_rom_axi4_deburster$from_master_awaddr, - boot_rom_axi4_deburster$from_master_rdata, - boot_rom_axi4_deburster$from_master_wdata, - boot_rom_axi4_deburster$to_slave_araddr, - boot_rom_axi4_deburster$to_slave_awaddr, - boot_rom_axi4_deburster$to_slave_rdata, - boot_rom_axi4_deburster$to_slave_wdata; - wire [7 : 0] boot_rom_axi4_deburster$from_master_arlen, - boot_rom_axi4_deburster$from_master_awlen, - boot_rom_axi4_deburster$from_master_wstrb, - boot_rom_axi4_deburster$to_slave_arlen, - boot_rom_axi4_deburster$to_slave_awlen, - boot_rom_axi4_deburster$to_slave_wstrb; - wire [3 : 0] boot_rom_axi4_deburster$from_master_arcache, - boot_rom_axi4_deburster$from_master_arid, - boot_rom_axi4_deburster$from_master_arqos, - boot_rom_axi4_deburster$from_master_arregion, - boot_rom_axi4_deburster$from_master_awcache, - boot_rom_axi4_deburster$from_master_awid, - boot_rom_axi4_deburster$from_master_awqos, - boot_rom_axi4_deburster$from_master_awregion, - boot_rom_axi4_deburster$from_master_bid, - boot_rom_axi4_deburster$from_master_rid, - boot_rom_axi4_deburster$from_master_wid, - boot_rom_axi4_deburster$to_slave_arcache, - boot_rom_axi4_deburster$to_slave_arid, - boot_rom_axi4_deburster$to_slave_arqos, - boot_rom_axi4_deburster$to_slave_arregion, - boot_rom_axi4_deburster$to_slave_awcache, - boot_rom_axi4_deburster$to_slave_awid, - boot_rom_axi4_deburster$to_slave_awqos, - boot_rom_axi4_deburster$to_slave_awregion, - boot_rom_axi4_deburster$to_slave_bid, - boot_rom_axi4_deburster$to_slave_rid, - boot_rom_axi4_deburster$to_slave_wid; - wire [2 : 0] boot_rom_axi4_deburster$from_master_arprot, - boot_rom_axi4_deburster$from_master_arsize, - boot_rom_axi4_deburster$from_master_awprot, - boot_rom_axi4_deburster$from_master_awsize, - boot_rom_axi4_deburster$to_slave_arprot, - boot_rom_axi4_deburster$to_slave_arsize, - boot_rom_axi4_deburster$to_slave_awprot, - boot_rom_axi4_deburster$to_slave_awsize; - wire [1 : 0] boot_rom_axi4_deburster$from_master_arburst, - boot_rom_axi4_deburster$from_master_awburst, - boot_rom_axi4_deburster$from_master_bresp, - boot_rom_axi4_deburster$from_master_rresp, - boot_rom_axi4_deburster$to_slave_arburst, - boot_rom_axi4_deburster$to_slave_awburst, - boot_rom_axi4_deburster$to_slave_bresp, - boot_rom_axi4_deburster$to_slave_rresp; - wire boot_rom_axi4_deburster$EN_reset, - boot_rom_axi4_deburster$from_master_arlock, - boot_rom_axi4_deburster$from_master_arready, - boot_rom_axi4_deburster$from_master_arvalid, - boot_rom_axi4_deburster$from_master_awlock, - boot_rom_axi4_deburster$from_master_awready, - boot_rom_axi4_deburster$from_master_awvalid, - boot_rom_axi4_deburster$from_master_bready, - boot_rom_axi4_deburster$from_master_bvalid, - boot_rom_axi4_deburster$from_master_rlast, - boot_rom_axi4_deburster$from_master_rready, - boot_rom_axi4_deburster$from_master_rvalid, - boot_rom_axi4_deburster$from_master_wlast, - boot_rom_axi4_deburster$from_master_wready, - boot_rom_axi4_deburster$from_master_wvalid, - boot_rom_axi4_deburster$to_slave_arlock, - boot_rom_axi4_deburster$to_slave_arready, - boot_rom_axi4_deburster$to_slave_arvalid, - boot_rom_axi4_deburster$to_slave_awlock, - boot_rom_axi4_deburster$to_slave_awready, - boot_rom_axi4_deburster$to_slave_awvalid, - boot_rom_axi4_deburster$to_slave_bready, - boot_rom_axi4_deburster$to_slave_bvalid, - boot_rom_axi4_deburster$to_slave_rlast, - boot_rom_axi4_deburster$to_slave_rready, - boot_rom_axi4_deburster$to_slave_rvalid, - boot_rom_axi4_deburster$to_slave_wlast, - boot_rom_axi4_deburster$to_slave_wready, - boot_rom_axi4_deburster$to_slave_wvalid; - - // ports of submodule core - wire [63 : 0] core$cpu_dmem_master_araddr, - core$cpu_dmem_master_awaddr, - core$cpu_dmem_master_rdata, - core$cpu_dmem_master_wdata, - core$cpu_imem_master_araddr, - core$cpu_imem_master_awaddr, - core$cpu_imem_master_rdata, - core$cpu_imem_master_wdata, - core$set_verbosity_logdelay; - wire [7 : 0] core$cpu_dmem_master_arlen, - core$cpu_dmem_master_awlen, - core$cpu_dmem_master_wstrb, - core$cpu_imem_master_arlen, - core$cpu_imem_master_awlen, - core$cpu_imem_master_wstrb; - wire [3 : 0] core$cpu_dmem_master_arcache, - core$cpu_dmem_master_arid, - core$cpu_dmem_master_arqos, - core$cpu_dmem_master_arregion, - core$cpu_dmem_master_awcache, - core$cpu_dmem_master_awid, - core$cpu_dmem_master_awqos, - core$cpu_dmem_master_awregion, - core$cpu_dmem_master_bid, - core$cpu_dmem_master_rid, - core$cpu_dmem_master_wid, - core$cpu_imem_master_arcache, - core$cpu_imem_master_arid, - core$cpu_imem_master_arqos, - core$cpu_imem_master_arregion, - core$cpu_imem_master_awcache, - core$cpu_imem_master_awid, - core$cpu_imem_master_awqos, - core$cpu_imem_master_awregion, - core$cpu_imem_master_bid, - core$cpu_imem_master_rid, - core$cpu_imem_master_wid, - core$set_verbosity_verbosity; - wire [2 : 0] core$cpu_dmem_master_arprot, - core$cpu_dmem_master_arsize, - core$cpu_dmem_master_awprot, - core$cpu_dmem_master_awsize, - core$cpu_imem_master_arprot, - core$cpu_imem_master_arsize, - core$cpu_imem_master_awprot, - core$cpu_imem_master_awsize; - wire [1 : 0] core$cpu_dmem_master_arburst, - core$cpu_dmem_master_awburst, - core$cpu_dmem_master_bresp, - core$cpu_dmem_master_rresp, - core$cpu_imem_master_arburst, - core$cpu_imem_master_awburst, - core$cpu_imem_master_bresp, - core$cpu_imem_master_rresp; - wire core$EN_cpu_reset_server_request_put, - core$EN_cpu_reset_server_response_get, - core$EN_set_verbosity, - core$RDY_cpu_reset_server_request_put, - core$RDY_cpu_reset_server_response_get, - core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - core$cpu_dmem_master_arlock, - core$cpu_dmem_master_arready, - core$cpu_dmem_master_arvalid, - core$cpu_dmem_master_awlock, - core$cpu_dmem_master_awready, - core$cpu_dmem_master_awvalid, - core$cpu_dmem_master_bready, - core$cpu_dmem_master_bvalid, - core$cpu_dmem_master_rlast, - core$cpu_dmem_master_rready, - core$cpu_dmem_master_rvalid, - core$cpu_dmem_master_wlast, - core$cpu_dmem_master_wready, - core$cpu_dmem_master_wvalid, - core$cpu_imem_master_arlock, - core$cpu_imem_master_arready, - core$cpu_imem_master_arvalid, - core$cpu_imem_master_awlock, - core$cpu_imem_master_awready, - core$cpu_imem_master_awvalid, - core$cpu_imem_master_bready, - core$cpu_imem_master_bvalid, - core$cpu_imem_master_rlast, - core$cpu_imem_master_rready, - core$cpu_imem_master_rvalid, - core$cpu_imem_master_wlast, - core$cpu_imem_master_wready, - core$cpu_imem_master_wvalid, - core$cpu_reset_server_request_put, - core$nmi_req_set_not_clear; - - // ports of submodule fabric - wire [63 : 0] fabric$v_from_masters_0_araddr, - fabric$v_from_masters_0_awaddr, - fabric$v_from_masters_0_rdata, - fabric$v_from_masters_0_wdata, - fabric$v_from_masters_1_araddr, - fabric$v_from_masters_1_awaddr, - fabric$v_from_masters_1_rdata, - fabric$v_from_masters_1_wdata, - fabric$v_to_slaves_0_araddr, - fabric$v_to_slaves_0_awaddr, - fabric$v_to_slaves_0_rdata, - fabric$v_to_slaves_0_wdata, - fabric$v_to_slaves_1_araddr, - fabric$v_to_slaves_1_awaddr, - fabric$v_to_slaves_1_rdata, - fabric$v_to_slaves_1_wdata, - fabric$v_to_slaves_2_araddr, - fabric$v_to_slaves_2_awaddr, - fabric$v_to_slaves_2_rdata, - fabric$v_to_slaves_2_wdata; - wire [7 : 0] fabric$v_from_masters_0_arlen, - fabric$v_from_masters_0_awlen, - fabric$v_from_masters_0_wstrb, - fabric$v_from_masters_1_arlen, - fabric$v_from_masters_1_awlen, - fabric$v_from_masters_1_wstrb, - fabric$v_to_slaves_0_arlen, - fabric$v_to_slaves_0_awlen, - fabric$v_to_slaves_0_wstrb, - fabric$v_to_slaves_1_arlen, - fabric$v_to_slaves_1_awlen, - fabric$v_to_slaves_1_wstrb, - fabric$v_to_slaves_2_arlen, - fabric$v_to_slaves_2_awlen, - fabric$v_to_slaves_2_wstrb; - wire [3 : 0] fabric$set_verbosity_verbosity, - fabric$v_from_masters_0_arcache, - fabric$v_from_masters_0_arid, - fabric$v_from_masters_0_arqos, - fabric$v_from_masters_0_arregion, - fabric$v_from_masters_0_awcache, - fabric$v_from_masters_0_awid, - fabric$v_from_masters_0_awqos, - fabric$v_from_masters_0_awregion, - fabric$v_from_masters_0_bid, - fabric$v_from_masters_0_rid, - fabric$v_from_masters_0_wid, - fabric$v_from_masters_1_arcache, - fabric$v_from_masters_1_arid, - fabric$v_from_masters_1_arqos, - fabric$v_from_masters_1_arregion, - fabric$v_from_masters_1_awcache, - fabric$v_from_masters_1_awid, - fabric$v_from_masters_1_awqos, - fabric$v_from_masters_1_awregion, - fabric$v_from_masters_1_bid, - fabric$v_from_masters_1_rid, - fabric$v_from_masters_1_wid, - fabric$v_to_slaves_0_arcache, - fabric$v_to_slaves_0_arid, - fabric$v_to_slaves_0_arqos, - fabric$v_to_slaves_0_arregion, - fabric$v_to_slaves_0_awcache, - fabric$v_to_slaves_0_awid, - fabric$v_to_slaves_0_awqos, - fabric$v_to_slaves_0_awregion, - fabric$v_to_slaves_0_bid, - fabric$v_to_slaves_0_rid, - fabric$v_to_slaves_0_wid, - fabric$v_to_slaves_1_arcache, - fabric$v_to_slaves_1_arid, - fabric$v_to_slaves_1_arqos, - fabric$v_to_slaves_1_arregion, - fabric$v_to_slaves_1_awcache, - fabric$v_to_slaves_1_awid, - fabric$v_to_slaves_1_awqos, - fabric$v_to_slaves_1_awregion, - fabric$v_to_slaves_1_bid, - fabric$v_to_slaves_1_rid, - fabric$v_to_slaves_1_wid, - fabric$v_to_slaves_2_arcache, - fabric$v_to_slaves_2_arid, - fabric$v_to_slaves_2_arqos, - fabric$v_to_slaves_2_arregion, - fabric$v_to_slaves_2_awcache, - fabric$v_to_slaves_2_awid, - fabric$v_to_slaves_2_awqos, - fabric$v_to_slaves_2_awregion, - fabric$v_to_slaves_2_bid, - fabric$v_to_slaves_2_rid, - fabric$v_to_slaves_2_wid; - wire [2 : 0] fabric$v_from_masters_0_arprot, - fabric$v_from_masters_0_arsize, - fabric$v_from_masters_0_awprot, - fabric$v_from_masters_0_awsize, - fabric$v_from_masters_1_arprot, - fabric$v_from_masters_1_arsize, - fabric$v_from_masters_1_awprot, - fabric$v_from_masters_1_awsize, - fabric$v_to_slaves_0_arprot, - fabric$v_to_slaves_0_arsize, - fabric$v_to_slaves_0_awprot, - fabric$v_to_slaves_0_awsize, - fabric$v_to_slaves_1_arprot, - fabric$v_to_slaves_1_arsize, - fabric$v_to_slaves_1_awprot, - fabric$v_to_slaves_1_awsize, - fabric$v_to_slaves_2_arprot, - fabric$v_to_slaves_2_arsize, - fabric$v_to_slaves_2_awprot, - fabric$v_to_slaves_2_awsize; - wire [1 : 0] fabric$v_from_masters_0_arburst, - fabric$v_from_masters_0_awburst, - fabric$v_from_masters_0_bresp, - fabric$v_from_masters_0_rresp, - fabric$v_from_masters_1_arburst, - fabric$v_from_masters_1_awburst, - fabric$v_from_masters_1_bresp, - fabric$v_from_masters_1_rresp, - fabric$v_to_slaves_0_arburst, - fabric$v_to_slaves_0_awburst, - fabric$v_to_slaves_0_bresp, - fabric$v_to_slaves_0_rresp, - fabric$v_to_slaves_1_arburst, - fabric$v_to_slaves_1_awburst, - fabric$v_to_slaves_1_bresp, - fabric$v_to_slaves_1_rresp, - fabric$v_to_slaves_2_arburst, - fabric$v_to_slaves_2_awburst, - fabric$v_to_slaves_2_bresp, - fabric$v_to_slaves_2_rresp; - wire fabric$EN_reset, - fabric$EN_set_verbosity, - fabric$RDY_reset, - fabric$v_from_masters_0_arlock, - fabric$v_from_masters_0_arready, - fabric$v_from_masters_0_arvalid, - fabric$v_from_masters_0_awlock, - fabric$v_from_masters_0_awready, - fabric$v_from_masters_0_awvalid, - fabric$v_from_masters_0_bready, - fabric$v_from_masters_0_bvalid, - fabric$v_from_masters_0_rlast, - fabric$v_from_masters_0_rready, - fabric$v_from_masters_0_rvalid, - fabric$v_from_masters_0_wlast, - fabric$v_from_masters_0_wready, - fabric$v_from_masters_0_wvalid, - fabric$v_from_masters_1_arlock, - fabric$v_from_masters_1_arready, - fabric$v_from_masters_1_arvalid, - fabric$v_from_masters_1_awlock, - fabric$v_from_masters_1_awready, - fabric$v_from_masters_1_awvalid, - fabric$v_from_masters_1_bready, - fabric$v_from_masters_1_bvalid, - fabric$v_from_masters_1_rlast, - fabric$v_from_masters_1_rready, - fabric$v_from_masters_1_rvalid, - fabric$v_from_masters_1_wlast, - fabric$v_from_masters_1_wready, - fabric$v_from_masters_1_wvalid, - fabric$v_to_slaves_0_arlock, - fabric$v_to_slaves_0_arready, - fabric$v_to_slaves_0_arvalid, - fabric$v_to_slaves_0_awlock, - fabric$v_to_slaves_0_awready, - fabric$v_to_slaves_0_awvalid, - fabric$v_to_slaves_0_bready, - fabric$v_to_slaves_0_bvalid, - fabric$v_to_slaves_0_rlast, - fabric$v_to_slaves_0_rready, - fabric$v_to_slaves_0_rvalid, - fabric$v_to_slaves_0_wlast, - fabric$v_to_slaves_0_wready, - fabric$v_to_slaves_0_wvalid, - fabric$v_to_slaves_1_arlock, - fabric$v_to_slaves_1_arready, - fabric$v_to_slaves_1_arvalid, - fabric$v_to_slaves_1_awlock, - fabric$v_to_slaves_1_awready, - fabric$v_to_slaves_1_awvalid, - fabric$v_to_slaves_1_bready, - fabric$v_to_slaves_1_bvalid, - fabric$v_to_slaves_1_rlast, - fabric$v_to_slaves_1_rready, - fabric$v_to_slaves_1_rvalid, - fabric$v_to_slaves_1_wlast, - fabric$v_to_slaves_1_wready, - fabric$v_to_slaves_1_wvalid, - fabric$v_to_slaves_2_arlock, - fabric$v_to_slaves_2_arready, - fabric$v_to_slaves_2_arvalid, - fabric$v_to_slaves_2_awlock, - fabric$v_to_slaves_2_awready, - fabric$v_to_slaves_2_awvalid, - fabric$v_to_slaves_2_bready, - fabric$v_to_slaves_2_bvalid, - fabric$v_to_slaves_2_rlast, - fabric$v_to_slaves_2_rready, - fabric$v_to_slaves_2_rvalid, - fabric$v_to_slaves_2_wlast, - fabric$v_to_slaves_2_wready, - fabric$v_to_slaves_2_wvalid; - - // ports of submodule mem0_controller - wire [352 : 0] mem0_controller$to_raw_mem_request_get; - wire [255 : 0] mem0_controller$to_raw_mem_response_put; - wire [63 : 0] mem0_controller$set_addr_map_addr_base, - mem0_controller$set_addr_map_addr_lim, - mem0_controller$set_watch_tohost_tohost_addr, - mem0_controller$slave_araddr, - mem0_controller$slave_awaddr, - mem0_controller$slave_rdata, - mem0_controller$slave_wdata; - wire [7 : 0] mem0_controller$slave_arlen, - mem0_controller$slave_awlen, - mem0_controller$slave_wstrb, - mem0_controller$status; - wire [3 : 0] mem0_controller$slave_arcache, - mem0_controller$slave_arid, - mem0_controller$slave_arqos, - mem0_controller$slave_arregion, - mem0_controller$slave_awcache, - mem0_controller$slave_awid, - mem0_controller$slave_awqos, - mem0_controller$slave_awregion, - mem0_controller$slave_bid, - mem0_controller$slave_rid, - mem0_controller$slave_wid; - wire [2 : 0] mem0_controller$slave_arprot, - mem0_controller$slave_arsize, - mem0_controller$slave_awprot, - mem0_controller$slave_awsize; - wire [1 : 0] mem0_controller$slave_arburst, - mem0_controller$slave_awburst, - mem0_controller$slave_bresp, - mem0_controller$slave_rresp; - wire mem0_controller$EN_server_reset_request_put, - mem0_controller$EN_server_reset_response_get, - mem0_controller$EN_set_addr_map, - mem0_controller$EN_set_watch_tohost, - mem0_controller$EN_to_raw_mem_request_get, - mem0_controller$EN_to_raw_mem_response_put, - mem0_controller$RDY_server_reset_request_put, - mem0_controller$RDY_server_reset_response_get, - mem0_controller$RDY_set_addr_map, - mem0_controller$RDY_to_raw_mem_request_get, - mem0_controller$RDY_to_raw_mem_response_put, - mem0_controller$set_watch_tohost_watch_tohost, - mem0_controller$slave_arlock, - mem0_controller$slave_arready, - mem0_controller$slave_arvalid, - mem0_controller$slave_awlock, - mem0_controller$slave_awready, - mem0_controller$slave_awvalid, - mem0_controller$slave_bready, - mem0_controller$slave_bvalid, - mem0_controller$slave_rlast, - mem0_controller$slave_rready, - mem0_controller$slave_rvalid, - mem0_controller$slave_wlast, - mem0_controller$slave_wready, - mem0_controller$slave_wvalid; - - // ports of submodule mem0_controller_axi4_deburster - wire [63 : 0] mem0_controller_axi4_deburster$from_master_araddr, - mem0_controller_axi4_deburster$from_master_awaddr, - mem0_controller_axi4_deburster$from_master_rdata, - mem0_controller_axi4_deburster$from_master_wdata, - mem0_controller_axi4_deburster$to_slave_araddr, - mem0_controller_axi4_deburster$to_slave_awaddr, - mem0_controller_axi4_deburster$to_slave_rdata, - mem0_controller_axi4_deburster$to_slave_wdata; - wire [7 : 0] mem0_controller_axi4_deburster$from_master_arlen, - mem0_controller_axi4_deburster$from_master_awlen, - mem0_controller_axi4_deburster$from_master_wstrb, - mem0_controller_axi4_deburster$to_slave_arlen, - mem0_controller_axi4_deburster$to_slave_awlen, - mem0_controller_axi4_deburster$to_slave_wstrb; - wire [3 : 0] mem0_controller_axi4_deburster$from_master_arcache, - mem0_controller_axi4_deburster$from_master_arid, - mem0_controller_axi4_deburster$from_master_arqos, - mem0_controller_axi4_deburster$from_master_arregion, - mem0_controller_axi4_deburster$from_master_awcache, - mem0_controller_axi4_deburster$from_master_awid, - mem0_controller_axi4_deburster$from_master_awqos, - mem0_controller_axi4_deburster$from_master_awregion, - mem0_controller_axi4_deburster$from_master_bid, - mem0_controller_axi4_deburster$from_master_rid, - mem0_controller_axi4_deburster$from_master_wid, - mem0_controller_axi4_deburster$to_slave_arcache, - mem0_controller_axi4_deburster$to_slave_arid, - mem0_controller_axi4_deburster$to_slave_arqos, - mem0_controller_axi4_deburster$to_slave_arregion, - mem0_controller_axi4_deburster$to_slave_awcache, - mem0_controller_axi4_deburster$to_slave_awid, - mem0_controller_axi4_deburster$to_slave_awqos, - mem0_controller_axi4_deburster$to_slave_awregion, - mem0_controller_axi4_deburster$to_slave_bid, - mem0_controller_axi4_deburster$to_slave_rid, - mem0_controller_axi4_deburster$to_slave_wid; - wire [2 : 0] mem0_controller_axi4_deburster$from_master_arprot, - mem0_controller_axi4_deburster$from_master_arsize, - mem0_controller_axi4_deburster$from_master_awprot, - mem0_controller_axi4_deburster$from_master_awsize, - mem0_controller_axi4_deburster$to_slave_arprot, - mem0_controller_axi4_deburster$to_slave_arsize, - mem0_controller_axi4_deburster$to_slave_awprot, - mem0_controller_axi4_deburster$to_slave_awsize; - wire [1 : 0] mem0_controller_axi4_deburster$from_master_arburst, - mem0_controller_axi4_deburster$from_master_awburst, - mem0_controller_axi4_deburster$from_master_bresp, - mem0_controller_axi4_deburster$from_master_rresp, - mem0_controller_axi4_deburster$to_slave_arburst, - mem0_controller_axi4_deburster$to_slave_awburst, - mem0_controller_axi4_deburster$to_slave_bresp, - mem0_controller_axi4_deburster$to_slave_rresp; - wire mem0_controller_axi4_deburster$EN_reset, - mem0_controller_axi4_deburster$from_master_arlock, - mem0_controller_axi4_deburster$from_master_arready, - mem0_controller_axi4_deburster$from_master_arvalid, - mem0_controller_axi4_deburster$from_master_awlock, - mem0_controller_axi4_deburster$from_master_awready, - mem0_controller_axi4_deburster$from_master_awvalid, - mem0_controller_axi4_deburster$from_master_bready, - mem0_controller_axi4_deburster$from_master_bvalid, - mem0_controller_axi4_deburster$from_master_rlast, - mem0_controller_axi4_deburster$from_master_rready, - mem0_controller_axi4_deburster$from_master_rvalid, - mem0_controller_axi4_deburster$from_master_wlast, - mem0_controller_axi4_deburster$from_master_wready, - mem0_controller_axi4_deburster$from_master_wvalid, - mem0_controller_axi4_deburster$to_slave_arlock, - mem0_controller_axi4_deburster$to_slave_arready, - mem0_controller_axi4_deburster$to_slave_arvalid, - mem0_controller_axi4_deburster$to_slave_awlock, - mem0_controller_axi4_deburster$to_slave_awready, - mem0_controller_axi4_deburster$to_slave_awvalid, - mem0_controller_axi4_deburster$to_slave_bready, - mem0_controller_axi4_deburster$to_slave_bvalid, - mem0_controller_axi4_deburster$to_slave_rlast, - mem0_controller_axi4_deburster$to_slave_rready, - mem0_controller_axi4_deburster$to_slave_rvalid, - mem0_controller_axi4_deburster$to_slave_wlast, - mem0_controller_axi4_deburster$to_slave_wready, - mem0_controller_axi4_deburster$to_slave_wvalid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // ports of submodule uart0 - wire [63 : 0] uart0$set_addr_map_addr_base, - uart0$set_addr_map_addr_lim, - uart0$slave_araddr, - uart0$slave_awaddr, - uart0$slave_rdata, - uart0$slave_wdata; - wire [7 : 0] uart0$get_to_console_get, - uart0$put_from_console_put, - uart0$slave_arlen, - uart0$slave_awlen, - uart0$slave_wstrb; - wire [3 : 0] uart0$slave_arcache, - uart0$slave_arid, - uart0$slave_arqos, - uart0$slave_arregion, - uart0$slave_awcache, - uart0$slave_awid, - uart0$slave_awqos, - uart0$slave_awregion, - uart0$slave_bid, - uart0$slave_rid, - uart0$slave_wid; - wire [2 : 0] uart0$slave_arprot, - uart0$slave_arsize, - uart0$slave_awprot, - uart0$slave_awsize; - wire [1 : 0] uart0$slave_arburst, - uart0$slave_awburst, - uart0$slave_bresp, - uart0$slave_rresp; - wire uart0$EN_get_to_console_get, - uart0$EN_put_from_console_put, - uart0$EN_server_reset_request_put, - uart0$EN_server_reset_response_get, - uart0$EN_set_addr_map, - uart0$RDY_get_to_console_get, - uart0$RDY_put_from_console_put, - uart0$RDY_server_reset_request_put, - uart0$RDY_server_reset_response_get, - uart0$intr, - uart0$slave_arlock, - uart0$slave_arready, - uart0$slave_arvalid, - uart0$slave_awlock, - uart0$slave_awready, - uart0$slave_awvalid, - uart0$slave_bready, - uart0$slave_bvalid, - uart0$slave_rlast, - uart0$slave_rready, - uart0$slave_rvalid, - uart0$slave_wlast, - uart0$slave_wready, - uart0$slave_wvalid; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_connect_external_interrupt_requests, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_addr_channel_5, - CAN_FIRE_RL_rl_rd_addr_channel_6, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, - CAN_FIRE_RL_rl_rd_data_channel_5, - CAN_FIRE_RL_rl_rd_data_channel_6, - CAN_FIRE_RL_rl_reset_complete_initial, - CAN_FIRE_RL_rl_reset_start_initial, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_addr_channel_5, - CAN_FIRE_RL_rl_wr_addr_channel_6, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_data_channel_5, - CAN_FIRE_RL_rl_wr_data_channel_6, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, - CAN_FIRE_RL_rl_wr_response_channel_5, - CAN_FIRE_RL_rl_wr_response_channel_6, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_set_verbosity, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_connect_external_interrupt_requests, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_addr_channel_5, - WILL_FIRE_RL_rl_rd_addr_channel_6, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, - WILL_FIRE_RL_rl_rd_data_channel_5, - WILL_FIRE_RL_rl_rd_data_channel_6, - WILL_FIRE_RL_rl_reset_complete_initial, - WILL_FIRE_RL_rl_reset_start_initial, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_addr_channel_5, - WILL_FIRE_RL_rl_wr_addr_channel_6, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_data_channel_5, - WILL_FIRE_RL_rl_wr_data_channel_6, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, - WILL_FIRE_RL_rl_wr_response_channel_5, - WILL_FIRE_RL_rl_wr_response_channel_6, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_set_verbosity, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h11286; - reg [31 : 0] v__h11556; - reg [31 : 0] v__h11280; - reg [31 : 0] v__h11550; - // synopsys translate_on - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = mem0_controller$to_raw_mem_request_get ; - assign RDY_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign CAN_FIRE_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign CAN_FIRE_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // actionvalue method get_to_console_get - assign get_to_console_get = uart0$get_to_console_get ; - assign RDY_get_to_console_get = uart0$RDY_get_to_console_get ; - assign CAN_FIRE_get_to_console_get = uart0$RDY_get_to_console_get ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = uart0$RDY_put_from_console_put ; - assign CAN_FIRE_put_from_console_put = uart0$RDY_put_from_console_put ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method status - assign status = mem0_controller$status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule boot_rom - mkBoot_ROM boot_rom(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(boot_rom$set_addr_map_addr_base), - .set_addr_map_addr_lim(boot_rom$set_addr_map_addr_lim), - .slave_araddr(boot_rom$slave_araddr), - .slave_arburst(boot_rom$slave_arburst), - .slave_arcache(boot_rom$slave_arcache), - .slave_arid(boot_rom$slave_arid), - .slave_arlen(boot_rom$slave_arlen), - .slave_arlock(boot_rom$slave_arlock), - .slave_arprot(boot_rom$slave_arprot), - .slave_arqos(boot_rom$slave_arqos), - .slave_arregion(boot_rom$slave_arregion), - .slave_arsize(boot_rom$slave_arsize), - .slave_arvalid(boot_rom$slave_arvalid), - .slave_awaddr(boot_rom$slave_awaddr), - .slave_awburst(boot_rom$slave_awburst), - .slave_awcache(boot_rom$slave_awcache), - .slave_awid(boot_rom$slave_awid), - .slave_awlen(boot_rom$slave_awlen), - .slave_awlock(boot_rom$slave_awlock), - .slave_awprot(boot_rom$slave_awprot), - .slave_awqos(boot_rom$slave_awqos), - .slave_awregion(boot_rom$slave_awregion), - .slave_awsize(boot_rom$slave_awsize), - .slave_awvalid(boot_rom$slave_awvalid), - .slave_bready(boot_rom$slave_bready), - .slave_rready(boot_rom$slave_rready), - .slave_wdata(boot_rom$slave_wdata), - .slave_wid(boot_rom$slave_wid), - .slave_wlast(boot_rom$slave_wlast), - .slave_wstrb(boot_rom$slave_wstrb), - .slave_wvalid(boot_rom$slave_wvalid), - .EN_set_addr_map(boot_rom$EN_set_addr_map), - .RDY_set_addr_map(), - .slave_awready(boot_rom$slave_awready), - .slave_wready(boot_rom$slave_wready), - .slave_bvalid(boot_rom$slave_bvalid), - .slave_bid(boot_rom$slave_bid), - .slave_bresp(boot_rom$slave_bresp), - .slave_arready(boot_rom$slave_arready), - .slave_rvalid(boot_rom$slave_rvalid), - .slave_rid(boot_rom$slave_rid), - .slave_rdata(boot_rom$slave_rdata), - .slave_rresp(boot_rom$slave_rresp), - .slave_rlast(boot_rom$slave_rlast)); - - // submodule boot_rom_axi4_deburster - mkAXI4_Deburster_A boot_rom_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(boot_rom_axi4_deburster$from_master_araddr), - .from_master_arburst(boot_rom_axi4_deburster$from_master_arburst), - .from_master_arcache(boot_rom_axi4_deburster$from_master_arcache), - .from_master_arid(boot_rom_axi4_deburster$from_master_arid), - .from_master_arlen(boot_rom_axi4_deburster$from_master_arlen), - .from_master_arlock(boot_rom_axi4_deburster$from_master_arlock), - .from_master_arprot(boot_rom_axi4_deburster$from_master_arprot), - .from_master_arqos(boot_rom_axi4_deburster$from_master_arqos), - .from_master_arregion(boot_rom_axi4_deburster$from_master_arregion), - .from_master_arsize(boot_rom_axi4_deburster$from_master_arsize), - .from_master_arvalid(boot_rom_axi4_deburster$from_master_arvalid), - .from_master_awaddr(boot_rom_axi4_deburster$from_master_awaddr), - .from_master_awburst(boot_rom_axi4_deburster$from_master_awburst), - .from_master_awcache(boot_rom_axi4_deburster$from_master_awcache), - .from_master_awid(boot_rom_axi4_deburster$from_master_awid), - .from_master_awlen(boot_rom_axi4_deburster$from_master_awlen), - .from_master_awlock(boot_rom_axi4_deburster$from_master_awlock), - .from_master_awprot(boot_rom_axi4_deburster$from_master_awprot), - .from_master_awqos(boot_rom_axi4_deburster$from_master_awqos), - .from_master_awregion(boot_rom_axi4_deburster$from_master_awregion), - .from_master_awsize(boot_rom_axi4_deburster$from_master_awsize), - .from_master_awvalid(boot_rom_axi4_deburster$from_master_awvalid), - .from_master_bready(boot_rom_axi4_deburster$from_master_bready), - .from_master_rready(boot_rom_axi4_deburster$from_master_rready), - .from_master_wdata(boot_rom_axi4_deburster$from_master_wdata), - .from_master_wid(boot_rom_axi4_deburster$from_master_wid), - .from_master_wlast(boot_rom_axi4_deburster$from_master_wlast), - .from_master_wstrb(boot_rom_axi4_deburster$from_master_wstrb), - .from_master_wvalid(boot_rom_axi4_deburster$from_master_wvalid), - .to_slave_arready(boot_rom_axi4_deburster$to_slave_arready), - .to_slave_awready(boot_rom_axi4_deburster$to_slave_awready), - .to_slave_bid(boot_rom_axi4_deburster$to_slave_bid), - .to_slave_bresp(boot_rom_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(boot_rom_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(boot_rom_axi4_deburster$to_slave_rdata), - .to_slave_rid(boot_rom_axi4_deburster$to_slave_rid), - .to_slave_rlast(boot_rom_axi4_deburster$to_slave_rlast), - .to_slave_rresp(boot_rom_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(boot_rom_axi4_deburster$to_slave_rvalid), - .to_slave_wready(boot_rom_axi4_deburster$to_slave_wready), - .EN_reset(boot_rom_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(boot_rom_axi4_deburster$from_master_awready), - .from_master_wready(boot_rom_axi4_deburster$from_master_wready), - .from_master_bvalid(boot_rom_axi4_deburster$from_master_bvalid), - .from_master_bid(boot_rom_axi4_deburster$from_master_bid), - .from_master_bresp(boot_rom_axi4_deburster$from_master_bresp), - .from_master_arready(boot_rom_axi4_deburster$from_master_arready), - .from_master_rvalid(boot_rom_axi4_deburster$from_master_rvalid), - .from_master_rid(boot_rom_axi4_deburster$from_master_rid), - .from_master_rdata(boot_rom_axi4_deburster$from_master_rdata), - .from_master_rresp(boot_rom_axi4_deburster$from_master_rresp), - .from_master_rlast(boot_rom_axi4_deburster$from_master_rlast), - .to_slave_awvalid(boot_rom_axi4_deburster$to_slave_awvalid), - .to_slave_awid(boot_rom_axi4_deburster$to_slave_awid), - .to_slave_awaddr(boot_rom_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(boot_rom_axi4_deburster$to_slave_awlen), - .to_slave_awsize(boot_rom_axi4_deburster$to_slave_awsize), - .to_slave_awburst(boot_rom_axi4_deburster$to_slave_awburst), - .to_slave_awlock(boot_rom_axi4_deburster$to_slave_awlock), - .to_slave_awcache(boot_rom_axi4_deburster$to_slave_awcache), - .to_slave_awprot(boot_rom_axi4_deburster$to_slave_awprot), - .to_slave_awqos(boot_rom_axi4_deburster$to_slave_awqos), - .to_slave_awregion(boot_rom_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(boot_rom_axi4_deburster$to_slave_wvalid), - .to_slave_wid(boot_rom_axi4_deburster$to_slave_wid), - .to_slave_wdata(boot_rom_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(boot_rom_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(boot_rom_axi4_deburster$to_slave_wlast), - .to_slave_bready(boot_rom_axi4_deburster$to_slave_bready), - .to_slave_arvalid(boot_rom_axi4_deburster$to_slave_arvalid), - .to_slave_arid(boot_rom_axi4_deburster$to_slave_arid), - .to_slave_araddr(boot_rom_axi4_deburster$to_slave_araddr), - .to_slave_arlen(boot_rom_axi4_deburster$to_slave_arlen), - .to_slave_arsize(boot_rom_axi4_deburster$to_slave_arsize), - .to_slave_arburst(boot_rom_axi4_deburster$to_slave_arburst), - .to_slave_arlock(boot_rom_axi4_deburster$to_slave_arlock), - .to_slave_arcache(boot_rom_axi4_deburster$to_slave_arcache), - .to_slave_arprot(boot_rom_axi4_deburster$to_slave_arprot), - .to_slave_arqos(boot_rom_axi4_deburster$to_slave_arqos), - .to_slave_arregion(boot_rom_axi4_deburster$to_slave_arregion), - .to_slave_rready(boot_rom_axi4_deburster$to_slave_rready)); - - // submodule core - mkCore core(.CLK(CLK), - .RST_N(RST_N), - .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_12_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_13_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_14_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_15_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_1_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_2_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_3_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_4_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_5_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_6_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_7_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_8_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_9_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear), - .cpu_dmem_master_arready(core$cpu_dmem_master_arready), - .cpu_dmem_master_awready(core$cpu_dmem_master_awready), - .cpu_dmem_master_bid(core$cpu_dmem_master_bid), - .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), - .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata), - .cpu_dmem_master_rid(core$cpu_dmem_master_rid), - .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast), - .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), - .cpu_dmem_master_wready(core$cpu_dmem_master_wready), - .cpu_imem_master_arready(core$cpu_imem_master_arready), - .cpu_imem_master_awready(core$cpu_imem_master_awready), - .cpu_imem_master_bid(core$cpu_imem_master_bid), - .cpu_imem_master_bresp(core$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), - .cpu_imem_master_rdata(core$cpu_imem_master_rdata), - .cpu_imem_master_rid(core$cpu_imem_master_rid), - .cpu_imem_master_rlast(core$cpu_imem_master_rlast), - .cpu_imem_master_rresp(core$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), - .cpu_imem_master_wready(core$cpu_imem_master_wready), - .cpu_reset_server_request_put(core$cpu_reset_server_request_put), - .nmi_req_set_not_clear(core$nmi_req_set_not_clear), - .set_verbosity_logdelay(core$set_verbosity_logdelay), - .set_verbosity_verbosity(core$set_verbosity_verbosity), - .EN_set_verbosity(core$EN_set_verbosity), - .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get), - .RDY_set_verbosity(), - .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put), - .cpu_reset_server_response_get(), - .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), - .cpu_imem_master_awid(core$cpu_imem_master_awid), - .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr), - .cpu_imem_master_awlen(core$cpu_imem_master_awlen), - .cpu_imem_master_awsize(core$cpu_imem_master_awsize), - .cpu_imem_master_awburst(core$cpu_imem_master_awburst), - .cpu_imem_master_awlock(core$cpu_imem_master_awlock), - .cpu_imem_master_awcache(core$cpu_imem_master_awcache), - .cpu_imem_master_awprot(core$cpu_imem_master_awprot), - .cpu_imem_master_awqos(core$cpu_imem_master_awqos), - .cpu_imem_master_awregion(core$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), - .cpu_imem_master_wid(core$cpu_imem_master_wid), - .cpu_imem_master_wdata(core$cpu_imem_master_wdata), - .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb), - .cpu_imem_master_wlast(core$cpu_imem_master_wlast), - .cpu_imem_master_bready(core$cpu_imem_master_bready), - .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), - .cpu_imem_master_arid(core$cpu_imem_master_arid), - .cpu_imem_master_araddr(core$cpu_imem_master_araddr), - .cpu_imem_master_arlen(core$cpu_imem_master_arlen), - .cpu_imem_master_arsize(core$cpu_imem_master_arsize), - .cpu_imem_master_arburst(core$cpu_imem_master_arburst), - .cpu_imem_master_arlock(core$cpu_imem_master_arlock), - .cpu_imem_master_arcache(core$cpu_imem_master_arcache), - .cpu_imem_master_arprot(core$cpu_imem_master_arprot), - .cpu_imem_master_arqos(core$cpu_imem_master_arqos), - .cpu_imem_master_arregion(core$cpu_imem_master_arregion), - .cpu_imem_master_rready(core$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), - .cpu_dmem_master_awid(core$cpu_dmem_master_awid), - .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr), - .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen), - .cpu_dmem_master_awsize(core$cpu_dmem_master_awsize), - .cpu_dmem_master_awburst(core$cpu_dmem_master_awburst), - .cpu_dmem_master_awlock(core$cpu_dmem_master_awlock), - .cpu_dmem_master_awcache(core$cpu_dmem_master_awcache), - .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot), - .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos), - .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(core$cpu_dmem_master_wid), - .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata), - .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb), - .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast), - .cpu_dmem_master_bready(core$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), - .cpu_dmem_master_arid(core$cpu_dmem_master_arid), - .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr), - .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen), - .cpu_dmem_master_arsize(core$cpu_dmem_master_arsize), - .cpu_dmem_master_arburst(core$cpu_dmem_master_arburst), - .cpu_dmem_master_arlock(core$cpu_dmem_master_arlock), - .cpu_dmem_master_arcache(core$cpu_dmem_master_arcache), - .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot), - .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos), - .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion), - .cpu_dmem_master_rready(core$cpu_dmem_master_rready)); - - // submodule fabric - mkFabric_AXI4 fabric(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric$v_to_slaves_2_wready), - .EN_reset(fabric$EN_reset), - .EN_set_verbosity(fabric$EN_set_verbosity), - .RDY_reset(fabric$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric$v_to_slaves_2_rready)); - - // submodule mem0_controller - mkMem_Controller mem0_controller(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(mem0_controller$set_addr_map_addr_base), - .set_addr_map_addr_lim(mem0_controller$set_addr_map_addr_lim), - .set_watch_tohost_tohost_addr(mem0_controller$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(mem0_controller$set_watch_tohost_watch_tohost), - .slave_araddr(mem0_controller$slave_araddr), - .slave_arburst(mem0_controller$slave_arburst), - .slave_arcache(mem0_controller$slave_arcache), - .slave_arid(mem0_controller$slave_arid), - .slave_arlen(mem0_controller$slave_arlen), - .slave_arlock(mem0_controller$slave_arlock), - .slave_arprot(mem0_controller$slave_arprot), - .slave_arqos(mem0_controller$slave_arqos), - .slave_arregion(mem0_controller$slave_arregion), - .slave_arsize(mem0_controller$slave_arsize), - .slave_arvalid(mem0_controller$slave_arvalid), - .slave_awaddr(mem0_controller$slave_awaddr), - .slave_awburst(mem0_controller$slave_awburst), - .slave_awcache(mem0_controller$slave_awcache), - .slave_awid(mem0_controller$slave_awid), - .slave_awlen(mem0_controller$slave_awlen), - .slave_awlock(mem0_controller$slave_awlock), - .slave_awprot(mem0_controller$slave_awprot), - .slave_awqos(mem0_controller$slave_awqos), - .slave_awregion(mem0_controller$slave_awregion), - .slave_awsize(mem0_controller$slave_awsize), - .slave_awvalid(mem0_controller$slave_awvalid), - .slave_bready(mem0_controller$slave_bready), - .slave_rready(mem0_controller$slave_rready), - .slave_wdata(mem0_controller$slave_wdata), - .slave_wid(mem0_controller$slave_wid), - .slave_wlast(mem0_controller$slave_wlast), - .slave_wstrb(mem0_controller$slave_wstrb), - .slave_wvalid(mem0_controller$slave_wvalid), - .to_raw_mem_response_put(mem0_controller$to_raw_mem_response_put), - .EN_server_reset_request_put(mem0_controller$EN_server_reset_request_put), - .EN_server_reset_response_get(mem0_controller$EN_server_reset_response_get), - .EN_set_addr_map(mem0_controller$EN_set_addr_map), - .EN_to_raw_mem_request_get(mem0_controller$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(mem0_controller$EN_to_raw_mem_response_put), - .EN_set_watch_tohost(mem0_controller$EN_set_watch_tohost), - .RDY_server_reset_request_put(mem0_controller$RDY_server_reset_request_put), - .RDY_server_reset_response_get(mem0_controller$RDY_server_reset_response_get), - .RDY_set_addr_map(mem0_controller$RDY_set_addr_map), - .slave_awready(mem0_controller$slave_awready), - .slave_wready(mem0_controller$slave_wready), - .slave_bvalid(mem0_controller$slave_bvalid), - .slave_bid(mem0_controller$slave_bid), - .slave_bresp(mem0_controller$slave_bresp), - .slave_arready(mem0_controller$slave_arready), - .slave_rvalid(mem0_controller$slave_rvalid), - .slave_rid(mem0_controller$slave_rid), - .slave_rdata(mem0_controller$slave_rdata), - .slave_rresp(mem0_controller$slave_rresp), - .slave_rlast(mem0_controller$slave_rlast), - .to_raw_mem_request_get(mem0_controller$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(mem0_controller$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(mem0_controller$RDY_to_raw_mem_response_put), - .status(mem0_controller$status), - .RDY_set_watch_tohost()); - - // submodule mem0_controller_axi4_deburster - mkAXI4_Deburster_A mem0_controller_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(mem0_controller_axi4_deburster$from_master_araddr), - .from_master_arburst(mem0_controller_axi4_deburster$from_master_arburst), - .from_master_arcache(mem0_controller_axi4_deburster$from_master_arcache), - .from_master_arid(mem0_controller_axi4_deburster$from_master_arid), - .from_master_arlen(mem0_controller_axi4_deburster$from_master_arlen), - .from_master_arlock(mem0_controller_axi4_deburster$from_master_arlock), - .from_master_arprot(mem0_controller_axi4_deburster$from_master_arprot), - .from_master_arqos(mem0_controller_axi4_deburster$from_master_arqos), - .from_master_arregion(mem0_controller_axi4_deburster$from_master_arregion), - .from_master_arsize(mem0_controller_axi4_deburster$from_master_arsize), - .from_master_arvalid(mem0_controller_axi4_deburster$from_master_arvalid), - .from_master_awaddr(mem0_controller_axi4_deburster$from_master_awaddr), - .from_master_awburst(mem0_controller_axi4_deburster$from_master_awburst), - .from_master_awcache(mem0_controller_axi4_deburster$from_master_awcache), - .from_master_awid(mem0_controller_axi4_deburster$from_master_awid), - .from_master_awlen(mem0_controller_axi4_deburster$from_master_awlen), - .from_master_awlock(mem0_controller_axi4_deburster$from_master_awlock), - .from_master_awprot(mem0_controller_axi4_deburster$from_master_awprot), - .from_master_awqos(mem0_controller_axi4_deburster$from_master_awqos), - .from_master_awregion(mem0_controller_axi4_deburster$from_master_awregion), - .from_master_awsize(mem0_controller_axi4_deburster$from_master_awsize), - .from_master_awvalid(mem0_controller_axi4_deburster$from_master_awvalid), - .from_master_bready(mem0_controller_axi4_deburster$from_master_bready), - .from_master_rready(mem0_controller_axi4_deburster$from_master_rready), - .from_master_wdata(mem0_controller_axi4_deburster$from_master_wdata), - .from_master_wid(mem0_controller_axi4_deburster$from_master_wid), - .from_master_wlast(mem0_controller_axi4_deburster$from_master_wlast), - .from_master_wstrb(mem0_controller_axi4_deburster$from_master_wstrb), - .from_master_wvalid(mem0_controller_axi4_deburster$from_master_wvalid), - .to_slave_arready(mem0_controller_axi4_deburster$to_slave_arready), - .to_slave_awready(mem0_controller_axi4_deburster$to_slave_awready), - .to_slave_bid(mem0_controller_axi4_deburster$to_slave_bid), - .to_slave_bresp(mem0_controller_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(mem0_controller_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(mem0_controller_axi4_deburster$to_slave_rdata), - .to_slave_rid(mem0_controller_axi4_deburster$to_slave_rid), - .to_slave_rlast(mem0_controller_axi4_deburster$to_slave_rlast), - .to_slave_rresp(mem0_controller_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(mem0_controller_axi4_deburster$to_slave_rvalid), - .to_slave_wready(mem0_controller_axi4_deburster$to_slave_wready), - .EN_reset(mem0_controller_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(mem0_controller_axi4_deburster$from_master_awready), - .from_master_wready(mem0_controller_axi4_deburster$from_master_wready), - .from_master_bvalid(mem0_controller_axi4_deburster$from_master_bvalid), - .from_master_bid(mem0_controller_axi4_deburster$from_master_bid), - .from_master_bresp(mem0_controller_axi4_deburster$from_master_bresp), - .from_master_arready(mem0_controller_axi4_deburster$from_master_arready), - .from_master_rvalid(mem0_controller_axi4_deburster$from_master_rvalid), - .from_master_rid(mem0_controller_axi4_deburster$from_master_rid), - .from_master_rdata(mem0_controller_axi4_deburster$from_master_rdata), - .from_master_rresp(mem0_controller_axi4_deburster$from_master_rresp), - .from_master_rlast(mem0_controller_axi4_deburster$from_master_rlast), - .to_slave_awvalid(mem0_controller_axi4_deburster$to_slave_awvalid), - .to_slave_awid(mem0_controller_axi4_deburster$to_slave_awid), - .to_slave_awaddr(mem0_controller_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(mem0_controller_axi4_deburster$to_slave_awlen), - .to_slave_awsize(mem0_controller_axi4_deburster$to_slave_awsize), - .to_slave_awburst(mem0_controller_axi4_deburster$to_slave_awburst), - .to_slave_awlock(mem0_controller_axi4_deburster$to_slave_awlock), - .to_slave_awcache(mem0_controller_axi4_deburster$to_slave_awcache), - .to_slave_awprot(mem0_controller_axi4_deburster$to_slave_awprot), - .to_slave_awqos(mem0_controller_axi4_deburster$to_slave_awqos), - .to_slave_awregion(mem0_controller_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(mem0_controller_axi4_deburster$to_slave_wvalid), - .to_slave_wid(mem0_controller_axi4_deburster$to_slave_wid), - .to_slave_wdata(mem0_controller_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(mem0_controller_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(mem0_controller_axi4_deburster$to_slave_wlast), - .to_slave_bready(mem0_controller_axi4_deburster$to_slave_bready), - .to_slave_arvalid(mem0_controller_axi4_deburster$to_slave_arvalid), - .to_slave_arid(mem0_controller_axi4_deburster$to_slave_arid), - .to_slave_araddr(mem0_controller_axi4_deburster$to_slave_araddr), - .to_slave_arlen(mem0_controller_axi4_deburster$to_slave_arlen), - .to_slave_arsize(mem0_controller_axi4_deburster$to_slave_arsize), - .to_slave_arburst(mem0_controller_axi4_deburster$to_slave_arburst), - .to_slave_arlock(mem0_controller_axi4_deburster$to_slave_arlock), - .to_slave_arcache(mem0_controller_axi4_deburster$to_slave_arcache), - .to_slave_arprot(mem0_controller_axi4_deburster$to_slave_arprot), - .to_slave_arqos(mem0_controller_axi4_deburster$to_slave_arqos), - .to_slave_arregion(mem0_controller_axi4_deburster$to_slave_arregion), - .to_slave_rready(mem0_controller_axi4_deburster$to_slave_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule uart0 - mkUART uart0(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(uart0$put_from_console_put), - .set_addr_map_addr_base(uart0$set_addr_map_addr_base), - .set_addr_map_addr_lim(uart0$set_addr_map_addr_lim), - .slave_araddr(uart0$slave_araddr), - .slave_arburst(uart0$slave_arburst), - .slave_arcache(uart0$slave_arcache), - .slave_arid(uart0$slave_arid), - .slave_arlen(uart0$slave_arlen), - .slave_arlock(uart0$slave_arlock), - .slave_arprot(uart0$slave_arprot), - .slave_arqos(uart0$slave_arqos), - .slave_arregion(uart0$slave_arregion), - .slave_arsize(uart0$slave_arsize), - .slave_arvalid(uart0$slave_arvalid), - .slave_awaddr(uart0$slave_awaddr), - .slave_awburst(uart0$slave_awburst), - .slave_awcache(uart0$slave_awcache), - .slave_awid(uart0$slave_awid), - .slave_awlen(uart0$slave_awlen), - .slave_awlock(uart0$slave_awlock), - .slave_awprot(uart0$slave_awprot), - .slave_awqos(uart0$slave_awqos), - .slave_awregion(uart0$slave_awregion), - .slave_awsize(uart0$slave_awsize), - .slave_awvalid(uart0$slave_awvalid), - .slave_bready(uart0$slave_bready), - .slave_rready(uart0$slave_rready), - .slave_wdata(uart0$slave_wdata), - .slave_wid(uart0$slave_wid), - .slave_wlast(uart0$slave_wlast), - .slave_wstrb(uart0$slave_wstrb), - .slave_wvalid(uart0$slave_wvalid), - .EN_server_reset_request_put(uart0$EN_server_reset_request_put), - .EN_server_reset_response_get(uart0$EN_server_reset_response_get), - .EN_set_addr_map(uart0$EN_set_addr_map), - .EN_get_to_console_get(uart0$EN_get_to_console_get), - .EN_put_from_console_put(uart0$EN_put_from_console_put), - .RDY_server_reset_request_put(uart0$RDY_server_reset_request_put), - .RDY_server_reset_response_get(uart0$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .slave_awready(uart0$slave_awready), - .slave_wready(uart0$slave_wready), - .slave_bvalid(uart0$slave_bvalid), - .slave_bid(uart0$slave_bid), - .slave_bresp(uart0$slave_bresp), - .slave_arready(uart0$slave_arready), - .slave_rvalid(uart0$slave_rvalid), - .slave_rid(uart0$slave_rid), - .slave_rdata(uart0$slave_rdata), - .slave_rresp(uart0$slave_rresp), - .slave_rlast(uart0$slave_rlast), - .get_to_console_get(uart0$get_to_console_get), - .RDY_get_to_console_get(uart0$RDY_get_to_console_get), - .RDY_put_from_console_put(uart0$RDY_put_from_console_put), - .intr(uart0$intr)); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_5 - assign CAN_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - - // rule RL_rl_wr_data_channel_5 - assign CAN_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_response_channel_5 - assign CAN_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_5 - assign CAN_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - - // rule RL_rl_rd_data_channel_5 - assign CAN_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_6 - assign CAN_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - - // rule RL_rl_wr_data_channel_6 - assign CAN_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - - // rule RL_rl_wr_response_channel_6 - assign CAN_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_6 - assign CAN_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - - // rule RL_rl_rd_data_channel_6 - assign CAN_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - - // rule RL_rl_connect_external_interrupt_requests - assign CAN_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - - // rule RL_rl_reset_start_initial - assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete_initial - assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete_initial = - MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = - mem0_controller$RDY_server_reset_request_put && - uart0$RDY_server_reset_request_put && - fabric$RDY_reset && - core$RDY_cpu_reset_server_request_put && - rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && - mem0_controller$RDY_server_reset_response_get && - uart0$RDY_server_reset_response_get && - core$RDY_cpu_reset_server_response_get && - rg_state == 2'd1 ; - - // register rg_state - assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_start_initial || - WILL_FIRE_RL_rl_reset_complete_initial ; - - // submodule boot_rom - assign boot_rom$set_addr_map_addr_base = soc_map$m_boot_rom_addr_base ; - assign boot_rom$set_addr_map_addr_lim = soc_map$m_boot_rom_addr_lim ; - assign boot_rom$slave_araddr = boot_rom_axi4_deburster$to_slave_araddr ; - assign boot_rom$slave_arburst = boot_rom_axi4_deburster$to_slave_arburst ; - assign boot_rom$slave_arcache = boot_rom_axi4_deburster$to_slave_arcache ; - assign boot_rom$slave_arid = boot_rom_axi4_deburster$to_slave_arid ; - assign boot_rom$slave_arlen = boot_rom_axi4_deburster$to_slave_arlen ; - assign boot_rom$slave_arlock = boot_rom_axi4_deburster$to_slave_arlock ; - assign boot_rom$slave_arprot = boot_rom_axi4_deburster$to_slave_arprot ; - assign boot_rom$slave_arqos = boot_rom_axi4_deburster$to_slave_arqos ; - assign boot_rom$slave_arregion = boot_rom_axi4_deburster$to_slave_arregion ; - assign boot_rom$slave_arsize = boot_rom_axi4_deburster$to_slave_arsize ; - assign boot_rom$slave_arvalid = boot_rom_axi4_deburster$to_slave_arvalid ; - assign boot_rom$slave_awaddr = boot_rom_axi4_deburster$to_slave_awaddr ; - assign boot_rom$slave_awburst = boot_rom_axi4_deburster$to_slave_awburst ; - assign boot_rom$slave_awcache = boot_rom_axi4_deburster$to_slave_awcache ; - assign boot_rom$slave_awid = boot_rom_axi4_deburster$to_slave_awid ; - assign boot_rom$slave_awlen = boot_rom_axi4_deburster$to_slave_awlen ; - assign boot_rom$slave_awlock = boot_rom_axi4_deburster$to_slave_awlock ; - assign boot_rom$slave_awprot = boot_rom_axi4_deburster$to_slave_awprot ; - assign boot_rom$slave_awqos = boot_rom_axi4_deburster$to_slave_awqos ; - assign boot_rom$slave_awregion = boot_rom_axi4_deburster$to_slave_awregion ; - assign boot_rom$slave_awsize = boot_rom_axi4_deburster$to_slave_awsize ; - assign boot_rom$slave_awvalid = boot_rom_axi4_deburster$to_slave_awvalid ; - assign boot_rom$slave_bready = boot_rom_axi4_deburster$to_slave_bready ; - assign boot_rom$slave_rready = boot_rom_axi4_deburster$to_slave_rready ; - assign boot_rom$slave_wdata = boot_rom_axi4_deburster$to_slave_wdata ; - assign boot_rom$slave_wid = boot_rom_axi4_deburster$to_slave_wid ; - assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; - assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; - assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - - // submodule boot_rom_axi4_deburster - assign boot_rom_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_0_araddr ; - assign boot_rom_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_0_arburst ; - assign boot_rom_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_0_arcache ; - assign boot_rom_axi4_deburster$from_master_arid = - fabric$v_to_slaves_0_arid ; - assign boot_rom_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_0_arlen ; - assign boot_rom_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_0_arlock ; - assign boot_rom_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_0_arprot ; - assign boot_rom_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_0_arqos ; - assign boot_rom_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_0_arregion ; - assign boot_rom_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_0_arsize ; - assign boot_rom_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_0_arvalid ; - assign boot_rom_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_0_awaddr ; - assign boot_rom_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_0_awburst ; - assign boot_rom_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_0_awcache ; - assign boot_rom_axi4_deburster$from_master_awid = - fabric$v_to_slaves_0_awid ; - assign boot_rom_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_0_awlen ; - assign boot_rom_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_0_awlock ; - assign boot_rom_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_0_awprot ; - assign boot_rom_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_0_awqos ; - assign boot_rom_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_0_awregion ; - assign boot_rom_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_0_awsize ; - assign boot_rom_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_0_awvalid ; - assign boot_rom_axi4_deburster$from_master_bready = - fabric$v_to_slaves_0_bready ; - assign boot_rom_axi4_deburster$from_master_rready = - fabric$v_to_slaves_0_rready ; - assign boot_rom_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_0_wdata ; - assign boot_rom_axi4_deburster$from_master_wid = fabric$v_to_slaves_0_wid ; - assign boot_rom_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_0_wlast ; - assign boot_rom_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_0_wstrb ; - assign boot_rom_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_0_wvalid ; - assign boot_rom_axi4_deburster$to_slave_arready = boot_rom$slave_arready ; - assign boot_rom_axi4_deburster$to_slave_awready = boot_rom$slave_awready ; - assign boot_rom_axi4_deburster$to_slave_bid = boot_rom$slave_bid ; - assign boot_rom_axi4_deburster$to_slave_bresp = boot_rom$slave_bresp ; - assign boot_rom_axi4_deburster$to_slave_bvalid = boot_rom$slave_bvalid ; - assign boot_rom_axi4_deburster$to_slave_rdata = boot_rom$slave_rdata ; - assign boot_rom_axi4_deburster$to_slave_rid = boot_rom$slave_rid ; - assign boot_rom_axi4_deburster$to_slave_rlast = boot_rom$slave_rlast ; - assign boot_rom_axi4_deburster$to_slave_rresp = boot_rom$slave_rresp ; - assign boot_rom_axi4_deburster$to_slave_rvalid = boot_rom$slave_rvalid ; - assign boot_rom_axi4_deburster$to_slave_wready = boot_rom$slave_wready ; - assign boot_rom_axi4_deburster$EN_reset = 1'b0 ; - - // submodule core - assign core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = - uart0$intr ; - assign core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$cpu_dmem_master_arready = fabric$v_from_masters_1_arready ; - assign core$cpu_dmem_master_awready = fabric$v_from_masters_1_awready ; - assign core$cpu_dmem_master_bid = fabric$v_from_masters_1_bid ; - assign core$cpu_dmem_master_bresp = fabric$v_from_masters_1_bresp ; - assign core$cpu_dmem_master_bvalid = fabric$v_from_masters_1_bvalid ; - assign core$cpu_dmem_master_rdata = fabric$v_from_masters_1_rdata ; - assign core$cpu_dmem_master_rid = fabric$v_from_masters_1_rid ; - assign core$cpu_dmem_master_rlast = fabric$v_from_masters_1_rlast ; - assign core$cpu_dmem_master_rresp = fabric$v_from_masters_1_rresp ; - assign core$cpu_dmem_master_rvalid = fabric$v_from_masters_1_rvalid ; - assign core$cpu_dmem_master_wready = fabric$v_from_masters_1_wready ; - assign core$cpu_imem_master_arready = fabric$v_from_masters_0_arready ; - assign core$cpu_imem_master_awready = fabric$v_from_masters_0_awready ; - assign core$cpu_imem_master_bid = fabric$v_from_masters_0_bid ; - assign core$cpu_imem_master_bresp = fabric$v_from_masters_0_bresp ; - assign core$cpu_imem_master_bvalid = fabric$v_from_masters_0_bvalid ; - assign core$cpu_imem_master_rdata = fabric$v_from_masters_0_rdata ; - assign core$cpu_imem_master_rid = fabric$v_from_masters_0_rid ; - assign core$cpu_imem_master_rlast = fabric$v_from_masters_0_rlast ; - assign core$cpu_imem_master_rresp = fabric$v_from_masters_0_rresp ; - assign core$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ; - assign core$cpu_imem_master_wready = fabric$v_from_masters_0_wready ; - assign core$cpu_reset_server_request_put = 1'd1 ; - assign core$nmi_req_set_not_clear = 1'd0 ; - assign core$set_verbosity_logdelay = set_verbosity_logdelay ; - assign core$set_verbosity_verbosity = set_verbosity_verbosity ; - assign core$EN_set_verbosity = EN_set_verbosity ; - assign core$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; - assign core$EN_cpu_reset_server_response_get = MUX_rg_state$write_1__SEL_2 ; - - // submodule fabric - assign fabric$set_verbosity_verbosity = 4'h0 ; - assign fabric$v_from_masters_0_araddr = core$cpu_imem_master_araddr ; - assign fabric$v_from_masters_0_arburst = core$cpu_imem_master_arburst ; - assign fabric$v_from_masters_0_arcache = core$cpu_imem_master_arcache ; - assign fabric$v_from_masters_0_arid = core$cpu_imem_master_arid ; - assign fabric$v_from_masters_0_arlen = core$cpu_imem_master_arlen ; - assign fabric$v_from_masters_0_arlock = core$cpu_imem_master_arlock ; - assign fabric$v_from_masters_0_arprot = core$cpu_imem_master_arprot ; - assign fabric$v_from_masters_0_arqos = core$cpu_imem_master_arqos ; - assign fabric$v_from_masters_0_arregion = core$cpu_imem_master_arregion ; - assign fabric$v_from_masters_0_arsize = core$cpu_imem_master_arsize ; - assign fabric$v_from_masters_0_arvalid = core$cpu_imem_master_arvalid ; - assign fabric$v_from_masters_0_awaddr = core$cpu_imem_master_awaddr ; - assign fabric$v_from_masters_0_awburst = core$cpu_imem_master_awburst ; - assign fabric$v_from_masters_0_awcache = core$cpu_imem_master_awcache ; - assign fabric$v_from_masters_0_awid = core$cpu_imem_master_awid ; - assign fabric$v_from_masters_0_awlen = core$cpu_imem_master_awlen ; - assign fabric$v_from_masters_0_awlock = core$cpu_imem_master_awlock ; - assign fabric$v_from_masters_0_awprot = core$cpu_imem_master_awprot ; - assign fabric$v_from_masters_0_awqos = core$cpu_imem_master_awqos ; - assign fabric$v_from_masters_0_awregion = core$cpu_imem_master_awregion ; - assign fabric$v_from_masters_0_awsize = core$cpu_imem_master_awsize ; - assign fabric$v_from_masters_0_awvalid = core$cpu_imem_master_awvalid ; - assign fabric$v_from_masters_0_bready = core$cpu_imem_master_bready ; - assign fabric$v_from_masters_0_rready = core$cpu_imem_master_rready ; - assign fabric$v_from_masters_0_wdata = core$cpu_imem_master_wdata ; - assign fabric$v_from_masters_0_wid = core$cpu_imem_master_wid ; - assign fabric$v_from_masters_0_wlast = core$cpu_imem_master_wlast ; - assign fabric$v_from_masters_0_wstrb = core$cpu_imem_master_wstrb ; - assign fabric$v_from_masters_0_wvalid = core$cpu_imem_master_wvalid ; - assign fabric$v_from_masters_1_araddr = core$cpu_dmem_master_araddr ; - assign fabric$v_from_masters_1_arburst = core$cpu_dmem_master_arburst ; - assign fabric$v_from_masters_1_arcache = core$cpu_dmem_master_arcache ; - assign fabric$v_from_masters_1_arid = core$cpu_dmem_master_arid ; - assign fabric$v_from_masters_1_arlen = core$cpu_dmem_master_arlen ; - assign fabric$v_from_masters_1_arlock = core$cpu_dmem_master_arlock ; - assign fabric$v_from_masters_1_arprot = core$cpu_dmem_master_arprot ; - assign fabric$v_from_masters_1_arqos = core$cpu_dmem_master_arqos ; - assign fabric$v_from_masters_1_arregion = core$cpu_dmem_master_arregion ; - assign fabric$v_from_masters_1_arsize = core$cpu_dmem_master_arsize ; - assign fabric$v_from_masters_1_arvalid = core$cpu_dmem_master_arvalid ; - assign fabric$v_from_masters_1_awaddr = core$cpu_dmem_master_awaddr ; - assign fabric$v_from_masters_1_awburst = core$cpu_dmem_master_awburst ; - assign fabric$v_from_masters_1_awcache = core$cpu_dmem_master_awcache ; - assign fabric$v_from_masters_1_awid = core$cpu_dmem_master_awid ; - assign fabric$v_from_masters_1_awlen = core$cpu_dmem_master_awlen ; - assign fabric$v_from_masters_1_awlock = core$cpu_dmem_master_awlock ; - assign fabric$v_from_masters_1_awprot = core$cpu_dmem_master_awprot ; - assign fabric$v_from_masters_1_awqos = core$cpu_dmem_master_awqos ; - assign fabric$v_from_masters_1_awregion = core$cpu_dmem_master_awregion ; - assign fabric$v_from_masters_1_awsize = core$cpu_dmem_master_awsize ; - assign fabric$v_from_masters_1_awvalid = core$cpu_dmem_master_awvalid ; - assign fabric$v_from_masters_1_bready = core$cpu_dmem_master_bready ; - assign fabric$v_from_masters_1_rready = core$cpu_dmem_master_rready ; - assign fabric$v_from_masters_1_wdata = core$cpu_dmem_master_wdata ; - assign fabric$v_from_masters_1_wid = core$cpu_dmem_master_wid ; - assign fabric$v_from_masters_1_wlast = core$cpu_dmem_master_wlast ; - assign fabric$v_from_masters_1_wstrb = core$cpu_dmem_master_wstrb ; - assign fabric$v_from_masters_1_wvalid = core$cpu_dmem_master_wvalid ; - assign fabric$v_to_slaves_0_arready = - boot_rom_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_0_awready = - boot_rom_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_0_bid = boot_rom_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_0_bresp = - boot_rom_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_0_bvalid = - boot_rom_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_0_rdata = - boot_rom_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_0_rid = boot_rom_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_0_rlast = - boot_rom_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_0_rresp = - boot_rom_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_0_rvalid = - boot_rom_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_0_wready = - boot_rom_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_1_arready = - mem0_controller_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_1_awready = - mem0_controller_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_1_bid = - mem0_controller_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_1_bresp = - mem0_controller_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_1_bvalid = - mem0_controller_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_1_rdata = - mem0_controller_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_1_rid = - mem0_controller_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_1_rlast = - mem0_controller_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_1_rresp = - mem0_controller_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_1_rvalid = - mem0_controller_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_1_wready = - mem0_controller_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_2_arready = uart0$slave_arready ; - assign fabric$v_to_slaves_2_awready = uart0$slave_awready ; - assign fabric$v_to_slaves_2_bid = uart0$slave_bid ; - assign fabric$v_to_slaves_2_bresp = uart0$slave_bresp ; - assign fabric$v_to_slaves_2_bvalid = uart0$slave_bvalid ; - assign fabric$v_to_slaves_2_rdata = uart0$slave_rdata ; - assign fabric$v_to_slaves_2_rid = uart0$slave_rid ; - assign fabric$v_to_slaves_2_rlast = uart0$slave_rlast ; - assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; - assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; - assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; - assign fabric$EN_set_verbosity = 1'b0 ; - - // submodule mem0_controller - assign mem0_controller$set_addr_map_addr_base = - soc_map$m_mem0_controller_addr_base ; - assign mem0_controller$set_addr_map_addr_lim = - soc_map$m_mem0_controller_addr_lim ; - assign mem0_controller$set_watch_tohost_tohost_addr = - set_watch_tohost_tohost_addr ; - assign mem0_controller$set_watch_tohost_watch_tohost = - set_watch_tohost_watch_tohost ; - assign mem0_controller$slave_araddr = - mem0_controller_axi4_deburster$to_slave_araddr ; - assign mem0_controller$slave_arburst = - mem0_controller_axi4_deburster$to_slave_arburst ; - assign mem0_controller$slave_arcache = - mem0_controller_axi4_deburster$to_slave_arcache ; - assign mem0_controller$slave_arid = - mem0_controller_axi4_deburster$to_slave_arid ; - assign mem0_controller$slave_arlen = - mem0_controller_axi4_deburster$to_slave_arlen ; - assign mem0_controller$slave_arlock = - mem0_controller_axi4_deburster$to_slave_arlock ; - assign mem0_controller$slave_arprot = - mem0_controller_axi4_deburster$to_slave_arprot ; - assign mem0_controller$slave_arqos = - mem0_controller_axi4_deburster$to_slave_arqos ; - assign mem0_controller$slave_arregion = - mem0_controller_axi4_deburster$to_slave_arregion ; - assign mem0_controller$slave_arsize = - mem0_controller_axi4_deburster$to_slave_arsize ; - assign mem0_controller$slave_arvalid = - mem0_controller_axi4_deburster$to_slave_arvalid ; - assign mem0_controller$slave_awaddr = - mem0_controller_axi4_deburster$to_slave_awaddr ; - assign mem0_controller$slave_awburst = - mem0_controller_axi4_deburster$to_slave_awburst ; - assign mem0_controller$slave_awcache = - mem0_controller_axi4_deburster$to_slave_awcache ; - assign mem0_controller$slave_awid = - mem0_controller_axi4_deburster$to_slave_awid ; - assign mem0_controller$slave_awlen = - mem0_controller_axi4_deburster$to_slave_awlen ; - assign mem0_controller$slave_awlock = - mem0_controller_axi4_deburster$to_slave_awlock ; - assign mem0_controller$slave_awprot = - mem0_controller_axi4_deburster$to_slave_awprot ; - assign mem0_controller$slave_awqos = - mem0_controller_axi4_deburster$to_slave_awqos ; - assign mem0_controller$slave_awregion = - mem0_controller_axi4_deburster$to_slave_awregion ; - assign mem0_controller$slave_awsize = - mem0_controller_axi4_deburster$to_slave_awsize ; - assign mem0_controller$slave_awvalid = - mem0_controller_axi4_deburster$to_slave_awvalid ; - assign mem0_controller$slave_bready = - mem0_controller_axi4_deburster$to_slave_bready ; - assign mem0_controller$slave_rready = - mem0_controller_axi4_deburster$to_slave_rready ; - assign mem0_controller$slave_wdata = - mem0_controller_axi4_deburster$to_slave_wdata ; - assign mem0_controller$slave_wid = - mem0_controller_axi4_deburster$to_slave_wid ; - assign mem0_controller$slave_wlast = - mem0_controller_axi4_deburster$to_slave_wlast ; - assign mem0_controller$slave_wstrb = - mem0_controller_axi4_deburster$to_slave_wstrb ; - assign mem0_controller$slave_wvalid = - mem0_controller_axi4_deburster$to_slave_wvalid ; - assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; - assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; - assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_to_raw_mem_request_get = - EN_to_raw_mem_request_get ; - assign mem0_controller$EN_to_raw_mem_response_put = - EN_to_raw_mem_response_put ; - assign mem0_controller$EN_set_watch_tohost = EN_set_watch_tohost ; - - // submodule mem0_controller_axi4_deburster - assign mem0_controller_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_1_araddr ; - assign mem0_controller_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_1_arburst ; - assign mem0_controller_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_1_arcache ; - assign mem0_controller_axi4_deburster$from_master_arid = - fabric$v_to_slaves_1_arid ; - assign mem0_controller_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_1_arlen ; - assign mem0_controller_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_1_arlock ; - assign mem0_controller_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_1_arprot ; - assign mem0_controller_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_1_arqos ; - assign mem0_controller_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_1_arregion ; - assign mem0_controller_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_1_arsize ; - assign mem0_controller_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_1_arvalid ; - assign mem0_controller_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_1_awaddr ; - assign mem0_controller_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_1_awburst ; - assign mem0_controller_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_1_awcache ; - assign mem0_controller_axi4_deburster$from_master_awid = - fabric$v_to_slaves_1_awid ; - assign mem0_controller_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_1_awlen ; - assign mem0_controller_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_1_awlock ; - assign mem0_controller_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_1_awprot ; - assign mem0_controller_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_1_awqos ; - assign mem0_controller_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_1_awregion ; - assign mem0_controller_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_1_awsize ; - assign mem0_controller_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_1_awvalid ; - assign mem0_controller_axi4_deburster$from_master_bready = - fabric$v_to_slaves_1_bready ; - assign mem0_controller_axi4_deburster$from_master_rready = - fabric$v_to_slaves_1_rready ; - assign mem0_controller_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_1_wdata ; - assign mem0_controller_axi4_deburster$from_master_wid = - fabric$v_to_slaves_1_wid ; - assign mem0_controller_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_1_wlast ; - assign mem0_controller_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_1_wstrb ; - assign mem0_controller_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_1_wvalid ; - assign mem0_controller_axi4_deburster$to_slave_arready = - mem0_controller$slave_arready ; - assign mem0_controller_axi4_deburster$to_slave_awready = - mem0_controller$slave_awready ; - assign mem0_controller_axi4_deburster$to_slave_bid = - mem0_controller$slave_bid ; - assign mem0_controller_axi4_deburster$to_slave_bresp = - mem0_controller$slave_bresp ; - assign mem0_controller_axi4_deburster$to_slave_bvalid = - mem0_controller$slave_bvalid ; - assign mem0_controller_axi4_deburster$to_slave_rdata = - mem0_controller$slave_rdata ; - assign mem0_controller_axi4_deburster$to_slave_rid = - mem0_controller$slave_rid ; - assign mem0_controller_axi4_deburster$to_slave_rlast = - mem0_controller$slave_rlast ; - assign mem0_controller_axi4_deburster$to_slave_rresp = - mem0_controller$slave_rresp ; - assign mem0_controller_axi4_deburster$to_slave_rvalid = - mem0_controller$slave_rvalid ; - assign mem0_controller_axi4_deburster$to_slave_wready = - mem0_controller$slave_wready ; - assign mem0_controller_axi4_deburster$EN_reset = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule uart0 - assign uart0$put_from_console_put = put_from_console_put ; - assign uart0$set_addr_map_addr_base = soc_map$m_uart0_addr_base ; - assign uart0$set_addr_map_addr_lim = soc_map$m_uart0_addr_lim ; - assign uart0$slave_araddr = fabric$v_to_slaves_2_araddr ; - assign uart0$slave_arburst = fabric$v_to_slaves_2_arburst ; - assign uart0$slave_arcache = fabric$v_to_slaves_2_arcache ; - assign uart0$slave_arid = fabric$v_to_slaves_2_arid ; - assign uart0$slave_arlen = fabric$v_to_slaves_2_arlen ; - assign uart0$slave_arlock = fabric$v_to_slaves_2_arlock ; - assign uart0$slave_arprot = fabric$v_to_slaves_2_arprot ; - assign uart0$slave_arqos = fabric$v_to_slaves_2_arqos ; - assign uart0$slave_arregion = fabric$v_to_slaves_2_arregion ; - assign uart0$slave_arsize = fabric$v_to_slaves_2_arsize ; - assign uart0$slave_arvalid = fabric$v_to_slaves_2_arvalid ; - assign uart0$slave_awaddr = fabric$v_to_slaves_2_awaddr ; - assign uart0$slave_awburst = fabric$v_to_slaves_2_awburst ; - assign uart0$slave_awcache = fabric$v_to_slaves_2_awcache ; - assign uart0$slave_awid = fabric$v_to_slaves_2_awid ; - assign uart0$slave_awlen = fabric$v_to_slaves_2_awlen ; - assign uart0$slave_awlock = fabric$v_to_slaves_2_awlock ; - assign uart0$slave_awprot = fabric$v_to_slaves_2_awprot ; - assign uart0$slave_awqos = fabric$v_to_slaves_2_awqos ; - assign uart0$slave_awregion = fabric$v_to_slaves_2_awregion ; - assign uart0$slave_awsize = fabric$v_to_slaves_2_awsize ; - assign uart0$slave_awvalid = fabric$v_to_slaves_2_awvalid ; - assign uart0$slave_bready = fabric$v_to_slaves_2_bready ; - assign uart0$slave_rready = fabric$v_to_slaves_2_rready ; - assign uart0$slave_wdata = fabric$v_to_slaves_2_wdata ; - assign uart0$slave_wid = fabric$v_to_slaves_2_wid ; - assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; - assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; - assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_get_to_console_get = EN_get_to_console_get ; - assign uart0$EN_put_from_console_put = EN_put_from_console_put ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - begin - v__h11286 = $stime; - #0; - end - v__h11280 = v__h11286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - $display("%0d:%m.rl_reset_start_initial ...", v__h11280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - begin - v__h11556 = $stime; - #0; - end - v__h11550 = v__h11556 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - $display("%0d:%m.rl_reset_complete_initial", v__h11550); - end - // synopsys translate_on -endmodule // mkSoC_Top - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTLB.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTLB.v deleted file mode 100644 index 824d1ae3..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTLB.v +++ /dev/null @@ -1,617 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_flush O 1 const -// lookup O 131 -// RDY_lookup O 1 -// RDY_insert O 1 -// CLK I 1 clock -// RST_N I 1 reset -// lookup_asid I 16 -// lookup_vpn I 27 -// insert_asid I 16 reg -// insert_vpn I 27 -// insert_pte I 64 reg -// insert_level I 2 -// insert_pte_pa I 64 reg -// EN_flush I 1 -// EN_insert I 1 -// -// Combinational paths from inputs to outputs: -// (lookup_asid, lookup_vpn) -> lookup -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTLB(CLK, - RST_N, - - EN_flush, - RDY_flush, - - lookup_asid, - lookup_vpn, - lookup, - RDY_lookup, - - insert_asid, - insert_vpn, - insert_pte, - insert_level, - insert_pte_pa, - EN_insert, - RDY_insert); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method flush - input EN_flush; - output RDY_flush; - - // value method lookup - input [15 : 0] lookup_asid; - input [26 : 0] lookup_vpn; - output [130 : 0] lookup; - output RDY_lookup; - - // action method insert - input [15 : 0] insert_asid; - input [26 : 0] insert_vpn; - input [63 : 0] insert_pte; - input [1 : 0] insert_level; - input [63 : 0] insert_pte_pa; - input EN_insert; - output RDY_insert; - - // signals for module outputs - wire [130 : 0] lookup; - wire RDY_flush, RDY_insert, RDY_lookup; - - // register rg_flushing - reg rg_flushing; - wire rg_flushing$D_IN, rg_flushing$EN; - - // register tlb0_valids_0 - reg tlb0_valids_0; - wire tlb0_valids_0$D_IN, tlb0_valids_0$EN; - - // register tlb0_valids_1 - reg tlb0_valids_1; - wire tlb0_valids_1$D_IN, tlb0_valids_1$EN; - - // register tlb0_valids_2 - reg tlb0_valids_2; - wire tlb0_valids_2$D_IN, tlb0_valids_2$EN; - - // register tlb0_valids_3 - reg tlb0_valids_3; - wire tlb0_valids_3$D_IN, tlb0_valids_3$EN; - - // register tlb1_valids_0 - reg tlb1_valids_0; - wire tlb1_valids_0$D_IN, tlb1_valids_0$EN; - - // register tlb1_valids_1 - reg tlb1_valids_1; - wire tlb1_valids_1$D_IN, tlb1_valids_1$EN; - - // register tlb1_valids_2 - reg tlb1_valids_2; - wire tlb1_valids_2$D_IN, tlb1_valids_2$EN; - - // register tlb1_valids_3 - reg tlb1_valids_3; - wire tlb1_valids_3$D_IN, tlb1_valids_3$EN; - - // register tlb2_valids_0 - reg tlb2_valids_0; - wire tlb2_valids_0$D_IN, tlb2_valids_0$EN; - - // register tlb2_valids_1 - reg tlb2_valids_1; - wire tlb2_valids_1$D_IN, tlb2_valids_1$EN; - - // register tlb2_valids_2 - reg tlb2_valids_2; - wire tlb2_valids_2$D_IN, tlb2_valids_2$EN; - - // register tlb2_valids_3 - reg tlb2_valids_3; - wire tlb2_valids_3$D_IN, tlb2_valids_3$EN; - - // ports of submodule tlb0_entries - wire [168 : 0] tlb0_entries$D_IN, tlb0_entries$D_OUT_1; - wire [1 : 0] tlb0_entries$ADDR_1, - tlb0_entries$ADDR_2, - tlb0_entries$ADDR_3, - tlb0_entries$ADDR_4, - tlb0_entries$ADDR_5, - tlb0_entries$ADDR_IN; - wire tlb0_entries$WE; - - // ports of submodule tlb1_entries - wire [159 : 0] tlb1_entries$D_IN, tlb1_entries$D_OUT_1; - wire [1 : 0] tlb1_entries$ADDR_1, - tlb1_entries$ADDR_2, - tlb1_entries$ADDR_3, - tlb1_entries$ADDR_4, - tlb1_entries$ADDR_5, - tlb1_entries$ADDR_IN; - wire tlb1_entries$WE; - - // ports of submodule tlb2_entries - wire [150 : 0] tlb2_entries$D_IN, tlb2_entries$D_OUT_1; - wire [1 : 0] tlb2_entries$ADDR_1, - tlb2_entries$ADDR_2, - tlb2_entries$ADDR_3, - tlb2_entries$ADDR_4, - tlb2_entries$ADDR_5, - tlb2_entries$ADDR_IN; - wire tlb2_entries$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_initialize, - CAN_FIRE_flush, - CAN_FIRE_insert, - WILL_FIRE_RL_rl_initialize, - WILL_FIRE_flush, - WILL_FIRE_insert; - - // inputs to muxes for submodule ports - wire MUX_tlb0_valids_0$write_1__SEL_1, - MUX_tlb0_valids_1$write_1__SEL_1, - MUX_tlb0_valids_2$write_1__SEL_1, - MUX_tlb0_valids_3$write_1__SEL_1, - MUX_tlb1_valids_0$write_1__SEL_1, - MUX_tlb1_valids_1$write_1__SEL_1, - MUX_tlb1_valids_2$write_1__SEL_1, - MUX_tlb1_valids_3$write_1__SEL_1, - MUX_tlb2_valids_0$write_1__SEL_1, - MUX_tlb2_valids_1$write_1__SEL_1, - MUX_tlb2_valids_2$write_1__SEL_1, - MUX_tlb2_valids_3$write_1__SEL_1; - - // remaining internal signals - reg SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51, - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29, - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8; - wire [129 : 0] IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d92, - IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d93; - wire NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73, - NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43, - NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22, - NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d80, - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61, - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65, - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54, - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60, - tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33, - tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41, - tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12, - tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20; - - // action method flush - assign RDY_flush = 1'd1 ; - assign CAN_FIRE_flush = 1'd1 ; - assign WILL_FIRE_flush = EN_flush ; - - // value method lookup - assign lookup = - { NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 && - NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 && - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61 || - NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d80, - IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d93 } ; - assign RDY_lookup = !rg_flushing ; - - // action method insert - assign RDY_insert = !rg_flushing ; - assign CAN_FIRE_insert = !rg_flushing ; - assign WILL_FIRE_insert = EN_insert ; - - // submodule tlb0_entries - RegFile #(.addr_width(32'd2), - .data_width(32'd169), - .lo(2'h0), - .hi(2'd3)) tlb0_entries(.CLK(CLK), - .ADDR_1(tlb0_entries$ADDR_1), - .ADDR_2(tlb0_entries$ADDR_2), - .ADDR_3(tlb0_entries$ADDR_3), - .ADDR_4(tlb0_entries$ADDR_4), - .ADDR_5(tlb0_entries$ADDR_5), - .ADDR_IN(tlb0_entries$ADDR_IN), - .D_IN(tlb0_entries$D_IN), - .WE(tlb0_entries$WE), - .D_OUT_1(tlb0_entries$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule tlb1_entries - RegFile #(.addr_width(32'd2), - .data_width(32'd160), - .lo(2'h0), - .hi(2'd3)) tlb1_entries(.CLK(CLK), - .ADDR_1(tlb1_entries$ADDR_1), - .ADDR_2(tlb1_entries$ADDR_2), - .ADDR_3(tlb1_entries$ADDR_3), - .ADDR_4(tlb1_entries$ADDR_4), - .ADDR_5(tlb1_entries$ADDR_5), - .ADDR_IN(tlb1_entries$ADDR_IN), - .D_IN(tlb1_entries$D_IN), - .WE(tlb1_entries$WE), - .D_OUT_1(tlb1_entries$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule tlb2_entries - RegFile #(.addr_width(32'd2), - .data_width(32'd151), - .lo(2'h0), - .hi(2'd3)) tlb2_entries(.CLK(CLK), - .ADDR_1(tlb2_entries$ADDR_1), - .ADDR_2(tlb2_entries$ADDR_2), - .ADDR_3(tlb2_entries$ADDR_3), - .ADDR_4(tlb2_entries$ADDR_4), - .ADDR_5(tlb2_entries$ADDR_5), - .ADDR_IN(tlb2_entries$ADDR_IN), - .D_IN(tlb2_entries$D_IN), - .WE(tlb2_entries$WE), - .D_OUT_1(tlb2_entries$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_initialize - assign CAN_FIRE_RL_rl_initialize = rg_flushing ; - assign WILL_FIRE_RL_rl_initialize = rg_flushing ; - - // inputs to muxes for submodule ports - assign MUX_tlb0_valids_0$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd0 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_1$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd1 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_2$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd2 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_3$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd3 && insert_level == 2'd0 ; - assign MUX_tlb1_valids_0$write_1__SEL_1 = - EN_insert && insert_vpn[10:9] == 2'd0 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_1$write_1__SEL_1 = - EN_insert && insert_vpn[10:9] == 2'd1 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_2$write_1__SEL_1 = - EN_insert && insert_vpn[10:9] == 2'd2 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_3$write_1__SEL_1 = - EN_insert && insert_vpn[10:9] == 2'd3 && insert_level == 2'd1 ; - assign MUX_tlb2_valids_0$write_1__SEL_1 = - EN_insert && insert_vpn[19:18] == 2'd0 && insert_level != 2'd0 && - insert_level != 2'd1 ; - assign MUX_tlb2_valids_1$write_1__SEL_1 = - EN_insert && insert_vpn[19:18] == 2'd1 && insert_level != 2'd0 && - insert_level != 2'd1 ; - assign MUX_tlb2_valids_2$write_1__SEL_1 = - EN_insert && insert_vpn[19:18] == 2'd2 && insert_level != 2'd0 && - insert_level != 2'd1 ; - assign MUX_tlb2_valids_3$write_1__SEL_1 = - EN_insert && insert_vpn[19:18] == 2'd3 && insert_level != 2'd0 && - insert_level != 2'd1 ; - - // register rg_flushing - assign rg_flushing$D_IN = EN_flush ; - assign rg_flushing$EN = rg_flushing || EN_flush ; - - // register tlb0_valids_0 - assign tlb0_valids_0$D_IN = MUX_tlb0_valids_0$write_1__SEL_1 ; - assign tlb0_valids_0$EN = - EN_insert && insert_vpn[1:0] == 2'd0 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_1 - assign tlb0_valids_1$D_IN = MUX_tlb0_valids_1$write_1__SEL_1 ; - assign tlb0_valids_1$EN = - EN_insert && insert_vpn[1:0] == 2'd1 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_2 - assign tlb0_valids_2$D_IN = MUX_tlb0_valids_2$write_1__SEL_1 ; - assign tlb0_valids_2$EN = - EN_insert && insert_vpn[1:0] == 2'd2 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_3 - assign tlb0_valids_3$D_IN = MUX_tlb0_valids_3$write_1__SEL_1 ; - assign tlb0_valids_3$EN = - EN_insert && insert_vpn[1:0] == 2'd3 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb1_valids_0 - assign tlb1_valids_0$D_IN = MUX_tlb1_valids_0$write_1__SEL_1 ; - assign tlb1_valids_0$EN = - EN_insert && insert_vpn[10:9] == 2'd0 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_1 - assign tlb1_valids_1$D_IN = MUX_tlb1_valids_1$write_1__SEL_1 ; - assign tlb1_valids_1$EN = - EN_insert && insert_vpn[10:9] == 2'd1 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_2 - assign tlb1_valids_2$D_IN = MUX_tlb1_valids_2$write_1__SEL_1 ; - assign tlb1_valids_2$EN = - EN_insert && insert_vpn[10:9] == 2'd2 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_3 - assign tlb1_valids_3$D_IN = MUX_tlb1_valids_3$write_1__SEL_1 ; - assign tlb1_valids_3$EN = - EN_insert && insert_vpn[10:9] == 2'd3 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb2_valids_0 - assign tlb2_valids_0$D_IN = MUX_tlb2_valids_0$write_1__SEL_1 ; - assign tlb2_valids_0$EN = - EN_insert && insert_vpn[19:18] == 2'd0 && insert_level != 2'd0 && - insert_level != 2'd1 || - rg_flushing ; - - // register tlb2_valids_1 - assign tlb2_valids_1$D_IN = MUX_tlb2_valids_1$write_1__SEL_1 ; - assign tlb2_valids_1$EN = - EN_insert && insert_vpn[19:18] == 2'd1 && insert_level != 2'd0 && - insert_level != 2'd1 || - rg_flushing ; - - // register tlb2_valids_2 - assign tlb2_valids_2$D_IN = MUX_tlb2_valids_2$write_1__SEL_1 ; - assign tlb2_valids_2$EN = - EN_insert && insert_vpn[19:18] == 2'd2 && insert_level != 2'd0 && - insert_level != 2'd1 || - rg_flushing ; - - // register tlb2_valids_3 - assign tlb2_valids_3$D_IN = MUX_tlb2_valids_3$write_1__SEL_1 ; - assign tlb2_valids_3$EN = - EN_insert && insert_vpn[19:18] == 2'd3 && insert_level != 2'd0 && - insert_level != 2'd1 || - rg_flushing ; - - // submodule tlb0_entries - assign tlb0_entries$ADDR_1 = lookup_vpn[1:0] ; - assign tlb0_entries$ADDR_2 = 2'h0 ; - assign tlb0_entries$ADDR_3 = 2'h0 ; - assign tlb0_entries$ADDR_4 = 2'h0 ; - assign tlb0_entries$ADDR_5 = 2'h0 ; - assign tlb0_entries$ADDR_IN = insert_vpn[1:0] ; - assign tlb0_entries$D_IN = - { insert_asid, insert_vpn[26:2], insert_pte, insert_pte_pa } ; - assign tlb0_entries$WE = EN_insert && insert_level == 2'd0 ; - - // submodule tlb1_entries - assign tlb1_entries$ADDR_1 = lookup_vpn[10:9] ; - assign tlb1_entries$ADDR_2 = 2'h0 ; - assign tlb1_entries$ADDR_3 = 2'h0 ; - assign tlb1_entries$ADDR_4 = 2'h0 ; - assign tlb1_entries$ADDR_5 = 2'h0 ; - assign tlb1_entries$ADDR_IN = insert_vpn[10:9] ; - assign tlb1_entries$D_IN = - { insert_asid, insert_vpn[26:11], insert_pte, insert_pte_pa } ; - assign tlb1_entries$WE = EN_insert && insert_level == 2'd1 ; - - // submodule tlb2_entries - assign tlb2_entries$ADDR_1 = lookup_vpn[19:18] ; - assign tlb2_entries$ADDR_2 = 2'h0 ; - assign tlb2_entries$ADDR_3 = 2'h0 ; - assign tlb2_entries$ADDR_4 = 2'h0 ; - assign tlb2_entries$ADDR_5 = 2'h0 ; - assign tlb2_entries$ADDR_IN = insert_vpn[19:18] ; - assign tlb2_entries$D_IN = - { insert_asid, insert_vpn[26:20], insert_pte, insert_pte_pa } ; - assign tlb2_entries$WE = - EN_insert && insert_level != 2'd0 && insert_level != 2'd1 ; - - // remaining internal signals - assign IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d92 = - (NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 && - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65 && - NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73) ? - { tlb1_entries$D_OUT_1[127:64], - 2'd1, - tlb1_entries$D_OUT_1[63:0] } : - { tlb2_entries$D_OUT_1[127:64], - 2'd2, - tlb2_entries$D_OUT_1[63:0] } ; - assign IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d93 = - (NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 && - NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 && - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61) ? - { tlb0_entries$D_OUT_1[127:64], - 2'd0, - tlb0_entries$D_OUT_1[63:0] } : - IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d92 ; - assign NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73 = - !SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 || - !tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54 && - !tlb0_entries$D_OUT_1[69] || - !tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60 ; - assign NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 = - !SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 || - !tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33 && - !tlb1_entries$D_OUT_1[69] || - !tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41 ; - assign NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 = - !SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 || - !tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12 && - !tlb2_entries$D_OUT_1[69] || - !tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20 ; - assign NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d80 = - NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 && - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65 && - NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73 || - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 && - (tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12 || - tlb2_entries$D_OUT_1[69]) && - tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20 && - NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 && - NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73 ; - assign SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61 = - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 && - (tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54 || - tlb0_entries$D_OUT_1[69]) && - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60 ; - assign SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65 = - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 && - (tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33 || - tlb1_entries$D_OUT_1[69]) && - tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41 ; - assign tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54 = - tlb0_entries$D_OUT_1[168:153] == lookup_asid ; - assign tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60 = - tlb0_entries$D_OUT_1[152:128] == lookup_vpn[26:2] ; - assign tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33 = - tlb1_entries$D_OUT_1[159:144] == lookup_asid ; - assign tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41 = - tlb1_entries$D_OUT_1[143:128] == lookup_vpn[26:11] ; - assign tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12 = - tlb2_entries$D_OUT_1[150:135] == lookup_asid ; - assign tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20 = - tlb2_entries$D_OUT_1[134:128] == lookup_vpn[26:20] ; - always@(lookup_vpn or - tlb2_valids_0 or tlb2_valids_1 or tlb2_valids_2 or tlb2_valids_3) - begin - case (lookup_vpn[19:18]) - 2'd0: - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 = - tlb2_valids_0; - 2'd1: - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 = - tlb2_valids_1; - 2'd2: - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 = - tlb2_valids_2; - 2'd3: - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 = - tlb2_valids_3; - endcase - end - always@(lookup_vpn or - tlb1_valids_0 or tlb1_valids_1 or tlb1_valids_2 or tlb1_valids_3) - begin - case (lookup_vpn[10:9]) - 2'd0: - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 = - tlb1_valids_0; - 2'd1: - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 = - tlb1_valids_1; - 2'd2: - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 = - tlb1_valids_2; - 2'd3: - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 = - tlb1_valids_3; - endcase - end - always@(lookup_vpn or - tlb0_valids_0 or tlb0_valids_1 or tlb0_valids_2 or tlb0_valids_3) - begin - case (lookup_vpn[1:0]) - 2'd0: - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 = - tlb0_valids_0; - 2'd1: - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 = - tlb0_valids_1; - 2'd2: - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 = - tlb0_valids_2; - 2'd3: - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 = - tlb0_valids_3; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_flushing <= `BSV_ASSIGNMENT_DELAY 1'd1; - end - else - begin - if (rg_flushing$EN) - rg_flushing <= `BSV_ASSIGNMENT_DELAY rg_flushing$D_IN; - end - if (tlb0_valids_0$EN) - tlb0_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_0$D_IN; - if (tlb0_valids_1$EN) - tlb0_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_1$D_IN; - if (tlb0_valids_2$EN) - tlb0_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_2$D_IN; - if (tlb0_valids_3$EN) - tlb0_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_3$D_IN; - if (tlb1_valids_0$EN) - tlb1_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_0$D_IN; - if (tlb1_valids_1$EN) - tlb1_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_1$D_IN; - if (tlb1_valids_2$EN) - tlb1_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_2$D_IN; - if (tlb1_valids_3$EN) - tlb1_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_3$D_IN; - if (tlb2_valids_0$EN) - tlb2_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_0$D_IN; - if (tlb2_valids_1$EN) - tlb2_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_1$D_IN; - if (tlb2_valids_2$EN) - tlb2_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_2$D_IN; - if (tlb2_valids_3$EN) - tlb2_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_flushing = 1'h0; - tlb0_valids_0 = 1'h0; - tlb0_valids_1 = 1'h0; - tlb0_valids_2 = 1'h0; - tlb0_valids_3 = 1'h0; - tlb1_valids_0 = 1'h0; - tlb1_valids_1 = 1'h0; - tlb1_valids_2 = 1'h0; - tlb1_valids_3 = 1'h0; - tlb2_valids_0 = 1'h0; - tlb2_valids_1 = 1'h0; - tlb2_valids_2 = 1'h0; - tlb2_valids_3 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkTLB - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v deleted file mode 100644 index a195f14f..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v +++ /dev/null @@ -1,255 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// CLK I 1 clock -// RST_N I 1 reset -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTop_HW_Side(CLK, - RST_N); - input CLK; - input RST_N; - - // register rg_banner_printed - reg rg_banner_printed; - wire rg_banner_printed$D_IN, rg_banner_printed$EN; - - // ports of submodule mem_model - wire [352 : 0] mem_model$mem_server_request_put; - wire [255 : 0] mem_model$mem_server_response_get; - wire mem_model$EN_mem_server_request_put, - mem_model$EN_mem_server_response_get, - mem_model$RDY_mem_server_request_put, - mem_model$RDY_mem_server_response_get; - - // ports of submodule soc_top - wire [352 : 0] soc_top$to_raw_mem_request_get; - wire [255 : 0] soc_top$to_raw_mem_response_put; - wire [63 : 0] soc_top$set_verbosity_logdelay, - soc_top$set_watch_tohost_tohost_addr; - wire [7 : 0] soc_top$get_to_console_get, - soc_top$put_from_console_put, - soc_top$status; - wire [3 : 0] soc_top$set_verbosity_verbosity; - wire soc_top$EN_get_to_console_get, - soc_top$EN_put_from_console_put, - soc_top$EN_set_verbosity, - soc_top$EN_set_watch_tohost, - soc_top$EN_to_raw_mem_request_get, - soc_top$EN_to_raw_mem_response_put, - soc_top$RDY_get_to_console_get, - soc_top$RDY_to_raw_mem_request_get, - soc_top$RDY_to_raw_mem_response_put, - soc_top$set_watch_tohost_watch_tohost; - - // rule scheduling signals - wire CAN_FIRE_RL_memCnx_ClientServerRequest, - CAN_FIRE_RL_memCnx_ClientServerResponse, - CAN_FIRE_RL_rl_relay_console_out, - CAN_FIRE_RL_rl_step0, - CAN_FIRE_RL_rl_terminate, - WILL_FIRE_RL_memCnx_ClientServerRequest, - WILL_FIRE_RL_memCnx_ClientServerResponse, - WILL_FIRE_RL_rl_relay_console_out, - WILL_FIRE_RL_rl_step0, - WILL_FIRE_RL_rl_terminate; - - // declarations used by system tasks - // synopsys translate_off - reg TASK_testplusargs___d12; - reg TASK_testplusargs___d11; - reg [31 : 0] v__h536; - reg [31 : 0] v__h530; - // synopsys translate_on - - // submodule mem_model - mkMem_Model mem_model(.CLK(CLK), - .RST_N(RST_N), - .mem_server_request_put(mem_model$mem_server_request_put), - .EN_mem_server_request_put(mem_model$EN_mem_server_request_put), - .EN_mem_server_response_get(mem_model$EN_mem_server_response_get), - .RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put), - .mem_server_response_get(mem_model$mem_server_response_get), - .RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get)); - - // submodule soc_top - mkSoC_Top soc_top(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(soc_top$put_from_console_put), - .set_verbosity_logdelay(soc_top$set_verbosity_logdelay), - .set_verbosity_verbosity(soc_top$set_verbosity_verbosity), - .set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost), - .to_raw_mem_response_put(soc_top$to_raw_mem_response_put), - .EN_set_verbosity(soc_top$EN_set_verbosity), - .EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put), - .EN_get_to_console_get(soc_top$EN_get_to_console_get), - .EN_put_from_console_put(soc_top$EN_put_from_console_put), - .EN_set_watch_tohost(soc_top$EN_set_watch_tohost), - .RDY_set_verbosity(), - .to_raw_mem_request_get(soc_top$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put), - .get_to_console_get(soc_top$get_to_console_get), - .RDY_get_to_console_get(soc_top$RDY_get_to_console_get), - .RDY_put_from_console_put(), - .status(soc_top$status), - .RDY_set_watch_tohost()); - - // rule RL_rl_step0 - assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ; - assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ; - - // rule RL_rl_terminate - assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ; - assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ; - - // rule RL_rl_relay_console_out - assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - - // rule RL_memCnx_ClientServerRequest - assign CAN_FIRE_RL_memCnx_ClientServerRequest = - soc_top$RDY_to_raw_mem_request_get && - mem_model$RDY_mem_server_request_put ; - assign WILL_FIRE_RL_memCnx_ClientServerRequest = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - - // rule RL_memCnx_ClientServerResponse - assign CAN_FIRE_RL_memCnx_ClientServerResponse = - soc_top$RDY_to_raw_mem_response_put && - mem_model$RDY_mem_server_response_get ; - assign WILL_FIRE_RL_memCnx_ClientServerResponse = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // register rg_banner_printed - assign rg_banner_printed$D_IN = 1'd1 ; - assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ; - - // submodule mem_model - assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ; - assign mem_model$EN_mem_server_request_put = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign mem_model$EN_mem_server_response_get = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // submodule soc_top - assign soc_top$put_from_console_put = 8'h0 ; - assign soc_top$set_verbosity_logdelay = 64'd0 ; - assign soc_top$set_verbosity_verbosity = - TASK_testplusargs___d11 ? - 4'd2 : - (TASK_testplusargs___d12 ? 4'd1 : 4'd0) ; - assign soc_top$set_watch_tohost_tohost_addr = 64'h0 ; - assign soc_top$set_watch_tohost_watch_tohost = 1'b0 ; - assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ; - assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ; - assign soc_top$EN_to_raw_mem_request_get = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign soc_top$EN_to_raw_mem_response_put = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ; - assign soc_top$EN_put_from_console_put = 1'b0 ; - assign soc_top$EN_set_watch_tohost = 1'b0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_banner_printed$EN) - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_banner_printed = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Bluespec RISC-V standalone system simulation v1.2"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d12 = $test$plusargs("v1"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d11 = $test$plusargs("v2"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h536 = $stime; - #0; - end - v__h530 = v__h536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $display("%0d: %m.rl_terminate: soc_top status is 0x%0h (= 0d%0d)", - v__h530, - soc_top$status, - soc_top$status); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) - $write("%c", soc_top$get_to_console_get); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001); - end - // synopsys translate_on -endmodule // mkTop_HW_Side - diff --git a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkUART.v b/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkUART.v deleted file mode 100644 index 033775ea..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_iverilog/Verilog_RTL/mkUART.v +++ /dev/null @@ -1,2925 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// intr O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// put_from_console_put I 8 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_put_from_console_put I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkUART(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - intr); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method intr - output intr; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [7 : 0] get_to_console_get; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - intr, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register cfg_verbosity - reg [7 : 0] cfg_verbosity; - wire [7 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_dll - reg [7 : 0] rg_dll; - wire [7 : 0] rg_dll$D_IN; - wire rg_dll$EN; - - // register rg_dlm - reg [7 : 0] rg_dlm; - wire [7 : 0] rg_dlm$D_IN; - wire rg_dlm$EN; - - // register rg_fcr - reg [7 : 0] rg_fcr; - wire [7 : 0] rg_fcr$D_IN; - wire rg_fcr$EN; - - // register rg_ier - reg [7 : 0] rg_ier; - wire [7 : 0] rg_ier$D_IN; - wire rg_ier$EN; - - // register rg_lcr - reg [7 : 0] rg_lcr; - wire [7 : 0] rg_lcr$D_IN; - wire rg_lcr$EN; - - // register rg_lsr - reg [7 : 0] rg_lsr; - reg [7 : 0] rg_lsr$D_IN; - wire rg_lsr$EN; - - // register rg_mcr - reg [7 : 0] rg_mcr; - wire [7 : 0] rg_mcr$D_IN; - wire rg_mcr$EN; - - // register rg_msr - reg [7 : 0] rg_msr; - wire [7 : 0] rg_msr$D_IN; - wire rg_msr$EN; - - // register rg_rbr - reg [7 : 0] rg_rbr; - wire [7 : 0] rg_rbr$D_IN; - wire rg_rbr$EN; - - // register rg_scr - reg [7 : 0] rg_scr; - wire [7 : 0] rg_scr$D_IN; - wire rg_scr$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_thr - reg [7 : 0] rg_thr; - wire [7 : 0] rg_thr$D_IN; - wire rg_thr$EN; - - // ports of submodule f_from_console - wire [7 : 0] f_from_console$D_IN, f_from_console$D_OUT; - wire f_from_console$CLR, - f_from_console$DEQ, - f_from_console$EMPTY_N, - f_from_console$ENQ, - f_from_console$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_to_console - wire [7 : 0] f_to_console$D_IN, f_to_console$D_OUT; - wire f_to_console$CLR, - f_to_console$DEQ, - f_to_console$EMPTY_N, - f_to_console$ENQ, - f_to_console$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_receive, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_receive, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_rg_lsr$write_1__VAL_3; - wire MUX_rg_lsr$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2519; - reg [31 : 0] v__h2187; - reg [31 : 0] v__h2025; - reg [31 : 0] v__h2898; - reg [31 : 0] v__h3244; - reg [31 : 0] v__h4006; - reg [31 : 0] v__h3449; - reg [31 : 0] v__h4306; - reg [31 : 0] v__h4749; - reg [31 : 0] v__h4859; - reg [31 : 0] v__h1811; - reg [31 : 0] v__h1805; - reg [31 : 0] v__h2019; - reg [31 : 0] v__h2181; - reg [31 : 0] v__h2513; - reg [31 : 0] v__h2892; - reg [31 : 0] v__h3238; - reg [31 : 0] v__h3443; - reg [31 : 0] v__h4000; - reg [31 : 0] v__h4300; - reg [31 : 0] v__h4743; - reg [31 : 0] v__h4853; - // synopsys translate_on - - // remaining internal signals - reg [7 : 0] y_avValue_snd__h2683; - wire [63 : 0] rdata__h2759, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133; - wire [7 : 0] fn_iir__h1356, - new_lsr__h4516, - x__h2797, - y_avValue_snd__h2696, - y_avValue_snd__h2709, - y_avValue_snd__h2724, - y_avValue_snd__h2738; - wire [1 : 0] rdr_rresp__h2792, - v__h3147, - v__h3395, - v__h3575, - y_avValue_fst__h2737, - y_avValue_fst__h2751; - wire NOT_cfg_verbosity_read_ULE_1_24___d125, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188, - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method get_to_console_get - assign get_to_console_get = f_to_console$D_OUT ; - assign RDY_get_to_console_get = f_to_console$EMPTY_N ; - assign CAN_FIRE_get_to_console_get = f_to_console$EMPTY_N ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = f_from_console$FULL_N ; - assign CAN_FIRE_put_from_console_put = f_from_console$FULL_N ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method intr - assign intr = !fn_iir__h1356[0] ; - - // submodule f_from_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_from_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_from_console$D_IN), - .ENQ(f_from_console$ENQ), - .DEQ(f_from_console$DEQ), - .CLR(f_from_console$CLR), - .D_OUT(f_from_console$D_OUT), - .FULL_N(f_from_console$FULL_N), - .EMPTY_N(f_from_console$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_to_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_to_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_to_console$D_IN), - .ENQ(f_to_console$ENQ), - .DEQ(f_to_console$DEQ), - .CLR(f_to_console$CLR), - .D_OUT(f_to_console$D_OUT), - .FULL_N(f_to_console$FULL_N), - .EMPTY_N(f_to_console$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 && - rg_state ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_receive - assign CAN_FIRE_RL_rl_receive = f_from_console$EMPTY_N && !rg_lsr[0] ; - assign WILL_FIRE_RL_rl_receive = - CAN_FIRE_RL_rl_receive && !WILL_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_rg_lsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 ; - assign MUX_rg_lsr$write_1__VAL_3 = { rg_lsr[7:1], 1'd0 } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 8'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_dll - assign rg_dll$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dll$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 || - WILL_FIRE_RL_rl_reset ; - - // register rg_dlm - assign rg_dlm$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dlm$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 || - WILL_FIRE_RL_rl_reset ; - - // register rg_fcr - assign rg_fcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_fcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h2 || - WILL_FIRE_RL_rl_reset ; - - // register rg_ier - assign rg_ier$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_ier$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lcr - assign rg_lcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_lcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h3 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lsr - always@(WILL_FIRE_RL_rl_reset or - WILL_FIRE_RL_rl_receive or - new_lsr__h4516 or - MUX_rg_lsr$write_1__SEL_3 or MUX_rg_lsr$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset: rg_lsr$D_IN = 8'd96; - WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h4516; - MUX_rg_lsr$write_1__SEL_3: rg_lsr$D_IN = MUX_rg_lsr$write_1__VAL_3; - default: rg_lsr$D_IN = 8'b10101010 /* unspecified value */ ; - endcase - assign rg_lsr$EN = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 || - WILL_FIRE_RL_rl_receive || - WILL_FIRE_RL_rl_reset ; - - // register rg_mcr - assign rg_mcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_mcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h4 || - WILL_FIRE_RL_rl_reset ; - - // register rg_msr - assign rg_msr$D_IN = 8'd0 ; - assign rg_msr$EN = CAN_FIRE_RL_rl_reset ; - - // register rg_rbr - assign rg_rbr$D_IN = f_from_console$D_OUT ; - assign rg_rbr$EN = WILL_FIRE_RL_rl_receive ; - - // register rg_scr - assign rg_scr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_scr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h7 || - WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = 1'd1 ; - assign rg_state$EN = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // register rg_thr - assign rg_thr$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_thr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - - // submodule f_from_console - assign f_from_console$D_IN = put_from_console_put ; - assign f_from_console$ENQ = EN_put_from_console_put ; - assign f_from_console$DEQ = WILL_FIRE_RL_rl_receive ; - assign f_from_console$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_to_console - assign f_to_console$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign f_to_console$ENQ = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - assign f_to_console$DEQ = EN_get_to_console_get ; - assign f_to_console$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h2759, - rdr_rresp__h2792, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3147 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_24___d125 = cfg_verbosity > 8'd1 ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - slave_xactor_f_wr_data$D_OUT[0] ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - !slave_xactor_f_wr_data$D_OUT[0] ; - assign fn_iir__h1356 = - (rg_ier[0] && rg_lsr[0]) ? 8'h04 : (rg_ier[1] ? 8'h02 : 8'd0) ; - assign new_lsr__h4516 = { rg_lsr[7:1], 1'd1 } ; - assign rdata__h2759 = { 56'd0, x__h2797 } ; - assign rdr_rresp__h2792 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0) ? - y_avValue_fst__h2751 : - 2'b10 ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 = - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - rg_lcr[7] ; - assign slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 = - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1] || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7] || - f_to_console$FULL_N) ; - assign v__h3147 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) ? - 2'b10 : - v__h3395 ; - assign v__h3395 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0) ? - v__h3575 : - 2'b11 ; - assign v__h3575 = y_avValue_fst__h2737 ; - assign x__h2797 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0 || - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) ? - 8'd0 : - y_avValue_snd__h2738 ; - assign y_avValue_fst__h2737 = 2'b0 ; - assign y_avValue_fst__h2751 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0) ? - y_avValue_fst__h2737 : - 2'b11 ; - assign y_avValue_snd__h2696 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - rg_lcr[7]) ? - rg_dlm : - y_avValue_snd__h2683 ; - assign y_avValue_snd__h2709 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - !rg_lcr[7]) ? - rg_ier : - y_avValue_snd__h2696 ; - assign y_avValue_snd__h2724 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - rg_lcr[7]) ? - rg_dll : - y_avValue_snd__h2709 ; - assign y_avValue_snd__h2738 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7]) ? - rg_rbr : - y_avValue_snd__h2724 ; - always@(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 or - fn_iir__h1356 or rg_lcr or rg_mcr or rg_lsr or rg_msr or rg_scr) - begin - case (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3]) - 3'h2: y_avValue_snd__h2683 = fn_iir__h1356; - 3'h3: y_avValue_snd__h2683 = rg_lcr; - 3'h4: y_avValue_snd__h2683 = rg_mcr; - 3'h5: y_avValue_snd__h2683 = rg_lsr; - 3'h6: y_avValue_snd__h2683 = rg_msr; - 3'h7: y_avValue_snd__h2683 = rg_scr; - default: y_avValue_snd__h2683 = 8'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dll <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dlm <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_fcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_ier <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lsr <= `BSV_ASSIGNMENT_DELAY 8'd96; - rg_mcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_msr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_scr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_dll$EN) rg_dll <= `BSV_ASSIGNMENT_DELAY rg_dll$D_IN; - if (rg_dlm$EN) rg_dlm <= `BSV_ASSIGNMENT_DELAY rg_dlm$D_IN; - if (rg_fcr$EN) rg_fcr <= `BSV_ASSIGNMENT_DELAY rg_fcr$D_IN; - if (rg_ier$EN) rg_ier <= `BSV_ASSIGNMENT_DELAY rg_ier$D_IN; - if (rg_lcr$EN) rg_lcr <= `BSV_ASSIGNMENT_DELAY rg_lcr$D_IN; - if (rg_lsr$EN) rg_lsr <= `BSV_ASSIGNMENT_DELAY rg_lsr$D_IN; - if (rg_mcr$EN) rg_mcr <= `BSV_ASSIGNMENT_DELAY rg_mcr$D_IN; - if (rg_msr$EN) rg_msr <= `BSV_ASSIGNMENT_DELAY rg_msr$D_IN; - if (rg_scr$EN) rg_scr <= `BSV_ASSIGNMENT_DELAY rg_scr$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_rbr$EN) rg_rbr <= `BSV_ASSIGNMENT_DELAY rg_rbr$D_IN; - if (rg_thr$EN) rg_thr <= `BSV_ASSIGNMENT_DELAY rg_thr$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 8'hAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_dll = 8'hAA; - rg_dlm = 8'hAA; - rg_fcr = 8'hAA; - rg_ier = 8'hAA; - rg_lcr = 8'hAA; - rg_lsr = 8'hAA; - rg_mcr = 8'hAA; - rg_msr = 8'hAA; - rg_rbr = 8'hAA; - rg_scr = 8'hAA; - rg_state = 1'h0; - rg_thr = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - begin - v__h2519 = $stime; - #0; - end - v__h2513 = v__h2519 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2513); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - begin - v__h2187 = $stime; - #0; - end - v__h2181 = v__h2187 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2181); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - begin - v__h2025 = $stime; - #0; - end - v__h2019 = v__h2025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: misaligned addr", - v__h2019); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h2898 = $stime; - #0; - end - v__h2892 = v__h2898 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_rd_req", v__h2892); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdata__h2759); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdr_rresp__h2792); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - begin - v__h3244 = $stime; - #0; - end - v__h3238 = v__h3244 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $display("%0d: ERROR: UART.rl_process_wr_req: misaligned addr", - v__h3238); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - begin - v__h4006 = $stime; - #0; - end - v__h4000 = v__h4006 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h4000); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - begin - v__h3449 = $stime; - #0; - end - v__h3443 = v__h3449 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h3443); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h4306 = $stime; - #0; - end - v__h4300 = v__h4306 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_wr_req", v__h4300); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", v__h3147); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h4749 = $stime; - #0; - end - v__h4743 = v__h4749 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_base 0x%0h is not 8-Byte-aligned", - v__h4743, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h4859 = $stime; - #0; - end - v__h4853 = v__h4859 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_lim 0x%0h is not 8-Byte-aligned", - v__h4853, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_receive && NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("UART_Model.rl_receive: received char 0x%0h; new_lsr = 0x%0h", - f_from_console$D_OUT, - new_lsr__h4516); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - begin - v__h1811 = $stime; - #0; - end - v__h1805 = v__h1811 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - $display("%0d: UART.rl_reset", v__h1805); - end - // synopsys translate_on -endmodule // mkUART - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v deleted file mode 100644 index 1cb3bfa4..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v +++ /dev/null @@ -1,1415 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// from_master_awready O 1 reg -// from_master_wready O 1 reg -// from_master_bvalid O 1 reg -// from_master_bid O 4 reg -// from_master_bresp O 2 reg -// from_master_arready O 1 reg -// from_master_rvalid O 1 reg -// from_master_rid O 4 reg -// from_master_rdata O 64 reg -// from_master_rresp O 2 reg -// from_master_rlast O 1 reg -// to_slave_awvalid O 1 reg -// to_slave_awid O 4 reg -// to_slave_awaddr O 64 reg -// to_slave_awlen O 8 reg -// to_slave_awsize O 3 reg -// to_slave_awburst O 2 reg -// to_slave_awlock O 1 reg -// to_slave_awcache O 4 reg -// to_slave_awprot O 3 reg -// to_slave_awqos O 4 reg -// to_slave_awregion O 4 reg -// to_slave_wvalid O 1 reg -// to_slave_wid O 4 reg -// to_slave_wdata O 64 reg -// to_slave_wstrb O 8 reg -// to_slave_wlast O 1 reg -// to_slave_bready O 1 reg -// to_slave_arvalid O 1 reg -// to_slave_arid O 4 reg -// to_slave_araddr O 64 reg -// to_slave_arlen O 8 reg -// to_slave_arsize O 3 reg -// to_slave_arburst O 2 reg -// to_slave_arlock O 1 reg -// to_slave_arcache O 4 reg -// to_slave_arprot O 3 reg -// to_slave_arqos O 4 reg -// to_slave_arregion O 4 reg -// to_slave_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// from_master_awvalid I 1 -// from_master_awid I 4 reg -// from_master_awaddr I 64 reg -// from_master_awlen I 8 reg -// from_master_awsize I 3 reg -// from_master_awburst I 2 reg -// from_master_awlock I 1 reg -// from_master_awcache I 4 reg -// from_master_awprot I 3 reg -// from_master_awqos I 4 reg -// from_master_awregion I 4 reg -// from_master_wvalid I 1 -// from_master_wid I 4 reg -// from_master_wdata I 64 reg -// from_master_wstrb I 8 reg -// from_master_wlast I 1 reg -// from_master_bready I 1 -// from_master_arvalid I 1 -// from_master_arid I 4 reg -// from_master_araddr I 64 reg -// from_master_arlen I 8 reg -// from_master_arsize I 3 reg -// from_master_arburst I 2 reg -// from_master_arlock I 1 reg -// from_master_arcache I 4 reg -// from_master_arprot I 3 reg -// from_master_arqos I 4 reg -// from_master_arregion I 4 reg -// from_master_rready I 1 -// to_slave_awready I 1 -// to_slave_wready I 1 -// to_slave_bvalid I 1 -// to_slave_bid I 4 reg -// to_slave_bresp I 2 reg -// to_slave_arready I 1 -// to_slave_rvalid I 1 -// to_slave_rid I 4 reg -// to_slave_rdata I 64 reg -// to_slave_rresp I 2 reg -// to_slave_rlast I 1 reg -// EN_reset I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkAXI4_Deburster_A(CLK, - RST_N, - - EN_reset, - RDY_reset, - - from_master_awvalid, - from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion, - - from_master_awready, - - from_master_wvalid, - from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast, - - from_master_wready, - - from_master_bvalid, - - from_master_bid, - - from_master_bresp, - - from_master_bready, - - from_master_arvalid, - from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion, - - from_master_arready, - - from_master_rvalid, - - from_master_rid, - - from_master_rdata, - - from_master_rresp, - - from_master_rlast, - - from_master_rready, - - to_slave_awvalid, - - to_slave_awid, - - to_slave_awaddr, - - to_slave_awlen, - - to_slave_awsize, - - to_slave_awburst, - - to_slave_awlock, - - to_slave_awcache, - - to_slave_awprot, - - to_slave_awqos, - - to_slave_awregion, - - to_slave_awready, - - to_slave_wvalid, - - to_slave_wid, - - to_slave_wdata, - - to_slave_wstrb, - - to_slave_wlast, - - to_slave_wready, - - to_slave_bvalid, - to_slave_bid, - to_slave_bresp, - - to_slave_bready, - - to_slave_arvalid, - - to_slave_arid, - - to_slave_araddr, - - to_slave_arlen, - - to_slave_arsize, - - to_slave_arburst, - - to_slave_arlock, - - to_slave_arcache, - - to_slave_arprot, - - to_slave_arqos, - - to_slave_arregion, - - to_slave_arready, - - to_slave_rvalid, - to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast, - - to_slave_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method from_master_m_awvalid - input from_master_awvalid; - input [3 : 0] from_master_awid; - input [63 : 0] from_master_awaddr; - input [7 : 0] from_master_awlen; - input [2 : 0] from_master_awsize; - input [1 : 0] from_master_awburst; - input from_master_awlock; - input [3 : 0] from_master_awcache; - input [2 : 0] from_master_awprot; - input [3 : 0] from_master_awqos; - input [3 : 0] from_master_awregion; - - // value method from_master_m_awready - output from_master_awready; - - // action method from_master_m_wvalid - input from_master_wvalid; - input [3 : 0] from_master_wid; - input [63 : 0] from_master_wdata; - input [7 : 0] from_master_wstrb; - input from_master_wlast; - - // value method from_master_m_wready - output from_master_wready; - - // value method from_master_m_bvalid - output from_master_bvalid; - - // value method from_master_m_bid - output [3 : 0] from_master_bid; - - // value method from_master_m_bresp - output [1 : 0] from_master_bresp; - - // value method from_master_m_buser - - // action method from_master_m_bready - input from_master_bready; - - // action method from_master_m_arvalid - input from_master_arvalid; - input [3 : 0] from_master_arid; - input [63 : 0] from_master_araddr; - input [7 : 0] from_master_arlen; - input [2 : 0] from_master_arsize; - input [1 : 0] from_master_arburst; - input from_master_arlock; - input [3 : 0] from_master_arcache; - input [2 : 0] from_master_arprot; - input [3 : 0] from_master_arqos; - input [3 : 0] from_master_arregion; - - // value method from_master_m_arready - output from_master_arready; - - // value method from_master_m_rvalid - output from_master_rvalid; - - // value method from_master_m_rid - output [3 : 0] from_master_rid; - - // value method from_master_m_rdata - output [63 : 0] from_master_rdata; - - // value method from_master_m_rresp - output [1 : 0] from_master_rresp; - - // value method from_master_m_rlast - output from_master_rlast; - - // value method from_master_m_ruser - - // action method from_master_m_rready - input from_master_rready; - - // value method to_slave_m_awvalid - output to_slave_awvalid; - - // value method to_slave_m_awid - output [3 : 0] to_slave_awid; - - // value method to_slave_m_awaddr - output [63 : 0] to_slave_awaddr; - - // value method to_slave_m_awlen - output [7 : 0] to_slave_awlen; - - // value method to_slave_m_awsize - output [2 : 0] to_slave_awsize; - - // value method to_slave_m_awburst - output [1 : 0] to_slave_awburst; - - // value method to_slave_m_awlock - output to_slave_awlock; - - // value method to_slave_m_awcache - output [3 : 0] to_slave_awcache; - - // value method to_slave_m_awprot - output [2 : 0] to_slave_awprot; - - // value method to_slave_m_awqos - output [3 : 0] to_slave_awqos; - - // value method to_slave_m_awregion - output [3 : 0] to_slave_awregion; - - // value method to_slave_m_awuser - - // action method to_slave_m_awready - input to_slave_awready; - - // value method to_slave_m_wvalid - output to_slave_wvalid; - - // value method to_slave_m_wid - output [3 : 0] to_slave_wid; - - // value method to_slave_m_wdata - output [63 : 0] to_slave_wdata; - - // value method to_slave_m_wstrb - output [7 : 0] to_slave_wstrb; - - // value method to_slave_m_wlast - output to_slave_wlast; - - // value method to_slave_m_wuser - - // action method to_slave_m_wready - input to_slave_wready; - - // action method to_slave_m_bvalid - input to_slave_bvalid; - input [3 : 0] to_slave_bid; - input [1 : 0] to_slave_bresp; - - // value method to_slave_m_bready - output to_slave_bready; - - // value method to_slave_m_arvalid - output to_slave_arvalid; - - // value method to_slave_m_arid - output [3 : 0] to_slave_arid; - - // value method to_slave_m_araddr - output [63 : 0] to_slave_araddr; - - // value method to_slave_m_arlen - output [7 : 0] to_slave_arlen; - - // value method to_slave_m_arsize - output [2 : 0] to_slave_arsize; - - // value method to_slave_m_arburst - output [1 : 0] to_slave_arburst; - - // value method to_slave_m_arlock - output to_slave_arlock; - - // value method to_slave_m_arcache - output [3 : 0] to_slave_arcache; - - // value method to_slave_m_arprot - output [2 : 0] to_slave_arprot; - - // value method to_slave_m_arqos - output [3 : 0] to_slave_arqos; - - // value method to_slave_m_arregion - output [3 : 0] to_slave_arregion; - - // value method to_slave_m_aruser - - // action method to_slave_m_arready - input to_slave_arready; - - // action method to_slave_m_rvalid - input to_slave_rvalid; - input [3 : 0] to_slave_rid; - input [63 : 0] to_slave_rdata; - input [1 : 0] to_slave_rresp; - input to_slave_rlast; - - // value method to_slave_m_rready - output to_slave_rready; - - // signals for module outputs - wire [63 : 0] from_master_rdata, - to_slave_araddr, - to_slave_awaddr, - to_slave_wdata; - wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb; - wire [3 : 0] from_master_bid, - from_master_rid, - to_slave_arcache, - to_slave_arid, - to_slave_arqos, - to_slave_arregion, - to_slave_awcache, - to_slave_awid, - to_slave_awqos, - to_slave_awregion, - to_slave_wid; - wire [2 : 0] to_slave_arprot, - to_slave_arsize, - to_slave_awprot, - to_slave_awsize; - wire [1 : 0] from_master_bresp, - from_master_rresp, - to_slave_arburst, - to_slave_awburst; - wire RDY_reset, - from_master_arready, - from_master_awready, - from_master_bvalid, - from_master_rlast, - from_master_rvalid, - from_master_wready, - to_slave_arlock, - to_slave_arvalid, - to_slave_awlock, - to_slave_awvalid, - to_slave_bready, - to_slave_rready, - to_slave_wlast, - to_slave_wvalid; - - // register m_rg_ar_beat_count - reg [7 : 0] m_rg_ar_beat_count; - wire [7 : 0] m_rg_ar_beat_count$D_IN; - wire m_rg_ar_beat_count$EN; - - // register m_rg_b_beat_count - reg [7 : 0] m_rg_b_beat_count; - wire [7 : 0] m_rg_b_beat_count$D_IN; - wire m_rg_b_beat_count$EN; - - // register m_rg_b_resp - reg [1 : 0] m_rg_b_resp; - wire [1 : 0] m_rg_b_resp$D_IN; - wire m_rg_b_resp$EN; - - // register m_rg_r_beat_count - reg [7 : 0] m_rg_r_beat_count; - wire [7 : 0] m_rg_r_beat_count$D_IN; - wire m_rg_r_beat_count$EN; - - // register m_rg_reset - reg m_rg_reset; - wire m_rg_reset$D_IN, m_rg_reset$EN; - - // register m_rg_w_beat_count - reg [7 : 0] m_rg_w_beat_count; - wire [7 : 0] m_rg_w_beat_count$D_IN; - wire m_rg_w_beat_count$EN; - - // ports of submodule m_f_r_arlen - wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT; - wire m_f_r_arlen$CLR, - m_f_r_arlen$DEQ, - m_f_r_arlen$EMPTY_N, - m_f_r_arlen$ENQ, - m_f_r_arlen$FULL_N; - - // ports of submodule m_f_w_awlen - wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT; - wire m_f_w_awlen$CLR, - m_f_w_awlen$DEQ, - m_f_w_awlen$EMPTY_N, - m_f_w_awlen$ENQ, - m_f_w_awlen$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_addr - wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN, - m_xactor_from_master_f_rd_addr$D_OUT; - wire m_xactor_from_master_f_rd_addr$CLR, - m_xactor_from_master_f_rd_addr$DEQ, - m_xactor_from_master_f_rd_addr$EMPTY_N, - m_xactor_from_master_f_rd_addr$ENQ, - m_xactor_from_master_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_data - wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN, - m_xactor_from_master_f_rd_data$D_OUT; - wire m_xactor_from_master_f_rd_data$CLR, - m_xactor_from_master_f_rd_data$DEQ, - m_xactor_from_master_f_rd_data$EMPTY_N, - m_xactor_from_master_f_rd_data$ENQ, - m_xactor_from_master_f_rd_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_addr - wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN, - m_xactor_from_master_f_wr_addr$D_OUT; - wire m_xactor_from_master_f_wr_addr$CLR, - m_xactor_from_master_f_wr_addr$DEQ, - m_xactor_from_master_f_wr_addr$EMPTY_N, - m_xactor_from_master_f_wr_addr$ENQ, - m_xactor_from_master_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_data - wire [76 : 0] m_xactor_from_master_f_wr_data$D_IN, - m_xactor_from_master_f_wr_data$D_OUT; - wire m_xactor_from_master_f_wr_data$CLR, - m_xactor_from_master_f_wr_data$DEQ, - m_xactor_from_master_f_wr_data$EMPTY_N, - m_xactor_from_master_f_wr_data$ENQ, - m_xactor_from_master_f_wr_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_resp - wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN, - m_xactor_from_master_f_wr_resp$D_OUT; - wire m_xactor_from_master_f_wr_resp$CLR, - m_xactor_from_master_f_wr_resp$DEQ, - m_xactor_from_master_f_wr_resp$EMPTY_N, - m_xactor_from_master_f_wr_resp$ENQ, - m_xactor_from_master_f_wr_resp$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_addr - wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN, - m_xactor_to_slave_f_rd_addr$D_OUT; - wire m_xactor_to_slave_f_rd_addr$CLR, - m_xactor_to_slave_f_rd_addr$DEQ, - m_xactor_to_slave_f_rd_addr$EMPTY_N, - m_xactor_to_slave_f_rd_addr$ENQ, - m_xactor_to_slave_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_data - wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN, - m_xactor_to_slave_f_rd_data$D_OUT; - wire m_xactor_to_slave_f_rd_data$CLR, - m_xactor_to_slave_f_rd_data$DEQ, - m_xactor_to_slave_f_rd_data$EMPTY_N, - m_xactor_to_slave_f_rd_data$ENQ, - m_xactor_to_slave_f_rd_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_addr - wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN, - m_xactor_to_slave_f_wr_addr$D_OUT; - wire m_xactor_to_slave_f_wr_addr$CLR, - m_xactor_to_slave_f_wr_addr$DEQ, - m_xactor_to_slave_f_wr_addr$EMPTY_N, - m_xactor_to_slave_f_wr_addr$ENQ, - m_xactor_to_slave_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_data - wire [76 : 0] m_xactor_to_slave_f_wr_data$D_IN, - m_xactor_to_slave_f_wr_data$D_OUT; - wire m_xactor_to_slave_f_wr_data$CLR, - m_xactor_to_slave_f_wr_data$DEQ, - m_xactor_to_slave_f_wr_data$EMPTY_N, - m_xactor_to_slave_f_wr_data$ENQ, - m_xactor_to_slave_f_wr_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_resp - wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN, - m_xactor_to_slave_f_wr_resp$D_OUT; - wire m_xactor_to_slave_f_wr_resp$CLR, - m_xactor_to_slave_f_wr_resp$DEQ, - m_xactor_to_slave_f_wr_resp$EMPTY_N, - m_xactor_to_slave_f_wr_resp$ENQ, - m_xactor_to_slave_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave, - CAN_FIRE_from_master_m_arvalid, - CAN_FIRE_from_master_m_awvalid, - CAN_FIRE_from_master_m_bready, - CAN_FIRE_from_master_m_rready, - CAN_FIRE_from_master_m_wvalid, - CAN_FIRE_reset, - CAN_FIRE_to_slave_m_arready, - CAN_FIRE_to_slave_m_awready, - CAN_FIRE_to_slave_m_bvalid, - CAN_FIRE_to_slave_m_rvalid, - CAN_FIRE_to_slave_m_wready, - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave, - WILL_FIRE_from_master_m_arvalid, - WILL_FIRE_from_master_m_awvalid, - WILL_FIRE_from_master_m_bready, - WILL_FIRE_from_master_m_rready, - WILL_FIRE_from_master_m_wvalid, - WILL_FIRE_reset, - WILL_FIRE_to_slave_m_arready, - WILL_FIRE_to_slave_m_awready, - WILL_FIRE_to_slave_m_bvalid, - WILL_FIRE_to_slave_m_rvalid, - WILL_FIRE_to_slave_m_wready; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2, - MUX_m_rg_b_beat_count$write_1__VAL_2, - MUX_m_rg_r_beat_count$write_1__VAL_2, - MUX_m_rg_w_beat_count$write_1__VAL_2; - wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2; - wire MUX_m_rg_b_resp$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2430; - reg [31 : 0] v__h1446; - reg [31 : 0] v__h1440; - reg [31 : 0] v__h2424; - // synopsys translate_on - - // remaining internal signals - wire [63 : 0] a_out_araddr__h2944, - a_out_awaddr__h1951, - addr___1__h2036, - addr___1__h3029; - wire [7 : 0] x__h2305, x__h2798, x__h3190, x__h3388; - wire m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95, - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51, - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106, - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35; - - // action method reset - assign RDY_reset = !m_rg_reset ; - assign CAN_FIRE_reset = !m_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method from_master_m_awvalid - assign CAN_FIRE_from_master_m_awvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_awvalid = 1'd1 ; - - // value method from_master_m_awready - assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ; - - // action method from_master_m_wvalid - assign CAN_FIRE_from_master_m_wvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_wvalid = 1'd1 ; - - // value method from_master_m_wready - assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ; - - // value method from_master_m_bvalid - assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ; - - // value method from_master_m_bid - assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ; - - // value method from_master_m_bresp - assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ; - - // action method from_master_m_bready - assign CAN_FIRE_from_master_m_bready = 1'd1 ; - assign WILL_FIRE_from_master_m_bready = 1'd1 ; - - // action method from_master_m_arvalid - assign CAN_FIRE_from_master_m_arvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_arvalid = 1'd1 ; - - // value method from_master_m_arready - assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ; - - // value method from_master_m_rvalid - assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ; - - // value method from_master_m_rid - assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ; - - // value method from_master_m_rdata - assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ; - - // value method from_master_m_rresp - assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ; - - // value method from_master_m_rlast - assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ; - - // action method from_master_m_rready - assign CAN_FIRE_from_master_m_rready = 1'd1 ; - assign WILL_FIRE_from_master_m_rready = 1'd1 ; - - // value method to_slave_m_awvalid - assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ; - - // value method to_slave_m_awid - assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ; - - // value method to_slave_m_awaddr - assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ; - - // value method to_slave_m_awlen - assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ; - - // value method to_slave_m_awsize - assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ; - - // value method to_slave_m_awburst - assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ; - - // value method to_slave_m_awlock - assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ; - - // value method to_slave_m_awcache - assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ; - - // value method to_slave_m_awprot - assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ; - - // value method to_slave_m_awqos - assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ; - - // value method to_slave_m_awregion - assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ; - - // action method to_slave_m_awready - assign CAN_FIRE_to_slave_m_awready = 1'd1 ; - assign WILL_FIRE_to_slave_m_awready = 1'd1 ; - - // value method to_slave_m_wvalid - assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ; - - // value method to_slave_m_wid - assign to_slave_wid = m_xactor_to_slave_f_wr_data$D_OUT[76:73] ; - - // value method to_slave_m_wdata - assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ; - - // value method to_slave_m_wstrb - assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ; - - // value method to_slave_m_wlast - assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ; - - // action method to_slave_m_wready - assign CAN_FIRE_to_slave_m_wready = 1'd1 ; - assign WILL_FIRE_to_slave_m_wready = 1'd1 ; - - // action method to_slave_m_bvalid - assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ; - - // value method to_slave_m_bready - assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ; - - // value method to_slave_m_arvalid - assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ; - - // value method to_slave_m_arid - assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ; - - // value method to_slave_m_araddr - assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ; - - // value method to_slave_m_arlen - assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ; - - // value method to_slave_m_arsize - assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ; - - // value method to_slave_m_arburst - assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ; - - // value method to_slave_m_arlock - assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ; - - // value method to_slave_m_arcache - assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ; - - // value method to_slave_m_arprot - assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ; - - // value method to_slave_m_arqos - assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ; - - // value method to_slave_m_arregion - assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ; - - // action method to_slave_m_arready - assign CAN_FIRE_to_slave_m_arready = 1'd1 ; - assign WILL_FIRE_to_slave_m_arready = 1'd1 ; - - // action method to_slave_m_rvalid - assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ; - - // value method to_slave_m_rready - assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ; - - // submodule m_f_r_arlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_r_arlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_r_arlen$D_IN), - .ENQ(m_f_r_arlen$ENQ), - .DEQ(m_f_r_arlen$DEQ), - .CLR(m_f_r_arlen$CLR), - .D_OUT(m_f_r_arlen$D_OUT), - .FULL_N(m_f_r_arlen$FULL_N), - .EMPTY_N(m_f_r_arlen$EMPTY_N)); - - // submodule m_f_w_awlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_w_awlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_w_awlen$D_IN), - .ENQ(m_f_w_awlen$ENQ), - .DEQ(m_f_w_awlen$DEQ), - .CLR(m_f_w_awlen$CLR), - .D_OUT(m_f_w_awlen$D_OUT), - .FULL_N(m_f_w_awlen$FULL_N), - .EMPTY_N(m_f_w_awlen$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_addr$D_IN), - .ENQ(m_xactor_from_master_f_rd_addr$ENQ), - .DEQ(m_xactor_from_master_f_rd_addr$DEQ), - .CLR(m_xactor_from_master_f_rd_addr$CLR), - .D_OUT(m_xactor_from_master_f_rd_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_data$D_IN), - .ENQ(m_xactor_from_master_f_rd_data$ENQ), - .DEQ(m_xactor_from_master_f_rd_data$DEQ), - .CLR(m_xactor_from_master_f_rd_data$CLR), - .D_OUT(m_xactor_from_master_f_rd_data$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_addr$D_IN), - .ENQ(m_xactor_from_master_f_wr_addr$ENQ), - .DEQ(m_xactor_from_master_f_wr_addr$DEQ), - .CLR(m_xactor_from_master_f_wr_addr$CLR), - .D_OUT(m_xactor_from_master_f_wr_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_data$D_IN), - .ENQ(m_xactor_from_master_f_wr_data$ENQ), - .DEQ(m_xactor_from_master_f_wr_data$DEQ), - .CLR(m_xactor_from_master_f_wr_data$CLR), - .D_OUT(m_xactor_from_master_f_wr_data$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_resp$D_IN), - .ENQ(m_xactor_from_master_f_wr_resp$ENQ), - .DEQ(m_xactor_from_master_f_wr_resp$DEQ), - .CLR(m_xactor_from_master_f_wr_resp$CLR), - .D_OUT(m_xactor_from_master_f_wr_resp$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_addr$D_IN), - .ENQ(m_xactor_to_slave_f_rd_addr$ENQ), - .DEQ(m_xactor_to_slave_f_rd_addr$DEQ), - .CLR(m_xactor_to_slave_f_rd_addr$CLR), - .D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_data$D_IN), - .ENQ(m_xactor_to_slave_f_rd_data$ENQ), - .DEQ(m_xactor_to_slave_f_rd_data$DEQ), - .CLR(m_xactor_to_slave_f_rd_data$CLR), - .D_OUT(m_xactor_to_slave_f_rd_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_addr$D_IN), - .ENQ(m_xactor_to_slave_f_wr_addr$ENQ), - .DEQ(m_xactor_to_slave_f_wr_addr$DEQ), - .CLR(m_xactor_to_slave_f_wr_addr$CLR), - .D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_data$D_IN), - .ENQ(m_xactor_to_slave_f_wr_data$ENQ), - .DEQ(m_xactor_to_slave_f_wr_data$DEQ), - .CLR(m_xactor_to_slave_f_wr_data$CLR), - .D_OUT(m_xactor_to_slave_f_wr_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_resp$D_IN), - .ENQ(m_xactor_to_slave_f_wr_resp$ENQ), - .DEQ(m_xactor_to_slave_f_wr_resp$DEQ), - .CLR(m_xactor_to_slave_f_wr_resp$CLR), - .D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave = - m_xactor_to_slave_f_wr_addr$FULL_N && - m_xactor_from_master_f_wr_addr$EMPTY_N && - m_xactor_to_slave_f_wr_data$FULL_N && - m_xactor_from_master_f_wr_data$EMPTY_N && - (m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - - // rule RL_m_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master = - m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N && - (m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 || - m_xactor_from_master_f_wr_resp$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - - // rule RL_m_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave = - m_xactor_to_slave_f_rd_addr$FULL_N && - m_xactor_from_master_f_rd_addr$EMPTY_N && - (m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - - // rule RL_m_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master = - m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N && - m_xactor_from_master_f_rd_data$FULL_N ; - assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ; - assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_b_resp$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - (m_rg_b_resp == 2'b0 && - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 || - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51) ; - assign MUX_m_rg_ar_beat_count$write_1__VAL_2 = - m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ? - x__h3190 : - 8'd0 ; - assign MUX_m_rg_b_beat_count$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - x__h2798 : - 8'd0 ; - assign MUX_m_rg_b_resp$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - 2'b0 ; - assign MUX_m_rg_r_beat_count$write_1__VAL_2 = - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ? - x__h3388 : - 8'd0 ; - assign MUX_m_rg_w_beat_count$write_1__VAL_2 = - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ? - x__h2305 : - 8'd0 ; - - // register m_rg_ar_beat_count - assign m_rg_ar_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ; - assign m_rg_ar_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ; - - // register m_rg_b_beat_count - assign m_rg_b_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ; - assign m_rg_b_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ; - - // register m_rg_b_resp - assign m_rg_b_resp$D_IN = - m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ; - assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ; - - // register m_rg_r_beat_count - assign m_rg_r_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ; - assign m_rg_r_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ; - - // register m_rg_reset - assign m_rg_reset$D_IN = !m_rg_reset ; - assign m_rg_reset$EN = m_rg_reset || EN_reset ; - - // register m_rg_w_beat_count - assign m_rg_w_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ; - assign m_rg_w_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ; - - // submodule m_f_r_arlen - assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_f_r_arlen$ENQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - m_rg_ar_beat_count == 8'd0 ; - assign m_f_r_arlen$DEQ = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master && - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ; - assign m_f_r_arlen$CLR = m_rg_reset ; - - // submodule m_f_w_awlen - assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign m_f_w_awlen$ENQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - m_rg_w_beat_count == 8'd0 ; - assign m_f_w_awlen$DEQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_f_w_awlen$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_addr - assign m_xactor_from_master_f_rd_addr$D_IN = - { from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion } ; - assign m_xactor_from_master_f_rd_addr$ENQ = - from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ; - assign m_xactor_from_master_f_rd_addr$DEQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - !m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ; - assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_data - assign m_xactor_from_master_f_rd_data$D_IN = - { m_xactor_to_slave_f_rd_data$D_OUT[70:1], - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 } ; - assign m_xactor_from_master_f_rd_data$ENQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_from_master_f_rd_data$DEQ = - from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ; - assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_addr - assign m_xactor_from_master_f_wr_addr$D_IN = - { from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion } ; - assign m_xactor_from_master_f_wr_addr$ENQ = - from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ; - assign m_xactor_from_master_f_wr_addr$DEQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ; - assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_data - assign m_xactor_from_master_f_wr_data$D_IN = - { from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast } ; - assign m_xactor_from_master_f_wr_data$ENQ = - from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ; - assign m_xactor_from_master_f_wr_data$DEQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_resp - assign m_xactor_from_master_f_wr_resp$D_IN = - { m_xactor_to_slave_f_wr_resp$D_OUT[5:2], - (m_rg_b_resp == 2'b0) ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - m_rg_b_resp } ; - assign m_xactor_from_master_f_wr_resp$ENQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_xactor_from_master_f_wr_resp$DEQ = - from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ; - assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_addr - assign m_xactor_to_slave_f_rd_addr$D_IN = - { m_xactor_from_master_f_rd_addr$D_OUT[96:93], - a_out_araddr__h2944, - 8'd0, - m_xactor_from_master_f_rd_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_rd_addr$ENQ = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - assign m_xactor_to_slave_f_rd_addr$DEQ = - m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ; - assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_data - assign m_xactor_to_slave_f_rd_data$D_IN = - { to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast } ; - assign m_xactor_to_slave_f_rd_data$ENQ = - to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ; - assign m_xactor_to_slave_f_rd_data$DEQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_addr - assign m_xactor_to_slave_f_wr_addr$D_IN = - { m_xactor_from_master_f_wr_addr$D_OUT[96:93], - a_out_awaddr__h1951, - 8'd0, - m_xactor_from_master_f_wr_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_wr_addr$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_addr$DEQ = - m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ; - assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_data - assign m_xactor_to_slave_f_wr_data$D_IN = - { m_xactor_from_master_f_wr_data$D_OUT[76:1], 1'd1 } ; - assign m_xactor_to_slave_f_wr_data$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_data$DEQ = - m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ; - assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_resp - assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ; - assign m_xactor_to_slave_f_wr_resp$ENQ = - to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ; - assign m_xactor_to_slave_f_wr_resp$DEQ = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ; - - // remaining internal signals - assign a_out_araddr__h2944 = - (m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h3029 : - m_xactor_from_master_f_rd_addr$D_OUT[92:29] ; - assign a_out_awaddr__h1951 = - (m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h2036 : - m_xactor_from_master_f_wr_addr$D_OUT[92:29] ; - assign addr___1__h2036 = - m_xactor_from_master_f_wr_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_w_beat_count } << - m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ; - assign addr___1__h3029 = - m_xactor_from_master_f_rd_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_ar_beat_count } << - m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ; - assign m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 = - m_rg_ar_beat_count < - m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 = - m_rg_b_beat_count < m_f_w_awlen$D_OUT ; - assign m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 = - m_rg_r_beat_count < m_f_r_arlen$D_OUT ; - assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 = - m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign x__h2305 = m_rg_w_beat_count + 8'd1 ; - assign x__h2798 = m_rg_b_beat_count + 8'd1 ; - assign x__h3190 = m_rg_ar_beat_count + 8'd1 ; - assign x__h3388 = m_rg_r_beat_count + 8'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0; - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (m_rg_ar_beat_count$EN) - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN; - if (m_rg_b_beat_count$EN) - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN; - if (m_rg_b_resp$EN) - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN; - if (m_rg_r_beat_count$EN) - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN; - if (m_rg_reset$EN) - m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN; - if (m_rg_w_beat_count$EN) - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_ar_beat_count = 8'hAA; - m_rg_b_beat_count = 8'hAA; - m_rg_b_resp = 2'h2; - m_rg_r_beat_count = 8'hAA; - m_rg_reset = 1'h0; - m_rg_w_beat_count = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - begin - v__h2430 = $stime; - #0; - end - v__h2424 = v__h2430 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", - v__h2424); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display(" WLAST not set on last data beat (awlen = %0d)", - m_xactor_from_master_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) - begin - v__h1446 = $stime; - #0; - end - v__h1440 = v__h1446 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) $display("%0d: %m::AXI4_Deburster.rl_reset", v__h1440); - end - // synopsys translate_on -endmodule // mkAXI4_Deburster_A - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v deleted file mode 100644 index 41b42457..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v +++ /dev/null @@ -1,2157 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkBoot_ROM(CLK, - RST_N, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready); - input CLK; - input RST_N; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_set_addr_map, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_module_ready - reg rg_module_ready; - wire rg_module_ready$D_IN, rg_module_ready$EN; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h808; - reg [31 : 0] v__h8928; - reg [31 : 0] v__h9221; - reg [31 : 0] v__h9331; - reg [31 : 0] v__h802; - reg [31 : 0] v__h8922; - reg [31 : 0] v__h9215; - reg [31 : 0] v__h9325; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] data64__h987; - reg [31 : 0] CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2; - wire [63 : 0] byte_addr__h705, rdata__h924; - wire [1 : 0] rdr_rresp__h957; - wire NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18, - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_module_ready - assign rg_module_ready$D_IN = 1'd1 ; - assign rg_module_ready$EN = EN_set_addr_map ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h924, - rdr_rresp__h957, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 ? - 2'b10 : - 2'b0 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = 1'b0 ; - - // remaining internal signals - assign NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 = - slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] || - slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ; - assign NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 = - slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] || - slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ; - assign byte_addr__h705 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign rdata__h924 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 64'd0 : - data64__h987 ; - assign rdr_rresp__h957 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 2'b10 : - 2'b0 ; - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16, - 64'd24, - 64'd56, - 64'd72, - 64'd80, - 64'd88, - 64'd200, - 64'd232, - 64'd312, - 64'd424, - 64'd448, - 64'd600, - 64'd728, - 64'd1136, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = 32'h0; - 64'd32: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h54040000; - 64'd40: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h88030000; - 64'd48: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h11000000; - 64'd64: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h50030000; - 64'd96, - 64'd112, - 64'd208, - 64'd224, - 64'd240, - 64'd432, - 64'd488, - 64'd872, - 64'd888: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h04000000; - 64'd104, 64'd120, 64'd504, 64'd792, 64'd920: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h02000000; - 64'd128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h16000000; - 64'd136: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h62626375; - 64'd144: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656B6970; - 64'd152: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65642D65; - 64'd160, - 64'd264, - 64'd280, - 64'd296, - 64'd336, - 64'd360, - 64'd384, - 64'd456, - 64'd552, - 64'd592, - 64'd608, - 64'd624, - 64'd672, - 64'd704, - 64'd760, - 64'd816, - 64'd840, - 64'd880: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h03000000; - 64'd168: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h26000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h732C7261; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7261622D; - 64'd192, - 64'd216, - 64'd400, - 64'd440, - 64'd496, - 64'd512, - 64'd584, - 64'd744, - 64'd752, - 64'd912: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h01000000; - 64'd248, 64'd896: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h80969800; - 64'd256: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40757063; - 64'd272: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h3F000000; - 64'd288, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4B000000; - 64'd304: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4F000000; - 64'd320: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h06000000; - 64'd328: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h63736972; - 64'd344: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h56000000; - 64'd352: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h75616D69; - 64'd368: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h60000000; - 64'd376: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h76732C76; - 64'd392: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69000000; - 64'd408: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70757272; - 64'd416: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F72746E; - 64'd464, 64'd632, 64'd712, 64'd824: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h1B000000; - 64'd472: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70632C76; - 64'd480: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00006374; - 64'd520: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h38407972; - 64'd528: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00303030; - 64'd536: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h07000000; - 64'd544: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D656D; - 64'd568: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000080; - 64'd576: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000010; - 64'd616: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h0F000000; - 64'd656: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69730063; - 64'd664: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7375622D; - 64'd680: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hA7000000; - 64'd688: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E696C63; - 64'd696, 64'd808: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h30303030; - 64'd720: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C632C76; - 64'd736: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h10000000; - 64'd776: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000002; - 64'd784: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000C00; - 64'd800: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h74726175; - 64'd832: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61303535; - 64'd856: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h000000C0; - 64'd864: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40000000; - 64'd904: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h08000000; - 64'd928: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h09000000; - 64'd936: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73736572; - 64'd944: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h2300736C; - 64'd952: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C65632D; - 64'd960: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61706D6F; - 64'd968: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D0065; - 64'd976: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656D6974; - 64'd984: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6572662D; - 64'd992: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h64007963; - 64'd1000: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79745F65; - 64'd1008: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73006765; - 64'd1016: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69720073; - 64'd1024: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00617369; - 64'd1032: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65707974; - 64'd1040: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h662D6B63; - 64'd1048: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79636E65; - 64'd1056, 64'd1072: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h72726574; - 64'd1064: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C6C6563; - 64'd1080: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h746E6F63; - 64'd1088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70007265; - 64'd1096: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7200656C; - 64'd1104: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E690073; - 64'd1112: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73747075; - 64'd1120: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65646E65; - 64'd1128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h68732D67; - default: CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00028067; - 64'd24: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80000000; - 64'd32: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hEDFE0DD0; - 64'd40: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h38000000; - 64'd48: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h28000000; - 64'd56, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h10000000; - 64'd64: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hCC000000; - 64'd72, - 64'd80, - 64'd104, - 64'd216, - 64'd296, - 64'd568, - 64'd576, - 64'd672, - 64'd680, - 64'd776, - 64'd784, - 64'd840, - 64'd856, - 64'd864, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = 32'h0; - 64'd88, 64'd256, 64'd688, 64'd800: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h01000000; - 64'd96, - 64'd112, - 64'd128, - 64'd208, - 64'd224, - 64'd240, - 64'd320, - 64'd432, - 64'd448, - 64'd488, - 64'd536, - 64'd736, - 64'd752, - 64'd872, - 64'd888, - 64'd904: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h03000000; - 64'd120, 64'd232, 64'd464: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0F000000; - 64'd136, 64'd328: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h1B000000; - 64'd144: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h732C7261; - 64'd152: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7261622D; - 64'd160, 64'd336: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000076; - 64'd168: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h12000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h62626375; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656B6970; - 64'd192: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000065; - 64'd200: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h73757063; - 64'd248: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C000000; - 64'd264, 64'd704, 64'd816: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000030; - 64'd272, 64'd288, 64'd392, 64'd600, 64'd616: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h04000000; - 64'd280: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00757063; - 64'd304: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h05000000; - 64'd312: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79616B6F; - 64'd344: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0A000000; - 64'd352: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h34367672; - 64'd360: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000073; - 64'd368, 64'd920: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0B000000; - 64'd376, 64'd472, 64'd720: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63736972; - 64'd384: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00003933; - 64'd400: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80969800; - 64'd408: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65746E69; - 64'd416: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F632D74; - 64'd424: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72656C6C; - 64'd440: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79000000; - 64'd456: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h8A000000; - 64'd480: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692D75; - 64'd496: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h9F000000; - 64'd504, 64'd512, 64'd584, 64'd608, 64'd624, 64'd792, 64'd928: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h02000000; - 64'd520: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6D656D; - 64'd528: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30303030; - 64'd544: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3F000000; - 64'd552: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00007972; - 64'd592: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00636F73; - 64'd632: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h21000000; - 64'd656: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F732D65; - 64'd664: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656C706D; - 64'd696: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30324074; - 64'd712: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0D000000; - 64'd728: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30746E69; - 64'd744, 64'd912: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAE000000; - 64'd760: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h07000000; - 64'd808: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30306340; - 64'd824: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h09000000; - 64'd832: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3631736E; - 64'd880: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hC2000000; - 64'd896: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h69000000; - 64'd936: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h64646123; - 64'd944: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C65632D; - 64'd952: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h657A6973; - 64'd960: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6300736C; - 64'd968: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C626974; - 64'd976: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h006C6564; - 64'd984: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65736162; - 64'd992: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E657571; - 64'd1000: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63697665; - 64'd1008: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72006570; - 64'd1016: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75746174; - 64'd1024: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C766373; - 64'd1032: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D756D6D; - 64'd1040: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6C6300; - 64'd1048: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75716572; - 64'd1056: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692300; - 64'd1064, 64'd1080: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D747075; - 64'd1072: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E690073; - 64'd1088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C6C6F72; - 64'd1096: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h646E6168; - 64'd1104: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65676E61; - 64'd1112: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72726574; - 64'd1120: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7478652D; - 64'd1128: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65720064; - 64'd1136: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00746669; - default: CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705 or - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 or - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2) - begin - case (byte_addr__h705) - 64'd0: data64__h987 = 64'h0202859300000297; - 64'd8: data64__h987 = 64'h0182B283F1402573; - default: data64__h987 = - { CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_module_ready$EN) - rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_module_ready = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - begin - v__h808 = $stime; - #0; - end - v__h802 = v__h808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", - v__h802); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - begin - v__h8928 = $stime; - #0; - end - v__h8922 = v__h8928 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", - v__h8922); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h9221 = $stime; - #0; - end - v__h9215 = v__h9221 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9215, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h9331 = $stime; - #0; - end - v__h9325 = v__h9331 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9325, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkBoot_ROM - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCPU.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCPU.v deleted file mode 100644 index 82110d98..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCPU.v +++ /dev/null @@ -1,7287 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// hart0_server_reset_response_get O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_set_verbosity O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// hart0_server_reset_request_put I 1 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// nmi_req_set_not_clear I 1 -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// EN_hart0_server_reset_request_put I 1 -// EN_set_verbosity I 1 -// EN_hart0_server_reset_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// imem_master_arready, -// dmem_master_awready, -// dmem_master_wready) -> imem_master_rready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready, -// dmem_master_arready) -> dmem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCPU(CLK, - RST_N, - - hart0_server_reset_request_put, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - nmi_req_set_not_clear, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity); - input CLK; - input RST_N; - - // action method hart0_server_reset_request_put - input hart0_server_reset_request_put; - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // actionvalue method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, - RDY_set_verbosity, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - hart0_server_reset_response_get, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid; - - // register cfg_logdelay - reg [63 : 0] cfg_logdelay; - wire [63 : 0] cfg_logdelay$D_IN; - wire cfg_logdelay$EN; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register imem_rg_f3 - reg [2 : 0] imem_rg_f3; - wire [2 : 0] imem_rg_f3$D_IN; - wire imem_rg_f3$EN; - - // register imem_rg_instr_15_0 - reg [15 : 0] imem_rg_instr_15_0; - wire [15 : 0] imem_rg_instr_15_0$D_IN; - wire imem_rg_instr_15_0$EN; - - // register imem_rg_mstatus_MXR - reg imem_rg_mstatus_MXR; - wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN; - - // register imem_rg_pc - reg [63 : 0] imem_rg_pc; - reg [63 : 0] imem_rg_pc$D_IN; - wire imem_rg_pc$EN; - - // register imem_rg_priv - reg [1 : 0] imem_rg_priv; - wire [1 : 0] imem_rg_priv$D_IN; - wire imem_rg_priv$EN; - - // register imem_rg_satp - reg [63 : 0] imem_rg_satp; - wire [63 : 0] imem_rg_satp$D_IN; - wire imem_rg_satp$EN; - - // register imem_rg_sstatus_SUM - reg imem_rg_sstatus_SUM; - wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN; - - // register imem_rg_tval - reg [63 : 0] imem_rg_tval; - reg [63 : 0] imem_rg_tval$D_IN; - wire imem_rg_tval$EN; - - // register rg_cur_priv - reg [1 : 0] rg_cur_priv; - reg [1 : 0] rg_cur_priv$D_IN; - wire rg_cur_priv$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_next_pc - reg [63 : 0] rg_next_pc; - reg [63 : 0] rg_next_pc$D_IN; - wire rg_next_pc$EN; - - // register rg_run_on_reset - reg rg_run_on_reset; - wire rg_run_on_reset$D_IN, rg_run_on_reset$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_start_CPI_cycles - reg [63 : 0] rg_start_CPI_cycles; - wire [63 : 0] rg_start_CPI_cycles$D_IN; - wire rg_start_CPI_cycles$EN; - - // register rg_start_CPI_instrs - reg [63 : 0] rg_start_CPI_instrs; - wire [63 : 0] rg_start_CPI_instrs$D_IN; - wire rg_start_CPI_instrs$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register stage1_rg_full - reg stage1_rg_full; - reg stage1_rg_full$D_IN; - wire stage1_rg_full$EN; - - // register stage2_rg_full - reg stage2_rg_full; - reg stage2_rg_full$D_IN; - wire stage2_rg_full$EN; - - // register stage2_rg_resetting - reg stage2_rg_resetting; - wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN; - - // register stage2_rg_stage2 - reg [365 : 0] stage2_rg_stage2; - wire [365 : 0] stage2_rg_stage2$D_IN; - wire stage2_rg_stage2$EN; - - // register stage3_rg_full - reg stage3_rg_full; - reg stage3_rg_full$D_IN; - wire stage3_rg_full$EN; - - // register stage3_rg_stage3 - reg [174 : 0] stage3_rg_stage3; - wire [174 : 0] stage3_rg_stage3$D_IN; - wire stage3_rg_stage3$EN; - - // ports of submodule csr_regfile - reg [63 : 0] csr_regfile$csr_trap_actions_xtval; - reg [3 : 0] csr_regfile$csr_trap_actions_exc_code; - reg [1 : 0] csr_regfile$csr_ret_actions_from_priv; - wire [193 : 0] csr_regfile$csr_trap_actions; - wire [129 : 0] csr_regfile$csr_ret_actions; - wire [64 : 0] csr_regfile$read_csr; - wire [63 : 0] csr_regfile$csr_trap_actions_pc, - csr_regfile$mav_csr_write_word, - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - csr_regfile$read_mstatus, - csr_regfile$read_satp, - csr_regfile$read_sstatus; - wire [27 : 0] csr_regfile$read_misa; - wire [11 : 0] csr_regfile$access_permitted_1_csr_addr, - csr_regfile$access_permitted_2_csr_addr, - csr_regfile$csr_counter_read_fault_csr_addr, - csr_regfile$mav_csr_write_csr_addr, - csr_regfile$mav_read_csr_csr_addr, - csr_regfile$read_csr_csr_addr, - csr_regfile$read_csr_port2_csr_addr; - wire [4 : 0] csr_regfile$interrupt_pending, - csr_regfile$ma_update_fcsr_fflags_flags; - wire [2 : 0] csr_regfile$read_frm; - wire [1 : 0] csr_regfile$access_permitted_1_priv, - csr_regfile$access_permitted_2_priv, - csr_regfile$csr_counter_read_fault_priv, - csr_regfile$csr_trap_actions_from_priv, - csr_regfile$interrupt_pending_cur_priv, - csr_regfile$ma_update_mstatus_fs_fs; - wire csr_regfile$EN_csr_minstret_incr, - csr_regfile$EN_csr_ret_actions, - csr_regfile$EN_csr_trap_actions, - csr_regfile$EN_debug, - csr_regfile$EN_ma_update_fcsr_fflags, - csr_regfile$EN_ma_update_mstatus_fs, - csr_regfile$EN_mav_csr_write, - csr_regfile$EN_mav_read_csr, - csr_regfile$EN_server_reset_request_put, - csr_regfile$EN_server_reset_response_get, - csr_regfile$RDY_server_reset_request_put, - csr_regfile$RDY_server_reset_response_get, - csr_regfile$access_permitted_1, - csr_regfile$access_permitted_1_read_not_write, - csr_regfile$access_permitted_2, - csr_regfile$access_permitted_2_read_not_write, - csr_regfile$csr_trap_actions_interrupt, - csr_regfile$csr_trap_actions_nmi, - csr_regfile$m_external_interrupt_req_set_not_clear, - csr_regfile$nmi_pending, - csr_regfile$nmi_req_set_not_clear, - csr_regfile$s_external_interrupt_req_set_not_clear, - csr_regfile$software_interrupt_req_set_not_clear, - csr_regfile$timer_interrupt_req_set_not_clear, - csr_regfile$wfi_resume; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fpr_regfile - wire [63 : 0] fpr_regfile$read_rs1, - fpr_regfile$read_rs2, - fpr_regfile$read_rs3, - fpr_regfile$write_rd_rd_val; - wire [4 : 0] fpr_regfile$read_rs1_port2_rs1, - fpr_regfile$read_rs1_rs1, - fpr_regfile$read_rs2_rs2, - fpr_regfile$read_rs3_rs3, - fpr_regfile$write_rd_rd; - wire fpr_regfile$EN_server_reset_request_put, - fpr_regfile$EN_server_reset_response_get, - fpr_regfile$EN_write_rd, - fpr_regfile$RDY_server_reset_request_put, - fpr_regfile$RDY_server_reset_response_get; - - // ports of submodule gpr_regfile - wire [63 : 0] gpr_regfile$read_rs1, - gpr_regfile$read_rs2, - gpr_regfile$write_rd_rd_val; - wire [4 : 0] gpr_regfile$read_rs1_port2_rs1, - gpr_regfile$read_rs1_rs1, - gpr_regfile$read_rs2_rs2, - gpr_regfile$write_rd_rd; - wire gpr_regfile$EN_server_reset_request_put, - gpr_regfile$EN_server_reset_response_get, - gpr_regfile$EN_write_rd, - gpr_regfile$RDY_server_reset_request_put, - gpr_regfile$RDY_server_reset_response_get; - - // ports of submodule near_mem - reg [63 : 0] near_mem$imem_req_addr; - reg [1 : 0] near_mem$dmem_req_op; - reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM; - wire [63 : 0] near_mem$dmem_master_araddr, - near_mem$dmem_master_awaddr, - near_mem$dmem_master_rdata, - near_mem$dmem_master_wdata, - near_mem$dmem_req_addr, - near_mem$dmem_req_satp, - near_mem$dmem_req_store_value, - near_mem$dmem_word64, - near_mem$imem_master_araddr, - near_mem$imem_master_awaddr, - near_mem$imem_master_rdata, - near_mem$imem_master_wdata, - near_mem$imem_pc, - near_mem$imem_req_satp; - wire [31 : 0] near_mem$imem_instr; - wire [7 : 0] near_mem$dmem_master_arlen, - near_mem$dmem_master_awlen, - near_mem$dmem_master_wstrb, - near_mem$imem_master_arlen, - near_mem$imem_master_awlen, - near_mem$imem_master_wstrb, - near_mem$server_fence_request_put; - wire [6 : 0] near_mem$dmem_req_amo_funct7; - wire [3 : 0] near_mem$dmem_exc_code, - near_mem$dmem_master_arcache, - near_mem$dmem_master_arid, - near_mem$dmem_master_arqos, - near_mem$dmem_master_arregion, - near_mem$dmem_master_awcache, - near_mem$dmem_master_awid, - near_mem$dmem_master_awqos, - near_mem$dmem_master_awregion, - near_mem$dmem_master_bid, - near_mem$dmem_master_rid, - near_mem$dmem_master_wid, - near_mem$imem_exc_code, - near_mem$imem_master_arcache, - near_mem$imem_master_arid, - near_mem$imem_master_arqos, - near_mem$imem_master_arregion, - near_mem$imem_master_awcache, - near_mem$imem_master_awid, - near_mem$imem_master_awqos, - near_mem$imem_master_awregion, - near_mem$imem_master_bid, - near_mem$imem_master_rid, - near_mem$imem_master_wid; - wire [2 : 0] near_mem$dmem_master_arprot, - near_mem$dmem_master_arsize, - near_mem$dmem_master_awprot, - near_mem$dmem_master_awsize, - near_mem$dmem_req_f3, - near_mem$imem_master_arprot, - near_mem$imem_master_arsize, - near_mem$imem_master_awprot, - near_mem$imem_master_awsize, - near_mem$imem_req_f3; - wire [1 : 0] near_mem$dmem_master_arburst, - near_mem$dmem_master_awburst, - near_mem$dmem_master_bresp, - near_mem$dmem_master_rresp, - near_mem$dmem_req_priv, - near_mem$imem_master_arburst, - near_mem$imem_master_awburst, - near_mem$imem_master_bresp, - near_mem$imem_master_rresp, - near_mem$imem_req_priv; - wire near_mem$EN_dmem_req, - near_mem$EN_imem_req, - near_mem$EN_server_fence_i_request_put, - near_mem$EN_server_fence_i_response_get, - near_mem$EN_server_fence_request_put, - near_mem$EN_server_fence_response_get, - near_mem$EN_server_reset_request_put, - near_mem$EN_server_reset_response_get, - near_mem$EN_sfence_vma, - near_mem$RDY_server_fence_i_request_put, - near_mem$RDY_server_fence_i_response_get, - near_mem$RDY_server_fence_request_put, - near_mem$RDY_server_fence_response_get, - near_mem$RDY_server_reset_request_put, - near_mem$RDY_server_reset_response_get, - near_mem$dmem_exc, - near_mem$dmem_master_arlock, - near_mem$dmem_master_arready, - near_mem$dmem_master_arvalid, - near_mem$dmem_master_awlock, - near_mem$dmem_master_awready, - near_mem$dmem_master_awvalid, - near_mem$dmem_master_bready, - near_mem$dmem_master_bvalid, - near_mem$dmem_master_rlast, - near_mem$dmem_master_rready, - near_mem$dmem_master_rvalid, - near_mem$dmem_master_wlast, - near_mem$dmem_master_wready, - near_mem$dmem_master_wvalid, - near_mem$dmem_req_mstatus_MXR, - near_mem$dmem_req_sstatus_SUM, - near_mem$dmem_valid, - near_mem$imem_exc, - near_mem$imem_is_i32_not_i16, - near_mem$imem_master_arlock, - near_mem$imem_master_arready, - near_mem$imem_master_arvalid, - near_mem$imem_master_awlock, - near_mem$imem_master_awready, - near_mem$imem_master_awvalid, - near_mem$imem_master_bready, - near_mem$imem_master_bvalid, - near_mem$imem_master_rlast, - near_mem$imem_master_rready, - near_mem$imem_master_rvalid, - near_mem$imem_master_wlast, - near_mem$imem_master_wready, - near_mem$imem_master_wvalid, - near_mem$imem_valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_pc_reset_value; - - // ports of submodule stage1_f_reset_reqs - wire stage1_f_reset_reqs$CLR, - stage1_f_reset_reqs$DEQ, - stage1_f_reset_reqs$EMPTY_N, - stage1_f_reset_reqs$ENQ, - stage1_f_reset_reqs$FULL_N; - - // ports of submodule stage1_f_reset_rsps - wire stage1_f_reset_rsps$CLR, - stage1_f_reset_rsps$DEQ, - stage1_f_reset_rsps$EMPTY_N, - stage1_f_reset_rsps$ENQ, - stage1_f_reset_rsps$FULL_N; - - // ports of submodule stage2_f_reset_reqs - wire stage2_f_reset_reqs$CLR, - stage2_f_reset_reqs$DEQ, - stage2_f_reset_reqs$EMPTY_N, - stage2_f_reset_reqs$ENQ, - stage2_f_reset_reqs$FULL_N; - - // ports of submodule stage2_f_reset_rsps - wire stage2_f_reset_rsps$CLR, - stage2_f_reset_rsps$DEQ, - stage2_f_reset_rsps$EMPTY_N, - stage2_f_reset_rsps$ENQ, - stage2_f_reset_rsps$FULL_N; - - // ports of submodule stage2_fbox - wire [63 : 0] stage2_fbox$req_v1, - stage2_fbox$req_v2, - stage2_fbox$req_v3, - stage2_fbox$word_fst; - wire [6 : 0] stage2_fbox$req_f7, stage2_fbox$req_opcode; - wire [4 : 0] stage2_fbox$req_rs2, stage2_fbox$word_snd; - wire [2 : 0] stage2_fbox$req_rm; - wire stage2_fbox$EN_req, - stage2_fbox$EN_server_reset_request_put, - stage2_fbox$EN_server_reset_response_get, - stage2_fbox$RDY_server_reset_request_put, - stage2_fbox$RDY_server_reset_response_get, - stage2_fbox$valid; - - // ports of submodule stage2_mbox - wire [63 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word; - wire [3 : 0] stage2_mbox$set_verbosity_verbosity; - wire [2 : 0] stage2_mbox$req_f3; - wire stage2_mbox$EN_req, - stage2_mbox$EN_req_reset, - stage2_mbox$EN_rsp_reset, - stage2_mbox$EN_set_verbosity, - stage2_mbox$req_is_OP_not_OP_32, - stage2_mbox$valid; - - // ports of submodule stage3_f_reset_reqs - wire stage3_f_reset_reqs$CLR, - stage3_f_reset_reqs$DEQ, - stage3_f_reset_reqs$EMPTY_N, - stage3_f_reset_reqs$ENQ, - stage3_f_reset_reqs$FULL_N; - - // ports of submodule stage3_f_reset_rsps - wire stage3_f_reset_rsps$CLR, - stage3_f_reset_rsps$DEQ, - stage3_f_reset_rsps$EMPTY_N, - stage3_f_reset_rsps$ENQ, - stage3_f_reset_rsps$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_imem_rl_assert_fail, - CAN_FIRE_RL_imem_rl_fetch_next_32b, - CAN_FIRE_RL_rl_WFI_resume, - CAN_FIRE_RL_rl_finish_FENCE, - CAN_FIRE_RL_rl_finish_FENCE_I, - CAN_FIRE_RL_rl_finish_SFENCE_VMA, - CAN_FIRE_RL_rl_pipe, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_RL_rl_reset_from_WFI, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_show_pipe, - CAN_FIRE_RL_rl_stage1_CSRR_S_or_C, - CAN_FIRE_RL_rl_stage1_CSRR_W, - CAN_FIRE_RL_rl_stage1_FENCE, - CAN_FIRE_RL_rl_stage1_FENCE_I, - CAN_FIRE_RL_rl_stage1_SFENCE_VMA, - CAN_FIRE_RL_rl_stage1_WFI, - CAN_FIRE_RL_rl_stage1_interrupt, - CAN_FIRE_RL_rl_stage1_restart_after_csrrx, - CAN_FIRE_RL_rl_stage1_trap, - CAN_FIRE_RL_rl_stage1_xRET, - CAN_FIRE_RL_rl_stage2_nonpipe, - CAN_FIRE_RL_rl_trap_fetch, - CAN_FIRE_RL_stage1_rl_reset, - CAN_FIRE_RL_stage2_rl_reset_begin, - CAN_FIRE_RL_stage2_rl_reset_end, - CAN_FIRE_RL_stage3_rl_reset, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_set_verbosity, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_imem_rl_assert_fail, - WILL_FIRE_RL_imem_rl_fetch_next_32b, - WILL_FIRE_RL_rl_WFI_resume, - WILL_FIRE_RL_rl_finish_FENCE, - WILL_FIRE_RL_rl_finish_FENCE_I, - WILL_FIRE_RL_rl_finish_SFENCE_VMA, - WILL_FIRE_RL_rl_pipe, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_RL_rl_reset_from_WFI, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_show_pipe, - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C, - WILL_FIRE_RL_rl_stage1_CSRR_W, - WILL_FIRE_RL_rl_stage1_FENCE, - WILL_FIRE_RL_rl_stage1_FENCE_I, - WILL_FIRE_RL_rl_stage1_SFENCE_VMA, - WILL_FIRE_RL_rl_stage1_WFI, - WILL_FIRE_RL_rl_stage1_interrupt, - WILL_FIRE_RL_rl_stage1_restart_after_csrrx, - WILL_FIRE_RL_rl_stage1_trap, - WILL_FIRE_RL_rl_stage1_xRET, - WILL_FIRE_RL_rl_stage2_nonpipe, - WILL_FIRE_RL_rl_trap_fetch, - WILL_FIRE_RL_stage1_rl_reset, - WILL_FIRE_RL_stage2_rl_reset_begin, - WILL_FIRE_RL_stage2_rl_reset_end, - WILL_FIRE_RL_stage3_rl_reset, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_set_verbosity, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - reg [63 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2; - wire [63 : 0] MUX_near_mem$imem_req_2__VAL_1, - MUX_near_mem$imem_req_2__VAL_2, - MUX_near_mem$imem_req_2__VAL_5; - wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1, - MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_3; - wire MUX_csr_regfile$mav_csr_write_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_2, - MUX_gpr_regfile$write_rd_1__SEL_3, - MUX_imem_rg_f3$write_1__SEL_1, - MUX_imem_rg_f3$write_1__SEL_2, - MUX_imem_rg_mstatus_MXR$write_1__SEL_4, - MUX_imem_rg_pc$write_1__SEL_4, - MUX_near_mem$imem_req_1__SEL_6, - MUX_rg_cur_priv$write_1__SEL_1, - MUX_rg_mstatus_MXR$write_1__SEL_1, - MUX_rg_next_pc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_11, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_4, - MUX_rg_state$write_1__SEL_6, - MUX_rg_state$write_1__SEL_7, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9, - MUX_stage1_rg_full$write_1__VAL_2, - MUX_stage2_rg_full$write_1__VAL_2; - - // remaining internal signals - reg [63 : 0] CASE_theResult__607_BITS_6_TO_0_0b100011_alu_o_ETC__q23, - CASE_theResult__607_BITS_6_TO_0_0b1100111_data_ETC__q22, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557, - _theResult_____1_fst__h16245, - alu_outputs___1_val1__h15039, - rs1_val__h23782, - value__h6429, - value__h6490, - x_out_bypass_rd_val__h6725, - x_out_data_to_stage2_addr__h14648, - x_out_data_to_stage2_val1__h14649, - x_out_data_to_stage3_rd_val__h6250, - x_out_fbypass_rd_val__h6874; - reg [4 : 0] x_out_bypass_rd__h6724, - x_out_data_to_stage2_rd__h14647, - x_out_data_to_stage3_fpr_flags__h6249, - x_out_data_to_stage3_rd__h6246, - x_out_fbypass_rd__h6873; - reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q15, - CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17, - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18, - CASE_theResult__607_BITS_31_TO_20_0b0_CASE_rg__ETC__q16, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1260, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1285, - alu_outputs_exc_code__h15680, - x_out_trap_info_exc_code__h6466; - reg [2 : 0] CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373; - reg [1 : 0] CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1, - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2, - CASE_stage2_rg_stage2_BITS_267_TO_265_1_IF_NOT_ETC__q3; - reg CASE_theResult__607_BITS_6_TO_0_0b1000011_NOT__ETC__q11, - CASE_theResult__607_BITS_6_TO_0_0b1000011_theR_ETC__q13, - CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12, - CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697, - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153, - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163, - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198, - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d232; - wire [127 : 0] csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d2005; - wire [63 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1558, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1559, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1576, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1432, - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1952, - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1441, - _theResult_____1_fst__h16238, - _theResult_____1_fst__h16273, - _theResult_____1_fst_rd_val__h6703, - _theResult_____1_snd_fst_rd_val__h6859, - _theResult_____2_fst_rd_val__h6700, - _theResult_____2_snd_rd_val__h6856, - _theResult____h28496, - _theResult___fst__h16363, - _theResult___fst__h16370, - _theResult___fst__h16490, - _theResult___fst_rd_val__h6714, - _theResult___snd__h18728, - _theResult___snd_rd_val__h6865, - alu_outputs___1_addr__h14775, - alu_outputs___1_addr__h14799, - alu_outputs___1_addr__h14828, - alu_outputs___1_addr__h15117, - alu_outputs___1_addr__h15141, - alu_outputs___1_val1__h14946, - alu_outputs___1_val1__h14987, - alu_outputs___1_val1__h15013, - alu_outputs___1_val1__h15058, - alu_outputs___1_val1__h15077, - alu_outputs___1_val1__h15428, - alu_outputs___1_val1__h15452, - alu_outputs___1_val1__h15653, - alu_outputs___1_val2__h15143, - branch_target__h14754, - cpi__h28498, - cpifrac__h28499, - data_to_stage2_addr__h14637, - data_to_stage3_rd_val__h6144, - delta_CPI_cycles__h28494, - delta_CPI_instrs___1__h28531, - delta_CPI_instrs__h28495, - fall_through_pc__h14598, - frs1_val_bypassed__h4626, - frs2_val_bypassed__h4631, - next_pc___1__h18221, - next_pc__h18219, - rd_val___1__h16226, - rd_val___1__h16234, - rd_val___1__h16241, - rd_val___1__h16248, - rd_val___1__h16255, - rd_val___1__h16262, - rd_val___1__h18759, - rd_val___1__h18790, - rd_val___1__h18844, - rd_val___1__h18873, - rd_val___1__h18927, - rd_val___1__h18975, - rd_val___1__h18981, - rd_val___1__h19026, - rd_val__h14531, - rd_val__h14574, - rd_val__h18622, - rd_val__h18674, - rd_val__h18696, - rd_val__h19313, - rd_val__h19369, - rd_val__h19422, - rs1_val__h23289, - rs1_val_bypassed__h4615, - rs2_val_bypassed__h4621, - trap_info_tval__h18051, - val__h14533, - val__h14576, - value__h18109, - x__h28497, - x_out_data_to_stage2_val2__h14650, - x_out_data_to_stage2_val3__h14651, - x_out_next_pc__h14611, - y__h24086; - wire [31 : 0] IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d599, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d601, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d603, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d604, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d605, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d607, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d608, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d609, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d611, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d613, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d614, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d616, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d617, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d618, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d619, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d620, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d621, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d622, - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d623, - _theResult____h4607, - _theResult___fst__h7200, - _theResult___fst__h7228, - alu_outputs___1_addr5117_BITS_31_TO_0__q21, - instr___1__h7021, - instr__h10146, - instr__h10318, - instr__h10487, - instr__h10676, - instr__h10865, - instr__h10982, - instr__h11160, - instr__h11279, - instr__h11374, - instr__h11510, - instr__h11646, - instr__h11782, - instr__h11920, - instr__h12058, - instr__h12216, - instr__h12312, - instr__h12465, - instr__h12664, - instr__h12815, - instr__h13854, - instr__h14007, - instr__h14206, - instr__h14357, - instr__h4605, - instr__h7300, - instr__h7445, - instr__h7637, - instr__h7832, - instr__h8061, - instr__h8515, - instr__h8631, - instr__h8696, - instr__h9013, - instr__h9351, - instr__h9535, - instr__h9664, - instr__h9891, - instr_out___1__h7170, - instr_out___1__h7202, - instr_out___1__h7230, - rs1_val_bypassed615_BITS_31_TO_0_MINUS_rs2_val_ETC__q10, - rs1_val_bypassed615_BITS_31_TO_0_PLUS_rs2_val__ETC__q9, - rs1_val_bypassed615_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8, - rs1_val_bypassed615_BITS_31_TO_0__q7, - tmp__h18872, - v32__h15047, - x__h18793, - x__h18847, - x__h18984, - x__h19029, - x_out_data_to_stage2_instr__h14645; - wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401, - theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q5; - wire [19 : 0] imm20__h9403; - wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426, - theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q4; - wire [11 : 0] imm12__h10159, - imm12__h10355, - imm12__h10692, - imm12__h12313, - imm12__h12665, - imm12__h7301, - imm12__h7638, - imm12__h9275, - imm12__h9944, - offset__h8008, - theResult__607_BITS_31_TO_20__q20, - theResult__607_BITS_31_TO_25_CONCAT_theResult__ETC__q6; - wire [9 : 0] funct10__h15025, nzimm10__h10157, nzimm10__h9942; - wire [8 : 0] offset__h12227, offset__h8640; - wire [7 : 0] offset__h12599, offset__h7071; - wire [6 : 0] offset__h7580; - wire [5 : 0] imm6__h9273, shamt__h14931; - wire [4 : 0] offset_BITS_4_TO_0___h12940, - offset_BITS_4_TO_0___h7569, - offset_BITS_4_TO_0___h8000, - rd__h7640, - rs1__h7639; - wire [3 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1220, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1224, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1262, - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1214, - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1270, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287, - IF_rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7__ETC___d1258, - alu_outputs___1_exc_code__h15424, - cur_verbosity__h3134, - x_out_trap_info_exc_code__h18054; - wire [2 : 0] rm__h15556, x_out_data_to_stage2_rounding_mode__h14653; - wire [1 : 0] IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d258, - IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d284, - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289, - IF_near_mem_dmem_valid__25_AND_NOT_near_mem_dm_ETC___d256, - IF_near_mem_dmem_valid__25_THEN_IF_near_mem_dm_ETC___d128, - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132, - IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130, - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137, - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265, - sxl__h5045, - uxl__h5046; - wire IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1750, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1043, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1050, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1235, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d2002, - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627, - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629, - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d733, - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1824, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1895, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1897, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1900, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1914, - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1190, - NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1353, - NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1403, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1760, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1771, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1779, - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632, - _0_OR_0_OR_near_mem_imem_exc__48_OR_IF_IF_NOT_n_ETC___d1893, - csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1753, - csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1758, - csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1764, - csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d411, - csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d417, - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d1000, - fpr_regfile_RDY_server_reset_request_put__697__ETC___d1709, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1603, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1606, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1609, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1612, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1615, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1618, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1621, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1624, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1627, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1630, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1633, - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1636, - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d639, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d641, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1749, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647, - rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7_EQ__ETC___d1256, - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917, - rg_state_6_EQ_3_766_AND_stage3_rg_full_6_OR_NO_ETC___d1785, - stage2_f_reset_rsps_i_notEmpty__720_AND_stage3_ETC___d1729, - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d672, - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d680; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // actionvalue method hart0_server_reset_response_get - assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ; - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = near_mem$imem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = near_mem$imem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = near_mem$imem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = near_mem$imem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = near_mem$imem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = near_mem$imem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = near_mem$imem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = near_mem$imem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = near_mem$imem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = near_mem$imem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = near_mem$imem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = near_mem$imem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = near_mem$imem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = near_mem$imem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = near_mem$imem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = near_mem$imem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = near_mem$imem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = near_mem$imem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = near_mem$imem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = near_mem$imem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = near_mem$imem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = near_mem$imem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = near_mem$imem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = near_mem$imem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = near_mem$imem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = near_mem$imem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = near_mem$imem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = near_mem$imem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = near_mem$imem_master_rready ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = near_mem$dmem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = near_mem$dmem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = near_mem$dmem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = near_mem$dmem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = near_mem$dmem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = near_mem$dmem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = near_mem$dmem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = near_mem$dmem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = near_mem$dmem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = near_mem$dmem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = near_mem$dmem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = near_mem$dmem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = near_mem$dmem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = near_mem$dmem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = near_mem$dmem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = near_mem$dmem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = near_mem$dmem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = near_mem$dmem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = near_mem$dmem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = near_mem$dmem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = near_mem$dmem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = near_mem$dmem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = near_mem$dmem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = near_mem$dmem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = near_mem$dmem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = near_mem$dmem_master_rready ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // submodule csr_regfile - mkCSR_RegFile csr_regfile(.CLK(CLK), - .RST_N(RST_N), - .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr), - .access_permitted_1_priv(csr_regfile$access_permitted_1_priv), - .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write), - .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr), - .access_permitted_2_priv(csr_regfile$access_permitted_2_priv), - .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write), - .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr), - .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv), - .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv), - .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code), - .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv), - .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt), - .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi), - .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc), - .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval), - .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv), - .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear), - .ma_update_fcsr_fflags_flags(csr_regfile$ma_update_fcsr_fflags_flags), - .ma_update_mstatus_fs_fs(csr_regfile$ma_update_mstatus_fs_fs), - .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr), - .mav_csr_write_word(csr_regfile$mav_csr_write_word), - .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr), - .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear), - .read_csr_csr_addr(csr_regfile$read_csr_csr_addr), - .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr), - .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear), - .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear), - .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get), - .EN_mav_read_csr(csr_regfile$EN_mav_read_csr), - .EN_mav_csr_write(csr_regfile$EN_mav_csr_write), - .EN_ma_update_fcsr_fflags(csr_regfile$EN_ma_update_fcsr_fflags), - .EN_ma_update_mstatus_fs(csr_regfile$EN_ma_update_mstatus_fs), - .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions), - .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions), - .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr), - .EN_debug(csr_regfile$EN_debug), - .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get), - .read_csr(csr_regfile$read_csr), - .read_csr_port2(), - .mav_read_csr(), - .mav_csr_write(), - .read_frm(csr_regfile$read_frm), - .read_misa(csr_regfile$read_misa), - .read_mstatus(csr_regfile$read_mstatus), - .read_sstatus(csr_regfile$read_sstatus), - .read_ustatus(), - .read_satp(csr_regfile$read_satp), - .csr_trap_actions(csr_regfile$csr_trap_actions), - .RDY_csr_trap_actions(), - .csr_ret_actions(csr_regfile$csr_ret_actions), - .RDY_csr_ret_actions(), - .read_csr_minstret(csr_regfile$read_csr_minstret), - .read_csr_mcycle(csr_regfile$read_csr_mcycle), - .read_csr_mtime(), - .access_permitted_1(csr_regfile$access_permitted_1), - .access_permitted_2(csr_regfile$access_permitted_2), - .csr_counter_read_fault(), - .csr_mip_read(), - .interrupt_pending(csr_regfile$interrupt_pending), - .wfi_resume(csr_regfile$wfi_resume), - .nmi_pending(csr_regfile$nmi_pending), - .RDY_debug()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fpr_regfile - mkFPR_RegFile fpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(fpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(fpr_regfile$read_rs1_rs1), - .read_rs2_rs2(fpr_regfile$read_rs2_rs2), - .read_rs3_rs3(fpr_regfile$read_rs3_rs3), - .write_rd_rd(fpr_regfile$write_rd_rd), - .write_rd_rd_val(fpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(fpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(fpr_regfile$EN_server_reset_response_get), - .EN_write_rd(fpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(fpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fpr_regfile$RDY_server_reset_response_get), - .read_rs1(fpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(fpr_regfile$read_rs2), - .read_rs3(fpr_regfile$read_rs3)); - - // submodule gpr_regfile - mkGPR_RegFile gpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(gpr_regfile$read_rs1_rs1), - .read_rs2_rs2(gpr_regfile$read_rs2_rs2), - .write_rd_rd(gpr_regfile$write_rd_rd), - .write_rd_rd_val(gpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get), - .EN_write_rd(gpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get), - .read_rs1(gpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(gpr_regfile$read_rs2)); - - // submodule near_mem - mkNear_Mem near_mem(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(near_mem$dmem_master_arready), - .dmem_master_awready(near_mem$dmem_master_awready), - .dmem_master_bid(near_mem$dmem_master_bid), - .dmem_master_bresp(near_mem$dmem_master_bresp), - .dmem_master_bvalid(near_mem$dmem_master_bvalid), - .dmem_master_rdata(near_mem$dmem_master_rdata), - .dmem_master_rid(near_mem$dmem_master_rid), - .dmem_master_rlast(near_mem$dmem_master_rlast), - .dmem_master_rresp(near_mem$dmem_master_rresp), - .dmem_master_rvalid(near_mem$dmem_master_rvalid), - .dmem_master_wready(near_mem$dmem_master_wready), - .dmem_req_addr(near_mem$dmem_req_addr), - .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7), - .dmem_req_f3(near_mem$dmem_req_f3), - .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR), - .dmem_req_op(near_mem$dmem_req_op), - .dmem_req_priv(near_mem$dmem_req_priv), - .dmem_req_satp(near_mem$dmem_req_satp), - .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM), - .dmem_req_store_value(near_mem$dmem_req_store_value), - .imem_master_arready(near_mem$imem_master_arready), - .imem_master_awready(near_mem$imem_master_awready), - .imem_master_bid(near_mem$imem_master_bid), - .imem_master_bresp(near_mem$imem_master_bresp), - .imem_master_bvalid(near_mem$imem_master_bvalid), - .imem_master_rdata(near_mem$imem_master_rdata), - .imem_master_rid(near_mem$imem_master_rid), - .imem_master_rlast(near_mem$imem_master_rlast), - .imem_master_rresp(near_mem$imem_master_rresp), - .imem_master_rvalid(near_mem$imem_master_rvalid), - .imem_master_wready(near_mem$imem_master_wready), - .imem_req_addr(near_mem$imem_req_addr), - .imem_req_f3(near_mem$imem_req_f3), - .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR), - .imem_req_priv(near_mem$imem_req_priv), - .imem_req_satp(near_mem$imem_req_satp), - .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM), - .server_fence_request_put(near_mem$server_fence_request_put), - .EN_server_reset_request_put(near_mem$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem$EN_server_reset_response_get), - .EN_imem_req(near_mem$EN_imem_req), - .EN_dmem_req(near_mem$EN_dmem_req), - .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put), - .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get), - .EN_server_fence_request_put(near_mem$EN_server_fence_request_put), - .EN_server_fence_response_get(near_mem$EN_server_fence_response_get), - .EN_sfence_vma(near_mem$EN_sfence_vma), - .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get), - .imem_valid(near_mem$imem_valid), - .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16), - .imem_pc(near_mem$imem_pc), - .imem_instr(near_mem$imem_instr), - .imem_exc(near_mem$imem_exc), - .imem_exc_code(near_mem$imem_exc_code), - .imem_tval(), - .imem_master_awvalid(near_mem$imem_master_awvalid), - .imem_master_awid(near_mem$imem_master_awid), - .imem_master_awaddr(near_mem$imem_master_awaddr), - .imem_master_awlen(near_mem$imem_master_awlen), - .imem_master_awsize(near_mem$imem_master_awsize), - .imem_master_awburst(near_mem$imem_master_awburst), - .imem_master_awlock(near_mem$imem_master_awlock), - .imem_master_awcache(near_mem$imem_master_awcache), - .imem_master_awprot(near_mem$imem_master_awprot), - .imem_master_awqos(near_mem$imem_master_awqos), - .imem_master_awregion(near_mem$imem_master_awregion), - .imem_master_wvalid(near_mem$imem_master_wvalid), - .imem_master_wid(near_mem$imem_master_wid), - .imem_master_wdata(near_mem$imem_master_wdata), - .imem_master_wstrb(near_mem$imem_master_wstrb), - .imem_master_wlast(near_mem$imem_master_wlast), - .imem_master_bready(near_mem$imem_master_bready), - .imem_master_arvalid(near_mem$imem_master_arvalid), - .imem_master_arid(near_mem$imem_master_arid), - .imem_master_araddr(near_mem$imem_master_araddr), - .imem_master_arlen(near_mem$imem_master_arlen), - .imem_master_arsize(near_mem$imem_master_arsize), - .imem_master_arburst(near_mem$imem_master_arburst), - .imem_master_arlock(near_mem$imem_master_arlock), - .imem_master_arcache(near_mem$imem_master_arcache), - .imem_master_arprot(near_mem$imem_master_arprot), - .imem_master_arqos(near_mem$imem_master_arqos), - .imem_master_arregion(near_mem$imem_master_arregion), - .imem_master_rready(near_mem$imem_master_rready), - .dmem_valid(near_mem$dmem_valid), - .dmem_word64(near_mem$dmem_word64), - .dmem_st_amo_val(), - .dmem_exc(near_mem$dmem_exc), - .dmem_exc_code(near_mem$dmem_exc_code), - .dmem_master_awvalid(near_mem$dmem_master_awvalid), - .dmem_master_awid(near_mem$dmem_master_awid), - .dmem_master_awaddr(near_mem$dmem_master_awaddr), - .dmem_master_awlen(near_mem$dmem_master_awlen), - .dmem_master_awsize(near_mem$dmem_master_awsize), - .dmem_master_awburst(near_mem$dmem_master_awburst), - .dmem_master_awlock(near_mem$dmem_master_awlock), - .dmem_master_awcache(near_mem$dmem_master_awcache), - .dmem_master_awprot(near_mem$dmem_master_awprot), - .dmem_master_awqos(near_mem$dmem_master_awqos), - .dmem_master_awregion(near_mem$dmem_master_awregion), - .dmem_master_wvalid(near_mem$dmem_master_wvalid), - .dmem_master_wid(near_mem$dmem_master_wid), - .dmem_master_wdata(near_mem$dmem_master_wdata), - .dmem_master_wstrb(near_mem$dmem_master_wstrb), - .dmem_master_wlast(near_mem$dmem_master_wlast), - .dmem_master_bready(near_mem$dmem_master_bready), - .dmem_master_arvalid(near_mem$dmem_master_arvalid), - .dmem_master_arid(near_mem$dmem_master_arid), - .dmem_master_araddr(near_mem$dmem_master_araddr), - .dmem_master_arlen(near_mem$dmem_master_arlen), - .dmem_master_arsize(near_mem$dmem_master_arsize), - .dmem_master_arburst(near_mem$dmem_master_arburst), - .dmem_master_arlock(near_mem$dmem_master_arlock), - .dmem_master_arcache(near_mem$dmem_master_arcache), - .dmem_master_arprot(near_mem$dmem_master_arprot), - .dmem_master_arqos(near_mem$dmem_master_arqos), - .dmem_master_arregion(near_mem$dmem_master_arregion), - .dmem_master_rready(near_mem$dmem_master_rready), - .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put), - .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get), - .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put), - .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get), - .RDY_sfence_vma()); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(soc_map$m_pc_reset_value), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule stage1_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_reqs$ENQ), - .DEQ(stage1_f_reset_reqs$DEQ), - .CLR(stage1_f_reset_reqs$CLR), - .FULL_N(stage1_f_reset_reqs$FULL_N), - .EMPTY_N(stage1_f_reset_reqs$EMPTY_N)); - - // submodule stage1_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_rsps$ENQ), - .DEQ(stage1_f_reset_rsps$DEQ), - .CLR(stage1_f_reset_rsps$CLR), - .FULL_N(stage1_f_reset_rsps$FULL_N), - .EMPTY_N(stage1_f_reset_rsps$EMPTY_N)); - - // submodule stage2_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_reqs$ENQ), - .DEQ(stage2_f_reset_reqs$DEQ), - .CLR(stage2_f_reset_reqs$CLR), - .FULL_N(stage2_f_reset_reqs$FULL_N), - .EMPTY_N(stage2_f_reset_reqs$EMPTY_N)); - - // submodule stage2_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_rsps$ENQ), - .DEQ(stage2_f_reset_rsps$DEQ), - .CLR(stage2_f_reset_rsps$CLR), - .FULL_N(stage2_f_reset_rsps$FULL_N), - .EMPTY_N(stage2_f_reset_rsps$EMPTY_N)); - - // submodule stage2_fbox - mkFBox_Top stage2_fbox(.CLK(CLK), - .RST_N(RST_N), - .req_f7(stage2_fbox$req_f7), - .req_opcode(stage2_fbox$req_opcode), - .req_rm(stage2_fbox$req_rm), - .req_rs2(stage2_fbox$req_rs2), - .req_v1(stage2_fbox$req_v1), - .req_v2(stage2_fbox$req_v2), - .req_v3(stage2_fbox$req_v3), - .EN_server_reset_request_put(stage2_fbox$EN_server_reset_request_put), - .EN_server_reset_response_get(stage2_fbox$EN_server_reset_response_get), - .EN_req(stage2_fbox$EN_req), - .RDY_server_reset_request_put(stage2_fbox$RDY_server_reset_request_put), - .RDY_server_reset_response_get(stage2_fbox$RDY_server_reset_response_get), - .valid(stage2_fbox$valid), - .word_fst(stage2_fbox$word_fst), - .word_snd(stage2_fbox$word_snd)); - - // submodule stage2_mbox - mkRISCV_MBox stage2_mbox(.CLK(CLK), - .RST_N(RST_N), - .req_f3(stage2_mbox$req_f3), - .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32), - .req_v1(stage2_mbox$req_v1), - .req_v2(stage2_mbox$req_v2), - .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity), - .EN_set_verbosity(stage2_mbox$EN_set_verbosity), - .EN_req_reset(stage2_mbox$EN_req_reset), - .EN_rsp_reset(stage2_mbox$EN_rsp_reset), - .EN_req(stage2_mbox$EN_req), - .RDY_set_verbosity(), - .RDY_req_reset(), - .RDY_rsp_reset(), - .valid(stage2_mbox$valid), - .word(stage2_mbox$word)); - - // submodule stage3_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_reqs$ENQ), - .DEQ(stage3_f_reset_reqs$DEQ), - .CLR(stage3_f_reset_reqs$CLR), - .FULL_N(stage3_f_reset_reqs$FULL_N), - .EMPTY_N(stage3_f_reset_reqs$EMPTY_N)); - - // submodule stage3_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_rsps$ENQ), - .DEQ(stage3_f_reset_rsps$DEQ), - .CLR(stage3_f_reset_rsps$CLR), - .FULL_N(stage3_f_reset_rsps$FULL_N), - .EMPTY_N(stage3_f_reset_rsps$EMPTY_N)); - - // rule RL_rl_show_pipe - assign CAN_FIRE_RL_rl_show_pipe = - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - rg_state != 4'd0 && - rg_state != 4'd1 && - rg_state != 4'd10 ; - assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ; - - // rule RL_rl_stage2_nonpipe - assign CAN_FIRE_RL_rl_stage2_nonpipe = - rg_state == 4'd3 && !stage3_rg_full && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd3 && - (!stage1_rg_full || - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647) ; - assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ; - - // rule RL_rl_stage1_CSRR_W - assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_stage1_CSRR_S_or_C - assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_stage1_restart_after_csrrx - assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx = - CAN_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // rule RL_rl_stage1_xRET - assign CAN_FIRE_RL_rl_stage1_xRET = - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd7 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd8 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd9) ; - assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ; - - // rule RL_rl_stage1_FENCE_I - assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - - // rule RL_rl_finish_FENCE_I - assign CAN_FIRE_RL_rl_finish_FENCE_I = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_i_response_get && - rg_state == 4'd7 ; - assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ; - - // rule RL_rl_stage1_FENCE - assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - - // rule RL_rl_finish_FENCE - assign CAN_FIRE_RL_rl_finish_FENCE = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_response_get && - rg_state == 4'd8 ; - assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ; - - // rule RL_rl_finish_SFENCE_VMA - assign CAN_FIRE_RL_rl_finish_SFENCE_VMA = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_finish_SFENCE_VMA = - CAN_FIRE_RL_rl_finish_SFENCE_VMA ; - - // rule RL_rl_stage1_WFI - assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - - // rule RL_rl_WFI_resume - assign CAN_FIRE_RL_rl_WFI_resume = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd10 && - csr_regfile$wfi_resume ; - assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ; - - // rule RL_rl_reset_from_WFI - assign CAN_FIRE_RL_rl_reset_from_WFI = - rg_state == 4'd10 && f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_4 ; - - // rule RL_rl_stage1_trap - assign CAN_FIRE_RL_rl_stage1_trap = - rg_state == 4'd4 || - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd11 ; - assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ; - - // rule RL_rl_trap_fetch - assign CAN_FIRE_RL_rl_trap_fetch = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd5 ; - assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; - - // rule RL_rl_stage1_interrupt - assign CAN_FIRE_RL_rl_stage1_interrupt = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - rg_state == 4'd3 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1750 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd0 && - !stage3_rg_full ; - assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ; - - // rule RL_imem_rl_assert_fail - assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ; - assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = - gpr_regfile$RDY_server_reset_response_get && - fpr_regfile$RDY_server_reset_response_get && - near_mem$RDY_server_reset_response_get && - csr_regfile$RDY_server_reset_response_get && - stage1_f_reset_rsps$EMPTY_N && - stage2_f_reset_rsps_i_notEmpty__720_AND_stage3_ETC___d1729 && - rg_state == 4'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_pipe - assign CAN_FIRE_RL_rl_pipe = - (csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1764 || - !near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state_6_EQ_3_766_AND_stage3_rg_full_6_OR_NO_ETC___d1785 ; - assign WILL_FIRE_RL_rl_pipe = - CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_rl_stage1_SFENCE_VMA - assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = - gpr_regfile$RDY_server_reset_request_put && - fpr_regfile_RDY_server_reset_request_put__697__ETC___d1709 && - rg_state == 4'd0 ; - assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ; - - // rule RL_imem_rl_fetch_next_32b - assign CAN_FIRE_RL_imem_rl_fetch_next_32b = - near_mem$imem_valid && - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] == 2'b11 ; - assign WILL_FIRE_RL_imem_rl_fetch_next_32b = - CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_stage3_rl_reset - assign CAN_FIRE_RL_stage3_rl_reset = - stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ; - - // rule RL_stage2_rl_reset_end - assign CAN_FIRE_RL_stage2_rl_reset_end = - stage2_fbox$RDY_server_reset_response_get && - stage2_f_reset_rsps$FULL_N && - stage2_rg_resetting ; - assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ; - - // rule RL_stage2_rl_reset_begin - assign CAN_FIRE_RL_stage2_rl_reset_begin = - stage2_fbox$RDY_server_reset_request_put && - stage2_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_stage2_rl_reset_begin = - CAN_FIRE_RL_stage2_rl_reset_begin ; - - // rule RL_stage1_rl_reset - assign CAN_FIRE_RL_stage1_rl_reset = - stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_csr_regfile$mav_csr_write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 ; - assign MUX_gpr_regfile$write_rd_1__SEL_2 = - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - assign MUX_gpr_regfile$write_rd_1__SEL_3 = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - !stage3_rg_stage3[69] ; - assign MUX_imem_rg_f3$write_1__SEL_1 = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ; - assign MUX_imem_rg_f3$write_1__SEL_2 = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 ; - assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_imem_rg_pc$write_1__SEL_4 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_near_mem$imem_req_1__SEL_6 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_rg_cur_priv$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_mstatus_MXR$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_next_pc$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign MUX_rg_state$write_1__SEL_1 = - CAN_FIRE_RL_rl_reset_complete && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_2 = - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd2 ; - assign MUX_rg_state$write_1__SEL_3 = - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd3 ; - assign MUX_rg_state$write_1__SEL_4 = - CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ; - assign MUX_rg_state$write_1__SEL_6 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_rg_state$write_1__SEL_7 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_state$write_1__SEL_8 = - near_mem$RDY_server_fence_i_request_put && - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd5 ; - assign MUX_rg_state$write_1__SEL_9 = - near_mem$RDY_server_fence_request_put && - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd4 ; - assign MUX_rg_state$write_1__SEL_10 = - CAN_FIRE_RL_rl_stage1_SFENCE_VMA && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_11 = - rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd10 ; - assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 = - (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ? - csr_regfile$interrupt_pending[3:0] : - 4'd0 ; - always@(x_out_data_to_stage2_instr__h14645 or - csr_regfile$read_csr or - y__h24086 or - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1952) - begin - case (x_out_data_to_stage2_instr__h14645[14:12]) - 3'b010, 3'b110: - MUX_csr_regfile$mav_csr_write_2__VAL_2 = - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1952; - default: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - csr_regfile$read_csr[63:0] & y__h24086; - endcase - end - assign MUX_near_mem$imem_req_2__VAL_1 = - { soc_map$m_pc_reset_value[63:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_2 = - { x_out_next_pc__h14611[63:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[63:2], 2'b0 } ; - assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd3 : 4'd2 ; - assign MUX_rg_state$write_1__VAL_2 = - csr_regfile$access_permitted_1 ? 4'd6 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_3 = - csr_regfile$access_permitted_2 ? 4'd6 : 4'd4 ; - assign MUX_stage1_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1900 || - (csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1758 || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1779) && - stage1_rg_full ; - assign MUX_stage2_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1895 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd2 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd0 ; - - // register cfg_logdelay - assign cfg_logdelay$D_IN = set_verbosity_logdelay ; - assign cfg_logdelay$EN = EN_set_verbosity ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register imem_rg_f3 - assign imem_rg_f3$D_IN = 3'b010 ; - assign imem_rg_f3$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_instr_15_0 - assign imem_rg_instr_15_0$D_IN = near_mem$imem_instr[31:16] ; - assign imem_rg_instr_15_0$EN = CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // register imem_rg_mstatus_MXR - assign imem_rg_mstatus_MXR$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_mstatus[19] : - rg_mstatus_MXR ; - assign imem_rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_pc - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h14611 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_pc$D_IN = soc_map$m_pc_reset_value; - MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h14611; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_pc$D_IN = x_out_next_pc__h14611; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc; - default: imem_rg_pc$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_pc$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - - // register imem_rg_priv - assign imem_rg_priv$D_IN = rg_cur_priv ; - assign imem_rg_priv$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_satp - assign imem_rg_satp$D_IN = csr_regfile$read_satp ; - assign imem_rg_satp$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_sstatus_SUM - assign imem_rg_sstatus_SUM$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_sstatus[18] : - rg_sstatus_SUM ; - assign imem_rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_tval - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h14611 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or - rg_next_pc or - WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h18221) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_tval$D_IN = soc_map$m_pc_reset_value; - MUX_imem_rg_f3$write_1__SEL_2: - imem_rg_tval$D_IN = x_out_next_pc__h14611; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_tval$D_IN = x_out_next_pc__h14611; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - imem_rg_tval$D_IN = next_pc___1__h18221; - default: imem_rg_tval$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_tval$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // register rg_cur_priv - always@(MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or - csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_cur_priv$write_1__SEL_1: - rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[65:64]; - WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11; - default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_cur_priv$EN = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_mstatus[19] : - csr_regfile$csr_trap_actions[85] ; - assign rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_next_pc - always@(MUX_rg_next_pc$write_1__SEL_1 or - x_out_next_pc__h14611 or - MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h14611; - MUX_rg_cur_priv$write_1__SEL_1: - rg_next_pc$D_IN = csr_regfile$csr_trap_actions[193:130]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_next_pc$D_IN = csr_regfile$csr_ret_actions[129:66]; - default: rg_next_pc$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_next_pc$EN = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET ; - - // register rg_run_on_reset - assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ; - assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_sstatus[18] : - csr_regfile$csr_trap_actions[84] ; - assign rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_start_CPI_cycles - assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ; - assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_start_CPI_instrs - assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ; - assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_state - always@(WILL_FIRE_RL_rl_reset_complete or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_stage1_CSRR_W or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or - MUX_rg_state$write_1__VAL_3 or - WILL_FIRE_RL_rl_reset_from_WFI or - WILL_FIRE_RL_rl_reset_start or - MUX_rg_state$write_1__SEL_6 or - MUX_rg_state$write_1__SEL_7 or - WILL_FIRE_RL_rl_stage1_FENCE_I or - WILL_FIRE_RL_rl_stage1_FENCE or - WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_reset_complete: - rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_stage1_CSRR_W: - rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: - rg_state$D_IN = MUX_rg_state$write_1__VAL_3; - WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1; - MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd5; - WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd7; - WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd8; - WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd10; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_complete || - WILL_FIRE_RL_rl_stage1_CSRR_W || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C || - WILL_FIRE_RL_rl_reset_from_WFI || - WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_WFI ; - - // register stage1_rg_full - always@(WILL_FIRE_RL_stage1_rl_reset or - WILL_FIRE_RL_rl_pipe or - MUX_stage1_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or - WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_trap_fetch or - WILL_FIRE_RL_rl_stage1_trap or - WILL_FIRE_RL_rl_WFI_resume or - WILL_FIRE_RL_rl_finish_SFENCE_VMA or - WILL_FIRE_RL_rl_finish_FENCE or - WILL_FIRE_RL_rl_finish_FENCE_I or - WILL_FIRE_RL_rl_stage1_xRET or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_interrupt: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_trap_fetch: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_trap: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I: - stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_xRET: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0; - default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage1_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage1_rl_reset || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register stage2_rg_full - always@(WILL_FIRE_RL_stage2_rl_reset_begin or - WILL_FIRE_RL_rl_pipe or - MUX_stage2_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage2_rl_reset_begin: stage2_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage2_nonpipe: - stage2_rg_full$D_IN = 1'd0; - default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage2_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage2_rl_reset_begin ; - - // register stage2_rg_resetting - assign stage2_rg_resetting$D_IN = WILL_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_rg_resetting$EN = - WILL_FIRE_RL_stage2_rl_reset_end || - WILL_FIRE_RL_stage2_rl_reset_begin ; - - // register stage2_rg_stage2 - assign stage2_rg_stage2$D_IN = - { rg_cur_priv, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373, - x_out_data_to_stage2_rd__h14647, - x_out_data_to_stage2_addr__h14648, - x_out_data_to_stage2_val1__h14649, - x_out_data_to_stage2_val2__h14650, - x_out_data_to_stage2_val3__h14651, - _theResult____h4607[6:0] == 7'b0000111 || - (_theResult____h4607[6:0] == 7'b1010011 || - _theResult____h4607[6:0] == 7'b1000011 || - _theResult____h4607[6:0] == 7'b1000111 || - _theResult____h4607[6:0] == 7'b1001011 || - _theResult____h4607[6:0] == 7'b1001111) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd3) && - _theResult____h4607[31:25] != 7'h71 && - _theResult____h4607[31:25] != 7'h51 && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd3) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd1) && - _theResult____h4607[31:25] != 7'h70 && - _theResult____h4607[31:25] != 7'h50, - x_out_data_to_stage2_rounding_mode__h14653 } ; - assign stage2_rg_stage2$EN = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 ; - - // register stage3_rg_full - always@(WILL_FIRE_RL_stage3_rl_reset or - WILL_FIRE_RL_rl_pipe or - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 or - MUX_imem_rg_f3$write_1__SEL_1) - case (1'b1) - WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage3_rg_full$D_IN = - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2; - MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0; - default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage3_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_stage3_rl_reset ; - - // register stage3_rg_stage3 - assign stage3_rg_stage3$D_IN = - { stage2_rg_stage2[363:268], - stage2_rg_stage2[365:364], - stage2_rg_stage2[267:265] == 3'd0 || - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163, - x_out_data_to_stage3_rd__h6246, - stage2_rg_stage2[267:265] != 3'd0 && - stage2_rg_stage2[267:265] != 3'd1 && - stage2_rg_stage2[267:265] != 3'd4 && - stage2_rg_stage2[267:265] != 3'd2 && - stage2_rg_stage2[267:265] != 3'd3, - stage2_rg_stage2[267:265] != 3'd0 && - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198, - x_out_data_to_stage3_fpr_flags__h6249, - x_out_data_to_stage3_rd_val__h6250 } ; - assign stage3_rg_stage3$EN = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd2 ; - - // submodule csr_regfile - assign csr_regfile$access_permitted_1_csr_addr = - x_out_data_to_stage2_instr__h14645[31:20] ; - assign csr_regfile$access_permitted_1_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ; - assign csr_regfile$access_permitted_2_csr_addr = - x_out_data_to_stage2_instr__h14645[31:20] ; - assign csr_regfile$access_permitted_2_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_2_read_not_write = - rs1_val__h23782 == 64'd0 ; - assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ; - assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ; - always@(IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287) - begin - case (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287) - 4'd7: csr_regfile$csr_ret_actions_from_priv = 2'b11; - 4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b01; - default: csr_regfile$csr_ret_actions_from_priv = 2'b0; - endcase - end - always@(WILL_FIRE_RL_rl_stage1_interrupt or - MUX_csr_regfile$csr_trap_actions_5__VAL_1 or - WILL_FIRE_RL_rl_stage1_trap or - x_out_trap_info_exc_code__h18054 or - WILL_FIRE_RL_rl_stage2_nonpipe or x_out_trap_info_exc_code__h6466) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_exc_code = - MUX_csr_regfile$csr_trap_actions_5__VAL_1; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h18054; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h6466; - default: csr_regfile$csr_trap_actions_exc_code = - 4'b1010 /* unspecified value */ ; - endcase - end - assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ; - assign csr_regfile$csr_trap_actions_interrupt = - WILL_FIRE_RL_rl_stage1_interrupt && !csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_nmi = - WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_pc = - (WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap) ? - imem_rg_pc : - value__h6429 ; - always@(WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_stage1_trap or - value__h18109 or WILL_FIRE_RL_rl_stage2_nonpipe or value__h6490) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_xtval = 64'd0; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_xtval = value__h18109; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_xtval = value__h6490; - default: csr_regfile$csr_trap_actions_xtval = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ; - assign csr_regfile$m_external_interrupt_req_set_not_clear = - m_external_interrupt_req_set_not_clear ; - assign csr_regfile$ma_update_fcsr_fflags_flags = stage3_rg_stage3[68:64] ; - assign csr_regfile$ma_update_mstatus_fs_fs = 2'h3 ; - assign csr_regfile$mav_csr_write_csr_addr = - x_out_data_to_stage2_instr__h14645[31:20] ; - assign csr_regfile$mav_csr_write_word = - MUX_csr_regfile$mav_csr_write_1__SEL_1 ? - rs1_val__h23289 : - MUX_csr_regfile$mav_csr_write_2__VAL_2 ; - assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ; - assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign csr_regfile$read_csr_csr_addr = - x_out_data_to_stage2_instr__h14645[31:20] ; - assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ; - assign csr_regfile$s_external_interrupt_req_set_not_clear = - s_external_interrupt_req_set_not_clear ; - assign csr_regfile$software_interrupt_req_set_not_clear = - software_interrupt_req_set_not_clear ; - assign csr_regfile$timer_interrupt_req_set_not_clear = - timer_interrupt_req_set_not_clear ; - assign csr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign csr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign csr_regfile$EN_mav_read_csr = 1'b0 ; - assign csr_regfile$EN_mav_csr_write = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h14645[19:15] != 5'd0 ; - assign csr_regfile$EN_ma_update_fcsr_fflags = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - stage3_rg_stage3[70] ; - assign csr_regfile$EN_ma_update_mstatus_fs = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - (stage3_rg_stage3[70] || stage3_rg_stage3[69]) ; - assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_1 ; - assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ; - assign csr_regfile$EN_csr_minstret_incr = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd2 || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_stage1_WFI || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign csr_regfile$EN_debug = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = hart0_server_reset_request_put ; - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = - gpr_regfile$RDY_server_reset_request_put && - fpr_regfile_RDY_server_reset_request_put__697__ETC___d1709 && - rg_state == 4'd0 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = rg_run_on_reset ; - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fpr_regfile - assign fpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign fpr_regfile$read_rs1_rs1 = _theResult____h4607[19:15] ; - assign fpr_regfile$read_rs2_rs2 = _theResult____h4607[24:20] ; - assign fpr_regfile$read_rs3_rs3 = _theResult____h4607[31:27] ; - assign fpr_regfile$write_rd_rd = stage3_rg_stage3[75:71] ; - assign fpr_regfile$write_rd_rd_val = stage3_rg_stage3[63:0] ; - assign fpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign fpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign fpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - stage3_rg_stage3[69] ; - - // submodule gpr_regfile - assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign gpr_regfile$read_rs1_rs1 = _theResult____h4607[19:15] ; - assign gpr_regfile$read_rs2_rs2 = _theResult____h4607[24:20] ; - assign gpr_regfile$write_rd_rd = - MUX_gpr_regfile$write_rd_1__SEL_3 ? - stage3_rg_stage3[75:71] : - x_out_data_to_stage2_instr__h14645[11:7] ; - assign gpr_regfile$write_rd_rd_val = - (MUX_csr_regfile$mav_csr_write_1__SEL_1 || - MUX_gpr_regfile$write_rd_1__SEL_2) ? - csr_regfile$read_csr[63:0] : - stage3_rg_stage3[63:0] ; - assign gpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign gpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign gpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - !stage3_rg_stage3[69] ; - - // submodule near_mem - assign near_mem$dmem_master_arready = dmem_master_arready ; - assign near_mem$dmem_master_awready = dmem_master_awready ; - assign near_mem$dmem_master_bid = dmem_master_bid ; - assign near_mem$dmem_master_bresp = dmem_master_bresp ; - assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; - assign near_mem$dmem_master_rdata = dmem_master_rdata ; - assign near_mem$dmem_master_rid = dmem_master_rid ; - assign near_mem$dmem_master_rlast = dmem_master_rlast ; - assign near_mem$dmem_master_rresp = dmem_master_rresp ; - assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; - assign near_mem$dmem_master_wready = dmem_master_wready ; - assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h14648 ; - assign near_mem$dmem_req_amo_funct7 = - x_out_data_to_stage2_val1__h14649[6:0] ; - assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h14645[14:12] ; - assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ; - always@(IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373) - begin - case (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373) - 3'd1: near_mem$dmem_req_op = 2'd0; - 3'd2: near_mem$dmem_req_op = 2'd1; - default: near_mem$dmem_req_op = 2'd2; - endcase - end - assign near_mem$dmem_req_priv = - csr_regfile$read_mstatus[17] ? - csr_regfile$read_mstatus[12:11] : - rg_cur_priv ; - assign near_mem$dmem_req_satp = csr_regfile$read_satp ; - assign near_mem$dmem_req_sstatus_SUM = csr_regfile$read_sstatus[18] ; - assign near_mem$dmem_req_store_value = x_out_data_to_stage2_val2__h14650 ; - assign near_mem$imem_master_arready = imem_master_arready ; - assign near_mem$imem_master_awready = imem_master_awready ; - assign near_mem$imem_master_bid = imem_master_bid ; - assign near_mem$imem_master_bresp = imem_master_bresp ; - assign near_mem$imem_master_bvalid = imem_master_bvalid ; - assign near_mem$imem_master_rdata = imem_master_rdata ; - assign near_mem$imem_master_rid = imem_master_rid ; - assign near_mem$imem_master_rlast = imem_master_rlast ; - assign near_mem$imem_master_rresp = imem_master_rresp ; - assign near_mem$imem_master_rvalid = imem_master_rvalid ; - assign near_mem$imem_master_wready = imem_master_wready ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_near_mem$imem_req_2__VAL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - MUX_near_mem$imem_req_2__VAL_2 or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - next_pc___1__h18221 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_trap_fetch or - MUX_near_mem$imem_req_2__VAL_5 or MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1; - MUX_imem_rg_f3$write_1__SEL_2: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_addr = next_pc___1__h18221; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - default: near_mem$imem_req_addr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_f3 = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_mstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_mstatus_MXR or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_mstatus_MXR) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_mstatus_MXR = imem_rg_mstatus_MXR; - default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_priv = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - MUX_near_mem$imem_req_1__SEL_6) ? - rg_cur_priv : - imem_rg_priv ; - assign near_mem$imem_req_satp = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? - imem_rg_satp : - csr_regfile$read_satp ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_sstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_sstatus_SUM or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_sstatus_SUM) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_sstatus_SUM = csr_regfile$read_sstatus[18]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_sstatus_SUM = imem_rg_sstatus_SUM; - default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$server_fence_request_put = - 8'b10101010 /* unspecified value */ ; - assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ; - assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ; - assign near_mem$EN_imem_req = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 || - WILL_FIRE_RL_imem_rl_fetch_next_32b || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_dmem_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 && - (IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == - 3'd1 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == - 3'd2 || - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == - 3'd4) ; - assign near_mem$EN_server_fence_i_request_put = - MUX_rg_state$write_1__SEL_8 ; - assign near_mem$EN_server_fence_i_response_get = - CAN_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_9 ; - assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ; - assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_10 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule stage1_f_reset_reqs - assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage1_f_reset_rsps - assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage1_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_f_reset_reqs - assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage2_f_reset_reqs$DEQ = CAN_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage2_f_reset_rsps - assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage2_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_fbox - assign stage2_fbox$req_f7 = x_out_data_to_stage2_instr__h14645[31:25] ; - assign stage2_fbox$req_opcode = x_out_data_to_stage2_instr__h14645[6:0] ; - assign stage2_fbox$req_rm = x_out_data_to_stage2_rounding_mode__h14653 ; - assign stage2_fbox$req_rs2 = x_out_data_to_stage2_instr__h14645[24:20] ; - assign stage2_fbox$req_v1 = x_out_data_to_stage2_val1__h14649 ; - assign stage2_fbox$req_v2 = x_out_data_to_stage2_val2__h14650 ; - assign stage2_fbox$req_v3 = x_out_data_to_stage2_val3__h14651 ; - assign stage2_fbox$EN_server_reset_request_put = - CAN_FIRE_RL_stage2_rl_reset_begin ; - assign stage2_fbox$EN_server_reset_response_get = - CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_fbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == - 3'd5 ; - - // submodule stage2_mbox - assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h14645[14:12] ; - assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4607[3] ; - assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h14649 ; - assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h14650 ; - assign stage2_mbox$set_verbosity_verbosity = 4'h0 ; - assign stage2_mbox$EN_set_verbosity = 1'b0 ; - assign stage2_mbox$EN_req_reset = 1'b0 ; - assign stage2_mbox$EN_rsp_reset = 1'b0 ; - assign stage2_mbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == - 3'd3 ; - - // submodule stage3_f_reset_reqs - assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage3_f_reset_rsps - assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage3_f_reset_rsps$CLR = 1'b0 ; - - // remaining internal signals - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 = - (_theResult____h4607[6:0] == 7'b1100011) ? - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 : - _theResult____h4607[6:0] == 7'b1101111 || - _theResult____h4607[6:0] == 7'b1100111 || - (_theResult____h4607[6:0] != 7'b0110011 || - _theResult____h4607[31:25] != 7'b0000001) && - (_theResult____h4607[6:0] != 7'b0111011 || - _theResult____h4607[31:25] != 7'b0000001) && - (_theResult____h4607[6:0] != 7'b0010011 && - _theResult____h4607[6:0] != 7'b0110011 || - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b101) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026 = - (_theResult____h4607[6:0] == 7'b1100011) ? - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 : - _theResult____h4607[6:0] != 7'b1101111 && - _theResult____h4607[6:0] != 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 = - (_theResult____h4607[6:0] == 7'b1100011) ? - (_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 : - _theResult____h4607[6:0] != 7'b1101111 && - _theResult____h4607[6:0] != 7'b1100111 && - (IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1043 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207 = - (_theResult____h4607[6:0] == 7'b1100011) ? - (_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 : - _theResult____h4607[6:0] == 7'b1101111 || - _theResult____h4607[6:0] == 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1220 = - ((_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b011) && - (_theResult____h4607[6:0] != 7'b0000111 || - csr_regfile$read_mstatus[14:13] != 2'h0)) ? - 4'd0 : - 4'd11 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1224 = - ((_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011) && - (_theResult____h4607[6:0] != 7'b0100111 || - csr_regfile$read_mstatus[14:13] != 2'h0)) ? - 4'd0 : - 4'd11 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1262 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1235 ? - 4'd6 : - ((_theResult____h4607[11:7] == 5'd0 && - _theResult____h4607[19:15] == 5'd0) ? - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1260 : - 4'd11) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1558 = - ((_theResult____h4607[6:0] == 7'b0010011 || - _theResult____h4607[6:0] == 7'b0110011) && - (_theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101)) ? - alu_outputs___1_val1__h14946 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1559 = - ((_theResult____h4607[6:0] == 7'b0110011 || - _theResult____h4607[6:0] == 7'b0111011) && - _theResult____h4607[31:25] == 7'b0000001) ? - rs1_val_bypassed__h4615 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1558 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1576 = - ((_theResult____h4607[6:0] == 7'b0110011 || - _theResult____h4607[6:0] == 7'b0111011) && - _theResult____h4607[31:25] == 7'b0000001) ? - rs2_val_bypassed__h4621 : - CASE_theResult__607_BITS_6_TO_0_0b100011_alu_o_ETC__q23 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1750 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - rs1_val_bypassed__h4615 == rs2_val_bypassed__h4621 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688 = - (rs1_val_bypassed__h4615 ^ 64'h8000000000000000) < - (rs2_val_bypassed__h4621 ^ 64'h8000000000000000) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690 = - rs1_val_bypassed__h4615 < rs2_val_bypassed__h4621 ; - assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1214 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d733 ? - 4'd11 : - 4'd0 ; - assign IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1270 = - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1190 ? - 4'd0 : - 4'd11 ; - assign IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d258 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - ((stage2_rg_stage2[3] || stage2_rg_stage2[264:260] == 5'd0) ? - 2'd0 : - IF_near_mem_dmem_valid__25_AND_NOT_near_mem_dm_ETC___d256) : - 2'd0 ; - assign IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d284 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - (stage2_rg_stage2[3] ? - IF_near_mem_dmem_valid__25_AND_NOT_near_mem_dm_ETC___d256 : - 2'd0) : - 2'd0 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1043 = - _theResult____h4607[6:0] == 7'b0110011 && - _theResult____h4607[31:25] == 7'b0000001 || - _theResult____h4607[6:0] == 7'b0111011 && - _theResult____h4607[31:25] == 7'b0000001 || - (_theResult____h4607[6:0] == 7'b0010011 || - _theResult____h4607[6:0] == 7'b0110011) && - (_theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101) ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1050 = - _theResult____h4607[14:12] == 3'b0 && - (_theResult____h4607[6:0] != 7'b0110011 || - !_theResult____h4607[30]) || - _theResult____h4607[14:12] == 3'b0 && - _theResult____h4607[6:0] == 7'b0110011 && - _theResult____h4607[30] || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b111 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1235 = - _theResult____h4607[11:7] == 5'd0 && - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) && - _theResult____h4607[31:25] == 7'b0001001 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1432 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 ? - next_pc___1__h18221 : - next_pc__h18219 ; - assign IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 = - near_mem$imem_exc ? - 4'd11 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1285 ; - assign IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d2002 = - imem_rg_pc == csr_regfile$csr_trap_actions[193:130] ; - assign IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 = - (!stage2_rg_full || stage2_rg_stage2[267:265] == 3'd0) ? - 2'd0 : - CASE_stage2_rg_stage2_BITS_267_TO_265_1_IF_NOT_ETC__q3 ; - assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1952 = - csr_regfile$read_csr[63:0] | rs1_val__h23782 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b001) ? - instr__h14206 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b101) ? - instr__h14357 : - 32'h0) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:13] == 3'b101) ? - instr__h14007 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d590 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[11:7] != 5'd0 && - instr__h4605[15:13] == 3'b001 && - csr_regfile$read_misa[3]) ? - instr__h13854 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d591 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b111) ? - instr__h12815 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d592 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b011) ? - instr__h12664 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d593 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:13] == 3'b111) ? - instr__h12465 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d594 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:12] == 4'b1001 && - instr__h4605[11:7] == 5'd0 && - instr__h4605[6:2] == 5'd0) ? - instr__h12216 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[11:7] != 5'd0 && - instr__h4605[15:13] == 3'b011) ? - instr__h12312 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d595) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d599 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100111 && - instr__h4605[6:5] == 2'b01) ? - instr__h11920 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100111 && - instr__h4605[6:5] == 2'b0) ? - instr__h12058 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d597) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d601 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100011 && - instr__h4605[6:5] == 2'b01) ? - instr__h11646 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100011 && - instr__h4605[6:5] == 2'b0) ? - instr__h11782 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d599) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d603 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100011 && - instr__h4605[6:5] == 2'b11) ? - instr__h11374 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:10] == 6'b100011 && - instr__h4605[6:5] == 2'b10) ? - instr__h11510 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d601) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d604 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d417 && - instr__h4605[6:2] != 5'd0) ? - instr__h11279 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d603 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d605 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d411 && - instr__h4605[6:2] != 5'd0) ? - instr__h11160 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d604 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d607 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b100 && - instr__h4605[11:10] == 2'b01 && - imm6__h9273 != 6'd0) ? - instr__h10865 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b100 && - instr__h4605[11:10] == 2'b10) ? - instr__h10982 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d605) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d608 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b100 && - instr__h4605[11:10] == 2'b0 && - imm6__h9273 != 6'd0) ? - instr__h10676 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d607 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d609 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:13] == 3'b0 && - instr__h4605[11:7] != 5'd0 && - imm6__h9273 != 6'd0) ? - instr__h10487 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d608 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d611 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b011 && - instr__h4605[11:7] == 5'd2 && - nzimm10__h9942 != 10'd0) ? - instr__h10146 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b0 && - nzimm10__h10157 != 10'd0) ? - instr__h10318 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d609) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d613 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b0 && - instr__h4605[11:7] != 5'd0 && - imm6__h9273 != 6'd0 || - csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b0 && - instr__h4605[11:7] == 5'd0 && - imm6__h9273 == 6'd0) ? - instr__h9664 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b001 && - instr__h4605[11:7] != 5'd0) ? - instr__h9891 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d611) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d614 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b011 && - instr__h4605[11:7] != 5'd0 && - instr__h4605[11:7] != 5'd2 && - imm6__h9273 != 6'd0) ? - instr__h9535 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d613 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d616 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b111) ? - instr__h9013 : - ((csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b010 && - instr__h4605[11:7] != 5'd0) ? - instr__h9351 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d614) ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d617 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b110) ? - instr__h8696 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d616 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d618 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d417 && - instr__h4605[6:2] == 5'd0) ? - instr__h8631 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d617 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d619 = - (csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d411 && - instr__h4605[6:2] == 5'd0) ? - instr__h8515 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d618 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d620 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b01 && - instr__h4605[15:13] == 3'b101) ? - instr__h8061 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d619 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d621 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b110) ? - instr__h7832 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d620 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d622 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b0 && - instr__h4605[15:13] == 3'b010) ? - instr__h7637 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d621 ; - assign IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d623 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:13] == 3'b110) ? - instr__h7445 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d622 ; - assign IF_near_mem_dmem_valid__25_AND_NOT_near_mem_dm_ETC___d256 = - (near_mem$dmem_valid && !near_mem$dmem_exc) ? 2'd2 : 2'd1 ; - assign IF_near_mem_dmem_valid__25_THEN_IF_near_mem_dm_ETC___d128 = - near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ; - assign IF_rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7__ETC___d1258 = - ((rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) && - _theResult____h4607[31:20] == 12'b000100000010) ? - 4'd8 : - (rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7_EQ__ETC___d1256 ? - 4'd10 : - 4'd11) ; - assign IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132 = - stage2_fbox$valid ? 2'd2 : 2'd1 ; - assign IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130 = - stage2_mbox$valid ? 2'd2 : 2'd1 ; - assign IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1 : - 2'd0 ; - assign IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 : - 2'd0 ; - assign IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627 = - x_out_bypass_rd__h6724 == _theResult____h4607[19:15] ; - assign IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629 = - x_out_bypass_rd__h6724 == _theResult____h4607[24:20] ; - assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d733 = - (_theResult____h4607[14:12] != 3'b0 || - _theResult____h4607[6:0] == 7'b0110011 && - _theResult____h4607[30]) && - (_theResult____h4607[14:12] != 3'b0 || - _theResult____h4607[6:0] != 7'b0110011 || - !_theResult____h4607[30]) && - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b011 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b111 ; - assign NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 = - cur_verbosity__h3134 > 4'd1 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - (!stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1779) && - (!stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1771) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1824 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1824 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd2 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd0) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1824 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd2 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd0) && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210 || - !stage1_rg_full ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1895 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__48_OR_IF_IF_NOT_n_ETC___d1893) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1897 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__48_OR_IF_IF_NOT_n_ETC___d1893) && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd2 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd0) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1900 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1897 && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210 || - !stage1_rg_full) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1914 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) ; - assign NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1190 = - csr_regfile$read_mstatus[14:13] != 2'h0 && - CASE_theResult__607_BITS_6_TO_0_0b1000011_theR_ETC__q13 && - ((_theResult____h4607[14:12] == 3'b111) ? - csr_regfile$read_frm != 3'b101 && - csr_regfile$read_frm != 3'b110 && - csr_regfile$read_frm != 3'b111 : - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b110) ; - assign NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1353 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd4 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd5 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd6 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd7 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd8 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd9 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd10 ; - assign NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1403 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 != - 3'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 != - 3'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 != - 3'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 != - 3'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 != - 3'd4 ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 = - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] != 2'b11) ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] == 2'b11) && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] == 2'b11) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1760 = - !near_mem$imem_valid || - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == - 2'd1 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1771 = - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632 || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1779 = - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026 ; - assign NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632 = - !near_mem$imem_valid || - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d322 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == - 2'd1 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629) ; - assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1441 = - { {52{theResult__607_BITS_31_TO_20__q20[11]}}, - theResult__607_BITS_31_TO_20__q20 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401 = - { {9{offset__h8008[11]}}, offset__h8008 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426 = - { {4{offset__h8640[8]}}, offset__h8640 } ; - assign _0_OR_0_OR_near_mem_imem_exc__48_OR_IF_IF_NOT_n_ETC___d1893 = - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026 ; - assign _theResult_____1_fst__h16238 = - (_theResult____h4607[14:12] == 3'b0 && - _theResult____h4607[6:0] == 7'b0110011 && - _theResult____h4607[30]) ? - rd_val___1__h16234 : - _theResult_____1_fst__h16245 ; - assign _theResult_____1_fst__h16273 = - rs1_val_bypassed__h4615 & _theResult___snd__h18728 ; - assign _theResult_____1_fst_rd_val__h6703 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - _theResult_____2_fst_rd_val__h6700 : - stage2_rg_stage2[195:132] ; - assign _theResult_____1_snd_fst_rd_val__h6859 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - _theResult_____2_snd_rd_val__h6856 : - stage2_rg_stage2[195:132] ; - assign _theResult_____2_fst_rd_val__h6700 = - (stage2_rg_stage2[3] || stage2_rg_stage2[264:260] == 5'd0) ? - stage2_rg_stage2[195:132] : - near_mem$dmem_word64 ; - assign _theResult_____2_snd_rd_val__h6856 = - stage2_rg_stage2[3] ? - data_to_stage3_rd_val__h6144 : - stage2_rg_stage2[195:132] ; - assign _theResult____h28496 = - (delta_CPI_instrs__h28495 == 64'd0) ? - delta_CPI_instrs___1__h28531 : - delta_CPI_instrs__h28495 ; - assign _theResult____h4607 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_ETC___d317 ? - instr___1__h7021 : - instr__h4605 ; - assign _theResult___fst__h16363 = - (_theResult____h4607[14:12] == 3'b001 && - !_theResult____h4607[25]) ? - rd_val___1__h18790 : - _theResult___fst__h16370 ; - assign _theResult___fst__h16370 = - _theResult____h4607[30] ? - rd_val___1__h18873 : - rd_val___1__h18844 ; - assign _theResult___fst__h16490 = - { {32{rs1_val_bypassed615_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8[31]}}, - rs1_val_bypassed615_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8 } ; - assign _theResult___fst__h7200 = - (near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11) ? - instr_out___1__h7202 : - _theResult___fst__h7228 ; - assign _theResult___fst__h7228 = - (near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11) ? - instr_out___1__h7230 : - near_mem$imem_instr ; - assign _theResult___fst_rd_val__h6714 = - stage2_rg_stage2[3] ? - stage2_rg_stage2[195:132] : - stage2_fbox$word_fst ; - assign _theResult___snd__h18728 = - (_theResult____h4607[6:0] == 7'b0010011) ? - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1441 : - rs2_val_bypassed__h4621 ; - assign _theResult___snd_rd_val__h6865 = - stage2_rg_stage2[3] ? - stage2_fbox$word_fst : - stage2_rg_stage2[195:132] ; - assign alu_outputs___1_addr5117_BITS_31_TO_0__q21 = - alu_outputs___1_addr__h15117[31:0] ; - assign alu_outputs___1_addr__h14775 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 ? - branch_target__h14754 : - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1432 ; - assign alu_outputs___1_addr__h14799 = - imem_rg_pc + - { {43{theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q5[20]}}, - theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q5 } ; - assign alu_outputs___1_addr__h14828 = - { alu_outputs___1_addr__h15117[63:1], 1'd0 } ; - assign alu_outputs___1_addr__h15117 = - rs1_val_bypassed__h4615 + - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d1441 ; - assign alu_outputs___1_addr__h15141 = - rs1_val_bypassed__h4615 + - { {52{theResult__607_BITS_31_TO_25_CONCAT_theResult__ETC__q6[11]}}, - theResult__607_BITS_31_TO_25_CONCAT_theResult__ETC__q6 } ; - assign alu_outputs___1_exc_code__h15424 = - (_theResult____h4607[14:12] == 3'b0) ? - (IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1235 ? - 4'd2 : - ((_theResult____h4607[11:7] == 5'd0 && - _theResult____h4607[19:15] == 5'd0) ? - CASE_theResult__607_BITS_31_TO_20_0b0_CASE_rg__ETC__q16 : - 4'd2)) : - 4'd2 ; - assign alu_outputs___1_val1__h14946 = - (_theResult____h4607[14:12] == 3'b001) ? - rd_val__h18622 : - (_theResult____h4607[30] ? rd_val__h18696 : rd_val__h18674) ; - assign alu_outputs___1_val1__h14987 = - (_theResult____h4607[14:12] == 3'b0 && - (_theResult____h4607[6:0] != 7'b0110011 || - !_theResult____h4607[30])) ? - rd_val___1__h16226 : - _theResult_____1_fst__h16238 ; - assign alu_outputs___1_val1__h15013 = - (_theResult____h4607[14:12] == 3'b0) ? - rd_val___1__h18759 : - _theResult___fst__h16363 ; - assign alu_outputs___1_val1__h15058 = - { {32{v32__h15047[31]}}, v32__h15047 } ; - assign alu_outputs___1_val1__h15077 = - imem_rg_pc + alu_outputs___1_val1__h15058 ; - assign alu_outputs___1_val1__h15428 = - _theResult____h4607[14] ? - { 59'd0, _theResult____h4607[19:15] } : - rs1_val_bypassed__h4615 ; - assign alu_outputs___1_val1__h15452 = - { 57'd0, _theResult____h4607[31:25] } ; - assign alu_outputs___1_val1__h15653 = - (_theResult____h4607[6:0] == 7'b1010011 && - (_theResult____h4607[31:25] == 7'h69 && - (_theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2 || - _theResult____h4607[24:20] == 5'd3) || - _theResult____h4607[31:25] == 7'h79 || - _theResult____h4607[31:25] == 7'h68 && - (_theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2 || - _theResult____h4607[24:20] == 5'd3) || - _theResult____h4607[31:25] == 7'h78)) ? - rs1_val_bypassed__h4615 : - frs1_val_bypassed__h4626 ; - assign alu_outputs___1_val2__h15143 = - (_theResult____h4607[6:0] == 7'b0100111) ? - frs2_val_bypassed__h4631 : - rs2_val_bypassed__h4621 ; - assign branch_target__h14754 = - imem_rg_pc + - { {51{theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q4[12]}}, - theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q4 } ; - assign cpi__h28498 = x__h28497 / 64'd10 ; - assign cpifrac__h28499 = x__h28497 % 64'd10 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1753 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1749 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1750 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1758 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd2 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd0 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1764 = - csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1753 || - (csr_regfile_interrupt_pending_rg_cur_priv_7_74_ETC___d1758 || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1760 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - stage1_rg_full ; - assign csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d2005 = - delta_CPI_cycles__h28494 * 64'd10 ; - assign csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d411 = - csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:12] == 4'b1000 && - instr__h4605[11:7] != 5'd0 ; - assign csr_regfile_read_misa__4_BIT_2_24_AND_IF_near__ETC___d417 = - csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[15:12] == 4'b1001 && - instr__h4605[11:7] != 5'd0 ; - assign csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d1000 = - csr_regfile$read_mstatus[14:13] == 2'h0 || - CASE_theResult__607_BITS_6_TO_0_0b1000011_NOT__ETC__q11 || - ((_theResult____h4607[14:12] == 3'b111) ? - csr_regfile$read_frm == 3'b101 || - csr_regfile$read_frm == 3'b110 || - csr_regfile$read_frm == 3'b111 : - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b110) ; - assign cur_verbosity__h3134 = - (csr_regfile$read_csr_minstret < cfg_logdelay) ? - 4'd0 : - cfg_verbosity ; - assign data_to_stage2_addr__h14637 = x_out_data_to_stage2_addr__h14648 ; - assign data_to_stage3_rd_val__h6144 = - stage2_rg_stage2[3] ? - ((stage2_rg_stage2[282:280] == 3'b010) ? - { 32'hFFFFFFFF, near_mem$dmem_word64[31:0] } : - near_mem$dmem_word64) : - near_mem$dmem_word64 ; - assign delta_CPI_cycles__h28494 = - csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ; - assign delta_CPI_instrs___1__h28531 = delta_CPI_instrs__h28495 + 64'd1 ; - assign delta_CPI_instrs__h28495 = - csr_regfile$read_csr_minstret - rg_start_CPI_instrs ; - assign fall_through_pc__h14598 = - imem_rg_pc + - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d639 ? - 64'd4 : - 64'd2) ; - assign fpr_regfile_RDY_server_reset_request_put__697__ETC___d1709 = - fpr_regfile$RDY_server_reset_request_put && - near_mem$RDY_server_reset_request_put && - csr_regfile$RDY_server_reset_request_put && - f_reset_reqs$EMPTY_N && - stage1_f_reset_reqs$FULL_N && - stage2_f_reset_reqs$FULL_N && - stage3_f_reset_reqs$FULL_N ; - assign frs1_val_bypassed__h4626 = - (IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6873 == _theResult____h4607[19:15]) ? - x_out_fbypass_rd_val__h6874 : - rd_val__h19313 ; - assign frs2_val_bypassed__h4631 = - (IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6873 == _theResult____h4607[24:20]) ? - x_out_fbypass_rd_val__h6874 : - rd_val__h19369 ; - assign funct10__h15025 = - { _theResult____h4607[31:25], _theResult____h4607[14:12] } ; - assign imm12__h10159 = { 2'd0, nzimm10__h10157 } ; - assign imm12__h10355 = { 6'b0, imm6__h9273 } ; - assign imm12__h10692 = { 6'b010000, imm6__h9273 } ; - assign imm12__h12313 = { 3'd0, offset__h12227 } ; - assign imm12__h12665 = { 4'd0, offset__h12599 } ; - assign imm12__h7301 = { 4'd0, offset__h7071 } ; - assign imm12__h7638 = { 5'd0, offset__h7580 } ; - assign imm12__h9275 = { {6{imm6__h9273[5]}}, imm6__h9273 } ; - assign imm12__h9944 = { {2{nzimm10__h9942[9]}}, nzimm10__h9942 } ; - assign imm20__h9403 = { {14{imm6__h9273[5]}}, imm6__h9273 } ; - assign imm6__h9273 = { instr__h4605[12], instr__h4605[6:2] } ; - assign instr___1__h7021 = - (csr_regfile$read_misa[2] && instr__h4605[1:0] == 2'b10 && - instr__h4605[11:7] != 5'd0 && - instr__h4605[15:13] == 3'b010) ? - instr__h7300 : - IF_csr_regfile_read_misa__4_BIT_2_24_AND_IF_ne_ETC___d623 ; - assign instr__h10146 = - { imm12__h9944, - instr__h4605[11:7], - 3'b0, - instr__h4605[11:7], - 7'b0010011 } ; - assign instr__h10318 = { imm12__h10159, 8'd16, rd__h7640, 7'b0010011 } ; - assign instr__h10487 = - { imm12__h10355, - instr__h4605[11:7], - 3'b001, - instr__h4605[11:7], - 7'b0010011 } ; - assign instr__h10676 = - { imm12__h10355, rs1__h7639, 3'b101, rs1__h7639, 7'b0010011 } ; - assign instr__h10865 = - { imm12__h10692, rs1__h7639, 3'b101, rs1__h7639, 7'b0010011 } ; - assign instr__h10982 = - { imm12__h9275, rs1__h7639, 3'b111, rs1__h7639, 7'b0010011 } ; - assign instr__h11160 = - { 7'b0, - instr__h4605[6:2], - 8'd0, - instr__h4605[11:7], - 7'b0110011 } ; - assign instr__h11279 = - { 7'b0, - instr__h4605[6:2], - instr__h4605[11:7], - 3'b0, - instr__h4605[11:7], - 7'b0110011 } ; - assign instr__h11374 = - { 7'b0, rd__h7640, rs1__h7639, 3'b111, rs1__h7639, 7'b0110011 } ; - assign instr__h11510 = - { 7'b0, rd__h7640, rs1__h7639, 3'b110, rs1__h7639, 7'b0110011 } ; - assign instr__h11646 = - { 7'b0, rd__h7640, rs1__h7639, 3'b100, rs1__h7639, 7'b0110011 } ; - assign instr__h11782 = - { 7'b0100000, - rd__h7640, - rs1__h7639, - 3'b0, - rs1__h7639, - 7'b0110011 } ; - assign instr__h11920 = - { 7'b0, rd__h7640, rs1__h7639, 3'b0, rs1__h7639, 7'b0111011 } ; - assign instr__h12058 = - { 7'b0100000, - rd__h7640, - rs1__h7639, - 3'b0, - rs1__h7639, - 7'b0111011 } ; - assign instr__h12216 = - { 12'b000000000001, - instr__h4605[11:7], - 3'b0, - instr__h4605[11:7], - 7'b1110011 } ; - assign instr__h12312 = - { imm12__h12313, 8'd19, instr__h4605[11:7], 7'b0000011 } ; - assign instr__h12465 = - { 3'd0, - instr__h4605[9:7], - instr__h4605[12], - instr__h4605[6:2], - 8'd19, - offset_BITS_4_TO_0___h12940, - 7'b0100011 } ; - assign instr__h12664 = - { imm12__h12665, rs1__h7639, 3'b011, rd__h7640, 7'b0000011 } ; - assign instr__h12815 = - { 4'd0, - instr__h4605[6:5], - instr__h4605[12], - rd__h7640, - rs1__h7639, - 3'b011, - offset_BITS_4_TO_0___h12940, - 7'b0100011 } ; - assign instr__h13854 = - { imm12__h12313, 8'd19, instr__h4605[11:7], 7'b0000111 } ; - assign instr__h14007 = - { 3'd0, - instr__h4605[9:7], - instr__h4605[12], - instr__h4605[6:2], - 8'd19, - offset_BITS_4_TO_0___h12940, - 7'b0100111 } ; - assign instr__h14206 = - { imm12__h12665, rs1__h7639, 3'b011, rd__h7640, 7'b0000111 } ; - assign instr__h14357 = - { 4'd0, - instr__h4605[6:5], - instr__h4605[12], - rd__h7640, - rs1__h7639, - 3'b011, - offset_BITS_4_TO_0___h12940, - 7'b0100111 } ; - assign instr__h4605 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 ? - instr_out___1__h7170 : - _theResult___fst__h7200 ; - assign instr__h7300 = - { imm12__h7301, 8'd18, instr__h4605[11:7], 7'b0000011 } ; - assign instr__h7445 = - { 4'd0, - instr__h4605[8:7], - instr__h4605[12], - instr__h4605[6:2], - 8'd18, - offset_BITS_4_TO_0___h7569, - 7'b0100011 } ; - assign instr__h7637 = - { imm12__h7638, rs1__h7639, 3'b010, rd__h7640, 7'b0000011 } ; - assign instr__h7832 = - { 5'd0, - instr__h4605[5], - instr__h4605[12], - rd__h7640, - rs1__h7639, - 3'b010, - offset_BITS_4_TO_0___h8000, - 7'b0100011 } ; - assign instr__h8061 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d401[19:12], - 12'd111 } ; - assign instr__h8515 = { 12'd0, instr__h4605[11:7], 15'd103 } ; - assign instr__h8631 = { 12'd0, instr__h4605[11:7], 15'd231 } ; - assign instr__h8696 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[10:5], - 5'd0, - rs1__h7639, - 3'b0, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[11], - 7'b1100011 } ; - assign instr__h9013 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[10:5], - 5'd0, - rs1__h7639, - 3'b001, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d426[11], - 7'b1100011 } ; - assign instr__h9351 = - { imm12__h9275, 8'd0, instr__h4605[11:7], 7'b0010011 } ; - assign instr__h9535 = { imm20__h9403, instr__h4605[11:7], 7'b0110111 } ; - assign instr__h9664 = - { imm12__h9275, - instr__h4605[11:7], - 3'b0, - instr__h4605[11:7], - 7'b0010011 } ; - assign instr__h9891 = - { imm12__h9275, - instr__h4605[11:7], - 3'b0, - instr__h4605[11:7], - 7'b0011011 } ; - assign instr_out___1__h7170 = - { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ; - assign instr_out___1__h7202 = { 16'b0, near_mem$imem_instr[15:0] } ; - assign instr_out___1__h7230 = { 16'b0, near_mem$imem_instr[31:16] } ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1603 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd0 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1606 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd1 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1609 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd2 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1612 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd3 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1615 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd4 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1618 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd5 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1621 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd6 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1624 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd7 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1627 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd8 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1630 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd9 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1633 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == - 4'd10 ; - assign near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1636 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd0 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd1 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd2 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd3 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd4 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd5 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd6 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd7 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd8 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd9 && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 != - 4'd10 ; - assign near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 = - near_mem$imem_pc[63:2] == imem_rg_pc[63:2] ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d639 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] == 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d641 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d639 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 = - near_mem$imem_pc == next_pc___1__h18221 ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1015 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1026) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1749 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d309 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 != - 2'd1 || - !IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627 && - !IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d641 && - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 != - 2'd1 || - !IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627 && - !IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629) ; - assign next_pc___1__h18221 = imem_rg_pc + 64'd2 ; - assign next_pc__h18219 = imem_rg_pc + 64'd4 ; - assign nzimm10__h10157 = - { instr__h4605[10:7], - instr__h4605[12:11], - instr__h4605[5], - instr__h4605[6], - 2'b0 } ; - assign nzimm10__h9942 = - { instr__h4605[12], - instr__h4605[4:3], - instr__h4605[5], - instr__h4605[2], - instr__h4605[6], - 4'b0 } ; - assign offset_BITS_4_TO_0___h12940 = { instr__h4605[11:10], 3'b0 } ; - assign offset_BITS_4_TO_0___h7569 = { instr__h4605[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h8000 = - { instr__h4605[11:10], instr__h4605[6], 2'b0 } ; - assign offset__h12227 = - { instr__h4605[4:2], - instr__h4605[12], - instr__h4605[6:5], - 3'b0 } ; - assign offset__h12599 = { instr__h4605[6:5], instr__h4605[12:10], 3'b0 } ; - assign offset__h7071 = - { instr__h4605[3:2], - instr__h4605[12], - instr__h4605[6:4], - 2'b0 } ; - assign offset__h7580 = - { instr__h4605[5], instr__h4605[12:10], instr__h4605[6], 2'b0 } ; - assign offset__h8008 = - { instr__h4605[12], - instr__h4605[8], - instr__h4605[10:9], - instr__h4605[6], - instr__h4605[7], - instr__h4605[2], - instr__h4605[11], - instr__h4605[5:3], - 1'b0 } ; - assign offset__h8640 = - { instr__h4605[12], - instr__h4605[6:5], - instr__h4605[2], - instr__h4605[11:10], - instr__h4605[4:3], - 1'b0 } ; - assign rd__h7640 = { 2'b01, instr__h4605[4:2] } ; - assign rd_val___1__h16226 = - rs1_val_bypassed__h4615 + _theResult___snd__h18728 ; - assign rd_val___1__h16234 = - rs1_val_bypassed__h4615 - _theResult___snd__h18728 ; - assign rd_val___1__h16241 = - ((rs1_val_bypassed__h4615 ^ 64'h8000000000000000) < - (_theResult___snd__h18728 ^ 64'h8000000000000000)) ? - 64'd1 : - 64'd0 ; - assign rd_val___1__h16248 = - (rs1_val_bypassed__h4615 < _theResult___snd__h18728) ? - 64'd1 : - 64'd0 ; - assign rd_val___1__h16255 = - rs1_val_bypassed__h4615 ^ _theResult___snd__h18728 ; - assign rd_val___1__h16262 = - rs1_val_bypassed__h4615 | _theResult___snd__h18728 ; - assign rd_val___1__h18759 = - { {32{alu_outputs___1_addr5117_BITS_31_TO_0__q21[31]}}, - alu_outputs___1_addr5117_BITS_31_TO_0__q21 } ; - assign rd_val___1__h18790 = { {32{x__h18793[31]}}, x__h18793 } ; - assign rd_val___1__h18844 = { {32{x__h18847[31]}}, x__h18847 } ; - assign rd_val___1__h18873 = { {32{tmp__h18872[31]}}, tmp__h18872 } ; - assign rd_val___1__h18927 = - { {32{rs1_val_bypassed615_BITS_31_TO_0_PLUS_rs2_val__ETC__q9[31]}}, - rs1_val_bypassed615_BITS_31_TO_0_PLUS_rs2_val__ETC__q9 } ; - assign rd_val___1__h18975 = - { {32{rs1_val_bypassed615_BITS_31_TO_0_MINUS_rs2_val_ETC__q10[31]}}, - rs1_val_bypassed615_BITS_31_TO_0_MINUS_rs2_val_ETC__q10 } ; - assign rd_val___1__h18981 = { {32{x__h18984[31]}}, x__h18984 } ; - assign rd_val___1__h19026 = { {32{x__h19029[31]}}, x__h19029 } ; - assign rd_val__h14531 = - (!stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d672) ? - stage3_rg_stage3[63:0] : - gpr_regfile$read_rs1 ; - assign rd_val__h14574 = - (!stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d680) ? - stage3_rg_stage3[63:0] : - gpr_regfile$read_rs2 ; - assign rd_val__h18622 = rs1_val_bypassed__h4615 << shamt__h14931 ; - assign rd_val__h18674 = rs1_val_bypassed__h4615 >> shamt__h14931 ; - assign rd_val__h18696 = - rs1_val_bypassed__h4615 >> shamt__h14931 | - ~(64'hFFFFFFFFFFFFFFFF >> shamt__h14931) & - {64{rs1_val_bypassed__h4615[63]}} ; - assign rd_val__h19313 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d672) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs1 ; - assign rd_val__h19369 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d680) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs2 ; - assign rd_val__h19422 = - (stage3_rg_stage3[69] && stage3_rg_full && - stage3_rg_stage3[76] && - stage3_rg_stage3[75:71] == _theResult____h4607[31:27]) ? - stage3_rg_stage3[63:0] : - fpr_regfile$read_rs3 ; - assign rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7_EQ__ETC___d1256 = - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] || - rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) && - _theResult____h4607[31:20] == 12'b000100000101 ; - assign rg_state_6_EQ_3_766_AND_NOT_csr_regfile_interr_ETC___d1917 = - rg_state == 4'd3 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1914 && - !stage3_rg_full && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == - 2'd0 ; - assign rg_state_6_EQ_3_766_AND_stage3_rg_full_6_OR_NO_ETC___d1785 = - rg_state == 4'd3 && - (stage3_rg_full || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd0 || - stage1_rg_full) && - (stage3_rg_full || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd3) && - (stage3_rg_full || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd0 || - !stage1_rg_full || - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d1771) && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 || - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != - 2'd0 || - stage3_rg_full) ; - assign rm__h15556 = x_out_data_to_stage2_rounding_mode__h14653 ; - assign rs1__h7639 = { 2'b01, instr__h4605[9:7] } ; - assign rs1_val__h23289 = - (x_out_data_to_stage2_instr__h14645[14:12] == 3'b001) ? - x_out_data_to_stage2_val1__h14649 : - { 59'd0, x_out_data_to_stage2_instr__h14645[19:15] } ; - assign rs1_val_bypassed615_BITS_31_TO_0_MINUS_rs2_val_ETC__q10 = - rs1_val_bypassed__h4615[31:0] - rs2_val_bypassed__h4621[31:0] ; - assign rs1_val_bypassed615_BITS_31_TO_0_PLUS_rs2_val__ETC__q9 = - rs1_val_bypassed__h4615[31:0] + rs2_val_bypassed__h4621[31:0] ; - assign rs1_val_bypassed615_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8 = - rs1_val_bypassed__h4615[31:0] >> rs2_val_bypassed__h4621[4:0] | - ~(32'hFFFFFFFF >> rs2_val_bypassed__h4621[4:0]) & - {32{rs1_val_bypassed615_BITS_31_TO_0__q7[31]}} ; - assign rs1_val_bypassed615_BITS_31_TO_0__q7 = - rs1_val_bypassed__h4615[31:0] ; - assign rs1_val_bypassed__h4615 = - (_theResult____h4607[19:15] == 5'd0) ? 64'd0 : val__h14533 ; - assign rs2_val_bypassed__h4621 = - (_theResult____h4607[24:20] == 5'd0) ? 64'd0 : val__h14576 ; - assign shamt__h14931 = - (_theResult____h4607[6:0] == 7'b0010011) ? - _theResult____h4607[25:20] : - rs2_val_bypassed__h4621[5:0] ; - assign stage2_f_reset_rsps_i_notEmpty__720_AND_stage3_ETC___d1729 = - stage2_f_reset_rsps$EMPTY_N && stage3_f_reset_rsps$EMPTY_N && - f_reset_rsps$FULL_N && - (!rg_run_on_reset || - !near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) ; - assign stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d672 = - stage3_rg_stage3[75:71] == _theResult____h4607[19:15] ; - assign stage3_rg_stage3_8_BITS_75_TO_71_7_EQ_IF_NOT_n_ETC___d680 = - stage3_rg_stage3[75:71] == _theResult____h4607[24:20] ; - assign sxl__h5045 = - (csr_regfile$read_misa[27:26] == 2'd2) ? - csr_regfile$read_mstatus[35:34] : - 2'd0 ; - assign theResult__607_BITS_31_TO_20__q20 = _theResult____h4607[31:20] ; - assign theResult__607_BITS_31_TO_25_CONCAT_theResult__ETC__q6 = - { _theResult____h4607[31:25], _theResult____h4607[11:7] } ; - assign theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q4 = - { _theResult____h4607[31], - _theResult____h4607[7], - _theResult____h4607[30:25], - _theResult____h4607[11:8], - 1'b0 } ; - assign theResult__607_BIT_31_CONCAT_theResult__607_BI_ETC__q5 = - { _theResult____h4607[31], - _theResult____h4607[19:12], - _theResult____h4607[20], - _theResult____h4607[30:21], - 1'b0 } ; - assign tmp__h18872 = - rs1_val_bypassed__h4615[31:0] >> _theResult____h4607[24:20] | - ~(32'hFFFFFFFF >> _theResult____h4607[24:20]) & - {32{rs1_val_bypassed615_BITS_31_TO_0__q7[31]}} ; - assign trap_info_tval__h18051 = - (_theResult____h4607[6:0] != 7'b1101111 && - _theResult____h4607[6:0] != 7'b1100111 && - (_theResult____h4607[6:0] != 7'b1110011 || - _theResult____h4607[14:12] != 3'b0 || - _theResult____h4607[11:7] != 5'd0 || - _theResult____h4607[19:15] != 5'd0 || - _theResult____h4607[31:20] != 12'b0 && - _theResult____h4607[31:20] != 12'b000000000001)) ? - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_09_OR__ETC___d639 ? - { 32'd0, _theResult____h4607 } : - { 48'd0, instr__h4605[15:0] }) : - CASE_theResult__607_BITS_6_TO_0_0b1100111_data_ETC__q22 ; - assign uxl__h5046 = - (csr_regfile$read_misa[27:26] == 2'd2) ? - csr_regfile$read_mstatus[33:32] : - 2'd0 ; - assign v32__h15047 = { _theResult____h4607[31:12], 12'h0 } ; - assign val__h14533 = - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == - 2'd2 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d627) ? - x_out_bypass_rd_val__h6725 : - rd_val__h14531 ; - assign val__h14576 = - (IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == - 2'd2 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d629) ? - x_out_bypass_rd_val__h6725 : - rd_val__h14574 ; - assign value__h18109 = - near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h18051 ; - assign x__h18793 = - rs1_val_bypassed__h4615[31:0] << _theResult____h4607[24:20] ; - assign x__h18847 = - rs1_val_bypassed__h4615[31:0] >> _theResult____h4607[24:20] ; - assign x__h18984 = - rs1_val_bypassed__h4615[31:0] << rs2_val_bypassed__h4621[4:0] ; - assign x__h19029 = - rs1_val_bypassed__h4615[31:0] >> rs2_val_bypassed__h4621[4:0] ; - assign x__h28497 = - csr_regfile_read_csr_mcycle__6_MINUS_rg_start__ETC___d2005[63:0] / - _theResult____h28496 ; - assign x_out_data_to_stage2_instr__h14645 = _theResult____h4607 ; - assign x_out_data_to_stage2_rounding_mode__h14653 = - (_theResult____h4607[14:12] == 3'b111) ? - csr_regfile$read_frm : - _theResult____h4607[14:12] ; - assign x_out_data_to_stage2_val2__h14650 = - (_theResult____h4607[6:0] == 7'b1100011) ? - branch_target__h14754 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1576 ; - assign x_out_data_to_stage2_val3__h14651 = - (IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == - 2'd2 && - x_out_fbypass_rd__h6873 == _theResult____h4607[31:27]) ? - x_out_fbypass_rd_val__h6874 : - rd_val__h19422 ; - assign x_out_next_pc__h14611 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207 ? - data_to_stage2_addr__h14637 : - fall_through_pc__h14598 ; - assign x_out_trap_info_exc_code__h18054 = - near_mem$imem_exc ? - near_mem$imem_exc_code : - alu_outputs_exc_code__h15680 ; - assign y__h24086 = ~rs1_val__h23782 ; - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd2, 3'd4: value__h6429 = stage2_rg_stage2[363:300]; - default: value__h6429 = stage2_rg_stage2[363:300]; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_exc_code) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd2, 3'd4: - x_out_trap_info_exc_code__h6466 = near_mem$dmem_exc_code; - default: x_out_trap_info_exc_code__h6466 = 4'd2; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd2, 3'd4: value__h6490 = stage2_rg_stage2[259:196]; - default: value__h6490 = 64'd0; - endcase - end - always@(stage2_rg_stage2 or stage2_fbox$word_snd) - begin - case (stage2_rg_stage2[267:265]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - x_out_data_to_stage3_fpr_flags__h6249 = 5'd0; - default: x_out_data_to_stage3_fpr_flags__h6249 = stage2_fbox$word_snd; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[267:265]) - 3'd0, 3'd1, 3'd4: - x_out_data_to_stage3_rd__h6246 = stage2_rg_stage2[264:260]; - 3'd2: x_out_data_to_stage3_rd__h6246 = 5'd0; - default: x_out_data_to_stage3_rd__h6246 = stage2_rg_stage2[264:260]; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[267:265]) - 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h6724 = stage2_rg_stage2[264:260]; - default: x_out_bypass_rd__h6724 = stage2_rg_stage2[264:260]; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd4: x_out_fbypass_rd__h6873 = stage2_rg_stage2[264:260]; - default: x_out_fbypass_rd__h6873 = stage2_rg_stage2[264:260]; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$word_fst or - data_to_stage3_rd_val__h6144 or stage2_mbox$word) - begin - case (stage2_rg_stage2[267:265]) - 3'd0: x_out_data_to_stage3_rd_val__h6250 = stage2_rg_stage2[195:132]; - 3'd1, 3'd4: - x_out_data_to_stage3_rd_val__h6250 = data_to_stage3_rd_val__h6144; - 3'd3: x_out_data_to_stage3_rd_val__h6250 = stage2_mbox$word; - default: x_out_data_to_stage3_rd_val__h6250 = stage2_fbox$word_fst; - endcase - end - always@(stage2_rg_stage2 or - _theResult___fst_rd_val__h6714 or - _theResult_____1_fst_rd_val__h6703 or stage2_mbox$word) - begin - case (stage2_rg_stage2[267:265]) - 3'd0: x_out_bypass_rd_val__h6725 = stage2_rg_stage2[195:132]; - 3'd1, 3'd4: - x_out_bypass_rd_val__h6725 = _theResult_____1_fst_rd_val__h6703; - 3'd3: x_out_bypass_rd_val__h6725 = stage2_mbox$word; - default: x_out_bypass_rd_val__h6725 = _theResult___fst_rd_val__h6714; - endcase - end - always@(stage2_rg_stage2 or - _theResult___snd_rd_val__h6865 or - _theResult_____1_snd_fst_rd_val__h6859) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd4: - x_out_fbypass_rd_val__h6874 = - _theResult_____1_snd_fst_rd_val__h6859; - default: x_out_fbypass_rd_val__h6874 = _theResult___snd_rd_val__h6865; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132 or - IF_near_mem_dmem_valid__25_THEN_IF_near_mem_dm_ETC___d128 or - IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130) - begin - case (stage2_rg_stage2[267:265]) - 3'd0: CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1 = 2'd2; - 3'd1, 3'd2, 3'd4: - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1 = - IF_near_mem_dmem_valid__25_THEN_IF_near_mem_dm_ETC___d128; - 3'd3: - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1 = - IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130; - default: CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q1 = - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$valid or - near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153 = - !near_mem$dmem_valid || near_mem$dmem_exc; - 3'd3: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153 = - !stage2_mbox$valid; - default: IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153 = - !stage2_fbox$valid; - endcase - end - always@(stage2_rg_stage2 or - stage2_fbox$valid or - near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163 = - near_mem$dmem_valid && !near_mem$dmem_exc; - 3'd3: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163 = - stage2_mbox$valid; - default: IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163 = - stage2_fbox$valid; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd4: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) && - stage2_rg_stage2[3]; - default: IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198 = - stage2_rg_stage2[267:265] != 3'd2 && - stage2_rg_stage2[267:265] != 3'd3 && - stage2_rg_stage2[3]; - endcase - end - always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd4: - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d232 = - near_mem$dmem_valid && near_mem$dmem_exc || - !stage2_rg_stage2[3]; - default: IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d232 = - stage2_rg_stage2[267:265] == 3'd2 || - stage2_rg_stage2[267:265] == 3'd3 || - !stage2_rg_stage2[3]; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132 or - IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d258 or - IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130) - begin - case (stage2_rg_stage2[267:265]) - 3'd0: CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 = 2'd2; - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 = - IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d258; - 3'd2: CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 = 2'd0; - 3'd3: - CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 = - IF_stage2_mbox_valid__29_THEN_2_ELSE_1___d130; - default: CASE_stage2_rg_stage2_BITS_267_TO_265_0_2_1_IF_ETC__q2 = - stage2_rg_stage2[3] ? - 2'd0 : - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132 or - IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d284) - begin - case (stage2_rg_stage2[267:265]) - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_267_TO_265_1_IF_NOT_ETC__q3 = - IF_NOT_near_mem_dmem_valid__25_47_OR_NOT_near__ETC___d284; - 3'd2, 3'd3: - CASE_stage2_rg_stage2_BITS_267_TO_265_1_IF_NOT_ETC__q3 = 2'd0; - default: CASE_stage2_rg_stage2_BITS_267_TO_265_1_IF_NOT_ETC__q3 = - stage2_rg_stage2[3] ? - IF_stage2_fbox_valid__31_THEN_2_ELSE_1___d132 : - 2'd0; - endcase - end - always@(_theResult____h4607) - begin - case (_theResult____h4607[6:0]) - 7'b0000011, - 7'b0000111, - 7'b0010011, - 7'b0010111, - 7'b0011011, - 7'b0110011, - 7'b0110111, - 7'b0111011, - 7'b1100111, - 7'b1101111: - x_out_data_to_stage2_rd__h14647 = _theResult____h4607[11:7]; - 7'b1100011: x_out_data_to_stage2_rd__h14647 = 5'd0; - default: x_out_data_to_stage2_rd__h14647 = _theResult____h4607[11:7]; - endcase - end - always@(funct10__h15025 or - _theResult___fst__h16490 or - rd_val___1__h18927 or - rd_val___1__h18981 or rd_val___1__h19026 or rd_val___1__h18975) - begin - case (funct10__h15025) - 10'b0: alu_outputs___1_val1__h15039 = rd_val___1__h18927; - 10'b0000000001: alu_outputs___1_val1__h15039 = rd_val___1__h18981; - 10'b0000000101: alu_outputs___1_val1__h15039 = rd_val___1__h19026; - 10'b0100000000: alu_outputs___1_val1__h15039 = rd_val___1__h18975; - default: alu_outputs___1_val1__h15039 = _theResult___fst__h16490; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) - begin - case (_theResult____h4607[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1021 = - _theResult____h4607[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) - begin - case (_theResult____h4607[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 = - _theResult____h4607[14:12] == 3'b111 && - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d690; - endcase - end - always@(_theResult____h4607 or rm__h15556) - begin - case (_theResult____h4607[6:0]) - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111: - CASE_theResult__607_BITS_6_TO_0_0b1000011_NOT__ETC__q11 = - _theResult____h4607[26:25] != 2'b0 && - _theResult____h4607[26:25] != 2'b01; - default: CASE_theResult__607_BITS_6_TO_0_0b1000011_NOT__ETC__q11 = - _theResult____h4607[31:25] != 7'h0 && - _theResult____h4607[31:25] != 7'h04 && - _theResult____h4607[31:25] != 7'h08 && - _theResult____h4607[31:25] != 7'h0C && - _theResult____h4607[31:25] != 7'h2C && - (_theResult____h4607[31:25] != 7'h10 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h10 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h10 || - rm__h15556 != 3'd2) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h60 || - _theResult____h4607[24:20] != 5'd3) && - (_theResult____h4607[31:25] != 7'h68 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h68 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h68 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h68 || - _theResult____h4607[24:20] != 5'd3) && - (_theResult____h4607[31:25] != 7'h14 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h14 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h50 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h50 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h50 || - rm__h15556 != 3'd2) && - (_theResult____h4607[31:25] != 7'h70 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h78 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h70 || - rm__h15556 != 3'd1) && - _theResult____h4607[31:25] != 7'b0000001 && - _theResult____h4607[31:25] != 7'h05 && - _theResult____h4607[31:25] != 7'b0001001 && - _theResult____h4607[31:25] != 7'h0D && - _theResult____h4607[31:25] != 7'h2D && - (_theResult____h4607[31:25] != 7'h11 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h11 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h11 || - rm__h15556 != 3'd2) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h61 || - _theResult____h4607[24:20] != 5'd3) && - (_theResult____h4607[31:25] != 7'h69 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h69 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h69 || - _theResult____h4607[24:20] != 5'd2) && - (_theResult____h4607[31:25] != 7'h69 || - _theResult____h4607[24:20] != 5'd3) && - (_theResult____h4607[31:25] != 7'h21 || - _theResult____h4607[24:20] != 5'd0) && - (_theResult____h4607[31:25] != 7'h20 || - _theResult____h4607[24:20] != 5'd1) && - (_theResult____h4607[31:25] != 7'h15 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h15 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h51 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h51 || - rm__h15556 != 3'd1) && - (_theResult____h4607[31:25] != 7'h51 || - rm__h15556 != 3'd2) && - (_theResult____h4607[31:25] != 7'h71 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h79 || - rm__h15556 != 3'd0) && - (_theResult____h4607[31:25] != 7'h71 || - rm__h15556 != 3'd1); - endcase - end - always@(_theResult____h4607 or - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d1000 or - csr_regfile$read_mstatus) - begin - case (_theResult____h4607[6:0]) - 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004 = - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b011 || - csr_regfile$read_mstatus[14:13] == 2'h0; - 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004 = - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b011 || - csr_regfile$read_mstatus[14:13] == 2'h0; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004 = - _theResult____h4607[31:27] != 5'b00010 && - _theResult____h4607[31:27] != 5'b00011 && - _theResult____h4607[31:27] != 5'b0 && - _theResult____h4607[31:27] != 5'b00001 && - _theResult____h4607[31:27] != 5'b01100 && - _theResult____h4607[31:27] != 5'b01000 && - _theResult____h4607[31:27] != 5'b00100 && - _theResult____h4607[31:27] != 5'b10000 && - _theResult____h4607[31:27] != 5'b11000 && - _theResult____h4607[31:27] != 5'b10100 && - _theResult____h4607[31:27] != 5'b11100 || - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b011; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004 = - _theResult____h4607[6:0] != 7'b1010011 && - _theResult____h4607[6:0] != 7'b1000011 && - _theResult____h4607[6:0] != 7'b1000111 && - _theResult____h4607[6:0] != 7'b1001011 && - _theResult____h4607[6:0] != 7'b1001111 || - csr_regfile_read_mstatus__8_BITS_14_TO_13_9_EQ_ETC___d1000; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004) - begin - case (_theResult____h4607[6:0]) - 7'b0000011: - CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b011; - 7'b0100011: - CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b010 && - _theResult____h4607[14:12] != 3'b011; - default: CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4607[6:0] == 7'b0001111 || - _theResult____h4607[6:0] == 7'b1110011 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1004; - endcase - end - always@(_theResult____h4607 or - CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 or - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d733 or - funct10__h15025) - begin - case (_theResult____h4607[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d733; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012 = - _theResult____h4607[14:12] != 3'b0 && - (_theResult____h4607[14:12] != 3'b001 || - _theResult____h4607[25]) && - (_theResult____h4607[14:12] != 3'b101 || - _theResult____h4607[25]); - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012 = - funct10__h15025 != 10'b0 && funct10__h15025 != 10'b0100000000 && - funct10__h15025 != 10'b0000000001 && - funct10__h15025 != 10'b0000000101 && - funct10__h15025 != 10'b0100000101; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1012 = - _theResult____h4607[6:0] != 7'b0110111 && - _theResult____h4607[6:0] != 7'b0010111 && - CASE_theResult__607_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12; - endcase - end - always@(_theResult____h4607 or rm__h15556) - begin - case (_theResult____h4607[6:0]) - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111: - CASE_theResult__607_BITS_6_TO_0_0b1000011_theR_ETC__q13 = - _theResult____h4607[26:25] == 2'b0 || - _theResult____h4607[26:25] == 2'b01; - default: CASE_theResult__607_BITS_6_TO_0_0b1000011_theR_ETC__q13 = - _theResult____h4607[31:25] == 7'h0 || - _theResult____h4607[31:25] == 7'h04 || - _theResult____h4607[31:25] == 7'h08 || - _theResult____h4607[31:25] == 7'h0C || - _theResult____h4607[31:25] == 7'h2C || - _theResult____h4607[31:25] == 7'h10 && - (rm__h15556 == 3'd0 || rm__h15556 == 3'd1 || - rm__h15556 == 3'd2) || - _theResult____h4607[31:25] == 7'h60 && - _theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[31:25] == 7'h60 && - (_theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2 || - _theResult____h4607[24:20] == 5'd3) || - _theResult____h4607[31:25] == 7'h68 && - (_theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2) || - _theResult____h4607[31:25] == 7'h68 && - _theResult____h4607[24:20] == 5'd3 || - _theResult____h4607[31:25] == 7'h14 && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h14 && - rm__h15556 == 3'd1 || - _theResult____h4607[31:25] == 7'h50 && - (rm__h15556 == 3'd0 || rm__h15556 == 3'd1) || - _theResult____h4607[31:25] == 7'h50 && - rm__h15556 == 3'd2 || - (_theResult____h4607[31:25] == 7'h70 || - _theResult____h4607[31:25] == 7'h78) && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h70 && - rm__h15556 == 3'd1 || - _theResult____h4607[31:25] == 7'b0000001 || - _theResult____h4607[31:25] == 7'h05 || - _theResult____h4607[31:25] == 7'b0001001 || - _theResult____h4607[31:25] == 7'h0D || - _theResult____h4607[31:25] == 7'h2D || - _theResult____h4607[31:25] == 7'h11 && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h11 && - (rm__h15556 == 3'd1 || rm__h15556 == 3'd2) || - _theResult____h4607[31:25] == 7'h61 && - _theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[31:25] == 7'h61 && - (_theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2 || - _theResult____h4607[24:20] == 5'd3) || - _theResult____h4607[31:25] == 7'h69 && - (_theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[24:20] == 5'd2) || - _theResult____h4607[31:25] == 7'h69 && - _theResult____h4607[24:20] == 5'd3 || - _theResult____h4607[31:25] == 7'h21 && - _theResult____h4607[24:20] == 5'd0 || - _theResult____h4607[31:25] == 7'h20 && - _theResult____h4607[24:20] == 5'd1 || - _theResult____h4607[31:25] == 7'h15 && - (rm__h15556 == 3'd0 || rm__h15556 == 3'd1) || - _theResult____h4607[31:25] == 7'h51 && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h51 && - (rm__h15556 == 3'd1 || rm__h15556 == 3'd2) || - _theResult____h4607[31:25] == 7'h71 && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h79 && - rm__h15556 == 3'd0 || - _theResult____h4607[31:25] == 7'h71 && rm__h15556 == 3'd1; - endcase - end - always@(_theResult____h4607 or - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1190 or - csr_regfile$read_mstatus) - begin - case (_theResult____h4607[6:0]) - 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194 = - (_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b011) && - csr_regfile$read_mstatus[14:13] != 2'h0; - 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194 = - (_theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011) && - csr_regfile$read_mstatus[14:13] != 2'h0; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194 = - (_theResult____h4607[31:27] == 5'b00010 || - _theResult____h4607[31:27] == 5'b00011 || - _theResult____h4607[31:27] == 5'b0 || - _theResult____h4607[31:27] == 5'b00001 || - _theResult____h4607[31:27] == 5'b01100 || - _theResult____h4607[31:27] == 5'b01000 || - _theResult____h4607[31:27] == 5'b00100 || - _theResult____h4607[31:27] == 5'b10000 || - _theResult____h4607[31:27] == 5'b11000 || - _theResult____h4607[31:27] == 5'b10100 || - _theResult____h4607[31:27] == 5'b11100) && - (_theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011); - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194 = - (_theResult____h4607[6:0] == 7'b1010011 || - _theResult____h4607[6:0] == 7'b1000011 || - _theResult____h4607[6:0] == 7'b1000111 || - _theResult____h4607[6:0] == 7'b1001011 || - _theResult____h4607[6:0] == 7'b1001111) && - NOT_csr_regfile_read_mstatus__8_BITS_14_TO_13__ETC___d1190; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194) - begin - case (_theResult____h4607[6:0]) - 7'b0000011: - CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14 = - _theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b100 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b110 || - _theResult____h4607[14:12] == 3'b011; - 7'b0100011: - CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14 = - _theResult____h4607[14:12] == 3'b0 || - _theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011; - default: CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14 = - _theResult____h4607[6:0] != 7'b0001111 && - _theResult____h4607[6:0] != 7'b1110011 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1194; - endcase - end - always@(_theResult____h4607 or - CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1050 or - funct10__h15025) - begin - case (_theResult____h4607[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1050; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202 = - _theResult____h4607[14:12] == 3'b0 || - (_theResult____h4607[14:12] == 3'b001 || - _theResult____h4607[14:12] == 3'b101) && - !_theResult____h4607[25]; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202 = - funct10__h15025 == 10'b0 || funct10__h15025 == 10'b0100000000 || - funct10__h15025 == 10'b0000000001 || - funct10__h15025 == 10'b0000000101 || - funct10__h15025 == 10'b0100000101; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1202 = - _theResult____h4607[6:0] == 7'b0110111 || - _theResult____h4607[6:0] == 7'b0010111 || - CASE_theResult__607_BITS_6_TO_0_0b11_theResult_ETC__q14; - endcase - end - always@(rg_cur_priv) - begin - case (rg_cur_priv) - 2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd8; - 2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd9; - default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd11; - endcase - end - always@(_theResult____h4607 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q15) - begin - case (_theResult____h4607[31:20]) - 12'b0: - CASE_theResult__607_BITS_31_TO_20_0b0_CASE_rg__ETC__q16 = - CASE_rg_cur_priv_0b0_8_0b1_9_11__q15; - 12'b000000000001: - CASE_theResult__607_BITS_31_TO_20_0b0_CASE_rg__ETC__q16 = 4'd3; - default: CASE_theResult__607_BITS_31_TO_20_0b0_CASE_rg__ETC__q16 = 4'd2; - endcase - end - always@(_theResult____h4607 or alu_outputs___1_exc_code__h15424) - begin - case (_theResult____h4607[6:0]) - 7'b0000011, - 7'b0001111, - 7'b0010011, - 7'b0010111, - 7'b0011011, - 7'b0100011, - 7'b0110011, - 7'b0110111, - 7'b0111011, - 7'b1100011: - alu_outputs_exc_code__h15680 = 4'd2; - 7'b1100111, 7'b1101111: alu_outputs_exc_code__h15680 = 4'd0; - 7'b1110011: - alu_outputs_exc_code__h15680 = alu_outputs___1_exc_code__h15424; - default: alu_outputs_exc_code__h15680 = 4'd2; - endcase - end - always@(_theResult____h4607 or - rg_cur_priv or - IF_rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7__ETC___d1258) - begin - case (_theResult____h4607[31:20]) - 12'b0, 12'b000000000001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1260 = 4'd11; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1260 = - (rg_cur_priv == 2'b11 && - _theResult____h4607[31:20] == 12'b001100000010) ? - 4'd7 : - IF_rg_cur_priv_7_EQ_0b11_229_OR_rg_cur_priv_7__ETC___d1258; - endcase - end - always@(_theResult____h4607) - begin - case (_theResult____h4607[14:12]) - 3'b0: CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17 = 4'd4; - 3'b001: CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17 = 4'd5; - default: CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17 = 4'd11; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1262) - begin - case (_theResult____h4607[14:12]) - 3'b0: - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1262; - 3'b001, 3'b101: - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18 = 4'd2; - 3'b010, 3'b011, 3'b110, 3'b111: - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18 = 4'd3; - 3'd4: CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18 = 4'd11; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1220 or - CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17 or - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1214 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1224 or - funct10__h15025 or - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1270 or - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18) - begin - case (_theResult____h4607[6:0]) - 7'b0000011, 7'b0000111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1220; - 7'b0001111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - CASE_theResult__607_BITS_14_TO_12_0b0_4_0b1_5_11__q17; - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d1214; - 7'b0010111, 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = 4'd0; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - (_theResult____h4607[14:12] != 3'b0 && - (_theResult____h4607[14:12] != 3'b001 || - _theResult____h4607[25]) && - (_theResult____h4607[14:12] != 3'b101 || - _theResult____h4607[25])) ? - 4'd11 : - 4'd0; - 7'b0100011, 7'b0100111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1224; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - ((_theResult____h4607[31:27] == 5'b00010 || - _theResult____h4607[31:27] == 5'b00011 || - _theResult____h4607[31:27] == 5'b0 || - _theResult____h4607[31:27] == 5'b00001 || - _theResult____h4607[31:27] == 5'b01100 || - _theResult____h4607[31:27] == 5'b01000 || - _theResult____h4607[31:27] == 5'b00100 || - _theResult____h4607[31:27] == 5'b10000 || - _theResult____h4607[31:27] == 5'b11000 || - _theResult____h4607[31:27] == 5'b10100 || - _theResult____h4607[31:27] == 5'b11100) && - (_theResult____h4607[14:12] == 3'b010 || - _theResult____h4607[14:12] == 3'b011)) ? - 4'd0 : - 4'd11; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - (funct10__h15025 != 10'b0 && - funct10__h15025 != 10'b0100000000 && - funct10__h15025 != 10'b0000000001 && - funct10__h15025 != 10'b0000000101 && - funct10__h15025 != 10'b0100000101) ? - 4'd11 : - 4'd0; - 7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111, 7'b1010011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - IF_NOT_csr_regfile_read_mstatus__8_BITS_14_TO__ETC___d1270; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - CASE_theResult__607_BITS_14_TO_12_0b0_IF_IF_NO_ETC__q18; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 = - 4'd11; - endcase - end - always@(_theResult____h4607 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1043 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697) - begin - case (_theResult____h4607[6:0]) - 7'b1100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1285 = - (_theResult____h4607[14:12] != 3'b0 && - _theResult____h4607[14:12] != 3'b001 && - _theResult____h4607[14:12] != 3'b100 && - _theResult____h4607[14:12] != 3'b101 && - _theResult____h4607[14:12] != 3'b110 && - _theResult____h4607[14:12] != 3'b111) ? - 4'd11 : - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d697 ? - 4'd1 : - 4'd0); - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1285 = 4'd1; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1285 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1043 ? - 4'd0 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1282; - endcase - end - always@(_theResult____h4607) - begin - case (_theResult____h4607[6:0]) - 7'b0000011, 7'b0000111: - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19 = 3'd1; - 7'b0010011, 7'b0010111, 7'b0011011, 7'b0110011, 7'b0110111, 7'b0111011: - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19 = 3'd0; - 7'b0100011, 7'b0100111: - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19 = 3'd2; - 7'b0101111: - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19 = 3'd4; - default: CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19 = 3'd5; - endcase - end - always@(_theResult____h4607 or - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19) - begin - case (_theResult____h4607[6:0]) - 7'b1100011, 7'b1100111, 7'b1101111: - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 = 3'd0; - default: IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 = - ((_theResult____h4607[6:0] == 7'b0110011 || - _theResult____h4607[6:0] == 7'b0111011) && - _theResult____h4607[31:25] == 7'b0000001) ? - 3'd3 : - CASE_theResult__607_BITS_6_TO_0_0b11_1_0b111_1_ETC__q19; - endcase - end - always@(_theResult____h4607 or - _theResult_____1_fst__h16273 or - rd_val___1__h16241 or - rd_val___1__h16248 or rd_val___1__h16255 or rd_val___1__h16262) - begin - case (_theResult____h4607[14:12]) - 3'b010: _theResult_____1_fst__h16245 = rd_val___1__h16241; - 3'b011: _theResult_____1_fst__h16245 = rd_val___1__h16248; - 3'b100: _theResult_____1_fst__h16245 = rd_val___1__h16255; - 3'b110: _theResult_____1_fst__h16245 = rd_val___1__h16262; - default: _theResult_____1_fst__h16245 = _theResult_____1_fst__h16273; - endcase - end - always@(_theResult____h4607 or - alu_outputs___1_addr__h15141 or - alu_outputs___1_addr__h15117 or - rs1_val_bypassed__h4615 or - alu_outputs___1_addr__h14775 or - alu_outputs___1_addr__h14828 or alu_outputs___1_addr__h14799) - begin - case (_theResult____h4607[6:0]) - 7'b0000011, 7'b0000111: - x_out_data_to_stage2_addr__h14648 = alu_outputs___1_addr__h15117; - 7'b0100011: - x_out_data_to_stage2_addr__h14648 = alu_outputs___1_addr__h15141; - 7'b0101111: x_out_data_to_stage2_addr__h14648 = rs1_val_bypassed__h4615; - 7'b1100011: - x_out_data_to_stage2_addr__h14648 = alu_outputs___1_addr__h14775; - 7'b1100111: - x_out_data_to_stage2_addr__h14648 = alu_outputs___1_addr__h14828; - 7'b1101111: - x_out_data_to_stage2_addr__h14648 = alu_outputs___1_addr__h14799; - default: x_out_data_to_stage2_addr__h14648 = - alu_outputs___1_addr__h15141; - endcase - end - always@(_theResult____h4607 or imem_rg_pc or data_to_stage2_addr__h14637) - begin - case (_theResult____h4607[6:0]) - 7'b1100111, 7'b1101111: - CASE_theResult__607_BITS_6_TO_0_0b1100111_data_ETC__q22 = - data_to_stage2_addr__h14637; - default: CASE_theResult__607_BITS_6_TO_0_0b1100111_data_ETC__q22 = - (_theResult____h4607[6:0] == 7'b1110011 && - _theResult____h4607[14:12] == 3'b0 && - _theResult____h4607[11:7] == 5'd0 && - _theResult____h4607[19:15] == 5'd0 && - _theResult____h4607[31:20] == 12'b000000000001) ? - imem_rg_pc : - 64'd0; - endcase - end - always@(_theResult____h4607 or - frs2_val_bypassed__h4631 or - alu_outputs___1_val2__h15143 or rs2_val_bypassed__h4621) - begin - case (_theResult____h4607[6:0]) - 7'b0100011, 7'b0100111: - CASE_theResult__607_BITS_6_TO_0_0b100011_alu_o_ETC__q23 = - alu_outputs___1_val2__h15143; - 7'b0101111: - CASE_theResult__607_BITS_6_TO_0_0b100011_alu_o_ETC__q23 = - rs2_val_bypassed__h4621; - default: CASE_theResult__607_BITS_6_TO_0_0b100011_alu_o_ETC__q23 = - frs2_val_bypassed__h4631; - endcase - end - always@(_theResult____h4607 or - alu_outputs___1_val1__h15653 or - alu_outputs___1_val1__h14987 or - alu_outputs___1_val1__h15077 or - alu_outputs___1_val1__h15013 or - alu_outputs___1_val1__h15452 or - alu_outputs___1_val1__h15058 or - alu_outputs___1_val1__h15039 or alu_outputs___1_val1__h15428) - begin - case (_theResult____h4607[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h14987; - 7'b0010111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15077; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15013; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15452; - 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15058; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15039; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15428; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1557 = - alu_outputs___1_val1__h15653; - endcase - end - always@(_theResult____h4607 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1559 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1432) - begin - case (_theResult____h4607[6:0]) - 7'b1100111, 7'b1101111: - x_out_data_to_stage2_val1__h14649 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d1432; - default: x_out_data_to_stage2_val1__h14649 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1559; - endcase - end - always@(x_out_data_to_stage2_instr__h14645 or - x_out_data_to_stage2_val1__h14649) - begin - case (x_out_data_to_stage2_instr__h14645[14:12]) - 3'b010, 3'b011: rs1_val__h23782 = x_out_data_to_stage2_val1__h14649; - default: rs1_val__h23782 = - { 59'd0, x_out_data_to_stage2_instr__h14645[19:15] }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0; - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11; - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_logdelay$EN) - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN; - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_cur_priv$EN) - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN; - if (rg_run_on_reset$EN) - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (stage1_rg_full$EN) - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN; - if (stage2_rg_full$EN) - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN; - if (stage2_rg_resetting$EN) - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY - stage2_rg_resetting$D_IN; - if (stage3_rg_full$EN) - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN; - end - if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN; - if (imem_rg_instr_15_0$EN) - imem_rg_instr_15_0 <= `BSV_ASSIGNMENT_DELAY imem_rg_instr_15_0$D_IN; - if (imem_rg_mstatus_MXR$EN) - imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN; - if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN; - if (imem_rg_priv$EN) - imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN; - if (imem_rg_satp$EN) - imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN; - if (imem_rg_sstatus_SUM$EN) - imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN; - if (imem_rg_tval$EN) - imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_start_CPI_cycles$EN) - rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN; - if (rg_start_CPI_instrs$EN) - rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN; - if (stage2_rg_stage2$EN) - stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN; - if (stage3_rg_stage3$EN) - stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_logdelay = 64'hAAAAAAAAAAAAAAAA; - cfg_verbosity = 4'hA; - imem_rg_f3 = 3'h2; - imem_rg_instr_15_0 = 16'hAAAA; - imem_rg_mstatus_MXR = 1'h0; - imem_rg_pc = 64'hAAAAAAAAAAAAAAAA; - imem_rg_priv = 2'h2; - imem_rg_satp = 64'hAAAAAAAAAAAAAAAA; - imem_rg_sstatus_SUM = 1'h0; - imem_rg_tval = 64'hAAAAAAAAAAAAAAAA; - rg_cur_priv = 2'h2; - rg_mstatus_MXR = 1'h0; - rg_next_pc = 64'hAAAAAAAAAAAAAAAA; - rg_run_on_reset = 1'h0; - rg_sstatus_SUM = 1'h0; - rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA; - rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - stage1_rg_full = 1'h0; - stage2_rg_full = 1'h0; - stage2_rg_resetting = 1'h0; - stage2_rg_stage2 = - 366'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - stage3_rg_full = 1'h0; - stage3_rg_stage3 = 175'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - rg_cur_priv, - csr_regfile$read_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write("MStatus{", - "sd:%0d", - csr_regfile$read_mstatus[14:13] == 2'h3 || - csr_regfile$read_mstatus[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2) - $write(" sxl:%0d uxl:%0d", sxl__h5045, uxl__h5046); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tsr:%0d", csr_regfile$read_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tw:%0d", csr_regfile$read_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tvm:%0d", csr_regfile$read_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mxr:%0d", csr_regfile$read_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" sum:%0d", csr_regfile$read_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mprv:%0d", csr_regfile$read_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" xs:%0d", csr_regfile$read_mstatus[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" fs:%0d", csr_regfile$read_mstatus[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mpp:%0d", csr_regfile$read_mstatus[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" spp:%0d", csr_regfile$read_mstatus[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" pies:%0d_%0d%0d", - csr_regfile$read_mstatus[7], - csr_regfile$read_mstatus[5], - csr_regfile$read_mstatus[4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" ies:%0d_%0d%0d", - csr_regfile$read_mstatus[3], - csr_regfile$read_mstatus[1], - csr_regfile$read_mstatus[0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("Rd %0d ", stage3_rg_stage3[75:71]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("rd_val:%h", stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write("FRd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("FRd %0d ", stage3_rg_stage3[75:71]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[76])) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] && - stage3_rg_full && - stage3_rg_stage3[76]) - $write("frd_val:%h", stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage2: pc 0x%08h instr 0x%08h priv %0d", - stage2_rg_stage2[363:300], - stage2_rg_stage2[299:268], - stage2_rg_stage2[365:364]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write("Output_Stage2", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[363:300]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("Output_Stage2", " NONPIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write("Output_Stage2", " PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[363:300], - stage2_rg_stage2[299:268], - stage2_rg_stage2[365:364]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - stage2_rg_stage2[267:265] != 3'd0 && - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - (stage2_rg_stage2[267:265] == 3'd0 || - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - stage2_rg_stage2[267:265] != 3'd0 && - stage2_rg_stage2[267:265] != 3'd1 && - stage2_rg_stage2[267:265] != 3'd4 && - stage2_rg_stage2[267:265] != 3'd2 && - stage2_rg_stage2[267:265] != 3'd3) - $write(" fflags: %05b", - "'h%h", - x_out_data_to_stage3_fpr_flags__h6249); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - (stage2_rg_stage2[267:265] == 3'd0 || - stage2_rg_stage2[267:265] == 3'd1 || - stage2_rg_stage2[267:265] == 3'd4 || - stage2_rg_stage2[267:265] == 3'd2 || - stage2_rg_stage2[267:265] == 3'd3)) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - stage2_rg_stage2[267:265] != 3'd0 && - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198) - $write(" frd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6246, - x_out_data_to_stage3_rd_val__h6250); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3 && - (stage2_rg_stage2[267:265] == 3'd0 || - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d232)) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6246, - x_out_data_to_stage3_rd_val__h6250); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", value__h6429); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", x_out_trap_info_exc_code__h6466); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", value__h6490, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", value__h6429); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", x_out_trap_info_exc_code__h6466); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd3) - $write("'h%h", value__h6490, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd1 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == 2'd0) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 != 2'd0) - $write("Rd %0d ", x_out_bypass_rd__h6724); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 != 2'd0 && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d265 != 2'd1) - $write("rd_val:%h", x_out_bypass_rd_val__h6725); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == 2'd0) - $write("FRd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 != 2'd0) - $write("FRd %0d ", x_out_fbypass_rd__h6873); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 != 2'd0 && - IF_NOT_stage2_rg_full_01_38_OR_stage2_rg_stage_ETC___d289 != 2'd1) - $write("frd_val:%h", x_out_fbypass_rd_val__h6874); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage1: pc 0x%08h instr 0x%08h priv %0d", - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write("Output_Stage1", " BUSY pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write("Output_Stage1", " NONPIPE: pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write("Output_Stage1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) - $write("Output_Stage1", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(" PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd0) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd1) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd2) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd3) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd4) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd5) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd6) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd7) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd8) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd9) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1287 == 4'd10) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1353) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n", - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(" op_stage2:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == 3'd0) - $write("OP_Stage2_ALU"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == 3'd1) - $write("OP_Stage2_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == 3'd2) - $write("OP_Stage2_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == 3'd3) - $write("OP_Stage2_M"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1205 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1207) && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d1373 == 3'd4) - $write("OP_Stage2_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - NOT_near_mem_imem_exc__48_031_AND_IF_IF_NOT_ne_ETC___d1403) - $write("OP_Stage2_FD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(" rd:%0d\n", x_out_data_to_stage2_rd__h14647); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(" addr:%h val1:%h val2:%h val3:%h}", - x_out_data_to_stage2_addr__h14648, - x_out_data_to_stage2_val1__h14649, - x_out_data_to_stage2_val2__h14650, - x_out_data_to_stage2_val3__h14651); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1603) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1606) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1609) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1612) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1615) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1618) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1621) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1624) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1627) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1630) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1633) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647 && - near_mem_imem_exc__48_OR_IF_IF_NOT_near_mem_im_ETC___d1636) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write("'h%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write("'h%h", x_out_trap_info_exc_code__h18054); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1029) - $write("'h%h", value__h18109, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1210) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_08_OR_NOT_near_mem_ime_ETC___d632) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d647) - $write(" next_pc 0x%08h", x_out_next_pc__h14611); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - value__h6429, - stage2_rg_stage2[299:268], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3134 != 4'd0) - $display(" mcause:0x%0h epc 0x%0h tval:0x%0h new pc 0x%0h, new mstatus 0x%0h", - csr_regfile$csr_trap_actions[65:2], - value__h6429, - value__h6490, - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[129:66]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h14645[19:15], - rs1_val__h23289, - x_out_data_to_stage2_instr__h14645[31:20], - csr_regfile$read_csr[63:0], - x_out_data_to_stage2_instr__h14645[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h14645[19:15], - rs1_val__h23289, - x_out_data_to_stage2_instr__h14645[31:20], - x_out_data_to_stage2_instr__h14645[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_CSRR_S_or_C", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h14645[19:15], - rs1_val__h23782, - x_out_data_to_stage2_instr__h14645[31:20], - csr_regfile$read_csr[63:0], - x_out_data_to_stage2_instr__h14645[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h14645[19:15], - rs1_val__h23782, - x_out_data_to_stage2_instr__h14645[31:20], - x_out_data_to_stage2_instr__h14645[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h14611); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d pc:%0x cur_priv:%0d", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - x_out_next_pc__h14611, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3134 != 4'd0) - $display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d", - csr_regfile$csr_ret_actions[129:66], - csr_regfile$csr_ret_actions[63:0], - csr_regfile$csr_ret_actions[65:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_finish_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_finish_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU.rl_stage1_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h3134 != 4'd0) - $display(" WFI resume"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_from_WFI && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d2002) - $display("%0d: CPU.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x", - csr_regfile$read_csr_mcycle, - csr_regfile$csr_trap_actions[193:130], - x_out_data_to_stage2_instr__h14645); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d2002) - $display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'", - cpi__h28498, - cpifrac__h28499, - delta_CPI_cycles__h28494, - _theResult____h28496); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_06_07_OR_NOT_near_mem_im_ETC___d2002) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3134 != 4'd0) - $display("%0d: CPU.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", - csr_regfile$read_csr_mcycle, - rg_cur_priv, - csr_regfile$csr_trap_actions[65:2], - imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3134 != 4'd0) - $display(" tval:0x%0h new pc:0x%0h new mstatus:0x%0h", - value__h18109, - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[129:66]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_trap_fetch && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3134 != 4'd0) - $display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", - csr_regfile$read_csr_mcycle, - imem_rg_pc, - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[1:0], - csr_regfile$csr_trap_actions[129:66]); - if (WILL_FIRE_RL_imem_rl_assert_fail) - $display("ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False"); - if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", soc_map$m_pc_reset_value); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h", - csr_regfile$read_csr_mcycle, - soc_map$m_pc_reset_value); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage3_rg_stage3[69]) - $display(" S3.fa_deq: write FRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[75:71], - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[76] && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - !stage3_rg_stage3[69]) - $display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[75:71], - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write(" S3.enq: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[363:300], - stage2_rg_stage2[299:268], - stage2_rg_stage2[365:364]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[267:265] != 3'd0 && - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d153) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[267:265] == 3'd0 || - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d163)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[267:265] != 3'd0 && - stage2_rg_stage2[267:265] != 3'd1 && - stage2_rg_stage2[267:265] != 3'd4 && - stage2_rg_stage2[267:265] != 3'd2 && - stage2_rg_stage2[267:265] != 3'd3) - $write(" fflags: %05b", - "'h%h", - x_out_data_to_stage3_fpr_flags__h6249); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[267:265] == 3'd0 || - stage2_rg_stage2[267:265] == 3'd1 || - stage2_rg_stage2[267:265] == 3'd4 || - stage2_rg_stage2[267:265] == 3'd2 || - stage2_rg_stage2[267:265] == 3'd3)) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - stage2_rg_stage2[267:265] != 3'd0 && - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d198) - $write(" frd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6246, - x_out_data_to_stage3_rd_val__h6250); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45 && - (stage2_rg_stage2[267:265] == 3'd0 || - IF_stage2_rg_stage2_02_BITS_267_TO_265_03_EQ_1_ETC___d232)) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6246, - x_out_data_to_stage3_rd_val__h6250); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_01_THEN_IF_stage2_rg_stage2__ETC___d137 == 2'd2 && - cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[363:300], - stage2_rg_stage2[299:268], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1827 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage2.enq (Data_Stage1_to_Stage2)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1782 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1886 && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h14611); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h3134 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h14645, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__9_ULT_cf_ETC___d45) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $write("CPU: Bluespec RISC-V Piccolo v3.0"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) $display(" (RV64)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h3134 != 4'd0) - $display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle); - end - // synopsys translate_on -endmodule // mkCPU - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v deleted file mode 100644 index 5a849419..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v +++ /dev/null @@ -1,228 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 64 -// fav_write O 64 -// fv_sie_read O 64 -// fav_sie_write O 64 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 64 -// fav_sie_write_misa I 28 -// fav_sie_write_wordxl I 64 -// EN_reset I 1 -// EN_fav_write I 1 -// EN_fav_sie_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// (fav_sie_write_misa, fav_sie_write_wordxl) -> fav_sie_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIE(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - fv_sie_read, - - fav_sie_write_misa, - fav_sie_write_wordxl, - EN_fav_sie_write, - fav_sie_write); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [63 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [63 : 0] fav_write_wordxl; - input EN_fav_write; - output [63 : 0] fav_write; - - // value method fv_sie_read - output [63 : 0] fv_sie_read; - - // actionvalue method fav_sie_write - input [27 : 0] fav_sie_write_misa; - input [63 : 0] fav_sie_write_wordxl; - input EN_fav_sie_write; - output [63 : 0] fav_sie_write; - - // signals for module outputs - wire [63 : 0] fav_sie_write, fav_write, fv_read, fv_sie_read; - - // register rg_mie - reg [11 : 0] rg_mie; - reg [11 : 0] rg_mie$D_IN; - wire rg_mie$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_sie_write, - CAN_FIRE_fav_write, - CAN_FIRE_reset, - WILL_FIRE_fav_sie_write, - WILL_FIRE_fav_write, - WILL_FIRE_reset; - - // inputs to muxes for submodule ports - wire [11 : 0] MUX_rg_mie$write_1__VAL_3; - - // remaining internal signals - wire [11 : 0] mie__h92, x__h458, x__h883; - wire seie__h123, - seie__h544, - ssie__h117, - ssie__h538, - stie__h120, - stie__h541, - ueie__h122, - ueie__h543, - usie__h116, - usie__h537, - utie__h119, - utie__h540; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 52'd0, rg_mie } ; - - // actionvalue method fav_write - assign fav_write = { 52'd0, mie__h92 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // value method fv_sie_read - assign fv_sie_read = { 52'd0, x__h458 } ; - - // actionvalue method fav_sie_write - assign fav_sie_write = { 52'd0, x__h883 } ; - assign CAN_FIRE_fav_sie_write = 1'd1 ; - assign WILL_FIRE_fav_sie_write = EN_fav_sie_write ; - - // inputs to muxes for submodule ports - assign MUX_rg_mie$write_1__VAL_3 = - { rg_mie[11], - 1'b0, - seie__h544, - ueie__h543, - rg_mie[7], - 1'b0, - stie__h541, - utie__h540, - rg_mie[3], - 1'b0, - ssie__h538, - usie__h537 } ; - - // register rg_mie - always@(EN_fav_write or - mie__h92 or - EN_reset or EN_fav_sie_write or MUX_rg_mie$write_1__VAL_3) - case (1'b1) - EN_fav_write: rg_mie$D_IN = mie__h92; - EN_reset: rg_mie$D_IN = 12'd0; - EN_fav_sie_write: rg_mie$D_IN = MUX_rg_mie$write_1__VAL_3; - default: rg_mie$D_IN = 12'b101010101010 /* unspecified value */ ; - endcase - assign rg_mie$EN = EN_fav_write || EN_fav_sie_write || EN_reset ; - - // remaining internal signals - assign mie__h92 = - { fav_write_wordxl[11], - 1'b0, - seie__h123, - ueie__h122, - fav_write_wordxl[7], - 1'b0, - stie__h120, - utie__h119, - fav_write_wordxl[3], - 1'b0, - ssie__h117, - usie__h116 } ; - assign seie__h123 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign seie__h544 = fav_sie_write_misa[18] && fav_sie_write_wordxl[9] ; - assign ssie__h117 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign ssie__h538 = fav_sie_write_misa[18] && fav_sie_write_wordxl[1] ; - assign stie__h120 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign stie__h541 = fav_sie_write_misa[18] && fav_sie_write_wordxl[5] ; - assign ueie__h122 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign ueie__h543 = fav_sie_write_misa[13] && fav_sie_write_wordxl[8] ; - assign usie__h116 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign usie__h537 = fav_sie_write_misa[13] && fav_sie_write_wordxl[0] ; - assign utie__h119 = fav_write_misa[13] && fav_write_wordxl[4] ; - assign utie__h540 = fav_sie_write_misa[13] && fav_sie_write_wordxl[4] ; - assign x__h458 = - { 2'd0, rg_mie[9:8], 2'd0, rg_mie[5:4], 2'd0, rg_mie[1:0] } ; - assign x__h883 = - { 2'd0, - seie__h544, - ueie__h543, - 2'd0, - stie__h541, - utie__h540, - 2'd0, - ssie__h538, - usie__h537 } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_mie = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIE - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v deleted file mode 100644 index 6ba79983..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v +++ /dev/null @@ -1,374 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 64 -// fav_write O 64 -// fv_sip_read O 64 -// fav_sip_write O 64 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 64 -// fav_sip_write_misa I 28 -// fav_sip_write_wordxl I 64 -// m_external_interrupt_req_req I 1 reg -// s_external_interrupt_req_req I 1 reg -// software_interrupt_req_req I 1 reg -// timer_interrupt_req_req I 1 reg -// EN_reset I 1 -// EN_fav_write I 1 -// EN_fav_sip_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// (fav_sip_write_misa, fav_sip_write_wordxl) -> fav_sip_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIP(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - fv_sip_read, - - fav_sip_write_misa, - fav_sip_write_wordxl, - EN_fav_sip_write, - fav_sip_write, - - m_external_interrupt_req_req, - - s_external_interrupt_req_req, - - software_interrupt_req_req, - - timer_interrupt_req_req); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [63 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [63 : 0] fav_write_wordxl; - input EN_fav_write; - output [63 : 0] fav_write; - - // value method fv_sip_read - output [63 : 0] fv_sip_read; - - // actionvalue method fav_sip_write - input [27 : 0] fav_sip_write_misa; - input [63 : 0] fav_sip_write_wordxl; - input EN_fav_sip_write; - output [63 : 0] fav_sip_write; - - // action method m_external_interrupt_req - input m_external_interrupt_req_req; - - // action method s_external_interrupt_req - input s_external_interrupt_req_req; - - // action method software_interrupt_req - input software_interrupt_req_req; - - // action method timer_interrupt_req - input timer_interrupt_req_req; - - // signals for module outputs - wire [63 : 0] fav_sip_write, fav_write, fv_read, fv_sip_read; - - // register rg_meip - reg rg_meip; - wire rg_meip$D_IN, rg_meip$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_seip - reg rg_seip; - wire rg_seip$D_IN, rg_seip$EN; - - // register rg_ssip - reg rg_ssip; - reg rg_ssip$D_IN; - wire rg_ssip$EN; - - // register rg_stip - reg rg_stip; - wire rg_stip$D_IN, rg_stip$EN; - - // register rg_ueip - reg rg_ueip; - reg rg_ueip$D_IN; - wire rg_ueip$EN; - - // register rg_usip - reg rg_usip; - reg rg_usip$D_IN; - wire rg_usip$EN; - - // register rg_utip - reg rg_utip; - wire rg_utip$D_IN, rg_utip$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_sip_write, - CAN_FIRE_fav_write, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_reset, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_fav_sip_write, - WILL_FIRE_fav_write, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_reset, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // remaining internal signals - wire [11 : 0] new_mip__h528, new_mip__h946; - wire seip__h562, - ssip__h566, - ssip__h986, - stip__h564, - ueip__h563, - ueip__h985, - usip__h567, - usip__h987, - utip__h565; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 52'd0, new_mip__h528 } ; - - // actionvalue method fav_write - assign fav_write = { 52'd0, new_mip__h946 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // value method fv_sip_read - assign fv_sip_read = - { 54'd0, - rg_seip, - rg_ueip, - 2'b0, - rg_stip, - rg_utip, - 2'b0, - rg_ssip, - rg_usip } ; - - // actionvalue method fav_sip_write - assign fav_sip_write = - { 54'd0, - rg_seip, - ueip__h985, - 2'b0, - rg_stip, - rg_utip, - 2'b0, - ssip__h986, - usip__h987 } ; - assign CAN_FIRE_fav_sip_write = 1'd1 ; - assign WILL_FIRE_fav_sip_write = EN_fav_sip_write ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // register rg_meip - assign rg_meip$D_IN = m_external_interrupt_req_req ; - assign rg_meip$EN = 1'b1 ; - - // register rg_msip - assign rg_msip$D_IN = software_interrupt_req_req ; - assign rg_msip$EN = 1'b1 ; - - // register rg_mtip - assign rg_mtip$D_IN = timer_interrupt_req_req ; - assign rg_mtip$EN = 1'b1 ; - - // register rg_seip - assign rg_seip$D_IN = s_external_interrupt_req_req ; - assign rg_seip$EN = 1'b1 ; - - // register rg_ssip - always@(EN_reset or - EN_fav_write or ssip__h566 or EN_fav_sip_write or ssip__h986) - case (1'b1) - EN_reset: rg_ssip$D_IN = 1'd0; - EN_fav_write: rg_ssip$D_IN = ssip__h566; - EN_fav_sip_write: rg_ssip$D_IN = ssip__h986; - default: rg_ssip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_ssip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_stip - assign rg_stip$D_IN = !EN_reset && stip__h564 ; - assign rg_stip$EN = EN_fav_write || EN_reset ; - - // register rg_ueip - always@(EN_reset or - EN_fav_write or ueip__h563 or EN_fav_sip_write or ueip__h985) - case (1'b1) - EN_reset: rg_ueip$D_IN = 1'd0; - EN_fav_write: rg_ueip$D_IN = ueip__h563; - EN_fav_sip_write: rg_ueip$D_IN = ueip__h985; - default: rg_ueip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_ueip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_usip - always@(EN_reset or - EN_fav_write or usip__h567 or EN_fav_sip_write or usip__h987) - case (1'b1) - EN_reset: rg_usip$D_IN = 1'd0; - EN_fav_write: rg_usip$D_IN = usip__h567; - EN_fav_sip_write: rg_usip$D_IN = usip__h987; - default: rg_usip$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign rg_usip$EN = EN_fav_write || EN_fav_sip_write || EN_reset ; - - // register rg_utip - assign rg_utip$D_IN = !EN_reset && utip__h565 ; - assign rg_utip$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign new_mip__h528 = - { rg_meip, - 1'b0, - rg_seip, - rg_ueip, - rg_mtip, - 1'b0, - rg_stip, - rg_utip, - rg_msip, - 1'b0, - rg_ssip, - rg_usip } ; - assign new_mip__h946 = - { rg_meip, - 1'b0, - seip__h562, - ueip__h563, - rg_mtip, - 1'b0, - stip__h564, - utip__h565, - rg_msip, - 1'b0, - ssip__h566, - usip__h567 } ; - assign seip__h562 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssip__h566 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign ssip__h986 = fav_sip_write_misa[18] && fav_sip_write_wordxl[1] ; - assign stip__h564 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueip__h563 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign ueip__h985 = fav_sip_write_misa[13] && fav_sip_write_wordxl[8] ; - assign usip__h567 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign usip__h987 = fav_sip_write_misa[13] && fav_sip_write_wordxl[0] ; - assign utip__h565 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN; - if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN; - if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN; - if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN; - if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN; - if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_meip = 1'h0; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_seip = 1'h0; - rg_ssip = 1'h0; - rg_stip = 1'h0; - rg_ueip = 1'h0; - rg_usip = 1'h0; - rg_utip = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIP - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v deleted file mode 100644 index d8ea7c79..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v +++ /dev/null @@ -1,3658 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_csr O 65 -// read_csr_port2 O 65 -// mav_read_csr O 65 -// mav_csr_write O 64 -// read_frm O 3 reg -// read_misa O 28 const -// read_mstatus O 64 reg -// read_sstatus O 64 -// read_ustatus O 64 -// read_satp O 64 reg -// csr_trap_actions O 194 -// RDY_csr_trap_actions O 1 const -// csr_ret_actions O 130 -// RDY_csr_ret_actions O 1 const -// read_csr_minstret O 64 reg -// read_csr_mcycle O 64 reg -// read_csr_mtime O 64 reg -// access_permitted_1 O 1 -// access_permitted_2 O 1 -// csr_counter_read_fault O 1 -// csr_mip_read O 64 -// interrupt_pending O 5 -// wfi_resume O 1 -// nmi_pending O 1 reg -// RDY_debug O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// read_csr_csr_addr I 12 -// read_csr_port2_csr_addr I 12 -// mav_read_csr_csr_addr I 12 -// mav_csr_write_csr_addr I 12 -// mav_csr_write_word I 64 -// ma_update_fcsr_fflags_flags I 5 -// ma_update_mstatus_fs_fs I 2 -// csr_trap_actions_from_priv I 2 -// csr_trap_actions_pc I 64 -// csr_trap_actions_nmi I 1 -// csr_trap_actions_interrupt I 1 -// csr_trap_actions_exc_code I 4 -// csr_trap_actions_xtval I 64 -// csr_ret_actions_from_priv I 2 -// access_permitted_1_priv I 2 -// access_permitted_1_csr_addr I 12 -// access_permitted_1_read_not_write I 1 -// access_permitted_2_priv I 2 -// access_permitted_2_csr_addr I 12 -// access_permitted_2_read_not_write I 1 -// csr_counter_read_fault_priv I 2 -// csr_counter_read_fault_csr_addr I 12 -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// interrupt_pending_cur_priv I 2 -// nmi_req_set_not_clear I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_ma_update_fcsr_fflags I 1 -// EN_ma_update_mstatus_fs I 1 -// EN_csr_minstret_incr I 1 -// EN_debug I 1 unused -// EN_mav_read_csr I 1 unused -// EN_mav_csr_write I 1 -// EN_csr_trap_actions I 1 -// EN_csr_ret_actions I 1 -// -// Combinational paths from inputs to outputs: -// read_csr_csr_addr -> read_csr -// read_csr_port2_csr_addr -> read_csr_port2 -// (access_permitted_1_priv, -// access_permitted_1_csr_addr, -// access_permitted_1_read_not_write) -> access_permitted_1 -// (access_permitted_2_priv, -// access_permitted_2_csr_addr, -// access_permitted_2_read_not_write) -> access_permitted_2 -// (csr_counter_read_fault_priv, -// csr_counter_read_fault_csr_addr) -> csr_counter_read_fault -// interrupt_pending_cur_priv -> interrupt_pending -// mav_read_csr_csr_addr -> mav_read_csr -// (mav_csr_write_csr_addr, -// mav_csr_write_word, -// EN_mav_csr_write) -> mav_csr_write -// (csr_trap_actions_from_priv, -// csr_trap_actions_nmi, -// csr_trap_actions_interrupt, -// csr_trap_actions_exc_code) -> csr_trap_actions -// csr_ret_actions_from_priv -> csr_ret_actions -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_csr_csr_addr, - read_csr, - - read_csr_port2_csr_addr, - read_csr_port2, - - mav_read_csr_csr_addr, - EN_mav_read_csr, - mav_read_csr, - - mav_csr_write_csr_addr, - mav_csr_write_word, - EN_mav_csr_write, - mav_csr_write, - - read_frm, - - ma_update_fcsr_fflags_flags, - EN_ma_update_fcsr_fflags, - - ma_update_mstatus_fs_fs, - EN_ma_update_mstatus_fs, - - read_misa, - - read_mstatus, - - read_sstatus, - - read_ustatus, - - read_satp, - - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_nmi, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval, - EN_csr_trap_actions, - csr_trap_actions, - RDY_csr_trap_actions, - - csr_ret_actions_from_priv, - EN_csr_ret_actions, - csr_ret_actions, - RDY_csr_ret_actions, - - read_csr_minstret, - - EN_csr_minstret_incr, - - read_csr_mcycle, - - read_csr_mtime, - - access_permitted_1_priv, - access_permitted_1_csr_addr, - access_permitted_1_read_not_write, - access_permitted_1, - - access_permitted_2_priv, - access_permitted_2_csr_addr, - access_permitted_2_read_not_write, - access_permitted_2, - - csr_counter_read_fault_priv, - csr_counter_read_fault_csr_addr, - csr_counter_read_fault, - - csr_mip_read, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - interrupt_pending_cur_priv, - interrupt_pending, - - wfi_resume, - - nmi_req_set_not_clear, - - nmi_pending, - - EN_debug, - RDY_debug); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_csr - input [11 : 0] read_csr_csr_addr; - output [64 : 0] read_csr; - - // value method read_csr_port2 - input [11 : 0] read_csr_port2_csr_addr; - output [64 : 0] read_csr_port2; - - // actionvalue method mav_read_csr - input [11 : 0] mav_read_csr_csr_addr; - input EN_mav_read_csr; - output [64 : 0] mav_read_csr; - - // actionvalue method mav_csr_write - input [11 : 0] mav_csr_write_csr_addr; - input [63 : 0] mav_csr_write_word; - input EN_mav_csr_write; - output [63 : 0] mav_csr_write; - - // value method read_frm - output [2 : 0] read_frm; - - // action method ma_update_fcsr_fflags - input [4 : 0] ma_update_fcsr_fflags_flags; - input EN_ma_update_fcsr_fflags; - - // action method ma_update_mstatus_fs - input [1 : 0] ma_update_mstatus_fs_fs; - input EN_ma_update_mstatus_fs; - - // value method read_misa - output [27 : 0] read_misa; - - // value method read_mstatus - output [63 : 0] read_mstatus; - - // value method read_sstatus - output [63 : 0] read_sstatus; - - // value method read_ustatus - output [63 : 0] read_ustatus; - - // value method read_satp - output [63 : 0] read_satp; - - // actionvalue method csr_trap_actions - input [1 : 0] csr_trap_actions_from_priv; - input [63 : 0] csr_trap_actions_pc; - input csr_trap_actions_nmi; - input csr_trap_actions_interrupt; - input [3 : 0] csr_trap_actions_exc_code; - input [63 : 0] csr_trap_actions_xtval; - input EN_csr_trap_actions; - output [193 : 0] csr_trap_actions; - output RDY_csr_trap_actions; - - // actionvalue method csr_ret_actions - input [1 : 0] csr_ret_actions_from_priv; - input EN_csr_ret_actions; - output [129 : 0] csr_ret_actions; - output RDY_csr_ret_actions; - - // value method read_csr_minstret - output [63 : 0] read_csr_minstret; - - // action method csr_minstret_incr - input EN_csr_minstret_incr; - - // value method read_csr_mcycle - output [63 : 0] read_csr_mcycle; - - // value method read_csr_mtime - output [63 : 0] read_csr_mtime; - - // value method access_permitted_1 - input [1 : 0] access_permitted_1_priv; - input [11 : 0] access_permitted_1_csr_addr; - input access_permitted_1_read_not_write; - output access_permitted_1; - - // value method access_permitted_2 - input [1 : 0] access_permitted_2_priv; - input [11 : 0] access_permitted_2_csr_addr; - input access_permitted_2_read_not_write; - output access_permitted_2; - - // value method csr_counter_read_fault - input [1 : 0] csr_counter_read_fault_priv; - input [11 : 0] csr_counter_read_fault_csr_addr; - output csr_counter_read_fault; - - // value method csr_mip_read - output [63 : 0] csr_mip_read; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // value method interrupt_pending - input [1 : 0] interrupt_pending_cur_priv; - output [4 : 0] interrupt_pending; - - // value method wfi_resume - output wfi_resume; - - // action method nmi_req - input nmi_req_set_not_clear; - - // value method nmi_pending - output nmi_pending; - - // action method debug - input EN_debug; - output RDY_debug; - - // signals for module outputs - wire [193 : 0] csr_trap_actions; - wire [129 : 0] csr_ret_actions; - wire [64 : 0] mav_read_csr, read_csr, read_csr_port2; - wire [63 : 0] csr_mip_read, - mav_csr_write, - read_csr_mcycle, - read_csr_minstret, - read_csr_mtime, - read_mstatus, - read_satp, - read_sstatus, - read_ustatus; - wire [27 : 0] read_misa; - wire [4 : 0] interrupt_pending; - wire [2 : 0] read_frm; - wire RDY_csr_ret_actions, - RDY_csr_trap_actions, - RDY_debug, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - access_permitted_1, - access_permitted_2, - csr_counter_read_fault, - nmi_pending, - wfi_resume; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register csr_mstatus_rg_mstatus - reg [63 : 0] csr_mstatus_rg_mstatus; - reg [63 : 0] csr_mstatus_rg_mstatus$D_IN; - wire csr_mstatus_rg_mstatus$EN; - - // register rg_dcsr - reg [31 : 0] rg_dcsr; - wire [31 : 0] rg_dcsr$D_IN; - wire rg_dcsr$EN; - - // register rg_dpc - reg [63 : 0] rg_dpc; - wire [63 : 0] rg_dpc$D_IN; - wire rg_dpc$EN; - - // register rg_dscratch0 - reg [63 : 0] rg_dscratch0; - wire [63 : 0] rg_dscratch0$D_IN; - wire rg_dscratch0$EN; - - // register rg_dscratch1 - reg [63 : 0] rg_dscratch1; - wire [63 : 0] rg_dscratch1$D_IN; - wire rg_dscratch1$EN; - - // register rg_fflags - reg [4 : 0] rg_fflags; - reg [4 : 0] rg_fflags$D_IN; - wire rg_fflags$EN; - - // register rg_frm - reg [2 : 0] rg_frm; - wire [2 : 0] rg_frm$D_IN; - wire rg_frm$EN; - - // register rg_mcause - reg [4 : 0] rg_mcause; - reg [4 : 0] rg_mcause$D_IN; - wire rg_mcause$EN; - - // register rg_mcounteren - reg [2 : 0] rg_mcounteren; - wire [2 : 0] rg_mcounteren$D_IN; - wire rg_mcounteren$EN; - - // register rg_mcycle - reg [63 : 0] rg_mcycle; - wire [63 : 0] rg_mcycle$D_IN; - wire rg_mcycle$EN; - - // register rg_medeleg - reg [15 : 0] rg_medeleg; - wire [15 : 0] rg_medeleg$D_IN; - wire rg_medeleg$EN; - - // register rg_mepc - reg [63 : 0] rg_mepc; - wire [63 : 0] rg_mepc$D_IN; - wire rg_mepc$EN; - - // register rg_mideleg - reg [11 : 0] rg_mideleg; - wire [11 : 0] rg_mideleg$D_IN; - wire rg_mideleg$EN; - - // register rg_minstret - reg [63 : 0] rg_minstret; - wire [63 : 0] rg_minstret$D_IN; - wire rg_minstret$EN; - - // register rg_mscratch - reg [63 : 0] rg_mscratch; - wire [63 : 0] rg_mscratch$D_IN; - wire rg_mscratch$EN; - - // register rg_mtval - reg [63 : 0] rg_mtval; - wire [63 : 0] rg_mtval$D_IN; - wire rg_mtval$EN; - - // register rg_mtvec - reg [62 : 0] rg_mtvec; - wire [62 : 0] rg_mtvec$D_IN; - wire rg_mtvec$EN; - - // register rg_nmi - reg rg_nmi; - wire rg_nmi$D_IN, rg_nmi$EN; - - // register rg_nmi_vector - reg [63 : 0] rg_nmi_vector; - wire [63 : 0] rg_nmi_vector$D_IN; - wire rg_nmi_vector$EN; - - // register rg_satp - reg [63 : 0] rg_satp; - wire [63 : 0] rg_satp$D_IN; - wire rg_satp$EN; - - // register rg_scause - reg [4 : 0] rg_scause; - reg [4 : 0] rg_scause$D_IN; - wire rg_scause$EN; - - // register rg_sepc - reg [63 : 0] rg_sepc; - wire [63 : 0] rg_sepc$D_IN; - wire rg_sepc$EN; - - // register rg_sscratch - reg [63 : 0] rg_sscratch; - wire [63 : 0] rg_sscratch$D_IN; - wire rg_sscratch$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_stval - reg [63 : 0] rg_stval; - wire [63 : 0] rg_stval$D_IN; - wire rg_stval$EN; - - // register rg_stvec - reg [62 : 0] rg_stvec; - wire [62 : 0] rg_stvec$D_IN; - wire rg_stvec$EN; - - // register rg_tdata1 - reg [63 : 0] rg_tdata1; - wire [63 : 0] rg_tdata1$D_IN; - wire rg_tdata1$EN; - - // register rg_tdata2 - reg [63 : 0] rg_tdata2; - wire [63 : 0] rg_tdata2$D_IN; - wire rg_tdata2$EN; - - // register rg_tdata3 - reg [63 : 0] rg_tdata3; - wire [63 : 0] rg_tdata3$D_IN; - wire rg_tdata3$EN; - - // register rg_tselect - reg [63 : 0] rg_tselect; - wire [63 : 0] rg_tselect$D_IN; - wire rg_tselect$EN; - - // ports of submodule csr_mie - wire [63 : 0] csr_mie$fav_sie_write, - csr_mie$fav_sie_write_wordxl, - csr_mie$fav_write, - csr_mie$fav_write_wordxl, - csr_mie$fv_read, - csr_mie$fv_sie_read; - wire [27 : 0] csr_mie$fav_sie_write_misa, csr_mie$fav_write_misa; - wire csr_mie$EN_fav_sie_write, csr_mie$EN_fav_write, csr_mie$EN_reset; - - // ports of submodule csr_mip - wire [63 : 0] csr_mip$fav_sip_write, - csr_mip$fav_sip_write_wordxl, - csr_mip$fav_write, - csr_mip$fav_write_wordxl, - csr_mip$fv_read, - csr_mip$fv_sip_read; - wire [27 : 0] csr_mip$fav_sip_write_misa, csr_mip$fav_write_misa; - wire csr_mip$EN_fav_sip_write, - csr_mip$EN_fav_write, - csr_mip$EN_reset, - csr_mip$m_external_interrupt_req_req, - csr_mip$s_external_interrupt_req_req, - csr_mip$software_interrupt_req_req, - csr_mip$timer_interrupt_req_req; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mtvec_reset_value, - soc_map$m_nmivec_reset_value; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_mcycle_incr, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_upd_minstret_csrrx, - CAN_FIRE_RL_rl_upd_minstret_incr, - CAN_FIRE_csr_minstret_incr, - CAN_FIRE_csr_ret_actions, - CAN_FIRE_csr_trap_actions, - CAN_FIRE_debug, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_ma_update_fcsr_fflags, - CAN_FIRE_ma_update_mstatus_fs, - CAN_FIRE_mav_csr_write, - CAN_FIRE_mav_read_csr, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_rl_mcycle_incr, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_upd_minstret_csrrx, - WILL_FIRE_RL_rl_upd_minstret_incr, - WILL_FIRE_csr_minstret_incr, - WILL_FIRE_csr_ret_actions, - WILL_FIRE_csr_trap_actions, - WILL_FIRE_debug, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_ma_update_fcsr_fflags, - WILL_FIRE_ma_update_mstatus_fs, - WILL_FIRE_mav_csr_write, - WILL_FIRE_mav_read_csr, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_2, - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4, - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5, - MUX_rg_minstret$write_1__VAL_1, - MUX_rg_minstret$write_1__VAL_2; - wire [62 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; - wire [15 : 0] MUX_rg_medeleg$write_1__VAL_1; - wire [4 : 0] MUX_rg_fflags$write_1__VAL_3, - MUX_rg_mcause$write_1__VAL_2, - MUX_rg_mcause$write_1__VAL_3; - wire [2 : 0] MUX_rg_frm$write_1__VAL_1; - wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_5, - MUX_rg_fflags$write_1__SEL_2, - MUX_rg_frm$write_1__SEL_1, - MUX_rg_mcause$write_1__SEL_2, - MUX_rg_mcause$write_1__SEL_3, - MUX_rg_mcounteren$write_1__SEL_1, - MUX_rg_medeleg$write_1__SEL_1, - MUX_rg_mideleg$write_1__SEL_1, - MUX_rg_mtvec$write_1__SEL_1, - MUX_rg_satp$write_1__SEL_1, - MUX_rg_scause$write_1__SEL_2, - MUX_rg_scause$write_1__SEL_3, - MUX_rg_sepc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2, - MUX_rg_stval$write_1__SEL_1, - MUX_rg_stvec$write_1__SEL_1, - MUX_rg_tdata1$write_1__SEL_1, - MUX_rw_minstret$wset_1__SEL_1; - - // remaining internal signals - reg [63 : 0] IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731, - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291, - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511, - y_avValue_fst__h9500; - reg [61 : 0] CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1; - reg CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2, - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742, - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845; - wire [63 : 0] IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275, - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477, - _theResult___fst__h13593, - _theResult___fst__h13794, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267, - exc_pc___1__h12586, - exc_pc__h12512, - mask__h11532, - mask__h11549, - mask__h13614, - mask__h13631, - result__h9129, - v__h11328, - v__h5882, - v__h6026, - v__h6140, - v__h7518, - v__h7554, - v__h8224, - v__h8286, - v__h8442, - val__h11533, - val__h11550, - val__h13632, - vector_offset__h12513, - wordxl1__h7649, - x__h10300, - x__h11531, - x__h11544, - x__h11561, - x__h13437, - x__h13438, - x__h13613, - x__h13626, - x__h13643, - y__h11545, - y__h11562, - y__h13627, - y__h13644, - y_avValue_fst__h12469, - y_avValue_fst__h12486, - y_avValue_snd_snd__h12559; - wire [22 : 0] fixed_up_val_23__h11372, - fixed_up_val_23__h13500, - fixed_up_val_23__h6191, - fixed_up_val_23__h7690, - fixed_up_val_23__h9712; - wire [5 : 0] ie_from_x__h13577, - ie_to_x__h11449, - pie_from_x__h13578, - pie_to_x__h11450; - wire [3 : 0] IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923, - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925, - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926, - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928, - exc_code__h13279; - wire [1 : 0] IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, - _theResult____h15189, - _theResult____h15401, - _theResult____h15613, - _theResult____h15825, - _theResult____h16037, - _theResult____h16249, - _theResult____h16461, - _theResult____h16673, - _theResult____h16885, - _theResult___fst__h11461, - new_priv__h11323, - to_y__h13793; - wire NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598, - NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701, - NOT_cfg_verbosity_read__42_ULE_1_43___d944, - NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910, - NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848, - NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875, - NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902, - NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883, - NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856, - NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892, - NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865, - NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901, - NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874, - NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402, - b__h11548, - b__h13630, - csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821, - csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745, - csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811, - csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788, - csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755, - csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832, - csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799, - csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766, - csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810, - csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777, - csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301, - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453, - deleg_bit___1__h11470, - deleg_bit___1__h11485, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807, - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806, - interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817, - mav_csr_write_csr_addr_ULE_0x33F___d739, - mav_csr_write_csr_addr_ULE_0xB1F___d735, - mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940, - mav_csr_write_csr_addr_ULT_0x323___d738, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859, - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861, - mav_csr_write_csr_addr_ULT_0xB03___d734, - sd__h11371, - sd__h13499, - sd__h7689, - sd__h9711; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_csr - assign read_csr = - { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || - read_csr_csr_addr == 12'h001 || - read_csr_csr_addr == 12'h002 || - read_csr_csr_addr == 12'h003 || - read_csr_csr_addr == 12'hC00 || - read_csr_csr_addr == 12'hC02 || - read_csr_csr_addr == 12'h100 || - read_csr_csr_addr == 12'h102 || - read_csr_csr_addr == 12'h103 || - read_csr_csr_addr == 12'h104 || - read_csr_csr_addr == 12'h105 || - read_csr_csr_addr == 12'h106 || - read_csr_csr_addr == 12'h140 || - read_csr_csr_addr == 12'h141 || - read_csr_csr_addr == 12'h142 || - read_csr_csr_addr == 12'h143 || - read_csr_csr_addr == 12'h144 || - read_csr_csr_addr == 12'h180 || - read_csr_csr_addr == 12'h302 || - read_csr_csr_addr == 12'h303 || - read_csr_csr_addr == 12'hF11 || - read_csr_csr_addr == 12'hF12 || - read_csr_csr_addr == 12'hF13 || - read_csr_csr_addr == 12'hF14 || - read_csr_csr_addr == 12'h300 || - read_csr_csr_addr == 12'h301 || - read_csr_csr_addr == 12'h304 || - read_csr_csr_addr == 12'h305 || - read_csr_csr_addr == 12'h306 || - read_csr_csr_addr == 12'h340 || - read_csr_csr_addr == 12'h341 || - read_csr_csr_addr == 12'h342 || - read_csr_csr_addr == 12'h343 || - read_csr_csr_addr == 12'h344 || - read_csr_csr_addr == 12'hB00 || - read_csr_csr_addr == 12'hB02 || - read_csr_csr_addr == 12'h7A0 || - read_csr_csr_addr == 12'h7A1 || - read_csr_csr_addr == 12'h7A2 || - read_csr_csr_addr == 12'h7A3, - (read_csr_csr_addr >= 12'hC03 && - read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hB03 && - read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'h323 && - read_csr_csr_addr <= 12'h33F) ? - 64'd0 : - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 } ; - - // value method read_csr_port2 - assign read_csr_port2 = - { read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F || - read_csr_port2_csr_addr == 12'h001 || - read_csr_port2_csr_addr == 12'h002 || - read_csr_port2_csr_addr == 12'h003 || - read_csr_port2_csr_addr == 12'hC00 || - read_csr_port2_csr_addr == 12'hC02 || - read_csr_port2_csr_addr == 12'h100 || - read_csr_port2_csr_addr == 12'h102 || - read_csr_port2_csr_addr == 12'h103 || - read_csr_port2_csr_addr == 12'h104 || - read_csr_port2_csr_addr == 12'h105 || - read_csr_port2_csr_addr == 12'h106 || - read_csr_port2_csr_addr == 12'h140 || - read_csr_port2_csr_addr == 12'h141 || - read_csr_port2_csr_addr == 12'h142 || - read_csr_port2_csr_addr == 12'h143 || - read_csr_port2_csr_addr == 12'h144 || - read_csr_port2_csr_addr == 12'h180 || - read_csr_port2_csr_addr == 12'h302 || - read_csr_port2_csr_addr == 12'h303 || - read_csr_port2_csr_addr == 12'hF11 || - read_csr_port2_csr_addr == 12'hF12 || - read_csr_port2_csr_addr == 12'hF13 || - read_csr_port2_csr_addr == 12'hF14 || - read_csr_port2_csr_addr == 12'h300 || - read_csr_port2_csr_addr == 12'h301 || - read_csr_port2_csr_addr == 12'h304 || - read_csr_port2_csr_addr == 12'h305 || - read_csr_port2_csr_addr == 12'h306 || - read_csr_port2_csr_addr == 12'h340 || - read_csr_port2_csr_addr == 12'h341 || - read_csr_port2_csr_addr == 12'h342 || - read_csr_port2_csr_addr == 12'h343 || - read_csr_port2_csr_addr == 12'h344 || - read_csr_port2_csr_addr == 12'hB00 || - read_csr_port2_csr_addr == 12'hB02 || - read_csr_port2_csr_addr == 12'h7A0 || - read_csr_port2_csr_addr == 12'h7A1 || - read_csr_port2_csr_addr == 12'h7A2 || - read_csr_port2_csr_addr == 12'h7A3, - (read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F) ? - 64'd0 : - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 } ; - - // actionvalue method mav_read_csr - assign mav_read_csr = - { mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F || - mav_read_csr_csr_addr == 12'h001 || - mav_read_csr_csr_addr == 12'h002 || - mav_read_csr_csr_addr == 12'h003 || - mav_read_csr_csr_addr == 12'hC00 || - mav_read_csr_csr_addr == 12'hC02 || - mav_read_csr_csr_addr == 12'h100 || - mav_read_csr_csr_addr == 12'h102 || - mav_read_csr_csr_addr == 12'h103 || - mav_read_csr_csr_addr == 12'h104 || - mav_read_csr_csr_addr == 12'h105 || - mav_read_csr_csr_addr == 12'h106 || - mav_read_csr_csr_addr == 12'h140 || - mav_read_csr_csr_addr == 12'h141 || - mav_read_csr_csr_addr == 12'h142 || - mav_read_csr_csr_addr == 12'h143 || - mav_read_csr_csr_addr == 12'h144 || - mav_read_csr_csr_addr == 12'h180 || - mav_read_csr_csr_addr == 12'h302 || - mav_read_csr_csr_addr == 12'h303 || - mav_read_csr_csr_addr == 12'hF11 || - mav_read_csr_csr_addr == 12'hF12 || - mav_read_csr_csr_addr == 12'hF13 || - mav_read_csr_csr_addr == 12'hF14 || - mav_read_csr_csr_addr == 12'h300 || - mav_read_csr_csr_addr == 12'h301 || - mav_read_csr_csr_addr == 12'h304 || - mav_read_csr_csr_addr == 12'h305 || - mav_read_csr_csr_addr == 12'h306 || - mav_read_csr_csr_addr == 12'h340 || - mav_read_csr_csr_addr == 12'h341 || - mav_read_csr_csr_addr == 12'h342 || - mav_read_csr_csr_addr == 12'h343 || - mav_read_csr_csr_addr == 12'h344 || - mav_read_csr_csr_addr == 12'hB00 || - mav_read_csr_csr_addr == 12'hB02 || - mav_read_csr_csr_addr == 12'h7A0 || - mav_read_csr_csr_addr == 12'h7A1 || - mav_read_csr_csr_addr == 12'h7A2 || - mav_read_csr_csr_addr == 12'h7A3, - (mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F) ? - 64'd0 : - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 } ; - assign CAN_FIRE_mav_read_csr = 1'd1 ; - assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; - - // actionvalue method mav_csr_write - assign mav_csr_write = - (!mav_csr_write_csr_addr_ULT_0xB03___d734 && - mav_csr_write_csr_addr_ULE_0xB1F___d735 || - !mav_csr_write_csr_addr_ULT_0x323___d738 && - mav_csr_write_csr_addr_ULE_0x33F___d739) ? - 64'd0 : - y_avValue_fst__h9500 ; - assign CAN_FIRE_mav_csr_write = 1'd1 ; - assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; - - // value method read_frm - assign read_frm = rg_frm ; - - // action method ma_update_fcsr_fflags - assign CAN_FIRE_ma_update_fcsr_fflags = 1'd1 ; - assign WILL_FIRE_ma_update_fcsr_fflags = EN_ma_update_fcsr_fflags ; - - // action method ma_update_mstatus_fs - assign CAN_FIRE_ma_update_mstatus_fs = 1'd1 ; - assign WILL_FIRE_ma_update_mstatus_fs = EN_ma_update_mstatus_fs ; - - // value method read_misa - assign read_misa = 28'd135532845 ; - - // value method read_mstatus - assign read_mstatus = csr_mstatus_rg_mstatus ; - - // value method read_sstatus - assign read_sstatus = - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] } ; - - // value method read_ustatus - assign read_ustatus = - { 59'd0, - csr_mstatus_rg_mstatus[4], - 3'd0, - csr_mstatus_rg_mstatus[0] } ; - - // value method read_satp - assign read_satp = rg_satp ; - - // actionvalue method csr_trap_actions - assign csr_trap_actions = - { x__h10300, x__h13437, x__h13438, new_priv__h11323 } ; - assign RDY_csr_trap_actions = 1'd1 ; - assign CAN_FIRE_csr_trap_actions = 1'd1 ; - assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; - - // actionvalue method csr_ret_actions - assign csr_ret_actions = - (csr_ret_actions_from_priv == 2'b11) ? - { rg_mepc, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[12:11], - _theResult___fst__h13593 } : - { rg_sepc, to_y__h13793, _theResult___fst__h13794 } ; - assign RDY_csr_ret_actions = 1'd1 ; - assign CAN_FIRE_csr_ret_actions = 1'd1 ; - assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; - - // value method read_csr_minstret - assign read_csr_minstret = rg_minstret ; - - // action method csr_minstret_incr - assign CAN_FIRE_csr_minstret_incr = 1'd1 ; - assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; - - // value method read_csr_mcycle - assign read_csr_mcycle = rg_mcycle ; - - // value method read_csr_mtime - assign read_csr_mtime = rg_mcycle ; - - // value method access_permitted_1 - assign access_permitted_1 = - NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598 && - (access_permitted_1_read_not_write || - access_permitted_1_csr_addr[11:10] != 2'b11) ; - - // value method access_permitted_2 - assign access_permitted_2 = - NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701 && - (access_permitted_2_read_not_write || - access_permitted_2_csr_addr[11:10] != 2'b11) ; - - // value method csr_counter_read_fault - assign csr_counter_read_fault = - (csr_counter_read_fault_priv == 2'b01 || - csr_counter_read_fault_priv == 2'b0) && - (csr_counter_read_fault_csr_addr == 12'hC00 && - !rg_mcounteren[0] || - csr_counter_read_fault_csr_addr == 12'hC01 && - !rg_mcounteren[1] || - csr_counter_read_fault_csr_addr == 12'hC02 && - !rg_mcounteren[2] || - csr_counter_read_fault_csr_addr >= 12'hC03 && - csr_counter_read_fault_csr_addr <= 12'hC1F) ; - - // value method csr_mip_read - assign csr_mip_read = csr_mip$fv_read ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // value method interrupt_pending - assign interrupt_pending = - { csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811 || - csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821 || - csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832, - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928 } ; - - // value method wfi_resume - assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 64'd0 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // value method nmi_pending - assign nmi_pending = rg_nmi ; - - // action method debug - assign RDY_debug = 1'd1 ; - assign CAN_FIRE_debug = 1'd1 ; - assign WILL_FIRE_debug = EN_debug ; - - // submodule csr_mie - mkCSR_MIE csr_mie(.CLK(CLK), - .RST_N(RST_N), - .fav_sie_write_misa(csr_mie$fav_sie_write_misa), - .fav_sie_write_wordxl(csr_mie$fav_sie_write_wordxl), - .fav_write_misa(csr_mie$fav_write_misa), - .fav_write_wordxl(csr_mie$fav_write_wordxl), - .EN_reset(csr_mie$EN_reset), - .EN_fav_write(csr_mie$EN_fav_write), - .EN_fav_sie_write(csr_mie$EN_fav_sie_write), - .fv_read(csr_mie$fv_read), - .fav_write(csr_mie$fav_write), - .fv_sie_read(csr_mie$fv_sie_read), - .fav_sie_write(csr_mie$fav_sie_write)); - - // submodule csr_mip - mkCSR_MIP csr_mip(.CLK(CLK), - .RST_N(RST_N), - .fav_sip_write_misa(csr_mip$fav_sip_write_misa), - .fav_sip_write_wordxl(csr_mip$fav_sip_write_wordxl), - .fav_write_misa(csr_mip$fav_write_misa), - .fav_write_wordxl(csr_mip$fav_write_wordxl), - .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), - .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), - .software_interrupt_req_req(csr_mip$software_interrupt_req_req), - .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), - .EN_reset(csr_mip$EN_reset), - .EN_fav_write(csr_mip$EN_fav_write), - .EN_fav_sip_write(csr_mip$EN_fav_sip_write), - .fv_read(csr_mip$fv_read), - .fav_write(csr_mip$fav_write), - .fv_sip_read(csr_mip$fv_sip_read), - .fav_sip_write(csr_mip$fav_sip_write)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), - .m_nmivec_reset_value(soc_map$m_nmivec_reset_value)); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = !rg_state ; - assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_mcycle_incr - assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; - assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; - - // rule RL_rl_upd_minstret_csrrx - assign CAN_FIRE_RL_rl_upd_minstret_csrrx = - MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; - assign WILL_FIRE_RL_rl_upd_minstret_csrrx = - CAN_FIRE_RL_rl_upd_minstret_csrrx ; - - // rule RL_rl_upd_minstret_incr - assign CAN_FIRE_RL_rl_upd_minstret_incr = - !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; - assign WILL_FIRE_RL_rl_upd_minstret_incr = - CAN_FIRE_RL_rl_upd_minstret_incr ; - - // inputs to muxes for submodule ports - assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 ; - assign MUX_rg_fflags$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 ; - assign MUX_rg_frm$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 ; - assign MUX_rg_mcause$write_1__SEL_2 = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) ; - assign MUX_rg_mcause$write_1__SEL_3 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 ; - assign MUX_rg_mcounteren$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 ; - assign MUX_rg_medeleg$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 ; - assign MUX_rg_mideleg$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 ; - assign MUX_rg_mtvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 ; - assign MUX_rg_satp$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 ; - assign MUX_rg_scause$write_1__SEL_2 = - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h11323 == 2'b01 ; - assign MUX_rg_scause$write_1__SEL_3 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 ; - assign MUX_rg_sepc$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; - assign MUX_rg_stval$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 ; - assign MUX_rg_stvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 ; - assign MUX_rg_tdata1$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 ; - assign MUX_rw_minstret$wset_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851 ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 = - { sd__h13499, 40'd5120, fixed_up_val_23__h13500 } ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 = - { sd__h9711, 40'd5120, fixed_up_val_23__h9712 } ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_5 = - { sd__h7689, - 40'd5120, - (mav_csr_write_csr_addr == 12'h100) ? - fixed_up_val_23__h6191 : - fixed_up_val_23__h7690 } ; - assign MUX_rg_fflags$write_1__VAL_3 = - rg_fflags | ma_update_fcsr_fflags_flags ; - assign MUX_rg_frm$write_1__VAL_1 = - (mav_csr_write_csr_addr == 12'h002) ? - mav_csr_write_word[2:0] : - mav_csr_write_word[7:5] ; - assign MUX_rg_mcause$write_1__VAL_2 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - exc_code__h13279 } ; - assign MUX_rg_mcause$write_1__VAL_3 = - { mav_csr_write_word[63], mav_csr_write_word[3:0] } ; - assign MUX_rg_medeleg$write_1__VAL_1 = - { mav_csr_write_word[15], - 1'd0, - mav_csr_write_word[13:12], - 2'd0, - mav_csr_write_word[9:0] } ; - assign MUX_rg_minstret$write_1__VAL_1 = - MUX_rw_minstret$wset_1__SEL_1 ? mav_csr_write_word : 64'd0 ; - assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; - assign MUX_rg_mtvec$write_1__VAL_1 = - { mav_csr_write_word[63:2], mav_csr_write_word[0] } ; - assign MUX_rg_mtvec$write_1__VAL_2 = - { soc_map$m_mtvec_reset_value[63:2], - soc_map$m_mtvec_reset_value[0] } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register csr_mstatus_rg_mstatus - always@(WILL_FIRE_RL_rl_reset_start or - EN_csr_ret_actions or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 or - EN_csr_trap_actions or - v__h11328 or - EN_ma_update_mstatus_fs or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 or - MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: - csr_mstatus_rg_mstatus$D_IN = 64'h0000000A00002000; - EN_csr_ret_actions: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_2; - EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = v__h11328; - EN_ma_update_mstatus_fs: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_4; - MUX_csr_mstatus_rg_mstatus$write_1__SEL_5: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_5; - default: csr_mstatus_rg_mstatus$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign csr_mstatus_rg_mstatus$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 || - EN_csr_trap_actions || - EN_ma_update_mstatus_fs || - EN_csr_ret_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_dcsr - assign rg_dcsr$D_IN = 32'h0 ; - assign rg_dcsr$EN = 1'b0 ; - - // register rg_dpc - assign rg_dpc$D_IN = 64'h0 ; - assign rg_dpc$EN = 1'b0 ; - - // register rg_dscratch0 - assign rg_dscratch0$D_IN = 64'h0 ; - assign rg_dscratch0$EN = 1'b0 ; - - // register rg_dscratch1 - assign rg_dscratch1$D_IN = 64'h0 ; - assign rg_dscratch1$EN = 1'b0 ; - - // register rg_fflags - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_fflags$write_1__SEL_2 or - mav_csr_write_word or - EN_ma_update_fcsr_fflags or MUX_rg_fflags$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_fflags$D_IN = 5'd0; - MUX_rg_fflags$write_1__SEL_2: rg_fflags$D_IN = mav_csr_write_word[4:0]; - EN_ma_update_fcsr_fflags: rg_fflags$D_IN = MUX_rg_fflags$write_1__VAL_3; - default: rg_fflags$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_fflags$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 || - EN_ma_update_fcsr_fflags || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_frm - assign rg_frm$D_IN = - MUX_rg_frm$write_1__SEL_1 ? MUX_rg_frm$write_1__VAL_1 : 3'd0 ; - assign rg_frm$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_mcause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - MUX_rg_mcause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; - MUX_rg_mcause$write_1__SEL_2: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; - MUX_rg_mcause$write_1__SEL_3: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_mcause$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcounteren - assign rg_mcounteren$D_IN = - MUX_rg_mcounteren$write_1__SEL_1 ? - mav_csr_write_word[2:0] : - 3'd0 ; - assign rg_mcounteren$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcycle - assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; - assign rg_mcycle$EN = 1'd1 ; - - // register rg_medeleg - assign rg_medeleg$D_IN = - MUX_rg_medeleg$write_1__SEL_1 ? - MUX_rg_medeleg$write_1__VAL_1 : - 16'd0 ; - assign rg_medeleg$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mepc - assign rg_mepc$D_IN = - MUX_rg_mcause$write_1__SEL_2 ? - csr_trap_actions_pc : - mav_csr_write_word ; - assign rg_mepc$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841 ; - - // register rg_mideleg - assign rg_mideleg$D_IN = - MUX_rg_mideleg$write_1__SEL_1 ? - mav_csr_write_word[11:0] : - 12'd0 ; - assign rg_mideleg$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_minstret - assign rg_minstret$D_IN = - WILL_FIRE_RL_rl_upd_minstret_csrrx ? - MUX_rg_minstret$write_1__VAL_1 : - MUX_rg_minstret$write_1__VAL_2 ; - assign rg_minstret$EN = - WILL_FIRE_RL_rl_upd_minstret_csrrx || - WILL_FIRE_RL_rl_upd_minstret_incr ; - - // register rg_mscratch - assign rg_mscratch$D_IN = mav_csr_write_word ; - assign rg_mscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 ; - - // register rg_mtval - assign rg_mtval$D_IN = - MUX_rg_mcause$write_1__SEL_2 ? - csr_trap_actions_xtval : - mav_csr_write_word ; - assign rg_mtval$EN = - EN_csr_trap_actions && - (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) || - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845 ; - - // register rg_mtvec - assign rg_mtvec$D_IN = - MUX_rg_mtvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_mtvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_nmi - assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ; - assign rg_nmi$EN = 1'b1 ; - - // register rg_nmi_vector - assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value ; - assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_satp - assign rg_satp$D_IN = - MUX_rg_satp$write_1__SEL_1 ? mav_csr_write_word : 64'd0 ; - assign rg_satp$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_scause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_scause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - MUX_rg_scause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_scause$D_IN = 5'd0; - MUX_rg_scause$write_1__SEL_2: - rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_2; - MUX_rg_scause$write_1__SEL_3: - rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_scause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_scause$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h11323 == 2'b01 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_sepc - assign rg_sepc$D_IN = - MUX_rg_sepc$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_pc ; - assign rg_sepc$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h11323 == 2'b01 ; - - // register rg_sscratch - assign rg_sscratch$D_IN = mav_csr_write_word ; - assign rg_sscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808 ; - - // register rg_state - assign rg_state$D_IN = !EN_server_reset_request_put ; - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; - - // register rg_stval - assign rg_stval$D_IN = - MUX_rg_stval$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_xtval ; - assign rg_stval$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 || - EN_csr_trap_actions && !csr_trap_actions_nmi && - new_priv__h11323 == 2'b01 ; - - // register rg_stvec - assign rg_stvec$D_IN = - MUX_rg_stvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_stvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata1 - assign rg_tdata1$D_IN = - MUX_rg_tdata1$write_1__SEL_1 ? result__h9129 : 64'd0 ; - assign rg_tdata1$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata2 - assign rg_tdata2$D_IN = mav_csr_write_word ; - assign rg_tdata2$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859 ; - - // register rg_tdata3 - assign rg_tdata3$D_IN = mav_csr_write_word ; - assign rg_tdata3$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861 ; - - // register rg_tselect - assign rg_tselect$D_IN = 64'd0 ; - assign rg_tselect$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853 || - WILL_FIRE_RL_rl_reset_start ; - - // submodule csr_mie - assign csr_mie$fav_sie_write_misa = 28'd135532845 ; - assign csr_mie$fav_sie_write_wordxl = mav_csr_write_word ; - assign csr_mie$fav_write_misa = 28'd135532845 ; - assign csr_mie$fav_write_wordxl = mav_csr_write_word ; - assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mie$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833 ; - assign csr_mie$EN_fav_sie_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801 ; - - // submodule csr_mip - assign csr_mip$fav_sip_write_misa = 28'd135532845 ; - assign csr_mip$fav_sip_write_wordxl = mav_csr_write_word ; - assign csr_mip$fav_write_misa = 28'd135532845 ; - assign csr_mip$fav_write_wordxl = mav_csr_write_word ; - assign csr_mip$m_external_interrupt_req_req = - m_external_interrupt_req_set_not_clear ; - assign csr_mip$s_external_interrupt_req_req = - s_external_interrupt_req_set_not_clear ; - assign csr_mip$software_interrupt_req_req = - software_interrupt_req_set_not_clear ; - assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; - assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mip$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847 ; - assign csr_mip$EN_fav_sip_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275 = - (new_priv__h11323 == 2'b11) ? - { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[63:13], - csr_trap_actions_from_priv, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[10:0] } : - { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[63:9], - csr_trap_actions_from_priv[0], - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267[7:0] } ; - assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923 = - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && - NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 && - NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865) ? - 4'd9 : - ((NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && - NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856) ? - 4'd7 : - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 ? - 4'd3 : - 4'd11)) ; - assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925 = - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && - NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883) ? - 4'd5 : - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 ? - 4'd1 : - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1923) ; - assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926 = - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && - NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 && - NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892) ? - 4'd8 : - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1925 ; - assign IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1928 = - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 && - NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910) ? - 4'd4 : - (NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 ? - 4'd0 : - IF_NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_N_ETC___d1926) ; - assign IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774 = - (csr_mstatus_rg_mstatus[12:11] == 2'b10) ? - 2'b01 : - csr_mstatus_rg_mstatus[12:11] ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477 = - (csr_ret_actions_from_priv == 2'b11) ? - _theResult___fst__h13593 : - _theResult___fst__h13794 ; - assign NOT_access_permitted_1_csr_addr_ULT_0xC03_498__ETC___d1598 = - (access_permitted_1_csr_addr >= 12'hC03 && - access_permitted_1_csr_addr <= 12'hC1F || - access_permitted_1_csr_addr >= 12'hB03 && - access_permitted_1_csr_addr <= 12'hB1F || - access_permitted_1_csr_addr >= 12'h323 && - access_permitted_1_csr_addr <= 12'h33F || - access_permitted_1_csr_addr == 12'h001 || - access_permitted_1_csr_addr == 12'h002 || - access_permitted_1_csr_addr == 12'h003 || - access_permitted_1_csr_addr == 12'hC00 || - access_permitted_1_csr_addr == 12'hC02 || - access_permitted_1_csr_addr == 12'h100 || - access_permitted_1_csr_addr == 12'h102 || - access_permitted_1_csr_addr == 12'h103 || - access_permitted_1_csr_addr == 12'h104 || - access_permitted_1_csr_addr == 12'h105 || - access_permitted_1_csr_addr == 12'h106 || - access_permitted_1_csr_addr == 12'h140 || - access_permitted_1_csr_addr == 12'h141 || - access_permitted_1_csr_addr == 12'h142 || - access_permitted_1_csr_addr == 12'h143 || - access_permitted_1_csr_addr == 12'h144 || - access_permitted_1_csr_addr == 12'h180 || - access_permitted_1_csr_addr == 12'h302 || - access_permitted_1_csr_addr == 12'h303 || - access_permitted_1_csr_addr == 12'hF11 || - access_permitted_1_csr_addr == 12'hF12 || - access_permitted_1_csr_addr == 12'hF13 || - access_permitted_1_csr_addr == 12'hF14 || - access_permitted_1_csr_addr == 12'h300 || - access_permitted_1_csr_addr == 12'h301 || - access_permitted_1_csr_addr == 12'h304 || - access_permitted_1_csr_addr == 12'h305 || - access_permitted_1_csr_addr == 12'h306 || - access_permitted_1_csr_addr == 12'h340 || - access_permitted_1_csr_addr == 12'h341 || - access_permitted_1_csr_addr == 12'h342 || - access_permitted_1_csr_addr == 12'h343 || - access_permitted_1_csr_addr == 12'h344 || - access_permitted_1_csr_addr == 12'hB00 || - access_permitted_1_csr_addr == 12'hB02 || - access_permitted_1_csr_addr == 12'h7A0 || - access_permitted_1_csr_addr == 12'h7A1 || - access_permitted_1_csr_addr == 12'h7A2 || - access_permitted_1_csr_addr == 12'h7A3) && - access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && - (access_permitted_1_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_access_permitted_2_csr_addr_ULT_0xC03_603__ETC___d1701 = - (access_permitted_2_csr_addr >= 12'hC03 && - access_permitted_2_csr_addr <= 12'hC1F || - access_permitted_2_csr_addr >= 12'hB03 && - access_permitted_2_csr_addr <= 12'hB1F || - access_permitted_2_csr_addr >= 12'h323 && - access_permitted_2_csr_addr <= 12'h33F || - access_permitted_2_csr_addr == 12'h001 || - access_permitted_2_csr_addr == 12'h002 || - access_permitted_2_csr_addr == 12'h003 || - access_permitted_2_csr_addr == 12'hC00 || - access_permitted_2_csr_addr == 12'hC02 || - access_permitted_2_csr_addr == 12'h100 || - access_permitted_2_csr_addr == 12'h102 || - access_permitted_2_csr_addr == 12'h103 || - access_permitted_2_csr_addr == 12'h104 || - access_permitted_2_csr_addr == 12'h105 || - access_permitted_2_csr_addr == 12'h106 || - access_permitted_2_csr_addr == 12'h140 || - access_permitted_2_csr_addr == 12'h141 || - access_permitted_2_csr_addr == 12'h142 || - access_permitted_2_csr_addr == 12'h143 || - access_permitted_2_csr_addr == 12'h144 || - access_permitted_2_csr_addr == 12'h180 || - access_permitted_2_csr_addr == 12'h302 || - access_permitted_2_csr_addr == 12'h303 || - access_permitted_2_csr_addr == 12'hF11 || - access_permitted_2_csr_addr == 12'hF12 || - access_permitted_2_csr_addr == 12'hF13 || - access_permitted_2_csr_addr == 12'hF14 || - access_permitted_2_csr_addr == 12'h300 || - access_permitted_2_csr_addr == 12'h301 || - access_permitted_2_csr_addr == 12'h304 || - access_permitted_2_csr_addr == 12'h305 || - access_permitted_2_csr_addr == 12'h306 || - access_permitted_2_csr_addr == 12'h340 || - access_permitted_2_csr_addr == 12'h341 || - access_permitted_2_csr_addr == 12'h342 || - access_permitted_2_csr_addr == 12'h343 || - access_permitted_2_csr_addr == 12'h344 || - access_permitted_2_csr_addr == 12'hB00 || - access_permitted_2_csr_addr == 12'hB02 || - access_permitted_2_csr_addr == 12'h7A0 || - access_permitted_2_csr_addr == 12'h7A1 || - access_permitted_2_csr_addr == 12'h7A2 || - access_permitted_2_csr_addr == 12'h7A3) && - access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && - (access_permitted_2_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_cfg_verbosity_read__42_ULE_1_43___d944 = cfg_verbosity > 4'd1 ; - assign NOT_csr_mip_fv_read__53_BIT_0_812_903_OR_NOT_c_ETC___d1910 = - !csr_mip$fv_read[0] || !csr_mie$fv_read[0] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 = - !csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 = - NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1848 && - NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 && - NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865 && - NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874 ; - assign NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1902 = - NOT_csr_mip_fv_read__53_BIT_11_728_834_OR_NOT__ETC___d1875 && - NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 && - NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892 && - NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901 ; - assign NOT_csr_mip_fv_read__53_BIT_1_779_876_OR_NOT_c_ETC___d1883 = - !csr_mip$fv_read[1] || !csr_mie$fv_read[1] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_3_746_849_OR_NOT_c_ETC___d1856 = - !csr_mip$fv_read[3] || !csr_mie$fv_read[3] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_5_790_885_OR_NOT_c_ETC___d1892 = - !csr_mip$fv_read[5] || !csr_mie$fv_read[5] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_7_757_858_OR_NOT_c_ETC___d1865 = - !csr_mip$fv_read[7] || !csr_mie$fv_read[7] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_8_801_894_OR_NOT_c_ETC___d1901 = - !csr_mip$fv_read[8] || !csr_mie$fv_read[8] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_mip_fv_read__53_BIT_9_768_867_OR_NOT_c_ETC___d1874 = - !csr_mip$fv_read[9] || !csr_mie$fv_read[9] || - !interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 && - (!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 || - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845) ; - assign NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402 = - !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h13279 != 4'd0 && - exc_code__h13279 != 4'd1 && - exc_code__h13279 != 4'd2 && - exc_code__h13279 != 4'd3 && - exc_code__h13279 != 4'd4 && - exc_code__h13279 != 4'd5 && - exc_code__h13279 != 4'd6 && - exc_code__h13279 != 4'd7 && - exc_code__h13279 != 4'd8 && - exc_code__h13279 != 4'd9 && - exc_code__h13279 != 4'd10 && - exc_code__h13279 != 4'd11 ; - assign _theResult____h15189 = rg_mideleg[11] ? 2'b01 : 2'b11 ; - assign _theResult____h15401 = rg_mideleg[3] ? 2'b01 : 2'b11 ; - assign _theResult____h15613 = rg_mideleg[7] ? 2'b01 : 2'b11 ; - assign _theResult____h15825 = rg_mideleg[9] ? 2'b01 : 2'b11 ; - assign _theResult____h16037 = rg_mideleg[1] ? 2'b01 : 2'b11 ; - assign _theResult____h16249 = rg_mideleg[5] ? 2'b01 : 2'b11 ; - assign _theResult____h16461 = rg_mideleg[8] ? 2'b01 : 2'b11 ; - assign _theResult____h16673 = rg_mideleg[0] ? 2'b01 : 2'b11 ; - assign _theResult____h16885 = rg_mideleg[4] ? 2'b01 : 2'b11 ; - assign _theResult___fst__h11461 = - (csr_trap_actions_interrupt ? - deleg_bit___1__h11470 : - deleg_bit___1__h11485) ? - 2'b01 : - 2'b11 ; - assign _theResult___fst__h13593 = - { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[63:13], - 2'd0, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[10:0] } ; - assign _theResult___fst__h13794 = - { csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[63:9], - 1'd0, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[7:0] } ; - assign b__h11548 = csr_mstatus_rg_mstatus[ie_to_x__h11449] ; - assign b__h13630 = csr_mstatus_rg_mstatus[pie_from_x__h13578] ; - assign csr_mip_fv_read__53_BIT_0_812_AND_csr_mie_fv_r_ETC___d1821 = - csr_mip$fv_read[0] && csr_mie$fv_read[0] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745 = - csr_mip$fv_read[11] && csr_mie$fv_read[11] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1811 = - csr_mip_fv_read__53_BIT_11_728_AND_csr_mie_fv__ETC___d1745 || - csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755 || - csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766 || - csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777 || - csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788 || - csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799 || - csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810 ; - assign csr_mip_fv_read__53_BIT_1_779_AND_csr_mie_fv_r_ETC___d1788 = - csr_mip$fv_read[1] && csr_mie$fv_read[1] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_3_746_AND_csr_mie_fv_r_ETC___d1755 = - csr_mip$fv_read[3] && csr_mie$fv_read[3] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_4_823_AND_csr_mie_fv_r_ETC___d1832 = - csr_mip$fv_read[4] && csr_mie$fv_read[4] && - (interrupt_pending_cur_priv < _theResult____h16885 || - interrupt_pending_cur_priv == _theResult____h16885 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_5_790_AND_csr_mie_fv_r_ETC___d1799 = - csr_mip$fv_read[5] && csr_mie$fv_read[5] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_7_757_AND_csr_mie_fv_r_ETC___d1766 = - csr_mip$fv_read[7] && csr_mie$fv_read[7] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_8_801_AND_csr_mie_fv_r_ETC___d1810 = - csr_mip$fv_read[8] && csr_mie$fv_read[8] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mip_fv_read__53_BIT_9_768_AND_csr_mie_fv_r_ETC___d1777 = - csr_mip$fv_read[9] && csr_mie$fv_read[9] && - (interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 || - interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 && - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742) ; - assign csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470 = - x__h13626 | mask__h13614 ; - assign csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1267 = - x__h11544 | val__h11533 ; - assign csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301 = - csr_trap_actions_interrupt && !csr_trap_actions_nmi && - CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 ; - assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453 = - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 != 4'd0 && - exc_code__h13279 != 4'd1 && - exc_code__h13279 != 4'd2 && - exc_code__h13279 != 4'd3 && - exc_code__h13279 != 4'd4 && - exc_code__h13279 != 4'd5 && - exc_code__h13279 != 4'd6 && - exc_code__h13279 != 4'd7 && - exc_code__h13279 != 4'd8 && - exc_code__h13279 != 4'd9 && - exc_code__h13279 != 4'd11 && - exc_code__h13279 != 4'd12 && - exc_code__h13279 != 4'd13 && - exc_code__h13279 != 4'd15 ; - assign deleg_bit___1__h11470 = rg_mideleg[csr_trap_actions_exc_code] ; - assign deleg_bit___1__h11485 = rg_medeleg[csr_trap_actions_exc_code] ; - assign exc_code__h13279 = - csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; - assign exc_pc___1__h12586 = exc_pc__h12512 + vector_offset__h12513 ; - assign exc_pc__h12512 = - csr_trap_actions_nmi ? - rg_nmi_vector : - y_avValue_snd_snd__h12559 ; - assign fixed_up_val_23__h11372 = - { IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[22:17], - 2'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13], - (IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[12:11] == - 2'b10) ? - 2'b01 : - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[12:11], - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[10:5], - 1'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[3:1], - 1'd0 } ; - assign fixed_up_val_23__h13500 = - { IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[22:17], - 2'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[14:13], - (IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[12:11] == - 2'b10) ? - 2'b01 : - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[12:11], - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[10:5], - 1'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[3:1], - 1'd0 } ; - assign fixed_up_val_23__h6191 = - { csr_mstatus_rg_mstatus[22:20], - mav_csr_write_word[19:18], - csr_mstatus_rg_mstatus[17], - 2'd0, - mav_csr_write_word[14:13], - IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, - csr_mstatus_rg_mstatus[10:9], - mav_csr_write_word[8], - csr_mstatus_rg_mstatus[7:6], - mav_csr_write_word[5], - 1'd0, - csr_mstatus_rg_mstatus[3:2], - mav_csr_write_word[1], - 1'd0 } ; - assign fixed_up_val_23__h7690 = - { mav_csr_write_word[22:17], - 2'd0, - mav_csr_write_word[14:13], - (mav_csr_write_word[12:11] == 2'b10) ? - 2'b01 : - mav_csr_write_word[12:11], - mav_csr_write_word[10:5], - 1'd0, - mav_csr_write_word[3:1], - 1'd0 } ; - assign fixed_up_val_23__h9712 = - { csr_mstatus_rg_mstatus[22:17], - 2'd0, - ma_update_mstatus_fs_fs, - IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_72__ETC___d774, - csr_mstatus_rg_mstatus[10:5], - 1'd0, - csr_mstatus_rg_mstatus[3:1], - 1'd0 } ; - assign ie_from_x__h13577 = { 4'd0, csr_ret_actions_from_priv } ; - assign ie_to_x__h11449 = { 4'd0, new_priv__h11323 } ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1734 = - interrupt_pending_cur_priv == _theResult____h15189 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1752 = - interrupt_pending_cur_priv == _theResult____h15401 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1763 = - interrupt_pending_cur_priv == _theResult____h15613 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1774 = - interrupt_pending_cur_priv == _theResult____h15825 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1785 = - interrupt_pending_cur_priv == _theResult____h16037 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1796 = - interrupt_pending_cur_priv == _theResult____h16249 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1807 = - interrupt_pending_cur_priv == _theResult____h16461 ; - assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1818 = - interrupt_pending_cur_priv == _theResult____h16673 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1733 = - interrupt_pending_cur_priv < _theResult____h15189 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1751 = - interrupt_pending_cur_priv < _theResult____h15401 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1762 = - interrupt_pending_cur_priv < _theResult____h15613 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1773 = - interrupt_pending_cur_priv < _theResult____h15825 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1784 = - interrupt_pending_cur_priv < _theResult____h16037 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1795 = - interrupt_pending_cur_priv < _theResult____h16249 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1806 = - interrupt_pending_cur_priv < _theResult____h16461 ; - assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1817 = - interrupt_pending_cur_priv < _theResult____h16673 ; - assign mask__h11532 = 64'd1 << ie_to_x__h11449 ; - assign mask__h11549 = 64'd1 << pie_to_x__h11450 ; - assign mask__h13614 = 64'd1 << pie_from_x__h13578 ; - assign mask__h13631 = 64'd1 << ie_from_x__h13577 ; - assign mav_csr_write_csr_addr_ULE_0x33F___d739 = - mav_csr_write_csr_addr <= 12'h33F ; - assign mav_csr_write_csr_addr_ULE_0xB1F___d735 = - mav_csr_write_csr_addr <= 12'hB1F ; - assign mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940 = - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr != 12'h001 && - mav_csr_write_csr_addr != 12'h002 && - mav_csr_write_csr_addr != 12'h003 && - mav_csr_write_csr_addr != 12'h100 && - mav_csr_write_csr_addr != 12'h102 && - mav_csr_write_csr_addr != 12'h103 && - mav_csr_write_csr_addr != 12'h104 && - mav_csr_write_csr_addr != 12'h105 && - mav_csr_write_csr_addr != 12'h106 && - mav_csr_write_csr_addr != 12'h140 && - mav_csr_write_csr_addr != 12'h141 && - mav_csr_write_csr_addr != 12'h142 && - mav_csr_write_csr_addr != 12'h143 && - mav_csr_write_csr_addr != 12'h144 && - mav_csr_write_csr_addr != 12'h180 && - mav_csr_write_csr_addr != 12'h302 && - mav_csr_write_csr_addr != 12'h303 && - mav_csr_write_csr_addr != 12'hF11 && - mav_csr_write_csr_addr != 12'hF12 && - mav_csr_write_csr_addr != 12'hF13 && - mav_csr_write_csr_addr != 12'hF14 && - mav_csr_write_csr_addr != 12'h300 && - mav_csr_write_csr_addr != 12'h301 && - mav_csr_write_csr_addr != 12'h304 && - mav_csr_write_csr_addr != 12'h305 && - mav_csr_write_csr_addr != 12'h306 && - mav_csr_write_csr_addr != 12'h340 && - mav_csr_write_csr_addr != 12'h341 && - mav_csr_write_csr_addr != 12'h342 && - mav_csr_write_csr_addr != 12'h343 && - mav_csr_write_csr_addr != 12'h344 && - mav_csr_write_csr_addr != 12'hB00 && - mav_csr_write_csr_addr != 12'hB02 && - mav_csr_write_csr_addr != 12'h7A0 && - mav_csr_write_csr_addr != 12'h7A1 && - mav_csr_write_csr_addr != 12'h7A2 && - mav_csr_write_csr_addr != 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0x323___d738 = - mav_csr_write_csr_addr < 12'h323 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - (mav_csr_write_csr_addr == 12'h001 || - mav_csr_write_csr_addr == 12'h003) ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d752 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - (mav_csr_write_csr_addr == 12'h002 || - mav_csr_write_csr_addr == 12'h003) ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d764 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - (mav_csr_write_csr_addr == 12'h100 || - mav_csr_write_csr_addr == 12'h300) ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d801 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h104 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h105 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h140 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h141 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d812 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h142 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h143 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d819 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h144 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h180 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d823 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h302 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h303 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d833 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h304 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d835 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h305 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d837 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h306 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h340 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d841 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h341 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d843 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h342 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d845 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h343 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d847 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h344 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d851 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'hB02 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d853 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h7A0 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d855 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h7A1 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d859 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h7A2 ; - assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d861 = - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - (mav_csr_write_csr_addr_ULT_0x323___d738 || - !mav_csr_write_csr_addr_ULE_0x33F___d739) && - mav_csr_write_csr_addr == 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0xB03___d734 = - mav_csr_write_csr_addr < 12'hB03 ; - assign new_priv__h11323 = - csr_trap_actions_nmi ? - 2'b11 : - ((csr_trap_actions_from_priv == 2'b11) ? - csr_trap_actions_from_priv : - _theResult___fst__h11461) ; - assign pie_from_x__h13578 = { 4'd1, csr_ret_actions_from_priv } ; - assign pie_to_x__h11450 = { 4'd1, new_priv__h11323 } ; - assign result__h9129 = { 4'd0, mav_csr_write_word[59:0] } ; - assign sd__h11371 = - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13] == - 2'h3 ; - assign sd__h13499 = - IF_csr_ret_actions_from_priv_EQ_0b11_457_THEN__ETC___d1477[14:13] == - 2'h3 ; - assign sd__h7689 = mav_csr_write_word[14:13] == 2'h3 ; - assign sd__h9711 = ma_update_mstatus_fs_fs == 2'h3 ; - assign to_y__h13793 = - { 1'b0, - csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1470[8] } ; - assign v__h11328 = { sd__h11371, 40'd5120, fixed_up_val_23__h11372 } ; - assign v__h5882 = { 59'd0, mav_csr_write_word[4:0] } ; - assign v__h6026 = { 56'd0, mav_csr_write_word[7:0] } ; - assign v__h6140 = - { sd__h7689, - 43'd8192, - mav_csr_write_word[19:18], - 3'd0, - mav_csr_write_word[14:13], - 4'd0, - mav_csr_write_word[8], - 2'd0, - mav_csr_write_word[5], - 3'd0, - mav_csr_write_word[1], - 1'd0 } ; - assign v__h7518 = - { 48'd0, - mav_csr_write_word[15], - 1'd0, - mav_csr_write_word[13:12], - 2'd0, - mav_csr_write_word[9:0] } ; - assign v__h7554 = { 52'd0, mav_csr_write_word[11:0] } ; - assign v__h8224 = - { mav_csr_write_word[63:2], 1'b0, mav_csr_write_word[0] } ; - assign v__h8286 = { 61'd0, mav_csr_write_word[2:0] } ; - assign v__h8442 = - { mav_csr_write_word[63], 59'd0, mav_csr_write_word[3:0] } ; - assign val__h11533 = 64'd0 << ie_to_x__h11449 ; - assign val__h11550 = { 63'd0, b__h11548 } << pie_to_x__h11450 ; - assign val__h13632 = { 63'd0, b__h13630 } << ie_from_x__h13577 ; - assign vector_offset__h12513 = { 58'd0, csr_trap_actions_exc_code, 2'd0 } ; - assign wordxl1__h7649 = { sd__h7689, 40'd5120, fixed_up_val_23__h7690 } ; - assign x__h10300 = - csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1301 ? - exc_pc___1__h12586 : - exc_pc__h12512 ; - assign x__h11531 = x__h11561 | val__h11550 ; - assign x__h11544 = x__h11531 & y__h11545 ; - assign x__h11561 = csr_mstatus_rg_mstatus & y__h11562 ; - assign x__h13437 = - (csr_trap_actions_nmi || new_priv__h11323 == 2'b11) ? - v__h11328 : - y_avValue_fst__h12486 ; - assign x__h13438 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - 59'd0, - exc_code__h13279 } ; - assign x__h13613 = x__h13643 | val__h13632 ; - assign x__h13626 = x__h13613 & y__h13627 ; - assign x__h13643 = csr_mstatus_rg_mstatus & y__h13644 ; - assign y__h11545 = ~mask__h11532 ; - assign y__h11562 = ~mask__h11549 ; - assign y__h13627 = ~mask__h13614 ; - assign y__h13644 = ~mask__h13631 ; - assign y_avValue_fst__h12469 = - { sd__h11371, - 43'd8192, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[19:18], - 3'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[14:13], - 4'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[8], - 2'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[5], - 3'd0, - IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1275[1], - 1'd0 } ; - assign y_avValue_fst__h12486 = - (new_priv__h11323 == 2'b01) ? y_avValue_fst__h12469 : v__h11328 ; - assign y_avValue_snd_snd__h12559 = - { CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1, - 2'd0 } ; - always@(mav_csr_write_csr_addr or - v__h5882 or - v__h8286 or - v__h6026 or - v__h6140 or - csr_mie$fav_sie_write or - v__h8224 or - mav_csr_write_word or - v__h8442 or - csr_mip$fav_sip_write or - wordxl1__h7649 or - v__h7518 or - v__h7554 or csr_mie$fav_write or csr_mip$fav_write or result__h9129) - begin - case (mav_csr_write_csr_addr) - 12'h001: y_avValue_fst__h9500 = v__h5882; - 12'h002, 12'h306: y_avValue_fst__h9500 = v__h8286; - 12'h003: y_avValue_fst__h9500 = v__h6026; - 12'h100: y_avValue_fst__h9500 = v__h6140; - 12'h102, - 12'h103, - 12'h106, - 12'h301, - 12'h7A0, - 12'hF11, - 12'hF12, - 12'hF13, - 12'hF14: - y_avValue_fst__h9500 = 64'd0; - 12'h104: y_avValue_fst__h9500 = csr_mie$fav_sie_write; - 12'h105, 12'h305: y_avValue_fst__h9500 = v__h8224; - 12'h140, - 12'h141, - 12'h143, - 12'h180, - 12'h340, - 12'h341, - 12'h343, - 12'h7A2, - 12'h7A3, - 12'hB00, - 12'hB02: - y_avValue_fst__h9500 = mav_csr_write_word; - 12'h142, 12'h342: y_avValue_fst__h9500 = v__h8442; - 12'h144: y_avValue_fst__h9500 = csr_mip$fav_sip_write; - 12'h300: y_avValue_fst__h9500 = wordxl1__h7649; - 12'h302: y_avValue_fst__h9500 = v__h7518; - 12'h303: y_avValue_fst__h9500 = v__h7554; - 12'h304: y_avValue_fst__h9500 = csr_mie$fav_write; - 12'h344: y_avValue_fst__h9500 = csr_mip$fav_write; - 12'h7A1: y_avValue_fst__h9500 = result__h9129; - default: y_avValue_fst__h9500 = 64'd0; - endcase - end - always@(new_priv__h11323 or rg_mtvec or rg_stvec) - begin - case (new_priv__h11323) - 2'b01: - CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = - rg_stvec[62:1]; - 2'b11: - CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = - rg_mtvec[62:1]; - default: CASE_new_priv1323_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 = - rg_mtvec[62:1]; - endcase - end - always@(new_priv__h11323 or rg_mtvec or rg_stvec) - begin - case (new_priv__h11323) - 2'b01: - CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_stvec[0]; - 2'b11: - CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_mtvec[0]; - default: CASE_new_priv1323_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 = - rg_mtvec[0]; - endcase - end - always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) - begin - case (interrupt_pending_cur_priv) - 2'b0: - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = - csr_mstatus_rg_mstatus[0]; - 2'b01: - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = - csr_mstatus_rg_mstatus[1]; - default: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1742 = - interrupt_pending_cur_priv == 2'b11 && - csr_mstatus_rg_mstatus[3]; - endcase - end - always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus) - begin - case (interrupt_pending_cur_priv) - 2'b0: - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = - !csr_mstatus_rg_mstatus[0]; - 2'b01: - IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = - !csr_mstatus_rg_mstatus[1]; - default: IF_interrupt_pending_cur_priv_EQ_0b0_735_THEN__ETC___d1845 = - interrupt_pending_cur_priv != 2'b11 || - !csr_mstatus_rg_mstatus[3]; - endcase - end - always@(read_csr_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_csr_addr) - 12'h001: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 59'd0, rg_fflags }; - 12'h002: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 61'd0, rg_frm }; - 12'h003: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 56'd0, rg_frm, rg_fflags }; - 12'h100: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = 64'd0; - 12'h104: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - csr_mie$fv_sie_read; - 12'h105: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { rg_stvec[62:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_sscratch; - 12'h141: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_sepc; - 12'h142: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { rg_scause[4], 59'd0, rg_scause[3:0] }; - 12'h143: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_stval; - 12'h144: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - csr_mip$fv_sip_read; - 12'h180: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_satp; - 12'h300: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - 64'h800000000014112D; - 12'h302: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 48'd0, rg_medeleg }; - 12'h303: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 52'd0, rg_mideleg }; - 12'h304: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_mscratch; - 12'h341: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mepc; - 12'h342: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_mtval; - 12'h344: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_tselect; - 12'h7A1: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_tdata1; - 12'h7A2: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_minstret; - default: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = - rg_tdata3; - endcase - end - always@(mav_read_csr_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (mav_read_csr_csr_addr) - 12'h001: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 59'd0, rg_fflags }; - 12'h002: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 61'd0, rg_frm }; - 12'h003: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 56'd0, rg_frm, rg_fflags }; - 12'h100: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = 64'd0; - 12'h104: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - csr_mie$fv_sie_read; - 12'h105: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { rg_stvec[62:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_sscratch; - 12'h141: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_sepc; - 12'h142: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { rg_scause[4], 59'd0, rg_scause[3:0] }; - 12'h143: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_stval; - 12'h144: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - csr_mip$fv_sip_read; - 12'h180: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_satp; - 12'h300: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - 64'h800000000014112D; - 12'h302: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 48'd0, rg_medeleg }; - 12'h303: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 52'd0, rg_mideleg }; - 12'h304: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - csr_mie$fv_read; - 12'h305: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_mscratch; - 12'h341: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mepc; - 12'h342: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_mtval; - 12'h344: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - csr_mip$fv_read; - 12'h7A0: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_tselect; - 12'h7A1: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_tdata1; - 12'h7A2: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_minstret; - default: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = - rg_tdata3; - endcase - end - always@(read_csr_port2_csr_addr or - rg_tdata3 or - rg_fflags or - rg_frm or - csr_mstatus_rg_mstatus or - csr_mie$fv_sie_read or - rg_stvec or - rg_sscratch or - rg_sepc or - rg_scause or - rg_stval or - csr_mip$fv_sip_read or - rg_satp or - rg_medeleg or - rg_mideleg or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_port2_csr_addr) - 12'h001: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 59'd0, rg_fflags }; - 12'h002: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 61'd0, rg_frm }; - 12'h003: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 56'd0, rg_frm, rg_fflags }; - 12'h100: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }; - 12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = 64'd0; - 12'h104: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - csr_mie$fv_sie_read; - 12'h105: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { rg_stvec[62:1], 1'b0, rg_stvec[0] }; - 12'h140: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_sscratch; - 12'h141: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_sepc; - 12'h142: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { rg_scause[4], 59'd0, rg_scause[3:0] }; - 12'h143: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_stval; - 12'h144: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - csr_mip$fv_sip_read; - 12'h180: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_satp; - 12'h300: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - 64'h800000000014112D; - 12'h302: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 48'd0, rg_medeleg }; - 12'h303: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 52'd0, rg_mideleg }; - 12'h304: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_mscratch; - 12'h341: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mepc; - 12'h342: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_mtval; - 12'h344: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_tselect; - 12'h7A1: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_tdata1; - 12'h7A2: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_minstret; - default: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = - rg_tdata3; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 64'h0000000A00002000; - rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (csr_mstatus_rg_mstatus$EN) - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY - csr_mstatus_rg_mstatus$D_IN; - if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; - if (rg_minstret$EN) - rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; - if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; - if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; - if (rg_dscratch0$EN) - rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; - if (rg_dscratch1$EN) - rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; - if (rg_fflags$EN) rg_fflags <= `BSV_ASSIGNMENT_DELAY rg_fflags$D_IN; - if (rg_frm$EN) rg_frm <= `BSV_ASSIGNMENT_DELAY rg_frm$D_IN; - if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; - if (rg_mcounteren$EN) - rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; - if (rg_medeleg$EN) rg_medeleg <= `BSV_ASSIGNMENT_DELAY rg_medeleg$D_IN; - if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; - if (rg_mideleg$EN) rg_mideleg <= `BSV_ASSIGNMENT_DELAY rg_mideleg$D_IN; - if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; - if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; - if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; - if (rg_nmi_vector$EN) - rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN; - if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; - if (rg_scause$EN) rg_scause <= `BSV_ASSIGNMENT_DELAY rg_scause$D_IN; - if (rg_sepc$EN) rg_sepc <= `BSV_ASSIGNMENT_DELAY rg_sepc$D_IN; - if (rg_sscratch$EN) rg_sscratch <= `BSV_ASSIGNMENT_DELAY rg_sscratch$D_IN; - if (rg_stval$EN) rg_stval <= `BSV_ASSIGNMENT_DELAY rg_stval$D_IN; - if (rg_stvec$EN) rg_stvec <= `BSV_ASSIGNMENT_DELAY rg_stvec$D_IN; - if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; - if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; - if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; - if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - csr_mstatus_rg_mstatus = 64'hAAAAAAAAAAAAAAAA; - rg_dcsr = 32'hAAAAAAAA; - rg_dpc = 64'hAAAAAAAAAAAAAAAA; - rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA; - rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA; - rg_fflags = 5'h0A; - rg_frm = 3'h2; - rg_mcause = 5'h0A; - rg_mcounteren = 3'h2; - rg_mcycle = 64'hAAAAAAAAAAAAAAAA; - rg_medeleg = 16'hAAAA; - rg_mepc = 64'hAAAAAAAAAAAAAAAA; - rg_mideleg = 12'hAAA; - rg_minstret = 64'hAAAAAAAAAAAAAAAA; - rg_mscratch = 64'hAAAAAAAAAAAAAAAA; - rg_mtval = 64'hAAAAAAAAAAAAAAAA; - rg_mtvec = 63'h2AAAAAAAAAAAAAAA; - rg_nmi = 1'h0; - rg_nmi_vector = 64'hAAAAAAAAAAAAAAAA; - rg_satp = 64'hAAAAAAAAAAAAAAAA; - rg_scause = 5'h0A; - rg_sepc = 64'hAAAAAAAAAAAAAAAA; - rg_sscratch = 64'hAAAAAAAAAAAAAAAA; - rg_state = 1'h0; - rg_stval = 64'hAAAAAAAAAAAAAAAA; - rg_stvec = 63'h2AAAAAAAAAAAAAAA; - rg_tdata1 = 64'hAAAAAAAAAAAAAAAA; - rg_tdata2 = 64'hAAAAAAAAAAAAAAAA; - rg_tdata3 = 64'hAAAAAAAAAAAAAAAA; - rg_tselect = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) - $display("sstatus = 0x%0h", - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("sip = 0x%0h", csr_mip$fv_sip_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("sie = 0x%0h", csr_mie$fv_sie_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mav_csr_write && - (mav_csr_write_csr_addr_ULT_0xB03___d734 || - !mav_csr_write_csr_addr_ULE_0xB1F___d735) && - mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d940 && - NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", - rg_mcycle, - mav_csr_write_csr_addr, - mav_csr_write_word); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" priv %0d: ", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" edeleg: 0x%0h", 16'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ideleg: 0x%0h", 12'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_scause[4] && - rg_scause[3:0] != 4'd0 && - rg_scause[3:0] != 4'd1 && - rg_scause[3:0] != 4'd2 && - rg_scause[3:0] != 4'd3 && - rg_scause[3:0] != 4'd4 && - rg_scause[3:0] != 4'd5 && - rg_scause[3:0] != 4'd6 && - rg_scause[3:0] != 4'd7 && - rg_scause[3:0] != 4'd8 && - rg_scause[3:0] != 4'd9 && - rg_scause[3:0] != 4'd10 && - rg_scause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_scause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_scause[4] && - rg_scause[3:0] != 4'd0 && - rg_scause[3:0] != 4'd1 && - rg_scause[3:0] != 4'd2 && - rg_scause[3:0] != 4'd3 && - rg_scause[3:0] != 4'd4 && - rg_scause[3:0] != 4'd5 && - rg_scause[3:0] != 4'd6 && - rg_scause[3:0] != 4'd7 && - rg_scause[3:0] != 4'd8 && - rg_scause[3:0] != 4'd9 && - rg_scause[3:0] != 4'd11 && - rg_scause[3:0] != 4'd12 && - rg_scause[3:0] != 4'd13 && - rg_scause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_scause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" status: 0x%0h", - { csr_mstatus_rg_mstatus[63], - 29'd0, - csr_mstatus_rg_mstatus[33:32], - 12'd0, - csr_mstatus_rg_mstatus[19:18], - 1'd0, - csr_mstatus_rg_mstatus[16:13], - 4'd0, - csr_mstatus_rg_mstatus[8], - 2'd0, - csr_mstatus_rg_mstatus[5:4], - 2'd0, - csr_mstatus_rg_mstatus[1:0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tvec: 0x%0h", { rg_stvec[62:1], 1'b0, rg_stvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" epc: 0x%0h", rg_sepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tval: 0x%0h", rg_stval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" priv %0d: ", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" edeleg: 0x%0h", rg_medeleg); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ideleg: 0x%0h", rg_mideleg); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd10 && - rg_mcause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd11 && - rg_mcause[3:0] != 4'd12 && - rg_mcause[3:0] != 4'd13 && - rg_mcause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" status: 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tvec: 0x%0h", { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" epc: 0x%0h", rg_mepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tval: 0x%0h", rg_mtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" Return: new pc 0x%0h ", x__h10300); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" new mstatus:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write("MStatus{", - "sd:%0d", - x__h13437[14:13] == 2'h3 || x__h13437[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" sxl:%0d uxl:%0d", x__h13437[35:34], x__h13437[33:32]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tsr:%0d", x__h13437[22]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tw:%0d", x__h13437[21]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" tvm:%0d", x__h13437[20]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" mxr:%0d", x__h13437[19]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" sum:%0d", x__h13437[18]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" mprv:%0d", x__h13437[17]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" xs:%0d", x__h13437[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" fs:%0d", x__h13437[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" mpp:%0d", x__h13437[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" spp:%0d", x__h13437[8]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" pies:%0d_%0d%0d", x__h13437[7], x__h13437[5], x__h13437[4]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" ies:%0d_%0d%0d", x__h13437[3], x__h13437[1], x__h13437[0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" new xcause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h13279 == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - NOT_csr_trap_actions_nmi_292_AND_csr_trap_acti_ETC___d1402) - $write("unknown interrupt Exc_Code %d", exc_code__h13279); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h13279 == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944 && - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1453) - $write("unknown trap Exc_Code %d", exc_code__h13279); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $write(" new priv %0d", new_priv__h11323); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", - rg_mcycle, - m_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", - rg_mcycle, - s_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: CSR_RegFile: timer_interrupt_req: %x", - rg_mcycle, - timer_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__42_ULE_1_43___d944) - $display("%0d: CSR_RegFile: software_interrupt_req: %x", - rg_mcycle, - software_interrupt_req_set_not_clear); - end - // synopsys translate_on -endmodule // mkCSR_RegFile - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCore.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCore.v deleted file mode 100644 index 5178628a..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkCore.v +++ /dev/null @@ -1,2499 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// cpu_reset_server_response_get O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg -// cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg -// cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg -// cpu_imem_master_bready O 1 -// cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg -// cpu_imem_master_rready O 1 -// cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg -// cpu_dmem_master_awaddr O 64 reg -// cpu_dmem_master_awlen O 8 reg -// cpu_dmem_master_awsize O 3 reg -// cpu_dmem_master_awburst O 2 reg -// cpu_dmem_master_awlock O 1 reg -// cpu_dmem_master_awcache O 4 reg -// cpu_dmem_master_awprot O 3 reg -// cpu_dmem_master_awqos O 4 reg -// cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg -// cpu_dmem_master_wdata O 64 reg -// cpu_dmem_master_wstrb O 8 reg -// cpu_dmem_master_wlast O 1 reg -// cpu_dmem_master_bready O 1 reg -// cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg -// cpu_dmem_master_araddr O 64 reg -// cpu_dmem_master_arlen O 8 reg -// cpu_dmem_master_arsize O 3 reg -// cpu_dmem_master_arburst O 2 reg -// cpu_dmem_master_arlock O 1 reg -// cpu_dmem_master_arcache O 4 reg -// cpu_dmem_master_arprot O 3 reg -// cpu_dmem_master_arqos O 4 reg -// cpu_dmem_master_arregion O 4 reg -// cpu_dmem_master_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// cpu_reset_server_request_put I 1 reg -// cpu_imem_master_awready I 1 -// cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg -// cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg -// cpu_dmem_master_awready I 1 -// cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg -// cpu_dmem_master_bresp I 2 reg -// cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg -// cpu_dmem_master_rdata I 64 reg -// cpu_dmem_master_rresp I 2 reg -// cpu_dmem_master_rlast I 1 reg -// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// nmi_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (cpu_imem_master_awready, -// cpu_imem_master_wready, -// cpu_imem_master_arready) -> cpu_imem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCore(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - cpu_reset_server_request_put, - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, - - cpu_imem_master_awvalid, - - cpu_imem_master_awid, - - cpu_imem_master_awaddr, - - cpu_imem_master_awlen, - - cpu_imem_master_awsize, - - cpu_imem_master_awburst, - - cpu_imem_master_awlock, - - cpu_imem_master_awcache, - - cpu_imem_master_awprot, - - cpu_imem_master_awqos, - - cpu_imem_master_awregion, - - cpu_imem_master_awready, - - cpu_imem_master_wvalid, - - cpu_imem_master_wid, - - cpu_imem_master_wdata, - - cpu_imem_master_wstrb, - - cpu_imem_master_wlast, - - cpu_imem_master_wready, - - cpu_imem_master_bvalid, - cpu_imem_master_bid, - cpu_imem_master_bresp, - - cpu_imem_master_bready, - - cpu_imem_master_arvalid, - - cpu_imem_master_arid, - - cpu_imem_master_araddr, - - cpu_imem_master_arlen, - - cpu_imem_master_arsize, - - cpu_imem_master_arburst, - - cpu_imem_master_arlock, - - cpu_imem_master_arcache, - - cpu_imem_master_arprot, - - cpu_imem_master_arqos, - - cpu_imem_master_arregion, - - cpu_imem_master_arready, - - cpu_imem_master_rvalid, - cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast, - - cpu_imem_master_rready, - - cpu_dmem_master_awvalid, - - cpu_dmem_master_awid, - - cpu_dmem_master_awaddr, - - cpu_dmem_master_awlen, - - cpu_dmem_master_awsize, - - cpu_dmem_master_awburst, - - cpu_dmem_master_awlock, - - cpu_dmem_master_awcache, - - cpu_dmem_master_awprot, - - cpu_dmem_master_awqos, - - cpu_dmem_master_awregion, - - cpu_dmem_master_awready, - - cpu_dmem_master_wvalid, - - cpu_dmem_master_wid, - - cpu_dmem_master_wdata, - - cpu_dmem_master_wstrb, - - cpu_dmem_master_wlast, - - cpu_dmem_master_wready, - - cpu_dmem_master_bvalid, - cpu_dmem_master_bid, - cpu_dmem_master_bresp, - - cpu_dmem_master_bready, - - cpu_dmem_master_arvalid, - - cpu_dmem_master_arid, - - cpu_dmem_master_araddr, - - cpu_dmem_master_arlen, - - cpu_dmem_master_arsize, - - cpu_dmem_master_arburst, - - cpu_dmem_master_arlock, - - cpu_dmem_master_arcache, - - cpu_dmem_master_arprot, - - cpu_dmem_master_arqos, - - cpu_dmem_master_arregion, - - cpu_dmem_master_arready, - - cpu_dmem_master_rvalid, - cpu_dmem_master_rid, - cpu_dmem_master_rdata, - cpu_dmem_master_rresp, - cpu_dmem_master_rlast, - - cpu_dmem_master_rready, - - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - - nmi_req_set_not_clear); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method cpu_reset_server_request_put - input cpu_reset_server_request_put; - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // actionvalue method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; - - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; - - // value method cpu_imem_master_m_awaddr - output [63 : 0] cpu_imem_master_awaddr; - - // value method cpu_imem_master_m_awlen - output [7 : 0] cpu_imem_master_awlen; - - // value method cpu_imem_master_m_awsize - output [2 : 0] cpu_imem_master_awsize; - - // value method cpu_imem_master_m_awburst - output [1 : 0] cpu_imem_master_awburst; - - // value method cpu_imem_master_m_awlock - output cpu_imem_master_awlock; - - // value method cpu_imem_master_m_awcache - output [3 : 0] cpu_imem_master_awcache; - - // value method cpu_imem_master_m_awprot - output [2 : 0] cpu_imem_master_awprot; - - // value method cpu_imem_master_m_awqos - output [3 : 0] cpu_imem_master_awqos; - - // value method cpu_imem_master_m_awregion - output [3 : 0] cpu_imem_master_awregion; - - // value method cpu_imem_master_m_awuser - - // action method cpu_imem_master_m_awready - input cpu_imem_master_awready; - - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; - - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - - // value method cpu_imem_master_m_wdata - output [63 : 0] cpu_imem_master_wdata; - - // value method cpu_imem_master_m_wstrb - output [7 : 0] cpu_imem_master_wstrb; - - // value method cpu_imem_master_m_wlast - output cpu_imem_master_wlast; - - // value method cpu_imem_master_m_wuser - - // action method cpu_imem_master_m_wready - input cpu_imem_master_wready; - - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; - input [1 : 0] cpu_imem_master_bresp; - - // value method cpu_imem_master_m_bready - output cpu_imem_master_bready; - - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; - - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; - - // value method cpu_imem_master_m_araddr - output [63 : 0] cpu_imem_master_araddr; - - // value method cpu_imem_master_m_arlen - output [7 : 0] cpu_imem_master_arlen; - - // value method cpu_imem_master_m_arsize - output [2 : 0] cpu_imem_master_arsize; - - // value method cpu_imem_master_m_arburst - output [1 : 0] cpu_imem_master_arburst; - - // value method cpu_imem_master_m_arlock - output cpu_imem_master_arlock; - - // value method cpu_imem_master_m_arcache - output [3 : 0] cpu_imem_master_arcache; - - // value method cpu_imem_master_m_arprot - output [2 : 0] cpu_imem_master_arprot; - - // value method cpu_imem_master_m_arqos - output [3 : 0] cpu_imem_master_arqos; - - // value method cpu_imem_master_m_arregion - output [3 : 0] cpu_imem_master_arregion; - - // value method cpu_imem_master_m_aruser - - // action method cpu_imem_master_m_arready - input cpu_imem_master_arready; - - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; - input [63 : 0] cpu_imem_master_rdata; - input [1 : 0] cpu_imem_master_rresp; - input cpu_imem_master_rlast; - - // value method cpu_imem_master_m_rready - output cpu_imem_master_rready; - - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; - - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; - - // value method cpu_dmem_master_m_awaddr - output [63 : 0] cpu_dmem_master_awaddr; - - // value method cpu_dmem_master_m_awlen - output [7 : 0] cpu_dmem_master_awlen; - - // value method cpu_dmem_master_m_awsize - output [2 : 0] cpu_dmem_master_awsize; - - // value method cpu_dmem_master_m_awburst - output [1 : 0] cpu_dmem_master_awburst; - - // value method cpu_dmem_master_m_awlock - output cpu_dmem_master_awlock; - - // value method cpu_dmem_master_m_awcache - output [3 : 0] cpu_dmem_master_awcache; - - // value method cpu_dmem_master_m_awprot - output [2 : 0] cpu_dmem_master_awprot; - - // value method cpu_dmem_master_m_awqos - output [3 : 0] cpu_dmem_master_awqos; - - // value method cpu_dmem_master_m_awregion - output [3 : 0] cpu_dmem_master_awregion; - - // value method cpu_dmem_master_m_awuser - - // action method cpu_dmem_master_m_awready - input cpu_dmem_master_awready; - - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; - - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - - // value method cpu_dmem_master_m_wdata - output [63 : 0] cpu_dmem_master_wdata; - - // value method cpu_dmem_master_m_wstrb - output [7 : 0] cpu_dmem_master_wstrb; - - // value method cpu_dmem_master_m_wlast - output cpu_dmem_master_wlast; - - // value method cpu_dmem_master_m_wuser - - // action method cpu_dmem_master_m_wready - input cpu_dmem_master_wready; - - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; - input [1 : 0] cpu_dmem_master_bresp; - - // value method cpu_dmem_master_m_bready - output cpu_dmem_master_bready; - - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; - - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; - - // value method cpu_dmem_master_m_araddr - output [63 : 0] cpu_dmem_master_araddr; - - // value method cpu_dmem_master_m_arlen - output [7 : 0] cpu_dmem_master_arlen; - - // value method cpu_dmem_master_m_arsize - output [2 : 0] cpu_dmem_master_arsize; - - // value method cpu_dmem_master_m_arburst - output [1 : 0] cpu_dmem_master_arburst; - - // value method cpu_dmem_master_m_arlock - output cpu_dmem_master_arlock; - - // value method cpu_dmem_master_m_arcache - output [3 : 0] cpu_dmem_master_arcache; - - // value method cpu_dmem_master_m_arprot - output [2 : 0] cpu_dmem_master_arprot; - - // value method cpu_dmem_master_m_arqos - output [3 : 0] cpu_dmem_master_arqos; - - // value method cpu_dmem_master_m_arregion - output [3 : 0] cpu_dmem_master_arregion; - - // value method cpu_dmem_master_m_aruser - - // action method cpu_dmem_master_m_arready - input cpu_dmem_master_arready; - - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; - input [63 : 0] cpu_dmem_master_rdata; - input [1 : 0] cpu_dmem_master_rresp; - input cpu_dmem_master_rlast; - - // value method cpu_dmem_master_m_rready - output cpu_dmem_master_rready; - - // action method core_external_interrupt_sources_0_m_interrupt_req - input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_1_m_interrupt_req - input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_2_m_interrupt_req - input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_3_m_interrupt_req - input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_4_m_interrupt_req - input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_5_m_interrupt_req - input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_6_m_interrupt_req - input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_7_m_interrupt_req - input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_8_m_interrupt_req - input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_9_m_interrupt_req - input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_10_m_interrupt_req - input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_11_m_interrupt_req - input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_12_m_interrupt_req - input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_13_m_interrupt_req - input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_14_m_interrupt_req - input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_15_m_interrupt_req - input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // signals for module outputs - wire [63 : 0] cpu_dmem_master_araddr, - cpu_dmem_master_awaddr, - cpu_dmem_master_wdata, - cpu_imem_master_araddr, - cpu_imem_master_awaddr, - cpu_imem_master_wdata; - wire [7 : 0] cpu_dmem_master_arlen, - cpu_dmem_master_awlen, - cpu_dmem_master_wstrb, - cpu_imem_master_arlen, - cpu_imem_master_awlen, - cpu_imem_master_wstrb; - wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, - cpu_dmem_master_arqos, - cpu_dmem_master_arregion, - cpu_dmem_master_awcache, - cpu_dmem_master_awid, - cpu_dmem_master_awqos, - cpu_dmem_master_awregion, - cpu_dmem_master_wid, - cpu_imem_master_arcache, - cpu_imem_master_arid, - cpu_imem_master_arqos, - cpu_imem_master_arregion, - cpu_imem_master_awcache, - cpu_imem_master_awid, - cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; - wire [2 : 0] cpu_dmem_master_arprot, - cpu_dmem_master_arsize, - cpu_dmem_master_awprot, - cpu_dmem_master_awsize, - cpu_imem_master_arprot, - cpu_imem_master_arsize, - cpu_imem_master_awprot, - cpu_imem_master_awsize; - wire [1 : 0] cpu_dmem_master_arburst, - cpu_dmem_master_awburst, - cpu_imem_master_arburst, - cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_set_verbosity, - cpu_dmem_master_arlock, - cpu_dmem_master_arvalid, - cpu_dmem_master_awlock, - cpu_dmem_master_awvalid, - cpu_dmem_master_bready, - cpu_dmem_master_rready, - cpu_dmem_master_wlast, - cpu_dmem_master_wvalid, - cpu_imem_master_arlock, - cpu_imem_master_arvalid, - cpu_imem_master_awlock, - cpu_imem_master_awvalid, - cpu_imem_master_bready, - cpu_imem_master_rready, - cpu_imem_master_wlast, - cpu_imem_master_wvalid, - cpu_reset_server_response_get; - - // ports of submodule cpu - wire [63 : 0] cpu$dmem_master_araddr, - cpu$dmem_master_awaddr, - cpu$dmem_master_rdata, - cpu$dmem_master_wdata, - cpu$imem_master_araddr, - cpu$imem_master_awaddr, - cpu$imem_master_rdata, - cpu$imem_master_wdata, - cpu$set_verbosity_logdelay; - wire [7 : 0] cpu$dmem_master_arlen, - cpu$dmem_master_awlen, - cpu$dmem_master_wstrb, - cpu$imem_master_arlen, - cpu$imem_master_awlen, - cpu$imem_master_wstrb; - wire [3 : 0] cpu$dmem_master_arcache, - cpu$dmem_master_arid, - cpu$dmem_master_arqos, - cpu$dmem_master_arregion, - cpu$dmem_master_awcache, - cpu$dmem_master_awid, - cpu$dmem_master_awqos, - cpu$dmem_master_awregion, - cpu$dmem_master_bid, - cpu$dmem_master_rid, - cpu$dmem_master_wid, - cpu$imem_master_arcache, - cpu$imem_master_arid, - cpu$imem_master_arqos, - cpu$imem_master_arregion, - cpu$imem_master_awcache, - cpu$imem_master_awid, - cpu$imem_master_awqos, - cpu$imem_master_awregion, - cpu$imem_master_bid, - cpu$imem_master_rid, - cpu$imem_master_wid, - cpu$set_verbosity_verbosity; - wire [2 : 0] cpu$dmem_master_arprot, - cpu$dmem_master_arsize, - cpu$dmem_master_awprot, - cpu$dmem_master_awsize, - cpu$imem_master_arprot, - cpu$imem_master_arsize, - cpu$imem_master_awprot, - cpu$imem_master_awsize; - wire [1 : 0] cpu$dmem_master_arburst, - cpu$dmem_master_awburst, - cpu$dmem_master_bresp, - cpu$dmem_master_rresp, - cpu$imem_master_arburst, - cpu$imem_master_awburst, - cpu$imem_master_bresp, - cpu$imem_master_rresp; - wire cpu$EN_hart0_server_reset_request_put, - cpu$EN_hart0_server_reset_response_get, - cpu$EN_set_verbosity, - cpu$RDY_hart0_server_reset_request_put, - cpu$RDY_hart0_server_reset_response_get, - cpu$dmem_master_arlock, - cpu$dmem_master_arready, - cpu$dmem_master_arvalid, - cpu$dmem_master_awlock, - cpu$dmem_master_awready, - cpu$dmem_master_awvalid, - cpu$dmem_master_bready, - cpu$dmem_master_bvalid, - cpu$dmem_master_rlast, - cpu$dmem_master_rready, - cpu$dmem_master_rvalid, - cpu$dmem_master_wlast, - cpu$dmem_master_wready, - cpu$dmem_master_wvalid, - cpu$hart0_server_reset_request_put, - cpu$hart0_server_reset_response_get, - cpu$imem_master_arlock, - cpu$imem_master_arready, - cpu$imem_master_arvalid, - cpu$imem_master_awlock, - cpu$imem_master_awready, - cpu$imem_master_awvalid, - cpu$imem_master_bready, - cpu$imem_master_bvalid, - cpu$imem_master_rlast, - cpu$imem_master_rready, - cpu$imem_master_rvalid, - cpu$imem_master_wlast, - cpu$imem_master_wready, - cpu$imem_master_wvalid, - cpu$m_external_interrupt_req_set_not_clear, - cpu$nmi_req_set_not_clear, - cpu$s_external_interrupt_req_set_not_clear, - cpu$software_interrupt_req_set_not_clear, - cpu$timer_interrupt_req_set_not_clear; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_araddr, - fabric_2x3$v_to_slaves_2_awaddr, - fabric_2x3$v_to_slaves_2_rdata, - fabric_2x3$v_to_slaves_2_wdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb, - fabric_2x3$v_to_slaves_2_arlen, - fabric_2x3$v_to_slaves_2_awlen, - fabric_2x3$v_to_slaves_2_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_wid, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, - fabric_2x3$v_to_slaves_2_arcache, - fabric_2x3$v_to_slaves_2_arid, - fabric_2x3$v_to_slaves_2_arqos, - fabric_2x3$v_to_slaves_2_arregion, - fabric_2x3$v_to_slaves_2_awcache, - fabric_2x3$v_to_slaves_2_awid, - fabric_2x3$v_to_slaves_2_awqos, - fabric_2x3$v_to_slaves_2_awregion, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize, - fabric_2x3$v_to_slaves_2_arprot, - fabric_2x3$v_to_slaves_2_arsize, - fabric_2x3$v_to_slaves_2_awprot, - fabric_2x3$v_to_slaves_2_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_arburst, - fabric_2x3$v_to_slaves_2_awburst, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arlock, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_arvalid, - fabric_2x3$v_to_slaves_2_awlock, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_awvalid, - fabric_2x3$v_to_slaves_2_bready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rready, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wlast, - fabric_2x3$v_to_slaves_2_wready, - fabric_2x3$v_to_slaves_2_wvalid; - - // ports of submodule near_mem_io - wire [63 : 0] near_mem_io$axi4_slave_araddr, - near_mem_io$axi4_slave_awaddr, - near_mem_io$axi4_slave_rdata, - near_mem_io$axi4_slave_wdata, - near_mem_io$set_addr_map_addr_base, - near_mem_io$set_addr_map_addr_lim; - wire [7 : 0] near_mem_io$axi4_slave_arlen, - near_mem_io$axi4_slave_awlen, - near_mem_io$axi4_slave_wstrb; - wire [3 : 0] near_mem_io$axi4_slave_arcache, - near_mem_io$axi4_slave_arid, - near_mem_io$axi4_slave_arqos, - near_mem_io$axi4_slave_arregion, - near_mem_io$axi4_slave_awcache, - near_mem_io$axi4_slave_awid, - near_mem_io$axi4_slave_awqos, - near_mem_io$axi4_slave_awregion, - near_mem_io$axi4_slave_bid, - near_mem_io$axi4_slave_rid, - near_mem_io$axi4_slave_wid; - wire [2 : 0] near_mem_io$axi4_slave_arprot, - near_mem_io$axi4_slave_arsize, - near_mem_io$axi4_slave_awprot, - near_mem_io$axi4_slave_awsize; - wire [1 : 0] near_mem_io$axi4_slave_arburst, - near_mem_io$axi4_slave_awburst, - near_mem_io$axi4_slave_bresp, - near_mem_io$axi4_slave_rresp; - wire near_mem_io$EN_get_sw_interrupt_req_get, - near_mem_io$EN_get_timer_interrupt_req_get, - near_mem_io$EN_server_reset_request_put, - near_mem_io$EN_server_reset_response_get, - near_mem_io$EN_set_addr_map, - near_mem_io$RDY_get_sw_interrupt_req_get, - near_mem_io$RDY_get_timer_interrupt_req_get, - near_mem_io$RDY_server_reset_request_put, - near_mem_io$RDY_server_reset_response_get, - near_mem_io$axi4_slave_arlock, - near_mem_io$axi4_slave_arready, - near_mem_io$axi4_slave_arvalid, - near_mem_io$axi4_slave_awlock, - near_mem_io$axi4_slave_awready, - near_mem_io$axi4_slave_awvalid, - near_mem_io$axi4_slave_bready, - near_mem_io$axi4_slave_bvalid, - near_mem_io$axi4_slave_rlast, - near_mem_io$axi4_slave_rready, - near_mem_io$axi4_slave_rvalid, - near_mem_io$axi4_slave_wlast, - near_mem_io$axi4_slave_wready, - near_mem_io$axi4_slave_wvalid, - near_mem_io$get_sw_interrupt_req_get, - near_mem_io$get_timer_interrupt_req_get; - - // ports of submodule plic - wire [63 : 0] plic$axi4_slave_araddr, - plic$axi4_slave_awaddr, - plic$axi4_slave_rdata, - plic$axi4_slave_wdata, - plic$set_addr_map_addr_base, - plic$set_addr_map_addr_lim; - wire [7 : 0] plic$axi4_slave_arlen, - plic$axi4_slave_awlen, - plic$axi4_slave_wstrb; - wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, - plic$axi4_slave_arqos, - plic$axi4_slave_arregion, - plic$axi4_slave_awcache, - plic$axi4_slave_awid, - plic$axi4_slave_awqos, - plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, - plic$axi4_slave_wid, - plic$set_verbosity_verbosity; - wire [2 : 0] plic$axi4_slave_arprot, - plic$axi4_slave_arsize, - plic$axi4_slave_awprot, - plic$axi4_slave_awsize; - wire [1 : 0] plic$axi4_slave_arburst, - plic$axi4_slave_awburst, - plic$axi4_slave_bresp, - plic$axi4_slave_rresp; - wire plic$EN_server_reset_request_put, - plic$EN_server_reset_response_get, - plic$EN_set_addr_map, - plic$EN_set_verbosity, - plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, - plic$axi4_slave_arlock, - plic$axi4_slave_arready, - plic$axi4_slave_arvalid, - plic$axi4_slave_awlock, - plic$axi4_slave_awready, - plic$axi4_slave_awvalid, - plic$axi4_slave_bready, - plic$axi4_slave_bvalid, - plic$axi4_slave_rlast, - plic$axi4_slave_rready, - plic$axi4_slave_rvalid, - plic$axi4_slave_wlast, - plic$axi4_slave_wready, - plic$axi4_slave_wvalid, - plic$v_sources_0_m_interrupt_req_set_not_clear, - plic$v_sources_10_m_interrupt_req_set_not_clear, - plic$v_sources_11_m_interrupt_req_set_not_clear, - plic$v_sources_12_m_interrupt_req_set_not_clear, - plic$v_sources_13_m_interrupt_req_set_not_clear, - plic$v_sources_14_m_interrupt_req_set_not_clear, - plic$v_sources_15_m_interrupt_req_set_not_clear, - plic$v_sources_1_m_interrupt_req_set_not_clear, - plic$v_sources_2_m_interrupt_req_set_not_clear, - plic$v_sources_3_m_interrupt_req_set_not_clear, - plic$v_sources_4_m_interrupt_req_set_not_clear, - plic$v_sources_5_m_interrupt_req_set_not_clear, - plic$v_sources_6_m_interrupt_req_set_not_clear, - plic$v_sources_7_m_interrupt_req_set_not_clear, - plic$v_sources_8_m_interrupt_req_set_not_clear, - plic$v_sources_9_m_interrupt_req_set_not_clear, - plic$v_targets_0_m_eip, - plic$v_targets_1_m_eip; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_sw_interrupts, - CAN_FIRE_RL_rl_relay_timer_interrupts, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_nmi_req, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_sw_interrupts, - WILL_FIRE_RL_rl_relay_timer_interrupts, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_nmi_req, - WILL_FIRE_set_verbosity; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4310; - reg [31 : 0] v__h4551; - reg [31 : 0] v__h4304; - reg [31 : 0] v__h4545; - // synopsys translate_on - - // remaining internal signals - wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // actionvalue method cpu_reset_server_response_get - assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ; - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; - - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - - // value method cpu_imem_master_m_awid - assign cpu_imem_master_awid = cpu$imem_master_awid ; - - // value method cpu_imem_master_m_awaddr - assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; - - // value method cpu_imem_master_m_awlen - assign cpu_imem_master_awlen = cpu$imem_master_awlen ; - - // value method cpu_imem_master_m_awsize - assign cpu_imem_master_awsize = cpu$imem_master_awsize ; - - // value method cpu_imem_master_m_awburst - assign cpu_imem_master_awburst = cpu$imem_master_awburst ; - - // value method cpu_imem_master_m_awlock - assign cpu_imem_master_awlock = cpu$imem_master_awlock ; - - // value method cpu_imem_master_m_awcache - assign cpu_imem_master_awcache = cpu$imem_master_awcache ; - - // value method cpu_imem_master_m_awprot - assign cpu_imem_master_awprot = cpu$imem_master_awprot ; - - // value method cpu_imem_master_m_awqos - assign cpu_imem_master_awqos = cpu$imem_master_awqos ; - - // value method cpu_imem_master_m_awregion - assign cpu_imem_master_awregion = cpu$imem_master_awregion ; - - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; - - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; - - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = cpu$imem_master_wid ; - - // value method cpu_imem_master_m_wdata - assign cpu_imem_master_wdata = cpu$imem_master_wdata ; - - // value method cpu_imem_master_m_wstrb - assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; - - // value method cpu_imem_master_m_wlast - assign cpu_imem_master_wlast = cpu$imem_master_wlast ; - - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; - - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = cpu$imem_master_bready ; - - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; - - // value method cpu_imem_master_m_arid - assign cpu_imem_master_arid = cpu$imem_master_arid ; - - // value method cpu_imem_master_m_araddr - assign cpu_imem_master_araddr = cpu$imem_master_araddr ; - - // value method cpu_imem_master_m_arlen - assign cpu_imem_master_arlen = cpu$imem_master_arlen ; - - // value method cpu_imem_master_m_arsize - assign cpu_imem_master_arsize = cpu$imem_master_arsize ; - - // value method cpu_imem_master_m_arburst - assign cpu_imem_master_arburst = cpu$imem_master_arburst ; - - // value method cpu_imem_master_m_arlock - assign cpu_imem_master_arlock = cpu$imem_master_arlock ; - - // value method cpu_imem_master_m_arcache - assign cpu_imem_master_arcache = cpu$imem_master_arcache ; - - // value method cpu_imem_master_m_arprot - assign cpu_imem_master_arprot = cpu$imem_master_arprot ; - - // value method cpu_imem_master_m_arqos - assign cpu_imem_master_arqos = cpu$imem_master_arqos ; - - // value method cpu_imem_master_m_arregion - assign cpu_imem_master_arregion = cpu$imem_master_arregion ; - - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; - - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - - // value method cpu_imem_master_m_rready - assign cpu_imem_master_rready = cpu$imem_master_rready ; - - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; - - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; - - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; - - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; - - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; - - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; - - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; - - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; - - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; - - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; - - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; - - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; - - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; - - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; - - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; - - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; - - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; - - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; - - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; - - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; - - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; - - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; - - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; - - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; - - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; - - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; - - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; - - // action method core_external_interrupt_sources_0_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_1_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_2_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_3_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_4_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_5_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_6_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_7_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_8_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_9_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_10_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_11_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_12_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_13_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_14_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_15_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // submodule cpu - mkCPU cpu(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(cpu$dmem_master_arready), - .dmem_master_awready(cpu$dmem_master_awready), - .dmem_master_bid(cpu$dmem_master_bid), - .dmem_master_bresp(cpu$dmem_master_bresp), - .dmem_master_bvalid(cpu$dmem_master_bvalid), - .dmem_master_rdata(cpu$dmem_master_rdata), - .dmem_master_rid(cpu$dmem_master_rid), - .dmem_master_rlast(cpu$dmem_master_rlast), - .dmem_master_rresp(cpu$dmem_master_rresp), - .dmem_master_rvalid(cpu$dmem_master_rvalid), - .dmem_master_wready(cpu$dmem_master_wready), - .hart0_server_reset_request_put(cpu$hart0_server_reset_request_put), - .imem_master_arready(cpu$imem_master_arready), - .imem_master_awready(cpu$imem_master_awready), - .imem_master_bid(cpu$imem_master_bid), - .imem_master_bresp(cpu$imem_master_bresp), - .imem_master_bvalid(cpu$imem_master_bvalid), - .imem_master_rdata(cpu$imem_master_rdata), - .imem_master_rid(cpu$imem_master_rid), - .imem_master_rlast(cpu$imem_master_rlast), - .imem_master_rresp(cpu$imem_master_rresp), - .imem_master_rvalid(cpu$imem_master_rvalid), - .imem_master_wready(cpu$imem_master_wready), - .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), - .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), - .s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear), - .set_verbosity_logdelay(cpu$set_verbosity_logdelay), - .set_verbosity_verbosity(cpu$set_verbosity_verbosity), - .software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), - .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), - .EN_set_verbosity(cpu$EN_set_verbosity), - .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), - .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), - .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), - .imem_master_awvalid(cpu$imem_master_awvalid), - .imem_master_awid(cpu$imem_master_awid), - .imem_master_awaddr(cpu$imem_master_awaddr), - .imem_master_awlen(cpu$imem_master_awlen), - .imem_master_awsize(cpu$imem_master_awsize), - .imem_master_awburst(cpu$imem_master_awburst), - .imem_master_awlock(cpu$imem_master_awlock), - .imem_master_awcache(cpu$imem_master_awcache), - .imem_master_awprot(cpu$imem_master_awprot), - .imem_master_awqos(cpu$imem_master_awqos), - .imem_master_awregion(cpu$imem_master_awregion), - .imem_master_wvalid(cpu$imem_master_wvalid), - .imem_master_wid(cpu$imem_master_wid), - .imem_master_wdata(cpu$imem_master_wdata), - .imem_master_wstrb(cpu$imem_master_wstrb), - .imem_master_wlast(cpu$imem_master_wlast), - .imem_master_bready(cpu$imem_master_bready), - .imem_master_arvalid(cpu$imem_master_arvalid), - .imem_master_arid(cpu$imem_master_arid), - .imem_master_araddr(cpu$imem_master_araddr), - .imem_master_arlen(cpu$imem_master_arlen), - .imem_master_arsize(cpu$imem_master_arsize), - .imem_master_arburst(cpu$imem_master_arburst), - .imem_master_arlock(cpu$imem_master_arlock), - .imem_master_arcache(cpu$imem_master_arcache), - .imem_master_arprot(cpu$imem_master_arprot), - .imem_master_arqos(cpu$imem_master_arqos), - .imem_master_arregion(cpu$imem_master_arregion), - .imem_master_rready(cpu$imem_master_rready), - .dmem_master_awvalid(cpu$dmem_master_awvalid), - .dmem_master_awid(cpu$dmem_master_awid), - .dmem_master_awaddr(cpu$dmem_master_awaddr), - .dmem_master_awlen(cpu$dmem_master_awlen), - .dmem_master_awsize(cpu$dmem_master_awsize), - .dmem_master_awburst(cpu$dmem_master_awburst), - .dmem_master_awlock(cpu$dmem_master_awlock), - .dmem_master_awcache(cpu$dmem_master_awcache), - .dmem_master_awprot(cpu$dmem_master_awprot), - .dmem_master_awqos(cpu$dmem_master_awqos), - .dmem_master_awregion(cpu$dmem_master_awregion), - .dmem_master_wvalid(cpu$dmem_master_wvalid), - .dmem_master_wid(cpu$dmem_master_wid), - .dmem_master_wdata(cpu$dmem_master_wdata), - .dmem_master_wstrb(cpu$dmem_master_wstrb), - .dmem_master_wlast(cpu$dmem_master_wlast), - .dmem_master_bready(cpu$dmem_master_bready), - .dmem_master_arvalid(cpu$dmem_master_arvalid), - .dmem_master_arid(cpu$dmem_master_arid), - .dmem_master_araddr(cpu$dmem_master_araddr), - .dmem_master_arlen(cpu$dmem_master_arlen), - .dmem_master_arsize(cpu$dmem_master_arsize), - .dmem_master_arburst(cpu$dmem_master_arburst), - .dmem_master_arlock(cpu$dmem_master_arlock), - .dmem_master_arcache(cpu$dmem_master_arcache), - .dmem_master_arprot(cpu$dmem_master_arprot), - .dmem_master_arqos(cpu$dmem_master_arqos), - .dmem_master_arregion(cpu$dmem_master_arregion), - .dmem_master_rready(cpu$dmem_master_rready), - .RDY_set_verbosity()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(), - .v_from_masters_1_wready(), - .v_from_masters_1_bvalid(), - .v_from_masters_1_bid(), - .v_from_masters_1_bresp(), - .v_from_masters_1_arready(), - .v_from_masters_1_rvalid(), - .v_from_masters_1_rid(), - .v_from_masters_1_rdata(), - .v_from_masters_1_rresp(), - .v_from_masters_1_rlast(), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); - - // submodule near_mem_io - mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(near_mem_io$axi4_slave_araddr), - .axi4_slave_arburst(near_mem_io$axi4_slave_arburst), - .axi4_slave_arcache(near_mem_io$axi4_slave_arcache), - .axi4_slave_arid(near_mem_io$axi4_slave_arid), - .axi4_slave_arlen(near_mem_io$axi4_slave_arlen), - .axi4_slave_arlock(near_mem_io$axi4_slave_arlock), - .axi4_slave_arprot(near_mem_io$axi4_slave_arprot), - .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), - .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), - .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), - .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), - .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), - .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), - .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), - .axi4_slave_awid(near_mem_io$axi4_slave_awid), - .axi4_slave_awlen(near_mem_io$axi4_slave_awlen), - .axi4_slave_awlock(near_mem_io$axi4_slave_awlock), - .axi4_slave_awprot(near_mem_io$axi4_slave_awprot), - .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), - .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), - .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), - .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), - .axi4_slave_bready(near_mem_io$axi4_slave_bready), - .axi4_slave_rready(near_mem_io$axi4_slave_rready), - .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), - .axi4_slave_wid(near_mem_io$axi4_slave_wid), - .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), - .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), - .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), - .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), - .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), - .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), - .EN_set_addr_map(near_mem_io$EN_set_addr_map), - .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), - .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), - .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(near_mem_io$axi4_slave_awready), - .axi4_slave_wready(near_mem_io$axi4_slave_wready), - .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), - .axi4_slave_bid(near_mem_io$axi4_slave_bid), - .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), - .axi4_slave_arready(near_mem_io$axi4_slave_arready), - .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), - .axi4_slave_rid(near_mem_io$axi4_slave_rid), - .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), - .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), - .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), - .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), - .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), - .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), - .RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get)); - - // submodule plic - mkPLIC_16_2_7 plic(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(plic$axi4_slave_araddr), - .axi4_slave_arburst(plic$axi4_slave_arburst), - .axi4_slave_arcache(plic$axi4_slave_arcache), - .axi4_slave_arid(plic$axi4_slave_arid), - .axi4_slave_arlen(plic$axi4_slave_arlen), - .axi4_slave_arlock(plic$axi4_slave_arlock), - .axi4_slave_arprot(plic$axi4_slave_arprot), - .axi4_slave_arqos(plic$axi4_slave_arqos), - .axi4_slave_arregion(plic$axi4_slave_arregion), - .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), - .axi4_slave_awaddr(plic$axi4_slave_awaddr), - .axi4_slave_awburst(plic$axi4_slave_awburst), - .axi4_slave_awcache(plic$axi4_slave_awcache), - .axi4_slave_awid(plic$axi4_slave_awid), - .axi4_slave_awlen(plic$axi4_slave_awlen), - .axi4_slave_awlock(plic$axi4_slave_awlock), - .axi4_slave_awprot(plic$axi4_slave_awprot), - .axi4_slave_awqos(plic$axi4_slave_awqos), - .axi4_slave_awregion(plic$axi4_slave_awregion), - .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_bready(plic$axi4_slave_bready), - .axi4_slave_rready(plic$axi4_slave_rready), - .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), - .axi4_slave_wlast(plic$axi4_slave_wlast), - .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .set_addr_map_addr_base(plic$set_addr_map_addr_base), - .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), - .set_verbosity_verbosity(plic$set_verbosity_verbosity), - .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), - .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), - .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), - .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), - .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), - .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), - .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), - .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), - .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), - .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), - .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), - .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), - .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), - .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), - .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), - .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), - .EN_set_verbosity(plic$EN_set_verbosity), - .EN_show_PLIC_state(plic$EN_show_PLIC_state), - .EN_server_reset_request_put(plic$EN_server_reset_request_put), - .EN_server_reset_response_get(plic$EN_server_reset_response_get), - .EN_set_addr_map(plic$EN_set_addr_map), - .RDY_set_verbosity(), - .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(plic$axi4_slave_awready), - .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), - .axi4_slave_bid(plic$axi4_slave_bid), - .axi4_slave_bresp(plic$axi4_slave_bresp), - .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), - .axi4_slave_rid(plic$axi4_slave_rid), - .axi4_slave_rdata(plic$axi4_slave_rdata), - .axi4_slave_rresp(plic$axi4_slave_rresp), - .axi4_slave_rlast(plic$axi4_slave_rlast), - .v_targets_0_m_eip(plic$v_targets_0_m_eip), - .v_targets_1_m_eip(plic$v_targets_1_m_eip)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_relay_sw_interrupts - assign CAN_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // rule RL_rl_relay_timer_interrupts - assign CAN_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - - // rule RL_rl_relay_external_interrupts - assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule cpu - assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; - assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; - assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; - assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; - assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; - assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ; - assign cpu$imem_master_arready = cpu_imem_master_arready ; - assign cpu$imem_master_awready = cpu_imem_master_awready ; - assign cpu$imem_master_bid = cpu_imem_master_bid ; - assign cpu$imem_master_bresp = cpu_imem_master_bresp ; - assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; - assign cpu$imem_master_rdata = cpu_imem_master_rdata ; - assign cpu$imem_master_rid = cpu_imem_master_rid ; - assign cpu$imem_master_rlast = cpu_imem_master_rlast ; - assign cpu$imem_master_rresp = cpu_imem_master_rresp ; - assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; - assign cpu$imem_master_wready = cpu_imem_master_wready ; - assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; - assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; - assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; - assign cpu$software_interrupt_req_set_not_clear = - near_mem_io$get_sw_interrupt_req_get ; - assign cpu$timer_interrupt_req_set_not_clear = - near_mem_io$get_timer_interrupt_req_get ; - assign cpu$EN_hart0_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign cpu$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign cpu$EN_set_verbosity = EN_set_verbosity ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = cpu_reset_server_request_put ; - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ; - assign f_reset_rsps$ENQ = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; - assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; - assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; - assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; - assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; - assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; - assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; - assign fabric_2x3$v_from_masters_0_wid = cpu$dmem_master_wid ; - assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_awaddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_bready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_wdata = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wstrb = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; - assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; - - // submodule near_mem_io - assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign near_mem_io$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; - assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; - assign near_mem_io$set_addr_map_addr_base = - soc_map$m_near_mem_io_addr_base ; - assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; - assign near_mem_io$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign near_mem_io$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_set_addr_map = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_get_timer_interrupt_req_get = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign near_mem_io$EN_get_sw_interrupt_req_get = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_2_wid ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; - assign plic$set_verbosity_verbosity = 4'h0 ; - assign plic$v_sources_0_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; - assign plic$v_sources_10_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; - assign plic$v_sources_11_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; - assign plic$v_sources_12_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; - assign plic$v_sources_13_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; - assign plic$v_sources_14_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; - assign plic$v_sources_15_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; - assign plic$v_sources_1_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; - assign plic$v_sources_2_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; - assign plic$v_sources_3_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; - assign plic$v_sources_4_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; - assign plic$v_sources_5_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; - assign plic$v_sources_6_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; - assign plic$v_sources_7_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; - assign plic$v_sources_8_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; - assign plic$v_sources_9_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; - assign plic$EN_set_verbosity = 1'b0 ; - assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - cpu$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h4310 = $stime; - #0; - end - v__h4304 = v__h4310 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4304); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h4551 = $stime; - #0; - end - v__h4545 = v__h4551 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4545); - end - // synopsys translate_on -endmodule // mkCore - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Core.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Core.v deleted file mode 100644 index 127765e3..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Core.v +++ /dev/null @@ -1,12093 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// valid O 1 -// word_fst O 64 -// word_snd O 5 -// CLK I 1 clock -// RST_N I 1 reset -// req_opcode I 7 -// req_f7 I 7 -// req_rm I 3 -// req_rs2 I 5 -// req_v1 I 64 -// req_v2 I 64 -// req_v3 I 64 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFBox_Core(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_opcode, - req_f7, - req_rm, - req_rs2, - req_v1, - req_v2, - req_v3, - EN_req, - - valid, - - word_fst, - - word_snd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [6 : 0] req_opcode; - input [6 : 0] req_f7; - input [2 : 0] req_rm; - input [4 : 0] req_rs2; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input [63 : 0] req_v3; - input EN_req; - - // value method valid - output valid; - - // value method word_fst - output [63 : 0] word_fst; - - // value method word_snd - output [4 : 0] word_snd; - - // signals for module outputs - wire [63 : 0] word_fst; - wire [4 : 0] word_snd; - wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid; - - // inlined wires - wire [68 : 0] dw_result$wget; - wire dw_valid$wget, dw_valid$whas; - - // register requestR - reg [214 : 0] requestR; - wire [214 : 0] requestR$D_IN; - wire requestR$EN; - - // register resultR - reg [69 : 0] resultR; - reg [69 : 0] resultR$D_IN; - wire resultR$EN; - - // register stateR - reg [1 : 0] stateR; - reg [1 : 0] stateR$D_IN; - wire stateR$EN; - - // ports of submodule fpu - reg [201 : 0] fpu$server_core_request_put; - wire [69 : 0] fpu$server_core_response_get; - wire fpu$EN_server_core_request_put, - fpu$EN_server_core_response_get, - fpu$EN_server_reset_request_put, - fpu$EN_server_reset_response_get, - fpu$RDY_server_core_request_put, - fpu$RDY_server_core_response_get, - fpu$RDY_server_reset_request_put, - fpu$RDY_server_reset_response_get; - - // ports of submodule frmFpuF - wire frmFpuF$CLR, frmFpuF$DEQ, frmFpuF$D_IN, frmFpuF$ENQ; - - // ports of submodule resetReqsF - wire resetReqsF$CLR, - resetReqsF$DEQ, - resetReqsF$EMPTY_N, - resetReqsF$ENQ, - resetReqsF$FULL_N; - - // ports of submodule resetRspsF - wire resetRspsF$CLR, - resetRspsF$DEQ, - resetRspsF$EMPTY_N, - resetRspsF$ENQ, - resetRspsF$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_doFADD_D, - CAN_FIRE_RL_doFADD_S, - CAN_FIRE_RL_doFCLASS_D, - CAN_FIRE_RL_doFCLASS_S, - CAN_FIRE_RL_doFCVT_D_L, - CAN_FIRE_RL_doFCVT_D_LU, - CAN_FIRE_RL_doFCVT_D_S, - CAN_FIRE_RL_doFCVT_D_W, - CAN_FIRE_RL_doFCVT_D_WU, - CAN_FIRE_RL_doFCVT_LU_D, - CAN_FIRE_RL_doFCVT_LU_S, - CAN_FIRE_RL_doFCVT_L_D, - CAN_FIRE_RL_doFCVT_L_S, - CAN_FIRE_RL_doFCVT_S_D, - CAN_FIRE_RL_doFCVT_S_L, - CAN_FIRE_RL_doFCVT_S_LU, - CAN_FIRE_RL_doFCVT_S_W, - CAN_FIRE_RL_doFCVT_S_WU, - CAN_FIRE_RL_doFCVT_WU_D, - CAN_FIRE_RL_doFCVT_WU_S, - CAN_FIRE_RL_doFCVT_W_D, - CAN_FIRE_RL_doFCVT_W_S, - CAN_FIRE_RL_doFDIV_D, - CAN_FIRE_RL_doFDIV_S, - CAN_FIRE_RL_doFEQ_D, - CAN_FIRE_RL_doFEQ_S, - CAN_FIRE_RL_doFLE_D, - CAN_FIRE_RL_doFLE_S, - CAN_FIRE_RL_doFLT_D, - CAN_FIRE_RL_doFLT_S, - CAN_FIRE_RL_doFMADD_D, - CAN_FIRE_RL_doFMADD_S, - CAN_FIRE_RL_doFMAX_D, - CAN_FIRE_RL_doFMAX_S, - CAN_FIRE_RL_doFMIN_D, - CAN_FIRE_RL_doFMIN_S, - CAN_FIRE_RL_doFMSUB_D, - CAN_FIRE_RL_doFMSUB_S, - CAN_FIRE_RL_doFMUL_D, - CAN_FIRE_RL_doFMUL_S, - CAN_FIRE_RL_doFMV_D_X, - CAN_FIRE_RL_doFMV_W_X, - CAN_FIRE_RL_doFMV_X_D, - CAN_FIRE_RL_doFMV_X_W, - CAN_FIRE_RL_doFNMADD_D, - CAN_FIRE_RL_doFNMADD_S, - CAN_FIRE_RL_doFNMSUB_D, - CAN_FIRE_RL_doFNMSUB_S, - CAN_FIRE_RL_doFSGNJN_D, - CAN_FIRE_RL_doFSGNJN_S, - CAN_FIRE_RL_doFSGNJX_D, - CAN_FIRE_RL_doFSGNJX_S, - CAN_FIRE_RL_doFSGNJ_D, - CAN_FIRE_RL_doFSGNJ_S, - CAN_FIRE_RL_doFSQRT_D, - CAN_FIRE_RL_doFSQRT_S, - CAN_FIRE_RL_doFSUB_D, - CAN_FIRE_RL_doFSUB_S, - CAN_FIRE_RL_rl_drive_fpu_result, - CAN_FIRE_RL_rl_get_fpu_result, - CAN_FIRE_RL_rl_reset_begin, - CAN_FIRE_RL_rl_reset_end, - CAN_FIRE_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_RL_doFADD_D, - WILL_FIRE_RL_doFADD_S, - WILL_FIRE_RL_doFCLASS_D, - WILL_FIRE_RL_doFCLASS_S, - WILL_FIRE_RL_doFCVT_D_L, - WILL_FIRE_RL_doFCVT_D_LU, - WILL_FIRE_RL_doFCVT_D_S, - WILL_FIRE_RL_doFCVT_D_W, - WILL_FIRE_RL_doFCVT_D_WU, - WILL_FIRE_RL_doFCVT_LU_D, - WILL_FIRE_RL_doFCVT_LU_S, - WILL_FIRE_RL_doFCVT_L_D, - WILL_FIRE_RL_doFCVT_L_S, - WILL_FIRE_RL_doFCVT_S_D, - WILL_FIRE_RL_doFCVT_S_L, - WILL_FIRE_RL_doFCVT_S_LU, - WILL_FIRE_RL_doFCVT_S_W, - WILL_FIRE_RL_doFCVT_S_WU, - WILL_FIRE_RL_doFCVT_WU_D, - WILL_FIRE_RL_doFCVT_WU_S, - WILL_FIRE_RL_doFCVT_W_D, - WILL_FIRE_RL_doFCVT_W_S, - WILL_FIRE_RL_doFDIV_D, - WILL_FIRE_RL_doFDIV_S, - WILL_FIRE_RL_doFEQ_D, - WILL_FIRE_RL_doFEQ_S, - WILL_FIRE_RL_doFLE_D, - WILL_FIRE_RL_doFLE_S, - WILL_FIRE_RL_doFLT_D, - WILL_FIRE_RL_doFLT_S, - WILL_FIRE_RL_doFMADD_D, - WILL_FIRE_RL_doFMADD_S, - WILL_FIRE_RL_doFMAX_D, - WILL_FIRE_RL_doFMAX_S, - WILL_FIRE_RL_doFMIN_D, - WILL_FIRE_RL_doFMIN_S, - WILL_FIRE_RL_doFMSUB_D, - WILL_FIRE_RL_doFMSUB_S, - WILL_FIRE_RL_doFMUL_D, - WILL_FIRE_RL_doFMUL_S, - WILL_FIRE_RL_doFMV_D_X, - WILL_FIRE_RL_doFMV_W_X, - WILL_FIRE_RL_doFMV_X_D, - WILL_FIRE_RL_doFMV_X_W, - WILL_FIRE_RL_doFNMADD_D, - WILL_FIRE_RL_doFNMADD_S, - WILL_FIRE_RL_doFNMSUB_D, - WILL_FIRE_RL_doFNMSUB_S, - WILL_FIRE_RL_doFSGNJN_D, - WILL_FIRE_RL_doFSGNJN_S, - WILL_FIRE_RL_doFSGNJX_D, - WILL_FIRE_RL_doFSGNJX_S, - WILL_FIRE_RL_doFSGNJ_D, - WILL_FIRE_RL_doFSGNJ_S, - WILL_FIRE_RL_doFSQRT_D, - WILL_FIRE_RL_doFSQRT_S, - WILL_FIRE_RL_doFSUB_D, - WILL_FIRE_RL_doFSUB_S, - WILL_FIRE_RL_rl_drive_fpu_result, - WILL_FIRE_RL_rl_get_fpu_result, - WILL_FIRE_RL_rl_reset_begin, - WILL_FIRE_RL_rl_reset_end, - WILL_FIRE_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // inputs to muxes for submodule ports - wire [214 : 0] MUX_requestR$write_1__VAL_2; - wire [201 : 0] MUX_fpu$server_core_request_put_1__VAL_1, - MUX_fpu$server_core_request_put_1__VAL_10, - MUX_fpu$server_core_request_put_1__VAL_11, - MUX_fpu$server_core_request_put_1__VAL_12, - MUX_fpu$server_core_request_put_1__VAL_13, - MUX_fpu$server_core_request_put_1__VAL_14, - MUX_fpu$server_core_request_put_1__VAL_15, - MUX_fpu$server_core_request_put_1__VAL_16, - MUX_fpu$server_core_request_put_1__VAL_17, - MUX_fpu$server_core_request_put_1__VAL_18, - MUX_fpu$server_core_request_put_1__VAL_2, - MUX_fpu$server_core_request_put_1__VAL_3, - MUX_fpu$server_core_request_put_1__VAL_4, - MUX_fpu$server_core_request_put_1__VAL_5, - MUX_fpu$server_core_request_put_1__VAL_6, - MUX_fpu$server_core_request_put_1__VAL_7, - MUX_fpu$server_core_request_put_1__VAL_8, - MUX_fpu$server_core_request_put_1__VAL_9; - wire [69 : 0] MUX_resultR$write_1__VAL_10, - MUX_resultR$write_1__VAL_11, - MUX_resultR$write_1__VAL_12, - MUX_resultR$write_1__VAL_13, - MUX_resultR$write_1__VAL_14, - MUX_resultR$write_1__VAL_15, - MUX_resultR$write_1__VAL_16, - MUX_resultR$write_1__VAL_17, - MUX_resultR$write_1__VAL_18, - MUX_resultR$write_1__VAL_19, - MUX_resultR$write_1__VAL_20, - MUX_resultR$write_1__VAL_21, - MUX_resultR$write_1__VAL_22, - MUX_resultR$write_1__VAL_23, - MUX_resultR$write_1__VAL_24, - MUX_resultR$write_1__VAL_25, - MUX_resultR$write_1__VAL_26, - MUX_resultR$write_1__VAL_27, - MUX_resultR$write_1__VAL_28, - MUX_resultR$write_1__VAL_29, - MUX_resultR$write_1__VAL_3, - MUX_resultR$write_1__VAL_30, - MUX_resultR$write_1__VAL_31, - MUX_resultR$write_1__VAL_32, - MUX_resultR$write_1__VAL_33, - MUX_resultR$write_1__VAL_34, - MUX_resultR$write_1__VAL_35, - MUX_resultR$write_1__VAL_36, - MUX_resultR$write_1__VAL_37, - MUX_resultR$write_1__VAL_38, - MUX_resultR$write_1__VAL_39, - MUX_resultR$write_1__VAL_4, - MUX_resultR$write_1__VAL_40, - MUX_resultR$write_1__VAL_41, - MUX_resultR$write_1__VAL_42, - MUX_resultR$write_1__VAL_43, - MUX_resultR$write_1__VAL_5, - MUX_resultR$write_1__VAL_7, - MUX_resultR$write_1__VAL_8, - MUX_resultR$write_1__VAL_9; - wire [68 : 0] MUX_dw_result$wset_1__VAL_1; - wire MUX_dw_result$wset_1__SEL_1; - - // remaining internal signals - reg [51 : 0] CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q88, - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q89, - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q75, - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q76, - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q104, - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q105, - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q100, - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q101, - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q110, - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q111, - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q108, - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q109, - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q168, - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q169, - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q170, - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q171, - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q172, - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q173, - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q90, - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q91, - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q79, - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q80, - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030; - reg [22 : 0] CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q132, - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q133, - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q134, - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q135, - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q18, - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q19, - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q20, - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q21, - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q36, - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q37, - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q136, - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q137, - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q34, - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q35, - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q138, - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q139, - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q61, - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q62, - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q59, - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q60, - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q48, - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q49, - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q50, - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q51, - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569; - reg [10 : 0] CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_theR_ETC__q86, - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_x019_ETC__q87, - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_theR_ETC__q73, - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_x055_ETC__q74, - CASE_guard3135_0b0_0_0b1_0_0b10_out_exp3754_0b_ETC__q103, - CASE_guard3135_0b0_0_0b1_theResult___exp3751_0_ETC__q102, - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_theR_ETC__q98, - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_x388_ETC__q99, - CASE_guard4092_0b0_0_0b1_0_0b10_out_exp4711_0b_ETC__q29, - CASE_guard4092_0b0_0_0b1_theResult___exp4708_0_ETC__q30, - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_theR_ETC__q106, - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_x483_ETC__q107, - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q156, - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q157, - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q158, - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q159, - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q160, - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q161, - CASE_guard9455_0b0_0_0b1_0_0b10_out_exp0074_0b_ETC__q83, - CASE_guard9455_0b0_0_0b1_theResult___exp0071_0_ETC__q84, - CASE_guard9814_0b0_0_0b1_0_0b10_out_exp0433_0b_ETC__q78, - CASE_guard9814_0b0_0_0b1_theResult___exp0430_0_ETC__q77, - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard4092_ETC__q31, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard9455_ETC__q85, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951; - reg [7 : 0] CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q124, - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q125, - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q128, - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q129, - CASE_guard2228_0b0_0_0b1_0_0b10_out_exp2647_0b_ETC__q15, - CASE_guard2228_0b0_0_0b1_theResult___exp2644_0_ETC__q14, - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_theRe_ETC__q16, - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_x2773_ETC__q17, - CASE_guard2795_0b0_0_0b1_0_0b10_out_exp3211_0b_ETC__q26, - CASE_guard2795_0b0_0_0b1_theResult___exp3208_0_ETC__q27, - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q126, - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q127, - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_theRe_ETC__q32, - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_x3336_ETC__q33, - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q130, - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q131, - CASE_guard5283_0b0_0_0b1_0_0b10_out_exp5699_0b_ETC__q54, - CASE_guard5283_0b0_0_0b1_theResult___exp5696_0_ETC__q55, - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_theRe_ETC__q57, - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_x5824_ETC__q58, - CASE_guard9167_0b0_0_0b1_0_0b10_out_exp9583_0b_ETC__q45, - CASE_guard9167_0b0_0_0b1_theResult___exp9580_0_ETC__q44, - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_theRe_ETC__q46, - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_x9709_ETC__q47, - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard2795_ETC__q28, - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5283_ETC__q56, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528; - reg [2 : 0] IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50; - reg CASE_guard0544_0b0_requestR_BIT_159_0b1_reques_ETC__q71, - CASE_guard10454_0b0_requestR_BIT_191_0b1_reque_ETC__q140, - CASE_guard19189_0b0_requestR_BIT_191_0b1_reque_ETC__q142, - CASE_guard2228_0b0_requestR_BIT_191_0b1_reques_ETC__q10, - CASE_guard2758_0b0_requestR_BIT_191_0b1_reques_ETC__q12, - CASE_guard28178_0b0_requestR_BIT_191_0b1_reque_ETC__q144, - CASE_guard3135_0b0_requestR_BIT_191_0b1_reques_ETC__q94, - CASE_guard37042_0b0_requestR_BIT_191_0b1_reque_ETC__q146, - CASE_guard3865_0b0_requestR_BIT_191_0b1_reques_ETC__q96, - CASE_guard60150_0b0_requestR_BITS_191_TO_160_E_ETC__q162, - CASE_guard69458_0b0_requestR_BITS_191_TO_160_E_ETC__q164, - CASE_guard78525_0b0_requestR_BITS_191_TO_160_E_ETC__q166, - CASE_guard9167_0b0_requestR_BIT_159_0b1_reques_ETC__q40, - CASE_guard9694_0b0_requestR_BIT_159_0b1_reques_ETC__q42, - CASE_guard9814_0b0_requestR_BIT_159_0b1_reques_ETC__q69, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q13, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q141, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q143, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q145, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q147, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q163, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q165, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q167, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q41, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q43, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q70, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q72, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q95, - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q97; - wire [117 : 0] IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114, - b__h96173, - x__h97073, - x__h98317; - wire [88 : 0] IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705, - b__h36962, - x__h37862, - x__h39123; - wire [85 : 0] IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629, - b__h71539, - x__h72215, - x__h73238; - wire [64 : 0] _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - _theResult_____2__h36897, - _theResult_____2__h96108, - out1___1__h37613, - out1___1__h96824; - wire [63 : 0] IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2052, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2067, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1764, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1822, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2051, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2053, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2066, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2068, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2132, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2133, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1760, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1762, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1820, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3169, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3171, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3223, - IF_requestR_3_BITS_126_TO_116_167_EQ_2047_168__ETC___d5215, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d3225, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5228, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5294, - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d3173, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1693, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1824, - IF_requestR_3_BIT_191_47_THEN_9223372036854775_ETC___d3110, - res___1__h204227, - res___1__h204665, - res___1__h204675, - res___1__h204694, - res___1__h50292, - res___1__h50528, - res___1__h50538, - res___1__h50557, - res__h146185, - res__h187935, - res__h192322, - res__h196815, - res__h199464, - res__h202104, - res__h203926, - res__h204710, - res__h204864, - res__h42283, - res__h42520, - res__h47670, - res__h49098, - res__h50112, - res__h50573, - sfd___3__h12218, - sfd___3__h22785, - sfd__h2613, - x__h13699, - x__h147233, - x__h188904, - x__h193397, - x__h197786, - x__h200426, - x__h202248, - x__h204207, - x__h204831, - x__h2341, - x__h2422, - x__h24232, - x__h2500, - x__h2592, - x__h30632, - x__h36719, - x__h38702, - x__h39389, - x__h40910, - x__h41604, - x__h44183, - x__h46653, - x__h46718, - x__h46800, - x__h48228, - x__h49242, - x__h50272, - x__h51579, - x__h51645, - x__h51713, - x__h51788, - x__h61681, - x__h71293, - x__h72814, - x__h73505, - x__h85002, - x__h95930, - x__h97896, - x__h98583; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q114, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q151, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q119, - IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q148, - IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q154, - IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q116, - IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q122, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852, - _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d4575, - _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_608__ETC___d3744, - _theResult____h110444, - _theResult____h128168, - _theResult____h169448, - _theResult___snd__h118562, - _theResult___snd__h118573, - _theResult___snd__h118575, - _theResult___snd__h118585, - _theResult___snd__h118591, - _theResult___snd__h118614, - _theResult___snd__h127188, - _theResult___snd__h127190, - _theResult___snd__h127197, - _theResult___snd__h127203, - _theResult___snd__h127226, - _theResult___snd__h136415, - _theResult___snd__h136426, - _theResult___snd__h136428, - _theResult___snd__h136438, - _theResult___snd__h136444, - _theResult___snd__h136467, - _theResult___snd__h145065, - _theResult___snd__h145079, - _theResult___snd__h145085, - _theResult___snd__h145103, - _theResult___snd__h168062, - _theResult___snd__h168064, - _theResult___snd__h168071, - _theResult___snd__h168077, - _theResult___snd__h168100, - _theResult___snd__h177695, - _theResult___snd__h177706, - _theResult___snd__h177708, - _theResult___snd__h177718, - _theResult___snd__h177724, - _theResult___snd__h177747, - _theResult___snd__h186461, - _theResult___snd__h186475, - _theResult___snd__h186481, - _theResult___snd__h186499, - b__h39635, - result__h128781, - result__h170061, - sfd__h102814, - sfdin__h118545, - sfdin__h136398, - sfdin__h177678, - x__h128876, - x__h170156, - x__h40311, - x__h41334; - wire [54 : 0] sfd___3__h59804, sfd___3__h69445, sfd__h51803, sfd__h61693; - wire [53 : 0] sfd__h168129, - sfd__h177776, - sfd__h186534, - sfd__h59831, - sfd__h60574, - sfd__h69472, - sfd__h70214, - sfd__h83152, - sfd__h83895, - sfd__h94109, - sfd__h94851, - value__h71541; - wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5005, - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5007, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4978, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4980, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5024, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5026, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2370, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2372, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2388, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2390, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2901, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2903, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2919, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2921, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5037, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2398, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2580, - _theResult___fst_sfd__h153039, - _theResult___fst_sfd__h168865, - _theResult___fst_sfd__h168868, - _theResult___fst_sfd__h178512, - _theResult___fst_sfd__h178515, - _theResult___fst_sfd__h187294, - _theResult___fst_sfd__h187297, - _theResult___fst_sfd__h187306, - _theResult___fst_sfd__h187312, - _theResult___fst_sfd__h60528, - _theResult___fst_sfd__h61284, - _theResult___fst_sfd__h61287, - _theResult___fst_sfd__h70168, - _theResult___fst_sfd__h70923, - _theResult___fst_sfd__h70926, - _theResult___fst_sfd__h83849, - _theResult___fst_sfd__h84605, - _theResult___fst_sfd__h84608, - _theResult___fst_sfd__h94805, - _theResult___fst_sfd__h95560, - _theResult___fst_sfd__h95563, - _theResult___fst_sfd__h99110, - _theResult___sfd__h168767, - _theResult___sfd__h178414, - _theResult___sfd__h187196, - _theResult___sfd__h60431, - _theResult___sfd__h61187, - _theResult___sfd__h70072, - _theResult___sfd__h70827, - _theResult___sfd__h83752, - _theResult___sfd__h84508, - _theResult___sfd__h94709, - _theResult___sfd__h95464, - _theResult___snd_fst_sfd__h149185, - _theResult___snd_fst_sfd__h168871, - _theResult___snd_fst_sfd__h187300, - _theResult___snd_fst_sfd__h61290, - _theResult___snd_fst_sfd__h70929, - _theResult___snd_fst_sfd__h84611, - _theResult___snd_fst_sfd__h95566, - out___1_sfd__h147299, - out_sfd__h168770, - out_sfd__h178417, - out_sfd__h187199, - out_sfd__h60434, - out_sfd__h61190, - out_sfd__h70075, - out_sfd__h70830, - out_sfd__h83755, - out_sfd__h84511, - out_sfd__h94712, - out_sfd__h95467, - value__h98653; - wire [32 : 0] _theResult_____2__h39570, - _theResult_____2__h71474, - out1___1__h40062, - out1___1__h71966; - wire [31 : 0] IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2048, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2061, - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2063, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1911, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1964, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2049, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2064, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1907, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1909, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1962, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2684, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2686, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2745, - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2046, - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2060, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d2747, - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d2688, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1848, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1966, - IF_requestR_3_BIT_191_47_THEN_2147483648_ELSE__ETC___d2617, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - requestR_BITS_159_TO_128__q1, - sfd___3__h29157, - sfd___3__h35273, - sfd__h24253, - x__h146191, - x__h2348, - x__h24238, - x__h2429, - x__h2507, - x__h2598, - x__h39392, - x__h40913, - x__h71296, - x__h72817; - wire [30 : 0] IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29; - wire [24 : 0] sfd__h118643, - sfd__h12245, - sfd__h127255, - sfd__h12788, - sfd__h136496, - sfd__h145138, - sfd__h22812, - sfd__h23351, - sfd__h29184, - sfd__h29724, - sfd__h35300, - sfd__h35839, - value__h36964; - wire [23 : 0] NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2654, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3139, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196; - wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4146, - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4148, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4192, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4194, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4165, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4167, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4211, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4213, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1402, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1404, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1420, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1422, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d545, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d547, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d563, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d565, - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d4224, - _theResult___fst_sfd__h110427, - _theResult___fst_sfd__h119176, - _theResult___fst_sfd__h119179, - _theResult___fst_sfd__h12742, - _theResult___fst_sfd__h127788, - _theResult___fst_sfd__h127791, - _theResult___fst_sfd__h13295, - _theResult___fst_sfd__h13298, - _theResult___fst_sfd__h137029, - _theResult___fst_sfd__h137032, - _theResult___fst_sfd__h145695, - _theResult___fst_sfd__h145698, - _theResult___fst_sfd__h145707, - _theResult___fst_sfd__h145713, - _theResult___fst_sfd__h147557, - _theResult___fst_sfd__h23305, - _theResult___fst_sfd__h23857, - _theResult___fst_sfd__h23860, - _theResult___fst_sfd__h29678, - _theResult___fst_sfd__h30231, - _theResult___fst_sfd__h30234, - _theResult___fst_sfd__h35793, - _theResult___fst_sfd__h36345, - _theResult___fst_sfd__h36348, - _theResult___sfd__h119078, - _theResult___sfd__h12645, - _theResult___sfd__h127690, - _theResult___sfd__h13198, - _theResult___sfd__h136931, - _theResult___sfd__h145597, - _theResult___sfd__h23209, - _theResult___sfd__h23761, - _theResult___sfd__h29581, - _theResult___sfd__h30134, - _theResult___sfd__h35697, - _theResult___sfd__h36249, - _theResult___snd_fst_sfd__h102768, - _theResult___snd_fst_sfd__h127794, - _theResult___snd_fst_sfd__h13301, - _theResult___snd_fst_sfd__h145701, - _theResult___snd_fst_sfd__h23863, - _theResult___snd_fst_sfd__h30237, - _theResult___snd_fst_sfd__h36351, - out_sfd__h119081, - out_sfd__h12648, - out_sfd__h127693, - out_sfd__h13201, - out_sfd__h136934, - out_sfd__h145600, - out_sfd__h23212, - out_sfd__h23764, - out_sfd__h29584, - out_sfd__h30137, - out_sfd__h35700, - out_sfd__h36252, - sV1_sfd__h1213, - sV2_sfd__h1316, - value__h147302; - wire [19 : 0] NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1730, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1877, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935; - wire [11 : 0] IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d4891, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150, - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737, - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3306, - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d4571, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4425, - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_608_ETC___d3740, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960, - x__h128909, - x__h170189, - x__h60559, - x__h70199, - x__h83880, - x__h94836; - wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4876, - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4878, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4551, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4553, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4945, - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4947, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2321, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2347, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2349, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2852, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2878, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2880, - IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d2890, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q153, - _theResult___exp__h168766, - _theResult___exp__h178413, - _theResult___exp__h187195, - _theResult___exp__h60430, - _theResult___exp__h61186, - _theResult___exp__h70071, - _theResult___exp__h70826, - _theResult___exp__h83751, - _theResult___exp__h84507, - _theResult___exp__h94708, - _theResult___exp__h95463, - _theResult___fst_exp__h153038, - _theResult___fst_exp__h168102, - _theResult___fst_exp__h168108, - _theResult___fst_exp__h168111, - _theResult___fst_exp__h168864, - _theResult___fst_exp__h168867, - _theResult___fst_exp__h177684, - _theResult___fst_exp__h177749, - _theResult___fst_exp__h177755, - _theResult___fst_exp__h177758, - _theResult___fst_exp__h178511, - _theResult___fst_exp__h178514, - _theResult___fst_exp__h186467, - _theResult___fst_exp__h186506, - _theResult___fst_exp__h186512, - _theResult___fst_exp__h186515, - _theResult___fst_exp__h187293, - _theResult___fst_exp__h187296, - _theResult___fst_exp__h187305, - _theResult___fst_exp__h187308, - _theResult___fst_exp__h60527, - _theResult___fst_exp__h61283, - _theResult___fst_exp__h61286, - _theResult___fst_exp__h70167, - _theResult___fst_exp__h70922, - _theResult___fst_exp__h70925, - _theResult___fst_exp__h83848, - _theResult___fst_exp__h84604, - _theResult___fst_exp__h84607, - _theResult___fst_exp__h94804, - _theResult___fst_exp__h95559, - _theResult___fst_exp__h95562, - _theResult___snd_fst_exp__h168870, - _theResult___snd_fst_exp__h187299, - _theResult___snd_fst_exp__h61289, - _theResult___snd_fst_exp__h61292, - _theResult___snd_fst_exp__h61295, - _theResult___snd_fst_exp__h70928, - _theResult___snd_fst_exp__h70931, - _theResult___snd_fst_exp__h70934, - _theResult___snd_fst_exp__h84610, - _theResult___snd_fst_exp__h84613, - _theResult___snd_fst_exp__h84616, - _theResult___snd_fst_exp__h95565, - _theResult___snd_fst_exp__h95568, - _theResult___snd_fst_exp__h95571, - din_inc___2_exp__h187331, - din_inc___2_exp__h187361, - din_inc___2_exp__h187385, - din_inc___2_exp__h61329, - din_inc___2_exp__h70964, - din_inc___2_exp__h84650, - din_inc___2_exp__h95601, - out_exp__h168769, - out_exp__h178416, - out_exp__h187198, - out_exp__h60433, - out_exp__h61189, - out_exp__h70074, - out_exp__h70829, - out_exp__h83754, - out_exp__h84510, - out_exp__h94711, - out_exp__h95466, - requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620, - x__h147243; - wire [8 : 0] IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4058, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923, - x__h12773, - x__h23336, - x__h29709, - x__h35824; - wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3599, - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3601, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4043, - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4045, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3716, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3718, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4112, - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4114, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1353, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1379, - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1381, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d496, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d522, - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d524, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1391, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1613, - IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d534, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696, - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q121, - _theResult___exp__h119077, - _theResult___exp__h12644, - _theResult___exp__h127689, - _theResult___exp__h13197, - _theResult___exp__h136930, - _theResult___exp__h145596, - _theResult___exp__h23208, - _theResult___exp__h23760, - _theResult___exp__h29580, - _theResult___exp__h30133, - _theResult___exp__h35696, - _theResult___exp__h36248, - _theResult___fst_exp__h110426, - _theResult___fst_exp__h118551, - _theResult___fst_exp__h118616, - _theResult___fst_exp__h118622, - _theResult___fst_exp__h118625, - _theResult___fst_exp__h119175, - _theResult___fst_exp__h119178, - _theResult___fst_exp__h127228, - _theResult___fst_exp__h127234, - _theResult___fst_exp__h127237, - _theResult___fst_exp__h12741, - _theResult___fst_exp__h127787, - _theResult___fst_exp__h127790, - _theResult___fst_exp__h13294, - _theResult___fst_exp__h13297, - _theResult___fst_exp__h136404, - _theResult___fst_exp__h136469, - _theResult___fst_exp__h136475, - _theResult___fst_exp__h136478, - _theResult___fst_exp__h137028, - _theResult___fst_exp__h137031, - _theResult___fst_exp__h145071, - _theResult___fst_exp__h145110, - _theResult___fst_exp__h145116, - _theResult___fst_exp__h145119, - _theResult___fst_exp__h145694, - _theResult___fst_exp__h145697, - _theResult___fst_exp__h145706, - _theResult___fst_exp__h145709, - _theResult___fst_exp__h23304, - _theResult___fst_exp__h23856, - _theResult___fst_exp__h23859, - _theResult___fst_exp__h29677, - _theResult___fst_exp__h30230, - _theResult___fst_exp__h30233, - _theResult___fst_exp__h35792, - _theResult___fst_exp__h36344, - _theResult___fst_exp__h36347, - _theResult___snd_fst_exp__h127793, - _theResult___snd_fst_exp__h13300, - _theResult___snd_fst_exp__h13303, - _theResult___snd_fst_exp__h13306, - _theResult___snd_fst_exp__h145700, - _theResult___snd_fst_exp__h23862, - _theResult___snd_fst_exp__h23865, - _theResult___snd_fst_exp__h23868, - _theResult___snd_fst_exp__h30236, - _theResult___snd_fst_exp__h30239, - _theResult___snd_fst_exp__h30242, - _theResult___snd_fst_exp__h36350, - _theResult___snd_fst_exp__h36353, - _theResult___snd_fst_exp__h36356, - din_inc___2_exp__h13340, - din_inc___2_exp__h145728, - din_inc___2_exp__h145752, - din_inc___2_exp__h145782, - din_inc___2_exp__h145806, - din_inc___2_exp__h23898, - din_inc___2_exp__h30276, - din_inc___2_exp__h36386, - out_exp__h119080, - out_exp__h12647, - out_exp__h127692, - out_exp__h13200, - out_exp__h136933, - out_exp__h145599, - out_exp__h23211, - out_exp__h23763, - out_exp__h29583, - out_exp__h30136, - out_exp__h35699, - out_exp__h36251, - sV1_exp__h1212, - sV2_exp__h1315, - x__h98593; - wire [6 : 0] IF_IF_requestR_3_BIT_191_47_THEN_NEG_requestR__ETC___d404, - IF_requestR_3_BIT_191_47_THEN_0_ELSE_IF_reques_ETC___d920; - wire [5 : 0] IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d3540, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d4817, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d3984, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1270, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d2241, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1524, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d2455; - wire [4 : 0] _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294, - x__h13466, - x__h146306, - x__h188037, - x__h192454, - x__h202123, - x__h24002, - x__h30402, - x__h36490, - x__h38500, - x__h39201, - x__h40708, - x__h41412, - x__h43644, - x__h49117, - x__h61451, - x__h71064, - x__h72612, - x__h73316, - x__h84772, - x__h95701, - x__h97694, - x__h98395; - wire [1 : 0] IF_sfd___32218_BIT_10_THEN_2_ELSE_0__q9, - IF_sfd___32218_BIT_11_THEN_2_ELSE_0__q8, - IF_sfd___32218_BIT_39_THEN_2_ELSE_0__q7, - IF_sfd___32218_BIT_40_THEN_2_ELSE_0__q6, - IF_sfd___32785_BIT_10_THEN_2_ELSE_0__q25, - IF_sfd___32785_BIT_11_THEN_2_ELSE_0__q24, - IF_sfd___32785_BIT_39_THEN_2_ELSE_0__q23, - IF_sfd___32785_BIT_40_THEN_2_ELSE_0__q22, - IF_sfd___35273_BIT_7_THEN_2_ELSE_0__q53, - IF_sfd___35273_BIT_8_THEN_2_ELSE_0__q52, - IF_sfd___39157_BIT_7_THEN_2_ELSE_0__q39, - IF_sfd___39157_BIT_8_THEN_2_ELSE_0__q38, - IF_sfd___39445_BIT_1_THEN_2_ELSE_0__q82, - IF_sfd___39445_BIT_2_THEN_2_ELSE_0__q81, - IF_sfd___39804_BIT_1_THEN_2_ELSE_0__q68, - IF_sfd___39804_BIT_2_THEN_2_ELSE_0__q67, - IF_sfdin18545_BIT_33_THEN_2_ELSE_0__q115, - IF_sfdin36398_BIT_33_THEN_2_ELSE_0__q120, - IF_sfdin77678_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd27188_BIT_33_THEN_2_ELSE_0__q117, - IF_theResult___snd45065_BIT_33_THEN_2_ELSE_0__q123, - IF_theResult___snd68062_BIT_4_THEN_2_ELSE_0__q149, - IF_theResult___snd86461_BIT_4_THEN_2_ELSE_0__q155, - IF_x0311_BIT_24_THEN_2_ELSE_0__q65, - IF_x1334_BIT_24_THEN_2_ELSE_0__q66, - IF_x2215_BIT_53_THEN_2_ELSE_0__q92, - IF_x3238_BIT_53_THEN_2_ELSE_0__q93, - IF_x7073_BIT_53_THEN_2_ELSE_0__q112, - IF_x7862_BIT_24_THEN_2_ELSE_0__q63, - IF_x8317_BIT_53_THEN_2_ELSE_0__q113, - IF_x9123_BIT_24_THEN_2_ELSE_0__q64, - guard__h110454, - guard__h119189, - guard__h12228, - guard__h12758, - guard__h128178, - guard__h137042, - guard__h160150, - guard__h169458, - guard__h178525, - guard__h22795, - guard__h23321, - guard__h29167, - guard__h29694, - guard__h35283, - guard__h35809, - guard__h36895, - guard__h37673, - guard__h38902, - guard__h39568, - guard__h40122, - guard__h41113, - guard__h59814, - guard__h60544, - guard__h69455, - guard__h70184, - guard__h71472, - guard__h72026, - guard__h73017, - guard__h83135, - guard__h83865, - guard__h94092, - guard__h94821, - guard__h96106, - guard__h96884, - guard__h98096; - wire IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_9_ETC___d4244, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1331, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1481, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2300, - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2415, - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1668, - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d2597, - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2831, - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2948, - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d474, - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d656, - IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d1128, - IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d3100, - IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d5061, - IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d5069, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5073, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5108, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5111, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5118, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5132, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5144, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5156, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1785, - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1927, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2710, - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3188, - IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d2301, - IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d5053, - IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2041, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5071, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5130, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5142, - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5154, - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4262, - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4340, - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4353, - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4366, - IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d2021, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4264, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4315, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4326, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4342, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4355, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4368, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1831, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1842, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1974, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1985, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2007, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2017, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2030, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2032, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2035, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2037, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2055, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2088, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2099, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2103, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1722, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1754, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1814, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1869, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1901, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1956, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2646, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2678, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2739, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3131, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3163, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3217, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1472, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1475, - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1484, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2939, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2942, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2951, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d647, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d650, - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d659, - IF_requestR_3_BIT_191_47_THEN_NOT_requestR_3_B_ETC___d5208, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1733, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1795, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1880, - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1937, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2657, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2720, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3142, - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3198, - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4334, - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4362, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1774, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1836, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1919, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1979, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2044, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2045, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2098, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2104, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2120, - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470, - NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d1278, - NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d2781, - NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d412, - NOT_requestR_3_BITS_159_TO_128_139_EQ_0_140_14_ETC___d1660, - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2699, - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2762, - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3180, - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3239, - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5212, - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5273, - NOT_requestR_3_BITS_190_TO_180_608_ULT_request_ETC___d5252, - NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d2102, - NOT_requestR_3_BIT_158_31_32_AND_NOT_requestR__ETC___d822, - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843, - NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d1013, - NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d3048, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569, - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570, - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738, - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d3542, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d4819, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d3986, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4499, - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4892, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d3664, - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4059, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4297, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4322, - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4349, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247, - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460, - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426, - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410, - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925, - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926, - guard__h128776, - guard__h170056, - requestR_3_BITS_126_TO_116_167_EQ_0_181_AND_re_ETC___d5188, - requestR_3_BITS_179_TO_128_610_ULE_requestR_3__ETC___d5200, - requestR_3_BITS_179_TO_128_610_ULT_requestR_3__ETC___d5205, - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5184, - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5256, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2757, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2768, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3234, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3245, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5176, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5221, - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5241, - requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199, - requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5197, - requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5251, - requestR_3_BITS_190_TO_180_608_ULT_requestR_3__ETC___d5204, - requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NOT_r_ETC___d856, - requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d2043, - requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077, - requestR_3_BIT_159_6_OR_requestR_3_BIT_158_31__ETC___d1671, - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1119, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1122, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1131, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3091, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3094, - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3103; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = resetReqsF$FULL_N ; - assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas && dw_valid$wget ; - - // value method word_fst - assign word_fst = dw_result$wget[68:5] ; - - // value method word_snd - assign word_snd = dw_result$wget[4:0] ; - - // submodule fpu - mkFPU fpu(.CLK(CLK), - .RST_N(RST_N), - .server_core_request_put(fpu$server_core_request_put), - .EN_server_core_request_put(fpu$EN_server_core_request_put), - .EN_server_core_response_get(fpu$EN_server_core_response_get), - .EN_server_reset_request_put(fpu$EN_server_reset_request_put), - .EN_server_reset_response_get(fpu$EN_server_reset_response_get), - .RDY_server_core_request_put(fpu$RDY_server_core_request_put), - .server_core_response_get(fpu$server_core_response_get), - .RDY_server_core_response_get(fpu$RDY_server_core_response_get), - .RDY_server_reset_request_put(fpu$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fpu$RDY_server_reset_response_get)); - - // submodule frmFpuF - FIFO2 #(.width(32'd1), .guarded(32'd1)) frmFpuF(.RST(RST_N), - .CLK(CLK), - .D_IN(frmFpuF$D_IN), - .ENQ(frmFpuF$ENQ), - .DEQ(frmFpuF$DEQ), - .CLR(frmFpuF$CLR), - .D_OUT(), - .FULL_N(), - .EMPTY_N()); - - // submodule resetReqsF - FIFO20 #(.guarded(32'd1)) resetReqsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetReqsF$ENQ), - .DEQ(resetReqsF$DEQ), - .CLR(resetReqsF$CLR), - .FULL_N(resetReqsF$FULL_N), - .EMPTY_N(resetReqsF$EMPTY_N)); - - // submodule resetRspsF - FIFO20 #(.guarded(32'd1)) resetRspsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetRspsF$ENQ), - .DEQ(resetRspsF$DEQ), - .CLR(resetRspsF$CLR), - .FULL_N(resetRspsF$FULL_N), - .EMPTY_N(resetRspsF$EMPTY_N)); - - // rule RL_rl_reset_end - assign CAN_FIRE_RL_rl_reset_end = - fpu$RDY_server_reset_response_get && resetRspsF$FULL_N && - stateR == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_end = CAN_FIRE_RL_rl_reset_end ; - - // rule RL_doFADD_S - assign CAN_FIRE_RL_doFADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0 ; - assign WILL_FIRE_RL_doFADD_S = CAN_FIRE_RL_doFADD_S ; - - // rule RL_doFSUB_S - assign CAN_FIRE_RL_doFSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h04 ; - assign WILL_FIRE_RL_doFSUB_S = CAN_FIRE_RL_doFSUB_S ; - - // rule RL_doFMUL_S - assign CAN_FIRE_RL_doFMUL_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h08 ; - assign WILL_FIRE_RL_doFMUL_S = CAN_FIRE_RL_doFMUL_S ; - - // rule RL_doFMADD_S - assign CAN_FIRE_RL_doFMADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000011 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFMADD_S = CAN_FIRE_RL_doFMADD_S ; - - // rule RL_doFMSUB_S - assign CAN_FIRE_RL_doFMSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000111 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFMSUB_S = CAN_FIRE_RL_doFMSUB_S ; - - // rule RL_doFNMADD_S - assign CAN_FIRE_RL_doFNMADD_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001111 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFNMADD_S = CAN_FIRE_RL_doFNMADD_S ; - - // rule RL_doFNMSUB_S - assign CAN_FIRE_RL_doFNMSUB_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001011 && - requestR[201:200] == 2'd0 ; - assign WILL_FIRE_RL_doFNMSUB_S = CAN_FIRE_RL_doFNMSUB_S ; - - // rule RL_doFDIV_S - assign CAN_FIRE_RL_doFDIV_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0C ; - assign WILL_FIRE_RL_doFDIV_S = CAN_FIRE_RL_doFDIV_S ; - - // rule RL_doFSQRT_S - assign CAN_FIRE_RL_doFSQRT_S = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h2C ; - assign WILL_FIRE_RL_doFSQRT_S = CAN_FIRE_RL_doFSQRT_S ; - - // rule RL_doFSGNJ_S - assign CAN_FIRE_RL_doFSGNJ_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFSGNJ_S = CAN_FIRE_RL_doFSGNJ_S ; - - // rule RL_doFSGNJN_S - assign CAN_FIRE_RL_doFSGNJN_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFSGNJN_S = CAN_FIRE_RL_doFSGNJN_S ; - - // rule RL_doFSGNJX_S - assign CAN_FIRE_RL_doFSGNJX_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h10 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFSGNJX_S = CAN_FIRE_RL_doFSGNJX_S ; - - // rule RL_doFCVT_S_L - assign CAN_FIRE_RL_doFCVT_S_L = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd2 ; - assign WILL_FIRE_RL_doFCVT_S_L = CAN_FIRE_RL_doFCVT_S_L ; - - // rule RL_doFCVT_S_LU - assign CAN_FIRE_RL_doFCVT_S_LU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd3 ; - assign WILL_FIRE_RL_doFCVT_S_LU = CAN_FIRE_RL_doFCVT_S_LU ; - - // rule RL_doFCVT_S_W - assign CAN_FIRE_RL_doFCVT_S_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_S_W = CAN_FIRE_RL_doFCVT_S_W ; - - // rule RL_doFCVT_S_WU - assign CAN_FIRE_RL_doFCVT_S_WU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h68 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_S_WU = CAN_FIRE_RL_doFCVT_S_WU ; - - // rule RL_doFCVT_L_S - assign CAN_FIRE_RL_doFCVT_L_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd2 ; - assign WILL_FIRE_RL_doFCVT_L_S = CAN_FIRE_RL_doFCVT_L_S ; - - // rule RL_doFCVT_LU_S - assign CAN_FIRE_RL_doFCVT_LU_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd3 ; - assign WILL_FIRE_RL_doFCVT_LU_S = CAN_FIRE_RL_doFCVT_LU_S ; - - // rule RL_doFCVT_W_S - assign CAN_FIRE_RL_doFCVT_W_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_W_S = CAN_FIRE_RL_doFCVT_W_S ; - - // rule RL_doFCVT_WU_S - assign CAN_FIRE_RL_doFCVT_WU_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h60 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_WU_S = CAN_FIRE_RL_doFCVT_WU_S ; - - // rule RL_doFMIN_S - assign CAN_FIRE_RL_doFMIN_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h14 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMIN_S = CAN_FIRE_RL_doFMIN_S ; - - // rule RL_doFMAX_S - assign CAN_FIRE_RL_doFMAX_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h14 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFMAX_S = CAN_FIRE_RL_doFMAX_S ; - - // rule RL_doFMV_W_X - assign CAN_FIRE_RL_doFMV_W_X = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h78 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_W_X = CAN_FIRE_RL_doFMV_W_X ; - - // rule RL_doFMV_X_W - assign CAN_FIRE_RL_doFMV_X_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h70 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_X_W = CAN_FIRE_RL_doFMV_X_W ; - - // rule RL_doFEQ_S - assign CAN_FIRE_RL_doFEQ_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFEQ_S = CAN_FIRE_RL_doFEQ_S ; - - // rule RL_doFLT_S - assign CAN_FIRE_RL_doFLT_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFLT_S = CAN_FIRE_RL_doFLT_S ; - - // rule RL_doFLE_S - assign CAN_FIRE_RL_doFLE_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h50 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFLE_S = CAN_FIRE_RL_doFLE_S ; - - // rule RL_doFCLASS_S - assign CAN_FIRE_RL_doFCLASS_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h70 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFCLASS_S = CAN_FIRE_RL_doFCLASS_S ; - - // rule RL_doFADD_D - assign CAN_FIRE_RL_doFADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h01 ; - assign WILL_FIRE_RL_doFADD_D = CAN_FIRE_RL_doFADD_D ; - - // rule RL_doFSUB_D - assign CAN_FIRE_RL_doFSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h05 ; - assign WILL_FIRE_RL_doFSUB_D = CAN_FIRE_RL_doFSUB_D ; - - // rule RL_doFMUL_D - assign CAN_FIRE_RL_doFMUL_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h09 ; - assign WILL_FIRE_RL_doFMUL_D = CAN_FIRE_RL_doFMUL_D ; - - // rule RL_doFMADD_D - assign CAN_FIRE_RL_doFMADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000011 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFMADD_D = CAN_FIRE_RL_doFMADD_D ; - - // rule RL_doFMSUB_D - assign CAN_FIRE_RL_doFMSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1000111 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFMSUB_D = CAN_FIRE_RL_doFMSUB_D ; - - // rule RL_doFNMADD_D - assign CAN_FIRE_RL_doFNMADD_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001111 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFNMADD_D = CAN_FIRE_RL_doFNMADD_D ; - - // rule RL_doFNMSUB_D - assign CAN_FIRE_RL_doFNMSUB_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1001011 && - requestR[201:200] == 2'd1 ; - assign WILL_FIRE_RL_doFNMSUB_D = CAN_FIRE_RL_doFNMSUB_D ; - - // rule RL_doFDIV_D - assign CAN_FIRE_RL_doFDIV_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h0D ; - assign WILL_FIRE_RL_doFDIV_D = CAN_FIRE_RL_doFDIV_D ; - - // rule RL_doFSQRT_D - assign CAN_FIRE_RL_doFSQRT_D = - fpu$RDY_server_core_request_put && requestR[214] && - stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h2D ; - assign WILL_FIRE_RL_doFSQRT_D = CAN_FIRE_RL_doFSQRT_D ; - - // rule RL_doFSGNJ_D - assign CAN_FIRE_RL_doFSGNJ_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFSGNJ_D = CAN_FIRE_RL_doFSGNJ_D ; - - // rule RL_doFSGNJN_D - assign CAN_FIRE_RL_doFSGNJN_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFSGNJN_D = CAN_FIRE_RL_doFSGNJN_D ; - - // rule RL_doFSGNJX_D - assign CAN_FIRE_RL_doFSGNJX_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h11 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFSGNJX_D = CAN_FIRE_RL_doFSGNJX_D ; - - // rule RL_doFCVT_D_W - assign CAN_FIRE_RL_doFCVT_D_W = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_D_W = CAN_FIRE_RL_doFCVT_D_W ; - - // rule RL_doFCVT_D_WU - assign CAN_FIRE_RL_doFCVT_D_WU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_D_WU = CAN_FIRE_RL_doFCVT_D_WU ; - - // rule RL_doFCVT_W_D - assign CAN_FIRE_RL_doFCVT_W_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_W_D = CAN_FIRE_RL_doFCVT_W_D ; - - // rule RL_doFCVT_WU_D - assign CAN_FIRE_RL_doFCVT_WU_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_WU_D = CAN_FIRE_RL_doFCVT_WU_D ; - - // rule RL_doFCVT_D_L - assign CAN_FIRE_RL_doFCVT_D_L = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd2 ; - assign WILL_FIRE_RL_doFCVT_D_L = CAN_FIRE_RL_doFCVT_D_L ; - - // rule RL_doFCVT_D_LU - assign CAN_FIRE_RL_doFCVT_D_LU = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h69 && - requestR[199:195] == 5'd3 ; - assign WILL_FIRE_RL_doFCVT_D_LU = CAN_FIRE_RL_doFCVT_D_LU ; - - // rule RL_doFCVT_L_D - assign CAN_FIRE_RL_doFCVT_L_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd2 ; - assign WILL_FIRE_RL_doFCVT_L_D = CAN_FIRE_RL_doFCVT_L_D ; - - // rule RL_doFCVT_LU_D - assign CAN_FIRE_RL_doFCVT_LU_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h61 && - requestR[199:195] == 5'd3 ; - assign WILL_FIRE_RL_doFCVT_LU_D = CAN_FIRE_RL_doFCVT_LU_D ; - - // rule RL_doFCVT_S_D - assign CAN_FIRE_RL_doFCVT_S_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h20 && - requestR[199:195] == 5'd1 ; - assign WILL_FIRE_RL_doFCVT_S_D = CAN_FIRE_RL_doFCVT_S_D ; - - // rule RL_doFCVT_D_S - assign CAN_FIRE_RL_doFCVT_D_S = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h21 && - requestR[199:195] == 5'd0 ; - assign WILL_FIRE_RL_doFCVT_D_S = CAN_FIRE_RL_doFCVT_D_S ; - - // rule RL_doFMIN_D - assign CAN_FIRE_RL_doFMIN_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h15 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMIN_D = CAN_FIRE_RL_doFMIN_D ; - - // rule RL_doFMAX_D - assign CAN_FIRE_RL_doFMAX_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h15 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFMAX_D = CAN_FIRE_RL_doFMAX_D ; - - // rule RL_doFEQ_D - assign CAN_FIRE_RL_doFEQ_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h2 ; - assign WILL_FIRE_RL_doFEQ_D = CAN_FIRE_RL_doFEQ_D ; - - // rule RL_doFLT_D - assign CAN_FIRE_RL_doFLT_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFLT_D = CAN_FIRE_RL_doFLT_D ; - - // rule RL_doFLE_D - assign CAN_FIRE_RL_doFLE_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h51 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFLE_D = CAN_FIRE_RL_doFLE_D ; - - // rule RL_doFMV_D_X - assign CAN_FIRE_RL_doFMV_D_X = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h79 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_D_X = CAN_FIRE_RL_doFMV_D_X ; - - // rule RL_doFMV_X_D - assign CAN_FIRE_RL_doFMV_X_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h71 && - requestR[194:192] == 3'h0 ; - assign WILL_FIRE_RL_doFMV_X_D = CAN_FIRE_RL_doFMV_X_D ; - - // rule RL_doFCLASS_D - assign CAN_FIRE_RL_doFCLASS_D = - requestR[214] && stateR == 2'd1 && - requestR[213:207] == 7'b1010011 && - requestR[206:200] == 7'h71 && - requestR[194:192] == 3'h1 ; - assign WILL_FIRE_RL_doFCLASS_D = CAN_FIRE_RL_doFCLASS_D ; - - // rule RL_rl_get_fpu_result - assign CAN_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ; - assign WILL_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ; - - // rule RL_rl_drive_fpu_result - assign CAN_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ; - assign WILL_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ; - - // rule RL_rl_reset_begin - assign CAN_FIRE_RL_rl_reset_begin = - fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_begin = CAN_FIRE_RL_rl_reset_begin ; - - // inputs to muxes for submodule ports - assign MUX_dw_result$wset_1__SEL_1 = - fpu$RDY_server_core_response_get && stateR == 2'd2 ; - assign MUX_dw_result$wset_1__VAL_1 = - { x__h204831, fpu$server_core_response_get[4:0] } ; - assign MUX_fpu$server_core_request_put_1__VAL_1 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd0 } ; - assign MUX_fpu$server_core_request_put_1__VAL_2 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd1 } ; - assign MUX_fpu$server_core_request_put_1__VAL_3 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd2 } ; - assign MUX_fpu$server_core_request_put_1__VAL_4 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd5 } ; - assign MUX_fpu$server_core_request_put_1__VAL_5 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd6 } ; - assign MUX_fpu$server_core_request_put_1__VAL_6 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd7 } ; - assign MUX_fpu$server_core_request_put_1__VAL_7 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd8 } ; - assign MUX_fpu$server_core_request_put_1__VAL_8 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 33'h1AAAAAAAA, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38, - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd3 } ; - assign MUX_fpu$server_core_request_put_1__VAL_9 = - { 33'h1AAAAAAAA, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29, - 130'h15555555555555554AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd4 } ; - assign MUX_fpu$server_core_request_put_1__VAL_10 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd0 } ; - assign MUX_fpu$server_core_request_put_1__VAL_11 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd1 } ; - assign MUX_fpu$server_core_request_put_1__VAL_12 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd2 } ; - assign MUX_fpu$server_core_request_put_1__VAL_13 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd5 } ; - assign MUX_fpu$server_core_request_put_1__VAL_14 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd6 } ; - assign MUX_fpu$server_core_request_put_1__VAL_15 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd7 } ; - assign MUX_fpu$server_core_request_put_1__VAL_16 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 1'd0, - requestR[63:0], - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd8 } ; - assign MUX_fpu$server_core_request_put_1__VAL_17 = - { 1'd0, - requestR[191:128], - 1'd0, - requestR[127:64], - 65'h0AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd3 } ; - assign MUX_fpu$server_core_request_put_1__VAL_18 = - { 1'd0, - requestR[191:128], - 130'h15555555555555554AAAAAAAAAAAAAAAA, - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50, - 4'd4 } ; - assign MUX_requestR$write_1__VAL_2 = - { 1'd1, - req_opcode, - req_f7, - req_rs2, - req_rm, - req_v1, - req_v2, - req_v3 } ; - assign MUX_resultR$write_1__VAL_3 = - { 1'd1, x__h204831, fpu$server_core_response_get[4:0] } ; - assign MUX_resultR$write_1__VAL_4 = { 1'd1, x__h204207, 5'd0 } ; - assign MUX_resultR$write_1__VAL_5 = { 1'd1, requestR[191:128], 5'd0 } ; - assign MUX_resultR$write_1__VAL_7 = { 1'd1, x__h202248, x__h202123 } ; - assign MUX_resultR$write_1__VAL_8 = { 1'd1, x__h200426, x__h202123 } ; - assign MUX_resultR$write_1__VAL_9 = { 1'd1, x__h197786, x__h192454 } ; - assign MUX_resultR$write_1__VAL_10 = { 1'd1, x__h193397, x__h192454 } ; - assign MUX_resultR$write_1__VAL_11 = { 1'd1, x__h188904, x__h192454 } ; - assign MUX_resultR$write_1__VAL_12 = { 1'd1, x__h147233, x__h188037 } ; - assign MUX_resultR$write_1__VAL_13 = { 1'd1, x__h98583, x__h146306 } ; - assign MUX_resultR$write_1__VAL_14 = { 1'd1, x__h97896, x__h98395 } ; - assign MUX_resultR$write_1__VAL_15 = { 1'd1, x__h95930, x__h97694 } ; - assign MUX_resultR$write_1__VAL_16 = { 1'd1, x__h85002, x__h95701 } ; - assign MUX_resultR$write_1__VAL_17 = { 1'd1, x__h73505, x__h84772 } ; - assign MUX_resultR$write_1__VAL_18 = { 1'd1, x__h72814, x__h73316 } ; - assign MUX_resultR$write_1__VAL_19 = { 1'd1, x__h71293, x__h72612 } ; - assign MUX_resultR$write_1__VAL_20 = { 1'd1, x__h61681, x__h71064 } ; - assign MUX_resultR$write_1__VAL_21 = { 1'd1, x__h51788, x__h61451 } ; - assign MUX_resultR$write_1__VAL_22 = { 1'd1, x__h51713, 5'd0 } ; - assign MUX_resultR$write_1__VAL_23 = { 1'd1, x__h51645, 5'd0 } ; - assign MUX_resultR$write_1__VAL_24 = { 1'd1, x__h51579, 5'd0 } ; - assign MUX_resultR$write_1__VAL_25 = { 1'd1, x__h50272, 5'd0 } ; - assign MUX_resultR$write_1__VAL_26 = { 1'd1, x__h49242, x__h49117 } ; - assign MUX_resultR$write_1__VAL_27 = { 1'd1, x__h48228, x__h49117 } ; - assign MUX_resultR$write_1__VAL_28 = { 1'd1, x__h46800, x__h43644 } ; - assign MUX_resultR$write_1__VAL_29 = { 1'd1, x__h46718, 5'd0 } ; - assign MUX_resultR$write_1__VAL_30 = { 1'd1, x__h46653, 5'd0 } ; - assign MUX_resultR$write_1__VAL_31 = { 1'd1, x__h44183, x__h43644 } ; - assign MUX_resultR$write_1__VAL_32 = { 1'd1, x__h41604, x__h43644 } ; - assign MUX_resultR$write_1__VAL_33 = { 1'd1, x__h40910, x__h41412 } ; - assign MUX_resultR$write_1__VAL_34 = { 1'd1, x__h39389, x__h40708 } ; - assign MUX_resultR$write_1__VAL_35 = { 1'd1, x__h38702, x__h39201 } ; - assign MUX_resultR$write_1__VAL_36 = { 1'd1, x__h36719, x__h38500 } ; - assign MUX_resultR$write_1__VAL_37 = { 1'd1, x__h30632, x__h36490 } ; - assign MUX_resultR$write_1__VAL_38 = { 1'd1, x__h24232, x__h30402 } ; - assign MUX_resultR$write_1__VAL_39 = { 1'd1, x__h13699, x__h24002 } ; - assign MUX_resultR$write_1__VAL_40 = { 1'd1, x__h2592, x__h13466 } ; - assign MUX_resultR$write_1__VAL_41 = { 1'd1, x__h2500, 5'd0 } ; - assign MUX_resultR$write_1__VAL_42 = { 1'd1, x__h2422, 5'd0 } ; - assign MUX_resultR$write_1__VAL_43 = { 1'd1, x__h2341, 5'd0 } ; - - // inlined wires - assign dw_valid$wget = !WILL_FIRE_RL_rl_drive_fpu_result || resultR[69] ; - assign dw_valid$whas = - WILL_FIRE_RL_rl_drive_fpu_result || - WILL_FIRE_RL_rl_get_fpu_result ; - assign dw_result$wget = - WILL_FIRE_RL_rl_get_fpu_result ? - MUX_dw_result$wset_1__VAL_1 : - resultR[68:0] ; - - // register requestR - assign requestR$D_IN = - WILL_FIRE_RL_rl_reset_begin ? - 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - MUX_requestR$write_1__VAL_2 ; - assign requestR$EN = WILL_FIRE_RL_rl_reset_begin || EN_req ; - - // register resultR - always@(WILL_FIRE_RL_rl_reset_begin or - EN_req or - WILL_FIRE_RL_rl_get_fpu_result or - MUX_resultR$write_1__VAL_3 or - WILL_FIRE_RL_doFCLASS_D or - MUX_resultR$write_1__VAL_4 or - WILL_FIRE_RL_doFMV_X_D or - MUX_resultR$write_1__VAL_5 or - WILL_FIRE_RL_doFMV_D_X or - WILL_FIRE_RL_doFLE_D or - MUX_resultR$write_1__VAL_7 or - WILL_FIRE_RL_doFLT_D or - MUX_resultR$write_1__VAL_8 or - WILL_FIRE_RL_doFEQ_D or - MUX_resultR$write_1__VAL_9 or - WILL_FIRE_RL_doFMAX_D or - MUX_resultR$write_1__VAL_10 or - WILL_FIRE_RL_doFMIN_D or - MUX_resultR$write_1__VAL_11 or - WILL_FIRE_RL_doFCVT_D_S or - MUX_resultR$write_1__VAL_12 or - WILL_FIRE_RL_doFCVT_S_D or - MUX_resultR$write_1__VAL_13 or - WILL_FIRE_RL_doFCVT_LU_D or - MUX_resultR$write_1__VAL_14 or - WILL_FIRE_RL_doFCVT_L_D or - MUX_resultR$write_1__VAL_15 or - WILL_FIRE_RL_doFCVT_D_LU or - MUX_resultR$write_1__VAL_16 or - WILL_FIRE_RL_doFCVT_D_L or - MUX_resultR$write_1__VAL_17 or - WILL_FIRE_RL_doFCVT_WU_D or - MUX_resultR$write_1__VAL_18 or - WILL_FIRE_RL_doFCVT_W_D or - MUX_resultR$write_1__VAL_19 or - WILL_FIRE_RL_doFCVT_D_WU or - MUX_resultR$write_1__VAL_20 or - WILL_FIRE_RL_doFCVT_D_W or - MUX_resultR$write_1__VAL_21 or - WILL_FIRE_RL_doFSGNJX_D or - MUX_resultR$write_1__VAL_22 or - WILL_FIRE_RL_doFSGNJN_D or - MUX_resultR$write_1__VAL_23 or - WILL_FIRE_RL_doFSGNJ_D or - MUX_resultR$write_1__VAL_24 or - WILL_FIRE_RL_doFCLASS_S or - MUX_resultR$write_1__VAL_25 or - WILL_FIRE_RL_doFLE_S or - MUX_resultR$write_1__VAL_26 or - WILL_FIRE_RL_doFLT_S or - MUX_resultR$write_1__VAL_27 or - WILL_FIRE_RL_doFEQ_S or - MUX_resultR$write_1__VAL_28 or - WILL_FIRE_RL_doFMV_X_W or - MUX_resultR$write_1__VAL_29 or - WILL_FIRE_RL_doFMV_W_X or - MUX_resultR$write_1__VAL_30 or - WILL_FIRE_RL_doFMAX_S or - MUX_resultR$write_1__VAL_31 or - WILL_FIRE_RL_doFMIN_S or - MUX_resultR$write_1__VAL_32 or - WILL_FIRE_RL_doFCVT_WU_S or - MUX_resultR$write_1__VAL_33 or - WILL_FIRE_RL_doFCVT_W_S or - MUX_resultR$write_1__VAL_34 or - WILL_FIRE_RL_doFCVT_LU_S or - MUX_resultR$write_1__VAL_35 or - WILL_FIRE_RL_doFCVT_L_S or - MUX_resultR$write_1__VAL_36 or - WILL_FIRE_RL_doFCVT_S_WU or - MUX_resultR$write_1__VAL_37 or - WILL_FIRE_RL_doFCVT_S_W or - MUX_resultR$write_1__VAL_38 or - WILL_FIRE_RL_doFCVT_S_LU or - MUX_resultR$write_1__VAL_39 or - WILL_FIRE_RL_doFCVT_S_L or - MUX_resultR$write_1__VAL_40 or - WILL_FIRE_RL_doFSGNJX_S or - MUX_resultR$write_1__VAL_41 or - WILL_FIRE_RL_doFSGNJN_S or - MUX_resultR$write_1__VAL_42 or - WILL_FIRE_RL_doFSGNJ_S or MUX_resultR$write_1__VAL_43) - case (1'b1) - WILL_FIRE_RL_rl_reset_begin || EN_req: - resultR$D_IN = 70'h0AAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_get_fpu_result: resultR$D_IN = MUX_resultR$write_1__VAL_3; - WILL_FIRE_RL_doFCLASS_D: resultR$D_IN = MUX_resultR$write_1__VAL_4; - WILL_FIRE_RL_doFMV_X_D: resultR$D_IN = MUX_resultR$write_1__VAL_5; - WILL_FIRE_RL_doFMV_D_X: resultR$D_IN = MUX_resultR$write_1__VAL_5; - WILL_FIRE_RL_doFLE_D: resultR$D_IN = MUX_resultR$write_1__VAL_7; - WILL_FIRE_RL_doFLT_D: resultR$D_IN = MUX_resultR$write_1__VAL_8; - WILL_FIRE_RL_doFEQ_D: resultR$D_IN = MUX_resultR$write_1__VAL_9; - WILL_FIRE_RL_doFMAX_D: resultR$D_IN = MUX_resultR$write_1__VAL_10; - WILL_FIRE_RL_doFMIN_D: resultR$D_IN = MUX_resultR$write_1__VAL_11; - WILL_FIRE_RL_doFCVT_D_S: resultR$D_IN = MUX_resultR$write_1__VAL_12; - WILL_FIRE_RL_doFCVT_S_D: resultR$D_IN = MUX_resultR$write_1__VAL_13; - WILL_FIRE_RL_doFCVT_LU_D: resultR$D_IN = MUX_resultR$write_1__VAL_14; - WILL_FIRE_RL_doFCVT_L_D: resultR$D_IN = MUX_resultR$write_1__VAL_15; - WILL_FIRE_RL_doFCVT_D_LU: resultR$D_IN = MUX_resultR$write_1__VAL_16; - WILL_FIRE_RL_doFCVT_D_L: resultR$D_IN = MUX_resultR$write_1__VAL_17; - WILL_FIRE_RL_doFCVT_WU_D: resultR$D_IN = MUX_resultR$write_1__VAL_18; - WILL_FIRE_RL_doFCVT_W_D: resultR$D_IN = MUX_resultR$write_1__VAL_19; - WILL_FIRE_RL_doFCVT_D_WU: resultR$D_IN = MUX_resultR$write_1__VAL_20; - WILL_FIRE_RL_doFCVT_D_W: resultR$D_IN = MUX_resultR$write_1__VAL_21; - WILL_FIRE_RL_doFSGNJX_D: resultR$D_IN = MUX_resultR$write_1__VAL_22; - WILL_FIRE_RL_doFSGNJN_D: resultR$D_IN = MUX_resultR$write_1__VAL_23; - WILL_FIRE_RL_doFSGNJ_D: resultR$D_IN = MUX_resultR$write_1__VAL_24; - WILL_FIRE_RL_doFCLASS_S: resultR$D_IN = MUX_resultR$write_1__VAL_25; - WILL_FIRE_RL_doFLE_S: resultR$D_IN = MUX_resultR$write_1__VAL_26; - WILL_FIRE_RL_doFLT_S: resultR$D_IN = MUX_resultR$write_1__VAL_27; - WILL_FIRE_RL_doFEQ_S: resultR$D_IN = MUX_resultR$write_1__VAL_28; - WILL_FIRE_RL_doFMV_X_W: resultR$D_IN = MUX_resultR$write_1__VAL_29; - WILL_FIRE_RL_doFMV_W_X: resultR$D_IN = MUX_resultR$write_1__VAL_30; - WILL_FIRE_RL_doFMAX_S: resultR$D_IN = MUX_resultR$write_1__VAL_31; - WILL_FIRE_RL_doFMIN_S: resultR$D_IN = MUX_resultR$write_1__VAL_32; - WILL_FIRE_RL_doFCVT_WU_S: resultR$D_IN = MUX_resultR$write_1__VAL_33; - WILL_FIRE_RL_doFCVT_W_S: resultR$D_IN = MUX_resultR$write_1__VAL_34; - WILL_FIRE_RL_doFCVT_LU_S: resultR$D_IN = MUX_resultR$write_1__VAL_35; - WILL_FIRE_RL_doFCVT_L_S: resultR$D_IN = MUX_resultR$write_1__VAL_36; - WILL_FIRE_RL_doFCVT_S_WU: resultR$D_IN = MUX_resultR$write_1__VAL_37; - WILL_FIRE_RL_doFCVT_S_W: resultR$D_IN = MUX_resultR$write_1__VAL_38; - WILL_FIRE_RL_doFCVT_S_LU: resultR$D_IN = MUX_resultR$write_1__VAL_39; - WILL_FIRE_RL_doFCVT_S_L: resultR$D_IN = MUX_resultR$write_1__VAL_40; - WILL_FIRE_RL_doFSGNJX_S: resultR$D_IN = MUX_resultR$write_1__VAL_41; - WILL_FIRE_RL_doFSGNJN_S: resultR$D_IN = MUX_resultR$write_1__VAL_42; - WILL_FIRE_RL_doFSGNJ_S: resultR$D_IN = MUX_resultR$write_1__VAL_43; - default: resultR$D_IN = 70'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign resultR$EN = - WILL_FIRE_RL_rl_reset_begin || EN_req || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFSGNJ_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFCVT_S_L || - WILL_FIRE_RL_doFCVT_S_LU || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_L_S || - WILL_FIRE_RL_doFCVT_LU_S || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFLE_S || - WILL_FIRE_RL_doFCLASS_S || - WILL_FIRE_RL_doFSGNJ_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_D_L || - WILL_FIRE_RL_doFCVT_D_LU || - WILL_FIRE_RL_doFCVT_L_D || - WILL_FIRE_RL_doFCVT_LU_D || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_rl_get_fpu_result ; - - // register stateR - always@(WILL_FIRE_RL_rl_reset_begin or - EN_req or - WILL_FIRE_RL_rl_get_fpu_result or - WILL_FIRE_RL_doFCLASS_D or - WILL_FIRE_RL_doFMV_X_D or - WILL_FIRE_RL_doFMV_D_X or - WILL_FIRE_RL_doFLE_D or - WILL_FIRE_RL_doFLT_D or - WILL_FIRE_RL_doFEQ_D or - WILL_FIRE_RL_doFMAX_D or - WILL_FIRE_RL_doFMIN_D or - WILL_FIRE_RL_doFCVT_D_S or - WILL_FIRE_RL_doFCVT_S_D or - WILL_FIRE_RL_doFCVT_LU_D or - WILL_FIRE_RL_doFCVT_L_D or - WILL_FIRE_RL_doFCVT_D_LU or - WILL_FIRE_RL_doFCVT_D_L or - WILL_FIRE_RL_doFCVT_WU_D or - WILL_FIRE_RL_doFCVT_W_D or - WILL_FIRE_RL_doFCVT_D_WU or - WILL_FIRE_RL_doFCVT_D_W or - WILL_FIRE_RL_doFSGNJX_D or - WILL_FIRE_RL_doFSGNJN_D or - WILL_FIRE_RL_doFSGNJ_D or - WILL_FIRE_RL_doFSQRT_D or - WILL_FIRE_RL_doFDIV_D or - WILL_FIRE_RL_doFNMSUB_D or - WILL_FIRE_RL_doFNMADD_D or - WILL_FIRE_RL_doFMSUB_D or - WILL_FIRE_RL_doFMADD_D or - WILL_FIRE_RL_doFMUL_D or - WILL_FIRE_RL_doFSUB_D or - WILL_FIRE_RL_doFADD_D or - WILL_FIRE_RL_doFCLASS_S or - WILL_FIRE_RL_doFLE_S or - WILL_FIRE_RL_doFLT_S or - WILL_FIRE_RL_doFEQ_S or - WILL_FIRE_RL_doFMV_X_W or - WILL_FIRE_RL_doFMV_W_X or - WILL_FIRE_RL_doFMAX_S or - WILL_FIRE_RL_doFMIN_S or - WILL_FIRE_RL_doFCVT_WU_S or - WILL_FIRE_RL_doFCVT_W_S or - WILL_FIRE_RL_doFCVT_LU_S or - WILL_FIRE_RL_doFCVT_L_S or - WILL_FIRE_RL_doFCVT_S_WU or - WILL_FIRE_RL_doFCVT_S_W or - WILL_FIRE_RL_doFCVT_S_LU or - WILL_FIRE_RL_doFCVT_S_L or - WILL_FIRE_RL_doFSGNJX_S or - WILL_FIRE_RL_doFSGNJN_S or - WILL_FIRE_RL_doFSGNJ_S or - WILL_FIRE_RL_doFSQRT_S or - WILL_FIRE_RL_doFDIV_S or - WILL_FIRE_RL_doFNMSUB_S or - WILL_FIRE_RL_doFNMADD_S or - WILL_FIRE_RL_doFMSUB_S or - WILL_FIRE_RL_doFMADD_S or - WILL_FIRE_RL_doFMUL_S or - WILL_FIRE_RL_doFSUB_S or - WILL_FIRE_RL_doFADD_S or WILL_FIRE_RL_rl_reset_end) - case (1'b1) - WILL_FIRE_RL_rl_reset_begin: stateR$D_IN = 2'd0; - EN_req: stateR$D_IN = 2'd1; - WILL_FIRE_RL_rl_get_fpu_result || WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_LU_D || - WILL_FIRE_RL_doFCVT_L_D || - WILL_FIRE_RL_doFCVT_D_LU || - WILL_FIRE_RL_doFCVT_D_L || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJ_D: - stateR$D_IN = 2'd3; - WILL_FIRE_RL_doFSQRT_D || WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFADD_D: - stateR$D_IN = 2'd2; - WILL_FIRE_RL_doFCLASS_S || WILL_FIRE_RL_doFLE_S || WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_LU_S || - WILL_FIRE_RL_doFCVT_L_S || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFCVT_S_LU || - WILL_FIRE_RL_doFCVT_S_L || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJ_S: - stateR$D_IN = 2'd3; - WILL_FIRE_RL_doFSQRT_S || WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFADD_S: - stateR$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_end: stateR$D_IN = 2'd1; - default: stateR$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign stateR$EN = - WILL_FIRE_RL_rl_reset_begin || WILL_FIRE_RL_rl_reset_end || - EN_req || - WILL_FIRE_RL_doFSQRT_D || - WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFADD_D || - WILL_FIRE_RL_doFSQRT_S || - WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFADD_S || - WILL_FIRE_RL_rl_get_fpu_result || - WILL_FIRE_RL_doFCLASS_D || - WILL_FIRE_RL_doFMV_X_D || - WILL_FIRE_RL_doFMV_D_X || - WILL_FIRE_RL_doFLE_D || - WILL_FIRE_RL_doFLT_D || - WILL_FIRE_RL_doFEQ_D || - WILL_FIRE_RL_doFMAX_D || - WILL_FIRE_RL_doFMIN_D || - WILL_FIRE_RL_doFCVT_D_S || - WILL_FIRE_RL_doFCVT_S_D || - WILL_FIRE_RL_doFCVT_LU_D || - WILL_FIRE_RL_doFCVT_L_D || - WILL_FIRE_RL_doFCVT_D_LU || - WILL_FIRE_RL_doFCVT_D_L || - WILL_FIRE_RL_doFCVT_WU_D || - WILL_FIRE_RL_doFCVT_W_D || - WILL_FIRE_RL_doFCVT_D_WU || - WILL_FIRE_RL_doFCVT_D_W || - WILL_FIRE_RL_doFSGNJX_D || - WILL_FIRE_RL_doFSGNJN_D || - WILL_FIRE_RL_doFSGNJ_D || - WILL_FIRE_RL_doFCLASS_S || - WILL_FIRE_RL_doFLE_S || - WILL_FIRE_RL_doFLT_S || - WILL_FIRE_RL_doFEQ_S || - WILL_FIRE_RL_doFMV_X_W || - WILL_FIRE_RL_doFMV_W_X || - WILL_FIRE_RL_doFMAX_S || - WILL_FIRE_RL_doFMIN_S || - WILL_FIRE_RL_doFCVT_WU_S || - WILL_FIRE_RL_doFCVT_W_S || - WILL_FIRE_RL_doFCVT_LU_S || - WILL_FIRE_RL_doFCVT_L_S || - WILL_FIRE_RL_doFCVT_S_WU || - WILL_FIRE_RL_doFCVT_S_W || - WILL_FIRE_RL_doFCVT_S_LU || - WILL_FIRE_RL_doFCVT_S_L || - WILL_FIRE_RL_doFSGNJX_S || - WILL_FIRE_RL_doFSGNJN_S || - WILL_FIRE_RL_doFSGNJ_S ; - - // submodule fpu - always@(WILL_FIRE_RL_doFADD_S or - MUX_fpu$server_core_request_put_1__VAL_1 or - WILL_FIRE_RL_doFSUB_S or - MUX_fpu$server_core_request_put_1__VAL_2 or - WILL_FIRE_RL_doFMUL_S or - MUX_fpu$server_core_request_put_1__VAL_3 or - WILL_FIRE_RL_doFMADD_S or - MUX_fpu$server_core_request_put_1__VAL_4 or - WILL_FIRE_RL_doFMSUB_S or - MUX_fpu$server_core_request_put_1__VAL_5 or - WILL_FIRE_RL_doFNMADD_S or - MUX_fpu$server_core_request_put_1__VAL_6 or - WILL_FIRE_RL_doFNMSUB_S or - MUX_fpu$server_core_request_put_1__VAL_7 or - WILL_FIRE_RL_doFDIV_S or - MUX_fpu$server_core_request_put_1__VAL_8 or - WILL_FIRE_RL_doFSQRT_S or - MUX_fpu$server_core_request_put_1__VAL_9 or - WILL_FIRE_RL_doFADD_D or - MUX_fpu$server_core_request_put_1__VAL_10 or - WILL_FIRE_RL_doFSUB_D or - MUX_fpu$server_core_request_put_1__VAL_11 or - WILL_FIRE_RL_doFMUL_D or - MUX_fpu$server_core_request_put_1__VAL_12 or - WILL_FIRE_RL_doFMADD_D or - MUX_fpu$server_core_request_put_1__VAL_13 or - WILL_FIRE_RL_doFMSUB_D or - MUX_fpu$server_core_request_put_1__VAL_14 or - WILL_FIRE_RL_doFNMADD_D or - MUX_fpu$server_core_request_put_1__VAL_15 or - WILL_FIRE_RL_doFNMSUB_D or - MUX_fpu$server_core_request_put_1__VAL_16 or - WILL_FIRE_RL_doFDIV_D or - MUX_fpu$server_core_request_put_1__VAL_17 or - WILL_FIRE_RL_doFSQRT_D or MUX_fpu$server_core_request_put_1__VAL_18) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_doFADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_1; - WILL_FIRE_RL_doFSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_2; - WILL_FIRE_RL_doFMUL_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_3; - WILL_FIRE_RL_doFMADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_4; - WILL_FIRE_RL_doFMSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_5; - WILL_FIRE_RL_doFNMADD_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_6; - WILL_FIRE_RL_doFNMSUB_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_7; - WILL_FIRE_RL_doFDIV_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_8; - WILL_FIRE_RL_doFSQRT_S: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_9; - WILL_FIRE_RL_doFADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_10; - WILL_FIRE_RL_doFSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_11; - WILL_FIRE_RL_doFMUL_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_12; - WILL_FIRE_RL_doFMADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_13; - WILL_FIRE_RL_doFMSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_14; - WILL_FIRE_RL_doFNMADD_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_15; - WILL_FIRE_RL_doFNMSUB_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_16; - WILL_FIRE_RL_doFDIV_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_17; - WILL_FIRE_RL_doFSQRT_D: - fpu$server_core_request_put = - MUX_fpu$server_core_request_put_1__VAL_18; - default: fpu$server_core_request_put = - 202'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fpu$EN_server_core_request_put = - WILL_FIRE_RL_doFADD_S || WILL_FIRE_RL_doFSUB_S || - WILL_FIRE_RL_doFMUL_S || - WILL_FIRE_RL_doFMADD_S || - WILL_FIRE_RL_doFMSUB_S || - WILL_FIRE_RL_doFNMADD_S || - WILL_FIRE_RL_doFNMSUB_S || - WILL_FIRE_RL_doFDIV_S || - WILL_FIRE_RL_doFSQRT_S || - WILL_FIRE_RL_doFADD_D || - WILL_FIRE_RL_doFSUB_D || - WILL_FIRE_RL_doFMUL_D || - WILL_FIRE_RL_doFMADD_D || - WILL_FIRE_RL_doFMSUB_D || - WILL_FIRE_RL_doFNMADD_D || - WILL_FIRE_RL_doFNMSUB_D || - WILL_FIRE_RL_doFDIV_D || - WILL_FIRE_RL_doFSQRT_D ; - assign fpu$EN_server_core_response_get = MUX_dw_result$wset_1__SEL_1 ; - assign fpu$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_begin ; - assign fpu$EN_server_reset_response_get = CAN_FIRE_RL_rl_reset_end ; - - // submodule frmFpuF - assign frmFpuF$D_IN = 1'b0 ; - assign frmFpuF$ENQ = 1'b0 ; - assign frmFpuF$DEQ = 1'b0 ; - assign frmFpuF$CLR = CAN_FIRE_RL_rl_reset_begin ; - - // submodule resetReqsF - assign resetReqsF$ENQ = EN_server_reset_request_put ; - assign resetReqsF$DEQ = - fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ; - assign resetReqsF$CLR = 1'b0 ; - - // submodule resetRspsF - assign resetRspsF$ENQ = - fpu$RDY_server_reset_response_get && resetRspsF$FULL_N && - stateR == 2'd0 ; - assign resetRspsF$DEQ = EN_server_reset_response_get ; - assign resetRspsF$CLR = 1'b0 ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q114 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d3542 ? - _theResult___snd__h118614 : - _theResult____h110444 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q151 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d4819 ? - _theResult___snd__h177747 : - _theResult____h169448 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q119 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d3986 ? - _theResult___snd__h136467 : - _theResult____h128168 ; - assign IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q148 = - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4499 ? - _theResult___snd__h168100 : - 57'd0 ; - assign IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q154 = - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4892 ? - _theResult___snd__h168100 : - _theResult___snd__h186499 ; - assign IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q116 = - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d3664 ? - _theResult___snd__h127226 : - 57'd0 ; - assign IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q122 = - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4059 ? - _theResult___snd__h127226 : - _theResult___snd__h145103 ; - assign IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_9_ETC___d4244 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - ((_theResult___fst_exp__h118551 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10454_0b0_requestR_BIT_191_0b1_reque_ETC__q140 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q141)) : - ((_theResult___fst_exp__h127237 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard19189_0b0_requestR_BIT_191_0b1_reque_ETC__q142 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q143)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1331 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9167_0b0_requestR_BIT_159_0b1_reques_ETC__q40 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q41) : - ((x__h29709[7:0] == 8'd255) ? - requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9694_0b0_requestR_BIT_159_0b1_reques_ETC__q42 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q43)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1481 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 ? - guard__h29167 != 2'b0 : - x__h29709[7:0] != 8'd255 && guard__h29694 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2300 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9814_0b0_requestR_BIT_159_0b1_reques_ETC__q69 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q70) : - ((x__h60559[10:0] == 11'd2047) ? - requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard0544_0b0_requestR_BIT_159_0b1_reques_ETC__q71 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q72)) ; - assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2415 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 ? - guard__h59814 != 2'b0 : - x__h60559[10:0] != 11'd2047 && guard__h60544 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1668 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530 ? - guard__h35283 != 2'b0 : - x__h35824[7:0] != 8'd255 && guard__h35809 != 2'b0 ; - assign IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d2597 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461 ? - guard__h69455 != 2'b0 : - x__h70199[10:0] != 11'd2047 && guard__h70184 != 2'b0 ; - assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2831 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3135_0b0_requestR_BIT_191_0b1_reques_ETC__q94 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q95) : - ((x__h83880[10:0] == 11'd2047) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3865_0b0_requestR_BIT_191_0b1_reques_ETC__q96 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q97)) ; - assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2948 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 ? - guard__h83135 != 2'b0 : - x__h83880[10:0] != 11'd2047 && guard__h83865 != 2'b0 ; - assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d474 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 ? - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2228_0b0_requestR_BIT_191_0b1_reques_ETC__q10 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11) : - ((x__h12773[7:0] == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2758_0b0_requestR_BIT_191_0b1_reques_ETC__q12 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q13)) ; - assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d656 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 ? - guard__h12228 != 2'b0 : - x__h12773[7:0] != 8'd255 && guard__h12758 != 2'b0 ; - assign IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d1128 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926 ? - guard__h22795 != 2'b0 : - x__h23336[7:0] != 8'd255 && guard__h23321 != 2'b0 ; - assign IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d3100 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963 ? - guard__h94092 != 2'b0 : - x__h94836[10:0] != 11'd2047 && guard__h94821 != 2'b0 ; - assign IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d3540 = - (_theResult____h110444[56] ? - 6'd0 : - (_theResult____h110444[55] ? - 6'd1 : - (_theResult____h110444[54] ? - 6'd2 : - (_theResult____h110444[53] ? - 6'd3 : - (_theResult____h110444[52] ? - 6'd4 : - (_theResult____h110444[51] ? - 6'd5 : - (_theResult____h110444[50] ? - 6'd6 : - (_theResult____h110444[49] ? - 6'd7 : - (_theResult____h110444[48] ? - 6'd8 : - (_theResult____h110444[47] ? - 6'd9 : - (_theResult____h110444[46] ? - 6'd10 : - (_theResult____h110444[45] ? - 6'd11 : - (_theResult____h110444[44] ? - 6'd12 : - (_theResult____h110444[43] ? - 6'd13 : - (_theResult____h110444[42] ? - 6'd14 : - (_theResult____h110444[41] ? - 6'd15 : - (_theResult____h110444[40] ? - 6'd16 : - (_theResult____h110444[39] ? - 6'd17 : - (_theResult____h110444[38] ? - 6'd18 : - (_theResult____h110444[37] ? - 6'd19 : - (_theResult____h110444[36] ? - 6'd20 : - (_theResult____h110444[35] ? - 6'd21 : - (_theResult____h110444[34] ? - 6'd22 : - (_theResult____h110444[33] ? - 6'd23 : - (_theResult____h110444[32] ? - 6'd24 : - (_theResult____h110444[31] ? - 6'd25 : - (_theResult____h110444[30] ? - 6'd26 : - (_theResult____h110444[29] ? - 6'd27 : - (_theResult____h110444[28] ? - 6'd28 : - (_theResult____h110444[27] ? - 6'd29 : - (_theResult____h110444[26] ? - 6'd30 : - (_theResult____h110444[25] ? - 6'd31 : - (_theResult____h110444[24] ? - 6'd32 : - (_theResult____h110444[23] ? - 6'd33 : - (_theResult____h110444[22] ? - 6'd34 : - (_theResult____h110444[21] ? - 6'd35 : - (_theResult____h110444[20] ? - 6'd36 : - (_theResult____h110444[19] ? - 6'd37 : - (_theResult____h110444[18] ? - 6'd38 : - (_theResult____h110444[17] ? - 6'd39 : - (_theResult____h110444[16] ? - 6'd40 : - (_theResult____h110444[15] ? - 6'd41 : - (_theResult____h110444[14] ? - 6'd42 : - (_theResult____h110444[13] ? - 6'd43 : - (_theResult____h110444[12] ? - 6'd44 : - (_theResult____h110444[11] ? - 6'd45 : - (_theResult____h110444[10] ? - 6'd46 : - (_theResult____h110444[9] ? - 6'd47 : - (_theResult____h110444[8] ? - 6'd48 : - (_theResult____h110444[7] ? - 6'd49 : - (_theResult____h110444[6] ? - 6'd50 : - (_theResult____h110444[5] ? - 6'd51 : - (_theResult____h110444[4] ? - 6'd52 : - (_theResult____h110444[3] ? - 6'd53 : - (_theResult____h110444[2] ? - 6'd54 : - (_theResult____h110444[1] ? - 6'd55 : - (_theResult____h110444[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d4817 = - (_theResult____h169448[56] ? - 6'd0 : - (_theResult____h169448[55] ? - 6'd1 : - (_theResult____h169448[54] ? - 6'd2 : - (_theResult____h169448[53] ? - 6'd3 : - (_theResult____h169448[52] ? - 6'd4 : - (_theResult____h169448[51] ? - 6'd5 : - (_theResult____h169448[50] ? - 6'd6 : - (_theResult____h169448[49] ? - 6'd7 : - (_theResult____h169448[48] ? - 6'd8 : - (_theResult____h169448[47] ? - 6'd9 : - (_theResult____h169448[46] ? - 6'd10 : - (_theResult____h169448[45] ? - 6'd11 : - (_theResult____h169448[44] ? - 6'd12 : - (_theResult____h169448[43] ? - 6'd13 : - (_theResult____h169448[42] ? - 6'd14 : - (_theResult____h169448[41] ? - 6'd15 : - (_theResult____h169448[40] ? - 6'd16 : - (_theResult____h169448[39] ? - 6'd17 : - (_theResult____h169448[38] ? - 6'd18 : - (_theResult____h169448[37] ? - 6'd19 : - (_theResult____h169448[36] ? - 6'd20 : - (_theResult____h169448[35] ? - 6'd21 : - (_theResult____h169448[34] ? - 6'd22 : - (_theResult____h169448[33] ? - 6'd23 : - (_theResult____h169448[32] ? - 6'd24 : - (_theResult____h169448[31] ? - 6'd25 : - (_theResult____h169448[30] ? - 6'd26 : - (_theResult____h169448[29] ? - 6'd27 : - (_theResult____h169448[28] ? - 6'd28 : - (_theResult____h169448[27] ? - 6'd29 : - (_theResult____h169448[26] ? - 6'd30 : - (_theResult____h169448[25] ? - 6'd31 : - (_theResult____h169448[24] ? - 6'd32 : - (_theResult____h169448[23] ? - 6'd33 : - (_theResult____h169448[22] ? - 6'd34 : - (_theResult____h169448[21] ? - 6'd35 : - (_theResult____h169448[20] ? - 6'd36 : - (_theResult____h169448[19] ? - 6'd37 : - (_theResult____h169448[18] ? - 6'd38 : - (_theResult____h169448[17] ? - 6'd39 : - (_theResult____h169448[16] ? - 6'd40 : - (_theResult____h169448[15] ? - 6'd41 : - (_theResult____h169448[14] ? - 6'd42 : - (_theResult____h169448[13] ? - 6'd43 : - (_theResult____h169448[12] ? - 6'd44 : - (_theResult____h169448[11] ? - 6'd45 : - (_theResult____h169448[10] ? - 6'd46 : - (_theResult____h169448[9] ? - 6'd47 : - (_theResult____h169448[8] ? - 6'd48 : - (_theResult____h169448[7] ? - 6'd49 : - (_theResult____h169448[6] ? - 6'd50 : - (_theResult____h169448[5] ? - 6'd51 : - (_theResult____h169448[4] ? - 6'd52 : - (_theResult____h169448[3] ? - 6'd53 : - (_theResult____h169448[2] ? - 6'd54 : - (_theResult____h169448[1] ? - 6'd55 : - (_theResult____h169448[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d3984 = - (_theResult____h128168[56] ? - 6'd0 : - (_theResult____h128168[55] ? - 6'd1 : - (_theResult____h128168[54] ? - 6'd2 : - (_theResult____h128168[53] ? - 6'd3 : - (_theResult____h128168[52] ? - 6'd4 : - (_theResult____h128168[51] ? - 6'd5 : - (_theResult____h128168[50] ? - 6'd6 : - (_theResult____h128168[49] ? - 6'd7 : - (_theResult____h128168[48] ? - 6'd8 : - (_theResult____h128168[47] ? - 6'd9 : - (_theResult____h128168[46] ? - 6'd10 : - (_theResult____h128168[45] ? - 6'd11 : - (_theResult____h128168[44] ? - 6'd12 : - (_theResult____h128168[43] ? - 6'd13 : - (_theResult____h128168[42] ? - 6'd14 : - (_theResult____h128168[41] ? - 6'd15 : - (_theResult____h128168[40] ? - 6'd16 : - (_theResult____h128168[39] ? - 6'd17 : - (_theResult____h128168[38] ? - 6'd18 : - (_theResult____h128168[37] ? - 6'd19 : - (_theResult____h128168[36] ? - 6'd20 : - (_theResult____h128168[35] ? - 6'd21 : - (_theResult____h128168[34] ? - 6'd22 : - (_theResult____h128168[33] ? - 6'd23 : - (_theResult____h128168[32] ? - 6'd24 : - (_theResult____h128168[31] ? - 6'd25 : - (_theResult____h128168[30] ? - 6'd26 : - (_theResult____h128168[29] ? - 6'd27 : - (_theResult____h128168[28] ? - 6'd28 : - (_theResult____h128168[27] ? - 6'd29 : - (_theResult____h128168[26] ? - 6'd30 : - (_theResult____h128168[25] ? - 6'd31 : - (_theResult____h128168[24] ? - 6'd32 : - (_theResult____h128168[23] ? - 6'd33 : - (_theResult____h128168[22] ? - 6'd34 : - (_theResult____h128168[21] ? - 6'd35 : - (_theResult____h128168[20] ? - 6'd36 : - (_theResult____h128168[19] ? - 6'd37 : - (_theResult____h128168[18] ? - 6'd38 : - (_theResult____h128168[17] ? - 6'd39 : - (_theResult____h128168[16] ? - 6'd40 : - (_theResult____h128168[15] ? - 6'd41 : - (_theResult____h128168[14] ? - 6'd42 : - (_theResult____h128168[13] ? - 6'd43 : - (_theResult____h128168[12] ? - 6'd44 : - (_theResult____h128168[11] ? - 6'd45 : - (_theResult____h128168[10] ? - 6'd46 : - (_theResult____h128168[9] ? - 6'd47 : - (_theResult____h128168[8] ? - 6'd48 : - (_theResult____h128168[7] ? - 6'd49 : - (_theResult____h128168[6] ? - 6'd50 : - (_theResult____h128168[5] ? - 6'd51 : - (_theResult____h128168[4] ? - 6'd52 : - (_theResult____h128168[3] ? - 6'd53 : - (_theResult____h128168[2] ? - 6'd54 : - (_theResult____h128168[1] ? - 6'd55 : - (_theResult____h128168[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d5061 = - (_theResult___fst_exp__h177684 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard69458_0b0_requestR_BITS_191_TO_160_E_ETC__q164 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q165) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3599 = - (guard__h110454 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h118551 : - _theResult___exp__h119077 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3601 = - (guard__h110454 == 2'b0) ? - _theResult___fst_exp__h118551 : - (requestR[191] ? - _theResult___exp__h119077 : - _theResult___fst_exp__h118551) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4146 = - (guard__h110454 == 2'b0 || requestR[191]) ? - sfdin__h118545[56:34] : - _theResult___sfd__h119078 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4148 = - (guard__h110454 == 2'b0) ? - sfdin__h118545[56:34] : - (requestR[191] ? - _theResult___sfd__h119078 : - sfdin__h118545[56:34]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4876 = - (guard__h169458 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h177684 : - _theResult___exp__h178413 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4878 = - (guard__h169458 == 2'b0) ? - _theResult___fst_exp__h177684 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h178413 : - _theResult___fst_exp__h177684) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5005 = - (guard__h169458 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - sfdin__h177678[56:5] : - _theResult___sfd__h178414 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5007 = - (guard__h169458 == 2'b0) ? - sfdin__h177678[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h178414 : - sfdin__h177678[56:5]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4043 = - (guard__h128178 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h136404 : - _theResult___exp__h136930 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4045 = - (guard__h128178 == 2'b0) ? - _theResult___fst_exp__h136404 : - (requestR[191] ? - _theResult___exp__h136930 : - _theResult___fst_exp__h136404) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4192 = - (guard__h128178 == 2'b0 || requestR[191]) ? - sfdin__h136398[56:34] : - _theResult___sfd__h136931 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4194 = - (guard__h128178 == 2'b0) ? - sfdin__h136398[56:34] : - (requestR[191] ? - _theResult___sfd__h136931 : - sfdin__h136398[56:34]) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4551 = - (guard__h160150 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h168111 : - _theResult___exp__h168766 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4553 = - (guard__h160150 == 2'b0) ? - _theResult___fst_exp__h168111 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h168766 : - _theResult___fst_exp__h168111) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4945 = - (guard__h178525 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___fst_exp__h186515 : - _theResult___exp__h187195 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4947 = - (guard__h178525 == 2'b0) ? - _theResult___fst_exp__h186515 : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___exp__h187195 : - _theResult___fst_exp__h186515) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4978 = - (guard__h160150 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___snd__h168062[56:5] : - _theResult___sfd__h168767 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4980 = - (guard__h160150 == 2'b0) ? - _theResult___snd__h168062[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h168767 : - _theResult___snd__h168062[56:5]) ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5024 = - (guard__h178525 == 2'b0 || - requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___snd__h186461[56:5] : - _theResult___sfd__h187196 ; - assign IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5026 = - (guard__h178525 == 2'b0) ? - _theResult___snd__h186461[56:5] : - ((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - _theResult___sfd__h187196 : - _theResult___snd__h186461[56:5]) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3716 = - (guard__h119189 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h127237 : - _theResult___exp__h127689 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3718 = - (guard__h119189 == 2'b0) ? - _theResult___fst_exp__h127237 : - (requestR[191] ? - _theResult___exp__h127689 : - _theResult___fst_exp__h127237) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4112 = - (guard__h137042 == 2'b0 || requestR[191]) ? - _theResult___fst_exp__h145119 : - _theResult___exp__h145596 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4114 = - (guard__h137042 == 2'b0) ? - _theResult___fst_exp__h145119 : - (requestR[191] ? - _theResult___exp__h145596 : - _theResult___fst_exp__h145119) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4165 = - (guard__h119189 == 2'b0 || requestR[191]) ? - _theResult___snd__h127188[56:34] : - _theResult___sfd__h127690 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4167 = - (guard__h119189 == 2'b0) ? - _theResult___snd__h127188[56:34] : - (requestR[191] ? - _theResult___sfd__h127690 : - _theResult___snd__h127188[56:34]) ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4211 = - (guard__h137042 == 2'b0 || requestR[191]) ? - _theResult___snd__h145065[56:34] : - _theResult___sfd__h145597 ; - assign IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4213 = - (guard__h137042 == 2'b0) ? - _theResult___snd__h145065[56:34] : - (requestR[191] ? - _theResult___sfd__h145597 : - _theResult___snd__h145065[56:34]) ; - assign IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d5069 = - (_theResult___fst_exp__h186515 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard78525_0b0_requestR_BITS_191_TO_160_E_ETC__q166 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q167) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1353 = - (guard__h29167 == 2'b0) ? - 8'd0 : - (requestR[159] ? _theResult___exp__h29580 : 8'd0) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1379 = - (guard__h29694 == 2'b0 || requestR[159]) ? - x__h29709[7:0] : - _theResult___exp__h30133 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1381 = - (guard__h29694 == 2'b0) ? - x__h29709[7:0] : - (requestR[159] ? _theResult___exp__h30133 : x__h29709[7:0]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1402 = - (guard__h29167 == 2'b0 || requestR[159]) ? - sfd___3__h29157[31:9] : - _theResult___sfd__h29581 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1404 = - (guard__h29167 == 2'b0) ? - sfd___3__h29157[31:9] : - (requestR[159] ? - _theResult___sfd__h29581 : - sfd___3__h29157[31:9]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1420 = - (guard__h29694 == 2'b0 || requestR[159]) ? - sfd___3__h29157[30:8] : - _theResult___sfd__h30134 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1422 = - (guard__h29694 == 2'b0) ? - sfd___3__h29157[30:8] : - (requestR[159] ? - _theResult___sfd__h30134 : - sfd___3__h29157[30:8]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2321 = - (guard__h59814 == 2'b0) ? - 11'd0 : - (requestR[159] ? _theResult___exp__h60430 : 11'd0) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2347 = - (guard__h60544 == 2'b0 || requestR[159]) ? - x__h60559[10:0] : - _theResult___exp__h61186 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2349 = - (guard__h60544 == 2'b0) ? - x__h60559[10:0] : - (requestR[159] ? _theResult___exp__h61186 : x__h60559[10:0]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2370 = - (guard__h59814 == 2'b0 || requestR[159]) ? - sfd___3__h59804[54:3] : - _theResult___sfd__h60431 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2372 = - (guard__h59814 == 2'b0) ? - sfd___3__h59804[54:3] : - (requestR[159] ? - _theResult___sfd__h60431 : - sfd___3__h59804[54:3]) ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2388 = - (guard__h60544 == 2'b0 || requestR[159]) ? - sfd___3__h59804[53:2] : - _theResult___sfd__h61187 ; - assign IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2390 = - (guard__h60544 == 2'b0) ? - sfd___3__h59804[53:2] : - (requestR[159] ? - _theResult___sfd__h61187 : - sfd___3__h59804[53:2]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2852 = - (guard__h83135 == 2'b0) ? - 11'd0 : - (requestR[191] ? _theResult___exp__h83751 : 11'd0) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2878 = - (guard__h83865 == 2'b0 || requestR[191]) ? - x__h83880[10:0] : - _theResult___exp__h84507 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2880 = - (guard__h83865 == 2'b0) ? - x__h83880[10:0] : - (requestR[191] ? _theResult___exp__h84507 : x__h83880[10:0]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2901 = - (guard__h83135 == 2'b0 || requestR[191]) ? - sfd___3__h12218[63:12] : - _theResult___sfd__h83752 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2903 = - (guard__h83135 == 2'b0) ? - sfd___3__h12218[63:12] : - (requestR[191] ? - _theResult___sfd__h83752 : - sfd___3__h12218[63:12]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2919 = - (guard__h83865 == 2'b0 || requestR[191]) ? - sfd___3__h12218[62:11] : - _theResult___sfd__h84508 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2921 = - (guard__h83865 == 2'b0) ? - sfd___3__h12218[62:11] : - (requestR[191] ? - _theResult___sfd__h84508 : - sfd___3__h12218[62:11]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d496 = - (guard__h12228 == 2'b0) ? - 8'd0 : - (requestR[191] ? _theResult___exp__h12644 : 8'd0) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d522 = - (guard__h12758 == 2'b0 || requestR[191]) ? - x__h12773[7:0] : - _theResult___exp__h13197 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d524 = - (guard__h12758 == 2'b0) ? - x__h12773[7:0] : - (requestR[191] ? _theResult___exp__h13197 : x__h12773[7:0]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d545 = - (guard__h12228 == 2'b0 || requestR[191]) ? - sfd___3__h12218[63:41] : - _theResult___sfd__h12645 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d547 = - (guard__h12228 == 2'b0) ? - sfd___3__h12218[63:41] : - (requestR[191] ? - _theResult___sfd__h12645 : - sfd___3__h12218[63:41]) ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d563 = - (guard__h12758 == 2'b0 || requestR[191]) ? - sfd___3__h12218[62:40] : - _theResult___sfd__h13198 ; - assign IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d565 = - (guard__h12758 == 2'b0) ? - sfd___3__h12218[62:40] : - (requestR[191] ? - _theResult___sfd__h13198 : - sfd___3__h12218[62:40]) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2048 = - (sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316[22] || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2017) ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - (IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d2021 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2046) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2052 = - (sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316 != 23'd0 && - !sV2_sfd__h1316[22]) ? - res__h42520 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2051 ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2061 = - IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d2021 ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2060 ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2063 = - (sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316[22]) ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - (IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2017 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2061) ; - assign IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2067 = - (sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316 != 23'd0 && - !sV2_sfd__h1316[22]) ? - res__h42520 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2066 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1764 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1693 : - ((sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - 64'd0 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1762) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1822 = - (sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - 64'd0 : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793[19] ? - 64'hFFFFFFFFFFFFFFFF : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1820) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1911 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1848 : - ((sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - 32'd0 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1909) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1964 = - (sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - 32'd0 : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935[19] ? - 32'hFFFFFFFF : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1962) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2049 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22]) ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2048 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2051 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22] && - sV2_exp__h1315 == 8'd255 && - sV2_sfd__h1316[22]) ? - 64'hFFFFFFFF7FC00000 : - { 32'hFFFFFFFF, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2049 } ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2053 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22]) ? - res__h42283 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2052 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2064 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22]) ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2063 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2066 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22] && - sV2_exp__h1315 == 8'd255 && - sV2_sfd__h1316[22]) ? - 64'hFFFFFFFF7FC00000 : - { 32'hFFFFFFFF, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2064 } ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2068 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22]) ? - res__h42283 : - IF_IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFF_ETC___d2067 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2132 = - (sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - res___1__h50538 : - ((sV1_exp__h1212 == 8'd0) ? res___1__h50557 : res__h50573) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2133 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0) ? - res___1__h50528 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2132 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 = - ((sV1_exp__h1212 == 8'd0) ? - (sV1_sfd__h1213[22] ? - 6'd2 : - (sV1_sfd__h1213[21] ? - 6'd3 : - (sV1_sfd__h1213[20] ? - 6'd4 : - (sV1_sfd__h1213[19] ? - 6'd5 : - (sV1_sfd__h1213[18] ? - 6'd6 : - (sV1_sfd__h1213[17] ? - 6'd7 : - (sV1_sfd__h1213[16] ? - 6'd8 : - (sV1_sfd__h1213[15] ? - 6'd9 : - (sV1_sfd__h1213[14] ? - 6'd10 : - (sV1_sfd__h1213[13] ? - 6'd11 : - (sV1_sfd__h1213[12] ? - 6'd12 : - (sV1_sfd__h1213[11] ? - 6'd13 : - (sV1_sfd__h1213[10] ? - 6'd14 : - (sV1_sfd__h1213[9] ? - 6'd15 : - (sV1_sfd__h1213[8] ? - 6'd16 : - (sV1_sfd__h1213[7] ? - 6'd17 : - (sV1_sfd__h1213[6] ? - 6'd18 : - (sV1_sfd__h1213[5] ? - 6'd19 : - (sV1_sfd__h1213[4] ? - 6'd20 : - (sV1_sfd__h1213[3] ? - 6'd21 : - (sV1_sfd__h1213[2] ? - 6'd22 : - (sV1_sfd__h1213[1] ? - 6'd23 : - (sV1_sfd__h1213[0] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5037 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0) ? - _theResult___snd_fst_sfd__h149185 : - _theResult___fst_sfd__h187312 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5073 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - (sV1_exp__h1212 == 8'd255 || sV1_exp__h1212 == 8'd0) && - sV1_sfd__h1213 == 23'd0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((sV1_exp__h1212 == 8'd0) ? - IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d5053 : - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5071) ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5108 = - (sV1_exp__h1212 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 && - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087[4] : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 && - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104[4] ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5111 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0) ? - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22] : - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5108 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5118 = - (sV1_exp__h1212 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 && - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087[3] : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 && - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 && - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104[3] ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5132 = - (sV1_exp__h1212 == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 || - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087[2] : - !SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 || - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5130 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5144 = - (sV1_exp__h1212 == 8'd0) ? - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 && - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 || - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087[1]) : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 && - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5142 ; - assign IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5156 = - (sV1_exp__h1212 == 8'd0) ? - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 || - !_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 && - _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087[0] : - !SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 || - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5154 ; - assign IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1270 = - sfd__h24253[31] ? - 6'd0 : - (sfd__h24253[30] ? - 6'd1 : - (sfd__h24253[29] ? - 6'd2 : - (sfd__h24253[28] ? - 6'd3 : - (sfd__h24253[27] ? - 6'd4 : - (sfd__h24253[26] ? - 6'd5 : - (sfd__h24253[25] ? - 6'd6 : - (sfd__h24253[24] ? - 6'd7 : - (sfd__h24253[23] ? - 6'd8 : - (sfd__h24253[22] ? - 6'd9 : - (sfd__h24253[21] ? - 6'd10 : - (sfd__h24253[20] ? - 6'd11 : - (sfd__h24253[19] ? - 6'd12 : - (sfd__h24253[18] ? - 6'd13 : - (sfd__h24253[17] ? - 6'd14 : - (sfd__h24253[16] ? - 6'd15 : - (sfd__h24253[15] ? - 6'd16 : - (sfd__h24253[14] ? - 6'd17 : - (sfd__h24253[13] ? - 6'd18 : - (sfd__h24253[12] ? - 6'd19 : - (sfd__h24253[11] ? - 6'd20 : - (sfd__h24253[10] ? - 6'd21 : - (sfd__h24253[9] ? - 6'd22 : - (sfd__h24253[8] ? - 6'd23 : - (sfd__h24253[7] ? - 6'd24 : - (sfd__h24253[6] ? - 6'd25 : - (sfd__h24253[5] ? - 6'd26 : - (sfd__h24253[4] ? - 6'd27 : - (sfd__h24253[3] ? - 6'd28 : - (sfd__h24253[2] ? - 6'd29 : - (sfd__h24253[1] ? - 6'd30 : - (sfd__h24253[0] ? - 6'd31 : - 6'd32))))))))))))))))))))))))))))))) ; - assign IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d2241 = - sfd__h24253[31] ? - 6'd0 : - (sfd__h24253[30] ? - 6'd1 : - (sfd__h24253[29] ? - 6'd2 : - (sfd__h24253[28] ? - 6'd3 : - (sfd__h24253[27] ? - 6'd4 : - (sfd__h24253[26] ? - 6'd5 : - (sfd__h24253[25] ? - 6'd6 : - (sfd__h24253[24] ? - 6'd7 : - (sfd__h24253[23] ? - 6'd8 : - (sfd__h24253[22] ? - 6'd9 : - (sfd__h24253[21] ? - 6'd10 : - (sfd__h24253[20] ? - 6'd11 : - (sfd__h24253[19] ? - 6'd12 : - (sfd__h24253[18] ? - 6'd13 : - (sfd__h24253[17] ? - 6'd14 : - (sfd__h24253[16] ? - 6'd15 : - (sfd__h24253[15] ? - 6'd16 : - (sfd__h24253[14] ? - 6'd17 : - (sfd__h24253[13] ? - 6'd18 : - (sfd__h24253[12] ? - 6'd19 : - (sfd__h24253[11] ? - 6'd20 : - (sfd__h24253[10] ? - 6'd21 : - (sfd__h24253[9] ? - 6'd22 : - (sfd__h24253[8] ? - 6'd23 : - (sfd__h24253[7] ? - 6'd24 : - (sfd__h24253[6] ? - 6'd25 : - (sfd__h24253[5] ? - 6'd26 : - (sfd__h24253[4] ? - 6'd27 : - (sfd__h24253[3] ? - 6'd28 : - (sfd__h24253[2] ? - 6'd29 : - (sfd__h24253[1] ? - 6'd30 : - (sfd__h24253[0] ? - 6'd31 : - 6'd55))))))))))))))))))))))))))))))) ; - assign IF_IF_requestR_3_BIT_191_47_THEN_NEG_requestR__ETC___d404 = - sfd__h2613[63] ? - 7'd0 : - (sfd__h2613[62] ? - 7'd1 : - (sfd__h2613[61] ? - 7'd2 : - (sfd__h2613[60] ? - 7'd3 : - (sfd__h2613[59] ? - 7'd4 : - (sfd__h2613[58] ? - 7'd5 : - (sfd__h2613[57] ? - 7'd6 : - (sfd__h2613[56] ? - 7'd7 : - (sfd__h2613[55] ? - 7'd8 : - (sfd__h2613[54] ? - 7'd9 : - (sfd__h2613[53] ? - 7'd10 : - (sfd__h2613[52] ? - 7'd11 : - (sfd__h2613[51] ? - 7'd12 : - (sfd__h2613[50] ? - 7'd13 : - (sfd__h2613[49] ? - 7'd14 : - (sfd__h2613[48] ? - 7'd15 : - (sfd__h2613[47] ? - 7'd16 : - (sfd__h2613[46] ? - 7'd17 : - (sfd__h2613[45] ? - 7'd18 : - (sfd__h2613[44] ? - 7'd19 : - (sfd__h2613[43] ? - 7'd20 : - (sfd__h2613[42] ? - 7'd21 : - (sfd__h2613[41] ? - 7'd22 : - (sfd__h2613[40] ? - 7'd23 : - (sfd__h2613[39] ? - 7'd24 : - (sfd__h2613[38] ? - 7'd25 : - (sfd__h2613[37] ? - 7'd26 : - (sfd__h2613[36] ? - 7'd27 : - (sfd__h2613[35] ? - 7'd28 : - (sfd__h2613[34] ? - 7'd29 : - (sfd__h2613[33] ? - 7'd30 : - (sfd__h2613[32] ? - 7'd31 : - (sfd__h2613[31] ? - 7'd32 : - (sfd__h2613[30] ? - 7'd33 : - (sfd__h2613[29] ? - 7'd34 : - (sfd__h2613[28] ? - 7'd35 : - (sfd__h2613[27] ? - 7'd36 : - (sfd__h2613[26] ? - 7'd37 : - (sfd__h2613[25] ? - 7'd38 : - (sfd__h2613[24] ? - 7'd39 : - (sfd__h2613[23] ? - 7'd40 : - (sfd__h2613[22] ? - 7'd41 : - (sfd__h2613[21] ? - 7'd42 : - (sfd__h2613[20] ? - 7'd43 : - (sfd__h2613[19] ? - 7'd44 : - (sfd__h2613[18] ? - 7'd45 : - (sfd__h2613[17] ? - 7'd46 : - (sfd__h2613[16] ? - 7'd47 : - (sfd__h2613[15] ? - 7'd48 : - (sfd__h2613[14] ? - 7'd49 : - (sfd__h2613[13] ? - 7'd50 : - (sfd__h2613[12] ? - 7'd51 : - (sfd__h2613[11] ? - 7'd52 : - (sfd__h2613[10] ? - 7'd53 : - (sfd__h2613[9] ? - 7'd54 : - (sfd__h2613[8] ? - 7'd55 : - (sfd__h2613[7] ? - 7'd56 : - (sfd__h2613[6] ? - 7'd57 : - (sfd__h2613[5] ? - 7'd58 : - (sfd__h2613[4] ? - 7'd59 : - (sfd__h2613[3] ? - 7'd60 : - (sfd__h2613[2] ? - 7'd61 : - (sfd__h2613[1] ? - 7'd62 : - (sfd__h2613[0] ? - 7'd63 : - 7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1760 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1733 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1754 ? - ((x__h37862[88:25] == 64'h7FFFFFFFFFFFFFFF) ? - x__h37862[88:25] : - x__h37862[88:25] + 64'd1) : - x__h37862[88:25]) : - 64'd0 ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1762 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048513) ? - ((_theResult_____2__h36897[64:63] == 2'b11) ? - _theResult_____2__h36897[63:0] : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1693) : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731[19] ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1693 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1760) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1785 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048513) ? - _theResult_____2__h36897[64:63] == 2'b11 && - guard__h36895 != 2'd0 : - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1733 || - guard__h37673 != 2'd0) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1820 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1795 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1814 ? - ((x__h39123[88:25] == 64'hFFFFFFFFFFFFFFFF) ? - x__h39123[88:25] : - x__h39123[88:25] + 64'd1) : - x__h39123[88:25]) : - 64'd0 ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1907 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1880 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1901 ? - ((x__h40311[56:25] == 32'h7FFFFFFF) ? - x__h40311[56:25] : - x__h40311[56:25] + 32'd1) : - x__h40311[56:25]) : - 32'd0 ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1909 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048545) ? - ((_theResult_____2__h39570[32:31] == 2'b11) ? - _theResult_____2__h39570[31:0] : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1848) : - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878[19] ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1848 : - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1907) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1927 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048545) ? - _theResult_____2__h39570[32:31] == 2'b11 && - guard__h39568 != 2'd0 : - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1880 || - guard__h40122 != 2'd0) ; - assign IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1962 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1937 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1956 ? - ((x__h41334[56:25] == 32'hFFFFFFFF) ? - x__h41334[56:25] : - x__h41334[56:25] + 32'd1) : - x__h41334[56:25]) : - 32'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2684 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2657 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2678 ? - ((x__h72215[85:54] == 32'h7FFFFFFF) ? - x__h72215[85:54] : - x__h72215[85:54] + 32'd1) : - x__h72215[85:54]) : - 32'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2686 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777185) ? - ((_theResult_____2__h71474[32:31] == 2'b11) ? - _theResult_____2__h71474[31:0] : - IF_requestR_3_BIT_191_47_THEN_2147483648_ELSE__ETC___d2617) : - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655[23] ? - IF_requestR_3_BIT_191_47_THEN_2147483648_ELSE__ETC___d2617 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2684) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2710 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777185) ? - _theResult_____2__h71474[32:31] == 2'b11 && - guard__h71472 != 2'd0 : - !NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2657 || - guard__h72026 != 2'd0) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2745 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2720 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2739 ? - ((x__h73238[85:54] == 32'hFFFFFFFF) ? - x__h73238[85:54] : - x__h73238[85:54] + 32'd1) : - x__h73238[85:54]) : - 32'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3169 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3142 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3163 ? - ((x__h97073[117:54] == 64'h7FFFFFFFFFFFFFFF) ? - x__h97073[117:54] : - x__h97073[117:54] + 64'd1) : - x__h97073[117:54]) : - 64'd0 ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3171 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777153) ? - ((_theResult_____2__h96108[64:63] == 2'b11) ? - _theResult_____2__h96108[63:0] : - IF_requestR_3_BIT_191_47_THEN_9223372036854775_ETC___d3110) : - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140[23] ? - IF_requestR_3_BIT_191_47_THEN_9223372036854775_ETC___d3110 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3169) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3188 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777153) ? - _theResult_____2__h96108[64:63] == 2'b11 && - guard__h96106 != 2'd0 : - !NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3142 || - guard__h96884 != 2'd0) ; - assign IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3223 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3198 ? - (IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3217 ? - ((x__h98317[117:54] == 64'hFFFFFFFFFFFFFFFF) ? - x__h98317[117:54] : - x__h98317[117:54] + 64'd1) : - x__h98317[117:54]) : - 64'd0 ; - assign IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d2301 = - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247) ? - requestR[159] : - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2300 ; - assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BI_ETC___d5053 = - (!_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 || - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 || - _theResult___fst_exp__h168111 == 11'd2047) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard60150_0b0_requestR_BITS_191_TO_160_E_ETC__q162 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q163) ; - assign IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2046 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2045 ? - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } : - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 ; - assign IF_NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFF_ETC___d2060 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2045 ? - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 : - { requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2041 = - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2030 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2032 : - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2035 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 && - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2037 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d4891 = - ((SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q153[10], - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q153 }) - - 12'd3074 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5071 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 ? - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_19_ETC___d5061 : - IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFF_ETC___d5069) : - requestR[191:160] == 32'hFFFFFFFF && requestR[159] ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5130 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104[2] : - _theResult___fst_exp__h187296 == 11'd2047 && - _theResult___fst_sfd__h187297 == 52'd0 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5142 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104[1] : - _theResult___fst_exp__h186515 == 11'd0 && - guard__h178525 != 2'b0 ; - assign IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d5154 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104[0] : - _theResult___fst_exp__h186515 != 11'd2047 && - guard__h178525 != 2'b0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4058 = - ((SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q121[7], - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q121 }) - - 9'd386 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4262 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - ((_theResult___fst_exp__h136404 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard28178_0b0_requestR_BIT_191_0b1_reque_ETC__q144 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q145)) : - ((_theResult___fst_exp__h145119 == 8'd255) ? - requestR[191] : - ((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard37042_0b0_requestR_BIT_191_0b1_reque_ETC__q146 : - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q147)) ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4340 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311[2] : - _theResult___fst_exp__h145697 == 8'd255 && - _theResult___fst_sfd__h145698 == 23'd0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4353 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311[1] : - _theResult___fst_exp__h145119 == 8'd0 && - guard__h137042 != 2'b0 ; - assign IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4366 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311[0] : - _theResult___fst_exp__h145119 != 8'd255 && - guard__h137042 != 2'b0 ; - assign IF_requestR_3_BITS_126_TO_116_167_EQ_2047_168__ETC___d5215 = - (requestR[126:116] == 11'd2047 && requestR[115] || - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5184) ? - requestR[191:128] : - (requestR_3_BITS_126_TO_116_167_EQ_0_181_AND_re_ETC___d5188 ? - requestR[127:64] : - res__h192322) ; - assign IF_requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_ETC___d2021 = - sV2_exp__h1315 == 8'd0 && sV2_sfd__h1316 == 23'd0 && - requestR[127:96] == 32'hFFFFFFFF && - requestR[95] && - sV1_exp__h1212 == 8'd0 && - sV1_sfd__h1213 == 23'd0 && - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ; - assign IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1391 = - (requestR[159:128] == 32'd0 || - !sfd__h24253[31] && !sfd__h24253[30] && !sfd__h24253[29] && - !sfd__h24253[28] && - !sfd__h24253[27] && - !sfd__h24253[26] && - !sfd__h24253[25] && - !sfd__h24253[24] && - !sfd__h24253[23] && - !sfd__h24253[22] && - !sfd__h24253[21] && - !sfd__h24253[20] && - !sfd__h24253[19] && - !sfd__h24253[18] && - !sfd__h24253[17] && - !sfd__h24253[16] && - !sfd__h24253[15] && - !sfd__h24253[14] && - !sfd__h24253[13] && - !sfd__h24253[12] && - !sfd__h24253[11] && - !sfd__h24253[10] && - !sfd__h24253[9] && - !sfd__h24253[8] && - !sfd__h24253[7] && - !sfd__h24253[6] && - !sfd__h24253[5] && - !sfd__h24253[4] && - !sfd__h24253[3] && - !sfd__h24253[2] && - !sfd__h24253[1] && - !sfd__h24253[0]) ? - 8'd0 : - _theResult___snd_fst_exp__h30242 ; - assign IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1613 = - (requestR[159:128] == 32'd0 || - !requestR[159] && - NOT_requestR_3_BIT_158_31_32_AND_NOT_requestR__ETC___d822) ? - 8'd0 : - _theResult___snd_fst_exp__h36356 ; - assign IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2398 = - (requestR[159:128] == 32'd0 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247) ? - 52'd0 : - _theResult___snd_fst_sfd__h61290 ; - assign IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2580 = - (requestR[159:128] == 32'd0 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 || - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460) ? - 52'd0 : - _theResult___snd_fst_sfd__h70929 ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d2747 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 32'd0 : - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718[23] ? - 32'hFFFFFFFF : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2745) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d3225 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 64'd0 : - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196[23] ? - 64'hFFFFFFFFFFFFFFFF : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3223) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5228 = - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5184 ? - requestR[127:64] : - (requestR_3_BITS_126_TO_116_167_EQ_0_181_AND_re_ETC___d5188 ? - requestR[191:128] : - res__h196815) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5294 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - res___1__h204675 : - ((requestR[190:180] == 11'd0) ? - res___1__h204694 : - res__h204710) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 = - ((requestR[190:180] == 11'd0) ? - (requestR[179] ? - 6'd2 : - (requestR[178] ? - 6'd3 : - (requestR[177] ? - 6'd4 : - (requestR[176] ? - 6'd5 : - (requestR[175] ? - 6'd6 : - (requestR[174] ? - 6'd7 : - (requestR[173] ? - 6'd8 : - (requestR[172] ? - 6'd9 : - (requestR[171] ? - 6'd10 : - (requestR[170] ? - 6'd11 : - (requestR[169] ? - 6'd12 : - (requestR[168] ? - 6'd13 : - (requestR[167] ? - 6'd14 : - (requestR[166] ? - 6'd15 : - (requestR[165] ? - 6'd16 : - (requestR[164] ? - 6'd17 : - (requestR[163] ? - 6'd18 : - (requestR[162] ? - 6'd19 : - (requestR[161] ? - 6'd20 : - (requestR[160] ? - 6'd21 : - (requestR[159] ? - 6'd22 : - (requestR[158] ? - 6'd23 : - (requestR[157] ? - 6'd24 : - (requestR[156] ? - 6'd25 : - (requestR[155] ? - 6'd26 : - (requestR[154] ? - 6'd27 : - (requestR[153] ? - 6'd28 : - (requestR[152] ? - 6'd29 : - (requestR[151] ? - 6'd30 : - (requestR[150] ? - 6'd31 : - (requestR[149] ? - 6'd32 : - (requestR[148] ? - 6'd33 : - (requestR[147] ? - 6'd34 : - (requestR[146] ? - 6'd35 : - (requestR[145] ? - 6'd36 : - (requestR[144] ? - 6'd37 : - (requestR[143] ? - 6'd38 : - (requestR[142] ? - 6'd39 : - (requestR[141] ? - 6'd40 : - (requestR[140] ? - 6'd41 : - (requestR[139] ? - 6'd42 : - (requestR[138] ? - 6'd43 : - (requestR[137] ? - 6'd44 : - (requestR[136] ? - 6'd45 : - (requestR[135] ? - 6'd46 : - (requestR[134] ? - 6'd47 : - (requestR[133] ? - 6'd48 : - (requestR[132] ? - 6'd49 : - (requestR[131] ? - 6'd50 : - (requestR[130] ? - 6'd51 : - (requestR[129] ? - 6'd52 : - (requestR[128] ? - 6'd53 : - 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4264 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 ? - IF_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_9_ETC___d4244 : - requestR[191]) : - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 ? - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4262 : - requestR[191]) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4315 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4297 : - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 && - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311[4] ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4326 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4322 : - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 && - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311[3] ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4342 = - (requestR[190:180] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4334 : - !SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 || - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4340 ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4355 = - (requestR[190:180] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4349 : - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 && - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4353 ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4368 = - (requestR[190:180] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4362 : - !SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 || - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4366 ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d2688 = - (requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0) ? - IF_requestR_3_BIT_191_47_THEN_2147483648_ELSE__ETC___d2617 : - ((requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 32'd0 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2686) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d3173 = - (requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0) ? - IF_requestR_3_BIT_191_47_THEN_9223372036854775_ETC___d3110 : - ((requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 64'd0 : - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3171) ; - assign IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d4224 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - _theResult___snd_fst_sfd__h102768 : - _theResult___fst_sfd__h145713 ; - assign IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d2890 = - (requestR[191:128] == 64'd0 || - !sfd__h2613[63] && !sfd__h2613[62] && !sfd__h2613[61] && - !sfd__h2613[60] && - !sfd__h2613[59] && - !sfd__h2613[58] && - !sfd__h2613[57] && - !sfd__h2613[56] && - !sfd__h2613[55] && - !sfd__h2613[54] && - !sfd__h2613[53] && - !sfd__h2613[52] && - !sfd__h2613[51] && - !sfd__h2613[50] && - !sfd__h2613[49] && - !sfd__h2613[48] && - !sfd__h2613[47] && - !sfd__h2613[46] && - !sfd__h2613[45] && - !sfd__h2613[44] && - !sfd__h2613[43] && - !sfd__h2613[42] && - !sfd__h2613[41] && - !sfd__h2613[40] && - !sfd__h2613[39] && - !sfd__h2613[38] && - !sfd__h2613[37] && - !sfd__h2613[36] && - !sfd__h2613[35] && - !sfd__h2613[34] && - !sfd__h2613[33] && - !sfd__h2613[32] && - !sfd__h2613[31] && - !sfd__h2613[30] && - !sfd__h2613[29] && - !sfd__h2613[28] && - !sfd__h2613[27] && - !sfd__h2613[26] && - !sfd__h2613[25] && - !sfd__h2613[24] && - !sfd__h2613[23] && - !sfd__h2613[22] && - !sfd__h2613[21] && - !sfd__h2613[20] && - !sfd__h2613[19] && - !sfd__h2613[18] && - !sfd__h2613[17] && - !sfd__h2613[16] && - !sfd__h2613[15] && - !sfd__h2613[14] && - !sfd__h2613[13] && - !sfd__h2613[12] && - !sfd__h2613[11] && - !sfd__h2613[10] && - !sfd__h2613[9] && - !sfd__h2613[8] && - !sfd__h2613[7] && - !sfd__h2613[6] && - !sfd__h2613[5] && - !sfd__h2613[4] && - !sfd__h2613[3] && - !sfd__h2613[2] && - !sfd__h2613[1] && - !sfd__h2613[0]) ? - 11'd0 : - _theResult___snd_fst_exp__h84616 ; - assign IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d534 = - (requestR[191:128] == 64'd0 || - !sfd__h2613[63] && !sfd__h2613[62] && !sfd__h2613[61] && - !sfd__h2613[60] && - !sfd__h2613[59] && - !sfd__h2613[58] && - !sfd__h2613[57] && - !sfd__h2613[56] && - !sfd__h2613[55] && - !sfd__h2613[54] && - !sfd__h2613[53] && - !sfd__h2613[52] && - !sfd__h2613[51] && - !sfd__h2613[50] && - !sfd__h2613[49] && - !sfd__h2613[48] && - !sfd__h2613[47] && - !sfd__h2613[46] && - !sfd__h2613[45] && - !sfd__h2613[44] && - !sfd__h2613[43] && - !sfd__h2613[42] && - !sfd__h2613[41] && - !sfd__h2613[40] && - !sfd__h2613[39] && - !sfd__h2613[38] && - !sfd__h2613[37] && - !sfd__h2613[36] && - !sfd__h2613[35] && - !sfd__h2613[34] && - !sfd__h2613[33] && - !sfd__h2613[32] && - !sfd__h2613[31] && - !sfd__h2613[30] && - !sfd__h2613[29] && - !sfd__h2613[28] && - !sfd__h2613[27] && - !sfd__h2613[26] && - !sfd__h2613[25] && - !sfd__h2613[24] && - !sfd__h2613[23] && - !sfd__h2613[22] && - !sfd__h2613[21] && - !sfd__h2613[20] && - !sfd__h2613[19] && - !sfd__h2613[18] && - !sfd__h2613[17] && - !sfd__h2613[16] && - !sfd__h2613[15] && - !sfd__h2613[14] && - !sfd__h2613[13] && - !sfd__h2613[12] && - !sfd__h2613[11] && - !sfd__h2613[10] && - !sfd__h2613[9] && - !sfd__h2613[8] && - !sfd__h2613[7] && - !sfd__h2613[6] && - !sfd__h2613[5] && - !sfd__h2613[4] && - !sfd__h2613[3] && - !sfd__h2613[2] && - !sfd__h2613[1] && - !sfd__h2613[0]) ? - 8'd0 : - _theResult___snd_fst_exp__h13306 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692 = - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) && - sV1_exp__h1212 == 8'd255 && - sV1_sfd__h1213 == 23'd0 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1693 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'h8000000000000000 : - 64'h7FFFFFFFFFFFFFFF ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696 = - sV1_exp__h1212 - 8'd127 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - -b__h36962 : - b__h36962 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1824 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd0 : - ((sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0) ? - 64'hFFFFFFFFFFFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1822) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1831 = - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0 || - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1795 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1814 && - x__h39123[88:25] == 64'hFFFFFFFFFFFFFFFF) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1842 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1831, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1836 } == - 5'd0 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1831 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1848 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 32'h80000000 : - 32'h7FFFFFFF ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - -b__h39635 : - b__h39635 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1966 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 32'd0 : - ((sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0) ? - 32'hFFFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1964) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1974 = - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0 || - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1937 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1956 && - x__h41334[56:25] == 32'hFFFFFFFF) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1985 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1974, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1979 } == - 5'd0 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1974 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2007 = - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22] && - sV2_exp__h1315 == 8'd255 && - sV2_sfd__h1316 != 23'd0 && - !sV2_sfd__h1316[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2017 = - sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159] && - sV2_exp__h1315 == 8'd0 && - sV2_sfd__h1316 == 23'd0 && - (requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2030 = - sV1_exp__h1212 < sV2_exp__h1315 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 = - sV1_exp__h1212 == sV2_exp__h1315 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2032 = - sV1_sfd__h1213 < sV2_sfd__h1316 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2035 = - sV1_exp__h1212 <= sV2_exp__h1315 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2037 = - sV1_sfd__h1213 <= sV2_sfd__h1316 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2055 = - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22] || - sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316 != 23'd0 && - !sV2_sfd__h1316[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2088 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2055 || - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22] || - sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316[22] ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2099 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2035 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2037) && - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2030 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 || - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2032) ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2103 = - sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0 && - sV2_exp__h1315 == 8'd0 && - sV2_sfd__h1316 == 23'd0 || - NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d2102 ; - assign IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[158:128] : - 31'h7FC00000 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1722 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h36895 == 2'b10) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[24] : - guard__h36895 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h36895 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[88] && - guard__h36895 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1754 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h37673 == 2'b10) ? - x__h37862[25] : - guard__h37673 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h37673 != 2'd0 : - requestR[194:192] == 3'h1 && x__h37862[88] && - guard__h37673 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1814 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h38902 == 2'b10) ? - x__h39123[25] : - guard__h38902 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h38902 != 2'd0 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1869 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h39568 == 2'b10) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[24] : - guard__h39568 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h39568 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[56] && - guard__h39568 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1901 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h40122 == 2'b10) ? - x__h40311[25] : - guard__h40122 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h40122 != 2'd0 : - requestR[194:192] == 3'h1 && x__h40311[56] && - guard__h40122 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1956 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h41113 == 2'b10) ? - x__h41334[25] : - guard__h41113 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h41113 != 2'd0 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2646 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h71472 == 2'b10) ? - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[53] : - guard__h71472 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h71472 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[85] && - guard__h71472 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2678 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h72026 == 2'b10) ? - x__h72215[54] : - guard__h72026 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h72026 != 2'd0 : - requestR[194:192] == 3'h1 && x__h72215[85] && - guard__h72026 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2739 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h73017 == 2'b10) ? - x__h73238[54] : - guard__h73017 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h73017 != 2'd0 ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3131 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h96106 == 2'b10) ? - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[53] : - guard__h96106 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h96106 != 2'd0 : - requestR[194:192] == 3'h1 && - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[117] && - guard__h96106 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3163 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h96884 == 2'b10) ? - x__h97073[54] : - guard__h96884 == 2'b11) : - ((requestR[194:192] == 3'h3) ? - guard__h96884 != 2'd0 : - requestR[194:192] == 3'h1 && x__h97073[117] && - guard__h96884 != 2'd0) ; - assign IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3217 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - ((guard__h98096 == 2'b10) ? - x__h98317[54] : - guard__h98096 == 2'b11) : - requestR[194:192] == 3'h3 && guard__h98096 != 2'd0 ; - assign IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1524 = - requestR[159] ? - 6'd0 : - (requestR[158] ? - 6'd1 : - (requestR[157] ? - 6'd2 : - (requestR[156] ? - 6'd3 : - (requestR[155] ? - 6'd4 : - (requestR[154] ? - 6'd5 : - (requestR[153] ? - 6'd6 : - (requestR[152] ? - 6'd7 : - (requestR[151] ? - 6'd8 : - (requestR[150] ? - 6'd9 : - (requestR[149] ? - 6'd10 : - (requestR[148] ? - 6'd11 : - (requestR[147] ? - 6'd12 : - (requestR[146] ? - 6'd13 : - (requestR[145] ? - 6'd14 : - (requestR[144] ? - 6'd15 : - (requestR[143] ? - 6'd16 : - (requestR[142] ? - 6'd17 : - (requestR[141] ? - 6'd18 : - (requestR[140] ? - 6'd19 : - (requestR[139] ? - 6'd20 : - (requestR[138] ? - 6'd21 : - (requestR[137] ? - 6'd22 : - (requestR[136] ? - 6'd23 : - (requestR[135] ? - 6'd24 : - (requestR[134] ? - 6'd25 : - (requestR[133] ? - 6'd26 : - (requestR[132] ? - 6'd27 : - (requestR[131] ? - 6'd28 : - (requestR[130] ? - 6'd29 : - (requestR[129] ? - 6'd30 : - (requestR[128] ? - 6'd31 : - 6'd32))))))))))))))))))))))))))))))) ; - assign IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d2455 = - requestR[159] ? - 6'd0 : - (requestR[158] ? - 6'd1 : - (requestR[157] ? - 6'd2 : - (requestR[156] ? - 6'd3 : - (requestR[155] ? - 6'd4 : - (requestR[154] ? - 6'd5 : - (requestR[153] ? - 6'd6 : - (requestR[152] ? - 6'd7 : - (requestR[151] ? - 6'd8 : - (requestR[150] ? - 6'd9 : - (requestR[149] ? - 6'd10 : - (requestR[148] ? - 6'd11 : - (requestR[147] ? - 6'd12 : - (requestR[146] ? - 6'd13 : - (requestR[145] ? - 6'd14 : - (requestR[144] ? - 6'd15 : - (requestR[143] ? - 6'd16 : - (requestR[142] ? - 6'd17 : - (requestR[141] ? - 6'd18 : - (requestR[140] ? - 6'd19 : - (requestR[139] ? - 6'd20 : - (requestR[138] ? - 6'd21 : - (requestR[137] ? - 6'd22 : - (requestR[136] ? - 6'd23 : - (requestR[135] ? - 6'd24 : - (requestR[134] ? - 6'd25 : - (requestR[133] ? - 6'd26 : - (requestR[132] ? - 6'd27 : - (requestR[131] ? - 6'd28 : - (requestR[130] ? - 6'd29 : - (requestR[129] ? - 6'd30 : - (requestR[128] ? - 6'd31 : - 6'd55))))))))))))))))))))))))))))))) ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1472 = - (sfd__h24253[31] || sfd__h24253[30] || sfd__h24253[29] || - sfd__h24253[28] || - sfd__h24253[27] || - sfd__h24253[26] || - sfd__h24253[25] || - sfd__h24253[24] || - sfd__h24253[23] || - sfd__h24253[22] || - sfd__h24253[21] || - sfd__h24253[20] || - sfd__h24253[19] || - sfd__h24253[18] || - sfd__h24253[17] || - sfd__h24253[16] || - sfd__h24253[15] || - sfd__h24253[14] || - sfd__h24253[13] || - sfd__h24253[12] || - sfd__h24253[11] || - sfd__h24253[10] || - sfd__h24253[9] || - sfd__h24253[8] || - sfd__h24253[7] || - sfd__h24253[6] || - sfd__h24253[5] || - sfd__h24253[4] || - sfd__h24253[3] || - sfd__h24253[2] || - sfd__h24253[1] || - sfd__h24253[0]) && - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 && - _theResult___fst_exp__h30233 == 8'd255 && - _theResult___fst_sfd__h30234 == 23'd0) ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1475 = - (sfd__h24253[31] || sfd__h24253[30] || sfd__h24253[29] || - sfd__h24253[28] || - sfd__h24253[27] || - sfd__h24253[26] || - sfd__h24253[25] || - sfd__h24253[24] || - sfd__h24253[23] || - sfd__h24253[22] || - sfd__h24253[21] || - sfd__h24253[20] || - sfd__h24253[19] || - sfd__h24253[18] || - sfd__h24253[17] || - sfd__h24253[16] || - sfd__h24253[15] || - sfd__h24253[14] || - sfd__h24253[13] || - sfd__h24253[12] || - sfd__h24253[11] || - sfd__h24253[10] || - sfd__h24253[9] || - sfd__h24253[8] || - sfd__h24253[7] || - sfd__h24253[6] || - sfd__h24253[5] || - sfd__h24253[4] || - sfd__h24253[3] || - sfd__h24253[2] || - sfd__h24253[1] || - sfd__h24253[0]) && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 ; - assign IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1484 = - (sfd__h24253[31] || sfd__h24253[30] || sfd__h24253[29] || - sfd__h24253[28] || - sfd__h24253[27] || - sfd__h24253[26] || - sfd__h24253[25] || - sfd__h24253[24] || - sfd__h24253[23] || - sfd__h24253[22] || - sfd__h24253[21] || - sfd__h24253[20] || - sfd__h24253[19] || - sfd__h24253[18] || - sfd__h24253[17] || - sfd__h24253[16] || - sfd__h24253[15] || - sfd__h24253[14] || - sfd__h24253[13] || - sfd__h24253[12] || - sfd__h24253[11] || - sfd__h24253[10] || - sfd__h24253[9] || - sfd__h24253[8] || - sfd__h24253[7] || - sfd__h24253[6] || - sfd__h24253[5] || - sfd__h24253[4] || - sfd__h24253[3] || - sfd__h24253[2] || - sfd__h24253[1] || - sfd__h24253[0]) && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 && - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1481 ; - assign IF_requestR_3_BIT_191_47_THEN_0_ELSE_IF_reques_ETC___d920 = - requestR[191] ? - 7'd0 : - (requestR[190] ? - 7'd1 : - (requestR[189] ? - 7'd2 : - (requestR[188] ? - 7'd3 : - (requestR[187] ? - 7'd4 : - (requestR[186] ? - 7'd5 : - (requestR[185] ? - 7'd6 : - (requestR[184] ? - 7'd7 : - (requestR[183] ? - 7'd8 : - (requestR[182] ? - 7'd9 : - (requestR[181] ? - 7'd10 : - (requestR[180] ? - 7'd11 : - (requestR[179] ? - 7'd12 : - (requestR[178] ? - 7'd13 : - (requestR[177] ? - 7'd14 : - (requestR[176] ? - 7'd15 : - (requestR[175] ? - 7'd16 : - (requestR[174] ? - 7'd17 : - (requestR[173] ? - 7'd18 : - (requestR[172] ? - 7'd19 : - (requestR[171] ? - 7'd20 : - (requestR[170] ? - 7'd21 : - (requestR[169] ? - 7'd22 : - (requestR[168] ? - 7'd23 : - (requestR[167] ? - 7'd24 : - (requestR[166] ? - 7'd25 : - (requestR[165] ? - 7'd26 : - (requestR[164] ? - 7'd27 : - (requestR[163] ? - 7'd28 : - (requestR[162] ? - 7'd29 : - (requestR[161] ? - 7'd30 : - (requestR[160] ? - 7'd31 : - (requestR[159] ? - 7'd32 : - (requestR[158] ? - 7'd33 : - (requestR[157] ? - 7'd34 : - (requestR[156] ? - 7'd35 : - (requestR[155] ? - 7'd36 : - (requestR[154] ? - 7'd37 : - (requestR[153] ? - 7'd38 : - (requestR[152] ? - 7'd39 : - (requestR[151] ? - 7'd40 : - (requestR[150] ? - 7'd41 : - (requestR[149] ? - 7'd42 : - (requestR[148] ? - 7'd43 : - (requestR[147] ? - 7'd44 : - (requestR[146] ? - 7'd45 : - (requestR[145] ? - 7'd46 : - (requestR[144] ? - 7'd47 : - (requestR[143] ? - 7'd48 : - (requestR[142] ? - 7'd49 : - (requestR[141] ? - 7'd50 : - (requestR[140] ? - 7'd51 : - (requestR[139] ? - 7'd52 : - (requestR[138] ? - 7'd53 : - (requestR[137] ? - 7'd54 : - (requestR[136] ? - 7'd55 : - (requestR[135] ? - 7'd56 : - (requestR[134] ? - 7'd57 : - (requestR[133] ? - 7'd58 : - (requestR[132] ? - 7'd59 : - (requestR[131] ? - 7'd60 : - (requestR[130] ? - 7'd61 : - (requestR[129] ? - 7'd62 : - (requestR[128] ? - 7'd63 : - 7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ; - assign IF_requestR_3_BIT_191_47_THEN_2147483648_ELSE__ETC___d2617 = - requestR[191] ? 32'h80000000 : 32'h7FFFFFFF ; - assign IF_requestR_3_BIT_191_47_THEN_9223372036854775_ETC___d3110 = - requestR[191] ? 64'h8000000000000000 : 64'h7FFFFFFFFFFFFFFF ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629 = - requestR[191] ? -b__h71539 : b__h71539 ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114 = - requestR[191] ? -b__h96173 : b__h96173 ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2939 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - (!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 || - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 && - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 && - _theResult___fst_exp__h84607 == 11'd2047 && - _theResult___fst_sfd__h84608 == 52'd0) ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2942 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2951 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 && - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 && - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2948 ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d647 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - (!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 || - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 && - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 && - _theResult___fst_exp__h13297 == 8'd255 && - _theResult___fst_sfd__h13298 == 23'd0) ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d650 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 ; - assign IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d659 = - (sfd__h2613[63] || sfd__h2613[62] || sfd__h2613[61] || - sfd__h2613[60] || - sfd__h2613[59] || - sfd__h2613[58] || - sfd__h2613[57] || - sfd__h2613[56] || - sfd__h2613[55] || - sfd__h2613[54] || - sfd__h2613[53] || - sfd__h2613[52] || - sfd__h2613[51] || - sfd__h2613[50] || - sfd__h2613[49] || - sfd__h2613[48] || - sfd__h2613[47] || - sfd__h2613[46] || - sfd__h2613[45] || - sfd__h2613[44] || - sfd__h2613[43] || - sfd__h2613[42] || - sfd__h2613[41] || - sfd__h2613[40] || - sfd__h2613[39] || - sfd__h2613[38] || - sfd__h2613[37] || - sfd__h2613[36] || - sfd__h2613[35] || - sfd__h2613[34] || - sfd__h2613[33] || - sfd__h2613[32] || - sfd__h2613[31] || - sfd__h2613[30] || - sfd__h2613[29] || - sfd__h2613[28] || - sfd__h2613[27] || - sfd__h2613[26] || - sfd__h2613[25] || - sfd__h2613[24] || - sfd__h2613[23] || - sfd__h2613[22] || - sfd__h2613[21] || - sfd__h2613[20] || - sfd__h2613[19] || - sfd__h2613[18] || - sfd__h2613[17] || - sfd__h2613[16] || - sfd__h2613[15] || - sfd__h2613[14] || - sfd__h2613[13] || - sfd__h2613[12] || - sfd__h2613[11] || - sfd__h2613[10] || - sfd__h2613[9] || - sfd__h2613[8] || - sfd__h2613[7] || - sfd__h2613[6] || - sfd__h2613[5] || - sfd__h2613[4] || - sfd__h2613[3] || - sfd__h2613[2] || - sfd__h2613[1] || - sfd__h2613[0]) && - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 && - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 && - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d656 ; - assign IF_requestR_3_BIT_191_47_THEN_NOT_requestR_3_B_ETC___d5208 = - requestR[191] ? - !requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5197 || - requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 && - !requestR_3_BITS_179_TO_128_610_ULE_requestR_3__ETC___d5200 : - requestR_3_BITS_190_TO_180_608_ULT_requestR_3__ETC___d5204 || - requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 && - requestR_3_BITS_179_TO_128_610_ULT_requestR_3__ETC___d5205 ; - assign IF_sfd___32218_BIT_10_THEN_2_ELSE_0__q9 = - sfd___3__h12218[10] ? 2'd2 : 2'd0 ; - assign IF_sfd___32218_BIT_11_THEN_2_ELSE_0__q8 = - sfd___3__h12218[11] ? 2'd2 : 2'd0 ; - assign IF_sfd___32218_BIT_39_THEN_2_ELSE_0__q7 = - sfd___3__h12218[39] ? 2'd2 : 2'd0 ; - assign IF_sfd___32218_BIT_40_THEN_2_ELSE_0__q6 = - sfd___3__h12218[40] ? 2'd2 : 2'd0 ; - assign IF_sfd___32785_BIT_10_THEN_2_ELSE_0__q25 = - sfd___3__h22785[10] ? 2'd2 : 2'd0 ; - assign IF_sfd___32785_BIT_11_THEN_2_ELSE_0__q24 = - sfd___3__h22785[11] ? 2'd2 : 2'd0 ; - assign IF_sfd___32785_BIT_39_THEN_2_ELSE_0__q23 = - sfd___3__h22785[39] ? 2'd2 : 2'd0 ; - assign IF_sfd___32785_BIT_40_THEN_2_ELSE_0__q22 = - sfd___3__h22785[40] ? 2'd2 : 2'd0 ; - assign IF_sfd___35273_BIT_7_THEN_2_ELSE_0__q53 = - sfd___3__h35273[7] ? 2'd2 : 2'd0 ; - assign IF_sfd___35273_BIT_8_THEN_2_ELSE_0__q52 = - sfd___3__h35273[8] ? 2'd2 : 2'd0 ; - assign IF_sfd___39157_BIT_7_THEN_2_ELSE_0__q39 = - sfd___3__h29157[7] ? 2'd2 : 2'd0 ; - assign IF_sfd___39157_BIT_8_THEN_2_ELSE_0__q38 = - sfd___3__h29157[8] ? 2'd2 : 2'd0 ; - assign IF_sfd___39445_BIT_1_THEN_2_ELSE_0__q82 = - sfd___3__h69445[1] ? 2'd2 : 2'd0 ; - assign IF_sfd___39445_BIT_2_THEN_2_ELSE_0__q81 = - sfd___3__h69445[2] ? 2'd2 : 2'd0 ; - assign IF_sfd___39804_BIT_1_THEN_2_ELSE_0__q68 = - sfd___3__h59804[1] ? 2'd2 : 2'd0 ; - assign IF_sfd___39804_BIT_2_THEN_2_ELSE_0__q67 = - sfd___3__h59804[2] ? 2'd2 : 2'd0 ; - assign IF_sfdin18545_BIT_33_THEN_2_ELSE_0__q115 = - sfdin__h118545[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin36398_BIT_33_THEN_2_ELSE_0__q120 = - sfdin__h136398[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin77678_BIT_4_THEN_2_ELSE_0__q152 = - sfdin__h177678[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd27188_BIT_33_THEN_2_ELSE_0__q117 = - _theResult___snd__h127188[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd45065_BIT_33_THEN_2_ELSE_0__q123 = - _theResult___snd__h145065[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd68062_BIT_4_THEN_2_ELSE_0__q149 = - _theResult___snd__h168062[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd86461_BIT_4_THEN_2_ELSE_0__q155 = - _theResult___snd__h186461[4] ? 2'd2 : 2'd0 ; - assign IF_x0311_BIT_24_THEN_2_ELSE_0__q65 = x__h40311[24] ? 2'd2 : 2'd0 ; - assign IF_x1334_BIT_24_THEN_2_ELSE_0__q66 = x__h41334[24] ? 2'd2 : 2'd0 ; - assign IF_x2215_BIT_53_THEN_2_ELSE_0__q92 = x__h72215[53] ? 2'd2 : 2'd0 ; - assign IF_x3238_BIT_53_THEN_2_ELSE_0__q93 = x__h73238[53] ? 2'd2 : 2'd0 ; - assign IF_x7073_BIT_53_THEN_2_ELSE_0__q112 = x__h97073[53] ? 2'd2 : 2'd0 ; - assign IF_x7862_BIT_24_THEN_2_ELSE_0__q63 = x__h37862[24] ? 2'd2 : 2'd0 ; - assign IF_x8317_BIT_53_THEN_2_ELSE_0__q113 = x__h98317[53] ? 2'd2 : 2'd0 ; - assign IF_x9123_BIT_24_THEN_2_ELSE_0__q64 = x__h39123[24] ? 2'd2 : 2'd0 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 = - -{ {12{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696[7]}}, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696 } ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1730 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 + - 20'd64 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1730 - - 20'd2 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1733 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731 ^ - 20'h80000) <= - 20'd524352 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1730 - - 20'd1 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1795 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793 ^ - 20'h80000) <= - 20'd524352 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1877 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 + - 20'd32 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1877 - - 20'd2 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1880 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878 ^ - 20'h80000) <= - 20'd524320 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935 = - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1877 - - 20'd1 ; - assign NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1937 = - (NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935 ^ - 20'h80000) <= - 20'd524320 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 = - -{ {13{requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620[10]}}, - requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620 } ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2654 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 + - 24'd32 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2654 - - 24'd2 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2657 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655 ^ - 24'h800000) <= - 24'd8388640 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2654 - - 24'd1 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2720 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718 ^ - 24'h800000) <= - 24'd8388640 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3139 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 + - 24'd64 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3139 - - 24'd2 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3142 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140 ^ - 24'h800000) <= - 24'd8388672 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196 = - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3139 - - 24'd1 ; - assign NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3198 = - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196 ^ - 24'h800000) <= - 24'd8388672 ; - assign NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4334 = - !_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 || - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282[2] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179__ETC___d4362 = - !_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 || - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282[0] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294[0]) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1774 = - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - ((NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048513) ? - _theResult_____2__h36897[64:63] != 2'b11 : - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1733 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1754 && - x__h37862[88:25] == 64'h7FFFFFFFFFFFFFFF) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1836 = - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1795 || - guard__h38902 != 2'd0) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1919 = - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - ((NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1698 == - 20'd1048545) ? - _theResult_____2__h39570[32:31] != 2'b11 : - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878[19] || - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1880 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1901 && - x__h40311[56:25] == 32'h7FFFFFFF) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1979 = - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - !NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935[19] && - (!NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1937 || - guard__h41113 != 2'd0) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2044 = - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0 || - sV2_exp__h1315 != 8'd0 || - sV2_sfd__h1316 != 23'd0) && - requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d2043 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2045 = - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV2_exp__h1315 != 8'd255 || sV2_sfd__h1316 == 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2044 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2098 = - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2030 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 || - !IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2032) && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2035 && - (!IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2031 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2037) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2104 = - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV2_exp__h1315 != 8'd255 || sV2_sfd__h1316 == 23'd0) && - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2103 ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2120 = - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV2_exp__h1315 != 8'd255 || sV2_sfd__h1316 == 23'd0) && - (requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d2043 || - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2103) ; - assign NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470 = - !sV1_sfd__h1213[21] && !sV1_sfd__h1213[20] && - !sV1_sfd__h1213[19] && - !sV1_sfd__h1213[18] && - !sV1_sfd__h1213[17] && - !sV1_sfd__h1213[16] && - !sV1_sfd__h1213[15] && - !sV1_sfd__h1213[14] && - !sV1_sfd__h1213[13] && - !sV1_sfd__h1213[12] && - !sV1_sfd__h1213[11] && - !sV1_sfd__h1213[10] && - !sV1_sfd__h1213[9] && - !sV1_sfd__h1213[8] && - !sV1_sfd__h1213[7] && - !sV1_sfd__h1213[6] && - !sV1_sfd__h1213[5] && - !sV1_sfd__h1213[4] && - !sV1_sfd__h1213[3] && - !sV1_sfd__h1213[2] && - !sV1_sfd__h1213[1] && - !sV1_sfd__h1213[0] ; - assign NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d1278 = - !sfd__h24253[31] && !sfd__h24253[30] && !sfd__h24253[29] && - !sfd__h24253[28] && - !sfd__h24253[27] && - !sfd__h24253[26] && - !sfd__h24253[25] && - !sfd__h24253[24] && - !sfd__h24253[23] && - !sfd__h24253[22] && - !sfd__h24253[21] && - !sfd__h24253[20] && - !sfd__h24253[19] && - !sfd__h24253[18] && - !sfd__h24253[17] && - !sfd__h24253[16] && - !sfd__h24253[15] && - !sfd__h24253[14] && - !sfd__h24253[13] && - !sfd__h24253[12] && - !sfd__h24253[11] && - !sfd__h24253[10] && - !sfd__h24253[9] && - !sfd__h24253[8] && - !sfd__h24253[7] && - !sfd__h24253[6] && - !sfd__h24253[5] && - !sfd__h24253[4] && - !sfd__h24253[3] && - !sfd__h24253[2] && - !sfd__h24253[1] && - !sfd__h24253[0] || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 || - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 ; - assign NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d2781 = - !sfd__h2613[63] && !sfd__h2613[62] && !sfd__h2613[61] && - !sfd__h2613[60] && - !sfd__h2613[59] && - !sfd__h2613[58] && - !sfd__h2613[57] && - !sfd__h2613[56] && - !sfd__h2613[55] && - !sfd__h2613[54] && - !sfd__h2613[53] && - !sfd__h2613[52] && - !sfd__h2613[51] && - !sfd__h2613[50] && - !sfd__h2613[49] && - !sfd__h2613[48] && - !sfd__h2613[47] && - !sfd__h2613[46] && - !sfd__h2613[45] && - !sfd__h2613[44] && - !sfd__h2613[43] && - !sfd__h2613[42] && - !sfd__h2613[41] && - !sfd__h2613[40] && - !sfd__h2613[39] && - !sfd__h2613[38] && - !sfd__h2613[37] && - !sfd__h2613[36] && - !sfd__h2613[35] && - !sfd__h2613[34] && - !sfd__h2613[33] && - !sfd__h2613[32] && - !sfd__h2613[31] && - !sfd__h2613[30] && - !sfd__h2613[29] && - !sfd__h2613[28] && - !sfd__h2613[27] && - !sfd__h2613[26] && - !sfd__h2613[25] && - !sfd__h2613[24] && - !sfd__h2613[23] && - !sfd__h2613[22] && - !sfd__h2613[21] && - !sfd__h2613[20] && - !sfd__h2613[19] && - !sfd__h2613[18] && - !sfd__h2613[17] && - !sfd__h2613[16] && - !sfd__h2613[15] && - !sfd__h2613[14] && - !sfd__h2613[13] && - !sfd__h2613[12] && - !sfd__h2613[11] && - !sfd__h2613[10] && - !sfd__h2613[9] && - !sfd__h2613[8] && - !sfd__h2613[7] && - !sfd__h2613[6] && - !sfd__h2613[5] && - !sfd__h2613[4] && - !sfd__h2613[3] && - !sfd__h2613[2] && - !sfd__h2613[1] && - !sfd__h2613[0] || - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 || - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 ; - assign NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d412 = - !sfd__h2613[63] && !sfd__h2613[62] && !sfd__h2613[61] && - !sfd__h2613[60] && - !sfd__h2613[59] && - !sfd__h2613[58] && - !sfd__h2613[57] && - !sfd__h2613[56] && - !sfd__h2613[55] && - !sfd__h2613[54] && - !sfd__h2613[53] && - !sfd__h2613[52] && - !sfd__h2613[51] && - !sfd__h2613[50] && - !sfd__h2613[49] && - !sfd__h2613[48] && - !sfd__h2613[47] && - !sfd__h2613[46] && - !sfd__h2613[45] && - !sfd__h2613[44] && - !sfd__h2613[43] && - !sfd__h2613[42] && - !sfd__h2613[41] && - !sfd__h2613[40] && - !sfd__h2613[39] && - !sfd__h2613[38] && - !sfd__h2613[37] && - !sfd__h2613[36] && - !sfd__h2613[35] && - !sfd__h2613[34] && - !sfd__h2613[33] && - !sfd__h2613[32] && - !sfd__h2613[31] && - !sfd__h2613[30] && - !sfd__h2613[29] && - !sfd__h2613[28] && - !sfd__h2613[27] && - !sfd__h2613[26] && - !sfd__h2613[25] && - !sfd__h2613[24] && - !sfd__h2613[23] && - !sfd__h2613[22] && - !sfd__h2613[21] && - !sfd__h2613[20] && - !sfd__h2613[19] && - !sfd__h2613[18] && - !sfd__h2613[17] && - !sfd__h2613[16] && - !sfd__h2613[15] && - !sfd__h2613[14] && - !sfd__h2613[13] && - !sfd__h2613[12] && - !sfd__h2613[11] && - !sfd__h2613[10] && - !sfd__h2613[9] && - !sfd__h2613[8] && - !sfd__h2613[7] && - !sfd__h2613[6] && - !sfd__h2613[5] && - !sfd__h2613[4] && - !sfd__h2613[3] && - !sfd__h2613[2] && - !sfd__h2613[1] && - !sfd__h2613[0] || - !_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 || - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 ; - assign NOT_requestR_3_BITS_159_TO_128_139_EQ_0_140_14_ETC___d1660 = - requestR[159:128] != 32'd0 && - (requestR[159] || - requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077) && - (!_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530 && - _theResult___fst_exp__h36347 == 8'd255 && - _theResult___fst_sfd__h36348 == 23'd0) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2699 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - ((NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777185) ? - _theResult_____2__h71474[32:31] != 2'b11 : - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2657 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2678 && - x__h72215[85:54] == 32'h7FFFFFFF) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2762 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - !NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2720 || - guard__h73017 != 2'd0) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3180 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - ((NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2622 == - 24'd16777153) ? - _theResult_____2__h96108[64:63] != 2'b11 : - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3142 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3163 && - x__h97073[117:54] == 64'h7FFFFFFFFFFFFFFF) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3239 = - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - !NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196[23] && - (!NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3198 || - guard__h98096 != 2'd0) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5212 = - (requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0 || - requestR[126:116] != 11'd0 || - requestR[115:64] != 52'd0) && - (requestR[191] && !requestR[127] || - (requestR[191] || !requestR[127]) && - IF_requestR_3_BIT_191_47_THEN_NOT_requestR_3_B_ETC___d5208) ; - assign NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5273 = - (requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - (requestR[191] && !requestR[127] || - (requestR[191] || !requestR[127]) && - IF_requestR_3_BIT_191_47_THEN_NOT_requestR_3_B_ETC___d5208 || - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5256) ; - assign NOT_requestR_3_BITS_190_TO_180_608_ULT_request_ETC___d5252 = - !requestR_3_BITS_190_TO_180_608_ULT_requestR_3__ETC___d5204 && - (!requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 || - !requestR_3_BITS_179_TO_128_610_ULT_requestR_3__ETC___d5205) && - requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5197 && - (!requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 || - requestR_3_BITS_179_TO_128_610_ULE_requestR_3__ETC___d5200) ; - assign NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d2102 = - (requestR[191:160] != 32'hFFFFFFFF || !requestR[159] || - requestR[127:96] == 32'hFFFFFFFF && requestR[95]) && - (requestR[191:160] == 32'hFFFFFFFF && requestR[159] || - requestR[127:96] != 32'hFFFFFFFF || - !requestR[95]) && - ((requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ? - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2098 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2099) ; - assign NOT_requestR_3_BIT_158_31_32_AND_NOT_requestR__ETC___d822 = - !requestR[158] && !requestR[157] && !requestR[156] && - !requestR[155] && - !requestR[154] && - !requestR[153] && - !requestR[152] && - !requestR[151] && - !requestR[150] && - !requestR[149] && - !requestR[148] && - !requestR[147] && - !requestR[146] && - !requestR[145] && - !requestR[144] && - !requestR[143] && - !requestR[142] && - !requestR[141] && - !requestR[140] && - !requestR[139] && - !requestR[138] && - !requestR[137] && - !requestR[136] && - !requestR[135] && - !requestR[134] && - !requestR[133] && - !requestR[132] && - !requestR[131] && - !requestR[130] && - !requestR[129] && - !requestR[128] ; - assign NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 = - !requestR[179] && !requestR[178] && !requestR[177] && - !requestR[176] && - !requestR[175] && - !requestR[174] && - !requestR[173] && - !requestR[172] && - !requestR[171] && - !requestR[170] && - !requestR[169] && - !requestR[168] && - !requestR[167] && - !requestR[166] && - !requestR[165] && - !requestR[164] && - !requestR[163] && - !requestR[162] && - !requestR[161] && - !requestR[160] && - !requestR[159] && - NOT_requestR_3_BIT_158_31_32_AND_NOT_requestR__ETC___d822 ; - assign NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d1013 = - !requestR[191] && !requestR[190] && !requestR[189] && - !requestR[188] && - !requestR[187] && - !requestR[186] && - !requestR[185] && - !requestR[184] && - !requestR[183] && - !requestR[182] && - !requestR[181] && - !requestR[180] && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 || - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 || - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 ; - assign NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d3048 = - !requestR[191] && !requestR[190] && !requestR[189] && - !requestR[188] && - !requestR[187] && - !requestR[186] && - !requestR[185] && - !requestR[184] && - !requestR[183] && - !requestR[182] && - !requestR[181] && - !requestR[180] && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 || - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 || - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568 = - { {4{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696[7]}}, - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1696 } ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568 + - 12'd1023 ; - assign SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q153 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150[10:0] - - 11'd1023 ; - assign SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737 = - { requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620[10], - requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620 } ; - assign SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 = - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 = - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737 + - 12'd127 ; - assign SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q121 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118[7:0] - - 8'd127 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d3542 = - ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d3540 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282 = - { 3'd0, - _theResult___fst_exp__h118551 == 8'd0 && - (sfdin__h118545[56:34] == 23'd0 || guard__h110454 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h119178 == 8'd255 && - _theResult___fst_sfd__h119179 == 23'd0, - 1'd0, - _theResult___fst_exp__h118551 != 8'd255 && - guard__h110454 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d4819 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d4817 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d5104 = - { 3'd0, - _theResult___fst_exp__h177684 == 11'd0 && - (sfdin__h177678[56:5] == 52'd0 || guard__h169458 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h178514 == 11'd2047 && - _theResult___fst_sfd__h178515 == 52'd0, - 1'd0, - _theResult___fst_exp__h177684 != 11'd2047 && - guard__h169458 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d3986 = - ({ 3'd0, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d3984 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d4311 = - { 3'd0, - _theResult___fst_exp__h136404 == 8'd0 && - (sfdin__h136398[56:34] == 23'd0 || guard__h128178 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h137031 == 8'd255 && - _theResult___fst_sfd__h137032 == 23'd0, - 1'd0, - _theResult___fst_exp__h136404 != 8'd255 && - guard__h128178 != 2'b0 } ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4499 = - ({ 6'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4892 = - ({ 6'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 } ^ - 12'h800) <= - (IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d4891 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d5087 = - { 3'd0, - _theResult___fst_exp__h168111 == 11'd0 && - guard__h160150 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h168867 == 11'd2047 && - _theResult___fst_sfd__h168868 == 52'd0, - 1'd0, - _theResult___fst_exp__h168111 != 11'd2047 && - guard__h160150 != 2'b0 } ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d3664 = - ({ 3'd0, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4059 = - ({ 3'd0, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 } ^ - 9'h100) <= - (IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4058 ^ - 9'h100) ; - assign _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294 = - { 3'd0, - _theResult___fst_exp__h127237 == 8'd0 && - guard__h119189 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h127790 == 8'd255 && - _theResult___fst_sfd__h127791 == 23'd0, - 1'd0, - _theResult___fst_exp__h127237 != 8'd255 && - guard__h119189 != 2'b0 } ; - assign _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d4575 = - b__h39635 >> - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d4571 ; - assign _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_608__ETC___d3744 = - sfd__h102814 >> - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_608_ETC___d3740 ; - assign _1_CONCAT_DONTCARE_CONCAT_requestR_3_BITS_63_TO_ETC___d78 = - { 33'h1AAAAAAAA, - requestR[63:32] == 32'hFFFFFFFF && requestR[31], - (requestR[63:32] == 32'hFFFFFFFF) ? - requestR[30:0] : - 31'h7FC00000 } ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3306 = - 12'd3074 - - { 6'd0, - requestR[179] ? - 6'd0 : - (requestR[178] ? - 6'd1 : - (requestR[177] ? - 6'd2 : - (requestR[176] ? - 6'd3 : - (requestR[175] ? - 6'd4 : - (requestR[174] ? - 6'd5 : - (requestR[173] ? - 6'd6 : - (requestR[172] ? - 6'd7 : - (requestR[171] ? - 6'd8 : - (requestR[170] ? - 6'd9 : - (requestR[169] ? - 6'd10 : - (requestR[168] ? - 6'd11 : - (requestR[167] ? - 6'd12 : - (requestR[166] ? - 6'd13 : - (requestR[165] ? - 6'd14 : - (requestR[164] ? - 6'd15 : - (requestR[163] ? - 6'd16 : - (requestR[162] ? - 6'd17 : - (requestR[161] ? - 6'd18 : - (requestR[160] ? - 6'd19 : - (requestR[159] ? - 6'd20 : - (requestR[158] ? - 6'd21 : - (requestR[157] ? - 6'd22 : - (requestR[156] ? - 6'd23 : - (requestR[155] ? - 6'd24 : - (requestR[154] ? - 6'd25 : - (requestR[153] ? - 6'd26 : - (requestR[152] ? - 6'd27 : - (requestR[151] ? - 6'd28 : - (requestR[150] ? - 6'd29 : - (requestR[149] ? - 6'd30 : - (requestR[148] ? - 6'd31 : - (requestR[147] ? - 6'd32 : - (requestR[146] ? - 6'd33 : - (requestR[145] ? - 6'd34 : - (requestR[144] ? - 6'd35 : - (requestR[143] ? - 6'd36 : - (requestR[142] ? - 6'd37 : - (requestR[141] ? - 6'd38 : - (requestR[140] ? - 6'd39 : - (requestR[139] ? - 6'd40 : - (requestR[138] ? - 6'd41 : - (requestR[137] ? - 6'd42 : - (requestR[136] ? - 6'd43 : - (requestR[135] ? - 6'd44 : - (requestR[134] ? - 6'd45 : - (requestR[133] ? - 6'd46 : - (requestR[132] ? - 6'd47 : - (requestR[131] ? - 6'd48 : - (requestR[130] ? - 6'd49 : - (requestR[129] ? - 6'd50 : - (requestR[128] ? - 6'd51 : - 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 = - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3306 ^ - 12'h800) <= - 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 = - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3306 ^ - 12'h800) < - 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4297 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282[4] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294[4]) ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4322 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282[3] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294[3]) ; - assign _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d4349 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 && - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d4282[1] : - _0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4294[1]) ; - assign _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d4571 = - 12'd3074 - - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4568 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273 = - (9'd32 - - { 3'd0, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1270 }) - - 9'd1 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273 ^ - 9'h100) <= - 9'd383 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273 ^ - 9'h100) < - 9'd107 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273 ^ - 9'h100) < - 9'd130 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244 = - (12'd32 - - { 6'd0, - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d2241 }) - - 12'd1 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244 ^ - 12'h800) <= - 12'd3071 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244 ^ - 12'h800) < - 12'd974 ; - assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 = - (_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244 ^ - 12'h800) < - 12'd1026 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527 = - (9'd32 - - { 3'd0, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1524 }) - - 9'd1 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527 ^ - 9'h100) <= - 9'd383 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527 ^ - 9'h100) < - 9'd107 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527 ^ - 9'h100) < - 9'd130 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458 = - (12'd32 - - { 6'd0, - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d2455 }) - - 12'd1 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458 ^ - 12'h800) <= - 12'd3071 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458 ^ - 12'h800) < - 12'd974 ; - assign _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461 = - (_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4425 = - 12'd3970 - - { 7'd0, - sV1_sfd__h1213[22] ? - 5'd0 : - (sV1_sfd__h1213[21] ? - 5'd1 : - (sV1_sfd__h1213[20] ? - 5'd2 : - (sV1_sfd__h1213[19] ? - 5'd3 : - (sV1_sfd__h1213[18] ? - 5'd4 : - (sV1_sfd__h1213[17] ? - 5'd5 : - (sV1_sfd__h1213[16] ? - 5'd6 : - (sV1_sfd__h1213[15] ? - 5'd7 : - (sV1_sfd__h1213[14] ? - 5'd8 : - (sV1_sfd__h1213[13] ? - 5'd9 : - (sV1_sfd__h1213[12] ? - 5'd10 : - (sV1_sfd__h1213[11] ? - 5'd11 : - (sV1_sfd__h1213[10] ? - 5'd12 : - (sV1_sfd__h1213[9] ? - 5'd13 : - (sV1_sfd__h1213[8] ? - 5'd14 : - (sV1_sfd__h1213[7] ? - 5'd15 : - (sV1_sfd__h1213[6] ? - 5'd16 : - (sV1_sfd__h1213[5] ? - 5'd17 : - (sV1_sfd__h1213[4] ? - 5'd18 : - (sV1_sfd__h1213[3] ? - 5'd19 : - (sV1_sfd__h1213[2] ? - 5'd20 : - (sV1_sfd__h1213[1] ? - 5'd21 : - (sV1_sfd__h1213[0] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 = - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4425 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 = - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4425 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_608_ETC___d3740 = - 12'd3970 - - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3737 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776 = - (12'd64 - - { 5'd0, - IF_IF_requestR_3_BIT_191_47_THEN_NEG_requestR__ETC___d404 }) - - 12'd1 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776 ^ - 12'h800) <= - 12'd3071 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776 ^ - 12'h800) < - 12'd974 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776 ^ - 12'h800) < - 12'd1026 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407 = - (9'd64 - - { 2'd0, - IF_IF_requestR_3_BIT_191_47_THEN_NEG_requestR__ETC___d404 }) - - 9'd1 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407 ^ - 9'h100) <= - 9'd383 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407 ^ - 9'h100) < - 9'd107 ; - assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 = - (_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407 ^ - 9'h100) < - 9'd130 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960 = - (12'd64 - - { 5'd0, - IF_requestR_3_BIT_191_47_THEN_0_ELSE_IF_reques_ETC___d920 }) - - 12'd1 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960 ^ - 12'h800) <= - 12'd3071 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960 ^ - 12'h800) < - 12'd974 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960 ^ - 12'h800) < - 12'd1026 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923 = - (9'd64 - - { 2'd0, - IF_requestR_3_BIT_191_47_THEN_0_ELSE_IF_reques_ETC___d920 }) - - 9'd1 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923 ^ - 9'h100) <= - 9'd383 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923 ^ - 9'h100) < - 9'd107 ; - assign _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926 = - (_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923 ^ - 9'h100) < - 9'd130 ; - assign _theResult_____2__h36897 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1722 ? - out1___1__h37613 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[88:24] ; - assign _theResult_____2__h39570 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d1869 ? - out1___1__h40062 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[56:24] ; - assign _theResult_____2__h71474 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2646 ? - out1___1__h71966 : - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[85:53] ; - assign _theResult_____2__h96108 = - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3131 ? - out1___1__h96824 : - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[117:53] ; - assign _theResult____h110444 = - (value__h71541 == 54'd0) ? sfd__h102814 : 57'd1 ; - assign _theResult____h128168 = - ((_3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_608_ETC___d3740 ^ - 12'h800) < - 12'd2105) ? - result__h128781 : - _theResult____h110444 ; - assign _theResult____h169448 = - ((_3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d4571 ^ - 12'h800) < - 12'd2105) ? - result__h170061 : - ((value__h36964 == 25'd0) ? b__h39635 : 57'd1) ; - assign _theResult___exp__h119077 = - sfd__h118643[24] ? - ((_theResult___fst_exp__h118551 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h145728) : - ((_theResult___fst_exp__h118551 == 8'd0 && - sfd__h118643[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h118551) ; - assign _theResult___exp__h12644 = - (sfd__h12245[24] || sfd__h12245[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h127689 = - sfd__h127255[24] ? - ((_theResult___fst_exp__h127237 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h145752) : - ((_theResult___fst_exp__h127237 == 8'd0 && - sfd__h127255[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h127237) ; - assign _theResult___exp__h13197 = - sfd__h12788[24] ? - ((x__h12773[7:0] == 8'd254) ? - 8'd255 : - din_inc___2_exp__h13340) : - ((x__h12773[7:0] == 8'd0 && sfd__h12788[24:23] == 2'b01) ? - 8'd1 : - x__h12773[7:0]) ; - assign _theResult___exp__h136930 = - sfd__h136496[24] ? - ((_theResult___fst_exp__h136404 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h145782) : - ((_theResult___fst_exp__h136404 == 8'd0 && - sfd__h136496[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h136404) ; - assign _theResult___exp__h145596 = - sfd__h145138[24] ? - ((_theResult___fst_exp__h145119 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h145806) : - ((_theResult___fst_exp__h145119 == 8'd0 && - sfd__h145138[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h145119) ; - assign _theResult___exp__h168766 = - sfd__h168129[53] ? - ((_theResult___fst_exp__h168111 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h187331) : - ((_theResult___fst_exp__h168111 == 11'd0 && - sfd__h168129[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h168111) ; - assign _theResult___exp__h178413 = - sfd__h177776[53] ? - ((_theResult___fst_exp__h177684 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h187361) : - ((_theResult___fst_exp__h177684 == 11'd0 && - sfd__h177776[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h177684) ; - assign _theResult___exp__h187195 = - sfd__h186534[53] ? - ((_theResult___fst_exp__h186515 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h187385) : - ((_theResult___fst_exp__h186515 == 11'd0 && - sfd__h186534[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h186515) ; - assign _theResult___exp__h23208 = - (sfd__h22812[24] || sfd__h22812[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h23760 = - sfd__h23351[24] ? - ((x__h23336[7:0] == 8'd254) ? - 8'd255 : - din_inc___2_exp__h23898) : - ((x__h23336[7:0] == 8'd0 && sfd__h23351[24:23] == 2'b01) ? - 8'd1 : - x__h23336[7:0]) ; - assign _theResult___exp__h29580 = - (sfd__h29184[24] || sfd__h29184[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h30133 = - sfd__h29724[24] ? - ((x__h29709[7:0] == 8'd254) ? - 8'd255 : - din_inc___2_exp__h30276) : - ((x__h29709[7:0] == 8'd0 && sfd__h29724[24:23] == 2'b01) ? - 8'd1 : - x__h29709[7:0]) ; - assign _theResult___exp__h35696 = - (sfd__h35300[24] || sfd__h35300[24:23] == 2'b01) ? 8'd1 : 8'd0 ; - assign _theResult___exp__h36248 = - sfd__h35839[24] ? - ((x__h35824[7:0] == 8'd254) ? - 8'd255 : - din_inc___2_exp__h36386) : - ((x__h35824[7:0] == 8'd0 && sfd__h35839[24:23] == 2'b01) ? - 8'd1 : - x__h35824[7:0]) ; - assign _theResult___exp__h60430 = - (sfd__h59831[53] || sfd__h59831[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h61186 = - sfd__h60574[53] ? - ((x__h60559[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h61329) : - ((x__h60559[10:0] == 11'd0 && sfd__h60574[53:52] == 2'b01) ? - 11'd1 : - x__h60559[10:0]) ; - assign _theResult___exp__h70071 = - (sfd__h69472[53] || sfd__h69472[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h70826 = - sfd__h70214[53] ? - ((x__h70199[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h70964) : - ((x__h70199[10:0] == 11'd0 && sfd__h70214[53:52] == 2'b01) ? - 11'd1 : - x__h70199[10:0]) ; - assign _theResult___exp__h83751 = - (sfd__h83152[53] || sfd__h83152[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h84507 = - sfd__h83895[53] ? - ((x__h83880[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h84650) : - ((x__h83880[10:0] == 11'd0 && sfd__h83895[53:52] == 2'b01) ? - 11'd1 : - x__h83880[10:0]) ; - assign _theResult___exp__h94708 = - (sfd__h94109[53] || sfd__h94109[53:52] == 2'b01) ? - 11'd1 : - 11'd0 ; - assign _theResult___exp__h95463 = - sfd__h94851[53] ? - ((x__h94836[10:0] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h95601) : - ((x__h94836[10:0] == 11'd0 && sfd__h94851[53:52] == 2'b01) ? - 11'd1 : - x__h94836[10:0]) ; - assign _theResult___fst_exp__h110426 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 8'd255 : - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 ; - assign _theResult___fst_exp__h118551 = - _theResult____h110444[56] ? - 8'd2 : - _theResult___fst_exp__h118625 ; - assign _theResult___fst_exp__h118616 = - 8'd0 - - { 2'd0, - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d3540 } ; - assign _theResult___fst_exp__h118622 = - (!_theResult____h110444[56] && !_theResult____h110444[55] && - !_theResult____h110444[54] && - !_theResult____h110444[53] && - !_theResult____h110444[52] && - !_theResult____h110444[51] && - !_theResult____h110444[50] && - !_theResult____h110444[49] && - !_theResult____h110444[48] && - !_theResult____h110444[47] && - !_theResult____h110444[46] && - !_theResult____h110444[45] && - !_theResult____h110444[44] && - !_theResult____h110444[43] && - !_theResult____h110444[42] && - !_theResult____h110444[41] && - !_theResult____h110444[40] && - !_theResult____h110444[39] && - !_theResult____h110444[38] && - !_theResult____h110444[37] && - !_theResult____h110444[36] && - !_theResult____h110444[35] && - !_theResult____h110444[34] && - !_theResult____h110444[33] && - !_theResult____h110444[32] && - !_theResult____h110444[31] && - !_theResult____h110444[30] && - !_theResult____h110444[29] && - !_theResult____h110444[28] && - !_theResult____h110444[27] && - !_theResult____h110444[26] && - !_theResult____h110444[25] && - !_theResult____h110444[24] && - !_theResult____h110444[23] && - !_theResult____h110444[22] && - !_theResult____h110444[21] && - !_theResult____h110444[20] && - !_theResult____h110444[19] && - !_theResult____h110444[18] && - !_theResult____h110444[17] && - !_theResult____h110444[16] && - !_theResult____h110444[15] && - !_theResult____h110444[14] && - !_theResult____h110444[13] && - !_theResult____h110444[12] && - !_theResult____h110444[11] && - !_theResult____h110444[10] && - !_theResult____h110444[9] && - !_theResult____h110444[8] && - !_theResult____h110444[7] && - !_theResult____h110444[6] && - !_theResult____h110444[5] && - !_theResult____h110444[4] && - !_theResult____h110444[3] && - !_theResult____h110444[2] && - !_theResult____h110444[1] && - !_theResult____h110444[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS__ETC___d3542) ? - 8'd0 : - _theResult___fst_exp__h118616 ; - assign _theResult___fst_exp__h118625 = - (!_theResult____h110444[56] && _theResult____h110444[55]) ? - 8'd1 : - _theResult___fst_exp__h118622 ; - assign _theResult___fst_exp__h119175 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q125 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 ; - assign _theResult___fst_exp__h119178 = - (_theResult___fst_exp__h118551 == 8'd255) ? - _theResult___fst_exp__h118551 : - _theResult___fst_exp__h119175 ; - assign _theResult___fst_exp__h127228 = - 8'd129 - - { 2'd0, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 } ; - assign _theResult___fst_exp__h127234 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 || - !_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d3664) ? - 8'd0 : - _theResult___fst_exp__h127228 ; - assign _theResult___fst_exp__h127237 = - (requestR[190:180] == 11'd0) ? - _theResult___fst_exp__h127234 : - 8'd129 ; - assign _theResult___fst_exp__h12741 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2228_0b0_0_0b1_0_0b10_out_exp2647_0b_ETC__q15 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499 ; - assign _theResult___fst_exp__h127787 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q129 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 ; - assign _theResult___fst_exp__h127790 = - (_theResult___fst_exp__h127237 == 8'd255) ? - _theResult___fst_exp__h127237 : - _theResult___fst_exp__h127787 ; - assign _theResult___fst_exp__h13294 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_x2773_ETC__q17 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 ; - assign _theResult___fst_exp__h13297 = - (x__h12773[7:0] == 8'd255) ? - x__h12773[7:0] : - _theResult___fst_exp__h13294 ; - assign _theResult___fst_exp__h136404 = - _theResult____h128168[56] ? - 8'd2 : - _theResult___fst_exp__h136478 ; - assign _theResult___fst_exp__h136469 = - 8'd0 - - { 2'd0, - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d3984 } ; - assign _theResult___fst_exp__h136475 = - (!_theResult____h128168[56] && !_theResult____h128168[55] && - !_theResult____h128168[54] && - !_theResult____h128168[53] && - !_theResult____h128168[52] && - !_theResult____h128168[51] && - !_theResult____h128168[50] && - !_theResult____h128168[49] && - !_theResult____h128168[48] && - !_theResult____h128168[47] && - !_theResult____h128168[46] && - !_theResult____h128168[45] && - !_theResult____h128168[44] && - !_theResult____h128168[43] && - !_theResult____h128168[42] && - !_theResult____h128168[41] && - !_theResult____h128168[40] && - !_theResult____h128168[39] && - !_theResult____h128168[38] && - !_theResult____h128168[37] && - !_theResult____h128168[36] && - !_theResult____h128168[35] && - !_theResult____h128168[34] && - !_theResult____h128168[33] && - !_theResult____h128168[32] && - !_theResult____h128168[31] && - !_theResult____h128168[30] && - !_theResult____h128168[29] && - !_theResult____h128168[28] && - !_theResult____h128168[27] && - !_theResult____h128168[26] && - !_theResult____h128168[25] && - !_theResult____h128168[24] && - !_theResult____h128168[23] && - !_theResult____h128168[22] && - !_theResult____h128168[21] && - !_theResult____h128168[20] && - !_theResult____h128168[19] && - !_theResult____h128168[18] && - !_theResult____h128168[17] && - !_theResult____h128168[16] && - !_theResult____h128168[15] && - !_theResult____h128168[14] && - !_theResult____h128168[13] && - !_theResult____h128168[12] && - !_theResult____h128168[11] && - !_theResult____h128168[10] && - !_theResult____h128168[9] && - !_theResult____h128168[8] && - !_theResult____h128168[7] && - !_theResult____h128168[6] && - !_theResult____h128168[5] && - !_theResult____h128168[4] && - !_theResult____h128168[3] && - !_theResult____h128168[2] && - !_theResult____h128168[1] && - !_theResult____h128168[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_ETC___d3986) ? - 8'd0 : - _theResult___fst_exp__h136469 ; - assign _theResult___fst_exp__h136478 = - (!_theResult____h128168[56] && _theResult____h128168[55]) ? - 8'd1 : - _theResult___fst_exp__h136475 ; - assign _theResult___fst_exp__h137028 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q127 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 ; - assign _theResult___fst_exp__h137031 = - (_theResult___fst_exp__h136404 == 8'd255) ? - _theResult___fst_exp__h136404 : - _theResult___fst_exp__h137028 ; - assign _theResult___fst_exp__h145071 = - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118[7:0] == - 8'd0) ? - 8'd1 : - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118[7:0] ; - assign _theResult___fst_exp__h145110 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC__q118[7:0] - - { 2'd0, - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 } ; - assign _theResult___fst_exp__h145116 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 || - !_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608_EQ__ETC___d4059) ? - 8'd0 : - _theResult___fst_exp__h145110 ; - assign _theResult___fst_exp__h145119 = - (requestR[190:180] == 11'd0) ? - _theResult___fst_exp__h145116 : - _theResult___fst_exp__h145071 ; - assign _theResult___fst_exp__h145694 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q131 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 ; - assign _theResult___fst_exp__h145697 = - (_theResult___fst_exp__h145119 == 8'd255) ? - _theResult___fst_exp__h145119 : - _theResult___fst_exp__h145694 ; - assign _theResult___fst_exp__h145706 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 ? - _theResult___snd_fst_exp__h127793 : - _theResult___fst_exp__h110426) : - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 ? - _theResult___snd_fst_exp__h145700 : - _theResult___fst_exp__h110426) ; - assign _theResult___fst_exp__h145709 = - (requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ? - 8'd0 : - _theResult___fst_exp__h145706 ; - assign _theResult___fst_exp__h153038 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 11'd2047 : - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 ; - assign _theResult___fst_exp__h168102 = - 11'd897 - - { 5'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 } ; - assign _theResult___fst_exp__h168108 = - (sV1_exp__h1212 == 8'd0 && !sV1_sfd__h1213[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470 || - !_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4499) ? - 11'd0 : - _theResult___fst_exp__h168102 ; - assign _theResult___fst_exp__h168111 = - (sV1_exp__h1212 == 8'd0) ? - _theResult___fst_exp__h168108 : - 11'd897 ; - assign _theResult___fst_exp__h168864 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q157 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 ; - assign _theResult___fst_exp__h168867 = - (_theResult___fst_exp__h168111 == 11'd2047) ? - _theResult___fst_exp__h168111 : - _theResult___fst_exp__h168864 ; - assign _theResult___fst_exp__h177684 = - _theResult____h169448[56] ? - 11'd2 : - _theResult___fst_exp__h177758 ; - assign _theResult___fst_exp__h177749 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d4817 } ; - assign _theResult___fst_exp__h177755 = - (!_theResult____h169448[56] && !_theResult____h169448[55] && - !_theResult____h169448[54] && - !_theResult____h169448[53] && - !_theResult____h169448[52] && - !_theResult____h169448[51] && - !_theResult____h169448[50] && - !_theResult____h169448[49] && - !_theResult____h169448[48] && - !_theResult____h169448[47] && - !_theResult____h169448[46] && - !_theResult____h169448[45] && - !_theResult____h169448[44] && - !_theResult____h169448[43] && - !_theResult____h169448[42] && - !_theResult____h169448[41] && - !_theResult____h169448[40] && - !_theResult____h169448[39] && - !_theResult____h169448[38] && - !_theResult____h169448[37] && - !_theResult____h169448[36] && - !_theResult____h169448[35] && - !_theResult____h169448[34] && - !_theResult____h169448[33] && - !_theResult____h169448[32] && - !_theResult____h169448[31] && - !_theResult____h169448[30] && - !_theResult____h169448[29] && - !_theResult____h169448[28] && - !_theResult____h169448[27] && - !_theResult____h169448[26] && - !_theResult____h169448[25] && - !_theResult____h169448[24] && - !_theResult____h169448[23] && - !_theResult____h169448[22] && - !_theResult____h169448[21] && - !_theResult____h169448[20] && - !_theResult____h169448[19] && - !_theResult____h169448[18] && - !_theResult____h169448[17] && - !_theResult____h169448[16] && - !_theResult____h169448[15] && - !_theResult____h169448[14] && - !_theResult____h169448[13] && - !_theResult____h169448[12] && - !_theResult____h169448[11] && - !_theResult____h169448[10] && - !_theResult____h169448[9] && - !_theResult____h169448[8] && - !_theResult____h169448[7] && - !_theResult____h169448[6] && - !_theResult____h169448[5] && - !_theResult____h169448[4] && - !_theResult____h169448[3] && - !_theResult____h169448[2] && - !_theResult____h169448[1] && - !_theResult____h169448[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_3_B_ETC___d4819) ? - 11'd0 : - _theResult___fst_exp__h177749 ; - assign _theResult___fst_exp__h177758 = - (!_theResult____h169448[56] && _theResult____h169448[55]) ? - 11'd1 : - _theResult___fst_exp__h177755 ; - assign _theResult___fst_exp__h178511 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q159 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 ; - assign _theResult___fst_exp__h178514 = - (_theResult___fst_exp__h177684 == 11'd2047) ? - _theResult___fst_exp__h177684 : - _theResult___fst_exp__h178511 ; - assign _theResult___fst_exp__h186467 = - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150[10:0] == - 11'd0) ? - 11'd1 : - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150[10:0] ; - assign _theResult___fst_exp__h186506 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC__q150[10:0] - - { 5'd0, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 } ; - assign _theResult___fst_exp__h186512 = - (sV1_exp__h1212 == 8'd0 && !sV1_sfd__h1213[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470 || - !_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d4892) ? - 11'd0 : - _theResult___fst_exp__h186506 ; - assign _theResult___fst_exp__h186515 = - (sV1_exp__h1212 == 8'd0) ? - _theResult___fst_exp__h186512 : - _theResult___fst_exp__h186467 ; - assign _theResult___fst_exp__h187293 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q161 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 ; - assign _theResult___fst_exp__h187296 = - (_theResult___fst_exp__h186515 == 11'd2047) ? - _theResult___fst_exp__h186515 : - _theResult___fst_exp__h187293 ; - assign _theResult___fst_exp__h187305 = - (sV1_exp__h1212 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 ? - _theResult___snd_fst_exp__h168870 : - _theResult___fst_exp__h153038) : - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 ? - _theResult___snd_fst_exp__h187299 : - _theResult___fst_exp__h153038) ; - assign _theResult___fst_exp__h187308 = - (sV1_exp__h1212 == 8'd0 && sV1_sfd__h1213 == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h187305 ; - assign _theResult___fst_exp__h23304 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2795_0b0_0_0b1_0_0b10_out_exp3211_0b_ETC__q26 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard2795_ETC__q28 ; - assign _theResult___fst_exp__h23856 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_x3336_ETC__q33 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004 ; - assign _theResult___fst_exp__h23859 = - (x__h23336[7:0] == 8'd255) ? - x__h23336[7:0] : - _theResult___fst_exp__h23856 ; - assign _theResult___fst_exp__h29677 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9167_0b0_0_0b1_0_0b10_out_exp9583_0b_ETC__q45 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356 ; - assign _theResult___fst_exp__h30230 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_x9709_ETC__q47 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 ; - assign _theResult___fst_exp__h30233 = - (x__h29709[7:0] == 8'd255) ? - x__h29709[7:0] : - _theResult___fst_exp__h30230 ; - assign _theResult___fst_exp__h35792 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5283_0b0_0_0b1_0_0b10_out_exp5699_0b_ETC__q54 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5283_ETC__q56 ; - assign _theResult___fst_exp__h36344 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_x5824_ETC__q58 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607 ; - assign _theResult___fst_exp__h36347 = - (x__h35824[7:0] == 8'd255) ? - x__h35824[7:0] : - _theResult___fst_exp__h36344 ; - assign _theResult___fst_exp__h60527 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9814_0b0_0_0b1_0_0b10_out_exp0433_0b_ETC__q78 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324 ; - assign _theResult___fst_exp__h61283 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_x055_ETC__q74 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 ; - assign _theResult___fst_exp__h61286 = - (x__h60559[10:0] == 11'd2047) ? - x__h60559[10:0] : - _theResult___fst_exp__h61283 ; - assign _theResult___fst_exp__h70167 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9455_0b0_0_0b1_0_0b10_out_exp0074_0b_ETC__q83 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard9455_ETC__q85 ; - assign _theResult___fst_exp__h70922 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_x019_ETC__q87 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539 ; - assign _theResult___fst_exp__h70925 = - (x__h70199[10:0] == 11'd2047) ? - x__h70199[10:0] : - _theResult___fst_exp__h70922 ; - assign _theResult___fst_exp__h83848 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3135_0b0_0_0b1_0_0b10_out_exp3754_0b_ETC__q103 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855 ; - assign _theResult___fst_exp__h84604 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_x388_ETC__q99 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 ; - assign _theResult___fst_exp__h84607 = - (x__h83880[10:0] == 11'd2047) ? - x__h83880[10:0] : - _theResult___fst_exp__h84604 ; - assign _theResult___fst_exp__h94804 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4092_0b0_0_0b1_0_0b10_out_exp4711_0b_ETC__q29 : - CASE_requestR_BITS_194_TO_192_0x3_IF_guard4092_ETC__q31 ; - assign _theResult___fst_exp__h95559 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_x483_ETC__q107 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039 ; - assign _theResult___fst_exp__h95562 = - (x__h94836[10:0] == 11'd2047) ? - x__h94836[10:0] : - _theResult___fst_exp__h95559 ; - assign _theResult___fst_sfd__h110427 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 23'd0 : - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 ; - assign _theResult___fst_sfd__h119176 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q133 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 ; - assign _theResult___fst_sfd__h119179 = - (_theResult___fst_exp__h118551 == 8'd255) ? - sfdin__h118545[56:34] : - _theResult___fst_sfd__h119176 ; - assign _theResult___fst_sfd__h12742 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q19 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 ; - assign _theResult___fst_sfd__h127788 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q135 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 ; - assign _theResult___fst_sfd__h127791 = - (_theResult___fst_exp__h127237 == 8'd255) ? - _theResult___snd__h127188[56:34] : - _theResult___fst_sfd__h127788 ; - assign _theResult___fst_sfd__h13295 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q21 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 ; - assign _theResult___fst_sfd__h13298 = - (x__h12773[7:0] == 8'd255) ? - sfd___3__h12218[62:40] : - _theResult___fst_sfd__h13295 ; - assign _theResult___fst_sfd__h137029 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q137 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 ; - assign _theResult___fst_sfd__h137032 = - (_theResult___fst_exp__h136404 == 8'd255) ? - sfdin__h136398[56:34] : - _theResult___fst_sfd__h137029 ; - assign _theResult___fst_sfd__h145695 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q139 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 ; - assign _theResult___fst_sfd__h145698 = - (_theResult___fst_exp__h145119 == 8'd255) ? - _theResult___snd__h145065[56:34] : - _theResult___fst_sfd__h145695 ; - assign _theResult___fst_sfd__h145707 = - (requestR[190:180] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3307 ? - _theResult___snd_fst_sfd__h127794 : - _theResult___fst_sfd__h110427) : - (SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3738 ? - _theResult___snd_fst_sfd__h145701 : - _theResult___fst_sfd__h110427) ; - assign _theResult___fst_sfd__h145713 = - ((requestR[190:180] == 11'd2047 || requestR[190:180] == 11'd0) && - requestR[179:128] == 52'd0) ? - 23'd0 : - _theResult___fst_sfd__h145707 ; - assign _theResult___fst_sfd__h147557 = { 1'd1, sV1_sfd__h1213[21:0] } ; - assign _theResult___fst_sfd__h153039 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3) ? - 52'd0 : - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 ; - assign _theResult___fst_sfd__h168865 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q169 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 ; - assign _theResult___fst_sfd__h168868 = - (_theResult___fst_exp__h168111 == 11'd2047) ? - _theResult___snd__h168062[56:5] : - _theResult___fst_sfd__h168865 ; - assign _theResult___fst_sfd__h178512 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q171 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 ; - assign _theResult___fst_sfd__h178515 = - (_theResult___fst_exp__h177684 == 11'd2047) ? - sfdin__h177678[56:5] : - _theResult___fst_sfd__h178512 ; - assign _theResult___fst_sfd__h187294 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q173 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 ; - assign _theResult___fst_sfd__h187297 = - (_theResult___fst_exp__h186515 == 11'd2047) ? - _theResult___snd__h186461[56:5] : - _theResult___fst_sfd__h187294 ; - assign _theResult___fst_sfd__h187306 = - (sV1_exp__h1212 == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4426 ? - _theResult___snd_fst_sfd__h168871 : - _theResult___fst_sfd__h153039) : - (SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4569 ? - _theResult___snd_fst_sfd__h187300 : - _theResult___fst_sfd__h153039) ; - assign _theResult___fst_sfd__h187312 = - ((sV1_exp__h1212 == 8'd255 || sV1_exp__h1212 == 8'd0) && - sV1_sfd__h1213 == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h187306 ; - assign _theResult___fst_sfd__h23305 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q37 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027 ; - assign _theResult___fst_sfd__h23857 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q35 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042 ; - assign _theResult___fst_sfd__h23860 = - (x__h23336[7:0] == 8'd255) ? - sfd___3__h22785[62:40] : - _theResult___fst_sfd__h23857 ; - assign _theResult___fst_sfd__h29678 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q49 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 ; - assign _theResult___fst_sfd__h30231 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q51 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 ; - assign _theResult___fst_sfd__h30234 = - (x__h29709[7:0] == 8'd255) ? - sfd___3__h29157[30:8] : - _theResult___fst_sfd__h30231 ; - assign _theResult___fst_sfd__h35793 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q62 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630 ; - assign _theResult___fst_sfd__h36345 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q60 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645 ; - assign _theResult___fst_sfd__h36348 = - (x__h35824[7:0] == 8'd255) ? - sfd___3__h35273[30:8] : - _theResult___fst_sfd__h36345 ; - assign _theResult___fst_sfd__h60528 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q80 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 ; - assign _theResult___fst_sfd__h61284 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q76 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 ; - assign _theResult___fst_sfd__h61287 = - (x__h60559[10:0] == 11'd2047) ? - sfd___3__h59804[53:2] : - _theResult___fst_sfd__h61284 ; - assign _theResult___fst_sfd__h70168 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q91 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561 ; - assign _theResult___fst_sfd__h70923 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q89 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576 ; - assign _theResult___fst_sfd__h70926 = - (x__h70199[10:0] == 11'd2047) ? - sfd___3__h69445[53:2] : - _theResult___fst_sfd__h70923 ; - assign _theResult___fst_sfd__h83849 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q105 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 ; - assign _theResult___fst_sfd__h84605 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q101 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 ; - assign _theResult___fst_sfd__h84608 = - (x__h83880[10:0] == 11'd2047) ? - sfd___3__h12218[62:11] : - _theResult___fst_sfd__h84605 ; - assign _theResult___fst_sfd__h94805 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q111 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062 ; - assign _theResult___fst_sfd__h95560 = - (requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 && - requestR[194:192] != 3'h3 && - requestR[194:192] != 3'h4) ? - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q109 : - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077 ; - assign _theResult___fst_sfd__h95563 = - (x__h94836[10:0] == 11'd2047) ? - sfd___3__h22785[62:11] : - _theResult___fst_sfd__h95560 ; - assign _theResult___fst_sfd__h99110 = { 1'd1, requestR[178:128] } ; - assign _theResult___sfd__h119078 = - sfd__h118643[24] ? - ((_theResult___fst_exp__h118551 == 8'd254) ? - 23'd0 : - sfd__h118643[23:1]) : - sfd__h118643[22:0] ; - assign _theResult___sfd__h12645 = - sfd__h12245[24] ? sfd__h12245[23:1] : sfd__h12245[22:0] ; - assign _theResult___sfd__h127690 = - sfd__h127255[24] ? - ((_theResult___fst_exp__h127237 == 8'd254) ? - 23'd0 : - sfd__h127255[23:1]) : - sfd__h127255[22:0] ; - assign _theResult___sfd__h13198 = - sfd__h12788[24] ? - ((x__h12773[7:0] == 8'd254) ? 23'd0 : sfd__h12788[23:1]) : - sfd__h12788[22:0] ; - assign _theResult___sfd__h136931 = - sfd__h136496[24] ? - ((_theResult___fst_exp__h136404 == 8'd254) ? - 23'd0 : - sfd__h136496[23:1]) : - sfd__h136496[22:0] ; - assign _theResult___sfd__h145597 = - sfd__h145138[24] ? - ((_theResult___fst_exp__h145119 == 8'd254) ? - 23'd0 : - sfd__h145138[23:1]) : - sfd__h145138[22:0] ; - assign _theResult___sfd__h168767 = - sfd__h168129[53] ? - ((_theResult___fst_exp__h168111 == 11'd2046) ? - 52'd0 : - sfd__h168129[52:1]) : - sfd__h168129[51:0] ; - assign _theResult___sfd__h178414 = - sfd__h177776[53] ? - ((_theResult___fst_exp__h177684 == 11'd2046) ? - 52'd0 : - sfd__h177776[52:1]) : - sfd__h177776[51:0] ; - assign _theResult___sfd__h187196 = - sfd__h186534[53] ? - ((_theResult___fst_exp__h186515 == 11'd2046) ? - 52'd0 : - sfd__h186534[52:1]) : - sfd__h186534[51:0] ; - assign _theResult___sfd__h23209 = - sfd__h22812[24] ? sfd__h22812[23:1] : sfd__h22812[22:0] ; - assign _theResult___sfd__h23761 = - sfd__h23351[24] ? - ((x__h23336[7:0] == 8'd254) ? 23'd0 : sfd__h23351[23:1]) : - sfd__h23351[22:0] ; - assign _theResult___sfd__h29581 = - sfd__h29184[24] ? sfd__h29184[23:1] : sfd__h29184[22:0] ; - assign _theResult___sfd__h30134 = - sfd__h29724[24] ? - ((x__h29709[7:0] == 8'd254) ? 23'd0 : sfd__h29724[23:1]) : - sfd__h29724[22:0] ; - assign _theResult___sfd__h35697 = - sfd__h35300[24] ? sfd__h35300[23:1] : sfd__h35300[22:0] ; - assign _theResult___sfd__h36249 = - sfd__h35839[24] ? - ((x__h35824[7:0] == 8'd254) ? 23'd0 : sfd__h35839[23:1]) : - sfd__h35839[22:0] ; - assign _theResult___sfd__h60431 = - sfd__h59831[53] ? sfd__h59831[52:1] : sfd__h59831[51:0] ; - assign _theResult___sfd__h61187 = - sfd__h60574[53] ? - ((x__h60559[10:0] == 11'd2046) ? 52'd0 : sfd__h60574[52:1]) : - sfd__h60574[51:0] ; - assign _theResult___sfd__h70072 = - sfd__h69472[53] ? sfd__h69472[52:1] : sfd__h69472[51:0] ; - assign _theResult___sfd__h70827 = - sfd__h70214[53] ? - ((x__h70199[10:0] == 11'd2046) ? 52'd0 : sfd__h70214[52:1]) : - sfd__h70214[51:0] ; - assign _theResult___sfd__h83752 = - sfd__h83152[53] ? sfd__h83152[52:1] : sfd__h83152[51:0] ; - assign _theResult___sfd__h84508 = - sfd__h83895[53] ? - ((x__h83880[10:0] == 11'd2046) ? 52'd0 : sfd__h83895[52:1]) : - sfd__h83895[51:0] ; - assign _theResult___sfd__h94709 = - sfd__h94109[53] ? sfd__h94109[52:1] : sfd__h94109[51:0] ; - assign _theResult___sfd__h95464 = - sfd__h94851[53] ? - ((x__h94836[10:0] == 11'd2046) ? 52'd0 : sfd__h94851[52:1]) : - sfd__h94851[51:0] ; - assign _theResult___snd__h118562 = { _theResult____h110444[55:0], 1'd0 } ; - assign _theResult___snd__h118573 = - (!_theResult____h110444[56] && _theResult____h110444[55]) ? - _theResult___snd__h118575 : - _theResult___snd__h118585 ; - assign _theResult___snd__h118575 = { _theResult____h110444[54:0], 2'd0 } ; - assign _theResult___snd__h118585 = - (!_theResult____h110444[56] && !_theResult____h110444[55] && - !_theResult____h110444[54] && - !_theResult____h110444[53] && - !_theResult____h110444[52] && - !_theResult____h110444[51] && - !_theResult____h110444[50] && - !_theResult____h110444[49] && - !_theResult____h110444[48] && - !_theResult____h110444[47] && - !_theResult____h110444[46] && - !_theResult____h110444[45] && - !_theResult____h110444[44] && - !_theResult____h110444[43] && - !_theResult____h110444[42] && - !_theResult____h110444[41] && - !_theResult____h110444[40] && - !_theResult____h110444[39] && - !_theResult____h110444[38] && - !_theResult____h110444[37] && - !_theResult____h110444[36] && - !_theResult____h110444[35] && - !_theResult____h110444[34] && - !_theResult____h110444[33] && - !_theResult____h110444[32] && - !_theResult____h110444[31] && - !_theResult____h110444[30] && - !_theResult____h110444[29] && - !_theResult____h110444[28] && - !_theResult____h110444[27] && - !_theResult____h110444[26] && - !_theResult____h110444[25] && - !_theResult____h110444[24] && - !_theResult____h110444[23] && - !_theResult____h110444[22] && - !_theResult____h110444[21] && - !_theResult____h110444[20] && - !_theResult____h110444[19] && - !_theResult____h110444[18] && - !_theResult____h110444[17] && - !_theResult____h110444[16] && - !_theResult____h110444[15] && - !_theResult____h110444[14] && - !_theResult____h110444[13] && - !_theResult____h110444[12] && - !_theResult____h110444[11] && - !_theResult____h110444[10] && - !_theResult____h110444[9] && - !_theResult____h110444[8] && - !_theResult____h110444[7] && - !_theResult____h110444[6] && - !_theResult____h110444[5] && - !_theResult____h110444[4] && - !_theResult____h110444[3] && - !_theResult____h110444[2] && - !_theResult____h110444[1] && - !_theResult____h110444[0]) ? - _theResult____h110444 : - _theResult___snd__h118591 ; - assign _theResult___snd__h118591 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_3_BI_ETC__q114[54:0], - 2'd0 } ; - assign _theResult___snd__h118614 = - _theResult____h110444 << - IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_TO_18_ETC___d3540 ; - assign _theResult___snd__h127188 = - (requestR[190:180] == 11'd0) ? - _theResult___snd__h127197 : - _theResult___snd__h127190 ; - assign _theResult___snd__h127190 = { requestR[179:128], 5'd0 } ; - assign _theResult___snd__h127197 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843) ? - sfd__h102814 : - _theResult___snd__h127203 ; - assign _theResult___snd__h127203 = - { IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q116[54:0], - 2'd0 } ; - assign _theResult___snd__h127226 = - sfd__h102814 << - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d3662 ; - assign _theResult___snd__h136415 = { _theResult____h128168[55:0], 1'd0 } ; - assign _theResult___snd__h136426 = - (!_theResult____h128168[56] && _theResult____h128168[55]) ? - _theResult___snd__h136428 : - _theResult___snd__h136438 ; - assign _theResult___snd__h136428 = { _theResult____h128168[54:0], 2'd0 } ; - assign _theResult___snd__h136438 = - (!_theResult____h128168[56] && !_theResult____h128168[55] && - !_theResult____h128168[54] && - !_theResult____h128168[53] && - !_theResult____h128168[52] && - !_theResult____h128168[51] && - !_theResult____h128168[50] && - !_theResult____h128168[49] && - !_theResult____h128168[48] && - !_theResult____h128168[47] && - !_theResult____h128168[46] && - !_theResult____h128168[45] && - !_theResult____h128168[44] && - !_theResult____h128168[43] && - !_theResult____h128168[42] && - !_theResult____h128168[41] && - !_theResult____h128168[40] && - !_theResult____h128168[39] && - !_theResult____h128168[38] && - !_theResult____h128168[37] && - !_theResult____h128168[36] && - !_theResult____h128168[35] && - !_theResult____h128168[34] && - !_theResult____h128168[33] && - !_theResult____h128168[32] && - !_theResult____h128168[31] && - !_theResult____h128168[30] && - !_theResult____h128168[29] && - !_theResult____h128168[28] && - !_theResult____h128168[27] && - !_theResult____h128168[26] && - !_theResult____h128168[25] && - !_theResult____h128168[24] && - !_theResult____h128168[23] && - !_theResult____h128168[22] && - !_theResult____h128168[21] && - !_theResult____h128168[20] && - !_theResult____h128168[19] && - !_theResult____h128168[18] && - !_theResult____h128168[17] && - !_theResult____h128168[16] && - !_theResult____h128168[15] && - !_theResult____h128168[14] && - !_theResult____h128168[13] && - !_theResult____h128168[12] && - !_theResult____h128168[11] && - !_theResult____h128168[10] && - !_theResult____h128168[9] && - !_theResult____h128168[8] && - !_theResult____h128168[7] && - !_theResult____h128168[6] && - !_theResult____h128168[5] && - !_theResult____h128168[4] && - !_theResult____h128168[3] && - !_theResult____h128168[2] && - !_theResult____h128168[1] && - !_theResult____h128168[0]) ? - _theResult____h128168 : - _theResult___snd__h136444 ; - assign _theResult___snd__h136444 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_3_B_ETC__q119[54:0], - 2'd0 } ; - assign _theResult___snd__h136467 = - _theResult____h128168 << - IF_IF_3970_MINUS_SEXT_requestR_3_BITS_190_TO_1_ETC___d3984 ; - assign _theResult___snd__h145065 = - (requestR[190:180] == 11'd0) ? - _theResult___snd__h145079 : - _theResult___snd__h127190 ; - assign _theResult___snd__h145079 = - (requestR[190:180] == 11'd0 && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843) ? - sfd__h102814 : - _theResult___snd__h145085 ; - assign _theResult___snd__h145085 = - { IF_0_CONCAT_IF_requestR_3_BITS_190_TO_180_608__ETC__q122[54:0], - 2'd0 } ; - assign _theResult___snd__h145103 = - sfd__h102814 << - IF_SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1_ETC___d4058 ; - assign _theResult___snd__h168062 = - (sV1_exp__h1212 == 8'd0) ? - _theResult___snd__h168071 : - _theResult___snd__h168064 ; - assign _theResult___snd__h168064 = { sV1_sfd__h1213, 34'd0 } ; - assign _theResult___snd__h168071 = - (sV1_exp__h1212 == 8'd0 && !sV1_sfd__h1213[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470) ? - b__h39635 : - _theResult___snd__h168077 ; - assign _theResult___snd__h168077 = - { IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q148[54:0], - 2'd0 } ; - assign _theResult___snd__h168100 = - b__h39635 << - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d4497 ; - assign _theResult___snd__h177695 = { _theResult____h169448[55:0], 1'd0 } ; - assign _theResult___snd__h177706 = - (!_theResult____h169448[56] && _theResult____h169448[55]) ? - _theResult___snd__h177708 : - _theResult___snd__h177718 ; - assign _theResult___snd__h177708 = { _theResult____h169448[54:0], 2'd0 } ; - assign _theResult___snd__h177718 = - (!_theResult____h169448[56] && !_theResult____h169448[55] && - !_theResult____h169448[54] && - !_theResult____h169448[53] && - !_theResult____h169448[52] && - !_theResult____h169448[51] && - !_theResult____h169448[50] && - !_theResult____h169448[49] && - !_theResult____h169448[48] && - !_theResult____h169448[47] && - !_theResult____h169448[46] && - !_theResult____h169448[45] && - !_theResult____h169448[44] && - !_theResult____h169448[43] && - !_theResult____h169448[42] && - !_theResult____h169448[41] && - !_theResult____h169448[40] && - !_theResult____h169448[39] && - !_theResult____h169448[38] && - !_theResult____h169448[37] && - !_theResult____h169448[36] && - !_theResult____h169448[35] && - !_theResult____h169448[34] && - !_theResult____h169448[33] && - !_theResult____h169448[32] && - !_theResult____h169448[31] && - !_theResult____h169448[30] && - !_theResult____h169448[29] && - !_theResult____h169448[28] && - !_theResult____h169448[27] && - !_theResult____h169448[26] && - !_theResult____h169448[25] && - !_theResult____h169448[24] && - !_theResult____h169448[23] && - !_theResult____h169448[22] && - !_theResult____h169448[21] && - !_theResult____h169448[20] && - !_theResult____h169448[19] && - !_theResult____h169448[18] && - !_theResult____h169448[17] && - !_theResult____h169448[16] && - !_theResult____h169448[15] && - !_theResult____h169448[14] && - !_theResult____h169448[13] && - !_theResult____h169448[12] && - !_theResult____h169448[11] && - !_theResult____h169448[10] && - !_theResult____h169448[9] && - !_theResult____h169448[8] && - !_theResult____h169448[7] && - !_theResult____h169448[6] && - !_theResult____h169448[5] && - !_theResult____h169448[4] && - !_theResult____h169448[3] && - !_theResult____h169448[2] && - !_theResult____h169448[1] && - !_theResult____h169448[0]) ? - _theResult____h169448 : - _theResult___snd__h177724 ; - assign _theResult___snd__h177724 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q151[54:0], - 2'd0 } ; - assign _theResult___snd__h177747 = - _theResult____h169448 << - IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_191_T_ETC___d4817 ; - assign _theResult___snd__h186461 = - (sV1_exp__h1212 == 8'd0) ? - _theResult___snd__h186475 : - _theResult___snd__h168064 ; - assign _theResult___snd__h186475 = - (sV1_exp__h1212 == 8'd0 && !sV1_sfd__h1213[22] && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d4470) ? - b__h39635 : - _theResult___snd__h186481 ; - assign _theResult___snd__h186481 = - { IF_0_CONCAT_IF_IF_requestR_3_BITS_191_TO_160_4_ETC__q154[54:0], - 2'd0 } ; - assign _theResult___snd__h186499 = - b__h39635 << - IF_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xF_ETC___d4891 ; - assign _theResult___snd_fst_exp__h127793 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _theResult___fst_exp__h119178 : - _theResult___fst_exp__h127790 ; - assign _theResult___snd_fst_exp__h13300 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 ? - _theResult___fst_exp__h12741 : - _theResult___fst_exp__h13297 ; - assign _theResult___snd_fst_exp__h13303 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d410 ? - 8'd0 : - _theResult___snd_fst_exp__h13300 ; - assign _theResult___snd_fst_exp__h13306 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d408 ? - _theResult___snd_fst_exp__h13303 : - 8'd255 ; - assign _theResult___snd_fst_exp__h145700 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - _theResult___fst_exp__h137031 : - _theResult___fst_exp__h145697 ; - assign _theResult___snd_fst_exp__h168870 = - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 ? - 11'd0 : - _theResult___fst_exp__h168867 ; - assign _theResult___snd_fst_exp__h187299 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - _theResult___fst_exp__h178514 : - _theResult___fst_exp__h187296 ; - assign _theResult___snd_fst_exp__h23862 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926 ? - _theResult___fst_exp__h23304 : - _theResult___fst_exp__h23859 ; - assign _theResult___snd_fst_exp__h23865 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 ? - 8'd0 : - _theResult___snd_fst_exp__h23862 ; - assign _theResult___snd_fst_exp__h23868 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 ? - _theResult___snd_fst_exp__h23865 : - 8'd255 ; - assign _theResult___snd_fst_exp__h30236 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 ? - _theResult___fst_exp__h29677 : - _theResult___fst_exp__h30233 ; - assign _theResult___snd_fst_exp__h30239 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1276 ? - 8'd0 : - _theResult___snd_fst_exp__h30236 ; - assign _theResult___snd_fst_exp__h30242 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1274 ? - _theResult___snd_fst_exp__h30239 : - 8'd255 ; - assign _theResult___snd_fst_exp__h36350 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530 ? - _theResult___fst_exp__h35792 : - _theResult___fst_exp__h36347 ; - assign _theResult___snd_fst_exp__h36353 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529 ? - 8'd0 : - _theResult___snd_fst_exp__h36350 ; - assign _theResult___snd_fst_exp__h36356 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 ? - _theResult___snd_fst_exp__h36353 : - 8'd255 ; - assign _theResult___snd_fst_exp__h61289 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 ? - _theResult___fst_exp__h60527 : - _theResult___fst_exp__h61286 ; - assign _theResult___snd_fst_exp__h61292 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247 ? - 11'd0 : - _theResult___snd_fst_exp__h61289 ; - assign _theResult___snd_fst_exp__h61295 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 ? - _theResult___snd_fst_exp__h61292 : - 11'd2047 ; - assign _theResult___snd_fst_exp__h70928 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461 ? - _theResult___fst_exp__h70167 : - _theResult___fst_exp__h70925 ; - assign _theResult___snd_fst_exp__h70931 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460 ? - 11'd0 : - _theResult___snd_fst_exp__h70928 ; - assign _theResult___snd_fst_exp__h70934 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 ? - _theResult___snd_fst_exp__h70931 : - 11'd2047 ; - assign _theResult___snd_fst_exp__h84610 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 ? - _theResult___fst_exp__h83848 : - _theResult___fst_exp__h84607 ; - assign _theResult___snd_fst_exp__h84613 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2779 ? - 11'd0 : - _theResult___snd_fst_exp__h84610 ; - assign _theResult___snd_fst_exp__h84616 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2777 ? - _theResult___snd_fst_exp__h84613 : - 11'd2047 ; - assign _theResult___snd_fst_exp__h95565 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963 ? - _theResult___fst_exp__h94804 : - _theResult___fst_exp__h95562 ; - assign _theResult___snd_fst_exp__h95568 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 ? - 11'd0 : - _theResult___snd_fst_exp__h95565 ; - assign _theResult___snd_fst_exp__h95571 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 ? - _theResult___snd_fst_exp__h95568 : - 11'd2047 ; - assign _theResult___snd_fst_sfd__h102768 = - (value__h98653[51:29] == 23'd0) ? - 23'd2097152 : - value__h98653[51:29] ; - assign _theResult___snd_fst_sfd__h127794 = - _3074_MINUS_0_CONCAT_IF_requestR_3_BIT_179_90_T_ETC___d3308 ? - _theResult___fst_sfd__h119179 : - _theResult___fst_sfd__h127791 ; - assign _theResult___snd_fst_sfd__h13301 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d413 ? - _theResult___fst_sfd__h12742 : - _theResult___fst_sfd__h13298 ; - assign _theResult___snd_fst_sfd__h145701 = - SEXT_requestR_3_BITS_190_TO_180_608_MINUS_1023_ETC___d3739 ? - _theResult___fst_sfd__h137032 : - _theResult___fst_sfd__h145698 ; - assign _theResult___snd_fst_sfd__h149185 = - (value__h147302 == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h147299 ; - assign _theResult___snd_fst_sfd__h168871 = - _3970_MINUS_0_CONCAT_IF_IF_requestR_3_BITS_191__ETC___d4427 ? - 52'd0 : - _theResult___fst_sfd__h168868 ; - assign _theResult___snd_fst_sfd__h187300 = - SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d4570 ? - _theResult___fst_sfd__h178515 : - _theResult___fst_sfd__h187297 ; - assign _theResult___snd_fst_sfd__h23863 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926 ? - _theResult___fst_sfd__h23305 : - _theResult___fst_sfd__h23860 ; - assign _theResult___snd_fst_sfd__h30237 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1279 ? - _theResult___fst_sfd__h29678 : - _theResult___fst_sfd__h30234 ; - assign _theResult___snd_fst_sfd__h36351 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1530 ? - _theResult___fst_sfd__h35793 : - _theResult___fst_sfd__h36348 ; - assign _theResult___snd_fst_sfd__h61290 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 ? - _theResult___fst_sfd__h60528 : - _theResult___fst_sfd__h61287 ; - assign _theResult___snd_fst_sfd__h70929 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461 ? - _theResult___fst_sfd__h70168 : - _theResult___fst_sfd__h70926 ; - assign _theResult___snd_fst_sfd__h84611 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2782 ? - _theResult___fst_sfd__h83849 : - _theResult___fst_sfd__h84608 ; - assign _theResult___snd_fst_sfd__h95566 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963 ? - _theResult___fst_sfd__h94805 : - _theResult___fst_sfd__h95563 ; - assign b__h36962 = { value__h36964, 64'd0 } ; - assign b__h39635 = { value__h36964, 32'd0 } ; - assign b__h71539 = { value__h71541, 32'd0 } ; - assign b__h96173 = { value__h71541, 64'd0 } ; - assign din_inc___2_exp__h13340 = x__h12773[7:0] + 8'd1 ; - assign din_inc___2_exp__h145728 = _theResult___fst_exp__h118551 + 8'd1 ; - assign din_inc___2_exp__h145752 = _theResult___fst_exp__h127237 + 8'd1 ; - assign din_inc___2_exp__h145782 = _theResult___fst_exp__h136404 + 8'd1 ; - assign din_inc___2_exp__h145806 = _theResult___fst_exp__h145119 + 8'd1 ; - assign din_inc___2_exp__h187331 = _theResult___fst_exp__h168111 + 11'd1 ; - assign din_inc___2_exp__h187361 = _theResult___fst_exp__h177684 + 11'd1 ; - assign din_inc___2_exp__h187385 = _theResult___fst_exp__h186515 + 11'd1 ; - assign din_inc___2_exp__h23898 = x__h23336[7:0] + 8'd1 ; - assign din_inc___2_exp__h30276 = x__h29709[7:0] + 8'd1 ; - assign din_inc___2_exp__h36386 = x__h35824[7:0] + 8'd1 ; - assign din_inc___2_exp__h61329 = x__h60559[10:0] + 11'd1 ; - assign din_inc___2_exp__h70964 = x__h70199[10:0] + 11'd1 ; - assign din_inc___2_exp__h84650 = x__h83880[10:0] + 11'd1 ; - assign din_inc___2_exp__h95601 = x__h94836[10:0] + 11'd1 ; - assign guard__h110454 = - { IF_sfdin18545_BIT_33_THEN_2_ELSE_0__q115[1], - { sfdin__h118545[32:0], 23'd0 } != 56'd0 } ; - assign guard__h119189 = - { IF_theResult___snd27188_BIT_33_THEN_2_ELSE_0__q117[1], - { _theResult___snd__h127188[32:0], 23'd0 } != 56'd0 } ; - assign guard__h12228 = - { IF_sfd___32218_BIT_40_THEN_2_ELSE_0__q6[1], - { sfd___3__h12218[39:0], 23'd0 } != 63'd0 } ; - assign guard__h12758 = - { IF_sfd___32218_BIT_39_THEN_2_ELSE_0__q7[1], - { sfd___3__h12218[38:0], 24'd0 } != 63'd0 } ; - assign guard__h128178 = - { IF_sfdin36398_BIT_33_THEN_2_ELSE_0__q120[1], - { sfdin__h136398[32:0], 23'd0 } != 56'd0 } ; - assign guard__h128776 = x__h128876 != 57'd0 ; - assign guard__h137042 = - { IF_theResult___snd45065_BIT_33_THEN_2_ELSE_0__q123[1], - { _theResult___snd__h145065[32:0], 23'd0 } != 56'd0 } ; - assign guard__h160150 = - { IF_theResult___snd68062_BIT_4_THEN_2_ELSE_0__q149[1], - { _theResult___snd__h168062[3:0], 52'd0 } != 56'd0 } ; - assign guard__h169458 = - { IF_sfdin77678_BIT_4_THEN_2_ELSE_0__q152[1], - { sfdin__h177678[3:0], 52'd0 } != 56'd0 } ; - assign guard__h170056 = x__h170156 != 57'd0 ; - assign guard__h178525 = - { IF_theResult___snd86461_BIT_4_THEN_2_ELSE_0__q155[1], - { _theResult___snd__h186461[3:0], 52'd0 } != 56'd0 } ; - assign guard__h22795 = - { IF_sfd___32785_BIT_40_THEN_2_ELSE_0__q22[1], - { sfd___3__h22785[39:0], 23'd0 } != 63'd0 } ; - assign guard__h23321 = - { IF_sfd___32785_BIT_39_THEN_2_ELSE_0__q23[1], - { sfd___3__h22785[38:0], 24'd0 } != 63'd0 } ; - assign guard__h29167 = - { IF_sfd___39157_BIT_8_THEN_2_ELSE_0__q38[1], - { sfd___3__h29157[7:0], 23'd0 } != 31'd0 } ; - assign guard__h29694 = - { IF_sfd___39157_BIT_7_THEN_2_ELSE_0__q39[1], - { sfd___3__h29157[6:0], 24'd0 } != 31'd0 } ; - assign guard__h35283 = - { IF_sfd___35273_BIT_8_THEN_2_ELSE_0__q52[1], - { sfd___3__h35273[7:0], 23'd0 } != 31'd0 } ; - assign guard__h35809 = - { IF_sfd___35273_BIT_7_THEN_2_ELSE_0__q53[1], - { sfd___3__h35273[6:0], 24'd0 } != 31'd0 } ; - assign guard__h36895 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[23], - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[22:0], - 65'd0 } != - 88'd0 } ; - assign guard__h37673 = - { IF_x7862_BIT_24_THEN_2_ELSE_0__q63[1], - { x__h37862[23:0], 64'd0 } != 88'd0 } ; - assign guard__h38902 = - { IF_x9123_BIT_24_THEN_2_ELSE_0__q64[1], - { x__h39123[23:0], 64'd0 } != 88'd0 } ; - assign guard__h39568 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[23], - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[22:0], - 33'd0 } != - 56'd0 } ; - assign guard__h40122 = - { IF_x0311_BIT_24_THEN_2_ELSE_0__q65[1], - { x__h40311[23:0], 32'd0 } != 56'd0 } ; - assign guard__h41113 = - { IF_x1334_BIT_24_THEN_2_ELSE_0__q66[1], - { x__h41334[23:0], 32'd0 } != 56'd0 } ; - assign guard__h59814 = - { IF_sfd___39804_BIT_2_THEN_2_ELSE_0__q67[1], - { sfd___3__h59804[1:0], 52'd0 } != 54'd0 } ; - assign guard__h60544 = - { IF_sfd___39804_BIT_1_THEN_2_ELSE_0__q68[1], - { sfd___3__h59804[0], 53'd0 } != 54'd0 } ; - assign guard__h69455 = - { IF_sfd___39445_BIT_2_THEN_2_ELSE_0__q81[1], - { sfd___3__h69445[1:0], 52'd0 } != 54'd0 } ; - assign guard__h70184 = - { IF_sfd___39445_BIT_1_THEN_2_ELSE_0__q82[1], - { sfd___3__h69445[0], 53'd0 } != 54'd0 } ; - assign guard__h71472 = - { IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[52], - { IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[51:0], - 33'd0 } != - 85'd0 } ; - assign guard__h72026 = - { IF_x2215_BIT_53_THEN_2_ELSE_0__q92[1], - { x__h72215[52:0], 32'd0 } != 85'd0 } ; - assign guard__h73017 = - { IF_x3238_BIT_53_THEN_2_ELSE_0__q93[1], - { x__h73238[52:0], 32'd0 } != 85'd0 } ; - assign guard__h83135 = - { IF_sfd___32218_BIT_11_THEN_2_ELSE_0__q8[1], - { sfd___3__h12218[10:0], 52'd0 } != 63'd0 } ; - assign guard__h83865 = - { IF_sfd___32218_BIT_10_THEN_2_ELSE_0__q9[1], - { sfd___3__h12218[9:0], 53'd0 } != 63'd0 } ; - assign guard__h94092 = - { IF_sfd___32785_BIT_11_THEN_2_ELSE_0__q24[1], - { sfd___3__h22785[10:0], 52'd0 } != 63'd0 } ; - assign guard__h94821 = - { IF_sfd___32785_BIT_10_THEN_2_ELSE_0__q25[1], - { sfd___3__h22785[9:0], 53'd0 } != 63'd0 } ; - assign guard__h96106 = - { IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[52], - { IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[51:0], - 65'd0 } != - 117'd0 } ; - assign guard__h96884 = - { IF_x7073_BIT_53_THEN_2_ELSE_0__q112[1], - { x__h97073[52:0], 64'd0 } != 117'd0 } ; - assign guard__h98096 = - { IF_x8317_BIT_53_THEN_2_ELSE_0__q113[1], - { x__h98317[52:0], 64'd0 } != 117'd0 } ; - assign out1___1__h37613 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[88:24] + - 65'd1 ; - assign out1___1__h40062 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[56:24] + - 33'd1 ; - assign out1___1__h71966 = - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[85:53] + - 33'd1 ; - assign out1___1__h96824 = - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[117:53] + - 65'd1 ; - assign out___1_sfd__h147299 = { value__h147302, 29'd0 } ; - assign out_exp__h119080 = - sfdin__h118545[34] ? - _theResult___exp__h119077 : - _theResult___fst_exp__h118551 ; - assign out_exp__h12647 = - sfd___3__h12218[41] ? _theResult___exp__h12644 : 8'd0 ; - assign out_exp__h127692 = - _theResult___snd__h127188[34] ? - _theResult___exp__h127689 : - _theResult___fst_exp__h127237 ; - assign out_exp__h13200 = - sfd___3__h12218[40] ? _theResult___exp__h13197 : x__h12773[7:0] ; - assign out_exp__h136933 = - sfdin__h136398[34] ? - _theResult___exp__h136930 : - _theResult___fst_exp__h136404 ; - assign out_exp__h145599 = - _theResult___snd__h145065[34] ? - _theResult___exp__h145596 : - _theResult___fst_exp__h145119 ; - assign out_exp__h168769 = - _theResult___snd__h168062[5] ? - _theResult___exp__h168766 : - _theResult___fst_exp__h168111 ; - assign out_exp__h178416 = - sfdin__h177678[5] ? - _theResult___exp__h178413 : - _theResult___fst_exp__h177684 ; - assign out_exp__h187198 = - _theResult___snd__h186461[5] ? - _theResult___exp__h187195 : - _theResult___fst_exp__h186515 ; - assign out_exp__h23211 = - sfd___3__h22785[41] ? _theResult___exp__h23208 : 8'd0 ; - assign out_exp__h23763 = - sfd___3__h22785[40] ? _theResult___exp__h23760 : x__h23336[7:0] ; - assign out_exp__h29583 = - sfd___3__h29157[9] ? _theResult___exp__h29580 : 8'd0 ; - assign out_exp__h30136 = - sfd___3__h29157[8] ? _theResult___exp__h30133 : x__h29709[7:0] ; - assign out_exp__h35699 = - sfd___3__h35273[9] ? _theResult___exp__h35696 : 8'd0 ; - assign out_exp__h36251 = - sfd___3__h35273[8] ? _theResult___exp__h36248 : x__h35824[7:0] ; - assign out_exp__h60433 = - sfd___3__h59804[3] ? _theResult___exp__h60430 : 11'd0 ; - assign out_exp__h61189 = - sfd___3__h59804[2] ? _theResult___exp__h61186 : x__h60559[10:0] ; - assign out_exp__h70074 = - sfd___3__h69445[3] ? _theResult___exp__h70071 : 11'd0 ; - assign out_exp__h70829 = - sfd___3__h69445[2] ? _theResult___exp__h70826 : x__h70199[10:0] ; - assign out_exp__h83754 = - sfd___3__h12218[12] ? _theResult___exp__h83751 : 11'd0 ; - assign out_exp__h84510 = - sfd___3__h12218[11] ? - _theResult___exp__h84507 : - x__h83880[10:0] ; - assign out_exp__h94711 = - sfd___3__h22785[12] ? _theResult___exp__h94708 : 11'd0 ; - assign out_exp__h95466 = - sfd___3__h22785[11] ? - _theResult___exp__h95463 : - x__h94836[10:0] ; - assign out_sfd__h119081 = - sfdin__h118545[34] ? - _theResult___sfd__h119078 : - sfdin__h118545[56:34] ; - assign out_sfd__h12648 = - sfd___3__h12218[41] ? - _theResult___sfd__h12645 : - sfd___3__h12218[63:41] ; - assign out_sfd__h127693 = - _theResult___snd__h127188[34] ? - _theResult___sfd__h127690 : - _theResult___snd__h127188[56:34] ; - assign out_sfd__h13201 = - sfd___3__h12218[40] ? - _theResult___sfd__h13198 : - sfd___3__h12218[62:40] ; - assign out_sfd__h136934 = - sfdin__h136398[34] ? - _theResult___sfd__h136931 : - sfdin__h136398[56:34] ; - assign out_sfd__h145600 = - _theResult___snd__h145065[34] ? - _theResult___sfd__h145597 : - _theResult___snd__h145065[56:34] ; - assign out_sfd__h168770 = - _theResult___snd__h168062[5] ? - _theResult___sfd__h168767 : - _theResult___snd__h168062[56:5] ; - assign out_sfd__h178417 = - sfdin__h177678[5] ? - _theResult___sfd__h178414 : - sfdin__h177678[56:5] ; - assign out_sfd__h187199 = - _theResult___snd__h186461[5] ? - _theResult___sfd__h187196 : - _theResult___snd__h186461[56:5] ; - assign out_sfd__h23212 = - sfd___3__h22785[41] ? - _theResult___sfd__h23209 : - sfd___3__h22785[63:41] ; - assign out_sfd__h23764 = - sfd___3__h22785[40] ? - _theResult___sfd__h23761 : - sfd___3__h22785[62:40] ; - assign out_sfd__h29584 = - sfd___3__h29157[9] ? - _theResult___sfd__h29581 : - sfd___3__h29157[31:9] ; - assign out_sfd__h30137 = - sfd___3__h29157[8] ? - _theResult___sfd__h30134 : - sfd___3__h29157[30:8] ; - assign out_sfd__h35700 = - sfd___3__h35273[9] ? - _theResult___sfd__h35697 : - sfd___3__h35273[31:9] ; - assign out_sfd__h36252 = - sfd___3__h35273[8] ? - _theResult___sfd__h36249 : - sfd___3__h35273[30:8] ; - assign out_sfd__h60434 = - sfd___3__h59804[3] ? - _theResult___sfd__h60431 : - sfd___3__h59804[54:3] ; - assign out_sfd__h61190 = - sfd___3__h59804[2] ? - _theResult___sfd__h61187 : - sfd___3__h59804[53:2] ; - assign out_sfd__h70075 = - sfd___3__h69445[3] ? - _theResult___sfd__h70072 : - sfd___3__h69445[54:3] ; - assign out_sfd__h70830 = - sfd___3__h69445[2] ? - _theResult___sfd__h70827 : - sfd___3__h69445[53:2] ; - assign out_sfd__h83755 = - sfd___3__h12218[12] ? - _theResult___sfd__h83752 : - sfd___3__h12218[63:12] ; - assign out_sfd__h84511 = - sfd___3__h12218[11] ? - _theResult___sfd__h84508 : - sfd___3__h12218[62:11] ; - assign out_sfd__h94712 = - sfd___3__h22785[12] ? - _theResult___sfd__h94709 : - sfd___3__h22785[63:12] ; - assign out_sfd__h95467 = - sfd___3__h22785[11] ? - _theResult___sfd__h95464 : - sfd___3__h22785[62:11] ; - assign requestR_3_BITS_126_TO_116_167_EQ_0_181_AND_re_ETC___d5188 = - requestR[126:116] == 11'd0 && requestR[115:64] == 52'd0 && - requestR[127] && - requestR[190:180] == 11'd0 && - requestR[179:128] == 52'd0 && - !requestR[191] ; - assign requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 = - { requestR[127:96] == 32'hFFFFFFFF && requestR[95], - (requestR[127:96] == 32'hFFFFFFFF) ? - requestR[94:64] : - 31'h7FC00000 } ; - assign requestR_3_BITS_179_TO_128_610_ULE_requestR_3__ETC___d5200 = - requestR[179:128] <= requestR[115:64] ; - assign requestR_3_BITS_179_TO_128_610_ULT_requestR_3__ETC___d5205 = - requestR[179:128] < requestR[115:64] ; - assign requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5184 = - requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 && - requestR[191] && - requestR[126:116] == 11'd0 && - requestR[115:64] == 52'd0 && - !requestR[127] ; - assign requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5256 = - requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 && - requestR[126:116] == 11'd0 && - requestR[115:64] == 52'd0 || - (!requestR[191] || requestR[127]) && - (requestR[191] || !requestR[127]) && - (requestR[191] ? - requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5251 : - NOT_requestR_3_BITS_190_TO_180_608_ULT_request_ETC___d5252) ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2757 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2720 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d2739 && - x__h73238[85:54] == 32'hFFFFFFFF) ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2768 = - { requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2757, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2762 } == - 5'd0 || - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2757 ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3234 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - (NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196[23] || - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3198 && - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_OR_NO_ETC___d3217 && - x__h98317[117:54] == 64'hFFFFFFFFFFFFFFFF) ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3245 = - { requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3234, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3239 } == - 5'd0 || - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3234 ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5176 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115] ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5221 = - requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179] || - requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0 && - !requestR[115] ; - assign requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5241 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5221 || - requestR[190:180] == 11'd2047 && requestR[179] || - requestR[126:116] == 11'd2047 && requestR[115] ; - assign requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 = - requestR[190:180] == requestR[126:116] ; - assign requestR_3_BITS_190_TO_180_608_MINUS_1023___d2620 = - requestR[190:180] - 11'd1023 ; - assign requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5197 = - requestR[190:180] <= requestR[126:116] ; - assign requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5251 = - requestR_3_BITS_190_TO_180_608_ULE_requestR_3__ETC___d5197 && - (!requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 || - requestR_3_BITS_179_TO_128_610_ULE_requestR_3__ETC___d5200) && - !requestR_3_BITS_190_TO_180_608_ULT_requestR_3__ETC___d5204 && - (!requestR_3_BITS_190_TO_180_608_EQ_requestR_3_B_ETC___d5199 || - !requestR_3_BITS_179_TO_128_610_ULT_requestR_3__ETC___d5205) ; - assign requestR_3_BITS_190_TO_180_608_ULT_requestR_3__ETC___d5204 = - requestR[190:180] < requestR[126:116] ; - assign requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NOT_r_ETC___d856 = - requestR[191:128] == 64'd0 || - !requestR[191] && !requestR[190] && !requestR[189] && - !requestR[188] && - !requestR[187] && - !requestR[186] && - !requestR[185] && - !requestR[184] && - !requestR[183] && - !requestR[182] && - !requestR[181] && - !requestR[180] && - NOT_requestR_3_BIT_179_90_91_AND_NOT_requestR__ETC___d843 ; - assign requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_A_ETC___d2043 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159] && - (requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) || - (requestR[191:160] == 32'hFFFFFFFF && requestR[159] || - requestR[127:96] != 32'hFFFFFFFF || - !requestR[95]) && - IF_NOT_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2041 ; - assign requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077 = - requestR[158] || requestR[157] || requestR[156] || - requestR[155] || - requestR[154] || - requestR[153] || - requestR[152] || - requestR[151] || - requestR[150] || - requestR[149] || - requestR[148] || - requestR[147] || - requestR[146] || - requestR[145] || - requestR[144] || - requestR[143] || - requestR[142] || - requestR[141] || - requestR[140] || - requestR[139] || - requestR[138] || - requestR[137] || - requestR[136] || - requestR[135] || - requestR[134] || - requestR[133] || - requestR[132] || - requestR[131] || - requestR[130] || - requestR[129] || - requestR[128] ; - assign requestR_3_BIT_159_6_OR_requestR_3_BIT_158_31__ETC___d1671 = - (requestR[159] || - requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077) && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529 && - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d1668 ; - assign requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098 = - requestR[179] || requestR[178] || requestR[177] || - requestR[176] || - requestR[175] || - requestR[174] || - requestR[173] || - requestR[172] || - requestR[171] || - requestR[170] || - requestR[169] || - requestR[168] || - requestR[167] || - requestR[166] || - requestR[165] || - requestR[164] || - requestR[163] || - requestR[162] || - requestR[161] || - requestR[160] || - requestR[159] || - requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077 ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1119 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - (!_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 || - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 && - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d926 && - _theResult___fst_exp__h23859 == 8'd255 && - _theResult___fst_sfd__h23860 == 23'd0) ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1122 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1131 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d924 && - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d925 && - IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d1128 ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3091 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - (!_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 || - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 && - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2963 && - _theResult___fst_exp__h95562 == 11'd2047 && - _theResult___fst_sfd__h95563 == 52'd0) ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3094 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 ; - assign requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3103 = - (requestR[191] || requestR[190] || requestR[189] || - requestR[188] || - requestR[187] || - requestR[186] || - requestR[185] || - requestR[184] || - requestR[183] || - requestR[182] || - requestR[181] || - requestR[180] || - requestR_3_BIT_179_90_OR_requestR_3_BIT_178_92_ETC___d1098) && - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2961 && - !_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2962 && - IF_64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47__ETC___d3100 ; - assign requestR_BITS_159_TO_128__q1 = requestR[159:128] ; - assign res___1__h204227 = - (requestR[190:180] == 11'd2047 && requestR[179]) ? - 64'd512 : - 64'd256 ; - assign res___1__h204665 = requestR[191] ? 64'd1 : 64'd128 ; - assign res___1__h204675 = requestR[191] ? 64'd8 : 64'd16 ; - assign res___1__h204694 = requestR[191] ? 64'd4 : 64'd32 ; - assign res___1__h50292 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213[22]) ? - 64'd512 : - 64'd256 ; - assign res___1__h50528 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd1 : - 64'd128 ; - assign res___1__h50538 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd8 : - 64'd16 ; - assign res___1__h50557 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd4 : - 64'd32 ; - assign res__h146185 = { 32'hFFFFFFFF, x__h146191 } ; - assign res__h187935 = - { IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5073, - x__h147243, - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5037 } ; - assign res__h192322 = - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5212 ? - requestR[191:128] : - requestR[127:64] ; - assign res__h196815 = - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5212 ? - requestR[127:64] : - requestR[191:128] ; - assign res__h199464 = - ((requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) && - (requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) && - requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_re_ETC___d5256) ? - 64'd1 : - 64'd0 ; - assign res__h202104 = - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5212 ? - 64'd1 : - 64'd0 ; - assign res__h203926 = - NOT_requestR_3_BITS_190_TO_180_608_EQ_2047_609_ETC___d5273 ? - 64'd1 : - 64'd0 ; - assign res__h204710 = requestR[191] ? 64'd2 : 64'd64 ; - assign res__h204864 = { 32'hFFFFFFFF, fpu$server_core_response_get[36:5] } ; - assign res__h42283 = - { 32'hFFFFFFFF, - requestR_3_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AN_ETC___d38 } ; - assign res__h42520 = - { 32'hFFFFFFFF, - requestR[191:160] == 32'hFFFFFFFF && requestR[159], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign res__h47670 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2104 ? - 64'd1 : - 64'd0 ; - assign res__h49098 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2045 ? - 64'd1 : - 64'd0 ; - assign res__h50112 = - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d2120 ? - 64'd1 : - 64'd0 ; - assign res__h50573 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 64'd2 : - 64'd64 ; - assign result__h128781 = - { _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_608__ETC___d3744[56:1], - _0b0_CONCAT_NOT_requestR_3_BITS_190_TO_180_608__ETC___d3744[0] | - guard__h128776 } ; - assign result__h170061 = - { _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d4575[56:1], - _0b0_CONCAT_NOT_IF_requestR_3_BITS_191_TO_160_4_ETC___d4575[0] | - guard__h170056 } ; - assign sV1_exp__h1212 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[158:151] : - 8'd255 ; - assign sV1_sfd__h1213 = - (requestR[191:160] == 32'hFFFFFFFF) ? - requestR[150:128] : - 23'd4194304 ; - assign sV2_exp__h1315 = - (requestR[127:96] == 32'hFFFFFFFF) ? requestR[94:87] : 8'd255 ; - assign sV2_sfd__h1316 = - (requestR[127:96] == 32'hFFFFFFFF) ? - requestR[86:64] : - 23'd4194304 ; - assign sfd___3__h12218 = - sfd__h2613 << - IF_IF_requestR_3_BIT_191_47_THEN_NEG_requestR__ETC___d404 ; - assign sfd___3__h22785 = - requestR[191:128] << - IF_requestR_3_BIT_191_47_THEN_0_ELSE_IF_reques_ETC___d920 ; - assign sfd___3__h29157 = - sfd__h24253 << - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d1270 ; - assign sfd___3__h35273 = - requestR[159:128] << - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d1524 ; - assign sfd___3__h59804 = - sfd__h51803 << - IF_IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_ETC___d2241 ; - assign sfd___3__h69445 = - sfd__h61693 << - IF_requestR_3_BIT_159_6_THEN_0_ELSE_IF_request_ETC___d2455 ; - assign sfd__h102814 = { value__h71541, 3'd0 } ; - assign sfd__h118643 = - { 1'b0, - _theResult___fst_exp__h118551 != 8'd0, - sfdin__h118545[56:34] } + - 25'd1 ; - assign sfd__h12245 = { 2'd0, sfd___3__h12218[63:41] } + 25'd1 ; - assign sfd__h127255 = - { 1'b0, - _theResult___fst_exp__h127237 != 8'd0, - _theResult___snd__h127188[56:34] } + - 25'd1 ; - assign sfd__h12788 = - { 1'b0, x__h12773[7:0] != 8'd0, sfd___3__h12218[62:40] } + - 25'd1 ; - assign sfd__h136496 = - { 1'b0, - _theResult___fst_exp__h136404 != 8'd0, - sfdin__h136398[56:34] } + - 25'd1 ; - assign sfd__h145138 = - { 1'b0, - _theResult___fst_exp__h145119 != 8'd0, - _theResult___snd__h145065[56:34] } + - 25'd1 ; - assign sfd__h168129 = - { 1'b0, - _theResult___fst_exp__h168111 != 11'd0, - _theResult___snd__h168062[56:5] } + - 54'd1 ; - assign sfd__h177776 = - { 1'b0, - _theResult___fst_exp__h177684 != 11'd0, - sfdin__h177678[56:5] } + - 54'd1 ; - assign sfd__h186534 = - { 1'b0, - _theResult___fst_exp__h186515 != 11'd0, - _theResult___snd__h186461[56:5] } + - 54'd1 ; - assign sfd__h22812 = { 2'd0, sfd___3__h22785[63:41] } + 25'd1 ; - assign sfd__h23351 = - { 1'b0, x__h23336[7:0] != 8'd0, sfd___3__h22785[62:40] } + - 25'd1 ; - assign sfd__h24253 = - requestR[159] ? -requestR[159:128] : requestR[159:128] ; - assign sfd__h2613 = requestR[191] ? -requestR[191:128] : requestR[191:128] ; - assign sfd__h29184 = { 2'd0, sfd___3__h29157[31:9] } + 25'd1 ; - assign sfd__h29724 = - { 1'b0, x__h29709[7:0] != 8'd0, sfd___3__h29157[30:8] } + 25'd1 ; - assign sfd__h35300 = { 2'd0, sfd___3__h35273[31:9] } + 25'd1 ; - assign sfd__h35839 = - { 1'b0, x__h35824[7:0] != 8'd0, sfd___3__h35273[30:8] } + 25'd1 ; - assign sfd__h51803 = { sfd__h24253, 23'd0 } ; - assign sfd__h59831 = { 2'd0, sfd___3__h59804[54:3] } + 54'd1 ; - assign sfd__h60574 = - { 1'b0, x__h60559[10:0] != 11'd0, sfd___3__h59804[53:2] } + - 54'd1 ; - assign sfd__h61693 = { requestR[159:128], 23'd0 } ; - assign sfd__h69472 = { 2'd0, sfd___3__h69445[54:3] } + 54'd1 ; - assign sfd__h70214 = - { 1'b0, x__h70199[10:0] != 11'd0, sfd___3__h69445[53:2] } + - 54'd1 ; - assign sfd__h83152 = { 2'd0, sfd___3__h12218[63:12] } + 54'd1 ; - assign sfd__h83895 = - { 1'b0, x__h83880[10:0] != 11'd0, sfd___3__h12218[62:11] } + - 54'd1 ; - assign sfd__h94109 = { 2'd0, sfd___3__h22785[63:12] } + 54'd1 ; - assign sfd__h94851 = - { 1'b0, x__h94836[10:0] != 11'd0, sfd___3__h22785[62:11] } + - 54'd1 ; - assign sfdin__h118545 = - _theResult____h110444[56] ? - _theResult___snd__h118562 : - _theResult___snd__h118573 ; - assign sfdin__h136398 = - _theResult____h128168[56] ? - _theResult___snd__h136415 : - _theResult___snd__h136426 ; - assign sfdin__h177678 = - _theResult____h169448[56] ? - _theResult___snd__h177695 : - _theResult___snd__h177706 ; - assign value__h147302 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 && - !sV1_sfd__h1213[22]) ? - _theResult___fst_sfd__h147557 : - sV1_sfd__h1213 ; - assign value__h36964 = { 1'b0, sV1_exp__h1212 != 8'd0, sV1_sfd__h1213 } ; - assign value__h71541 = - { 1'b0, requestR[190:180] != 11'd0, requestR[179:128] } ; - assign value__h98653 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 && - !requestR[179]) ? - _theResult___fst_sfd__h99110 : - requestR[179:128] ; - assign x__h12773 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d407 + - 9'd127 ; - assign x__h128876 = sfd__h102814 << x__h128909 ; - assign x__h128909 = - 12'd57 - - _3970_MINUS_SEXT_requestR_3_BITS_190_TO_180_608_ETC___d3740 ; - assign x__h13466 = - { 2'd0, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d647, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d650, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d659 } ; - assign x__h13699 = - { 33'h1FFFFFFFE, - requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NOT_r_ETC___d856 ? - 8'd0 : - _theResult___snd_fst_exp__h23868, - (requestR[191:128] == 64'd0 || - NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d1013) ? - 23'd0 : - _theResult___snd_fst_sfd__h23863 } ; - assign x__h146191 = - { (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - (requestR[190:180] == 11'd2047 || - requestR[190:180] == 11'd0) && - requestR[179:128] == 52'd0) ? - requestR[191] : - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4264, - x__h98593, - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d4224 } ; - assign x__h146306 = - { (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179] : - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4315, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4326, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4342, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4355, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_THE_ETC___d4368 } ; - assign x__h147233 = - (x__h147243 == 11'd2047 && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5037[51]) ? - 64'h7FF8000000000000 : - res__h187935 ; - assign x__h147243 = - (sV1_exp__h1212 == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h187308 ; - assign x__h170156 = b__h39635 << x__h170189 ; - assign x__h170189 = - 12'd57 - - _3074_MINUS_SEXT_IF_requestR_3_BITS_191_TO_160__ETC___d4571 ; - assign x__h188037 = - { IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5111, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5118, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5132, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5144, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d5156 } ; - assign x__h188904 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5176 ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115]) ? - requestR[191:128] : - ((requestR[190:180] == 11'd2047 && requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115]) ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && requestR[179]) ? - requestR[127:64] : - IF_requestR_3_BITS_126_TO_116_167_EQ_2047_168__ETC___d5215)))) ; - assign x__h192454 = - { requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5221, - 4'd0 } ; - assign x__h193397 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5176 ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] != 52'd0 && - !requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && - requestR[115:64] != 52'd0 && - !requestR[115]) ? - requestR[191:128] : - ((requestR[190:180] == 11'd2047 && requestR[179] && - requestR[126:116] == 11'd2047 && - requestR[115]) ? - 64'h7FF8000000000000 : - ((requestR[190:180] == 11'd2047 && requestR[179]) ? - requestR[127:64] : - ((requestR[126:116] == 11'd2047 && requestR[115]) ? - requestR[191:128] : - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5228))))) ; - assign x__h197786 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5241 ? - 64'd0 : - res__h199464 ; - assign x__h200426 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5241 ? - 64'd0 : - res__h202104 ; - assign x__h202123 = - { requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0, - 4'd0 } ; - assign x__h202248 = - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d5241 ? - 64'd0 : - res__h203926 ; - assign x__h204207 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ? - res___1__h204227 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - res___1__h204665 : - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d5294) ; - assign x__h204831 = - fpu$server_core_response_get[69] ? - res__h204864 : - fpu$server_core_response_get[68:5] ; - assign x__h23336 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d923 + - 9'd127 ; - assign x__h2341 = { 32'hFFFFFFFF, x__h2348 } ; - assign x__h2348 = - { requestR[127:96] == 32'hFFFFFFFF && requestR[95], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h24002 = - { 2'd0, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1119, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1122, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d1131 } ; - assign x__h2422 = { 32'hFFFFFFFF, x__h2429 } ; - assign x__h24232 = { 32'hFFFFFFFF, x__h24238 } ; - assign x__h24238 = - { requestR[159:128] != 32'd0 && - (NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d1278 ? - requestR[159] : - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d1331), - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1391, - (requestR[159:128] == 32'd0 || - NOT_IF_requestR_3_BIT_159_6_THEN_NEG_requestR__ETC___d1278) ? - 23'd0 : - _theResult___snd_fst_sfd__h30237 } ; - assign x__h2429 = - { requestR[127:96] != 32'hFFFFFFFF || !requestR[95], - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h2500 = { 32'hFFFFFFFF, x__h2507 } ; - assign x__h2507 = - { (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) != - (requestR[127:96] == 32'hFFFFFFFF && requestR[95]), - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d29 } ; - assign x__h2592 = { 32'hFFFFFFFF, x__h2598 } ; - assign x__h2598 = - { requestR[191:128] != 64'd0 && - (NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d412 ? - requestR[191] : - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d474), - IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d534, - (requestR[191:128] == 64'd0 || - NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d412) ? - 23'd0 : - _theResult___snd_fst_sfd__h13301 } ; - assign x__h29709 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d1273 + - 9'd127 ; - assign x__h30402 = - { 2'd0, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1472, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1475, - requestR[159:128] != 32'd0 && - IF_requestR_3_BIT_159_6_THEN_NEG_requestR_3_BI_ETC___d1484 } ; - assign x__h30632 = - { 33'h1FFFFFFFE, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d1613, - (requestR[159:128] == 32'd0 || - !requestR[159] && - NOT_requestR_3_BIT_158_31_32_AND_NOT_requestR__ETC___d822 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 || - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529) ? - 23'd0 : - _theResult___snd_fst_sfd__h36351 } ; - assign x__h35824 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1527 + - 9'd127 ; - assign x__h36490 = - { 2'd0, - NOT_requestR_3_BITS_159_TO_128_139_EQ_0_140_14_ETC___d1660, - requestR[159:128] != 32'd0 && - (requestR[159] || - requestR_3_BIT_158_31_OR_requestR_3_BIT_157_33_ETC___d1077) && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1528 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d1529, - requestR[159:128] != 32'd0 && - requestR_3_BIT_159_6_OR_requestR_3_BIT_158_31__ETC___d1671 } ; - assign x__h36719 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692 ? - 64'h7FFFFFFFFFFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1764 ; - assign x__h37862 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705 >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731 | - ~(89'h1FFFFFFFFFFFFFFFFFFFFFF >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1731) & - {89{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1705[88]}} ; - assign x__h38500 = - { sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0 || - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1774, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1785 } ; - assign x__h38702 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692 ? - 64'hFFFFFFFFFFFFFFFF : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1824 ; - assign x__h39123 = - { sV1_exp__h1212 != 8'd0, sV1_sfd__h1213, 65'd0 } >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1793 ; - assign x__h39201 = - { (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1842 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1831, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1836 } ; - assign x__h39389 = { {32{x__h39392[31]}}, x__h39392 } ; - assign x__h39392 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692 ? - 32'h7FFFFFFF : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d1911 ; - assign x__h40311 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852 >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878 | - ~(57'h1FFFFFFFFFFFFFF >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1878) & - {57{IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1852[56]}} ; - assign x__h40708 = - { sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 == 23'd0 || - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1919, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - (sV1_exp__h1212 != 8'd0 || sV1_sfd__h1213 != 23'd0) && - IF_NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_ETC___d1927 } ; - assign x__h40910 = { {32{x__h40913[31]}}, x__h40913 } ; - assign x__h40913 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1692 ? - 32'hFFFFFFFF : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1966 ; - assign x__h41334 = - { sV1_exp__h1212 != 8'd0, sV1_sfd__h1213, 33'd0 } >> - NEG_SEXT_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d1935 ; - assign x__h41412 = - { (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1985 : - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d1974, - 3'd0, - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 == 23'd0) && - (sV1_exp__h1212 != 8'd255 || sV1_sfd__h1213 != 23'd0) && - NOT_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d1979 } ; - assign x__h41604 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2007 ? - 64'hFFFFFFFF7FC00000 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2053 ; - assign x__h43644 = - { IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2055, - 4'd0 } ; - assign x__h44183 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2007 ? - 64'hFFFFFFFF7FC00000 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2068 ; - assign x__h46653 = { 32'hFFFFFFFF, requestR[159:128] } ; - assign x__h46718 = - { {32{requestR_BITS_159_TO_128__q1[31]}}, - requestR_BITS_159_TO_128__q1 } ; - assign x__h46800 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2088 ? - 64'd0 : - res__h47670 ; - assign x__h48228 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2088 ? - 64'd0 : - res__h49098 ; - assign x__h49117 = - { sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0 || - sV2_exp__h1315 == 8'd255 && sV2_sfd__h1316 != 23'd0, - 4'd0 } ; - assign x__h49242 = - IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFFFF__ETC___d2088 ? - 64'd0 : - res__h50112 ; - assign x__h50272 = - (sV1_exp__h1212 == 8'd255 && sV1_sfd__h1213 != 23'd0) ? - res___1__h50292 : - IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d2133 ; - assign x__h51579 = { requestR[127], requestR[190:128] } ; - assign x__h51645 = { !requestR[127], requestR[190:128] } ; - assign x__h51713 = { requestR[191] != requestR[127], requestR[190:128] } ; - assign x__h51788 = - { requestR[159:128] != 32'd0 && - IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT__ETC___d2301, - (requestR[159:128] == 32'd0) ? - 11'd0 : - _theResult___snd_fst_exp__h61295, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2398 } ; - assign x__h60559 = - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2244 + - 12'd1023 ; - assign x__h61451 = - { 2'd0, - requestR[159:128] != 32'd0 && - (!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 || - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2249 && - _theResult___fst_exp__h61286 == 11'd2047 && - _theResult___fst_sfd__h61287 == 52'd0), - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247, - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2245 && - !_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159_6_T_ETC___d2247 && - IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_159__ETC___d2415 } ; - assign x__h61681 = - { 1'd0, - (requestR[159:128] == 32'd0) ? - 11'd0 : - _theResult___snd_fst_exp__h70934, - IF_requestR_3_BITS_159_TO_128_139_EQ_0_140_OR__ETC___d2580 } ; - assign x__h70199 = - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2458 + - 12'd1023 ; - assign x__h71064 = - { 2'd0, - requestR[159:128] != 32'd0 && - (!_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 || - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2461 && - _theResult___fst_exp__h70925 == 11'd2047 && - _theResult___fst_sfd__h70926 == 52'd0), - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460, - requestR[159:128] != 32'd0 && - _32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2459 && - !_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_THEN_ETC___d2460 && - IF_32_MINUS_0_CONCAT_IF_requestR_3_BIT_159_6_T_ETC___d2597 } ; - assign x__h71293 = { {32{x__h71296[31]}}, x__h71296 } ; - assign x__h71296 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'h7FFFFFFF : - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d2688 ; - assign x__h72215 = - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629 >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655 | - ~(86'h3FFFFFFFFFFFFFFFFFFFFF >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2655) & - {86{IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d2629[85]}} ; - assign x__h72612 = - { requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2699, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d2710 } ; - assign x__h72814 = { {32{x__h72817[31]}}, x__h72817 } ; - assign x__h72817 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'hFFFFFFFF : - (requestR[191] ? - 32'd0 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 32'hFFFFFFFF : - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d2747)) ; - assign x__h73238 = - { requestR[190:180] != 11'd0, requestR[179:128], 33'd0 } >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d2718 ; - assign x__h73316 = - { requestR[191] ? - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2768 : - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d2757, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d2762 } ; - assign x__h73505 = - { requestR[191:128] != 64'd0 && - (NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d2781 ? - requestR[191] : - IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191__ETC___d2831), - IF_requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NO_ETC___d2890, - (requestR[191:128] == 64'd0 || - NOT_IF_requestR_3_BIT_191_47_THEN_NEG_requestR_ETC___d2781) ? - 52'd0 : - _theResult___snd_fst_sfd__h84611 } ; - assign x__h83880 = - _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_191_47__ETC___d2776 + - 12'd1023 ; - assign x__h84772 = - { 2'd0, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2939, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2942, - requestR[191:128] != 64'd0 && - IF_requestR_3_BIT_191_47_THEN_NEG_requestR_3_B_ETC___d2951 } ; - assign x__h85002 = - { 1'd0, - requestR_3_BITS_191_TO_128_44_EQ_0_45_OR_NOT_r_ETC___d856 ? - 11'd0 : - _theResult___snd_fst_exp__h95571, - (requestR[191:128] == 64'd0 || - NOT_requestR_3_BIT_191_47_67_AND_NOT_requestR__ETC___d3048) ? - 52'd0 : - _theResult___snd_fst_sfd__h95566 } ; - assign x__h94836 = - _64_MINUS_0_CONCAT_IF_requestR_3_BIT_191_47_THE_ETC___d2960 + - 12'd1023 ; - assign x__h95701 = - { 2'd0, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3091, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3094, - requestR[191:128] != 64'd0 && - requestR_3_BIT_191_47_OR_requestR_3_BIT_190_68_ETC___d3103 } ; - assign x__h95930 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 64'h7FFFFFFFFFFFFFFF : - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d3173 ; - assign x__h97073 = - IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114 >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140 | - ~(118'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFF >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3140) & - {118{IF_requestR_3_BIT_191_47_THEN_NEG_0b0_CONCAT_N_ETC___d3114[117]}} ; - assign x__h97694 = - { requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 || - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3180, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - (requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) && - IF_NEG_SEXT_requestR_3_BITS_190_TO_180_608_MIN_ETC___d3188 } ; - assign x__h97896 = - (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 || - !requestR[191] && requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 64'hFFFFFFFFFFFFFFFF : - (requestR[191] ? - 64'd0 : - ((requestR[190:180] == 11'd2047 && - requestR[179:128] == 52'd0) ? - 64'hFFFFFFFFFFFFFFFF : - IF_requestR_3_BITS_190_TO_180_608_EQ_0_618_AND_ETC___d3225)) ; - assign x__h98317 = - { requestR[190:180] != 11'd0, requestR[179:128], 65'd0 } >> - NEG_SEXT_requestR_3_BITS_190_TO_180_608_MINUS__ETC___d3196 ; - assign x__h98395 = - { requestR[191] ? - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3245 : - requestR_3_BITS_190_TO_180_608_EQ_2047_609_AND_ETC___d3234, - 3'd0, - (requestR[190:180] != 11'd2047 || - requestR[179:128] == 52'd0) && - (requestR[190:180] != 11'd2047 || - requestR[179:128] != 52'd0) && - NOT_requestR_3_BITS_190_TO_180_608_EQ_0_618_62_ETC___d3239 } ; - assign x__h98583 = - (x__h98593 == 8'd255 && - IF_requestR_3_BITS_190_TO_180_608_EQ_2047_609__ETC___d4224[22]) ? - 64'hFFFFFFFF7FC00000 : - res__h146185 ; - assign x__h98593 = - (requestR[190:180] == 11'd2047) ? - 8'd255 : - _theResult___fst_exp__h145709 ; - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd254; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = - requestR[191] ? 8'd255 : 8'd254; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = - requestR[191] ? 8'd254 : 8'd255; - default: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - 23'd8388607; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - requestR[191] ? 23'd0 : 23'd8388607; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = - requestR[191] ? 23'd8388607 : 23'd0; - default: CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = 23'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd2046; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 11'd2047 : - 11'd2046; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 11'd2046 : - 11'd2047; - default: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h1: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - 52'hFFFFFFFFFFFFF; - 3'h2: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'h3: - CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = - (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ? - 52'hFFFFFFFFFFFFF : - 52'd0; - default: CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = 52'd0; - endcase - end - always@(requestR) - begin - case (requestR[194:192]) - 3'h0: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = - requestR[194:192]; - 3'h1: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd4; - 3'h2: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd3; - 3'h3: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd2; - 3'h4: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = 3'd1; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x0_1_THEN__ETC___d50 = - 3'd0; - endcase - end - always@(guard__h12228 or requestR) - begin - case (guard__h12228) - 2'b0, 2'b01, 2'b10: - CASE_guard2228_0b0_requestR_BIT_191_0b1_reques_ETC__q10 = - requestR[191]; - 2'd3: - CASE_guard2228_0b0_requestR_BIT_191_0b1_reques_ETC__q10 = - guard__h12228 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h12228) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - (guard__h12228 == 2'b0) ? - requestR[191] : - (guard__h12228 == 2'b01 || guard__h12228 == 2'b10 || - guard__h12228 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h12758 or requestR) - begin - case (guard__h12758) - 2'b0, 2'b01, 2'b10: - CASE_guard2758_0b0_requestR_BIT_191_0b1_reques_ETC__q12 = - requestR[191]; - 2'd3: - CASE_guard2758_0b0_requestR_BIT_191_0b1_reques_ETC__q12 = - guard__h12758 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h12758) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q13 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q13 = - (guard__h12758 == 2'b0) ? - requestR[191] : - (guard__h12758 == 2'b01 || guard__h12758 == 2'b10 || - guard__h12758 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q13 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h12228 or _theResult___exp__h12644) - begin - case (guard__h12228) - 2'b0: CASE_guard2228_0b0_0_0b1_theResult___exp2644_0_ETC__q14 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard2228_0b0_0_0b1_theResult___exp2644_0_ETC__q14 = - _theResult___exp__h12644; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d496 or - guard__h12228 or - _theResult___exp__h12644 or - CASE_guard2228_0b0_0_0b1_theResult___exp2644_0_ETC__q14) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d496; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499 = - (guard__h12228 == 2'b0 || requestR[191]) ? - 8'd0 : - _theResult___exp__h12644; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499 = - CASE_guard2228_0b0_0_0b1_theResult___exp2644_0_ETC__q14; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d499 = - 8'd0; - endcase - end - always@(guard__h12228 or out_exp__h12647 or _theResult___exp__h12644) - begin - case (guard__h12228) - 2'b0, 2'b01: - CASE_guard2228_0b0_0_0b1_0_0b10_out_exp2647_0b_ETC__q15 = 8'd0; - 2'b10: - CASE_guard2228_0b0_0_0b1_0_0b10_out_exp2647_0b_ETC__q15 = - out_exp__h12647; - 2'b11: - CASE_guard2228_0b0_0_0b1_0_0b10_out_exp2647_0b_ETC__q15 = - _theResult___exp__h12644; - endcase - end - always@(guard__h12758 or x__h12773 or _theResult___exp__h13197) - begin - case (guard__h12758) - 2'b0: - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_theRe_ETC__q16 = - x__h12773[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_theRe_ETC__q16 = - _theResult___exp__h13197; - endcase - end - always@(requestR or - x__h12773 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d524 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d522 or - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_theRe_ETC__q16) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 = - x__h12773[7:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d524; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d522; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 = - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_theRe_ETC__q16; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d528 = - 8'd0; - endcase - end - always@(guard__h12758 or - x__h12773 or out_exp__h13200 or _theResult___exp__h13197) - begin - case (guard__h12758) - 2'b0, 2'b01: - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_x2773_ETC__q17 = - x__h12773[7:0]; - 2'b10: - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_x2773_ETC__q17 = - out_exp__h13200; - 2'b11: - CASE_guard2758_0b0_x2773_BITS_7_TO_0_0b1_x2773_ETC__q17 = - _theResult___exp__h13197; - endcase - end - always@(guard__h12228 or sfd___3__h12218 or _theResult___sfd__h12645) - begin - case (guard__h12228) - 2'b0: - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q18 = - sfd___3__h12218[63:41]; - 2'b01, 2'b10, 2'b11: - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q18 = - _theResult___sfd__h12645; - endcase - end - always@(requestR or - sfd___3__h12218 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d547 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d545 or - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q18) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 = - sfd___3__h12218[63:41]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d547; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d545; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 = - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q18; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d551 = - 23'd0; - endcase - end - always@(guard__h12228 or - sfd___3__h12218 or out_sfd__h12648 or _theResult___sfd__h12645) - begin - case (guard__h12228) - 2'b0, 2'b01: - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q19 = - sfd___3__h12218[63:41]; - 2'b10: - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q19 = - out_sfd__h12648; - 2'b11: - CASE_guard2228_0b0_sfd___32218_BITS_63_TO_41_0_ETC__q19 = - _theResult___sfd__h12645; - endcase - end - always@(guard__h12758 or sfd___3__h12218 or _theResult___sfd__h13198) - begin - case (guard__h12758) - 2'b0: - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q20 = - sfd___3__h12218[62:40]; - 2'b01, 2'b10, 2'b11: - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q20 = - _theResult___sfd__h13198; - endcase - end - always@(requestR or - sfd___3__h12218 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d565 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d563 or - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q20) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 = - sfd___3__h12218[62:40]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d565; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d563; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 = - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q20; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d569 = - 23'd0; - endcase - end - always@(guard__h12758 or - sfd___3__h12218 or out_sfd__h13201 or _theResult___sfd__h13198) - begin - case (guard__h12758) - 2'b0, 2'b01: - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q21 = - sfd___3__h12218[62:40]; - 2'b10: - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q21 = - out_sfd__h13201; - 2'b11: - CASE_guard2758_0b0_sfd___32218_BITS_62_TO_40_0_ETC__q21 = - _theResult___sfd__h13198; - endcase - end - always@(guard__h22795 or out_exp__h23211 or _theResult___exp__h23208) - begin - case (guard__h22795) - 2'b0, 2'b01: - CASE_guard2795_0b0_0_0b1_0_0b10_out_exp3211_0b_ETC__q26 = 8'd0; - 2'b10: - CASE_guard2795_0b0_0_0b1_0_0b10_out_exp3211_0b_ETC__q26 = - out_exp__h23211; - 2'b11: - CASE_guard2795_0b0_0_0b1_0_0b10_out_exp3211_0b_ETC__q26 = - _theResult___exp__h23208; - endcase - end - always@(guard__h22795 or _theResult___exp__h23208) - begin - case (guard__h22795) - 2'b0: CASE_guard2795_0b0_0_0b1_theResult___exp3208_0_ETC__q27 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard2795_0b0_0_0b1_theResult___exp3208_0_ETC__q27 = - _theResult___exp__h23208; - endcase - end - always@(requestR or - guard__h22795 or - _theResult___exp__h23208 or - CASE_guard2795_0b0_0_0b1_theResult___exp3208_0_ETC__q27) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard2795_ETC__q28 = - (guard__h22795 == 2'b0) ? 8'd0 : _theResult___exp__h23208; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard2795_ETC__q28 = - CASE_guard2795_0b0_0_0b1_theResult___exp3208_0_ETC__q27; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard2795_ETC__q28 = 8'd0; - endcase - end - always@(guard__h94092 or out_exp__h94711 or _theResult___exp__h94708) - begin - case (guard__h94092) - 2'b0, 2'b01: - CASE_guard4092_0b0_0_0b1_0_0b10_out_exp4711_0b_ETC__q29 = 11'd0; - 2'b10: - CASE_guard4092_0b0_0_0b1_0_0b10_out_exp4711_0b_ETC__q29 = - out_exp__h94711; - 2'b11: - CASE_guard4092_0b0_0_0b1_0_0b10_out_exp4711_0b_ETC__q29 = - _theResult___exp__h94708; - endcase - end - always@(guard__h94092 or _theResult___exp__h94708) - begin - case (guard__h94092) - 2'b0: CASE_guard4092_0b0_0_0b1_theResult___exp4708_0_ETC__q30 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard4092_0b0_0_0b1_theResult___exp4708_0_ETC__q30 = - _theResult___exp__h94708; - endcase - end - always@(requestR or - guard__h94092 or - _theResult___exp__h94708 or - CASE_guard4092_0b0_0_0b1_theResult___exp4708_0_ETC__q30) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard4092_ETC__q31 = - (guard__h94092 == 2'b0) ? 11'd0 : _theResult___exp__h94708; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard4092_ETC__q31 = - CASE_guard4092_0b0_0_0b1_theResult___exp4708_0_ETC__q30; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard4092_ETC__q31 = - 11'd0; - endcase - end - always@(guard__h23321 or x__h23336 or _theResult___exp__h23760) - begin - case (guard__h23321) - 2'b0: - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_theRe_ETC__q32 = - x__h23336[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_theRe_ETC__q32 = - _theResult___exp__h23760; - endcase - end - always@(requestR or - x__h23336 or - guard__h23321 or - _theResult___exp__h23760 or - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_theRe_ETC__q32) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004 = - x__h23336[7:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004 = - (guard__h23321 == 2'b0) ? - x__h23336[7:0] : - _theResult___exp__h23760; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004 = - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_theRe_ETC__q32; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1004 = - 8'd0; - endcase - end - always@(guard__h23321 or - x__h23336 or out_exp__h23763 or _theResult___exp__h23760) - begin - case (guard__h23321) - 2'b0, 2'b01: - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_x3336_ETC__q33 = - x__h23336[7:0]; - 2'b10: - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_x3336_ETC__q33 = - out_exp__h23763; - 2'b11: - CASE_guard3321_0b0_x3336_BITS_7_TO_0_0b1_x3336_ETC__q33 = - _theResult___exp__h23760; - endcase - end - always@(guard__h23321 or sfd___3__h22785 or _theResult___sfd__h23761) - begin - case (guard__h23321) - 2'b0: - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q34 = - sfd___3__h22785[62:40]; - 2'b01, 2'b10, 2'b11: - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q34 = - _theResult___sfd__h23761; - endcase - end - always@(requestR or - sfd___3__h22785 or - guard__h23321 or - _theResult___sfd__h23761 or - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q34) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042 = - sfd___3__h22785[62:40]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042 = - (guard__h23321 == 2'b0) ? - sfd___3__h22785[62:40] : - _theResult___sfd__h23761; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042 = - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q34; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1042 = - 23'd0; - endcase - end - always@(guard__h23321 or - sfd___3__h22785 or out_sfd__h23764 or _theResult___sfd__h23761) - begin - case (guard__h23321) - 2'b0, 2'b01: - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q35 = - sfd___3__h22785[62:40]; - 2'b10: - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q35 = - out_sfd__h23764; - 2'b11: - CASE_guard3321_0b0_sfd___32785_BITS_62_TO_40_0_ETC__q35 = - _theResult___sfd__h23761; - endcase - end - always@(guard__h22795 or sfd___3__h22785 or _theResult___sfd__h23209) - begin - case (guard__h22795) - 2'b0: - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q36 = - sfd___3__h22785[63:41]; - 2'b01, 2'b10, 2'b11: - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q36 = - _theResult___sfd__h23209; - endcase - end - always@(requestR or - sfd___3__h22785 or - guard__h22795 or - _theResult___sfd__h23209 or - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q36) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027 = - sfd___3__h22785[63:41]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027 = - (guard__h22795 == 2'b0) ? - sfd___3__h22785[63:41] : - _theResult___sfd__h23209; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027 = - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q36; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1027 = - 23'd0; - endcase - end - always@(guard__h22795 or - sfd___3__h22785 or out_sfd__h23212 or _theResult___sfd__h23209) - begin - case (guard__h22795) - 2'b0, 2'b01: - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q37 = - sfd___3__h22785[63:41]; - 2'b10: - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q37 = - out_sfd__h23212; - 2'b11: - CASE_guard2795_0b0_sfd___32785_BITS_63_TO_41_0_ETC__q37 = - _theResult___sfd__h23209; - endcase - end - always@(guard__h29167 or requestR) - begin - case (guard__h29167) - 2'b0, 2'b01, 2'b10: - CASE_guard9167_0b0_requestR_BIT_159_0b1_reques_ETC__q40 = - requestR[159]; - 2'd3: - CASE_guard9167_0b0_requestR_BIT_159_0b1_reques_ETC__q40 = - guard__h29167 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h29167) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q41 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q41 = - (guard__h29167 == 2'b0) ? - requestR[159] : - (guard__h29167 == 2'b01 || guard__h29167 == 2'b10 || - guard__h29167 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q41 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h29694 or requestR) - begin - case (guard__h29694) - 2'b0, 2'b01, 2'b10: - CASE_guard9694_0b0_requestR_BIT_159_0b1_reques_ETC__q42 = - requestR[159]; - 2'd3: - CASE_guard9694_0b0_requestR_BIT_159_0b1_reques_ETC__q42 = - guard__h29694 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h29694) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q43 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q43 = - (guard__h29694 == 2'b0) ? - requestR[159] : - (guard__h29694 == 2'b01 || guard__h29694 == 2'b10 || - guard__h29694 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q43 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h29167 or _theResult___exp__h29580) - begin - case (guard__h29167) - 2'b0: CASE_guard9167_0b0_0_0b1_theResult___exp9580_0_ETC__q44 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard9167_0b0_0_0b1_theResult___exp9580_0_ETC__q44 = - _theResult___exp__h29580; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1353 or - guard__h29167 or - _theResult___exp__h29580 or - CASE_guard9167_0b0_0_0b1_theResult___exp9580_0_ETC__q44) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1353; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356 = - (guard__h29167 == 2'b0 || requestR[159]) ? - 8'd0 : - _theResult___exp__h29580; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356 = - CASE_guard9167_0b0_0_0b1_theResult___exp9580_0_ETC__q44; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1356 = - 8'd0; - endcase - end - always@(guard__h29167 or out_exp__h29583 or _theResult___exp__h29580) - begin - case (guard__h29167) - 2'b0, 2'b01: - CASE_guard9167_0b0_0_0b1_0_0b10_out_exp9583_0b_ETC__q45 = 8'd0; - 2'b10: - CASE_guard9167_0b0_0_0b1_0_0b10_out_exp9583_0b_ETC__q45 = - out_exp__h29583; - 2'b11: - CASE_guard9167_0b0_0_0b1_0_0b10_out_exp9583_0b_ETC__q45 = - _theResult___exp__h29580; - endcase - end - always@(guard__h29694 or x__h29709 or _theResult___exp__h30133) - begin - case (guard__h29694) - 2'b0: - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_theRe_ETC__q46 = - x__h29709[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_theRe_ETC__q46 = - _theResult___exp__h30133; - endcase - end - always@(requestR or - x__h29709 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1381 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1379 or - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_theRe_ETC__q46) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 = - x__h29709[7:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1381; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1379; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 = - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_theRe_ETC__q46; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1385 = - 8'd0; - endcase - end - always@(guard__h29694 or - x__h29709 or out_exp__h30136 or _theResult___exp__h30133) - begin - case (guard__h29694) - 2'b0, 2'b01: - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_x9709_ETC__q47 = - x__h29709[7:0]; - 2'b10: - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_x9709_ETC__q47 = - out_exp__h30136; - 2'b11: - CASE_guard9694_0b0_x9709_BITS_7_TO_0_0b1_x9709_ETC__q47 = - _theResult___exp__h30133; - endcase - end - always@(guard__h29167 or sfd___3__h29157 or _theResult___sfd__h29581) - begin - case (guard__h29167) - 2'b0: - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q48 = - sfd___3__h29157[31:9]; - 2'b01, 2'b10, 2'b11: - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q48 = - _theResult___sfd__h29581; - endcase - end - always@(requestR or - sfd___3__h29157 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1404 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1402 or - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q48) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 = - sfd___3__h29157[31:9]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1404; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1402; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 = - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q48; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1408 = - 23'd0; - endcase - end - always@(guard__h29167 or - sfd___3__h29157 or out_sfd__h29584 or _theResult___sfd__h29581) - begin - case (guard__h29167) - 2'b0, 2'b01: - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q49 = - sfd___3__h29157[31:9]; - 2'b10: - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q49 = - out_sfd__h29584; - 2'b11: - CASE_guard9167_0b0_sfd___39157_BITS_31_TO_9_0b_ETC__q49 = - _theResult___sfd__h29581; - endcase - end - always@(guard__h29694 or sfd___3__h29157 or _theResult___sfd__h30134) - begin - case (guard__h29694) - 2'b0: - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q50 = - sfd___3__h29157[30:8]; - 2'b01, 2'b10, 2'b11: - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q50 = - _theResult___sfd__h30134; - endcase - end - always@(requestR or - sfd___3__h29157 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1422 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1420 or - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q50) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 = - sfd___3__h29157[30:8]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1422; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d1420; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 = - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q50; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1426 = - 23'd0; - endcase - end - always@(guard__h29694 or - sfd___3__h29157 or out_sfd__h30137 or _theResult___sfd__h30134) - begin - case (guard__h29694) - 2'b0, 2'b01: - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q51 = - sfd___3__h29157[30:8]; - 2'b10: - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q51 = - out_sfd__h30137; - 2'b11: - CASE_guard9694_0b0_sfd___39157_BITS_30_TO_8_0b_ETC__q51 = - _theResult___sfd__h30134; - endcase - end - always@(guard__h35283 or out_exp__h35699 or _theResult___exp__h35696) - begin - case (guard__h35283) - 2'b0, 2'b01: - CASE_guard5283_0b0_0_0b1_0_0b10_out_exp5699_0b_ETC__q54 = 8'd0; - 2'b10: - CASE_guard5283_0b0_0_0b1_0_0b10_out_exp5699_0b_ETC__q54 = - out_exp__h35699; - 2'b11: - CASE_guard5283_0b0_0_0b1_0_0b10_out_exp5699_0b_ETC__q54 = - _theResult___exp__h35696; - endcase - end - always@(guard__h35283 or _theResult___exp__h35696) - begin - case (guard__h35283) - 2'b0: CASE_guard5283_0b0_0_0b1_theResult___exp5696_0_ETC__q55 = 8'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard5283_0b0_0_0b1_theResult___exp5696_0_ETC__q55 = - _theResult___exp__h35696; - endcase - end - always@(requestR or - guard__h35283 or - _theResult___exp__h35696 or - CASE_guard5283_0b0_0_0b1_theResult___exp5696_0_ETC__q55) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5283_ETC__q56 = - (guard__h35283 == 2'b0) ? 8'd0 : _theResult___exp__h35696; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard5283_ETC__q56 = - CASE_guard5283_0b0_0_0b1_theResult___exp5696_0_ETC__q55; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard5283_ETC__q56 = 8'd0; - endcase - end - always@(guard__h35809 or x__h35824 or _theResult___exp__h36248) - begin - case (guard__h35809) - 2'b0: - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_theRe_ETC__q57 = - x__h35824[7:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_theRe_ETC__q57 = - _theResult___exp__h36248; - endcase - end - always@(requestR or - x__h35824 or - guard__h35809 or - _theResult___exp__h36248 or - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_theRe_ETC__q57) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607 = - x__h35824[7:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607 = - (guard__h35809 == 2'b0) ? - x__h35824[7:0] : - _theResult___exp__h36248; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607 = - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_theRe_ETC__q57; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1607 = - 8'd0; - endcase - end - always@(guard__h35809 or - x__h35824 or out_exp__h36251 or _theResult___exp__h36248) - begin - case (guard__h35809) - 2'b0, 2'b01: - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_x5824_ETC__q58 = - x__h35824[7:0]; - 2'b10: - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_x5824_ETC__q58 = - out_exp__h36251; - 2'b11: - CASE_guard5809_0b0_x5824_BITS_7_TO_0_0b1_x5824_ETC__q58 = - _theResult___exp__h36248; - endcase - end - always@(guard__h35809 or sfd___3__h35273 or _theResult___sfd__h36249) - begin - case (guard__h35809) - 2'b0: - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q59 = - sfd___3__h35273[30:8]; - 2'b01, 2'b10, 2'b11: - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q59 = - _theResult___sfd__h36249; - endcase - end - always@(requestR or - sfd___3__h35273 or - guard__h35809 or - _theResult___sfd__h36249 or - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q59) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645 = - sfd___3__h35273[30:8]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645 = - (guard__h35809 == 2'b0) ? - sfd___3__h35273[30:8] : - _theResult___sfd__h36249; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645 = - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q59; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1645 = - 23'd0; - endcase - end - always@(guard__h35809 or - sfd___3__h35273 or out_sfd__h36252 or _theResult___sfd__h36249) - begin - case (guard__h35809) - 2'b0, 2'b01: - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q60 = - sfd___3__h35273[30:8]; - 2'b10: - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q60 = - out_sfd__h36252; - 2'b11: - CASE_guard5809_0b0_sfd___35273_BITS_30_TO_8_0b_ETC__q60 = - _theResult___sfd__h36249; - endcase - end - always@(guard__h35283 or sfd___3__h35273 or _theResult___sfd__h35697) - begin - case (guard__h35283) - 2'b0: - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q61 = - sfd___3__h35273[31:9]; - 2'b01, 2'b10, 2'b11: - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q61 = - _theResult___sfd__h35697; - endcase - end - always@(requestR or - sfd___3__h35273 or - guard__h35283 or - _theResult___sfd__h35697 or - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q61) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630 = - sfd___3__h35273[31:9]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630 = - (guard__h35283 == 2'b0) ? - sfd___3__h35273[31:9] : - _theResult___sfd__h35697; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630 = - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q61; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d1630 = - 23'd0; - endcase - end - always@(guard__h35283 or - sfd___3__h35273 or out_sfd__h35700 or _theResult___sfd__h35697) - begin - case (guard__h35283) - 2'b0, 2'b01: - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q62 = - sfd___3__h35273[31:9]; - 2'b10: - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q62 = - out_sfd__h35700; - 2'b11: - CASE_guard5283_0b0_sfd___35273_BITS_31_TO_9_0b_ETC__q62 = - _theResult___sfd__h35697; - endcase - end - always@(guard__h59814 or requestR) - begin - case (guard__h59814) - 2'b0, 2'b01, 2'b10: - CASE_guard9814_0b0_requestR_BIT_159_0b1_reques_ETC__q69 = - requestR[159]; - 2'd3: - CASE_guard9814_0b0_requestR_BIT_159_0b1_reques_ETC__q69 = - guard__h59814 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h59814) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q70 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q70 = - (guard__h59814 == 2'b0) ? - requestR[159] : - (guard__h59814 == 2'b01 || guard__h59814 == 2'b10 || - guard__h59814 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q70 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h60544 or requestR) - begin - case (guard__h60544) - 2'b0, 2'b01, 2'b10: - CASE_guard0544_0b0_requestR_BIT_159_0b1_reques_ETC__q71 = - requestR[159]; - 2'd3: - CASE_guard0544_0b0_requestR_BIT_159_0b1_reques_ETC__q71 = - guard__h60544 == 2'b11 && requestR[159]; - endcase - end - always@(requestR or guard__h60544) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q72 = - requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q72 = - (guard__h60544 == 2'b0) ? - requestR[159] : - (guard__h60544 == 2'b01 || guard__h60544 == 2'b10 || - guard__h60544 == 2'b11) && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q72 = - requestR[194:192] == 3'h1 && requestR[159]; - endcase - end - always@(guard__h60544 or x__h60559 or _theResult___exp__h61186) - begin - case (guard__h60544) - 2'b0: - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_theR_ETC__q73 = - x__h60559[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_theR_ETC__q73 = - _theResult___exp__h61186; - endcase - end - always@(requestR or - x__h60559 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2349 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2347 or - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_theR_ETC__q73) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 = - x__h60559[10:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2349; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2347; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 = - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_theR_ETC__q73; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2353 = - 11'd0; - endcase - end - always@(guard__h60544 or - x__h60559 or out_exp__h61189 or _theResult___exp__h61186) - begin - case (guard__h60544) - 2'b0, 2'b01: - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_x055_ETC__q74 = - x__h60559[10:0]; - 2'b10: - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_x055_ETC__q74 = - out_exp__h61189; - 2'b11: - CASE_guard0544_0b0_x0559_BITS_10_TO_0_0b1_x055_ETC__q74 = - _theResult___exp__h61186; - endcase - end - always@(guard__h60544 or sfd___3__h59804 or _theResult___sfd__h61187) - begin - case (guard__h60544) - 2'b0: - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q75 = - sfd___3__h59804[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q75 = - _theResult___sfd__h61187; - endcase - end - always@(requestR or - sfd___3__h59804 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2390 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2388 or - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q75) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 = - sfd___3__h59804[53:2]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2390; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2388; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 = - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q75; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2394 = - 52'd0; - endcase - end - always@(guard__h60544 or - sfd___3__h59804 or out_sfd__h61190 or _theResult___sfd__h61187) - begin - case (guard__h60544) - 2'b0, 2'b01: - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q76 = - sfd___3__h59804[53:2]; - 2'b10: - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q76 = - out_sfd__h61190; - 2'b11: - CASE_guard0544_0b0_sfd___39804_BITS_53_TO_2_0b_ETC__q76 = - _theResult___sfd__h61187; - endcase - end - always@(guard__h59814 or _theResult___exp__h60430) - begin - case (guard__h59814) - 2'b0: CASE_guard9814_0b0_0_0b1_theResult___exp0430_0_ETC__q77 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard9814_0b0_0_0b1_theResult___exp0430_0_ETC__q77 = - _theResult___exp__h60430; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2321 or - guard__h59814 or - _theResult___exp__h60430 or - CASE_guard9814_0b0_0_0b1_theResult___exp0430_0_ETC__q77) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2321; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324 = - (guard__h59814 == 2'b0 || requestR[159]) ? - 11'd0 : - _theResult___exp__h60430; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324 = - CASE_guard9814_0b0_0_0b1_theResult___exp0430_0_ETC__q77; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2324 = - 11'd0; - endcase - end - always@(guard__h59814 or out_exp__h60433 or _theResult___exp__h60430) - begin - case (guard__h59814) - 2'b0, 2'b01: - CASE_guard9814_0b0_0_0b1_0_0b10_out_exp0433_0b_ETC__q78 = 11'd0; - 2'b10: - CASE_guard9814_0b0_0_0b1_0_0b10_out_exp0433_0b_ETC__q78 = - out_exp__h60433; - 2'b11: - CASE_guard9814_0b0_0_0b1_0_0b10_out_exp0433_0b_ETC__q78 = - _theResult___exp__h60430; - endcase - end - always@(guard__h59814 or sfd___3__h59804 or _theResult___sfd__h60431) - begin - case (guard__h59814) - 2'b0: - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q79 = - sfd___3__h59804[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q79 = - _theResult___sfd__h60431; - endcase - end - always@(requestR or - sfd___3__h59804 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2372 or - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2370 or - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q79) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 = - sfd___3__h59804[54:3]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2372; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 = - IF_IF_IF_requestR_3_BIT_159_6_THEN_NEG_request_ETC___d2370; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 = - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q79; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2376 = - 52'd0; - endcase - end - always@(guard__h59814 or - sfd___3__h59804 or out_sfd__h60434 or _theResult___sfd__h60431) - begin - case (guard__h59814) - 2'b0, 2'b01: - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q80 = - sfd___3__h59804[54:3]; - 2'b10: - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q80 = - out_sfd__h60434; - 2'b11: - CASE_guard9814_0b0_sfd___39804_BITS_54_TO_3_0b_ETC__q80 = - _theResult___sfd__h60431; - endcase - end - always@(guard__h69455 or out_exp__h70074 or _theResult___exp__h70071) - begin - case (guard__h69455) - 2'b0, 2'b01: - CASE_guard9455_0b0_0_0b1_0_0b10_out_exp0074_0b_ETC__q83 = 11'd0; - 2'b10: - CASE_guard9455_0b0_0_0b1_0_0b10_out_exp0074_0b_ETC__q83 = - out_exp__h70074; - 2'b11: - CASE_guard9455_0b0_0_0b1_0_0b10_out_exp0074_0b_ETC__q83 = - _theResult___exp__h70071; - endcase - end - always@(guard__h69455 or _theResult___exp__h70071) - begin - case (guard__h69455) - 2'b0: CASE_guard9455_0b0_0_0b1_theResult___exp0071_0_ETC__q84 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard9455_0b0_0_0b1_theResult___exp0071_0_ETC__q84 = - _theResult___exp__h70071; - endcase - end - always@(requestR or - guard__h69455 or - _theResult___exp__h70071 or - CASE_guard9455_0b0_0_0b1_theResult___exp0071_0_ETC__q84) - begin - case (requestR[194:192]) - 3'h3: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard9455_ETC__q85 = - (guard__h69455 == 2'b0) ? 11'd0 : _theResult___exp__h70071; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x3_IF_guard9455_ETC__q85 = - CASE_guard9455_0b0_0_0b1_theResult___exp0071_0_ETC__q84; - default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard9455_ETC__q85 = - 11'd0; - endcase - end - always@(guard__h70184 or x__h70199 or _theResult___exp__h70826) - begin - case (guard__h70184) - 2'b0: - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_theR_ETC__q86 = - x__h70199[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_theR_ETC__q86 = - _theResult___exp__h70826; - endcase - end - always@(requestR or - x__h70199 or - guard__h70184 or - _theResult___exp__h70826 or - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_theR_ETC__q86) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539 = - x__h70199[10:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539 = - (guard__h70184 == 2'b0) ? - x__h70199[10:0] : - _theResult___exp__h70826; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539 = - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_theR_ETC__q86; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2539 = - 11'd0; - endcase - end - always@(guard__h70184 or - x__h70199 or out_exp__h70829 or _theResult___exp__h70826) - begin - case (guard__h70184) - 2'b0, 2'b01: - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_x019_ETC__q87 = - x__h70199[10:0]; - 2'b10: - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_x019_ETC__q87 = - out_exp__h70829; - 2'b11: - CASE_guard0184_0b0_x0199_BITS_10_TO_0_0b1_x019_ETC__q87 = - _theResult___exp__h70826; - endcase - end - always@(guard__h70184 or sfd___3__h69445 or _theResult___sfd__h70827) - begin - case (guard__h70184) - 2'b0: - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q88 = - sfd___3__h69445[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q88 = - _theResult___sfd__h70827; - endcase - end - always@(requestR or - sfd___3__h69445 or - guard__h70184 or - _theResult___sfd__h70827 or - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q88) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576 = - sfd___3__h69445[53:2]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576 = - (guard__h70184 == 2'b0) ? - sfd___3__h69445[53:2] : - _theResult___sfd__h70827; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576 = - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q88; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2576 = - 52'd0; - endcase - end - always@(guard__h70184 or - sfd___3__h69445 or out_sfd__h70830 or _theResult___sfd__h70827) - begin - case (guard__h70184) - 2'b0, 2'b01: - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q89 = - sfd___3__h69445[53:2]; - 2'b10: - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q89 = - out_sfd__h70830; - 2'b11: - CASE_guard0184_0b0_sfd___39445_BITS_53_TO_2_0b_ETC__q89 = - _theResult___sfd__h70827; - endcase - end - always@(guard__h69455 or sfd___3__h69445 or _theResult___sfd__h70072) - begin - case (guard__h69455) - 2'b0: - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q90 = - sfd___3__h69445[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q90 = - _theResult___sfd__h70072; - endcase - end - always@(requestR or - sfd___3__h69445 or - guard__h69455 or - _theResult___sfd__h70072 or - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q90) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561 = - sfd___3__h69445[54:3]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561 = - (guard__h69455 == 2'b0) ? - sfd___3__h69445[54:3] : - _theResult___sfd__h70072; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561 = - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q90; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2561 = - 52'd0; - endcase - end - always@(guard__h69455 or - sfd___3__h69445 or out_sfd__h70075 or _theResult___sfd__h70072) - begin - case (guard__h69455) - 2'b0, 2'b01: - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q91 = - sfd___3__h69445[54:3]; - 2'b10: - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q91 = - out_sfd__h70075; - 2'b11: - CASE_guard9455_0b0_sfd___39445_BITS_54_TO_3_0b_ETC__q91 = - _theResult___sfd__h70072; - endcase - end - always@(guard__h83135 or requestR) - begin - case (guard__h83135) - 2'b0, 2'b01, 2'b10: - CASE_guard3135_0b0_requestR_BIT_191_0b1_reques_ETC__q94 = - requestR[191]; - 2'd3: - CASE_guard3135_0b0_requestR_BIT_191_0b1_reques_ETC__q94 = - guard__h83135 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h83135) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q95 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q95 = - (guard__h83135 == 2'b0) ? - requestR[191] : - (guard__h83135 == 2'b01 || guard__h83135 == 2'b10 || - guard__h83135 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q95 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h83865 or requestR) - begin - case (guard__h83865) - 2'b0, 2'b01, 2'b10: - CASE_guard3865_0b0_requestR_BIT_191_0b1_reques_ETC__q96 = - requestR[191]; - 2'd3: - CASE_guard3865_0b0_requestR_BIT_191_0b1_reques_ETC__q96 = - guard__h83865 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h83865) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q97 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q97 = - (guard__h83865 == 2'b0) ? - requestR[191] : - (guard__h83865 == 2'b01 || guard__h83865 == 2'b10 || - guard__h83865 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q97 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h83865 or x__h83880 or _theResult___exp__h84507) - begin - case (guard__h83865) - 2'b0: - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_theR_ETC__q98 = - x__h83880[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_theR_ETC__q98 = - _theResult___exp__h84507; - endcase - end - always@(requestR or - x__h83880 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2880 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2878 or - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_theR_ETC__q98) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 = - x__h83880[10:0]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2880; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2878; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 = - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_theR_ETC__q98; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2884 = - 11'd0; - endcase - end - always@(guard__h83865 or - x__h83880 or out_exp__h84510 or _theResult___exp__h84507) - begin - case (guard__h83865) - 2'b0, 2'b01: - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_x388_ETC__q99 = - x__h83880[10:0]; - 2'b10: - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_x388_ETC__q99 = - out_exp__h84510; - 2'b11: - CASE_guard3865_0b0_x3880_BITS_10_TO_0_0b1_x388_ETC__q99 = - _theResult___exp__h84507; - endcase - end - always@(guard__h83865 or sfd___3__h12218 or _theResult___sfd__h84508) - begin - case (guard__h83865) - 2'b0: - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q100 = - sfd___3__h12218[62:11]; - 2'b01, 2'b10, 2'b11: - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q100 = - _theResult___sfd__h84508; - endcase - end - always@(requestR or - sfd___3__h12218 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2921 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2919 or - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q100) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 = - sfd___3__h12218[62:11]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2921; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2919; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 = - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q100; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2925 = - 52'd0; - endcase - end - always@(guard__h83865 or - sfd___3__h12218 or out_sfd__h84511 or _theResult___sfd__h84508) - begin - case (guard__h83865) - 2'b0, 2'b01: - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q101 = - sfd___3__h12218[62:11]; - 2'b10: - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q101 = - out_sfd__h84511; - 2'b11: - CASE_guard3865_0b0_sfd___32218_BITS_62_TO_11_0_ETC__q101 = - _theResult___sfd__h84508; - endcase - end - always@(guard__h83135 or _theResult___exp__h83751) - begin - case (guard__h83135) - 2'b0: CASE_guard3135_0b0_0_0b1_theResult___exp3751_0_ETC__q102 = 11'd0; - 2'b01, 2'b10, 2'b11: - CASE_guard3135_0b0_0_0b1_theResult___exp3751_0_ETC__q102 = - _theResult___exp__h83751; - endcase - end - always@(requestR or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2852 or - guard__h83135 or - _theResult___exp__h83751 or - CASE_guard3135_0b0_0_0b1_theResult___exp3751_0_ETC__q102) - begin - case (requestR[194:192]) - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2852; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855 = - (guard__h83135 == 2'b0 || requestR[191]) ? - 11'd0 : - _theResult___exp__h83751; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855 = - CASE_guard3135_0b0_0_0b1_theResult___exp3751_0_ETC__q102; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2855 = - 11'd0; - endcase - end - always@(guard__h83135 or out_exp__h83754 or _theResult___exp__h83751) - begin - case (guard__h83135) - 2'b0, 2'b01: - CASE_guard3135_0b0_0_0b1_0_0b10_out_exp3754_0b_ETC__q103 = 11'd0; - 2'b10: - CASE_guard3135_0b0_0_0b1_0_0b10_out_exp3754_0b_ETC__q103 = - out_exp__h83754; - 2'b11: - CASE_guard3135_0b0_0_0b1_0_0b10_out_exp3754_0b_ETC__q103 = - _theResult___exp__h83751; - endcase - end - always@(guard__h83135 or sfd___3__h12218 or _theResult___sfd__h83752) - begin - case (guard__h83135) - 2'b0: - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q104 = - sfd___3__h12218[63:12]; - 2'b01, 2'b10, 2'b11: - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q104 = - _theResult___sfd__h83752; - endcase - end - always@(requestR or - sfd___3__h12218 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2903 or - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2901 or - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q104) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 = - sfd___3__h12218[63:12]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2903; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 = - IF_IF_IF_requestR_3_BIT_191_47_THEN_NEG_reques_ETC___d2901; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 = - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q104; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d2907 = - 52'd0; - endcase - end - always@(guard__h83135 or - sfd___3__h12218 or out_sfd__h83755 or _theResult___sfd__h83752) - begin - case (guard__h83135) - 2'b0, 2'b01: - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q105 = - sfd___3__h12218[63:12]; - 2'b10: - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q105 = - out_sfd__h83755; - 2'b11: - CASE_guard3135_0b0_sfd___32218_BITS_63_TO_12_0_ETC__q105 = - _theResult___sfd__h83752; - endcase - end - always@(guard__h94821 or x__h94836 or _theResult___exp__h95463) - begin - case (guard__h94821) - 2'b0: - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_theR_ETC__q106 = - x__h94836[10:0]; - 2'b01, 2'b10, 2'b11: - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_theR_ETC__q106 = - _theResult___exp__h95463; - endcase - end - always@(requestR or - x__h94836 or - guard__h94821 or - _theResult___exp__h95463 or - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_theR_ETC__q106) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039 = - x__h94836[10:0]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039 = - (guard__h94821 == 2'b0) ? - x__h94836[10:0] : - _theResult___exp__h95463; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039 = - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_theR_ETC__q106; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3039 = - 11'd0; - endcase - end - always@(guard__h94821 or - x__h94836 or out_exp__h95466 or _theResult___exp__h95463) - begin - case (guard__h94821) - 2'b0, 2'b01: - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_x483_ETC__q107 = - x__h94836[10:0]; - 2'b10: - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_x483_ETC__q107 = - out_exp__h95466; - 2'b11: - CASE_guard4821_0b0_x4836_BITS_10_TO_0_0b1_x483_ETC__q107 = - _theResult___exp__h95463; - endcase - end - always@(guard__h94821 or sfd___3__h22785 or _theResult___sfd__h95464) - begin - case (guard__h94821) - 2'b0: - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q108 = - sfd___3__h22785[62:11]; - 2'b01, 2'b10, 2'b11: - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q108 = - _theResult___sfd__h95464; - endcase - end - always@(requestR or - sfd___3__h22785 or - guard__h94821 or - _theResult___sfd__h95464 or - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q108) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077 = - sfd___3__h22785[62:11]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077 = - (guard__h94821 == 2'b0) ? - sfd___3__h22785[62:11] : - _theResult___sfd__h95464; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077 = - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q108; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3077 = - 52'd0; - endcase - end - always@(guard__h94821 or - sfd___3__h22785 or out_sfd__h95467 or _theResult___sfd__h95464) - begin - case (guard__h94821) - 2'b0, 2'b01: - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q109 = - sfd___3__h22785[62:11]; - 2'b10: - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q109 = - out_sfd__h95467; - 2'b11: - CASE_guard4821_0b0_sfd___32785_BITS_62_TO_11_0_ETC__q109 = - _theResult___sfd__h95464; - endcase - end - always@(guard__h94092 or sfd___3__h22785 or _theResult___sfd__h94709) - begin - case (guard__h94092) - 2'b0: - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q110 = - sfd___3__h22785[63:12]; - 2'b01, 2'b10, 2'b11: - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q110 = - _theResult___sfd__h94709; - endcase - end - always@(requestR or - sfd___3__h22785 or - guard__h94092 or - _theResult___sfd__h94709 or - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q110) - begin - case (requestR[194:192]) - 3'h1, 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062 = - sfd___3__h22785[63:12]; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062 = - (guard__h94092 == 2'b0) ? - sfd___3__h22785[63:12] : - _theResult___sfd__h94709; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062 = - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q110; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3062 = - 52'd0; - endcase - end - always@(guard__h94092 or - sfd___3__h22785 or out_sfd__h94712 or _theResult___sfd__h94709) - begin - case (guard__h94092) - 2'b0, 2'b01: - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q111 = - sfd___3__h22785[63:12]; - 2'b10: - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q111 = - out_sfd__h94712; - 2'b11: - CASE_guard4092_0b0_sfd___32785_BITS_63_TO_12_0_ETC__q111 = - _theResult___sfd__h94709; - endcase - end - always@(guard__h110454 or - _theResult___fst_exp__h118551 or _theResult___exp__h119077) - begin - case (guard__h110454) - 2'b0: - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q124 = - _theResult___fst_exp__h118551; - 2'b01, 2'b10, 2'b11: - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q124 = - _theResult___exp__h119077; - endcase - end - always@(requestR or - _theResult___fst_exp__h118551 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3601 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3599 or - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q124) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 = - _theResult___fst_exp__h118551; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3601; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d3599; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 = - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q124; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3605 = - 8'd0; - endcase - end - always@(guard__h110454 or - _theResult___fst_exp__h118551 or - out_exp__h119080 or _theResult___exp__h119077) - begin - case (guard__h110454) - 2'b0, 2'b01: - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q125 = - _theResult___fst_exp__h118551; - 2'b10: - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q125 = - out_exp__h119080; - 2'b11: - CASE_guard10454_0b0_theResult___fst_exp18551_0_ETC__q125 = - _theResult___exp__h119077; - endcase - end - always@(guard__h128178 or - _theResult___fst_exp__h136404 or _theResult___exp__h136930) - begin - case (guard__h128178) - 2'b0: - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q126 = - _theResult___fst_exp__h136404; - 2'b01, 2'b10, 2'b11: - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q126 = - _theResult___exp__h136930; - endcase - end - always@(requestR or - _theResult___fst_exp__h136404 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4045 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4043 or - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q126) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 = - _theResult___fst_exp__h136404; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4045; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4043; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 = - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q126; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4049 = - 8'd0; - endcase - end - always@(guard__h128178 or - _theResult___fst_exp__h136404 or - out_exp__h136933 or _theResult___exp__h136930) - begin - case (guard__h128178) - 2'b0, 2'b01: - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q127 = - _theResult___fst_exp__h136404; - 2'b10: - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q127 = - out_exp__h136933; - 2'b11: - CASE_guard28178_0b0_theResult___fst_exp36404_0_ETC__q127 = - _theResult___exp__h136930; - endcase - end - always@(guard__h119189 or - _theResult___fst_exp__h127237 or _theResult___exp__h127689) - begin - case (guard__h119189) - 2'b0: - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q128 = - _theResult___fst_exp__h127237; - 2'b01, 2'b10, 2'b11: - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q128 = - _theResult___exp__h127689; - endcase - end - always@(requestR or - _theResult___fst_exp__h127237 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3718 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3716 or - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q128) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 = - _theResult___fst_exp__h127237; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3718; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d3716; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 = - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q128; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d3722 = - 8'd0; - endcase - end - always@(guard__h119189 or - _theResult___fst_exp__h127237 or - out_exp__h127692 or _theResult___exp__h127689) - begin - case (guard__h119189) - 2'b0, 2'b01: - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q129 = - _theResult___fst_exp__h127237; - 2'b10: - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q129 = - out_exp__h127692; - 2'b11: - CASE_guard19189_0b0_theResult___fst_exp27237_0_ETC__q129 = - _theResult___exp__h127689; - endcase - end - always@(guard__h137042 or - _theResult___fst_exp__h145119 or _theResult___exp__h145596) - begin - case (guard__h137042) - 2'b0: - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q130 = - _theResult___fst_exp__h145119; - 2'b01, 2'b10, 2'b11: - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q130 = - _theResult___exp__h145596; - endcase - end - always@(requestR or - _theResult___fst_exp__h145119 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4114 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4112 or - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q130) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 = - _theResult___fst_exp__h145119; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4114; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4112; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 = - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q130; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4118 = - 8'd0; - endcase - end - always@(guard__h137042 or - _theResult___fst_exp__h145119 or - out_exp__h145599 or _theResult___exp__h145596) - begin - case (guard__h137042) - 2'b0, 2'b01: - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q131 = - _theResult___fst_exp__h145119; - 2'b10: - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q131 = - out_exp__h145599; - 2'b11: - CASE_guard37042_0b0_theResult___fst_exp45119_0_ETC__q131 = - _theResult___exp__h145596; - endcase - end - always@(guard__h110454 or sfdin__h118545 or _theResult___sfd__h119078) - begin - case (guard__h110454) - 2'b0: - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q132 = - sfdin__h118545[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q132 = - _theResult___sfd__h119078; - endcase - end - always@(requestR or - sfdin__h118545 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4148 or - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4146 or - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q132) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 = - sfdin__h118545[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4148; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 = - IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_3_BITS_190_ETC___d4146; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 = - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q132; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4152 = - 23'd0; - endcase - end - always@(guard__h110454 or - sfdin__h118545 or out_sfd__h119081 or _theResult___sfd__h119078) - begin - case (guard__h110454) - 2'b0, 2'b01: - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q133 = - sfdin__h118545[56:34]; - 2'b10: - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q133 = - out_sfd__h119081; - 2'b11: - CASE_guard10454_0b0_sfdin18545_BITS_56_TO_34_0_ETC__q133 = - _theResult___sfd__h119078; - endcase - end - always@(guard__h119189 or - _theResult___snd__h127188 or _theResult___sfd__h127690) - begin - case (guard__h119189) - 2'b0: - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q134 = - _theResult___snd__h127188[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q134 = - _theResult___sfd__h127690; - endcase - end - always@(requestR or - _theResult___snd__h127188 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4167 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4165 or - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q134) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 = - _theResult___snd__h127188[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4167; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4165; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 = - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q134; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4171 = - 23'd0; - endcase - end - always@(guard__h119189 or - _theResult___snd__h127188 or - out_sfd__h127693 or _theResult___sfd__h127690) - begin - case (guard__h119189) - 2'b0, 2'b01: - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q135 = - _theResult___snd__h127188[56:34]; - 2'b10: - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q135 = - out_sfd__h127693; - 2'b11: - CASE_guard19189_0b0_theResult___snd27188_BITS__ETC__q135 = - _theResult___sfd__h127690; - endcase - end - always@(guard__h128178 or sfdin__h136398 or _theResult___sfd__h136931) - begin - case (guard__h128178) - 2'b0: - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q136 = - sfdin__h136398[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q136 = - _theResult___sfd__h136931; - endcase - end - always@(requestR or - sfdin__h136398 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4194 or - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4192 or - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q136) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 = - sfdin__h136398[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4194; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 = - IF_IF_IF_IF_3970_MINUS_SEXT_requestR_3_BITS_19_ETC___d4192; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 = - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q136; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4198 = - 23'd0; - endcase - end - always@(guard__h128178 or - sfdin__h136398 or out_sfd__h136934 or _theResult___sfd__h136931) - begin - case (guard__h128178) - 2'b0, 2'b01: - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q137 = - sfdin__h136398[56:34]; - 2'b10: - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q137 = - out_sfd__h136934; - 2'b11: - CASE_guard28178_0b0_sfdin36398_BITS_56_TO_34_0_ETC__q137 = - _theResult___sfd__h136931; - endcase - end - always@(guard__h137042 or - _theResult___snd__h145065 or _theResult___sfd__h145597) - begin - case (guard__h137042) - 2'b0: - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q138 = - _theResult___snd__h145065[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q138 = - _theResult___sfd__h145597; - endcase - end - always@(requestR or - _theResult___snd__h145065 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4213 or - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4211 or - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q138) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 = - _theResult___snd__h145065[56:34]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4213; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 = - IF_IF_IF_requestR_3_BITS_190_TO_180_608_EQ_0_6_ETC___d4211; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 = - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q138; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4217 = - 23'd0; - endcase - end - always@(guard__h137042 or - _theResult___snd__h145065 or - out_sfd__h145600 or _theResult___sfd__h145597) - begin - case (guard__h137042) - 2'b0, 2'b01: - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q139 = - _theResult___snd__h145065[56:34]; - 2'b10: - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q139 = - out_sfd__h145600; - 2'b11: - CASE_guard37042_0b0_theResult___snd45065_BITS__ETC__q139 = - _theResult___sfd__h145597; - endcase - end - always@(guard__h110454 or requestR) - begin - case (guard__h110454) - 2'b0, 2'b01, 2'b10: - CASE_guard10454_0b0_requestR_BIT_191_0b1_reque_ETC__q140 = - requestR[191]; - 2'd3: - CASE_guard10454_0b0_requestR_BIT_191_0b1_reque_ETC__q140 = - guard__h110454 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h110454) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q141 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q141 = - (guard__h110454 == 2'b0) ? - requestR[191] : - (guard__h110454 == 2'b01 || guard__h110454 == 2'b10 || - guard__h110454 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q141 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h119189 or requestR) - begin - case (guard__h119189) - 2'b0, 2'b01, 2'b10: - CASE_guard19189_0b0_requestR_BIT_191_0b1_reque_ETC__q142 = - requestR[191]; - 2'd3: - CASE_guard19189_0b0_requestR_BIT_191_0b1_reque_ETC__q142 = - guard__h119189 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h119189) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q143 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q143 = - (guard__h119189 == 2'b0) ? - requestR[191] : - (guard__h119189 == 2'b01 || guard__h119189 == 2'b10 || - guard__h119189 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q143 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h128178 or requestR) - begin - case (guard__h128178) - 2'b0, 2'b01, 2'b10: - CASE_guard28178_0b0_requestR_BIT_191_0b1_reque_ETC__q144 = - requestR[191]; - 2'd3: - CASE_guard28178_0b0_requestR_BIT_191_0b1_reque_ETC__q144 = - guard__h128178 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h128178) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q145 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q145 = - (guard__h128178 == 2'b0) ? - requestR[191] : - (guard__h128178 == 2'b01 || guard__h128178 == 2'b10 || - guard__h128178 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q145 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h137042 or requestR) - begin - case (guard__h137042) - 2'b0, 2'b01, 2'b10: - CASE_guard37042_0b0_requestR_BIT_191_0b1_reque_ETC__q146 = - requestR[191]; - 2'd3: - CASE_guard37042_0b0_requestR_BIT_191_0b1_reque_ETC__q146 = - guard__h137042 == 2'b11 && requestR[191]; - endcase - end - always@(requestR or guard__h137042) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q147 = - requestR[191]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q147 = - (guard__h137042 == 2'b0) ? - requestR[191] : - (guard__h137042 == 2'b01 || guard__h137042 == 2'b10 || - guard__h137042 == 2'b11) && - requestR[191]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q147 = - requestR[194:192] == 3'h1 && requestR[191]; - endcase - end - always@(guard__h160150 or - _theResult___fst_exp__h168111 or _theResult___exp__h168766) - begin - case (guard__h160150) - 2'b0: - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q156 = - _theResult___fst_exp__h168111; - 2'b01, 2'b10, 2'b11: - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q156 = - _theResult___exp__h168766; - endcase - end - always@(requestR or - _theResult___fst_exp__h168111 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4553 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4551 or - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q156) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 = - _theResult___fst_exp__h168111; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4553; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4551; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 = - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q156; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4557 = - 11'd0; - endcase - end - always@(guard__h160150 or - _theResult___fst_exp__h168111 or - out_exp__h168769 or _theResult___exp__h168766) - begin - case (guard__h160150) - 2'b0, 2'b01: - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q157 = - _theResult___fst_exp__h168111; - 2'b10: - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q157 = - out_exp__h168769; - 2'b11: - CASE_guard60150_0b0_theResult___fst_exp68111_0_ETC__q157 = - _theResult___exp__h168766; - endcase - end - always@(guard__h169458 or - _theResult___fst_exp__h177684 or _theResult___exp__h178413) - begin - case (guard__h169458) - 2'b0: - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q158 = - _theResult___fst_exp__h177684; - 2'b01, 2'b10, 2'b11: - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q158 = - _theResult___exp__h178413; - endcase - end - always@(requestR or - _theResult___fst_exp__h177684 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4878 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4876 or - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q158) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 = - _theResult___fst_exp__h177684; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4878; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d4876; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 = - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q158; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4882 = - 11'd0; - endcase - end - always@(guard__h169458 or - _theResult___fst_exp__h177684 or - out_exp__h178416 or _theResult___exp__h178413) - begin - case (guard__h169458) - 2'b0, 2'b01: - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q159 = - _theResult___fst_exp__h177684; - 2'b10: - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q159 = - out_exp__h178416; - 2'b11: - CASE_guard69458_0b0_theResult___fst_exp77684_0_ETC__q159 = - _theResult___exp__h178413; - endcase - end - always@(guard__h178525 or - _theResult___fst_exp__h186515 or _theResult___exp__h187195) - begin - case (guard__h178525) - 2'b0: - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q160 = - _theResult___fst_exp__h186515; - 2'b01, 2'b10, 2'b11: - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q160 = - _theResult___exp__h187195; - endcase - end - always@(requestR or - _theResult___fst_exp__h186515 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4947 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4945 or - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q160) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 = - _theResult___fst_exp__h186515; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4947; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4945; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 = - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q160; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4951 = - 11'd0; - endcase - end - always@(guard__h178525 or - _theResult___fst_exp__h186515 or - out_exp__h187198 or _theResult___exp__h187195) - begin - case (guard__h178525) - 2'b0, 2'b01: - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q161 = - _theResult___fst_exp__h186515; - 2'b10: - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q161 = - out_exp__h187198; - 2'b11: - CASE_guard78525_0b0_theResult___fst_exp86515_0_ETC__q161 = - _theResult___exp__h187195; - endcase - end - always@(guard__h160150 or requestR) - begin - case (guard__h160150) - 2'b0, 2'b01, 2'b10: - CASE_guard60150_0b0_requestR_BITS_191_TO_160_E_ETC__q162 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard60150_0b0_requestR_BITS_191_TO_160_E_ETC__q162 = - guard__h160150 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h160150) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q163 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q163 = - (guard__h160150 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h160150 == 2'b01 || guard__h160150 == 2'b10 || - guard__h160150 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q163 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h169458 or requestR) - begin - case (guard__h169458) - 2'b0, 2'b01, 2'b10: - CASE_guard69458_0b0_requestR_BITS_191_TO_160_E_ETC__q164 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard69458_0b0_requestR_BITS_191_TO_160_E_ETC__q164 = - guard__h169458 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h169458) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q165 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q165 = - (guard__h169458 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h169458 == 2'b01 || guard__h169458 == 2'b10 || - guard__h169458 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q165 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h178525 or requestR) - begin - case (guard__h178525) - 2'b0, 2'b01, 2'b10: - CASE_guard78525_0b0_requestR_BITS_191_TO_160_E_ETC__q166 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 2'd3: - CASE_guard78525_0b0_requestR_BITS_191_TO_160_E_ETC__q166 = - guard__h178525 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(requestR or guard__h178525) - begin - case (requestR[194:192]) - 3'h2, 3'h3: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q167 = - requestR[191:160] == 32'hFFFFFFFF && requestR[159]; - 3'h4: - CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q167 = - (guard__h178525 == 2'b0) ? - requestR[191:160] == 32'hFFFFFFFF && requestR[159] : - (guard__h178525 == 2'b01 || guard__h178525 == 2'b10 || - guard__h178525 == 2'b11) && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q167 = - requestR[194:192] == 3'h1 && - requestR[191:160] == 32'hFFFFFFFF && - requestR[159]; - endcase - end - always@(guard__h160150 or - _theResult___snd__h168062 or _theResult___sfd__h168767) - begin - case (guard__h160150) - 2'b0: - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q168 = - _theResult___snd__h168062[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q168 = - _theResult___sfd__h168767; - endcase - end - always@(requestR or - _theResult___snd__h168062 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4980 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4978 or - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q168) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 = - _theResult___snd__h168062[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4980; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d4978; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 = - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q168; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d4984 = - 52'd0; - endcase - end - always@(guard__h160150 or - _theResult___snd__h168062 or - out_sfd__h168770 or _theResult___sfd__h168767) - begin - case (guard__h160150) - 2'b0, 2'b01: - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q169 = - _theResult___snd__h168062[56:5]; - 2'b10: - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q169 = - out_sfd__h168770; - 2'b11: - CASE_guard60150_0b0_theResult___snd68062_BITS__ETC__q169 = - _theResult___sfd__h168767; - endcase - end - always@(guard__h169458 or sfdin__h177678 or _theResult___sfd__h178414) - begin - case (guard__h169458) - 2'b0: - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q170 = - sfdin__h177678[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q170 = - _theResult___sfd__h178414; - endcase - end - always@(requestR or - sfdin__h177678 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5007 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5005 or - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q170) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 = - sfdin__h177678[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5007; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_3_BITS_ETC___d5005; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 = - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q170; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5011 = - 52'd0; - endcase - end - always@(guard__h169458 or - sfdin__h177678 or out_sfd__h178417 or _theResult___sfd__h178414) - begin - case (guard__h169458) - 2'b0, 2'b01: - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q171 = - sfdin__h177678[56:5]; - 2'b10: - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q171 = - out_sfd__h178417; - 2'b11: - CASE_guard69458_0b0_sfdin77678_BITS_56_TO_5_0b_ETC__q171 = - _theResult___sfd__h178414; - endcase - end - always@(guard__h178525 or - _theResult___snd__h186461 or _theResult___sfd__h187196) - begin - case (guard__h178525) - 2'b0: - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q172 = - _theResult___snd__h186461[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q172 = - _theResult___sfd__h187196; - endcase - end - always@(requestR or - _theResult___snd__h186461 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5026 or - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5024 or - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q172) - begin - case (requestR[194:192]) - 3'h1: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 = - _theResult___snd__h186461[56:5]; - 3'h2: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5026; - 3'h3: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 = - IF_IF_IF_IF_requestR_3_BITS_191_TO_160_4_EQ_0x_ETC___d5024; - 3'h4: - IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 = - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q172; - default: IF_requestR_3_BITS_194_TO_192_0_EQ_0x4_5_THEN__ETC___d5030 = - 52'd0; - endcase - end - always@(guard__h178525 or - _theResult___snd__h186461 or - out_sfd__h187199 or _theResult___sfd__h187196) - begin - case (guard__h178525) - 2'b0, 2'b01: - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q173 = - _theResult___snd__h186461[56:5]; - 2'b10: - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q173 = - out_sfd__h187199; - 2'b11: - CASE_guard78525_0b0_theResult___snd86461_BITS__ETC__q173 = - _theResult___sfd__h187196; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - stateR <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (stateR$EN) stateR <= `BSV_ASSIGNMENT_DELAY stateR$D_IN; - end - if (requestR$EN) requestR <= `BSV_ASSIGNMENT_DELAY requestR$D_IN; - if (resultR$EN) resultR <= `BSV_ASSIGNMENT_DELAY resultR$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - requestR = 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - resultR = 70'h2AAAAAAAAAAAAAAAAA; - stateR = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkFBox_Core - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Top.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Top.v deleted file mode 100644 index 916b8699..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFBox_Top.v +++ /dev/null @@ -1,184 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// valid O 1 -// word_fst O 64 -// word_snd O 5 -// CLK I 1 clock -// RST_N I 1 reset -// req_opcode I 7 -// req_f7 I 7 -// req_rm I 3 -// req_rs2 I 5 -// req_v1 I 64 -// req_v2 I 64 -// req_v3 I 64 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFBox_Top(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_opcode, - req_f7, - req_rm, - req_rs2, - req_v1, - req_v2, - req_v3, - EN_req, - - valid, - - word_fst, - - word_snd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [6 : 0] req_opcode; - input [6 : 0] req_f7; - input [2 : 0] req_rm; - input [4 : 0] req_rs2; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input [63 : 0] req_v3; - input EN_req; - - // value method valid - output valid; - - // value method word_fst - output [63 : 0] word_fst; - - // value method word_snd - output [4 : 0] word_snd; - - // signals for module outputs - wire [63 : 0] word_fst; - wire [4 : 0] word_snd; - wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid; - - // ports of submodule fbox_core - wire [63 : 0] fbox_core$req_v1, - fbox_core$req_v2, - fbox_core$req_v3, - fbox_core$word_fst; - wire [6 : 0] fbox_core$req_f7, fbox_core$req_opcode; - wire [4 : 0] fbox_core$req_rs2, fbox_core$word_snd; - wire [2 : 0] fbox_core$req_rm; - wire fbox_core$EN_req, - fbox_core$EN_server_reset_request_put, - fbox_core$EN_server_reset_response_get, - fbox_core$RDY_server_reset_request_put, - fbox_core$RDY_server_reset_response_get, - fbox_core$valid; - - // rule scheduling signals - wire CAN_FIRE_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = - fbox_core$RDY_server_reset_request_put ; - assign CAN_FIRE_server_reset_request_put = - fbox_core$RDY_server_reset_request_put ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - fbox_core$RDY_server_reset_response_get ; - assign CAN_FIRE_server_reset_response_get = - fbox_core$RDY_server_reset_response_get ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = fbox_core$valid ; - - // value method word_fst - assign word_fst = fbox_core$word_fst ; - - // value method word_snd - assign word_snd = fbox_core$word_snd ; - - // submodule fbox_core - mkFBox_Core fbox_core(.CLK(CLK), - .RST_N(RST_N), - .req_f7(fbox_core$req_f7), - .req_opcode(fbox_core$req_opcode), - .req_rm(fbox_core$req_rm), - .req_rs2(fbox_core$req_rs2), - .req_v1(fbox_core$req_v1), - .req_v2(fbox_core$req_v2), - .req_v3(fbox_core$req_v3), - .EN_server_reset_request_put(fbox_core$EN_server_reset_request_put), - .EN_server_reset_response_get(fbox_core$EN_server_reset_response_get), - .EN_req(fbox_core$EN_req), - .RDY_server_reset_request_put(fbox_core$RDY_server_reset_request_put), - .RDY_server_reset_response_get(fbox_core$RDY_server_reset_response_get), - .valid(fbox_core$valid), - .word_fst(fbox_core$word_fst), - .word_snd(fbox_core$word_snd)); - - // submodule fbox_core - assign fbox_core$req_f7 = req_f7 ; - assign fbox_core$req_opcode = req_opcode ; - assign fbox_core$req_rm = req_rm ; - assign fbox_core$req_rs2 = req_rs2 ; - assign fbox_core$req_v1 = req_v1 ; - assign fbox_core$req_v2 = req_v2 ; - assign fbox_core$req_v3 = req_v3 ; - assign fbox_core$EN_server_reset_request_put = EN_server_reset_request_put ; - assign fbox_core$EN_server_reset_response_get = - EN_server_reset_response_get ; - assign fbox_core$EN_req = EN_req ; -endmodule // mkFBox_Top - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPR_RegFile.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPR_RegFile.v deleted file mode 100644 index ae1589d4..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPR_RegFile.v +++ /dev/null @@ -1,258 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 64 -// read_rs1_port2 O 64 -// read_rs2 O 64 -// read_rs3 O 64 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// read_rs3_rs3 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - read_rs3_rs3, - read_rs3, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [63 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [63 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [63 : 0] read_rs2; - - // value method read_rs3 - input [4 : 0] read_rs3_rs3; - output [63 : 0] read_rs3; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [63 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [63 : 0] read_rs1, read_rs1_port2, read_rs2, read_rs3; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [63 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3, - regfile$D_OUT_4; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = regfile$D_OUT_4 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = regfile$D_OUT_3 ; - - // value method read_rs2 - assign read_rs2 = regfile$D_OUT_2 ; - - // value method read_rs3 - assign read_rs3 = regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd64), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(regfile$D_OUT_4), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs3_rs3 ; - assign regfile$ADDR_2 = read_rs2_rs2 ; - assign regfile$ADDR_3 = read_rs1_port2_rs1 ; - assign regfile$ADDR_4 = read_rs1_rs1 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkFPR_RegFile - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPU.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPU.v deleted file mode 100644 index ec7dfc10..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFPU.v +++ /dev/null @@ -1,12705 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_core_request_put O 1 reg -// server_core_response_get O 70 reg -// RDY_server_core_response_get O 1 reg -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// server_core_request_put I 202 reg -// EN_server_core_request_put I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_server_core_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFPU(CLK, - RST_N, - - server_core_request_put, - EN_server_core_request_put, - RDY_server_core_request_put, - - EN_server_core_response_get, - server_core_response_get, - RDY_server_core_response_get, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get); - input CLK; - input RST_N; - - // action method server_core_request_put - input [201 : 0] server_core_request_put; - input EN_server_core_request_put; - output RDY_server_core_request_put; - - // actionvalue method server_core_response_get - input EN_server_core_response_get; - output [69 : 0] server_core_response_get; - output RDY_server_core_response_get; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // signals for module outputs - wire [69 : 0] server_core_response_get; - wire RDY_server_core_request_put, - RDY_server_core_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get; - - // inlined wires - reg [68 : 0] resWire$wget; - wire crg_done$EN_port0__write, - crg_done$EN_port1__write, - crg_done$port1__read, - crg_done$port2__read, - crg_done_1$EN_port0__write, - crg_done_1$EN_port1__write, - crg_done_1$port1__read, - crg_done_1$port2__read, - resWire$whas; - - // register crg_done - reg crg_done; - wire crg_done$D_IN, crg_done$EN; - - // register crg_done_1 - reg crg_done_1; - wire crg_done_1$D_IN, crg_done_1$EN; - - // register rg_b - reg [115 : 0] rg_b; - wire [115 : 0] rg_b$D_IN; - wire rg_b$EN; - - // register rg_busy - reg rg_busy; - wire rg_busy$D_IN, rg_busy$EN; - - // register rg_busy_1 - reg rg_busy_1; - wire rg_busy_1$D_IN, rg_busy_1$EN; - - // register rg_d - reg [57 : 0] rg_d; - wire [57 : 0] rg_d$D_IN; - wire rg_d$EN; - - // register rg_index - reg [5 : 0] rg_index; - wire [5 : 0] rg_index$D_IN; - wire rg_index$EN; - - // register rg_index_1 - reg [5 : 0] rg_index_1; - wire [5 : 0] rg_index_1$D_IN; - wire rg_index_1$EN; - - // register rg_q - reg [57 : 0] rg_q; - wire [57 : 0] rg_q$D_IN; - wire rg_q$EN; - - // register rg_r - reg [115 : 0] rg_r; - wire [115 : 0] rg_r$D_IN; - wire rg_r$EN; - - // register rg_r_1 - reg [115 : 0] rg_r_1; - wire [115 : 0] rg_r_1$D_IN; - wire rg_r_1$EN; - - // register rg_res - reg [116 : 0] rg_res; - wire [116 : 0] rg_res$D_IN; - wire rg_res$EN; - - // register rg_s - reg [115 : 0] rg_s; - wire [115 : 0] rg_s$D_IN; - wire rg_s$EN; - - // ports of submodule fpu_div64_fOperands_S0 - wire [130 : 0] fpu_div64_fOperands_S0$D_IN, fpu_div64_fOperands_S0$D_OUT; - wire fpu_div64_fOperands_S0$CLR, - fpu_div64_fOperands_S0$DEQ, - fpu_div64_fOperands_S0$EMPTY_N, - fpu_div64_fOperands_S0$ENQ, - fpu_div64_fOperands_S0$FULL_N; - - // ports of submodule fpu_div64_fResult_S5 - wire [68 : 0] fpu_div64_fResult_S5$D_IN, fpu_div64_fResult_S5$D_OUT; - wire fpu_div64_fResult_S5$CLR, - fpu_div64_fResult_S5$DEQ, - fpu_div64_fResult_S5$EMPTY_N, - fpu_div64_fResult_S5$ENQ, - fpu_div64_fResult_S5$FULL_N; - - // ports of submodule fpu_div64_fState_S1 - wire [318 : 0] fpu_div64_fState_S1$D_IN, fpu_div64_fState_S1$D_OUT; - wire fpu_div64_fState_S1$CLR, - fpu_div64_fState_S1$DEQ, - fpu_div64_fState_S1$EMPTY_N, - fpu_div64_fState_S1$ENQ, - fpu_div64_fState_S1$FULL_N; - - // ports of submodule fpu_div64_fState_S2 - wire [147 : 0] fpu_div64_fState_S2$D_IN, fpu_div64_fState_S2$D_OUT; - wire fpu_div64_fState_S2$CLR, - fpu_div64_fState_S2$DEQ, - fpu_div64_fState_S2$EMPTY_N, - fpu_div64_fState_S2$ENQ, - fpu_div64_fState_S2$FULL_N; - - // ports of submodule fpu_div64_fState_S3 - wire [194 : 0] fpu_div64_fState_S3$D_IN, fpu_div64_fState_S3$D_OUT; - wire fpu_div64_fState_S3$CLR, - fpu_div64_fState_S3$DEQ, - fpu_div64_fState_S3$EMPTY_N, - fpu_div64_fState_S3$ENQ, - fpu_div64_fState_S3$FULL_N; - - // ports of submodule fpu_div64_fState_S4 - wire [138 : 0] fpu_div64_fState_S4$D_IN, fpu_div64_fState_S4$D_OUT; - wire fpu_div64_fState_S4$CLR, - fpu_div64_fState_S4$DEQ, - fpu_div64_fState_S4$EMPTY_N, - fpu_div64_fState_S4$ENQ, - fpu_div64_fState_S4$FULL_N; - - // ports of submodule fpu_madd_fOperand_S0 - wire [195 : 0] fpu_madd_fOperand_S0$D_IN, fpu_madd_fOperand_S0$D_OUT; - wire fpu_madd_fOperand_S0$CLR, - fpu_madd_fOperand_S0$DEQ, - fpu_madd_fOperand_S0$EMPTY_N, - fpu_madd_fOperand_S0$ENQ, - fpu_madd_fOperand_S0$FULL_N; - - // ports of submodule fpu_madd_fProd_S2 - wire [105 : 0] fpu_madd_fProd_S2$D_IN, fpu_madd_fProd_S2$D_OUT; - wire fpu_madd_fProd_S2$CLR, - fpu_madd_fProd_S2$DEQ, - fpu_madd_fProd_S2$EMPTY_N, - fpu_madd_fProd_S2$ENQ, - fpu_madd_fProd_S2$FULL_N; - - // ports of submodule fpu_madd_fProd_S3 - wire [105 : 0] fpu_madd_fProd_S3$D_IN, fpu_madd_fProd_S3$D_OUT; - wire fpu_madd_fProd_S3$CLR, - fpu_madd_fProd_S3$DEQ, - fpu_madd_fProd_S3$EMPTY_N, - fpu_madd_fProd_S3$ENQ, - fpu_madd_fProd_S3$FULL_N; - - // ports of submodule fpu_madd_fResult_S9 - wire [68 : 0] fpu_madd_fResult_S9$D_IN, fpu_madd_fResult_S9$D_OUT; - wire fpu_madd_fResult_S9$CLR, - fpu_madd_fResult_S9$DEQ, - fpu_madd_fResult_S9$EMPTY_N, - fpu_madd_fResult_S9$ENQ, - fpu_madd_fResult_S9$FULL_N; - - // ports of submodule fpu_madd_fState_S1 - wire [257 : 0] fpu_madd_fState_S1$D_IN, fpu_madd_fState_S1$D_OUT; - wire fpu_madd_fState_S1$CLR, - fpu_madd_fState_S1$DEQ, - fpu_madd_fState_S1$EMPTY_N, - fpu_madd_fState_S1$ENQ, - fpu_madd_fState_S1$FULL_N; - - // ports of submodule fpu_madd_fState_S2 - wire [151 : 0] fpu_madd_fState_S2$D_IN, fpu_madd_fState_S2$D_OUT; - wire fpu_madd_fState_S2$CLR, - fpu_madd_fState_S2$DEQ, - fpu_madd_fState_S2$EMPTY_N, - fpu_madd_fState_S2$ENQ, - fpu_madd_fState_S2$FULL_N; - - // ports of submodule fpu_madd_fState_S3 - wire [151 : 0] fpu_madd_fState_S3$D_IN, fpu_madd_fState_S3$D_OUT; - wire fpu_madd_fState_S3$CLR, - fpu_madd_fState_S3$DEQ, - fpu_madd_fState_S3$EMPTY_N, - fpu_madd_fState_S3$ENQ, - fpu_madd_fState_S3$FULL_N; - - // ports of submodule fpu_madd_fState_S4 - wire [203 : 0] fpu_madd_fState_S4$D_IN, fpu_madd_fState_S4$D_OUT; - wire fpu_madd_fState_S4$CLR, - fpu_madd_fState_S4$DEQ, - fpu_madd_fState_S4$EMPTY_N, - fpu_madd_fState_S4$ENQ, - fpu_madd_fState_S4$FULL_N; - - // ports of submodule fpu_madd_fState_S5 - wire [215 : 0] fpu_madd_fState_S5$D_IN, fpu_madd_fState_S5$D_OUT; - wire fpu_madd_fState_S5$CLR, - fpu_madd_fState_S5$DEQ, - fpu_madd_fState_S5$EMPTY_N, - fpu_madd_fState_S5$ENQ, - fpu_madd_fState_S5$FULL_N; - - // ports of submodule fpu_madd_fState_S6 - wire [202 : 0] fpu_madd_fState_S6$D_IN, fpu_madd_fState_S6$D_OUT; - wire fpu_madd_fState_S6$CLR, - fpu_madd_fState_S6$DEQ, - fpu_madd_fState_S6$EMPTY_N, - fpu_madd_fState_S6$ENQ, - fpu_madd_fState_S6$FULL_N; - - // ports of submodule fpu_madd_fState_S7 - wire [202 : 0] fpu_madd_fState_S7$D_IN, fpu_madd_fState_S7$D_OUT; - wire fpu_madd_fState_S7$CLR, - fpu_madd_fState_S7$DEQ, - fpu_madd_fState_S7$EMPTY_N, - fpu_madd_fState_S7$ENQ, - fpu_madd_fState_S7$FULL_N; - - // ports of submodule fpu_madd_fState_S8 - wire [140 : 0] fpu_madd_fState_S8$D_IN, fpu_madd_fState_S8$D_OUT; - wire fpu_madd_fState_S8$CLR, - fpu_madd_fState_S8$DEQ, - fpu_madd_fState_S8$EMPTY_N, - fpu_madd_fState_S8$ENQ, - fpu_madd_fState_S8$FULL_N; - - // ports of submodule fpu_sqr64_fOperand_S0 - wire [66 : 0] fpu_sqr64_fOperand_S0$D_IN, fpu_sqr64_fOperand_S0$D_OUT; - wire fpu_sqr64_fOperand_S0$CLR, - fpu_sqr64_fOperand_S0$DEQ, - fpu_sqr64_fOperand_S0$EMPTY_N, - fpu_sqr64_fOperand_S0$ENQ, - fpu_sqr64_fOperand_S0$FULL_N; - - // ports of submodule fpu_sqr64_fResult_S5 - wire [68 : 0] fpu_sqr64_fResult_S5$D_IN, fpu_sqr64_fResult_S5$D_OUT; - wire fpu_sqr64_fResult_S5$CLR, - fpu_sqr64_fResult_S5$DEQ, - fpu_sqr64_fResult_S5$EMPTY_N, - fpu_sqr64_fResult_S5$ENQ, - fpu_sqr64_fResult_S5$FULL_N; - - // ports of submodule fpu_sqr64_fState_S1 - wire [194 : 0] fpu_sqr64_fState_S1$D_IN, fpu_sqr64_fState_S1$D_OUT; - wire fpu_sqr64_fState_S1$CLR, - fpu_sqr64_fState_S1$DEQ, - fpu_sqr64_fState_S1$EMPTY_N, - fpu_sqr64_fState_S1$ENQ, - fpu_sqr64_fState_S1$FULL_N; - - // ports of submodule fpu_sqr64_fState_S2 - wire [136 : 0] fpu_sqr64_fState_S2$D_IN, fpu_sqr64_fState_S2$D_OUT; - wire fpu_sqr64_fState_S2$CLR, - fpu_sqr64_fState_S2$DEQ, - fpu_sqr64_fState_S2$EMPTY_N, - fpu_sqr64_fState_S2$ENQ, - fpu_sqr64_fState_S2$FULL_N; - - // ports of submodule fpu_sqr64_fState_S3 - wire [195 : 0] fpu_sqr64_fState_S3$D_IN, fpu_sqr64_fState_S3$D_OUT; - wire fpu_sqr64_fState_S3$CLR, - fpu_sqr64_fState_S3$DEQ, - fpu_sqr64_fState_S3$EMPTY_N, - fpu_sqr64_fState_S3$ENQ, - fpu_sqr64_fState_S3$FULL_N; - - // ports of submodule fpu_sqr64_fState_S4 - wire [138 : 0] fpu_sqr64_fState_S4$D_IN, fpu_sqr64_fState_S4$D_OUT; - wire fpu_sqr64_fState_S4$CLR, - fpu_sqr64_fState_S4$DEQ, - fpu_sqr64_fState_S4$EMPTY_N, - fpu_sqr64_fState_S4$ENQ, - fpu_sqr64_fState_S4$FULL_N; - - // ports of submodule iFifo - wire [201 : 0] iFifo$D_IN, iFifo$D_OUT; - wire iFifo$CLR, iFifo$DEQ, iFifo$EMPTY_N, iFifo$ENQ, iFifo$FULL_N; - - // ports of submodule isDoubleFifo - wire isDoubleFifo$CLR, - isDoubleFifo$DEQ, - isDoubleFifo$D_IN, - isDoubleFifo$D_OUT, - isDoubleFifo$EMPTY_N, - isDoubleFifo$ENQ, - isDoubleFifo$FULL_N; - - // ports of submodule isNegateFifo - wire isNegateFifo$CLR, - isNegateFifo$DEQ, - isNegateFifo$D_IN, - isNegateFifo$D_OUT, - isNegateFifo$EMPTY_N, - isNegateFifo$ENQ, - isNegateFifo$FULL_N; - - // ports of submodule oFifo - wire [69 : 0] oFifo$D_IN, oFifo$D_OUT; - wire oFifo$CLR, oFifo$DEQ, oFifo$EMPTY_N, oFifo$ENQ, oFifo$FULL_N; - - // ports of submodule resetReqsF - wire resetReqsF$CLR, - resetReqsF$DEQ, - resetReqsF$EMPTY_N, - resetReqsF$ENQ, - resetReqsF$FULL_N; - - // ports of submodule resetRspsF - wire resetRspsF$CLR, - resetRspsF$DEQ, - resetRspsF$EMPTY_N, - resetRspsF$ENQ, - resetRspsF$FULL_N; - - // ports of submodule rmdFifo - wire [2 : 0] rmdFifo$D_IN, rmdFifo$D_OUT; - wire rmdFifo$CLR, rmdFifo$DEQ, rmdFifo$EMPTY_N, rmdFifo$ENQ, rmdFifo$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_fpu_div64_s1_stage, - CAN_FIRE_RL_fpu_div64_s2_stage, - CAN_FIRE_RL_fpu_div64_s3_stage, - CAN_FIRE_RL_fpu_div64_s4_stage, - CAN_FIRE_RL_fpu_div64_s5_stage, - CAN_FIRE_RL_fpu_madd_s1_stage, - CAN_FIRE_RL_fpu_madd_s2_stage, - CAN_FIRE_RL_fpu_madd_s3_stage, - CAN_FIRE_RL_fpu_madd_s4_stage, - CAN_FIRE_RL_fpu_madd_s5_stage, - CAN_FIRE_RL_fpu_madd_s6_stage, - CAN_FIRE_RL_fpu_madd_s7_stage, - CAN_FIRE_RL_fpu_madd_s8_stage, - CAN_FIRE_RL_fpu_madd_s9_stage, - CAN_FIRE_RL_fpu_sqr64_s1_stage, - CAN_FIRE_RL_fpu_sqr64_s2_stage, - CAN_FIRE_RL_fpu_sqr64_s3_stage, - CAN_FIRE_RL_fpu_sqr64_s4_stage, - CAN_FIRE_RL_fpu_sqr64_s5_stage, - CAN_FIRE_RL_getResDiv, - CAN_FIRE_RL_getResMAdd, - CAN_FIRE_RL_getResSqr, - CAN_FIRE_RL_passResult, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_start_op, - CAN_FIRE_RL_work, - CAN_FIRE_RL_work_1, - CAN_FIRE___me_check_22, - CAN_FIRE___me_check_23, - CAN_FIRE_server_core_request_put, - CAN_FIRE_server_core_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - WILL_FIRE_RL_fpu_div64_s1_stage, - WILL_FIRE_RL_fpu_div64_s2_stage, - WILL_FIRE_RL_fpu_div64_s3_stage, - WILL_FIRE_RL_fpu_div64_s4_stage, - WILL_FIRE_RL_fpu_div64_s5_stage, - WILL_FIRE_RL_fpu_madd_s1_stage, - WILL_FIRE_RL_fpu_madd_s2_stage, - WILL_FIRE_RL_fpu_madd_s3_stage, - WILL_FIRE_RL_fpu_madd_s4_stage, - WILL_FIRE_RL_fpu_madd_s5_stage, - WILL_FIRE_RL_fpu_madd_s6_stage, - WILL_FIRE_RL_fpu_madd_s7_stage, - WILL_FIRE_RL_fpu_madd_s8_stage, - WILL_FIRE_RL_fpu_madd_s9_stage, - WILL_FIRE_RL_fpu_sqr64_s1_stage, - WILL_FIRE_RL_fpu_sqr64_s2_stage, - WILL_FIRE_RL_fpu_sqr64_s3_stage, - WILL_FIRE_RL_fpu_sqr64_s4_stage, - WILL_FIRE_RL_fpu_sqr64_s5_stage, - WILL_FIRE_RL_getResDiv, - WILL_FIRE_RL_getResMAdd, - WILL_FIRE_RL_getResSqr, - WILL_FIRE_RL_passResult, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_start_op, - WILL_FIRE_RL_work, - WILL_FIRE_RL_work_1, - WILL_FIRE___me_check_22, - WILL_FIRE___me_check_23, - WILL_FIRE_server_core_request_put, - WILL_FIRE_server_core_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get; - - // inputs to muxes for submodule ports - wire [116 : 0] MUX_rg_res$write_1__VAL_2; - wire [115 : 0] MUX_rg_b$write_1__VAL_1, - MUX_rg_b$write_1__VAL_2, - MUX_rg_r$write_1__VAL_1, - MUX_rg_r$write_1__VAL_2, - MUX_rg_r_1$write_1__VAL_2, - MUX_rg_s$write_1__VAL_1, - MUX_rg_s$write_1__VAL_2; - wire [57 : 0] MUX_rg_d$write_1__VAL_1, MUX_rg_q$write_1__VAL_2; - wire [5 : 0] MUX_rg_index$write_1__VAL_2, MUX_rg_index_1$write_1__VAL_2; - wire MUX_crg_done$port1__write_1__SEL_1, - MUX_crg_done$port1__write_1__SEL_2, - MUX_crg_done_1$port1__write_1__SEL_1, - MUX_crg_done_1$port1__write_1__SEL_2; - - // remaining internal signals - reg [63 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183, - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177, - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623; - reg [62 : 0] CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131, - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179; - reg [51 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4, - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110, - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111, - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112, - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113, - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75, - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76, - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77, - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78, - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79, - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80, - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48, - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49, - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50, - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51, - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52, - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53, - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108, - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109, - _theResult___fst_sfd__h142620, - _theResult___fst_sfd__h148292, - _theResult___fst_sfd__h164060, - _theResult___fst_sfd__h173650, - _theResult___fst_sfd__h182402, - _theResult___fst_sfd__h186932, - _theResult___fst_sfd__h19468, - _theResult___fst_sfd__h19957, - _theResult___fst_sfd__h202698, - _theResult___fst_sfd__h212288, - _theResult___fst_sfd__h221040, - _theResult___fst_sfd__h225871, - _theResult___fst_sfd__h241637, - _theResult___fst_sfd__h251227, - _theResult___fst_sfd__h259979, - _theResult___fst_sfd__h43554, - _theResult___fst_sfd__h95988; - reg [22 : 0] CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162, - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163, - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160, - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161, - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164, - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165, - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166, - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167, - _theResult___fst_sfd__h269560, - _theResult___fst_sfd__h278281, - _theResult___fst_sfd__h286863, - _theResult___fst_sfd__h296047, - _theResult___fst_sfd__h304683; - reg [10 : 0] CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22, - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104, - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105, - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106, - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107, - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69, - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70, - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71, - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72, - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73, - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74, - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42, - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43, - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44, - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45, - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46, - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47, - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102, - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103, - _theResult___fst_exp__h142619, - _theResult___fst_exp__h148291, - _theResult___fst_exp__h164059, - _theResult___fst_exp__h173649, - _theResult___fst_exp__h182401, - _theResult___fst_exp__h186931, - _theResult___fst_exp__h19467, - _theResult___fst_exp__h202697, - _theResult___fst_exp__h212287, - _theResult___fst_exp__h221039, - _theResult___fst_exp__h225870, - _theResult___fst_exp__h241636, - _theResult___fst_exp__h251226, - _theResult___fst_exp__h259978, - _theResult___fst_exp__h43553, - _theResult___fst_exp__h95987; - reg [7 : 0] CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154, - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155, - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152, - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153, - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156, - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157, - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158, - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159, - _theResult___fst_exp__h269559, - _theResult___fst_exp__h278280, - _theResult___fst_exp__h286862, - _theResult___fst_exp__h296046, - _theResult___fst_exp__h304682; - reg CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9, - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168, - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126, - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178, - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122, - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116, - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124, - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118, - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87, - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81, - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89, - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83, - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91, - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85, - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54, - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56, - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145, - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144, - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58, - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147, - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146, - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149, - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148, - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120, - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114, - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151, - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115, - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803, - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348, - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028, - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397, - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418; - wire [194 : 0] IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212; - wire [139 : 0] IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595; - wire [118 : 0] IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959; - wire [115 : 0] IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83, - IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22, - IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72, - _theResult___fst__h1476, - _theResult___fst__h1515, - _theResult___fst__h1600, - _theResult___snd_fst__h1478, - _theResult___snd_fst__h1517, - _theResult___snd_fst__h1602, - _theResult___snd_snd__h1649, - _theResult___snd_snd__h1715, - _theResult___snd_snd_snd__h1481, - _theResult___snd_snd_snd__h1520, - _theResult___snd_snd_snd__h1605, - b___1__h77160, - b__h1608, - b__h1712, - b__h32583, - r__h1659, - r__h1663, - r__h1724, - r__h1753, - s__h1658, - s__h1723, - sum__h1606, - sum__h1710, - value__h32541, - x__h85931; - wire [113 : 0] x__h31426; - wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24, - _theResult___fst__h116827, - _theResult___snd__h130966, - _theResult___snd__h130980, - _theResult___snd__h130982, - _theResult___snd__h130994, - _theResult___snd__h131000, - _theResult___snd__h131018, - _theResult___snd__h131023, - fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012, - sfdBC__h115662, - sfdin__h130943, - x__h116896; - wire [68 : 0] IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081; - wire [63 : 0] IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612, - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330, - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555, - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618, - IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657, - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452, - fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936; - wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980, - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065, - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552; - wire [58 : 0] IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19, - _theResult___snd__h94767, - _theResult___snd__h94782, - _theResult___snd__h94784, - _theResult___snd__h94797, - _theResult___snd__h94803, - _theResult___snd__h94821, - _theResult___snd__h94826, - result__h85925, - sfdin__h94744, - x__h86149; - wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12, - IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14, - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10, - _theResult____h32523, - _theResult___snd__h34715, - _theResult___snd__h42350, - _theResult___snd__h42365, - _theResult___snd__h42367, - _theResult___snd__h42380, - _theResult___snd__h42386, - _theResult___snd__h42404, - _theResult___snd__h42409, - _theResult___snd_snd_snd__h33963, - result__h32617, - result__h32648, - result__h32823, - rg_q_PLUS_NEG_INV_rg_q_59_60___d561, - sfd___1__h60702, - sfd__h44951, - sfd__h44953, - sfdin__h34118, - sfdin__h42327, - x__h32762, - x__h33052, - x__h60693; - wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64, - IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97, - IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139, - IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29, - IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100, - IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93, - IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33, - IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40, - IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60, - IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67, - IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135, - IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330, - _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038, - _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038, - _theResult____h164614, - _theResult____h203252, - _theResult____h242191, - _theResult____h269577, - _theResult____h287214, - _theResult___snd__h141392, - _theResult___snd__h141406, - _theResult___snd__h141408, - _theResult___snd__h141420, - _theResult___snd__h141426, - _theResult___snd__h141444, - _theResult___snd__h141449, - _theResult___snd__h163287, - _theResult___snd__h163289, - _theResult___snd__h163296, - _theResult___snd__h163302, - _theResult___snd__h163325, - _theResult___snd__h172863, - _theResult___snd__h172874, - _theResult___snd__h172876, - _theResult___snd__h172886, - _theResult___snd__h172892, - _theResult___snd__h172915, - _theResult___snd__h181599, - _theResult___snd__h181613, - _theResult___snd__h181619, - _theResult___snd__h181637, - _theResult___snd__h201925, - _theResult___snd__h201927, - _theResult___snd__h201934, - _theResult___snd__h201940, - _theResult___snd__h201963, - _theResult___snd__h211501, - _theResult___snd__h211512, - _theResult___snd__h211514, - _theResult___snd__h211524, - _theResult___snd__h211530, - _theResult___snd__h211553, - _theResult___snd__h220237, - _theResult___snd__h220251, - _theResult___snd__h220257, - _theResult___snd__h220275, - _theResult___snd__h240864, - _theResult___snd__h240866, - _theResult___snd__h240873, - _theResult___snd__h240879, - _theResult___snd__h240902, - _theResult___snd__h250440, - _theResult___snd__h250451, - _theResult___snd__h250453, - _theResult___snd__h250463, - _theResult___snd__h250469, - _theResult___snd__h250492, - _theResult___snd__h259176, - _theResult___snd__h259190, - _theResult___snd__h259196, - _theResult___snd__h259214, - _theResult___snd__h277697, - _theResult___snd__h277708, - _theResult___snd__h277710, - _theResult___snd__h277720, - _theResult___snd__h277726, - _theResult___snd__h277749, - _theResult___snd__h286293, - _theResult___snd__h286295, - _theResult___snd__h286302, - _theResult___snd__h286308, - _theResult___snd__h286331, - _theResult___snd__h295463, - _theResult___snd__h295474, - _theResult___snd__h295476, - _theResult___snd__h295486, - _theResult___snd__h295492, - _theResult___snd__h295515, - _theResult___snd__h304083, - _theResult___snd__h304097, - _theResult___snd__h304103, - _theResult___snd__h304121, - fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615, - guard__h132367, - result__h132372, - result__h165227, - result__h203865, - result__h242804, - result__h287827, - sfdA__h131577, - sfdBC__h131578, - sfd__h133119, - sfd__h144536, - sfd__h183176, - sfd__h222115, - sfd__h261975, - sfdin__h141369, - sfdin__h172846, - sfdin__h211484, - sfdin__h250423, - sfdin__h277680, - sfdin__h295446, - value__h32661, - x__h131940, - x__h131944, - x__h132359, - x__h132871, - x__h132880, - x__h165324, - x__h203962, - x__h242901, - x__h287924, - x__h31487; - wire [53 : 0] sfd__h142040, - sfd__h163354, - sfd__h172944, - sfd__h181672, - sfd__h201992, - sfd__h211582, - sfd__h220310, - sfd__h240931, - sfd__h250521, - sfd__h259249, - sfd__h42982, - sfd__h95416, - value__h270197, - value__h31429, - value__h53174; - wire [52 : 0] sfdA__h2035, - sfdA__h2039, - sfdB__h2036, - sfdB__h2041, - x__h114243, - x__h114255; - wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450, - _theResult___fst_sfd__h164063, - _theResult___fst_sfd__h173653, - _theResult___fst_sfd__h182405, - _theResult___fst_sfd__h182414, - _theResult___fst_sfd__h182420, - _theResult___fst_sfd__h202701, - _theResult___fst_sfd__h212291, - _theResult___fst_sfd__h221043, - _theResult___fst_sfd__h221052, - _theResult___fst_sfd__h221058, - _theResult___fst_sfd__h241640, - _theResult___fst_sfd__h251230, - _theResult___fst_sfd__h259982, - _theResult___fst_sfd__h259991, - _theResult___fst_sfd__h259997, - _theResult___fst_sfd__h43557, - _theResult___fst_sfd__h95991, - _theResult___fst_sfd__h96608, - _theResult___sfd__h142542, - _theResult___sfd__h163982, - _theResult___sfd__h173572, - _theResult___sfd__h182324, - _theResult___sfd__h202620, - _theResult___sfd__h212210, - _theResult___sfd__h220962, - _theResult___sfd__h241559, - _theResult___sfd__h251149, - _theResult___sfd__h259901, - _theResult___sfd__h43476, - _theResult___sfd__h95910, - _theResult___snd_fst_sfd__h144486, - _theResult___snd_fst_sfd__h164066, - _theResult___snd_fst_sfd__h182408, - _theResult___snd_fst_sfd__h183126, - _theResult___snd_fst_sfd__h202704, - _theResult___snd_fst_sfd__h221046, - _theResult___snd_fst_sfd__h222065, - _theResult___snd_fst_sfd__h241643, - _theResult___snd_fst_sfd__h259985, - _theResult___snd_fst_sfd__h31362, - out___1_sfd__h144235, - out___1_sfd__h182875, - out___1_sfd__h221814, - out_sfd__h142545, - out_sfd__h163985, - out_sfd__h173575, - out_sfd__h182327, - out_sfd__h202623, - out_sfd__h212213, - out_sfd__h220965, - out_sfd__h241562, - out_sfd__h251152, - out_sfd__h259904, - out_sfd__h43479, - out_sfd__h95913, - sfd__h18934, - sfd__h18937, - sfd__h45004, - sfd__h99402, - sfd__h99405, - sfd__h99408; - wire [24 : 0] sfd__h277778, - sfd__h286360, - sfd__h295544, - sfd__h304156, - value__h148923, - value__h187561, - value__h226500; - wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576, - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643, - _theResult___fst_sfd__h278284, - _theResult___fst_sfd__h286866, - _theResult___fst_sfd__h296050, - _theResult___fst_sfd__h304686, - _theResult___fst_sfd__h304695, - _theResult___fst_sfd__h304701, - _theResult___sfd__h278203, - _theResult___sfd__h286785, - _theResult___sfd__h295969, - _theResult___sfd__h304605, - _theResult___snd_fst_sfd__h261925, - _theResult___snd_fst_sfd__h286869, - _theResult___snd_fst_sfd__h304689, - out_sfd__h278206, - out_sfd__h286788, - out_sfd__h295972, - out_sfd__h304608, - sfd__h304707; - wire [12 : 0] IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352, - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568, - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195, - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007, - value__h130883, - value__h141307, - value__h31374, - value__h31550, - x__h116929, - x__h132471, - x__h52551, - x__h52569; - wire [11 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106, - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331, - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668, - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17, - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389, - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531, - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809, - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326, - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683, - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034, - x__h165357, - x__h203995, - x__h242934, - x__h287957; - wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211, - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242, - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760, - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467, - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433, - IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011, - IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66, - _theResult___exp__h142541, - _theResult___exp__h163981, - _theResult___exp__h173571, - _theResult___exp__h182323, - _theResult___exp__h202619, - _theResult___exp__h212209, - _theResult___exp__h220961, - _theResult___exp__h241558, - _theResult___exp__h251148, - _theResult___exp__h259900, - _theResult___exp__h43475, - _theResult___exp__h95909, - _theResult___fst__h31322, - _theResult___fst_exp__h130949, - _theResult___fst_exp__h130952, - _theResult___fst_exp__h130971, - _theResult___fst_exp__h130986, - _theResult___fst_exp__h131025, - _theResult___fst_exp__h131031, - _theResult___fst_exp__h131034, - _theResult___fst_exp__h141375, - _theResult___fst_exp__h141378, - _theResult___fst_exp__h141397, - _theResult___fst_exp__h141412, - _theResult___fst_exp__h141451, - _theResult___fst_exp__h141457, - _theResult___fst_exp__h141460, - _theResult___fst_exp__h163327, - _theResult___fst_exp__h163333, - _theResult___fst_exp__h163336, - _theResult___fst_exp__h164062, - _theResult___fst_exp__h172852, - _theResult___fst_exp__h172917, - _theResult___fst_exp__h172923, - _theResult___fst_exp__h172926, - _theResult___fst_exp__h173652, - _theResult___fst_exp__h181605, - _theResult___fst_exp__h181644, - _theResult___fst_exp__h181650, - _theResult___fst_exp__h181653, - _theResult___fst_exp__h182404, - _theResult___fst_exp__h182413, - _theResult___fst_exp__h182416, - _theResult___fst_exp__h201965, - _theResult___fst_exp__h201971, - _theResult___fst_exp__h201974, - _theResult___fst_exp__h202700, - _theResult___fst_exp__h211490, - _theResult___fst_exp__h211555, - _theResult___fst_exp__h211561, - _theResult___fst_exp__h211564, - _theResult___fst_exp__h212290, - _theResult___fst_exp__h220243, - _theResult___fst_exp__h220282, - _theResult___fst_exp__h220288, - _theResult___fst_exp__h220291, - _theResult___fst_exp__h221042, - _theResult___fst_exp__h221051, - _theResult___fst_exp__h221054, - _theResult___fst_exp__h240904, - _theResult___fst_exp__h240910, - _theResult___fst_exp__h240913, - _theResult___fst_exp__h241639, - _theResult___fst_exp__h250429, - _theResult___fst_exp__h250494, - _theResult___fst_exp__h250500, - _theResult___fst_exp__h250503, - _theResult___fst_exp__h251229, - _theResult___fst_exp__h259182, - _theResult___fst_exp__h259221, - _theResult___fst_exp__h259227, - _theResult___fst_exp__h259230, - _theResult___fst_exp__h259981, - _theResult___fst_exp__h259990, - _theResult___fst_exp__h259993, - _theResult___fst_exp__h42284, - _theResult___fst_exp__h42287, - _theResult___fst_exp__h42290, - _theResult___fst_exp__h42333, - _theResult___fst_exp__h42336, - _theResult___fst_exp__h42356, - _theResult___fst_exp__h42372, - _theResult___fst_exp__h42411, - _theResult___fst_exp__h42417, - _theResult___fst_exp__h42420, - _theResult___fst_exp__h43556, - _theResult___fst_exp__h94750, - _theResult___fst_exp__h94753, - _theResult___fst_exp__h94773, - _theResult___fst_exp__h94789, - _theResult___fst_exp__h94828, - _theResult___fst_exp__h94834, - _theResult___fst_exp__h94837, - _theResult___fst_exp__h95990, - _theResult___snd_fst_exp__h164065, - _theResult___snd_fst_exp__h182407, - _theResult___snd_fst_exp__h202703, - _theResult___snd_fst_exp__h221045, - _theResult___snd_fst_exp__h241642, - _theResult___snd_fst_exp__h259984, - _theResult___snd_fst_exp__h31334, - _theResult___snd_fst_exp__h31337, - _theResult___snd_fst_exp__h31361, - din_exp30866_MINUS_1023__q23, - din_exp__h130866, - din_inc___2_exp__h142626, - din_inc___2_exp__h182469, - din_inc___2_exp__h182504, - din_inc___2_exp__h182530, - din_inc___2_exp__h221107, - din_inc___2_exp__h221142, - din_inc___2_exp__h221168, - din_inc___2_exp__h260046, - din_inc___2_exp__h260081, - din_inc___2_exp__h260107, - din_inc___2_exp__h43566, - din_inc___2_exp__h96000, - fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7, - fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8, - fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128, - fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129, - fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27, - fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26, - fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16, - fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18, - out_exp__h142544, - out_exp__h163984, - out_exp__h173574, - out_exp__h182326, - out_exp__h202622, - out_exp__h212212, - out_exp__h220964, - out_exp__h241561, - out_exp__h251151, - out_exp__h259903, - out_exp__h43478, - out_exp__h95912, - resWirewget_BITS_67_TO_57_MINUS_1023__q137, - theResult___fst_exp2290_MINUS_1023__q11, - value41307_BITS_10_TO_0_MINUS_1023__q28, - x__h31541, - x__h32769, - x__h96539; - wire [8 : 0] IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332; - wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448, - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518, - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549, - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141, - _theResult___exp__h278202, - _theResult___exp__h286784, - _theResult___exp__h295968, - _theResult___exp__h304604, - _theResult___fst_exp__h277686, - _theResult___fst_exp__h277751, - _theResult___fst_exp__h277757, - _theResult___fst_exp__h277760, - _theResult___fst_exp__h278283, - _theResult___fst_exp__h286333, - _theResult___fst_exp__h286339, - _theResult___fst_exp__h286342, - _theResult___fst_exp__h286865, - _theResult___fst_exp__h295452, - _theResult___fst_exp__h295517, - _theResult___fst_exp__h295523, - _theResult___fst_exp__h295526, - _theResult___fst_exp__h296049, - _theResult___fst_exp__h304089, - _theResult___fst_exp__h304128, - _theResult___fst_exp__h304134, - _theResult___fst_exp__h304137, - _theResult___fst_exp__h304685, - _theResult___fst_exp__h304694, - _theResult___fst_exp__h304697, - _theResult___snd_fst_exp__h286868, - _theResult___snd_fst_exp__h304688, - din_inc___2_exp__h304723, - din_inc___2_exp__h304749, - din_inc___2_exp__h304784, - din_inc___2_exp__h304810, - exp__h304706, - iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95, - iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35, - iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62, - out_exp__h278205, - out_exp__h286787, - out_exp__h295971, - out_exp__h304607; - wire [6 : 0] IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460, - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342, - x__h85465; - wire [5 : 0] IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982, - b__h11457, - b__h4039, - x__h60732; - wire [4 : 0] IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926, - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921, - IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688, - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501, - fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942, - fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043, - resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768; - wire [2 : 0] IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523; - wire [1 : 0] IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98, - IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13, - IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25, - IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30, - IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20, - IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65, - IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38, - IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134, - IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140, - IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94, - IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143, - IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101, - IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61, - IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68, - IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34, - IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41, - IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136, - _theResult___snd_fst__h131051, - _theResult___snd_fst__h141477, - _theResult___snd_fst__h42439, - _theResult___snd_fst__h94856, - _theResult___snd_snd__h131371, - _theResult___snd_snd_snd__h131369, - guardBC__h115666, - guard__h133123, - guard__h155375, - guard__h164624, - guard__h173663, - guard__h194013, - guard__h203262, - guard__h212301, - guard__h232952, - guard__h242201, - guard__h251240, - guard__h269587, - guard__h278294, - guard__h287224, - guard__h296060, - guard__h33946, - guard__h86435, - x__h131406, - x__h141760, - x__h42705, - x__h95138; - wire IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025, - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802, - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146, - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374, - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371, - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747, - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355, - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422, - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516, - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521, - IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610, - IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85, - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56, - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44, - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728, - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756, - NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946, - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400, - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481, - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488, - NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923, - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584, - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244, - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955, - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730, - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807, - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324, - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032, - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032, - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033, - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282, - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057, - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280, - _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463, - _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883, - _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904, - _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633, - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759, - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107, - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273, - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624, - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984, - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984, - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716, - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684, - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685, - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498, - fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359, - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405, - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857, - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926, - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004, - guard__h165222, - guard__h203860, - guard__h242799, - guard__h287822, - rg_index_1_4_PLUS_1_6_ULE_58___d37, - rg_index_1_4_ULE_58___d38, - rg_index_PLUS_1_ULE_57___d6, - rg_index_ULE_57___d7, - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63, - sfdlsb__h116825, - sfdlsb__h32643, - value_BIT_52___h53270; - - // action method server_core_request_put - assign RDY_server_core_request_put = iFifo$FULL_N ; - assign CAN_FIRE_server_core_request_put = iFifo$FULL_N ; - assign WILL_FIRE_server_core_request_put = EN_server_core_request_put ; - - // actionvalue method server_core_response_get - assign server_core_response_get = oFifo$D_OUT ; - assign RDY_server_core_response_get = oFifo$EMPTY_N ; - assign CAN_FIRE_server_core_response_get = oFifo$EMPTY_N ; - assign WILL_FIRE_server_core_response_get = EN_server_core_response_get ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = resetReqsF$FULL_N ; - assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // submodule fpu_div64_fOperands_S0 - FIFOL1 #(.width(32'd131)) fpu_div64_fOperands_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fOperands_S0$D_IN), - .ENQ(fpu_div64_fOperands_S0$ENQ), - .DEQ(fpu_div64_fOperands_S0$DEQ), - .CLR(fpu_div64_fOperands_S0$CLR), - .D_OUT(fpu_div64_fOperands_S0$D_OUT), - .FULL_N(fpu_div64_fOperands_S0$FULL_N), - .EMPTY_N(fpu_div64_fOperands_S0$EMPTY_N)); - - // submodule fpu_div64_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_div64_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fResult_S5$D_IN), - .ENQ(fpu_div64_fResult_S5$ENQ), - .DEQ(fpu_div64_fResult_S5$DEQ), - .CLR(fpu_div64_fResult_S5$CLR), - .D_OUT(fpu_div64_fResult_S5$D_OUT), - .FULL_N(fpu_div64_fResult_S5$FULL_N), - .EMPTY_N(fpu_div64_fResult_S5$EMPTY_N)); - - // submodule fpu_div64_fState_S1 - FIFOL1 #(.width(32'd319)) fpu_div64_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S1$D_IN), - .ENQ(fpu_div64_fState_S1$ENQ), - .DEQ(fpu_div64_fState_S1$DEQ), - .CLR(fpu_div64_fState_S1$CLR), - .D_OUT(fpu_div64_fState_S1$D_OUT), - .FULL_N(fpu_div64_fState_S1$FULL_N), - .EMPTY_N(fpu_div64_fState_S1$EMPTY_N)); - - // submodule fpu_div64_fState_S2 - FIFOL1 #(.width(32'd148)) fpu_div64_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S2$D_IN), - .ENQ(fpu_div64_fState_S2$ENQ), - .DEQ(fpu_div64_fState_S2$DEQ), - .CLR(fpu_div64_fState_S2$CLR), - .D_OUT(fpu_div64_fState_S2$D_OUT), - .FULL_N(fpu_div64_fState_S2$FULL_N), - .EMPTY_N(fpu_div64_fState_S2$EMPTY_N)); - - // submodule fpu_div64_fState_S3 - FIFOL1 #(.width(32'd195)) fpu_div64_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S3$D_IN), - .ENQ(fpu_div64_fState_S3$ENQ), - .DEQ(fpu_div64_fState_S3$DEQ), - .CLR(fpu_div64_fState_S3$CLR), - .D_OUT(fpu_div64_fState_S3$D_OUT), - .FULL_N(fpu_div64_fState_S3$FULL_N), - .EMPTY_N(fpu_div64_fState_S3$EMPTY_N)); - - // submodule fpu_div64_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_div64_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_div64_fState_S4$D_IN), - .ENQ(fpu_div64_fState_S4$ENQ), - .DEQ(fpu_div64_fState_S4$DEQ), - .CLR(fpu_div64_fState_S4$CLR), - .D_OUT(fpu_div64_fState_S4$D_OUT), - .FULL_N(fpu_div64_fState_S4$FULL_N), - .EMPTY_N(fpu_div64_fState_S4$EMPTY_N)); - - // submodule fpu_madd_fOperand_S0 - FIFOL1 #(.width(32'd196)) fpu_madd_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fOperand_S0$D_IN), - .ENQ(fpu_madd_fOperand_S0$ENQ), - .DEQ(fpu_madd_fOperand_S0$DEQ), - .CLR(fpu_madd_fOperand_S0$CLR), - .D_OUT(fpu_madd_fOperand_S0$D_OUT), - .FULL_N(fpu_madd_fOperand_S0$FULL_N), - .EMPTY_N(fpu_madd_fOperand_S0$EMPTY_N)); - - // submodule fpu_madd_fProd_S2 - FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fProd_S2$D_IN), - .ENQ(fpu_madd_fProd_S2$ENQ), - .DEQ(fpu_madd_fProd_S2$DEQ), - .CLR(fpu_madd_fProd_S2$CLR), - .D_OUT(fpu_madd_fProd_S2$D_OUT), - .FULL_N(fpu_madd_fProd_S2$FULL_N), - .EMPTY_N(fpu_madd_fProd_S2$EMPTY_N)); - - // submodule fpu_madd_fProd_S3 - FIFOL1 #(.width(32'd106)) fpu_madd_fProd_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fProd_S3$D_IN), - .ENQ(fpu_madd_fProd_S3$ENQ), - .DEQ(fpu_madd_fProd_S3$DEQ), - .CLR(fpu_madd_fProd_S3$CLR), - .D_OUT(fpu_madd_fProd_S3$D_OUT), - .FULL_N(fpu_madd_fProd_S3$FULL_N), - .EMPTY_N(fpu_madd_fProd_S3$EMPTY_N)); - - // submodule fpu_madd_fResult_S9 - FIFOL1 #(.width(32'd69)) fpu_madd_fResult_S9(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fResult_S9$D_IN), - .ENQ(fpu_madd_fResult_S9$ENQ), - .DEQ(fpu_madd_fResult_S9$DEQ), - .CLR(fpu_madd_fResult_S9$CLR), - .D_OUT(fpu_madd_fResult_S9$D_OUT), - .FULL_N(fpu_madd_fResult_S9$FULL_N), - .EMPTY_N(fpu_madd_fResult_S9$EMPTY_N)); - - // submodule fpu_madd_fState_S1 - FIFOL1 #(.width(32'd258)) fpu_madd_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S1$D_IN), - .ENQ(fpu_madd_fState_S1$ENQ), - .DEQ(fpu_madd_fState_S1$DEQ), - .CLR(fpu_madd_fState_S1$CLR), - .D_OUT(fpu_madd_fState_S1$D_OUT), - .FULL_N(fpu_madd_fState_S1$FULL_N), - .EMPTY_N(fpu_madd_fState_S1$EMPTY_N)); - - // submodule fpu_madd_fState_S2 - FIFOL1 #(.width(32'd152)) fpu_madd_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S2$D_IN), - .ENQ(fpu_madd_fState_S2$ENQ), - .DEQ(fpu_madd_fState_S2$DEQ), - .CLR(fpu_madd_fState_S2$CLR), - .D_OUT(fpu_madd_fState_S2$D_OUT), - .FULL_N(fpu_madd_fState_S2$FULL_N), - .EMPTY_N(fpu_madd_fState_S2$EMPTY_N)); - - // submodule fpu_madd_fState_S3 - FIFOL1 #(.width(32'd152)) fpu_madd_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S3$D_IN), - .ENQ(fpu_madd_fState_S3$ENQ), - .DEQ(fpu_madd_fState_S3$DEQ), - .CLR(fpu_madd_fState_S3$CLR), - .D_OUT(fpu_madd_fState_S3$D_OUT), - .FULL_N(fpu_madd_fState_S3$FULL_N), - .EMPTY_N(fpu_madd_fState_S3$EMPTY_N)); - - // submodule fpu_madd_fState_S4 - FIFOL1 #(.width(32'd204)) fpu_madd_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S4$D_IN), - .ENQ(fpu_madd_fState_S4$ENQ), - .DEQ(fpu_madd_fState_S4$DEQ), - .CLR(fpu_madd_fState_S4$CLR), - .D_OUT(fpu_madd_fState_S4$D_OUT), - .FULL_N(fpu_madd_fState_S4$FULL_N), - .EMPTY_N(fpu_madd_fState_S4$EMPTY_N)); - - // submodule fpu_madd_fState_S5 - FIFOL1 #(.width(32'd216)) fpu_madd_fState_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S5$D_IN), - .ENQ(fpu_madd_fState_S5$ENQ), - .DEQ(fpu_madd_fState_S5$DEQ), - .CLR(fpu_madd_fState_S5$CLR), - .D_OUT(fpu_madd_fState_S5$D_OUT), - .FULL_N(fpu_madd_fState_S5$FULL_N), - .EMPTY_N(fpu_madd_fState_S5$EMPTY_N)); - - // submodule fpu_madd_fState_S6 - FIFOL1 #(.width(32'd203)) fpu_madd_fState_S6(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S6$D_IN), - .ENQ(fpu_madd_fState_S6$ENQ), - .DEQ(fpu_madd_fState_S6$DEQ), - .CLR(fpu_madd_fState_S6$CLR), - .D_OUT(fpu_madd_fState_S6$D_OUT), - .FULL_N(fpu_madd_fState_S6$FULL_N), - .EMPTY_N(fpu_madd_fState_S6$EMPTY_N)); - - // submodule fpu_madd_fState_S7 - FIFOL1 #(.width(32'd203)) fpu_madd_fState_S7(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S7$D_IN), - .ENQ(fpu_madd_fState_S7$ENQ), - .DEQ(fpu_madd_fState_S7$DEQ), - .CLR(fpu_madd_fState_S7$CLR), - .D_OUT(fpu_madd_fState_S7$D_OUT), - .FULL_N(fpu_madd_fState_S7$FULL_N), - .EMPTY_N(fpu_madd_fState_S7$EMPTY_N)); - - // submodule fpu_madd_fState_S8 - FIFOL1 #(.width(32'd141)) fpu_madd_fState_S8(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_madd_fState_S8$D_IN), - .ENQ(fpu_madd_fState_S8$ENQ), - .DEQ(fpu_madd_fState_S8$DEQ), - .CLR(fpu_madd_fState_S8$CLR), - .D_OUT(fpu_madd_fState_S8$D_OUT), - .FULL_N(fpu_madd_fState_S8$FULL_N), - .EMPTY_N(fpu_madd_fState_S8$EMPTY_N)); - - // submodule fpu_sqr64_fOperand_S0 - FIFOL1 #(.width(32'd67)) fpu_sqr64_fOperand_S0(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fOperand_S0$D_IN), - .ENQ(fpu_sqr64_fOperand_S0$ENQ), - .DEQ(fpu_sqr64_fOperand_S0$DEQ), - .CLR(fpu_sqr64_fOperand_S0$CLR), - .D_OUT(fpu_sqr64_fOperand_S0$D_OUT), - .FULL_N(fpu_sqr64_fOperand_S0$FULL_N), - .EMPTY_N(fpu_sqr64_fOperand_S0$EMPTY_N)); - - // submodule fpu_sqr64_fResult_S5 - FIFOL1 #(.width(32'd69)) fpu_sqr64_fResult_S5(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fResult_S5$D_IN), - .ENQ(fpu_sqr64_fResult_S5$ENQ), - .DEQ(fpu_sqr64_fResult_S5$DEQ), - .CLR(fpu_sqr64_fResult_S5$CLR), - .D_OUT(fpu_sqr64_fResult_S5$D_OUT), - .FULL_N(fpu_sqr64_fResult_S5$FULL_N), - .EMPTY_N(fpu_sqr64_fResult_S5$EMPTY_N)); - - // submodule fpu_sqr64_fState_S1 - FIFOL1 #(.width(32'd195)) fpu_sqr64_fState_S1(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S1$D_IN), - .ENQ(fpu_sqr64_fState_S1$ENQ), - .DEQ(fpu_sqr64_fState_S1$DEQ), - .CLR(fpu_sqr64_fState_S1$CLR), - .D_OUT(fpu_sqr64_fState_S1$D_OUT), - .FULL_N(fpu_sqr64_fState_S1$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S1$EMPTY_N)); - - // submodule fpu_sqr64_fState_S2 - FIFOL1 #(.width(32'd137)) fpu_sqr64_fState_S2(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S2$D_IN), - .ENQ(fpu_sqr64_fState_S2$ENQ), - .DEQ(fpu_sqr64_fState_S2$DEQ), - .CLR(fpu_sqr64_fState_S2$CLR), - .D_OUT(fpu_sqr64_fState_S2$D_OUT), - .FULL_N(fpu_sqr64_fState_S2$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S2$EMPTY_N)); - - // submodule fpu_sqr64_fState_S3 - FIFOL1 #(.width(32'd196)) fpu_sqr64_fState_S3(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S3$D_IN), - .ENQ(fpu_sqr64_fState_S3$ENQ), - .DEQ(fpu_sqr64_fState_S3$DEQ), - .CLR(fpu_sqr64_fState_S3$CLR), - .D_OUT(fpu_sqr64_fState_S3$D_OUT), - .FULL_N(fpu_sqr64_fState_S3$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S3$EMPTY_N)); - - // submodule fpu_sqr64_fState_S4 - FIFOL1 #(.width(32'd139)) fpu_sqr64_fState_S4(.RST(RST_N), - .CLK(CLK), - .D_IN(fpu_sqr64_fState_S4$D_IN), - .ENQ(fpu_sqr64_fState_S4$ENQ), - .DEQ(fpu_sqr64_fState_S4$DEQ), - .CLR(fpu_sqr64_fState_S4$CLR), - .D_OUT(fpu_sqr64_fState_S4$D_OUT), - .FULL_N(fpu_sqr64_fState_S4$FULL_N), - .EMPTY_N(fpu_sqr64_fState_S4$EMPTY_N)); - - // submodule iFifo - FIFO2 #(.width(32'd202), .guarded(32'd1)) iFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(iFifo$D_IN), - .ENQ(iFifo$ENQ), - .DEQ(iFifo$DEQ), - .CLR(iFifo$CLR), - .D_OUT(iFifo$D_OUT), - .FULL_N(iFifo$FULL_N), - .EMPTY_N(iFifo$EMPTY_N)); - - // submodule isDoubleFifo - FIFO2 #(.width(32'd1), .guarded(32'd1)) isDoubleFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(isDoubleFifo$D_IN), - .ENQ(isDoubleFifo$ENQ), - .DEQ(isDoubleFifo$DEQ), - .CLR(isDoubleFifo$CLR), - .D_OUT(isDoubleFifo$D_OUT), - .FULL_N(isDoubleFifo$FULL_N), - .EMPTY_N(isDoubleFifo$EMPTY_N)); - - // submodule isNegateFifo - FIFO2 #(.width(32'd1), .guarded(32'd1)) isNegateFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(isNegateFifo$D_IN), - .ENQ(isNegateFifo$ENQ), - .DEQ(isNegateFifo$DEQ), - .CLR(isNegateFifo$CLR), - .D_OUT(isNegateFifo$D_OUT), - .FULL_N(isNegateFifo$FULL_N), - .EMPTY_N(isNegateFifo$EMPTY_N)); - - // submodule oFifo - FIFO2 #(.width(32'd70), .guarded(32'd1)) oFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(oFifo$D_IN), - .ENQ(oFifo$ENQ), - .DEQ(oFifo$DEQ), - .CLR(oFifo$CLR), - .D_OUT(oFifo$D_OUT), - .FULL_N(oFifo$FULL_N), - .EMPTY_N(oFifo$EMPTY_N)); - - // submodule resetReqsF - FIFO20 #(.guarded(32'd1)) resetReqsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetReqsF$ENQ), - .DEQ(resetReqsF$DEQ), - .CLR(resetReqsF$CLR), - .FULL_N(resetReqsF$FULL_N), - .EMPTY_N(resetReqsF$EMPTY_N)); - - // submodule resetRspsF - FIFO20 #(.guarded(32'd1)) resetRspsF(.RST(RST_N), - .CLK(CLK), - .ENQ(resetRspsF$ENQ), - .DEQ(resetRspsF$DEQ), - .CLR(resetRspsF$CLR), - .FULL_N(resetRspsF$FULL_N), - .EMPTY_N(resetRspsF$EMPTY_N)); - - // submodule rmdFifo - FIFO2 #(.width(32'd3), .guarded(32'd1)) rmdFifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rmdFifo$D_IN), - .ENQ(rmdFifo$ENQ), - .DEQ(rmdFifo$DEQ), - .CLR(rmdFifo$CLR), - .D_OUT(rmdFifo$D_OUT), - .FULL_N(rmdFifo$FULL_N), - .EMPTY_N(rmdFifo$EMPTY_N)); - - // rule RL_getResDiv - assign CAN_FIRE_RL_getResDiv = fpu_div64_fResult_S5$EMPTY_N ; - assign WILL_FIRE_RL_getResDiv = fpu_div64_fResult_S5$EMPTY_N ; - - // rule RL_getResSqr - assign CAN_FIRE_RL_getResSqr = fpu_sqr64_fResult_S5$EMPTY_N ; - assign WILL_FIRE_RL_getResSqr = fpu_sqr64_fResult_S5$EMPTY_N ; - - // rule RL_getResMAdd - assign CAN_FIRE_RL_getResMAdd = fpu_madd_fResult_S9$EMPTY_N ; - assign WILL_FIRE_RL_getResMAdd = fpu_madd_fResult_S9$EMPTY_N ; - - // rule __me_check_22 - assign CAN_FIRE___me_check_22 = 1'b1 ; - assign WILL_FIRE___me_check_22 = 1'b1 ; - - // rule __me_check_23 - assign CAN_FIRE___me_check_23 = 1'b1 ; - assign WILL_FIRE___me_check_23 = 1'b1 ; - - // rule RL_passResult - assign CAN_FIRE_RL_passResult = - isDoubleFifo$EMPTY_N && isNegateFifo$EMPTY_N && - rmdFifo$EMPTY_N && - oFifo$FULL_N && - resWire$whas ; - assign WILL_FIRE_RL_passResult = CAN_FIRE_RL_passResult ; - - // rule RL_fpu_div64_s5_stage - assign CAN_FIRE_RL_fpu_div64_s5_stage = - fpu_div64_fState_S4$EMPTY_N && fpu_div64_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s5_stage = CAN_FIRE_RL_fpu_div64_s5_stage ; - - // rule RL_fpu_div64_s4_stage - assign CAN_FIRE_RL_fpu_div64_s4_stage = - fpu_div64_fState_S3$EMPTY_N && fpu_div64_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s4_stage = CAN_FIRE_RL_fpu_div64_s4_stage ; - - // rule RL_fpu_div64_s3_stage - assign CAN_FIRE_RL_fpu_div64_s3_stage = - fpu_div64_fState_S2$EMPTY_N && fpu_div64_fState_S3$FULL_N && - (fpu_div64_fState_S2$D_OUT[147] || crg_done) ; - assign WILL_FIRE_RL_fpu_div64_s3_stage = CAN_FIRE_RL_fpu_div64_s3_stage ; - - // rule RL_work - assign CAN_FIRE_RL_work = rg_busy ; - assign WILL_FIRE_RL_work = rg_busy ; - - // rule RL_fpu_div64_s2_stage - assign CAN_FIRE_RL_fpu_div64_s2_stage = - fpu_div64_fState_S1$EMPTY_N && fpu_div64_fState_S2$FULL_N && - (fpu_div64_fState_S1$D_OUT[318] || !rg_busy) ; - assign WILL_FIRE_RL_fpu_div64_s2_stage = - CAN_FIRE_RL_fpu_div64_s2_stage && !rg_busy ; - - // rule RL_fpu_div64_s1_stage - assign CAN_FIRE_RL_fpu_div64_s1_stage = - fpu_div64_fOperands_S0$EMPTY_N && fpu_div64_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_div64_s1_stage = CAN_FIRE_RL_fpu_div64_s1_stage ; - - // rule RL_fpu_sqr64_s5_stage - assign CAN_FIRE_RL_fpu_sqr64_s5_stage = - fpu_sqr64_fState_S4$EMPTY_N && fpu_sqr64_fResult_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s5_stage = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - - // rule RL_fpu_sqr64_s4_stage - assign CAN_FIRE_RL_fpu_sqr64_s4_stage = - fpu_sqr64_fState_S3$EMPTY_N && fpu_sqr64_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s4_stage = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - - // rule RL_fpu_sqr64_s3_stage - assign CAN_FIRE_RL_fpu_sqr64_s3_stage = - fpu_sqr64_fState_S2$EMPTY_N && fpu_sqr64_fState_S3$FULL_N && - (fpu_sqr64_fState_S2$D_OUT[136] || crg_done_1) ; - assign WILL_FIRE_RL_fpu_sqr64_s3_stage = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - - // rule RL_work_1 - assign CAN_FIRE_RL_work_1 = rg_busy_1 ; - assign WILL_FIRE_RL_work_1 = rg_busy_1 ; - - // rule RL_fpu_sqr64_s2_stage - assign CAN_FIRE_RL_fpu_sqr64_s2_stage = - fpu_sqr64_fState_S1$EMPTY_N && fpu_sqr64_fState_S2$FULL_N && - (fpu_sqr64_fState_S1$D_OUT[194] || !rg_busy_1) ; - assign WILL_FIRE_RL_fpu_sqr64_s2_stage = - CAN_FIRE_RL_fpu_sqr64_s2_stage && !rg_busy_1 ; - - // rule RL_fpu_sqr64_s1_stage - assign CAN_FIRE_RL_fpu_sqr64_s1_stage = - fpu_sqr64_fOperand_S0$EMPTY_N && fpu_sqr64_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_sqr64_s1_stage = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - - // rule RL_fpu_madd_s9_stage - assign CAN_FIRE_RL_fpu_madd_s9_stage = - fpu_madd_fState_S8$EMPTY_N && fpu_madd_fResult_S9$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s9_stage = CAN_FIRE_RL_fpu_madd_s9_stage ; - - // rule RL_fpu_madd_s8_stage - assign CAN_FIRE_RL_fpu_madd_s8_stage = - fpu_madd_fState_S7$EMPTY_N && fpu_madd_fState_S8$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s8_stage = CAN_FIRE_RL_fpu_madd_s8_stage ; - - // rule RL_fpu_madd_s7_stage - assign CAN_FIRE_RL_fpu_madd_s7_stage = - fpu_madd_fState_S6$EMPTY_N && fpu_madd_fState_S7$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s7_stage = CAN_FIRE_RL_fpu_madd_s7_stage ; - - // rule RL_fpu_madd_s6_stage - assign CAN_FIRE_RL_fpu_madd_s6_stage = - fpu_madd_fState_S5$EMPTY_N && fpu_madd_fState_S6$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s6_stage = CAN_FIRE_RL_fpu_madd_s6_stage ; - - // rule RL_fpu_madd_s5_stage - assign CAN_FIRE_RL_fpu_madd_s5_stage = - fpu_madd_fState_S4$EMPTY_N && fpu_madd_fState_S5$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s5_stage = CAN_FIRE_RL_fpu_madd_s5_stage ; - - // rule RL_fpu_madd_s4_stage - assign CAN_FIRE_RL_fpu_madd_s4_stage = - fpu_madd_fState_S3$EMPTY_N && fpu_madd_fProd_S3$EMPTY_N && - fpu_madd_fState_S4$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s4_stage = CAN_FIRE_RL_fpu_madd_s4_stage ; - - // rule RL_fpu_madd_s3_stage - assign CAN_FIRE_RL_fpu_madd_s3_stage = - fpu_madd_fState_S2$EMPTY_N && fpu_madd_fProd_S2$EMPTY_N && - fpu_madd_fProd_S3$FULL_N && - fpu_madd_fState_S3$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s3_stage = CAN_FIRE_RL_fpu_madd_s3_stage ; - - // rule RL_fpu_madd_s2_stage - assign CAN_FIRE_RL_fpu_madd_s2_stage = - fpu_madd_fState_S1$EMPTY_N && fpu_madd_fProd_S2$FULL_N && - fpu_madd_fState_S2$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s2_stage = CAN_FIRE_RL_fpu_madd_s2_stage ; - - // rule RL_fpu_madd_s1_stage - assign CAN_FIRE_RL_fpu_madd_s1_stage = - fpu_madd_fOperand_S0$EMPTY_N && fpu_madd_fState_S1$FULL_N ; - assign WILL_FIRE_RL_fpu_madd_s1_stage = CAN_FIRE_RL_fpu_madd_s1_stage ; - - // rule RL_start_op - assign CAN_FIRE_RL_start_op = - iFifo$EMPTY_N && isDoubleFifo$FULL_N && isNegateFifo$FULL_N && - rmdFifo$FULL_N && - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 ; - assign WILL_FIRE_RL_start_op = CAN_FIRE_RL_start_op ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = resetReqsF$EMPTY_N && resetRspsF$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_crg_done$port1__write_1__SEL_1 = rg_busy && rg_index == 6'd28 ; - assign MUX_crg_done$port1__write_1__SEL_2 = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - assign MUX_crg_done_1$port1__write_1__SEL_1 = - rg_busy_1 && rg_index_1 == 6'd29 ; - assign MUX_crg_done_1$port1__write_1__SEL_2 = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - assign MUX_rg_b$write_1__VAL_1 = - fpu_sqr64_fState_S1$D_OUT[57] ? - 116'h40000000000000000000000000000 : - b___1__h77160 ; - assign MUX_rg_b$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___fst__h1476 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign MUX_rg_d$write_1__VAL_1 = - { 1'd0, fpu_div64_fState_S1$D_OUT[67:11] } ; - assign MUX_rg_index$write_1__VAL_2 = rg_index + 6'd1 ; - assign MUX_rg_index_1$write_1__VAL_2 = rg_index_1 + 6'd1 ; - assign MUX_rg_q$write_1__VAL_2 = - rg_index_PLUS_1_ULE_57___d6 ? - { IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14[56:0], - !IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] } : - IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 ; - assign MUX_rg_r$write_1__VAL_1 = - { 2'd0, fpu_div64_fState_S1$D_OUT[181:68] } ; - assign MUX_rg_r$write_1__VAL_2 = - rg_index_PLUS_1_ULE_57___d6 ? - (IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[115] ? - { IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0], - 1'd0 } + - b__h32583 : - { IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22[114:0], - 1'd0 } - - b__h32583) : - IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 ; - assign MUX_rg_r_1$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___snd_snd_snd__h1481 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 ; - assign MUX_rg_res$write_1__VAL_2 = - { rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44 || - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0 : - IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44, - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 } ; - assign MUX_rg_s$write_1__VAL_1 = - { fpu_sqr64_fState_S1$D_OUT[57:0], 58'd0 } ; - assign MUX_rg_s$write_1__VAL_2 = - rg_index_1_4_PLUS_1_6_ULE_58___d37 ? - _theResult___snd_fst__h1478 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 ; - - // inlined wires - always@(fpu_div64_fResult_S5$EMPTY_N or - fpu_div64_fResult_S5$D_OUT or - fpu_sqr64_fResult_S5$EMPTY_N or - fpu_sqr64_fResult_S5$D_OUT or - fpu_madd_fResult_S9$EMPTY_N or fpu_madd_fResult_S9$D_OUT) - begin - case (1'b1) // synopsys parallel_case - fpu_div64_fResult_S5$EMPTY_N: resWire$wget = fpu_div64_fResult_S5$D_OUT; - fpu_sqr64_fResult_S5$EMPTY_N: resWire$wget = fpu_sqr64_fResult_S5$D_OUT; - fpu_madd_fResult_S9$EMPTY_N: resWire$wget = fpu_madd_fResult_S9$D_OUT; - default: resWire$wget = 69'h0AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign resWire$whas = - fpu_div64_fResult_S5$EMPTY_N || fpu_sqr64_fResult_S5$EMPTY_N || - fpu_madd_fResult_S9$EMPTY_N ; - assign crg_done$EN_port0__write = - WILL_FIRE_RL_fpu_div64_s3_stage && - !fpu_div64_fState_S2$D_OUT[147] ; - assign crg_done$port1__read = !crg_done$EN_port0__write && crg_done ; - assign crg_done$EN_port1__write = - rg_busy && rg_index == 6'd28 || - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - assign crg_done$port2__read = - crg_done$EN_port1__write ? - MUX_crg_done$port1__write_1__SEL_1 : - crg_done$port1__read ; - assign crg_done_1$EN_port0__write = - WILL_FIRE_RL_fpu_sqr64_s3_stage && - !fpu_sqr64_fState_S2$D_OUT[136] ; - assign crg_done_1$port1__read = !crg_done_1$EN_port0__write && crg_done_1 ; - assign crg_done_1$EN_port1__write = - rg_busy_1 && rg_index_1 == 6'd29 || - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - assign crg_done_1$port2__read = - crg_done_1$EN_port1__write ? - MUX_crg_done_1$port1__write_1__SEL_1 : - crg_done_1$port1__read ; - - // register crg_done - assign crg_done$D_IN = crg_done$port2__read ; - assign crg_done$EN = 1'b1 ; - - // register crg_done_1 - assign crg_done_1$D_IN = crg_done_1$port2__read ; - assign crg_done_1$EN = 1'b1 ; - - // register rg_b - assign rg_b$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - MUX_rg_b$write_1__VAL_1 : - MUX_rg_b$write_1__VAL_2 ; - assign rg_b$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_busy - assign rg_busy$D_IN = !MUX_crg_done$port1__write_1__SEL_1 ; - assign rg_busy$EN = - rg_busy && rg_index == 6'd28 || - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] ; - - // register rg_busy_1 - assign rg_busy_1$D_IN = !MUX_crg_done_1$port1__write_1__SEL_1 ; - assign rg_busy_1$EN = - rg_busy_1 && rg_index_1 == 6'd29 || - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] ; - - // register rg_d - assign rg_d$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - MUX_rg_d$write_1__VAL_1 : - rg_d ; - assign rg_d$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_index - assign rg_index$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - 6'd0 : - MUX_rg_index$write_1__VAL_2 ; - assign rg_index$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_index_1 - assign rg_index_1$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 6'd0 : - MUX_rg_index_1$write_1__VAL_2 ; - assign rg_index_1$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_q - assign rg_q$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - 58'd0 : - MUX_rg_q$write_1__VAL_2 ; - assign rg_q$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_r - assign rg_r$D_IN = - MUX_crg_done$port1__write_1__SEL_2 ? - MUX_rg_r$write_1__VAL_1 : - MUX_rg_r$write_1__VAL_2 ; - assign rg_r$EN = - WILL_FIRE_RL_fpu_div64_s2_stage && - !fpu_div64_fState_S1$D_OUT[318] || - rg_busy ; - - // register rg_r_1 - assign rg_r_1$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 116'd0 : - MUX_rg_r_1$write_1__VAL_2 ; - assign rg_r_1$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_res - assign rg_res$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - MUX_rg_res$write_1__VAL_2 ; - assign rg_res$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // register rg_s - assign rg_s$D_IN = - MUX_crg_done_1$port1__write_1__SEL_2 ? - MUX_rg_s$write_1__VAL_1 : - MUX_rg_s$write_1__VAL_2 ; - assign rg_s$EN = - WILL_FIRE_RL_fpu_sqr64_s2_stage && - !fpu_sqr64_fState_S1$D_OUT[194] || - rg_busy_1 ; - - // submodule fpu_div64_fOperands_S0 - assign fpu_div64_fOperands_S0$D_IN = - { IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330, - iFifo$D_OUT[6:4] } ; - assign fpu_div64_fOperands_S0$ENQ = - WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd3 ; - assign fpu_div64_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_div64_s1_stage ; - assign fpu_div64_fOperands_S0$CLR = 1'b0 ; - - // submodule fpu_div64_fResult_S5 - assign fpu_div64_fResult_S5$D_IN = - fpu_div64_fState_S4$D_OUT[138] ? - fpu_div64_fState_S4$D_OUT[137:69] : - { (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[65:2] : - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173, - fpu_div64_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h43556 == 11'd2047 && - _theResult___fst_sfd__h43557 == 52'd0, - 1'd0, - fpu_div64_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_div64_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_div64_fResult_S5$ENQ = CAN_FIRE_RL_fpu_div64_s5_stage ; - assign fpu_div64_fResult_S5$DEQ = fpu_div64_fResult_S5$EMPTY_N ; - assign fpu_div64_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S1 - assign fpu_div64_fState_S1$D_IN = - { fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363, - (fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118]) ? - { fpu_div64_fOperands_S0$D_OUT[130:119], sfd__h18934 } : - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455, - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0), - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - !IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481, - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[54]) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[118]) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - !fpu_div64_fOperands_S0$D_OUT[54]) && - NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488, - fpu_div64_fOperands_S0$D_OUT[2:0], - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405, - _theResult___snd_fst_exp__h31361, - _theResult___snd_fst_sfd__h31362, - x__h31426, - x__h31487, - x__h31541 } ; - assign fpu_div64_fState_S1$ENQ = CAN_FIRE_RL_fpu_div64_s1_stage ; - assign fpu_div64_fState_S1$DEQ = WILL_FIRE_RL_fpu_div64_s2_stage ; - assign fpu_div64_fState_S1$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S2 - assign fpu_div64_fState_S2$D_IN = - { fpu_div64_fState_S1$D_OUT[318:182], - fpu_div64_fState_S1$D_OUT[10:0] } ; - assign fpu_div64_fState_S2$ENQ = WILL_FIRE_RL_fpu_div64_s2_stage ; - assign fpu_div64_fState_S2$DEQ = CAN_FIRE_RL_fpu_div64_s3_stage ; - assign fpu_div64_fState_S2$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S3 - assign fpu_div64_fState_S3$D_IN = - { fpu_div64_fState_S2$D_OUT[147:11], x__h33052 } ; - assign fpu_div64_fState_S3$ENQ = CAN_FIRE_RL_fpu_div64_s3_stage ; - assign fpu_div64_fState_S3$DEQ = CAN_FIRE_RL_fpu_div64_s4_stage ; - assign fpu_div64_fState_S3$CLR = 1'b0 ; - - // submodule fpu_div64_fState_S4 - assign fpu_div64_fState_S4$D_IN = - { (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[194] : - fpu_div64_fState_S3$D_OUT[194], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - fpu_div64_fState_S3$D_OUT[193:130] : - { CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174, - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 }) : - fpu_div64_fState_S3$D_OUT[193:130], - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926, - fpu_div64_fState_S3$D_OUT[124:122], - fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936, - x__h42705 } ; - assign fpu_div64_fState_S4$ENQ = CAN_FIRE_RL_fpu_div64_s4_stage ; - assign fpu_div64_fState_S4$DEQ = CAN_FIRE_RL_fpu_div64_s5_stage ; - assign fpu_div64_fState_S4$CLR = 1'b0 ; - - // submodule fpu_madd_fOperand_S0 - assign fpu_madd_fOperand_S0$D_IN = - { iFifo$D_OUT[3:0] != 4'd2, - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623, - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176, - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177, - iFifo$D_OUT[6:4] } ; - assign fpu_madd_fOperand_S0$ENQ = - WILL_FIRE_RL_start_op && - (iFifo$D_OUT[3:0] == 4'd0 || iFifo$D_OUT[3:0] == 4'd1 || - iFifo$D_OUT[3:0] == 4'd2 || - iFifo$D_OUT[3:0] == 4'd5 || - iFifo$D_OUT[3:0] == 4'd6 || - iFifo$D_OUT[3:0] == 4'd7 || - iFifo$D_OUT[3:0] == 4'd8) ; - assign fpu_madd_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_madd_s1_stage ; - assign fpu_madd_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_madd_fProd_S2 - assign fpu_madd_fProd_S2$D_IN = - fpu_madd_fState_S1$D_OUT[105:53] * - fpu_madd_fState_S1$D_OUT[52:0] ; - assign fpu_madd_fProd_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fProd_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fProd_S2$CLR = 1'b0 ; - - // submodule fpu_madd_fProd_S3 - assign fpu_madd_fProd_S3$D_IN = fpu_madd_fProd_S2$D_OUT ; - assign fpu_madd_fProd_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fProd_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fProd_S3$CLR = 1'b0 ; - - // submodule fpu_madd_fResult_S9 - assign fpu_madd_fResult_S9$D_IN = - fpu_madd_fState_S8$D_OUT[140] ? - fpu_madd_fState_S8$D_OUT[139:71] : - IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 ; - assign fpu_madd_fResult_S9$ENQ = CAN_FIRE_RL_fpu_madd_s9_stage ; - assign fpu_madd_fResult_S9$DEQ = fpu_madd_fResult_S9$EMPTY_N ; - assign fpu_madd_fResult_S9$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S1 - assign fpu_madd_fState_S1$D_IN = - { x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54] || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861, - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939, - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947, - 4'd0, - fpu_madd_fOperand_S0$D_OUT[2:0], - fpu_madd_fOperand_S0$D_OUT[195], - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911, - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 } ; - assign fpu_madd_fState_S1$ENQ = CAN_FIRE_RL_fpu_madd_s1_stage ; - assign fpu_madd_fState_S1$DEQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fState_S1$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S2 - assign fpu_madd_fState_S2$D_IN = fpu_madd_fState_S1$D_OUT[257:106] ; - assign fpu_madd_fState_S2$ENQ = CAN_FIRE_RL_fpu_madd_s2_stage ; - assign fpu_madd_fState_S2$DEQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fState_S2$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S3 - assign fpu_madd_fState_S3$D_IN = fpu_madd_fState_S2$D_OUT ; - assign fpu_madd_fState_S3$ENQ = CAN_FIRE_RL_fpu_madd_s3_stage ; - assign fpu_madd_fState_S3$DEQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fState_S3$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S4 - assign fpu_madd_fState_S4$D_IN = - { fpu_madd_fState_S3$D_OUT[151:87], - IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525, - fpu_madd_fState_S3$D_OUT[81:14], - !fpu_madd_fState_S3$D_OUT[151] && fpu_madd_fState_S3$D_OUT[13], - fpu_madd_fState_S3$D_OUT[151] ? - 63'd0 : - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536, - x__h131406 } ; - assign fpu_madd_fState_S4$ENQ = CAN_FIRE_RL_fpu_madd_s4_stage ; - assign fpu_madd_fState_S4$DEQ = CAN_FIRE_RL_fpu_madd_s5_stage ; - assign fpu_madd_fState_S4$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S5 - assign fpu_madd_fState_S5$D_IN = - { fpu_madd_fState_S4$D_OUT[203:130], - fpu_madd_fState_S4$D_OUT[129] != fpu_madd_fState_S4$D_OUT[65], - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - fpu_madd_fState_S4$D_OUT[65] : - fpu_madd_fState_S4$D_OUT[129], - IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 } ; - assign fpu_madd_fState_S5$ENQ = CAN_FIRE_RL_fpu_madd_s5_stage ; - assign fpu_madd_fState_S5$DEQ = CAN_FIRE_RL_fpu_madd_s6_stage ; - assign fpu_madd_fState_S5$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S6 - assign fpu_madd_fState_S6$D_IN = - { fpu_madd_fState_S5$D_OUT[215:127], - fpu_madd_fState_S5$D_OUT[113:57], - x__h132359 } ; - assign fpu_madd_fState_S6$ENQ = CAN_FIRE_RL_fpu_madd_s6_stage ; - assign fpu_madd_fState_S6$DEQ = CAN_FIRE_RL_fpu_madd_s7_stage ; - assign fpu_madd_fState_S6$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S7 - assign fpu_madd_fState_S7$D_IN = - { fpu_madd_fState_S6$D_OUT[202:114], x__h132871, x__h132880 } ; - assign fpu_madd_fState_S7$ENQ = CAN_FIRE_RL_fpu_madd_s7_stage ; - assign fpu_madd_fState_S7$DEQ = CAN_FIRE_RL_fpu_madd_s8_stage ; - assign fpu_madd_fState_S7$CLR = 1'b0 ; - - // submodule fpu_madd_fState_S8 - assign fpu_madd_fState_S8$D_IN = - { fpu_madd_fState_S7$D_OUT[202:138], - fpu_madd_fState_S7$D_OUT[202] ? - fpu_madd_fState_S7$D_OUT[137:133] : - fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942, - fpu_madd_fState_S7$D_OUT[132:129], - !fpu_madd_fState_S7$D_OUT[202] && - fpu_madd_fState_S7$D_OUT[127], - fpu_madd_fState_S7$D_OUT[202] ? - 63'd0 : - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952, - x__h141760, - fpu_madd_fState_S7$D_OUT[128] } ; - assign fpu_madd_fState_S8$ENQ = CAN_FIRE_RL_fpu_madd_s8_stage ; - assign fpu_madd_fState_S8$DEQ = CAN_FIRE_RL_fpu_madd_s9_stage ; - assign fpu_madd_fState_S8$CLR = 1'b0 ; - - // submodule fpu_sqr64_fOperand_S0 - assign fpu_sqr64_fOperand_S0$D_IN = - { IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848, - iFifo$D_OUT[6:4] } ; - assign fpu_sqr64_fOperand_S0$ENQ = - WILL_FIRE_RL_start_op && iFifo$D_OUT[3:0] == 4'd4 ; - assign fpu_sqr64_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - assign fpu_sqr64_fOperand_S0$CLR = 1'b0 ; - - // submodule fpu_sqr64_fResult_S5 - assign fpu_sqr64_fResult_S5$D_IN = - fpu_sqr64_fState_S4$D_OUT[138] ? - fpu_sqr64_fState_S4$D_OUT[137:69] : - { (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[65:2] : - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183, - fpu_sqr64_fState_S4$D_OUT[73:69] | - { 2'd0, - _theResult___fst_exp__h95990 == 11'd2047 && - _theResult___fst_sfd__h95991 == 52'd0, - 1'd0, - fpu_sqr64_fState_S4$D_OUT[64:54] != 11'd2047 && - fpu_sqr64_fState_S4$D_OUT[1:0] != 2'b0 } } ; - assign fpu_sqr64_fResult_S5$ENQ = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - assign fpu_sqr64_fResult_S5$DEQ = fpu_sqr64_fResult_S5$EMPTY_N ; - assign fpu_sqr64_fResult_S5$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S1 - assign fpu_sqr64_fState_S1$D_IN = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_sqr64_fOperand_S0$D_OUT[54]) ? - { 1'd1, - fpu_sqr64_fOperand_S0$D_OUT[66:55], - sfd__h45004, - 130'h20AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212 ; - assign fpu_sqr64_fState_S1$ENQ = CAN_FIRE_RL_fpu_sqr64_s1_stage ; - assign fpu_sqr64_fState_S1$DEQ = WILL_FIRE_RL_fpu_sqr64_s2_stage ; - assign fpu_sqr64_fState_S1$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S2 - assign fpu_sqr64_fState_S2$D_IN = fpu_sqr64_fState_S1$D_OUT[194:58] ; - assign fpu_sqr64_fState_S2$ENQ = WILL_FIRE_RL_fpu_sqr64_s2_stage ; - assign fpu_sqr64_fState_S2$DEQ = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - assign fpu_sqr64_fState_S2$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S3 - assign fpu_sqr64_fState_S3$D_IN = { fpu_sqr64_fState_S2$D_OUT, x__h86149 } ; - assign fpu_sqr64_fState_S3$ENQ = CAN_FIRE_RL_fpu_sqr64_s3_stage ; - assign fpu_sqr64_fState_S3$DEQ = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - assign fpu_sqr64_fState_S3$CLR = 1'b0 ; - - // submodule fpu_sqr64_fState_S4 - assign fpu_sqr64_fState_S4$D_IN = - { fpu_sqr64_fState_S3$D_OUT[195:131], - fpu_sqr64_fState_S3$D_OUT[195] && - fpu_sqr64_fState_S3$D_OUT[130], - fpu_sqr64_fState_S3$D_OUT[195] && - fpu_sqr64_fState_S3$D_OUT[129], - IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671, - fpu_sqr64_fState_S3$D_OUT[125:122], - fpu_sqr64_fState_S3$D_OUT[195] ? - fpu_sqr64_fState_S3$D_OUT[121:59] : - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678, - x__h95138 } ; - assign fpu_sqr64_fState_S4$ENQ = CAN_FIRE_RL_fpu_sqr64_s4_stage ; - assign fpu_sqr64_fState_S4$DEQ = CAN_FIRE_RL_fpu_sqr64_s5_stage ; - assign fpu_sqr64_fState_S4$CLR = 1'b0 ; - - // submodule iFifo - assign iFifo$D_IN = server_core_request_put ; - assign iFifo$ENQ = EN_server_core_request_put ; - assign iFifo$DEQ = CAN_FIRE_RL_start_op ; - assign iFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule isDoubleFifo - assign isDoubleFifo$D_IN = !iFifo$D_OUT[201] ; - assign isDoubleFifo$ENQ = CAN_FIRE_RL_start_op ; - assign isDoubleFifo$DEQ = CAN_FIRE_RL_passResult ; - assign isDoubleFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule isNegateFifo - assign isNegateFifo$D_IN = - iFifo$D_OUT[3:0] == 4'd7 || iFifo$D_OUT[3:0] == 4'd8 ; - assign isNegateFifo$ENQ = CAN_FIRE_RL_start_op ; - assign isNegateFifo$DEQ = CAN_FIRE_RL_passResult ; - assign isNegateFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule oFifo - assign oFifo$D_IN = - { !isDoubleFifo$D_OUT, - IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657, - isDoubleFifo$D_OUT ? - resWire$wget[4:0] : - resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 } ; - assign oFifo$ENQ = CAN_FIRE_RL_passResult ; - assign oFifo$DEQ = EN_server_core_response_get ; - assign oFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule resetReqsF - assign resetReqsF$ENQ = EN_server_reset_request_put ; - assign resetReqsF$DEQ = CAN_FIRE_RL_rl_reset ; - assign resetReqsF$CLR = 1'b0 ; - - // submodule resetRspsF - assign resetRspsF$ENQ = CAN_FIRE_RL_rl_reset ; - assign resetRspsF$DEQ = EN_server_reset_response_get ; - assign resetRspsF$CLR = 1'b0 ; - - // submodule rmdFifo - assign rmdFifo$D_IN = iFifo$D_OUT[6:4] ; - assign rmdFifo$ENQ = CAN_FIRE_RL_start_op ; - assign rmdFifo$DEQ = CAN_FIRE_RL_passResult ; - assign rmdFifo$CLR = CAN_FIRE_RL_rl_reset ; - - // remaining internal signals - assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133 = - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 ? - _theResult___snd__h277749 : - _theResult____h269577 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 ? - _theResult___snd__h172915 : - _theResult____h164614 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 ? - _theResult___snd__h250492 : - _theResult____h242191 ; - assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97 = - _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 ? - _theResult___snd__h211553 : - _theResult____h203252 ; - assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139 = - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 ? - _theResult___snd__h295515 : - _theResult____h287214 ; - assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24 = - _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 ? - _theResult___snd__h131023 : - _theResult___snd__h131018 ; - assign IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12 = - _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883 ? - _theResult___snd__h42409 : - _theResult___snd__h42404 ; - assign IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29 = - _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 ? - _theResult___snd__h141449 : - _theResult___snd__h141444 ; - assign IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19 = - _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633 ? - _theResult___snd__h94826 : - _theResult___snd__h94821 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100 = - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 ? - _theResult___snd__h201963 : - _theResult___snd__h220275 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93 = - _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 ? - _theResult___snd__h201963 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33 = - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 ? - _theResult___snd__h163325 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40 = - _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 ? - _theResult___snd__h163325 : - _theResult___snd__h181637 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60 = - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 ? - _theResult___snd__h240902 : - 57'd0 ; - assign IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67 = - _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 ? - _theResult___snd__h240902 : - _theResult___snd__h259214 ; - assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135 = - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 ? - _theResult___snd__h286331 : - 57'd0 ; - assign IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142 = - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 ? - _theResult___snd__h286331 : - _theResult___snd__h304121 ; - assign IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h43566, sfd__h42982[52:1] }) : - { IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977, - sfd__h42982[51:0] } ; - assign IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h142626, sfd__h142040[52:1] }) : - { IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986, - sfd__h142040[51:0] } ; - assign IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 63'h7FF0000000000000 : - { din_inc___2_exp__h96000, sfd__h95416[52:1] }) : - { IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721, - sfd__h95416[51:0] } ; - assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - ((_theResult___fst_exp__h277686 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823) : - ((_theResult___fst_exp__h286342 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023) ; - assign IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - ((_theResult___fst_exp__h277686 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388) : - ((_theResult___fst_exp__h286342 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[168] : - ((_theResult___fst_exp__h163336 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[38] : - ((_theResult___fst_exp__h240913 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 && - iFifo$D_OUT[6:4] != 3'd2 && - iFifo$D_OUT[6:4] != 3'd3 && - iFifo$D_OUT[6:4] != 3'd4 || - !iFifo$D_OUT[38] : - ((_theResult___fst_exp__h240913 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - (iFifo$D_OUT[6:4] == 3'd0 || iFifo$D_OUT[6:4] == 3'd1 || - iFifo$D_OUT[6:4] == 3'd2 || - iFifo$D_OUT[6:4] == 3'd3 || - iFifo$D_OUT[6:4] == 3'd4) && - iFifo$D_OUT[103] : - ((_theResult___fst_exp__h201974 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115) ; - assign IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - iFifo$D_OUT[6:4] != 3'd0 && iFifo$D_OUT[6:4] != 3'd1 && - iFifo$D_OUT[6:4] != 3'd2 && - iFifo$D_OUT[6:4] != 3'd3 && - iFifo$D_OUT[6:4] != 3'd4 || - !iFifo$D_OUT[103] : - ((_theResult___fst_exp__h201974 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121) ; - assign IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 = - (_theResult____h269577[56] ? - 6'd0 : - (_theResult____h269577[55] ? - 6'd1 : - (_theResult____h269577[54] ? - 6'd2 : - (_theResult____h269577[53] ? - 6'd3 : - (_theResult____h269577[52] ? - 6'd4 : - (_theResult____h269577[51] ? - 6'd5 : - (_theResult____h269577[50] ? - 6'd6 : - (_theResult____h269577[49] ? - 6'd7 : - (_theResult____h269577[48] ? - 6'd8 : - (_theResult____h269577[47] ? - 6'd9 : - (_theResult____h269577[46] ? - 6'd10 : - (_theResult____h269577[45] ? - 6'd11 : - (_theResult____h269577[44] ? - 6'd12 : - (_theResult____h269577[43] ? - 6'd13 : - (_theResult____h269577[42] ? - 6'd14 : - (_theResult____h269577[41] ? - 6'd15 : - (_theResult____h269577[40] ? - 6'd16 : - (_theResult____h269577[39] ? - 6'd17 : - (_theResult____h269577[38] ? - 6'd18 : - (_theResult____h269577[37] ? - 6'd19 : - (_theResult____h269577[36] ? - 6'd20 : - (_theResult____h269577[35] ? - 6'd21 : - (_theResult____h269577[34] ? - 6'd22 : - (_theResult____h269577[33] ? - 6'd23 : - (_theResult____h269577[32] ? - 6'd24 : - (_theResult____h269577[31] ? - 6'd25 : - (_theResult____h269577[30] ? - 6'd26 : - (_theResult____h269577[29] ? - 6'd27 : - (_theResult____h269577[28] ? - 6'd28 : - (_theResult____h269577[27] ? - 6'd29 : - (_theResult____h269577[26] ? - 6'd30 : - (_theResult____h269577[25] ? - 6'd31 : - (_theResult____h269577[24] ? - 6'd32 : - (_theResult____h269577[23] ? - 6'd33 : - (_theResult____h269577[22] ? - 6'd34 : - (_theResult____h269577[21] ? - 6'd35 : - (_theResult____h269577[20] ? - 6'd36 : - (_theResult____h269577[19] ? - 6'd37 : - (_theResult____h269577[18] ? - 6'd38 : - (_theResult____h269577[17] ? - 6'd39 : - (_theResult____h269577[16] ? - 6'd40 : - (_theResult____h269577[15] ? - 6'd41 : - (_theResult____h269577[14] ? - 6'd42 : - (_theResult____h269577[13] ? - 6'd43 : - (_theResult____h269577[12] ? - 6'd44 : - (_theResult____h269577[11] ? - 6'd45 : - (_theResult____h269577[10] ? - 6'd46 : - (_theResult____h269577[9] ? - 6'd47 : - (_theResult____h269577[8] ? - 6'd48 : - (_theResult____h269577[7] ? - 6'd49 : - (_theResult____h269577[6] ? - 6'd50 : - (_theResult____h269577[5] ? - 6'd51 : - (_theResult____h269577[4] ? - 6'd52 : - (_theResult____h269577[3] ? - 6'd53 : - (_theResult____h269577[2] ? - 6'd54 : - (_theResult____h269577[1] ? - 6'd55 : - (_theResult____h269577[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 = - (_theResult____h203252[56] ? - 6'd0 : - (_theResult____h203252[55] ? - 6'd1 : - (_theResult____h203252[54] ? - 6'd2 : - (_theResult____h203252[53] ? - 6'd3 : - (_theResult____h203252[52] ? - 6'd4 : - (_theResult____h203252[51] ? - 6'd5 : - (_theResult____h203252[50] ? - 6'd6 : - (_theResult____h203252[49] ? - 6'd7 : - (_theResult____h203252[48] ? - 6'd8 : - (_theResult____h203252[47] ? - 6'd9 : - (_theResult____h203252[46] ? - 6'd10 : - (_theResult____h203252[45] ? - 6'd11 : - (_theResult____h203252[44] ? - 6'd12 : - (_theResult____h203252[43] ? - 6'd13 : - (_theResult____h203252[42] ? - 6'd14 : - (_theResult____h203252[41] ? - 6'd15 : - (_theResult____h203252[40] ? - 6'd16 : - (_theResult____h203252[39] ? - 6'd17 : - (_theResult____h203252[38] ? - 6'd18 : - (_theResult____h203252[37] ? - 6'd19 : - (_theResult____h203252[36] ? - 6'd20 : - (_theResult____h203252[35] ? - 6'd21 : - (_theResult____h203252[34] ? - 6'd22 : - (_theResult____h203252[33] ? - 6'd23 : - (_theResult____h203252[32] ? - 6'd24 : - (_theResult____h203252[31] ? - 6'd25 : - (_theResult____h203252[30] ? - 6'd26 : - (_theResult____h203252[29] ? - 6'd27 : - (_theResult____h203252[28] ? - 6'd28 : - (_theResult____h203252[27] ? - 6'd29 : - (_theResult____h203252[26] ? - 6'd30 : - (_theResult____h203252[25] ? - 6'd31 : - (_theResult____h203252[24] ? - 6'd32 : - (_theResult____h203252[23] ? - 6'd33 : - (_theResult____h203252[22] ? - 6'd34 : - (_theResult____h203252[21] ? - 6'd35 : - (_theResult____h203252[20] ? - 6'd36 : - (_theResult____h203252[19] ? - 6'd37 : - (_theResult____h203252[18] ? - 6'd38 : - (_theResult____h203252[17] ? - 6'd39 : - (_theResult____h203252[16] ? - 6'd40 : - (_theResult____h203252[15] ? - 6'd41 : - (_theResult____h203252[14] ? - 6'd42 : - (_theResult____h203252[13] ? - 6'd43 : - (_theResult____h203252[12] ? - 6'd44 : - (_theResult____h203252[11] ? - 6'd45 : - (_theResult____h203252[10] ? - 6'd46 : - (_theResult____h203252[9] ? - 6'd47 : - (_theResult____h203252[8] ? - 6'd48 : - (_theResult____h203252[7] ? - 6'd49 : - (_theResult____h203252[6] ? - 6'd50 : - (_theResult____h203252[5] ? - 6'd51 : - (_theResult____h203252[4] ? - 6'd52 : - (_theResult____h203252[3] ? - 6'd53 : - (_theResult____h203252[2] ? - 6'd54 : - (_theResult____h203252[1] ? - 6'd55 : - (_theResult____h203252[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 = - (_theResult____h164614[56] ? - 6'd0 : - (_theResult____h164614[55] ? - 6'd1 : - (_theResult____h164614[54] ? - 6'd2 : - (_theResult____h164614[53] ? - 6'd3 : - (_theResult____h164614[52] ? - 6'd4 : - (_theResult____h164614[51] ? - 6'd5 : - (_theResult____h164614[50] ? - 6'd6 : - (_theResult____h164614[49] ? - 6'd7 : - (_theResult____h164614[48] ? - 6'd8 : - (_theResult____h164614[47] ? - 6'd9 : - (_theResult____h164614[46] ? - 6'd10 : - (_theResult____h164614[45] ? - 6'd11 : - (_theResult____h164614[44] ? - 6'd12 : - (_theResult____h164614[43] ? - 6'd13 : - (_theResult____h164614[42] ? - 6'd14 : - (_theResult____h164614[41] ? - 6'd15 : - (_theResult____h164614[40] ? - 6'd16 : - (_theResult____h164614[39] ? - 6'd17 : - (_theResult____h164614[38] ? - 6'd18 : - (_theResult____h164614[37] ? - 6'd19 : - (_theResult____h164614[36] ? - 6'd20 : - (_theResult____h164614[35] ? - 6'd21 : - (_theResult____h164614[34] ? - 6'd22 : - (_theResult____h164614[33] ? - 6'd23 : - (_theResult____h164614[32] ? - 6'd24 : - (_theResult____h164614[31] ? - 6'd25 : - (_theResult____h164614[30] ? - 6'd26 : - (_theResult____h164614[29] ? - 6'd27 : - (_theResult____h164614[28] ? - 6'd28 : - (_theResult____h164614[27] ? - 6'd29 : - (_theResult____h164614[26] ? - 6'd30 : - (_theResult____h164614[25] ? - 6'd31 : - (_theResult____h164614[24] ? - 6'd32 : - (_theResult____h164614[23] ? - 6'd33 : - (_theResult____h164614[22] ? - 6'd34 : - (_theResult____h164614[21] ? - 6'd35 : - (_theResult____h164614[20] ? - 6'd36 : - (_theResult____h164614[19] ? - 6'd37 : - (_theResult____h164614[18] ? - 6'd38 : - (_theResult____h164614[17] ? - 6'd39 : - (_theResult____h164614[16] ? - 6'd40 : - (_theResult____h164614[15] ? - 6'd41 : - (_theResult____h164614[14] ? - 6'd42 : - (_theResult____h164614[13] ? - 6'd43 : - (_theResult____h164614[12] ? - 6'd44 : - (_theResult____h164614[11] ? - 6'd45 : - (_theResult____h164614[10] ? - 6'd46 : - (_theResult____h164614[9] ? - 6'd47 : - (_theResult____h164614[8] ? - 6'd48 : - (_theResult____h164614[7] ? - 6'd49 : - (_theResult____h164614[6] ? - 6'd50 : - (_theResult____h164614[5] ? - 6'd51 : - (_theResult____h164614[4] ? - 6'd52 : - (_theResult____h164614[3] ? - 6'd53 : - (_theResult____h164614[2] ? - 6'd54 : - (_theResult____h164614[1] ? - 6'd55 : - (_theResult____h164614[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 = - (_theResult____h242191[56] ? - 6'd0 : - (_theResult____h242191[55] ? - 6'd1 : - (_theResult____h242191[54] ? - 6'd2 : - (_theResult____h242191[53] ? - 6'd3 : - (_theResult____h242191[52] ? - 6'd4 : - (_theResult____h242191[51] ? - 6'd5 : - (_theResult____h242191[50] ? - 6'd6 : - (_theResult____h242191[49] ? - 6'd7 : - (_theResult____h242191[48] ? - 6'd8 : - (_theResult____h242191[47] ? - 6'd9 : - (_theResult____h242191[46] ? - 6'd10 : - (_theResult____h242191[45] ? - 6'd11 : - (_theResult____h242191[44] ? - 6'd12 : - (_theResult____h242191[43] ? - 6'd13 : - (_theResult____h242191[42] ? - 6'd14 : - (_theResult____h242191[41] ? - 6'd15 : - (_theResult____h242191[40] ? - 6'd16 : - (_theResult____h242191[39] ? - 6'd17 : - (_theResult____h242191[38] ? - 6'd18 : - (_theResult____h242191[37] ? - 6'd19 : - (_theResult____h242191[36] ? - 6'd20 : - (_theResult____h242191[35] ? - 6'd21 : - (_theResult____h242191[34] ? - 6'd22 : - (_theResult____h242191[33] ? - 6'd23 : - (_theResult____h242191[32] ? - 6'd24 : - (_theResult____h242191[31] ? - 6'd25 : - (_theResult____h242191[30] ? - 6'd26 : - (_theResult____h242191[29] ? - 6'd27 : - (_theResult____h242191[28] ? - 6'd28 : - (_theResult____h242191[27] ? - 6'd29 : - (_theResult____h242191[26] ? - 6'd30 : - (_theResult____h242191[25] ? - 6'd31 : - (_theResult____h242191[24] ? - 6'd32 : - (_theResult____h242191[23] ? - 6'd33 : - (_theResult____h242191[22] ? - 6'd34 : - (_theResult____h242191[21] ? - 6'd35 : - (_theResult____h242191[20] ? - 6'd36 : - (_theResult____h242191[19] ? - 6'd37 : - (_theResult____h242191[18] ? - 6'd38 : - (_theResult____h242191[17] ? - 6'd39 : - (_theResult____h242191[16] ? - 6'd40 : - (_theResult____h242191[15] ? - 6'd41 : - (_theResult____h242191[14] ? - 6'd42 : - (_theResult____h242191[13] ? - 6'd43 : - (_theResult____h242191[12] ? - 6'd44 : - (_theResult____h242191[11] ? - 6'd45 : - (_theResult____h242191[10] ? - 6'd46 : - (_theResult____h242191[9] ? - 6'd47 : - (_theResult____h242191[8] ? - 6'd48 : - (_theResult____h242191[7] ? - 6'd49 : - (_theResult____h242191[6] ? - 6'd50 : - (_theResult____h242191[5] ? - 6'd51 : - (_theResult____h242191[4] ? - 6'd52 : - (_theResult____h242191[3] ? - 6'd53 : - (_theResult____h242191[2] ? - 6'd54 : - (_theResult____h242191[1] ? - 6'd55 : - (_theResult____h242191[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 = - (_theResult____h287214[56] ? - 6'd0 : - (_theResult____h287214[55] ? - 6'd1 : - (_theResult____h287214[54] ? - 6'd2 : - (_theResult____h287214[53] ? - 6'd3 : - (_theResult____h287214[52] ? - 6'd4 : - (_theResult____h287214[51] ? - 6'd5 : - (_theResult____h287214[50] ? - 6'd6 : - (_theResult____h287214[49] ? - 6'd7 : - (_theResult____h287214[48] ? - 6'd8 : - (_theResult____h287214[47] ? - 6'd9 : - (_theResult____h287214[46] ? - 6'd10 : - (_theResult____h287214[45] ? - 6'd11 : - (_theResult____h287214[44] ? - 6'd12 : - (_theResult____h287214[43] ? - 6'd13 : - (_theResult____h287214[42] ? - 6'd14 : - (_theResult____h287214[41] ? - 6'd15 : - (_theResult____h287214[40] ? - 6'd16 : - (_theResult____h287214[39] ? - 6'd17 : - (_theResult____h287214[38] ? - 6'd18 : - (_theResult____h287214[37] ? - 6'd19 : - (_theResult____h287214[36] ? - 6'd20 : - (_theResult____h287214[35] ? - 6'd21 : - (_theResult____h287214[34] ? - 6'd22 : - (_theResult____h287214[33] ? - 6'd23 : - (_theResult____h287214[32] ? - 6'd24 : - (_theResult____h287214[31] ? - 6'd25 : - (_theResult____h287214[30] ? - 6'd26 : - (_theResult____h287214[29] ? - 6'd27 : - (_theResult____h287214[28] ? - 6'd28 : - (_theResult____h287214[27] ? - 6'd29 : - (_theResult____h287214[26] ? - 6'd30 : - (_theResult____h287214[25] ? - 6'd31 : - (_theResult____h287214[24] ? - 6'd32 : - (_theResult____h287214[23] ? - 6'd33 : - (_theResult____h287214[22] ? - 6'd34 : - (_theResult____h287214[21] ? - 6'd35 : - (_theResult____h287214[20] ? - 6'd36 : - (_theResult____h287214[19] ? - 6'd37 : - (_theResult____h287214[18] ? - 6'd38 : - (_theResult____h287214[17] ? - 6'd39 : - (_theResult____h287214[16] ? - 6'd40 : - (_theResult____h287214[15] ? - 6'd41 : - (_theResult____h287214[14] ? - 6'd42 : - (_theResult____h287214[13] ? - 6'd43 : - (_theResult____h287214[12] ? - 6'd44 : - (_theResult____h287214[11] ? - 6'd45 : - (_theResult____h287214[10] ? - 6'd46 : - (_theResult____h287214[9] ? - 6'd47 : - (_theResult____h287214[8] ? - 6'd48 : - (_theResult____h287214[7] ? - 6'd49 : - (_theResult____h287214[6] ? - 6'd50 : - (_theResult____h287214[5] ? - 6'd51 : - (_theResult____h287214[4] ? - 6'd52 : - (_theResult____h287214[3] ? - 6'd53 : - (_theResult____h287214[2] ? - 6'd54 : - (_theResult____h287214[1] ? - 6'd55 : - (_theResult____h287214[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 = - (din_exp__h130866 == 11'd0) ? - 12'd3074 : - { din_exp30866_MINUS_1023__q23[10], - din_exp30866_MINUS_1023__q23 } ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 = - (sfdBC__h115662[105] ? - 7'd0 : - (sfdBC__h115662[104] ? - 7'd1 : - (sfdBC__h115662[103] ? - 7'd2 : - (sfdBC__h115662[102] ? - 7'd3 : - (sfdBC__h115662[101] ? - 7'd4 : - (sfdBC__h115662[100] ? - 7'd5 : - (sfdBC__h115662[99] ? - 7'd6 : - (sfdBC__h115662[98] ? - 7'd7 : - (sfdBC__h115662[97] ? - 7'd8 : - (sfdBC__h115662[96] ? - 7'd9 : - (sfdBC__h115662[95] ? - 7'd10 : - (sfdBC__h115662[94] ? - 7'd11 : - (sfdBC__h115662[93] ? - 7'd12 : - (sfdBC__h115662[92] ? - 7'd13 : - (sfdBC__h115662[91] ? - 7'd14 : - (sfdBC__h115662[90] ? - 7'd15 : - (sfdBC__h115662[89] ? - 7'd16 : - (sfdBC__h115662[88] ? - 7'd17 : - (sfdBC__h115662[87] ? - 7'd18 : - (sfdBC__h115662[86] ? - 7'd19 : - (sfdBC__h115662[85] ? - 7'd20 : - (sfdBC__h115662[84] ? - 7'd21 : - (sfdBC__h115662[83] ? - 7'd22 : - (sfdBC__h115662[82] ? - 7'd23 : - (sfdBC__h115662[81] ? - 7'd24 : - (sfdBC__h115662[80] ? - 7'd25 : - (sfdBC__h115662[79] ? - 7'd26 : - (sfdBC__h115662[78] ? - 7'd27 : - (sfdBC__h115662[77] ? - 7'd28 : - (sfdBC__h115662[76] ? - 7'd29 : - (sfdBC__h115662[75] ? - 7'd30 : - (sfdBC__h115662[74] ? - 7'd31 : - (sfdBC__h115662[73] ? - 7'd32 : - (sfdBC__h115662[72] ? - 7'd33 : - (sfdBC__h115662[71] ? - 7'd34 : - (sfdBC__h115662[70] ? - 7'd35 : - (sfdBC__h115662[69] ? - 7'd36 : - (sfdBC__h115662[68] ? - 7'd37 : - (sfdBC__h115662[67] ? - 7'd38 : - (sfdBC__h115662[66] ? - 7'd39 : - (sfdBC__h115662[65] ? - 7'd40 : - (sfdBC__h115662[64] ? - 7'd41 : - (sfdBC__h115662[63] ? - 7'd42 : - (sfdBC__h115662[62] ? - 7'd43 : - (sfdBC__h115662[61] ? - 7'd44 : - (sfdBC__h115662[60] ? - 7'd45 : - (sfdBC__h115662[59] ? - 7'd46 : - (sfdBC__h115662[58] ? - 7'd47 : - (sfdBC__h115662[57] ? - 7'd48 : - (sfdBC__h115662[56] ? - 7'd49 : - (sfdBC__h115662[55] ? - 7'd50 : - (sfdBC__h115662[54] ? - 7'd51 : - (sfdBC__h115662[53] ? - 7'd52 : - (sfdBC__h115662[52] ? - 7'd53 : - (sfdBC__h115662[51] ? - 7'd54 : - (sfdBC__h115662[50] ? - 7'd55 : - (sfdBC__h115662[49] ? - 7'd56 : - (sfdBC__h115662[48] ? - 7'd57 : - (sfdBC__h115662[47] ? - 7'd58 : - (sfdBC__h115662[46] ? - 7'd59 : - (sfdBC__h115662[45] ? - 7'd60 : - (sfdBC__h115662[44] ? - 7'd61 : - (sfdBC__h115662[43] ? - 7'd62 : - (sfdBC__h115662[42] ? - 7'd63 : - (sfdBC__h115662[41] ? - 7'd64 : - (sfdBC__h115662[40] ? - 7'd65 : - (sfdBC__h115662[39] ? - 7'd66 : - (sfdBC__h115662[38] ? - 7'd67 : - (sfdBC__h115662[37] ? - 7'd68 : - (sfdBC__h115662[36] ? - 7'd69 : - (sfdBC__h115662[35] ? - 7'd70 : - (sfdBC__h115662[34] ? - 7'd71 : - (sfdBC__h115662[33] ? - 7'd72 : - (sfdBC__h115662[32] ? - 7'd73 : - (sfdBC__h115662[31] ? - 7'd74 : - (sfdBC__h115662[30] ? - 7'd75 : - (sfdBC__h115662[29] ? - 7'd76 : - (sfdBC__h115662[28] ? - 7'd77 : - (sfdBC__h115662[27] ? - 7'd78 : - (sfdBC__h115662[26] ? - 7'd79 : - (sfdBC__h115662[25] ? - 7'd80 : - (sfdBC__h115662[24] ? - 7'd81 : - (sfdBC__h115662[23] ? - 7'd82 : - (sfdBC__h115662[22] ? - 7'd83 : - (sfdBC__h115662[21] ? - 7'd84 : - (sfdBC__h115662[20] ? - 7'd85 : - (sfdBC__h115662[19] ? - 7'd86 : - (sfdBC__h115662[18] ? - 7'd87 : - (sfdBC__h115662[17] ? - 7'd88 : - (sfdBC__h115662[16] ? - 7'd89 : - (sfdBC__h115662[15] ? - 7'd90 : - (sfdBC__h115662[14] ? - 7'd91 : - (sfdBC__h115662[13] ? - 7'd92 : - (sfdBC__h115662[12] ? - 7'd93 : - (sfdBC__h115662[11] ? - 7'd94 : - (sfdBC__h115662[10] ? - 7'd95 : - (sfdBC__h115662[9] ? - 7'd96 : - (sfdBC__h115662[8] ? - 7'd97 : - (sfdBC__h115662[7] ? - 7'd98 : - (sfdBC__h115662[6] ? - 7'd99 : - (sfdBC__h115662[5] ? - 7'd100 : - (sfdBC__h115662[4] ? - 7'd101 : - (sfdBC__h115662[3] ? - 7'd102 : - (sfdBC__h115662[2] ? - 7'd103 : - (sfdBC__h115662[1] ? - 7'd104 : - (sfdBC__h115662[0] ? - 7'd105 : - 7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 = - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 - - 12'd3074 ; - assign IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h130949, sfdin__h130943[105:54] } ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 = - (guard__h269587 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h277686 : - _theResult___exp__h278202 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 = - (guard__h269587 == 2'b0) ? - _theResult___fst_exp__h277686 : - (resWire$wget[68] ? - _theResult___exp__h278202 : - _theResult___fst_exp__h277686) ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 = - (guard__h269587 == 2'b0 || resWire$wget[68]) ? - sfdin__h277680[56:34] : - _theResult___sfd__h278203 ; - assign IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 = - (guard__h269587 == 2'b0) ? - sfdin__h277680[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h278203 : - sfdin__h277680[56:34]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 = - (guard__h164624 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h172852 : - _theResult___exp__h173571 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 = - (guard__h164624 == 2'b0) ? - _theResult___fst_exp__h172852 : - (iFifo$D_OUT[168] ? - _theResult___exp__h173571 : - _theResult___fst_exp__h172852) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 = - (guard__h164624 == 2'b0 || iFifo$D_OUT[168]) ? - sfdin__h172846[56:5] : - _theResult___sfd__h173572 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 = - (guard__h164624 == 2'b0) ? - sfdin__h172846[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h173572 : - sfdin__h172846[56:5]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 = - (guard__h242201 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h250429 : - _theResult___exp__h251148 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 = - (guard__h242201 == 2'b0) ? - _theResult___fst_exp__h250429 : - (iFifo$D_OUT[38] ? - _theResult___exp__h251148 : - _theResult___fst_exp__h250429) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 = - (guard__h242201 == 2'b0 || iFifo$D_OUT[38]) ? - sfdin__h250423[56:5] : - _theResult___sfd__h251149 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 = - (guard__h242201 == 2'b0) ? - sfdin__h250423[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h251149 : - sfdin__h250423[56:5]) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 = - (guard__h203262 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h211490 : - _theResult___exp__h212209 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 = - (guard__h203262 == 2'b0) ? - _theResult___fst_exp__h211490 : - (iFifo$D_OUT[103] ? - _theResult___exp__h212209 : - _theResult___fst_exp__h211490) ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 = - (guard__h203262 == 2'b0 || iFifo$D_OUT[103]) ? - sfdin__h211484[56:5] : - _theResult___sfd__h212210 ; - assign IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 = - (guard__h203262 == 2'b0) ? - sfdin__h211484[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h212210 : - sfdin__h211484[56:5]) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 = - (guard__h287224 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h295452 : - _theResult___exp__h295968 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 = - (guard__h287224 == 2'b0) ? - _theResult___fst_exp__h295452 : - (resWire$wget[68] ? - _theResult___exp__h295968 : - _theResult___fst_exp__h295452) ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 = - (guard__h287224 == 2'b0 || resWire$wget[68]) ? - sfdin__h295446[56:34] : - _theResult___sfd__h295969 ; - assign IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 = - (guard__h287224 == 2'b0) ? - sfdin__h295446[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h295969 : - sfdin__h295446[56:34]) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 = - (guard__h194013 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h201974 : - _theResult___exp__h202619 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 = - (guard__h194013 == 2'b0) ? - _theResult___fst_exp__h201974 : - (iFifo$D_OUT[103] ? - _theResult___exp__h202619 : - _theResult___fst_exp__h201974) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 = - (guard__h212301 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___fst_exp__h220291 : - _theResult___exp__h220961 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 = - (guard__h212301 == 2'b0) ? - _theResult___fst_exp__h220291 : - (iFifo$D_OUT[103] ? - _theResult___exp__h220961 : - _theResult___fst_exp__h220291) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 = - (guard__h194013 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___snd__h201925[56:5] : - _theResult___sfd__h202620 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 = - (guard__h194013 == 2'b0) ? - _theResult___snd__h201925[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h202620 : - _theResult___snd__h201925[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 = - (guard__h212301 == 2'b0 || iFifo$D_OUT[103]) ? - _theResult___snd__h220237[56:5] : - _theResult___sfd__h220962 ; - assign IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 = - (guard__h212301 == 2'b0) ? - _theResult___snd__h220237[56:5] : - (iFifo$D_OUT[103] ? - _theResult___sfd__h220962 : - _theResult___snd__h220237[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 = - (guard__h155375 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h163336 : - _theResult___exp__h163981 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 = - (guard__h155375 == 2'b0) ? - _theResult___fst_exp__h163336 : - (iFifo$D_OUT[168] ? - _theResult___exp__h163981 : - _theResult___fst_exp__h163336) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 = - (guard__h173663 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___fst_exp__h181653 : - _theResult___exp__h182323 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 = - (guard__h173663 == 2'b0) ? - _theResult___fst_exp__h181653 : - (iFifo$D_OUT[168] ? - _theResult___exp__h182323 : - _theResult___fst_exp__h181653) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 = - (guard__h155375 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___snd__h163287[56:5] : - _theResult___sfd__h163982 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 = - (guard__h155375 == 2'b0) ? - _theResult___snd__h163287[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h163982 : - _theResult___snd__h163287[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 = - (guard__h173663 == 2'b0 || iFifo$D_OUT[168]) ? - _theResult___snd__h181599[56:5] : - _theResult___sfd__h182324 ; - assign IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 = - (guard__h173663 == 2'b0) ? - _theResult___snd__h181599[56:5] : - (iFifo$D_OUT[168] ? - _theResult___sfd__h182324 : - _theResult___snd__h181599[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 = - (guard__h232952 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h240913 : - _theResult___exp__h241558 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 = - (guard__h232952 == 2'b0) ? - _theResult___fst_exp__h240913 : - (iFifo$D_OUT[38] ? - _theResult___exp__h241558 : - _theResult___fst_exp__h240913) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 = - (guard__h251240 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___fst_exp__h259230 : - _theResult___exp__h259900 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 = - (guard__h251240 == 2'b0) ? - _theResult___fst_exp__h259230 : - (iFifo$D_OUT[38] ? - _theResult___exp__h259900 : - _theResult___fst_exp__h259230) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 = - (guard__h232952 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___snd__h240864[56:5] : - _theResult___sfd__h241559 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 = - (guard__h232952 == 2'b0) ? - _theResult___snd__h240864[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h241559 : - _theResult___snd__h240864[56:5]) ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 = - (guard__h251240 == 2'b0 || iFifo$D_OUT[38]) ? - _theResult___snd__h259176[56:5] : - _theResult___sfd__h259901 ; - assign IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 = - (guard__h251240 == 2'b0) ? - _theResult___snd__h259176[56:5] : - (iFifo$D_OUT[38] ? - _theResult___sfd__h259901 : - _theResult___snd__h259176[56:5]) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 = - (guard__h278294 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h286342 : - _theResult___exp__h286784 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 = - (guard__h278294 == 2'b0) ? - _theResult___fst_exp__h286342 : - (resWire$wget[68] ? - _theResult___exp__h286784 : - _theResult___fst_exp__h286342) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 = - (guard__h296060 == 2'b0 || resWire$wget[68]) ? - _theResult___fst_exp__h304137 : - _theResult___exp__h304604 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 = - (guard__h296060 == 2'b0) ? - _theResult___fst_exp__h304137 : - (resWire$wget[68] ? - _theResult___exp__h304604 : - _theResult___fst_exp__h304137) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 = - (guard__h278294 == 2'b0 || resWire$wget[68]) ? - _theResult___snd__h286293[56:34] : - _theResult___sfd__h286785 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 = - (guard__h278294 == 2'b0) ? - _theResult___snd__h286293[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h286785 : - _theResult___snd__h286293[56:34]) ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 = - (guard__h296060 == 2'b0 || resWire$wget[68]) ? - _theResult___snd__h304083[56:34] : - _theResult___sfd__h304605 ; - assign IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 = - (guard__h296060 == 2'b0) ? - _theResult___snd__h304083[56:34] : - (resWire$wget[68] ? - _theResult___sfd__h304605 : - _theResult___snd__h304083[56:34]) ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 12'd3074 : - { theResult___fst_exp2290_MINUS_1023__q11[10], - theResult___fst_exp2290_MINUS_1023__q11 } ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 = - (sfdin__h34118[57] ? - 6'd0 : - (sfdin__h34118[56] ? - 6'd1 : - (sfdin__h34118[55] ? - 6'd2 : - (sfdin__h34118[54] ? - 6'd3 : - (sfdin__h34118[53] ? - 6'd4 : - (sfdin__h34118[52] ? - 6'd5 : - (sfdin__h34118[51] ? - 6'd6 : - (sfdin__h34118[50] ? - 6'd7 : - (sfdin__h34118[49] ? - 6'd8 : - (sfdin__h34118[48] ? - 6'd9 : - (sfdin__h34118[47] ? - 6'd10 : - (sfdin__h34118[46] ? - 6'd11 : - (sfdin__h34118[45] ? - 6'd12 : - (sfdin__h34118[44] ? - 6'd13 : - (sfdin__h34118[43] ? - 6'd14 : - (sfdin__h34118[42] ? - 6'd15 : - (sfdin__h34118[41] ? - 6'd16 : - (sfdin__h34118[40] ? - 6'd17 : - (sfdin__h34118[39] ? - 6'd18 : - (sfdin__h34118[38] ? - 6'd19 : - (sfdin__h34118[37] ? - 6'd20 : - (sfdin__h34118[36] ? - 6'd21 : - (sfdin__h34118[35] ? - 6'd22 : - (sfdin__h34118[34] ? - 6'd23 : - (sfdin__h34118[33] ? - 6'd24 : - (sfdin__h34118[32] ? - 6'd25 : - (sfdin__h34118[31] ? - 6'd26 : - (sfdin__h34118[30] ? - 6'd27 : - (sfdin__h34118[29] ? - 6'd28 : - (sfdin__h34118[28] ? - 6'd29 : - (sfdin__h34118[27] ? - 6'd30 : - (sfdin__h34118[26] ? - 6'd31 : - (sfdin__h34118[25] ? - 6'd32 : - (sfdin__h34118[24] ? - 6'd33 : - (sfdin__h34118[23] ? - 6'd34 : - (sfdin__h34118[22] ? - 6'd35 : - (sfdin__h34118[21] ? - 6'd36 : - (sfdin__h34118[20] ? - 6'd37 : - (sfdin__h34118[19] ? - 6'd38 : - (sfdin__h34118[18] ? - 6'd39 : - (sfdin__h34118[17] ? - 6'd40 : - (sfdin__h34118[16] ? - 6'd41 : - (sfdin__h34118[15] ? - 6'd42 : - (sfdin__h34118[14] ? - 6'd43 : - (sfdin__h34118[13] ? - 6'd44 : - (sfdin__h34118[12] ? - 6'd45 : - (sfdin__h34118[11] ? - 6'd46 : - (sfdin__h34118[10] ? - 6'd47 : - (sfdin__h34118[9] ? - 6'd48 : - (sfdin__h34118[8] ? - 6'd49 : - (sfdin__h34118[7] ? - 6'd50 : - (sfdin__h34118[6] ? - 6'd51 : - (sfdin__h34118[5] ? - 6'd52 : - (sfdin__h34118[4] ? - 6'd53 : - (sfdin__h34118[3] ? - 6'd54 : - (sfdin__h34118[2] ? - 6'd55 : - (sfdin__h34118[1] ? - 6'd56 : - (sfdin__h34118[0] ? - 6'd57 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 = - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 - - 12'd3074 ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d926 = - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 ? - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921 : - { fpu_div64_fState_S3$D_OUT[129:128], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[127] : - fpu_div64_fState_S3$D_OUT[127], - fpu_div64_fState_S3$D_OUT[126], - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[125] : - fpu_div64_fState_S3$D_OUT[125] } ; - assign IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h42333, sfdin__h42327[57:6] } ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 == 52'd0) ? - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194] : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ? - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 : - fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194]) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 == 52'd0) ? - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ? - 63'h7FF0000000000000 : - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936 = - (x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51]) ? - { fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 } : - ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118]) ? - fpu_madd_fOperand_S0$D_OUT[130:67] : - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54]) ? - fpu_madd_fOperand_S0$D_OUT[66:3] : - { NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923, - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 })) ; - assign IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1939 = - (x__h96539 == 11'd2047 && - _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51]) ? - { fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194], - x__h96539, - sfd__h99402 } : - IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 ; - assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 = - (sfd__h133119[56] ? - 6'd0 : - (sfd__h133119[55] ? - 6'd1 : - (sfd__h133119[54] ? - 6'd2 : - (sfd__h133119[53] ? - 6'd3 : - (sfd__h133119[52] ? - 6'd4 : - (sfd__h133119[51] ? - 6'd5 : - (sfd__h133119[50] ? - 6'd6 : - (sfd__h133119[49] ? - 6'd7 : - (sfd__h133119[48] ? - 6'd8 : - (sfd__h133119[47] ? - 6'd9 : - (sfd__h133119[46] ? - 6'd10 : - (sfd__h133119[45] ? - 6'd11 : - (sfd__h133119[44] ? - 6'd12 : - (sfd__h133119[43] ? - 6'd13 : - (sfd__h133119[42] ? - 6'd14 : - (sfd__h133119[41] ? - 6'd15 : - (sfd__h133119[40] ? - 6'd16 : - (sfd__h133119[39] ? - 6'd17 : - (sfd__h133119[38] ? - 6'd18 : - (sfd__h133119[37] ? - 6'd19 : - (sfd__h133119[36] ? - 6'd20 : - (sfd__h133119[35] ? - 6'd21 : - (sfd__h133119[34] ? - 6'd22 : - (sfd__h133119[33] ? - 6'd23 : - (sfd__h133119[32] ? - 6'd24 : - (sfd__h133119[31] ? - 6'd25 : - (sfd__h133119[30] ? - 6'd26 : - (sfd__h133119[29] ? - 6'd27 : - (sfd__h133119[28] ? - 6'd28 : - (sfd__h133119[27] ? - 6'd29 : - (sfd__h133119[26] ? - 6'd30 : - (sfd__h133119[25] ? - 6'd31 : - (sfd__h133119[24] ? - 6'd32 : - (sfd__h133119[23] ? - 6'd33 : - (sfd__h133119[22] ? - 6'd34 : - (sfd__h133119[21] ? - 6'd35 : - (sfd__h133119[20] ? - 6'd36 : - (sfd__h133119[19] ? - 6'd37 : - (sfd__h133119[18] ? - 6'd38 : - (sfd__h133119[17] ? - 6'd39 : - (sfd__h133119[16] ? - 6'd40 : - (sfd__h133119[15] ? - 6'd41 : - (sfd__h133119[14] ? - 6'd42 : - (sfd__h133119[13] ? - 6'd43 : - (sfd__h133119[12] ? - 6'd44 : - (sfd__h133119[11] ? - 6'd45 : - (sfd__h133119[10] ? - 6'd46 : - (sfd__h133119[9] ? - 6'd47 : - (sfd__h133119[8] ? - 6'd48 : - (sfd__h133119[7] ? - 6'd49 : - (sfd__h133119[6] ? - 6'd50 : - (sfd__h133119[5] ? - 6'd51 : - (sfd__h133119[4] ? - 6'd52 : - (sfd__h133119[3] ? - 6'd53 : - (sfd__h133119[2] ? - 6'd54 : - (sfd__h133119[1] ? - 6'd55 : - (sfd__h133119[0] ? - 6'd56 : - 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2952 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h141375, sfdin__h141369[56:5] } ; - assign IF_IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_ETC___d75 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - ((IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73) : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 ; - assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503 = - (!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ? - fpu_madd_fState_S3$D_OUT[86] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[4] ; - assign IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506 = - (!fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004) ? - fpu_madd_fState_S3$D_OUT[85] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[3] ; - assign IF_NOT_fpu_madd_fState_S4_first__547_BIT_130_5_ETC___d2595 = - { NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 : - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 - - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 : - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 - - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563, - x__h131940, - x__h131944 } ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 = - ((SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99[10], - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - ((_theResult___fst_exp__h211490 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117) : - ((_theResult___fst_exp__h220291 == 11'd2047) ? - iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119) ; - assign IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - ((_theResult___fst_exp__h211490 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123) : - ((_theResult___fst_exp__h220291 == 11'd2047) ? - !iFifo$D_OUT[103] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125) ; - assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 = - ((SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39[10], - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - ((_theResult___fst_exp__h172852 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57) : - ((_theResult___fst_exp__h181653 == 11'd2047) ? - iFifo$D_OUT[168] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59) ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 = - ((SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] == - 11'd0) ? - 12'd3074 : - { SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66[10], - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 }) - - 12'd3074 ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - ((_theResult___fst_exp__h250429 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84) : - ((_theResult___fst_exp__h259230 == 11'd2047) ? - iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86) ; - assign IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - ((_theResult___fst_exp__h250429 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90) : - ((_theResult___fst_exp__h259230 == 11'd2047) ? - !iFifo$D_OUT[38] : - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 = - ((SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] == - 8'd0) ? - 9'd386 : - { SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141[7], - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 }) - - 9'd386 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - ((_theResult___fst_exp__h295452 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324) : - ((_theResult___fst_exp__h304137 == 8'd255) ? - !resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - ((_theResult___fst_exp__h295452 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409) : - ((_theResult___fst_exp__h304137 == 8'd255) ? - resWire$wget[68] : - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418) ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[2] : - _theResult___fst_exp__h304685 == 8'd255 && - _theResult___fst_sfd__h304686 == 23'd0 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[1] : - _theResult___fst_exp__h304137 == 8'd0 && - guard__h296060 != 2'b0 ; - assign IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[0] : - _theResult___fst_exp__h304137 != 8'd255 && - guard__h296060 != 2'b0 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 = - (((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7[10]}}, - fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7 }) - - { 7'd0, b__h4039 }) - - (((fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8[10]}}, - fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8 }) - - { 7'd0, b__h11457 }) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) <= - 13'd5120 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) < - 13'd3020 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ^ - 13'h1000) < - 13'd3074 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401) ? - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 : - CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0) ? - 11'd2047 : - ((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353) ? - 11'd0 : - _theResult___fst_exp__h19467) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401) ? - 52'd0 : - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ? - _theResult___fst_sfd__h19957 : - _theResult___fst_sfd__h19468) ; - assign IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d455 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54]) ? - { fpu_div64_fOperands_S0$D_OUT[66:55], sfd__h18937 } : - ((fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118]) ? - fpu_div64_fOperands_S0$D_OUT[130:67] : - ((fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54]) ? - fpu_div64_fOperands_S0$D_OUT[66:3] : - NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452)) ; - assign IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - fpu_div64_fState_S3$D_OUT[57:56] == 2'b0 && - !fpu_div64_fState_S3$D_OUT[194] : - !fpu_div64_fState_S3$D_OUT[194] ; - assign IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d921 = - ((fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - { fpu_div64_fState_S3$D_OUT[129:128], - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[127], - fpu_div64_fState_S3$D_OUT[126], - fpu_div64_fState_S3$D_OUT[57:56] != 2'b0 || - fpu_div64_fState_S3$D_OUT[125] } : - fpu_div64_fState_S3$D_OUT[129:125]) | - { 2'd0, - sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023, - _theResult___fst_exp__h42336 == 11'd0 && guard__h33946 != 2'd0, - sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023 } ; - assign IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h42982[53:52] == 2'b01) ? - 11'd1 : - fpu_div64_fState_S4$D_OUT[64:54] ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1932 = - (fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 && - !fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ? - 63'h7FF8000000000000 : - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1931 ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1938 = - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118]) ? - { fpu_madd_fOperand_S0$D_OUT[130:119], sfd__h99405 } : - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54]) ? - { fpu_madd_fOperand_S0$D_OUT[66:55], sfd__h99408 } : - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1936) ; - assign IF_fpu_madd_fOperand_S0_first__803_BITS_129_TO_ETC___d1959 = - { ((fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128[10]}}, - fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 }) + - ((fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129[10]}}, - fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 }), - x__h114243, - x__h114255 } ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1861 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54] || - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 || - fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1911 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[193:131] : - 63'd0 ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 == 52'd0 && - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) ; - assign IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1947 = - x__h96539 == 11'd2047 && _theResult___fst_sfd__h96608 != 52'd0 && - !_theResult___fst_sfd__h96608[51] || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[118] || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0 && - !fpu_madd_fOperand_S0$D_OUT[54] || - NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fProd_S3$D_OUT != 106'd0 || - fpu_madd_fState_S3$D_OUT[83] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[1] ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fProd_S3$D_OUT != 106'd0 || - fpu_madd_fState_S3$D_OUT[82] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[0] ; - assign IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2536 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - (fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - 63'd0 : - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2534) : - 63'h7FEFFFFFFFFFFFFF ; - assign IF_fpu_madd_fState_S3_first__995_BIT_151_996_T_ETC___d2525 = - fpu_madd_fState_S3$D_OUT[151] ? - fpu_madd_fState_S3$D_OUT[86:82] : - { IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2503, - IF_NOT_fpu_madd_fState_S3_first__995_BITS_12_T_ETC___d2506, - NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 } ; - assign IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 = - (fpu_madd_fState_S4$D_OUT[128:118] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27[10]}}, - fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27 } ; - assign IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 = - (fpu_madd_fState_S4$D_OUT[64:54] == 11'd0) ? - 13'd7170 : - { {2{fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26[10]}}, - fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26 } ; - assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 = - (value__h141307[10:0] == 11'd0) ? - 12'd3074 : - { value41307_BITS_10_TO_0_MINUS_1023__q28[10], - value41307_BITS_10_TO_0_MINUS_1023__q28 } ; - assign IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 = - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 - - 12'd3074 ; - assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 = - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd0 && - sfd__h142040[53:52] == 2'b01) ? - 11'd1 : - fpu_madd_fState_S8$D_OUT[65:55] ; - assign IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 = - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[65:55] : - _theResult___fst_exp__h142619 ; - assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060 = - (fpu_madd_fState_S8$D_OUT[67] && - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 == - 11'd0 && - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h142620) == - 52'd0 && - !fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043[0] && - fpu_madd_fState_S8$D_OUT[0]) ? - fpu_madd_fState_S8$D_OUT[70:68] == 3'd3 : - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[66] : - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127) ; - assign IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3081 = - { IF_fpu_madd_fState_S8_first__960_BIT_67_963_AN_ETC___d3060, - (fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[65:3] : - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132, - fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 } ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0) ? - (fpu_sqr64_fOperand_S0$D_OUT[54] ? - 6'd2 : - (fpu_sqr64_fOperand_S0$D_OUT[53] ? - 6'd3 : - (fpu_sqr64_fOperand_S0$D_OUT[52] ? - 6'd4 : - (fpu_sqr64_fOperand_S0$D_OUT[51] ? - 6'd5 : - (fpu_sqr64_fOperand_S0$D_OUT[50] ? - 6'd6 : - (fpu_sqr64_fOperand_S0$D_OUT[49] ? - 6'd7 : - (fpu_sqr64_fOperand_S0$D_OUT[48] ? - 6'd8 : - (fpu_sqr64_fOperand_S0$D_OUT[47] ? - 6'd9 : - (fpu_sqr64_fOperand_S0$D_OUT[46] ? - 6'd10 : - (fpu_sqr64_fOperand_S0$D_OUT[45] ? - 6'd11 : - (fpu_sqr64_fOperand_S0$D_OUT[44] ? - 6'd12 : - (fpu_sqr64_fOperand_S0$D_OUT[43] ? - 6'd13 : - (fpu_sqr64_fOperand_S0$D_OUT[42] ? - 6'd14 : - (fpu_sqr64_fOperand_S0$D_OUT[41] ? - 6'd15 : - (fpu_sqr64_fOperand_S0$D_OUT[40] ? - 6'd16 : - (fpu_sqr64_fOperand_S0$D_OUT[39] ? - 6'd17 : - (fpu_sqr64_fOperand_S0$D_OUT[38] ? - 6'd18 : - (fpu_sqr64_fOperand_S0$D_OUT[37] ? - 6'd19 : - (fpu_sqr64_fOperand_S0$D_OUT[36] ? - 6'd20 : - (fpu_sqr64_fOperand_S0$D_OUT[35] ? - 6'd21 : - (fpu_sqr64_fOperand_S0$D_OUT[34] ? - 6'd22 : - (fpu_sqr64_fOperand_S0$D_OUT[33] ? - 6'd23 : - (fpu_sqr64_fOperand_S0$D_OUT[32] ? - 6'd24 : - (fpu_sqr64_fOperand_S0$D_OUT[31] ? - 6'd25 : - (fpu_sqr64_fOperand_S0$D_OUT[30] ? - 6'd26 : - (fpu_sqr64_fOperand_S0$D_OUT[29] ? - 6'd27 : - (fpu_sqr64_fOperand_S0$D_OUT[28] ? - 6'd28 : - (fpu_sqr64_fOperand_S0$D_OUT[27] ? - 6'd29 : - (fpu_sqr64_fOperand_S0$D_OUT[26] ? - 6'd30 : - (fpu_sqr64_fOperand_S0$D_OUT[25] ? - 6'd31 : - (fpu_sqr64_fOperand_S0$D_OUT[24] ? - 6'd32 : - (fpu_sqr64_fOperand_S0$D_OUT[23] ? - 6'd33 : - (fpu_sqr64_fOperand_S0$D_OUT[22] ? - 6'd34 : - (fpu_sqr64_fOperand_S0$D_OUT[21] ? - 6'd35 : - (fpu_sqr64_fOperand_S0$D_OUT[20] ? - 6'd36 : - (fpu_sqr64_fOperand_S0$D_OUT[19] ? - 6'd37 : - (fpu_sqr64_fOperand_S0$D_OUT[18] ? - 6'd38 : - (fpu_sqr64_fOperand_S0$D_OUT[17] ? - 6'd39 : - (fpu_sqr64_fOperand_S0$D_OUT[16] ? - 6'd40 : - (fpu_sqr64_fOperand_S0$D_OUT[15] ? - 6'd41 : - (fpu_sqr64_fOperand_S0$D_OUT[14] ? - 6'd42 : - (fpu_sqr64_fOperand_S0$D_OUT[13] ? - 6'd43 : - (fpu_sqr64_fOperand_S0$D_OUT[12] ? - 6'd44 : - (fpu_sqr64_fOperand_S0$D_OUT[11] ? - 6'd45 : - (fpu_sqr64_fOperand_S0$D_OUT[10] ? - 6'd46 : - (fpu_sqr64_fOperand_S0$D_OUT[9] ? - 6'd47 : - (fpu_sqr64_fOperand_S0$D_OUT[8] ? - 6'd48 : - (fpu_sqr64_fOperand_S0$D_OUT[7] ? - 6'd49 : - (fpu_sqr64_fOperand_S0$D_OUT[6] ? - 6'd50 : - (fpu_sqr64_fOperand_S0$D_OUT[5] ? - 6'd51 : - (fpu_sqr64_fOperand_S0$D_OUT[4] ? - 6'd52 : - (fpu_sqr64_fOperand_S0$D_OUT[3] ? - 6'd53 : - 6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1 ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195 = - ((fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0) ? - 13'd7170 : - { {2{fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16[10]}}, - fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16 }) - - { 7'd0, - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 } ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1212 = - (fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54] || - fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_sqr64_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_sqr64_fOperand_S0$D_OUT[54:3] == 52'd0 && - !fpu_sqr64_fOperand_S0$D_OUT[66]) ? - { 1'd1, - fpu_sqr64_fOperand_S0$D_OUT[66:3], - 130'h00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } : - (fpu_sqr64_fOperand_S0$D_OUT[66] ? - 195'h5FFE00000000000020AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - { 70'h155555555555555540, - fpu_sqr64_fOperand_S0$D_OUT[2:0], - fpu_sqr64_fOperand_S0$D_OUT[66], - x__h52551[10:0], - fpu_sqr64_fOperand_S0$D_OUT[54:3], - x__h60693 }) ; - assign IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195[12:1] ; - assign IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 = - (fpu_sqr64_fState_S1$D_OUT[57] ? - 7'd0 : - (fpu_sqr64_fState_S1$D_OUT[56] ? - 7'd1 : - (fpu_sqr64_fState_S1$D_OUT[55] ? - 7'd2 : - (fpu_sqr64_fState_S1$D_OUT[54] ? - 7'd3 : - (fpu_sqr64_fState_S1$D_OUT[53] ? - 7'd4 : - (fpu_sqr64_fState_S1$D_OUT[52] ? - 7'd5 : - (fpu_sqr64_fState_S1$D_OUT[51] ? - 7'd6 : - (fpu_sqr64_fState_S1$D_OUT[50] ? - 7'd7 : - (fpu_sqr64_fState_S1$D_OUT[49] ? - 7'd8 : - (fpu_sqr64_fState_S1$D_OUT[48] ? - 7'd9 : - (fpu_sqr64_fState_S1$D_OUT[47] ? - 7'd10 : - (fpu_sqr64_fState_S1$D_OUT[46] ? - 7'd11 : - (fpu_sqr64_fState_S1$D_OUT[45] ? - 7'd12 : - (fpu_sqr64_fState_S1$D_OUT[44] ? - 7'd13 : - (fpu_sqr64_fState_S1$D_OUT[43] ? - 7'd14 : - (fpu_sqr64_fState_S1$D_OUT[42] ? - 7'd15 : - (fpu_sqr64_fState_S1$D_OUT[41] ? - 7'd16 : - (fpu_sqr64_fState_S1$D_OUT[40] ? - 7'd17 : - (fpu_sqr64_fState_S1$D_OUT[39] ? - 7'd18 : - (fpu_sqr64_fState_S1$D_OUT[38] ? - 7'd19 : - (fpu_sqr64_fState_S1$D_OUT[37] ? - 7'd20 : - (fpu_sqr64_fState_S1$D_OUT[36] ? - 7'd21 : - (fpu_sqr64_fState_S1$D_OUT[35] ? - 7'd22 : - (fpu_sqr64_fState_S1$D_OUT[34] ? - 7'd23 : - (fpu_sqr64_fState_S1$D_OUT[33] ? - 7'd24 : - (fpu_sqr64_fState_S1$D_OUT[32] ? - 7'd25 : - (fpu_sqr64_fState_S1$D_OUT[31] ? - 7'd26 : - (fpu_sqr64_fState_S1$D_OUT[30] ? - 7'd27 : - (fpu_sqr64_fState_S1$D_OUT[29] ? - 7'd28 : - (fpu_sqr64_fState_S1$D_OUT[28] ? - 7'd29 : - (fpu_sqr64_fState_S1$D_OUT[27] ? - 7'd30 : - (fpu_sqr64_fState_S1$D_OUT[26] ? - 7'd31 : - (fpu_sqr64_fState_S1$D_OUT[25] ? - 7'd32 : - (fpu_sqr64_fState_S1$D_OUT[24] ? - 7'd33 : - (fpu_sqr64_fState_S1$D_OUT[23] ? - 7'd34 : - (fpu_sqr64_fState_S1$D_OUT[22] ? - 7'd35 : - (fpu_sqr64_fState_S1$D_OUT[21] ? - 7'd36 : - (fpu_sqr64_fState_S1$D_OUT[20] ? - 7'd37 : - (fpu_sqr64_fState_S1$D_OUT[19] ? - 7'd38 : - (fpu_sqr64_fState_S1$D_OUT[18] ? - 7'd39 : - (fpu_sqr64_fState_S1$D_OUT[17] ? - 7'd40 : - (fpu_sqr64_fState_S1$D_OUT[16] ? - 7'd41 : - (fpu_sqr64_fState_S1$D_OUT[15] ? - 7'd42 : - (fpu_sqr64_fState_S1$D_OUT[14] ? - 7'd43 : - (fpu_sqr64_fState_S1$D_OUT[13] ? - 7'd44 : - (fpu_sqr64_fState_S1$D_OUT[12] ? - 7'd45 : - (fpu_sqr64_fState_S1$D_OUT[11] ? - 7'd46 : - (fpu_sqr64_fState_S1$D_OUT[10] ? - 7'd47 : - (fpu_sqr64_fState_S1$D_OUT[9] ? - 7'd48 : - (fpu_sqr64_fState_S1$D_OUT[8] ? - 7'd49 : - (fpu_sqr64_fState_S1$D_OUT[7] ? - 7'd50 : - (fpu_sqr64_fState_S1$D_OUT[6] ? - 7'd51 : - (fpu_sqr64_fState_S1$D_OUT[5] ? - 7'd52 : - (fpu_sqr64_fState_S1$D_OUT[4] ? - 7'd53 : - (fpu_sqr64_fState_S1$D_OUT[3] ? - 7'd54 : - (fpu_sqr64_fState_S1$D_OUT[2] ? - 7'd55 : - (fpu_sqr64_fState_S1$D_OUT[1] ? - 7'd56 : - (fpu_sqr64_fState_S1$D_OUT[0] ? - 7'd57 : - 7'd116)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 7'd1 ; - assign IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 12'd3074 : - { fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18[10], - fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18 } ; - assign IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 = - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 - - 12'd3074 ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_195_376__ETC___d1671 = - fpu_sqr64_fState_S3$D_OUT[195] ? - fpu_sqr64_fState_S3$D_OUT[128:126] : - { fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023, - _theResult___fst_exp__h94753 == 11'd0 && - guard__h86435 != 2'd0, - fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023 } ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_A_ETC___d1678 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 63'h7FEFFFFFFFFFFFFF : - { _theResult___fst_exp__h94750, sfdin__h94744[58:7] } ; - assign IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 = - (fpu_sqr64_fState_S3$D_OUT[58] ? - 6'd0 : - (fpu_sqr64_fState_S3$D_OUT[57] ? - 6'd1 : - (fpu_sqr64_fState_S3$D_OUT[56] ? - 6'd2 : - (fpu_sqr64_fState_S3$D_OUT[55] ? - 6'd3 : - (fpu_sqr64_fState_S3$D_OUT[54] ? - 6'd4 : - (fpu_sqr64_fState_S3$D_OUT[53] ? - 6'd5 : - (fpu_sqr64_fState_S3$D_OUT[52] ? - 6'd6 : - (fpu_sqr64_fState_S3$D_OUT[51] ? - 6'd7 : - (fpu_sqr64_fState_S3$D_OUT[50] ? - 6'd8 : - (fpu_sqr64_fState_S3$D_OUT[49] ? - 6'd9 : - (fpu_sqr64_fState_S3$D_OUT[48] ? - 6'd10 : - (fpu_sqr64_fState_S3$D_OUT[47] ? - 6'd11 : - (fpu_sqr64_fState_S3$D_OUT[46] ? - 6'd12 : - (fpu_sqr64_fState_S3$D_OUT[45] ? - 6'd13 : - (fpu_sqr64_fState_S3$D_OUT[44] ? - 6'd14 : - (fpu_sqr64_fState_S3$D_OUT[43] ? - 6'd15 : - (fpu_sqr64_fState_S3$D_OUT[42] ? - 6'd16 : - (fpu_sqr64_fState_S3$D_OUT[41] ? - 6'd17 : - (fpu_sqr64_fState_S3$D_OUT[40] ? - 6'd18 : - (fpu_sqr64_fState_S3$D_OUT[39] ? - 6'd19 : - (fpu_sqr64_fState_S3$D_OUT[38] ? - 6'd20 : - (fpu_sqr64_fState_S3$D_OUT[37] ? - 6'd21 : - (fpu_sqr64_fState_S3$D_OUT[36] ? - 6'd22 : - (fpu_sqr64_fState_S3$D_OUT[35] ? - 6'd23 : - (fpu_sqr64_fState_S3$D_OUT[34] ? - 6'd24 : - (fpu_sqr64_fState_S3$D_OUT[33] ? - 6'd25 : - (fpu_sqr64_fState_S3$D_OUT[32] ? - 6'd26 : - (fpu_sqr64_fState_S3$D_OUT[31] ? - 6'd27 : - (fpu_sqr64_fState_S3$D_OUT[30] ? - 6'd28 : - (fpu_sqr64_fState_S3$D_OUT[29] ? - 6'd29 : - (fpu_sqr64_fState_S3$D_OUT[28] ? - 6'd30 : - (fpu_sqr64_fState_S3$D_OUT[27] ? - 6'd31 : - (fpu_sqr64_fState_S3$D_OUT[26] ? - 6'd32 : - (fpu_sqr64_fState_S3$D_OUT[25] ? - 6'd33 : - (fpu_sqr64_fState_S3$D_OUT[24] ? - 6'd34 : - (fpu_sqr64_fState_S3$D_OUT[23] ? - 6'd35 : - (fpu_sqr64_fState_S3$D_OUT[22] ? - 6'd36 : - (fpu_sqr64_fState_S3$D_OUT[21] ? - 6'd37 : - (fpu_sqr64_fState_S3$D_OUT[20] ? - 6'd38 : - (fpu_sqr64_fState_S3$D_OUT[19] ? - 6'd39 : - (fpu_sqr64_fState_S3$D_OUT[18] ? - 6'd40 : - (fpu_sqr64_fState_S3$D_OUT[17] ? - 6'd41 : - (fpu_sqr64_fState_S3$D_OUT[16] ? - 6'd42 : - (fpu_sqr64_fState_S3$D_OUT[15] ? - 6'd43 : - (fpu_sqr64_fState_S3$D_OUT[14] ? - 6'd44 : - (fpu_sqr64_fState_S3$D_OUT[13] ? - 6'd45 : - (fpu_sqr64_fState_S3$D_OUT[12] ? - 6'd46 : - (fpu_sqr64_fState_S3$D_OUT[11] ? - 6'd47 : - (fpu_sqr64_fState_S3$D_OUT[10] ? - 6'd48 : - (fpu_sqr64_fState_S3$D_OUT[9] ? - 6'd49 : - (fpu_sqr64_fState_S3$D_OUT[8] ? - 6'd50 : - (fpu_sqr64_fState_S3$D_OUT[7] ? - 6'd51 : - (fpu_sqr64_fState_S3$D_OUT[6] ? - 6'd52 : - (fpu_sqr64_fState_S3$D_OUT[5] ? - 6'd53 : - (fpu_sqr64_fState_S3$D_OUT[4] ? - 6'd54 : - (fpu_sqr64_fState_S3$D_OUT[3] ? - 6'd55 : - (fpu_sqr64_fState_S3$D_OUT[2] ? - 6'd56 : - (fpu_sqr64_fState_S3$D_OUT[1] ? - 6'd57 : - (fpu_sqr64_fState_S3$D_OUT[0] ? - 6'd58 : - 6'd59))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - - 6'd1 ; - assign IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd0 && - sfd__h95416[53:52] == 2'b01) ? - 11'd1 : - fpu_sqr64_fState_S4$D_OUT[64:54] ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 = - ((iFifo$D_OUT[102:95] == 8'd0) ? - (iFifo$D_OUT[94] ? - 6'd2 : - (iFifo$D_OUT[93] ? - 6'd3 : - (iFifo$D_OUT[92] ? - 6'd4 : - (iFifo$D_OUT[91] ? - 6'd5 : - (iFifo$D_OUT[90] ? - 6'd6 : - (iFifo$D_OUT[89] ? - 6'd7 : - (iFifo$D_OUT[88] ? - 6'd8 : - (iFifo$D_OUT[87] ? - 6'd9 : - (iFifo$D_OUT[86] ? - 6'd10 : - (iFifo$D_OUT[85] ? - 6'd11 : - (iFifo$D_OUT[84] ? - 6'd12 : - (iFifo$D_OUT[83] ? - 6'd13 : - (iFifo$D_OUT[82] ? - 6'd14 : - (iFifo$D_OUT[81] ? - 6'd15 : - (iFifo$D_OUT[80] ? - 6'd16 : - (iFifo$D_OUT[79] ? - 6'd17 : - (iFifo$D_OUT[78] ? - 6'd18 : - (iFifo$D_OUT[77] ? - 6'd19 : - (iFifo$D_OUT[76] ? - 6'd20 : - (iFifo$D_OUT[75] ? - 6'd21 : - (iFifo$D_OUT[74] ? - 6'd22 : - (iFifo$D_OUT[73] ? - 6'd23 : - (iFifo$D_OUT[72] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4802 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5146 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803) ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d5347 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5374 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348) ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 = - { (iFifo$D_OUT[102:95] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h221054, - (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0) ? - _theResult___snd_fst_sfd__h183126 : - _theResult___fst_sfd__h221058 } ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 = - { (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0 || - (iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - iFifo$D_OUT[103] : - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5148, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ; - assign IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 = - { (iFifo$D_OUT[102:95] == 8'd255 && - iFifo$D_OUT[94:72] != 23'd0 || - (iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - !iFifo$D_OUT[103] : - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d5376, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5327 } ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 = - ((iFifo$D_OUT[167:160] == 8'd0) ? - (iFifo$D_OUT[159] ? - 6'd2 : - (iFifo$D_OUT[158] ? - 6'd3 : - (iFifo$D_OUT[157] ? - 6'd4 : - (iFifo$D_OUT[156] ? - 6'd5 : - (iFifo$D_OUT[155] ? - 6'd6 : - (iFifo$D_OUT[154] ? - 6'd7 : - (iFifo$D_OUT[153] ? - 6'd8 : - (iFifo$D_OUT[152] ? - 6'd9 : - (iFifo$D_OUT[151] ? - 6'd10 : - (iFifo$D_OUT[150] ? - 6'd11 : - (iFifo$D_OUT[149] ? - 6'd12 : - (iFifo$D_OUT[148] ? - 6'd13 : - (iFifo$D_OUT[147] ? - 6'd14 : - (iFifo$D_OUT[146] ? - 6'd15 : - (iFifo$D_OUT[145] ? - 6'd16 : - (iFifo$D_OUT[144] ? - 6'd17 : - (iFifo$D_OUT[143] ? - 6'd18 : - (iFifo$D_OUT[142] ? - 6'd19 : - (iFifo$D_OUT[141] ? - 6'd20 : - (iFifo$D_OUT[140] ? - 6'd21 : - (iFifo$D_OUT[139] ? - 6'd22 : - (iFifo$D_OUT[138] ? - 6'd23 : - (iFifo$D_OUT[137] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d3317 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3663 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320) ; - assign IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 = - { (iFifo$D_OUT[167:160] == 8'd255 && - iFifo$D_OUT[159:137] != 23'd0 || - (iFifo$D_OUT[167:160] == 8'd255 || - iFifo$D_OUT[167:160] == 8'd0) && - iFifo$D_OUT[159:137] == 23'd0) ? - iFifo$D_OUT[168] : - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3665, - (iFifo$D_OUT[167:160] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h182416, - (iFifo$D_OUT[167:160] == 8'd255 && - iFifo$D_OUT[159:137] != 23'd0) ? - _theResult___snd_fst_sfd__h144486 : - _theResult___fst_sfd__h182420 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 = - ((iFifo$D_OUT[37:30] == 8'd0) ? - (iFifo$D_OUT[29] ? - 6'd2 : - (iFifo$D_OUT[28] ? - 6'd3 : - (iFifo$D_OUT[27] ? - 6'd4 : - (iFifo$D_OUT[26] ? - 6'd5 : - (iFifo$D_OUT[25] ? - 6'd6 : - (iFifo$D_OUT[24] ? - 6'd7 : - (iFifo$D_OUT[23] ? - 6'd8 : - (iFifo$D_OUT[22] ? - 6'd9 : - (iFifo$D_OUT[21] ? - 6'd10 : - (iFifo$D_OUT[20] ? - 6'd11 : - (iFifo$D_OUT[19] ? - 6'd12 : - (iFifo$D_OUT[18] ? - 6'd13 : - (iFifo$D_OUT[17] ? - 6'd14 : - (iFifo$D_OUT[16] ? - 6'd15 : - (iFifo$D_OUT[15] ? - 6'd16 : - (iFifo$D_OUT[14] ? - 6'd17 : - (iFifo$D_OUT[13] ? - 6'd18 : - (iFifo$D_OUT[12] ? - 6'd19 : - (iFifo$D_OUT[11] ? - 6'd20 : - (iFifo$D_OUT[10] ? - 6'd21 : - (iFifo$D_OUT[9] ? - 6'd22 : - (iFifo$D_OUT[8] ? - 6'd23 : - (iFifo$D_OUT[7] ? - 6'd24 : - 6'd57))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4027 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4371 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028) ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - IF_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_ETC___d4581 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4608 : - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582) ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 = - { (iFifo$D_OUT[37:30] == 8'd255) ? - 11'd2047 : - _theResult___fst_exp__h259993, - (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0) ? - _theResult___snd_fst_sfd__h222065 : - _theResult___fst_sfd__h259997 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 = - { (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 || - (iFifo$D_OUT[37:30] == 8'd255 || - iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - iFifo$D_OUT[38] : - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4373, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ; - assign IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 = - { (iFifo$D_OUT[37:30] == 8'd255 && iFifo$D_OUT[29:7] != 23'd0 || - (iFifo$D_OUT[37:30] == 8'd255 || - iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - !iFifo$D_OUT[38] : - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d4610, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4552 } ; - assign IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 = - iFifo$D_OUT[136] ? - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5328 : - iFifo$D_OUT[135:72] ; - assign IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 = - iFifo$D_OUT[201] ? - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_255_ETC___d3846 : - iFifo$D_OUT[200:137] ; - assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555 = - iFifo$D_OUT[71] ? - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4553 : - iFifo$D_OUT[70:7] ; - assign IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 = - iFifo$D_OUT[71] ? - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_255_8_ETC___d4612 : - { iFifo$D_OUT[71] || !iFifo$D_OUT[70], iFifo$D_OUT[69:7] } ; - assign IF_isDoubleFifo_first__407_THEN_IF_isNegateFif_ETC___d6657 = - isDoubleFifo$D_OUT ? - { isNegateFifo$D_OUT ^ resWire$wget[68], resWire$wget[67:5] } : - { 32'hAAAAAAAA, - IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424, - exp__h304706, - sfd__h304707 } ; - assign IF_isNegateFifo_first__409_THEN_IF_resWire_wge_ETC___d6424 = - isNegateFifo$D_OUT ? - ((resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0 || - (resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - !resWire$wget[68] : - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377) : - ((resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0 || - (resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - resWire$wget[68] : - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 = - ((resWire$wget[67:57] == 11'd0) ? - (resWire$wget[56] ? - 6'd2 : - (resWire$wget[55] ? - 6'd3 : - (resWire$wget[54] ? - 6'd4 : - (resWire$wget[53] ? - 6'd5 : - (resWire$wget[52] ? - 6'd6 : - (resWire$wget[51] ? - 6'd7 : - (resWire$wget[50] ? - 6'd8 : - (resWire$wget[49] ? - 6'd9 : - (resWire$wget[48] ? - 6'd10 : - (resWire$wget[47] ? - 6'd11 : - (resWire$wget[46] ? - 6'd12 : - (resWire$wget[45] ? - 6'd13 : - (resWire$wget[44] ? - 6'd14 : - (resWire$wget[43] ? - 6'd15 : - (resWire$wget[42] ? - 6'd16 : - (resWire$wget[41] ? - 6'd17 : - (resWire$wget[40] ? - 6'd18 : - (resWire$wget[39] ? - 6'd19 : - (resWire$wget[38] ? - 6'd20 : - (resWire$wget[37] ? - 6'd21 : - (resWire$wget[36] ? - 6'd22 : - (resWire$wget[35] ? - 6'd23 : - (resWire$wget[34] ? - 6'd24 : - (resWire$wget[33] ? - 6'd25 : - (resWire$wget[32] ? - 6'd26 : - (resWire$wget[31] ? - 6'd27 : - (resWire$wget[30] ? - 6'd28 : - (resWire$wget[29] ? - 6'd29 : - (resWire$wget[28] ? - 6'd30 : - (resWire$wget[27] ? - 6'd31 : - (resWire$wget[26] ? - 6'd32 : - (resWire$wget[25] ? - 6'd33 : - (resWire$wget[24] ? - 6'd34 : - (resWire$wget[23] ? - 6'd35 : - (resWire$wget[22] ? - 6'd36 : - (resWire$wget[21] ? - 6'd37 : - (resWire$wget[20] ? - 6'd38 : - (resWire$wget[19] ? - 6'd39 : - (resWire$wget[18] ? - 6'd40 : - (resWire$wget[17] ? - 6'd41 : - (resWire$wget[16] ? - 6'd42 : - (resWire$wget[15] ? - 6'd43 : - (resWire$wget[14] ? - 6'd44 : - (resWire$wget[13] ? - 6'd45 : - (resWire$wget[12] ? - 6'd46 : - (resWire$wget[11] ? - 6'd47 : - (resWire$wget[10] ? - 6'd48 : - (resWire$wget[9] ? - 6'd49 : - (resWire$wget[8] ? - 6'd50 : - (resWire$wget[7] ? - 6'd51 : - (resWire$wget[6] ? - 6'd52 : - (resWire$wget[5] ? - 6'd53 : - 6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd1) - - 6'd1 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6377 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6025 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6375 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6422 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - IF_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BI_ETC___d6399 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6420 : - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400) ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[4] ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 && - _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705[3] ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736 = - (resWire$wget[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 : - !SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 || - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6734 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749 = - (resWire$wget[67:57] == 11'd0) ? - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 && - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6747 ; - assign IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 = - (resWire$wget[67:57] == 11'd0) ? - NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 : - !SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 || - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6760 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 = - rg_index_1_4_ULE_58___d38 ? _theResult___fst__h1515 : rg_b ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 = - rg_index_1_4_ULE_58___d38 ? - _theResult___snd_snd_snd__h1520 : - rg_r_1 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d73 = - rg_index_1_4_ULE_58___d38 ? - IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72 : - rg_res[115:0] ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 = - rg_index_1_4_ULE_58___d38 ? _theResult___snd_fst__h1517 : rg_s ; - assign IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 < - sum__h1710 ; - assign IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 = - rg_index_1_4_ULE_58___d38 ? - rg_b != 116'd0 && !rg_res[116] : - !rg_res[116] ; - assign IF_rg_index_1_4_ULE_58_8_THEN_rg_b_9_EQ_0_0_OR_ETC___d44 = - rg_index_1_4_ULE_58___d38 ? - rg_b == 116'd0 || rg_res[116] : - rg_res[116] ; - assign IF_rg_index_ULE_57_THEN_IF_rg_r_0_BIT_115_1_TH_ETC___d22 = - rg_index_ULE_57___d7 ? - (rg_r[115] ? - { rg_r[114:0], 1'd0 } + b__h32583 : - { rg_r[114:0], 1'd0 } - b__h32583) : - rg_r ; - assign IF_rg_index_ULE_57_THEN_rg_q_BITS_56_TO_0_CONC_ETC___d14 = - rg_index_ULE_57___d7 ? { rg_q[56:0], !rg_r[115] } : rg_q ; - assign IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10 = - rg_r[115] ? - rg_q_PLUS_NEG_INV_rg_q_59_60___d561 - 58'd1 : - rg_q_PLUS_NEG_INV_rg_q_59_60___d561 ; - assign IF_rg_res_1_BIT_116_2_THEN_rg_res_1_BITS_115_T_ETC___d72 = - rg_res[116] ? - rg_res[115:0] : - ((rg_b == 116'd0) ? rg_r_1 : rg_res[115:0]) ; - assign IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98 = - sfdin__h211484[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13 = - sfdin__h42327[5] ? 2'd2 : 2'd0 ; - assign IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25 = - sfdin__h130943[53] ? 2'd2 : 2'd0 ; - assign IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30 = - sfdin__h141369[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20 = - sfdin__h94744[6] ? 2'd2 : 2'd0 ; - assign IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65 = - sfdin__h250423[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38 = - sfdin__h172846[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134 = - sfdin__h277680[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140 = - sfdin__h295446[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94 = - _theResult___snd__h201925[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143 = - _theResult___snd__h304083[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101 = - _theResult___snd__h220237[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61 = - _theResult___snd__h240864[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68 = - _theResult___snd__h259176[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34 = - _theResult___snd__h163287[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41 = - _theResult___snd__h181599[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136 = - _theResult___snd__h286293[33] ? 2'd2 : 2'd0 ; - assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6728 = - !_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 || - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[2] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[2]) ; - assign NOT_3074_MINUS_0_CONCAT_IF_resWire_wget__410_B_ETC___d6756 = - !_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 || - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[0] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[0]) ; - assign NOT_IF_fpu_madd_fOperand_S0_first__803_BIT_195_ETC___d1946 = - (x__h96539 != 11'd2047 || !_theResult___fst_sfd__h96608[51]) && - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - !fpu_madd_fOperand_S0$D_OUT[118]) && - (fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - !fpu_madd_fOperand_S0$D_OUT[54]) && - (fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 || - IF_fpu_madd_fOperand_S0_first__803_BIT_195_804_ETC___d1927 && - !fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 = - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d452 = - { NOT_fpu_div64_fOperands_S0_first__06_BITS_129__ETC___d400 && - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d422, - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d433, - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436 ? - 52'h8000000000000 : - IF_fpu_div64_fOperands_S0_first__06_BITS_65_TO_ETC___d450 } ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d481 = - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 && - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ; - assign NOT_fpu_div64_fOperands_S0_first__06_BITS_65_T_ETC___d488 = - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0 || - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0) && - (fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd2047 || - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0) && - (!IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355) ; - assign NOT_fpu_madd_fOperand_S0_first__803_BITS_129_T_ETC___d1923 = - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) && - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) && - (x__h96539 != 11'd2047 || - _theResult___fst_sfd__h96608 != 52'd0 || - (fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[118:67] != 52'd0) && - (fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd2047 || - fpu_madd_fOperand_S0$D_OUT[54:3] != 52'd0) || - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855) && - IF_IF_fpu_madd_fOperand_S0_first__803_BIT_195__ETC___d1922 ; - assign NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 = - fpu_madd_fOperand_S0$D_OUT[130] != - fpu_madd_fOperand_S0$D_OUT[66] ; - assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510 = - !fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - (fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - fpu_madd_fState_S3$D_OUT[84] : - fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501[2]) ; - assign NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2523 = - { NOT_fpu_madd_fState_S3_first__995_BITS_12_TO_0_ETC___d2510, - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2516 : - fpu_madd_fState_S3$D_OUT[83], - !fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 || - IF_fpu_madd_fState_S3_first__995_BITS_12_TO_0__ETC___d2521 } ; - assign NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 = - !fpu_madd_fState_S4$D_OUT[130] || - (IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 ^ - 13'h1000) > - (IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 ^ - 13'h1000) || - IF_fpu_madd_fState_S4_first__547_BITS_64_TO_54_ETC___d2563 == - IF_fpu_madd_fState_S4_first__547_BITS_128_TO_1_ETC___d2568 && - sfdBC__h131578 > sfdA__h131577 ; - assign NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 = - !iFifo$D_OUT[158] && !iFifo$D_OUT[157] && !iFifo$D_OUT[156] && - !iFifo$D_OUT[155] && - !iFifo$D_OUT[154] && - !iFifo$D_OUT[153] && - !iFifo$D_OUT[152] && - !iFifo$D_OUT[151] && - !iFifo$D_OUT[150] && - !iFifo$D_OUT[149] && - !iFifo$D_OUT[148] && - !iFifo$D_OUT[147] && - !iFifo$D_OUT[146] && - !iFifo$D_OUT[145] && - !iFifo$D_OUT[144] && - !iFifo$D_OUT[143] && - !iFifo$D_OUT[142] && - !iFifo$D_OUT[141] && - !iFifo$D_OUT[140] && - !iFifo$D_OUT[139] && - !iFifo$D_OUT[138] && - !iFifo$D_OUT[137] ; - assign NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 = - !iFifo$D_OUT[28] && !iFifo$D_OUT[27] && !iFifo$D_OUT[26] && - !iFifo$D_OUT[25] && - !iFifo$D_OUT[24] && - !iFifo$D_OUT[23] && - !iFifo$D_OUT[22] && - !iFifo$D_OUT[21] && - !iFifo$D_OUT[20] && - !iFifo$D_OUT[19] && - !iFifo$D_OUT[18] && - !iFifo$D_OUT[17] && - !iFifo$D_OUT[16] && - !iFifo$D_OUT[15] && - !iFifo$D_OUT[14] && - !iFifo$D_OUT[13] && - !iFifo$D_OUT[12] && - !iFifo$D_OUT[11] && - !iFifo$D_OUT[10] && - !iFifo$D_OUT[9] && - !iFifo$D_OUT[8] && - !iFifo$D_OUT[7] ; - assign NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 = - !iFifo$D_OUT[93] && !iFifo$D_OUT[92] && !iFifo$D_OUT[91] && - !iFifo$D_OUT[90] && - !iFifo$D_OUT[89] && - !iFifo$D_OUT[88] && - !iFifo$D_OUT[87] && - !iFifo$D_OUT[86] && - !iFifo$D_OUT[85] && - !iFifo$D_OUT[84] && - !iFifo$D_OUT[83] && - !iFifo$D_OUT[82] && - !iFifo$D_OUT[81] && - !iFifo$D_OUT[80] && - !iFifo$D_OUT[79] && - !iFifo$D_OUT[78] && - !iFifo$D_OUT[77] && - !iFifo$D_OUT[76] && - !iFifo$D_OUT[75] && - !iFifo$D_OUT[74] && - !iFifo$D_OUT[73] && - !iFifo$D_OUT[72] ; - assign NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 = - !resWire$wget[56] && !resWire$wget[55] && !resWire$wget[54] && - !resWire$wget[53] && - !resWire$wget[52] && - !resWire$wget[51] && - !resWire$wget[50] && - !resWire$wget[49] && - !resWire$wget[48] && - !resWire$wget[47] && - !resWire$wget[46] && - !resWire$wget[45] && - !resWire$wget[44] && - !resWire$wget[43] && - !resWire$wget[42] && - !resWire$wget[41] && - !resWire$wget[40] && - !resWire$wget[39] && - !resWire$wget[38] && - !resWire$wget[37] && - !resWire$wget[36] && - !resWire$wget[35] && - !resWire$wget[34] && - !resWire$wget[33] && - !resWire$wget[32] && - !resWire$wget[31] && - !resWire$wget[30] && - !resWire$wget[29] && - !resWire$wget[28] && - !resWire$wget[27] && - !resWire$wget[26] && - !resWire$wget[25] && - !resWire$wget[24] && - !resWire$wget[23] && - !resWire$wget[22] && - !resWire$wget[21] && - !resWire$wget[20] && - !resWire$wget[19] && - !resWire$wget[18] && - !resWire$wget[17] && - !resWire$wget[16] && - !resWire$wget[15] && - !resWire$wget[14] && - !resWire$wget[13] && - !resWire$wget[12] && - !resWire$wget[11] && - !resWire$wget[10] && - !resWire$wget[9] && - !resWire$wget[8] && - !resWire$wget[7] && - !resWire$wget[6] && - !resWire$wget[5] ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 = - { {4{iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95[7]}}, - iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 } ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q99 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] - - 11'd1023 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 = - { {4{iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35[7]}}, - iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 } ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q39 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] - - 11'd1023 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 = - { {4{iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62[7]}}, - iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 } ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^ - 12'h800) <= - 12'd3071 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ^ - 12'h800) < - 12'd1026 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 + - 12'd1023 ; - assign SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q66 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] - - 11'd1023 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 = - { resWirewget_BITS_67_TO_57_MINUS_1023__q137[10], - resWirewget_BITS_67_TO_57_MINUS_1023__q137 } ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^ - 12'h800) <= - 12'd2175 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ^ - 12'h800) < - 12'd1922 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 + - 12'd127 ; - assign SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q141 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] - - 8'd127 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769 = - ({ 3'd0, - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676 = - { 3'd0, - _theResult___fst_exp__h277686 == 8'd0 && - (sfdin__h277680[56:34] == 23'd0 || guard__h269587 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h278283 == 8'd255 && - _theResult___fst_sfd__h278284 == 23'd0, - 1'd0, - _theResult___fst_exp__h277686 != 8'd255 && - guard__h269587 != 2'b0 } ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057 = - ({ 6'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ^ - 12'h800) <= - 12'd2048 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280 = - ({ 3'd0, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ^ - 9'h100) <= - 9'd256 ; - assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6705 = - { 3'd0, - _theResult___fst_exp__h295452 == 8'd0 && - (sfdin__h295446[56:34] == 23'd0 || guard__h287224 != 2'b0), - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h296049 == 8'd255 && - _theResult___fst_sfd__h296050 == 23'd0, - 1'd0, - _theResult___fst_exp__h295452 != 8'd255 && - guard__h287224 != 2'b0 } ; - assign _0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463 = - ({ 5'd0, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ^ - 12'h800) <= - (IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883 = - ({ 6'd0, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 } ^ - 12'h800) <= - (IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 ^ - 12'h800) ; - assign _0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904 = - ({ 6'd0, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ^ - 12'h800) <= - (IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ^ - 12'h800) ; - assign _0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633 = - ({ 6'd0, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 } ^ - 12'h800) <= - (IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759 = - ({ 6'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107 = - ({ 6'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273 = - ({ 6'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624 = - ({ 6'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ^ - 12'h800) ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984 = - ({ 6'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^ - 12'h800) <= - 12'd2944 ; - assign _0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332 = - ({ 6'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ^ - 12'h800) <= - (IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ^ - 12'h800) ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984 = - ({ 3'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^ - 9'h100) <= - 9'd384 ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333 = - ({ 3'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ^ - 9'h100) <= - (IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ^ - 9'h100) ; - assign _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688 = - { 3'd0, - _theResult___fst_exp__h286342 == 8'd0 && - guard__h278294 != 2'b0, - 1'd0 } | - { 2'd0, - _theResult___fst_exp__h286865 == 8'd255 && - _theResult___fst_sfd__h286866 == 23'd0, - 1'd0, - _theResult___fst_exp__h286342 != 8'd255 && - guard__h278294 != 2'b0 } ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813 = - sfd__h183176 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330 = - sfd__h144536 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ; - assign _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038 = - sfd__h222115 >> - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ; - assign _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038 = - sfd__h261975 >> - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 = - 12'd3074 - - { 6'd0, - resWire$wget[56] ? - 6'd0 : - (resWire$wget[55] ? - 6'd1 : - (resWire$wget[54] ? - 6'd2 : - (resWire$wget[53] ? - 6'd3 : - (resWire$wget[52] ? - 6'd4 : - (resWire$wget[51] ? - 6'd5 : - (resWire$wget[50] ? - 6'd6 : - (resWire$wget[49] ? - 6'd7 : - (resWire$wget[48] ? - 6'd8 : - (resWire$wget[47] ? - 6'd9 : - (resWire$wget[46] ? - 6'd10 : - (resWire$wget[45] ? - 6'd11 : - (resWire$wget[44] ? - 6'd12 : - (resWire$wget[43] ? - 6'd13 : - (resWire$wget[42] ? - 6'd14 : - (resWire$wget[41] ? - 6'd15 : - (resWire$wget[40] ? - 6'd16 : - (resWire$wget[39] ? - 6'd17 : - (resWire$wget[38] ? - 6'd18 : - (resWire$wget[37] ? - 6'd19 : - (resWire$wget[36] ? - 6'd20 : - (resWire$wget[35] ? - 6'd21 : - (resWire$wget[34] ? - 6'd22 : - (resWire$wget[33] ? - 6'd23 : - (resWire$wget[32] ? - 6'd24 : - (resWire$wget[31] ? - 6'd25 : - (resWire$wget[30] ? - 6'd26 : - (resWire$wget[29] ? - 6'd27 : - (resWire$wget[28] ? - 6'd28 : - (resWire$wget[27] ? - 6'd29 : - (resWire$wget[26] ? - 6'd30 : - (resWire$wget[25] ? - 6'd31 : - (resWire$wget[24] ? - 6'd32 : - (resWire$wget[23] ? - 6'd33 : - (resWire$wget[22] ? - 6'd34 : - (resWire$wget[21] ? - 6'd35 : - (resWire$wget[20] ? - 6'd36 : - (resWire$wget[19] ? - 6'd37 : - (resWire$wget[18] ? - 6'd38 : - (resWire$wget[17] ? - 6'd39 : - (resWire$wget[16] ? - 6'd40 : - (resWire$wget[15] ? - 6'd41 : - (resWire$wget[14] ? - 6'd42 : - (resWire$wget[13] ? - 6'd43 : - (resWire$wget[12] ? - 6'd44 : - (resWire$wget[11] ? - 6'd45 : - (resWire$wget[10] ? - 6'd46 : - (resWire$wget[9] ? - 6'd47 : - (resWire$wget[8] ? - 6'd48 : - (resWire$wget[7] ? - 6'd49 : - (resWire$wget[6] ? - 6'd50 : - (resWire$wget[5] ? - 6'd51 : - 6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 = - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^ - 12'h800) <= - 12'd2175 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 = - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5531 ^ - 12'h800) < - 12'd1922 ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6691 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[4] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[4]) ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6716 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[3] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[3]) ; - assign _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d6743 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 && - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d6676[1] : - _0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6688[1]) ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4806 ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3323 ; - assign _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 = - 12'd3074 - - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4031 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[159] ? - 5'd0 : - (iFifo$D_OUT[158] ? - 5'd1 : - (iFifo$D_OUT[157] ? - 5'd2 : - (iFifo$D_OUT[156] ? - 5'd3 : - (iFifo$D_OUT[155] ? - 5'd4 : - (iFifo$D_OUT[154] ? - 5'd5 : - (iFifo$D_OUT[153] ? - 5'd6 : - (iFifo$D_OUT[152] ? - 5'd7 : - (iFifo$D_OUT[151] ? - 5'd8 : - (iFifo$D_OUT[150] ? - 5'd9 : - (iFifo$D_OUT[149] ? - 5'd10 : - (iFifo$D_OUT[148] ? - 5'd11 : - (iFifo$D_OUT[147] ? - 5'd12 : - (iFifo$D_OUT[146] ? - 5'd13 : - (iFifo$D_OUT[145] ? - 5'd14 : - (iFifo$D_OUT[144] ? - 5'd15 : - (iFifo$D_OUT[143] ? - 5'd16 : - (iFifo$D_OUT[142] ? - 5'd17 : - (iFifo$D_OUT[141] ? - 5'd18 : - (iFifo$D_OUT[140] ? - 5'd19 : - (iFifo$D_OUT[139] ? - 5'd20 : - (iFifo$D_OUT[138] ? - 5'd21 : - (iFifo$D_OUT[137] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3188 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[29] ? - 5'd0 : - (iFifo$D_OUT[28] ? - 5'd1 : - (iFifo$D_OUT[27] ? - 5'd2 : - (iFifo$D_OUT[26] ? - 5'd3 : - (iFifo$D_OUT[25] ? - 5'd4 : - (iFifo$D_OUT[24] ? - 5'd5 : - (iFifo$D_OUT[23] ? - 5'd6 : - (iFifo$D_OUT[22] ? - 5'd7 : - (iFifo$D_OUT[21] ? - 5'd8 : - (iFifo$D_OUT[20] ? - 5'd9 : - (iFifo$D_OUT[19] ? - 5'd10 : - (iFifo$D_OUT[18] ? - 5'd11 : - (iFifo$D_OUT[17] ? - 5'd12 : - (iFifo$D_OUT[16] ? - 5'd13 : - (iFifo$D_OUT[15] ? - 5'd14 : - (iFifo$D_OUT[14] ? - 5'd15 : - (iFifo$D_OUT[13] ? - 5'd16 : - (iFifo$D_OUT[12] ? - 5'd17 : - (iFifo$D_OUT[11] ? - 5'd18 : - (iFifo$D_OUT[10] ? - 5'd19 : - (iFifo$D_OUT[9] ? - 5'd20 : - (iFifo$D_OUT[8] ? - 5'd21 : - (iFifo$D_OUT[7] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3908 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 = - 12'd3970 - - { 7'd0, - iFifo$D_OUT[94] ? - 5'd0 : - (iFifo$D_OUT[93] ? - 5'd1 : - (iFifo$D_OUT[92] ? - 5'd2 : - (iFifo$D_OUT[91] ? - 5'd3 : - (iFifo$D_OUT[90] ? - 5'd4 : - (iFifo$D_OUT[89] ? - 5'd5 : - (iFifo$D_OUT[88] ? - 5'd6 : - (iFifo$D_OUT[87] ? - 5'd7 : - (iFifo$D_OUT[86] ? - 5'd8 : - (iFifo$D_OUT[85] ? - 5'd9 : - (iFifo$D_OUT[84] ? - 5'd10 : - (iFifo$D_OUT[83] ? - 5'd11 : - (iFifo$D_OUT[82] ? - 5'd12 : - (iFifo$D_OUT[81] ? - 5'd13 : - (iFifo$D_OUT[80] ? - 5'd14 : - (iFifo$D_OUT[79] ? - 5'd15 : - (iFifo$D_OUT[78] ? - 5'd16 : - (iFifo$D_OUT[77] ? - 5'd17 : - (iFifo$D_OUT[76] ? - 5'd18 : - (iFifo$D_OUT[75] ? - 5'd19 : - (iFifo$D_OUT[74] ? - 5'd20 : - (iFifo$D_OUT[73] ? - 5'd21 : - (iFifo$D_OUT[72] ? - 5'd22 : - 5'd23)))))))))))))))))))))) } ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^ - 12'h800) <= - 12'd3071 ; - assign _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 = - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4683 ^ - 12'h800) < - 12'd1026 ; - assign _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 = - 12'd3970 - - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6031 ; - assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 = - 13'd7170 - fpu_madd_fState_S3$D_OUT[12:0] ; - assign _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 = - (_7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ^ - 13'h1000) <= - 13'd4096 ; - assign _theResult____h164614 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ^ - 12'h800) < - 12'd2105) ? - result__h165227 : - ((value__h148923 == 25'd0) ? sfd__h144536 : 57'd1) ; - assign _theResult____h203252 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ^ - 12'h800) < - 12'd2105) ? - result__h203865 : - ((value__h187561 == 25'd0) ? sfd__h183176 : 57'd1) ; - assign _theResult____h242191 = - ((_3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ^ - 12'h800) < - 12'd2105) ? - result__h242804 : - ((value__h226500 == 25'd0) ? sfd__h222115 : 57'd1) ; - assign _theResult____h269577 = - (value__h270197 == 54'd0) ? sfd__h261975 : 57'd1 ; - assign _theResult____h287214 = - ((_3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ^ - 12'h800) < - 12'd2105) ? - result__h287827 : - _theResult____h269577 ; - assign _theResult____h32523 = - (fpu_div64_fState_S2$D_OUT[10:0] < 11'd58) ? - result__h32648 : - result__h32823 ; - assign _theResult___exp__h142541 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h142626) : - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d2986 ; - assign _theResult___exp__h163981 = - sfd__h163354[53] ? - ((_theResult___fst_exp__h163336 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182469) : - ((_theResult___fst_exp__h163336 == 11'd0 && - sfd__h163354[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h163336) ; - assign _theResult___exp__h173571 = - sfd__h172944[53] ? - ((_theResult___fst_exp__h172852 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182504) : - ((_theResult___fst_exp__h172852 == 11'd0 && - sfd__h172944[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h172852) ; - assign _theResult___exp__h182323 = - sfd__h181672[53] ? - ((_theResult___fst_exp__h181653 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h182530) : - ((_theResult___fst_exp__h181653 == 11'd0 && - sfd__h181672[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h181653) ; - assign _theResult___exp__h202619 = - sfd__h201992[53] ? - ((_theResult___fst_exp__h201974 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221107) : - ((_theResult___fst_exp__h201974 == 11'd0 && - sfd__h201992[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h201974) ; - assign _theResult___exp__h212209 = - sfd__h211582[53] ? - ((_theResult___fst_exp__h211490 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221142) : - ((_theResult___fst_exp__h211490 == 11'd0 && - sfd__h211582[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h211490) ; - assign _theResult___exp__h220961 = - sfd__h220310[53] ? - ((_theResult___fst_exp__h220291 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h221168) : - ((_theResult___fst_exp__h220291 == 11'd0 && - sfd__h220310[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h220291) ; - assign _theResult___exp__h241558 = - sfd__h240931[53] ? - ((_theResult___fst_exp__h240913 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260046) : - ((_theResult___fst_exp__h240913 == 11'd0 && - sfd__h240931[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h240913) ; - assign _theResult___exp__h251148 = - sfd__h250521[53] ? - ((_theResult___fst_exp__h250429 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260081) : - ((_theResult___fst_exp__h250429 == 11'd0 && - sfd__h250521[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h250429) ; - assign _theResult___exp__h259900 = - sfd__h259249[53] ? - ((_theResult___fst_exp__h259230 == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h260107) : - ((_theResult___fst_exp__h259230 == 11'd0 && - sfd__h259249[53:52] == 2'b01) ? - 11'd1 : - _theResult___fst_exp__h259230) ; - assign _theResult___exp__h278202 = - sfd__h277778[24] ? - ((_theResult___fst_exp__h277686 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304723) : - ((_theResult___fst_exp__h277686 == 8'd0 && - sfd__h277778[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h277686) ; - assign _theResult___exp__h286784 = - sfd__h286360[24] ? - ((_theResult___fst_exp__h286342 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304749) : - ((_theResult___fst_exp__h286342 == 8'd0 && - sfd__h286360[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h286342) ; - assign _theResult___exp__h295968 = - sfd__h295544[24] ? - ((_theResult___fst_exp__h295452 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304784) : - ((_theResult___fst_exp__h295452 == 8'd0 && - sfd__h295544[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h295452) ; - assign _theResult___exp__h304604 = - sfd__h304156[24] ? - ((_theResult___fst_exp__h304137 == 8'd254) ? - 8'd255 : - din_inc___2_exp__h304810) : - ((_theResult___fst_exp__h304137 == 8'd0 && - sfd__h304156[24:23] == 2'b01) ? - 8'd1 : - _theResult___fst_exp__h304137) ; - assign _theResult___exp__h43475 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h43566) : - IF_fpu_div64_fState_S4_first__43_BITS_64_TO_54_ETC___d977 ; - assign _theResult___exp__h95909 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 11'd2047 : - din_inc___2_exp__h96000) : - IF_fpu_sqr64_fState_S4_first__687_BITS_64_TO_5_ETC___d1721 ; - assign _theResult___fst__h116827 = - { fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[105:1], - fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012[0] | - sfdlsb__h116825 } ; - assign _theResult___fst__h1476 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___fst__h1600 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign _theResult___fst__h1515 = - (rg_res[116] || rg_b == 116'd0) ? rg_b : b__h1608 ; - assign _theResult___fst__h1600 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 : - b__h1712 ; - assign _theResult___fst__h31322 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499 ? - value__h31550[10:0] : - 11'd0 ; - assign _theResult___fst_exp__h130949 = - sfdBC__h115662[105] ? - _theResult___fst_exp__h130971 : - _theResult___fst_exp__h131034 ; - assign _theResult___fst_exp__h130952 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h130949 ; - assign _theResult___fst_exp__h130971 = - (din_exp__h130866 == 11'd0) ? 11'd2 : din_exp__h130866 + 11'd1 ; - assign _theResult___fst_exp__h130986 = - (din_exp__h130866 == 11'd0) ? 11'd1 : din_exp__h130866 ; - assign _theResult___fst_exp__h131025 = - din_exp__h130866 - - { 4'd0, - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 } ; - assign _theResult___fst_exp__h131031 = - (!sfdBC__h115662[105] && !sfdBC__h115662[104] && - !sfdBC__h115662[103] && - !sfdBC__h115662[102] && - !sfdBC__h115662[101] && - !sfdBC__h115662[100] && - !sfdBC__h115662[99] && - !sfdBC__h115662[98] && - !sfdBC__h115662[97] && - !sfdBC__h115662[96] && - !sfdBC__h115662[95] && - !sfdBC__h115662[94] && - !sfdBC__h115662[93] && - !sfdBC__h115662[92] && - !sfdBC__h115662[91] && - !sfdBC__h115662[90] && - !sfdBC__h115662[89] && - !sfdBC__h115662[88] && - !sfdBC__h115662[87] && - !sfdBC__h115662[86] && - !sfdBC__h115662[85] && - !sfdBC__h115662[84] && - !sfdBC__h115662[83] && - !sfdBC__h115662[82] && - !sfdBC__h115662[81] && - !sfdBC__h115662[80] && - !sfdBC__h115662[79] && - !sfdBC__h115662[78] && - !sfdBC__h115662[77] && - !sfdBC__h115662[76] && - !sfdBC__h115662[75] && - !sfdBC__h115662[74] && - !sfdBC__h115662[73] && - !sfdBC__h115662[72] && - !sfdBC__h115662[71] && - !sfdBC__h115662[70] && - !sfdBC__h115662[69] && - !sfdBC__h115662[68] && - !sfdBC__h115662[67] && - !sfdBC__h115662[66] && - !sfdBC__h115662[65] && - !sfdBC__h115662[64] && - !sfdBC__h115662[63] && - !sfdBC__h115662[62] && - !sfdBC__h115662[61] && - !sfdBC__h115662[60] && - !sfdBC__h115662[59] && - !sfdBC__h115662[58] && - !sfdBC__h115662[57] && - !sfdBC__h115662[56] && - !sfdBC__h115662[55] && - !sfdBC__h115662[54] && - !sfdBC__h115662[53] && - !sfdBC__h115662[52] && - !sfdBC__h115662[51] && - !sfdBC__h115662[50] && - !sfdBC__h115662[49] && - !sfdBC__h115662[48] && - !sfdBC__h115662[47] && - !sfdBC__h115662[46] && - !sfdBC__h115662[45] && - !sfdBC__h115662[44] && - !sfdBC__h115662[43] && - !sfdBC__h115662[42] && - !sfdBC__h115662[41] && - !sfdBC__h115662[40] && - !sfdBC__h115662[39] && - !sfdBC__h115662[38] && - !sfdBC__h115662[37] && - !sfdBC__h115662[36] && - !sfdBC__h115662[35] && - !sfdBC__h115662[34] && - !sfdBC__h115662[33] && - !sfdBC__h115662[32] && - !sfdBC__h115662[31] && - !sfdBC__h115662[30] && - !sfdBC__h115662[29] && - !sfdBC__h115662[28] && - !sfdBC__h115662[27] && - !sfdBC__h115662[26] && - !sfdBC__h115662[25] && - !sfdBC__h115662[24] && - !sfdBC__h115662[23] && - !sfdBC__h115662[22] && - !sfdBC__h115662[21] && - !sfdBC__h115662[20] && - !sfdBC__h115662[19] && - !sfdBC__h115662[18] && - !sfdBC__h115662[17] && - !sfdBC__h115662[16] && - !sfdBC__h115662[15] && - !sfdBC__h115662[14] && - !sfdBC__h115662[13] && - !sfdBC__h115662[12] && - !sfdBC__h115662[11] && - !sfdBC__h115662[10] && - !sfdBC__h115662[9] && - !sfdBC__h115662[8] && - !sfdBC__h115662[7] && - !sfdBC__h115662[6] && - !sfdBC__h115662[5] && - !sfdBC__h115662[4] && - !sfdBC__h115662[3] && - !sfdBC__h115662[2] && - !sfdBC__h115662[1] && - !sfdBC__h115662[0] || - !_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S3_f_ETC___d2463) ? - 11'd0 : - _theResult___fst_exp__h131025 ; - assign _theResult___fst_exp__h131034 = - (!sfdBC__h115662[105] && sfdBC__h115662[104]) ? - _theResult___fst_exp__h130986 : - _theResult___fst_exp__h131031 ; - assign _theResult___fst_exp__h141375 = - sfd__h133119[56] ? - _theResult___fst_exp__h141397 : - _theResult___fst_exp__h141460 ; - assign _theResult___fst_exp__h141378 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h141375 ; - assign _theResult___fst_exp__h141397 = - (value__h141307[10:0] == 11'd0) ? - 11'd2 : - value__h141307[10:0] + 11'd1 ; - assign _theResult___fst_exp__h141412 = - (value__h141307[10:0] == 11'd0) ? 11'd1 : value__h141307[10:0] ; - assign _theResult___fst_exp__h141451 = - value__h141307[10:0] - - { 5'd0, - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 } ; - assign _theResult___fst_exp__h141457 = - (!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] && - !sfd__h133119[53] && - !sfd__h133119[52] && - !sfd__h133119[51] && - !sfd__h133119[50] && - !sfd__h133119[49] && - !sfd__h133119[48] && - !sfd__h133119[47] && - !sfd__h133119[46] && - !sfd__h133119[45] && - !sfd__h133119[44] && - !sfd__h133119[43] && - !sfd__h133119[42] && - !sfd__h133119[41] && - !sfd__h133119[40] && - !sfd__h133119[39] && - !sfd__h133119[38] && - !sfd__h133119[37] && - !sfd__h133119[36] && - !sfd__h133119[35] && - !sfd__h133119[34] && - !sfd__h133119[33] && - !sfd__h133119[32] && - !sfd__h133119[31] && - !sfd__h133119[30] && - !sfd__h133119[29] && - !sfd__h133119[28] && - !sfd__h133119[27] && - !sfd__h133119[26] && - !sfd__h133119[25] && - !sfd__h133119[24] && - !sfd__h133119[23] && - !sfd__h133119[22] && - !sfd__h133119[21] && - !sfd__h133119[20] && - !sfd__h133119[19] && - !sfd__h133119[18] && - !sfd__h133119[17] && - !sfd__h133119[16] && - !sfd__h133119[15] && - !sfd__h133119[14] && - !sfd__h133119[13] && - !sfd__h133119[12] && - !sfd__h133119[11] && - !sfd__h133119[10] && - !sfd__h133119[9] && - !sfd__h133119[8] && - !sfd__h133119[7] && - !sfd__h133119[6] && - !sfd__h133119[5] && - !sfd__h133119[4] && - !sfd__h133119[3] && - !sfd__h133119[2] && - !sfd__h133119[1] && - !sfd__h133119[0] || - !_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__651_B_ETC___d2904) ? - 11'd0 : - _theResult___fst_exp__h141451 ; - assign _theResult___fst_exp__h141460 = - (!sfd__h133119[56] && sfd__h133119[55]) ? - _theResult___fst_exp__h141412 : - _theResult___fst_exp__h141457 ; - assign _theResult___fst_exp__h163327 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ; - assign _theResult___fst_exp__h163333 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 || - !_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3273) ? - 11'd0 : - _theResult___fst_exp__h163327 ; - assign _theResult___fst_exp__h163336 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___fst_exp__h163333 : - 11'd897 ; - assign _theResult___fst_exp__h164062 = - (_theResult___fst_exp__h163336 == 11'd2047) ? - _theResult___fst_exp__h163336 : - _theResult___fst_exp__h164059 ; - assign _theResult___fst_exp__h172852 = - _theResult____h164614[56] ? - 11'd2 : - _theResult___fst_exp__h172926 ; - assign _theResult___fst_exp__h172917 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 } ; - assign _theResult___fst_exp__h172923 = - (!_theResult____h164614[56] && !_theResult____h164614[55] && - !_theResult____h164614[54] && - !_theResult____h164614[53] && - !_theResult____h164614[52] && - !_theResult____h164614[51] && - !_theResult____h164614[50] && - !_theResult____h164614[49] && - !_theResult____h164614[48] && - !_theResult____h164614[47] && - !_theResult____h164614[46] && - !_theResult____h164614[45] && - !_theResult____h164614[44] && - !_theResult____h164614[43] && - !_theResult____h164614[42] && - !_theResult____h164614[41] && - !_theResult____h164614[40] && - !_theResult____h164614[39] && - !_theResult____h164614[38] && - !_theResult____h164614[37] && - !_theResult____h164614[36] && - !_theResult____h164614[35] && - !_theResult____h164614[34] && - !_theResult____h164614[33] && - !_theResult____h164614[32] && - !_theResult____h164614[31] && - !_theResult____h164614[30] && - !_theResult____h164614[29] && - !_theResult____h164614[28] && - !_theResult____h164614[27] && - !_theResult____h164614[26] && - !_theResult____h164614[25] && - !_theResult____h164614[24] && - !_theResult____h164614[23] && - !_theResult____h164614[22] && - !_theResult____h164614[21] && - !_theResult____h164614[20] && - !_theResult____h164614[19] && - !_theResult____h164614[18] && - !_theResult____h164614[17] && - !_theResult____h164614[16] && - !_theResult____h164614[15] && - !_theResult____h164614[14] && - !_theResult____h164614[13] && - !_theResult____h164614[12] && - !_theResult____h164614[11] && - !_theResult____h164614[10] && - !_theResult____h164614[9] && - !_theResult____h164614[8] && - !_theResult____h164614[7] && - !_theResult____h164614[6] && - !_theResult____h164614[5] && - !_theResult____h164614[4] && - !_theResult____h164614[3] && - !_theResult____h164614[2] && - !_theResult____h164614[1] && - !_theResult____h164614[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d3574) ? - 11'd0 : - _theResult___fst_exp__h172917 ; - assign _theResult___fst_exp__h172926 = - (!_theResult____h164614[56] && _theResult____h164614[55]) ? - 11'd1 : - _theResult___fst_exp__h172923 ; - assign _theResult___fst_exp__h173652 = - (_theResult___fst_exp__h172852 == 11'd2047) ? - _theResult___fst_exp__h172852 : - _theResult___fst_exp__h173649 ; - assign _theResult___fst_exp__h181605 = - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] ; - assign _theResult___fst_exp__h181644 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC__q36[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 } ; - assign _theResult___fst_exp__h181650 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244 || - !_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_160_1_ETC___d3624) ? - 11'd0 : - _theResult___fst_exp__h181644 ; - assign _theResult___fst_exp__h181653 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___fst_exp__h181650 : - _theResult___fst_exp__h181605 ; - assign _theResult___fst_exp__h182404 = - (_theResult___fst_exp__h181653 == 11'd2047) ? - _theResult___fst_exp__h181653 : - _theResult___fst_exp__h182401 ; - assign _theResult___fst_exp__h182413 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - _theResult___snd_fst_exp__h164065 : - _theResult___fst_exp__h148291) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - _theResult___snd_fst_exp__h182407 : - _theResult___fst_exp__h148291) ; - assign _theResult___fst_exp__h182416 = - (iFifo$D_OUT[167:160] == 8'd0 && iFifo$D_OUT[159:137] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h182413 ; - assign _theResult___fst_exp__h201965 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ; - assign _theResult___fst_exp__h201971 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 || - !_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d4759) ? - 11'd0 : - _theResult___fst_exp__h201965 ; - assign _theResult___fst_exp__h201974 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___fst_exp__h201971 : - 11'd897 ; - assign _theResult___fst_exp__h202700 = - (_theResult___fst_exp__h201974 == 11'd2047) ? - _theResult___fst_exp__h201974 : - _theResult___fst_exp__h202697 ; - assign _theResult___fst_exp__h211490 = - _theResult____h203252[56] ? - 11'd2 : - _theResult___fst_exp__h211564 ; - assign _theResult___fst_exp__h211555 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 } ; - assign _theResult___fst_exp__h211561 = - (!_theResult____h203252[56] && !_theResult____h203252[55] && - !_theResult____h203252[54] && - !_theResult____h203252[53] && - !_theResult____h203252[52] && - !_theResult____h203252[51] && - !_theResult____h203252[50] && - !_theResult____h203252[49] && - !_theResult____h203252[48] && - !_theResult____h203252[47] && - !_theResult____h203252[46] && - !_theResult____h203252[45] && - !_theResult____h203252[44] && - !_theResult____h203252[43] && - !_theResult____h203252[42] && - !_theResult____h203252[41] && - !_theResult____h203252[40] && - !_theResult____h203252[39] && - !_theResult____h203252[38] && - !_theResult____h203252[37] && - !_theResult____h203252[36] && - !_theResult____h203252[35] && - !_theResult____h203252[34] && - !_theResult____h203252[33] && - !_theResult____h203252[32] && - !_theResult____h203252[31] && - !_theResult____h203252[30] && - !_theResult____h203252[29] && - !_theResult____h203252[28] && - !_theResult____h203252[27] && - !_theResult____h203252[26] && - !_theResult____h203252[25] && - !_theResult____h203252[24] && - !_theResult____h203252[23] && - !_theResult____h203252[22] && - !_theResult____h203252[21] && - !_theResult____h203252[20] && - !_theResult____h203252[19] && - !_theResult____h203252[18] && - !_theResult____h203252[17] && - !_theResult____h203252[16] && - !_theResult____h203252[15] && - !_theResult____h203252[14] && - !_theResult____h203252[13] && - !_theResult____h203252[12] && - !_theResult____h203252[11] && - !_theResult____h203252[10] && - !_theResult____h203252[9] && - !_theResult____h203252[8] && - !_theResult____h203252[7] && - !_theResult____h203252[6] && - !_theResult____h203252[5] && - !_theResult____h203252[4] && - !_theResult____h203252[3] && - !_theResult____h203252[2] && - !_theResult____h203252[1] && - !_theResult____h203252[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d5057) ? - 11'd0 : - _theResult___fst_exp__h211555 ; - assign _theResult___fst_exp__h211564 = - (!_theResult____h203252[56] && _theResult____h203252[55]) ? - 11'd1 : - _theResult___fst_exp__h211561 ; - assign _theResult___fst_exp__h212290 = - (_theResult___fst_exp__h211490 == 11'd2047) ? - _theResult___fst_exp__h211490 : - _theResult___fst_exp__h212287 ; - assign _theResult___fst_exp__h220243 = - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] ; - assign _theResult___fst_exp__h220282 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC__q96[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 } ; - assign _theResult___fst_exp__h220288 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730 || - !_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_62_ETC___d5107) ? - 11'd0 : - _theResult___fst_exp__h220282 ; - assign _theResult___fst_exp__h220291 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___fst_exp__h220288 : - _theResult___fst_exp__h220243 ; - assign _theResult___fst_exp__h221042 = - (_theResult___fst_exp__h220291 == 11'd2047) ? - _theResult___fst_exp__h220291 : - _theResult___fst_exp__h221039 ; - assign _theResult___fst_exp__h221051 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - _theResult___snd_fst_exp__h202703 : - _theResult___fst_exp__h186931) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - _theResult___snd_fst_exp__h221045 : - _theResult___fst_exp__h186931) ; - assign _theResult___fst_exp__h221054 = - (iFifo$D_OUT[102:95] == 8'd0 && iFifo$D_OUT[94:72] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h221051 ; - assign _theResult___fst_exp__h240904 = - 11'd897 - - { 5'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ; - assign _theResult___fst_exp__h240910 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 || - !_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d3984) ? - 11'd0 : - _theResult___fst_exp__h240904 ; - assign _theResult___fst_exp__h240913 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___fst_exp__h240910 : - 11'd897 ; - assign _theResult___fst_exp__h241639 = - (_theResult___fst_exp__h240913 == 11'd2047) ? - _theResult___fst_exp__h240913 : - _theResult___fst_exp__h241636 ; - assign _theResult___fst_exp__h250429 = - _theResult____h242191[56] ? - 11'd2 : - _theResult___fst_exp__h250503 ; - assign _theResult___fst_exp__h250494 = - 11'd0 - - { 5'd0, - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 } ; - assign _theResult___fst_exp__h250500 = - (!_theResult____h242191[56] && !_theResult____h242191[55] && - !_theResult____h242191[54] && - !_theResult____h242191[53] && - !_theResult____h242191[52] && - !_theResult____h242191[51] && - !_theResult____h242191[50] && - !_theResult____h242191[49] && - !_theResult____h242191[48] && - !_theResult____h242191[47] && - !_theResult____h242191[46] && - !_theResult____h242191[45] && - !_theResult____h242191[44] && - !_theResult____h242191[43] && - !_theResult____h242191[42] && - !_theResult____h242191[41] && - !_theResult____h242191[40] && - !_theResult____h242191[39] && - !_theResult____h242191[38] && - !_theResult____h242191[37] && - !_theResult____h242191[36] && - !_theResult____h242191[35] && - !_theResult____h242191[34] && - !_theResult____h242191[33] && - !_theResult____h242191[32] && - !_theResult____h242191[31] && - !_theResult____h242191[30] && - !_theResult____h242191[29] && - !_theResult____h242191[28] && - !_theResult____h242191[27] && - !_theResult____h242191[26] && - !_theResult____h242191[25] && - !_theResult____h242191[24] && - !_theResult____h242191[23] && - !_theResult____h242191[22] && - !_theResult____h242191[21] && - !_theResult____h242191[20] && - !_theResult____h242191[19] && - !_theResult____h242191[18] && - !_theResult____h242191[17] && - !_theResult____h242191[16] && - !_theResult____h242191[15] && - !_theResult____h242191[14] && - !_theResult____h242191[13] && - !_theResult____h242191[12] && - !_theResult____h242191[11] && - !_theResult____h242191[10] && - !_theResult____h242191[9] && - !_theResult____h242191[8] && - !_theResult____h242191[7] && - !_theResult____h242191[6] && - !_theResult____h242191[5] && - !_theResult____h242191[4] && - !_theResult____h242191[3] && - !_theResult____h242191[2] && - !_theResult____h242191[1] && - !_theResult____h242191[0] || - !_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__08_ETC___d4282) ? - 11'd0 : - _theResult___fst_exp__h250494 ; - assign _theResult___fst_exp__h250503 = - (!_theResult____h242191[56] && _theResult____h242191[55]) ? - 11'd1 : - _theResult___fst_exp__h250500 ; - assign _theResult___fst_exp__h251229 = - (_theResult___fst_exp__h250429 == 11'd2047) ? - _theResult___fst_exp__h250429 : - _theResult___fst_exp__h251226 ; - assign _theResult___fst_exp__h259182 = - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] == - 11'd0) ? - 11'd1 : - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] ; - assign _theResult___fst_exp__h259221 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC__q63[10:0] - - { 5'd0, - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 } ; - assign _theResult___fst_exp__h259227 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955 || - !_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30_850_ETC___d4332) ? - 11'd0 : - _theResult___fst_exp__h259221 ; - assign _theResult___fst_exp__h259230 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___fst_exp__h259227 : - _theResult___fst_exp__h259182 ; - assign _theResult___fst_exp__h259981 = - (_theResult___fst_exp__h259230 == 11'd2047) ? - _theResult___fst_exp__h259230 : - _theResult___fst_exp__h259978 ; - assign _theResult___fst_exp__h259990 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - _theResult___snd_fst_exp__h241642 : - _theResult___fst_exp__h225870) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - _theResult___snd_fst_exp__h259984 : - _theResult___fst_exp__h225870) ; - assign _theResult___fst_exp__h259993 = - (iFifo$D_OUT[37:30] == 8'd0 && iFifo$D_OUT[29:7] == 23'd0) ? - 11'd0 : - _theResult___fst_exp__h259990 ; - assign _theResult___fst_exp__h277686 = - _theResult____h269577[56] ? - 8'd2 : - _theResult___fst_exp__h277760 ; - assign _theResult___fst_exp__h277751 = - 8'd0 - - { 2'd0, - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 } ; - assign _theResult___fst_exp__h277757 = - (!_theResult____h269577[56] && !_theResult____h269577[55] && - !_theResult____h269577[54] && - !_theResult____h269577[53] && - !_theResult____h269577[52] && - !_theResult____h269577[51] && - !_theResult____h269577[50] && - !_theResult____h269577[49] && - !_theResult____h269577[48] && - !_theResult____h269577[47] && - !_theResult____h269577[46] && - !_theResult____h269577[45] && - !_theResult____h269577[44] && - !_theResult____h269577[43] && - !_theResult____h269577[42] && - !_theResult____h269577[41] && - !_theResult____h269577[40] && - !_theResult____h269577[39] && - !_theResult____h269577[38] && - !_theResult____h269577[37] && - !_theResult____h269577[36] && - !_theResult____h269577[35] && - !_theResult____h269577[34] && - !_theResult____h269577[33] && - !_theResult____h269577[32] && - !_theResult____h269577[31] && - !_theResult____h269577[30] && - !_theResult____h269577[29] && - !_theResult____h269577[28] && - !_theResult____h269577[27] && - !_theResult____h269577[26] && - !_theResult____h269577[25] && - !_theResult____h269577[24] && - !_theResult____h269577[23] && - !_theResult____h269577[22] && - !_theResult____h269577[21] && - !_theResult____h269577[20] && - !_theResult____h269577[19] && - !_theResult____h269577[18] && - !_theResult____h269577[17] && - !_theResult____h269577[16] && - !_theResult____h269577[15] && - !_theResult____h269577[14] && - !_theResult____h269577[13] && - !_theResult____h269577[12] && - !_theResult____h269577[11] && - !_theResult____h269577[10] && - !_theResult____h269577[9] && - !_theResult____h269577[8] && - !_theResult____h269577[7] && - !_theResult____h269577[6] && - !_theResult____h269577[5] && - !_theResult____h269577[4] && - !_theResult____h269577[3] && - !_theResult____h269577[2] && - !_theResult____h269577[1] && - !_theResult____h269577[0] || - !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__41_ETC___d5769) ? - 8'd0 : - _theResult___fst_exp__h277751 ; - assign _theResult___fst_exp__h277760 = - (!_theResult____h269577[56] && _theResult____h269577[55]) ? - 8'd1 : - _theResult___fst_exp__h277757 ; - assign _theResult___fst_exp__h278283 = - (_theResult___fst_exp__h277686 == 8'd255) ? - _theResult___fst_exp__h277686 : - _theResult___fst_exp__h278280 ; - assign _theResult___fst_exp__h286333 = - 8'd129 - - { 2'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ; - assign _theResult___fst_exp__h286339 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 || - !_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d5984) ? - 8'd0 : - _theResult___fst_exp__h286333 ; - assign _theResult___fst_exp__h286342 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___fst_exp__h286339 : - 8'd129 ; - assign _theResult___fst_exp__h286865 = - (_theResult___fst_exp__h286342 == 8'd255) ? - _theResult___fst_exp__h286342 : - _theResult___fst_exp__h286862 ; - assign _theResult___fst_exp__h295452 = - _theResult____h287214[56] ? - 8'd2 : - _theResult___fst_exp__h295526 ; - assign _theResult___fst_exp__h295517 = - 8'd0 - - { 2'd0, - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 } ; - assign _theResult___fst_exp__h295523 = - (!_theResult____h287214[56] && !_theResult____h287214[55] && - !_theResult____h287214[54] && - !_theResult____h287214[53] && - !_theResult____h287214[52] && - !_theResult____h287214[51] && - !_theResult____h287214[50] && - !_theResult____h287214[49] && - !_theResult____h287214[48] && - !_theResult____h287214[47] && - !_theResult____h287214[46] && - !_theResult____h287214[45] && - !_theResult____h287214[44] && - !_theResult____h287214[43] && - !_theResult____h287214[42] && - !_theResult____h287214[41] && - !_theResult____h287214[40] && - !_theResult____h287214[39] && - !_theResult____h287214[38] && - !_theResult____h287214[37] && - !_theResult____h287214[36] && - !_theResult____h287214[35] && - !_theResult____h287214[34] && - !_theResult____h287214[33] && - !_theResult____h287214[32] && - !_theResult____h287214[31] && - !_theResult____h287214[30] && - !_theResult____h287214[29] && - !_theResult____h287214[28] && - !_theResult____h287214[27] && - !_theResult____h287214[26] && - !_theResult____h287214[25] && - !_theResult____h287214[24] && - !_theResult____h287214[23] && - !_theResult____h287214[22] && - !_theResult____h287214[21] && - !_theResult____h287214[20] && - !_theResult____h287214[19] && - !_theResult____h287214[18] && - !_theResult____h287214[17] && - !_theResult____h287214[16] && - !_theResult____h287214[15] && - !_theResult____h287214[14] && - !_theResult____h287214[13] && - !_theResult____h287214[12] && - !_theResult____h287214[11] && - !_theResult____h287214[10] && - !_theResult____h287214[9] && - !_theResult____h287214[8] && - !_theResult____h287214[7] && - !_theResult____h287214[6] && - !_theResult____h287214[5] && - !_theResult____h287214[4] && - !_theResult____h287214[3] && - !_theResult____h287214[2] && - !_theResult____h287214[1] && - !_theResult____h287214[0] || - !_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget__4_ETC___d6280) ? - 8'd0 : - _theResult___fst_exp__h295517 ; - assign _theResult___fst_exp__h295526 = - (!_theResult____h287214[56] && _theResult____h287214[55]) ? - 8'd1 : - _theResult___fst_exp__h295523 ; - assign _theResult___fst_exp__h296049 = - (_theResult___fst_exp__h295452 == 8'd255) ? - _theResult___fst_exp__h295452 : - _theResult___fst_exp__h296046 ; - assign _theResult___fst_exp__h304089 = - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] == - 8'd0) ? - 8'd1 : - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] ; - assign _theResult___fst_exp__h304128 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC__q138[7:0] - - { 2'd0, - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 } ; - assign _theResult___fst_exp__h304134 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927 || - !_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_41_ETC___d6333) ? - 8'd0 : - _theResult___fst_exp__h304128 ; - assign _theResult___fst_exp__h304137 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___fst_exp__h304134 : - _theResult___fst_exp__h304089 ; - assign _theResult___fst_exp__h304685 = - (_theResult___fst_exp__h304137 == 8'd255) ? - _theResult___fst_exp__h304137 : - _theResult___fst_exp__h304682 ; - assign _theResult___fst_exp__h304694 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - _theResult___snd_fst_exp__h286868 : - _theResult___fst_exp__h269559) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - _theResult___snd_fst_exp__h304688 : - _theResult___fst_exp__h269559) ; - assign _theResult___fst_exp__h304697 = - (resWire$wget[67:57] == 11'd0 && resWire$wget[56:5] == 52'd0) ? - 8'd0 : - _theResult___fst_exp__h304694 ; - assign _theResult___fst_exp__h42284 = - fpu_div64_fState_S3$D_OUT[120:110] - 11'd1 ; - assign _theResult___fst_exp__h42287 = - (fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___fst_exp__h42284 : - 11'd2046 ; - assign _theResult___fst_exp__h42290 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___fst_exp__h42287 : - fpu_div64_fState_S3$D_OUT[120:110] ; - assign _theResult___fst_exp__h42333 = - sfdin__h34118[57] ? - _theResult___fst_exp__h42356 : - _theResult___fst_exp__h42420 ; - assign _theResult___fst_exp__h42336 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h42333 ; - assign _theResult___fst_exp__h42356 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 11'd2 : - _theResult___fst_exp__h42290 + 11'd1 ; - assign _theResult___fst_exp__h42372 = - (_theResult___fst_exp__h42290 == 11'd0) ? - 11'd1 : - _theResult___fst_exp__h42290 ; - assign _theResult___fst_exp__h42411 = - _theResult___fst_exp__h42290 - - { 5'd0, - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 } ; - assign _theResult___fst_exp__h42417 = - (!sfdin__h34118[57] && !sfdin__h34118[56] && - !sfdin__h34118[55] && - !sfdin__h34118[54] && - !sfdin__h34118[53] && - !sfdin__h34118[52] && - !sfdin__h34118[51] && - !sfdin__h34118[50] && - !sfdin__h34118[49] && - !sfdin__h34118[48] && - !sfdin__h34118[47] && - !sfdin__h34118[46] && - !sfdin__h34118[45] && - !sfdin__h34118[44] && - !sfdin__h34118[43] && - !sfdin__h34118[42] && - !sfdin__h34118[41] && - !sfdin__h34118[40] && - !sfdin__h34118[39] && - !sfdin__h34118[38] && - !sfdin__h34118[37] && - !sfdin__h34118[36] && - !sfdin__h34118[35] && - !sfdin__h34118[34] && - !sfdin__h34118[33] && - !sfdin__h34118[32] && - !sfdin__h34118[31] && - !sfdin__h34118[30] && - !sfdin__h34118[29] && - !sfdin__h34118[28] && - !sfdin__h34118[27] && - !sfdin__h34118[26] && - !sfdin__h34118[25] && - !sfdin__h34118[24] && - !sfdin__h34118[23] && - !sfdin__h34118[22] && - !sfdin__h34118[21] && - !sfdin__h34118[20] && - !sfdin__h34118[19] && - !sfdin__h34118[18] && - !sfdin__h34118[17] && - !sfdin__h34118[16] && - !sfdin__h34118[15] && - !sfdin__h34118[14] && - !sfdin__h34118[13] && - !sfdin__h34118[12] && - !sfdin__h34118[11] && - !sfdin__h34118[10] && - !sfdin__h34118[9] && - !sfdin__h34118[8] && - !sfdin__h34118[7] && - !sfdin__h34118[6] && - !sfdin__h34118[5] && - !sfdin__h34118[4] && - !sfdin__h34118[3] && - !sfdin__h34118[2] && - !sfdin__h34118[1] && - !sfdin__h34118[0] || - !_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__86_B_ETC___d883) ? - 11'd0 : - _theResult___fst_exp__h42411 ; - assign _theResult___fst_exp__h42420 = - (!sfdin__h34118[57] && sfdin__h34118[56]) ? - _theResult___fst_exp__h42372 : - _theResult___fst_exp__h42417 ; - assign _theResult___fst_exp__h43556 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h43553 ; - assign _theResult___fst_exp__h94750 = - fpu_sqr64_fState_S3$D_OUT[58] ? - _theResult___fst_exp__h94773 : - _theResult___fst_exp__h94837 ; - assign _theResult___fst_exp__h94753 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 11'd2046 : - _theResult___fst_exp__h94750 ; - assign _theResult___fst_exp__h94773 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd2 : - fpu_sqr64_fState_S3$D_OUT[121:111] + 11'd1 ; - assign _theResult___fst_exp__h94789 = - (fpu_sqr64_fState_S3$D_OUT[121:111] == 11'd0) ? - 11'd1 : - fpu_sqr64_fState_S3$D_OUT[121:111] ; - assign _theResult___fst_exp__h94828 = - fpu_sqr64_fState_S3$D_OUT[121:111] - - { 5'd0, - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 } ; - assign _theResult___fst_exp__h94834 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - !fpu_sqr64_fState_S3$D_OUT[57] && - !fpu_sqr64_fState_S3$D_OUT[56] && - !fpu_sqr64_fState_S3$D_OUT[55] && - !fpu_sqr64_fState_S3$D_OUT[54] && - !fpu_sqr64_fState_S3$D_OUT[53] && - !fpu_sqr64_fState_S3$D_OUT[52] && - !fpu_sqr64_fState_S3$D_OUT[51] && - !fpu_sqr64_fState_S3$D_OUT[50] && - !fpu_sqr64_fState_S3$D_OUT[49] && - !fpu_sqr64_fState_S3$D_OUT[48] && - !fpu_sqr64_fState_S3$D_OUT[47] && - !fpu_sqr64_fState_S3$D_OUT[46] && - !fpu_sqr64_fState_S3$D_OUT[45] && - !fpu_sqr64_fState_S3$D_OUT[44] && - !fpu_sqr64_fState_S3$D_OUT[43] && - !fpu_sqr64_fState_S3$D_OUT[42] && - !fpu_sqr64_fState_S3$D_OUT[41] && - !fpu_sqr64_fState_S3$D_OUT[40] && - !fpu_sqr64_fState_S3$D_OUT[39] && - !fpu_sqr64_fState_S3$D_OUT[38] && - !fpu_sqr64_fState_S3$D_OUT[37] && - !fpu_sqr64_fState_S3$D_OUT[36] && - !fpu_sqr64_fState_S3$D_OUT[35] && - !fpu_sqr64_fState_S3$D_OUT[34] && - !fpu_sqr64_fState_S3$D_OUT[33] && - !fpu_sqr64_fState_S3$D_OUT[32] && - !fpu_sqr64_fState_S3$D_OUT[31] && - !fpu_sqr64_fState_S3$D_OUT[30] && - !fpu_sqr64_fState_S3$D_OUT[29] && - !fpu_sqr64_fState_S3$D_OUT[28] && - !fpu_sqr64_fState_S3$D_OUT[27] && - !fpu_sqr64_fState_S3$D_OUT[26] && - !fpu_sqr64_fState_S3$D_OUT[25] && - !fpu_sqr64_fState_S3$D_OUT[24] && - !fpu_sqr64_fState_S3$D_OUT[23] && - !fpu_sqr64_fState_S3$D_OUT[22] && - !fpu_sqr64_fState_S3$D_OUT[21] && - !fpu_sqr64_fState_S3$D_OUT[20] && - !fpu_sqr64_fState_S3$D_OUT[19] && - !fpu_sqr64_fState_S3$D_OUT[18] && - !fpu_sqr64_fState_S3$D_OUT[17] && - !fpu_sqr64_fState_S3$D_OUT[16] && - !fpu_sqr64_fState_S3$D_OUT[15] && - !fpu_sqr64_fState_S3$D_OUT[14] && - !fpu_sqr64_fState_S3$D_OUT[13] && - !fpu_sqr64_fState_S3$D_OUT[12] && - !fpu_sqr64_fState_S3$D_OUT[11] && - !fpu_sqr64_fState_S3$D_OUT[10] && - !fpu_sqr64_fState_S3$D_OUT[9] && - !fpu_sqr64_fState_S3$D_OUT[8] && - !fpu_sqr64_fState_S3$D_OUT[7] && - !fpu_sqr64_fState_S3$D_OUT[6] && - !fpu_sqr64_fState_S3$D_OUT[5] && - !fpu_sqr64_fState_S3$D_OUT[4] && - !fpu_sqr64_fState_S3$D_OUT[3] && - !fpu_sqr64_fState_S3$D_OUT[2] && - !fpu_sqr64_fState_S3$D_OUT[1] && - !fpu_sqr64_fState_S3$D_OUT[0] || - !_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375_BIT_ETC___d1633) ? - 11'd0 : - _theResult___fst_exp__h94828 ; - assign _theResult___fst_exp__h94837 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - fpu_sqr64_fState_S3$D_OUT[57]) ? - _theResult___fst_exp__h94789 : - _theResult___fst_exp__h94834 ; - assign _theResult___fst_exp__h95990 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - _theResult___fst_exp__h95987 ; - assign _theResult___fst_sfd__h164063 = - (_theResult___fst_exp__h163336 == 11'd2047) ? - _theResult___snd__h163287[56:5] : - _theResult___fst_sfd__h164060 ; - assign _theResult___fst_sfd__h173653 = - (_theResult___fst_exp__h172852 == 11'd2047) ? - sfdin__h172846[56:5] : - _theResult___fst_sfd__h173650 ; - assign _theResult___fst_sfd__h182405 = - (_theResult___fst_exp__h181653 == 11'd2047) ? - _theResult___snd__h181599[56:5] : - _theResult___fst_sfd__h182402 ; - assign _theResult___fst_sfd__h182414 = - (iFifo$D_OUT[167:160] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3189 ? - _theResult___snd_fst_sfd__h164066 : - _theResult___fst_sfd__h148292) : - (SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3324 ? - _theResult___snd_fst_sfd__h182408 : - _theResult___fst_sfd__h148292) ; - assign _theResult___fst_sfd__h182420 = - ((iFifo$D_OUT[167:160] == 8'd255 || - iFifo$D_OUT[167:160] == 8'd0) && - iFifo$D_OUT[159:137] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h182414 ; - assign _theResult___fst_sfd__h202701 = - (_theResult___fst_exp__h201974 == 11'd2047) ? - _theResult___snd__h201925[56:5] : - _theResult___fst_sfd__h202698 ; - assign _theResult___fst_sfd__h212291 = - (_theResult___fst_exp__h211490 == 11'd2047) ? - sfdin__h211484[56:5] : - _theResult___fst_sfd__h212288 ; - assign _theResult___fst_sfd__h221043 = - (_theResult___fst_exp__h220291 == 11'd2047) ? - _theResult___snd__h220237[56:5] : - _theResult___fst_sfd__h221040 ; - assign _theResult___fst_sfd__h221052 = - (iFifo$D_OUT[102:95] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4684 ? - _theResult___snd_fst_sfd__h202704 : - _theResult___fst_sfd__h186932) : - (SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4807 ? - _theResult___snd_fst_sfd__h221046 : - _theResult___fst_sfd__h186932) ; - assign _theResult___fst_sfd__h221058 = - ((iFifo$D_OUT[102:95] == 8'd255 || - iFifo$D_OUT[102:95] == 8'd0) && - iFifo$D_OUT[94:72] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h221052 ; - assign _theResult___fst_sfd__h241640 = - (_theResult___fst_exp__h240913 == 11'd2047) ? - _theResult___snd__h240864[56:5] : - _theResult___fst_sfd__h241637 ; - assign _theResult___fst_sfd__h251230 = - (_theResult___fst_exp__h250429 == 11'd2047) ? - sfdin__h250423[56:5] : - _theResult___fst_sfd__h251227 ; - assign _theResult___fst_sfd__h259982 = - (_theResult___fst_exp__h259230 == 11'd2047) ? - _theResult___snd__h259176[56:5] : - _theResult___fst_sfd__h259979 ; - assign _theResult___fst_sfd__h259991 = - (iFifo$D_OUT[37:30] == 8'd0) ? - (_3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3909 ? - _theResult___snd_fst_sfd__h241643 : - _theResult___fst_sfd__h225871) : - (SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4032 ? - _theResult___snd_fst_sfd__h259985 : - _theResult___fst_sfd__h225871) ; - assign _theResult___fst_sfd__h259997 = - ((iFifo$D_OUT[37:30] == 8'd255 || iFifo$D_OUT[37:30] == 8'd0) && - iFifo$D_OUT[29:7] == 23'd0) ? - 52'd0 : - _theResult___fst_sfd__h259991 ; - assign _theResult___fst_sfd__h278284 = - (_theResult___fst_exp__h277686 == 8'd255) ? - sfdin__h277680[56:34] : - _theResult___fst_sfd__h278281 ; - assign _theResult___fst_sfd__h286866 = - (_theResult___fst_exp__h286342 == 8'd255) ? - _theResult___snd__h286293[56:34] : - _theResult___fst_sfd__h286863 ; - assign _theResult___fst_sfd__h296050 = - (_theResult___fst_exp__h295452 == 8'd255) ? - sfdin__h295446[56:34] : - _theResult___fst_sfd__h296047 ; - assign _theResult___fst_sfd__h304686 = - (_theResult___fst_exp__h304137 == 8'd255) ? - _theResult___snd__h304083[56:34] : - _theResult___fst_sfd__h304683 ; - assign _theResult___fst_sfd__h304695 = - (resWire$wget[67:57] == 11'd0) ? - (_3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5532 ? - _theResult___snd_fst_sfd__h286869 : - _theResult___fst_sfd__h269560) : - (SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6032 ? - _theResult___snd_fst_sfd__h304689 : - _theResult___fst_sfd__h269560) ; - assign _theResult___fst_sfd__h304701 = - ((resWire$wget[67:57] == 11'd2047 || - resWire$wget[67:57] == 11'd0) && - resWire$wget[56:5] == 52'd0) ? - 23'd0 : - _theResult___fst_sfd__h304695 ; - assign _theResult___fst_sfd__h43557 = - (fpu_div64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_div64_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h43554 ; - assign _theResult___fst_sfd__h95991 = - (fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2047) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - _theResult___fst_sfd__h95988 ; - assign _theResult___fst_sfd__h96608 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[182:131] : - 52'd0 ; - assign _theResult___sfd__h142542 = - sfd__h142040[53] ? - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2046) ? - 52'd0 : - sfd__h142040[52:1]) : - sfd__h142040[51:0] ; - assign _theResult___sfd__h163982 = - sfd__h163354[53] ? - ((_theResult___fst_exp__h163336 == 11'd2046) ? - 52'd0 : - sfd__h163354[52:1]) : - sfd__h163354[51:0] ; - assign _theResult___sfd__h173572 = - sfd__h172944[53] ? - ((_theResult___fst_exp__h172852 == 11'd2046) ? - 52'd0 : - sfd__h172944[52:1]) : - sfd__h172944[51:0] ; - assign _theResult___sfd__h182324 = - sfd__h181672[53] ? - ((_theResult___fst_exp__h181653 == 11'd2046) ? - 52'd0 : - sfd__h181672[52:1]) : - sfd__h181672[51:0] ; - assign _theResult___sfd__h202620 = - sfd__h201992[53] ? - ((_theResult___fst_exp__h201974 == 11'd2046) ? - 52'd0 : - sfd__h201992[52:1]) : - sfd__h201992[51:0] ; - assign _theResult___sfd__h212210 = - sfd__h211582[53] ? - ((_theResult___fst_exp__h211490 == 11'd2046) ? - 52'd0 : - sfd__h211582[52:1]) : - sfd__h211582[51:0] ; - assign _theResult___sfd__h220962 = - sfd__h220310[53] ? - ((_theResult___fst_exp__h220291 == 11'd2046) ? - 52'd0 : - sfd__h220310[52:1]) : - sfd__h220310[51:0] ; - assign _theResult___sfd__h241559 = - sfd__h240931[53] ? - ((_theResult___fst_exp__h240913 == 11'd2046) ? - 52'd0 : - sfd__h240931[52:1]) : - sfd__h240931[51:0] ; - assign _theResult___sfd__h251149 = - sfd__h250521[53] ? - ((_theResult___fst_exp__h250429 == 11'd2046) ? - 52'd0 : - sfd__h250521[52:1]) : - sfd__h250521[51:0] ; - assign _theResult___sfd__h259901 = - sfd__h259249[53] ? - ((_theResult___fst_exp__h259230 == 11'd2046) ? - 52'd0 : - sfd__h259249[52:1]) : - sfd__h259249[51:0] ; - assign _theResult___sfd__h278203 = - sfd__h277778[24] ? - ((_theResult___fst_exp__h277686 == 8'd254) ? - 23'd0 : - sfd__h277778[23:1]) : - sfd__h277778[22:0] ; - assign _theResult___sfd__h286785 = - sfd__h286360[24] ? - ((_theResult___fst_exp__h286342 == 8'd254) ? - 23'd0 : - sfd__h286360[23:1]) : - sfd__h286360[22:0] ; - assign _theResult___sfd__h295969 = - sfd__h295544[24] ? - ((_theResult___fst_exp__h295452 == 8'd254) ? - 23'd0 : - sfd__h295544[23:1]) : - sfd__h295544[22:0] ; - assign _theResult___sfd__h304605 = - sfd__h304156[24] ? - ((_theResult___fst_exp__h304137 == 8'd254) ? - 23'd0 : - sfd__h304156[23:1]) : - sfd__h304156[22:0] ; - assign _theResult___sfd__h43476 = - sfd__h42982[53] ? - ((fpu_div64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h42982[52:1]) : - sfd__h42982[51:0] ; - assign _theResult___sfd__h95910 = - sfd__h95416[53] ? - ((fpu_sqr64_fState_S4$D_OUT[64:54] == 11'd2046) ? - 52'd0 : - sfd__h95416[52:1]) : - sfd__h95416[51:0] ; - assign _theResult___snd__h130966 = { sfdBC__h115662[104:0], 1'd0 } ; - assign _theResult___snd__h130980 = - (!sfdBC__h115662[105] && sfdBC__h115662[104]) ? - _theResult___snd__h130982 : - _theResult___snd__h130994 ; - assign _theResult___snd__h130982 = { sfdBC__h115662[103:0], 2'd0 } ; - assign _theResult___snd__h130994 = - (!sfdBC__h115662[105] && !sfdBC__h115662[104] && - !sfdBC__h115662[103] && - !sfdBC__h115662[102] && - !sfdBC__h115662[101] && - !sfdBC__h115662[100] && - !sfdBC__h115662[99] && - !sfdBC__h115662[98] && - !sfdBC__h115662[97] && - !sfdBC__h115662[96] && - !sfdBC__h115662[95] && - !sfdBC__h115662[94] && - !sfdBC__h115662[93] && - !sfdBC__h115662[92] && - !sfdBC__h115662[91] && - !sfdBC__h115662[90] && - !sfdBC__h115662[89] && - !sfdBC__h115662[88] && - !sfdBC__h115662[87] && - !sfdBC__h115662[86] && - !sfdBC__h115662[85] && - !sfdBC__h115662[84] && - !sfdBC__h115662[83] && - !sfdBC__h115662[82] && - !sfdBC__h115662[81] && - !sfdBC__h115662[80] && - !sfdBC__h115662[79] && - !sfdBC__h115662[78] && - !sfdBC__h115662[77] && - !sfdBC__h115662[76] && - !sfdBC__h115662[75] && - !sfdBC__h115662[74] && - !sfdBC__h115662[73] && - !sfdBC__h115662[72] && - !sfdBC__h115662[71] && - !sfdBC__h115662[70] && - !sfdBC__h115662[69] && - !sfdBC__h115662[68] && - !sfdBC__h115662[67] && - !sfdBC__h115662[66] && - !sfdBC__h115662[65] && - !sfdBC__h115662[64] && - !sfdBC__h115662[63] && - !sfdBC__h115662[62] && - !sfdBC__h115662[61] && - !sfdBC__h115662[60] && - !sfdBC__h115662[59] && - !sfdBC__h115662[58] && - !sfdBC__h115662[57] && - !sfdBC__h115662[56] && - !sfdBC__h115662[55] && - !sfdBC__h115662[54] && - !sfdBC__h115662[53] && - !sfdBC__h115662[52] && - !sfdBC__h115662[51] && - !sfdBC__h115662[50] && - !sfdBC__h115662[49] && - !sfdBC__h115662[48] && - !sfdBC__h115662[47] && - !sfdBC__h115662[46] && - !sfdBC__h115662[45] && - !sfdBC__h115662[44] && - !sfdBC__h115662[43] && - !sfdBC__h115662[42] && - !sfdBC__h115662[41] && - !sfdBC__h115662[40] && - !sfdBC__h115662[39] && - !sfdBC__h115662[38] && - !sfdBC__h115662[37] && - !sfdBC__h115662[36] && - !sfdBC__h115662[35] && - !sfdBC__h115662[34] && - !sfdBC__h115662[33] && - !sfdBC__h115662[32] && - !sfdBC__h115662[31] && - !sfdBC__h115662[30] && - !sfdBC__h115662[29] && - !sfdBC__h115662[28] && - !sfdBC__h115662[27] && - !sfdBC__h115662[26] && - !sfdBC__h115662[25] && - !sfdBC__h115662[24] && - !sfdBC__h115662[23] && - !sfdBC__h115662[22] && - !sfdBC__h115662[21] && - !sfdBC__h115662[20] && - !sfdBC__h115662[19] && - !sfdBC__h115662[18] && - !sfdBC__h115662[17] && - !sfdBC__h115662[16] && - !sfdBC__h115662[15] && - !sfdBC__h115662[14] && - !sfdBC__h115662[13] && - !sfdBC__h115662[12] && - !sfdBC__h115662[11] && - !sfdBC__h115662[10] && - !sfdBC__h115662[9] && - !sfdBC__h115662[8] && - !sfdBC__h115662[7] && - !sfdBC__h115662[6] && - !sfdBC__h115662[5] && - !sfdBC__h115662[4] && - !sfdBC__h115662[3] && - !sfdBC__h115662[2] && - !sfdBC__h115662[1] && - !sfdBC__h115662[0]) ? - sfdBC__h115662 : - _theResult___snd__h131000 ; - assign _theResult___snd__h131000 = - { IF_0_CONCAT_IF_IF_7170_MINUS_fpu_madd_fState_S_ETC__q24[103:0], - 2'd0 } ; - assign _theResult___snd__h131018 = - sfdBC__h115662 << - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2462 ; - assign _theResult___snd__h131023 = - sfdBC__h115662 << - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2460 ; - assign _theResult___snd__h141392 = { sfd__h133119[55:0], 1'd0 } ; - assign _theResult___snd__h141406 = - (!sfd__h133119[56] && sfd__h133119[55]) ? - _theResult___snd__h141408 : - _theResult___snd__h141420 ; - assign _theResult___snd__h141408 = { sfd__h133119[54:0], 2'd0 } ; - assign _theResult___snd__h141420 = - (!sfd__h133119[56] && !sfd__h133119[55] && !sfd__h133119[54] && - !sfd__h133119[53] && - !sfd__h133119[52] && - !sfd__h133119[51] && - !sfd__h133119[50] && - !sfd__h133119[49] && - !sfd__h133119[48] && - !sfd__h133119[47] && - !sfd__h133119[46] && - !sfd__h133119[45] && - !sfd__h133119[44] && - !sfd__h133119[43] && - !sfd__h133119[42] && - !sfd__h133119[41] && - !sfd__h133119[40] && - !sfd__h133119[39] && - !sfd__h133119[38] && - !sfd__h133119[37] && - !sfd__h133119[36] && - !sfd__h133119[35] && - !sfd__h133119[34] && - !sfd__h133119[33] && - !sfd__h133119[32] && - !sfd__h133119[31] && - !sfd__h133119[30] && - !sfd__h133119[29] && - !sfd__h133119[28] && - !sfd__h133119[27] && - !sfd__h133119[26] && - !sfd__h133119[25] && - !sfd__h133119[24] && - !sfd__h133119[23] && - !sfd__h133119[22] && - !sfd__h133119[21] && - !sfd__h133119[20] && - !sfd__h133119[19] && - !sfd__h133119[18] && - !sfd__h133119[17] && - !sfd__h133119[16] && - !sfd__h133119[15] && - !sfd__h133119[14] && - !sfd__h133119[13] && - !sfd__h133119[12] && - !sfd__h133119[11] && - !sfd__h133119[10] && - !sfd__h133119[9] && - !sfd__h133119[8] && - !sfd__h133119[7] && - !sfd__h133119[6] && - !sfd__h133119[5] && - !sfd__h133119[4] && - !sfd__h133119[3] && - !sfd__h133119[2] && - !sfd__h133119[1] && - !sfd__h133119[0]) ? - sfd__h133119 : - _theResult___snd__h141426 ; - assign _theResult___snd__h141426 = - { IF_0_CONCAT_IF_IF_fpu_madd_fState_S7_first__65_ETC__q29[54:0], - 2'd0 } ; - assign _theResult___snd__h141444 = - sfd__h133119 << - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2903 ; - assign _theResult___snd__h141449 = - sfd__h133119 << - IF_IF_fpu_madd_fState_S7_first__651_BIT_128_65_ETC___d2901 ; - assign _theResult___snd__h163287 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___snd__h163296 : - _theResult___snd__h163289 ; - assign _theResult___snd__h163289 = { iFifo$D_OUT[159:137], 34'd0 } ; - assign _theResult___snd__h163296 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ? - sfd__h144536 : - _theResult___snd__h163302 ; - assign _theResult___snd__h163302 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q33[54:0], - 2'd0 } ; - assign _theResult___snd__h163325 = - sfd__h144536 << - IF_iFifo_first__087_BITS_167_TO_160_130_EQ_0_1_ETC___d3271 ; - assign _theResult___snd__h172863 = { _theResult____h164614[55:0], 1'd0 } ; - assign _theResult___snd__h172874 = - (!_theResult____h164614[56] && _theResult____h164614[55]) ? - _theResult___snd__h172876 : - _theResult___snd__h172886 ; - assign _theResult___snd__h172876 = { _theResult____h164614[54:0], 2'd0 } ; - assign _theResult___snd__h172886 = - (!_theResult____h164614[56] && !_theResult____h164614[55] && - !_theResult____h164614[54] && - !_theResult____h164614[53] && - !_theResult____h164614[52] && - !_theResult____h164614[51] && - !_theResult____h164614[50] && - !_theResult____h164614[49] && - !_theResult____h164614[48] && - !_theResult____h164614[47] && - !_theResult____h164614[46] && - !_theResult____h164614[45] && - !_theResult____h164614[44] && - !_theResult____h164614[43] && - !_theResult____h164614[42] && - !_theResult____h164614[41] && - !_theResult____h164614[40] && - !_theResult____h164614[39] && - !_theResult____h164614[38] && - !_theResult____h164614[37] && - !_theResult____h164614[36] && - !_theResult____h164614[35] && - !_theResult____h164614[34] && - !_theResult____h164614[33] && - !_theResult____h164614[32] && - !_theResult____h164614[31] && - !_theResult____h164614[30] && - !_theResult____h164614[29] && - !_theResult____h164614[28] && - !_theResult____h164614[27] && - !_theResult____h164614[26] && - !_theResult____h164614[25] && - !_theResult____h164614[24] && - !_theResult____h164614[23] && - !_theResult____h164614[22] && - !_theResult____h164614[21] && - !_theResult____h164614[20] && - !_theResult____h164614[19] && - !_theResult____h164614[18] && - !_theResult____h164614[17] && - !_theResult____h164614[16] && - !_theResult____h164614[15] && - !_theResult____h164614[14] && - !_theResult____h164614[13] && - !_theResult____h164614[12] && - !_theResult____h164614[11] && - !_theResult____h164614[10] && - !_theResult____h164614[9] && - !_theResult____h164614[8] && - !_theResult____h164614[7] && - !_theResult____h164614[6] && - !_theResult____h164614[5] && - !_theResult____h164614[4] && - !_theResult____h164614[3] && - !_theResult____h164614[2] && - !_theResult____h164614[1] && - !_theResult____h164614[0]) ? - _theResult____h164614 : - _theResult___snd__h172892 ; - assign _theResult___snd__h172892 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q37[54:0], - 2'd0 } ; - assign _theResult___snd__h172915 = - _theResult____h164614 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_16_ETC___d3572 ; - assign _theResult___snd__h181599 = - (iFifo$D_OUT[167:160] == 8'd0) ? - _theResult___snd__h181613 : - _theResult___snd__h163289 ; - assign _theResult___snd__h181613 = - (iFifo$D_OUT[167:160] == 8'd0 && !iFifo$D_OUT[159] && - NOT_iFifo_first__087_BIT_158_142_202_AND_NOT_i_ETC___d3244) ? - sfd__h144536 : - _theResult___snd__h181619 ; - assign _theResult___snd__h181619 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_167_TO_16_ETC__q40[54:0], - 2'd0 } ; - assign _theResult___snd__h181637 = - sfd__h144536 << - IF_SEXT_iFifo_first__087_BITS_167_TO_160_130_M_ETC___d3623 ; - assign _theResult___snd__h201925 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___snd__h201934 : - _theResult___snd__h201927 ; - assign _theResult___snd__h201927 = { iFifo$D_OUT[94:72], 34'd0 } ; - assign _theResult___snd__h201934 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ? - sfd__h183176 : - _theResult___snd__h201940 ; - assign _theResult___snd__h201940 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q93[54:0], - 2'd0 } ; - assign _theResult___snd__h201963 = - sfd__h183176 << - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_0_63_ETC___d4757 ; - assign _theResult___snd__h211501 = { _theResult____h203252[55:0], 1'd0 } ; - assign _theResult___snd__h211512 = - (!_theResult____h203252[56] && _theResult____h203252[55]) ? - _theResult___snd__h211514 : - _theResult___snd__h211524 ; - assign _theResult___snd__h211514 = { _theResult____h203252[54:0], 2'd0 } ; - assign _theResult___snd__h211524 = - (!_theResult____h203252[56] && !_theResult____h203252[55] && - !_theResult____h203252[54] && - !_theResult____h203252[53] && - !_theResult____h203252[52] && - !_theResult____h203252[51] && - !_theResult____h203252[50] && - !_theResult____h203252[49] && - !_theResult____h203252[48] && - !_theResult____h203252[47] && - !_theResult____h203252[46] && - !_theResult____h203252[45] && - !_theResult____h203252[44] && - !_theResult____h203252[43] && - !_theResult____h203252[42] && - !_theResult____h203252[41] && - !_theResult____h203252[40] && - !_theResult____h203252[39] && - !_theResult____h203252[38] && - !_theResult____h203252[37] && - !_theResult____h203252[36] && - !_theResult____h203252[35] && - !_theResult____h203252[34] && - !_theResult____h203252[33] && - !_theResult____h203252[32] && - !_theResult____h203252[31] && - !_theResult____h203252[30] && - !_theResult____h203252[29] && - !_theResult____h203252[28] && - !_theResult____h203252[27] && - !_theResult____h203252[26] && - !_theResult____h203252[25] && - !_theResult____h203252[24] && - !_theResult____h203252[23] && - !_theResult____h203252[22] && - !_theResult____h203252[21] && - !_theResult____h203252[20] && - !_theResult____h203252[19] && - !_theResult____h203252[18] && - !_theResult____h203252[17] && - !_theResult____h203252[16] && - !_theResult____h203252[15] && - !_theResult____h203252[14] && - !_theResult____h203252[13] && - !_theResult____h203252[12] && - !_theResult____h203252[11] && - !_theResult____h203252[10] && - !_theResult____h203252[9] && - !_theResult____h203252[8] && - !_theResult____h203252[7] && - !_theResult____h203252[6] && - !_theResult____h203252[5] && - !_theResult____h203252[4] && - !_theResult____h203252[3] && - !_theResult____h203252[2] && - !_theResult____h203252[1] && - !_theResult____h203252[0]) ? - _theResult____h203252 : - _theResult___snd__h211530 ; - assign _theResult___snd__h211530 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q97[54:0], - 2'd0 } ; - assign _theResult___snd__h211553 = - _theResult____h203252 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_10_ETC___d5055 ; - assign _theResult___snd__h220237 = - (iFifo$D_OUT[102:95] == 8'd0) ? - _theResult___snd__h220251 : - _theResult___snd__h201927 ; - assign _theResult___snd__h220251 = - (iFifo$D_OUT[102:95] == 8'd0 && !iFifo$D_OUT[94] && - NOT_iFifo_first__087_BIT_93_637_688_AND_NOT_iF_ETC___d4730) ? - sfd__h183176 : - _theResult___snd__h220257 ; - assign _theResult___snd__h220257 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_102_TO_95_ETC__q100[54:0], - 2'd0 } ; - assign _theResult___snd__h220275 = - sfd__h183176 << - IF_SEXT_iFifo_first__087_BITS_102_TO_95_625_MI_ETC___d5106 ; - assign _theResult___snd__h240864 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___snd__h240873 : - _theResult___snd__h240866 ; - assign _theResult___snd__h240866 = { iFifo$D_OUT[29:7], 34'd0 } ; - assign _theResult___snd__h240873 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ? - sfd__h222115 : - _theResult___snd__h240879 ; - assign _theResult___snd__h240879 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q60[54:0], - 2'd0 } ; - assign _theResult___snd__h240902 = - sfd__h222115 << - IF_iFifo_first__087_BITS_37_TO_30_850_EQ_0_856_ETC___d3982 ; - assign _theResult___snd__h250440 = { _theResult____h242191[55:0], 1'd0 } ; - assign _theResult___snd__h250451 = - (!_theResult____h242191[56] && _theResult____h242191[55]) ? - _theResult___snd__h250453 : - _theResult___snd__h250463 ; - assign _theResult___snd__h250453 = { _theResult____h242191[54:0], 2'd0 } ; - assign _theResult___snd__h250463 = - (!_theResult____h242191[56] && !_theResult____h242191[55] && - !_theResult____h242191[54] && - !_theResult____h242191[53] && - !_theResult____h242191[52] && - !_theResult____h242191[51] && - !_theResult____h242191[50] && - !_theResult____h242191[49] && - !_theResult____h242191[48] && - !_theResult____h242191[47] && - !_theResult____h242191[46] && - !_theResult____h242191[45] && - !_theResult____h242191[44] && - !_theResult____h242191[43] && - !_theResult____h242191[42] && - !_theResult____h242191[41] && - !_theResult____h242191[40] && - !_theResult____h242191[39] && - !_theResult____h242191[38] && - !_theResult____h242191[37] && - !_theResult____h242191[36] && - !_theResult____h242191[35] && - !_theResult____h242191[34] && - !_theResult____h242191[33] && - !_theResult____h242191[32] && - !_theResult____h242191[31] && - !_theResult____h242191[30] && - !_theResult____h242191[29] && - !_theResult____h242191[28] && - !_theResult____h242191[27] && - !_theResult____h242191[26] && - !_theResult____h242191[25] && - !_theResult____h242191[24] && - !_theResult____h242191[23] && - !_theResult____h242191[22] && - !_theResult____h242191[21] && - !_theResult____h242191[20] && - !_theResult____h242191[19] && - !_theResult____h242191[18] && - !_theResult____h242191[17] && - !_theResult____h242191[16] && - !_theResult____h242191[15] && - !_theResult____h242191[14] && - !_theResult____h242191[13] && - !_theResult____h242191[12] && - !_theResult____h242191[11] && - !_theResult____h242191[10] && - !_theResult____h242191[9] && - !_theResult____h242191[8] && - !_theResult____h242191[7] && - !_theResult____h242191[6] && - !_theResult____h242191[5] && - !_theResult____h242191[4] && - !_theResult____h242191[3] && - !_theResult____h242191[2] && - !_theResult____h242191[1] && - !_theResult____h242191[0]) ? - _theResult____h242191 : - _theResult___snd__h250469 ; - assign _theResult___snd__h250469 = - { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_iFifo_first__ETC__q64[54:0], - 2'd0 } ; - assign _theResult___snd__h250492 = - _theResult____h242191 << - IF_IF_3074_MINUS_SEXT_iFifo_first__087_BITS_37_ETC___d4280 ; - assign _theResult___snd__h259176 = - (iFifo$D_OUT[37:30] == 8'd0) ? - _theResult___snd__h259190 : - _theResult___snd__h240866 ; - assign _theResult___snd__h259190 = - (iFifo$D_OUT[37:30] == 8'd0 && !iFifo$D_OUT[29] && - NOT_iFifo_first__087_BIT_28_862_913_AND_NOT_iF_ETC___d3955) ? - sfd__h222115 : - _theResult___snd__h259196 ; - assign _theResult___snd__h259196 = - { IF_0_CONCAT_IF_iFifo_first__087_BITS_37_TO_30__ETC__q67[54:0], - 2'd0 } ; - assign _theResult___snd__h259214 = - sfd__h222115 << - IF_SEXT_iFifo_first__087_BITS_37_TO_30_850_MIN_ETC___d4331 ; - assign _theResult___snd__h277697 = { _theResult____h269577[55:0], 1'd0 } ; - assign _theResult___snd__h277708 = - (!_theResult____h269577[56] && _theResult____h269577[55]) ? - _theResult___snd__h277710 : - _theResult___snd__h277720 ; - assign _theResult___snd__h277710 = { _theResult____h269577[54:0], 2'd0 } ; - assign _theResult___snd__h277720 = - (!_theResult____h269577[56] && !_theResult____h269577[55] && - !_theResult____h269577[54] && - !_theResult____h269577[53] && - !_theResult____h269577[52] && - !_theResult____h269577[51] && - !_theResult____h269577[50] && - !_theResult____h269577[49] && - !_theResult____h269577[48] && - !_theResult____h269577[47] && - !_theResult____h269577[46] && - !_theResult____h269577[45] && - !_theResult____h269577[44] && - !_theResult____h269577[43] && - !_theResult____h269577[42] && - !_theResult____h269577[41] && - !_theResult____h269577[40] && - !_theResult____h269577[39] && - !_theResult____h269577[38] && - !_theResult____h269577[37] && - !_theResult____h269577[36] && - !_theResult____h269577[35] && - !_theResult____h269577[34] && - !_theResult____h269577[33] && - !_theResult____h269577[32] && - !_theResult____h269577[31] && - !_theResult____h269577[30] && - !_theResult____h269577[29] && - !_theResult____h269577[28] && - !_theResult____h269577[27] && - !_theResult____h269577[26] && - !_theResult____h269577[25] && - !_theResult____h269577[24] && - !_theResult____h269577[23] && - !_theResult____h269577[22] && - !_theResult____h269577[21] && - !_theResult____h269577[20] && - !_theResult____h269577[19] && - !_theResult____h269577[18] && - !_theResult____h269577[17] && - !_theResult____h269577[16] && - !_theResult____h269577[15] && - !_theResult____h269577[14] && - !_theResult____h269577[13] && - !_theResult____h269577[12] && - !_theResult____h269577[11] && - !_theResult____h269577[10] && - !_theResult____h269577[9] && - !_theResult____h269577[8] && - !_theResult____h269577[7] && - !_theResult____h269577[6] && - !_theResult____h269577[5] && - !_theResult____h269577[4] && - !_theResult____h269577[3] && - !_theResult____h269577[2] && - !_theResult____h269577[1] && - !_theResult____h269577[0]) ? - _theResult____h269577 : - _theResult___snd__h277726 ; - assign _theResult___snd__h277726 = - { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_resWire_wget__ETC__q133[54:0], - 2'd0 } ; - assign _theResult___snd__h277749 = - _theResult____h269577 << - IF_IF_0b0_CONCAT_NOT_resWire_wget__410_BITS_67_ETC___d5767 ; - assign _theResult___snd__h286293 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___snd__h286302 : - _theResult___snd__h286295 ; - assign _theResult___snd__h286295 = { resWire$wget[56:5], 5'd0 } ; - assign _theResult___snd__h286302 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ? - sfd__h261975 : - _theResult___snd__h286308 ; - assign _theResult___snd__h286308 = - { IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q135[54:0], - 2'd0 } ; - assign _theResult___snd__h286331 = - sfd__h261975 << - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d5982 ; - assign _theResult___snd__h295463 = { _theResult____h287214[55:0], 1'd0 } ; - assign _theResult___snd__h295474 = - (!_theResult____h287214[56] && _theResult____h287214[55]) ? - _theResult___snd__h295476 : - _theResult___snd__h295486 ; - assign _theResult___snd__h295476 = { _theResult____h287214[54:0], 2'd0 } ; - assign _theResult___snd__h295486 = - (!_theResult____h287214[56] && !_theResult____h287214[55] && - !_theResult____h287214[54] && - !_theResult____h287214[53] && - !_theResult____h287214[52] && - !_theResult____h287214[51] && - !_theResult____h287214[50] && - !_theResult____h287214[49] && - !_theResult____h287214[48] && - !_theResult____h287214[47] && - !_theResult____h287214[46] && - !_theResult____h287214[45] && - !_theResult____h287214[44] && - !_theResult____h287214[43] && - !_theResult____h287214[42] && - !_theResult____h287214[41] && - !_theResult____h287214[40] && - !_theResult____h287214[39] && - !_theResult____h287214[38] && - !_theResult____h287214[37] && - !_theResult____h287214[36] && - !_theResult____h287214[35] && - !_theResult____h287214[34] && - !_theResult____h287214[33] && - !_theResult____h287214[32] && - !_theResult____h287214[31] && - !_theResult____h287214[30] && - !_theResult____h287214[29] && - !_theResult____h287214[28] && - !_theResult____h287214[27] && - !_theResult____h287214[26] && - !_theResult____h287214[25] && - !_theResult____h287214[24] && - !_theResult____h287214[23] && - !_theResult____h287214[22] && - !_theResult____h287214[21] && - !_theResult____h287214[20] && - !_theResult____h287214[19] && - !_theResult____h287214[18] && - !_theResult____h287214[17] && - !_theResult____h287214[16] && - !_theResult____h287214[15] && - !_theResult____h287214[14] && - !_theResult____h287214[13] && - !_theResult____h287214[12] && - !_theResult____h287214[11] && - !_theResult____h287214[10] && - !_theResult____h287214[9] && - !_theResult____h287214[8] && - !_theResult____h287214[7] && - !_theResult____h287214[6] && - !_theResult____h287214[5] && - !_theResult____h287214[4] && - !_theResult____h287214[3] && - !_theResult____h287214[2] && - !_theResult____h287214[1] && - !_theResult____h287214[0]) ? - _theResult____h287214 : - _theResult___snd__h295492 ; - assign _theResult___snd__h295492 = - { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_resWire_wget_ETC__q139[54:0], - 2'd0 } ; - assign _theResult___snd__h295515 = - _theResult____h287214 << - IF_IF_3970_MINUS_SEXT_resWire_wget__410_BITS_6_ETC___d6278 ; - assign _theResult___snd__h304083 = - (resWire$wget[67:57] == 11'd0) ? - _theResult___snd__h304097 : - _theResult___snd__h286295 ; - assign _theResult___snd__h304097 = - (resWire$wget[67:57] == 11'd0 && - NOT_resWire_wget__410_BIT_56_426_825_AND_NOT_r_ETC___d5927) ? - sfd__h261975 : - _theResult___snd__h304103 ; - assign _theResult___snd__h304103 = - { IF_0_CONCAT_IF_resWire_wget__410_BITS_67_TO_57_ETC__q142[54:0], - 2'd0 } ; - assign _theResult___snd__h304121 = - sfd__h261975 << - IF_SEXT_resWire_wget__410_BITS_67_TO_57_416_MI_ETC___d6332 ; - assign _theResult___snd__h34715 = - { fpu_div64_fState_S3$D_OUT[56:0], 1'd0 } ; - assign _theResult___snd__h42350 = { sfdin__h34118[56:0], 1'd0 } ; - assign _theResult___snd__h42365 = - (!sfdin__h34118[57] && sfdin__h34118[56]) ? - _theResult___snd__h42367 : - _theResult___snd__h42380 ; - assign _theResult___snd__h42367 = { sfdin__h34118[55:0], 2'd0 } ; - assign _theResult___snd__h42380 = - (!sfdin__h34118[57] && !sfdin__h34118[56] && - !sfdin__h34118[55] && - !sfdin__h34118[54] && - !sfdin__h34118[53] && - !sfdin__h34118[52] && - !sfdin__h34118[51] && - !sfdin__h34118[50] && - !sfdin__h34118[49] && - !sfdin__h34118[48] && - !sfdin__h34118[47] && - !sfdin__h34118[46] && - !sfdin__h34118[45] && - !sfdin__h34118[44] && - !sfdin__h34118[43] && - !sfdin__h34118[42] && - !sfdin__h34118[41] && - !sfdin__h34118[40] && - !sfdin__h34118[39] && - !sfdin__h34118[38] && - !sfdin__h34118[37] && - !sfdin__h34118[36] && - !sfdin__h34118[35] && - !sfdin__h34118[34] && - !sfdin__h34118[33] && - !sfdin__h34118[32] && - !sfdin__h34118[31] && - !sfdin__h34118[30] && - !sfdin__h34118[29] && - !sfdin__h34118[28] && - !sfdin__h34118[27] && - !sfdin__h34118[26] && - !sfdin__h34118[25] && - !sfdin__h34118[24] && - !sfdin__h34118[23] && - !sfdin__h34118[22] && - !sfdin__h34118[21] && - !sfdin__h34118[20] && - !sfdin__h34118[19] && - !sfdin__h34118[18] && - !sfdin__h34118[17] && - !sfdin__h34118[16] && - !sfdin__h34118[15] && - !sfdin__h34118[14] && - !sfdin__h34118[13] && - !sfdin__h34118[12] && - !sfdin__h34118[11] && - !sfdin__h34118[10] && - !sfdin__h34118[9] && - !sfdin__h34118[8] && - !sfdin__h34118[7] && - !sfdin__h34118[6] && - !sfdin__h34118[5] && - !sfdin__h34118[4] && - !sfdin__h34118[3] && - !sfdin__h34118[2] && - !sfdin__h34118[1] && - !sfdin__h34118[0]) ? - sfdin__h34118 : - _theResult___snd__h42386 ; - assign _theResult___snd__h42386 = - { IF_0_CONCAT_IF_IF_fpu_div64_fState_S3_first__8_ETC__q12[55:0], - 2'd0 } ; - assign _theResult___snd__h42404 = - sfdin__h34118 << - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d882 ; - assign _theResult___snd__h42409 = - sfdin__h34118 << - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d880 ; - assign _theResult___snd__h94767 = - { fpu_sqr64_fState_S3$D_OUT[57:0], 1'd0 } ; - assign _theResult___snd__h94782 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - fpu_sqr64_fState_S3$D_OUT[57]) ? - _theResult___snd__h94784 : - _theResult___snd__h94797 ; - assign _theResult___snd__h94784 = - { fpu_sqr64_fState_S3$D_OUT[56:0], 2'd0 } ; - assign _theResult___snd__h94797 = - (!fpu_sqr64_fState_S3$D_OUT[58] && - !fpu_sqr64_fState_S3$D_OUT[57] && - !fpu_sqr64_fState_S3$D_OUT[56] && - !fpu_sqr64_fState_S3$D_OUT[55] && - !fpu_sqr64_fState_S3$D_OUT[54] && - !fpu_sqr64_fState_S3$D_OUT[53] && - !fpu_sqr64_fState_S3$D_OUT[52] && - !fpu_sqr64_fState_S3$D_OUT[51] && - !fpu_sqr64_fState_S3$D_OUT[50] && - !fpu_sqr64_fState_S3$D_OUT[49] && - !fpu_sqr64_fState_S3$D_OUT[48] && - !fpu_sqr64_fState_S3$D_OUT[47] && - !fpu_sqr64_fState_S3$D_OUT[46] && - !fpu_sqr64_fState_S3$D_OUT[45] && - !fpu_sqr64_fState_S3$D_OUT[44] && - !fpu_sqr64_fState_S3$D_OUT[43] && - !fpu_sqr64_fState_S3$D_OUT[42] && - !fpu_sqr64_fState_S3$D_OUT[41] && - !fpu_sqr64_fState_S3$D_OUT[40] && - !fpu_sqr64_fState_S3$D_OUT[39] && - !fpu_sqr64_fState_S3$D_OUT[38] && - !fpu_sqr64_fState_S3$D_OUT[37] && - !fpu_sqr64_fState_S3$D_OUT[36] && - !fpu_sqr64_fState_S3$D_OUT[35] && - !fpu_sqr64_fState_S3$D_OUT[34] && - !fpu_sqr64_fState_S3$D_OUT[33] && - !fpu_sqr64_fState_S3$D_OUT[32] && - !fpu_sqr64_fState_S3$D_OUT[31] && - !fpu_sqr64_fState_S3$D_OUT[30] && - !fpu_sqr64_fState_S3$D_OUT[29] && - !fpu_sqr64_fState_S3$D_OUT[28] && - !fpu_sqr64_fState_S3$D_OUT[27] && - !fpu_sqr64_fState_S3$D_OUT[26] && - !fpu_sqr64_fState_S3$D_OUT[25] && - !fpu_sqr64_fState_S3$D_OUT[24] && - !fpu_sqr64_fState_S3$D_OUT[23] && - !fpu_sqr64_fState_S3$D_OUT[22] && - !fpu_sqr64_fState_S3$D_OUT[21] && - !fpu_sqr64_fState_S3$D_OUT[20] && - !fpu_sqr64_fState_S3$D_OUT[19] && - !fpu_sqr64_fState_S3$D_OUT[18] && - !fpu_sqr64_fState_S3$D_OUT[17] && - !fpu_sqr64_fState_S3$D_OUT[16] && - !fpu_sqr64_fState_S3$D_OUT[15] && - !fpu_sqr64_fState_S3$D_OUT[14] && - !fpu_sqr64_fState_S3$D_OUT[13] && - !fpu_sqr64_fState_S3$D_OUT[12] && - !fpu_sqr64_fState_S3$D_OUT[11] && - !fpu_sqr64_fState_S3$D_OUT[10] && - !fpu_sqr64_fState_S3$D_OUT[9] && - !fpu_sqr64_fState_S3$D_OUT[8] && - !fpu_sqr64_fState_S3$D_OUT[7] && - !fpu_sqr64_fState_S3$D_OUT[6] && - !fpu_sqr64_fState_S3$D_OUT[5] && - !fpu_sqr64_fState_S3$D_OUT[4] && - !fpu_sqr64_fState_S3$D_OUT[3] && - !fpu_sqr64_fState_S3$D_OUT[2] && - !fpu_sqr64_fState_S3$D_OUT[1] && - !fpu_sqr64_fState_S3$D_OUT[0]) ? - fpu_sqr64_fState_S3$D_OUT[58:0] : - _theResult___snd__h94803 ; - assign _theResult___snd__h94803 = - { IF_0_CONCAT_IF_fpu_sqr64_fState_S3_first__375__ETC__q19[56:0], - 2'd0 } ; - assign _theResult___snd__h94821 = - fpu_sqr64_fState_S3$D_OUT[58:0] << - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1632 ; - assign _theResult___snd__h94826 = - fpu_sqr64_fState_S3$D_OUT[58:0] << - IF_fpu_sqr64_fState_S3_first__375_BIT_58_384_T_ETC___d1630 ; - assign _theResult___snd_fst__h131051 = - { IF_sfdin30943_BIT_53_THEN_2_ELSE_0__q25[1], - { sfdin__h130943[52:0], 52'd0 } != 105'd0 } ; - assign _theResult___snd_fst__h141477 = - { IF_sfdin41369_BIT_4_THEN_2_ELSE_0__q30[1], - { sfdin__h141369[3:0], 52'd0 } != 56'd0 } ; - assign _theResult___snd_fst__h1478 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___snd_fst__h1602 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 ; - assign _theResult___snd_fst__h1517 = - (rg_res[116] || rg_b == 116'd0 || - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63) ? - rg_s : - s__h1658 ; - assign _theResult___snd_fst__h1602 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0 || - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 : - s__h1723 ; - assign _theResult___snd_fst__h42439 = - { IF_sfdin2327_BIT_5_THEN_2_ELSE_0__q13[1], - { sfdin__h42327[4:0], 52'd0 } != 57'd0 } ; - assign _theResult___snd_fst__h94856 = - { IF_sfdin4744_BIT_6_THEN_2_ELSE_0__q20[1], - { sfdin__h94744[5:0], 52'd0 } != 58'd0 } ; - assign _theResult___snd_fst_exp__h164065 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - 11'd0 : - _theResult___fst_exp__h164062 ; - assign _theResult___snd_fst_exp__h182407 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - _theResult___fst_exp__h173652 : - _theResult___fst_exp__h182404 ; - assign _theResult___snd_fst_exp__h202703 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - 11'd0 : - _theResult___fst_exp__h202700 ; - assign _theResult___snd_fst_exp__h221045 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - _theResult___fst_exp__h212290 : - _theResult___fst_exp__h221042 ; - assign _theResult___snd_fst_exp__h241642 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - 11'd0 : - _theResult___fst_exp__h241639 ; - assign _theResult___snd_fst_exp__h259984 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - _theResult___fst_exp__h251229 : - _theResult___fst_exp__h259981 ; - assign _theResult___snd_fst_exp__h286868 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _theResult___fst_exp__h278283 : - _theResult___fst_exp__h286865 ; - assign _theResult___snd_fst_exp__h304688 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _theResult___fst_exp__h296049 : - _theResult___fst_exp__h304685 ; - assign _theResult___snd_fst_exp__h31334 = - (IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d499) ? - 11'd0 : - value__h31374[10:0] ; - assign _theResult___snd_fst_exp__h31337 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 ? - _theResult___snd_fst_exp__h31334 : - 11'd2046 ; - assign _theResult___snd_fst_exp__h31361 = - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 ? - 11'd0 : - _theResult___snd_fst_exp__h31337 ; - assign _theResult___snd_fst_sfd__h144486 = - (iFifo$D_OUT[159:137] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h144235 ; - assign _theResult___snd_fst_sfd__h164066 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_15_ETC___d3190 ? - 52'd0 : - _theResult___fst_sfd__h164063 ; - assign _theResult___snd_fst_sfd__h182408 = - SEXT_iFifo_first__087_BITS_167_TO_160_130_MINU_ETC___d3325 ? - _theResult___fst_sfd__h173653 : - _theResult___fst_sfd__h182405 ; - assign _theResult___snd_fst_sfd__h183126 = - (iFifo$D_OUT[94:72] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h182875 ; - assign _theResult___snd_fst_sfd__h202704 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_94_ETC___d4685 ? - 52'd0 : - _theResult___fst_sfd__h202701 ; - assign _theResult___snd_fst_sfd__h221046 = - SEXT_iFifo_first__087_BITS_102_TO_95_625_MINUS_ETC___d4808 ? - _theResult___fst_sfd__h212291 : - _theResult___fst_sfd__h221043 ; - assign _theResult___snd_fst_sfd__h222065 = - (iFifo$D_OUT[29:7] == 23'd0) ? - 52'h4000000000000 : - out___1_sfd__h221814 ; - assign _theResult___snd_fst_sfd__h241643 = - _3970_MINUS_0_CONCAT_IF_iFifo_first__087_BIT_29_ETC___d3910 ? - 52'd0 : - _theResult___fst_sfd__h241640 ; - assign _theResult___snd_fst_sfd__h259985 = - SEXT_iFifo_first__087_BITS_37_TO_30_850_MINUS__ETC___d4033 ? - _theResult___fst_sfd__h251230 : - _theResult___fst_sfd__h259982 ; - assign _theResult___snd_fst_sfd__h261925 = - (resWire$wget[56:34] == 23'd0) ? - 23'd2097152 : - resWire$wget[56:34] ; - assign _theResult___snd_fst_sfd__h286869 = - _3074_MINUS_0_CONCAT_IF_resWire_wget__410_BIT_5_ETC___d5533 ? - _theResult___fst_sfd__h278284 : - _theResult___fst_sfd__h286866 ; - assign _theResult___snd_fst_sfd__h304689 = - SEXT_resWire_wget__410_BITS_67_TO_57_416_MINUS_ETC___d6033 ? - _theResult___fst_sfd__h296050 : - _theResult___fst_sfd__h304686 ; - assign _theResult___snd_fst_sfd__h31362 = - (fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353) ? - 52'd0 : - 52'hFFFFFFFFFFFFF ; - assign _theResult___snd_snd__h131371 = - (fpu_madd_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ; - assign _theResult___snd_snd__h1649 = - rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63 ? r__h1663 : r__h1659 ; - assign _theResult___snd_snd__h1715 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d85 ? - r__h1753 : - r__h1724 ; - assign _theResult___snd_snd_snd__h131369 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 ? - _theResult___snd_snd__h131371 : - guardBC__h115666 ; - assign _theResult___snd_snd_snd__h1481 = - IF_rg_index_1_4_ULE_58_8_THEN_NOT_rg_b_9_EQ_0__ETC___d56 ? - _theResult___snd_snd_snd__h1605 : - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 ; - assign _theResult___snd_snd_snd__h1520 = - (rg_res[116] || rg_b == 116'd0) ? - rg_r_1 : - _theResult___snd_snd__h1649 ; - assign _theResult___snd_snd_snd__h1605 = - (IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 == - 116'd0) ? - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 : - _theResult___snd_snd__h1715 ; - assign _theResult___snd_snd_snd__h33963 = - (fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - _theResult___snd__h34715 : - fpu_div64_fState_S3$D_OUT[57:0] ; - assign b___1__h77160 = 116'h40000000000000000000000000000 >> x__h85465 ; - assign b__h11457 = - (fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0) ? - (fpu_div64_fOperands_S0$D_OUT[54] ? - 6'd1 : - (fpu_div64_fOperands_S0$D_OUT[53] ? - 6'd2 : - (fpu_div64_fOperands_S0$D_OUT[52] ? - 6'd3 : - (fpu_div64_fOperands_S0$D_OUT[51] ? - 6'd4 : - (fpu_div64_fOperands_S0$D_OUT[50] ? - 6'd5 : - (fpu_div64_fOperands_S0$D_OUT[49] ? - 6'd6 : - (fpu_div64_fOperands_S0$D_OUT[48] ? - 6'd7 : - (fpu_div64_fOperands_S0$D_OUT[47] ? - 6'd8 : - (fpu_div64_fOperands_S0$D_OUT[46] ? - 6'd9 : - (fpu_div64_fOperands_S0$D_OUT[45] ? - 6'd10 : - (fpu_div64_fOperands_S0$D_OUT[44] ? - 6'd11 : - (fpu_div64_fOperands_S0$D_OUT[43] ? - 6'd12 : - (fpu_div64_fOperands_S0$D_OUT[42] ? - 6'd13 : - (fpu_div64_fOperands_S0$D_OUT[41] ? - 6'd14 : - (fpu_div64_fOperands_S0$D_OUT[40] ? - 6'd15 : - (fpu_div64_fOperands_S0$D_OUT[39] ? - 6'd16 : - (fpu_div64_fOperands_S0$D_OUT[38] ? - 6'd17 : - (fpu_div64_fOperands_S0$D_OUT[37] ? - 6'd18 : - (fpu_div64_fOperands_S0$D_OUT[36] ? - 6'd19 : - (fpu_div64_fOperands_S0$D_OUT[35] ? - 6'd20 : - (fpu_div64_fOperands_S0$D_OUT[34] ? - 6'd21 : - (fpu_div64_fOperands_S0$D_OUT[33] ? - 6'd22 : - (fpu_div64_fOperands_S0$D_OUT[32] ? - 6'd23 : - (fpu_div64_fOperands_S0$D_OUT[31] ? - 6'd24 : - (fpu_div64_fOperands_S0$D_OUT[30] ? - 6'd25 : - (fpu_div64_fOperands_S0$D_OUT[29] ? - 6'd26 : - (fpu_div64_fOperands_S0$D_OUT[28] ? - 6'd27 : - (fpu_div64_fOperands_S0$D_OUT[27] ? - 6'd28 : - (fpu_div64_fOperands_S0$D_OUT[26] ? - 6'd29 : - (fpu_div64_fOperands_S0$D_OUT[25] ? - 6'd30 : - (fpu_div64_fOperands_S0$D_OUT[24] ? - 6'd31 : - (fpu_div64_fOperands_S0$D_OUT[23] ? - 6'd32 : - (fpu_div64_fOperands_S0$D_OUT[22] ? - 6'd33 : - (fpu_div64_fOperands_S0$D_OUT[21] ? - 6'd34 : - (fpu_div64_fOperands_S0$D_OUT[20] ? - 6'd35 : - (fpu_div64_fOperands_S0$D_OUT[19] ? - 6'd36 : - (fpu_div64_fOperands_S0$D_OUT[18] ? - 6'd37 : - (fpu_div64_fOperands_S0$D_OUT[17] ? - 6'd38 : - (fpu_div64_fOperands_S0$D_OUT[16] ? - 6'd39 : - (fpu_div64_fOperands_S0$D_OUT[15] ? - 6'd40 : - (fpu_div64_fOperands_S0$D_OUT[14] ? - 6'd41 : - (fpu_div64_fOperands_S0$D_OUT[13] ? - 6'd42 : - (fpu_div64_fOperands_S0$D_OUT[12] ? - 6'd43 : - (fpu_div64_fOperands_S0$D_OUT[11] ? - 6'd44 : - (fpu_div64_fOperands_S0$D_OUT[10] ? - 6'd45 : - (fpu_div64_fOperands_S0$D_OUT[9] ? - 6'd46 : - (fpu_div64_fOperands_S0$D_OUT[8] ? - 6'd47 : - (fpu_div64_fOperands_S0$D_OUT[7] ? - 6'd48 : - (fpu_div64_fOperands_S0$D_OUT[6] ? - 6'd49 : - (fpu_div64_fOperands_S0$D_OUT[5] ? - 6'd50 : - (fpu_div64_fOperands_S0$D_OUT[4] ? - 6'd51 : - (fpu_div64_fOperands_S0$D_OUT[3] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign b__h1608 = { 2'd0, rg_b[115:2] } ; - assign b__h1712 = - { 2'd0, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49[115:2] } ; - assign b__h32583 = { rg_d, 58'd0 } ; - assign b__h4039 = - (fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0) ? - (fpu_div64_fOperands_S0$D_OUT[118] ? - 6'd1 : - (fpu_div64_fOperands_S0$D_OUT[117] ? - 6'd2 : - (fpu_div64_fOperands_S0$D_OUT[116] ? - 6'd3 : - (fpu_div64_fOperands_S0$D_OUT[115] ? - 6'd4 : - (fpu_div64_fOperands_S0$D_OUT[114] ? - 6'd5 : - (fpu_div64_fOperands_S0$D_OUT[113] ? - 6'd6 : - (fpu_div64_fOperands_S0$D_OUT[112] ? - 6'd7 : - (fpu_div64_fOperands_S0$D_OUT[111] ? - 6'd8 : - (fpu_div64_fOperands_S0$D_OUT[110] ? - 6'd9 : - (fpu_div64_fOperands_S0$D_OUT[109] ? - 6'd10 : - (fpu_div64_fOperands_S0$D_OUT[108] ? - 6'd11 : - (fpu_div64_fOperands_S0$D_OUT[107] ? - 6'd12 : - (fpu_div64_fOperands_S0$D_OUT[106] ? - 6'd13 : - (fpu_div64_fOperands_S0$D_OUT[105] ? - 6'd14 : - (fpu_div64_fOperands_S0$D_OUT[104] ? - 6'd15 : - (fpu_div64_fOperands_S0$D_OUT[103] ? - 6'd16 : - (fpu_div64_fOperands_S0$D_OUT[102] ? - 6'd17 : - (fpu_div64_fOperands_S0$D_OUT[101] ? - 6'd18 : - (fpu_div64_fOperands_S0$D_OUT[100] ? - 6'd19 : - (fpu_div64_fOperands_S0$D_OUT[99] ? - 6'd20 : - (fpu_div64_fOperands_S0$D_OUT[98] ? - 6'd21 : - (fpu_div64_fOperands_S0$D_OUT[97] ? - 6'd22 : - (fpu_div64_fOperands_S0$D_OUT[96] ? - 6'd23 : - (fpu_div64_fOperands_S0$D_OUT[95] ? - 6'd24 : - (fpu_div64_fOperands_S0$D_OUT[94] ? - 6'd25 : - (fpu_div64_fOperands_S0$D_OUT[93] ? - 6'd26 : - (fpu_div64_fOperands_S0$D_OUT[92] ? - 6'd27 : - (fpu_div64_fOperands_S0$D_OUT[91] ? - 6'd28 : - (fpu_div64_fOperands_S0$D_OUT[90] ? - 6'd29 : - (fpu_div64_fOperands_S0$D_OUT[89] ? - 6'd30 : - (fpu_div64_fOperands_S0$D_OUT[88] ? - 6'd31 : - (fpu_div64_fOperands_S0$D_OUT[87] ? - 6'd32 : - (fpu_div64_fOperands_S0$D_OUT[86] ? - 6'd33 : - (fpu_div64_fOperands_S0$D_OUT[85] ? - 6'd34 : - (fpu_div64_fOperands_S0$D_OUT[84] ? - 6'd35 : - (fpu_div64_fOperands_S0$D_OUT[83] ? - 6'd36 : - (fpu_div64_fOperands_S0$D_OUT[82] ? - 6'd37 : - (fpu_div64_fOperands_S0$D_OUT[81] ? - 6'd38 : - (fpu_div64_fOperands_S0$D_OUT[80] ? - 6'd39 : - (fpu_div64_fOperands_S0$D_OUT[79] ? - 6'd40 : - (fpu_div64_fOperands_S0$D_OUT[78] ? - 6'd41 : - (fpu_div64_fOperands_S0$D_OUT[77] ? - 6'd42 : - (fpu_div64_fOperands_S0$D_OUT[76] ? - 6'd43 : - (fpu_div64_fOperands_S0$D_OUT[75] ? - 6'd44 : - (fpu_div64_fOperands_S0$D_OUT[74] ? - 6'd45 : - (fpu_div64_fOperands_S0$D_OUT[73] ? - 6'd46 : - (fpu_div64_fOperands_S0$D_OUT[72] ? - 6'd47 : - (fpu_div64_fOperands_S0$D_OUT[71] ? - 6'd48 : - (fpu_div64_fOperands_S0$D_OUT[70] ? - 6'd49 : - (fpu_div64_fOperands_S0$D_OUT[69] ? - 6'd50 : - (fpu_div64_fOperands_S0$D_OUT[68] ? - 6'd51 : - (fpu_div64_fOperands_S0$D_OUT[67] ? - 6'd52 : - 6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) : - 6'd0 ; - assign din_exp30866_MINUS_1023__q23 = din_exp__h130866 - 11'd1023 ; - assign din_exp__h130866 = - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ? - value__h130883[10:0] : - 11'd0 ; - assign din_inc___2_exp__h142626 = fpu_madd_fState_S8$D_OUT[65:55] + 11'd1 ; - assign din_inc___2_exp__h182469 = _theResult___fst_exp__h163336 + 11'd1 ; - assign din_inc___2_exp__h182504 = _theResult___fst_exp__h172852 + 11'd1 ; - assign din_inc___2_exp__h182530 = _theResult___fst_exp__h181653 + 11'd1 ; - assign din_inc___2_exp__h221107 = _theResult___fst_exp__h201974 + 11'd1 ; - assign din_inc___2_exp__h221142 = _theResult___fst_exp__h211490 + 11'd1 ; - assign din_inc___2_exp__h221168 = _theResult___fst_exp__h220291 + 11'd1 ; - assign din_inc___2_exp__h260046 = _theResult___fst_exp__h240913 + 11'd1 ; - assign din_inc___2_exp__h260081 = _theResult___fst_exp__h250429 + 11'd1 ; - assign din_inc___2_exp__h260107 = _theResult___fst_exp__h259230 + 11'd1 ; - assign din_inc___2_exp__h304723 = _theResult___fst_exp__h277686 + 8'd1 ; - assign din_inc___2_exp__h304749 = _theResult___fst_exp__h286342 + 8'd1 ; - assign din_inc___2_exp__h304784 = _theResult___fst_exp__h295452 + 8'd1 ; - assign din_inc___2_exp__h304810 = _theResult___fst_exp__h304137 + 8'd1 ; - assign din_inc___2_exp__h43566 = fpu_div64_fState_S4$D_OUT[64:54] + 11'd1 ; - assign din_inc___2_exp__h96000 = fpu_sqr64_fState_S4$D_OUT[64:54] + 11'd1 ; - assign exp__h304706 = - (resWire$wget[67:57] == 11'd2047) ? - 8'd255 : - _theResult___fst_exp__h304697 ; - assign fpu_div64_fOperands_S0D_OUT_BITS_129_TO_119_M_ETC__q7 = - fpu_div64_fOperands_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_div64_fOperands_S0D_OUT_BITS_65_TO_55_MIN_ETC__q8 = - fpu_div64_fOperands_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d436 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 && - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d498 = - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] != 52'd0 && - !fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54] || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d401 ; - assign fpu_div64_fOperands_S0_first__06_BITS_65_TO_55_ETC___d359 = - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[129:119] == 11'd0 && - fpu_div64_fOperands_S0$D_OUT[118:67] == 52'd0 || - fpu_div64_fOperands_S0$D_OUT[65:55] == 11'd2047 && - fpu_div64_fOperands_S0$D_OUT[54:3] == 52'd0 || - !IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d353 || - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d355 ; - assign fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 = - fpu_div64_fOperands_S0$D_OUT[130] == - fpu_div64_fOperands_S0$D_OUT[66] ; - assign fpu_div64_fState_S3_first__86_BIT_121_07_CONCA_ETC___d936 = - { fpu_div64_fState_S3$D_OUT[121], - IF_fpu_div64_fState_S3_first__86_BITS_120_TO_1_ETC___d597 ? - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d929 : - ((fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - ((fpu_div64_fState_S3$D_OUT[57:56] == 2'b0) ? - { _theResult___fst_exp__h42284, - fpu_div64_fState_S3$D_OUT[109:58] } : - 63'h7FEFFFFFFFFFFFFF) : - fpu_div64_fState_S3$D_OUT[120:58]) } ; - assign fpu_madd_fOperand_S0D_OUT_BITS_129_TO_119_MIN_ETC__q128 = - fpu_madd_fOperand_S0$D_OUT[129:119] - 11'd1023 ; - assign fpu_madd_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_ETC__q129 = - fpu_madd_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1857 = - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 || - x__h96539 == 11'd0 && _theResult___fst_sfd__h96608 == 52'd0 && - (fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0) && - fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 ; - assign fpu_madd_fOperand_S0_first__803_BITS_129_TO_11_ETC___d1926 = - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 || - fpu_madd_fOperand_S0$D_OUT[129:119] == 11'd0 && - fpu_madd_fOperand_S0$D_OUT[118:67] == 52'd0 && - fpu_madd_fOperand_S0$D_OUT[65:55] == 11'd2047 && - fpu_madd_fOperand_S0$D_OUT[54:3] == 52'd0 ; - assign fpu_madd_fOperand_S0_first__803_BIT_195_804_AN_ETC___d1855 = - (fpu_madd_fOperand_S0$D_OUT[195] && - fpu_madd_fOperand_S0$D_OUT[194]) == - NOT_fpu_madd_fOperand_S0_first__803_BIT_130_85_ETC___d1854 ; - assign fpu_madd_fProd_S3_first__009_SRL_IF_7170_MINUS_ETC___d2012 = - fpu_madd_fProd_S3$D_OUT >> - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ; - assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 = - (fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ; - assign fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2004 = - (fpu_madd_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ; - assign fpu_madd_fState_S3_first__995_BITS_86_TO_82_00_ETC___d2501 = - fpu_madd_fState_S3$D_OUT[86:82] | - { 2'd0, - sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023, - _theResult___fst_exp__h130952 == 11'd0 && - guardBC__h115666 != 2'd0, - sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023 } ; - assign fpu_madd_fState_S4D_OUT_BITS_128_TO_118_MINUS_ETC__q27 = - fpu_madd_fState_S4$D_OUT[128:118] - 11'd1023 ; - assign fpu_madd_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q26 = - fpu_madd_fState_S4$D_OUT[64:54] - 11'd1023 ; - assign fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615 = - fpu_madd_fState_S5$D_OUT[56:0] >> - fpu_madd_fState_S5$D_OUT[126:114] ; - assign fpu_madd_fState_S7_first__651_BITS_137_TO_133__ETC___d2942 = - fpu_madd_fState_S7$D_OUT[137:133] | - { 2'd0, - sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023, - _theResult___fst_exp__h141378 == 11'd0 && - guard__h133123 != 2'd0, - sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023 } ; - assign fpu_madd_fState_S8_first__960_BITS_75_TO_71_03_ETC___d3043 = - fpu_madd_fState_S8$D_OUT[75:71] | - { 2'd0, - IF_fpu_madd_fState_S8_first__960_BITS_65_TO_55_ETC___d3011 == - 11'd2047 && - ((fpu_madd_fState_S8$D_OUT[65:55] == 11'd2047) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___fst_sfd__h142620) == - 52'd0, - 1'd0, - fpu_madd_fState_S8$D_OUT[65:55] != 11'd2047 && - fpu_madd_fState_S8$D_OUT[2:1] != 2'b0 } ; - assign fpu_sqr64_fOperand_S0D_OUT_BITS_65_TO_55_MINU_ETC__q16 = - fpu_sqr64_fOperand_S0$D_OUT[65:55] - 11'd1023 ; - assign fpu_sqr64_fState_S3D_OUT_BITS_121_TO_111_MINU_ETC__q18 = - fpu_sqr64_fState_S3$D_OUT[121:111] - 11'd1023 ; - assign guardBC__h115666 = - (sfdBC__h115662[105] && - IF_IF_7170_MINUS_fpu_madd_fState_S3_first__995_ETC___d2031 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h131051 ; - assign guard__h132367 = fpu_madd_fState_S5$D_OUT[56:0] << x__h132471 ; - assign guard__h133123 = - (sfd__h133119[56] && - IF_fpu_madd_fState_S7_first__651_BITS_126_TO_1_ETC___d2668 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h141477 ; - assign guard__h155375 = - { IF_theResult___snd63287_BIT_4_THEN_2_ELSE_0__q34[1], - { _theResult___snd__h163287[3:0], 52'd0 } != 56'd0 } ; - assign guard__h164624 = - { IF_sfdin72846_BIT_4_THEN_2_ELSE_0__q38[1], - { sfdin__h172846[3:0], 52'd0 } != 56'd0 } ; - assign guard__h165222 = x__h165324 != 57'd0 ; - assign guard__h173663 = - { IF_theResult___snd81599_BIT_4_THEN_2_ELSE_0__q41[1], - { _theResult___snd__h181599[3:0], 52'd0 } != 56'd0 } ; - assign guard__h194013 = - { IF_theResult___snd01925_BIT_4_THEN_2_ELSE_0__q94[1], - { _theResult___snd__h201925[3:0], 52'd0 } != 56'd0 } ; - assign guard__h203262 = - { IF_sfdin11484_BIT_4_THEN_2_ELSE_0__q98[1], - { sfdin__h211484[3:0], 52'd0 } != 56'd0 } ; - assign guard__h203860 = x__h203962 != 57'd0 ; - assign guard__h212301 = - { IF_theResult___snd20237_BIT_4_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h220237[3:0], 52'd0 } != 56'd0 } ; - assign guard__h232952 = - { IF_theResult___snd40864_BIT_4_THEN_2_ELSE_0__q61[1], - { _theResult___snd__h240864[3:0], 52'd0 } != 56'd0 } ; - assign guard__h242201 = - { IF_sfdin50423_BIT_4_THEN_2_ELSE_0__q65[1], - { sfdin__h250423[3:0], 52'd0 } != 56'd0 } ; - assign guard__h242799 = x__h242901 != 57'd0 ; - assign guard__h251240 = - { IF_theResult___snd59176_BIT_4_THEN_2_ELSE_0__q68[1], - { _theResult___snd__h259176[3:0], 52'd0 } != 56'd0 } ; - assign guard__h269587 = - { IF_sfdin77680_BIT_33_THEN_2_ELSE_0__q134[1], - { sfdin__h277680[32:0], 23'd0 } != 56'd0 } ; - assign guard__h278294 = - { IF_theResult___snd86293_BIT_33_THEN_2_ELSE_0__q136[1], - { _theResult___snd__h286293[32:0], 23'd0 } != 56'd0 } ; - assign guard__h287224 = - { IF_sfdin95446_BIT_33_THEN_2_ELSE_0__q140[1], - { sfdin__h295446[32:0], 23'd0 } != 56'd0 } ; - assign guard__h287822 = x__h287924 != 57'd0 ; - assign guard__h296060 = - { IF_theResult___snd04083_BIT_33_THEN_2_ELSE_0__q143[1], - { _theResult___snd__h304083[32:0], 23'd0 } != 56'd0 } ; - assign guard__h33946 = x__h42705 ; - assign guard__h86435 = x__h95138 ; - assign iFifoD_OUT_BITS_102_TO_95_MINUS_127__q95 = - iFifo$D_OUT[102:95] - 8'd127 ; - assign iFifoD_OUT_BITS_167_TO_160_MINUS_127__q35 = - iFifo$D_OUT[167:160] - 8'd127 ; - assign iFifoD_OUT_BITS_37_TO_30_MINUS_127__q62 = - iFifo$D_OUT[37:30] - 8'd127 ; - assign out___1_sfd__h144235 = { iFifo$D_OUT[159:137], 29'd0 } ; - assign out___1_sfd__h182875 = { iFifo$D_OUT[94:72], 29'd0 } ; - assign out___1_sfd__h221814 = { iFifo$D_OUT[29:7], 29'd0 } ; - assign out_exp__h142544 = - fpu_madd_fState_S8$D_OUT[3] ? - _theResult___exp__h142541 : - fpu_madd_fState_S8$D_OUT[65:55] ; - assign out_exp__h163984 = - _theResult___snd__h163287[5] ? - _theResult___exp__h163981 : - _theResult___fst_exp__h163336 ; - assign out_exp__h173574 = - sfdin__h172846[5] ? - _theResult___exp__h173571 : - _theResult___fst_exp__h172852 ; - assign out_exp__h182326 = - _theResult___snd__h181599[5] ? - _theResult___exp__h182323 : - _theResult___fst_exp__h181653 ; - assign out_exp__h202622 = - _theResult___snd__h201925[5] ? - _theResult___exp__h202619 : - _theResult___fst_exp__h201974 ; - assign out_exp__h212212 = - sfdin__h211484[5] ? - _theResult___exp__h212209 : - _theResult___fst_exp__h211490 ; - assign out_exp__h220964 = - _theResult___snd__h220237[5] ? - _theResult___exp__h220961 : - _theResult___fst_exp__h220291 ; - assign out_exp__h241561 = - _theResult___snd__h240864[5] ? - _theResult___exp__h241558 : - _theResult___fst_exp__h240913 ; - assign out_exp__h251151 = - sfdin__h250423[5] ? - _theResult___exp__h251148 : - _theResult___fst_exp__h250429 ; - assign out_exp__h259903 = - _theResult___snd__h259176[5] ? - _theResult___exp__h259900 : - _theResult___fst_exp__h259230 ; - assign out_exp__h278205 = - sfdin__h277680[34] ? - _theResult___exp__h278202 : - _theResult___fst_exp__h277686 ; - assign out_exp__h286787 = - _theResult___snd__h286293[34] ? - _theResult___exp__h286784 : - _theResult___fst_exp__h286342 ; - assign out_exp__h295971 = - sfdin__h295446[34] ? - _theResult___exp__h295968 : - _theResult___fst_exp__h295452 ; - assign out_exp__h304607 = - _theResult___snd__h304083[34] ? - _theResult___exp__h304604 : - _theResult___fst_exp__h304137 ; - assign out_exp__h43478 = - fpu_div64_fState_S4$D_OUT[2] ? - _theResult___exp__h43475 : - fpu_div64_fState_S4$D_OUT[64:54] ; - assign out_exp__h95912 = - fpu_sqr64_fState_S4$D_OUT[2] ? - _theResult___exp__h95909 : - fpu_sqr64_fState_S4$D_OUT[64:54] ; - assign out_sfd__h142545 = - fpu_madd_fState_S8$D_OUT[3] ? - _theResult___sfd__h142542 : - fpu_madd_fState_S8$D_OUT[54:3] ; - assign out_sfd__h163985 = - _theResult___snd__h163287[5] ? - _theResult___sfd__h163982 : - _theResult___snd__h163287[56:5] ; - assign out_sfd__h173575 = - sfdin__h172846[5] ? - _theResult___sfd__h173572 : - sfdin__h172846[56:5] ; - assign out_sfd__h182327 = - _theResult___snd__h181599[5] ? - _theResult___sfd__h182324 : - _theResult___snd__h181599[56:5] ; - assign out_sfd__h202623 = - _theResult___snd__h201925[5] ? - _theResult___sfd__h202620 : - _theResult___snd__h201925[56:5] ; - assign out_sfd__h212213 = - sfdin__h211484[5] ? - _theResult___sfd__h212210 : - sfdin__h211484[56:5] ; - assign out_sfd__h220965 = - _theResult___snd__h220237[5] ? - _theResult___sfd__h220962 : - _theResult___snd__h220237[56:5] ; - assign out_sfd__h241562 = - _theResult___snd__h240864[5] ? - _theResult___sfd__h241559 : - _theResult___snd__h240864[56:5] ; - assign out_sfd__h251152 = - sfdin__h250423[5] ? - _theResult___sfd__h251149 : - sfdin__h250423[56:5] ; - assign out_sfd__h259904 = - _theResult___snd__h259176[5] ? - _theResult___sfd__h259901 : - _theResult___snd__h259176[56:5] ; - assign out_sfd__h278206 = - sfdin__h277680[34] ? - _theResult___sfd__h278203 : - sfdin__h277680[56:34] ; - assign out_sfd__h286788 = - _theResult___snd__h286293[34] ? - _theResult___sfd__h286785 : - _theResult___snd__h286293[56:34] ; - assign out_sfd__h295972 = - sfdin__h295446[34] ? - _theResult___sfd__h295969 : - sfdin__h295446[56:34] ; - assign out_sfd__h304608 = - _theResult___snd__h304083[34] ? - _theResult___sfd__h304605 : - _theResult___snd__h304083[56:34] ; - assign out_sfd__h43479 = - fpu_div64_fState_S4$D_OUT[2] ? - _theResult___sfd__h43476 : - fpu_div64_fState_S4$D_OUT[53:2] ; - assign out_sfd__h95913 = - fpu_sqr64_fState_S4$D_OUT[2] ? - _theResult___sfd__h95910 : - fpu_sqr64_fState_S4$D_OUT[53:2] ; - assign r__h1659 = r__h1663 + rg_b ; - assign r__h1663 = { 1'd0, rg_r_1[115:1] } ; - assign r__h1724 = - r__h1753 + - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign r__h1753 = - { 1'd0, - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69[115:1] } ; - assign resWire_wget__410_BITS_4_TO_0_658_OR_NOT_resWi_ETC___d6768 = - resWire$wget[4:0] | - { (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6709, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6720, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6736, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6749, - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] == 52'd0) && - (resWire$wget[67:57] != 11'd2047 || - resWire$wget[56:5] != 52'd0) && - (resWire$wget[67:57] != 11'd0 || - resWire$wget[56:5] != 52'd0) && - IF_resWire_wget__410_BITS_67_TO_57_416_EQ_0_42_ETC___d6762 } ; - assign resWirewget_BITS_67_TO_57_MINUS_1023__q137 = - resWire$wget[67:57] - 11'd1023 ; - assign result__h132372 = - { fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[56:1], - fpu_madd_fState_S5_first__601_BITS_56_TO_0_610_ETC___d2615[0] | - guard__h132367 != 57'd0 } ; - assign result__h165227 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_167_TO_16_ETC___d3330[0] | - guard__h165222 } ; - assign result__h203865 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_102_TO_95_ETC___d4813[0] | - guard__h203860 } ; - assign result__h242804 = - { _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[56:1], - _0b0_CONCAT_NOT_iFifo_first__087_BITS_37_TO_30__ETC___d4038[0] | - guard__h242799 } ; - assign result__h287827 = - { _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[56:1], - _0b0_CONCAT_NOT_resWire_wget__410_BITS_67_TO_57_ETC___d6038[0] | - guard__h287822 } ; - assign result__h32617 = { _theResult____h32523[57:1], 1'd1 } ; - assign result__h32648 = - { 1'd0, - value__h32661[56:1], - value__h32661[0] | sfdlsb__h32643 } ; - assign result__h32823 = - (IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] == - 57'd0) ? - 58'd0 : - 58'd1 ; - assign result__h85925 = { x__h85931[58:1], 1'd1 } ; - assign rg_index_1_4_PLUS_1_6_ULE_58___d37 = rg_index_1 + 6'd1 <= 6'd58 ; - assign rg_index_1_4_ULE_58___d38 = rg_index_1 <= 6'd58 ; - assign rg_index_PLUS_1_ULE_57___d6 = rg_index + 6'd1 <= 6'd57 ; - assign rg_index_ULE_57___d7 = rg_index <= 6'd57 ; - assign rg_q_PLUS_NEG_INV_rg_q_59_60___d561 = rg_q + -(~rg_q) ; - assign rg_s_1_ULT_rg_r_1_0_PLUS_rg_b_9_2___d63 = rg_s < sum__h1606 ; - assign s__h1658 = rg_s - sum__h1606 ; - assign s__h1723 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d83 - - sum__h1710 ; - assign sfdA__h131577 = - { 1'b0, - fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } ; - assign sfdA__h2035 = - { fpu_div64_fOperands_S0$D_OUT[129:119] != 11'd0, - fpu_div64_fOperands_S0$D_OUT[118:67] } ; - assign sfdA__h2039 = sfdA__h2035 << b__h4039 ; - assign sfdBC__h115662 = - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2008 ? - fpu_madd_fProd_S3$D_OUT : - _theResult___fst__h116827 ; - assign sfdBC__h131578 = - { 1'b0, - fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } ; - assign sfdB__h2036 = - { fpu_div64_fOperands_S0$D_OUT[65:55] != 11'd0, - fpu_div64_fOperands_S0$D_OUT[54:3] } ; - assign sfdB__h2041 = sfdB__h2036 << b__h11457 ; - assign sfd___1__h60702 = { 1'd0, sfd__h44953[57:1] } ; - assign sfd__h133119 = - fpu_madd_fState_S7$D_OUT[128] ? - fpu_madd_fState_S7$D_OUT[56:0] : - fpu_madd_fState_S7$D_OUT[113:57] ; - assign sfd__h142040 = - { 1'b0, - fpu_madd_fState_S8$D_OUT[65:55] != 11'd0, - fpu_madd_fState_S8$D_OUT[54:3] } + - 54'd1 ; - assign sfd__h144536 = { value__h148923, 32'd0 } ; - assign sfd__h163354 = - { 1'b0, - _theResult___fst_exp__h163336 != 11'd0, - _theResult___snd__h163287[56:5] } + - 54'd1 ; - assign sfd__h172944 = - { 1'b0, - _theResult___fst_exp__h172852 != 11'd0, - sfdin__h172846[56:5] } + - 54'd1 ; - assign sfd__h181672 = - { 1'b0, - _theResult___fst_exp__h181653 != 11'd0, - _theResult___snd__h181599[56:5] } + - 54'd1 ; - assign sfd__h183176 = { value__h187561, 32'd0 } ; - assign sfd__h18934 = { 1'd1, fpu_div64_fOperands_S0$D_OUT[117:67] } ; - assign sfd__h18937 = { 1'd1, fpu_div64_fOperands_S0$D_OUT[53:3] } ; - assign sfd__h201992 = - { 1'b0, - _theResult___fst_exp__h201974 != 11'd0, - _theResult___snd__h201925[56:5] } + - 54'd1 ; - assign sfd__h211582 = - { 1'b0, - _theResult___fst_exp__h211490 != 11'd0, - sfdin__h211484[56:5] } + - 54'd1 ; - assign sfd__h220310 = - { 1'b0, - _theResult___fst_exp__h220291 != 11'd0, - _theResult___snd__h220237[56:5] } + - 54'd1 ; - assign sfd__h222115 = { value__h226500, 32'd0 } ; - assign sfd__h240931 = - { 1'b0, - _theResult___fst_exp__h240913 != 11'd0, - _theResult___snd__h240864[56:5] } + - 54'd1 ; - assign sfd__h250521 = - { 1'b0, - _theResult___fst_exp__h250429 != 11'd0, - sfdin__h250423[56:5] } + - 54'd1 ; - assign sfd__h259249 = - { 1'b0, - _theResult___fst_exp__h259230 != 11'd0, - _theResult___snd__h259176[56:5] } + - 54'd1 ; - assign sfd__h261975 = { value__h270197, 3'd0 } ; - assign sfd__h277778 = - { 1'b0, - _theResult___fst_exp__h277686 != 8'd0, - sfdin__h277680[56:34] } + - 25'd1 ; - assign sfd__h286360 = - { 1'b0, - _theResult___fst_exp__h286342 != 8'd0, - _theResult___snd__h286293[56:34] } + - 25'd1 ; - assign sfd__h295544 = - { 1'b0, - _theResult___fst_exp__h295452 != 8'd0, - sfdin__h295446[56:34] } + - 25'd1 ; - assign sfd__h304156 = - { 1'b0, - _theResult___fst_exp__h304137 != 8'd0, - _theResult___snd__h304083[56:34] } + - 25'd1 ; - assign sfd__h304707 = - (resWire$wget[67:57] == 11'd2047 && - resWire$wget[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h261925 : - _theResult___fst_sfd__h304701 ; - assign sfd__h42982 = - { 1'b0, - fpu_div64_fState_S4$D_OUT[64:54] != 11'd0, - fpu_div64_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfd__h44951 = { value__h53174, 4'd0 } ; - assign sfd__h44953 = sfd__h44951 << x__h60732 ; - assign sfd__h45004 = { 1'd1, fpu_sqr64_fOperand_S0$D_OUT[53:3] } ; - assign sfd__h95416 = - { 1'b0, - fpu_sqr64_fState_S4$D_OUT[64:54] != 11'd0, - fpu_sqr64_fState_S4$D_OUT[53:2] } + - 54'd1 ; - assign sfd__h99402 = { 1'd1, _theResult___fst_sfd__h96608[50:0] } ; - assign sfd__h99405 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[117:67] } ; - assign sfd__h99408 = { 1'd1, fpu_madd_fOperand_S0$D_OUT[53:3] } ; - assign sfdin__h130943 = - sfdBC__h115662[105] ? - _theResult___snd__h130966 : - _theResult___snd__h130980 ; - assign sfdin__h141369 = - sfd__h133119[56] ? - _theResult___snd__h141392 : - _theResult___snd__h141406 ; - assign sfdin__h172846 = - _theResult____h164614[56] ? - _theResult___snd__h172863 : - _theResult___snd__h172874 ; - assign sfdin__h211484 = - _theResult____h203252[56] ? - _theResult___snd__h211501 : - _theResult___snd__h211512 ; - assign sfdin__h250423 = - _theResult____h242191[56] ? - _theResult___snd__h250440 : - _theResult___snd__h250451 ; - assign sfdin__h277680 = - _theResult____h269577[56] ? - _theResult___snd__h277697 : - _theResult___snd__h277708 ; - assign sfdin__h295446 = - _theResult____h287214[56] ? - _theResult___snd__h295463 : - _theResult___snd__h295474 ; - assign sfdin__h34118 = - (fpu_div64_fState_S3$D_OUT[120:110] == 11'd2047) ? - _theResult___snd_snd_snd__h33963 : - fpu_div64_fState_S3$D_OUT[57:0] ; - assign sfdin__h42327 = - sfdin__h34118[57] ? - _theResult___snd__h42350 : - _theResult___snd__h42365 ; - assign sfdin__h94744 = - fpu_sqr64_fState_S3$D_OUT[58] ? - _theResult___snd__h94767 : - _theResult___snd__h94782 ; - assign sfdlsb__h116825 = x__h116896 != 106'd0 ; - assign sfdlsb__h32643 = x__h32762 != 58'd0 ; - assign sum__h1606 = rg_r_1 + rg_b ; - assign sum__h1710 = - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d69 + - IF_rg_index_1_4_ULE_58_8_THEN_IF_rg_res_1_BIT__ETC___d49 ; - assign theResult___fst_exp2290_MINUS_1023__q11 = - _theResult___fst_exp__h42290 - 11'd1023 ; - assign value41307_BITS_10_TO_0_MINUS_1023__q28 = - value__h141307[10:0] - 11'd1023 ; - assign value_BIT_52___h53270 = fpu_sqr64_fOperand_S0$D_OUT[65:55] != 11'd0 ; - assign value__h130883 = fpu_madd_fState_S3$D_OUT[12:0] + 13'd1023 ; - assign value__h141307 = fpu_madd_fState_S7$D_OUT[126:114] + 13'd1023 ; - assign value__h148923 = - { 1'b0, iFifo$D_OUT[167:160] != 8'd0, iFifo$D_OUT[159:137] } ; - assign value__h187561 = - { 1'b0, iFifo$D_OUT[102:95] != 8'd0, iFifo$D_OUT[94:72] } ; - assign value__h226500 = - { 1'b0, iFifo$D_OUT[37:30] != 8'd0, iFifo$D_OUT[29:7] } ; - assign value__h270197 = - { 1'b0, resWire$wget[67:57] != 11'd0, resWire$wget[56:5] } ; - assign value__h31374 = - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 + - 13'd1023 ; - assign value__h31429 = { 1'b0, sfdA__h2039 } ; - assign value__h31550 = - 13'd7170 - - IF_fpu_div64_fOperands_S0_first__06_BITS_129_T_ETC___d352 ; - assign value__h32541 = rg_r[115] ? rg_r + b__h32583 : rg_r ; - assign value__h32661 = - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] >> - fpu_div64_fState_S2$D_OUT[10:0] ; - assign value__h53174 = - { 1'b0, - value_BIT_52___h53270, - fpu_sqr64_fOperand_S0$D_OUT[54:3] } ; - assign x__h114243 = - { fpu_madd_fOperand_S0$D_OUT[129:119] != 11'd0, - fpu_madd_fOperand_S0$D_OUT[118:67] } ; - assign x__h114255 = - { fpu_madd_fOperand_S0$D_OUT[65:55] != 11'd0, - fpu_madd_fOperand_S0$D_OUT[54:3] } ; - assign x__h116896 = fpu_madd_fProd_S3$D_OUT << x__h116929 ; - assign x__h116929 = - 13'd106 - - _7170_MINUS_fpu_madd_fState_S3_first__995_BITS__ETC___d2007 ; - assign x__h131406 = - fpu_madd_fState_S3_first__995_BITS_12_TO_0_001_ETC___d2002 ? - _theResult___snd_snd_snd__h131369 : - 2'd3 ; - assign x__h131940 = - { 1'b0, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - { fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } : - { fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } } ; - assign x__h131944 = - { 1'b0, - NOT_fpu_madd_fState_S4_first__547_BIT_130_553__ETC___d2584 ? - { fpu_madd_fState_S4$D_OUT[128:118] != 11'd0, - fpu_madd_fState_S4$D_OUT[117:66], - 3'b0 } : - { fpu_madd_fState_S4$D_OUT[64:54] != 11'd0, - fpu_madd_fState_S4$D_OUT[53:0], - 1'b0 } } ; - assign x__h132359 = - fpu_madd_fState_S5$D_OUT[215] ? - fpu_madd_fState_S5$D_OUT[56:0] : - (((fpu_madd_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ? - result__h132372 : - ((fpu_madd_fState_S5$D_OUT[56:0] == 57'd0) ? - fpu_madd_fState_S5$D_OUT[56:0] : - 57'd1)) ; - assign x__h132471 = 13'd57 - fpu_madd_fState_S5$D_OUT[126:114] ; - assign x__h132871 = - fpu_madd_fState_S6$D_OUT[113:57] + - fpu_madd_fState_S6$D_OUT[56:0] ; - assign x__h132880 = - fpu_madd_fState_S6$D_OUT[113:57] - - fpu_madd_fState_S6$D_OUT[56:0] ; - assign x__h141760 = fpu_madd_fState_S7$D_OUT[202] ? 2'd0 : guard__h133123 ; - assign x__h165324 = sfd__h144536 << x__h165357 ; - assign x__h165357 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_167_TO_1_ETC___d3326 ; - assign x__h203962 = sfd__h183176 << x__h203995 ; - assign x__h203995 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_102_TO_9_ETC___d4809 ; - assign x__h242901 = sfd__h222115 << x__h242934 ; - assign x__h242934 = - 12'd57 - - _3074_MINUS_SEXT_iFifo_first__087_BITS_37_TO_30_ETC___d4034 ; - assign x__h287924 = sfd__h261975 << x__h287957 ; - assign x__h287957 = - 12'd57 - - _3970_MINUS_SEXT_resWire_wget__410_BITS_67_TO_5_ETC___d6034 ; - assign x__h31426 = { value__h31429, 60'd0 } ; - assign x__h31487 = { sfdB__h2041, 4'b0 } ; - assign x__h31541 = - fpu_div64_fOperands_S0_first__06_BITS_129_TO_1_ETC___d363 ? - 11'd0 : - _theResult___fst__h31322 ; - assign x__h32762 = - { 1'd0, - IF_rg_r_BIT_115_THEN_rg_q_PLUS_NEG_INV_rg_q_59_ETC__q10[56:0] } << - x__h32769 ; - assign x__h32769 = 11'd58 - fpu_div64_fState_S2$D_OUT[10:0] ; - assign x__h33052 = - (value__h32541[114:58] == 57'd0) ? - _theResult____h32523 : - result__h32617 ; - assign x__h42705 = - (sfdin__h34118[57] && - IF_IF_fpu_div64_fState_S3_first__86_BITS_120_T_ETC___d643 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h42439 ; - assign x__h52551 = x__h52569 + 13'd1024 ; - assign x__h52569 = - { IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17[11], - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC__q17 } ; - assign x__h60693 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1195[0] ? - sfd__h44953 : - sfd___1__h60702 ; - assign x__h60732 = - IF_fpu_sqr64_fOperand_S0_first__059_BITS_65_TO_ETC___d1193 - - 6'd1 ; - assign x__h85465 = - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342[0] ? - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 + - 7'd1 : - IF_fpu_sqr64_fState_S1_first__216_BIT_57_226_T_ETC___d1342 ; - assign x__h85931 = rg_res[116] ? rg_res[115:0] : 116'd0 ; - assign x__h86149 = (rg_s == 116'd0) ? x__h85931[58:0] : result__h85925 ; - assign x__h95138 = - (fpu_sqr64_fState_S3$D_OUT[58] && - IF_fpu_sqr64_fState_S3_first__375_BITS_121_TO__ETC___d1389 == - 12'd1023) ? - 2'd3 : - _theResult___snd_fst__h94856 ; - assign x__h96539 = - fpu_madd_fOperand_S0$D_OUT[195] ? - fpu_madd_fOperand_S0$D_OUT[193:183] : - 11'd0 ; - always@(fpu_div64_fState_S4$D_OUT or - out_sfd__h43479 or _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - fpu_div64_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - out_sfd__h43479; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 = - _theResult___sfd__h43476; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 = - fpu_div64_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 = - _theResult___sfd__h43476; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2 or - _theResult___sfd__h43476) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h43554 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q1; - 3'd1: - _theResult___fst_sfd__h43554 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q2; - 3'd2: - _theResult___fst_sfd__h43554 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[53:2] : - _theResult___sfd__h43476; - 3'd3: - _theResult___fst_sfd__h43554 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[53:2] : - (fpu_div64_fState_S4$D_OUT[65] ? - _theResult___sfd__h43476 : - fpu_div64_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h43554 = fpu_div64_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h43554 = 52'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - out_sfd__h95913 or _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - fpu_sqr64_fState_S4$D_OUT[53:2]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - out_sfd__h95913; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 = - _theResult___sfd__h95910; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 = - fpu_sqr64_fState_S4$D_OUT[53:2]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 = - _theResult___sfd__h95910; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4 or - _theResult___sfd__h95910) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_sfd__h95988 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q3; - 3'd1: - _theResult___fst_sfd__h95988 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q4; - 3'd2: - _theResult___fst_sfd__h95988 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - _theResult___sfd__h95910; - 3'd3: - _theResult___fst_sfd__h95988 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[53:2] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - _theResult___sfd__h95910 : - fpu_sqr64_fState_S4$D_OUT[53:2]); - 3'd4: _theResult___fst_sfd__h95988 = fpu_sqr64_fState_S4$D_OUT[53:2]; - default: _theResult___fst_sfd__h95988 = 52'd0; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - out_sfd__h142545 or _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - fpu_madd_fState_S8$D_OUT[54:3]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - out_sfd__h142545; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 = - _theResult___sfd__h142542; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 = - fpu_madd_fState_S8$D_OUT[54:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 = - _theResult___sfd__h142542; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6 or - _theResult___sfd__h142542) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_sfd__h142620 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q5; - 3'd1: - _theResult___fst_sfd__h142620 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q6; - 3'd2: - _theResult___fst_sfd__h142620 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[54:3] : - _theResult___sfd__h142542; - 3'd3: - _theResult___fst_sfd__h142620 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[54:3] : - (fpu_madd_fState_S8$D_OUT[66] ? - _theResult___sfd__h142542 : - fpu_madd_fState_S8$D_OUT[54:3]); - 3'd4: _theResult___fst_sfd__h142620 = fpu_madd_fState_S8$D_OUT[54:3]; - default: _theResult___fst_sfd__h142620 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h148291 = 11'd2047; - 3'd2: - _theResult___fst_exp__h148291 = - iFifo$D_OUT[168] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h148291 = - iFifo$D_OUT[168] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h148291 = 11'd2046; - default: _theResult___fst_exp__h148291 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h148292 = 52'd0; - 3'd2: - _theResult___fst_sfd__h148292 = - iFifo$D_OUT[168] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h148292 = - iFifo$D_OUT[168] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h148292 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h148292 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h186931 = 11'd2047; - 3'd2: - _theResult___fst_exp__h186931 = - iFifo$D_OUT[103] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h186931 = - iFifo$D_OUT[103] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h186931 = 11'd2046; - default: _theResult___fst_exp__h186931 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_exp__h225870 = 11'd2047; - 3'd2: - _theResult___fst_exp__h225870 = - iFifo$D_OUT[38] ? 11'd2046 : 11'd2047; - 3'd3: - _theResult___fst_exp__h225870 = - iFifo$D_OUT[38] ? 11'd2047 : 11'd2046; - 3'd4: _theResult___fst_exp__h225870 = 11'd2046; - default: _theResult___fst_exp__h225870 = 11'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h186932 = 52'd0; - 3'd2: - _theResult___fst_sfd__h186932 = - iFifo$D_OUT[103] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h186932 = - iFifo$D_OUT[103] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h186932 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h186932 = 52'd0; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1: _theResult___fst_sfd__h225871 = 52'd0; - 3'd2: - _theResult___fst_sfd__h225871 = - iFifo$D_OUT[38] ? 52'hFFFFFFFFFFFFF : 52'd0; - 3'd3: - _theResult___fst_sfd__h225871 = - iFifo$D_OUT[38] ? 52'd0 : 52'hFFFFFFFFFFFFF; - 3'd4: _theResult___fst_sfd__h225871 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h225871 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_exp__h19467 = 11'd2047; - 3'd2: - _theResult___fst_exp__h19467 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 11'd2047 : - 11'd2046; - 3'd3: - _theResult___fst_exp__h19467 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 11'd2046 : - 11'd2047; - 3'd4: _theResult___fst_exp__h19467 = 11'd2046; - default: _theResult___fst_exp__h19467 = 11'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1: _theResult___fst_sfd__h19468 = 52'd0; - 3'd2: - _theResult___fst_sfd__h19468 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd0 : - 52'hFFFFFFFFFFFFF; - 3'd3: - _theResult___fst_sfd__h19468 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'hFFFFFFFFFFFFF : - 52'd0; - 3'd4: _theResult___fst_sfd__h19468 = 52'hFFFFFFFFFFFFF; - default: _theResult___fst_sfd__h19468 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0: _theResult___fst_sfd__h19957 = 52'd0; - 3'd1: _theResult___fst_sfd__h19957 = 52'd1; - 3'd2: - _theResult___fst_sfd__h19957 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd1 : - 52'd0; - 3'd3: - _theResult___fst_sfd__h19957 = - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405 ? - 52'd0 : - 52'd1; - default: _theResult___fst_sfd__h19957 = 52'd0; - endcase - end - always@(fpu_div64_fOperands_S0$D_OUT or - fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405) - begin - case (fpu_div64_fOperands_S0$D_OUT[2:0]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 = - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405; - default: CASE_fpu_div64_fOperands_S0D_OUT_BITS_2_TO_0__ETC__q9 = - fpu_div64_fOperands_S0$D_OUT[2:0] == 3'd4 && - !fpu_div64_fOperands_S0_first__06_BIT_130_03_EQ_ETC___d405; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - out_exp__h43478 or _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - fpu_div64_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - out_exp__h43478; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 = - _theResult___exp__h43475; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 = - fpu_div64_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 = - _theResult___exp__h43475; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15 or - _theResult___exp__h43475) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h43553 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q14; - 3'd1: - _theResult___fst_exp__h43553 = - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q15; - 3'd2: - _theResult___fst_exp__h43553 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[64:54] : - _theResult___exp__h43475; - 3'd3: - _theResult___fst_exp__h43553 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[64:54] : - (fpu_div64_fState_S4$D_OUT[65] ? - _theResult___exp__h43475 : - fpu_div64_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h43553 = fpu_div64_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h43553 = 11'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - out_exp__h95912 or _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - fpu_sqr64_fState_S4$D_OUT[64:54]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - out_exp__h95912; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 = - _theResult___exp__h95909; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 = - fpu_sqr64_fState_S4$D_OUT[64:54]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 = - _theResult___exp__h95909; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22 or - _theResult___exp__h95909) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - _theResult___fst_exp__h95987 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q21; - 3'd1: - _theResult___fst_exp__h95987 = - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q22; - 3'd2: - _theResult___fst_exp__h95987 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - _theResult___exp__h95909; - 3'd3: - _theResult___fst_exp__h95987 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[64:54] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - _theResult___exp__h95909 : - fpu_sqr64_fState_S4$D_OUT[64:54]); - 3'd4: _theResult___fst_exp__h95987 = fpu_sqr64_fState_S4$D_OUT[64:54]; - default: _theResult___fst_exp__h95987 = 11'd0; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - out_exp__h142544 or _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - fpu_madd_fState_S8$D_OUT[65:55]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - out_exp__h142544; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 = - _theResult___exp__h142541; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 = - fpu_madd_fState_S8$D_OUT[65:55]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 = - _theResult___exp__h142541; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32 or - _theResult___exp__h142541) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - _theResult___fst_exp__h142619 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q31; - 3'd1: - _theResult___fst_exp__h142619 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q32; - 3'd2: - _theResult___fst_exp__h142619 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[65:55] : - _theResult___exp__h142541; - 3'd3: - _theResult___fst_exp__h142619 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[65:55] : - (fpu_madd_fState_S8$D_OUT[66] ? - _theResult___exp__h142541 : - fpu_madd_fState_S8$D_OUT[65:55]); - 3'd4: _theResult___fst_exp__h142619 = fpu_madd_fState_S8$D_OUT[65:55]; - default: _theResult___fst_exp__h142619 = 11'd0; - endcase - end - always@(guard__h155375 or - _theResult___fst_exp__h163336 or - out_exp__h163984 or _theResult___exp__h163981) - begin - case (guard__h155375) - 2'b0, 2'b01: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - _theResult___fst_exp__h163336; - 2'b10: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - out_exp__h163984; - 2'b11: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 = - _theResult___exp__h163981; - endcase - end - always@(guard__h155375 or - _theResult___fst_exp__h163336 or _theResult___exp__h163981) - begin - case (guard__h155375) - 2'b0: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 = - _theResult___fst_exp__h163336; - 2'b01, 2'b10, 2'b11: - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 = - _theResult___exp__h163981; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42 or - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692 or - _theResult___fst_exp__h163336) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h164059 = - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q42; - 3'd1: - _theResult___fst_exp__h164059 = - CASE_guard55375_0b0_theResult___fst_exp63336_0_ETC__q43; - 3'd2: - _theResult___fst_exp__h164059 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3690; - 3'd3: - _theResult___fst_exp__h164059 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3692; - 3'd4: _theResult___fst_exp__h164059 = _theResult___fst_exp__h163336; - default: _theResult___fst_exp__h164059 = 11'd0; - endcase - end - always@(guard__h164624 or - _theResult___fst_exp__h172852 or - out_exp__h173574 or _theResult___exp__h173571) - begin - case (guard__h164624) - 2'b0, 2'b01: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - _theResult___fst_exp__h172852; - 2'b10: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - out_exp__h173574; - 2'b11: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 = - _theResult___exp__h173571; - endcase - end - always@(guard__h164624 or - _theResult___fst_exp__h172852 or _theResult___exp__h173571) - begin - case (guard__h164624) - 2'b0: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 = - _theResult___fst_exp__h172852; - 2'b01, 2'b10, 2'b11: - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 = - _theResult___exp__h173571; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44 or - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731 or - _theResult___fst_exp__h172852) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h173649 = - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q44; - 3'd1: - _theResult___fst_exp__h173649 = - CASE_guard64624_0b0_theResult___fst_exp72852_0_ETC__q45; - 3'd2: - _theResult___fst_exp__h173649 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3729; - 3'd3: - _theResult___fst_exp__h173649 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3731; - 3'd4: _theResult___fst_exp__h173649 = _theResult___fst_exp__h172852; - default: _theResult___fst_exp__h173649 = 11'd0; - endcase - end - always@(guard__h173663 or - _theResult___fst_exp__h181653 or - out_exp__h182326 or _theResult___exp__h182323) - begin - case (guard__h173663) - 2'b0, 2'b01: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - _theResult___fst_exp__h181653; - 2'b10: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - out_exp__h182326; - 2'b11: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 = - _theResult___exp__h182323; - endcase - end - always@(guard__h173663 or - _theResult___fst_exp__h181653 or _theResult___exp__h182323) - begin - case (guard__h173663) - 2'b0: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 = - _theResult___fst_exp__h181653; - 2'b01, 2'b10, 2'b11: - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 = - _theResult___exp__h182323; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46 or - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762 or - _theResult___fst_exp__h181653) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h182401 = - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q46; - 3'd1: - _theResult___fst_exp__h182401 = - CASE_guard73663_0b0_theResult___fst_exp81653_0_ETC__q47; - 3'd2: - _theResult___fst_exp__h182401 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3760; - 3'd3: - _theResult___fst_exp__h182401 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3762; - 3'd4: _theResult___fst_exp__h182401 = _theResult___fst_exp__h181653; - default: _theResult___fst_exp__h182401 = 11'd0; - endcase - end - always@(guard__h155375 or - _theResult___snd__h163287 or - out_sfd__h163985 or _theResult___sfd__h163982) - begin - case (guard__h155375) - 2'b0, 2'b01: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - _theResult___snd__h163287[56:5]; - 2'b10: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - out_sfd__h163985; - 2'b11: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 = - _theResult___sfd__h163982; - endcase - end - always@(guard__h155375 or - _theResult___snd__h163287 or _theResult___sfd__h163982) - begin - case (guard__h155375) - 2'b0: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 = - _theResult___snd__h163287[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 = - _theResult___sfd__h163982; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48 or - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788 or - _theResult___snd__h163287) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h164060 = - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q48; - 3'd1: - _theResult___fst_sfd__h164060 = - CASE_guard55375_0b0_theResult___snd63287_BITS__ETC__q49; - 3'd2: - _theResult___fst_sfd__h164060 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3786; - 3'd3: - _theResult___fst_sfd__h164060 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3788; - 3'd4: _theResult___fst_sfd__h164060 = _theResult___snd__h163287[56:5]; - default: _theResult___fst_sfd__h164060 = 52'd0; - endcase - end - always@(guard__h164624 or - sfdin__h172846 or out_sfd__h173575 or _theResult___sfd__h173572) - begin - case (guard__h164624) - 2'b0, 2'b01: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - sfdin__h172846[56:5]; - 2'b10: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - out_sfd__h173575; - 2'b11: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 = - _theResult___sfd__h173572; - endcase - end - always@(guard__h164624 or sfdin__h172846 or _theResult___sfd__h173572) - begin - case (guard__h164624) - 2'b0: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 = - sfdin__h172846[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 = - _theResult___sfd__h173572; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50 or - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815 or - sfdin__h172846) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h173650 = - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q50; - 3'd1: - _theResult___fst_sfd__h173650 = - CASE_guard64624_0b0_sfdin72846_BITS_56_TO_5_0b_ETC__q51; - 3'd2: - _theResult___fst_sfd__h173650 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3813; - 3'd3: - _theResult___fst_sfd__h173650 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d3815; - 3'd4: _theResult___fst_sfd__h173650 = sfdin__h172846[56:5]; - default: _theResult___fst_sfd__h173650 = 52'd0; - endcase - end - always@(guard__h173663 or - _theResult___snd__h181599 or - out_sfd__h182327 or _theResult___sfd__h182324) - begin - case (guard__h173663) - 2'b0, 2'b01: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - _theResult___snd__h181599[56:5]; - 2'b10: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - out_sfd__h182327; - 2'b11: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 = - _theResult___sfd__h182324; - endcase - end - always@(guard__h173663 or - _theResult___snd__h181599 or _theResult___sfd__h182324) - begin - case (guard__h173663) - 2'b0: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 = - _theResult___snd__h181599[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 = - _theResult___sfd__h182324; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52 or - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832 or - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834 or - _theResult___snd__h181599) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h182402 = - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q52; - 3'd1: - _theResult___fst_sfd__h182402 = - CASE_guard73663_0b0_theResult___snd81599_BITS__ETC__q53; - 3'd2: - _theResult___fst_sfd__h182402 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3832; - 3'd3: - _theResult___fst_sfd__h182402 = - IF_IF_IF_iFifo_first__087_BITS_167_TO_160_130__ETC___d3834; - 3'd4: _theResult___fst_sfd__h182402 = _theResult___snd__h181599[56:5]; - default: _theResult___fst_sfd__h182402 = 52'd0; - endcase - end - always@(guard__h155375 or iFifo$D_OUT) - begin - case (guard__h155375) - 2'b0, 2'b01, 2'b10: - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 = - guard__h155375 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54 or - guard__h155375) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - CASE_guard55375_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q54; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - (guard__h155375 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h155375 == 2'b01 || guard__h155375 == 2'b10 || - guard__h155375 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard55375_ETC__q55 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 = - iFifo$D_OUT[168]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d3320 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h164624 or iFifo$D_OUT) - begin - case (guard__h164624) - 2'b0, 2'b01, 2'b10: - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 = - guard__h164624 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56 or - guard__h164624) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - CASE_guard64624_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q56; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - (guard__h164624 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h164624 == 2'b01 || guard__h164624 == 2'b10 || - guard__h164624 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard64624_ETC__q57 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h173663 or iFifo$D_OUT) - begin - case (guard__h173663) - 2'b0, 2'b01, 2'b10: - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 = - iFifo$D_OUT[168]; - 2'd3: - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 = - guard__h173663 == 2'b11 && iFifo$D_OUT[168]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58 or - guard__h173663) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - CASE_guard73663_0b0_iFifoD_OUT_BIT_168_0b1_iF_ETC__q58; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - (guard__h173663 == 2'b0) ? - iFifo$D_OUT[168] : - (guard__h173663 == 2'b01 || guard__h173663 == 2'b10 || - guard__h173663 == 2'b11) && - iFifo$D_OUT[168]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - iFifo$D_OUT[168]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard73663_ETC__q59 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[168]; - endcase - end - always@(guard__h232952 or - _theResult___fst_exp__h240913 or - out_exp__h241561 or _theResult___exp__h241558) - begin - case (guard__h232952) - 2'b0, 2'b01: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - _theResult___fst_exp__h240913; - 2'b10: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - out_exp__h241561; - 2'b11: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 = - _theResult___exp__h241558; - endcase - end - always@(guard__h232952 or - _theResult___fst_exp__h240913 or _theResult___exp__h241558) - begin - case (guard__h232952) - 2'b0: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 = - _theResult___fst_exp__h240913; - 2'b01, 2'b10, 2'b11: - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 = - _theResult___exp__h241558; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69 or - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400 or - _theResult___fst_exp__h240913) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h241636 = - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q69; - 3'd1: - _theResult___fst_exp__h241636 = - CASE_guard32952_0b0_theResult___fst_exp40913_0_ETC__q70; - 3'd2: - _theResult___fst_exp__h241636 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4398; - 3'd3: - _theResult___fst_exp__h241636 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4400; - 3'd4: _theResult___fst_exp__h241636 = _theResult___fst_exp__h240913; - default: _theResult___fst_exp__h241636 = 11'd0; - endcase - end - always@(guard__h242201 or - _theResult___fst_exp__h250429 or - out_exp__h251151 or _theResult___exp__h251148) - begin - case (guard__h242201) - 2'b0, 2'b01: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - _theResult___fst_exp__h250429; - 2'b10: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - out_exp__h251151; - 2'b11: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 = - _theResult___exp__h251148; - endcase - end - always@(guard__h242201 or - _theResult___fst_exp__h250429 or _theResult___exp__h251148) - begin - case (guard__h242201) - 2'b0: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 = - _theResult___fst_exp__h250429; - 2'b01, 2'b10, 2'b11: - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 = - _theResult___exp__h251148; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71 or - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438 or - _theResult___fst_exp__h250429) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h251226 = - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q71; - 3'd1: - _theResult___fst_exp__h251226 = - CASE_guard42201_0b0_theResult___fst_exp50429_0_ETC__q72; - 3'd2: - _theResult___fst_exp__h251226 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4436; - 3'd3: - _theResult___fst_exp__h251226 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4438; - 3'd4: _theResult___fst_exp__h251226 = _theResult___fst_exp__h250429; - default: _theResult___fst_exp__h251226 = 11'd0; - endcase - end - always@(guard__h251240 or - _theResult___fst_exp__h259230 or - out_exp__h259903 or _theResult___exp__h259900) - begin - case (guard__h251240) - 2'b0, 2'b01: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - _theResult___fst_exp__h259230; - 2'b10: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - out_exp__h259903; - 2'b11: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 = - _theResult___exp__h259900; - endcase - end - always@(guard__h251240 or - _theResult___fst_exp__h259230 or _theResult___exp__h259900) - begin - case (guard__h251240) - 2'b0: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 = - _theResult___fst_exp__h259230; - 2'b01, 2'b10, 2'b11: - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 = - _theResult___exp__h259900; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73 or - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469 or - _theResult___fst_exp__h259230) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h259978 = - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q73; - 3'd1: - _theResult___fst_exp__h259978 = - CASE_guard51240_0b0_theResult___fst_exp59230_0_ETC__q74; - 3'd2: - _theResult___fst_exp__h259978 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4467; - 3'd3: - _theResult___fst_exp__h259978 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4469; - 3'd4: _theResult___fst_exp__h259978 = _theResult___fst_exp__h259230; - default: _theResult___fst_exp__h259978 = 11'd0; - endcase - end - always@(guard__h232952 or - _theResult___snd__h240864 or - out_sfd__h241562 or _theResult___sfd__h241559) - begin - case (guard__h232952) - 2'b0, 2'b01: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - _theResult___snd__h240864[56:5]; - 2'b10: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - out_sfd__h241562; - 2'b11: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 = - _theResult___sfd__h241559; - endcase - end - always@(guard__h232952 or - _theResult___snd__h240864 or _theResult___sfd__h241559) - begin - case (guard__h232952) - 2'b0: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 = - _theResult___snd__h240864[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 = - _theResult___sfd__h241559; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75 or - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495 or - _theResult___snd__h240864) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h241637 = - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q75; - 3'd1: - _theResult___fst_sfd__h241637 = - CASE_guard32952_0b0_theResult___snd40864_BITS__ETC__q76; - 3'd2: - _theResult___fst_sfd__h241637 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4493; - 3'd3: - _theResult___fst_sfd__h241637 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4495; - 3'd4: _theResult___fst_sfd__h241637 = _theResult___snd__h240864[56:5]; - default: _theResult___fst_sfd__h241637 = 52'd0; - endcase - end - always@(guard__h242201 or - sfdin__h250423 or out_sfd__h251152 or _theResult___sfd__h251149) - begin - case (guard__h242201) - 2'b0, 2'b01: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - sfdin__h250423[56:5]; - 2'b10: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - out_sfd__h251152; - 2'b11: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 = - _theResult___sfd__h251149; - endcase - end - always@(guard__h242201 or sfdin__h250423 or _theResult___sfd__h251149) - begin - case (guard__h242201) - 2'b0: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 = - sfdin__h250423[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 = - _theResult___sfd__h251149; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77 or - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521 or - sfdin__h250423) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h251227 = - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q77; - 3'd1: - _theResult___fst_sfd__h251227 = - CASE_guard42201_0b0_sfdin50423_BITS_56_TO_5_0b_ETC__q78; - 3'd2: - _theResult___fst_sfd__h251227 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4519; - 3'd3: - _theResult___fst_sfd__h251227 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d4521; - 3'd4: _theResult___fst_sfd__h251227 = sfdin__h250423[56:5]; - default: _theResult___fst_sfd__h251227 = 52'd0; - endcase - end - always@(guard__h251240 or - _theResult___snd__h259176 or - out_sfd__h259904 or _theResult___sfd__h259901) - begin - case (guard__h251240) - 2'b0, 2'b01: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - _theResult___snd__h259176[56:5]; - 2'b10: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - out_sfd__h259904; - 2'b11: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 = - _theResult___sfd__h259901; - endcase - end - always@(guard__h251240 or - _theResult___snd__h259176 or _theResult___sfd__h259901) - begin - case (guard__h251240) - 2'b0: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 = - _theResult___snd__h259176[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 = - _theResult___sfd__h259901; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79 or - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538 or - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540 or - _theResult___snd__h259176) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h259979 = - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q79; - 3'd1: - _theResult___fst_sfd__h259979 = - CASE_guard51240_0b0_theResult___snd59176_BITS__ETC__q80; - 3'd2: - _theResult___fst_sfd__h259979 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4538; - 3'd3: - _theResult___fst_sfd__h259979 = - IF_IF_IF_iFifo_first__087_BITS_37_TO_30_850_EQ_ETC___d4540; - 3'd4: _theResult___fst_sfd__h259979 = _theResult___snd__h259176[56:5]; - default: _theResult___fst_sfd__h259979 = 52'd0; - endcase - end - always@(guard__h232952 or iFifo$D_OUT) - begin - case (guard__h232952) - 2'b0, 2'b01, 2'b10: - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 = - guard__h232952 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81 or - guard__h232952) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - CASE_guard32952_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q81; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - (guard__h232952 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h232952 == 2'b01 || guard__h232952 == 2'b10 || - guard__h232952 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q82 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 = - iFifo$D_OUT[38]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4028 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h242201 or iFifo$D_OUT) - begin - case (guard__h242201) - 2'b0, 2'b01, 2'b10: - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 = - guard__h242201 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83 or - guard__h242201) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - CASE_guard42201_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q83; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - (guard__h242201 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h242201 == 2'b01 || guard__h242201 == 2'b10 || - guard__h242201 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q84 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h251240 or iFifo$D_OUT) - begin - case (guard__h251240) - 2'b0, 2'b01, 2'b10: - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 = - iFifo$D_OUT[38]; - 2'd3: - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 = - guard__h251240 == 2'b11 && iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85 or - guard__h251240) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - CASE_guard51240_0b0_iFifoD_OUT_BIT_38_0b1_iFi_ETC__q85; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - (guard__h251240 == 2'b0) ? - iFifo$D_OUT[38] : - (guard__h251240 == 2'b01 || guard__h251240 == 2'b10 || - guard__h251240 == 2'b11) && - iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q86 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[38]; - endcase - end - always@(guard__h232952 or iFifo$D_OUT) - begin - case (guard__h232952) - 2'b0, 2'b01, 2'b10: - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 = - guard__h232952 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87 or - guard__h232952) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - CASE_guard32952_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q87; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - (guard__h232952 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h232952 != 2'b01 && guard__h232952 != 2'b10 && - guard__h232952 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard32952_ETC__q88 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h242201 or iFifo$D_OUT) - begin - case (guard__h242201) - 2'b0, 2'b01, 2'b10: - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 = - guard__h242201 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89 or - guard__h242201) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - CASE_guard42201_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q89; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - (guard__h242201 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h242201 != 2'b01 && guard__h242201 != 2'b10 && - guard__h242201 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard42201_ETC__q90 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h251240 or iFifo$D_OUT) - begin - case (guard__h251240) - 2'b0, 2'b01, 2'b10: - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 = - !iFifo$D_OUT[38]; - 2'd3: - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 = - guard__h251240 != 2'b11 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91 or - guard__h251240) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - CASE_guard51240_0b0_NOT_iFifoD_OUT_BIT_38_0b1_ETC__q91; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - (guard__h251240 == 2'b0) ? - !iFifo$D_OUT[38] : - guard__h251240 != 2'b01 && guard__h251240 != 2'b10 && - guard__h251240 != 2'b11 || - !iFifo$D_OUT[38]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - !iFifo$D_OUT[38]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard51240_ETC__q92 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 = - !iFifo$D_OUT[38]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4582 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[38]; - endcase - end - always@(guard__h194013 or - _theResult___fst_exp__h201974 or - out_exp__h202622 or _theResult___exp__h202619) - begin - case (guard__h194013) - 2'b0, 2'b01: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - _theResult___fst_exp__h201974; - 2'b10: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - out_exp__h202622; - 2'b11: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 = - _theResult___exp__h202619; - endcase - end - always@(guard__h194013 or - _theResult___fst_exp__h201974 or _theResult___exp__h202619) - begin - case (guard__h194013) - 2'b0: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 = - _theResult___fst_exp__h201974; - 2'b01, 2'b10, 2'b11: - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 = - _theResult___exp__h202619; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102 or - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175 or - _theResult___fst_exp__h201974) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h202697 = - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q102; - 3'd1: - _theResult___fst_exp__h202697 = - CASE_guard94013_0b0_theResult___fst_exp01974_0_ETC__q103; - 3'd2: - _theResult___fst_exp__h202697 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5173; - 3'd3: - _theResult___fst_exp__h202697 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5175; - 3'd4: _theResult___fst_exp__h202697 = _theResult___fst_exp__h201974; - default: _theResult___fst_exp__h202697 = 11'd0; - endcase - end - always@(guard__h203262 or - _theResult___fst_exp__h211490 or - out_exp__h212212 or _theResult___exp__h212209) - begin - case (guard__h203262) - 2'b0, 2'b01: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - _theResult___fst_exp__h211490; - 2'b10: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - out_exp__h212212; - 2'b11: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 = - _theResult___exp__h212209; - endcase - end - always@(guard__h203262 or - _theResult___fst_exp__h211490 or _theResult___exp__h212209) - begin - case (guard__h203262) - 2'b0: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 = - _theResult___fst_exp__h211490; - 2'b01, 2'b10, 2'b11: - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 = - _theResult___exp__h212209; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104 or - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213 or - _theResult___fst_exp__h211490) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h212287 = - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q104; - 3'd1: - _theResult___fst_exp__h212287 = - CASE_guard03262_0b0_theResult___fst_exp11490_0_ETC__q105; - 3'd2: - _theResult___fst_exp__h212287 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5211; - 3'd3: - _theResult___fst_exp__h212287 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5213; - 3'd4: _theResult___fst_exp__h212287 = _theResult___fst_exp__h211490; - default: _theResult___fst_exp__h212287 = 11'd0; - endcase - end - always@(guard__h212301 or - _theResult___fst_exp__h220291 or - out_exp__h220964 or _theResult___exp__h220961) - begin - case (guard__h212301) - 2'b0, 2'b01: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - _theResult___fst_exp__h220291; - 2'b10: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - out_exp__h220964; - 2'b11: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 = - _theResult___exp__h220961; - endcase - end - always@(guard__h212301 or - _theResult___fst_exp__h220291 or _theResult___exp__h220961) - begin - case (guard__h212301) - 2'b0: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 = - _theResult___fst_exp__h220291; - 2'b01, 2'b10, 2'b11: - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 = - _theResult___exp__h220961; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106 or - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244 or - _theResult___fst_exp__h220291) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_exp__h221039 = - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q106; - 3'd1: - _theResult___fst_exp__h221039 = - CASE_guard12301_0b0_theResult___fst_exp20291_0_ETC__q107; - 3'd2: - _theResult___fst_exp__h221039 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5242; - 3'd3: - _theResult___fst_exp__h221039 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5244; - 3'd4: _theResult___fst_exp__h221039 = _theResult___fst_exp__h220291; - default: _theResult___fst_exp__h221039 = 11'd0; - endcase - end - always@(guard__h194013 or - _theResult___snd__h201925 or - out_sfd__h202623 or _theResult___sfd__h202620) - begin - case (guard__h194013) - 2'b0, 2'b01: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - _theResult___snd__h201925[56:5]; - 2'b10: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - out_sfd__h202623; - 2'b11: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 = - _theResult___sfd__h202620; - endcase - end - always@(guard__h194013 or - _theResult___snd__h201925 or _theResult___sfd__h202620) - begin - case (guard__h194013) - 2'b0: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 = - _theResult___snd__h201925[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 = - _theResult___sfd__h202620; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108 or - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270 or - _theResult___snd__h201925) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h202698 = - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q108; - 3'd1: - _theResult___fst_sfd__h202698 = - CASE_guard94013_0b0_theResult___snd01925_BITS__ETC__q109; - 3'd2: - _theResult___fst_sfd__h202698 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5268; - 3'd3: - _theResult___fst_sfd__h202698 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5270; - 3'd4: _theResult___fst_sfd__h202698 = _theResult___snd__h201925[56:5]; - default: _theResult___fst_sfd__h202698 = 52'd0; - endcase - end - always@(guard__h203262 or - sfdin__h211484 or out_sfd__h212213 or _theResult___sfd__h212210) - begin - case (guard__h203262) - 2'b0, 2'b01: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - sfdin__h211484[56:5]; - 2'b10: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - out_sfd__h212213; - 2'b11: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 = - _theResult___sfd__h212210; - endcase - end - always@(guard__h203262 or sfdin__h211484 or _theResult___sfd__h212210) - begin - case (guard__h203262) - 2'b0: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 = - sfdin__h211484[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 = - _theResult___sfd__h212210; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110 or - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294 or - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296 or - sfdin__h211484) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h212288 = - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q110; - 3'd1: - _theResult___fst_sfd__h212288 = - CASE_guard03262_0b0_sfdin11484_BITS_56_TO_5_0b_ETC__q111; - 3'd2: - _theResult___fst_sfd__h212288 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5294; - 3'd3: - _theResult___fst_sfd__h212288 = - IF_IF_IF_IF_3074_MINUS_SEXT_iFifo_first__087_B_ETC___d5296; - 3'd4: _theResult___fst_sfd__h212288 = sfdin__h211484[56:5]; - default: _theResult___fst_sfd__h212288 = 52'd0; - endcase - end - always@(guard__h212301 or - _theResult___snd__h220237 or - out_sfd__h220965 or _theResult___sfd__h220962) - begin - case (guard__h212301) - 2'b0, 2'b01: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - _theResult___snd__h220237[56:5]; - 2'b10: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - out_sfd__h220965; - 2'b11: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 = - _theResult___sfd__h220962; - endcase - end - always@(guard__h212301 or - _theResult___snd__h220237 or _theResult___sfd__h220962) - begin - case (guard__h212301) - 2'b0: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 = - _theResult___snd__h220237[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 = - _theResult___sfd__h220962; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112 or - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313 or - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315 or - _theResult___snd__h220237) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - _theResult___fst_sfd__h221040 = - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q112; - 3'd1: - _theResult___fst_sfd__h221040 = - CASE_guard12301_0b0_theResult___snd20237_BITS__ETC__q113; - 3'd2: - _theResult___fst_sfd__h221040 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5313; - 3'd3: - _theResult___fst_sfd__h221040 = - IF_IF_IF_iFifo_first__087_BITS_102_TO_95_625_E_ETC___d5315; - 3'd4: _theResult___fst_sfd__h221040 = _theResult___snd__h220237[56:5]; - default: _theResult___fst_sfd__h221040 = 52'd0; - endcase - end - always@(guard__h194013 or iFifo$D_OUT) - begin - case (guard__h194013) - 2'b0, 2'b01, 2'b10: - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 = - guard__h194013 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114 or - guard__h194013) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - CASE_guard94013_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q114; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - (guard__h194013 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h194013 == 2'b01 || guard__h194013 == 2'b10 || - guard__h194013 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q115 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 = - iFifo$D_OUT[103]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d4803 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h203262 or iFifo$D_OUT) - begin - case (guard__h203262) - 2'b0, 2'b01, 2'b10: - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 = - guard__h203262 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116 or - guard__h203262) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - CASE_guard03262_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q116; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - (guard__h203262 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h203262 == 2'b01 || guard__h203262 == 2'b10 || - guard__h203262 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q117 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h212301 or iFifo$D_OUT) - begin - case (guard__h212301) - 2'b0, 2'b01, 2'b10: - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 = - iFifo$D_OUT[103]; - 2'd3: - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 = - guard__h212301 == 2'b11 && iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118 or - guard__h212301) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - CASE_guard12301_0b0_iFifoD_OUT_BIT_103_0b1_iF_ETC__q118; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - (guard__h212301 == 2'b0) ? - iFifo$D_OUT[103] : - (guard__h212301 == 2'b01 || guard__h212301 == 2'b10 || - guard__h212301 == 2'b11) && - iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q119 = - iFifo$D_OUT[6:4] == 3'd4 && iFifo$D_OUT[103]; - endcase - end - always@(guard__h194013 or iFifo$D_OUT) - begin - case (guard__h194013) - 2'b0, 2'b01, 2'b10: - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 = - guard__h194013 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120 or - guard__h194013) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - CASE_guard94013_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q120; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - (guard__h194013 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h194013 != 2'b01 && guard__h194013 != 2'b10 && - guard__h194013 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard94013_ETC__q121 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT) - begin - case (iFifo$D_OUT[6:4]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 = - !iFifo$D_OUT[103]; - default: IF_iFifo_first__087_BITS_6_TO_4_118_EQ_0_191_O_ETC___d5348 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(guard__h203262 or iFifo$D_OUT) - begin - case (guard__h203262) - 2'b0, 2'b01, 2'b10: - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 = - guard__h203262 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122 or - guard__h203262) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - CASE_guard03262_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q122; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - (guard__h203262 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h203262 != 2'b01 && guard__h203262 != 2'b10 && - guard__h203262 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard03262_ETC__q123 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(guard__h212301 or iFifo$D_OUT) - begin - case (guard__h212301) - 2'b0, 2'b01, 2'b10: - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 = - !iFifo$D_OUT[103]; - 2'd3: - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 = - guard__h212301 != 2'b11 || !iFifo$D_OUT[103]; - endcase - end - always@(iFifo$D_OUT or - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124 or - guard__h212301) - begin - case (iFifo$D_OUT[6:4]) - 3'd0: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - CASE_guard12301_0b0_NOT_iFifoD_OUT_BIT_103_0b_ETC__q124; - 3'd1: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - (guard__h212301 == 2'b0) ? - !iFifo$D_OUT[103] : - guard__h212301 != 2'b01 && guard__h212301 != 2'b10 && - guard__h212301 != 2'b11 || - !iFifo$D_OUT[103]; - 3'd2, 3'd3: - CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - !iFifo$D_OUT[103]; - default: CASE_iFifoD_OUT_BITS_6_TO_4_0_CASE_guard12301_ETC__q125 = - iFifo$D_OUT[6:4] != 3'd4 || !iFifo$D_OUT[103]; - endcase - end - always@(fpu_madd_fState_S8$D_OUT) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 = - fpu_madd_fState_S8$D_OUT[66]; - 2'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126 = - fpu_madd_fState_S8$D_OUT[2:1] == 2'b11 && - fpu_madd_fState_S8$D_OUT[66]; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q126; - 3'd1: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[66] : - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b01 || - fpu_madd_fState_S8$D_OUT[2:1] == 2'b10 || - fpu_madd_fState_S8$D_OUT[2:1] == 2'b11) && - fpu_madd_fState_S8$D_OUT[66]; - 3'd2, 3'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - fpu_madd_fState_S8$D_OUT[66]; - default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q127 = - fpu_madd_fState_S8$D_OUT[70:68] == 3'd4 && - fpu_madd_fState_S8$D_OUT[66]; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618 or - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848; - 4'd5, 4'd7: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4555; - 4'd6: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618; - default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d4623 = - IF_iFifo_first__087_BIT_71_849_THEN_IF_iFifo_f_ETC___d4618; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0, 2'b01: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b10: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - fpu_madd_fState_S8$D_OUT[3] ? - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 : - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 = - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[2:1]) - 2'b0: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 = - fpu_madd_fState_S8$D_OUT[65:3]; - 2'b01, 2'b10, 2'b11: - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 = - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - endcase - end - always@(fpu_madd_fState_S8$D_OUT or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130 or - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131 or - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065) - begin - case (fpu_madd_fState_S8$D_OUT[70:68]) - 3'd0: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q130; - 3'd1: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - CASE_fpu_madd_fState_S8D_OUT_BITS_2_TO_1_0b0__ETC__q131; - 3'd2: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0 || - fpu_madd_fState_S8$D_OUT[66]) ? - fpu_madd_fState_S8$D_OUT[65:3] : - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065; - 3'd3: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - (fpu_madd_fState_S8$D_OUT[2:1] == 2'b0) ? - fpu_madd_fState_S8$D_OUT[65:3] : - (fpu_madd_fState_S8$D_OUT[66] ? - IF_0b0_CONCAT_NOT_fpu_madd_fState_S8_first__96_ETC___d3065 : - fpu_madd_fState_S8$D_OUT[65:3]); - 3'd4: - CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - fpu_madd_fState_S8$D_OUT[65:3]; - default: CASE_fpu_madd_fState_S8D_OUT_BITS_70_TO_68_0__ETC__q132 = - 63'd0; - endcase - end - always@(iFifo$D_OUT or - fpu_madd_fOperand_S0$FULL_N or - fpu_div64_fOperands_S0$FULL_N or fpu_sqr64_fOperand_S0$FULL_N) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1, 4'd2, 4'd5, 4'd6, 4'd7: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_madd_fOperand_S0$FULL_N; - 4'd3: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_div64_fOperands_S0$FULL_N; - 4'd4: - IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - fpu_sqr64_fOperand_S0$FULL_N; - default: IF_iFifo_first__087_BITS_3_TO_0_088_EQ_0_089_O_ETC___d3110 = - iFifo$D_OUT[3:0] != 4'd8 || fpu_madd_fOperand_S0$FULL_N; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1: _theResult___fst_exp__h269559 = 8'd255; - 3'd2: - _theResult___fst_exp__h269559 = resWire$wget[68] ? 8'd254 : 8'd255; - 3'd3: - _theResult___fst_exp__h269559 = resWire$wget[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h269559 = 8'd254; - default: _theResult___fst_exp__h269559 = 8'd0; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1: _theResult___fst_sfd__h269560 = 23'd0; - 3'd2: - _theResult___fst_sfd__h269560 = - resWire$wget[68] ? 23'd8388607 : 23'd0; - 3'd3: - _theResult___fst_sfd__h269560 = - resWire$wget[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h269560 = 23'd8388607; - default: _theResult___fst_sfd__h269560 = 23'd0; - endcase - end - always@(guard__h269587 or resWire$wget) - begin - case (guard__h269587) - 2'b0, 2'b01, 2'b10: - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 = - resWire$wget[68]; - 2'd3: - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 = - guard__h269587 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144 or - guard__h269587) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - CASE_guard69587_0b0_resWirewget_BIT_68_0b1_re_ETC__q144; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - (guard__h269587 == 2'b0) ? - resWire$wget[68] : - (guard__h269587 == 2'b01 || guard__h269587 == 2'b10 || - guard__h269587 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6388 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h269587 or resWire$wget) - begin - case (guard__h269587) - 2'b0, 2'b01, 2'b10: - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 = - !resWire$wget[68]; - 2'd3: - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 = - guard__h269587 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145 or - guard__h269587) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - CASE_guard69587_0b0_NOT_resWirewget_BIT_68_0b_ETC__q145; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - (guard__h269587 == 2'b0) ? - !resWire$wget[68] : - guard__h269587 != 2'b01 && guard__h269587 != 2'b10 && - guard__h269587 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d5823 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h278294 or resWire$wget) - begin - case (guard__h278294) - 2'b0, 2'b01, 2'b10: - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 = - resWire$wget[68]; - 2'd3: - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 = - guard__h278294 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146 or - guard__h278294) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - CASE_guard78294_0b0_resWirewget_BIT_68_0b1_re_ETC__q146; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - (guard__h278294 == 2'b0) ? - resWire$wget[68] : - (guard__h278294 == 2'b01 || guard__h278294 == 2'b10 || - guard__h278294 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6397 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h278294 or resWire$wget) - begin - case (guard__h278294) - 2'b0, 2'b01, 2'b10: - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 = - !resWire$wget[68]; - 2'd3: - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 = - guard__h278294 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147 or - guard__h278294) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - CASE_guard78294_0b0_NOT_resWirewget_BIT_68_0b_ETC__q147; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - (guard__h278294 == 2'b0) ? - !resWire$wget[68] : - guard__h278294 != 2'b01 && guard__h278294 != 2'b10 && - guard__h278294 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6023 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h287224 or resWire$wget) - begin - case (guard__h287224) - 2'b0, 2'b01, 2'b10: - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 = - resWire$wget[68]; - 2'd3: - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 = - guard__h287224 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148 or - guard__h287224) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - CASE_guard87224_0b0_resWirewget_BIT_68_0b1_re_ETC__q148; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - (guard__h287224 == 2'b0) ? - resWire$wget[68] : - (guard__h287224 == 2'b01 || guard__h287224 == 2'b10 || - guard__h287224 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6409 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h287224 or resWire$wget) - begin - case (guard__h287224) - 2'b0, 2'b01, 2'b10: - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 = - !resWire$wget[68]; - 2'd3: - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 = - guard__h287224 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149 or - guard__h287224) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - CASE_guard87224_0b0_NOT_resWirewget_BIT_68_0b_ETC__q149; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - (guard__h287224 == 2'b0) ? - !resWire$wget[68] : - guard__h287224 != 2'b01 && guard__h287224 != 2'b10 && - guard__h287224 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_I_ETC___d6324 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h296060 or resWire$wget) - begin - case (guard__h296060) - 2'b0, 2'b01, 2'b10: - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 = - resWire$wget[68]; - 2'd3: - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 = - guard__h296060 == 2'b11 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150 or - guard__h296060) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - CASE_guard96060_0b0_resWirewget_BIT_68_0b1_re_ETC__q150; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - (guard__h296060 == 2'b0) ? - resWire$wget[68] : - (guard__h296060 == 2'b01 || guard__h296060 == 2'b10 || - guard__h296060 == 2'b11) && - resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6418 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(guard__h296060 or resWire$wget) - begin - case (guard__h296060) - 2'b0, 2'b01, 2'b10: - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 = - !resWire$wget[68]; - 2'd3: - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 = - guard__h296060 != 2'b11 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or - resWire$wget or - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151 or - guard__h296060) - begin - case (rmdFifo$D_OUT) - 3'd0: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - CASE_guard96060_0b0_NOT_resWirewget_BIT_68_0b_ETC__q151; - 3'd1: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - (guard__h296060 == 2'b0) ? - !resWire$wget[68] : - guard__h296060 != 2'b01 && guard__h296060 != 2'b10 && - guard__h296060 != 2'b11 || - !resWire$wget[68]; - 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_THEN_IF_IF_IF_r_ETC___d6373 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 = - resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6400 = - rmdFifo$D_OUT == 3'd4 && resWire$wget[68]; - endcase - end - always@(rmdFifo$D_OUT or resWire$wget) - begin - case (rmdFifo$D_OUT) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 = - !resWire$wget[68]; - default: IF_rmdFifo_first__778_EQ_0_779_OR_rmdFifo_firs_ETC___d6028 = - rmdFifo$D_OUT != 3'd4 || !resWire$wget[68]; - endcase - end - always@(guard__h278294 or - _theResult___fst_exp__h286342 or - out_exp__h286787 or _theResult___exp__h286784) - begin - case (guard__h278294) - 2'b0, 2'b01: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - _theResult___fst_exp__h286342; - 2'b10: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - out_exp__h286787; - 2'b11: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 = - _theResult___exp__h286784; - endcase - end - always@(guard__h278294 or - _theResult___fst_exp__h286342 or _theResult___exp__h286784) - begin - case (guard__h278294) - 2'b0: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 = - _theResult___fst_exp__h286342; - 2'b01, 2'b10, 2'b11: - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 = - _theResult___exp__h286784; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152 or - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481 or - _theResult___fst_exp__h286342) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h286862 = - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q152; - 3'd1: - _theResult___fst_exp__h286862 = - CASE_guard78294_0b0_theResult___fst_exp86342_0_ETC__q153; - 3'd2: - _theResult___fst_exp__h286862 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6479; - 3'd3: - _theResult___fst_exp__h286862 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6481; - 3'd4: _theResult___fst_exp__h286862 = _theResult___fst_exp__h286342; - default: _theResult___fst_exp__h286862 = 8'd0; - endcase - end - always@(guard__h269587 or - _theResult___fst_exp__h277686 or - out_exp__h278205 or _theResult___exp__h278202) - begin - case (guard__h269587) - 2'b0, 2'b01: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - _theResult___fst_exp__h277686; - 2'b10: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - out_exp__h278205; - 2'b11: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 = - _theResult___exp__h278202; - endcase - end - always@(guard__h269587 or - _theResult___fst_exp__h277686 or _theResult___exp__h278202) - begin - case (guard__h269587) - 2'b0: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 = - _theResult___fst_exp__h277686; - 2'b01, 2'b10, 2'b11: - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 = - _theResult___exp__h278202; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154 or - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450 or - _theResult___fst_exp__h277686) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h278280 = - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q154; - 3'd1: - _theResult___fst_exp__h278280 = - CASE_guard69587_0b0_theResult___fst_exp77686_0_ETC__q155; - 3'd2: - _theResult___fst_exp__h278280 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6448; - 3'd3: - _theResult___fst_exp__h278280 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6450; - 3'd4: _theResult___fst_exp__h278280 = _theResult___fst_exp__h277686; - default: _theResult___fst_exp__h278280 = 8'd0; - endcase - end - always@(guard__h287224 or - _theResult___fst_exp__h295452 or - out_exp__h295971 or _theResult___exp__h295968) - begin - case (guard__h287224) - 2'b0, 2'b01: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - _theResult___fst_exp__h295452; - 2'b10: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - out_exp__h295971; - 2'b11: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 = - _theResult___exp__h295968; - endcase - end - always@(guard__h287224 or - _theResult___fst_exp__h295452 or _theResult___exp__h295968) - begin - case (guard__h287224) - 2'b0: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 = - _theResult___fst_exp__h295452; - 2'b01, 2'b10, 2'b11: - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 = - _theResult___exp__h295968; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156 or - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520 or - _theResult___fst_exp__h295452) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h296046 = - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q156; - 3'd1: - _theResult___fst_exp__h296046 = - CASE_guard87224_0b0_theResult___fst_exp95452_0_ETC__q157; - 3'd2: - _theResult___fst_exp__h296046 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6518; - 3'd3: - _theResult___fst_exp__h296046 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6520; - 3'd4: _theResult___fst_exp__h296046 = _theResult___fst_exp__h295452; - default: _theResult___fst_exp__h296046 = 8'd0; - endcase - end - always@(guard__h296060 or - _theResult___fst_exp__h304137 or - out_exp__h304607 or _theResult___exp__h304604) - begin - case (guard__h296060) - 2'b0, 2'b01: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - _theResult___fst_exp__h304137; - 2'b10: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - out_exp__h304607; - 2'b11: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 = - _theResult___exp__h304604; - endcase - end - always@(guard__h296060 or - _theResult___fst_exp__h304137 or _theResult___exp__h304604) - begin - case (guard__h296060) - 2'b0: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 = - _theResult___fst_exp__h304137; - 2'b01, 2'b10, 2'b11: - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 = - _theResult___exp__h304604; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158 or - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551 or - _theResult___fst_exp__h304137) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_exp__h304682 = - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q158; - 3'd1: - _theResult___fst_exp__h304682 = - CASE_guard96060_0b0_theResult___fst_exp04137_0_ETC__q159; - 3'd2: - _theResult___fst_exp__h304682 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6549; - 3'd3: - _theResult___fst_exp__h304682 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6551; - 3'd4: _theResult___fst_exp__h304682 = _theResult___fst_exp__h304137; - default: _theResult___fst_exp__h304682 = 8'd0; - endcase - end - always@(guard__h278294 or - _theResult___snd__h286293 or - out_sfd__h286788 or _theResult___sfd__h286785) - begin - case (guard__h278294) - 2'b0, 2'b01: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - _theResult___snd__h286293[56:34]; - 2'b10: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - out_sfd__h286788; - 2'b11: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 = - _theResult___sfd__h286785; - endcase - end - always@(guard__h278294 or - _theResult___snd__h286293 or _theResult___sfd__h286785) - begin - case (guard__h278294) - 2'b0: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 = - _theResult___snd__h286293[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 = - _theResult___sfd__h286785; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160 or - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597 or - _theResult___snd__h286293) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h286863 = - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q160; - 3'd1: - _theResult___fst_sfd__h286863 = - CASE_guard78294_0b0_theResult___snd86293_BITS__ETC__q161; - 3'd2: - _theResult___fst_sfd__h286863 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6595; - 3'd3: - _theResult___fst_sfd__h286863 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6597; - 3'd4: _theResult___fst_sfd__h286863 = _theResult___snd__h286293[56:34]; - default: _theResult___fst_sfd__h286863 = 23'd0; - endcase - end - always@(guard__h269587 or - sfdin__h277680 or out_sfd__h278206 or _theResult___sfd__h278203) - begin - case (guard__h269587) - 2'b0, 2'b01: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - sfdin__h277680[56:34]; - 2'b10: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - out_sfd__h278206; - 2'b11: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 = - _theResult___sfd__h278203; - endcase - end - always@(guard__h269587 or sfdin__h277680 or _theResult___sfd__h278203) - begin - case (guard__h269587) - 2'b0: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 = - sfdin__h277680[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 = - _theResult___sfd__h278203; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162 or - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576 or - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578 or - sfdin__h277680) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h278281 = - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q162; - 3'd1: - _theResult___fst_sfd__h278281 = - CASE_guard69587_0b0_sfdin77680_BITS_56_TO_34_0_ETC__q163; - 3'd2: - _theResult___fst_sfd__h278281 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6576; - 3'd3: - _theResult___fst_sfd__h278281 = - IF_IF_IF_IF_0b0_CONCAT_NOT_resWire_wget__410_B_ETC___d6578; - 3'd4: _theResult___fst_sfd__h278281 = sfdin__h277680[56:34]; - default: _theResult___fst_sfd__h278281 = 23'd0; - endcase - end - always@(guard__h287224 or - sfdin__h295446 or out_sfd__h295972 or _theResult___sfd__h295969) - begin - case (guard__h287224) - 2'b0, 2'b01: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - sfdin__h295446[56:34]; - 2'b10: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - out_sfd__h295972; - 2'b11: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 = - _theResult___sfd__h295969; - endcase - end - always@(guard__h287224 or sfdin__h295446 or _theResult___sfd__h295969) - begin - case (guard__h287224) - 2'b0: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 = - sfdin__h295446[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 = - _theResult___sfd__h295969; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164 or - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622 or - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624 or - sfdin__h295446) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h296047 = - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q164; - 3'd1: - _theResult___fst_sfd__h296047 = - CASE_guard87224_0b0_sfdin95446_BITS_56_TO_34_0_ETC__q165; - 3'd2: - _theResult___fst_sfd__h296047 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6622; - 3'd3: - _theResult___fst_sfd__h296047 = - IF_IF_IF_IF_3970_MINUS_SEXT_resWire_wget__410__ETC___d6624; - 3'd4: _theResult___fst_sfd__h296047 = sfdin__h295446[56:34]; - default: _theResult___fst_sfd__h296047 = 23'd0; - endcase - end - always@(guard__h296060 or - _theResult___snd__h304083 or - out_sfd__h304608 or _theResult___sfd__h304605) - begin - case (guard__h296060) - 2'b0, 2'b01: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - _theResult___snd__h304083[56:34]; - 2'b10: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - out_sfd__h304608; - 2'b11: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 = - _theResult___sfd__h304605; - endcase - end - always@(guard__h296060 or - _theResult___snd__h304083 or _theResult___sfd__h304605) - begin - case (guard__h296060) - 2'b0: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 = - _theResult___snd__h304083[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 = - _theResult___sfd__h304605; - endcase - end - always@(rmdFifo$D_OUT or - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166 or - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641 or - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643 or - _theResult___snd__h304083) - begin - case (rmdFifo$D_OUT) - 3'd0: - _theResult___fst_sfd__h304683 = - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q166; - 3'd1: - _theResult___fst_sfd__h304683 = - CASE_guard96060_0b0_theResult___snd04083_BITS__ETC__q167; - 3'd2: - _theResult___fst_sfd__h304683 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6641; - 3'd3: - _theResult___fst_sfd__h304683 = - IF_IF_IF_resWire_wget__410_BITS_67_TO_57_416_E_ETC___d6643; - 3'd4: _theResult___fst_sfd__h304683 = _theResult___snd__h304083[56:34]; - default: _theResult___fst_sfd__h304683 = 23'd0; - endcase - end - always@(fpu_div64_fState_S4$D_OUT) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 = - fpu_div64_fState_S4$D_OUT[65]; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 = - fpu_div64_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_div64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_div64_fState_S4$D_OUT[65]) ? - fpu_div64_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - 3'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[64:2] : - (fpu_div64_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 : - fpu_div64_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - fpu_div64_fState_S4$D_OUT[64:2]; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 = - 63'd0; - endcase - end - always@(fpu_div64_fState_S4$D_OUT) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 = - fpu_div64_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 = - fpu_div64_fState_S4$D_OUT[1:0] == 2'b11 && - fpu_div64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - fpu_div64_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - fpu_div64_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980 : - fpu_div64_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 = - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980) - begin - case (fpu_div64_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 = - IF_0b0_CONCAT_NOT_fpu_div64_fState_S4_first__4_ETC___d980; - endcase - end - always@(fpu_div64_fState_S4$D_OUT or - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168 or - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 or - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172) - begin - case (fpu_div64_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - { CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q170, - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q171 }; - 3'd1: - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - (fpu_div64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_div64_fState_S4$D_OUT[65:2] : - { (fpu_div64_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_div64_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_div64_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_div64_fState_S4$D_OUT[65], - CASE_fpu_div64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q172 }; - default: CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q173 = - { CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q168, - CASE_fpu_div64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q169 }; - endcase - end - always@(fpu_div64_fState_S3$D_OUT) - begin - case (fpu_div64_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1, 3'd2, 3'd3: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174 = - fpu_div64_fState_S3$D_OUT[121]; - default: CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q174 = - fpu_div64_fState_S3$D_OUT[124:122] == 3'd4 && - fpu_div64_fState_S3$D_OUT[121]; - endcase - end - always@(fpu_div64_fState_S3$D_OUT) - begin - case (fpu_div64_fState_S3$D_OUT[124:122]) - 3'd0, 3'd1: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'h7FF0000000000000; - 3'd2: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - fpu_div64_fState_S3$D_OUT[121] ? - 63'h7FEFFFFFFFFFFFFF : - 63'h7FF0000000000000; - 3'd3: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - fpu_div64_fState_S3$D_OUT[121] ? - 63'h7FF0000000000000 : - 63'h7FEFFFFFFFFFFFFF; - 3'd4: - CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'h7FEFFFFFFFFFFFFF; - default: CASE_fpu_div64_fState_S3D_OUT_BITS_124_TO_122_ETC__q175 = - 63'd0; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848 or - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330 or - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378) - begin - case (iFifo$D_OUT[3:0]) - 4'd0: - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330; - 4'd1: - CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - iFifo$D_OUT[136] ? - IF_iFifo_first__087_BITS_102_TO_95_625_EQ_255__ETC___d5378 : - { iFifo$D_OUT[136] || !iFifo$D_OUT[135], - iFifo$D_OUT[134:72] }; - default: CASE_iFifoD_OUT_BITS_3_TO_0_0_IF_iFifo_first__ETC__q176 = - IF_iFifo_first__087_BIT_201_115_THEN_IF_iFifo__ETC___d3848; - endcase - end - always@(iFifo$D_OUT or - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330) - begin - case (iFifo$D_OUT[3:0]) - 4'd0, 4'd1: - CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 = - 64'h3FF0000000000000; - default: CASE_iFifoD_OUT_BITS_3_TO_0_0_460718241880001_ETC__q177 = - IF_iFifo_first__087_BIT_136_624_THEN_IF_iFifo__ETC___d5330; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd2, 3'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 = - fpu_sqr64_fState_S4$D_OUT[65]; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 = - fpu_sqr64_fState_S4$D_OUT[68:66] == 3'd4 && - fpu_sqr64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd2: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0 || - fpu_sqr64_fState_S4$D_OUT[65]) ? - fpu_sqr64_fState_S4$D_OUT[64:2] : - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - 3'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[64:2] : - (fpu_sqr64_fState_S4$D_OUT[65] ? - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 : - fpu_sqr64_fState_S4$D_OUT[64:2]); - 3'd4: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - fpu_sqr64_fState_S4$D_OUT[64:2]; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 = - 63'd0; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01, 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 = - fpu_sqr64_fState_S4$D_OUT[65]; - 2'd3: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 = - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b11 && - fpu_sqr64_fState_S4$D_OUT[65]; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'b0, 2'b01: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - fpu_sqr64_fState_S4$D_OUT[64:2]; - 2'b10: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - fpu_sqr64_fState_S4$D_OUT[2] ? - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724 : - fpu_sqr64_fState_S4$D_OUT[64:2]; - 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 = - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724) - begin - case (fpu_sqr64_fState_S4$D_OUT[1:0]) - 2'd0: CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 = 63'd0; - 2'b01, 2'b10, 2'b11: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 = - IF_0b0_CONCAT_NOT_fpu_sqr64_fState_S4_first__6_ETC___d1724; - endcase - end - always@(fpu_sqr64_fState_S4$D_OUT or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 or - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182) - begin - case (fpu_sqr64_fState_S4$D_OUT[68:66]) - 3'd0: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - { CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q180, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0b0_ETC__q181 }; - 3'd1: - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b0) ? - fpu_sqr64_fState_S4$D_OUT[65:2] : - { (fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b01 || - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b10 || - fpu_sqr64_fState_S4$D_OUT[1:0] == 2'b11) && - fpu_sqr64_fState_S4$D_OUT[65], - CASE_fpu_sqr64_fState_S4D_OUT_BITS_1_TO_0_0_0_ETC__q182 }; - default: CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_0_ETC__q183 = - { CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q178, - CASE_fpu_sqr64_fState_S4D_OUT_BITS_68_TO_66_2_ETC__q179 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - crg_done <= `BSV_ASSIGNMENT_DELAY 1'd0; - crg_done_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (crg_done$EN) crg_done <= `BSV_ASSIGNMENT_DELAY crg_done$D_IN; - if (crg_done_1$EN) - crg_done_1 <= `BSV_ASSIGNMENT_DELAY crg_done_1$D_IN; - if (rg_busy$EN) rg_busy <= `BSV_ASSIGNMENT_DELAY rg_busy$D_IN; - if (rg_busy_1$EN) rg_busy_1 <= `BSV_ASSIGNMENT_DELAY rg_busy_1$D_IN; - end - if (rg_b$EN) rg_b <= `BSV_ASSIGNMENT_DELAY rg_b$D_IN; - if (rg_d$EN) rg_d <= `BSV_ASSIGNMENT_DELAY rg_d$D_IN; - if (rg_index$EN) rg_index <= `BSV_ASSIGNMENT_DELAY rg_index$D_IN; - if (rg_index_1$EN) rg_index_1 <= `BSV_ASSIGNMENT_DELAY rg_index_1$D_IN; - if (rg_q$EN) rg_q <= `BSV_ASSIGNMENT_DELAY rg_q$D_IN; - if (rg_r$EN) rg_r <= `BSV_ASSIGNMENT_DELAY rg_r$D_IN; - if (rg_r_1$EN) rg_r_1 <= `BSV_ASSIGNMENT_DELAY rg_r_1$D_IN; - if (rg_res$EN) rg_res <= `BSV_ASSIGNMENT_DELAY rg_res$D_IN; - if (rg_s$EN) rg_s <= `BSV_ASSIGNMENT_DELAY rg_s$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - crg_done = 1'h0; - crg_done_1 = 1'h0; - rg_b = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_busy = 1'h0; - rg_busy_1 = 1'h0; - rg_d = 58'h2AAAAAAAAAAAAAA; - rg_index = 6'h2A; - rg_index_1 = 6'h2A; - rg_q = 58'h2AAAAAAAAAAAAAA; - rg_r = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_r_1 = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_res = 117'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_s = 116'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (fpu_div64_fResult_S5$EMPTY_N && fpu_madd_fResult_S9$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 29: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResDiv] and\n [RL_getResMAdd] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fpu_div64_fResult_S5$EMPTY_N && fpu_sqr64_fResult_S5$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 29: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResDiv] and [RL_getResSqr]\n ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fpu_sqr64_fResult_S5$EMPTY_N && fpu_madd_fResult_S9$EMPTY_N) - $display("Error: \"../../src_Core/CPU/FPU.bsv\", line 109, column 40: (R0001)\n Mutually exclusive rules (from the ME sets [RL_getResSqr] and\n [RL_getResMAdd] ) fired in the same clock cycle.\n"); - end - // synopsys translate_on -endmodule // mkFPU - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric.v deleted file mode 100644 index 771fc0dc..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric.v +++ /dev/null @@ -1,8149 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 = - fabric_cfg_verbosity > 4'd1 ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - $display("%0d: %m::AXI4_Fabric.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v deleted file mode 100644 index 8c7d9af3..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v +++ /dev/null @@ -1,7465 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_2x3(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8650; - reg [31 : 0] v__h9025; - reg [31 : 0] v__h9400; - reg [31 : 0] v__h9845; - reg [31 : 0] v__h10214; - reg [31 : 0] v__h10583; - reg [31 : 0] v__h11872; - reg [31 : 0] v__h12325; - reg [31 : 0] v__h12702; - reg [31 : 0] v__h12994; - reg [31 : 0] v__h13286; - reg [31 : 0] v__h13589; - reg [31 : 0] v__h13855; - reg [31 : 0] v__h14121; - reg [31 : 0] v__h14385; - reg [31 : 0] v__h14611; - reg [31 : 0] v__h15040; - reg [31 : 0] v__h15396; - reg [31 : 0] v__h15752; - reg [31 : 0] v__h16169; - reg [31 : 0] v__h16501; - reg [31 : 0] v__h16833; - reg [31 : 0] v__h17849; - reg [31 : 0] v__h18100; - reg [31 : 0] v__h18475; - reg [31 : 0] v__h18716; - reg [31 : 0] v__h19091; - reg [31 : 0] v__h19332; - reg [31 : 0] v__h19694; - reg [31 : 0] v__h19945; - reg [31 : 0] v__h20275; - reg [31 : 0] v__h20516; - reg [31 : 0] v__h20846; - reg [31 : 0] v__h21087; - reg [31 : 0] v__h21600; - reg [31 : 0] v__h22001; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8644; - reg [31 : 0] v__h9019; - reg [31 : 0] v__h9394; - reg [31 : 0] v__h9839; - reg [31 : 0] v__h10208; - reg [31 : 0] v__h10577; - reg [31 : 0] v__h11866; - reg [31 : 0] v__h12319; - reg [31 : 0] v__h12696; - reg [31 : 0] v__h12988; - reg [31 : 0] v__h13280; - reg [31 : 0] v__h13583; - reg [31 : 0] v__h13849; - reg [31 : 0] v__h14115; - reg [31 : 0] v__h14379; - reg [31 : 0] v__h14605; - reg [31 : 0] v__h15034; - reg [31 : 0] v__h15390; - reg [31 : 0] v__h15746; - reg [31 : 0] v__h16163; - reg [31 : 0] v__h16495; - reg [31 : 0] v__h16827; - reg [31 : 0] v__h17843; - reg [31 : 0] v__h18094; - reg [31 : 0] v__h18469; - reg [31 : 0] v__h18710; - reg [31 : 0] v__h19085; - reg [31 : 0] v__h19326; - reg [31 : 0] v__h19688; - reg [31 : 0] v__h19939; - reg [31 : 0] v__h20269; - reg [31 : 0] v__h20510; - reg [31 : 0] v__h20840; - reg [31 : 0] v__h21081; - reg [31 : 0] v__h21594; - reg [31 : 0] v__h21995; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11777, - x__h12230, - x__h17986, - x__h18612, - x__h19228, - x__h21532, - x__h21933; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - x1_avValue_rresp__h17964, - x1_avValue_rresp__h18590, - x1_avValue_rresp__h19206; - wire _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156, - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371, - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411, - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540, - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - 8'd0 : - x__h17986 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - 8'd0 : - x__h18612 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - 8'd0 : - x__h19228 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? - 8'd0 : - x__h11777 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ? - 8'd0 : - x__h12230 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ? - 8'd0 : - x__h21532 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ? - 8'd0 : - x__h21933 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - x1_avValue_rresp__h17964 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - x1_avValue_rresp__h18590 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - x1_avValue_rresp__h19206 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h17964 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18590 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19206 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11777 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12230 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h17986 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h18612 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19228 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21532 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h21933 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8650 = $stime; - #0; - end - v__h8644 = v__h8650 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8644, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9025 = $stime; - #0; - end - v__h9019 = v__h9025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9019, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9400 = $stime; - #0; - end - v__h9394 = v__h9400 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9394, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9845 = $stime; - #0; - end - v__h9839 = v__h9845 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9839, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10214 = $stime; - #0; - end - v__h10208 = v__h10214 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10208, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10583 = $stime; - #0; - end - v__h10577 = v__h10583 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10577, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h11872 = $stime; - #0; - end - v__h11866 = v__h11872 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h11866, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12325 = $stime; - #0; - end - v__h12319 = v__h12325 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12319, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12702 = $stime; - #0; - end - v__h12696 = v__h12702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12696, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h12994 = $stime; - #0; - end - v__h12988 = v__h12994 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12988, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13286 = $stime; - #0; - end - v__h13280 = v__h13286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13280, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13589 = $stime; - #0; - end - v__h13583 = v__h13589 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13583, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13855 = $stime; - #0; - end - v__h13849 = v__h13855 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13849, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14121 = $stime; - #0; - end - v__h14115 = v__h14121 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14115, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14385 = $stime; - #0; - end - v__h14379 = v__h14385 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14379, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14611 = $stime; - #0; - end - v__h14605 = v__h14611 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14605, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15040 = $stime; - #0; - end - v__h15034 = v__h15040 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15034, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15396 = $stime; - #0; - end - v__h15390 = v__h15396 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15390, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15752 = $stime; - #0; - end - v__h15746 = v__h15752 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15746, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16169 = $stime; - #0; - end - v__h16163 = v__h16169 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16163, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16501 = $stime; - #0; - end - v__h16495 = v__h16501 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16495, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16833 = $stime; - #0; - end - v__h16827 = v__h16833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16827, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h17849 = $stime; - #0; - end - v__h17843 = v__h17849 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h17843, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18100 = $stime; - #0; - end - v__h18094 = v__h18100 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18094, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18475 = $stime; - #0; - end - v__h18469 = v__h18475 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18469, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h18716 = $stime; - #0; - end - v__h18710 = v__h18716 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18710, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19091 = $stime; - #0; - end - v__h19085 = v__h19091 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19085, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19332 = $stime; - #0; - end - v__h19326 = v__h19332 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19326, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h19694 = $stime; - #0; - end - v__h19688 = v__h19694 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19688, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19945 = $stime; - #0; - end - v__h19939 = v__h19945 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19939, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20275 = $stime; - #0; - end - v__h20269 = v__h20275 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20269, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20516 = $stime; - #0; - end - v__h20510 = v__h20516 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20510, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h20846 = $stime; - #0; - end - v__h20840 = v__h20846 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20840, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21087 = $stime; - #0; - end - v__h21081 = v__h21087 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21081, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21600 = $stime; - #0; - end - v__h21594 = v__h21600 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21594, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22001 = $stime; - #0; - end - v__h21995 = v__h22001 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21995, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_2x3 - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v deleted file mode 100644 index ac19188b..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v +++ /dev/null @@ -1,8145 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_AXI4(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_AXI4 - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v deleted file mode 100644 index 5d5bbfb6..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v +++ /dev/null @@ -1,249 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 64 -// read_rs1_port2 O 64 -// read_rs2 O 64 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// Combinational paths from inputs to outputs: -// read_rs1_rs1 -> read_rs1 -// read_rs1_port2_rs1 -> read_rs1_port2 -// read_rs2_rs2 -> read_rs2 -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkGPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [63 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [63 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [63 : 0] read_rs2; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [63 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [63 : 0] read_rs1, read_rs1_port2, read_rs2; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [63 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_3 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = - (read_rs1_port2_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_2 ; - - // value method read_rs2 - assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 64'd0 : regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd64), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs2_rs2 ; - assign regfile$ADDR_2 = read_rs1_port2_rs1 ; - assign regfile$ADDR_3 = read_rs1_rs1 ; - assign regfile$ADDR_4 = 5'h0 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkGPR_RegFile - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v deleted file mode 100644 index f4d13fdd..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 64 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 32 -// put_args_y_is_signed I 1 -// put_args_y I 32 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_32(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [31 : 0] put_args_x; - input put_args_y_is_signed; - input [31 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [63 : 0] result_value; - - // signals for module outputs - wire [63 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [63 : 0] m_rg_x; - wire [63 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [63 : 0] m_rg_xy; - wire [63 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [31 : 0] m_rg_y; - wire [31 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [63 : 0] xy___1__h654; - wire [31 : 0] _theResult___fst__h491, - _theResult___fst__h494, - _theResult___fst__h536, - _theResult___fst__h539, - _theResult___snd_fst__h531; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 32'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h654 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 32'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h491 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h539 : - _theResult___snd_fst__h531 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[31] != put_args_y[31] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 = - put_args_x_is_signed ? - put_args_x[31] : - put_args_y_is_signed && put_args_y[31] ; - assign _theResult___fst__h491 = - put_args_x_is_signed ? _theResult___fst__h494 : put_args_x ; - assign _theResult___fst__h494 = put_args_x[31] ? -put_args_x : put_args_x ; - assign _theResult___fst__h536 = - put_args_y_is_signed ? _theResult___fst__h539 : put_args_y ; - assign _theResult___fst__h539 = put_args_y[31] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h531 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h536 ; - assign xy___1__h654 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 64'hAAAAAAAAAAAAAAAA; - m_rg_xy = 64'hAAAAAAAAAAAAAAAA; - m_rg_y = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_32 - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v deleted file mode 100644 index 0b513191..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 128 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 64 -// put_args_y_is_signed I 1 -// put_args_y I 64 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_64(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [63 : 0] put_args_x; - input put_args_y_is_signed; - input [63 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [127 : 0] result_value; - - // signals for module outputs - wire [127 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [127 : 0] m_rg_x; - wire [127 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [127 : 0] m_rg_xy; - wire [127 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [63 : 0] m_rg_y; - wire [63 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [127 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [127 : 0] xy___1__h648; - wire [63 : 0] _theResult___fst__h488, - _theResult___fst__h491, - _theResult___fst__h533, - _theResult___fst__h536, - _theResult___snd_fst__h528; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 64'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h648 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 64'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h488 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h536 : - _theResult___snd_fst__h528 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[63] != put_args_y[63] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 = - put_args_x_is_signed ? - put_args_x[63] : - put_args_y_is_signed && put_args_y[63] ; - assign _theResult___fst__h488 = - put_args_x_is_signed ? _theResult___fst__h491 : put_args_x ; - assign _theResult___fst__h491 = put_args_x[63] ? -put_args_x : put_args_x ; - assign _theResult___fst__h533 = - put_args_y_is_signed ? _theResult___fst__h536 : put_args_y ; - assign _theResult___fst__h536 = put_args_y[63] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h528 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h533 ; - assign xy___1__h648 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_y = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_64 - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v deleted file mode 100644 index d0653fb5..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v +++ /dev/null @@ -1,8181 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// valid O 1 -// addr O 64 reg -// word64 O 64 -// st_amo_val O 64 -// exc O 1 -// exc_code O 4 reg -// RDY_server_flush_request_put O 1 reg -// RDY_server_flush_response_get O 1 -// RDY_tlb_flush O 1 const -// mem_master_awvalid O 1 -// mem_master_awid O 4 reg -// mem_master_awaddr O 64 reg -// mem_master_awlen O 8 reg -// mem_master_awsize O 3 reg -// mem_master_awburst O 2 reg -// mem_master_awlock O 1 reg -// mem_master_awcache O 4 reg -// mem_master_awprot O 3 reg -// mem_master_awqos O 4 reg -// mem_master_awregion O 4 reg -// mem_master_wvalid O 1 -// mem_master_wid O 4 reg -// mem_master_wdata O 64 reg -// mem_master_wstrb O 8 reg -// mem_master_wlast O 1 reg -// mem_master_bready O 1 -// mem_master_arvalid O 1 -// mem_master_arid O 4 reg -// mem_master_araddr O 64 reg -// mem_master_arlen O 8 reg -// mem_master_arsize O 3 reg -// mem_master_arburst O 2 reg -// mem_master_arlock O 1 reg -// mem_master_arcache O 4 reg -// mem_master_arprot O 3 reg -// mem_master_arqos O 4 reg -// mem_master_arregion O 4 reg -// mem_master_rready O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_op I 2 -// req_f3 I 3 -// req_amo_funct7 I 7 reg -// req_addr I 64 -// req_st_value I 64 -// req_priv I 2 reg -// req_sstatus_SUM I 1 reg -// req_mstatus_MXR I 1 reg -// req_satp I 64 reg -// mem_master_awready I 1 -// mem_master_wready I 1 -// mem_master_bvalid I 1 -// mem_master_bid I 4 reg -// mem_master_bresp I 2 reg -// mem_master_arready I 1 -// mem_master_rvalid I 1 -// mem_master_rid I 4 reg -// mem_master_rdata I 64 reg -// mem_master_rresp I 2 reg -// mem_master_rlast I 1 reg -// EN_set_verbosity I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// EN_server_flush_request_put I 1 -// EN_server_flush_response_get I 1 -// EN_tlb_flush I 1 -// -// Combinational paths from inputs to outputs: -// (mem_master_awready, mem_master_wready) -> valid -// (mem_master_awready, mem_master_wready) -> word64 -// (mem_master_awready, mem_master_wready) -> st_amo_val -// (mem_master_awready, mem_master_wready) -> mem_master_bready -// (mem_master_awready, -// mem_master_wready, -// mem_master_arready, -// EN_req) -> mem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMMU_Cache(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_op, - req_f3, - req_amo_funct7, - req_addr, - req_st_value, - req_priv, - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - EN_req, - - valid, - - addr, - - word64, - - st_amo_val, - - exc, - - exc_code, - - EN_server_flush_request_put, - RDY_server_flush_request_put, - - EN_server_flush_response_get, - RDY_server_flush_response_get, - - EN_tlb_flush, - RDY_tlb_flush, - - mem_master_awvalid, - - mem_master_awid, - - mem_master_awaddr, - - mem_master_awlen, - - mem_master_awsize, - - mem_master_awburst, - - mem_master_awlock, - - mem_master_awcache, - - mem_master_awprot, - - mem_master_awqos, - - mem_master_awregion, - - mem_master_awready, - - mem_master_wvalid, - - mem_master_wid, - - mem_master_wdata, - - mem_master_wstrb, - - mem_master_wlast, - - mem_master_wready, - - mem_master_bvalid, - mem_master_bid, - mem_master_bresp, - - mem_master_bready, - - mem_master_arvalid, - - mem_master_arid, - - mem_master_araddr, - - mem_master_arlen, - - mem_master_arsize, - - mem_master_arburst, - - mem_master_arlock, - - mem_master_arcache, - - mem_master_arprot, - - mem_master_arqos, - - mem_master_arregion, - - mem_master_arready, - - mem_master_rvalid, - mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast, - - mem_master_rready); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [1 : 0] req_op; - input [2 : 0] req_f3; - input [6 : 0] req_amo_funct7; - input [63 : 0] req_addr; - input [63 : 0] req_st_value; - input [1 : 0] req_priv; - input req_sstatus_SUM; - input req_mstatus_MXR; - input [63 : 0] req_satp; - input EN_req; - - // value method valid - output valid; - - // value method addr - output [63 : 0] addr; - - // value method word64 - output [63 : 0] word64; - - // value method st_amo_val - output [63 : 0] st_amo_val; - - // value method exc - output exc; - - // value method exc_code - output [3 : 0] exc_code; - - // action method server_flush_request_put - input EN_server_flush_request_put; - output RDY_server_flush_request_put; - - // action method server_flush_response_get - input EN_server_flush_response_get; - output RDY_server_flush_response_get; - - // action method tlb_flush - input EN_tlb_flush; - output RDY_tlb_flush; - - // value method mem_master_m_awvalid - output mem_master_awvalid; - - // value method mem_master_m_awid - output [3 : 0] mem_master_awid; - - // value method mem_master_m_awaddr - output [63 : 0] mem_master_awaddr; - - // value method mem_master_m_awlen - output [7 : 0] mem_master_awlen; - - // value method mem_master_m_awsize - output [2 : 0] mem_master_awsize; - - // value method mem_master_m_awburst - output [1 : 0] mem_master_awburst; - - // value method mem_master_m_awlock - output mem_master_awlock; - - // value method mem_master_m_awcache - output [3 : 0] mem_master_awcache; - - // value method mem_master_m_awprot - output [2 : 0] mem_master_awprot; - - // value method mem_master_m_awqos - output [3 : 0] mem_master_awqos; - - // value method mem_master_m_awregion - output [3 : 0] mem_master_awregion; - - // value method mem_master_m_awuser - - // action method mem_master_m_awready - input mem_master_awready; - - // value method mem_master_m_wvalid - output mem_master_wvalid; - - // value method mem_master_m_wid - output [3 : 0] mem_master_wid; - - // value method mem_master_m_wdata - output [63 : 0] mem_master_wdata; - - // value method mem_master_m_wstrb - output [7 : 0] mem_master_wstrb; - - // value method mem_master_m_wlast - output mem_master_wlast; - - // value method mem_master_m_wuser - - // action method mem_master_m_wready - input mem_master_wready; - - // action method mem_master_m_bvalid - input mem_master_bvalid; - input [3 : 0] mem_master_bid; - input [1 : 0] mem_master_bresp; - - // value method mem_master_m_bready - output mem_master_bready; - - // value method mem_master_m_arvalid - output mem_master_arvalid; - - // value method mem_master_m_arid - output [3 : 0] mem_master_arid; - - // value method mem_master_m_araddr - output [63 : 0] mem_master_araddr; - - // value method mem_master_m_arlen - output [7 : 0] mem_master_arlen; - - // value method mem_master_m_arsize - output [2 : 0] mem_master_arsize; - - // value method mem_master_m_arburst - output [1 : 0] mem_master_arburst; - - // value method mem_master_m_arlock - output mem_master_arlock; - - // value method mem_master_m_arcache - output [3 : 0] mem_master_arcache; - - // value method mem_master_m_arprot - output [2 : 0] mem_master_arprot; - - // value method mem_master_m_arqos - output [3 : 0] mem_master_arqos; - - // value method mem_master_m_arregion - output [3 : 0] mem_master_arregion; - - // value method mem_master_m_aruser - - // action method mem_master_m_arready - input mem_master_arready; - - // action method mem_master_m_rvalid - input mem_master_rvalid; - input [3 : 0] mem_master_rid; - input [63 : 0] mem_master_rdata; - input [1 : 0] mem_master_rresp; - input mem_master_rlast; - - // value method mem_master_m_rready - output mem_master_rready; - - // signals for module outputs - reg [63 : 0] word64; - wire [63 : 0] addr, - mem_master_araddr, - mem_master_awaddr, - mem_master_wdata, - st_amo_val; - wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; - wire [3 : 0] exc_code, - mem_master_arcache, - mem_master_arid, - mem_master_arqos, - mem_master_arregion, - mem_master_awcache, - mem_master_awid, - mem_master_awqos, - mem_master_awregion, - mem_master_wid; - wire [2 : 0] mem_master_arprot, - mem_master_arsize, - mem_master_awprot, - mem_master_awsize; - wire [1 : 0] mem_master_arburst, mem_master_awburst; - wire RDY_server_flush_request_put, - RDY_server_flush_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_verbosity, - RDY_tlb_flush, - exc, - mem_master_arlock, - mem_master_arvalid, - mem_master_awlock, - mem_master_awvalid, - mem_master_bready, - mem_master_rready, - mem_master_wlast, - mem_master_wvalid, - valid; - - // inlined wires - reg [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1; - wire [10 : 0] crg_sb_to_load_delay$port0__write_1, - crg_sb_to_load_delay$port2__read; - wire [3 : 0] ctr_wr_rsps_pending_crg$port1__write_1, - ctr_wr_rsps_pending_crg$port2__read, - ctr_wr_rsps_pending_crg$port3__read; - wire crg_sb_to_load_delay$EN_port1__write, - ctr_wr_rsps_pending_crg$EN_port0__write, - ctr_wr_rsps_pending_crg$EN_port2__write, - dw_valid$whas, - master_xactor_crg_rd_addr_full$EN_port0__write, - master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port1__read, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port0__write, - master_xactor_crg_rd_data_full$EN_port1__write, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port1__read, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port0__write, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$EN_port2__write, - master_xactor_crg_wr_addr_full$port1__read, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port0__write, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$EN_port2__write, - master_xactor_crg_wr_data_full$port1__read, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read, - master_xactor_crg_wr_resp_full$EN_port0__write, - master_xactor_crg_wr_resp_full$EN_port2__write, - master_xactor_crg_wr_resp_full$port1__read, - master_xactor_crg_wr_resp_full$port2__read, - master_xactor_crg_wr_resp_full$port3__read; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_sb_to_load_delay - reg [10 : 0] crg_sb_to_load_delay; - wire [10 : 0] crg_sb_to_load_delay$D_IN; - wire crg_sb_to_load_delay$EN; - - // register ctr_wr_rsps_pending_crg - reg [3 : 0] ctr_wr_rsps_pending_crg; - wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN; - wire ctr_wr_rsps_pending_crg$EN; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - reg [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - reg [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [76 : 0] master_xactor_rg_wr_data; - reg [76 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - - // register rg_addr - reg [63 : 0] rg_addr; - wire [63 : 0] rg_addr$D_IN; - wire rg_addr$EN; - - // register rg_amo_funct7 - reg [6 : 0] rg_amo_funct7; - wire [6 : 0] rg_amo_funct7$D_IN; - wire rg_amo_funct7$EN; - - // register rg_cset_in_cache - reg [5 : 0] rg_cset_in_cache; - wire [5 : 0] rg_cset_in_cache$D_IN; - wire rg_cset_in_cache$EN; - - // register rg_error_during_refill - reg rg_error_during_refill; - wire rg_error_during_refill$D_IN, rg_error_during_refill$EN; - - // register rg_exc_code - reg [3 : 0] rg_exc_code; - reg [3 : 0] rg_exc_code$D_IN; - wire rg_exc_code$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_ld_val - reg [63 : 0] rg_ld_val; - reg [63 : 0] rg_ld_val$D_IN; - wire rg_ld_val$EN; - - // register rg_lower_word32 - reg [31 : 0] rg_lower_word32; - wire [31 : 0] rg_lower_word32$D_IN; - wire rg_lower_word32$EN; - - // register rg_lower_word32_full - reg rg_lower_word32_full; - wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN; - - // register rg_lrsc_pa - reg [63 : 0] rg_lrsc_pa; - wire [63 : 0] rg_lrsc_pa$D_IN; - wire rg_lrsc_pa$EN; - - // register rg_lrsc_valid - reg rg_lrsc_valid; - wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_op - reg [1 : 0] rg_op; - wire [1 : 0] rg_op$D_IN; - wire rg_op$EN; - - // register rg_pa - reg [63 : 0] rg_pa; - wire [63 : 0] rg_pa$D_IN; - wire rg_pa$EN; - - // register rg_priv - reg [1 : 0] rg_priv; - wire [1 : 0] rg_priv$D_IN; - wire rg_priv$EN; - - // register rg_pte_pa - reg [63 : 0] rg_pte_pa; - reg [63 : 0] rg_pte_pa$D_IN; - wire rg_pte_pa$EN; - - // register rg_satp - reg [63 : 0] rg_satp; - wire [63 : 0] rg_satp$D_IN; - wire rg_satp$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_st_amo_val - reg [63 : 0] rg_st_amo_val; - wire [63 : 0] rg_st_amo_val$D_IN; - wire rg_st_amo_val$EN; - - // register rg_state - reg [4 : 0] rg_state; - reg [4 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_word64_set_in_cache - reg [8 : 0] rg_word64_set_in_cache; - wire [8 : 0] rg_word64_set_in_cache$D_IN; - wire rg_word64_set_in_cache$EN; - - // ports of submodule f_pte_writebacks - wire [127 : 0] f_pte_writebacks$D_IN, f_pte_writebacks$D_OUT; - wire f_pte_writebacks$CLR, - f_pte_writebacks$DEQ, - f_pte_writebacks$EMPTY_N, - f_pte_writebacks$ENQ, - f_pte_writebacks$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule ram_state_and_ctag_cset - wire [52 : 0] ram_state_and_ctag_cset$DIA, - ram_state_and_ctag_cset$DIB, - ram_state_and_ctag_cset$DOB; - wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB; - wire ram_state_and_ctag_cset$ENA, - ram_state_and_ctag_cset$ENB, - ram_state_and_ctag_cset$WEA, - ram_state_and_ctag_cset$WEB; - - // ports of submodule ram_word64_set - reg [63 : 0] ram_word64_set$DIB; - reg [8 : 0] ram_word64_set$ADDRB; - wire [63 : 0] ram_word64_set$DIA, ram_word64_set$DOB; - wire [8 : 0] ram_word64_set$ADDRA; - wire ram_word64_set$ENA, - ram_word64_set$ENB, - ram_word64_set$WEA, - ram_word64_set$WEB; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - wire soc_map$m_is_mem_addr; - - // ports of submodule tlb - reg [1 : 0] tlb$insert_level; - wire [130 : 0] tlb$lookup; - wire [63 : 0] tlb$insert_pte, tlb$insert_pte_pa; - wire [26 : 0] tlb$insert_vpn, tlb$lookup_vpn; - wire [15 : 0] tlb$insert_asid, tlb$lookup_asid; - wire tlb$EN_flush, tlb$EN_insert, tlb$RDY_insert, tlb$RDY_lookup; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_ST_AMO_response, - CAN_FIRE_RL_rl_cache_refill_rsps_loop, - CAN_FIRE_RL_rl_discard_write_rsp, - CAN_FIRE_RL_rl_drive_exception_rsp, - CAN_FIRE_RL_rl_io_AMO_SC_req, - CAN_FIRE_RL_rl_io_AMO_op_req, - CAN_FIRE_RL_rl_io_AMO_read_rsp, - CAN_FIRE_RL_rl_io_read_req, - CAN_FIRE_RL_rl_io_read_rsp, - CAN_FIRE_RL_rl_io_write_req, - CAN_FIRE_RL_rl_maintain_io_read_rsp, - CAN_FIRE_RL_rl_probe_and_immed_rsp, - CAN_FIRE_RL_rl_ptw_level_0, - CAN_FIRE_RL_rl_ptw_level_1, - CAN_FIRE_RL_rl_ptw_level_2, - CAN_FIRE_RL_rl_rereq, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_shift_sb_to_load_delay, - CAN_FIRE_RL_rl_start_cache_refill, - CAN_FIRE_RL_rl_start_reset, - CAN_FIRE_RL_rl_start_tlb_refill, - CAN_FIRE_RL_rl_writeback_updated_PTE, - CAN_FIRE_mem_master_m_arready, - CAN_FIRE_mem_master_m_awready, - CAN_FIRE_mem_master_m_bvalid, - CAN_FIRE_mem_master_m_rvalid, - CAN_FIRE_mem_master_m_wready, - CAN_FIRE_req, - CAN_FIRE_server_flush_request_put, - CAN_FIRE_server_flush_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_verbosity, - CAN_FIRE_tlb_flush, - WILL_FIRE_RL_rl_ST_AMO_response, - WILL_FIRE_RL_rl_cache_refill_rsps_loop, - WILL_FIRE_RL_rl_discard_write_rsp, - WILL_FIRE_RL_rl_drive_exception_rsp, - WILL_FIRE_RL_rl_io_AMO_SC_req, - WILL_FIRE_RL_rl_io_AMO_op_req, - WILL_FIRE_RL_rl_io_AMO_read_rsp, - WILL_FIRE_RL_rl_io_read_req, - WILL_FIRE_RL_rl_io_read_rsp, - WILL_FIRE_RL_rl_io_write_req, - WILL_FIRE_RL_rl_maintain_io_read_rsp, - WILL_FIRE_RL_rl_probe_and_immed_rsp, - WILL_FIRE_RL_rl_ptw_level_0, - WILL_FIRE_RL_rl_ptw_level_1, - WILL_FIRE_RL_rl_ptw_level_2, - WILL_FIRE_RL_rl_rereq, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_shift_sb_to_load_delay, - WILL_FIRE_RL_rl_start_cache_refill, - WILL_FIRE_RL_rl_start_reset, - WILL_FIRE_RL_rl_start_tlb_refill, - WILL_FIRE_RL_rl_writeback_updated_PTE, - WILL_FIRE_mem_master_m_arready, - WILL_FIRE_mem_master_m_awready, - WILL_FIRE_mem_master_m_bvalid, - WILL_FIRE_mem_master_m_rvalid, - WILL_FIRE_mem_master_m_wready, - WILL_FIRE_req, - WILL_FIRE_server_flush_request_put, - WILL_FIRE_server_flush_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_verbosity, - WILL_FIRE_tlb_flush; - - // inputs to muxes for submodule ports - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2, - MUX_master_xactor_rg_rd_addr$write_1__VAL_3, - MUX_master_xactor_rg_rd_addr$write_1__VAL_4, - MUX_master_xactor_rg_rd_addr$write_1__VAL_5, - MUX_master_xactor_rg_wr_addr$write_1__VAL_1, - MUX_master_xactor_rg_wr_addr$write_1__VAL_2, - MUX_master_xactor_rg_wr_addr$write_1__VAL_4; - wire [76 : 0] MUX_master_xactor_rg_wr_data$write_1__VAL_1, - MUX_master_xactor_rg_wr_data$write_1__VAL_2, - MUX_master_xactor_rg_wr_data$write_1__VAL_3, - MUX_master_xactor_rg_wr_data$write_1__VAL_4; - wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3, - MUX_ram_word64_set$a_put_3__VAL_2, - MUX_rg_ld_val$write_1__VAL_2; - wire [52 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1; - wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2, - MUX_ram_word64_set$b_put_2__VAL_4; - wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1; - wire [4 : 0] MUX_rg_state$write_1__VAL_10, - MUX_rg_state$write_1__VAL_11, - MUX_rg_state$write_1__VAL_12, - MUX_rg_state$write_1__VAL_13, - MUX_rg_state$write_1__VAL_14, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_6; - wire [3 : 0] MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_6; - wire MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1, - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2, - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_1, - MUX_dw_output_ld_val$wset_1__SEL_4, - MUX_dw_output_st_amo_val$wset_1__SEL_1, - MUX_master_xactor_rg_rd_addr$write_1__SEL_1, - MUX_master_xactor_rg_rd_addr$write_1__SEL_2, - MUX_master_xactor_rg_rd_addr$write_1__SEL_3, - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1, - MUX_ram_word64_set$a_put_3__SEL_1, - MUX_ram_word64_set$b_put_1__SEL_2, - MUX_rg_error_during_refill$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_2, - MUX_rg_exc_code$write_1__SEL_3, - MUX_rg_exc_code$write_1__SEL_5, - MUX_rg_exc_code$write_1__SEL_6, - MUX_rg_exc_code$write_1__SEL_7, - MUX_rg_exc_code$write_1__SEL_8, - MUX_rg_ld_val$write_1__SEL_2, - MUX_rg_lrsc_valid$write_1__SEL_2, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_14, - MUX_rg_state$write_1__SEL_18, - MUX_rg_state$write_1__SEL_3, - MUX_tlb$insert_1__SEL_1, - MUX_tlb$insert_1__SEL_2, - MUX_tlb$insert_1__SEL_3, - MUX_tlb$insert_1__SEL_4; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4708; - reg [31 : 0] v__h4809; - reg [31 : 0] v__h30746; - reg [31 : 0] v__h31644; - reg [31 : 0] v__h4339; - reg [31 : 0] v__h5262; - reg [31 : 0] v__h14971; - reg [31 : 0] v__h19190; - reg [31 : 0] v__h18615; - reg [31 : 0] v__h22626; - reg [31 : 0] v__h24225; - reg [31 : 0] v__h23982; - reg [31 : 0] v__h24536; - reg [31 : 0] v__h24648; - reg [31 : 0] v__h24154; - reg [31 : 0] v__h25282; - reg [31 : 0] v__h25042; - reg [31 : 0] v__h25705; - reg [31 : 0] v__h25593; - reg [31 : 0] v__h25211; - reg [31 : 0] v__h26177; - reg [31 : 0] v__h26248; - reg [31 : 0] v__h26330; - reg [31 : 0] v__h26106; - reg [31 : 0] v__h27239; - reg [31 : 0] v__h27461; - reg [31 : 0] v__h29434; - reg [31 : 0] v__h30534; - reg [31 : 0] v__h30641; - reg [31 : 0] v__h30826; - reg [31 : 0] v__h31348; - reg [31 : 0] v__h31762; - reg [31 : 0] v__h3705; - reg [31 : 0] v__h32080; - reg [31 : 0] v__h32255; - reg [31 : 0] v__h34868; - reg [31 : 0] v__h35120; - reg [31 : 0] v__h32351; - reg [31 : 0] v__h23262; - reg [31 : 0] v__h26457; - reg [31 : 0] v__h29060; - reg [31 : 0] v__h36090; - reg [31 : 0] v__h37244; - reg [31 : 0] v__h35740; - reg [31 : 0] v__h35701; - reg [31 : 0] v__h3699; - reg [31 : 0] v__h4333; - reg [31 : 0] v__h4702; - reg [31 : 0] v__h4803; - reg [31 : 0] v__h5256; - reg [31 : 0] v__h14965; - reg [31 : 0] v__h18609; - reg [31 : 0] v__h19184; - reg [31 : 0] v__h22620; - reg [31 : 0] v__h23256; - reg [31 : 0] v__h23976; - reg [31 : 0] v__h24148; - reg [31 : 0] v__h24219; - reg [31 : 0] v__h24530; - reg [31 : 0] v__h24642; - reg [31 : 0] v__h25036; - reg [31 : 0] v__h25205; - reg [31 : 0] v__h25276; - reg [31 : 0] v__h25587; - reg [31 : 0] v__h25699; - reg [31 : 0] v__h26100; - reg [31 : 0] v__h26171; - reg [31 : 0] v__h26242; - reg [31 : 0] v__h26324; - reg [31 : 0] v__h26451; - reg [31 : 0] v__h27233; - reg [31 : 0] v__h27455; - reg [31 : 0] v__h29054; - reg [31 : 0] v__h29428; - reg [31 : 0] v__h30528; - reg [31 : 0] v__h30635; - reg [31 : 0] v__h30740; - reg [31 : 0] v__h30820; - reg [31 : 0] v__h31342; - reg [31 : 0] v__h31638; - reg [31 : 0] v__h31756; - reg [31 : 0] v__h32074; - reg [31 : 0] v__h32249; - reg [31 : 0] v__h32345; - reg [31 : 0] v__h34862; - reg [31 : 0] v__h35114; - reg [31 : 0] v__h35695; - reg [31 : 0] v__h35734; - reg [31 : 0] v__h36084; - reg [31 : 0] v__h37238; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34, - CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35, - CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50, - CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30, - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33, - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755, - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630, - _theResult_____2__h19719, - _theResult_____2__h32673, - _theResult___fst__h6654, - ld_val__h29543, - mem_req_wr_data_wdata__h18986, - mem_req_wr_data_wdata__h22422, - mem_req_wr_data_wdata__h31144, - mem_req_wr_data_wdata__h32648, - new_ld_val__h32381, - new_value__h17706, - new_value__h7679, - w1__h19711, - w1__h32661, - w1__h32665; - reg [7 : 0] mem_req_wr_data_wstrb__h18987, mem_req_wr_data_wstrb__h32649; - reg [2 : 0] value__h31966, value__h34992; - reg CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285, - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211, - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245, - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225, - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297; - wire [63 : 0] IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563, - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694, - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d787, - _theResult___fst__h6279, - _theResult___fst__h6350, - _theResult___snd_fst__h18994, - _theResult___snd_fst__h22430, - _theResult___snd_fst__h31152, - _theResult___snd_fst__h32656, - _theResult___snd_fst__h6281, - _theResult___snd_fst__h6352, - _theResult___snd_fst__h6883, - cline_fabric_addr__h26510, - lev_0_pte_pa__h25314, - lev_0_pte_pa_w64_fa__h25316, - lev_1_PTN_pa__h24255, - lev_1_pte_pa__h24257, - lev_1_pte_pa_w64_fa__h24259, - lev_2_pte_pa__h23315, - lev_2_pte_pa_w64_fa__h23317, - new_st_val__h19441, - new_st_val__h19723, - new_st_val__h19814, - new_st_val__h20794, - new_st_val__h20798, - new_st_val__h20802, - new_st_val__h20806, - new_st_val__h20811, - new_st_val__h20817, - new_st_val__h20822, - new_st_val__h32677, - new_st_val__h32768, - new_st_val__h34628, - new_st_val__h34632, - new_st_val__h34636, - new_st_val__h34640, - new_st_val__h34645, - new_st_val__h34651, - new_st_val__h34656, - pa___1__h6660, - pa___1__h6709, - pa___1__h6778, - pte___1__h6932, - pte___1__h6960, - pte___2__h6652, - result__h14088, - result__h14116, - result__h14144, - result__h14172, - result__h14200, - result__h14228, - result__h14256, - result__h14301, - result__h14329, - result__h14357, - result__h14385, - result__h14413, - result__h14441, - result__h14469, - result__h14497, - result__h14542, - result__h14570, - result__h14598, - result__h14626, - result__h14667, - result__h14695, - result__h14723, - result__h14751, - result__h14792, - result__h14820, - result__h14859, - result__h14887, - result__h29603, - result__h29633, - result__h29660, - result__h29687, - result__h29714, - result__h29741, - result__h29768, - result__h29795, - result__h29839, - result__h29866, - result__h29893, - result__h29920, - result__h29947, - result__h29974, - result__h30001, - result__h30028, - result__h30072, - result__h30099, - result__h30126, - result__h30153, - result__h30193, - result__h30220, - result__h30247, - result__h30274, - result__h30314, - result__h30341, - result__h30379, - result__h30406, - result__h32856, - result__h33764, - result__h33792, - result__h33820, - result__h33848, - result__h33876, - result__h33904, - result__h33932, - result__h33977, - result__h34005, - result__h34033, - result__h34061, - result__h34089, - result__h34117, - result__h34145, - result__h34173, - result__h34218, - result__h34246, - result__h34274, - result__h34302, - result__h34343, - result__h34371, - result__h34399, - result__h34427, - result__h34468, - result__h34496, - result__h34535, - result__h34563, - result__h7732, - satp_pa__h2470, - st_val__h32393, - value__h6977, - vpn_0_pa__h25313, - vpn_1_pa__h24256, - vpn_2_pa__h23314, - w1___1__h19782, - w1___1__h32736, - w2___1__h32737, - w2__h32667, - word64__h7498, - x1_avValue_pa__h6190, - x__h15358, - y__h7768; - wire [55 : 0] x__h24360, x__h5382, x__h6663, x__h6712, x__h6781; - wire [31 : 0] ld_val9543_BITS_31_TO_0__q38, - ld_val9543_BITS_63_TO_32__q45, - master_xactor_rg_rd_data_BITS_34_TO_3__q3, - master_xactor_rg_rd_data_BITS_66_TO_35__q10, - new_value679_BITS_31_TO_0__q31, - rg_st_amo_val_BITS_31_TO_0__q32, - w12661_BITS_31_TO_0__q51, - word64498_BITS_31_TO_0__q17, - word64498_BITS_63_TO_32__q24; - wire [15 : 0] ld_val9543_BITS_15_TO_0__q37, - ld_val9543_BITS_31_TO_16__q41, - ld_val9543_BITS_47_TO_32__q44, - ld_val9543_BITS_63_TO_48__q48, - master_xactor_rg_rd_data_BITS_18_TO_3__q2, - master_xactor_rg_rd_data_BITS_34_TO_19__q6, - master_xactor_rg_rd_data_BITS_50_TO_35__q9, - master_xactor_rg_rd_data_BITS_66_TO_51__q13, - word64498_BITS_15_TO_0__q16, - word64498_BITS_31_TO_16__q20, - word64498_BITS_47_TO_32__q23, - word64498_BITS_63_TO_48__q27; - wire [7 : 0] ld_val9543_BITS_15_TO_8__q39, - ld_val9543_BITS_23_TO_16__q40, - ld_val9543_BITS_31_TO_24__q42, - ld_val9543_BITS_39_TO_32__q43, - ld_val9543_BITS_47_TO_40__q46, - ld_val9543_BITS_55_TO_48__q47, - ld_val9543_BITS_63_TO_56__q49, - ld_val9543_BITS_7_TO_0__q36, - master_xactor_rg_rd_data_BITS_10_TO_3__q1, - master_xactor_rg_rd_data_BITS_18_TO_11__q4, - master_xactor_rg_rd_data_BITS_26_TO_19__q5, - master_xactor_rg_rd_data_BITS_34_TO_27__q7, - master_xactor_rg_rd_data_BITS_42_TO_35__q8, - master_xactor_rg_rd_data_BITS_50_TO_43__q11, - master_xactor_rg_rd_data_BITS_58_TO_51__q12, - master_xactor_rg_rd_data_BITS_66_TO_59__q14, - strobe64__h18920, - strobe64__h18922, - strobe64__h18924, - strobe64__h32582, - strobe64__h32584, - strobe64__h32586, - word64498_BITS_15_TO_8__q18, - word64498_BITS_23_TO_16__q19, - word64498_BITS_31_TO_24__q21, - word64498_BITS_39_TO_32__q22, - word64498_BITS_47_TO_40__q25, - word64498_BITS_55_TO_48__q26, - word64498_BITS_63_TO_56__q28, - word64498_BITS_7_TO_0__q15; - wire [5 : 0] shift_bits__h18787, shift_bits__h32449; - wire [4 : 0] IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d399, - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d398, - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d401; - wire [3 : 0] access_exc_code__h3151, - b__h23216, - exc_code___1__h6552, - x1_avValue_exc_code__h6191; - wire IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293, - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217, - IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d305, - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d304, - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435, - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284, - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289, - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d292, - NOT_cfg_verbosity_read__8_ULE_2_060___d1061, - NOT_cfg_verbosity_read__8_ULT_2_05___d406, - NOT_dmem_not_imem_01_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d341, - NOT_dmem_not_imem_01_OR_NOT_rg_op_6_EQ_0_7_8_A_ETC___d108, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d624, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d637, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d764, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d798, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d816, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d855, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d860, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d866, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d874, - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d878, - NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d921, - NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d984, - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928, - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990, - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199, - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d437, - NOT_req_f3_BITS_1_TO_0_389_EQ_0b0_390_391_AND__ETC___d1410, - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294, - NOT_rg_op_6_EQ_0_7_8_AND_NOT_rg_op_6_EQ_2_9_0__ETC___d392, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d446, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d761, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d853, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d858, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d864, - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d872, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d632, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d759, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d819, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d825, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d831, - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d837, - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348, - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371, - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d409, - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d583, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d142, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d307, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d353, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d368, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d421, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d428, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d431, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d458, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d597, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d604, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d610, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d616, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d639, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d766, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d771, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d800, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d806, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d812, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d818, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d823, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d829, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d835, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d841, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d849, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d857, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d876, - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d880, - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123, - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139, - cfg_verbosity_read__8_ULE_1___d19, - dmem_not_imem_AND_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_ETC___d343, - dmem_not_imem_OR_NOT_rg_op_6_EQ_0_7_8_AND_NOT__ETC___d100, - lrsc_result__h15348, - master_xactor_crg_rd_data_full_port1__read__96_ETC___d1222, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971, - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975, - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178, - ram_state_and_ctag_cset_b_read__73_BIT_52_74_A_ETC___d438, - req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419, - rg_amo_funct7_1_BITS_6_TO_2_2_EQ_0b10_3_AND_NO_ETC___d613, - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d387, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d424, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d449, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d588, - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d607, - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d447, - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d635, - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d762, - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d767, - rg_op_6_EQ_2_9_AND_rg_amo_funct7_1_BITS_6_TO_2_ETC___d248, - rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117, - rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d309, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d356, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d395, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414, - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417, - rg_priv_9_ULE_0b1___d60, - rg_state_3_EQ_13_088_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d1090, - rg_state_3_EQ_3_12_AND_NOT_rg_op_6_EQ_0_7_8_AN_ETC___d316, - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106, - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350, - y__h6478; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method addr - assign addr = rg_addr ; - - // value method word64 - always@(MUX_dw_output_ld_val$wset_1__SEL_1 or - ld_val__h29543 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h32381 or - MUX_dw_output_st_amo_val$wset_1__SEL_1 or - MUX_dw_output_ld_val$wset_1__VAL_3 or - MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h29543; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - word64 = new_ld_val__h32381; - MUX_dw_output_st_amo_val$wset_1__SEL_1: - word64 = MUX_dw_output_ld_val$wset_1__VAL_3; - MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val; - default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // value method st_amo_val - assign st_amo_val = - MUX_dw_output_st_amo_val$wset_1__SEL_1 ? 64'd0 : rg_st_amo_val ; - - // value method exc - assign exc = rg_state == 5'd4 ; - - // value method exc_code - assign exc_code = rg_exc_code ; - - // action method server_flush_request_put - assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; - - // action method server_flush_response_get - assign RDY_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; - - // action method tlb_flush - assign RDY_tlb_flush = 1'd1 ; - assign CAN_FIRE_tlb_flush = 1'd1 ; - assign WILL_FIRE_tlb_flush = EN_tlb_flush ; - - // value method mem_master_m_awvalid - assign mem_master_awvalid = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - - // value method mem_master_m_awid - assign mem_master_awid = master_xactor_rg_wr_addr[96:93] ; - - // value method mem_master_m_awaddr - assign mem_master_awaddr = master_xactor_rg_wr_addr[92:29] ; - - // value method mem_master_m_awlen - assign mem_master_awlen = master_xactor_rg_wr_addr[28:21] ; - - // value method mem_master_m_awsize - assign mem_master_awsize = master_xactor_rg_wr_addr[20:18] ; - - // value method mem_master_m_awburst - assign mem_master_awburst = master_xactor_rg_wr_addr[17:16] ; - - // value method mem_master_m_awlock - assign mem_master_awlock = master_xactor_rg_wr_addr[15] ; - - // value method mem_master_m_awcache - assign mem_master_awcache = master_xactor_rg_wr_addr[14:11] ; - - // value method mem_master_m_awprot - assign mem_master_awprot = master_xactor_rg_wr_addr[10:8] ; - - // value method mem_master_m_awqos - assign mem_master_awqos = master_xactor_rg_wr_addr[7:4] ; - - // value method mem_master_m_awregion - assign mem_master_awregion = master_xactor_rg_wr_addr[3:0] ; - - // action method mem_master_m_awready - assign CAN_FIRE_mem_master_m_awready = 1'd1 ; - assign WILL_FIRE_mem_master_m_awready = 1'd1 ; - - // value method mem_master_m_wvalid - assign mem_master_wvalid = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - - // value method mem_master_m_wid - assign mem_master_wid = master_xactor_rg_wr_data[76:73] ; - - // value method mem_master_m_wdata - assign mem_master_wdata = master_xactor_rg_wr_data[72:9] ; - - // value method mem_master_m_wstrb - assign mem_master_wstrb = master_xactor_rg_wr_data[8:1] ; - - // value method mem_master_m_wlast - assign mem_master_wlast = master_xactor_rg_wr_data[0] ; - - // action method mem_master_m_wready - assign CAN_FIRE_mem_master_m_wready = 1'd1 ; - assign WILL_FIRE_mem_master_m_wready = 1'd1 ; - - // action method mem_master_m_bvalid - assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ; - - // value method mem_master_m_bready - assign mem_master_bready = !master_xactor_crg_wr_resp_full$port2__read ; - - // value method mem_master_m_arvalid - assign mem_master_arvalid = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - - // value method mem_master_m_arid - assign mem_master_arid = master_xactor_rg_rd_addr[96:93] ; - - // value method mem_master_m_araddr - assign mem_master_araddr = master_xactor_rg_rd_addr[92:29] ; - - // value method mem_master_m_arlen - assign mem_master_arlen = master_xactor_rg_rd_addr[28:21] ; - - // value method mem_master_m_arsize - assign mem_master_arsize = master_xactor_rg_rd_addr[20:18] ; - - // value method mem_master_m_arburst - assign mem_master_arburst = master_xactor_rg_rd_addr[17:16] ; - - // value method mem_master_m_arlock - assign mem_master_arlock = master_xactor_rg_rd_addr[15] ; - - // value method mem_master_m_arcache - assign mem_master_arcache = master_xactor_rg_rd_addr[14:11] ; - - // value method mem_master_m_arprot - assign mem_master_arprot = master_xactor_rg_rd_addr[10:8] ; - - // value method mem_master_m_arqos - assign mem_master_arqos = master_xactor_rg_rd_addr[7:4] ; - - // value method mem_master_m_arregion - assign mem_master_arregion = master_xactor_rg_rd_addr[3:0] ; - - // action method mem_master_m_arready - assign CAN_FIRE_mem_master_m_arready = 1'd1 ; - assign WILL_FIRE_mem_master_m_arready = 1'd1 ; - - // action method mem_master_m_rvalid - assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ; - - // value method mem_master_m_rready - assign mem_master_rready = !master_xactor_crg_rd_data_full$port2__read ; - - // submodule f_pte_writebacks - FIFO2 #(.width(32'd128), .guarded(32'd1)) f_pte_writebacks(.RST(RST_N), - .CLK(CLK), - .D_IN(f_pte_writebacks$D_IN), - .ENQ(f_pte_writebacks$ENQ), - .DEQ(f_pte_writebacks$DEQ), - .CLR(f_pte_writebacks$CLR), - .D_OUT(f_pte_writebacks$D_OUT), - .FULL_N(f_pte_writebacks$FULL_N), - .EMPTY_N(f_pte_writebacks$EMPTY_N)); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule ram_state_and_ctag_cset - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd6), - .DATA_WIDTH(32'd53), - .MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_state_and_ctag_cset$ADDRA), - .ADDRB(ram_state_and_ctag_cset$ADDRB), - .DIA(ram_state_and_ctag_cset$DIA), - .DIB(ram_state_and_ctag_cset$DIB), - .WEA(ram_state_and_ctag_cset$WEA), - .WEB(ram_state_and_ctag_cset$WEB), - .ENA(ram_state_and_ctag_cset$ENA), - .ENB(ram_state_and_ctag_cset$ENB), - .DOA(), - .DOB(ram_state_and_ctag_cset$DOB)); - - // submodule ram_word64_set - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd9), - .DATA_WIDTH(32'd64), - .MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_word64_set$ADDRA), - .ADDRB(ram_word64_set$ADDRB), - .DIA(ram_word64_set$DIA), - .DIB(ram_word64_set$DIB), - .WEA(ram_word64_set$WEA), - .WEB(ram_word64_set$WEB), - .ENA(ram_word64_set$ENA), - .ENB(ram_word64_set$ENB), - .DOA(), - .DOB(ram_word64_set$DOB)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(soc_map$m_is_mem_addr), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule tlb - mkTLB #(.dmem_not_imem(dmem_not_imem)) tlb(.CLK(CLK), - .RST_N(RST_N), - .insert_asid(tlb$insert_asid), - .insert_level(tlb$insert_level), - .insert_pte(tlb$insert_pte), - .insert_pte_pa(tlb$insert_pte_pa), - .insert_vpn(tlb$insert_vpn), - .lookup_asid(tlb$lookup_asid), - .lookup_vpn(tlb$lookup_vpn), - .EN_flush(tlb$EN_flush), - .EN_insert(tlb$EN_insert), - .RDY_flush(), - .lookup(tlb$lookup), - .RDY_lookup(tlb$RDY_lookup), - .RDY_insert(tlb$RDY_insert)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - (rg_cset_in_cache != 6'd63 || - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) && - rg_state == 5'd1 ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // rule RL_rl_shift_sb_to_load_delay - assign CAN_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - assign WILL_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - - // rule RL_rl_rereq - assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ; - assign WILL_FIRE_RL_rl_rereq = - CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ; - - // rule RL_rl_ST_AMO_response - assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ; - assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ; - - // rule RL_rl_maintain_io_read_rsp - assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ; - assign WILL_FIRE_RL_rl_maintain_io_read_rsp = - CAN_FIRE_RL_rl_maintain_io_read_rsp ; - - // rule RL_rl_io_AMO_SC_req - assign CAN_FIRE_RL_rl_io_AMO_SC_req = - rg_state == 5'd13 && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_SC_req = - CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_drive_exception_rsp - assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ; - assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ; - - // rule RL_rl_start_reset - assign CAN_FIRE_RL_rl_start_reset = - f_reset_reqs$EMPTY_N && rg_state != 5'd1 ; - assign WILL_FIRE_RL_rl_start_reset = CAN_FIRE_RL_rl_start_reset ; - - // rule RL_rl_probe_and_immed_rsp - assign CAN_FIRE_RL_rl_probe_and_immed_rsp = - (cfg_verbosity_read__8_ULE_1___d19 || tlb$RDY_lookup) && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$RDY_lookup) && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d309 && - rg_state_3_EQ_3_12_AND_NOT_rg_op_6_EQ_0_7_8_AN_ETC___d316 ; - assign WILL_FIRE_RL_rl_probe_and_immed_rsp = - CAN_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_ptw_level_2 - assign CAN_FIRE_RL_rl_ptw_level_2 = - master_xactor_crg_rd_data_full$port1__read && - NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d921 && - rg_state == 5'd6 ; - assign WILL_FIRE_RL_rl_ptw_level_2 = - CAN_FIRE_RL_rl_ptw_level_2 && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_ptw_level_1 - assign CAN_FIRE_RL_rl_ptw_level_1 = - master_xactor_crg_rd_data_full$port1__read && - NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d984 && - rg_state == 5'd7 ; - assign WILL_FIRE_RL_rl_ptw_level_1 = - CAN_FIRE_RL_rl_ptw_level_1 && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_ptw_level_0 - assign CAN_FIRE_RL_rl_ptw_level_0 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - !master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4] || - tlb$RDY_insert) && - rg_state == 5'd8 ; - assign WILL_FIRE_RL_rl_ptw_level_0 = - CAN_FIRE_RL_rl_ptw_level_0 && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_cache_refill_rsps_loop - assign CAN_FIRE_RL_rl_cache_refill_rsps_loop = - master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd10 ; - assign WILL_FIRE_RL_rl_cache_refill_rsps_loop = - CAN_FIRE_RL_rl_cache_refill_rsps_loop && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_rsp - assign CAN_FIRE_RL_rl_io_read_rsp = - master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd14 ; - assign WILL_FIRE_RL_rl_io_read_rsp = - CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_write_req - assign CAN_FIRE_RL_rl_io_write_req = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - rg_state == 5'd13 && - rg_op == 2'd1 ; - assign WILL_FIRE_RL_rl_io_write_req = - CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_op_req - assign CAN_FIRE_RL_rl_io_AMO_op_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 5'd13 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] != 5'b00010 && - rg_amo_funct7[6:2] != 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_op_req = - CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_writeback_updated_PTE - assign CAN_FIRE_RL_rl_writeback_updated_PTE = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - f_pte_writebacks$EMPTY_N ; - assign WILL_FIRE_RL_rl_writeback_updated_PTE = - CAN_FIRE_RL_rl_writeback_updated_PTE && - !WILL_FIRE_RL_rl_io_AMO_read_rsp && - !WILL_FIRE_RL_rl_io_write_req && - !WILL_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_read_rsp - assign CAN_FIRE_RL_rl_io_AMO_read_rsp = - master_xactor_crg_rd_data_full_port1__read__96_ETC___d1222 && - rg_state == 5'd16 ; - assign WILL_FIRE_RL_rl_io_AMO_read_rsp = - CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_tlb_refill - assign CAN_FIRE_RL_rl_start_tlb_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 5'd5 && - b__h23216 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_tlb_refill = - CAN_FIRE_RL_rl_start_tlb_refill && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_cache_refill - assign CAN_FIRE_RL_rl_start_cache_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 5'd9 && - b__h23216 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_cache_refill = - CAN_FIRE_RL_rl_start_cache_refill && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_req - assign CAN_FIRE_RL_rl_io_read_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state_3_EQ_13_088_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d1090 ; - assign WILL_FIRE_RL_rl_io_read_req = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_discard_write_rsp - assign CAN_FIRE_RL_rl_discard_write_rsp = - b__h23216 != 4'd0 && master_xactor_crg_wr_resp_full$port1__read ; - assign WILL_FIRE_RL_rl_discard_write_rsp = - CAN_FIRE_RL_rl_discard_write_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // inputs to muxes for submodule ports - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3 = - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign MUX_dw_output_ld_val$wset_1__SEL_1 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_dw_output_ld_val$wset_1__SEL_4 = - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign MUX_dw_output_st_amo_val$wset_1__SEL_1 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459 ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_1 = - WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_2 = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_3 = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ; - assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 = - EN_req && - req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419 ; - assign MUX_ram_word64_set$a_put_3__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ram_word64_set$b_put_1__SEL_2 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 ; - assign MUX_rg_error_during_refill$write_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_1 = - EN_req && - NOT_req_f3_BITS_1_TO_0_389_EQ_0b0_390_391_AND__ETC___d1410 ; - assign MUX_rg_exc_code$write_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_3 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_5 = - WILL_FIRE_RL_rl_ptw_level_0 && - (!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - !master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4] || - master_xactor_rg_rd_data[2:1] != 2'b0) ; - assign MUX_rg_exc_code$write_1__SEL_6 = - WILL_FIRE_RL_rl_ptw_level_1 && - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990 ; - assign MUX_rg_exc_code$write_1__SEL_7 = - WILL_FIRE_RL_rl_ptw_level_2 && - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928 ; - assign MUX_rg_exc_code$write_1__SEL_8 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ; - assign MUX_rg_ld_val$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626 ; - assign MUX_rg_lrsc_valid$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452 ; - assign MUX_rg_state$write_1__SEL_3 = - CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ; - assign MUX_rg_state$write_1__SEL_10 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 ; - assign MUX_rg_state$write_1__SEL_14 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396 ; - assign MUX_rg_state$write_1__SEL_18 = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign MUX_tlb$insert_1__SEL_1 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 ; - assign MUX_tlb$insert_1__SEL_2 = - WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971 ; - assign MUX_tlb$insert_1__SEL_3 = - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006 ; - assign MUX_tlb$insert_1__SEL_4 = - WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 = - ctr_wr_rsps_pending_crg + 4'd1 ; - assign MUX_dw_output_ld_val$wset_1__VAL_3 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - new_value__h7679 : - new_value__h17706 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, lev_1_pte_pa_w64_fa__h24259, 29'd851968 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, lev_0_pte_pa_w64_fa__h25316, 29'd851968 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_3 = - { 4'd0, rg_pa, 8'd0, value__h31966, 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_4 = - { 4'd0, lev_2_pte_pa_w64_fa__h23317, 29'd851968 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_5 = - { 4'd0, cline_fabric_addr__h26510, 29'd15532032 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_1 = - { 4'd0, rg_pa, 8'd0, value__h34992, 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_2 = - { 4'd0, x1_avValue_pa__h6190, 8'd0, value__h34992, 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_4 = - { 4'd0, f_pte_writebacks$D_OUT[127:64], 29'd851968 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_1 = - { 4'd0, - mem_req_wr_data_wdata__h32648, - mem_req_wr_data_wstrb__h32649, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_2 = - { 4'd0, - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d787, - mem_req_wr_data_wstrb__h18987, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_3 = - { 4'd0, f_pte_writebacks$D_OUT[63:0], 9'd511 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_4 = - { 4'd0, - mem_req_wr_data_wdata__h31144, - mem_req_wr_data_wstrb__h32649, - 1'd1 } ; - assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 = { 1'd1, rg_pa[63:12] } ; - assign MUX_ram_word64_set$a_put_3__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 : - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 ; - assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ; - assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ; - assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ; - assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ; - assign MUX_rg_exc_code$write_1__VAL_6 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - exc_code___1__h6552 : - access_exc_code__h3151 ; - assign MUX_rg_ld_val$write_1__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - x__h15358 : - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 ; - assign MUX_rg_state$write_1__VAL_2 = - NOT_req_f3_BITS_1_TO_0_389_EQ_0b0_390_391_AND__ETC___d1410 ? - 5'd4 : - 5'd3 ; - assign MUX_rg_state$write_1__VAL_6 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? 5'd15 : 5'd4 ; - assign MUX_rg_state$write_1__VAL_10 = - (master_xactor_rg_rd_data[2:1] != 2'b0 || - rg_error_during_refill) ? - 5'd4 : - 5'd11 ; - assign MUX_rg_state$write_1__VAL_11 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - ((!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && - master_xactor_rg_rd_data[5] || - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4]) ? - 5'd4 : - 5'd11) : - 5'd4 ; - assign MUX_rg_state$write_1__VAL_12 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - ((!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && - master_xactor_rg_rd_data[5]) ? - 5'd4 : - ((!master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4]) ? - 5'd8 : - ((master_xactor_rg_rd_data[21:13] == 9'd0) ? - 5'd11 : - 5'd4))) : - 5'd4 ; - assign MUX_rg_state$write_1__VAL_13 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? - ((!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && - master_xactor_rg_rd_data[5]) ? - 5'd4 : - ((!master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4]) ? - 5'd7 : - ((master_xactor_rg_rd_data[30:22] != 9'd0 || - master_xactor_rg_rd_data[21:13] != 9'd0) ? - 5'd4 : - 5'd11))) : - 5'd4 ; - assign MUX_rg_state$write_1__VAL_14 = - (rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - !tlb$lookup[130]) ? - 5'd5 : - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d401 ; - - // inlined wires - assign dw_valid$whas = - (WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_read_rsp) && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459 || - WILL_FIRE_RL_rl_drive_exception_rsp || - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign master_xactor_crg_wr_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_addr_full$port1__read = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full$port1__read && - mem_master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full$port1__read ; - assign master_xactor_crg_wr_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign master_xactor_crg_wr_addr_full$port3__read = - master_xactor_crg_wr_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_data_full$port1__read = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full$port1__read && mem_master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full$port1__read ; - assign master_xactor_crg_wr_data_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign master_xactor_crg_wr_data_full$port3__read = - master_xactor_crg_wr_data_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_wr_resp_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_resp_full$port1__read = - !master_xactor_crg_wr_resp_full$EN_port0__write && - master_xactor_crg_wr_resp_full ; - assign master_xactor_crg_wr_resp_full$port2__read = - !WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_crg_wr_resp_full$port1__read ; - assign master_xactor_crg_wr_resp_full$EN_port2__write = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_wr_resp_full$port3__read = - master_xactor_crg_wr_resp_full$EN_port2__write || - master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_addr_full$port1__read = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full$port1__read && - mem_master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full$port1__read ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - (WILL_FIRE_RL_rl_ptw_level_1 || WILL_FIRE_RL_rl_ptw_level_2) && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] || - WILL_FIRE_RL_rl_io_AMO_op_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_tlb_refill ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_data_full$port1__read = - !master_xactor_crg_rd_data_full$EN_port0__write && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port1__write = - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_cache_refill_rsps_loop || - WILL_FIRE_RL_rl_ptw_level_0 || - WILL_FIRE_RL_rl_ptw_level_1 || - WILL_FIRE_RL_rl_ptw_level_2 || - WILL_FIRE_RL_rl_io_AMO_read_rsp ; - assign master_xactor_crg_rd_data_full$port2__read = - !master_xactor_crg_rd_data_full$EN_port1__write && - master_xactor_crg_rd_data_full$port1__read ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - mem_master_rvalid && - !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - assign ctr_wr_rsps_pending_crg$EN_port0__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_3: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - default: ctr_wr_rsps_pending_crg$port0__write_1 = - 4'b1010 /* unspecified value */ ; - endcase - end - assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h23216 - 4'd1 ; - assign ctr_wr_rsps_pending_crg$port2__read = - WILL_FIRE_RL_rl_discard_write_rsp ? - ctr_wr_rsps_pending_crg$port1__write_1 : - b__h23216 ; - assign ctr_wr_rsps_pending_crg$EN_port2__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign ctr_wr_rsps_pending_crg$port3__read = - ctr_wr_rsps_pending_crg$EN_port2__write ? - 4'd0 : - ctr_wr_rsps_pending_crg$port2__read ; - assign crg_sb_to_load_delay$port0__write_1 = - { 1'd0, crg_sb_to_load_delay[10:1] } ; - assign crg_sb_to_load_delay$EN_port1__write = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d766 ; - assign crg_sb_to_load_delay$port2__read = - crg_sb_to_load_delay$EN_port1__write ? - 11'd2047 : - crg_sb_to_load_delay$port0__write_1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register crg_sb_to_load_delay - assign crg_sb_to_load_delay$D_IN = crg_sb_to_load_delay$port2__read ; - assign crg_sb_to_load_delay$EN = 1'b1 ; - - // register ctr_wr_rsps_pending_crg - assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ; - assign ctr_wr_rsps_pending_crg$EN = 1'b1 ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = - master_xactor_crg_wr_resp_full$port3__read ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - always@(MUX_master_xactor_rg_rd_addr$write_1__SEL_1 or - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 or - MUX_master_xactor_rg_rd_addr$write_1__SEL_2 or - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 or - MUX_master_xactor_rg_rd_addr$write_1__SEL_3 or - MUX_master_xactor_rg_rd_addr$write_1__VAL_3 or - WILL_FIRE_RL_rl_start_tlb_refill or - MUX_master_xactor_rg_rd_addr$write_1__VAL_4 or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_master_xactor_rg_rd_addr$write_1__VAL_5) - begin - case (1'b1) // synopsys parallel_case - MUX_master_xactor_rg_rd_addr$write_1__SEL_1: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_1; - MUX_master_xactor_rg_rd_addr$write_1__SEL_2: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_2; - MUX_master_xactor_rg_rd_addr$write_1__SEL_3: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_3; - WILL_FIRE_RL_rl_start_tlb_refill: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_4; - WILL_FIRE_RL_rl_start_cache_refill: - master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__VAL_5; - default: master_xactor_rg_rd_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_rd_addr$EN = - WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] || - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] || - WILL_FIRE_RL_rl_io_AMO_op_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_tlb_refill || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_writeback_updated_PTE or - MUX_master_xactor_rg_wr_addr$write_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - WILL_FIRE_RL_rl_writeback_updated_PTE: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_4; - default: master_xactor_rg_wr_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_addr$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_writeback_updated_PTE ; - - // register master_xactor_rg_wr_data - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_data$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_data$write_1__VAL_2 or - WILL_FIRE_RL_rl_writeback_updated_PTE or - MUX_master_xactor_rg_wr_data$write_1__VAL_3 or - WILL_FIRE_RL_rl_io_write_req or - MUX_master_xactor_rg_wr_data$write_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_2; - WILL_FIRE_RL_rl_writeback_updated_PTE: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_4; - default: master_xactor_rg_wr_data$D_IN = - 77'h0AAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_data$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 || - WILL_FIRE_RL_rl_writeback_updated_PTE || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = - { mem_master_bid, mem_master_bresp } ; - assign master_xactor_rg_wr_resp$EN = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - - // register rg_addr - assign rg_addr$D_IN = req_addr ; - assign rg_addr$EN = EN_req ; - - // register rg_amo_funct7 - assign rg_amo_funct7$D_IN = req_amo_funct7 ; - assign rg_amo_funct7$EN = EN_req ; - - // register rg_cset_in_cache - assign rg_cset_in_cache$D_IN = - WILL_FIRE_RL_rl_reset ? - MUX_rg_cset_in_cache$write_1__VAL_1 : - 6'd0 ; - assign rg_cset_in_cache$EN = - WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ; - - // register rg_error_during_refill - assign rg_error_during_refill$D_IN = - MUX_rg_error_during_refill$write_1__SEL_1 ; - assign rg_error_during_refill$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register rg_exc_code - always@(MUX_rg_exc_code$write_1__SEL_1 or - MUX_rg_exc_code$write_1__VAL_1 or - MUX_rg_exc_code$write_1__SEL_2 or - MUX_rg_exc_code$write_1__SEL_3 or - MUX_rg_error_during_refill$write_1__SEL_1 or - access_exc_code__h3151 or - MUX_rg_exc_code$write_1__SEL_5 or - MUX_rg_exc_code$write_1__VAL_6 or - MUX_rg_exc_code$write_1__SEL_6 or - MUX_rg_exc_code$write_1__SEL_7 or - MUX_rg_exc_code$write_1__SEL_8 or x1_avValue_exc_code__h6191) - case (1'b1) - MUX_rg_exc_code$write_1__SEL_1: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1; - MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7; - MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5; - MUX_rg_error_during_refill$write_1__SEL_1: - rg_exc_code$D_IN = access_exc_code__h3151; - MUX_rg_exc_code$write_1__SEL_5: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_6; - MUX_rg_exc_code$write_1__SEL_6: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_6; - MUX_rg_exc_code$write_1__SEL_7: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_6; - MUX_rg_exc_code$write_1__SEL_8: - rg_exc_code$D_IN = x1_avValue_exc_code__h6191; - default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_exc_code$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - EN_req && - NOT_req_f3_BITS_1_TO_0_389_EQ_0b0_390_391_AND__ETC___d1410 || - WILL_FIRE_RL_rl_ptw_level_2 && - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928 || - WILL_FIRE_RL_rl_ptw_level_1 && - NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990 || - WILL_FIRE_RL_rl_ptw_level_0 && - (!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - !master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4] || - master_xactor_rg_rd_data[2:1] != 2'b0) ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_ld_val - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h32381 or - MUX_rg_ld_val$write_1__SEL_2 or - MUX_rg_ld_val$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_rsp or - ld_val__h29543 or WILL_FIRE_RL_rl_io_AMO_SC_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - rg_ld_val$D_IN = new_ld_val__h32381; - MUX_rg_ld_val$write_1__SEL_2: - rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h29543; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1; - default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_ld_val$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_SC_req ; - - // register rg_lower_word32 - assign rg_lower_word32$D_IN = 32'h0 ; - assign rg_lower_word32$EN = 1'b0 ; - - // register rg_lower_word32_full - assign rg_lower_word32_full$D_IN = 1'd0 ; - assign rg_lower_word32_full$EN = - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_lrsc_pa - assign rg_lrsc_pa$D_IN = soc_map$m_is_mem_addr_addr ; - assign rg_lrsc_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d597 ; - - // register rg_lrsc_valid - assign rg_lrsc_valid$D_IN = - MUX_rg_lrsc_valid$write_1__SEL_2 && - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453 ; - assign rg_lrsc_valid$EN = - WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452 || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = req_mstatus_MXR ; - assign rg_mstatus_MXR$EN = EN_req ; - - // register rg_op - assign rg_op$D_IN = req_op ; - assign rg_op$EN = EN_req ; - - // register rg_pa - assign rg_pa$D_IN = EN_req ? req_addr : soc_map$m_is_mem_addr_addr ; - assign rg_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d421 || - EN_req ; - - // register rg_priv - assign rg_priv$D_IN = req_priv ; - assign rg_priv$EN = EN_req ; - - // register rg_pte_pa - always@(MUX_master_xactor_rg_rd_addr$write_1__SEL_1 or - lev_1_pte_pa__h24257 or - MUX_master_xactor_rg_rd_addr$write_1__SEL_2 or - lev_0_pte_pa__h25314 or - WILL_FIRE_RL_rl_start_tlb_refill or lev_2_pte_pa__h23315) - begin - case (1'b1) // synopsys parallel_case - MUX_master_xactor_rg_rd_addr$write_1__SEL_1: - rg_pte_pa$D_IN = lev_1_pte_pa__h24257; - MUX_master_xactor_rg_rd_addr$write_1__SEL_2: - rg_pte_pa$D_IN = lev_0_pte_pa__h25314; - WILL_FIRE_RL_rl_start_tlb_refill: rg_pte_pa$D_IN = lev_2_pte_pa__h23315; - default: rg_pte_pa$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_pte_pa$EN = - WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] || - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] || - WILL_FIRE_RL_rl_start_tlb_refill ; - - // register rg_satp - assign rg_satp$D_IN = req_satp ; - assign rg_satp$EN = EN_req ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = req_sstatus_SUM ; - assign rg_sstatus_SUM$EN = EN_req ; - - // register rg_st_amo_val - assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h19441 ; - assign rg_st_amo_val$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d880 || - EN_req ; - - // register rg_state - always@(EN_tlb_flush or - EN_req or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_req or - WILL_FIRE_RL_rl_start_cache_refill or - WILL_FIRE_RL_rl_start_tlb_refill or - WILL_FIRE_RL_rl_io_AMO_read_rsp or - MUX_rg_state$write_1__VAL_6 or - WILL_FIRE_RL_rl_io_AMO_op_req or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_io_read_rsp or - MUX_rg_state$write_1__SEL_10 or - MUX_rg_state$write_1__VAL_10 or - WILL_FIRE_RL_rl_ptw_level_0 or - MUX_rg_state$write_1__VAL_11 or - WILL_FIRE_RL_rl_ptw_level_1 or - MUX_rg_state$write_1__VAL_12 or - WILL_FIRE_RL_rl_ptw_level_2 or - MUX_rg_state$write_1__VAL_13 or - MUX_rg_state$write_1__SEL_14 or - MUX_rg_state$write_1__VAL_14 or - WILL_FIRE_RL_rl_start_reset or - WILL_FIRE_RL_rl_io_AMO_SC_req or - WILL_FIRE_RL_rl_rereq or MUX_rg_state$write_1__SEL_18) - case (1'b1) - EN_tlb_flush: rg_state$D_IN = 5'd2; - EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14; - WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10; - WILL_FIRE_RL_rl_start_tlb_refill: rg_state$D_IN = 5'd6; - WILL_FIRE_RL_rl_io_AMO_read_rsp: - rg_state$D_IN = MUX_rg_state$write_1__VAL_6; - WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16; - WILL_FIRE_RL_rl_io_write_req: rg_state$D_IN = 5'd12; - WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_6; - MUX_rg_state$write_1__SEL_10: - rg_state$D_IN = MUX_rg_state$write_1__VAL_10; - WILL_FIRE_RL_rl_ptw_level_0: rg_state$D_IN = MUX_rg_state$write_1__VAL_11; - WILL_FIRE_RL_rl_ptw_level_1: rg_state$D_IN = MUX_rg_state$write_1__VAL_12; - WILL_FIRE_RL_rl_ptw_level_2: rg_state$D_IN = MUX_rg_state$write_1__VAL_13; - MUX_rg_state$write_1__SEL_14: - rg_state$D_IN = MUX_rg_state$write_1__VAL_14; - WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_state$D_IN = 5'd12; - WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3; - MUX_rg_state$write_1__SEL_18: rg_state$D_IN = 5'd2; - default: rg_state$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_state$EN = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_ptw_level_2 || - WILL_FIRE_RL_rl_ptw_level_1 || - WILL_FIRE_RL_rl_ptw_level_0 || - EN_req || - WILL_FIRE_RL_rl_start_reset || - EN_tlb_flush || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_tlb_refill || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_io_AMO_SC_req || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_io_AMO_op_req ; - - // register rg_word64_set_in_cache - assign rg_word64_set_in_cache$D_IN = - MUX_ram_word64_set$b_put_1__SEL_2 ? - MUX_ram_word64_set$b_put_2__VAL_2 : - MUX_ram_word64_set$b_put_2__VAL_4 ; - assign rg_word64_set_in_cache$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule f_pte_writebacks - assign f_pte_writebacks$D_IN = { tlb$lookup[63:0], value__h6977 } ; - assign f_pte_writebacks$ENQ = MUX_tlb$insert_1__SEL_1 ; - assign f_pte_writebacks$DEQ = WILL_FIRE_RL_rl_writeback_updated_PTE ; - assign f_pte_writebacks$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = !EN_server_reset_request_put ; - assign f_reset_reqs$ENQ = - EN_server_reset_request_put || EN_server_flush_request_put ; - assign f_reset_reqs$DEQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ; - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign f_reset_rsps$DEQ = - EN_server_flush_response_get || EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule ram_state_and_ctag_cset - assign ram_state_and_ctag_cset$ADDRA = - WILL_FIRE_RL_rl_start_cache_refill ? - rg_addr[11:6] : - rg_cset_in_cache ; - assign ram_state_and_ctag_cset$ADDRB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - req_addr[11:6] : - rg_addr[11:6] ; - assign ram_state_and_ctag_cset$DIA = - WILL_FIRE_RL_rl_start_cache_refill ? - MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 : - 53'h0AAAAAAAAAAAAA ; - assign ram_state_and_ctag_cset$DIB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - 53'h0AAAAAAAAAAAAA /* unspecified value */ : - 53'h0AAAAAAAAAAAAA /* unspecified value */ ; - assign ram_state_and_ctag_cset$WEA = 1'd1 ; - assign ram_state_and_ctag_cset$WEB = 1'd0 ; - assign ram_state_and_ctag_cset$ENA = - WILL_FIRE_RL_rl_start_cache_refill || WILL_FIRE_RL_rl_reset ; - assign ram_state_and_ctag_cset$ENB = - EN_req && - req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419 || - WILL_FIRE_RL_rl_rereq ; - - // submodule ram_word64_set - assign ram_word64_set$ADDRA = - MUX_ram_word64_set$a_put_3__SEL_1 ? - rg_word64_set_in_cache : - rg_addr[11:3] ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - req_addr or - MUX_ram_word64_set$b_put_1__SEL_2 or - MUX_ram_word64_set$b_put_2__VAL_2 or - WILL_FIRE_RL_rl_rereq or - rg_addr or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_ram_word64_set$b_put_2__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$ADDRB = req_addr[11:3]; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2; - WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3]; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4; - default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ; - endcase - end - assign ram_word64_set$DIA = - MUX_ram_word64_set$a_put_3__SEL_1 ? - master_xactor_rg_rd_data[66:3] : - MUX_ram_word64_set$a_put_3__VAL_2 ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - MUX_ram_word64_set$b_put_1__SEL_2 or - WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_rereq: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - default: ram_word64_set$DIB = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign ram_word64_set$WEA = 1'd1 ; - assign ram_word64_set$WEB = 1'd0 ; - assign ram_word64_set$ENA = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d639 ; - assign ram_word64_set$ENB = - EN_req && - req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = - (rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8) ? - _theResult___fst__h6279 : - rg_addr ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule tlb - assign tlb$insert_asid = rg_satp[59:44] ; - always@(MUX_tlb$insert_1__SEL_1 or - tlb$lookup or - MUX_tlb$insert_1__SEL_2 or - MUX_tlb$insert_1__SEL_3 or MUX_tlb$insert_1__SEL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_tlb$insert_1__SEL_1: tlb$insert_level = tlb$lookup[65:64]; - MUX_tlb$insert_1__SEL_2: tlb$insert_level = 2'd2; - MUX_tlb$insert_1__SEL_3: tlb$insert_level = 2'd1; - MUX_tlb$insert_1__SEL_4: tlb$insert_level = 2'd0; - default: tlb$insert_level = 2'b10 /* unspecified value */ ; - endcase - end - assign tlb$insert_pte = - (MUX_tlb$insert_1__SEL_2 || MUX_tlb$insert_1__SEL_3 || - MUX_tlb$insert_1__SEL_4) ? - master_xactor_rg_rd_data[66:3] : - value__h6977 ; - assign tlb$insert_pte_pa = - MUX_tlb$insert_1__SEL_1 ? tlb$lookup[63:0] : rg_pte_pa ; - assign tlb$insert_vpn = rg_addr[38:12] ; - assign tlb$lookup_asid = rg_satp[59:44] ; - assign tlb$lookup_vpn = rg_addr[38:12] ; - assign tlb$EN_flush = WILL_FIRE_RL_rl_start_reset || EN_tlb_flush ; - assign tlb$EN_insert = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 || - WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971 || - WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006 || - WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) ; - - // remaining internal signals - assign IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293 = - (x1_avValue_pa__h6190[2:0] == 3'h0) ? - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 : - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d292 ; - assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577 = - (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299 = - (rg_addr[2:0] == 3'h0) ? ld_val__h29543 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217 = - (rg_addr[2:0] == 3'h0) ? - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 : - rg_addr[2:0] != 3'h4 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 ; - assign IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 = - (rg_addr[2:0] == 3'h0) ? word64__h7498 : 64'd0 ; - assign IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 = - (rg_f3 == 3'b010) ? - { {32{rg_st_amo_val_BITS_31_TO_0__q32[31]}}, - rg_st_amo_val_BITS_31_TO_0__q32 } : - rg_st_amo_val ; - assign IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d305 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - !ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 || - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 : - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d304 ; - assign IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d399 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 5'd9 : - IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d398 ; - assign IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d304 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - rg_op_6_EQ_2_9_AND_rg_amo_funct7_1_BITS_6_TO_2_ETC___d248 : - !ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 && - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 && - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 ; - assign IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d398 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - 5'd12 : - ((!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) ? - 5'd9 : - 5'd12) ; - assign IF_rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_am_ETC___d787 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - mem_req_wr_data_wdata__h18986 : - mem_req_wr_data_wdata__h22422 ; - assign IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d401 = - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ? - 5'd4 : - ((dmem_not_imem && !soc_map$m_is_mem_addr) ? - 5'd13 : - IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d399) ; - assign IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 = - x1_avValue_pa__h6190 == rg_lrsc_pa ; - assign NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284 = - x1_avValue_pa__h6190[2:0] != 3'h7 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289 = - x1_avValue_pa__h6190[2:0] != 3'h6 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d292 = - x1_avValue_pa__h6190[2:0] != 3'h4 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_cfg_verbosity_read__8_ULE_2_060___d1061 = cfg_verbosity > 4'd2 ; - assign NOT_cfg_verbosity_read__8_ULT_2_05___d406 = cfg_verbosity >= 4'd2 ; - assign NOT_dmem_not_imem_01_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d341 = - !dmem_not_imem && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb$lookup[69] ; - assign NOT_dmem_not_imem_01_OR_NOT_rg_op_6_EQ_0_7_8_A_ETC___d108 = - !dmem_not_imem || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - !tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d624 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - rg_op != 2'd1 && ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d637 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d635 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d764 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d762 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d798 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d816 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d855 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d853 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d860 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d858 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d866 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d864 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d874 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d872 ; - assign NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d878 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634 ; - assign NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d921 = - master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - ((!master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4]) ? - !master_xactor_crg_rd_addr_full$port2__read : - master_xactor_rg_rd_data[30:22] != 9'd0 || - master_xactor_rg_rd_data[21:13] != 9'd0 || - tlb$RDY_insert) ; - assign NOT_master_xactor_rg_rd_data_97_BITS_2_TO_1_98_ETC___d984 = - master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - ((!master_xactor_rg_rd_data[6] && !master_xactor_rg_rd_data[4]) ? - !master_xactor_crg_rd_addr_full$port2__read : - master_xactor_rg_rd_data[21:13] != 9'd0 || tlb$RDY_insert) ; - assign NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d928 = - !master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - (master_xactor_rg_rd_data[30:22] != 9'd0 || - master_xactor_rg_rd_data[21:13] != 9'd0) || - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign NOT_master_xactor_rg_rd_data_97_BIT_3_01_02_OR_ETC___d990 = - !master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5] || - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[21:13] != 9'd0 || - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 = - !ram_state_and_ctag_cset$DOB[52] || !rg_priv_9_ULE_0b1___d60 || - rg_satp[63:60] != 4'd8 || - tlb$RDY_lookup ; - assign NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d437 = - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 ; - assign NOT_req_f3_BITS_1_TO_0_389_EQ_0b0_390_391_AND__ETC___d1410 = - req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && - (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && - (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; - assign NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294 = - rg_f3 != 3'b011 || - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 ; - assign NOT_rg_op_6_EQ_0_7_8_AND_NOT_rg_op_6_EQ_2_9_0__ETC___d392 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d446 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d761 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d853 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d858 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d864 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d872 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d632 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d759 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d819 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d825 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d831 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d837 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348 = - (rg_priv != 2'b0 || tlb$lookup[70]) && - (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) && - (NOT_dmem_not_imem_01_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d341 || - dmem_not_imem_AND_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_ETC___d343 || - dmem_not_imem && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - tlb$lookup[68]) ; - assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371 = - (rg_priv != 2'b0 || tlb$lookup[70]) && - (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) && - dmem_not_imem && - tlb$lookup[68] ; - assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d409 = - (rg_priv != 2'b0 || tlb$lookup[70]) && - (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) && - tlb$lookup[72] && - !pte___2__h6652[7] && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ; - assign NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d583 = - (rg_priv != 2'b0 || tlb$lookup[70]) && - (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) && - (!dmem_not_imem && tlb$lookup[69] || - dmem_not_imem && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106) ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d142 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d307 = - (NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d142 || - tlb$RDY_lookup && tlb$RDY_insert && f_pte_writebacks$FULL_N) && - (dmem_not_imem && !soc_map$m_is_mem_addr || - IF_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_ETC___d305) ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d353 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130] && - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348 && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d368 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d348 && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d421 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d428 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - (rg_priv != 2'b0 || tlb$lookup[70]) && - (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) && - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d424 && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d431 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d428 && - dmem_not_imem && - !soc_map$m_is_mem_addr && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d452 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d449 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d458 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d420 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15348) ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d459 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d458 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d583 && - tlb$lookup[72] ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d588 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d597 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d604 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d610 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d607 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d616 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d586 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7_1_BITS_6_TO_2_2_EQ_0b10_3_AND_NO_ETC___d613 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - !tlb$lookup[130] || - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371 && - tlb$lookup[72] && - tlb$lookup[73] ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d626 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d624 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d639 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d637 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d766 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d764 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d771 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d767 || - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634) ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d772 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d771 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d800 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d798 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d806 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - rg_lrsc_valid && - !rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d812 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !rg_lrsc_valid && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d818 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d816 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d823 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d819 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d823 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d829 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d825 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d835 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d831 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d835 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d841 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d837 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d841 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d849 = - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15348 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d849 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d857 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d855 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d860 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d866 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d876 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d874 ; - assign NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d880 = - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d620 && - NOT_dmem_not_imem_01_OR_soc_map_m_is_mem_addr__ETC___d878 ; - assign NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123 = - !tlb$lookup[72] || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - !tlb$lookup[73] ; - assign NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d139 = - !tlb$lookup[72] || !tlb$lookup[73] || pte___2__h6652[7] || - rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ; - assign _theResult___fst__h6279 = - tlb$lookup[130] ? _theResult___fst__h6350 : rg_addr ; - assign _theResult___fst__h6350 = - (rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) ? - rg_addr : - _theResult___fst__h6654 ; - assign _theResult___snd_fst__h18994 = rg_st_amo_val << shift_bits__h18787 ; - assign _theResult___snd_fst__h22430 = - new_st_val__h19441 << shift_bits__h18787 ; - assign _theResult___snd_fst__h31152 = rg_st_amo_val << shift_bits__h32449 ; - assign _theResult___snd_fst__h32656 = st_val__h32393 << shift_bits__h32449 ; - assign _theResult___snd_fst__h6281 = - tlb$lookup[130] ? - _theResult___snd_fst__h6352 : - tlb$lookup[129:66] ; - assign _theResult___snd_fst__h6352 = - (rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) ? - tlb$lookup[129:66] : - _theResult___snd_fst__h6883 ; - assign _theResult___snd_fst__h6883 = - (!pte___2__h6652[7] && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010)) ? - pte___1__h6960 : - pte___2__h6652 ; - assign access_exc_code__h3151 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd5 : - 4'd7) : - 4'd1 ; - assign b__h23216 = - ctr_wr_rsps_pending_crg$EN_port0__write ? - ctr_wr_rsps_pending_crg$port0__write_1 : - ctr_wr_rsps_pending_crg ; - assign cfg_verbosity_read__8_ULE_1___d19 = cfg_verbosity <= 4'd1 ; - assign cline_fabric_addr__h26510 = { rg_pa[63:6], 6'd0 } ; - assign dmem_not_imem_AND_rg_op_6_EQ_0_7_OR_rg_op_6_EQ_ETC___d343 = - dmem_not_imem && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 ; - assign dmem_not_imem_OR_NOT_rg_op_6_EQ_0_7_8_AND_NOT__ETC___d100 = - dmem_not_imem || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - !tlb$lookup[69] ; - assign exc_code___1__h6552 = x1_avValue_exc_code__h6191 ; - assign ld_val9543_BITS_15_TO_0__q37 = ld_val__h29543[15:0] ; - assign ld_val9543_BITS_15_TO_8__q39 = ld_val__h29543[15:8] ; - assign ld_val9543_BITS_23_TO_16__q40 = ld_val__h29543[23:16] ; - assign ld_val9543_BITS_31_TO_0__q38 = ld_val__h29543[31:0] ; - assign ld_val9543_BITS_31_TO_16__q41 = ld_val__h29543[31:16] ; - assign ld_val9543_BITS_31_TO_24__q42 = ld_val__h29543[31:24] ; - assign ld_val9543_BITS_39_TO_32__q43 = ld_val__h29543[39:32] ; - assign ld_val9543_BITS_47_TO_32__q44 = ld_val__h29543[47:32] ; - assign ld_val9543_BITS_47_TO_40__q46 = ld_val__h29543[47:40] ; - assign ld_val9543_BITS_55_TO_48__q47 = ld_val__h29543[55:48] ; - assign ld_val9543_BITS_63_TO_32__q45 = ld_val__h29543[63:32] ; - assign ld_val9543_BITS_63_TO_48__q48 = ld_val__h29543[63:48] ; - assign ld_val9543_BITS_63_TO_56__q49 = ld_val__h29543[63:56] ; - assign ld_val9543_BITS_7_TO_0__q36 = ld_val__h29543[7:0] ; - assign lev_0_pte_pa__h25314 = lev_1_PTN_pa__h24255 + vpn_0_pa__h25313 ; - assign lev_0_pte_pa_w64_fa__h25316 = { lev_0_pte_pa__h25314[63:3], 3'b0 } ; - assign lev_1_PTN_pa__h24255 = { 8'd0, x__h24360 } ; - assign lev_1_pte_pa__h24257 = lev_1_PTN_pa__h24255 + vpn_1_pa__h24256 ; - assign lev_1_pte_pa_w64_fa__h24259 = { lev_1_pte_pa__h24257[63:3], 3'b0 } ; - assign lev_2_pte_pa__h23315 = satp_pa__h2470 + vpn_2_pa__h23314 ; - assign lev_2_pte_pa_w64_fa__h23317 = { lev_2_pte_pa__h23315[63:3], 3'b0 } ; - assign lrsc_result__h15348 = - !rg_lrsc_valid || - !rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234 ; - assign master_xactor_crg_rd_data_full_port1__read__96_ETC___d1222 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1006 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[21:13] == 9'd0 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[21:13] == 9'd0 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[21:13] != 9'd0 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - (!master_xactor_rg_rd_data[3] || - !master_xactor_rg_rd_data[4] && master_xactor_rg_rd_data[5]) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - !master_xactor_rg_rd_data[5] && - !master_xactor_rg_rd_data[6] && - !master_xactor_rg_rd_data[4] && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - (master_xactor_rg_rd_data[30:22] != 9'd0 || - master_xactor_rg_rd_data[21:13] != 9'd0) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d971 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[30:22] == 9'd0 && - master_xactor_rg_rd_data[21:13] == 9'd0 ; - assign master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975 = - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[30:22] == 9'd0 && - master_xactor_rg_rd_data[21:13] == 9'd0 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign master_xactor_rg_rd_data_BITS_10_TO_3__q1 = - master_xactor_rg_rd_data[10:3] ; - assign master_xactor_rg_rd_data_BITS_18_TO_11__q4 = - master_xactor_rg_rd_data[18:11] ; - assign master_xactor_rg_rd_data_BITS_18_TO_3__q2 = - master_xactor_rg_rd_data[18:3] ; - assign master_xactor_rg_rd_data_BITS_26_TO_19__q5 = - master_xactor_rg_rd_data[26:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_19__q6 = - master_xactor_rg_rd_data[34:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_27__q7 = - master_xactor_rg_rd_data[34:27] ; - assign master_xactor_rg_rd_data_BITS_34_TO_3__q3 = - master_xactor_rg_rd_data[34:3] ; - assign master_xactor_rg_rd_data_BITS_42_TO_35__q8 = - master_xactor_rg_rd_data[42:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_35__q9 = - master_xactor_rg_rd_data[50:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_43__q11 = - master_xactor_rg_rd_data[50:43] ; - assign master_xactor_rg_rd_data_BITS_58_TO_51__q12 = - master_xactor_rg_rd_data[58:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_35__q10 = - master_xactor_rg_rd_data[66:35] ; - assign master_xactor_rg_rd_data_BITS_66_TO_51__q13 = - master_xactor_rg_rd_data[66:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_59__q14 = - master_xactor_rg_rd_data[66:59] ; - assign new_st_val__h19441 = - (rg_f3 == 3'b010) ? - new_st_val__h19723 : - _theResult_____2__h19719 ; - assign new_st_val__h19723 = { 32'd0, _theResult_____2__h19719[31:0] } ; - assign new_st_val__h19814 = - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 + - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ; - assign new_st_val__h20794 = w1__h19711 ^ w2__h32667 ; - assign new_st_val__h20798 = w1__h19711 & w2__h32667 ; - assign new_st_val__h20802 = w1__h19711 | w2__h32667 ; - assign new_st_val__h20806 = - (w1__h19711 < w2__h32667) ? w1__h19711 : w2__h32667 ; - assign new_st_val__h20811 = - (w1__h19711 <= w2__h32667) ? w2__h32667 : w1__h19711 ; - assign new_st_val__h20817 = - ((IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 ^ - 64'h8000000000000000) < - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^ - 64'h8000000000000000)) ? - w1__h19711 : - w2__h32667 ; - assign new_st_val__h20822 = - ((IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 ^ - 64'h8000000000000000) <= - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^ - 64'h8000000000000000)) ? - w2__h32667 : - w1__h19711 ; - assign new_st_val__h32677 = { 32'd0, _theResult_____2__h32673[31:0] } ; - assign new_st_val__h32768 = - new_ld_val__h32381 + - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ; - assign new_st_val__h34628 = w1__h32665 ^ w2__h32667 ; - assign new_st_val__h34632 = w1__h32665 & w2__h32667 ; - assign new_st_val__h34636 = w1__h32665 | w2__h32667 ; - assign new_st_val__h34640 = - (w1__h32665 < w2__h32667) ? w1__h32665 : w2__h32667 ; - assign new_st_val__h34645 = - (w1__h32665 <= w2__h32667) ? w2__h32667 : w1__h32665 ; - assign new_st_val__h34651 = - ((new_ld_val__h32381 ^ 64'h8000000000000000) < - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^ - 64'h8000000000000000)) ? - w1__h32665 : - w2__h32667 ; - assign new_st_val__h34656 = - ((new_ld_val__h32381 ^ 64'h8000000000000000) <= - (IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_rg_st_amo_val_ETC___d694 ^ - 64'h8000000000000000)) ? - w2__h32667 : - w1__h32665 ; - assign new_value679_BITS_31_TO_0__q31 = new_value__h7679[31:0] ; - assign pa___1__h6660 = { 8'd0, x__h6663 } ; - assign pa___1__h6709 = { 8'd0, x__h6712 } ; - assign pa___1__h6778 = { 8'd0, x__h6781 } ; - assign pte___1__h6932 = { tlb$lookup[129:73], 1'd1, tlb$lookup[71:66] } ; - assign pte___1__h6960 = - { pte___2__h6652[63:8], 1'd1, pte___2__h6652[6:0] } ; - assign pte___2__h6652 = - tlb$lookup[72] ? tlb$lookup[129:66] : pte___1__h6932 ; - assign ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 = - ram_state_and_ctag_cset$DOB[51:0] == - x1_avValue_pa__h6190[63:12] ; - assign ram_state_and_ctag_cset_b_read__73_BIT_52_74_A_ETC___d438 = - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d437 ; - assign req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419 = - req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || - req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || - req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; - assign result__h14088 = - { {56{word64498_BITS_15_TO_8__q18[7]}}, - word64498_BITS_15_TO_8__q18 } ; - assign result__h14116 = - { {56{word64498_BITS_23_TO_16__q19[7]}}, - word64498_BITS_23_TO_16__q19 } ; - assign result__h14144 = - { {56{word64498_BITS_31_TO_24__q21[7]}}, - word64498_BITS_31_TO_24__q21 } ; - assign result__h14172 = - { {56{word64498_BITS_39_TO_32__q22[7]}}, - word64498_BITS_39_TO_32__q22 } ; - assign result__h14200 = - { {56{word64498_BITS_47_TO_40__q25[7]}}, - word64498_BITS_47_TO_40__q25 } ; - assign result__h14228 = - { {56{word64498_BITS_55_TO_48__q26[7]}}, - word64498_BITS_55_TO_48__q26 } ; - assign result__h14256 = - { {56{word64498_BITS_63_TO_56__q28[7]}}, - word64498_BITS_63_TO_56__q28 } ; - assign result__h14301 = { 56'd0, word64__h7498[7:0] } ; - assign result__h14329 = { 56'd0, word64__h7498[15:8] } ; - assign result__h14357 = { 56'd0, word64__h7498[23:16] } ; - assign result__h14385 = { 56'd0, word64__h7498[31:24] } ; - assign result__h14413 = { 56'd0, word64__h7498[39:32] } ; - assign result__h14441 = { 56'd0, word64__h7498[47:40] } ; - assign result__h14469 = { 56'd0, word64__h7498[55:48] } ; - assign result__h14497 = { 56'd0, word64__h7498[63:56] } ; - assign result__h14542 = - { {48{word64498_BITS_15_TO_0__q16[15]}}, - word64498_BITS_15_TO_0__q16 } ; - assign result__h14570 = - { {48{word64498_BITS_31_TO_16__q20[15]}}, - word64498_BITS_31_TO_16__q20 } ; - assign result__h14598 = - { {48{word64498_BITS_47_TO_32__q23[15]}}, - word64498_BITS_47_TO_32__q23 } ; - assign result__h14626 = - { {48{word64498_BITS_63_TO_48__q27[15]}}, - word64498_BITS_63_TO_48__q27 } ; - assign result__h14667 = { 48'd0, word64__h7498[15:0] } ; - assign result__h14695 = { 48'd0, word64__h7498[31:16] } ; - assign result__h14723 = { 48'd0, word64__h7498[47:32] } ; - assign result__h14751 = { 48'd0, word64__h7498[63:48] } ; - assign result__h14792 = - { {32{word64498_BITS_31_TO_0__q17[31]}}, - word64498_BITS_31_TO_0__q17 } ; - assign result__h14820 = - { {32{word64498_BITS_63_TO_32__q24[31]}}, - word64498_BITS_63_TO_32__q24 } ; - assign result__h14859 = { 32'd0, word64__h7498[31:0] } ; - assign result__h14887 = { 32'd0, word64__h7498[63:32] } ; - assign result__h29603 = - { {56{master_xactor_rg_rd_data_BITS_10_TO_3__q1[7]}}, - master_xactor_rg_rd_data_BITS_10_TO_3__q1 } ; - assign result__h29633 = - { {56{master_xactor_rg_rd_data_BITS_18_TO_11__q4[7]}}, - master_xactor_rg_rd_data_BITS_18_TO_11__q4 } ; - assign result__h29660 = - { {56{master_xactor_rg_rd_data_BITS_26_TO_19__q5[7]}}, - master_xactor_rg_rd_data_BITS_26_TO_19__q5 } ; - assign result__h29687 = - { {56{master_xactor_rg_rd_data_BITS_34_TO_27__q7[7]}}, - master_xactor_rg_rd_data_BITS_34_TO_27__q7 } ; - assign result__h29714 = - { {56{master_xactor_rg_rd_data_BITS_42_TO_35__q8[7]}}, - master_xactor_rg_rd_data_BITS_42_TO_35__q8 } ; - assign result__h29741 = - { {56{master_xactor_rg_rd_data_BITS_50_TO_43__q11[7]}}, - master_xactor_rg_rd_data_BITS_50_TO_43__q11 } ; - assign result__h29768 = - { {56{master_xactor_rg_rd_data_BITS_58_TO_51__q12[7]}}, - master_xactor_rg_rd_data_BITS_58_TO_51__q12 } ; - assign result__h29795 = - { {56{master_xactor_rg_rd_data_BITS_66_TO_59__q14[7]}}, - master_xactor_rg_rd_data_BITS_66_TO_59__q14 } ; - assign result__h29839 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h29866 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h29893 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h29920 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h29947 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h29974 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h30001 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h30028 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h30072 = - { {48{master_xactor_rg_rd_data_BITS_18_TO_3__q2[15]}}, - master_xactor_rg_rd_data_BITS_18_TO_3__q2 } ; - assign result__h30099 = - { {48{master_xactor_rg_rd_data_BITS_34_TO_19__q6[15]}}, - master_xactor_rg_rd_data_BITS_34_TO_19__q6 } ; - assign result__h30126 = - { {48{master_xactor_rg_rd_data_BITS_50_TO_35__q9[15]}}, - master_xactor_rg_rd_data_BITS_50_TO_35__q9 } ; - assign result__h30153 = - { {48{master_xactor_rg_rd_data_BITS_66_TO_51__q13[15]}}, - master_xactor_rg_rd_data_BITS_66_TO_51__q13 } ; - assign result__h30193 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h30220 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h30247 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h30274 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h30314 = - { {32{master_xactor_rg_rd_data_BITS_34_TO_3__q3[31]}}, - master_xactor_rg_rd_data_BITS_34_TO_3__q3 } ; - assign result__h30341 = - { {32{master_xactor_rg_rd_data_BITS_66_TO_35__q10[31]}}, - master_xactor_rg_rd_data_BITS_66_TO_35__q10 } ; - assign result__h30379 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h30406 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; - assign result__h32856 = - { {56{ld_val9543_BITS_7_TO_0__q36[7]}}, - ld_val9543_BITS_7_TO_0__q36 } ; - assign result__h33764 = - { {56{ld_val9543_BITS_15_TO_8__q39[7]}}, - ld_val9543_BITS_15_TO_8__q39 } ; - assign result__h33792 = - { {56{ld_val9543_BITS_23_TO_16__q40[7]}}, - ld_val9543_BITS_23_TO_16__q40 } ; - assign result__h33820 = - { {56{ld_val9543_BITS_31_TO_24__q42[7]}}, - ld_val9543_BITS_31_TO_24__q42 } ; - assign result__h33848 = - { {56{ld_val9543_BITS_39_TO_32__q43[7]}}, - ld_val9543_BITS_39_TO_32__q43 } ; - assign result__h33876 = - { {56{ld_val9543_BITS_47_TO_40__q46[7]}}, - ld_val9543_BITS_47_TO_40__q46 } ; - assign result__h33904 = - { {56{ld_val9543_BITS_55_TO_48__q47[7]}}, - ld_val9543_BITS_55_TO_48__q47 } ; - assign result__h33932 = - { {56{ld_val9543_BITS_63_TO_56__q49[7]}}, - ld_val9543_BITS_63_TO_56__q49 } ; - assign result__h33977 = { 56'd0, ld_val__h29543[7:0] } ; - assign result__h34005 = { 56'd0, ld_val__h29543[15:8] } ; - assign result__h34033 = { 56'd0, ld_val__h29543[23:16] } ; - assign result__h34061 = { 56'd0, ld_val__h29543[31:24] } ; - assign result__h34089 = { 56'd0, ld_val__h29543[39:32] } ; - assign result__h34117 = { 56'd0, ld_val__h29543[47:40] } ; - assign result__h34145 = { 56'd0, ld_val__h29543[55:48] } ; - assign result__h34173 = { 56'd0, ld_val__h29543[63:56] } ; - assign result__h34218 = - { {48{ld_val9543_BITS_15_TO_0__q37[15]}}, - ld_val9543_BITS_15_TO_0__q37 } ; - assign result__h34246 = - { {48{ld_val9543_BITS_31_TO_16__q41[15]}}, - ld_val9543_BITS_31_TO_16__q41 } ; - assign result__h34274 = - { {48{ld_val9543_BITS_47_TO_32__q44[15]}}, - ld_val9543_BITS_47_TO_32__q44 } ; - assign result__h34302 = - { {48{ld_val9543_BITS_63_TO_48__q48[15]}}, - ld_val9543_BITS_63_TO_48__q48 } ; - assign result__h34343 = { 48'd0, ld_val__h29543[15:0] } ; - assign result__h34371 = { 48'd0, ld_val__h29543[31:16] } ; - assign result__h34399 = { 48'd0, ld_val__h29543[47:32] } ; - assign result__h34427 = { 48'd0, ld_val__h29543[63:48] } ; - assign result__h34468 = - { {32{ld_val9543_BITS_31_TO_0__q38[31]}}, - ld_val9543_BITS_31_TO_0__q38 } ; - assign result__h34496 = - { {32{ld_val9543_BITS_63_TO_32__q45[31]}}, - ld_val9543_BITS_63_TO_32__q45 } ; - assign result__h34535 = { 32'd0, ld_val__h29543[31:0] } ; - assign result__h34563 = { 32'd0, ld_val__h29543[63:32] } ; - assign result__h7732 = - { {56{word64498_BITS_7_TO_0__q15[7]}}, - word64498_BITS_7_TO_0__q15 } ; - assign rg_amo_funct7_1_BITS_6_TO_2_2_EQ_0b10_3_AND_NO_ETC___d613 = - rg_amo_funct7[6:2] == 5'b00010 && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234 = - rg_lrsc_pa == x1_avValue_pa__h6190 ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d387 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d424 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - tlb$lookup[68] ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d449 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset_b_read__73_BIT_52_74_A_ETC___d438 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d447 ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d453 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d588 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178 && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d607 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178) && - !cfg_verbosity_read__8_ULE_1___d19 ; - assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d447 = - rg_op == 2'd1 && - IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_T_ETC___d435 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d446 ; - assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d635 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d632 || - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d634 ; - assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d762 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_6_EQ_2_9_0_OR_NOT_rg_amo_funct7_1_BI_ETC___d759 || - NOT_rg_op_6_EQ_1_27_43_AND_NOT_rg_op_6_EQ_2_9__ETC___d761 ; - assign rg_op_6_EQ_1_27_OR_rg_op_6_EQ_2_9_AND_rg_amo_f_ETC___d767 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && - rg_lrsc_pa_33_EQ_IF_rg_priv_9_ULE_0b1_0_AND_rg_ETC___d234) ; - assign rg_op_6_EQ_2_9_AND_rg_amo_funct7_1_BITS_6_TO_2_ETC___d248 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h15348 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 ; - assign rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 = - rg_priv == 2'b0 && !tlb$lookup[70] || - rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM || - dmem_not_imem_OR_NOT_rg_op_6_EQ_0_7_8_AND_NOT__ETC___d100 && - NOT_dmem_not_imem_01_OR_NOT_rg_op_6_EQ_0_7_8_A_ETC___d108 && - (!dmem_not_imem || rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - !tlb$lookup[68]) ; - assign rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d130 = - rg_priv == 2'b0 && !tlb$lookup[70] || - rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM || - !dmem_not_imem || - !tlb$lookup[68] ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - tlb$lookup[130] && - (rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d309 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - !tlb$lookup[130] || - (rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 ? - tlb$RDY_lookup : - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d307) ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d356 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - (rg_priv_9_EQ_0b0_6_AND_NOT_tlb_lookup_rg_satp__ETC___d117 || - NOT_tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_ad_ETC___d123) && - tlb$lookup[130] ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - tlb$lookup[130] && - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d371 && - tlb$lookup[72] && - tlb$lookup[73] && - !pte___2__h6652[7] && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d395 = - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d126 || - dmem_not_imem && !soc_map$m_is_mem_addr || - rg_op_6_EQ_0_7_OR_rg_op_6_EQ_2_9_AND_rg_amo_fu_ETC___d387 || - NOT_rg_op_6_EQ_0_7_8_AND_NOT_rg_op_6_EQ_2_9_0__ETC___d392 ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d396 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - !tlb$lookup[130] || - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d395 ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414 = - rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8 && - tlb$lookup[130] && - NOT_rg_priv_9_EQ_0b0_6_34_OR_tlb_lookup_rg_sat_ETC___d409 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406 && - dmem_not_imem && - tlb$lookup[68] && - tlb$lookup[73] ; - assign rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417 = - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406 && - (!dmem_not_imem || !tlb$lookup[68] || !tlb$lookup[73]) ; - assign rg_priv_9_ULE_0b1___d60 = rg_priv <= 2'b01 ; - assign rg_st_amo_val_BITS_31_TO_0__q32 = rg_st_amo_val[31:0] ; - assign rg_state_3_EQ_13_088_AND_rg_op_6_EQ_0_7_OR_rg__ETC___d1090 = - rg_state == 5'd13 && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - b__h23216 == 4'd0 ; - assign rg_state_3_EQ_3_12_AND_NOT_rg_op_6_EQ_0_7_8_AN_ETC___d316 = - rg_state == 5'd3 && - (rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - crg_sb_to_load_delay$port0__write_1 == 11'd0) ; - assign satp_pa__h2470 = { 8'd0, x__h5382 } ; - assign shift_bits__h18787 = { x1_avValue_pa__h6190[2:0], 3'b0 } ; - assign shift_bits__h32449 = { rg_pa[2:0], 3'b0 } ; - assign st_val__h32393 = - (rg_f3 == 3'b010) ? - new_st_val__h32677 : - _theResult_____2__h32673 ; - assign strobe64__h18920 = 8'b00000001 << x1_avValue_pa__h6190[2:0] ; - assign strobe64__h18922 = 8'b00000011 << x1_avValue_pa__h6190[2:0] ; - assign strobe64__h18924 = 8'b00001111 << x1_avValue_pa__h6190[2:0] ; - assign strobe64__h32582 = 8'b00000001 << rg_pa[2:0] ; - assign strobe64__h32584 = 8'b00000011 << rg_pa[2:0] ; - assign strobe64__h32586 = 8'b00001111 << rg_pa[2:0] ; - assign tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d106 = - tlb$lookup[67] | y__h6478 ; - assign tlb_lookup_rg_satp_2_BITS_59_TO_44_9_rg_addr_0_ETC___d350 = - tlb$lookup[72] && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - tlb$lookup[73]) ; - assign value__h6977 = - (rg_priv_9_ULE_0b1___d60 && rg_satp[63:60] == 4'd8) ? - _theResult___snd_fst__h6281 : - tlb$lookup[129:66] ; - assign vpn_0_pa__h25313 = { 52'd0, rg_addr[20:12], 3'd0 } ; - assign vpn_1_pa__h24256 = { 52'd0, rg_addr[29:21], 3'd0 } ; - assign vpn_2_pa__h23314 = { 52'd0, rg_addr[38:30], 3'd0 } ; - assign w12661_BITS_31_TO_0__q51 = w1__h32661[31:0] ; - assign w1___1__h19782 = { 32'd0, new_value__h7679[31:0] } ; - assign w1___1__h32736 = { 32'd0, w1__h32661[31:0] } ; - assign w2___1__h32737 = { 32'd0, rg_st_amo_val[31:0] } ; - assign w2__h32667 = (rg_f3 == 3'b010) ? w2___1__h32737 : rg_st_amo_val ; - assign word64498_BITS_15_TO_0__q16 = word64__h7498[15:0] ; - assign word64498_BITS_15_TO_8__q18 = word64__h7498[15:8] ; - assign word64498_BITS_23_TO_16__q19 = word64__h7498[23:16] ; - assign word64498_BITS_31_TO_0__q17 = word64__h7498[31:0] ; - assign word64498_BITS_31_TO_16__q20 = word64__h7498[31:16] ; - assign word64498_BITS_31_TO_24__q21 = word64__h7498[31:24] ; - assign word64498_BITS_39_TO_32__q22 = word64__h7498[39:32] ; - assign word64498_BITS_47_TO_32__q23 = word64__h7498[47:32] ; - assign word64498_BITS_47_TO_40__q25 = word64__h7498[47:40] ; - assign word64498_BITS_55_TO_48__q26 = word64__h7498[55:48] ; - assign word64498_BITS_63_TO_32__q24 = word64__h7498[63:32] ; - assign word64498_BITS_63_TO_48__q27 = word64__h7498[63:48] ; - assign word64498_BITS_63_TO_56__q28 = word64__h7498[63:56] ; - assign word64498_BITS_7_TO_0__q15 = word64__h7498[7:0] ; - assign word64__h7498 = ram_word64_set$DOB & y__h7768 ; - assign x1_avValue_exc_code__h6191 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd13 : - 4'd15) : - 4'd12 ; - assign x1_avValue_pa__h6190 = soc_map$m_is_mem_addr_addr ; - assign x__h15358 = { 63'd0, lrsc_result__h15348 } ; - assign x__h24360 = { master_xactor_rg_rd_data[56:13], 12'b0 } ; - assign x__h5382 = { rg_satp[43:0], 12'b0 } ; - assign x__h6663 = { tlb$lookup[119:76], rg_addr[11:0] } ; - assign x__h6712 = { tlb$lookup[119:85], rg_addr[20:0] } ; - assign x__h6781 = { tlb$lookup[119:94], rg_addr[29:0] } ; - assign y__h6478 = rg_mstatus_MXR & tlb$lookup[69] ; - assign y__h7768 = - {64{ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__73_BITS_51_TO__ETC___d178}} ; - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h31966 = 3'b0; - 2'b01: value__h31966 = 3'b001; - 2'b10: value__h31966 = 3'b010; - 2'd3: value__h31966 = 3'b011; - endcase - end - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h34992 = 3'b0; - 2'b01: value__h34992 = 3'b001; - 2'b10: value__h34992 = 3'b010; - 2'b11: value__h34992 = 3'b011; - endcase - end - always@(tlb$lookup or - rg_addr or pa___1__h6660 or pa___1__h6709 or pa___1__h6778) - begin - case (tlb$lookup[65:64]) - 2'd0: _theResult___fst__h6654 = pa___1__h6660; - 2'd1: _theResult___fst__h6654 = pa___1__h6709; - 2'd2: _theResult___fst__h6654 = pa___1__h6778; - 2'd3: _theResult___fst__h6654 = rg_addr; - endcase - end - always@(rg_f3 or strobe64__h32582 or strobe64__h32584 or strobe64__h32586) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h32649 = strobe64__h32582; - 2'b01: mem_req_wr_data_wstrb__h32649 = strobe64__h32584; - 2'b10: mem_req_wr_data_wstrb__h32649 = strobe64__h32586; - 2'b11: mem_req_wr_data_wstrb__h32649 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h31152) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h31144 = _theResult___snd_fst__h31152; - 2'd3: mem_req_wr_data_wdata__h31144 = rg_st_amo_val; - endcase - end - always@(rg_f3 or strobe64__h18920 or strobe64__h18922 or strobe64__h18924) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h18987 = strobe64__h18920; - 2'b01: mem_req_wr_data_wstrb__h18987 = strobe64__h18922; - 2'b10: mem_req_wr_data_wstrb__h18987 = strobe64__h18924; - 2'b11: mem_req_wr_data_wstrb__h18987 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h18994) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h18986 = _theResult___snd_fst__h18994; - 2'd3: mem_req_wr_data_wdata__h18986 = rg_st_amo_val; - endcase - end - always@(rg_f3 or rg_priv_9_ULE_0b1___d60 or rg_satp or tlb$RDY_lookup) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01: - IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 = - !rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$RDY_lookup; - default: IF_rg_f3_81_BITS_1_TO_0_38_EQ_0b0_39_OR_rg_f3__ETC___d245 = - rg_f3[1:0] != 2'b10 || !rg_priv_9_ULE_0b1___d60 || - rg_satp[63:60] != 4'd8 || - tlb$RDY_lookup; - endcase - end - always@(rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199) - begin - case (rg_addr[2:0]) - 3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 = - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199; - 3'd7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 = - rg_addr[2:0] != 3'h7 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199; - endcase - end - always@(rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199) - begin - case (rg_addr[2:0]) - 3'h0, 3'h2, 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 = - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 = - rg_addr[2:0] != 3'h6 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199; - endcase - end - always@(rg_f3 or - rg_addr or - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217) - begin - case (rg_f3) - 3'b0, 3'b100: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d203; - 3'b001, 3'b101: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_OR_rg_ad_ETC___d211; - 3'b010, 3'b110: - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_NOT_ETC___d217; - default: IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225 = - rg_f3 != 3'b011 || rg_addr[2:0] != 3'h0 || - NOT_ram_state_and_ctag_cset_b_read__73_BIT_52__ETC___d199; - endcase - end - always@(rg_amo_funct7 or - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225) - begin - case (rg_amo_funct7[6:2]) - 5'b0, 5'b00100, 5'b01000, 5'b01100, 5'b10000, 5'b11000, 5'b11100: - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 = - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225; - default: CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29 = - rg_amo_funct7[6:2] != 5'b10100 || - IF_rg_f3_81_EQ_0b0_82_OR_rg_f3_81_EQ_0b100_83__ETC___d225; - endcase - end - always@(x1_avValue_pa__h6190 or - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284 or - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285 = - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29; - 3'd7: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285 = - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d284; - endcase - end - always@(x1_avValue_pa__h6190 or - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289 or - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0, 3'h2, 3'h4: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290 = - CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_81_ETC__q29; - default: IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290 = - NOT_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS__ETC___d289; - endcase - end - always@(rg_f3 or - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294 or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285 or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290 or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d285; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d290; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d293; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d297 = - NOT_rg_f3_81_EQ_0b11_18_19_OR_rg_amo_funct7_1__ETC___d294; - endcase - end - always@(rg_addr or - result__h7732 or - result__h14088 or - result__h14116 or - result__h14144 or - result__h14172 or - result__h14200 or result__h14228 or result__h14256) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h7732; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14088; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14116; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14144; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14172; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14200; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14228; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 = - result__h14256; - endcase - end - always@(rg_addr or - result__h14301 or - result__h14329 or - result__h14357 or - result__h14385 or - result__h14413 or - result__h14441 or result__h14469 or result__h14497) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14301; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14329; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14357; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14385; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14413; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14441; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14469; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 = - result__h14497; - endcase - end - always@(rg_addr or - result__h14542 or - result__h14570 or result__h14598 or result__h14626) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 = - result__h14542; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 = - result__h14570; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 = - result__h14598; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 = - result__h14626; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 = - 64'd0; - endcase - end - always@(rg_addr or - result__h14667 or - result__h14695 or result__h14723 or result__h14751) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 = - result__h14667; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 = - result__h14695; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 = - result__h14723; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 = - result__h14751; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 = - 64'd0; - endcase - end - always@(rg_addr or result__h14859 or result__h14887) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562 = - result__h14859; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562 = - result__h14887; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562 = - 64'd0; - endcase - end - always@(rg_addr or result__h14792 or result__h14820) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30 = - result__h14792; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30 = - result__h14820; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562) - begin - case (rg_f3) - 3'b0: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516; - 3'b001: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544; - 3'b010: - new_value__h7679 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4792_0x4_re_ETC__q30; - 3'b011: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563; - 3'b100: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532; - 3'b101: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552; - 3'b110: - new_value__h7679 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562; - 3'd7: new_value__h7679 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 or - w1___1__h19782 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562) - begin - case (rg_f3) - 3'b0: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516; - 3'b001: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544; - 3'b010: w1__h19711 = w1___1__h19782; - 3'b011: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563; - 3'b100: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532; - 3'b101: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552; - 3'b110: - w1__h19711 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562; - 3'd7: w1__h19711 = 64'd0; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 = - { ram_word64_set$DOB[63:16], rg_st_amo_val[15:0] }; - 3'h2: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 = - { rg_st_amo_val[15:0], ram_word64_set$DOB[47:0] }; - default: IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 = - ram_word64_set$DOB; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:8], rg_st_amo_val[7:0] }; - 3'h1: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:16], - rg_st_amo_val[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:24], - rg_st_amo_val[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:40], - rg_st_amo_val[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { ram_word64_set$DOB[63:56], - rg_st_amo_val[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 = - { rg_st_amo_val[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544 or - new_value679_BITS_31_TO_0__q31 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d516; - 3'b001: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d544; - 3'b010: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - { {32{new_value679_BITS_31_TO_0__q31[31]}}, - new_value679_BITS_31_TO_0__q31 }; - 3'b011: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_ram_ETC___d563; - 3'b100: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d532; - 3'b101: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d552; - 3'b110: - IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d562; - 3'd7: IF_rg_f3_81_EQ_0b10_12_THEN_SEXT_IF_rg_f3_81_E_ETC___d630 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h20822 or - new_st_val__h19814 or - w2__h32667 or - new_st_val__h20794 or - new_st_val__h20802 or - new_st_val__h20798 or - new_st_val__h20817 or new_st_val__h20806 or new_st_val__h20811) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h19719 = new_st_val__h19814; - 5'b00001: _theResult_____2__h19719 = w2__h32667; - 5'b00100: _theResult_____2__h19719 = new_st_val__h20794; - 5'b01000: _theResult_____2__h19719 = new_st_val__h20802; - 5'b01100: _theResult_____2__h19719 = new_st_val__h20798; - 5'b10000: _theResult_____2__h19719 = new_st_val__h20817; - 5'b11000: _theResult_____2__h19719 = new_st_val__h20806; - 5'b11100: _theResult_____2__h19719 = new_st_val__h20811; - default: _theResult_____2__h19719 = new_st_val__h20822; - endcase - end - always@(rg_f3 or new_st_val__h19441 or _theResult___snd_fst__h22430) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h22422 = _theResult___snd_fst__h22430; - 2'd3: mem_req_wr_data_wdata__h22422 = new_st_val__h19441; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or new_st_val__h19441) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 = - { ram_word64_set$DOB[63:16], new_st_val__h19441[15:0] }; - 3'h2: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 = - { ram_word64_set$DOB[63:32], - new_st_val__h19441[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 = - { ram_word64_set$DOB[63:48], - new_st_val__h19441[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 = - { new_st_val__h19441[15:0], ram_word64_set$DOB[47:0] }; - default: IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 = - ram_word64_set$DOB; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or new_st_val__h19441) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:8], new_st_val__h19441[7:0] }; - 3'h1: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:16], - new_st_val__h19441[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:24], - new_st_val__h19441[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:32], - new_st_val__h19441[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:40], - new_st_val__h19441[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:48], - new_st_val__h19441[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { ram_word64_set$DOB[63:56], - new_st_val__h19441[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 = - { new_st_val__h19441[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or rg_st_amo_val) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - { ram_word64_set$DOB[63:32], rg_st_amo_val[31:0] }; - 3'h4: - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - { rg_st_amo_val[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672 or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681 or - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33 or - rg_st_amo_val) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d672; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d681; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 = - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q33; - 3'b011: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 = - rg_st_amo_val; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or - result__h30193 or - result__h30220 or result__h30247 or result__h30274) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 = - result__h30193; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 = - result__h30220; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 = - result__h30247; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 = - result__h30274; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 = - 64'd0; - endcase - end - always@(rg_addr or - result__h30072 or - result__h30099 or result__h30126 or result__h30153) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 = - result__h30072; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 = - result__h30099; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 = - result__h30126; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 = - result__h30153; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 = - 64'd0; - endcase - end - always@(rg_addr or - result__h29839 or - result__h29866 or - result__h29893 or - result__h29920 or - result__h29947 or - result__h29974 or result__h30001 or result__h30028) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29839; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29866; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29893; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29920; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29947; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h29974; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h30001; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 = - result__h30028; - endcase - end - always@(rg_addr or - result__h29603 or - result__h29633 or - result__h29660 or - result__h29687 or - result__h29714 or - result__h29741 or result__h29768 or result__h29795) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29603; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29633; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29660; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29687; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29714; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29741; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29768; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 = - result__h29795; - endcase - end - always@(rg_addr or result__h30314 or result__h30341) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34 = - result__h30314; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34 = - result__h30341; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34 = - 64'd0; - endcase - end - always@(rg_addr or result__h30379 or result__h30406) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35 = - result__h30379; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35 = - result__h30406; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156 or - CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34 or - rg_addr or - master_xactor_rg_rd_data or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164 or - CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35) - begin - case (rg_f3) - 3'b0: - ld_val__h29543 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1128; - 3'b001: - ld_val__h29543 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1156; - 3'b010: - ld_val__h29543 = - CASE_rg_addr_BITS_2_TO_0_0x0_result0314_0x4_re_ETC__q34; - 3'b011: - ld_val__h29543 = - (rg_addr[2:0] == 3'h0) ? master_xactor_rg_rd_data[66:3] : 64'd0; - 3'b100: - ld_val__h29543 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1144; - 3'b101: - ld_val__h29543 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1164; - 3'b110: - ld_val__h29543 = - CASE_rg_addr_BITS_2_TO_0_0x0_result0379_0x4_re_ETC__q35; - 3'd7: ld_val__h29543 = 64'd0; - endcase - end - always@(rg_addr or result__h34535 or result__h34563) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 = - result__h34535; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 = - result__h34563; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298 = - 64'd0; - endcase - end - always@(rg_addr or - result__h34343 or - result__h34371 or result__h34399 or result__h34427) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 = - result__h34343; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 = - result__h34371; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 = - result__h34399; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 = - result__h34427; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 = - 64'd0; - endcase - end - always@(rg_addr or - result__h34218 or - result__h34246 or result__h34274 or result__h34302) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 = - result__h34218; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 = - result__h34246; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 = - result__h34274; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 = - result__h34302; - default: IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 = - 64'd0; - endcase - end - always@(rg_addr or - result__h33977 or - result__h34005 or - result__h34033 or - result__h34061 or - result__h34089 or - result__h34117 or result__h34145 or result__h34173) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h33977; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34005; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34033; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34061; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34089; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34117; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34145; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 = - result__h34173; - endcase - end - always@(rg_addr or - result__h32856 or - result__h33764 or - result__h33792 or - result__h33820 or - result__h33848 or - result__h33876 or result__h33904 or result__h33932) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h32856; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33764; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33792; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33820; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33848; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33876; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33904; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 = - result__h33932; - endcase - end - always@(rg_addr or result__h34468 or result__h34496) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50 = - result__h34468; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50 = - result__h34496; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298) - begin - case (rg_f3) - 3'b0: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252; - 3'b001: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280; - 3'b010: - w1__h32661 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4468_0x4_re_ETC__q50; - 3'b011: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299; - 3'b100: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268; - 3'b101: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288; - 3'b110: - w1__h32661 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298; - 3'd7: w1__h32661 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 or - w1___1__h32736 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298) - begin - case (rg_f3) - 3'b0: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252; - 3'b001: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280; - 3'b010: w1__h32665 = w1___1__h32736; - 3'b011: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299; - 3'b100: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268; - 3'b101: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288; - 3'b110: - w1__h32665 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298; - 3'd7: w1__h32665 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280 or - w12661_BITS_31_TO_0__q51 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288 or - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298) - begin - case (rg_f3) - 3'b0: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1252; - 3'b001: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_SEX_ETC___d1280; - 3'b010: - new_ld_val__h32381 = - { {32{w12661_BITS_31_TO_0__q51[31]}}, - w12661_BITS_31_TO_0__q51 }; - 3'b011: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_IF__ETC___d1299; - 3'b100: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1268; - 3'b101: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1288; - 3'b110: - new_ld_val__h32381 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_0_C_ETC___d1298; - 3'd7: new_ld_val__h32381 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h34656 or - new_st_val__h32768 or - w2__h32667 or - new_st_val__h34628 or - new_st_val__h34636 or - new_st_val__h34632 or - new_st_val__h34651 or new_st_val__h34640 or new_st_val__h34645) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h32673 = new_st_val__h32768; - 5'b00001: _theResult_____2__h32673 = w2__h32667; - 5'b00100: _theResult_____2__h32673 = new_st_val__h34628; - 5'b01000: _theResult_____2__h32673 = new_st_val__h34636; - 5'b01100: _theResult_____2__h32673 = new_st_val__h34632; - 5'b10000: _theResult_____2__h32673 = new_st_val__h34651; - 5'b11000: _theResult_____2__h32673 = new_st_val__h34640; - 5'b11100: _theResult_____2__h32673 = new_st_val__h34645; - default: _theResult_____2__h32673 = new_st_val__h34656; - endcase - end - always@(rg_f3 or st_val__h32393 or _theResult___snd_fst__h32656) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h32648 = _theResult___snd_fst__h32656; - 2'd3: mem_req_wr_data_wdata__h32648 = st_val__h32393; - endcase - end - always@(x1_avValue_pa__h6190 or ram_word64_set$DOB or new_st_val__h19441) - begin - case (x1_avValue_pa__h6190[2:0]) - 3'h0: - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - { ram_word64_set$DOB[63:32], new_st_val__h19441[31:0] }; - 3'h4: - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - { new_st_val__h19441[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737 or - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746 or - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52 or - new_st_val__h19441) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d737; - 3'b001: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 = - IF_IF_rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_6_ETC___d746; - 3'b010: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 = - CASE_x1_avValue_pa190_BITS_2_TO_0_0x0_ram_word_ETC__q52; - 3'b011: - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 = - new_st_val__h19441; - default: IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577) - begin - case (rg_f3) - 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: - new_value__h17706 = - IF_rg_addr_0_BITS_2_TO_0_85_EQ_0x0_86_THEN_1_E_ETC___d577; - 3'd7: new_value__h17706 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0; - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_sb_to_load_delay$EN) - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY - crg_sb_to_load_delay$D_IN; - if (ctr_wr_rsps_pending_crg$EN) - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY - ctr_wr_rsps_pending_crg$D_IN; - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_cset_in_cache$EN) - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN; - if (rg_lower_word32_full$EN) - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY - rg_lower_word32_full$D_IN; - if (rg_lrsc_valid$EN) - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; - if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN; - if (rg_amo_funct7$EN) - rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN; - if (rg_error_during_refill$EN) - rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY - rg_error_during_refill$D_IN; - if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN; - if (rg_lower_word32$EN) - rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN; - if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN; - if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN; - if (rg_priv$EN) rg_priv <= `BSV_ASSIGNMENT_DELAY rg_priv$D_IN; - if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN; - if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_st_amo_val$EN) - rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN; - if (rg_word64_set_in_cache$EN) - rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY - rg_word64_set_in_cache$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_sb_to_load_delay = 11'h2AA; - ctr_wr_rsps_pending_crg = 4'hA; - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; - rg_addr = 64'hAAAAAAAAAAAAAAAA; - rg_amo_funct7 = 7'h2A; - rg_cset_in_cache = 6'h2A; - rg_error_during_refill = 1'h0; - rg_exc_code = 4'hA; - rg_f3 = 3'h2; - rg_ld_val = 64'hAAAAAAAAAAAAAAAA; - rg_lower_word32 = 32'hAAAAAAAA; - rg_lower_word32_full = 1'h0; - rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA; - rg_lrsc_valid = 1'h0; - rg_mstatus_MXR = 1'h0; - rg_op = 2'h2; - rg_pa = 64'hAAAAAAAAAAAAAAAA; - rg_priv = 2'h2; - rg_pte_pa = 64'hAAAAAAAAAAAAAAAA; - rg_satp = 64'hAAAAAAAAAAAAAAAA; - rg_sstatus_SUM = 1'h0; - rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; - rg_state = 5'h0A; - rg_word64_set_in_cache = 9'h0AA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - begin - v__h4708 = $stime; - #0; - end - v__h4702 = v__h4708 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h4702, - "D_MMU_Cache", - $signed(32'd64), - $signed(32'd1)); - else - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h4702, - "I_MMU_Cache", - $signed(32'd64), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - !cfg_verbosity_read__8_ULE_1___d19 && - f_reset_reqs$D_OUT) - begin - v__h4809 = $stime; - #0; - end - v__h4803 = v__h4809 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - !cfg_verbosity_read__8_ULE_1___d19 && - f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: Flushed", v__h4803, "D_MMU_Cache"); - else - $display("%0d: %s.rl_reset: Flushed", v__h4803, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_rereq && !cfg_verbosity_read__8_ULE_1___d19) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - rg_addr[11:6], - rg_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h30746 = $stime; - #0; - end - v__h30740 = v__h30746 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h30740, - "D_MMU_Cache", - rg_addr, - rg_ld_val); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h30740, - "I_MMU_Cache", - rg_addr, - rg_ld_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h31644 = $stime; - #0; - end - v__h31638 = v__h31644 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h31638, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h31638, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19) - $display(" FAIL due to I/O address."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__8_ULE_1___d19) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h4339 = $stime; - #0; - end - v__h4333 = v__h4339 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_start_reset", v__h4333, "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_reset", v__h4333, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h5262 = $stime; - #0; - end - v__h5256 = v__h5262 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h5256, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h5256, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - rg_satp[63:60] != 4'd0) - $display(" Priv:%0d SATP:{mode %0d asid %0h pa %0h} VA:%0h.%0h.%0h", - rg_priv, - rg_satp[63:60], - rg_satp[59:44], - satp_pa__h2470, - rg_addr[29:21], - rg_addr[20:12], - rg_addr[11:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", - rg_addr[63:12], - rg_addr[11:6], - rg_addr[5:3], - rg_addr[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" CSet 0x%0x: (state, tag):", rg_addr[11:6]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" ("); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - ram_state_and_ctag_cset$DOB[52]) - $write("CTAG_CLEAN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - !ram_state_and_ctag_cset$DOB[52]) - $write("CTAG_EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - ram_state_and_ctag_cset$DOB[52]) - $write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - !ram_state_and_ctag_cset$DOB[52]) - $write(", --"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(")"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" TLB result: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d353) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d356) - $write("VM_XLATE_EXCEPTION"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - rg_priv_9_ULE_0b1___d60 && - rg_satp[63:60] == 4'd8 && - !tlb$lookup[130]) - $write("VM_XLATE_TLB_MISS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", x1_avValue_exc_code__h6191); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "pte_modified: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d368) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", value__h6977, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $display(" fa_record_pte_A_D_updates:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("TLB_Lookup_Result { ", "hit: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", tlb$lookup[129:66]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pte_level: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", tlb$lookup[65:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pte_pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", tlb$lookup[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417) - $write("VM_XLATE_EXCEPTION"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", x1_avValue_exc_code__h6191); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pte_modified: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d417) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d414) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write(", ", "pte: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("'h%h", value__h6977, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - rg_priv_9_ULE_0b1_0_AND_rg_satp_2_BITS_63_TO_6_ETC___d378 && - NOT_cfg_verbosity_read__8_ULT_2_05___d406) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d431) - $display(" => IO_REQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591) - begin - v__h14971 = $stime; - #0; - end - v__h14965 = v__h14971 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h14965, - "D_MMU_Cache", - rg_addr, - word64__h7498, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h14965, - "I_MMU_Cache", - rg_addr, - word64__h7498, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d604) - $display(" AMO LR: reserving PA 0x%0h", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d591) - $display(" Read-hit: addr 0x%0h word64 0x%0h", - rg_addr, - word64__h7498); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d610) - $display(" Read Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d616) - $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", - rg_lrsc_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d800) - $display(" ST: cancelling LR/SC reservation for PA", - x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d806) - $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", - rg_lrsc_pa, - x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d812) - $display(" AMO SC: fail due to invalid LR/SC reservation"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d818) - $display(" AMO SC result = %0d", lrsc_result__h15348); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824) - $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", - x1_avValue_pa__h6190, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824) - $write(" 0x%0x", - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d690); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d824) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!rg_priv_9_ULE_0b1___d60 || rg_satp[63:60] != 4'd8 || - tlb$lookup[130]) && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d829) - $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", - x1_avValue_pa__h6190, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842) - begin - v__h19190 = $stime; - #0; - end - v__h19184 = v__h19190 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842) - $display("%0d: ERROR: CreditCounter: overflow", v__h19184); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d842) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", value__h34992); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", mem_req_wr_data_wdata__h18986); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", mem_req_wr_data_wstrb__h18987); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d836) - $display(" => rl_write_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850) - begin - v__h18615 = $stime; - #0; - end - v__h18609 = v__h18615 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h18609, - "D_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h18609, - "I_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d850) - $display(" AMO SC: Fail response for addr 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d857) - $display(" AMO Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", - rg_addr, - rg_amo_funct7, - rg_f3, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $display(" PA 0x%0h ", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $display(" Cache word64 0x%0h, load-result 0x%0h", - word64__h7498, - word64__h7498); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $display(" 0x%0h op 0x%0h -> 0x%0h", - word64__h7498, - word64__h7498, - new_st_val__h19441); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(" 0x%0x", - IF_rg_f3_81_EQ_0b0_82_THEN_IF_IF_rg_priv_9_ULE_ETC___d755); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868) - begin - v__h22626 = $stime; - #0; - end - v__h22620 = v__h22626 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868) - $display("%0d: ERROR: CreditCounter: overflow", v__h22620); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d868) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", value__h34992); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", mem_req_wr_data_wdata__h22422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", mem_req_wr_data_wstrb__h18987); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d862) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_rg_priv_9_ULE_0b1_0_1_OR_NOT_rg_satp_2_BIT_ETC___d876) - $display(" AMO_op: cancelling LR/SC reservation for PA", - x1_avValue_pa__h6190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - begin - v__h24225 = $stime; - #0; - end - v__h24219 = v__h24225 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h24219, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - else - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h24219, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - begin - v__h23982 = $stime; - #0; - end - v__h23976 = v__h23982 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - if (dmem_not_imem) - $display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1", - v__h23976, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1", - v__h23976, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $display(" Req for level 1 PTE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", lev_1_pte_pa_w64_fa__h24259); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963) - begin - v__h24536 = $stime; - #0; - end - v__h24530 = v__h24536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d963) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h", - v__h24530, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h", - v__h24530, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - (master_xactor_rg_rd_data[30:22] != 9'd0 || - master_xactor_rg_rd_data[21:13] != 9'd0)) - $display(" Invalid PTE: PPN[1] or PPN[0] is not zero; page fault %0d", - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975) - begin - v__h24648 = $stime; - #0; - end - v__h24642 = v__h24648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage", - v__h24642, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage", - v__h24642, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d975) - $display(" Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h24255); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h24154 = $stime; - #0; - end - v__h24148 = v__h24154 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_2 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h24148, - "D_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - else - $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h24148, - "I_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - begin - v__h25282 = $stime; - #0; - end - v__h25276 = v__h25282 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h25276, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h25276, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - begin - v__h25042 = $stime; - #0; - end - v__h25036 = v__h25042 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - if (dmem_not_imem) - $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0", - v__h25036, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0", - v__h25036, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $display(" Req for level 0 PTE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", lev_0_pte_pa_w64_fa__h25316); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010) - begin - v__h25705 = $stime; - #0; - end - v__h25699 = v__h25705 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage", - v__h25699, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage", - v__h25699, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1010) - $display(" Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h24255); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016) - begin - v__h25593 = $stime; - #0; - end - v__h25587 = v__h25593 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1016) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h", - v__h25587, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h", - v__h25587, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - master_xactor_rg_rd_data[3] && - (master_xactor_rg_rd_data[4] || !master_xactor_rg_rd_data[5]) && - (master_xactor_rg_rd_data[6] || master_xactor_rg_rd_data[4]) && - master_xactor_rg_rd_data[21:13] != 9'd0) - $display(" Invalid PTE: PPN [0] is not zero; page fault %0d", - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h25211 = $stime; - #0; - end - v__h25205 = v__h25211 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_1 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h25205, - "D_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - else - $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h25205, - "I_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - begin - v__h26177 = $stime; - #0; - end - v__h26171 = v__h26177 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d937) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h26171, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d", - v__h26171, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - begin - v__h26248 = $stime; - #0; - end - v__h26242 = v__h26248 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d947) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d", - v__h26242, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d", - v__h26242, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa, - exc_code___1__h6552); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041) - begin - v__h26330 = $stime; - #0; - end - v__h26324 = v__h26330 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE", - v__h26324, - "D_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE", - v__h26324, - "I_MMU_Cache", - rg_addr, - master_xactor_rg_rd_data[66:3], - rg_pte_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data_97_BITS_2_TO_1_98_EQ__ETC___d1041) - $display(" Addr Space page pa: 0x%0h", lev_1_PTN_pa__h24255); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h26106 = $stime; - #0; - end - v__h26100 = v__h26106 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_ptw_level_0 && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h26100, - "D_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - else - $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d", - v__h26100, - "I_MMU_Cache", - rg_addr, - rg_pte_pa, - access_exc_code__h3151); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - begin - v__h27239 = $stime; - #0; - end - v__h27233 = v__h27239 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h27233, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h27233, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h27461 = $stime; - #0; - end - v__h27455 = v__h27461 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h27455, - "D_MMU_Cache", - access_exc_code__h3151); - else - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h27455, - "I_MMU_Cache", - access_exc_code__h3151); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 && - (master_xactor_rg_rd_data[2:1] != 2'b0 || rg_error_during_refill) && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" => MODULE_EXCEPTION_RSP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !rg_error_during_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" => CACHE_REREQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", - rg_word64_set_in_cache, - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write(" 0x%0x", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__8_ULE_2_060___d1061) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h29434 = $stime; - #0; - end - v__h29428 = v__h29434 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h29428, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h29428, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h30534 = $stime; - #0; - end - v__h30528 = v__h30534 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h30528, - "D_MMU_Cache", - rg_addr, - ld_val__h29543); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h30528, - "I_MMU_Cache", - rg_addr, - ld_val__h29543); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h30641 = $stime; - #0; - end - v__h30635 = v__h30641 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h30635, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h30635, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h30826 = $stime; - #0; - end - v__h30820 = v__h30826 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h30820, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h30820, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h31348 = $stime; - #0; - end - v__h31342 = v__h31348 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h31342); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", value__h34992); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", mem_req_wr_data_wdata__h31144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", mem_req_wr_data_wstrb__h32649); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__8_ULE_1___d19) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h31762 = $stime; - #0; - end - v__h31756 = v__h31762 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h31756, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h31756, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", value__h31966); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h3705 = $stime; - #0; - end - v__h3699 = v__h3705 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h3699); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", f_pte_writebacks$D_OUT[127:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", f_pte_writebacks$D_OUT[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd255); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_updated_PTE && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h32080 = $stime; - #0; - end - v__h32074 = v__h32080 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h32074, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h32074, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h32255 = $stime; - #0; - end - v__h32249 = v__h32255 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h32249, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h32249, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h34868 = $stime; - #0; - end - v__h34862 = v__h34868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h34862); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", value__h34992); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", mem_req_wr_data_wdata__h32648); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", mem_req_wr_data_wstrb__h32649); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h35120 = $stime; - #0; - end - v__h35114 = v__h35120 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h35114, - "D_MMU_Cache", - rg_addr, - new_ld_val__h32381); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h35114, - "I_MMU_Cache", - rg_addr, - new_ld_val__h32381); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h32351 = $stime; - #0; - end - v__h32345 = v__h32351 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h32345, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h32345, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h23262 = $stime; - #0; - end - v__h23256 = v__h23262 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE", - v__h23256, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE", - v__h23256, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", lev_2_pte_pa_w64_fa__h23317); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_tlb_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h26457 = $stime; - #0; - end - v__h26451 = v__h26457 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_start_cache_refill: ", - v__h26451, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_cache_refill: ", - v__h26451, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", cline_fabric_addr__h26510); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd7); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" Victim way %0d; => CACHE_REFILL", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h29060 = $stime; - #0; - end - v__h29054 = v__h29060 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h29054, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h29054, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", value__h31966); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h36090 = $stime; - #0; - end - v__h36084 = v__h36090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $write("%0d: %s.req: op:", v__h36084, "D_MMU_Cache"); - else - $write("%0d: %s.req: op:", v__h36084, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_op == 2'd0) - $write("CACHE_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_op == 2'd1) - $write("CACHE_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_op != 2'd0 && - req_op != 2'd1) - $write("CACHE_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", - req_f3, - req_addr, - req_st_value); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv == 2'b0) - $write("U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv == 2'b01) - $write("S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv == 2'b11) - $write("M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19 && req_priv != 2'b0 && - req_priv != 2'b01 && - req_priv != 2'b11) - $write("RESERVED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19) - $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && !cfg_verbosity_read__8_ULE_1___d19) - $display(" amo_funct7 = 0x%0h", req_amo_funct7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && - req_f3_BITS_1_TO_0_389_EQ_0b0_390_OR_req_f3_BI_ETC___d1419 && - !cfg_verbosity_read__8_ULE_1___d19) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - req_addr[11:6], - req_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_tlb_flush && !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h37244 = $stime; - #0; - end - v__h37238 = v__h37244 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_tlb_flush && !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $display("%0d: %s.tlb_flush", v__h37238, "D_MMU_Cache"); - else - $display("%0d: %s.tlb_flush", v__h37238, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - begin - v__h35740 = $stime; - #0; - end - v__h35734 = v__h35740 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - if (dmem_not_imem) - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h35734, - "D_MMU_Cache", - $unsigned(b__h23216)); - else - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h35734, - "I_MMU_Cache", - $unsigned(b__h23216)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - !cfg_verbosity_read__8_ULE_1___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - begin - v__h35701 = $stime; - #0; - end - v__h35695 = v__h35701 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - if (dmem_not_imem) - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h35695, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h35695, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("\n"); - end - // synopsys translate_on -endmodule // mkMMU_Cache - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v deleted file mode 100644 index f673c615..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v +++ /dev/null @@ -1,2169 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// to_raw_mem_response_put I 256 -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_to_raw_mem_response_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Controller(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [63 : 0] slave_rdata; - wire [7 : 0] status; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // inlined wires - reg [353 : 0] f_raw_mem_reqs_rv$port1__write_1; - wire [353 : 0] f_raw_mem_reqs_rv$port1__read, - f_raw_mem_reqs_rv$port2__read, - f_raw_mem_reqs_rv$port3__read; - wire [256 : 0] f_raw_mem_rsps_rv$port1__read, - f_raw_mem_rsps_rv$port1__write_1, - f_raw_mem_rsps_rv$port2__read, - f_raw_mem_rsps_rv$port3__read; - wire [170 : 0] f_reqs_rv$port1__read, - f_reqs_rv$port1__write_1, - f_reqs_rv$port2__read; - wire f_raw_mem_reqs_rv$EN_port1__write, - f_reqs_rv$EN_port0__write, - f_reqs_rv$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register f_raw_mem_reqs_rv - reg [353 : 0] f_raw_mem_reqs_rv; - wire [353 : 0] f_raw_mem_reqs_rv$D_IN; - wire f_raw_mem_reqs_rv$EN; - - // register f_raw_mem_rsps_rv - reg [256 : 0] f_raw_mem_rsps_rv; - wire [256 : 0] f_raw_mem_rsps_rv$D_IN; - wire f_raw_mem_rsps_rv$EN; - - // register f_reqs_rv - reg [170 : 0] f_reqs_rv; - wire [170 : 0] f_reqs_rv$D_IN; - wire f_reqs_rv$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_cached_clean - reg rg_cached_clean; - wire rg_cached_clean$D_IN, rg_cached_clean$EN; - - // register rg_cached_raw_mem_addr - reg [63 : 0] rg_cached_raw_mem_addr; - wire [63 : 0] rg_cached_raw_mem_addr$D_IN; - wire rg_cached_raw_mem_addr$EN; - - // register rg_cached_raw_mem_word - reg [255 : 0] rg_cached_raw_mem_word; - wire [255 : 0] rg_cached_raw_mem_word$D_IN; - wire rg_cached_raw_mem_word$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_status - reg [7 : 0] rg_status; - wire [7 : 0] rg_status$D_IN; - wire rg_status$EN; - - // register rg_tohost_addr - reg [63 : 0] rg_tohost_addr; - wire [63 : 0] rg_tohost_addr$D_IN; - wire rg_tohost_addr$EN; - - // register rg_watch_tohost - reg rg_watch_tohost; - wire rg_watch_tohost$D_IN, rg_watch_tohost$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_external_reset, - CAN_FIRE_RL_rl_invalid_rd_address, - CAN_FIRE_RL_rl_invalid_wr_address, - CAN_FIRE_RL_rl_merge_rd_req, - CAN_FIRE_RL_rl_merge_wr_req, - CAN_FIRE_RL_rl_miss_clean_req, - CAN_FIRE_RL_rl_power_on_reset, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reload, - CAN_FIRE_RL_rl_reset_reload_cache, - CAN_FIRE_RL_rl_writeback_dirty, - CAN_FIRE_RL_rl_writeback_dirty_idle, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_external_reset, - WILL_FIRE_RL_rl_invalid_rd_address, - WILL_FIRE_RL_rl_invalid_wr_address, - WILL_FIRE_RL_rl_merge_rd_req, - WILL_FIRE_RL_rl_merge_wr_req, - WILL_FIRE_RL_rl_miss_clean_req, - WILL_FIRE_RL_rl_power_on_reset, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reload, - WILL_FIRE_RL_rl_reset_reload_cache, - WILL_FIRE_RL_rl_writeback_dirty, - WILL_FIRE_RL_rl_writeback_dirty_idle, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire [353 : 0] MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1, - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - wire [255 : 0] MUX_rg_cached_raw_mem_word$write_1__VAL_1; - wire [170 : 0] MUX_f_reqs_rv$port1__write_1__VAL_1, - MUX_f_reqs_rv$port1__write_1__VAL_2; - wire [70 : 0] MUX_slave_xactor_f_rd_data$enq_1__VAL_1, - MUX_slave_xactor_f_rd_data$enq_1__VAL_2; - wire [5 : 0] MUX_slave_xactor_f_wr_resp$enq_1__VAL_1, - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2; - wire MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2538; - reg [31 : 0] v__h3481; - reg [31 : 0] v__h3974; - reg [31 : 0] v__h4443; - reg [31 : 0] v__h4706; - reg [31 : 0] v__h5425; - reg [31 : 0] v__h7622; - reg [31 : 0] v__h7823; - reg [31 : 0] v__h8335; - reg [31 : 0] v__h9119; - reg [31 : 0] v__h9714; - reg [31 : 0] v__h2853; - reg [31 : 0] v__h3193; - reg [31 : 0] v__h1743; - reg [31 : 0] v__h2088; - reg [31 : 0] v__h1737; - reg [31 : 0] v__h2082; - reg [31 : 0] v__h2532; - reg [31 : 0] v__h2847; - reg [31 : 0] v__h3187; - reg [31 : 0] v__h3475; - reg [31 : 0] v__h3968; - reg [31 : 0] v__h4437; - reg [31 : 0] v__h4700; - reg [31 : 0] v__h5419; - reg [31 : 0] v__h7616; - reg [31 : 0] v__h7817; - reg [31 : 0] v__h8329; - reg [31 : 0] v__h9113; - reg [31 : 0] v__h9708; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rdata__h5068, word64_old__h5862; - wire [63 : 0] exit_value__h7860, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1, - mask__h5867, - req_raw_mem_addr__h3314, - updated_word64__h5868, - x__h6241, - y__h6242, - y__h6243; - wire [7 : 0] SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191; - wire [4 : 0] n__h5067; - wire NOT_cfg_verbosity_read_ULE_1___d5, - NOT_cfg_verbosity_read_ULE_2_2___d33, - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279, - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128, - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123, - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126, - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135, - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284, - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131, - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = rg_state == 2'd3 ; - assign CAN_FIRE_set_addr_map = rg_state == 2'd3 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = f_raw_mem_reqs_rv[352:0] ; - assign RDY_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign CAN_FIRE_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = !f_raw_mem_rsps_rv$port1__read[256] ; - assign CAN_FIRE_to_raw_mem_response_put = - !f_raw_mem_rsps_rv$port1__read[256] ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // value method status - assign status = rg_status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset_reload_cache - assign CAN_FIRE_RL_rl_reset_reload_cache = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_reload_cache = - CAN_FIRE_RL_rl_reset_reload_cache ; - - // rule RL_rl_writeback_dirty_idle - assign CAN_FIRE_RL_rl_writeback_dirty_idle = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd3 && - !f_reqs_rv[170] && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty_idle = - CAN_FIRE_RL_rl_writeback_dirty_idle ; - - // rule RL_rl_writeback_dirty - assign CAN_FIRE_RL_rl_writeback_dirty = - !f_raw_mem_reqs_rv$port1__read[353] && f_reqs_rv[170] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty = CAN_FIRE_RL_rl_writeback_dirty ; - - // rule RL_rl_miss_clean_req - assign CAN_FIRE_RL_rl_miss_clean_req = - f_reqs_rv[170] && !f_raw_mem_reqs_rv$port1__read[353] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - rg_cached_clean ; - assign WILL_FIRE_RL_rl_miss_clean_req = - CAN_FIRE_RL_rl_miss_clean_req && - !WILL_FIRE_RL_rl_external_reset && - !EN_set_addr_map ; - - // rule RL_rl_reload - assign CAN_FIRE_RL_rl_reload = f_raw_mem_rsps_rv[256] && rg_state == 2'd2 ; - assign WILL_FIRE_RL_rl_reload = CAN_FIRE_RL_rl_reload ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_invalid_rd_address - assign CAN_FIRE_RL_rl_invalid_rd_address = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_rd_address = - CAN_FIRE_RL_rl_invalid_rd_address ; - - // rule RL_rl_invalid_wr_address - assign CAN_FIRE_RL_rl_invalid_wr_address = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_wr_address = - CAN_FIRE_RL_rl_invalid_wr_address ; - - // rule RL_rl_merge_rd_req - assign CAN_FIRE_RL_rl_merge_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && !f_reqs_rv$port1__read[170] ; - assign WILL_FIRE_RL_rl_merge_rd_req = CAN_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_merge_wr_req - assign CAN_FIRE_RL_rl_merge_wr_req = - !f_reqs_rv$port1__read[170] && slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N ; - assign WILL_FIRE_RL_rl_merge_wr_req = - CAN_FIRE_RL_rl_merge_wr_req && !WILL_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_power_on_reset - assign CAN_FIRE_RL_rl_power_on_reset = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_power_on_reset = CAN_FIRE_RL_rl_power_on_reset ; - - // rule RL_rl_external_reset - assign CAN_FIRE_RL_rl_external_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && rg_state == 2'd3 ; - assign WILL_FIRE_RL_rl_external_reset = CAN_FIRE_RL_rl_external_reset ; - - // inputs to muxes for submodule ports - assign MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - assign MUX_rg_state$write_1__SEL_1 = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - assign MUX_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 = - { 34'h3FFFFFFFF, - rg_cached_raw_mem_addr, - rg_cached_raw_mem_word } ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3 = - { 34'h2FFFFFFFF, - req_raw_mem_addr__h3314, - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_1 = - { 2'd2, slave_xactor_f_rd_addr$D_OUT, 72'hAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_2 = - { 2'd3, - slave_xactor_f_wr_addr$D_OUT, - slave_xactor_f_wr_data$D_OUT[8:1], - slave_xactor_f_wr_data$D_OUT[72:9] } ; - assign MUX_rg_cached_raw_mem_word$write_1__VAL_1 = - { (f_reqs_rv[105:104] == 2'd3) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[255:192], - (f_reqs_rv[105:104] == 2'd2) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[191:128], - (f_reqs_rv[105:104] == 2'd1) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[127:64], - (f_reqs_rv[105:104] == 2'd0) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[63:0] } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_1 = - { f_reqs_rv[168:165], rdata__h5068, 3'd1 } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_2 = - { f_reqs_rv[168:101], 3'd5 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 = - { f_reqs_rv[168:165], 2'd0 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 = - { f_reqs_rv[168:165], 2'd2 } ; - - // inlined wires - assign f_reqs_rv$EN_port0__write = - WILL_FIRE_RL_rl_invalid_wr_address || - WILL_FIRE_RL_rl_invalid_rd_address || - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs_rv$port1__read = - f_reqs_rv$EN_port0__write ? - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_reqs_rv ; - assign f_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_merge_rd_req || WILL_FIRE_RL_rl_merge_wr_req ; - assign f_reqs_rv$port1__write_1 = - WILL_FIRE_RL_rl_merge_rd_req ? - MUX_f_reqs_rv$port1__write_1__VAL_1 : - MUX_f_reqs_rv$port1__write_1__VAL_2 ; - assign f_reqs_rv$port2__read = - f_reqs_rv$EN_port1__write ? - f_reqs_rv$port1__write_1 : - f_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port1__read = - EN_to_raw_mem_request_get ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv ; - assign f_raw_mem_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_miss_clean_req ; - always@(MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 or - WILL_FIRE_RL_rl_reset_reload_cache or - WILL_FIRE_RL_rl_miss_clean_req or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1; - WILL_FIRE_RL_rl_reset_reload_cache: - f_raw_mem_reqs_rv$port1__write_1 = - 354'h2FFFFFFFF0000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_miss_clean_req: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - default: f_raw_mem_reqs_rv$port1__write_1 = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign f_raw_mem_reqs_rv$port2__read = - f_raw_mem_reqs_rv$EN_port1__write ? - f_raw_mem_reqs_rv$port1__write_1 : - f_raw_mem_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv$port2__read ; - assign f_raw_mem_rsps_rv$port1__read = - CAN_FIRE_RL_rl_reload ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv ; - assign f_raw_mem_rsps_rv$port1__write_1 = - { 1'd1, to_raw_mem_response_put } ; - assign f_raw_mem_rsps_rv$port2__read = - EN_to_raw_mem_response_put ? - f_raw_mem_rsps_rv$port1__write_1 : - f_raw_mem_rsps_rv$port1__read ; - assign f_raw_mem_rsps_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv$port2__read ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register f_raw_mem_reqs_rv - assign f_raw_mem_reqs_rv$D_IN = f_raw_mem_reqs_rv$port3__read ; - assign f_raw_mem_reqs_rv$EN = 1'b1 ; - - // register f_raw_mem_rsps_rv - assign f_raw_mem_rsps_rv$D_IN = f_raw_mem_rsps_rv$port3__read ; - assign f_raw_mem_rsps_rv$EN = 1'b1 ; - - // register f_reqs_rv - assign f_reqs_rv$D_IN = f_reqs_rv$port2__read ; - assign f_reqs_rv$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_cached_clean - assign rg_cached_clean$D_IN = !WILL_FIRE_RL_rl_process_wr_req ; - assign rg_cached_clean$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload || - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - - // register rg_cached_raw_mem_addr - assign rg_cached_raw_mem_addr$D_IN = - WILL_FIRE_RL_rl_miss_clean_req ? - req_raw_mem_addr__h3314 : - 64'd0 ; - assign rg_cached_raw_mem_addr$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_cached_raw_mem_word - assign rg_cached_raw_mem_word$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_rg_cached_raw_mem_word$write_1__VAL_1 : - f_raw_mem_rsps_rv[255:0] ; - assign rg_cached_raw_mem_word$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload ; - - // register rg_state - always@(MUX_rg_state$write_1__SEL_1 or - MUX_rg_state$write_1__SEL_2 or WILL_FIRE_RL_rl_reload) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_state$write_1__SEL_1: rg_state$D_IN = 2'd1; - MUX_rg_state$write_1__SEL_2: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reload: rg_state$D_IN = 2'd3; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset || - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_reload ; - - // register rg_status - assign rg_status$D_IN = - (WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset) ? - 8'd0 : - 8'd1 ; - assign rg_status$EN = - WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 || - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - - // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_watch_tohost ; - - // register rg_watch_tohost - assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ; - assign rg_watch_tohost$EN = EN_set_watch_tohost ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_merge_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_slave_xactor_f_rd_data$enq_1__VAL_1 : - MUX_slave_xactor_f_rd_data$enq_1__VAL_2 ; - assign slave_xactor_f_rd_data$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_invalid_rd_address ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 : - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 ; - assign slave_xactor_f_wr_resp$ENQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_invalid_wr_address ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_1 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d5 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read_ULE_2_2___d33 = cfg_verbosity > 4'd2 ; - assign NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 = - f_reqs_rv[92:90] != 3'b0 && - (f_reqs_rv[92:90] != 3'b001 || f_reqs_rv[101]) && - (f_reqs_rv[92:90] != 3'b010 || f_reqs_rv[102:101] != 2'h0) && - (f_reqs_rv[92:90] != 3'b011 || f_reqs_rv[103:101] != 3'h0) && - (f_reqs_rv[92:90] != 3'b100 || f_reqs_rv[104:101] != 4'h0) && - (f_reqs_rv[92:90] != 3'b101 || f_reqs_rv[105:101] != 5'h0) && - (f_reqs_rv[92:90] != 3'b110 || f_reqs_rv[106:101] != 6'h0) && - (f_reqs_rv[92:90] != 3'b111 || f_reqs_rv[107:101] != 7'h0) ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 = {8{f_reqs_rv[64]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212 = {8{f_reqs_rv[65]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208 = {8{f_reqs_rv[66]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205 = {8{f_reqs_rv[67]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201 = {8{f_reqs_rv[68]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198 = {8{f_reqs_rv[69]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194 = {8{f_reqs_rv[70]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191 = {8{f_reqs_rv[71]}} ; - assign exit_value__h7860 = { 1'd0, f_reqs_rv[63:1] } ; - assign f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1 = - f_reqs_rv[164:101] - rg_addr_base ; - assign f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 = - f_reqs_rv[164:101] < rg_addr_lim ; - assign f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 = - f_reqs_rv[92:90] == 3'b0 || - f_reqs_rv[92:90] == 3'b001 && !f_reqs_rv[101] || - f_reqs_rv[92:90] == 3'b010 && f_reqs_rv[102:101] == 2'h0 || - f_reqs_rv[92:90] == 3'b011 && f_reqs_rv[103:101] == 3'h0 || - f_reqs_rv[92:90] == 3'b100 && f_reqs_rv[104:101] == 4'h0 || - f_reqs_rv[92:90] == 3'b101 && f_reqs_rv[105:101] == 5'h0 || - f_reqs_rv[92:90] == 3'b110 && f_reqs_rv[106:101] == 6'h0 || - f_reqs_rv[92:90] == 3'b111 && f_reqs_rv[107:101] == 7'h0 ; - assign mask__h5867 = - { SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - assign n__h5067 = { 3'd0, f_reqs_rv[105:104] } ; - assign req_raw_mem_addr__h3314 = - { 5'd0, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1[63:5] } ; - assign rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 = - rg_addr_base <= f_reqs_rv[164:101] ; - assign rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 = - rg_cached_raw_mem_addr == req_raw_mem_addr__h3314 ; - assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 = - rg_state == 2'd3 && - (NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 || - !rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 || - !f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128) ; - assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 = - rg_state == 2'd3 && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 && - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 && - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 ; - assign rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 = - rg_watch_tohost && f_reqs_rv[164:101] == rg_tohost_addr && - f_reqs_rv[63:0] != 64'd0 ; - assign updated_word64__h5868 = x__h6241 | y__h6242 ; - assign x__h6241 = word64_old__h5862 & y__h6243 ; - assign y__h6242 = f_reqs_rv[63:0] & mask__h5867 ; - assign y__h6243 = - { ~SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - ~SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - ~SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - ~SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - ~SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - ~SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - ~SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - ~SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - always@(f_reqs_rv or rg_cached_raw_mem_word) - begin - case (f_reqs_rv[105:104]) - 2'd0: word64_old__h5862 = rg_cached_raw_mem_word[63:0]; - 2'd1: word64_old__h5862 = rg_cached_raw_mem_word[127:64]; - 2'd2: word64_old__h5862 = rg_cached_raw_mem_word[191:128]; - 2'd3: word64_old__h5862 = rg_cached_raw_mem_word[255:192]; - endcase - end - always@(n__h5067 or rg_cached_raw_mem_word) - begin - case (n__h5067) - 5'd0: rdata__h5068 = rg_cached_raw_mem_word[63:0]; - 5'd1: rdata__h5068 = rg_cached_raw_mem_word[127:64]; - 5'd2: rdata__h5068 = rg_cached_raw_mem_word[191:128]; - 5'd3: rdata__h5068 = rg_cached_raw_mem_word[255:192]; - default: rdata__h5068 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - rg_status <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000; - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (f_raw_mem_reqs_rv$EN) - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_reqs_rv$D_IN; - if (f_raw_mem_rsps_rv$EN) - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_rsps_rv$D_IN; - if (f_reqs_rv$EN) f_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_reqs_rv$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_status$EN) rg_status <= `BSV_ASSIGNMENT_DELAY rg_status$D_IN; - if (rg_tohost_addr$EN) - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; - if (rg_watch_tohost$EN) - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_cached_clean$EN) - rg_cached_clean <= `BSV_ASSIGNMENT_DELAY rg_cached_clean$D_IN; - if (rg_cached_raw_mem_addr$EN) - rg_cached_raw_mem_addr <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_addr$D_IN; - if (rg_cached_raw_mem_word$EN) - rg_cached_raw_mem_word <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_word$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - f_raw_mem_reqs_rv = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv = 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_cached_clean = 1'h0; - rg_cached_raw_mem_addr = 64'hAAAAAAAAAAAAAAAA; - rg_cached_raw_mem_word = - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state = 2'h2; - rg_status = 8'hAA; - rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; - rg_watch_tohost = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2538 = $stime; - #0; - end - v__h2532 = v__h2538 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING", - v__h2532); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3481 = $stime; - #0; - end - v__h3475 = v__h3481 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h", - v__h3475, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3974 = $stime; - #0; - end - v__h3968 = v__h3974 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h", - v__h3968, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4443 = $stime; - #0; - end - v__h4437 = v__h4443 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h", - v__h4437, - req_raw_mem_addr__h3314); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_reload: raw addr 0x%0h", - v__h4700, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", f_raw_mem_rsps_rv[255:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h5425 = $stime; - #0; - end - v__h5419 = v__h5425 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", rdata__h5068); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h7622 = $stime; - #0; - end - v__h7616 = v__h7622 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7616); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - begin - v__h7823 = $stime; - #0; - end - v__h7817 = v__h7823 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - $display("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h () data 0x%0h", - v__h7817, - f_reqs_rv[164:101], - f_reqs_rv[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] == 63'd0) - $display("PASS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] != 63'd0) - $display("FAIL %0d", exit_value__h7860); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - begin - v__h8335 = $stime; - #0; - end - v__h8329 = v__h8335 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("%0d: ERROR: Mem_Controller:", v__h8329); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" read-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" read-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - begin - v__h9119 = $stime; - #0; - end - v__h9113 = v__h9119 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("%0d: ERROR: Mem_Controller:", v__h9113); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" write-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" write-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - begin - v__h9714 = $stime; - #0; - end - v__h9708 = v__h9714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - $display("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9708, - set_addr_map_addr_base, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h2853 = $stime; - #0; - end - v__h2847 = v__h2853 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_rd_req", v__h2847); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3193 = $stime; - #0; - end - v__h3187 = v__h3193 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_wr_req", v__h3187); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h1743 = $stime; - #0; - end - v__h1737 = v__h1743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_power_on_reset", v__h1737); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2088 = $stime; - #0; - end - v__h2082 = v__h2088 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE", - v__h2082); - end - // synopsys translate_on -endmodule // mkMem_Controller - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v deleted file mode 100644 index 104c51b0..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v +++ /dev/null @@ -1,192 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_mem_server_request_put O 1 reg -// mem_server_response_get O 256 reg -// RDY_mem_server_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// mem_server_request_put I 353 -// EN_mem_server_request_put I 1 -// EN_mem_server_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Model(CLK, - RST_N, - - mem_server_request_put, - EN_mem_server_request_put, - RDY_mem_server_request_put, - - EN_mem_server_response_get, - mem_server_response_get, - RDY_mem_server_response_get); - input CLK; - input RST_N; - - // action method mem_server_request_put - input [352 : 0] mem_server_request_put; - input EN_mem_server_request_put; - output RDY_mem_server_request_put; - - // actionvalue method mem_server_response_get - input EN_mem_server_response_get; - output [255 : 0] mem_server_response_get; - output RDY_mem_server_response_get; - - // signals for module outputs - wire [255 : 0] mem_server_response_get; - wire RDY_mem_server_request_put, RDY_mem_server_response_get; - - // ports of submodule f_raw_mem_rsps - wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT; - wire f_raw_mem_rsps$CLR, - f_raw_mem_rsps$DEQ, - f_raw_mem_rsps$EMPTY_N, - f_raw_mem_rsps$ENQ, - f_raw_mem_rsps$FULL_N; - - // ports of submodule rf - wire [255 : 0] rf$D_IN, rf$D_OUT_1; - wire [63 : 0] rf$ADDR_1, - rf$ADDR_2, - rf$ADDR_3, - rf$ADDR_4, - rf$ADDR_5, - rf$ADDR_IN; - wire rf$WE; - - // rule scheduling signals - wire CAN_FIRE_mem_server_request_put, - CAN_FIRE_mem_server_response_get, - WILL_FIRE_mem_server_request_put, - WILL_FIRE_mem_server_response_get; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h371; - reg [31 : 0] v__h365; - // synopsys translate_on - - // remaining internal signals - wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2; - - // action method mem_server_request_put - assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ; - - // actionvalue method mem_server_response_get - assign mem_server_response_get = f_raw_mem_rsps$D_OUT ; - assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ; - - // submodule f_raw_mem_rsps - FIFO2 #(.width(32'd256), .guarded(32'd1)) f_raw_mem_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_raw_mem_rsps$D_IN), - .ENQ(f_raw_mem_rsps$ENQ), - .DEQ(f_raw_mem_rsps$DEQ), - .CLR(f_raw_mem_rsps$CLR), - .D_OUT(f_raw_mem_rsps$D_OUT), - .FULL_N(f_raw_mem_rsps$FULL_N), - .EMPTY_N(f_raw_mem_rsps$EMPTY_N)); - - // submodule rf - RegFileLoad #(.file("Mem.hex"), - .addr_width(32'd64), - .data_width(32'd256), - .lo(64'd0), - .hi(64'd8388607), - .binary(1'd0)) rf(.CLK(CLK), - .ADDR_1(rf$ADDR_1), - .ADDR_2(rf$ADDR_2), - .ADDR_3(rf$ADDR_3), - .ADDR_4(rf$ADDR_4), - .ADDR_5(rf$ADDR_5), - .ADDR_IN(rf$ADDR_IN), - .D_IN(rf$D_IN), - .WE(rf$WE), - .D_OUT_1(rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule f_raw_mem_rsps - assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ; - assign f_raw_mem_rsps$ENQ = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - !mem_server_request_put[352] ; - assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ; - assign f_raw_mem_rsps$CLR = 1'b0 ; - - // submodule rf - assign rf$ADDR_1 = mem_server_request_put[319:256] ; - assign rf$ADDR_2 = 64'h0 ; - assign rf$ADDR_3 = 64'h0 ; - assign rf$ADDR_4 = 64'h0 ; - assign rf$ADDR_5 = 64'h0 ; - assign rf$ADDR_IN = mem_server_request_put[319:256] ; - assign rf$D_IN = mem_server_request_put[255:0] ; - assign rf$WE = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - mem_server_request_put[352] ; - - // remaining internal signals - assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 = - mem_server_request_put[319:256] < 64'h0000000000800000 ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - begin - v__h371 = $stime; - #0; - end - v__h365 = v__h371 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)", - v__h365, - mem_server_request_put[319:256], - 64'h0000000000800000); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkMem_Model - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v deleted file mode 100644 index 4c587b57..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v +++ /dev/null @@ -1,1660 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 -// RDY_server_reset_response_get O 1 reg -// imem_valid O 1 -// imem_is_i32_not_i16 O 1 const -// imem_pc O 64 reg -// imem_instr O 32 -// imem_exc O 1 -// imem_exc_code O 4 reg -// imem_tval O 64 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_valid O 1 -// dmem_word64 O 64 -// dmem_st_amo_val O 64 -// dmem_exc O 1 -// dmem_exc_code O 4 reg -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_server_fence_i_request_put O 1 -// RDY_server_fence_i_response_get O 1 -// RDY_server_fence_request_put O 1 reg -// RDY_server_fence_response_get O 1 -// RDY_sfence_vma O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// imem_req_f3 I 3 -// imem_req_addr I 64 -// imem_req_priv I 2 reg -// imem_req_sstatus_SUM I 1 reg -// imem_req_mstatus_MXR I 1 reg -// imem_req_satp I 64 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_req_op I 2 -// dmem_req_f3 I 3 -// dmem_req_amo_funct7 I 7 reg -// dmem_req_addr I 64 -// dmem_req_store_value I 64 -// dmem_req_priv I 2 reg -// dmem_req_sstatus_SUM I 1 reg -// dmem_req_mstatus_MXR I 1 reg -// dmem_req_satp I 64 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// server_fence_request_put I 8 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_imem_req I 1 -// EN_dmem_req I 1 -// EN_server_fence_i_request_put I 1 -// EN_server_fence_i_response_get I 1 -// EN_server_fence_request_put I 1 -// EN_server_fence_response_get I 1 -// EN_sfence_vma I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_valid -// (imem_master_awready, imem_master_wready) -> imem_instr -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// imem_master_arready, -// EN_imem_req) -> imem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_valid -// (dmem_master_awready, dmem_master_wready) -> dmem_word64 -// (dmem_master_awready, dmem_master_wready) -> dmem_st_amo_val -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// (dmem_master_awready, -// dmem_master_wready, -// dmem_master_arready, -// EN_dmem_req) -> dmem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - imem_req_f3, - imem_req_addr, - imem_req_priv, - imem_req_sstatus_SUM, - imem_req_mstatus_MXR, - imem_req_satp, - EN_imem_req, - - imem_valid, - - imem_is_i32_not_i16, - - imem_pc, - - imem_instr, - - imem_exc, - - imem_exc_code, - - imem_tval, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_req_op, - dmem_req_f3, - dmem_req_amo_funct7, - dmem_req_addr, - dmem_req_store_value, - dmem_req_priv, - dmem_req_sstatus_SUM, - dmem_req_mstatus_MXR, - dmem_req_satp, - EN_dmem_req, - - dmem_valid, - - dmem_word64, - - dmem_st_amo_val, - - dmem_exc, - - dmem_exc_code, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - EN_server_fence_i_request_put, - RDY_server_fence_i_request_put, - - EN_server_fence_i_response_get, - RDY_server_fence_i_response_get, - - server_fence_request_put, - EN_server_fence_request_put, - RDY_server_fence_request_put, - - EN_server_fence_response_get, - RDY_server_fence_response_get, - - EN_sfence_vma, - RDY_sfence_vma); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method imem_req - input [2 : 0] imem_req_f3; - input [63 : 0] imem_req_addr; - input [1 : 0] imem_req_priv; - input imem_req_sstatus_SUM; - input imem_req_mstatus_MXR; - input [63 : 0] imem_req_satp; - input EN_imem_req; - - // value method imem_valid - output imem_valid; - - // value method imem_is_i32_not_i16 - output imem_is_i32_not_i16; - - // value method imem_pc - output [63 : 0] imem_pc; - - // value method imem_instr - output [31 : 0] imem_instr; - - // value method imem_exc - output imem_exc; - - // value method imem_exc_code - output [3 : 0] imem_exc_code; - - // value method imem_tval - output [63 : 0] imem_tval; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // action method dmem_req - input [1 : 0] dmem_req_op; - input [2 : 0] dmem_req_f3; - input [6 : 0] dmem_req_amo_funct7; - input [63 : 0] dmem_req_addr; - input [63 : 0] dmem_req_store_value; - input [1 : 0] dmem_req_priv; - input dmem_req_sstatus_SUM; - input dmem_req_mstatus_MXR; - input [63 : 0] dmem_req_satp; - input EN_dmem_req; - - // value method dmem_valid - output dmem_valid; - - // value method dmem_word64 - output [63 : 0] dmem_word64; - - // value method dmem_st_amo_val - output [63 : 0] dmem_st_amo_val; - - // value method dmem_exc - output dmem_exc; - - // value method dmem_exc_code - output [3 : 0] dmem_exc_code; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method server_fence_i_request_put - input EN_server_fence_i_request_put; - output RDY_server_fence_i_request_put; - - // action method server_fence_i_response_get - input EN_server_fence_i_response_get; - output RDY_server_fence_i_response_get; - - // action method server_fence_request_put - input [7 : 0] server_fence_request_put; - input EN_server_fence_request_put; - output RDY_server_fence_request_put; - - // action method server_fence_response_get - input EN_server_fence_response_get; - output RDY_server_fence_response_get; - - // action method sfence_vma - input EN_sfence_vma; - output RDY_sfence_vma; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - dmem_st_amo_val, - dmem_word64, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata, - imem_pc, - imem_tval; - wire [31 : 0] imem_instr; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_exc_code, - dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_exc_code, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_server_fence_i_request_put, - RDY_server_fence_i_response_get, - RDY_server_fence_request_put, - RDY_server_fence_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_sfence_vma, - dmem_exc, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - dmem_valid, - imem_exc, - imem_is_i32_not_i16, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid, - imem_valid; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule dcache - wire [63 : 0] dcache$mem_master_araddr, - dcache$mem_master_awaddr, - dcache$mem_master_rdata, - dcache$mem_master_wdata, - dcache$req_addr, - dcache$req_satp, - dcache$req_st_value, - dcache$st_amo_val, - dcache$word64; - wire [7 : 0] dcache$mem_master_arlen, - dcache$mem_master_awlen, - dcache$mem_master_wstrb; - wire [6 : 0] dcache$req_amo_funct7; - wire [3 : 0] dcache$exc_code, - dcache$mem_master_arcache, - dcache$mem_master_arid, - dcache$mem_master_arqos, - dcache$mem_master_arregion, - dcache$mem_master_awcache, - dcache$mem_master_awid, - dcache$mem_master_awqos, - dcache$mem_master_awregion, - dcache$mem_master_bid, - dcache$mem_master_rid, - dcache$mem_master_wid, - dcache$set_verbosity_verbosity; - wire [2 : 0] dcache$mem_master_arprot, - dcache$mem_master_arsize, - dcache$mem_master_awprot, - dcache$mem_master_awsize, - dcache$req_f3; - wire [1 : 0] dcache$mem_master_arburst, - dcache$mem_master_awburst, - dcache$mem_master_bresp, - dcache$mem_master_rresp, - dcache$req_op, - dcache$req_priv; - wire dcache$EN_req, - dcache$EN_server_flush_request_put, - dcache$EN_server_flush_response_get, - dcache$EN_server_reset_request_put, - dcache$EN_server_reset_response_get, - dcache$EN_set_verbosity, - dcache$EN_tlb_flush, - dcache$RDY_server_flush_request_put, - dcache$RDY_server_flush_response_get, - dcache$RDY_server_reset_request_put, - dcache$RDY_server_reset_response_get, - dcache$exc, - dcache$mem_master_arlock, - dcache$mem_master_arready, - dcache$mem_master_arvalid, - dcache$mem_master_awlock, - dcache$mem_master_awready, - dcache$mem_master_awvalid, - dcache$mem_master_bready, - dcache$mem_master_bvalid, - dcache$mem_master_rlast, - dcache$mem_master_rready, - dcache$mem_master_rvalid, - dcache$mem_master_wlast, - dcache$mem_master_wready, - dcache$mem_master_wvalid, - dcache$req_mstatus_MXR, - dcache$req_sstatus_SUM, - dcache$valid; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule icache - wire [63 : 0] icache$addr, - icache$mem_master_araddr, - icache$mem_master_awaddr, - icache$mem_master_rdata, - icache$mem_master_wdata, - icache$req_addr, - icache$req_satp, - icache$req_st_value, - icache$word64; - wire [7 : 0] icache$mem_master_arlen, - icache$mem_master_awlen, - icache$mem_master_wstrb; - wire [6 : 0] icache$req_amo_funct7; - wire [3 : 0] icache$exc_code, - icache$mem_master_arcache, - icache$mem_master_arid, - icache$mem_master_arqos, - icache$mem_master_arregion, - icache$mem_master_awcache, - icache$mem_master_awid, - icache$mem_master_awqos, - icache$mem_master_awregion, - icache$mem_master_bid, - icache$mem_master_rid, - icache$mem_master_wid, - icache$set_verbosity_verbosity; - wire [2 : 0] icache$mem_master_arprot, - icache$mem_master_arsize, - icache$mem_master_awprot, - icache$mem_master_awsize, - icache$req_f3; - wire [1 : 0] icache$mem_master_arburst, - icache$mem_master_awburst, - icache$mem_master_bresp, - icache$mem_master_rresp, - icache$req_op, - icache$req_priv; - wire icache$EN_req, - icache$EN_server_flush_request_put, - icache$EN_server_flush_response_get, - icache$EN_server_reset_request_put, - icache$EN_server_reset_response_get, - icache$EN_set_verbosity, - icache$EN_tlb_flush, - icache$RDY_server_flush_request_put, - icache$RDY_server_flush_response_get, - icache$RDY_server_reset_request_put, - icache$RDY_server_reset_response_get, - icache$exc, - icache$mem_master_arlock, - icache$mem_master_arready, - icache$mem_master_arvalid, - icache$mem_master_awlock, - icache$mem_master_awready, - icache$mem_master_awvalid, - icache$mem_master_bready, - icache$mem_master_bvalid, - icache$mem_master_rlast, - icache$mem_master_rready, - icache$mem_master_rvalid, - icache$mem_master_wlast, - icache$mem_master_wready, - icache$mem_master_wvalid, - icache$req_mstatus_MXR, - icache$req_sstatus_SUM, - icache$valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_dmem_req, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_imem_req, - CAN_FIRE_server_fence_i_request_put, - CAN_FIRE_server_fence_i_response_get, - CAN_FIRE_server_fence_request_put, - CAN_FIRE_server_fence_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_sfence_vma, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_dmem_req, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_imem_req, - WILL_FIRE_server_fence_i_request_put, - WILL_FIRE_server_fence_i_response_get, - WILL_FIRE_server_fence_request_put, - WILL_FIRE_server_fence_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_sfence_vma; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h1675; - reg [31 : 0] v__h1826; - reg [31 : 0] v__h1669; - reg [31 : 0] v__h1820; - // synopsys translate_on - - // remaining internal signals - wire NOT_cfg_verbosity_read_ULE_1___d9; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = rg_state == 2'd2 ; - assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method imem_req - assign CAN_FIRE_imem_req = 1'd1 ; - assign WILL_FIRE_imem_req = EN_imem_req ; - - // value method imem_valid - assign imem_valid = icache$valid ; - - // value method imem_is_i32_not_i16 - assign imem_is_i32_not_i16 = 1'd1 ; - - // value method imem_pc - assign imem_pc = icache$addr ; - - // value method imem_instr - assign imem_instr = icache$word64[31:0] ; - - // value method imem_exc - assign imem_exc = icache$exc ; - - // value method imem_exc_code - assign imem_exc_code = icache$exc_code ; - - // value method imem_tval - assign imem_tval = icache$addr ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = icache$mem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = icache$mem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = icache$mem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = icache$mem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = icache$mem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = icache$mem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = icache$mem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = icache$mem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = icache$mem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = icache$mem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = icache$mem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = icache$mem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = icache$mem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = icache$mem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = icache$mem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = icache$mem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = icache$mem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = icache$mem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = icache$mem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = icache$mem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = icache$mem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = icache$mem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = icache$mem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = icache$mem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = icache$mem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = icache$mem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = icache$mem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = icache$mem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = icache$mem_master_rready ; - - // action method dmem_req - assign CAN_FIRE_dmem_req = 1'd1 ; - assign WILL_FIRE_dmem_req = EN_dmem_req ; - - // value method dmem_valid - assign dmem_valid = dcache$valid ; - - // value method dmem_word64 - assign dmem_word64 = dcache$word64 ; - - // value method dmem_st_amo_val - assign dmem_st_amo_val = dcache$st_amo_val ; - - // value method dmem_exc - assign dmem_exc = dcache$exc ; - - // value method dmem_exc_code - assign dmem_exc_code = dcache$exc_code ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = dcache$mem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = dcache$mem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = dcache$mem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = dcache$mem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = dcache$mem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = dcache$mem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = dcache$mem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = dcache$mem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = dcache$mem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = dcache$mem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = dcache$mem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = dcache$mem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = dcache$mem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = dcache$mem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = dcache$mem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = dcache$mem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = dcache$mem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = dcache$mem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = dcache$mem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = dcache$mem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = dcache$mem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = dcache$mem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = dcache$mem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = dcache$mem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = dcache$mem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = dcache$mem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = dcache$mem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = dcache$mem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = dcache$mem_master_rready ; - - // action method server_fence_i_request_put - assign RDY_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_i_request_put = - EN_server_fence_i_request_put ; - - // action method server_fence_i_response_get - assign RDY_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_i_response_get = - EN_server_fence_i_response_get ; - - // action method server_fence_request_put - assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_request_put = - dcache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ; - - // action method server_fence_response_get - assign RDY_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ; - - // action method sfence_vma - assign RDY_sfence_vma = 1'd1 ; - assign CAN_FIRE_sfence_vma = 1'd1 ; - assign WILL_FIRE_sfence_vma = EN_sfence_vma ; - - // submodule dcache - mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(dcache$mem_master_arready), - .mem_master_awready(dcache$mem_master_awready), - .mem_master_bid(dcache$mem_master_bid), - .mem_master_bresp(dcache$mem_master_bresp), - .mem_master_bvalid(dcache$mem_master_bvalid), - .mem_master_rdata(dcache$mem_master_rdata), - .mem_master_rid(dcache$mem_master_rid), - .mem_master_rlast(dcache$mem_master_rlast), - .mem_master_rresp(dcache$mem_master_rresp), - .mem_master_rvalid(dcache$mem_master_rvalid), - .mem_master_wready(dcache$mem_master_wready), - .req_addr(dcache$req_addr), - .req_amo_funct7(dcache$req_amo_funct7), - .req_f3(dcache$req_f3), - .req_mstatus_MXR(dcache$req_mstatus_MXR), - .req_op(dcache$req_op), - .req_priv(dcache$req_priv), - .req_satp(dcache$req_satp), - .req_sstatus_SUM(dcache$req_sstatus_SUM), - .req_st_value(dcache$req_st_value), - .set_verbosity_verbosity(dcache$set_verbosity_verbosity), - .EN_set_verbosity(dcache$EN_set_verbosity), - .EN_server_reset_request_put(dcache$EN_server_reset_request_put), - .EN_server_reset_response_get(dcache$EN_server_reset_response_get), - .EN_req(dcache$EN_req), - .EN_server_flush_request_put(dcache$EN_server_flush_request_put), - .EN_server_flush_response_get(dcache$EN_server_flush_response_get), - .EN_tlb_flush(dcache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), - .valid(dcache$valid), - .addr(), - .word64(dcache$word64), - .st_amo_val(dcache$st_amo_val), - .exc(dcache$exc), - .exc_code(dcache$exc_code), - .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(dcache$mem_master_awvalid), - .mem_master_awid(dcache$mem_master_awid), - .mem_master_awaddr(dcache$mem_master_awaddr), - .mem_master_awlen(dcache$mem_master_awlen), - .mem_master_awsize(dcache$mem_master_awsize), - .mem_master_awburst(dcache$mem_master_awburst), - .mem_master_awlock(dcache$mem_master_awlock), - .mem_master_awcache(dcache$mem_master_awcache), - .mem_master_awprot(dcache$mem_master_awprot), - .mem_master_awqos(dcache$mem_master_awqos), - .mem_master_awregion(dcache$mem_master_awregion), - .mem_master_wvalid(dcache$mem_master_wvalid), - .mem_master_wid(dcache$mem_master_wid), - .mem_master_wdata(dcache$mem_master_wdata), - .mem_master_wstrb(dcache$mem_master_wstrb), - .mem_master_wlast(dcache$mem_master_wlast), - .mem_master_bready(dcache$mem_master_bready), - .mem_master_arvalid(dcache$mem_master_arvalid), - .mem_master_arid(dcache$mem_master_arid), - .mem_master_araddr(dcache$mem_master_araddr), - .mem_master_arlen(dcache$mem_master_arlen), - .mem_master_arsize(dcache$mem_master_arsize), - .mem_master_arburst(dcache$mem_master_arburst), - .mem_master_arlock(dcache$mem_master_arlock), - .mem_master_arcache(dcache$mem_master_arcache), - .mem_master_arprot(dcache$mem_master_arprot), - .mem_master_arqos(dcache$mem_master_arqos), - .mem_master_arregion(dcache$mem_master_arregion), - .mem_master_rready(dcache$mem_master_rready)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule icache - mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(icache$mem_master_arready), - .mem_master_awready(icache$mem_master_awready), - .mem_master_bid(icache$mem_master_bid), - .mem_master_bresp(icache$mem_master_bresp), - .mem_master_bvalid(icache$mem_master_bvalid), - .mem_master_rdata(icache$mem_master_rdata), - .mem_master_rid(icache$mem_master_rid), - .mem_master_rlast(icache$mem_master_rlast), - .mem_master_rresp(icache$mem_master_rresp), - .mem_master_rvalid(icache$mem_master_rvalid), - .mem_master_wready(icache$mem_master_wready), - .req_addr(icache$req_addr), - .req_amo_funct7(icache$req_amo_funct7), - .req_f3(icache$req_f3), - .req_mstatus_MXR(icache$req_mstatus_MXR), - .req_op(icache$req_op), - .req_priv(icache$req_priv), - .req_satp(icache$req_satp), - .req_sstatus_SUM(icache$req_sstatus_SUM), - .req_st_value(icache$req_st_value), - .set_verbosity_verbosity(icache$set_verbosity_verbosity), - .EN_set_verbosity(icache$EN_set_verbosity), - .EN_server_reset_request_put(icache$EN_server_reset_request_put), - .EN_server_reset_response_get(icache$EN_server_reset_response_get), - .EN_req(icache$EN_req), - .EN_server_flush_request_put(icache$EN_server_flush_request_put), - .EN_server_flush_response_get(icache$EN_server_flush_response_get), - .EN_tlb_flush(icache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), - .valid(icache$valid), - .addr(icache$addr), - .word64(icache$word64), - .st_amo_val(), - .exc(icache$exc), - .exc_code(icache$exc_code), - .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(icache$mem_master_awvalid), - .mem_master_awid(icache$mem_master_awid), - .mem_master_awaddr(icache$mem_master_awaddr), - .mem_master_awlen(icache$mem_master_awlen), - .mem_master_awsize(icache$mem_master_awsize), - .mem_master_awburst(icache$mem_master_awburst), - .mem_master_awlock(icache$mem_master_awlock), - .mem_master_awcache(icache$mem_master_awcache), - .mem_master_awprot(icache$mem_master_awprot), - .mem_master_awqos(icache$mem_master_awqos), - .mem_master_awregion(icache$mem_master_awregion), - .mem_master_wvalid(icache$mem_master_wvalid), - .mem_master_wid(icache$mem_master_wid), - .mem_master_wdata(icache$mem_master_wdata), - .mem_master_wstrb(icache$mem_master_wstrb), - .mem_master_wlast(icache$mem_master_wlast), - .mem_master_bready(icache$mem_master_bready), - .mem_master_arvalid(icache$mem_master_arvalid), - .mem_master_arid(icache$mem_master_arid), - .mem_master_araddr(icache$mem_master_araddr), - .mem_master_arlen(icache$mem_master_arlen), - .mem_master_arsize(icache$mem_master_arsize), - .mem_master_arburst(icache$mem_master_arburst), - .mem_master_arlock(icache$mem_master_arlock), - .mem_master_arcache(icache$mem_master_arcache), - .mem_master_arprot(icache$mem_master_arprot), - .mem_master_arqos(icache$mem_master_arqos), - .mem_master_arregion(icache$mem_master_arregion), - .mem_master_rready(icache$mem_master_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - dcache$RDY_server_reset_request_put && - icache$RDY_server_reset_request_put && - rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && - !EN_server_fence_i_request_put ; - assign MUX_rg_state$write_1__SEL_3 = - dcache$RDY_server_reset_response_get && - icache$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - rg_state == 2'd1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete) - begin - case (1'b1) // synopsys parallel_case - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1; - WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset || - WILL_FIRE_RL_rl_reset_complete ; - - // submodule dcache - assign dcache$mem_master_arready = dmem_master_arready ; - assign dcache$mem_master_awready = dmem_master_awready ; - assign dcache$mem_master_bid = dmem_master_bid ; - assign dcache$mem_master_bresp = dmem_master_bresp ; - assign dcache$mem_master_bvalid = dmem_master_bvalid ; - assign dcache$mem_master_rdata = dmem_master_rdata ; - assign dcache$mem_master_rid = dmem_master_rid ; - assign dcache$mem_master_rlast = dmem_master_rlast ; - assign dcache$mem_master_rresp = dmem_master_rresp ; - assign dcache$mem_master_rvalid = dmem_master_rvalid ; - assign dcache$mem_master_wready = dmem_master_wready ; - assign dcache$req_addr = dmem_req_addr ; - assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ; - assign dcache$req_f3 = dmem_req_f3 ; - assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ; - assign dcache$req_op = dmem_req_op ; - assign dcache$req_priv = dmem_req_priv ; - assign dcache$req_satp = dmem_req_satp ; - assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ; - assign dcache$req_st_value = dmem_req_store_value ; - assign dcache$set_verbosity_verbosity = 4'h0 ; - assign dcache$EN_set_verbosity = 1'b0 ; - assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign dcache$EN_req = EN_dmem_req ; - assign dcache$EN_server_flush_request_put = - EN_server_fence_i_request_put || EN_server_fence_request_put ; - assign dcache$EN_server_flush_response_get = - EN_server_fence_i_response_get || EN_server_fence_response_get ; - assign dcache$EN_tlb_flush = EN_sfence_vma ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule icache - assign icache$mem_master_arready = imem_master_arready ; - assign icache$mem_master_awready = imem_master_awready ; - assign icache$mem_master_bid = imem_master_bid ; - assign icache$mem_master_bresp = imem_master_bresp ; - assign icache$mem_master_bvalid = imem_master_bvalid ; - assign icache$mem_master_rdata = imem_master_rdata ; - assign icache$mem_master_rid = imem_master_rid ; - assign icache$mem_master_rlast = imem_master_rlast ; - assign icache$mem_master_rresp = imem_master_rresp ; - assign icache$mem_master_rvalid = imem_master_rvalid ; - assign icache$mem_master_wready = imem_master_wready ; - assign icache$req_addr = imem_req_addr ; - assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ; - assign icache$req_f3 = imem_req_f3 ; - assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ; - assign icache$req_op = 2'd0 ; - assign icache$req_priv = imem_req_priv ; - assign icache$req_satp = imem_req_satp ; - assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ; - assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign icache$set_verbosity_verbosity = 4'h0 ; - assign icache$EN_set_verbosity = 1'b0 ; - assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign icache$EN_req = EN_imem_req ; - assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ; - assign icache$EN_server_flush_response_get = - EN_server_fence_i_response_get ; - assign icache$EN_tlb_flush = EN_sfence_vma ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1675 = $stime; - #0; - end - v__h1669 = v__h1675 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset", v__h1669); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1826 = $stime; - #0; - end - v__h1820 = v__h1826 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset_complete", v__h1820); - end - // synopsys translate_on -endmodule // mkNear_Mem - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v deleted file mode 100644 index 32e93584..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v +++ /dev/null @@ -1,1308 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// RDY_server_request_put O 1 reg -// server_response_get O 66 reg -// RDY_server_response_get O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// server_request_put I 137 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_server_request_put I 1 -// EN_server_response_get I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - server_request_put, - EN_server_request_put, - RDY_server_request_put, - - EN_server_response_get, - server_response_get, - RDY_server_response_get, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method server_request_put - input [136 : 0] server_request_put; - input EN_server_request_put; - output RDY_server_request_put; - - // actionvalue method server_response_get - input EN_server_response_get; - output [65 : 0] server_response_get; - output RDY_server_response_get; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [65 : 0] server_response_get; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_request_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_server_response_get, - RDY_set_addr_map, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reqs - wire [136 : 0] f_reqs$D_IN, f_reqs$D_OUT; - wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_rsps - wire [65 : 0] f_rsps$D_IN, f_rsps$D_OUT; - wire f_rsps$CLR, f_rsps$DEQ, f_rsps$EMPTY_N, f_rsps$ENQ, f_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_request_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_server_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_request_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_server_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire [65 : 0] MUX_f_rsps$enq_1__VAL_1, MUX_f_rsps$enq_1__VAL_2; - wire [63 : 0] MUX_crg_time$port1__write_1__VAL_1, - MUX_crg_timecmp$port1__write_1__VAL_1; - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8676; - reg [31 : 0] v__h8808; - reg [31 : 0] v__h1471; - reg [31 : 0] v__h1868; - reg [31 : 0] v__h2065; - reg [31 : 0] v__h1714; - reg [31 : 0] v__h2442; - reg [31 : 0] v__h7890; - reg [31 : 0] v__h8258; - reg [31 : 0] v__h8368; - reg [31 : 0] v__h8475; - reg [31 : 0] v__h1465; - reg [31 : 0] v__h1708; - reg [31 : 0] v__h1862; - reg [31 : 0] v__h2059; - reg [31 : 0] v__h2436; - reg [31 : 0] v__h7884; - reg [31 : 0] v__h8252; - reg [31 : 0] v__h8362; - reg [31 : 0] v__h8469; - reg [31 : 0] v__h8670; - reg [31 : 0] v__h8802; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rsp_rdata__h2209; - wire [63 : 0] byte_addr__h1981, - mask__h2865, - mask__h5362, - new_data__h5360, - new_time__h4107, - new_time__h6632, - new_timecmp__h2834, - new_timecmp__h5331, - old_time__h6631, - rdata__h1996, - rdata__h2020, - rdata__h2026, - x__h2876, - x__h4149, - x__h5373, - x__h6674, - y__h2877, - y__h2878, - y__h5374, - y__h5375; - wire [7 : 0] SEXT_f_reqs_first__8_BIT_0_31___d132, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_7_07___d108; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method server_request_put - assign RDY_server_request_put = f_reqs$FULL_N ; - assign CAN_FIRE_server_request_put = f_reqs$FULL_N ; - assign WILL_FIRE_server_request_put = EN_server_request_put ; - - // actionvalue method server_response_get - assign server_response_get = f_rsps$D_OUT ; - assign RDY_server_response_get = f_rsps$EMPTY_N ; - assign CAN_FIRE_server_response_get = f_rsps$EMPTY_N ; - assign WILL_FIRE_server_response_get = EN_server_response_get ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reqs - FIFO2 #(.width(32'd137), .guarded(32'd1)) f_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reqs$D_IN), - .ENQ(f_reqs$ENQ), - .DEQ(f_reqs$DEQ), - .CLR(f_reqs$CLR), - .D_OUT(f_reqs$D_OUT), - .FULL_N(f_reqs$FULL_N), - .EMPTY_N(f_reqs$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_rsps - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_rsps$D_IN), - .ENQ(f_rsps$ENQ), - .DEQ(f_rsps$DEQ), - .CLR(f_rsps$CLR), - .D_OUT(f_rsps$D_OUT), - .FULL_N(f_rsps$FULL_N), - .EMPTY_N(f_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && rg_state && - !f_reset_reqs$EMPTY_N && - f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && - (byte_addr__h1981 != 64'h0 || - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - f_sw_interrupt_req$FULL_N) && - rg_state && - !f_reset_reqs$EMPTY_N && - !f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign MUX_crg_time$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h000000000000BFF8) ? - new_time__h4107 : - new_time__h6632 ; - assign MUX_crg_timecmp$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h0000000000004000) ? - new_timecmp__h2834 : - new_timecmp__h5331 ; - assign MUX_f_rsps$enq_1__VAL_1 = - { 1'd1, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - rsp_rdata__h2209 } ; - assign MUX_f_rsps$enq_1__VAL_2 = - { 1'd0, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - 64'hAAAAAAAAAAAAAAAA } ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? - MUX_crg_time$port1__write_1__VAL_1 : - 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h6631 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - MUX_crg_timecmp$port1__write_1__VAL_1 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = MUX_rg_msip$write_1__SEL_1 && f_reqs$D_OUT[8] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reqs - assign f_reqs$D_IN = server_request_put ; - assign f_reqs$ENQ = EN_server_request_put ; - assign f_reqs$DEQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_rsps - assign f_rsps$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_f_rsps$enq_1__VAL_1 : - MUX_f_rsps$enq_1__VAL_2 ; - assign f_rsps$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_process_wr_req ; - assign f_rsps$DEQ = EN_server_response_get ; - assign f_rsps$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = f_reqs$D_OUT[8] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_f_reqs_first__8_BIT_0_31___d132 = {8{f_reqs$D_OUT[0]}} ; - assign SEXT_f_reqs_first__8_BIT_1_28___d129 = {8{f_reqs$D_OUT[1]}} ; - assign SEXT_f_reqs_first__8_BIT_2_24___d125 = {8{f_reqs$D_OUT[2]}} ; - assign SEXT_f_reqs_first__8_BIT_3_21___d122 = {8{f_reqs$D_OUT[3]}} ; - assign SEXT_f_reqs_first__8_BIT_4_17___d118 = {8{f_reqs$D_OUT[4]}} ; - assign SEXT_f_reqs_first__8_BIT_5_14___d115 = {8{f_reqs$D_OUT[5]}} ; - assign SEXT_f_reqs_first__8_BIT_6_10___d111 = {8{f_reqs$D_OUT[6]}} ; - assign SEXT_f_reqs_first__8_BIT_7_07___d108 = {8{f_reqs$D_OUT[7]}} ; - assign byte_addr__h1981 = f_reqs$D_OUT[135:72] - rg_addr_base ; - assign mask__h2865 = - { SEXT_f_reqs_first__8_BIT_7_07___d108, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign mask__h5362 = - { SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'd0 } ; - assign new_data__h5360 = { f_reqs$D_OUT[39:8], 32'h0 } ; - assign new_time__h4107 = x__h4149 | y__h2877 ; - assign new_time__h6632 = x__h6674 | y__h5374 ; - assign new_timecmp__h2834 = x__h2876 | y__h2877 ; - assign new_timecmp__h5331 = x__h5373 | y__h5374 ; - assign old_time__h6631 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata__h1996 = { 63'd0, rg_msip } ; - assign rdata__h2020 = { 32'd0, crg_timecmp[63:32] } ; - assign rdata__h2026 = { 32'd0, crg_time[63:32] } ; - assign rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 = - rg_msip == f_reqs$D_OUT[8] ; - assign x__h2876 = crg_timecmp & y__h2878 ; - assign x__h4149 = old_time__h6631 & y__h2878 ; - assign x__h5373 = crg_timecmp & y__h5375 ; - assign x__h6674 = old_time__h6631 & y__h5375 ; - assign y__h2877 = f_reqs$D_OUT[71:8] & mask__h2865 ; - assign y__h2878 = - { ~SEXT_f_reqs_first__8_BIT_7_07___d108, - ~SEXT_f_reqs_first__8_BIT_6_10___d111, - ~SEXT_f_reqs_first__8_BIT_5_14___d115, - ~SEXT_f_reqs_first__8_BIT_4_17___d118, - ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign y__h5374 = new_data__h5360 & mask__h5362 ; - assign y__h5375 = - { ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'hFFFFFFFF } ; - always@(byte_addr__h1981 or - rdata__h1996 or - crg_timecmp or rdata__h2020 or crg_time or rdata__h2026) - begin - case (byte_addr__h1981) - 64'h0: rsp_rdata__h2209 = rdata__h1996; - 64'h0000000000000004: rsp_rdata__h2209 = 64'd0; - 64'h0000000000004000: rsp_rdata__h2209 = crg_timecmp; - 64'h0000000000004004: rsp_rdata__h2209 = rdata__h2020; - 64'h000000000000BFF8: rsp_rdata__h2209 = crg_time; - 64'h000000000000BFFC: rsp_rdata__h2209 = rdata__h2026; - default: rsp_rdata__h2209 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8676 = $stime; - #0; - end - v__h8670 = v__h8676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_timer_interrupt_req: %x", - v__h8670, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8808 = $stime; - #0; - end - v__h8802 = v__h8808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_sw_interrupt_req: %x", - v__h8802, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1471 = $stime; - #0; - end - v__h1465 = v__h1471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO.rl_reset", v__h1465); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1868 = $stime; - #0; - end - v__h1862 = v__h1868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_rd_req: rg_mtip = %0d", - v__h1862, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h2065 = $stime; - #0; - end - v__h2059 = v__h2065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_rd_req: unrecognized addr", - v__h2059); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rsp_rdata__h2209, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1714 = $stime; - #0; - end - v__h1708 = v__h1714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h1708, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2442 = $stime; - #0; - end - v__h2436 = v__h2442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_wr_req: rg_mtip = %0d", - v__h2436, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", f_reqs$D_OUT[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h2834); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h2834 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h4107); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h5331); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h5331 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h6632); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h7890 = $stime; - #0; - end - v__h7884 = v__h7890 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_wr_req: unrecognized addr", - v__h7884); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 64'hAAAAAAAAAAAAAAAA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h8258 = $stime; - #0; - end - v__h8252 = v__h8258 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h8252, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h8368 = $stime; - #0; - end - v__h8362 = v__h8368 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h8362, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h8475 = $stime; - #0; - end - v__h8469 = v__h8475 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h8469, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v deleted file mode 100644 index 0883c8da..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v +++ /dev/null @@ -1,2812 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO_AXI4(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h10065; - reg [31 : 0] v__h10197; - reg [31 : 0] v__h1852; - reg [31 : 0] v__h2269; - reg [31 : 0] v__h2453; - reg [31 : 0] v__h2640; - reg [31 : 0] v__h2878; - reg [31 : 0] v__h2095; - reg [31 : 0] v__h3161; - reg [31 : 0] v__h3391; - reg [31 : 0] v__h8927; - reg [31 : 0] v__h9148; - reg [31 : 0] v__h9475; - reg [31 : 0] v__h9585; - reg [31 : 0] v__h9692; - reg [31 : 0] v__h1846; - reg [31 : 0] v__h2089; - reg [31 : 0] v__h2263; - reg [31 : 0] v__h2447; - reg [31 : 0] v__h2634; - reg [31 : 0] v__h2872; - reg [31 : 0] v__h3155; - reg [31 : 0] v__h3385; - reg [31 : 0] v__h8921; - reg [31 : 0] v__h9142; - reg [31 : 0] v__h9469; - reg [31 : 0] v__h9579; - reg [31 : 0] v__h9686; - reg [31 : 0] v__h10059; - reg [31 : 0] v__h10191; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] _theResult___fst__h2566; - reg [1 : 0] _theResult___snd__h2567, v__h3517; - wire [63 : 0] byte_addr__h2405, - byte_addr__h3353, - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190, - mask__h3798, - new_time__h5056, - new_timecmp__h3767, - old_time__h7614, - rdata___1__h2562, - x__h2751, - x__h3809, - x__h5098, - y__h3810, - y__h3811; - wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153; - wire [1 : 0] rresp__h2548, v__h3357; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108, - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53, - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102, - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? new_time__h5056 : 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h7614 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - new_timecmp__h3767 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = - MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - x__h2751, - rresp__h2548, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3357 } ; - assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 = - {8{slave_xactor_f_wr_data$D_OUT[1]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174 = - {8{slave_xactor_f_wr_data$D_OUT[2]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170 = - {8{slave_xactor_f_wr_data$D_OUT[3]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167 = - {8{slave_xactor_f_wr_data$D_OUT[4]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163 = - {8{slave_xactor_f_wr_data$D_OUT[5]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160 = - {8{slave_xactor_f_wr_data$D_OUT[6]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156 = - {8{slave_xactor_f_wr_data$D_OUT[7]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153 = - {8{slave_xactor_f_wr_data$D_OUT[8]}} ; - assign byte_addr__h2405 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign byte_addr__h3353 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190 = - new_timecmp__h3767 - old_time__h7614 ; - assign mask__h3798 = - { SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - assign new_time__h5056 = x__h5098 | y__h3810 ; - assign new_timecmp__h3767 = x__h3809 | y__h3810 ; - assign old_time__h7614 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata___1__h2562 = { 63'd0, rg_msip } ; - assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 = - rg_msip == slave_xactor_f_wr_data$D_OUT[9] ; - assign rresp__h2548 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 2'b11 : - _theResult___snd__h2567 ; - assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 = - slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 = - slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 || - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - f_sw_interrupt_req$FULL_N) ; - assign v__h3357 = - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ? - 2'b11 : - v__h3517 ; - assign x__h2751 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 64'd0 : - _theResult___fst__h2566 ; - assign x__h3809 = crg_timecmp & y__h3811 ; - assign x__h5098 = old_time__h7614 & y__h3811 ; - assign y__h3810 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3798 ; - assign y__h3811 = - { ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - always@(byte_addr__h2405) - begin - case (byte_addr__h2405) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - _theResult___snd__h2567 = 2'b0; - default: _theResult___snd__h2567 = 2'b11; - endcase - end - always@(byte_addr__h2405 or rdata___1__h2562 or crg_timecmp or crg_time) - begin - case (byte_addr__h2405) - 64'h0: _theResult___fst__h2566 = rdata___1__h2562; - 64'h0000000000000004: _theResult___fst__h2566 = 64'd0; - 64'h0000000000004000, 64'h0000000000004004: - _theResult___fst__h2566 = crg_timecmp; - 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___fst__h2566 = crg_time; - default: _theResult___fst__h2566 = 64'd0; - endcase - end - always@(byte_addr__h3353) - begin - case (byte_addr__h3353) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - v__h3517 = 2'b0; - default: v__h3517 = 2'b11; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10065 = $stime; - #0; - end - v__h10059 = v__h10065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x", - v__h10059, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10197 = $stime; - #0; - end - v__h10191 = v__h10197 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x", - v__h10191, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1852 = $stime; - #0; - end - v__h1846 = v__h1852 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1846); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2269 = $stime; - #0; - end - v__h2263 = v__h2269 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", - v__h2263, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - begin - v__h2453 = $stime; - #0; - end - v__h2447 = v__h2453 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2447); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - begin - v__h2640 = $stime; - #0; - end - v__h2634 = v__h2640 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2634); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2878 = $stime; - #0; - end - v__h2872 = v__h2878 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2872); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", x__h2751); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rresp__h2548); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2095 = $stime; - #0; - end - v__h2089 = v__h2095 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h2089, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h3161 = $stime; - #0; - end - v__h3155 = v__h3161 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", - v__h3155, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - begin - v__h3391 = $stime; - #0; - end - v__h3385 = v__h3391 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h3385); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - begin - v__h8927 = $stime; - #0; - end - v__h8921 = v__h8927 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h8921); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h9148 = $stime; - #0; - end - v__h9142 = v__h9148 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9142); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", v__h3357); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h9475 = $stime; - #0; - end - v__h9469 = v__h9475 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9469, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h9585 = $stime; - #0; - end - v__h9579 = v__h9585 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9579, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h9692 = $stime; - #0; - end - v__h9686 = v__h9692 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9686, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO_AXI4 - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v deleted file mode 100644 index f74de61e..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v +++ /dev/null @@ -1,26991 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_show_PLIC_state O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// v_targets_0_m_eip O 1 -// v_targets_1_m_eip O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// v_sources_0_m_interrupt_req_set_not_clear I 1 -// v_sources_1_m_interrupt_req_set_not_clear I 1 -// v_sources_2_m_interrupt_req_set_not_clear I 1 -// v_sources_3_m_interrupt_req_set_not_clear I 1 -// v_sources_4_m_interrupt_req_set_not_clear I 1 -// v_sources_5_m_interrupt_req_set_not_clear I 1 -// v_sources_6_m_interrupt_req_set_not_clear I 1 -// v_sources_7_m_interrupt_req_set_not_clear I 1 -// v_sources_8_m_interrupt_req_set_not_clear I 1 -// v_sources_9_m_interrupt_req_set_not_clear I 1 -// v_sources_10_m_interrupt_req_set_not_clear I 1 -// v_sources_11_m_interrupt_req_set_not_clear I 1 -// v_sources_12_m_interrupt_req_set_not_clear I 1 -// v_sources_13_m_interrupt_req_set_not_clear I 1 -// v_sources_14_m_interrupt_req_set_not_clear I 1 -// v_sources_15_m_interrupt_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_show_PLIC_state I 1 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkPLIC_16_2_7(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_show_PLIC_state, - RDY_show_PLIC_state, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - v_sources_0_m_interrupt_req_set_not_clear, - - v_sources_1_m_interrupt_req_set_not_clear, - - v_sources_2_m_interrupt_req_set_not_clear, - - v_sources_3_m_interrupt_req_set_not_clear, - - v_sources_4_m_interrupt_req_set_not_clear, - - v_sources_5_m_interrupt_req_set_not_clear, - - v_sources_6_m_interrupt_req_set_not_clear, - - v_sources_7_m_interrupt_req_set_not_clear, - - v_sources_8_m_interrupt_req_set_not_clear, - - v_sources_9_m_interrupt_req_set_not_clear, - - v_sources_10_m_interrupt_req_set_not_clear, - - v_sources_11_m_interrupt_req_set_not_clear, - - v_sources_12_m_interrupt_req_set_not_clear, - - v_sources_13_m_interrupt_req_set_not_clear, - - v_sources_14_m_interrupt_req_set_not_clear, - - v_sources_15_m_interrupt_req_set_not_clear, - - v_targets_0_m_eip, - - v_targets_1_m_eip); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method show_PLIC_state - input EN_show_PLIC_state; - output RDY_show_PLIC_state; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // action method v_sources_0_m_interrupt_req - input v_sources_0_m_interrupt_req_set_not_clear; - - // action method v_sources_1_m_interrupt_req - input v_sources_1_m_interrupt_req_set_not_clear; - - // action method v_sources_2_m_interrupt_req - input v_sources_2_m_interrupt_req_set_not_clear; - - // action method v_sources_3_m_interrupt_req - input v_sources_3_m_interrupt_req_set_not_clear; - - // action method v_sources_4_m_interrupt_req - input v_sources_4_m_interrupt_req_set_not_clear; - - // action method v_sources_5_m_interrupt_req - input v_sources_5_m_interrupt_req_set_not_clear; - - // action method v_sources_6_m_interrupt_req - input v_sources_6_m_interrupt_req_set_not_clear; - - // action method v_sources_7_m_interrupt_req - input v_sources_7_m_interrupt_req_set_not_clear; - - // action method v_sources_8_m_interrupt_req - input v_sources_8_m_interrupt_req_set_not_clear; - - // action method v_sources_9_m_interrupt_req - input v_sources_9_m_interrupt_req_set_not_clear; - - // action method v_sources_10_m_interrupt_req - input v_sources_10_m_interrupt_req_set_not_clear; - - // action method v_sources_11_m_interrupt_req - input v_sources_11_m_interrupt_req_set_not_clear; - - // action method v_sources_12_m_interrupt_req - input v_sources_12_m_interrupt_req_set_not_clear; - - // action method v_sources_13_m_interrupt_req - input v_sources_13_m_interrupt_req_set_not_clear; - - // action method v_sources_14_m_interrupt_req - input v_sources_14_m_interrupt_req_set_not_clear; - - // action method v_sources_15_m_interrupt_req - input v_sources_15_m_interrupt_req_set_not_clear; - - // value method v_targets_0_m_eip - output v_targets_0_m_eip; - - // value method v_targets_1_m_eip - output v_targets_1_m_eip; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_verbosity, - RDY_show_PLIC_state, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - v_targets_0_m_eip, - v_targets_1_m_eip; - - // register m_cfg_verbosity - reg [3 : 0] m_cfg_verbosity; - wire [3 : 0] m_cfg_verbosity$D_IN; - wire m_cfg_verbosity$EN; - - // register m_rg_addr_base - reg [63 : 0] m_rg_addr_base; - wire [63 : 0] m_rg_addr_base$D_IN; - wire m_rg_addr_base$EN; - - // register m_rg_addr_lim - reg [63 : 0] m_rg_addr_lim; - wire [63 : 0] m_rg_addr_lim$D_IN; - wire m_rg_addr_lim$EN; - - // register m_vrg_servicing_source_0 - reg [4 : 0] m_vrg_servicing_source_0; - wire [4 : 0] m_vrg_servicing_source_0$D_IN; - wire m_vrg_servicing_source_0$EN; - - // register m_vrg_servicing_source_1 - reg [4 : 0] m_vrg_servicing_source_1; - wire [4 : 0] m_vrg_servicing_source_1$D_IN; - wire m_vrg_servicing_source_1$EN; - - // register m_vrg_source_busy_0 - reg m_vrg_source_busy_0; - wire m_vrg_source_busy_0$D_IN, m_vrg_source_busy_0$EN; - - // register m_vrg_source_busy_1 - reg m_vrg_source_busy_1; - wire m_vrg_source_busy_1$D_IN, m_vrg_source_busy_1$EN; - - // register m_vrg_source_busy_10 - reg m_vrg_source_busy_10; - wire m_vrg_source_busy_10$D_IN, m_vrg_source_busy_10$EN; - - // register m_vrg_source_busy_11 - reg m_vrg_source_busy_11; - wire m_vrg_source_busy_11$D_IN, m_vrg_source_busy_11$EN; - - // register m_vrg_source_busy_12 - reg m_vrg_source_busy_12; - wire m_vrg_source_busy_12$D_IN, m_vrg_source_busy_12$EN; - - // register m_vrg_source_busy_13 - reg m_vrg_source_busy_13; - wire m_vrg_source_busy_13$D_IN, m_vrg_source_busy_13$EN; - - // register m_vrg_source_busy_14 - reg m_vrg_source_busy_14; - wire m_vrg_source_busy_14$D_IN, m_vrg_source_busy_14$EN; - - // register m_vrg_source_busy_15 - reg m_vrg_source_busy_15; - wire m_vrg_source_busy_15$D_IN, m_vrg_source_busy_15$EN; - - // register m_vrg_source_busy_16 - reg m_vrg_source_busy_16; - wire m_vrg_source_busy_16$D_IN, m_vrg_source_busy_16$EN; - - // register m_vrg_source_busy_2 - reg m_vrg_source_busy_2; - wire m_vrg_source_busy_2$D_IN, m_vrg_source_busy_2$EN; - - // register m_vrg_source_busy_3 - reg m_vrg_source_busy_3; - wire m_vrg_source_busy_3$D_IN, m_vrg_source_busy_3$EN; - - // register m_vrg_source_busy_4 - reg m_vrg_source_busy_4; - wire m_vrg_source_busy_4$D_IN, m_vrg_source_busy_4$EN; - - // register m_vrg_source_busy_5 - reg m_vrg_source_busy_5; - wire m_vrg_source_busy_5$D_IN, m_vrg_source_busy_5$EN; - - // register m_vrg_source_busy_6 - reg m_vrg_source_busy_6; - wire m_vrg_source_busy_6$D_IN, m_vrg_source_busy_6$EN; - - // register m_vrg_source_busy_7 - reg m_vrg_source_busy_7; - wire m_vrg_source_busy_7$D_IN, m_vrg_source_busy_7$EN; - - // register m_vrg_source_busy_8 - reg m_vrg_source_busy_8; - wire m_vrg_source_busy_8$D_IN, m_vrg_source_busy_8$EN; - - // register m_vrg_source_busy_9 - reg m_vrg_source_busy_9; - wire m_vrg_source_busy_9$D_IN, m_vrg_source_busy_9$EN; - - // register m_vrg_source_ip_0 - reg m_vrg_source_ip_0; - wire m_vrg_source_ip_0$D_IN, m_vrg_source_ip_0$EN; - - // register m_vrg_source_ip_1 - reg m_vrg_source_ip_1; - wire m_vrg_source_ip_1$D_IN, m_vrg_source_ip_1$EN; - - // register m_vrg_source_ip_10 - reg m_vrg_source_ip_10; - wire m_vrg_source_ip_10$D_IN, m_vrg_source_ip_10$EN; - - // register m_vrg_source_ip_11 - reg m_vrg_source_ip_11; - wire m_vrg_source_ip_11$D_IN, m_vrg_source_ip_11$EN; - - // register m_vrg_source_ip_12 - reg m_vrg_source_ip_12; - wire m_vrg_source_ip_12$D_IN, m_vrg_source_ip_12$EN; - - // register m_vrg_source_ip_13 - reg m_vrg_source_ip_13; - wire m_vrg_source_ip_13$D_IN, m_vrg_source_ip_13$EN; - - // register m_vrg_source_ip_14 - reg m_vrg_source_ip_14; - wire m_vrg_source_ip_14$D_IN, m_vrg_source_ip_14$EN; - - // register m_vrg_source_ip_15 - reg m_vrg_source_ip_15; - wire m_vrg_source_ip_15$D_IN, m_vrg_source_ip_15$EN; - - // register m_vrg_source_ip_16 - reg m_vrg_source_ip_16; - wire m_vrg_source_ip_16$D_IN, m_vrg_source_ip_16$EN; - - // register m_vrg_source_ip_2 - reg m_vrg_source_ip_2; - wire m_vrg_source_ip_2$D_IN, m_vrg_source_ip_2$EN; - - // register m_vrg_source_ip_3 - reg m_vrg_source_ip_3; - wire m_vrg_source_ip_3$D_IN, m_vrg_source_ip_3$EN; - - // register m_vrg_source_ip_4 - reg m_vrg_source_ip_4; - wire m_vrg_source_ip_4$D_IN, m_vrg_source_ip_4$EN; - - // register m_vrg_source_ip_5 - reg m_vrg_source_ip_5; - wire m_vrg_source_ip_5$D_IN, m_vrg_source_ip_5$EN; - - // register m_vrg_source_ip_6 - reg m_vrg_source_ip_6; - wire m_vrg_source_ip_6$D_IN, m_vrg_source_ip_6$EN; - - // register m_vrg_source_ip_7 - reg m_vrg_source_ip_7; - wire m_vrg_source_ip_7$D_IN, m_vrg_source_ip_7$EN; - - // register m_vrg_source_ip_8 - reg m_vrg_source_ip_8; - wire m_vrg_source_ip_8$D_IN, m_vrg_source_ip_8$EN; - - // register m_vrg_source_ip_9 - reg m_vrg_source_ip_9; - wire m_vrg_source_ip_9$D_IN, m_vrg_source_ip_9$EN; - - // register m_vrg_source_prio_0 - reg [2 : 0] m_vrg_source_prio_0; - wire [2 : 0] m_vrg_source_prio_0$D_IN; - wire m_vrg_source_prio_0$EN; - - // register m_vrg_source_prio_1 - reg [2 : 0] m_vrg_source_prio_1; - wire [2 : 0] m_vrg_source_prio_1$D_IN; - wire m_vrg_source_prio_1$EN; - - // register m_vrg_source_prio_10 - reg [2 : 0] m_vrg_source_prio_10; - wire [2 : 0] m_vrg_source_prio_10$D_IN; - wire m_vrg_source_prio_10$EN; - - // register m_vrg_source_prio_11 - reg [2 : 0] m_vrg_source_prio_11; - wire [2 : 0] m_vrg_source_prio_11$D_IN; - wire m_vrg_source_prio_11$EN; - - // register m_vrg_source_prio_12 - reg [2 : 0] m_vrg_source_prio_12; - wire [2 : 0] m_vrg_source_prio_12$D_IN; - wire m_vrg_source_prio_12$EN; - - // register m_vrg_source_prio_13 - reg [2 : 0] m_vrg_source_prio_13; - wire [2 : 0] m_vrg_source_prio_13$D_IN; - wire m_vrg_source_prio_13$EN; - - // register m_vrg_source_prio_14 - reg [2 : 0] m_vrg_source_prio_14; - wire [2 : 0] m_vrg_source_prio_14$D_IN; - wire m_vrg_source_prio_14$EN; - - // register m_vrg_source_prio_15 - reg [2 : 0] m_vrg_source_prio_15; - wire [2 : 0] m_vrg_source_prio_15$D_IN; - wire m_vrg_source_prio_15$EN; - - // register m_vrg_source_prio_16 - reg [2 : 0] m_vrg_source_prio_16; - wire [2 : 0] m_vrg_source_prio_16$D_IN; - wire m_vrg_source_prio_16$EN; - - // register m_vrg_source_prio_2 - reg [2 : 0] m_vrg_source_prio_2; - wire [2 : 0] m_vrg_source_prio_2$D_IN; - wire m_vrg_source_prio_2$EN; - - // register m_vrg_source_prio_3 - reg [2 : 0] m_vrg_source_prio_3; - wire [2 : 0] m_vrg_source_prio_3$D_IN; - wire m_vrg_source_prio_3$EN; - - // register m_vrg_source_prio_4 - reg [2 : 0] m_vrg_source_prio_4; - wire [2 : 0] m_vrg_source_prio_4$D_IN; - wire m_vrg_source_prio_4$EN; - - // register m_vrg_source_prio_5 - reg [2 : 0] m_vrg_source_prio_5; - wire [2 : 0] m_vrg_source_prio_5$D_IN; - wire m_vrg_source_prio_5$EN; - - // register m_vrg_source_prio_6 - reg [2 : 0] m_vrg_source_prio_6; - wire [2 : 0] m_vrg_source_prio_6$D_IN; - wire m_vrg_source_prio_6$EN; - - // register m_vrg_source_prio_7 - reg [2 : 0] m_vrg_source_prio_7; - wire [2 : 0] m_vrg_source_prio_7$D_IN; - wire m_vrg_source_prio_7$EN; - - // register m_vrg_source_prio_8 - reg [2 : 0] m_vrg_source_prio_8; - wire [2 : 0] m_vrg_source_prio_8$D_IN; - wire m_vrg_source_prio_8$EN; - - // register m_vrg_source_prio_9 - reg [2 : 0] m_vrg_source_prio_9; - wire [2 : 0] m_vrg_source_prio_9$D_IN; - wire m_vrg_source_prio_9$EN; - - // register m_vrg_target_threshold_0 - reg [2 : 0] m_vrg_target_threshold_0; - wire [2 : 0] m_vrg_target_threshold_0$D_IN; - wire m_vrg_target_threshold_0$EN; - - // register m_vrg_target_threshold_1 - reg [2 : 0] m_vrg_target_threshold_1; - wire [2 : 0] m_vrg_target_threshold_1$D_IN; - wire m_vrg_target_threshold_1$EN; - - // register m_vvrg_ie_0_0 - reg m_vvrg_ie_0_0; - wire m_vvrg_ie_0_0$D_IN, m_vvrg_ie_0_0$EN; - - // register m_vvrg_ie_0_1 - reg m_vvrg_ie_0_1; - wire m_vvrg_ie_0_1$D_IN, m_vvrg_ie_0_1$EN; - - // register m_vvrg_ie_0_10 - reg m_vvrg_ie_0_10; - wire m_vvrg_ie_0_10$D_IN, m_vvrg_ie_0_10$EN; - - // register m_vvrg_ie_0_11 - reg m_vvrg_ie_0_11; - wire m_vvrg_ie_0_11$D_IN, m_vvrg_ie_0_11$EN; - - // register m_vvrg_ie_0_12 - reg m_vvrg_ie_0_12; - wire m_vvrg_ie_0_12$D_IN, m_vvrg_ie_0_12$EN; - - // register m_vvrg_ie_0_13 - reg m_vvrg_ie_0_13; - wire m_vvrg_ie_0_13$D_IN, m_vvrg_ie_0_13$EN; - - // register m_vvrg_ie_0_14 - reg m_vvrg_ie_0_14; - wire m_vvrg_ie_0_14$D_IN, m_vvrg_ie_0_14$EN; - - // register m_vvrg_ie_0_15 - reg m_vvrg_ie_0_15; - wire m_vvrg_ie_0_15$D_IN, m_vvrg_ie_0_15$EN; - - // register m_vvrg_ie_0_16 - reg m_vvrg_ie_0_16; - wire m_vvrg_ie_0_16$D_IN, m_vvrg_ie_0_16$EN; - - // register m_vvrg_ie_0_2 - reg m_vvrg_ie_0_2; - wire m_vvrg_ie_0_2$D_IN, m_vvrg_ie_0_2$EN; - - // register m_vvrg_ie_0_3 - reg m_vvrg_ie_0_3; - wire m_vvrg_ie_0_3$D_IN, m_vvrg_ie_0_3$EN; - - // register m_vvrg_ie_0_4 - reg m_vvrg_ie_0_4; - wire m_vvrg_ie_0_4$D_IN, m_vvrg_ie_0_4$EN; - - // register m_vvrg_ie_0_5 - reg m_vvrg_ie_0_5; - wire m_vvrg_ie_0_5$D_IN, m_vvrg_ie_0_5$EN; - - // register m_vvrg_ie_0_6 - reg m_vvrg_ie_0_6; - wire m_vvrg_ie_0_6$D_IN, m_vvrg_ie_0_6$EN; - - // register m_vvrg_ie_0_7 - reg m_vvrg_ie_0_7; - wire m_vvrg_ie_0_7$D_IN, m_vvrg_ie_0_7$EN; - - // register m_vvrg_ie_0_8 - reg m_vvrg_ie_0_8; - wire m_vvrg_ie_0_8$D_IN, m_vvrg_ie_0_8$EN; - - // register m_vvrg_ie_0_9 - reg m_vvrg_ie_0_9; - wire m_vvrg_ie_0_9$D_IN, m_vvrg_ie_0_9$EN; - - // register m_vvrg_ie_1_0 - reg m_vvrg_ie_1_0; - wire m_vvrg_ie_1_0$D_IN, m_vvrg_ie_1_0$EN; - - // register m_vvrg_ie_1_1 - reg m_vvrg_ie_1_1; - wire m_vvrg_ie_1_1$D_IN, m_vvrg_ie_1_1$EN; - - // register m_vvrg_ie_1_10 - reg m_vvrg_ie_1_10; - wire m_vvrg_ie_1_10$D_IN, m_vvrg_ie_1_10$EN; - - // register m_vvrg_ie_1_11 - reg m_vvrg_ie_1_11; - wire m_vvrg_ie_1_11$D_IN, m_vvrg_ie_1_11$EN; - - // register m_vvrg_ie_1_12 - reg m_vvrg_ie_1_12; - wire m_vvrg_ie_1_12$D_IN, m_vvrg_ie_1_12$EN; - - // register m_vvrg_ie_1_13 - reg m_vvrg_ie_1_13; - wire m_vvrg_ie_1_13$D_IN, m_vvrg_ie_1_13$EN; - - // register m_vvrg_ie_1_14 - reg m_vvrg_ie_1_14; - wire m_vvrg_ie_1_14$D_IN, m_vvrg_ie_1_14$EN; - - // register m_vvrg_ie_1_15 - reg m_vvrg_ie_1_15; - wire m_vvrg_ie_1_15$D_IN, m_vvrg_ie_1_15$EN; - - // register m_vvrg_ie_1_16 - reg m_vvrg_ie_1_16; - wire m_vvrg_ie_1_16$D_IN, m_vvrg_ie_1_16$EN; - - // register m_vvrg_ie_1_2 - reg m_vvrg_ie_1_2; - wire m_vvrg_ie_1_2$D_IN, m_vvrg_ie_1_2$EN; - - // register m_vvrg_ie_1_3 - reg m_vvrg_ie_1_3; - wire m_vvrg_ie_1_3$D_IN, m_vvrg_ie_1_3$EN; - - // register m_vvrg_ie_1_4 - reg m_vvrg_ie_1_4; - wire m_vvrg_ie_1_4$D_IN, m_vvrg_ie_1_4$EN; - - // register m_vvrg_ie_1_5 - reg m_vvrg_ie_1_5; - wire m_vvrg_ie_1_5$D_IN, m_vvrg_ie_1_5$EN; - - // register m_vvrg_ie_1_6 - reg m_vvrg_ie_1_6; - wire m_vvrg_ie_1_6$D_IN, m_vvrg_ie_1_6$EN; - - // register m_vvrg_ie_1_7 - reg m_vvrg_ie_1_7; - wire m_vvrg_ie_1_7$D_IN, m_vvrg_ie_1_7$EN; - - // register m_vvrg_ie_1_8 - reg m_vvrg_ie_1_8; - wire m_vvrg_ie_1_8$D_IN, m_vvrg_ie_1_8$EN; - - // register m_vvrg_ie_1_9 - reg m_vvrg_ie_1_9; - wire m_vvrg_ie_1_9$D_IN, m_vvrg_ie_1_9$EN; - - // ports of submodule m_f_reset_reqs - wire m_f_reset_reqs$CLR, - m_f_reset_reqs$DEQ, - m_f_reset_reqs$EMPTY_N, - m_f_reset_reqs$ENQ, - m_f_reset_reqs$FULL_N; - - // ports of submodule m_f_reset_rsps - wire m_f_reset_rsps$CLR, - m_f_reset_rsps$DEQ, - m_f_reset_rsps$EMPTY_N, - m_f_reset_rsps$ENQ, - m_f_reset_rsps$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_addr - wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT; - wire m_slave_xactor_f_rd_addr$CLR, - m_slave_xactor_f_rd_addr$DEQ, - m_slave_xactor_f_rd_addr$EMPTY_N, - m_slave_xactor_f_rd_addr$ENQ, - m_slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_data - wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT; - wire m_slave_xactor_f_rd_data$CLR, - m_slave_xactor_f_rd_data$DEQ, - m_slave_xactor_f_rd_data$EMPTY_N, - m_slave_xactor_f_rd_data$ENQ, - m_slave_xactor_f_rd_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_addr - wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT; - wire m_slave_xactor_f_wr_addr$CLR, - m_slave_xactor_f_wr_addr$DEQ, - m_slave_xactor_f_wr_addr$EMPTY_N, - m_slave_xactor_f_wr_addr$ENQ, - m_slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; - wire m_slave_xactor_f_wr_data$CLR, - m_slave_xactor_f_wr_data$DEQ, - m_slave_xactor_f_wr_data$EMPTY_N, - m_slave_xactor_f_wr_data$ENQ, - m_slave_xactor_f_wr_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_resp - wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT; - wire m_slave_xactor_f_wr_resp$CLR, - m_slave_xactor_f_wr_resp$DEQ, - m_slave_xactor_f_wr_resp$EMPTY_N, - m_slave_xactor_f_wr_resp$ENQ, - m_slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_process_rd_req, - CAN_FIRE_RL_m_rl_process_wr_req, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_verbosity, - CAN_FIRE_show_PLIC_state, - CAN_FIRE_v_sources_0_m_interrupt_req, - CAN_FIRE_v_sources_10_m_interrupt_req, - CAN_FIRE_v_sources_11_m_interrupt_req, - CAN_FIRE_v_sources_12_m_interrupt_req, - CAN_FIRE_v_sources_13_m_interrupt_req, - CAN_FIRE_v_sources_14_m_interrupt_req, - CAN_FIRE_v_sources_15_m_interrupt_req, - CAN_FIRE_v_sources_1_m_interrupt_req, - CAN_FIRE_v_sources_2_m_interrupt_req, - CAN_FIRE_v_sources_3_m_interrupt_req, - CAN_FIRE_v_sources_4_m_interrupt_req, - CAN_FIRE_v_sources_5_m_interrupt_req, - CAN_FIRE_v_sources_6_m_interrupt_req, - CAN_FIRE_v_sources_7_m_interrupt_req, - CAN_FIRE_v_sources_8_m_interrupt_req, - CAN_FIRE_v_sources_9_m_interrupt_req, - WILL_FIRE_RL_m_rl_process_rd_req, - WILL_FIRE_RL_m_rl_process_wr_req, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_verbosity, - WILL_FIRE_show_PLIC_state, - WILL_FIRE_v_sources_0_m_interrupt_req, - WILL_FIRE_v_sources_10_m_interrupt_req, - WILL_FIRE_v_sources_11_m_interrupt_req, - WILL_FIRE_v_sources_12_m_interrupt_req, - WILL_FIRE_v_sources_13_m_interrupt_req, - WILL_FIRE_v_sources_14_m_interrupt_req, - WILL_FIRE_v_sources_15_m_interrupt_req, - WILL_FIRE_v_sources_1_m_interrupt_req, - WILL_FIRE_v_sources_2_m_interrupt_req, - WILL_FIRE_v_sources_3_m_interrupt_req, - WILL_FIRE_v_sources_4_m_interrupt_req, - WILL_FIRE_v_sources_5_m_interrupt_req, - WILL_FIRE_v_sources_6_m_interrupt_req, - WILL_FIRE_v_sources_7_m_interrupt_req, - WILL_FIRE_v_sources_8_m_interrupt_req, - WILL_FIRE_v_sources_9_m_interrupt_req; - - // inputs to muxes for submodule ports - wire MUX_m_vrg_servicing_source_0$write_1__SEL_1, - MUX_m_vrg_servicing_source_1$write_1__SEL_1, - MUX_m_vrg_source_busy_0$write_1__SEL_2, - MUX_m_vrg_source_busy_1$write_1__SEL_1, - MUX_m_vrg_source_busy_1$write_1__SEL_2, - MUX_m_vrg_source_busy_10$write_1__SEL_1, - MUX_m_vrg_source_busy_10$write_1__SEL_2, - MUX_m_vrg_source_busy_11$write_1__SEL_1, - MUX_m_vrg_source_busy_11$write_1__SEL_2, - MUX_m_vrg_source_busy_12$write_1__SEL_1, - MUX_m_vrg_source_busy_12$write_1__SEL_2, - MUX_m_vrg_source_busy_13$write_1__SEL_1, - MUX_m_vrg_source_busy_13$write_1__SEL_2, - MUX_m_vrg_source_busy_14$write_1__SEL_1, - MUX_m_vrg_source_busy_14$write_1__SEL_2, - MUX_m_vrg_source_busy_15$write_1__SEL_1, - MUX_m_vrg_source_busy_15$write_1__SEL_2, - MUX_m_vrg_source_busy_16$write_1__SEL_1, - MUX_m_vrg_source_busy_16$write_1__SEL_2, - MUX_m_vrg_source_busy_2$write_1__SEL_1, - MUX_m_vrg_source_busy_2$write_1__SEL_2, - MUX_m_vrg_source_busy_3$write_1__SEL_1, - MUX_m_vrg_source_busy_3$write_1__SEL_2, - MUX_m_vrg_source_busy_4$write_1__SEL_1, - MUX_m_vrg_source_busy_4$write_1__SEL_2, - MUX_m_vrg_source_busy_5$write_1__SEL_1, - MUX_m_vrg_source_busy_5$write_1__SEL_2, - MUX_m_vrg_source_busy_6$write_1__SEL_1, - MUX_m_vrg_source_busy_6$write_1__SEL_2, - MUX_m_vrg_source_busy_7$write_1__SEL_1, - MUX_m_vrg_source_busy_7$write_1__SEL_2, - MUX_m_vrg_source_busy_8$write_1__SEL_1, - MUX_m_vrg_source_busy_8$write_1__SEL_2, - MUX_m_vrg_source_busy_9$write_1__SEL_1, - MUX_m_vrg_source_busy_9$write_1__SEL_2, - MUX_m_vrg_source_prio_0$write_1__SEL_1, - MUX_m_vrg_source_prio_1$write_1__SEL_1, - MUX_m_vrg_source_prio_10$write_1__SEL_1, - MUX_m_vrg_source_prio_11$write_1__SEL_1, - MUX_m_vrg_source_prio_12$write_1__SEL_1, - MUX_m_vrg_source_prio_13$write_1__SEL_1, - MUX_m_vrg_source_prio_14$write_1__SEL_1, - MUX_m_vrg_source_prio_15$write_1__SEL_1, - MUX_m_vrg_source_prio_16$write_1__SEL_1, - MUX_m_vrg_source_prio_2$write_1__SEL_1, - MUX_m_vrg_source_prio_3$write_1__SEL_1, - MUX_m_vrg_source_prio_4$write_1__SEL_1, - MUX_m_vrg_source_prio_5$write_1__SEL_1, - MUX_m_vrg_source_prio_6$write_1__SEL_1, - MUX_m_vrg_source_prio_7$write_1__SEL_1, - MUX_m_vrg_source_prio_8$write_1__SEL_1, - MUX_m_vrg_source_prio_9$write_1__SEL_1, - MUX_m_vrg_target_threshold_0$write_1__SEL_1, - MUX_m_vrg_target_threshold_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__VAL_1, - MUX_m_vvrg_ie_0_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_1$write_1__VAL_1, - MUX_m_vvrg_ie_0_10$write_1__SEL_1, - MUX_m_vvrg_ie_0_10$write_1__VAL_1, - MUX_m_vvrg_ie_0_11$write_1__SEL_1, - MUX_m_vvrg_ie_0_11$write_1__VAL_1, - MUX_m_vvrg_ie_0_12$write_1__SEL_1, - MUX_m_vvrg_ie_0_12$write_1__VAL_1, - MUX_m_vvrg_ie_0_13$write_1__SEL_1, - MUX_m_vvrg_ie_0_13$write_1__VAL_1, - MUX_m_vvrg_ie_0_14$write_1__SEL_1, - MUX_m_vvrg_ie_0_14$write_1__VAL_1, - MUX_m_vvrg_ie_0_15$write_1__SEL_1, - MUX_m_vvrg_ie_0_15$write_1__VAL_1, - MUX_m_vvrg_ie_0_16$write_1__SEL_1, - MUX_m_vvrg_ie_0_16$write_1__VAL_1, - MUX_m_vvrg_ie_0_2$write_1__SEL_1, - MUX_m_vvrg_ie_0_2$write_1__VAL_1, - MUX_m_vvrg_ie_0_3$write_1__SEL_1, - MUX_m_vvrg_ie_0_3$write_1__VAL_1, - MUX_m_vvrg_ie_0_4$write_1__SEL_1, - MUX_m_vvrg_ie_0_4$write_1__VAL_1, - MUX_m_vvrg_ie_0_5$write_1__SEL_1, - MUX_m_vvrg_ie_0_5$write_1__VAL_1, - MUX_m_vvrg_ie_0_6$write_1__SEL_1, - MUX_m_vvrg_ie_0_6$write_1__VAL_1, - MUX_m_vvrg_ie_0_7$write_1__SEL_1, - MUX_m_vvrg_ie_0_7$write_1__VAL_1, - MUX_m_vvrg_ie_0_8$write_1__SEL_1, - MUX_m_vvrg_ie_0_8$write_1__VAL_1, - MUX_m_vvrg_ie_0_9$write_1__SEL_1, - MUX_m_vvrg_ie_0_9$write_1__VAL_1, - MUX_m_vvrg_ie_1_0$write_1__SEL_1, - MUX_m_vvrg_ie_1_0$write_1__VAL_1, - MUX_m_vvrg_ie_1_1$write_1__SEL_1, - MUX_m_vvrg_ie_1_1$write_1__VAL_1, - MUX_m_vvrg_ie_1_10$write_1__SEL_1, - MUX_m_vvrg_ie_1_10$write_1__VAL_1, - MUX_m_vvrg_ie_1_11$write_1__SEL_1, - MUX_m_vvrg_ie_1_11$write_1__VAL_1, - MUX_m_vvrg_ie_1_12$write_1__SEL_1, - MUX_m_vvrg_ie_1_12$write_1__VAL_1, - MUX_m_vvrg_ie_1_13$write_1__SEL_1, - MUX_m_vvrg_ie_1_13$write_1__VAL_1, - MUX_m_vvrg_ie_1_14$write_1__SEL_1, - MUX_m_vvrg_ie_1_14$write_1__VAL_1, - MUX_m_vvrg_ie_1_15$write_1__SEL_1, - MUX_m_vvrg_ie_1_15$write_1__VAL_1, - MUX_m_vvrg_ie_1_16$write_1__SEL_1, - MUX_m_vvrg_ie_1_16$write_1__VAL_1, - MUX_m_vvrg_ie_1_2$write_1__SEL_1, - MUX_m_vvrg_ie_1_2$write_1__VAL_1, - MUX_m_vvrg_ie_1_3$write_1__SEL_1, - MUX_m_vvrg_ie_1_3$write_1__VAL_1, - MUX_m_vvrg_ie_1_4$write_1__SEL_1, - MUX_m_vvrg_ie_1_4$write_1__VAL_1, - MUX_m_vvrg_ie_1_5$write_1__SEL_1, - MUX_m_vvrg_ie_1_5$write_1__VAL_1, - MUX_m_vvrg_ie_1_6$write_1__SEL_1, - MUX_m_vvrg_ie_1_6$write_1__VAL_1, - MUX_m_vvrg_ie_1_7$write_1__SEL_1, - MUX_m_vvrg_ie_1_7$write_1__VAL_1, - MUX_m_vvrg_ie_1_8$write_1__SEL_1, - MUX_m_vvrg_ie_1_8$write_1__VAL_1, - MUX_m_vvrg_ie_1_9$write_1__SEL_1, - MUX_m_vvrg_ie_1_9$write_1__VAL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h75676; - reg [31 : 0] v__h75874; - reg [31 : 0] v__h76072; - reg [31 : 0] v__h76270; - reg [31 : 0] v__h76468; - reg [31 : 0] v__h76666; - reg [31 : 0] v__h76864; - reg [31 : 0] v__h77062; - reg [31 : 0] v__h77260; - reg [31 : 0] v__h77458; - reg [31 : 0] v__h77656; - reg [31 : 0] v__h77854; - reg [31 : 0] v__h78052; - reg [31 : 0] v__h78250; - reg [31 : 0] v__h78448; - reg [31 : 0] v__h78646; - reg [31 : 0] v__h6144; - reg [31 : 0] v__h13080; - reg [31 : 0] v__h13265; - reg [31 : 0] v__h13463; - reg [31 : 0] v__h13713; - reg [31 : 0] v__h18186; - reg [31 : 0] v__h23802; - reg [31 : 0] v__h25975; - reg [31 : 0] v__h24056; - reg [31 : 0] v__h26250; - reg [31 : 0] v__h26463; - reg [31 : 0] v__h26740; - reg [31 : 0] v__h26968; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h28048; - reg [31 : 0] v__h67030; - reg [31 : 0] v__h67318; - reg [31 : 0] v__h67847; - reg [31 : 0] v__h67933; - reg [31 : 0] v__h68132; - reg [31 : 0] v__h68353; - reg [31 : 0] v__h74690; - reg [31 : 0] v__h74800; - reg [31 : 0] v__h74913; - reg [31 : 0] v__h6138; - reg [31 : 0] v__h13074; - reg [31 : 0] v__h13259; - reg [31 : 0] v__h13457; - reg [31 : 0] v__h13707; - reg [31 : 0] v__h18180; - reg [31 : 0] v__h23796; - reg [31 : 0] v__h24050; - reg [31 : 0] v__h25969; - reg [31 : 0] v__h26244; - reg [31 : 0] v__h26457; - reg [31 : 0] v__h26734; - reg [31 : 0] v__h26962; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28042; - reg [31 : 0] v__h67024; - reg [31 : 0] v__h67312; - reg [31 : 0] v__h67841; - reg [31 : 0] v__h67927; - reg [31 : 0] v__h68126; - reg [31 : 0] v__h68347; - reg [31 : 0] v__h74684; - reg [31 : 0] v__h74794; - reg [31 : 0] v__h74907; - reg [31 : 0] v__h75670; - reg [31 : 0] v__h75868; - reg [31 : 0] v__h76066; - reg [31 : 0] v__h76264; - reg [31 : 0] v__h76462; - reg [31 : 0] v__h76660; - reg [31 : 0] v__h76858; - reg [31 : 0] v__h77056; - reg [31 : 0] v__h77254; - reg [31 : 0] v__h77452; - reg [31 : 0] v__h77650; - reg [31 : 0] v__h77848; - reg [31 : 0] v__h78046; - reg [31 : 0] v__h78244; - reg [31 : 0] v__h78442; - reg [31 : 0] v__h78640; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] y_avValue_fst__h26148; - reg [4 : 0] x__h24011, x__h67487; - reg [2 : 0] x__h13493, x__h23832; - reg [1 : 0] v__h67107, y_avValue_snd__h26149; - reg CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - wire [63 : 0] addr_offset__h13216, - addr_offset__h26929, - rdata___1__h26404, - rdata__h26202, - v__h13422, - v__h13671, - v__h18144, - v__h23761, - v__h25455, - v__h25474, - x__h26361, - y_avValue_fst__h26094, - y_avValue_fst__h26115, - y_avValue_fst__h26127, - y_avValue_fst__h26143, - y_avValue_fst__h26159, - y_avValue_fst__h26164, - y_avValue_fst__h26175, - y_avValue_fst__h26180, - y_avValue_fst__h26194; - wire [31 : 0] v_ie__h18147, - v_ip__h13674, - wdata32__h26930, - x__h23673, - x__h67110; - wire [9 : 0] source_id__h15665, - source_id__h15772, - source_id__h15845, - source_id__h15918, - source_id__h15991, - source_id__h16064, - source_id__h16137, - source_id__h16210, - source_id__h16283, - source_id__h16356, - source_id__h16429, - source_id__h16502, - source_id__h16575, - source_id__h16648, - source_id__h16721, - source_id__h16794, - source_id__h16867, - source_id__h16940, - source_id__h17013, - source_id__h17086, - source_id__h17159, - source_id__h17232, - source_id__h17305, - source_id__h17378, - source_id__h17451, - source_id__h17524, - source_id__h17597, - source_id__h17670, - source_id__h17743, - source_id__h17816, - source_id__h17889, - source_id__h20137, - source_id__h20313, - source_id__h20421, - source_id__h20529, - source_id__h20637, - source_id__h20745, - source_id__h20853, - source_id__h20961, - source_id__h21069, - source_id__h21177, - source_id__h21285, - source_id__h21393, - source_id__h21501, - source_id__h21609, - source_id__h21717, - source_id__h21825, - source_id__h21933, - source_id__h22041, - source_id__h22149, - source_id__h22257, - source_id__h22365, - source_id__h22473, - source_id__h22581, - source_id__h22689, - source_id__h22797, - source_id__h22905, - source_id__h23013, - source_id__h23121, - source_id__h23229, - source_id__h23337, - source_id__h23445, - source_id__h29475, - source_id__h30685, - source_id__h31895, - source_id__h33105, - source_id__h34315, - source_id__h35525, - source_id__h36735, - source_id__h37945, - source_id__h39155, - source_id__h40365, - source_id__h41575, - source_id__h42785, - source_id__h43995, - source_id__h45205, - source_id__h46415, - source_id__h47625, - source_id__h48835, - source_id__h50045, - source_id__h51255, - source_id__h52465, - source_id__h53675, - source_id__h54885, - source_id__h56095, - source_id__h57305, - source_id__h58515, - source_id__h59725, - source_id__h60935, - source_id__h62145, - source_id__h63355, - source_id__h64565, - source_id__h65775, - source_id__h67436, - source_id_base__h13630, - source_id_base__h28148; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71313, - b__h73318, - max_id__h23959; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71312, - a__h73317; - wire [1 : 0] rresp__h26203, - v__h26934, - v__h27094, - v__h27107, - v__h27942, - v__h27961, - v__h28125, - v__h28144, - v__h67144, - v__h67432, - v__h67476, - y_avValue_snd__h26095, - y_avValue_snd__h26116, - y_avValue_snd__h26128, - y_avValue_snd__h26144, - y_avValue_snd__h26160, - y_avValue_snd__h26165, - y_avValue_snd__h26176, - y_avValue_snd__h26181, - y_avValue_snd__h26195; - wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, - NOT_m_cfg_verbosity_read_ULE_1_5___d16, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982, - NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313, - 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_dfoo264, - _dfoo266, - _dfoo268, - _dfoo27, - _dfoo270, - _dfoo272, - _dfoo273, - _dfoo274, - _dfoo275, - _dfoo276, - _dfoo277, - _dfoo278, - _dfoo279, - _dfoo28, - _dfoo280, - _dfoo281, - _dfoo282, - _dfoo283, - _dfoo284, - _dfoo285, - _dfoo286, - _dfoo287, - _dfoo288, - _dfoo289, - _dfoo29, - _dfoo290, - _dfoo291, - _dfoo292, - _dfoo293, - _dfoo294, - _dfoo295, - _dfoo296, - _dfoo297, - _dfoo298, - _dfoo299, - _dfoo3, - _dfoo30, - _dfoo300, - _dfoo301, - _dfoo302, - _dfoo303, - _dfoo304, - _dfoo305, - _dfoo306, - _dfoo307, - _dfoo308, - _dfoo309, - _dfoo31, - _dfoo310, - _dfoo311, - _dfoo312, - _dfoo313, - _dfoo314, - _dfoo315, - _dfoo316, - _dfoo317, - _dfoo318, - _dfoo319, - _dfoo32, - _dfoo320, - _dfoo321, - _dfoo322, - _dfoo323, - _dfoo324, - _dfoo325, - _dfoo326, - _dfoo327, - _dfoo328, - _dfoo329, - _dfoo33, - _dfoo330, - _dfoo331, - _dfoo332, - _dfoo333, - _dfoo334, - _dfoo335, - _dfoo336, - _dfoo337, - _dfoo338, - _dfoo339, - _dfoo34, - _dfoo340, - _dfoo342, - _dfoo344, - _dfoo346, - _dfoo348, - _dfoo35, - _dfoo350, - _dfoo352, - _dfoo354, - _dfoo356, - _dfoo358, - _dfoo36, - _dfoo360, - _dfoo362, - _dfoo364, - _dfoo366, - _dfoo368, - _dfoo37, - _dfoo370, - _dfoo372, - _dfoo374, - _dfoo376, - _dfoo378, - _dfoo38, - _dfoo380, - _dfoo382, - _dfoo384, - _dfoo386, - _dfoo388, - _dfoo39, - _dfoo390, - _dfoo392, - _dfoo394, - _dfoo396, - _dfoo398, - _dfoo4, - _dfoo40, - _dfoo400, - _dfoo402, - _dfoo404, - _dfoo406, - _dfoo408, - _dfoo409, - _dfoo41, - _dfoo410, - _dfoo411, - _dfoo412, - _dfoo413, - _dfoo414, - _dfoo415, - _dfoo416, - _dfoo417, - _dfoo418, - _dfoo419, - _dfoo42, - _dfoo420, - _dfoo421, - _dfoo422, - _dfoo423, - _dfoo424, - _dfoo425, - _dfoo426, - _dfoo427, - _dfoo428, - _dfoo429, - _dfoo43, - _dfoo430, - _dfoo431, - _dfoo432, - _dfoo433, - _dfoo434, - _dfoo435, - _dfoo436, - _dfoo437, - _dfoo438, - _dfoo439, - _dfoo44, - _dfoo440, - _dfoo441, - _dfoo442, - _dfoo443, - _dfoo444, - _dfoo445, - _dfoo446, - _dfoo447, - _dfoo448, - _dfoo449, - _dfoo45, - _dfoo450, - _dfoo451, - _dfoo452, - _dfoo453, - _dfoo454, - _dfoo455, - _dfoo456, - _dfoo457, - _dfoo458, - _dfoo459, - _dfoo46, - _dfoo460, - _dfoo461, - _dfoo462, - _dfoo463, - _dfoo464, - _dfoo465, - _dfoo466, - _dfoo467, - _dfoo468, - _dfoo469, - _dfoo47, - _dfoo470, - _dfoo471, - _dfoo472, - _dfoo473, - _dfoo474, - _dfoo475, - _dfoo476, - _dfoo478, - _dfoo48, - _dfoo480, - _dfoo482, - _dfoo484, - _dfoo486, - _dfoo488, - _dfoo49, - _dfoo490, - _dfoo492, - _dfoo494, - _dfoo496, - _dfoo498, - _dfoo5, - _dfoo50, - _dfoo500, - _dfoo502, - _dfoo504, - _dfoo506, - _dfoo508, - _dfoo51, - _dfoo510, - _dfoo512, - _dfoo514, - _dfoo516, - _dfoo518, - _dfoo52, - _dfoo520, - _dfoo522, - _dfoo524, - _dfoo526, - _dfoo528, - _dfoo53, - _dfoo530, - _dfoo532, - _dfoo534, - _dfoo536, - _dfoo538, - _dfoo54, - _dfoo540, - _dfoo542, - _dfoo544, - _dfoo545, - _dfoo546, - _dfoo547, - _dfoo548, - _dfoo549, - _dfoo55, - _dfoo550, - _dfoo551, - _dfoo552, - _dfoo553, - _dfoo554, - _dfoo555, - _dfoo556, - _dfoo557, - _dfoo558, - _dfoo559, - _dfoo56, - _dfoo560, - _dfoo561, - _dfoo562, - _dfoo563, - _dfoo564, - _dfoo565, - _dfoo566, - _dfoo567, - _dfoo568, - _dfoo569, - _dfoo57, - _dfoo570, - _dfoo571, - _dfoo572, - _dfoo573, - _dfoo574, - _dfoo575, - _dfoo576, - _dfoo577, - _dfoo578, - _dfoo579, - _dfoo58, - _dfoo580, - _dfoo581, - _dfoo582, - _dfoo583, - _dfoo584, - _dfoo585, - _dfoo586, - _dfoo587, - _dfoo588, - _dfoo589, - _dfoo59, - _dfoo590, - _dfoo591, - _dfoo592, - _dfoo593, - _dfoo594, - _dfoo595, - _dfoo596, - _dfoo597, - _dfoo598, - _dfoo599, - _dfoo6, - _dfoo60, - _dfoo600, - _dfoo601, - _dfoo602, - _dfoo603, - _dfoo604, - _dfoo605, - _dfoo606, - _dfoo607, - _dfoo608, - _dfoo609, - _dfoo61, - _dfoo610, - _dfoo611, - _dfoo612, - _dfoo614, - _dfoo616, - _dfoo618, - _dfoo62, - _dfoo620, - _dfoo622, - _dfoo624, - _dfoo626, - _dfoo628, - _dfoo63, - _dfoo630, - _dfoo632, - _dfoo634, - _dfoo636, - _dfoo638, - _dfoo64, - _dfoo640, - _dfoo642, - _dfoo644, - _dfoo646, - _dfoo648, - _dfoo65, - _dfoo650, - _dfoo652, - _dfoo654, - _dfoo656, - _dfoo658, - _dfoo66, - _dfoo660, - _dfoo662, - _dfoo664, - _dfoo666, - _dfoo668, - _dfoo67, - _dfoo670, - _dfoo672, - _dfoo674, - _dfoo676, - _dfoo678, - _dfoo68, - _dfoo680, - _dfoo681, - _dfoo682, - _dfoo683, - _dfoo684, - _dfoo685, - _dfoo686, - _dfoo687, - _dfoo688, - _dfoo689, - _dfoo690, - _dfoo691, - _dfoo692, - _dfoo693, - _dfoo694, - _dfoo695, - _dfoo696, - _dfoo697, - _dfoo698, - _dfoo699, - _dfoo7, - _dfoo70, - _dfoo700, - _dfoo701, - _dfoo702, - _dfoo703, - _dfoo704, - _dfoo705, - _dfoo706, - _dfoo707, - _dfoo708, - _dfoo709, - _dfoo710, - _dfoo711, - _dfoo712, - _dfoo713, - _dfoo714, - _dfoo715, - _dfoo716, - _dfoo717, - _dfoo718, - _dfoo719, - _dfoo72, - _dfoo720, - _dfoo721, - _dfoo722, - _dfoo723, - _dfoo724, - _dfoo725, - _dfoo726, - _dfoo727, - _dfoo728, - _dfoo729, - _dfoo730, - _dfoo731, - _dfoo732, - _dfoo733, - _dfoo734, - _dfoo735, - _dfoo736, - _dfoo737, - _dfoo738, - _dfoo739, - _dfoo74, - _dfoo740, - _dfoo741, - _dfoo742, - _dfoo743, - _dfoo744, - _dfoo745, - _dfoo746, - _dfoo747, - _dfoo748, - _dfoo750, - _dfoo752, - _dfoo754, - _dfoo756, - _dfoo758, - _dfoo76, - _dfoo760, - _dfoo762, - _dfoo764, - _dfoo766, - _dfoo768, - _dfoo770, - _dfoo772, - _dfoo774, - _dfoo776, - _dfoo778, - _dfoo78, - _dfoo780, - _dfoo782, - _dfoo784, - _dfoo786, - _dfoo788, - _dfoo790, - _dfoo792, - _dfoo794, - _dfoo796, - _dfoo798, - _dfoo8, - _dfoo80, - _dfoo800, - _dfoo802, - _dfoo804, - _dfoo806, - _dfoo808, - _dfoo810, - _dfoo812, - _dfoo814, - _dfoo816, - _dfoo817, - _dfoo818, - _dfoo819, - _dfoo82, - _dfoo820, - _dfoo821, - _dfoo822, - _dfoo823, - _dfoo824, - _dfoo825, - _dfoo826, - _dfoo827, - _dfoo828, - _dfoo829, - _dfoo830, - _dfoo831, - _dfoo832, - _dfoo833, - _dfoo834, - _dfoo835, - _dfoo836, - _dfoo837, - _dfoo838, - _dfoo839, - _dfoo84, - _dfoo840, - _dfoo841, - _dfoo842, - _dfoo843, - _dfoo844, - _dfoo845, - _dfoo846, - _dfoo847, - _dfoo848, - _dfoo849, - _dfoo850, - _dfoo851, - _dfoo852, - _dfoo853, - _dfoo854, - _dfoo855, - _dfoo856, - _dfoo857, - _dfoo858, - _dfoo859, - _dfoo86, - _dfoo860, - _dfoo861, - _dfoo862, - _dfoo863, - _dfoo864, - _dfoo865, - _dfoo866, - _dfoo867, - _dfoo868, - _dfoo869, - _dfoo870, - _dfoo871, - _dfoo872, - _dfoo873, - _dfoo874, - _dfoo875, - _dfoo876, - _dfoo877, - _dfoo878, - _dfoo879, - _dfoo88, - _dfoo880, - _dfoo881, - _dfoo882, - _dfoo883, - _dfoo884, - _dfoo886, - _dfoo888, - _dfoo890, - _dfoo892, - _dfoo894, - _dfoo896, - _dfoo898, - _dfoo9, - _dfoo90, - _dfoo900, - _dfoo902, - _dfoo904, - _dfoo906, - _dfoo908, - _dfoo910, - _dfoo912, - _dfoo914, - _dfoo916, - _dfoo918, - _dfoo92, - _dfoo920, - _dfoo922, - _dfoo924, - _dfoo926, - _dfoo928, - _dfoo930, - _dfoo932, - _dfoo934, - _dfoo936, - _dfoo938, - _dfoo94, - _dfoo940, - _dfoo942, - _dfoo944, - _dfoo946, - _dfoo948, - _dfoo950, - _dfoo952, - _dfoo953, - _dfoo954, - _dfoo955, - _dfoo956, - _dfoo957, - _dfoo958, - _dfoo959, - _dfoo96, - _dfoo960, - _dfoo961, - _dfoo962, - _dfoo963, - _dfoo964, - _dfoo965, - _dfoo966, - _dfoo967, - _dfoo968, - _dfoo969, - _dfoo970, - _dfoo971, - _dfoo972, - _dfoo973, - _dfoo974, - _dfoo975, - _dfoo976, - _dfoo977, - _dfoo978, - _dfoo979, - _dfoo98, - _dfoo980, - _dfoo981, - _dfoo982, - _dfoo983, - _dfoo984, - _dfoo985, - _dfoo986, - _dfoo987, - _dfoo988, - _dfoo989, - _dfoo990, - _dfoo991, - _dfoo992, - _dfoo993, - _dfoo994, - _dfoo995, - _dfoo996, - _dfoo997, - _dfoo998, - _dfoo999, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, - m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method show_PLIC_state - assign RDY_show_PLIC_state = 1'd1 ; - assign CAN_FIRE_show_PLIC_state = 1'd1 ; - assign WILL_FIRE_show_PLIC_state = EN_show_PLIC_state ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // action method v_sources_0_m_interrupt_req - assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - - // action method v_sources_1_m_interrupt_req - assign CAN_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - - // action method v_sources_2_m_interrupt_req - assign CAN_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - - // action method v_sources_3_m_interrupt_req - assign CAN_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - - // action method v_sources_4_m_interrupt_req - assign CAN_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - - // action method v_sources_5_m_interrupt_req - assign CAN_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - - // action method v_sources_6_m_interrupt_req - assign CAN_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - - // action method v_sources_7_m_interrupt_req - assign CAN_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - - // action method v_sources_8_m_interrupt_req - assign CAN_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - - // action method v_sources_9_m_interrupt_req - assign CAN_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - - // action method v_sources_10_m_interrupt_req - assign CAN_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - - // action method v_sources_11_m_interrupt_req - assign CAN_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - - // action method v_sources_12_m_interrupt_req - assign CAN_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - - // action method v_sources_13_m_interrupt_req - assign CAN_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - - // action method v_sources_14_m_interrupt_req - assign CAN_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - - // action method v_sources_15_m_interrupt_req - assign CAN_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - - // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71312 > m_vrg_target_threshold_0 ; - - // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73317 > m_vrg_target_threshold_1 ; - - // submodule m_f_reset_reqs - FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_reqs$ENQ), - .DEQ(m_f_reset_reqs$DEQ), - .CLR(m_f_reset_reqs$CLR), - .FULL_N(m_f_reset_reqs$FULL_N), - .EMPTY_N(m_f_reset_reqs$EMPTY_N)); - - // submodule m_f_reset_rsps - FIFO20 #(.guarded(32'd1)) m_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_rsps$ENQ), - .DEQ(m_f_reset_rsps$DEQ), - .CLR(m_f_reset_rsps$CLR), - .FULL_N(m_f_reset_rsps$FULL_N), - .EMPTY_N(m_f_reset_rsps$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_addr$D_IN), - .ENQ(m_slave_xactor_f_rd_addr$ENQ), - .DEQ(m_slave_xactor_f_rd_addr$DEQ), - .CLR(m_slave_xactor_f_rd_addr$CLR), - .D_OUT(m_slave_xactor_f_rd_addr$D_OUT), - .FULL_N(m_slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_data$D_IN), - .ENQ(m_slave_xactor_f_rd_data$ENQ), - .DEQ(m_slave_xactor_f_rd_data$DEQ), - .CLR(m_slave_xactor_f_rd_data$CLR), - .D_OUT(m_slave_xactor_f_rd_data$D_OUT), - .FULL_N(m_slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_addr$D_IN), - .ENQ(m_slave_xactor_f_wr_addr$ENQ), - .DEQ(m_slave_xactor_f_wr_addr$DEQ), - .CLR(m_slave_xactor_f_wr_addr$CLR), - .D_OUT(m_slave_xactor_f_wr_addr$D_OUT), - .FULL_N(m_slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_data$D_IN), - .ENQ(m_slave_xactor_f_wr_data$ENQ), - .DEQ(m_slave_xactor_f_wr_data$DEQ), - .CLR(m_slave_xactor_f_wr_data$CLR), - .D_OUT(m_slave_xactor_f_wr_data$D_OUT), - .FULL_N(m_slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_resp$D_IN), - .ENQ(m_slave_xactor_f_wr_resp$ENQ), - .DEQ(m_slave_xactor_f_wr_resp$DEQ), - .CLR(m_slave_xactor_f_wr_resp$CLR), - .D_OUT(m_slave_xactor_f_wr_resp$D_OUT), - .FULL_N(m_slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = - m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - - // rule RL_m_rl_process_rd_req - assign CAN_FIRE_RL_m_rl_process_rd_req = - m_slave_xactor_f_rd_addr$EMPTY_N && - m_slave_xactor_f_rd_data$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - - // rule RL_m_rl_process_wr_req - assign CAN_FIRE_RL_m_rl_process_wr_req = - m_slave_xactor_f_wr_addr$EMPTY_N && - m_slave_xactor_f_wr_data$EMPTY_N && - m_slave_xactor_f_wr_resp$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_wr_req = - CAN_FIRE_RL_m_rl_process_wr_req && - !WILL_FIRE_RL_m_rl_process_rd_req ; - - // inputs to muxes for submodule ports - assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; - assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; - assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; - assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; - assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; - assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; - assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; - assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; - assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; - assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; - assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; - assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; - assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; - assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; - assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; - assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; - assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; - assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; - assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; - assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; - assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ; - assign MUX_m_vvrg_ie_0_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ; - assign MUX_m_vvrg_ie_0_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ; - assign MUX_m_vvrg_ie_0_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ; - assign MUX_m_vvrg_ie_0_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ; - assign MUX_m_vvrg_ie_0_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ; - assign MUX_m_vvrg_ie_0_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ; - assign MUX_m_vvrg_ie_0_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ; - assign MUX_m_vvrg_ie_0_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ; - assign MUX_m_vvrg_ie_0_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ; - assign MUX_m_vvrg_ie_0_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ; - assign MUX_m_vvrg_ie_0_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ; - assign MUX_m_vvrg_ie_0_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ; - assign MUX_m_vvrg_ie_0_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ; - assign MUX_m_vvrg_ie_0_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ; - assign MUX_m_vvrg_ie_0_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ; - assign MUX_m_vvrg_ie_1_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ; - assign MUX_m_vvrg_ie_1_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ; - assign MUX_m_vvrg_ie_1_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ; - assign MUX_m_vvrg_ie_1_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ; - assign MUX_m_vvrg_ie_1_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ; - assign MUX_m_vvrg_ie_1_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ; - assign MUX_m_vvrg_ie_1_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ; - assign MUX_m_vvrg_ie_1_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ; - assign MUX_m_vvrg_ie_1_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ; - assign MUX_m_vvrg_ie_1_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ; - assign MUX_m_vvrg_ie_1_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ; - assign MUX_m_vvrg_ie_1_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ; - assign MUX_m_vvrg_ie_1_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ; - assign MUX_m_vvrg_ie_1_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ; - assign MUX_m_vvrg_ie_1_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ; - assign MUX_m_vvrg_ie_1_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ; - assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; - assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2040 ; - assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2038 ; - assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2020 ; - assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2018 ; - assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2016 ; - assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2014 ; - assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2012 ; - assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2010 ; - assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2008 ; - assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2036 ; - assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2034 ; - assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2032 ; - assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2030 ; - assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2028 ; - assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2026 ; - assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2024 ; - assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2022 ; - assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2006 ; - assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2004 ; - assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1986 ; - assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1984 ; - assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1982 ; - assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1980 ; - assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1978 ; - assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1976 ; - assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1974 ; - assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2002 ; - assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2000 ; - assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1998 ; - assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1996 ; - assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1994 ; - assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1992 ; - assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1990 ; - assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1988 ; - - // register m_cfg_verbosity - assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign m_cfg_verbosity$EN = EN_set_verbosity ; - - // register m_rg_addr_base - assign m_rg_addr_base$D_IN = set_addr_map_addr_base ; - assign m_rg_addr_base$EN = EN_set_addr_map ; - - // register m_rg_addr_lim - assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign m_rg_addr_lim$EN = EN_set_addr_map ; - - // register m_vrg_servicing_source_0 - assign m_vrg_servicing_source_0$D_IN = - MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_servicing_source_1 - assign m_vrg_servicing_source_1$D_IN = - MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_0 - assign m_vrg_source_busy_0$D_IN = - !MUX_m_vrg_source_busy_0$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_1 - assign m_vrg_source_busy_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_10 - assign m_vrg_source_busy_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_11 - assign m_vrg_source_busy_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_12 - assign m_vrg_source_busy_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_13 - assign m_vrg_source_busy_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_14 - assign m_vrg_source_busy_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_15 - assign m_vrg_source_busy_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_16 - assign m_vrg_source_busy_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_2 - assign m_vrg_source_busy_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_3 - assign m_vrg_source_busy_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_4 - assign m_vrg_source_busy_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_5 - assign m_vrg_source_busy_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_6 - assign m_vrg_source_busy_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_7 - assign m_vrg_source_busy_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_8 - assign m_vrg_source_busy_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_9 - assign m_vrg_source_busy_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_0 - assign m_vrg_source_ip_0$D_IN = 1'd0 ; - assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_1 - assign m_vrg_source_ip_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_0_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_1$EN = - !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_10 - assign m_vrg_source_ip_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_9_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_10$EN = - !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_11 - assign m_vrg_source_ip_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_10_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_11$EN = - !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_12 - assign m_vrg_source_ip_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_11_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_12$EN = - !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_13 - assign m_vrg_source_ip_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_12_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_13$EN = - !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_14 - assign m_vrg_source_ip_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_13_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_14$EN = - !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_15 - assign m_vrg_source_ip_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_14_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_15$EN = - !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_16 - assign m_vrg_source_ip_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_15_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_16$EN = - !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_2 - assign m_vrg_source_ip_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_1_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_2$EN = - !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_3 - assign m_vrg_source_ip_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_2_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_3$EN = - !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_4 - assign m_vrg_source_ip_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_3_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_4$EN = - !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_5 - assign m_vrg_source_ip_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_4_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_5$EN = - !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_6 - assign m_vrg_source_ip_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_5_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_6$EN = - !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_7 - assign m_vrg_source_ip_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_6_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_7$EN = - !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_8 - assign m_vrg_source_ip_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_7_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_8$EN = - !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_9 - assign m_vrg_source_ip_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_8_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_9$EN = - !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_0 - assign m_vrg_source_prio_0$D_IN = - MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_1 - assign m_vrg_source_prio_1$D_IN = - MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_10 - assign m_vrg_source_prio_10$D_IN = - MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_11 - assign m_vrg_source_prio_11$D_IN = - MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_12 - assign m_vrg_source_prio_12$D_IN = - MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_13 - assign m_vrg_source_prio_13$D_IN = - MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_14 - assign m_vrg_source_prio_14$D_IN = - MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_15 - assign m_vrg_source_prio_15$D_IN = - MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_16 - assign m_vrg_source_prio_16$D_IN = - MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_2 - assign m_vrg_source_prio_2$D_IN = - MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_3 - assign m_vrg_source_prio_3$D_IN = - MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_4 - assign m_vrg_source_prio_4$D_IN = - MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_5 - assign m_vrg_source_prio_5$D_IN = - MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_6 - assign m_vrg_source_prio_6$D_IN = - MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_7 - assign m_vrg_source_prio_7$D_IN = - MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_8 - assign m_vrg_source_prio_8$D_IN = - MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_9 - assign m_vrg_source_prio_9$D_IN = - MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_0 - assign m_vrg_target_threshold_0$D_IN = - MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_1 - assign m_vrg_target_threshold_1$D_IN = - MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_0 - assign m_vvrg_ie_0_0$D_IN = - MUX_m_vvrg_ie_0_0$write_1__SEL_1 && - MUX_m_vvrg_ie_0_0$write_1__VAL_1 ; - assign m_vvrg_ie_0_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_1 - assign m_vvrg_ie_0_1$D_IN = - MUX_m_vvrg_ie_0_1$write_1__SEL_1 && - MUX_m_vvrg_ie_0_1$write_1__VAL_1 ; - assign m_vvrg_ie_0_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_10 - assign m_vvrg_ie_0_10$D_IN = - MUX_m_vvrg_ie_0_10$write_1__SEL_1 && - MUX_m_vvrg_ie_0_10$write_1__VAL_1 ; - assign m_vvrg_ie_0_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_11 - assign m_vvrg_ie_0_11$D_IN = - MUX_m_vvrg_ie_0_11$write_1__SEL_1 && - MUX_m_vvrg_ie_0_11$write_1__VAL_1 ; - assign m_vvrg_ie_0_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_12 - assign m_vvrg_ie_0_12$D_IN = - MUX_m_vvrg_ie_0_12$write_1__SEL_1 && - MUX_m_vvrg_ie_0_12$write_1__VAL_1 ; - assign m_vvrg_ie_0_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_13 - assign m_vvrg_ie_0_13$D_IN = - MUX_m_vvrg_ie_0_13$write_1__SEL_1 && - MUX_m_vvrg_ie_0_13$write_1__VAL_1 ; - assign m_vvrg_ie_0_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_14 - assign m_vvrg_ie_0_14$D_IN = - MUX_m_vvrg_ie_0_14$write_1__SEL_1 && - MUX_m_vvrg_ie_0_14$write_1__VAL_1 ; - assign m_vvrg_ie_0_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_15 - assign m_vvrg_ie_0_15$D_IN = - MUX_m_vvrg_ie_0_15$write_1__SEL_1 && - MUX_m_vvrg_ie_0_15$write_1__VAL_1 ; - assign m_vvrg_ie_0_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_16 - assign m_vvrg_ie_0_16$D_IN = - MUX_m_vvrg_ie_0_16$write_1__SEL_1 && - MUX_m_vvrg_ie_0_16$write_1__VAL_1 ; - assign m_vvrg_ie_0_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_2 - assign m_vvrg_ie_0_2$D_IN = - MUX_m_vvrg_ie_0_2$write_1__SEL_1 && - MUX_m_vvrg_ie_0_2$write_1__VAL_1 ; - assign m_vvrg_ie_0_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_3 - assign m_vvrg_ie_0_3$D_IN = - MUX_m_vvrg_ie_0_3$write_1__SEL_1 && - MUX_m_vvrg_ie_0_3$write_1__VAL_1 ; - assign m_vvrg_ie_0_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_4 - assign m_vvrg_ie_0_4$D_IN = - MUX_m_vvrg_ie_0_4$write_1__SEL_1 && - MUX_m_vvrg_ie_0_4$write_1__VAL_1 ; - assign m_vvrg_ie_0_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_5 - assign m_vvrg_ie_0_5$D_IN = - MUX_m_vvrg_ie_0_5$write_1__SEL_1 && - MUX_m_vvrg_ie_0_5$write_1__VAL_1 ; - assign m_vvrg_ie_0_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_6 - assign m_vvrg_ie_0_6$D_IN = - MUX_m_vvrg_ie_0_6$write_1__SEL_1 && - MUX_m_vvrg_ie_0_6$write_1__VAL_1 ; - assign m_vvrg_ie_0_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_7 - assign m_vvrg_ie_0_7$D_IN = - MUX_m_vvrg_ie_0_7$write_1__SEL_1 && - MUX_m_vvrg_ie_0_7$write_1__VAL_1 ; - assign m_vvrg_ie_0_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_8 - assign m_vvrg_ie_0_8$D_IN = - MUX_m_vvrg_ie_0_8$write_1__SEL_1 && - MUX_m_vvrg_ie_0_8$write_1__VAL_1 ; - assign m_vvrg_ie_0_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_9 - assign m_vvrg_ie_0_9$D_IN = - MUX_m_vvrg_ie_0_9$write_1__SEL_1 && - MUX_m_vvrg_ie_0_9$write_1__VAL_1 ; - assign m_vvrg_ie_0_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_0 - assign m_vvrg_ie_1_0$D_IN = - MUX_m_vvrg_ie_1_0$write_1__SEL_1 && - MUX_m_vvrg_ie_1_0$write_1__VAL_1 ; - assign m_vvrg_ie_1_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_1 - assign m_vvrg_ie_1_1$D_IN = - MUX_m_vvrg_ie_1_1$write_1__SEL_1 && - MUX_m_vvrg_ie_1_1$write_1__VAL_1 ; - assign m_vvrg_ie_1_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_10 - assign m_vvrg_ie_1_10$D_IN = - MUX_m_vvrg_ie_1_10$write_1__SEL_1 && - MUX_m_vvrg_ie_1_10$write_1__VAL_1 ; - assign m_vvrg_ie_1_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_11 - assign m_vvrg_ie_1_11$D_IN = - MUX_m_vvrg_ie_1_11$write_1__SEL_1 && - MUX_m_vvrg_ie_1_11$write_1__VAL_1 ; - assign m_vvrg_ie_1_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_12 - assign m_vvrg_ie_1_12$D_IN = - MUX_m_vvrg_ie_1_12$write_1__SEL_1 && - MUX_m_vvrg_ie_1_12$write_1__VAL_1 ; - assign m_vvrg_ie_1_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_13 - assign m_vvrg_ie_1_13$D_IN = - MUX_m_vvrg_ie_1_13$write_1__SEL_1 && - MUX_m_vvrg_ie_1_13$write_1__VAL_1 ; - assign m_vvrg_ie_1_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_14 - assign m_vvrg_ie_1_14$D_IN = - MUX_m_vvrg_ie_1_14$write_1__SEL_1 && - MUX_m_vvrg_ie_1_14$write_1__VAL_1 ; - assign m_vvrg_ie_1_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_15 - assign m_vvrg_ie_1_15$D_IN = - MUX_m_vvrg_ie_1_15$write_1__SEL_1 && - MUX_m_vvrg_ie_1_15$write_1__VAL_1 ; - assign m_vvrg_ie_1_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_16 - assign m_vvrg_ie_1_16$D_IN = - MUX_m_vvrg_ie_1_16$write_1__SEL_1 && - MUX_m_vvrg_ie_1_16$write_1__VAL_1 ; - assign m_vvrg_ie_1_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_2 - assign m_vvrg_ie_1_2$D_IN = - MUX_m_vvrg_ie_1_2$write_1__SEL_1 && - MUX_m_vvrg_ie_1_2$write_1__VAL_1 ; - assign m_vvrg_ie_1_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_3 - assign m_vvrg_ie_1_3$D_IN = - MUX_m_vvrg_ie_1_3$write_1__SEL_1 && - MUX_m_vvrg_ie_1_3$write_1__VAL_1 ; - assign m_vvrg_ie_1_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_4 - assign m_vvrg_ie_1_4$D_IN = - MUX_m_vvrg_ie_1_4$write_1__SEL_1 && - MUX_m_vvrg_ie_1_4$write_1__VAL_1 ; - assign m_vvrg_ie_1_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_5 - assign m_vvrg_ie_1_5$D_IN = - MUX_m_vvrg_ie_1_5$write_1__SEL_1 && - MUX_m_vvrg_ie_1_5$write_1__VAL_1 ; - assign m_vvrg_ie_1_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_6 - assign m_vvrg_ie_1_6$D_IN = - MUX_m_vvrg_ie_1_6$write_1__SEL_1 && - MUX_m_vvrg_ie_1_6$write_1__VAL_1 ; - assign m_vvrg_ie_1_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_7 - assign m_vvrg_ie_1_7$D_IN = - MUX_m_vvrg_ie_1_7$write_1__SEL_1 && - MUX_m_vvrg_ie_1_7$write_1__VAL_1 ; - assign m_vvrg_ie_1_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_8 - assign m_vvrg_ie_1_8$D_IN = - MUX_m_vvrg_ie_1_8$write_1__SEL_1 && - MUX_m_vvrg_ie_1_8$write_1__VAL_1 ; - assign m_vvrg_ie_1_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_9 - assign m_vvrg_ie_1_9$D_IN = - MUX_m_vvrg_ie_1_9$write_1__SEL_1 && - MUX_m_vvrg_ie_1_9$write_1__VAL_1 ; - assign m_vvrg_ie_1_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 || - WILL_FIRE_RL_m_rl_reset ; - - // submodule m_f_reset_reqs - assign m_f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign m_f_reset_reqs$DEQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_reqs$CLR = 1'b0 ; - - // submodule m_f_reset_rsps - assign m_f_reset_rsps$ENQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign m_f_reset_rsps$CLR = 1'b0 ; - - // submodule m_slave_xactor_f_rd_addr - assign m_slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign m_slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ; - assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_rd_data - assign m_slave_xactor_f_rd_data$D_IN = - { m_slave_xactor_f_rd_addr$D_OUT[96:93], - x__h26361, - rresp__h26203, - 1'd1 } ; - assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ; - assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_addr - assign m_slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign m_slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ; - assign m_slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_data - assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign m_slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; - assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_resp - assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26934 } ; - assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; - assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ; - - // remaining internal signals - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 : - ((x__h23673 == 32'h00200000) ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 : - x__h23673 != 32'h00200004 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 || - x__h24011 != 5'd0) ; - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - addr_offset__h13216[11:2] == 10'd0 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 : - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67110 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67110 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26929[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 = - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - 5'd2 : - (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ; - assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200000 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30685 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31895 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33105 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34315 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35525 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36735 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37945 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39155 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40365 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41575 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42785 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43995 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45205 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46415 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47625 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48835 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50045 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51255 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52465 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53675 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54885 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56095 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57305 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58515 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59725 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60935 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62145 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63355 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64565 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65775 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29475 <= 10'd16 ; - assign NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313 = - !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321 = - !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_11 != - v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329 = - !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_12 != - v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337 = - !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_13 != - v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345 = - !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_14 != - v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353 = - !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_15 != - v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361 = - !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_16 != - v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242 = - !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249 = - !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257 = - !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265 = - !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273 = - !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281 = - !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289 = - !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297 = - !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305 = - !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; - assign _dfoo1 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo10 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo100 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo32 ; - assign _dfoo1000 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo932 ; - assign _dfoo1001 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo865 ; - assign _dfoo1002 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo934 ; - assign _dfoo1003 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo867 ; - assign _dfoo1004 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo936 ; - assign _dfoo1005 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo869 ; - assign _dfoo1006 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo938 ; - assign _dfoo1007 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo871 ; - assign _dfoo1008 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo940 ; - assign _dfoo1009 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo873 ; - assign _dfoo1010 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo942 ; - assign _dfoo1011 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo875 ; - assign _dfoo1012 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo944 ; - assign _dfoo1013 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo877 ; - assign _dfoo1014 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo946 ; - assign _dfoo1015 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo879 ; - assign _dfoo1016 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo948 ; - assign _dfoo1017 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo881 ; - assign _dfoo1018 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo950 ; - assign _dfoo1019 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo883 ; - assign _dfoo102 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo34 ; - assign _dfoo1020 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo952 ; - assign _dfoo1022 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo954 ; - assign _dfoo1024 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo956 ; - assign _dfoo1026 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo958 ; - assign _dfoo1028 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo960 ; - assign _dfoo1030 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo962 ; - assign _dfoo1032 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo964 ; - assign _dfoo1034 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo966 ; - assign _dfoo1036 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo968 ; - assign _dfoo1038 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo970 ; - assign _dfoo104 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo36 ; - assign _dfoo1040 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo972 ; - assign _dfoo1042 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo974 ; - assign _dfoo1044 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo976 ; - assign _dfoo1046 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo978 ; - assign _dfoo1048 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo980 ; - assign _dfoo1050 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo982 ; - assign _dfoo1052 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo984 ; - assign _dfoo1054 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo986 ; - assign _dfoo1056 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo988 ; - assign _dfoo1058 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo990 ; - assign _dfoo106 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo38 ; - assign _dfoo1060 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo992 ; - assign _dfoo1062 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo994 ; - assign _dfoo1064 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo996 ; - assign _dfoo1066 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo998 ; - assign _dfoo1068 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1000 ; - assign _dfoo1070 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1002 ; - assign _dfoo1072 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1004 ; - assign _dfoo1074 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1006 ; - assign _dfoo1076 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1008 ; - assign _dfoo1078 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1010 ; - assign _dfoo108 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo40 ; - assign _dfoo1080 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1012 ; - assign _dfoo1082 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1014 ; - assign _dfoo1084 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1016 ; - assign _dfoo1086 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1018 ; - assign _dfoo1088 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1020 ; - assign _dfoo1089 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo953 ; - assign _dfoo1090 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1022 ; - assign _dfoo1091 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo955 ; - assign _dfoo1092 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1024 ; - assign _dfoo1093 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo957 ; - assign _dfoo1094 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1026 ; - assign _dfoo1095 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo959 ; - assign _dfoo1096 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1028 ; - assign _dfoo1097 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo961 ; - assign _dfoo1098 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1030 ; - assign _dfoo1099 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo963 ; - assign _dfoo11 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo110 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo42 ; - assign _dfoo1100 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1032 ; - assign _dfoo1101 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo965 ; - assign _dfoo1102 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1034 ; - assign _dfoo1103 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo967 ; - assign _dfoo1104 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1036 ; - assign _dfoo1105 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo969 ; - assign _dfoo1106 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1038 ; - assign _dfoo1107 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo971 ; - assign _dfoo1108 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1040 ; - assign _dfoo1109 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo973 ; - assign _dfoo1110 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1042 ; - assign _dfoo1111 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo975 ; - assign _dfoo1112 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1044 ; - assign _dfoo1113 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo977 ; - assign _dfoo1114 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1046 ; - assign _dfoo1115 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo979 ; - assign _dfoo1116 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1048 ; - assign _dfoo1117 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo981 ; - assign _dfoo1118 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1050 ; - assign _dfoo1119 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo983 ; - assign _dfoo112 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo44 ; - assign _dfoo1120 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1052 ; - assign _dfoo1121 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo985 ; - assign _dfoo1122 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1054 ; - assign _dfoo1123 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo987 ; - assign _dfoo1124 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1056 ; - assign _dfoo1125 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo989 ; - assign _dfoo1126 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1058 ; - assign _dfoo1127 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo991 ; - assign _dfoo1128 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1060 ; - assign _dfoo1129 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo993 ; - assign _dfoo1130 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1062 ; - assign _dfoo1131 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo995 ; - assign _dfoo1132 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1064 ; - assign _dfoo1133 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo997 ; - assign _dfoo1134 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1066 ; - assign _dfoo1135 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo999 ; - assign _dfoo1136 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1068 ; - assign _dfoo1137 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1001 ; - assign _dfoo1138 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1070 ; - assign _dfoo1139 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1003 ; - assign _dfoo114 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo46 ; - assign _dfoo1140 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1072 ; - assign _dfoo1141 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1005 ; - assign _dfoo1142 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1074 ; - assign _dfoo1143 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1007 ; - assign _dfoo1144 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1076 ; - assign _dfoo1145 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1009 ; - assign _dfoo1146 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1078 ; - assign _dfoo1147 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1011 ; - assign _dfoo1148 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1080 ; - assign _dfoo1149 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1013 ; - assign _dfoo1150 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1082 ; - assign _dfoo1151 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1015 ; - assign _dfoo1152 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1084 ; - assign _dfoo1153 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1017 ; - assign _dfoo1154 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1086 ; - assign _dfoo1155 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1019 ; - assign _dfoo1156 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1088 ; - assign _dfoo1158 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1090 ; - assign _dfoo116 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo48 ; - assign _dfoo1160 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1092 ; - assign _dfoo1162 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1094 ; - assign _dfoo1164 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1096 ; - assign _dfoo1166 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1098 ; - assign _dfoo1168 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1100 ; - assign _dfoo1170 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1102 ; - assign _dfoo1172 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1104 ; - assign _dfoo1174 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1106 ; - assign _dfoo1176 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1108 ; - assign _dfoo1178 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1110 ; - assign _dfoo118 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo50 ; - assign _dfoo1180 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1112 ; - assign _dfoo1182 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1114 ; - assign _dfoo1184 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1116 ; - assign _dfoo1186 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1118 ; - assign _dfoo1188 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1120 ; - assign _dfoo1190 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1122 ; - assign _dfoo1192 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1124 ; - assign _dfoo1194 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1126 ; - assign _dfoo1196 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1128 ; - assign _dfoo1198 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1130 ; - assign _dfoo12 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo120 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo52 ; - assign _dfoo1200 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1132 ; - assign _dfoo1202 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1134 ; - assign _dfoo1204 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1136 ; - assign _dfoo1206 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1138 ; - assign _dfoo1208 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1140 ; - assign _dfoo1210 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1142 ; - assign _dfoo1212 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1144 ; - assign _dfoo1214 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1146 ; - assign _dfoo1216 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1148 ; - assign _dfoo1218 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1150 ; - assign _dfoo122 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo54 ; - assign _dfoo1220 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1152 ; - assign _dfoo1222 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1154 ; - assign _dfoo1224 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1156 ; - assign _dfoo1225 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1089 ; - assign _dfoo1226 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1158 ; - assign _dfoo1227 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1091 ; - assign _dfoo1228 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1160 ; - assign _dfoo1229 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1093 ; - assign _dfoo1230 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1162 ; - assign _dfoo1231 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1095 ; - assign _dfoo1232 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1164 ; - assign _dfoo1233 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1097 ; - assign _dfoo1234 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1166 ; - assign _dfoo1235 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1099 ; - assign _dfoo1236 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1168 ; - assign _dfoo1237 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1101 ; - assign _dfoo1238 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1170 ; - assign _dfoo1239 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1103 ; - assign _dfoo124 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo56 ; - assign _dfoo1240 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1172 ; - assign _dfoo1241 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1105 ; - assign _dfoo1242 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1174 ; - assign _dfoo1243 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1107 ; - assign _dfoo1244 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1176 ; - assign _dfoo1245 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1109 ; - assign _dfoo1246 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1178 ; - assign _dfoo1247 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1111 ; - assign _dfoo1248 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1180 ; - assign _dfoo1249 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1113 ; - assign _dfoo1250 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1182 ; - assign _dfoo1251 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1115 ; - assign _dfoo1252 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1184 ; - assign _dfoo1253 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1117 ; - assign _dfoo1254 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1186 ; - assign _dfoo1255 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1119 ; - assign _dfoo1256 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1188 ; - assign _dfoo1257 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1121 ; - assign _dfoo1258 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1190 ; - assign _dfoo1259 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1123 ; - assign _dfoo126 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo58 ; - assign _dfoo1260 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1192 ; - assign _dfoo1261 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1125 ; - assign _dfoo1262 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1194 ; - assign _dfoo1263 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1127 ; - assign _dfoo1264 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1196 ; - assign _dfoo1265 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1129 ; - assign _dfoo1266 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1198 ; - assign _dfoo1267 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1131 ; - assign _dfoo1268 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1200 ; - assign _dfoo1269 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1133 ; - assign _dfoo1270 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1202 ; - assign _dfoo1271 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1135 ; - assign _dfoo1272 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1204 ; - assign _dfoo1273 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1137 ; - assign _dfoo1274 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1206 ; - assign _dfoo1275 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1139 ; - assign _dfoo1276 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1208 ; - assign _dfoo1277 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1141 ; - assign _dfoo1278 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1210 ; - assign _dfoo1279 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1143 ; - assign _dfoo128 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo60 ; - assign _dfoo1280 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1212 ; - assign _dfoo1281 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1145 ; - assign _dfoo1282 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1214 ; - assign _dfoo1283 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1147 ; - assign _dfoo1284 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1216 ; - assign _dfoo1285 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1149 ; - assign _dfoo1286 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1218 ; - assign _dfoo1287 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1151 ; - assign _dfoo1288 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1220 ; - assign _dfoo1289 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1153 ; - assign _dfoo1290 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1222 ; - assign _dfoo1291 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1155 ; - assign _dfoo1292 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1224 ; - assign _dfoo1294 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1226 ; - assign _dfoo1296 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1228 ; - assign _dfoo1298 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1230 ; - assign _dfoo13 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo130 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo62 ; - assign _dfoo1300 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1232 ; - assign _dfoo1302 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1234 ; - assign _dfoo1304 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1236 ; - assign _dfoo1306 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1238 ; - assign _dfoo1308 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1240 ; - assign _dfoo1310 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1242 ; - assign _dfoo1312 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1244 ; - assign _dfoo1314 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1246 ; - assign _dfoo1316 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1248 ; - assign _dfoo1318 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1250 ; - assign _dfoo132 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo64 ; - assign _dfoo1320 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1252 ; - assign _dfoo1322 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1254 ; - assign _dfoo1324 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1256 ; - assign _dfoo1326 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1258 ; - assign _dfoo1328 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1260 ; - assign _dfoo1330 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1262 ; - assign _dfoo1332 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1264 ; - assign _dfoo1334 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1266 ; - assign _dfoo1336 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1268 ; - assign _dfoo1338 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1270 ; - assign _dfoo134 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo66 ; - assign _dfoo1340 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1272 ; - assign _dfoo1342 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1274 ; - assign _dfoo1344 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1276 ; - assign _dfoo1346 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1278 ; - assign _dfoo1348 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1280 ; - assign _dfoo1350 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1282 ; - assign _dfoo1352 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1284 ; - assign _dfoo1354 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1286 ; - assign _dfoo1356 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1288 ; - assign _dfoo1358 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1290 ; - assign _dfoo136 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo68 ; - assign _dfoo1360 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1292 ; - assign _dfoo1361 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1225 ; - assign _dfoo1362 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1294 ; - assign _dfoo1363 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1227 ; - assign _dfoo1364 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1296 ; - assign _dfoo1365 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1229 ; - assign _dfoo1366 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1298 ; - assign _dfoo1367 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1231 ; - assign _dfoo1368 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1300 ; - assign _dfoo1369 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1233 ; - assign _dfoo137 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo1 ; - assign _dfoo1370 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1302 ; - assign _dfoo1371 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1235 ; - assign _dfoo1372 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1304 ; - assign _dfoo1373 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1237 ; - assign _dfoo1374 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1306 ; - assign _dfoo1375 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1239 ; - assign _dfoo1376 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1308 ; - assign _dfoo1377 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1241 ; - assign _dfoo1378 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1310 ; - assign _dfoo1379 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1243 ; - assign _dfoo138 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo70 ; - assign _dfoo1380 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1312 ; - assign _dfoo1381 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1245 ; - assign _dfoo1382 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1314 ; - assign _dfoo1383 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1247 ; - assign _dfoo1384 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1316 ; - assign _dfoo1385 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1249 ; - assign _dfoo1386 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1318 ; - assign _dfoo1387 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1251 ; - assign _dfoo1388 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1320 ; - assign _dfoo1389 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1253 ; - assign _dfoo139 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo3 ; - assign _dfoo1390 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1322 ; - assign _dfoo1391 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1255 ; - assign _dfoo1392 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1324 ; - assign _dfoo1393 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1257 ; - assign _dfoo1394 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1326 ; - assign _dfoo1395 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1259 ; - assign _dfoo1396 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1328 ; - assign _dfoo1397 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1261 ; - assign _dfoo1398 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1330 ; - assign _dfoo1399 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1263 ; - assign _dfoo14 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo140 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo72 ; - assign _dfoo1400 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1332 ; - assign _dfoo1401 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1265 ; - assign _dfoo1402 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1334 ; - assign _dfoo1403 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1267 ; - assign _dfoo1404 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1336 ; - assign _dfoo1405 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1269 ; - assign _dfoo1406 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1338 ; - assign _dfoo1407 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1271 ; - assign _dfoo1408 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1340 ; - assign _dfoo1409 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1273 ; - assign _dfoo141 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo5 ; - assign _dfoo1410 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1342 ; - assign _dfoo1411 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1275 ; - assign _dfoo1412 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1344 ; - assign _dfoo1413 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1277 ; - assign _dfoo1414 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1346 ; - assign _dfoo1415 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1279 ; - assign _dfoo1416 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1348 ; - assign _dfoo1417 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1281 ; - assign _dfoo1418 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1350 ; - assign _dfoo1419 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1283 ; - assign _dfoo142 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo74 ; - assign _dfoo1420 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1352 ; - assign _dfoo1421 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1285 ; - assign _dfoo1422 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1354 ; - assign _dfoo1423 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1287 ; - assign _dfoo1424 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1356 ; - assign _dfoo1425 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1289 ; - assign _dfoo1426 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1358 ; - assign _dfoo1427 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1291 ; - assign _dfoo1428 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1360 ; - assign _dfoo143 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo7 ; - assign _dfoo1430 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1362 ; - assign _dfoo1432 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1364 ; - assign _dfoo1434 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1366 ; - assign _dfoo1436 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1368 ; - assign _dfoo1438 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1370 ; - assign _dfoo144 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo76 ; - assign _dfoo1440 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1372 ; - assign _dfoo1442 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1374 ; - assign _dfoo1444 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1376 ; - assign _dfoo1446 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1378 ; - assign _dfoo1448 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1380 ; - assign _dfoo145 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo9 ; - assign _dfoo1450 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1382 ; - assign _dfoo1452 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1384 ; - assign _dfoo1454 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1386 ; - assign _dfoo1456 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1388 ; - assign _dfoo1458 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1390 ; - assign _dfoo146 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo78 ; - assign _dfoo1460 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1392 ; - assign _dfoo1462 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1394 ; - assign _dfoo1464 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1396 ; - assign _dfoo1466 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1398 ; - assign _dfoo1468 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1400 ; - assign _dfoo147 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo11 ; - assign _dfoo1470 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1402 ; - assign _dfoo1472 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1404 ; - assign _dfoo1474 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1406 ; - assign _dfoo1476 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1408 ; - assign _dfoo1478 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1410 ; - assign _dfoo148 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo80 ; - assign _dfoo1480 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1412 ; - assign _dfoo1482 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1414 ; - assign _dfoo1484 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1416 ; - assign _dfoo1486 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1418 ; - assign _dfoo1488 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1420 ; - assign _dfoo149 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo13 ; - assign _dfoo1490 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1422 ; - assign _dfoo1492 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1424 ; - assign _dfoo1494 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1426 ; - assign _dfoo1496 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1428 ; - assign _dfoo1497 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1361 ; - assign _dfoo1498 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1430 ; - assign _dfoo1499 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1363 ; - assign _dfoo15 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo150 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo82 ; - assign _dfoo1500 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1432 ; - assign _dfoo1501 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1365 ; - assign _dfoo1502 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1434 ; - assign _dfoo1503 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1367 ; - assign _dfoo1504 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1436 ; - assign _dfoo1505 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1369 ; - assign _dfoo1506 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1438 ; - assign _dfoo1507 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1371 ; - assign _dfoo1508 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1440 ; - assign _dfoo1509 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1373 ; - assign _dfoo151 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo15 ; - assign _dfoo1510 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1442 ; - assign _dfoo1511 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1375 ; - assign _dfoo1512 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1444 ; - assign _dfoo1513 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1377 ; - assign _dfoo1514 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1446 ; - assign _dfoo1515 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1379 ; - assign _dfoo1516 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1448 ; - assign _dfoo1517 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1381 ; - assign _dfoo1518 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1450 ; - assign _dfoo1519 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1383 ; - assign _dfoo152 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo84 ; - assign _dfoo1520 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1452 ; - assign _dfoo1521 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1385 ; - assign _dfoo1522 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1454 ; - assign _dfoo1523 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1387 ; - assign _dfoo1524 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1456 ; - assign _dfoo1525 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1389 ; - assign _dfoo1526 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1458 ; - assign _dfoo1527 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1391 ; - assign _dfoo1528 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1460 ; - assign _dfoo1529 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1393 ; - assign _dfoo153 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo17 ; - assign _dfoo1530 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1462 ; - assign _dfoo1531 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1395 ; - assign _dfoo1532 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1464 ; - assign _dfoo1533 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1397 ; - assign _dfoo1534 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1466 ; - assign _dfoo1535 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1399 ; - assign _dfoo1536 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1468 ; - assign _dfoo1537 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1401 ; - assign _dfoo1538 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1470 ; - assign _dfoo1539 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1403 ; - assign _dfoo154 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo86 ; - assign _dfoo1540 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1472 ; - assign _dfoo1541 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1405 ; - assign _dfoo1542 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1474 ; - assign _dfoo1543 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1407 ; - assign _dfoo1544 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1476 ; - assign _dfoo1545 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1409 ; - assign _dfoo1546 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1478 ; - assign _dfoo1547 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1411 ; - assign _dfoo1548 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1480 ; - assign _dfoo1549 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1413 ; - assign _dfoo155 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo19 ; - assign _dfoo1550 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1482 ; - assign _dfoo1551 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1415 ; - assign _dfoo1552 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1484 ; - assign _dfoo1553 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1417 ; - assign _dfoo1554 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1486 ; - assign _dfoo1555 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1419 ; - assign _dfoo1556 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1488 ; - assign _dfoo1557 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1421 ; - assign _dfoo1558 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1490 ; - assign _dfoo1559 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1423 ; - assign _dfoo156 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo88 ; - assign _dfoo1560 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1492 ; - assign _dfoo1561 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1425 ; - assign _dfoo1562 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1494 ; - assign _dfoo1563 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1427 ; - assign _dfoo1564 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1496 ; - assign _dfoo1566 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1498 ; - assign _dfoo1568 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1500 ; - assign _dfoo157 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo21 ; - assign _dfoo1570 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1502 ; - assign _dfoo1572 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1504 ; - assign _dfoo1574 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1506 ; - assign _dfoo1576 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1508 ; - assign _dfoo1578 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1510 ; - assign _dfoo158 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo90 ; - assign _dfoo1580 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1512 ; - assign _dfoo1582 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1514 ; - assign _dfoo1584 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1516 ; - assign _dfoo1586 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1518 ; - assign _dfoo1588 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1520 ; - assign _dfoo159 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo23 ; - assign _dfoo1590 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1522 ; - assign _dfoo1592 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1524 ; - assign _dfoo1594 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1526 ; - assign _dfoo1596 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1528 ; - assign _dfoo1598 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1530 ; - assign _dfoo16 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo160 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo92 ; - assign _dfoo1600 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1532 ; - assign _dfoo1602 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1534 ; - assign _dfoo1604 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1536 ; - assign _dfoo1606 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1538 ; - assign _dfoo1608 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1540 ; - assign _dfoo161 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo25 ; - assign _dfoo1610 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1542 ; - assign _dfoo1612 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1544 ; - assign _dfoo1614 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1546 ; - assign _dfoo1616 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1548 ; - assign _dfoo1618 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1550 ; - assign _dfoo162 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo94 ; - assign _dfoo1620 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1552 ; - assign _dfoo1622 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1554 ; - assign _dfoo1624 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1556 ; - assign _dfoo1626 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1558 ; - assign _dfoo1628 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1560 ; - assign _dfoo163 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo27 ; - assign _dfoo1630 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1562 ; - assign _dfoo1632 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1564 ; - assign _dfoo1633 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1497 ; - assign _dfoo1634 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1566 ; - assign _dfoo1635 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1499 ; - assign _dfoo1636 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1568 ; - assign _dfoo1637 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1501 ; - assign _dfoo1638 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1570 ; - assign _dfoo1639 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1503 ; - assign _dfoo164 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo96 ; - assign _dfoo1640 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1572 ; - assign _dfoo1641 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1505 ; - assign _dfoo1642 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1574 ; - assign _dfoo1643 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1507 ; - assign _dfoo1644 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1576 ; - assign _dfoo1645 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1509 ; - assign _dfoo1646 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1578 ; - assign _dfoo1647 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1511 ; - assign _dfoo1648 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1580 ; - assign _dfoo1649 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1513 ; - assign _dfoo165 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo29 ; - assign _dfoo1650 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1582 ; - assign _dfoo1651 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1515 ; - assign _dfoo1652 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1584 ; - assign _dfoo1653 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1517 ; - assign _dfoo1654 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1586 ; - assign _dfoo1655 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1519 ; - assign _dfoo1656 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1588 ; - assign _dfoo1657 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1521 ; - assign _dfoo1658 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1590 ; - assign _dfoo1659 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1523 ; - assign _dfoo166 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo98 ; - assign _dfoo1660 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1592 ; - assign _dfoo1661 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1525 ; - assign _dfoo1662 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1594 ; - assign _dfoo1663 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1527 ; - assign _dfoo1664 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1596 ; - assign _dfoo1665 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1529 ; - assign _dfoo1666 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1598 ; - assign _dfoo1667 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1531 ; - assign _dfoo1668 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1600 ; - assign _dfoo1669 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1533 ; - assign _dfoo167 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo31 ; - assign _dfoo1670 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1602 ; - assign _dfoo1671 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1535 ; - assign _dfoo1672 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1604 ; - assign _dfoo1673 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1537 ; - assign _dfoo1674 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1606 ; - assign _dfoo1675 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1539 ; - assign _dfoo1676 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1608 ; - assign _dfoo1677 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1541 ; - assign _dfoo1678 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1610 ; - assign _dfoo1679 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1543 ; - assign _dfoo168 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo100 ; - assign _dfoo1680 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1612 ; - assign _dfoo1681 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1545 ; - assign _dfoo1682 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1614 ; - assign _dfoo1683 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1547 ; - assign _dfoo1684 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1616 ; - assign _dfoo1685 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1549 ; - assign _dfoo1686 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1618 ; - assign _dfoo1687 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1551 ; - assign _dfoo1688 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1620 ; - assign _dfoo1689 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1553 ; - assign _dfoo169 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo33 ; - assign _dfoo1690 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1622 ; - assign _dfoo1691 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1555 ; - assign _dfoo1692 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1624 ; - assign _dfoo1693 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1557 ; - assign _dfoo1694 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1626 ; - assign _dfoo1695 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1559 ; - assign _dfoo1696 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1628 ; - assign _dfoo1697 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1561 ; - assign _dfoo1698 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1630 ; - assign _dfoo1699 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1563 ; - assign _dfoo17 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo170 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo102 ; - assign _dfoo1700 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1632 ; - assign _dfoo1702 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1634 ; - assign _dfoo1704 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1636 ; - assign _dfoo1706 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1638 ; - assign _dfoo1708 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1640 ; - assign _dfoo171 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo35 ; - assign _dfoo1710 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1642 ; - assign _dfoo1712 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1644 ; - assign _dfoo1714 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1646 ; - assign _dfoo1716 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1648 ; - assign _dfoo1718 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1650 ; - assign _dfoo172 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo104 ; - assign _dfoo1720 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1652 ; - assign _dfoo1722 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1654 ; - assign _dfoo1724 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1656 ; - assign _dfoo1726 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1658 ; - assign _dfoo1728 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1660 ; - assign _dfoo173 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo37 ; - assign _dfoo1730 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1662 ; - assign _dfoo1732 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1664 ; - assign _dfoo1734 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1666 ; - assign _dfoo1736 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1668 ; - assign _dfoo1738 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1670 ; - assign _dfoo174 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo106 ; - assign _dfoo1740 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1672 ; - assign _dfoo1742 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1674 ; - assign _dfoo1744 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1676 ; - assign _dfoo1746 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1678 ; - assign _dfoo1748 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1680 ; - assign _dfoo175 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo39 ; - assign _dfoo1750 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1682 ; - assign _dfoo1752 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1684 ; - assign _dfoo1754 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1686 ; - assign _dfoo1756 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1688 ; - assign _dfoo1758 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1690 ; - assign _dfoo176 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo108 ; - assign _dfoo1760 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1692 ; - assign _dfoo1762 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1694 ; - assign _dfoo1764 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1696 ; - assign _dfoo1766 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1698 ; - assign _dfoo1768 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1700 ; - assign _dfoo1769 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1633 ; - assign _dfoo177 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo41 ; - assign _dfoo1770 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1702 ; - assign _dfoo1771 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1635 ; - assign _dfoo1772 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1704 ; - assign _dfoo1773 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1637 ; - assign _dfoo1774 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1706 ; - assign _dfoo1775 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1639 ; - assign _dfoo1776 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1708 ; - assign _dfoo1777 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1641 ; - assign _dfoo1778 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1710 ; - assign _dfoo1779 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1643 ; - assign _dfoo178 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo110 ; - assign _dfoo1780 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1712 ; - assign _dfoo1781 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1645 ; - assign _dfoo1782 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1714 ; - assign _dfoo1783 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1647 ; - assign _dfoo1784 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1716 ; - assign _dfoo1785 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1649 ; - assign _dfoo1786 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1718 ; - assign _dfoo1787 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1651 ; - assign _dfoo1788 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1720 ; - assign _dfoo1789 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1653 ; - assign _dfoo179 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo43 ; - assign _dfoo1790 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1722 ; - assign _dfoo1791 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1655 ; - assign _dfoo1792 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1724 ; - assign _dfoo1793 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1657 ; - assign _dfoo1794 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1726 ; - assign _dfoo1795 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1659 ; - assign _dfoo1796 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1728 ; - assign _dfoo1797 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1661 ; - assign _dfoo1798 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1730 ; - assign _dfoo1799 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1663 ; - assign _dfoo18 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo180 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo112 ; - assign _dfoo1800 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1732 ; - assign _dfoo1801 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1665 ; - assign _dfoo1802 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1734 ; - assign _dfoo1803 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1667 ; - assign _dfoo1804 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1736 ; - assign _dfoo1805 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1669 ; - assign _dfoo1806 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1738 ; - assign _dfoo1807 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1671 ; - assign _dfoo1808 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1740 ; - assign _dfoo1809 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1673 ; - assign _dfoo181 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo45 ; - assign _dfoo1810 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1742 ; - assign _dfoo1811 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1675 ; - assign _dfoo1812 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1744 ; - assign _dfoo1813 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1677 ; - assign _dfoo1814 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1746 ; - assign _dfoo1815 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1679 ; - assign _dfoo1816 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1748 ; - assign _dfoo1817 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1681 ; - assign _dfoo1818 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1750 ; - assign _dfoo1819 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1683 ; - assign _dfoo182 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo114 ; - assign _dfoo1820 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1752 ; - assign _dfoo1821 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1685 ; - assign _dfoo1822 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1754 ; - assign _dfoo1823 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1687 ; - assign _dfoo1824 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1756 ; - assign _dfoo1825 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1689 ; - assign _dfoo1826 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1758 ; - assign _dfoo1827 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1691 ; - assign _dfoo1828 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1760 ; - assign _dfoo1829 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1693 ; - assign _dfoo183 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo47 ; - assign _dfoo1830 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1762 ; - assign _dfoo1831 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1695 ; - assign _dfoo1832 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1764 ; - assign _dfoo1833 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1697 ; - assign _dfoo1834 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1766 ; - assign _dfoo1835 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1699 ; - assign _dfoo1836 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1768 ; - assign _dfoo1838 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1770 ; - assign _dfoo184 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo116 ; - assign _dfoo1840 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1772 ; - assign _dfoo1842 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1774 ; - assign _dfoo1844 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1776 ; - assign _dfoo1846 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1778 ; - assign _dfoo1848 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1780 ; - assign _dfoo185 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo49 ; - assign _dfoo1850 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1782 ; - assign _dfoo1852 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1784 ; - assign _dfoo1854 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1786 ; - assign _dfoo1856 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1788 ; - assign _dfoo1858 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1790 ; - assign _dfoo186 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo118 ; - assign _dfoo1860 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1792 ; - assign _dfoo1862 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1794 ; - assign _dfoo1864 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1796 ; - assign _dfoo1866 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1798 ; - assign _dfoo1868 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1800 ; - assign _dfoo187 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo51 ; - assign _dfoo1870 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1802 ; - assign _dfoo1872 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1804 ; - assign _dfoo1874 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1806 ; - assign _dfoo1876 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1808 ; - assign _dfoo1878 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1810 ; - assign _dfoo188 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo120 ; - assign _dfoo1880 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1812 ; - assign _dfoo1882 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1814 ; - assign _dfoo1884 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1816 ; - assign _dfoo1886 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1818 ; - assign _dfoo1888 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1820 ; - assign _dfoo189 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo53 ; - assign _dfoo1890 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1822 ; - assign _dfoo1892 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1824 ; - assign _dfoo1894 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1826 ; - assign _dfoo1896 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1828 ; - assign _dfoo1898 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1830 ; - assign _dfoo19 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo190 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo122 ; - assign _dfoo1900 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1832 ; - assign _dfoo1902 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1834 ; - assign _dfoo1904 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1836 ; - assign _dfoo1905 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1769 ; - assign _dfoo1906 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1838 ; - assign _dfoo1907 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1771 ; - assign _dfoo1908 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1840 ; - assign _dfoo1909 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1773 ; - assign _dfoo191 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo55 ; - assign _dfoo1910 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1842 ; - assign _dfoo1911 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1775 ; - assign _dfoo1912 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1844 ; - assign _dfoo1913 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1777 ; - assign _dfoo1914 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1846 ; - assign _dfoo1915 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1779 ; - assign _dfoo1916 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1848 ; - assign _dfoo1917 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1781 ; - assign _dfoo1918 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1850 ; - assign _dfoo1919 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1783 ; - assign _dfoo192 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo124 ; - assign _dfoo1920 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1852 ; - assign _dfoo1921 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1785 ; - assign _dfoo1922 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1854 ; - assign _dfoo1923 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1787 ; - assign _dfoo1924 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1856 ; - assign _dfoo1925 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1789 ; - assign _dfoo1926 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1858 ; - assign _dfoo1927 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1791 ; - assign _dfoo1928 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1860 ; - assign _dfoo1929 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1793 ; - assign _dfoo193 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo57 ; - assign _dfoo1930 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1862 ; - assign _dfoo1931 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1795 ; - assign _dfoo1932 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1864 ; - assign _dfoo1933 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1797 ; - assign _dfoo1934 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1866 ; - assign _dfoo1935 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1799 ; - assign _dfoo1936 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1868 ; - assign _dfoo1937 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1801 ; - assign _dfoo1938 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1870 ; - assign _dfoo1939 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1803 ; - assign _dfoo194 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo126 ; - assign _dfoo1940 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1872 ; - assign _dfoo1941 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1805 ; - assign _dfoo1942 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1874 ; - assign _dfoo1943 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1807 ; - assign _dfoo1944 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1876 ; - assign _dfoo1945 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1809 ; - assign _dfoo1946 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1878 ; - assign _dfoo1947 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1811 ; - assign _dfoo1948 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1880 ; - assign _dfoo1949 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1813 ; - assign _dfoo195 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo59 ; - assign _dfoo1950 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1882 ; - assign _dfoo1951 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1815 ; - assign _dfoo1952 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1884 ; - assign _dfoo1953 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1817 ; - assign _dfoo1954 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1886 ; - assign _dfoo1955 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1819 ; - assign _dfoo1956 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1888 ; - assign _dfoo1957 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1821 ; - assign _dfoo1958 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1890 ; - assign _dfoo1959 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1823 ; - assign _dfoo196 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo128 ; - assign _dfoo1960 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1892 ; - assign _dfoo1961 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1825 ; - assign _dfoo1962 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1894 ; - assign _dfoo1963 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1827 ; - assign _dfoo1964 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1896 ; - assign _dfoo1965 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1829 ; - assign _dfoo1966 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1898 ; - assign _dfoo1967 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1831 ; - assign _dfoo1968 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1900 ; - assign _dfoo1969 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1833 ; - assign _dfoo197 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo61 ; - assign _dfoo1970 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1902 ; - assign _dfoo1971 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1835 ; - assign _dfoo1972 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1904 ; - assign _dfoo1974 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1906 ; - assign _dfoo1976 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1908 ; - assign _dfoo1978 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1910 ; - assign _dfoo198 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo130 ; - assign _dfoo1980 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1912 ; - assign _dfoo1982 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1914 ; - assign _dfoo1984 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1916 ; - assign _dfoo1986 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1918 ; - assign _dfoo1988 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1920 ; - assign _dfoo199 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo63 ; - assign _dfoo1990 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1922 ; - assign _dfoo1992 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1924 ; - assign _dfoo1994 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1926 ; - assign _dfoo1996 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1928 ; - assign _dfoo1998 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1930 ; - assign _dfoo2 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo20 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo200 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo132 ; - assign _dfoo2000 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1932 ; - assign _dfoo2002 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1934 ; - assign _dfoo2004 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1936 ; - assign _dfoo2006 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1938 ; - assign _dfoo2008 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1940 ; - assign _dfoo201 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo65 ; - assign _dfoo2010 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1942 ; - assign _dfoo2012 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1944 ; - assign _dfoo2014 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1946 ; - assign _dfoo2016 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1948 ; - assign _dfoo2018 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1950 ; - assign _dfoo202 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo134 ; - assign _dfoo2020 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1952 ; - assign _dfoo2022 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1954 ; - assign _dfoo2024 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1956 ; - assign _dfoo2026 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1958 ; - assign _dfoo2028 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1960 ; - assign _dfoo203 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo67 ; - assign _dfoo2030 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1962 ; - assign _dfoo2032 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1964 ; - assign _dfoo2034 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1966 ; - assign _dfoo2036 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1968 ; - assign _dfoo2038 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1970 ; - assign _dfoo204 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo136 ; - assign _dfoo2040 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1972 ; - assign _dfoo2041 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1905 ; - assign _dfoo2043 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1907 ; - assign _dfoo2045 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1909 ; - assign _dfoo2047 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1911 ; - assign _dfoo2049 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1913 ; - assign _dfoo2051 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1915 ; - assign _dfoo2053 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1917 ; - assign _dfoo2055 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1919 ; - assign _dfoo2057 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1921 ; - assign _dfoo2059 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1923 ; - assign _dfoo206 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo138 ; - assign _dfoo2061 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1925 ; - assign _dfoo2063 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1927 ; - assign _dfoo2065 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1929 ; - assign _dfoo2067 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1931 ; - assign _dfoo2069 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1933 ; - assign _dfoo2071 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1935 ; - assign _dfoo2073 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1937 ; - assign _dfoo2075 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1939 ; - assign _dfoo2077 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1941 ; - assign _dfoo2079 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1943 ; - assign _dfoo208 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo140 ; - assign _dfoo2081 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1945 ; - assign _dfoo2083 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1947 ; - assign _dfoo2085 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1949 ; - assign _dfoo2087 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1951 ; - assign _dfoo2089 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1953 ; - assign _dfoo2091 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1955 ; - assign _dfoo2093 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1957 ; - assign _dfoo2095 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1959 ; - assign _dfoo2097 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1961 ; - assign _dfoo2099 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1963 ; - assign _dfoo21 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo210 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo142 ; - assign _dfoo2101 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1965 ; - assign _dfoo2103 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1967 ; - assign _dfoo2105 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1969 ; - assign _dfoo2107 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1971 ; - assign _dfoo212 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo144 ; - assign _dfoo214 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo146 ; - assign _dfoo216 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo148 ; - assign _dfoo218 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo150 ; - assign _dfoo22 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo220 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo152 ; - assign _dfoo222 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo154 ; - assign _dfoo224 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo156 ; - assign _dfoo226 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo158 ; - assign _dfoo228 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo160 ; - assign _dfoo23 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo230 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo162 ; - assign _dfoo232 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo164 ; - assign _dfoo234 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo166 ; - assign _dfoo236 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo168 ; - assign _dfoo238 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo170 ; - assign _dfoo24 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo240 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo172 ; - assign _dfoo242 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo174 ; - assign _dfoo244 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo176 ; - assign _dfoo246 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo178 ; - assign _dfoo248 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo180 ; - assign _dfoo25 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo250 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo182 ; - assign _dfoo252 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo184 ; - assign _dfoo254 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo186 ; - assign _dfoo256 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo188 ; - assign _dfoo258 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo190 ; - assign _dfoo26 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo260 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo192 ; - assign _dfoo262 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo194 ; - assign _dfoo264 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo196 ; - assign _dfoo266 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo198 ; - assign _dfoo268 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo200 ; - assign _dfoo27 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo270 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo202 ; - assign _dfoo272 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo204 ; - assign _dfoo273 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo137 ; - assign _dfoo274 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo206 ; - assign _dfoo275 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo139 ; - assign _dfoo276 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo208 ; - assign _dfoo277 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo141 ; - assign _dfoo278 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo210 ; - assign _dfoo279 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo143 ; - assign _dfoo28 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo280 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo212 ; - assign _dfoo281 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo145 ; - assign _dfoo282 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo214 ; - assign _dfoo283 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo147 ; - assign _dfoo284 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo216 ; - assign _dfoo285 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo149 ; - assign _dfoo286 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo218 ; - assign _dfoo287 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo151 ; - assign _dfoo288 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo220 ; - assign _dfoo289 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo153 ; - assign _dfoo29 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo290 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo222 ; - assign _dfoo291 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo155 ; - assign _dfoo292 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo224 ; - assign _dfoo293 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo157 ; - assign _dfoo294 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo226 ; - assign _dfoo295 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo159 ; - assign _dfoo296 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo228 ; - assign _dfoo297 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo161 ; - assign _dfoo298 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo230 ; - assign _dfoo299 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo163 ; - assign _dfoo3 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo30 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo300 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo232 ; - assign _dfoo301 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo165 ; - assign _dfoo302 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo234 ; - assign _dfoo303 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo167 ; - assign _dfoo304 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo236 ; - assign _dfoo305 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo169 ; - assign _dfoo306 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo238 ; - assign _dfoo307 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo171 ; - assign _dfoo308 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo240 ; - assign _dfoo309 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo173 ; - assign _dfoo31 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo310 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo242 ; - assign _dfoo311 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo175 ; - assign _dfoo312 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo244 ; - assign _dfoo313 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo177 ; - assign _dfoo314 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo246 ; - assign _dfoo315 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo179 ; - assign _dfoo316 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo248 ; - assign _dfoo317 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo181 ; - assign _dfoo318 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo250 ; - assign _dfoo319 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo183 ; - assign _dfoo32 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo320 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo252 ; - assign _dfoo321 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo185 ; - assign _dfoo322 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo254 ; - assign _dfoo323 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo187 ; - assign _dfoo324 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo256 ; - assign _dfoo325 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo189 ; - assign _dfoo326 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo258 ; - assign _dfoo327 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo191 ; - assign _dfoo328 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo260 ; - assign _dfoo329 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo193 ; - assign _dfoo33 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo330 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo262 ; - assign _dfoo331 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo195 ; - assign _dfoo332 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo264 ; - assign _dfoo333 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo197 ; - assign _dfoo334 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo266 ; - assign _dfoo335 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo199 ; - assign _dfoo336 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo268 ; - assign _dfoo337 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo201 ; - assign _dfoo338 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo270 ; - assign _dfoo339 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo203 ; - assign _dfoo34 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo340 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo272 ; - assign _dfoo342 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo274 ; - assign _dfoo344 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo276 ; - assign _dfoo346 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo278 ; - assign _dfoo348 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo280 ; - assign _dfoo35 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo350 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo282 ; - assign _dfoo352 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo284 ; - assign _dfoo354 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo286 ; - assign _dfoo356 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo288 ; - assign _dfoo358 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo290 ; - assign _dfoo36 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo360 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo292 ; - assign _dfoo362 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo294 ; - assign _dfoo364 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo296 ; - assign _dfoo366 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo298 ; - assign _dfoo368 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo300 ; - assign _dfoo37 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo370 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo302 ; - assign _dfoo372 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo304 ; - assign _dfoo374 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo306 ; - assign _dfoo376 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo308 ; - assign _dfoo378 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo310 ; - assign _dfoo38 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo380 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo312 ; - assign _dfoo382 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo314 ; - assign _dfoo384 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo316 ; - assign _dfoo386 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo318 ; - assign _dfoo388 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo320 ; - assign _dfoo39 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo390 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo322 ; - assign _dfoo392 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo324 ; - assign _dfoo394 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo326 ; - assign _dfoo396 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo328 ; - assign _dfoo398 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo330 ; - assign _dfoo4 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo40 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo400 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo332 ; - assign _dfoo402 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo334 ; - assign _dfoo404 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo336 ; - assign _dfoo406 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo338 ; - assign _dfoo408 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo340 ; - assign _dfoo409 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo273 ; - assign _dfoo41 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo410 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo342 ; - assign _dfoo411 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo275 ; - assign _dfoo412 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo344 ; - assign _dfoo413 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo277 ; - assign _dfoo414 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo346 ; - assign _dfoo415 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo279 ; - assign _dfoo416 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo348 ; - assign _dfoo417 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo281 ; - assign _dfoo418 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo350 ; - assign _dfoo419 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo283 ; - assign _dfoo42 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo420 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo352 ; - assign _dfoo421 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo285 ; - assign _dfoo422 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo354 ; - assign _dfoo423 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo287 ; - assign _dfoo424 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo356 ; - assign _dfoo425 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo289 ; - assign _dfoo426 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo358 ; - assign _dfoo427 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo291 ; - assign _dfoo428 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo360 ; - assign _dfoo429 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo293 ; - assign _dfoo43 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo430 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo362 ; - assign _dfoo431 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo295 ; - assign _dfoo432 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo364 ; - assign _dfoo433 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo297 ; - assign _dfoo434 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo366 ; - assign _dfoo435 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo299 ; - assign _dfoo436 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo368 ; - assign _dfoo437 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo301 ; - assign _dfoo438 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo370 ; - assign _dfoo439 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo303 ; - assign _dfoo44 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo440 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo372 ; - assign _dfoo441 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo305 ; - assign _dfoo442 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo374 ; - assign _dfoo443 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo307 ; - assign _dfoo444 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo376 ; - assign _dfoo445 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo309 ; - assign _dfoo446 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo378 ; - assign _dfoo447 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo311 ; - assign _dfoo448 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo380 ; - assign _dfoo449 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo313 ; - assign _dfoo45 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo450 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo382 ; - assign _dfoo451 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo315 ; - assign _dfoo452 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo384 ; - assign _dfoo453 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo317 ; - assign _dfoo454 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo386 ; - assign _dfoo455 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo319 ; - assign _dfoo456 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo388 ; - assign _dfoo457 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo321 ; - assign _dfoo458 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo390 ; - assign _dfoo459 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo323 ; - assign _dfoo46 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo460 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo392 ; - assign _dfoo461 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo325 ; - assign _dfoo462 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo394 ; - assign _dfoo463 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo327 ; - assign _dfoo464 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo396 ; - assign _dfoo465 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo329 ; - assign _dfoo466 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo398 ; - assign _dfoo467 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo331 ; - assign _dfoo468 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo400 ; - assign _dfoo469 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo333 ; - assign _dfoo47 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo470 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo402 ; - assign _dfoo471 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo335 ; - assign _dfoo472 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo404 ; - assign _dfoo473 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo337 ; - assign _dfoo474 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo406 ; - assign _dfoo475 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo339 ; - assign _dfoo476 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo408 ; - assign _dfoo478 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo410 ; - assign _dfoo48 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo480 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo412 ; - assign _dfoo482 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo414 ; - assign _dfoo484 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo416 ; - assign _dfoo486 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo418 ; - assign _dfoo488 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo420 ; - assign _dfoo49 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo490 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo422 ; - assign _dfoo492 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo424 ; - assign _dfoo494 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo426 ; - assign _dfoo496 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo428 ; - assign _dfoo498 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo430 ; - assign _dfoo5 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo50 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo500 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo432 ; - assign _dfoo502 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo434 ; - assign _dfoo504 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo436 ; - assign _dfoo506 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo438 ; - assign _dfoo508 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo440 ; - assign _dfoo51 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo510 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo442 ; - assign _dfoo512 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo444 ; - assign _dfoo514 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo446 ; - assign _dfoo516 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo448 ; - assign _dfoo518 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo450 ; - assign _dfoo52 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo520 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo452 ; - assign _dfoo522 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo454 ; - assign _dfoo524 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo456 ; - assign _dfoo526 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo458 ; - assign _dfoo528 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo460 ; - assign _dfoo53 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo530 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo462 ; - assign _dfoo532 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo464 ; - assign _dfoo534 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo466 ; - assign _dfoo536 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo468 ; - assign _dfoo538 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo470 ; - assign _dfoo54 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo540 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo472 ; - assign _dfoo542 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo474 ; - assign _dfoo544 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo476 ; - assign _dfoo545 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo409 ; - assign _dfoo546 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo478 ; - assign _dfoo547 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo411 ; - assign _dfoo548 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo480 ; - assign _dfoo549 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo413 ; - assign _dfoo55 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo550 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo482 ; - assign _dfoo551 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo415 ; - assign _dfoo552 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo484 ; - assign _dfoo553 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo417 ; - assign _dfoo554 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo486 ; - assign _dfoo555 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo419 ; - assign _dfoo556 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo488 ; - assign _dfoo557 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo421 ; - assign _dfoo558 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo490 ; - assign _dfoo559 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo423 ; - assign _dfoo56 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo560 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo492 ; - assign _dfoo561 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo425 ; - assign _dfoo562 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo494 ; - assign _dfoo563 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo427 ; - assign _dfoo564 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo496 ; - assign _dfoo565 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo429 ; - assign _dfoo566 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo498 ; - assign _dfoo567 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo431 ; - assign _dfoo568 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo500 ; - assign _dfoo569 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo433 ; - assign _dfoo57 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo570 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo502 ; - assign _dfoo571 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo435 ; - assign _dfoo572 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo504 ; - assign _dfoo573 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo437 ; - assign _dfoo574 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo506 ; - assign _dfoo575 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo439 ; - assign _dfoo576 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo508 ; - assign _dfoo577 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo441 ; - assign _dfoo578 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo510 ; - assign _dfoo579 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo443 ; - assign _dfoo58 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo580 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo512 ; - assign _dfoo581 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo445 ; - assign _dfoo582 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo514 ; - assign _dfoo583 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo447 ; - assign _dfoo584 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo516 ; - assign _dfoo585 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo449 ; - assign _dfoo586 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo518 ; - assign _dfoo587 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo451 ; - assign _dfoo588 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo520 ; - assign _dfoo589 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo453 ; - assign _dfoo59 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo590 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo522 ; - assign _dfoo591 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo455 ; - assign _dfoo592 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo524 ; - assign _dfoo593 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo457 ; - assign _dfoo594 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo526 ; - assign _dfoo595 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo459 ; - assign _dfoo596 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo528 ; - assign _dfoo597 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo461 ; - assign _dfoo598 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo530 ; - assign _dfoo599 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo463 ; - assign _dfoo6 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo60 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo600 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo532 ; - assign _dfoo601 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo465 ; - assign _dfoo602 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo534 ; - assign _dfoo603 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo467 ; - assign _dfoo604 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo536 ; - assign _dfoo605 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo469 ; - assign _dfoo606 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo538 ; - assign _dfoo607 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo471 ; - assign _dfoo608 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo540 ; - assign _dfoo609 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo473 ; - assign _dfoo61 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo610 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo542 ; - assign _dfoo611 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo475 ; - assign _dfoo612 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo544 ; - assign _dfoo614 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo546 ; - assign _dfoo616 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo548 ; - assign _dfoo618 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo550 ; - assign _dfoo62 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo620 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo552 ; - assign _dfoo622 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo554 ; - assign _dfoo624 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo556 ; - assign _dfoo626 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo558 ; - assign _dfoo628 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo560 ; - assign _dfoo63 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo630 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo562 ; - assign _dfoo632 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo564 ; - assign _dfoo634 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo566 ; - assign _dfoo636 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo568 ; - assign _dfoo638 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo570 ; - assign _dfoo64 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo640 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo572 ; - assign _dfoo642 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo574 ; - assign _dfoo644 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo576 ; - assign _dfoo646 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo578 ; - assign _dfoo648 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo580 ; - assign _dfoo65 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo650 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo582 ; - assign _dfoo652 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo584 ; - assign _dfoo654 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo586 ; - assign _dfoo656 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo588 ; - assign _dfoo658 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo590 ; - assign _dfoo66 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo660 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo592 ; - assign _dfoo662 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo594 ; - assign _dfoo664 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo596 ; - assign _dfoo666 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo598 ; - assign _dfoo668 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo600 ; - assign _dfoo67 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo670 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo602 ; - assign _dfoo672 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo604 ; - assign _dfoo674 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo606 ; - assign _dfoo676 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo608 ; - assign _dfoo678 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo610 ; - assign _dfoo68 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo680 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo612 ; - assign _dfoo681 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo545 ; - assign _dfoo682 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo614 ; - assign _dfoo683 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo547 ; - assign _dfoo684 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo616 ; - assign _dfoo685 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo549 ; - assign _dfoo686 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo618 ; - assign _dfoo687 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo551 ; - assign _dfoo688 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo620 ; - assign _dfoo689 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo553 ; - assign _dfoo690 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo622 ; - assign _dfoo691 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo555 ; - assign _dfoo692 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo624 ; - assign _dfoo693 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo557 ; - assign _dfoo694 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo626 ; - assign _dfoo695 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo559 ; - assign _dfoo696 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo628 ; - assign _dfoo697 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo561 ; - assign _dfoo698 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo630 ; - assign _dfoo699 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo563 ; - assign _dfoo7 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo70 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo2 ; - assign _dfoo700 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo632 ; - assign _dfoo701 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo565 ; - assign _dfoo702 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo634 ; - assign _dfoo703 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo567 ; - assign _dfoo704 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo636 ; - assign _dfoo705 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo569 ; - assign _dfoo706 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo638 ; - assign _dfoo707 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo571 ; - assign _dfoo708 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo640 ; - assign _dfoo709 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo573 ; - assign _dfoo710 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo642 ; - assign _dfoo711 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo575 ; - assign _dfoo712 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo644 ; - assign _dfoo713 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo577 ; - assign _dfoo714 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo646 ; - assign _dfoo715 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo579 ; - assign _dfoo716 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo648 ; - assign _dfoo717 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo581 ; - assign _dfoo718 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo650 ; - assign _dfoo719 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo583 ; - assign _dfoo72 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo4 ; - assign _dfoo720 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo652 ; - assign _dfoo721 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo585 ; - assign _dfoo722 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo654 ; - assign _dfoo723 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo587 ; - assign _dfoo724 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo656 ; - assign _dfoo725 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo589 ; - assign _dfoo726 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo658 ; - assign _dfoo727 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo591 ; - assign _dfoo728 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo660 ; - assign _dfoo729 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo593 ; - assign _dfoo730 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo662 ; - assign _dfoo731 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo595 ; - assign _dfoo732 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo664 ; - assign _dfoo733 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo597 ; - assign _dfoo734 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo666 ; - assign _dfoo735 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo599 ; - assign _dfoo736 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo668 ; - assign _dfoo737 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo601 ; - assign _dfoo738 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo670 ; - assign _dfoo739 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo603 ; - assign _dfoo74 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo6 ; - assign _dfoo740 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo672 ; - assign _dfoo741 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo605 ; - assign _dfoo742 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo674 ; - assign _dfoo743 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo607 ; - assign _dfoo744 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo676 ; - assign _dfoo745 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo609 ; - assign _dfoo746 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo678 ; - assign _dfoo747 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo611 ; - assign _dfoo748 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo680 ; - assign _dfoo750 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo682 ; - assign _dfoo752 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo684 ; - assign _dfoo754 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo686 ; - assign _dfoo756 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo688 ; - assign _dfoo758 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo690 ; - assign _dfoo76 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo8 ; - assign _dfoo760 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo692 ; - assign _dfoo762 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo694 ; - assign _dfoo764 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo696 ; - assign _dfoo766 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo698 ; - assign _dfoo768 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo700 ; - assign _dfoo770 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo702 ; - assign _dfoo772 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo704 ; - assign _dfoo774 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo706 ; - assign _dfoo776 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo708 ; - assign _dfoo778 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo710 ; - assign _dfoo78 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo10 ; - assign _dfoo780 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo712 ; - assign _dfoo782 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo714 ; - assign _dfoo784 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo716 ; - assign _dfoo786 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo718 ; - assign _dfoo788 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo720 ; - assign _dfoo790 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo722 ; - assign _dfoo792 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo724 ; - assign _dfoo794 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo726 ; - assign _dfoo796 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo728 ; - assign _dfoo798 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo730 ; - assign _dfoo8 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo80 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo12 ; - assign _dfoo800 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo732 ; - assign _dfoo802 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo734 ; - assign _dfoo804 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo736 ; - assign _dfoo806 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo738 ; - assign _dfoo808 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo740 ; - assign _dfoo810 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo742 ; - assign _dfoo812 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo744 ; - assign _dfoo814 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo746 ; - assign _dfoo816 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo748 ; - assign _dfoo817 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo681 ; - assign _dfoo818 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo750 ; - assign _dfoo819 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo683 ; - assign _dfoo82 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo14 ; - assign _dfoo820 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo752 ; - assign _dfoo821 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo685 ; - assign _dfoo822 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo754 ; - assign _dfoo823 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo687 ; - assign _dfoo824 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo756 ; - assign _dfoo825 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo689 ; - assign _dfoo826 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo758 ; - assign _dfoo827 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo691 ; - assign _dfoo828 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo760 ; - assign _dfoo829 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo693 ; - assign _dfoo830 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo762 ; - assign _dfoo831 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo695 ; - assign _dfoo832 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo764 ; - assign _dfoo833 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo697 ; - assign _dfoo834 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo766 ; - assign _dfoo835 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo699 ; - assign _dfoo836 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo768 ; - assign _dfoo837 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo701 ; - assign _dfoo838 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo770 ; - assign _dfoo839 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo703 ; - assign _dfoo84 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo16 ; - assign _dfoo840 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo772 ; - assign _dfoo841 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo705 ; - assign _dfoo842 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo774 ; - assign _dfoo843 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo707 ; - assign _dfoo844 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo776 ; - assign _dfoo845 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo709 ; - assign _dfoo846 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo778 ; - assign _dfoo847 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo711 ; - assign _dfoo848 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo780 ; - assign _dfoo849 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo713 ; - assign _dfoo850 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo782 ; - assign _dfoo851 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo715 ; - assign _dfoo852 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo784 ; - assign _dfoo853 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo717 ; - assign _dfoo854 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo786 ; - assign _dfoo855 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo719 ; - assign _dfoo856 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo788 ; - assign _dfoo857 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo721 ; - assign _dfoo858 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo790 ; - assign _dfoo859 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo723 ; - assign _dfoo86 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo18 ; - assign _dfoo860 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo792 ; - assign _dfoo861 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo725 ; - assign _dfoo862 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo794 ; - assign _dfoo863 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo727 ; - assign _dfoo864 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo796 ; - assign _dfoo865 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo729 ; - assign _dfoo866 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo798 ; - assign _dfoo867 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo731 ; - assign _dfoo868 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo800 ; - assign _dfoo869 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo733 ; - assign _dfoo870 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo802 ; - assign _dfoo871 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo735 ; - assign _dfoo872 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo804 ; - assign _dfoo873 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo737 ; - assign _dfoo874 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo806 ; - assign _dfoo875 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo739 ; - assign _dfoo876 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo808 ; - assign _dfoo877 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo741 ; - assign _dfoo878 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo810 ; - assign _dfoo879 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo743 ; - assign _dfoo88 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo20 ; - assign _dfoo880 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo812 ; - assign _dfoo881 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo745 ; - assign _dfoo882 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo814 ; - assign _dfoo883 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo747 ; - assign _dfoo884 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo816 ; - assign _dfoo886 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo818 ; - assign _dfoo888 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo820 ; - assign _dfoo890 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo822 ; - assign _dfoo892 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo824 ; - assign _dfoo894 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo826 ; - assign _dfoo896 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo828 ; - assign _dfoo898 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo830 ; - assign _dfoo9 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo90 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo22 ; - assign _dfoo900 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo832 ; - assign _dfoo902 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo834 ; - assign _dfoo904 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo836 ; - assign _dfoo906 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo838 ; - assign _dfoo908 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo840 ; - assign _dfoo910 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo842 ; - assign _dfoo912 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo844 ; - assign _dfoo914 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo846 ; - assign _dfoo916 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo848 ; - assign _dfoo918 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo850 ; - assign _dfoo92 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo24 ; - assign _dfoo920 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo852 ; - assign _dfoo922 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo854 ; - assign _dfoo924 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo856 ; - assign _dfoo926 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo858 ; - assign _dfoo928 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo860 ; - assign _dfoo930 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo862 ; - assign _dfoo932 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo864 ; - assign _dfoo934 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo866 ; - assign _dfoo936 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo868 ; - assign _dfoo938 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo870 ; - assign _dfoo94 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo26 ; - assign _dfoo940 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo872 ; - assign _dfoo942 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo874 ; - assign _dfoo944 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo876 ; - assign _dfoo946 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo878 ; - assign _dfoo948 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo880 ; - assign _dfoo950 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo882 ; - assign _dfoo952 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo884 ; - assign _dfoo953 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo817 ; - assign _dfoo954 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo886 ; - assign _dfoo955 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo819 ; - assign _dfoo956 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo888 ; - assign _dfoo957 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo821 ; - assign _dfoo958 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo890 ; - assign _dfoo959 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo823 ; - assign _dfoo96 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo28 ; - assign _dfoo960 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo892 ; - assign _dfoo961 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo825 ; - assign _dfoo962 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo894 ; - assign _dfoo963 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo827 ; - assign _dfoo964 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo896 ; - assign _dfoo965 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo829 ; - assign _dfoo966 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo898 ; - assign _dfoo967 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo831 ; - assign _dfoo968 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo900 ; - assign _dfoo969 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo833 ; - assign _dfoo970 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo902 ; - assign _dfoo971 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo835 ; - assign _dfoo972 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo904 ; - assign _dfoo973 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo837 ; - assign _dfoo974 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo906 ; - assign _dfoo975 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo839 ; - assign _dfoo976 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo908 ; - assign _dfoo977 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo841 ; - assign _dfoo978 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo910 ; - assign _dfoo979 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo843 ; - assign _dfoo98 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo30 ; - assign _dfoo980 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo912 ; - assign _dfoo981 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo845 ; - assign _dfoo982 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo914 ; - assign _dfoo983 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo847 ; - assign _dfoo984 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo916 ; - assign _dfoo985 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo849 ; - assign _dfoo986 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo918 ; - assign _dfoo987 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo851 ; - assign _dfoo988 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo920 ; - assign _dfoo989 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo853 ; - assign _dfoo990 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo922 ; - assign _dfoo991 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo855 ; - assign _dfoo992 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo924 ; - assign _dfoo993 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo857 ; - assign _dfoo994 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo926 ; - assign _dfoo995 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo859 ; - assign _dfoo996 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo928 ; - assign _dfoo997 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo861 ; - assign _dfoo998 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo930 ; - assign _dfoo999 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo863 ; - assign a__h71312 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73317 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; - assign addr_offset__h13216 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26929 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71313 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73318 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = - addr_offset__h13216 < 64'h0000000000003000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = - addr_offset__h13216[11:7] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 = - addr_offset__h13216 < 64'h0000000000001000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 = - addr_offset__h13216[11:2] <= 10'd16 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 = - addr_offset__h13216[16:12] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 = - addr_offset__h13216 < 64'h0000000000002000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = - source_id_base__h13630 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26929[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26929[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26929[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26929 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26929[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26929[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26929[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26929[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26929[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26929[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26929[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26929[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26929[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26929[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26929[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26929[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26929[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26929[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26929[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26929[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26929[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26929 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28148 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26929 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26929[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26929[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26929[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && - m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && - m_vvrg_ie_1_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && - m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && - m_vvrg_ie_1_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && - m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && - m_vvrg_ie_1_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && - m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && - m_vvrg_ie_1_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 || - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 || - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 || - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 || - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && - m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && - m_vvrg_ie_1_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && - m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && - m_vvrg_ie_1_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && - m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && - m_vvrg_ie_1_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = - m_vrg_source_ip_16 && - !m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 || - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 || - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 || - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 ; - assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = - m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && - m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && - m_vvrg_ie_1_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && - m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && - m_vvrg_ie_1_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && - m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && - m_vvrg_ie_1_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && - m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && - m_vvrg_ie_1_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && - m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && - m_vvrg_ie_1_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && - m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && - m_vvrg_ie_1_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 || - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 || - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 || - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 || - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && - m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && - m_vvrg_ie_1_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && - m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && - m_vvrg_ie_1_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; - assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 = - m_vrg_source_prio_16 <= - (m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ; - assign max_id__h23959 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ; - assign rdata___1__h26404 = { rdata__h26202[31:0], 32'h0 } ; - assign rdata__h26202 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 64'd0 : - y_avValue_fst__h26194 ; - assign rresp__h26203 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 2'b11 : - y_avValue_snd__h26195 ; - assign source_id__h15665 = { addr_offset__h13216[4:0], 5'd31 } ; - assign source_id__h15772 = { addr_offset__h13216[4:0], 5'd30 } ; - assign source_id__h15845 = { addr_offset__h13216[4:0], 5'd29 } ; - assign source_id__h15918 = { addr_offset__h13216[4:0], 5'd28 } ; - assign source_id__h15991 = { addr_offset__h13216[4:0], 5'd27 } ; - assign source_id__h16064 = { addr_offset__h13216[4:0], 5'd26 } ; - assign source_id__h16137 = { addr_offset__h13216[4:0], 5'd25 } ; - assign source_id__h16210 = { addr_offset__h13216[4:0], 5'd24 } ; - assign source_id__h16283 = { addr_offset__h13216[4:0], 5'd23 } ; - assign source_id__h16356 = { addr_offset__h13216[4:0], 5'd22 } ; - assign source_id__h16429 = { addr_offset__h13216[4:0], 5'd21 } ; - assign source_id__h16502 = { addr_offset__h13216[4:0], 5'd20 } ; - assign source_id__h16575 = { addr_offset__h13216[4:0], 5'd19 } ; - assign source_id__h16648 = { addr_offset__h13216[4:0], 5'd18 } ; - assign source_id__h16721 = { addr_offset__h13216[4:0], 5'd17 } ; - assign source_id__h16794 = { addr_offset__h13216[4:0], 5'd16 } ; - assign source_id__h16867 = { addr_offset__h13216[4:0], 5'd15 } ; - assign source_id__h16940 = { addr_offset__h13216[4:0], 5'd14 } ; - assign source_id__h17013 = { addr_offset__h13216[4:0], 5'd13 } ; - assign source_id__h17086 = { addr_offset__h13216[4:0], 5'd12 } ; - assign source_id__h17159 = { addr_offset__h13216[4:0], 5'd11 } ; - assign source_id__h17232 = { addr_offset__h13216[4:0], 5'd10 } ; - assign source_id__h17305 = { addr_offset__h13216[4:0], 5'd9 } ; - assign source_id__h17378 = { addr_offset__h13216[4:0], 5'd8 } ; - assign source_id__h17451 = { addr_offset__h13216[4:0], 5'd7 } ; - assign source_id__h17524 = { addr_offset__h13216[4:0], 5'd6 } ; - assign source_id__h17597 = { addr_offset__h13216[4:0], 5'd5 } ; - assign source_id__h17670 = { addr_offset__h13216[4:0], 5'd4 } ; - assign source_id__h17743 = { addr_offset__h13216[4:0], 5'd3 } ; - assign source_id__h17816 = { addr_offset__h13216[4:0], 5'd2 } ; - assign source_id__h17889 = { addr_offset__h13216[4:0], 5'd1 } ; - assign source_id__h20137 = 10'd31 + source_id_base__h13630 ; - assign source_id__h20313 = 10'd30 + source_id_base__h13630 ; - assign source_id__h20421 = 10'd29 + source_id_base__h13630 ; - assign source_id__h20529 = 10'd28 + source_id_base__h13630 ; - assign source_id__h20637 = 10'd27 + source_id_base__h13630 ; - assign source_id__h20745 = 10'd26 + source_id_base__h13630 ; - assign source_id__h20853 = 10'd25 + source_id_base__h13630 ; - assign source_id__h20961 = 10'd24 + source_id_base__h13630 ; - assign source_id__h21069 = 10'd23 + source_id_base__h13630 ; - assign source_id__h21177 = 10'd22 + source_id_base__h13630 ; - assign source_id__h21285 = 10'd21 + source_id_base__h13630 ; - assign source_id__h21393 = 10'd20 + source_id_base__h13630 ; - assign source_id__h21501 = 10'd19 + source_id_base__h13630 ; - assign source_id__h21609 = 10'd18 + source_id_base__h13630 ; - assign source_id__h21717 = 10'd17 + source_id_base__h13630 ; - assign source_id__h21825 = 10'd16 + source_id_base__h13630 ; - assign source_id__h21933 = 10'd15 + source_id_base__h13630 ; - assign source_id__h22041 = 10'd14 + source_id_base__h13630 ; - assign source_id__h22149 = 10'd13 + source_id_base__h13630 ; - assign source_id__h22257 = 10'd12 + source_id_base__h13630 ; - assign source_id__h22365 = 10'd11 + source_id_base__h13630 ; - assign source_id__h22473 = 10'd10 + source_id_base__h13630 ; - assign source_id__h22581 = 10'd9 + source_id_base__h13630 ; - assign source_id__h22689 = 10'd8 + source_id_base__h13630 ; - assign source_id__h22797 = 10'd7 + source_id_base__h13630 ; - assign source_id__h22905 = 10'd6 + source_id_base__h13630 ; - assign source_id__h23013 = 10'd5 + source_id_base__h13630 ; - assign source_id__h23121 = 10'd4 + source_id_base__h13630 ; - assign source_id__h23229 = 10'd3 + source_id_base__h13630 ; - assign source_id__h23337 = 10'd2 + source_id_base__h13630 ; - assign source_id__h23445 = 10'd1 + source_id_base__h13630 ; - assign source_id__h29475 = { addr_offset__h26929[4:0], 5'd1 } ; - assign source_id__h30685 = { addr_offset__h26929[4:0], 5'd2 } ; - assign source_id__h31895 = { addr_offset__h26929[4:0], 5'd3 } ; - assign source_id__h33105 = { addr_offset__h26929[4:0], 5'd4 } ; - assign source_id__h34315 = { addr_offset__h26929[4:0], 5'd5 } ; - assign source_id__h35525 = { addr_offset__h26929[4:0], 5'd6 } ; - assign source_id__h36735 = { addr_offset__h26929[4:0], 5'd7 } ; - assign source_id__h37945 = { addr_offset__h26929[4:0], 5'd8 } ; - assign source_id__h39155 = { addr_offset__h26929[4:0], 5'd9 } ; - assign source_id__h40365 = { addr_offset__h26929[4:0], 5'd10 } ; - assign source_id__h41575 = { addr_offset__h26929[4:0], 5'd11 } ; - assign source_id__h42785 = { addr_offset__h26929[4:0], 5'd12 } ; - assign source_id__h43995 = { addr_offset__h26929[4:0], 5'd13 } ; - assign source_id__h45205 = { addr_offset__h26929[4:0], 5'd14 } ; - assign source_id__h46415 = { addr_offset__h26929[4:0], 5'd15 } ; - assign source_id__h47625 = { addr_offset__h26929[4:0], 5'd16 } ; - assign source_id__h48835 = { addr_offset__h26929[4:0], 5'd17 } ; - assign source_id__h50045 = { addr_offset__h26929[4:0], 5'd18 } ; - assign source_id__h51255 = { addr_offset__h26929[4:0], 5'd19 } ; - assign source_id__h52465 = { addr_offset__h26929[4:0], 5'd20 } ; - assign source_id__h53675 = { addr_offset__h26929[4:0], 5'd21 } ; - assign source_id__h54885 = { addr_offset__h26929[4:0], 5'd22 } ; - assign source_id__h56095 = { addr_offset__h26929[4:0], 5'd23 } ; - assign source_id__h57305 = { addr_offset__h26929[4:0], 5'd24 } ; - assign source_id__h58515 = { addr_offset__h26929[4:0], 5'd25 } ; - assign source_id__h59725 = { addr_offset__h26929[4:0], 5'd26 } ; - assign source_id__h60935 = { addr_offset__h26929[4:0], 5'd27 } ; - assign source_id__h62145 = { addr_offset__h26929[4:0], 5'd28 } ; - assign source_id__h63355 = { addr_offset__h26929[4:0], 5'd29 } ; - assign source_id__h64565 = { addr_offset__h26929[4:0], 5'd30 } ; - assign source_id__h65775 = { addr_offset__h26929[4:0], 5'd31 } ; - assign source_id__h67436 = { 5'd0, x__h67487 } ; - assign source_id_base__h13630 = { addr_offset__h13216[4:0], 5'h0 } ; - assign source_id_base__h28148 = { addr_offset__h26929[4:0], 5'h0 } ; - assign v__h13422 = { 61'd0, x__h13493 } ; - assign v__h13671 = { 32'd0, v_ip__h13674 } ; - assign v__h18144 = { 32'd0, v_ie__h18147 } ; - assign v__h23761 = { 61'd0, x__h23832 } ; - assign v__h25455 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ? - v__h25474 : - 64'd0 ; - assign v__h25474 = { 59'd0, max_id__h23959 } ; - assign v__h26934 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? - 2'b11 : - v__h27094 ; - assign v__h27094 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27107 : - v__h27942 ; - assign v__h27107 = - (addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? - 2'b0 : - 2'b10 ; - assign v__h27942 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27961 : - v__h28125 ; - assign v__h27961 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? - 2'b0 : - 2'b10 ; - assign v__h28125 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28144 : - v__h67107 ; - assign v__h28144 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? - 2'b0 : - 2'b10 ; - assign v__h67144 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - 2'b0 : - 2'b10 ; - assign v__h67432 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67476 : - 2'b10 ; - assign v__h67476 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? - 2'b0 : - 2'b10 ; - assign v_ie__h18147 = - { source_id__h20137 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h20313 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h20421 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h20529 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h20637 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h20745 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h20853 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h20961 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h21069 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h21177 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h21285 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h21393 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h21501 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h21609 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h21717 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h21825 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h21933 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h22041 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h22149 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h22257 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h22365 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h22473 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h22581 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h22689 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h22797 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h22905 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h23013 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h23121 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h23229 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h23337 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h23445 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h13674 = - { source_id__h15665 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - source_id__h15772 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - source_id__h15845 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - source_id__h15918 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - source_id__h15991 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - source_id__h16064 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - source_id__h16137 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - source_id__h16210 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - source_id__h16283 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - source_id__h16356 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - source_id__h16429 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - source_id__h16502 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - source_id__h16575 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - source_id__h16648 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - source_id__h16721 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - source_id__h16794 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - source_id__h16867 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - source_id__h16940 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - source_id__h17013 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - source_id__h17086 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - source_id__h17159 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - source_id__h17232 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - source_id__h17305 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - source_id__h17378 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - source_id__h17451 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - source_id__h17524 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - source_id__h17597 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - source_id__h17670 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - source_id__h17743 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - source_id__h17816 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - source_id__h17889 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26930 = - (addr_offset__h26929[2:0] == 3'd4) ? - m_slave_xactor_f_wr_data$D_OUT[72:41] : - m_slave_xactor_f_wr_data$D_OUT[40:9] ; - assign x__h23673 = - { addr_offset__h13216[31:16], 4'd0, addr_offset__h13216[11:0] } ; - assign x__h26361 = - (addr_offset__h13216[2:0] == 3'd4) ? - rdata___1__h26404 : - rdata__h26202 ; - assign x__h67110 = - { addr_offset__h26929[31:16], 4'd0, addr_offset__h26929[11:0] } ; - assign y_avValue_fst__h26094 = (x__h24011 == 5'd0) ? v__h25455 : 64'd0 ; - assign y_avValue_fst__h26115 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_fst__h26094 : - 64'd0 ; - assign y_avValue_fst__h26127 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - v__h23761 : - 64'd0 ; - assign y_avValue_fst__h26143 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - v__h18144 : - 64'd0 ; - assign y_avValue_fst__h26159 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - v__h13671 : - 64'd0 ; - assign y_avValue_fst__h26164 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_fst__h26143 : - y_avValue_fst__h26148 ; - assign y_avValue_fst__h26175 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - v__h13422 : - 64'd0 ; - assign y_avValue_fst__h26180 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_fst__h26159 : - y_avValue_fst__h26164 ; - assign y_avValue_fst__h26194 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_fst__h26175 : - y_avValue_fst__h26180 ; - assign y_avValue_snd__h26095 = (x__h24011 == 5'd0) ? 2'b0 : 2'b10 ; - assign y_avValue_snd__h26116 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_snd__h26095 : - 2'b10 ; - assign y_avValue_snd__h26128 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26144 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26160 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26165 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_snd__h26144 : - y_avValue_snd__h26149 ; - assign y_avValue_snd__h26176 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26181 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_snd__h26160 : - y_avValue_snd__h26165 ; - assign y_avValue_snd__h26195 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_snd__h26176 : - y_avValue_snd__h26181 ; - always@(addr_offset__h13216 or - m_vrg_source_prio_0 or - m_vrg_source_prio_1 or - m_vrg_source_prio_2 or - m_vrg_source_prio_3 or - m_vrg_source_prio_4 or - m_vrg_source_prio_5 or - m_vrg_source_prio_6 or - m_vrg_source_prio_7 or - m_vrg_source_prio_8 or - m_vrg_source_prio_9 or - m_vrg_source_prio_10 or - m_vrg_source_prio_11 or - m_vrg_source_prio_12 or - m_vrg_source_prio_13 or - m_vrg_source_prio_14 or - m_vrg_source_prio_15 or m_vrg_source_prio_16) - begin - case (addr_offset__h13216[11:2]) - 10'd0: x__h13493 = m_vrg_source_prio_0; - 10'd1: x__h13493 = m_vrg_source_prio_1; - 10'd2: x__h13493 = m_vrg_source_prio_2; - 10'd3: x__h13493 = m_vrg_source_prio_3; - 10'd4: x__h13493 = m_vrg_source_prio_4; - 10'd5: x__h13493 = m_vrg_source_prio_5; - 10'd6: x__h13493 = m_vrg_source_prio_6; - 10'd7: x__h13493 = m_vrg_source_prio_7; - 10'd8: x__h13493 = m_vrg_source_prio_8; - 10'd9: x__h13493 = m_vrg_source_prio_9; - 10'd10: x__h13493 = m_vrg_source_prio_10; - 10'd11: x__h13493 = m_vrg_source_prio_11; - 10'd12: x__h13493 = m_vrg_source_prio_12; - 10'd13: x__h13493 = m_vrg_source_prio_13; - 10'd14: x__h13493 = m_vrg_source_prio_14; - 10'd15: x__h13493 = m_vrg_source_prio_15; - 10'd16: x__h13493 = m_vrg_source_prio_16; - default: x__h13493 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_target_threshold_0 or m_vrg_target_threshold_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h23832 = m_vrg_target_threshold_0; - 5'd1: x__h23832 = m_vrg_target_threshold_1; - default: x__h23832 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h24011 = m_vrg_servicing_source_0; - 5'd1: x__h24011 = m_vrg_servicing_source_1; - default: x__h24011 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h26929 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h26929[16:12]) - 5'd0: x__h67487 = m_vrg_servicing_source_0; - 5'd1: x__h67487 = m_vrg_servicing_source_1; - default: x__h67487 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15665 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15665) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15772 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15772) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15845 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15845) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15918 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15918) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15991 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15991) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16064 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16064) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17159 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17159) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16137 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16137) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16210 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16210) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16283 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16283) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16356 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16356) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16429 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16429) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16502 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16502) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16575 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16575) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16648 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16648) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16721 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16721) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16794 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16794) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16867 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16867) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16940 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16940) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17013 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17013) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17086 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17086) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17232 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17232) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17305 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17305) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17378 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17378) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17451 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17451) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17524 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17524) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17597 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17597) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17670 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17670) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17743 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17743) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17889 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17889) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17816 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17816) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_snd__h26128 or y_avValue_snd__h26116) - begin - case (x__h23673) - 32'h00200000: y_avValue_snd__h26149 = y_avValue_snd__h26128; - 32'h00200004: y_avValue_snd__h26149 = y_avValue_snd__h26116; - default: y_avValue_snd__h26149 = 2'b10; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_0_1; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_1_1; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_0_2; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_1_2; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_0_3; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_1_3; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_0_4; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_1_4; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_0_5; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_1_5; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_0_6; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_1_6; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_0_7; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_1_7; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_0_8; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_1_8; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_0_9; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_1_9; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_0_10; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_1_10; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_0_11; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_1_11; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_0_12; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_1_12; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_0_13; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_1_13; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_0_14; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_1_14; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_0_15; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_1_15; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_0_16; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_1_16; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_fst__h26127 or y_avValue_fst__h26115) - begin - case (x__h23673) - 32'h00200000: y_avValue_fst__h26148 = y_avValue_fst__h26127; - 32'h00200004: y_avValue_fst__h26148 = y_avValue_fst__h26115; - default: y_avValue_fst__h26148 = 64'd0; - endcase - end - always@(source_id__h67436 or - m_vrg_source_busy_0 or - m_vrg_source_busy_1 or - m_vrg_source_busy_2 or - m_vrg_source_busy_3 or - m_vrg_source_busy_4 or - m_vrg_source_busy_5 or - m_vrg_source_busy_6 or - m_vrg_source_busy_7 or - m_vrg_source_busy_8 or - m_vrg_source_busy_9 or - m_vrg_source_busy_10 or - m_vrg_source_busy_11 or - m_vrg_source_busy_12 or - m_vrg_source_busy_13 or - m_vrg_source_busy_14 or - m_vrg_source_busy_15 or m_vrg_source_busy_16) - begin - case (source_id__h67436) - 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_0; - 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_1; - 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_2; - 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_3; - 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_4; - 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_5; - 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_6; - 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_7; - 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_8; - 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_9; - 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_10; - 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_11; - 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_12; - 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_13; - 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_14; - 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_15; - 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h67110 or v__h67144 or v__h67432) - begin - case (x__h67110) - 32'h00200000: v__h67107 = v__h67144; - 32'h00200004: v__h67107 = v__h67432; - default: v__h67107 = 2'b10; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_cfg_verbosity$EN) - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN; - if (m_vrg_servicing_source_0$EN) - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_0$D_IN; - if (m_vrg_servicing_source_1$EN) - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_1$D_IN; - if (m_vrg_source_busy_0$EN) - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_0$D_IN; - if (m_vrg_source_busy_1$EN) - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_1$D_IN; - if (m_vrg_source_busy_10$EN) - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_10$D_IN; - if (m_vrg_source_busy_11$EN) - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_11$D_IN; - if (m_vrg_source_busy_12$EN) - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_12$D_IN; - if (m_vrg_source_busy_13$EN) - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_13$D_IN; - if (m_vrg_source_busy_14$EN) - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_14$D_IN; - if (m_vrg_source_busy_15$EN) - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_15$D_IN; - if (m_vrg_source_busy_16$EN) - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_16$D_IN; - if (m_vrg_source_busy_2$EN) - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_2$D_IN; - if (m_vrg_source_busy_3$EN) - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_3$D_IN; - if (m_vrg_source_busy_4$EN) - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_4$D_IN; - if (m_vrg_source_busy_5$EN) - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_5$D_IN; - if (m_vrg_source_busy_6$EN) - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_6$D_IN; - if (m_vrg_source_busy_7$EN) - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_7$D_IN; - if (m_vrg_source_busy_8$EN) - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_8$D_IN; - if (m_vrg_source_busy_9$EN) - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_9$D_IN; - if (m_vrg_source_ip_0$EN) - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_0$D_IN; - if (m_vrg_source_ip_1$EN) - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_1$D_IN; - if (m_vrg_source_ip_10$EN) - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_10$D_IN; - if (m_vrg_source_ip_11$EN) - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_11$D_IN; - if (m_vrg_source_ip_12$EN) - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_12$D_IN; - if (m_vrg_source_ip_13$EN) - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_13$D_IN; - if (m_vrg_source_ip_14$EN) - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_14$D_IN; - if (m_vrg_source_ip_15$EN) - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_15$D_IN; - if (m_vrg_source_ip_16$EN) - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_16$D_IN; - if (m_vrg_source_ip_2$EN) - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_2$D_IN; - if (m_vrg_source_ip_3$EN) - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_3$D_IN; - if (m_vrg_source_ip_4$EN) - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_4$D_IN; - if (m_vrg_source_ip_5$EN) - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_5$D_IN; - if (m_vrg_source_ip_6$EN) - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_6$D_IN; - if (m_vrg_source_ip_7$EN) - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_7$D_IN; - if (m_vrg_source_ip_8$EN) - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_8$D_IN; - if (m_vrg_source_ip_9$EN) - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_9$D_IN; - if (m_vrg_source_prio_0$EN) - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_0$D_IN; - if (m_vrg_source_prio_1$EN) - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_1$D_IN; - if (m_vrg_source_prio_10$EN) - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_10$D_IN; - if (m_vrg_source_prio_11$EN) - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_11$D_IN; - if (m_vrg_source_prio_12$EN) - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_12$D_IN; - if (m_vrg_source_prio_13$EN) - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_13$D_IN; - if (m_vrg_source_prio_14$EN) - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_14$D_IN; - if (m_vrg_source_prio_15$EN) - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_15$D_IN; - if (m_vrg_source_prio_16$EN) - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_16$D_IN; - if (m_vrg_source_prio_2$EN) - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_2$D_IN; - if (m_vrg_source_prio_3$EN) - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_3$D_IN; - if (m_vrg_source_prio_4$EN) - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_4$D_IN; - if (m_vrg_source_prio_5$EN) - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_5$D_IN; - if (m_vrg_source_prio_6$EN) - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_6$D_IN; - if (m_vrg_source_prio_7$EN) - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_7$D_IN; - if (m_vrg_source_prio_8$EN) - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_8$D_IN; - if (m_vrg_source_prio_9$EN) - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_9$D_IN; - if (m_vrg_target_threshold_0$EN) - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_0$D_IN; - if (m_vrg_target_threshold_1$EN) - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_1$D_IN; - if (m_vvrg_ie_0_0$EN) - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_0$D_IN; - if (m_vvrg_ie_0_1$EN) - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_1$D_IN; - if (m_vvrg_ie_0_10$EN) - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_10$D_IN; - if (m_vvrg_ie_0_11$EN) - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_11$D_IN; - if (m_vvrg_ie_0_12$EN) - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_12$D_IN; - if (m_vvrg_ie_0_13$EN) - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_13$D_IN; - if (m_vvrg_ie_0_14$EN) - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_14$D_IN; - if (m_vvrg_ie_0_15$EN) - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_15$D_IN; - if (m_vvrg_ie_0_16$EN) - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_16$D_IN; - if (m_vvrg_ie_0_2$EN) - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_2$D_IN; - if (m_vvrg_ie_0_3$EN) - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_3$D_IN; - if (m_vvrg_ie_0_4$EN) - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_4$D_IN; - if (m_vvrg_ie_0_5$EN) - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_5$D_IN; - if (m_vvrg_ie_0_6$EN) - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_6$D_IN; - if (m_vvrg_ie_0_7$EN) - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_7$D_IN; - if (m_vvrg_ie_0_8$EN) - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_8$D_IN; - if (m_vvrg_ie_0_9$EN) - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_9$D_IN; - if (m_vvrg_ie_1_0$EN) - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_0$D_IN; - if (m_vvrg_ie_1_1$EN) - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_1$D_IN; - if (m_vvrg_ie_1_10$EN) - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_10$D_IN; - if (m_vvrg_ie_1_11$EN) - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_11$D_IN; - if (m_vvrg_ie_1_12$EN) - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_12$D_IN; - if (m_vvrg_ie_1_13$EN) - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_13$D_IN; - if (m_vvrg_ie_1_14$EN) - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_14$D_IN; - if (m_vvrg_ie_1_15$EN) - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_15$D_IN; - if (m_vvrg_ie_1_16$EN) - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_16$D_IN; - if (m_vvrg_ie_1_2$EN) - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_2$D_IN; - if (m_vvrg_ie_1_3$EN) - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_3$D_IN; - if (m_vvrg_ie_1_4$EN) - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_4$D_IN; - if (m_vvrg_ie_1_5$EN) - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_5$D_IN; - if (m_vvrg_ie_1_6$EN) - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_6$D_IN; - if (m_vvrg_ie_1_7$EN) - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_7$D_IN; - if (m_vvrg_ie_1_8$EN) - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_8$D_IN; - if (m_vvrg_ie_1_9$EN) - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_9$D_IN; - end - if (m_rg_addr_base$EN) - m_rg_addr_base <= `BSV_ASSIGNMENT_DELAY m_rg_addr_base$D_IN; - if (m_rg_addr_lim$EN) - m_rg_addr_lim <= `BSV_ASSIGNMENT_DELAY m_rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_cfg_verbosity = 4'hA; - m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - m_vrg_servicing_source_0 = 5'h0A; - m_vrg_servicing_source_1 = 5'h0A; - m_vrg_source_busy_0 = 1'h0; - m_vrg_source_busy_1 = 1'h0; - m_vrg_source_busy_10 = 1'h0; - m_vrg_source_busy_11 = 1'h0; - m_vrg_source_busy_12 = 1'h0; - m_vrg_source_busy_13 = 1'h0; - m_vrg_source_busy_14 = 1'h0; - m_vrg_source_busy_15 = 1'h0; - m_vrg_source_busy_16 = 1'h0; - m_vrg_source_busy_2 = 1'h0; - m_vrg_source_busy_3 = 1'h0; - m_vrg_source_busy_4 = 1'h0; - m_vrg_source_busy_5 = 1'h0; - m_vrg_source_busy_6 = 1'h0; - m_vrg_source_busy_7 = 1'h0; - m_vrg_source_busy_8 = 1'h0; - m_vrg_source_busy_9 = 1'h0; - m_vrg_source_ip_0 = 1'h0; - m_vrg_source_ip_1 = 1'h0; - m_vrg_source_ip_10 = 1'h0; - m_vrg_source_ip_11 = 1'h0; - m_vrg_source_ip_12 = 1'h0; - m_vrg_source_ip_13 = 1'h0; - m_vrg_source_ip_14 = 1'h0; - m_vrg_source_ip_15 = 1'h0; - m_vrg_source_ip_16 = 1'h0; - m_vrg_source_ip_2 = 1'h0; - m_vrg_source_ip_3 = 1'h0; - m_vrg_source_ip_4 = 1'h0; - m_vrg_source_ip_5 = 1'h0; - m_vrg_source_ip_6 = 1'h0; - m_vrg_source_ip_7 = 1'h0; - m_vrg_source_ip_8 = 1'h0; - m_vrg_source_ip_9 = 1'h0; - m_vrg_source_prio_0 = 3'h2; - m_vrg_source_prio_1 = 3'h2; - m_vrg_source_prio_10 = 3'h2; - m_vrg_source_prio_11 = 3'h2; - m_vrg_source_prio_12 = 3'h2; - m_vrg_source_prio_13 = 3'h2; - m_vrg_source_prio_14 = 3'h2; - m_vrg_source_prio_15 = 3'h2; - m_vrg_source_prio_16 = 3'h2; - m_vrg_source_prio_2 = 3'h2; - m_vrg_source_prio_3 = 3'h2; - m_vrg_source_prio_4 = 3'h2; - m_vrg_source_prio_5 = 3'h2; - m_vrg_source_prio_6 = 3'h2; - m_vrg_source_prio_7 = 3'h2; - m_vrg_source_prio_8 = 3'h2; - m_vrg_source_prio_9 = 3'h2; - m_vrg_target_threshold_0 = 3'h2; - m_vrg_target_threshold_1 = 3'h2; - m_vvrg_ie_0_0 = 1'h0; - m_vvrg_ie_0_1 = 1'h0; - m_vvrg_ie_0_10 = 1'h0; - m_vvrg_ie_0_11 = 1'h0; - m_vvrg_ie_0_12 = 1'h0; - m_vvrg_ie_0_13 = 1'h0; - m_vvrg_ie_0_14 = 1'h0; - m_vvrg_ie_0_15 = 1'h0; - m_vvrg_ie_0_16 = 1'h0; - m_vvrg_ie_0_2 = 1'h0; - m_vvrg_ie_0_3 = 1'h0; - m_vvrg_ie_0_4 = 1'h0; - m_vvrg_ie_0_5 = 1'h0; - m_vvrg_ie_0_6 = 1'h0; - m_vvrg_ie_0_7 = 1'h0; - m_vvrg_ie_0_8 = 1'h0; - m_vvrg_ie_0_9 = 1'h0; - m_vvrg_ie_1_0 = 1'h0; - m_vvrg_ie_1_1 = 1'h0; - m_vvrg_ie_1_10 = 1'h0; - m_vvrg_ie_1_11 = 1'h0; - m_vvrg_ie_1_12 = 1'h0; - m_vvrg_ie_1_13 = 1'h0; - m_vvrg_ie_1_14 = 1'h0; - m_vvrg_ie_1_15 = 1'h0; - m_vvrg_ie_1_16 = 1'h0; - m_vvrg_ie_1_2 = 1'h0; - m_vvrg_ie_1_3 = 1'h0; - m_vvrg_ie_1_4 = 1'h0; - m_vvrg_ie_1_5 = 1'h0; - m_vvrg_ie_1_6 = 1'h0; - m_vvrg_ie_1_7 = 1'h0; - m_vvrg_ie_1_8 = 1'h0; - m_vvrg_ie_1_9 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src IPs :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src Prios:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src busy :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71312, - m_vrg_target_threshold_0, - b__h71313, - m_vrg_servicing_source_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73317, - m_vrg_target_threshold_1, - b__h73318, - m_vrg_servicing_source_1); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - begin - v__h75676 = $stime; - #0; - end - v__h75670 = v__h75676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75670, - $signed(32'd1), - v_sources_0_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - begin - v__h75874 = $stime; - #0; - end - v__h75868 = v__h75874 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75868, - $signed(32'd2), - v_sources_1_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - begin - v__h76072 = $stime; - #0; - end - v__h76066 = v__h76072 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76066, - $signed(32'd3), - v_sources_2_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - begin - v__h76270 = $stime; - #0; - end - v__h76264 = v__h76270 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76264, - $signed(32'd4), - v_sources_3_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - begin - v__h76468 = $stime; - #0; - end - v__h76462 = v__h76468 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76462, - $signed(32'd5), - v_sources_4_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - begin - v__h76666 = $stime; - #0; - end - v__h76660 = v__h76666 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76660, - $signed(32'd6), - v_sources_5_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - begin - v__h76864 = $stime; - #0; - end - v__h76858 = v__h76864 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76858, - $signed(32'd7), - v_sources_6_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - begin - v__h77062 = $stime; - #0; - end - v__h77056 = v__h77062 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77056, - $signed(32'd8), - v_sources_7_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - begin - v__h77260 = $stime; - #0; - end - v__h77254 = v__h77260 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77254, - $signed(32'd9), - v_sources_8_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - begin - v__h77458 = $stime; - #0; - end - v__h77452 = v__h77458 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77452, - $signed(32'd10), - v_sources_9_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - begin - v__h77656 = $stime; - #0; - end - v__h77650 = v__h77656 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77650, - $signed(32'd11), - v_sources_10_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - begin - v__h77854 = $stime; - #0; - end - v__h77848 = v__h77854 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77848, - $signed(32'd12), - v_sources_11_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - begin - v__h78052 = $stime; - #0; - end - v__h78046 = v__h78052 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78046, - $signed(32'd13), - v_sources_12_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - begin - v__h78250 = $stime; - #0; - end - v__h78244 = v__h78250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78244, - $signed(32'd14), - v_sources_13_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - begin - v__h78448 = $stime; - #0; - end - v__h78442 = v__h78448 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78442, - $signed(32'd15), - v_sources_14_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - begin - v__h78646 = $stime; - #0; - end - v__h78640 = v__h78646 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78640, - $signed(32'd16), - v_sources_15_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - begin - v__h6144 = $stime; - #0; - end - v__h6138 = v__h6144 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h6138); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h13080 = $stime; - #0; - end - v__h13074 = v__h13080 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req:", v__h13074); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - begin - v__h13265 = $stime; - #0; - end - v__h13259 = v__h13265 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h13259); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - begin - v__h13463 = $stime; - #0; - end - v__h13457 = v__h13463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h13457, - addr_offset__h13216[11:2], - v__h13422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - begin - v__h13713 = $stime; - #0; - end - v__h13707 = v__h13713 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h13707, - source_id_base__h13630, - v__h13671); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - begin - v__h18186 = $stime; - #0; - end - v__h18180 = v__h18186 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h18180, - source_id_base__h13630, - v__h18144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - begin - v__h23802 = $stime; - #0; - end - v__h23796 = v__h23802 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h23796, - addr_offset__h13216[16:12], - v__h23761); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - begin - v__h25975 = $stime; - #0; - end - v__h25969 = v__h25975 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h25969, - addr_offset__h13216[16:12], - v__h25474); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - begin - v__h24056 = $stime; - #0; - end - v__h24050 = v__h24056 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h24050, - addr_offset__h13216[16:12]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Still servicing interrupt from source %0d", x__h24011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Trying to claim service for source %0d", - max_id__h23959); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Ignoring."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - begin - v__h26250 = $stime; - #0; - end - v__h26244 = v__h26250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h26244); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26463 = $stime; - #0; - end - v__h26457 = v__h26463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req", v__h26457); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", x__h26361); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", rresp__h26203); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26740 = $stime; - #0; - end - v__h26734 = v__h26740 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26734); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - begin - v__h26968 = $stime; - #0; - end - v__h26962 = v__h26968 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26962); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - begin - v__h27865 = $stime; - #0; - end - v__h27859 = v__h27865 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27859, - addr_offset__h26929[11:2], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - begin - v__h28048 = $stime; - #0; - end - v__h28042 = v__h28048 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28042, - source_id_base__h28148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - begin - v__h67030 = $stime; - #0; - end - v__h67024 = v__h67030 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67024, - addr_offset__h26929[11:7], - source_id_base__h28148, - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - begin - v__h67318 = $stime; - #0; - end - v__h67312 = v__h67318 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67312, - addr_offset__h26929[16:12], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - begin - v__h67847 = $stime; - #0; - end - v__h67841 = v__h67847 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67841, - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - begin - v__h67933 = $stime; - #0; - end - v__h67927 = v__h67933 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67927); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Completion message from target %0d to source %0d", - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Ignoring"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - begin - v__h68132 = $stime; - #0; - end - v__h68126 = v__h68132 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68126); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h68353 = $stime; - #0; - end - v__h68347 = v__h68353 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68347); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26934); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h74690 = $stime; - #0; - end - v__h74684 = v__h74690 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74684, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h74800 = $stime; - #0; - end - v__h74794 = v__h74800 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74794, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - begin - v__h74913 = $stime; - #0; - end - v__h74907 = v__h74913 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74907, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkPLIC_16_2_7 - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v deleted file mode 100644 index f852a5f3..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v +++ /dev/null @@ -1,734 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_req_reset O 1 const -// RDY_rsp_reset O 1 const -// valid O 1 -// word O 64 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_is_OP_not_OP_32 I 1 -// req_f3 I 3 -// req_v1 I 64 -// req_v2 I 64 -// EN_set_verbosity I 1 -// EN_req_reset I 1 unused -// EN_rsp_reset I 1 unused -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkRISCV_MBox(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_req_reset, - RDY_req_reset, - - EN_rsp_reset, - RDY_rsp_reset, - - req_is_OP_not_OP_32, - req_f3, - req_v1, - req_v2, - EN_req, - - valid, - - word); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method req_reset - input EN_req_reset; - output RDY_req_reset; - - // action method rsp_reset - input EN_rsp_reset; - output RDY_rsp_reset; - - // action method req - input req_is_OP_not_OP_32; - input [2 : 0] req_f3; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input EN_req; - - // value method valid - output valid; - - // value method word - output [63 : 0] word; - - // signals for module outputs - wire [63 : 0] word; - wire RDY_req_reset, RDY_rsp_reset, RDY_set_verbosity, valid; - - // inlined wires - wire dw_valid$whas; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register intDiv_rg_denom2 - reg [63 : 0] intDiv_rg_denom2; - reg [63 : 0] intDiv_rg_denom2$D_IN; - wire intDiv_rg_denom2$EN; - - // register intDiv_rg_denom_is_signed - reg intDiv_rg_denom_is_signed; - wire intDiv_rg_denom_is_signed$D_IN, intDiv_rg_denom_is_signed$EN; - - // register intDiv_rg_n - reg [63 : 0] intDiv_rg_n; - reg [63 : 0] intDiv_rg_n$D_IN; - wire intDiv_rg_n$EN; - - // register intDiv_rg_numer_is_signed - reg intDiv_rg_numer_is_signed; - wire intDiv_rg_numer_is_signed$D_IN, intDiv_rg_numer_is_signed$EN; - - // register intDiv_rg_quo - reg [63 : 0] intDiv_rg_quo; - reg [63 : 0] intDiv_rg_quo$D_IN; - wire intDiv_rg_quo$EN; - - // register intDiv_rg_quoIsNeg - reg intDiv_rg_quoIsNeg; - wire intDiv_rg_quoIsNeg$D_IN, intDiv_rg_quoIsNeg$EN; - - // register intDiv_rg_remIsNeg - reg intDiv_rg_remIsNeg; - wire intDiv_rg_remIsNeg$D_IN, intDiv_rg_remIsNeg$EN; - - // register intDiv_rg_state - reg [2 : 0] intDiv_rg_state; - reg [2 : 0] intDiv_rg_state$D_IN; - wire intDiv_rg_state$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_is_OP_not_OP_32 - reg rg_is_OP_not_OP_32; - wire rg_is_OP_not_OP_32$D_IN, rg_is_OP_not_OP_32$EN; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_v1 - reg [63 : 0] rg_v1; - reg [63 : 0] rg_v1$D_IN; - wire rg_v1$EN; - - // register rg_v2 - reg [63 : 0] rg_v2; - wire [63 : 0] rg_v2$D_IN; - wire rg_v2$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_intDiv_rl_loop1, - CAN_FIRE_RL_intDiv_rl_loop2, - CAN_FIRE_RL_intDiv_rl_start_div_by_zero, - CAN_FIRE_RL_intDiv_rl_start_overflow, - CAN_FIRE_RL_intDiv_rl_start_s, - CAN_FIRE_RL_rg_div_rem, - CAN_FIRE_RL_rl_mul, - CAN_FIRE_RL_rl_mul2, - CAN_FIRE_req, - CAN_FIRE_req_reset, - CAN_FIRE_rsp_reset, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_intDiv_rl_loop1, - WILL_FIRE_RL_intDiv_rl_loop2, - WILL_FIRE_RL_intDiv_rl_start_div_by_zero, - WILL_FIRE_RL_intDiv_rl_start_overflow, - WILL_FIRE_RL_intDiv_rl_start_s, - WILL_FIRE_RL_rg_div_rem, - WILL_FIRE_RL_rl_mul, - WILL_FIRE_RL_rl_mul2, - WILL_FIRE_req, - WILL_FIRE_req_reset, - WILL_FIRE_rsp_reset, - WILL_FIRE_set_verbosity; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_dw_result$wset_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_1, - MUX_intDiv_rg_denom2$write_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_3, - MUX_intDiv_rg_n$write_1__VAL_1, - MUX_intDiv_rg_n$write_1__VAL_2, - MUX_intDiv_rg_quo$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_2, - MUX_rg_v1$write_1__VAL_3, - MUX_rg_v1$write_1__VAL_4, - MUX_rg_v2$write_1__VAL_1; - wire [1 : 0] MUX_rg_state$write_1__VAL_1; - wire MUX_intDiv_rg_denom2$write_1__SEL_1, - MUX_intDiv_rg_denom2$write_1__SEL_2, - MUX_intDiv_rg_quo$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_2, - MUX_intDiv_rg_state$write_1__SEL_3, - MUX_rg_v1$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4706; - reg [31 : 0] v__h4700; - // synopsys translate_on - - // remaining internal signals - wire [255 : 0] SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118, - SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110, - _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115; - wire [127 : 0] SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125, - SEXT_rg_v1____d108, - rg_v1_MUL_rg_v2___d105, - v1__h4494; - wire [63 : 0] IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138, - _theResult___fst__h5162, - _theResult___fst__h5192, - _theResult___fst__h5218, - _theResult___fst__h787, - _theResult___snd__h5163, - _theResult___snd__h5193, - _theResult___snd__h5219, - _theResult___snd_fst__h782, - denom___1__h729, - numer___1__h728, - result___1__h4957, - v__h4418, - v__h4476, - v__h4527, - v__h4583, - v__h4600, - x__h3955, - x__h4041, - x__h4111, - x__h4126, - y__h3834; - wire [31 : 0] IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3, - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6, - req_v1_BITS_31_TO_0__q1, - req_v2_BITS_31_TO_0__q2, - rg_v1_BITS_31_TO_0__q4, - rg_v2_BITS_31_TO_0__q5; - wire IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39, - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47, - rg_v1_ULT_intDiv_rg_denom2_4___d59, - rg_v1_ULT_rg_v2___d55; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method req_reset - assign RDY_req_reset = 1'd1 ; - assign CAN_FIRE_req_reset = 1'd1 ; - assign WILL_FIRE_req_reset = EN_req_reset ; - - // action method rsp_reset - assign RDY_rsp_reset = 1'd1 ; - assign CAN_FIRE_rsp_reset = 1'd1 ; - assign WILL_FIRE_rsp_reset = EN_rsp_reset ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method word - assign word = WILL_FIRE_RL_rl_mul2 ? rg_v1 : MUX_dw_result$wset_1__VAL_2 ; - - // rule RL_rl_mul2 - assign CAN_FIRE_RL_rl_mul2 = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_mul2 = CAN_FIRE_RL_rl_mul2 ; - - // rule RL_rg_div_rem - assign CAN_FIRE_RL_rg_div_rem = - rg_state == 2'd2 && intDiv_rg_state == 3'd4 ; - assign WILL_FIRE_RL_rg_div_rem = CAN_FIRE_RL_rg_div_rem ; - - // rule RL_intDiv_rl_start_div_by_zero - assign CAN_FIRE_RL_intDiv_rl_start_div_by_zero = - intDiv_rg_state == 3'd1 && rg_v2 == 64'd0 ; - assign WILL_FIRE_RL_intDiv_rl_start_div_by_zero = - CAN_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // rule RL_intDiv_rl_start_overflow - assign CAN_FIRE_RL_intDiv_rl_start_overflow = - intDiv_rg_state == 3'd1 && intDiv_rg_numer_is_signed && - rg_v1 == 64'h8000000000000000 && - intDiv_rg_denom_is_signed && - rg_v2 == 64'hFFFFFFFFFFFFFFFF ; - assign WILL_FIRE_RL_intDiv_rl_start_overflow = - CAN_FIRE_RL_intDiv_rl_start_overflow && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_start_s - assign CAN_FIRE_RL_intDiv_rl_start_s = - intDiv_rg_state == 3'd1 && rg_v2 != 64'd0 && - (!intDiv_rg_numer_is_signed || rg_v1 != 64'h8000000000000000 || - !intDiv_rg_denom_is_signed || - rg_v2 != 64'hFFFFFFFFFFFFFFFF) ; - assign WILL_FIRE_RL_intDiv_rl_start_s = - CAN_FIRE_RL_intDiv_rl_start_s && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_loop1 - assign CAN_FIRE_RL_intDiv_rl_loop1 = intDiv_rg_state == 3'd2 ; - assign WILL_FIRE_RL_intDiv_rl_loop1 = CAN_FIRE_RL_intDiv_rl_loop1 ; - - // rule RL_rl_mul - assign CAN_FIRE_RL_rl_mul = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_mul = rg_state == 2'd0 ; - - // rule RL_intDiv_rl_loop2 - assign CAN_FIRE_RL_intDiv_rl_loop2 = intDiv_rg_state == 3'd3 ; - assign WILL_FIRE_RL_intDiv_rl_loop2 = - CAN_FIRE_RL_intDiv_rl_loop2 && !WILL_FIRE_RL_rl_mul ; - - // inputs to muxes for submodule ports - assign MUX_intDiv_rg_denom2$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ; - assign MUX_intDiv_rg_denom2$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 ; - assign MUX_intDiv_rg_quo$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_quoIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_intDiv_rg_state$write_1__SEL_1 = EN_req && req_f3[2] ; - assign MUX_intDiv_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 ; - assign MUX_intDiv_rg_state$write_1__SEL_3 = - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ; - assign MUX_rg_v1$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_remIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_dw_result$wset_1__VAL_2 = - rg_is_OP_not_OP_32 ? - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138 : - result___1__h4957 ; - assign MUX_intDiv_rg_denom2$write_1__VAL_1 = - { intDiv_rg_denom2[62:0], 1'd0 } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_2 = - { 1'd0, intDiv_rg_denom2[63:1] } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_3 = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - denom___1__h729 : - _theResult___snd_fst__h782 ; - assign MUX_intDiv_rg_n$write_1__VAL_1 = { intDiv_rg_n[62:0], 1'd0 } ; - assign MUX_intDiv_rg_n$write_1__VAL_2 = { 1'd0, intDiv_rg_n[63:1] } ; - assign MUX_intDiv_rg_quo$write_1__VAL_1 = - rg_v1_ULT_rg_v2___d55 ? x__h4041 : x__h4126 ; - assign MUX_rg_state$write_1__VAL_1 = req_f3[2] ? 2'd2 : 2'd0 ; - assign MUX_rg_v1$write_1__VAL_1 = - req_is_OP_not_OP_32 ? req_v1 : _theResult___fst__h5162 ; - assign MUX_rg_v1$write_1__VAL_2 = - rg_v1_ULT_rg_v2___d55 ? x__h4111 : x__h3955 ; - assign MUX_rg_v1$write_1__VAL_3 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - rg_v1_MUL_rg_v2___d105[63:0] : - v__h4418 ; - assign MUX_rg_v1$write_1__VAL_4 = - intDiv_rg_numer_is_signed ? numer___1__h728 : rg_v1 ; - assign MUX_rg_v2$write_1__VAL_1 = - req_is_OP_not_OP_32 ? req_v2 : _theResult___snd__h5163 ; - - // inlined wires - assign dw_valid$whas = WILL_FIRE_RL_rg_div_rem || WILL_FIRE_RL_rl_mul2 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register intDiv_rg_denom2 - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_denom2$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_denom2$write_1__VAL_2 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_intDiv_rg_denom2$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_3; - default: intDiv_rg_denom2$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_denom2$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_denom_is_signed - assign intDiv_rg_denom_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_denom_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_n - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_n$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_n$write_1__VAL_2 or WILL_FIRE_RL_intDiv_rl_start_s) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_n$D_IN = 64'd1; - default: intDiv_rg_n$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_n$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_numer_is_signed - assign intDiv_rg_numer_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_numer_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_quo - always@(MUX_intDiv_rg_quo$write_1__SEL_1 or - MUX_intDiv_rg_quo$write_1__VAL_1 or - WILL_FIRE_RL_intDiv_rl_start_overflow or - rg_v1 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_quo$write_1__SEL_1: - intDiv_rg_quo$D_IN = MUX_intDiv_rg_quo$write_1__VAL_1; - WILL_FIRE_RL_intDiv_rl_start_overflow: intDiv_rg_quo$D_IN = rg_v1; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_quo$D_IN = 64'd0; - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_quo$D_IN = 64'hFFFFFFFFFFFFFFFF; - default: intDiv_rg_quo$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_quo$EN = - MUX_intDiv_rg_quo$write_1__SEL_1 || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register intDiv_rg_quoIsNeg - assign intDiv_rg_quoIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[63] != rg_v2[63] : - IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39 ; - assign intDiv_rg_quoIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_remIsNeg - assign intDiv_rg_remIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[63] : - intDiv_rg_numer_is_signed && rg_v1[63] ; - assign intDiv_rg_remIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_state - always@(MUX_intDiv_rg_state$write_1__SEL_1 or - MUX_intDiv_rg_state$write_1__SEL_2 or - MUX_intDiv_rg_state$write_1__SEL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_overflow or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - case (1'b1) - MUX_intDiv_rg_state$write_1__SEL_1: intDiv_rg_state$D_IN = 3'd1; - MUX_intDiv_rg_state$write_1__SEL_2: intDiv_rg_state$D_IN = 3'd4; - MUX_intDiv_rg_state$write_1__SEL_3: intDiv_rg_state$D_IN = 3'd3; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_state$D_IN = 3'd2; - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_state$D_IN = 3'd4; - default: intDiv_rg_state$D_IN = 3'b010 /* unspecified value */ ; - endcase - assign intDiv_rg_state$EN = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 || - EN_req && req_f3[2] || - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_is_OP_not_OP_32 - assign rg_is_OP_not_OP_32$D_IN = req_is_OP_not_OP_32 ; - assign rg_is_OP_not_OP_32$EN = EN_req ; - - // register rg_state - assign rg_state$D_IN = EN_req ? MUX_rg_state$write_1__VAL_1 : 2'd1 ; - assign rg_state$EN = EN_req || WILL_FIRE_RL_rl_mul ; - - // register rg_v1 - always@(EN_req or - MUX_rg_v1$write_1__VAL_1 or - MUX_rg_v1$write_1__SEL_2 or - MUX_rg_v1$write_1__VAL_2 or - WILL_FIRE_RL_rl_mul or - MUX_rg_v1$write_1__VAL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_rg_v1$write_1__VAL_4 or WILL_FIRE_RL_intDiv_rl_start_overflow) - case (1'b1) - EN_req: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_1; - MUX_rg_v1$write_1__SEL_2: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_2; - WILL_FIRE_RL_rl_mul: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_3; - WILL_FIRE_RL_intDiv_rl_start_s: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_4; - WILL_FIRE_RL_intDiv_rl_start_overflow: rg_v1$D_IN = 64'd0; - default: rg_v1$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign rg_v1$EN = - MUX_rg_v1$write_1__SEL_2 || WILL_FIRE_RL_rl_mul || EN_req || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow ; - - // register rg_v2 - assign rg_v2$D_IN = - EN_req ? - MUX_rg_v2$write_1__VAL_1 : - MUX_intDiv_rg_denom2$write_1__VAL_3 ; - assign rg_v2$EN = EN_req || WILL_FIRE_RL_intDiv_rl_start_s ; - - // remaining internal signals - assign IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39 = - intDiv_rg_numer_is_signed ? - rg_v1[63] : - intDiv_rg_denom_is_signed && rg_v2[63] ; - assign IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138 = - rg_f3[1] ? rg_v1 : intDiv_rg_quo ; - assign IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3 = - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138[31:0] ; - assign SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125 = - { {32{rg_v1_BITS_31_TO_0__q4[31]}}, rg_v1_BITS_31_TO_0__q4 } * - { {32{rg_v2_BITS_31_TO_0__q5[31]}}, rg_v2_BITS_31_TO_0__q5 } ; - assign SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6 = - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125[31:0] ; - assign SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118 = - SEXT_rg_v1____d108 * { 64'd0, rg_v2 } ; - assign SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110 = - SEXT_rg_v1____d108 * { {64{rg_v2[63]}}, rg_v2 } ; - assign SEXT_rg_v1____d108 = { {64{rg_v1[63]}}, rg_v1 } ; - assign _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115 = - v1__h4494 * { 64'd0, rg_v2 } ; - assign _theResult___fst__h5162 = - req_f3[0] ? _theResult___fst__h5218 : _theResult___fst__h5192 ; - assign _theResult___fst__h5192 = - { {32{req_v1_BITS_31_TO_0__q1[31]}}, req_v1_BITS_31_TO_0__q1 } ; - assign _theResult___fst__h5218 = { 32'd0, req_v1[31:0] } ; - assign _theResult___fst__h787 = - intDiv_rg_denom_is_signed ? denom___1__h729 : rg_v2 ; - assign _theResult___snd__h5163 = - req_f3[0] ? _theResult___snd__h5219 : _theResult___snd__h5193 ; - assign _theResult___snd__h5193 = - { {32{req_v2_BITS_31_TO_0__q2[31]}}, req_v2_BITS_31_TO_0__q2 } ; - assign _theResult___snd__h5219 = { 32'd0, req_v2[31:0] } ; - assign _theResult___snd_fst__h782 = - intDiv_rg_numer_is_signed ? rg_v2 : _theResult___fst__h787 ; - assign denom___1__h729 = rg_v2[63] ? -rg_v2 : rg_v2 ; - assign intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 = - intDiv_rg_denom2 <= y__h3834 ; - assign numer___1__h728 = rg_v1[63] ? x__h4111 : rg_v1 ; - assign req_v1_BITS_31_TO_0__q1 = req_v1[31:0] ; - assign req_v2_BITS_31_TO_0__q2 = req_v2[31:0] ; - assign result___1__h4957 = - { {32{IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3[31]}}, - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3 } ; - assign rg_v1_BITS_31_TO_0__q4 = rg_v1[31:0] ; - assign rg_v1_MUL_rg_v2___d105 = rg_v1 * rg_v2 ; - assign rg_v1_ULT_intDiv_rg_denom2_4___d59 = rg_v1 < intDiv_rg_denom2 ; - assign rg_v1_ULT_rg_v2___d55 = rg_v1 < rg_v2 ; - assign rg_v2_BITS_31_TO_0__q5 = rg_v2[31:0] ; - assign v1__h4494 = { 64'd0, rg_v1 } ; - assign v__h4418 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b001) ? - SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110[127:64] : - v__h4476 ; - assign v__h4476 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b011) ? - _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115[127:64] : - v__h4527 ; - assign v__h4527 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b010) ? - SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118[127:64] : - v__h4583 ; - assign v__h4583 = - (!rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - v__h4600 : - 64'hFFFFFFFFFFFFFFFF ; - assign v__h4600 = - { {32{SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6[31]}}, - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6 } ; - assign x__h3955 = rg_v1 - intDiv_rg_denom2 ; - assign x__h4041 = -intDiv_rg_quo ; - assign x__h4111 = -rg_v1 ; - assign x__h4126 = intDiv_rg_quo + intDiv_rg_n ; - assign y__h3834 = { 1'd0, rg_v1[63:1] } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (intDiv_rg_state$EN) - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY intDiv_rg_state$D_IN; - end - if (intDiv_rg_denom2$EN) - intDiv_rg_denom2 <= `BSV_ASSIGNMENT_DELAY intDiv_rg_denom2$D_IN; - if (intDiv_rg_denom_is_signed$EN) - intDiv_rg_denom_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_denom_is_signed$D_IN; - if (intDiv_rg_n$EN) intDiv_rg_n <= `BSV_ASSIGNMENT_DELAY intDiv_rg_n$D_IN; - if (intDiv_rg_numer_is_signed$EN) - intDiv_rg_numer_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_numer_is_signed$D_IN; - if (intDiv_rg_quo$EN) - intDiv_rg_quo <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quo$D_IN; - if (intDiv_rg_quoIsNeg$EN) - intDiv_rg_quoIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quoIsNeg$D_IN; - if (intDiv_rg_remIsNeg$EN) - intDiv_rg_remIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_remIsNeg$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_is_OP_not_OP_32$EN) - rg_is_OP_not_OP_32 <= `BSV_ASSIGNMENT_DELAY rg_is_OP_not_OP_32$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_v1$EN) rg_v1 <= `BSV_ASSIGNMENT_DELAY rg_v1$D_IN; - if (rg_v2$EN) rg_v2 <= `BSV_ASSIGNMENT_DELAY rg_v2$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - intDiv_rg_denom2 = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_denom_is_signed = 1'h0; - intDiv_rg_n = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_numer_is_signed = 1'h0; - intDiv_rg_quo = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_quoIsNeg = 1'h0; - intDiv_rg_remIsNeg = 1'h0; - intDiv_rg_state = 3'h2; - rg_f3 = 3'h2; - rg_is_OP_not_OP_32 = 1'h0; - rg_state = 2'h2; - rg_v1 = 64'hAAAAAAAAAAAAAAAA; - rg_v2 = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && cfg_verbosity > 4'd1) - $display(" RISCV_MBox.rl_mul"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $display("%0d: ERROR: RISCV_MBox.rl_mul: illegal f3.", v__h4700); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $display(" f3 0x%0h v1 0x%0h v2 0x%0h", rg_f3, rg_v1, rg_v2); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkRISCV_MBox - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v deleted file mode 100644 index c88e21cd..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v +++ /dev/null @@ -1,298 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// m_near_mem_io_addr_base O 64 const -// m_near_mem_io_addr_size O 64 const -// m_near_mem_io_addr_lim O 64 const -// m_plic_addr_base O 64 const -// m_plic_addr_size O 64 const -// m_plic_addr_lim O 64 const -// m_uart0_addr_base O 64 const -// m_uart0_addr_size O 64 const -// m_uart0_addr_lim O 64 const -// m_boot_rom_addr_base O 64 const -// m_boot_rom_addr_size O 64 const -// m_boot_rom_addr_lim O 64 const -// m_mem0_controller_addr_base O 64 const -// m_mem0_controller_addr_size O 64 const -// m_mem0_controller_addr_lim O 64 const -// m_tcm_addr_base O 64 const -// m_tcm_addr_size O 64 const -// m_tcm_addr_lim O 64 const -// m_is_mem_addr O 1 -// m_is_IO_addr O 1 -// m_is_near_mem_IO_addr O 1 -// m_pc_reset_value O 64 const -// m_mtvec_reset_value O 64 const -// m_nmivec_reset_value O 64 const -// CLK I 1 unused -// RST_N I 1 unused -// m_is_mem_addr_addr I 64 -// m_is_IO_addr_addr I 64 -// m_is_near_mem_IO_addr_addr I 64 -// -// Combinational paths from inputs to outputs: -// m_is_mem_addr_addr -> m_is_mem_addr -// m_is_IO_addr_addr -> m_is_IO_addr -// m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Map(CLK, - RST_N, - - m_near_mem_io_addr_base, - - m_near_mem_io_addr_size, - - m_near_mem_io_addr_lim, - - m_plic_addr_base, - - m_plic_addr_size, - - m_plic_addr_lim, - - m_uart0_addr_base, - - m_uart0_addr_size, - - m_uart0_addr_lim, - - m_boot_rom_addr_base, - - m_boot_rom_addr_size, - - m_boot_rom_addr_lim, - - m_mem0_controller_addr_base, - - m_mem0_controller_addr_size, - - m_mem0_controller_addr_lim, - - m_tcm_addr_base, - - m_tcm_addr_size, - - m_tcm_addr_lim, - - m_is_mem_addr_addr, - m_is_mem_addr, - - m_is_IO_addr_addr, - m_is_IO_addr, - - m_is_near_mem_IO_addr_addr, - m_is_near_mem_IO_addr, - - m_pc_reset_value, - - m_mtvec_reset_value, - - m_nmivec_reset_value); - input CLK; - input RST_N; - - // value method m_near_mem_io_addr_base - output [63 : 0] m_near_mem_io_addr_base; - - // value method m_near_mem_io_addr_size - output [63 : 0] m_near_mem_io_addr_size; - - // value method m_near_mem_io_addr_lim - output [63 : 0] m_near_mem_io_addr_lim; - - // value method m_plic_addr_base - output [63 : 0] m_plic_addr_base; - - // value method m_plic_addr_size - output [63 : 0] m_plic_addr_size; - - // value method m_plic_addr_lim - output [63 : 0] m_plic_addr_lim; - - // value method m_uart0_addr_base - output [63 : 0] m_uart0_addr_base; - - // value method m_uart0_addr_size - output [63 : 0] m_uart0_addr_size; - - // value method m_uart0_addr_lim - output [63 : 0] m_uart0_addr_lim; - - // value method m_boot_rom_addr_base - output [63 : 0] m_boot_rom_addr_base; - - // value method m_boot_rom_addr_size - output [63 : 0] m_boot_rom_addr_size; - - // value method m_boot_rom_addr_lim - output [63 : 0] m_boot_rom_addr_lim; - - // value method m_mem0_controller_addr_base - output [63 : 0] m_mem0_controller_addr_base; - - // value method m_mem0_controller_addr_size - output [63 : 0] m_mem0_controller_addr_size; - - // value method m_mem0_controller_addr_lim - output [63 : 0] m_mem0_controller_addr_lim; - - // value method m_tcm_addr_base - output [63 : 0] m_tcm_addr_base; - - // value method m_tcm_addr_size - output [63 : 0] m_tcm_addr_size; - - // value method m_tcm_addr_lim - output [63 : 0] m_tcm_addr_lim; - - // value method m_is_mem_addr - input [63 : 0] m_is_mem_addr_addr; - output m_is_mem_addr; - - // value method m_is_IO_addr - input [63 : 0] m_is_IO_addr_addr; - output m_is_IO_addr; - - // value method m_is_near_mem_IO_addr - input [63 : 0] m_is_near_mem_IO_addr_addr; - output m_is_near_mem_IO_addr; - - // value method m_pc_reset_value - output [63 : 0] m_pc_reset_value; - - // value method m_mtvec_reset_value - output [63 : 0] m_mtvec_reset_value; - - // value method m_nmivec_reset_value - output [63 : 0] m_nmivec_reset_value; - - // signals for module outputs - wire [63 : 0] m_boot_rom_addr_base, - m_boot_rom_addr_lim, - m_boot_rom_addr_size, - m_mem0_controller_addr_base, - m_mem0_controller_addr_lim, - m_mem0_controller_addr_size, - m_mtvec_reset_value, - m_near_mem_io_addr_base, - m_near_mem_io_addr_lim, - m_near_mem_io_addr_size, - m_nmivec_reset_value, - m_pc_reset_value, - m_plic_addr_base, - m_plic_addr_lim, - m_plic_addr_size, - m_tcm_addr_base, - m_tcm_addr_lim, - m_tcm_addr_size, - m_uart0_addr_base, - m_uart0_addr_lim, - m_uart0_addr_size; - wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; - - // value method m_near_mem_io_addr_base - assign m_near_mem_io_addr_base = 64'h0000000002000000 ; - - // value method m_near_mem_io_addr_size - assign m_near_mem_io_addr_size = 64'h000000000000C000 ; - - // value method m_near_mem_io_addr_lim - assign m_near_mem_io_addr_lim = 64'd33603584 ; - - // value method m_plic_addr_base - assign m_plic_addr_base = 64'h000000000C000000 ; - - // value method m_plic_addr_size - assign m_plic_addr_size = 64'h0000000000400000 ; - - // value method m_plic_addr_lim - assign m_plic_addr_lim = 64'd205520896 ; - - // value method m_uart0_addr_base - assign m_uart0_addr_base = 64'h00000000C0000000 ; - - // value method m_uart0_addr_size - assign m_uart0_addr_size = 64'h0000000000000080 ; - - // value method m_uart0_addr_lim - assign m_uart0_addr_lim = 64'h00000000C0000080 ; - - // value method m_boot_rom_addr_base - assign m_boot_rom_addr_base = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_size - assign m_boot_rom_addr_size = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_lim - assign m_boot_rom_addr_lim = 64'd8192 ; - - // value method m_mem0_controller_addr_base - assign m_mem0_controller_addr_base = 64'h0000000080000000 ; - - // value method m_mem0_controller_addr_size - assign m_mem0_controller_addr_size = 64'h0000000010000000 ; - - // value method m_mem0_controller_addr_lim - assign m_mem0_controller_addr_lim = 64'h0000000090000000 ; - - // value method m_tcm_addr_base - assign m_tcm_addr_base = 64'h0 ; - - // value method m_tcm_addr_size - assign m_tcm_addr_size = 64'd0 ; - - // value method m_tcm_addr_lim - assign m_tcm_addr_lim = 64'd0 ; - - // value method m_is_mem_addr - assign m_is_mem_addr = - m_is_mem_addr_addr >= 64'h0000000000001000 && - m_is_mem_addr_addr < 64'd8192 || - m_is_mem_addr_addr >= 64'h0000000080000000 && - m_is_mem_addr_addr < 64'h0000000090000000 ; - - // value method m_is_IO_addr - assign m_is_IO_addr = - m_is_IO_addr_addr >= 64'h0000000002000000 && - m_is_IO_addr_addr < 64'd33603584 || - m_is_IO_addr_addr >= 64'h000000000C000000 && - m_is_IO_addr_addr < 64'd205520896 || - m_is_IO_addr_addr >= 64'h00000000C0000000 && - m_is_IO_addr_addr < 64'h00000000C0000080 ; - - // value method m_is_near_mem_IO_addr - assign m_is_near_mem_IO_addr = - m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 && - m_is_near_mem_IO_addr_addr < 64'd33603584 ; - - // value method m_pc_reset_value - assign m_pc_reset_value = 64'h0000000000001000 ; - - // value method m_mtvec_reset_value - assign m_mtvec_reset_value = 64'h0000000000001000 ; - - // value method m_nmivec_reset_value - assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ; -endmodule // mkSoC_Map - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v deleted file mode 100644 index 42e03763..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v +++ /dev/null @@ -1,2333 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// to_raw_mem_response_put I 256 -// put_from_console_put I 8 reg -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_set_verbosity I 1 -// EN_to_raw_mem_response_put I 1 -// EN_put_from_console_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Top(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [7 : 0] get_to_console_get, status; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_set_verbosity, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule boot_rom - wire [63 : 0] boot_rom$set_addr_map_addr_base, - boot_rom$set_addr_map_addr_lim, - boot_rom$slave_araddr, - boot_rom$slave_awaddr, - boot_rom$slave_rdata, - boot_rom$slave_wdata; - wire [7 : 0] boot_rom$slave_arlen, - boot_rom$slave_awlen, - boot_rom$slave_wstrb; - wire [3 : 0] boot_rom$slave_arcache, - boot_rom$slave_arid, - boot_rom$slave_arqos, - boot_rom$slave_arregion, - boot_rom$slave_awcache, - boot_rom$slave_awid, - boot_rom$slave_awqos, - boot_rom$slave_awregion, - boot_rom$slave_bid, - boot_rom$slave_rid, - boot_rom$slave_wid; - wire [2 : 0] boot_rom$slave_arprot, - boot_rom$slave_arsize, - boot_rom$slave_awprot, - boot_rom$slave_awsize; - wire [1 : 0] boot_rom$slave_arburst, - boot_rom$slave_awburst, - boot_rom$slave_bresp, - boot_rom$slave_rresp; - wire boot_rom$EN_set_addr_map, - boot_rom$slave_arlock, - boot_rom$slave_arready, - boot_rom$slave_arvalid, - boot_rom$slave_awlock, - boot_rom$slave_awready, - boot_rom$slave_awvalid, - boot_rom$slave_bready, - boot_rom$slave_bvalid, - boot_rom$slave_rlast, - boot_rom$slave_rready, - boot_rom$slave_rvalid, - boot_rom$slave_wlast, - boot_rom$slave_wready, - boot_rom$slave_wvalid; - - // ports of submodule boot_rom_axi4_deburster - wire [63 : 0] boot_rom_axi4_deburster$from_master_araddr, - boot_rom_axi4_deburster$from_master_awaddr, - boot_rom_axi4_deburster$from_master_rdata, - boot_rom_axi4_deburster$from_master_wdata, - boot_rom_axi4_deburster$to_slave_araddr, - boot_rom_axi4_deburster$to_slave_awaddr, - boot_rom_axi4_deburster$to_slave_rdata, - boot_rom_axi4_deburster$to_slave_wdata; - wire [7 : 0] boot_rom_axi4_deburster$from_master_arlen, - boot_rom_axi4_deburster$from_master_awlen, - boot_rom_axi4_deburster$from_master_wstrb, - boot_rom_axi4_deburster$to_slave_arlen, - boot_rom_axi4_deburster$to_slave_awlen, - boot_rom_axi4_deburster$to_slave_wstrb; - wire [3 : 0] boot_rom_axi4_deburster$from_master_arcache, - boot_rom_axi4_deburster$from_master_arid, - boot_rom_axi4_deburster$from_master_arqos, - boot_rom_axi4_deburster$from_master_arregion, - boot_rom_axi4_deburster$from_master_awcache, - boot_rom_axi4_deburster$from_master_awid, - boot_rom_axi4_deburster$from_master_awqos, - boot_rom_axi4_deburster$from_master_awregion, - boot_rom_axi4_deburster$from_master_bid, - boot_rom_axi4_deburster$from_master_rid, - boot_rom_axi4_deburster$from_master_wid, - boot_rom_axi4_deburster$to_slave_arcache, - boot_rom_axi4_deburster$to_slave_arid, - boot_rom_axi4_deburster$to_slave_arqos, - boot_rom_axi4_deburster$to_slave_arregion, - boot_rom_axi4_deburster$to_slave_awcache, - boot_rom_axi4_deburster$to_slave_awid, - boot_rom_axi4_deburster$to_slave_awqos, - boot_rom_axi4_deburster$to_slave_awregion, - boot_rom_axi4_deburster$to_slave_bid, - boot_rom_axi4_deburster$to_slave_rid, - boot_rom_axi4_deburster$to_slave_wid; - wire [2 : 0] boot_rom_axi4_deburster$from_master_arprot, - boot_rom_axi4_deburster$from_master_arsize, - boot_rom_axi4_deburster$from_master_awprot, - boot_rom_axi4_deburster$from_master_awsize, - boot_rom_axi4_deburster$to_slave_arprot, - boot_rom_axi4_deburster$to_slave_arsize, - boot_rom_axi4_deburster$to_slave_awprot, - boot_rom_axi4_deburster$to_slave_awsize; - wire [1 : 0] boot_rom_axi4_deburster$from_master_arburst, - boot_rom_axi4_deburster$from_master_awburst, - boot_rom_axi4_deburster$from_master_bresp, - boot_rom_axi4_deburster$from_master_rresp, - boot_rom_axi4_deburster$to_slave_arburst, - boot_rom_axi4_deburster$to_slave_awburst, - boot_rom_axi4_deburster$to_slave_bresp, - boot_rom_axi4_deburster$to_slave_rresp; - wire boot_rom_axi4_deburster$EN_reset, - boot_rom_axi4_deburster$from_master_arlock, - boot_rom_axi4_deburster$from_master_arready, - boot_rom_axi4_deburster$from_master_arvalid, - boot_rom_axi4_deburster$from_master_awlock, - boot_rom_axi4_deburster$from_master_awready, - boot_rom_axi4_deburster$from_master_awvalid, - boot_rom_axi4_deburster$from_master_bready, - boot_rom_axi4_deburster$from_master_bvalid, - boot_rom_axi4_deburster$from_master_rlast, - boot_rom_axi4_deburster$from_master_rready, - boot_rom_axi4_deburster$from_master_rvalid, - boot_rom_axi4_deburster$from_master_wlast, - boot_rom_axi4_deburster$from_master_wready, - boot_rom_axi4_deburster$from_master_wvalid, - boot_rom_axi4_deburster$to_slave_arlock, - boot_rom_axi4_deburster$to_slave_arready, - boot_rom_axi4_deburster$to_slave_arvalid, - boot_rom_axi4_deburster$to_slave_awlock, - boot_rom_axi4_deburster$to_slave_awready, - boot_rom_axi4_deburster$to_slave_awvalid, - boot_rom_axi4_deburster$to_slave_bready, - boot_rom_axi4_deburster$to_slave_bvalid, - boot_rom_axi4_deburster$to_slave_rlast, - boot_rom_axi4_deburster$to_slave_rready, - boot_rom_axi4_deburster$to_slave_rvalid, - boot_rom_axi4_deburster$to_slave_wlast, - boot_rom_axi4_deburster$to_slave_wready, - boot_rom_axi4_deburster$to_slave_wvalid; - - // ports of submodule core - wire [63 : 0] core$cpu_dmem_master_araddr, - core$cpu_dmem_master_awaddr, - core$cpu_dmem_master_rdata, - core$cpu_dmem_master_wdata, - core$cpu_imem_master_araddr, - core$cpu_imem_master_awaddr, - core$cpu_imem_master_rdata, - core$cpu_imem_master_wdata, - core$set_verbosity_logdelay; - wire [7 : 0] core$cpu_dmem_master_arlen, - core$cpu_dmem_master_awlen, - core$cpu_dmem_master_wstrb, - core$cpu_imem_master_arlen, - core$cpu_imem_master_awlen, - core$cpu_imem_master_wstrb; - wire [3 : 0] core$cpu_dmem_master_arcache, - core$cpu_dmem_master_arid, - core$cpu_dmem_master_arqos, - core$cpu_dmem_master_arregion, - core$cpu_dmem_master_awcache, - core$cpu_dmem_master_awid, - core$cpu_dmem_master_awqos, - core$cpu_dmem_master_awregion, - core$cpu_dmem_master_bid, - core$cpu_dmem_master_rid, - core$cpu_dmem_master_wid, - core$cpu_imem_master_arcache, - core$cpu_imem_master_arid, - core$cpu_imem_master_arqos, - core$cpu_imem_master_arregion, - core$cpu_imem_master_awcache, - core$cpu_imem_master_awid, - core$cpu_imem_master_awqos, - core$cpu_imem_master_awregion, - core$cpu_imem_master_bid, - core$cpu_imem_master_rid, - core$cpu_imem_master_wid, - core$set_verbosity_verbosity; - wire [2 : 0] core$cpu_dmem_master_arprot, - core$cpu_dmem_master_arsize, - core$cpu_dmem_master_awprot, - core$cpu_dmem_master_awsize, - core$cpu_imem_master_arprot, - core$cpu_imem_master_arsize, - core$cpu_imem_master_awprot, - core$cpu_imem_master_awsize; - wire [1 : 0] core$cpu_dmem_master_arburst, - core$cpu_dmem_master_awburst, - core$cpu_dmem_master_bresp, - core$cpu_dmem_master_rresp, - core$cpu_imem_master_arburst, - core$cpu_imem_master_awburst, - core$cpu_imem_master_bresp, - core$cpu_imem_master_rresp; - wire core$EN_cpu_reset_server_request_put, - core$EN_cpu_reset_server_response_get, - core$EN_set_verbosity, - core$RDY_cpu_reset_server_request_put, - core$RDY_cpu_reset_server_response_get, - core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - core$cpu_dmem_master_arlock, - core$cpu_dmem_master_arready, - core$cpu_dmem_master_arvalid, - core$cpu_dmem_master_awlock, - core$cpu_dmem_master_awready, - core$cpu_dmem_master_awvalid, - core$cpu_dmem_master_bready, - core$cpu_dmem_master_bvalid, - core$cpu_dmem_master_rlast, - core$cpu_dmem_master_rready, - core$cpu_dmem_master_rvalid, - core$cpu_dmem_master_wlast, - core$cpu_dmem_master_wready, - core$cpu_dmem_master_wvalid, - core$cpu_imem_master_arlock, - core$cpu_imem_master_arready, - core$cpu_imem_master_arvalid, - core$cpu_imem_master_awlock, - core$cpu_imem_master_awready, - core$cpu_imem_master_awvalid, - core$cpu_imem_master_bready, - core$cpu_imem_master_bvalid, - core$cpu_imem_master_rlast, - core$cpu_imem_master_rready, - core$cpu_imem_master_rvalid, - core$cpu_imem_master_wlast, - core$cpu_imem_master_wready, - core$cpu_imem_master_wvalid, - core$cpu_reset_server_request_put, - core$nmi_req_set_not_clear; - - // ports of submodule fabric - wire [63 : 0] fabric$v_from_masters_0_araddr, - fabric$v_from_masters_0_awaddr, - fabric$v_from_masters_0_rdata, - fabric$v_from_masters_0_wdata, - fabric$v_from_masters_1_araddr, - fabric$v_from_masters_1_awaddr, - fabric$v_from_masters_1_rdata, - fabric$v_from_masters_1_wdata, - fabric$v_to_slaves_0_araddr, - fabric$v_to_slaves_0_awaddr, - fabric$v_to_slaves_0_rdata, - fabric$v_to_slaves_0_wdata, - fabric$v_to_slaves_1_araddr, - fabric$v_to_slaves_1_awaddr, - fabric$v_to_slaves_1_rdata, - fabric$v_to_slaves_1_wdata, - fabric$v_to_slaves_2_araddr, - fabric$v_to_slaves_2_awaddr, - fabric$v_to_slaves_2_rdata, - fabric$v_to_slaves_2_wdata; - wire [7 : 0] fabric$v_from_masters_0_arlen, - fabric$v_from_masters_0_awlen, - fabric$v_from_masters_0_wstrb, - fabric$v_from_masters_1_arlen, - fabric$v_from_masters_1_awlen, - fabric$v_from_masters_1_wstrb, - fabric$v_to_slaves_0_arlen, - fabric$v_to_slaves_0_awlen, - fabric$v_to_slaves_0_wstrb, - fabric$v_to_slaves_1_arlen, - fabric$v_to_slaves_1_awlen, - fabric$v_to_slaves_1_wstrb, - fabric$v_to_slaves_2_arlen, - fabric$v_to_slaves_2_awlen, - fabric$v_to_slaves_2_wstrb; - wire [3 : 0] fabric$set_verbosity_verbosity, - fabric$v_from_masters_0_arcache, - fabric$v_from_masters_0_arid, - fabric$v_from_masters_0_arqos, - fabric$v_from_masters_0_arregion, - fabric$v_from_masters_0_awcache, - fabric$v_from_masters_0_awid, - fabric$v_from_masters_0_awqos, - fabric$v_from_masters_0_awregion, - fabric$v_from_masters_0_bid, - fabric$v_from_masters_0_rid, - fabric$v_from_masters_0_wid, - fabric$v_from_masters_1_arcache, - fabric$v_from_masters_1_arid, - fabric$v_from_masters_1_arqos, - fabric$v_from_masters_1_arregion, - fabric$v_from_masters_1_awcache, - fabric$v_from_masters_1_awid, - fabric$v_from_masters_1_awqos, - fabric$v_from_masters_1_awregion, - fabric$v_from_masters_1_bid, - fabric$v_from_masters_1_rid, - fabric$v_from_masters_1_wid, - fabric$v_to_slaves_0_arcache, - fabric$v_to_slaves_0_arid, - fabric$v_to_slaves_0_arqos, - fabric$v_to_slaves_0_arregion, - fabric$v_to_slaves_0_awcache, - fabric$v_to_slaves_0_awid, - fabric$v_to_slaves_0_awqos, - fabric$v_to_slaves_0_awregion, - fabric$v_to_slaves_0_bid, - fabric$v_to_slaves_0_rid, - fabric$v_to_slaves_0_wid, - fabric$v_to_slaves_1_arcache, - fabric$v_to_slaves_1_arid, - fabric$v_to_slaves_1_arqos, - fabric$v_to_slaves_1_arregion, - fabric$v_to_slaves_1_awcache, - fabric$v_to_slaves_1_awid, - fabric$v_to_slaves_1_awqos, - fabric$v_to_slaves_1_awregion, - fabric$v_to_slaves_1_bid, - fabric$v_to_slaves_1_rid, - fabric$v_to_slaves_1_wid, - fabric$v_to_slaves_2_arcache, - fabric$v_to_slaves_2_arid, - fabric$v_to_slaves_2_arqos, - fabric$v_to_slaves_2_arregion, - fabric$v_to_slaves_2_awcache, - fabric$v_to_slaves_2_awid, - fabric$v_to_slaves_2_awqos, - fabric$v_to_slaves_2_awregion, - fabric$v_to_slaves_2_bid, - fabric$v_to_slaves_2_rid, - fabric$v_to_slaves_2_wid; - wire [2 : 0] fabric$v_from_masters_0_arprot, - fabric$v_from_masters_0_arsize, - fabric$v_from_masters_0_awprot, - fabric$v_from_masters_0_awsize, - fabric$v_from_masters_1_arprot, - fabric$v_from_masters_1_arsize, - fabric$v_from_masters_1_awprot, - fabric$v_from_masters_1_awsize, - fabric$v_to_slaves_0_arprot, - fabric$v_to_slaves_0_arsize, - fabric$v_to_slaves_0_awprot, - fabric$v_to_slaves_0_awsize, - fabric$v_to_slaves_1_arprot, - fabric$v_to_slaves_1_arsize, - fabric$v_to_slaves_1_awprot, - fabric$v_to_slaves_1_awsize, - fabric$v_to_slaves_2_arprot, - fabric$v_to_slaves_2_arsize, - fabric$v_to_slaves_2_awprot, - fabric$v_to_slaves_2_awsize; - wire [1 : 0] fabric$v_from_masters_0_arburst, - fabric$v_from_masters_0_awburst, - fabric$v_from_masters_0_bresp, - fabric$v_from_masters_0_rresp, - fabric$v_from_masters_1_arburst, - fabric$v_from_masters_1_awburst, - fabric$v_from_masters_1_bresp, - fabric$v_from_masters_1_rresp, - fabric$v_to_slaves_0_arburst, - fabric$v_to_slaves_0_awburst, - fabric$v_to_slaves_0_bresp, - fabric$v_to_slaves_0_rresp, - fabric$v_to_slaves_1_arburst, - fabric$v_to_slaves_1_awburst, - fabric$v_to_slaves_1_bresp, - fabric$v_to_slaves_1_rresp, - fabric$v_to_slaves_2_arburst, - fabric$v_to_slaves_2_awburst, - fabric$v_to_slaves_2_bresp, - fabric$v_to_slaves_2_rresp; - wire fabric$EN_reset, - fabric$EN_set_verbosity, - fabric$RDY_reset, - fabric$v_from_masters_0_arlock, - fabric$v_from_masters_0_arready, - fabric$v_from_masters_0_arvalid, - fabric$v_from_masters_0_awlock, - fabric$v_from_masters_0_awready, - fabric$v_from_masters_0_awvalid, - fabric$v_from_masters_0_bready, - fabric$v_from_masters_0_bvalid, - fabric$v_from_masters_0_rlast, - fabric$v_from_masters_0_rready, - fabric$v_from_masters_0_rvalid, - fabric$v_from_masters_0_wlast, - fabric$v_from_masters_0_wready, - fabric$v_from_masters_0_wvalid, - fabric$v_from_masters_1_arlock, - fabric$v_from_masters_1_arready, - fabric$v_from_masters_1_arvalid, - fabric$v_from_masters_1_awlock, - fabric$v_from_masters_1_awready, - fabric$v_from_masters_1_awvalid, - fabric$v_from_masters_1_bready, - fabric$v_from_masters_1_bvalid, - fabric$v_from_masters_1_rlast, - fabric$v_from_masters_1_rready, - fabric$v_from_masters_1_rvalid, - fabric$v_from_masters_1_wlast, - fabric$v_from_masters_1_wready, - fabric$v_from_masters_1_wvalid, - fabric$v_to_slaves_0_arlock, - fabric$v_to_slaves_0_arready, - fabric$v_to_slaves_0_arvalid, - fabric$v_to_slaves_0_awlock, - fabric$v_to_slaves_0_awready, - fabric$v_to_slaves_0_awvalid, - fabric$v_to_slaves_0_bready, - fabric$v_to_slaves_0_bvalid, - fabric$v_to_slaves_0_rlast, - fabric$v_to_slaves_0_rready, - fabric$v_to_slaves_0_rvalid, - fabric$v_to_slaves_0_wlast, - fabric$v_to_slaves_0_wready, - fabric$v_to_slaves_0_wvalid, - fabric$v_to_slaves_1_arlock, - fabric$v_to_slaves_1_arready, - fabric$v_to_slaves_1_arvalid, - fabric$v_to_slaves_1_awlock, - fabric$v_to_slaves_1_awready, - fabric$v_to_slaves_1_awvalid, - fabric$v_to_slaves_1_bready, - fabric$v_to_slaves_1_bvalid, - fabric$v_to_slaves_1_rlast, - fabric$v_to_slaves_1_rready, - fabric$v_to_slaves_1_rvalid, - fabric$v_to_slaves_1_wlast, - fabric$v_to_slaves_1_wready, - fabric$v_to_slaves_1_wvalid, - fabric$v_to_slaves_2_arlock, - fabric$v_to_slaves_2_arready, - fabric$v_to_slaves_2_arvalid, - fabric$v_to_slaves_2_awlock, - fabric$v_to_slaves_2_awready, - fabric$v_to_slaves_2_awvalid, - fabric$v_to_slaves_2_bready, - fabric$v_to_slaves_2_bvalid, - fabric$v_to_slaves_2_rlast, - fabric$v_to_slaves_2_rready, - fabric$v_to_slaves_2_rvalid, - fabric$v_to_slaves_2_wlast, - fabric$v_to_slaves_2_wready, - fabric$v_to_slaves_2_wvalid; - - // ports of submodule mem0_controller - wire [352 : 0] mem0_controller$to_raw_mem_request_get; - wire [255 : 0] mem0_controller$to_raw_mem_response_put; - wire [63 : 0] mem0_controller$set_addr_map_addr_base, - mem0_controller$set_addr_map_addr_lim, - mem0_controller$set_watch_tohost_tohost_addr, - mem0_controller$slave_araddr, - mem0_controller$slave_awaddr, - mem0_controller$slave_rdata, - mem0_controller$slave_wdata; - wire [7 : 0] mem0_controller$slave_arlen, - mem0_controller$slave_awlen, - mem0_controller$slave_wstrb, - mem0_controller$status; - wire [3 : 0] mem0_controller$slave_arcache, - mem0_controller$slave_arid, - mem0_controller$slave_arqos, - mem0_controller$slave_arregion, - mem0_controller$slave_awcache, - mem0_controller$slave_awid, - mem0_controller$slave_awqos, - mem0_controller$slave_awregion, - mem0_controller$slave_bid, - mem0_controller$slave_rid, - mem0_controller$slave_wid; - wire [2 : 0] mem0_controller$slave_arprot, - mem0_controller$slave_arsize, - mem0_controller$slave_awprot, - mem0_controller$slave_awsize; - wire [1 : 0] mem0_controller$slave_arburst, - mem0_controller$slave_awburst, - mem0_controller$slave_bresp, - mem0_controller$slave_rresp; - wire mem0_controller$EN_server_reset_request_put, - mem0_controller$EN_server_reset_response_get, - mem0_controller$EN_set_addr_map, - mem0_controller$EN_set_watch_tohost, - mem0_controller$EN_to_raw_mem_request_get, - mem0_controller$EN_to_raw_mem_response_put, - mem0_controller$RDY_server_reset_request_put, - mem0_controller$RDY_server_reset_response_get, - mem0_controller$RDY_set_addr_map, - mem0_controller$RDY_to_raw_mem_request_get, - mem0_controller$RDY_to_raw_mem_response_put, - mem0_controller$set_watch_tohost_watch_tohost, - mem0_controller$slave_arlock, - mem0_controller$slave_arready, - mem0_controller$slave_arvalid, - mem0_controller$slave_awlock, - mem0_controller$slave_awready, - mem0_controller$slave_awvalid, - mem0_controller$slave_bready, - mem0_controller$slave_bvalid, - mem0_controller$slave_rlast, - mem0_controller$slave_rready, - mem0_controller$slave_rvalid, - mem0_controller$slave_wlast, - mem0_controller$slave_wready, - mem0_controller$slave_wvalid; - - // ports of submodule mem0_controller_axi4_deburster - wire [63 : 0] mem0_controller_axi4_deburster$from_master_araddr, - mem0_controller_axi4_deburster$from_master_awaddr, - mem0_controller_axi4_deburster$from_master_rdata, - mem0_controller_axi4_deburster$from_master_wdata, - mem0_controller_axi4_deburster$to_slave_araddr, - mem0_controller_axi4_deburster$to_slave_awaddr, - mem0_controller_axi4_deburster$to_slave_rdata, - mem0_controller_axi4_deburster$to_slave_wdata; - wire [7 : 0] mem0_controller_axi4_deburster$from_master_arlen, - mem0_controller_axi4_deburster$from_master_awlen, - mem0_controller_axi4_deburster$from_master_wstrb, - mem0_controller_axi4_deburster$to_slave_arlen, - mem0_controller_axi4_deburster$to_slave_awlen, - mem0_controller_axi4_deburster$to_slave_wstrb; - wire [3 : 0] mem0_controller_axi4_deburster$from_master_arcache, - mem0_controller_axi4_deburster$from_master_arid, - mem0_controller_axi4_deburster$from_master_arqos, - mem0_controller_axi4_deburster$from_master_arregion, - mem0_controller_axi4_deburster$from_master_awcache, - mem0_controller_axi4_deburster$from_master_awid, - mem0_controller_axi4_deburster$from_master_awqos, - mem0_controller_axi4_deburster$from_master_awregion, - mem0_controller_axi4_deburster$from_master_bid, - mem0_controller_axi4_deburster$from_master_rid, - mem0_controller_axi4_deburster$from_master_wid, - mem0_controller_axi4_deburster$to_slave_arcache, - mem0_controller_axi4_deburster$to_slave_arid, - mem0_controller_axi4_deburster$to_slave_arqos, - mem0_controller_axi4_deburster$to_slave_arregion, - mem0_controller_axi4_deburster$to_slave_awcache, - mem0_controller_axi4_deburster$to_slave_awid, - mem0_controller_axi4_deburster$to_slave_awqos, - mem0_controller_axi4_deburster$to_slave_awregion, - mem0_controller_axi4_deburster$to_slave_bid, - mem0_controller_axi4_deburster$to_slave_rid, - mem0_controller_axi4_deburster$to_slave_wid; - wire [2 : 0] mem0_controller_axi4_deburster$from_master_arprot, - mem0_controller_axi4_deburster$from_master_arsize, - mem0_controller_axi4_deburster$from_master_awprot, - mem0_controller_axi4_deburster$from_master_awsize, - mem0_controller_axi4_deburster$to_slave_arprot, - mem0_controller_axi4_deburster$to_slave_arsize, - mem0_controller_axi4_deburster$to_slave_awprot, - mem0_controller_axi4_deburster$to_slave_awsize; - wire [1 : 0] mem0_controller_axi4_deburster$from_master_arburst, - mem0_controller_axi4_deburster$from_master_awburst, - mem0_controller_axi4_deburster$from_master_bresp, - mem0_controller_axi4_deburster$from_master_rresp, - mem0_controller_axi4_deburster$to_slave_arburst, - mem0_controller_axi4_deburster$to_slave_awburst, - mem0_controller_axi4_deburster$to_slave_bresp, - mem0_controller_axi4_deburster$to_slave_rresp; - wire mem0_controller_axi4_deburster$EN_reset, - mem0_controller_axi4_deburster$from_master_arlock, - mem0_controller_axi4_deburster$from_master_arready, - mem0_controller_axi4_deburster$from_master_arvalid, - mem0_controller_axi4_deburster$from_master_awlock, - mem0_controller_axi4_deburster$from_master_awready, - mem0_controller_axi4_deburster$from_master_awvalid, - mem0_controller_axi4_deburster$from_master_bready, - mem0_controller_axi4_deburster$from_master_bvalid, - mem0_controller_axi4_deburster$from_master_rlast, - mem0_controller_axi4_deburster$from_master_rready, - mem0_controller_axi4_deburster$from_master_rvalid, - mem0_controller_axi4_deburster$from_master_wlast, - mem0_controller_axi4_deburster$from_master_wready, - mem0_controller_axi4_deburster$from_master_wvalid, - mem0_controller_axi4_deburster$to_slave_arlock, - mem0_controller_axi4_deburster$to_slave_arready, - mem0_controller_axi4_deburster$to_slave_arvalid, - mem0_controller_axi4_deburster$to_slave_awlock, - mem0_controller_axi4_deburster$to_slave_awready, - mem0_controller_axi4_deburster$to_slave_awvalid, - mem0_controller_axi4_deburster$to_slave_bready, - mem0_controller_axi4_deburster$to_slave_bvalid, - mem0_controller_axi4_deburster$to_slave_rlast, - mem0_controller_axi4_deburster$to_slave_rready, - mem0_controller_axi4_deburster$to_slave_rvalid, - mem0_controller_axi4_deburster$to_slave_wlast, - mem0_controller_axi4_deburster$to_slave_wready, - mem0_controller_axi4_deburster$to_slave_wvalid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // ports of submodule uart0 - wire [63 : 0] uart0$set_addr_map_addr_base, - uart0$set_addr_map_addr_lim, - uart0$slave_araddr, - uart0$slave_awaddr, - uart0$slave_rdata, - uart0$slave_wdata; - wire [7 : 0] uart0$get_to_console_get, - uart0$put_from_console_put, - uart0$slave_arlen, - uart0$slave_awlen, - uart0$slave_wstrb; - wire [3 : 0] uart0$slave_arcache, - uart0$slave_arid, - uart0$slave_arqos, - uart0$slave_arregion, - uart0$slave_awcache, - uart0$slave_awid, - uart0$slave_awqos, - uart0$slave_awregion, - uart0$slave_bid, - uart0$slave_rid, - uart0$slave_wid; - wire [2 : 0] uart0$slave_arprot, - uart0$slave_arsize, - uart0$slave_awprot, - uart0$slave_awsize; - wire [1 : 0] uart0$slave_arburst, - uart0$slave_awburst, - uart0$slave_bresp, - uart0$slave_rresp; - wire uart0$EN_get_to_console_get, - uart0$EN_put_from_console_put, - uart0$EN_server_reset_request_put, - uart0$EN_server_reset_response_get, - uart0$EN_set_addr_map, - uart0$RDY_get_to_console_get, - uart0$RDY_put_from_console_put, - uart0$RDY_server_reset_request_put, - uart0$RDY_server_reset_response_get, - uart0$intr, - uart0$slave_arlock, - uart0$slave_arready, - uart0$slave_arvalid, - uart0$slave_awlock, - uart0$slave_awready, - uart0$slave_awvalid, - uart0$slave_bready, - uart0$slave_bvalid, - uart0$slave_rlast, - uart0$slave_rready, - uart0$slave_rvalid, - uart0$slave_wlast, - uart0$slave_wready, - uart0$slave_wvalid; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_connect_external_interrupt_requests, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_addr_channel_5, - CAN_FIRE_RL_rl_rd_addr_channel_6, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, - CAN_FIRE_RL_rl_rd_data_channel_5, - CAN_FIRE_RL_rl_rd_data_channel_6, - CAN_FIRE_RL_rl_reset_complete_initial, - CAN_FIRE_RL_rl_reset_start_initial, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_addr_channel_5, - CAN_FIRE_RL_rl_wr_addr_channel_6, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_data_channel_5, - CAN_FIRE_RL_rl_wr_data_channel_6, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, - CAN_FIRE_RL_rl_wr_response_channel_5, - CAN_FIRE_RL_rl_wr_response_channel_6, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_set_verbosity, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_connect_external_interrupt_requests, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_addr_channel_5, - WILL_FIRE_RL_rl_rd_addr_channel_6, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, - WILL_FIRE_RL_rl_rd_data_channel_5, - WILL_FIRE_RL_rl_rd_data_channel_6, - WILL_FIRE_RL_rl_reset_complete_initial, - WILL_FIRE_RL_rl_reset_start_initial, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_addr_channel_5, - WILL_FIRE_RL_rl_wr_addr_channel_6, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_data_channel_5, - WILL_FIRE_RL_rl_wr_data_channel_6, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, - WILL_FIRE_RL_rl_wr_response_channel_5, - WILL_FIRE_RL_rl_wr_response_channel_6, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_set_verbosity, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h11286; - reg [31 : 0] v__h11556; - reg [31 : 0] v__h11280; - reg [31 : 0] v__h11550; - // synopsys translate_on - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = mem0_controller$to_raw_mem_request_get ; - assign RDY_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign CAN_FIRE_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign CAN_FIRE_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // actionvalue method get_to_console_get - assign get_to_console_get = uart0$get_to_console_get ; - assign RDY_get_to_console_get = uart0$RDY_get_to_console_get ; - assign CAN_FIRE_get_to_console_get = uart0$RDY_get_to_console_get ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = uart0$RDY_put_from_console_put ; - assign CAN_FIRE_put_from_console_put = uart0$RDY_put_from_console_put ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method status - assign status = mem0_controller$status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule boot_rom - mkBoot_ROM boot_rom(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(boot_rom$set_addr_map_addr_base), - .set_addr_map_addr_lim(boot_rom$set_addr_map_addr_lim), - .slave_araddr(boot_rom$slave_araddr), - .slave_arburst(boot_rom$slave_arburst), - .slave_arcache(boot_rom$slave_arcache), - .slave_arid(boot_rom$slave_arid), - .slave_arlen(boot_rom$slave_arlen), - .slave_arlock(boot_rom$slave_arlock), - .slave_arprot(boot_rom$slave_arprot), - .slave_arqos(boot_rom$slave_arqos), - .slave_arregion(boot_rom$slave_arregion), - .slave_arsize(boot_rom$slave_arsize), - .slave_arvalid(boot_rom$slave_arvalid), - .slave_awaddr(boot_rom$slave_awaddr), - .slave_awburst(boot_rom$slave_awburst), - .slave_awcache(boot_rom$slave_awcache), - .slave_awid(boot_rom$slave_awid), - .slave_awlen(boot_rom$slave_awlen), - .slave_awlock(boot_rom$slave_awlock), - .slave_awprot(boot_rom$slave_awprot), - .slave_awqos(boot_rom$slave_awqos), - .slave_awregion(boot_rom$slave_awregion), - .slave_awsize(boot_rom$slave_awsize), - .slave_awvalid(boot_rom$slave_awvalid), - .slave_bready(boot_rom$slave_bready), - .slave_rready(boot_rom$slave_rready), - .slave_wdata(boot_rom$slave_wdata), - .slave_wid(boot_rom$slave_wid), - .slave_wlast(boot_rom$slave_wlast), - .slave_wstrb(boot_rom$slave_wstrb), - .slave_wvalid(boot_rom$slave_wvalid), - .EN_set_addr_map(boot_rom$EN_set_addr_map), - .RDY_set_addr_map(), - .slave_awready(boot_rom$slave_awready), - .slave_wready(boot_rom$slave_wready), - .slave_bvalid(boot_rom$slave_bvalid), - .slave_bid(boot_rom$slave_bid), - .slave_bresp(boot_rom$slave_bresp), - .slave_arready(boot_rom$slave_arready), - .slave_rvalid(boot_rom$slave_rvalid), - .slave_rid(boot_rom$slave_rid), - .slave_rdata(boot_rom$slave_rdata), - .slave_rresp(boot_rom$slave_rresp), - .slave_rlast(boot_rom$slave_rlast)); - - // submodule boot_rom_axi4_deburster - mkAXI4_Deburster_A boot_rom_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(boot_rom_axi4_deburster$from_master_araddr), - .from_master_arburst(boot_rom_axi4_deburster$from_master_arburst), - .from_master_arcache(boot_rom_axi4_deburster$from_master_arcache), - .from_master_arid(boot_rom_axi4_deburster$from_master_arid), - .from_master_arlen(boot_rom_axi4_deburster$from_master_arlen), - .from_master_arlock(boot_rom_axi4_deburster$from_master_arlock), - .from_master_arprot(boot_rom_axi4_deburster$from_master_arprot), - .from_master_arqos(boot_rom_axi4_deburster$from_master_arqos), - .from_master_arregion(boot_rom_axi4_deburster$from_master_arregion), - .from_master_arsize(boot_rom_axi4_deburster$from_master_arsize), - .from_master_arvalid(boot_rom_axi4_deburster$from_master_arvalid), - .from_master_awaddr(boot_rom_axi4_deburster$from_master_awaddr), - .from_master_awburst(boot_rom_axi4_deburster$from_master_awburst), - .from_master_awcache(boot_rom_axi4_deburster$from_master_awcache), - .from_master_awid(boot_rom_axi4_deburster$from_master_awid), - .from_master_awlen(boot_rom_axi4_deburster$from_master_awlen), - .from_master_awlock(boot_rom_axi4_deburster$from_master_awlock), - .from_master_awprot(boot_rom_axi4_deburster$from_master_awprot), - .from_master_awqos(boot_rom_axi4_deburster$from_master_awqos), - .from_master_awregion(boot_rom_axi4_deburster$from_master_awregion), - .from_master_awsize(boot_rom_axi4_deburster$from_master_awsize), - .from_master_awvalid(boot_rom_axi4_deburster$from_master_awvalid), - .from_master_bready(boot_rom_axi4_deburster$from_master_bready), - .from_master_rready(boot_rom_axi4_deburster$from_master_rready), - .from_master_wdata(boot_rom_axi4_deburster$from_master_wdata), - .from_master_wid(boot_rom_axi4_deburster$from_master_wid), - .from_master_wlast(boot_rom_axi4_deburster$from_master_wlast), - .from_master_wstrb(boot_rom_axi4_deburster$from_master_wstrb), - .from_master_wvalid(boot_rom_axi4_deburster$from_master_wvalid), - .to_slave_arready(boot_rom_axi4_deburster$to_slave_arready), - .to_slave_awready(boot_rom_axi4_deburster$to_slave_awready), - .to_slave_bid(boot_rom_axi4_deburster$to_slave_bid), - .to_slave_bresp(boot_rom_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(boot_rom_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(boot_rom_axi4_deburster$to_slave_rdata), - .to_slave_rid(boot_rom_axi4_deburster$to_slave_rid), - .to_slave_rlast(boot_rom_axi4_deburster$to_slave_rlast), - .to_slave_rresp(boot_rom_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(boot_rom_axi4_deburster$to_slave_rvalid), - .to_slave_wready(boot_rom_axi4_deburster$to_slave_wready), - .EN_reset(boot_rom_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(boot_rom_axi4_deburster$from_master_awready), - .from_master_wready(boot_rom_axi4_deburster$from_master_wready), - .from_master_bvalid(boot_rom_axi4_deburster$from_master_bvalid), - .from_master_bid(boot_rom_axi4_deburster$from_master_bid), - .from_master_bresp(boot_rom_axi4_deburster$from_master_bresp), - .from_master_arready(boot_rom_axi4_deburster$from_master_arready), - .from_master_rvalid(boot_rom_axi4_deburster$from_master_rvalid), - .from_master_rid(boot_rom_axi4_deburster$from_master_rid), - .from_master_rdata(boot_rom_axi4_deburster$from_master_rdata), - .from_master_rresp(boot_rom_axi4_deburster$from_master_rresp), - .from_master_rlast(boot_rom_axi4_deburster$from_master_rlast), - .to_slave_awvalid(boot_rom_axi4_deburster$to_slave_awvalid), - .to_slave_awid(boot_rom_axi4_deburster$to_slave_awid), - .to_slave_awaddr(boot_rom_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(boot_rom_axi4_deburster$to_slave_awlen), - .to_slave_awsize(boot_rom_axi4_deburster$to_slave_awsize), - .to_slave_awburst(boot_rom_axi4_deburster$to_slave_awburst), - .to_slave_awlock(boot_rom_axi4_deburster$to_slave_awlock), - .to_slave_awcache(boot_rom_axi4_deburster$to_slave_awcache), - .to_slave_awprot(boot_rom_axi4_deburster$to_slave_awprot), - .to_slave_awqos(boot_rom_axi4_deburster$to_slave_awqos), - .to_slave_awregion(boot_rom_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(boot_rom_axi4_deburster$to_slave_wvalid), - .to_slave_wid(boot_rom_axi4_deburster$to_slave_wid), - .to_slave_wdata(boot_rom_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(boot_rom_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(boot_rom_axi4_deburster$to_slave_wlast), - .to_slave_bready(boot_rom_axi4_deburster$to_slave_bready), - .to_slave_arvalid(boot_rom_axi4_deburster$to_slave_arvalid), - .to_slave_arid(boot_rom_axi4_deburster$to_slave_arid), - .to_slave_araddr(boot_rom_axi4_deburster$to_slave_araddr), - .to_slave_arlen(boot_rom_axi4_deburster$to_slave_arlen), - .to_slave_arsize(boot_rom_axi4_deburster$to_slave_arsize), - .to_slave_arburst(boot_rom_axi4_deburster$to_slave_arburst), - .to_slave_arlock(boot_rom_axi4_deburster$to_slave_arlock), - .to_slave_arcache(boot_rom_axi4_deburster$to_slave_arcache), - .to_slave_arprot(boot_rom_axi4_deburster$to_slave_arprot), - .to_slave_arqos(boot_rom_axi4_deburster$to_slave_arqos), - .to_slave_arregion(boot_rom_axi4_deburster$to_slave_arregion), - .to_slave_rready(boot_rom_axi4_deburster$to_slave_rready)); - - // submodule core - mkCore core(.CLK(CLK), - .RST_N(RST_N), - .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_12_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_13_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_14_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_15_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_1_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_2_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_3_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_4_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_5_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_6_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_7_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_8_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_9_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear), - .cpu_dmem_master_arready(core$cpu_dmem_master_arready), - .cpu_dmem_master_awready(core$cpu_dmem_master_awready), - .cpu_dmem_master_bid(core$cpu_dmem_master_bid), - .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), - .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata), - .cpu_dmem_master_rid(core$cpu_dmem_master_rid), - .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast), - .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), - .cpu_dmem_master_wready(core$cpu_dmem_master_wready), - .cpu_imem_master_arready(core$cpu_imem_master_arready), - .cpu_imem_master_awready(core$cpu_imem_master_awready), - .cpu_imem_master_bid(core$cpu_imem_master_bid), - .cpu_imem_master_bresp(core$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), - .cpu_imem_master_rdata(core$cpu_imem_master_rdata), - .cpu_imem_master_rid(core$cpu_imem_master_rid), - .cpu_imem_master_rlast(core$cpu_imem_master_rlast), - .cpu_imem_master_rresp(core$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), - .cpu_imem_master_wready(core$cpu_imem_master_wready), - .cpu_reset_server_request_put(core$cpu_reset_server_request_put), - .nmi_req_set_not_clear(core$nmi_req_set_not_clear), - .set_verbosity_logdelay(core$set_verbosity_logdelay), - .set_verbosity_verbosity(core$set_verbosity_verbosity), - .EN_set_verbosity(core$EN_set_verbosity), - .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get), - .RDY_set_verbosity(), - .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put), - .cpu_reset_server_response_get(), - .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), - .cpu_imem_master_awid(core$cpu_imem_master_awid), - .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr), - .cpu_imem_master_awlen(core$cpu_imem_master_awlen), - .cpu_imem_master_awsize(core$cpu_imem_master_awsize), - .cpu_imem_master_awburst(core$cpu_imem_master_awburst), - .cpu_imem_master_awlock(core$cpu_imem_master_awlock), - .cpu_imem_master_awcache(core$cpu_imem_master_awcache), - .cpu_imem_master_awprot(core$cpu_imem_master_awprot), - .cpu_imem_master_awqos(core$cpu_imem_master_awqos), - .cpu_imem_master_awregion(core$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), - .cpu_imem_master_wid(core$cpu_imem_master_wid), - .cpu_imem_master_wdata(core$cpu_imem_master_wdata), - .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb), - .cpu_imem_master_wlast(core$cpu_imem_master_wlast), - .cpu_imem_master_bready(core$cpu_imem_master_bready), - .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), - .cpu_imem_master_arid(core$cpu_imem_master_arid), - .cpu_imem_master_araddr(core$cpu_imem_master_araddr), - .cpu_imem_master_arlen(core$cpu_imem_master_arlen), - .cpu_imem_master_arsize(core$cpu_imem_master_arsize), - .cpu_imem_master_arburst(core$cpu_imem_master_arburst), - .cpu_imem_master_arlock(core$cpu_imem_master_arlock), - .cpu_imem_master_arcache(core$cpu_imem_master_arcache), - .cpu_imem_master_arprot(core$cpu_imem_master_arprot), - .cpu_imem_master_arqos(core$cpu_imem_master_arqos), - .cpu_imem_master_arregion(core$cpu_imem_master_arregion), - .cpu_imem_master_rready(core$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), - .cpu_dmem_master_awid(core$cpu_dmem_master_awid), - .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr), - .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen), - .cpu_dmem_master_awsize(core$cpu_dmem_master_awsize), - .cpu_dmem_master_awburst(core$cpu_dmem_master_awburst), - .cpu_dmem_master_awlock(core$cpu_dmem_master_awlock), - .cpu_dmem_master_awcache(core$cpu_dmem_master_awcache), - .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot), - .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos), - .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(core$cpu_dmem_master_wid), - .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata), - .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb), - .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast), - .cpu_dmem_master_bready(core$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), - .cpu_dmem_master_arid(core$cpu_dmem_master_arid), - .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr), - .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen), - .cpu_dmem_master_arsize(core$cpu_dmem_master_arsize), - .cpu_dmem_master_arburst(core$cpu_dmem_master_arburst), - .cpu_dmem_master_arlock(core$cpu_dmem_master_arlock), - .cpu_dmem_master_arcache(core$cpu_dmem_master_arcache), - .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot), - .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos), - .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion), - .cpu_dmem_master_rready(core$cpu_dmem_master_rready)); - - // submodule fabric - mkFabric_AXI4 fabric(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric$v_to_slaves_2_wready), - .EN_reset(fabric$EN_reset), - .EN_set_verbosity(fabric$EN_set_verbosity), - .RDY_reset(fabric$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric$v_to_slaves_2_rready)); - - // submodule mem0_controller - mkMem_Controller mem0_controller(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(mem0_controller$set_addr_map_addr_base), - .set_addr_map_addr_lim(mem0_controller$set_addr_map_addr_lim), - .set_watch_tohost_tohost_addr(mem0_controller$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(mem0_controller$set_watch_tohost_watch_tohost), - .slave_araddr(mem0_controller$slave_araddr), - .slave_arburst(mem0_controller$slave_arburst), - .slave_arcache(mem0_controller$slave_arcache), - .slave_arid(mem0_controller$slave_arid), - .slave_arlen(mem0_controller$slave_arlen), - .slave_arlock(mem0_controller$slave_arlock), - .slave_arprot(mem0_controller$slave_arprot), - .slave_arqos(mem0_controller$slave_arqos), - .slave_arregion(mem0_controller$slave_arregion), - .slave_arsize(mem0_controller$slave_arsize), - .slave_arvalid(mem0_controller$slave_arvalid), - .slave_awaddr(mem0_controller$slave_awaddr), - .slave_awburst(mem0_controller$slave_awburst), - .slave_awcache(mem0_controller$slave_awcache), - .slave_awid(mem0_controller$slave_awid), - .slave_awlen(mem0_controller$slave_awlen), - .slave_awlock(mem0_controller$slave_awlock), - .slave_awprot(mem0_controller$slave_awprot), - .slave_awqos(mem0_controller$slave_awqos), - .slave_awregion(mem0_controller$slave_awregion), - .slave_awsize(mem0_controller$slave_awsize), - .slave_awvalid(mem0_controller$slave_awvalid), - .slave_bready(mem0_controller$slave_bready), - .slave_rready(mem0_controller$slave_rready), - .slave_wdata(mem0_controller$slave_wdata), - .slave_wid(mem0_controller$slave_wid), - .slave_wlast(mem0_controller$slave_wlast), - .slave_wstrb(mem0_controller$slave_wstrb), - .slave_wvalid(mem0_controller$slave_wvalid), - .to_raw_mem_response_put(mem0_controller$to_raw_mem_response_put), - .EN_server_reset_request_put(mem0_controller$EN_server_reset_request_put), - .EN_server_reset_response_get(mem0_controller$EN_server_reset_response_get), - .EN_set_addr_map(mem0_controller$EN_set_addr_map), - .EN_to_raw_mem_request_get(mem0_controller$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(mem0_controller$EN_to_raw_mem_response_put), - .EN_set_watch_tohost(mem0_controller$EN_set_watch_tohost), - .RDY_server_reset_request_put(mem0_controller$RDY_server_reset_request_put), - .RDY_server_reset_response_get(mem0_controller$RDY_server_reset_response_get), - .RDY_set_addr_map(mem0_controller$RDY_set_addr_map), - .slave_awready(mem0_controller$slave_awready), - .slave_wready(mem0_controller$slave_wready), - .slave_bvalid(mem0_controller$slave_bvalid), - .slave_bid(mem0_controller$slave_bid), - .slave_bresp(mem0_controller$slave_bresp), - .slave_arready(mem0_controller$slave_arready), - .slave_rvalid(mem0_controller$slave_rvalid), - .slave_rid(mem0_controller$slave_rid), - .slave_rdata(mem0_controller$slave_rdata), - .slave_rresp(mem0_controller$slave_rresp), - .slave_rlast(mem0_controller$slave_rlast), - .to_raw_mem_request_get(mem0_controller$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(mem0_controller$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(mem0_controller$RDY_to_raw_mem_response_put), - .status(mem0_controller$status), - .RDY_set_watch_tohost()); - - // submodule mem0_controller_axi4_deburster - mkAXI4_Deburster_A mem0_controller_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(mem0_controller_axi4_deburster$from_master_araddr), - .from_master_arburst(mem0_controller_axi4_deburster$from_master_arburst), - .from_master_arcache(mem0_controller_axi4_deburster$from_master_arcache), - .from_master_arid(mem0_controller_axi4_deburster$from_master_arid), - .from_master_arlen(mem0_controller_axi4_deburster$from_master_arlen), - .from_master_arlock(mem0_controller_axi4_deburster$from_master_arlock), - .from_master_arprot(mem0_controller_axi4_deburster$from_master_arprot), - .from_master_arqos(mem0_controller_axi4_deburster$from_master_arqos), - .from_master_arregion(mem0_controller_axi4_deburster$from_master_arregion), - .from_master_arsize(mem0_controller_axi4_deburster$from_master_arsize), - .from_master_arvalid(mem0_controller_axi4_deburster$from_master_arvalid), - .from_master_awaddr(mem0_controller_axi4_deburster$from_master_awaddr), - .from_master_awburst(mem0_controller_axi4_deburster$from_master_awburst), - .from_master_awcache(mem0_controller_axi4_deburster$from_master_awcache), - .from_master_awid(mem0_controller_axi4_deburster$from_master_awid), - .from_master_awlen(mem0_controller_axi4_deburster$from_master_awlen), - .from_master_awlock(mem0_controller_axi4_deburster$from_master_awlock), - .from_master_awprot(mem0_controller_axi4_deburster$from_master_awprot), - .from_master_awqos(mem0_controller_axi4_deburster$from_master_awqos), - .from_master_awregion(mem0_controller_axi4_deburster$from_master_awregion), - .from_master_awsize(mem0_controller_axi4_deburster$from_master_awsize), - .from_master_awvalid(mem0_controller_axi4_deburster$from_master_awvalid), - .from_master_bready(mem0_controller_axi4_deburster$from_master_bready), - .from_master_rready(mem0_controller_axi4_deburster$from_master_rready), - .from_master_wdata(mem0_controller_axi4_deburster$from_master_wdata), - .from_master_wid(mem0_controller_axi4_deburster$from_master_wid), - .from_master_wlast(mem0_controller_axi4_deburster$from_master_wlast), - .from_master_wstrb(mem0_controller_axi4_deburster$from_master_wstrb), - .from_master_wvalid(mem0_controller_axi4_deburster$from_master_wvalid), - .to_slave_arready(mem0_controller_axi4_deburster$to_slave_arready), - .to_slave_awready(mem0_controller_axi4_deburster$to_slave_awready), - .to_slave_bid(mem0_controller_axi4_deburster$to_slave_bid), - .to_slave_bresp(mem0_controller_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(mem0_controller_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(mem0_controller_axi4_deburster$to_slave_rdata), - .to_slave_rid(mem0_controller_axi4_deburster$to_slave_rid), - .to_slave_rlast(mem0_controller_axi4_deburster$to_slave_rlast), - .to_slave_rresp(mem0_controller_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(mem0_controller_axi4_deburster$to_slave_rvalid), - .to_slave_wready(mem0_controller_axi4_deburster$to_slave_wready), - .EN_reset(mem0_controller_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(mem0_controller_axi4_deburster$from_master_awready), - .from_master_wready(mem0_controller_axi4_deburster$from_master_wready), - .from_master_bvalid(mem0_controller_axi4_deburster$from_master_bvalid), - .from_master_bid(mem0_controller_axi4_deburster$from_master_bid), - .from_master_bresp(mem0_controller_axi4_deburster$from_master_bresp), - .from_master_arready(mem0_controller_axi4_deburster$from_master_arready), - .from_master_rvalid(mem0_controller_axi4_deburster$from_master_rvalid), - .from_master_rid(mem0_controller_axi4_deburster$from_master_rid), - .from_master_rdata(mem0_controller_axi4_deburster$from_master_rdata), - .from_master_rresp(mem0_controller_axi4_deburster$from_master_rresp), - .from_master_rlast(mem0_controller_axi4_deburster$from_master_rlast), - .to_slave_awvalid(mem0_controller_axi4_deburster$to_slave_awvalid), - .to_slave_awid(mem0_controller_axi4_deburster$to_slave_awid), - .to_slave_awaddr(mem0_controller_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(mem0_controller_axi4_deburster$to_slave_awlen), - .to_slave_awsize(mem0_controller_axi4_deburster$to_slave_awsize), - .to_slave_awburst(mem0_controller_axi4_deburster$to_slave_awburst), - .to_slave_awlock(mem0_controller_axi4_deburster$to_slave_awlock), - .to_slave_awcache(mem0_controller_axi4_deburster$to_slave_awcache), - .to_slave_awprot(mem0_controller_axi4_deburster$to_slave_awprot), - .to_slave_awqos(mem0_controller_axi4_deburster$to_slave_awqos), - .to_slave_awregion(mem0_controller_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(mem0_controller_axi4_deburster$to_slave_wvalid), - .to_slave_wid(mem0_controller_axi4_deburster$to_slave_wid), - .to_slave_wdata(mem0_controller_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(mem0_controller_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(mem0_controller_axi4_deburster$to_slave_wlast), - .to_slave_bready(mem0_controller_axi4_deburster$to_slave_bready), - .to_slave_arvalid(mem0_controller_axi4_deburster$to_slave_arvalid), - .to_slave_arid(mem0_controller_axi4_deburster$to_slave_arid), - .to_slave_araddr(mem0_controller_axi4_deburster$to_slave_araddr), - .to_slave_arlen(mem0_controller_axi4_deburster$to_slave_arlen), - .to_slave_arsize(mem0_controller_axi4_deburster$to_slave_arsize), - .to_slave_arburst(mem0_controller_axi4_deburster$to_slave_arburst), - .to_slave_arlock(mem0_controller_axi4_deburster$to_slave_arlock), - .to_slave_arcache(mem0_controller_axi4_deburster$to_slave_arcache), - .to_slave_arprot(mem0_controller_axi4_deburster$to_slave_arprot), - .to_slave_arqos(mem0_controller_axi4_deburster$to_slave_arqos), - .to_slave_arregion(mem0_controller_axi4_deburster$to_slave_arregion), - .to_slave_rready(mem0_controller_axi4_deburster$to_slave_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule uart0 - mkUART uart0(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(uart0$put_from_console_put), - .set_addr_map_addr_base(uart0$set_addr_map_addr_base), - .set_addr_map_addr_lim(uart0$set_addr_map_addr_lim), - .slave_araddr(uart0$slave_araddr), - .slave_arburst(uart0$slave_arburst), - .slave_arcache(uart0$slave_arcache), - .slave_arid(uart0$slave_arid), - .slave_arlen(uart0$slave_arlen), - .slave_arlock(uart0$slave_arlock), - .slave_arprot(uart0$slave_arprot), - .slave_arqos(uart0$slave_arqos), - .slave_arregion(uart0$slave_arregion), - .slave_arsize(uart0$slave_arsize), - .slave_arvalid(uart0$slave_arvalid), - .slave_awaddr(uart0$slave_awaddr), - .slave_awburst(uart0$slave_awburst), - .slave_awcache(uart0$slave_awcache), - .slave_awid(uart0$slave_awid), - .slave_awlen(uart0$slave_awlen), - .slave_awlock(uart0$slave_awlock), - .slave_awprot(uart0$slave_awprot), - .slave_awqos(uart0$slave_awqos), - .slave_awregion(uart0$slave_awregion), - .slave_awsize(uart0$slave_awsize), - .slave_awvalid(uart0$slave_awvalid), - .slave_bready(uart0$slave_bready), - .slave_rready(uart0$slave_rready), - .slave_wdata(uart0$slave_wdata), - .slave_wid(uart0$slave_wid), - .slave_wlast(uart0$slave_wlast), - .slave_wstrb(uart0$slave_wstrb), - .slave_wvalid(uart0$slave_wvalid), - .EN_server_reset_request_put(uart0$EN_server_reset_request_put), - .EN_server_reset_response_get(uart0$EN_server_reset_response_get), - .EN_set_addr_map(uart0$EN_set_addr_map), - .EN_get_to_console_get(uart0$EN_get_to_console_get), - .EN_put_from_console_put(uart0$EN_put_from_console_put), - .RDY_server_reset_request_put(uart0$RDY_server_reset_request_put), - .RDY_server_reset_response_get(uart0$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .slave_awready(uart0$slave_awready), - .slave_wready(uart0$slave_wready), - .slave_bvalid(uart0$slave_bvalid), - .slave_bid(uart0$slave_bid), - .slave_bresp(uart0$slave_bresp), - .slave_arready(uart0$slave_arready), - .slave_rvalid(uart0$slave_rvalid), - .slave_rid(uart0$slave_rid), - .slave_rdata(uart0$slave_rdata), - .slave_rresp(uart0$slave_rresp), - .slave_rlast(uart0$slave_rlast), - .get_to_console_get(uart0$get_to_console_get), - .RDY_get_to_console_get(uart0$RDY_get_to_console_get), - .RDY_put_from_console_put(uart0$RDY_put_from_console_put), - .intr(uart0$intr)); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_5 - assign CAN_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - - // rule RL_rl_wr_data_channel_5 - assign CAN_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_response_channel_5 - assign CAN_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_5 - assign CAN_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - - // rule RL_rl_rd_data_channel_5 - assign CAN_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_6 - assign CAN_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - - // rule RL_rl_wr_data_channel_6 - assign CAN_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - - // rule RL_rl_wr_response_channel_6 - assign CAN_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_6 - assign CAN_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - - // rule RL_rl_rd_data_channel_6 - assign CAN_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - - // rule RL_rl_connect_external_interrupt_requests - assign CAN_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - - // rule RL_rl_reset_start_initial - assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete_initial - assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete_initial = - MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = - mem0_controller$RDY_server_reset_request_put && - uart0$RDY_server_reset_request_put && - fabric$RDY_reset && - core$RDY_cpu_reset_server_request_put && - rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && - mem0_controller$RDY_server_reset_response_get && - uart0$RDY_server_reset_response_get && - core$RDY_cpu_reset_server_response_get && - rg_state == 2'd1 ; - - // register rg_state - assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_start_initial || - WILL_FIRE_RL_rl_reset_complete_initial ; - - // submodule boot_rom - assign boot_rom$set_addr_map_addr_base = soc_map$m_boot_rom_addr_base ; - assign boot_rom$set_addr_map_addr_lim = soc_map$m_boot_rom_addr_lim ; - assign boot_rom$slave_araddr = boot_rom_axi4_deburster$to_slave_araddr ; - assign boot_rom$slave_arburst = boot_rom_axi4_deburster$to_slave_arburst ; - assign boot_rom$slave_arcache = boot_rom_axi4_deburster$to_slave_arcache ; - assign boot_rom$slave_arid = boot_rom_axi4_deburster$to_slave_arid ; - assign boot_rom$slave_arlen = boot_rom_axi4_deburster$to_slave_arlen ; - assign boot_rom$slave_arlock = boot_rom_axi4_deburster$to_slave_arlock ; - assign boot_rom$slave_arprot = boot_rom_axi4_deburster$to_slave_arprot ; - assign boot_rom$slave_arqos = boot_rom_axi4_deburster$to_slave_arqos ; - assign boot_rom$slave_arregion = boot_rom_axi4_deburster$to_slave_arregion ; - assign boot_rom$slave_arsize = boot_rom_axi4_deburster$to_slave_arsize ; - assign boot_rom$slave_arvalid = boot_rom_axi4_deburster$to_slave_arvalid ; - assign boot_rom$slave_awaddr = boot_rom_axi4_deburster$to_slave_awaddr ; - assign boot_rom$slave_awburst = boot_rom_axi4_deburster$to_slave_awburst ; - assign boot_rom$slave_awcache = boot_rom_axi4_deburster$to_slave_awcache ; - assign boot_rom$slave_awid = boot_rom_axi4_deburster$to_slave_awid ; - assign boot_rom$slave_awlen = boot_rom_axi4_deburster$to_slave_awlen ; - assign boot_rom$slave_awlock = boot_rom_axi4_deburster$to_slave_awlock ; - assign boot_rom$slave_awprot = boot_rom_axi4_deburster$to_slave_awprot ; - assign boot_rom$slave_awqos = boot_rom_axi4_deburster$to_slave_awqos ; - assign boot_rom$slave_awregion = boot_rom_axi4_deburster$to_slave_awregion ; - assign boot_rom$slave_awsize = boot_rom_axi4_deburster$to_slave_awsize ; - assign boot_rom$slave_awvalid = boot_rom_axi4_deburster$to_slave_awvalid ; - assign boot_rom$slave_bready = boot_rom_axi4_deburster$to_slave_bready ; - assign boot_rom$slave_rready = boot_rom_axi4_deburster$to_slave_rready ; - assign boot_rom$slave_wdata = boot_rom_axi4_deburster$to_slave_wdata ; - assign boot_rom$slave_wid = boot_rom_axi4_deburster$to_slave_wid ; - assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; - assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; - assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - - // submodule boot_rom_axi4_deburster - assign boot_rom_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_0_araddr ; - assign boot_rom_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_0_arburst ; - assign boot_rom_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_0_arcache ; - assign boot_rom_axi4_deburster$from_master_arid = - fabric$v_to_slaves_0_arid ; - assign boot_rom_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_0_arlen ; - assign boot_rom_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_0_arlock ; - assign boot_rom_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_0_arprot ; - assign boot_rom_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_0_arqos ; - assign boot_rom_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_0_arregion ; - assign boot_rom_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_0_arsize ; - assign boot_rom_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_0_arvalid ; - assign boot_rom_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_0_awaddr ; - assign boot_rom_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_0_awburst ; - assign boot_rom_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_0_awcache ; - assign boot_rom_axi4_deburster$from_master_awid = - fabric$v_to_slaves_0_awid ; - assign boot_rom_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_0_awlen ; - assign boot_rom_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_0_awlock ; - assign boot_rom_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_0_awprot ; - assign boot_rom_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_0_awqos ; - assign boot_rom_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_0_awregion ; - assign boot_rom_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_0_awsize ; - assign boot_rom_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_0_awvalid ; - assign boot_rom_axi4_deburster$from_master_bready = - fabric$v_to_slaves_0_bready ; - assign boot_rom_axi4_deburster$from_master_rready = - fabric$v_to_slaves_0_rready ; - assign boot_rom_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_0_wdata ; - assign boot_rom_axi4_deburster$from_master_wid = fabric$v_to_slaves_0_wid ; - assign boot_rom_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_0_wlast ; - assign boot_rom_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_0_wstrb ; - assign boot_rom_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_0_wvalid ; - assign boot_rom_axi4_deburster$to_slave_arready = boot_rom$slave_arready ; - assign boot_rom_axi4_deburster$to_slave_awready = boot_rom$slave_awready ; - assign boot_rom_axi4_deburster$to_slave_bid = boot_rom$slave_bid ; - assign boot_rom_axi4_deburster$to_slave_bresp = boot_rom$slave_bresp ; - assign boot_rom_axi4_deburster$to_slave_bvalid = boot_rom$slave_bvalid ; - assign boot_rom_axi4_deburster$to_slave_rdata = boot_rom$slave_rdata ; - assign boot_rom_axi4_deburster$to_slave_rid = boot_rom$slave_rid ; - assign boot_rom_axi4_deburster$to_slave_rlast = boot_rom$slave_rlast ; - assign boot_rom_axi4_deburster$to_slave_rresp = boot_rom$slave_rresp ; - assign boot_rom_axi4_deburster$to_slave_rvalid = boot_rom$slave_rvalid ; - assign boot_rom_axi4_deburster$to_slave_wready = boot_rom$slave_wready ; - assign boot_rom_axi4_deburster$EN_reset = 1'b0 ; - - // submodule core - assign core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = - uart0$intr ; - assign core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$cpu_dmem_master_arready = fabric$v_from_masters_1_arready ; - assign core$cpu_dmem_master_awready = fabric$v_from_masters_1_awready ; - assign core$cpu_dmem_master_bid = fabric$v_from_masters_1_bid ; - assign core$cpu_dmem_master_bresp = fabric$v_from_masters_1_bresp ; - assign core$cpu_dmem_master_bvalid = fabric$v_from_masters_1_bvalid ; - assign core$cpu_dmem_master_rdata = fabric$v_from_masters_1_rdata ; - assign core$cpu_dmem_master_rid = fabric$v_from_masters_1_rid ; - assign core$cpu_dmem_master_rlast = fabric$v_from_masters_1_rlast ; - assign core$cpu_dmem_master_rresp = fabric$v_from_masters_1_rresp ; - assign core$cpu_dmem_master_rvalid = fabric$v_from_masters_1_rvalid ; - assign core$cpu_dmem_master_wready = fabric$v_from_masters_1_wready ; - assign core$cpu_imem_master_arready = fabric$v_from_masters_0_arready ; - assign core$cpu_imem_master_awready = fabric$v_from_masters_0_awready ; - assign core$cpu_imem_master_bid = fabric$v_from_masters_0_bid ; - assign core$cpu_imem_master_bresp = fabric$v_from_masters_0_bresp ; - assign core$cpu_imem_master_bvalid = fabric$v_from_masters_0_bvalid ; - assign core$cpu_imem_master_rdata = fabric$v_from_masters_0_rdata ; - assign core$cpu_imem_master_rid = fabric$v_from_masters_0_rid ; - assign core$cpu_imem_master_rlast = fabric$v_from_masters_0_rlast ; - assign core$cpu_imem_master_rresp = fabric$v_from_masters_0_rresp ; - assign core$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ; - assign core$cpu_imem_master_wready = fabric$v_from_masters_0_wready ; - assign core$cpu_reset_server_request_put = 1'd1 ; - assign core$nmi_req_set_not_clear = 1'd0 ; - assign core$set_verbosity_logdelay = set_verbosity_logdelay ; - assign core$set_verbosity_verbosity = set_verbosity_verbosity ; - assign core$EN_set_verbosity = EN_set_verbosity ; - assign core$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; - assign core$EN_cpu_reset_server_response_get = MUX_rg_state$write_1__SEL_2 ; - - // submodule fabric - assign fabric$set_verbosity_verbosity = 4'h0 ; - assign fabric$v_from_masters_0_araddr = core$cpu_imem_master_araddr ; - assign fabric$v_from_masters_0_arburst = core$cpu_imem_master_arburst ; - assign fabric$v_from_masters_0_arcache = core$cpu_imem_master_arcache ; - assign fabric$v_from_masters_0_arid = core$cpu_imem_master_arid ; - assign fabric$v_from_masters_0_arlen = core$cpu_imem_master_arlen ; - assign fabric$v_from_masters_0_arlock = core$cpu_imem_master_arlock ; - assign fabric$v_from_masters_0_arprot = core$cpu_imem_master_arprot ; - assign fabric$v_from_masters_0_arqos = core$cpu_imem_master_arqos ; - assign fabric$v_from_masters_0_arregion = core$cpu_imem_master_arregion ; - assign fabric$v_from_masters_0_arsize = core$cpu_imem_master_arsize ; - assign fabric$v_from_masters_0_arvalid = core$cpu_imem_master_arvalid ; - assign fabric$v_from_masters_0_awaddr = core$cpu_imem_master_awaddr ; - assign fabric$v_from_masters_0_awburst = core$cpu_imem_master_awburst ; - assign fabric$v_from_masters_0_awcache = core$cpu_imem_master_awcache ; - assign fabric$v_from_masters_0_awid = core$cpu_imem_master_awid ; - assign fabric$v_from_masters_0_awlen = core$cpu_imem_master_awlen ; - assign fabric$v_from_masters_0_awlock = core$cpu_imem_master_awlock ; - assign fabric$v_from_masters_0_awprot = core$cpu_imem_master_awprot ; - assign fabric$v_from_masters_0_awqos = core$cpu_imem_master_awqos ; - assign fabric$v_from_masters_0_awregion = core$cpu_imem_master_awregion ; - assign fabric$v_from_masters_0_awsize = core$cpu_imem_master_awsize ; - assign fabric$v_from_masters_0_awvalid = core$cpu_imem_master_awvalid ; - assign fabric$v_from_masters_0_bready = core$cpu_imem_master_bready ; - assign fabric$v_from_masters_0_rready = core$cpu_imem_master_rready ; - assign fabric$v_from_masters_0_wdata = core$cpu_imem_master_wdata ; - assign fabric$v_from_masters_0_wid = core$cpu_imem_master_wid ; - assign fabric$v_from_masters_0_wlast = core$cpu_imem_master_wlast ; - assign fabric$v_from_masters_0_wstrb = core$cpu_imem_master_wstrb ; - assign fabric$v_from_masters_0_wvalid = core$cpu_imem_master_wvalid ; - assign fabric$v_from_masters_1_araddr = core$cpu_dmem_master_araddr ; - assign fabric$v_from_masters_1_arburst = core$cpu_dmem_master_arburst ; - assign fabric$v_from_masters_1_arcache = core$cpu_dmem_master_arcache ; - assign fabric$v_from_masters_1_arid = core$cpu_dmem_master_arid ; - assign fabric$v_from_masters_1_arlen = core$cpu_dmem_master_arlen ; - assign fabric$v_from_masters_1_arlock = core$cpu_dmem_master_arlock ; - assign fabric$v_from_masters_1_arprot = core$cpu_dmem_master_arprot ; - assign fabric$v_from_masters_1_arqos = core$cpu_dmem_master_arqos ; - assign fabric$v_from_masters_1_arregion = core$cpu_dmem_master_arregion ; - assign fabric$v_from_masters_1_arsize = core$cpu_dmem_master_arsize ; - assign fabric$v_from_masters_1_arvalid = core$cpu_dmem_master_arvalid ; - assign fabric$v_from_masters_1_awaddr = core$cpu_dmem_master_awaddr ; - assign fabric$v_from_masters_1_awburst = core$cpu_dmem_master_awburst ; - assign fabric$v_from_masters_1_awcache = core$cpu_dmem_master_awcache ; - assign fabric$v_from_masters_1_awid = core$cpu_dmem_master_awid ; - assign fabric$v_from_masters_1_awlen = core$cpu_dmem_master_awlen ; - assign fabric$v_from_masters_1_awlock = core$cpu_dmem_master_awlock ; - assign fabric$v_from_masters_1_awprot = core$cpu_dmem_master_awprot ; - assign fabric$v_from_masters_1_awqos = core$cpu_dmem_master_awqos ; - assign fabric$v_from_masters_1_awregion = core$cpu_dmem_master_awregion ; - assign fabric$v_from_masters_1_awsize = core$cpu_dmem_master_awsize ; - assign fabric$v_from_masters_1_awvalid = core$cpu_dmem_master_awvalid ; - assign fabric$v_from_masters_1_bready = core$cpu_dmem_master_bready ; - assign fabric$v_from_masters_1_rready = core$cpu_dmem_master_rready ; - assign fabric$v_from_masters_1_wdata = core$cpu_dmem_master_wdata ; - assign fabric$v_from_masters_1_wid = core$cpu_dmem_master_wid ; - assign fabric$v_from_masters_1_wlast = core$cpu_dmem_master_wlast ; - assign fabric$v_from_masters_1_wstrb = core$cpu_dmem_master_wstrb ; - assign fabric$v_from_masters_1_wvalid = core$cpu_dmem_master_wvalid ; - assign fabric$v_to_slaves_0_arready = - boot_rom_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_0_awready = - boot_rom_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_0_bid = boot_rom_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_0_bresp = - boot_rom_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_0_bvalid = - boot_rom_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_0_rdata = - boot_rom_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_0_rid = boot_rom_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_0_rlast = - boot_rom_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_0_rresp = - boot_rom_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_0_rvalid = - boot_rom_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_0_wready = - boot_rom_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_1_arready = - mem0_controller_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_1_awready = - mem0_controller_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_1_bid = - mem0_controller_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_1_bresp = - mem0_controller_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_1_bvalid = - mem0_controller_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_1_rdata = - mem0_controller_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_1_rid = - mem0_controller_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_1_rlast = - mem0_controller_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_1_rresp = - mem0_controller_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_1_rvalid = - mem0_controller_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_1_wready = - mem0_controller_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_2_arready = uart0$slave_arready ; - assign fabric$v_to_slaves_2_awready = uart0$slave_awready ; - assign fabric$v_to_slaves_2_bid = uart0$slave_bid ; - assign fabric$v_to_slaves_2_bresp = uart0$slave_bresp ; - assign fabric$v_to_slaves_2_bvalid = uart0$slave_bvalid ; - assign fabric$v_to_slaves_2_rdata = uart0$slave_rdata ; - assign fabric$v_to_slaves_2_rid = uart0$slave_rid ; - assign fabric$v_to_slaves_2_rlast = uart0$slave_rlast ; - assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; - assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; - assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; - assign fabric$EN_set_verbosity = 1'b0 ; - - // submodule mem0_controller - assign mem0_controller$set_addr_map_addr_base = - soc_map$m_mem0_controller_addr_base ; - assign mem0_controller$set_addr_map_addr_lim = - soc_map$m_mem0_controller_addr_lim ; - assign mem0_controller$set_watch_tohost_tohost_addr = - set_watch_tohost_tohost_addr ; - assign mem0_controller$set_watch_tohost_watch_tohost = - set_watch_tohost_watch_tohost ; - assign mem0_controller$slave_araddr = - mem0_controller_axi4_deburster$to_slave_araddr ; - assign mem0_controller$slave_arburst = - mem0_controller_axi4_deburster$to_slave_arburst ; - assign mem0_controller$slave_arcache = - mem0_controller_axi4_deburster$to_slave_arcache ; - assign mem0_controller$slave_arid = - mem0_controller_axi4_deburster$to_slave_arid ; - assign mem0_controller$slave_arlen = - mem0_controller_axi4_deburster$to_slave_arlen ; - assign mem0_controller$slave_arlock = - mem0_controller_axi4_deburster$to_slave_arlock ; - assign mem0_controller$slave_arprot = - mem0_controller_axi4_deburster$to_slave_arprot ; - assign mem0_controller$slave_arqos = - mem0_controller_axi4_deburster$to_slave_arqos ; - assign mem0_controller$slave_arregion = - mem0_controller_axi4_deburster$to_slave_arregion ; - assign mem0_controller$slave_arsize = - mem0_controller_axi4_deburster$to_slave_arsize ; - assign mem0_controller$slave_arvalid = - mem0_controller_axi4_deburster$to_slave_arvalid ; - assign mem0_controller$slave_awaddr = - mem0_controller_axi4_deburster$to_slave_awaddr ; - assign mem0_controller$slave_awburst = - mem0_controller_axi4_deburster$to_slave_awburst ; - assign mem0_controller$slave_awcache = - mem0_controller_axi4_deburster$to_slave_awcache ; - assign mem0_controller$slave_awid = - mem0_controller_axi4_deburster$to_slave_awid ; - assign mem0_controller$slave_awlen = - mem0_controller_axi4_deburster$to_slave_awlen ; - assign mem0_controller$slave_awlock = - mem0_controller_axi4_deburster$to_slave_awlock ; - assign mem0_controller$slave_awprot = - mem0_controller_axi4_deburster$to_slave_awprot ; - assign mem0_controller$slave_awqos = - mem0_controller_axi4_deburster$to_slave_awqos ; - assign mem0_controller$slave_awregion = - mem0_controller_axi4_deburster$to_slave_awregion ; - assign mem0_controller$slave_awsize = - mem0_controller_axi4_deburster$to_slave_awsize ; - assign mem0_controller$slave_awvalid = - mem0_controller_axi4_deburster$to_slave_awvalid ; - assign mem0_controller$slave_bready = - mem0_controller_axi4_deburster$to_slave_bready ; - assign mem0_controller$slave_rready = - mem0_controller_axi4_deburster$to_slave_rready ; - assign mem0_controller$slave_wdata = - mem0_controller_axi4_deburster$to_slave_wdata ; - assign mem0_controller$slave_wid = - mem0_controller_axi4_deburster$to_slave_wid ; - assign mem0_controller$slave_wlast = - mem0_controller_axi4_deburster$to_slave_wlast ; - assign mem0_controller$slave_wstrb = - mem0_controller_axi4_deburster$to_slave_wstrb ; - assign mem0_controller$slave_wvalid = - mem0_controller_axi4_deburster$to_slave_wvalid ; - assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; - assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; - assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_to_raw_mem_request_get = - EN_to_raw_mem_request_get ; - assign mem0_controller$EN_to_raw_mem_response_put = - EN_to_raw_mem_response_put ; - assign mem0_controller$EN_set_watch_tohost = EN_set_watch_tohost ; - - // submodule mem0_controller_axi4_deburster - assign mem0_controller_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_1_araddr ; - assign mem0_controller_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_1_arburst ; - assign mem0_controller_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_1_arcache ; - assign mem0_controller_axi4_deburster$from_master_arid = - fabric$v_to_slaves_1_arid ; - assign mem0_controller_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_1_arlen ; - assign mem0_controller_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_1_arlock ; - assign mem0_controller_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_1_arprot ; - assign mem0_controller_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_1_arqos ; - assign mem0_controller_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_1_arregion ; - assign mem0_controller_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_1_arsize ; - assign mem0_controller_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_1_arvalid ; - assign mem0_controller_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_1_awaddr ; - assign mem0_controller_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_1_awburst ; - assign mem0_controller_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_1_awcache ; - assign mem0_controller_axi4_deburster$from_master_awid = - fabric$v_to_slaves_1_awid ; - assign mem0_controller_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_1_awlen ; - assign mem0_controller_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_1_awlock ; - assign mem0_controller_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_1_awprot ; - assign mem0_controller_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_1_awqos ; - assign mem0_controller_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_1_awregion ; - assign mem0_controller_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_1_awsize ; - assign mem0_controller_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_1_awvalid ; - assign mem0_controller_axi4_deburster$from_master_bready = - fabric$v_to_slaves_1_bready ; - assign mem0_controller_axi4_deburster$from_master_rready = - fabric$v_to_slaves_1_rready ; - assign mem0_controller_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_1_wdata ; - assign mem0_controller_axi4_deburster$from_master_wid = - fabric$v_to_slaves_1_wid ; - assign mem0_controller_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_1_wlast ; - assign mem0_controller_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_1_wstrb ; - assign mem0_controller_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_1_wvalid ; - assign mem0_controller_axi4_deburster$to_slave_arready = - mem0_controller$slave_arready ; - assign mem0_controller_axi4_deburster$to_slave_awready = - mem0_controller$slave_awready ; - assign mem0_controller_axi4_deburster$to_slave_bid = - mem0_controller$slave_bid ; - assign mem0_controller_axi4_deburster$to_slave_bresp = - mem0_controller$slave_bresp ; - assign mem0_controller_axi4_deburster$to_slave_bvalid = - mem0_controller$slave_bvalid ; - assign mem0_controller_axi4_deburster$to_slave_rdata = - mem0_controller$slave_rdata ; - assign mem0_controller_axi4_deburster$to_slave_rid = - mem0_controller$slave_rid ; - assign mem0_controller_axi4_deburster$to_slave_rlast = - mem0_controller$slave_rlast ; - assign mem0_controller_axi4_deburster$to_slave_rresp = - mem0_controller$slave_rresp ; - assign mem0_controller_axi4_deburster$to_slave_rvalid = - mem0_controller$slave_rvalid ; - assign mem0_controller_axi4_deburster$to_slave_wready = - mem0_controller$slave_wready ; - assign mem0_controller_axi4_deburster$EN_reset = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule uart0 - assign uart0$put_from_console_put = put_from_console_put ; - assign uart0$set_addr_map_addr_base = soc_map$m_uart0_addr_base ; - assign uart0$set_addr_map_addr_lim = soc_map$m_uart0_addr_lim ; - assign uart0$slave_araddr = fabric$v_to_slaves_2_araddr ; - assign uart0$slave_arburst = fabric$v_to_slaves_2_arburst ; - assign uart0$slave_arcache = fabric$v_to_slaves_2_arcache ; - assign uart0$slave_arid = fabric$v_to_slaves_2_arid ; - assign uart0$slave_arlen = fabric$v_to_slaves_2_arlen ; - assign uart0$slave_arlock = fabric$v_to_slaves_2_arlock ; - assign uart0$slave_arprot = fabric$v_to_slaves_2_arprot ; - assign uart0$slave_arqos = fabric$v_to_slaves_2_arqos ; - assign uart0$slave_arregion = fabric$v_to_slaves_2_arregion ; - assign uart0$slave_arsize = fabric$v_to_slaves_2_arsize ; - assign uart0$slave_arvalid = fabric$v_to_slaves_2_arvalid ; - assign uart0$slave_awaddr = fabric$v_to_slaves_2_awaddr ; - assign uart0$slave_awburst = fabric$v_to_slaves_2_awburst ; - assign uart0$slave_awcache = fabric$v_to_slaves_2_awcache ; - assign uart0$slave_awid = fabric$v_to_slaves_2_awid ; - assign uart0$slave_awlen = fabric$v_to_slaves_2_awlen ; - assign uart0$slave_awlock = fabric$v_to_slaves_2_awlock ; - assign uart0$slave_awprot = fabric$v_to_slaves_2_awprot ; - assign uart0$slave_awqos = fabric$v_to_slaves_2_awqos ; - assign uart0$slave_awregion = fabric$v_to_slaves_2_awregion ; - assign uart0$slave_awsize = fabric$v_to_slaves_2_awsize ; - assign uart0$slave_awvalid = fabric$v_to_slaves_2_awvalid ; - assign uart0$slave_bready = fabric$v_to_slaves_2_bready ; - assign uart0$slave_rready = fabric$v_to_slaves_2_rready ; - assign uart0$slave_wdata = fabric$v_to_slaves_2_wdata ; - assign uart0$slave_wid = fabric$v_to_slaves_2_wid ; - assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; - assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; - assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_get_to_console_get = EN_get_to_console_get ; - assign uart0$EN_put_from_console_put = EN_put_from_console_put ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - begin - v__h11286 = $stime; - #0; - end - v__h11280 = v__h11286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - $display("%0d:%m.rl_reset_start_initial ...", v__h11280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - begin - v__h11556 = $stime; - #0; - end - v__h11550 = v__h11556 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - $display("%0d:%m.rl_reset_complete_initial", v__h11550); - end - // synopsys translate_on -endmodule // mkSoC_Top - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTLB.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTLB.v deleted file mode 100644 index 824d1ae3..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTLB.v +++ /dev/null @@ -1,617 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_flush O 1 const -// lookup O 131 -// RDY_lookup O 1 -// RDY_insert O 1 -// CLK I 1 clock -// RST_N I 1 reset -// lookup_asid I 16 -// lookup_vpn I 27 -// insert_asid I 16 reg -// insert_vpn I 27 -// insert_pte I 64 reg -// insert_level I 2 -// insert_pte_pa I 64 reg -// EN_flush I 1 -// EN_insert I 1 -// -// Combinational paths from inputs to outputs: -// (lookup_asid, lookup_vpn) -> lookup -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTLB(CLK, - RST_N, - - EN_flush, - RDY_flush, - - lookup_asid, - lookup_vpn, - lookup, - RDY_lookup, - - insert_asid, - insert_vpn, - insert_pte, - insert_level, - insert_pte_pa, - EN_insert, - RDY_insert); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method flush - input EN_flush; - output RDY_flush; - - // value method lookup - input [15 : 0] lookup_asid; - input [26 : 0] lookup_vpn; - output [130 : 0] lookup; - output RDY_lookup; - - // action method insert - input [15 : 0] insert_asid; - input [26 : 0] insert_vpn; - input [63 : 0] insert_pte; - input [1 : 0] insert_level; - input [63 : 0] insert_pte_pa; - input EN_insert; - output RDY_insert; - - // signals for module outputs - wire [130 : 0] lookup; - wire RDY_flush, RDY_insert, RDY_lookup; - - // register rg_flushing - reg rg_flushing; - wire rg_flushing$D_IN, rg_flushing$EN; - - // register tlb0_valids_0 - reg tlb0_valids_0; - wire tlb0_valids_0$D_IN, tlb0_valids_0$EN; - - // register tlb0_valids_1 - reg tlb0_valids_1; - wire tlb0_valids_1$D_IN, tlb0_valids_1$EN; - - // register tlb0_valids_2 - reg tlb0_valids_2; - wire tlb0_valids_2$D_IN, tlb0_valids_2$EN; - - // register tlb0_valids_3 - reg tlb0_valids_3; - wire tlb0_valids_3$D_IN, tlb0_valids_3$EN; - - // register tlb1_valids_0 - reg tlb1_valids_0; - wire tlb1_valids_0$D_IN, tlb1_valids_0$EN; - - // register tlb1_valids_1 - reg tlb1_valids_1; - wire tlb1_valids_1$D_IN, tlb1_valids_1$EN; - - // register tlb1_valids_2 - reg tlb1_valids_2; - wire tlb1_valids_2$D_IN, tlb1_valids_2$EN; - - // register tlb1_valids_3 - reg tlb1_valids_3; - wire tlb1_valids_3$D_IN, tlb1_valids_3$EN; - - // register tlb2_valids_0 - reg tlb2_valids_0; - wire tlb2_valids_0$D_IN, tlb2_valids_0$EN; - - // register tlb2_valids_1 - reg tlb2_valids_1; - wire tlb2_valids_1$D_IN, tlb2_valids_1$EN; - - // register tlb2_valids_2 - reg tlb2_valids_2; - wire tlb2_valids_2$D_IN, tlb2_valids_2$EN; - - // register tlb2_valids_3 - reg tlb2_valids_3; - wire tlb2_valids_3$D_IN, tlb2_valids_3$EN; - - // ports of submodule tlb0_entries - wire [168 : 0] tlb0_entries$D_IN, tlb0_entries$D_OUT_1; - wire [1 : 0] tlb0_entries$ADDR_1, - tlb0_entries$ADDR_2, - tlb0_entries$ADDR_3, - tlb0_entries$ADDR_4, - tlb0_entries$ADDR_5, - tlb0_entries$ADDR_IN; - wire tlb0_entries$WE; - - // ports of submodule tlb1_entries - wire [159 : 0] tlb1_entries$D_IN, tlb1_entries$D_OUT_1; - wire [1 : 0] tlb1_entries$ADDR_1, - tlb1_entries$ADDR_2, - tlb1_entries$ADDR_3, - tlb1_entries$ADDR_4, - tlb1_entries$ADDR_5, - tlb1_entries$ADDR_IN; - wire tlb1_entries$WE; - - // ports of submodule tlb2_entries - wire [150 : 0] tlb2_entries$D_IN, tlb2_entries$D_OUT_1; - wire [1 : 0] tlb2_entries$ADDR_1, - tlb2_entries$ADDR_2, - tlb2_entries$ADDR_3, - tlb2_entries$ADDR_4, - tlb2_entries$ADDR_5, - tlb2_entries$ADDR_IN; - wire tlb2_entries$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_initialize, - CAN_FIRE_flush, - CAN_FIRE_insert, - WILL_FIRE_RL_rl_initialize, - WILL_FIRE_flush, - WILL_FIRE_insert; - - // inputs to muxes for submodule ports - wire MUX_tlb0_valids_0$write_1__SEL_1, - MUX_tlb0_valids_1$write_1__SEL_1, - MUX_tlb0_valids_2$write_1__SEL_1, - MUX_tlb0_valids_3$write_1__SEL_1, - MUX_tlb1_valids_0$write_1__SEL_1, - MUX_tlb1_valids_1$write_1__SEL_1, - MUX_tlb1_valids_2$write_1__SEL_1, - MUX_tlb1_valids_3$write_1__SEL_1, - MUX_tlb2_valids_0$write_1__SEL_1, - MUX_tlb2_valids_1$write_1__SEL_1, - MUX_tlb2_valids_2$write_1__SEL_1, - MUX_tlb2_valids_3$write_1__SEL_1; - - // remaining internal signals - reg SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51, - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29, - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8; - wire [129 : 0] IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d92, - IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d93; - wire NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73, - NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43, - NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22, - NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d80, - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61, - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65, - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54, - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60, - tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33, - tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41, - tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12, - tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20; - - // action method flush - assign RDY_flush = 1'd1 ; - assign CAN_FIRE_flush = 1'd1 ; - assign WILL_FIRE_flush = EN_flush ; - - // value method lookup - assign lookup = - { NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 && - NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 && - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61 || - NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d80, - IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d93 } ; - assign RDY_lookup = !rg_flushing ; - - // action method insert - assign RDY_insert = !rg_flushing ; - assign CAN_FIRE_insert = !rg_flushing ; - assign WILL_FIRE_insert = EN_insert ; - - // submodule tlb0_entries - RegFile #(.addr_width(32'd2), - .data_width(32'd169), - .lo(2'h0), - .hi(2'd3)) tlb0_entries(.CLK(CLK), - .ADDR_1(tlb0_entries$ADDR_1), - .ADDR_2(tlb0_entries$ADDR_2), - .ADDR_3(tlb0_entries$ADDR_3), - .ADDR_4(tlb0_entries$ADDR_4), - .ADDR_5(tlb0_entries$ADDR_5), - .ADDR_IN(tlb0_entries$ADDR_IN), - .D_IN(tlb0_entries$D_IN), - .WE(tlb0_entries$WE), - .D_OUT_1(tlb0_entries$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule tlb1_entries - RegFile #(.addr_width(32'd2), - .data_width(32'd160), - .lo(2'h0), - .hi(2'd3)) tlb1_entries(.CLK(CLK), - .ADDR_1(tlb1_entries$ADDR_1), - .ADDR_2(tlb1_entries$ADDR_2), - .ADDR_3(tlb1_entries$ADDR_3), - .ADDR_4(tlb1_entries$ADDR_4), - .ADDR_5(tlb1_entries$ADDR_5), - .ADDR_IN(tlb1_entries$ADDR_IN), - .D_IN(tlb1_entries$D_IN), - .WE(tlb1_entries$WE), - .D_OUT_1(tlb1_entries$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule tlb2_entries - RegFile #(.addr_width(32'd2), - .data_width(32'd151), - .lo(2'h0), - .hi(2'd3)) tlb2_entries(.CLK(CLK), - .ADDR_1(tlb2_entries$ADDR_1), - .ADDR_2(tlb2_entries$ADDR_2), - .ADDR_3(tlb2_entries$ADDR_3), - .ADDR_4(tlb2_entries$ADDR_4), - .ADDR_5(tlb2_entries$ADDR_5), - .ADDR_IN(tlb2_entries$ADDR_IN), - .D_IN(tlb2_entries$D_IN), - .WE(tlb2_entries$WE), - .D_OUT_1(tlb2_entries$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_initialize - assign CAN_FIRE_RL_rl_initialize = rg_flushing ; - assign WILL_FIRE_RL_rl_initialize = rg_flushing ; - - // inputs to muxes for submodule ports - assign MUX_tlb0_valids_0$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd0 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_1$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd1 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_2$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd2 && insert_level == 2'd0 ; - assign MUX_tlb0_valids_3$write_1__SEL_1 = - EN_insert && insert_vpn[1:0] == 2'd3 && insert_level == 2'd0 ; - assign MUX_tlb1_valids_0$write_1__SEL_1 = - EN_insert && insert_vpn[10:9] == 2'd0 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_1$write_1__SEL_1 = - EN_insert && insert_vpn[10:9] == 2'd1 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_2$write_1__SEL_1 = - EN_insert && insert_vpn[10:9] == 2'd2 && insert_level == 2'd1 ; - assign MUX_tlb1_valids_3$write_1__SEL_1 = - EN_insert && insert_vpn[10:9] == 2'd3 && insert_level == 2'd1 ; - assign MUX_tlb2_valids_0$write_1__SEL_1 = - EN_insert && insert_vpn[19:18] == 2'd0 && insert_level != 2'd0 && - insert_level != 2'd1 ; - assign MUX_tlb2_valids_1$write_1__SEL_1 = - EN_insert && insert_vpn[19:18] == 2'd1 && insert_level != 2'd0 && - insert_level != 2'd1 ; - assign MUX_tlb2_valids_2$write_1__SEL_1 = - EN_insert && insert_vpn[19:18] == 2'd2 && insert_level != 2'd0 && - insert_level != 2'd1 ; - assign MUX_tlb2_valids_3$write_1__SEL_1 = - EN_insert && insert_vpn[19:18] == 2'd3 && insert_level != 2'd0 && - insert_level != 2'd1 ; - - // register rg_flushing - assign rg_flushing$D_IN = EN_flush ; - assign rg_flushing$EN = rg_flushing || EN_flush ; - - // register tlb0_valids_0 - assign tlb0_valids_0$D_IN = MUX_tlb0_valids_0$write_1__SEL_1 ; - assign tlb0_valids_0$EN = - EN_insert && insert_vpn[1:0] == 2'd0 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_1 - assign tlb0_valids_1$D_IN = MUX_tlb0_valids_1$write_1__SEL_1 ; - assign tlb0_valids_1$EN = - EN_insert && insert_vpn[1:0] == 2'd1 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_2 - assign tlb0_valids_2$D_IN = MUX_tlb0_valids_2$write_1__SEL_1 ; - assign tlb0_valids_2$EN = - EN_insert && insert_vpn[1:0] == 2'd2 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb0_valids_3 - assign tlb0_valids_3$D_IN = MUX_tlb0_valids_3$write_1__SEL_1 ; - assign tlb0_valids_3$EN = - EN_insert && insert_vpn[1:0] == 2'd3 && insert_level == 2'd0 || - rg_flushing ; - - // register tlb1_valids_0 - assign tlb1_valids_0$D_IN = MUX_tlb1_valids_0$write_1__SEL_1 ; - assign tlb1_valids_0$EN = - EN_insert && insert_vpn[10:9] == 2'd0 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_1 - assign tlb1_valids_1$D_IN = MUX_tlb1_valids_1$write_1__SEL_1 ; - assign tlb1_valids_1$EN = - EN_insert && insert_vpn[10:9] == 2'd1 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_2 - assign tlb1_valids_2$D_IN = MUX_tlb1_valids_2$write_1__SEL_1 ; - assign tlb1_valids_2$EN = - EN_insert && insert_vpn[10:9] == 2'd2 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb1_valids_3 - assign tlb1_valids_3$D_IN = MUX_tlb1_valids_3$write_1__SEL_1 ; - assign tlb1_valids_3$EN = - EN_insert && insert_vpn[10:9] == 2'd3 && insert_level == 2'd1 || - rg_flushing ; - - // register tlb2_valids_0 - assign tlb2_valids_0$D_IN = MUX_tlb2_valids_0$write_1__SEL_1 ; - assign tlb2_valids_0$EN = - EN_insert && insert_vpn[19:18] == 2'd0 && insert_level != 2'd0 && - insert_level != 2'd1 || - rg_flushing ; - - // register tlb2_valids_1 - assign tlb2_valids_1$D_IN = MUX_tlb2_valids_1$write_1__SEL_1 ; - assign tlb2_valids_1$EN = - EN_insert && insert_vpn[19:18] == 2'd1 && insert_level != 2'd0 && - insert_level != 2'd1 || - rg_flushing ; - - // register tlb2_valids_2 - assign tlb2_valids_2$D_IN = MUX_tlb2_valids_2$write_1__SEL_1 ; - assign tlb2_valids_2$EN = - EN_insert && insert_vpn[19:18] == 2'd2 && insert_level != 2'd0 && - insert_level != 2'd1 || - rg_flushing ; - - // register tlb2_valids_3 - assign tlb2_valids_3$D_IN = MUX_tlb2_valids_3$write_1__SEL_1 ; - assign tlb2_valids_3$EN = - EN_insert && insert_vpn[19:18] == 2'd3 && insert_level != 2'd0 && - insert_level != 2'd1 || - rg_flushing ; - - // submodule tlb0_entries - assign tlb0_entries$ADDR_1 = lookup_vpn[1:0] ; - assign tlb0_entries$ADDR_2 = 2'h0 ; - assign tlb0_entries$ADDR_3 = 2'h0 ; - assign tlb0_entries$ADDR_4 = 2'h0 ; - assign tlb0_entries$ADDR_5 = 2'h0 ; - assign tlb0_entries$ADDR_IN = insert_vpn[1:0] ; - assign tlb0_entries$D_IN = - { insert_asid, insert_vpn[26:2], insert_pte, insert_pte_pa } ; - assign tlb0_entries$WE = EN_insert && insert_level == 2'd0 ; - - // submodule tlb1_entries - assign tlb1_entries$ADDR_1 = lookup_vpn[10:9] ; - assign tlb1_entries$ADDR_2 = 2'h0 ; - assign tlb1_entries$ADDR_3 = 2'h0 ; - assign tlb1_entries$ADDR_4 = 2'h0 ; - assign tlb1_entries$ADDR_5 = 2'h0 ; - assign tlb1_entries$ADDR_IN = insert_vpn[10:9] ; - assign tlb1_entries$D_IN = - { insert_asid, insert_vpn[26:11], insert_pte, insert_pte_pa } ; - assign tlb1_entries$WE = EN_insert && insert_level == 2'd1 ; - - // submodule tlb2_entries - assign tlb2_entries$ADDR_1 = lookup_vpn[19:18] ; - assign tlb2_entries$ADDR_2 = 2'h0 ; - assign tlb2_entries$ADDR_3 = 2'h0 ; - assign tlb2_entries$ADDR_4 = 2'h0 ; - assign tlb2_entries$ADDR_5 = 2'h0 ; - assign tlb2_entries$ADDR_IN = insert_vpn[19:18] ; - assign tlb2_entries$D_IN = - { insert_asid, insert_vpn[26:20], insert_pte, insert_pte_pa } ; - assign tlb2_entries$WE = - EN_insert && insert_level != 2'd0 && insert_level != 2'd1 ; - - // remaining internal signals - assign IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d92 = - (NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 && - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65 && - NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73) ? - { tlb1_entries$D_OUT_1[127:64], - 2'd1, - tlb1_entries$D_OUT_1[63:0] } : - { tlb2_entries$D_OUT_1[127:64], - 2'd2, - tlb2_entries$D_OUT_1[63:0] } ; - assign IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d93 = - (NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 && - NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 && - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61) ? - { tlb0_entries$D_OUT_1[127:64], - 2'd0, - tlb0_entries$D_OUT_1[63:0] } : - IF_NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb_ETC___d92 ; - assign NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73 = - !SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 || - !tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54 && - !tlb0_entries$D_OUT_1[69] || - !tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60 ; - assign NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 = - !SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 || - !tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33 && - !tlb1_entries$D_OUT_1[69] || - !tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41 ; - assign NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 = - !SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 || - !tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12 && - !tlb2_entries$D_OUT_1[69] || - !tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20 ; - assign NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d80 = - NOT_SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_v_ETC___d22 && - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65 && - NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73 || - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 && - (tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12 || - tlb2_entries$D_OUT_1[69]) && - tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20 && - NOT_SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tl_ETC___d43 && - NOT_SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tl_ETC___d73 ; - assign SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d61 = - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 && - (tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54 || - tlb0_entries$D_OUT_1[69]) && - tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60 ; - assign SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d65 = - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 && - (tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33 || - tlb1_entries$D_OUT_1[69]) && - tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41 ; - assign tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d54 = - tlb0_entries$D_OUT_1[168:153] == lookup_asid ; - assign tlb0_entries_sub_lookup_vpn_BITS_1_TO_0_0_2_BI_ETC___d60 = - tlb0_entries$D_OUT_1[152:128] == lookup_vpn[26:2] ; - assign tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d33 = - tlb1_entries$D_OUT_1[159:144] == lookup_asid ; - assign tlb1_entries_sub_lookup_vpn_BITS_10_TO_9_8_1_B_ETC___d41 = - tlb1_entries$D_OUT_1[143:128] == lookup_vpn[26:11] ; - assign tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d12 = - tlb2_entries$D_OUT_1[150:135] == lookup_asid ; - assign tlb2_entries_sub_lookup_vpn_BITS_19_TO_18_0_BI_ETC___d20 = - tlb2_entries$D_OUT_1[134:128] == lookup_vpn[26:20] ; - always@(lookup_vpn or - tlb2_valids_0 or tlb2_valids_1 or tlb2_valids_2 or tlb2_valids_3) - begin - case (lookup_vpn[19:18]) - 2'd0: - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 = - tlb2_valids_0; - 2'd1: - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 = - tlb2_valids_1; - 2'd2: - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 = - tlb2_valids_2; - 2'd3: - SEL_ARR_tlb2_valids_0_tlb2_valids_1_tlb2_valid_ETC___d8 = - tlb2_valids_3; - endcase - end - always@(lookup_vpn or - tlb1_valids_0 or tlb1_valids_1 or tlb1_valids_2 or tlb1_valids_3) - begin - case (lookup_vpn[10:9]) - 2'd0: - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 = - tlb1_valids_0; - 2'd1: - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 = - tlb1_valids_1; - 2'd2: - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 = - tlb1_valids_2; - 2'd3: - SEL_ARR_tlb1_valids_0_3_tlb1_valids_1_4_tlb1_v_ETC___d29 = - tlb1_valids_3; - endcase - end - always@(lookup_vpn or - tlb0_valids_0 or tlb0_valids_1 or tlb0_valids_2 or tlb0_valids_3) - begin - case (lookup_vpn[1:0]) - 2'd0: - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 = - tlb0_valids_0; - 2'd1: - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 = - tlb0_valids_1; - 2'd2: - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 = - tlb0_valids_2; - 2'd3: - SEL_ARR_tlb0_valids_0_5_tlb0_valids_1_6_tlb0_v_ETC___d51 = - tlb0_valids_3; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_flushing <= `BSV_ASSIGNMENT_DELAY 1'd1; - end - else - begin - if (rg_flushing$EN) - rg_flushing <= `BSV_ASSIGNMENT_DELAY rg_flushing$D_IN; - end - if (tlb0_valids_0$EN) - tlb0_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_0$D_IN; - if (tlb0_valids_1$EN) - tlb0_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_1$D_IN; - if (tlb0_valids_2$EN) - tlb0_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_2$D_IN; - if (tlb0_valids_3$EN) - tlb0_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_3$D_IN; - if (tlb1_valids_0$EN) - tlb1_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_0$D_IN; - if (tlb1_valids_1$EN) - tlb1_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_1$D_IN; - if (tlb1_valids_2$EN) - tlb1_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_2$D_IN; - if (tlb1_valids_3$EN) - tlb1_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_3$D_IN; - if (tlb2_valids_0$EN) - tlb2_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_0$D_IN; - if (tlb2_valids_1$EN) - tlb2_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_1$D_IN; - if (tlb2_valids_2$EN) - tlb2_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_2$D_IN; - if (tlb2_valids_3$EN) - tlb2_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_flushing = 1'h0; - tlb0_valids_0 = 1'h0; - tlb0_valids_1 = 1'h0; - tlb0_valids_2 = 1'h0; - tlb0_valids_3 = 1'h0; - tlb1_valids_0 = 1'h0; - tlb1_valids_1 = 1'h0; - tlb1_valids_2 = 1'h0; - tlb1_valids_3 = 1'h0; - tlb2_valids_0 = 1'h0; - tlb2_valids_1 = 1'h0; - tlb2_valids_2 = 1'h0; - tlb2_valids_3 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkTLB - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v deleted file mode 100644 index 470d28c6..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v +++ /dev/null @@ -1,328 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// CLK I 1 clock -// RST_N I 1 reset -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTop_HW_Side(CLK, - RST_N); - input CLK; - input RST_N; - - // register rg_banner_printed - reg rg_banner_printed; - wire rg_banner_printed$D_IN, rg_banner_printed$EN; - - // register rg_console_in_poll - reg [11 : 0] rg_console_in_poll; - wire [11 : 0] rg_console_in_poll$D_IN; - wire rg_console_in_poll$EN; - - // ports of submodule mem_model - wire [352 : 0] mem_model$mem_server_request_put; - wire [255 : 0] mem_model$mem_server_response_get; - wire mem_model$EN_mem_server_request_put, - mem_model$EN_mem_server_response_get, - mem_model$RDY_mem_server_request_put, - mem_model$RDY_mem_server_response_get; - - // ports of submodule soc_top - wire [352 : 0] soc_top$to_raw_mem_request_get; - wire [255 : 0] soc_top$to_raw_mem_response_put; - wire [63 : 0] soc_top$set_verbosity_logdelay, - soc_top$set_watch_tohost_tohost_addr; - wire [7 : 0] soc_top$get_to_console_get, - soc_top$put_from_console_put, - soc_top$status; - wire [3 : 0] soc_top$set_verbosity_verbosity; - wire soc_top$EN_get_to_console_get, - soc_top$EN_put_from_console_put, - soc_top$EN_set_verbosity, - soc_top$EN_set_watch_tohost, - soc_top$EN_to_raw_mem_request_get, - soc_top$EN_to_raw_mem_response_put, - soc_top$RDY_get_to_console_get, - soc_top$RDY_put_from_console_put, - soc_top$RDY_to_raw_mem_request_get, - soc_top$RDY_to_raw_mem_response_put, - soc_top$set_watch_tohost_watch_tohost; - - // rule scheduling signals - wire CAN_FIRE_RL_memCnx_ClientServerRequest, - CAN_FIRE_RL_memCnx_ClientServerResponse, - CAN_FIRE_RL_rl_relay_console_in, - CAN_FIRE_RL_rl_relay_console_out, - CAN_FIRE_RL_rl_step0, - CAN_FIRE_RL_rl_terminate, - WILL_FIRE_RL_memCnx_ClientServerRequest, - WILL_FIRE_RL_memCnx_ClientServerResponse, - WILL_FIRE_RL_rl_relay_console_in, - WILL_FIRE_RL_rl_relay_console_out, - WILL_FIRE_RL_rl_step0, - WILL_FIRE_RL_rl_terminate; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h702; - reg [31 : 0] v__h743; - reg TASK_testplusargs___d12; - reg TASK_testplusargs___d11; - reg TASK_testplusargs___d15; - reg [63 : 0] tohost_addr__h571; - reg [31 : 0] v__h633; - reg [7 : 0] v__h941; - reg [31 : 0] v__h627; - reg [31 : 0] v__h737; - reg [31 : 0] v__h696; - // synopsys translate_on - - // submodule mem_model - mkMem_Model mem_model(.CLK(CLK), - .RST_N(RST_N), - .mem_server_request_put(mem_model$mem_server_request_put), - .EN_mem_server_request_put(mem_model$EN_mem_server_request_put), - .EN_mem_server_response_get(mem_model$EN_mem_server_response_get), - .RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put), - .mem_server_response_get(mem_model$mem_server_response_get), - .RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get)); - - // submodule soc_top - mkSoC_Top soc_top(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(soc_top$put_from_console_put), - .set_verbosity_logdelay(soc_top$set_verbosity_logdelay), - .set_verbosity_verbosity(soc_top$set_verbosity_verbosity), - .set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost), - .to_raw_mem_response_put(soc_top$to_raw_mem_response_put), - .EN_set_verbosity(soc_top$EN_set_verbosity), - .EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put), - .EN_get_to_console_get(soc_top$EN_get_to_console_get), - .EN_put_from_console_put(soc_top$EN_put_from_console_put), - .EN_set_watch_tohost(soc_top$EN_set_watch_tohost), - .RDY_set_verbosity(), - .to_raw_mem_request_get(soc_top$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put), - .get_to_console_get(soc_top$get_to_console_get), - .RDY_get_to_console_get(soc_top$RDY_get_to_console_get), - .RDY_put_from_console_put(soc_top$RDY_put_from_console_put), - .status(soc_top$status), - .RDY_set_watch_tohost()); - - // rule RL_rl_terminate - assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ; - assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ; - - // rule RL_rl_step0 - assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ; - assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ; - - // rule RL_rl_relay_console_out - assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - - // rule RL_rl_relay_console_in - assign CAN_FIRE_RL_rl_relay_console_in = - rg_console_in_poll != 12'd0 || soc_top$RDY_put_from_console_put ; - assign WILL_FIRE_RL_rl_relay_console_in = CAN_FIRE_RL_rl_relay_console_in ; - - // rule RL_memCnx_ClientServerRequest - assign CAN_FIRE_RL_memCnx_ClientServerRequest = - soc_top$RDY_to_raw_mem_request_get && - mem_model$RDY_mem_server_request_put ; - assign WILL_FIRE_RL_memCnx_ClientServerRequest = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - - // rule RL_memCnx_ClientServerResponse - assign CAN_FIRE_RL_memCnx_ClientServerResponse = - soc_top$RDY_to_raw_mem_response_put && - mem_model$RDY_mem_server_response_get ; - assign WILL_FIRE_RL_memCnx_ClientServerResponse = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // register rg_banner_printed - assign rg_banner_printed$D_IN = 1'd1 ; - assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ; - - // register rg_console_in_poll - assign rg_console_in_poll$D_IN = rg_console_in_poll + 12'd1 ; - assign rg_console_in_poll$EN = CAN_FIRE_RL_rl_relay_console_in ; - - // submodule mem_model - assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ; - assign mem_model$EN_mem_server_request_put = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign mem_model$EN_mem_server_response_get = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // submodule soc_top - assign soc_top$put_from_console_put = v__h941 ; - assign soc_top$set_verbosity_logdelay = 64'd0 ; - assign soc_top$set_verbosity_verbosity = - TASK_testplusargs___d11 ? - 4'd2 : - (TASK_testplusargs___d12 ? 4'd1 : 4'd0) ; - assign soc_top$set_watch_tohost_tohost_addr = tohost_addr__h571 ; - assign soc_top$set_watch_tohost_watch_tohost = TASK_testplusargs___d15 ; - assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ; - assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ; - assign soc_top$EN_to_raw_mem_request_get = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign soc_top$EN_to_raw_mem_response_put = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ; - assign soc_top$EN_put_from_console_put = - WILL_FIRE_RL_rl_relay_console_in && - rg_console_in_poll == 12'd0 && - v__h941 != 8'd0 ; - assign soc_top$EN_set_watch_tohost = CAN_FIRE_RL_rl_step0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_banner_printed$EN) - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN; - if (rg_console_in_poll$EN) - rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY rg_console_in_poll$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_banner_printed = 1'h0; - rg_console_in_poll = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h702 = $stime; - #0; - end - v__h696 = v__h702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $display("%0d: %m:.rl_terminate: soc_top status is 0x%0h (= 0d%0d)", - v__h696, - soc_top$status, - soc_top$status); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h743 = $stime; - #0; - end - v__h737 = v__h743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $imported_c_end_timing({ 32'd0, v__h737 }); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Bluespec RISC-V standalone system simulation v1.2"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d12 = $test$plusargs("v1"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d11 = $test$plusargs("v2"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d15 = $test$plusargs("tohost"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - tohost_addr__h571 = $imported_c_get_symbol_val("tohost"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("INFO: watch_tohost = %0d, tohost_addr = 0x%0h", - TASK_testplusargs___d15, - tohost_addr__h571); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - v__h633 = $stime; - #0; - end - v__h627 = v__h633 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) $imported_c_start_timing({ 32'd0, v__h627 }); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) - $write("%c", soc_top$get_to_console_get); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_relay_console_in && rg_console_in_poll == 12'd0) - begin - v__h941 = $imported_c_trygetchar(8'hAA); - #0; - end - end - // synopsys translate_on -endmodule // mkTop_HW_Side - diff --git a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkUART.v b/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkUART.v deleted file mode 100644 index 033775ea..00000000 --- a/builds/RV64ACDFIMSU_Piccolo_verilator/Verilog_RTL/mkUART.v +++ /dev/null @@ -1,2925 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// intr O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// put_from_console_put I 8 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_put_from_console_put I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkUART(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - intr); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method intr - output intr; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [7 : 0] get_to_console_get; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - intr, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register cfg_verbosity - reg [7 : 0] cfg_verbosity; - wire [7 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_dll - reg [7 : 0] rg_dll; - wire [7 : 0] rg_dll$D_IN; - wire rg_dll$EN; - - // register rg_dlm - reg [7 : 0] rg_dlm; - wire [7 : 0] rg_dlm$D_IN; - wire rg_dlm$EN; - - // register rg_fcr - reg [7 : 0] rg_fcr; - wire [7 : 0] rg_fcr$D_IN; - wire rg_fcr$EN; - - // register rg_ier - reg [7 : 0] rg_ier; - wire [7 : 0] rg_ier$D_IN; - wire rg_ier$EN; - - // register rg_lcr - reg [7 : 0] rg_lcr; - wire [7 : 0] rg_lcr$D_IN; - wire rg_lcr$EN; - - // register rg_lsr - reg [7 : 0] rg_lsr; - reg [7 : 0] rg_lsr$D_IN; - wire rg_lsr$EN; - - // register rg_mcr - reg [7 : 0] rg_mcr; - wire [7 : 0] rg_mcr$D_IN; - wire rg_mcr$EN; - - // register rg_msr - reg [7 : 0] rg_msr; - wire [7 : 0] rg_msr$D_IN; - wire rg_msr$EN; - - // register rg_rbr - reg [7 : 0] rg_rbr; - wire [7 : 0] rg_rbr$D_IN; - wire rg_rbr$EN; - - // register rg_scr - reg [7 : 0] rg_scr; - wire [7 : 0] rg_scr$D_IN; - wire rg_scr$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_thr - reg [7 : 0] rg_thr; - wire [7 : 0] rg_thr$D_IN; - wire rg_thr$EN; - - // ports of submodule f_from_console - wire [7 : 0] f_from_console$D_IN, f_from_console$D_OUT; - wire f_from_console$CLR, - f_from_console$DEQ, - f_from_console$EMPTY_N, - f_from_console$ENQ, - f_from_console$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_to_console - wire [7 : 0] f_to_console$D_IN, f_to_console$D_OUT; - wire f_to_console$CLR, - f_to_console$DEQ, - f_to_console$EMPTY_N, - f_to_console$ENQ, - f_to_console$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_receive, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_receive, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_rg_lsr$write_1__VAL_3; - wire MUX_rg_lsr$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2519; - reg [31 : 0] v__h2187; - reg [31 : 0] v__h2025; - reg [31 : 0] v__h2898; - reg [31 : 0] v__h3244; - reg [31 : 0] v__h4006; - reg [31 : 0] v__h3449; - reg [31 : 0] v__h4306; - reg [31 : 0] v__h4749; - reg [31 : 0] v__h4859; - reg [31 : 0] v__h1811; - reg [31 : 0] v__h1805; - reg [31 : 0] v__h2019; - reg [31 : 0] v__h2181; - reg [31 : 0] v__h2513; - reg [31 : 0] v__h2892; - reg [31 : 0] v__h3238; - reg [31 : 0] v__h3443; - reg [31 : 0] v__h4000; - reg [31 : 0] v__h4300; - reg [31 : 0] v__h4743; - reg [31 : 0] v__h4853; - // synopsys translate_on - - // remaining internal signals - reg [7 : 0] y_avValue_snd__h2683; - wire [63 : 0] rdata__h2759, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133; - wire [7 : 0] fn_iir__h1356, - new_lsr__h4516, - x__h2797, - y_avValue_snd__h2696, - y_avValue_snd__h2709, - y_avValue_snd__h2724, - y_avValue_snd__h2738; - wire [1 : 0] rdr_rresp__h2792, - v__h3147, - v__h3395, - v__h3575, - y_avValue_fst__h2737, - y_avValue_fst__h2751; - wire NOT_cfg_verbosity_read_ULE_1_24___d125, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188, - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method get_to_console_get - assign get_to_console_get = f_to_console$D_OUT ; - assign RDY_get_to_console_get = f_to_console$EMPTY_N ; - assign CAN_FIRE_get_to_console_get = f_to_console$EMPTY_N ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = f_from_console$FULL_N ; - assign CAN_FIRE_put_from_console_put = f_from_console$FULL_N ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method intr - assign intr = !fn_iir__h1356[0] ; - - // submodule f_from_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_from_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_from_console$D_IN), - .ENQ(f_from_console$ENQ), - .DEQ(f_from_console$DEQ), - .CLR(f_from_console$CLR), - .D_OUT(f_from_console$D_OUT), - .FULL_N(f_from_console$FULL_N), - .EMPTY_N(f_from_console$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_to_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_to_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_to_console$D_IN), - .ENQ(f_to_console$ENQ), - .DEQ(f_to_console$DEQ), - .CLR(f_to_console$CLR), - .D_OUT(f_to_console$D_OUT), - .FULL_N(f_to_console$FULL_N), - .EMPTY_N(f_to_console$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 && - rg_state ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_receive - assign CAN_FIRE_RL_rl_receive = f_from_console$EMPTY_N && !rg_lsr[0] ; - assign WILL_FIRE_RL_rl_receive = - CAN_FIRE_RL_rl_receive && !WILL_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_rg_lsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 ; - assign MUX_rg_lsr$write_1__VAL_3 = { rg_lsr[7:1], 1'd0 } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 8'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_dll - assign rg_dll$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dll$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 || - WILL_FIRE_RL_rl_reset ; - - // register rg_dlm - assign rg_dlm$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dlm$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 || - WILL_FIRE_RL_rl_reset ; - - // register rg_fcr - assign rg_fcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_fcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h2 || - WILL_FIRE_RL_rl_reset ; - - // register rg_ier - assign rg_ier$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_ier$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lcr - assign rg_lcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_lcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h3 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lsr - always@(WILL_FIRE_RL_rl_reset or - WILL_FIRE_RL_rl_receive or - new_lsr__h4516 or - MUX_rg_lsr$write_1__SEL_3 or MUX_rg_lsr$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset: rg_lsr$D_IN = 8'd96; - WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h4516; - MUX_rg_lsr$write_1__SEL_3: rg_lsr$D_IN = MUX_rg_lsr$write_1__VAL_3; - default: rg_lsr$D_IN = 8'b10101010 /* unspecified value */ ; - endcase - assign rg_lsr$EN = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 || - WILL_FIRE_RL_rl_receive || - WILL_FIRE_RL_rl_reset ; - - // register rg_mcr - assign rg_mcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_mcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h4 || - WILL_FIRE_RL_rl_reset ; - - // register rg_msr - assign rg_msr$D_IN = 8'd0 ; - assign rg_msr$EN = CAN_FIRE_RL_rl_reset ; - - // register rg_rbr - assign rg_rbr$D_IN = f_from_console$D_OUT ; - assign rg_rbr$EN = WILL_FIRE_RL_rl_receive ; - - // register rg_scr - assign rg_scr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_scr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h7 || - WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = 1'd1 ; - assign rg_state$EN = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // register rg_thr - assign rg_thr$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_thr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - - // submodule f_from_console - assign f_from_console$D_IN = put_from_console_put ; - assign f_from_console$ENQ = EN_put_from_console_put ; - assign f_from_console$DEQ = WILL_FIRE_RL_rl_receive ; - assign f_from_console$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_to_console - assign f_to_console$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign f_to_console$ENQ = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - assign f_to_console$DEQ = EN_get_to_console_get ; - assign f_to_console$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h2759, - rdr_rresp__h2792, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3147 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_24___d125 = cfg_verbosity > 8'd1 ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - slave_xactor_f_wr_data$D_OUT[0] ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - !slave_xactor_f_wr_data$D_OUT[0] ; - assign fn_iir__h1356 = - (rg_ier[0] && rg_lsr[0]) ? 8'h04 : (rg_ier[1] ? 8'h02 : 8'd0) ; - assign new_lsr__h4516 = { rg_lsr[7:1], 1'd1 } ; - assign rdata__h2759 = { 56'd0, x__h2797 } ; - assign rdr_rresp__h2792 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0) ? - y_avValue_fst__h2751 : - 2'b10 ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 = - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - rg_lcr[7] ; - assign slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 = - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1] || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7] || - f_to_console$FULL_N) ; - assign v__h3147 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) ? - 2'b10 : - v__h3395 ; - assign v__h3395 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0) ? - v__h3575 : - 2'b11 ; - assign v__h3575 = y_avValue_fst__h2737 ; - assign x__h2797 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0 || - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) ? - 8'd0 : - y_avValue_snd__h2738 ; - assign y_avValue_fst__h2737 = 2'b0 ; - assign y_avValue_fst__h2751 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0) ? - y_avValue_fst__h2737 : - 2'b11 ; - assign y_avValue_snd__h2696 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - rg_lcr[7]) ? - rg_dlm : - y_avValue_snd__h2683 ; - assign y_avValue_snd__h2709 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - !rg_lcr[7]) ? - rg_ier : - y_avValue_snd__h2696 ; - assign y_avValue_snd__h2724 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - rg_lcr[7]) ? - rg_dll : - y_avValue_snd__h2709 ; - assign y_avValue_snd__h2738 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7]) ? - rg_rbr : - y_avValue_snd__h2724 ; - always@(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 or - fn_iir__h1356 or rg_lcr or rg_mcr or rg_lsr or rg_msr or rg_scr) - begin - case (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3]) - 3'h2: y_avValue_snd__h2683 = fn_iir__h1356; - 3'h3: y_avValue_snd__h2683 = rg_lcr; - 3'h4: y_avValue_snd__h2683 = rg_mcr; - 3'h5: y_avValue_snd__h2683 = rg_lsr; - 3'h6: y_avValue_snd__h2683 = rg_msr; - 3'h7: y_avValue_snd__h2683 = rg_scr; - default: y_avValue_snd__h2683 = 8'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dll <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dlm <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_fcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_ier <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lsr <= `BSV_ASSIGNMENT_DELAY 8'd96; - rg_mcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_msr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_scr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_dll$EN) rg_dll <= `BSV_ASSIGNMENT_DELAY rg_dll$D_IN; - if (rg_dlm$EN) rg_dlm <= `BSV_ASSIGNMENT_DELAY rg_dlm$D_IN; - if (rg_fcr$EN) rg_fcr <= `BSV_ASSIGNMENT_DELAY rg_fcr$D_IN; - if (rg_ier$EN) rg_ier <= `BSV_ASSIGNMENT_DELAY rg_ier$D_IN; - if (rg_lcr$EN) rg_lcr <= `BSV_ASSIGNMENT_DELAY rg_lcr$D_IN; - if (rg_lsr$EN) rg_lsr <= `BSV_ASSIGNMENT_DELAY rg_lsr$D_IN; - if (rg_mcr$EN) rg_mcr <= `BSV_ASSIGNMENT_DELAY rg_mcr$D_IN; - if (rg_msr$EN) rg_msr <= `BSV_ASSIGNMENT_DELAY rg_msr$D_IN; - if (rg_scr$EN) rg_scr <= `BSV_ASSIGNMENT_DELAY rg_scr$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_rbr$EN) rg_rbr <= `BSV_ASSIGNMENT_DELAY rg_rbr$D_IN; - if (rg_thr$EN) rg_thr <= `BSV_ASSIGNMENT_DELAY rg_thr$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 8'hAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_dll = 8'hAA; - rg_dlm = 8'hAA; - rg_fcr = 8'hAA; - rg_ier = 8'hAA; - rg_lcr = 8'hAA; - rg_lsr = 8'hAA; - rg_mcr = 8'hAA; - rg_msr = 8'hAA; - rg_rbr = 8'hAA; - rg_scr = 8'hAA; - rg_state = 1'h0; - rg_thr = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - begin - v__h2519 = $stime; - #0; - end - v__h2513 = v__h2519 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2513); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - begin - v__h2187 = $stime; - #0; - end - v__h2181 = v__h2187 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2181); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - begin - v__h2025 = $stime; - #0; - end - v__h2019 = v__h2025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: misaligned addr", - v__h2019); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h2898 = $stime; - #0; - end - v__h2892 = v__h2898 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_rd_req", v__h2892); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdata__h2759); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdr_rresp__h2792); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - begin - v__h3244 = $stime; - #0; - end - v__h3238 = v__h3244 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $display("%0d: ERROR: UART.rl_process_wr_req: misaligned addr", - v__h3238); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - begin - v__h4006 = $stime; - #0; - end - v__h4000 = v__h4006 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h4000); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - begin - v__h3449 = $stime; - #0; - end - v__h3443 = v__h3449 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h3443); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h4306 = $stime; - #0; - end - v__h4300 = v__h4306 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_wr_req", v__h4300); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", v__h3147); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h4749 = $stime; - #0; - end - v__h4743 = v__h4749 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_base 0x%0h is not 8-Byte-aligned", - v__h4743, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h4859 = $stime; - #0; - end - v__h4853 = v__h4859 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_lim 0x%0h is not 8-Byte-aligned", - v__h4853, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_receive && NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("UART_Model.rl_receive: received char 0x%0h; new_lsr = 0x%0h", - f_from_console$D_OUT, - new_lsr__h4516); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - begin - v__h1811 = $stime; - #0; - end - v__h1805 = v__h1811 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - $display("%0d: UART.rl_reset", v__h1805); - end - // synopsys translate_on -endmodule // mkUART - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v deleted file mode 100644 index 1cb3bfa4..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v +++ /dev/null @@ -1,1415 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// from_master_awready O 1 reg -// from_master_wready O 1 reg -// from_master_bvalid O 1 reg -// from_master_bid O 4 reg -// from_master_bresp O 2 reg -// from_master_arready O 1 reg -// from_master_rvalid O 1 reg -// from_master_rid O 4 reg -// from_master_rdata O 64 reg -// from_master_rresp O 2 reg -// from_master_rlast O 1 reg -// to_slave_awvalid O 1 reg -// to_slave_awid O 4 reg -// to_slave_awaddr O 64 reg -// to_slave_awlen O 8 reg -// to_slave_awsize O 3 reg -// to_slave_awburst O 2 reg -// to_slave_awlock O 1 reg -// to_slave_awcache O 4 reg -// to_slave_awprot O 3 reg -// to_slave_awqos O 4 reg -// to_slave_awregion O 4 reg -// to_slave_wvalid O 1 reg -// to_slave_wid O 4 reg -// to_slave_wdata O 64 reg -// to_slave_wstrb O 8 reg -// to_slave_wlast O 1 reg -// to_slave_bready O 1 reg -// to_slave_arvalid O 1 reg -// to_slave_arid O 4 reg -// to_slave_araddr O 64 reg -// to_slave_arlen O 8 reg -// to_slave_arsize O 3 reg -// to_slave_arburst O 2 reg -// to_slave_arlock O 1 reg -// to_slave_arcache O 4 reg -// to_slave_arprot O 3 reg -// to_slave_arqos O 4 reg -// to_slave_arregion O 4 reg -// to_slave_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// from_master_awvalid I 1 -// from_master_awid I 4 reg -// from_master_awaddr I 64 reg -// from_master_awlen I 8 reg -// from_master_awsize I 3 reg -// from_master_awburst I 2 reg -// from_master_awlock I 1 reg -// from_master_awcache I 4 reg -// from_master_awprot I 3 reg -// from_master_awqos I 4 reg -// from_master_awregion I 4 reg -// from_master_wvalid I 1 -// from_master_wid I 4 reg -// from_master_wdata I 64 reg -// from_master_wstrb I 8 reg -// from_master_wlast I 1 reg -// from_master_bready I 1 -// from_master_arvalid I 1 -// from_master_arid I 4 reg -// from_master_araddr I 64 reg -// from_master_arlen I 8 reg -// from_master_arsize I 3 reg -// from_master_arburst I 2 reg -// from_master_arlock I 1 reg -// from_master_arcache I 4 reg -// from_master_arprot I 3 reg -// from_master_arqos I 4 reg -// from_master_arregion I 4 reg -// from_master_rready I 1 -// to_slave_awready I 1 -// to_slave_wready I 1 -// to_slave_bvalid I 1 -// to_slave_bid I 4 reg -// to_slave_bresp I 2 reg -// to_slave_arready I 1 -// to_slave_rvalid I 1 -// to_slave_rid I 4 reg -// to_slave_rdata I 64 reg -// to_slave_rresp I 2 reg -// to_slave_rlast I 1 reg -// EN_reset I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkAXI4_Deburster_A(CLK, - RST_N, - - EN_reset, - RDY_reset, - - from_master_awvalid, - from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion, - - from_master_awready, - - from_master_wvalid, - from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast, - - from_master_wready, - - from_master_bvalid, - - from_master_bid, - - from_master_bresp, - - from_master_bready, - - from_master_arvalid, - from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion, - - from_master_arready, - - from_master_rvalid, - - from_master_rid, - - from_master_rdata, - - from_master_rresp, - - from_master_rlast, - - from_master_rready, - - to_slave_awvalid, - - to_slave_awid, - - to_slave_awaddr, - - to_slave_awlen, - - to_slave_awsize, - - to_slave_awburst, - - to_slave_awlock, - - to_slave_awcache, - - to_slave_awprot, - - to_slave_awqos, - - to_slave_awregion, - - to_slave_awready, - - to_slave_wvalid, - - to_slave_wid, - - to_slave_wdata, - - to_slave_wstrb, - - to_slave_wlast, - - to_slave_wready, - - to_slave_bvalid, - to_slave_bid, - to_slave_bresp, - - to_slave_bready, - - to_slave_arvalid, - - to_slave_arid, - - to_slave_araddr, - - to_slave_arlen, - - to_slave_arsize, - - to_slave_arburst, - - to_slave_arlock, - - to_slave_arcache, - - to_slave_arprot, - - to_slave_arqos, - - to_slave_arregion, - - to_slave_arready, - - to_slave_rvalid, - to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast, - - to_slave_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method from_master_m_awvalid - input from_master_awvalid; - input [3 : 0] from_master_awid; - input [63 : 0] from_master_awaddr; - input [7 : 0] from_master_awlen; - input [2 : 0] from_master_awsize; - input [1 : 0] from_master_awburst; - input from_master_awlock; - input [3 : 0] from_master_awcache; - input [2 : 0] from_master_awprot; - input [3 : 0] from_master_awqos; - input [3 : 0] from_master_awregion; - - // value method from_master_m_awready - output from_master_awready; - - // action method from_master_m_wvalid - input from_master_wvalid; - input [3 : 0] from_master_wid; - input [63 : 0] from_master_wdata; - input [7 : 0] from_master_wstrb; - input from_master_wlast; - - // value method from_master_m_wready - output from_master_wready; - - // value method from_master_m_bvalid - output from_master_bvalid; - - // value method from_master_m_bid - output [3 : 0] from_master_bid; - - // value method from_master_m_bresp - output [1 : 0] from_master_bresp; - - // value method from_master_m_buser - - // action method from_master_m_bready - input from_master_bready; - - // action method from_master_m_arvalid - input from_master_arvalid; - input [3 : 0] from_master_arid; - input [63 : 0] from_master_araddr; - input [7 : 0] from_master_arlen; - input [2 : 0] from_master_arsize; - input [1 : 0] from_master_arburst; - input from_master_arlock; - input [3 : 0] from_master_arcache; - input [2 : 0] from_master_arprot; - input [3 : 0] from_master_arqos; - input [3 : 0] from_master_arregion; - - // value method from_master_m_arready - output from_master_arready; - - // value method from_master_m_rvalid - output from_master_rvalid; - - // value method from_master_m_rid - output [3 : 0] from_master_rid; - - // value method from_master_m_rdata - output [63 : 0] from_master_rdata; - - // value method from_master_m_rresp - output [1 : 0] from_master_rresp; - - // value method from_master_m_rlast - output from_master_rlast; - - // value method from_master_m_ruser - - // action method from_master_m_rready - input from_master_rready; - - // value method to_slave_m_awvalid - output to_slave_awvalid; - - // value method to_slave_m_awid - output [3 : 0] to_slave_awid; - - // value method to_slave_m_awaddr - output [63 : 0] to_slave_awaddr; - - // value method to_slave_m_awlen - output [7 : 0] to_slave_awlen; - - // value method to_slave_m_awsize - output [2 : 0] to_slave_awsize; - - // value method to_slave_m_awburst - output [1 : 0] to_slave_awburst; - - // value method to_slave_m_awlock - output to_slave_awlock; - - // value method to_slave_m_awcache - output [3 : 0] to_slave_awcache; - - // value method to_slave_m_awprot - output [2 : 0] to_slave_awprot; - - // value method to_slave_m_awqos - output [3 : 0] to_slave_awqos; - - // value method to_slave_m_awregion - output [3 : 0] to_slave_awregion; - - // value method to_slave_m_awuser - - // action method to_slave_m_awready - input to_slave_awready; - - // value method to_slave_m_wvalid - output to_slave_wvalid; - - // value method to_slave_m_wid - output [3 : 0] to_slave_wid; - - // value method to_slave_m_wdata - output [63 : 0] to_slave_wdata; - - // value method to_slave_m_wstrb - output [7 : 0] to_slave_wstrb; - - // value method to_slave_m_wlast - output to_slave_wlast; - - // value method to_slave_m_wuser - - // action method to_slave_m_wready - input to_slave_wready; - - // action method to_slave_m_bvalid - input to_slave_bvalid; - input [3 : 0] to_slave_bid; - input [1 : 0] to_slave_bresp; - - // value method to_slave_m_bready - output to_slave_bready; - - // value method to_slave_m_arvalid - output to_slave_arvalid; - - // value method to_slave_m_arid - output [3 : 0] to_slave_arid; - - // value method to_slave_m_araddr - output [63 : 0] to_slave_araddr; - - // value method to_slave_m_arlen - output [7 : 0] to_slave_arlen; - - // value method to_slave_m_arsize - output [2 : 0] to_slave_arsize; - - // value method to_slave_m_arburst - output [1 : 0] to_slave_arburst; - - // value method to_slave_m_arlock - output to_slave_arlock; - - // value method to_slave_m_arcache - output [3 : 0] to_slave_arcache; - - // value method to_slave_m_arprot - output [2 : 0] to_slave_arprot; - - // value method to_slave_m_arqos - output [3 : 0] to_slave_arqos; - - // value method to_slave_m_arregion - output [3 : 0] to_slave_arregion; - - // value method to_slave_m_aruser - - // action method to_slave_m_arready - input to_slave_arready; - - // action method to_slave_m_rvalid - input to_slave_rvalid; - input [3 : 0] to_slave_rid; - input [63 : 0] to_slave_rdata; - input [1 : 0] to_slave_rresp; - input to_slave_rlast; - - // value method to_slave_m_rready - output to_slave_rready; - - // signals for module outputs - wire [63 : 0] from_master_rdata, - to_slave_araddr, - to_slave_awaddr, - to_slave_wdata; - wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb; - wire [3 : 0] from_master_bid, - from_master_rid, - to_slave_arcache, - to_slave_arid, - to_slave_arqos, - to_slave_arregion, - to_slave_awcache, - to_slave_awid, - to_slave_awqos, - to_slave_awregion, - to_slave_wid; - wire [2 : 0] to_slave_arprot, - to_slave_arsize, - to_slave_awprot, - to_slave_awsize; - wire [1 : 0] from_master_bresp, - from_master_rresp, - to_slave_arburst, - to_slave_awburst; - wire RDY_reset, - from_master_arready, - from_master_awready, - from_master_bvalid, - from_master_rlast, - from_master_rvalid, - from_master_wready, - to_slave_arlock, - to_slave_arvalid, - to_slave_awlock, - to_slave_awvalid, - to_slave_bready, - to_slave_rready, - to_slave_wlast, - to_slave_wvalid; - - // register m_rg_ar_beat_count - reg [7 : 0] m_rg_ar_beat_count; - wire [7 : 0] m_rg_ar_beat_count$D_IN; - wire m_rg_ar_beat_count$EN; - - // register m_rg_b_beat_count - reg [7 : 0] m_rg_b_beat_count; - wire [7 : 0] m_rg_b_beat_count$D_IN; - wire m_rg_b_beat_count$EN; - - // register m_rg_b_resp - reg [1 : 0] m_rg_b_resp; - wire [1 : 0] m_rg_b_resp$D_IN; - wire m_rg_b_resp$EN; - - // register m_rg_r_beat_count - reg [7 : 0] m_rg_r_beat_count; - wire [7 : 0] m_rg_r_beat_count$D_IN; - wire m_rg_r_beat_count$EN; - - // register m_rg_reset - reg m_rg_reset; - wire m_rg_reset$D_IN, m_rg_reset$EN; - - // register m_rg_w_beat_count - reg [7 : 0] m_rg_w_beat_count; - wire [7 : 0] m_rg_w_beat_count$D_IN; - wire m_rg_w_beat_count$EN; - - // ports of submodule m_f_r_arlen - wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT; - wire m_f_r_arlen$CLR, - m_f_r_arlen$DEQ, - m_f_r_arlen$EMPTY_N, - m_f_r_arlen$ENQ, - m_f_r_arlen$FULL_N; - - // ports of submodule m_f_w_awlen - wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT; - wire m_f_w_awlen$CLR, - m_f_w_awlen$DEQ, - m_f_w_awlen$EMPTY_N, - m_f_w_awlen$ENQ, - m_f_w_awlen$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_addr - wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN, - m_xactor_from_master_f_rd_addr$D_OUT; - wire m_xactor_from_master_f_rd_addr$CLR, - m_xactor_from_master_f_rd_addr$DEQ, - m_xactor_from_master_f_rd_addr$EMPTY_N, - m_xactor_from_master_f_rd_addr$ENQ, - m_xactor_from_master_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_data - wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN, - m_xactor_from_master_f_rd_data$D_OUT; - wire m_xactor_from_master_f_rd_data$CLR, - m_xactor_from_master_f_rd_data$DEQ, - m_xactor_from_master_f_rd_data$EMPTY_N, - m_xactor_from_master_f_rd_data$ENQ, - m_xactor_from_master_f_rd_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_addr - wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN, - m_xactor_from_master_f_wr_addr$D_OUT; - wire m_xactor_from_master_f_wr_addr$CLR, - m_xactor_from_master_f_wr_addr$DEQ, - m_xactor_from_master_f_wr_addr$EMPTY_N, - m_xactor_from_master_f_wr_addr$ENQ, - m_xactor_from_master_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_data - wire [76 : 0] m_xactor_from_master_f_wr_data$D_IN, - m_xactor_from_master_f_wr_data$D_OUT; - wire m_xactor_from_master_f_wr_data$CLR, - m_xactor_from_master_f_wr_data$DEQ, - m_xactor_from_master_f_wr_data$EMPTY_N, - m_xactor_from_master_f_wr_data$ENQ, - m_xactor_from_master_f_wr_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_resp - wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN, - m_xactor_from_master_f_wr_resp$D_OUT; - wire m_xactor_from_master_f_wr_resp$CLR, - m_xactor_from_master_f_wr_resp$DEQ, - m_xactor_from_master_f_wr_resp$EMPTY_N, - m_xactor_from_master_f_wr_resp$ENQ, - m_xactor_from_master_f_wr_resp$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_addr - wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN, - m_xactor_to_slave_f_rd_addr$D_OUT; - wire m_xactor_to_slave_f_rd_addr$CLR, - m_xactor_to_slave_f_rd_addr$DEQ, - m_xactor_to_slave_f_rd_addr$EMPTY_N, - m_xactor_to_slave_f_rd_addr$ENQ, - m_xactor_to_slave_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_data - wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN, - m_xactor_to_slave_f_rd_data$D_OUT; - wire m_xactor_to_slave_f_rd_data$CLR, - m_xactor_to_slave_f_rd_data$DEQ, - m_xactor_to_slave_f_rd_data$EMPTY_N, - m_xactor_to_slave_f_rd_data$ENQ, - m_xactor_to_slave_f_rd_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_addr - wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN, - m_xactor_to_slave_f_wr_addr$D_OUT; - wire m_xactor_to_slave_f_wr_addr$CLR, - m_xactor_to_slave_f_wr_addr$DEQ, - m_xactor_to_slave_f_wr_addr$EMPTY_N, - m_xactor_to_slave_f_wr_addr$ENQ, - m_xactor_to_slave_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_data - wire [76 : 0] m_xactor_to_slave_f_wr_data$D_IN, - m_xactor_to_slave_f_wr_data$D_OUT; - wire m_xactor_to_slave_f_wr_data$CLR, - m_xactor_to_slave_f_wr_data$DEQ, - m_xactor_to_slave_f_wr_data$EMPTY_N, - m_xactor_to_slave_f_wr_data$ENQ, - m_xactor_to_slave_f_wr_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_resp - wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN, - m_xactor_to_slave_f_wr_resp$D_OUT; - wire m_xactor_to_slave_f_wr_resp$CLR, - m_xactor_to_slave_f_wr_resp$DEQ, - m_xactor_to_slave_f_wr_resp$EMPTY_N, - m_xactor_to_slave_f_wr_resp$ENQ, - m_xactor_to_slave_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave, - CAN_FIRE_from_master_m_arvalid, - CAN_FIRE_from_master_m_awvalid, - CAN_FIRE_from_master_m_bready, - CAN_FIRE_from_master_m_rready, - CAN_FIRE_from_master_m_wvalid, - CAN_FIRE_reset, - CAN_FIRE_to_slave_m_arready, - CAN_FIRE_to_slave_m_awready, - CAN_FIRE_to_slave_m_bvalid, - CAN_FIRE_to_slave_m_rvalid, - CAN_FIRE_to_slave_m_wready, - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave, - WILL_FIRE_from_master_m_arvalid, - WILL_FIRE_from_master_m_awvalid, - WILL_FIRE_from_master_m_bready, - WILL_FIRE_from_master_m_rready, - WILL_FIRE_from_master_m_wvalid, - WILL_FIRE_reset, - WILL_FIRE_to_slave_m_arready, - WILL_FIRE_to_slave_m_awready, - WILL_FIRE_to_slave_m_bvalid, - WILL_FIRE_to_slave_m_rvalid, - WILL_FIRE_to_slave_m_wready; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2, - MUX_m_rg_b_beat_count$write_1__VAL_2, - MUX_m_rg_r_beat_count$write_1__VAL_2, - MUX_m_rg_w_beat_count$write_1__VAL_2; - wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2; - wire MUX_m_rg_b_resp$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2430; - reg [31 : 0] v__h1446; - reg [31 : 0] v__h1440; - reg [31 : 0] v__h2424; - // synopsys translate_on - - // remaining internal signals - wire [63 : 0] a_out_araddr__h2944, - a_out_awaddr__h1951, - addr___1__h2036, - addr___1__h3029; - wire [7 : 0] x__h2305, x__h2798, x__h3190, x__h3388; - wire m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95, - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51, - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106, - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35; - - // action method reset - assign RDY_reset = !m_rg_reset ; - assign CAN_FIRE_reset = !m_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method from_master_m_awvalid - assign CAN_FIRE_from_master_m_awvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_awvalid = 1'd1 ; - - // value method from_master_m_awready - assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ; - - // action method from_master_m_wvalid - assign CAN_FIRE_from_master_m_wvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_wvalid = 1'd1 ; - - // value method from_master_m_wready - assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ; - - // value method from_master_m_bvalid - assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ; - - // value method from_master_m_bid - assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ; - - // value method from_master_m_bresp - assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ; - - // action method from_master_m_bready - assign CAN_FIRE_from_master_m_bready = 1'd1 ; - assign WILL_FIRE_from_master_m_bready = 1'd1 ; - - // action method from_master_m_arvalid - assign CAN_FIRE_from_master_m_arvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_arvalid = 1'd1 ; - - // value method from_master_m_arready - assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ; - - // value method from_master_m_rvalid - assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ; - - // value method from_master_m_rid - assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ; - - // value method from_master_m_rdata - assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ; - - // value method from_master_m_rresp - assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ; - - // value method from_master_m_rlast - assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ; - - // action method from_master_m_rready - assign CAN_FIRE_from_master_m_rready = 1'd1 ; - assign WILL_FIRE_from_master_m_rready = 1'd1 ; - - // value method to_slave_m_awvalid - assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ; - - // value method to_slave_m_awid - assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ; - - // value method to_slave_m_awaddr - assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ; - - // value method to_slave_m_awlen - assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ; - - // value method to_slave_m_awsize - assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ; - - // value method to_slave_m_awburst - assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ; - - // value method to_slave_m_awlock - assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ; - - // value method to_slave_m_awcache - assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ; - - // value method to_slave_m_awprot - assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ; - - // value method to_slave_m_awqos - assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ; - - // value method to_slave_m_awregion - assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ; - - // action method to_slave_m_awready - assign CAN_FIRE_to_slave_m_awready = 1'd1 ; - assign WILL_FIRE_to_slave_m_awready = 1'd1 ; - - // value method to_slave_m_wvalid - assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ; - - // value method to_slave_m_wid - assign to_slave_wid = m_xactor_to_slave_f_wr_data$D_OUT[76:73] ; - - // value method to_slave_m_wdata - assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ; - - // value method to_slave_m_wstrb - assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ; - - // value method to_slave_m_wlast - assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ; - - // action method to_slave_m_wready - assign CAN_FIRE_to_slave_m_wready = 1'd1 ; - assign WILL_FIRE_to_slave_m_wready = 1'd1 ; - - // action method to_slave_m_bvalid - assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ; - - // value method to_slave_m_bready - assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ; - - // value method to_slave_m_arvalid - assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ; - - // value method to_slave_m_arid - assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ; - - // value method to_slave_m_araddr - assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ; - - // value method to_slave_m_arlen - assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ; - - // value method to_slave_m_arsize - assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ; - - // value method to_slave_m_arburst - assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ; - - // value method to_slave_m_arlock - assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ; - - // value method to_slave_m_arcache - assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ; - - // value method to_slave_m_arprot - assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ; - - // value method to_slave_m_arqos - assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ; - - // value method to_slave_m_arregion - assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ; - - // action method to_slave_m_arready - assign CAN_FIRE_to_slave_m_arready = 1'd1 ; - assign WILL_FIRE_to_slave_m_arready = 1'd1 ; - - // action method to_slave_m_rvalid - assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ; - - // value method to_slave_m_rready - assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ; - - // submodule m_f_r_arlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_r_arlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_r_arlen$D_IN), - .ENQ(m_f_r_arlen$ENQ), - .DEQ(m_f_r_arlen$DEQ), - .CLR(m_f_r_arlen$CLR), - .D_OUT(m_f_r_arlen$D_OUT), - .FULL_N(m_f_r_arlen$FULL_N), - .EMPTY_N(m_f_r_arlen$EMPTY_N)); - - // submodule m_f_w_awlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_w_awlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_w_awlen$D_IN), - .ENQ(m_f_w_awlen$ENQ), - .DEQ(m_f_w_awlen$DEQ), - .CLR(m_f_w_awlen$CLR), - .D_OUT(m_f_w_awlen$D_OUT), - .FULL_N(m_f_w_awlen$FULL_N), - .EMPTY_N(m_f_w_awlen$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_addr$D_IN), - .ENQ(m_xactor_from_master_f_rd_addr$ENQ), - .DEQ(m_xactor_from_master_f_rd_addr$DEQ), - .CLR(m_xactor_from_master_f_rd_addr$CLR), - .D_OUT(m_xactor_from_master_f_rd_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_data$D_IN), - .ENQ(m_xactor_from_master_f_rd_data$ENQ), - .DEQ(m_xactor_from_master_f_rd_data$DEQ), - .CLR(m_xactor_from_master_f_rd_data$CLR), - .D_OUT(m_xactor_from_master_f_rd_data$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_addr$D_IN), - .ENQ(m_xactor_from_master_f_wr_addr$ENQ), - .DEQ(m_xactor_from_master_f_wr_addr$DEQ), - .CLR(m_xactor_from_master_f_wr_addr$CLR), - .D_OUT(m_xactor_from_master_f_wr_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_data$D_IN), - .ENQ(m_xactor_from_master_f_wr_data$ENQ), - .DEQ(m_xactor_from_master_f_wr_data$DEQ), - .CLR(m_xactor_from_master_f_wr_data$CLR), - .D_OUT(m_xactor_from_master_f_wr_data$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_resp$D_IN), - .ENQ(m_xactor_from_master_f_wr_resp$ENQ), - .DEQ(m_xactor_from_master_f_wr_resp$DEQ), - .CLR(m_xactor_from_master_f_wr_resp$CLR), - .D_OUT(m_xactor_from_master_f_wr_resp$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_addr$D_IN), - .ENQ(m_xactor_to_slave_f_rd_addr$ENQ), - .DEQ(m_xactor_to_slave_f_rd_addr$DEQ), - .CLR(m_xactor_to_slave_f_rd_addr$CLR), - .D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_data$D_IN), - .ENQ(m_xactor_to_slave_f_rd_data$ENQ), - .DEQ(m_xactor_to_slave_f_rd_data$DEQ), - .CLR(m_xactor_to_slave_f_rd_data$CLR), - .D_OUT(m_xactor_to_slave_f_rd_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_addr$D_IN), - .ENQ(m_xactor_to_slave_f_wr_addr$ENQ), - .DEQ(m_xactor_to_slave_f_wr_addr$DEQ), - .CLR(m_xactor_to_slave_f_wr_addr$CLR), - .D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_data$D_IN), - .ENQ(m_xactor_to_slave_f_wr_data$ENQ), - .DEQ(m_xactor_to_slave_f_wr_data$DEQ), - .CLR(m_xactor_to_slave_f_wr_data$CLR), - .D_OUT(m_xactor_to_slave_f_wr_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_resp$D_IN), - .ENQ(m_xactor_to_slave_f_wr_resp$ENQ), - .DEQ(m_xactor_to_slave_f_wr_resp$DEQ), - .CLR(m_xactor_to_slave_f_wr_resp$CLR), - .D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave = - m_xactor_to_slave_f_wr_addr$FULL_N && - m_xactor_from_master_f_wr_addr$EMPTY_N && - m_xactor_to_slave_f_wr_data$FULL_N && - m_xactor_from_master_f_wr_data$EMPTY_N && - (m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - - // rule RL_m_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master = - m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N && - (m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 || - m_xactor_from_master_f_wr_resp$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - - // rule RL_m_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave = - m_xactor_to_slave_f_rd_addr$FULL_N && - m_xactor_from_master_f_rd_addr$EMPTY_N && - (m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - - // rule RL_m_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master = - m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N && - m_xactor_from_master_f_rd_data$FULL_N ; - assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ; - assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_b_resp$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - (m_rg_b_resp == 2'b0 && - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 || - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51) ; - assign MUX_m_rg_ar_beat_count$write_1__VAL_2 = - m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ? - x__h3190 : - 8'd0 ; - assign MUX_m_rg_b_beat_count$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - x__h2798 : - 8'd0 ; - assign MUX_m_rg_b_resp$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - 2'b0 ; - assign MUX_m_rg_r_beat_count$write_1__VAL_2 = - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ? - x__h3388 : - 8'd0 ; - assign MUX_m_rg_w_beat_count$write_1__VAL_2 = - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ? - x__h2305 : - 8'd0 ; - - // register m_rg_ar_beat_count - assign m_rg_ar_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ; - assign m_rg_ar_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ; - - // register m_rg_b_beat_count - assign m_rg_b_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ; - assign m_rg_b_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ; - - // register m_rg_b_resp - assign m_rg_b_resp$D_IN = - m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ; - assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ; - - // register m_rg_r_beat_count - assign m_rg_r_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ; - assign m_rg_r_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ; - - // register m_rg_reset - assign m_rg_reset$D_IN = !m_rg_reset ; - assign m_rg_reset$EN = m_rg_reset || EN_reset ; - - // register m_rg_w_beat_count - assign m_rg_w_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ; - assign m_rg_w_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ; - - // submodule m_f_r_arlen - assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_f_r_arlen$ENQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - m_rg_ar_beat_count == 8'd0 ; - assign m_f_r_arlen$DEQ = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master && - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ; - assign m_f_r_arlen$CLR = m_rg_reset ; - - // submodule m_f_w_awlen - assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign m_f_w_awlen$ENQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - m_rg_w_beat_count == 8'd0 ; - assign m_f_w_awlen$DEQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_f_w_awlen$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_addr - assign m_xactor_from_master_f_rd_addr$D_IN = - { from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion } ; - assign m_xactor_from_master_f_rd_addr$ENQ = - from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ; - assign m_xactor_from_master_f_rd_addr$DEQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - !m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ; - assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_data - assign m_xactor_from_master_f_rd_data$D_IN = - { m_xactor_to_slave_f_rd_data$D_OUT[70:1], - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 } ; - assign m_xactor_from_master_f_rd_data$ENQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_from_master_f_rd_data$DEQ = - from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ; - assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_addr - assign m_xactor_from_master_f_wr_addr$D_IN = - { from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion } ; - assign m_xactor_from_master_f_wr_addr$ENQ = - from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ; - assign m_xactor_from_master_f_wr_addr$DEQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ; - assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_data - assign m_xactor_from_master_f_wr_data$D_IN = - { from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast } ; - assign m_xactor_from_master_f_wr_data$ENQ = - from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ; - assign m_xactor_from_master_f_wr_data$DEQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_resp - assign m_xactor_from_master_f_wr_resp$D_IN = - { m_xactor_to_slave_f_wr_resp$D_OUT[5:2], - (m_rg_b_resp == 2'b0) ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - m_rg_b_resp } ; - assign m_xactor_from_master_f_wr_resp$ENQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_xactor_from_master_f_wr_resp$DEQ = - from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ; - assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_addr - assign m_xactor_to_slave_f_rd_addr$D_IN = - { m_xactor_from_master_f_rd_addr$D_OUT[96:93], - a_out_araddr__h2944, - 8'd0, - m_xactor_from_master_f_rd_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_rd_addr$ENQ = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - assign m_xactor_to_slave_f_rd_addr$DEQ = - m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ; - assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_data - assign m_xactor_to_slave_f_rd_data$D_IN = - { to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast } ; - assign m_xactor_to_slave_f_rd_data$ENQ = - to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ; - assign m_xactor_to_slave_f_rd_data$DEQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_addr - assign m_xactor_to_slave_f_wr_addr$D_IN = - { m_xactor_from_master_f_wr_addr$D_OUT[96:93], - a_out_awaddr__h1951, - 8'd0, - m_xactor_from_master_f_wr_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_wr_addr$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_addr$DEQ = - m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ; - assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_data - assign m_xactor_to_slave_f_wr_data$D_IN = - { m_xactor_from_master_f_wr_data$D_OUT[76:1], 1'd1 } ; - assign m_xactor_to_slave_f_wr_data$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_data$DEQ = - m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ; - assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_resp - assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ; - assign m_xactor_to_slave_f_wr_resp$ENQ = - to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ; - assign m_xactor_to_slave_f_wr_resp$DEQ = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ; - - // remaining internal signals - assign a_out_araddr__h2944 = - (m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h3029 : - m_xactor_from_master_f_rd_addr$D_OUT[92:29] ; - assign a_out_awaddr__h1951 = - (m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h2036 : - m_xactor_from_master_f_wr_addr$D_OUT[92:29] ; - assign addr___1__h2036 = - m_xactor_from_master_f_wr_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_w_beat_count } << - m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ; - assign addr___1__h3029 = - m_xactor_from_master_f_rd_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_ar_beat_count } << - m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ; - assign m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 = - m_rg_ar_beat_count < - m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 = - m_rg_b_beat_count < m_f_w_awlen$D_OUT ; - assign m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 = - m_rg_r_beat_count < m_f_r_arlen$D_OUT ; - assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 = - m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign x__h2305 = m_rg_w_beat_count + 8'd1 ; - assign x__h2798 = m_rg_b_beat_count + 8'd1 ; - assign x__h3190 = m_rg_ar_beat_count + 8'd1 ; - assign x__h3388 = m_rg_r_beat_count + 8'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0; - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (m_rg_ar_beat_count$EN) - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN; - if (m_rg_b_beat_count$EN) - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN; - if (m_rg_b_resp$EN) - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN; - if (m_rg_r_beat_count$EN) - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN; - if (m_rg_reset$EN) - m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN; - if (m_rg_w_beat_count$EN) - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_ar_beat_count = 8'hAA; - m_rg_b_beat_count = 8'hAA; - m_rg_b_resp = 2'h2; - m_rg_r_beat_count = 8'hAA; - m_rg_reset = 1'h0; - m_rg_w_beat_count = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - begin - v__h2430 = $stime; - #0; - end - v__h2424 = v__h2430 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", - v__h2424); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display(" WLAST not set on last data beat (awlen = %0d)", - m_xactor_from_master_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) - begin - v__h1446 = $stime; - #0; - end - v__h1440 = v__h1446 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) $display("%0d: %m::AXI4_Deburster.rl_reset", v__h1440); - end - // synopsys translate_on -endmodule // mkAXI4_Deburster_A - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v deleted file mode 100644 index 41b42457..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkBoot_ROM.v +++ /dev/null @@ -1,2157 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkBoot_ROM(CLK, - RST_N, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready); - input CLK; - input RST_N; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_set_addr_map, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_module_ready - reg rg_module_ready; - wire rg_module_ready$D_IN, rg_module_ready$EN; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h808; - reg [31 : 0] v__h8928; - reg [31 : 0] v__h9221; - reg [31 : 0] v__h9331; - reg [31 : 0] v__h802; - reg [31 : 0] v__h8922; - reg [31 : 0] v__h9215; - reg [31 : 0] v__h9325; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] data64__h987; - reg [31 : 0] CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2; - wire [63 : 0] byte_addr__h705, rdata__h924; - wire [1 : 0] rdr_rresp__h957; - wire NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18, - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_module_ready - assign rg_module_ready$D_IN = 1'd1 ; - assign rg_module_ready$EN = EN_set_addr_map ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h924, - rdr_rresp__h957, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 ? - 2'b10 : - 2'b0 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = 1'b0 ; - - // remaining internal signals - assign NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 = - slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] || - slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ; - assign NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 = - slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] || - slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ; - assign byte_addr__h705 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign rdata__h924 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 64'd0 : - data64__h987 ; - assign rdr_rresp__h957 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 2'b10 : - 2'b0 ; - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16, - 64'd24, - 64'd56, - 64'd72, - 64'd80, - 64'd88, - 64'd200, - 64'd232, - 64'd312, - 64'd424, - 64'd448, - 64'd600, - 64'd728, - 64'd1136, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = 32'h0; - 64'd32: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h54040000; - 64'd40: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h88030000; - 64'd48: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h11000000; - 64'd64: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h50030000; - 64'd96, - 64'd112, - 64'd208, - 64'd224, - 64'd240, - 64'd432, - 64'd488, - 64'd872, - 64'd888: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h04000000; - 64'd104, 64'd120, 64'd504, 64'd792, 64'd920: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h02000000; - 64'd128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h16000000; - 64'd136: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h62626375; - 64'd144: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656B6970; - 64'd152: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65642D65; - 64'd160, - 64'd264, - 64'd280, - 64'd296, - 64'd336, - 64'd360, - 64'd384, - 64'd456, - 64'd552, - 64'd592, - 64'd608, - 64'd624, - 64'd672, - 64'd704, - 64'd760, - 64'd816, - 64'd840, - 64'd880: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h03000000; - 64'd168: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h26000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h732C7261; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7261622D; - 64'd192, - 64'd216, - 64'd400, - 64'd440, - 64'd496, - 64'd512, - 64'd584, - 64'd744, - 64'd752, - 64'd912: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h01000000; - 64'd248, 64'd896: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h80969800; - 64'd256: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40757063; - 64'd272: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h3F000000; - 64'd288, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4B000000; - 64'd304: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4F000000; - 64'd320: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h06000000; - 64'd328: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h63736972; - 64'd344: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h56000000; - 64'd352: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h75616D69; - 64'd368: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h60000000; - 64'd376: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h76732C76; - 64'd392: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69000000; - 64'd408: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70757272; - 64'd416: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F72746E; - 64'd464, 64'd632, 64'd712, 64'd824: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h1B000000; - 64'd472: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70632C76; - 64'd480: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00006374; - 64'd520: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h38407972; - 64'd528: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00303030; - 64'd536: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h07000000; - 64'd544: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D656D; - 64'd568: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000080; - 64'd576: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000010; - 64'd616: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h0F000000; - 64'd656: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69730063; - 64'd664: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7375622D; - 64'd680: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hA7000000; - 64'd688: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E696C63; - 64'd696, 64'd808: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h30303030; - 64'd720: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C632C76; - 64'd736: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h10000000; - 64'd776: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000002; - 64'd784: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000C00; - 64'd800: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h74726175; - 64'd832: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61303535; - 64'd856: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h000000C0; - 64'd864: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40000000; - 64'd904: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h08000000; - 64'd928: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h09000000; - 64'd936: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73736572; - 64'd944: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h2300736C; - 64'd952: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C65632D; - 64'd960: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61706D6F; - 64'd968: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D0065; - 64'd976: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656D6974; - 64'd984: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6572662D; - 64'd992: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h64007963; - 64'd1000: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79745F65; - 64'd1008: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73006765; - 64'd1016: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69720073; - 64'd1024: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00617369; - 64'd1032: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65707974; - 64'd1040: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h662D6B63; - 64'd1048: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79636E65; - 64'd1056, 64'd1072: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h72726574; - 64'd1064: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C6C6563; - 64'd1080: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h746E6F63; - 64'd1088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70007265; - 64'd1096: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7200656C; - 64'd1104: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E690073; - 64'd1112: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73747075; - 64'd1120: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65646E65; - 64'd1128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h68732D67; - default: CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00028067; - 64'd24: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80000000; - 64'd32: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hEDFE0DD0; - 64'd40: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h38000000; - 64'd48: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h28000000; - 64'd56, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h10000000; - 64'd64: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hCC000000; - 64'd72, - 64'd80, - 64'd104, - 64'd216, - 64'd296, - 64'd568, - 64'd576, - 64'd672, - 64'd680, - 64'd776, - 64'd784, - 64'd840, - 64'd856, - 64'd864, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = 32'h0; - 64'd88, 64'd256, 64'd688, 64'd800: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h01000000; - 64'd96, - 64'd112, - 64'd128, - 64'd208, - 64'd224, - 64'd240, - 64'd320, - 64'd432, - 64'd448, - 64'd488, - 64'd536, - 64'd736, - 64'd752, - 64'd872, - 64'd888, - 64'd904: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h03000000; - 64'd120, 64'd232, 64'd464: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0F000000; - 64'd136, 64'd328: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h1B000000; - 64'd144: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h732C7261; - 64'd152: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7261622D; - 64'd160, 64'd336: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000076; - 64'd168: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h12000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h62626375; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656B6970; - 64'd192: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000065; - 64'd200: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h73757063; - 64'd248: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C000000; - 64'd264, 64'd704, 64'd816: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000030; - 64'd272, 64'd288, 64'd392, 64'd600, 64'd616: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h04000000; - 64'd280: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00757063; - 64'd304: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h05000000; - 64'd312: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79616B6F; - 64'd344: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0A000000; - 64'd352: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h34367672; - 64'd360: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000073; - 64'd368, 64'd920: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0B000000; - 64'd376, 64'd472, 64'd720: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63736972; - 64'd384: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00003933; - 64'd400: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80969800; - 64'd408: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65746E69; - 64'd416: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F632D74; - 64'd424: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72656C6C; - 64'd440: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79000000; - 64'd456: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h8A000000; - 64'd480: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692D75; - 64'd496: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h9F000000; - 64'd504, 64'd512, 64'd584, 64'd608, 64'd624, 64'd792, 64'd928: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h02000000; - 64'd520: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6D656D; - 64'd528: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30303030; - 64'd544: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3F000000; - 64'd552: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00007972; - 64'd592: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00636F73; - 64'd632: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h21000000; - 64'd656: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F732D65; - 64'd664: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656C706D; - 64'd696: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30324074; - 64'd712: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0D000000; - 64'd728: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30746E69; - 64'd744, 64'd912: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAE000000; - 64'd760: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h07000000; - 64'd808: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30306340; - 64'd824: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h09000000; - 64'd832: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3631736E; - 64'd880: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hC2000000; - 64'd896: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h69000000; - 64'd936: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h64646123; - 64'd944: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C65632D; - 64'd952: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h657A6973; - 64'd960: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6300736C; - 64'd968: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C626974; - 64'd976: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h006C6564; - 64'd984: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65736162; - 64'd992: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E657571; - 64'd1000: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63697665; - 64'd1008: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72006570; - 64'd1016: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75746174; - 64'd1024: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C766373; - 64'd1032: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D756D6D; - 64'd1040: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6C6300; - 64'd1048: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75716572; - 64'd1056: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692300; - 64'd1064, 64'd1080: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D747075; - 64'd1072: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E690073; - 64'd1088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C6C6F72; - 64'd1096: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h646E6168; - 64'd1104: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65676E61; - 64'd1112: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72726574; - 64'd1120: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7478652D; - 64'd1128: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65720064; - 64'd1136: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00746669; - default: CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705 or - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 or - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2) - begin - case (byte_addr__h705) - 64'd0: data64__h987 = 64'h0202859300000297; - 64'd8: data64__h987 = 64'h0182B283F1402573; - default: data64__h987 = - { CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_module_ready$EN) - rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_module_ready = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - begin - v__h808 = $stime; - #0; - end - v__h802 = v__h808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", - v__h802); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - begin - v__h8928 = $stime; - #0; - end - v__h8922 = v__h8928 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", - v__h8922); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h9221 = $stime; - #0; - end - v__h9215 = v__h9221 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9215, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h9331 = $stime; - #0; - end - v__h9325 = v__h9331 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9325, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkBoot_ROM - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCPU.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCPU.v deleted file mode 100644 index 87171917..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCPU.v +++ /dev/null @@ -1,6297 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// hart0_server_reset_response_get O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_set_verbosity O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// hart0_server_reset_request_put I 1 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// nmi_req_set_not_clear I 1 -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// EN_hart0_server_reset_request_put I 1 -// EN_set_verbosity I 1 -// EN_hart0_server_reset_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> imem_master_rready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> dmem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCPU(CLK, - RST_N, - - hart0_server_reset_request_put, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - nmi_req_set_not_clear, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity); - input CLK; - input RST_N; - - // action method hart0_server_reset_request_put - input hart0_server_reset_request_put; - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // actionvalue method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, - RDY_set_verbosity, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - hart0_server_reset_response_get, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid; - - // register cfg_logdelay - reg [63 : 0] cfg_logdelay; - wire [63 : 0] cfg_logdelay$D_IN; - wire cfg_logdelay$EN; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register imem_rg_f3 - reg [2 : 0] imem_rg_f3; - wire [2 : 0] imem_rg_f3$D_IN; - wire imem_rg_f3$EN; - - // register imem_rg_instr_15_0 - reg [15 : 0] imem_rg_instr_15_0; - wire [15 : 0] imem_rg_instr_15_0$D_IN; - wire imem_rg_instr_15_0$EN; - - // register imem_rg_mstatus_MXR - reg imem_rg_mstatus_MXR; - wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN; - - // register imem_rg_pc - reg [63 : 0] imem_rg_pc; - reg [63 : 0] imem_rg_pc$D_IN; - wire imem_rg_pc$EN; - - // register imem_rg_priv - reg [1 : 0] imem_rg_priv; - wire [1 : 0] imem_rg_priv$D_IN; - wire imem_rg_priv$EN; - - // register imem_rg_satp - reg [63 : 0] imem_rg_satp; - wire [63 : 0] imem_rg_satp$D_IN; - wire imem_rg_satp$EN; - - // register imem_rg_sstatus_SUM - reg imem_rg_sstatus_SUM; - wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN; - - // register imem_rg_tval - reg [63 : 0] imem_rg_tval; - reg [63 : 0] imem_rg_tval$D_IN; - wire imem_rg_tval$EN; - - // register rg_cur_priv - reg [1 : 0] rg_cur_priv; - reg [1 : 0] rg_cur_priv$D_IN; - wire rg_cur_priv$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_next_pc - reg [63 : 0] rg_next_pc; - reg [63 : 0] rg_next_pc$D_IN; - wire rg_next_pc$EN; - - // register rg_run_on_reset - reg rg_run_on_reset; - wire rg_run_on_reset$D_IN, rg_run_on_reset$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_start_CPI_cycles - reg [63 : 0] rg_start_CPI_cycles; - wire [63 : 0] rg_start_CPI_cycles$D_IN; - wire rg_start_CPI_cycles$EN; - - // register rg_start_CPI_instrs - reg [63 : 0] rg_start_CPI_instrs; - wire [63 : 0] rg_start_CPI_instrs$D_IN; - wire rg_start_CPI_instrs$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register stage1_rg_full - reg stage1_rg_full; - reg stage1_rg_full$D_IN; - wire stage1_rg_full$EN; - - // register stage2_rg_full - reg stage2_rg_full; - reg stage2_rg_full$D_IN; - wire stage2_rg_full$EN; - - // register stage2_rg_resetting - reg stage2_rg_resetting; - wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN; - - // register stage2_rg_stage2 - reg [297 : 0] stage2_rg_stage2; - wire [297 : 0] stage2_rg_stage2$D_IN; - wire stage2_rg_stage2$EN; - - // register stage3_rg_full - reg stage3_rg_full; - reg stage3_rg_full$D_IN; - wire stage3_rg_full$EN; - - // register stage3_rg_stage3 - reg [167 : 0] stage3_rg_stage3; - wire [167 : 0] stage3_rg_stage3$D_IN; - wire stage3_rg_stage3$EN; - - // ports of submodule csr_regfile - reg [63 : 0] csr_regfile$csr_trap_actions_xtval; - reg [3 : 0] csr_regfile$csr_trap_actions_exc_code; - reg [1 : 0] csr_regfile$csr_ret_actions_from_priv; - wire [193 : 0] csr_regfile$csr_trap_actions; - wire [129 : 0] csr_regfile$csr_ret_actions; - wire [64 : 0] csr_regfile$read_csr; - wire [63 : 0] csr_regfile$csr_trap_actions_pc, - csr_regfile$mav_csr_write_word, - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - csr_regfile$read_mstatus, - csr_regfile$read_satp; - wire [27 : 0] csr_regfile$read_misa; - wire [11 : 0] csr_regfile$access_permitted_1_csr_addr, - csr_regfile$access_permitted_2_csr_addr, - csr_regfile$csr_counter_read_fault_csr_addr, - csr_regfile$mav_csr_write_csr_addr, - csr_regfile$mav_read_csr_csr_addr, - csr_regfile$read_csr_csr_addr, - csr_regfile$read_csr_port2_csr_addr; - wire [4 : 0] csr_regfile$interrupt_pending; - wire [1 : 0] csr_regfile$access_permitted_1_priv, - csr_regfile$access_permitted_2_priv, - csr_regfile$csr_counter_read_fault_priv, - csr_regfile$csr_trap_actions_from_priv, - csr_regfile$interrupt_pending_cur_priv; - wire csr_regfile$EN_csr_minstret_incr, - csr_regfile$EN_csr_ret_actions, - csr_regfile$EN_csr_trap_actions, - csr_regfile$EN_debug, - csr_regfile$EN_mav_csr_write, - csr_regfile$EN_mav_read_csr, - csr_regfile$EN_server_reset_request_put, - csr_regfile$EN_server_reset_response_get, - csr_regfile$RDY_server_reset_request_put, - csr_regfile$RDY_server_reset_response_get, - csr_regfile$access_permitted_1, - csr_regfile$access_permitted_1_read_not_write, - csr_regfile$access_permitted_2, - csr_regfile$access_permitted_2_read_not_write, - csr_regfile$csr_trap_actions_interrupt, - csr_regfile$csr_trap_actions_nmi, - csr_regfile$m_external_interrupt_req_set_not_clear, - csr_regfile$nmi_pending, - csr_regfile$nmi_req_set_not_clear, - csr_regfile$s_external_interrupt_req_set_not_clear, - csr_regfile$software_interrupt_req_set_not_clear, - csr_regfile$timer_interrupt_req_set_not_clear, - csr_regfile$wfi_resume; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule gpr_regfile - wire [63 : 0] gpr_regfile$read_rs1, - gpr_regfile$read_rs2, - gpr_regfile$write_rd_rd_val; - wire [4 : 0] gpr_regfile$read_rs1_port2_rs1, - gpr_regfile$read_rs1_rs1, - gpr_regfile$read_rs2_rs2, - gpr_regfile$write_rd_rd; - wire gpr_regfile$EN_server_reset_request_put, - gpr_regfile$EN_server_reset_response_get, - gpr_regfile$EN_write_rd, - gpr_regfile$RDY_server_reset_request_put, - gpr_regfile$RDY_server_reset_response_get; - - // ports of submodule near_mem - reg [63 : 0] near_mem$imem_req_addr; - reg [1 : 0] near_mem$dmem_req_op; - reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM; - wire [63 : 0] near_mem$dmem_master_araddr, - near_mem$dmem_master_awaddr, - near_mem$dmem_master_rdata, - near_mem$dmem_master_wdata, - near_mem$dmem_req_addr, - near_mem$dmem_req_satp, - near_mem$dmem_req_store_value, - near_mem$dmem_word64, - near_mem$imem_master_araddr, - near_mem$imem_master_awaddr, - near_mem$imem_master_rdata, - near_mem$imem_master_wdata, - near_mem$imem_pc, - near_mem$imem_req_satp; - wire [31 : 0] near_mem$imem_instr; - wire [7 : 0] near_mem$dmem_master_arlen, - near_mem$dmem_master_awlen, - near_mem$dmem_master_wstrb, - near_mem$imem_master_arlen, - near_mem$imem_master_awlen, - near_mem$imem_master_wstrb, - near_mem$server_fence_request_put; - wire [6 : 0] near_mem$dmem_req_amo_funct7; - wire [3 : 0] near_mem$dmem_exc_code, - near_mem$dmem_master_arcache, - near_mem$dmem_master_arid, - near_mem$dmem_master_arqos, - near_mem$dmem_master_arregion, - near_mem$dmem_master_awcache, - near_mem$dmem_master_awid, - near_mem$dmem_master_awqos, - near_mem$dmem_master_awregion, - near_mem$dmem_master_bid, - near_mem$dmem_master_rid, - near_mem$dmem_master_wid, - near_mem$imem_exc_code, - near_mem$imem_master_arcache, - near_mem$imem_master_arid, - near_mem$imem_master_arqos, - near_mem$imem_master_arregion, - near_mem$imem_master_awcache, - near_mem$imem_master_awid, - near_mem$imem_master_awqos, - near_mem$imem_master_awregion, - near_mem$imem_master_bid, - near_mem$imem_master_rid, - near_mem$imem_master_wid; - wire [2 : 0] near_mem$dmem_master_arprot, - near_mem$dmem_master_arsize, - near_mem$dmem_master_awprot, - near_mem$dmem_master_awsize, - near_mem$dmem_req_f3, - near_mem$imem_master_arprot, - near_mem$imem_master_arsize, - near_mem$imem_master_awprot, - near_mem$imem_master_awsize, - near_mem$imem_req_f3; - wire [1 : 0] near_mem$dmem_master_arburst, - near_mem$dmem_master_awburst, - near_mem$dmem_master_bresp, - near_mem$dmem_master_rresp, - near_mem$dmem_req_priv, - near_mem$imem_master_arburst, - near_mem$imem_master_awburst, - near_mem$imem_master_bresp, - near_mem$imem_master_rresp, - near_mem$imem_req_priv; - wire near_mem$EN_dmem_req, - near_mem$EN_imem_req, - near_mem$EN_server_fence_i_request_put, - near_mem$EN_server_fence_i_response_get, - near_mem$EN_server_fence_request_put, - near_mem$EN_server_fence_response_get, - near_mem$EN_server_reset_request_put, - near_mem$EN_server_reset_response_get, - near_mem$EN_sfence_vma, - near_mem$RDY_server_fence_i_request_put, - near_mem$RDY_server_fence_i_response_get, - near_mem$RDY_server_fence_request_put, - near_mem$RDY_server_fence_response_get, - near_mem$RDY_server_reset_request_put, - near_mem$RDY_server_reset_response_get, - near_mem$dmem_exc, - near_mem$dmem_master_arlock, - near_mem$dmem_master_arready, - near_mem$dmem_master_arvalid, - near_mem$dmem_master_awlock, - near_mem$dmem_master_awready, - near_mem$dmem_master_awvalid, - near_mem$dmem_master_bready, - near_mem$dmem_master_bvalid, - near_mem$dmem_master_rlast, - near_mem$dmem_master_rready, - near_mem$dmem_master_rvalid, - near_mem$dmem_master_wlast, - near_mem$dmem_master_wready, - near_mem$dmem_master_wvalid, - near_mem$dmem_req_mstatus_MXR, - near_mem$dmem_req_sstatus_SUM, - near_mem$dmem_valid, - near_mem$imem_exc, - near_mem$imem_is_i32_not_i16, - near_mem$imem_master_arlock, - near_mem$imem_master_arready, - near_mem$imem_master_arvalid, - near_mem$imem_master_awlock, - near_mem$imem_master_awready, - near_mem$imem_master_awvalid, - near_mem$imem_master_bready, - near_mem$imem_master_bvalid, - near_mem$imem_master_rlast, - near_mem$imem_master_rready, - near_mem$imem_master_rvalid, - near_mem$imem_master_wlast, - near_mem$imem_master_wready, - near_mem$imem_master_wvalid, - near_mem$imem_valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_pc_reset_value; - - // ports of submodule stage1_f_reset_reqs - wire stage1_f_reset_reqs$CLR, - stage1_f_reset_reqs$DEQ, - stage1_f_reset_reqs$EMPTY_N, - stage1_f_reset_reqs$ENQ, - stage1_f_reset_reqs$FULL_N; - - // ports of submodule stage1_f_reset_rsps - wire stage1_f_reset_rsps$CLR, - stage1_f_reset_rsps$DEQ, - stage1_f_reset_rsps$EMPTY_N, - stage1_f_reset_rsps$ENQ, - stage1_f_reset_rsps$FULL_N; - - // ports of submodule stage2_f_reset_reqs - wire stage2_f_reset_reqs$CLR, - stage2_f_reset_reqs$DEQ, - stage2_f_reset_reqs$EMPTY_N, - stage2_f_reset_reqs$ENQ, - stage2_f_reset_reqs$FULL_N; - - // ports of submodule stage2_f_reset_rsps - wire stage2_f_reset_rsps$CLR, - stage2_f_reset_rsps$DEQ, - stage2_f_reset_rsps$EMPTY_N, - stage2_f_reset_rsps$ENQ, - stage2_f_reset_rsps$FULL_N; - - // ports of submodule stage2_mbox - wire [63 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word; - wire [3 : 0] stage2_mbox$set_verbosity_verbosity; - wire [2 : 0] stage2_mbox$req_f3; - wire stage2_mbox$EN_req, - stage2_mbox$EN_req_reset, - stage2_mbox$EN_rsp_reset, - stage2_mbox$EN_set_verbosity, - stage2_mbox$req_is_OP_not_OP_32, - stage2_mbox$valid; - - // ports of submodule stage3_f_reset_reqs - wire stage3_f_reset_reqs$CLR, - stage3_f_reset_reqs$DEQ, - stage3_f_reset_reqs$EMPTY_N, - stage3_f_reset_reqs$ENQ, - stage3_f_reset_reqs$FULL_N; - - // ports of submodule stage3_f_reset_rsps - wire stage3_f_reset_rsps$CLR, - stage3_f_reset_rsps$DEQ, - stage3_f_reset_rsps$EMPTY_N, - stage3_f_reset_rsps$ENQ, - stage3_f_reset_rsps$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_imem_rl_assert_fail, - CAN_FIRE_RL_imem_rl_fetch_next_32b, - CAN_FIRE_RL_rl_WFI_resume, - CAN_FIRE_RL_rl_finish_FENCE, - CAN_FIRE_RL_rl_finish_FENCE_I, - CAN_FIRE_RL_rl_finish_SFENCE_VMA, - CAN_FIRE_RL_rl_pipe, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_RL_rl_reset_from_WFI, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_show_pipe, - CAN_FIRE_RL_rl_stage1_CSRR_S_or_C, - CAN_FIRE_RL_rl_stage1_CSRR_W, - CAN_FIRE_RL_rl_stage1_FENCE, - CAN_FIRE_RL_rl_stage1_FENCE_I, - CAN_FIRE_RL_rl_stage1_SFENCE_VMA, - CAN_FIRE_RL_rl_stage1_WFI, - CAN_FIRE_RL_rl_stage1_interrupt, - CAN_FIRE_RL_rl_stage1_restart_after_csrrx, - CAN_FIRE_RL_rl_stage1_trap, - CAN_FIRE_RL_rl_stage1_xRET, - CAN_FIRE_RL_rl_stage2_nonpipe, - CAN_FIRE_RL_rl_trap_fetch, - CAN_FIRE_RL_stage1_rl_reset, - CAN_FIRE_RL_stage2_rl_reset_begin, - CAN_FIRE_RL_stage2_rl_reset_end, - CAN_FIRE_RL_stage3_rl_reset, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_set_verbosity, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_imem_rl_assert_fail, - WILL_FIRE_RL_imem_rl_fetch_next_32b, - WILL_FIRE_RL_rl_WFI_resume, - WILL_FIRE_RL_rl_finish_FENCE, - WILL_FIRE_RL_rl_finish_FENCE_I, - WILL_FIRE_RL_rl_finish_SFENCE_VMA, - WILL_FIRE_RL_rl_pipe, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_RL_rl_reset_from_WFI, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_show_pipe, - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C, - WILL_FIRE_RL_rl_stage1_CSRR_W, - WILL_FIRE_RL_rl_stage1_FENCE, - WILL_FIRE_RL_rl_stage1_FENCE_I, - WILL_FIRE_RL_rl_stage1_SFENCE_VMA, - WILL_FIRE_RL_rl_stage1_WFI, - WILL_FIRE_RL_rl_stage1_interrupt, - WILL_FIRE_RL_rl_stage1_restart_after_csrrx, - WILL_FIRE_RL_rl_stage1_trap, - WILL_FIRE_RL_rl_stage1_xRET, - WILL_FIRE_RL_rl_stage2_nonpipe, - WILL_FIRE_RL_rl_trap_fetch, - WILL_FIRE_RL_stage1_rl_reset, - WILL_FIRE_RL_stage2_rl_reset_begin, - WILL_FIRE_RL_stage2_rl_reset_end, - WILL_FIRE_RL_stage3_rl_reset, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_set_verbosity, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - reg [63 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2; - wire [63 : 0] MUX_near_mem$imem_req_2__VAL_1, - MUX_near_mem$imem_req_2__VAL_2, - MUX_near_mem$imem_req_2__VAL_5; - wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1, - MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_3; - wire MUX_csr_regfile$mav_csr_write_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_3, - MUX_imem_rg_f3$write_1__SEL_1, - MUX_imem_rg_f3$write_1__SEL_2, - MUX_imem_rg_mstatus_MXR$write_1__SEL_4, - MUX_imem_rg_pc$write_1__SEL_4, - MUX_near_mem$imem_req_1__SEL_6, - MUX_rg_cur_priv$write_1__SEL_1, - MUX_rg_mstatus_MXR$write_1__SEL_1, - MUX_rg_next_pc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_11, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_4, - MUX_rg_state$write_1__SEL_6, - MUX_rg_state$write_1__SEL_7, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9, - MUX_stage1_rg_full$write_1__VAL_2, - MUX_stage2_rg_full$write_1__VAL_2; - - // remaining internal signals - reg [63 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1151, - _theResult_____1_fst__h13382, - alu_outputs___1_val1__h12576, - rs1_val__h18963, - x_out_bypass_rd_val__h6000, - x_out_data_to_stage2_addr__h12206, - x_out_data_to_stage2_val1__h12207, - x_out_data_to_stage3_rd_val__h5649; - reg [4 : 0] x_out_bypass_rd__h5999, x_out_data_to_stage3_rd__h5648; - reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q5, - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14, - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q16, - CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15, - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17, - CASE_theResult__283_BITS_31_TO_20_0b0_CASE_rg__ETC__q6, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d811, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d831, - alu_outputs_exc_code__h12932; - reg [2 : 0] CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18, - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916; - reg [1 : 0] CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q1, - CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2; - reg CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12, - CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762, - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d136, - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145; - wire [127 : 0] csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1401; - wire [63 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1064, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1065, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d962, - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1348, - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d971, - _theResult_____1_fst__h13375, - _theResult_____1_fst__h13410, - _theResult____h23527, - _theResult___fst__h13487, - _theResult___fst__h13494, - _theResult___fst__h13601, - _theResult___snd__h14727, - alu_outputs___1_addr__h12330, - alu_outputs___1_addr__h12351, - alu_outputs___1_addr__h12377, - alu_outputs___1_addr__h12629, - alu_outputs___1_addr__h12650, - alu_outputs___1_val1__h12492, - alu_outputs___1_val1__h12530, - alu_outputs___1_val1__h12553, - alu_outputs___1_val1__h12592, - alu_outputs___1_val1__h12608, - alu_outputs___1_val1__h12890, - alu_outputs___1_val1__h12911, - branch_target__h12308, - cpi__h23529, - cpifrac__h23530, - data_to_stage2_addr__h12198, - delta_CPI_cycles__h23525, - delta_CPI_instrs___1__h23562, - delta_CPI_instrs__h23526, - fall_through_pc__h12162, - next_pc___1__h14260, - next_pc__h14258, - output_stage2___1_bypass_rd_val__h5988, - rd_val___1__h13363, - rd_val___1__h13371, - rd_val___1__h13378, - rd_val___1__h13385, - rd_val___1__h13392, - rd_val___1__h13399, - rd_val___1__h14756, - rd_val___1__h14787, - rd_val___1__h14841, - rd_val___1__h14870, - rd_val___1__h14922, - rd_val___1__h14970, - rd_val___1__h14976, - rd_val___1__h15021, - rd_val__h12119, - rd_val__h14623, - rd_val__h14675, - rd_val__h14697, - rd_val__h6112, - rs1_val__h18473, - rs1_val_bypassed__h4291, - rs2_val__h12304, - trap_info_tval__h14094, - val__h12121, - val__h6114, - value__h14148, - x__h23528, - x_out_data_to_stage2_val2__h12208, - x_out_next_pc__h12175, - y__h19264; - wire [31 : 0] IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d466, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d467, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d469, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d471, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d473, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d475, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d476, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d477, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d479, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d480, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d481, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d483, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d485, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d486, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d488, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d489, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d490, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d491, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d492, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d493, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d494, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d495, - _theResult____h4283, - _theResult___fst__h6331, - _theResult___fst__h6359, - alu_outputs___1_addr2629_BITS_31_TO_0__q20, - instr___1__h6160, - instr__h10113, - instr__h10291, - instr__h10410, - instr__h10505, - instr__h10641, - instr__h10777, - instr__h10913, - instr__h11051, - instr__h11189, - instr__h11347, - instr__h11443, - instr__h11596, - instr__h11795, - instr__h11946, - instr__h4281, - instr__h6431, - instr__h6576, - instr__h6768, - instr__h6963, - instr__h7192, - instr__h7646, - instr__h7762, - instr__h7827, - instr__h8144, - instr__h8482, - instr__h8666, - instr__h8795, - instr__h9022, - instr__h9277, - instr__h9449, - instr__h9618, - instr__h9807, - instr__h9996, - instr_out___1__h6301, - instr_out___1__h6333, - instr_out___1__h6361, - rs1_val_bypassed291_BITS_31_TO_0_MINUS_rs2_val_ETC__q11, - rs1_val_bypassed291_BITS_31_TO_0_PLUS_rs2_val2_ETC__q10, - rs1_val_bypassed291_BITS_31_TO_0_SRL_rs2_val23_ETC__q9, - rs1_val_bypassed291_BITS_31_TO_0__q8, - tmp__h14869, - v32__h12581, - x__h14790, - x__h14844, - x__h14979, - x__h15024, - x_out_data_to_stage2_instr__h12203; - wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292, - theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q4; - wire [19 : 0] imm20__h8534; - wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317, - theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q3; - wire [11 : 0] imm12__h11444, - imm12__h11796, - imm12__h6432, - imm12__h6769, - imm12__h8406, - imm12__h9075, - imm12__h9290, - imm12__h9486, - imm12__h9823, - offset__h7139, - theResult__283_BITS_31_TO_20__q19, - theResult__283_BITS_31_TO_25_CONCAT_theResult__ETC__q7; - wire [9 : 0] funct10__h12562, nzimm10__h9073, nzimm10__h9288; - wire [8 : 0] offset__h11358, offset__h7771; - wire [7 : 0] offset__h11730, offset__h6202; - wire [6 : 0] offset__h6711; - wire [5 : 0] imm6__h8404, shamt__h12477; - wire [4 : 0] offset_BITS_4_TO_0___h12071, - offset_BITS_4_TO_0___h6700, - offset_BITS_4_TO_0___h7131, - rd__h6771, - rs1__h6770, - x_out_data_to_stage2_rd__h12205; - wire [3 : 0] IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d774, - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833, - IF_rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_E_ETC___d809, - alu_outputs___1_exc_code__h12886, - cur_verbosity__h2988, - x_out_trap_info_exc_code__h14097; - wire [1 : 0] IF_NOT_near_mem_dmem_valid__13_32_OR_NOT_near__ETC___d179, - IF_near_mem_dmem_valid__13_THEN_IF_near_mem_dm_ETC___d116, - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122, - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183, - IF_stage2_rg_stage2_2_BITS_196_TO_192_52_EQ_0__ETC___d178, - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119, - sxl__h4705, - uxl__h4706; - wire IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1209, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d717, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d724, - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d1398, - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499, - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501, - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d605, - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1259, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1291, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1293, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1296, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1310, - NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d899, - NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d940, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d208, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d213, - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1219, - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1230, - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1238, - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504, - _0_OR_0_OR_near_mem_imem_exc__20_OR_IF_IF_NOT_n_ETC___d1289, - csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1212, - csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1217, - csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1223, - csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d302, - csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d308, - gpr_regfile_RDY_server_reset_request_put__161__ETC___d1173, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1076, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1079, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1082, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1085, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1088, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1091, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1094, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1097, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1100, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1103, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1106, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1109, - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d511, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d513, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1208, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770, - rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_EQ_0_ETC___d807, - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313, - rg_state_2_EQ_3_225_AND_stage3_rg_full_2_OR_NO_ETC___d1244, - stage2_f_reset_rsps_i_notEmpty__182_AND_stage3_ETC___d1191; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // actionvalue method hart0_server_reset_response_get - assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ; - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = near_mem$imem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = near_mem$imem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = near_mem$imem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = near_mem$imem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = near_mem$imem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = near_mem$imem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = near_mem$imem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = near_mem$imem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = near_mem$imem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = near_mem$imem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = near_mem$imem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = near_mem$imem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = near_mem$imem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = near_mem$imem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = near_mem$imem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = near_mem$imem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = near_mem$imem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = near_mem$imem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = near_mem$imem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = near_mem$imem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = near_mem$imem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = near_mem$imem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = near_mem$imem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = near_mem$imem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = near_mem$imem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = near_mem$imem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = near_mem$imem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = near_mem$imem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = near_mem$imem_master_rready ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = near_mem$dmem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = near_mem$dmem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = near_mem$dmem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = near_mem$dmem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = near_mem$dmem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = near_mem$dmem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = near_mem$dmem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = near_mem$dmem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = near_mem$dmem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = near_mem$dmem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = near_mem$dmem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = near_mem$dmem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = near_mem$dmem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = near_mem$dmem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = near_mem$dmem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = near_mem$dmem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = near_mem$dmem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = near_mem$dmem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = near_mem$dmem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = near_mem$dmem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = near_mem$dmem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = near_mem$dmem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = near_mem$dmem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = near_mem$dmem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = near_mem$dmem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = near_mem$dmem_master_rready ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // submodule csr_regfile - mkCSR_RegFile csr_regfile(.CLK(CLK), - .RST_N(RST_N), - .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr), - .access_permitted_1_priv(csr_regfile$access_permitted_1_priv), - .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write), - .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr), - .access_permitted_2_priv(csr_regfile$access_permitted_2_priv), - .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write), - .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr), - .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv), - .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv), - .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code), - .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv), - .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt), - .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi), - .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc), - .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval), - .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv), - .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear), - .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr), - .mav_csr_write_word(csr_regfile$mav_csr_write_word), - .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr), - .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear), - .read_csr_csr_addr(csr_regfile$read_csr_csr_addr), - .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr), - .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear), - .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear), - .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get), - .EN_mav_read_csr(csr_regfile$EN_mav_read_csr), - .EN_mav_csr_write(csr_regfile$EN_mav_csr_write), - .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions), - .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions), - .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr), - .EN_debug(csr_regfile$EN_debug), - .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get), - .read_csr(csr_regfile$read_csr), - .read_csr_port2(), - .mav_read_csr(), - .mav_csr_write(), - .read_misa(csr_regfile$read_misa), - .read_mstatus(csr_regfile$read_mstatus), - .read_ustatus(), - .read_satp(csr_regfile$read_satp), - .csr_trap_actions(csr_regfile$csr_trap_actions), - .RDY_csr_trap_actions(), - .csr_ret_actions(csr_regfile$csr_ret_actions), - .RDY_csr_ret_actions(), - .read_csr_minstret(csr_regfile$read_csr_minstret), - .read_csr_mcycle(csr_regfile$read_csr_mcycle), - .read_csr_mtime(), - .access_permitted_1(csr_regfile$access_permitted_1), - .access_permitted_2(csr_regfile$access_permitted_2), - .csr_counter_read_fault(), - .csr_mip_read(), - .interrupt_pending(csr_regfile$interrupt_pending), - .wfi_resume(csr_regfile$wfi_resume), - .nmi_pending(csr_regfile$nmi_pending), - .RDY_debug()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule gpr_regfile - mkGPR_RegFile gpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(gpr_regfile$read_rs1_rs1), - .read_rs2_rs2(gpr_regfile$read_rs2_rs2), - .write_rd_rd(gpr_regfile$write_rd_rd), - .write_rd_rd_val(gpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get), - .EN_write_rd(gpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get), - .read_rs1(gpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(gpr_regfile$read_rs2)); - - // submodule near_mem - mkNear_Mem near_mem(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(near_mem$dmem_master_arready), - .dmem_master_awready(near_mem$dmem_master_awready), - .dmem_master_bid(near_mem$dmem_master_bid), - .dmem_master_bresp(near_mem$dmem_master_bresp), - .dmem_master_bvalid(near_mem$dmem_master_bvalid), - .dmem_master_rdata(near_mem$dmem_master_rdata), - .dmem_master_rid(near_mem$dmem_master_rid), - .dmem_master_rlast(near_mem$dmem_master_rlast), - .dmem_master_rresp(near_mem$dmem_master_rresp), - .dmem_master_rvalid(near_mem$dmem_master_rvalid), - .dmem_master_wready(near_mem$dmem_master_wready), - .dmem_req_addr(near_mem$dmem_req_addr), - .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7), - .dmem_req_f3(near_mem$dmem_req_f3), - .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR), - .dmem_req_op(near_mem$dmem_req_op), - .dmem_req_priv(near_mem$dmem_req_priv), - .dmem_req_satp(near_mem$dmem_req_satp), - .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM), - .dmem_req_store_value(near_mem$dmem_req_store_value), - .imem_master_arready(near_mem$imem_master_arready), - .imem_master_awready(near_mem$imem_master_awready), - .imem_master_bid(near_mem$imem_master_bid), - .imem_master_bresp(near_mem$imem_master_bresp), - .imem_master_bvalid(near_mem$imem_master_bvalid), - .imem_master_rdata(near_mem$imem_master_rdata), - .imem_master_rid(near_mem$imem_master_rid), - .imem_master_rlast(near_mem$imem_master_rlast), - .imem_master_rresp(near_mem$imem_master_rresp), - .imem_master_rvalid(near_mem$imem_master_rvalid), - .imem_master_wready(near_mem$imem_master_wready), - .imem_req_addr(near_mem$imem_req_addr), - .imem_req_f3(near_mem$imem_req_f3), - .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR), - .imem_req_priv(near_mem$imem_req_priv), - .imem_req_satp(near_mem$imem_req_satp), - .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM), - .server_fence_request_put(near_mem$server_fence_request_put), - .EN_server_reset_request_put(near_mem$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem$EN_server_reset_response_get), - .EN_imem_req(near_mem$EN_imem_req), - .EN_dmem_req(near_mem$EN_dmem_req), - .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put), - .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get), - .EN_server_fence_request_put(near_mem$EN_server_fence_request_put), - .EN_server_fence_response_get(near_mem$EN_server_fence_response_get), - .EN_sfence_vma(near_mem$EN_sfence_vma), - .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get), - .imem_valid(near_mem$imem_valid), - .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16), - .imem_pc(near_mem$imem_pc), - .imem_instr(near_mem$imem_instr), - .imem_exc(near_mem$imem_exc), - .imem_exc_code(near_mem$imem_exc_code), - .imem_tval(), - .imem_master_awvalid(near_mem$imem_master_awvalid), - .imem_master_awid(near_mem$imem_master_awid), - .imem_master_awaddr(near_mem$imem_master_awaddr), - .imem_master_awlen(near_mem$imem_master_awlen), - .imem_master_awsize(near_mem$imem_master_awsize), - .imem_master_awburst(near_mem$imem_master_awburst), - .imem_master_awlock(near_mem$imem_master_awlock), - .imem_master_awcache(near_mem$imem_master_awcache), - .imem_master_awprot(near_mem$imem_master_awprot), - .imem_master_awqos(near_mem$imem_master_awqos), - .imem_master_awregion(near_mem$imem_master_awregion), - .imem_master_wvalid(near_mem$imem_master_wvalid), - .imem_master_wid(near_mem$imem_master_wid), - .imem_master_wdata(near_mem$imem_master_wdata), - .imem_master_wstrb(near_mem$imem_master_wstrb), - .imem_master_wlast(near_mem$imem_master_wlast), - .imem_master_bready(near_mem$imem_master_bready), - .imem_master_arvalid(near_mem$imem_master_arvalid), - .imem_master_arid(near_mem$imem_master_arid), - .imem_master_araddr(near_mem$imem_master_araddr), - .imem_master_arlen(near_mem$imem_master_arlen), - .imem_master_arsize(near_mem$imem_master_arsize), - .imem_master_arburst(near_mem$imem_master_arburst), - .imem_master_arlock(near_mem$imem_master_arlock), - .imem_master_arcache(near_mem$imem_master_arcache), - .imem_master_arprot(near_mem$imem_master_arprot), - .imem_master_arqos(near_mem$imem_master_arqos), - .imem_master_arregion(near_mem$imem_master_arregion), - .imem_master_rready(near_mem$imem_master_rready), - .dmem_valid(near_mem$dmem_valid), - .dmem_word64(near_mem$dmem_word64), - .dmem_st_amo_val(), - .dmem_exc(near_mem$dmem_exc), - .dmem_exc_code(near_mem$dmem_exc_code), - .dmem_master_awvalid(near_mem$dmem_master_awvalid), - .dmem_master_awid(near_mem$dmem_master_awid), - .dmem_master_awaddr(near_mem$dmem_master_awaddr), - .dmem_master_awlen(near_mem$dmem_master_awlen), - .dmem_master_awsize(near_mem$dmem_master_awsize), - .dmem_master_awburst(near_mem$dmem_master_awburst), - .dmem_master_awlock(near_mem$dmem_master_awlock), - .dmem_master_awcache(near_mem$dmem_master_awcache), - .dmem_master_awprot(near_mem$dmem_master_awprot), - .dmem_master_awqos(near_mem$dmem_master_awqos), - .dmem_master_awregion(near_mem$dmem_master_awregion), - .dmem_master_wvalid(near_mem$dmem_master_wvalid), - .dmem_master_wid(near_mem$dmem_master_wid), - .dmem_master_wdata(near_mem$dmem_master_wdata), - .dmem_master_wstrb(near_mem$dmem_master_wstrb), - .dmem_master_wlast(near_mem$dmem_master_wlast), - .dmem_master_bready(near_mem$dmem_master_bready), - .dmem_master_arvalid(near_mem$dmem_master_arvalid), - .dmem_master_arid(near_mem$dmem_master_arid), - .dmem_master_araddr(near_mem$dmem_master_araddr), - .dmem_master_arlen(near_mem$dmem_master_arlen), - .dmem_master_arsize(near_mem$dmem_master_arsize), - .dmem_master_arburst(near_mem$dmem_master_arburst), - .dmem_master_arlock(near_mem$dmem_master_arlock), - .dmem_master_arcache(near_mem$dmem_master_arcache), - .dmem_master_arprot(near_mem$dmem_master_arprot), - .dmem_master_arqos(near_mem$dmem_master_arqos), - .dmem_master_arregion(near_mem$dmem_master_arregion), - .dmem_master_rready(near_mem$dmem_master_rready), - .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put), - .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get), - .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put), - .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get), - .RDY_sfence_vma()); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(soc_map$m_pc_reset_value), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule stage1_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_reqs$ENQ), - .DEQ(stage1_f_reset_reqs$DEQ), - .CLR(stage1_f_reset_reqs$CLR), - .FULL_N(stage1_f_reset_reqs$FULL_N), - .EMPTY_N(stage1_f_reset_reqs$EMPTY_N)); - - // submodule stage1_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_rsps$ENQ), - .DEQ(stage1_f_reset_rsps$DEQ), - .CLR(stage1_f_reset_rsps$CLR), - .FULL_N(stage1_f_reset_rsps$FULL_N), - .EMPTY_N(stage1_f_reset_rsps$EMPTY_N)); - - // submodule stage2_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_reqs$ENQ), - .DEQ(stage2_f_reset_reqs$DEQ), - .CLR(stage2_f_reset_reqs$CLR), - .FULL_N(stage2_f_reset_reqs$FULL_N), - .EMPTY_N(stage2_f_reset_reqs$EMPTY_N)); - - // submodule stage2_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_rsps$ENQ), - .DEQ(stage2_f_reset_rsps$DEQ), - .CLR(stage2_f_reset_rsps$CLR), - .FULL_N(stage2_f_reset_rsps$FULL_N), - .EMPTY_N(stage2_f_reset_rsps$EMPTY_N)); - - // submodule stage2_mbox - mkRISCV_MBox stage2_mbox(.CLK(CLK), - .RST_N(RST_N), - .req_f3(stage2_mbox$req_f3), - .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32), - .req_v1(stage2_mbox$req_v1), - .req_v2(stage2_mbox$req_v2), - .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity), - .EN_set_verbosity(stage2_mbox$EN_set_verbosity), - .EN_req_reset(stage2_mbox$EN_req_reset), - .EN_rsp_reset(stage2_mbox$EN_rsp_reset), - .EN_req(stage2_mbox$EN_req), - .RDY_set_verbosity(), - .RDY_req_reset(), - .RDY_rsp_reset(), - .valid(stage2_mbox$valid), - .word(stage2_mbox$word)); - - // submodule stage3_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_reqs$ENQ), - .DEQ(stage3_f_reset_reqs$DEQ), - .CLR(stage3_f_reset_reqs$CLR), - .FULL_N(stage3_f_reset_reqs$FULL_N), - .EMPTY_N(stage3_f_reset_reqs$EMPTY_N)); - - // submodule stage3_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_rsps$ENQ), - .DEQ(stage3_f_reset_rsps$DEQ), - .CLR(stage3_f_reset_rsps$CLR), - .FULL_N(stage3_f_reset_rsps$FULL_N), - .EMPTY_N(stage3_f_reset_rsps$EMPTY_N)); - - // rule RL_rl_show_pipe - assign CAN_FIRE_RL_rl_show_pipe = - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - rg_state != 4'd0 && - rg_state != 4'd1 && - rg_state != 4'd10 ; - assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ; - - // rule RL_rl_stage2_nonpipe - assign CAN_FIRE_RL_rl_stage2_nonpipe = - rg_state == 4'd3 && !stage3_rg_full && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd3 && - (!stage1_rg_full || - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519) ; - assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ; - - // rule RL_rl_stage1_CSRR_W - assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_stage1_CSRR_S_or_C - assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_stage1_restart_after_csrrx - assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx = - CAN_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // rule RL_rl_stage1_xRET - assign CAN_FIRE_RL_rl_stage1_xRET = - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - (IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd7 || - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd8 || - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd9) ; - assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ; - - // rule RL_rl_stage1_FENCE_I - assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - - // rule RL_rl_finish_FENCE_I - assign CAN_FIRE_RL_rl_finish_FENCE_I = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_i_response_get && - rg_state == 4'd7 ; - assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ; - - // rule RL_rl_stage1_FENCE - assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - - // rule RL_rl_finish_FENCE - assign CAN_FIRE_RL_rl_finish_FENCE = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_response_get && - rg_state == 4'd8 ; - assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ; - - // rule RL_rl_stage1_SFENCE_VMA - assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - - // rule RL_rl_finish_SFENCE_VMA - assign CAN_FIRE_RL_rl_finish_SFENCE_VMA = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_finish_SFENCE_VMA = - CAN_FIRE_RL_rl_finish_SFENCE_VMA ; - - // rule RL_rl_stage1_WFI - assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - - // rule RL_rl_WFI_resume - assign CAN_FIRE_RL_rl_WFI_resume = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd10 && - csr_regfile$wfi_resume ; - assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ; - - // rule RL_rl_reset_from_WFI - assign CAN_FIRE_RL_rl_reset_from_WFI = - rg_state == 4'd10 && f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_4 ; - - // rule RL_rl_stage1_trap - assign CAN_FIRE_RL_rl_stage1_trap = - rg_state == 4'd4 || - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd11 ; - assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ; - - // rule RL_rl_trap_fetch - assign CAN_FIRE_RL_rl_trap_fetch = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd5 ; - assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; - - // rule RL_rl_stage1_interrupt - assign CAN_FIRE_RL_rl_stage1_interrupt = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - rg_state == 4'd3 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1209 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd0 && - !stage3_rg_full ; - assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ; - - // rule RL_imem_rl_assert_fail - assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ; - assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = - gpr_regfile$RDY_server_reset_response_get && - near_mem$RDY_server_reset_response_get && - csr_regfile$RDY_server_reset_response_get && - stage1_f_reset_rsps$EMPTY_N && - stage2_f_reset_rsps_i_notEmpty__182_AND_stage3_ETC___d1191 && - rg_state == 4'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_pipe - assign CAN_FIRE_RL_rl_pipe = - (csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1223 || - !near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state_2_EQ_3_225_AND_stage3_rg_full_2_OR_NO_ETC___d1244 ; - assign WILL_FIRE_RL_rl_pipe = - CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = - gpr_regfile_RDY_server_reset_request_put__161__ETC___d1173 && - rg_state == 4'd0 ; - assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ; - - // rule RL_imem_rl_fetch_next_32b - assign CAN_FIRE_RL_imem_rl_fetch_next_32b = - near_mem$imem_valid && - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] == 2'b11 ; - assign WILL_FIRE_RL_imem_rl_fetch_next_32b = - CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_stage3_rl_reset - assign CAN_FIRE_RL_stage3_rl_reset = - stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ; - - // rule RL_stage2_rl_reset_end - assign CAN_FIRE_RL_stage2_rl_reset_end = - stage2_f_reset_rsps$FULL_N && stage2_rg_resetting ; - assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ; - - // rule RL_stage2_rl_reset_begin - assign CAN_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ; - - // rule RL_stage1_rl_reset - assign CAN_FIRE_RL_stage1_rl_reset = - stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_csr_regfile$mav_csr_write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 ; - assign MUX_gpr_regfile$write_rd_1__SEL_1 = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[69] ; - assign MUX_gpr_regfile$write_rd_1__SEL_3 = - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - assign MUX_imem_rg_f3$write_1__SEL_1 = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ; - assign MUX_imem_rg_f3$write_1__SEL_2 = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 ; - assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_imem_rg_pc$write_1__SEL_4 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_near_mem$imem_req_1__SEL_6 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_rg_cur_priv$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_mstatus_MXR$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_next_pc$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign MUX_rg_state$write_1__SEL_1 = - CAN_FIRE_RL_rl_reset_complete && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_2 = - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd2 ; - assign MUX_rg_state$write_1__SEL_3 = - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd3 ; - assign MUX_rg_state$write_1__SEL_4 = - CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ; - assign MUX_rg_state$write_1__SEL_6 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_rg_state$write_1__SEL_7 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_state$write_1__SEL_8 = - near_mem$RDY_server_fence_i_request_put && - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd5 ; - assign MUX_rg_state$write_1__SEL_9 = - near_mem$RDY_server_fence_request_put && - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd4 ; - assign MUX_rg_state$write_1__SEL_10 = - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd6 ; - assign MUX_rg_state$write_1__SEL_11 = - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd10 ; - assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 = - (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ? - csr_regfile$interrupt_pending[3:0] : - 4'd0 ; - always@(x_out_data_to_stage2_instr__h12203 or - csr_regfile$read_csr or - y__h19264 or - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1348) - begin - case (x_out_data_to_stage2_instr__h12203[14:12]) - 3'b010, 3'b110: - MUX_csr_regfile$mav_csr_write_2__VAL_2 = - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1348; - default: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - csr_regfile$read_csr[63:0] & y__h19264; - endcase - end - assign MUX_near_mem$imem_req_2__VAL_1 = - { soc_map$m_pc_reset_value[63:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_2 = - { x_out_next_pc__h12175[63:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[63:2], 2'b0 } ; - assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd3 : 4'd2 ; - assign MUX_rg_state$write_1__VAL_2 = - csr_regfile$access_permitted_1 ? 4'd6 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_3 = - csr_regfile$access_permitted_2 ? 4'd6 : 4'd4 ; - assign MUX_stage1_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1296 || - (csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1217 || - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1238) && - stage1_rg_full ; - assign MUX_stage2_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1291 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd2 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd0 ; - - // register cfg_logdelay - assign cfg_logdelay$D_IN = set_verbosity_logdelay ; - assign cfg_logdelay$EN = EN_set_verbosity ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register imem_rg_f3 - assign imem_rg_f3$D_IN = 3'b010 ; - assign imem_rg_f3$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_instr_15_0 - assign imem_rg_instr_15_0$D_IN = near_mem$imem_instr[31:16] ; - assign imem_rg_instr_15_0$EN = CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // register imem_rg_mstatus_MXR - assign imem_rg_mstatus_MXR$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_mstatus[19] : - rg_mstatus_MXR ; - assign imem_rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_pc - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h12175 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_pc$D_IN = soc_map$m_pc_reset_value; - MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h12175; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_pc$D_IN = x_out_next_pc__h12175; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc; - default: imem_rg_pc$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_pc$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - - // register imem_rg_priv - assign imem_rg_priv$D_IN = rg_cur_priv ; - assign imem_rg_priv$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_satp - assign imem_rg_satp$D_IN = csr_regfile$read_satp ; - assign imem_rg_satp$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_sstatus_SUM - assign imem_rg_sstatus_SUM$D_IN = - WILL_FIRE_RL_rl_trap_fetch && rg_sstatus_SUM ; - assign imem_rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_tval - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h12175 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or - rg_next_pc or - WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h14260) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_tval$D_IN = soc_map$m_pc_reset_value; - MUX_imem_rg_f3$write_1__SEL_2: - imem_rg_tval$D_IN = x_out_next_pc__h12175; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_tval$D_IN = x_out_next_pc__h12175; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - imem_rg_tval$D_IN = next_pc___1__h14260; - default: imem_rg_tval$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_tval$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // register rg_cur_priv - always@(MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or - csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_cur_priv$write_1__SEL_1: - rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[65:64]; - WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11; - default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_cur_priv$EN = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_mstatus[19] : - csr_regfile$csr_trap_actions[85] ; - assign rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_next_pc - always@(MUX_rg_next_pc$write_1__SEL_1 or - x_out_next_pc__h12175 or - MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h12175; - MUX_rg_cur_priv$write_1__SEL_1: - rg_next_pc$D_IN = csr_regfile$csr_trap_actions[193:130]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_next_pc$D_IN = csr_regfile$csr_ret_actions[129:66]; - default: rg_next_pc$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_next_pc$EN = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET ; - - // register rg_run_on_reset - assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ; - assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = - WILL_FIRE_RL_rl_stage1_interrupt && - csr_regfile$csr_trap_actions[84] ; - assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_7 ; - - // register rg_start_CPI_cycles - assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ; - assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_start_CPI_instrs - assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ; - assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_state - always@(WILL_FIRE_RL_rl_reset_complete or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_stage1_CSRR_W or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or - MUX_rg_state$write_1__VAL_3 or - WILL_FIRE_RL_rl_reset_from_WFI or - WILL_FIRE_RL_rl_reset_start or - MUX_rg_state$write_1__SEL_6 or - MUX_rg_state$write_1__SEL_7 or - WILL_FIRE_RL_rl_stage1_FENCE_I or - WILL_FIRE_RL_rl_stage1_FENCE or - WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_reset_complete: - rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_stage1_CSRR_W: - rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: - rg_state$D_IN = MUX_rg_state$write_1__VAL_3; - WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1; - MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd5; - WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd7; - WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd8; - WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd10; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_complete || - WILL_FIRE_RL_rl_stage1_CSRR_W || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C || - WILL_FIRE_RL_rl_reset_from_WFI || - WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_WFI ; - - // register stage1_rg_full - always@(WILL_FIRE_RL_stage1_rl_reset or - WILL_FIRE_RL_rl_pipe or - MUX_stage1_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or - WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_trap_fetch or - WILL_FIRE_RL_rl_stage1_trap or - WILL_FIRE_RL_rl_WFI_resume or - WILL_FIRE_RL_rl_finish_SFENCE_VMA or - WILL_FIRE_RL_rl_finish_FENCE or - WILL_FIRE_RL_rl_finish_FENCE_I or - WILL_FIRE_RL_rl_stage1_xRET or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_interrupt: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_trap_fetch: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_trap: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I: - stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_xRET: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0; - default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage1_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage1_rl_reset || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register stage2_rg_full - always@(stage2_f_reset_reqs$EMPTY_N or - WILL_FIRE_RL_rl_pipe or - MUX_stage2_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - stage2_f_reset_reqs$EMPTY_N: stage2_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage2_nonpipe: - stage2_rg_full$D_IN = 1'd0; - default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage2_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage2_nonpipe || - stage2_f_reset_reqs$EMPTY_N ; - - // register stage2_rg_resetting - assign stage2_rg_resetting$D_IN = stage2_f_reset_reqs$EMPTY_N ; - assign stage2_rg_resetting$EN = - WILL_FIRE_RL_stage2_rl_reset_end || stage2_f_reset_reqs$EMPTY_N ; - - // register stage2_rg_stage2 - assign stage2_rg_stage2$D_IN = - { rg_cur_priv, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916, - x_out_data_to_stage2_rd__h12205, - x_out_data_to_stage2_addr__h12206, - x_out_data_to_stage2_val1__h12207, - x_out_data_to_stage2_val2__h12208 } ; - assign stage2_rg_stage2$EN = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 ; - - // register stage3_rg_full - always@(WILL_FIRE_RL_stage3_rl_reset or - WILL_FIRE_RL_rl_pipe or - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 or - MUX_imem_rg_f3$write_1__SEL_1) - case (1'b1) - WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage3_rg_full$D_IN = - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2; - MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0; - default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage3_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_stage3_rl_reset ; - - // register stage3_rg_stage3 - assign stage3_rg_stage3$D_IN = - { stage2_rg_stage2[295:200], - stage2_rg_stage2[297:296], - stage2_rg_stage2[199:197] == 3'd0 || - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145, - x_out_data_to_stage3_rd__h5648, - x_out_data_to_stage3_rd_val__h5649 } ; - assign stage3_rg_stage3$EN = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd2 ; - - // submodule csr_regfile - assign csr_regfile$access_permitted_1_csr_addr = - x_out_data_to_stage2_instr__h12203[31:20] ; - assign csr_regfile$access_permitted_1_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ; - assign csr_regfile$access_permitted_2_csr_addr = - x_out_data_to_stage2_instr__h12203[31:20] ; - assign csr_regfile$access_permitted_2_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_2_read_not_write = - rs1_val__h18963 == 64'd0 ; - assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ; - assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ; - always@(IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833) - begin - case (IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833) - 4'd7: csr_regfile$csr_ret_actions_from_priv = 2'b11; - 4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b01; - default: csr_regfile$csr_ret_actions_from_priv = 2'b0; - endcase - end - always@(WILL_FIRE_RL_rl_stage1_interrupt or - MUX_csr_regfile$csr_trap_actions_5__VAL_1 or - WILL_FIRE_RL_rl_stage1_trap or - x_out_trap_info_exc_code__h14097 or - WILL_FIRE_RL_rl_stage2_nonpipe or near_mem$dmem_exc_code) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_exc_code = - MUX_csr_regfile$csr_trap_actions_5__VAL_1; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h14097; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_exc_code = near_mem$dmem_exc_code; - default: csr_regfile$csr_trap_actions_exc_code = - 4'b1010 /* unspecified value */ ; - endcase - end - assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ; - assign csr_regfile$csr_trap_actions_interrupt = - WILL_FIRE_RL_rl_stage1_interrupt && !csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_nmi = - WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_pc = - WILL_FIRE_RL_rl_stage2_nonpipe ? - stage2_rg_stage2[295:232] : - imem_rg_pc ; - always@(WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_stage1_trap or - value__h14148 or WILL_FIRE_RL_rl_stage2_nonpipe or stage2_rg_stage2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_xtval = 64'd0; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_xtval = value__h14148; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_xtval = stage2_rg_stage2[191:128]; - default: csr_regfile$csr_trap_actions_xtval = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ; - assign csr_regfile$m_external_interrupt_req_set_not_clear = - m_external_interrupt_req_set_not_clear ; - assign csr_regfile$mav_csr_write_csr_addr = - x_out_data_to_stage2_instr__h12203[31:20] ; - assign csr_regfile$mav_csr_write_word = - MUX_csr_regfile$mav_csr_write_1__SEL_1 ? - rs1_val__h18473 : - MUX_csr_regfile$mav_csr_write_2__VAL_2 ; - assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ; - assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign csr_regfile$read_csr_csr_addr = - x_out_data_to_stage2_instr__h12203[31:20] ; - assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ; - assign csr_regfile$s_external_interrupt_req_set_not_clear = - s_external_interrupt_req_set_not_clear ; - assign csr_regfile$software_interrupt_req_set_not_clear = - software_interrupt_req_set_not_clear ; - assign csr_regfile$timer_interrupt_req_set_not_clear = - timer_interrupt_req_set_not_clear ; - assign csr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign csr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign csr_regfile$EN_mav_read_csr = 1'b0 ; - assign csr_regfile$EN_mav_csr_write = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h12203[19:15] != 5'd0 ; - assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_1 ; - assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ; - assign csr_regfile$EN_csr_minstret_incr = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd2 || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_stage1_WFI || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign csr_regfile$EN_debug = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = hart0_server_reset_request_put ; - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = - gpr_regfile_RDY_server_reset_request_put__161__ETC___d1173 && - rg_state == 4'd0 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = rg_run_on_reset ; - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule gpr_regfile - assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign gpr_regfile$read_rs1_rs1 = _theResult____h4283[19:15] ; - assign gpr_regfile$read_rs2_rs2 = _theResult____h4283[24:20] ; - assign gpr_regfile$write_rd_rd = - MUX_gpr_regfile$write_rd_1__SEL_1 ? - stage3_rg_stage3[68:64] : - x_out_data_to_stage2_instr__h12203[11:7] ; - assign gpr_regfile$write_rd_rd_val = - (MUX_csr_regfile$mav_csr_write_1__SEL_1 || - MUX_gpr_regfile$write_rd_1__SEL_3) ? - csr_regfile$read_csr[63:0] : - stage3_rg_stage3[63:0] ; - assign gpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign gpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign gpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[69] || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - - // submodule near_mem - assign near_mem$dmem_master_arready = dmem_master_arready ; - assign near_mem$dmem_master_awready = dmem_master_awready ; - assign near_mem$dmem_master_bid = dmem_master_bid ; - assign near_mem$dmem_master_bresp = dmem_master_bresp ; - assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; - assign near_mem$dmem_master_rdata = dmem_master_rdata ; - assign near_mem$dmem_master_rid = dmem_master_rid ; - assign near_mem$dmem_master_rlast = dmem_master_rlast ; - assign near_mem$dmem_master_rresp = dmem_master_rresp ; - assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; - assign near_mem$dmem_master_wready = dmem_master_wready ; - assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h12206 ; - assign near_mem$dmem_req_amo_funct7 = - x_out_data_to_stage2_val1__h12207[6:0] ; - assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h12203[14:12] ; - assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ; - always@(IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916) - begin - case (IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916) - 3'd1: near_mem$dmem_req_op = 2'd0; - 3'd2: near_mem$dmem_req_op = 2'd1; - default: near_mem$dmem_req_op = 2'd2; - endcase - end - assign near_mem$dmem_req_priv = - csr_regfile$read_mstatus[17] ? - csr_regfile$read_mstatus[12:11] : - rg_cur_priv ; - assign near_mem$dmem_req_satp = csr_regfile$read_satp ; - assign near_mem$dmem_req_sstatus_SUM = 1'd0 ; - assign near_mem$dmem_req_store_value = x_out_data_to_stage2_val2__h12208 ; - assign near_mem$imem_master_arready = imem_master_arready ; - assign near_mem$imem_master_awready = imem_master_awready ; - assign near_mem$imem_master_bid = imem_master_bid ; - assign near_mem$imem_master_bresp = imem_master_bresp ; - assign near_mem$imem_master_bvalid = imem_master_bvalid ; - assign near_mem$imem_master_rdata = imem_master_rdata ; - assign near_mem$imem_master_rid = imem_master_rid ; - assign near_mem$imem_master_rlast = imem_master_rlast ; - assign near_mem$imem_master_rresp = imem_master_rresp ; - assign near_mem$imem_master_rvalid = imem_master_rvalid ; - assign near_mem$imem_master_wready = imem_master_wready ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_near_mem$imem_req_2__VAL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - MUX_near_mem$imem_req_2__VAL_2 or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - next_pc___1__h14260 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_trap_fetch or - MUX_near_mem$imem_req_2__VAL_5 or MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1; - MUX_imem_rg_f3$write_1__SEL_2: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_addr = next_pc___1__h14260; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - default: near_mem$imem_req_addr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_f3 = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_mstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_mstatus_MXR or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_mstatus_MXR) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_mstatus_MXR = imem_rg_mstatus_MXR; - default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_priv = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - MUX_near_mem$imem_req_1__SEL_6) ? - rg_cur_priv : - imem_rg_priv ; - assign near_mem$imem_req_satp = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? - imem_rg_satp : - csr_regfile$read_satp ; - always@(WILL_FIRE_RL_rl_trap_fetch or - rg_sstatus_SUM or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - imem_rg_sstatus_SUM or - MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_sstatus_SUM = imem_rg_sstatus_SUM; - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_sstatus_SUM = 1'd0; - default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$server_fence_request_put = - 8'b10101010 /* unspecified value */ ; - assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ; - assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ; - assign near_mem$EN_imem_req = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_imem_rl_fetch_next_32b || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_dmem_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 && - (IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == - 3'd1 || - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == - 3'd2 || - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == - 3'd4) ; - assign near_mem$EN_server_fence_i_request_put = - MUX_rg_state$write_1__SEL_8 ; - assign near_mem$EN_server_fence_i_response_get = - CAN_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_9 ; - assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ; - assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_10 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule stage1_f_reset_reqs - assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage1_f_reset_rsps - assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage1_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_f_reset_reqs - assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage2_f_reset_reqs$DEQ = stage2_f_reset_reqs$EMPTY_N ; - assign stage2_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage2_f_reset_rsps - assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage2_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_mbox - assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h12203[14:12] ; - assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4283[3] ; - assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h12207 ; - assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h12208 ; - assign stage2_mbox$set_verbosity_verbosity = 4'h0 ; - assign stage2_mbox$EN_set_verbosity = 1'b0 ; - assign stage2_mbox$EN_req_reset = 1'b0 ; - assign stage2_mbox$EN_rsp_reset = 1'b0 ; - assign stage2_mbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == - 3'd3 ; - - // submodule stage3_f_reset_reqs - assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage3_f_reset_rsps - assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage3_f_reset_rsps$CLR = 1'b0 ; - - // remaining internal signals - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1064 = - ((_theResult____h4283[6:0] == 7'b0010011 || - _theResult____h4283[6:0] == 7'b0110011) && - (_theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b101)) ? - alu_outputs___1_val1__h12492 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1065 = - ((_theResult____h4283[6:0] == 7'b0110011 || - _theResult____h4283[6:0] == 7'b0111011) && - _theResult____h4283[31:25] == 7'b0000001) ? - rs1_val_bypassed__h4291 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1064 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1209 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558 = - rs1_val_bypassed__h4291 == rs2_val__h12304 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560 = - (rs1_val_bypassed__h4291 ^ 64'h8000000000000000) < - (rs2_val__h12304 ^ 64'h8000000000000000) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562 = - rs1_val_bypassed__h4291 < rs2_val__h12304 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 = - (_theResult____h4283[6:0] == 7'b1100011) ? - _theResult____h4283[14:12] != 3'b0 && - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b100 && - _theResult____h4283[14:12] != 3'b101 && - _theResult____h4283[14:12] != 3'b110 && - _theResult____h4283[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 : - _theResult____h4283[6:0] == 7'b1101111 || - _theResult____h4283[6:0] == 7'b1100111 || - (_theResult____h4283[6:0] != 7'b0110011 || - _theResult____h4283[31:25] != 7'b0000001) && - (_theResult____h4283[6:0] != 7'b0111011 || - _theResult____h4283[31:25] != 7'b0000001) && - (_theResult____h4283[6:0] != 7'b0010011 && - _theResult____h4283[6:0] != 7'b0110011 || - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b101) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700 = - (_theResult____h4283[6:0] == 7'b1100011) ? - _theResult____h4283[14:12] != 3'b0 && - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b100 && - _theResult____h4283[14:12] != 3'b101 && - _theResult____h4283[14:12] != 3'b110 && - _theResult____h4283[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 : - _theResult____h4283[6:0] != 7'b1101111 && - _theResult____h4283[6:0] != 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 = - (_theResult____h4283[6:0] == 7'b1100011) ? - (_theResult____h4283[14:12] == 3'b0 || - _theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b100 || - _theResult____h4283[14:12] == 3'b101 || - _theResult____h4283[14:12] == 3'b110 || - _theResult____h4283[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 : - _theResult____h4283[6:0] != 7'b1101111 && - _theResult____h4283[6:0] != 7'b1100111 && - (IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d717 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767 = - (_theResult____h4283[6:0] == 7'b1100011) ? - (_theResult____h4283[14:12] == 3'b0 || - _theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b100 || - _theResult____h4283[14:12] == 3'b101 || - _theResult____h4283[14:12] == 3'b110 || - _theResult____h4283[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 : - _theResult____h4283[6:0] == 7'b1101111 || - _theResult____h4283[6:0] == 7'b1100111 ; - assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d774 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d605 ? - 4'd11 : - 4'd0 ; - assign IF_NOT_near_mem_dmem_valid__13_32_OR_NOT_near__ETC___d179 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - IF_stage2_rg_stage2_2_BITS_196_TO_192_52_EQ_0__ETC___d178 : - 2'd0 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d717 = - _theResult____h4283[6:0] == 7'b0110011 && - _theResult____h4283[31:25] == 7'b0000001 || - _theResult____h4283[6:0] == 7'b0111011 && - _theResult____h4283[31:25] == 7'b0000001 || - (_theResult____h4283[6:0] == 7'b0010011 || - _theResult____h4283[6:0] == 7'b0110011) && - (_theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b101) ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d724 = - _theResult____h4283[14:12] == 3'b0 && - (_theResult____h4283[6:0] != 7'b0110011 || - !_theResult____h4283[30]) || - _theResult____h4283[14:12] == 3'b0 && - _theResult____h4283[6:0] == 7'b0110011 && - _theResult____h4283[30] || - _theResult____h4283[14:12] == 3'b010 || - _theResult____h4283[14:12] == 3'b011 || - _theResult____h4283[14:12] == 3'b100 || - _theResult____h4283[14:12] == 3'b110 || - _theResult____h4283[14:12] == 3'b111 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d962 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d208 ? - next_pc___1__h14260 : - next_pc__h14258 ; - assign IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d1398 = - imem_rg_pc == csr_regfile$csr_trap_actions[193:130] ; - assign IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 = - near_mem$imem_exc ? - 4'd11 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d831 ; - assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1348 = - csr_regfile$read_csr[63:0] | rs1_val__h18963 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d466 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b0 && - instr__h4281[15:13] == 3'b011) ? - instr__h11795 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b0 && - instr__h4281[15:13] == 3'b111) ? - instr__h11946 : - 32'h0) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d467 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:13] == 3'b111) ? - instr__h11596 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d466 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d469 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:12] == 4'b1001 && - instr__h4281[11:7] == 5'd0 && - instr__h4281[6:2] == 5'd0) ? - instr__h11347 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[11:7] != 5'd0 && - instr__h4281[15:13] == 3'b011) ? - instr__h11443 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d467) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d471 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100111 && - instr__h4281[6:5] == 2'b01) ? - instr__h11051 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100111 && - instr__h4281[6:5] == 2'b0) ? - instr__h11189 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d469) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d473 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100011 && - instr__h4281[6:5] == 2'b01) ? - instr__h10777 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100011 && - instr__h4281[6:5] == 2'b0) ? - instr__h10913 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d471) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d475 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100011 && - instr__h4281[6:5] == 2'b11) ? - instr__h10505 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100011 && - instr__h4281[6:5] == 2'b10) ? - instr__h10641 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d473) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d476 = - (csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d308 && - instr__h4281[6:2] != 5'd0) ? - instr__h10410 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d475 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d477 = - (csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d302 && - instr__h4281[6:2] != 5'd0) ? - instr__h10291 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d476 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d479 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b100 && - instr__h4281[11:10] == 2'b01 && - imm6__h8404 != 6'd0) ? - instr__h9996 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b100 && - instr__h4281[11:10] == 2'b10) ? - instr__h10113 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d477) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d480 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b100 && - instr__h4281[11:10] == 2'b0 && - imm6__h8404 != 6'd0) ? - instr__h9807 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d479 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d481 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:13] == 3'b0 && - instr__h4281[11:7] != 5'd0 && - imm6__h8404 != 6'd0) ? - instr__h9618 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d480 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d483 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b011 && - instr__h4281[11:7] == 5'd2 && - nzimm10__h9073 != 10'd0) ? - instr__h9277 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b0 && - instr__h4281[15:13] == 3'b0 && - nzimm10__h9288 != 10'd0) ? - instr__h9449 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d481) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d485 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b0 && - instr__h4281[11:7] != 5'd0 && - imm6__h8404 != 6'd0 || - csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b0 && - instr__h4281[11:7] == 5'd0 && - imm6__h8404 == 6'd0) ? - instr__h8795 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b001 && - instr__h4281[11:7] != 5'd0) ? - instr__h9022 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d483) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d486 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b011 && - instr__h4281[11:7] != 5'd0 && - instr__h4281[11:7] != 5'd2 && - imm6__h8404 != 6'd0) ? - instr__h8666 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d485 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d488 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b111) ? - instr__h8144 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b010 && - instr__h4281[11:7] != 5'd0) ? - instr__h8482 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d486) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d489 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b110) ? - instr__h7827 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d488 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d490 = - (csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d308 && - instr__h4281[6:2] == 5'd0) ? - instr__h7762 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d489 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d491 = - (csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d302 && - instr__h4281[6:2] == 5'd0) ? - instr__h7646 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d490 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d492 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b101) ? - instr__h7192 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d491 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d493 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b0 && - instr__h4281[15:13] == 3'b110) ? - instr__h6963 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d492 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d494 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b0 && - instr__h4281[15:13] == 3'b010) ? - instr__h6768 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d493 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d495 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:13] == 3'b110) ? - instr__h6576 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d494 ; - assign IF_near_mem_dmem_valid__13_THEN_IF_near_mem_dm_ETC___d116 = - near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ; - assign IF_rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_E_ETC___d809 = - ((rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) && - _theResult____h4283[31:20] == 12'b000100000010) ? - 4'd8 : - (rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_EQ_0_ETC___d807 ? - 4'd10 : - 4'd11) ; - assign IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q1 : - 2'd0 ; - assign IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2 : - 2'd0 ; - assign IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499 = - x_out_bypass_rd__h5999 == _theResult____h4283[19:15] ; - assign IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501 = - x_out_bypass_rd__h5999 == _theResult____h4283[24:20] ; - assign IF_stage2_rg_stage2_2_BITS_196_TO_192_52_EQ_0__ETC___d178 = - (stage2_rg_stage2[196:192] == 5'd0) ? - 2'd0 : - ((near_mem$dmem_valid && !near_mem$dmem_exc) ? 2'd2 : 2'd1) ; - assign IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119 = - stage2_mbox$valid ? 2'd2 : 2'd1 ; - assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d605 = - (_theResult____h4283[14:12] != 3'b0 || - _theResult____h4283[6:0] == 7'b0110011 && - _theResult____h4283[30]) && - (_theResult____h4283[14:12] != 3'b0 || - _theResult____h4283[6:0] != 7'b0110011 || - !_theResult____h4283[30]) && - _theResult____h4283[14:12] != 3'b010 && - _theResult____h4283[14:12] != 3'b011 && - _theResult____h4283[14:12] != 3'b100 && - _theResult____h4283[14:12] != 3'b110 && - _theResult____h4283[14:12] != 3'b111 ; - assign NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 = - cur_verbosity__h2988 > 4'd1 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - (!stage1_rg_full || - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1238) && - (!stage1_rg_full || - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1230) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1259 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1259 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd2 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd0) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1259 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd2 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd0) && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770 || - !stage1_rg_full ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1291 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__20_OR_IF_IF_NOT_n_ETC___d1289) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1293 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__20_OR_IF_IF_NOT_n_ETC___d1289) && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd2 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd0) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1296 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1293 && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770 || - !stage1_rg_full) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1310 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) ; - assign NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d899 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd0 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd1 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd2 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd3 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd4 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd5 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd6 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd7 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd8 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd9 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd10 ; - assign NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d940 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 != - 3'd0 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 != - 3'd1 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 != - 3'd2 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 != - 3'd3 ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d208 = - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] != 2'b11) ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d213 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d208 && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] == 2'b11) && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] == 2'b11) ; - assign NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1219 = - !near_mem$imem_valid || - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == - 2'd1 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501) ; - assign NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1230 = - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504 || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) ; - assign NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1238 = - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700 ; - assign NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504 = - !near_mem$imem_valid || - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d213 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == - 2'd1 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501) ; - assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d971 = - { {52{theResult__283_BITS_31_TO_20__q19[11]}}, - theResult__283_BITS_31_TO_20__q19 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292 = - { {9{offset__h7139[11]}}, offset__h7139 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317 = - { {4{offset__h7771[8]}}, offset__h7771 } ; - assign _0_OR_0_OR_near_mem_imem_exc__20_OR_IF_IF_NOT_n_ETC___d1289 = - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700 ; - assign _theResult_____1_fst__h13375 = - (_theResult____h4283[14:12] == 3'b0 && - _theResult____h4283[6:0] == 7'b0110011 && - _theResult____h4283[30]) ? - rd_val___1__h13371 : - _theResult_____1_fst__h13382 ; - assign _theResult_____1_fst__h13410 = - rs1_val_bypassed__h4291 & _theResult___snd__h14727 ; - assign _theResult____h23527 = - (delta_CPI_instrs__h23526 == 64'd0) ? - delta_CPI_instrs___1__h23562 : - delta_CPI_instrs__h23526 ; - assign _theResult____h4283 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d208 ? - instr___1__h6160 : - instr__h4281 ; - assign _theResult___fst__h13487 = - (_theResult____h4283[14:12] == 3'b001 && - !_theResult____h4283[25]) ? - rd_val___1__h14787 : - _theResult___fst__h13494 ; - assign _theResult___fst__h13494 = - _theResult____h4283[30] ? - rd_val___1__h14870 : - rd_val___1__h14841 ; - assign _theResult___fst__h13601 = - { {32{rs1_val_bypassed291_BITS_31_TO_0_SRL_rs2_val23_ETC__q9[31]}}, - rs1_val_bypassed291_BITS_31_TO_0_SRL_rs2_val23_ETC__q9 } ; - assign _theResult___fst__h6331 = - (near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11) ? - instr_out___1__h6333 : - _theResult___fst__h6359 ; - assign _theResult___fst__h6359 = - (near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11) ? - instr_out___1__h6361 : - near_mem$imem_instr ; - assign _theResult___snd__h14727 = - (_theResult____h4283[6:0] == 7'b0010011) ? - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d971 : - rs2_val__h12304 ; - assign alu_outputs___1_addr2629_BITS_31_TO_0__q20 = - alu_outputs___1_addr__h12629[31:0] ; - assign alu_outputs___1_addr__h12330 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 ? - branch_target__h12308 : - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d962 ; - assign alu_outputs___1_addr__h12351 = - imem_rg_pc + - { {43{theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q4[20]}}, - theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q4 } ; - assign alu_outputs___1_addr__h12377 = - { alu_outputs___1_addr__h12629[63:1], 1'd0 } ; - assign alu_outputs___1_addr__h12629 = - rs1_val_bypassed__h4291 + - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d971 ; - assign alu_outputs___1_addr__h12650 = - rs1_val_bypassed__h4291 + - { {52{theResult__283_BITS_31_TO_25_CONCAT_theResult__ETC__q7[11]}}, - theResult__283_BITS_31_TO_25_CONCAT_theResult__ETC__q7 } ; - assign alu_outputs___1_exc_code__h12886 = - (_theResult____h4283[14:12] == 3'b0) ? - ((_theResult____h4283[11:7] == 5'd0 && - _theResult____h4283[19:15] == 5'd0) ? - CASE_theResult__283_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 : - 4'd2) : - 4'd2 ; - assign alu_outputs___1_val1__h12492 = - (_theResult____h4283[14:12] == 3'b001) ? - rd_val__h14623 : - (_theResult____h4283[30] ? rd_val__h14697 : rd_val__h14675) ; - assign alu_outputs___1_val1__h12530 = - (_theResult____h4283[14:12] == 3'b0 && - (_theResult____h4283[6:0] != 7'b0110011 || - !_theResult____h4283[30])) ? - rd_val___1__h13363 : - _theResult_____1_fst__h13375 ; - assign alu_outputs___1_val1__h12553 = - (_theResult____h4283[14:12] == 3'b0) ? - rd_val___1__h14756 : - _theResult___fst__h13487 ; - assign alu_outputs___1_val1__h12592 = - { {32{v32__h12581[31]}}, v32__h12581 } ; - assign alu_outputs___1_val1__h12608 = - imem_rg_pc + alu_outputs___1_val1__h12592 ; - assign alu_outputs___1_val1__h12890 = - _theResult____h4283[14] ? - { 59'd0, _theResult____h4283[19:15] } : - rs1_val_bypassed__h4291 ; - assign alu_outputs___1_val1__h12911 = - { 57'd0, _theResult____h4283[31:25] } ; - assign branch_target__h12308 = - imem_rg_pc + - { {51{theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q3[12]}}, - theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q3 } ; - assign cpi__h23529 = x__h23528 / 64'd10 ; - assign cpifrac__h23530 = x__h23528 % 64'd10 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1212 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1208 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1209 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1217 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd2 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd0 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1223 = - csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1212 || - (csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1217 || - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1219 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - stage1_rg_full ; - assign csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1401 = - delta_CPI_cycles__h23525 * 64'd10 ; - assign csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d302 = - csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:12] == 4'b1000 && - instr__h4281[11:7] != 5'd0 ; - assign csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d308 = - csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:12] == 4'b1001 && - instr__h4281[11:7] != 5'd0 ; - assign cur_verbosity__h2988 = - (csr_regfile$read_csr_minstret < cfg_logdelay) ? - 4'd0 : - cfg_verbosity ; - assign data_to_stage2_addr__h12198 = x_out_data_to_stage2_addr__h12206 ; - assign delta_CPI_cycles__h23525 = - csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ; - assign delta_CPI_instrs___1__h23562 = delta_CPI_instrs__h23526 + 64'd1 ; - assign delta_CPI_instrs__h23526 = - csr_regfile$read_csr_minstret - rg_start_CPI_instrs ; - assign fall_through_pc__h12162 = - imem_rg_pc + - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d511 ? - 64'd4 : - 64'd2) ; - assign funct10__h12562 = - { _theResult____h4283[31:25], _theResult____h4283[14:12] } ; - assign gpr_regfile_RDY_server_reset_request_put__161__ETC___d1173 = - gpr_regfile$RDY_server_reset_request_put && - near_mem$RDY_server_reset_request_put && - csr_regfile$RDY_server_reset_request_put && - f_reset_reqs$EMPTY_N && - stage1_f_reset_reqs$FULL_N && - stage2_f_reset_reqs$FULL_N && - stage3_f_reset_reqs$FULL_N ; - assign imm12__h11444 = { 3'd0, offset__h11358 } ; - assign imm12__h11796 = { 4'd0, offset__h11730 } ; - assign imm12__h6432 = { 4'd0, offset__h6202 } ; - assign imm12__h6769 = { 5'd0, offset__h6711 } ; - assign imm12__h8406 = { {6{imm6__h8404[5]}}, imm6__h8404 } ; - assign imm12__h9075 = { {2{nzimm10__h9073[9]}}, nzimm10__h9073 } ; - assign imm12__h9290 = { 2'd0, nzimm10__h9288 } ; - assign imm12__h9486 = { 6'b0, imm6__h8404 } ; - assign imm12__h9823 = { 6'b010000, imm6__h8404 } ; - assign imm20__h8534 = { {14{imm6__h8404[5]}}, imm6__h8404 } ; - assign imm6__h8404 = { instr__h4281[12], instr__h4281[6:2] } ; - assign instr___1__h6160 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[11:7] != 5'd0 && - instr__h4281[15:13] == 3'b010) ? - instr__h6431 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d495 ; - assign instr__h10113 = - { imm12__h8406, rs1__h6770, 3'b111, rs1__h6770, 7'b0010011 } ; - assign instr__h10291 = - { 7'b0, - instr__h4281[6:2], - 8'd0, - instr__h4281[11:7], - 7'b0110011 } ; - assign instr__h10410 = - { 7'b0, - instr__h4281[6:2], - instr__h4281[11:7], - 3'b0, - instr__h4281[11:7], - 7'b0110011 } ; - assign instr__h10505 = - { 7'b0, rd__h6771, rs1__h6770, 3'b111, rs1__h6770, 7'b0110011 } ; - assign instr__h10641 = - { 7'b0, rd__h6771, rs1__h6770, 3'b110, rs1__h6770, 7'b0110011 } ; - assign instr__h10777 = - { 7'b0, rd__h6771, rs1__h6770, 3'b100, rs1__h6770, 7'b0110011 } ; - assign instr__h10913 = - { 7'b0100000, - rd__h6771, - rs1__h6770, - 3'b0, - rs1__h6770, - 7'b0110011 } ; - assign instr__h11051 = - { 7'b0, rd__h6771, rs1__h6770, 3'b0, rs1__h6770, 7'b0111011 } ; - assign instr__h11189 = - { 7'b0100000, - rd__h6771, - rs1__h6770, - 3'b0, - rs1__h6770, - 7'b0111011 } ; - assign instr__h11347 = - { 12'b000000000001, - instr__h4281[11:7], - 3'b0, - instr__h4281[11:7], - 7'b1110011 } ; - assign instr__h11443 = - { imm12__h11444, 8'd19, instr__h4281[11:7], 7'b0000011 } ; - assign instr__h11596 = - { 3'd0, - instr__h4281[9:7], - instr__h4281[12], - instr__h4281[6:2], - 8'd19, - offset_BITS_4_TO_0___h12071, - 7'b0100011 } ; - assign instr__h11795 = - { imm12__h11796, rs1__h6770, 3'b011, rd__h6771, 7'b0000011 } ; - assign instr__h11946 = - { 4'd0, - instr__h4281[6:5], - instr__h4281[12], - rd__h6771, - rs1__h6770, - 3'b011, - offset_BITS_4_TO_0___h12071, - 7'b0100011 } ; - assign instr__h4281 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 ? - instr_out___1__h6301 : - _theResult___fst__h6331 ; - assign instr__h6431 = - { imm12__h6432, 8'd18, instr__h4281[11:7], 7'b0000011 } ; - assign instr__h6576 = - { 4'd0, - instr__h4281[8:7], - instr__h4281[12], - instr__h4281[6:2], - 8'd18, - offset_BITS_4_TO_0___h6700, - 7'b0100011 } ; - assign instr__h6768 = - { imm12__h6769, rs1__h6770, 3'b010, rd__h6771, 7'b0000011 } ; - assign instr__h6963 = - { 5'd0, - instr__h4281[5], - instr__h4281[12], - rd__h6771, - rs1__h6770, - 3'b010, - offset_BITS_4_TO_0___h7131, - 7'b0100011 } ; - assign instr__h7192 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292[19:12], - 12'd111 } ; - assign instr__h7646 = { 12'd0, instr__h4281[11:7], 15'd103 } ; - assign instr__h7762 = { 12'd0, instr__h4281[11:7], 15'd231 } ; - assign instr__h7827 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[10:5], - 5'd0, - rs1__h6770, - 3'b0, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[11], - 7'b1100011 } ; - assign instr__h8144 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[10:5], - 5'd0, - rs1__h6770, - 3'b001, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[11], - 7'b1100011 } ; - assign instr__h8482 = - { imm12__h8406, 8'd0, instr__h4281[11:7], 7'b0010011 } ; - assign instr__h8666 = { imm20__h8534, instr__h4281[11:7], 7'b0110111 } ; - assign instr__h8795 = - { imm12__h8406, - instr__h4281[11:7], - 3'b0, - instr__h4281[11:7], - 7'b0010011 } ; - assign instr__h9022 = - { imm12__h8406, - instr__h4281[11:7], - 3'b0, - instr__h4281[11:7], - 7'b0011011 } ; - assign instr__h9277 = - { imm12__h9075, - instr__h4281[11:7], - 3'b0, - instr__h4281[11:7], - 7'b0010011 } ; - assign instr__h9449 = { imm12__h9290, 8'd16, rd__h6771, 7'b0010011 } ; - assign instr__h9618 = - { imm12__h9486, - instr__h4281[11:7], - 3'b001, - instr__h4281[11:7], - 7'b0010011 } ; - assign instr__h9807 = - { imm12__h9486, rs1__h6770, 3'b101, rs1__h6770, 7'b0010011 } ; - assign instr__h9996 = - { imm12__h9823, rs1__h6770, 3'b101, rs1__h6770, 7'b0010011 } ; - assign instr_out___1__h6301 = - { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ; - assign instr_out___1__h6333 = { 16'b0, near_mem$imem_instr[15:0] } ; - assign instr_out___1__h6361 = { 16'b0, near_mem$imem_instr[31:16] } ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1076 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd0 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1079 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd1 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1082 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd2 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1085 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd3 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1088 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd4 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1091 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd5 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1094 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd6 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1097 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd7 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1100 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd8 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1103 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd9 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1106 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd10 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1109 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd0 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd1 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd2 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd3 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd4 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd5 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd6 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd7 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd8 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd9 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd10 ; - assign near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 = - near_mem$imem_pc[63:2] == imem_rg_pc[63:2] ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d511 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] == 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d513 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d511 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 = - near_mem$imem_pc == next_pc___1__h14260 ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1208 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 != - 2'd1 || - !IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499 && - !IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d513 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 != - 2'd1 || - !IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499 && - !IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) ; - assign next_pc___1__h14260 = imem_rg_pc + 64'd2 ; - assign next_pc__h14258 = imem_rg_pc + 64'd4 ; - assign nzimm10__h9073 = - { instr__h4281[12], - instr__h4281[4:3], - instr__h4281[5], - instr__h4281[2], - instr__h4281[6], - 4'b0 } ; - assign nzimm10__h9288 = - { instr__h4281[10:7], - instr__h4281[12:11], - instr__h4281[5], - instr__h4281[6], - 2'b0 } ; - assign offset_BITS_4_TO_0___h12071 = { instr__h4281[11:10], 3'b0 } ; - assign offset_BITS_4_TO_0___h6700 = { instr__h4281[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h7131 = - { instr__h4281[11:10], instr__h4281[6], 2'b0 } ; - assign offset__h11358 = - { instr__h4281[4:2], - instr__h4281[12], - instr__h4281[6:5], - 3'b0 } ; - assign offset__h11730 = { instr__h4281[6:5], instr__h4281[12:10], 3'b0 } ; - assign offset__h6202 = - { instr__h4281[3:2], - instr__h4281[12], - instr__h4281[6:4], - 2'b0 } ; - assign offset__h6711 = - { instr__h4281[5], instr__h4281[12:10], instr__h4281[6], 2'b0 } ; - assign offset__h7139 = - { instr__h4281[12], - instr__h4281[8], - instr__h4281[10:9], - instr__h4281[6], - instr__h4281[7], - instr__h4281[2], - instr__h4281[11], - instr__h4281[5:3], - 1'b0 } ; - assign offset__h7771 = - { instr__h4281[12], - instr__h4281[6:5], - instr__h4281[2], - instr__h4281[11:10], - instr__h4281[4:3], - 1'b0 } ; - assign output_stage2___1_bypass_rd_val__h5988 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - ((stage2_rg_stage2[196:192] == 5'd0) ? - stage2_rg_stage2[127:64] : - near_mem$dmem_word64) : - stage2_rg_stage2[127:64] ; - assign rd__h6771 = { 2'b01, instr__h4281[4:2] } ; - assign rd_val___1__h13363 = - rs1_val_bypassed__h4291 + _theResult___snd__h14727 ; - assign rd_val___1__h13371 = - rs1_val_bypassed__h4291 - _theResult___snd__h14727 ; - assign rd_val___1__h13378 = - ((rs1_val_bypassed__h4291 ^ 64'h8000000000000000) < - (_theResult___snd__h14727 ^ 64'h8000000000000000)) ? - 64'd1 : - 64'd0 ; - assign rd_val___1__h13385 = - (rs1_val_bypassed__h4291 < _theResult___snd__h14727) ? - 64'd1 : - 64'd0 ; - assign rd_val___1__h13392 = - rs1_val_bypassed__h4291 ^ _theResult___snd__h14727 ; - assign rd_val___1__h13399 = - rs1_val_bypassed__h4291 | _theResult___snd__h14727 ; - assign rd_val___1__h14756 = - { {32{alu_outputs___1_addr2629_BITS_31_TO_0__q20[31]}}, - alu_outputs___1_addr2629_BITS_31_TO_0__q20 } ; - assign rd_val___1__h14787 = { {32{x__h14790[31]}}, x__h14790 } ; - assign rd_val___1__h14841 = { {32{x__h14844[31]}}, x__h14844 } ; - assign rd_val___1__h14870 = { {32{tmp__h14869[31]}}, tmp__h14869 } ; - assign rd_val___1__h14922 = - { {32{rs1_val_bypassed291_BITS_31_TO_0_PLUS_rs2_val2_ETC__q10[31]}}, - rs1_val_bypassed291_BITS_31_TO_0_PLUS_rs2_val2_ETC__q10 } ; - assign rd_val___1__h14970 = - { {32{rs1_val_bypassed291_BITS_31_TO_0_MINUS_rs2_val_ETC__q11[31]}}, - rs1_val_bypassed291_BITS_31_TO_0_MINUS_rs2_val_ETC__q11 } ; - assign rd_val___1__h14976 = { {32{x__h14979[31]}}, x__h14979 } ; - assign rd_val___1__h15021 = { {32{x__h15024[31]}}, x__h15024 } ; - assign rd_val__h12119 = - (stage3_rg_full && stage3_rg_stage3[69] && - stage3_rg_stage3[68:64] == _theResult____h4283[24:20]) ? - stage3_rg_stage3[63:0] : - gpr_regfile$read_rs2 ; - assign rd_val__h14623 = rs1_val_bypassed__h4291 << shamt__h12477 ; - assign rd_val__h14675 = rs1_val_bypassed__h4291 >> shamt__h12477 ; - assign rd_val__h14697 = - rs1_val_bypassed__h4291 >> shamt__h12477 | - ~(64'hFFFFFFFFFFFFFFFF >> shamt__h12477) & - {64{rs1_val_bypassed__h4291[63]}} ; - assign rd_val__h6112 = - (stage3_rg_full && stage3_rg_stage3[69] && - stage3_rg_stage3[68:64] == _theResult____h4283[19:15]) ? - stage3_rg_stage3[63:0] : - gpr_regfile$read_rs1 ; - assign rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_EQ_0_ETC___d807 = - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] || - rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) && - _theResult____h4283[31:20] == 12'b000100000101 ; - assign rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 = - rg_state == 4'd3 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1310 && - !stage3_rg_full && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd0 ; - assign rg_state_2_EQ_3_225_AND_stage3_rg_full_2_OR_NO_ETC___d1244 = - rg_state == 4'd3 && - (stage3_rg_full || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd0 || - stage1_rg_full) && - (stage3_rg_full || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd3) && - (stage3_rg_full || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd0 || - !stage1_rg_full || - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1230) && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd0 || - stage3_rg_full) ; - assign rs1__h6770 = { 2'b01, instr__h4281[9:7] } ; - assign rs1_val__h18473 = - (x_out_data_to_stage2_instr__h12203[14:12] == 3'b001) ? - x_out_data_to_stage2_val1__h12207 : - { 59'd0, x_out_data_to_stage2_instr__h12203[19:15] } ; - assign rs1_val_bypassed291_BITS_31_TO_0_MINUS_rs2_val_ETC__q11 = - rs1_val_bypassed__h4291[31:0] - rs2_val__h12304[31:0] ; - assign rs1_val_bypassed291_BITS_31_TO_0_PLUS_rs2_val2_ETC__q10 = - rs1_val_bypassed__h4291[31:0] + rs2_val__h12304[31:0] ; - assign rs1_val_bypassed291_BITS_31_TO_0_SRL_rs2_val23_ETC__q9 = - rs1_val_bypassed__h4291[31:0] >> rs2_val__h12304[4:0] | - ~(32'hFFFFFFFF >> rs2_val__h12304[4:0]) & - {32{rs1_val_bypassed291_BITS_31_TO_0__q8[31]}} ; - assign rs1_val_bypassed291_BITS_31_TO_0__q8 = - rs1_val_bypassed__h4291[31:0] ; - assign rs1_val_bypassed__h4291 = - (_theResult____h4283[19:15] == 5'd0) ? 64'd0 : val__h6114 ; - assign rs2_val__h12304 = - (_theResult____h4283[24:20] == 5'd0) ? 64'd0 : val__h12121 ; - assign shamt__h12477 = - (_theResult____h4283[6:0] == 7'b0010011) ? - _theResult____h4283[25:20] : - rs2_val__h12304[5:0] ; - assign stage2_f_reset_rsps_i_notEmpty__182_AND_stage3_ETC___d1191 = - stage2_f_reset_rsps$EMPTY_N && stage3_f_reset_rsps$EMPTY_N && - f_reset_rsps$FULL_N && - (!rg_run_on_reset || - !near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) ; - assign sxl__h4705 = - (csr_regfile$read_misa[27:26] == 2'd2) ? - csr_regfile$read_mstatus[35:34] : - 2'd0 ; - assign theResult__283_BITS_31_TO_20__q19 = _theResult____h4283[31:20] ; - assign theResult__283_BITS_31_TO_25_CONCAT_theResult__ETC__q7 = - { _theResult____h4283[31:25], _theResult____h4283[11:7] } ; - assign theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q3 = - { _theResult____h4283[31], - _theResult____h4283[7], - _theResult____h4283[30:25], - _theResult____h4283[11:8], - 1'b0 } ; - assign theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q4 = - { _theResult____h4283[31], - _theResult____h4283[19:12], - _theResult____h4283[20], - _theResult____h4283[30:21], - 1'b0 } ; - assign tmp__h14869 = - rs1_val_bypassed__h4291[31:0] >> _theResult____h4283[24:20] | - ~(32'hFFFFFFFF >> _theResult____h4283[24:20]) & - {32{rs1_val_bypassed291_BITS_31_TO_0__q8[31]}} ; - assign trap_info_tval__h14094 = - (_theResult____h4283[6:0] != 7'b1101111 && - _theResult____h4283[6:0] != 7'b1100111 && - (_theResult____h4283[6:0] != 7'b1110011 || - _theResult____h4283[14:12] != 3'b0 || - _theResult____h4283[11:7] != 5'd0 || - _theResult____h4283[19:15] != 5'd0 || - _theResult____h4283[31:20] != 12'b0 && - _theResult____h4283[31:20] != 12'b000000000001)) ? - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d511 ? - { 32'd0, _theResult____h4283 } : - { 48'd0, instr__h4281[15:0] }) : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1151 ; - assign uxl__h4706 = - (csr_regfile$read_misa[27:26] == 2'd2) ? - csr_regfile$read_mstatus[33:32] : - 2'd0 ; - assign v32__h12581 = { _theResult____h4283[31:12], 12'h0 } ; - assign val__h12121 = - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == - 2'd2 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501) ? - x_out_bypass_rd_val__h6000 : - rd_val__h12119 ; - assign val__h6114 = - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == - 2'd2 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499) ? - x_out_bypass_rd_val__h6000 : - rd_val__h6112 ; - assign value__h14148 = - near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h14094 ; - assign x__h14790 = - rs1_val_bypassed__h4291[31:0] << _theResult____h4283[24:20] ; - assign x__h14844 = - rs1_val_bypassed__h4291[31:0] >> _theResult____h4283[24:20] ; - assign x__h14979 = rs1_val_bypassed__h4291[31:0] << rs2_val__h12304[4:0] ; - assign x__h15024 = rs1_val_bypassed__h4291[31:0] >> rs2_val__h12304[4:0] ; - assign x__h23528 = - csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1401[63:0] / - _theResult____h23527 ; - assign x_out_data_to_stage2_instr__h12203 = _theResult____h4283 ; - assign x_out_data_to_stage2_rd__h12205 = - (_theResult____h4283[6:0] == 7'b1100011) ? - 5'd0 : - _theResult____h4283[11:7] ; - assign x_out_data_to_stage2_val2__h12208 = - (_theResult____h4283[6:0] == 7'b1100011) ? - branch_target__h12308 : - rs2_val__h12304 ; - assign x_out_next_pc__h12175 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767 ? - data_to_stage2_addr__h12198 : - fall_through_pc__h12162 ; - assign x_out_trap_info_exc_code__h14097 = - near_mem$imem_exc ? - near_mem$imem_exc_code : - alu_outputs_exc_code__h12932 ; - assign y__h19264 = ~rs1_val__h18963 ; - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[199:197]) - 3'd0, 3'd1, 3'd4: - x_out_data_to_stage3_rd__h5648 = stage2_rg_stage2[196:192]; - 3'd2: x_out_data_to_stage3_rd__h5648 = 5'd0; - default: x_out_data_to_stage3_rd__h5648 = stage2_rg_stage2[196:192]; - endcase - end - always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64) - begin - case (stage2_rg_stage2[199:197]) - 3'd0: x_out_data_to_stage3_rd_val__h5649 = stage2_rg_stage2[127:64]; - 3'd1, 3'd4: x_out_data_to_stage3_rd_val__h5649 = near_mem$dmem_word64; - default: x_out_data_to_stage3_rd_val__h5649 = stage2_mbox$word; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[199:197]) - 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h5999 = stage2_rg_stage2[196:192]; - default: x_out_bypass_rd__h5999 = stage2_rg_stage2[196:192]; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$word or output_stage2___1_bypass_rd_val__h5988) - begin - case (stage2_rg_stage2[199:197]) - 3'd0: x_out_bypass_rd_val__h6000 = stage2_rg_stage2[127:64]; - 3'd1, 3'd4: - x_out_bypass_rd_val__h6000 = output_stage2___1_bypass_rd_val__h5988; - default: x_out_bypass_rd_val__h6000 = stage2_mbox$word; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119 or - IF_near_mem_dmem_valid__13_THEN_IF_near_mem_dm_ETC___d116) - begin - case (stage2_rg_stage2[199:197]) - 3'd0: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q1 = 2'd2; - 3'd1, 3'd2, 3'd4: - CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q1 = - IF_near_mem_dmem_valid__13_THEN_IF_near_mem_dm_ETC___d116; - default: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q1 = - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[199:197]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d136 = - !near_mem$dmem_valid || near_mem$dmem_exc; - default: IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d136 = - !stage2_mbox$valid; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[199:197]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145 = - near_mem$dmem_valid && !near_mem$dmem_exc; - default: IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145 = - stage2_mbox$valid; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119 or - IF_NOT_near_mem_dmem_valid__13_32_OR_NOT_near__ETC___d179) - begin - case (stage2_rg_stage2[199:197]) - 3'd0: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2 = 2'd2; - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2 = - IF_NOT_near_mem_dmem_valid__13_32_OR_NOT_near__ETC___d179; - 3'd2: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2 = 2'd0; - default: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2 = - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119; - endcase - end - always@(rg_cur_priv) - begin - case (rg_cur_priv) - 2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd8; - 2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd9; - default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd11; - endcase - end - always@(_theResult____h4283 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q5) - begin - case (_theResult____h4283[31:20]) - 12'b0: - CASE_theResult__283_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = - CASE_rg_cur_priv_0b0_8_0b1_9_11__q5; - 12'b000000000001: - CASE_theResult__283_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd3; - default: CASE_theResult__283_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd2; - endcase - end - always@(_theResult____h4283 or alu_outputs___1_exc_code__h12886) - begin - case (_theResult____h4283[6:0]) - 7'b0000011, - 7'b0001111, - 7'b0010011, - 7'b0010111, - 7'b0011011, - 7'b0100011, - 7'b0110011, - 7'b0110111, - 7'b0111011, - 7'b1100011: - alu_outputs_exc_code__h12932 = 4'd2; - 7'b1100111, 7'b1101111: alu_outputs_exc_code__h12932 = 4'd0; - 7'b1110011: - alu_outputs_exc_code__h12932 = alu_outputs___1_exc_code__h12886; - default: alu_outputs_exc_code__h12932 = 4'd2; - endcase - end - always@(funct10__h12562 or - _theResult___fst__h13601 or - rd_val___1__h14922 or - rd_val___1__h14976 or rd_val___1__h15021 or rd_val___1__h14970) - begin - case (funct10__h12562) - 10'b0: alu_outputs___1_val1__h12576 = rd_val___1__h14922; - 10'b0000000001: alu_outputs___1_val1__h12576 = rd_val___1__h14976; - 10'b0000000101: alu_outputs___1_val1__h12576 = rd_val___1__h15021; - 10'b0100000000: alu_outputs___1_val1__h12576 = rd_val___1__h14970; - default: alu_outputs___1_val1__h12576 = _theResult___fst__h13601; - endcase - end - always@(_theResult____h4283 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560) - begin - case (_theResult____h4283[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - _theResult____h4283[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562; - endcase - end - always@(_theResult____h4283 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560) - begin - case (_theResult____h4283[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - _theResult____h4283[14:12] == 3'b111 && - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[6:0]) - 7'b0000011: - CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4283[14:12] != 3'b0 && - _theResult____h4283[14:12] != 3'b100 && - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b101 && - _theResult____h4283[14:12] != 3'b010 && - _theResult____h4283[14:12] != 3'b110 && - _theResult____h4283[14:12] != 3'b011; - 7'b0100011: - CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4283[14:12] != 3'b0 && - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b010 && - _theResult____h4283[14:12] != 3'b011; - default: CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4283[6:0] != 7'b0101111 || - _theResult____h4283[31:27] != 5'b00010 && - _theResult____h4283[31:27] != 5'b00011 && - _theResult____h4283[31:27] != 5'b0 && - _theResult____h4283[31:27] != 5'b00001 && - _theResult____h4283[31:27] != 5'b01100 && - _theResult____h4283[31:27] != 5'b01000 && - _theResult____h4283[31:27] != 5'b00100 && - _theResult____h4283[31:27] != 5'b10000 && - _theResult____h4283[31:27] != 5'b11000 && - _theResult____h4283[31:27] != 5'b10100 && - _theResult____h4283[31:27] != 5'b11100 || - _theResult____h4283[14:12] != 3'b010 && - _theResult____h4283[14:12] != 3'b011; - endcase - end - always@(_theResult____h4283 or - CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 or - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d605 or - funct10__h12562) - begin - case (_theResult____h4283[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d605; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - _theResult____h4283[14:12] != 3'b0 && - (_theResult____h4283[14:12] != 3'b001 || - _theResult____h4283[25]) && - (_theResult____h4283[14:12] != 3'b101 || - _theResult____h4283[25]); - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - funct10__h12562 != 10'b0 && funct10__h12562 != 10'b0100000000 && - funct10__h12562 != 10'b0000000001 && - funct10__h12562 != 10'b0000000101 && - funct10__h12562 != 10'b0100000101; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - _theResult____h4283[6:0] != 7'b0110111 && - _theResult____h4283[6:0] != 7'b0010111 && - CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[6:0]) - 7'b0000011: - CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13 = - _theResult____h4283[14:12] == 3'b0 || - _theResult____h4283[14:12] == 3'b100 || - _theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b101 || - _theResult____h4283[14:12] == 3'b010 || - _theResult____h4283[14:12] == 3'b110 || - _theResult____h4283[14:12] == 3'b011; - 7'b0100011: - CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13 = - _theResult____h4283[14:12] == 3'b0 || - _theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b010 || - _theResult____h4283[14:12] == 3'b011; - default: CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13 = - _theResult____h4283[6:0] == 7'b0101111 && - (_theResult____h4283[31:27] == 5'b00010 || - _theResult____h4283[31:27] == 5'b00011 || - _theResult____h4283[31:27] == 5'b0 || - _theResult____h4283[31:27] == 5'b00001 || - _theResult____h4283[31:27] == 5'b01100 || - _theResult____h4283[31:27] == 5'b01000 || - _theResult____h4283[31:27] == 5'b00100 || - _theResult____h4283[31:27] == 5'b10000 || - _theResult____h4283[31:27] == 5'b11000 || - _theResult____h4283[31:27] == 5'b10100 || - _theResult____h4283[31:27] == 5'b11100) && - (_theResult____h4283[14:12] == 3'b010 || - _theResult____h4283[14:12] == 3'b011); - endcase - end - always@(_theResult____h4283 or - CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d724 or - funct10__h12562) - begin - case (_theResult____h4283[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d724; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762 = - _theResult____h4283[14:12] == 3'b0 || - (_theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b101) && - !_theResult____h4283[25]; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762 = - funct10__h12562 == 10'b0 || funct10__h12562 == 10'b0100000000 || - funct10__h12562 == 10'b0000000001 || - funct10__h12562 == 10'b0000000101 || - funct10__h12562 == 10'b0100000101; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762 = - _theResult____h4283[6:0] == 7'b0110111 || - _theResult____h4283[6:0] == 7'b0010111 || - CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13; - endcase - end - always@(_theResult____h4283 or - rg_cur_priv or - IF_rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_E_ETC___d809) - begin - case (_theResult____h4283[31:20]) - 12'b0, 12'b000000000001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d811 = 4'd11; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d811 = - (rg_cur_priv == 2'b11 && - _theResult____h4283[31:20] == 12'b001100000010) ? - 4'd7 : - IF_rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_E_ETC___d809; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[14:12]) - 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd0; - 3'd7: CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd11; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[14:12]) - 3'b0: CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd4; - 3'b001: CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd5; - default: CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd11; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[14:12]) - 3'b0, 3'b001, 3'b010, 3'b011: - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q16 = 4'd0; - default: CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q16 = - 4'd11; - endcase - end - always@(_theResult____h4283 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d811) - begin - case (_theResult____h4283[14:12]) - 3'b0: - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17 = - (_theResult____h4283[11:7] == 5'd0 && - _theResult____h4283[19:15] == 5'd0) ? - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d811 : - 4'd11; - 3'b001, 3'b101: - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17 = 4'd2; - 3'b010, 3'b011, 3'b110, 3'b111: - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17 = 4'd3; - 3'd4: CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17 = 4'd11; - endcase - end - always@(_theResult____h4283 or - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 or - CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15 or - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d774 or - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q16 or - funct10__h12562 or - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17) - begin - case (_theResult____h4283[6:0]) - 7'b0000011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14; - 7'b0001111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15; - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d774; - 7'b0010111, 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = 4'd0; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - (_theResult____h4283[14:12] != 3'b0 && - (_theResult____h4283[14:12] != 3'b001 || - _theResult____h4283[25]) && - (_theResult____h4283[14:12] != 3'b101 || - _theResult____h4283[25])) ? - 4'd11 : - 4'd0; - 7'b0100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q16; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - ((_theResult____h4283[31:27] == 5'b00010 || - _theResult____h4283[31:27] == 5'b00011 || - _theResult____h4283[31:27] == 5'b0 || - _theResult____h4283[31:27] == 5'b00001 || - _theResult____h4283[31:27] == 5'b01100 || - _theResult____h4283[31:27] == 5'b01000 || - _theResult____h4283[31:27] == 5'b00100 || - _theResult____h4283[31:27] == 5'b10000 || - _theResult____h4283[31:27] == 5'b11000 || - _theResult____h4283[31:27] == 5'b10100 || - _theResult____h4283[31:27] == 5'b11100) && - (_theResult____h4283[14:12] == 3'b010 || - _theResult____h4283[14:12] == 3'b011)) ? - 4'd0 : - 4'd11; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - (funct10__h12562 != 10'b0 && - funct10__h12562 != 10'b0100000000 && - funct10__h12562 != 10'b0000000001 && - funct10__h12562 != 10'b0000000101 && - funct10__h12562 != 10'b0100000101) ? - 4'd11 : - 4'd0; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - 4'd11; - endcase - end - always@(_theResult____h4283 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d717 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569) - begin - case (_theResult____h4283[6:0]) - 7'b1100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d831 = - (_theResult____h4283[14:12] != 3'b0 && - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b100 && - _theResult____h4283[14:12] != 3'b101 && - _theResult____h4283[14:12] != 3'b110 && - _theResult____h4283[14:12] != 3'b111) ? - 4'd11 : - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 ? - 4'd1 : - 4'd0); - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d831 = 4'd1; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d831 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d717 ? - 4'd0 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[6:0]) - 7'b0000011: - CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18 = 3'd1; - 7'b0010011, 7'b0010111, 7'b0011011, 7'b0110011, 7'b0110111, 7'b0111011: - CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18 = 3'd0; - 7'b0100011: - CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18 = 3'd2; - default: CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18 = 3'd4; - endcase - end - always@(_theResult____h4283 or - CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18) - begin - case (_theResult____h4283[6:0]) - 7'b1100011, 7'b1100111, 7'b1101111: - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 = 3'd0; - default: IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 = - ((_theResult____h4283[6:0] == 7'b0110011 || - _theResult____h4283[6:0] == 7'b0111011) && - _theResult____h4283[31:25] == 7'b0000001) ? - 3'd3 : - CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18; - endcase - end - always@(_theResult____h4283 or - _theResult_____1_fst__h13410 or - rd_val___1__h13378 or - rd_val___1__h13385 or rd_val___1__h13392 or rd_val___1__h13399) - begin - case (_theResult____h4283[14:12]) - 3'b010: _theResult_____1_fst__h13382 = rd_val___1__h13378; - 3'b011: _theResult_____1_fst__h13382 = rd_val___1__h13385; - 3'b100: _theResult_____1_fst__h13382 = rd_val___1__h13392; - 3'b110: _theResult_____1_fst__h13382 = rd_val___1__h13399; - default: _theResult_____1_fst__h13382 = _theResult_____1_fst__h13410; - endcase - end - always@(_theResult____h4283 or - rs1_val_bypassed__h4291 or - alu_outputs___1_addr__h12629 or - alu_outputs___1_addr__h12650 or - alu_outputs___1_addr__h12330 or - alu_outputs___1_addr__h12377 or alu_outputs___1_addr__h12351) - begin - case (_theResult____h4283[6:0]) - 7'b0000011: - x_out_data_to_stage2_addr__h12206 = alu_outputs___1_addr__h12629; - 7'b0100011: - x_out_data_to_stage2_addr__h12206 = alu_outputs___1_addr__h12650; - 7'b1100011: - x_out_data_to_stage2_addr__h12206 = alu_outputs___1_addr__h12330; - 7'b1100111: - x_out_data_to_stage2_addr__h12206 = alu_outputs___1_addr__h12377; - 7'b1101111: - x_out_data_to_stage2_addr__h12206 = alu_outputs___1_addr__h12351; - default: x_out_data_to_stage2_addr__h12206 = rs1_val_bypassed__h4291; - endcase - end - always@(_theResult____h4283 or imem_rg_pc or data_to_stage2_addr__h12198) - begin - case (_theResult____h4283[6:0]) - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1151 = - data_to_stage2_addr__h12198; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1151 = - (_theResult____h4283[6:0] == 7'b1110011 && - _theResult____h4283[14:12] == 3'b0 && - _theResult____h4283[11:7] == 5'd0 && - _theResult____h4283[19:15] == 5'd0 && - _theResult____h4283[31:20] == 12'b000000000001) ? - imem_rg_pc : - 64'd0; - endcase - end - always@(_theResult____h4283 or - alu_outputs___1_val1__h12911 or - alu_outputs___1_val1__h12530 or - alu_outputs___1_val1__h12608 or - alu_outputs___1_val1__h12553 or - alu_outputs___1_val1__h12592 or - alu_outputs___1_val1__h12576 or alu_outputs___1_val1__h12890) - begin - case (_theResult____h4283[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12530; - 7'b0010111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12608; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12553; - 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12592; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12576; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12890; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12911; - endcase - end - always@(_theResult____h4283 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1065 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d962) - begin - case (_theResult____h4283[6:0]) - 7'b1100111, 7'b1101111: - x_out_data_to_stage2_val1__h12207 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d962; - default: x_out_data_to_stage2_val1__h12207 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1065; - endcase - end - always@(x_out_data_to_stage2_instr__h12203 or - x_out_data_to_stage2_val1__h12207) - begin - case (x_out_data_to_stage2_instr__h12203[14:12]) - 3'b010, 3'b011: rs1_val__h18963 = x_out_data_to_stage2_val1__h12207; - default: rs1_val__h18963 = - { 59'd0, x_out_data_to_stage2_instr__h12203[19:15] }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0; - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11; - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_logdelay$EN) - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN; - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_cur_priv$EN) - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN; - if (rg_run_on_reset$EN) - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (stage1_rg_full$EN) - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN; - if (stage2_rg_full$EN) - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN; - if (stage2_rg_resetting$EN) - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY - stage2_rg_resetting$D_IN; - if (stage3_rg_full$EN) - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN; - end - if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN; - if (imem_rg_instr_15_0$EN) - imem_rg_instr_15_0 <= `BSV_ASSIGNMENT_DELAY imem_rg_instr_15_0$D_IN; - if (imem_rg_mstatus_MXR$EN) - imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN; - if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN; - if (imem_rg_priv$EN) - imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN; - if (imem_rg_satp$EN) - imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN; - if (imem_rg_sstatus_SUM$EN) - imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN; - if (imem_rg_tval$EN) - imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_start_CPI_cycles$EN) - rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN; - if (rg_start_CPI_instrs$EN) - rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN; - if (stage2_rg_stage2$EN) - stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN; - if (stage3_rg_stage3$EN) - stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_logdelay = 64'hAAAAAAAAAAAAAAAA; - cfg_verbosity = 4'hA; - imem_rg_f3 = 3'h2; - imem_rg_instr_15_0 = 16'hAAAA; - imem_rg_mstatus_MXR = 1'h0; - imem_rg_pc = 64'hAAAAAAAAAAAAAAAA; - imem_rg_priv = 2'h2; - imem_rg_satp = 64'hAAAAAAAAAAAAAAAA; - imem_rg_sstatus_SUM = 1'h0; - imem_rg_tval = 64'hAAAAAAAAAAAAAAAA; - rg_cur_priv = 2'h2; - rg_mstatus_MXR = 1'h0; - rg_next_pc = 64'hAAAAAAAAAAAAAAAA; - rg_run_on_reset = 1'h0; - rg_sstatus_SUM = 1'h0; - rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA; - rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - stage1_rg_full = 1'h0; - stage2_rg_full = 1'h0; - stage2_rg_resetting = 1'h0; - stage2_rg_stage2 = - 298'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - stage3_rg_full = 1'h0; - stage3_rg_stage3 = 168'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - rg_cur_priv, - csr_regfile$read_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write("MStatus{", - "sd:%0d", - csr_regfile$read_mstatus[14:13] == 2'h3 || - csr_regfile$read_mstatus[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2) - $write(" sxl:%0d uxl:%0d", sxl__h4705, uxl__h4706); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tsr:%0d", csr_regfile$read_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tw:%0d", csr_regfile$read_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tvm:%0d", csr_regfile$read_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mxr:%0d", csr_regfile$read_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" sum:%0d", csr_regfile$read_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mprv:%0d", csr_regfile$read_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" xs:%0d", csr_regfile$read_mstatus[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" fs:%0d", csr_regfile$read_mstatus[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mpp:%0d", csr_regfile$read_mstatus[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" spp:%0d", csr_regfile$read_mstatus[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" pies:%0d_%0d%0d", - csr_regfile$read_mstatus[7], - csr_regfile$read_mstatus[5], - csr_regfile$read_mstatus[4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" ies:%0d_%0d%0d", - csr_regfile$read_mstatus[3], - csr_regfile$read_mstatus[1], - csr_regfile$read_mstatus[0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_full || !stage3_rg_stage3[69])) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full && stage3_rg_stage3[69]) - $write("Rd %0d ", - stage3_rg_stage3[68:64], - "rd_val:%h", - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage2: pc 0x%08h instr 0x%08h priv %0d", - stage2_rg_stage2[295:232], - stage2_rg_stage2[231:200], - stage2_rg_stage2[297:296]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write("Output_Stage2", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[295:232]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("Output_Stage2", " NONPIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write("Output_Stage2", " PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[295:232], - stage2_rg_stage2[231:200], - stage2_rg_stage2[297:296]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3 && - stage2_rg_stage2[199:197] != 3'd0 && - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d136) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3 && - (stage2_rg_stage2[199:197] == 3'd0 || - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h5648, - x_out_data_to_stage3_rd_val__h5649); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", stage2_rg_stage2[295:232]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", near_mem$dmem_exc_code); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", stage2_rg_stage2[191:128], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", stage2_rg_stage2[295:232]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", near_mem$dmem_exc_code); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", stage2_rg_stage2[191:128], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == 2'd0) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 != 2'd0) - $write("Rd %0d ", x_out_bypass_rd__h5999); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 != 2'd1) - $write("rd_val:%h", x_out_bypass_rd_val__h6000); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage1: pc 0x%08h instr 0x%08h priv %0d", - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write("Output_Stage1", " BUSY pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write("Output_Stage1", " NONPIPE: pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write("Output_Stage1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) - $write("Output_Stage1", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(" PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd0) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd1) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd2) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd3) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd4) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd5) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd6) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd7) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd8) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd9) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd10) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d899) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n", - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(" op_stage2:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == 3'd0) - $write("OP_Stage2_ALU"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == 3'd1) - $write("OP_Stage2_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == 3'd2) - $write("OP_Stage2_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == 3'd3) - $write("OP_Stage2_M"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d940) - $write("OP_Stage2_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(" rd:%0d\n", x_out_data_to_stage2_rd__h12205); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(" addr:%h val1:%h val2:%h}", - x_out_data_to_stage2_addr__h12206, - x_out_data_to_stage2_val1__h12207, - x_out_data_to_stage2_val2__h12208); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1076) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1079) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1082) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1085) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1088) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1091) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1094) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1097) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1100) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1103) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1106) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1109) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write("'h%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write("'h%h", x_out_trap_info_exc_code__h14097); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write("'h%h", value__h14148, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519) - $write(" next_pc 0x%08h", x_out_next_pc__h12175); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[295:232], - stage2_rg_stage2[231:200], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h2988 != 4'd0) - $display(" mcause:0x%0h epc 0x%0h tval:0x%0h new pc 0x%0h, new mstatus 0x%0h", - csr_regfile$csr_trap_actions[65:2], - stage2_rg_stage2[295:232], - stage2_rg_stage2[191:128], - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[129:66]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12203[19:15], - rs1_val__h18473, - x_out_data_to_stage2_instr__h12203[31:20], - csr_regfile$read_csr[63:0], - x_out_data_to_stage2_instr__h12203[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12203[19:15], - rs1_val__h18473, - x_out_data_to_stage2_instr__h12203[31:20], - x_out_data_to_stage2_instr__h12203[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_S_or_C", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12203[19:15], - rs1_val__h18963, - x_out_data_to_stage2_instr__h12203[31:20], - csr_regfile$read_csr[63:0], - x_out_data_to_stage2_instr__h12203[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12203[19:15], - rs1_val__h18963, - x_out_data_to_stage2_instr__h12203[31:20], - x_out_data_to_stage2_instr__h12203[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12175); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d pc:%0x cur_priv:%0d", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - x_out_next_pc__h12175, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2988 != 4'd0) - $display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d", - csr_regfile$csr_ret_actions[129:66], - csr_regfile$csr_ret_actions[63:0], - csr_regfile$csr_ret_actions[65:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_stage1_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h2988 != 4'd0) - $display(" WFI resume"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_from_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d1398) - $display("%0d: CPU.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x", - csr_regfile$read_csr_mcycle, - csr_regfile$csr_trap_actions[193:130], - x_out_data_to_stage2_instr__h12203); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d1398) - $display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'", - cpi__h23529, - cpifrac__h23530, - delta_CPI_cycles__h23525, - _theResult____h23527); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d1398) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2988 != 4'd0) - $display("%0d: CPU.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", - csr_regfile$read_csr_mcycle, - rg_cur_priv, - csr_regfile$csr_trap_actions[65:2], - imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2988 != 4'd0) - $display(" tval:0x%0h new pc:0x%0h new mstatus:0x%0h", - value__h14148, - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[129:66]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_trap_fetch && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2988 != 4'd0) - $display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", - csr_regfile$read_csr_mcycle, - imem_rg_pc, - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[1:0], - csr_regfile$csr_trap_actions[129:66]); - if (WILL_FIRE_RL_imem_rl_assert_fail) - $display("ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False"); - if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", soc_map$m_pc_reset_value); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h", - csr_regfile$read_csr_mcycle, - soc_map$m_pc_reset_value); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[69] && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[68:64], - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" S3.enq: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[295:232], - stage2_rg_stage2[231:200], - stage2_rg_stage2[297:296]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - stage2_rg_stage2[199:197] != 3'd0 && - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d136) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - (stage2_rg_stage2[199:197] == 3'd0 || - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h5648, - x_out_data_to_stage3_rd_val__h5649); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[295:232], - stage2_rg_stage2[231:200], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage2.enq (Data_Stage1_to_Stage2)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12175); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $write("CPU: Bluespec RISC-V Piccolo v3.0"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) $display(" (RV64)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h2988 != 4'd0) - $display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle); - end - // synopsys translate_on -endmodule // mkCPU - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v deleted file mode 100644 index bcb2abf3..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIE.v +++ /dev/null @@ -1,141 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 64 -// fav_write O 64 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 64 -// EN_reset I 1 -// EN_fav_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIE(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [63 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [63 : 0] fav_write_wordxl; - input EN_fav_write; - output [63 : 0] fav_write; - - // signals for module outputs - wire [63 : 0] fav_write, fv_read; - - // register rg_mie - reg [11 : 0] rg_mie; - wire [11 : 0] rg_mie$D_IN; - wire rg_mie$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_write, - CAN_FIRE_reset, - WILL_FIRE_fav_write, - WILL_FIRE_reset; - - // remaining internal signals - wire [11 : 0] mie__h88; - wire seie__h119, ssie__h113, stie__h116, ueie__h118, usie__h112, utie__h115; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 52'd0, rg_mie } ; - - // actionvalue method fav_write - assign fav_write = { 52'd0, mie__h88 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // register rg_mie - assign rg_mie$D_IN = EN_fav_write ? mie__h88 : 12'd0 ; - assign rg_mie$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign mie__h88 = - { fav_write_wordxl[11], - 1'b0, - seie__h119, - ueie__h118, - fav_write_wordxl[7], - 1'b0, - stie__h116, - utie__h115, - fav_write_wordxl[3], - 1'b0, - ssie__h113, - usie__h112 } ; - assign seie__h119 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssie__h113 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign stie__h116 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueie__h118 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign usie__h112 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign utie__h115 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_mie = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIE - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v deleted file mode 100644 index df113ffb..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_MIP.v +++ /dev/null @@ -1,289 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 64 -// fav_write O 64 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 64 -// m_external_interrupt_req_req I 1 reg -// s_external_interrupt_req_req I 1 reg -// software_interrupt_req_req I 1 reg -// timer_interrupt_req_req I 1 reg -// EN_reset I 1 -// EN_fav_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIP(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - m_external_interrupt_req_req, - - s_external_interrupt_req_req, - - software_interrupt_req_req, - - timer_interrupt_req_req); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [63 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [63 : 0] fav_write_wordxl; - input EN_fav_write; - output [63 : 0] fav_write; - - // action method m_external_interrupt_req - input m_external_interrupt_req_req; - - // action method s_external_interrupt_req - input s_external_interrupt_req_req; - - // action method software_interrupt_req - input software_interrupt_req_req; - - // action method timer_interrupt_req - input timer_interrupt_req_req; - - // signals for module outputs - wire [63 : 0] fav_write, fv_read; - - // register rg_meip - reg rg_meip; - wire rg_meip$D_IN, rg_meip$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_seip - reg rg_seip; - wire rg_seip$D_IN, rg_seip$EN; - - // register rg_ssip - reg rg_ssip; - wire rg_ssip$D_IN, rg_ssip$EN; - - // register rg_stip - reg rg_stip; - wire rg_stip$D_IN, rg_stip$EN; - - // register rg_ueip - reg rg_ueip; - wire rg_ueip$D_IN, rg_ueip$EN; - - // register rg_usip - reg rg_usip; - wire rg_usip$D_IN, rg_usip$EN; - - // register rg_utip - reg rg_utip; - wire rg_utip$D_IN, rg_utip$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_write, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_reset, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_fav_write, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_reset, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // remaining internal signals - wire [11 : 0] new_mip__h524, new_mip__h942; - wire seip__h558, ssip__h562, stip__h560, ueip__h559, usip__h563, utip__h561; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 52'd0, new_mip__h524 } ; - - // actionvalue method fav_write - assign fav_write = { 52'd0, new_mip__h942 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // register rg_meip - assign rg_meip$D_IN = m_external_interrupt_req_req ; - assign rg_meip$EN = 1'b1 ; - - // register rg_msip - assign rg_msip$D_IN = software_interrupt_req_req ; - assign rg_msip$EN = 1'b1 ; - - // register rg_mtip - assign rg_mtip$D_IN = timer_interrupt_req_req ; - assign rg_mtip$EN = 1'b1 ; - - // register rg_seip - assign rg_seip$D_IN = s_external_interrupt_req_req ; - assign rg_seip$EN = 1'b1 ; - - // register rg_ssip - assign rg_ssip$D_IN = !EN_reset && ssip__h562 ; - assign rg_ssip$EN = EN_fav_write || EN_reset ; - - // register rg_stip - assign rg_stip$D_IN = !EN_reset && stip__h560 ; - assign rg_stip$EN = EN_fav_write || EN_reset ; - - // register rg_ueip - assign rg_ueip$D_IN = !EN_reset && ueip__h559 ; - assign rg_ueip$EN = EN_fav_write || EN_reset ; - - // register rg_usip - assign rg_usip$D_IN = !EN_reset && usip__h563 ; - assign rg_usip$EN = EN_fav_write || EN_reset ; - - // register rg_utip - assign rg_utip$D_IN = !EN_reset && utip__h561 ; - assign rg_utip$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign new_mip__h524 = - { rg_meip, - 1'b0, - rg_seip, - rg_ueip, - rg_mtip, - 1'b0, - rg_stip, - rg_utip, - rg_msip, - 1'b0, - rg_ssip, - rg_usip } ; - assign new_mip__h942 = - { rg_meip, - 1'b0, - seip__h558, - ueip__h559, - rg_mtip, - 1'b0, - stip__h560, - utip__h561, - rg_msip, - 1'b0, - ssip__h562, - usip__h563 } ; - assign seip__h558 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssip__h562 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign stip__h560 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueip__h559 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign usip__h563 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign utip__h561 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN; - if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN; - if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN; - if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN; - if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN; - if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_meip = 1'h0; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_seip = 1'h0; - rg_ssip = 1'h0; - rg_stip = 1'h0; - rg_ueip = 1'h0; - rg_usip = 1'h0; - rg_utip = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIP - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v deleted file mode 100644 index ab0a2899..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCSR_RegFile.v +++ /dev/null @@ -1,2371 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_csr O 65 -// read_csr_port2 O 65 -// mav_read_csr O 65 -// mav_csr_write O 64 -// read_misa O 28 const -// read_mstatus O 64 reg -// read_ustatus O 64 -// read_satp O 64 const -// csr_trap_actions O 194 -// RDY_csr_trap_actions O 1 const -// csr_ret_actions O 130 -// RDY_csr_ret_actions O 1 const -// read_csr_minstret O 64 reg -// read_csr_mcycle O 64 reg -// read_csr_mtime O 64 reg -// access_permitted_1 O 1 -// access_permitted_2 O 1 -// csr_counter_read_fault O 1 -// csr_mip_read O 64 -// interrupt_pending O 5 -// wfi_resume O 1 -// nmi_pending O 1 reg -// RDY_debug O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// read_csr_csr_addr I 12 -// read_csr_port2_csr_addr I 12 -// mav_read_csr_csr_addr I 12 -// mav_csr_write_csr_addr I 12 -// mav_csr_write_word I 64 -// csr_trap_actions_from_priv I 2 -// csr_trap_actions_pc I 64 -// csr_trap_actions_nmi I 1 -// csr_trap_actions_interrupt I 1 -// csr_trap_actions_exc_code I 4 -// csr_trap_actions_xtval I 64 -// csr_ret_actions_from_priv I 2 -// access_permitted_1_priv I 2 -// access_permitted_1_csr_addr I 12 -// access_permitted_1_read_not_write I 1 -// access_permitted_2_priv I 2 -// access_permitted_2_csr_addr I 12 -// access_permitted_2_read_not_write I 1 -// csr_counter_read_fault_priv I 2 -// csr_counter_read_fault_csr_addr I 12 -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// interrupt_pending_cur_priv I 2 -// nmi_req_set_not_clear I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_csr_minstret_incr I 1 -// EN_debug I 1 unused -// EN_mav_read_csr I 1 unused -// EN_mav_csr_write I 1 -// EN_csr_trap_actions I 1 -// EN_csr_ret_actions I 1 -// -// Combinational paths from inputs to outputs: -// read_csr_csr_addr -> read_csr -// read_csr_port2_csr_addr -> read_csr_port2 -// (access_permitted_1_priv, -// access_permitted_1_csr_addr, -// access_permitted_1_read_not_write) -> access_permitted_1 -// (access_permitted_2_priv, -// access_permitted_2_csr_addr, -// access_permitted_2_read_not_write) -> access_permitted_2 -// (csr_counter_read_fault_priv, -// csr_counter_read_fault_csr_addr) -> csr_counter_read_fault -// interrupt_pending_cur_priv -> interrupt_pending -// mav_read_csr_csr_addr -> mav_read_csr -// (mav_csr_write_csr_addr, -// mav_csr_write_word, -// EN_mav_csr_write) -> mav_csr_write -// (csr_trap_actions_from_priv, -// csr_trap_actions_nmi, -// csr_trap_actions_interrupt, -// csr_trap_actions_exc_code) -> csr_trap_actions -// csr_ret_actions_from_priv -> csr_ret_actions -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_csr_csr_addr, - read_csr, - - read_csr_port2_csr_addr, - read_csr_port2, - - mav_read_csr_csr_addr, - EN_mav_read_csr, - mav_read_csr, - - mav_csr_write_csr_addr, - mav_csr_write_word, - EN_mav_csr_write, - mav_csr_write, - - read_misa, - - read_mstatus, - - read_ustatus, - - read_satp, - - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_nmi, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval, - EN_csr_trap_actions, - csr_trap_actions, - RDY_csr_trap_actions, - - csr_ret_actions_from_priv, - EN_csr_ret_actions, - csr_ret_actions, - RDY_csr_ret_actions, - - read_csr_minstret, - - EN_csr_minstret_incr, - - read_csr_mcycle, - - read_csr_mtime, - - access_permitted_1_priv, - access_permitted_1_csr_addr, - access_permitted_1_read_not_write, - access_permitted_1, - - access_permitted_2_priv, - access_permitted_2_csr_addr, - access_permitted_2_read_not_write, - access_permitted_2, - - csr_counter_read_fault_priv, - csr_counter_read_fault_csr_addr, - csr_counter_read_fault, - - csr_mip_read, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - interrupt_pending_cur_priv, - interrupt_pending, - - wfi_resume, - - nmi_req_set_not_clear, - - nmi_pending, - - EN_debug, - RDY_debug); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_csr - input [11 : 0] read_csr_csr_addr; - output [64 : 0] read_csr; - - // value method read_csr_port2 - input [11 : 0] read_csr_port2_csr_addr; - output [64 : 0] read_csr_port2; - - // actionvalue method mav_read_csr - input [11 : 0] mav_read_csr_csr_addr; - input EN_mav_read_csr; - output [64 : 0] mav_read_csr; - - // actionvalue method mav_csr_write - input [11 : 0] mav_csr_write_csr_addr; - input [63 : 0] mav_csr_write_word; - input EN_mav_csr_write; - output [63 : 0] mav_csr_write; - - // value method read_misa - output [27 : 0] read_misa; - - // value method read_mstatus - output [63 : 0] read_mstatus; - - // value method read_ustatus - output [63 : 0] read_ustatus; - - // value method read_satp - output [63 : 0] read_satp; - - // actionvalue method csr_trap_actions - input [1 : 0] csr_trap_actions_from_priv; - input [63 : 0] csr_trap_actions_pc; - input csr_trap_actions_nmi; - input csr_trap_actions_interrupt; - input [3 : 0] csr_trap_actions_exc_code; - input [63 : 0] csr_trap_actions_xtval; - input EN_csr_trap_actions; - output [193 : 0] csr_trap_actions; - output RDY_csr_trap_actions; - - // actionvalue method csr_ret_actions - input [1 : 0] csr_ret_actions_from_priv; - input EN_csr_ret_actions; - output [129 : 0] csr_ret_actions; - output RDY_csr_ret_actions; - - // value method read_csr_minstret - output [63 : 0] read_csr_minstret; - - // action method csr_minstret_incr - input EN_csr_minstret_incr; - - // value method read_csr_mcycle - output [63 : 0] read_csr_mcycle; - - // value method read_csr_mtime - output [63 : 0] read_csr_mtime; - - // value method access_permitted_1 - input [1 : 0] access_permitted_1_priv; - input [11 : 0] access_permitted_1_csr_addr; - input access_permitted_1_read_not_write; - output access_permitted_1; - - // value method access_permitted_2 - input [1 : 0] access_permitted_2_priv; - input [11 : 0] access_permitted_2_csr_addr; - input access_permitted_2_read_not_write; - output access_permitted_2; - - // value method csr_counter_read_fault - input [1 : 0] csr_counter_read_fault_priv; - input [11 : 0] csr_counter_read_fault_csr_addr; - output csr_counter_read_fault; - - // value method csr_mip_read - output [63 : 0] csr_mip_read; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // value method interrupt_pending - input [1 : 0] interrupt_pending_cur_priv; - output [4 : 0] interrupt_pending; - - // value method wfi_resume - output wfi_resume; - - // action method nmi_req - input nmi_req_set_not_clear; - - // value method nmi_pending - output nmi_pending; - - // action method debug - input EN_debug; - output RDY_debug; - - // signals for module outputs - wire [193 : 0] csr_trap_actions; - wire [129 : 0] csr_ret_actions; - wire [64 : 0] mav_read_csr, read_csr, read_csr_port2; - wire [63 : 0] csr_mip_read, - mav_csr_write, - read_csr_mcycle, - read_csr_minstret, - read_csr_mtime, - read_mstatus, - read_satp, - read_ustatus; - wire [27 : 0] read_misa; - wire [4 : 0] interrupt_pending; - wire RDY_csr_ret_actions, - RDY_csr_trap_actions, - RDY_debug, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - access_permitted_1, - access_permitted_2, - csr_counter_read_fault, - nmi_pending, - wfi_resume; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register csr_mstatus_rg_mstatus - reg [63 : 0] csr_mstatus_rg_mstatus; - reg [63 : 0] csr_mstatus_rg_mstatus$D_IN; - wire csr_mstatus_rg_mstatus$EN; - - // register rg_dcsr - reg [31 : 0] rg_dcsr; - wire [31 : 0] rg_dcsr$D_IN; - wire rg_dcsr$EN; - - // register rg_dpc - reg [63 : 0] rg_dpc; - wire [63 : 0] rg_dpc$D_IN; - wire rg_dpc$EN; - - // register rg_dscratch0 - reg [63 : 0] rg_dscratch0; - wire [63 : 0] rg_dscratch0$D_IN; - wire rg_dscratch0$EN; - - // register rg_dscratch1 - reg [63 : 0] rg_dscratch1; - wire [63 : 0] rg_dscratch1$D_IN; - wire rg_dscratch1$EN; - - // register rg_mcause - reg [4 : 0] rg_mcause; - reg [4 : 0] rg_mcause$D_IN; - wire rg_mcause$EN; - - // register rg_mcounteren - reg [2 : 0] rg_mcounteren; - wire [2 : 0] rg_mcounteren$D_IN; - wire rg_mcounteren$EN; - - // register rg_mcycle - reg [63 : 0] rg_mcycle; - wire [63 : 0] rg_mcycle$D_IN; - wire rg_mcycle$EN; - - // register rg_mepc - reg [63 : 0] rg_mepc; - wire [63 : 0] rg_mepc$D_IN; - wire rg_mepc$EN; - - // register rg_minstret - reg [63 : 0] rg_minstret; - wire [63 : 0] rg_minstret$D_IN; - wire rg_minstret$EN; - - // register rg_mscratch - reg [63 : 0] rg_mscratch; - wire [63 : 0] rg_mscratch$D_IN; - wire rg_mscratch$EN; - - // register rg_mtval - reg [63 : 0] rg_mtval; - wire [63 : 0] rg_mtval$D_IN; - wire rg_mtval$EN; - - // register rg_mtvec - reg [62 : 0] rg_mtvec; - wire [62 : 0] rg_mtvec$D_IN; - wire rg_mtvec$EN; - - // register rg_nmi - reg rg_nmi; - wire rg_nmi$D_IN, rg_nmi$EN; - - // register rg_nmi_vector - reg [63 : 0] rg_nmi_vector; - wire [63 : 0] rg_nmi_vector$D_IN; - wire rg_nmi_vector$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_tdata1 - reg [63 : 0] rg_tdata1; - wire [63 : 0] rg_tdata1$D_IN; - wire rg_tdata1$EN; - - // register rg_tdata2 - reg [63 : 0] rg_tdata2; - wire [63 : 0] rg_tdata2$D_IN; - wire rg_tdata2$EN; - - // register rg_tdata3 - reg [63 : 0] rg_tdata3; - wire [63 : 0] rg_tdata3$D_IN; - wire rg_tdata3$EN; - - // register rg_tselect - reg [63 : 0] rg_tselect; - wire [63 : 0] rg_tselect$D_IN; - wire rg_tselect$EN; - - // ports of submodule csr_mie - wire [63 : 0] csr_mie$fav_write, csr_mie$fav_write_wordxl, csr_mie$fv_read; - wire [27 : 0] csr_mie$fav_write_misa; - wire csr_mie$EN_fav_write, csr_mie$EN_reset; - - // ports of submodule csr_mip - wire [63 : 0] csr_mip$fav_write, csr_mip$fav_write_wordxl, csr_mip$fv_read; - wire [27 : 0] csr_mip$fav_write_misa; - wire csr_mip$EN_fav_write, - csr_mip$EN_reset, - csr_mip$m_external_interrupt_req_req, - csr_mip$s_external_interrupt_req_req, - csr_mip$software_interrupt_req_req, - csr_mip$timer_interrupt_req_req; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mtvec_reset_value, - soc_map$m_nmivec_reset_value; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_mcycle_incr, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_upd_minstret_csrrx, - CAN_FIRE_RL_rl_upd_minstret_incr, - CAN_FIRE_csr_minstret_incr, - CAN_FIRE_csr_ret_actions, - CAN_FIRE_csr_trap_actions, - CAN_FIRE_debug, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_mav_csr_write, - CAN_FIRE_mav_read_csr, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_rl_mcycle_incr, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_upd_minstret_csrrx, - WILL_FIRE_RL_rl_upd_minstret_incr, - WILL_FIRE_csr_minstret_incr, - WILL_FIRE_csr_ret_actions, - WILL_FIRE_csr_trap_actions, - WILL_FIRE_debug, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_mav_csr_write, - WILL_FIRE_mav_read_csr, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_3, - MUX_rg_minstret$write_1__VAL_1, - MUX_rg_minstret$write_1__VAL_2; - wire [62 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; - wire [4 : 0] MUX_rg_mcause$write_1__VAL_2, MUX_rg_mcause$write_1__VAL_3; - wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_2, - MUX_rg_mcause$write_1__SEL_2, - MUX_rg_mcounteren$write_1__SEL_1, - MUX_rg_mepc$write_1__SEL_1, - MUX_rg_mtval$write_1__SEL_1, - MUX_rg_mtvec$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2, - MUX_rg_tdata1$write_1__SEL_1, - MUX_rw_minstret$wset_1__SEL_1; - - // remaining internal signals - reg [63 : 0] IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582, - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440, - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170, - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305; - wire [65 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d880; - wire [63 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862, - _theResult___fst__h8385, - _theResult___fst__h8586, - csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855, - exc_pc___1__h7373, - exc_pc__h7109, - exc_pc__h7320, - mask__h8406, - mask__h8423, - result__h5433, - v__h4528, - v__h4590, - v__h4746, - val__h8424, - vector_offset__h7321, - wordxl1__h4016, - x__h5891, - x__h8214, - x__h8215, - x__h8405, - x__h8418, - x__h8435, - y__h8419, - y__h8436; - wire [22 : 0] fixed_up_val_23__h4057, - fixed_up_val_23__h6519, - fixed_up_val_23__h8277; - wire [5 : 0] ie_from_x__h8369, pie_from_x__h8370; - wire [3 : 0] IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1137, - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1139, - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1141, - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1143, - exc_code__h8056; - wire [1 : 0] mpp__h7414, to_y__h8585; - wire NOT_access_permitted_1_csr_addr_ULT_0xC03_81_8_ETC___d947, - NOT_access_permitted_2_csr_addr_ULT_0xC03_52_5_ETC___d1017, - NOT_cfg_verbosity_read__49_ULE_1_50___d551, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1101, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1106, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1111, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1116, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1121, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1126, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1131, - NOT_csr_trap_actions_nmi_10_AND_csr_trap_actio_ETC___d787, - b__h8422, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1055, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1060, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1065, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1070, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1075, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1080, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1085, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1090, - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d838, - mav_csr_write_csr_addr_ULE_0x33F___d448, - mav_csr_write_csr_addr_ULE_0xB1F___d444, - mav_csr_write_csr_addr_ULT_0x323_47_OR_NOT_mav_ETC___d547, - mav_csr_write_csr_addr_ULT_0x323___d447, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d467, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d477, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d481, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d486, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d488, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d492, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d494, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d500, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d502, - mav_csr_write_csr_addr_ULT_0xB03___d443; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_csr - assign read_csr = - { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || - read_csr_csr_addr == 12'hC00 || - read_csr_csr_addr == 12'hC02 || - read_csr_csr_addr == 12'hF11 || - read_csr_csr_addr == 12'hF12 || - read_csr_csr_addr == 12'hF13 || - read_csr_csr_addr == 12'hF14 || - read_csr_csr_addr == 12'h300 || - read_csr_csr_addr == 12'h301 || - read_csr_csr_addr == 12'h304 || - read_csr_csr_addr == 12'h305 || - read_csr_csr_addr == 12'h306 || - read_csr_csr_addr == 12'h340 || - read_csr_csr_addr == 12'h341 || - read_csr_csr_addr == 12'h342 || - read_csr_csr_addr == 12'h343 || - read_csr_csr_addr == 12'h344 || - read_csr_csr_addr == 12'hB00 || - read_csr_csr_addr == 12'hB02 || - read_csr_csr_addr == 12'h7A0 || - read_csr_csr_addr == 12'h7A1 || - read_csr_csr_addr == 12'h7A2 || - read_csr_csr_addr == 12'h7A3, - (read_csr_csr_addr >= 12'hC03 && - read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hB03 && - read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'h323 && - read_csr_csr_addr <= 12'h33F) ? - 64'd0 : - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 } ; - - // value method read_csr_port2 - assign read_csr_port2 = - { read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F || - read_csr_port2_csr_addr == 12'hC00 || - read_csr_port2_csr_addr == 12'hC02 || - read_csr_port2_csr_addr == 12'hF11 || - read_csr_port2_csr_addr == 12'hF12 || - read_csr_port2_csr_addr == 12'hF13 || - read_csr_port2_csr_addr == 12'hF14 || - read_csr_port2_csr_addr == 12'h300 || - read_csr_port2_csr_addr == 12'h301 || - read_csr_port2_csr_addr == 12'h304 || - read_csr_port2_csr_addr == 12'h305 || - read_csr_port2_csr_addr == 12'h306 || - read_csr_port2_csr_addr == 12'h340 || - read_csr_port2_csr_addr == 12'h341 || - read_csr_port2_csr_addr == 12'h342 || - read_csr_port2_csr_addr == 12'h343 || - read_csr_port2_csr_addr == 12'h344 || - read_csr_port2_csr_addr == 12'hB00 || - read_csr_port2_csr_addr == 12'hB02 || - read_csr_port2_csr_addr == 12'h7A0 || - read_csr_port2_csr_addr == 12'h7A1 || - read_csr_port2_csr_addr == 12'h7A2 || - read_csr_port2_csr_addr == 12'h7A3, - (read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F) ? - 64'd0 : - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 } ; - - // actionvalue method mav_read_csr - assign mav_read_csr = - { mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F || - mav_read_csr_csr_addr == 12'hC00 || - mav_read_csr_csr_addr == 12'hC02 || - mav_read_csr_csr_addr == 12'hF11 || - mav_read_csr_csr_addr == 12'hF12 || - mav_read_csr_csr_addr == 12'hF13 || - mav_read_csr_csr_addr == 12'hF14 || - mav_read_csr_csr_addr == 12'h300 || - mav_read_csr_csr_addr == 12'h301 || - mav_read_csr_csr_addr == 12'h304 || - mav_read_csr_csr_addr == 12'h305 || - mav_read_csr_csr_addr == 12'h306 || - mav_read_csr_csr_addr == 12'h340 || - mav_read_csr_csr_addr == 12'h341 || - mav_read_csr_csr_addr == 12'h342 || - mav_read_csr_csr_addr == 12'h343 || - mav_read_csr_csr_addr == 12'h344 || - mav_read_csr_csr_addr == 12'hB00 || - mav_read_csr_csr_addr == 12'hB02 || - mav_read_csr_csr_addr == 12'h7A0 || - mav_read_csr_csr_addr == 12'h7A1 || - mav_read_csr_csr_addr == 12'h7A2 || - mav_read_csr_csr_addr == 12'h7A3, - (mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F) ? - 64'd0 : - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 } ; - assign CAN_FIRE_mav_read_csr = 1'd1 ; - assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; - - // actionvalue method mav_csr_write - assign mav_csr_write = - (!mav_csr_write_csr_addr_ULT_0xB03___d443 && - mav_csr_write_csr_addr_ULE_0xB1F___d444 || - !mav_csr_write_csr_addr_ULT_0x323___d447 && - mav_csr_write_csr_addr_ULE_0x33F___d448 || - mav_csr_write_csr_addr == 12'hF11 || - mav_csr_write_csr_addr == 12'hF12 || - mav_csr_write_csr_addr == 12'hF13 || - mav_csr_write_csr_addr == 12'hF14) ? - 64'd0 : - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 ; - assign CAN_FIRE_mav_csr_write = 1'd1 ; - assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; - - // value method read_misa - assign read_misa = 28'd135270661 ; - - // value method read_mstatus - assign read_mstatus = csr_mstatus_rg_mstatus ; - - // value method read_ustatus - assign read_ustatus = - { 59'd0, - csr_mstatus_rg_mstatus[4], - 3'd0, - csr_mstatus_rg_mstatus[0] } ; - - // value method read_satp - assign read_satp = 64'hAAAAAAAAAAAAAAAA ; - - // actionvalue method csr_trap_actions - assign csr_trap_actions = { x__h5891, x__h8214, x__h8215, 2'b11 } ; - assign RDY_csr_trap_actions = 1'd1 ; - assign CAN_FIRE_csr_trap_actions = 1'd1 ; - assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; - - // actionvalue method csr_ret_actions - assign csr_ret_actions = - { rg_mepc, - IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d880 } ; - assign RDY_csr_ret_actions = 1'd1 ; - assign CAN_FIRE_csr_ret_actions = 1'd1 ; - assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; - - // value method read_csr_minstret - assign read_csr_minstret = rg_minstret ; - - // action method csr_minstret_incr - assign CAN_FIRE_csr_minstret_incr = 1'd1 ; - assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; - - // value method read_csr_mcycle - assign read_csr_mcycle = rg_mcycle ; - - // value method read_csr_mtime - assign read_csr_mtime = rg_mcycle ; - - // value method access_permitted_1 - assign access_permitted_1 = - NOT_access_permitted_1_csr_addr_ULT_0xC03_81_8_ETC___d947 && - (access_permitted_1_read_not_write || - access_permitted_1_csr_addr[11:10] != 2'b11) ; - - // value method access_permitted_2 - assign access_permitted_2 = - NOT_access_permitted_2_csr_addr_ULT_0xC03_52_5_ETC___d1017 && - (access_permitted_2_read_not_write || - access_permitted_2_csr_addr[11:10] != 2'b11) ; - - // value method csr_counter_read_fault - assign csr_counter_read_fault = - (csr_counter_read_fault_priv == 2'b01 || - csr_counter_read_fault_priv == 2'b0) && - (csr_counter_read_fault_csr_addr == 12'hC00 && - !rg_mcounteren[0] || - csr_counter_read_fault_csr_addr == 12'hC01 && - !rg_mcounteren[1] || - csr_counter_read_fault_csr_addr == 12'hC02 && - !rg_mcounteren[2] || - csr_counter_read_fault_csr_addr >= 12'hC03 && - csr_counter_read_fault_csr_addr <= 12'hC1F) ; - - // value method csr_mip_read - assign csr_mip_read = csr_mip$fv_read ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // value method interrupt_pending - assign interrupt_pending = - { csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1090, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1131 ? - 4'd4 : - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1143 } ; - - // value method wfi_resume - assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 64'd0 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // value method nmi_pending - assign nmi_pending = rg_nmi ; - - // action method debug - assign RDY_debug = 1'd1 ; - assign CAN_FIRE_debug = 1'd1 ; - assign WILL_FIRE_debug = EN_debug ; - - // submodule csr_mie - mkCSR_MIE csr_mie(.CLK(CLK), - .RST_N(RST_N), - .fav_write_misa(csr_mie$fav_write_misa), - .fav_write_wordxl(csr_mie$fav_write_wordxl), - .EN_reset(csr_mie$EN_reset), - .EN_fav_write(csr_mie$EN_fav_write), - .fv_read(csr_mie$fv_read), - .fav_write(csr_mie$fav_write)); - - // submodule csr_mip - mkCSR_MIP csr_mip(.CLK(CLK), - .RST_N(RST_N), - .fav_write_misa(csr_mip$fav_write_misa), - .fav_write_wordxl(csr_mip$fav_write_wordxl), - .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), - .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), - .software_interrupt_req_req(csr_mip$software_interrupt_req_req), - .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), - .EN_reset(csr_mip$EN_reset), - .EN_fav_write(csr_mip$EN_fav_write), - .fv_read(csr_mip$fv_read), - .fav_write(csr_mip$fav_write)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), - .m_nmivec_reset_value(soc_map$m_nmivec_reset_value)); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = !rg_state ; - assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_mcycle_incr - assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; - assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; - - // rule RL_rl_upd_minstret_csrrx - assign CAN_FIRE_RL_rl_upd_minstret_csrrx = - MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; - assign WILL_FIRE_RL_rl_upd_minstret_csrrx = - CAN_FIRE_RL_rl_upd_minstret_csrrx ; - - // rule RL_rl_upd_minstret_incr - assign CAN_FIRE_RL_rl_upd_minstret_incr = - !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; - assign WILL_FIRE_RL_rl_upd_minstret_incr = - CAN_FIRE_RL_rl_upd_minstret_incr ; - - // inputs to muxes for submodule ports - assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453 ; - assign MUX_rg_mcause$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d481 ; - assign MUX_rg_mcounteren$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474 ; - assign MUX_rg_mepc$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479 ; - assign MUX_rg_mtval$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d486 ; - assign MUX_rg_mtvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; - assign MUX_rg_tdata1$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496 ; - assign MUX_rw_minstret$wset_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d492 ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 = - { 41'd1024, fixed_up_val_23__h8277 } ; - assign MUX_rg_mcause$write_1__VAL_2 = - { mav_csr_write_word[63], mav_csr_write_word[3:0] } ; - assign MUX_rg_mcause$write_1__VAL_3 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - exc_code__h8056 } ; - assign MUX_rg_minstret$write_1__VAL_1 = - MUX_rw_minstret$wset_1__SEL_1 ? mav_csr_write_word : 64'd0 ; - assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; - assign MUX_rg_mtvec$write_1__VAL_1 = - { mav_csr_write_word[63:2], mav_csr_write_word[0] } ; - assign MUX_rg_mtvec$write_1__VAL_2 = - { soc_map$m_mtvec_reset_value[63:2], - soc_map$m_mtvec_reset_value[0] } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register csr_mstatus_rg_mstatus - always@(WILL_FIRE_RL_rl_reset_start or - MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 or - wordxl1__h4016 or - EN_csr_ret_actions or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 or - EN_csr_trap_actions or x__h8214) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: - csr_mstatus_rg_mstatus$D_IN = 64'h0000000200000000; - MUX_csr_mstatus_rg_mstatus$write_1__SEL_2: - csr_mstatus_rg_mstatus$D_IN = wordxl1__h4016; - EN_csr_ret_actions: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_3; - EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = x__h8214; - default: csr_mstatus_rg_mstatus$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign csr_mstatus_rg_mstatus$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453 || - EN_csr_trap_actions || - EN_csr_ret_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_dcsr - assign rg_dcsr$D_IN = 32'h0 ; - assign rg_dcsr$EN = 1'b0 ; - - // register rg_dpc - assign rg_dpc$D_IN = 64'h0 ; - assign rg_dpc$EN = 1'b0 ; - - // register rg_dscratch0 - assign rg_dscratch0$D_IN = 64'h0 ; - assign rg_dscratch0$EN = 1'b0 ; - - // register rg_dscratch1 - assign rg_dscratch1$D_IN = 64'h0 ; - assign rg_dscratch1$EN = 1'b0 ; - - // register rg_mcause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_mcause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - EN_csr_trap_actions or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; - MUX_rg_mcause$write_1__SEL_2: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; - EN_csr_trap_actions: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_mcause$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d481 || - EN_csr_trap_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcounteren - assign rg_mcounteren$D_IN = - MUX_rg_mcounteren$write_1__SEL_1 ? - mav_csr_write_word[2:0] : - 3'd0 ; - assign rg_mcounteren$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcycle - assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; - assign rg_mcycle$EN = 1'd1 ; - - // register rg_mepc - assign rg_mepc$D_IN = - MUX_rg_mepc$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_pc ; - assign rg_mepc$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479 || - EN_csr_trap_actions ; - - // register rg_minstret - assign rg_minstret$D_IN = - WILL_FIRE_RL_rl_upd_minstret_csrrx ? - MUX_rg_minstret$write_1__VAL_1 : - MUX_rg_minstret$write_1__VAL_2 ; - assign rg_minstret$EN = - WILL_FIRE_RL_rl_upd_minstret_csrrx || - WILL_FIRE_RL_rl_upd_minstret_incr ; - - // register rg_mscratch - assign rg_mscratch$D_IN = mav_csr_write_word ; - assign rg_mscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d477 ; - - // register rg_mtval - assign rg_mtval$D_IN = - MUX_rg_mtval$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_xtval ; - assign rg_mtval$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d486 || - EN_csr_trap_actions ; - - // register rg_mtvec - assign rg_mtvec$D_IN = - MUX_rg_mtvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_mtvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_nmi - assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ; - assign rg_nmi$EN = 1'b1 ; - - // register rg_nmi_vector - assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value ; - assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_state - assign rg_state$D_IN = !EN_server_reset_request_put ; - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata1 - assign rg_tdata1$D_IN = - MUX_rg_tdata1$write_1__SEL_1 ? result__h5433 : 64'd0 ; - assign rg_tdata1$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata2 - assign rg_tdata2$D_IN = mav_csr_write_word ; - assign rg_tdata2$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d500 ; - - // register rg_tdata3 - assign rg_tdata3$D_IN = mav_csr_write_word ; - assign rg_tdata3$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d502 ; - - // register rg_tselect - assign rg_tselect$D_IN = 64'd0 ; - assign rg_tselect$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d494 || - WILL_FIRE_RL_rl_reset_start ; - - // submodule csr_mie - assign csr_mie$fav_write_misa = 28'd135270661 ; - assign csr_mie$fav_write_wordxl = mav_csr_write_word ; - assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mie$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d467 ; - - // submodule csr_mip - assign csr_mip$fav_write_misa = 28'd135270661 ; - assign csr_mip$fav_write_wordxl = mav_csr_write_word ; - assign csr_mip$m_external_interrupt_req_req = - m_external_interrupt_req_set_not_clear ; - assign csr_mip$s_external_interrupt_req_req = - s_external_interrupt_req_set_not_clear ; - assign csr_mip$software_interrupt_req_req = - software_interrupt_req_set_not_clear ; - assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; - assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mip$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d488 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1137 = - (!csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ? - 4'd3 : - 4'd11 ; - assign IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1139 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1106 ? - 4'd9 : - (NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1101 ? - 4'd7 : - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1137) ; - assign IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1141 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1116 ? - 4'd5 : - (NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1111 ? - 4'd1 : - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1139) ; - assign IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1143 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1126 ? - 4'd0 : - (NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1121 ? - 4'd8 : - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1141) ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862 = - (csr_ret_actions_from_priv == 2'b11) ? - _theResult___fst__h8385 : - _theResult___fst__h8586 ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d880 = - (csr_ret_actions_from_priv == 2'b11) ? - { csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[12:11], - _theResult___fst__h8385 } : - { to_y__h8585, _theResult___fst__h8586 } ; - assign NOT_access_permitted_1_csr_addr_ULT_0xC03_81_8_ETC___d947 = - (access_permitted_1_csr_addr >= 12'hC03 && - access_permitted_1_csr_addr <= 12'hC1F || - access_permitted_1_csr_addr >= 12'hB03 && - access_permitted_1_csr_addr <= 12'hB1F || - access_permitted_1_csr_addr >= 12'h323 && - access_permitted_1_csr_addr <= 12'h33F || - access_permitted_1_csr_addr == 12'hC00 || - access_permitted_1_csr_addr == 12'hC02 || - access_permitted_1_csr_addr == 12'hF11 || - access_permitted_1_csr_addr == 12'hF12 || - access_permitted_1_csr_addr == 12'hF13 || - access_permitted_1_csr_addr == 12'hF14 || - access_permitted_1_csr_addr == 12'h300 || - access_permitted_1_csr_addr == 12'h301 || - access_permitted_1_csr_addr == 12'h304 || - access_permitted_1_csr_addr == 12'h305 || - access_permitted_1_csr_addr == 12'h306 || - access_permitted_1_csr_addr == 12'h340 || - access_permitted_1_csr_addr == 12'h341 || - access_permitted_1_csr_addr == 12'h342 || - access_permitted_1_csr_addr == 12'h343 || - access_permitted_1_csr_addr == 12'h344 || - access_permitted_1_csr_addr == 12'hB00 || - access_permitted_1_csr_addr == 12'hB02 || - access_permitted_1_csr_addr == 12'h7A0 || - access_permitted_1_csr_addr == 12'h7A1 || - access_permitted_1_csr_addr == 12'h7A2 || - access_permitted_1_csr_addr == 12'h7A3) && - access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && - (access_permitted_1_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_access_permitted_2_csr_addr_ULT_0xC03_52_5_ETC___d1017 = - (access_permitted_2_csr_addr >= 12'hC03 && - access_permitted_2_csr_addr <= 12'hC1F || - access_permitted_2_csr_addr >= 12'hB03 && - access_permitted_2_csr_addr <= 12'hB1F || - access_permitted_2_csr_addr >= 12'h323 && - access_permitted_2_csr_addr <= 12'h33F || - access_permitted_2_csr_addr == 12'hC00 || - access_permitted_2_csr_addr == 12'hC02 || - access_permitted_2_csr_addr == 12'hF11 || - access_permitted_2_csr_addr == 12'hF12 || - access_permitted_2_csr_addr == 12'hF13 || - access_permitted_2_csr_addr == 12'hF14 || - access_permitted_2_csr_addr == 12'h300 || - access_permitted_2_csr_addr == 12'h301 || - access_permitted_2_csr_addr == 12'h304 || - access_permitted_2_csr_addr == 12'h305 || - access_permitted_2_csr_addr == 12'h306 || - access_permitted_2_csr_addr == 12'h340 || - access_permitted_2_csr_addr == 12'h341 || - access_permitted_2_csr_addr == 12'h342 || - access_permitted_2_csr_addr == 12'h343 || - access_permitted_2_csr_addr == 12'h344 || - access_permitted_2_csr_addr == 12'hB00 || - access_permitted_2_csr_addr == 12'hB02 || - access_permitted_2_csr_addr == 12'h7A0 || - access_permitted_2_csr_addr == 12'h7A1 || - access_permitted_2_csr_addr == 12'h7A2 || - access_permitted_2_csr_addr == 12'h7A3) && - access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && - (access_permitted_2_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_cfg_verbosity_read__49_ULE_1_50___d551 = cfg_verbosity > 4'd1 ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1101 = - (!csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) && - (!csr_mip$fv_read[3] || !csr_mie$fv_read[3] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1106 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1101 && - (!csr_mip$fv_read[7] || !csr_mie$fv_read[7] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1111 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1106 && - (!csr_mip$fv_read[9] || !csr_mie$fv_read[9] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1116 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1111 && - (!csr_mip$fv_read[1] || !csr_mie$fv_read[1] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1121 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1116 && - (!csr_mip$fv_read[5] || !csr_mie$fv_read[5] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1126 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1121 && - (!csr_mip$fv_read[8] || !csr_mie$fv_read[8] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1131 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1126 && - (!csr_mip$fv_read[0] || !csr_mie$fv_read[0] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_trap_actions_nmi_10_AND_csr_trap_actio_ETC___d787 = - !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8056 != 4'd0 && - exc_code__h8056 != 4'd1 && - exc_code__h8056 != 4'd2 && - exc_code__h8056 != 4'd3 && - exc_code__h8056 != 4'd4 && - exc_code__h8056 != 4'd5 && - exc_code__h8056 != 4'd6 && - exc_code__h8056 != 4'd7 && - exc_code__h8056 != 4'd8 && - exc_code__h8056 != 4'd9 && - exc_code__h8056 != 4'd10 && - exc_code__h8056 != 4'd11 ; - assign _theResult___fst__h8385 = - { csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[63:13], - 2'd0, - csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[10:0] } ; - assign _theResult___fst__h8586 = - { csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[63:9], - 1'd0, - csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[7:0] } ; - assign b__h8422 = csr_mstatus_rg_mstatus[pie_from_x__h8370] ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1055 = - csr_mip$fv_read[11] && csr_mie$fv_read[11] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) || - csr_mip$fv_read[3] && csr_mie$fv_read[3] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1060 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1055 || - csr_mip$fv_read[7] && csr_mie$fv_read[7] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1065 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1060 || - csr_mip$fv_read[9] && csr_mie$fv_read[9] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1070 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1065 || - csr_mip$fv_read[1] && csr_mie$fv_read[1] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1075 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1070 || - csr_mip$fv_read[5] && csr_mie$fv_read[5] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1080 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1075 || - csr_mip$fv_read[8] && csr_mie$fv_read[8] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1085 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1080 || - csr_mip$fv_read[0] && csr_mie$fv_read[0] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1090 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1085 || - csr_mip$fv_read[4] && csr_mie$fv_read[4] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855 = - x__h8418 | mask__h8406 ; - assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d838 = - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 != 4'd0 && - exc_code__h8056 != 4'd1 && - exc_code__h8056 != 4'd2 && - exc_code__h8056 != 4'd3 && - exc_code__h8056 != 4'd4 && - exc_code__h8056 != 4'd5 && - exc_code__h8056 != 4'd6 && - exc_code__h8056 != 4'd7 && - exc_code__h8056 != 4'd8 && - exc_code__h8056 != 4'd9 && - exc_code__h8056 != 4'd11 && - exc_code__h8056 != 4'd12 && - exc_code__h8056 != 4'd13 && - exc_code__h8056 != 4'd15 ; - assign exc_code__h8056 = - csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; - assign exc_pc___1__h7373 = exc_pc__h7320 + vector_offset__h7321 ; - assign exc_pc__h7109 = { rg_mtvec[62:1], 2'd0 } ; - assign exc_pc__h7320 = - csr_trap_actions_nmi ? rg_nmi_vector : exc_pc__h7109 ; - assign fixed_up_val_23__h4057 = - { mav_csr_write_word[22:17], - 4'd0, - (mav_csr_write_word[12:11] == 2'b11) ? - mav_csr_write_word[12:11] : - 2'b0, - mav_csr_write_word[10:9], - 1'd0, - mav_csr_write_word[7:6], - 2'd0, - mav_csr_write_word[3:2], - 2'd0 } ; - assign fixed_up_val_23__h6519 = - { csr_mstatus_rg_mstatus[22:17], - 4'd0, - mpp__h7414, - csr_mstatus_rg_mstatus[10:9], - 1'd0, - csr_mstatus_rg_mstatus[3], - csr_mstatus_rg_mstatus[6], - 3'd0, - csr_mstatus_rg_mstatus[2], - 2'd0 } ; - assign fixed_up_val_23__h8277 = - { IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[22:17], - 4'd0, - (IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[12:11] == - 2'b11) ? - IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[12:11] : - 2'b0, - IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[10:9], - 1'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[7:6], - 2'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[3:2], - 2'd0 } ; - assign ie_from_x__h8369 = { 4'd0, csr_ret_actions_from_priv } ; - assign mask__h8406 = 64'd1 << pie_from_x__h8370 ; - assign mask__h8423 = 64'd1 << ie_from_x__h8369 ; - assign mav_csr_write_csr_addr_ULE_0x33F___d448 = - mav_csr_write_csr_addr <= 12'h33F ; - assign mav_csr_write_csr_addr_ULE_0xB1F___d444 = - mav_csr_write_csr_addr <= 12'hB1F ; - assign mav_csr_write_csr_addr_ULT_0x323_47_OR_NOT_mav_ETC___d547 = - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr != 12'hF11 && - mav_csr_write_csr_addr != 12'hF12 && - mav_csr_write_csr_addr != 12'hF13 && - mav_csr_write_csr_addr != 12'hF14 && - mav_csr_write_csr_addr != 12'h300 && - mav_csr_write_csr_addr != 12'h301 && - mav_csr_write_csr_addr != 12'h304 && - mav_csr_write_csr_addr != 12'h305 && - mav_csr_write_csr_addr != 12'h306 && - mav_csr_write_csr_addr != 12'h340 && - mav_csr_write_csr_addr != 12'h341 && - mav_csr_write_csr_addr != 12'h342 && - mav_csr_write_csr_addr != 12'h343 && - mav_csr_write_csr_addr != 12'h344 && - mav_csr_write_csr_addr != 12'hB00 && - mav_csr_write_csr_addr != 12'hB02 && - mav_csr_write_csr_addr != 12'h7A0 && - mav_csr_write_csr_addr != 12'h7A1 && - mav_csr_write_csr_addr != 12'h7A2 && - mav_csr_write_csr_addr != 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0x323___d447 = - mav_csr_write_csr_addr < 12'h323 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h300 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d467 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h304 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h305 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h306 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d477 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h340 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h341 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d481 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h342 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d486 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h343 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d488 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h344 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d492 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'hB02 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d494 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h7A0 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h7A1 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d500 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h7A2 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d502 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0xB03___d443 = - mav_csr_write_csr_addr < 12'hB03 ; - assign mpp__h7414 = - (csr_trap_actions_from_priv == 2'b11) ? - csr_trap_actions_from_priv : - 2'b0 ; - assign pie_from_x__h8370 = { 4'd1, csr_ret_actions_from_priv } ; - assign result__h5433 = { 4'd0, mav_csr_write_word[59:0] } ; - assign to_y__h8585 = - { 1'b0, - csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[8] } ; - assign v__h4528 = - { mav_csr_write_word[63:2], 1'b0, mav_csr_write_word[0] } ; - assign v__h4590 = { 61'd0, mav_csr_write_word[2:0] } ; - assign v__h4746 = - { mav_csr_write_word[63], 59'd0, mav_csr_write_word[3:0] } ; - assign val__h8424 = { 63'd0, b__h8422 } << ie_from_x__h8369 ; - assign vector_offset__h7321 = { 58'd0, csr_trap_actions_exc_code, 2'd0 } ; - assign wordxl1__h4016 = { 41'd1024, fixed_up_val_23__h4057 } ; - assign x__h5891 = - (csr_trap_actions_interrupt && !csr_trap_actions_nmi && - rg_mtvec[0]) ? - exc_pc___1__h7373 : - exc_pc__h7320 ; - assign x__h8214 = { 41'd1024, fixed_up_val_23__h6519 } ; - assign x__h8215 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - 59'd0, - exc_code__h8056 } ; - assign x__h8405 = x__h8435 | val__h8424 ; - assign x__h8418 = x__h8405 & y__h8419 ; - assign x__h8435 = csr_mstatus_rg_mstatus & y__h8436 ; - assign y__h8419 = ~mask__h8406 ; - assign y__h8436 = ~mask__h8423 ; - always@(read_csr_port2_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_port2_csr_addr) - 12'h300: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - 64'h8000000000101105; - 12'h304: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_mscratch; - 12'h341: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = rg_mepc; - 12'h342: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_mtval; - 12'h344: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_tselect; - 12'h7A1: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_tdata1; - 12'h7A2: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_minstret; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = 64'd0; - default: IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_tdata3; - endcase - end - always@(read_csr_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_csr_addr) - 12'h300: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - 64'h8000000000101105; - 12'h304: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_mscratch; - 12'h341: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = rg_mepc; - 12'h342: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_mtval; - 12'h344: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_tselect; - 12'h7A1: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_tdata1; - 12'h7A2: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_minstret; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = 64'd0; - default: IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_tdata3; - endcase - end - always@(mav_read_csr_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (mav_read_csr_csr_addr) - 12'h300: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - 64'h8000000000101105; - 12'h304: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - csr_mie$fv_read; - 12'h305: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_mscratch; - 12'h341: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = rg_mepc; - 12'h342: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_mtval; - 12'h344: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - csr_mip$fv_read; - 12'h7A0: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_tselect; - 12'h7A1: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_tdata1; - 12'h7A2: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_minstret; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = 64'd0; - default: IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_tdata3; - endcase - end - always@(mav_csr_write_csr_addr or - wordxl1__h4016 or - csr_mie$fav_write or - v__h4528 or - v__h4590 or - mav_csr_write_word or - v__h4746 or csr_mip$fav_write or result__h5433) - begin - case (mav_csr_write_csr_addr) - 12'h300: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - wordxl1__h4016; - 12'h301, 12'h7A0: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = 64'd0; - 12'h304: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - csr_mie$fav_write; - 12'h305: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - v__h4528; - 12'h306: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - v__h4590; - 12'h340, 12'h341, 12'h343, 12'h7A2, 12'h7A3, 12'hB00, 12'hB02: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - mav_csr_write_word; - 12'h342: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - v__h4746; - 12'h344: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - csr_mip$fav_write; - 12'h7A1: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - result__h5433; - default: IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 64'h0000000200000000; - rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (csr_mstatus_rg_mstatus$EN) - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY - csr_mstatus_rg_mstatus$D_IN; - if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; - if (rg_minstret$EN) - rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; - if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; - if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; - if (rg_dscratch0$EN) - rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; - if (rg_dscratch1$EN) - rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; - if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; - if (rg_mcounteren$EN) - rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; - if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; - if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; - if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; - if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; - if (rg_nmi_vector$EN) - rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN; - if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; - if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; - if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; - if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - csr_mstatus_rg_mstatus = 64'hAAAAAAAAAAAAAAAA; - rg_dcsr = 32'hAAAAAAAA; - rg_dpc = 64'hAAAAAAAAAAAAAAAA; - rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA; - rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA; - rg_mcause = 5'h0A; - rg_mcounteren = 3'h2; - rg_mcycle = 64'hAAAAAAAAAAAAAAAA; - rg_mepc = 64'hAAAAAAAAAAAAAAAA; - rg_minstret = 64'hAAAAAAAAAAAAAAAA; - rg_mscratch = 64'hAAAAAAAAAAAAAAAA; - rg_mtval = 64'hAAAAAAAAAAAAAAAA; - rg_mtvec = 63'h2AAAAAAAAAAAAAAA; - rg_nmi = 1'h0; - rg_nmi_vector = 64'hAAAAAAAAAAAAAAAA; - rg_state = 1'h0; - rg_tdata1 = 64'hAAAAAAAAAAAAAAAA; - rg_tdata2 = 64'hAAAAAAAAAAAAAAAA; - rg_tdata3 = 64'hAAAAAAAAAAAAAAAA; - rg_tselect = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" priv %0d: ", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" edeleg: 0x%0h", 16'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" ideleg: 0x%0h", 12'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd10 && - rg_mcause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd11 && - rg_mcause[3:0] != 4'd12 && - rg_mcause[3:0] != 4'd13 && - rg_mcause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" status: 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" tvec: 0x%0h", { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" epc: 0x%0h", rg_mepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" tval: 0x%0h", rg_mtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" Return: new pc 0x%0h ", x__h5891); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" new mstatus:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write("MStatus{", "sd:%0d", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" sxl:%0d uxl:%0d", 2'd0, 2'd2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" tsr:%0d", csr_mstatus_rg_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" tw:%0d", csr_mstatus_rg_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" tvm:%0d", csr_mstatus_rg_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" mxr:%0d", csr_mstatus_rg_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" sum:%0d", csr_mstatus_rg_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" mprv:%0d", csr_mstatus_rg_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" xs:%0d", 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" fs:%0d", 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" mpp:%0d", mpp__h7414); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" spp:%0d", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" pies:%0d_%0d%0d", csr_mstatus_rg_mstatus[3], 1'd0, 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" ies:%0d_%0d%0d", 1'd0, 1'd0, 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" new xcause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - NOT_csr_trap_actions_nmi_10_AND_csr_trap_actio_ETC___d787) - $write("unknown interrupt Exc_Code %d", exc_code__h8056); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d838) - $write("unknown trap Exc_Code %d", exc_code__h8056); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" new priv %0d", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mav_csr_write && - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - mav_csr_write_csr_addr_ULT_0x323_47_OR_NOT_mav_ETC___d547 && - NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", - rg_mcycle, - mav_csr_write_csr_addr, - mav_csr_write_word); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", - rg_mcycle, - m_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", - rg_mcycle, - s_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: CSR_RegFile: software_interrupt_req: %x", - rg_mcycle, - software_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: CSR_RegFile: timer_interrupt_req: %x", - rg_mcycle, - timer_interrupt_req_set_not_clear); - end - // synopsys translate_on -endmodule // mkCSR_RegFile - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCore.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCore.v deleted file mode 100644 index d4c0ffcf..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkCore.v +++ /dev/null @@ -1,2497 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// cpu_reset_server_response_get O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg -// cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg -// cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg -// cpu_imem_master_bready O 1 -// cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg -// cpu_imem_master_rready O 1 -// cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg -// cpu_dmem_master_awaddr O 64 reg -// cpu_dmem_master_awlen O 8 reg -// cpu_dmem_master_awsize O 3 reg -// cpu_dmem_master_awburst O 2 reg -// cpu_dmem_master_awlock O 1 reg -// cpu_dmem_master_awcache O 4 reg -// cpu_dmem_master_awprot O 3 reg -// cpu_dmem_master_awqos O 4 reg -// cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg -// cpu_dmem_master_wdata O 64 reg -// cpu_dmem_master_wstrb O 8 reg -// cpu_dmem_master_wlast O 1 reg -// cpu_dmem_master_bready O 1 reg -// cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg -// cpu_dmem_master_araddr O 64 reg -// cpu_dmem_master_arlen O 8 reg -// cpu_dmem_master_arsize O 3 reg -// cpu_dmem_master_arburst O 2 reg -// cpu_dmem_master_arlock O 1 reg -// cpu_dmem_master_arcache O 4 reg -// cpu_dmem_master_arprot O 3 reg -// cpu_dmem_master_arqos O 4 reg -// cpu_dmem_master_arregion O 4 reg -// cpu_dmem_master_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// cpu_reset_server_request_put I 1 reg -// cpu_imem_master_awready I 1 -// cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg -// cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg -// cpu_dmem_master_awready I 1 -// cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg -// cpu_dmem_master_bresp I 2 reg -// cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg -// cpu_dmem_master_rdata I 64 reg -// cpu_dmem_master_rresp I 2 reg -// cpu_dmem_master_rlast I 1 reg -// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// nmi_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCore(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - cpu_reset_server_request_put, - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, - - cpu_imem_master_awvalid, - - cpu_imem_master_awid, - - cpu_imem_master_awaddr, - - cpu_imem_master_awlen, - - cpu_imem_master_awsize, - - cpu_imem_master_awburst, - - cpu_imem_master_awlock, - - cpu_imem_master_awcache, - - cpu_imem_master_awprot, - - cpu_imem_master_awqos, - - cpu_imem_master_awregion, - - cpu_imem_master_awready, - - cpu_imem_master_wvalid, - - cpu_imem_master_wid, - - cpu_imem_master_wdata, - - cpu_imem_master_wstrb, - - cpu_imem_master_wlast, - - cpu_imem_master_wready, - - cpu_imem_master_bvalid, - cpu_imem_master_bid, - cpu_imem_master_bresp, - - cpu_imem_master_bready, - - cpu_imem_master_arvalid, - - cpu_imem_master_arid, - - cpu_imem_master_araddr, - - cpu_imem_master_arlen, - - cpu_imem_master_arsize, - - cpu_imem_master_arburst, - - cpu_imem_master_arlock, - - cpu_imem_master_arcache, - - cpu_imem_master_arprot, - - cpu_imem_master_arqos, - - cpu_imem_master_arregion, - - cpu_imem_master_arready, - - cpu_imem_master_rvalid, - cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast, - - cpu_imem_master_rready, - - cpu_dmem_master_awvalid, - - cpu_dmem_master_awid, - - cpu_dmem_master_awaddr, - - cpu_dmem_master_awlen, - - cpu_dmem_master_awsize, - - cpu_dmem_master_awburst, - - cpu_dmem_master_awlock, - - cpu_dmem_master_awcache, - - cpu_dmem_master_awprot, - - cpu_dmem_master_awqos, - - cpu_dmem_master_awregion, - - cpu_dmem_master_awready, - - cpu_dmem_master_wvalid, - - cpu_dmem_master_wid, - - cpu_dmem_master_wdata, - - cpu_dmem_master_wstrb, - - cpu_dmem_master_wlast, - - cpu_dmem_master_wready, - - cpu_dmem_master_bvalid, - cpu_dmem_master_bid, - cpu_dmem_master_bresp, - - cpu_dmem_master_bready, - - cpu_dmem_master_arvalid, - - cpu_dmem_master_arid, - - cpu_dmem_master_araddr, - - cpu_dmem_master_arlen, - - cpu_dmem_master_arsize, - - cpu_dmem_master_arburst, - - cpu_dmem_master_arlock, - - cpu_dmem_master_arcache, - - cpu_dmem_master_arprot, - - cpu_dmem_master_arqos, - - cpu_dmem_master_arregion, - - cpu_dmem_master_arready, - - cpu_dmem_master_rvalid, - cpu_dmem_master_rid, - cpu_dmem_master_rdata, - cpu_dmem_master_rresp, - cpu_dmem_master_rlast, - - cpu_dmem_master_rready, - - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - - nmi_req_set_not_clear); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method cpu_reset_server_request_put - input cpu_reset_server_request_put; - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // actionvalue method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; - - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; - - // value method cpu_imem_master_m_awaddr - output [63 : 0] cpu_imem_master_awaddr; - - // value method cpu_imem_master_m_awlen - output [7 : 0] cpu_imem_master_awlen; - - // value method cpu_imem_master_m_awsize - output [2 : 0] cpu_imem_master_awsize; - - // value method cpu_imem_master_m_awburst - output [1 : 0] cpu_imem_master_awburst; - - // value method cpu_imem_master_m_awlock - output cpu_imem_master_awlock; - - // value method cpu_imem_master_m_awcache - output [3 : 0] cpu_imem_master_awcache; - - // value method cpu_imem_master_m_awprot - output [2 : 0] cpu_imem_master_awprot; - - // value method cpu_imem_master_m_awqos - output [3 : 0] cpu_imem_master_awqos; - - // value method cpu_imem_master_m_awregion - output [3 : 0] cpu_imem_master_awregion; - - // value method cpu_imem_master_m_awuser - - // action method cpu_imem_master_m_awready - input cpu_imem_master_awready; - - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; - - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - - // value method cpu_imem_master_m_wdata - output [63 : 0] cpu_imem_master_wdata; - - // value method cpu_imem_master_m_wstrb - output [7 : 0] cpu_imem_master_wstrb; - - // value method cpu_imem_master_m_wlast - output cpu_imem_master_wlast; - - // value method cpu_imem_master_m_wuser - - // action method cpu_imem_master_m_wready - input cpu_imem_master_wready; - - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; - input [1 : 0] cpu_imem_master_bresp; - - // value method cpu_imem_master_m_bready - output cpu_imem_master_bready; - - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; - - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; - - // value method cpu_imem_master_m_araddr - output [63 : 0] cpu_imem_master_araddr; - - // value method cpu_imem_master_m_arlen - output [7 : 0] cpu_imem_master_arlen; - - // value method cpu_imem_master_m_arsize - output [2 : 0] cpu_imem_master_arsize; - - // value method cpu_imem_master_m_arburst - output [1 : 0] cpu_imem_master_arburst; - - // value method cpu_imem_master_m_arlock - output cpu_imem_master_arlock; - - // value method cpu_imem_master_m_arcache - output [3 : 0] cpu_imem_master_arcache; - - // value method cpu_imem_master_m_arprot - output [2 : 0] cpu_imem_master_arprot; - - // value method cpu_imem_master_m_arqos - output [3 : 0] cpu_imem_master_arqos; - - // value method cpu_imem_master_m_arregion - output [3 : 0] cpu_imem_master_arregion; - - // value method cpu_imem_master_m_aruser - - // action method cpu_imem_master_m_arready - input cpu_imem_master_arready; - - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; - input [63 : 0] cpu_imem_master_rdata; - input [1 : 0] cpu_imem_master_rresp; - input cpu_imem_master_rlast; - - // value method cpu_imem_master_m_rready - output cpu_imem_master_rready; - - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; - - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; - - // value method cpu_dmem_master_m_awaddr - output [63 : 0] cpu_dmem_master_awaddr; - - // value method cpu_dmem_master_m_awlen - output [7 : 0] cpu_dmem_master_awlen; - - // value method cpu_dmem_master_m_awsize - output [2 : 0] cpu_dmem_master_awsize; - - // value method cpu_dmem_master_m_awburst - output [1 : 0] cpu_dmem_master_awburst; - - // value method cpu_dmem_master_m_awlock - output cpu_dmem_master_awlock; - - // value method cpu_dmem_master_m_awcache - output [3 : 0] cpu_dmem_master_awcache; - - // value method cpu_dmem_master_m_awprot - output [2 : 0] cpu_dmem_master_awprot; - - // value method cpu_dmem_master_m_awqos - output [3 : 0] cpu_dmem_master_awqos; - - // value method cpu_dmem_master_m_awregion - output [3 : 0] cpu_dmem_master_awregion; - - // value method cpu_dmem_master_m_awuser - - // action method cpu_dmem_master_m_awready - input cpu_dmem_master_awready; - - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; - - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - - // value method cpu_dmem_master_m_wdata - output [63 : 0] cpu_dmem_master_wdata; - - // value method cpu_dmem_master_m_wstrb - output [7 : 0] cpu_dmem_master_wstrb; - - // value method cpu_dmem_master_m_wlast - output cpu_dmem_master_wlast; - - // value method cpu_dmem_master_m_wuser - - // action method cpu_dmem_master_m_wready - input cpu_dmem_master_wready; - - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; - input [1 : 0] cpu_dmem_master_bresp; - - // value method cpu_dmem_master_m_bready - output cpu_dmem_master_bready; - - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; - - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; - - // value method cpu_dmem_master_m_araddr - output [63 : 0] cpu_dmem_master_araddr; - - // value method cpu_dmem_master_m_arlen - output [7 : 0] cpu_dmem_master_arlen; - - // value method cpu_dmem_master_m_arsize - output [2 : 0] cpu_dmem_master_arsize; - - // value method cpu_dmem_master_m_arburst - output [1 : 0] cpu_dmem_master_arburst; - - // value method cpu_dmem_master_m_arlock - output cpu_dmem_master_arlock; - - // value method cpu_dmem_master_m_arcache - output [3 : 0] cpu_dmem_master_arcache; - - // value method cpu_dmem_master_m_arprot - output [2 : 0] cpu_dmem_master_arprot; - - // value method cpu_dmem_master_m_arqos - output [3 : 0] cpu_dmem_master_arqos; - - // value method cpu_dmem_master_m_arregion - output [3 : 0] cpu_dmem_master_arregion; - - // value method cpu_dmem_master_m_aruser - - // action method cpu_dmem_master_m_arready - input cpu_dmem_master_arready; - - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; - input [63 : 0] cpu_dmem_master_rdata; - input [1 : 0] cpu_dmem_master_rresp; - input cpu_dmem_master_rlast; - - // value method cpu_dmem_master_m_rready - output cpu_dmem_master_rready; - - // action method core_external_interrupt_sources_0_m_interrupt_req - input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_1_m_interrupt_req - input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_2_m_interrupt_req - input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_3_m_interrupt_req - input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_4_m_interrupt_req - input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_5_m_interrupt_req - input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_6_m_interrupt_req - input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_7_m_interrupt_req - input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_8_m_interrupt_req - input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_9_m_interrupt_req - input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_10_m_interrupt_req - input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_11_m_interrupt_req - input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_12_m_interrupt_req - input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_13_m_interrupt_req - input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_14_m_interrupt_req - input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_15_m_interrupt_req - input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // signals for module outputs - wire [63 : 0] cpu_dmem_master_araddr, - cpu_dmem_master_awaddr, - cpu_dmem_master_wdata, - cpu_imem_master_araddr, - cpu_imem_master_awaddr, - cpu_imem_master_wdata; - wire [7 : 0] cpu_dmem_master_arlen, - cpu_dmem_master_awlen, - cpu_dmem_master_wstrb, - cpu_imem_master_arlen, - cpu_imem_master_awlen, - cpu_imem_master_wstrb; - wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, - cpu_dmem_master_arqos, - cpu_dmem_master_arregion, - cpu_dmem_master_awcache, - cpu_dmem_master_awid, - cpu_dmem_master_awqos, - cpu_dmem_master_awregion, - cpu_dmem_master_wid, - cpu_imem_master_arcache, - cpu_imem_master_arid, - cpu_imem_master_arqos, - cpu_imem_master_arregion, - cpu_imem_master_awcache, - cpu_imem_master_awid, - cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; - wire [2 : 0] cpu_dmem_master_arprot, - cpu_dmem_master_arsize, - cpu_dmem_master_awprot, - cpu_dmem_master_awsize, - cpu_imem_master_arprot, - cpu_imem_master_arsize, - cpu_imem_master_awprot, - cpu_imem_master_awsize; - wire [1 : 0] cpu_dmem_master_arburst, - cpu_dmem_master_awburst, - cpu_imem_master_arburst, - cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_set_verbosity, - cpu_dmem_master_arlock, - cpu_dmem_master_arvalid, - cpu_dmem_master_awlock, - cpu_dmem_master_awvalid, - cpu_dmem_master_bready, - cpu_dmem_master_rready, - cpu_dmem_master_wlast, - cpu_dmem_master_wvalid, - cpu_imem_master_arlock, - cpu_imem_master_arvalid, - cpu_imem_master_awlock, - cpu_imem_master_awvalid, - cpu_imem_master_bready, - cpu_imem_master_rready, - cpu_imem_master_wlast, - cpu_imem_master_wvalid, - cpu_reset_server_response_get; - - // ports of submodule cpu - wire [63 : 0] cpu$dmem_master_araddr, - cpu$dmem_master_awaddr, - cpu$dmem_master_rdata, - cpu$dmem_master_wdata, - cpu$imem_master_araddr, - cpu$imem_master_awaddr, - cpu$imem_master_rdata, - cpu$imem_master_wdata, - cpu$set_verbosity_logdelay; - wire [7 : 0] cpu$dmem_master_arlen, - cpu$dmem_master_awlen, - cpu$dmem_master_wstrb, - cpu$imem_master_arlen, - cpu$imem_master_awlen, - cpu$imem_master_wstrb; - wire [3 : 0] cpu$dmem_master_arcache, - cpu$dmem_master_arid, - cpu$dmem_master_arqos, - cpu$dmem_master_arregion, - cpu$dmem_master_awcache, - cpu$dmem_master_awid, - cpu$dmem_master_awqos, - cpu$dmem_master_awregion, - cpu$dmem_master_bid, - cpu$dmem_master_rid, - cpu$dmem_master_wid, - cpu$imem_master_arcache, - cpu$imem_master_arid, - cpu$imem_master_arqos, - cpu$imem_master_arregion, - cpu$imem_master_awcache, - cpu$imem_master_awid, - cpu$imem_master_awqos, - cpu$imem_master_awregion, - cpu$imem_master_bid, - cpu$imem_master_rid, - cpu$imem_master_wid, - cpu$set_verbosity_verbosity; - wire [2 : 0] cpu$dmem_master_arprot, - cpu$dmem_master_arsize, - cpu$dmem_master_awprot, - cpu$dmem_master_awsize, - cpu$imem_master_arprot, - cpu$imem_master_arsize, - cpu$imem_master_awprot, - cpu$imem_master_awsize; - wire [1 : 0] cpu$dmem_master_arburst, - cpu$dmem_master_awburst, - cpu$dmem_master_bresp, - cpu$dmem_master_rresp, - cpu$imem_master_arburst, - cpu$imem_master_awburst, - cpu$imem_master_bresp, - cpu$imem_master_rresp; - wire cpu$EN_hart0_server_reset_request_put, - cpu$EN_hart0_server_reset_response_get, - cpu$EN_set_verbosity, - cpu$RDY_hart0_server_reset_request_put, - cpu$RDY_hart0_server_reset_response_get, - cpu$dmem_master_arlock, - cpu$dmem_master_arready, - cpu$dmem_master_arvalid, - cpu$dmem_master_awlock, - cpu$dmem_master_awready, - cpu$dmem_master_awvalid, - cpu$dmem_master_bready, - cpu$dmem_master_bvalid, - cpu$dmem_master_rlast, - cpu$dmem_master_rready, - cpu$dmem_master_rvalid, - cpu$dmem_master_wlast, - cpu$dmem_master_wready, - cpu$dmem_master_wvalid, - cpu$hart0_server_reset_request_put, - cpu$hart0_server_reset_response_get, - cpu$imem_master_arlock, - cpu$imem_master_arready, - cpu$imem_master_arvalid, - cpu$imem_master_awlock, - cpu$imem_master_awready, - cpu$imem_master_awvalid, - cpu$imem_master_bready, - cpu$imem_master_bvalid, - cpu$imem_master_rlast, - cpu$imem_master_rready, - cpu$imem_master_rvalid, - cpu$imem_master_wlast, - cpu$imem_master_wready, - cpu$imem_master_wvalid, - cpu$m_external_interrupt_req_set_not_clear, - cpu$nmi_req_set_not_clear, - cpu$s_external_interrupt_req_set_not_clear, - cpu$software_interrupt_req_set_not_clear, - cpu$timer_interrupt_req_set_not_clear; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_araddr, - fabric_2x3$v_to_slaves_2_awaddr, - fabric_2x3$v_to_slaves_2_rdata, - fabric_2x3$v_to_slaves_2_wdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb, - fabric_2x3$v_to_slaves_2_arlen, - fabric_2x3$v_to_slaves_2_awlen, - fabric_2x3$v_to_slaves_2_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_wid, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, - fabric_2x3$v_to_slaves_2_arcache, - fabric_2x3$v_to_slaves_2_arid, - fabric_2x3$v_to_slaves_2_arqos, - fabric_2x3$v_to_slaves_2_arregion, - fabric_2x3$v_to_slaves_2_awcache, - fabric_2x3$v_to_slaves_2_awid, - fabric_2x3$v_to_slaves_2_awqos, - fabric_2x3$v_to_slaves_2_awregion, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize, - fabric_2x3$v_to_slaves_2_arprot, - fabric_2x3$v_to_slaves_2_arsize, - fabric_2x3$v_to_slaves_2_awprot, - fabric_2x3$v_to_slaves_2_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_arburst, - fabric_2x3$v_to_slaves_2_awburst, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arlock, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_arvalid, - fabric_2x3$v_to_slaves_2_awlock, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_awvalid, - fabric_2x3$v_to_slaves_2_bready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rready, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wlast, - fabric_2x3$v_to_slaves_2_wready, - fabric_2x3$v_to_slaves_2_wvalid; - - // ports of submodule near_mem_io - wire [63 : 0] near_mem_io$axi4_slave_araddr, - near_mem_io$axi4_slave_awaddr, - near_mem_io$axi4_slave_rdata, - near_mem_io$axi4_slave_wdata, - near_mem_io$set_addr_map_addr_base, - near_mem_io$set_addr_map_addr_lim; - wire [7 : 0] near_mem_io$axi4_slave_arlen, - near_mem_io$axi4_slave_awlen, - near_mem_io$axi4_slave_wstrb; - wire [3 : 0] near_mem_io$axi4_slave_arcache, - near_mem_io$axi4_slave_arid, - near_mem_io$axi4_slave_arqos, - near_mem_io$axi4_slave_arregion, - near_mem_io$axi4_slave_awcache, - near_mem_io$axi4_slave_awid, - near_mem_io$axi4_slave_awqos, - near_mem_io$axi4_slave_awregion, - near_mem_io$axi4_slave_bid, - near_mem_io$axi4_slave_rid, - near_mem_io$axi4_slave_wid; - wire [2 : 0] near_mem_io$axi4_slave_arprot, - near_mem_io$axi4_slave_arsize, - near_mem_io$axi4_slave_awprot, - near_mem_io$axi4_slave_awsize; - wire [1 : 0] near_mem_io$axi4_slave_arburst, - near_mem_io$axi4_slave_awburst, - near_mem_io$axi4_slave_bresp, - near_mem_io$axi4_slave_rresp; - wire near_mem_io$EN_get_sw_interrupt_req_get, - near_mem_io$EN_get_timer_interrupt_req_get, - near_mem_io$EN_server_reset_request_put, - near_mem_io$EN_server_reset_response_get, - near_mem_io$EN_set_addr_map, - near_mem_io$RDY_get_sw_interrupt_req_get, - near_mem_io$RDY_get_timer_interrupt_req_get, - near_mem_io$RDY_server_reset_request_put, - near_mem_io$RDY_server_reset_response_get, - near_mem_io$axi4_slave_arlock, - near_mem_io$axi4_slave_arready, - near_mem_io$axi4_slave_arvalid, - near_mem_io$axi4_slave_awlock, - near_mem_io$axi4_slave_awready, - near_mem_io$axi4_slave_awvalid, - near_mem_io$axi4_slave_bready, - near_mem_io$axi4_slave_bvalid, - near_mem_io$axi4_slave_rlast, - near_mem_io$axi4_slave_rready, - near_mem_io$axi4_slave_rvalid, - near_mem_io$axi4_slave_wlast, - near_mem_io$axi4_slave_wready, - near_mem_io$axi4_slave_wvalid, - near_mem_io$get_sw_interrupt_req_get, - near_mem_io$get_timer_interrupt_req_get; - - // ports of submodule plic - wire [63 : 0] plic$axi4_slave_araddr, - plic$axi4_slave_awaddr, - plic$axi4_slave_rdata, - plic$axi4_slave_wdata, - plic$set_addr_map_addr_base, - plic$set_addr_map_addr_lim; - wire [7 : 0] plic$axi4_slave_arlen, - plic$axi4_slave_awlen, - plic$axi4_slave_wstrb; - wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, - plic$axi4_slave_arqos, - plic$axi4_slave_arregion, - plic$axi4_slave_awcache, - plic$axi4_slave_awid, - plic$axi4_slave_awqos, - plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, - plic$axi4_slave_wid, - plic$set_verbosity_verbosity; - wire [2 : 0] plic$axi4_slave_arprot, - plic$axi4_slave_arsize, - plic$axi4_slave_awprot, - plic$axi4_slave_awsize; - wire [1 : 0] plic$axi4_slave_arburst, - plic$axi4_slave_awburst, - plic$axi4_slave_bresp, - plic$axi4_slave_rresp; - wire plic$EN_server_reset_request_put, - plic$EN_server_reset_response_get, - plic$EN_set_addr_map, - plic$EN_set_verbosity, - plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, - plic$axi4_slave_arlock, - plic$axi4_slave_arready, - plic$axi4_slave_arvalid, - plic$axi4_slave_awlock, - plic$axi4_slave_awready, - plic$axi4_slave_awvalid, - plic$axi4_slave_bready, - plic$axi4_slave_bvalid, - plic$axi4_slave_rlast, - plic$axi4_slave_rready, - plic$axi4_slave_rvalid, - plic$axi4_slave_wlast, - plic$axi4_slave_wready, - plic$axi4_slave_wvalid, - plic$v_sources_0_m_interrupt_req_set_not_clear, - plic$v_sources_10_m_interrupt_req_set_not_clear, - plic$v_sources_11_m_interrupt_req_set_not_clear, - plic$v_sources_12_m_interrupt_req_set_not_clear, - plic$v_sources_13_m_interrupt_req_set_not_clear, - plic$v_sources_14_m_interrupt_req_set_not_clear, - plic$v_sources_15_m_interrupt_req_set_not_clear, - plic$v_sources_1_m_interrupt_req_set_not_clear, - plic$v_sources_2_m_interrupt_req_set_not_clear, - plic$v_sources_3_m_interrupt_req_set_not_clear, - plic$v_sources_4_m_interrupt_req_set_not_clear, - plic$v_sources_5_m_interrupt_req_set_not_clear, - plic$v_sources_6_m_interrupt_req_set_not_clear, - plic$v_sources_7_m_interrupt_req_set_not_clear, - plic$v_sources_8_m_interrupt_req_set_not_clear, - plic$v_sources_9_m_interrupt_req_set_not_clear, - plic$v_targets_0_m_eip, - plic$v_targets_1_m_eip; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_sw_interrupts, - CAN_FIRE_RL_rl_relay_timer_interrupts, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_nmi_req, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_sw_interrupts, - WILL_FIRE_RL_rl_relay_timer_interrupts, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_nmi_req, - WILL_FIRE_set_verbosity; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4310; - reg [31 : 0] v__h4551; - reg [31 : 0] v__h4304; - reg [31 : 0] v__h4545; - // synopsys translate_on - - // remaining internal signals - wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // actionvalue method cpu_reset_server_response_get - assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ; - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; - - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - - // value method cpu_imem_master_m_awid - assign cpu_imem_master_awid = cpu$imem_master_awid ; - - // value method cpu_imem_master_m_awaddr - assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; - - // value method cpu_imem_master_m_awlen - assign cpu_imem_master_awlen = cpu$imem_master_awlen ; - - // value method cpu_imem_master_m_awsize - assign cpu_imem_master_awsize = cpu$imem_master_awsize ; - - // value method cpu_imem_master_m_awburst - assign cpu_imem_master_awburst = cpu$imem_master_awburst ; - - // value method cpu_imem_master_m_awlock - assign cpu_imem_master_awlock = cpu$imem_master_awlock ; - - // value method cpu_imem_master_m_awcache - assign cpu_imem_master_awcache = cpu$imem_master_awcache ; - - // value method cpu_imem_master_m_awprot - assign cpu_imem_master_awprot = cpu$imem_master_awprot ; - - // value method cpu_imem_master_m_awqos - assign cpu_imem_master_awqos = cpu$imem_master_awqos ; - - // value method cpu_imem_master_m_awregion - assign cpu_imem_master_awregion = cpu$imem_master_awregion ; - - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; - - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; - - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = cpu$imem_master_wid ; - - // value method cpu_imem_master_m_wdata - assign cpu_imem_master_wdata = cpu$imem_master_wdata ; - - // value method cpu_imem_master_m_wstrb - assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; - - // value method cpu_imem_master_m_wlast - assign cpu_imem_master_wlast = cpu$imem_master_wlast ; - - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; - - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = cpu$imem_master_bready ; - - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; - - // value method cpu_imem_master_m_arid - assign cpu_imem_master_arid = cpu$imem_master_arid ; - - // value method cpu_imem_master_m_araddr - assign cpu_imem_master_araddr = cpu$imem_master_araddr ; - - // value method cpu_imem_master_m_arlen - assign cpu_imem_master_arlen = cpu$imem_master_arlen ; - - // value method cpu_imem_master_m_arsize - assign cpu_imem_master_arsize = cpu$imem_master_arsize ; - - // value method cpu_imem_master_m_arburst - assign cpu_imem_master_arburst = cpu$imem_master_arburst ; - - // value method cpu_imem_master_m_arlock - assign cpu_imem_master_arlock = cpu$imem_master_arlock ; - - // value method cpu_imem_master_m_arcache - assign cpu_imem_master_arcache = cpu$imem_master_arcache ; - - // value method cpu_imem_master_m_arprot - assign cpu_imem_master_arprot = cpu$imem_master_arprot ; - - // value method cpu_imem_master_m_arqos - assign cpu_imem_master_arqos = cpu$imem_master_arqos ; - - // value method cpu_imem_master_m_arregion - assign cpu_imem_master_arregion = cpu$imem_master_arregion ; - - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; - - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - - // value method cpu_imem_master_m_rready - assign cpu_imem_master_rready = cpu$imem_master_rready ; - - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; - - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; - - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; - - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; - - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; - - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; - - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; - - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; - - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; - - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; - - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; - - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; - - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; - - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; - - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; - - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; - - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; - - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; - - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; - - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; - - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; - - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; - - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; - - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; - - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; - - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; - - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; - - // action method core_external_interrupt_sources_0_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_1_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_2_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_3_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_4_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_5_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_6_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_7_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_8_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_9_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_10_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_11_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_12_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_13_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_14_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_15_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // submodule cpu - mkCPU cpu(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(cpu$dmem_master_arready), - .dmem_master_awready(cpu$dmem_master_awready), - .dmem_master_bid(cpu$dmem_master_bid), - .dmem_master_bresp(cpu$dmem_master_bresp), - .dmem_master_bvalid(cpu$dmem_master_bvalid), - .dmem_master_rdata(cpu$dmem_master_rdata), - .dmem_master_rid(cpu$dmem_master_rid), - .dmem_master_rlast(cpu$dmem_master_rlast), - .dmem_master_rresp(cpu$dmem_master_rresp), - .dmem_master_rvalid(cpu$dmem_master_rvalid), - .dmem_master_wready(cpu$dmem_master_wready), - .hart0_server_reset_request_put(cpu$hart0_server_reset_request_put), - .imem_master_arready(cpu$imem_master_arready), - .imem_master_awready(cpu$imem_master_awready), - .imem_master_bid(cpu$imem_master_bid), - .imem_master_bresp(cpu$imem_master_bresp), - .imem_master_bvalid(cpu$imem_master_bvalid), - .imem_master_rdata(cpu$imem_master_rdata), - .imem_master_rid(cpu$imem_master_rid), - .imem_master_rlast(cpu$imem_master_rlast), - .imem_master_rresp(cpu$imem_master_rresp), - .imem_master_rvalid(cpu$imem_master_rvalid), - .imem_master_wready(cpu$imem_master_wready), - .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), - .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), - .s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear), - .set_verbosity_logdelay(cpu$set_verbosity_logdelay), - .set_verbosity_verbosity(cpu$set_verbosity_verbosity), - .software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), - .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), - .EN_set_verbosity(cpu$EN_set_verbosity), - .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), - .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), - .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), - .imem_master_awvalid(cpu$imem_master_awvalid), - .imem_master_awid(cpu$imem_master_awid), - .imem_master_awaddr(cpu$imem_master_awaddr), - .imem_master_awlen(cpu$imem_master_awlen), - .imem_master_awsize(cpu$imem_master_awsize), - .imem_master_awburst(cpu$imem_master_awburst), - .imem_master_awlock(cpu$imem_master_awlock), - .imem_master_awcache(cpu$imem_master_awcache), - .imem_master_awprot(cpu$imem_master_awprot), - .imem_master_awqos(cpu$imem_master_awqos), - .imem_master_awregion(cpu$imem_master_awregion), - .imem_master_wvalid(cpu$imem_master_wvalid), - .imem_master_wid(cpu$imem_master_wid), - .imem_master_wdata(cpu$imem_master_wdata), - .imem_master_wstrb(cpu$imem_master_wstrb), - .imem_master_wlast(cpu$imem_master_wlast), - .imem_master_bready(cpu$imem_master_bready), - .imem_master_arvalid(cpu$imem_master_arvalid), - .imem_master_arid(cpu$imem_master_arid), - .imem_master_araddr(cpu$imem_master_araddr), - .imem_master_arlen(cpu$imem_master_arlen), - .imem_master_arsize(cpu$imem_master_arsize), - .imem_master_arburst(cpu$imem_master_arburst), - .imem_master_arlock(cpu$imem_master_arlock), - .imem_master_arcache(cpu$imem_master_arcache), - .imem_master_arprot(cpu$imem_master_arprot), - .imem_master_arqos(cpu$imem_master_arqos), - .imem_master_arregion(cpu$imem_master_arregion), - .imem_master_rready(cpu$imem_master_rready), - .dmem_master_awvalid(cpu$dmem_master_awvalid), - .dmem_master_awid(cpu$dmem_master_awid), - .dmem_master_awaddr(cpu$dmem_master_awaddr), - .dmem_master_awlen(cpu$dmem_master_awlen), - .dmem_master_awsize(cpu$dmem_master_awsize), - .dmem_master_awburst(cpu$dmem_master_awburst), - .dmem_master_awlock(cpu$dmem_master_awlock), - .dmem_master_awcache(cpu$dmem_master_awcache), - .dmem_master_awprot(cpu$dmem_master_awprot), - .dmem_master_awqos(cpu$dmem_master_awqos), - .dmem_master_awregion(cpu$dmem_master_awregion), - .dmem_master_wvalid(cpu$dmem_master_wvalid), - .dmem_master_wid(cpu$dmem_master_wid), - .dmem_master_wdata(cpu$dmem_master_wdata), - .dmem_master_wstrb(cpu$dmem_master_wstrb), - .dmem_master_wlast(cpu$dmem_master_wlast), - .dmem_master_bready(cpu$dmem_master_bready), - .dmem_master_arvalid(cpu$dmem_master_arvalid), - .dmem_master_arid(cpu$dmem_master_arid), - .dmem_master_araddr(cpu$dmem_master_araddr), - .dmem_master_arlen(cpu$dmem_master_arlen), - .dmem_master_arsize(cpu$dmem_master_arsize), - .dmem_master_arburst(cpu$dmem_master_arburst), - .dmem_master_arlock(cpu$dmem_master_arlock), - .dmem_master_arcache(cpu$dmem_master_arcache), - .dmem_master_arprot(cpu$dmem_master_arprot), - .dmem_master_arqos(cpu$dmem_master_arqos), - .dmem_master_arregion(cpu$dmem_master_arregion), - .dmem_master_rready(cpu$dmem_master_rready), - .RDY_set_verbosity()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(), - .v_from_masters_1_wready(), - .v_from_masters_1_bvalid(), - .v_from_masters_1_bid(), - .v_from_masters_1_bresp(), - .v_from_masters_1_arready(), - .v_from_masters_1_rvalid(), - .v_from_masters_1_rid(), - .v_from_masters_1_rdata(), - .v_from_masters_1_rresp(), - .v_from_masters_1_rlast(), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); - - // submodule near_mem_io - mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(near_mem_io$axi4_slave_araddr), - .axi4_slave_arburst(near_mem_io$axi4_slave_arburst), - .axi4_slave_arcache(near_mem_io$axi4_slave_arcache), - .axi4_slave_arid(near_mem_io$axi4_slave_arid), - .axi4_slave_arlen(near_mem_io$axi4_slave_arlen), - .axi4_slave_arlock(near_mem_io$axi4_slave_arlock), - .axi4_slave_arprot(near_mem_io$axi4_slave_arprot), - .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), - .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), - .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), - .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), - .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), - .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), - .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), - .axi4_slave_awid(near_mem_io$axi4_slave_awid), - .axi4_slave_awlen(near_mem_io$axi4_slave_awlen), - .axi4_slave_awlock(near_mem_io$axi4_slave_awlock), - .axi4_slave_awprot(near_mem_io$axi4_slave_awprot), - .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), - .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), - .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), - .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), - .axi4_slave_bready(near_mem_io$axi4_slave_bready), - .axi4_slave_rready(near_mem_io$axi4_slave_rready), - .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), - .axi4_slave_wid(near_mem_io$axi4_slave_wid), - .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), - .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), - .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), - .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), - .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), - .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), - .EN_set_addr_map(near_mem_io$EN_set_addr_map), - .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), - .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), - .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(near_mem_io$axi4_slave_awready), - .axi4_slave_wready(near_mem_io$axi4_slave_wready), - .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), - .axi4_slave_bid(near_mem_io$axi4_slave_bid), - .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), - .axi4_slave_arready(near_mem_io$axi4_slave_arready), - .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), - .axi4_slave_rid(near_mem_io$axi4_slave_rid), - .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), - .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), - .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), - .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), - .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), - .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), - .RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get)); - - // submodule plic - mkPLIC_16_2_7 plic(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(plic$axi4_slave_araddr), - .axi4_slave_arburst(plic$axi4_slave_arburst), - .axi4_slave_arcache(plic$axi4_slave_arcache), - .axi4_slave_arid(plic$axi4_slave_arid), - .axi4_slave_arlen(plic$axi4_slave_arlen), - .axi4_slave_arlock(plic$axi4_slave_arlock), - .axi4_slave_arprot(plic$axi4_slave_arprot), - .axi4_slave_arqos(plic$axi4_slave_arqos), - .axi4_slave_arregion(plic$axi4_slave_arregion), - .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), - .axi4_slave_awaddr(plic$axi4_slave_awaddr), - .axi4_slave_awburst(plic$axi4_slave_awburst), - .axi4_slave_awcache(plic$axi4_slave_awcache), - .axi4_slave_awid(plic$axi4_slave_awid), - .axi4_slave_awlen(plic$axi4_slave_awlen), - .axi4_slave_awlock(plic$axi4_slave_awlock), - .axi4_slave_awprot(plic$axi4_slave_awprot), - .axi4_slave_awqos(plic$axi4_slave_awqos), - .axi4_slave_awregion(plic$axi4_slave_awregion), - .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_bready(plic$axi4_slave_bready), - .axi4_slave_rready(plic$axi4_slave_rready), - .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), - .axi4_slave_wlast(plic$axi4_slave_wlast), - .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .set_addr_map_addr_base(plic$set_addr_map_addr_base), - .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), - .set_verbosity_verbosity(plic$set_verbosity_verbosity), - .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), - .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), - .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), - .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), - .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), - .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), - .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), - .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), - .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), - .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), - .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), - .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), - .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), - .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), - .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), - .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), - .EN_set_verbosity(plic$EN_set_verbosity), - .EN_show_PLIC_state(plic$EN_show_PLIC_state), - .EN_server_reset_request_put(plic$EN_server_reset_request_put), - .EN_server_reset_response_get(plic$EN_server_reset_response_get), - .EN_set_addr_map(plic$EN_set_addr_map), - .RDY_set_verbosity(), - .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(plic$axi4_slave_awready), - .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), - .axi4_slave_bid(plic$axi4_slave_bid), - .axi4_slave_bresp(plic$axi4_slave_bresp), - .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), - .axi4_slave_rid(plic$axi4_slave_rid), - .axi4_slave_rdata(plic$axi4_slave_rdata), - .axi4_slave_rresp(plic$axi4_slave_rresp), - .axi4_slave_rlast(plic$axi4_slave_rlast), - .v_targets_0_m_eip(plic$v_targets_0_m_eip), - .v_targets_1_m_eip(plic$v_targets_1_m_eip)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_relay_sw_interrupts - assign CAN_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // rule RL_rl_relay_timer_interrupts - assign CAN_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - - // rule RL_rl_relay_external_interrupts - assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule cpu - assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; - assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; - assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; - assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; - assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; - assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ; - assign cpu$imem_master_arready = cpu_imem_master_arready ; - assign cpu$imem_master_awready = cpu_imem_master_awready ; - assign cpu$imem_master_bid = cpu_imem_master_bid ; - assign cpu$imem_master_bresp = cpu_imem_master_bresp ; - assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; - assign cpu$imem_master_rdata = cpu_imem_master_rdata ; - assign cpu$imem_master_rid = cpu_imem_master_rid ; - assign cpu$imem_master_rlast = cpu_imem_master_rlast ; - assign cpu$imem_master_rresp = cpu_imem_master_rresp ; - assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; - assign cpu$imem_master_wready = cpu_imem_master_wready ; - assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; - assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; - assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; - assign cpu$software_interrupt_req_set_not_clear = - near_mem_io$get_sw_interrupt_req_get ; - assign cpu$timer_interrupt_req_set_not_clear = - near_mem_io$get_timer_interrupt_req_get ; - assign cpu$EN_hart0_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign cpu$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign cpu$EN_set_verbosity = EN_set_verbosity ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = cpu_reset_server_request_put ; - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ; - assign f_reset_rsps$ENQ = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; - assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; - assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; - assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; - assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; - assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; - assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; - assign fabric_2x3$v_from_masters_0_wid = cpu$dmem_master_wid ; - assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_awaddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_bready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_wdata = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wstrb = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; - assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; - - // submodule near_mem_io - assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign near_mem_io$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; - assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; - assign near_mem_io$set_addr_map_addr_base = - soc_map$m_near_mem_io_addr_base ; - assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; - assign near_mem_io$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign near_mem_io$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_set_addr_map = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_get_timer_interrupt_req_get = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign near_mem_io$EN_get_sw_interrupt_req_get = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_2_wid ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; - assign plic$set_verbosity_verbosity = 4'h0 ; - assign plic$v_sources_0_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; - assign plic$v_sources_10_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; - assign plic$v_sources_11_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; - assign plic$v_sources_12_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; - assign plic$v_sources_13_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; - assign plic$v_sources_14_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; - assign plic$v_sources_15_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; - assign plic$v_sources_1_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; - assign plic$v_sources_2_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; - assign plic$v_sources_3_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; - assign plic$v_sources_4_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; - assign plic$v_sources_5_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; - assign plic$v_sources_6_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; - assign plic$v_sources_7_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; - assign plic$v_sources_8_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; - assign plic$v_sources_9_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; - assign plic$EN_set_verbosity = 1'b0 ; - assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - cpu$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h4310 = $stime; - #0; - end - v__h4304 = v__h4310 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4304); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h4551 = $stime; - #0; - end - v__h4545 = v__h4551 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4545); - end - // synopsys translate_on -endmodule // mkCore - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric.v deleted file mode 100644 index 771fc0dc..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric.v +++ /dev/null @@ -1,8149 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 = - fabric_cfg_verbosity > 4'd1 ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - $display("%0d: %m::AXI4_Fabric.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v deleted file mode 100644 index 2e372865..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_2x3.v +++ /dev/null @@ -1,7465 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_2x3(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8650; - reg [31 : 0] v__h9025; - reg [31 : 0] v__h9400; - reg [31 : 0] v__h9845; - reg [31 : 0] v__h10214; - reg [31 : 0] v__h10583; - reg [31 : 0] v__h11872; - reg [31 : 0] v__h12325; - reg [31 : 0] v__h12702; - reg [31 : 0] v__h12994; - reg [31 : 0] v__h13286; - reg [31 : 0] v__h13589; - reg [31 : 0] v__h13855; - reg [31 : 0] v__h14121; - reg [31 : 0] v__h14385; - reg [31 : 0] v__h14611; - reg [31 : 0] v__h15040; - reg [31 : 0] v__h15396; - reg [31 : 0] v__h15752; - reg [31 : 0] v__h16169; - reg [31 : 0] v__h16501; - reg [31 : 0] v__h16833; - reg [31 : 0] v__h17849; - reg [31 : 0] v__h18100; - reg [31 : 0] v__h18475; - reg [31 : 0] v__h18716; - reg [31 : 0] v__h19091; - reg [31 : 0] v__h19332; - reg [31 : 0] v__h19694; - reg [31 : 0] v__h19945; - reg [31 : 0] v__h20275; - reg [31 : 0] v__h20516; - reg [31 : 0] v__h20846; - reg [31 : 0] v__h21087; - reg [31 : 0] v__h21600; - reg [31 : 0] v__h22001; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8644; - reg [31 : 0] v__h9019; - reg [31 : 0] v__h9394; - reg [31 : 0] v__h9839; - reg [31 : 0] v__h10208; - reg [31 : 0] v__h10577; - reg [31 : 0] v__h11866; - reg [31 : 0] v__h12319; - reg [31 : 0] v__h12696; - reg [31 : 0] v__h12988; - reg [31 : 0] v__h13280; - reg [31 : 0] v__h13583; - reg [31 : 0] v__h13849; - reg [31 : 0] v__h14115; - reg [31 : 0] v__h14379; - reg [31 : 0] v__h14605; - reg [31 : 0] v__h15034; - reg [31 : 0] v__h15390; - reg [31 : 0] v__h15746; - reg [31 : 0] v__h16163; - reg [31 : 0] v__h16495; - reg [31 : 0] v__h16827; - reg [31 : 0] v__h17843; - reg [31 : 0] v__h18094; - reg [31 : 0] v__h18469; - reg [31 : 0] v__h18710; - reg [31 : 0] v__h19085; - reg [31 : 0] v__h19326; - reg [31 : 0] v__h19688; - reg [31 : 0] v__h19939; - reg [31 : 0] v__h20269; - reg [31 : 0] v__h20510; - reg [31 : 0] v__h20840; - reg [31 : 0] v__h21081; - reg [31 : 0] v__h21594; - reg [31 : 0] v__h21995; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11777, - x__h12230, - x__h17986, - x__h18612, - x__h19228, - x__h21532, - x__h21933; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - x1_avValue_rresp__h17964, - x1_avValue_rresp__h18590, - x1_avValue_rresp__h19206; - wire _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156, - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371, - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411, - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540, - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - 8'd0 : - x__h17986 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - 8'd0 : - x__h18612 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - 8'd0 : - x__h19228 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? - 8'd0 : - x__h11777 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ? - 8'd0 : - x__h12230 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ? - 8'd0 : - x__h21532 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ? - 8'd0 : - x__h21933 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - x1_avValue_rresp__h17964 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - x1_avValue_rresp__h18590 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - x1_avValue_rresp__h19206 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h17964 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18590 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19206 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11777 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12230 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h17986 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h18612 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19228 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21532 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h21933 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8650 = $stime; - #0; - end - v__h8644 = v__h8650 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8644, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9025 = $stime; - #0; - end - v__h9019 = v__h9025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9019, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9400 = $stime; - #0; - end - v__h9394 = v__h9400 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9394, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9845 = $stime; - #0; - end - v__h9839 = v__h9845 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9839, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10214 = $stime; - #0; - end - v__h10208 = v__h10214 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10208, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10583 = $stime; - #0; - end - v__h10577 = v__h10583 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10577, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h11872 = $stime; - #0; - end - v__h11866 = v__h11872 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h11866, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12325 = $stime; - #0; - end - v__h12319 = v__h12325 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12319, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12702 = $stime; - #0; - end - v__h12696 = v__h12702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12696, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h12994 = $stime; - #0; - end - v__h12988 = v__h12994 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12988, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13286 = $stime; - #0; - end - v__h13280 = v__h13286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13280, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13589 = $stime; - #0; - end - v__h13583 = v__h13589 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13583, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13855 = $stime; - #0; - end - v__h13849 = v__h13855 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13849, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14121 = $stime; - #0; - end - v__h14115 = v__h14121 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14115, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14385 = $stime; - #0; - end - v__h14379 = v__h14385 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14379, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14611 = $stime; - #0; - end - v__h14605 = v__h14611 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14605, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15040 = $stime; - #0; - end - v__h15034 = v__h15040 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15034, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15396 = $stime; - #0; - end - v__h15390 = v__h15396 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15390, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15752 = $stime; - #0; - end - v__h15746 = v__h15752 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15746, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16169 = $stime; - #0; - end - v__h16163 = v__h16169 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16163, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16501 = $stime; - #0; - end - v__h16495 = v__h16501 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16495, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16833 = $stime; - #0; - end - v__h16827 = v__h16833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16827, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h17849 = $stime; - #0; - end - v__h17843 = v__h17849 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h17843, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18100 = $stime; - #0; - end - v__h18094 = v__h18100 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18094, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18475 = $stime; - #0; - end - v__h18469 = v__h18475 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18469, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h18716 = $stime; - #0; - end - v__h18710 = v__h18716 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18710, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19091 = $stime; - #0; - end - v__h19085 = v__h19091 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19085, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19332 = $stime; - #0; - end - v__h19326 = v__h19332 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19326, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h19694 = $stime; - #0; - end - v__h19688 = v__h19694 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19688, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19945 = $stime; - #0; - end - v__h19939 = v__h19945 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19939, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20275 = $stime; - #0; - end - v__h20269 = v__h20275 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20269, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20516 = $stime; - #0; - end - v__h20510 = v__h20516 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20510, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h20846 = $stime; - #0; - end - v__h20840 = v__h20846 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20840, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21087 = $stime; - #0; - end - v__h21081 = v__h21087 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21081, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21600 = $stime; - #0; - end - v__h21594 = v__h21600 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21594, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22001 = $stime; - #0; - end - v__h21995 = v__h22001 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21995, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_2x3 - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v deleted file mode 100644 index ac19188b..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkFabric_AXI4.v +++ /dev/null @@ -1,8145 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_AXI4(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_AXI4 - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v deleted file mode 100644 index 5d5bbfb6..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkGPR_RegFile.v +++ /dev/null @@ -1,249 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 64 -// read_rs1_port2 O 64 -// read_rs2 O 64 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// Combinational paths from inputs to outputs: -// read_rs1_rs1 -> read_rs1 -// read_rs1_port2_rs1 -> read_rs1_port2 -// read_rs2_rs2 -> read_rs2 -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkGPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [63 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [63 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [63 : 0] read_rs2; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [63 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [63 : 0] read_rs1, read_rs1_port2, read_rs2; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [63 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_3 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = - (read_rs1_port2_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_2 ; - - // value method read_rs2 - assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 64'd0 : regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd64), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs2_rs2 ; - assign regfile$ADDR_2 = read_rs1_port2_rs1 ; - assign regfile$ADDR_3 = read_rs1_rs1 ; - assign regfile$ADDR_4 = 5'h0 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkGPR_RegFile - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v deleted file mode 100644 index f4d13fdd..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_32.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 64 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 32 -// put_args_y_is_signed I 1 -// put_args_y I 32 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_32(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [31 : 0] put_args_x; - input put_args_y_is_signed; - input [31 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [63 : 0] result_value; - - // signals for module outputs - wire [63 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [63 : 0] m_rg_x; - wire [63 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [63 : 0] m_rg_xy; - wire [63 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [31 : 0] m_rg_y; - wire [31 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [63 : 0] xy___1__h654; - wire [31 : 0] _theResult___fst__h491, - _theResult___fst__h494, - _theResult___fst__h536, - _theResult___fst__h539, - _theResult___snd_fst__h531; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 32'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h654 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 32'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h491 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h539 : - _theResult___snd_fst__h531 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[31] != put_args_y[31] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 = - put_args_x_is_signed ? - put_args_x[31] : - put_args_y_is_signed && put_args_y[31] ; - assign _theResult___fst__h491 = - put_args_x_is_signed ? _theResult___fst__h494 : put_args_x ; - assign _theResult___fst__h494 = put_args_x[31] ? -put_args_x : put_args_x ; - assign _theResult___fst__h536 = - put_args_y_is_signed ? _theResult___fst__h539 : put_args_y ; - assign _theResult___fst__h539 = put_args_y[31] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h531 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h536 ; - assign xy___1__h654 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 64'hAAAAAAAAAAAAAAAA; - m_rg_xy = 64'hAAAAAAAAAAAAAAAA; - m_rg_y = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_32 - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v deleted file mode 100644 index 0b513191..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkIntMul_64.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 128 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 64 -// put_args_y_is_signed I 1 -// put_args_y I 64 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_64(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [63 : 0] put_args_x; - input put_args_y_is_signed; - input [63 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [127 : 0] result_value; - - // signals for module outputs - wire [127 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [127 : 0] m_rg_x; - wire [127 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [127 : 0] m_rg_xy; - wire [127 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [63 : 0] m_rg_y; - wire [63 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [127 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [127 : 0] xy___1__h648; - wire [63 : 0] _theResult___fst__h488, - _theResult___fst__h491, - _theResult___fst__h533, - _theResult___fst__h536, - _theResult___snd_fst__h528; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 64'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h648 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 64'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h488 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h536 : - _theResult___snd_fst__h528 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[63] != put_args_y[63] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 = - put_args_x_is_signed ? - put_args_x[63] : - put_args_y_is_signed && put_args_y[63] ; - assign _theResult___fst__h488 = - put_args_x_is_signed ? _theResult___fst__h491 : put_args_x ; - assign _theResult___fst__h491 = put_args_x[63] ? -put_args_x : put_args_x ; - assign _theResult___fst__h533 = - put_args_y_is_signed ? _theResult___fst__h536 : put_args_y ; - assign _theResult___fst__h536 = put_args_y[63] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h528 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h533 ; - assign xy___1__h648 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_y = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_64 - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v deleted file mode 100644 index 887c3ebc..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkMMU_Cache.v +++ /dev/null @@ -1,6051 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// valid O 1 -// addr O 64 reg -// word64 O 64 -// st_amo_val O 64 -// exc O 1 -// exc_code O 4 reg -// RDY_server_flush_request_put O 1 reg -// RDY_server_flush_response_get O 1 -// RDY_tlb_flush O 1 const -// mem_master_awvalid O 1 -// mem_master_awid O 4 reg -// mem_master_awaddr O 64 reg -// mem_master_awlen O 8 reg -// mem_master_awsize O 3 reg -// mem_master_awburst O 2 reg -// mem_master_awlock O 1 reg -// mem_master_awcache O 4 reg -// mem_master_awprot O 3 reg -// mem_master_awqos O 4 reg -// mem_master_awregion O 4 reg -// mem_master_wvalid O 1 -// mem_master_wid O 4 reg -// mem_master_wdata O 64 reg -// mem_master_wstrb O 8 reg -// mem_master_wlast O 1 reg -// mem_master_bready O 1 -// mem_master_arvalid O 1 -// mem_master_arid O 4 reg -// mem_master_araddr O 64 reg -// mem_master_arlen O 8 reg -// mem_master_arsize O 3 reg -// mem_master_arburst O 2 reg -// mem_master_arlock O 1 reg -// mem_master_arcache O 4 reg -// mem_master_arprot O 3 reg -// mem_master_arqos O 4 reg -// mem_master_arregion O 4 reg -// mem_master_rready O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_op I 2 -// req_f3 I 3 -// req_amo_funct7 I 7 reg -// req_addr I 64 -// req_st_value I 64 -// req_priv I 2 unused -// req_sstatus_SUM I 1 unused -// req_mstatus_MXR I 1 unused -// req_satp I 64 unused -// mem_master_awready I 1 -// mem_master_wready I 1 -// mem_master_bvalid I 1 -// mem_master_bid I 4 reg -// mem_master_bresp I 2 reg -// mem_master_arready I 1 -// mem_master_rvalid I 1 -// mem_master_rid I 4 reg -// mem_master_rdata I 64 reg -// mem_master_rresp I 2 reg -// mem_master_rlast I 1 reg -// EN_set_verbosity I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// EN_server_flush_request_put I 1 -// EN_server_flush_response_get I 1 -// EN_tlb_flush I 1 unused -// -// Combinational paths from inputs to outputs: -// (mem_master_awready, mem_master_wready) -> valid -// (mem_master_awready, mem_master_wready) -> word64 -// (mem_master_awready, mem_master_wready) -> st_amo_val -// (mem_master_awready, mem_master_wready) -> mem_master_bready -// (mem_master_awready, mem_master_wready, EN_req) -> mem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMMU_Cache(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_op, - req_f3, - req_amo_funct7, - req_addr, - req_st_value, - req_priv, - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - EN_req, - - valid, - - addr, - - word64, - - st_amo_val, - - exc, - - exc_code, - - EN_server_flush_request_put, - RDY_server_flush_request_put, - - EN_server_flush_response_get, - RDY_server_flush_response_get, - - EN_tlb_flush, - RDY_tlb_flush, - - mem_master_awvalid, - - mem_master_awid, - - mem_master_awaddr, - - mem_master_awlen, - - mem_master_awsize, - - mem_master_awburst, - - mem_master_awlock, - - mem_master_awcache, - - mem_master_awprot, - - mem_master_awqos, - - mem_master_awregion, - - mem_master_awready, - - mem_master_wvalid, - - mem_master_wid, - - mem_master_wdata, - - mem_master_wstrb, - - mem_master_wlast, - - mem_master_wready, - - mem_master_bvalid, - mem_master_bid, - mem_master_bresp, - - mem_master_bready, - - mem_master_arvalid, - - mem_master_arid, - - mem_master_araddr, - - mem_master_arlen, - - mem_master_arsize, - - mem_master_arburst, - - mem_master_arlock, - - mem_master_arcache, - - mem_master_arprot, - - mem_master_arqos, - - mem_master_arregion, - - mem_master_arready, - - mem_master_rvalid, - mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast, - - mem_master_rready); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [1 : 0] req_op; - input [2 : 0] req_f3; - input [6 : 0] req_amo_funct7; - input [63 : 0] req_addr; - input [63 : 0] req_st_value; - input [1 : 0] req_priv; - input req_sstatus_SUM; - input req_mstatus_MXR; - input [63 : 0] req_satp; - input EN_req; - - // value method valid - output valid; - - // value method addr - output [63 : 0] addr; - - // value method word64 - output [63 : 0] word64; - - // value method st_amo_val - output [63 : 0] st_amo_val; - - // value method exc - output exc; - - // value method exc_code - output [3 : 0] exc_code; - - // action method server_flush_request_put - input EN_server_flush_request_put; - output RDY_server_flush_request_put; - - // action method server_flush_response_get - input EN_server_flush_response_get; - output RDY_server_flush_response_get; - - // action method tlb_flush - input EN_tlb_flush; - output RDY_tlb_flush; - - // value method mem_master_m_awvalid - output mem_master_awvalid; - - // value method mem_master_m_awid - output [3 : 0] mem_master_awid; - - // value method mem_master_m_awaddr - output [63 : 0] mem_master_awaddr; - - // value method mem_master_m_awlen - output [7 : 0] mem_master_awlen; - - // value method mem_master_m_awsize - output [2 : 0] mem_master_awsize; - - // value method mem_master_m_awburst - output [1 : 0] mem_master_awburst; - - // value method mem_master_m_awlock - output mem_master_awlock; - - // value method mem_master_m_awcache - output [3 : 0] mem_master_awcache; - - // value method mem_master_m_awprot - output [2 : 0] mem_master_awprot; - - // value method mem_master_m_awqos - output [3 : 0] mem_master_awqos; - - // value method mem_master_m_awregion - output [3 : 0] mem_master_awregion; - - // value method mem_master_m_awuser - - // action method mem_master_m_awready - input mem_master_awready; - - // value method mem_master_m_wvalid - output mem_master_wvalid; - - // value method mem_master_m_wid - output [3 : 0] mem_master_wid; - - // value method mem_master_m_wdata - output [63 : 0] mem_master_wdata; - - // value method mem_master_m_wstrb - output [7 : 0] mem_master_wstrb; - - // value method mem_master_m_wlast - output mem_master_wlast; - - // value method mem_master_m_wuser - - // action method mem_master_m_wready - input mem_master_wready; - - // action method mem_master_m_bvalid - input mem_master_bvalid; - input [3 : 0] mem_master_bid; - input [1 : 0] mem_master_bresp; - - // value method mem_master_m_bready - output mem_master_bready; - - // value method mem_master_m_arvalid - output mem_master_arvalid; - - // value method mem_master_m_arid - output [3 : 0] mem_master_arid; - - // value method mem_master_m_araddr - output [63 : 0] mem_master_araddr; - - // value method mem_master_m_arlen - output [7 : 0] mem_master_arlen; - - // value method mem_master_m_arsize - output [2 : 0] mem_master_arsize; - - // value method mem_master_m_arburst - output [1 : 0] mem_master_arburst; - - // value method mem_master_m_arlock - output mem_master_arlock; - - // value method mem_master_m_arcache - output [3 : 0] mem_master_arcache; - - // value method mem_master_m_arprot - output [2 : 0] mem_master_arprot; - - // value method mem_master_m_arqos - output [3 : 0] mem_master_arqos; - - // value method mem_master_m_arregion - output [3 : 0] mem_master_arregion; - - // value method mem_master_m_aruser - - // action method mem_master_m_arready - input mem_master_arready; - - // action method mem_master_m_rvalid - input mem_master_rvalid; - input [3 : 0] mem_master_rid; - input [63 : 0] mem_master_rdata; - input [1 : 0] mem_master_rresp; - input mem_master_rlast; - - // value method mem_master_m_rready - output mem_master_rready; - - // signals for module outputs - reg [63 : 0] word64; - wire [63 : 0] addr, - mem_master_araddr, - mem_master_awaddr, - mem_master_wdata, - st_amo_val; - wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; - wire [3 : 0] exc_code, - mem_master_arcache, - mem_master_arid, - mem_master_arqos, - mem_master_arregion, - mem_master_awcache, - mem_master_awid, - mem_master_awqos, - mem_master_awregion, - mem_master_wid; - wire [2 : 0] mem_master_arprot, - mem_master_arsize, - mem_master_awprot, - mem_master_awsize; - wire [1 : 0] mem_master_arburst, mem_master_awburst; - wire RDY_server_flush_request_put, - RDY_server_flush_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_verbosity, - RDY_tlb_flush, - exc, - mem_master_arlock, - mem_master_arvalid, - mem_master_awlock, - mem_master_awvalid, - mem_master_bready, - mem_master_rready, - mem_master_wlast, - mem_master_wvalid, - valid; - - // inlined wires - reg [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1; - wire [10 : 0] crg_sb_to_load_delay$port0__write_1, - crg_sb_to_load_delay$port2__read; - wire [3 : 0] ctr_wr_rsps_pending_crg$port1__write_1, - ctr_wr_rsps_pending_crg$port2__read, - ctr_wr_rsps_pending_crg$port3__read; - wire crg_sb_to_load_delay$EN_port1__write, - ctr_wr_rsps_pending_crg$EN_port0__write, - ctr_wr_rsps_pending_crg$EN_port2__write, - dw_valid$whas, - master_xactor_crg_rd_addr_full$EN_port0__write, - master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port1__read, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port0__write, - master_xactor_crg_rd_data_full$EN_port1__write, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port1__read, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port0__write, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$EN_port2__write, - master_xactor_crg_wr_addr_full$port1__read, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port0__write, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$EN_port2__write, - master_xactor_crg_wr_data_full$port1__read, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read, - master_xactor_crg_wr_resp_full$EN_port0__write, - master_xactor_crg_wr_resp_full$EN_port2__write, - master_xactor_crg_wr_resp_full$port1__read, - master_xactor_crg_wr_resp_full$port2__read, - master_xactor_crg_wr_resp_full$port3__read; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_sb_to_load_delay - reg [10 : 0] crg_sb_to_load_delay; - wire [10 : 0] crg_sb_to_load_delay$D_IN; - wire crg_sb_to_load_delay$EN; - - // register ctr_wr_rsps_pending_crg - reg [3 : 0] ctr_wr_rsps_pending_crg; - wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN; - wire ctr_wr_rsps_pending_crg$EN; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - wire [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - reg [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [76 : 0] master_xactor_rg_wr_data; - reg [76 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - - // register rg_addr - reg [63 : 0] rg_addr; - wire [63 : 0] rg_addr$D_IN; - wire rg_addr$EN; - - // register rg_amo_funct7 - reg [6 : 0] rg_amo_funct7; - wire [6 : 0] rg_amo_funct7$D_IN; - wire rg_amo_funct7$EN; - - // register rg_cset_in_cache - reg [5 : 0] rg_cset_in_cache; - wire [5 : 0] rg_cset_in_cache$D_IN; - wire rg_cset_in_cache$EN; - - // register rg_error_during_refill - reg rg_error_during_refill; - wire rg_error_during_refill$D_IN, rg_error_during_refill$EN; - - // register rg_exc_code - reg [3 : 0] rg_exc_code; - reg [3 : 0] rg_exc_code$D_IN; - wire rg_exc_code$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_ld_val - reg [63 : 0] rg_ld_val; - reg [63 : 0] rg_ld_val$D_IN; - wire rg_ld_val$EN; - - // register rg_lower_word32 - reg [31 : 0] rg_lower_word32; - wire [31 : 0] rg_lower_word32$D_IN; - wire rg_lower_word32$EN; - - // register rg_lower_word32_full - reg rg_lower_word32_full; - wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN; - - // register rg_lrsc_pa - reg [63 : 0] rg_lrsc_pa; - wire [63 : 0] rg_lrsc_pa$D_IN; - wire rg_lrsc_pa$EN; - - // register rg_lrsc_valid - reg rg_lrsc_valid; - wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN; - - // register rg_op - reg [1 : 0] rg_op; - wire [1 : 0] rg_op$D_IN; - wire rg_op$EN; - - // register rg_pa - reg [63 : 0] rg_pa; - wire [63 : 0] rg_pa$D_IN; - wire rg_pa$EN; - - // register rg_pte_pa - reg [63 : 0] rg_pte_pa; - wire [63 : 0] rg_pte_pa$D_IN; - wire rg_pte_pa$EN; - - // register rg_st_amo_val - reg [63 : 0] rg_st_amo_val; - wire [63 : 0] rg_st_amo_val$D_IN; - wire rg_st_amo_val$EN; - - // register rg_state - reg [4 : 0] rg_state; - reg [4 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_word64_set_in_cache - reg [8 : 0] rg_word64_set_in_cache; - wire [8 : 0] rg_word64_set_in_cache$D_IN; - wire rg_word64_set_in_cache$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule ram_state_and_ctag_cset - wire [52 : 0] ram_state_and_ctag_cset$DIA, - ram_state_and_ctag_cset$DIB, - ram_state_and_ctag_cset$DOB; - wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB; - wire ram_state_and_ctag_cset$ENA, - ram_state_and_ctag_cset$ENB, - ram_state_and_ctag_cset$WEA, - ram_state_and_ctag_cset$WEB; - - // ports of submodule ram_word64_set - reg [63 : 0] ram_word64_set$DIB; - reg [8 : 0] ram_word64_set$ADDRB; - wire [63 : 0] ram_word64_set$DIA, ram_word64_set$DOB; - wire [8 : 0] ram_word64_set$ADDRA; - wire ram_word64_set$ENA, - ram_word64_set$ENB, - ram_word64_set$WEA, - ram_word64_set$WEB; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - wire soc_map$m_is_mem_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_ST_AMO_response, - CAN_FIRE_RL_rl_cache_refill_rsps_loop, - CAN_FIRE_RL_rl_discard_write_rsp, - CAN_FIRE_RL_rl_drive_exception_rsp, - CAN_FIRE_RL_rl_io_AMO_SC_req, - CAN_FIRE_RL_rl_io_AMO_op_req, - CAN_FIRE_RL_rl_io_AMO_read_rsp, - CAN_FIRE_RL_rl_io_read_req, - CAN_FIRE_RL_rl_io_read_rsp, - CAN_FIRE_RL_rl_io_write_req, - CAN_FIRE_RL_rl_maintain_io_read_rsp, - CAN_FIRE_RL_rl_probe_and_immed_rsp, - CAN_FIRE_RL_rl_rereq, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_shift_sb_to_load_delay, - CAN_FIRE_RL_rl_start_cache_refill, - CAN_FIRE_RL_rl_start_reset, - CAN_FIRE_mem_master_m_arready, - CAN_FIRE_mem_master_m_awready, - CAN_FIRE_mem_master_m_bvalid, - CAN_FIRE_mem_master_m_rvalid, - CAN_FIRE_mem_master_m_wready, - CAN_FIRE_req, - CAN_FIRE_server_flush_request_put, - CAN_FIRE_server_flush_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_verbosity, - CAN_FIRE_tlb_flush, - WILL_FIRE_RL_rl_ST_AMO_response, - WILL_FIRE_RL_rl_cache_refill_rsps_loop, - WILL_FIRE_RL_rl_discard_write_rsp, - WILL_FIRE_RL_rl_drive_exception_rsp, - WILL_FIRE_RL_rl_io_AMO_SC_req, - WILL_FIRE_RL_rl_io_AMO_op_req, - WILL_FIRE_RL_rl_io_AMO_read_rsp, - WILL_FIRE_RL_rl_io_read_req, - WILL_FIRE_RL_rl_io_read_rsp, - WILL_FIRE_RL_rl_io_write_req, - WILL_FIRE_RL_rl_maintain_io_read_rsp, - WILL_FIRE_RL_rl_probe_and_immed_rsp, - WILL_FIRE_RL_rl_rereq, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_shift_sb_to_load_delay, - WILL_FIRE_RL_rl_start_cache_refill, - WILL_FIRE_RL_rl_start_reset, - WILL_FIRE_mem_master_m_arready, - WILL_FIRE_mem_master_m_awready, - WILL_FIRE_mem_master_m_bvalid, - WILL_FIRE_mem_master_m_rvalid, - WILL_FIRE_mem_master_m_wready, - WILL_FIRE_req, - WILL_FIRE_server_flush_request_put, - WILL_FIRE_server_flush_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_verbosity, - WILL_FIRE_tlb_flush; - - // inputs to muxes for submodule ports - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2, - MUX_master_xactor_rg_wr_addr$write_1__VAL_1, - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - wire [76 : 0] MUX_master_xactor_rg_wr_data$write_1__VAL_1, - MUX_master_xactor_rg_wr_data$write_1__VAL_2, - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3, - MUX_ram_word64_set$a_put_3__VAL_2, - MUX_rg_ld_val$write_1__VAL_2; - wire [52 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1; - wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2, - MUX_ram_word64_set$b_put_2__VAL_4; - wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1; - wire [4 : 0] MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_4, - MUX_rg_state$write_1__VAL_8, - MUX_rg_state$write_1__VAL_9; - wire [3 : 0] MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_1; - wire MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1, - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2, - MUX_dw_output_ld_val$wset_1__SEL_1, - MUX_dw_output_ld_val$wset_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_4, - MUX_master_xactor_rg_rd_addr$write_1__SEL_1, - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1, - MUX_ram_word64_set$a_put_1__SEL_1, - MUX_ram_word64_set$b_put_1__SEL_2, - MUX_rg_error_during_refill$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_2, - MUX_rg_exc_code$write_1__SEL_3, - MUX_rg_ld_val$write_1__SEL_2, - MUX_rg_lrsc_valid$write_1__SEL_2, - MUX_rg_state$write_1__SEL_13, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h3732; - reg [31 : 0] v__h3833; - reg [31 : 0] v__h25363; - reg [31 : 0] v__h26261; - reg [31 : 0] v__h3369; - reg [31 : 0] v__h4286; - reg [31 : 0] v__h12754; - reg [31 : 0] v__h17070; - reg [31 : 0] v__h16398; - reg [31 : 0] v__h20536; - reg [31 : 0] v__h21830; - reg [31 : 0] v__h22071; - reg [31 : 0] v__h24049; - reg [31 : 0] v__h25151; - reg [31 : 0] v__h25258; - reg [31 : 0] v__h25443; - reg [31 : 0] v__h25965; - reg [31 : 0] v__h26379; - reg [31 : 0] v__h26697; - reg [31 : 0] v__h26872; - reg [31 : 0] v__h29485; - reg [31 : 0] v__h29737; - reg [31 : 0] v__h26968; - reg [31 : 0] v__h20981; - reg [31 : 0] v__h23675; - reg [31 : 0] v__h30707; - reg [31 : 0] v__h30357; - reg [31 : 0] v__h30318; - reg [31 : 0] v__h26962; - reg [31 : 0] v__h3363; - reg [31 : 0] v__h3726; - reg [31 : 0] v__h3827; - reg [31 : 0] v__h4280; - reg [31 : 0] v__h12748; - reg [31 : 0] v__h16392; - reg [31 : 0] v__h17064; - reg [31 : 0] v__h20530; - reg [31 : 0] v__h20975; - reg [31 : 0] v__h21824; - reg [31 : 0] v__h22065; - reg [31 : 0] v__h23669; - reg [31 : 0] v__h24043; - reg [31 : 0] v__h25145; - reg [31 : 0] v__h25252; - reg [31 : 0] v__h25357; - reg [31 : 0] v__h25437; - reg [31 : 0] v__h25959; - reg [31 : 0] v__h26255; - reg [31 : 0] v__h26373; - reg [31 : 0] v__h26691; - reg [31 : 0] v__h26866; - reg [31 : 0] v__h29479; - reg [31 : 0] v__h29731; - reg [31 : 0] v__h30312; - reg [31 : 0] v__h30351; - reg [31 : 0] v__h30701; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32, - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51, - CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29, - CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33, - CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34, - CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425, - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360, - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434, - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302, - _theResult_____2__h17629, - _theResult_____2__h27290, - ld_val__h24158, - mem_req_wr_data_wdata__h16835, - mem_req_wr_data_wdata__h20332, - mem_req_wr_data_wdata__h25761, - mem_req_wr_data_wdata__h27265, - new_ld_val__h26998, - new_value__h15489, - new_value__h5462, - w1__h17621, - w1__h27278, - w1__h27282; - reg [7 : 0] mem_req_wr_data_wstrb__h20333, mem_req_wr_data_wstrb__h27266; - reg [2 : 0] value__h26583, value__h29609; - wire [63 : 0] IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257, - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366, - IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d466, - _theResult___snd_fst__h16843, - _theResult___snd_fst__h20340, - _theResult___snd_fst__h25769, - _theResult___snd_fst__h27273, - cline_fabric_addr__h21034, - new_st_val__h17351, - new_st_val__h17633, - new_st_val__h17724, - new_st_val__h18704, - new_st_val__h18708, - new_st_val__h18712, - new_st_val__h18716, - new_st_val__h18721, - new_st_val__h18727, - new_st_val__h18732, - new_st_val__h27294, - new_st_val__h27385, - new_st_val__h29245, - new_st_val__h29249, - new_st_val__h29253, - new_st_val__h29257, - new_st_val__h29262, - new_st_val__h29268, - new_st_val__h29273, - result__h11871, - result__h11899, - result__h11927, - result__h11955, - result__h11983, - result__h12011, - result__h12039, - result__h12084, - result__h12112, - result__h12140, - result__h12168, - result__h12196, - result__h12224, - result__h12252, - result__h12280, - result__h12325, - result__h12353, - result__h12381, - result__h12409, - result__h12450, - result__h12478, - result__h12506, - result__h12534, - result__h12575, - result__h12603, - result__h12642, - result__h12670, - result__h24218, - result__h24248, - result__h24275, - result__h24302, - result__h24329, - result__h24356, - result__h24383, - result__h24410, - result__h24454, - result__h24481, - result__h24508, - result__h24535, - result__h24562, - result__h24589, - result__h24616, - result__h24643, - result__h24687, - result__h24714, - result__h24741, - result__h24768, - result__h24808, - result__h24835, - result__h24862, - result__h24889, - result__h24929, - result__h24956, - result__h24994, - result__h25021, - result__h27473, - result__h28381, - result__h28409, - result__h28437, - result__h28465, - result__h28493, - result__h28521, - result__h28549, - result__h28594, - result__h28622, - result__h28650, - result__h28678, - result__h28706, - result__h28734, - result__h28762, - result__h28790, - result__h28835, - result__h28863, - result__h28891, - result__h28919, - result__h28960, - result__h28988, - result__h29016, - result__h29044, - result__h29085, - result__h29113, - result__h29152, - result__h29180, - result__h5515, - st_val__h27010, - w1___1__h17692, - w1___1__h27353, - w2___1__h27354, - w2__h27284, - word64__h5281, - x__h13141, - y__h5551; - wire [31 : 0] ld_val4158_BITS_31_TO_0__q37, - ld_val4158_BITS_63_TO_32__q44, - master_xactor_rg_rd_data_BITS_34_TO_3__q3, - master_xactor_rg_rd_data_BITS_66_TO_35__q10, - new_value462_BITS_31_TO_0__q30, - rg_st_amo_val_BITS_31_TO_0__q31, - w17278_BITS_31_TO_0__q50, - word64281_BITS_31_TO_0__q17, - word64281_BITS_63_TO_32__q24; - wire [15 : 0] ld_val4158_BITS_15_TO_0__q36, - ld_val4158_BITS_31_TO_16__q40, - ld_val4158_BITS_47_TO_32__q43, - ld_val4158_BITS_63_TO_48__q47, - master_xactor_rg_rd_data_BITS_18_TO_3__q2, - master_xactor_rg_rd_data_BITS_34_TO_19__q6, - master_xactor_rg_rd_data_BITS_50_TO_35__q9, - master_xactor_rg_rd_data_BITS_66_TO_51__q13, - word64281_BITS_15_TO_0__q16, - word64281_BITS_31_TO_16__q20, - word64281_BITS_47_TO_32__q23, - word64281_BITS_63_TO_48__q27; - wire [7 : 0] ld_val4158_BITS_15_TO_8__q38, - ld_val4158_BITS_23_TO_16__q39, - ld_val4158_BITS_31_TO_24__q41, - ld_val4158_BITS_39_TO_32__q42, - ld_val4158_BITS_47_TO_40__q45, - ld_val4158_BITS_55_TO_48__q46, - ld_val4158_BITS_63_TO_56__q48, - ld_val4158_BITS_7_TO_0__q35, - master_xactor_rg_rd_data_BITS_10_TO_3__q1, - master_xactor_rg_rd_data_BITS_18_TO_11__q4, - master_xactor_rg_rd_data_BITS_26_TO_19__q5, - master_xactor_rg_rd_data_BITS_34_TO_27__q7, - master_xactor_rg_rd_data_BITS_42_TO_35__q8, - master_xactor_rg_rd_data_BITS_50_TO_43__q11, - master_xactor_rg_rd_data_BITS_58_TO_51__q12, - master_xactor_rg_rd_data_BITS_66_TO_59__q14, - strobe64__h20266, - strobe64__h20268, - strobe64__h20270, - strobe64__h27199, - strobe64__h27201, - strobe64__h27203, - word64281_BITS_15_TO_8__q18, - word64281_BITS_23_TO_16__q19, - word64281_BITS_31_TO_24__q21, - word64281_BITS_39_TO_32__q22, - word64281_BITS_47_TO_40__q25, - word64281_BITS_55_TO_48__q26, - word64281_BITS_63_TO_56__q28, - word64281_BITS_7_TO_0__q15; - wire [5 : 0] shift_bits__h20133, shift_bits__h27066; - wire [4 : 0] IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d110, - IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d109; - wire [3 : 0] access_exc_code__h2925, b__h20935; - wire IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d78, - NOT_cfg_verbosity_read__0_ULE_1_1___d12, - NOT_cfg_verbosity_read__0_ULE_2_54___d555, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d309, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d443, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d479, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d491, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d519, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d532, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d534, - NOT_ram_state_and_ctag_cset_b_read__9_BIT_52_0_ETC___d119, - NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911, - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d105, - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446, - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494, - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502, - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d128, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d440, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d517, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d520, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d524, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d530, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d304, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d438, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d492, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d496, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d500, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d505, - dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d80, - lrsc_result__h13131, - master_xactor_crg_rd_data_full_port1__read__51_ETC___d723, - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74, - ram_state_and_ctag_cset_b_read__9_BIT_52_0_AND_ETC___d120, - req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920, - rg_addr_0_EQ_rg_lrsc_pa_8___d117, - rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d292, - rg_lrsc_pa_8_EQ_rg_addr_0___d59, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d100, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d288, - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d129, - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d307, - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d441, - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d444, - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513, - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d68, - rg_state_EQ_13_90_AND_rg_op_4_EQ_0_5_OR_rg_op__ETC___d592, - rg_state_EQ_3_1_AND_NOT_rg_op_4_EQ_0_5_2_AND_N_ETC___d90; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method addr - assign addr = rg_addr ; - - // value method word64 - always@(MUX_dw_output_ld_val$wset_1__SEL_1 or - ld_val__h24158 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h26998 or - MUX_dw_output_ld_val$wset_1__SEL_3 or - MUX_dw_output_ld_val$wset_1__VAL_3 or - MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h24158; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - word64 = new_ld_val__h26998; - MUX_dw_output_ld_val$wset_1__SEL_3: - word64 = MUX_dw_output_ld_val$wset_1__VAL_3; - MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val; - default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // value method st_amo_val - assign st_amo_val = - MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ; - - // value method exc - assign exc = rg_state == 5'd4 ; - - // value method exc_code - assign exc_code = rg_exc_code ; - - // action method server_flush_request_put - assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; - - // action method server_flush_response_get - assign RDY_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; - - // action method tlb_flush - assign RDY_tlb_flush = 1'd1 ; - assign CAN_FIRE_tlb_flush = 1'd1 ; - assign WILL_FIRE_tlb_flush = EN_tlb_flush ; - - // value method mem_master_m_awvalid - assign mem_master_awvalid = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - - // value method mem_master_m_awid - assign mem_master_awid = master_xactor_rg_wr_addr[96:93] ; - - // value method mem_master_m_awaddr - assign mem_master_awaddr = master_xactor_rg_wr_addr[92:29] ; - - // value method mem_master_m_awlen - assign mem_master_awlen = master_xactor_rg_wr_addr[28:21] ; - - // value method mem_master_m_awsize - assign mem_master_awsize = master_xactor_rg_wr_addr[20:18] ; - - // value method mem_master_m_awburst - assign mem_master_awburst = master_xactor_rg_wr_addr[17:16] ; - - // value method mem_master_m_awlock - assign mem_master_awlock = master_xactor_rg_wr_addr[15] ; - - // value method mem_master_m_awcache - assign mem_master_awcache = master_xactor_rg_wr_addr[14:11] ; - - // value method mem_master_m_awprot - assign mem_master_awprot = master_xactor_rg_wr_addr[10:8] ; - - // value method mem_master_m_awqos - assign mem_master_awqos = master_xactor_rg_wr_addr[7:4] ; - - // value method mem_master_m_awregion - assign mem_master_awregion = master_xactor_rg_wr_addr[3:0] ; - - // action method mem_master_m_awready - assign CAN_FIRE_mem_master_m_awready = 1'd1 ; - assign WILL_FIRE_mem_master_m_awready = 1'd1 ; - - // value method mem_master_m_wvalid - assign mem_master_wvalid = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - - // value method mem_master_m_wid - assign mem_master_wid = master_xactor_rg_wr_data[76:73] ; - - // value method mem_master_m_wdata - assign mem_master_wdata = master_xactor_rg_wr_data[72:9] ; - - // value method mem_master_m_wstrb - assign mem_master_wstrb = master_xactor_rg_wr_data[8:1] ; - - // value method mem_master_m_wlast - assign mem_master_wlast = master_xactor_rg_wr_data[0] ; - - // action method mem_master_m_wready - assign CAN_FIRE_mem_master_m_wready = 1'd1 ; - assign WILL_FIRE_mem_master_m_wready = 1'd1 ; - - // action method mem_master_m_bvalid - assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ; - - // value method mem_master_m_bready - assign mem_master_bready = !master_xactor_crg_wr_resp_full$port2__read ; - - // value method mem_master_m_arvalid - assign mem_master_arvalid = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - - // value method mem_master_m_arid - assign mem_master_arid = master_xactor_rg_rd_addr[96:93] ; - - // value method mem_master_m_araddr - assign mem_master_araddr = master_xactor_rg_rd_addr[92:29] ; - - // value method mem_master_m_arlen - assign mem_master_arlen = master_xactor_rg_rd_addr[28:21] ; - - // value method mem_master_m_arsize - assign mem_master_arsize = master_xactor_rg_rd_addr[20:18] ; - - // value method mem_master_m_arburst - assign mem_master_arburst = master_xactor_rg_rd_addr[17:16] ; - - // value method mem_master_m_arlock - assign mem_master_arlock = master_xactor_rg_rd_addr[15] ; - - // value method mem_master_m_arcache - assign mem_master_arcache = master_xactor_rg_rd_addr[14:11] ; - - // value method mem_master_m_arprot - assign mem_master_arprot = master_xactor_rg_rd_addr[10:8] ; - - // value method mem_master_m_arqos - assign mem_master_arqos = master_xactor_rg_rd_addr[7:4] ; - - // value method mem_master_m_arregion - assign mem_master_arregion = master_xactor_rg_rd_addr[3:0] ; - - // action method mem_master_m_arready - assign CAN_FIRE_mem_master_m_arready = 1'd1 ; - assign WILL_FIRE_mem_master_m_arready = 1'd1 ; - - // action method mem_master_m_rvalid - assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ; - - // value method mem_master_m_rready - assign mem_master_rready = !master_xactor_crg_rd_data_full$port2__read ; - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule ram_state_and_ctag_cset - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd6), - .DATA_WIDTH(32'd53), - .MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_state_and_ctag_cset$ADDRA), - .ADDRB(ram_state_and_ctag_cset$ADDRB), - .DIA(ram_state_and_ctag_cset$DIA), - .DIB(ram_state_and_ctag_cset$DIB), - .WEA(ram_state_and_ctag_cset$WEA), - .WEB(ram_state_and_ctag_cset$WEB), - .ENA(ram_state_and_ctag_cset$ENA), - .ENB(ram_state_and_ctag_cset$ENB), - .DOA(), - .DOB(ram_state_and_ctag_cset$DOB)); - - // submodule ram_word64_set - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd9), - .DATA_WIDTH(32'd64), - .MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_word64_set$ADDRA), - .ADDRB(ram_word64_set$ADDRB), - .DIA(ram_word64_set$DIA), - .DIB(ram_word64_set$DIB), - .WEA(ram_word64_set$WEA), - .WEB(ram_word64_set$WEB), - .ENA(ram_word64_set$ENA), - .ENB(ram_word64_set$ENB), - .DOA(), - .DOB(ram_word64_set$DOB)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(soc_map$m_is_mem_addr), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - (rg_cset_in_cache != 6'd63 || - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) && - rg_state == 5'd1 ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // rule RL_rl_shift_sb_to_load_delay - assign CAN_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - assign WILL_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - - // rule RL_rl_rereq - assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ; - assign WILL_FIRE_RL_rl_rereq = - CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ; - - // rule RL_rl_ST_AMO_response - assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ; - assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ; - - // rule RL_rl_maintain_io_read_rsp - assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ; - assign WILL_FIRE_RL_rl_maintain_io_read_rsp = - CAN_FIRE_RL_rl_maintain_io_read_rsp ; - - // rule RL_rl_io_AMO_SC_req - assign CAN_FIRE_RL_rl_io_AMO_SC_req = - rg_state == 5'd13 && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_SC_req = - CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_drive_exception_rsp - assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ; - assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ; - - // rule RL_rl_start_reset - assign CAN_FIRE_RL_rl_start_reset = - f_reset_reqs$EMPTY_N && rg_state != 5'd1 ; - assign WILL_FIRE_RL_rl_start_reset = CAN_FIRE_RL_rl_start_reset ; - - // rule RL_rl_probe_and_immed_rsp - assign CAN_FIRE_RL_rl_probe_and_immed_rsp = - dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d80 && - rg_state_EQ_3_1_AND_NOT_rg_op_4_EQ_0_5_2_AND_N_ETC___d90 ; - assign WILL_FIRE_RL_rl_probe_and_immed_rsp = - CAN_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_cache_refill_rsps_loop - assign CAN_FIRE_RL_rl_cache_refill_rsps_loop = - master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd10 ; - assign WILL_FIRE_RL_rl_cache_refill_rsps_loop = - CAN_FIRE_RL_rl_cache_refill_rsps_loop && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_rsp - assign CAN_FIRE_RL_rl_io_read_rsp = - master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd14 ; - assign WILL_FIRE_RL_rl_io_read_rsp = - CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_write_req - assign CAN_FIRE_RL_rl_io_write_req = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - rg_state == 5'd13 && - rg_op == 2'd1 ; - assign WILL_FIRE_RL_rl_io_write_req = - CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_op_req - assign CAN_FIRE_RL_rl_io_AMO_op_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 5'd13 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] != 5'b00010 && - rg_amo_funct7[6:2] != 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_op_req = - CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_read_rsp - assign CAN_FIRE_RL_rl_io_AMO_read_rsp = - master_xactor_crg_rd_data_full_port1__read__51_ETC___d723 && - rg_state == 5'd16 ; - assign WILL_FIRE_RL_rl_io_AMO_read_rsp = - CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_cache_refill - assign CAN_FIRE_RL_rl_start_cache_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 5'd9 && - b__h20935 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_cache_refill = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_io_read_req - assign CAN_FIRE_RL_rl_io_read_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state_EQ_13_90_AND_rg_op_4_EQ_0_5_OR_rg_op__ETC___d592 ; - assign WILL_FIRE_RL_rl_io_read_req = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_discard_write_rsp - assign CAN_FIRE_RL_rl_discard_write_rsp = - b__h20935 != 4'd0 && master_xactor_crg_wr_resp_full$port1__read ; - assign WILL_FIRE_RL_rl_discard_write_rsp = - CAN_FIRE_RL_rl_discard_write_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // inputs to muxes for submodule ports - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 ; - assign MUX_dw_output_ld_val$wset_1__SEL_1 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_dw_output_ld_val$wset_1__SEL_3 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136 ; - assign MUX_dw_output_ld_val$wset_1__SEL_4 = - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_1 = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ; - assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 = - EN_req && - req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 ; - assign MUX_ram_word64_set$a_put_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ram_word64_set$b_put_1__SEL_2 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 ; - assign MUX_rg_error_during_refill$write_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_1 = - EN_req && - NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 ; - assign MUX_rg_exc_code$write_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_3 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_ld_val$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298 ; - assign MUX_rg_lrsc_valid$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ; - assign MUX_rg_state$write_1__SEL_3 = - CAN_FIRE_RL_rl_start_cache_refill && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - assign MUX_rg_state$write_1__SEL_8 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 ; - assign MUX_rg_state$write_1__SEL_9 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (dmem_not_imem && !soc_map$m_is_mem_addr || - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d100 || - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d105) ; - assign MUX_rg_state$write_1__SEL_13 = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 = - ctr_wr_rsps_pending_crg + 4'd1 ; - assign MUX_dw_output_ld_val$wset_1__VAL_3 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - new_value__h5462 : - new_value__h15489 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, rg_pa, 8'd0, value__h26583, 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, cline_fabric_addr__h21034, 29'd15532032 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_1 = - { 4'd0, rg_pa, 8'd0, value__h29609, 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_2 = - { 4'd0, rg_addr, 8'd0, value__h29609, 18'd65536 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_1 = - { 4'd0, - mem_req_wr_data_wdata__h27265, - mem_req_wr_data_wstrb__h27266, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_2 = - { 4'd0, - IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d466, - mem_req_wr_data_wstrb__h20333, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_3 = - { 4'd0, - mem_req_wr_data_wdata__h25761, - mem_req_wr_data_wstrb__h27266, - 1'd1 } ; - assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 = { 1'd1, rg_pa[63:12] } ; - assign MUX_ram_word64_set$a_put_3__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 : - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 ; - assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ; - assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ; - assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ; - assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ; - assign MUX_rg_ld_val$write_1__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - x__h13141 : - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 ; - assign MUX_rg_state$write_1__VAL_1 = - NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 ? - 5'd4 : - 5'd3 ; - assign MUX_rg_state$write_1__VAL_4 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? 5'd15 : 5'd4 ; - assign MUX_rg_state$write_1__VAL_8 = - (master_xactor_rg_rd_data[2:1] != 2'b0 || - rg_error_during_refill) ? - 5'd4 : - 5'd11 ; - assign MUX_rg_state$write_1__VAL_9 = - (dmem_not_imem && !soc_map$m_is_mem_addr) ? - 5'd13 : - IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d110 ; - - // inlined wires - assign dw_valid$whas = - (WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_io_read_rsp) && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136 || - WILL_FIRE_RL_rl_drive_exception_rsp || - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign master_xactor_crg_wr_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_addr_full$port1__read = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full$port1__read && - mem_master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full$port1__read ; - assign master_xactor_crg_wr_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 || - WILL_FIRE_RL_rl_io_write_req ; - assign master_xactor_crg_wr_addr_full$port3__read = - master_xactor_crg_wr_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_data_full$port1__read = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full$port1__read && mem_master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full$port1__read ; - assign master_xactor_crg_wr_data_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 || - WILL_FIRE_RL_rl_io_write_req ; - assign master_xactor_crg_wr_data_full$port3__read = - master_xactor_crg_wr_data_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_wr_resp_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_resp_full$port1__read = - !master_xactor_crg_wr_resp_full$EN_port0__write && - master_xactor_crg_wr_resp_full ; - assign master_xactor_crg_wr_resp_full$port2__read = - !WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_crg_wr_resp_full$port1__read ; - assign master_xactor_crg_wr_resp_full$EN_port2__write = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_wr_resp_full$port3__read = - master_xactor_crg_wr_resp_full$EN_port2__write || - master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_addr_full$port1__read = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full$port1__read && - mem_master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full$port1__read ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write || - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_data_full$port1__read = - !master_xactor_crg_rd_data_full$EN_port0__write && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port1__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp || WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_cache_refill_rsps_loop ; - assign master_xactor_crg_rd_data_full$port2__read = - !master_xactor_crg_rd_data_full$EN_port1__write && - master_xactor_crg_rd_data_full$port1__read ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - mem_master_rvalid && - !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - assign ctr_wr_rsps_pending_crg$EN_port0__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 || - WILL_FIRE_RL_rl_io_write_req ; - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - WILL_FIRE_RL_rl_io_write_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - WILL_FIRE_RL_rl_io_write_req: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - default: ctr_wr_rsps_pending_crg$port0__write_1 = - 4'b1010 /* unspecified value */ ; - endcase - end - assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h20935 - 4'd1 ; - assign ctr_wr_rsps_pending_crg$port2__read = - WILL_FIRE_RL_rl_discard_write_rsp ? - ctr_wr_rsps_pending_crg$port1__write_1 : - b__h20935 ; - assign ctr_wr_rsps_pending_crg$EN_port2__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign ctr_wr_rsps_pending_crg$port3__read = - ctr_wr_rsps_pending_crg$EN_port2__write ? - 4'd0 : - ctr_wr_rsps_pending_crg$port2__read ; - assign crg_sb_to_load_delay$port0__write_1 = - { 1'd0, crg_sb_to_load_delay[10:1] } ; - assign crg_sb_to_load_delay$EN_port1__write = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d443 ; - assign crg_sb_to_load_delay$port2__read = - crg_sb_to_load_delay$EN_port1__write ? - 11'd2047 : - crg_sb_to_load_delay$port0__write_1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register crg_sb_to_load_delay - assign crg_sb_to_load_delay$D_IN = crg_sb_to_load_delay$port2__read ; - assign crg_sb_to_load_delay$EN = 1'b1 ; - - // register ctr_wr_rsps_pending_crg - assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ; - assign ctr_wr_rsps_pending_crg$EN = 1'b1 ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = - master_xactor_crg_wr_resp_full$port3__read ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - assign master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__SEL_1 ? - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 : - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ; - assign master_xactor_rg_rd_addr$EN = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - default: master_xactor_rg_wr_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_addr$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_data - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_data$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_data$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req or - MUX_master_xactor_rg_wr_data$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - default: master_xactor_rg_wr_data$D_IN = - 77'h0AAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_data$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = - { mem_master_bid, mem_master_bresp } ; - assign master_xactor_rg_wr_resp$EN = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - - // register rg_addr - assign rg_addr$D_IN = req_addr ; - assign rg_addr$EN = EN_req ; - - // register rg_amo_funct7 - assign rg_amo_funct7$D_IN = req_amo_funct7 ; - assign rg_amo_funct7$EN = EN_req ; - - // register rg_cset_in_cache - assign rg_cset_in_cache$D_IN = - WILL_FIRE_RL_rl_reset ? - MUX_rg_cset_in_cache$write_1__VAL_1 : - 6'd0 ; - assign rg_cset_in_cache$EN = - WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ; - - // register rg_error_during_refill - assign rg_error_during_refill$D_IN = - MUX_rg_error_during_refill$write_1__SEL_1 ; - assign rg_error_during_refill$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register rg_exc_code - always@(MUX_rg_exc_code$write_1__SEL_1 or - MUX_rg_exc_code$write_1__VAL_1 or - MUX_rg_exc_code$write_1__SEL_2 or - MUX_rg_exc_code$write_1__SEL_3 or - MUX_rg_error_during_refill$write_1__SEL_1 or access_exc_code__h2925) - case (1'b1) - MUX_rg_exc_code$write_1__SEL_1: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1; - MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7; - MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5; - MUX_rg_error_during_refill$write_1__SEL_1: - rg_exc_code$D_IN = access_exc_code__h2925; - default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_exc_code$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - EN_req && - NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_ld_val - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h26998 or - MUX_rg_ld_val$write_1__SEL_2 or - MUX_rg_ld_val$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_rsp or - ld_val__h24158 or WILL_FIRE_RL_rl_io_AMO_SC_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - rg_ld_val$D_IN = new_ld_val__h26998; - MUX_rg_ld_val$write_1__SEL_2: - rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h24158; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1; - default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_ld_val$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_SC_req ; - - // register rg_lower_word32 - assign rg_lower_word32$D_IN = 32'h0 ; - assign rg_lower_word32$EN = 1'b0 ; - - // register rg_lower_word32_full - assign rg_lower_word32_full$D_IN = 1'd0 ; - assign rg_lower_word32_full$EN = - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_lrsc_pa - assign rg_lrsc_pa$D_IN = rg_addr ; - assign rg_lrsc_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ; - - // register rg_lrsc_valid - assign rg_lrsc_valid$D_IN = - MUX_rg_lrsc_valid$write_1__SEL_2 && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133 ; - assign rg_lrsc_valid$EN = - WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131 || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_op - assign rg_op$D_IN = req_op ; - assign rg_op$EN = EN_req ; - - // register rg_pa - assign rg_pa$D_IN = EN_req ? req_addr : rg_addr ; - assign rg_pa$EN = EN_req || WILL_FIRE_RL_rl_probe_and_immed_rsp ; - - // register rg_pte_pa - assign rg_pte_pa$D_IN = 64'h0 ; - assign rg_pte_pa$EN = 1'b0 ; - - // register rg_st_amo_val - assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h17351 ; - assign rg_st_amo_val$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d534 || - EN_req ; - - // register rg_state - always@(EN_req or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_io_read_req or - WILL_FIRE_RL_rl_start_cache_refill or - WILL_FIRE_RL_rl_io_AMO_read_rsp or - MUX_rg_state$write_1__VAL_4 or - WILL_FIRE_RL_rl_io_AMO_op_req or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_io_read_rsp or - MUX_rg_state$write_1__SEL_8 or - MUX_rg_state$write_1__VAL_8 or - MUX_rg_state$write_1__SEL_9 or - MUX_rg_state$write_1__VAL_9 or - WILL_FIRE_RL_rl_start_reset or - WILL_FIRE_RL_rl_io_AMO_SC_req or - WILL_FIRE_RL_rl_rereq or MUX_rg_state$write_1__SEL_13) - case (1'b1) - EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14; - WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10; - WILL_FIRE_RL_rl_io_AMO_read_rsp: - rg_state$D_IN = MUX_rg_state$write_1__VAL_4; - WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16; - WILL_FIRE_RL_rl_io_write_req: rg_state$D_IN = 5'd12; - WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_4; - MUX_rg_state$write_1__SEL_8: rg_state$D_IN = MUX_rg_state$write_1__VAL_8; - MUX_rg_state$write_1__SEL_9: rg_state$D_IN = MUX_rg_state$write_1__VAL_9; - WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_state$D_IN = 5'd12; - WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3; - MUX_rg_state$write_1__SEL_13: rg_state$D_IN = 5'd2; - default: rg_state$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_state$EN = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 || - MUX_rg_state$write_1__SEL_9 || - WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_io_read_rsp || - EN_req || - WILL_FIRE_RL_rl_start_reset || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_io_AMO_SC_req || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_io_AMO_op_req ; - - // register rg_word64_set_in_cache - assign rg_word64_set_in_cache$D_IN = - MUX_ram_word64_set$b_put_1__SEL_2 ? - MUX_ram_word64_set$b_put_2__VAL_2 : - MUX_ram_word64_set$b_put_2__VAL_4 ; - assign rg_word64_set_in_cache$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = !EN_server_reset_request_put ; - assign f_reset_reqs$ENQ = - EN_server_reset_request_put || EN_server_flush_request_put ; - assign f_reset_reqs$DEQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ; - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign f_reset_rsps$DEQ = - EN_server_flush_response_get || EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule ram_state_and_ctag_cset - assign ram_state_and_ctag_cset$ADDRA = - WILL_FIRE_RL_rl_start_cache_refill ? - rg_addr[11:6] : - rg_cset_in_cache ; - assign ram_state_and_ctag_cset$ADDRB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - req_addr[11:6] : - rg_addr[11:6] ; - assign ram_state_and_ctag_cset$DIA = - WILL_FIRE_RL_rl_start_cache_refill ? - MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 : - 53'h0AAAAAAAAAAAAA ; - assign ram_state_and_ctag_cset$DIB = - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ? - 53'h0AAAAAAAAAAAAA /* unspecified value */ : - 53'h0AAAAAAAAAAAAA /* unspecified value */ ; - assign ram_state_and_ctag_cset$WEA = 1'd1 ; - assign ram_state_and_ctag_cset$WEB = 1'd0 ; - assign ram_state_and_ctag_cset$ENA = - WILL_FIRE_RL_rl_start_cache_refill || WILL_FIRE_RL_rl_reset ; - assign ram_state_and_ctag_cset$ENB = - EN_req && - req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 || - WILL_FIRE_RL_rl_rereq ; - - // submodule ram_word64_set - assign ram_word64_set$ADDRA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - rg_word64_set_in_cache : - rg_addr[11:3] ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - req_addr or - MUX_ram_word64_set$b_put_1__SEL_2 or - MUX_ram_word64_set$b_put_2__VAL_2 or - WILL_FIRE_RL_rl_rereq or - rg_addr or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_ram_word64_set$b_put_2__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$ADDRB = req_addr[11:3]; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2; - WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3]; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4; - default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ; - endcase - end - assign ram_word64_set$DIA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - master_xactor_rg_rd_data[66:3] : - MUX_ram_word64_set$a_put_3__VAL_2 ; - always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or - MUX_ram_word64_set$b_put_1__SEL_2 or - WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_1__SEL_1: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_rereq: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - default: ram_word64_set$DIB = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign ram_word64_set$WEA = 1'd1 ; - assign ram_word64_set$WEB = 1'd0 ; - assign ram_word64_set$ENA = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d309 ; - assign ram_word64_set$ENB = - EN_req && - req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = rg_addr ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271 = - (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 = - (rg_addr[2:0] == 3'h0) ? ld_val__h24158 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 = - (rg_addr[2:0] == 3'h0) ? word64__h5281 : 64'd0 ; - assign IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 = - (rg_f3 == 3'b010) ? - { {32{rg_st_amo_val_BITS_31_TO_0__q31[31]}}, - rg_st_amo_val_BITS_31_TO_0__q31 } : - rg_st_amo_val ; - assign IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d110 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 5'd9 : - IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d109 ; - assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d109 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - 5'd12 : - ((!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) ? - 5'd9 : - 5'd12) ; - assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d466 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - mem_req_wr_data_wdata__h16835 : - mem_req_wr_data_wdata__h20332 ; - assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d78 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d68 : - !ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read ; - assign NOT_cfg_verbosity_read__0_ULE_1_1___d12 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read__0_ULE_2_54___d555 = cfg_verbosity > 4'd2 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - rg_op != 2'd1 && ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d309 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d307 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d443 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d441 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d479 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 && - rg_addr_0_EQ_rg_lrsc_pa_8___d117 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d491 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d519 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d517 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d520 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d524 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d532 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d530 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d534 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306 ; - assign NOT_ram_state_and_ctag_cset_b_read__9_BIT_52_0_ETC___d119 = - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - rg_addr_0_EQ_rg_lrsc_pa_8___d117 ; - assign NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 = - req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && - (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && - (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; - assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d105 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) ; - assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d444 || - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306) ; - assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d492 ; - assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d500 ; - assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d505 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d128 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - rg_addr_0_EQ_rg_lrsc_pa_8___d117 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d440 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d517 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d520 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d524 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d530 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - rg_addr_0_EQ_rg_lrsc_pa_8___d117 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d304 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d438 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d492 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d496 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d500 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d505 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign _theResult___snd_fst__h16843 = rg_st_amo_val << shift_bits__h20133 ; - assign _theResult___snd_fst__h20340 = - new_st_val__h17351 << shift_bits__h20133 ; - assign _theResult___snd_fst__h25769 = rg_st_amo_val << shift_bits__h27066 ; - assign _theResult___snd_fst__h27273 = st_val__h27010 << shift_bits__h27066 ; - assign access_exc_code__h2925 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd5 : - 4'd7) : - 4'd1 ; - assign b__h20935 = - ctr_wr_rsps_pending_crg$EN_port0__write ? - ctr_wr_rsps_pending_crg$port0__write_1 : - ctr_wr_rsps_pending_crg ; - assign cline_fabric_addr__h21034 = { rg_pa[63:6], 6'd0 } ; - assign dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d80 = - dmem_not_imem && !soc_map$m_is_mem_addr || rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d78 ; - assign ld_val4158_BITS_15_TO_0__q36 = ld_val__h24158[15:0] ; - assign ld_val4158_BITS_15_TO_8__q38 = ld_val__h24158[15:8] ; - assign ld_val4158_BITS_23_TO_16__q39 = ld_val__h24158[23:16] ; - assign ld_val4158_BITS_31_TO_0__q37 = ld_val__h24158[31:0] ; - assign ld_val4158_BITS_31_TO_16__q40 = ld_val__h24158[31:16] ; - assign ld_val4158_BITS_31_TO_24__q41 = ld_val__h24158[31:24] ; - assign ld_val4158_BITS_39_TO_32__q42 = ld_val__h24158[39:32] ; - assign ld_val4158_BITS_47_TO_32__q43 = ld_val__h24158[47:32] ; - assign ld_val4158_BITS_47_TO_40__q45 = ld_val__h24158[47:40] ; - assign ld_val4158_BITS_55_TO_48__q46 = ld_val__h24158[55:48] ; - assign ld_val4158_BITS_63_TO_32__q44 = ld_val__h24158[63:32] ; - assign ld_val4158_BITS_63_TO_48__q47 = ld_val__h24158[63:48] ; - assign ld_val4158_BITS_63_TO_56__q48 = ld_val__h24158[63:56] ; - assign ld_val4158_BITS_7_TO_0__q35 = ld_val__h24158[7:0] ; - assign lrsc_result__h13131 = - !rg_lrsc_valid || !rg_lrsc_pa_8_EQ_rg_addr_0___d59 ; - assign master_xactor_crg_rd_data_full_port1__read__51_ETC___d723 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; - assign master_xactor_rg_rd_data_BITS_10_TO_3__q1 = - master_xactor_rg_rd_data[10:3] ; - assign master_xactor_rg_rd_data_BITS_18_TO_11__q4 = - master_xactor_rg_rd_data[18:11] ; - assign master_xactor_rg_rd_data_BITS_18_TO_3__q2 = - master_xactor_rg_rd_data[18:3] ; - assign master_xactor_rg_rd_data_BITS_26_TO_19__q5 = - master_xactor_rg_rd_data[26:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_19__q6 = - master_xactor_rg_rd_data[34:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_27__q7 = - master_xactor_rg_rd_data[34:27] ; - assign master_xactor_rg_rd_data_BITS_34_TO_3__q3 = - master_xactor_rg_rd_data[34:3] ; - assign master_xactor_rg_rd_data_BITS_42_TO_35__q8 = - master_xactor_rg_rd_data[42:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_35__q9 = - master_xactor_rg_rd_data[50:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_43__q11 = - master_xactor_rg_rd_data[50:43] ; - assign master_xactor_rg_rd_data_BITS_58_TO_51__q12 = - master_xactor_rg_rd_data[58:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_35__q10 = - master_xactor_rg_rd_data[66:35] ; - assign master_xactor_rg_rd_data_BITS_66_TO_51__q13 = - master_xactor_rg_rd_data[66:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_59__q14 = - master_xactor_rg_rd_data[66:59] ; - assign new_st_val__h17351 = - (rg_f3 == 3'b010) ? - new_st_val__h17633 : - _theResult_____2__h17629 ; - assign new_st_val__h17633 = { 32'd0, _theResult_____2__h17629[31:0] } ; - assign new_st_val__h17724 = - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 + - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ; - assign new_st_val__h18704 = w1__h17621 ^ w2__h27284 ; - assign new_st_val__h18708 = w1__h17621 & w2__h27284 ; - assign new_st_val__h18712 = w1__h17621 | w2__h27284 ; - assign new_st_val__h18716 = - (w1__h17621 < w2__h27284) ? w1__h17621 : w2__h27284 ; - assign new_st_val__h18721 = - (w1__h17621 <= w2__h27284) ? w2__h27284 : w1__h17621 ; - assign new_st_val__h18727 = - ((IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 ^ - 64'h8000000000000000) < - (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^ - 64'h8000000000000000)) ? - w1__h17621 : - w2__h27284 ; - assign new_st_val__h18732 = - ((IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 ^ - 64'h8000000000000000) <= - (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^ - 64'h8000000000000000)) ? - w2__h27284 : - w1__h17621 ; - assign new_st_val__h27294 = { 32'd0, _theResult_____2__h27290[31:0] } ; - assign new_st_val__h27385 = - new_ld_val__h26998 + - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ; - assign new_st_val__h29245 = w1__h27282 ^ w2__h27284 ; - assign new_st_val__h29249 = w1__h27282 & w2__h27284 ; - assign new_st_val__h29253 = w1__h27282 | w2__h27284 ; - assign new_st_val__h29257 = - (w1__h27282 < w2__h27284) ? w1__h27282 : w2__h27284 ; - assign new_st_val__h29262 = - (w1__h27282 <= w2__h27284) ? w2__h27284 : w1__h27282 ; - assign new_st_val__h29268 = - ((new_ld_val__h26998 ^ 64'h8000000000000000) < - (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^ - 64'h8000000000000000)) ? - w1__h27282 : - w2__h27284 ; - assign new_st_val__h29273 = - ((new_ld_val__h26998 ^ 64'h8000000000000000) <= - (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^ - 64'h8000000000000000)) ? - w2__h27284 : - w1__h27282 ; - assign new_value462_BITS_31_TO_0__q30 = new_value__h5462[31:0] ; - assign ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 = - ram_state_and_ctag_cset$DOB[51:0] == rg_addr[63:12] ; - assign ram_state_and_ctag_cset_b_read__9_BIT_52_0_AND_ETC___d120 = - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - NOT_ram_state_and_ctag_cset_b_read__9_BIT_52_0_ETC___d119 ; - assign req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 = - req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || - req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || - req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; - assign result__h11871 = - { {56{word64281_BITS_15_TO_8__q18[7]}}, - word64281_BITS_15_TO_8__q18 } ; - assign result__h11899 = - { {56{word64281_BITS_23_TO_16__q19[7]}}, - word64281_BITS_23_TO_16__q19 } ; - assign result__h11927 = - { {56{word64281_BITS_31_TO_24__q21[7]}}, - word64281_BITS_31_TO_24__q21 } ; - assign result__h11955 = - { {56{word64281_BITS_39_TO_32__q22[7]}}, - word64281_BITS_39_TO_32__q22 } ; - assign result__h11983 = - { {56{word64281_BITS_47_TO_40__q25[7]}}, - word64281_BITS_47_TO_40__q25 } ; - assign result__h12011 = - { {56{word64281_BITS_55_TO_48__q26[7]}}, - word64281_BITS_55_TO_48__q26 } ; - assign result__h12039 = - { {56{word64281_BITS_63_TO_56__q28[7]}}, - word64281_BITS_63_TO_56__q28 } ; - assign result__h12084 = { 56'd0, word64__h5281[7:0] } ; - assign result__h12112 = { 56'd0, word64__h5281[15:8] } ; - assign result__h12140 = { 56'd0, word64__h5281[23:16] } ; - assign result__h12168 = { 56'd0, word64__h5281[31:24] } ; - assign result__h12196 = { 56'd0, word64__h5281[39:32] } ; - assign result__h12224 = { 56'd0, word64__h5281[47:40] } ; - assign result__h12252 = { 56'd0, word64__h5281[55:48] } ; - assign result__h12280 = { 56'd0, word64__h5281[63:56] } ; - assign result__h12325 = - { {48{word64281_BITS_15_TO_0__q16[15]}}, - word64281_BITS_15_TO_0__q16 } ; - assign result__h12353 = - { {48{word64281_BITS_31_TO_16__q20[15]}}, - word64281_BITS_31_TO_16__q20 } ; - assign result__h12381 = - { {48{word64281_BITS_47_TO_32__q23[15]}}, - word64281_BITS_47_TO_32__q23 } ; - assign result__h12409 = - { {48{word64281_BITS_63_TO_48__q27[15]}}, - word64281_BITS_63_TO_48__q27 } ; - assign result__h12450 = { 48'd0, word64__h5281[15:0] } ; - assign result__h12478 = { 48'd0, word64__h5281[31:16] } ; - assign result__h12506 = { 48'd0, word64__h5281[47:32] } ; - assign result__h12534 = { 48'd0, word64__h5281[63:48] } ; - assign result__h12575 = - { {32{word64281_BITS_31_TO_0__q17[31]}}, - word64281_BITS_31_TO_0__q17 } ; - assign result__h12603 = - { {32{word64281_BITS_63_TO_32__q24[31]}}, - word64281_BITS_63_TO_32__q24 } ; - assign result__h12642 = { 32'd0, word64__h5281[31:0] } ; - assign result__h12670 = { 32'd0, word64__h5281[63:32] } ; - assign result__h24218 = - { {56{master_xactor_rg_rd_data_BITS_10_TO_3__q1[7]}}, - master_xactor_rg_rd_data_BITS_10_TO_3__q1 } ; - assign result__h24248 = - { {56{master_xactor_rg_rd_data_BITS_18_TO_11__q4[7]}}, - master_xactor_rg_rd_data_BITS_18_TO_11__q4 } ; - assign result__h24275 = - { {56{master_xactor_rg_rd_data_BITS_26_TO_19__q5[7]}}, - master_xactor_rg_rd_data_BITS_26_TO_19__q5 } ; - assign result__h24302 = - { {56{master_xactor_rg_rd_data_BITS_34_TO_27__q7[7]}}, - master_xactor_rg_rd_data_BITS_34_TO_27__q7 } ; - assign result__h24329 = - { {56{master_xactor_rg_rd_data_BITS_42_TO_35__q8[7]}}, - master_xactor_rg_rd_data_BITS_42_TO_35__q8 } ; - assign result__h24356 = - { {56{master_xactor_rg_rd_data_BITS_50_TO_43__q11[7]}}, - master_xactor_rg_rd_data_BITS_50_TO_43__q11 } ; - assign result__h24383 = - { {56{master_xactor_rg_rd_data_BITS_58_TO_51__q12[7]}}, - master_xactor_rg_rd_data_BITS_58_TO_51__q12 } ; - assign result__h24410 = - { {56{master_xactor_rg_rd_data_BITS_66_TO_59__q14[7]}}, - master_xactor_rg_rd_data_BITS_66_TO_59__q14 } ; - assign result__h24454 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h24481 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h24508 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h24535 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h24562 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h24589 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h24616 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h24643 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h24687 = - { {48{master_xactor_rg_rd_data_BITS_18_TO_3__q2[15]}}, - master_xactor_rg_rd_data_BITS_18_TO_3__q2 } ; - assign result__h24714 = - { {48{master_xactor_rg_rd_data_BITS_34_TO_19__q6[15]}}, - master_xactor_rg_rd_data_BITS_34_TO_19__q6 } ; - assign result__h24741 = - { {48{master_xactor_rg_rd_data_BITS_50_TO_35__q9[15]}}, - master_xactor_rg_rd_data_BITS_50_TO_35__q9 } ; - assign result__h24768 = - { {48{master_xactor_rg_rd_data_BITS_66_TO_51__q13[15]}}, - master_xactor_rg_rd_data_BITS_66_TO_51__q13 } ; - assign result__h24808 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h24835 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h24862 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h24889 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h24929 = - { {32{master_xactor_rg_rd_data_BITS_34_TO_3__q3[31]}}, - master_xactor_rg_rd_data_BITS_34_TO_3__q3 } ; - assign result__h24956 = - { {32{master_xactor_rg_rd_data_BITS_66_TO_35__q10[31]}}, - master_xactor_rg_rd_data_BITS_66_TO_35__q10 } ; - assign result__h24994 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h25021 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; - assign result__h27473 = - { {56{ld_val4158_BITS_7_TO_0__q35[7]}}, - ld_val4158_BITS_7_TO_0__q35 } ; - assign result__h28381 = - { {56{ld_val4158_BITS_15_TO_8__q38[7]}}, - ld_val4158_BITS_15_TO_8__q38 } ; - assign result__h28409 = - { {56{ld_val4158_BITS_23_TO_16__q39[7]}}, - ld_val4158_BITS_23_TO_16__q39 } ; - assign result__h28437 = - { {56{ld_val4158_BITS_31_TO_24__q41[7]}}, - ld_val4158_BITS_31_TO_24__q41 } ; - assign result__h28465 = - { {56{ld_val4158_BITS_39_TO_32__q42[7]}}, - ld_val4158_BITS_39_TO_32__q42 } ; - assign result__h28493 = - { {56{ld_val4158_BITS_47_TO_40__q45[7]}}, - ld_val4158_BITS_47_TO_40__q45 } ; - assign result__h28521 = - { {56{ld_val4158_BITS_55_TO_48__q46[7]}}, - ld_val4158_BITS_55_TO_48__q46 } ; - assign result__h28549 = - { {56{ld_val4158_BITS_63_TO_56__q48[7]}}, - ld_val4158_BITS_63_TO_56__q48 } ; - assign result__h28594 = { 56'd0, ld_val__h24158[7:0] } ; - assign result__h28622 = { 56'd0, ld_val__h24158[15:8] } ; - assign result__h28650 = { 56'd0, ld_val__h24158[23:16] } ; - assign result__h28678 = { 56'd0, ld_val__h24158[31:24] } ; - assign result__h28706 = { 56'd0, ld_val__h24158[39:32] } ; - assign result__h28734 = { 56'd0, ld_val__h24158[47:40] } ; - assign result__h28762 = { 56'd0, ld_val__h24158[55:48] } ; - assign result__h28790 = { 56'd0, ld_val__h24158[63:56] } ; - assign result__h28835 = - { {48{ld_val4158_BITS_15_TO_0__q36[15]}}, - ld_val4158_BITS_15_TO_0__q36 } ; - assign result__h28863 = - { {48{ld_val4158_BITS_31_TO_16__q40[15]}}, - ld_val4158_BITS_31_TO_16__q40 } ; - assign result__h28891 = - { {48{ld_val4158_BITS_47_TO_32__q43[15]}}, - ld_val4158_BITS_47_TO_32__q43 } ; - assign result__h28919 = - { {48{ld_val4158_BITS_63_TO_48__q47[15]}}, - ld_val4158_BITS_63_TO_48__q47 } ; - assign result__h28960 = { 48'd0, ld_val__h24158[15:0] } ; - assign result__h28988 = { 48'd0, ld_val__h24158[31:16] } ; - assign result__h29016 = { 48'd0, ld_val__h24158[47:32] } ; - assign result__h29044 = { 48'd0, ld_val__h24158[63:48] } ; - assign result__h29085 = - { {32{ld_val4158_BITS_31_TO_0__q37[31]}}, - ld_val4158_BITS_31_TO_0__q37 } ; - assign result__h29113 = - { {32{ld_val4158_BITS_63_TO_32__q44[31]}}, - ld_val4158_BITS_63_TO_32__q44 } ; - assign result__h29152 = { 32'd0, ld_val__h24158[31:0] } ; - assign result__h29180 = { 32'd0, ld_val__h24158[63:32] } ; - assign result__h5515 = - { {56{word64281_BITS_7_TO_0__q15[7]}}, - word64281_BITS_7_TO_0__q15 } ; - assign rg_addr_0_EQ_rg_lrsc_pa_8___d117 = rg_addr == rg_lrsc_pa ; - assign rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d292 = - rg_amo_funct7[6:2] == 5'b00010 && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) && - rg_addr_0_EQ_rg_lrsc_pa_8___d117 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_lrsc_pa_8_EQ_rg_addr_0___d59 = rg_lrsc_pa == rg_addr ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d100 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset_b_read__9_BIT_52_0_AND_ETC___d120 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d129 ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136 = - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13131 ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d288 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d129 = - rg_op == 2'd1 && rg_addr_0_EQ_rg_lrsc_pa_8___d117 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d128 ; - assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d307 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d304 || - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306 ; - assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d441 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d438 || - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d440 ; - assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d444 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) ; - assign rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13131 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d68 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13131 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read ; - assign rg_st_amo_val_BITS_31_TO_0__q31 = rg_st_amo_val[31:0] ; - assign rg_state_EQ_13_90_AND_rg_op_4_EQ_0_5_OR_rg_op__ETC___d592 = - rg_state == 5'd13 && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - b__h20935 == 4'd0 ; - assign rg_state_EQ_3_1_AND_NOT_rg_op_4_EQ_0_5_2_AND_N_ETC___d90 = - rg_state == 5'd3 && - (rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - crg_sb_to_load_delay$port0__write_1 == 11'd0) ; - assign shift_bits__h20133 = { rg_addr[2:0], 3'b0 } ; - assign shift_bits__h27066 = { rg_pa[2:0], 3'b0 } ; - assign st_val__h27010 = - (rg_f3 == 3'b010) ? - new_st_val__h27294 : - _theResult_____2__h27290 ; - assign strobe64__h20266 = 8'b00000001 << rg_addr[2:0] ; - assign strobe64__h20268 = 8'b00000011 << rg_addr[2:0] ; - assign strobe64__h20270 = 8'b00001111 << rg_addr[2:0] ; - assign strobe64__h27199 = 8'b00000001 << rg_pa[2:0] ; - assign strobe64__h27201 = 8'b00000011 << rg_pa[2:0] ; - assign strobe64__h27203 = 8'b00001111 << rg_pa[2:0] ; - assign w17278_BITS_31_TO_0__q50 = w1__h27278[31:0] ; - assign w1___1__h17692 = { 32'd0, new_value__h5462[31:0] } ; - assign w1___1__h27353 = { 32'd0, w1__h27278[31:0] } ; - assign w2___1__h27354 = { 32'd0, rg_st_amo_val[31:0] } ; - assign w2__h27284 = (rg_f3 == 3'b010) ? w2___1__h27354 : rg_st_amo_val ; - assign word64281_BITS_15_TO_0__q16 = word64__h5281[15:0] ; - assign word64281_BITS_15_TO_8__q18 = word64__h5281[15:8] ; - assign word64281_BITS_23_TO_16__q19 = word64__h5281[23:16] ; - assign word64281_BITS_31_TO_0__q17 = word64__h5281[31:0] ; - assign word64281_BITS_31_TO_16__q20 = word64__h5281[31:16] ; - assign word64281_BITS_31_TO_24__q21 = word64__h5281[31:24] ; - assign word64281_BITS_39_TO_32__q22 = word64__h5281[39:32] ; - assign word64281_BITS_47_TO_32__q23 = word64__h5281[47:32] ; - assign word64281_BITS_47_TO_40__q25 = word64__h5281[47:40] ; - assign word64281_BITS_55_TO_48__q26 = word64__h5281[55:48] ; - assign word64281_BITS_63_TO_32__q24 = word64__h5281[63:32] ; - assign word64281_BITS_63_TO_48__q27 = word64__h5281[63:48] ; - assign word64281_BITS_63_TO_56__q28 = word64__h5281[63:56] ; - assign word64281_BITS_7_TO_0__q15 = word64__h5281[7:0] ; - assign word64__h5281 = ram_word64_set$DOB & y__h5551 ; - assign x__h13141 = { 63'd0, lrsc_result__h13131 } ; - assign y__h5551 = - {64{ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74}} ; - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h26583 = 3'b0; - 2'b01: value__h26583 = 3'b001; - 2'b10: value__h26583 = 3'b010; - 2'd3: value__h26583 = 3'b011; - endcase - end - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h29609 = 3'b0; - 2'b01: value__h29609 = 3'b001; - 2'b10: value__h29609 = 3'b010; - 2'b11: value__h29609 = 3'b011; - endcase - end - always@(rg_f3 or strobe64__h20266 or strobe64__h20268 or strobe64__h20270) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h20333 = strobe64__h20266; - 2'b01: mem_req_wr_data_wstrb__h20333 = strobe64__h20268; - 2'b10: mem_req_wr_data_wstrb__h20333 = strobe64__h20270; - 2'b11: mem_req_wr_data_wstrb__h20333 = 8'b11111111; - endcase - end - always@(rg_f3 or strobe64__h27199 or strobe64__h27201 or strobe64__h27203) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h27266 = strobe64__h27199; - 2'b01: mem_req_wr_data_wstrb__h27266 = strobe64__h27201; - 2'b10: mem_req_wr_data_wstrb__h27266 = strobe64__h27203; - 2'b11: mem_req_wr_data_wstrb__h27266 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h16843) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h16835 = _theResult___snd_fst__h16843; - 2'd3: mem_req_wr_data_wdata__h16835 = rg_st_amo_val; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h25769) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h25761 = _theResult___snd_fst__h25769; - 2'd3: mem_req_wr_data_wdata__h25761 = rg_st_amo_val; - endcase - end - always@(rg_addr or - result__h5515 or - result__h11871 or - result__h11899 or - result__h11927 or - result__h11955 or - result__h11983 or result__h12011 or result__h12039) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h5515; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h11871; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h11899; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h11927; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h11955; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h11983; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h12011; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h12039; - endcase - end - always@(rg_addr or - result__h12084 or - result__h12112 or - result__h12140 or - result__h12168 or - result__h12196 or - result__h12224 or result__h12252 or result__h12280) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12084; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12112; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12140; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12168; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12196; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12224; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12252; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12280; - endcase - end - always@(rg_addr or - result__h12450 or - result__h12478 or result__h12506 or result__h12534) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 = - result__h12450; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 = - result__h12478; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 = - result__h12506; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 = - result__h12534; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 = - 64'd0; - endcase - end - always@(rg_addr or - result__h12325 or - result__h12353 or result__h12381 or result__h12409) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 = - result__h12325; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 = - result__h12353; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 = - result__h12381; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 = - result__h12409; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 = - 64'd0; - endcase - end - always@(rg_addr or result__h12642 or result__h12670) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255 = - result__h12642; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255 = - result__h12670; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255 = - 64'd0; - endcase - end - always@(rg_addr or result__h12575 or result__h12603) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 = - result__h12575; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 = - result__h12603; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 or - CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255) - begin - case (rg_f3) - 3'b0: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204; - 3'b001: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234; - 3'b010: - new_value__h5462 = - CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29; - 3'b011: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257; - 3'b100: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221; - 3'b101: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243; - 3'b110: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255; - 3'd7: new_value__h5462 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 or - w1___1__h17692 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255) - begin - case (rg_f3) - 3'b0: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204; - 3'b001: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234; - 3'b010: w1__h17621 = w1___1__h17692; - 3'b011: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257; - 3'b100: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221; - 3'b101: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243; - 3'b110: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255; - 3'd7: w1__h17621 = 64'd0; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 = - { ram_word64_set$DOB[63:16], rg_st_amo_val[15:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 = - { rg_st_amo_val[15:0], ram_word64_set$DOB[47:0] }; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:8], rg_st_amo_val[7:0] }; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:16], - rg_st_amo_val[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:24], - rg_st_amo_val[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:40], - rg_st_amo_val[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:56], - rg_st_amo_val[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { rg_st_amo_val[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 or - new_value462_BITS_31_TO_0__q30 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204; - 3'b001: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234; - 3'b010: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - { {32{new_value462_BITS_31_TO_0__q30[31]}}, - new_value462_BITS_31_TO_0__q30 }; - 3'b011: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257; - 3'b100: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221; - 3'b101: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243; - 3'b110: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255; - 3'd7: IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h18732 or - new_st_val__h17724 or - w2__h27284 or - new_st_val__h18704 or - new_st_val__h18712 or - new_st_val__h18708 or - new_st_val__h18727 or new_st_val__h18716 or new_st_val__h18721) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h17629 = new_st_val__h17724; - 5'b00001: _theResult_____2__h17629 = w2__h27284; - 5'b00100: _theResult_____2__h17629 = new_st_val__h18704; - 5'b01000: _theResult_____2__h17629 = new_st_val__h18712; - 5'b01100: _theResult_____2__h17629 = new_st_val__h18708; - 5'b10000: _theResult_____2__h17629 = new_st_val__h18727; - 5'b11000: _theResult_____2__h17629 = new_st_val__h18716; - 5'b11100: _theResult_____2__h17629 = new_st_val__h18721; - default: _theResult_____2__h17629 = new_st_val__h18732; - endcase - end - always@(rg_f3 or new_st_val__h17351 or _theResult___snd_fst__h20340) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h20332 = _theResult___snd_fst__h20340; - 2'd3: mem_req_wr_data_wdata__h20332 = new_st_val__h17351; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17351) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 = - { ram_word64_set$DOB[63:16], new_st_val__h17351[15:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 = - { ram_word64_set$DOB[63:32], - new_st_val__h17351[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 = - { ram_word64_set$DOB[63:48], - new_st_val__h17351[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 = - { new_st_val__h17351[15:0], ram_word64_set$DOB[47:0] }; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17351) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:8], new_st_val__h17351[7:0] }; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:16], - new_st_val__h17351[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:24], - new_st_val__h17351[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:32], - new_st_val__h17351[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:40], - new_st_val__h17351[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:48], - new_st_val__h17351[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:56], - new_st_val__h17351[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { new_st_val__h17351[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - { ram_word64_set$DOB[63:32], rg_st_amo_val[31:0] }; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - { rg_st_amo_val[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 or - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 or - rg_st_amo_val) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342; - 3'b001: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351; - 3'b010: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 = - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32; - 3'b011: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 = - rg_st_amo_val; - default: IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or - result__h24808 or - result__h24835 or result__h24862 or result__h24889) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 = - result__h24808; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 = - result__h24835; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 = - result__h24862; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 = - result__h24889; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 = - 64'd0; - endcase - end - always@(rg_addr or - result__h24687 or - result__h24714 or result__h24741 or result__h24768) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 = - result__h24687; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 = - result__h24714; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 = - result__h24741; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 = - result__h24768; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 = - 64'd0; - endcase - end - always@(rg_addr or - result__h24454 or - result__h24481 or - result__h24508 or - result__h24535 or - result__h24562 or - result__h24589 or result__h24616 or result__h24643) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24454; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24481; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24508; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24535; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24562; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24589; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24616; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24643; - endcase - end - always@(rg_addr or - result__h24218 or - result__h24248 or - result__h24275 or - result__h24302 or - result__h24329 or - result__h24356 or result__h24383 or result__h24410) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24218; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24248; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24275; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24302; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24329; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24356; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24383; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24410; - endcase - end - always@(rg_addr or result__h24929 or result__h24956) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 = - result__h24929; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 = - result__h24956; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 = - 64'd0; - endcase - end - always@(rg_addr or result__h24994 or result__h25021) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34 = - result__h24994; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34 = - result__h25021; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 or - rg_addr or - master_xactor_rg_rd_data or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34) - begin - case (rg_f3) - 3'b0: - ld_val__h24158 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630; - 3'b001: - ld_val__h24158 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658; - 3'b010: - ld_val__h24158 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33; - 3'b011: - ld_val__h24158 = - (rg_addr[2:0] == 3'h0) ? master_xactor_rg_rd_data[66:3] : 64'd0; - 3'b100: - ld_val__h24158 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646; - 3'b101: - ld_val__h24158 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666; - 3'b110: - ld_val__h24158 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34; - 3'd7: ld_val__h24158 = 64'd0; - endcase - end - always@(rg_addr or - result__h28960 or - result__h28988 or result__h29016 or result__h29044) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 = - result__h28960; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 = - result__h28988; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 = - result__h29016; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 = - result__h29044; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 = - 64'd0; - endcase - end - always@(rg_addr or result__h29152 or result__h29180) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799 = - result__h29152; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799 = - result__h29180; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28835 or - result__h28863 or result__h28891 or result__h28919) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 = - result__h28835; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 = - result__h28863; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 = - result__h28891; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 = - result__h28919; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28594 or - result__h28622 or - result__h28650 or - result__h28678 or - result__h28706 or - result__h28734 or result__h28762 or result__h28790) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28594; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28622; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28650; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28678; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28706; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28734; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28762; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28790; - endcase - end - always@(rg_addr or - result__h27473 or - result__h28381 or - result__h28409 or - result__h28437 or - result__h28465 or - result__h28493 or result__h28521 or result__h28549) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h27473; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28381; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28409; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28437; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28465; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28493; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28521; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28549; - endcase - end - always@(rg_addr or result__h29085 or result__h29113) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 = - result__h29085; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 = - result__h29113; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 or - CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799) - begin - case (rg_f3) - 3'b0: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753; - 3'b001: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781; - 3'b010: - w1__h27278 = - CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49; - 3'b011: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800; - 3'b100: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769; - 3'b101: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789; - 3'b110: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799; - 3'd7: w1__h27278 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 or - w1___1__h27353 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799) - begin - case (rg_f3) - 3'b0: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753; - 3'b001: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781; - 3'b010: w1__h27282 = w1___1__h27353; - 3'b011: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800; - 3'b100: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769; - 3'b101: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789; - 3'b110: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799; - 3'd7: w1__h27282 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 or - w17278_BITS_31_TO_0__q50 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799) - begin - case (rg_f3) - 3'b0: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753; - 3'b001: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781; - 3'b010: - new_ld_val__h26998 = - { {32{w17278_BITS_31_TO_0__q50[31]}}, - w17278_BITS_31_TO_0__q50 }; - 3'b011: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800; - 3'b100: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769; - 3'b101: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789; - 3'b110: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799; - 3'd7: new_ld_val__h26998 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h29273 or - new_st_val__h27385 or - w2__h27284 or - new_st_val__h29245 or - new_st_val__h29253 or - new_st_val__h29249 or - new_st_val__h29268 or new_st_val__h29257 or new_st_val__h29262) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h27290 = new_st_val__h27385; - 5'b00001: _theResult_____2__h27290 = w2__h27284; - 5'b00100: _theResult_____2__h27290 = new_st_val__h29245; - 5'b01000: _theResult_____2__h27290 = new_st_val__h29253; - 5'b01100: _theResult_____2__h27290 = new_st_val__h29249; - 5'b10000: _theResult_____2__h27290 = new_st_val__h29268; - 5'b11000: _theResult_____2__h27290 = new_st_val__h29257; - 5'b11100: _theResult_____2__h27290 = new_st_val__h29262; - default: _theResult_____2__h27290 = new_st_val__h29273; - endcase - end - always@(rg_f3 or st_val__h27010 or _theResult___snd_fst__h27273) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h27265 = _theResult___snd_fst__h27273; - 2'd3: mem_req_wr_data_wdata__h27265 = st_val__h27010; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17351) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - { ram_word64_set$DOB[63:32], new_st_val__h17351[31:0] }; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - { new_st_val__h17351[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 or - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 or - new_st_val__h17351) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416; - 3'b001: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425; - 3'b010: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 = - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51; - 3'b011: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 = - new_st_val__h17351; - default: IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271) - begin - case (rg_f3) - 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: - new_value__h15489 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271; - 3'd7: new_value__h15489 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0; - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_sb_to_load_delay$EN) - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY - crg_sb_to_load_delay$D_IN; - if (ctr_wr_rsps_pending_crg$EN) - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY - ctr_wr_rsps_pending_crg$D_IN; - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_cset_in_cache$EN) - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN; - if (rg_lower_word32_full$EN) - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY - rg_lower_word32_full$D_IN; - if (rg_lrsc_valid$EN) - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; - if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN; - if (rg_amo_funct7$EN) - rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN; - if (rg_error_during_refill$EN) - rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY - rg_error_during_refill$D_IN; - if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN; - if (rg_lower_word32$EN) - rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN; - if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN; - if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN; - if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN; - if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN; - if (rg_st_amo_val$EN) - rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN; - if (rg_word64_set_in_cache$EN) - rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY - rg_word64_set_in_cache$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_sb_to_load_delay = 11'h2AA; - ctr_wr_rsps_pending_crg = 4'hA; - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; - rg_addr = 64'hAAAAAAAAAAAAAAAA; - rg_amo_funct7 = 7'h2A; - rg_cset_in_cache = 6'h2A; - rg_error_during_refill = 1'h0; - rg_exc_code = 4'hA; - rg_f3 = 3'h2; - rg_ld_val = 64'hAAAAAAAAAAAAAAAA; - rg_lower_word32 = 32'hAAAAAAAA; - rg_lower_word32_full = 1'h0; - rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA; - rg_lrsc_valid = 1'h0; - rg_op = 2'h2; - rg_pa = 64'hAAAAAAAAAAAAAAAA; - rg_pte_pa = 64'hAAAAAAAAAAAAAAAA; - rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; - rg_state = 5'h0A; - rg_word64_set_in_cache = 9'h0AA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - begin - v__h3732 = $stime; - #0; - end - v__h3726 = v__h3732 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h3726, - "D_MMU_Cache", - $signed(32'd64), - $signed(32'd1)); - else - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h3726, - "I_MMU_Cache", - $signed(32'd64), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - f_reset_reqs$D_OUT) - begin - v__h3833 = $stime; - #0; - end - v__h3827 = v__h3833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: Flushed", v__h3827, "D_MMU_Cache"); - else - $display("%0d: %s.rl_reset: Flushed", v__h3827, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_rereq && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - rg_addr[11:6], - rg_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25363 = $stime; - #0; - end - v__h25357 = v__h25363 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25357, - "D_MMU_Cache", - rg_addr, - rg_ld_val); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25357, - "I_MMU_Cache", - rg_addr, - rg_ld_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26261 = $stime; - #0; - end - v__h26255 = v__h26261 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26255, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26255, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" FAIL due to I/O address."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h3369 = $stime; - #0; - end - v__h3363 = v__h3369 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_start_reset", v__h3363, "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_reset", v__h3363, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h4286 = $stime; - #0; - end - v__h4280 = v__h4286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h4280, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h4280, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", - rg_addr[63:12], - rg_addr[11:6], - rg_addr[5:3], - rg_addr[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" CSet 0x%0x: (state, tag):", rg_addr[11:6]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" ("); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - ram_state_and_ctag_cset$DOB[52]) - $write("CTAG_CLEAN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !ram_state_and_ctag_cset$DOB[52]) - $write("CTAG_EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - ram_state_and_ctag_cset$DOB[52]) - $write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !ram_state_and_ctag_cset$DOB[52]) - $write(", --"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(")"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" TLB result: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'hA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && dmem_not_imem && - !soc_map$m_is_mem_addr && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => IO_REQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275) - begin - v__h12754 = $stime; - #0; - end - v__h12748 = v__h12754 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h12748, - "D_MMU_Cache", - rg_addr, - word64__h5281, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h12748, - "I_MMU_Cache", - rg_addr, - word64__h5281, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO LR: reserving PA 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275) - $display(" Read-hit: addr 0x%0h word64 0x%0h", - rg_addr, - word64__h5281); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d288) - $display(" Read Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d292) - $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", - rg_lrsc_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d479) - $display(" ST: cancelling LR/SC reservation for PA", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - rg_lrsc_valid && - !rg_lrsc_pa_8_EQ_rg_addr_0___d59 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", - rg_lrsc_pa, - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !rg_lrsc_valid && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO SC: fail due to invalid LR/SC reservation"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d491) - $display(" AMO SC result = %0d", lrsc_result__h13131); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494) - $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494) - $write(" 0x%0x", - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d496) - $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507) - begin - v__h17070 = $stime; - #0; - end - v__h17064 = v__h17070 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507) - $display("%0d: ERROR: CreditCounter: overflow", v__h17064); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", value__h29609); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", mem_req_wr_data_wdata__h16835); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", mem_req_wr_data_wstrb__h20333); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $display(" => rl_write_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513) - begin - v__h16398 = $stime; - #0; - end - v__h16392 = v__h16398 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h16392, - "D_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h16392, - "I_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513) - $display(" AMO SC: Fail response for addr 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d519) - $display(" AMO Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", - rg_addr, - rg_amo_funct7, - rg_f3, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $display(" PA 0x%0h ", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $display(" Cache word64 0x%0h, load-result 0x%0h", - word64__h5281, - word64__h5281); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $display(" 0x%0h op 0x%0h -> 0x%0h", - word64__h5281, - word64__h5281, - new_st_val__h17351); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(" 0x%0x", - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526) - begin - v__h20536 = $stime; - #0; - end - v__h20530 = v__h20536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526) - $display("%0d: ERROR: CreditCounter: overflow", v__h20530); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", value__h29609); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", mem_req_wr_data_wdata__h20332); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", mem_req_wr_data_wstrb__h20333); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d532) - $display(" AMO_op: cancelling LR/SC reservation for PA", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - begin - v__h21830 = $stime; - #0; - end - v__h21824 = v__h21830 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h21824, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h21824, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h22071 = $stime; - #0; - end - v__h22065 = v__h22071 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h22065, - "D_MMU_Cache", - access_exc_code__h2925); - else - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h22065, - "I_MMU_Cache", - access_exc_code__h2925); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 && - (master_xactor_rg_rd_data[2:1] != 2'b0 || rg_error_during_refill) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => MODULE_EXCEPTION_RSP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !rg_error_during_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => CACHE_REREQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", - rg_word64_set_in_cache, - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(" 0x%0x", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h24049 = $stime; - #0; - end - v__h24043 = v__h24049 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h24043, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h24043, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25151 = $stime; - #0; - end - v__h25145 = v__h25151 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25145, - "D_MMU_Cache", - rg_addr, - ld_val__h24158); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25145, - "I_MMU_Cache", - rg_addr, - ld_val__h24158); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25258 = $stime; - #0; - end - v__h25252 = v__h25258 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h25252, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h25252, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25443 = $stime; - #0; - end - v__h25437 = v__h25443 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h25437, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h25437, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h25965 = $stime; - #0; - end - v__h25959 = v__h25965 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h25959); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h29609); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wdata__h25761); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wstrb__h27266); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26379 = $stime; - #0; - end - v__h26373 = v__h26379 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h26373, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h26373, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h26583); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26697 = $stime; - #0; - end - v__h26691 = v__h26697 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h26691, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h26691, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26872 = $stime; - #0; - end - v__h26866 = v__h26872 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26866, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26866, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h29485 = $stime; - #0; - end - v__h29479 = v__h29485 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h29479); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h29609); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wdata__h27265); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wstrb__h27266); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h29737 = $stime; - #0; - end - v__h29731 = v__h29737 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29731, - "D_MMU_Cache", - rg_addr, - new_ld_val__h26998); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29731, - "I_MMU_Cache", - rg_addr, - new_ld_val__h26998); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26968 = $stime; - #0; - end - v__h26962 = v__h26968 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h26962, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h26962, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h20981 = $stime; - #0; - end - v__h20975 = v__h20981 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_start_cache_refill: ", - v__h20975, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_cache_refill: ", - v__h20975, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", cline_fabric_addr__h21034); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd7); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" Victim way %0d; => CACHE_REFILL", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h23675 = $stime; - #0; - end - v__h23669 = v__h23675 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h23669, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h23669, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h26583); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h30707 = $stime; - #0; - end - v__h30701 = v__h30707 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $write("%0d: %s.req: op:", v__h30701, "D_MMU_Cache"); - else - $write("%0d: %s.req: op:", v__h30701, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && req_op == 2'd0) - $write("CACHE_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && req_op == 2'd1) - $write("CACHE_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_op != 2'd0 && - req_op != 2'd1) - $write("CACHE_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", - req_f3, - req_addr, - req_st_value); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b0) - $write("U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b01) - $write("S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b11) - $write("M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv != 2'b0 && - req_priv != 2'b01 && - req_priv != 2'b11) - $write("RESERVED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" amo_funct7 = 0x%0h", req_amo_funct7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && - req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - req_addr[11:6], - req_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h30357 = $stime; - #0; - end - v__h30351 = v__h30357 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h30351, - "D_MMU_Cache", - $unsigned(b__h20935)); - else - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h30351, - "I_MMU_Cache", - $unsigned(b__h20935)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - begin - v__h30318 = $stime; - #0; - end - v__h30312 = v__h30318 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - if (dmem_not_imem) - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h30312, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h30312, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("\n"); - end - // synopsys translate_on -endmodule // mkMMU_Cache - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v deleted file mode 100644 index f673c615..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Controller.v +++ /dev/null @@ -1,2169 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// to_raw_mem_response_put I 256 -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_to_raw_mem_response_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Controller(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [63 : 0] slave_rdata; - wire [7 : 0] status; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // inlined wires - reg [353 : 0] f_raw_mem_reqs_rv$port1__write_1; - wire [353 : 0] f_raw_mem_reqs_rv$port1__read, - f_raw_mem_reqs_rv$port2__read, - f_raw_mem_reqs_rv$port3__read; - wire [256 : 0] f_raw_mem_rsps_rv$port1__read, - f_raw_mem_rsps_rv$port1__write_1, - f_raw_mem_rsps_rv$port2__read, - f_raw_mem_rsps_rv$port3__read; - wire [170 : 0] f_reqs_rv$port1__read, - f_reqs_rv$port1__write_1, - f_reqs_rv$port2__read; - wire f_raw_mem_reqs_rv$EN_port1__write, - f_reqs_rv$EN_port0__write, - f_reqs_rv$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register f_raw_mem_reqs_rv - reg [353 : 0] f_raw_mem_reqs_rv; - wire [353 : 0] f_raw_mem_reqs_rv$D_IN; - wire f_raw_mem_reqs_rv$EN; - - // register f_raw_mem_rsps_rv - reg [256 : 0] f_raw_mem_rsps_rv; - wire [256 : 0] f_raw_mem_rsps_rv$D_IN; - wire f_raw_mem_rsps_rv$EN; - - // register f_reqs_rv - reg [170 : 0] f_reqs_rv; - wire [170 : 0] f_reqs_rv$D_IN; - wire f_reqs_rv$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_cached_clean - reg rg_cached_clean; - wire rg_cached_clean$D_IN, rg_cached_clean$EN; - - // register rg_cached_raw_mem_addr - reg [63 : 0] rg_cached_raw_mem_addr; - wire [63 : 0] rg_cached_raw_mem_addr$D_IN; - wire rg_cached_raw_mem_addr$EN; - - // register rg_cached_raw_mem_word - reg [255 : 0] rg_cached_raw_mem_word; - wire [255 : 0] rg_cached_raw_mem_word$D_IN; - wire rg_cached_raw_mem_word$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_status - reg [7 : 0] rg_status; - wire [7 : 0] rg_status$D_IN; - wire rg_status$EN; - - // register rg_tohost_addr - reg [63 : 0] rg_tohost_addr; - wire [63 : 0] rg_tohost_addr$D_IN; - wire rg_tohost_addr$EN; - - // register rg_watch_tohost - reg rg_watch_tohost; - wire rg_watch_tohost$D_IN, rg_watch_tohost$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_external_reset, - CAN_FIRE_RL_rl_invalid_rd_address, - CAN_FIRE_RL_rl_invalid_wr_address, - CAN_FIRE_RL_rl_merge_rd_req, - CAN_FIRE_RL_rl_merge_wr_req, - CAN_FIRE_RL_rl_miss_clean_req, - CAN_FIRE_RL_rl_power_on_reset, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reload, - CAN_FIRE_RL_rl_reset_reload_cache, - CAN_FIRE_RL_rl_writeback_dirty, - CAN_FIRE_RL_rl_writeback_dirty_idle, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_external_reset, - WILL_FIRE_RL_rl_invalid_rd_address, - WILL_FIRE_RL_rl_invalid_wr_address, - WILL_FIRE_RL_rl_merge_rd_req, - WILL_FIRE_RL_rl_merge_wr_req, - WILL_FIRE_RL_rl_miss_clean_req, - WILL_FIRE_RL_rl_power_on_reset, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reload, - WILL_FIRE_RL_rl_reset_reload_cache, - WILL_FIRE_RL_rl_writeback_dirty, - WILL_FIRE_RL_rl_writeback_dirty_idle, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire [353 : 0] MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1, - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - wire [255 : 0] MUX_rg_cached_raw_mem_word$write_1__VAL_1; - wire [170 : 0] MUX_f_reqs_rv$port1__write_1__VAL_1, - MUX_f_reqs_rv$port1__write_1__VAL_2; - wire [70 : 0] MUX_slave_xactor_f_rd_data$enq_1__VAL_1, - MUX_slave_xactor_f_rd_data$enq_1__VAL_2; - wire [5 : 0] MUX_slave_xactor_f_wr_resp$enq_1__VAL_1, - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2; - wire MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2538; - reg [31 : 0] v__h3481; - reg [31 : 0] v__h3974; - reg [31 : 0] v__h4443; - reg [31 : 0] v__h4706; - reg [31 : 0] v__h5425; - reg [31 : 0] v__h7622; - reg [31 : 0] v__h7823; - reg [31 : 0] v__h8335; - reg [31 : 0] v__h9119; - reg [31 : 0] v__h9714; - reg [31 : 0] v__h2853; - reg [31 : 0] v__h3193; - reg [31 : 0] v__h1743; - reg [31 : 0] v__h2088; - reg [31 : 0] v__h1737; - reg [31 : 0] v__h2082; - reg [31 : 0] v__h2532; - reg [31 : 0] v__h2847; - reg [31 : 0] v__h3187; - reg [31 : 0] v__h3475; - reg [31 : 0] v__h3968; - reg [31 : 0] v__h4437; - reg [31 : 0] v__h4700; - reg [31 : 0] v__h5419; - reg [31 : 0] v__h7616; - reg [31 : 0] v__h7817; - reg [31 : 0] v__h8329; - reg [31 : 0] v__h9113; - reg [31 : 0] v__h9708; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rdata__h5068, word64_old__h5862; - wire [63 : 0] exit_value__h7860, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1, - mask__h5867, - req_raw_mem_addr__h3314, - updated_word64__h5868, - x__h6241, - y__h6242, - y__h6243; - wire [7 : 0] SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191; - wire [4 : 0] n__h5067; - wire NOT_cfg_verbosity_read_ULE_1___d5, - NOT_cfg_verbosity_read_ULE_2_2___d33, - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279, - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128, - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123, - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126, - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135, - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284, - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131, - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = rg_state == 2'd3 ; - assign CAN_FIRE_set_addr_map = rg_state == 2'd3 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = f_raw_mem_reqs_rv[352:0] ; - assign RDY_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign CAN_FIRE_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = !f_raw_mem_rsps_rv$port1__read[256] ; - assign CAN_FIRE_to_raw_mem_response_put = - !f_raw_mem_rsps_rv$port1__read[256] ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // value method status - assign status = rg_status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset_reload_cache - assign CAN_FIRE_RL_rl_reset_reload_cache = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_reload_cache = - CAN_FIRE_RL_rl_reset_reload_cache ; - - // rule RL_rl_writeback_dirty_idle - assign CAN_FIRE_RL_rl_writeback_dirty_idle = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd3 && - !f_reqs_rv[170] && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty_idle = - CAN_FIRE_RL_rl_writeback_dirty_idle ; - - // rule RL_rl_writeback_dirty - assign CAN_FIRE_RL_rl_writeback_dirty = - !f_raw_mem_reqs_rv$port1__read[353] && f_reqs_rv[170] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty = CAN_FIRE_RL_rl_writeback_dirty ; - - // rule RL_rl_miss_clean_req - assign CAN_FIRE_RL_rl_miss_clean_req = - f_reqs_rv[170] && !f_raw_mem_reqs_rv$port1__read[353] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - rg_cached_clean ; - assign WILL_FIRE_RL_rl_miss_clean_req = - CAN_FIRE_RL_rl_miss_clean_req && - !WILL_FIRE_RL_rl_external_reset && - !EN_set_addr_map ; - - // rule RL_rl_reload - assign CAN_FIRE_RL_rl_reload = f_raw_mem_rsps_rv[256] && rg_state == 2'd2 ; - assign WILL_FIRE_RL_rl_reload = CAN_FIRE_RL_rl_reload ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_invalid_rd_address - assign CAN_FIRE_RL_rl_invalid_rd_address = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_rd_address = - CAN_FIRE_RL_rl_invalid_rd_address ; - - // rule RL_rl_invalid_wr_address - assign CAN_FIRE_RL_rl_invalid_wr_address = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_wr_address = - CAN_FIRE_RL_rl_invalid_wr_address ; - - // rule RL_rl_merge_rd_req - assign CAN_FIRE_RL_rl_merge_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && !f_reqs_rv$port1__read[170] ; - assign WILL_FIRE_RL_rl_merge_rd_req = CAN_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_merge_wr_req - assign CAN_FIRE_RL_rl_merge_wr_req = - !f_reqs_rv$port1__read[170] && slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N ; - assign WILL_FIRE_RL_rl_merge_wr_req = - CAN_FIRE_RL_rl_merge_wr_req && !WILL_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_power_on_reset - assign CAN_FIRE_RL_rl_power_on_reset = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_power_on_reset = CAN_FIRE_RL_rl_power_on_reset ; - - // rule RL_rl_external_reset - assign CAN_FIRE_RL_rl_external_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && rg_state == 2'd3 ; - assign WILL_FIRE_RL_rl_external_reset = CAN_FIRE_RL_rl_external_reset ; - - // inputs to muxes for submodule ports - assign MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - assign MUX_rg_state$write_1__SEL_1 = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - assign MUX_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 = - { 34'h3FFFFFFFF, - rg_cached_raw_mem_addr, - rg_cached_raw_mem_word } ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3 = - { 34'h2FFFFFFFF, - req_raw_mem_addr__h3314, - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_1 = - { 2'd2, slave_xactor_f_rd_addr$D_OUT, 72'hAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_2 = - { 2'd3, - slave_xactor_f_wr_addr$D_OUT, - slave_xactor_f_wr_data$D_OUT[8:1], - slave_xactor_f_wr_data$D_OUT[72:9] } ; - assign MUX_rg_cached_raw_mem_word$write_1__VAL_1 = - { (f_reqs_rv[105:104] == 2'd3) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[255:192], - (f_reqs_rv[105:104] == 2'd2) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[191:128], - (f_reqs_rv[105:104] == 2'd1) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[127:64], - (f_reqs_rv[105:104] == 2'd0) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[63:0] } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_1 = - { f_reqs_rv[168:165], rdata__h5068, 3'd1 } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_2 = - { f_reqs_rv[168:101], 3'd5 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 = - { f_reqs_rv[168:165], 2'd0 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 = - { f_reqs_rv[168:165], 2'd2 } ; - - // inlined wires - assign f_reqs_rv$EN_port0__write = - WILL_FIRE_RL_rl_invalid_wr_address || - WILL_FIRE_RL_rl_invalid_rd_address || - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs_rv$port1__read = - f_reqs_rv$EN_port0__write ? - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_reqs_rv ; - assign f_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_merge_rd_req || WILL_FIRE_RL_rl_merge_wr_req ; - assign f_reqs_rv$port1__write_1 = - WILL_FIRE_RL_rl_merge_rd_req ? - MUX_f_reqs_rv$port1__write_1__VAL_1 : - MUX_f_reqs_rv$port1__write_1__VAL_2 ; - assign f_reqs_rv$port2__read = - f_reqs_rv$EN_port1__write ? - f_reqs_rv$port1__write_1 : - f_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port1__read = - EN_to_raw_mem_request_get ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv ; - assign f_raw_mem_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_miss_clean_req ; - always@(MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 or - WILL_FIRE_RL_rl_reset_reload_cache or - WILL_FIRE_RL_rl_miss_clean_req or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1; - WILL_FIRE_RL_rl_reset_reload_cache: - f_raw_mem_reqs_rv$port1__write_1 = - 354'h2FFFFFFFF0000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_miss_clean_req: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - default: f_raw_mem_reqs_rv$port1__write_1 = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign f_raw_mem_reqs_rv$port2__read = - f_raw_mem_reqs_rv$EN_port1__write ? - f_raw_mem_reqs_rv$port1__write_1 : - f_raw_mem_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv$port2__read ; - assign f_raw_mem_rsps_rv$port1__read = - CAN_FIRE_RL_rl_reload ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv ; - assign f_raw_mem_rsps_rv$port1__write_1 = - { 1'd1, to_raw_mem_response_put } ; - assign f_raw_mem_rsps_rv$port2__read = - EN_to_raw_mem_response_put ? - f_raw_mem_rsps_rv$port1__write_1 : - f_raw_mem_rsps_rv$port1__read ; - assign f_raw_mem_rsps_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv$port2__read ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register f_raw_mem_reqs_rv - assign f_raw_mem_reqs_rv$D_IN = f_raw_mem_reqs_rv$port3__read ; - assign f_raw_mem_reqs_rv$EN = 1'b1 ; - - // register f_raw_mem_rsps_rv - assign f_raw_mem_rsps_rv$D_IN = f_raw_mem_rsps_rv$port3__read ; - assign f_raw_mem_rsps_rv$EN = 1'b1 ; - - // register f_reqs_rv - assign f_reqs_rv$D_IN = f_reqs_rv$port2__read ; - assign f_reqs_rv$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_cached_clean - assign rg_cached_clean$D_IN = !WILL_FIRE_RL_rl_process_wr_req ; - assign rg_cached_clean$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload || - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - - // register rg_cached_raw_mem_addr - assign rg_cached_raw_mem_addr$D_IN = - WILL_FIRE_RL_rl_miss_clean_req ? - req_raw_mem_addr__h3314 : - 64'd0 ; - assign rg_cached_raw_mem_addr$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_cached_raw_mem_word - assign rg_cached_raw_mem_word$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_rg_cached_raw_mem_word$write_1__VAL_1 : - f_raw_mem_rsps_rv[255:0] ; - assign rg_cached_raw_mem_word$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload ; - - // register rg_state - always@(MUX_rg_state$write_1__SEL_1 or - MUX_rg_state$write_1__SEL_2 or WILL_FIRE_RL_rl_reload) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_state$write_1__SEL_1: rg_state$D_IN = 2'd1; - MUX_rg_state$write_1__SEL_2: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reload: rg_state$D_IN = 2'd3; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset || - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_reload ; - - // register rg_status - assign rg_status$D_IN = - (WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset) ? - 8'd0 : - 8'd1 ; - assign rg_status$EN = - WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 || - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - - // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_watch_tohost ; - - // register rg_watch_tohost - assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ; - assign rg_watch_tohost$EN = EN_set_watch_tohost ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_merge_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_slave_xactor_f_rd_data$enq_1__VAL_1 : - MUX_slave_xactor_f_rd_data$enq_1__VAL_2 ; - assign slave_xactor_f_rd_data$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_invalid_rd_address ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 : - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 ; - assign slave_xactor_f_wr_resp$ENQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_invalid_wr_address ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_1 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d5 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read_ULE_2_2___d33 = cfg_verbosity > 4'd2 ; - assign NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 = - f_reqs_rv[92:90] != 3'b0 && - (f_reqs_rv[92:90] != 3'b001 || f_reqs_rv[101]) && - (f_reqs_rv[92:90] != 3'b010 || f_reqs_rv[102:101] != 2'h0) && - (f_reqs_rv[92:90] != 3'b011 || f_reqs_rv[103:101] != 3'h0) && - (f_reqs_rv[92:90] != 3'b100 || f_reqs_rv[104:101] != 4'h0) && - (f_reqs_rv[92:90] != 3'b101 || f_reqs_rv[105:101] != 5'h0) && - (f_reqs_rv[92:90] != 3'b110 || f_reqs_rv[106:101] != 6'h0) && - (f_reqs_rv[92:90] != 3'b111 || f_reqs_rv[107:101] != 7'h0) ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 = {8{f_reqs_rv[64]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212 = {8{f_reqs_rv[65]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208 = {8{f_reqs_rv[66]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205 = {8{f_reqs_rv[67]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201 = {8{f_reqs_rv[68]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198 = {8{f_reqs_rv[69]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194 = {8{f_reqs_rv[70]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191 = {8{f_reqs_rv[71]}} ; - assign exit_value__h7860 = { 1'd0, f_reqs_rv[63:1] } ; - assign f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1 = - f_reqs_rv[164:101] - rg_addr_base ; - assign f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 = - f_reqs_rv[164:101] < rg_addr_lim ; - assign f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 = - f_reqs_rv[92:90] == 3'b0 || - f_reqs_rv[92:90] == 3'b001 && !f_reqs_rv[101] || - f_reqs_rv[92:90] == 3'b010 && f_reqs_rv[102:101] == 2'h0 || - f_reqs_rv[92:90] == 3'b011 && f_reqs_rv[103:101] == 3'h0 || - f_reqs_rv[92:90] == 3'b100 && f_reqs_rv[104:101] == 4'h0 || - f_reqs_rv[92:90] == 3'b101 && f_reqs_rv[105:101] == 5'h0 || - f_reqs_rv[92:90] == 3'b110 && f_reqs_rv[106:101] == 6'h0 || - f_reqs_rv[92:90] == 3'b111 && f_reqs_rv[107:101] == 7'h0 ; - assign mask__h5867 = - { SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - assign n__h5067 = { 3'd0, f_reqs_rv[105:104] } ; - assign req_raw_mem_addr__h3314 = - { 5'd0, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1[63:5] } ; - assign rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 = - rg_addr_base <= f_reqs_rv[164:101] ; - assign rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 = - rg_cached_raw_mem_addr == req_raw_mem_addr__h3314 ; - assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 = - rg_state == 2'd3 && - (NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 || - !rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 || - !f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128) ; - assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 = - rg_state == 2'd3 && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 && - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 && - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 ; - assign rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 = - rg_watch_tohost && f_reqs_rv[164:101] == rg_tohost_addr && - f_reqs_rv[63:0] != 64'd0 ; - assign updated_word64__h5868 = x__h6241 | y__h6242 ; - assign x__h6241 = word64_old__h5862 & y__h6243 ; - assign y__h6242 = f_reqs_rv[63:0] & mask__h5867 ; - assign y__h6243 = - { ~SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - ~SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - ~SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - ~SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - ~SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - ~SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - ~SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - ~SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - always@(f_reqs_rv or rg_cached_raw_mem_word) - begin - case (f_reqs_rv[105:104]) - 2'd0: word64_old__h5862 = rg_cached_raw_mem_word[63:0]; - 2'd1: word64_old__h5862 = rg_cached_raw_mem_word[127:64]; - 2'd2: word64_old__h5862 = rg_cached_raw_mem_word[191:128]; - 2'd3: word64_old__h5862 = rg_cached_raw_mem_word[255:192]; - endcase - end - always@(n__h5067 or rg_cached_raw_mem_word) - begin - case (n__h5067) - 5'd0: rdata__h5068 = rg_cached_raw_mem_word[63:0]; - 5'd1: rdata__h5068 = rg_cached_raw_mem_word[127:64]; - 5'd2: rdata__h5068 = rg_cached_raw_mem_word[191:128]; - 5'd3: rdata__h5068 = rg_cached_raw_mem_word[255:192]; - default: rdata__h5068 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - rg_status <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000; - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (f_raw_mem_reqs_rv$EN) - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_reqs_rv$D_IN; - if (f_raw_mem_rsps_rv$EN) - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_rsps_rv$D_IN; - if (f_reqs_rv$EN) f_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_reqs_rv$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_status$EN) rg_status <= `BSV_ASSIGNMENT_DELAY rg_status$D_IN; - if (rg_tohost_addr$EN) - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; - if (rg_watch_tohost$EN) - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_cached_clean$EN) - rg_cached_clean <= `BSV_ASSIGNMENT_DELAY rg_cached_clean$D_IN; - if (rg_cached_raw_mem_addr$EN) - rg_cached_raw_mem_addr <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_addr$D_IN; - if (rg_cached_raw_mem_word$EN) - rg_cached_raw_mem_word <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_word$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - f_raw_mem_reqs_rv = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv = 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_cached_clean = 1'h0; - rg_cached_raw_mem_addr = 64'hAAAAAAAAAAAAAAAA; - rg_cached_raw_mem_word = - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state = 2'h2; - rg_status = 8'hAA; - rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; - rg_watch_tohost = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2538 = $stime; - #0; - end - v__h2532 = v__h2538 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING", - v__h2532); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3481 = $stime; - #0; - end - v__h3475 = v__h3481 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h", - v__h3475, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3974 = $stime; - #0; - end - v__h3968 = v__h3974 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h", - v__h3968, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4443 = $stime; - #0; - end - v__h4437 = v__h4443 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h", - v__h4437, - req_raw_mem_addr__h3314); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_reload: raw addr 0x%0h", - v__h4700, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", f_raw_mem_rsps_rv[255:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h5425 = $stime; - #0; - end - v__h5419 = v__h5425 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", rdata__h5068); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h7622 = $stime; - #0; - end - v__h7616 = v__h7622 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7616); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - begin - v__h7823 = $stime; - #0; - end - v__h7817 = v__h7823 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - $display("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h () data 0x%0h", - v__h7817, - f_reqs_rv[164:101], - f_reqs_rv[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] == 63'd0) - $display("PASS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] != 63'd0) - $display("FAIL %0d", exit_value__h7860); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - begin - v__h8335 = $stime; - #0; - end - v__h8329 = v__h8335 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("%0d: ERROR: Mem_Controller:", v__h8329); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" read-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" read-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - begin - v__h9119 = $stime; - #0; - end - v__h9113 = v__h9119 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("%0d: ERROR: Mem_Controller:", v__h9113); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" write-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" write-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - begin - v__h9714 = $stime; - #0; - end - v__h9708 = v__h9714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - $display("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9708, - set_addr_map_addr_base, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h2853 = $stime; - #0; - end - v__h2847 = v__h2853 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_rd_req", v__h2847); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3193 = $stime; - #0; - end - v__h3187 = v__h3193 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_wr_req", v__h3187); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h1743 = $stime; - #0; - end - v__h1737 = v__h1743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_power_on_reset", v__h1737); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2088 = $stime; - #0; - end - v__h2082 = v__h2088 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE", - v__h2082); - end - // synopsys translate_on -endmodule // mkMem_Controller - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v deleted file mode 100644 index 104c51b0..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkMem_Model.v +++ /dev/null @@ -1,192 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_mem_server_request_put O 1 reg -// mem_server_response_get O 256 reg -// RDY_mem_server_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// mem_server_request_put I 353 -// EN_mem_server_request_put I 1 -// EN_mem_server_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Model(CLK, - RST_N, - - mem_server_request_put, - EN_mem_server_request_put, - RDY_mem_server_request_put, - - EN_mem_server_response_get, - mem_server_response_get, - RDY_mem_server_response_get); - input CLK; - input RST_N; - - // action method mem_server_request_put - input [352 : 0] mem_server_request_put; - input EN_mem_server_request_put; - output RDY_mem_server_request_put; - - // actionvalue method mem_server_response_get - input EN_mem_server_response_get; - output [255 : 0] mem_server_response_get; - output RDY_mem_server_response_get; - - // signals for module outputs - wire [255 : 0] mem_server_response_get; - wire RDY_mem_server_request_put, RDY_mem_server_response_get; - - // ports of submodule f_raw_mem_rsps - wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT; - wire f_raw_mem_rsps$CLR, - f_raw_mem_rsps$DEQ, - f_raw_mem_rsps$EMPTY_N, - f_raw_mem_rsps$ENQ, - f_raw_mem_rsps$FULL_N; - - // ports of submodule rf - wire [255 : 0] rf$D_IN, rf$D_OUT_1; - wire [63 : 0] rf$ADDR_1, - rf$ADDR_2, - rf$ADDR_3, - rf$ADDR_4, - rf$ADDR_5, - rf$ADDR_IN; - wire rf$WE; - - // rule scheduling signals - wire CAN_FIRE_mem_server_request_put, - CAN_FIRE_mem_server_response_get, - WILL_FIRE_mem_server_request_put, - WILL_FIRE_mem_server_response_get; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h371; - reg [31 : 0] v__h365; - // synopsys translate_on - - // remaining internal signals - wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2; - - // action method mem_server_request_put - assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ; - - // actionvalue method mem_server_response_get - assign mem_server_response_get = f_raw_mem_rsps$D_OUT ; - assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ; - - // submodule f_raw_mem_rsps - FIFO2 #(.width(32'd256), .guarded(32'd1)) f_raw_mem_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_raw_mem_rsps$D_IN), - .ENQ(f_raw_mem_rsps$ENQ), - .DEQ(f_raw_mem_rsps$DEQ), - .CLR(f_raw_mem_rsps$CLR), - .D_OUT(f_raw_mem_rsps$D_OUT), - .FULL_N(f_raw_mem_rsps$FULL_N), - .EMPTY_N(f_raw_mem_rsps$EMPTY_N)); - - // submodule rf - RegFileLoad #(.file("Mem.hex"), - .addr_width(32'd64), - .data_width(32'd256), - .lo(64'd0), - .hi(64'd8388607), - .binary(1'd0)) rf(.CLK(CLK), - .ADDR_1(rf$ADDR_1), - .ADDR_2(rf$ADDR_2), - .ADDR_3(rf$ADDR_3), - .ADDR_4(rf$ADDR_4), - .ADDR_5(rf$ADDR_5), - .ADDR_IN(rf$ADDR_IN), - .D_IN(rf$D_IN), - .WE(rf$WE), - .D_OUT_1(rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule f_raw_mem_rsps - assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ; - assign f_raw_mem_rsps$ENQ = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - !mem_server_request_put[352] ; - assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ; - assign f_raw_mem_rsps$CLR = 1'b0 ; - - // submodule rf - assign rf$ADDR_1 = mem_server_request_put[319:256] ; - assign rf$ADDR_2 = 64'h0 ; - assign rf$ADDR_3 = 64'h0 ; - assign rf$ADDR_4 = 64'h0 ; - assign rf$ADDR_5 = 64'h0 ; - assign rf$ADDR_IN = mem_server_request_put[319:256] ; - assign rf$D_IN = mem_server_request_put[255:0] ; - assign rf$WE = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - mem_server_request_put[352] ; - - // remaining internal signals - assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 = - mem_server_request_put[319:256] < 64'h0000000000800000 ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - begin - v__h371 = $stime; - #0; - end - v__h365 = v__h371 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)", - v__h365, - mem_server_request_put[319:256], - 64'h0000000000800000); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkMem_Model - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v deleted file mode 100644 index 5e2773cc..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem.v +++ /dev/null @@ -1,1654 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 -// RDY_server_reset_response_get O 1 reg -// imem_valid O 1 -// imem_is_i32_not_i16 O 1 const -// imem_pc O 64 reg -// imem_instr O 32 -// imem_exc O 1 -// imem_exc_code O 4 reg -// imem_tval O 64 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_valid O 1 -// dmem_word64 O 64 -// dmem_st_amo_val O 64 -// dmem_exc O 1 -// dmem_exc_code O 4 reg -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_server_fence_i_request_put O 1 -// RDY_server_fence_i_response_get O 1 -// RDY_server_fence_request_put O 1 reg -// RDY_server_fence_response_get O 1 -// RDY_sfence_vma O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// imem_req_f3 I 3 -// imem_req_addr I 64 -// imem_req_priv I 2 unused -// imem_req_sstatus_SUM I 1 unused -// imem_req_mstatus_MXR I 1 unused -// imem_req_satp I 64 unused -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_req_op I 2 -// dmem_req_f3 I 3 -// dmem_req_amo_funct7 I 7 reg -// dmem_req_addr I 64 -// dmem_req_store_value I 64 -// dmem_req_priv I 2 unused -// dmem_req_sstatus_SUM I 1 unused -// dmem_req_mstatus_MXR I 1 unused -// dmem_req_satp I 64 unused -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// server_fence_request_put I 8 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_imem_req I 1 -// EN_dmem_req I 1 -// EN_server_fence_i_request_put I 1 -// EN_server_fence_i_response_get I 1 -// EN_server_fence_request_put I 1 -// EN_server_fence_response_get I 1 -// EN_sfence_vma I 1 unused -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_valid -// (imem_master_awready, imem_master_wready) -> imem_instr -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, imem_master_wready, EN_imem_req) -> imem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_valid -// (dmem_master_awready, dmem_master_wready) -> dmem_word64 -// (dmem_master_awready, dmem_master_wready) -> dmem_st_amo_val -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// (dmem_master_awready, dmem_master_wready, EN_dmem_req) -> dmem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - imem_req_f3, - imem_req_addr, - imem_req_priv, - imem_req_sstatus_SUM, - imem_req_mstatus_MXR, - imem_req_satp, - EN_imem_req, - - imem_valid, - - imem_is_i32_not_i16, - - imem_pc, - - imem_instr, - - imem_exc, - - imem_exc_code, - - imem_tval, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_req_op, - dmem_req_f3, - dmem_req_amo_funct7, - dmem_req_addr, - dmem_req_store_value, - dmem_req_priv, - dmem_req_sstatus_SUM, - dmem_req_mstatus_MXR, - dmem_req_satp, - EN_dmem_req, - - dmem_valid, - - dmem_word64, - - dmem_st_amo_val, - - dmem_exc, - - dmem_exc_code, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - EN_server_fence_i_request_put, - RDY_server_fence_i_request_put, - - EN_server_fence_i_response_get, - RDY_server_fence_i_response_get, - - server_fence_request_put, - EN_server_fence_request_put, - RDY_server_fence_request_put, - - EN_server_fence_response_get, - RDY_server_fence_response_get, - - EN_sfence_vma, - RDY_sfence_vma); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method imem_req - input [2 : 0] imem_req_f3; - input [63 : 0] imem_req_addr; - input [1 : 0] imem_req_priv; - input imem_req_sstatus_SUM; - input imem_req_mstatus_MXR; - input [63 : 0] imem_req_satp; - input EN_imem_req; - - // value method imem_valid - output imem_valid; - - // value method imem_is_i32_not_i16 - output imem_is_i32_not_i16; - - // value method imem_pc - output [63 : 0] imem_pc; - - // value method imem_instr - output [31 : 0] imem_instr; - - // value method imem_exc - output imem_exc; - - // value method imem_exc_code - output [3 : 0] imem_exc_code; - - // value method imem_tval - output [63 : 0] imem_tval; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // action method dmem_req - input [1 : 0] dmem_req_op; - input [2 : 0] dmem_req_f3; - input [6 : 0] dmem_req_amo_funct7; - input [63 : 0] dmem_req_addr; - input [63 : 0] dmem_req_store_value; - input [1 : 0] dmem_req_priv; - input dmem_req_sstatus_SUM; - input dmem_req_mstatus_MXR; - input [63 : 0] dmem_req_satp; - input EN_dmem_req; - - // value method dmem_valid - output dmem_valid; - - // value method dmem_word64 - output [63 : 0] dmem_word64; - - // value method dmem_st_amo_val - output [63 : 0] dmem_st_amo_val; - - // value method dmem_exc - output dmem_exc; - - // value method dmem_exc_code - output [3 : 0] dmem_exc_code; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method server_fence_i_request_put - input EN_server_fence_i_request_put; - output RDY_server_fence_i_request_put; - - // action method server_fence_i_response_get - input EN_server_fence_i_response_get; - output RDY_server_fence_i_response_get; - - // action method server_fence_request_put - input [7 : 0] server_fence_request_put; - input EN_server_fence_request_put; - output RDY_server_fence_request_put; - - // action method server_fence_response_get - input EN_server_fence_response_get; - output RDY_server_fence_response_get; - - // action method sfence_vma - input EN_sfence_vma; - output RDY_sfence_vma; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - dmem_st_amo_val, - dmem_word64, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata, - imem_pc, - imem_tval; - wire [31 : 0] imem_instr; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_exc_code, - dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_exc_code, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_server_fence_i_request_put, - RDY_server_fence_i_response_get, - RDY_server_fence_request_put, - RDY_server_fence_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_sfence_vma, - dmem_exc, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - dmem_valid, - imem_exc, - imem_is_i32_not_i16, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid, - imem_valid; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule dcache - wire [63 : 0] dcache$mem_master_araddr, - dcache$mem_master_awaddr, - dcache$mem_master_rdata, - dcache$mem_master_wdata, - dcache$req_addr, - dcache$req_satp, - dcache$req_st_value, - dcache$st_amo_val, - dcache$word64; - wire [7 : 0] dcache$mem_master_arlen, - dcache$mem_master_awlen, - dcache$mem_master_wstrb; - wire [6 : 0] dcache$req_amo_funct7; - wire [3 : 0] dcache$exc_code, - dcache$mem_master_arcache, - dcache$mem_master_arid, - dcache$mem_master_arqos, - dcache$mem_master_arregion, - dcache$mem_master_awcache, - dcache$mem_master_awid, - dcache$mem_master_awqos, - dcache$mem_master_awregion, - dcache$mem_master_bid, - dcache$mem_master_rid, - dcache$mem_master_wid, - dcache$set_verbosity_verbosity; - wire [2 : 0] dcache$mem_master_arprot, - dcache$mem_master_arsize, - dcache$mem_master_awprot, - dcache$mem_master_awsize, - dcache$req_f3; - wire [1 : 0] dcache$mem_master_arburst, - dcache$mem_master_awburst, - dcache$mem_master_bresp, - dcache$mem_master_rresp, - dcache$req_op, - dcache$req_priv; - wire dcache$EN_req, - dcache$EN_server_flush_request_put, - dcache$EN_server_flush_response_get, - dcache$EN_server_reset_request_put, - dcache$EN_server_reset_response_get, - dcache$EN_set_verbosity, - dcache$EN_tlb_flush, - dcache$RDY_server_flush_request_put, - dcache$RDY_server_flush_response_get, - dcache$RDY_server_reset_request_put, - dcache$RDY_server_reset_response_get, - dcache$exc, - dcache$mem_master_arlock, - dcache$mem_master_arready, - dcache$mem_master_arvalid, - dcache$mem_master_awlock, - dcache$mem_master_awready, - dcache$mem_master_awvalid, - dcache$mem_master_bready, - dcache$mem_master_bvalid, - dcache$mem_master_rlast, - dcache$mem_master_rready, - dcache$mem_master_rvalid, - dcache$mem_master_wlast, - dcache$mem_master_wready, - dcache$mem_master_wvalid, - dcache$req_mstatus_MXR, - dcache$req_sstatus_SUM, - dcache$valid; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule icache - wire [63 : 0] icache$addr, - icache$mem_master_araddr, - icache$mem_master_awaddr, - icache$mem_master_rdata, - icache$mem_master_wdata, - icache$req_addr, - icache$req_satp, - icache$req_st_value, - icache$word64; - wire [7 : 0] icache$mem_master_arlen, - icache$mem_master_awlen, - icache$mem_master_wstrb; - wire [6 : 0] icache$req_amo_funct7; - wire [3 : 0] icache$exc_code, - icache$mem_master_arcache, - icache$mem_master_arid, - icache$mem_master_arqos, - icache$mem_master_arregion, - icache$mem_master_awcache, - icache$mem_master_awid, - icache$mem_master_awqos, - icache$mem_master_awregion, - icache$mem_master_bid, - icache$mem_master_rid, - icache$mem_master_wid, - icache$set_verbosity_verbosity; - wire [2 : 0] icache$mem_master_arprot, - icache$mem_master_arsize, - icache$mem_master_awprot, - icache$mem_master_awsize, - icache$req_f3; - wire [1 : 0] icache$mem_master_arburst, - icache$mem_master_awburst, - icache$mem_master_bresp, - icache$mem_master_rresp, - icache$req_op, - icache$req_priv; - wire icache$EN_req, - icache$EN_server_flush_request_put, - icache$EN_server_flush_response_get, - icache$EN_server_reset_request_put, - icache$EN_server_reset_response_get, - icache$EN_set_verbosity, - icache$EN_tlb_flush, - icache$RDY_server_flush_request_put, - icache$RDY_server_flush_response_get, - icache$RDY_server_reset_request_put, - icache$RDY_server_reset_response_get, - icache$exc, - icache$mem_master_arlock, - icache$mem_master_arready, - icache$mem_master_arvalid, - icache$mem_master_awlock, - icache$mem_master_awready, - icache$mem_master_awvalid, - icache$mem_master_bready, - icache$mem_master_bvalid, - icache$mem_master_rlast, - icache$mem_master_rready, - icache$mem_master_rvalid, - icache$mem_master_wlast, - icache$mem_master_wready, - icache$mem_master_wvalid, - icache$req_mstatus_MXR, - icache$req_sstatus_SUM, - icache$valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_dmem_req, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_imem_req, - CAN_FIRE_server_fence_i_request_put, - CAN_FIRE_server_fence_i_response_get, - CAN_FIRE_server_fence_request_put, - CAN_FIRE_server_fence_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_sfence_vma, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_dmem_req, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_imem_req, - WILL_FIRE_server_fence_i_request_put, - WILL_FIRE_server_fence_i_response_get, - WILL_FIRE_server_fence_request_put, - WILL_FIRE_server_fence_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_sfence_vma; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h1675; - reg [31 : 0] v__h1826; - reg [31 : 0] v__h1669; - reg [31 : 0] v__h1820; - // synopsys translate_on - - // remaining internal signals - wire NOT_cfg_verbosity_read_ULE_1___d9; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = rg_state == 2'd2 ; - assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method imem_req - assign CAN_FIRE_imem_req = 1'd1 ; - assign WILL_FIRE_imem_req = EN_imem_req ; - - // value method imem_valid - assign imem_valid = icache$valid ; - - // value method imem_is_i32_not_i16 - assign imem_is_i32_not_i16 = 1'd1 ; - - // value method imem_pc - assign imem_pc = icache$addr ; - - // value method imem_instr - assign imem_instr = icache$word64[31:0] ; - - // value method imem_exc - assign imem_exc = icache$exc ; - - // value method imem_exc_code - assign imem_exc_code = icache$exc_code ; - - // value method imem_tval - assign imem_tval = icache$addr ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = icache$mem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = icache$mem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = icache$mem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = icache$mem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = icache$mem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = icache$mem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = icache$mem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = icache$mem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = icache$mem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = icache$mem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = icache$mem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = icache$mem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = icache$mem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = icache$mem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = icache$mem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = icache$mem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = icache$mem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = icache$mem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = icache$mem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = icache$mem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = icache$mem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = icache$mem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = icache$mem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = icache$mem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = icache$mem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = icache$mem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = icache$mem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = icache$mem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = icache$mem_master_rready ; - - // action method dmem_req - assign CAN_FIRE_dmem_req = 1'd1 ; - assign WILL_FIRE_dmem_req = EN_dmem_req ; - - // value method dmem_valid - assign dmem_valid = dcache$valid ; - - // value method dmem_word64 - assign dmem_word64 = dcache$word64 ; - - // value method dmem_st_amo_val - assign dmem_st_amo_val = dcache$st_amo_val ; - - // value method dmem_exc - assign dmem_exc = dcache$exc ; - - // value method dmem_exc_code - assign dmem_exc_code = dcache$exc_code ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = dcache$mem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = dcache$mem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = dcache$mem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = dcache$mem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = dcache$mem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = dcache$mem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = dcache$mem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = dcache$mem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = dcache$mem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = dcache$mem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = dcache$mem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = dcache$mem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = dcache$mem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = dcache$mem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = dcache$mem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = dcache$mem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = dcache$mem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = dcache$mem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = dcache$mem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = dcache$mem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = dcache$mem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = dcache$mem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = dcache$mem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = dcache$mem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = dcache$mem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = dcache$mem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = dcache$mem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = dcache$mem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = dcache$mem_master_rready ; - - // action method server_fence_i_request_put - assign RDY_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_i_request_put = - EN_server_fence_i_request_put ; - - // action method server_fence_i_response_get - assign RDY_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_i_response_get = - EN_server_fence_i_response_get ; - - // action method server_fence_request_put - assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_request_put = - dcache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ; - - // action method server_fence_response_get - assign RDY_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ; - - // action method sfence_vma - assign RDY_sfence_vma = 1'd1 ; - assign CAN_FIRE_sfence_vma = 1'd1 ; - assign WILL_FIRE_sfence_vma = EN_sfence_vma ; - - // submodule dcache - mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(dcache$mem_master_arready), - .mem_master_awready(dcache$mem_master_awready), - .mem_master_bid(dcache$mem_master_bid), - .mem_master_bresp(dcache$mem_master_bresp), - .mem_master_bvalid(dcache$mem_master_bvalid), - .mem_master_rdata(dcache$mem_master_rdata), - .mem_master_rid(dcache$mem_master_rid), - .mem_master_rlast(dcache$mem_master_rlast), - .mem_master_rresp(dcache$mem_master_rresp), - .mem_master_rvalid(dcache$mem_master_rvalid), - .mem_master_wready(dcache$mem_master_wready), - .req_addr(dcache$req_addr), - .req_amo_funct7(dcache$req_amo_funct7), - .req_f3(dcache$req_f3), - .req_mstatus_MXR(dcache$req_mstatus_MXR), - .req_op(dcache$req_op), - .req_priv(dcache$req_priv), - .req_satp(dcache$req_satp), - .req_sstatus_SUM(dcache$req_sstatus_SUM), - .req_st_value(dcache$req_st_value), - .set_verbosity_verbosity(dcache$set_verbosity_verbosity), - .EN_set_verbosity(dcache$EN_set_verbosity), - .EN_server_reset_request_put(dcache$EN_server_reset_request_put), - .EN_server_reset_response_get(dcache$EN_server_reset_response_get), - .EN_req(dcache$EN_req), - .EN_server_flush_request_put(dcache$EN_server_flush_request_put), - .EN_server_flush_response_get(dcache$EN_server_flush_response_get), - .EN_tlb_flush(dcache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), - .valid(dcache$valid), - .addr(), - .word64(dcache$word64), - .st_amo_val(dcache$st_amo_val), - .exc(dcache$exc), - .exc_code(dcache$exc_code), - .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(dcache$mem_master_awvalid), - .mem_master_awid(dcache$mem_master_awid), - .mem_master_awaddr(dcache$mem_master_awaddr), - .mem_master_awlen(dcache$mem_master_awlen), - .mem_master_awsize(dcache$mem_master_awsize), - .mem_master_awburst(dcache$mem_master_awburst), - .mem_master_awlock(dcache$mem_master_awlock), - .mem_master_awcache(dcache$mem_master_awcache), - .mem_master_awprot(dcache$mem_master_awprot), - .mem_master_awqos(dcache$mem_master_awqos), - .mem_master_awregion(dcache$mem_master_awregion), - .mem_master_wvalid(dcache$mem_master_wvalid), - .mem_master_wid(dcache$mem_master_wid), - .mem_master_wdata(dcache$mem_master_wdata), - .mem_master_wstrb(dcache$mem_master_wstrb), - .mem_master_wlast(dcache$mem_master_wlast), - .mem_master_bready(dcache$mem_master_bready), - .mem_master_arvalid(dcache$mem_master_arvalid), - .mem_master_arid(dcache$mem_master_arid), - .mem_master_araddr(dcache$mem_master_araddr), - .mem_master_arlen(dcache$mem_master_arlen), - .mem_master_arsize(dcache$mem_master_arsize), - .mem_master_arburst(dcache$mem_master_arburst), - .mem_master_arlock(dcache$mem_master_arlock), - .mem_master_arcache(dcache$mem_master_arcache), - .mem_master_arprot(dcache$mem_master_arprot), - .mem_master_arqos(dcache$mem_master_arqos), - .mem_master_arregion(dcache$mem_master_arregion), - .mem_master_rready(dcache$mem_master_rready)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule icache - mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(icache$mem_master_arready), - .mem_master_awready(icache$mem_master_awready), - .mem_master_bid(icache$mem_master_bid), - .mem_master_bresp(icache$mem_master_bresp), - .mem_master_bvalid(icache$mem_master_bvalid), - .mem_master_rdata(icache$mem_master_rdata), - .mem_master_rid(icache$mem_master_rid), - .mem_master_rlast(icache$mem_master_rlast), - .mem_master_rresp(icache$mem_master_rresp), - .mem_master_rvalid(icache$mem_master_rvalid), - .mem_master_wready(icache$mem_master_wready), - .req_addr(icache$req_addr), - .req_amo_funct7(icache$req_amo_funct7), - .req_f3(icache$req_f3), - .req_mstatus_MXR(icache$req_mstatus_MXR), - .req_op(icache$req_op), - .req_priv(icache$req_priv), - .req_satp(icache$req_satp), - .req_sstatus_SUM(icache$req_sstatus_SUM), - .req_st_value(icache$req_st_value), - .set_verbosity_verbosity(icache$set_verbosity_verbosity), - .EN_set_verbosity(icache$EN_set_verbosity), - .EN_server_reset_request_put(icache$EN_server_reset_request_put), - .EN_server_reset_response_get(icache$EN_server_reset_response_get), - .EN_req(icache$EN_req), - .EN_server_flush_request_put(icache$EN_server_flush_request_put), - .EN_server_flush_response_get(icache$EN_server_flush_response_get), - .EN_tlb_flush(icache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), - .valid(icache$valid), - .addr(icache$addr), - .word64(icache$word64), - .st_amo_val(), - .exc(icache$exc), - .exc_code(icache$exc_code), - .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(icache$mem_master_awvalid), - .mem_master_awid(icache$mem_master_awid), - .mem_master_awaddr(icache$mem_master_awaddr), - .mem_master_awlen(icache$mem_master_awlen), - .mem_master_awsize(icache$mem_master_awsize), - .mem_master_awburst(icache$mem_master_awburst), - .mem_master_awlock(icache$mem_master_awlock), - .mem_master_awcache(icache$mem_master_awcache), - .mem_master_awprot(icache$mem_master_awprot), - .mem_master_awqos(icache$mem_master_awqos), - .mem_master_awregion(icache$mem_master_awregion), - .mem_master_wvalid(icache$mem_master_wvalid), - .mem_master_wid(icache$mem_master_wid), - .mem_master_wdata(icache$mem_master_wdata), - .mem_master_wstrb(icache$mem_master_wstrb), - .mem_master_wlast(icache$mem_master_wlast), - .mem_master_bready(icache$mem_master_bready), - .mem_master_arvalid(icache$mem_master_arvalid), - .mem_master_arid(icache$mem_master_arid), - .mem_master_araddr(icache$mem_master_araddr), - .mem_master_arlen(icache$mem_master_arlen), - .mem_master_arsize(icache$mem_master_arsize), - .mem_master_arburst(icache$mem_master_arburst), - .mem_master_arlock(icache$mem_master_arlock), - .mem_master_arcache(icache$mem_master_arcache), - .mem_master_arprot(icache$mem_master_arprot), - .mem_master_arqos(icache$mem_master_arqos), - .mem_master_arregion(icache$mem_master_arregion), - .mem_master_rready(icache$mem_master_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - dcache$RDY_server_reset_request_put && - icache$RDY_server_reset_request_put && - rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && - !EN_server_fence_i_request_put ; - assign MUX_rg_state$write_1__SEL_3 = - dcache$RDY_server_reset_response_get && - icache$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - rg_state == 2'd1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete) - begin - case (1'b1) // synopsys parallel_case - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1; - WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset || - WILL_FIRE_RL_rl_reset_complete ; - - // submodule dcache - assign dcache$mem_master_arready = dmem_master_arready ; - assign dcache$mem_master_awready = dmem_master_awready ; - assign dcache$mem_master_bid = dmem_master_bid ; - assign dcache$mem_master_bresp = dmem_master_bresp ; - assign dcache$mem_master_bvalid = dmem_master_bvalid ; - assign dcache$mem_master_rdata = dmem_master_rdata ; - assign dcache$mem_master_rid = dmem_master_rid ; - assign dcache$mem_master_rlast = dmem_master_rlast ; - assign dcache$mem_master_rresp = dmem_master_rresp ; - assign dcache$mem_master_rvalid = dmem_master_rvalid ; - assign dcache$mem_master_wready = dmem_master_wready ; - assign dcache$req_addr = dmem_req_addr ; - assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ; - assign dcache$req_f3 = dmem_req_f3 ; - assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ; - assign dcache$req_op = dmem_req_op ; - assign dcache$req_priv = dmem_req_priv ; - assign dcache$req_satp = dmem_req_satp ; - assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ; - assign dcache$req_st_value = dmem_req_store_value ; - assign dcache$set_verbosity_verbosity = 4'h0 ; - assign dcache$EN_set_verbosity = 1'b0 ; - assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign dcache$EN_req = EN_dmem_req ; - assign dcache$EN_server_flush_request_put = - EN_server_fence_i_request_put || EN_server_fence_request_put ; - assign dcache$EN_server_flush_response_get = - EN_server_fence_i_response_get || EN_server_fence_response_get ; - assign dcache$EN_tlb_flush = EN_sfence_vma ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule icache - assign icache$mem_master_arready = imem_master_arready ; - assign icache$mem_master_awready = imem_master_awready ; - assign icache$mem_master_bid = imem_master_bid ; - assign icache$mem_master_bresp = imem_master_bresp ; - assign icache$mem_master_bvalid = imem_master_bvalid ; - assign icache$mem_master_rdata = imem_master_rdata ; - assign icache$mem_master_rid = imem_master_rid ; - assign icache$mem_master_rlast = imem_master_rlast ; - assign icache$mem_master_rresp = imem_master_rresp ; - assign icache$mem_master_rvalid = imem_master_rvalid ; - assign icache$mem_master_wready = imem_master_wready ; - assign icache$req_addr = imem_req_addr ; - assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ; - assign icache$req_f3 = imem_req_f3 ; - assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ; - assign icache$req_op = 2'd0 ; - assign icache$req_priv = imem_req_priv ; - assign icache$req_satp = imem_req_satp ; - assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ; - assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign icache$set_verbosity_verbosity = 4'h0 ; - assign icache$EN_set_verbosity = 1'b0 ; - assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign icache$EN_req = EN_imem_req ; - assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ; - assign icache$EN_server_flush_response_get = - EN_server_fence_i_response_get ; - assign icache$EN_tlb_flush = EN_sfence_vma ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1675 = $stime; - #0; - end - v__h1669 = v__h1675 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset", v__h1669); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1826 = $stime; - #0; - end - v__h1820 = v__h1826 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset_complete", v__h1820); - end - // synopsys translate_on -endmodule // mkNear_Mem - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v deleted file mode 100644 index 32e93584..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO.v +++ /dev/null @@ -1,1308 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// RDY_server_request_put O 1 reg -// server_response_get O 66 reg -// RDY_server_response_get O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// server_request_put I 137 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_server_request_put I 1 -// EN_server_response_get I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - server_request_put, - EN_server_request_put, - RDY_server_request_put, - - EN_server_response_get, - server_response_get, - RDY_server_response_get, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method server_request_put - input [136 : 0] server_request_put; - input EN_server_request_put; - output RDY_server_request_put; - - // actionvalue method server_response_get - input EN_server_response_get; - output [65 : 0] server_response_get; - output RDY_server_response_get; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [65 : 0] server_response_get; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_request_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_server_response_get, - RDY_set_addr_map, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reqs - wire [136 : 0] f_reqs$D_IN, f_reqs$D_OUT; - wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_rsps - wire [65 : 0] f_rsps$D_IN, f_rsps$D_OUT; - wire f_rsps$CLR, f_rsps$DEQ, f_rsps$EMPTY_N, f_rsps$ENQ, f_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_request_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_server_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_request_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_server_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire [65 : 0] MUX_f_rsps$enq_1__VAL_1, MUX_f_rsps$enq_1__VAL_2; - wire [63 : 0] MUX_crg_time$port1__write_1__VAL_1, - MUX_crg_timecmp$port1__write_1__VAL_1; - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8676; - reg [31 : 0] v__h8808; - reg [31 : 0] v__h1471; - reg [31 : 0] v__h1868; - reg [31 : 0] v__h2065; - reg [31 : 0] v__h1714; - reg [31 : 0] v__h2442; - reg [31 : 0] v__h7890; - reg [31 : 0] v__h8258; - reg [31 : 0] v__h8368; - reg [31 : 0] v__h8475; - reg [31 : 0] v__h1465; - reg [31 : 0] v__h1708; - reg [31 : 0] v__h1862; - reg [31 : 0] v__h2059; - reg [31 : 0] v__h2436; - reg [31 : 0] v__h7884; - reg [31 : 0] v__h8252; - reg [31 : 0] v__h8362; - reg [31 : 0] v__h8469; - reg [31 : 0] v__h8670; - reg [31 : 0] v__h8802; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rsp_rdata__h2209; - wire [63 : 0] byte_addr__h1981, - mask__h2865, - mask__h5362, - new_data__h5360, - new_time__h4107, - new_time__h6632, - new_timecmp__h2834, - new_timecmp__h5331, - old_time__h6631, - rdata__h1996, - rdata__h2020, - rdata__h2026, - x__h2876, - x__h4149, - x__h5373, - x__h6674, - y__h2877, - y__h2878, - y__h5374, - y__h5375; - wire [7 : 0] SEXT_f_reqs_first__8_BIT_0_31___d132, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_7_07___d108; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method server_request_put - assign RDY_server_request_put = f_reqs$FULL_N ; - assign CAN_FIRE_server_request_put = f_reqs$FULL_N ; - assign WILL_FIRE_server_request_put = EN_server_request_put ; - - // actionvalue method server_response_get - assign server_response_get = f_rsps$D_OUT ; - assign RDY_server_response_get = f_rsps$EMPTY_N ; - assign CAN_FIRE_server_response_get = f_rsps$EMPTY_N ; - assign WILL_FIRE_server_response_get = EN_server_response_get ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reqs - FIFO2 #(.width(32'd137), .guarded(32'd1)) f_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reqs$D_IN), - .ENQ(f_reqs$ENQ), - .DEQ(f_reqs$DEQ), - .CLR(f_reqs$CLR), - .D_OUT(f_reqs$D_OUT), - .FULL_N(f_reqs$FULL_N), - .EMPTY_N(f_reqs$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_rsps - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_rsps$D_IN), - .ENQ(f_rsps$ENQ), - .DEQ(f_rsps$DEQ), - .CLR(f_rsps$CLR), - .D_OUT(f_rsps$D_OUT), - .FULL_N(f_rsps$FULL_N), - .EMPTY_N(f_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && rg_state && - !f_reset_reqs$EMPTY_N && - f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && - (byte_addr__h1981 != 64'h0 || - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - f_sw_interrupt_req$FULL_N) && - rg_state && - !f_reset_reqs$EMPTY_N && - !f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign MUX_crg_time$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h000000000000BFF8) ? - new_time__h4107 : - new_time__h6632 ; - assign MUX_crg_timecmp$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h0000000000004000) ? - new_timecmp__h2834 : - new_timecmp__h5331 ; - assign MUX_f_rsps$enq_1__VAL_1 = - { 1'd1, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - rsp_rdata__h2209 } ; - assign MUX_f_rsps$enq_1__VAL_2 = - { 1'd0, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - 64'hAAAAAAAAAAAAAAAA } ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? - MUX_crg_time$port1__write_1__VAL_1 : - 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h6631 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - MUX_crg_timecmp$port1__write_1__VAL_1 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = MUX_rg_msip$write_1__SEL_1 && f_reqs$D_OUT[8] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reqs - assign f_reqs$D_IN = server_request_put ; - assign f_reqs$ENQ = EN_server_request_put ; - assign f_reqs$DEQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_rsps - assign f_rsps$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_f_rsps$enq_1__VAL_1 : - MUX_f_rsps$enq_1__VAL_2 ; - assign f_rsps$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_process_wr_req ; - assign f_rsps$DEQ = EN_server_response_get ; - assign f_rsps$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = f_reqs$D_OUT[8] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_f_reqs_first__8_BIT_0_31___d132 = {8{f_reqs$D_OUT[0]}} ; - assign SEXT_f_reqs_first__8_BIT_1_28___d129 = {8{f_reqs$D_OUT[1]}} ; - assign SEXT_f_reqs_first__8_BIT_2_24___d125 = {8{f_reqs$D_OUT[2]}} ; - assign SEXT_f_reqs_first__8_BIT_3_21___d122 = {8{f_reqs$D_OUT[3]}} ; - assign SEXT_f_reqs_first__8_BIT_4_17___d118 = {8{f_reqs$D_OUT[4]}} ; - assign SEXT_f_reqs_first__8_BIT_5_14___d115 = {8{f_reqs$D_OUT[5]}} ; - assign SEXT_f_reqs_first__8_BIT_6_10___d111 = {8{f_reqs$D_OUT[6]}} ; - assign SEXT_f_reqs_first__8_BIT_7_07___d108 = {8{f_reqs$D_OUT[7]}} ; - assign byte_addr__h1981 = f_reqs$D_OUT[135:72] - rg_addr_base ; - assign mask__h2865 = - { SEXT_f_reqs_first__8_BIT_7_07___d108, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign mask__h5362 = - { SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'd0 } ; - assign new_data__h5360 = { f_reqs$D_OUT[39:8], 32'h0 } ; - assign new_time__h4107 = x__h4149 | y__h2877 ; - assign new_time__h6632 = x__h6674 | y__h5374 ; - assign new_timecmp__h2834 = x__h2876 | y__h2877 ; - assign new_timecmp__h5331 = x__h5373 | y__h5374 ; - assign old_time__h6631 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata__h1996 = { 63'd0, rg_msip } ; - assign rdata__h2020 = { 32'd0, crg_timecmp[63:32] } ; - assign rdata__h2026 = { 32'd0, crg_time[63:32] } ; - assign rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 = - rg_msip == f_reqs$D_OUT[8] ; - assign x__h2876 = crg_timecmp & y__h2878 ; - assign x__h4149 = old_time__h6631 & y__h2878 ; - assign x__h5373 = crg_timecmp & y__h5375 ; - assign x__h6674 = old_time__h6631 & y__h5375 ; - assign y__h2877 = f_reqs$D_OUT[71:8] & mask__h2865 ; - assign y__h2878 = - { ~SEXT_f_reqs_first__8_BIT_7_07___d108, - ~SEXT_f_reqs_first__8_BIT_6_10___d111, - ~SEXT_f_reqs_first__8_BIT_5_14___d115, - ~SEXT_f_reqs_first__8_BIT_4_17___d118, - ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign y__h5374 = new_data__h5360 & mask__h5362 ; - assign y__h5375 = - { ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'hFFFFFFFF } ; - always@(byte_addr__h1981 or - rdata__h1996 or - crg_timecmp or rdata__h2020 or crg_time or rdata__h2026) - begin - case (byte_addr__h1981) - 64'h0: rsp_rdata__h2209 = rdata__h1996; - 64'h0000000000000004: rsp_rdata__h2209 = 64'd0; - 64'h0000000000004000: rsp_rdata__h2209 = crg_timecmp; - 64'h0000000000004004: rsp_rdata__h2209 = rdata__h2020; - 64'h000000000000BFF8: rsp_rdata__h2209 = crg_time; - 64'h000000000000BFFC: rsp_rdata__h2209 = rdata__h2026; - default: rsp_rdata__h2209 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8676 = $stime; - #0; - end - v__h8670 = v__h8676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_timer_interrupt_req: %x", - v__h8670, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8808 = $stime; - #0; - end - v__h8802 = v__h8808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_sw_interrupt_req: %x", - v__h8802, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1471 = $stime; - #0; - end - v__h1465 = v__h1471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO.rl_reset", v__h1465); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1868 = $stime; - #0; - end - v__h1862 = v__h1868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_rd_req: rg_mtip = %0d", - v__h1862, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h2065 = $stime; - #0; - end - v__h2059 = v__h2065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_rd_req: unrecognized addr", - v__h2059); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rsp_rdata__h2209, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1714 = $stime; - #0; - end - v__h1708 = v__h1714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h1708, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2442 = $stime; - #0; - end - v__h2436 = v__h2442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_wr_req: rg_mtip = %0d", - v__h2436, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", f_reqs$D_OUT[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h2834); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h2834 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h4107); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h5331); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h5331 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h6632); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h7890 = $stime; - #0; - end - v__h7884 = v__h7890 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_wr_req: unrecognized addr", - v__h7884); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 64'hAAAAAAAAAAAAAAAA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h8258 = $stime; - #0; - end - v__h8252 = v__h8258 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h8252, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h8368 = $stime; - #0; - end - v__h8362 = v__h8368 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h8362, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h8475 = $stime; - #0; - end - v__h8469 = v__h8475 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h8469, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v deleted file mode 100644 index 0883c8da..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkNear_Mem_IO_AXI4.v +++ /dev/null @@ -1,2812 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO_AXI4(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h10065; - reg [31 : 0] v__h10197; - reg [31 : 0] v__h1852; - reg [31 : 0] v__h2269; - reg [31 : 0] v__h2453; - reg [31 : 0] v__h2640; - reg [31 : 0] v__h2878; - reg [31 : 0] v__h2095; - reg [31 : 0] v__h3161; - reg [31 : 0] v__h3391; - reg [31 : 0] v__h8927; - reg [31 : 0] v__h9148; - reg [31 : 0] v__h9475; - reg [31 : 0] v__h9585; - reg [31 : 0] v__h9692; - reg [31 : 0] v__h1846; - reg [31 : 0] v__h2089; - reg [31 : 0] v__h2263; - reg [31 : 0] v__h2447; - reg [31 : 0] v__h2634; - reg [31 : 0] v__h2872; - reg [31 : 0] v__h3155; - reg [31 : 0] v__h3385; - reg [31 : 0] v__h8921; - reg [31 : 0] v__h9142; - reg [31 : 0] v__h9469; - reg [31 : 0] v__h9579; - reg [31 : 0] v__h9686; - reg [31 : 0] v__h10059; - reg [31 : 0] v__h10191; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] _theResult___fst__h2566; - reg [1 : 0] _theResult___snd__h2567, v__h3517; - wire [63 : 0] byte_addr__h2405, - byte_addr__h3353, - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190, - mask__h3798, - new_time__h5056, - new_timecmp__h3767, - old_time__h7614, - rdata___1__h2562, - x__h2751, - x__h3809, - x__h5098, - y__h3810, - y__h3811; - wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153; - wire [1 : 0] rresp__h2548, v__h3357; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108, - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53, - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102, - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? new_time__h5056 : 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h7614 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - new_timecmp__h3767 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = - MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - x__h2751, - rresp__h2548, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3357 } ; - assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 = - {8{slave_xactor_f_wr_data$D_OUT[1]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174 = - {8{slave_xactor_f_wr_data$D_OUT[2]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170 = - {8{slave_xactor_f_wr_data$D_OUT[3]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167 = - {8{slave_xactor_f_wr_data$D_OUT[4]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163 = - {8{slave_xactor_f_wr_data$D_OUT[5]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160 = - {8{slave_xactor_f_wr_data$D_OUT[6]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156 = - {8{slave_xactor_f_wr_data$D_OUT[7]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153 = - {8{slave_xactor_f_wr_data$D_OUT[8]}} ; - assign byte_addr__h2405 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign byte_addr__h3353 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190 = - new_timecmp__h3767 - old_time__h7614 ; - assign mask__h3798 = - { SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - assign new_time__h5056 = x__h5098 | y__h3810 ; - assign new_timecmp__h3767 = x__h3809 | y__h3810 ; - assign old_time__h7614 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata___1__h2562 = { 63'd0, rg_msip } ; - assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 = - rg_msip == slave_xactor_f_wr_data$D_OUT[9] ; - assign rresp__h2548 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 2'b11 : - _theResult___snd__h2567 ; - assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 = - slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 = - slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 || - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - f_sw_interrupt_req$FULL_N) ; - assign v__h3357 = - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ? - 2'b11 : - v__h3517 ; - assign x__h2751 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 64'd0 : - _theResult___fst__h2566 ; - assign x__h3809 = crg_timecmp & y__h3811 ; - assign x__h5098 = old_time__h7614 & y__h3811 ; - assign y__h3810 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3798 ; - assign y__h3811 = - { ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - always@(byte_addr__h2405) - begin - case (byte_addr__h2405) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - _theResult___snd__h2567 = 2'b0; - default: _theResult___snd__h2567 = 2'b11; - endcase - end - always@(byte_addr__h2405 or rdata___1__h2562 or crg_timecmp or crg_time) - begin - case (byte_addr__h2405) - 64'h0: _theResult___fst__h2566 = rdata___1__h2562; - 64'h0000000000000004: _theResult___fst__h2566 = 64'd0; - 64'h0000000000004000, 64'h0000000000004004: - _theResult___fst__h2566 = crg_timecmp; - 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___fst__h2566 = crg_time; - default: _theResult___fst__h2566 = 64'd0; - endcase - end - always@(byte_addr__h3353) - begin - case (byte_addr__h3353) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - v__h3517 = 2'b0; - default: v__h3517 = 2'b11; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10065 = $stime; - #0; - end - v__h10059 = v__h10065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x", - v__h10059, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10197 = $stime; - #0; - end - v__h10191 = v__h10197 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x", - v__h10191, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1852 = $stime; - #0; - end - v__h1846 = v__h1852 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1846); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2269 = $stime; - #0; - end - v__h2263 = v__h2269 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", - v__h2263, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - begin - v__h2453 = $stime; - #0; - end - v__h2447 = v__h2453 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2447); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - begin - v__h2640 = $stime; - #0; - end - v__h2634 = v__h2640 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2634); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2878 = $stime; - #0; - end - v__h2872 = v__h2878 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2872); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", x__h2751); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rresp__h2548); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2095 = $stime; - #0; - end - v__h2089 = v__h2095 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h2089, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h3161 = $stime; - #0; - end - v__h3155 = v__h3161 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", - v__h3155, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - begin - v__h3391 = $stime; - #0; - end - v__h3385 = v__h3391 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h3385); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - begin - v__h8927 = $stime; - #0; - end - v__h8921 = v__h8927 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h8921); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h9148 = $stime; - #0; - end - v__h9142 = v__h9148 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9142); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", v__h3357); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h9475 = $stime; - #0; - end - v__h9469 = v__h9475 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9469, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h9585 = $stime; - #0; - end - v__h9579 = v__h9585 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9579, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h9692 = $stime; - #0; - end - v__h9686 = v__h9692 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9686, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO_AXI4 - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v deleted file mode 100644 index f74de61e..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkPLIC_16_2_7.v +++ /dev/null @@ -1,26991 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_show_PLIC_state O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// v_targets_0_m_eip O 1 -// v_targets_1_m_eip O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// v_sources_0_m_interrupt_req_set_not_clear I 1 -// v_sources_1_m_interrupt_req_set_not_clear I 1 -// v_sources_2_m_interrupt_req_set_not_clear I 1 -// v_sources_3_m_interrupt_req_set_not_clear I 1 -// v_sources_4_m_interrupt_req_set_not_clear I 1 -// v_sources_5_m_interrupt_req_set_not_clear I 1 -// v_sources_6_m_interrupt_req_set_not_clear I 1 -// v_sources_7_m_interrupt_req_set_not_clear I 1 -// v_sources_8_m_interrupt_req_set_not_clear I 1 -// v_sources_9_m_interrupt_req_set_not_clear I 1 -// v_sources_10_m_interrupt_req_set_not_clear I 1 -// v_sources_11_m_interrupt_req_set_not_clear I 1 -// v_sources_12_m_interrupt_req_set_not_clear I 1 -// v_sources_13_m_interrupt_req_set_not_clear I 1 -// v_sources_14_m_interrupt_req_set_not_clear I 1 -// v_sources_15_m_interrupt_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_show_PLIC_state I 1 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkPLIC_16_2_7(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_show_PLIC_state, - RDY_show_PLIC_state, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - v_sources_0_m_interrupt_req_set_not_clear, - - v_sources_1_m_interrupt_req_set_not_clear, - - v_sources_2_m_interrupt_req_set_not_clear, - - v_sources_3_m_interrupt_req_set_not_clear, - - v_sources_4_m_interrupt_req_set_not_clear, - - v_sources_5_m_interrupt_req_set_not_clear, - - v_sources_6_m_interrupt_req_set_not_clear, - - v_sources_7_m_interrupt_req_set_not_clear, - - v_sources_8_m_interrupt_req_set_not_clear, - - v_sources_9_m_interrupt_req_set_not_clear, - - v_sources_10_m_interrupt_req_set_not_clear, - - v_sources_11_m_interrupt_req_set_not_clear, - - v_sources_12_m_interrupt_req_set_not_clear, - - v_sources_13_m_interrupt_req_set_not_clear, - - v_sources_14_m_interrupt_req_set_not_clear, - - v_sources_15_m_interrupt_req_set_not_clear, - - v_targets_0_m_eip, - - v_targets_1_m_eip); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method show_PLIC_state - input EN_show_PLIC_state; - output RDY_show_PLIC_state; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // action method v_sources_0_m_interrupt_req - input v_sources_0_m_interrupt_req_set_not_clear; - - // action method v_sources_1_m_interrupt_req - input v_sources_1_m_interrupt_req_set_not_clear; - - // action method v_sources_2_m_interrupt_req - input v_sources_2_m_interrupt_req_set_not_clear; - - // action method v_sources_3_m_interrupt_req - input v_sources_3_m_interrupt_req_set_not_clear; - - // action method v_sources_4_m_interrupt_req - input v_sources_4_m_interrupt_req_set_not_clear; - - // action method v_sources_5_m_interrupt_req - input v_sources_5_m_interrupt_req_set_not_clear; - - // action method v_sources_6_m_interrupt_req - input v_sources_6_m_interrupt_req_set_not_clear; - - // action method v_sources_7_m_interrupt_req - input v_sources_7_m_interrupt_req_set_not_clear; - - // action method v_sources_8_m_interrupt_req - input v_sources_8_m_interrupt_req_set_not_clear; - - // action method v_sources_9_m_interrupt_req - input v_sources_9_m_interrupt_req_set_not_clear; - - // action method v_sources_10_m_interrupt_req - input v_sources_10_m_interrupt_req_set_not_clear; - - // action method v_sources_11_m_interrupt_req - input v_sources_11_m_interrupt_req_set_not_clear; - - // action method v_sources_12_m_interrupt_req - input v_sources_12_m_interrupt_req_set_not_clear; - - // action method v_sources_13_m_interrupt_req - input v_sources_13_m_interrupt_req_set_not_clear; - - // action method v_sources_14_m_interrupt_req - input v_sources_14_m_interrupt_req_set_not_clear; - - // action method v_sources_15_m_interrupt_req - input v_sources_15_m_interrupt_req_set_not_clear; - - // value method v_targets_0_m_eip - output v_targets_0_m_eip; - - // value method v_targets_1_m_eip - output v_targets_1_m_eip; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_verbosity, - RDY_show_PLIC_state, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - v_targets_0_m_eip, - v_targets_1_m_eip; - - // register m_cfg_verbosity - reg [3 : 0] m_cfg_verbosity; - wire [3 : 0] m_cfg_verbosity$D_IN; - wire m_cfg_verbosity$EN; - - // register m_rg_addr_base - reg [63 : 0] m_rg_addr_base; - wire [63 : 0] m_rg_addr_base$D_IN; - wire m_rg_addr_base$EN; - - // register m_rg_addr_lim - reg [63 : 0] m_rg_addr_lim; - wire [63 : 0] m_rg_addr_lim$D_IN; - wire m_rg_addr_lim$EN; - - // register m_vrg_servicing_source_0 - reg [4 : 0] m_vrg_servicing_source_0; - wire [4 : 0] m_vrg_servicing_source_0$D_IN; - wire m_vrg_servicing_source_0$EN; - - // register m_vrg_servicing_source_1 - reg [4 : 0] m_vrg_servicing_source_1; - wire [4 : 0] m_vrg_servicing_source_1$D_IN; - wire m_vrg_servicing_source_1$EN; - - // register m_vrg_source_busy_0 - reg m_vrg_source_busy_0; - wire m_vrg_source_busy_0$D_IN, m_vrg_source_busy_0$EN; - - // register m_vrg_source_busy_1 - reg m_vrg_source_busy_1; - wire m_vrg_source_busy_1$D_IN, m_vrg_source_busy_1$EN; - - // register m_vrg_source_busy_10 - reg m_vrg_source_busy_10; - wire m_vrg_source_busy_10$D_IN, m_vrg_source_busy_10$EN; - - // register m_vrg_source_busy_11 - reg m_vrg_source_busy_11; - wire m_vrg_source_busy_11$D_IN, m_vrg_source_busy_11$EN; - - // register m_vrg_source_busy_12 - reg m_vrg_source_busy_12; - wire m_vrg_source_busy_12$D_IN, m_vrg_source_busy_12$EN; - - // register m_vrg_source_busy_13 - reg m_vrg_source_busy_13; - wire m_vrg_source_busy_13$D_IN, m_vrg_source_busy_13$EN; - - // register m_vrg_source_busy_14 - reg m_vrg_source_busy_14; - wire m_vrg_source_busy_14$D_IN, m_vrg_source_busy_14$EN; - - // register m_vrg_source_busy_15 - reg m_vrg_source_busy_15; - wire m_vrg_source_busy_15$D_IN, m_vrg_source_busy_15$EN; - - // register m_vrg_source_busy_16 - reg m_vrg_source_busy_16; - wire m_vrg_source_busy_16$D_IN, m_vrg_source_busy_16$EN; - - // register m_vrg_source_busy_2 - reg m_vrg_source_busy_2; - wire m_vrg_source_busy_2$D_IN, m_vrg_source_busy_2$EN; - - // register m_vrg_source_busy_3 - reg m_vrg_source_busy_3; - wire m_vrg_source_busy_3$D_IN, m_vrg_source_busy_3$EN; - - // register m_vrg_source_busy_4 - reg m_vrg_source_busy_4; - wire m_vrg_source_busy_4$D_IN, m_vrg_source_busy_4$EN; - - // register m_vrg_source_busy_5 - reg m_vrg_source_busy_5; - wire m_vrg_source_busy_5$D_IN, m_vrg_source_busy_5$EN; - - // register m_vrg_source_busy_6 - reg m_vrg_source_busy_6; - wire m_vrg_source_busy_6$D_IN, m_vrg_source_busy_6$EN; - - // register m_vrg_source_busy_7 - reg m_vrg_source_busy_7; - wire m_vrg_source_busy_7$D_IN, m_vrg_source_busy_7$EN; - - // register m_vrg_source_busy_8 - reg m_vrg_source_busy_8; - wire m_vrg_source_busy_8$D_IN, m_vrg_source_busy_8$EN; - - // register m_vrg_source_busy_9 - reg m_vrg_source_busy_9; - wire m_vrg_source_busy_9$D_IN, m_vrg_source_busy_9$EN; - - // register m_vrg_source_ip_0 - reg m_vrg_source_ip_0; - wire m_vrg_source_ip_0$D_IN, m_vrg_source_ip_0$EN; - - // register m_vrg_source_ip_1 - reg m_vrg_source_ip_1; - wire m_vrg_source_ip_1$D_IN, m_vrg_source_ip_1$EN; - - // register m_vrg_source_ip_10 - reg m_vrg_source_ip_10; - wire m_vrg_source_ip_10$D_IN, m_vrg_source_ip_10$EN; - - // register m_vrg_source_ip_11 - reg m_vrg_source_ip_11; - wire m_vrg_source_ip_11$D_IN, m_vrg_source_ip_11$EN; - - // register m_vrg_source_ip_12 - reg m_vrg_source_ip_12; - wire m_vrg_source_ip_12$D_IN, m_vrg_source_ip_12$EN; - - // register m_vrg_source_ip_13 - reg m_vrg_source_ip_13; - wire m_vrg_source_ip_13$D_IN, m_vrg_source_ip_13$EN; - - // register m_vrg_source_ip_14 - reg m_vrg_source_ip_14; - wire m_vrg_source_ip_14$D_IN, m_vrg_source_ip_14$EN; - - // register m_vrg_source_ip_15 - reg m_vrg_source_ip_15; - wire m_vrg_source_ip_15$D_IN, m_vrg_source_ip_15$EN; - - // register m_vrg_source_ip_16 - reg m_vrg_source_ip_16; - wire m_vrg_source_ip_16$D_IN, m_vrg_source_ip_16$EN; - - // register m_vrg_source_ip_2 - reg m_vrg_source_ip_2; - wire m_vrg_source_ip_2$D_IN, m_vrg_source_ip_2$EN; - - // register m_vrg_source_ip_3 - reg m_vrg_source_ip_3; - wire m_vrg_source_ip_3$D_IN, m_vrg_source_ip_3$EN; - - // register m_vrg_source_ip_4 - reg m_vrg_source_ip_4; - wire m_vrg_source_ip_4$D_IN, m_vrg_source_ip_4$EN; - - // register m_vrg_source_ip_5 - reg m_vrg_source_ip_5; - wire m_vrg_source_ip_5$D_IN, m_vrg_source_ip_5$EN; - - // register m_vrg_source_ip_6 - reg m_vrg_source_ip_6; - wire m_vrg_source_ip_6$D_IN, m_vrg_source_ip_6$EN; - - // register m_vrg_source_ip_7 - reg m_vrg_source_ip_7; - wire m_vrg_source_ip_7$D_IN, m_vrg_source_ip_7$EN; - - // register m_vrg_source_ip_8 - reg m_vrg_source_ip_8; - wire m_vrg_source_ip_8$D_IN, m_vrg_source_ip_8$EN; - - // register m_vrg_source_ip_9 - reg m_vrg_source_ip_9; - wire m_vrg_source_ip_9$D_IN, m_vrg_source_ip_9$EN; - - // register m_vrg_source_prio_0 - reg [2 : 0] m_vrg_source_prio_0; - wire [2 : 0] m_vrg_source_prio_0$D_IN; - wire m_vrg_source_prio_0$EN; - - // register m_vrg_source_prio_1 - reg [2 : 0] m_vrg_source_prio_1; - wire [2 : 0] m_vrg_source_prio_1$D_IN; - wire m_vrg_source_prio_1$EN; - - // register m_vrg_source_prio_10 - reg [2 : 0] m_vrg_source_prio_10; - wire [2 : 0] m_vrg_source_prio_10$D_IN; - wire m_vrg_source_prio_10$EN; - - // register m_vrg_source_prio_11 - reg [2 : 0] m_vrg_source_prio_11; - wire [2 : 0] m_vrg_source_prio_11$D_IN; - wire m_vrg_source_prio_11$EN; - - // register m_vrg_source_prio_12 - reg [2 : 0] m_vrg_source_prio_12; - wire [2 : 0] m_vrg_source_prio_12$D_IN; - wire m_vrg_source_prio_12$EN; - - // register m_vrg_source_prio_13 - reg [2 : 0] m_vrg_source_prio_13; - wire [2 : 0] m_vrg_source_prio_13$D_IN; - wire m_vrg_source_prio_13$EN; - - // register m_vrg_source_prio_14 - reg [2 : 0] m_vrg_source_prio_14; - wire [2 : 0] m_vrg_source_prio_14$D_IN; - wire m_vrg_source_prio_14$EN; - - // register m_vrg_source_prio_15 - reg [2 : 0] m_vrg_source_prio_15; - wire [2 : 0] m_vrg_source_prio_15$D_IN; - wire m_vrg_source_prio_15$EN; - - // register m_vrg_source_prio_16 - reg [2 : 0] m_vrg_source_prio_16; - wire [2 : 0] m_vrg_source_prio_16$D_IN; - wire m_vrg_source_prio_16$EN; - - // register m_vrg_source_prio_2 - reg [2 : 0] m_vrg_source_prio_2; - wire [2 : 0] m_vrg_source_prio_2$D_IN; - wire m_vrg_source_prio_2$EN; - - // register m_vrg_source_prio_3 - reg [2 : 0] m_vrg_source_prio_3; - wire [2 : 0] m_vrg_source_prio_3$D_IN; - wire m_vrg_source_prio_3$EN; - - // register m_vrg_source_prio_4 - reg [2 : 0] m_vrg_source_prio_4; - wire [2 : 0] m_vrg_source_prio_4$D_IN; - wire m_vrg_source_prio_4$EN; - - // register m_vrg_source_prio_5 - reg [2 : 0] m_vrg_source_prio_5; - wire [2 : 0] m_vrg_source_prio_5$D_IN; - wire m_vrg_source_prio_5$EN; - - // register m_vrg_source_prio_6 - reg [2 : 0] m_vrg_source_prio_6; - wire [2 : 0] m_vrg_source_prio_6$D_IN; - wire m_vrg_source_prio_6$EN; - - // register m_vrg_source_prio_7 - reg [2 : 0] m_vrg_source_prio_7; - wire [2 : 0] m_vrg_source_prio_7$D_IN; - wire m_vrg_source_prio_7$EN; - - // register m_vrg_source_prio_8 - reg [2 : 0] m_vrg_source_prio_8; - wire [2 : 0] m_vrg_source_prio_8$D_IN; - wire m_vrg_source_prio_8$EN; - - // register m_vrg_source_prio_9 - reg [2 : 0] m_vrg_source_prio_9; - wire [2 : 0] m_vrg_source_prio_9$D_IN; - wire m_vrg_source_prio_9$EN; - - // register m_vrg_target_threshold_0 - reg [2 : 0] m_vrg_target_threshold_0; - wire [2 : 0] m_vrg_target_threshold_0$D_IN; - wire m_vrg_target_threshold_0$EN; - - // register m_vrg_target_threshold_1 - reg [2 : 0] m_vrg_target_threshold_1; - wire [2 : 0] m_vrg_target_threshold_1$D_IN; - wire m_vrg_target_threshold_1$EN; - - // register m_vvrg_ie_0_0 - reg m_vvrg_ie_0_0; - wire m_vvrg_ie_0_0$D_IN, m_vvrg_ie_0_0$EN; - - // register m_vvrg_ie_0_1 - reg m_vvrg_ie_0_1; - wire m_vvrg_ie_0_1$D_IN, m_vvrg_ie_0_1$EN; - - // register m_vvrg_ie_0_10 - reg m_vvrg_ie_0_10; - wire m_vvrg_ie_0_10$D_IN, m_vvrg_ie_0_10$EN; - - // register m_vvrg_ie_0_11 - reg m_vvrg_ie_0_11; - wire m_vvrg_ie_0_11$D_IN, m_vvrg_ie_0_11$EN; - - // register m_vvrg_ie_0_12 - reg m_vvrg_ie_0_12; - wire m_vvrg_ie_0_12$D_IN, m_vvrg_ie_0_12$EN; - - // register m_vvrg_ie_0_13 - reg m_vvrg_ie_0_13; - wire m_vvrg_ie_0_13$D_IN, m_vvrg_ie_0_13$EN; - - // register m_vvrg_ie_0_14 - reg m_vvrg_ie_0_14; - wire m_vvrg_ie_0_14$D_IN, m_vvrg_ie_0_14$EN; - - // register m_vvrg_ie_0_15 - reg m_vvrg_ie_0_15; - wire m_vvrg_ie_0_15$D_IN, m_vvrg_ie_0_15$EN; - - // register m_vvrg_ie_0_16 - reg m_vvrg_ie_0_16; - wire m_vvrg_ie_0_16$D_IN, m_vvrg_ie_0_16$EN; - - // register m_vvrg_ie_0_2 - reg m_vvrg_ie_0_2; - wire m_vvrg_ie_0_2$D_IN, m_vvrg_ie_0_2$EN; - - // register m_vvrg_ie_0_3 - reg m_vvrg_ie_0_3; - wire m_vvrg_ie_0_3$D_IN, m_vvrg_ie_0_3$EN; - - // register m_vvrg_ie_0_4 - reg m_vvrg_ie_0_4; - wire m_vvrg_ie_0_4$D_IN, m_vvrg_ie_0_4$EN; - - // register m_vvrg_ie_0_5 - reg m_vvrg_ie_0_5; - wire m_vvrg_ie_0_5$D_IN, m_vvrg_ie_0_5$EN; - - // register m_vvrg_ie_0_6 - reg m_vvrg_ie_0_6; - wire m_vvrg_ie_0_6$D_IN, m_vvrg_ie_0_6$EN; - - // register m_vvrg_ie_0_7 - reg m_vvrg_ie_0_7; - wire m_vvrg_ie_0_7$D_IN, m_vvrg_ie_0_7$EN; - - // register m_vvrg_ie_0_8 - reg m_vvrg_ie_0_8; - wire m_vvrg_ie_0_8$D_IN, m_vvrg_ie_0_8$EN; - - // register m_vvrg_ie_0_9 - reg m_vvrg_ie_0_9; - wire m_vvrg_ie_0_9$D_IN, m_vvrg_ie_0_9$EN; - - // register m_vvrg_ie_1_0 - reg m_vvrg_ie_1_0; - wire m_vvrg_ie_1_0$D_IN, m_vvrg_ie_1_0$EN; - - // register m_vvrg_ie_1_1 - reg m_vvrg_ie_1_1; - wire m_vvrg_ie_1_1$D_IN, m_vvrg_ie_1_1$EN; - - // register m_vvrg_ie_1_10 - reg m_vvrg_ie_1_10; - wire m_vvrg_ie_1_10$D_IN, m_vvrg_ie_1_10$EN; - - // register m_vvrg_ie_1_11 - reg m_vvrg_ie_1_11; - wire m_vvrg_ie_1_11$D_IN, m_vvrg_ie_1_11$EN; - - // register m_vvrg_ie_1_12 - reg m_vvrg_ie_1_12; - wire m_vvrg_ie_1_12$D_IN, m_vvrg_ie_1_12$EN; - - // register m_vvrg_ie_1_13 - reg m_vvrg_ie_1_13; - wire m_vvrg_ie_1_13$D_IN, m_vvrg_ie_1_13$EN; - - // register m_vvrg_ie_1_14 - reg m_vvrg_ie_1_14; - wire m_vvrg_ie_1_14$D_IN, m_vvrg_ie_1_14$EN; - - // register m_vvrg_ie_1_15 - reg m_vvrg_ie_1_15; - wire m_vvrg_ie_1_15$D_IN, m_vvrg_ie_1_15$EN; - - // register m_vvrg_ie_1_16 - reg m_vvrg_ie_1_16; - wire m_vvrg_ie_1_16$D_IN, m_vvrg_ie_1_16$EN; - - // register m_vvrg_ie_1_2 - reg m_vvrg_ie_1_2; - wire m_vvrg_ie_1_2$D_IN, m_vvrg_ie_1_2$EN; - - // register m_vvrg_ie_1_3 - reg m_vvrg_ie_1_3; - wire m_vvrg_ie_1_3$D_IN, m_vvrg_ie_1_3$EN; - - // register m_vvrg_ie_1_4 - reg m_vvrg_ie_1_4; - wire m_vvrg_ie_1_4$D_IN, m_vvrg_ie_1_4$EN; - - // register m_vvrg_ie_1_5 - reg m_vvrg_ie_1_5; - wire m_vvrg_ie_1_5$D_IN, m_vvrg_ie_1_5$EN; - - // register m_vvrg_ie_1_6 - reg m_vvrg_ie_1_6; - wire m_vvrg_ie_1_6$D_IN, m_vvrg_ie_1_6$EN; - - // register m_vvrg_ie_1_7 - reg m_vvrg_ie_1_7; - wire m_vvrg_ie_1_7$D_IN, m_vvrg_ie_1_7$EN; - - // register m_vvrg_ie_1_8 - reg m_vvrg_ie_1_8; - wire m_vvrg_ie_1_8$D_IN, m_vvrg_ie_1_8$EN; - - // register m_vvrg_ie_1_9 - reg m_vvrg_ie_1_9; - wire m_vvrg_ie_1_9$D_IN, m_vvrg_ie_1_9$EN; - - // ports of submodule m_f_reset_reqs - wire m_f_reset_reqs$CLR, - m_f_reset_reqs$DEQ, - m_f_reset_reqs$EMPTY_N, - m_f_reset_reqs$ENQ, - m_f_reset_reqs$FULL_N; - - // ports of submodule m_f_reset_rsps - wire m_f_reset_rsps$CLR, - m_f_reset_rsps$DEQ, - m_f_reset_rsps$EMPTY_N, - m_f_reset_rsps$ENQ, - m_f_reset_rsps$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_addr - wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT; - wire m_slave_xactor_f_rd_addr$CLR, - m_slave_xactor_f_rd_addr$DEQ, - m_slave_xactor_f_rd_addr$EMPTY_N, - m_slave_xactor_f_rd_addr$ENQ, - m_slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_data - wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT; - wire m_slave_xactor_f_rd_data$CLR, - m_slave_xactor_f_rd_data$DEQ, - m_slave_xactor_f_rd_data$EMPTY_N, - m_slave_xactor_f_rd_data$ENQ, - m_slave_xactor_f_rd_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_addr - wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT; - wire m_slave_xactor_f_wr_addr$CLR, - m_slave_xactor_f_wr_addr$DEQ, - m_slave_xactor_f_wr_addr$EMPTY_N, - m_slave_xactor_f_wr_addr$ENQ, - m_slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; - wire m_slave_xactor_f_wr_data$CLR, - m_slave_xactor_f_wr_data$DEQ, - m_slave_xactor_f_wr_data$EMPTY_N, - m_slave_xactor_f_wr_data$ENQ, - m_slave_xactor_f_wr_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_resp - wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT; - wire m_slave_xactor_f_wr_resp$CLR, - m_slave_xactor_f_wr_resp$DEQ, - m_slave_xactor_f_wr_resp$EMPTY_N, - m_slave_xactor_f_wr_resp$ENQ, - m_slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_process_rd_req, - CAN_FIRE_RL_m_rl_process_wr_req, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_verbosity, - CAN_FIRE_show_PLIC_state, - CAN_FIRE_v_sources_0_m_interrupt_req, - CAN_FIRE_v_sources_10_m_interrupt_req, - CAN_FIRE_v_sources_11_m_interrupt_req, - CAN_FIRE_v_sources_12_m_interrupt_req, - CAN_FIRE_v_sources_13_m_interrupt_req, - CAN_FIRE_v_sources_14_m_interrupt_req, - CAN_FIRE_v_sources_15_m_interrupt_req, - CAN_FIRE_v_sources_1_m_interrupt_req, - CAN_FIRE_v_sources_2_m_interrupt_req, - CAN_FIRE_v_sources_3_m_interrupt_req, - CAN_FIRE_v_sources_4_m_interrupt_req, - CAN_FIRE_v_sources_5_m_interrupt_req, - CAN_FIRE_v_sources_6_m_interrupt_req, - CAN_FIRE_v_sources_7_m_interrupt_req, - CAN_FIRE_v_sources_8_m_interrupt_req, - CAN_FIRE_v_sources_9_m_interrupt_req, - WILL_FIRE_RL_m_rl_process_rd_req, - WILL_FIRE_RL_m_rl_process_wr_req, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_verbosity, - WILL_FIRE_show_PLIC_state, - WILL_FIRE_v_sources_0_m_interrupt_req, - WILL_FIRE_v_sources_10_m_interrupt_req, - WILL_FIRE_v_sources_11_m_interrupt_req, - WILL_FIRE_v_sources_12_m_interrupt_req, - WILL_FIRE_v_sources_13_m_interrupt_req, - WILL_FIRE_v_sources_14_m_interrupt_req, - WILL_FIRE_v_sources_15_m_interrupt_req, - WILL_FIRE_v_sources_1_m_interrupt_req, - WILL_FIRE_v_sources_2_m_interrupt_req, - WILL_FIRE_v_sources_3_m_interrupt_req, - WILL_FIRE_v_sources_4_m_interrupt_req, - WILL_FIRE_v_sources_5_m_interrupt_req, - WILL_FIRE_v_sources_6_m_interrupt_req, - WILL_FIRE_v_sources_7_m_interrupt_req, - WILL_FIRE_v_sources_8_m_interrupt_req, - WILL_FIRE_v_sources_9_m_interrupt_req; - - // inputs to muxes for submodule ports - wire MUX_m_vrg_servicing_source_0$write_1__SEL_1, - MUX_m_vrg_servicing_source_1$write_1__SEL_1, - MUX_m_vrg_source_busy_0$write_1__SEL_2, - MUX_m_vrg_source_busy_1$write_1__SEL_1, - MUX_m_vrg_source_busy_1$write_1__SEL_2, - MUX_m_vrg_source_busy_10$write_1__SEL_1, - MUX_m_vrg_source_busy_10$write_1__SEL_2, - MUX_m_vrg_source_busy_11$write_1__SEL_1, - MUX_m_vrg_source_busy_11$write_1__SEL_2, - MUX_m_vrg_source_busy_12$write_1__SEL_1, - MUX_m_vrg_source_busy_12$write_1__SEL_2, - MUX_m_vrg_source_busy_13$write_1__SEL_1, - MUX_m_vrg_source_busy_13$write_1__SEL_2, - MUX_m_vrg_source_busy_14$write_1__SEL_1, - MUX_m_vrg_source_busy_14$write_1__SEL_2, - MUX_m_vrg_source_busy_15$write_1__SEL_1, - MUX_m_vrg_source_busy_15$write_1__SEL_2, - MUX_m_vrg_source_busy_16$write_1__SEL_1, - MUX_m_vrg_source_busy_16$write_1__SEL_2, - MUX_m_vrg_source_busy_2$write_1__SEL_1, - MUX_m_vrg_source_busy_2$write_1__SEL_2, - MUX_m_vrg_source_busy_3$write_1__SEL_1, - MUX_m_vrg_source_busy_3$write_1__SEL_2, - MUX_m_vrg_source_busy_4$write_1__SEL_1, - MUX_m_vrg_source_busy_4$write_1__SEL_2, - MUX_m_vrg_source_busy_5$write_1__SEL_1, - MUX_m_vrg_source_busy_5$write_1__SEL_2, - MUX_m_vrg_source_busy_6$write_1__SEL_1, - MUX_m_vrg_source_busy_6$write_1__SEL_2, - MUX_m_vrg_source_busy_7$write_1__SEL_1, - MUX_m_vrg_source_busy_7$write_1__SEL_2, - MUX_m_vrg_source_busy_8$write_1__SEL_1, - MUX_m_vrg_source_busy_8$write_1__SEL_2, - MUX_m_vrg_source_busy_9$write_1__SEL_1, - MUX_m_vrg_source_busy_9$write_1__SEL_2, - MUX_m_vrg_source_prio_0$write_1__SEL_1, - MUX_m_vrg_source_prio_1$write_1__SEL_1, - MUX_m_vrg_source_prio_10$write_1__SEL_1, - MUX_m_vrg_source_prio_11$write_1__SEL_1, - MUX_m_vrg_source_prio_12$write_1__SEL_1, - MUX_m_vrg_source_prio_13$write_1__SEL_1, - MUX_m_vrg_source_prio_14$write_1__SEL_1, - MUX_m_vrg_source_prio_15$write_1__SEL_1, - MUX_m_vrg_source_prio_16$write_1__SEL_1, - MUX_m_vrg_source_prio_2$write_1__SEL_1, - MUX_m_vrg_source_prio_3$write_1__SEL_1, - MUX_m_vrg_source_prio_4$write_1__SEL_1, - MUX_m_vrg_source_prio_5$write_1__SEL_1, - MUX_m_vrg_source_prio_6$write_1__SEL_1, - MUX_m_vrg_source_prio_7$write_1__SEL_1, - MUX_m_vrg_source_prio_8$write_1__SEL_1, - MUX_m_vrg_source_prio_9$write_1__SEL_1, - MUX_m_vrg_target_threshold_0$write_1__SEL_1, - MUX_m_vrg_target_threshold_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__VAL_1, - MUX_m_vvrg_ie_0_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_1$write_1__VAL_1, - MUX_m_vvrg_ie_0_10$write_1__SEL_1, - MUX_m_vvrg_ie_0_10$write_1__VAL_1, - MUX_m_vvrg_ie_0_11$write_1__SEL_1, - MUX_m_vvrg_ie_0_11$write_1__VAL_1, - MUX_m_vvrg_ie_0_12$write_1__SEL_1, - MUX_m_vvrg_ie_0_12$write_1__VAL_1, - MUX_m_vvrg_ie_0_13$write_1__SEL_1, - MUX_m_vvrg_ie_0_13$write_1__VAL_1, - MUX_m_vvrg_ie_0_14$write_1__SEL_1, - MUX_m_vvrg_ie_0_14$write_1__VAL_1, - MUX_m_vvrg_ie_0_15$write_1__SEL_1, - MUX_m_vvrg_ie_0_15$write_1__VAL_1, - MUX_m_vvrg_ie_0_16$write_1__SEL_1, - MUX_m_vvrg_ie_0_16$write_1__VAL_1, - MUX_m_vvrg_ie_0_2$write_1__SEL_1, - MUX_m_vvrg_ie_0_2$write_1__VAL_1, - MUX_m_vvrg_ie_0_3$write_1__SEL_1, - MUX_m_vvrg_ie_0_3$write_1__VAL_1, - MUX_m_vvrg_ie_0_4$write_1__SEL_1, - MUX_m_vvrg_ie_0_4$write_1__VAL_1, - MUX_m_vvrg_ie_0_5$write_1__SEL_1, - MUX_m_vvrg_ie_0_5$write_1__VAL_1, - MUX_m_vvrg_ie_0_6$write_1__SEL_1, - MUX_m_vvrg_ie_0_6$write_1__VAL_1, - MUX_m_vvrg_ie_0_7$write_1__SEL_1, - MUX_m_vvrg_ie_0_7$write_1__VAL_1, - MUX_m_vvrg_ie_0_8$write_1__SEL_1, - MUX_m_vvrg_ie_0_8$write_1__VAL_1, - MUX_m_vvrg_ie_0_9$write_1__SEL_1, - MUX_m_vvrg_ie_0_9$write_1__VAL_1, - MUX_m_vvrg_ie_1_0$write_1__SEL_1, - MUX_m_vvrg_ie_1_0$write_1__VAL_1, - MUX_m_vvrg_ie_1_1$write_1__SEL_1, - MUX_m_vvrg_ie_1_1$write_1__VAL_1, - MUX_m_vvrg_ie_1_10$write_1__SEL_1, - MUX_m_vvrg_ie_1_10$write_1__VAL_1, - MUX_m_vvrg_ie_1_11$write_1__SEL_1, - MUX_m_vvrg_ie_1_11$write_1__VAL_1, - MUX_m_vvrg_ie_1_12$write_1__SEL_1, - MUX_m_vvrg_ie_1_12$write_1__VAL_1, - MUX_m_vvrg_ie_1_13$write_1__SEL_1, - MUX_m_vvrg_ie_1_13$write_1__VAL_1, - MUX_m_vvrg_ie_1_14$write_1__SEL_1, - MUX_m_vvrg_ie_1_14$write_1__VAL_1, - MUX_m_vvrg_ie_1_15$write_1__SEL_1, - MUX_m_vvrg_ie_1_15$write_1__VAL_1, - MUX_m_vvrg_ie_1_16$write_1__SEL_1, - MUX_m_vvrg_ie_1_16$write_1__VAL_1, - MUX_m_vvrg_ie_1_2$write_1__SEL_1, - MUX_m_vvrg_ie_1_2$write_1__VAL_1, - MUX_m_vvrg_ie_1_3$write_1__SEL_1, - MUX_m_vvrg_ie_1_3$write_1__VAL_1, - MUX_m_vvrg_ie_1_4$write_1__SEL_1, - MUX_m_vvrg_ie_1_4$write_1__VAL_1, - MUX_m_vvrg_ie_1_5$write_1__SEL_1, - MUX_m_vvrg_ie_1_5$write_1__VAL_1, - MUX_m_vvrg_ie_1_6$write_1__SEL_1, - MUX_m_vvrg_ie_1_6$write_1__VAL_1, - MUX_m_vvrg_ie_1_7$write_1__SEL_1, - MUX_m_vvrg_ie_1_7$write_1__VAL_1, - MUX_m_vvrg_ie_1_8$write_1__SEL_1, - MUX_m_vvrg_ie_1_8$write_1__VAL_1, - MUX_m_vvrg_ie_1_9$write_1__SEL_1, - MUX_m_vvrg_ie_1_9$write_1__VAL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h75676; - reg [31 : 0] v__h75874; - reg [31 : 0] v__h76072; - reg [31 : 0] v__h76270; - reg [31 : 0] v__h76468; - reg [31 : 0] v__h76666; - reg [31 : 0] v__h76864; - reg [31 : 0] v__h77062; - reg [31 : 0] v__h77260; - reg [31 : 0] v__h77458; - reg [31 : 0] v__h77656; - reg [31 : 0] v__h77854; - reg [31 : 0] v__h78052; - reg [31 : 0] v__h78250; - reg [31 : 0] v__h78448; - reg [31 : 0] v__h78646; - reg [31 : 0] v__h6144; - reg [31 : 0] v__h13080; - reg [31 : 0] v__h13265; - reg [31 : 0] v__h13463; - reg [31 : 0] v__h13713; - reg [31 : 0] v__h18186; - reg [31 : 0] v__h23802; - reg [31 : 0] v__h25975; - reg [31 : 0] v__h24056; - reg [31 : 0] v__h26250; - reg [31 : 0] v__h26463; - reg [31 : 0] v__h26740; - reg [31 : 0] v__h26968; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h28048; - reg [31 : 0] v__h67030; - reg [31 : 0] v__h67318; - reg [31 : 0] v__h67847; - reg [31 : 0] v__h67933; - reg [31 : 0] v__h68132; - reg [31 : 0] v__h68353; - reg [31 : 0] v__h74690; - reg [31 : 0] v__h74800; - reg [31 : 0] v__h74913; - reg [31 : 0] v__h6138; - reg [31 : 0] v__h13074; - reg [31 : 0] v__h13259; - reg [31 : 0] v__h13457; - reg [31 : 0] v__h13707; - reg [31 : 0] v__h18180; - reg [31 : 0] v__h23796; - reg [31 : 0] v__h24050; - reg [31 : 0] v__h25969; - reg [31 : 0] v__h26244; - reg [31 : 0] v__h26457; - reg [31 : 0] v__h26734; - reg [31 : 0] v__h26962; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28042; - reg [31 : 0] v__h67024; - reg [31 : 0] v__h67312; - reg [31 : 0] v__h67841; - reg [31 : 0] v__h67927; - reg [31 : 0] v__h68126; - reg [31 : 0] v__h68347; - reg [31 : 0] v__h74684; - reg [31 : 0] v__h74794; - reg [31 : 0] v__h74907; - reg [31 : 0] v__h75670; - reg [31 : 0] v__h75868; - reg [31 : 0] v__h76066; - reg [31 : 0] v__h76264; - reg [31 : 0] v__h76462; - reg [31 : 0] v__h76660; - reg [31 : 0] v__h76858; - reg [31 : 0] v__h77056; - reg [31 : 0] v__h77254; - reg [31 : 0] v__h77452; - reg [31 : 0] v__h77650; - reg [31 : 0] v__h77848; - reg [31 : 0] v__h78046; - reg [31 : 0] v__h78244; - reg [31 : 0] v__h78442; - reg [31 : 0] v__h78640; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] y_avValue_fst__h26148; - reg [4 : 0] x__h24011, x__h67487; - reg [2 : 0] x__h13493, x__h23832; - reg [1 : 0] v__h67107, y_avValue_snd__h26149; - reg CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - wire [63 : 0] addr_offset__h13216, - addr_offset__h26929, - rdata___1__h26404, - rdata__h26202, - v__h13422, - v__h13671, - v__h18144, - v__h23761, - v__h25455, - v__h25474, - x__h26361, - y_avValue_fst__h26094, - y_avValue_fst__h26115, - y_avValue_fst__h26127, - y_avValue_fst__h26143, - y_avValue_fst__h26159, - y_avValue_fst__h26164, - y_avValue_fst__h26175, - y_avValue_fst__h26180, - y_avValue_fst__h26194; - wire [31 : 0] v_ie__h18147, - v_ip__h13674, - wdata32__h26930, - x__h23673, - x__h67110; - wire [9 : 0] source_id__h15665, - source_id__h15772, - source_id__h15845, - source_id__h15918, - source_id__h15991, - source_id__h16064, - source_id__h16137, - source_id__h16210, - source_id__h16283, - source_id__h16356, - source_id__h16429, - source_id__h16502, - source_id__h16575, - source_id__h16648, - source_id__h16721, - source_id__h16794, - source_id__h16867, - source_id__h16940, - source_id__h17013, - source_id__h17086, - source_id__h17159, - source_id__h17232, - source_id__h17305, - source_id__h17378, - source_id__h17451, - source_id__h17524, - source_id__h17597, - source_id__h17670, - source_id__h17743, - source_id__h17816, - source_id__h17889, - source_id__h20137, - source_id__h20313, - source_id__h20421, - source_id__h20529, - source_id__h20637, - source_id__h20745, - source_id__h20853, - source_id__h20961, - source_id__h21069, - source_id__h21177, - source_id__h21285, - source_id__h21393, - source_id__h21501, - source_id__h21609, - source_id__h21717, - source_id__h21825, - source_id__h21933, - source_id__h22041, - source_id__h22149, - source_id__h22257, - source_id__h22365, - source_id__h22473, - source_id__h22581, - source_id__h22689, - source_id__h22797, - source_id__h22905, - source_id__h23013, - source_id__h23121, - source_id__h23229, - source_id__h23337, - source_id__h23445, - source_id__h29475, - source_id__h30685, - source_id__h31895, - source_id__h33105, - source_id__h34315, - source_id__h35525, - source_id__h36735, - source_id__h37945, - source_id__h39155, - source_id__h40365, - source_id__h41575, - source_id__h42785, - source_id__h43995, - source_id__h45205, - source_id__h46415, - source_id__h47625, - source_id__h48835, - source_id__h50045, - source_id__h51255, - source_id__h52465, - source_id__h53675, - source_id__h54885, - source_id__h56095, - source_id__h57305, - source_id__h58515, - source_id__h59725, - source_id__h60935, - source_id__h62145, - source_id__h63355, - source_id__h64565, - source_id__h65775, - source_id__h67436, - source_id_base__h13630, - source_id_base__h28148; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71313, - b__h73318, - max_id__h23959; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71312, - a__h73317; - wire [1 : 0] rresp__h26203, - v__h26934, - v__h27094, - v__h27107, - v__h27942, - v__h27961, - v__h28125, - v__h28144, - v__h67144, - v__h67432, - v__h67476, - y_avValue_snd__h26095, - y_avValue_snd__h26116, - y_avValue_snd__h26128, - y_avValue_snd__h26144, - y_avValue_snd__h26160, - y_avValue_snd__h26165, - y_avValue_snd__h26176, - y_avValue_snd__h26181, - y_avValue_snd__h26195; - wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, - NOT_m_cfg_verbosity_read_ULE_1_5___d16, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982, - NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313, - NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321, - NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329, - NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337, - NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345, - NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353, - NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361, - NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242, - NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249, - NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257, - NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265, - NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273, - NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281, - NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289, - NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297, - NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305, - _dfoo1, - _dfoo10, - _dfoo100, - _dfoo1000, - _dfoo1001, - _dfoo1002, - _dfoo1003, - _dfoo1004, - _dfoo1005, - _dfoo1006, - _dfoo1007, - _dfoo1008, - _dfoo1009, - _dfoo1010, - _dfoo1011, - _dfoo1012, - _dfoo1013, - _dfoo1014, - _dfoo1015, - _dfoo1016, - _dfoo1017, - _dfoo1018, - _dfoo1019, - _dfoo102, - _dfoo1020, - _dfoo1022, - _dfoo1024, - _dfoo1026, - _dfoo1028, - _dfoo1030, - _dfoo1032, - _dfoo1034, - _dfoo1036, - _dfoo1038, - _dfoo104, - _dfoo1040, - _dfoo1042, - _dfoo1044, - _dfoo1046, - _dfoo1048, - _dfoo1050, - _dfoo1052, - _dfoo1054, - _dfoo1056, - _dfoo1058, - _dfoo106, - _dfoo1060, - _dfoo1062, - _dfoo1064, - _dfoo1066, - _dfoo1068, - _dfoo1070, - _dfoo1072, - _dfoo1074, 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_dfoo1154, - _dfoo1155, - _dfoo1156, - _dfoo1158, - _dfoo116, - _dfoo1160, - _dfoo1162, - _dfoo1164, - _dfoo1166, - _dfoo1168, - _dfoo1170, - _dfoo1172, - _dfoo1174, - _dfoo1176, - _dfoo1178, - _dfoo118, - _dfoo1180, - _dfoo1182, - _dfoo1184, - _dfoo1186, - _dfoo1188, - _dfoo1190, - _dfoo1192, - _dfoo1194, - _dfoo1196, - _dfoo1198, - _dfoo12, - _dfoo120, - _dfoo1200, - _dfoo1202, - _dfoo1204, - _dfoo1206, - _dfoo1208, - _dfoo1210, - _dfoo1212, - _dfoo1214, - _dfoo1216, - _dfoo1218, - _dfoo122, - _dfoo1220, - _dfoo1222, - _dfoo1224, - _dfoo1225, - _dfoo1226, - _dfoo1227, - _dfoo1228, - _dfoo1229, - _dfoo1230, - _dfoo1231, - _dfoo1232, - _dfoo1233, - _dfoo1234, - _dfoo1235, - _dfoo1236, - _dfoo1237, - _dfoo1238, - _dfoo1239, - _dfoo124, - _dfoo1240, - _dfoo1241, - _dfoo1242, - _dfoo1243, - _dfoo1244, - _dfoo1245, - _dfoo1246, - _dfoo1247, - _dfoo1248, - _dfoo1249, - _dfoo1250, - _dfoo1251, - _dfoo1252, - _dfoo1253, - _dfoo1254, - _dfoo1255, - _dfoo1256, - _dfoo1257, - _dfoo1258, - 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_dfoo1363, - _dfoo1364, - _dfoo1365, - _dfoo1366, - _dfoo1367, - _dfoo1368, - _dfoo1369, - _dfoo137, - _dfoo1370, - _dfoo1371, - _dfoo1372, - _dfoo1373, - _dfoo1374, - _dfoo1375, - _dfoo1376, - _dfoo1377, - _dfoo1378, - _dfoo1379, - _dfoo138, - _dfoo1380, - _dfoo1381, - _dfoo1382, - _dfoo1383, - _dfoo1384, - _dfoo1385, - _dfoo1386, - _dfoo1387, - _dfoo1388, - _dfoo1389, - _dfoo139, - _dfoo1390, - _dfoo1391, - _dfoo1392, - _dfoo1393, - _dfoo1394, - _dfoo1395, - _dfoo1396, - _dfoo1397, - _dfoo1398, - _dfoo1399, - _dfoo14, - _dfoo140, - _dfoo1400, - _dfoo1401, - _dfoo1402, - _dfoo1403, - _dfoo1404, - _dfoo1405, - _dfoo1406, - _dfoo1407, - _dfoo1408, - _dfoo1409, - _dfoo141, - _dfoo1410, - _dfoo1411, - _dfoo1412, - _dfoo1413, - _dfoo1414, - _dfoo1415, - _dfoo1416, - _dfoo1417, - _dfoo1418, - _dfoo1419, - _dfoo142, - _dfoo1420, - _dfoo1421, - _dfoo1422, - _dfoo1423, - _dfoo1424, - _dfoo1425, - _dfoo1426, - _dfoo1427, - _dfoo1428, - _dfoo143, - _dfoo1430, - _dfoo1432, - _dfoo1434, - _dfoo1436, - _dfoo1438, - _dfoo144, - _dfoo1440, - _dfoo1442, - _dfoo1444, - _dfoo1446, - _dfoo1448, - _dfoo145, - _dfoo1450, - _dfoo1452, - _dfoo1454, - _dfoo1456, - _dfoo1458, - _dfoo146, - _dfoo1460, - _dfoo1462, - _dfoo1464, - _dfoo1466, - _dfoo1468, - _dfoo147, - _dfoo1470, - _dfoo1472, - _dfoo1474, - _dfoo1476, - _dfoo1478, - _dfoo148, - _dfoo1480, - _dfoo1482, - _dfoo1484, - _dfoo1486, - _dfoo1488, - _dfoo149, - _dfoo1490, - _dfoo1492, - _dfoo1494, - _dfoo1496, - _dfoo1497, - _dfoo1498, - _dfoo1499, - _dfoo15, - _dfoo150, - _dfoo1500, - _dfoo1501, - _dfoo1502, - _dfoo1503, - _dfoo1504, - _dfoo1505, - _dfoo1506, - _dfoo1507, - _dfoo1508, - _dfoo1509, - _dfoo151, - _dfoo1510, - _dfoo1511, - _dfoo1512, - _dfoo1513, - _dfoo1514, - _dfoo1515, - _dfoo1516, - _dfoo1517, - _dfoo1518, - _dfoo1519, - _dfoo152, - _dfoo1520, - _dfoo1521, - _dfoo1522, - _dfoo1523, - _dfoo1524, - _dfoo1525, - _dfoo1526, - _dfoo1527, - _dfoo1528, - _dfoo1529, - _dfoo153, - _dfoo1530, - _dfoo1531, - _dfoo1532, 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m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, - m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method show_PLIC_state - assign RDY_show_PLIC_state = 1'd1 ; - assign CAN_FIRE_show_PLIC_state = 1'd1 ; - assign WILL_FIRE_show_PLIC_state = EN_show_PLIC_state ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // action method v_sources_0_m_interrupt_req - assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - - // action method v_sources_1_m_interrupt_req - assign CAN_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - - // action method v_sources_2_m_interrupt_req - assign CAN_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - - // action method v_sources_3_m_interrupt_req - assign CAN_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - - // action method v_sources_4_m_interrupt_req - assign CAN_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - - // action method v_sources_5_m_interrupt_req - assign CAN_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - - // action method v_sources_6_m_interrupt_req - assign CAN_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - - // action method v_sources_7_m_interrupt_req - assign CAN_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - - // action method v_sources_8_m_interrupt_req - assign CAN_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - - // action method v_sources_9_m_interrupt_req - assign CAN_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - - // action method v_sources_10_m_interrupt_req - assign CAN_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - - // action method v_sources_11_m_interrupt_req - assign CAN_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - - // action method v_sources_12_m_interrupt_req - assign CAN_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - - // action method v_sources_13_m_interrupt_req - assign CAN_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - - // action method v_sources_14_m_interrupt_req - assign CAN_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - - // action method v_sources_15_m_interrupt_req - assign CAN_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - - // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71312 > m_vrg_target_threshold_0 ; - - // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73317 > m_vrg_target_threshold_1 ; - - // submodule m_f_reset_reqs - FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_reqs$ENQ), - .DEQ(m_f_reset_reqs$DEQ), - .CLR(m_f_reset_reqs$CLR), - .FULL_N(m_f_reset_reqs$FULL_N), - .EMPTY_N(m_f_reset_reqs$EMPTY_N)); - - // submodule m_f_reset_rsps - FIFO20 #(.guarded(32'd1)) m_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_rsps$ENQ), - .DEQ(m_f_reset_rsps$DEQ), - .CLR(m_f_reset_rsps$CLR), - .FULL_N(m_f_reset_rsps$FULL_N), - .EMPTY_N(m_f_reset_rsps$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_addr$D_IN), - .ENQ(m_slave_xactor_f_rd_addr$ENQ), - .DEQ(m_slave_xactor_f_rd_addr$DEQ), - .CLR(m_slave_xactor_f_rd_addr$CLR), - .D_OUT(m_slave_xactor_f_rd_addr$D_OUT), - .FULL_N(m_slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_data$D_IN), - .ENQ(m_slave_xactor_f_rd_data$ENQ), - .DEQ(m_slave_xactor_f_rd_data$DEQ), - .CLR(m_slave_xactor_f_rd_data$CLR), - .D_OUT(m_slave_xactor_f_rd_data$D_OUT), - .FULL_N(m_slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_addr$D_IN), - .ENQ(m_slave_xactor_f_wr_addr$ENQ), - .DEQ(m_slave_xactor_f_wr_addr$DEQ), - .CLR(m_slave_xactor_f_wr_addr$CLR), - .D_OUT(m_slave_xactor_f_wr_addr$D_OUT), - .FULL_N(m_slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_data$D_IN), - .ENQ(m_slave_xactor_f_wr_data$ENQ), - .DEQ(m_slave_xactor_f_wr_data$DEQ), - .CLR(m_slave_xactor_f_wr_data$CLR), - .D_OUT(m_slave_xactor_f_wr_data$D_OUT), - .FULL_N(m_slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_resp$D_IN), - .ENQ(m_slave_xactor_f_wr_resp$ENQ), - .DEQ(m_slave_xactor_f_wr_resp$DEQ), - .CLR(m_slave_xactor_f_wr_resp$CLR), - .D_OUT(m_slave_xactor_f_wr_resp$D_OUT), - .FULL_N(m_slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = - m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - - // rule RL_m_rl_process_rd_req - assign CAN_FIRE_RL_m_rl_process_rd_req = - m_slave_xactor_f_rd_addr$EMPTY_N && - m_slave_xactor_f_rd_data$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - - // rule RL_m_rl_process_wr_req - assign CAN_FIRE_RL_m_rl_process_wr_req = - m_slave_xactor_f_wr_addr$EMPTY_N && - m_slave_xactor_f_wr_data$EMPTY_N && - m_slave_xactor_f_wr_resp$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_wr_req = - CAN_FIRE_RL_m_rl_process_wr_req && - !WILL_FIRE_RL_m_rl_process_rd_req ; - - // inputs to muxes for submodule ports - assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; - assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; - assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; - assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; - assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; - assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; - assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; - assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; - assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; - assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; - assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; - assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; - assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; - assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; - assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; - assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; - assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; - assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; - assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; - assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; - assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ; - assign MUX_m_vvrg_ie_0_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ; - assign MUX_m_vvrg_ie_0_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ; - assign MUX_m_vvrg_ie_0_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ; - assign MUX_m_vvrg_ie_0_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ; - assign MUX_m_vvrg_ie_0_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ; - assign MUX_m_vvrg_ie_0_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ; - assign MUX_m_vvrg_ie_0_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ; - assign MUX_m_vvrg_ie_0_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ; - assign MUX_m_vvrg_ie_0_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ; - assign MUX_m_vvrg_ie_0_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ; - assign MUX_m_vvrg_ie_0_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ; - assign MUX_m_vvrg_ie_0_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ; - assign MUX_m_vvrg_ie_0_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ; - assign MUX_m_vvrg_ie_0_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ; - assign MUX_m_vvrg_ie_0_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ; - assign MUX_m_vvrg_ie_1_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ; - assign MUX_m_vvrg_ie_1_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ; - assign MUX_m_vvrg_ie_1_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ; - assign MUX_m_vvrg_ie_1_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ; - assign MUX_m_vvrg_ie_1_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ; - assign MUX_m_vvrg_ie_1_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ; - assign MUX_m_vvrg_ie_1_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ; - assign MUX_m_vvrg_ie_1_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ; - assign MUX_m_vvrg_ie_1_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ; - assign MUX_m_vvrg_ie_1_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ; - assign MUX_m_vvrg_ie_1_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ; - assign MUX_m_vvrg_ie_1_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ; - assign MUX_m_vvrg_ie_1_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ; - assign MUX_m_vvrg_ie_1_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ; - assign MUX_m_vvrg_ie_1_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ; - assign MUX_m_vvrg_ie_1_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ; - assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; - assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2040 ; - assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2038 ; - assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2020 ; - assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2018 ; - assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2016 ; - assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2014 ; - assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2012 ; - assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2010 ; - assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2008 ; - assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2036 ; - assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2034 ; - assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2032 ; - assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2030 ; - assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2028 ; - assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2026 ; - assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2024 ; - assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2022 ; - assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2006 ; - assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2004 ; - assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1986 ; - assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1984 ; - assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1982 ; - assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1980 ; - assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1978 ; - assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1976 ; - assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1974 ; - assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2002 ; - assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2000 ; - assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1998 ; - assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1996 ; - assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1994 ; - assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1992 ; - assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1990 ; - assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1988 ; - - // register m_cfg_verbosity - assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign m_cfg_verbosity$EN = EN_set_verbosity ; - - // register m_rg_addr_base - assign m_rg_addr_base$D_IN = set_addr_map_addr_base ; - assign m_rg_addr_base$EN = EN_set_addr_map ; - - // register m_rg_addr_lim - assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign m_rg_addr_lim$EN = EN_set_addr_map ; - - // register m_vrg_servicing_source_0 - assign m_vrg_servicing_source_0$D_IN = - MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_servicing_source_1 - assign m_vrg_servicing_source_1$D_IN = - MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_0 - assign m_vrg_source_busy_0$D_IN = - !MUX_m_vrg_source_busy_0$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_1 - assign m_vrg_source_busy_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_10 - assign m_vrg_source_busy_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_11 - assign m_vrg_source_busy_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_12 - assign m_vrg_source_busy_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_13 - assign m_vrg_source_busy_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_14 - assign m_vrg_source_busy_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_15 - assign m_vrg_source_busy_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_16 - assign m_vrg_source_busy_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_2 - assign m_vrg_source_busy_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_3 - assign m_vrg_source_busy_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_4 - assign m_vrg_source_busy_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_5 - assign m_vrg_source_busy_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_6 - assign m_vrg_source_busy_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_7 - assign m_vrg_source_busy_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_8 - assign m_vrg_source_busy_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_9 - assign m_vrg_source_busy_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_0 - assign m_vrg_source_ip_0$D_IN = 1'd0 ; - assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_1 - assign m_vrg_source_ip_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_0_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_1$EN = - !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_10 - assign m_vrg_source_ip_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_9_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_10$EN = - !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_11 - assign m_vrg_source_ip_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_10_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_11$EN = - !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_12 - assign m_vrg_source_ip_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_11_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_12$EN = - !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_13 - assign m_vrg_source_ip_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_12_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_13$EN = - !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_14 - assign m_vrg_source_ip_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_13_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_14$EN = - !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_15 - assign m_vrg_source_ip_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_14_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_15$EN = - !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_16 - assign m_vrg_source_ip_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_15_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_16$EN = - !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_2 - assign m_vrg_source_ip_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_1_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_2$EN = - !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_3 - assign m_vrg_source_ip_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_2_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_3$EN = - !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_4 - assign m_vrg_source_ip_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_3_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_4$EN = - !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_5 - assign m_vrg_source_ip_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_4_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_5$EN = - !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_6 - assign m_vrg_source_ip_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_5_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_6$EN = - !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_7 - assign m_vrg_source_ip_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_6_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_7$EN = - !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_8 - assign m_vrg_source_ip_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_7_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_8$EN = - !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_9 - assign m_vrg_source_ip_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_8_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_9$EN = - !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_0 - assign m_vrg_source_prio_0$D_IN = - MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_1 - assign m_vrg_source_prio_1$D_IN = - MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_10 - assign m_vrg_source_prio_10$D_IN = - MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_11 - assign m_vrg_source_prio_11$D_IN = - MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_12 - assign m_vrg_source_prio_12$D_IN = - MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_13 - assign m_vrg_source_prio_13$D_IN = - MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_14 - assign m_vrg_source_prio_14$D_IN = - MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_15 - assign m_vrg_source_prio_15$D_IN = - MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_16 - assign m_vrg_source_prio_16$D_IN = - MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_2 - assign m_vrg_source_prio_2$D_IN = - MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_3 - assign m_vrg_source_prio_3$D_IN = - MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_4 - assign m_vrg_source_prio_4$D_IN = - MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_5 - assign m_vrg_source_prio_5$D_IN = - MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_6 - assign m_vrg_source_prio_6$D_IN = - MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_7 - assign m_vrg_source_prio_7$D_IN = - MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_8 - assign m_vrg_source_prio_8$D_IN = - MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_9 - assign m_vrg_source_prio_9$D_IN = - MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_0 - assign m_vrg_target_threshold_0$D_IN = - MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_1 - assign m_vrg_target_threshold_1$D_IN = - MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_0 - assign m_vvrg_ie_0_0$D_IN = - MUX_m_vvrg_ie_0_0$write_1__SEL_1 && - MUX_m_vvrg_ie_0_0$write_1__VAL_1 ; - assign m_vvrg_ie_0_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_1 - assign m_vvrg_ie_0_1$D_IN = - MUX_m_vvrg_ie_0_1$write_1__SEL_1 && - MUX_m_vvrg_ie_0_1$write_1__VAL_1 ; - assign m_vvrg_ie_0_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_10 - assign m_vvrg_ie_0_10$D_IN = - MUX_m_vvrg_ie_0_10$write_1__SEL_1 && - MUX_m_vvrg_ie_0_10$write_1__VAL_1 ; - assign m_vvrg_ie_0_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_11 - assign m_vvrg_ie_0_11$D_IN = - MUX_m_vvrg_ie_0_11$write_1__SEL_1 && - MUX_m_vvrg_ie_0_11$write_1__VAL_1 ; - assign m_vvrg_ie_0_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_12 - assign m_vvrg_ie_0_12$D_IN = - MUX_m_vvrg_ie_0_12$write_1__SEL_1 && - MUX_m_vvrg_ie_0_12$write_1__VAL_1 ; - assign m_vvrg_ie_0_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_13 - assign m_vvrg_ie_0_13$D_IN = - MUX_m_vvrg_ie_0_13$write_1__SEL_1 && - MUX_m_vvrg_ie_0_13$write_1__VAL_1 ; - assign m_vvrg_ie_0_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_14 - assign m_vvrg_ie_0_14$D_IN = - MUX_m_vvrg_ie_0_14$write_1__SEL_1 && - MUX_m_vvrg_ie_0_14$write_1__VAL_1 ; - assign m_vvrg_ie_0_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_15 - assign m_vvrg_ie_0_15$D_IN = - MUX_m_vvrg_ie_0_15$write_1__SEL_1 && - MUX_m_vvrg_ie_0_15$write_1__VAL_1 ; - assign m_vvrg_ie_0_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_16 - assign m_vvrg_ie_0_16$D_IN = - MUX_m_vvrg_ie_0_16$write_1__SEL_1 && - MUX_m_vvrg_ie_0_16$write_1__VAL_1 ; - assign m_vvrg_ie_0_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_2 - assign m_vvrg_ie_0_2$D_IN = - MUX_m_vvrg_ie_0_2$write_1__SEL_1 && - MUX_m_vvrg_ie_0_2$write_1__VAL_1 ; - assign m_vvrg_ie_0_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_3 - assign m_vvrg_ie_0_3$D_IN = - MUX_m_vvrg_ie_0_3$write_1__SEL_1 && - MUX_m_vvrg_ie_0_3$write_1__VAL_1 ; - assign m_vvrg_ie_0_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_4 - assign m_vvrg_ie_0_4$D_IN = - MUX_m_vvrg_ie_0_4$write_1__SEL_1 && - MUX_m_vvrg_ie_0_4$write_1__VAL_1 ; - assign m_vvrg_ie_0_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_5 - assign m_vvrg_ie_0_5$D_IN = - MUX_m_vvrg_ie_0_5$write_1__SEL_1 && - MUX_m_vvrg_ie_0_5$write_1__VAL_1 ; - assign m_vvrg_ie_0_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_6 - assign m_vvrg_ie_0_6$D_IN = - MUX_m_vvrg_ie_0_6$write_1__SEL_1 && - MUX_m_vvrg_ie_0_6$write_1__VAL_1 ; - assign m_vvrg_ie_0_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_7 - assign m_vvrg_ie_0_7$D_IN = - MUX_m_vvrg_ie_0_7$write_1__SEL_1 && - MUX_m_vvrg_ie_0_7$write_1__VAL_1 ; - assign m_vvrg_ie_0_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_8 - assign m_vvrg_ie_0_8$D_IN = - MUX_m_vvrg_ie_0_8$write_1__SEL_1 && - MUX_m_vvrg_ie_0_8$write_1__VAL_1 ; - assign m_vvrg_ie_0_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_9 - assign m_vvrg_ie_0_9$D_IN = - MUX_m_vvrg_ie_0_9$write_1__SEL_1 && - MUX_m_vvrg_ie_0_9$write_1__VAL_1 ; - assign m_vvrg_ie_0_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_0 - assign m_vvrg_ie_1_0$D_IN = - MUX_m_vvrg_ie_1_0$write_1__SEL_1 && - MUX_m_vvrg_ie_1_0$write_1__VAL_1 ; - assign m_vvrg_ie_1_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_1 - assign m_vvrg_ie_1_1$D_IN = - MUX_m_vvrg_ie_1_1$write_1__SEL_1 && - MUX_m_vvrg_ie_1_1$write_1__VAL_1 ; - assign m_vvrg_ie_1_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_10 - assign m_vvrg_ie_1_10$D_IN = - MUX_m_vvrg_ie_1_10$write_1__SEL_1 && - MUX_m_vvrg_ie_1_10$write_1__VAL_1 ; - assign m_vvrg_ie_1_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_11 - assign m_vvrg_ie_1_11$D_IN = - MUX_m_vvrg_ie_1_11$write_1__SEL_1 && - MUX_m_vvrg_ie_1_11$write_1__VAL_1 ; - assign m_vvrg_ie_1_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_12 - assign m_vvrg_ie_1_12$D_IN = - MUX_m_vvrg_ie_1_12$write_1__SEL_1 && - MUX_m_vvrg_ie_1_12$write_1__VAL_1 ; - assign m_vvrg_ie_1_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_13 - assign m_vvrg_ie_1_13$D_IN = - MUX_m_vvrg_ie_1_13$write_1__SEL_1 && - MUX_m_vvrg_ie_1_13$write_1__VAL_1 ; - assign m_vvrg_ie_1_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_14 - assign m_vvrg_ie_1_14$D_IN = - MUX_m_vvrg_ie_1_14$write_1__SEL_1 && - MUX_m_vvrg_ie_1_14$write_1__VAL_1 ; - assign m_vvrg_ie_1_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_15 - assign m_vvrg_ie_1_15$D_IN = - MUX_m_vvrg_ie_1_15$write_1__SEL_1 && - MUX_m_vvrg_ie_1_15$write_1__VAL_1 ; - assign m_vvrg_ie_1_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_16 - assign m_vvrg_ie_1_16$D_IN = - MUX_m_vvrg_ie_1_16$write_1__SEL_1 && - MUX_m_vvrg_ie_1_16$write_1__VAL_1 ; - assign m_vvrg_ie_1_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_2 - assign m_vvrg_ie_1_2$D_IN = - MUX_m_vvrg_ie_1_2$write_1__SEL_1 && - MUX_m_vvrg_ie_1_2$write_1__VAL_1 ; - assign m_vvrg_ie_1_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_3 - assign m_vvrg_ie_1_3$D_IN = - MUX_m_vvrg_ie_1_3$write_1__SEL_1 && - MUX_m_vvrg_ie_1_3$write_1__VAL_1 ; - assign m_vvrg_ie_1_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_4 - assign m_vvrg_ie_1_4$D_IN = - MUX_m_vvrg_ie_1_4$write_1__SEL_1 && - MUX_m_vvrg_ie_1_4$write_1__VAL_1 ; - assign m_vvrg_ie_1_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_5 - assign m_vvrg_ie_1_5$D_IN = - MUX_m_vvrg_ie_1_5$write_1__SEL_1 && - MUX_m_vvrg_ie_1_5$write_1__VAL_1 ; - assign m_vvrg_ie_1_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_6 - assign m_vvrg_ie_1_6$D_IN = - MUX_m_vvrg_ie_1_6$write_1__SEL_1 && - MUX_m_vvrg_ie_1_6$write_1__VAL_1 ; - assign m_vvrg_ie_1_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_7 - assign m_vvrg_ie_1_7$D_IN = - MUX_m_vvrg_ie_1_7$write_1__SEL_1 && - MUX_m_vvrg_ie_1_7$write_1__VAL_1 ; - assign m_vvrg_ie_1_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_8 - assign m_vvrg_ie_1_8$D_IN = - MUX_m_vvrg_ie_1_8$write_1__SEL_1 && - MUX_m_vvrg_ie_1_8$write_1__VAL_1 ; - assign m_vvrg_ie_1_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_9 - assign m_vvrg_ie_1_9$D_IN = - MUX_m_vvrg_ie_1_9$write_1__SEL_1 && - MUX_m_vvrg_ie_1_9$write_1__VAL_1 ; - assign m_vvrg_ie_1_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 || - WILL_FIRE_RL_m_rl_reset ; - - // submodule m_f_reset_reqs - assign m_f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign m_f_reset_reqs$DEQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_reqs$CLR = 1'b0 ; - - // submodule m_f_reset_rsps - assign m_f_reset_rsps$ENQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign m_f_reset_rsps$CLR = 1'b0 ; - - // submodule m_slave_xactor_f_rd_addr - assign m_slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign m_slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ; - assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_rd_data - assign m_slave_xactor_f_rd_data$D_IN = - { m_slave_xactor_f_rd_addr$D_OUT[96:93], - x__h26361, - rresp__h26203, - 1'd1 } ; - assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ; - assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_addr - assign m_slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign m_slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ; - assign m_slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_data - assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign m_slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; - assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_resp - assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26934 } ; - assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; - assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ; - - // remaining internal signals - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 : - ((x__h23673 == 32'h00200000) ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 : - x__h23673 != 32'h00200004 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 || - x__h24011 != 5'd0) ; - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - addr_offset__h13216[11:2] == 10'd0 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 : - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67110 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67110 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26929[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 = - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - 5'd2 : - (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ; - assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200000 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30685 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31895 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33105 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34315 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35525 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36735 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37945 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39155 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40365 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41575 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42785 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43995 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45205 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46415 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47625 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48835 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50045 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51255 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52465 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53675 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54885 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56095 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57305 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58515 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59725 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60935 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62145 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63355 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64565 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65775 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29475 <= 10'd16 ; - assign NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313 = - !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321 = - !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_11 != - v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329 = - !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_12 != - v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337 = - !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_13 != - v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345 = - !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_14 != - v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353 = - !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_15 != - v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361 = - !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_16 != - v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242 = - !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249 = - !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257 = - !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265 = - !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273 = - !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281 = - !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289 = - !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297 = - !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305 = - !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; - assign _dfoo1 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo10 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo100 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo32 ; - assign _dfoo1000 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo932 ; - assign _dfoo1001 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo865 ; - assign _dfoo1002 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo934 ; - assign _dfoo1003 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo867 ; - assign _dfoo1004 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo936 ; - assign _dfoo1005 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo869 ; - assign _dfoo1006 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo938 ; - assign _dfoo1007 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo871 ; - assign _dfoo1008 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo940 ; - assign _dfoo1009 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo873 ; - assign _dfoo1010 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo942 ; - assign _dfoo1011 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo875 ; - assign _dfoo1012 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo944 ; - assign _dfoo1013 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo877 ; - assign _dfoo1014 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo946 ; - assign _dfoo1015 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo879 ; - assign _dfoo1016 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo948 ; - assign _dfoo1017 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo881 ; - assign _dfoo1018 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo950 ; - assign _dfoo1019 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo883 ; - assign _dfoo102 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo34 ; - assign _dfoo1020 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo952 ; - assign _dfoo1022 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo954 ; - assign _dfoo1024 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo956 ; - assign _dfoo1026 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo958 ; - assign _dfoo1028 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo960 ; - assign _dfoo1030 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo962 ; - assign _dfoo1032 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo964 ; - assign _dfoo1034 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo966 ; - assign _dfoo1036 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo968 ; - assign _dfoo1038 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo970 ; - assign _dfoo104 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo36 ; - assign _dfoo1040 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo972 ; - assign _dfoo1042 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo974 ; - assign _dfoo1044 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo976 ; - assign _dfoo1046 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo978 ; - assign _dfoo1048 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo980 ; - assign _dfoo1050 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo982 ; - assign _dfoo1052 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo984 ; - assign _dfoo1054 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo986 ; - assign _dfoo1056 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo988 ; - assign _dfoo1058 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo990 ; - assign _dfoo106 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo38 ; - assign _dfoo1060 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo992 ; - assign _dfoo1062 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo994 ; - assign _dfoo1064 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo996 ; - assign _dfoo1066 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo998 ; - assign _dfoo1068 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1000 ; - assign _dfoo1070 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1002 ; - assign _dfoo1072 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1004 ; - assign _dfoo1074 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1006 ; - assign _dfoo1076 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1008 ; - assign _dfoo1078 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1010 ; - assign _dfoo108 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo40 ; - assign _dfoo1080 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1012 ; - assign _dfoo1082 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1014 ; - assign _dfoo1084 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1016 ; - assign _dfoo1086 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1018 ; - assign _dfoo1088 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1020 ; - assign _dfoo1089 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo953 ; - assign _dfoo1090 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1022 ; - assign _dfoo1091 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo955 ; - assign _dfoo1092 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1024 ; - assign _dfoo1093 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo957 ; - assign _dfoo1094 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1026 ; - assign _dfoo1095 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo959 ; - assign _dfoo1096 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1028 ; - assign _dfoo1097 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo961 ; - assign _dfoo1098 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1030 ; - assign _dfoo1099 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo963 ; - assign _dfoo11 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo110 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo42 ; - assign _dfoo1100 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1032 ; - assign _dfoo1101 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo965 ; - assign _dfoo1102 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1034 ; - assign _dfoo1103 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo967 ; - assign _dfoo1104 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1036 ; - assign _dfoo1105 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo969 ; - assign _dfoo1106 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1038 ; - assign _dfoo1107 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo971 ; - assign _dfoo1108 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1040 ; - assign _dfoo1109 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo973 ; - assign _dfoo1110 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1042 ; - assign _dfoo1111 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo975 ; - assign _dfoo1112 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1044 ; - assign _dfoo1113 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo977 ; - assign _dfoo1114 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1046 ; - assign _dfoo1115 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo979 ; - assign _dfoo1116 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1048 ; - assign _dfoo1117 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo981 ; - assign _dfoo1118 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1050 ; - assign _dfoo1119 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo983 ; - assign _dfoo112 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo44 ; - assign _dfoo1120 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1052 ; - assign _dfoo1121 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo985 ; - assign _dfoo1122 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1054 ; - assign _dfoo1123 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo987 ; - assign _dfoo1124 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1056 ; - assign _dfoo1125 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo989 ; - assign _dfoo1126 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1058 ; - assign _dfoo1127 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo991 ; - assign _dfoo1128 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1060 ; - assign _dfoo1129 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo993 ; - assign _dfoo1130 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1062 ; - assign _dfoo1131 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo995 ; - assign _dfoo1132 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1064 ; - assign _dfoo1133 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo997 ; - assign _dfoo1134 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1066 ; - assign _dfoo1135 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo999 ; - assign _dfoo1136 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1068 ; - assign _dfoo1137 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1001 ; - assign _dfoo1138 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1070 ; - assign _dfoo1139 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1003 ; - assign _dfoo114 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo46 ; - assign _dfoo1140 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1072 ; - assign _dfoo1141 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1005 ; - assign _dfoo1142 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1074 ; - assign _dfoo1143 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1007 ; - assign _dfoo1144 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1076 ; - assign _dfoo1145 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1009 ; - assign _dfoo1146 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1078 ; - assign _dfoo1147 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1011 ; - assign _dfoo1148 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1080 ; - assign _dfoo1149 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1013 ; - assign _dfoo1150 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1082 ; - assign _dfoo1151 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1015 ; - assign _dfoo1152 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1084 ; - assign _dfoo1153 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1017 ; - assign _dfoo1154 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1086 ; - assign _dfoo1155 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1019 ; - assign _dfoo1156 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1088 ; - assign _dfoo1158 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1090 ; - assign _dfoo116 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo48 ; - assign _dfoo1160 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1092 ; - assign _dfoo1162 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1094 ; - assign _dfoo1164 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1096 ; - assign _dfoo1166 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1098 ; - assign _dfoo1168 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1100 ; - assign _dfoo1170 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1102 ; - assign _dfoo1172 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1104 ; - assign _dfoo1174 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1106 ; - assign _dfoo1176 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1108 ; - assign _dfoo1178 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1110 ; - assign _dfoo118 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo50 ; - assign _dfoo1180 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1112 ; - assign _dfoo1182 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1114 ; - assign _dfoo1184 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1116 ; - assign _dfoo1186 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1118 ; - assign _dfoo1188 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1120 ; - assign _dfoo1190 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1122 ; - assign _dfoo1192 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1124 ; - assign _dfoo1194 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1126 ; - assign _dfoo1196 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1128 ; - assign _dfoo1198 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1130 ; - assign _dfoo12 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo120 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo52 ; - assign _dfoo1200 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1132 ; - assign _dfoo1202 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1134 ; - assign _dfoo1204 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1136 ; - assign _dfoo1206 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1138 ; - assign _dfoo1208 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1140 ; - assign _dfoo1210 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1142 ; - assign _dfoo1212 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1144 ; - assign _dfoo1214 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1146 ; - assign _dfoo1216 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1148 ; - assign _dfoo1218 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1150 ; - assign _dfoo122 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo54 ; - assign _dfoo1220 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1152 ; - assign _dfoo1222 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1154 ; - assign _dfoo1224 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1156 ; - assign _dfoo1225 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1089 ; - assign _dfoo1226 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1158 ; - assign _dfoo1227 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1091 ; - assign _dfoo1228 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1160 ; - assign _dfoo1229 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1093 ; - assign _dfoo1230 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1162 ; - assign _dfoo1231 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1095 ; - assign _dfoo1232 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1164 ; - assign _dfoo1233 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1097 ; - assign _dfoo1234 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1166 ; - assign _dfoo1235 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1099 ; - assign _dfoo1236 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1168 ; - assign _dfoo1237 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1101 ; - assign _dfoo1238 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1170 ; - assign _dfoo1239 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1103 ; - assign _dfoo124 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo56 ; - assign _dfoo1240 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1172 ; - assign _dfoo1241 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1105 ; - assign _dfoo1242 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1174 ; - assign _dfoo1243 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1107 ; - assign _dfoo1244 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1176 ; - assign _dfoo1245 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1109 ; - assign _dfoo1246 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1178 ; - assign _dfoo1247 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1111 ; - assign _dfoo1248 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1180 ; - assign _dfoo1249 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1113 ; - assign _dfoo1250 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1182 ; - assign _dfoo1251 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1115 ; - assign _dfoo1252 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1184 ; - assign _dfoo1253 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1117 ; - assign _dfoo1254 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1186 ; - assign _dfoo1255 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1119 ; - assign _dfoo1256 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1188 ; - assign _dfoo1257 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1121 ; - assign _dfoo1258 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1190 ; - assign _dfoo1259 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1123 ; - assign _dfoo126 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo58 ; - assign _dfoo1260 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1192 ; - assign _dfoo1261 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1125 ; - assign _dfoo1262 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1194 ; - assign _dfoo1263 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1127 ; - assign _dfoo1264 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1196 ; - assign _dfoo1265 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1129 ; - assign _dfoo1266 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1198 ; - assign _dfoo1267 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1131 ; - assign _dfoo1268 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1200 ; - assign _dfoo1269 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1133 ; - assign _dfoo1270 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1202 ; - assign _dfoo1271 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1135 ; - assign _dfoo1272 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1204 ; - assign _dfoo1273 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1137 ; - assign _dfoo1274 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1206 ; - assign _dfoo1275 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1139 ; - assign _dfoo1276 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1208 ; - assign _dfoo1277 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1141 ; - assign _dfoo1278 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1210 ; - assign _dfoo1279 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1143 ; - assign _dfoo128 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo60 ; - assign _dfoo1280 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1212 ; - assign _dfoo1281 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1145 ; - assign _dfoo1282 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1214 ; - assign _dfoo1283 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1147 ; - assign _dfoo1284 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1216 ; - assign _dfoo1285 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1149 ; - assign _dfoo1286 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1218 ; - assign _dfoo1287 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1151 ; - assign _dfoo1288 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1220 ; - assign _dfoo1289 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1153 ; - assign _dfoo1290 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1222 ; - assign _dfoo1291 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1155 ; - assign _dfoo1292 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1224 ; - assign _dfoo1294 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1226 ; - assign _dfoo1296 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1228 ; - assign _dfoo1298 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1230 ; - assign _dfoo13 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo130 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo62 ; - assign _dfoo1300 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1232 ; - assign _dfoo1302 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1234 ; - assign _dfoo1304 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1236 ; - assign _dfoo1306 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1238 ; - assign _dfoo1308 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1240 ; - assign _dfoo1310 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1242 ; - assign _dfoo1312 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1244 ; - assign _dfoo1314 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1246 ; - assign _dfoo1316 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1248 ; - assign _dfoo1318 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1250 ; - assign _dfoo132 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo64 ; - assign _dfoo1320 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1252 ; - assign _dfoo1322 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1254 ; - assign _dfoo1324 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1256 ; - assign _dfoo1326 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1258 ; - assign _dfoo1328 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1260 ; - assign _dfoo1330 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1262 ; - assign _dfoo1332 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1264 ; - assign _dfoo1334 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1266 ; - assign _dfoo1336 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1268 ; - assign _dfoo1338 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1270 ; - assign _dfoo134 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo66 ; - assign _dfoo1340 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1272 ; - assign _dfoo1342 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1274 ; - assign _dfoo1344 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1276 ; - assign _dfoo1346 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1278 ; - assign _dfoo1348 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1280 ; - assign _dfoo1350 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1282 ; - assign _dfoo1352 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1284 ; - assign _dfoo1354 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1286 ; - assign _dfoo1356 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1288 ; - assign _dfoo1358 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1290 ; - assign _dfoo136 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo68 ; - assign _dfoo1360 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1292 ; - assign _dfoo1361 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1225 ; - assign _dfoo1362 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1294 ; - assign _dfoo1363 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1227 ; - assign _dfoo1364 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1296 ; - assign _dfoo1365 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1229 ; - assign _dfoo1366 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1298 ; - assign _dfoo1367 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1231 ; - assign _dfoo1368 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1300 ; - assign _dfoo1369 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1233 ; - assign _dfoo137 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo1 ; - assign _dfoo1370 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1302 ; - assign _dfoo1371 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1235 ; - assign _dfoo1372 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1304 ; - assign _dfoo1373 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1237 ; - assign _dfoo1374 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1306 ; - assign _dfoo1375 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1239 ; - assign _dfoo1376 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1308 ; - assign _dfoo1377 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1241 ; - assign _dfoo1378 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1310 ; - assign _dfoo1379 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1243 ; - assign _dfoo138 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo70 ; - assign _dfoo1380 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1312 ; - assign _dfoo1381 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1245 ; - assign _dfoo1382 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1314 ; - assign _dfoo1383 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1247 ; - assign _dfoo1384 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1316 ; - assign _dfoo1385 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1249 ; - assign _dfoo1386 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1318 ; - assign _dfoo1387 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1251 ; - assign _dfoo1388 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1320 ; - assign _dfoo1389 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1253 ; - assign _dfoo139 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo3 ; - assign _dfoo1390 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1322 ; - assign _dfoo1391 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1255 ; - assign _dfoo1392 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1324 ; - assign _dfoo1393 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1257 ; - assign _dfoo1394 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1326 ; - assign _dfoo1395 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1259 ; - assign _dfoo1396 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1328 ; - assign _dfoo1397 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1261 ; - assign _dfoo1398 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1330 ; - assign _dfoo1399 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1263 ; - assign _dfoo14 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo140 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo72 ; - assign _dfoo1400 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1332 ; - assign _dfoo1401 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1265 ; - assign _dfoo1402 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1334 ; - assign _dfoo1403 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1267 ; - assign _dfoo1404 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1336 ; - assign _dfoo1405 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1269 ; - assign _dfoo1406 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1338 ; - assign _dfoo1407 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1271 ; - assign _dfoo1408 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1340 ; - assign _dfoo1409 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1273 ; - assign _dfoo141 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo5 ; - assign _dfoo1410 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1342 ; - assign _dfoo1411 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1275 ; - assign _dfoo1412 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1344 ; - assign _dfoo1413 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1277 ; - assign _dfoo1414 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1346 ; - assign _dfoo1415 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1279 ; - assign _dfoo1416 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1348 ; - assign _dfoo1417 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1281 ; - assign _dfoo1418 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1350 ; - assign _dfoo1419 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1283 ; - assign _dfoo142 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo74 ; - assign _dfoo1420 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1352 ; - assign _dfoo1421 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1285 ; - assign _dfoo1422 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1354 ; - assign _dfoo1423 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1287 ; - assign _dfoo1424 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1356 ; - assign _dfoo1425 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1289 ; - assign _dfoo1426 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1358 ; - assign _dfoo1427 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1291 ; - assign _dfoo1428 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1360 ; - assign _dfoo143 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo7 ; - assign _dfoo1430 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1362 ; - assign _dfoo1432 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1364 ; - assign _dfoo1434 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1366 ; - assign _dfoo1436 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1368 ; - assign _dfoo1438 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1370 ; - assign _dfoo144 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo76 ; - assign _dfoo1440 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1372 ; - assign _dfoo1442 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1374 ; - assign _dfoo1444 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1376 ; - assign _dfoo1446 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1378 ; - assign _dfoo1448 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1380 ; - assign _dfoo145 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo9 ; - assign _dfoo1450 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1382 ; - assign _dfoo1452 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1384 ; - assign _dfoo1454 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1386 ; - assign _dfoo1456 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1388 ; - assign _dfoo1458 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1390 ; - assign _dfoo146 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo78 ; - assign _dfoo1460 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1392 ; - assign _dfoo1462 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1394 ; - assign _dfoo1464 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1396 ; - assign _dfoo1466 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1398 ; - assign _dfoo1468 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1400 ; - assign _dfoo147 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo11 ; - assign _dfoo1470 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1402 ; - assign _dfoo1472 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1404 ; - assign _dfoo1474 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1406 ; - assign _dfoo1476 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1408 ; - assign _dfoo1478 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1410 ; - assign _dfoo148 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo80 ; - assign _dfoo1480 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1412 ; - assign _dfoo1482 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1414 ; - assign _dfoo1484 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1416 ; - assign _dfoo1486 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1418 ; - assign _dfoo1488 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1420 ; - assign _dfoo149 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo13 ; - assign _dfoo1490 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1422 ; - assign _dfoo1492 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1424 ; - assign _dfoo1494 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1426 ; - assign _dfoo1496 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1428 ; - assign _dfoo1497 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1361 ; - assign _dfoo1498 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1430 ; - assign _dfoo1499 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1363 ; - assign _dfoo15 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo150 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo82 ; - assign _dfoo1500 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1432 ; - assign _dfoo1501 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1365 ; - assign _dfoo1502 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1434 ; - assign _dfoo1503 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1367 ; - assign _dfoo1504 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1436 ; - assign _dfoo1505 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1369 ; - assign _dfoo1506 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1438 ; - assign _dfoo1507 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1371 ; - assign _dfoo1508 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1440 ; - assign _dfoo1509 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1373 ; - assign _dfoo151 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo15 ; - assign _dfoo1510 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1442 ; - assign _dfoo1511 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1375 ; - assign _dfoo1512 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1444 ; - assign _dfoo1513 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1377 ; - assign _dfoo1514 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1446 ; - assign _dfoo1515 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1379 ; - assign _dfoo1516 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1448 ; - assign _dfoo1517 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1381 ; - assign _dfoo1518 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1450 ; - assign _dfoo1519 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1383 ; - assign _dfoo152 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo84 ; - assign _dfoo1520 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1452 ; - assign _dfoo1521 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1385 ; - assign _dfoo1522 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1454 ; - assign _dfoo1523 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1387 ; - assign _dfoo1524 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1456 ; - assign _dfoo1525 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1389 ; - assign _dfoo1526 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1458 ; - assign _dfoo1527 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1391 ; - assign _dfoo1528 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1460 ; - assign _dfoo1529 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1393 ; - assign _dfoo153 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo17 ; - assign _dfoo1530 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1462 ; - assign _dfoo1531 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1395 ; - assign _dfoo1532 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1464 ; - assign _dfoo1533 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1397 ; - assign _dfoo1534 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1466 ; - assign _dfoo1535 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1399 ; - assign _dfoo1536 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1468 ; - assign _dfoo1537 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1401 ; - assign _dfoo1538 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1470 ; - assign _dfoo1539 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1403 ; - assign _dfoo154 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo86 ; - assign _dfoo1540 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1472 ; - assign _dfoo1541 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1405 ; - assign _dfoo1542 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1474 ; - assign _dfoo1543 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1407 ; - assign _dfoo1544 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1476 ; - assign _dfoo1545 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1409 ; - assign _dfoo1546 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1478 ; - assign _dfoo1547 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1411 ; - assign _dfoo1548 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1480 ; - assign _dfoo1549 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1413 ; - assign _dfoo155 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo19 ; - assign _dfoo1550 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1482 ; - assign _dfoo1551 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1415 ; - assign _dfoo1552 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1484 ; - assign _dfoo1553 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1417 ; - assign _dfoo1554 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1486 ; - assign _dfoo1555 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1419 ; - assign _dfoo1556 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1488 ; - assign _dfoo1557 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1421 ; - assign _dfoo1558 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1490 ; - assign _dfoo1559 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1423 ; - assign _dfoo156 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo88 ; - assign _dfoo1560 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1492 ; - assign _dfoo1561 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1425 ; - assign _dfoo1562 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1494 ; - assign _dfoo1563 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1427 ; - assign _dfoo1564 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1496 ; - assign _dfoo1566 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1498 ; - assign _dfoo1568 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1500 ; - assign _dfoo157 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo21 ; - assign _dfoo1570 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1502 ; - assign _dfoo1572 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1504 ; - assign _dfoo1574 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1506 ; - assign _dfoo1576 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1508 ; - assign _dfoo1578 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1510 ; - assign _dfoo158 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo90 ; - assign _dfoo1580 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1512 ; - assign _dfoo1582 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1514 ; - assign _dfoo1584 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1516 ; - assign _dfoo1586 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1518 ; - assign _dfoo1588 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1520 ; - assign _dfoo159 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo23 ; - assign _dfoo1590 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1522 ; - assign _dfoo1592 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1524 ; - assign _dfoo1594 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1526 ; - assign _dfoo1596 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1528 ; - assign _dfoo1598 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1530 ; - assign _dfoo16 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo160 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo92 ; - assign _dfoo1600 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1532 ; - assign _dfoo1602 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1534 ; - assign _dfoo1604 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1536 ; - assign _dfoo1606 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1538 ; - assign _dfoo1608 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1540 ; - assign _dfoo161 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo25 ; - assign _dfoo1610 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1542 ; - assign _dfoo1612 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1544 ; - assign _dfoo1614 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1546 ; - assign _dfoo1616 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1548 ; - assign _dfoo1618 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1550 ; - assign _dfoo162 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo94 ; - assign _dfoo1620 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1552 ; - assign _dfoo1622 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1554 ; - assign _dfoo1624 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1556 ; - assign _dfoo1626 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1558 ; - assign _dfoo1628 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1560 ; - assign _dfoo163 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo27 ; - assign _dfoo1630 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1562 ; - assign _dfoo1632 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1564 ; - assign _dfoo1633 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1497 ; - assign _dfoo1634 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1566 ; - assign _dfoo1635 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1499 ; - assign _dfoo1636 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1568 ; - assign _dfoo1637 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1501 ; - assign _dfoo1638 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1570 ; - assign _dfoo1639 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1503 ; - assign _dfoo164 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo96 ; - assign _dfoo1640 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1572 ; - assign _dfoo1641 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1505 ; - assign _dfoo1642 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1574 ; - assign _dfoo1643 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1507 ; - assign _dfoo1644 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1576 ; - assign _dfoo1645 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1509 ; - assign _dfoo1646 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1578 ; - assign _dfoo1647 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1511 ; - assign _dfoo1648 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1580 ; - assign _dfoo1649 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1513 ; - assign _dfoo165 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo29 ; - assign _dfoo1650 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1582 ; - assign _dfoo1651 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1515 ; - assign _dfoo1652 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1584 ; - assign _dfoo1653 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1517 ; - assign _dfoo1654 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1586 ; - assign _dfoo1655 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1519 ; - assign _dfoo1656 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1588 ; - assign _dfoo1657 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1521 ; - assign _dfoo1658 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1590 ; - assign _dfoo1659 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1523 ; - assign _dfoo166 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo98 ; - assign _dfoo1660 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1592 ; - assign _dfoo1661 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1525 ; - assign _dfoo1662 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1594 ; - assign _dfoo1663 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1527 ; - assign _dfoo1664 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1596 ; - assign _dfoo1665 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1529 ; - assign _dfoo1666 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1598 ; - assign _dfoo1667 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1531 ; - assign _dfoo1668 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1600 ; - assign _dfoo1669 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1533 ; - assign _dfoo167 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo31 ; - assign _dfoo1670 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1602 ; - assign _dfoo1671 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1535 ; - assign _dfoo1672 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1604 ; - assign _dfoo1673 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1537 ; - assign _dfoo1674 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1606 ; - assign _dfoo1675 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1539 ; - assign _dfoo1676 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1608 ; - assign _dfoo1677 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1541 ; - assign _dfoo1678 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1610 ; - assign _dfoo1679 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1543 ; - assign _dfoo168 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo100 ; - assign _dfoo1680 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1612 ; - assign _dfoo1681 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1545 ; - assign _dfoo1682 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1614 ; - assign _dfoo1683 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1547 ; - assign _dfoo1684 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1616 ; - assign _dfoo1685 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1549 ; - assign _dfoo1686 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1618 ; - assign _dfoo1687 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1551 ; - assign _dfoo1688 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1620 ; - assign _dfoo1689 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1553 ; - assign _dfoo169 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo33 ; - assign _dfoo1690 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1622 ; - assign _dfoo1691 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1555 ; - assign _dfoo1692 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1624 ; - assign _dfoo1693 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1557 ; - assign _dfoo1694 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1626 ; - assign _dfoo1695 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1559 ; - assign _dfoo1696 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1628 ; - assign _dfoo1697 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1561 ; - assign _dfoo1698 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1630 ; - assign _dfoo1699 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1563 ; - assign _dfoo17 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo170 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo102 ; - assign _dfoo1700 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1632 ; - assign _dfoo1702 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1634 ; - assign _dfoo1704 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1636 ; - assign _dfoo1706 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1638 ; - assign _dfoo1708 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1640 ; - assign _dfoo171 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo35 ; - assign _dfoo1710 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1642 ; - assign _dfoo1712 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1644 ; - assign _dfoo1714 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1646 ; - assign _dfoo1716 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1648 ; - assign _dfoo1718 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1650 ; - assign _dfoo172 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo104 ; - assign _dfoo1720 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1652 ; - assign _dfoo1722 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1654 ; - assign _dfoo1724 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1656 ; - assign _dfoo1726 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1658 ; - assign _dfoo1728 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1660 ; - assign _dfoo173 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo37 ; - assign _dfoo1730 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1662 ; - assign _dfoo1732 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1664 ; - assign _dfoo1734 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1666 ; - assign _dfoo1736 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1668 ; - assign _dfoo1738 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1670 ; - assign _dfoo174 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo106 ; - assign _dfoo1740 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1672 ; - assign _dfoo1742 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1674 ; - assign _dfoo1744 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1676 ; - assign _dfoo1746 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1678 ; - assign _dfoo1748 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1680 ; - assign _dfoo175 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo39 ; - assign _dfoo1750 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1682 ; - assign _dfoo1752 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1684 ; - assign _dfoo1754 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1686 ; - assign _dfoo1756 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1688 ; - assign _dfoo1758 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1690 ; - assign _dfoo176 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo108 ; - assign _dfoo1760 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1692 ; - assign _dfoo1762 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1694 ; - assign _dfoo1764 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1696 ; - assign _dfoo1766 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1698 ; - assign _dfoo1768 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1700 ; - assign _dfoo1769 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1633 ; - assign _dfoo177 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo41 ; - assign _dfoo1770 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1702 ; - assign _dfoo1771 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1635 ; - assign _dfoo1772 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1704 ; - assign _dfoo1773 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1637 ; - assign _dfoo1774 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1706 ; - assign _dfoo1775 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1639 ; - assign _dfoo1776 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1708 ; - assign _dfoo1777 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1641 ; - assign _dfoo1778 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1710 ; - assign _dfoo1779 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1643 ; - assign _dfoo178 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo110 ; - assign _dfoo1780 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1712 ; - assign _dfoo1781 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1645 ; - assign _dfoo1782 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1714 ; - assign _dfoo1783 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1647 ; - assign _dfoo1784 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1716 ; - assign _dfoo1785 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1649 ; - assign _dfoo1786 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1718 ; - assign _dfoo1787 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1651 ; - assign _dfoo1788 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1720 ; - assign _dfoo1789 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1653 ; - assign _dfoo179 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo43 ; - assign _dfoo1790 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1722 ; - assign _dfoo1791 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1655 ; - assign _dfoo1792 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1724 ; - assign _dfoo1793 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1657 ; - assign _dfoo1794 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1726 ; - assign _dfoo1795 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1659 ; - assign _dfoo1796 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1728 ; - assign _dfoo1797 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1661 ; - assign _dfoo1798 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1730 ; - assign _dfoo1799 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1663 ; - assign _dfoo18 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo180 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo112 ; - assign _dfoo1800 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1732 ; - assign _dfoo1801 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1665 ; - assign _dfoo1802 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1734 ; - assign _dfoo1803 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1667 ; - assign _dfoo1804 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1736 ; - assign _dfoo1805 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1669 ; - assign _dfoo1806 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1738 ; - assign _dfoo1807 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1671 ; - assign _dfoo1808 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1740 ; - assign _dfoo1809 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1673 ; - assign _dfoo181 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo45 ; - assign _dfoo1810 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1742 ; - assign _dfoo1811 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1675 ; - assign _dfoo1812 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1744 ; - assign _dfoo1813 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1677 ; - assign _dfoo1814 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1746 ; - assign _dfoo1815 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1679 ; - assign _dfoo1816 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1748 ; - assign _dfoo1817 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1681 ; - assign _dfoo1818 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1750 ; - assign _dfoo1819 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1683 ; - assign _dfoo182 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo114 ; - assign _dfoo1820 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1752 ; - assign _dfoo1821 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1685 ; - assign _dfoo1822 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1754 ; - assign _dfoo1823 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1687 ; - assign _dfoo1824 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1756 ; - assign _dfoo1825 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1689 ; - assign _dfoo1826 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1758 ; - assign _dfoo1827 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1691 ; - assign _dfoo1828 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1760 ; - assign _dfoo1829 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1693 ; - assign _dfoo183 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo47 ; - assign _dfoo1830 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1762 ; - assign _dfoo1831 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1695 ; - assign _dfoo1832 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1764 ; - assign _dfoo1833 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1697 ; - assign _dfoo1834 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1766 ; - assign _dfoo1835 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1699 ; - assign _dfoo1836 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1768 ; - assign _dfoo1838 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1770 ; - assign _dfoo184 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo116 ; - assign _dfoo1840 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1772 ; - assign _dfoo1842 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1774 ; - assign _dfoo1844 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1776 ; - assign _dfoo1846 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1778 ; - assign _dfoo1848 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1780 ; - assign _dfoo185 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo49 ; - assign _dfoo1850 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1782 ; - assign _dfoo1852 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1784 ; - assign _dfoo1854 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1786 ; - assign _dfoo1856 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1788 ; - assign _dfoo1858 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1790 ; - assign _dfoo186 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo118 ; - assign _dfoo1860 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1792 ; - assign _dfoo1862 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1794 ; - assign _dfoo1864 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1796 ; - assign _dfoo1866 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1798 ; - assign _dfoo1868 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1800 ; - assign _dfoo187 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo51 ; - assign _dfoo1870 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1802 ; - assign _dfoo1872 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1804 ; - assign _dfoo1874 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1806 ; - assign _dfoo1876 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1808 ; - assign _dfoo1878 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1810 ; - assign _dfoo188 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo120 ; - assign _dfoo1880 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1812 ; - assign _dfoo1882 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1814 ; - assign _dfoo1884 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1816 ; - assign _dfoo1886 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1818 ; - assign _dfoo1888 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1820 ; - assign _dfoo189 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo53 ; - assign _dfoo1890 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1822 ; - assign _dfoo1892 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1824 ; - assign _dfoo1894 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1826 ; - assign _dfoo1896 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1828 ; - assign _dfoo1898 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1830 ; - assign _dfoo19 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo190 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo122 ; - assign _dfoo1900 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1832 ; - assign _dfoo1902 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1834 ; - assign _dfoo1904 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1836 ; - assign _dfoo1905 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1769 ; - assign _dfoo1906 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1838 ; - assign _dfoo1907 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1771 ; - assign _dfoo1908 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1840 ; - assign _dfoo1909 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1773 ; - assign _dfoo191 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo55 ; - assign _dfoo1910 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1842 ; - assign _dfoo1911 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1775 ; - assign _dfoo1912 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1844 ; - assign _dfoo1913 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1777 ; - assign _dfoo1914 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1846 ; - assign _dfoo1915 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1779 ; - assign _dfoo1916 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1848 ; - assign _dfoo1917 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1781 ; - assign _dfoo1918 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1850 ; - assign _dfoo1919 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1783 ; - assign _dfoo192 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo124 ; - assign _dfoo1920 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1852 ; - assign _dfoo1921 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1785 ; - assign _dfoo1922 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1854 ; - assign _dfoo1923 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1787 ; - assign _dfoo1924 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1856 ; - assign _dfoo1925 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1789 ; - assign _dfoo1926 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1858 ; - assign _dfoo1927 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1791 ; - assign _dfoo1928 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1860 ; - assign _dfoo1929 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1793 ; - assign _dfoo193 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo57 ; - assign _dfoo1930 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1862 ; - assign _dfoo1931 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1795 ; - assign _dfoo1932 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1864 ; - assign _dfoo1933 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1797 ; - assign _dfoo1934 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1866 ; - assign _dfoo1935 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1799 ; - assign _dfoo1936 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1868 ; - assign _dfoo1937 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1801 ; - assign _dfoo1938 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1870 ; - assign _dfoo1939 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1803 ; - assign _dfoo194 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo126 ; - assign _dfoo1940 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1872 ; - assign _dfoo1941 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1805 ; - assign _dfoo1942 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1874 ; - assign _dfoo1943 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1807 ; - assign _dfoo1944 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1876 ; - assign _dfoo1945 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1809 ; - assign _dfoo1946 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1878 ; - assign _dfoo1947 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1811 ; - assign _dfoo1948 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1880 ; - assign _dfoo1949 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1813 ; - assign _dfoo195 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo59 ; - assign _dfoo1950 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1882 ; - assign _dfoo1951 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1815 ; - assign _dfoo1952 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1884 ; - assign _dfoo1953 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1817 ; - assign _dfoo1954 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1886 ; - assign _dfoo1955 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1819 ; - assign _dfoo1956 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1888 ; - assign _dfoo1957 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1821 ; - assign _dfoo1958 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1890 ; - assign _dfoo1959 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1823 ; - assign _dfoo196 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo128 ; - assign _dfoo1960 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1892 ; - assign _dfoo1961 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1825 ; - assign _dfoo1962 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1894 ; - assign _dfoo1963 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1827 ; - assign _dfoo1964 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1896 ; - assign _dfoo1965 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1829 ; - assign _dfoo1966 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1898 ; - assign _dfoo1967 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1831 ; - assign _dfoo1968 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1900 ; - assign _dfoo1969 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1833 ; - assign _dfoo197 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo61 ; - assign _dfoo1970 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1902 ; - assign _dfoo1971 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1835 ; - assign _dfoo1972 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1904 ; - assign _dfoo1974 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1906 ; - assign _dfoo1976 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1908 ; - assign _dfoo1978 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1910 ; - assign _dfoo198 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo130 ; - assign _dfoo1980 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1912 ; - assign _dfoo1982 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1914 ; - assign _dfoo1984 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1916 ; - assign _dfoo1986 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1918 ; - assign _dfoo1988 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1920 ; - assign _dfoo199 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo63 ; - assign _dfoo1990 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1922 ; - assign _dfoo1992 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1924 ; - assign _dfoo1994 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1926 ; - assign _dfoo1996 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1928 ; - assign _dfoo1998 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1930 ; - assign _dfoo2 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo20 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo200 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo132 ; - assign _dfoo2000 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1932 ; - assign _dfoo2002 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1934 ; - assign _dfoo2004 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1936 ; - assign _dfoo2006 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1938 ; - assign _dfoo2008 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1940 ; - assign _dfoo201 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo65 ; - assign _dfoo2010 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1942 ; - assign _dfoo2012 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1944 ; - assign _dfoo2014 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1946 ; - assign _dfoo2016 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1948 ; - assign _dfoo2018 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1950 ; - assign _dfoo202 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo134 ; - assign _dfoo2020 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1952 ; - assign _dfoo2022 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1954 ; - assign _dfoo2024 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1956 ; - assign _dfoo2026 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1958 ; - assign _dfoo2028 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1960 ; - assign _dfoo203 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo67 ; - assign _dfoo2030 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1962 ; - assign _dfoo2032 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1964 ; - assign _dfoo2034 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1966 ; - assign _dfoo2036 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1968 ; - assign _dfoo2038 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1970 ; - assign _dfoo204 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo136 ; - assign _dfoo2040 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1972 ; - assign _dfoo2041 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1905 ; - assign _dfoo2043 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1907 ; - assign _dfoo2045 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1909 ; - assign _dfoo2047 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1911 ; - assign _dfoo2049 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1913 ; - assign _dfoo2051 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1915 ; - assign _dfoo2053 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1917 ; - assign _dfoo2055 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1919 ; - assign _dfoo2057 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1921 ; - assign _dfoo2059 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1923 ; - assign _dfoo206 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo138 ; - assign _dfoo2061 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1925 ; - assign _dfoo2063 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1927 ; - assign _dfoo2065 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1929 ; - assign _dfoo2067 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1931 ; - assign _dfoo2069 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1933 ; - assign _dfoo2071 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1935 ; - assign _dfoo2073 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1937 ; - assign _dfoo2075 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1939 ; - assign _dfoo2077 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1941 ; - assign _dfoo2079 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1943 ; - assign _dfoo208 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo140 ; - assign _dfoo2081 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1945 ; - assign _dfoo2083 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1947 ; - assign _dfoo2085 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1949 ; - assign _dfoo2087 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1951 ; - assign _dfoo2089 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1953 ; - assign _dfoo2091 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1955 ; - assign _dfoo2093 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1957 ; - assign _dfoo2095 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1959 ; - assign _dfoo2097 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1961 ; - assign _dfoo2099 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1963 ; - assign _dfoo21 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo210 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo142 ; - assign _dfoo2101 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1965 ; - assign _dfoo2103 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1967 ; - assign _dfoo2105 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1969 ; - assign _dfoo2107 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1971 ; - assign _dfoo212 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo144 ; - assign _dfoo214 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo146 ; - assign _dfoo216 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo148 ; - assign _dfoo218 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo150 ; - assign _dfoo22 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo220 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo152 ; - assign _dfoo222 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo154 ; - assign _dfoo224 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo156 ; - assign _dfoo226 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo158 ; - assign _dfoo228 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo160 ; - assign _dfoo23 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo230 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo162 ; - assign _dfoo232 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo164 ; - assign _dfoo234 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo166 ; - assign _dfoo236 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo168 ; - assign _dfoo238 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo170 ; - assign _dfoo24 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo240 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo172 ; - assign _dfoo242 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo174 ; - assign _dfoo244 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo176 ; - assign _dfoo246 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo178 ; - assign _dfoo248 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo180 ; - assign _dfoo25 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo250 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo182 ; - assign _dfoo252 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo184 ; - assign _dfoo254 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo186 ; - assign _dfoo256 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo188 ; - assign _dfoo258 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo190 ; - assign _dfoo26 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo260 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo192 ; - assign _dfoo262 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo194 ; - assign _dfoo264 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo196 ; - assign _dfoo266 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo198 ; - assign _dfoo268 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo200 ; - assign _dfoo27 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo270 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo202 ; - assign _dfoo272 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo204 ; - assign _dfoo273 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo137 ; - assign _dfoo274 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo206 ; - assign _dfoo275 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo139 ; - assign _dfoo276 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo208 ; - assign _dfoo277 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo141 ; - assign _dfoo278 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo210 ; - assign _dfoo279 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo143 ; - assign _dfoo28 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo280 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo212 ; - assign _dfoo281 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo145 ; - assign _dfoo282 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo214 ; - assign _dfoo283 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo147 ; - assign _dfoo284 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo216 ; - assign _dfoo285 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo149 ; - assign _dfoo286 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo218 ; - assign _dfoo287 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo151 ; - assign _dfoo288 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo220 ; - assign _dfoo289 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo153 ; - assign _dfoo29 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo290 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo222 ; - assign _dfoo291 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo155 ; - assign _dfoo292 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo224 ; - assign _dfoo293 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo157 ; - assign _dfoo294 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo226 ; - assign _dfoo295 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo159 ; - assign _dfoo296 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo228 ; - assign _dfoo297 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo161 ; - assign _dfoo298 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo230 ; - assign _dfoo299 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo163 ; - assign _dfoo3 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo30 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo300 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo232 ; - assign _dfoo301 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo165 ; - assign _dfoo302 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo234 ; - assign _dfoo303 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo167 ; - assign _dfoo304 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo236 ; - assign _dfoo305 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo169 ; - assign _dfoo306 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo238 ; - assign _dfoo307 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo171 ; - assign _dfoo308 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo240 ; - assign _dfoo309 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo173 ; - assign _dfoo31 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo310 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo242 ; - assign _dfoo311 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo175 ; - assign _dfoo312 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo244 ; - assign _dfoo313 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo177 ; - assign _dfoo314 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo246 ; - assign _dfoo315 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo179 ; - assign _dfoo316 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo248 ; - assign _dfoo317 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo181 ; - assign _dfoo318 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo250 ; - assign _dfoo319 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo183 ; - assign _dfoo32 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo320 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo252 ; - assign _dfoo321 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo185 ; - assign _dfoo322 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo254 ; - assign _dfoo323 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo187 ; - assign _dfoo324 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo256 ; - assign _dfoo325 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo189 ; - assign _dfoo326 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo258 ; - assign _dfoo327 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo191 ; - assign _dfoo328 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo260 ; - assign _dfoo329 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo193 ; - assign _dfoo33 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo330 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo262 ; - assign _dfoo331 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo195 ; - assign _dfoo332 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo264 ; - assign _dfoo333 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo197 ; - assign _dfoo334 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo266 ; - assign _dfoo335 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo199 ; - assign _dfoo336 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo268 ; - assign _dfoo337 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo201 ; - assign _dfoo338 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo270 ; - assign _dfoo339 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo203 ; - assign _dfoo34 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo340 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo272 ; - assign _dfoo342 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo274 ; - assign _dfoo344 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo276 ; - assign _dfoo346 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo278 ; - assign _dfoo348 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo280 ; - assign _dfoo35 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo350 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo282 ; - assign _dfoo352 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo284 ; - assign _dfoo354 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo286 ; - assign _dfoo356 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo288 ; - assign _dfoo358 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo290 ; - assign _dfoo36 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo360 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo292 ; - assign _dfoo362 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo294 ; - assign _dfoo364 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo296 ; - assign _dfoo366 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo298 ; - assign _dfoo368 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo300 ; - assign _dfoo37 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo370 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo302 ; - assign _dfoo372 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo304 ; - assign _dfoo374 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo306 ; - assign _dfoo376 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo308 ; - assign _dfoo378 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo310 ; - assign _dfoo38 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo380 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo312 ; - assign _dfoo382 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo314 ; - assign _dfoo384 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo316 ; - assign _dfoo386 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo318 ; - assign _dfoo388 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo320 ; - assign _dfoo39 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo390 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo322 ; - assign _dfoo392 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo324 ; - assign _dfoo394 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo326 ; - assign _dfoo396 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo328 ; - assign _dfoo398 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo330 ; - assign _dfoo4 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo40 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo400 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo332 ; - assign _dfoo402 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo334 ; - assign _dfoo404 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo336 ; - assign _dfoo406 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo338 ; - assign _dfoo408 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo340 ; - assign _dfoo409 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo273 ; - assign _dfoo41 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo410 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo342 ; - assign _dfoo411 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo275 ; - assign _dfoo412 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo344 ; - assign _dfoo413 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo277 ; - assign _dfoo414 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo346 ; - assign _dfoo415 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo279 ; - assign _dfoo416 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo348 ; - assign _dfoo417 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo281 ; - assign _dfoo418 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo350 ; - assign _dfoo419 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo283 ; - assign _dfoo42 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo420 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo352 ; - assign _dfoo421 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo285 ; - assign _dfoo422 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo354 ; - assign _dfoo423 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo287 ; - assign _dfoo424 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo356 ; - assign _dfoo425 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo289 ; - assign _dfoo426 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo358 ; - assign _dfoo427 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo291 ; - assign _dfoo428 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo360 ; - assign _dfoo429 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo293 ; - assign _dfoo43 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo430 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo362 ; - assign _dfoo431 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo295 ; - assign _dfoo432 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo364 ; - assign _dfoo433 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo297 ; - assign _dfoo434 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo366 ; - assign _dfoo435 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo299 ; - assign _dfoo436 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo368 ; - assign _dfoo437 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo301 ; - assign _dfoo438 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo370 ; - assign _dfoo439 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo303 ; - assign _dfoo44 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo440 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo372 ; - assign _dfoo441 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo305 ; - assign _dfoo442 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo374 ; - assign _dfoo443 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo307 ; - assign _dfoo444 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo376 ; - assign _dfoo445 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo309 ; - assign _dfoo446 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo378 ; - assign _dfoo447 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo311 ; - assign _dfoo448 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo380 ; - assign _dfoo449 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo313 ; - assign _dfoo45 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo450 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo382 ; - assign _dfoo451 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo315 ; - assign _dfoo452 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo384 ; - assign _dfoo453 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo317 ; - assign _dfoo454 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo386 ; - assign _dfoo455 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo319 ; - assign _dfoo456 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo388 ; - assign _dfoo457 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo321 ; - assign _dfoo458 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo390 ; - assign _dfoo459 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo323 ; - assign _dfoo46 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo460 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo392 ; - assign _dfoo461 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo325 ; - assign _dfoo462 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo394 ; - assign _dfoo463 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo327 ; - assign _dfoo464 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo396 ; - assign _dfoo465 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo329 ; - assign _dfoo466 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo398 ; - assign _dfoo467 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo331 ; - assign _dfoo468 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo400 ; - assign _dfoo469 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo333 ; - assign _dfoo47 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo470 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo402 ; - assign _dfoo471 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo335 ; - assign _dfoo472 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo404 ; - assign _dfoo473 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo337 ; - assign _dfoo474 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo406 ; - assign _dfoo475 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo339 ; - assign _dfoo476 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo408 ; - assign _dfoo478 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo410 ; - assign _dfoo48 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo480 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo412 ; - assign _dfoo482 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo414 ; - assign _dfoo484 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo416 ; - assign _dfoo486 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo418 ; - assign _dfoo488 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo420 ; - assign _dfoo49 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo490 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo422 ; - assign _dfoo492 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo424 ; - assign _dfoo494 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo426 ; - assign _dfoo496 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo428 ; - assign _dfoo498 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo430 ; - assign _dfoo5 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo50 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo500 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo432 ; - assign _dfoo502 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo434 ; - assign _dfoo504 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo436 ; - assign _dfoo506 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo438 ; - assign _dfoo508 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo440 ; - assign _dfoo51 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo510 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo442 ; - assign _dfoo512 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo444 ; - assign _dfoo514 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo446 ; - assign _dfoo516 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo448 ; - assign _dfoo518 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo450 ; - assign _dfoo52 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo520 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo452 ; - assign _dfoo522 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo454 ; - assign _dfoo524 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo456 ; - assign _dfoo526 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo458 ; - assign _dfoo528 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo460 ; - assign _dfoo53 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo530 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo462 ; - assign _dfoo532 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo464 ; - assign _dfoo534 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo466 ; - assign _dfoo536 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo468 ; - assign _dfoo538 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo470 ; - assign _dfoo54 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo540 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo472 ; - assign _dfoo542 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo474 ; - assign _dfoo544 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo476 ; - assign _dfoo545 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo409 ; - assign _dfoo546 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo478 ; - assign _dfoo547 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo411 ; - assign _dfoo548 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo480 ; - assign _dfoo549 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo413 ; - assign _dfoo55 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo550 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo482 ; - assign _dfoo551 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo415 ; - assign _dfoo552 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo484 ; - assign _dfoo553 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo417 ; - assign _dfoo554 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo486 ; - assign _dfoo555 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo419 ; - assign _dfoo556 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo488 ; - assign _dfoo557 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo421 ; - assign _dfoo558 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo490 ; - assign _dfoo559 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo423 ; - assign _dfoo56 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo560 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo492 ; - assign _dfoo561 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo425 ; - assign _dfoo562 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo494 ; - assign _dfoo563 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo427 ; - assign _dfoo564 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo496 ; - assign _dfoo565 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo429 ; - assign _dfoo566 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo498 ; - assign _dfoo567 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo431 ; - assign _dfoo568 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo500 ; - assign _dfoo569 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo433 ; - assign _dfoo57 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo570 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo502 ; - assign _dfoo571 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo435 ; - assign _dfoo572 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo504 ; - assign _dfoo573 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo437 ; - assign _dfoo574 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo506 ; - assign _dfoo575 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo439 ; - assign _dfoo576 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo508 ; - assign _dfoo577 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo441 ; - assign _dfoo578 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo510 ; - assign _dfoo579 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo443 ; - assign _dfoo58 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo580 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo512 ; - assign _dfoo581 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo445 ; - assign _dfoo582 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo514 ; - assign _dfoo583 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo447 ; - assign _dfoo584 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo516 ; - assign _dfoo585 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo449 ; - assign _dfoo586 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo518 ; - assign _dfoo587 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo451 ; - assign _dfoo588 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo520 ; - assign _dfoo589 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo453 ; - assign _dfoo59 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo590 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo522 ; - assign _dfoo591 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo455 ; - assign _dfoo592 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo524 ; - assign _dfoo593 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo457 ; - assign _dfoo594 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo526 ; - assign _dfoo595 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo459 ; - assign _dfoo596 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo528 ; - assign _dfoo597 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo461 ; - assign _dfoo598 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo530 ; - assign _dfoo599 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo463 ; - assign _dfoo6 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo60 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo600 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo532 ; - assign _dfoo601 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo465 ; - assign _dfoo602 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo534 ; - assign _dfoo603 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo467 ; - assign _dfoo604 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo536 ; - assign _dfoo605 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo469 ; - assign _dfoo606 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo538 ; - assign _dfoo607 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo471 ; - assign _dfoo608 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo540 ; - assign _dfoo609 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo473 ; - assign _dfoo61 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo610 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo542 ; - assign _dfoo611 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo475 ; - assign _dfoo612 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo544 ; - assign _dfoo614 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo546 ; - assign _dfoo616 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo548 ; - assign _dfoo618 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo550 ; - assign _dfoo62 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo620 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo552 ; - assign _dfoo622 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo554 ; - assign _dfoo624 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo556 ; - assign _dfoo626 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo558 ; - assign _dfoo628 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo560 ; - assign _dfoo63 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo630 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo562 ; - assign _dfoo632 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo564 ; - assign _dfoo634 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo566 ; - assign _dfoo636 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo568 ; - assign _dfoo638 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo570 ; - assign _dfoo64 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo640 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo572 ; - assign _dfoo642 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo574 ; - assign _dfoo644 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo576 ; - assign _dfoo646 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo578 ; - assign _dfoo648 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo580 ; - assign _dfoo65 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo650 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo582 ; - assign _dfoo652 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo584 ; - assign _dfoo654 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo586 ; - assign _dfoo656 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo588 ; - assign _dfoo658 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo590 ; - assign _dfoo66 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo660 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo592 ; - assign _dfoo662 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo594 ; - assign _dfoo664 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo596 ; - assign _dfoo666 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo598 ; - assign _dfoo668 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo600 ; - assign _dfoo67 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo670 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo602 ; - assign _dfoo672 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo604 ; - assign _dfoo674 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo606 ; - assign _dfoo676 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo608 ; - assign _dfoo678 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo610 ; - assign _dfoo68 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo680 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo612 ; - assign _dfoo681 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo545 ; - assign _dfoo682 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo614 ; - assign _dfoo683 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo547 ; - assign _dfoo684 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo616 ; - assign _dfoo685 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo549 ; - assign _dfoo686 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo618 ; - assign _dfoo687 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo551 ; - assign _dfoo688 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo620 ; - assign _dfoo689 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo553 ; - assign _dfoo690 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo622 ; - assign _dfoo691 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo555 ; - assign _dfoo692 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo624 ; - assign _dfoo693 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo557 ; - assign _dfoo694 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo626 ; - assign _dfoo695 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo559 ; - assign _dfoo696 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo628 ; - assign _dfoo697 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo561 ; - assign _dfoo698 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo630 ; - assign _dfoo699 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo563 ; - assign _dfoo7 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo70 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo2 ; - assign _dfoo700 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo632 ; - assign _dfoo701 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo565 ; - assign _dfoo702 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo634 ; - assign _dfoo703 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo567 ; - assign _dfoo704 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo636 ; - assign _dfoo705 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo569 ; - assign _dfoo706 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo638 ; - assign _dfoo707 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo571 ; - assign _dfoo708 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo640 ; - assign _dfoo709 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo573 ; - assign _dfoo710 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo642 ; - assign _dfoo711 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo575 ; - assign _dfoo712 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo644 ; - assign _dfoo713 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo577 ; - assign _dfoo714 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo646 ; - assign _dfoo715 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo579 ; - assign _dfoo716 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo648 ; - assign _dfoo717 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo581 ; - assign _dfoo718 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo650 ; - assign _dfoo719 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo583 ; - assign _dfoo72 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo4 ; - assign _dfoo720 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo652 ; - assign _dfoo721 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo585 ; - assign _dfoo722 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo654 ; - assign _dfoo723 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo587 ; - assign _dfoo724 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo656 ; - assign _dfoo725 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo589 ; - assign _dfoo726 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo658 ; - assign _dfoo727 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo591 ; - assign _dfoo728 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo660 ; - assign _dfoo729 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo593 ; - assign _dfoo730 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo662 ; - assign _dfoo731 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo595 ; - assign _dfoo732 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo664 ; - assign _dfoo733 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo597 ; - assign _dfoo734 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo666 ; - assign _dfoo735 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo599 ; - assign _dfoo736 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo668 ; - assign _dfoo737 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo601 ; - assign _dfoo738 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo670 ; - assign _dfoo739 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo603 ; - assign _dfoo74 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo6 ; - assign _dfoo740 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo672 ; - assign _dfoo741 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo605 ; - assign _dfoo742 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo674 ; - assign _dfoo743 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo607 ; - assign _dfoo744 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo676 ; - assign _dfoo745 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo609 ; - assign _dfoo746 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo678 ; - assign _dfoo747 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo611 ; - assign _dfoo748 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo680 ; - assign _dfoo750 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo682 ; - assign _dfoo752 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo684 ; - assign _dfoo754 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo686 ; - assign _dfoo756 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo688 ; - assign _dfoo758 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo690 ; - assign _dfoo76 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo8 ; - assign _dfoo760 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo692 ; - assign _dfoo762 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo694 ; - assign _dfoo764 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo696 ; - assign _dfoo766 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo698 ; - assign _dfoo768 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo700 ; - assign _dfoo770 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo702 ; - assign _dfoo772 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo704 ; - assign _dfoo774 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo706 ; - assign _dfoo776 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo708 ; - assign _dfoo778 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo710 ; - assign _dfoo78 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo10 ; - assign _dfoo780 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo712 ; - assign _dfoo782 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo714 ; - assign _dfoo784 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo716 ; - assign _dfoo786 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo718 ; - assign _dfoo788 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo720 ; - assign _dfoo790 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo722 ; - assign _dfoo792 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo724 ; - assign _dfoo794 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo726 ; - assign _dfoo796 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo728 ; - assign _dfoo798 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo730 ; - assign _dfoo8 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo80 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo12 ; - assign _dfoo800 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo732 ; - assign _dfoo802 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo734 ; - assign _dfoo804 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo736 ; - assign _dfoo806 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo738 ; - assign _dfoo808 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo740 ; - assign _dfoo810 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo742 ; - assign _dfoo812 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo744 ; - assign _dfoo814 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo746 ; - assign _dfoo816 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo748 ; - assign _dfoo817 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo681 ; - assign _dfoo818 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo750 ; - assign _dfoo819 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo683 ; - assign _dfoo82 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo14 ; - assign _dfoo820 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo752 ; - assign _dfoo821 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo685 ; - assign _dfoo822 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo754 ; - assign _dfoo823 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo687 ; - assign _dfoo824 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo756 ; - assign _dfoo825 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo689 ; - assign _dfoo826 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo758 ; - assign _dfoo827 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo691 ; - assign _dfoo828 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo760 ; - assign _dfoo829 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo693 ; - assign _dfoo830 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo762 ; - assign _dfoo831 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo695 ; - assign _dfoo832 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo764 ; - assign _dfoo833 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo697 ; - assign _dfoo834 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo766 ; - assign _dfoo835 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo699 ; - assign _dfoo836 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo768 ; - assign _dfoo837 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo701 ; - assign _dfoo838 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo770 ; - assign _dfoo839 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo703 ; - assign _dfoo84 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo16 ; - assign _dfoo840 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo772 ; - assign _dfoo841 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo705 ; - assign _dfoo842 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo774 ; - assign _dfoo843 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo707 ; - assign _dfoo844 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo776 ; - assign _dfoo845 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo709 ; - assign _dfoo846 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo778 ; - assign _dfoo847 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo711 ; - assign _dfoo848 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo780 ; - assign _dfoo849 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo713 ; - assign _dfoo850 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo782 ; - assign _dfoo851 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo715 ; - assign _dfoo852 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo784 ; - assign _dfoo853 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo717 ; - assign _dfoo854 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo786 ; - assign _dfoo855 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo719 ; - assign _dfoo856 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo788 ; - assign _dfoo857 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo721 ; - assign _dfoo858 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo790 ; - assign _dfoo859 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo723 ; - assign _dfoo86 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo18 ; - assign _dfoo860 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo792 ; - assign _dfoo861 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo725 ; - assign _dfoo862 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo794 ; - assign _dfoo863 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo727 ; - assign _dfoo864 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo796 ; - assign _dfoo865 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo729 ; - assign _dfoo866 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo798 ; - assign _dfoo867 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo731 ; - assign _dfoo868 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo800 ; - assign _dfoo869 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo733 ; - assign _dfoo870 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo802 ; - assign _dfoo871 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo735 ; - assign _dfoo872 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo804 ; - assign _dfoo873 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo737 ; - assign _dfoo874 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo806 ; - assign _dfoo875 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo739 ; - assign _dfoo876 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo808 ; - assign _dfoo877 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo741 ; - assign _dfoo878 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo810 ; - assign _dfoo879 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo743 ; - assign _dfoo88 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo20 ; - assign _dfoo880 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo812 ; - assign _dfoo881 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo745 ; - assign _dfoo882 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo814 ; - assign _dfoo883 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo747 ; - assign _dfoo884 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo816 ; - assign _dfoo886 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo818 ; - assign _dfoo888 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo820 ; - assign _dfoo890 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo822 ; - assign _dfoo892 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo824 ; - assign _dfoo894 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo826 ; - assign _dfoo896 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo828 ; - assign _dfoo898 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo830 ; - assign _dfoo9 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo90 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo22 ; - assign _dfoo900 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo832 ; - assign _dfoo902 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo834 ; - assign _dfoo904 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo836 ; - assign _dfoo906 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo838 ; - assign _dfoo908 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo840 ; - assign _dfoo910 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo842 ; - assign _dfoo912 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo844 ; - assign _dfoo914 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo846 ; - assign _dfoo916 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo848 ; - assign _dfoo918 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo850 ; - assign _dfoo92 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo24 ; - assign _dfoo920 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo852 ; - assign _dfoo922 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo854 ; - assign _dfoo924 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo856 ; - assign _dfoo926 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo858 ; - assign _dfoo928 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo860 ; - assign _dfoo930 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo862 ; - assign _dfoo932 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo864 ; - assign _dfoo934 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo866 ; - assign _dfoo936 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo868 ; - assign _dfoo938 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo870 ; - assign _dfoo94 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo26 ; - assign _dfoo940 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo872 ; - assign _dfoo942 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo874 ; - assign _dfoo944 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo876 ; - assign _dfoo946 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo878 ; - assign _dfoo948 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo880 ; - assign _dfoo950 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo882 ; - assign _dfoo952 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo884 ; - assign _dfoo953 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo817 ; - assign _dfoo954 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo886 ; - assign _dfoo955 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo819 ; - assign _dfoo956 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo888 ; - assign _dfoo957 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo821 ; - assign _dfoo958 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo890 ; - assign _dfoo959 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo823 ; - assign _dfoo96 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo28 ; - assign _dfoo960 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo892 ; - assign _dfoo961 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo825 ; - assign _dfoo962 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo894 ; - assign _dfoo963 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo827 ; - assign _dfoo964 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo896 ; - assign _dfoo965 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo829 ; - assign _dfoo966 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo898 ; - assign _dfoo967 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo831 ; - assign _dfoo968 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo900 ; - assign _dfoo969 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo833 ; - assign _dfoo970 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo902 ; - assign _dfoo971 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo835 ; - assign _dfoo972 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo904 ; - assign _dfoo973 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo837 ; - assign _dfoo974 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo906 ; - assign _dfoo975 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo839 ; - assign _dfoo976 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo908 ; - assign _dfoo977 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo841 ; - assign _dfoo978 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo910 ; - assign _dfoo979 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo843 ; - assign _dfoo98 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo30 ; - assign _dfoo980 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo912 ; - assign _dfoo981 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo845 ; - assign _dfoo982 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo914 ; - assign _dfoo983 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo847 ; - assign _dfoo984 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo916 ; - assign _dfoo985 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo849 ; - assign _dfoo986 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo918 ; - assign _dfoo987 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo851 ; - assign _dfoo988 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo920 ; - assign _dfoo989 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo853 ; - assign _dfoo990 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo922 ; - assign _dfoo991 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo855 ; - assign _dfoo992 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo924 ; - assign _dfoo993 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo857 ; - assign _dfoo994 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo926 ; - assign _dfoo995 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo859 ; - assign _dfoo996 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo928 ; - assign _dfoo997 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo861 ; - assign _dfoo998 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo930 ; - assign _dfoo999 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo863 ; - assign a__h71312 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73317 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; - assign addr_offset__h13216 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26929 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71313 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73318 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = - addr_offset__h13216 < 64'h0000000000003000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = - addr_offset__h13216[11:7] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 = - addr_offset__h13216 < 64'h0000000000001000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 = - addr_offset__h13216[11:2] <= 10'd16 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 = - addr_offset__h13216[16:12] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 = - addr_offset__h13216 < 64'h0000000000002000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = - source_id_base__h13630 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26929[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26929[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26929[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26929 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26929[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26929[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26929[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26929[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26929[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26929[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26929[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26929[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26929[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26929[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26929[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26929[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26929[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26929[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26929[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26929[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26929[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26929 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28148 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26929 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26929[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26929[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26929[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && - m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && - m_vvrg_ie_1_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && - m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && - m_vvrg_ie_1_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && - m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && - m_vvrg_ie_1_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && - m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && - m_vvrg_ie_1_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 || - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 || - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 || - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 || - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && - m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && - m_vvrg_ie_1_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && - m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && - m_vvrg_ie_1_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && - m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && - m_vvrg_ie_1_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = - m_vrg_source_ip_16 && - !m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 || - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 || - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 || - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 ; - assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = - m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && - m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && - m_vvrg_ie_1_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && - m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && - m_vvrg_ie_1_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && - m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && - m_vvrg_ie_1_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && - m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && - m_vvrg_ie_1_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && - m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && - m_vvrg_ie_1_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && - m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && - m_vvrg_ie_1_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 || - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 || - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 || - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 || - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && - m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && - m_vvrg_ie_1_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && - m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && - m_vvrg_ie_1_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; - assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 = - m_vrg_source_prio_16 <= - (m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ; - assign max_id__h23959 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ; - assign rdata___1__h26404 = { rdata__h26202[31:0], 32'h0 } ; - assign rdata__h26202 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 64'd0 : - y_avValue_fst__h26194 ; - assign rresp__h26203 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 2'b11 : - y_avValue_snd__h26195 ; - assign source_id__h15665 = { addr_offset__h13216[4:0], 5'd31 } ; - assign source_id__h15772 = { addr_offset__h13216[4:0], 5'd30 } ; - assign source_id__h15845 = { addr_offset__h13216[4:0], 5'd29 } ; - assign source_id__h15918 = { addr_offset__h13216[4:0], 5'd28 } ; - assign source_id__h15991 = { addr_offset__h13216[4:0], 5'd27 } ; - assign source_id__h16064 = { addr_offset__h13216[4:0], 5'd26 } ; - assign source_id__h16137 = { addr_offset__h13216[4:0], 5'd25 } ; - assign source_id__h16210 = { addr_offset__h13216[4:0], 5'd24 } ; - assign source_id__h16283 = { addr_offset__h13216[4:0], 5'd23 } ; - assign source_id__h16356 = { addr_offset__h13216[4:0], 5'd22 } ; - assign source_id__h16429 = { addr_offset__h13216[4:0], 5'd21 } ; - assign source_id__h16502 = { addr_offset__h13216[4:0], 5'd20 } ; - assign source_id__h16575 = { addr_offset__h13216[4:0], 5'd19 } ; - assign source_id__h16648 = { addr_offset__h13216[4:0], 5'd18 } ; - assign source_id__h16721 = { addr_offset__h13216[4:0], 5'd17 } ; - assign source_id__h16794 = { addr_offset__h13216[4:0], 5'd16 } ; - assign source_id__h16867 = { addr_offset__h13216[4:0], 5'd15 } ; - assign source_id__h16940 = { addr_offset__h13216[4:0], 5'd14 } ; - assign source_id__h17013 = { addr_offset__h13216[4:0], 5'd13 } ; - assign source_id__h17086 = { addr_offset__h13216[4:0], 5'd12 } ; - assign source_id__h17159 = { addr_offset__h13216[4:0], 5'd11 } ; - assign source_id__h17232 = { addr_offset__h13216[4:0], 5'd10 } ; - assign source_id__h17305 = { addr_offset__h13216[4:0], 5'd9 } ; - assign source_id__h17378 = { addr_offset__h13216[4:0], 5'd8 } ; - assign source_id__h17451 = { addr_offset__h13216[4:0], 5'd7 } ; - assign source_id__h17524 = { addr_offset__h13216[4:0], 5'd6 } ; - assign source_id__h17597 = { addr_offset__h13216[4:0], 5'd5 } ; - assign source_id__h17670 = { addr_offset__h13216[4:0], 5'd4 } ; - assign source_id__h17743 = { addr_offset__h13216[4:0], 5'd3 } ; - assign source_id__h17816 = { addr_offset__h13216[4:0], 5'd2 } ; - assign source_id__h17889 = { addr_offset__h13216[4:0], 5'd1 } ; - assign source_id__h20137 = 10'd31 + source_id_base__h13630 ; - assign source_id__h20313 = 10'd30 + source_id_base__h13630 ; - assign source_id__h20421 = 10'd29 + source_id_base__h13630 ; - assign source_id__h20529 = 10'd28 + source_id_base__h13630 ; - assign source_id__h20637 = 10'd27 + source_id_base__h13630 ; - assign source_id__h20745 = 10'd26 + source_id_base__h13630 ; - assign source_id__h20853 = 10'd25 + source_id_base__h13630 ; - assign source_id__h20961 = 10'd24 + source_id_base__h13630 ; - assign source_id__h21069 = 10'd23 + source_id_base__h13630 ; - assign source_id__h21177 = 10'd22 + source_id_base__h13630 ; - assign source_id__h21285 = 10'd21 + source_id_base__h13630 ; - assign source_id__h21393 = 10'd20 + source_id_base__h13630 ; - assign source_id__h21501 = 10'd19 + source_id_base__h13630 ; - assign source_id__h21609 = 10'd18 + source_id_base__h13630 ; - assign source_id__h21717 = 10'd17 + source_id_base__h13630 ; - assign source_id__h21825 = 10'd16 + source_id_base__h13630 ; - assign source_id__h21933 = 10'd15 + source_id_base__h13630 ; - assign source_id__h22041 = 10'd14 + source_id_base__h13630 ; - assign source_id__h22149 = 10'd13 + source_id_base__h13630 ; - assign source_id__h22257 = 10'd12 + source_id_base__h13630 ; - assign source_id__h22365 = 10'd11 + source_id_base__h13630 ; - assign source_id__h22473 = 10'd10 + source_id_base__h13630 ; - assign source_id__h22581 = 10'd9 + source_id_base__h13630 ; - assign source_id__h22689 = 10'd8 + source_id_base__h13630 ; - assign source_id__h22797 = 10'd7 + source_id_base__h13630 ; - assign source_id__h22905 = 10'd6 + source_id_base__h13630 ; - assign source_id__h23013 = 10'd5 + source_id_base__h13630 ; - assign source_id__h23121 = 10'd4 + source_id_base__h13630 ; - assign source_id__h23229 = 10'd3 + source_id_base__h13630 ; - assign source_id__h23337 = 10'd2 + source_id_base__h13630 ; - assign source_id__h23445 = 10'd1 + source_id_base__h13630 ; - assign source_id__h29475 = { addr_offset__h26929[4:0], 5'd1 } ; - assign source_id__h30685 = { addr_offset__h26929[4:0], 5'd2 } ; - assign source_id__h31895 = { addr_offset__h26929[4:0], 5'd3 } ; - assign source_id__h33105 = { addr_offset__h26929[4:0], 5'd4 } ; - assign source_id__h34315 = { addr_offset__h26929[4:0], 5'd5 } ; - assign source_id__h35525 = { addr_offset__h26929[4:0], 5'd6 } ; - assign source_id__h36735 = { addr_offset__h26929[4:0], 5'd7 } ; - assign source_id__h37945 = { addr_offset__h26929[4:0], 5'd8 } ; - assign source_id__h39155 = { addr_offset__h26929[4:0], 5'd9 } ; - assign source_id__h40365 = { addr_offset__h26929[4:0], 5'd10 } ; - assign source_id__h41575 = { addr_offset__h26929[4:0], 5'd11 } ; - assign source_id__h42785 = { addr_offset__h26929[4:0], 5'd12 } ; - assign source_id__h43995 = { addr_offset__h26929[4:0], 5'd13 } ; - assign source_id__h45205 = { addr_offset__h26929[4:0], 5'd14 } ; - assign source_id__h46415 = { addr_offset__h26929[4:0], 5'd15 } ; - assign source_id__h47625 = { addr_offset__h26929[4:0], 5'd16 } ; - assign source_id__h48835 = { addr_offset__h26929[4:0], 5'd17 } ; - assign source_id__h50045 = { addr_offset__h26929[4:0], 5'd18 } ; - assign source_id__h51255 = { addr_offset__h26929[4:0], 5'd19 } ; - assign source_id__h52465 = { addr_offset__h26929[4:0], 5'd20 } ; - assign source_id__h53675 = { addr_offset__h26929[4:0], 5'd21 } ; - assign source_id__h54885 = { addr_offset__h26929[4:0], 5'd22 } ; - assign source_id__h56095 = { addr_offset__h26929[4:0], 5'd23 } ; - assign source_id__h57305 = { addr_offset__h26929[4:0], 5'd24 } ; - assign source_id__h58515 = { addr_offset__h26929[4:0], 5'd25 } ; - assign source_id__h59725 = { addr_offset__h26929[4:0], 5'd26 } ; - assign source_id__h60935 = { addr_offset__h26929[4:0], 5'd27 } ; - assign source_id__h62145 = { addr_offset__h26929[4:0], 5'd28 } ; - assign source_id__h63355 = { addr_offset__h26929[4:0], 5'd29 } ; - assign source_id__h64565 = { addr_offset__h26929[4:0], 5'd30 } ; - assign source_id__h65775 = { addr_offset__h26929[4:0], 5'd31 } ; - assign source_id__h67436 = { 5'd0, x__h67487 } ; - assign source_id_base__h13630 = { addr_offset__h13216[4:0], 5'h0 } ; - assign source_id_base__h28148 = { addr_offset__h26929[4:0], 5'h0 } ; - assign v__h13422 = { 61'd0, x__h13493 } ; - assign v__h13671 = { 32'd0, v_ip__h13674 } ; - assign v__h18144 = { 32'd0, v_ie__h18147 } ; - assign v__h23761 = { 61'd0, x__h23832 } ; - assign v__h25455 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ? - v__h25474 : - 64'd0 ; - assign v__h25474 = { 59'd0, max_id__h23959 } ; - assign v__h26934 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? - 2'b11 : - v__h27094 ; - assign v__h27094 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27107 : - v__h27942 ; - assign v__h27107 = - (addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? - 2'b0 : - 2'b10 ; - assign v__h27942 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27961 : - v__h28125 ; - assign v__h27961 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? - 2'b0 : - 2'b10 ; - assign v__h28125 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28144 : - v__h67107 ; - assign v__h28144 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? - 2'b0 : - 2'b10 ; - assign v__h67144 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - 2'b0 : - 2'b10 ; - assign v__h67432 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67476 : - 2'b10 ; - assign v__h67476 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? - 2'b0 : - 2'b10 ; - assign v_ie__h18147 = - { source_id__h20137 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h20313 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h20421 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h20529 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h20637 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h20745 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h20853 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h20961 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h21069 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h21177 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h21285 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h21393 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h21501 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h21609 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h21717 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h21825 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h21933 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h22041 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h22149 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h22257 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h22365 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h22473 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h22581 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h22689 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h22797 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h22905 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h23013 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h23121 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h23229 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h23337 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h23445 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h13674 = - { source_id__h15665 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - source_id__h15772 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - source_id__h15845 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - source_id__h15918 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - source_id__h15991 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - source_id__h16064 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - source_id__h16137 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - source_id__h16210 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - source_id__h16283 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - source_id__h16356 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - source_id__h16429 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - source_id__h16502 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - source_id__h16575 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - source_id__h16648 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - source_id__h16721 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - source_id__h16794 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - source_id__h16867 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - source_id__h16940 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - source_id__h17013 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - source_id__h17086 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - source_id__h17159 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - source_id__h17232 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - source_id__h17305 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - source_id__h17378 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - source_id__h17451 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - source_id__h17524 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - source_id__h17597 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - source_id__h17670 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - source_id__h17743 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - source_id__h17816 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - source_id__h17889 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26930 = - (addr_offset__h26929[2:0] == 3'd4) ? - m_slave_xactor_f_wr_data$D_OUT[72:41] : - m_slave_xactor_f_wr_data$D_OUT[40:9] ; - assign x__h23673 = - { addr_offset__h13216[31:16], 4'd0, addr_offset__h13216[11:0] } ; - assign x__h26361 = - (addr_offset__h13216[2:0] == 3'd4) ? - rdata___1__h26404 : - rdata__h26202 ; - assign x__h67110 = - { addr_offset__h26929[31:16], 4'd0, addr_offset__h26929[11:0] } ; - assign y_avValue_fst__h26094 = (x__h24011 == 5'd0) ? v__h25455 : 64'd0 ; - assign y_avValue_fst__h26115 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_fst__h26094 : - 64'd0 ; - assign y_avValue_fst__h26127 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - v__h23761 : - 64'd0 ; - assign y_avValue_fst__h26143 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - v__h18144 : - 64'd0 ; - assign y_avValue_fst__h26159 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - v__h13671 : - 64'd0 ; - assign y_avValue_fst__h26164 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_fst__h26143 : - y_avValue_fst__h26148 ; - assign y_avValue_fst__h26175 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - v__h13422 : - 64'd0 ; - assign y_avValue_fst__h26180 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_fst__h26159 : - y_avValue_fst__h26164 ; - assign y_avValue_fst__h26194 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_fst__h26175 : - y_avValue_fst__h26180 ; - assign y_avValue_snd__h26095 = (x__h24011 == 5'd0) ? 2'b0 : 2'b10 ; - assign y_avValue_snd__h26116 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_snd__h26095 : - 2'b10 ; - assign y_avValue_snd__h26128 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26144 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26160 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26165 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_snd__h26144 : - y_avValue_snd__h26149 ; - assign y_avValue_snd__h26176 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26181 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_snd__h26160 : - y_avValue_snd__h26165 ; - assign y_avValue_snd__h26195 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_snd__h26176 : - y_avValue_snd__h26181 ; - always@(addr_offset__h13216 or - m_vrg_source_prio_0 or - m_vrg_source_prio_1 or - m_vrg_source_prio_2 or - m_vrg_source_prio_3 or - m_vrg_source_prio_4 or - m_vrg_source_prio_5 or - m_vrg_source_prio_6 or - m_vrg_source_prio_7 or - m_vrg_source_prio_8 or - m_vrg_source_prio_9 or - m_vrg_source_prio_10 or - m_vrg_source_prio_11 or - m_vrg_source_prio_12 or - m_vrg_source_prio_13 or - m_vrg_source_prio_14 or - m_vrg_source_prio_15 or m_vrg_source_prio_16) - begin - case (addr_offset__h13216[11:2]) - 10'd0: x__h13493 = m_vrg_source_prio_0; - 10'd1: x__h13493 = m_vrg_source_prio_1; - 10'd2: x__h13493 = m_vrg_source_prio_2; - 10'd3: x__h13493 = m_vrg_source_prio_3; - 10'd4: x__h13493 = m_vrg_source_prio_4; - 10'd5: x__h13493 = m_vrg_source_prio_5; - 10'd6: x__h13493 = m_vrg_source_prio_6; - 10'd7: x__h13493 = m_vrg_source_prio_7; - 10'd8: x__h13493 = m_vrg_source_prio_8; - 10'd9: x__h13493 = m_vrg_source_prio_9; - 10'd10: x__h13493 = m_vrg_source_prio_10; - 10'd11: x__h13493 = m_vrg_source_prio_11; - 10'd12: x__h13493 = m_vrg_source_prio_12; - 10'd13: x__h13493 = m_vrg_source_prio_13; - 10'd14: x__h13493 = m_vrg_source_prio_14; - 10'd15: x__h13493 = m_vrg_source_prio_15; - 10'd16: x__h13493 = m_vrg_source_prio_16; - default: x__h13493 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_target_threshold_0 or m_vrg_target_threshold_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h23832 = m_vrg_target_threshold_0; - 5'd1: x__h23832 = m_vrg_target_threshold_1; - default: x__h23832 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h24011 = m_vrg_servicing_source_0; - 5'd1: x__h24011 = m_vrg_servicing_source_1; - default: x__h24011 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h26929 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h26929[16:12]) - 5'd0: x__h67487 = m_vrg_servicing_source_0; - 5'd1: x__h67487 = m_vrg_servicing_source_1; - default: x__h67487 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15665 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15665) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15772 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15772) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15845 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15845) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15918 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15918) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15991 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15991) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16064 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16064) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17159 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17159) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16137 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16137) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16210 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16210) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16283 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16283) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16356 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16356) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16429 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16429) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16502 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16502) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16575 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16575) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16648 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16648) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16721 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16721) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16794 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16794) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16867 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16867) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16940 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16940) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17013 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17013) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17086 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17086) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17232 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17232) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17305 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17305) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17378 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17378) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17451 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17451) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17524 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17524) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17597 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17597) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17670 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17670) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17743 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17743) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17889 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17889) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17816 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17816) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_snd__h26128 or y_avValue_snd__h26116) - begin - case (x__h23673) - 32'h00200000: y_avValue_snd__h26149 = y_avValue_snd__h26128; - 32'h00200004: y_avValue_snd__h26149 = y_avValue_snd__h26116; - default: y_avValue_snd__h26149 = 2'b10; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_0_1; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_1_1; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_0_2; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_1_2; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_0_3; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_1_3; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_0_4; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_1_4; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_0_5; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_1_5; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_0_6; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_1_6; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_0_7; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_1_7; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_0_8; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_1_8; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_0_9; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_1_9; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_0_10; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_1_10; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_0_11; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_1_11; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_0_12; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_1_12; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_0_13; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_1_13; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_0_14; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_1_14; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_0_15; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_1_15; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_0_16; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_1_16; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_fst__h26127 or y_avValue_fst__h26115) - begin - case (x__h23673) - 32'h00200000: y_avValue_fst__h26148 = y_avValue_fst__h26127; - 32'h00200004: y_avValue_fst__h26148 = y_avValue_fst__h26115; - default: y_avValue_fst__h26148 = 64'd0; - endcase - end - always@(source_id__h67436 or - m_vrg_source_busy_0 or - m_vrg_source_busy_1 or - m_vrg_source_busy_2 or - m_vrg_source_busy_3 or - m_vrg_source_busy_4 or - m_vrg_source_busy_5 or - m_vrg_source_busy_6 or - m_vrg_source_busy_7 or - m_vrg_source_busy_8 or - m_vrg_source_busy_9 or - m_vrg_source_busy_10 or - m_vrg_source_busy_11 or - m_vrg_source_busy_12 or - m_vrg_source_busy_13 or - m_vrg_source_busy_14 or - m_vrg_source_busy_15 or m_vrg_source_busy_16) - begin - case (source_id__h67436) - 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_0; - 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_1; - 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_2; - 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_3; - 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_4; - 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_5; - 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_6; - 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_7; - 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_8; - 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_9; - 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_10; - 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_11; - 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_12; - 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_13; - 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_14; - 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_15; - 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h67110 or v__h67144 or v__h67432) - begin - case (x__h67110) - 32'h00200000: v__h67107 = v__h67144; - 32'h00200004: v__h67107 = v__h67432; - default: v__h67107 = 2'b10; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_cfg_verbosity$EN) - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN; - if (m_vrg_servicing_source_0$EN) - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_0$D_IN; - if (m_vrg_servicing_source_1$EN) - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_1$D_IN; - if (m_vrg_source_busy_0$EN) - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_0$D_IN; - if (m_vrg_source_busy_1$EN) - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_1$D_IN; - if (m_vrg_source_busy_10$EN) - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_10$D_IN; - if (m_vrg_source_busy_11$EN) - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_11$D_IN; - if (m_vrg_source_busy_12$EN) - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_12$D_IN; - if (m_vrg_source_busy_13$EN) - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_13$D_IN; - if (m_vrg_source_busy_14$EN) - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_14$D_IN; - if (m_vrg_source_busy_15$EN) - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_15$D_IN; - if (m_vrg_source_busy_16$EN) - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_16$D_IN; - if (m_vrg_source_busy_2$EN) - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_2$D_IN; - if (m_vrg_source_busy_3$EN) - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_3$D_IN; - if (m_vrg_source_busy_4$EN) - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_4$D_IN; - if (m_vrg_source_busy_5$EN) - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_5$D_IN; - if (m_vrg_source_busy_6$EN) - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_6$D_IN; - if (m_vrg_source_busy_7$EN) - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_7$D_IN; - if (m_vrg_source_busy_8$EN) - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_8$D_IN; - if (m_vrg_source_busy_9$EN) - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_9$D_IN; - if (m_vrg_source_ip_0$EN) - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_0$D_IN; - if (m_vrg_source_ip_1$EN) - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_1$D_IN; - if (m_vrg_source_ip_10$EN) - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_10$D_IN; - if (m_vrg_source_ip_11$EN) - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_11$D_IN; - if (m_vrg_source_ip_12$EN) - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_12$D_IN; - if (m_vrg_source_ip_13$EN) - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_13$D_IN; - if (m_vrg_source_ip_14$EN) - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_14$D_IN; - if (m_vrg_source_ip_15$EN) - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_15$D_IN; - if (m_vrg_source_ip_16$EN) - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_16$D_IN; - if (m_vrg_source_ip_2$EN) - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_2$D_IN; - if (m_vrg_source_ip_3$EN) - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_3$D_IN; - if (m_vrg_source_ip_4$EN) - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_4$D_IN; - if (m_vrg_source_ip_5$EN) - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_5$D_IN; - if (m_vrg_source_ip_6$EN) - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_6$D_IN; - if (m_vrg_source_ip_7$EN) - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_7$D_IN; - if (m_vrg_source_ip_8$EN) - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_8$D_IN; - if (m_vrg_source_ip_9$EN) - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_9$D_IN; - if (m_vrg_source_prio_0$EN) - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_0$D_IN; - if (m_vrg_source_prio_1$EN) - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_1$D_IN; - if (m_vrg_source_prio_10$EN) - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_10$D_IN; - if (m_vrg_source_prio_11$EN) - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_11$D_IN; - if (m_vrg_source_prio_12$EN) - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_12$D_IN; - if (m_vrg_source_prio_13$EN) - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_13$D_IN; - if (m_vrg_source_prio_14$EN) - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_14$D_IN; - if (m_vrg_source_prio_15$EN) - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_15$D_IN; - if (m_vrg_source_prio_16$EN) - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_16$D_IN; - if (m_vrg_source_prio_2$EN) - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_2$D_IN; - if (m_vrg_source_prio_3$EN) - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_3$D_IN; - if (m_vrg_source_prio_4$EN) - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_4$D_IN; - if (m_vrg_source_prio_5$EN) - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_5$D_IN; - if (m_vrg_source_prio_6$EN) - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_6$D_IN; - if (m_vrg_source_prio_7$EN) - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_7$D_IN; - if (m_vrg_source_prio_8$EN) - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_8$D_IN; - if (m_vrg_source_prio_9$EN) - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_9$D_IN; - if (m_vrg_target_threshold_0$EN) - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_0$D_IN; - if (m_vrg_target_threshold_1$EN) - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_1$D_IN; - if (m_vvrg_ie_0_0$EN) - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_0$D_IN; - if (m_vvrg_ie_0_1$EN) - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_1$D_IN; - if (m_vvrg_ie_0_10$EN) - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_10$D_IN; - if (m_vvrg_ie_0_11$EN) - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_11$D_IN; - if (m_vvrg_ie_0_12$EN) - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_12$D_IN; - if (m_vvrg_ie_0_13$EN) - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_13$D_IN; - if (m_vvrg_ie_0_14$EN) - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_14$D_IN; - if (m_vvrg_ie_0_15$EN) - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_15$D_IN; - if (m_vvrg_ie_0_16$EN) - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_16$D_IN; - if (m_vvrg_ie_0_2$EN) - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_2$D_IN; - if (m_vvrg_ie_0_3$EN) - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_3$D_IN; - if (m_vvrg_ie_0_4$EN) - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_4$D_IN; - if (m_vvrg_ie_0_5$EN) - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_5$D_IN; - if (m_vvrg_ie_0_6$EN) - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_6$D_IN; - if (m_vvrg_ie_0_7$EN) - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_7$D_IN; - if (m_vvrg_ie_0_8$EN) - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_8$D_IN; - if (m_vvrg_ie_0_9$EN) - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_9$D_IN; - if (m_vvrg_ie_1_0$EN) - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_0$D_IN; - if (m_vvrg_ie_1_1$EN) - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_1$D_IN; - if (m_vvrg_ie_1_10$EN) - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_10$D_IN; - if (m_vvrg_ie_1_11$EN) - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_11$D_IN; - if (m_vvrg_ie_1_12$EN) - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_12$D_IN; - if (m_vvrg_ie_1_13$EN) - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_13$D_IN; - if (m_vvrg_ie_1_14$EN) - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_14$D_IN; - if (m_vvrg_ie_1_15$EN) - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_15$D_IN; - if (m_vvrg_ie_1_16$EN) - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_16$D_IN; - if (m_vvrg_ie_1_2$EN) - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_2$D_IN; - if (m_vvrg_ie_1_3$EN) - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_3$D_IN; - if (m_vvrg_ie_1_4$EN) - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_4$D_IN; - if (m_vvrg_ie_1_5$EN) - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_5$D_IN; - if (m_vvrg_ie_1_6$EN) - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_6$D_IN; - if (m_vvrg_ie_1_7$EN) - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_7$D_IN; - if (m_vvrg_ie_1_8$EN) - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_8$D_IN; - if (m_vvrg_ie_1_9$EN) - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_9$D_IN; - end - if (m_rg_addr_base$EN) - m_rg_addr_base <= `BSV_ASSIGNMENT_DELAY m_rg_addr_base$D_IN; - if (m_rg_addr_lim$EN) - m_rg_addr_lim <= `BSV_ASSIGNMENT_DELAY m_rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_cfg_verbosity = 4'hA; - m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - m_vrg_servicing_source_0 = 5'h0A; - m_vrg_servicing_source_1 = 5'h0A; - m_vrg_source_busy_0 = 1'h0; - m_vrg_source_busy_1 = 1'h0; - m_vrg_source_busy_10 = 1'h0; - m_vrg_source_busy_11 = 1'h0; - m_vrg_source_busy_12 = 1'h0; - m_vrg_source_busy_13 = 1'h0; - m_vrg_source_busy_14 = 1'h0; - m_vrg_source_busy_15 = 1'h0; - m_vrg_source_busy_16 = 1'h0; - m_vrg_source_busy_2 = 1'h0; - m_vrg_source_busy_3 = 1'h0; - m_vrg_source_busy_4 = 1'h0; - m_vrg_source_busy_5 = 1'h0; - m_vrg_source_busy_6 = 1'h0; - m_vrg_source_busy_7 = 1'h0; - m_vrg_source_busy_8 = 1'h0; - m_vrg_source_busy_9 = 1'h0; - m_vrg_source_ip_0 = 1'h0; - m_vrg_source_ip_1 = 1'h0; - m_vrg_source_ip_10 = 1'h0; - m_vrg_source_ip_11 = 1'h0; - m_vrg_source_ip_12 = 1'h0; - m_vrg_source_ip_13 = 1'h0; - m_vrg_source_ip_14 = 1'h0; - m_vrg_source_ip_15 = 1'h0; - m_vrg_source_ip_16 = 1'h0; - m_vrg_source_ip_2 = 1'h0; - m_vrg_source_ip_3 = 1'h0; - m_vrg_source_ip_4 = 1'h0; - m_vrg_source_ip_5 = 1'h0; - m_vrg_source_ip_6 = 1'h0; - m_vrg_source_ip_7 = 1'h0; - m_vrg_source_ip_8 = 1'h0; - m_vrg_source_ip_9 = 1'h0; - m_vrg_source_prio_0 = 3'h2; - m_vrg_source_prio_1 = 3'h2; - m_vrg_source_prio_10 = 3'h2; - m_vrg_source_prio_11 = 3'h2; - m_vrg_source_prio_12 = 3'h2; - m_vrg_source_prio_13 = 3'h2; - m_vrg_source_prio_14 = 3'h2; - m_vrg_source_prio_15 = 3'h2; - m_vrg_source_prio_16 = 3'h2; - m_vrg_source_prio_2 = 3'h2; - m_vrg_source_prio_3 = 3'h2; - m_vrg_source_prio_4 = 3'h2; - m_vrg_source_prio_5 = 3'h2; - m_vrg_source_prio_6 = 3'h2; - m_vrg_source_prio_7 = 3'h2; - m_vrg_source_prio_8 = 3'h2; - m_vrg_source_prio_9 = 3'h2; - m_vrg_target_threshold_0 = 3'h2; - m_vrg_target_threshold_1 = 3'h2; - m_vvrg_ie_0_0 = 1'h0; - m_vvrg_ie_0_1 = 1'h0; - m_vvrg_ie_0_10 = 1'h0; - m_vvrg_ie_0_11 = 1'h0; - m_vvrg_ie_0_12 = 1'h0; - m_vvrg_ie_0_13 = 1'h0; - m_vvrg_ie_0_14 = 1'h0; - m_vvrg_ie_0_15 = 1'h0; - m_vvrg_ie_0_16 = 1'h0; - m_vvrg_ie_0_2 = 1'h0; - m_vvrg_ie_0_3 = 1'h0; - m_vvrg_ie_0_4 = 1'h0; - m_vvrg_ie_0_5 = 1'h0; - m_vvrg_ie_0_6 = 1'h0; - m_vvrg_ie_0_7 = 1'h0; - m_vvrg_ie_0_8 = 1'h0; - m_vvrg_ie_0_9 = 1'h0; - m_vvrg_ie_1_0 = 1'h0; - m_vvrg_ie_1_1 = 1'h0; - m_vvrg_ie_1_10 = 1'h0; - m_vvrg_ie_1_11 = 1'h0; - m_vvrg_ie_1_12 = 1'h0; - m_vvrg_ie_1_13 = 1'h0; - m_vvrg_ie_1_14 = 1'h0; - m_vvrg_ie_1_15 = 1'h0; - m_vvrg_ie_1_16 = 1'h0; - m_vvrg_ie_1_2 = 1'h0; - m_vvrg_ie_1_3 = 1'h0; - m_vvrg_ie_1_4 = 1'h0; - m_vvrg_ie_1_5 = 1'h0; - m_vvrg_ie_1_6 = 1'h0; - m_vvrg_ie_1_7 = 1'h0; - m_vvrg_ie_1_8 = 1'h0; - m_vvrg_ie_1_9 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src IPs :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src Prios:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src busy :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71312, - m_vrg_target_threshold_0, - b__h71313, - m_vrg_servicing_source_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73317, - m_vrg_target_threshold_1, - b__h73318, - m_vrg_servicing_source_1); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - begin - v__h75676 = $stime; - #0; - end - v__h75670 = v__h75676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75670, - $signed(32'd1), - v_sources_0_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - begin - v__h75874 = $stime; - #0; - end - v__h75868 = v__h75874 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75868, - $signed(32'd2), - v_sources_1_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - begin - v__h76072 = $stime; - #0; - end - v__h76066 = v__h76072 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76066, - $signed(32'd3), - v_sources_2_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - begin - v__h76270 = $stime; - #0; - end - v__h76264 = v__h76270 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76264, - $signed(32'd4), - v_sources_3_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - begin - v__h76468 = $stime; - #0; - end - v__h76462 = v__h76468 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76462, - $signed(32'd5), - v_sources_4_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - begin - v__h76666 = $stime; - #0; - end - v__h76660 = v__h76666 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76660, - $signed(32'd6), - v_sources_5_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - begin - v__h76864 = $stime; - #0; - end - v__h76858 = v__h76864 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76858, - $signed(32'd7), - v_sources_6_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - begin - v__h77062 = $stime; - #0; - end - v__h77056 = v__h77062 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77056, - $signed(32'd8), - v_sources_7_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - begin - v__h77260 = $stime; - #0; - end - v__h77254 = v__h77260 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77254, - $signed(32'd9), - v_sources_8_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - begin - v__h77458 = $stime; - #0; - end - v__h77452 = v__h77458 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77452, - $signed(32'd10), - v_sources_9_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - begin - v__h77656 = $stime; - #0; - end - v__h77650 = v__h77656 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77650, - $signed(32'd11), - v_sources_10_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - begin - v__h77854 = $stime; - #0; - end - v__h77848 = v__h77854 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77848, - $signed(32'd12), - v_sources_11_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - begin - v__h78052 = $stime; - #0; - end - v__h78046 = v__h78052 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78046, - $signed(32'd13), - v_sources_12_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - begin - v__h78250 = $stime; - #0; - end - v__h78244 = v__h78250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78244, - $signed(32'd14), - v_sources_13_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - begin - v__h78448 = $stime; - #0; - end - v__h78442 = v__h78448 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78442, - $signed(32'd15), - v_sources_14_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - begin - v__h78646 = $stime; - #0; - end - v__h78640 = v__h78646 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78640, - $signed(32'd16), - v_sources_15_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - begin - v__h6144 = $stime; - #0; - end - v__h6138 = v__h6144 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h6138); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h13080 = $stime; - #0; - end - v__h13074 = v__h13080 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req:", v__h13074); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - begin - v__h13265 = $stime; - #0; - end - v__h13259 = v__h13265 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h13259); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - begin - v__h13463 = $stime; - #0; - end - v__h13457 = v__h13463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h13457, - addr_offset__h13216[11:2], - v__h13422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - begin - v__h13713 = $stime; - #0; - end - v__h13707 = v__h13713 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h13707, - source_id_base__h13630, - v__h13671); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - begin - v__h18186 = $stime; - #0; - end - v__h18180 = v__h18186 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h18180, - source_id_base__h13630, - v__h18144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - begin - v__h23802 = $stime; - #0; - end - v__h23796 = v__h23802 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h23796, - addr_offset__h13216[16:12], - v__h23761); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - begin - v__h25975 = $stime; - #0; - end - v__h25969 = v__h25975 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h25969, - addr_offset__h13216[16:12], - v__h25474); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - begin - v__h24056 = $stime; - #0; - end - v__h24050 = v__h24056 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h24050, - addr_offset__h13216[16:12]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Still servicing interrupt from source %0d", x__h24011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Trying to claim service for source %0d", - max_id__h23959); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Ignoring."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - begin - v__h26250 = $stime; - #0; - end - v__h26244 = v__h26250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h26244); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26463 = $stime; - #0; - end - v__h26457 = v__h26463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req", v__h26457); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", x__h26361); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", rresp__h26203); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26740 = $stime; - #0; - end - v__h26734 = v__h26740 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26734); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - begin - v__h26968 = $stime; - #0; - end - v__h26962 = v__h26968 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26962); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - begin - v__h27865 = $stime; - #0; - end - v__h27859 = v__h27865 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27859, - addr_offset__h26929[11:2], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - begin - v__h28048 = $stime; - #0; - end - v__h28042 = v__h28048 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28042, - source_id_base__h28148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - begin - v__h67030 = $stime; - #0; - end - v__h67024 = v__h67030 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67024, - addr_offset__h26929[11:7], - source_id_base__h28148, - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - begin - v__h67318 = $stime; - #0; - end - v__h67312 = v__h67318 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67312, - addr_offset__h26929[16:12], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - begin - v__h67847 = $stime; - #0; - end - v__h67841 = v__h67847 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67841, - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - begin - v__h67933 = $stime; - #0; - end - v__h67927 = v__h67933 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67927); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Completion message from target %0d to source %0d", - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Ignoring"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - begin - v__h68132 = $stime; - #0; - end - v__h68126 = v__h68132 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68126); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h68353 = $stime; - #0; - end - v__h68347 = v__h68353 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68347); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26934); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h74690 = $stime; - #0; - end - v__h74684 = v__h74690 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74684, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h74800 = $stime; - #0; - end - v__h74794 = v__h74800 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74794, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - begin - v__h74913 = $stime; - #0; - end - v__h74907 = v__h74913 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74907, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkPLIC_16_2_7 - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v deleted file mode 100644 index f852a5f3..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkRISCV_MBox.v +++ /dev/null @@ -1,734 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_req_reset O 1 const -// RDY_rsp_reset O 1 const -// valid O 1 -// word O 64 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_is_OP_not_OP_32 I 1 -// req_f3 I 3 -// req_v1 I 64 -// req_v2 I 64 -// EN_set_verbosity I 1 -// EN_req_reset I 1 unused -// EN_rsp_reset I 1 unused -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkRISCV_MBox(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_req_reset, - RDY_req_reset, - - EN_rsp_reset, - RDY_rsp_reset, - - req_is_OP_not_OP_32, - req_f3, - req_v1, - req_v2, - EN_req, - - valid, - - word); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method req_reset - input EN_req_reset; - output RDY_req_reset; - - // action method rsp_reset - input EN_rsp_reset; - output RDY_rsp_reset; - - // action method req - input req_is_OP_not_OP_32; - input [2 : 0] req_f3; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input EN_req; - - // value method valid - output valid; - - // value method word - output [63 : 0] word; - - // signals for module outputs - wire [63 : 0] word; - wire RDY_req_reset, RDY_rsp_reset, RDY_set_verbosity, valid; - - // inlined wires - wire dw_valid$whas; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register intDiv_rg_denom2 - reg [63 : 0] intDiv_rg_denom2; - reg [63 : 0] intDiv_rg_denom2$D_IN; - wire intDiv_rg_denom2$EN; - - // register intDiv_rg_denom_is_signed - reg intDiv_rg_denom_is_signed; - wire intDiv_rg_denom_is_signed$D_IN, intDiv_rg_denom_is_signed$EN; - - // register intDiv_rg_n - reg [63 : 0] intDiv_rg_n; - reg [63 : 0] intDiv_rg_n$D_IN; - wire intDiv_rg_n$EN; - - // register intDiv_rg_numer_is_signed - reg intDiv_rg_numer_is_signed; - wire intDiv_rg_numer_is_signed$D_IN, intDiv_rg_numer_is_signed$EN; - - // register intDiv_rg_quo - reg [63 : 0] intDiv_rg_quo; - reg [63 : 0] intDiv_rg_quo$D_IN; - wire intDiv_rg_quo$EN; - - // register intDiv_rg_quoIsNeg - reg intDiv_rg_quoIsNeg; - wire intDiv_rg_quoIsNeg$D_IN, intDiv_rg_quoIsNeg$EN; - - // register intDiv_rg_remIsNeg - reg intDiv_rg_remIsNeg; - wire intDiv_rg_remIsNeg$D_IN, intDiv_rg_remIsNeg$EN; - - // register intDiv_rg_state - reg [2 : 0] intDiv_rg_state; - reg [2 : 0] intDiv_rg_state$D_IN; - wire intDiv_rg_state$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_is_OP_not_OP_32 - reg rg_is_OP_not_OP_32; - wire rg_is_OP_not_OP_32$D_IN, rg_is_OP_not_OP_32$EN; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_v1 - reg [63 : 0] rg_v1; - reg [63 : 0] rg_v1$D_IN; - wire rg_v1$EN; - - // register rg_v2 - reg [63 : 0] rg_v2; - wire [63 : 0] rg_v2$D_IN; - wire rg_v2$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_intDiv_rl_loop1, - CAN_FIRE_RL_intDiv_rl_loop2, - CAN_FIRE_RL_intDiv_rl_start_div_by_zero, - CAN_FIRE_RL_intDiv_rl_start_overflow, - CAN_FIRE_RL_intDiv_rl_start_s, - CAN_FIRE_RL_rg_div_rem, - CAN_FIRE_RL_rl_mul, - CAN_FIRE_RL_rl_mul2, - CAN_FIRE_req, - CAN_FIRE_req_reset, - CAN_FIRE_rsp_reset, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_intDiv_rl_loop1, - WILL_FIRE_RL_intDiv_rl_loop2, - WILL_FIRE_RL_intDiv_rl_start_div_by_zero, - WILL_FIRE_RL_intDiv_rl_start_overflow, - WILL_FIRE_RL_intDiv_rl_start_s, - WILL_FIRE_RL_rg_div_rem, - WILL_FIRE_RL_rl_mul, - WILL_FIRE_RL_rl_mul2, - WILL_FIRE_req, - WILL_FIRE_req_reset, - WILL_FIRE_rsp_reset, - WILL_FIRE_set_verbosity; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_dw_result$wset_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_1, - MUX_intDiv_rg_denom2$write_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_3, - MUX_intDiv_rg_n$write_1__VAL_1, - MUX_intDiv_rg_n$write_1__VAL_2, - MUX_intDiv_rg_quo$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_2, - MUX_rg_v1$write_1__VAL_3, - MUX_rg_v1$write_1__VAL_4, - MUX_rg_v2$write_1__VAL_1; - wire [1 : 0] MUX_rg_state$write_1__VAL_1; - wire MUX_intDiv_rg_denom2$write_1__SEL_1, - MUX_intDiv_rg_denom2$write_1__SEL_2, - MUX_intDiv_rg_quo$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_2, - MUX_intDiv_rg_state$write_1__SEL_3, - MUX_rg_v1$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4706; - reg [31 : 0] v__h4700; - // synopsys translate_on - - // remaining internal signals - wire [255 : 0] SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118, - SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110, - _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115; - wire [127 : 0] SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125, - SEXT_rg_v1____d108, - rg_v1_MUL_rg_v2___d105, - v1__h4494; - wire [63 : 0] IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138, - _theResult___fst__h5162, - _theResult___fst__h5192, - _theResult___fst__h5218, - _theResult___fst__h787, - _theResult___snd__h5163, - _theResult___snd__h5193, - _theResult___snd__h5219, - _theResult___snd_fst__h782, - denom___1__h729, - numer___1__h728, - result___1__h4957, - v__h4418, - v__h4476, - v__h4527, - v__h4583, - v__h4600, - x__h3955, - x__h4041, - x__h4111, - x__h4126, - y__h3834; - wire [31 : 0] IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3, - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6, - req_v1_BITS_31_TO_0__q1, - req_v2_BITS_31_TO_0__q2, - rg_v1_BITS_31_TO_0__q4, - rg_v2_BITS_31_TO_0__q5; - wire IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39, - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47, - rg_v1_ULT_intDiv_rg_denom2_4___d59, - rg_v1_ULT_rg_v2___d55; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method req_reset - assign RDY_req_reset = 1'd1 ; - assign CAN_FIRE_req_reset = 1'd1 ; - assign WILL_FIRE_req_reset = EN_req_reset ; - - // action method rsp_reset - assign RDY_rsp_reset = 1'd1 ; - assign CAN_FIRE_rsp_reset = 1'd1 ; - assign WILL_FIRE_rsp_reset = EN_rsp_reset ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method word - assign word = WILL_FIRE_RL_rl_mul2 ? rg_v1 : MUX_dw_result$wset_1__VAL_2 ; - - // rule RL_rl_mul2 - assign CAN_FIRE_RL_rl_mul2 = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_mul2 = CAN_FIRE_RL_rl_mul2 ; - - // rule RL_rg_div_rem - assign CAN_FIRE_RL_rg_div_rem = - rg_state == 2'd2 && intDiv_rg_state == 3'd4 ; - assign WILL_FIRE_RL_rg_div_rem = CAN_FIRE_RL_rg_div_rem ; - - // rule RL_intDiv_rl_start_div_by_zero - assign CAN_FIRE_RL_intDiv_rl_start_div_by_zero = - intDiv_rg_state == 3'd1 && rg_v2 == 64'd0 ; - assign WILL_FIRE_RL_intDiv_rl_start_div_by_zero = - CAN_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // rule RL_intDiv_rl_start_overflow - assign CAN_FIRE_RL_intDiv_rl_start_overflow = - intDiv_rg_state == 3'd1 && intDiv_rg_numer_is_signed && - rg_v1 == 64'h8000000000000000 && - intDiv_rg_denom_is_signed && - rg_v2 == 64'hFFFFFFFFFFFFFFFF ; - assign WILL_FIRE_RL_intDiv_rl_start_overflow = - CAN_FIRE_RL_intDiv_rl_start_overflow && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_start_s - assign CAN_FIRE_RL_intDiv_rl_start_s = - intDiv_rg_state == 3'd1 && rg_v2 != 64'd0 && - (!intDiv_rg_numer_is_signed || rg_v1 != 64'h8000000000000000 || - !intDiv_rg_denom_is_signed || - rg_v2 != 64'hFFFFFFFFFFFFFFFF) ; - assign WILL_FIRE_RL_intDiv_rl_start_s = - CAN_FIRE_RL_intDiv_rl_start_s && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_loop1 - assign CAN_FIRE_RL_intDiv_rl_loop1 = intDiv_rg_state == 3'd2 ; - assign WILL_FIRE_RL_intDiv_rl_loop1 = CAN_FIRE_RL_intDiv_rl_loop1 ; - - // rule RL_rl_mul - assign CAN_FIRE_RL_rl_mul = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_mul = rg_state == 2'd0 ; - - // rule RL_intDiv_rl_loop2 - assign CAN_FIRE_RL_intDiv_rl_loop2 = intDiv_rg_state == 3'd3 ; - assign WILL_FIRE_RL_intDiv_rl_loop2 = - CAN_FIRE_RL_intDiv_rl_loop2 && !WILL_FIRE_RL_rl_mul ; - - // inputs to muxes for submodule ports - assign MUX_intDiv_rg_denom2$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ; - assign MUX_intDiv_rg_denom2$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 ; - assign MUX_intDiv_rg_quo$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_quoIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_intDiv_rg_state$write_1__SEL_1 = EN_req && req_f3[2] ; - assign MUX_intDiv_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 ; - assign MUX_intDiv_rg_state$write_1__SEL_3 = - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ; - assign MUX_rg_v1$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_remIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_dw_result$wset_1__VAL_2 = - rg_is_OP_not_OP_32 ? - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138 : - result___1__h4957 ; - assign MUX_intDiv_rg_denom2$write_1__VAL_1 = - { intDiv_rg_denom2[62:0], 1'd0 } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_2 = - { 1'd0, intDiv_rg_denom2[63:1] } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_3 = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - denom___1__h729 : - _theResult___snd_fst__h782 ; - assign MUX_intDiv_rg_n$write_1__VAL_1 = { intDiv_rg_n[62:0], 1'd0 } ; - assign MUX_intDiv_rg_n$write_1__VAL_2 = { 1'd0, intDiv_rg_n[63:1] } ; - assign MUX_intDiv_rg_quo$write_1__VAL_1 = - rg_v1_ULT_rg_v2___d55 ? x__h4041 : x__h4126 ; - assign MUX_rg_state$write_1__VAL_1 = req_f3[2] ? 2'd2 : 2'd0 ; - assign MUX_rg_v1$write_1__VAL_1 = - req_is_OP_not_OP_32 ? req_v1 : _theResult___fst__h5162 ; - assign MUX_rg_v1$write_1__VAL_2 = - rg_v1_ULT_rg_v2___d55 ? x__h4111 : x__h3955 ; - assign MUX_rg_v1$write_1__VAL_3 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - rg_v1_MUL_rg_v2___d105[63:0] : - v__h4418 ; - assign MUX_rg_v1$write_1__VAL_4 = - intDiv_rg_numer_is_signed ? numer___1__h728 : rg_v1 ; - assign MUX_rg_v2$write_1__VAL_1 = - req_is_OP_not_OP_32 ? req_v2 : _theResult___snd__h5163 ; - - // inlined wires - assign dw_valid$whas = WILL_FIRE_RL_rg_div_rem || WILL_FIRE_RL_rl_mul2 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register intDiv_rg_denom2 - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_denom2$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_denom2$write_1__VAL_2 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_intDiv_rg_denom2$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_3; - default: intDiv_rg_denom2$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_denom2$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_denom_is_signed - assign intDiv_rg_denom_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_denom_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_n - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_n$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_n$write_1__VAL_2 or WILL_FIRE_RL_intDiv_rl_start_s) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_n$D_IN = 64'd1; - default: intDiv_rg_n$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_n$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_numer_is_signed - assign intDiv_rg_numer_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_numer_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_quo - always@(MUX_intDiv_rg_quo$write_1__SEL_1 or - MUX_intDiv_rg_quo$write_1__VAL_1 or - WILL_FIRE_RL_intDiv_rl_start_overflow or - rg_v1 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_quo$write_1__SEL_1: - intDiv_rg_quo$D_IN = MUX_intDiv_rg_quo$write_1__VAL_1; - WILL_FIRE_RL_intDiv_rl_start_overflow: intDiv_rg_quo$D_IN = rg_v1; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_quo$D_IN = 64'd0; - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_quo$D_IN = 64'hFFFFFFFFFFFFFFFF; - default: intDiv_rg_quo$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_quo$EN = - MUX_intDiv_rg_quo$write_1__SEL_1 || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register intDiv_rg_quoIsNeg - assign intDiv_rg_quoIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[63] != rg_v2[63] : - IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39 ; - assign intDiv_rg_quoIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_remIsNeg - assign intDiv_rg_remIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[63] : - intDiv_rg_numer_is_signed && rg_v1[63] ; - assign intDiv_rg_remIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_state - always@(MUX_intDiv_rg_state$write_1__SEL_1 or - MUX_intDiv_rg_state$write_1__SEL_2 or - MUX_intDiv_rg_state$write_1__SEL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_overflow or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - case (1'b1) - MUX_intDiv_rg_state$write_1__SEL_1: intDiv_rg_state$D_IN = 3'd1; - MUX_intDiv_rg_state$write_1__SEL_2: intDiv_rg_state$D_IN = 3'd4; - MUX_intDiv_rg_state$write_1__SEL_3: intDiv_rg_state$D_IN = 3'd3; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_state$D_IN = 3'd2; - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_state$D_IN = 3'd4; - default: intDiv_rg_state$D_IN = 3'b010 /* unspecified value */ ; - endcase - assign intDiv_rg_state$EN = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 || - EN_req && req_f3[2] || - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_is_OP_not_OP_32 - assign rg_is_OP_not_OP_32$D_IN = req_is_OP_not_OP_32 ; - assign rg_is_OP_not_OP_32$EN = EN_req ; - - // register rg_state - assign rg_state$D_IN = EN_req ? MUX_rg_state$write_1__VAL_1 : 2'd1 ; - assign rg_state$EN = EN_req || WILL_FIRE_RL_rl_mul ; - - // register rg_v1 - always@(EN_req or - MUX_rg_v1$write_1__VAL_1 or - MUX_rg_v1$write_1__SEL_2 or - MUX_rg_v1$write_1__VAL_2 or - WILL_FIRE_RL_rl_mul or - MUX_rg_v1$write_1__VAL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_rg_v1$write_1__VAL_4 or WILL_FIRE_RL_intDiv_rl_start_overflow) - case (1'b1) - EN_req: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_1; - MUX_rg_v1$write_1__SEL_2: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_2; - WILL_FIRE_RL_rl_mul: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_3; - WILL_FIRE_RL_intDiv_rl_start_s: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_4; - WILL_FIRE_RL_intDiv_rl_start_overflow: rg_v1$D_IN = 64'd0; - default: rg_v1$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign rg_v1$EN = - MUX_rg_v1$write_1__SEL_2 || WILL_FIRE_RL_rl_mul || EN_req || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow ; - - // register rg_v2 - assign rg_v2$D_IN = - EN_req ? - MUX_rg_v2$write_1__VAL_1 : - MUX_intDiv_rg_denom2$write_1__VAL_3 ; - assign rg_v2$EN = EN_req || WILL_FIRE_RL_intDiv_rl_start_s ; - - // remaining internal signals - assign IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39 = - intDiv_rg_numer_is_signed ? - rg_v1[63] : - intDiv_rg_denom_is_signed && rg_v2[63] ; - assign IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138 = - rg_f3[1] ? rg_v1 : intDiv_rg_quo ; - assign IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3 = - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138[31:0] ; - assign SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125 = - { {32{rg_v1_BITS_31_TO_0__q4[31]}}, rg_v1_BITS_31_TO_0__q4 } * - { {32{rg_v2_BITS_31_TO_0__q5[31]}}, rg_v2_BITS_31_TO_0__q5 } ; - assign SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6 = - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125[31:0] ; - assign SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118 = - SEXT_rg_v1____d108 * { 64'd0, rg_v2 } ; - assign SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110 = - SEXT_rg_v1____d108 * { {64{rg_v2[63]}}, rg_v2 } ; - assign SEXT_rg_v1____d108 = { {64{rg_v1[63]}}, rg_v1 } ; - assign _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115 = - v1__h4494 * { 64'd0, rg_v2 } ; - assign _theResult___fst__h5162 = - req_f3[0] ? _theResult___fst__h5218 : _theResult___fst__h5192 ; - assign _theResult___fst__h5192 = - { {32{req_v1_BITS_31_TO_0__q1[31]}}, req_v1_BITS_31_TO_0__q1 } ; - assign _theResult___fst__h5218 = { 32'd0, req_v1[31:0] } ; - assign _theResult___fst__h787 = - intDiv_rg_denom_is_signed ? denom___1__h729 : rg_v2 ; - assign _theResult___snd__h5163 = - req_f3[0] ? _theResult___snd__h5219 : _theResult___snd__h5193 ; - assign _theResult___snd__h5193 = - { {32{req_v2_BITS_31_TO_0__q2[31]}}, req_v2_BITS_31_TO_0__q2 } ; - assign _theResult___snd__h5219 = { 32'd0, req_v2[31:0] } ; - assign _theResult___snd_fst__h782 = - intDiv_rg_numer_is_signed ? rg_v2 : _theResult___fst__h787 ; - assign denom___1__h729 = rg_v2[63] ? -rg_v2 : rg_v2 ; - assign intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 = - intDiv_rg_denom2 <= y__h3834 ; - assign numer___1__h728 = rg_v1[63] ? x__h4111 : rg_v1 ; - assign req_v1_BITS_31_TO_0__q1 = req_v1[31:0] ; - assign req_v2_BITS_31_TO_0__q2 = req_v2[31:0] ; - assign result___1__h4957 = - { {32{IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3[31]}}, - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3 } ; - assign rg_v1_BITS_31_TO_0__q4 = rg_v1[31:0] ; - assign rg_v1_MUL_rg_v2___d105 = rg_v1 * rg_v2 ; - assign rg_v1_ULT_intDiv_rg_denom2_4___d59 = rg_v1 < intDiv_rg_denom2 ; - assign rg_v1_ULT_rg_v2___d55 = rg_v1 < rg_v2 ; - assign rg_v2_BITS_31_TO_0__q5 = rg_v2[31:0] ; - assign v1__h4494 = { 64'd0, rg_v1 } ; - assign v__h4418 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b001) ? - SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110[127:64] : - v__h4476 ; - assign v__h4476 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b011) ? - _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115[127:64] : - v__h4527 ; - assign v__h4527 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b010) ? - SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118[127:64] : - v__h4583 ; - assign v__h4583 = - (!rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - v__h4600 : - 64'hFFFFFFFFFFFFFFFF ; - assign v__h4600 = - { {32{SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6[31]}}, - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6 } ; - assign x__h3955 = rg_v1 - intDiv_rg_denom2 ; - assign x__h4041 = -intDiv_rg_quo ; - assign x__h4111 = -rg_v1 ; - assign x__h4126 = intDiv_rg_quo + intDiv_rg_n ; - assign y__h3834 = { 1'd0, rg_v1[63:1] } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (intDiv_rg_state$EN) - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY intDiv_rg_state$D_IN; - end - if (intDiv_rg_denom2$EN) - intDiv_rg_denom2 <= `BSV_ASSIGNMENT_DELAY intDiv_rg_denom2$D_IN; - if (intDiv_rg_denom_is_signed$EN) - intDiv_rg_denom_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_denom_is_signed$D_IN; - if (intDiv_rg_n$EN) intDiv_rg_n <= `BSV_ASSIGNMENT_DELAY intDiv_rg_n$D_IN; - if (intDiv_rg_numer_is_signed$EN) - intDiv_rg_numer_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_numer_is_signed$D_IN; - if (intDiv_rg_quo$EN) - intDiv_rg_quo <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quo$D_IN; - if (intDiv_rg_quoIsNeg$EN) - intDiv_rg_quoIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quoIsNeg$D_IN; - if (intDiv_rg_remIsNeg$EN) - intDiv_rg_remIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_remIsNeg$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_is_OP_not_OP_32$EN) - rg_is_OP_not_OP_32 <= `BSV_ASSIGNMENT_DELAY rg_is_OP_not_OP_32$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_v1$EN) rg_v1 <= `BSV_ASSIGNMENT_DELAY rg_v1$D_IN; - if (rg_v2$EN) rg_v2 <= `BSV_ASSIGNMENT_DELAY rg_v2$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - intDiv_rg_denom2 = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_denom_is_signed = 1'h0; - intDiv_rg_n = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_numer_is_signed = 1'h0; - intDiv_rg_quo = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_quoIsNeg = 1'h0; - intDiv_rg_remIsNeg = 1'h0; - intDiv_rg_state = 3'h2; - rg_f3 = 3'h2; - rg_is_OP_not_OP_32 = 1'h0; - rg_state = 2'h2; - rg_v1 = 64'hAAAAAAAAAAAAAAAA; - rg_v2 = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && cfg_verbosity > 4'd1) - $display(" RISCV_MBox.rl_mul"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $display("%0d: ERROR: RISCV_MBox.rl_mul: illegal f3.", v__h4700); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $display(" f3 0x%0h v1 0x%0h v2 0x%0h", rg_f3, rg_v1, rg_v2); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkRISCV_MBox - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v deleted file mode 100644 index c88e21cd..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Map.v +++ /dev/null @@ -1,298 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// m_near_mem_io_addr_base O 64 const -// m_near_mem_io_addr_size O 64 const -// m_near_mem_io_addr_lim O 64 const -// m_plic_addr_base O 64 const -// m_plic_addr_size O 64 const -// m_plic_addr_lim O 64 const -// m_uart0_addr_base O 64 const -// m_uart0_addr_size O 64 const -// m_uart0_addr_lim O 64 const -// m_boot_rom_addr_base O 64 const -// m_boot_rom_addr_size O 64 const -// m_boot_rom_addr_lim O 64 const -// m_mem0_controller_addr_base O 64 const -// m_mem0_controller_addr_size O 64 const -// m_mem0_controller_addr_lim O 64 const -// m_tcm_addr_base O 64 const -// m_tcm_addr_size O 64 const -// m_tcm_addr_lim O 64 const -// m_is_mem_addr O 1 -// m_is_IO_addr O 1 -// m_is_near_mem_IO_addr O 1 -// m_pc_reset_value O 64 const -// m_mtvec_reset_value O 64 const -// m_nmivec_reset_value O 64 const -// CLK I 1 unused -// RST_N I 1 unused -// m_is_mem_addr_addr I 64 -// m_is_IO_addr_addr I 64 -// m_is_near_mem_IO_addr_addr I 64 -// -// Combinational paths from inputs to outputs: -// m_is_mem_addr_addr -> m_is_mem_addr -// m_is_IO_addr_addr -> m_is_IO_addr -// m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Map(CLK, - RST_N, - - m_near_mem_io_addr_base, - - m_near_mem_io_addr_size, - - m_near_mem_io_addr_lim, - - m_plic_addr_base, - - m_plic_addr_size, - - m_plic_addr_lim, - - m_uart0_addr_base, - - m_uart0_addr_size, - - m_uart0_addr_lim, - - m_boot_rom_addr_base, - - m_boot_rom_addr_size, - - m_boot_rom_addr_lim, - - m_mem0_controller_addr_base, - - m_mem0_controller_addr_size, - - m_mem0_controller_addr_lim, - - m_tcm_addr_base, - - m_tcm_addr_size, - - m_tcm_addr_lim, - - m_is_mem_addr_addr, - m_is_mem_addr, - - m_is_IO_addr_addr, - m_is_IO_addr, - - m_is_near_mem_IO_addr_addr, - m_is_near_mem_IO_addr, - - m_pc_reset_value, - - m_mtvec_reset_value, - - m_nmivec_reset_value); - input CLK; - input RST_N; - - // value method m_near_mem_io_addr_base - output [63 : 0] m_near_mem_io_addr_base; - - // value method m_near_mem_io_addr_size - output [63 : 0] m_near_mem_io_addr_size; - - // value method m_near_mem_io_addr_lim - output [63 : 0] m_near_mem_io_addr_lim; - - // value method m_plic_addr_base - output [63 : 0] m_plic_addr_base; - - // value method m_plic_addr_size - output [63 : 0] m_plic_addr_size; - - // value method m_plic_addr_lim - output [63 : 0] m_plic_addr_lim; - - // value method m_uart0_addr_base - output [63 : 0] m_uart0_addr_base; - - // value method m_uart0_addr_size - output [63 : 0] m_uart0_addr_size; - - // value method m_uart0_addr_lim - output [63 : 0] m_uart0_addr_lim; - - // value method m_boot_rom_addr_base - output [63 : 0] m_boot_rom_addr_base; - - // value method m_boot_rom_addr_size - output [63 : 0] m_boot_rom_addr_size; - - // value method m_boot_rom_addr_lim - output [63 : 0] m_boot_rom_addr_lim; - - // value method m_mem0_controller_addr_base - output [63 : 0] m_mem0_controller_addr_base; - - // value method m_mem0_controller_addr_size - output [63 : 0] m_mem0_controller_addr_size; - - // value method m_mem0_controller_addr_lim - output [63 : 0] m_mem0_controller_addr_lim; - - // value method m_tcm_addr_base - output [63 : 0] m_tcm_addr_base; - - // value method m_tcm_addr_size - output [63 : 0] m_tcm_addr_size; - - // value method m_tcm_addr_lim - output [63 : 0] m_tcm_addr_lim; - - // value method m_is_mem_addr - input [63 : 0] m_is_mem_addr_addr; - output m_is_mem_addr; - - // value method m_is_IO_addr - input [63 : 0] m_is_IO_addr_addr; - output m_is_IO_addr; - - // value method m_is_near_mem_IO_addr - input [63 : 0] m_is_near_mem_IO_addr_addr; - output m_is_near_mem_IO_addr; - - // value method m_pc_reset_value - output [63 : 0] m_pc_reset_value; - - // value method m_mtvec_reset_value - output [63 : 0] m_mtvec_reset_value; - - // value method m_nmivec_reset_value - output [63 : 0] m_nmivec_reset_value; - - // signals for module outputs - wire [63 : 0] m_boot_rom_addr_base, - m_boot_rom_addr_lim, - m_boot_rom_addr_size, - m_mem0_controller_addr_base, - m_mem0_controller_addr_lim, - m_mem0_controller_addr_size, - m_mtvec_reset_value, - m_near_mem_io_addr_base, - m_near_mem_io_addr_lim, - m_near_mem_io_addr_size, - m_nmivec_reset_value, - m_pc_reset_value, - m_plic_addr_base, - m_plic_addr_lim, - m_plic_addr_size, - m_tcm_addr_base, - m_tcm_addr_lim, - m_tcm_addr_size, - m_uart0_addr_base, - m_uart0_addr_lim, - m_uart0_addr_size; - wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; - - // value method m_near_mem_io_addr_base - assign m_near_mem_io_addr_base = 64'h0000000002000000 ; - - // value method m_near_mem_io_addr_size - assign m_near_mem_io_addr_size = 64'h000000000000C000 ; - - // value method m_near_mem_io_addr_lim - assign m_near_mem_io_addr_lim = 64'd33603584 ; - - // value method m_plic_addr_base - assign m_plic_addr_base = 64'h000000000C000000 ; - - // value method m_plic_addr_size - assign m_plic_addr_size = 64'h0000000000400000 ; - - // value method m_plic_addr_lim - assign m_plic_addr_lim = 64'd205520896 ; - - // value method m_uart0_addr_base - assign m_uart0_addr_base = 64'h00000000C0000000 ; - - // value method m_uart0_addr_size - assign m_uart0_addr_size = 64'h0000000000000080 ; - - // value method m_uart0_addr_lim - assign m_uart0_addr_lim = 64'h00000000C0000080 ; - - // value method m_boot_rom_addr_base - assign m_boot_rom_addr_base = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_size - assign m_boot_rom_addr_size = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_lim - assign m_boot_rom_addr_lim = 64'd8192 ; - - // value method m_mem0_controller_addr_base - assign m_mem0_controller_addr_base = 64'h0000000080000000 ; - - // value method m_mem0_controller_addr_size - assign m_mem0_controller_addr_size = 64'h0000000010000000 ; - - // value method m_mem0_controller_addr_lim - assign m_mem0_controller_addr_lim = 64'h0000000090000000 ; - - // value method m_tcm_addr_base - assign m_tcm_addr_base = 64'h0 ; - - // value method m_tcm_addr_size - assign m_tcm_addr_size = 64'd0 ; - - // value method m_tcm_addr_lim - assign m_tcm_addr_lim = 64'd0 ; - - // value method m_is_mem_addr - assign m_is_mem_addr = - m_is_mem_addr_addr >= 64'h0000000000001000 && - m_is_mem_addr_addr < 64'd8192 || - m_is_mem_addr_addr >= 64'h0000000080000000 && - m_is_mem_addr_addr < 64'h0000000090000000 ; - - // value method m_is_IO_addr - assign m_is_IO_addr = - m_is_IO_addr_addr >= 64'h0000000002000000 && - m_is_IO_addr_addr < 64'd33603584 || - m_is_IO_addr_addr >= 64'h000000000C000000 && - m_is_IO_addr_addr < 64'd205520896 || - m_is_IO_addr_addr >= 64'h00000000C0000000 && - m_is_IO_addr_addr < 64'h00000000C0000080 ; - - // value method m_is_near_mem_IO_addr - assign m_is_near_mem_IO_addr = - m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 && - m_is_near_mem_IO_addr_addr < 64'd33603584 ; - - // value method m_pc_reset_value - assign m_pc_reset_value = 64'h0000000000001000 ; - - // value method m_mtvec_reset_value - assign m_mtvec_reset_value = 64'h0000000000001000 ; - - // value method m_nmivec_reset_value - assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ; -endmodule // mkSoC_Map - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v deleted file mode 100644 index 42e03763..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkSoC_Top.v +++ /dev/null @@ -1,2333 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// to_raw_mem_response_put I 256 -// put_from_console_put I 8 reg -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_set_verbosity I 1 -// EN_to_raw_mem_response_put I 1 -// EN_put_from_console_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Top(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [7 : 0] get_to_console_get, status; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_set_verbosity, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule boot_rom - wire [63 : 0] boot_rom$set_addr_map_addr_base, - boot_rom$set_addr_map_addr_lim, - boot_rom$slave_araddr, - boot_rom$slave_awaddr, - boot_rom$slave_rdata, - boot_rom$slave_wdata; - wire [7 : 0] boot_rom$slave_arlen, - boot_rom$slave_awlen, - boot_rom$slave_wstrb; - wire [3 : 0] boot_rom$slave_arcache, - boot_rom$slave_arid, - boot_rom$slave_arqos, - boot_rom$slave_arregion, - boot_rom$slave_awcache, - boot_rom$slave_awid, - boot_rom$slave_awqos, - boot_rom$slave_awregion, - boot_rom$slave_bid, - boot_rom$slave_rid, - boot_rom$slave_wid; - wire [2 : 0] boot_rom$slave_arprot, - boot_rom$slave_arsize, - boot_rom$slave_awprot, - boot_rom$slave_awsize; - wire [1 : 0] boot_rom$slave_arburst, - boot_rom$slave_awburst, - boot_rom$slave_bresp, - boot_rom$slave_rresp; - wire boot_rom$EN_set_addr_map, - boot_rom$slave_arlock, - boot_rom$slave_arready, - boot_rom$slave_arvalid, - boot_rom$slave_awlock, - boot_rom$slave_awready, - boot_rom$slave_awvalid, - boot_rom$slave_bready, - boot_rom$slave_bvalid, - boot_rom$slave_rlast, - boot_rom$slave_rready, - boot_rom$slave_rvalid, - boot_rom$slave_wlast, - boot_rom$slave_wready, - boot_rom$slave_wvalid; - - // ports of submodule boot_rom_axi4_deburster - wire [63 : 0] boot_rom_axi4_deburster$from_master_araddr, - boot_rom_axi4_deburster$from_master_awaddr, - boot_rom_axi4_deburster$from_master_rdata, - boot_rom_axi4_deburster$from_master_wdata, - boot_rom_axi4_deburster$to_slave_araddr, - boot_rom_axi4_deburster$to_slave_awaddr, - boot_rom_axi4_deburster$to_slave_rdata, - boot_rom_axi4_deburster$to_slave_wdata; - wire [7 : 0] boot_rom_axi4_deburster$from_master_arlen, - boot_rom_axi4_deburster$from_master_awlen, - boot_rom_axi4_deburster$from_master_wstrb, - boot_rom_axi4_deburster$to_slave_arlen, - boot_rom_axi4_deburster$to_slave_awlen, - boot_rom_axi4_deburster$to_slave_wstrb; - wire [3 : 0] boot_rom_axi4_deburster$from_master_arcache, - boot_rom_axi4_deburster$from_master_arid, - boot_rom_axi4_deburster$from_master_arqos, - boot_rom_axi4_deburster$from_master_arregion, - boot_rom_axi4_deburster$from_master_awcache, - boot_rom_axi4_deburster$from_master_awid, - boot_rom_axi4_deburster$from_master_awqos, - boot_rom_axi4_deburster$from_master_awregion, - boot_rom_axi4_deburster$from_master_bid, - boot_rom_axi4_deburster$from_master_rid, - boot_rom_axi4_deburster$from_master_wid, - boot_rom_axi4_deburster$to_slave_arcache, - boot_rom_axi4_deburster$to_slave_arid, - boot_rom_axi4_deburster$to_slave_arqos, - boot_rom_axi4_deburster$to_slave_arregion, - boot_rom_axi4_deburster$to_slave_awcache, - boot_rom_axi4_deburster$to_slave_awid, - boot_rom_axi4_deburster$to_slave_awqos, - boot_rom_axi4_deburster$to_slave_awregion, - boot_rom_axi4_deburster$to_slave_bid, - boot_rom_axi4_deburster$to_slave_rid, - boot_rom_axi4_deburster$to_slave_wid; - wire [2 : 0] boot_rom_axi4_deburster$from_master_arprot, - boot_rom_axi4_deburster$from_master_arsize, - boot_rom_axi4_deburster$from_master_awprot, - boot_rom_axi4_deburster$from_master_awsize, - boot_rom_axi4_deburster$to_slave_arprot, - boot_rom_axi4_deburster$to_slave_arsize, - boot_rom_axi4_deburster$to_slave_awprot, - boot_rom_axi4_deburster$to_slave_awsize; - wire [1 : 0] boot_rom_axi4_deburster$from_master_arburst, - boot_rom_axi4_deburster$from_master_awburst, - boot_rom_axi4_deburster$from_master_bresp, - boot_rom_axi4_deburster$from_master_rresp, - boot_rom_axi4_deburster$to_slave_arburst, - boot_rom_axi4_deburster$to_slave_awburst, - boot_rom_axi4_deburster$to_slave_bresp, - boot_rom_axi4_deburster$to_slave_rresp; - wire boot_rom_axi4_deburster$EN_reset, - boot_rom_axi4_deburster$from_master_arlock, - boot_rom_axi4_deburster$from_master_arready, - boot_rom_axi4_deburster$from_master_arvalid, - boot_rom_axi4_deburster$from_master_awlock, - boot_rom_axi4_deburster$from_master_awready, - boot_rom_axi4_deburster$from_master_awvalid, - boot_rom_axi4_deburster$from_master_bready, - boot_rom_axi4_deburster$from_master_bvalid, - boot_rom_axi4_deburster$from_master_rlast, - boot_rom_axi4_deburster$from_master_rready, - boot_rom_axi4_deburster$from_master_rvalid, - boot_rom_axi4_deburster$from_master_wlast, - boot_rom_axi4_deburster$from_master_wready, - boot_rom_axi4_deburster$from_master_wvalid, - boot_rom_axi4_deburster$to_slave_arlock, - boot_rom_axi4_deburster$to_slave_arready, - boot_rom_axi4_deburster$to_slave_arvalid, - boot_rom_axi4_deburster$to_slave_awlock, - boot_rom_axi4_deburster$to_slave_awready, - boot_rom_axi4_deburster$to_slave_awvalid, - boot_rom_axi4_deburster$to_slave_bready, - boot_rom_axi4_deburster$to_slave_bvalid, - boot_rom_axi4_deburster$to_slave_rlast, - boot_rom_axi4_deburster$to_slave_rready, - boot_rom_axi4_deburster$to_slave_rvalid, - boot_rom_axi4_deburster$to_slave_wlast, - boot_rom_axi4_deburster$to_slave_wready, - boot_rom_axi4_deburster$to_slave_wvalid; - - // ports of submodule core - wire [63 : 0] core$cpu_dmem_master_araddr, - core$cpu_dmem_master_awaddr, - core$cpu_dmem_master_rdata, - core$cpu_dmem_master_wdata, - core$cpu_imem_master_araddr, - core$cpu_imem_master_awaddr, - core$cpu_imem_master_rdata, - core$cpu_imem_master_wdata, - core$set_verbosity_logdelay; - wire [7 : 0] core$cpu_dmem_master_arlen, - core$cpu_dmem_master_awlen, - core$cpu_dmem_master_wstrb, - core$cpu_imem_master_arlen, - core$cpu_imem_master_awlen, - core$cpu_imem_master_wstrb; - wire [3 : 0] core$cpu_dmem_master_arcache, - core$cpu_dmem_master_arid, - core$cpu_dmem_master_arqos, - core$cpu_dmem_master_arregion, - core$cpu_dmem_master_awcache, - core$cpu_dmem_master_awid, - core$cpu_dmem_master_awqos, - core$cpu_dmem_master_awregion, - core$cpu_dmem_master_bid, - core$cpu_dmem_master_rid, - core$cpu_dmem_master_wid, - core$cpu_imem_master_arcache, - core$cpu_imem_master_arid, - core$cpu_imem_master_arqos, - core$cpu_imem_master_arregion, - core$cpu_imem_master_awcache, - core$cpu_imem_master_awid, - core$cpu_imem_master_awqos, - core$cpu_imem_master_awregion, - core$cpu_imem_master_bid, - core$cpu_imem_master_rid, - core$cpu_imem_master_wid, - core$set_verbosity_verbosity; - wire [2 : 0] core$cpu_dmem_master_arprot, - core$cpu_dmem_master_arsize, - core$cpu_dmem_master_awprot, - core$cpu_dmem_master_awsize, - core$cpu_imem_master_arprot, - core$cpu_imem_master_arsize, - core$cpu_imem_master_awprot, - core$cpu_imem_master_awsize; - wire [1 : 0] core$cpu_dmem_master_arburst, - core$cpu_dmem_master_awburst, - core$cpu_dmem_master_bresp, - core$cpu_dmem_master_rresp, - core$cpu_imem_master_arburst, - core$cpu_imem_master_awburst, - core$cpu_imem_master_bresp, - core$cpu_imem_master_rresp; - wire core$EN_cpu_reset_server_request_put, - core$EN_cpu_reset_server_response_get, - core$EN_set_verbosity, - core$RDY_cpu_reset_server_request_put, - core$RDY_cpu_reset_server_response_get, - core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - core$cpu_dmem_master_arlock, - core$cpu_dmem_master_arready, - core$cpu_dmem_master_arvalid, - core$cpu_dmem_master_awlock, - core$cpu_dmem_master_awready, - core$cpu_dmem_master_awvalid, - core$cpu_dmem_master_bready, - core$cpu_dmem_master_bvalid, - core$cpu_dmem_master_rlast, - core$cpu_dmem_master_rready, - core$cpu_dmem_master_rvalid, - core$cpu_dmem_master_wlast, - core$cpu_dmem_master_wready, - core$cpu_dmem_master_wvalid, - core$cpu_imem_master_arlock, - core$cpu_imem_master_arready, - core$cpu_imem_master_arvalid, - core$cpu_imem_master_awlock, - core$cpu_imem_master_awready, - core$cpu_imem_master_awvalid, - core$cpu_imem_master_bready, - core$cpu_imem_master_bvalid, - core$cpu_imem_master_rlast, - core$cpu_imem_master_rready, - core$cpu_imem_master_rvalid, - core$cpu_imem_master_wlast, - core$cpu_imem_master_wready, - core$cpu_imem_master_wvalid, - core$cpu_reset_server_request_put, - core$nmi_req_set_not_clear; - - // ports of submodule fabric - wire [63 : 0] fabric$v_from_masters_0_araddr, - fabric$v_from_masters_0_awaddr, - fabric$v_from_masters_0_rdata, - fabric$v_from_masters_0_wdata, - fabric$v_from_masters_1_araddr, - fabric$v_from_masters_1_awaddr, - fabric$v_from_masters_1_rdata, - fabric$v_from_masters_1_wdata, - fabric$v_to_slaves_0_araddr, - fabric$v_to_slaves_0_awaddr, - fabric$v_to_slaves_0_rdata, - fabric$v_to_slaves_0_wdata, - fabric$v_to_slaves_1_araddr, - fabric$v_to_slaves_1_awaddr, - fabric$v_to_slaves_1_rdata, - fabric$v_to_slaves_1_wdata, - fabric$v_to_slaves_2_araddr, - fabric$v_to_slaves_2_awaddr, - fabric$v_to_slaves_2_rdata, - fabric$v_to_slaves_2_wdata; - wire [7 : 0] fabric$v_from_masters_0_arlen, - fabric$v_from_masters_0_awlen, - fabric$v_from_masters_0_wstrb, - fabric$v_from_masters_1_arlen, - fabric$v_from_masters_1_awlen, - fabric$v_from_masters_1_wstrb, - fabric$v_to_slaves_0_arlen, - fabric$v_to_slaves_0_awlen, - fabric$v_to_slaves_0_wstrb, - fabric$v_to_slaves_1_arlen, - fabric$v_to_slaves_1_awlen, - fabric$v_to_slaves_1_wstrb, - fabric$v_to_slaves_2_arlen, - fabric$v_to_slaves_2_awlen, - fabric$v_to_slaves_2_wstrb; - wire [3 : 0] fabric$set_verbosity_verbosity, - fabric$v_from_masters_0_arcache, - fabric$v_from_masters_0_arid, - fabric$v_from_masters_0_arqos, - fabric$v_from_masters_0_arregion, - fabric$v_from_masters_0_awcache, - fabric$v_from_masters_0_awid, - fabric$v_from_masters_0_awqos, - fabric$v_from_masters_0_awregion, - fabric$v_from_masters_0_bid, - fabric$v_from_masters_0_rid, - fabric$v_from_masters_0_wid, - fabric$v_from_masters_1_arcache, - fabric$v_from_masters_1_arid, - fabric$v_from_masters_1_arqos, - fabric$v_from_masters_1_arregion, - fabric$v_from_masters_1_awcache, - fabric$v_from_masters_1_awid, - fabric$v_from_masters_1_awqos, - fabric$v_from_masters_1_awregion, - fabric$v_from_masters_1_bid, - fabric$v_from_masters_1_rid, - fabric$v_from_masters_1_wid, - fabric$v_to_slaves_0_arcache, - fabric$v_to_slaves_0_arid, - fabric$v_to_slaves_0_arqos, - fabric$v_to_slaves_0_arregion, - fabric$v_to_slaves_0_awcache, - fabric$v_to_slaves_0_awid, - fabric$v_to_slaves_0_awqos, - fabric$v_to_slaves_0_awregion, - fabric$v_to_slaves_0_bid, - fabric$v_to_slaves_0_rid, - fabric$v_to_slaves_0_wid, - fabric$v_to_slaves_1_arcache, - fabric$v_to_slaves_1_arid, - fabric$v_to_slaves_1_arqos, - fabric$v_to_slaves_1_arregion, - fabric$v_to_slaves_1_awcache, - fabric$v_to_slaves_1_awid, - fabric$v_to_slaves_1_awqos, - fabric$v_to_slaves_1_awregion, - fabric$v_to_slaves_1_bid, - fabric$v_to_slaves_1_rid, - fabric$v_to_slaves_1_wid, - fabric$v_to_slaves_2_arcache, - fabric$v_to_slaves_2_arid, - fabric$v_to_slaves_2_arqos, - fabric$v_to_slaves_2_arregion, - fabric$v_to_slaves_2_awcache, - fabric$v_to_slaves_2_awid, - fabric$v_to_slaves_2_awqos, - fabric$v_to_slaves_2_awregion, - fabric$v_to_slaves_2_bid, - fabric$v_to_slaves_2_rid, - fabric$v_to_slaves_2_wid; - wire [2 : 0] fabric$v_from_masters_0_arprot, - fabric$v_from_masters_0_arsize, - fabric$v_from_masters_0_awprot, - fabric$v_from_masters_0_awsize, - fabric$v_from_masters_1_arprot, - fabric$v_from_masters_1_arsize, - fabric$v_from_masters_1_awprot, - fabric$v_from_masters_1_awsize, - fabric$v_to_slaves_0_arprot, - fabric$v_to_slaves_0_arsize, - fabric$v_to_slaves_0_awprot, - fabric$v_to_slaves_0_awsize, - fabric$v_to_slaves_1_arprot, - fabric$v_to_slaves_1_arsize, - fabric$v_to_slaves_1_awprot, - fabric$v_to_slaves_1_awsize, - fabric$v_to_slaves_2_arprot, - fabric$v_to_slaves_2_arsize, - fabric$v_to_slaves_2_awprot, - fabric$v_to_slaves_2_awsize; - wire [1 : 0] fabric$v_from_masters_0_arburst, - fabric$v_from_masters_0_awburst, - fabric$v_from_masters_0_bresp, - fabric$v_from_masters_0_rresp, - fabric$v_from_masters_1_arburst, - fabric$v_from_masters_1_awburst, - fabric$v_from_masters_1_bresp, - fabric$v_from_masters_1_rresp, - fabric$v_to_slaves_0_arburst, - fabric$v_to_slaves_0_awburst, - fabric$v_to_slaves_0_bresp, - fabric$v_to_slaves_0_rresp, - fabric$v_to_slaves_1_arburst, - fabric$v_to_slaves_1_awburst, - fabric$v_to_slaves_1_bresp, - fabric$v_to_slaves_1_rresp, - fabric$v_to_slaves_2_arburst, - fabric$v_to_slaves_2_awburst, - fabric$v_to_slaves_2_bresp, - fabric$v_to_slaves_2_rresp; - wire fabric$EN_reset, - fabric$EN_set_verbosity, - fabric$RDY_reset, - fabric$v_from_masters_0_arlock, - fabric$v_from_masters_0_arready, - fabric$v_from_masters_0_arvalid, - fabric$v_from_masters_0_awlock, - fabric$v_from_masters_0_awready, - fabric$v_from_masters_0_awvalid, - fabric$v_from_masters_0_bready, - fabric$v_from_masters_0_bvalid, - fabric$v_from_masters_0_rlast, - fabric$v_from_masters_0_rready, - fabric$v_from_masters_0_rvalid, - fabric$v_from_masters_0_wlast, - fabric$v_from_masters_0_wready, - fabric$v_from_masters_0_wvalid, - fabric$v_from_masters_1_arlock, - fabric$v_from_masters_1_arready, - fabric$v_from_masters_1_arvalid, - fabric$v_from_masters_1_awlock, - fabric$v_from_masters_1_awready, - fabric$v_from_masters_1_awvalid, - fabric$v_from_masters_1_bready, - fabric$v_from_masters_1_bvalid, - fabric$v_from_masters_1_rlast, - fabric$v_from_masters_1_rready, - fabric$v_from_masters_1_rvalid, - fabric$v_from_masters_1_wlast, - fabric$v_from_masters_1_wready, - fabric$v_from_masters_1_wvalid, - fabric$v_to_slaves_0_arlock, - fabric$v_to_slaves_0_arready, - fabric$v_to_slaves_0_arvalid, - fabric$v_to_slaves_0_awlock, - fabric$v_to_slaves_0_awready, - fabric$v_to_slaves_0_awvalid, - fabric$v_to_slaves_0_bready, - fabric$v_to_slaves_0_bvalid, - fabric$v_to_slaves_0_rlast, - fabric$v_to_slaves_0_rready, - fabric$v_to_slaves_0_rvalid, - fabric$v_to_slaves_0_wlast, - fabric$v_to_slaves_0_wready, - fabric$v_to_slaves_0_wvalid, - fabric$v_to_slaves_1_arlock, - fabric$v_to_slaves_1_arready, - fabric$v_to_slaves_1_arvalid, - fabric$v_to_slaves_1_awlock, - fabric$v_to_slaves_1_awready, - fabric$v_to_slaves_1_awvalid, - fabric$v_to_slaves_1_bready, - fabric$v_to_slaves_1_bvalid, - fabric$v_to_slaves_1_rlast, - fabric$v_to_slaves_1_rready, - fabric$v_to_slaves_1_rvalid, - fabric$v_to_slaves_1_wlast, - fabric$v_to_slaves_1_wready, - fabric$v_to_slaves_1_wvalid, - fabric$v_to_slaves_2_arlock, - fabric$v_to_slaves_2_arready, - fabric$v_to_slaves_2_arvalid, - fabric$v_to_slaves_2_awlock, - fabric$v_to_slaves_2_awready, - fabric$v_to_slaves_2_awvalid, - fabric$v_to_slaves_2_bready, - fabric$v_to_slaves_2_bvalid, - fabric$v_to_slaves_2_rlast, - fabric$v_to_slaves_2_rready, - fabric$v_to_slaves_2_rvalid, - fabric$v_to_slaves_2_wlast, - fabric$v_to_slaves_2_wready, - fabric$v_to_slaves_2_wvalid; - - // ports of submodule mem0_controller - wire [352 : 0] mem0_controller$to_raw_mem_request_get; - wire [255 : 0] mem0_controller$to_raw_mem_response_put; - wire [63 : 0] mem0_controller$set_addr_map_addr_base, - mem0_controller$set_addr_map_addr_lim, - mem0_controller$set_watch_tohost_tohost_addr, - mem0_controller$slave_araddr, - mem0_controller$slave_awaddr, - mem0_controller$slave_rdata, - mem0_controller$slave_wdata; - wire [7 : 0] mem0_controller$slave_arlen, - mem0_controller$slave_awlen, - mem0_controller$slave_wstrb, - mem0_controller$status; - wire [3 : 0] mem0_controller$slave_arcache, - mem0_controller$slave_arid, - mem0_controller$slave_arqos, - mem0_controller$slave_arregion, - mem0_controller$slave_awcache, - mem0_controller$slave_awid, - mem0_controller$slave_awqos, - mem0_controller$slave_awregion, - mem0_controller$slave_bid, - mem0_controller$slave_rid, - mem0_controller$slave_wid; - wire [2 : 0] mem0_controller$slave_arprot, - mem0_controller$slave_arsize, - mem0_controller$slave_awprot, - mem0_controller$slave_awsize; - wire [1 : 0] mem0_controller$slave_arburst, - mem0_controller$slave_awburst, - mem0_controller$slave_bresp, - mem0_controller$slave_rresp; - wire mem0_controller$EN_server_reset_request_put, - mem0_controller$EN_server_reset_response_get, - mem0_controller$EN_set_addr_map, - mem0_controller$EN_set_watch_tohost, - mem0_controller$EN_to_raw_mem_request_get, - mem0_controller$EN_to_raw_mem_response_put, - mem0_controller$RDY_server_reset_request_put, - mem0_controller$RDY_server_reset_response_get, - mem0_controller$RDY_set_addr_map, - mem0_controller$RDY_to_raw_mem_request_get, - mem0_controller$RDY_to_raw_mem_response_put, - mem0_controller$set_watch_tohost_watch_tohost, - mem0_controller$slave_arlock, - mem0_controller$slave_arready, - mem0_controller$slave_arvalid, - mem0_controller$slave_awlock, - mem0_controller$slave_awready, - mem0_controller$slave_awvalid, - mem0_controller$slave_bready, - mem0_controller$slave_bvalid, - mem0_controller$slave_rlast, - mem0_controller$slave_rready, - mem0_controller$slave_rvalid, - mem0_controller$slave_wlast, - mem0_controller$slave_wready, - mem0_controller$slave_wvalid; - - // ports of submodule mem0_controller_axi4_deburster - wire [63 : 0] mem0_controller_axi4_deburster$from_master_araddr, - mem0_controller_axi4_deburster$from_master_awaddr, - mem0_controller_axi4_deburster$from_master_rdata, - mem0_controller_axi4_deburster$from_master_wdata, - mem0_controller_axi4_deburster$to_slave_araddr, - mem0_controller_axi4_deburster$to_slave_awaddr, - mem0_controller_axi4_deburster$to_slave_rdata, - mem0_controller_axi4_deburster$to_slave_wdata; - wire [7 : 0] mem0_controller_axi4_deburster$from_master_arlen, - mem0_controller_axi4_deburster$from_master_awlen, - mem0_controller_axi4_deburster$from_master_wstrb, - mem0_controller_axi4_deburster$to_slave_arlen, - mem0_controller_axi4_deburster$to_slave_awlen, - mem0_controller_axi4_deburster$to_slave_wstrb; - wire [3 : 0] mem0_controller_axi4_deburster$from_master_arcache, - mem0_controller_axi4_deburster$from_master_arid, - mem0_controller_axi4_deburster$from_master_arqos, - mem0_controller_axi4_deburster$from_master_arregion, - mem0_controller_axi4_deburster$from_master_awcache, - mem0_controller_axi4_deburster$from_master_awid, - mem0_controller_axi4_deburster$from_master_awqos, - mem0_controller_axi4_deburster$from_master_awregion, - mem0_controller_axi4_deburster$from_master_bid, - mem0_controller_axi4_deburster$from_master_rid, - mem0_controller_axi4_deburster$from_master_wid, - mem0_controller_axi4_deburster$to_slave_arcache, - mem0_controller_axi4_deburster$to_slave_arid, - mem0_controller_axi4_deburster$to_slave_arqos, - mem0_controller_axi4_deburster$to_slave_arregion, - mem0_controller_axi4_deburster$to_slave_awcache, - mem0_controller_axi4_deburster$to_slave_awid, - mem0_controller_axi4_deburster$to_slave_awqos, - mem0_controller_axi4_deburster$to_slave_awregion, - mem0_controller_axi4_deburster$to_slave_bid, - mem0_controller_axi4_deburster$to_slave_rid, - mem0_controller_axi4_deburster$to_slave_wid; - wire [2 : 0] mem0_controller_axi4_deburster$from_master_arprot, - mem0_controller_axi4_deburster$from_master_arsize, - mem0_controller_axi4_deburster$from_master_awprot, - mem0_controller_axi4_deburster$from_master_awsize, - mem0_controller_axi4_deburster$to_slave_arprot, - mem0_controller_axi4_deburster$to_slave_arsize, - mem0_controller_axi4_deburster$to_slave_awprot, - mem0_controller_axi4_deburster$to_slave_awsize; - wire [1 : 0] mem0_controller_axi4_deburster$from_master_arburst, - mem0_controller_axi4_deburster$from_master_awburst, - mem0_controller_axi4_deburster$from_master_bresp, - mem0_controller_axi4_deburster$from_master_rresp, - mem0_controller_axi4_deburster$to_slave_arburst, - mem0_controller_axi4_deburster$to_slave_awburst, - mem0_controller_axi4_deburster$to_slave_bresp, - mem0_controller_axi4_deburster$to_slave_rresp; - wire mem0_controller_axi4_deburster$EN_reset, - mem0_controller_axi4_deburster$from_master_arlock, - mem0_controller_axi4_deburster$from_master_arready, - mem0_controller_axi4_deburster$from_master_arvalid, - mem0_controller_axi4_deburster$from_master_awlock, - mem0_controller_axi4_deburster$from_master_awready, - mem0_controller_axi4_deburster$from_master_awvalid, - mem0_controller_axi4_deburster$from_master_bready, - mem0_controller_axi4_deburster$from_master_bvalid, - mem0_controller_axi4_deburster$from_master_rlast, - mem0_controller_axi4_deburster$from_master_rready, - mem0_controller_axi4_deburster$from_master_rvalid, - mem0_controller_axi4_deburster$from_master_wlast, - mem0_controller_axi4_deburster$from_master_wready, - mem0_controller_axi4_deburster$from_master_wvalid, - mem0_controller_axi4_deburster$to_slave_arlock, - mem0_controller_axi4_deburster$to_slave_arready, - mem0_controller_axi4_deburster$to_slave_arvalid, - mem0_controller_axi4_deburster$to_slave_awlock, - mem0_controller_axi4_deburster$to_slave_awready, - mem0_controller_axi4_deburster$to_slave_awvalid, - mem0_controller_axi4_deburster$to_slave_bready, - mem0_controller_axi4_deburster$to_slave_bvalid, - mem0_controller_axi4_deburster$to_slave_rlast, - mem0_controller_axi4_deburster$to_slave_rready, - mem0_controller_axi4_deburster$to_slave_rvalid, - mem0_controller_axi4_deburster$to_slave_wlast, - mem0_controller_axi4_deburster$to_slave_wready, - mem0_controller_axi4_deburster$to_slave_wvalid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // ports of submodule uart0 - wire [63 : 0] uart0$set_addr_map_addr_base, - uart0$set_addr_map_addr_lim, - uart0$slave_araddr, - uart0$slave_awaddr, - uart0$slave_rdata, - uart0$slave_wdata; - wire [7 : 0] uart0$get_to_console_get, - uart0$put_from_console_put, - uart0$slave_arlen, - uart0$slave_awlen, - uart0$slave_wstrb; - wire [3 : 0] uart0$slave_arcache, - uart0$slave_arid, - uart0$slave_arqos, - uart0$slave_arregion, - uart0$slave_awcache, - uart0$slave_awid, - uart0$slave_awqos, - uart0$slave_awregion, - uart0$slave_bid, - uart0$slave_rid, - uart0$slave_wid; - wire [2 : 0] uart0$slave_arprot, - uart0$slave_arsize, - uart0$slave_awprot, - uart0$slave_awsize; - wire [1 : 0] uart0$slave_arburst, - uart0$slave_awburst, - uart0$slave_bresp, - uart0$slave_rresp; - wire uart0$EN_get_to_console_get, - uart0$EN_put_from_console_put, - uart0$EN_server_reset_request_put, - uart0$EN_server_reset_response_get, - uart0$EN_set_addr_map, - uart0$RDY_get_to_console_get, - uart0$RDY_put_from_console_put, - uart0$RDY_server_reset_request_put, - uart0$RDY_server_reset_response_get, - uart0$intr, - uart0$slave_arlock, - uart0$slave_arready, - uart0$slave_arvalid, - uart0$slave_awlock, - uart0$slave_awready, - uart0$slave_awvalid, - uart0$slave_bready, - uart0$slave_bvalid, - uart0$slave_rlast, - uart0$slave_rready, - uart0$slave_rvalid, - uart0$slave_wlast, - uart0$slave_wready, - uart0$slave_wvalid; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_connect_external_interrupt_requests, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_addr_channel_5, - CAN_FIRE_RL_rl_rd_addr_channel_6, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, - CAN_FIRE_RL_rl_rd_data_channel_5, - CAN_FIRE_RL_rl_rd_data_channel_6, - CAN_FIRE_RL_rl_reset_complete_initial, - CAN_FIRE_RL_rl_reset_start_initial, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_addr_channel_5, - CAN_FIRE_RL_rl_wr_addr_channel_6, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_data_channel_5, - CAN_FIRE_RL_rl_wr_data_channel_6, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, - CAN_FIRE_RL_rl_wr_response_channel_5, - CAN_FIRE_RL_rl_wr_response_channel_6, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_set_verbosity, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_connect_external_interrupt_requests, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_addr_channel_5, - WILL_FIRE_RL_rl_rd_addr_channel_6, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, - WILL_FIRE_RL_rl_rd_data_channel_5, - WILL_FIRE_RL_rl_rd_data_channel_6, - WILL_FIRE_RL_rl_reset_complete_initial, - WILL_FIRE_RL_rl_reset_start_initial, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_addr_channel_5, - WILL_FIRE_RL_rl_wr_addr_channel_6, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_data_channel_5, - WILL_FIRE_RL_rl_wr_data_channel_6, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, - WILL_FIRE_RL_rl_wr_response_channel_5, - WILL_FIRE_RL_rl_wr_response_channel_6, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_set_verbosity, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h11286; - reg [31 : 0] v__h11556; - reg [31 : 0] v__h11280; - reg [31 : 0] v__h11550; - // synopsys translate_on - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = mem0_controller$to_raw_mem_request_get ; - assign RDY_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign CAN_FIRE_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign CAN_FIRE_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // actionvalue method get_to_console_get - assign get_to_console_get = uart0$get_to_console_get ; - assign RDY_get_to_console_get = uart0$RDY_get_to_console_get ; - assign CAN_FIRE_get_to_console_get = uart0$RDY_get_to_console_get ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = uart0$RDY_put_from_console_put ; - assign CAN_FIRE_put_from_console_put = uart0$RDY_put_from_console_put ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method status - assign status = mem0_controller$status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule boot_rom - mkBoot_ROM boot_rom(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(boot_rom$set_addr_map_addr_base), - .set_addr_map_addr_lim(boot_rom$set_addr_map_addr_lim), - .slave_araddr(boot_rom$slave_araddr), - .slave_arburst(boot_rom$slave_arburst), - .slave_arcache(boot_rom$slave_arcache), - .slave_arid(boot_rom$slave_arid), - .slave_arlen(boot_rom$slave_arlen), - .slave_arlock(boot_rom$slave_arlock), - .slave_arprot(boot_rom$slave_arprot), - .slave_arqos(boot_rom$slave_arqos), - .slave_arregion(boot_rom$slave_arregion), - .slave_arsize(boot_rom$slave_arsize), - .slave_arvalid(boot_rom$slave_arvalid), - .slave_awaddr(boot_rom$slave_awaddr), - .slave_awburst(boot_rom$slave_awburst), - .slave_awcache(boot_rom$slave_awcache), - .slave_awid(boot_rom$slave_awid), - .slave_awlen(boot_rom$slave_awlen), - .slave_awlock(boot_rom$slave_awlock), - .slave_awprot(boot_rom$slave_awprot), - .slave_awqos(boot_rom$slave_awqos), - .slave_awregion(boot_rom$slave_awregion), - .slave_awsize(boot_rom$slave_awsize), - .slave_awvalid(boot_rom$slave_awvalid), - .slave_bready(boot_rom$slave_bready), - .slave_rready(boot_rom$slave_rready), - .slave_wdata(boot_rom$slave_wdata), - .slave_wid(boot_rom$slave_wid), - .slave_wlast(boot_rom$slave_wlast), - .slave_wstrb(boot_rom$slave_wstrb), - .slave_wvalid(boot_rom$slave_wvalid), - .EN_set_addr_map(boot_rom$EN_set_addr_map), - .RDY_set_addr_map(), - .slave_awready(boot_rom$slave_awready), - .slave_wready(boot_rom$slave_wready), - .slave_bvalid(boot_rom$slave_bvalid), - .slave_bid(boot_rom$slave_bid), - .slave_bresp(boot_rom$slave_bresp), - .slave_arready(boot_rom$slave_arready), - .slave_rvalid(boot_rom$slave_rvalid), - .slave_rid(boot_rom$slave_rid), - .slave_rdata(boot_rom$slave_rdata), - .slave_rresp(boot_rom$slave_rresp), - .slave_rlast(boot_rom$slave_rlast)); - - // submodule boot_rom_axi4_deburster - mkAXI4_Deburster_A boot_rom_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(boot_rom_axi4_deburster$from_master_araddr), - .from_master_arburst(boot_rom_axi4_deburster$from_master_arburst), - .from_master_arcache(boot_rom_axi4_deburster$from_master_arcache), - .from_master_arid(boot_rom_axi4_deburster$from_master_arid), - .from_master_arlen(boot_rom_axi4_deburster$from_master_arlen), - .from_master_arlock(boot_rom_axi4_deburster$from_master_arlock), - .from_master_arprot(boot_rom_axi4_deburster$from_master_arprot), - .from_master_arqos(boot_rom_axi4_deburster$from_master_arqos), - .from_master_arregion(boot_rom_axi4_deburster$from_master_arregion), - .from_master_arsize(boot_rom_axi4_deburster$from_master_arsize), - .from_master_arvalid(boot_rom_axi4_deburster$from_master_arvalid), - .from_master_awaddr(boot_rom_axi4_deburster$from_master_awaddr), - .from_master_awburst(boot_rom_axi4_deburster$from_master_awburst), - .from_master_awcache(boot_rom_axi4_deburster$from_master_awcache), - .from_master_awid(boot_rom_axi4_deburster$from_master_awid), - .from_master_awlen(boot_rom_axi4_deburster$from_master_awlen), - .from_master_awlock(boot_rom_axi4_deburster$from_master_awlock), - .from_master_awprot(boot_rom_axi4_deburster$from_master_awprot), - .from_master_awqos(boot_rom_axi4_deburster$from_master_awqos), - .from_master_awregion(boot_rom_axi4_deburster$from_master_awregion), - .from_master_awsize(boot_rom_axi4_deburster$from_master_awsize), - .from_master_awvalid(boot_rom_axi4_deburster$from_master_awvalid), - .from_master_bready(boot_rom_axi4_deburster$from_master_bready), - .from_master_rready(boot_rom_axi4_deburster$from_master_rready), - .from_master_wdata(boot_rom_axi4_deburster$from_master_wdata), - .from_master_wid(boot_rom_axi4_deburster$from_master_wid), - .from_master_wlast(boot_rom_axi4_deburster$from_master_wlast), - .from_master_wstrb(boot_rom_axi4_deburster$from_master_wstrb), - .from_master_wvalid(boot_rom_axi4_deburster$from_master_wvalid), - .to_slave_arready(boot_rom_axi4_deburster$to_slave_arready), - .to_slave_awready(boot_rom_axi4_deburster$to_slave_awready), - .to_slave_bid(boot_rom_axi4_deburster$to_slave_bid), - .to_slave_bresp(boot_rom_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(boot_rom_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(boot_rom_axi4_deburster$to_slave_rdata), - .to_slave_rid(boot_rom_axi4_deburster$to_slave_rid), - .to_slave_rlast(boot_rom_axi4_deburster$to_slave_rlast), - .to_slave_rresp(boot_rom_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(boot_rom_axi4_deburster$to_slave_rvalid), - .to_slave_wready(boot_rom_axi4_deburster$to_slave_wready), - .EN_reset(boot_rom_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(boot_rom_axi4_deburster$from_master_awready), - .from_master_wready(boot_rom_axi4_deburster$from_master_wready), - .from_master_bvalid(boot_rom_axi4_deburster$from_master_bvalid), - .from_master_bid(boot_rom_axi4_deburster$from_master_bid), - .from_master_bresp(boot_rom_axi4_deburster$from_master_bresp), - .from_master_arready(boot_rom_axi4_deburster$from_master_arready), - .from_master_rvalid(boot_rom_axi4_deburster$from_master_rvalid), - .from_master_rid(boot_rom_axi4_deburster$from_master_rid), - .from_master_rdata(boot_rom_axi4_deburster$from_master_rdata), - .from_master_rresp(boot_rom_axi4_deburster$from_master_rresp), - .from_master_rlast(boot_rom_axi4_deburster$from_master_rlast), - .to_slave_awvalid(boot_rom_axi4_deburster$to_slave_awvalid), - .to_slave_awid(boot_rom_axi4_deburster$to_slave_awid), - .to_slave_awaddr(boot_rom_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(boot_rom_axi4_deburster$to_slave_awlen), - .to_slave_awsize(boot_rom_axi4_deburster$to_slave_awsize), - .to_slave_awburst(boot_rom_axi4_deburster$to_slave_awburst), - .to_slave_awlock(boot_rom_axi4_deburster$to_slave_awlock), - .to_slave_awcache(boot_rom_axi4_deburster$to_slave_awcache), - .to_slave_awprot(boot_rom_axi4_deburster$to_slave_awprot), - .to_slave_awqos(boot_rom_axi4_deburster$to_slave_awqos), - .to_slave_awregion(boot_rom_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(boot_rom_axi4_deburster$to_slave_wvalid), - .to_slave_wid(boot_rom_axi4_deburster$to_slave_wid), - .to_slave_wdata(boot_rom_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(boot_rom_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(boot_rom_axi4_deburster$to_slave_wlast), - .to_slave_bready(boot_rom_axi4_deburster$to_slave_bready), - .to_slave_arvalid(boot_rom_axi4_deburster$to_slave_arvalid), - .to_slave_arid(boot_rom_axi4_deburster$to_slave_arid), - .to_slave_araddr(boot_rom_axi4_deburster$to_slave_araddr), - .to_slave_arlen(boot_rom_axi4_deburster$to_slave_arlen), - .to_slave_arsize(boot_rom_axi4_deburster$to_slave_arsize), - .to_slave_arburst(boot_rom_axi4_deburster$to_slave_arburst), - .to_slave_arlock(boot_rom_axi4_deburster$to_slave_arlock), - .to_slave_arcache(boot_rom_axi4_deburster$to_slave_arcache), - .to_slave_arprot(boot_rom_axi4_deburster$to_slave_arprot), - .to_slave_arqos(boot_rom_axi4_deburster$to_slave_arqos), - .to_slave_arregion(boot_rom_axi4_deburster$to_slave_arregion), - .to_slave_rready(boot_rom_axi4_deburster$to_slave_rready)); - - // submodule core - mkCore core(.CLK(CLK), - .RST_N(RST_N), - .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_12_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_13_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_14_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_15_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_1_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_2_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_3_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_4_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_5_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_6_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_7_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_8_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_9_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear), - .cpu_dmem_master_arready(core$cpu_dmem_master_arready), - .cpu_dmem_master_awready(core$cpu_dmem_master_awready), - .cpu_dmem_master_bid(core$cpu_dmem_master_bid), - .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), - .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata), - .cpu_dmem_master_rid(core$cpu_dmem_master_rid), - .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast), - .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), - .cpu_dmem_master_wready(core$cpu_dmem_master_wready), - .cpu_imem_master_arready(core$cpu_imem_master_arready), - .cpu_imem_master_awready(core$cpu_imem_master_awready), - .cpu_imem_master_bid(core$cpu_imem_master_bid), - .cpu_imem_master_bresp(core$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), - .cpu_imem_master_rdata(core$cpu_imem_master_rdata), - .cpu_imem_master_rid(core$cpu_imem_master_rid), - .cpu_imem_master_rlast(core$cpu_imem_master_rlast), - .cpu_imem_master_rresp(core$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), - .cpu_imem_master_wready(core$cpu_imem_master_wready), - .cpu_reset_server_request_put(core$cpu_reset_server_request_put), - .nmi_req_set_not_clear(core$nmi_req_set_not_clear), - .set_verbosity_logdelay(core$set_verbosity_logdelay), - .set_verbosity_verbosity(core$set_verbosity_verbosity), - .EN_set_verbosity(core$EN_set_verbosity), - .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get), - .RDY_set_verbosity(), - .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put), - .cpu_reset_server_response_get(), - .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), - .cpu_imem_master_awid(core$cpu_imem_master_awid), - .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr), - .cpu_imem_master_awlen(core$cpu_imem_master_awlen), - .cpu_imem_master_awsize(core$cpu_imem_master_awsize), - .cpu_imem_master_awburst(core$cpu_imem_master_awburst), - .cpu_imem_master_awlock(core$cpu_imem_master_awlock), - .cpu_imem_master_awcache(core$cpu_imem_master_awcache), - .cpu_imem_master_awprot(core$cpu_imem_master_awprot), - .cpu_imem_master_awqos(core$cpu_imem_master_awqos), - .cpu_imem_master_awregion(core$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), - .cpu_imem_master_wid(core$cpu_imem_master_wid), - .cpu_imem_master_wdata(core$cpu_imem_master_wdata), - .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb), - .cpu_imem_master_wlast(core$cpu_imem_master_wlast), - .cpu_imem_master_bready(core$cpu_imem_master_bready), - .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), - .cpu_imem_master_arid(core$cpu_imem_master_arid), - .cpu_imem_master_araddr(core$cpu_imem_master_araddr), - .cpu_imem_master_arlen(core$cpu_imem_master_arlen), - .cpu_imem_master_arsize(core$cpu_imem_master_arsize), - .cpu_imem_master_arburst(core$cpu_imem_master_arburst), - .cpu_imem_master_arlock(core$cpu_imem_master_arlock), - .cpu_imem_master_arcache(core$cpu_imem_master_arcache), - .cpu_imem_master_arprot(core$cpu_imem_master_arprot), - .cpu_imem_master_arqos(core$cpu_imem_master_arqos), - .cpu_imem_master_arregion(core$cpu_imem_master_arregion), - .cpu_imem_master_rready(core$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), - .cpu_dmem_master_awid(core$cpu_dmem_master_awid), - .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr), - .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen), - .cpu_dmem_master_awsize(core$cpu_dmem_master_awsize), - .cpu_dmem_master_awburst(core$cpu_dmem_master_awburst), - .cpu_dmem_master_awlock(core$cpu_dmem_master_awlock), - .cpu_dmem_master_awcache(core$cpu_dmem_master_awcache), - .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot), - .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos), - .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(core$cpu_dmem_master_wid), - .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata), - .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb), - .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast), - .cpu_dmem_master_bready(core$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), - .cpu_dmem_master_arid(core$cpu_dmem_master_arid), - .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr), - .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen), - .cpu_dmem_master_arsize(core$cpu_dmem_master_arsize), - .cpu_dmem_master_arburst(core$cpu_dmem_master_arburst), - .cpu_dmem_master_arlock(core$cpu_dmem_master_arlock), - .cpu_dmem_master_arcache(core$cpu_dmem_master_arcache), - .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot), - .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos), - .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion), - .cpu_dmem_master_rready(core$cpu_dmem_master_rready)); - - // submodule fabric - mkFabric_AXI4 fabric(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric$v_to_slaves_2_wready), - .EN_reset(fabric$EN_reset), - .EN_set_verbosity(fabric$EN_set_verbosity), - .RDY_reset(fabric$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric$v_to_slaves_2_rready)); - - // submodule mem0_controller - mkMem_Controller mem0_controller(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(mem0_controller$set_addr_map_addr_base), - .set_addr_map_addr_lim(mem0_controller$set_addr_map_addr_lim), - .set_watch_tohost_tohost_addr(mem0_controller$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(mem0_controller$set_watch_tohost_watch_tohost), - .slave_araddr(mem0_controller$slave_araddr), - .slave_arburst(mem0_controller$slave_arburst), - .slave_arcache(mem0_controller$slave_arcache), - .slave_arid(mem0_controller$slave_arid), - .slave_arlen(mem0_controller$slave_arlen), - .slave_arlock(mem0_controller$slave_arlock), - .slave_arprot(mem0_controller$slave_arprot), - .slave_arqos(mem0_controller$slave_arqos), - .slave_arregion(mem0_controller$slave_arregion), - .slave_arsize(mem0_controller$slave_arsize), - .slave_arvalid(mem0_controller$slave_arvalid), - .slave_awaddr(mem0_controller$slave_awaddr), - .slave_awburst(mem0_controller$slave_awburst), - .slave_awcache(mem0_controller$slave_awcache), - .slave_awid(mem0_controller$slave_awid), - .slave_awlen(mem0_controller$slave_awlen), - .slave_awlock(mem0_controller$slave_awlock), - .slave_awprot(mem0_controller$slave_awprot), - .slave_awqos(mem0_controller$slave_awqos), - .slave_awregion(mem0_controller$slave_awregion), - .slave_awsize(mem0_controller$slave_awsize), - .slave_awvalid(mem0_controller$slave_awvalid), - .slave_bready(mem0_controller$slave_bready), - .slave_rready(mem0_controller$slave_rready), - .slave_wdata(mem0_controller$slave_wdata), - .slave_wid(mem0_controller$slave_wid), - .slave_wlast(mem0_controller$slave_wlast), - .slave_wstrb(mem0_controller$slave_wstrb), - .slave_wvalid(mem0_controller$slave_wvalid), - .to_raw_mem_response_put(mem0_controller$to_raw_mem_response_put), - .EN_server_reset_request_put(mem0_controller$EN_server_reset_request_put), - .EN_server_reset_response_get(mem0_controller$EN_server_reset_response_get), - .EN_set_addr_map(mem0_controller$EN_set_addr_map), - .EN_to_raw_mem_request_get(mem0_controller$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(mem0_controller$EN_to_raw_mem_response_put), - .EN_set_watch_tohost(mem0_controller$EN_set_watch_tohost), - .RDY_server_reset_request_put(mem0_controller$RDY_server_reset_request_put), - .RDY_server_reset_response_get(mem0_controller$RDY_server_reset_response_get), - .RDY_set_addr_map(mem0_controller$RDY_set_addr_map), - .slave_awready(mem0_controller$slave_awready), - .slave_wready(mem0_controller$slave_wready), - .slave_bvalid(mem0_controller$slave_bvalid), - .slave_bid(mem0_controller$slave_bid), - .slave_bresp(mem0_controller$slave_bresp), - .slave_arready(mem0_controller$slave_arready), - .slave_rvalid(mem0_controller$slave_rvalid), - .slave_rid(mem0_controller$slave_rid), - .slave_rdata(mem0_controller$slave_rdata), - .slave_rresp(mem0_controller$slave_rresp), - .slave_rlast(mem0_controller$slave_rlast), - .to_raw_mem_request_get(mem0_controller$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(mem0_controller$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(mem0_controller$RDY_to_raw_mem_response_put), - .status(mem0_controller$status), - .RDY_set_watch_tohost()); - - // submodule mem0_controller_axi4_deburster - mkAXI4_Deburster_A mem0_controller_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(mem0_controller_axi4_deburster$from_master_araddr), - .from_master_arburst(mem0_controller_axi4_deburster$from_master_arburst), - .from_master_arcache(mem0_controller_axi4_deburster$from_master_arcache), - .from_master_arid(mem0_controller_axi4_deburster$from_master_arid), - .from_master_arlen(mem0_controller_axi4_deburster$from_master_arlen), - .from_master_arlock(mem0_controller_axi4_deburster$from_master_arlock), - .from_master_arprot(mem0_controller_axi4_deburster$from_master_arprot), - .from_master_arqos(mem0_controller_axi4_deburster$from_master_arqos), - .from_master_arregion(mem0_controller_axi4_deburster$from_master_arregion), - .from_master_arsize(mem0_controller_axi4_deburster$from_master_arsize), - .from_master_arvalid(mem0_controller_axi4_deburster$from_master_arvalid), - .from_master_awaddr(mem0_controller_axi4_deburster$from_master_awaddr), - .from_master_awburst(mem0_controller_axi4_deburster$from_master_awburst), - .from_master_awcache(mem0_controller_axi4_deburster$from_master_awcache), - .from_master_awid(mem0_controller_axi4_deburster$from_master_awid), - .from_master_awlen(mem0_controller_axi4_deburster$from_master_awlen), - .from_master_awlock(mem0_controller_axi4_deburster$from_master_awlock), - .from_master_awprot(mem0_controller_axi4_deburster$from_master_awprot), - .from_master_awqos(mem0_controller_axi4_deburster$from_master_awqos), - .from_master_awregion(mem0_controller_axi4_deburster$from_master_awregion), - .from_master_awsize(mem0_controller_axi4_deburster$from_master_awsize), - .from_master_awvalid(mem0_controller_axi4_deburster$from_master_awvalid), - .from_master_bready(mem0_controller_axi4_deburster$from_master_bready), - .from_master_rready(mem0_controller_axi4_deburster$from_master_rready), - .from_master_wdata(mem0_controller_axi4_deburster$from_master_wdata), - .from_master_wid(mem0_controller_axi4_deburster$from_master_wid), - .from_master_wlast(mem0_controller_axi4_deburster$from_master_wlast), - .from_master_wstrb(mem0_controller_axi4_deburster$from_master_wstrb), - .from_master_wvalid(mem0_controller_axi4_deburster$from_master_wvalid), - .to_slave_arready(mem0_controller_axi4_deburster$to_slave_arready), - .to_slave_awready(mem0_controller_axi4_deburster$to_slave_awready), - .to_slave_bid(mem0_controller_axi4_deburster$to_slave_bid), - .to_slave_bresp(mem0_controller_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(mem0_controller_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(mem0_controller_axi4_deburster$to_slave_rdata), - .to_slave_rid(mem0_controller_axi4_deburster$to_slave_rid), - .to_slave_rlast(mem0_controller_axi4_deburster$to_slave_rlast), - .to_slave_rresp(mem0_controller_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(mem0_controller_axi4_deburster$to_slave_rvalid), - .to_slave_wready(mem0_controller_axi4_deburster$to_slave_wready), - .EN_reset(mem0_controller_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(mem0_controller_axi4_deburster$from_master_awready), - .from_master_wready(mem0_controller_axi4_deburster$from_master_wready), - .from_master_bvalid(mem0_controller_axi4_deburster$from_master_bvalid), - .from_master_bid(mem0_controller_axi4_deburster$from_master_bid), - .from_master_bresp(mem0_controller_axi4_deburster$from_master_bresp), - .from_master_arready(mem0_controller_axi4_deburster$from_master_arready), - .from_master_rvalid(mem0_controller_axi4_deburster$from_master_rvalid), - .from_master_rid(mem0_controller_axi4_deburster$from_master_rid), - .from_master_rdata(mem0_controller_axi4_deburster$from_master_rdata), - .from_master_rresp(mem0_controller_axi4_deburster$from_master_rresp), - .from_master_rlast(mem0_controller_axi4_deburster$from_master_rlast), - .to_slave_awvalid(mem0_controller_axi4_deburster$to_slave_awvalid), - .to_slave_awid(mem0_controller_axi4_deburster$to_slave_awid), - .to_slave_awaddr(mem0_controller_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(mem0_controller_axi4_deburster$to_slave_awlen), - .to_slave_awsize(mem0_controller_axi4_deburster$to_slave_awsize), - .to_slave_awburst(mem0_controller_axi4_deburster$to_slave_awburst), - .to_slave_awlock(mem0_controller_axi4_deburster$to_slave_awlock), - .to_slave_awcache(mem0_controller_axi4_deburster$to_slave_awcache), - .to_slave_awprot(mem0_controller_axi4_deburster$to_slave_awprot), - .to_slave_awqos(mem0_controller_axi4_deburster$to_slave_awqos), - .to_slave_awregion(mem0_controller_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(mem0_controller_axi4_deburster$to_slave_wvalid), - .to_slave_wid(mem0_controller_axi4_deburster$to_slave_wid), - .to_slave_wdata(mem0_controller_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(mem0_controller_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(mem0_controller_axi4_deburster$to_slave_wlast), - .to_slave_bready(mem0_controller_axi4_deburster$to_slave_bready), - .to_slave_arvalid(mem0_controller_axi4_deburster$to_slave_arvalid), - .to_slave_arid(mem0_controller_axi4_deburster$to_slave_arid), - .to_slave_araddr(mem0_controller_axi4_deburster$to_slave_araddr), - .to_slave_arlen(mem0_controller_axi4_deburster$to_slave_arlen), - .to_slave_arsize(mem0_controller_axi4_deburster$to_slave_arsize), - .to_slave_arburst(mem0_controller_axi4_deburster$to_slave_arburst), - .to_slave_arlock(mem0_controller_axi4_deburster$to_slave_arlock), - .to_slave_arcache(mem0_controller_axi4_deburster$to_slave_arcache), - .to_slave_arprot(mem0_controller_axi4_deburster$to_slave_arprot), - .to_slave_arqos(mem0_controller_axi4_deburster$to_slave_arqos), - .to_slave_arregion(mem0_controller_axi4_deburster$to_slave_arregion), - .to_slave_rready(mem0_controller_axi4_deburster$to_slave_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule uart0 - mkUART uart0(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(uart0$put_from_console_put), - .set_addr_map_addr_base(uart0$set_addr_map_addr_base), - .set_addr_map_addr_lim(uart0$set_addr_map_addr_lim), - .slave_araddr(uart0$slave_araddr), - .slave_arburst(uart0$slave_arburst), - .slave_arcache(uart0$slave_arcache), - .slave_arid(uart0$slave_arid), - .slave_arlen(uart0$slave_arlen), - .slave_arlock(uart0$slave_arlock), - .slave_arprot(uart0$slave_arprot), - .slave_arqos(uart0$slave_arqos), - .slave_arregion(uart0$slave_arregion), - .slave_arsize(uart0$slave_arsize), - .slave_arvalid(uart0$slave_arvalid), - .slave_awaddr(uart0$slave_awaddr), - .slave_awburst(uart0$slave_awburst), - .slave_awcache(uart0$slave_awcache), - .slave_awid(uart0$slave_awid), - .slave_awlen(uart0$slave_awlen), - .slave_awlock(uart0$slave_awlock), - .slave_awprot(uart0$slave_awprot), - .slave_awqos(uart0$slave_awqos), - .slave_awregion(uart0$slave_awregion), - .slave_awsize(uart0$slave_awsize), - .slave_awvalid(uart0$slave_awvalid), - .slave_bready(uart0$slave_bready), - .slave_rready(uart0$slave_rready), - .slave_wdata(uart0$slave_wdata), - .slave_wid(uart0$slave_wid), - .slave_wlast(uart0$slave_wlast), - .slave_wstrb(uart0$slave_wstrb), - .slave_wvalid(uart0$slave_wvalid), - .EN_server_reset_request_put(uart0$EN_server_reset_request_put), - .EN_server_reset_response_get(uart0$EN_server_reset_response_get), - .EN_set_addr_map(uart0$EN_set_addr_map), - .EN_get_to_console_get(uart0$EN_get_to_console_get), - .EN_put_from_console_put(uart0$EN_put_from_console_put), - .RDY_server_reset_request_put(uart0$RDY_server_reset_request_put), - .RDY_server_reset_response_get(uart0$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .slave_awready(uart0$slave_awready), - .slave_wready(uart0$slave_wready), - .slave_bvalid(uart0$slave_bvalid), - .slave_bid(uart0$slave_bid), - .slave_bresp(uart0$slave_bresp), - .slave_arready(uart0$slave_arready), - .slave_rvalid(uart0$slave_rvalid), - .slave_rid(uart0$slave_rid), - .slave_rdata(uart0$slave_rdata), - .slave_rresp(uart0$slave_rresp), - .slave_rlast(uart0$slave_rlast), - .get_to_console_get(uart0$get_to_console_get), - .RDY_get_to_console_get(uart0$RDY_get_to_console_get), - .RDY_put_from_console_put(uart0$RDY_put_from_console_put), - .intr(uart0$intr)); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_5 - assign CAN_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - - // rule RL_rl_wr_data_channel_5 - assign CAN_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_response_channel_5 - assign CAN_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_5 - assign CAN_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - - // rule RL_rl_rd_data_channel_5 - assign CAN_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_6 - assign CAN_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - - // rule RL_rl_wr_data_channel_6 - assign CAN_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - - // rule RL_rl_wr_response_channel_6 - assign CAN_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_6 - assign CAN_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - - // rule RL_rl_rd_data_channel_6 - assign CAN_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - - // rule RL_rl_connect_external_interrupt_requests - assign CAN_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - - // rule RL_rl_reset_start_initial - assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete_initial - assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete_initial = - MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = - mem0_controller$RDY_server_reset_request_put && - uart0$RDY_server_reset_request_put && - fabric$RDY_reset && - core$RDY_cpu_reset_server_request_put && - rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && - mem0_controller$RDY_server_reset_response_get && - uart0$RDY_server_reset_response_get && - core$RDY_cpu_reset_server_response_get && - rg_state == 2'd1 ; - - // register rg_state - assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_start_initial || - WILL_FIRE_RL_rl_reset_complete_initial ; - - // submodule boot_rom - assign boot_rom$set_addr_map_addr_base = soc_map$m_boot_rom_addr_base ; - assign boot_rom$set_addr_map_addr_lim = soc_map$m_boot_rom_addr_lim ; - assign boot_rom$slave_araddr = boot_rom_axi4_deburster$to_slave_araddr ; - assign boot_rom$slave_arburst = boot_rom_axi4_deburster$to_slave_arburst ; - assign boot_rom$slave_arcache = boot_rom_axi4_deburster$to_slave_arcache ; - assign boot_rom$slave_arid = boot_rom_axi4_deburster$to_slave_arid ; - assign boot_rom$slave_arlen = boot_rom_axi4_deburster$to_slave_arlen ; - assign boot_rom$slave_arlock = boot_rom_axi4_deburster$to_slave_arlock ; - assign boot_rom$slave_arprot = boot_rom_axi4_deburster$to_slave_arprot ; - assign boot_rom$slave_arqos = boot_rom_axi4_deburster$to_slave_arqos ; - assign boot_rom$slave_arregion = boot_rom_axi4_deburster$to_slave_arregion ; - assign boot_rom$slave_arsize = boot_rom_axi4_deburster$to_slave_arsize ; - assign boot_rom$slave_arvalid = boot_rom_axi4_deburster$to_slave_arvalid ; - assign boot_rom$slave_awaddr = boot_rom_axi4_deburster$to_slave_awaddr ; - assign boot_rom$slave_awburst = boot_rom_axi4_deburster$to_slave_awburst ; - assign boot_rom$slave_awcache = boot_rom_axi4_deburster$to_slave_awcache ; - assign boot_rom$slave_awid = boot_rom_axi4_deburster$to_slave_awid ; - assign boot_rom$slave_awlen = boot_rom_axi4_deburster$to_slave_awlen ; - assign boot_rom$slave_awlock = boot_rom_axi4_deburster$to_slave_awlock ; - assign boot_rom$slave_awprot = boot_rom_axi4_deburster$to_slave_awprot ; - assign boot_rom$slave_awqos = boot_rom_axi4_deburster$to_slave_awqos ; - assign boot_rom$slave_awregion = boot_rom_axi4_deburster$to_slave_awregion ; - assign boot_rom$slave_awsize = boot_rom_axi4_deburster$to_slave_awsize ; - assign boot_rom$slave_awvalid = boot_rom_axi4_deburster$to_slave_awvalid ; - assign boot_rom$slave_bready = boot_rom_axi4_deburster$to_slave_bready ; - assign boot_rom$slave_rready = boot_rom_axi4_deburster$to_slave_rready ; - assign boot_rom$slave_wdata = boot_rom_axi4_deburster$to_slave_wdata ; - assign boot_rom$slave_wid = boot_rom_axi4_deburster$to_slave_wid ; - assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; - assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; - assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - - // submodule boot_rom_axi4_deburster - assign boot_rom_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_0_araddr ; - assign boot_rom_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_0_arburst ; - assign boot_rom_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_0_arcache ; - assign boot_rom_axi4_deburster$from_master_arid = - fabric$v_to_slaves_0_arid ; - assign boot_rom_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_0_arlen ; - assign boot_rom_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_0_arlock ; - assign boot_rom_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_0_arprot ; - assign boot_rom_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_0_arqos ; - assign boot_rom_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_0_arregion ; - assign boot_rom_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_0_arsize ; - assign boot_rom_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_0_arvalid ; - assign boot_rom_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_0_awaddr ; - assign boot_rom_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_0_awburst ; - assign boot_rom_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_0_awcache ; - assign boot_rom_axi4_deburster$from_master_awid = - fabric$v_to_slaves_0_awid ; - assign boot_rom_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_0_awlen ; - assign boot_rom_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_0_awlock ; - assign boot_rom_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_0_awprot ; - assign boot_rom_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_0_awqos ; - assign boot_rom_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_0_awregion ; - assign boot_rom_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_0_awsize ; - assign boot_rom_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_0_awvalid ; - assign boot_rom_axi4_deburster$from_master_bready = - fabric$v_to_slaves_0_bready ; - assign boot_rom_axi4_deburster$from_master_rready = - fabric$v_to_slaves_0_rready ; - assign boot_rom_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_0_wdata ; - assign boot_rom_axi4_deburster$from_master_wid = fabric$v_to_slaves_0_wid ; - assign boot_rom_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_0_wlast ; - assign boot_rom_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_0_wstrb ; - assign boot_rom_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_0_wvalid ; - assign boot_rom_axi4_deburster$to_slave_arready = boot_rom$slave_arready ; - assign boot_rom_axi4_deburster$to_slave_awready = boot_rom$slave_awready ; - assign boot_rom_axi4_deburster$to_slave_bid = boot_rom$slave_bid ; - assign boot_rom_axi4_deburster$to_slave_bresp = boot_rom$slave_bresp ; - assign boot_rom_axi4_deburster$to_slave_bvalid = boot_rom$slave_bvalid ; - assign boot_rom_axi4_deburster$to_slave_rdata = boot_rom$slave_rdata ; - assign boot_rom_axi4_deburster$to_slave_rid = boot_rom$slave_rid ; - assign boot_rom_axi4_deburster$to_slave_rlast = boot_rom$slave_rlast ; - assign boot_rom_axi4_deburster$to_slave_rresp = boot_rom$slave_rresp ; - assign boot_rom_axi4_deburster$to_slave_rvalid = boot_rom$slave_rvalid ; - assign boot_rom_axi4_deburster$to_slave_wready = boot_rom$slave_wready ; - assign boot_rom_axi4_deburster$EN_reset = 1'b0 ; - - // submodule core - assign core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = - uart0$intr ; - assign core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$cpu_dmem_master_arready = fabric$v_from_masters_1_arready ; - assign core$cpu_dmem_master_awready = fabric$v_from_masters_1_awready ; - assign core$cpu_dmem_master_bid = fabric$v_from_masters_1_bid ; - assign core$cpu_dmem_master_bresp = fabric$v_from_masters_1_bresp ; - assign core$cpu_dmem_master_bvalid = fabric$v_from_masters_1_bvalid ; - assign core$cpu_dmem_master_rdata = fabric$v_from_masters_1_rdata ; - assign core$cpu_dmem_master_rid = fabric$v_from_masters_1_rid ; - assign core$cpu_dmem_master_rlast = fabric$v_from_masters_1_rlast ; - assign core$cpu_dmem_master_rresp = fabric$v_from_masters_1_rresp ; - assign core$cpu_dmem_master_rvalid = fabric$v_from_masters_1_rvalid ; - assign core$cpu_dmem_master_wready = fabric$v_from_masters_1_wready ; - assign core$cpu_imem_master_arready = fabric$v_from_masters_0_arready ; - assign core$cpu_imem_master_awready = fabric$v_from_masters_0_awready ; - assign core$cpu_imem_master_bid = fabric$v_from_masters_0_bid ; - assign core$cpu_imem_master_bresp = fabric$v_from_masters_0_bresp ; - assign core$cpu_imem_master_bvalid = fabric$v_from_masters_0_bvalid ; - assign core$cpu_imem_master_rdata = fabric$v_from_masters_0_rdata ; - assign core$cpu_imem_master_rid = fabric$v_from_masters_0_rid ; - assign core$cpu_imem_master_rlast = fabric$v_from_masters_0_rlast ; - assign core$cpu_imem_master_rresp = fabric$v_from_masters_0_rresp ; - assign core$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ; - assign core$cpu_imem_master_wready = fabric$v_from_masters_0_wready ; - assign core$cpu_reset_server_request_put = 1'd1 ; - assign core$nmi_req_set_not_clear = 1'd0 ; - assign core$set_verbosity_logdelay = set_verbosity_logdelay ; - assign core$set_verbosity_verbosity = set_verbosity_verbosity ; - assign core$EN_set_verbosity = EN_set_verbosity ; - assign core$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; - assign core$EN_cpu_reset_server_response_get = MUX_rg_state$write_1__SEL_2 ; - - // submodule fabric - assign fabric$set_verbosity_verbosity = 4'h0 ; - assign fabric$v_from_masters_0_araddr = core$cpu_imem_master_araddr ; - assign fabric$v_from_masters_0_arburst = core$cpu_imem_master_arburst ; - assign fabric$v_from_masters_0_arcache = core$cpu_imem_master_arcache ; - assign fabric$v_from_masters_0_arid = core$cpu_imem_master_arid ; - assign fabric$v_from_masters_0_arlen = core$cpu_imem_master_arlen ; - assign fabric$v_from_masters_0_arlock = core$cpu_imem_master_arlock ; - assign fabric$v_from_masters_0_arprot = core$cpu_imem_master_arprot ; - assign fabric$v_from_masters_0_arqos = core$cpu_imem_master_arqos ; - assign fabric$v_from_masters_0_arregion = core$cpu_imem_master_arregion ; - assign fabric$v_from_masters_0_arsize = core$cpu_imem_master_arsize ; - assign fabric$v_from_masters_0_arvalid = core$cpu_imem_master_arvalid ; - assign fabric$v_from_masters_0_awaddr = core$cpu_imem_master_awaddr ; - assign fabric$v_from_masters_0_awburst = core$cpu_imem_master_awburst ; - assign fabric$v_from_masters_0_awcache = core$cpu_imem_master_awcache ; - assign fabric$v_from_masters_0_awid = core$cpu_imem_master_awid ; - assign fabric$v_from_masters_0_awlen = core$cpu_imem_master_awlen ; - assign fabric$v_from_masters_0_awlock = core$cpu_imem_master_awlock ; - assign fabric$v_from_masters_0_awprot = core$cpu_imem_master_awprot ; - assign fabric$v_from_masters_0_awqos = core$cpu_imem_master_awqos ; - assign fabric$v_from_masters_0_awregion = core$cpu_imem_master_awregion ; - assign fabric$v_from_masters_0_awsize = core$cpu_imem_master_awsize ; - assign fabric$v_from_masters_0_awvalid = core$cpu_imem_master_awvalid ; - assign fabric$v_from_masters_0_bready = core$cpu_imem_master_bready ; - assign fabric$v_from_masters_0_rready = core$cpu_imem_master_rready ; - assign fabric$v_from_masters_0_wdata = core$cpu_imem_master_wdata ; - assign fabric$v_from_masters_0_wid = core$cpu_imem_master_wid ; - assign fabric$v_from_masters_0_wlast = core$cpu_imem_master_wlast ; - assign fabric$v_from_masters_0_wstrb = core$cpu_imem_master_wstrb ; - assign fabric$v_from_masters_0_wvalid = core$cpu_imem_master_wvalid ; - assign fabric$v_from_masters_1_araddr = core$cpu_dmem_master_araddr ; - assign fabric$v_from_masters_1_arburst = core$cpu_dmem_master_arburst ; - assign fabric$v_from_masters_1_arcache = core$cpu_dmem_master_arcache ; - assign fabric$v_from_masters_1_arid = core$cpu_dmem_master_arid ; - assign fabric$v_from_masters_1_arlen = core$cpu_dmem_master_arlen ; - assign fabric$v_from_masters_1_arlock = core$cpu_dmem_master_arlock ; - assign fabric$v_from_masters_1_arprot = core$cpu_dmem_master_arprot ; - assign fabric$v_from_masters_1_arqos = core$cpu_dmem_master_arqos ; - assign fabric$v_from_masters_1_arregion = core$cpu_dmem_master_arregion ; - assign fabric$v_from_masters_1_arsize = core$cpu_dmem_master_arsize ; - assign fabric$v_from_masters_1_arvalid = core$cpu_dmem_master_arvalid ; - assign fabric$v_from_masters_1_awaddr = core$cpu_dmem_master_awaddr ; - assign fabric$v_from_masters_1_awburst = core$cpu_dmem_master_awburst ; - assign fabric$v_from_masters_1_awcache = core$cpu_dmem_master_awcache ; - assign fabric$v_from_masters_1_awid = core$cpu_dmem_master_awid ; - assign fabric$v_from_masters_1_awlen = core$cpu_dmem_master_awlen ; - assign fabric$v_from_masters_1_awlock = core$cpu_dmem_master_awlock ; - assign fabric$v_from_masters_1_awprot = core$cpu_dmem_master_awprot ; - assign fabric$v_from_masters_1_awqos = core$cpu_dmem_master_awqos ; - assign fabric$v_from_masters_1_awregion = core$cpu_dmem_master_awregion ; - assign fabric$v_from_masters_1_awsize = core$cpu_dmem_master_awsize ; - assign fabric$v_from_masters_1_awvalid = core$cpu_dmem_master_awvalid ; - assign fabric$v_from_masters_1_bready = core$cpu_dmem_master_bready ; - assign fabric$v_from_masters_1_rready = core$cpu_dmem_master_rready ; - assign fabric$v_from_masters_1_wdata = core$cpu_dmem_master_wdata ; - assign fabric$v_from_masters_1_wid = core$cpu_dmem_master_wid ; - assign fabric$v_from_masters_1_wlast = core$cpu_dmem_master_wlast ; - assign fabric$v_from_masters_1_wstrb = core$cpu_dmem_master_wstrb ; - assign fabric$v_from_masters_1_wvalid = core$cpu_dmem_master_wvalid ; - assign fabric$v_to_slaves_0_arready = - boot_rom_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_0_awready = - boot_rom_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_0_bid = boot_rom_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_0_bresp = - boot_rom_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_0_bvalid = - boot_rom_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_0_rdata = - boot_rom_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_0_rid = boot_rom_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_0_rlast = - boot_rom_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_0_rresp = - boot_rom_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_0_rvalid = - boot_rom_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_0_wready = - boot_rom_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_1_arready = - mem0_controller_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_1_awready = - mem0_controller_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_1_bid = - mem0_controller_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_1_bresp = - mem0_controller_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_1_bvalid = - mem0_controller_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_1_rdata = - mem0_controller_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_1_rid = - mem0_controller_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_1_rlast = - mem0_controller_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_1_rresp = - mem0_controller_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_1_rvalid = - mem0_controller_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_1_wready = - mem0_controller_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_2_arready = uart0$slave_arready ; - assign fabric$v_to_slaves_2_awready = uart0$slave_awready ; - assign fabric$v_to_slaves_2_bid = uart0$slave_bid ; - assign fabric$v_to_slaves_2_bresp = uart0$slave_bresp ; - assign fabric$v_to_slaves_2_bvalid = uart0$slave_bvalid ; - assign fabric$v_to_slaves_2_rdata = uart0$slave_rdata ; - assign fabric$v_to_slaves_2_rid = uart0$slave_rid ; - assign fabric$v_to_slaves_2_rlast = uart0$slave_rlast ; - assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; - assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; - assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; - assign fabric$EN_set_verbosity = 1'b0 ; - - // submodule mem0_controller - assign mem0_controller$set_addr_map_addr_base = - soc_map$m_mem0_controller_addr_base ; - assign mem0_controller$set_addr_map_addr_lim = - soc_map$m_mem0_controller_addr_lim ; - assign mem0_controller$set_watch_tohost_tohost_addr = - set_watch_tohost_tohost_addr ; - assign mem0_controller$set_watch_tohost_watch_tohost = - set_watch_tohost_watch_tohost ; - assign mem0_controller$slave_araddr = - mem0_controller_axi4_deburster$to_slave_araddr ; - assign mem0_controller$slave_arburst = - mem0_controller_axi4_deburster$to_slave_arburst ; - assign mem0_controller$slave_arcache = - mem0_controller_axi4_deburster$to_slave_arcache ; - assign mem0_controller$slave_arid = - mem0_controller_axi4_deburster$to_slave_arid ; - assign mem0_controller$slave_arlen = - mem0_controller_axi4_deburster$to_slave_arlen ; - assign mem0_controller$slave_arlock = - mem0_controller_axi4_deburster$to_slave_arlock ; - assign mem0_controller$slave_arprot = - mem0_controller_axi4_deburster$to_slave_arprot ; - assign mem0_controller$slave_arqos = - mem0_controller_axi4_deburster$to_slave_arqos ; - assign mem0_controller$slave_arregion = - mem0_controller_axi4_deburster$to_slave_arregion ; - assign mem0_controller$slave_arsize = - mem0_controller_axi4_deburster$to_slave_arsize ; - assign mem0_controller$slave_arvalid = - mem0_controller_axi4_deburster$to_slave_arvalid ; - assign mem0_controller$slave_awaddr = - mem0_controller_axi4_deburster$to_slave_awaddr ; - assign mem0_controller$slave_awburst = - mem0_controller_axi4_deburster$to_slave_awburst ; - assign mem0_controller$slave_awcache = - mem0_controller_axi4_deburster$to_slave_awcache ; - assign mem0_controller$slave_awid = - mem0_controller_axi4_deburster$to_slave_awid ; - assign mem0_controller$slave_awlen = - mem0_controller_axi4_deburster$to_slave_awlen ; - assign mem0_controller$slave_awlock = - mem0_controller_axi4_deburster$to_slave_awlock ; - assign mem0_controller$slave_awprot = - mem0_controller_axi4_deburster$to_slave_awprot ; - assign mem0_controller$slave_awqos = - mem0_controller_axi4_deburster$to_slave_awqos ; - assign mem0_controller$slave_awregion = - mem0_controller_axi4_deburster$to_slave_awregion ; - assign mem0_controller$slave_awsize = - mem0_controller_axi4_deburster$to_slave_awsize ; - assign mem0_controller$slave_awvalid = - mem0_controller_axi4_deburster$to_slave_awvalid ; - assign mem0_controller$slave_bready = - mem0_controller_axi4_deburster$to_slave_bready ; - assign mem0_controller$slave_rready = - mem0_controller_axi4_deburster$to_slave_rready ; - assign mem0_controller$slave_wdata = - mem0_controller_axi4_deburster$to_slave_wdata ; - assign mem0_controller$slave_wid = - mem0_controller_axi4_deburster$to_slave_wid ; - assign mem0_controller$slave_wlast = - mem0_controller_axi4_deburster$to_slave_wlast ; - assign mem0_controller$slave_wstrb = - mem0_controller_axi4_deburster$to_slave_wstrb ; - assign mem0_controller$slave_wvalid = - mem0_controller_axi4_deburster$to_slave_wvalid ; - assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; - assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; - assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_to_raw_mem_request_get = - EN_to_raw_mem_request_get ; - assign mem0_controller$EN_to_raw_mem_response_put = - EN_to_raw_mem_response_put ; - assign mem0_controller$EN_set_watch_tohost = EN_set_watch_tohost ; - - // submodule mem0_controller_axi4_deburster - assign mem0_controller_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_1_araddr ; - assign mem0_controller_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_1_arburst ; - assign mem0_controller_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_1_arcache ; - assign mem0_controller_axi4_deburster$from_master_arid = - fabric$v_to_slaves_1_arid ; - assign mem0_controller_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_1_arlen ; - assign mem0_controller_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_1_arlock ; - assign mem0_controller_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_1_arprot ; - assign mem0_controller_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_1_arqos ; - assign mem0_controller_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_1_arregion ; - assign mem0_controller_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_1_arsize ; - assign mem0_controller_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_1_arvalid ; - assign mem0_controller_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_1_awaddr ; - assign mem0_controller_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_1_awburst ; - assign mem0_controller_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_1_awcache ; - assign mem0_controller_axi4_deburster$from_master_awid = - fabric$v_to_slaves_1_awid ; - assign mem0_controller_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_1_awlen ; - assign mem0_controller_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_1_awlock ; - assign mem0_controller_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_1_awprot ; - assign mem0_controller_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_1_awqos ; - assign mem0_controller_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_1_awregion ; - assign mem0_controller_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_1_awsize ; - assign mem0_controller_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_1_awvalid ; - assign mem0_controller_axi4_deburster$from_master_bready = - fabric$v_to_slaves_1_bready ; - assign mem0_controller_axi4_deburster$from_master_rready = - fabric$v_to_slaves_1_rready ; - assign mem0_controller_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_1_wdata ; - assign mem0_controller_axi4_deburster$from_master_wid = - fabric$v_to_slaves_1_wid ; - assign mem0_controller_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_1_wlast ; - assign mem0_controller_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_1_wstrb ; - assign mem0_controller_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_1_wvalid ; - assign mem0_controller_axi4_deburster$to_slave_arready = - mem0_controller$slave_arready ; - assign mem0_controller_axi4_deburster$to_slave_awready = - mem0_controller$slave_awready ; - assign mem0_controller_axi4_deburster$to_slave_bid = - mem0_controller$slave_bid ; - assign mem0_controller_axi4_deburster$to_slave_bresp = - mem0_controller$slave_bresp ; - assign mem0_controller_axi4_deburster$to_slave_bvalid = - mem0_controller$slave_bvalid ; - assign mem0_controller_axi4_deburster$to_slave_rdata = - mem0_controller$slave_rdata ; - assign mem0_controller_axi4_deburster$to_slave_rid = - mem0_controller$slave_rid ; - assign mem0_controller_axi4_deburster$to_slave_rlast = - mem0_controller$slave_rlast ; - assign mem0_controller_axi4_deburster$to_slave_rresp = - mem0_controller$slave_rresp ; - assign mem0_controller_axi4_deburster$to_slave_rvalid = - mem0_controller$slave_rvalid ; - assign mem0_controller_axi4_deburster$to_slave_wready = - mem0_controller$slave_wready ; - assign mem0_controller_axi4_deburster$EN_reset = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule uart0 - assign uart0$put_from_console_put = put_from_console_put ; - assign uart0$set_addr_map_addr_base = soc_map$m_uart0_addr_base ; - assign uart0$set_addr_map_addr_lim = soc_map$m_uart0_addr_lim ; - assign uart0$slave_araddr = fabric$v_to_slaves_2_araddr ; - assign uart0$slave_arburst = fabric$v_to_slaves_2_arburst ; - assign uart0$slave_arcache = fabric$v_to_slaves_2_arcache ; - assign uart0$slave_arid = fabric$v_to_slaves_2_arid ; - assign uart0$slave_arlen = fabric$v_to_slaves_2_arlen ; - assign uart0$slave_arlock = fabric$v_to_slaves_2_arlock ; - assign uart0$slave_arprot = fabric$v_to_slaves_2_arprot ; - assign uart0$slave_arqos = fabric$v_to_slaves_2_arqos ; - assign uart0$slave_arregion = fabric$v_to_slaves_2_arregion ; - assign uart0$slave_arsize = fabric$v_to_slaves_2_arsize ; - assign uart0$slave_arvalid = fabric$v_to_slaves_2_arvalid ; - assign uart0$slave_awaddr = fabric$v_to_slaves_2_awaddr ; - assign uart0$slave_awburst = fabric$v_to_slaves_2_awburst ; - assign uart0$slave_awcache = fabric$v_to_slaves_2_awcache ; - assign uart0$slave_awid = fabric$v_to_slaves_2_awid ; - assign uart0$slave_awlen = fabric$v_to_slaves_2_awlen ; - assign uart0$slave_awlock = fabric$v_to_slaves_2_awlock ; - assign uart0$slave_awprot = fabric$v_to_slaves_2_awprot ; - assign uart0$slave_awqos = fabric$v_to_slaves_2_awqos ; - assign uart0$slave_awregion = fabric$v_to_slaves_2_awregion ; - assign uart0$slave_awsize = fabric$v_to_slaves_2_awsize ; - assign uart0$slave_awvalid = fabric$v_to_slaves_2_awvalid ; - assign uart0$slave_bready = fabric$v_to_slaves_2_bready ; - assign uart0$slave_rready = fabric$v_to_slaves_2_rready ; - assign uart0$slave_wdata = fabric$v_to_slaves_2_wdata ; - assign uart0$slave_wid = fabric$v_to_slaves_2_wid ; - assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; - assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; - assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_get_to_console_get = EN_get_to_console_get ; - assign uart0$EN_put_from_console_put = EN_put_from_console_put ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - begin - v__h11286 = $stime; - #0; - end - v__h11280 = v__h11286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - $display("%0d:%m.rl_reset_start_initial ...", v__h11280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - begin - v__h11556 = $stime; - #0; - end - v__h11550 = v__h11556 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - $display("%0d:%m.rl_reset_complete_initial", v__h11550); - end - // synopsys translate_on -endmodule // mkSoC_Top - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v deleted file mode 100644 index a195f14f..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkTop_HW_Side.v +++ /dev/null @@ -1,255 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// CLK I 1 clock -// RST_N I 1 reset -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTop_HW_Side(CLK, - RST_N); - input CLK; - input RST_N; - - // register rg_banner_printed - reg rg_banner_printed; - wire rg_banner_printed$D_IN, rg_banner_printed$EN; - - // ports of submodule mem_model - wire [352 : 0] mem_model$mem_server_request_put; - wire [255 : 0] mem_model$mem_server_response_get; - wire mem_model$EN_mem_server_request_put, - mem_model$EN_mem_server_response_get, - mem_model$RDY_mem_server_request_put, - mem_model$RDY_mem_server_response_get; - - // ports of submodule soc_top - wire [352 : 0] soc_top$to_raw_mem_request_get; - wire [255 : 0] soc_top$to_raw_mem_response_put; - wire [63 : 0] soc_top$set_verbosity_logdelay, - soc_top$set_watch_tohost_tohost_addr; - wire [7 : 0] soc_top$get_to_console_get, - soc_top$put_from_console_put, - soc_top$status; - wire [3 : 0] soc_top$set_verbosity_verbosity; - wire soc_top$EN_get_to_console_get, - soc_top$EN_put_from_console_put, - soc_top$EN_set_verbosity, - soc_top$EN_set_watch_tohost, - soc_top$EN_to_raw_mem_request_get, - soc_top$EN_to_raw_mem_response_put, - soc_top$RDY_get_to_console_get, - soc_top$RDY_to_raw_mem_request_get, - soc_top$RDY_to_raw_mem_response_put, - soc_top$set_watch_tohost_watch_tohost; - - // rule scheduling signals - wire CAN_FIRE_RL_memCnx_ClientServerRequest, - CAN_FIRE_RL_memCnx_ClientServerResponse, - CAN_FIRE_RL_rl_relay_console_out, - CAN_FIRE_RL_rl_step0, - CAN_FIRE_RL_rl_terminate, - WILL_FIRE_RL_memCnx_ClientServerRequest, - WILL_FIRE_RL_memCnx_ClientServerResponse, - WILL_FIRE_RL_rl_relay_console_out, - WILL_FIRE_RL_rl_step0, - WILL_FIRE_RL_rl_terminate; - - // declarations used by system tasks - // synopsys translate_off - reg TASK_testplusargs___d12; - reg TASK_testplusargs___d11; - reg [31 : 0] v__h536; - reg [31 : 0] v__h530; - // synopsys translate_on - - // submodule mem_model - mkMem_Model mem_model(.CLK(CLK), - .RST_N(RST_N), - .mem_server_request_put(mem_model$mem_server_request_put), - .EN_mem_server_request_put(mem_model$EN_mem_server_request_put), - .EN_mem_server_response_get(mem_model$EN_mem_server_response_get), - .RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put), - .mem_server_response_get(mem_model$mem_server_response_get), - .RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get)); - - // submodule soc_top - mkSoC_Top soc_top(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(soc_top$put_from_console_put), - .set_verbosity_logdelay(soc_top$set_verbosity_logdelay), - .set_verbosity_verbosity(soc_top$set_verbosity_verbosity), - .set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost), - .to_raw_mem_response_put(soc_top$to_raw_mem_response_put), - .EN_set_verbosity(soc_top$EN_set_verbosity), - .EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put), - .EN_get_to_console_get(soc_top$EN_get_to_console_get), - .EN_put_from_console_put(soc_top$EN_put_from_console_put), - .EN_set_watch_tohost(soc_top$EN_set_watch_tohost), - .RDY_set_verbosity(), - .to_raw_mem_request_get(soc_top$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put), - .get_to_console_get(soc_top$get_to_console_get), - .RDY_get_to_console_get(soc_top$RDY_get_to_console_get), - .RDY_put_from_console_put(), - .status(soc_top$status), - .RDY_set_watch_tohost()); - - // rule RL_rl_step0 - assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ; - assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ; - - // rule RL_rl_terminate - assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ; - assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ; - - // rule RL_rl_relay_console_out - assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - - // rule RL_memCnx_ClientServerRequest - assign CAN_FIRE_RL_memCnx_ClientServerRequest = - soc_top$RDY_to_raw_mem_request_get && - mem_model$RDY_mem_server_request_put ; - assign WILL_FIRE_RL_memCnx_ClientServerRequest = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - - // rule RL_memCnx_ClientServerResponse - assign CAN_FIRE_RL_memCnx_ClientServerResponse = - soc_top$RDY_to_raw_mem_response_put && - mem_model$RDY_mem_server_response_get ; - assign WILL_FIRE_RL_memCnx_ClientServerResponse = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // register rg_banner_printed - assign rg_banner_printed$D_IN = 1'd1 ; - assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ; - - // submodule mem_model - assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ; - assign mem_model$EN_mem_server_request_put = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign mem_model$EN_mem_server_response_get = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // submodule soc_top - assign soc_top$put_from_console_put = 8'h0 ; - assign soc_top$set_verbosity_logdelay = 64'd0 ; - assign soc_top$set_verbosity_verbosity = - TASK_testplusargs___d11 ? - 4'd2 : - (TASK_testplusargs___d12 ? 4'd1 : 4'd0) ; - assign soc_top$set_watch_tohost_tohost_addr = 64'h0 ; - assign soc_top$set_watch_tohost_watch_tohost = 1'b0 ; - assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ; - assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ; - assign soc_top$EN_to_raw_mem_request_get = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign soc_top$EN_to_raw_mem_response_put = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ; - assign soc_top$EN_put_from_console_put = 1'b0 ; - assign soc_top$EN_set_watch_tohost = 1'b0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_banner_printed$EN) - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_banner_printed = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Bluespec RISC-V standalone system simulation v1.2"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d12 = $test$plusargs("v1"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d11 = $test$plusargs("v2"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h536 = $stime; - #0; - end - v__h530 = v__h536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $display("%0d: %m.rl_terminate: soc_top status is 0x%0h (= 0d%0d)", - v__h530, - soc_top$status, - soc_top$status); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) - $write("%c", soc_top$get_to_console_get); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001); - end - // synopsys translate_on -endmodule // mkTop_HW_Side - diff --git a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkUART.v b/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkUART.v deleted file mode 100644 index 033775ea..00000000 --- a/builds/RV64ACIMU_Piccolo_iverilog/Verilog_RTL/mkUART.v +++ /dev/null @@ -1,2925 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// intr O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// put_from_console_put I 8 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_put_from_console_put I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkUART(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - intr); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method intr - output intr; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [7 : 0] get_to_console_get; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - intr, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register cfg_verbosity - reg [7 : 0] cfg_verbosity; - wire [7 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_dll - reg [7 : 0] rg_dll; - wire [7 : 0] rg_dll$D_IN; - wire rg_dll$EN; - - // register rg_dlm - reg [7 : 0] rg_dlm; - wire [7 : 0] rg_dlm$D_IN; - wire rg_dlm$EN; - - // register rg_fcr - reg [7 : 0] rg_fcr; - wire [7 : 0] rg_fcr$D_IN; - wire rg_fcr$EN; - - // register rg_ier - reg [7 : 0] rg_ier; - wire [7 : 0] rg_ier$D_IN; - wire rg_ier$EN; - - // register rg_lcr - reg [7 : 0] rg_lcr; - wire [7 : 0] rg_lcr$D_IN; - wire rg_lcr$EN; - - // register rg_lsr - reg [7 : 0] rg_lsr; - reg [7 : 0] rg_lsr$D_IN; - wire rg_lsr$EN; - - // register rg_mcr - reg [7 : 0] rg_mcr; - wire [7 : 0] rg_mcr$D_IN; - wire rg_mcr$EN; - - // register rg_msr - reg [7 : 0] rg_msr; - wire [7 : 0] rg_msr$D_IN; - wire rg_msr$EN; - - // register rg_rbr - reg [7 : 0] rg_rbr; - wire [7 : 0] rg_rbr$D_IN; - wire rg_rbr$EN; - - // register rg_scr - reg [7 : 0] rg_scr; - wire [7 : 0] rg_scr$D_IN; - wire rg_scr$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_thr - reg [7 : 0] rg_thr; - wire [7 : 0] rg_thr$D_IN; - wire rg_thr$EN; - - // ports of submodule f_from_console - wire [7 : 0] f_from_console$D_IN, f_from_console$D_OUT; - wire f_from_console$CLR, - f_from_console$DEQ, - f_from_console$EMPTY_N, - f_from_console$ENQ, - f_from_console$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_to_console - wire [7 : 0] f_to_console$D_IN, f_to_console$D_OUT; - wire f_to_console$CLR, - f_to_console$DEQ, - f_to_console$EMPTY_N, - f_to_console$ENQ, - f_to_console$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_receive, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_receive, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_rg_lsr$write_1__VAL_3; - wire MUX_rg_lsr$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2519; - reg [31 : 0] v__h2187; - reg [31 : 0] v__h2025; - reg [31 : 0] v__h2898; - reg [31 : 0] v__h3244; - reg [31 : 0] v__h4006; - reg [31 : 0] v__h3449; - reg [31 : 0] v__h4306; - reg [31 : 0] v__h4749; - reg [31 : 0] v__h4859; - reg [31 : 0] v__h1811; - reg [31 : 0] v__h1805; - reg [31 : 0] v__h2019; - reg [31 : 0] v__h2181; - reg [31 : 0] v__h2513; - reg [31 : 0] v__h2892; - reg [31 : 0] v__h3238; - reg [31 : 0] v__h3443; - reg [31 : 0] v__h4000; - reg [31 : 0] v__h4300; - reg [31 : 0] v__h4743; - reg [31 : 0] v__h4853; - // synopsys translate_on - - // remaining internal signals - reg [7 : 0] y_avValue_snd__h2683; - wire [63 : 0] rdata__h2759, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133; - wire [7 : 0] fn_iir__h1356, - new_lsr__h4516, - x__h2797, - y_avValue_snd__h2696, - y_avValue_snd__h2709, - y_avValue_snd__h2724, - y_avValue_snd__h2738; - wire [1 : 0] rdr_rresp__h2792, - v__h3147, - v__h3395, - v__h3575, - y_avValue_fst__h2737, - y_avValue_fst__h2751; - wire NOT_cfg_verbosity_read_ULE_1_24___d125, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188, - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method get_to_console_get - assign get_to_console_get = f_to_console$D_OUT ; - assign RDY_get_to_console_get = f_to_console$EMPTY_N ; - assign CAN_FIRE_get_to_console_get = f_to_console$EMPTY_N ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = f_from_console$FULL_N ; - assign CAN_FIRE_put_from_console_put = f_from_console$FULL_N ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method intr - assign intr = !fn_iir__h1356[0] ; - - // submodule f_from_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_from_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_from_console$D_IN), - .ENQ(f_from_console$ENQ), - .DEQ(f_from_console$DEQ), - .CLR(f_from_console$CLR), - .D_OUT(f_from_console$D_OUT), - .FULL_N(f_from_console$FULL_N), - .EMPTY_N(f_from_console$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_to_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_to_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_to_console$D_IN), - .ENQ(f_to_console$ENQ), - .DEQ(f_to_console$DEQ), - .CLR(f_to_console$CLR), - .D_OUT(f_to_console$D_OUT), - .FULL_N(f_to_console$FULL_N), - .EMPTY_N(f_to_console$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 && - rg_state ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_receive - assign CAN_FIRE_RL_rl_receive = f_from_console$EMPTY_N && !rg_lsr[0] ; - assign WILL_FIRE_RL_rl_receive = - CAN_FIRE_RL_rl_receive && !WILL_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_rg_lsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 ; - assign MUX_rg_lsr$write_1__VAL_3 = { rg_lsr[7:1], 1'd0 } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 8'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_dll - assign rg_dll$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dll$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 || - WILL_FIRE_RL_rl_reset ; - - // register rg_dlm - assign rg_dlm$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dlm$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 || - WILL_FIRE_RL_rl_reset ; - - // register rg_fcr - assign rg_fcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_fcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h2 || - WILL_FIRE_RL_rl_reset ; - - // register rg_ier - assign rg_ier$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_ier$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lcr - assign rg_lcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_lcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h3 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lsr - always@(WILL_FIRE_RL_rl_reset or - WILL_FIRE_RL_rl_receive or - new_lsr__h4516 or - MUX_rg_lsr$write_1__SEL_3 or MUX_rg_lsr$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset: rg_lsr$D_IN = 8'd96; - WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h4516; - MUX_rg_lsr$write_1__SEL_3: rg_lsr$D_IN = MUX_rg_lsr$write_1__VAL_3; - default: rg_lsr$D_IN = 8'b10101010 /* unspecified value */ ; - endcase - assign rg_lsr$EN = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 || - WILL_FIRE_RL_rl_receive || - WILL_FIRE_RL_rl_reset ; - - // register rg_mcr - assign rg_mcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_mcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h4 || - WILL_FIRE_RL_rl_reset ; - - // register rg_msr - assign rg_msr$D_IN = 8'd0 ; - assign rg_msr$EN = CAN_FIRE_RL_rl_reset ; - - // register rg_rbr - assign rg_rbr$D_IN = f_from_console$D_OUT ; - assign rg_rbr$EN = WILL_FIRE_RL_rl_receive ; - - // register rg_scr - assign rg_scr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_scr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h7 || - WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = 1'd1 ; - assign rg_state$EN = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // register rg_thr - assign rg_thr$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_thr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - - // submodule f_from_console - assign f_from_console$D_IN = put_from_console_put ; - assign f_from_console$ENQ = EN_put_from_console_put ; - assign f_from_console$DEQ = WILL_FIRE_RL_rl_receive ; - assign f_from_console$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_to_console - assign f_to_console$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign f_to_console$ENQ = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - assign f_to_console$DEQ = EN_get_to_console_get ; - assign f_to_console$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h2759, - rdr_rresp__h2792, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3147 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_24___d125 = cfg_verbosity > 8'd1 ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - slave_xactor_f_wr_data$D_OUT[0] ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - !slave_xactor_f_wr_data$D_OUT[0] ; - assign fn_iir__h1356 = - (rg_ier[0] && rg_lsr[0]) ? 8'h04 : (rg_ier[1] ? 8'h02 : 8'd0) ; - assign new_lsr__h4516 = { rg_lsr[7:1], 1'd1 } ; - assign rdata__h2759 = { 56'd0, x__h2797 } ; - assign rdr_rresp__h2792 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0) ? - y_avValue_fst__h2751 : - 2'b10 ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 = - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - rg_lcr[7] ; - assign slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 = - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1] || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7] || - f_to_console$FULL_N) ; - assign v__h3147 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) ? - 2'b10 : - v__h3395 ; - assign v__h3395 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0) ? - v__h3575 : - 2'b11 ; - assign v__h3575 = y_avValue_fst__h2737 ; - assign x__h2797 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0 || - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) ? - 8'd0 : - y_avValue_snd__h2738 ; - assign y_avValue_fst__h2737 = 2'b0 ; - assign y_avValue_fst__h2751 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0) ? - y_avValue_fst__h2737 : - 2'b11 ; - assign y_avValue_snd__h2696 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - rg_lcr[7]) ? - rg_dlm : - y_avValue_snd__h2683 ; - assign y_avValue_snd__h2709 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - !rg_lcr[7]) ? - rg_ier : - y_avValue_snd__h2696 ; - assign y_avValue_snd__h2724 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - rg_lcr[7]) ? - rg_dll : - y_avValue_snd__h2709 ; - assign y_avValue_snd__h2738 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7]) ? - rg_rbr : - y_avValue_snd__h2724 ; - always@(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 or - fn_iir__h1356 or rg_lcr or rg_mcr or rg_lsr or rg_msr or rg_scr) - begin - case (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3]) - 3'h2: y_avValue_snd__h2683 = fn_iir__h1356; - 3'h3: y_avValue_snd__h2683 = rg_lcr; - 3'h4: y_avValue_snd__h2683 = rg_mcr; - 3'h5: y_avValue_snd__h2683 = rg_lsr; - 3'h6: y_avValue_snd__h2683 = rg_msr; - 3'h7: y_avValue_snd__h2683 = rg_scr; - default: y_avValue_snd__h2683 = 8'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dll <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dlm <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_fcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_ier <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lsr <= `BSV_ASSIGNMENT_DELAY 8'd96; - rg_mcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_msr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_scr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_dll$EN) rg_dll <= `BSV_ASSIGNMENT_DELAY rg_dll$D_IN; - if (rg_dlm$EN) rg_dlm <= `BSV_ASSIGNMENT_DELAY rg_dlm$D_IN; - if (rg_fcr$EN) rg_fcr <= `BSV_ASSIGNMENT_DELAY rg_fcr$D_IN; - if (rg_ier$EN) rg_ier <= `BSV_ASSIGNMENT_DELAY rg_ier$D_IN; - if (rg_lcr$EN) rg_lcr <= `BSV_ASSIGNMENT_DELAY rg_lcr$D_IN; - if (rg_lsr$EN) rg_lsr <= `BSV_ASSIGNMENT_DELAY rg_lsr$D_IN; - if (rg_mcr$EN) rg_mcr <= `BSV_ASSIGNMENT_DELAY rg_mcr$D_IN; - if (rg_msr$EN) rg_msr <= `BSV_ASSIGNMENT_DELAY rg_msr$D_IN; - if (rg_scr$EN) rg_scr <= `BSV_ASSIGNMENT_DELAY rg_scr$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_rbr$EN) rg_rbr <= `BSV_ASSIGNMENT_DELAY rg_rbr$D_IN; - if (rg_thr$EN) rg_thr <= `BSV_ASSIGNMENT_DELAY rg_thr$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 8'hAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_dll = 8'hAA; - rg_dlm = 8'hAA; - rg_fcr = 8'hAA; - rg_ier = 8'hAA; - rg_lcr = 8'hAA; - rg_lsr = 8'hAA; - rg_mcr = 8'hAA; - rg_msr = 8'hAA; - rg_rbr = 8'hAA; - rg_scr = 8'hAA; - rg_state = 1'h0; - rg_thr = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - begin - v__h2519 = $stime; - #0; - end - v__h2513 = v__h2519 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2513); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - begin - v__h2187 = $stime; - #0; - end - v__h2181 = v__h2187 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2181); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - begin - v__h2025 = $stime; - #0; - end - v__h2019 = v__h2025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: misaligned addr", - v__h2019); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h2898 = $stime; - #0; - end - v__h2892 = v__h2898 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_rd_req", v__h2892); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdata__h2759); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdr_rresp__h2792); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - begin - v__h3244 = $stime; - #0; - end - v__h3238 = v__h3244 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $display("%0d: ERROR: UART.rl_process_wr_req: misaligned addr", - v__h3238); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - begin - v__h4006 = $stime; - #0; - end - v__h4000 = v__h4006 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h4000); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - begin - v__h3449 = $stime; - #0; - end - v__h3443 = v__h3449 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h3443); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h4306 = $stime; - #0; - end - v__h4300 = v__h4306 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_wr_req", v__h4300); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", v__h3147); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h4749 = $stime; - #0; - end - v__h4743 = v__h4749 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_base 0x%0h is not 8-Byte-aligned", - v__h4743, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h4859 = $stime; - #0; - end - v__h4853 = v__h4859 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_lim 0x%0h is not 8-Byte-aligned", - v__h4853, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_receive && NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("UART_Model.rl_receive: received char 0x%0h; new_lsr = 0x%0h", - f_from_console$D_OUT, - new_lsr__h4516); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - begin - v__h1811 = $stime; - #0; - end - v__h1805 = v__h1811 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - $display("%0d: UART.rl_reset", v__h1805); - end - // synopsys translate_on -endmodule // mkUART - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v deleted file mode 100644 index 1cb3bfa4..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkAXI4_Deburster_A.v +++ /dev/null @@ -1,1415 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// from_master_awready O 1 reg -// from_master_wready O 1 reg -// from_master_bvalid O 1 reg -// from_master_bid O 4 reg -// from_master_bresp O 2 reg -// from_master_arready O 1 reg -// from_master_rvalid O 1 reg -// from_master_rid O 4 reg -// from_master_rdata O 64 reg -// from_master_rresp O 2 reg -// from_master_rlast O 1 reg -// to_slave_awvalid O 1 reg -// to_slave_awid O 4 reg -// to_slave_awaddr O 64 reg -// to_slave_awlen O 8 reg -// to_slave_awsize O 3 reg -// to_slave_awburst O 2 reg -// to_slave_awlock O 1 reg -// to_slave_awcache O 4 reg -// to_slave_awprot O 3 reg -// to_slave_awqos O 4 reg -// to_slave_awregion O 4 reg -// to_slave_wvalid O 1 reg -// to_slave_wid O 4 reg -// to_slave_wdata O 64 reg -// to_slave_wstrb O 8 reg -// to_slave_wlast O 1 reg -// to_slave_bready O 1 reg -// to_slave_arvalid O 1 reg -// to_slave_arid O 4 reg -// to_slave_araddr O 64 reg -// to_slave_arlen O 8 reg -// to_slave_arsize O 3 reg -// to_slave_arburst O 2 reg -// to_slave_arlock O 1 reg -// to_slave_arcache O 4 reg -// to_slave_arprot O 3 reg -// to_slave_arqos O 4 reg -// to_slave_arregion O 4 reg -// to_slave_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// from_master_awvalid I 1 -// from_master_awid I 4 reg -// from_master_awaddr I 64 reg -// from_master_awlen I 8 reg -// from_master_awsize I 3 reg -// from_master_awburst I 2 reg -// from_master_awlock I 1 reg -// from_master_awcache I 4 reg -// from_master_awprot I 3 reg -// from_master_awqos I 4 reg -// from_master_awregion I 4 reg -// from_master_wvalid I 1 -// from_master_wid I 4 reg -// from_master_wdata I 64 reg -// from_master_wstrb I 8 reg -// from_master_wlast I 1 reg -// from_master_bready I 1 -// from_master_arvalid I 1 -// from_master_arid I 4 reg -// from_master_araddr I 64 reg -// from_master_arlen I 8 reg -// from_master_arsize I 3 reg -// from_master_arburst I 2 reg -// from_master_arlock I 1 reg -// from_master_arcache I 4 reg -// from_master_arprot I 3 reg -// from_master_arqos I 4 reg -// from_master_arregion I 4 reg -// from_master_rready I 1 -// to_slave_awready I 1 -// to_slave_wready I 1 -// to_slave_bvalid I 1 -// to_slave_bid I 4 reg -// to_slave_bresp I 2 reg -// to_slave_arready I 1 -// to_slave_rvalid I 1 -// to_slave_rid I 4 reg -// to_slave_rdata I 64 reg -// to_slave_rresp I 2 reg -// to_slave_rlast I 1 reg -// EN_reset I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkAXI4_Deburster_A(CLK, - RST_N, - - EN_reset, - RDY_reset, - - from_master_awvalid, - from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion, - - from_master_awready, - - from_master_wvalid, - from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast, - - from_master_wready, - - from_master_bvalid, - - from_master_bid, - - from_master_bresp, - - from_master_bready, - - from_master_arvalid, - from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion, - - from_master_arready, - - from_master_rvalid, - - from_master_rid, - - from_master_rdata, - - from_master_rresp, - - from_master_rlast, - - from_master_rready, - - to_slave_awvalid, - - to_slave_awid, - - to_slave_awaddr, - - to_slave_awlen, - - to_slave_awsize, - - to_slave_awburst, - - to_slave_awlock, - - to_slave_awcache, - - to_slave_awprot, - - to_slave_awqos, - - to_slave_awregion, - - to_slave_awready, - - to_slave_wvalid, - - to_slave_wid, - - to_slave_wdata, - - to_slave_wstrb, - - to_slave_wlast, - - to_slave_wready, - - to_slave_bvalid, - to_slave_bid, - to_slave_bresp, - - to_slave_bready, - - to_slave_arvalid, - - to_slave_arid, - - to_slave_araddr, - - to_slave_arlen, - - to_slave_arsize, - - to_slave_arburst, - - to_slave_arlock, - - to_slave_arcache, - - to_slave_arprot, - - to_slave_arqos, - - to_slave_arregion, - - to_slave_arready, - - to_slave_rvalid, - to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast, - - to_slave_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method from_master_m_awvalid - input from_master_awvalid; - input [3 : 0] from_master_awid; - input [63 : 0] from_master_awaddr; - input [7 : 0] from_master_awlen; - input [2 : 0] from_master_awsize; - input [1 : 0] from_master_awburst; - input from_master_awlock; - input [3 : 0] from_master_awcache; - input [2 : 0] from_master_awprot; - input [3 : 0] from_master_awqos; - input [3 : 0] from_master_awregion; - - // value method from_master_m_awready - output from_master_awready; - - // action method from_master_m_wvalid - input from_master_wvalid; - input [3 : 0] from_master_wid; - input [63 : 0] from_master_wdata; - input [7 : 0] from_master_wstrb; - input from_master_wlast; - - // value method from_master_m_wready - output from_master_wready; - - // value method from_master_m_bvalid - output from_master_bvalid; - - // value method from_master_m_bid - output [3 : 0] from_master_bid; - - // value method from_master_m_bresp - output [1 : 0] from_master_bresp; - - // value method from_master_m_buser - - // action method from_master_m_bready - input from_master_bready; - - // action method from_master_m_arvalid - input from_master_arvalid; - input [3 : 0] from_master_arid; - input [63 : 0] from_master_araddr; - input [7 : 0] from_master_arlen; - input [2 : 0] from_master_arsize; - input [1 : 0] from_master_arburst; - input from_master_arlock; - input [3 : 0] from_master_arcache; - input [2 : 0] from_master_arprot; - input [3 : 0] from_master_arqos; - input [3 : 0] from_master_arregion; - - // value method from_master_m_arready - output from_master_arready; - - // value method from_master_m_rvalid - output from_master_rvalid; - - // value method from_master_m_rid - output [3 : 0] from_master_rid; - - // value method from_master_m_rdata - output [63 : 0] from_master_rdata; - - // value method from_master_m_rresp - output [1 : 0] from_master_rresp; - - // value method from_master_m_rlast - output from_master_rlast; - - // value method from_master_m_ruser - - // action method from_master_m_rready - input from_master_rready; - - // value method to_slave_m_awvalid - output to_slave_awvalid; - - // value method to_slave_m_awid - output [3 : 0] to_slave_awid; - - // value method to_slave_m_awaddr - output [63 : 0] to_slave_awaddr; - - // value method to_slave_m_awlen - output [7 : 0] to_slave_awlen; - - // value method to_slave_m_awsize - output [2 : 0] to_slave_awsize; - - // value method to_slave_m_awburst - output [1 : 0] to_slave_awburst; - - // value method to_slave_m_awlock - output to_slave_awlock; - - // value method to_slave_m_awcache - output [3 : 0] to_slave_awcache; - - // value method to_slave_m_awprot - output [2 : 0] to_slave_awprot; - - // value method to_slave_m_awqos - output [3 : 0] to_slave_awqos; - - // value method to_slave_m_awregion - output [3 : 0] to_slave_awregion; - - // value method to_slave_m_awuser - - // action method to_slave_m_awready - input to_slave_awready; - - // value method to_slave_m_wvalid - output to_slave_wvalid; - - // value method to_slave_m_wid - output [3 : 0] to_slave_wid; - - // value method to_slave_m_wdata - output [63 : 0] to_slave_wdata; - - // value method to_slave_m_wstrb - output [7 : 0] to_slave_wstrb; - - // value method to_slave_m_wlast - output to_slave_wlast; - - // value method to_slave_m_wuser - - // action method to_slave_m_wready - input to_slave_wready; - - // action method to_slave_m_bvalid - input to_slave_bvalid; - input [3 : 0] to_slave_bid; - input [1 : 0] to_slave_bresp; - - // value method to_slave_m_bready - output to_slave_bready; - - // value method to_slave_m_arvalid - output to_slave_arvalid; - - // value method to_slave_m_arid - output [3 : 0] to_slave_arid; - - // value method to_slave_m_araddr - output [63 : 0] to_slave_araddr; - - // value method to_slave_m_arlen - output [7 : 0] to_slave_arlen; - - // value method to_slave_m_arsize - output [2 : 0] to_slave_arsize; - - // value method to_slave_m_arburst - output [1 : 0] to_slave_arburst; - - // value method to_slave_m_arlock - output to_slave_arlock; - - // value method to_slave_m_arcache - output [3 : 0] to_slave_arcache; - - // value method to_slave_m_arprot - output [2 : 0] to_slave_arprot; - - // value method to_slave_m_arqos - output [3 : 0] to_slave_arqos; - - // value method to_slave_m_arregion - output [3 : 0] to_slave_arregion; - - // value method to_slave_m_aruser - - // action method to_slave_m_arready - input to_slave_arready; - - // action method to_slave_m_rvalid - input to_slave_rvalid; - input [3 : 0] to_slave_rid; - input [63 : 0] to_slave_rdata; - input [1 : 0] to_slave_rresp; - input to_slave_rlast; - - // value method to_slave_m_rready - output to_slave_rready; - - // signals for module outputs - wire [63 : 0] from_master_rdata, - to_slave_araddr, - to_slave_awaddr, - to_slave_wdata; - wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb; - wire [3 : 0] from_master_bid, - from_master_rid, - to_slave_arcache, - to_slave_arid, - to_slave_arqos, - to_slave_arregion, - to_slave_awcache, - to_slave_awid, - to_slave_awqos, - to_slave_awregion, - to_slave_wid; - wire [2 : 0] to_slave_arprot, - to_slave_arsize, - to_slave_awprot, - to_slave_awsize; - wire [1 : 0] from_master_bresp, - from_master_rresp, - to_slave_arburst, - to_slave_awburst; - wire RDY_reset, - from_master_arready, - from_master_awready, - from_master_bvalid, - from_master_rlast, - from_master_rvalid, - from_master_wready, - to_slave_arlock, - to_slave_arvalid, - to_slave_awlock, - to_slave_awvalid, - to_slave_bready, - to_slave_rready, - to_slave_wlast, - to_slave_wvalid; - - // register m_rg_ar_beat_count - reg [7 : 0] m_rg_ar_beat_count; - wire [7 : 0] m_rg_ar_beat_count$D_IN; - wire m_rg_ar_beat_count$EN; - - // register m_rg_b_beat_count - reg [7 : 0] m_rg_b_beat_count; - wire [7 : 0] m_rg_b_beat_count$D_IN; - wire m_rg_b_beat_count$EN; - - // register m_rg_b_resp - reg [1 : 0] m_rg_b_resp; - wire [1 : 0] m_rg_b_resp$D_IN; - wire m_rg_b_resp$EN; - - // register m_rg_r_beat_count - reg [7 : 0] m_rg_r_beat_count; - wire [7 : 0] m_rg_r_beat_count$D_IN; - wire m_rg_r_beat_count$EN; - - // register m_rg_reset - reg m_rg_reset; - wire m_rg_reset$D_IN, m_rg_reset$EN; - - // register m_rg_w_beat_count - reg [7 : 0] m_rg_w_beat_count; - wire [7 : 0] m_rg_w_beat_count$D_IN; - wire m_rg_w_beat_count$EN; - - // ports of submodule m_f_r_arlen - wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT; - wire m_f_r_arlen$CLR, - m_f_r_arlen$DEQ, - m_f_r_arlen$EMPTY_N, - m_f_r_arlen$ENQ, - m_f_r_arlen$FULL_N; - - // ports of submodule m_f_w_awlen - wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT; - wire m_f_w_awlen$CLR, - m_f_w_awlen$DEQ, - m_f_w_awlen$EMPTY_N, - m_f_w_awlen$ENQ, - m_f_w_awlen$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_addr - wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN, - m_xactor_from_master_f_rd_addr$D_OUT; - wire m_xactor_from_master_f_rd_addr$CLR, - m_xactor_from_master_f_rd_addr$DEQ, - m_xactor_from_master_f_rd_addr$EMPTY_N, - m_xactor_from_master_f_rd_addr$ENQ, - m_xactor_from_master_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_rd_data - wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN, - m_xactor_from_master_f_rd_data$D_OUT; - wire m_xactor_from_master_f_rd_data$CLR, - m_xactor_from_master_f_rd_data$DEQ, - m_xactor_from_master_f_rd_data$EMPTY_N, - m_xactor_from_master_f_rd_data$ENQ, - m_xactor_from_master_f_rd_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_addr - wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN, - m_xactor_from_master_f_wr_addr$D_OUT; - wire m_xactor_from_master_f_wr_addr$CLR, - m_xactor_from_master_f_wr_addr$DEQ, - m_xactor_from_master_f_wr_addr$EMPTY_N, - m_xactor_from_master_f_wr_addr$ENQ, - m_xactor_from_master_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_data - wire [76 : 0] m_xactor_from_master_f_wr_data$D_IN, - m_xactor_from_master_f_wr_data$D_OUT; - wire m_xactor_from_master_f_wr_data$CLR, - m_xactor_from_master_f_wr_data$DEQ, - m_xactor_from_master_f_wr_data$EMPTY_N, - m_xactor_from_master_f_wr_data$ENQ, - m_xactor_from_master_f_wr_data$FULL_N; - - // ports of submodule m_xactor_from_master_f_wr_resp - wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN, - m_xactor_from_master_f_wr_resp$D_OUT; - wire m_xactor_from_master_f_wr_resp$CLR, - m_xactor_from_master_f_wr_resp$DEQ, - m_xactor_from_master_f_wr_resp$EMPTY_N, - m_xactor_from_master_f_wr_resp$ENQ, - m_xactor_from_master_f_wr_resp$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_addr - wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN, - m_xactor_to_slave_f_rd_addr$D_OUT; - wire m_xactor_to_slave_f_rd_addr$CLR, - m_xactor_to_slave_f_rd_addr$DEQ, - m_xactor_to_slave_f_rd_addr$EMPTY_N, - m_xactor_to_slave_f_rd_addr$ENQ, - m_xactor_to_slave_f_rd_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_rd_data - wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN, - m_xactor_to_slave_f_rd_data$D_OUT; - wire m_xactor_to_slave_f_rd_data$CLR, - m_xactor_to_slave_f_rd_data$DEQ, - m_xactor_to_slave_f_rd_data$EMPTY_N, - m_xactor_to_slave_f_rd_data$ENQ, - m_xactor_to_slave_f_rd_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_addr - wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN, - m_xactor_to_slave_f_wr_addr$D_OUT; - wire m_xactor_to_slave_f_wr_addr$CLR, - m_xactor_to_slave_f_wr_addr$DEQ, - m_xactor_to_slave_f_wr_addr$EMPTY_N, - m_xactor_to_slave_f_wr_addr$ENQ, - m_xactor_to_slave_f_wr_addr$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_data - wire [76 : 0] m_xactor_to_slave_f_wr_data$D_IN, - m_xactor_to_slave_f_wr_data$D_OUT; - wire m_xactor_to_slave_f_wr_data$CLR, - m_xactor_to_slave_f_wr_data$DEQ, - m_xactor_to_slave_f_wr_data$EMPTY_N, - m_xactor_to_slave_f_wr_data$ENQ, - m_xactor_to_slave_f_wr_data$FULL_N; - - // ports of submodule m_xactor_to_slave_f_wr_resp - wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN, - m_xactor_to_slave_f_wr_resp$D_OUT; - wire m_xactor_to_slave_f_wr_resp$CLR, - m_xactor_to_slave_f_wr_resp$DEQ, - m_xactor_to_slave_f_wr_resp$EMPTY_N, - m_xactor_to_slave_f_wr_resp$ENQ, - m_xactor_to_slave_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave, - CAN_FIRE_from_master_m_arvalid, - CAN_FIRE_from_master_m_awvalid, - CAN_FIRE_from_master_m_bready, - CAN_FIRE_from_master_m_rready, - CAN_FIRE_from_master_m_wvalid, - CAN_FIRE_reset, - CAN_FIRE_to_slave_m_arready, - CAN_FIRE_to_slave_m_awready, - CAN_FIRE_to_slave_m_bvalid, - CAN_FIRE_to_slave_m_rvalid, - CAN_FIRE_to_slave_m_wready, - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave, - WILL_FIRE_from_master_m_arvalid, - WILL_FIRE_from_master_m_awvalid, - WILL_FIRE_from_master_m_bready, - WILL_FIRE_from_master_m_rready, - WILL_FIRE_from_master_m_wvalid, - WILL_FIRE_reset, - WILL_FIRE_to_slave_m_arready, - WILL_FIRE_to_slave_m_awready, - WILL_FIRE_to_slave_m_bvalid, - WILL_FIRE_to_slave_m_rvalid, - WILL_FIRE_to_slave_m_wready; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2, - MUX_m_rg_b_beat_count$write_1__VAL_2, - MUX_m_rg_r_beat_count$write_1__VAL_2, - MUX_m_rg_w_beat_count$write_1__VAL_2; - wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2; - wire MUX_m_rg_b_resp$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2430; - reg [31 : 0] v__h1446; - reg [31 : 0] v__h1440; - reg [31 : 0] v__h2424; - // synopsys translate_on - - // remaining internal signals - wire [63 : 0] a_out_araddr__h2944, - a_out_awaddr__h1951, - addr___1__h2036, - addr___1__h3029; - wire [7 : 0] x__h2305, x__h2798, x__h3190, x__h3388; - wire m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95, - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51, - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106, - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35; - - // action method reset - assign RDY_reset = !m_rg_reset ; - assign CAN_FIRE_reset = !m_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method from_master_m_awvalid - assign CAN_FIRE_from_master_m_awvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_awvalid = 1'd1 ; - - // value method from_master_m_awready - assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ; - - // action method from_master_m_wvalid - assign CAN_FIRE_from_master_m_wvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_wvalid = 1'd1 ; - - // value method from_master_m_wready - assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ; - - // value method from_master_m_bvalid - assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ; - - // value method from_master_m_bid - assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ; - - // value method from_master_m_bresp - assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ; - - // action method from_master_m_bready - assign CAN_FIRE_from_master_m_bready = 1'd1 ; - assign WILL_FIRE_from_master_m_bready = 1'd1 ; - - // action method from_master_m_arvalid - assign CAN_FIRE_from_master_m_arvalid = 1'd1 ; - assign WILL_FIRE_from_master_m_arvalid = 1'd1 ; - - // value method from_master_m_arready - assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ; - - // value method from_master_m_rvalid - assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ; - - // value method from_master_m_rid - assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ; - - // value method from_master_m_rdata - assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ; - - // value method from_master_m_rresp - assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ; - - // value method from_master_m_rlast - assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ; - - // action method from_master_m_rready - assign CAN_FIRE_from_master_m_rready = 1'd1 ; - assign WILL_FIRE_from_master_m_rready = 1'd1 ; - - // value method to_slave_m_awvalid - assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ; - - // value method to_slave_m_awid - assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ; - - // value method to_slave_m_awaddr - assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ; - - // value method to_slave_m_awlen - assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ; - - // value method to_slave_m_awsize - assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ; - - // value method to_slave_m_awburst - assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ; - - // value method to_slave_m_awlock - assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ; - - // value method to_slave_m_awcache - assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ; - - // value method to_slave_m_awprot - assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ; - - // value method to_slave_m_awqos - assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ; - - // value method to_slave_m_awregion - assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ; - - // action method to_slave_m_awready - assign CAN_FIRE_to_slave_m_awready = 1'd1 ; - assign WILL_FIRE_to_slave_m_awready = 1'd1 ; - - // value method to_slave_m_wvalid - assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ; - - // value method to_slave_m_wid - assign to_slave_wid = m_xactor_to_slave_f_wr_data$D_OUT[76:73] ; - - // value method to_slave_m_wdata - assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ; - - // value method to_slave_m_wstrb - assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ; - - // value method to_slave_m_wlast - assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ; - - // action method to_slave_m_wready - assign CAN_FIRE_to_slave_m_wready = 1'd1 ; - assign WILL_FIRE_to_slave_m_wready = 1'd1 ; - - // action method to_slave_m_bvalid - assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ; - - // value method to_slave_m_bready - assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ; - - // value method to_slave_m_arvalid - assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ; - - // value method to_slave_m_arid - assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ; - - // value method to_slave_m_araddr - assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ; - - // value method to_slave_m_arlen - assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ; - - // value method to_slave_m_arsize - assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ; - - // value method to_slave_m_arburst - assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ; - - // value method to_slave_m_arlock - assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ; - - // value method to_slave_m_arcache - assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ; - - // value method to_slave_m_arprot - assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ; - - // value method to_slave_m_arqos - assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ; - - // value method to_slave_m_arregion - assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ; - - // action method to_slave_m_arready - assign CAN_FIRE_to_slave_m_arready = 1'd1 ; - assign WILL_FIRE_to_slave_m_arready = 1'd1 ; - - // action method to_slave_m_rvalid - assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ; - assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ; - - // value method to_slave_m_rready - assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ; - - // submodule m_f_r_arlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_r_arlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_r_arlen$D_IN), - .ENQ(m_f_r_arlen$ENQ), - .DEQ(m_f_r_arlen$DEQ), - .CLR(m_f_r_arlen$CLR), - .D_OUT(m_f_r_arlen$D_OUT), - .FULL_N(m_f_r_arlen$FULL_N), - .EMPTY_N(m_f_r_arlen$EMPTY_N)); - - // submodule m_f_w_awlen - SizedFIFO #(.p1width(32'd8), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(32'd1)) m_f_w_awlen(.RST(RST_N), - .CLK(CLK), - .D_IN(m_f_w_awlen$D_IN), - .ENQ(m_f_w_awlen$ENQ), - .DEQ(m_f_w_awlen$DEQ), - .CLR(m_f_w_awlen$CLR), - .D_OUT(m_f_w_awlen$D_OUT), - .FULL_N(m_f_w_awlen$FULL_N), - .EMPTY_N(m_f_w_awlen$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_addr$D_IN), - .ENQ(m_xactor_from_master_f_rd_addr$ENQ), - .DEQ(m_xactor_from_master_f_rd_addr$DEQ), - .CLR(m_xactor_from_master_f_rd_addr$CLR), - .D_OUT(m_xactor_from_master_f_rd_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_rd_data$D_IN), - .ENQ(m_xactor_from_master_f_rd_data$ENQ), - .DEQ(m_xactor_from_master_f_rd_data$DEQ), - .CLR(m_xactor_from_master_f_rd_data$CLR), - .D_OUT(m_xactor_from_master_f_rd_data$D_OUT), - .FULL_N(m_xactor_from_master_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_addr$D_IN), - .ENQ(m_xactor_from_master_f_wr_addr$ENQ), - .DEQ(m_xactor_from_master_f_wr_addr$DEQ), - .CLR(m_xactor_from_master_f_wr_addr$CLR), - .D_OUT(m_xactor_from_master_f_wr_addr$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_data$D_IN), - .ENQ(m_xactor_from_master_f_wr_data$ENQ), - .DEQ(m_xactor_from_master_f_wr_data$DEQ), - .CLR(m_xactor_from_master_f_wr_data$CLR), - .D_OUT(m_xactor_from_master_f_wr_data$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N)); - - // submodule m_xactor_from_master_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_from_master_f_wr_resp$D_IN), - .ENQ(m_xactor_from_master_f_wr_resp$ENQ), - .DEQ(m_xactor_from_master_f_wr_resp$DEQ), - .CLR(m_xactor_from_master_f_wr_resp$CLR), - .D_OUT(m_xactor_from_master_f_wr_resp$D_OUT), - .FULL_N(m_xactor_from_master_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_addr$D_IN), - .ENQ(m_xactor_to_slave_f_rd_addr$ENQ), - .DEQ(m_xactor_to_slave_f_rd_addr$DEQ), - .CLR(m_xactor_to_slave_f_rd_addr$CLR), - .D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_rd_data$D_IN), - .ENQ(m_xactor_to_slave_f_rd_data$ENQ), - .DEQ(m_xactor_to_slave_f_rd_data$DEQ), - .CLR(m_xactor_to_slave_f_rd_data$CLR), - .D_OUT(m_xactor_to_slave_f_rd_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_rd_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_addr$D_IN), - .ENQ(m_xactor_to_slave_f_wr_addr$ENQ), - .DEQ(m_xactor_to_slave_f_wr_addr$DEQ), - .CLR(m_xactor_to_slave_f_wr_addr$CLR), - .D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_data$D_IN), - .ENQ(m_xactor_to_slave_f_wr_data$ENQ), - .DEQ(m_xactor_to_slave_f_wr_data$DEQ), - .CLR(m_xactor_to_slave_f_wr_data$CLR), - .D_OUT(m_xactor_to_slave_f_wr_data$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_data$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N)); - - // submodule m_xactor_to_slave_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_xactor_to_slave_f_wr_resp$D_IN), - .ENQ(m_xactor_to_slave_f_wr_resp$ENQ), - .DEQ(m_xactor_to_slave_f_wr_resp$DEQ), - .CLR(m_xactor_to_slave_f_wr_resp$CLR), - .D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT), - .FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N), - .EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave = - m_xactor_to_slave_f_wr_addr$FULL_N && - m_xactor_from_master_f_wr_addr$EMPTY_N && - m_xactor_to_slave_f_wr_data$FULL_N && - m_xactor_from_master_f_wr_data$EMPTY_N && - (m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - - // rule RL_m_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master = - m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N && - (m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 || - m_xactor_from_master_f_wr_resp$FULL_N) ; - assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - - // rule RL_m_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave = - m_xactor_to_slave_f_rd_addr$FULL_N && - m_xactor_from_master_f_rd_addr$EMPTY_N && - (m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ; - assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - - // rule RL_m_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master = - m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N && - m_xactor_from_master_f_rd_data$FULL_N ; - assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ; - assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_b_resp$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - (m_rg_b_resp == 2'b0 && - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 || - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51) ; - assign MUX_m_rg_ar_beat_count$write_1__VAL_2 = - m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ? - x__h3190 : - 8'd0 ; - assign MUX_m_rg_b_beat_count$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - x__h2798 : - 8'd0 ; - assign MUX_m_rg_b_resp$write_1__VAL_2 = - m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - 2'b0 ; - assign MUX_m_rg_r_beat_count$write_1__VAL_2 = - m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ? - x__h3388 : - 8'd0 ; - assign MUX_m_rg_w_beat_count$write_1__VAL_2 = - m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ? - x__h2305 : - 8'd0 ; - - // register m_rg_ar_beat_count - assign m_rg_ar_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ; - assign m_rg_ar_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ; - - // register m_rg_b_beat_count - assign m_rg_b_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ; - assign m_rg_b_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ; - - // register m_rg_b_resp - assign m_rg_b_resp$D_IN = - m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ; - assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ; - - // register m_rg_r_beat_count - assign m_rg_r_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ; - assign m_rg_r_beat_count$EN = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ; - - // register m_rg_reset - assign m_rg_reset$D_IN = !m_rg_reset ; - assign m_rg_reset$EN = m_rg_reset || EN_reset ; - - // register m_rg_w_beat_count - assign m_rg_w_beat_count$D_IN = - m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ; - assign m_rg_w_beat_count$EN = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ; - - // submodule m_f_r_arlen - assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_f_r_arlen$ENQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - m_rg_ar_beat_count == 8'd0 ; - assign m_f_r_arlen$DEQ = - WILL_FIRE_RL_m_rl_rd_resp_slave_to_master && - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 ; - assign m_f_r_arlen$CLR = m_rg_reset ; - - // submodule m_f_w_awlen - assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign m_f_w_awlen$ENQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - m_rg_w_beat_count == 8'd0 ; - assign m_f_w_awlen$DEQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_f_w_awlen$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_addr - assign m_xactor_from_master_f_rd_addr$D_IN = - { from_master_arid, - from_master_araddr, - from_master_arlen, - from_master_arsize, - from_master_arburst, - from_master_arlock, - from_master_arcache, - from_master_arprot, - from_master_arqos, - from_master_arregion } ; - assign m_xactor_from_master_f_rd_addr$ENQ = - from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ; - assign m_xactor_from_master_f_rd_addr$DEQ = - WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave && - !m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 ; - assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_rd_data - assign m_xactor_from_master_f_rd_data$D_IN = - { m_xactor_to_slave_f_rd_data$D_OUT[70:1], - !m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 } ; - assign m_xactor_from_master_f_rd_data$ENQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_from_master_f_rd_data$DEQ = - from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ; - assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_addr - assign m_xactor_from_master_f_wr_addr$D_IN = - { from_master_awid, - from_master_awaddr, - from_master_awlen, - from_master_awsize, - from_master_awburst, - from_master_awlock, - from_master_awcache, - from_master_awprot, - from_master_awqos, - from_master_awregion } ; - assign m_xactor_from_master_f_wr_addr$ENQ = - from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ; - assign m_xactor_from_master_f_wr_addr$DEQ = - WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 ; - assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_data - assign m_xactor_from_master_f_wr_data$D_IN = - { from_master_wid, - from_master_wdata, - from_master_wstrb, - from_master_wlast } ; - assign m_xactor_from_master_f_wr_data$ENQ = - from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ; - assign m_xactor_from_master_f_wr_data$DEQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_from_master_f_wr_resp - assign m_xactor_from_master_f_wr_resp$D_IN = - { m_xactor_to_slave_f_wr_resp$D_OUT[5:2], - (m_rg_b_resp == 2'b0) ? - m_xactor_to_slave_f_wr_resp$D_OUT[1:0] : - m_rg_b_resp } ; - assign m_xactor_from_master_f_wr_resp$ENQ = - WILL_FIRE_RL_m_rl_wr_resp_slave_to_master && - !m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 ; - assign m_xactor_from_master_f_wr_resp$DEQ = - from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ; - assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_addr - assign m_xactor_to_slave_f_rd_addr$D_IN = - { m_xactor_from_master_f_rd_addr$D_OUT[96:93], - a_out_araddr__h2944, - 8'd0, - m_xactor_from_master_f_rd_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_rd_addr$ENQ = - CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ; - assign m_xactor_to_slave_f_rd_addr$DEQ = - m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ; - assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_rd_data - assign m_xactor_to_slave_f_rd_data$D_IN = - { to_slave_rid, - to_slave_rdata, - to_slave_rresp, - to_slave_rlast } ; - assign m_xactor_to_slave_f_rd_data$ENQ = - to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ; - assign m_xactor_to_slave_f_rd_data$DEQ = - CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ; - assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_addr - assign m_xactor_to_slave_f_wr_addr$D_IN = - { m_xactor_from_master_f_wr_addr$D_OUT[96:93], - a_out_awaddr__h1951, - 8'd0, - m_xactor_from_master_f_wr_addr$D_OUT[20:18], - 2'b0, - m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ; - assign m_xactor_to_slave_f_wr_addr$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_addr$DEQ = - m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ; - assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_data - assign m_xactor_to_slave_f_wr_data$D_IN = - { m_xactor_from_master_f_wr_data$D_OUT[76:1], 1'd1 } ; - assign m_xactor_to_slave_f_wr_data$ENQ = - CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ; - assign m_xactor_to_slave_f_wr_data$DEQ = - m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ; - assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ; - - // submodule m_xactor_to_slave_f_wr_resp - assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ; - assign m_xactor_to_slave_f_wr_resp$ENQ = - to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ; - assign m_xactor_to_slave_f_wr_resp$DEQ = - CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ; - assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ; - - // remaining internal signals - assign a_out_araddr__h2944 = - (m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h3029 : - m_xactor_from_master_f_rd_addr$D_OUT[92:29] ; - assign a_out_awaddr__h1951 = - (m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b01) ? - addr___1__h2036 : - m_xactor_from_master_f_wr_addr$D_OUT[92:29] ; - assign addr___1__h2036 = - m_xactor_from_master_f_wr_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_w_beat_count } << - m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ; - assign addr___1__h3029 = - m_xactor_from_master_f_rd_addr$D_OUT[92:29] + - ({ 56'd0, m_rg_ar_beat_count } << - m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ; - assign m_rg_ar_beat_count_3_ULT_m_xactor_from_master__ETC___d95 = - m_rg_ar_beat_count < - m_xactor_from_master_f_rd_addr$D_OUT[28:21] ; - assign m_rg_b_beat_count_9_ULT_m_f_w_awlen_first__0___d51 = - m_rg_b_beat_count < m_f_w_awlen$D_OUT ; - assign m_rg_r_beat_count_04_ULT_m_f_r_arlen_first__05___d106 = - m_rg_r_beat_count < m_f_r_arlen$D_OUT ; - assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 = - m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ; - assign x__h2305 = m_rg_w_beat_count + 8'd1 ; - assign x__h2798 = m_rg_b_beat_count + 8'd1 ; - assign x__h3190 = m_rg_ar_beat_count + 8'd1 ; - assign x__h3388 = m_rg_r_beat_count + 8'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0; - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (m_rg_ar_beat_count$EN) - m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN; - if (m_rg_b_beat_count$EN) - m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN; - if (m_rg_b_resp$EN) - m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN; - if (m_rg_r_beat_count$EN) - m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN; - if (m_rg_reset$EN) - m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN; - if (m_rg_w_beat_count$EN) - m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_ar_beat_count = 8'hAA; - m_rg_b_beat_count = 8'hAA; - m_rg_b_resp = 2'h2; - m_rg_r_beat_count = 8'hAA; - m_rg_reset = 1'h0; - m_rg_w_beat_count = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - begin - v__h2430 = $stime; - #0; - end - v__h2424 = v__h2430 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", - v__h2424); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $display(" WLAST not set on last data beat (awlen = %0d)", - m_xactor_from_master_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave && - !m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d35 && - !m_xactor_from_master_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) - begin - v__h1446 = $stime; - #0; - end - v__h1440 = v__h1446 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (m_rg_reset) $display("%0d: %m::AXI4_Deburster.rl_reset", v__h1440); - end - // synopsys translate_on -endmodule // mkAXI4_Deburster_A - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v deleted file mode 100644 index 41b42457..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkBoot_ROM.v +++ /dev/null @@ -1,2157 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkBoot_ROM(CLK, - RST_N, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready); - input CLK; - input RST_N; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_set_addr_map, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_module_ready - reg rg_module_ready; - wire rg_module_ready$D_IN, rg_module_ready$EN; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h808; - reg [31 : 0] v__h8928; - reg [31 : 0] v__h9221; - reg [31 : 0] v__h9331; - reg [31 : 0] v__h802; - reg [31 : 0] v__h8922; - reg [31 : 0] v__h9215; - reg [31 : 0] v__h9325; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] data64__h987; - reg [31 : 0] CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2; - wire [63 : 0] byte_addr__h705, rdata__h924; - wire [1 : 0] rdr_rresp__h957; - wire NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18, - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - rg_module_ready ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_module_ready - assign rg_module_ready$D_IN = 1'd1 ; - assign rg_module_ready$EN = EN_set_addr_map ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h924, - rdr_rresp__h957, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 ? - 2'b10 : - 2'b0 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = 1'b0 ; - - // remaining internal signals - assign NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 = - slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] || - slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ; - assign NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218 = - slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0 || - rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] || - slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ; - assign byte_addr__h705 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign rdata__h924 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 64'd0 : - data64__h987 ; - assign rdr_rresp__h957 = - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18 ? - 2'b10 : - 2'b0 ; - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16, - 64'd24, - 64'd56, - 64'd72, - 64'd80, - 64'd88, - 64'd200, - 64'd232, - 64'd312, - 64'd424, - 64'd448, - 64'd600, - 64'd728, - 64'd1136, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = 32'h0; - 64'd32: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h54040000; - 64'd40: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h88030000; - 64'd48: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h11000000; - 64'd64: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h50030000; - 64'd96, - 64'd112, - 64'd208, - 64'd224, - 64'd240, - 64'd432, - 64'd488, - 64'd872, - 64'd888: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h04000000; - 64'd104, 64'd120, 64'd504, 64'd792, 64'd920: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h02000000; - 64'd128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h16000000; - 64'd136: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h62626375; - 64'd144: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656B6970; - 64'd152: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65642D65; - 64'd160, - 64'd264, - 64'd280, - 64'd296, - 64'd336, - 64'd360, - 64'd384, - 64'd456, - 64'd552, - 64'd592, - 64'd608, - 64'd624, - 64'd672, - 64'd704, - 64'd760, - 64'd816, - 64'd840, - 64'd880: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h03000000; - 64'd168: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h26000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h732C7261; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7261622D; - 64'd192, - 64'd216, - 64'd400, - 64'd440, - 64'd496, - 64'd512, - 64'd584, - 64'd744, - 64'd752, - 64'd912: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h01000000; - 64'd248, 64'd896: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h80969800; - 64'd256: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40757063; - 64'd272: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h3F000000; - 64'd288, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4B000000; - 64'd304: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h4F000000; - 64'd320: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h06000000; - 64'd328: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h63736972; - 64'd344: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h56000000; - 64'd352: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h75616D69; - 64'd368: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h60000000; - 64'd376: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h76732C76; - 64'd392: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69000000; - 64'd408: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70757272; - 64'd416: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F72746E; - 64'd464, 64'd632, 64'd712, 64'd824: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h1B000000; - 64'd472: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70632C76; - 64'd480: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00006374; - 64'd520: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h38407972; - 64'd528: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00303030; - 64'd536: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h07000000; - 64'd544: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D656D; - 64'd568: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000080; - 64'd576: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000010; - 64'd616: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h0F000000; - 64'd656: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69730063; - 64'd664: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7375622D; - 64'd680: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hA7000000; - 64'd688: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E696C63; - 64'd696, 64'd808: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h30303030; - 64'd720: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C632C76; - 64'd736: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h10000000; - 64'd776: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000002; - 64'd784: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00000C00; - 64'd800: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h74726175; - 64'd832: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61303535; - 64'd856: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h000000C0; - 64'd864: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h40000000; - 64'd904: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h08000000; - 64'd928: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h09000000; - 64'd936: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73736572; - 64'd944: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h2300736C; - 64'd952: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C65632D; - 64'd960: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h61706D6F; - 64'd968: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6F6D0065; - 64'd976: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h656D6974; - 64'd984: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6572662D; - 64'd992: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h64007963; - 64'd1000: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79745F65; - 64'd1008: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73006765; - 64'd1016: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h69720073; - 64'd1024: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h00617369; - 64'd1032: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65707974; - 64'd1040: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h662D6B63; - 64'd1048: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h79636E65; - 64'd1056, 64'd1072: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h72726574; - 64'd1064: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6C6C6563; - 64'd1080: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h746E6F63; - 64'd1088: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h70007265; - 64'd1096: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h7200656C; - 64'd1104: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h6E690073; - 64'd1112: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h73747075; - 64'd1120: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h65646E65; - 64'd1128: - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'h68732D67; - default: CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705) - begin - case (byte_addr__h705) - 64'd16: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00028067; - 64'd24: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80000000; - 64'd32: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hEDFE0DD0; - 64'd40: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h38000000; - 64'd48: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h28000000; - 64'd56, 64'd560, 64'd768, 64'd848: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h10000000; - 64'd64: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hCC000000; - 64'd72, - 64'd80, - 64'd104, - 64'd216, - 64'd296, - 64'd568, - 64'd576, - 64'd672, - 64'd680, - 64'd776, - 64'd784, - 64'd840, - 64'd856, - 64'd864, - 64'd1144, - 64'd1152, - 64'd1160, - 64'd1168, - 64'd1176, - 64'd1184, - 64'd1192, - 64'd1200, - 64'd1208, - 64'd1216, - 64'd1224, - 64'd1232, - 64'd1240, - 64'd1248, - 64'd1256, - 64'd1264, - 64'd1272, - 64'd1280, - 64'd1288, - 64'd1296, - 64'd1304, - 64'd1312, - 64'd1320, - 64'd1328, - 64'd1336, - 64'd1344, - 64'd1352, - 64'd1360, - 64'd1368, - 64'd1376, - 64'd1384, - 64'd1392, - 64'd1400, - 64'd1408, - 64'd1416, - 64'd1424, - 64'd1432, - 64'd1440, - 64'd1448, - 64'd1456, - 64'd1464, - 64'd1472, - 64'd1480, - 64'd1488, - 64'd1496, - 64'd1504, - 64'd1512, - 64'd1520, - 64'd1528, - 64'd1536, - 64'd1544, - 64'd1552, - 64'd1560, - 64'd1568, - 64'd1576, - 64'd1584, - 64'd1592, - 64'd1600, - 64'd1608, - 64'd1616, - 64'd1624, - 64'd1632, - 64'd1640, - 64'd1648, - 64'd1656, - 64'd1664, - 64'd1672, - 64'd1680, - 64'd1688, - 64'd1696, - 64'd1704, - 64'd1712, - 64'd1720, - 64'd1728, - 64'd1736, - 64'd1744, - 64'd1752, - 64'd1760, - 64'd1768, - 64'd1776, - 64'd1784, - 64'd1792, - 64'd1800, - 64'd1808, - 64'd1816, - 64'd1824, - 64'd1832, - 64'd1840, - 64'd1848, - 64'd1856, - 64'd1864, - 64'd1872, - 64'd1880, - 64'd1888, - 64'd1896, - 64'd1904, - 64'd1912, - 64'd1920, - 64'd1928, - 64'd1936, - 64'd1944, - 64'd1952, - 64'd1960, - 64'd1968, - 64'd1976, - 64'd1984, - 64'd1992, - 64'd2000, - 64'd2008, - 64'd2016, - 64'd2024, - 64'd2032, - 64'd2040, - 64'd2048, - 64'd2056, - 64'd2064, - 64'd2072, - 64'd2080, - 64'd2088, - 64'd2096, - 64'd2104, - 64'd2112, - 64'd2120, - 64'd2128, - 64'd2136, - 64'd2144, - 64'd2152, - 64'd2160, - 64'd2168, - 64'd2176, - 64'd2184, - 64'd2192, - 64'd2200, - 64'd2208, - 64'd2216, - 64'd2224, - 64'd2232, - 64'd2240, - 64'd2248, - 64'd2256, - 64'd2264, - 64'd2272, - 64'd2280, - 64'd2288, - 64'd2296, - 64'd2304, - 64'd2312, - 64'd2320, - 64'd2328, - 64'd2336, - 64'd2344, - 64'd2352, - 64'd2360, - 64'd2368, - 64'd2376, - 64'd2384, - 64'd2392, - 64'd2400, - 64'd2408, - 64'd2416, - 64'd2424, - 64'd2432, - 64'd2440, - 64'd2448, - 64'd2456, - 64'd2464, - 64'd2472, - 64'd2480, - 64'd2488, - 64'd2496, - 64'd2504, - 64'd2512, - 64'd2520, - 64'd2528, - 64'd2536, - 64'd2544, - 64'd2552, - 64'd2560, - 64'd2568, - 64'd2576, - 64'd2584, - 64'd2592, - 64'd2600, - 64'd2608, - 64'd2616, - 64'd2624, - 64'd2632, - 64'd2640, - 64'd2648, - 64'd2656, - 64'd2664, - 64'd2672, - 64'd2680, - 64'd2688, - 64'd2696, - 64'd2704, - 64'd2712, - 64'd2720, - 64'd2728, - 64'd2736, - 64'd2744, - 64'd2752, - 64'd2760, - 64'd2768, - 64'd2776, - 64'd2784, - 64'd2792, - 64'd2800, - 64'd2808, - 64'd2816, - 64'd2824, - 64'd2832, - 64'd2840, - 64'd2848, - 64'd2856, - 64'd2864, - 64'd2872, - 64'd2880, - 64'd2888, - 64'd2896, - 64'd2904, - 64'd2912, - 64'd2920, - 64'd2928, - 64'd2936, - 64'd2944, - 64'd2952, - 64'd2960, - 64'd2968, - 64'd2976, - 64'd2984, - 64'd2992, - 64'd3000, - 64'd3008, - 64'd3016, - 64'd3024, - 64'd3032, - 64'd3040, - 64'd3048, - 64'd3056, - 64'd3064, - 64'd3072, - 64'd3080, - 64'd3088, - 64'd3096, - 64'd3104, - 64'd3112, - 64'd3120, - 64'd3128, - 64'd3136, - 64'd3144, - 64'd3152, - 64'd3160, - 64'd3168, - 64'd3176, - 64'd3184, - 64'd3192, - 64'd3200, - 64'd3208, - 64'd3216, - 64'd3224, - 64'd3232, - 64'd3240, - 64'd3248, - 64'd3256, - 64'd3264, - 64'd3272, - 64'd3280, - 64'd3288, - 64'd3296, - 64'd3304, - 64'd3312, - 64'd3320, - 64'd3328, - 64'd3336, - 64'd3344, - 64'd3352, - 64'd3360, - 64'd3368, - 64'd3376, - 64'd3384, - 64'd3392, - 64'd3400, - 64'd3408, - 64'd3416, - 64'd3424, - 64'd3432, - 64'd3440, - 64'd3448, - 64'd3456, - 64'd3464, - 64'd3472, - 64'd3480, - 64'd3488, - 64'd3496, - 64'd3504, - 64'd3512, - 64'd3520, - 64'd3528, - 64'd3536, - 64'd3544, - 64'd3552, - 64'd3560, - 64'd3568, - 64'd3576, - 64'd3584, - 64'd3592, - 64'd3600, - 64'd3608, - 64'd3616, - 64'd3624, - 64'd3632, - 64'd3640, - 64'd3648, - 64'd3656, - 64'd3664, - 64'd3672, - 64'd3680, - 64'd3688, - 64'd3696, - 64'd3704, - 64'd3712, - 64'd3720, - 64'd3728, - 64'd3736, - 64'd3744, - 64'd3752, - 64'd3760, - 64'd3768, - 64'd3776, - 64'd3784, - 64'd3792, - 64'd3800, - 64'd3808, - 64'd3816, - 64'd3824, - 64'd3832, - 64'd3840, - 64'd3848, - 64'd3856, - 64'd3864, - 64'd3872, - 64'd3880, - 64'd3888, - 64'd3896, - 64'd3904, - 64'd3912, - 64'd3920, - 64'd3928, - 64'd3936, - 64'd3944, - 64'd3952, - 64'd3960, - 64'd3968, - 64'd3976, - 64'd3984, - 64'd3992, - 64'd4000, - 64'd4008, - 64'd4016, - 64'd4024, - 64'd4032, - 64'd4040, - 64'd4048, - 64'd4056, - 64'd4064, - 64'd4072, - 64'd4080, - 64'd4088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = 32'h0; - 64'd88, 64'd256, 64'd688, 64'd800: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h01000000; - 64'd96, - 64'd112, - 64'd128, - 64'd208, - 64'd224, - 64'd240, - 64'd320, - 64'd432, - 64'd448, - 64'd488, - 64'd536, - 64'd736, - 64'd752, - 64'd872, - 64'd888, - 64'd904: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h03000000; - 64'd120, 64'd232, 64'd464: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0F000000; - 64'd136, 64'd328: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h1B000000; - 64'd144: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h732C7261; - 64'd152: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7261622D; - 64'd160, 64'd336: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000076; - 64'd168: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h12000000; - 64'd176, 64'd640: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h62626375; - 64'd184, 64'd648: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656B6970; - 64'd192: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000065; - 64'd200: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h73757063; - 64'd248: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C000000; - 64'd264, 64'd704, 64'd816: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000030; - 64'd272, 64'd288, 64'd392, 64'd600, 64'd616: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h04000000; - 64'd280: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00757063; - 64'd304: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h05000000; - 64'd312: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79616B6F; - 64'd344: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0A000000; - 64'd352: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h34367672; - 64'd360: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00000073; - 64'd368, 64'd920: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0B000000; - 64'd376, 64'd472, 64'd720: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63736972; - 64'd384: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00003933; - 64'd400: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h80969800; - 64'd408: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65746E69; - 64'd416: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F632D74; - 64'd424: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72656C6C; - 64'd440: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h79000000; - 64'd456: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h8A000000; - 64'd480: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692D75; - 64'd496: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h9F000000; - 64'd504, 64'd512, 64'd584, 64'd608, 64'd624, 64'd792, 64'd928: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h02000000; - 64'd520: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6D656D; - 64'd528: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30303030; - 64'd544: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3F000000; - 64'd552: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00007972; - 64'd592: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00636F73; - 64'd632: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h21000000; - 64'd656: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F732D65; - 64'd664: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h656C706D; - 64'd696: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30324074; - 64'd712: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h0D000000; - 64'd728: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30746E69; - 64'd744, 64'd912: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAE000000; - 64'd760: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h07000000; - 64'd808: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h30306340; - 64'd824: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h09000000; - 64'd832: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h3631736E; - 64'd880: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hC2000000; - 64'd896: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h69000000; - 64'd936: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h64646123; - 64'd944: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C65632D; - 64'd952: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h657A6973; - 64'd960: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6300736C; - 64'd968: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C626974; - 64'd976: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h006C6564; - 64'd984: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65736162; - 64'd992: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E657571; - 64'd1000: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h63697665; - 64'd1008: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72006570; - 64'd1016: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75746174; - 64'd1024: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2C766373; - 64'd1032: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D756D6D; - 64'd1040: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6F6C6300; - 64'd1048: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h75716572; - 64'd1056: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E692300; - 64'd1064, 64'd1080: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h2D747075; - 64'd1072: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6E690073; - 64'd1088: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h6C6C6F72; - 64'd1096: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h646E6168; - 64'd1104: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65676E61; - 64'd1112: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h72726574; - 64'd1120: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h7478652D; - 64'd1128: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h65720064; - 64'd1136: - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'h00746669; - default: CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 = - 32'hAAAAAAAA; - endcase - end - always@(byte_addr__h705 or - CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1 or - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2) - begin - case (byte_addr__h705) - 64'd0: data64__h987 = 64'h0202859300000297; - 64'd8: data64__h987 = 64'h0182B283F1402573; - default: data64__h987 = - { CASE_byte_addr05_16_0x0_24_0x0_32_0x54040000_4_ETC__q1, - CASE_byte_addr05_16_0x28067_24_0x80000000_32_0_ETC__q2 }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_module_ready$EN) - rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_module_ready = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - begin - v__h808 = $stime; - #0; - end - v__h802 = v__h808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", - v__h802); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_slave_xactor_f_rd_addr_first_BITS_31_TO_29_ETC___d18) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - begin - v__h8928 = $stime; - #0; - end - v__h8922 = v__h8928 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", - v__h8922); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_slave_xactor_f_wr_addr_first__208_BITS_31__ETC___d1218) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h9221 = $stime; - #0; - end - v__h9215 = v__h9221 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9215, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h9331 = $stime; - #0; - end - v__h9325 = v__h9331 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9325, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkBoot_ROM - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCPU.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCPU.v deleted file mode 100644 index 87171917..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCPU.v +++ /dev/null @@ -1,6297 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_hart0_server_reset_request_put O 1 reg -// hart0_server_reset_response_get O 1 reg -// RDY_hart0_server_reset_response_get O 1 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_set_verbosity O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// hart0_server_reset_request_put I 1 reg -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// nmi_req_set_not_clear I 1 -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// EN_hart0_server_reset_request_put I 1 -// EN_set_verbosity I 1 -// EN_hart0_server_reset_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> imem_master_rready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> dmem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCPU(CLK, - RST_N, - - hart0_server_reset_request_put, - EN_hart0_server_reset_request_put, - RDY_hart0_server_reset_request_put, - - EN_hart0_server_reset_response_get, - hart0_server_reset_response_get, - RDY_hart0_server_reset_response_get, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - nmi_req_set_not_clear, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity); - input CLK; - input RST_N; - - // action method hart0_server_reset_request_put - input hart0_server_reset_request_put; - input EN_hart0_server_reset_request_put; - output RDY_hart0_server_reset_request_put; - - // actionvalue method hart0_server_reset_response_get - input EN_hart0_server_reset_response_get; - output hart0_server_reset_response_get; - output RDY_hart0_server_reset_response_get; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_hart0_server_reset_request_put, - RDY_hart0_server_reset_response_get, - RDY_set_verbosity, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - hart0_server_reset_response_get, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid; - - // register cfg_logdelay - reg [63 : 0] cfg_logdelay; - wire [63 : 0] cfg_logdelay$D_IN; - wire cfg_logdelay$EN; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register imem_rg_f3 - reg [2 : 0] imem_rg_f3; - wire [2 : 0] imem_rg_f3$D_IN; - wire imem_rg_f3$EN; - - // register imem_rg_instr_15_0 - reg [15 : 0] imem_rg_instr_15_0; - wire [15 : 0] imem_rg_instr_15_0$D_IN; - wire imem_rg_instr_15_0$EN; - - // register imem_rg_mstatus_MXR - reg imem_rg_mstatus_MXR; - wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN; - - // register imem_rg_pc - reg [63 : 0] imem_rg_pc; - reg [63 : 0] imem_rg_pc$D_IN; - wire imem_rg_pc$EN; - - // register imem_rg_priv - reg [1 : 0] imem_rg_priv; - wire [1 : 0] imem_rg_priv$D_IN; - wire imem_rg_priv$EN; - - // register imem_rg_satp - reg [63 : 0] imem_rg_satp; - wire [63 : 0] imem_rg_satp$D_IN; - wire imem_rg_satp$EN; - - // register imem_rg_sstatus_SUM - reg imem_rg_sstatus_SUM; - wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN; - - // register imem_rg_tval - reg [63 : 0] imem_rg_tval; - reg [63 : 0] imem_rg_tval$D_IN; - wire imem_rg_tval$EN; - - // register rg_cur_priv - reg [1 : 0] rg_cur_priv; - reg [1 : 0] rg_cur_priv$D_IN; - wire rg_cur_priv$EN; - - // register rg_mstatus_MXR - reg rg_mstatus_MXR; - wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN; - - // register rg_next_pc - reg [63 : 0] rg_next_pc; - reg [63 : 0] rg_next_pc$D_IN; - wire rg_next_pc$EN; - - // register rg_run_on_reset - reg rg_run_on_reset; - wire rg_run_on_reset$D_IN, rg_run_on_reset$EN; - - // register rg_sstatus_SUM - reg rg_sstatus_SUM; - wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN; - - // register rg_start_CPI_cycles - reg [63 : 0] rg_start_CPI_cycles; - wire [63 : 0] rg_start_CPI_cycles$D_IN; - wire rg_start_CPI_cycles$EN; - - // register rg_start_CPI_instrs - reg [63 : 0] rg_start_CPI_instrs; - wire [63 : 0] rg_start_CPI_instrs$D_IN; - wire rg_start_CPI_instrs$EN; - - // register rg_state - reg [3 : 0] rg_state; - reg [3 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register stage1_rg_full - reg stage1_rg_full; - reg stage1_rg_full$D_IN; - wire stage1_rg_full$EN; - - // register stage2_rg_full - reg stage2_rg_full; - reg stage2_rg_full$D_IN; - wire stage2_rg_full$EN; - - // register stage2_rg_resetting - reg stage2_rg_resetting; - wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN; - - // register stage2_rg_stage2 - reg [297 : 0] stage2_rg_stage2; - wire [297 : 0] stage2_rg_stage2$D_IN; - wire stage2_rg_stage2$EN; - - // register stage3_rg_full - reg stage3_rg_full; - reg stage3_rg_full$D_IN; - wire stage3_rg_full$EN; - - // register stage3_rg_stage3 - reg [167 : 0] stage3_rg_stage3; - wire [167 : 0] stage3_rg_stage3$D_IN; - wire stage3_rg_stage3$EN; - - // ports of submodule csr_regfile - reg [63 : 0] csr_regfile$csr_trap_actions_xtval; - reg [3 : 0] csr_regfile$csr_trap_actions_exc_code; - reg [1 : 0] csr_regfile$csr_ret_actions_from_priv; - wire [193 : 0] csr_regfile$csr_trap_actions; - wire [129 : 0] csr_regfile$csr_ret_actions; - wire [64 : 0] csr_regfile$read_csr; - wire [63 : 0] csr_regfile$csr_trap_actions_pc, - csr_regfile$mav_csr_write_word, - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - csr_regfile$read_mstatus, - csr_regfile$read_satp; - wire [27 : 0] csr_regfile$read_misa; - wire [11 : 0] csr_regfile$access_permitted_1_csr_addr, - csr_regfile$access_permitted_2_csr_addr, - csr_regfile$csr_counter_read_fault_csr_addr, - csr_regfile$mav_csr_write_csr_addr, - csr_regfile$mav_read_csr_csr_addr, - csr_regfile$read_csr_csr_addr, - csr_regfile$read_csr_port2_csr_addr; - wire [4 : 0] csr_regfile$interrupt_pending; - wire [1 : 0] csr_regfile$access_permitted_1_priv, - csr_regfile$access_permitted_2_priv, - csr_regfile$csr_counter_read_fault_priv, - csr_regfile$csr_trap_actions_from_priv, - csr_regfile$interrupt_pending_cur_priv; - wire csr_regfile$EN_csr_minstret_incr, - csr_regfile$EN_csr_ret_actions, - csr_regfile$EN_csr_trap_actions, - csr_regfile$EN_debug, - csr_regfile$EN_mav_csr_write, - csr_regfile$EN_mav_read_csr, - csr_regfile$EN_server_reset_request_put, - csr_regfile$EN_server_reset_response_get, - csr_regfile$RDY_server_reset_request_put, - csr_regfile$RDY_server_reset_response_get, - csr_regfile$access_permitted_1, - csr_regfile$access_permitted_1_read_not_write, - csr_regfile$access_permitted_2, - csr_regfile$access_permitted_2_read_not_write, - csr_regfile$csr_trap_actions_interrupt, - csr_regfile$csr_trap_actions_nmi, - csr_regfile$m_external_interrupt_req_set_not_clear, - csr_regfile$nmi_pending, - csr_regfile$nmi_req_set_not_clear, - csr_regfile$s_external_interrupt_req_set_not_clear, - csr_regfile$software_interrupt_req_set_not_clear, - csr_regfile$timer_interrupt_req_set_not_clear, - csr_regfile$wfi_resume; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule gpr_regfile - wire [63 : 0] gpr_regfile$read_rs1, - gpr_regfile$read_rs2, - gpr_regfile$write_rd_rd_val; - wire [4 : 0] gpr_regfile$read_rs1_port2_rs1, - gpr_regfile$read_rs1_rs1, - gpr_regfile$read_rs2_rs2, - gpr_regfile$write_rd_rd; - wire gpr_regfile$EN_server_reset_request_put, - gpr_regfile$EN_server_reset_response_get, - gpr_regfile$EN_write_rd, - gpr_regfile$RDY_server_reset_request_put, - gpr_regfile$RDY_server_reset_response_get; - - // ports of submodule near_mem - reg [63 : 0] near_mem$imem_req_addr; - reg [1 : 0] near_mem$dmem_req_op; - reg near_mem$imem_req_mstatus_MXR, near_mem$imem_req_sstatus_SUM; - wire [63 : 0] near_mem$dmem_master_araddr, - near_mem$dmem_master_awaddr, - near_mem$dmem_master_rdata, - near_mem$dmem_master_wdata, - near_mem$dmem_req_addr, - near_mem$dmem_req_satp, - near_mem$dmem_req_store_value, - near_mem$dmem_word64, - near_mem$imem_master_araddr, - near_mem$imem_master_awaddr, - near_mem$imem_master_rdata, - near_mem$imem_master_wdata, - near_mem$imem_pc, - near_mem$imem_req_satp; - wire [31 : 0] near_mem$imem_instr; - wire [7 : 0] near_mem$dmem_master_arlen, - near_mem$dmem_master_awlen, - near_mem$dmem_master_wstrb, - near_mem$imem_master_arlen, - near_mem$imem_master_awlen, - near_mem$imem_master_wstrb, - near_mem$server_fence_request_put; - wire [6 : 0] near_mem$dmem_req_amo_funct7; - wire [3 : 0] near_mem$dmem_exc_code, - near_mem$dmem_master_arcache, - near_mem$dmem_master_arid, - near_mem$dmem_master_arqos, - near_mem$dmem_master_arregion, - near_mem$dmem_master_awcache, - near_mem$dmem_master_awid, - near_mem$dmem_master_awqos, - near_mem$dmem_master_awregion, - near_mem$dmem_master_bid, - near_mem$dmem_master_rid, - near_mem$dmem_master_wid, - near_mem$imem_exc_code, - near_mem$imem_master_arcache, - near_mem$imem_master_arid, - near_mem$imem_master_arqos, - near_mem$imem_master_arregion, - near_mem$imem_master_awcache, - near_mem$imem_master_awid, - near_mem$imem_master_awqos, - near_mem$imem_master_awregion, - near_mem$imem_master_bid, - near_mem$imem_master_rid, - near_mem$imem_master_wid; - wire [2 : 0] near_mem$dmem_master_arprot, - near_mem$dmem_master_arsize, - near_mem$dmem_master_awprot, - near_mem$dmem_master_awsize, - near_mem$dmem_req_f3, - near_mem$imem_master_arprot, - near_mem$imem_master_arsize, - near_mem$imem_master_awprot, - near_mem$imem_master_awsize, - near_mem$imem_req_f3; - wire [1 : 0] near_mem$dmem_master_arburst, - near_mem$dmem_master_awburst, - near_mem$dmem_master_bresp, - near_mem$dmem_master_rresp, - near_mem$dmem_req_priv, - near_mem$imem_master_arburst, - near_mem$imem_master_awburst, - near_mem$imem_master_bresp, - near_mem$imem_master_rresp, - near_mem$imem_req_priv; - wire near_mem$EN_dmem_req, - near_mem$EN_imem_req, - near_mem$EN_server_fence_i_request_put, - near_mem$EN_server_fence_i_response_get, - near_mem$EN_server_fence_request_put, - near_mem$EN_server_fence_response_get, - near_mem$EN_server_reset_request_put, - near_mem$EN_server_reset_response_get, - near_mem$EN_sfence_vma, - near_mem$RDY_server_fence_i_request_put, - near_mem$RDY_server_fence_i_response_get, - near_mem$RDY_server_fence_request_put, - near_mem$RDY_server_fence_response_get, - near_mem$RDY_server_reset_request_put, - near_mem$RDY_server_reset_response_get, - near_mem$dmem_exc, - near_mem$dmem_master_arlock, - near_mem$dmem_master_arready, - near_mem$dmem_master_arvalid, - near_mem$dmem_master_awlock, - near_mem$dmem_master_awready, - near_mem$dmem_master_awvalid, - near_mem$dmem_master_bready, - near_mem$dmem_master_bvalid, - near_mem$dmem_master_rlast, - near_mem$dmem_master_rready, - near_mem$dmem_master_rvalid, - near_mem$dmem_master_wlast, - near_mem$dmem_master_wready, - near_mem$dmem_master_wvalid, - near_mem$dmem_req_mstatus_MXR, - near_mem$dmem_req_sstatus_SUM, - near_mem$dmem_valid, - near_mem$imem_exc, - near_mem$imem_is_i32_not_i16, - near_mem$imem_master_arlock, - near_mem$imem_master_arready, - near_mem$imem_master_arvalid, - near_mem$imem_master_awlock, - near_mem$imem_master_awready, - near_mem$imem_master_awvalid, - near_mem$imem_master_bready, - near_mem$imem_master_bvalid, - near_mem$imem_master_rlast, - near_mem$imem_master_rready, - near_mem$imem_master_rvalid, - near_mem$imem_master_wlast, - near_mem$imem_master_wready, - near_mem$imem_master_wvalid, - near_mem$imem_valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_pc_reset_value; - - // ports of submodule stage1_f_reset_reqs - wire stage1_f_reset_reqs$CLR, - stage1_f_reset_reqs$DEQ, - stage1_f_reset_reqs$EMPTY_N, - stage1_f_reset_reqs$ENQ, - stage1_f_reset_reqs$FULL_N; - - // ports of submodule stage1_f_reset_rsps - wire stage1_f_reset_rsps$CLR, - stage1_f_reset_rsps$DEQ, - stage1_f_reset_rsps$EMPTY_N, - stage1_f_reset_rsps$ENQ, - stage1_f_reset_rsps$FULL_N; - - // ports of submodule stage2_f_reset_reqs - wire stage2_f_reset_reqs$CLR, - stage2_f_reset_reqs$DEQ, - stage2_f_reset_reqs$EMPTY_N, - stage2_f_reset_reqs$ENQ, - stage2_f_reset_reqs$FULL_N; - - // ports of submodule stage2_f_reset_rsps - wire stage2_f_reset_rsps$CLR, - stage2_f_reset_rsps$DEQ, - stage2_f_reset_rsps$EMPTY_N, - stage2_f_reset_rsps$ENQ, - stage2_f_reset_rsps$FULL_N; - - // ports of submodule stage2_mbox - wire [63 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word; - wire [3 : 0] stage2_mbox$set_verbosity_verbosity; - wire [2 : 0] stage2_mbox$req_f3; - wire stage2_mbox$EN_req, - stage2_mbox$EN_req_reset, - stage2_mbox$EN_rsp_reset, - stage2_mbox$EN_set_verbosity, - stage2_mbox$req_is_OP_not_OP_32, - stage2_mbox$valid; - - // ports of submodule stage3_f_reset_reqs - wire stage3_f_reset_reqs$CLR, - stage3_f_reset_reqs$DEQ, - stage3_f_reset_reqs$EMPTY_N, - stage3_f_reset_reqs$ENQ, - stage3_f_reset_reqs$FULL_N; - - // ports of submodule stage3_f_reset_rsps - wire stage3_f_reset_rsps$CLR, - stage3_f_reset_rsps$DEQ, - stage3_f_reset_rsps$EMPTY_N, - stage3_f_reset_rsps$ENQ, - stage3_f_reset_rsps$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_imem_rl_assert_fail, - CAN_FIRE_RL_imem_rl_fetch_next_32b, - CAN_FIRE_RL_rl_WFI_resume, - CAN_FIRE_RL_rl_finish_FENCE, - CAN_FIRE_RL_rl_finish_FENCE_I, - CAN_FIRE_RL_rl_finish_SFENCE_VMA, - CAN_FIRE_RL_rl_pipe, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_RL_rl_reset_from_WFI, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_show_pipe, - CAN_FIRE_RL_rl_stage1_CSRR_S_or_C, - CAN_FIRE_RL_rl_stage1_CSRR_W, - CAN_FIRE_RL_rl_stage1_FENCE, - CAN_FIRE_RL_rl_stage1_FENCE_I, - CAN_FIRE_RL_rl_stage1_SFENCE_VMA, - CAN_FIRE_RL_rl_stage1_WFI, - CAN_FIRE_RL_rl_stage1_interrupt, - CAN_FIRE_RL_rl_stage1_restart_after_csrrx, - CAN_FIRE_RL_rl_stage1_trap, - CAN_FIRE_RL_rl_stage1_xRET, - CAN_FIRE_RL_rl_stage2_nonpipe, - CAN_FIRE_RL_rl_trap_fetch, - CAN_FIRE_RL_stage1_rl_reset, - CAN_FIRE_RL_stage2_rl_reset_begin, - CAN_FIRE_RL_stage2_rl_reset_end, - CAN_FIRE_RL_stage3_rl_reset, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_hart0_server_reset_request_put, - CAN_FIRE_hart0_server_reset_response_get, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_set_verbosity, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_imem_rl_assert_fail, - WILL_FIRE_RL_imem_rl_fetch_next_32b, - WILL_FIRE_RL_rl_WFI_resume, - WILL_FIRE_RL_rl_finish_FENCE, - WILL_FIRE_RL_rl_finish_FENCE_I, - WILL_FIRE_RL_rl_finish_SFENCE_VMA, - WILL_FIRE_RL_rl_pipe, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_RL_rl_reset_from_WFI, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_show_pipe, - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C, - WILL_FIRE_RL_rl_stage1_CSRR_W, - WILL_FIRE_RL_rl_stage1_FENCE, - WILL_FIRE_RL_rl_stage1_FENCE_I, - WILL_FIRE_RL_rl_stage1_SFENCE_VMA, - WILL_FIRE_RL_rl_stage1_WFI, - WILL_FIRE_RL_rl_stage1_interrupt, - WILL_FIRE_RL_rl_stage1_restart_after_csrrx, - WILL_FIRE_RL_rl_stage1_trap, - WILL_FIRE_RL_rl_stage1_xRET, - WILL_FIRE_RL_rl_stage2_nonpipe, - WILL_FIRE_RL_rl_trap_fetch, - WILL_FIRE_RL_stage1_rl_reset, - WILL_FIRE_RL_stage2_rl_reset_begin, - WILL_FIRE_RL_stage2_rl_reset_end, - WILL_FIRE_RL_stage3_rl_reset, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_hart0_server_reset_request_put, - WILL_FIRE_hart0_server_reset_response_get, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_set_verbosity, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - reg [63 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2; - wire [63 : 0] MUX_near_mem$imem_req_2__VAL_1, - MUX_near_mem$imem_req_2__VAL_2, - MUX_near_mem$imem_req_2__VAL_5; - wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1, - MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_2, - MUX_rg_state$write_1__VAL_3; - wire MUX_csr_regfile$mav_csr_write_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_1, - MUX_gpr_regfile$write_rd_1__SEL_3, - MUX_imem_rg_f3$write_1__SEL_1, - MUX_imem_rg_f3$write_1__SEL_2, - MUX_imem_rg_mstatus_MXR$write_1__SEL_4, - MUX_imem_rg_pc$write_1__SEL_4, - MUX_near_mem$imem_req_1__SEL_6, - MUX_rg_cur_priv$write_1__SEL_1, - MUX_rg_mstatus_MXR$write_1__SEL_1, - MUX_rg_next_pc$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_11, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_4, - MUX_rg_state$write_1__SEL_6, - MUX_rg_state$write_1__SEL_7, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9, - MUX_stage1_rg_full$write_1__VAL_2, - MUX_stage2_rg_full$write_1__VAL_2; - - // remaining internal signals - reg [63 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1151, - _theResult_____1_fst__h13382, - alu_outputs___1_val1__h12576, - rs1_val__h18963, - x_out_bypass_rd_val__h6000, - x_out_data_to_stage2_addr__h12206, - x_out_data_to_stage2_val1__h12207, - x_out_data_to_stage3_rd_val__h5649; - reg [4 : 0] x_out_bypass_rd__h5999, x_out_data_to_stage3_rd__h5648; - reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q5, - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14, - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q16, - CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15, - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17, - CASE_theResult__283_BITS_31_TO_20_0b0_CASE_rg__ETC__q6, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d811, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d831, - alu_outputs_exc_code__h12932; - reg [2 : 0] CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18, - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916; - reg [1 : 0] CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q1, - CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2; - reg CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12, - CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762, - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d136, - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145; - wire [127 : 0] csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1401; - wire [63 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1064, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1065, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d962, - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1348, - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d971, - _theResult_____1_fst__h13375, - _theResult_____1_fst__h13410, - _theResult____h23527, - _theResult___fst__h13487, - _theResult___fst__h13494, - _theResult___fst__h13601, - _theResult___snd__h14727, - alu_outputs___1_addr__h12330, - alu_outputs___1_addr__h12351, - alu_outputs___1_addr__h12377, - alu_outputs___1_addr__h12629, - alu_outputs___1_addr__h12650, - alu_outputs___1_val1__h12492, - alu_outputs___1_val1__h12530, - alu_outputs___1_val1__h12553, - alu_outputs___1_val1__h12592, - alu_outputs___1_val1__h12608, - alu_outputs___1_val1__h12890, - alu_outputs___1_val1__h12911, - branch_target__h12308, - cpi__h23529, - cpifrac__h23530, - data_to_stage2_addr__h12198, - delta_CPI_cycles__h23525, - delta_CPI_instrs___1__h23562, - delta_CPI_instrs__h23526, - fall_through_pc__h12162, - next_pc___1__h14260, - next_pc__h14258, - output_stage2___1_bypass_rd_val__h5988, - rd_val___1__h13363, - rd_val___1__h13371, - rd_val___1__h13378, - rd_val___1__h13385, - rd_val___1__h13392, - rd_val___1__h13399, - rd_val___1__h14756, - rd_val___1__h14787, - rd_val___1__h14841, - rd_val___1__h14870, - rd_val___1__h14922, - rd_val___1__h14970, - rd_val___1__h14976, - rd_val___1__h15021, - rd_val__h12119, - rd_val__h14623, - rd_val__h14675, - rd_val__h14697, - rd_val__h6112, - rs1_val__h18473, - rs1_val_bypassed__h4291, - rs2_val__h12304, - trap_info_tval__h14094, - val__h12121, - val__h6114, - value__h14148, - x__h23528, - x_out_data_to_stage2_val2__h12208, - x_out_next_pc__h12175, - y__h19264; - wire [31 : 0] IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d466, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d467, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d469, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d471, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d473, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d475, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d476, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d477, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d479, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d480, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d481, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d483, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d485, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d486, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d488, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d489, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d490, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d491, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d492, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d493, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d494, - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d495, - _theResult____h4283, - _theResult___fst__h6331, - _theResult___fst__h6359, - alu_outputs___1_addr2629_BITS_31_TO_0__q20, - instr___1__h6160, - instr__h10113, - instr__h10291, - instr__h10410, - instr__h10505, - instr__h10641, - instr__h10777, - instr__h10913, - instr__h11051, - instr__h11189, - instr__h11347, - instr__h11443, - instr__h11596, - instr__h11795, - instr__h11946, - instr__h4281, - instr__h6431, - instr__h6576, - instr__h6768, - instr__h6963, - instr__h7192, - instr__h7646, - instr__h7762, - instr__h7827, - instr__h8144, - instr__h8482, - instr__h8666, - instr__h8795, - instr__h9022, - instr__h9277, - instr__h9449, - instr__h9618, - instr__h9807, - instr__h9996, - instr_out___1__h6301, - instr_out___1__h6333, - instr_out___1__h6361, - rs1_val_bypassed291_BITS_31_TO_0_MINUS_rs2_val_ETC__q11, - rs1_val_bypassed291_BITS_31_TO_0_PLUS_rs2_val2_ETC__q10, - rs1_val_bypassed291_BITS_31_TO_0_SRL_rs2_val23_ETC__q9, - rs1_val_bypassed291_BITS_31_TO_0__q8, - tmp__h14869, - v32__h12581, - x__h14790, - x__h14844, - x__h14979, - x__h15024, - x_out_data_to_stage2_instr__h12203; - wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292, - theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q4; - wire [19 : 0] imm20__h8534; - wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317, - theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q3; - wire [11 : 0] imm12__h11444, - imm12__h11796, - imm12__h6432, - imm12__h6769, - imm12__h8406, - imm12__h9075, - imm12__h9290, - imm12__h9486, - imm12__h9823, - offset__h7139, - theResult__283_BITS_31_TO_20__q19, - theResult__283_BITS_31_TO_25_CONCAT_theResult__ETC__q7; - wire [9 : 0] funct10__h12562, nzimm10__h9073, nzimm10__h9288; - wire [8 : 0] offset__h11358, offset__h7771; - wire [7 : 0] offset__h11730, offset__h6202; - wire [6 : 0] offset__h6711; - wire [5 : 0] imm6__h8404, shamt__h12477; - wire [4 : 0] offset_BITS_4_TO_0___h12071, - offset_BITS_4_TO_0___h6700, - offset_BITS_4_TO_0___h7131, - rd__h6771, - rs1__h6770, - x_out_data_to_stage2_rd__h12205; - wire [3 : 0] IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d774, - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833, - IF_rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_E_ETC___d809, - alu_outputs___1_exc_code__h12886, - cur_verbosity__h2988, - x_out_trap_info_exc_code__h14097; - wire [1 : 0] IF_NOT_near_mem_dmem_valid__13_32_OR_NOT_near__ETC___d179, - IF_near_mem_dmem_valid__13_THEN_IF_near_mem_dm_ETC___d116, - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122, - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183, - IF_stage2_rg_stage2_2_BITS_196_TO_192_52_EQ_0__ETC___d178, - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119, - sxl__h4705, - uxl__h4706; - wire IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1209, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765, - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d717, - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d724, - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d1398, - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499, - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501, - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d605, - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1259, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1291, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1293, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1296, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1310, - NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d899, - NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d940, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d208, - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d213, - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1219, - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1230, - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1238, - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504, - _0_OR_0_OR_near_mem_imem_exc__20_OR_IF_IF_NOT_n_ETC___d1289, - csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1212, - csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1217, - csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1223, - csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d302, - csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d308, - gpr_regfile_RDY_server_reset_request_put__161__ETC___d1173, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1076, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1079, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1082, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1085, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1088, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1091, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1094, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1097, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1100, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1103, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1106, - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1109, - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d511, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d513, - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1208, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703, - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770, - rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_EQ_0_ETC___d807, - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313, - rg_state_2_EQ_3_225_AND_stage3_rg_full_2_OR_NO_ETC___d1244, - stage2_f_reset_rsps_i_notEmpty__182_AND_stage3_ETC___d1191; - - // action method hart0_server_reset_request_put - assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_hart0_server_reset_request_put = - EN_hart0_server_reset_request_put ; - - // actionvalue method hart0_server_reset_response_get - assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ; - assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_hart0_server_reset_response_get = - EN_hart0_server_reset_response_get ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = near_mem$imem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = near_mem$imem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = near_mem$imem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = near_mem$imem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = near_mem$imem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = near_mem$imem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = near_mem$imem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = near_mem$imem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = near_mem$imem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = near_mem$imem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = near_mem$imem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = near_mem$imem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = near_mem$imem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = near_mem$imem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = near_mem$imem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = near_mem$imem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = near_mem$imem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = near_mem$imem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = near_mem$imem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = near_mem$imem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = near_mem$imem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = near_mem$imem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = near_mem$imem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = near_mem$imem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = near_mem$imem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = near_mem$imem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = near_mem$imem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = near_mem$imem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = near_mem$imem_master_rready ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = near_mem$dmem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = near_mem$dmem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = near_mem$dmem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = near_mem$dmem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = near_mem$dmem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = near_mem$dmem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = near_mem$dmem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = near_mem$dmem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = near_mem$dmem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = near_mem$dmem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = near_mem$dmem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = near_mem$dmem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = near_mem$dmem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = near_mem$dmem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = near_mem$dmem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = near_mem$dmem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = near_mem$dmem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = near_mem$dmem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = near_mem$dmem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = near_mem$dmem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = near_mem$dmem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = near_mem$dmem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = near_mem$dmem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = near_mem$dmem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = near_mem$dmem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = near_mem$dmem_master_rready ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // submodule csr_regfile - mkCSR_RegFile csr_regfile(.CLK(CLK), - .RST_N(RST_N), - .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr), - .access_permitted_1_priv(csr_regfile$access_permitted_1_priv), - .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write), - .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr), - .access_permitted_2_priv(csr_regfile$access_permitted_2_priv), - .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write), - .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr), - .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv), - .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv), - .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code), - .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv), - .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt), - .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi), - .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc), - .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval), - .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv), - .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear), - .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr), - .mav_csr_write_word(csr_regfile$mav_csr_write_word), - .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr), - .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear), - .read_csr_csr_addr(csr_regfile$read_csr_csr_addr), - .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr), - .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear), - .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear), - .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get), - .EN_mav_read_csr(csr_regfile$EN_mav_read_csr), - .EN_mav_csr_write(csr_regfile$EN_mav_csr_write), - .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions), - .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions), - .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr), - .EN_debug(csr_regfile$EN_debug), - .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get), - .read_csr(csr_regfile$read_csr), - .read_csr_port2(), - .mav_read_csr(), - .mav_csr_write(), - .read_misa(csr_regfile$read_misa), - .read_mstatus(csr_regfile$read_mstatus), - .read_ustatus(), - .read_satp(csr_regfile$read_satp), - .csr_trap_actions(csr_regfile$csr_trap_actions), - .RDY_csr_trap_actions(), - .csr_ret_actions(csr_regfile$csr_ret_actions), - .RDY_csr_ret_actions(), - .read_csr_minstret(csr_regfile$read_csr_minstret), - .read_csr_mcycle(csr_regfile$read_csr_mcycle), - .read_csr_mtime(), - .access_permitted_1(csr_regfile$access_permitted_1), - .access_permitted_2(csr_regfile$access_permitted_2), - .csr_counter_read_fault(), - .csr_mip_read(), - .interrupt_pending(csr_regfile$interrupt_pending), - .wfi_resume(csr_regfile$wfi_resume), - .nmi_pending(csr_regfile$nmi_pending), - .RDY_debug()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule gpr_regfile - mkGPR_RegFile gpr_regfile(.CLK(CLK), - .RST_N(RST_N), - .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1), - .read_rs1_rs1(gpr_regfile$read_rs1_rs1), - .read_rs2_rs2(gpr_regfile$read_rs2_rs2), - .write_rd_rd(gpr_regfile$write_rd_rd), - .write_rd_rd_val(gpr_regfile$write_rd_rd_val), - .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put), - .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get), - .EN_write_rd(gpr_regfile$EN_write_rd), - .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put), - .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get), - .read_rs1(gpr_regfile$read_rs1), - .read_rs1_port2(), - .read_rs2(gpr_regfile$read_rs2)); - - // submodule near_mem - mkNear_Mem near_mem(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(near_mem$dmem_master_arready), - .dmem_master_awready(near_mem$dmem_master_awready), - .dmem_master_bid(near_mem$dmem_master_bid), - .dmem_master_bresp(near_mem$dmem_master_bresp), - .dmem_master_bvalid(near_mem$dmem_master_bvalid), - .dmem_master_rdata(near_mem$dmem_master_rdata), - .dmem_master_rid(near_mem$dmem_master_rid), - .dmem_master_rlast(near_mem$dmem_master_rlast), - .dmem_master_rresp(near_mem$dmem_master_rresp), - .dmem_master_rvalid(near_mem$dmem_master_rvalid), - .dmem_master_wready(near_mem$dmem_master_wready), - .dmem_req_addr(near_mem$dmem_req_addr), - .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7), - .dmem_req_f3(near_mem$dmem_req_f3), - .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR), - .dmem_req_op(near_mem$dmem_req_op), - .dmem_req_priv(near_mem$dmem_req_priv), - .dmem_req_satp(near_mem$dmem_req_satp), - .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM), - .dmem_req_store_value(near_mem$dmem_req_store_value), - .imem_master_arready(near_mem$imem_master_arready), - .imem_master_awready(near_mem$imem_master_awready), - .imem_master_bid(near_mem$imem_master_bid), - .imem_master_bresp(near_mem$imem_master_bresp), - .imem_master_bvalid(near_mem$imem_master_bvalid), - .imem_master_rdata(near_mem$imem_master_rdata), - .imem_master_rid(near_mem$imem_master_rid), - .imem_master_rlast(near_mem$imem_master_rlast), - .imem_master_rresp(near_mem$imem_master_rresp), - .imem_master_rvalid(near_mem$imem_master_rvalid), - .imem_master_wready(near_mem$imem_master_wready), - .imem_req_addr(near_mem$imem_req_addr), - .imem_req_f3(near_mem$imem_req_f3), - .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR), - .imem_req_priv(near_mem$imem_req_priv), - .imem_req_satp(near_mem$imem_req_satp), - .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM), - .server_fence_request_put(near_mem$server_fence_request_put), - .EN_server_reset_request_put(near_mem$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem$EN_server_reset_response_get), - .EN_imem_req(near_mem$EN_imem_req), - .EN_dmem_req(near_mem$EN_dmem_req), - .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put), - .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get), - .EN_server_fence_request_put(near_mem$EN_server_fence_request_put), - .EN_server_fence_response_get(near_mem$EN_server_fence_response_get), - .EN_sfence_vma(near_mem$EN_sfence_vma), - .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get), - .imem_valid(near_mem$imem_valid), - .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16), - .imem_pc(near_mem$imem_pc), - .imem_instr(near_mem$imem_instr), - .imem_exc(near_mem$imem_exc), - .imem_exc_code(near_mem$imem_exc_code), - .imem_tval(), - .imem_master_awvalid(near_mem$imem_master_awvalid), - .imem_master_awid(near_mem$imem_master_awid), - .imem_master_awaddr(near_mem$imem_master_awaddr), - .imem_master_awlen(near_mem$imem_master_awlen), - .imem_master_awsize(near_mem$imem_master_awsize), - .imem_master_awburst(near_mem$imem_master_awburst), - .imem_master_awlock(near_mem$imem_master_awlock), - .imem_master_awcache(near_mem$imem_master_awcache), - .imem_master_awprot(near_mem$imem_master_awprot), - .imem_master_awqos(near_mem$imem_master_awqos), - .imem_master_awregion(near_mem$imem_master_awregion), - .imem_master_wvalid(near_mem$imem_master_wvalid), - .imem_master_wid(near_mem$imem_master_wid), - .imem_master_wdata(near_mem$imem_master_wdata), - .imem_master_wstrb(near_mem$imem_master_wstrb), - .imem_master_wlast(near_mem$imem_master_wlast), - .imem_master_bready(near_mem$imem_master_bready), - .imem_master_arvalid(near_mem$imem_master_arvalid), - .imem_master_arid(near_mem$imem_master_arid), - .imem_master_araddr(near_mem$imem_master_araddr), - .imem_master_arlen(near_mem$imem_master_arlen), - .imem_master_arsize(near_mem$imem_master_arsize), - .imem_master_arburst(near_mem$imem_master_arburst), - .imem_master_arlock(near_mem$imem_master_arlock), - .imem_master_arcache(near_mem$imem_master_arcache), - .imem_master_arprot(near_mem$imem_master_arprot), - .imem_master_arqos(near_mem$imem_master_arqos), - .imem_master_arregion(near_mem$imem_master_arregion), - .imem_master_rready(near_mem$imem_master_rready), - .dmem_valid(near_mem$dmem_valid), - .dmem_word64(near_mem$dmem_word64), - .dmem_st_amo_val(), - .dmem_exc(near_mem$dmem_exc), - .dmem_exc_code(near_mem$dmem_exc_code), - .dmem_master_awvalid(near_mem$dmem_master_awvalid), - .dmem_master_awid(near_mem$dmem_master_awid), - .dmem_master_awaddr(near_mem$dmem_master_awaddr), - .dmem_master_awlen(near_mem$dmem_master_awlen), - .dmem_master_awsize(near_mem$dmem_master_awsize), - .dmem_master_awburst(near_mem$dmem_master_awburst), - .dmem_master_awlock(near_mem$dmem_master_awlock), - .dmem_master_awcache(near_mem$dmem_master_awcache), - .dmem_master_awprot(near_mem$dmem_master_awprot), - .dmem_master_awqos(near_mem$dmem_master_awqos), - .dmem_master_awregion(near_mem$dmem_master_awregion), - .dmem_master_wvalid(near_mem$dmem_master_wvalid), - .dmem_master_wid(near_mem$dmem_master_wid), - .dmem_master_wdata(near_mem$dmem_master_wdata), - .dmem_master_wstrb(near_mem$dmem_master_wstrb), - .dmem_master_wlast(near_mem$dmem_master_wlast), - .dmem_master_bready(near_mem$dmem_master_bready), - .dmem_master_arvalid(near_mem$dmem_master_arvalid), - .dmem_master_arid(near_mem$dmem_master_arid), - .dmem_master_araddr(near_mem$dmem_master_araddr), - .dmem_master_arlen(near_mem$dmem_master_arlen), - .dmem_master_arsize(near_mem$dmem_master_arsize), - .dmem_master_arburst(near_mem$dmem_master_arburst), - .dmem_master_arlock(near_mem$dmem_master_arlock), - .dmem_master_arcache(near_mem$dmem_master_arcache), - .dmem_master_arprot(near_mem$dmem_master_arprot), - .dmem_master_arqos(near_mem$dmem_master_arqos), - .dmem_master_arregion(near_mem$dmem_master_arregion), - .dmem_master_rready(near_mem$dmem_master_rready), - .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put), - .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get), - .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put), - .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get), - .RDY_sfence_vma()); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(soc_map$m_pc_reset_value), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule stage1_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_reqs$ENQ), - .DEQ(stage1_f_reset_reqs$DEQ), - .CLR(stage1_f_reset_reqs$CLR), - .FULL_N(stage1_f_reset_reqs$FULL_N), - .EMPTY_N(stage1_f_reset_reqs$EMPTY_N)); - - // submodule stage1_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage1_f_reset_rsps$ENQ), - .DEQ(stage1_f_reset_rsps$DEQ), - .CLR(stage1_f_reset_rsps$CLR), - .FULL_N(stage1_f_reset_rsps$FULL_N), - .EMPTY_N(stage1_f_reset_rsps$EMPTY_N)); - - // submodule stage2_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_reqs$ENQ), - .DEQ(stage2_f_reset_reqs$DEQ), - .CLR(stage2_f_reset_reqs$CLR), - .FULL_N(stage2_f_reset_reqs$FULL_N), - .EMPTY_N(stage2_f_reset_reqs$EMPTY_N)); - - // submodule stage2_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage2_f_reset_rsps$ENQ), - .DEQ(stage2_f_reset_rsps$DEQ), - .CLR(stage2_f_reset_rsps$CLR), - .FULL_N(stage2_f_reset_rsps$FULL_N), - .EMPTY_N(stage2_f_reset_rsps$EMPTY_N)); - - // submodule stage2_mbox - mkRISCV_MBox stage2_mbox(.CLK(CLK), - .RST_N(RST_N), - .req_f3(stage2_mbox$req_f3), - .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32), - .req_v1(stage2_mbox$req_v1), - .req_v2(stage2_mbox$req_v2), - .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity), - .EN_set_verbosity(stage2_mbox$EN_set_verbosity), - .EN_req_reset(stage2_mbox$EN_req_reset), - .EN_rsp_reset(stage2_mbox$EN_rsp_reset), - .EN_req(stage2_mbox$EN_req), - .RDY_set_verbosity(), - .RDY_req_reset(), - .RDY_rsp_reset(), - .valid(stage2_mbox$valid), - .word(stage2_mbox$word)); - - // submodule stage3_f_reset_reqs - FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_reqs$ENQ), - .DEQ(stage3_f_reset_reqs$DEQ), - .CLR(stage3_f_reset_reqs$CLR), - .FULL_N(stage3_f_reset_reqs$FULL_N), - .EMPTY_N(stage3_f_reset_reqs$EMPTY_N)); - - // submodule stage3_f_reset_rsps - FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(stage3_f_reset_rsps$ENQ), - .DEQ(stage3_f_reset_rsps$DEQ), - .CLR(stage3_f_reset_rsps$CLR), - .FULL_N(stage3_f_reset_rsps$FULL_N), - .EMPTY_N(stage3_f_reset_rsps$EMPTY_N)); - - // rule RL_rl_show_pipe - assign CAN_FIRE_RL_rl_show_pipe = - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - rg_state != 4'd0 && - rg_state != 4'd1 && - rg_state != 4'd10 ; - assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ; - - // rule RL_rl_stage2_nonpipe - assign CAN_FIRE_RL_rl_stage2_nonpipe = - rg_state == 4'd3 && !stage3_rg_full && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd3 && - (!stage1_rg_full || - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519) ; - assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ; - - // rule RL_rl_stage1_CSRR_W - assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_stage1_CSRR_S_or_C - assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_stage1_restart_after_csrrx - assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx = - CAN_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // rule RL_rl_stage1_xRET - assign CAN_FIRE_RL_rl_stage1_xRET = - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - (IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd7 || - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd8 || - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd9) ; - assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ; - - // rule RL_rl_stage1_FENCE_I - assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_8 ; - - // rule RL_rl_finish_FENCE_I - assign CAN_FIRE_RL_rl_finish_FENCE_I = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_i_response_get && - rg_state == 4'd7 ; - assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ; - - // rule RL_rl_stage1_FENCE - assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_9 ; - - // rule RL_rl_finish_FENCE - assign CAN_FIRE_RL_rl_finish_FENCE = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - near_mem$RDY_server_fence_response_get && - rg_state == 4'd8 ; - assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ; - - // rule RL_rl_stage1_SFENCE_VMA - assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_10 ; - - // rule RL_rl_finish_SFENCE_VMA - assign CAN_FIRE_RL_rl_finish_SFENCE_VMA = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd9 ; - assign WILL_FIRE_RL_rl_finish_SFENCE_VMA = - CAN_FIRE_RL_rl_finish_SFENCE_VMA ; - - // rule RL_rl_stage1_WFI - assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_11 ; - - // rule RL_rl_WFI_resume - assign CAN_FIRE_RL_rl_WFI_resume = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd10 && - csr_regfile$wfi_resume ; - assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ; - - // rule RL_rl_reset_from_WFI - assign CAN_FIRE_RL_rl_reset_from_WFI = - rg_state == 4'd10 && f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_4 ; - - // rule RL_rl_stage1_trap - assign CAN_FIRE_RL_rl_stage1_trap = - rg_state == 4'd4 || - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd11 ; - assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ; - - // rule RL_rl_trap_fetch - assign CAN_FIRE_RL_rl_trap_fetch = - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd5 ; - assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; - - // rule RL_rl_stage1_interrupt - assign CAN_FIRE_RL_rl_stage1_interrupt = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - rg_state == 4'd3 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1209 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd0 && - !stage3_rg_full ; - assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ; - - // rule RL_imem_rl_assert_fail - assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ; - assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = - gpr_regfile$RDY_server_reset_response_get && - near_mem$RDY_server_reset_response_get && - csr_regfile$RDY_server_reset_response_get && - stage1_f_reset_rsps$EMPTY_N && - stage2_f_reset_rsps_i_notEmpty__182_AND_stage3_ETC___d1191 && - rg_state == 4'd1 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_pipe - assign CAN_FIRE_RL_rl_pipe = - (csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1223 || - !near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state_2_EQ_3_225_AND_stage3_rg_full_2_OR_NO_ETC___d1244 ; - assign WILL_FIRE_RL_rl_pipe = - CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = - gpr_regfile_RDY_server_reset_request_put__161__ETC___d1173 && - rg_state == 4'd0 ; - assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ; - - // rule RL_imem_rl_fetch_next_32b - assign CAN_FIRE_RL_imem_rl_fetch_next_32b = - near_mem$imem_valid && - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] == 2'b11 ; - assign WILL_FIRE_RL_imem_rl_fetch_next_32b = - CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // rule RL_stage3_rl_reset - assign CAN_FIRE_RL_stage3_rl_reset = - stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ; - - // rule RL_stage2_rl_reset_end - assign CAN_FIRE_RL_stage2_rl_reset_end = - stage2_f_reset_rsps$FULL_N && stage2_rg_resetting ; - assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ; - - // rule RL_stage2_rl_reset_begin - assign CAN_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ; - - // rule RL_stage1_rl_reset - assign CAN_FIRE_RL_stage1_rl_reset = - stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_csr_regfile$mav_csr_write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 ; - assign MUX_gpr_regfile$write_rd_1__SEL_1 = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[69] ; - assign MUX_gpr_regfile$write_rd_1__SEL_3 = - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - assign MUX_imem_rg_f3$write_1__SEL_1 = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ; - assign MUX_imem_rg_f3$write_1__SEL_2 = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 ; - assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_imem_rg_pc$write_1__SEL_4 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_near_mem$imem_req_1__SEL_6 = - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign MUX_rg_cur_priv$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_mstatus_MXR$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_next_pc$write_1__SEL_1 = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign MUX_rg_state$write_1__SEL_1 = - CAN_FIRE_RL_rl_reset_complete && - !WILL_FIRE_RL_imem_rl_fetch_next_32b ; - assign MUX_rg_state$write_1__SEL_2 = - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd2 ; - assign MUX_rg_state$write_1__SEL_3 = - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd3 ; - assign MUX_rg_state$write_1__SEL_4 = - CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ; - assign MUX_rg_state$write_1__SEL_6 = - WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_rg_state$write_1__SEL_7 = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_state$write_1__SEL_8 = - near_mem$RDY_server_fence_i_request_put && - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd5 ; - assign MUX_rg_state$write_1__SEL_9 = - near_mem$RDY_server_fence_request_put && - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd4 ; - assign MUX_rg_state$write_1__SEL_10 = - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd6 ; - assign MUX_rg_state$write_1__SEL_11 = - rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd10 ; - assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 = - (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ? - csr_regfile$interrupt_pending[3:0] : - 4'd0 ; - always@(x_out_data_to_stage2_instr__h12203 or - csr_regfile$read_csr or - y__h19264 or - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1348) - begin - case (x_out_data_to_stage2_instr__h12203[14:12]) - 3'b010, 3'b110: - MUX_csr_regfile$mav_csr_write_2__VAL_2 = - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1348; - default: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - csr_regfile$read_csr[63:0] & y__h19264; - endcase - end - assign MUX_near_mem$imem_req_2__VAL_1 = - { soc_map$m_pc_reset_value[63:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_2 = - { x_out_next_pc__h12175[63:2], 2'b0 } ; - assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[63:2], 2'b0 } ; - assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd3 : 4'd2 ; - assign MUX_rg_state$write_1__VAL_2 = - csr_regfile$access_permitted_1 ? 4'd6 : 4'd4 ; - assign MUX_rg_state$write_1__VAL_3 = - csr_regfile$access_permitted_2 ? 4'd6 : 4'd4 ; - assign MUX_stage1_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1296 || - (csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1217 || - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1238) && - stage1_rg_full ; - assign MUX_stage2_rg_full$write_1__VAL_2 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1291 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd2 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd0 ; - - // register cfg_logdelay - assign cfg_logdelay$D_IN = set_verbosity_logdelay ; - assign cfg_logdelay$EN = EN_set_verbosity ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register imem_rg_f3 - assign imem_rg_f3$D_IN = 3'b010 ; - assign imem_rg_f3$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_instr_15_0 - assign imem_rg_instr_15_0$D_IN = near_mem$imem_instr[31:16] ; - assign imem_rg_instr_15_0$EN = CAN_FIRE_RL_imem_rl_fetch_next_32b ; - - // register imem_rg_mstatus_MXR - assign imem_rg_mstatus_MXR$D_IN = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - MUX_imem_rg_mstatus_MXR$write_1__SEL_4) ? - csr_regfile$read_mstatus[19] : - rg_mstatus_MXR ; - assign imem_rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_pc - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h12175 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_pc$D_IN = soc_map$m_pc_reset_value; - MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h12175; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_pc$D_IN = x_out_next_pc__h12175; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc; - default: imem_rg_pc$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_pc$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - - // register imem_rg_priv - assign imem_rg_priv$D_IN = rg_cur_priv ; - assign imem_rg_priv$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_satp - assign imem_rg_satp$D_IN = csr_regfile$read_satp ; - assign imem_rg_satp$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_sstatus_SUM - assign imem_rg_sstatus_SUM$D_IN = - WILL_FIRE_RL_rl_trap_fetch && rg_sstatus_SUM ; - assign imem_rg_sstatus_SUM$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register imem_rg_tval - always@(MUX_imem_rg_f3$write_1__SEL_1 or - soc_map$m_pc_reset_value or - MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h12175 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_imem_rg_pc$write_1__SEL_4 or - rg_next_pc or - WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h14260) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - imem_rg_tval$D_IN = soc_map$m_pc_reset_value; - MUX_imem_rg_f3$write_1__SEL_2: - imem_rg_tval$D_IN = x_out_next_pc__h12175; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_tval$D_IN = x_out_next_pc__h12175; - MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - imem_rg_tval$D_IN = next_pc___1__h14260; - default: imem_rg_tval$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign imem_rg_tval$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_imem_rl_fetch_next_32b ; - - // register rg_cur_priv - always@(MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or - csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_cur_priv$write_1__SEL_1: - rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[65:64]; - WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11; - default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_cur_priv$EN = - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mstatus_MXR - assign rg_mstatus_MXR$D_IN = - MUX_rg_mstatus_MXR$write_1__SEL_1 ? - csr_regfile$read_mstatus[19] : - csr_regfile$csr_trap_actions[85] ; - assign rg_mstatus_MXR$EN = - WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt ; - - // register rg_next_pc - always@(MUX_rg_next_pc$write_1__SEL_1 or - x_out_next_pc__h12175 or - MUX_rg_cur_priv$write_1__SEL_1 or - csr_regfile$csr_trap_actions or - WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h12175; - MUX_rg_cur_priv$write_1__SEL_1: - rg_next_pc$D_IN = csr_regfile$csr_trap_actions[193:130]; - WILL_FIRE_RL_rl_stage1_xRET: - rg_next_pc$D_IN = csr_regfile$csr_ret_actions[129:66]; - default: rg_next_pc$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_next_pc$EN = - WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_xRET ; - - // register rg_run_on_reset - assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ; - assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ; - - // register rg_sstatus_SUM - assign rg_sstatus_SUM$D_IN = - WILL_FIRE_RL_rl_stage1_interrupt && - csr_regfile$csr_trap_actions[84] ; - assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_7 ; - - // register rg_start_CPI_cycles - assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ; - assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_start_CPI_instrs - assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ; - assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ; - - // register rg_state - always@(WILL_FIRE_RL_rl_reset_complete or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_stage1_CSRR_W or - MUX_rg_state$write_1__VAL_2 or - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or - MUX_rg_state$write_1__VAL_3 or - WILL_FIRE_RL_rl_reset_from_WFI or - WILL_FIRE_RL_rl_reset_start or - MUX_rg_state$write_1__SEL_6 or - MUX_rg_state$write_1__SEL_7 or - WILL_FIRE_RL_rl_stage1_FENCE_I or - WILL_FIRE_RL_rl_stage1_FENCE or - WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_reset_complete: - rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_stage1_CSRR_W: - rg_state$D_IN = MUX_rg_state$write_1__VAL_2; - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: - rg_state$D_IN = MUX_rg_state$write_1__VAL_3; - WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1; - MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd5; - WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd7; - WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd8; - WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd10; - default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_complete || - WILL_FIRE_RL_rl_stage1_CSRR_W || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C || - WILL_FIRE_RL_rl_reset_from_WFI || - WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA || - WILL_FIRE_RL_rl_stage1_WFI ; - - // register stage1_rg_full - always@(WILL_FIRE_RL_stage1_rl_reset or - WILL_FIRE_RL_rl_pipe or - MUX_stage1_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or - WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_trap_fetch or - WILL_FIRE_RL_rl_stage1_trap or - WILL_FIRE_RL_rl_WFI_resume or - WILL_FIRE_RL_rl_finish_SFENCE_VMA or - WILL_FIRE_RL_rl_finish_FENCE or - WILL_FIRE_RL_rl_finish_FENCE_I or - WILL_FIRE_RL_rl_stage1_xRET or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_interrupt: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_trap_fetch: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_trap: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I: - stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage1_xRET: stage1_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0; - default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage1_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_stage1_rl_reset || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - - // register stage2_rg_full - always@(stage2_f_reset_reqs$EMPTY_N or - WILL_FIRE_RL_rl_pipe or - MUX_stage2_rg_full$write_1__VAL_2 or - MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_stage2_nonpipe) - case (1'b1) - stage2_f_reset_reqs$EMPTY_N: stage2_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2; - MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage2_nonpipe: - stage2_rg_full$D_IN = 1'd0; - default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage2_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_rl_stage2_nonpipe || - stage2_f_reset_reqs$EMPTY_N ; - - // register stage2_rg_resetting - assign stage2_rg_resetting$D_IN = stage2_f_reset_reqs$EMPTY_N ; - assign stage2_rg_resetting$EN = - WILL_FIRE_RL_stage2_rl_reset_end || stage2_f_reset_reqs$EMPTY_N ; - - // register stage2_rg_stage2 - assign stage2_rg_stage2$D_IN = - { rg_cur_priv, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916, - x_out_data_to_stage2_rd__h12205, - x_out_data_to_stage2_addr__h12206, - x_out_data_to_stage2_val1__h12207, - x_out_data_to_stage2_val2__h12208 } ; - assign stage2_rg_stage2$EN = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 ; - - // register stage3_rg_full - always@(WILL_FIRE_RL_stage3_rl_reset or - WILL_FIRE_RL_rl_pipe or - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 or - MUX_imem_rg_f3$write_1__SEL_1) - case (1'b1) - WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0; - WILL_FIRE_RL_rl_pipe: - stage3_rg_full$D_IN = - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2; - MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0; - default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ; - endcase - assign stage3_rg_full$EN = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe || - WILL_FIRE_RL_stage3_rl_reset ; - - // register stage3_rg_stage3 - assign stage3_rg_stage3$D_IN = - { stage2_rg_stage2[295:200], - stage2_rg_stage2[297:296], - stage2_rg_stage2[199:197] == 3'd0 || - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145, - x_out_data_to_stage3_rd__h5648, - x_out_data_to_stage3_rd_val__h5649 } ; - assign stage3_rg_stage3$EN = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd2 ; - - // submodule csr_regfile - assign csr_regfile$access_permitted_1_csr_addr = - x_out_data_to_stage2_instr__h12203[31:20] ; - assign csr_regfile$access_permitted_1_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ; - assign csr_regfile$access_permitted_2_csr_addr = - x_out_data_to_stage2_instr__h12203[31:20] ; - assign csr_regfile$access_permitted_2_priv = rg_cur_priv ; - assign csr_regfile$access_permitted_2_read_not_write = - rs1_val__h18963 == 64'd0 ; - assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ; - assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ; - always@(IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833) - begin - case (IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833) - 4'd7: csr_regfile$csr_ret_actions_from_priv = 2'b11; - 4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b01; - default: csr_regfile$csr_ret_actions_from_priv = 2'b0; - endcase - end - always@(WILL_FIRE_RL_rl_stage1_interrupt or - MUX_csr_regfile$csr_trap_actions_5__VAL_1 or - WILL_FIRE_RL_rl_stage1_trap or - x_out_trap_info_exc_code__h14097 or - WILL_FIRE_RL_rl_stage2_nonpipe or near_mem$dmem_exc_code) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_exc_code = - MUX_csr_regfile$csr_trap_actions_5__VAL_1; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h14097; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_exc_code = near_mem$dmem_exc_code; - default: csr_regfile$csr_trap_actions_exc_code = - 4'b1010 /* unspecified value */ ; - endcase - end - assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ; - assign csr_regfile$csr_trap_actions_interrupt = - WILL_FIRE_RL_rl_stage1_interrupt && !csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_nmi = - WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ; - assign csr_regfile$csr_trap_actions_pc = - WILL_FIRE_RL_rl_stage2_nonpipe ? - stage2_rg_stage2[295:232] : - imem_rg_pc ; - always@(WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_stage1_trap or - value__h14148 or WILL_FIRE_RL_rl_stage2_nonpipe or stage2_rg_stage2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage1_interrupt: - csr_regfile$csr_trap_actions_xtval = 64'd0; - WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_xtval = value__h14148; - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_xtval = stage2_rg_stage2[191:128]; - default: csr_regfile$csr_trap_actions_xtval = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ; - assign csr_regfile$m_external_interrupt_req_set_not_clear = - m_external_interrupt_req_set_not_clear ; - assign csr_regfile$mav_csr_write_csr_addr = - x_out_data_to_stage2_instr__h12203[31:20] ; - assign csr_regfile$mav_csr_write_word = - MUX_csr_regfile$mav_csr_write_1__SEL_1 ? - rs1_val__h18473 : - MUX_csr_regfile$mav_csr_write_2__VAL_2 ; - assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ; - assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign csr_regfile$read_csr_csr_addr = - x_out_data_to_stage2_instr__h12203[31:20] ; - assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ; - assign csr_regfile$s_external_interrupt_req_set_not_clear = - s_external_interrupt_req_set_not_clear ; - assign csr_regfile$software_interrupt_req_set_not_clear = - software_interrupt_req_set_not_clear ; - assign csr_regfile$timer_interrupt_req_set_not_clear = - timer_interrupt_req_set_not_clear ; - assign csr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign csr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign csr_regfile$EN_mav_read_csr = 1'b0 ; - assign csr_regfile$EN_mav_csr_write = - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h12203[19:15] != 5'd0 ; - assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_1 ; - assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ; - assign csr_regfile$EN_csr_minstret_incr = - WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd2 || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 || - WILL_FIRE_RL_rl_stage1_WFI || - WILL_FIRE_RL_rl_stage1_FENCE || - WILL_FIRE_RL_rl_stage1_FENCE_I || - WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; - assign csr_regfile$EN_debug = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = hart0_server_reset_request_put ; - assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = - gpr_regfile_RDY_server_reset_request_put__161__ETC___d1173 && - rg_state == 4'd0 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = rg_run_on_reset ; - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_1 ; - assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule gpr_regfile - assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ; - assign gpr_regfile$read_rs1_rs1 = _theResult____h4283[19:15] ; - assign gpr_regfile$read_rs2_rs2 = _theResult____h4283[24:20] ; - assign gpr_regfile$write_rd_rd = - MUX_gpr_regfile$write_rd_1__SEL_1 ? - stage3_rg_stage3[68:64] : - x_out_data_to_stage2_instr__h12203[11:7] ; - assign gpr_regfile$write_rd_rd_val = - (MUX_csr_regfile$mav_csr_write_1__SEL_1 || - MUX_gpr_regfile$write_rd_1__SEL_3) ? - csr_regfile$read_csr[63:0] : - stage3_rg_stage3[63:0] ; - assign gpr_regfile$EN_server_reset_request_put = - CAN_FIRE_RL_rl_reset_start ; - assign gpr_regfile$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_1 ; - assign gpr_regfile$EN_write_rd = - WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[69] || - WILL_FIRE_RL_rl_stage1_CSRR_W && - csr_regfile$access_permitted_1 || - WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 ; - - // submodule near_mem - assign near_mem$dmem_master_arready = dmem_master_arready ; - assign near_mem$dmem_master_awready = dmem_master_awready ; - assign near_mem$dmem_master_bid = dmem_master_bid ; - assign near_mem$dmem_master_bresp = dmem_master_bresp ; - assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; - assign near_mem$dmem_master_rdata = dmem_master_rdata ; - assign near_mem$dmem_master_rid = dmem_master_rid ; - assign near_mem$dmem_master_rlast = dmem_master_rlast ; - assign near_mem$dmem_master_rresp = dmem_master_rresp ; - assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; - assign near_mem$dmem_master_wready = dmem_master_wready ; - assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h12206 ; - assign near_mem$dmem_req_amo_funct7 = - x_out_data_to_stage2_val1__h12207[6:0] ; - assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h12203[14:12] ; - assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ; - always@(IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916) - begin - case (IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916) - 3'd1: near_mem$dmem_req_op = 2'd0; - 3'd2: near_mem$dmem_req_op = 2'd1; - default: near_mem$dmem_req_op = 2'd2; - endcase - end - assign near_mem$dmem_req_priv = - csr_regfile$read_mstatus[17] ? - csr_regfile$read_mstatus[12:11] : - rg_cur_priv ; - assign near_mem$dmem_req_satp = csr_regfile$read_satp ; - assign near_mem$dmem_req_sstatus_SUM = 1'd0 ; - assign near_mem$dmem_req_store_value = x_out_data_to_stage2_val2__h12208 ; - assign near_mem$imem_master_arready = imem_master_arready ; - assign near_mem$imem_master_awready = imem_master_awready ; - assign near_mem$imem_master_bid = imem_master_bid ; - assign near_mem$imem_master_bresp = imem_master_bresp ; - assign near_mem$imem_master_bvalid = imem_master_bvalid ; - assign near_mem$imem_master_rdata = imem_master_rdata ; - assign near_mem$imem_master_rid = imem_master_rid ; - assign near_mem$imem_master_rlast = imem_master_rlast ; - assign near_mem$imem_master_rresp = imem_master_rresp ; - assign near_mem$imem_master_rvalid = imem_master_rvalid ; - assign near_mem$imem_master_wready = imem_master_wready ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_near_mem$imem_req_2__VAL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - MUX_near_mem$imem_req_2__VAL_2 or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - next_pc___1__h14260 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_trap_fetch or - MUX_near_mem$imem_req_2__VAL_5 or MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1; - MUX_imem_rg_f3$write_1__SEL_2: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_addr = next_pc___1__h14260; - WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5; - default: near_mem$imem_req_addr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_f3 = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ; - always@(MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6 or - csr_regfile$read_mstatus or - WILL_FIRE_RL_rl_trap_fetch or - rg_mstatus_MXR or - WILL_FIRE_RL_imem_rl_fetch_next_32b or imem_rg_mstatus_MXR) - begin - case (1'b1) // synopsys parallel_case - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_mstatus_MXR = csr_regfile$read_mstatus[19]; - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_mstatus_MXR = rg_mstatus_MXR; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_mstatus_MXR = imem_rg_mstatus_MXR; - default: near_mem$imem_req_mstatus_MXR = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$imem_req_priv = - (MUX_imem_rg_f3$write_1__SEL_1 || - MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - MUX_near_mem$imem_req_1__SEL_6) ? - rg_cur_priv : - imem_rg_priv ; - assign near_mem$imem_req_satp = - WILL_FIRE_RL_imem_rl_fetch_next_32b ? - imem_rg_satp : - csr_regfile$read_satp ; - always@(WILL_FIRE_RL_rl_trap_fetch or - rg_sstatus_SUM or - WILL_FIRE_RL_imem_rl_fetch_next_32b or - imem_rg_sstatus_SUM or - MUX_imem_rg_f3$write_1__SEL_1 or - MUX_imem_rg_f3$write_1__SEL_2 or - WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - MUX_near_mem$imem_req_1__SEL_6) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_trap_fetch: - near_mem$imem_req_sstatus_SUM = rg_sstatus_SUM; - WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_sstatus_SUM = imem_rg_sstatus_SUM; - MUX_imem_rg_f3$write_1__SEL_1 || MUX_imem_rg_f3$write_1__SEL_2 || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - MUX_near_mem$imem_req_1__SEL_6: - near_mem$imem_req_sstatus_SUM = 1'd0; - default: near_mem$imem_req_sstatus_SUM = 1'b0 /* unspecified value */ ; - endcase - end - assign near_mem$server_fence_request_put = - 8'b10101010 /* unspecified value */ ; - assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ; - assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_1 ; - assign near_mem$EN_imem_req = - WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 || - WILL_FIRE_RL_imem_rl_fetch_next_32b || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx || - WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_dmem_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 && - (IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == - 3'd1 || - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == - 3'd2 || - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == - 3'd4) ; - assign near_mem$EN_server_fence_i_request_put = - MUX_rg_state$write_1__SEL_8 ; - assign near_mem$EN_server_fence_i_response_get = - CAN_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_9 ; - assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ; - assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_10 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule stage1_f_reset_reqs - assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage1_f_reset_rsps - assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ; - assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage1_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_f_reset_reqs - assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage2_f_reset_reqs$DEQ = stage2_f_reset_reqs$EMPTY_N ; - assign stage2_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage2_f_reset_rsps - assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ; - assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage2_f_reset_rsps$CLR = 1'b0 ; - - // submodule stage2_mbox - assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h12203[14:12] ; - assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4283[3] ; - assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h12207 ; - assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h12208 ; - assign stage2_mbox$set_verbosity_verbosity = 4'h0 ; - assign stage2_mbox$EN_set_verbosity = 1'b0 ; - assign stage2_mbox$EN_req_reset = 1'b0 ; - assign stage2_mbox$EN_rsp_reset = 1'b0 ; - assign stage2_mbox$EN_req = - WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == - 3'd3 ; - - // submodule stage3_f_reset_reqs - assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ; - assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_reqs$CLR = 1'b0 ; - - // submodule stage3_f_reset_rsps - assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ; - assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_1 ; - assign stage3_f_reset_rsps$CLR = 1'b0 ; - - // remaining internal signals - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1064 = - ((_theResult____h4283[6:0] == 7'b0010011 || - _theResult____h4283[6:0] == 7'b0110011) && - (_theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b101)) ? - alu_outputs___1_val1__h12492 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1065 = - ((_theResult____h4283[6:0] == 7'b0110011 || - _theResult____h4283[6:0] == 7'b0111011) && - _theResult____h4283[31:25] == 7'b0000001) ? - rs1_val_bypassed__h4291 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1064 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1209 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558 = - rs1_val_bypassed__h4291 == rs2_val__h12304 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560 = - (rs1_val_bypassed__h4291 ^ 64'h8000000000000000) < - (rs2_val__h12304 ^ 64'h8000000000000000) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562 = - rs1_val_bypassed__h4291 < rs2_val__h12304 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 = - (_theResult____h4283[6:0] == 7'b1100011) ? - _theResult____h4283[14:12] != 3'b0 && - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b100 && - _theResult____h4283[14:12] != 3'b101 && - _theResult____h4283[14:12] != 3'b110 && - _theResult____h4283[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 : - _theResult____h4283[6:0] == 7'b1101111 || - _theResult____h4283[6:0] == 7'b1100111 || - (_theResult____h4283[6:0] != 7'b0110011 || - _theResult____h4283[31:25] != 7'b0000001) && - (_theResult____h4283[6:0] != 7'b0111011 || - _theResult____h4283[31:25] != 7'b0000001) && - (_theResult____h4283[6:0] != 7'b0010011 && - _theResult____h4283[6:0] != 7'b0110011 || - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b101) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700 = - (_theResult____h4283[6:0] == 7'b1100011) ? - _theResult____h4283[14:12] != 3'b0 && - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b100 && - _theResult____h4283[14:12] != 3'b101 && - _theResult____h4283[14:12] != 3'b110 && - _theResult____h4283[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 : - _theResult____h4283[6:0] != 7'b1101111 && - _theResult____h4283[6:0] != 7'b1100111 ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 = - (_theResult____h4283[6:0] == 7'b1100011) ? - (_theResult____h4283[14:12] == 3'b0 || - _theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b100 || - _theResult____h4283[14:12] == 3'b101 || - _theResult____h4283[14:12] == 3'b110 || - _theResult____h4283[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 : - _theResult____h4283[6:0] != 7'b1101111 && - _theResult____h4283[6:0] != 7'b1100111 && - (IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d717 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762) ; - assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767 = - (_theResult____h4283[6:0] == 7'b1100011) ? - (_theResult____h4283[14:12] == 3'b0 || - _theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b100 || - _theResult____h4283[14:12] == 3'b101 || - _theResult____h4283[14:12] == 3'b110 || - _theResult____h4283[14:12] == 3'b111) && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 : - _theResult____h4283[6:0] == 7'b1101111 || - _theResult____h4283[6:0] == 7'b1100111 ; - assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d774 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d605 ? - 4'd11 : - 4'd0 ; - assign IF_NOT_near_mem_dmem_valid__13_32_OR_NOT_near__ETC___d179 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - IF_stage2_rg_stage2_2_BITS_196_TO_192_52_EQ_0__ETC___d178 : - 2'd0 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d717 = - _theResult____h4283[6:0] == 7'b0110011 && - _theResult____h4283[31:25] == 7'b0000001 || - _theResult____h4283[6:0] == 7'b0111011 && - _theResult____h4283[31:25] == 7'b0000001 || - (_theResult____h4283[6:0] == 7'b0010011 || - _theResult____h4283[6:0] == 7'b0110011) && - (_theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b101) ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d724 = - _theResult____h4283[14:12] == 3'b0 && - (_theResult____h4283[6:0] != 7'b0110011 || - !_theResult____h4283[30]) || - _theResult____h4283[14:12] == 3'b0 && - _theResult____h4283[6:0] == 7'b0110011 && - _theResult____h4283[30] || - _theResult____h4283[14:12] == 3'b010 || - _theResult____h4283[14:12] == 3'b011 || - _theResult____h4283[14:12] == 3'b100 || - _theResult____h4283[14:12] == 3'b110 || - _theResult____h4283[14:12] == 3'b111 ; - assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d962 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d208 ? - next_pc___1__h14260 : - next_pc__h14258 ; - assign IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d1398 = - imem_rg_pc == csr_regfile$csr_trap_actions[193:130] ; - assign IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 = - near_mem$imem_exc ? - 4'd11 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d831 ; - assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1348 = - csr_regfile$read_csr[63:0] | rs1_val__h18963 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d466 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b0 && - instr__h4281[15:13] == 3'b011) ? - instr__h11795 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b0 && - instr__h4281[15:13] == 3'b111) ? - instr__h11946 : - 32'h0) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d467 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:13] == 3'b111) ? - instr__h11596 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d466 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d469 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:12] == 4'b1001 && - instr__h4281[11:7] == 5'd0 && - instr__h4281[6:2] == 5'd0) ? - instr__h11347 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[11:7] != 5'd0 && - instr__h4281[15:13] == 3'b011) ? - instr__h11443 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d467) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d471 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100111 && - instr__h4281[6:5] == 2'b01) ? - instr__h11051 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100111 && - instr__h4281[6:5] == 2'b0) ? - instr__h11189 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d469) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d473 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100011 && - instr__h4281[6:5] == 2'b01) ? - instr__h10777 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100011 && - instr__h4281[6:5] == 2'b0) ? - instr__h10913 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d471) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d475 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100011 && - instr__h4281[6:5] == 2'b11) ? - instr__h10505 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:10] == 6'b100011 && - instr__h4281[6:5] == 2'b10) ? - instr__h10641 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d473) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d476 = - (csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d308 && - instr__h4281[6:2] != 5'd0) ? - instr__h10410 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d475 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d477 = - (csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d302 && - instr__h4281[6:2] != 5'd0) ? - instr__h10291 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d476 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d479 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b100 && - instr__h4281[11:10] == 2'b01 && - imm6__h8404 != 6'd0) ? - instr__h9996 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b100 && - instr__h4281[11:10] == 2'b10) ? - instr__h10113 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d477) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d480 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b100 && - instr__h4281[11:10] == 2'b0 && - imm6__h8404 != 6'd0) ? - instr__h9807 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d479 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d481 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:13] == 3'b0 && - instr__h4281[11:7] != 5'd0 && - imm6__h8404 != 6'd0) ? - instr__h9618 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d480 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d483 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b011 && - instr__h4281[11:7] == 5'd2 && - nzimm10__h9073 != 10'd0) ? - instr__h9277 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b0 && - instr__h4281[15:13] == 3'b0 && - nzimm10__h9288 != 10'd0) ? - instr__h9449 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d481) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d485 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b0 && - instr__h4281[11:7] != 5'd0 && - imm6__h8404 != 6'd0 || - csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b0 && - instr__h4281[11:7] == 5'd0 && - imm6__h8404 == 6'd0) ? - instr__h8795 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b001 && - instr__h4281[11:7] != 5'd0) ? - instr__h9022 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d483) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d486 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b011 && - instr__h4281[11:7] != 5'd0 && - instr__h4281[11:7] != 5'd2 && - imm6__h8404 != 6'd0) ? - instr__h8666 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d485 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d488 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b111) ? - instr__h8144 : - ((csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b010 && - instr__h4281[11:7] != 5'd0) ? - instr__h8482 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d486) ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d489 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b110) ? - instr__h7827 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d488 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d490 = - (csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d308 && - instr__h4281[6:2] == 5'd0) ? - instr__h7762 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d489 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d491 = - (csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d302 && - instr__h4281[6:2] == 5'd0) ? - instr__h7646 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d490 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d492 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b01 && - instr__h4281[15:13] == 3'b101) ? - instr__h7192 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d491 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d493 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b0 && - instr__h4281[15:13] == 3'b110) ? - instr__h6963 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d492 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d494 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b0 && - instr__h4281[15:13] == 3'b010) ? - instr__h6768 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d493 ; - assign IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d495 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:13] == 3'b110) ? - instr__h6576 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d494 ; - assign IF_near_mem_dmem_valid__13_THEN_IF_near_mem_dm_ETC___d116 = - near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ; - assign IF_rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_E_ETC___d809 = - ((rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) && - _theResult____h4283[31:20] == 12'b000100000010) ? - 4'd8 : - (rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_EQ_0_ETC___d807 ? - 4'd10 : - 4'd11) ; - assign IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q1 : - 2'd0 ; - assign IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 = - stage2_rg_full ? - CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2 : - 2'd0 ; - assign IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499 = - x_out_bypass_rd__h5999 == _theResult____h4283[19:15] ; - assign IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501 = - x_out_bypass_rd__h5999 == _theResult____h4283[24:20] ; - assign IF_stage2_rg_stage2_2_BITS_196_TO_192_52_EQ_0__ETC___d178 = - (stage2_rg_stage2[196:192] == 5'd0) ? - 2'd0 : - ((near_mem$dmem_valid && !near_mem$dmem_exc) ? 2'd2 : 2'd1) ; - assign IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119 = - stage2_mbox$valid ? 2'd2 : 2'd1 ; - assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d605 = - (_theResult____h4283[14:12] != 3'b0 || - _theResult____h4283[6:0] == 7'b0110011 && - _theResult____h4283[30]) && - (_theResult____h4283[14:12] != 3'b0 || - _theResult____h4283[6:0] != 7'b0110011 || - !_theResult____h4283[30]) && - _theResult____h4283[14:12] != 3'b010 && - _theResult____h4283[14:12] != 3'b011 && - _theResult____h4283[14:12] != 3'b100 && - _theResult____h4283[14:12] != 3'b110 && - _theResult____h4283[14:12] != 3'b111 ; - assign NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 = - cur_verbosity__h2988 > 4'd1 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - (!stage1_rg_full || - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1238) && - (!stage1_rg_full || - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1230) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1259 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1259 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd2 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd0) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1259 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd2 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd0) && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770 || - !stage1_rg_full ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1291 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__20_OR_IF_IF_NOT_n_ETC___d1289) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770 ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1293 = - (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - _0_OR_0_OR_near_mem_imem_exc__20_OR_IF_IF_NOT_n_ETC___d1289) && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd2 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd0) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1296 = - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1293 && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770 || - !stage1_rg_full) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1310 = - !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) ; - assign NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d899 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd0 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd1 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd2 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd3 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd4 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd5 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd6 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd7 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd8 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd9 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd10 ; - assign NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d940 = - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 != - 3'd0 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 != - 3'd1 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 != - 3'd2 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 != - 3'd3 ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d208 = - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] != 2'b11) ; - assign NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d213 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d208 && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] == 2'b11) && - (!near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] != 2'b0 || - near_mem$imem_instr[1:0] == 2'b11) ; - assign NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1219 = - !near_mem$imem_valid || - !near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == - 2'd1 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501) ; - assign NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1230 = - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504 || - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) ; - assign NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1238 = - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700 ; - assign NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504 = - !near_mem$imem_valid || - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d213 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == - 2'd1 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501) ; - assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d971 = - { {52{theResult__283_BITS_31_TO_20__q19[11]}}, - theResult__283_BITS_31_TO_20__q19 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292 = - { {9{offset__h7139[11]}}, offset__h7139 } ; - assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317 = - { {4{offset__h7771[8]}}, offset__h7771 } ; - assign _0_OR_0_OR_near_mem_imem_exc__20_OR_IF_IF_NOT_n_ETC___d1289 = - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700 ; - assign _theResult_____1_fst__h13375 = - (_theResult____h4283[14:12] == 3'b0 && - _theResult____h4283[6:0] == 7'b0110011 && - _theResult____h4283[30]) ? - rd_val___1__h13371 : - _theResult_____1_fst__h13382 ; - assign _theResult_____1_fst__h13410 = - rs1_val_bypassed__h4291 & _theResult___snd__h14727 ; - assign _theResult____h23527 = - (delta_CPI_instrs__h23526 == 64'd0) ? - delta_CPI_instrs___1__h23562 : - delta_CPI_instrs__h23526 ; - assign _theResult____h4283 = - NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_ETC___d208 ? - instr___1__h6160 : - instr__h4281 ; - assign _theResult___fst__h13487 = - (_theResult____h4283[14:12] == 3'b001 && - !_theResult____h4283[25]) ? - rd_val___1__h14787 : - _theResult___fst__h13494 ; - assign _theResult___fst__h13494 = - _theResult____h4283[30] ? - rd_val___1__h14870 : - rd_val___1__h14841 ; - assign _theResult___fst__h13601 = - { {32{rs1_val_bypassed291_BITS_31_TO_0_SRL_rs2_val23_ETC__q9[31]}}, - rs1_val_bypassed291_BITS_31_TO_0_SRL_rs2_val23_ETC__q9 } ; - assign _theResult___fst__h6331 = - (near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11) ? - instr_out___1__h6333 : - _theResult___fst__h6359 ; - assign _theResult___fst__h6359 = - (near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11) ? - instr_out___1__h6361 : - near_mem$imem_instr ; - assign _theResult___snd__h14727 = - (_theResult____h4283[6:0] == 7'b0010011) ? - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d971 : - rs2_val__h12304 ; - assign alu_outputs___1_addr2629_BITS_31_TO_0__q20 = - alu_outputs___1_addr__h12629[31:0] ; - assign alu_outputs___1_addr__h12330 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 ? - branch_target__h12308 : - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d962 ; - assign alu_outputs___1_addr__h12351 = - imem_rg_pc + - { {43{theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q4[20]}}, - theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q4 } ; - assign alu_outputs___1_addr__h12377 = - { alu_outputs___1_addr__h12629[63:1], 1'd0 } ; - assign alu_outputs___1_addr__h12629 = - rs1_val_bypassed__h4291 + - SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d971 ; - assign alu_outputs___1_addr__h12650 = - rs1_val_bypassed__h4291 + - { {52{theResult__283_BITS_31_TO_25_CONCAT_theResult__ETC__q7[11]}}, - theResult__283_BITS_31_TO_25_CONCAT_theResult__ETC__q7 } ; - assign alu_outputs___1_exc_code__h12886 = - (_theResult____h4283[14:12] == 3'b0) ? - ((_theResult____h4283[11:7] == 5'd0 && - _theResult____h4283[19:15] == 5'd0) ? - CASE_theResult__283_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 : - 4'd2) : - 4'd2 ; - assign alu_outputs___1_val1__h12492 = - (_theResult____h4283[14:12] == 3'b001) ? - rd_val__h14623 : - (_theResult____h4283[30] ? rd_val__h14697 : rd_val__h14675) ; - assign alu_outputs___1_val1__h12530 = - (_theResult____h4283[14:12] == 3'b0 && - (_theResult____h4283[6:0] != 7'b0110011 || - !_theResult____h4283[30])) ? - rd_val___1__h13363 : - _theResult_____1_fst__h13375 ; - assign alu_outputs___1_val1__h12553 = - (_theResult____h4283[14:12] == 3'b0) ? - rd_val___1__h14756 : - _theResult___fst__h13487 ; - assign alu_outputs___1_val1__h12592 = - { {32{v32__h12581[31]}}, v32__h12581 } ; - assign alu_outputs___1_val1__h12608 = - imem_rg_pc + alu_outputs___1_val1__h12592 ; - assign alu_outputs___1_val1__h12890 = - _theResult____h4283[14] ? - { 59'd0, _theResult____h4283[19:15] } : - rs1_val_bypassed__h4291 ; - assign alu_outputs___1_val1__h12911 = - { 57'd0, _theResult____h4283[31:25] } ; - assign branch_target__h12308 = - imem_rg_pc + - { {51{theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q3[12]}}, - theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q3 } ; - assign cpi__h23529 = x__h23528 / 64'd10 ; - assign cpifrac__h23530 = x__h23528 % 64'd10 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1212 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1208 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1209 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1217 = - (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd2 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd0 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1223 = - csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1212 || - (csr_regfile_interrupt_pending_rg_cur_priv_3_20_ETC___d1217 || - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1219 || - near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - stage1_rg_full ; - assign csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1401 = - delta_CPI_cycles__h23525 * 64'd10 ; - assign csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d302 = - csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:12] == 4'b1000 && - instr__h4281[11:7] != 5'd0 ; - assign csr_regfile_read_misa__0_BIT_2_15_AND_IF_near__ETC___d308 = - csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[15:12] == 4'b1001 && - instr__h4281[11:7] != 5'd0 ; - assign cur_verbosity__h2988 = - (csr_regfile$read_csr_minstret < cfg_logdelay) ? - 4'd0 : - cfg_verbosity ; - assign data_to_stage2_addr__h12198 = x_out_data_to_stage2_addr__h12206 ; - assign delta_CPI_cycles__h23525 = - csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ; - assign delta_CPI_instrs___1__h23562 = delta_CPI_instrs__h23526 + 64'd1 ; - assign delta_CPI_instrs__h23526 = - csr_regfile$read_csr_minstret - rg_start_CPI_instrs ; - assign fall_through_pc__h12162 = - imem_rg_pc + - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d511 ? - 64'd4 : - 64'd2) ; - assign funct10__h12562 = - { _theResult____h4283[31:25], _theResult____h4283[14:12] } ; - assign gpr_regfile_RDY_server_reset_request_put__161__ETC___d1173 = - gpr_regfile$RDY_server_reset_request_put && - near_mem$RDY_server_reset_request_put && - csr_regfile$RDY_server_reset_request_put && - f_reset_reqs$EMPTY_N && - stage1_f_reset_reqs$FULL_N && - stage2_f_reset_reqs$FULL_N && - stage3_f_reset_reqs$FULL_N ; - assign imm12__h11444 = { 3'd0, offset__h11358 } ; - assign imm12__h11796 = { 4'd0, offset__h11730 } ; - assign imm12__h6432 = { 4'd0, offset__h6202 } ; - assign imm12__h6769 = { 5'd0, offset__h6711 } ; - assign imm12__h8406 = { {6{imm6__h8404[5]}}, imm6__h8404 } ; - assign imm12__h9075 = { {2{nzimm10__h9073[9]}}, nzimm10__h9073 } ; - assign imm12__h9290 = { 2'd0, nzimm10__h9288 } ; - assign imm12__h9486 = { 6'b0, imm6__h8404 } ; - assign imm12__h9823 = { 6'b010000, imm6__h8404 } ; - assign imm20__h8534 = { {14{imm6__h8404[5]}}, imm6__h8404 } ; - assign imm6__h8404 = { instr__h4281[12], instr__h4281[6:2] } ; - assign instr___1__h6160 = - (csr_regfile$read_misa[2] && instr__h4281[1:0] == 2'b10 && - instr__h4281[11:7] != 5'd0 && - instr__h4281[15:13] == 3'b010) ? - instr__h6431 : - IF_csr_regfile_read_misa__0_BIT_2_15_AND_IF_ne_ETC___d495 ; - assign instr__h10113 = - { imm12__h8406, rs1__h6770, 3'b111, rs1__h6770, 7'b0010011 } ; - assign instr__h10291 = - { 7'b0, - instr__h4281[6:2], - 8'd0, - instr__h4281[11:7], - 7'b0110011 } ; - assign instr__h10410 = - { 7'b0, - instr__h4281[6:2], - instr__h4281[11:7], - 3'b0, - instr__h4281[11:7], - 7'b0110011 } ; - assign instr__h10505 = - { 7'b0, rd__h6771, rs1__h6770, 3'b111, rs1__h6770, 7'b0110011 } ; - assign instr__h10641 = - { 7'b0, rd__h6771, rs1__h6770, 3'b110, rs1__h6770, 7'b0110011 } ; - assign instr__h10777 = - { 7'b0, rd__h6771, rs1__h6770, 3'b100, rs1__h6770, 7'b0110011 } ; - assign instr__h10913 = - { 7'b0100000, - rd__h6771, - rs1__h6770, - 3'b0, - rs1__h6770, - 7'b0110011 } ; - assign instr__h11051 = - { 7'b0, rd__h6771, rs1__h6770, 3'b0, rs1__h6770, 7'b0111011 } ; - assign instr__h11189 = - { 7'b0100000, - rd__h6771, - rs1__h6770, - 3'b0, - rs1__h6770, - 7'b0111011 } ; - assign instr__h11347 = - { 12'b000000000001, - instr__h4281[11:7], - 3'b0, - instr__h4281[11:7], - 7'b1110011 } ; - assign instr__h11443 = - { imm12__h11444, 8'd19, instr__h4281[11:7], 7'b0000011 } ; - assign instr__h11596 = - { 3'd0, - instr__h4281[9:7], - instr__h4281[12], - instr__h4281[6:2], - 8'd19, - offset_BITS_4_TO_0___h12071, - 7'b0100011 } ; - assign instr__h11795 = - { imm12__h11796, rs1__h6770, 3'b011, rd__h6771, 7'b0000011 } ; - assign instr__h11946 = - { 4'd0, - instr__h4281[6:5], - instr__h4281[12], - rd__h6771, - rs1__h6770, - 3'b011, - offset_BITS_4_TO_0___h12071, - 7'b0100011 } ; - assign instr__h4281 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 ? - instr_out___1__h6301 : - _theResult___fst__h6331 ; - assign instr__h6431 = - { imm12__h6432, 8'd18, instr__h4281[11:7], 7'b0000011 } ; - assign instr__h6576 = - { 4'd0, - instr__h4281[8:7], - instr__h4281[12], - instr__h4281[6:2], - 8'd18, - offset_BITS_4_TO_0___h6700, - 7'b0100011 } ; - assign instr__h6768 = - { imm12__h6769, rs1__h6770, 3'b010, rd__h6771, 7'b0000011 } ; - assign instr__h6963 = - { 5'd0, - instr__h4281[5], - instr__h4281[12], - rd__h6771, - rs1__h6770, - 3'b010, - offset_BITS_4_TO_0___h7131, - 7'b0100011 } ; - assign instr__h7192 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292[20], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292[10:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292[11], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d292[19:12], - 12'd111 } ; - assign instr__h7646 = { 12'd0, instr__h4281[11:7], 15'd103 } ; - assign instr__h7762 = { 12'd0, instr__h4281[11:7], 15'd231 } ; - assign instr__h7827 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[10:5], - 5'd0, - rs1__h6770, - 3'b0, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[11], - 7'b1100011 } ; - assign instr__h8144 = - { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[12], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[10:5], - 5'd0, - rs1__h6770, - 3'b001, - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[4:1], - SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d317[11], - 7'b1100011 } ; - assign instr__h8482 = - { imm12__h8406, 8'd0, instr__h4281[11:7], 7'b0010011 } ; - assign instr__h8666 = { imm20__h8534, instr__h4281[11:7], 7'b0110111 } ; - assign instr__h8795 = - { imm12__h8406, - instr__h4281[11:7], - 3'b0, - instr__h4281[11:7], - 7'b0010011 } ; - assign instr__h9022 = - { imm12__h8406, - instr__h4281[11:7], - 3'b0, - instr__h4281[11:7], - 7'b0011011 } ; - assign instr__h9277 = - { imm12__h9075, - instr__h4281[11:7], - 3'b0, - instr__h4281[11:7], - 7'b0010011 } ; - assign instr__h9449 = { imm12__h9290, 8'd16, rd__h6771, 7'b0010011 } ; - assign instr__h9618 = - { imm12__h9486, - instr__h4281[11:7], - 3'b001, - instr__h4281[11:7], - 7'b0010011 } ; - assign instr__h9807 = - { imm12__h9486, rs1__h6770, 3'b101, rs1__h6770, 7'b0010011 } ; - assign instr__h9996 = - { imm12__h9823, rs1__h6770, 3'b101, rs1__h6770, 7'b0010011 } ; - assign instr_out___1__h6301 = - { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ; - assign instr_out___1__h6333 = { 16'b0, near_mem$imem_instr[15:0] } ; - assign instr_out___1__h6361 = { 16'b0, near_mem$imem_instr[31:16] } ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1076 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd0 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1079 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd1 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1082 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd2 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1085 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd3 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1088 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd4 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1091 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd5 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1094 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd6 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1097 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd7 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1100 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd8 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1103 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd9 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1106 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == - 4'd10 ; - assign near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1109 = - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd0 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd1 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd2 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd3 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd4 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd5 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd6 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd7 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd8 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd9 && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 != - 4'd10 ; - assign near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 = - near_mem$imem_pc[63:2] == imem_rg_pc[63:2] ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d511 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] == 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d513 = - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d511 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] != 2'b0 && - near_mem$imem_instr[17:16] != 2'b11 || - near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && - imem_rg_pc[1:0] == 2'b0 && - near_mem$imem_instr[1:0] != 2'b11 ; - assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 = - near_mem$imem_pc == next_pc___1__h14260 ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1208 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d200 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 != - 2'd1 || - !IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499 && - !IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 = - near_mem$imem_valid && - near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d513 && - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 != - 2'd1 || - !IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499 && - !IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - (near_mem$imem_exc || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d689 && - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d700) ; - assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770 = - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) ; - assign next_pc___1__h14260 = imem_rg_pc + 64'd2 ; - assign next_pc__h14258 = imem_rg_pc + 64'd4 ; - assign nzimm10__h9073 = - { instr__h4281[12], - instr__h4281[4:3], - instr__h4281[5], - instr__h4281[2], - instr__h4281[6], - 4'b0 } ; - assign nzimm10__h9288 = - { instr__h4281[10:7], - instr__h4281[12:11], - instr__h4281[5], - instr__h4281[6], - 2'b0 } ; - assign offset_BITS_4_TO_0___h12071 = { instr__h4281[11:10], 3'b0 } ; - assign offset_BITS_4_TO_0___h6700 = { instr__h4281[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h7131 = - { instr__h4281[11:10], instr__h4281[6], 2'b0 } ; - assign offset__h11358 = - { instr__h4281[4:2], - instr__h4281[12], - instr__h4281[6:5], - 3'b0 } ; - assign offset__h11730 = { instr__h4281[6:5], instr__h4281[12:10], 3'b0 } ; - assign offset__h6202 = - { instr__h4281[3:2], - instr__h4281[12], - instr__h4281[6:4], - 2'b0 } ; - assign offset__h6711 = - { instr__h4281[5], instr__h4281[12:10], instr__h4281[6], 2'b0 } ; - assign offset__h7139 = - { instr__h4281[12], - instr__h4281[8], - instr__h4281[10:9], - instr__h4281[6], - instr__h4281[7], - instr__h4281[2], - instr__h4281[11], - instr__h4281[5:3], - 1'b0 } ; - assign offset__h7771 = - { instr__h4281[12], - instr__h4281[6:5], - instr__h4281[2], - instr__h4281[11:10], - instr__h4281[4:3], - 1'b0 } ; - assign output_stage2___1_bypass_rd_val__h5988 = - (!near_mem$dmem_valid || !near_mem$dmem_exc) ? - ((stage2_rg_stage2[196:192] == 5'd0) ? - stage2_rg_stage2[127:64] : - near_mem$dmem_word64) : - stage2_rg_stage2[127:64] ; - assign rd__h6771 = { 2'b01, instr__h4281[4:2] } ; - assign rd_val___1__h13363 = - rs1_val_bypassed__h4291 + _theResult___snd__h14727 ; - assign rd_val___1__h13371 = - rs1_val_bypassed__h4291 - _theResult___snd__h14727 ; - assign rd_val___1__h13378 = - ((rs1_val_bypassed__h4291 ^ 64'h8000000000000000) < - (_theResult___snd__h14727 ^ 64'h8000000000000000)) ? - 64'd1 : - 64'd0 ; - assign rd_val___1__h13385 = - (rs1_val_bypassed__h4291 < _theResult___snd__h14727) ? - 64'd1 : - 64'd0 ; - assign rd_val___1__h13392 = - rs1_val_bypassed__h4291 ^ _theResult___snd__h14727 ; - assign rd_val___1__h13399 = - rs1_val_bypassed__h4291 | _theResult___snd__h14727 ; - assign rd_val___1__h14756 = - { {32{alu_outputs___1_addr2629_BITS_31_TO_0__q20[31]}}, - alu_outputs___1_addr2629_BITS_31_TO_0__q20 } ; - assign rd_val___1__h14787 = { {32{x__h14790[31]}}, x__h14790 } ; - assign rd_val___1__h14841 = { {32{x__h14844[31]}}, x__h14844 } ; - assign rd_val___1__h14870 = { {32{tmp__h14869[31]}}, tmp__h14869 } ; - assign rd_val___1__h14922 = - { {32{rs1_val_bypassed291_BITS_31_TO_0_PLUS_rs2_val2_ETC__q10[31]}}, - rs1_val_bypassed291_BITS_31_TO_0_PLUS_rs2_val2_ETC__q10 } ; - assign rd_val___1__h14970 = - { {32{rs1_val_bypassed291_BITS_31_TO_0_MINUS_rs2_val_ETC__q11[31]}}, - rs1_val_bypassed291_BITS_31_TO_0_MINUS_rs2_val_ETC__q11 } ; - assign rd_val___1__h14976 = { {32{x__h14979[31]}}, x__h14979 } ; - assign rd_val___1__h15021 = { {32{x__h15024[31]}}, x__h15024 } ; - assign rd_val__h12119 = - (stage3_rg_full && stage3_rg_stage3[69] && - stage3_rg_stage3[68:64] == _theResult____h4283[24:20]) ? - stage3_rg_stage3[63:0] : - gpr_regfile$read_rs2 ; - assign rd_val__h14623 = rs1_val_bypassed__h4291 << shamt__h12477 ; - assign rd_val__h14675 = rs1_val_bypassed__h4291 >> shamt__h12477 ; - assign rd_val__h14697 = - rs1_val_bypassed__h4291 >> shamt__h12477 | - ~(64'hFFFFFFFFFFFFFFFF >> shamt__h12477) & - {64{rs1_val_bypassed__h4291[63]}} ; - assign rd_val__h6112 = - (stage3_rg_full && stage3_rg_stage3[69] && - stage3_rg_stage3[68:64] == _theResult____h4283[19:15]) ? - stage3_rg_stage3[63:0] : - gpr_regfile$read_rs1 ; - assign rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_EQ_0_ETC___d807 = - (rg_cur_priv == 2'b11 || - rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] || - rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) && - _theResult____h4283[31:20] == 12'b000100000101 ; - assign rg_state_2_EQ_3_225_AND_NOT_csr_regfile_interr_ETC___d1313 = - rg_state == 4'd3 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1310 && - !stage3_rg_full && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == - 2'd0 ; - assign rg_state_2_EQ_3_225_AND_stage3_rg_full_2_OR_NO_ETC___d1244 = - rg_state == 4'd3 && - (stage3_rg_full || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd0 || - stage1_rg_full) && - (stage3_rg_full || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd3) && - (stage3_rg_full || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd0 || - !stage1_rg_full || - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d1230) && - (NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 || - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != - 2'd0 || - stage3_rg_full) ; - assign rs1__h6770 = { 2'b01, instr__h4281[9:7] } ; - assign rs1_val__h18473 = - (x_out_data_to_stage2_instr__h12203[14:12] == 3'b001) ? - x_out_data_to_stage2_val1__h12207 : - { 59'd0, x_out_data_to_stage2_instr__h12203[19:15] } ; - assign rs1_val_bypassed291_BITS_31_TO_0_MINUS_rs2_val_ETC__q11 = - rs1_val_bypassed__h4291[31:0] - rs2_val__h12304[31:0] ; - assign rs1_val_bypassed291_BITS_31_TO_0_PLUS_rs2_val2_ETC__q10 = - rs1_val_bypassed__h4291[31:0] + rs2_val__h12304[31:0] ; - assign rs1_val_bypassed291_BITS_31_TO_0_SRL_rs2_val23_ETC__q9 = - rs1_val_bypassed__h4291[31:0] >> rs2_val__h12304[4:0] | - ~(32'hFFFFFFFF >> rs2_val__h12304[4:0]) & - {32{rs1_val_bypassed291_BITS_31_TO_0__q8[31]}} ; - assign rs1_val_bypassed291_BITS_31_TO_0__q8 = - rs1_val_bypassed__h4291[31:0] ; - assign rs1_val_bypassed__h4291 = - (_theResult____h4283[19:15] == 5'd0) ? 64'd0 : val__h6114 ; - assign rs2_val__h12304 = - (_theResult____h4283[24:20] == 5'd0) ? 64'd0 : val__h12121 ; - assign shamt__h12477 = - (_theResult____h4283[6:0] == 7'b0010011) ? - _theResult____h4283[25:20] : - rs2_val__h12304[5:0] ; - assign stage2_f_reset_rsps_i_notEmpty__182_AND_stage3_ETC___d1191 = - stage2_f_reset_rsps$EMPTY_N && stage3_f_reset_rsps$EMPTY_N && - f_reset_rsps$FULL_N && - (!rg_run_on_reset || - !near_mem_imem_pc_BITS_63_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) ; - assign sxl__h4705 = - (csr_regfile$read_misa[27:26] == 2'd2) ? - csr_regfile$read_mstatus[35:34] : - 2'd0 ; - assign theResult__283_BITS_31_TO_20__q19 = _theResult____h4283[31:20] ; - assign theResult__283_BITS_31_TO_25_CONCAT_theResult__ETC__q7 = - { _theResult____h4283[31:25], _theResult____h4283[11:7] } ; - assign theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q3 = - { _theResult____h4283[31], - _theResult____h4283[7], - _theResult____h4283[30:25], - _theResult____h4283[11:8], - 1'b0 } ; - assign theResult__283_BIT_31_CONCAT_theResult__283_BI_ETC__q4 = - { _theResult____h4283[31], - _theResult____h4283[19:12], - _theResult____h4283[20], - _theResult____h4283[30:21], - 1'b0 } ; - assign tmp__h14869 = - rs1_val_bypassed__h4291[31:0] >> _theResult____h4283[24:20] | - ~(32'hFFFFFFFF >> _theResult____h4283[24:20]) & - {32{rs1_val_bypassed291_BITS_31_TO_0__q8[31]}} ; - assign trap_info_tval__h14094 = - (_theResult____h4283[6:0] != 7'b1101111 && - _theResult____h4283[6:0] != 7'b1100111 && - (_theResult____h4283[6:0] != 7'b1110011 || - _theResult____h4283[14:12] != 3'b0 || - _theResult____h4283[11:7] != 5'd0 || - _theResult____h4283[19:15] != 5'd0 || - _theResult____h4283[31:20] != 12'b0 && - _theResult____h4283[31:20] != 12'b000000000001)) ? - (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_00_OR__ETC___d511 ? - { 32'd0, _theResult____h4283 } : - { 48'd0, instr__h4281[15:0] }) : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1151 ; - assign uxl__h4706 = - (csr_regfile$read_misa[27:26] == 2'd2) ? - csr_regfile$read_mstatus[33:32] : - 2'd0 ; - assign v32__h12581 = { _theResult____h4283[31:12], 12'h0 } ; - assign val__h12121 = - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == - 2'd2 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d501) ? - x_out_bypass_rd_val__h6000 : - rd_val__h12119 ; - assign val__h6114 = - (IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == - 2'd2 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d499) ? - x_out_bypass_rd_val__h6000 : - rd_val__h6112 ; - assign value__h14148 = - near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h14094 ; - assign x__h14790 = - rs1_val_bypassed__h4291[31:0] << _theResult____h4283[24:20] ; - assign x__h14844 = - rs1_val_bypassed__h4291[31:0] >> _theResult____h4283[24:20] ; - assign x__h14979 = rs1_val_bypassed__h4291[31:0] << rs2_val__h12304[4:0] ; - assign x__h15024 = rs1_val_bypassed__h4291[31:0] >> rs2_val__h12304[4:0] ; - assign x__h23528 = - csr_regfile_read_csr_mcycle__2_MINUS_rg_start__ETC___d1401[63:0] / - _theResult____h23527 ; - assign x_out_data_to_stage2_instr__h12203 = _theResult____h4283 ; - assign x_out_data_to_stage2_rd__h12205 = - (_theResult____h4283[6:0] == 7'b1100011) ? - 5'd0 : - _theResult____h4283[11:7] ; - assign x_out_data_to_stage2_val2__h12208 = - (_theResult____h4283[6:0] == 7'b1100011) ? - branch_target__h12308 : - rs2_val__h12304 ; - assign x_out_next_pc__h12175 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767 ? - data_to_stage2_addr__h12198 : - fall_through_pc__h12162 ; - assign x_out_trap_info_exc_code__h14097 = - near_mem$imem_exc ? - near_mem$imem_exc_code : - alu_outputs_exc_code__h12932 ; - assign y__h19264 = ~rs1_val__h18963 ; - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[199:197]) - 3'd0, 3'd1, 3'd4: - x_out_data_to_stage3_rd__h5648 = stage2_rg_stage2[196:192]; - 3'd2: x_out_data_to_stage3_rd__h5648 = 5'd0; - default: x_out_data_to_stage3_rd__h5648 = stage2_rg_stage2[196:192]; - endcase - end - always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64) - begin - case (stage2_rg_stage2[199:197]) - 3'd0: x_out_data_to_stage3_rd_val__h5649 = stage2_rg_stage2[127:64]; - 3'd1, 3'd4: x_out_data_to_stage3_rd_val__h5649 = near_mem$dmem_word64; - default: x_out_data_to_stage3_rd_val__h5649 = stage2_mbox$word; - endcase - end - always@(stage2_rg_stage2) - begin - case (stage2_rg_stage2[199:197]) - 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h5999 = stage2_rg_stage2[196:192]; - default: x_out_bypass_rd__h5999 = stage2_rg_stage2[196:192]; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$word or output_stage2___1_bypass_rd_val__h5988) - begin - case (stage2_rg_stage2[199:197]) - 3'd0: x_out_bypass_rd_val__h6000 = stage2_rg_stage2[127:64]; - 3'd1, 3'd4: - x_out_bypass_rd_val__h6000 = output_stage2___1_bypass_rd_val__h5988; - default: x_out_bypass_rd_val__h6000 = stage2_mbox$word; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119 or - IF_near_mem_dmem_valid__13_THEN_IF_near_mem_dm_ETC___d116) - begin - case (stage2_rg_stage2[199:197]) - 3'd0: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q1 = 2'd2; - 3'd1, 3'd2, 3'd4: - CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q1 = - IF_near_mem_dmem_valid__13_THEN_IF_near_mem_dm_ETC___d116; - default: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q1 = - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[199:197]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d136 = - !near_mem$dmem_valid || near_mem$dmem_exc; - default: IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d136 = - !stage2_mbox$valid; - endcase - end - always@(stage2_rg_stage2 or - stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc) - begin - case (stage2_rg_stage2[199:197]) - 3'd1, 3'd2, 3'd4: - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145 = - near_mem$dmem_valid && !near_mem$dmem_exc; - default: IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145 = - stage2_mbox$valid; - endcase - end - always@(stage2_rg_stage2 or - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119 or - IF_NOT_near_mem_dmem_valid__13_32_OR_NOT_near__ETC___d179) - begin - case (stage2_rg_stage2[199:197]) - 3'd0: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2 = 2'd2; - 3'd1, 3'd4: - CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2 = - IF_NOT_near_mem_dmem_valid__13_32_OR_NOT_near__ETC___d179; - 3'd2: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2 = 2'd0; - default: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q2 = - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_3_9_ETC___d119; - endcase - end - always@(rg_cur_priv) - begin - case (rg_cur_priv) - 2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd8; - 2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd9; - default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd11; - endcase - end - always@(_theResult____h4283 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q5) - begin - case (_theResult____h4283[31:20]) - 12'b0: - CASE_theResult__283_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = - CASE_rg_cur_priv_0b0_8_0b1_9_11__q5; - 12'b000000000001: - CASE_theResult__283_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd3; - default: CASE_theResult__283_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd2; - endcase - end - always@(_theResult____h4283 or alu_outputs___1_exc_code__h12886) - begin - case (_theResult____h4283[6:0]) - 7'b0000011, - 7'b0001111, - 7'b0010011, - 7'b0010111, - 7'b0011011, - 7'b0100011, - 7'b0110011, - 7'b0110111, - 7'b0111011, - 7'b1100011: - alu_outputs_exc_code__h12932 = 4'd2; - 7'b1100111, 7'b1101111: alu_outputs_exc_code__h12932 = 4'd0; - 7'b1110011: - alu_outputs_exc_code__h12932 = alu_outputs___1_exc_code__h12886; - default: alu_outputs_exc_code__h12932 = 4'd2; - endcase - end - always@(funct10__h12562 or - _theResult___fst__h13601 or - rd_val___1__h14922 or - rd_val___1__h14976 or rd_val___1__h15021 or rd_val___1__h14970) - begin - case (funct10__h12562) - 10'b0: alu_outputs___1_val1__h12576 = rd_val___1__h14922; - 10'b0000000001: alu_outputs___1_val1__h12576 = rd_val___1__h14976; - 10'b0000000101: alu_outputs___1_val1__h12576 = rd_val___1__h15021; - 10'b0100000000: alu_outputs___1_val1__h12576 = rd_val___1__h14970; - default: alu_outputs___1_val1__h12576 = _theResult___fst__h13601; - endcase - end - always@(_theResult____h4283 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560) - begin - case (_theResult____h4283[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d695 = - _theResult____h4283[14:12] != 3'b111 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562; - endcase - end - always@(_theResult____h4283 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560) - begin - case (_theResult____h4283[14:12]) - 3'b0: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558; - 3'b001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d558; - 3'b100: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560; - 3'b101: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d560; - 3'b110: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 = - _theResult____h4283[14:12] == 3'b111 && - !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d562; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[6:0]) - 7'b0000011: - CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4283[14:12] != 3'b0 && - _theResult____h4283[14:12] != 3'b100 && - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b101 && - _theResult____h4283[14:12] != 3'b010 && - _theResult____h4283[14:12] != 3'b110 && - _theResult____h4283[14:12] != 3'b011; - 7'b0100011: - CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4283[14:12] != 3'b0 && - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b010 && - _theResult____h4283[14:12] != 3'b011; - default: CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 = - _theResult____h4283[6:0] != 7'b0101111 || - _theResult____h4283[31:27] != 5'b00010 && - _theResult____h4283[31:27] != 5'b00011 && - _theResult____h4283[31:27] != 5'b0 && - _theResult____h4283[31:27] != 5'b00001 && - _theResult____h4283[31:27] != 5'b01100 && - _theResult____h4283[31:27] != 5'b01000 && - _theResult____h4283[31:27] != 5'b00100 && - _theResult____h4283[31:27] != 5'b10000 && - _theResult____h4283[31:27] != 5'b11000 && - _theResult____h4283[31:27] != 5'b10100 && - _theResult____h4283[31:27] != 5'b11100 || - _theResult____h4283[14:12] != 3'b010 && - _theResult____h4283[14:12] != 3'b011; - endcase - end - always@(_theResult____h4283 or - CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12 or - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d605 or - funct10__h12562) - begin - case (_theResult____h4283[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d605; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - _theResult____h4283[14:12] != 3'b0 && - (_theResult____h4283[14:12] != 3'b001 || - _theResult____h4283[25]) && - (_theResult____h4283[14:12] != 3'b101 || - _theResult____h4283[25]); - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - funct10__h12562 != 10'b0 && funct10__h12562 != 10'b0100000000 && - funct10__h12562 != 10'b0000000001 && - funct10__h12562 != 10'b0000000101 && - funct10__h12562 != 10'b0100000101; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - _theResult____h4283[6:0] != 7'b0110111 && - _theResult____h4283[6:0] != 7'b0010111 && - CASE_theResult__283_BITS_6_TO_0_0b11_NOT_theRe_ETC__q12; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[6:0]) - 7'b0000011: - CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13 = - _theResult____h4283[14:12] == 3'b0 || - _theResult____h4283[14:12] == 3'b100 || - _theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b101 || - _theResult____h4283[14:12] == 3'b010 || - _theResult____h4283[14:12] == 3'b110 || - _theResult____h4283[14:12] == 3'b011; - 7'b0100011: - CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13 = - _theResult____h4283[14:12] == 3'b0 || - _theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b010 || - _theResult____h4283[14:12] == 3'b011; - default: CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13 = - _theResult____h4283[6:0] == 7'b0101111 && - (_theResult____h4283[31:27] == 5'b00010 || - _theResult____h4283[31:27] == 5'b00011 || - _theResult____h4283[31:27] == 5'b0 || - _theResult____h4283[31:27] == 5'b00001 || - _theResult____h4283[31:27] == 5'b01100 || - _theResult____h4283[31:27] == 5'b01000 || - _theResult____h4283[31:27] == 5'b00100 || - _theResult____h4283[31:27] == 5'b10000 || - _theResult____h4283[31:27] == 5'b11000 || - _theResult____h4283[31:27] == 5'b10100 || - _theResult____h4283[31:27] == 5'b11100) && - (_theResult____h4283[14:12] == 3'b010 || - _theResult____h4283[14:12] == 3'b011); - endcase - end - always@(_theResult____h4283 or - CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d724 or - funct10__h12562) - begin - case (_theResult____h4283[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d724; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762 = - _theResult____h4283[14:12] == 3'b0 || - (_theResult____h4283[14:12] == 3'b001 || - _theResult____h4283[14:12] == 3'b101) && - !_theResult____h4283[25]; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762 = - funct10__h12562 == 10'b0 || funct10__h12562 == 10'b0100000000 || - funct10__h12562 == 10'b0000000001 || - funct10__h12562 == 10'b0000000101 || - funct10__h12562 == 10'b0100000101; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d762 = - _theResult____h4283[6:0] == 7'b0110111 || - _theResult____h4283[6:0] == 7'b0010111 || - CASE_theResult__283_BITS_6_TO_0_0b11_theResult_ETC__q13; - endcase - end - always@(_theResult____h4283 or - rg_cur_priv or - IF_rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_E_ETC___d809) - begin - case (_theResult____h4283[31:20]) - 12'b0, 12'b000000000001: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d811 = 4'd11; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d811 = - (rg_cur_priv == 2'b11 && - _theResult____h4283[31:20] == 12'b001100000010) ? - 4'd7 : - IF_rg_cur_priv_3_EQ_0b11_90_OR_rg_cur_priv_3_E_ETC___d809; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[14:12]) - 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd0; - 3'd7: CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd11; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[14:12]) - 3'b0: CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd4; - 3'b001: CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd5; - default: CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15 = 4'd11; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[14:12]) - 3'b0, 3'b001, 3'b010, 3'b011: - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q16 = 4'd0; - default: CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q16 = - 4'd11; - endcase - end - always@(_theResult____h4283 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d811) - begin - case (_theResult____h4283[14:12]) - 3'b0: - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17 = - (_theResult____h4283[11:7] == 5'd0 && - _theResult____h4283[19:15] == 5'd0) ? - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d811 : - 4'd11; - 3'b001, 3'b101: - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17 = 4'd2; - 3'b010, 3'b011, 3'b110, 3'b111: - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17 = 4'd3; - 3'd4: CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17 = 4'd11; - endcase - end - always@(_theResult____h4283 or - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 or - CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15 or - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d774 or - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q16 or - funct10__h12562 or - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17) - begin - case (_theResult____h4283[6:0]) - 7'b0000011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14; - 7'b0001111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - CASE_theResult__283_BITS_14_TO_12_0b0_4_0b1_5_11__q15; - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d774; - 7'b0010111, 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = 4'd0; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - (_theResult____h4283[14:12] != 3'b0 && - (_theResult____h4283[14:12] != 3'b001 || - _theResult____h4283[25]) && - (_theResult____h4283[14:12] != 3'b101 || - _theResult____h4283[25])) ? - 4'd11 : - 4'd0; - 7'b0100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - CASE_theResult__283_BITS_14_TO_12_0b0_0_0b1_0__ETC__q16; - 7'b0101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - ((_theResult____h4283[31:27] == 5'b00010 || - _theResult____h4283[31:27] == 5'b00011 || - _theResult____h4283[31:27] == 5'b0 || - _theResult____h4283[31:27] == 5'b00001 || - _theResult____h4283[31:27] == 5'b01100 || - _theResult____h4283[31:27] == 5'b01000 || - _theResult____h4283[31:27] == 5'b00100 || - _theResult____h4283[31:27] == 5'b10000 || - _theResult____h4283[31:27] == 5'b11000 || - _theResult____h4283[31:27] == 5'b10100 || - _theResult____h4283[31:27] == 5'b11100) && - (_theResult____h4283[14:12] == 3'b010 || - _theResult____h4283[14:12] == 3'b011)) ? - 4'd0 : - 4'd11; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - (funct10__h12562 != 10'b0 && - funct10__h12562 != 10'b0100000000 && - funct10__h12562 != 10'b0000000001 && - funct10__h12562 != 10'b0000000101 && - funct10__h12562 != 10'b0100000101) ? - 4'd11 : - 4'd0; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - CASE_theResult__283_BITS_14_TO_12_0b0_IF_theRe_ETC__q17; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 = - 4'd11; - endcase - end - always@(_theResult____h4283 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d717 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569) - begin - case (_theResult____h4283[6:0]) - 7'b1100011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d831 = - (_theResult____h4283[14:12] != 3'b0 && - _theResult____h4283[14:12] != 3'b001 && - _theResult____h4283[14:12] != 3'b100 && - _theResult____h4283[14:12] != 3'b101 && - _theResult____h4283[14:12] != 3'b110 && - _theResult____h4283[14:12] != 3'b111) ? - 4'd11 : - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d569 ? - 4'd1 : - 4'd0); - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d831 = 4'd1; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d831 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d717 ? - 4'd0 : - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d828; - endcase - end - always@(_theResult____h4283) - begin - case (_theResult____h4283[6:0]) - 7'b0000011: - CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18 = 3'd1; - 7'b0010011, 7'b0010111, 7'b0011011, 7'b0110011, 7'b0110111, 7'b0111011: - CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18 = 3'd0; - 7'b0100011: - CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18 = 3'd2; - default: CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18 = 3'd4; - endcase - end - always@(_theResult____h4283 or - CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18) - begin - case (_theResult____h4283[6:0]) - 7'b1100011, 7'b1100111, 7'b1101111: - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 = 3'd0; - default: IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 = - ((_theResult____h4283[6:0] == 7'b0110011 || - _theResult____h4283[6:0] == 7'b0111011) && - _theResult____h4283[31:25] == 7'b0000001) ? - 3'd3 : - CASE_theResult__283_BITS_6_TO_0_0b11_1_0b10011_ETC__q18; - endcase - end - always@(_theResult____h4283 or - _theResult_____1_fst__h13410 or - rd_val___1__h13378 or - rd_val___1__h13385 or rd_val___1__h13392 or rd_val___1__h13399) - begin - case (_theResult____h4283[14:12]) - 3'b010: _theResult_____1_fst__h13382 = rd_val___1__h13378; - 3'b011: _theResult_____1_fst__h13382 = rd_val___1__h13385; - 3'b100: _theResult_____1_fst__h13382 = rd_val___1__h13392; - 3'b110: _theResult_____1_fst__h13382 = rd_val___1__h13399; - default: _theResult_____1_fst__h13382 = _theResult_____1_fst__h13410; - endcase - end - always@(_theResult____h4283 or - rs1_val_bypassed__h4291 or - alu_outputs___1_addr__h12629 or - alu_outputs___1_addr__h12650 or - alu_outputs___1_addr__h12330 or - alu_outputs___1_addr__h12377 or alu_outputs___1_addr__h12351) - begin - case (_theResult____h4283[6:0]) - 7'b0000011: - x_out_data_to_stage2_addr__h12206 = alu_outputs___1_addr__h12629; - 7'b0100011: - x_out_data_to_stage2_addr__h12206 = alu_outputs___1_addr__h12650; - 7'b1100011: - x_out_data_to_stage2_addr__h12206 = alu_outputs___1_addr__h12330; - 7'b1100111: - x_out_data_to_stage2_addr__h12206 = alu_outputs___1_addr__h12377; - 7'b1101111: - x_out_data_to_stage2_addr__h12206 = alu_outputs___1_addr__h12351; - default: x_out_data_to_stage2_addr__h12206 = rs1_val_bypassed__h4291; - endcase - end - always@(_theResult____h4283 or imem_rg_pc or data_to_stage2_addr__h12198) - begin - case (_theResult____h4283[6:0]) - 7'b1100111, 7'b1101111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1151 = - data_to_stage2_addr__h12198; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1151 = - (_theResult____h4283[6:0] == 7'b1110011 && - _theResult____h4283[14:12] == 3'b0 && - _theResult____h4283[11:7] == 5'd0 && - _theResult____h4283[19:15] == 5'd0 && - _theResult____h4283[31:20] == 12'b000000000001) ? - imem_rg_pc : - 64'd0; - endcase - end - always@(_theResult____h4283 or - alu_outputs___1_val1__h12911 or - alu_outputs___1_val1__h12530 or - alu_outputs___1_val1__h12608 or - alu_outputs___1_val1__h12553 or - alu_outputs___1_val1__h12592 or - alu_outputs___1_val1__h12576 or alu_outputs___1_val1__h12890) - begin - case (_theResult____h4283[6:0]) - 7'b0010011, 7'b0110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12530; - 7'b0010111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12608; - 7'b0011011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12553; - 7'b0110111: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12592; - 7'b0111011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12576; - 7'b1110011: - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12890; - default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1063 = - alu_outputs___1_val1__h12911; - endcase - end - always@(_theResult____h4283 or - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1065 or - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d962) - begin - case (_theResult____h4283[6:0]) - 7'b1100111, 7'b1101111: - x_out_data_to_stage2_val1__h12207 = - IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d962; - default: x_out_data_to_stage2_val1__h12207 = - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1065; - endcase - end - always@(x_out_data_to_stage2_instr__h12203 or - x_out_data_to_stage2_val1__h12207) - begin - case (x_out_data_to_stage2_instr__h12203[14:12]) - 3'b010, 3'b011: rs1_val__h18963 = x_out_data_to_stage2_val1__h12207; - default: rs1_val__h18963 = - { 59'd0, x_out_data_to_stage2_instr__h12203[19:15] }; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0; - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11; - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0; - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_logdelay$EN) - cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN; - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_cur_priv$EN) - rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN; - if (rg_run_on_reset$EN) - rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (stage1_rg_full$EN) - stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN; - if (stage2_rg_full$EN) - stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN; - if (stage2_rg_resetting$EN) - stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY - stage2_rg_resetting$D_IN; - if (stage3_rg_full$EN) - stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN; - end - if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN; - if (imem_rg_instr_15_0$EN) - imem_rg_instr_15_0 <= `BSV_ASSIGNMENT_DELAY imem_rg_instr_15_0$D_IN; - if (imem_rg_mstatus_MXR$EN) - imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN; - if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN; - if (imem_rg_priv$EN) - imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN; - if (imem_rg_satp$EN) - imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN; - if (imem_rg_sstatus_SUM$EN) - imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN; - if (imem_rg_tval$EN) - imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN; - if (rg_mstatus_MXR$EN) - rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN; - if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN; - if (rg_sstatus_SUM$EN) - rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN; - if (rg_start_CPI_cycles$EN) - rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN; - if (rg_start_CPI_instrs$EN) - rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN; - if (stage2_rg_stage2$EN) - stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN; - if (stage3_rg_stage3$EN) - stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_logdelay = 64'hAAAAAAAAAAAAAAAA; - cfg_verbosity = 4'hA; - imem_rg_f3 = 3'h2; - imem_rg_instr_15_0 = 16'hAAAA; - imem_rg_mstatus_MXR = 1'h0; - imem_rg_pc = 64'hAAAAAAAAAAAAAAAA; - imem_rg_priv = 2'h2; - imem_rg_satp = 64'hAAAAAAAAAAAAAAAA; - imem_rg_sstatus_SUM = 1'h0; - imem_rg_tval = 64'hAAAAAAAAAAAAAAAA; - rg_cur_priv = 2'h2; - rg_mstatus_MXR = 1'h0; - rg_next_pc = 64'hAAAAAAAAAAAAAAAA; - rg_run_on_reset = 1'h0; - rg_sstatus_SUM = 1'h0; - rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA; - rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA; - rg_state = 4'hA; - stage1_rg_full = 1'h0; - stage2_rg_full = 1'h0; - stage2_rg_resetting = 1'h0; - stage2_rg_stage2 = - 298'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - stage3_rg_full = 1'h0; - stage3_rg_stage3 = 168'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - rg_cur_priv, - csr_regfile$read_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write("MStatus{", - "sd:%0d", - csr_regfile$read_mstatus[14:13] == 2'h3 || - csr_regfile$read_mstatus[16:15] == 2'h3); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2) - $write(" sxl:%0d uxl:%0d", sxl__h4705, uxl__h4706); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tsr:%0d", csr_regfile$read_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tw:%0d", csr_regfile$read_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" tvm:%0d", csr_regfile$read_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mxr:%0d", csr_regfile$read_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" sum:%0d", csr_regfile$read_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mprv:%0d", csr_regfile$read_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" xs:%0d", csr_regfile$read_mstatus[16:15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" fs:%0d", csr_regfile$read_mstatus[14:13]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" mpp:%0d", csr_regfile$read_mstatus[12:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" spp:%0d", csr_regfile$read_mstatus[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" pies:%0d_%0d%0d", - csr_regfile$read_mstatus[7], - csr_regfile$read_mstatus[5], - csr_regfile$read_mstatus[4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $write(" ies:%0d_%0d%0d", - csr_regfile$read_mstatus[3], - csr_regfile$read_mstatus[1], - csr_regfile$read_mstatus[0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - (!stage3_rg_full || !stage3_rg_stage3[69])) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full && stage3_rg_stage3[69]) - $write("Rd %0d ", - stage3_rg_stage3[68:64], - "rd_val:%h", - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage2: pc 0x%08h instr 0x%08h priv %0d", - stage2_rg_stage2[295:232], - stage2_rg_stage2[231:200], - stage2_rg_stage2[297:296]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write("Output_Stage2", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[295:232]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("Output_Stage2", " NONPIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write("Output_Stage2", " PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[295:232], - stage2_rg_stage2[231:200], - stage2_rg_stage2[297:296]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3 && - stage2_rg_stage2[199:197] != 3'd0 && - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d136) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3 && - (stage2_rg_stage2[199:197] == 3'd0 || - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h5648, - x_out_data_to_stage3_rd_val__h5649); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", stage2_rg_stage2[295:232]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", near_mem$dmem_exc_code); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", stage2_rg_stage2[191:128], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", stage2_rg_stage2[295:232]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", near_mem$dmem_exc_code); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd1) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd3) - $write("'h%h", stage2_rg_stage2[191:128], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd1 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 != 2'd3) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == 2'd0) - $write("Rd -"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 != 2'd0) - $write("Rd %0d ", x_out_bypass_rd__h5999); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == 2'd0) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 == 2'd1) - $write("-"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 != 2'd0 && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d183 != 2'd1) - $write("rd_val:%h", x_out_bypass_rd_val__h6000); - if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) - $display(" Stage1: pc 0x%08h instr 0x%08h priv %0d", - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write("Output_Stage1", " BUSY pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write("Output_Stage1", " NONPIPE: pc:%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write("Output_Stage1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) - $write("Output_Stage1", " EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(" PIPE: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd0) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd1) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd2) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd3) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd4) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd5) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd6) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd7) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd8) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd9) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d833 == 4'd10) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d899) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n", - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(" op_stage2:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == 3'd0) - $write("OP_Stage2_ALU"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == 3'd1) - $write("OP_Stage2_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == 3'd2) - $write("OP_Stage2_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - !near_mem$imem_exc && - (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d765 || - IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d767) && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d916 == 3'd3) - $write("OP_Stage2_M"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - NOT_near_mem_imem_exc__20_05_AND_IF_IF_NOT_nea_ETC___d940) - $write("OP_Stage2_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(" rd:%0d\n", x_out_data_to_stage2_rd__h12205); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(" addr:%h val1:%h val2:%h}", - x_out_data_to_stage2_addr__h12206, - x_out_data_to_stage2_val1__h12207, - x_out_data_to_stage2_val2__h12208); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1076) - $write("CONTROL_STRAIGHT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1079) - $write("CONTROL_BRANCH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1082) - $write("CONTROL_CSRR_W"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1085) - $write("CONTROL_CSRR_S_or_C"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1088) - $write("CONTROL_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1091) - $write("CONTROL_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1094) - $write("CONTROL_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1097) - $write("CONTROL_MRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1100) - $write("CONTROL_SRET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1103) - $write("CONTROL_URET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1106) - $write("CONTROL_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519 && - near_mem_imem_exc__20_OR_IF_IF_NOT_near_mem_im_ETC___d1109) - $write("CONTROL_TRAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write("Trap_Info { ", "epc: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write("'h%h", imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write("'h%h", x_out_trap_info_exc_code__h14097); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write(", ", "tval: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d703) - $write("'h%h", value__h14148, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d770) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - NOT_near_mem_imem_valid_99_OR_NOT_near_mem_ime_ETC___d504) - $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d519) - $write(" next_pc 0x%08h", x_out_next_pc__h12175); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_show_pipe) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[295:232], - stage2_rg_stage2[231:200], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h2988 != 4'd0) - $display(" mcause:0x%0h epc 0x%0h tval:0x%0h new pc 0x%0h, new mstatus 0x%0h", - csr_regfile$csr_trap_actions[65:2], - stage2_rg_stage2[295:232], - stage2_rg_stage2[191:128], - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[129:66]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12203[19:15], - rs1_val__h18473, - x_out_data_to_stage2_instr__h12203[31:20], - csr_regfile$read_csr[63:0], - x_out_data_to_stage2_instr__h12203[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12203[19:15], - rs1_val__h18473, - x_out_data_to_stage2_instr__h12203[31:20], - x_out_data_to_stage2_instr__h12203[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_S_or_C", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12203[19:15], - rs1_val__h18963, - x_out_data_to_stage2_instr__h12203[31:20], - csr_regfile$read_csr[63:0], - x_out_data_to_stage2_instr__h12203[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !csr_regfile$access_permitted_2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12203[19:15], - rs1_val__h18963, - x_out_data_to_stage2_instr__h12203[31:20], - x_out_data_to_stage2_instr__h12203[11:7]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12175); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d pc:%0x cur_priv:%0d", - csr_regfile$read_csr_mcycle, - csr_regfile$read_csr_minstret, - x_out_next_pc__h12175, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2988 != 4'd0) - $display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d", - csr_regfile$csr_ret_actions[129:66], - csr_regfile$csr_ret_actions[63:0], - csr_regfile$csr_ret_actions[65:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE_I && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_FENCE_I"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_FENCE && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_SFENCE_VMA", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_finish_SFENCE_VMA"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU.rl_stage1_WFI"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h2988 != 4'd0) - $display(" WFI resume"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_from_WFI && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d1398) - $display("%0d: CPU.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x", - csr_regfile$read_csr_mcycle, - csr_regfile$csr_trap_actions[193:130], - x_out_data_to_stage2_instr__h12203); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d1398) - $display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'", - cpi__h23529, - cpifrac__h23530, - delta_CPI_cycles__h23525, - _theResult____h23527); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && - IF_NOT_stage1_rg_full_97_98_OR_NOT_near_mem_im_ETC___d1398) - $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2988 != 4'd0) - $display("%0d: CPU.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", - csr_regfile$read_csr_mcycle, - rg_cur_priv, - csr_regfile$csr_trap_actions[65:2], - imem_rg_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2988 != 4'd0) - $display(" tval:0x%0h new pc:0x%0h new mstatus:0x%0h", - value__h14148, - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[129:66]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_trap_fetch && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - imem_rg_pc, - x_out_data_to_stage2_instr__h12203, - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2988 != 4'd0) - $display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", - csr_regfile$read_csr_mcycle, - imem_rg_pc, - csr_regfile$csr_trap_actions[193:130], - csr_regfile$csr_trap_actions[1:0], - csr_regfile$csr_trap_actions[129:66]); - if (WILL_FIRE_RL_imem_rl_assert_fail) - $display("ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False"); - if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", soc_map$m_pc_reset_value); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h", - csr_regfile$read_csr_mcycle, - soc_map$m_pc_reset_value); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE", - csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[69] && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h", - stage3_rg_stage3[68:64], - stage3_rg_stage3[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" S3.enq: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n", - stage2_rg_stage2[295:232], - stage2_rg_stage2[231:200], - stage2_rg_stage2[297:296]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" rd_valid:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - stage2_rg_stage2[199:197] != 3'd0 && - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d136) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 && - (stage2_rg_stage2[199:197] == 3'd0 || - IF_stage2_rg_stage2_2_BITS_199_TO_197_3_EQ_1_5_ETC___d145)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h5648, - x_out_data_to_stage3_rd_val__h5649); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - IF_stage2_rg_full_1_THEN_IF_stage2_rg_stage2_2_ETC___d122 == 2'd2 && - cur_verbosity__h2988 == 4'd1) - $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", - csr_regfile$read_csr_minstret, - stage2_rg_stage2[295:232], - stage2_rg_stage2[231:200], - rg_cur_priv); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage2.enq (Data_Stage1_to_Stage2)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_pipe && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1241 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1282 && - NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12175); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $write("CPU: Bluespec RISC-V Piccolo v3.0"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) $display(" (RV64)"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h2988 != 4'd0) - $display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle); - end - // synopsys translate_on -endmodule // mkCPU - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v deleted file mode 100644 index bcb2abf3..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIE.v +++ /dev/null @@ -1,141 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 64 -// fav_write O 64 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 64 -// EN_reset I 1 -// EN_fav_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIE(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [63 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [63 : 0] fav_write_wordxl; - input EN_fav_write; - output [63 : 0] fav_write; - - // signals for module outputs - wire [63 : 0] fav_write, fv_read; - - // register rg_mie - reg [11 : 0] rg_mie; - wire [11 : 0] rg_mie$D_IN; - wire rg_mie$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_write, - CAN_FIRE_reset, - WILL_FIRE_fav_write, - WILL_FIRE_reset; - - // remaining internal signals - wire [11 : 0] mie__h88; - wire seie__h119, ssie__h113, stie__h116, ueie__h118, usie__h112, utie__h115; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 52'd0, rg_mie } ; - - // actionvalue method fav_write - assign fav_write = { 52'd0, mie__h88 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // register rg_mie - assign rg_mie$D_IN = EN_fav_write ? mie__h88 : 12'd0 ; - assign rg_mie$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign mie__h88 = - { fav_write_wordxl[11], - 1'b0, - seie__h119, - ueie__h118, - fav_write_wordxl[7], - 1'b0, - stie__h116, - utie__h115, - fav_write_wordxl[3], - 1'b0, - ssie__h113, - usie__h112 } ; - assign seie__h119 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssie__h113 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign stie__h116 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueie__h118 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign usie__h112 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign utie__h115 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_mie = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIE - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v deleted file mode 100644 index df113ffb..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_MIP.v +++ /dev/null @@ -1,289 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// fv_read O 64 -// fav_write O 64 -// CLK I 1 clock -// RST_N I 1 reset -// fav_write_misa I 28 -// fav_write_wordxl I 64 -// m_external_interrupt_req_req I 1 reg -// s_external_interrupt_req_req I 1 reg -// software_interrupt_req_req I 1 reg -// timer_interrupt_req_req I 1 reg -// EN_reset I 1 -// EN_fav_write I 1 -// -// Combinational paths from inputs to outputs: -// (fav_write_misa, fav_write_wordxl) -> fav_write -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_MIP(CLK, - RST_N, - - EN_reset, - - fv_read, - - fav_write_misa, - fav_write_wordxl, - EN_fav_write, - fav_write, - - m_external_interrupt_req_req, - - s_external_interrupt_req_req, - - software_interrupt_req_req, - - timer_interrupt_req_req); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - - // value method fv_read - output [63 : 0] fv_read; - - // actionvalue method fav_write - input [27 : 0] fav_write_misa; - input [63 : 0] fav_write_wordxl; - input EN_fav_write; - output [63 : 0] fav_write; - - // action method m_external_interrupt_req - input m_external_interrupt_req_req; - - // action method s_external_interrupt_req - input s_external_interrupt_req_req; - - // action method software_interrupt_req - input software_interrupt_req_req; - - // action method timer_interrupt_req - input timer_interrupt_req_req; - - // signals for module outputs - wire [63 : 0] fav_write, fv_read; - - // register rg_meip - reg rg_meip; - wire rg_meip$D_IN, rg_meip$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_seip - reg rg_seip; - wire rg_seip$D_IN, rg_seip$EN; - - // register rg_ssip - reg rg_ssip; - wire rg_ssip$D_IN, rg_ssip$EN; - - // register rg_stip - reg rg_stip; - wire rg_stip$D_IN, rg_stip$EN; - - // register rg_ueip - reg rg_ueip; - wire rg_ueip$D_IN, rg_ueip$EN; - - // register rg_usip - reg rg_usip; - wire rg_usip$D_IN, rg_usip$EN; - - // register rg_utip - reg rg_utip; - wire rg_utip$D_IN, rg_utip$EN; - - // rule scheduling signals - wire CAN_FIRE_fav_write, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_reset, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_fav_write, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_reset, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // remaining internal signals - wire [11 : 0] new_mip__h524, new_mip__h942; - wire seip__h558, ssip__h562, stip__h560, ueip__h559, usip__h563, utip__h561; - - // action method reset - assign CAN_FIRE_reset = 1'd1 ; - assign WILL_FIRE_reset = EN_reset ; - - // value method fv_read - assign fv_read = { 52'd0, new_mip__h524 } ; - - // actionvalue method fav_write - assign fav_write = { 52'd0, new_mip__h942 } ; - assign CAN_FIRE_fav_write = 1'd1 ; - assign WILL_FIRE_fav_write = EN_fav_write ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // register rg_meip - assign rg_meip$D_IN = m_external_interrupt_req_req ; - assign rg_meip$EN = 1'b1 ; - - // register rg_msip - assign rg_msip$D_IN = software_interrupt_req_req ; - assign rg_msip$EN = 1'b1 ; - - // register rg_mtip - assign rg_mtip$D_IN = timer_interrupt_req_req ; - assign rg_mtip$EN = 1'b1 ; - - // register rg_seip - assign rg_seip$D_IN = s_external_interrupt_req_req ; - assign rg_seip$EN = 1'b1 ; - - // register rg_ssip - assign rg_ssip$D_IN = !EN_reset && ssip__h562 ; - assign rg_ssip$EN = EN_fav_write || EN_reset ; - - // register rg_stip - assign rg_stip$D_IN = !EN_reset && stip__h560 ; - assign rg_stip$EN = EN_fav_write || EN_reset ; - - // register rg_ueip - assign rg_ueip$D_IN = !EN_reset && ueip__h559 ; - assign rg_ueip$EN = EN_fav_write || EN_reset ; - - // register rg_usip - assign rg_usip$D_IN = !EN_reset && usip__h563 ; - assign rg_usip$EN = EN_fav_write || EN_reset ; - - // register rg_utip - assign rg_utip$D_IN = !EN_reset && utip__h561 ; - assign rg_utip$EN = EN_fav_write || EN_reset ; - - // remaining internal signals - assign new_mip__h524 = - { rg_meip, - 1'b0, - rg_seip, - rg_ueip, - rg_mtip, - 1'b0, - rg_stip, - rg_utip, - rg_msip, - 1'b0, - rg_ssip, - rg_usip } ; - assign new_mip__h942 = - { rg_meip, - 1'b0, - seip__h558, - ueip__h559, - rg_mtip, - 1'b0, - stip__h560, - utip__h561, - rg_msip, - 1'b0, - ssip__h562, - usip__h563 } ; - assign seip__h558 = fav_write_misa[18] && fav_write_wordxl[9] ; - assign ssip__h562 = fav_write_misa[18] && fav_write_wordxl[1] ; - assign stip__h560 = fav_write_misa[18] && fav_write_wordxl[5] ; - assign ueip__h559 = fav_write_misa[13] && fav_write_wordxl[8] ; - assign usip__h563 = fav_write_misa[13] && fav_write_wordxl[0] ; - assign utip__h561 = fav_write_misa[13] && fav_write_wordxl[4] ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN; - if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN; - if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN; - if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN; - if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN; - if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_meip = 1'h0; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_seip = 1'h0; - rg_ssip = 1'h0; - rg_stip = 1'h0; - rg_ueip = 1'h0; - rg_usip = 1'h0; - rg_utip = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCSR_MIP - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v deleted file mode 100644 index 3cf39d61..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCSR_RegFile.v +++ /dev/null @@ -1,2371 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_csr O 65 -// read_csr_port2 O 65 -// mav_read_csr O 65 -// mav_csr_write O 64 -// read_misa O 28 const -// read_mstatus O 64 reg -// read_ustatus O 64 -// read_satp O 64 const -// csr_trap_actions O 194 -// RDY_csr_trap_actions O 1 const -// csr_ret_actions O 130 -// RDY_csr_ret_actions O 1 const -// read_csr_minstret O 64 reg -// read_csr_mcycle O 64 reg -// read_csr_mtime O 64 reg -// access_permitted_1 O 1 -// access_permitted_2 O 1 -// csr_counter_read_fault O 1 -// csr_mip_read O 64 -// interrupt_pending O 5 -// wfi_resume O 1 -// nmi_pending O 1 reg -// RDY_debug O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// read_csr_csr_addr I 12 -// read_csr_port2_csr_addr I 12 -// mav_read_csr_csr_addr I 12 -// mav_csr_write_csr_addr I 12 -// mav_csr_write_word I 64 -// csr_trap_actions_from_priv I 2 -// csr_trap_actions_pc I 64 -// csr_trap_actions_nmi I 1 -// csr_trap_actions_interrupt I 1 -// csr_trap_actions_exc_code I 4 -// csr_trap_actions_xtval I 64 -// csr_ret_actions_from_priv I 2 -// access_permitted_1_priv I 2 -// access_permitted_1_csr_addr I 12 -// access_permitted_1_read_not_write I 1 -// access_permitted_2_priv I 2 -// access_permitted_2_csr_addr I 12 -// access_permitted_2_read_not_write I 1 -// csr_counter_read_fault_priv I 2 -// csr_counter_read_fault_csr_addr I 12 -// m_external_interrupt_req_set_not_clear I 1 reg -// s_external_interrupt_req_set_not_clear I 1 reg -// timer_interrupt_req_set_not_clear I 1 reg -// software_interrupt_req_set_not_clear I 1 reg -// interrupt_pending_cur_priv I 2 -// nmi_req_set_not_clear I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_csr_minstret_incr I 1 -// EN_debug I 1 unused -// EN_mav_read_csr I 1 unused -// EN_mav_csr_write I 1 -// EN_csr_trap_actions I 1 -// EN_csr_ret_actions I 1 -// -// Combinational paths from inputs to outputs: -// read_csr_csr_addr -> read_csr -// read_csr_port2_csr_addr -> read_csr_port2 -// (access_permitted_1_priv, -// access_permitted_1_csr_addr, -// access_permitted_1_read_not_write) -> access_permitted_1 -// (access_permitted_2_priv, -// access_permitted_2_csr_addr, -// access_permitted_2_read_not_write) -> access_permitted_2 -// (csr_counter_read_fault_priv, -// csr_counter_read_fault_csr_addr) -> csr_counter_read_fault -// interrupt_pending_cur_priv -> interrupt_pending -// mav_read_csr_csr_addr -> mav_read_csr -// (mav_csr_write_csr_addr, -// mav_csr_write_word, -// EN_mav_csr_write) -> mav_csr_write -// (csr_trap_actions_from_priv, -// csr_trap_actions_nmi, -// csr_trap_actions_interrupt, -// csr_trap_actions_exc_code) -> csr_trap_actions -// csr_ret_actions_from_priv -> csr_ret_actions -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCSR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_csr_csr_addr, - read_csr, - - read_csr_port2_csr_addr, - read_csr_port2, - - mav_read_csr_csr_addr, - EN_mav_read_csr, - mav_read_csr, - - mav_csr_write_csr_addr, - mav_csr_write_word, - EN_mav_csr_write, - mav_csr_write, - - read_misa, - - read_mstatus, - - read_ustatus, - - read_satp, - - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_nmi, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval, - EN_csr_trap_actions, - csr_trap_actions, - RDY_csr_trap_actions, - - csr_ret_actions_from_priv, - EN_csr_ret_actions, - csr_ret_actions, - RDY_csr_ret_actions, - - read_csr_minstret, - - EN_csr_minstret_incr, - - read_csr_mcycle, - - read_csr_mtime, - - access_permitted_1_priv, - access_permitted_1_csr_addr, - access_permitted_1_read_not_write, - access_permitted_1, - - access_permitted_2_priv, - access_permitted_2_csr_addr, - access_permitted_2_read_not_write, - access_permitted_2, - - csr_counter_read_fault_priv, - csr_counter_read_fault_csr_addr, - csr_counter_read_fault, - - csr_mip_read, - - m_external_interrupt_req_set_not_clear, - - s_external_interrupt_req_set_not_clear, - - timer_interrupt_req_set_not_clear, - - software_interrupt_req_set_not_clear, - - interrupt_pending_cur_priv, - interrupt_pending, - - wfi_resume, - - nmi_req_set_not_clear, - - nmi_pending, - - EN_debug, - RDY_debug); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_csr - input [11 : 0] read_csr_csr_addr; - output [64 : 0] read_csr; - - // value method read_csr_port2 - input [11 : 0] read_csr_port2_csr_addr; - output [64 : 0] read_csr_port2; - - // actionvalue method mav_read_csr - input [11 : 0] mav_read_csr_csr_addr; - input EN_mav_read_csr; - output [64 : 0] mav_read_csr; - - // actionvalue method mav_csr_write - input [11 : 0] mav_csr_write_csr_addr; - input [63 : 0] mav_csr_write_word; - input EN_mav_csr_write; - output [63 : 0] mav_csr_write; - - // value method read_misa - output [27 : 0] read_misa; - - // value method read_mstatus - output [63 : 0] read_mstatus; - - // value method read_ustatus - output [63 : 0] read_ustatus; - - // value method read_satp - output [63 : 0] read_satp; - - // actionvalue method csr_trap_actions - input [1 : 0] csr_trap_actions_from_priv; - input [63 : 0] csr_trap_actions_pc; - input csr_trap_actions_nmi; - input csr_trap_actions_interrupt; - input [3 : 0] csr_trap_actions_exc_code; - input [63 : 0] csr_trap_actions_xtval; - input EN_csr_trap_actions; - output [193 : 0] csr_trap_actions; - output RDY_csr_trap_actions; - - // actionvalue method csr_ret_actions - input [1 : 0] csr_ret_actions_from_priv; - input EN_csr_ret_actions; - output [129 : 0] csr_ret_actions; - output RDY_csr_ret_actions; - - // value method read_csr_minstret - output [63 : 0] read_csr_minstret; - - // action method csr_minstret_incr - input EN_csr_minstret_incr; - - // value method read_csr_mcycle - output [63 : 0] read_csr_mcycle; - - // value method read_csr_mtime - output [63 : 0] read_csr_mtime; - - // value method access_permitted_1 - input [1 : 0] access_permitted_1_priv; - input [11 : 0] access_permitted_1_csr_addr; - input access_permitted_1_read_not_write; - output access_permitted_1; - - // value method access_permitted_2 - input [1 : 0] access_permitted_2_priv; - input [11 : 0] access_permitted_2_csr_addr; - input access_permitted_2_read_not_write; - output access_permitted_2; - - // value method csr_counter_read_fault - input [1 : 0] csr_counter_read_fault_priv; - input [11 : 0] csr_counter_read_fault_csr_addr; - output csr_counter_read_fault; - - // value method csr_mip_read - output [63 : 0] csr_mip_read; - - // action method m_external_interrupt_req - input m_external_interrupt_req_set_not_clear; - - // action method s_external_interrupt_req - input s_external_interrupt_req_set_not_clear; - - // action method timer_interrupt_req - input timer_interrupt_req_set_not_clear; - - // action method software_interrupt_req - input software_interrupt_req_set_not_clear; - - // value method interrupt_pending - input [1 : 0] interrupt_pending_cur_priv; - output [4 : 0] interrupt_pending; - - // value method wfi_resume - output wfi_resume; - - // action method nmi_req - input nmi_req_set_not_clear; - - // value method nmi_pending - output nmi_pending; - - // action method debug - input EN_debug; - output RDY_debug; - - // signals for module outputs - wire [193 : 0] csr_trap_actions; - wire [129 : 0] csr_ret_actions; - wire [64 : 0] mav_read_csr, read_csr, read_csr_port2; - wire [63 : 0] csr_mip_read, - mav_csr_write, - read_csr_mcycle, - read_csr_minstret, - read_csr_mtime, - read_mstatus, - read_satp, - read_ustatus; - wire [27 : 0] read_misa; - wire [4 : 0] interrupt_pending; - wire RDY_csr_ret_actions, - RDY_csr_trap_actions, - RDY_debug, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - access_permitted_1, - access_permitted_2, - csr_counter_read_fault, - nmi_pending, - wfi_resume; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register csr_mstatus_rg_mstatus - reg [63 : 0] csr_mstatus_rg_mstatus; - reg [63 : 0] csr_mstatus_rg_mstatus$D_IN; - wire csr_mstatus_rg_mstatus$EN; - - // register rg_dcsr - reg [31 : 0] rg_dcsr; - wire [31 : 0] rg_dcsr$D_IN; - wire rg_dcsr$EN; - - // register rg_dpc - reg [63 : 0] rg_dpc; - wire [63 : 0] rg_dpc$D_IN; - wire rg_dpc$EN; - - // register rg_dscratch0 - reg [63 : 0] rg_dscratch0; - wire [63 : 0] rg_dscratch0$D_IN; - wire rg_dscratch0$EN; - - // register rg_dscratch1 - reg [63 : 0] rg_dscratch1; - wire [63 : 0] rg_dscratch1$D_IN; - wire rg_dscratch1$EN; - - // register rg_mcause - reg [4 : 0] rg_mcause; - reg [4 : 0] rg_mcause$D_IN; - wire rg_mcause$EN; - - // register rg_mcounteren - reg [2 : 0] rg_mcounteren; - wire [2 : 0] rg_mcounteren$D_IN; - wire rg_mcounteren$EN; - - // register rg_mcycle - reg [63 : 0] rg_mcycle; - wire [63 : 0] rg_mcycle$D_IN; - wire rg_mcycle$EN; - - // register rg_mepc - reg [63 : 0] rg_mepc; - wire [63 : 0] rg_mepc$D_IN; - wire rg_mepc$EN; - - // register rg_minstret - reg [63 : 0] rg_minstret; - wire [63 : 0] rg_minstret$D_IN; - wire rg_minstret$EN; - - // register rg_mscratch - reg [63 : 0] rg_mscratch; - wire [63 : 0] rg_mscratch$D_IN; - wire rg_mscratch$EN; - - // register rg_mtval - reg [63 : 0] rg_mtval; - wire [63 : 0] rg_mtval$D_IN; - wire rg_mtval$EN; - - // register rg_mtvec - reg [62 : 0] rg_mtvec; - wire [62 : 0] rg_mtvec$D_IN; - wire rg_mtvec$EN; - - // register rg_nmi - reg rg_nmi; - wire rg_nmi$D_IN, rg_nmi$EN; - - // register rg_nmi_vector - reg [63 : 0] rg_nmi_vector; - wire [63 : 0] rg_nmi_vector$D_IN; - wire rg_nmi_vector$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_tdata1 - reg [63 : 0] rg_tdata1; - wire [63 : 0] rg_tdata1$D_IN; - wire rg_tdata1$EN; - - // register rg_tdata2 - reg [63 : 0] rg_tdata2; - wire [63 : 0] rg_tdata2$D_IN; - wire rg_tdata2$EN; - - // register rg_tdata3 - reg [63 : 0] rg_tdata3; - wire [63 : 0] rg_tdata3$D_IN; - wire rg_tdata3$EN; - - // register rg_tselect - reg [63 : 0] rg_tselect; - wire [63 : 0] rg_tselect$D_IN; - wire rg_tselect$EN; - - // ports of submodule csr_mie - wire [63 : 0] csr_mie$fav_write, csr_mie$fav_write_wordxl, csr_mie$fv_read; - wire [27 : 0] csr_mie$fav_write_misa; - wire csr_mie$EN_fav_write, csr_mie$EN_reset; - - // ports of submodule csr_mip - wire [63 : 0] csr_mip$fav_write, csr_mip$fav_write_wordxl, csr_mip$fv_read; - wire [27 : 0] csr_mip$fav_write_misa; - wire csr_mip$EN_fav_write, - csr_mip$EN_reset, - csr_mip$m_external_interrupt_req_req, - csr_mip$s_external_interrupt_req_req, - csr_mip$software_interrupt_req_req, - csr_mip$timer_interrupt_req_req; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mtvec_reset_value, - soc_map$m_nmivec_reset_value; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_mcycle_incr, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_RL_rl_upd_minstret_csrrx, - CAN_FIRE_RL_rl_upd_minstret_incr, - CAN_FIRE_csr_minstret_incr, - CAN_FIRE_csr_ret_actions, - CAN_FIRE_csr_trap_actions, - CAN_FIRE_debug, - CAN_FIRE_m_external_interrupt_req, - CAN_FIRE_mav_csr_write, - CAN_FIRE_mav_read_csr, - CAN_FIRE_nmi_req, - CAN_FIRE_s_external_interrupt_req, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_software_interrupt_req, - CAN_FIRE_timer_interrupt_req, - WILL_FIRE_RL_rl_mcycle_incr, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_RL_rl_upd_minstret_csrrx, - WILL_FIRE_RL_rl_upd_minstret_incr, - WILL_FIRE_csr_minstret_incr, - WILL_FIRE_csr_ret_actions, - WILL_FIRE_csr_trap_actions, - WILL_FIRE_debug, - WILL_FIRE_m_external_interrupt_req, - WILL_FIRE_mav_csr_write, - WILL_FIRE_mav_read_csr, - WILL_FIRE_nmi_req, - WILL_FIRE_s_external_interrupt_req, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_software_interrupt_req, - WILL_FIRE_timer_interrupt_req; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_3, - MUX_rg_minstret$write_1__VAL_1, - MUX_rg_minstret$write_1__VAL_2; - wire [62 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2; - wire [4 : 0] MUX_rg_mcause$write_1__VAL_2, MUX_rg_mcause$write_1__VAL_3; - wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_2, - MUX_rg_mcause$write_1__SEL_2, - MUX_rg_mcounteren$write_1__SEL_1, - MUX_rg_mepc$write_1__SEL_1, - MUX_rg_mtval$write_1__SEL_1, - MUX_rg_mtvec$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2, - MUX_rg_tdata1$write_1__SEL_1, - MUX_rw_minstret$wset_1__SEL_1; - - // remaining internal signals - reg [63 : 0] IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582, - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440, - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170, - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305; - wire [65 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d880; - wire [63 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862, - _theResult___fst__h8385, - _theResult___fst__h8586, - csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855, - exc_pc___1__h7373, - exc_pc__h7109, - exc_pc__h7320, - mask__h8406, - mask__h8423, - result__h5433, - v__h4528, - v__h4590, - v__h4746, - val__h8424, - vector_offset__h7321, - wordxl1__h4016, - x__h5891, - x__h8214, - x__h8215, - x__h8405, - x__h8418, - x__h8435, - y__h8419, - y__h8436; - wire [22 : 0] fixed_up_val_23__h4057, - fixed_up_val_23__h6519, - fixed_up_val_23__h8277; - wire [5 : 0] ie_from_x__h8369, pie_from_x__h8370; - wire [3 : 0] IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1137, - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1139, - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1141, - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1143, - exc_code__h8056; - wire [1 : 0] mpp__h7414, to_y__h8585; - wire NOT_access_permitted_1_csr_addr_ULT_0xC03_81_8_ETC___d947, - NOT_access_permitted_2_csr_addr_ULT_0xC03_52_5_ETC___d1017, - NOT_cfg_verbosity_read__49_ULE_1_50___d551, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1101, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1106, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1111, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1116, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1121, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1126, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1131, - NOT_csr_trap_actions_nmi_10_AND_csr_trap_actio_ETC___d787, - b__h8422, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1055, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1060, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1065, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1070, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1075, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1080, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1085, - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1090, - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d838, - mav_csr_write_csr_addr_ULE_0x33F___d448, - mav_csr_write_csr_addr_ULE_0xB1F___d444, - mav_csr_write_csr_addr_ULT_0x323_47_OR_NOT_mav_ETC___d547, - mav_csr_write_csr_addr_ULT_0x323___d447, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d467, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d477, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d481, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d486, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d488, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d492, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d494, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d500, - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d502, - mav_csr_write_csr_addr_ULT_0xB03___d443; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_csr - assign read_csr = - { read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F || - read_csr_csr_addr == 12'hC00 || - read_csr_csr_addr == 12'hC02 || - read_csr_csr_addr == 12'hF11 || - read_csr_csr_addr == 12'hF12 || - read_csr_csr_addr == 12'hF13 || - read_csr_csr_addr == 12'hF14 || - read_csr_csr_addr == 12'h300 || - read_csr_csr_addr == 12'h301 || - read_csr_csr_addr == 12'h304 || - read_csr_csr_addr == 12'h305 || - read_csr_csr_addr == 12'h306 || - read_csr_csr_addr == 12'h340 || - read_csr_csr_addr == 12'h341 || - read_csr_csr_addr == 12'h342 || - read_csr_csr_addr == 12'h343 || - read_csr_csr_addr == 12'h344 || - read_csr_csr_addr == 12'hB00 || - read_csr_csr_addr == 12'hB02 || - read_csr_csr_addr == 12'h7A0 || - read_csr_csr_addr == 12'h7A1 || - read_csr_csr_addr == 12'h7A2 || - read_csr_csr_addr == 12'h7A3, - (read_csr_csr_addr >= 12'hC03 && - read_csr_csr_addr <= 12'hC1F || - read_csr_csr_addr >= 12'hB03 && - read_csr_csr_addr <= 12'hB1F || - read_csr_csr_addr >= 12'h323 && - read_csr_csr_addr <= 12'h33F) ? - 64'd0 : - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 } ; - - // value method read_csr_port2 - assign read_csr_port2 = - { read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F || - read_csr_port2_csr_addr == 12'hC00 || - read_csr_port2_csr_addr == 12'hC02 || - read_csr_port2_csr_addr == 12'hF11 || - read_csr_port2_csr_addr == 12'hF12 || - read_csr_port2_csr_addr == 12'hF13 || - read_csr_port2_csr_addr == 12'hF14 || - read_csr_port2_csr_addr == 12'h300 || - read_csr_port2_csr_addr == 12'h301 || - read_csr_port2_csr_addr == 12'h304 || - read_csr_port2_csr_addr == 12'h305 || - read_csr_port2_csr_addr == 12'h306 || - read_csr_port2_csr_addr == 12'h340 || - read_csr_port2_csr_addr == 12'h341 || - read_csr_port2_csr_addr == 12'h342 || - read_csr_port2_csr_addr == 12'h343 || - read_csr_port2_csr_addr == 12'h344 || - read_csr_port2_csr_addr == 12'hB00 || - read_csr_port2_csr_addr == 12'hB02 || - read_csr_port2_csr_addr == 12'h7A0 || - read_csr_port2_csr_addr == 12'h7A1 || - read_csr_port2_csr_addr == 12'h7A2 || - read_csr_port2_csr_addr == 12'h7A3, - (read_csr_port2_csr_addr >= 12'hC03 && - read_csr_port2_csr_addr <= 12'hC1F || - read_csr_port2_csr_addr >= 12'hB03 && - read_csr_port2_csr_addr <= 12'hB1F || - read_csr_port2_csr_addr >= 12'h323 && - read_csr_port2_csr_addr <= 12'h33F) ? - 64'd0 : - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 } ; - - // actionvalue method mav_read_csr - assign mav_read_csr = - { mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F || - mav_read_csr_csr_addr == 12'hC00 || - mav_read_csr_csr_addr == 12'hC02 || - mav_read_csr_csr_addr == 12'hF11 || - mav_read_csr_csr_addr == 12'hF12 || - mav_read_csr_csr_addr == 12'hF13 || - mav_read_csr_csr_addr == 12'hF14 || - mav_read_csr_csr_addr == 12'h300 || - mav_read_csr_csr_addr == 12'h301 || - mav_read_csr_csr_addr == 12'h304 || - mav_read_csr_csr_addr == 12'h305 || - mav_read_csr_csr_addr == 12'h306 || - mav_read_csr_csr_addr == 12'h340 || - mav_read_csr_csr_addr == 12'h341 || - mav_read_csr_csr_addr == 12'h342 || - mav_read_csr_csr_addr == 12'h343 || - mav_read_csr_csr_addr == 12'h344 || - mav_read_csr_csr_addr == 12'hB00 || - mav_read_csr_csr_addr == 12'hB02 || - mav_read_csr_csr_addr == 12'h7A0 || - mav_read_csr_csr_addr == 12'h7A1 || - mav_read_csr_csr_addr == 12'h7A2 || - mav_read_csr_csr_addr == 12'h7A3, - (mav_read_csr_csr_addr >= 12'hC03 && - mav_read_csr_csr_addr <= 12'hC1F || - mav_read_csr_csr_addr >= 12'hB03 && - mav_read_csr_csr_addr <= 12'hB1F || - mav_read_csr_csr_addr >= 12'h323 && - mav_read_csr_csr_addr <= 12'h33F) ? - 64'd0 : - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 } ; - assign CAN_FIRE_mav_read_csr = 1'd1 ; - assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ; - - // actionvalue method mav_csr_write - assign mav_csr_write = - (!mav_csr_write_csr_addr_ULT_0xB03___d443 && - mav_csr_write_csr_addr_ULE_0xB1F___d444 || - !mav_csr_write_csr_addr_ULT_0x323___d447 && - mav_csr_write_csr_addr_ULE_0x33F___d448 || - mav_csr_write_csr_addr == 12'hF11 || - mav_csr_write_csr_addr == 12'hF12 || - mav_csr_write_csr_addr == 12'hF13 || - mav_csr_write_csr_addr == 12'hF14) ? - 64'd0 : - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 ; - assign CAN_FIRE_mav_csr_write = 1'd1 ; - assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ; - - // value method read_misa - assign read_misa = 28'd135270661 ; - - // value method read_mstatus - assign read_mstatus = csr_mstatus_rg_mstatus ; - - // value method read_ustatus - assign read_ustatus = - { 59'd0, - csr_mstatus_rg_mstatus[4], - 3'd0, - csr_mstatus_rg_mstatus[0] } ; - - // value method read_satp - assign read_satp = 64'hAAAAAAAAAAAAAAAA ; - - // actionvalue method csr_trap_actions - assign csr_trap_actions = { x__h5891, x__h8214, x__h8215, 2'b11 } ; - assign RDY_csr_trap_actions = 1'd1 ; - assign CAN_FIRE_csr_trap_actions = 1'd1 ; - assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; - - // actionvalue method csr_ret_actions - assign csr_ret_actions = - { rg_mepc, - IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d880 } ; - assign RDY_csr_ret_actions = 1'd1 ; - assign CAN_FIRE_csr_ret_actions = 1'd1 ; - assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ; - - // value method read_csr_minstret - assign read_csr_minstret = rg_minstret ; - - // action method csr_minstret_incr - assign CAN_FIRE_csr_minstret_incr = 1'd1 ; - assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ; - - // value method read_csr_mcycle - assign read_csr_mcycle = rg_mcycle ; - - // value method read_csr_mtime - assign read_csr_mtime = rg_mcycle ; - - // value method access_permitted_1 - assign access_permitted_1 = - NOT_access_permitted_1_csr_addr_ULT_0xC03_81_8_ETC___d947 && - (access_permitted_1_read_not_write || - access_permitted_1_csr_addr[11:10] != 2'b11) ; - - // value method access_permitted_2 - assign access_permitted_2 = - NOT_access_permitted_2_csr_addr_ULT_0xC03_52_5_ETC___d1017 && - (access_permitted_2_read_not_write || - access_permitted_2_csr_addr[11:10] != 2'b11) ; - - // value method csr_counter_read_fault - assign csr_counter_read_fault = - (csr_counter_read_fault_priv == 2'b01 || - csr_counter_read_fault_priv == 2'b0) && - (csr_counter_read_fault_csr_addr == 12'hC00 && - !rg_mcounteren[0] || - csr_counter_read_fault_csr_addr == 12'hC01 && - !rg_mcounteren[1] || - csr_counter_read_fault_csr_addr == 12'hC02 && - !rg_mcounteren[2] || - csr_counter_read_fault_csr_addr >= 12'hC03 && - csr_counter_read_fault_csr_addr <= 12'hC1F) ; - - // value method csr_mip_read - assign csr_mip_read = csr_mip$fv_read ; - - // action method m_external_interrupt_req - assign CAN_FIRE_m_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_m_external_interrupt_req = 1'd1 ; - - // action method s_external_interrupt_req - assign CAN_FIRE_s_external_interrupt_req = 1'd1 ; - assign WILL_FIRE_s_external_interrupt_req = 1'd1 ; - - // action method timer_interrupt_req - assign CAN_FIRE_timer_interrupt_req = 1'd1 ; - assign WILL_FIRE_timer_interrupt_req = 1'd1 ; - - // action method software_interrupt_req - assign CAN_FIRE_software_interrupt_req = 1'd1 ; - assign WILL_FIRE_software_interrupt_req = 1'd1 ; - - // value method interrupt_pending - assign interrupt_pending = - { csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1090, - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1131 ? - 4'd4 : - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1143 } ; - - // value method wfi_resume - assign wfi_resume = (csr_mip$fv_read & csr_mie$fv_read) != 64'd0 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // value method nmi_pending - assign nmi_pending = rg_nmi ; - - // action method debug - assign RDY_debug = 1'd1 ; - assign CAN_FIRE_debug = 1'd1 ; - assign WILL_FIRE_debug = EN_debug ; - - // submodule csr_mie - mkCSR_MIE csr_mie(.CLK(CLK), - .RST_N(RST_N), - .fav_write_misa(csr_mie$fav_write_misa), - .fav_write_wordxl(csr_mie$fav_write_wordxl), - .EN_reset(csr_mie$EN_reset), - .EN_fav_write(csr_mie$EN_fav_write), - .fv_read(csr_mie$fv_read), - .fav_write(csr_mie$fav_write)); - - // submodule csr_mip - mkCSR_MIP csr_mip(.CLK(CLK), - .RST_N(RST_N), - .fav_write_misa(csr_mip$fav_write_misa), - .fav_write_wordxl(csr_mip$fav_write_wordxl), - .m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req), - .s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req), - .software_interrupt_req_req(csr_mip$software_interrupt_req_req), - .timer_interrupt_req_req(csr_mip$timer_interrupt_req_req), - .EN_reset(csr_mip$EN_reset), - .EN_fav_write(csr_mip$EN_fav_write), - .fv_read(csr_mip$fv_read), - .fav_write(csr_mip$fav_write)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(soc_map$m_mtvec_reset_value), - .m_nmivec_reset_value(soc_map$m_nmivec_reset_value)); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = !rg_state ; - assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_mcycle_incr - assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; - assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ; - - // rule RL_rl_upd_minstret_csrrx - assign CAN_FIRE_RL_rl_upd_minstret_csrrx = - MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ; - assign WILL_FIRE_RL_rl_upd_minstret_csrrx = - CAN_FIRE_RL_rl_upd_minstret_csrrx ; - - // rule RL_rl_upd_minstret_incr - assign CAN_FIRE_RL_rl_upd_minstret_incr = - !CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ; - assign WILL_FIRE_RL_rl_upd_minstret_incr = - CAN_FIRE_RL_rl_upd_minstret_incr ; - - // inputs to muxes for submodule ports - assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453 ; - assign MUX_rg_mcause$write_1__SEL_2 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d481 ; - assign MUX_rg_mcounteren$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474 ; - assign MUX_rg_mepc$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479 ; - assign MUX_rg_mtval$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d486 ; - assign MUX_rg_mtvec$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; - assign MUX_rg_tdata1$write_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496 ; - assign MUX_rw_minstret$wset_1__SEL_1 = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d492 ; - assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 = - { 41'd1024, fixed_up_val_23__h8277 } ; - assign MUX_rg_mcause$write_1__VAL_2 = - { mav_csr_write_word[63], mav_csr_write_word[3:0] } ; - assign MUX_rg_mcause$write_1__VAL_3 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - exc_code__h8056 } ; - assign MUX_rg_minstret$write_1__VAL_1 = - MUX_rw_minstret$wset_1__SEL_1 ? mav_csr_write_word : 64'd0 ; - assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ; - assign MUX_rg_mtvec$write_1__VAL_1 = - { mav_csr_write_word[63:2], mav_csr_write_word[0] } ; - assign MUX_rg_mtvec$write_1__VAL_2 = - { soc_map$m_mtvec_reset_value[63:2], - soc_map$m_mtvec_reset_value[0] } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register csr_mstatus_rg_mstatus - always@(WILL_FIRE_RL_rl_reset_start or - MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 or - wordxl1__h4016 or - EN_csr_ret_actions or - MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 or - EN_csr_trap_actions or x__h8214) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: - csr_mstatus_rg_mstatus$D_IN = 64'h0000000200000000; - MUX_csr_mstatus_rg_mstatus$write_1__SEL_2: - csr_mstatus_rg_mstatus$D_IN = wordxl1__h4016; - EN_csr_ret_actions: - csr_mstatus_rg_mstatus$D_IN = - MUX_csr_mstatus_rg_mstatus$write_1__VAL_3; - EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = x__h8214; - default: csr_mstatus_rg_mstatus$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign csr_mstatus_rg_mstatus$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453 || - EN_csr_trap_actions || - EN_csr_ret_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_dcsr - assign rg_dcsr$D_IN = 32'h0 ; - assign rg_dcsr$EN = 1'b0 ; - - // register rg_dpc - assign rg_dpc$D_IN = 64'h0 ; - assign rg_dpc$EN = 1'b0 ; - - // register rg_dscratch0 - assign rg_dscratch0$D_IN = 64'h0 ; - assign rg_dscratch0$EN = 1'b0 ; - - // register rg_dscratch1 - assign rg_dscratch1$D_IN = 64'h0 ; - assign rg_dscratch1$EN = 1'b0 ; - - // register rg_mcause - always@(WILL_FIRE_RL_rl_reset_start or - MUX_rg_mcause$write_1__SEL_2 or - MUX_rg_mcause$write_1__VAL_2 or - EN_csr_trap_actions or MUX_rg_mcause$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0; - MUX_rg_mcause$write_1__SEL_2: - rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2; - EN_csr_trap_actions: rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3; - default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_mcause$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d481 || - EN_csr_trap_actions || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcounteren - assign rg_mcounteren$D_IN = - MUX_rg_mcounteren$write_1__SEL_1 ? - mav_csr_write_word[2:0] : - 3'd0 ; - assign rg_mcounteren$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_mcycle - assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ; - assign rg_mcycle$EN = 1'd1 ; - - // register rg_mepc - assign rg_mepc$D_IN = - MUX_rg_mepc$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_pc ; - assign rg_mepc$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479 || - EN_csr_trap_actions ; - - // register rg_minstret - assign rg_minstret$D_IN = - WILL_FIRE_RL_rl_upd_minstret_csrrx ? - MUX_rg_minstret$write_1__VAL_1 : - MUX_rg_minstret$write_1__VAL_2 ; - assign rg_minstret$EN = - WILL_FIRE_RL_rl_upd_minstret_csrrx || - WILL_FIRE_RL_rl_upd_minstret_incr ; - - // register rg_mscratch - assign rg_mscratch$D_IN = mav_csr_write_word ; - assign rg_mscratch$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d477 ; - - // register rg_mtval - assign rg_mtval$D_IN = - MUX_rg_mtval$write_1__SEL_1 ? - mav_csr_write_word : - csr_trap_actions_xtval ; - assign rg_mtval$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d486 || - EN_csr_trap_actions ; - - // register rg_mtvec - assign rg_mtvec$D_IN = - MUX_rg_mtvec$write_1__SEL_1 ? - MUX_rg_mtvec$write_1__VAL_1 : - MUX_rg_mtvec$write_1__VAL_2 ; - assign rg_mtvec$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_nmi - assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ; - assign rg_nmi$EN = 1'b1 ; - - // register rg_nmi_vector - assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value ; - assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_state - assign rg_state$D_IN = !EN_server_reset_request_put ; - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata1 - assign rg_tdata1$D_IN = - MUX_rg_tdata1$write_1__SEL_1 ? result__h5433 : 64'd0 ; - assign rg_tdata1$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496 || - WILL_FIRE_RL_rl_reset_start ; - - // register rg_tdata2 - assign rg_tdata2$D_IN = mav_csr_write_word ; - assign rg_tdata2$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d500 ; - - // register rg_tdata3 - assign rg_tdata3$D_IN = mav_csr_write_word ; - assign rg_tdata3$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d502 ; - - // register rg_tselect - assign rg_tselect$D_IN = 64'd0 ; - assign rg_tselect$EN = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d494 || - WILL_FIRE_RL_rl_reset_start ; - - // submodule csr_mie - assign csr_mie$fav_write_misa = 28'd135270661 ; - assign csr_mie$fav_write_wordxl = mav_csr_write_word ; - assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mie$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d467 ; - - // submodule csr_mip - assign csr_mip$fav_write_misa = 28'd135270661 ; - assign csr_mip$fav_write_wordxl = mav_csr_write_word ; - assign csr_mip$m_external_interrupt_req_req = - m_external_interrupt_req_set_not_clear ; - assign csr_mip$s_external_interrupt_req_req = - s_external_interrupt_req_set_not_clear ; - assign csr_mip$software_interrupt_req_req = - software_interrupt_req_set_not_clear ; - assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; - assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; - assign csr_mip$EN_fav_write = - EN_mav_csr_write && - mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d488 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1137 = - (!csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ? - 4'd3 : - 4'd11 ; - assign IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1139 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1106 ? - 4'd9 : - (NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1101 ? - 4'd7 : - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1137) ; - assign IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1141 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1116 ? - 4'd5 : - (NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1111 ? - 4'd1 : - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1139) ; - assign IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1143 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1126 ? - 4'd0 : - (NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1121 ? - 4'd8 : - IF_NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_N_ETC___d1141) ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862 = - (csr_ret_actions_from_priv == 2'b11) ? - _theResult___fst__h8385 : - _theResult___fst__h8586 ; - assign IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d880 = - (csr_ret_actions_from_priv == 2'b11) ? - { csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[12:11], - _theResult___fst__h8385 } : - { to_y__h8585, _theResult___fst__h8586 } ; - assign NOT_access_permitted_1_csr_addr_ULT_0xC03_81_8_ETC___d947 = - (access_permitted_1_csr_addr >= 12'hC03 && - access_permitted_1_csr_addr <= 12'hC1F || - access_permitted_1_csr_addr >= 12'hB03 && - access_permitted_1_csr_addr <= 12'hB1F || - access_permitted_1_csr_addr >= 12'h323 && - access_permitted_1_csr_addr <= 12'h33F || - access_permitted_1_csr_addr == 12'hC00 || - access_permitted_1_csr_addr == 12'hC02 || - access_permitted_1_csr_addr == 12'hF11 || - access_permitted_1_csr_addr == 12'hF12 || - access_permitted_1_csr_addr == 12'hF13 || - access_permitted_1_csr_addr == 12'hF14 || - access_permitted_1_csr_addr == 12'h300 || - access_permitted_1_csr_addr == 12'h301 || - access_permitted_1_csr_addr == 12'h304 || - access_permitted_1_csr_addr == 12'h305 || - access_permitted_1_csr_addr == 12'h306 || - access_permitted_1_csr_addr == 12'h340 || - access_permitted_1_csr_addr == 12'h341 || - access_permitted_1_csr_addr == 12'h342 || - access_permitted_1_csr_addr == 12'h343 || - access_permitted_1_csr_addr == 12'h344 || - access_permitted_1_csr_addr == 12'hB00 || - access_permitted_1_csr_addr == 12'hB02 || - access_permitted_1_csr_addr == 12'h7A0 || - access_permitted_1_csr_addr == 12'h7A1 || - access_permitted_1_csr_addr == 12'h7A2 || - access_permitted_1_csr_addr == 12'h7A3) && - access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] && - (access_permitted_1_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_access_permitted_2_csr_addr_ULT_0xC03_52_5_ETC___d1017 = - (access_permitted_2_csr_addr >= 12'hC03 && - access_permitted_2_csr_addr <= 12'hC1F || - access_permitted_2_csr_addr >= 12'hB03 && - access_permitted_2_csr_addr <= 12'hB1F || - access_permitted_2_csr_addr >= 12'h323 && - access_permitted_2_csr_addr <= 12'h33F || - access_permitted_2_csr_addr == 12'hC00 || - access_permitted_2_csr_addr == 12'hC02 || - access_permitted_2_csr_addr == 12'hF11 || - access_permitted_2_csr_addr == 12'hF12 || - access_permitted_2_csr_addr == 12'hF13 || - access_permitted_2_csr_addr == 12'hF14 || - access_permitted_2_csr_addr == 12'h300 || - access_permitted_2_csr_addr == 12'h301 || - access_permitted_2_csr_addr == 12'h304 || - access_permitted_2_csr_addr == 12'h305 || - access_permitted_2_csr_addr == 12'h306 || - access_permitted_2_csr_addr == 12'h340 || - access_permitted_2_csr_addr == 12'h341 || - access_permitted_2_csr_addr == 12'h342 || - access_permitted_2_csr_addr == 12'h343 || - access_permitted_2_csr_addr == 12'h344 || - access_permitted_2_csr_addr == 12'hB00 || - access_permitted_2_csr_addr == 12'hB02 || - access_permitted_2_csr_addr == 12'h7A0 || - access_permitted_2_csr_addr == 12'h7A1 || - access_permitted_2_csr_addr == 12'h7A2 || - access_permitted_2_csr_addr == 12'h7A3) && - access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] && - (access_permitted_2_csr_addr != 12'h180 || - !csr_mstatus_rg_mstatus[20]) ; - assign NOT_cfg_verbosity_read__49_ULE_1_50___d551 = cfg_verbosity > 4'd1 ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1101 = - (!csr_mip$fv_read[11] || !csr_mie$fv_read[11] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) && - (!csr_mip$fv_read[3] || !csr_mie$fv_read[3] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1106 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1101 && - (!csr_mip$fv_read[7] || !csr_mie$fv_read[7] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1111 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1106 && - (!csr_mip$fv_read[9] || !csr_mie$fv_read[9] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1116 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1111 && - (!csr_mip$fv_read[1] || !csr_mie$fv_read[1] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1121 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1116 && - (!csr_mip$fv_read[5] || !csr_mie$fv_read[5] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1126 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1121 && - (!csr_mip$fv_read[8] || !csr_mie$fv_read[8] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1131 = - NOT_csr_mip_fv_read__48_BIT_11_044_091_OR_NOT__ETC___d1126 && - (!csr_mip$fv_read[0] || !csr_mie$fv_read[0] || - interrupt_pending_cur_priv == 2'b11 && - !csr_mstatus_rg_mstatus[3]) ; - assign NOT_csr_trap_actions_nmi_10_AND_csr_trap_actio_ETC___d787 = - !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8056 != 4'd0 && - exc_code__h8056 != 4'd1 && - exc_code__h8056 != 4'd2 && - exc_code__h8056 != 4'd3 && - exc_code__h8056 != 4'd4 && - exc_code__h8056 != 4'd5 && - exc_code__h8056 != 4'd6 && - exc_code__h8056 != 4'd7 && - exc_code__h8056 != 4'd8 && - exc_code__h8056 != 4'd9 && - exc_code__h8056 != 4'd10 && - exc_code__h8056 != 4'd11 ; - assign _theResult___fst__h8385 = - { csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[63:13], - 2'd0, - csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[10:0] } ; - assign _theResult___fst__h8586 = - { csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[63:9], - 1'd0, - csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[7:0] } ; - assign b__h8422 = csr_mstatus_rg_mstatus[pie_from_x__h8370] ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1055 = - csr_mip$fv_read[11] && csr_mie$fv_read[11] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) || - csr_mip$fv_read[3] && csr_mie$fv_read[3] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1060 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1055 || - csr_mip$fv_read[7] && csr_mie$fv_read[7] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1065 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1060 || - csr_mip$fv_read[9] && csr_mie$fv_read[9] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1070 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1065 || - csr_mip$fv_read[1] && csr_mie$fv_read[1] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1075 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1070 || - csr_mip$fv_read[5] && csr_mie$fv_read[5] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1080 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1075 || - csr_mip$fv_read[8] && csr_mie$fv_read[8] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1085 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1080 || - csr_mip$fv_read[0] && csr_mie$fv_read[0] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1090 = - csr_mip_fv_read__48_BIT_11_044_AND_csr_mie_fv__ETC___d1085 || - csr_mip$fv_read[4] && csr_mie$fv_read[4] && - (interrupt_pending_cur_priv != 2'b11 || - csr_mstatus_rg_mstatus[3]) ; - assign csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855 = - x__h8418 | mask__h8406 ; - assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d838 = - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 != 4'd0 && - exc_code__h8056 != 4'd1 && - exc_code__h8056 != 4'd2 && - exc_code__h8056 != 4'd3 && - exc_code__h8056 != 4'd4 && - exc_code__h8056 != 4'd5 && - exc_code__h8056 != 4'd6 && - exc_code__h8056 != 4'd7 && - exc_code__h8056 != 4'd8 && - exc_code__h8056 != 4'd9 && - exc_code__h8056 != 4'd11 && - exc_code__h8056 != 4'd12 && - exc_code__h8056 != 4'd13 && - exc_code__h8056 != 4'd15 ; - assign exc_code__h8056 = - csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; - assign exc_pc___1__h7373 = exc_pc__h7320 + vector_offset__h7321 ; - assign exc_pc__h7109 = { rg_mtvec[62:1], 2'd0 } ; - assign exc_pc__h7320 = - csr_trap_actions_nmi ? rg_nmi_vector : exc_pc__h7109 ; - assign fixed_up_val_23__h4057 = - { mav_csr_write_word[22:17], - 4'd0, - (mav_csr_write_word[12:11] == 2'b11) ? - mav_csr_write_word[12:11] : - 2'b0, - mav_csr_write_word[10:9], - 1'd0, - mav_csr_write_word[7:6], - 2'd0, - mav_csr_write_word[3:2], - 2'd0 } ; - assign fixed_up_val_23__h6519 = - { csr_mstatus_rg_mstatus[22:17], - 4'd0, - mpp__h7414, - csr_mstatus_rg_mstatus[10:9], - 1'd0, - csr_mstatus_rg_mstatus[3], - csr_mstatus_rg_mstatus[6], - 3'd0, - csr_mstatus_rg_mstatus[2], - 2'd0 } ; - assign fixed_up_val_23__h8277 = - { IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[22:17], - 4'd0, - (IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[12:11] == - 2'b11) ? - IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[12:11] : - 2'b0, - IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[10:9], - 1'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[7:6], - 2'd0, - IF_csr_ret_actions_from_priv_EQ_0b11_42_THEN_c_ETC___d862[3:2], - 2'd0 } ; - assign ie_from_x__h8369 = { 4'd0, csr_ret_actions_from_priv } ; - assign mask__h8406 = 64'd1 << pie_from_x__h8370 ; - assign mask__h8423 = 64'd1 << ie_from_x__h8369 ; - assign mav_csr_write_csr_addr_ULE_0x33F___d448 = - mav_csr_write_csr_addr <= 12'h33F ; - assign mav_csr_write_csr_addr_ULE_0xB1F___d444 = - mav_csr_write_csr_addr <= 12'hB1F ; - assign mav_csr_write_csr_addr_ULT_0x323_47_OR_NOT_mav_ETC___d547 = - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr != 12'hF11 && - mav_csr_write_csr_addr != 12'hF12 && - mav_csr_write_csr_addr != 12'hF13 && - mav_csr_write_csr_addr != 12'hF14 && - mav_csr_write_csr_addr != 12'h300 && - mav_csr_write_csr_addr != 12'h301 && - mav_csr_write_csr_addr != 12'h304 && - mav_csr_write_csr_addr != 12'h305 && - mav_csr_write_csr_addr != 12'h306 && - mav_csr_write_csr_addr != 12'h340 && - mav_csr_write_csr_addr != 12'h341 && - mav_csr_write_csr_addr != 12'h342 && - mav_csr_write_csr_addr != 12'h343 && - mav_csr_write_csr_addr != 12'h344 && - mav_csr_write_csr_addr != 12'hB00 && - mav_csr_write_csr_addr != 12'hB02 && - mav_csr_write_csr_addr != 12'h7A0 && - mav_csr_write_csr_addr != 12'h7A1 && - mav_csr_write_csr_addr != 12'h7A2 && - mav_csr_write_csr_addr != 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0x323___d447 = - mav_csr_write_csr_addr < 12'h323 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d453 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h300 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d467 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h304 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d469 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h305 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d474 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h306 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d477 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h340 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d479 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h341 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d481 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h342 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d486 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h343 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d488 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h344 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d492 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'hB02 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d494 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h7A0 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d496 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h7A1 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d500 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h7A2 ; - assign mav_csr_write_csr_addr_ULT_0xB03_43_OR_NOT_mav_ETC___d502 = - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - (mav_csr_write_csr_addr_ULT_0x323___d447 || - !mav_csr_write_csr_addr_ULE_0x33F___d448) && - mav_csr_write_csr_addr == 12'h7A3 ; - assign mav_csr_write_csr_addr_ULT_0xB03___d443 = - mav_csr_write_csr_addr < 12'hB03 ; - assign mpp__h7414 = - (csr_trap_actions_from_priv == 2'b11) ? - csr_trap_actions_from_priv : - 2'b0 ; - assign pie_from_x__h8370 = { 4'd1, csr_ret_actions_from_priv } ; - assign result__h5433 = { 4'd0, mav_csr_write_word[59:0] } ; - assign to_y__h8585 = - { 1'b0, - csr_mstatus_rg_mstatus_33_AND_INV_1_SL_0_CONCA_ETC___d855[8] } ; - assign v__h4528 = - { mav_csr_write_word[63:2], 1'b0, mav_csr_write_word[0] } ; - assign v__h4590 = { 61'd0, mav_csr_write_word[2:0] } ; - assign v__h4746 = - { mav_csr_write_word[63], 59'd0, mav_csr_write_word[3:0] } ; - assign val__h8424 = { 63'd0, b__h8422 } << ie_from_x__h8369 ; - assign vector_offset__h7321 = { 58'd0, csr_trap_actions_exc_code, 2'd0 } ; - assign wordxl1__h4016 = { 41'd1024, fixed_up_val_23__h4057 } ; - assign x__h5891 = - (csr_trap_actions_interrupt && !csr_trap_actions_nmi && - rg_mtvec[0]) ? - exc_pc___1__h7373 : - exc_pc__h7320 ; - assign x__h8214 = { 41'd1024, fixed_up_val_23__h6519 } ; - assign x__h8215 = - { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - 59'd0, - exc_code__h8056 } ; - assign x__h8405 = x__h8435 | val__h8424 ; - assign x__h8418 = x__h8405 & y__h8419 ; - assign x__h8435 = csr_mstatus_rg_mstatus & y__h8436 ; - assign y__h8419 = ~mask__h8406 ; - assign y__h8436 = ~mask__h8423 ; - always@(read_csr_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_csr_addr) - 12'h300: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - 64'h8000000000101105; - 12'h304: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_mscratch; - 12'h341: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = rg_mepc; - 12'h342: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_mtval; - 12'h344: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_tselect; - 12'h7A1: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_tdata1; - 12'h7A2: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_minstret; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = 64'd0; - default: IF_read_csr_csr_addr_EQ_0xC00_0_THEN_rg_mcycle_ETC___d170 = - rg_tdata3; - endcase - end - always@(read_csr_port2_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (read_csr_port2_csr_addr) - 12'h300: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - 64'h8000000000101105; - 12'h304: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - csr_mie$fv_read; - 12'h305: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_mscratch; - 12'h341: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = rg_mepc; - 12'h342: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_mtval; - 12'h344: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - csr_mip$fv_read; - 12'h7A0: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_tselect; - 12'h7A1: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_tdata1; - 12'h7A2: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_minstret; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = 64'd0; - default: IF_read_csr_port2_csr_addr_EQ_0xC00_85_THEN_rg_ETC___d305 = - rg_tdata3; - endcase - end - always@(mav_read_csr_csr_addr or - rg_tdata3 or - csr_mstatus_rg_mstatus or - csr_mie$fv_read or - rg_mtvec or - rg_mcounteren or - rg_mscratch or - rg_mepc or - rg_mcause or - rg_mtval or - csr_mip$fv_read or - rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret) - begin - case (mav_read_csr_csr_addr) - 12'h300: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - csr_mstatus_rg_mstatus; - 12'h301: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - 64'h8000000000101105; - 12'h304: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - csr_mie$fv_read; - 12'h305: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }; - 12'h306: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - { 61'd0, rg_mcounteren }; - 12'h340: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_mscratch; - 12'h341: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = rg_mepc; - 12'h342: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - { rg_mcause[4], 59'd0, rg_mcause[3:0] }; - 12'h343: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_mtval; - 12'h344: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - csr_mip$fv_read; - 12'h7A0: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_tselect; - 12'h7A1: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_tdata1; - 12'h7A2: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_tdata2; - 12'hB00, 12'hC00: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_mcycle; - 12'hB02, 12'hC02: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_minstret; - 12'hF11, 12'hF12, 12'hF13, 12'hF14: - IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = 64'd0; - default: IF_mav_read_csr_csr_addr_EQ_0xC00_20_THEN_rg_m_ETC___d440 = - rg_tdata3; - endcase - end - always@(mav_csr_write_csr_addr or - wordxl1__h4016 or - csr_mie$fav_write or - v__h4528 or - v__h4590 or - mav_csr_write_word or - v__h4746 or csr_mip$fav_write or result__h5433) - begin - case (mav_csr_write_csr_addr) - 12'h300: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - wordxl1__h4016; - 12'h301, 12'h7A0: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = 64'd0; - 12'h304: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - csr_mie$fav_write; - 12'h305: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - v__h4528; - 12'h306: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - v__h4590; - 12'h340, 12'h341, 12'h343, 12'h7A2, 12'h7A3, 12'hB00, 12'hB02: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - mav_csr_write_word; - 12'h342: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - v__h4746; - 12'h344: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - csr_mip$fav_write; - 12'h7A1: - IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - result__h5433; - default: IF_mav_csr_write_csr_addr_EQ_0x300_52_THEN_102_ETC___d582 = - 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 64'h0000000200000000; - rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (csr_mstatus_rg_mstatus$EN) - csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY - csr_mstatus_rg_mstatus$D_IN; - if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN; - if (rg_minstret$EN) - rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN; - if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN; - if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN; - if (rg_dscratch0$EN) - rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN; - if (rg_dscratch1$EN) - rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN; - if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN; - if (rg_mcounteren$EN) - rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN; - if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN; - if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN; - if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN; - if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN; - if (rg_nmi_vector$EN) - rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN; - if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN; - if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN; - if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN; - if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - csr_mstatus_rg_mstatus = 64'hAAAAAAAAAAAAAAAA; - rg_dcsr = 32'hAAAAAAAA; - rg_dpc = 64'hAAAAAAAAAAAAAAAA; - rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA; - rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA; - rg_mcause = 5'h0A; - rg_mcounteren = 3'h2; - rg_mcycle = 64'hAAAAAAAAAAAAAAAA; - rg_mepc = 64'hAAAAAAAAAAAAAAAA; - rg_minstret = 64'hAAAAAAAAAAAAAAAA; - rg_mscratch = 64'hAAAAAAAAAAAAAAAA; - rg_mtval = 64'hAAAAAAAAAAAAAAAA; - rg_mtvec = 63'h2AAAAAAAAAAAAAAA; - rg_nmi = 1'h0; - rg_nmi_vector = 64'hAAAAAAAAAAAAAAAA; - rg_state = 1'h0; - rg_tdata1 = 64'hAAAAAAAAAAAAAAAA; - rg_tdata2 = 64'hAAAAAAAAAAAAAAAA; - rg_tdata3 = 64'hAAAAAAAAAAAAAAAA; - rg_tselect = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mip = 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_debug) $display("mie = 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h", - csr_trap_actions_from_priv, - csr_trap_actions_pc, - csr_trap_actions_interrupt, - csr_trap_actions_exc_code, - csr_trap_actions_xtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" priv %0d: ", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" ip: 0x%0h", csr_mip$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" ie: 0x%0h", csr_mie$fv_read); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" edeleg: 0x%0h", 16'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" ideleg: 0x%0h", 12'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" cause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd10 && - rg_mcause[3:0] != 4'd11) - $write("unknown interrupt Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !rg_mcause[4] && - rg_mcause[3:0] != 4'd0 && - rg_mcause[3:0] != 4'd1 && - rg_mcause[3:0] != 4'd2 && - rg_mcause[3:0] != 4'd3 && - rg_mcause[3:0] != 4'd4 && - rg_mcause[3:0] != 4'd5 && - rg_mcause[3:0] != 4'd6 && - rg_mcause[3:0] != 4'd7 && - rg_mcause[3:0] != 4'd8 && - rg_mcause[3:0] != 4'd9 && - rg_mcause[3:0] != 4'd11 && - rg_mcause[3:0] != 4'd12 && - rg_mcause[3:0] != 4'd13 && - rg_mcause[3:0] != 4'd15) - $write("unknown trap Exc_Code %d", rg_mcause[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" status: 0x%0h", csr_mstatus_rg_mstatus); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" tvec: 0x%0h", { rg_mtvec[62:1], 1'b0, rg_mtvec[0] }); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" epc: 0x%0h", rg_mepc); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" tval: 0x%0h", rg_mtval); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" Return: new pc 0x%0h ", x__h5891); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" new mstatus:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write("MStatus{", "sd:%0d", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" sxl:%0d uxl:%0d", 2'd0, 2'd2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" tsr:%0d", csr_mstatus_rg_mstatus[22]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" tw:%0d", csr_mstatus_rg_mstatus[21]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" tvm:%0d", csr_mstatus_rg_mstatus[20]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" mxr:%0d", csr_mstatus_rg_mstatus[19]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" sum:%0d", csr_mstatus_rg_mstatus[18]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" mprv:%0d", csr_mstatus_rg_mstatus[17]); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" xs:%0d", 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" fs:%0d", 2'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" mpp:%0d", mpp__h7414); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" spp:%0d", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" pies:%0d_%0d%0d", csr_mstatus_rg_mstatus[3], 1'd0, 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" ies:%0d_%0d%0d", 1'd0, 1'd0, 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write("}"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" new xcause:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd0) - $write("USER_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd1) - $write("SUPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd2) - $write("HYPERVISOR_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd3) - $write("MACHINE_SW_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd4) - $write("USER_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd5) - $write("SUPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd6) - $write("HYPERVISOR_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd7) - $write("MACHINE_TIMER_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd8) - $write("USER_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd9) - $write("SUPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd10) - $write("HYPERVISOR_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - !csr_trap_actions_nmi && - csr_trap_actions_interrupt && - exc_code__h8056 == 4'd11) - $write("MACHINE_EXTERNAL_INTERRUPT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - NOT_csr_trap_actions_nmi_10_AND_csr_trap_actio_ETC___d787) - $write("unknown interrupt Exc_Code %d", exc_code__h8056); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd0) - $write("INSTRUCTION_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd1) - $write("INSTRUCTION_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd2) - $write("ILLEGAL_INSTRUCTION"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd3) - $write("BREAKPOINT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd4) - $write("LOAD_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd5) - $write("LOAD_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd6) - $write("STORE_AMO_ADDR_MISALIGNED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd7) - $write("STORE_AMO_ACCESS_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd8) - $write("ECALL_FROM_U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd9) - $write("ECALL_FROM_S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd11) - $write("ECALL_FROM_M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd12) - $write("INSTRUCTION_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd13) - $write("LOAD_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8056 == 4'd15) - $write("STORE_AMO_PAGE_FAULT"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551 && - csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d838) - $write("unknown trap Exc_Code %d", exc_code__h8056); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $write(" new priv %0d", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_csr_trap_actions && NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mav_csr_write && - (mav_csr_write_csr_addr_ULT_0xB03___d443 || - !mav_csr_write_csr_addr_ULE_0xB1F___d444) && - mav_csr_write_csr_addr_ULT_0x323_47_OR_NOT_mav_ETC___d547 && - NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful", - rg_mcycle, - mav_csr_write_csr_addr, - mav_csr_write_word); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: CSR_RegFile: m_external_interrupt_req: %x", - rg_mcycle, - m_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: CSR_RegFile: s_external_interrupt_req: %x", - rg_mcycle, - s_external_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: CSR_RegFile: software_interrupt_req: %x", - rg_mcycle, - software_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_cfg_verbosity_read__49_ULE_1_50___d551) - $display("%0d: CSR_RegFile: timer_interrupt_req: %x", - rg_mcycle, - timer_interrupt_req_set_not_clear); - end - // synopsys translate_on -endmodule // mkCSR_RegFile - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCore.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCore.v deleted file mode 100644 index d4c0ffcf..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkCore.v +++ /dev/null @@ -1,2497 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_cpu_reset_server_request_put O 1 reg -// cpu_reset_server_response_get O 1 reg -// RDY_cpu_reset_server_response_get O 1 reg -// cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg -// cpu_imem_master_wvalid O 1 -// cpu_imem_master_wid O 4 reg -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg -// cpu_imem_master_bready O 1 -// cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg -// cpu_imem_master_rready O 1 -// cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg -// cpu_dmem_master_awaddr O 64 reg -// cpu_dmem_master_awlen O 8 reg -// cpu_dmem_master_awsize O 3 reg -// cpu_dmem_master_awburst O 2 reg -// cpu_dmem_master_awlock O 1 reg -// cpu_dmem_master_awcache O 4 reg -// cpu_dmem_master_awprot O 3 reg -// cpu_dmem_master_awqos O 4 reg -// cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg -// cpu_dmem_master_wid O 4 reg -// cpu_dmem_master_wdata O 64 reg -// cpu_dmem_master_wstrb O 8 reg -// cpu_dmem_master_wlast O 1 reg -// cpu_dmem_master_bready O 1 reg -// cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg -// cpu_dmem_master_araddr O 64 reg -// cpu_dmem_master_arlen O 8 reg -// cpu_dmem_master_arsize O 3 reg -// cpu_dmem_master_arburst O 2 reg -// cpu_dmem_master_arlock O 1 reg -// cpu_dmem_master_arcache O 4 reg -// cpu_dmem_master_arprot O 3 reg -// cpu_dmem_master_arqos O 4 reg -// cpu_dmem_master_arregion O 4 reg -// cpu_dmem_master_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// cpu_reset_server_request_put I 1 reg -// cpu_imem_master_awready I 1 -// cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg -// cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg -// cpu_dmem_master_awready I 1 -// cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg -// cpu_dmem_master_bresp I 2 reg -// cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg -// cpu_dmem_master_rdata I 64 reg -// cpu_dmem_master_rresp I 2 reg -// cpu_dmem_master_rlast I 1 reg -// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1 -// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1 -// nmi_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_cpu_reset_server_request_put I 1 -// EN_cpu_reset_server_response_get I 1 -// -// Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCore(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - cpu_reset_server_request_put, - EN_cpu_reset_server_request_put, - RDY_cpu_reset_server_request_put, - - EN_cpu_reset_server_response_get, - cpu_reset_server_response_get, - RDY_cpu_reset_server_response_get, - - cpu_imem_master_awvalid, - - cpu_imem_master_awid, - - cpu_imem_master_awaddr, - - cpu_imem_master_awlen, - - cpu_imem_master_awsize, - - cpu_imem_master_awburst, - - cpu_imem_master_awlock, - - cpu_imem_master_awcache, - - cpu_imem_master_awprot, - - cpu_imem_master_awqos, - - cpu_imem_master_awregion, - - cpu_imem_master_awready, - - cpu_imem_master_wvalid, - - cpu_imem_master_wid, - - cpu_imem_master_wdata, - - cpu_imem_master_wstrb, - - cpu_imem_master_wlast, - - cpu_imem_master_wready, - - cpu_imem_master_bvalid, - cpu_imem_master_bid, - cpu_imem_master_bresp, - - cpu_imem_master_bready, - - cpu_imem_master_arvalid, - - cpu_imem_master_arid, - - cpu_imem_master_araddr, - - cpu_imem_master_arlen, - - cpu_imem_master_arsize, - - cpu_imem_master_arburst, - - cpu_imem_master_arlock, - - cpu_imem_master_arcache, - - cpu_imem_master_arprot, - - cpu_imem_master_arqos, - - cpu_imem_master_arregion, - - cpu_imem_master_arready, - - cpu_imem_master_rvalid, - cpu_imem_master_rid, - cpu_imem_master_rdata, - cpu_imem_master_rresp, - cpu_imem_master_rlast, - - cpu_imem_master_rready, - - cpu_dmem_master_awvalid, - - cpu_dmem_master_awid, - - cpu_dmem_master_awaddr, - - cpu_dmem_master_awlen, - - cpu_dmem_master_awsize, - - cpu_dmem_master_awburst, - - cpu_dmem_master_awlock, - - cpu_dmem_master_awcache, - - cpu_dmem_master_awprot, - - cpu_dmem_master_awqos, - - cpu_dmem_master_awregion, - - cpu_dmem_master_awready, - - cpu_dmem_master_wvalid, - - cpu_dmem_master_wid, - - cpu_dmem_master_wdata, - - cpu_dmem_master_wstrb, - - cpu_dmem_master_wlast, - - cpu_dmem_master_wready, - - cpu_dmem_master_bvalid, - cpu_dmem_master_bid, - cpu_dmem_master_bresp, - - cpu_dmem_master_bready, - - cpu_dmem_master_arvalid, - - cpu_dmem_master_arid, - - cpu_dmem_master_araddr, - - cpu_dmem_master_arlen, - - cpu_dmem_master_arsize, - - cpu_dmem_master_arburst, - - cpu_dmem_master_arlock, - - cpu_dmem_master_arcache, - - cpu_dmem_master_arprot, - - cpu_dmem_master_arqos, - - cpu_dmem_master_arregion, - - cpu_dmem_master_arready, - - cpu_dmem_master_rvalid, - cpu_dmem_master_rid, - cpu_dmem_master_rdata, - cpu_dmem_master_rresp, - cpu_dmem_master_rlast, - - cpu_dmem_master_rready, - - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - - nmi_req_set_not_clear); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method cpu_reset_server_request_put - input cpu_reset_server_request_put; - input EN_cpu_reset_server_request_put; - output RDY_cpu_reset_server_request_put; - - // actionvalue method cpu_reset_server_response_get - input EN_cpu_reset_server_response_get; - output cpu_reset_server_response_get; - output RDY_cpu_reset_server_response_get; - - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; - - // value method cpu_imem_master_m_awaddr - output [63 : 0] cpu_imem_master_awaddr; - - // value method cpu_imem_master_m_awlen - output [7 : 0] cpu_imem_master_awlen; - - // value method cpu_imem_master_m_awsize - output [2 : 0] cpu_imem_master_awsize; - - // value method cpu_imem_master_m_awburst - output [1 : 0] cpu_imem_master_awburst; - - // value method cpu_imem_master_m_awlock - output cpu_imem_master_awlock; - - // value method cpu_imem_master_m_awcache - output [3 : 0] cpu_imem_master_awcache; - - // value method cpu_imem_master_m_awprot - output [2 : 0] cpu_imem_master_awprot; - - // value method cpu_imem_master_m_awqos - output [3 : 0] cpu_imem_master_awqos; - - // value method cpu_imem_master_m_awregion - output [3 : 0] cpu_imem_master_awregion; - - // value method cpu_imem_master_m_awuser - - // action method cpu_imem_master_m_awready - input cpu_imem_master_awready; - - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; - - // value method cpu_imem_master_m_wid - output [3 : 0] cpu_imem_master_wid; - - // value method cpu_imem_master_m_wdata - output [63 : 0] cpu_imem_master_wdata; - - // value method cpu_imem_master_m_wstrb - output [7 : 0] cpu_imem_master_wstrb; - - // value method cpu_imem_master_m_wlast - output cpu_imem_master_wlast; - - // value method cpu_imem_master_m_wuser - - // action method cpu_imem_master_m_wready - input cpu_imem_master_wready; - - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; - input [1 : 0] cpu_imem_master_bresp; - - // value method cpu_imem_master_m_bready - output cpu_imem_master_bready; - - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; - - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; - - // value method cpu_imem_master_m_araddr - output [63 : 0] cpu_imem_master_araddr; - - // value method cpu_imem_master_m_arlen - output [7 : 0] cpu_imem_master_arlen; - - // value method cpu_imem_master_m_arsize - output [2 : 0] cpu_imem_master_arsize; - - // value method cpu_imem_master_m_arburst - output [1 : 0] cpu_imem_master_arburst; - - // value method cpu_imem_master_m_arlock - output cpu_imem_master_arlock; - - // value method cpu_imem_master_m_arcache - output [3 : 0] cpu_imem_master_arcache; - - // value method cpu_imem_master_m_arprot - output [2 : 0] cpu_imem_master_arprot; - - // value method cpu_imem_master_m_arqos - output [3 : 0] cpu_imem_master_arqos; - - // value method cpu_imem_master_m_arregion - output [3 : 0] cpu_imem_master_arregion; - - // value method cpu_imem_master_m_aruser - - // action method cpu_imem_master_m_arready - input cpu_imem_master_arready; - - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; - input [63 : 0] cpu_imem_master_rdata; - input [1 : 0] cpu_imem_master_rresp; - input cpu_imem_master_rlast; - - // value method cpu_imem_master_m_rready - output cpu_imem_master_rready; - - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; - - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; - - // value method cpu_dmem_master_m_awaddr - output [63 : 0] cpu_dmem_master_awaddr; - - // value method cpu_dmem_master_m_awlen - output [7 : 0] cpu_dmem_master_awlen; - - // value method cpu_dmem_master_m_awsize - output [2 : 0] cpu_dmem_master_awsize; - - // value method cpu_dmem_master_m_awburst - output [1 : 0] cpu_dmem_master_awburst; - - // value method cpu_dmem_master_m_awlock - output cpu_dmem_master_awlock; - - // value method cpu_dmem_master_m_awcache - output [3 : 0] cpu_dmem_master_awcache; - - // value method cpu_dmem_master_m_awprot - output [2 : 0] cpu_dmem_master_awprot; - - // value method cpu_dmem_master_m_awqos - output [3 : 0] cpu_dmem_master_awqos; - - // value method cpu_dmem_master_m_awregion - output [3 : 0] cpu_dmem_master_awregion; - - // value method cpu_dmem_master_m_awuser - - // action method cpu_dmem_master_m_awready - input cpu_dmem_master_awready; - - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; - - // value method cpu_dmem_master_m_wid - output [3 : 0] cpu_dmem_master_wid; - - // value method cpu_dmem_master_m_wdata - output [63 : 0] cpu_dmem_master_wdata; - - // value method cpu_dmem_master_m_wstrb - output [7 : 0] cpu_dmem_master_wstrb; - - // value method cpu_dmem_master_m_wlast - output cpu_dmem_master_wlast; - - // value method cpu_dmem_master_m_wuser - - // action method cpu_dmem_master_m_wready - input cpu_dmem_master_wready; - - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; - input [1 : 0] cpu_dmem_master_bresp; - - // value method cpu_dmem_master_m_bready - output cpu_dmem_master_bready; - - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; - - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; - - // value method cpu_dmem_master_m_araddr - output [63 : 0] cpu_dmem_master_araddr; - - // value method cpu_dmem_master_m_arlen - output [7 : 0] cpu_dmem_master_arlen; - - // value method cpu_dmem_master_m_arsize - output [2 : 0] cpu_dmem_master_arsize; - - // value method cpu_dmem_master_m_arburst - output [1 : 0] cpu_dmem_master_arburst; - - // value method cpu_dmem_master_m_arlock - output cpu_dmem_master_arlock; - - // value method cpu_dmem_master_m_arcache - output [3 : 0] cpu_dmem_master_arcache; - - // value method cpu_dmem_master_m_arprot - output [2 : 0] cpu_dmem_master_arprot; - - // value method cpu_dmem_master_m_arqos - output [3 : 0] cpu_dmem_master_arqos; - - // value method cpu_dmem_master_m_arregion - output [3 : 0] cpu_dmem_master_arregion; - - // value method cpu_dmem_master_m_aruser - - // action method cpu_dmem_master_m_arready - input cpu_dmem_master_arready; - - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; - input [63 : 0] cpu_dmem_master_rdata; - input [1 : 0] cpu_dmem_master_rresp; - input cpu_dmem_master_rlast; - - // value method cpu_dmem_master_m_rready - output cpu_dmem_master_rready; - - // action method core_external_interrupt_sources_0_m_interrupt_req - input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_1_m_interrupt_req - input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_2_m_interrupt_req - input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_3_m_interrupt_req - input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_4_m_interrupt_req - input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_5_m_interrupt_req - input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_6_m_interrupt_req - input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_7_m_interrupt_req - input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_8_m_interrupt_req - input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_9_m_interrupt_req - input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_10_m_interrupt_req - input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_11_m_interrupt_req - input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_12_m_interrupt_req - input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_13_m_interrupt_req - input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_14_m_interrupt_req - input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear; - - // action method core_external_interrupt_sources_15_m_interrupt_req - input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear; - - // action method nmi_req - input nmi_req_set_not_clear; - - // signals for module outputs - wire [63 : 0] cpu_dmem_master_araddr, - cpu_dmem_master_awaddr, - cpu_dmem_master_wdata, - cpu_imem_master_araddr, - cpu_imem_master_awaddr, - cpu_imem_master_wdata; - wire [7 : 0] cpu_dmem_master_arlen, - cpu_dmem_master_awlen, - cpu_dmem_master_wstrb, - cpu_imem_master_arlen, - cpu_imem_master_awlen, - cpu_imem_master_wstrb; - wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, - cpu_dmem_master_arqos, - cpu_dmem_master_arregion, - cpu_dmem_master_awcache, - cpu_dmem_master_awid, - cpu_dmem_master_awqos, - cpu_dmem_master_awregion, - cpu_dmem_master_wid, - cpu_imem_master_arcache, - cpu_imem_master_arid, - cpu_imem_master_arqos, - cpu_imem_master_arregion, - cpu_imem_master_awcache, - cpu_imem_master_awid, - cpu_imem_master_awqos, - cpu_imem_master_awregion, - cpu_imem_master_wid; - wire [2 : 0] cpu_dmem_master_arprot, - cpu_dmem_master_arsize, - cpu_dmem_master_awprot, - cpu_dmem_master_awsize, - cpu_imem_master_arprot, - cpu_imem_master_arsize, - cpu_imem_master_awprot, - cpu_imem_master_awsize; - wire [1 : 0] cpu_dmem_master_arburst, - cpu_dmem_master_awburst, - cpu_imem_master_arburst, - cpu_imem_master_awburst; - wire RDY_cpu_reset_server_request_put, - RDY_cpu_reset_server_response_get, - RDY_set_verbosity, - cpu_dmem_master_arlock, - cpu_dmem_master_arvalid, - cpu_dmem_master_awlock, - cpu_dmem_master_awvalid, - cpu_dmem_master_bready, - cpu_dmem_master_rready, - cpu_dmem_master_wlast, - cpu_dmem_master_wvalid, - cpu_imem_master_arlock, - cpu_imem_master_arvalid, - cpu_imem_master_awlock, - cpu_imem_master_awvalid, - cpu_imem_master_bready, - cpu_imem_master_rready, - cpu_imem_master_wlast, - cpu_imem_master_wvalid, - cpu_reset_server_response_get; - - // ports of submodule cpu - wire [63 : 0] cpu$dmem_master_araddr, - cpu$dmem_master_awaddr, - cpu$dmem_master_rdata, - cpu$dmem_master_wdata, - cpu$imem_master_araddr, - cpu$imem_master_awaddr, - cpu$imem_master_rdata, - cpu$imem_master_wdata, - cpu$set_verbosity_logdelay; - wire [7 : 0] cpu$dmem_master_arlen, - cpu$dmem_master_awlen, - cpu$dmem_master_wstrb, - cpu$imem_master_arlen, - cpu$imem_master_awlen, - cpu$imem_master_wstrb; - wire [3 : 0] cpu$dmem_master_arcache, - cpu$dmem_master_arid, - cpu$dmem_master_arqos, - cpu$dmem_master_arregion, - cpu$dmem_master_awcache, - cpu$dmem_master_awid, - cpu$dmem_master_awqos, - cpu$dmem_master_awregion, - cpu$dmem_master_bid, - cpu$dmem_master_rid, - cpu$dmem_master_wid, - cpu$imem_master_arcache, - cpu$imem_master_arid, - cpu$imem_master_arqos, - cpu$imem_master_arregion, - cpu$imem_master_awcache, - cpu$imem_master_awid, - cpu$imem_master_awqos, - cpu$imem_master_awregion, - cpu$imem_master_bid, - cpu$imem_master_rid, - cpu$imem_master_wid, - cpu$set_verbosity_verbosity; - wire [2 : 0] cpu$dmem_master_arprot, - cpu$dmem_master_arsize, - cpu$dmem_master_awprot, - cpu$dmem_master_awsize, - cpu$imem_master_arprot, - cpu$imem_master_arsize, - cpu$imem_master_awprot, - cpu$imem_master_awsize; - wire [1 : 0] cpu$dmem_master_arburst, - cpu$dmem_master_awburst, - cpu$dmem_master_bresp, - cpu$dmem_master_rresp, - cpu$imem_master_arburst, - cpu$imem_master_awburst, - cpu$imem_master_bresp, - cpu$imem_master_rresp; - wire cpu$EN_hart0_server_reset_request_put, - cpu$EN_hart0_server_reset_response_get, - cpu$EN_set_verbosity, - cpu$RDY_hart0_server_reset_request_put, - cpu$RDY_hart0_server_reset_response_get, - cpu$dmem_master_arlock, - cpu$dmem_master_arready, - cpu$dmem_master_arvalid, - cpu$dmem_master_awlock, - cpu$dmem_master_awready, - cpu$dmem_master_awvalid, - cpu$dmem_master_bready, - cpu$dmem_master_bvalid, - cpu$dmem_master_rlast, - cpu$dmem_master_rready, - cpu$dmem_master_rvalid, - cpu$dmem_master_wlast, - cpu$dmem_master_wready, - cpu$dmem_master_wvalid, - cpu$hart0_server_reset_request_put, - cpu$hart0_server_reset_response_get, - cpu$imem_master_arlock, - cpu$imem_master_arready, - cpu$imem_master_arvalid, - cpu$imem_master_awlock, - cpu$imem_master_awready, - cpu$imem_master_awvalid, - cpu$imem_master_bready, - cpu$imem_master_bvalid, - cpu$imem_master_rlast, - cpu$imem_master_rready, - cpu$imem_master_rvalid, - cpu$imem_master_wlast, - cpu$imem_master_wready, - cpu$imem_master_wvalid, - cpu$m_external_interrupt_req_set_not_clear, - cpu$nmi_req_set_not_clear, - cpu$s_external_interrupt_req_set_not_clear, - cpu$software_interrupt_req_set_not_clear, - cpu$timer_interrupt_req_set_not_clear; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_araddr, - fabric_2x3$v_to_slaves_2_awaddr, - fabric_2x3$v_to_slaves_2_rdata, - fabric_2x3$v_to_slaves_2_wdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb, - fabric_2x3$v_to_slaves_2_arlen, - fabric_2x3$v_to_slaves_2_awlen, - fabric_2x3$v_to_slaves_2_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_0_wid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_wid, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_0_wid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_1_wid, - fabric_2x3$v_to_slaves_2_arcache, - fabric_2x3$v_to_slaves_2_arid, - fabric_2x3$v_to_slaves_2_arqos, - fabric_2x3$v_to_slaves_2_arregion, - fabric_2x3$v_to_slaves_2_awcache, - fabric_2x3$v_to_slaves_2_awid, - fabric_2x3$v_to_slaves_2_awqos, - fabric_2x3$v_to_slaves_2_awregion, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid, - fabric_2x3$v_to_slaves_2_wid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize, - fabric_2x3$v_to_slaves_2_arprot, - fabric_2x3$v_to_slaves_2_arsize, - fabric_2x3$v_to_slaves_2_awprot, - fabric_2x3$v_to_slaves_2_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_arburst, - fabric_2x3$v_to_slaves_2_awburst, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arlock, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_arvalid, - fabric_2x3$v_to_slaves_2_awlock, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_awvalid, - fabric_2x3$v_to_slaves_2_bready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rready, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wlast, - fabric_2x3$v_to_slaves_2_wready, - fabric_2x3$v_to_slaves_2_wvalid; - - // ports of submodule near_mem_io - wire [63 : 0] near_mem_io$axi4_slave_araddr, - near_mem_io$axi4_slave_awaddr, - near_mem_io$axi4_slave_rdata, - near_mem_io$axi4_slave_wdata, - near_mem_io$set_addr_map_addr_base, - near_mem_io$set_addr_map_addr_lim; - wire [7 : 0] near_mem_io$axi4_slave_arlen, - near_mem_io$axi4_slave_awlen, - near_mem_io$axi4_slave_wstrb; - wire [3 : 0] near_mem_io$axi4_slave_arcache, - near_mem_io$axi4_slave_arid, - near_mem_io$axi4_slave_arqos, - near_mem_io$axi4_slave_arregion, - near_mem_io$axi4_slave_awcache, - near_mem_io$axi4_slave_awid, - near_mem_io$axi4_slave_awqos, - near_mem_io$axi4_slave_awregion, - near_mem_io$axi4_slave_bid, - near_mem_io$axi4_slave_rid, - near_mem_io$axi4_slave_wid; - wire [2 : 0] near_mem_io$axi4_slave_arprot, - near_mem_io$axi4_slave_arsize, - near_mem_io$axi4_slave_awprot, - near_mem_io$axi4_slave_awsize; - wire [1 : 0] near_mem_io$axi4_slave_arburst, - near_mem_io$axi4_slave_awburst, - near_mem_io$axi4_slave_bresp, - near_mem_io$axi4_slave_rresp; - wire near_mem_io$EN_get_sw_interrupt_req_get, - near_mem_io$EN_get_timer_interrupt_req_get, - near_mem_io$EN_server_reset_request_put, - near_mem_io$EN_server_reset_response_get, - near_mem_io$EN_set_addr_map, - near_mem_io$RDY_get_sw_interrupt_req_get, - near_mem_io$RDY_get_timer_interrupt_req_get, - near_mem_io$RDY_server_reset_request_put, - near_mem_io$RDY_server_reset_response_get, - near_mem_io$axi4_slave_arlock, - near_mem_io$axi4_slave_arready, - near_mem_io$axi4_slave_arvalid, - near_mem_io$axi4_slave_awlock, - near_mem_io$axi4_slave_awready, - near_mem_io$axi4_slave_awvalid, - near_mem_io$axi4_slave_bready, - near_mem_io$axi4_slave_bvalid, - near_mem_io$axi4_slave_rlast, - near_mem_io$axi4_slave_rready, - near_mem_io$axi4_slave_rvalid, - near_mem_io$axi4_slave_wlast, - near_mem_io$axi4_slave_wready, - near_mem_io$axi4_slave_wvalid, - near_mem_io$get_sw_interrupt_req_get, - near_mem_io$get_timer_interrupt_req_get; - - // ports of submodule plic - wire [63 : 0] plic$axi4_slave_araddr, - plic$axi4_slave_awaddr, - plic$axi4_slave_rdata, - plic$axi4_slave_wdata, - plic$set_addr_map_addr_base, - plic$set_addr_map_addr_lim; - wire [7 : 0] plic$axi4_slave_arlen, - plic$axi4_slave_awlen, - plic$axi4_slave_wstrb; - wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, - plic$axi4_slave_arqos, - plic$axi4_slave_arregion, - plic$axi4_slave_awcache, - plic$axi4_slave_awid, - plic$axi4_slave_awqos, - plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, - plic$axi4_slave_wid, - plic$set_verbosity_verbosity; - wire [2 : 0] plic$axi4_slave_arprot, - plic$axi4_slave_arsize, - plic$axi4_slave_awprot, - plic$axi4_slave_awsize; - wire [1 : 0] plic$axi4_slave_arburst, - plic$axi4_slave_awburst, - plic$axi4_slave_bresp, - plic$axi4_slave_rresp; - wire plic$EN_server_reset_request_put, - plic$EN_server_reset_response_get, - plic$EN_set_addr_map, - plic$EN_set_verbosity, - plic$EN_show_PLIC_state, - plic$RDY_server_reset_request_put, - plic$RDY_server_reset_response_get, - plic$axi4_slave_arlock, - plic$axi4_slave_arready, - plic$axi4_slave_arvalid, - plic$axi4_slave_awlock, - plic$axi4_slave_awready, - plic$axi4_slave_awvalid, - plic$axi4_slave_bready, - plic$axi4_slave_bvalid, - plic$axi4_slave_rlast, - plic$axi4_slave_rready, - plic$axi4_slave_rvalid, - plic$axi4_slave_wlast, - plic$axi4_slave_wready, - plic$axi4_slave_wvalid, - plic$v_sources_0_m_interrupt_req_set_not_clear, - plic$v_sources_10_m_interrupt_req_set_not_clear, - plic$v_sources_11_m_interrupt_req_set_not_clear, - plic$v_sources_12_m_interrupt_req_set_not_clear, - plic$v_sources_13_m_interrupt_req_set_not_clear, - plic$v_sources_14_m_interrupt_req_set_not_clear, - plic$v_sources_15_m_interrupt_req_set_not_clear, - plic$v_sources_1_m_interrupt_req_set_not_clear, - plic$v_sources_2_m_interrupt_req_set_not_clear, - plic$v_sources_3_m_interrupt_req_set_not_clear, - plic$v_sources_4_m_interrupt_req_set_not_clear, - plic$v_sources_5_m_interrupt_req_set_not_clear, - plic$v_sources_6_m_interrupt_req_set_not_clear, - plic$v_sources_7_m_interrupt_req_set_not_clear, - plic$v_sources_8_m_interrupt_req_set_not_clear, - plic$v_sources_9_m_interrupt_req_set_not_clear, - plic$v_targets_0_m_eip, - plic$v_targets_1_m_eip; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete, - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_relay_external_interrupts, - CAN_FIRE_RL_rl_relay_sw_interrupts, - CAN_FIRE_RL_rl_relay_timer_interrupts, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, - CAN_FIRE_cpu_reset_server_request_put, - CAN_FIRE_cpu_reset_server_response_get, - CAN_FIRE_nmi_req, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_rl_cpu_hart0_reset_complete, - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_relay_external_interrupts, - WILL_FIRE_RL_rl_relay_sw_interrupts, - WILL_FIRE_RL_rl_relay_timer_interrupts, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, - WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, - WILL_FIRE_cpu_reset_server_request_put, - WILL_FIRE_cpu_reset_server_response_get, - WILL_FIRE_nmi_req, - WILL_FIRE_set_verbosity; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4310; - reg [31 : 0] v__h4551; - reg [31 : 0] v__h4304; - reg [31 : 0] v__h4545; - // synopsys translate_on - - // remaining internal signals - wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method cpu_reset_server_request_put - assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_cpu_reset_server_request_put = - EN_cpu_reset_server_request_put ; - - // actionvalue method cpu_reset_server_response_get - assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ; - assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_cpu_reset_server_response_get = - EN_cpu_reset_server_response_get ; - - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - - // value method cpu_imem_master_m_awid - assign cpu_imem_master_awid = cpu$imem_master_awid ; - - // value method cpu_imem_master_m_awaddr - assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; - - // value method cpu_imem_master_m_awlen - assign cpu_imem_master_awlen = cpu$imem_master_awlen ; - - // value method cpu_imem_master_m_awsize - assign cpu_imem_master_awsize = cpu$imem_master_awsize ; - - // value method cpu_imem_master_m_awburst - assign cpu_imem_master_awburst = cpu$imem_master_awburst ; - - // value method cpu_imem_master_m_awlock - assign cpu_imem_master_awlock = cpu$imem_master_awlock ; - - // value method cpu_imem_master_m_awcache - assign cpu_imem_master_awcache = cpu$imem_master_awcache ; - - // value method cpu_imem_master_m_awprot - assign cpu_imem_master_awprot = cpu$imem_master_awprot ; - - // value method cpu_imem_master_m_awqos - assign cpu_imem_master_awqos = cpu$imem_master_awqos ; - - // value method cpu_imem_master_m_awregion - assign cpu_imem_master_awregion = cpu$imem_master_awregion ; - - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; - - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; - - // value method cpu_imem_master_m_wid - assign cpu_imem_master_wid = cpu$imem_master_wid ; - - // value method cpu_imem_master_m_wdata - assign cpu_imem_master_wdata = cpu$imem_master_wdata ; - - // value method cpu_imem_master_m_wstrb - assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; - - // value method cpu_imem_master_m_wlast - assign cpu_imem_master_wlast = cpu$imem_master_wlast ; - - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; - - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = cpu$imem_master_bready ; - - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; - - // value method cpu_imem_master_m_arid - assign cpu_imem_master_arid = cpu$imem_master_arid ; - - // value method cpu_imem_master_m_araddr - assign cpu_imem_master_araddr = cpu$imem_master_araddr ; - - // value method cpu_imem_master_m_arlen - assign cpu_imem_master_arlen = cpu$imem_master_arlen ; - - // value method cpu_imem_master_m_arsize - assign cpu_imem_master_arsize = cpu$imem_master_arsize ; - - // value method cpu_imem_master_m_arburst - assign cpu_imem_master_arburst = cpu$imem_master_arburst ; - - // value method cpu_imem_master_m_arlock - assign cpu_imem_master_arlock = cpu$imem_master_arlock ; - - // value method cpu_imem_master_m_arcache - assign cpu_imem_master_arcache = cpu$imem_master_arcache ; - - // value method cpu_imem_master_m_arprot - assign cpu_imem_master_arprot = cpu$imem_master_arprot ; - - // value method cpu_imem_master_m_arqos - assign cpu_imem_master_arqos = cpu$imem_master_arqos ; - - // value method cpu_imem_master_m_arregion - assign cpu_imem_master_arregion = cpu$imem_master_arregion ; - - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; - - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - - // value method cpu_imem_master_m_rready - assign cpu_imem_master_rready = cpu$imem_master_rready ; - - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; - - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; - - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; - - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; - - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; - - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; - - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; - - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; - - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; - - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; - - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; - - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; - - // value method cpu_dmem_master_m_wid - assign cpu_dmem_master_wid = fabric_2x3$v_to_slaves_0_wid ; - - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; - - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; - - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; - - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; - - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; - - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; - - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; - - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; - - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; - - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; - - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; - - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; - - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; - - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; - - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; - - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; - - // action method core_external_interrupt_sources_0_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_1_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_2_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_3_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_4_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_5_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_6_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_7_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_8_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_9_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_10_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_11_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_12_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_13_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_14_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ; - - // action method core_external_interrupt_sources_15_m_interrupt_req - assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ; - - // action method nmi_req - assign CAN_FIRE_nmi_req = 1'd1 ; - assign WILL_FIRE_nmi_req = 1'd1 ; - - // submodule cpu - mkCPU cpu(.CLK(CLK), - .RST_N(RST_N), - .dmem_master_arready(cpu$dmem_master_arready), - .dmem_master_awready(cpu$dmem_master_awready), - .dmem_master_bid(cpu$dmem_master_bid), - .dmem_master_bresp(cpu$dmem_master_bresp), - .dmem_master_bvalid(cpu$dmem_master_bvalid), - .dmem_master_rdata(cpu$dmem_master_rdata), - .dmem_master_rid(cpu$dmem_master_rid), - .dmem_master_rlast(cpu$dmem_master_rlast), - .dmem_master_rresp(cpu$dmem_master_rresp), - .dmem_master_rvalid(cpu$dmem_master_rvalid), - .dmem_master_wready(cpu$dmem_master_wready), - .hart0_server_reset_request_put(cpu$hart0_server_reset_request_put), - .imem_master_arready(cpu$imem_master_arready), - .imem_master_awready(cpu$imem_master_awready), - .imem_master_bid(cpu$imem_master_bid), - .imem_master_bresp(cpu$imem_master_bresp), - .imem_master_bvalid(cpu$imem_master_bvalid), - .imem_master_rdata(cpu$imem_master_rdata), - .imem_master_rid(cpu$imem_master_rid), - .imem_master_rlast(cpu$imem_master_rlast), - .imem_master_rresp(cpu$imem_master_rresp), - .imem_master_rvalid(cpu$imem_master_rvalid), - .imem_master_wready(cpu$imem_master_wready), - .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), - .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), - .s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear), - .set_verbosity_logdelay(cpu$set_verbosity_logdelay), - .set_verbosity_verbosity(cpu$set_verbosity_verbosity), - .software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear), - .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), - .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), - .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), - .EN_set_verbosity(cpu$EN_set_verbosity), - .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), - .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), - .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), - .imem_master_awvalid(cpu$imem_master_awvalid), - .imem_master_awid(cpu$imem_master_awid), - .imem_master_awaddr(cpu$imem_master_awaddr), - .imem_master_awlen(cpu$imem_master_awlen), - .imem_master_awsize(cpu$imem_master_awsize), - .imem_master_awburst(cpu$imem_master_awburst), - .imem_master_awlock(cpu$imem_master_awlock), - .imem_master_awcache(cpu$imem_master_awcache), - .imem_master_awprot(cpu$imem_master_awprot), - .imem_master_awqos(cpu$imem_master_awqos), - .imem_master_awregion(cpu$imem_master_awregion), - .imem_master_wvalid(cpu$imem_master_wvalid), - .imem_master_wid(cpu$imem_master_wid), - .imem_master_wdata(cpu$imem_master_wdata), - .imem_master_wstrb(cpu$imem_master_wstrb), - .imem_master_wlast(cpu$imem_master_wlast), - .imem_master_bready(cpu$imem_master_bready), - .imem_master_arvalid(cpu$imem_master_arvalid), - .imem_master_arid(cpu$imem_master_arid), - .imem_master_araddr(cpu$imem_master_araddr), - .imem_master_arlen(cpu$imem_master_arlen), - .imem_master_arsize(cpu$imem_master_arsize), - .imem_master_arburst(cpu$imem_master_arburst), - .imem_master_arlock(cpu$imem_master_arlock), - .imem_master_arcache(cpu$imem_master_arcache), - .imem_master_arprot(cpu$imem_master_arprot), - .imem_master_arqos(cpu$imem_master_arqos), - .imem_master_arregion(cpu$imem_master_arregion), - .imem_master_rready(cpu$imem_master_rready), - .dmem_master_awvalid(cpu$dmem_master_awvalid), - .dmem_master_awid(cpu$dmem_master_awid), - .dmem_master_awaddr(cpu$dmem_master_awaddr), - .dmem_master_awlen(cpu$dmem_master_awlen), - .dmem_master_awsize(cpu$dmem_master_awsize), - .dmem_master_awburst(cpu$dmem_master_awburst), - .dmem_master_awlock(cpu$dmem_master_awlock), - .dmem_master_awcache(cpu$dmem_master_awcache), - .dmem_master_awprot(cpu$dmem_master_awprot), - .dmem_master_awqos(cpu$dmem_master_awqos), - .dmem_master_awregion(cpu$dmem_master_awregion), - .dmem_master_wvalid(cpu$dmem_master_wvalid), - .dmem_master_wid(cpu$dmem_master_wid), - .dmem_master_wdata(cpu$dmem_master_wdata), - .dmem_master_wstrb(cpu$dmem_master_wstrb), - .dmem_master_wlast(cpu$dmem_master_wlast), - .dmem_master_bready(cpu$dmem_master_bready), - .dmem_master_arvalid(cpu$dmem_master_arvalid), - .dmem_master_arid(cpu$dmem_master_arid), - .dmem_master_araddr(cpu$dmem_master_araddr), - .dmem_master_arlen(cpu$dmem_master_arlen), - .dmem_master_arsize(cpu$dmem_master_arsize), - .dmem_master_arburst(cpu$dmem_master_arburst), - .dmem_master_arlock(cpu$dmem_master_arlock), - .dmem_master_arcache(cpu$dmem_master_arcache), - .dmem_master_arprot(cpu$dmem_master_arprot), - .dmem_master_arqos(cpu$dmem_master_arqos), - .dmem_master_arregion(cpu$dmem_master_arregion), - .dmem_master_rready(cpu$dmem_master_rready), - .RDY_set_verbosity()); - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric_2x3$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric_2x3$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(), - .v_from_masters_1_wready(), - .v_from_masters_1_bvalid(), - .v_from_masters_1_bid(), - .v_from_masters_1_bresp(), - .v_from_masters_1_arready(), - .v_from_masters_1_rvalid(), - .v_from_masters_1_rid(), - .v_from_masters_1_rdata(), - .v_from_masters_1_rresp(), - .v_from_masters_1_rlast(), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric_2x3$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric_2x3$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric_2x3$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); - - // submodule near_mem_io - mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(near_mem_io$axi4_slave_araddr), - .axi4_slave_arburst(near_mem_io$axi4_slave_arburst), - .axi4_slave_arcache(near_mem_io$axi4_slave_arcache), - .axi4_slave_arid(near_mem_io$axi4_slave_arid), - .axi4_slave_arlen(near_mem_io$axi4_slave_arlen), - .axi4_slave_arlock(near_mem_io$axi4_slave_arlock), - .axi4_slave_arprot(near_mem_io$axi4_slave_arprot), - .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), - .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), - .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), - .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), - .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), - .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), - .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), - .axi4_slave_awid(near_mem_io$axi4_slave_awid), - .axi4_slave_awlen(near_mem_io$axi4_slave_awlen), - .axi4_slave_awlock(near_mem_io$axi4_slave_awlock), - .axi4_slave_awprot(near_mem_io$axi4_slave_awprot), - .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), - .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), - .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), - .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), - .axi4_slave_bready(near_mem_io$axi4_slave_bready), - .axi4_slave_rready(near_mem_io$axi4_slave_rready), - .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), - .axi4_slave_wid(near_mem_io$axi4_slave_wid), - .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), - .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), - .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), - .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), - .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), - .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), - .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), - .EN_set_addr_map(near_mem_io$EN_set_addr_map), - .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), - .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), - .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), - .RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(near_mem_io$axi4_slave_awready), - .axi4_slave_wready(near_mem_io$axi4_slave_wready), - .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), - .axi4_slave_bid(near_mem_io$axi4_slave_bid), - .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), - .axi4_slave_arready(near_mem_io$axi4_slave_arready), - .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), - .axi4_slave_rid(near_mem_io$axi4_slave_rid), - .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), - .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), - .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), - .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), - .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), - .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), - .RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get)); - - // submodule plic - mkPLIC_16_2_7 plic(.CLK(CLK), - .RST_N(RST_N), - .axi4_slave_araddr(plic$axi4_slave_araddr), - .axi4_slave_arburst(plic$axi4_slave_arburst), - .axi4_slave_arcache(plic$axi4_slave_arcache), - .axi4_slave_arid(plic$axi4_slave_arid), - .axi4_slave_arlen(plic$axi4_slave_arlen), - .axi4_slave_arlock(plic$axi4_slave_arlock), - .axi4_slave_arprot(plic$axi4_slave_arprot), - .axi4_slave_arqos(plic$axi4_slave_arqos), - .axi4_slave_arregion(plic$axi4_slave_arregion), - .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), - .axi4_slave_awaddr(plic$axi4_slave_awaddr), - .axi4_slave_awburst(plic$axi4_slave_awburst), - .axi4_slave_awcache(plic$axi4_slave_awcache), - .axi4_slave_awid(plic$axi4_slave_awid), - .axi4_slave_awlen(plic$axi4_slave_awlen), - .axi4_slave_awlock(plic$axi4_slave_awlock), - .axi4_slave_awprot(plic$axi4_slave_awprot), - .axi4_slave_awqos(plic$axi4_slave_awqos), - .axi4_slave_awregion(plic$axi4_slave_awregion), - .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), - .axi4_slave_bready(plic$axi4_slave_bready), - .axi4_slave_rready(plic$axi4_slave_rready), - .axi4_slave_wdata(plic$axi4_slave_wdata), - .axi4_slave_wid(plic$axi4_slave_wid), - .axi4_slave_wlast(plic$axi4_slave_wlast), - .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), - .set_addr_map_addr_base(plic$set_addr_map_addr_base), - .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), - .set_verbosity_verbosity(plic$set_verbosity_verbosity), - .v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear), - .v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear), - .v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear), - .v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear), - .v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear), - .v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear), - .v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear), - .v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear), - .v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear), - .v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear), - .v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear), - .v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear), - .v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear), - .v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear), - .v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear), - .v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear), - .EN_set_verbosity(plic$EN_set_verbosity), - .EN_show_PLIC_state(plic$EN_show_PLIC_state), - .EN_server_reset_request_put(plic$EN_server_reset_request_put), - .EN_server_reset_response_get(plic$EN_server_reset_response_get), - .EN_set_addr_map(plic$EN_set_addr_map), - .RDY_set_verbosity(), - .RDY_show_PLIC_state(), - .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), - .RDY_server_reset_response_get(plic$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .axi4_slave_awready(plic$axi4_slave_awready), - .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), - .axi4_slave_bid(plic$axi4_slave_bid), - .axi4_slave_bresp(plic$axi4_slave_bresp), - .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), - .axi4_slave_rid(plic$axi4_slave_rid), - .axi4_slave_rdata(plic$axi4_slave_rdata), - .axi4_slave_rresp(plic$axi4_slave_rresp), - .axi4_slave_rlast(plic$axi4_slave_rlast), - .v_targets_0_m_eip(plic$v_targets_0_m_eip), - .v_targets_1_m_eip(plic$v_targets_1_m_eip)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_relay_sw_interrupts - assign CAN_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_sw_interrupts = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // rule RL_rl_relay_timer_interrupts - assign CAN_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign WILL_FIRE_RL_rl_relay_timer_interrupts = - near_mem_io$RDY_get_timer_interrupt_req_get ; - - // rule RL_rl_relay_external_interrupts - assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ; - - // rule RL_rl_cpu_hart0_reset_from_soc_start - assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - - // rule RL_rl_cpu_hart0_reset_complete - assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule cpu - assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; - assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; - assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; - assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; - assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; - assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ; - assign cpu$imem_master_arready = cpu_imem_master_arready ; - assign cpu$imem_master_awready = cpu_imem_master_awready ; - assign cpu$imem_master_bid = cpu_imem_master_bid ; - assign cpu$imem_master_bresp = cpu_imem_master_bresp ; - assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; - assign cpu$imem_master_rdata = cpu_imem_master_rdata ; - assign cpu$imem_master_rid = cpu_imem_master_rid ; - assign cpu$imem_master_rlast = cpu_imem_master_rlast ; - assign cpu$imem_master_rresp = cpu_imem_master_rresp ; - assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; - assign cpu$imem_master_wready = cpu_imem_master_wready ; - assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; - assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; - assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; - assign cpu$software_interrupt_req_set_not_clear = - near_mem_io$get_sw_interrupt_req_get ; - assign cpu$timer_interrupt_req_set_not_clear = - near_mem_io$get_timer_interrupt_req_get ; - assign cpu$EN_hart0_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign cpu$EN_hart0_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign cpu$EN_set_verbosity = EN_set_verbosity ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = cpu_reset_server_request_put ; - assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; - assign f_reset_reqs$DEQ = - near_mem_io$RDY_server_reset_request_put && - plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ; - assign f_reset_rsps$ENQ = - near_mem_io$RDY_server_reset_response_get && - plic$RDY_server_reset_response_get && - cpu$RDY_hart0_server_reset_response_get && - f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; - assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; - assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; - assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; - assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; - assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; - assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; - assign fabric_2x3$v_from_masters_0_wid = cpu$dmem_master_wid ; - assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_awaddr = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awburst = - 2'b10 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awcache = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlen = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awprot = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awqos = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awregion = - 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awsize = - 3'b010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ; - assign fabric_2x3$v_from_masters_1_bready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_rready = 1'd0 ; - assign fabric_2x3$v_from_masters_1_wdata = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wid = 4'b1010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wstrb = - 8'b10101010 /* unspecified value */ ; - assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; - assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; - - // submodule near_mem_io - assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign near_mem_io$axi4_slave_wid = fabric_2x3$v_to_slaves_1_wid ; - assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; - assign near_mem_io$set_addr_map_addr_base = - soc_map$m_near_mem_io_addr_base ; - assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; - assign near_mem_io$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign near_mem_io$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_set_addr_map = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign near_mem_io$EN_get_timer_interrupt_req_get = - near_mem_io$RDY_get_timer_interrupt_req_get ; - assign near_mem_io$EN_get_sw_interrupt_req_get = - near_mem_io$RDY_get_sw_interrupt_req_get ; - - // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign plic$axi4_slave_wid = fabric_2x3$v_to_slaves_2_wid ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; - assign plic$set_verbosity_verbosity = 4'h0 ; - assign plic$v_sources_0_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; - assign plic$v_sources_10_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ; - assign plic$v_sources_11_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ; - assign plic$v_sources_12_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ; - assign plic$v_sources_13_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ; - assign plic$v_sources_14_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ; - assign plic$v_sources_15_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ; - assign plic$v_sources_1_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ; - assign plic$v_sources_2_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ; - assign plic$v_sources_3_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ; - assign plic$v_sources_4_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ; - assign plic$v_sources_5_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ; - assign plic$v_sources_6_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ; - assign plic$v_sources_7_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ; - assign plic$v_sources_8_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ; - assign plic$v_sources_9_m_interrupt_req_set_not_clear = - core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ; - assign plic$EN_set_verbosity = 1'b0 ; - assign plic$EN_show_PLIC_state = 1'b0 ; - assign plic$EN_server_reset_request_put = - CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign plic$EN_server_reset_response_get = - CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 = - plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset && - cpu$RDY_hart0_server_reset_request_put && - f_reset_reqs$EMPTY_N ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - begin - v__h4310 = $stime; - #0; - end - v__h4304 = v__h4310 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4304); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - begin - v__h4551 = $stime; - #0; - end - v__h4545 = v__h4551 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4545); - end - // synopsys translate_on -endmodule // mkCore - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric.v deleted file mode 100644 index 771fc0dc..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric.v +++ /dev/null @@ -1,8149 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 = - fabric_cfg_verbosity > 4'd1 ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: ERROR: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $display("%0d: %m::AXI4_Fabric.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__0_ULE_1_1___d42) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - $display("%0d: %m::AXI4_Fabric.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v deleted file mode 100644 index 2e372865..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_2x3.v +++ /dev/null @@ -1,7465 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_2x3(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8650; - reg [31 : 0] v__h9025; - reg [31 : 0] v__h9400; - reg [31 : 0] v__h9845; - reg [31 : 0] v__h10214; - reg [31 : 0] v__h10583; - reg [31 : 0] v__h11872; - reg [31 : 0] v__h12325; - reg [31 : 0] v__h12702; - reg [31 : 0] v__h12994; - reg [31 : 0] v__h13286; - reg [31 : 0] v__h13589; - reg [31 : 0] v__h13855; - reg [31 : 0] v__h14121; - reg [31 : 0] v__h14385; - reg [31 : 0] v__h14611; - reg [31 : 0] v__h15040; - reg [31 : 0] v__h15396; - reg [31 : 0] v__h15752; - reg [31 : 0] v__h16169; - reg [31 : 0] v__h16501; - reg [31 : 0] v__h16833; - reg [31 : 0] v__h17849; - reg [31 : 0] v__h18100; - reg [31 : 0] v__h18475; - reg [31 : 0] v__h18716; - reg [31 : 0] v__h19091; - reg [31 : 0] v__h19332; - reg [31 : 0] v__h19694; - reg [31 : 0] v__h19945; - reg [31 : 0] v__h20275; - reg [31 : 0] v__h20516; - reg [31 : 0] v__h20846; - reg [31 : 0] v__h21087; - reg [31 : 0] v__h21600; - reg [31 : 0] v__h22001; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8644; - reg [31 : 0] v__h9019; - reg [31 : 0] v__h9394; - reg [31 : 0] v__h9839; - reg [31 : 0] v__h10208; - reg [31 : 0] v__h10577; - reg [31 : 0] v__h11866; - reg [31 : 0] v__h12319; - reg [31 : 0] v__h12696; - reg [31 : 0] v__h12988; - reg [31 : 0] v__h13280; - reg [31 : 0] v__h13583; - reg [31 : 0] v__h13849; - reg [31 : 0] v__h14115; - reg [31 : 0] v__h14379; - reg [31 : 0] v__h14605; - reg [31 : 0] v__h15034; - reg [31 : 0] v__h15390; - reg [31 : 0] v__h15746; - reg [31 : 0] v__h16163; - reg [31 : 0] v__h16495; - reg [31 : 0] v__h16827; - reg [31 : 0] v__h17843; - reg [31 : 0] v__h18094; - reg [31 : 0] v__h18469; - reg [31 : 0] v__h18710; - reg [31 : 0] v__h19085; - reg [31 : 0] v__h19326; - reg [31 : 0] v__h19688; - reg [31 : 0] v__h19939; - reg [31 : 0] v__h20269; - reg [31 : 0] v__h20510; - reg [31 : 0] v__h20840; - reg [31 : 0] v__h21081; - reg [31 : 0] v__h21594; - reg [31 : 0] v__h21995; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11777, - x__h12230, - x__h17986, - x__h18612, - x__h19228, - x__h21532, - x__h21933; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - x1_avValue_rresp__h17964, - x1_avValue_rresp__h18590, - x1_avValue_rresp__h19206; - wire _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130, - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156, - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371, - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411, - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540, - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138, - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325, - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330, - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - (!soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332) ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - (!soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327) && - soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - 8'd0 : - x__h17986 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - 8'd0 : - x__h18612 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - 8'd0 : - x__h19228 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ? - 8'd0 : - x__h11777 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ? - 8'd0 : - x__h12230 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ? - 8'd0 : - x__h21532 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ? - 8'd0 : - x__h21933 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ; - assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398 = - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 ? - x1_avValue_rresp__h17964 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437 = - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 ? - x1_avValue_rresp__h18590 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476 = - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 ? - x1_avValue_rresp__h19206 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__50_AND_fabri_ETC___d156 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d277 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d282 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d327 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d332 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_near_mem_io_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_plic_addr_lim ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d16 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d275 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d325 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_near_mem_io_addr_base__3_ULE_fabric__ETC___d81 = - soc_map$m_near_mem_io_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d23 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d280 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d330 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_plic_addr_base__2_ULE_fabric_xactors_ETC___d86 = - soc_map$m_plic_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h17964 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18590 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19206 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11777 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12230 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h17986 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h18612 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19228 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21532 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h21933 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8650 = $stime; - #0; - end - v__h8644 = v__h8650 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8644, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9025 = $stime; - #0; - end - v__h9019 = v__h9025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9019, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9400 = $stime; - #0; - end - v__h9394 = v__h9400 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9394, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9845 = $stime; - #0; - end - v__h9839 = v__h9845 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9839, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10214 = $stime; - #0; - end - v__h10208 = v__h10214 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10208, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10583 = $stime; - #0; - end - v__h10577 = v__h10583 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10577, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h11872 = $stime; - #0; - end - v__h11866 = v__h11872 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h11866, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_36_EQ_fabric_v_f_w_ETC___d138 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12325 = $stime; - #0; - end - v__h12319 = v__h12325 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12319, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_62_EQ_fabric_v_f_w_ETC___d164 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12702 = $stime; - #0; - end - v__h12696 = v__h12702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12696, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h12994 = $stime; - #0; - end - v__h12988 = v__h12994 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12988, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13286 = $stime; - #0; - end - v__h13280 = v__h13286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13280, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13589 = $stime; - #0; - end - v__h13583 = v__h13589 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13583, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13855 = $stime; - #0; - end - v__h13849 = v__h13855 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13849, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14121 = $stime; - #0; - end - v__h14115 = v__h14121 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14115, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14385 = $stime; - #0; - end - v__h14379 = v__h14385 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14379, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14611 = $stime; - #0; - end - v__h14605 = v__h14611 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14605, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15040 = $stime; - #0; - end - v__h15034 = v__h15040 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15034, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15396 = $stime; - #0; - end - v__h15390 = v__h15396 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15390, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15752 = $stime; - #0; - end - v__h15746 = v__h15752 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15746, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16169 = $stime; - #0; - end - v__h16163 = v__h16169 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16163, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16501 = $stime; - #0; - end - v__h16495 = v__h16501 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16495, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16833 = $stime; - #0; - end - v__h16827 = v__h16833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16827, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h17849 = $stime; - #0; - end - v__h17843 = v__h17849 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h17843, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18100 = $stime; - #0; - end - v__h18094 = v__h18100 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18094, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18475 = $stime; - #0; - end - v__h18469 = v__h18475 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18469, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h18716 = $stime; - #0; - end - v__h18710 = v__h18716 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18710, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19091 = $stime; - #0; - end - v__h19085 = v__h19091 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19085, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19332 = $stime; - #0; - end - v__h19326 = v__h19332 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19326, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h19694 = $stime; - #0; - end - v__h19688 = v__h19694 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19688, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_rd_ETC___d371 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19945 = $stime; - #0; - end - v__h19939 = v__h19945 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19939, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_69_EQ_fabric_v_f_ETC___d398); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20275 = $stime; - #0; - end - v__h20269 = v__h20275 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20269, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_rd_ETC___d411 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20516 = $stime; - #0; - end - v__h20510 = v__h20516 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20510, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_09_EQ_fabric_v_f_ETC___d437); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h20846 = $stime; - #0; - end - v__h20840 = v__h20846 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20840, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_rd_ETC___d450 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21087 = $stime; - #0; - end - v__h21081 = v__h21087 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21081, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_48_EQ_fabric_v_f_ETC___d476); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21600 = $stime; - #0; - end - v__h21594 = v__h21600 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21594, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22001 = $stime; - #0; - end - v__h21995 = v__h22001 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21995, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_2x3 - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v deleted file mode 100644 index ac19188b..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v +++ /dev/null @@ -1,8145 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// v_to_slaves_1_awvalid O 1 reg -// v_to_slaves_1_awid O 4 reg -// v_to_slaves_1_awaddr O 64 reg -// v_to_slaves_1_awlen O 8 reg -// v_to_slaves_1_awsize O 3 reg -// v_to_slaves_1_awburst O 2 reg -// v_to_slaves_1_awlock O 1 reg -// v_to_slaves_1_awcache O 4 reg -// v_to_slaves_1_awprot O 3 reg -// v_to_slaves_1_awqos O 4 reg -// v_to_slaves_1_awregion O 4 reg -// v_to_slaves_1_wvalid O 1 reg -// v_to_slaves_1_wid O 4 reg -// v_to_slaves_1_wdata O 64 reg -// v_to_slaves_1_wstrb O 8 reg -// v_to_slaves_1_wlast O 1 reg -// v_to_slaves_1_bready O 1 reg -// v_to_slaves_1_arvalid O 1 reg -// v_to_slaves_1_arid O 4 reg -// v_to_slaves_1_araddr O 64 reg -// v_to_slaves_1_arlen O 8 reg -// v_to_slaves_1_arsize O 3 reg -// v_to_slaves_1_arburst O 2 reg -// v_to_slaves_1_arlock O 1 reg -// v_to_slaves_1_arcache O 4 reg -// v_to_slaves_1_arprot O 3 reg -// v_to_slaves_1_arqos O 4 reg -// v_to_slaves_1_arregion O 4 reg -// v_to_slaves_1_rready O 1 reg -// v_to_slaves_2_awvalid O 1 reg -// v_to_slaves_2_awid O 4 reg -// v_to_slaves_2_awaddr O 64 reg -// v_to_slaves_2_awlen O 8 reg -// v_to_slaves_2_awsize O 3 reg -// v_to_slaves_2_awburst O 2 reg -// v_to_slaves_2_awlock O 1 reg -// v_to_slaves_2_awcache O 4 reg -// v_to_slaves_2_awprot O 3 reg -// v_to_slaves_2_awqos O 4 reg -// v_to_slaves_2_awregion O 4 reg -// v_to_slaves_2_wvalid O 1 reg -// v_to_slaves_2_wid O 4 reg -// v_to_slaves_2_wdata O 64 reg -// v_to_slaves_2_wstrb O 8 reg -// v_to_slaves_2_wlast O 1 reg -// v_to_slaves_2_bready O 1 reg -// v_to_slaves_2_arvalid O 1 reg -// v_to_slaves_2_arid O 4 reg -// v_to_slaves_2_araddr O 64 reg -// v_to_slaves_2_arlen O 8 reg -// v_to_slaves_2_arsize O 3 reg -// v_to_slaves_2_arburst O 2 reg -// v_to_slaves_2_arlock O 1 reg -// v_to_slaves_2_arcache O 4 reg -// v_to_slaves_2_arprot O 3 reg -// v_to_slaves_2_arqos O 4 reg -// v_to_slaves_2_arregion O 4 reg -// v_to_slaves_2_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// v_to_slaves_1_awready I 1 -// v_to_slaves_1_wready I 1 -// v_to_slaves_1_bvalid I 1 -// v_to_slaves_1_bid I 4 reg -// v_to_slaves_1_bresp I 2 reg -// v_to_slaves_1_arready I 1 -// v_to_slaves_1_rvalid I 1 -// v_to_slaves_1_rid I 4 reg -// v_to_slaves_1_rdata I 64 reg -// v_to_slaves_1_rresp I 2 reg -// v_to_slaves_1_rlast I 1 reg -// v_to_slaves_2_awready I 1 -// v_to_slaves_2_wready I 1 -// v_to_slaves_2_bvalid I 1 -// v_to_slaves_2_bid I 4 reg -// v_to_slaves_2_bresp I 2 reg -// v_to_slaves_2_arready I 1 -// v_to_slaves_2_rvalid I 1 -// v_to_slaves_2_rid I 4 reg -// v_to_slaves_2_rdata I 64 reg -// v_to_slaves_2_rresp I 2 reg -// v_to_slaves_2_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_AXI4(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready, - - v_to_slaves_1_awvalid, - - v_to_slaves_1_awid, - - v_to_slaves_1_awaddr, - - v_to_slaves_1_awlen, - - v_to_slaves_1_awsize, - - v_to_slaves_1_awburst, - - v_to_slaves_1_awlock, - - v_to_slaves_1_awcache, - - v_to_slaves_1_awprot, - - v_to_slaves_1_awqos, - - v_to_slaves_1_awregion, - - v_to_slaves_1_awready, - - v_to_slaves_1_wvalid, - - v_to_slaves_1_wid, - - v_to_slaves_1_wdata, - - v_to_slaves_1_wstrb, - - v_to_slaves_1_wlast, - - v_to_slaves_1_wready, - - v_to_slaves_1_bvalid, - v_to_slaves_1_bid, - v_to_slaves_1_bresp, - - v_to_slaves_1_bready, - - v_to_slaves_1_arvalid, - - v_to_slaves_1_arid, - - v_to_slaves_1_araddr, - - v_to_slaves_1_arlen, - - v_to_slaves_1_arsize, - - v_to_slaves_1_arburst, - - v_to_slaves_1_arlock, - - v_to_slaves_1_arcache, - - v_to_slaves_1_arprot, - - v_to_slaves_1_arqos, - - v_to_slaves_1_arregion, - - v_to_slaves_1_arready, - - v_to_slaves_1_rvalid, - v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast, - - v_to_slaves_1_rready, - - v_to_slaves_2_awvalid, - - v_to_slaves_2_awid, - - v_to_slaves_2_awaddr, - - v_to_slaves_2_awlen, - - v_to_slaves_2_awsize, - - v_to_slaves_2_awburst, - - v_to_slaves_2_awlock, - - v_to_slaves_2_awcache, - - v_to_slaves_2_awprot, - - v_to_slaves_2_awqos, - - v_to_slaves_2_awregion, - - v_to_slaves_2_awready, - - v_to_slaves_2_wvalid, - - v_to_slaves_2_wid, - - v_to_slaves_2_wdata, - - v_to_slaves_2_wstrb, - - v_to_slaves_2_wlast, - - v_to_slaves_2_wready, - - v_to_slaves_2_bvalid, - v_to_slaves_2_bid, - v_to_slaves_2_bresp, - - v_to_slaves_2_bready, - - v_to_slaves_2_arvalid, - - v_to_slaves_2_arid, - - v_to_slaves_2_araddr, - - v_to_slaves_2_arlen, - - v_to_slaves_2_arsize, - - v_to_slaves_2_arburst, - - v_to_slaves_2_arlock, - - v_to_slaves_2_arcache, - - v_to_slaves_2_arprot, - - v_to_slaves_2_arqos, - - v_to_slaves_2_arregion, - - v_to_slaves_2_arready, - - v_to_slaves_2_rvalid, - v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast, - - v_to_slaves_2_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // value method v_to_slaves_1_m_awvalid - output v_to_slaves_1_awvalid; - - // value method v_to_slaves_1_m_awid - output [3 : 0] v_to_slaves_1_awid; - - // value method v_to_slaves_1_m_awaddr - output [63 : 0] v_to_slaves_1_awaddr; - - // value method v_to_slaves_1_m_awlen - output [7 : 0] v_to_slaves_1_awlen; - - // value method v_to_slaves_1_m_awsize - output [2 : 0] v_to_slaves_1_awsize; - - // value method v_to_slaves_1_m_awburst - output [1 : 0] v_to_slaves_1_awburst; - - // value method v_to_slaves_1_m_awlock - output v_to_slaves_1_awlock; - - // value method v_to_slaves_1_m_awcache - output [3 : 0] v_to_slaves_1_awcache; - - // value method v_to_slaves_1_m_awprot - output [2 : 0] v_to_slaves_1_awprot; - - // value method v_to_slaves_1_m_awqos - output [3 : 0] v_to_slaves_1_awqos; - - // value method v_to_slaves_1_m_awregion - output [3 : 0] v_to_slaves_1_awregion; - - // value method v_to_slaves_1_m_awuser - - // action method v_to_slaves_1_m_awready - input v_to_slaves_1_awready; - - // value method v_to_slaves_1_m_wvalid - output v_to_slaves_1_wvalid; - - // value method v_to_slaves_1_m_wid - output [3 : 0] v_to_slaves_1_wid; - - // value method v_to_slaves_1_m_wdata - output [63 : 0] v_to_slaves_1_wdata; - - // value method v_to_slaves_1_m_wstrb - output [7 : 0] v_to_slaves_1_wstrb; - - // value method v_to_slaves_1_m_wlast - output v_to_slaves_1_wlast; - - // value method v_to_slaves_1_m_wuser - - // action method v_to_slaves_1_m_wready - input v_to_slaves_1_wready; - - // action method v_to_slaves_1_m_bvalid - input v_to_slaves_1_bvalid; - input [3 : 0] v_to_slaves_1_bid; - input [1 : 0] v_to_slaves_1_bresp; - - // value method v_to_slaves_1_m_bready - output v_to_slaves_1_bready; - - // value method v_to_slaves_1_m_arvalid - output v_to_slaves_1_arvalid; - - // value method v_to_slaves_1_m_arid - output [3 : 0] v_to_slaves_1_arid; - - // value method v_to_slaves_1_m_araddr - output [63 : 0] v_to_slaves_1_araddr; - - // value method v_to_slaves_1_m_arlen - output [7 : 0] v_to_slaves_1_arlen; - - // value method v_to_slaves_1_m_arsize - output [2 : 0] v_to_slaves_1_arsize; - - // value method v_to_slaves_1_m_arburst - output [1 : 0] v_to_slaves_1_arburst; - - // value method v_to_slaves_1_m_arlock - output v_to_slaves_1_arlock; - - // value method v_to_slaves_1_m_arcache - output [3 : 0] v_to_slaves_1_arcache; - - // value method v_to_slaves_1_m_arprot - output [2 : 0] v_to_slaves_1_arprot; - - // value method v_to_slaves_1_m_arqos - output [3 : 0] v_to_slaves_1_arqos; - - // value method v_to_slaves_1_m_arregion - output [3 : 0] v_to_slaves_1_arregion; - - // value method v_to_slaves_1_m_aruser - - // action method v_to_slaves_1_m_arready - input v_to_slaves_1_arready; - - // action method v_to_slaves_1_m_rvalid - input v_to_slaves_1_rvalid; - input [3 : 0] v_to_slaves_1_rid; - input [63 : 0] v_to_slaves_1_rdata; - input [1 : 0] v_to_slaves_1_rresp; - input v_to_slaves_1_rlast; - - // value method v_to_slaves_1_m_rready - output v_to_slaves_1_rready; - - // value method v_to_slaves_2_m_awvalid - output v_to_slaves_2_awvalid; - - // value method v_to_slaves_2_m_awid - output [3 : 0] v_to_slaves_2_awid; - - // value method v_to_slaves_2_m_awaddr - output [63 : 0] v_to_slaves_2_awaddr; - - // value method v_to_slaves_2_m_awlen - output [7 : 0] v_to_slaves_2_awlen; - - // value method v_to_slaves_2_m_awsize - output [2 : 0] v_to_slaves_2_awsize; - - // value method v_to_slaves_2_m_awburst - output [1 : 0] v_to_slaves_2_awburst; - - // value method v_to_slaves_2_m_awlock - output v_to_slaves_2_awlock; - - // value method v_to_slaves_2_m_awcache - output [3 : 0] v_to_slaves_2_awcache; - - // value method v_to_slaves_2_m_awprot - output [2 : 0] v_to_slaves_2_awprot; - - // value method v_to_slaves_2_m_awqos - output [3 : 0] v_to_slaves_2_awqos; - - // value method v_to_slaves_2_m_awregion - output [3 : 0] v_to_slaves_2_awregion; - - // value method v_to_slaves_2_m_awuser - - // action method v_to_slaves_2_m_awready - input v_to_slaves_2_awready; - - // value method v_to_slaves_2_m_wvalid - output v_to_slaves_2_wvalid; - - // value method v_to_slaves_2_m_wid - output [3 : 0] v_to_slaves_2_wid; - - // value method v_to_slaves_2_m_wdata - output [63 : 0] v_to_slaves_2_wdata; - - // value method v_to_slaves_2_m_wstrb - output [7 : 0] v_to_slaves_2_wstrb; - - // value method v_to_slaves_2_m_wlast - output v_to_slaves_2_wlast; - - // value method v_to_slaves_2_m_wuser - - // action method v_to_slaves_2_m_wready - input v_to_slaves_2_wready; - - // action method v_to_slaves_2_m_bvalid - input v_to_slaves_2_bvalid; - input [3 : 0] v_to_slaves_2_bid; - input [1 : 0] v_to_slaves_2_bresp; - - // value method v_to_slaves_2_m_bready - output v_to_slaves_2_bready; - - // value method v_to_slaves_2_m_arvalid - output v_to_slaves_2_arvalid; - - // value method v_to_slaves_2_m_arid - output [3 : 0] v_to_slaves_2_arid; - - // value method v_to_slaves_2_m_araddr - output [63 : 0] v_to_slaves_2_araddr; - - // value method v_to_slaves_2_m_arlen - output [7 : 0] v_to_slaves_2_arlen; - - // value method v_to_slaves_2_m_arsize - output [2 : 0] v_to_slaves_2_arsize; - - // value method v_to_slaves_2_m_arburst - output [1 : 0] v_to_slaves_2_arburst; - - // value method v_to_slaves_2_m_arlock - output v_to_slaves_2_arlock; - - // value method v_to_slaves_2_m_arcache - output [3 : 0] v_to_slaves_2_arcache; - - // value method v_to_slaves_2_m_arprot - output [2 : 0] v_to_slaves_2_arprot; - - // value method v_to_slaves_2_m_arqos - output [3 : 0] v_to_slaves_2_arqos; - - // value method v_to_slaves_2_m_arregion - output [3 : 0] v_to_slaves_2_arregion; - - // value method v_to_slaves_2_m_aruser - - // action method v_to_slaves_2_m_arready - input v_to_slaves_2_arready; - - // action method v_to_slaves_2_m_rvalid - input v_to_slaves_2_rvalid; - input [3 : 0] v_to_slaves_2_rid; - input [63 : 0] v_to_slaves_2_rdata; - input [1 : 0] v_to_slaves_2_rresp; - input v_to_slaves_2_rlast; - - // value method v_to_slaves_2_m_rready - output v_to_slaves_2_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata, - v_to_slaves_1_araddr, - v_to_slaves_1_awaddr, - v_to_slaves_1_wdata, - v_to_slaves_2_araddr, - v_to_slaves_2_awaddr, - v_to_slaves_2_wdata; - wire [7 : 0] v_to_slaves_0_arlen, - v_to_slaves_0_awlen, - v_to_slaves_0_wstrb, - v_to_slaves_1_arlen, - v_to_slaves_1_awlen, - v_to_slaves_1_wstrb, - v_to_slaves_2_arlen, - v_to_slaves_2_awlen, - v_to_slaves_2_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid, - v_to_slaves_1_arcache, - v_to_slaves_1_arid, - v_to_slaves_1_arqos, - v_to_slaves_1_arregion, - v_to_slaves_1_awcache, - v_to_slaves_1_awid, - v_to_slaves_1_awqos, - v_to_slaves_1_awregion, - v_to_slaves_1_wid, - v_to_slaves_2_arcache, - v_to_slaves_2_arid, - v_to_slaves_2_arqos, - v_to_slaves_2_arregion, - v_to_slaves_2_awcache, - v_to_slaves_2_awid, - v_to_slaves_2_awqos, - v_to_slaves_2_awregion, - v_to_slaves_2_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize, - v_to_slaves_1_arprot, - v_to_slaves_1_arsize, - v_to_slaves_1_awprot, - v_to_slaves_1_awsize, - v_to_slaves_2_arprot, - v_to_slaves_2_arsize, - v_to_slaves_2_awprot, - v_to_slaves_2_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst, - v_to_slaves_1_arburst, - v_to_slaves_1_awburst, - v_to_slaves_2_arburst, - v_to_slaves_2_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid, - v_to_slaves_1_arlock, - v_to_slaves_1_arvalid, - v_to_slaves_1_awlock, - v_to_slaves_1_awvalid, - v_to_slaves_1_bready, - v_to_slaves_1_rready, - v_to_slaves_1_wlast, - v_to_slaves_1_wvalid, - v_to_slaves_2_arlock, - v_to_slaves_2_arvalid, - v_to_slaves_2_awlock, - v_to_slaves_2_awvalid, - v_to_slaves_2_bready, - v_to_slaves_2_rready, - v_to_slaves_2_wlast, - v_to_slaves_2_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // register fabric_v_rg_r_beat_count_0 - reg [7 : 0] fabric_v_rg_r_beat_count_0; - reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN; - wire fabric_v_rg_r_beat_count_0$EN; - - // register fabric_v_rg_r_beat_count_1 - reg [7 : 0] fabric_v_rg_r_beat_count_1; - reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN; - wire fabric_v_rg_r_beat_count_1$EN; - - // register fabric_v_rg_r_beat_count_2 - reg [7 : 0] fabric_v_rg_r_beat_count_2; - reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN; - wire fabric_v_rg_r_beat_count_2$EN; - - // register fabric_v_rg_r_err_beat_count_0 - reg [7 : 0] fabric_v_rg_r_err_beat_count_0; - wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN; - wire fabric_v_rg_r_err_beat_count_0$EN; - - // register fabric_v_rg_r_err_beat_count_1 - reg [7 : 0] fabric_v_rg_r_err_beat_count_1; - wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN; - wire fabric_v_rg_r_err_beat_count_1$EN; - - // register fabric_v_rg_wd_beat_count_0 - reg [7 : 0] fabric_v_rg_wd_beat_count_0; - wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN; - wire fabric_v_rg_wd_beat_count_0$EN; - - // register fabric_v_rg_wd_beat_count_1 - reg [7 : 0] fabric_v_rg_wd_beat_count_1; - wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN; - wire fabric_v_rg_wd_beat_count_1$EN; - - // ports of submodule fabric_v_f_rd_err_info_0 - wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT; - wire fabric_v_f_rd_err_info_0$CLR, - fabric_v_f_rd_err_info_0$DEQ, - fabric_v_f_rd_err_info_0$EMPTY_N, - fabric_v_f_rd_err_info_0$ENQ, - fabric_v_f_rd_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_rd_err_info_1 - wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT; - wire fabric_v_f_rd_err_info_1$CLR, - fabric_v_f_rd_err_info_1$DEQ, - fabric_v_f_rd_err_info_1$EMPTY_N, - fabric_v_f_rd_err_info_1$ENQ, - fabric_v_f_rd_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_1 - wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT; - wire fabric_v_f_rd_mis_1$CLR, - fabric_v_f_rd_mis_1$DEQ, - fabric_v_f_rd_mis_1$EMPTY_N, - fabric_v_f_rd_mis_1$ENQ, - fabric_v_f_rd_mis_1$FULL_N; - - // ports of submodule fabric_v_f_rd_mis_2 - wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT; - wire fabric_v_f_rd_mis_2$CLR, - fabric_v_f_rd_mis_2$DEQ, - fabric_v_f_rd_mis_2$EMPTY_N, - fabric_v_f_rd_mis_2$ENQ, - fabric_v_f_rd_mis_2$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT; - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT; - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_0 - reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT; - wire fabric_v_f_wd_tasks_0$CLR, - fabric_v_f_wd_tasks_0$DEQ, - fabric_v_f_wd_tasks_0$EMPTY_N, - fabric_v_f_wd_tasks_0$ENQ, - fabric_v_f_wd_tasks_0$FULL_N; - - // ports of submodule fabric_v_f_wd_tasks_1 - reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN; - wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT; - wire fabric_v_f_wd_tasks_1$CLR, - fabric_v_f_wd_tasks_1$DEQ, - fabric_v_f_wd_tasks_1$EMPTY_N, - fabric_v_f_wd_tasks_1$ENQ, - fabric_v_f_wd_tasks_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_0 - wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT; - wire fabric_v_f_wr_err_info_0$CLR, - fabric_v_f_wr_err_info_0$DEQ, - fabric_v_f_wr_err_info_0$EMPTY_N, - fabric_v_f_wr_err_info_0$ENQ, - fabric_v_f_wr_err_info_0$FULL_N; - - // ports of submodule fabric_v_f_wr_err_info_1 - wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT; - wire fabric_v_f_wr_err_info_1$CLR, - fabric_v_f_wr_err_info_1$DEQ, - fabric_v_f_wr_err_info_1$EMPTY_N, - fabric_v_f_wr_err_info_1$ENQ, - fabric_v_f_wr_err_info_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_0 - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$D_IN, - fabric_v_f_wr_mis_0$D_OUT, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_1 - wire fabric_v_f_wr_mis_1$CLR, - fabric_v_f_wr_mis_1$DEQ, - fabric_v_f_wr_mis_1$D_IN, - fabric_v_f_wr_mis_1$D_OUT, - fabric_v_f_wr_mis_1$EMPTY_N, - fabric_v_f_wr_mis_1$ENQ, - fabric_v_f_wr_mis_1$FULL_N; - - // ports of submodule fabric_v_f_wr_mis_2 - wire fabric_v_f_wr_mis_2$CLR, - fabric_v_f_wr_mis_2$DEQ, - fabric_v_f_wr_mis_2$D_IN, - fabric_v_f_wr_mis_2$D_OUT, - fabric_v_f_wr_mis_2$EMPTY_N, - fabric_v_f_wr_mis_2$ENQ, - fabric_v_f_wr_mis_2$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT; - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN; - wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT; - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN; - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN; - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN, - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_addr$CLR, - fabric_xactors_to_slaves_1_f_rd_addr$DEQ, - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_addr$ENQ, - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_rd_data$CLR, - fabric_xactors_to_slaves_1_f_rd_data$DEQ, - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_rd_data$ENQ, - fabric_xactors_to_slaves_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN, - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_addr$CLR, - fabric_xactors_to_slaves_1_f_wr_addr$DEQ, - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_addr$ENQ, - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN, - fabric_xactors_to_slaves_1_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_data$CLR, - fabric_xactors_to_slaves_1_f_wr_data$DEQ, - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_data$ENQ, - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_1_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN, - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_1_f_wr_resp$CLR, - fabric_xactors_to_slaves_1_f_wr_resp$DEQ, - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_1_f_wr_resp$ENQ, - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN, - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_addr$CLR, - fabric_xactors_to_slaves_2_f_rd_addr$DEQ, - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_addr$ENQ, - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_rd_data$CLR, - fabric_xactors_to_slaves_2_f_rd_data$DEQ, - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_rd_data$ENQ, - fabric_xactors_to_slaves_2_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN, - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_addr$CLR, - fabric_xactors_to_slaves_2_f_wr_addr$DEQ, - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_addr$ENQ, - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN, - fabric_xactors_to_slaves_2_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_data$CLR, - fabric_xactors_to_slaves_2_f_wr_data$DEQ, - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_data$ENQ, - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_2_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN, - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_2_f_wr_resp$CLR, - fabric_xactors_to_slaves_2_f_wr_resp$DEQ, - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_2_f_wr_resp$ENQ, - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - CAN_FIRE_v_to_slaves_1_m_arready, - CAN_FIRE_v_to_slaves_1_m_awready, - CAN_FIRE_v_to_slaves_1_m_bvalid, - CAN_FIRE_v_to_slaves_1_m_rvalid, - CAN_FIRE_v_to_slaves_1_m_wready, - CAN_FIRE_v_to_slaves_2_m_arready, - CAN_FIRE_v_to_slaves_2_m_awready, - CAN_FIRE_v_to_slaves_2_m_bvalid, - CAN_FIRE_v_to_slaves_2_m_rvalid, - CAN_FIRE_v_to_slaves_2_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_v_to_slaves_1_m_arready, - WILL_FIRE_v_to_slaves_1_m_awready, - WILL_FIRE_v_to_slaves_1_m_bvalid, - WILL_FIRE_v_to_slaves_1_m_rvalid, - WILL_FIRE_v_to_slaves_1_m_wready, - WILL_FIRE_v_to_slaves_2_m_arready, - WILL_FIRE_v_to_slaves_2_m_awready, - WILL_FIRE_v_to_slaves_2_m_bvalid, - WILL_FIRE_v_to_slaves_2_m_rvalid, - WILL_FIRE_v_to_slaves_2_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3, - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3, - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - wire [8 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1, - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2; - wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2, - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2, - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1, - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8683; - reg [31 : 0] v__h9083; - reg [31 : 0] v__h9483; - reg [31 : 0] v__h9953; - reg [31 : 0] v__h10347; - reg [31 : 0] v__h10741; - reg [31 : 0] v__h11192; - reg [31 : 0] v__h11599; - reg [31 : 0] v__h12074; - reg [31 : 0] v__h12527; - reg [31 : 0] v__h12904; - reg [31 : 0] v__h13196; - reg [31 : 0] v__h13488; - reg [31 : 0] v__h13791; - reg [31 : 0] v__h14057; - reg [31 : 0] v__h14323; - reg [31 : 0] v__h14587; - reg [31 : 0] v__h14813; - reg [31 : 0] v__h15267; - reg [31 : 0] v__h15648; - reg [31 : 0] v__h16029; - reg [31 : 0] v__h16471; - reg [31 : 0] v__h16828; - reg [31 : 0] v__h17185; - reg [31 : 0] v__h17536; - reg [31 : 0] v__h17837; - reg [31 : 0] v__h18245; - reg [31 : 0] v__h18496; - reg [31 : 0] v__h18871; - reg [31 : 0] v__h19112; - reg [31 : 0] v__h19487; - reg [31 : 0] v__h19728; - reg [31 : 0] v__h20090; - reg [31 : 0] v__h20341; - reg [31 : 0] v__h20671; - reg [31 : 0] v__h20912; - reg [31 : 0] v__h21242; - reg [31 : 0] v__h21483; - reg [31 : 0] v__h21996; - reg [31 : 0] v__h22397; - reg [31 : 0] v__h5698; - reg [31 : 0] v__h5692; - reg [31 : 0] v__h8677; - reg [31 : 0] v__h9077; - reg [31 : 0] v__h9477; - reg [31 : 0] v__h9947; - reg [31 : 0] v__h10341; - reg [31 : 0] v__h10735; - reg [31 : 0] v__h11186; - reg [31 : 0] v__h11593; - reg [31 : 0] v__h12068; - reg [31 : 0] v__h12521; - reg [31 : 0] v__h12898; - reg [31 : 0] v__h13190; - reg [31 : 0] v__h13482; - reg [31 : 0] v__h13785; - reg [31 : 0] v__h14051; - reg [31 : 0] v__h14317; - reg [31 : 0] v__h14581; - reg [31 : 0] v__h14807; - reg [31 : 0] v__h15261; - reg [31 : 0] v__h15642; - reg [31 : 0] v__h16023; - reg [31 : 0] v__h16465; - reg [31 : 0] v__h16822; - reg [31 : 0] v__h17179; - reg [31 : 0] v__h17530; - reg [31 : 0] v__h17831; - reg [31 : 0] v__h18239; - reg [31 : 0] v__h18490; - reg [31 : 0] v__h18865; - reg [31 : 0] v__h19106; - reg [31 : 0] v__h19481; - reg [31 : 0] v__h19722; - reg [31 : 0] v__h20084; - reg [31 : 0] v__h20335; - reg [31 : 0] v__h20665; - reg [31 : 0] v__h20906; - reg [31 : 0] v__h21236; - reg [31 : 0] v__h21477; - reg [31 : 0] v__h21990; - reg [31 : 0] v__h22391; - // synopsys translate_on - - // remaining internal signals - reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1, - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2; - wire [7 : 0] x__h11979, - x__h12432, - x__h18382, - x__h19008, - x__h19624, - x__h21928, - x__h22329; - wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342, - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398, - x1_avValue_rresp__h18360, - x1_avValue_rresp__h18986, - x1_avValue_rresp__h19602; - wire NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441, - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459, - _dor1fabric_v_f_rd_mis_0$EN_deq, - _dor1fabric_v_f_rd_mis_1$EN_deq, - _dor1fabric_v_f_rd_mis_2$EN_deq, - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185, - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210, - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473, - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513, - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642, - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193, - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333, - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23, - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389, - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93, - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388, - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89, - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391, - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // value method v_to_slaves_1_m_awvalid - assign v_to_slaves_1_awvalid = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_awid - assign v_to_slaves_1_awid = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_awaddr - assign v_to_slaves_1_awaddr = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_awlen - assign v_to_slaves_1_awlen = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_awsize - assign v_to_slaves_1_awsize = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_awburst - assign v_to_slaves_1_awburst = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_awlock - assign v_to_slaves_1_awlock = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_awcache - assign v_to_slaves_1_awcache = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_awprot - assign v_to_slaves_1_awprot = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_awqos - assign v_to_slaves_1_awqos = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_awregion - assign v_to_slaves_1_awregion = - fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_awready - assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ; - - // value method v_to_slaves_1_m_wvalid - assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_1_m_wid - assign v_to_slaves_1_wid = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_1_m_wdata - assign v_to_slaves_1_wdata = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_1_m_wstrb - assign v_to_slaves_1_wstrb = - fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_1_m_wlast - assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_1_m_wready - assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ; - - // action method v_to_slaves_1_m_bvalid - assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ; - - // value method v_to_slaves_1_m_bready - assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - - // value method v_to_slaves_1_m_arvalid - assign v_to_slaves_1_arvalid = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_1_m_arid - assign v_to_slaves_1_arid = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_1_m_araddr - assign v_to_slaves_1_araddr = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_1_m_arlen - assign v_to_slaves_1_arlen = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_1_m_arsize - assign v_to_slaves_1_arsize = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_1_m_arburst - assign v_to_slaves_1_arburst = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_1_m_arlock - assign v_to_slaves_1_arlock = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_1_m_arcache - assign v_to_slaves_1_arcache = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_1_m_arprot - assign v_to_slaves_1_arprot = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_1_m_arqos - assign v_to_slaves_1_arqos = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_1_m_arregion - assign v_to_slaves_1_arregion = - fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_1_m_arready - assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ; - - // action method v_to_slaves_1_m_rvalid - assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ; - - // value method v_to_slaves_1_m_rready - assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - - // value method v_to_slaves_2_m_awvalid - assign v_to_slaves_2_awvalid = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_awid - assign v_to_slaves_2_awid = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_awaddr - assign v_to_slaves_2_awaddr = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_awlen - assign v_to_slaves_2_awlen = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_awsize - assign v_to_slaves_2_awsize = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_awburst - assign v_to_slaves_2_awburst = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_awlock - assign v_to_slaves_2_awlock = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_awcache - assign v_to_slaves_2_awcache = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_awprot - assign v_to_slaves_2_awprot = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_awqos - assign v_to_slaves_2_awqos = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_awregion - assign v_to_slaves_2_awregion = - fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_awready - assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ; - - // value method v_to_slaves_2_m_wvalid - assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_2_m_wid - assign v_to_slaves_2_wid = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_2_m_wdata - assign v_to_slaves_2_wdata = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_2_m_wstrb - assign v_to_slaves_2_wstrb = - fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_2_m_wlast - assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_2_m_wready - assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ; - - // action method v_to_slaves_2_m_bvalid - assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ; - - // value method v_to_slaves_2_m_bready - assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - - // value method v_to_slaves_2_m_arvalid - assign v_to_slaves_2_arvalid = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_2_m_arid - assign v_to_slaves_2_arid = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_2_m_araddr - assign v_to_slaves_2_araddr = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_2_m_arlen - assign v_to_slaves_2_arlen = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_2_m_arsize - assign v_to_slaves_2_arsize = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_2_m_arburst - assign v_to_slaves_2_arburst = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_2_m_arlock - assign v_to_slaves_2_arlock = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_2_m_arcache - assign v_to_slaves_2_arcache = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_2_m_arprot - assign v_to_slaves_2_arprot = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_2_m_arqos - assign v_to_slaves_2_arqos = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_2_m_arregion - assign v_to_slaves_2_arregion = - fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_2_m_arready - assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ; - - // action method v_to_slaves_2_m_rvalid - assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ; - - // value method v_to_slaves_2_m_rready - assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_info_0 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_0$D_IN), - .ENQ(fabric_v_f_rd_err_info_0$ENQ), - .DEQ(fabric_v_f_rd_err_info_0$DEQ), - .CLR(fabric_v_f_rd_err_info_0$CLR), - .D_OUT(fabric_v_f_rd_err_info_0$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_info_1 - SizedFIFO #(.p1width(32'd12), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_info_1$D_IN), - .ENQ(fabric_v_f_rd_err_info_1$ENQ), - .DEQ(fabric_v_f_rd_err_info_1$DEQ), - .CLR(fabric_v_f_rd_err_info_1$CLR), - .D_OUT(fabric_v_f_rd_err_info_1$D_OUT), - .FULL_N(fabric_v_f_rd_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_1 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_1$D_IN), - .ENQ(fabric_v_f_rd_mis_1$ENQ), - .DEQ(fabric_v_f_rd_mis_1$DEQ), - .CLR(fabric_v_f_rd_mis_1$CLR), - .D_OUT(fabric_v_f_rd_mis_1$D_OUT), - .FULL_N(fabric_v_f_rd_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_2 - SizedFIFO #(.p1width(32'd9), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_2$D_IN), - .ENQ(fabric_v_f_rd_mis_2$ENQ), - .DEQ(fabric_v_f_rd_mis_2$DEQ), - .CLR(fabric_v_f_rd_mis_2$CLR), - .D_OUT(fabric_v_f_rd_mis_2$D_OUT), - .FULL_N(fabric_v_f_rd_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_0 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_0$D_IN), - .ENQ(fabric_v_f_wd_tasks_0$ENQ), - .DEQ(fabric_v_f_wd_tasks_0$DEQ), - .CLR(fabric_v_f_wd_tasks_0$CLR), - .D_OUT(fabric_v_f_wd_tasks_0$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_0$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N)); - - // submodule fabric_v_f_wd_tasks_1 - FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wd_tasks_1$D_IN), - .ENQ(fabric_v_f_wd_tasks_1$ENQ), - .DEQ(fabric_v_f_wd_tasks_1$DEQ), - .CLR(fabric_v_f_wd_tasks_1$CLR), - .D_OUT(fabric_v_f_wd_tasks_1$D_OUT), - .FULL_N(fabric_v_f_wd_tasks_1$FULL_N), - .EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_0$D_IN), - .ENQ(fabric_v_f_wr_err_info_0$ENQ), - .DEQ(fabric_v_f_wr_err_info_0$DEQ), - .CLR(fabric_v_f_wr_err_info_0$CLR), - .D_OUT(fabric_v_f_wr_err_info_0$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_info_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_info_1$D_IN), - .ENQ(fabric_v_f_wr_err_info_1$ENQ), - .DEQ(fabric_v_f_wr_err_info_1$DEQ), - .CLR(fabric_v_f_wr_err_info_1$CLR), - .D_OUT(fabric_v_f_wr_err_info_1$D_OUT), - .FULL_N(fabric_v_f_wr_err_info_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_1$D_IN), - .ENQ(fabric_v_f_wr_mis_1$ENQ), - .DEQ(fabric_v_f_wr_mis_1$DEQ), - .CLR(fabric_v_f_wr_mis_1$CLR), - .D_OUT(fabric_v_f_wr_mis_1$D_OUT), - .FULL_N(fabric_v_f_wr_mis_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_2 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_2$D_IN), - .ENQ(fabric_v_f_wr_mis_2$ENQ), - .DEQ(fabric_v_f_wr_mis_2$DEQ), - .CLR(fabric_v_f_wr_mis_2$CLR), - .D_OUT(fabric_v_f_wr_mis_2$D_OUT), - .FULL_N(fabric_v_f_wr_mis_2$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_wr_addr$FULL_N && - fabric_v_f_wr_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_v_f_wd_tasks_1$FULL_N && - fabric_v_f_wr_sjs_1$FULL_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_data_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - !WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - !fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - !fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - fabric_v_f_wr_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_1$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - fabric_v_f_wr_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_2$D_OUT && - fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_info_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_2 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_3 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_4 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - fabric_xactors_to_slaves_1_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_1$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_5 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - fabric_xactors_to_slaves_2_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_2$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 && - IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 == - 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_0$FULL_N && - fabric_v_f_rd_err_info_0$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - - // rule RL_fabric_rl_rd_xaction_no_such_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N && - fabric_v_f_rd_err_info_1$FULL_N && - NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - (fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_2 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - (fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) && - (!fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - fabric_v_f_rd_sjs_0$EMPTY_N) && - !fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_3 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_0$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_4 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - fabric_v_f_rd_mis_1$EMPTY_N && - fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_1$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_5 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - fabric_v_f_rd_mis_2$EMPTY_N && - fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_v_f_rd_mis_2$D_OUT[8] && - fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_info_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ; - assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ; - assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 = - { 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 = - { 1'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 = - { 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 = - { 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 = - { 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 = - { 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ; - assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - 8'd0 : - x__h18382 ; - assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - 8'd0 : - x__h19008 ; - assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - 8'd0 : - x__h19624 ; - assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ? - 8'd0 : - x__h11979 ; - assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 = - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ? - 8'd0 : - x__h12432 ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539, - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_0$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 = - { fabric_v_f_rd_err_info_1$D_OUT[3:0], - 66'd3, - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 = - { fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // register fabric_v_rg_r_beat_count_0 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_v_rg_r_beat_count_0$D_IN = - MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_0$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_1 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_v_rg_r_beat_count_1$D_IN = - MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_1$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - fabric_rg_reset ; - - // register fabric_v_rg_r_beat_count_2 - always@(fabric_rg_reset or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2) - case (1'b1) - fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_v_rg_r_beat_count_2$D_IN = - MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2; - default: fabric_v_rg_r_beat_count_2$D_IN = - 8'b10101010 /* unspecified value */ ; - endcase - assign fabric_v_rg_r_beat_count_2$EN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - fabric_rg_reset ; - - // register fabric_v_rg_r_err_beat_count_0 - assign fabric_v_rg_r_err_beat_count_0$D_IN = - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ? - 8'd0 : - x__h21928 ; - assign fabric_v_rg_r_err_beat_count_0$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // register fabric_v_rg_r_err_beat_count_1 - assign fabric_v_rg_r_err_beat_count_1$D_IN = - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ? - 8'd0 : - x__h22329 ; - assign fabric_v_rg_r_err_beat_count_1$EN = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // register fabric_v_rg_wd_beat_count_0 - assign fabric_v_rg_wd_beat_count_0$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_0$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - fabric_rg_reset ; - - // register fabric_v_rg_wd_beat_count_1 - assign fabric_v_rg_wd_beat_count_1$D_IN = - fabric_rg_reset ? - 8'd0 : - MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ; - assign fabric_v_rg_wd_beat_count_1$EN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_0 - assign fabric_v_f_rd_err_info_0$D_IN = - { fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_err_info_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_info_1 - assign fabric_v_f_rd_err_info_1$D_IN = - { fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21], - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ; - assign fabric_v_f_rd_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_err_info_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_v_f_rd_mis_0$DEQ = - _dor1fabric_v_f_rd_mis_0$EN_deq && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_1 - assign fabric_v_f_rd_mis_1$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_v_f_rd_mis_1$DEQ = - _dor1fabric_v_f_rd_mis_1$EN_deq && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ; - assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_2 - assign fabric_v_f_rd_mis_2$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 : - MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ; - assign fabric_v_f_rd_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_v_f_rd_mis_2$DEQ = - _dor1fabric_v_f_rd_mis_2$EN_deq && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ; - assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1: - fabric_v_f_rd_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2: - fabric_v_f_rd_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave: - fabric_v_f_rd_sjs_0$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3: - fabric_v_f_rd_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4: - fabric_v_f_rd_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5: - fabric_v_f_rd_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1: - fabric_v_f_rd_sjs_1$D_IN = 2'd3; - default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or - MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_0$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wd_tasks_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 ; - assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wd_tasks_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or - MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4; - default: fabric_v_f_wd_tasks_1$D_IN = - 10'b1010101010 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wd_tasks_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wd_tasks_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 ; - assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_0 - assign fabric_v_f_wr_err_info_0$D_IN = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_err_info_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_info_1 - assign fabric_v_f_wr_err_info_1$D_IN = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ; - assign fabric_v_f_wr_err_info_1$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_err_info_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_1 - assign fabric_v_f_wr_mis_1$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_v_f_wr_mis_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_2 - assign fabric_v_f_wr_mis_2$D_IN = - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ; - assign fabric_v_f_wr_mis_2$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_v_f_wr_mis_2$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1: - fabric_v_f_wr_sjs_0$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2: - fabric_v_f_wr_sjs_0$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave: - fabric_v_f_wr_sjs_0$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3: - fabric_v_f_wr_sjs_1$D_IN = 2'd0; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4: - fabric_v_f_wr_sjs_1$D_IN = 2'd1; - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5: - fabric_v_f_wr_sjs_1$D_IN = 2'd2; - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1: - fabric_v_f_wr_sjs_1$D_IN = 2'd3; - default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master: - fabric_xactors_from_masters_0_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_0_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_rd_data$D_IN = - 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_1_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - fabric_xactors_to_slaves_2_f_wr_resp$D_OUT; - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1: - fabric_xactors_from_masters_1_f_wr_resp$D_IN = - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4; - default: fabric_xactors_from_masters_1_f_wr_resp$D_IN = - 6'b101010 /* unspecified value */ ; - endcase - end - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_addr - assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ = - fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N && - v_to_slaves_1_arready ; - assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_rd_data - assign fabric_xactors_to_slaves_1_f_rd_data$D_IN = - { v_to_slaves_1_rid, - v_to_slaves_1_rdata, - v_to_slaves_1_rresp, - v_to_slaves_1_rlast } ; - assign fabric_xactors_to_slaves_1_f_rd_data$ENQ = - v_to_slaves_1_rvalid && - fabric_xactors_to_slaves_1_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_1_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_addr - assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ; - assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ = - fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N && - v_to_slaves_1_awready ; - assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_data - assign fabric_xactors_to_slaves_1_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_1_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ; - assign fabric_xactors_to_slaves_1_f_wr_data$DEQ = - fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N && - v_to_slaves_1_wready ; - assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_1_f_wr_resp - assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN = - { v_to_slaves_1_bid, v_to_slaves_1_bresp } ; - assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ = - v_to_slaves_1_bvalid && - fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_addr - assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ = - fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N && - v_to_slaves_2_arready ; - assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_rd_data - assign fabric_xactors_to_slaves_2_f_rd_data$D_IN = - { v_to_slaves_2_rid, - v_to_slaves_2_rdata, - v_to_slaves_2_rresp, - v_to_slaves_2_rlast } ; - assign fabric_xactors_to_slaves_2_f_rd_data$ENQ = - v_to_slaves_2_rvalid && - fabric_xactors_to_slaves_2_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_2_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_addr - assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ; - assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ = - fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N && - v_to_slaves_2_awready ; - assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_data - assign fabric_xactors_to_slaves_2_f_wr_data$D_IN = - MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_2_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ; - assign fabric_xactors_to_slaves_2_f_wr_data$DEQ = - fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N && - v_to_slaves_2_wready ; - assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_2_f_wr_resp - assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN = - { v_to_slaves_2_bid, v_to_slaves_2_bresp } ; - assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ = - v_to_slaves_2_bvalid && - fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ; - assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500 = - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 ? - x1_avValue_rresp__h18360 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539 = - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 ? - x1_avValue_rresp__h18986 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578 = - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 ? - x1_avValue_rresp__h19602 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d102 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d34 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d342 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) ? - 2'd0 : - 2'd2) ; - assign IF_soc_map_m_mem0_controller_addr_base__3_ULE__ETC___d398 = - (soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) ? - 2'd1 : - ((soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) ? - 2'd0 : - 2'd2) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d150 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 || - !fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d171 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 || - !fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d441 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 || - !fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336) ; - assign NOT_soc_map_m_mem0_controller_addr_base__3_ULE_ETC___d459 = - (!soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386) && - (!soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389) && - (!soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 || - !fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392) ; - assign _dor1fabric_v_f_rd_mis_0$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign _dor1fabric_v_f_rd_mis_1$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign _dor1fabric_v_f_rd_mis_2$EN_deq = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ; - assign fabric_v_f_wd_tasks_0_i_notEmpty__76_AND_fabri_ETC___d185 = - fabric_v_f_wd_tasks_0$EMPTY_N && - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ; - assign fabric_v_f_wd_tasks_1_i_notEmpty__04_AND_fabri_ETC___d210 = - fabric_v_f_wd_tasks_1$EMPTY_N && - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ; - assign fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 = - fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 = - fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ; - assign fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 = - fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ; - assign fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624 = - fabric_v_rg_r_err_beat_count_0 == - fabric_v_f_rd_err_info_0$D_OUT[11:4] ; - assign fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642 = - fabric_v_rg_r_err_beat_count_1 == - fabric_v_f_rd_err_info_1$D_OUT[11:4] ; - assign fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 = - fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ; - assign fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 = - fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 = - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 = - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 = - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_mem0_controller_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_boot_rom_addr_lim ; - assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 = - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < - soc_map$m_uart0_addr_lim ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 = - soc_map$m_boot_rom_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d31 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d16 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d21 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 && - fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d28 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d339 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d329 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d330 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d332 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d333 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 && - fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d336 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d395 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d385 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d386 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d388 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d389 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 && - fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d392 ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 = - soc_map$m_mem0_controller_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d99 = - soc_map_m_mem0_controller_addr_base__3_ULE_fab_ETC___d89 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 || - soc_map_m_boot_rom_addr_base__0_ULE_fabric_xac_ETC___d92 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 || - soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 && - fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d26 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d335 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d391 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ; - assign soc_map_m_uart0_addr_base__5_ULE_fabric_xactor_ETC___d95 = - soc_map$m_uart0_addr_base <= - fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ; - assign x1_avValue_rresp__h18360 = - (fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h18986 = - (fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ; - assign x1_avValue_rresp__h19602 = - (fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ? - 2'b10 : - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ; - assign x__h11979 = fabric_v_rg_wd_beat_count_0 + 8'd1 ; - assign x__h12432 = fabric_v_rg_wd_beat_count_1 + 8'd1 ; - assign x__h18382 = fabric_v_rg_r_beat_count_0 + 8'd1 ; - assign x__h19008 = fabric_v_rg_r_beat_count_1 + 8'd1 ; - assign x__h19624 = fabric_v_rg_r_beat_count_2 + 8'd1 ; - assign x__h21928 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ; - assign x__h22329 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ; - always@(fabric_v_f_wd_tasks_0$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_0$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1; - endcase - end - always@(fabric_v_f_wd_tasks_1$D_OUT or - fabric_xactors_to_slaves_0_f_wr_data$FULL_N or - fabric_xactors_to_slaves_1_f_wr_data$FULL_N or - fabric_xactors_to_slaves_2_f_wr_data$FULL_N) - begin - case (fabric_v_f_wd_tasks_1$D_OUT[9:8]) - 2'd0: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - 2'd1: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_1_f_wr_data$FULL_N; - 2'd2: - CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = - fabric_xactors_to_slaves_2_f_wr_data$FULL_N; - 2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0; - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - if (fabric_v_rg_r_beat_count_0$EN) - fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_0$D_IN; - if (fabric_v_rg_r_beat_count_1$EN) - fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_1$D_IN; - if (fabric_v_rg_r_beat_count_2$EN) - fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_beat_count_2$D_IN; - if (fabric_v_rg_r_err_beat_count_0$EN) - fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_0$D_IN; - if (fabric_v_rg_r_err_beat_count_1$EN) - fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_r_err_beat_count_1$D_IN; - if (fabric_v_rg_wd_beat_count_0$EN) - fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_0$D_IN; - if (fabric_v_rg_wd_beat_count_1$EN) - fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY - fabric_v_rg_wd_beat_count_1$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - fabric_v_rg_r_beat_count_0 = 8'hAA; - fabric_v_rg_r_beat_count_1 = 8'hAA; - fabric_v_rg_r_beat_count_2 = 8'hAA; - fabric_v_rg_r_err_beat_count_0 = 8'hAA; - fabric_v_rg_r_err_beat_count_1 = 8'hAA; - fabric_v_rg_wd_beat_count_0 = 8'hAA; - fabric_v_rg_wd_beat_count_1 = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h8683 = $stime; - #0; - end - v__h8677 = v__h8683 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h8677, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9083 = $stime; - #0; - end - v__h9077 = v__h9083 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9077, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9483 = $stime; - #0; - end - v__h9477 = v__h9483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9477, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h9953 = $stime; - #0; - end - v__h9947 = v__h9953 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h9947, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10347 = $stime; - #0; - end - v__h10341 = v__h10347 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10341, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h10741 = $stime; - #0; - end - v__h10735 = v__h10741 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d", - v__h10735, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h11192 = $stime; - #0; - end - v__h11186 = v__h11192 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11186, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h11599 = $stime; - #0; - end - v__h11593 = v__h11599 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?", - v__h11593, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - begin - v__h12074 = $stime; - #0; - end - v__h12068 = v__h12074 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12068, - $signed(32'd0), - fabric_v_f_wd_tasks_0$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data && - fabric_v_rg_wd_beat_count_0_91_EQ_fabric_v_f_w_ETC___d193 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - begin - v__h12527 = $stime; - #0; - end - v__h12521 = v__h12527 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d", - v__h12521, - $signed(32'd1), - fabric_v_f_wd_tasks_1$D_OUT[9:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $display(" WLAST not set on final data beat (awlen = %0d)", - fabric_v_f_wd_tasks_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 && - fabric_v_rg_wd_beat_count_1_16_EQ_fabric_v_f_w_ETC___d218 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h12904 = $stime; - #0; - end - v__h12898 = v__h12904 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h12898, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13196 = $stime; - #0; - end - v__h13190 = v__h13196 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13190, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13488 = $stime; - #0; - end - v__h13482 = v__h13488 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13482, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h13791 = $stime; - #0; - end - v__h13785 = v__h13791 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h13785, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14057 = $stime; - #0; - end - v__h14051 = v__h14057 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14051, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14323 = $stime; - #0; - end - v__h14317 = v__h14323 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d", - v__h14317, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h14587 = $stime; - #0; - end - v__h14581 = v__h14587 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14581, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h14813 = $stime; - #0; - end - v__h14807 = v__h14813 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err", - v__h14807, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_wr_err_info_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h15267 = $stime; - #0; - end - v__h15261 = v__h15267 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15261, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h15648 = $stime; - #0; - end - v__h15642 = v__h15648 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h15642, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16029 = $stime; - #0; - end - v__h16023 = v__h16029 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16023, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16471 = $stime; - #0; - end - v__h16465 = v__h16471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16465, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h16828 = $stime; - #0; - end - v__h16822 = v__h16828 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h16822, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17185 = $stime; - #0; - end - v__h17179 = v__h17185 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d", - v__h17179, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - begin - v__h17536 = $stime; - #0; - end - v__h17530 = v__h17536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17530, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h17837 = $stime; - #0; - end - v__h17831 = v__h17837 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?", - v__h17831, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h18245 = $stime; - #0; - end - v__h18239 = v__h18245 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18239, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h18496 = $stime; - #0; - end - v__h18490 = v__h18496 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h18490, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h18871 = $stime; - #0; - end - v__h18865 = v__h18871 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h18865, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19112 = $stime; - #0; - end - v__h19106 = v__h19112 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19106, - $signed(32'd0), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h19487 = $stime; - #0; - end - v__h19481 = v__h19487 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h19481, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - begin - v__h19728 = $stime; - #0; - end - v__h19722 = v__h19728 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h19722, - $signed(32'd0), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - begin - v__h20090 = $stime; - #0; - end - v__h20084 = v__h20090 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20084, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_0$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_rd_ETC___d473 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20341 = $stime; - #0; - end - v__h20335 = v__h20341 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20335, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_0_71_EQ_fabric_v_f_ETC___d500); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - begin - v__h20671 = $stime; - #0; - end - v__h20665 = v__h20671 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h20665, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_1$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_rd_ETC___d513 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - begin - v__h20912 = $stime; - #0; - end - v__h20906 = v__h20912 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h20906, - $signed(32'd1), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_1_11_EQ_fabric_v_f_ETC___d539); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - begin - v__h21242 = $stime; - #0; - end - v__h21236 = v__h21242 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d", - v__h21236, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $display(" RLAST not set on final data beat (arlen = %0d)", - fabric_v_f_rd_mis_2$D_OUT[7:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_rd_ETC___d552 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - begin - v__h21483 = $stime; - #0; - end - v__h21477 = v__h21483 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d", - v__h21477, - $signed(32'd1), - $signed(32'd2)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", - IF_fabric_v_rg_r_beat_count_2_50_EQ_fabric_v_f_ETC___d578); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0 && - !fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - begin - v__h21996 = $stime; - #0; - end - v__h21990 = v__h21996 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h21990, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_0_22_EQ_fabric_v__ETC___d624) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - begin - v__h22397 = $stime; - #0; - end - v__h22391 = v__h22397 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err", - v__h22391, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(" r: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0 && - !fabric_v_rg_r_err_beat_count_1_40_EQ_fabric_v__ETC___d642) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - fabric_cfg_verbosity != 4'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h5698 = $stime; - #0; - end - v__h5692 = v__h5698 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: %m.rl_reset", v__h5692); - end - // synopsys translate_on -endmodule // mkFabric_AXI4 - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v deleted file mode 100644 index 5d5bbfb6..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkGPR_RegFile.v +++ /dev/null @@ -1,249 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// read_rs1 O 64 -// read_rs1_port2 O 64 -// read_rs2 O 64 -// CLK I 1 clock -// RST_N I 1 reset -// read_rs1_rs1 I 5 -// read_rs1_port2_rs1 I 5 -// read_rs2_rs2 I 5 -// write_rd_rd I 5 -// write_rd_rd_val I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_write_rd I 1 -// -// Combinational paths from inputs to outputs: -// read_rs1_rs1 -> read_rs1 -// read_rs1_port2_rs1 -> read_rs1_port2 -// read_rs2_rs2 -> read_rs2 -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkGPR_RegFile(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - read_rs1_rs1, - read_rs1, - - read_rs1_port2_rs1, - read_rs1_port2, - - read_rs2_rs2, - read_rs2, - - write_rd_rd, - write_rd_rd_val, - EN_write_rd); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // value method read_rs1 - input [4 : 0] read_rs1_rs1; - output [63 : 0] read_rs1; - - // value method read_rs1_port2 - input [4 : 0] read_rs1_port2_rs1; - output [63 : 0] read_rs1_port2; - - // value method read_rs2 - input [4 : 0] read_rs2_rs2; - output [63 : 0] read_rs2; - - // action method write_rd - input [4 : 0] write_rd_rd; - input [63 : 0] write_rd_rd_val; - input EN_write_rd; - - // signals for module outputs - wire [63 : 0] read_rs1, read_rs1_port2, read_rs2; - wire RDY_server_reset_request_put, RDY_server_reset_response_get; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule regfile - wire [63 : 0] regfile$D_IN, - regfile$D_OUT_1, - regfile$D_OUT_2, - regfile$D_OUT_3; - wire [4 : 0] regfile$ADDR_1, - regfile$ADDR_2, - regfile$ADDR_3, - regfile$ADDR_4, - regfile$ADDR_5, - regfile$ADDR_IN; - wire regfile$WE; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset_loop, - CAN_FIRE_RL_rl_reset_start, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_write_rd, - WILL_FIRE_RL_rl_reset_loop, - WILL_FIRE_RL_rl_reset_start, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_write_rd; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - rg_state == 2'd2 && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // value method read_rs1 - assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_3 ; - - // value method read_rs1_port2 - assign read_rs1_port2 = - (read_rs1_port2_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_2 ; - - // value method read_rs2 - assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 64'd0 : regfile$D_OUT_1 ; - - // action method write_rd - assign CAN_FIRE_write_rd = 1'd1 ; - assign WILL_FIRE_write_rd = EN_write_rd ; - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule regfile - RegFile #(.addr_width(32'd5), - .data_width(32'd64), - .lo(5'h0), - .hi(5'd31)) regfile(.CLK(CLK), - .ADDR_1(regfile$ADDR_1), - .ADDR_2(regfile$ADDR_2), - .ADDR_3(regfile$ADDR_3), - .ADDR_4(regfile$ADDR_4), - .ADDR_5(regfile$ADDR_5), - .ADDR_IN(regfile$ADDR_IN), - .D_IN(regfile$D_IN), - .WE(regfile$WE), - .D_OUT_1(regfile$D_OUT_1), - .D_OUT_2(regfile$D_OUT_2), - .D_OUT_3(regfile$D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // rule RL_rl_reset_start - assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ; - - // rule RL_rl_reset_loop - assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start) - case (1'b1) - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start || - WILL_FIRE_RL_rl_reset_loop ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = EN_server_reset_request_put ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule regfile - assign regfile$ADDR_1 = read_rs2_rs2 ; - assign regfile$ADDR_2 = read_rs1_port2_rs1 ; - assign regfile$ADDR_3 = read_rs1_rs1 ; - assign regfile$ADDR_4 = 5'h0 ; - assign regfile$ADDR_5 = 5'h0 ; - assign regfile$ADDR_IN = write_rd_rd ; - assign regfile$D_IN = write_rd_rd_val ; - assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkGPR_RegFile - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v deleted file mode 100644 index f4d13fdd..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_32.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 64 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 32 -// put_args_y_is_signed I 1 -// put_args_y I 32 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_32(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [31 : 0] put_args_x; - input put_args_y_is_signed; - input [31 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [63 : 0] result_value; - - // signals for module outputs - wire [63 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [63 : 0] m_rg_x; - wire [63 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [63 : 0] m_rg_xy; - wire [63 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [31 : 0] m_rg_y; - wire [31 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [63 : 0] xy___1__h654; - wire [31 : 0] _theResult___fst__h491, - _theResult___fst__h494, - _theResult___fst__h536, - _theResult___fst__h539, - _theResult___snd_fst__h531; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 32'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h654 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 32'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h491 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h539 : - _theResult___snd_fst__h531 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[31] != put_args_y[31] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d29 = - put_args_x_is_signed ? - put_args_x[31] : - put_args_y_is_signed && put_args_y[31] ; - assign _theResult___fst__h491 = - put_args_x_is_signed ? _theResult___fst__h494 : put_args_x ; - assign _theResult___fst__h494 = put_args_x[31] ? -put_args_x : put_args_x ; - assign _theResult___fst__h536 = - put_args_y_is_signed ? _theResult___fst__h539 : put_args_y ; - assign _theResult___fst__h539 = put_args_y[31] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h531 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h536 ; - assign xy___1__h654 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 64'hAAAAAAAAAAAAAAAA; - m_rg_xy = 64'hAAAAAAAAAAAAAAAA; - m_rg_y = 32'hAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_32 - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v deleted file mode 100644 index 0b513191..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkIntMul_64.v +++ /dev/null @@ -1,223 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// result_valid O 1 -// result_value O 128 -// CLK I 1 clock -// RST_N I 1 reset -// put_args_x_is_signed I 1 -// put_args_x I 64 -// put_args_y_is_signed I 1 -// put_args_y I 64 -// EN_put_args I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkIntMul_64(CLK, - RST_N, - - put_args_x_is_signed, - put_args_x, - put_args_y_is_signed, - put_args_y, - EN_put_args, - - result_valid, - - result_value); - input CLK; - input RST_N; - - // action method put_args - input put_args_x_is_signed; - input [63 : 0] put_args_x; - input put_args_y_is_signed; - input [63 : 0] put_args_y; - input EN_put_args; - - // value method result_valid - output result_valid; - - // value method result_value - output [127 : 0] result_value; - - // signals for module outputs - wire [127 : 0] result_value; - wire result_valid; - - // register m_rg_isNeg - reg m_rg_isNeg; - wire m_rg_isNeg$D_IN, m_rg_isNeg$EN; - - // register m_rg_signed - reg m_rg_signed; - wire m_rg_signed$D_IN, m_rg_signed$EN; - - // register m_rg_state - reg m_rg_state; - wire m_rg_state$D_IN, m_rg_state$EN; - - // register m_rg_x - reg [127 : 0] m_rg_x; - wire [127 : 0] m_rg_x$D_IN; - wire m_rg_x$EN; - - // register m_rg_xy - reg [127 : 0] m_rg_xy; - wire [127 : 0] m_rg_xy$D_IN; - wire m_rg_xy$EN; - - // register m_rg_y - reg [63 : 0] m_rg_y; - wire [63 : 0] m_rg_y$D_IN; - wire m_rg_y$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_m_compute, - CAN_FIRE_put_args, - WILL_FIRE_RL_m_compute, - WILL_FIRE_put_args; - - // inputs to muxes for submodule ports - wire [127 : 0] MUX_m_rg_x$write_1__VAL_1, - MUX_m_rg_x$write_1__VAL_2, - MUX_m_rg_xy$write_1__VAL_2; - wire [63 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2; - - // remaining internal signals - wire [127 : 0] xy___1__h648; - wire [63 : 0] _theResult___fst__h488, - _theResult___fst__h491, - _theResult___fst__h533, - _theResult___fst__h536, - _theResult___snd_fst__h528; - wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29; - - // action method put_args - assign CAN_FIRE_put_args = 1'd1 ; - assign WILL_FIRE_put_args = EN_put_args ; - - // value method result_valid - assign result_valid = m_rg_state && m_rg_y == 64'd0 ; - - // value method result_value - assign result_value = m_rg_isNeg ? xy___1__h648 : m_rg_xy ; - - // rule RL_m_compute - assign CAN_FIRE_RL_m_compute = m_rg_y != 64'd0 && m_rg_state ; - assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ; - - // inputs to muxes for submodule ports - assign MUX_m_rg_x$write_1__VAL_1 = { 64'd0, _theResult___fst__h488 } ; - assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[126:0], 1'd0 } ; - assign MUX_m_rg_xy$write_1__VAL_2 = m_rg_xy + m_rg_x ; - assign MUX_m_rg_y$write_1__VAL_1 = - (put_args_x_is_signed && put_args_y_is_signed) ? - _theResult___fst__h536 : - _theResult___snd_fst__h528 ; - assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[63:1] } ; - - // register m_rg_isNeg - assign m_rg_isNeg$D_IN = - (put_args_x_is_signed && put_args_y_is_signed) ? - put_args_x[63] != put_args_y[63] : - IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 ; - assign m_rg_isNeg$EN = EN_put_args ; - - // register m_rg_signed - assign m_rg_signed$D_IN = 1'b0 ; - assign m_rg_signed$EN = 1'b0 ; - - // register m_rg_state - assign m_rg_state$D_IN = 1'd1 ; - assign m_rg_state$EN = EN_put_args ; - - // register m_rg_x - assign m_rg_x$D_IN = - EN_put_args ? - MUX_m_rg_x$write_1__VAL_1 : - MUX_m_rg_x$write_1__VAL_2 ; - assign m_rg_x$EN = EN_put_args || WILL_FIRE_RL_m_compute ; - - // register m_rg_xy - assign m_rg_xy$D_IN = EN_put_args ? 128'd0 : MUX_m_rg_xy$write_1__VAL_2 ; - assign m_rg_xy$EN = WILL_FIRE_RL_m_compute && m_rg_y[0] || EN_put_args ; - - // register m_rg_y - assign m_rg_y$D_IN = - EN_put_args ? - MUX_m_rg_y$write_1__VAL_1 : - MUX_m_rg_y$write_1__VAL_2 ; - assign m_rg_y$EN = WILL_FIRE_RL_m_compute || EN_put_args ; - - // remaining internal signals - assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_63_ETC___d29 = - put_args_x_is_signed ? - put_args_x[63] : - put_args_y_is_signed && put_args_y[63] ; - assign _theResult___fst__h488 = - put_args_x_is_signed ? _theResult___fst__h491 : put_args_x ; - assign _theResult___fst__h491 = put_args_x[63] ? -put_args_x : put_args_x ; - assign _theResult___fst__h533 = - put_args_y_is_signed ? _theResult___fst__h536 : put_args_y ; - assign _theResult___fst__h536 = put_args_y[63] ? -put_args_y : put_args_y ; - assign _theResult___snd_fst__h528 = - put_args_x_is_signed ? put_args_y : _theResult___fst__h533 ; - assign xy___1__h648 = -m_rg_xy ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_rg_state$EN) - m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN; - end - if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN; - if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN; - if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN; - if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN; - if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_rg_isNeg = 1'h0; - m_rg_signed = 1'h0; - m_rg_state = 1'h0; - m_rg_x = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_xy = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - m_rg_y = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkIntMul_64 - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v deleted file mode 100644 index 60132569..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkMMU_Cache.v +++ /dev/null @@ -1,6051 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 -// valid O 1 -// addr O 64 reg -// word64 O 64 -// st_amo_val O 64 -// exc O 1 -// exc_code O 4 reg -// RDY_server_flush_request_put O 1 reg -// RDY_server_flush_response_get O 1 -// RDY_tlb_flush O 1 const -// mem_master_awvalid O 1 -// mem_master_awid O 4 reg -// mem_master_awaddr O 64 reg -// mem_master_awlen O 8 reg -// mem_master_awsize O 3 reg -// mem_master_awburst O 2 reg -// mem_master_awlock O 1 reg -// mem_master_awcache O 4 reg -// mem_master_awprot O 3 reg -// mem_master_awqos O 4 reg -// mem_master_awregion O 4 reg -// mem_master_wvalid O 1 -// mem_master_wid O 4 reg -// mem_master_wdata O 64 reg -// mem_master_wstrb O 8 reg -// mem_master_wlast O 1 reg -// mem_master_bready O 1 -// mem_master_arvalid O 1 -// mem_master_arid O 4 reg -// mem_master_araddr O 64 reg -// mem_master_arlen O 8 reg -// mem_master_arsize O 3 reg -// mem_master_arburst O 2 reg -// mem_master_arlock O 1 reg -// mem_master_arcache O 4 reg -// mem_master_arprot O 3 reg -// mem_master_arqos O 4 reg -// mem_master_arregion O 4 reg -// mem_master_rready O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_op I 2 -// req_f3 I 3 -// req_amo_funct7 I 7 reg -// req_addr I 64 -// req_st_value I 64 -// req_priv I 2 unused -// req_sstatus_SUM I 1 unused -// req_mstatus_MXR I 1 unused -// req_satp I 64 unused -// mem_master_awready I 1 -// mem_master_wready I 1 -// mem_master_bvalid I 1 -// mem_master_bid I 4 reg -// mem_master_bresp I 2 reg -// mem_master_arready I 1 -// mem_master_rvalid I 1 -// mem_master_rid I 4 reg -// mem_master_rdata I 64 reg -// mem_master_rresp I 2 reg -// mem_master_rlast I 1 reg -// EN_set_verbosity I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_req I 1 -// EN_server_flush_request_put I 1 -// EN_server_flush_response_get I 1 -// EN_tlb_flush I 1 unused -// -// Combinational paths from inputs to outputs: -// (mem_master_awready, mem_master_wready) -> valid -// (mem_master_awready, mem_master_wready) -> word64 -// (mem_master_awready, mem_master_wready) -> st_amo_val -// (mem_master_awready, mem_master_wready) -> mem_master_bready -// (mem_master_awready, mem_master_wready, EN_req) -> mem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMMU_Cache(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - req_op, - req_f3, - req_amo_funct7, - req_addr, - req_st_value, - req_priv, - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - EN_req, - - valid, - - addr, - - word64, - - st_amo_val, - - exc, - - exc_code, - - EN_server_flush_request_put, - RDY_server_flush_request_put, - - EN_server_flush_response_get, - RDY_server_flush_response_get, - - EN_tlb_flush, - RDY_tlb_flush, - - mem_master_awvalid, - - mem_master_awid, - - mem_master_awaddr, - - mem_master_awlen, - - mem_master_awsize, - - mem_master_awburst, - - mem_master_awlock, - - mem_master_awcache, - - mem_master_awprot, - - mem_master_awqos, - - mem_master_awregion, - - mem_master_awready, - - mem_master_wvalid, - - mem_master_wid, - - mem_master_wdata, - - mem_master_wstrb, - - mem_master_wlast, - - mem_master_wready, - - mem_master_bvalid, - mem_master_bid, - mem_master_bresp, - - mem_master_bready, - - mem_master_arvalid, - - mem_master_arid, - - mem_master_araddr, - - mem_master_arlen, - - mem_master_arsize, - - mem_master_arburst, - - mem_master_arlock, - - mem_master_arcache, - - mem_master_arprot, - - mem_master_arqos, - - mem_master_arregion, - - mem_master_arready, - - mem_master_rvalid, - mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast, - - mem_master_rready); - parameter [0 : 0] dmem_not_imem = 1'b0; - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method req - input [1 : 0] req_op; - input [2 : 0] req_f3; - input [6 : 0] req_amo_funct7; - input [63 : 0] req_addr; - input [63 : 0] req_st_value; - input [1 : 0] req_priv; - input req_sstatus_SUM; - input req_mstatus_MXR; - input [63 : 0] req_satp; - input EN_req; - - // value method valid - output valid; - - // value method addr - output [63 : 0] addr; - - // value method word64 - output [63 : 0] word64; - - // value method st_amo_val - output [63 : 0] st_amo_val; - - // value method exc - output exc; - - // value method exc_code - output [3 : 0] exc_code; - - // action method server_flush_request_put - input EN_server_flush_request_put; - output RDY_server_flush_request_put; - - // action method server_flush_response_get - input EN_server_flush_response_get; - output RDY_server_flush_response_get; - - // action method tlb_flush - input EN_tlb_flush; - output RDY_tlb_flush; - - // value method mem_master_m_awvalid - output mem_master_awvalid; - - // value method mem_master_m_awid - output [3 : 0] mem_master_awid; - - // value method mem_master_m_awaddr - output [63 : 0] mem_master_awaddr; - - // value method mem_master_m_awlen - output [7 : 0] mem_master_awlen; - - // value method mem_master_m_awsize - output [2 : 0] mem_master_awsize; - - // value method mem_master_m_awburst - output [1 : 0] mem_master_awburst; - - // value method mem_master_m_awlock - output mem_master_awlock; - - // value method mem_master_m_awcache - output [3 : 0] mem_master_awcache; - - // value method mem_master_m_awprot - output [2 : 0] mem_master_awprot; - - // value method mem_master_m_awqos - output [3 : 0] mem_master_awqos; - - // value method mem_master_m_awregion - output [3 : 0] mem_master_awregion; - - // value method mem_master_m_awuser - - // action method mem_master_m_awready - input mem_master_awready; - - // value method mem_master_m_wvalid - output mem_master_wvalid; - - // value method mem_master_m_wid - output [3 : 0] mem_master_wid; - - // value method mem_master_m_wdata - output [63 : 0] mem_master_wdata; - - // value method mem_master_m_wstrb - output [7 : 0] mem_master_wstrb; - - // value method mem_master_m_wlast - output mem_master_wlast; - - // value method mem_master_m_wuser - - // action method mem_master_m_wready - input mem_master_wready; - - // action method mem_master_m_bvalid - input mem_master_bvalid; - input [3 : 0] mem_master_bid; - input [1 : 0] mem_master_bresp; - - // value method mem_master_m_bready - output mem_master_bready; - - // value method mem_master_m_arvalid - output mem_master_arvalid; - - // value method mem_master_m_arid - output [3 : 0] mem_master_arid; - - // value method mem_master_m_araddr - output [63 : 0] mem_master_araddr; - - // value method mem_master_m_arlen - output [7 : 0] mem_master_arlen; - - // value method mem_master_m_arsize - output [2 : 0] mem_master_arsize; - - // value method mem_master_m_arburst - output [1 : 0] mem_master_arburst; - - // value method mem_master_m_arlock - output mem_master_arlock; - - // value method mem_master_m_arcache - output [3 : 0] mem_master_arcache; - - // value method mem_master_m_arprot - output [2 : 0] mem_master_arprot; - - // value method mem_master_m_arqos - output [3 : 0] mem_master_arqos; - - // value method mem_master_m_arregion - output [3 : 0] mem_master_arregion; - - // value method mem_master_m_aruser - - // action method mem_master_m_arready - input mem_master_arready; - - // action method mem_master_m_rvalid - input mem_master_rvalid; - input [3 : 0] mem_master_rid; - input [63 : 0] mem_master_rdata; - input [1 : 0] mem_master_rresp; - input mem_master_rlast; - - // value method mem_master_m_rready - output mem_master_rready; - - // signals for module outputs - reg [63 : 0] word64; - wire [63 : 0] addr, - mem_master_araddr, - mem_master_awaddr, - mem_master_wdata, - st_amo_val; - wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; - wire [3 : 0] exc_code, - mem_master_arcache, - mem_master_arid, - mem_master_arqos, - mem_master_arregion, - mem_master_awcache, - mem_master_awid, - mem_master_awqos, - mem_master_awregion, - mem_master_wid; - wire [2 : 0] mem_master_arprot, - mem_master_arsize, - mem_master_awprot, - mem_master_awsize; - wire [1 : 0] mem_master_arburst, mem_master_awburst; - wire RDY_server_flush_request_put, - RDY_server_flush_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_verbosity, - RDY_tlb_flush, - exc, - mem_master_arlock, - mem_master_arvalid, - mem_master_awlock, - mem_master_awvalid, - mem_master_bready, - mem_master_rready, - mem_master_wlast, - mem_master_wvalid, - valid; - - // inlined wires - reg [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1; - wire [10 : 0] crg_sb_to_load_delay$port0__write_1, - crg_sb_to_load_delay$port2__read; - wire [3 : 0] ctr_wr_rsps_pending_crg$port1__write_1, - ctr_wr_rsps_pending_crg$port2__read, - ctr_wr_rsps_pending_crg$port3__read; - wire crg_sb_to_load_delay$EN_port1__write, - ctr_wr_rsps_pending_crg$EN_port0__write, - ctr_wr_rsps_pending_crg$EN_port2__write, - dw_valid$whas, - master_xactor_crg_rd_addr_full$EN_port0__write, - master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port1__read, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port0__write, - master_xactor_crg_rd_data_full$EN_port1__write, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port1__read, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port0__write, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$EN_port2__write, - master_xactor_crg_wr_addr_full$port1__read, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port0__write, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$EN_port2__write, - master_xactor_crg_wr_data_full$port1__read, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read, - master_xactor_crg_wr_resp_full$EN_port0__write, - master_xactor_crg_wr_resp_full$EN_port2__write, - master_xactor_crg_wr_resp_full$port1__read, - master_xactor_crg_wr_resp_full$port2__read, - master_xactor_crg_wr_resp_full$port3__read; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_sb_to_load_delay - reg [10 : 0] crg_sb_to_load_delay; - wire [10 : 0] crg_sb_to_load_delay$D_IN; - wire crg_sb_to_load_delay$EN; - - // register ctr_wr_rsps_pending_crg - reg [3 : 0] ctr_wr_rsps_pending_crg; - wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN; - wire ctr_wr_rsps_pending_crg$EN; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - wire [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - reg [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [76 : 0] master_xactor_rg_wr_data; - reg [76 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; - - // register rg_addr - reg [63 : 0] rg_addr; - wire [63 : 0] rg_addr$D_IN; - wire rg_addr$EN; - - // register rg_amo_funct7 - reg [6 : 0] rg_amo_funct7; - wire [6 : 0] rg_amo_funct7$D_IN; - wire rg_amo_funct7$EN; - - // register rg_cset_in_cache - reg [5 : 0] rg_cset_in_cache; - wire [5 : 0] rg_cset_in_cache$D_IN; - wire rg_cset_in_cache$EN; - - // register rg_error_during_refill - reg rg_error_during_refill; - wire rg_error_during_refill$D_IN, rg_error_during_refill$EN; - - // register rg_exc_code - reg [3 : 0] rg_exc_code; - reg [3 : 0] rg_exc_code$D_IN; - wire rg_exc_code$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_ld_val - reg [63 : 0] rg_ld_val; - reg [63 : 0] rg_ld_val$D_IN; - wire rg_ld_val$EN; - - // register rg_lower_word32 - reg [31 : 0] rg_lower_word32; - wire [31 : 0] rg_lower_word32$D_IN; - wire rg_lower_word32$EN; - - // register rg_lower_word32_full - reg rg_lower_word32_full; - wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN; - - // register rg_lrsc_pa - reg [63 : 0] rg_lrsc_pa; - wire [63 : 0] rg_lrsc_pa$D_IN; - wire rg_lrsc_pa$EN; - - // register rg_lrsc_valid - reg rg_lrsc_valid; - wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN; - - // register rg_op - reg [1 : 0] rg_op; - wire [1 : 0] rg_op$D_IN; - wire rg_op$EN; - - // register rg_pa - reg [63 : 0] rg_pa; - wire [63 : 0] rg_pa$D_IN; - wire rg_pa$EN; - - // register rg_pte_pa - reg [63 : 0] rg_pte_pa; - wire [63 : 0] rg_pte_pa$D_IN; - wire rg_pte_pa$EN; - - // register rg_st_amo_val - reg [63 : 0] rg_st_amo_val; - wire [63 : 0] rg_st_amo_val$D_IN; - wire rg_st_amo_val$EN; - - // register rg_state - reg [4 : 0] rg_state; - reg [4 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_word64_set_in_cache - reg [8 : 0] rg_word64_set_in_cache; - wire [8 : 0] rg_word64_set_in_cache$D_IN; - wire rg_word64_set_in_cache$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$D_IN, - f_reset_reqs$D_OUT, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$D_IN, - f_reset_rsps$D_OUT, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule ram_state_and_ctag_cset - wire [52 : 0] ram_state_and_ctag_cset$DIA, - ram_state_and_ctag_cset$DIB, - ram_state_and_ctag_cset$DOB; - wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB; - wire ram_state_and_ctag_cset$ENA, - ram_state_and_ctag_cset$ENB, - ram_state_and_ctag_cset$WEA, - ram_state_and_ctag_cset$WEB; - - // ports of submodule ram_word64_set - reg [63 : 0] ram_word64_set$DIB; - reg [8 : 0] ram_word64_set$ADDRB; - wire [63 : 0] ram_word64_set$DIA, ram_word64_set$DOB; - wire [8 : 0] ram_word64_set$ADDRA; - wire ram_word64_set$ENA, - ram_word64_set$ENB, - ram_word64_set$WEA, - ram_word64_set$WEB; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - wire soc_map$m_is_mem_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_ST_AMO_response, - CAN_FIRE_RL_rl_cache_refill_rsps_loop, - CAN_FIRE_RL_rl_discard_write_rsp, - CAN_FIRE_RL_rl_drive_exception_rsp, - CAN_FIRE_RL_rl_io_AMO_SC_req, - CAN_FIRE_RL_rl_io_AMO_op_req, - CAN_FIRE_RL_rl_io_AMO_read_rsp, - CAN_FIRE_RL_rl_io_read_req, - CAN_FIRE_RL_rl_io_read_rsp, - CAN_FIRE_RL_rl_io_write_req, - CAN_FIRE_RL_rl_maintain_io_read_rsp, - CAN_FIRE_RL_rl_probe_and_immed_rsp, - CAN_FIRE_RL_rl_rereq, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_shift_sb_to_load_delay, - CAN_FIRE_RL_rl_start_cache_refill, - CAN_FIRE_RL_rl_start_reset, - CAN_FIRE_mem_master_m_arready, - CAN_FIRE_mem_master_m_awready, - CAN_FIRE_mem_master_m_bvalid, - CAN_FIRE_mem_master_m_rvalid, - CAN_FIRE_mem_master_m_wready, - CAN_FIRE_req, - CAN_FIRE_server_flush_request_put, - CAN_FIRE_server_flush_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_verbosity, - CAN_FIRE_tlb_flush, - WILL_FIRE_RL_rl_ST_AMO_response, - WILL_FIRE_RL_rl_cache_refill_rsps_loop, - WILL_FIRE_RL_rl_discard_write_rsp, - WILL_FIRE_RL_rl_drive_exception_rsp, - WILL_FIRE_RL_rl_io_AMO_SC_req, - WILL_FIRE_RL_rl_io_AMO_op_req, - WILL_FIRE_RL_rl_io_AMO_read_rsp, - WILL_FIRE_RL_rl_io_read_req, - WILL_FIRE_RL_rl_io_read_rsp, - WILL_FIRE_RL_rl_io_write_req, - WILL_FIRE_RL_rl_maintain_io_read_rsp, - WILL_FIRE_RL_rl_probe_and_immed_rsp, - WILL_FIRE_RL_rl_rereq, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_shift_sb_to_load_delay, - WILL_FIRE_RL_rl_start_cache_refill, - WILL_FIRE_RL_rl_start_reset, - WILL_FIRE_mem_master_m_arready, - WILL_FIRE_mem_master_m_awready, - WILL_FIRE_mem_master_m_bvalid, - WILL_FIRE_mem_master_m_rvalid, - WILL_FIRE_mem_master_m_wready, - WILL_FIRE_req, - WILL_FIRE_server_flush_request_put, - WILL_FIRE_server_flush_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_verbosity, - WILL_FIRE_tlb_flush; - - // inputs to muxes for submodule ports - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2, - MUX_master_xactor_rg_wr_addr$write_1__VAL_1, - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - wire [76 : 0] MUX_master_xactor_rg_wr_data$write_1__VAL_1, - MUX_master_xactor_rg_wr_data$write_1__VAL_2, - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3, - MUX_ram_word64_set$a_put_3__VAL_2, - MUX_rg_ld_val$write_1__VAL_2; - wire [52 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1; - wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2, - MUX_ram_word64_set$b_put_2__VAL_4; - wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1; - wire [4 : 0] MUX_rg_state$write_1__VAL_1, - MUX_rg_state$write_1__VAL_4, - MUX_rg_state$write_1__VAL_8, - MUX_rg_state$write_1__VAL_9; - wire [3 : 0] MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1, - MUX_rg_exc_code$write_1__VAL_1; - wire MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1, - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2, - MUX_dw_output_ld_val$wset_1__SEL_1, - MUX_dw_output_ld_val$wset_1__SEL_3, - MUX_dw_output_ld_val$wset_1__SEL_4, - MUX_master_xactor_rg_rd_addr$write_1__SEL_1, - MUX_ram_state_and_ctag_cset$b_put_2__SEL_1, - MUX_ram_word64_set$a_put_1__SEL_1, - MUX_ram_word64_set$b_put_1__SEL_2, - MUX_rg_error_during_refill$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_1, - MUX_rg_exc_code$write_1__SEL_2, - MUX_rg_exc_code$write_1__SEL_3, - MUX_rg_ld_val$write_1__SEL_2, - MUX_rg_lrsc_valid$write_1__SEL_2, - MUX_rg_state$write_1__SEL_13, - MUX_rg_state$write_1__SEL_2, - MUX_rg_state$write_1__SEL_3, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h3732; - reg [31 : 0] v__h3833; - reg [31 : 0] v__h25363; - reg [31 : 0] v__h26261; - reg [31 : 0] v__h3369; - reg [31 : 0] v__h4286; - reg [31 : 0] v__h12754; - reg [31 : 0] v__h17070; - reg [31 : 0] v__h16398; - reg [31 : 0] v__h20536; - reg [31 : 0] v__h21830; - reg [31 : 0] v__h22071; - reg [31 : 0] v__h24049; - reg [31 : 0] v__h25151; - reg [31 : 0] v__h25258; - reg [31 : 0] v__h25443; - reg [31 : 0] v__h25965; - reg [31 : 0] v__h26379; - reg [31 : 0] v__h26697; - reg [31 : 0] v__h26872; - reg [31 : 0] v__h29485; - reg [31 : 0] v__h29737; - reg [31 : 0] v__h26968; - reg [31 : 0] v__h20981; - reg [31 : 0] v__h23675; - reg [31 : 0] v__h30707; - reg [31 : 0] v__h30357; - reg [31 : 0] v__h30318; - reg [31 : 0] v__h26962; - reg [31 : 0] v__h3363; - reg [31 : 0] v__h3726; - reg [31 : 0] v__h3827; - reg [31 : 0] v__h4280; - reg [31 : 0] v__h12748; - reg [31 : 0] v__h16392; - reg [31 : 0] v__h17064; - reg [31 : 0] v__h20530; - reg [31 : 0] v__h20975; - reg [31 : 0] v__h21824; - reg [31 : 0] v__h22065; - reg [31 : 0] v__h23669; - reg [31 : 0] v__h24043; - reg [31 : 0] v__h25145; - reg [31 : 0] v__h25252; - reg [31 : 0] v__h25357; - reg [31 : 0] v__h25437; - reg [31 : 0] v__h25959; - reg [31 : 0] v__h26255; - reg [31 : 0] v__h26373; - reg [31 : 0] v__h26691; - reg [31 : 0] v__h26866; - reg [31 : 0] v__h29479; - reg [31 : 0] v__h29731; - reg [31 : 0] v__h30312; - reg [31 : 0] v__h30351; - reg [31 : 0] v__h30701; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32, - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51, - CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29, - CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33, - CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34, - CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425, - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360, - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434, - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302, - _theResult_____2__h17629, - _theResult_____2__h27290, - ld_val__h24158, - mem_req_wr_data_wdata__h16835, - mem_req_wr_data_wdata__h20332, - mem_req_wr_data_wdata__h25761, - mem_req_wr_data_wdata__h27265, - new_ld_val__h26998, - new_value__h15489, - new_value__h5462, - w1__h17621, - w1__h27278, - w1__h27282; - reg [7 : 0] mem_req_wr_data_wstrb__h20333, mem_req_wr_data_wstrb__h27266; - reg [2 : 0] value__h26583, value__h29609; - wire [63 : 0] IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800, - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257, - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366, - IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d466, - _theResult___snd_fst__h16843, - _theResult___snd_fst__h20340, - _theResult___snd_fst__h25769, - _theResult___snd_fst__h27273, - cline_fabric_addr__h21034, - new_st_val__h17351, - new_st_val__h17633, - new_st_val__h17724, - new_st_val__h18704, - new_st_val__h18708, - new_st_val__h18712, - new_st_val__h18716, - new_st_val__h18721, - new_st_val__h18727, - new_st_val__h18732, - new_st_val__h27294, - new_st_val__h27385, - new_st_val__h29245, - new_st_val__h29249, - new_st_val__h29253, - new_st_val__h29257, - new_st_val__h29262, - new_st_val__h29268, - new_st_val__h29273, - result__h11871, - result__h11899, - result__h11927, - result__h11955, - result__h11983, - result__h12011, - result__h12039, - result__h12084, - result__h12112, - result__h12140, - result__h12168, - result__h12196, - result__h12224, - result__h12252, - result__h12280, - result__h12325, - result__h12353, - result__h12381, - result__h12409, - result__h12450, - result__h12478, - result__h12506, - result__h12534, - result__h12575, - result__h12603, - result__h12642, - result__h12670, - result__h24218, - result__h24248, - result__h24275, - result__h24302, - result__h24329, - result__h24356, - result__h24383, - result__h24410, - result__h24454, - result__h24481, - result__h24508, - result__h24535, - result__h24562, - result__h24589, - result__h24616, - result__h24643, - result__h24687, - result__h24714, - result__h24741, - result__h24768, - result__h24808, - result__h24835, - result__h24862, - result__h24889, - result__h24929, - result__h24956, - result__h24994, - result__h25021, - result__h27473, - result__h28381, - result__h28409, - result__h28437, - result__h28465, - result__h28493, - result__h28521, - result__h28549, - result__h28594, - result__h28622, - result__h28650, - result__h28678, - result__h28706, - result__h28734, - result__h28762, - result__h28790, - result__h28835, - result__h28863, - result__h28891, - result__h28919, - result__h28960, - result__h28988, - result__h29016, - result__h29044, - result__h29085, - result__h29113, - result__h29152, - result__h29180, - result__h5515, - st_val__h27010, - w1___1__h17692, - w1___1__h27353, - w2___1__h27354, - w2__h27284, - word64__h5281, - x__h13141, - y__h5551; - wire [31 : 0] ld_val4158_BITS_31_TO_0__q37, - ld_val4158_BITS_63_TO_32__q44, - master_xactor_rg_rd_data_BITS_34_TO_3__q3, - master_xactor_rg_rd_data_BITS_66_TO_35__q10, - new_value462_BITS_31_TO_0__q30, - rg_st_amo_val_BITS_31_TO_0__q31, - w17278_BITS_31_TO_0__q50, - word64281_BITS_31_TO_0__q17, - word64281_BITS_63_TO_32__q24; - wire [15 : 0] ld_val4158_BITS_15_TO_0__q36, - ld_val4158_BITS_31_TO_16__q40, - ld_val4158_BITS_47_TO_32__q43, - ld_val4158_BITS_63_TO_48__q47, - master_xactor_rg_rd_data_BITS_18_TO_3__q2, - master_xactor_rg_rd_data_BITS_34_TO_19__q6, - master_xactor_rg_rd_data_BITS_50_TO_35__q9, - master_xactor_rg_rd_data_BITS_66_TO_51__q13, - word64281_BITS_15_TO_0__q16, - word64281_BITS_31_TO_16__q20, - word64281_BITS_47_TO_32__q23, - word64281_BITS_63_TO_48__q27; - wire [7 : 0] ld_val4158_BITS_15_TO_8__q38, - ld_val4158_BITS_23_TO_16__q39, - ld_val4158_BITS_31_TO_24__q41, - ld_val4158_BITS_39_TO_32__q42, - ld_val4158_BITS_47_TO_40__q45, - ld_val4158_BITS_55_TO_48__q46, - ld_val4158_BITS_63_TO_56__q48, - ld_val4158_BITS_7_TO_0__q35, - master_xactor_rg_rd_data_BITS_10_TO_3__q1, - master_xactor_rg_rd_data_BITS_18_TO_11__q4, - master_xactor_rg_rd_data_BITS_26_TO_19__q5, - master_xactor_rg_rd_data_BITS_34_TO_27__q7, - master_xactor_rg_rd_data_BITS_42_TO_35__q8, - master_xactor_rg_rd_data_BITS_50_TO_43__q11, - master_xactor_rg_rd_data_BITS_58_TO_51__q12, - master_xactor_rg_rd_data_BITS_66_TO_59__q14, - strobe64__h20266, - strobe64__h20268, - strobe64__h20270, - strobe64__h27199, - strobe64__h27201, - strobe64__h27203, - word64281_BITS_15_TO_8__q18, - word64281_BITS_23_TO_16__q19, - word64281_BITS_31_TO_24__q21, - word64281_BITS_39_TO_32__q22, - word64281_BITS_47_TO_40__q25, - word64281_BITS_55_TO_48__q26, - word64281_BITS_63_TO_56__q28, - word64281_BITS_7_TO_0__q15; - wire [5 : 0] shift_bits__h20133, shift_bits__h27066; - wire [4 : 0] IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d110, - IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d109; - wire [3 : 0] access_exc_code__h2925, b__h20935; - wire IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d78, - NOT_cfg_verbosity_read__0_ULE_1_1___d12, - NOT_cfg_verbosity_read__0_ULE_2_54___d555, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d309, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d443, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d479, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d491, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d519, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d532, - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d534, - NOT_ram_state_and_ctag_cset_b_read__9_BIT_52_0_ETC___d119, - NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911, - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d105, - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446, - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494, - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502, - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d128, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d440, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d517, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d520, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d524, - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d530, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d304, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d438, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d492, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d496, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d500, - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d505, - dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d80, - lrsc_result__h13131, - master_xactor_crg_rd_data_full_port1__read__51_ETC___d723, - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74, - ram_state_and_ctag_cset_b_read__9_BIT_52_0_AND_ETC___d120, - req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920, - rg_addr_0_EQ_rg_lrsc_pa_8___d117, - rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d292, - rg_lrsc_pa_8_EQ_rg_addr_0___d59, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d100, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275, - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d288, - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d129, - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d307, - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d441, - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d444, - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513, - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d68, - rg_state_EQ_13_90_AND_rg_op_4_EQ_0_5_OR_rg_op__ETC___d592, - rg_state_EQ_3_1_AND_NOT_rg_op_4_EQ_0_5_2_AND_N_ETC___d90; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = - !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method addr - assign addr = rg_addr ; - - // value method word64 - always@(MUX_dw_output_ld_val$wset_1__SEL_1 or - ld_val__h24158 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h26998 or - MUX_dw_output_ld_val$wset_1__SEL_3 or - MUX_dw_output_ld_val$wset_1__VAL_3 or - MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val) - begin - case (1'b1) // synopsys parallel_case - MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h24158; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - word64 = new_ld_val__h26998; - MUX_dw_output_ld_val$wset_1__SEL_3: - word64 = MUX_dw_output_ld_val$wset_1__VAL_3; - MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val; - default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // value method st_amo_val - assign st_amo_val = - MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ; - - // value method exc - assign exc = rg_state == 5'd4 ; - - // value method exc_code - assign exc_code = rg_exc_code ; - - // action method server_flush_request_put - assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; - - // action method server_flush_response_get - assign RDY_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_flush_response_get = - f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; - - // action method tlb_flush - assign RDY_tlb_flush = 1'd1 ; - assign CAN_FIRE_tlb_flush = 1'd1 ; - assign WILL_FIRE_tlb_flush = EN_tlb_flush ; - - // value method mem_master_m_awvalid - assign mem_master_awvalid = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - - // value method mem_master_m_awid - assign mem_master_awid = master_xactor_rg_wr_addr[96:93] ; - - // value method mem_master_m_awaddr - assign mem_master_awaddr = master_xactor_rg_wr_addr[92:29] ; - - // value method mem_master_m_awlen - assign mem_master_awlen = master_xactor_rg_wr_addr[28:21] ; - - // value method mem_master_m_awsize - assign mem_master_awsize = master_xactor_rg_wr_addr[20:18] ; - - // value method mem_master_m_awburst - assign mem_master_awburst = master_xactor_rg_wr_addr[17:16] ; - - // value method mem_master_m_awlock - assign mem_master_awlock = master_xactor_rg_wr_addr[15] ; - - // value method mem_master_m_awcache - assign mem_master_awcache = master_xactor_rg_wr_addr[14:11] ; - - // value method mem_master_m_awprot - assign mem_master_awprot = master_xactor_rg_wr_addr[10:8] ; - - // value method mem_master_m_awqos - assign mem_master_awqos = master_xactor_rg_wr_addr[7:4] ; - - // value method mem_master_m_awregion - assign mem_master_awregion = master_xactor_rg_wr_addr[3:0] ; - - // action method mem_master_m_awready - assign CAN_FIRE_mem_master_m_awready = 1'd1 ; - assign WILL_FIRE_mem_master_m_awready = 1'd1 ; - - // value method mem_master_m_wvalid - assign mem_master_wvalid = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - - // value method mem_master_m_wid - assign mem_master_wid = master_xactor_rg_wr_data[76:73] ; - - // value method mem_master_m_wdata - assign mem_master_wdata = master_xactor_rg_wr_data[72:9] ; - - // value method mem_master_m_wstrb - assign mem_master_wstrb = master_xactor_rg_wr_data[8:1] ; - - // value method mem_master_m_wlast - assign mem_master_wlast = master_xactor_rg_wr_data[0] ; - - // action method mem_master_m_wready - assign CAN_FIRE_mem_master_m_wready = 1'd1 ; - assign WILL_FIRE_mem_master_m_wready = 1'd1 ; - - // action method mem_master_m_bvalid - assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ; - - // value method mem_master_m_bready - assign mem_master_bready = !master_xactor_crg_wr_resp_full$port2__read ; - - // value method mem_master_m_arvalid - assign mem_master_arvalid = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - - // value method mem_master_m_arid - assign mem_master_arid = master_xactor_rg_rd_addr[96:93] ; - - // value method mem_master_m_araddr - assign mem_master_araddr = master_xactor_rg_rd_addr[92:29] ; - - // value method mem_master_m_arlen - assign mem_master_arlen = master_xactor_rg_rd_addr[28:21] ; - - // value method mem_master_m_arsize - assign mem_master_arsize = master_xactor_rg_rd_addr[20:18] ; - - // value method mem_master_m_arburst - assign mem_master_arburst = master_xactor_rg_rd_addr[17:16] ; - - // value method mem_master_m_arlock - assign mem_master_arlock = master_xactor_rg_rd_addr[15] ; - - // value method mem_master_m_arcache - assign mem_master_arcache = master_xactor_rg_rd_addr[14:11] ; - - // value method mem_master_m_arprot - assign mem_master_arprot = master_xactor_rg_rd_addr[10:8] ; - - // value method mem_master_m_arqos - assign mem_master_arqos = master_xactor_rg_rd_addr[7:4] ; - - // value method mem_master_m_arregion - assign mem_master_arregion = master_xactor_rg_rd_addr[3:0] ; - - // action method mem_master_m_arready - assign CAN_FIRE_mem_master_m_arready = 1'd1 ; - assign WILL_FIRE_mem_master_m_arready = 1'd1 ; - - // action method mem_master_m_rvalid - assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ; - - // value method mem_master_m_rready - assign mem_master_rready = !master_xactor_crg_rd_data_full$port2__read ; - - // submodule f_reset_reqs - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_reqs$D_IN), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .D_OUT(f_reset_reqs$D_OUT), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reset_rsps$D_IN), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .D_OUT(f_reset_rsps$D_OUT), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule ram_state_and_ctag_cset - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd6), - .DATA_WIDTH(32'd53), - .MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_state_and_ctag_cset$ADDRA), - .ADDRB(ram_state_and_ctag_cset$ADDRB), - .DIA(ram_state_and_ctag_cset$DIA), - .DIB(ram_state_and_ctag_cset$DIB), - .WEA(ram_state_and_ctag_cset$WEA), - .WEB(ram_state_and_ctag_cset$WEB), - .ENA(ram_state_and_ctag_cset$ENA), - .ENB(ram_state_and_ctag_cset$ENB), - .DOA(), - .DOB(ram_state_and_ctag_cset$DOB)); - - // submodule ram_word64_set - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd9), - .DATA_WIDTH(32'd64), - .MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(ram_word64_set$ADDRA), - .ADDRB(ram_word64_set$ADDRB), - .DIA(ram_word64_set$DIA), - .DIB(ram_word64_set$DIB), - .WEA(ram_word64_set$WEA), - .WEB(ram_word64_set$WEB), - .ENA(ram_word64_set$ENA), - .ENB(ram_word64_set$ENB), - .DOA(), - .DOB(ram_word64_set$DOB)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(soc_map$m_is_mem_addr), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - (rg_cset_in_cache != 6'd63 || - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) && - rg_state == 5'd1 ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // rule RL_rl_shift_sb_to_load_delay - assign CAN_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - assign WILL_FIRE_RL_rl_shift_sb_to_load_delay = 1'd1 ; - - // rule RL_rl_rereq - assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ; - assign WILL_FIRE_RL_rl_rereq = - CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ; - - // rule RL_rl_ST_AMO_response - assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ; - assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ; - - // rule RL_rl_maintain_io_read_rsp - assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ; - assign WILL_FIRE_RL_rl_maintain_io_read_rsp = - CAN_FIRE_RL_rl_maintain_io_read_rsp ; - - // rule RL_rl_io_AMO_SC_req - assign CAN_FIRE_RL_rl_io_AMO_SC_req = - rg_state == 5'd13 && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_SC_req = - CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_drive_exception_rsp - assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ; - assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ; - - // rule RL_rl_start_reset - assign CAN_FIRE_RL_rl_start_reset = - f_reset_reqs$EMPTY_N && rg_state != 5'd1 ; - assign WILL_FIRE_RL_rl_start_reset = CAN_FIRE_RL_rl_start_reset ; - - // rule RL_rl_probe_and_immed_rsp - assign CAN_FIRE_RL_rl_probe_and_immed_rsp = - dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d80 && - rg_state_EQ_3_1_AND_NOT_rg_op_4_EQ_0_5_2_AND_N_ETC___d90 ; - assign WILL_FIRE_RL_rl_probe_and_immed_rsp = - CAN_FIRE_RL_rl_probe_and_immed_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_cache_refill_rsps_loop - assign CAN_FIRE_RL_rl_cache_refill_rsps_loop = - master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd10 ; - assign WILL_FIRE_RL_rl_cache_refill_rsps_loop = - CAN_FIRE_RL_rl_cache_refill_rsps_loop && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - - // rule RL_rl_io_read_rsp - assign CAN_FIRE_RL_rl_io_read_rsp = - master_xactor_crg_rd_data_full$port1__read && rg_state == 5'd14 ; - assign WILL_FIRE_RL_rl_io_read_rsp = - CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_write_req - assign CAN_FIRE_RL_rl_io_write_req = - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read && - rg_state == 5'd13 && - rg_op == 2'd1 ; - assign WILL_FIRE_RL_rl_io_write_req = - CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_op_req - assign CAN_FIRE_RL_rl_io_AMO_op_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 5'd13 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] != 5'b00010 && - rg_amo_funct7[6:2] != 5'b00011 ; - assign WILL_FIRE_RL_rl_io_AMO_op_req = - CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_io_AMO_read_rsp - assign CAN_FIRE_RL_rl_io_AMO_read_rsp = - master_xactor_crg_rd_data_full_port1__read__51_ETC___d723 && - rg_state == 5'd16 ; - assign WILL_FIRE_RL_rl_io_AMO_read_rsp = - CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ; - - // rule RL_rl_start_cache_refill - assign CAN_FIRE_RL_rl_start_cache_refill = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state == 5'd9 && - b__h20935 == 4'd0 ; - assign WILL_FIRE_RL_rl_start_cache_refill = MUX_rg_state$write_1__SEL_3 ; - - // rule RL_rl_io_read_req - assign CAN_FIRE_RL_rl_io_read_req = - !master_xactor_crg_rd_addr_full$port2__read && - rg_state_EQ_13_90_AND_rg_op_4_EQ_0_5_OR_rg_op__ETC___d592 ; - assign WILL_FIRE_RL_rl_io_read_req = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_discard_write_rsp - assign CAN_FIRE_RL_rl_discard_write_rsp = - b__h20935 != 4'd0 && master_xactor_crg_wr_resp_full$port1__read ; - assign WILL_FIRE_RL_rl_discard_write_rsp = - CAN_FIRE_RL_rl_discard_write_rsp && - !WILL_FIRE_RL_rl_start_reset ; - - // inputs to muxes for submodule ports - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 ; - assign MUX_dw_output_ld_val$wset_1__SEL_1 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_dw_output_ld_val$wset_1__SEL_3 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136 ; - assign MUX_dw_output_ld_val$wset_1__SEL_4 = - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign MUX_master_xactor_rg_rd_addr$write_1__SEL_1 = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ; - assign MUX_ram_state_and_ctag_cset$b_put_2__SEL_1 = - EN_req && - req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 ; - assign MUX_ram_word64_set$a_put_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 ; - assign MUX_ram_word64_set$b_put_1__SEL_2 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 ; - assign MUX_rg_error_during_refill$write_1__SEL_1 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_1 = - EN_req && - NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 ; - assign MUX_rg_exc_code$write_1__SEL_2 = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_exc_code$write_1__SEL_3 = - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 ; - assign MUX_rg_ld_val$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298 ; - assign MUX_rg_lrsc_valid$write_1__SEL_2 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ; - assign MUX_rg_state$write_1__SEL_3 = - CAN_FIRE_RL_rl_start_cache_refill && - !WILL_FIRE_RL_rl_start_reset && - !EN_req ; - assign MUX_rg_state$write_1__SEL_8 = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 ; - assign MUX_rg_state$write_1__SEL_9 = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (dmem_not_imem && !soc_map$m_is_mem_addr || - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d100 || - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d105) ; - assign MUX_rg_state$write_1__SEL_13 = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 = - ctr_wr_rsps_pending_crg + 4'd1 ; - assign MUX_dw_output_ld_val$wset_1__VAL_3 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - new_value__h5462 : - new_value__h15489 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, rg_pa, 8'd0, value__h26583, 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, cline_fabric_addr__h21034, 29'd15532032 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_1 = - { 4'd0, rg_pa, 8'd0, value__h29609, 18'd65536 } ; - assign MUX_master_xactor_rg_wr_addr$write_1__VAL_2 = - { 4'd0, rg_addr, 8'd0, value__h29609, 18'd65536 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_1 = - { 4'd0, - mem_req_wr_data_wdata__h27265, - mem_req_wr_data_wstrb__h27266, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_2 = - { 4'd0, - IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d466, - mem_req_wr_data_wstrb__h20333, - 1'd1 } ; - assign MUX_master_xactor_rg_wr_data$write_1__VAL_3 = - { 4'd0, - mem_req_wr_data_wdata__h25761, - mem_req_wr_data_wstrb__h27266, - 1'd1 } ; - assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 = { 1'd1, rg_pa[63:12] } ; - assign MUX_ram_word64_set$a_put_3__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 : - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 ; - assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ; - assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ; - assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ; - assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ; - assign MUX_rg_ld_val$write_1__VAL_2 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - x__h13141 : - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 ; - assign MUX_rg_state$write_1__VAL_1 = - NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 ? - 5'd4 : - 5'd3 ; - assign MUX_rg_state$write_1__VAL_4 = - (master_xactor_rg_rd_data[2:1] == 2'b0) ? 5'd15 : 5'd4 ; - assign MUX_rg_state$write_1__VAL_8 = - (master_xactor_rg_rd_data[2:1] != 2'b0 || - rg_error_during_refill) ? - 5'd4 : - 5'd11 ; - assign MUX_rg_state$write_1__VAL_9 = - (dmem_not_imem && !soc_map$m_is_mem_addr) ? - 5'd13 : - IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d110 ; - - // inlined wires - assign dw_valid$whas = - (WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_io_read_rsp) && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136 || - WILL_FIRE_RL_rl_drive_exception_rsp || - WILL_FIRE_RL_rl_maintain_io_read_rsp || - WILL_FIRE_RL_rl_ST_AMO_response ; - assign master_xactor_crg_wr_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_addr_full$port1__read = - !master_xactor_crg_wr_addr_full$EN_port0__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full$port1__read && - mem_master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full$port1__read ; - assign master_xactor_crg_wr_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 || - WILL_FIRE_RL_rl_io_write_req ; - assign master_xactor_crg_wr_addr_full$port3__read = - master_xactor_crg_wr_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_data_full$port1__read = - !master_xactor_crg_wr_data_full$EN_port0__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full$port1__read && mem_master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full$port1__read ; - assign master_xactor_crg_wr_data_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 || - WILL_FIRE_RL_rl_io_write_req ; - assign master_xactor_crg_wr_data_full$port3__read = - master_xactor_crg_wr_data_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_wr_resp_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_wr_resp_full$port1__read = - !master_xactor_crg_wr_resp_full$EN_port0__write && - master_xactor_crg_wr_resp_full ; - assign master_xactor_crg_wr_resp_full$port2__read = - !WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_crg_wr_resp_full$port1__read ; - assign master_xactor_crg_wr_resp_full$EN_port2__write = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_wr_resp_full$port3__read = - master_xactor_crg_wr_resp_full$EN_port2__write || - master_xactor_crg_wr_resp_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_addr_full$port1__read = - !master_xactor_crg_rd_addr_full$EN_port0__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full$port1__read && - mem_master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full$port1__read ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write || - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$EN_port0__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign master_xactor_crg_rd_data_full$port1__read = - !master_xactor_crg_rd_data_full$EN_port0__write && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port1__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp || WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_cache_refill_rsps_loop ; - assign master_xactor_crg_rd_data_full$port2__read = - !master_xactor_crg_rd_data_full$EN_port1__write && - master_xactor_crg_rd_data_full$port1__read ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - mem_master_rvalid && - !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - assign ctr_wr_rsps_pending_crg$EN_port0__write = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 || - WILL_FIRE_RL_rl_io_write_req ; - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - WILL_FIRE_RL_rl_io_write_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - WILL_FIRE_RL_rl_io_write_req: - ctr_wr_rsps_pending_crg$port0__write_1 = - MUX_ctr_wr_rsps_pending_crg$port0__write_1__VAL_1; - default: ctr_wr_rsps_pending_crg$port0__write_1 = - 4'b1010 /* unspecified value */ ; - endcase - end - assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h20935 - 4'd1 ; - assign ctr_wr_rsps_pending_crg$port2__read = - WILL_FIRE_RL_rl_discard_write_rsp ? - ctr_wr_rsps_pending_crg$port1__write_1 : - b__h20935 ; - assign ctr_wr_rsps_pending_crg$EN_port2__write = - WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ; - assign ctr_wr_rsps_pending_crg$port3__read = - ctr_wr_rsps_pending_crg$EN_port2__write ? - 4'd0 : - ctr_wr_rsps_pending_crg$port2__read ; - assign crg_sb_to_load_delay$port0__write_1 = - { 1'd0, crg_sb_to_load_delay[10:1] } ; - assign crg_sb_to_load_delay$EN_port1__write = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d443 ; - assign crg_sb_to_load_delay$port2__read = - crg_sb_to_load_delay$EN_port1__write ? - 11'd2047 : - crg_sb_to_load_delay$port0__write_1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register crg_sb_to_load_delay - assign crg_sb_to_load_delay$D_IN = crg_sb_to_load_delay$port2__read ; - assign crg_sb_to_load_delay$EN = 1'b1 ; - - // register ctr_wr_rsps_pending_crg - assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ; - assign ctr_wr_rsps_pending_crg$EN = 1'b1 ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = - master_xactor_crg_wr_resp_full$port3__read ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - assign master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_rg_rd_addr$write_1__SEL_1 ? - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 : - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ; - assign master_xactor_rg_rd_addr$EN = - WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { mem_master_rid, - mem_master_rdata, - mem_master_rresp, - mem_master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_addr$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_addr$D_IN = - MUX_master_xactor_rg_wr_addr$write_1__VAL_1; - default: master_xactor_rg_wr_addr$D_IN = - 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_addr$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_data - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - MUX_master_xactor_rg_wr_data$write_1__VAL_1 or - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2 or - MUX_master_xactor_rg_wr_data$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_write_req or - MUX_master_xactor_rg_wr_data$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_1; - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_2: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_2; - WILL_FIRE_RL_rl_io_write_req: - master_xactor_rg_wr_data$D_IN = - MUX_master_xactor_rg_wr_data$write_1__VAL_3; - default: master_xactor_rg_wr_data$D_IN = - 77'h0AAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign master_xactor_rg_wr_data$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 || - WILL_FIRE_RL_rl_io_write_req ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = - { mem_master_bid, mem_master_bresp } ; - assign master_xactor_rg_wr_resp$EN = - mem_master_bvalid && - !master_xactor_crg_wr_resp_full$port2__read ; - - // register rg_addr - assign rg_addr$D_IN = req_addr ; - assign rg_addr$EN = EN_req ; - - // register rg_amo_funct7 - assign rg_amo_funct7$D_IN = req_amo_funct7 ; - assign rg_amo_funct7$EN = EN_req ; - - // register rg_cset_in_cache - assign rg_cset_in_cache$D_IN = - WILL_FIRE_RL_rl_reset ? - MUX_rg_cset_in_cache$write_1__VAL_1 : - 6'd0 ; - assign rg_cset_in_cache$EN = - WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ; - - // register rg_error_during_refill - assign rg_error_during_refill$D_IN = - MUX_rg_error_during_refill$write_1__SEL_1 ; - assign rg_error_during_refill$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // register rg_exc_code - always@(MUX_rg_exc_code$write_1__SEL_1 or - MUX_rg_exc_code$write_1__VAL_1 or - MUX_rg_exc_code$write_1__SEL_2 or - MUX_rg_exc_code$write_1__SEL_3 or - MUX_rg_error_during_refill$write_1__SEL_1 or access_exc_code__h2925) - case (1'b1) - MUX_rg_exc_code$write_1__SEL_1: - rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1; - MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7; - MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5; - MUX_rg_error_during_refill$write_1__SEL_1: - rg_exc_code$D_IN = access_exc_code__h2925; - default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; - endcase - assign rg_exc_code$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 || - EN_req && - NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_ld_val - always@(MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1 or - new_ld_val__h26998 or - MUX_rg_ld_val$write_1__SEL_2 or - MUX_rg_ld_val$write_1__VAL_2 or - WILL_FIRE_RL_rl_io_read_rsp or - ld_val__h24158 or WILL_FIRE_RL_rl_io_AMO_SC_req) - begin - case (1'b1) // synopsys parallel_case - MUX_ctr_wr_rsps_pending_crg$port0__write_1__SEL_1: - rg_ld_val$D_IN = new_ld_val__h26998; - MUX_rg_ld_val$write_1__SEL_2: - rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2; - WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h24158; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1; - default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign rg_ld_val$EN = - WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298 || - WILL_FIRE_RL_rl_io_read_rsp || - WILL_FIRE_RL_rl_io_AMO_SC_req ; - - // register rg_lower_word32 - assign rg_lower_word32$D_IN = 32'h0 ; - assign rg_lower_word32$EN = 1'b0 ; - - // register rg_lower_word32_full - assign rg_lower_word32_full$D_IN = 1'd0 ; - assign rg_lower_word32_full$EN = - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_lrsc_pa - assign rg_lrsc_pa$D_IN = rg_addr ; - assign rg_lrsc_pa$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ; - - // register rg_lrsc_valid - assign rg_lrsc_valid$D_IN = - MUX_rg_lrsc_valid$write_1__SEL_2 && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133 ; - assign rg_lrsc_valid$EN = - WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131 || - WILL_FIRE_RL_rl_start_reset ; - - // register rg_op - assign rg_op$D_IN = req_op ; - assign rg_op$EN = EN_req ; - - // register rg_pa - assign rg_pa$D_IN = EN_req ? req_addr : rg_addr ; - assign rg_pa$EN = EN_req || WILL_FIRE_RL_rl_probe_and_immed_rsp ; - - // register rg_pte_pa - assign rg_pte_pa$D_IN = 64'h0 ; - assign rg_pte_pa$EN = 1'b0 ; - - // register rg_st_amo_val - assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h17351 ; - assign rg_st_amo_val$EN = - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d534 || - EN_req ; - - // register rg_state - always@(EN_req or - MUX_rg_state$write_1__VAL_1 or - WILL_FIRE_RL_rl_io_read_req or - WILL_FIRE_RL_rl_start_cache_refill or - WILL_FIRE_RL_rl_io_AMO_read_rsp or - MUX_rg_state$write_1__VAL_4 or - WILL_FIRE_RL_rl_io_AMO_op_req or - WILL_FIRE_RL_rl_io_write_req or - WILL_FIRE_RL_rl_io_read_rsp or - MUX_rg_state$write_1__SEL_8 or - MUX_rg_state$write_1__VAL_8 or - MUX_rg_state$write_1__SEL_9 or - MUX_rg_state$write_1__VAL_9 or - WILL_FIRE_RL_rl_start_reset or - WILL_FIRE_RL_rl_io_AMO_SC_req or - WILL_FIRE_RL_rl_rereq or MUX_rg_state$write_1__SEL_13) - case (1'b1) - EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_1; - WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14; - WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10; - WILL_FIRE_RL_rl_io_AMO_read_rsp: - rg_state$D_IN = MUX_rg_state$write_1__VAL_4; - WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16; - WILL_FIRE_RL_rl_io_write_req: rg_state$D_IN = 5'd12; - WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_4; - MUX_rg_state$write_1__SEL_8: rg_state$D_IN = MUX_rg_state$write_1__VAL_8; - MUX_rg_state$write_1__SEL_9: rg_state$D_IN = MUX_rg_state$write_1__VAL_9; - WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1; - WILL_FIRE_RL_rl_io_AMO_SC_req: rg_state$D_IN = 5'd12; - WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3; - MUX_rg_state$write_1__SEL_13: rg_state$D_IN = 5'd2; - default: rg_state$D_IN = 5'b01010 /* unspecified value */ ; - endcase - assign rg_state$EN = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 || - MUX_rg_state$write_1__SEL_9 || - WILL_FIRE_RL_rl_io_AMO_read_rsp || - WILL_FIRE_RL_rl_io_read_rsp || - EN_req || - WILL_FIRE_RL_rl_start_reset || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill || - WILL_FIRE_RL_rl_io_AMO_SC_req || - WILL_FIRE_RL_rl_io_write_req || - WILL_FIRE_RL_rl_io_read_req || - WILL_FIRE_RL_rl_io_AMO_op_req ; - - // register rg_word64_set_in_cache - assign rg_word64_set_in_cache$D_IN = - MUX_ram_word64_set$b_put_1__SEL_2 ? - MUX_ram_word64_set$b_put_2__VAL_2 : - MUX_ram_word64_set$b_put_2__VAL_4 ; - assign rg_word64_set_in_cache$EN = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule f_reset_reqs - assign f_reset_reqs$D_IN = !EN_server_reset_request_put ; - assign f_reset_reqs$ENQ = - EN_server_reset_request_put || EN_server_flush_request_put ; - assign f_reset_reqs$DEQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ; - assign f_reset_rsps$ENQ = - WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ; - assign f_reset_rsps$DEQ = - EN_server_flush_response_get || EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule ram_state_and_ctag_cset - assign ram_state_and_ctag_cset$ADDRA = - WILL_FIRE_RL_rl_start_cache_refill ? - rg_addr[11:6] : - rg_cset_in_cache ; - assign ram_state_and_ctag_cset$ADDRB = - MUX_ram_state_and_ctag_cset$b_put_2__SEL_1 ? - req_addr[11:6] : - rg_addr[11:6] ; - assign ram_state_and_ctag_cset$DIA = - WILL_FIRE_RL_rl_start_cache_refill ? - MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 : - 53'h0AAAAAAAAAAAAA ; - assign ram_state_and_ctag_cset$DIB = - MUX_ram_state_and_ctag_cset$b_put_2__SEL_1 ? - 53'h0AAAAAAAAAAAAA /* unspecified value */ : - 53'h0AAAAAAAAAAAAA /* unspecified value */ ; - assign ram_state_and_ctag_cset$WEA = 1'd1 ; - assign ram_state_and_ctag_cset$WEB = 1'd0 ; - assign ram_state_and_ctag_cset$ENA = - WILL_FIRE_RL_rl_start_cache_refill || WILL_FIRE_RL_rl_reset ; - assign ram_state_and_ctag_cset$ENB = - EN_req && - req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 || - WILL_FIRE_RL_rl_rereq ; - - // submodule ram_word64_set - assign ram_word64_set$ADDRA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - rg_word64_set_in_cache : - rg_addr[11:3] ; - always@(MUX_ram_state_and_ctag_cset$b_put_2__SEL_1 or - req_addr or - MUX_ram_word64_set$b_put_1__SEL_2 or - MUX_ram_word64_set$b_put_2__VAL_2 or - WILL_FIRE_RL_rl_rereq or - rg_addr or - WILL_FIRE_RL_rl_start_cache_refill or - MUX_ram_word64_set$b_put_2__VAL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_2__SEL_1: - ram_word64_set$ADDRB = req_addr[11:3]; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2; - WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3]; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4; - default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ; - endcase - end - assign ram_word64_set$DIA = - MUX_ram_word64_set$a_put_1__SEL_1 ? - master_xactor_rg_rd_data[66:3] : - MUX_ram_word64_set$a_put_3__VAL_2 ; - always@(MUX_ram_state_and_ctag_cset$b_put_2__SEL_1 or - MUX_ram_word64_set$b_put_1__SEL_2 or - WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill) - begin - case (1'b1) // synopsys parallel_case - MUX_ram_state_and_ctag_cset$b_put_2__SEL_1: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - MUX_ram_word64_set$b_put_1__SEL_2: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_rereq: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - WILL_FIRE_RL_rl_start_cache_refill: - ram_word64_set$DIB = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - default: ram_word64_set$DIB = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign ram_word64_set$WEA = 1'd1 ; - assign ram_word64_set$WEB = 1'd0 ; - assign ram_word64_set$ENA = - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] == 2'b0 || - WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d309 ; - assign ram_word64_set$ENB = - EN_req && - req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 || - WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] != 3'd7 || - WILL_FIRE_RL_rl_rereq || - WILL_FIRE_RL_rl_start_cache_refill ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = rg_addr ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271 = - (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 = - (rg_addr[2:0] == 3'h0) ? ld_val__h24158 : 64'd0 ; - assign IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 = - (rg_addr[2:0] == 3'h0) ? word64__h5281 : 64'd0 ; - assign IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 = - (rg_f3 == 3'b010) ? - { {32{rg_st_amo_val_BITS_31_TO_0__q31[31]}}, - rg_st_amo_val_BITS_31_TO_0__q31 } : - rg_st_amo_val ; - assign IF_rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d110 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 5'd9 : - IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d109 ; - assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d109 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - 5'd12 : - ((!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) ? - 5'd9 : - 5'd12) ; - assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d466 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - mem_req_wr_data_wdata__h16835 : - mem_req_wr_data_wdata__h20332 ; - assign IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d78 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ? - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d68 : - !ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read ; - assign NOT_cfg_verbosity_read__0_ULE_1_1___d12 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read__0_ULE_2_54___d555 = cfg_verbosity > 4'd2 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d298 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - rg_op != 2'd1 && ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d309 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d307 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d443 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d441 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d479 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 && - rg_addr_0_EQ_rg_lrsc_pa_8___d117 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d491 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d519 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d517 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d520 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d524 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d532 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d530 ; - assign NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d534 = - (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306 ; - assign NOT_ram_state_and_ctag_cset_b_read__9_BIT_52_0_ETC___d119 = - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - rg_addr_0_EQ_rg_lrsc_pa_8___d117 ; - assign NOT_req_f3_BITS_1_TO_0_90_EQ_0b0_91_92_AND_NOT_ETC___d911 = - req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && - (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && - (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; - assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d105 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) ; - assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d446 = - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d444 || - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306) ; - assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d492 ; - assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d500 ; - assign NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d505 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d128 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - rg_addr_0_EQ_rg_lrsc_pa_8___d117 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d440 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d517 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d520 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d524 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d530 = - rg_op != 2'd1 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - rg_addr_0_EQ_rg_lrsc_pa_8___d117 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d304 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d438 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - (rg_f3 == 3'b0 || rg_f3 == 3'b001) ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d492 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d496 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d500 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d505 = - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) && - ctr_wr_rsps_pending_crg == 4'd15 ; - assign _theResult___snd_fst__h16843 = rg_st_amo_val << shift_bits__h20133 ; - assign _theResult___snd_fst__h20340 = - new_st_val__h17351 << shift_bits__h20133 ; - assign _theResult___snd_fst__h25769 = rg_st_amo_val << shift_bits__h27066 ; - assign _theResult___snd_fst__h27273 = st_val__h27010 << shift_bits__h27066 ; - assign access_exc_code__h2925 = - dmem_not_imem ? - ((rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ? - 4'd5 : - 4'd7) : - 4'd1 ; - assign b__h20935 = - ctr_wr_rsps_pending_crg$EN_port0__write ? - ctr_wr_rsps_pending_crg$port0__write_1 : - ctr_wr_rsps_pending_crg ; - assign cline_fabric_addr__h21034 = { rg_pa[63:6], 6'd0 } ; - assign dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d80 = - dmem_not_imem && !soc_map$m_is_mem_addr || rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 || - IF_rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_ETC___d78 ; - assign ld_val4158_BITS_15_TO_0__q36 = ld_val__h24158[15:0] ; - assign ld_val4158_BITS_15_TO_8__q38 = ld_val__h24158[15:8] ; - assign ld_val4158_BITS_23_TO_16__q39 = ld_val__h24158[23:16] ; - assign ld_val4158_BITS_31_TO_0__q37 = ld_val__h24158[31:0] ; - assign ld_val4158_BITS_31_TO_16__q40 = ld_val__h24158[31:16] ; - assign ld_val4158_BITS_31_TO_24__q41 = ld_val__h24158[31:24] ; - assign ld_val4158_BITS_39_TO_32__q42 = ld_val__h24158[39:32] ; - assign ld_val4158_BITS_47_TO_32__q43 = ld_val__h24158[47:32] ; - assign ld_val4158_BITS_47_TO_40__q45 = ld_val__h24158[47:40] ; - assign ld_val4158_BITS_55_TO_48__q46 = ld_val__h24158[55:48] ; - assign ld_val4158_BITS_63_TO_32__q44 = ld_val__h24158[63:32] ; - assign ld_val4158_BITS_63_TO_48__q47 = ld_val__h24158[63:48] ; - assign ld_val4158_BITS_63_TO_56__q48 = ld_val__h24158[63:56] ; - assign ld_val4158_BITS_7_TO_0__q35 = ld_val__h24158[7:0] ; - assign lrsc_result__h13131 = - !rg_lrsc_valid || !rg_lrsc_pa_8_EQ_rg_addr_0___d59 ; - assign master_xactor_crg_rd_data_full_port1__read__51_ETC___d723 = - master_xactor_crg_rd_data_full$port1__read && - (master_xactor_rg_rd_data[2:1] != 2'b0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; - assign master_xactor_rg_rd_data_BITS_10_TO_3__q1 = - master_xactor_rg_rd_data[10:3] ; - assign master_xactor_rg_rd_data_BITS_18_TO_11__q4 = - master_xactor_rg_rd_data[18:11] ; - assign master_xactor_rg_rd_data_BITS_18_TO_3__q2 = - master_xactor_rg_rd_data[18:3] ; - assign master_xactor_rg_rd_data_BITS_26_TO_19__q5 = - master_xactor_rg_rd_data[26:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_19__q6 = - master_xactor_rg_rd_data[34:19] ; - assign master_xactor_rg_rd_data_BITS_34_TO_27__q7 = - master_xactor_rg_rd_data[34:27] ; - assign master_xactor_rg_rd_data_BITS_34_TO_3__q3 = - master_xactor_rg_rd_data[34:3] ; - assign master_xactor_rg_rd_data_BITS_42_TO_35__q8 = - master_xactor_rg_rd_data[42:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_35__q9 = - master_xactor_rg_rd_data[50:35] ; - assign master_xactor_rg_rd_data_BITS_50_TO_43__q11 = - master_xactor_rg_rd_data[50:43] ; - assign master_xactor_rg_rd_data_BITS_58_TO_51__q12 = - master_xactor_rg_rd_data[58:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_35__q10 = - master_xactor_rg_rd_data[66:35] ; - assign master_xactor_rg_rd_data_BITS_66_TO_51__q13 = - master_xactor_rg_rd_data[66:51] ; - assign master_xactor_rg_rd_data_BITS_66_TO_59__q14 = - master_xactor_rg_rd_data[66:59] ; - assign new_st_val__h17351 = - (rg_f3 == 3'b010) ? - new_st_val__h17633 : - _theResult_____2__h17629 ; - assign new_st_val__h17633 = { 32'd0, _theResult_____2__h17629[31:0] } ; - assign new_st_val__h17724 = - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 + - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ; - assign new_st_val__h18704 = w1__h17621 ^ w2__h27284 ; - assign new_st_val__h18708 = w1__h17621 & w2__h27284 ; - assign new_st_val__h18712 = w1__h17621 | w2__h27284 ; - assign new_st_val__h18716 = - (w1__h17621 < w2__h27284) ? w1__h17621 : w2__h27284 ; - assign new_st_val__h18721 = - (w1__h17621 <= w2__h27284) ? w2__h27284 : w1__h17621 ; - assign new_st_val__h18727 = - ((IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 ^ - 64'h8000000000000000) < - (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^ - 64'h8000000000000000)) ? - w1__h17621 : - w2__h27284 ; - assign new_st_val__h18732 = - ((IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 ^ - 64'h8000000000000000) <= - (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^ - 64'h8000000000000000)) ? - w2__h27284 : - w1__h17621 ; - assign new_st_val__h27294 = { 32'd0, _theResult_____2__h27290[31:0] } ; - assign new_st_val__h27385 = - new_ld_val__h26998 + - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ; - assign new_st_val__h29245 = w1__h27282 ^ w2__h27284 ; - assign new_st_val__h29249 = w1__h27282 & w2__h27284 ; - assign new_st_val__h29253 = w1__h27282 | w2__h27284 ; - assign new_st_val__h29257 = - (w1__h27282 < w2__h27284) ? w1__h27282 : w2__h27284 ; - assign new_st_val__h29262 = - (w1__h27282 <= w2__h27284) ? w2__h27284 : w1__h27282 ; - assign new_st_val__h29268 = - ((new_ld_val__h26998 ^ 64'h8000000000000000) < - (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^ - 64'h8000000000000000)) ? - w1__h27282 : - w2__h27284 ; - assign new_st_val__h29273 = - ((new_ld_val__h26998 ^ 64'h8000000000000000) <= - (IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_rg_st_amo_val_ETC___d366 ^ - 64'h8000000000000000)) ? - w2__h27284 : - w1__h27282 ; - assign new_value462_BITS_31_TO_0__q30 = new_value__h5462[31:0] ; - assign ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 = - ram_state_and_ctag_cset$DOB[51:0] == rg_addr[63:12] ; - assign ram_state_and_ctag_cset_b_read__9_BIT_52_0_AND_ETC___d120 = - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 || - NOT_ram_state_and_ctag_cset_b_read__9_BIT_52_0_ETC___d119 ; - assign req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 = - req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || - req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || - req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; - assign result__h11871 = - { {56{word64281_BITS_15_TO_8__q18[7]}}, - word64281_BITS_15_TO_8__q18 } ; - assign result__h11899 = - { {56{word64281_BITS_23_TO_16__q19[7]}}, - word64281_BITS_23_TO_16__q19 } ; - assign result__h11927 = - { {56{word64281_BITS_31_TO_24__q21[7]}}, - word64281_BITS_31_TO_24__q21 } ; - assign result__h11955 = - { {56{word64281_BITS_39_TO_32__q22[7]}}, - word64281_BITS_39_TO_32__q22 } ; - assign result__h11983 = - { {56{word64281_BITS_47_TO_40__q25[7]}}, - word64281_BITS_47_TO_40__q25 } ; - assign result__h12011 = - { {56{word64281_BITS_55_TO_48__q26[7]}}, - word64281_BITS_55_TO_48__q26 } ; - assign result__h12039 = - { {56{word64281_BITS_63_TO_56__q28[7]}}, - word64281_BITS_63_TO_56__q28 } ; - assign result__h12084 = { 56'd0, word64__h5281[7:0] } ; - assign result__h12112 = { 56'd0, word64__h5281[15:8] } ; - assign result__h12140 = { 56'd0, word64__h5281[23:16] } ; - assign result__h12168 = { 56'd0, word64__h5281[31:24] } ; - assign result__h12196 = { 56'd0, word64__h5281[39:32] } ; - assign result__h12224 = { 56'd0, word64__h5281[47:40] } ; - assign result__h12252 = { 56'd0, word64__h5281[55:48] } ; - assign result__h12280 = { 56'd0, word64__h5281[63:56] } ; - assign result__h12325 = - { {48{word64281_BITS_15_TO_0__q16[15]}}, - word64281_BITS_15_TO_0__q16 } ; - assign result__h12353 = - { {48{word64281_BITS_31_TO_16__q20[15]}}, - word64281_BITS_31_TO_16__q20 } ; - assign result__h12381 = - { {48{word64281_BITS_47_TO_32__q23[15]}}, - word64281_BITS_47_TO_32__q23 } ; - assign result__h12409 = - { {48{word64281_BITS_63_TO_48__q27[15]}}, - word64281_BITS_63_TO_48__q27 } ; - assign result__h12450 = { 48'd0, word64__h5281[15:0] } ; - assign result__h12478 = { 48'd0, word64__h5281[31:16] } ; - assign result__h12506 = { 48'd0, word64__h5281[47:32] } ; - assign result__h12534 = { 48'd0, word64__h5281[63:48] } ; - assign result__h12575 = - { {32{word64281_BITS_31_TO_0__q17[31]}}, - word64281_BITS_31_TO_0__q17 } ; - assign result__h12603 = - { {32{word64281_BITS_63_TO_32__q24[31]}}, - word64281_BITS_63_TO_32__q24 } ; - assign result__h12642 = { 32'd0, word64__h5281[31:0] } ; - assign result__h12670 = { 32'd0, word64__h5281[63:32] } ; - assign result__h24218 = - { {56{master_xactor_rg_rd_data_BITS_10_TO_3__q1[7]}}, - master_xactor_rg_rd_data_BITS_10_TO_3__q1 } ; - assign result__h24248 = - { {56{master_xactor_rg_rd_data_BITS_18_TO_11__q4[7]}}, - master_xactor_rg_rd_data_BITS_18_TO_11__q4 } ; - assign result__h24275 = - { {56{master_xactor_rg_rd_data_BITS_26_TO_19__q5[7]}}, - master_xactor_rg_rd_data_BITS_26_TO_19__q5 } ; - assign result__h24302 = - { {56{master_xactor_rg_rd_data_BITS_34_TO_27__q7[7]}}, - master_xactor_rg_rd_data_BITS_34_TO_27__q7 } ; - assign result__h24329 = - { {56{master_xactor_rg_rd_data_BITS_42_TO_35__q8[7]}}, - master_xactor_rg_rd_data_BITS_42_TO_35__q8 } ; - assign result__h24356 = - { {56{master_xactor_rg_rd_data_BITS_50_TO_43__q11[7]}}, - master_xactor_rg_rd_data_BITS_50_TO_43__q11 } ; - assign result__h24383 = - { {56{master_xactor_rg_rd_data_BITS_58_TO_51__q12[7]}}, - master_xactor_rg_rd_data_BITS_58_TO_51__q12 } ; - assign result__h24410 = - { {56{master_xactor_rg_rd_data_BITS_66_TO_59__q14[7]}}, - master_xactor_rg_rd_data_BITS_66_TO_59__q14 } ; - assign result__h24454 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h24481 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h24508 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h24535 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h24562 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h24589 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h24616 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h24643 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h24687 = - { {48{master_xactor_rg_rd_data_BITS_18_TO_3__q2[15]}}, - master_xactor_rg_rd_data_BITS_18_TO_3__q2 } ; - assign result__h24714 = - { {48{master_xactor_rg_rd_data_BITS_34_TO_19__q6[15]}}, - master_xactor_rg_rd_data_BITS_34_TO_19__q6 } ; - assign result__h24741 = - { {48{master_xactor_rg_rd_data_BITS_50_TO_35__q9[15]}}, - master_xactor_rg_rd_data_BITS_50_TO_35__q9 } ; - assign result__h24768 = - { {48{master_xactor_rg_rd_data_BITS_66_TO_51__q13[15]}}, - master_xactor_rg_rd_data_BITS_66_TO_51__q13 } ; - assign result__h24808 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h24835 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h24862 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h24889 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h24929 = - { {32{master_xactor_rg_rd_data_BITS_34_TO_3__q3[31]}}, - master_xactor_rg_rd_data_BITS_34_TO_3__q3 } ; - assign result__h24956 = - { {32{master_xactor_rg_rd_data_BITS_66_TO_35__q10[31]}}, - master_xactor_rg_rd_data_BITS_66_TO_35__q10 } ; - assign result__h24994 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h25021 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; - assign result__h27473 = - { {56{ld_val4158_BITS_7_TO_0__q35[7]}}, - ld_val4158_BITS_7_TO_0__q35 } ; - assign result__h28381 = - { {56{ld_val4158_BITS_15_TO_8__q38[7]}}, - ld_val4158_BITS_15_TO_8__q38 } ; - assign result__h28409 = - { {56{ld_val4158_BITS_23_TO_16__q39[7]}}, - ld_val4158_BITS_23_TO_16__q39 } ; - assign result__h28437 = - { {56{ld_val4158_BITS_31_TO_24__q41[7]}}, - ld_val4158_BITS_31_TO_24__q41 } ; - assign result__h28465 = - { {56{ld_val4158_BITS_39_TO_32__q42[7]}}, - ld_val4158_BITS_39_TO_32__q42 } ; - assign result__h28493 = - { {56{ld_val4158_BITS_47_TO_40__q45[7]}}, - ld_val4158_BITS_47_TO_40__q45 } ; - assign result__h28521 = - { {56{ld_val4158_BITS_55_TO_48__q46[7]}}, - ld_val4158_BITS_55_TO_48__q46 } ; - assign result__h28549 = - { {56{ld_val4158_BITS_63_TO_56__q48[7]}}, - ld_val4158_BITS_63_TO_56__q48 } ; - assign result__h28594 = { 56'd0, ld_val__h24158[7:0] } ; - assign result__h28622 = { 56'd0, ld_val__h24158[15:8] } ; - assign result__h28650 = { 56'd0, ld_val__h24158[23:16] } ; - assign result__h28678 = { 56'd0, ld_val__h24158[31:24] } ; - assign result__h28706 = { 56'd0, ld_val__h24158[39:32] } ; - assign result__h28734 = { 56'd0, ld_val__h24158[47:40] } ; - assign result__h28762 = { 56'd0, ld_val__h24158[55:48] } ; - assign result__h28790 = { 56'd0, ld_val__h24158[63:56] } ; - assign result__h28835 = - { {48{ld_val4158_BITS_15_TO_0__q36[15]}}, - ld_val4158_BITS_15_TO_0__q36 } ; - assign result__h28863 = - { {48{ld_val4158_BITS_31_TO_16__q40[15]}}, - ld_val4158_BITS_31_TO_16__q40 } ; - assign result__h28891 = - { {48{ld_val4158_BITS_47_TO_32__q43[15]}}, - ld_val4158_BITS_47_TO_32__q43 } ; - assign result__h28919 = - { {48{ld_val4158_BITS_63_TO_48__q47[15]}}, - ld_val4158_BITS_63_TO_48__q47 } ; - assign result__h28960 = { 48'd0, ld_val__h24158[15:0] } ; - assign result__h28988 = { 48'd0, ld_val__h24158[31:16] } ; - assign result__h29016 = { 48'd0, ld_val__h24158[47:32] } ; - assign result__h29044 = { 48'd0, ld_val__h24158[63:48] } ; - assign result__h29085 = - { {32{ld_val4158_BITS_31_TO_0__q37[31]}}, - ld_val4158_BITS_31_TO_0__q37 } ; - assign result__h29113 = - { {32{ld_val4158_BITS_63_TO_32__q44[31]}}, - ld_val4158_BITS_63_TO_32__q44 } ; - assign result__h29152 = { 32'd0, ld_val__h24158[31:0] } ; - assign result__h29180 = { 32'd0, ld_val__h24158[63:32] } ; - assign result__h5515 = - { {56{word64281_BITS_7_TO_0__q15[7]}}, - word64281_BITS_7_TO_0__q15 } ; - assign rg_addr_0_EQ_rg_lrsc_pa_8___d117 = rg_addr == rg_lrsc_pa ; - assign rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d292 = - rg_amo_funct7[6:2] == 5'b00010 && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) && - rg_addr_0_EQ_rg_lrsc_pa_8___d117 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_lrsc_pa_8_EQ_rg_addr_0___d59 = rg_lrsc_pa == rg_addr ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d100 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d131 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset_b_read__9_BIT_52_0_AND_ETC___d120 || - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d129 ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d136 = - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d133 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13131 ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d288 = - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - (!ram_state_and_ctag_cset$DOB[52] || - !ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d129 = - rg_op == 2'd1 && rg_addr_0_EQ_rg_lrsc_pa_8___d117 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 || - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d128 ; - assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d307 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d304 || - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d306 ; - assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d441 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d438 || - NOT_rg_op_4_EQ_1_2_25_AND_NOT_rg_op_4_EQ_2_6_3_ETC___d440 ; - assign rg_op_4_EQ_1_2_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d444 = - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 || - rg_lrsc_valid && rg_lrsc_pa_8_EQ_rg_addr_0___d59) ; - assign rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13131 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 ; - assign rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d68 = - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 && - lrsc_result__h13131 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read ; - assign rg_st_amo_val_BITS_31_TO_0__q31 = rg_st_amo_val[31:0] ; - assign rg_state_EQ_13_90_AND_rg_op_4_EQ_0_5_OR_rg_op__ETC___d592 = - rg_state == 5'd13 && - (rg_op == 2'd0 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) && - b__h20935 == 4'd0 ; - assign rg_state_EQ_3_1_AND_NOT_rg_op_4_EQ_0_5_2_AND_N_ETC___d90 = - rg_state == 5'd3 && - (rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) || - crg_sb_to_load_delay$port0__write_1 == 11'd0) ; - assign shift_bits__h20133 = { rg_addr[2:0], 3'b0 } ; - assign shift_bits__h27066 = { rg_pa[2:0], 3'b0 } ; - assign st_val__h27010 = - (rg_f3 == 3'b010) ? - new_st_val__h27294 : - _theResult_____2__h27290 ; - assign strobe64__h20266 = 8'b00000001 << rg_addr[2:0] ; - assign strobe64__h20268 = 8'b00000011 << rg_addr[2:0] ; - assign strobe64__h20270 = 8'b00001111 << rg_addr[2:0] ; - assign strobe64__h27199 = 8'b00000001 << rg_pa[2:0] ; - assign strobe64__h27201 = 8'b00000011 << rg_pa[2:0] ; - assign strobe64__h27203 = 8'b00001111 << rg_pa[2:0] ; - assign w17278_BITS_31_TO_0__q50 = w1__h27278[31:0] ; - assign w1___1__h17692 = { 32'd0, new_value__h5462[31:0] } ; - assign w1___1__h27353 = { 32'd0, w1__h27278[31:0] } ; - assign w2___1__h27354 = { 32'd0, rg_st_amo_val[31:0] } ; - assign w2__h27284 = (rg_f3 == 3'b010) ? w2___1__h27354 : rg_st_amo_val ; - assign word64281_BITS_15_TO_0__q16 = word64__h5281[15:0] ; - assign word64281_BITS_15_TO_8__q18 = word64__h5281[15:8] ; - assign word64281_BITS_23_TO_16__q19 = word64__h5281[23:16] ; - assign word64281_BITS_31_TO_0__q17 = word64__h5281[31:0] ; - assign word64281_BITS_31_TO_16__q20 = word64__h5281[31:16] ; - assign word64281_BITS_31_TO_24__q21 = word64__h5281[31:24] ; - assign word64281_BITS_39_TO_32__q22 = word64__h5281[39:32] ; - assign word64281_BITS_47_TO_32__q23 = word64__h5281[47:32] ; - assign word64281_BITS_47_TO_40__q25 = word64__h5281[47:40] ; - assign word64281_BITS_55_TO_48__q26 = word64__h5281[55:48] ; - assign word64281_BITS_63_TO_32__q24 = word64__h5281[63:32] ; - assign word64281_BITS_63_TO_48__q27 = word64__h5281[63:48] ; - assign word64281_BITS_63_TO_56__q28 = word64__h5281[63:56] ; - assign word64281_BITS_7_TO_0__q15 = word64__h5281[7:0] ; - assign word64__h5281 = ram_word64_set$DOB & y__h5551 ; - assign x__h13141 = { 63'd0, lrsc_result__h13131 } ; - assign y__h5551 = - {64{ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74}} ; - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h26583 = 3'b0; - 2'b01: value__h26583 = 3'b001; - 2'b10: value__h26583 = 3'b010; - 2'd3: value__h26583 = 3'b011; - endcase - end - always@(rg_f3) - begin - case (rg_f3[1:0]) - 2'b0: value__h29609 = 3'b0; - 2'b01: value__h29609 = 3'b001; - 2'b10: value__h29609 = 3'b010; - 2'b11: value__h29609 = 3'b011; - endcase - end - always@(rg_f3 or strobe64__h27199 or strobe64__h27201 or strobe64__h27203) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h27266 = strobe64__h27199; - 2'b01: mem_req_wr_data_wstrb__h27266 = strobe64__h27201; - 2'b10: mem_req_wr_data_wstrb__h27266 = strobe64__h27203; - 2'b11: mem_req_wr_data_wstrb__h27266 = 8'b11111111; - endcase - end - always@(rg_f3 or strobe64__h20266 or strobe64__h20268 or strobe64__h20270) - begin - case (rg_f3[1:0]) - 2'b0: mem_req_wr_data_wstrb__h20333 = strobe64__h20266; - 2'b01: mem_req_wr_data_wstrb__h20333 = strobe64__h20268; - 2'b10: mem_req_wr_data_wstrb__h20333 = strobe64__h20270; - 2'b11: mem_req_wr_data_wstrb__h20333 = 8'b11111111; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h16843) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h16835 = _theResult___snd_fst__h16843; - 2'd3: mem_req_wr_data_wdata__h16835 = rg_st_amo_val; - endcase - end - always@(rg_f3 or rg_st_amo_val or _theResult___snd_fst__h25769) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h25761 = _theResult___snd_fst__h25769; - 2'd3: mem_req_wr_data_wdata__h25761 = rg_st_amo_val; - endcase - end - always@(rg_addr or - result__h5515 or - result__h11871 or - result__h11899 or - result__h11927 or - result__h11955 or - result__h11983 or result__h12011 or result__h12039) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h5515; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h11871; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h11899; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h11927; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h11955; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h11983; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h12011; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 = - result__h12039; - endcase - end - always@(rg_addr or - result__h12084 or - result__h12112 or - result__h12140 or - result__h12168 or - result__h12196 or - result__h12224 or result__h12252 or result__h12280) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12084; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12112; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12140; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12168; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12196; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12224; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12252; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 = - result__h12280; - endcase - end - always@(rg_addr or - result__h12325 or - result__h12353 or result__h12381 or result__h12409) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 = - result__h12325; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 = - result__h12353; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 = - result__h12381; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 = - result__h12409; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 = - 64'd0; - endcase - end - always@(rg_addr or - result__h12450 or - result__h12478 or result__h12506 or result__h12534) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 = - result__h12450; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 = - result__h12478; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 = - result__h12506; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 = - result__h12534; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 = - 64'd0; - endcase - end - always@(rg_addr or result__h12642 or result__h12670) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255 = - result__h12642; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255 = - result__h12670; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255 = - 64'd0; - endcase - end - always@(rg_addr or result__h12575 or result__h12603) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 = - result__h12575; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 = - result__h12603; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 or - CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255) - begin - case (rg_f3) - 3'b0: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204; - 3'b001: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234; - 3'b010: - new_value__h5462 = - CASE_rg_addr_BITS_2_TO_0_0x0_result2575_0x4_re_ETC__q29; - 3'b011: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257; - 3'b100: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221; - 3'b101: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243; - 3'b110: - new_value__h5462 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255; - 3'd7: new_value__h5462 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 or - w1___1__h17692 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255) - begin - case (rg_f3) - 3'b0: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204; - 3'b001: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234; - 3'b010: w1__h17621 = w1___1__h17692; - 3'b011: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257; - 3'b100: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221; - 3'b101: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243; - 3'b110: - w1__h17621 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255; - 3'd7: w1__h17621 = 64'd0; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 = - { ram_word64_set$DOB[63:16], rg_st_amo_val[15:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 = - { rg_st_amo_val[15:0], ram_word64_set$DOB[47:0] }; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:8], rg_st_amo_val[7:0] }; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:16], - rg_st_amo_val[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:24], - rg_st_amo_val[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:32], - rg_st_amo_val[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:40], - rg_st_amo_val[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:48], - rg_st_amo_val[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { ram_word64_set$DOB[63:56], - rg_st_amo_val[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 = - { rg_st_amo_val[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234 or - new_value462_BITS_31_TO_0__q30 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d204; - 3'b001: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d234; - 3'b010: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - { {32{new_value462_BITS_31_TO_0__q30[31]}}, - new_value462_BITS_31_TO_0__q30 }; - 3'b011: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d257; - 3'b100: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d221; - 3'b101: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d243; - 3'b110: - IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d255; - 3'd7: IF_rg_f3_38_EQ_0b10_44_THEN_SEXT_IF_rg_f3_38_E_ETC___d302 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h18732 or - new_st_val__h17724 or - w2__h27284 or - new_st_val__h18704 or - new_st_val__h18712 or - new_st_val__h18708 or - new_st_val__h18727 or new_st_val__h18716 or new_st_val__h18721) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h17629 = new_st_val__h17724; - 5'b00001: _theResult_____2__h17629 = w2__h27284; - 5'b00100: _theResult_____2__h17629 = new_st_val__h18704; - 5'b01000: _theResult_____2__h17629 = new_st_val__h18712; - 5'b01100: _theResult_____2__h17629 = new_st_val__h18708; - 5'b10000: _theResult_____2__h17629 = new_st_val__h18727; - 5'b11000: _theResult_____2__h17629 = new_st_val__h18716; - 5'b11100: _theResult_____2__h17629 = new_st_val__h18721; - default: _theResult_____2__h17629 = new_st_val__h18732; - endcase - end - always@(rg_f3 or new_st_val__h17351 or _theResult___snd_fst__h20340) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h20332 = _theResult___snd_fst__h20340; - 2'd3: mem_req_wr_data_wdata__h20332 = new_st_val__h17351; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17351) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 = - { ram_word64_set$DOB[63:16], new_st_val__h17351[15:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 = - { ram_word64_set$DOB[63:32], - new_st_val__h17351[15:0], - ram_word64_set$DOB[15:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 = - { ram_word64_set$DOB[63:48], - new_st_val__h17351[15:0], - ram_word64_set$DOB[31:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 = - { new_st_val__h17351[15:0], ram_word64_set$DOB[47:0] }; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17351) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:8], new_st_val__h17351[7:0] }; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:16], - new_st_val__h17351[7:0], - ram_word64_set$DOB[7:0] }; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:24], - new_st_val__h17351[7:0], - ram_word64_set$DOB[15:0] }; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:32], - new_st_val__h17351[7:0], - ram_word64_set$DOB[23:0] }; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:40], - new_st_val__h17351[7:0], - ram_word64_set$DOB[31:0] }; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:48], - new_st_val__h17351[7:0], - ram_word64_set$DOB[39:0] }; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { ram_word64_set$DOB[63:56], - new_st_val__h17351[7:0], - ram_word64_set$DOB[47:0] }; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 = - { new_st_val__h17351[7:0], ram_word64_set$DOB[55:0] }; - endcase - end - always@(rg_addr or ram_word64_set$DOB or rg_st_amo_val) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - { ram_word64_set$DOB[63:32], rg_st_amo_val[31:0] }; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - { rg_st_amo_val[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351 or - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32 or - rg_st_amo_val) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d342; - 3'b001: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d351; - 3'b010: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 = - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q32; - 3'b011: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 = - rg_st_amo_val; - default: IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360 = - ram_word64_set$DOB; - endcase - end - always@(rg_addr or - result__h24808 or - result__h24835 or result__h24862 or result__h24889) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 = - result__h24808; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 = - result__h24835; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 = - result__h24862; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 = - result__h24889; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 = - 64'd0; - endcase - end - always@(rg_addr or - result__h24687 or - result__h24714 or result__h24741 or result__h24768) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 = - result__h24687; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 = - result__h24714; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 = - result__h24741; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 = - result__h24768; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 = - 64'd0; - endcase - end - always@(rg_addr or - result__h24454 or - result__h24481 or - result__h24508 or - result__h24535 or - result__h24562 or - result__h24589 or result__h24616 or result__h24643) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24454; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24481; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24508; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24535; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24562; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24589; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24616; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 = - result__h24643; - endcase - end - always@(rg_addr or - result__h24218 or - result__h24248 or - result__h24275 or - result__h24302 or - result__h24329 or - result__h24356 or result__h24383 or result__h24410) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24218; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24248; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24275; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24302; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24329; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24356; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24383; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 = - result__h24410; - endcase - end - always@(rg_addr or result__h24929 or result__h24956) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 = - result__h24929; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 = - result__h24956; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 = - 64'd0; - endcase - end - always@(rg_addr or result__h24994 or result__h25021) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34 = - result__h24994; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34 = - result__h25021; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33 or - rg_addr or - master_xactor_rg_rd_data or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666 or - CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34) - begin - case (rg_f3) - 3'b0: - ld_val__h24158 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d630; - 3'b001: - ld_val__h24158 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d658; - 3'b010: - ld_val__h24158 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4929_0x4_re_ETC__q33; - 3'b011: - ld_val__h24158 = - (rg_addr[2:0] == 3'h0) ? master_xactor_rg_rd_data[66:3] : 64'd0; - 3'b100: - ld_val__h24158 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d646; - 3'b101: - ld_val__h24158 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d666; - 3'b110: - ld_val__h24158 = - CASE_rg_addr_BITS_2_TO_0_0x0_result4994_0x4_re_ETC__q34; - 3'd7: ld_val__h24158 = 64'd0; - endcase - end - always@(rg_addr or result__h29152 or result__h29180) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799 = - result__h29152; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799 = - result__h29180; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28960 or - result__h28988 or result__h29016 or result__h29044) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 = - result__h28960; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 = - result__h28988; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 = - result__h29016; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 = - result__h29044; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 = - 64'd0; - endcase - end - always@(rg_addr or - result__h28594 or - result__h28622 or - result__h28650 or - result__h28678 or - result__h28706 or - result__h28734 or result__h28762 or result__h28790) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28594; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28622; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28650; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28678; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28706; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28734; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28762; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 = - result__h28790; - endcase - end - always@(rg_addr or - result__h28835 or - result__h28863 or result__h28891 or result__h28919) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 = - result__h28835; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 = - result__h28863; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 = - result__h28891; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 = - result__h28919; - default: IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 = - 64'd0; - endcase - end - always@(rg_addr or - result__h27473 or - result__h28381 or - result__h28409 or - result__h28437 or - result__h28465 or - result__h28493 or result__h28521 or result__h28549) - begin - case (rg_addr[2:0]) - 3'h0: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h27473; - 3'h1: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28381; - 3'h2: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28409; - 3'h3: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28437; - 3'h4: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28465; - 3'h5: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28493; - 3'h6: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28521; - 3'h7: - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 = - result__h28549; - endcase - end - always@(rg_addr or result__h29085 or result__h29113) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 = - result__h29085; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 = - result__h29113; - default: CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 = - 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 or - CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799) - begin - case (rg_f3) - 3'b0: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753; - 3'b001: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781; - 3'b010: - w1__h27278 = - CASE_rg_addr_BITS_2_TO_0_0x0_result9085_0x4_re_ETC__q49; - 3'b011: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800; - 3'b100: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769; - 3'b101: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789; - 3'b110: - w1__h27278 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799; - 3'd7: w1__h27278 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 or - w1___1__h27353 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799) - begin - case (rg_f3) - 3'b0: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753; - 3'b001: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781; - 3'b010: w1__h27282 = w1___1__h27353; - 3'b011: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800; - 3'b100: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769; - 3'b101: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789; - 3'b110: - w1__h27282 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799; - 3'd7: w1__h27282 = 64'd0; - endcase - end - always@(rg_f3 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781 or - w17278_BITS_31_TO_0__q50 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799) - begin - case (rg_f3) - 3'b0: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d753; - 3'b001: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_SEXT_ETC___d781; - 3'b010: - new_ld_val__h26998 = - { {32{w17278_BITS_31_TO_0__q50[31]}}, - w17278_BITS_31_TO_0__q50 }; - 3'b011: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_IF_r_ETC___d800; - 3'b100: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d769; - 3'b101: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d789; - 3'b110: - new_ld_val__h26998 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_0_CO_ETC___d799; - 3'd7: new_ld_val__h26998 = 64'd0; - endcase - end - always@(rg_amo_funct7 or - new_st_val__h29273 or - new_st_val__h27385 or - w2__h27284 or - new_st_val__h29245 or - new_st_val__h29253 or - new_st_val__h29249 or - new_st_val__h29268 or new_st_val__h29257 or new_st_val__h29262) - begin - case (rg_amo_funct7[6:2]) - 5'b0: _theResult_____2__h27290 = new_st_val__h27385; - 5'b00001: _theResult_____2__h27290 = w2__h27284; - 5'b00100: _theResult_____2__h27290 = new_st_val__h29245; - 5'b01000: _theResult_____2__h27290 = new_st_val__h29253; - 5'b01100: _theResult_____2__h27290 = new_st_val__h29249; - 5'b10000: _theResult_____2__h27290 = new_st_val__h29268; - 5'b11000: _theResult_____2__h27290 = new_st_val__h29257; - 5'b11100: _theResult_____2__h27290 = new_st_val__h29262; - default: _theResult_____2__h27290 = new_st_val__h29273; - endcase - end - always@(rg_f3 or st_val__h27010 or _theResult___snd_fst__h27273) - begin - case (rg_f3[1:0]) - 2'b0, 2'b01, 2'b10: - mem_req_wr_data_wdata__h27265 = _theResult___snd_fst__h27273; - 2'd3: mem_req_wr_data_wdata__h27265 = st_val__h27010; - endcase - end - always@(rg_addr or ram_word64_set$DOB or new_st_val__h17351) - begin - case (rg_addr[2:0]) - 3'h0: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - { ram_word64_set$DOB[63:32], new_st_val__h17351[31:0] }; - 3'h4: - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - { new_st_val__h17351[31:0], ram_word64_set$DOB[31:0] }; - default: CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or - ram_word64_set$DOB or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416 or - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425 or - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51 or - new_st_val__h17351) - begin - case (rg_f3) - 3'b0: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d416; - 3'b001: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_ram__ETC___d425; - 3'b010: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 = - CASE_rg_addr_BITS_2_TO_0_0x0_ram_word64_setDO_ETC__q51; - 3'b011: - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 = - new_st_val__h17351; - default: IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434 = - ram_word64_set$DOB; - endcase - end - always@(rg_f3 or IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271) - begin - case (rg_f3) - 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: - new_value__h15489 = - IF_rg_addr_0_BITS_2_TO_0_6_EQ_0x0_40_THEN_1_EL_ETC___d271; - 3'd7: new_value__h15489 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0; - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_sb_to_load_delay$EN) - crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY - crg_sb_to_load_delay$D_IN; - if (ctr_wr_rsps_pending_crg$EN) - ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY - ctr_wr_rsps_pending_crg$D_IN; - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; - if (rg_cset_in_cache$EN) - rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN; - if (rg_lower_word32_full$EN) - rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY - rg_lower_word32_full$D_IN; - if (rg_lrsc_valid$EN) - rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; - if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN; - if (rg_amo_funct7$EN) - rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN; - if (rg_error_during_refill$EN) - rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY - rg_error_during_refill$D_IN; - if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN; - if (rg_lower_word32$EN) - rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN; - if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN; - if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN; - if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN; - if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN; - if (rg_st_amo_val$EN) - rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN; - if (rg_word64_set_in_cache$EN) - rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY - rg_word64_set_in_cache$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_sb_to_load_delay = 11'h2AA; - ctr_wr_rsps_pending_crg = 4'hA; - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; - rg_addr = 64'hAAAAAAAAAAAAAAAA; - rg_amo_funct7 = 7'h2A; - rg_cset_in_cache = 6'h2A; - rg_error_during_refill = 1'h0; - rg_exc_code = 4'hA; - rg_f3 = 3'h2; - rg_ld_val = 64'hAAAAAAAAAAAAAAAA; - rg_lower_word32 = 32'hAAAAAAAA; - rg_lower_word32_full = 1'h0; - rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA; - rg_lrsc_valid = 1'h0; - rg_op = 2'h2; - rg_pa = 64'hAAAAAAAAAAAAAAAA; - rg_pte_pa = 64'hAAAAAAAAAAAAAAAA; - rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; - rg_state = 5'h0A; - rg_word64_set_in_cache = 9'h0AA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - begin - v__h3732 = $stime; - #0; - end - v__h3726 = v__h3732 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - cfg_verbosity != 4'd0 && - !f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h3726, - "D_MMU_Cache", - $signed(32'd64), - $signed(32'd1)); - else - $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", - v__h3726, - "I_MMU_Cache", - $signed(32'd64), - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - f_reset_reqs$D_OUT) - begin - v__h3833 = $stime; - #0; - end - v__h3827 = v__h3833 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - f_reset_reqs$D_OUT) - if (dmem_not_imem) - $display("%0d: %s.rl_reset: Flushed", v__h3827, "D_MMU_Cache"); - else - $display("%0d: %s.rl_reset: Flushed", v__h3827, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_rereq && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - rg_addr[11:6], - rg_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25363 = $stime; - #0; - end - v__h25357 = v__h25363 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_maintain_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25357, - "D_MMU_Cache", - rg_addr, - rg_ld_val); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25357, - "I_MMU_Cache", - rg_addr, - rg_ld_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26261 = $stime; - #0; - end - v__h26255 = v__h26261 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26255, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26255, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" FAIL due to I/O address."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_SC_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h3369 = $stime; - #0; - end - v__h3363 = v__h3369 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_reset && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_start_reset", v__h3363, "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_reset", v__h3363, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h4286 = $stime; - #0; - end - v__h4280 = v__h4286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h4280, - "D_MMU_Cache", - rg_addr); - else - $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", - v__h4280, - "I_MMU_Cache", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", - rg_addr[63:12], - rg_addr[11:6], - rg_addr[5:3], - rg_addr[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" CSet 0x%0x: (state, tag):", rg_addr[11:6]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" ("); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - ram_state_and_ctag_cset$DOB[52]) - $write("CTAG_CLEAN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !ram_state_and_ctag_cset$DOB[52]) - $write("CTAG_EMPTY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - ram_state_and_ctag_cset$DOB[52]) - $write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !ram_state_and_ctag_cset$DOB[52]) - $write(", --"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(")"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" TLB result: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("VM_Xlate_Result { ", "outcome: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("VM_XLATE_OK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "pa: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "exc_code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'hA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && dmem_not_imem && - !soc_map$m_is_mem_addr && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => IO_REQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275) - begin - v__h12754 = $stime; - #0; - end - v__h12748 = v__h12754 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h12748, - "D_MMU_Cache", - rg_addr, - word64__h5281, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h12748, - "I_MMU_Cache", - rg_addr, - word64__h5281, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00010 && - ram_state_and_ctag_cset$DOB[52] && - ram_state_and_ctag_cset_b_read__9_BITS_51_TO_0_ETC___d74 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO LR: reserving PA 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d275) - $display(" Read-hit: addr 0x%0h word64 0x%0h", - rg_addr, - word64__h5281); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_0_5_OR_rg_op_4_EQ_2_6_AND_rg_amo_fu_ETC___d288) - $display(" Read Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7_7_BITS_6_TO_2_8_EQ_0b10_9_AND_NO_ETC___d292) - $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", - rg_lrsc_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d479) - $display(" ST: cancelling LR/SC reservation for PA", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - rg_lrsc_valid && - !rg_lrsc_pa_8_EQ_rg_addr_0___d59 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", - rg_lrsc_pa, - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op == 2'd2 && - rg_amo_funct7[6:2] == 5'b00011 && - !rg_lrsc_valid && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" AMO SC: fail due to invalid LR/SC reservation"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d491) - $display(" AMO SC result = %0d", lrsc_result__h13131); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494) - $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494) - $write(" 0x%0x", - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d360); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d494) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op != 2'd0 && - (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) && - (rg_op == 2'd1 || - rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) && - NOT_rg_op_4_EQ_2_6_3_OR_NOT_rg_amo_funct7_7_BI_ETC___d496) - $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", - rg_addr, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507) - begin - v__h17070 = $stime; - #0; - end - v__h17064 = v__h17070 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507) - $display("%0d: ERROR: CreditCounter: overflow", v__h17064); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d507) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", value__h29609); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", mem_req_wr_data_wdata__h16835); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", mem_req_wr_data_wstrb__h20333); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - NOT_rg_op_4_EQ_0_5_2_AND_NOT_rg_op_4_EQ_2_6_3__ETC___d502) - $display(" => rl_write_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513) - begin - v__h16398 = $stime; - #0; - end - v__h16392 = v__h16398 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513) - if (dmem_not_imem) - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h16392, - "D_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - else - $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", - v__h16392, - "I_MMU_Cache", - rg_addr, - 64'd1, - 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - (!dmem_not_imem || soc_map$m_is_mem_addr) && - rg_op_4_EQ_2_6_AND_rg_amo_funct7_7_BITS_6_TO_2_ETC___d513) - $display(" AMO SC: Fail response for addr 0x%0h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d519) - $display(" AMO Miss: -> CACHE_START_REFILL."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", - rg_addr, - rg_amo_funct7, - rg_f3, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $display(" PA 0x%0h ", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $display(" Cache word64 0x%0h, load-result 0x%0h", - word64__h5281, - word64__h5281); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $display(" 0x%0h op 0x%0h -> 0x%0h", - word64__h5281, - word64__h5281, - new_st_val__h17351); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(" New Word64_Set:"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_addr[5:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(" 0x%0x", - IF_rg_f3_38_EQ_0b0_39_THEN_IF_rg_addr_0_BITS_2_ETC___d434); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526) - begin - v__h20536 = $stime; - #0; - end - v__h20530 = v__h20536 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526) - $display("%0d: ERROR: CreditCounter: overflow", v__h20530); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d526) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", value__h29609); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", mem_req_wr_data_wdata__h20332); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", mem_req_wr_data_wstrb__h20333); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d522) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_probe_and_immed_rsp && - NOT_dmem_not_imem_13_OR_soc_map_m_is_mem_addr__ETC___d532) - $display(" AMO_op: cancelling LR/SC reservation for PA", - rg_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - begin - v__h21830 = $stime; - #0; - end - v__h21824 = v__h21830 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h21824, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_cache_refill_rsps_loop:", - v__h21824, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h22071 = $stime; - #0; - end - v__h22065 = v__h22071 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h22065, - "D_MMU_Cache", - access_exc_code__h2925); - else - $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", - v__h22065, - "I_MMU_Cache", - access_exc_code__h2925); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 && - (master_xactor_rg_rd_data[2:1] != 2'b0 || rg_error_during_refill) && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => MODULE_EXCEPTION_RSP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - rg_word64_set_in_cache[2:0] == 3'd7 && - master_xactor_rg_rd_data[2:1] == 2'b0 && - !rg_error_during_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => CACHE_REREQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", - rg_word64_set_in_cache, - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(" 0x%0x", ram_word64_set$DOB); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(" CSet 0x%0x, Word64 0x%0x: ", - rg_addr[11:6], - rg_word64_set_in_cache[2:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write(" 0x%0x", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_cache_refill_rsps_loop && - NOT_cfg_verbosity_read__0_ULE_2_54___d555) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h24049 = $stime; - #0; - end - v__h24043 = v__h24049 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h24043, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h24043, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25151 = $stime; - #0; - end - v__h25145 = v__h25151 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25145, - "D_MMU_Cache", - rg_addr, - ld_val__h24158); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h25145, - "I_MMU_Cache", - rg_addr, - ld_val__h24158); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25258 = $stime; - #0; - end - v__h25252 = v__h25258 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h25252, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", - v__h25252, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h25443 = $stime; - #0; - end - v__h25437 = v__h25443 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h25437, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h25437, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h25965 = $stime; - #0; - end - v__h25959 = v__h25965 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h25959); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h29609); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wdata__h25761); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wstrb__h27266); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_write_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26379 = $stime; - #0; - end - v__h26373 = v__h26379 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h26373, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", - v__h26373, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h26583); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_op_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26697 = $stime; - #0; - end - v__h26691 = v__h26697 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h26691, - "D_MMU_Cache", - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", - v__h26691, - "I_MMU_Cache", - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_rd_data[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - master_xactor_rg_rd_data[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - !master_xactor_rg_rd_data[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26872 = $stime; - #0; - end - v__h26866 = v__h26872 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26866, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - else - $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", - v__h26866, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa, - rg_st_amo_val); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - begin - v__h29485 = $stime; - #0; - end - v__h29479 = v__h29485 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h29479); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - ctr_wr_rsps_pending_crg == 4'd15) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h29609); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wdata__h27265); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", mem_req_wr_data_wstrb__h27266); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h29737 = $stime; - #0; - end - v__h29731 = v__h29737 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29731, - "D_MMU_Cache", - rg_addr, - new_ld_val__h26998); - else - $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", - v__h29731, - "I_MMU_Cache", - rg_addr, - new_ld_val__h26998); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" => rl_ST_AMO_response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h26968 = $stime; - #0; - end - v__h26962 = v__h26968 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_AMO_read_rsp && - master_xactor_rg_rd_data[2:1] != 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h26962, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", - v__h26962, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h20981 = $stime; - #0; - end - v__h20975 = v__h20981 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_start_cache_refill: ", - v__h20975, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_start_cache_refill: ", - v__h20975, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", cline_fabric_addr__h21034); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd7); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'b011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_start_cache_refill && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" Victim way %0d; => CACHE_REFILL", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h23675 = $stime; - #0; - end - v__h23669 = v__h23675 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h23669, - "D_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - else - $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", - v__h23669, - "I_MMU_Cache", - rg_f3, - rg_addr, - rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" To fabric: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", rg_pa); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 8'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", value__h26583); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 2'b01); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 3'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 4'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_io_read_req && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h30707 = $stime; - #0; - end - v__h30701 = v__h30707 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $write("%0d: %s.req: op:", v__h30701, "D_MMU_Cache"); - else - $write("%0d: %s.req: op:", v__h30701, "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && req_op == 2'd0) - $write("CACHE_LD"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && req_op == 2'd1) - $write("CACHE_ST"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_op != 2'd0 && - req_op != 2'd1) - $write("CACHE_AMO"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", - req_f3, - req_addr, - req_st_value); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b0) - $write("U"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b01) - $write("S"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv == 2'b11) - $write("M"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12 && - req_priv != 2'b0 && - req_priv != 2'b01 && - req_priv != 2'b11) - $write("RESERVED"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", - req_sstatus_SUM, - req_mstatus_MXR, - req_satp, - "\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" amo_funct7 = 0x%0h", req_amo_funct7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_req && - req_f3_BITS_1_TO_0_90_EQ_0b0_91_OR_req_f3_BITS_ETC___d920 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", - req_addr[11:6], - req_addr[11:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - begin - v__h30357 = $stime; - #0; - end - v__h30351 = v__h30357 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - if (dmem_not_imem) - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h30351, - "D_MMU_Cache", - $unsigned(b__h20935)); - else - $write("%0d: %s.rl_discard_write_rsp: pending %0d ", - v__h30351, - "I_MMU_Cache", - $unsigned(b__h20935)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] == 2'b0 && - NOT_cfg_verbosity_read__0_ULE_1_1___d12) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - begin - v__h30318 = $stime; - #0; - end - v__h30312 = v__h30318 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - if (dmem_not_imem) - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h30312, - "D_MMU_Cache"); - else - $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", - v__h30312, - "I_MMU_Cache"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", master_xactor_rg_wr_resp[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_discard_write_rsp && - master_xactor_rg_wr_resp[1:0] != 2'b0) - $write("\n"); - end - // synopsys translate_on -endmodule // mkMMU_Cache - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v deleted file mode 100644 index f673c615..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Controller.v +++ /dev/null @@ -1,2169 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// to_raw_mem_response_put I 256 -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_to_raw_mem_response_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Controller(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [63 : 0] slave_rdata; - wire [7 : 0] status; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // inlined wires - reg [353 : 0] f_raw_mem_reqs_rv$port1__write_1; - wire [353 : 0] f_raw_mem_reqs_rv$port1__read, - f_raw_mem_reqs_rv$port2__read, - f_raw_mem_reqs_rv$port3__read; - wire [256 : 0] f_raw_mem_rsps_rv$port1__read, - f_raw_mem_rsps_rv$port1__write_1, - f_raw_mem_rsps_rv$port2__read, - f_raw_mem_rsps_rv$port3__read; - wire [170 : 0] f_reqs_rv$port1__read, - f_reqs_rv$port1__write_1, - f_reqs_rv$port2__read; - wire f_raw_mem_reqs_rv$EN_port1__write, - f_reqs_rv$EN_port0__write, - f_reqs_rv$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register f_raw_mem_reqs_rv - reg [353 : 0] f_raw_mem_reqs_rv; - wire [353 : 0] f_raw_mem_reqs_rv$D_IN; - wire f_raw_mem_reqs_rv$EN; - - // register f_raw_mem_rsps_rv - reg [256 : 0] f_raw_mem_rsps_rv; - wire [256 : 0] f_raw_mem_rsps_rv$D_IN; - wire f_raw_mem_rsps_rv$EN; - - // register f_reqs_rv - reg [170 : 0] f_reqs_rv; - wire [170 : 0] f_reqs_rv$D_IN; - wire f_reqs_rv$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_cached_clean - reg rg_cached_clean; - wire rg_cached_clean$D_IN, rg_cached_clean$EN; - - // register rg_cached_raw_mem_addr - reg [63 : 0] rg_cached_raw_mem_addr; - wire [63 : 0] rg_cached_raw_mem_addr$D_IN; - wire rg_cached_raw_mem_addr$EN; - - // register rg_cached_raw_mem_word - reg [255 : 0] rg_cached_raw_mem_word; - wire [255 : 0] rg_cached_raw_mem_word$D_IN; - wire rg_cached_raw_mem_word$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_status - reg [7 : 0] rg_status; - wire [7 : 0] rg_status$D_IN; - wire rg_status$EN; - - // register rg_tohost_addr - reg [63 : 0] rg_tohost_addr; - wire [63 : 0] rg_tohost_addr$D_IN; - wire rg_tohost_addr$EN; - - // register rg_watch_tohost - reg rg_watch_tohost; - wire rg_watch_tohost$D_IN, rg_watch_tohost$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_external_reset, - CAN_FIRE_RL_rl_invalid_rd_address, - CAN_FIRE_RL_rl_invalid_wr_address, - CAN_FIRE_RL_rl_merge_rd_req, - CAN_FIRE_RL_rl_merge_wr_req, - CAN_FIRE_RL_rl_miss_clean_req, - CAN_FIRE_RL_rl_power_on_reset, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reload, - CAN_FIRE_RL_rl_reset_reload_cache, - CAN_FIRE_RL_rl_writeback_dirty, - CAN_FIRE_RL_rl_writeback_dirty_idle, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_external_reset, - WILL_FIRE_RL_rl_invalid_rd_address, - WILL_FIRE_RL_rl_invalid_wr_address, - WILL_FIRE_RL_rl_merge_rd_req, - WILL_FIRE_RL_rl_merge_wr_req, - WILL_FIRE_RL_rl_miss_clean_req, - WILL_FIRE_RL_rl_power_on_reset, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reload, - WILL_FIRE_RL_rl_reset_reload_cache, - WILL_FIRE_RL_rl_writeback_dirty, - WILL_FIRE_RL_rl_writeback_dirty_idle, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire [353 : 0] MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1, - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - wire [255 : 0] MUX_rg_cached_raw_mem_word$write_1__VAL_1; - wire [170 : 0] MUX_f_reqs_rv$port1__write_1__VAL_1, - MUX_f_reqs_rv$port1__write_1__VAL_2; - wire [70 : 0] MUX_slave_xactor_f_rd_data$enq_1__VAL_1, - MUX_slave_xactor_f_rd_data$enq_1__VAL_2; - wire [5 : 0] MUX_slave_xactor_f_wr_resp$enq_1__VAL_1, - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2; - wire MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2538; - reg [31 : 0] v__h3481; - reg [31 : 0] v__h3974; - reg [31 : 0] v__h4443; - reg [31 : 0] v__h4706; - reg [31 : 0] v__h5425; - reg [31 : 0] v__h7622; - reg [31 : 0] v__h7823; - reg [31 : 0] v__h8335; - reg [31 : 0] v__h9119; - reg [31 : 0] v__h9714; - reg [31 : 0] v__h2853; - reg [31 : 0] v__h3193; - reg [31 : 0] v__h1743; - reg [31 : 0] v__h2088; - reg [31 : 0] v__h1737; - reg [31 : 0] v__h2082; - reg [31 : 0] v__h2532; - reg [31 : 0] v__h2847; - reg [31 : 0] v__h3187; - reg [31 : 0] v__h3475; - reg [31 : 0] v__h3968; - reg [31 : 0] v__h4437; - reg [31 : 0] v__h4700; - reg [31 : 0] v__h5419; - reg [31 : 0] v__h7616; - reg [31 : 0] v__h7817; - reg [31 : 0] v__h8329; - reg [31 : 0] v__h9113; - reg [31 : 0] v__h9708; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rdata__h5068, word64_old__h5862; - wire [63 : 0] exit_value__h7860, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1, - mask__h5867, - req_raw_mem_addr__h3314, - updated_word64__h5868, - x__h6241, - y__h6242, - y__h6243; - wire [7 : 0] SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191; - wire [4 : 0] n__h5067; - wire NOT_cfg_verbosity_read_ULE_1___d5, - NOT_cfg_verbosity_read_ULE_2_2___d33, - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279, - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128, - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123, - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126, - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135, - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284, - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131, - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = rg_state == 2'd3 ; - assign CAN_FIRE_set_addr_map = rg_state == 2'd3 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = f_raw_mem_reqs_rv[352:0] ; - assign RDY_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign CAN_FIRE_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = !f_raw_mem_rsps_rv$port1__read[256] ; - assign CAN_FIRE_to_raw_mem_response_put = - !f_raw_mem_rsps_rv$port1__read[256] ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // value method status - assign status = rg_status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset_reload_cache - assign CAN_FIRE_RL_rl_reset_reload_cache = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_reset_reload_cache = - CAN_FIRE_RL_rl_reset_reload_cache ; - - // rule RL_rl_writeback_dirty_idle - assign CAN_FIRE_RL_rl_writeback_dirty_idle = - !f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd3 && - !f_reqs_rv[170] && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty_idle = - CAN_FIRE_RL_rl_writeback_dirty_idle ; - - // rule RL_rl_writeback_dirty - assign CAN_FIRE_RL_rl_writeback_dirty = - !f_raw_mem_reqs_rv$port1__read[353] && f_reqs_rv[170] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !rg_cached_clean ; - assign WILL_FIRE_RL_rl_writeback_dirty = CAN_FIRE_RL_rl_writeback_dirty ; - - // rule RL_rl_miss_clean_req - assign CAN_FIRE_RL_rl_miss_clean_req = - f_reqs_rv[170] && !f_raw_mem_reqs_rv$port1__read[353] && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - !rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - rg_cached_clean ; - assign WILL_FIRE_RL_rl_miss_clean_req = - CAN_FIRE_RL_rl_miss_clean_req && - !WILL_FIRE_RL_rl_external_reset && - !EN_set_addr_map ; - - // rule RL_rl_reload - assign CAN_FIRE_RL_rl_reload = f_raw_mem_rsps_rv[256] && rg_state == 2'd2 ; - assign WILL_FIRE_RL_rl_reload = CAN_FIRE_RL_rl_reload ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 && - rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_invalid_rd_address - assign CAN_FIRE_RL_rl_invalid_rd_address = - f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - !f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_rd_address = - CAN_FIRE_RL_rl_invalid_rd_address ; - - // rule RL_rl_invalid_wr_address - assign CAN_FIRE_RL_rl_invalid_wr_address = - f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N && - rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 && - f_reqs_rv[169] ; - assign WILL_FIRE_RL_rl_invalid_wr_address = - CAN_FIRE_RL_rl_invalid_wr_address ; - - // rule RL_rl_merge_rd_req - assign CAN_FIRE_RL_rl_merge_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && !f_reqs_rv$port1__read[170] ; - assign WILL_FIRE_RL_rl_merge_rd_req = CAN_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_merge_wr_req - assign CAN_FIRE_RL_rl_merge_wr_req = - !f_reqs_rv$port1__read[170] && slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N ; - assign WILL_FIRE_RL_rl_merge_wr_req = - CAN_FIRE_RL_rl_merge_wr_req && !WILL_FIRE_RL_rl_merge_rd_req ; - - // rule RL_rl_power_on_reset - assign CAN_FIRE_RL_rl_power_on_reset = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_power_on_reset = CAN_FIRE_RL_rl_power_on_reset ; - - // rule RL_rl_external_reset - assign CAN_FIRE_RL_rl_external_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && rg_state == 2'd3 ; - assign WILL_FIRE_RL_rl_external_reset = CAN_FIRE_RL_rl_external_reset ; - - // inputs to muxes for submodule ports - assign MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - assign MUX_rg_state$write_1__SEL_1 = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - assign MUX_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 = - { 34'h3FFFFFFFF, - rg_cached_raw_mem_addr, - rg_cached_raw_mem_word } ; - assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3 = - { 34'h2FFFFFFFF, - req_raw_mem_addr__h3314, - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_1 = - { 2'd2, slave_xactor_f_rd_addr$D_OUT, 72'hAAAAAAAAAAAAAAAAAA } ; - assign MUX_f_reqs_rv$port1__write_1__VAL_2 = - { 2'd3, - slave_xactor_f_wr_addr$D_OUT, - slave_xactor_f_wr_data$D_OUT[8:1], - slave_xactor_f_wr_data$D_OUT[72:9] } ; - assign MUX_rg_cached_raw_mem_word$write_1__VAL_1 = - { (f_reqs_rv[105:104] == 2'd3) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[255:192], - (f_reqs_rv[105:104] == 2'd2) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[191:128], - (f_reqs_rv[105:104] == 2'd1) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[127:64], - (f_reqs_rv[105:104] == 2'd0) ? - updated_word64__h5868 : - rg_cached_raw_mem_word[63:0] } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_1 = - { f_reqs_rv[168:165], rdata__h5068, 3'd1 } ; - assign MUX_slave_xactor_f_rd_data$enq_1__VAL_2 = - { f_reqs_rv[168:101], 3'd5 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 = - { f_reqs_rv[168:165], 2'd0 } ; - assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 = - { f_reqs_rv[168:165], 2'd2 } ; - - // inlined wires - assign f_reqs_rv$EN_port0__write = - WILL_FIRE_RL_rl_invalid_wr_address || - WILL_FIRE_RL_rl_invalid_rd_address || - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs_rv$port1__read = - f_reqs_rv$EN_port0__write ? - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_reqs_rv ; - assign f_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_merge_rd_req || WILL_FIRE_RL_rl_merge_wr_req ; - assign f_reqs_rv$port1__write_1 = - WILL_FIRE_RL_rl_merge_rd_req ? - MUX_f_reqs_rv$port1__write_1__VAL_1 : - MUX_f_reqs_rv$port1__write_1__VAL_2 ; - assign f_reqs_rv$port2__read = - f_reqs_rv$EN_port1__write ? - f_reqs_rv$port1__write_1 : - f_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port1__read = - EN_to_raw_mem_request_get ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv ; - assign f_raw_mem_reqs_rv$EN_port1__write = - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_miss_clean_req ; - always@(MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 or - WILL_FIRE_RL_rl_reset_reload_cache or - WILL_FIRE_RL_rl_miss_clean_req or - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1; - WILL_FIRE_RL_rl_reset_reload_cache: - f_raw_mem_reqs_rv$port1__write_1 = - 354'h2FFFFFFFF0000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_rl_miss_clean_req: - f_raw_mem_reqs_rv$port1__write_1 = - MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3; - default: f_raw_mem_reqs_rv$port1__write_1 = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign f_raw_mem_reqs_rv$port2__read = - f_raw_mem_reqs_rv$EN_port1__write ? - f_raw_mem_reqs_rv$port1__write_1 : - f_raw_mem_reqs_rv$port1__read ; - assign f_raw_mem_reqs_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_reqs_rv$port2__read ; - assign f_raw_mem_rsps_rv$port1__read = - CAN_FIRE_RL_rl_reload ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv ; - assign f_raw_mem_rsps_rv$port1__write_1 = - { 1'd1, to_raw_mem_response_put } ; - assign f_raw_mem_rsps_rv$port2__read = - EN_to_raw_mem_response_put ? - f_raw_mem_rsps_rv$port1__write_1 : - f_raw_mem_rsps_rv$port1__read ; - assign f_raw_mem_rsps_rv$port3__read = - MUX_rg_state$write_1__SEL_1 ? - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - f_raw_mem_rsps_rv$port2__read ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register f_raw_mem_reqs_rv - assign f_raw_mem_reqs_rv$D_IN = f_raw_mem_reqs_rv$port3__read ; - assign f_raw_mem_reqs_rv$EN = 1'b1 ; - - // register f_raw_mem_rsps_rv - assign f_raw_mem_rsps_rv$D_IN = f_raw_mem_rsps_rv$port3__read ; - assign f_raw_mem_rsps_rv$EN = 1'b1 ; - - // register f_reqs_rv - assign f_reqs_rv$D_IN = f_reqs_rv$port2__read ; - assign f_reqs_rv$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_cached_clean - assign rg_cached_clean$D_IN = !WILL_FIRE_RL_rl_process_wr_req ; - assign rg_cached_clean$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload || - WILL_FIRE_RL_rl_writeback_dirty || - WILL_FIRE_RL_rl_writeback_dirty_idle ; - - // register rg_cached_raw_mem_addr - assign rg_cached_raw_mem_addr$D_IN = - WILL_FIRE_RL_rl_miss_clean_req ? - req_raw_mem_addr__h3314 : - 64'd0 ; - assign rg_cached_raw_mem_addr$EN = MUX_rg_state$write_1__SEL_2 ; - - // register rg_cached_raw_mem_word - assign rg_cached_raw_mem_word$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_rg_cached_raw_mem_word$write_1__VAL_1 : - f_raw_mem_rsps_rv[255:0] ; - assign rg_cached_raw_mem_word$EN = - WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload ; - - // register rg_state - always@(MUX_rg_state$write_1__SEL_1 or - MUX_rg_state$write_1__SEL_2 or WILL_FIRE_RL_rl_reload) - begin - case (1'b1) // synopsys parallel_case - MUX_rg_state$write_1__SEL_1: rg_state$D_IN = 2'd1; - MUX_rg_state$write_1__SEL_2: rg_state$D_IN = 2'd2; - WILL_FIRE_RL_rl_reload: rg_state$D_IN = 2'd3; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset || - WILL_FIRE_RL_rl_miss_clean_req || - WILL_FIRE_RL_rl_reset_reload_cache || - WILL_FIRE_RL_rl_reload ; - - // register rg_status - assign rg_status$D_IN = - (WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset) ? - 8'd0 : - 8'd1 ; - assign rg_status$EN = - WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 || - WILL_FIRE_RL_rl_external_reset || - WILL_FIRE_RL_rl_power_on_reset ; - - // register rg_tohost_addr - assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ; - assign rg_tohost_addr$EN = EN_set_watch_tohost ; - - // register rg_watch_tohost - assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ; - assign rg_watch_tohost$EN = EN_set_watch_tohost ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_external_reset ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_merge_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_slave_xactor_f_rd_data$enq_1__VAL_1 : - MUX_slave_xactor_f_rd_data$enq_1__VAL_2 ; - assign slave_xactor_f_rd_data$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_invalid_rd_address ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_merge_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_1 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - WILL_FIRE_RL_rl_process_wr_req ? - MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 : - MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 ; - assign slave_xactor_f_wr_resp$ENQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_invalid_wr_address ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_1 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d5 = cfg_verbosity > 4'd1 ; - assign NOT_cfg_verbosity_read_ULE_2_2___d33 = cfg_verbosity > 4'd2 ; - assign NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 = - f_reqs_rv[92:90] != 3'b0 && - (f_reqs_rv[92:90] != 3'b001 || f_reqs_rv[101]) && - (f_reqs_rv[92:90] != 3'b010 || f_reqs_rv[102:101] != 2'h0) && - (f_reqs_rv[92:90] != 3'b011 || f_reqs_rv[103:101] != 3'h0) && - (f_reqs_rv[92:90] != 3'b100 || f_reqs_rv[104:101] != 4'h0) && - (f_reqs_rv[92:90] != 3'b101 || f_reqs_rv[105:101] != 5'h0) && - (f_reqs_rv[92:90] != 3'b110 || f_reqs_rv[106:101] != 6'h0) && - (f_reqs_rv[92:90] != 3'b111 || f_reqs_rv[107:101] != 7'h0) ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 = {8{f_reqs_rv[64]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212 = {8{f_reqs_rv[65]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208 = {8{f_reqs_rv[66]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205 = {8{f_reqs_rv[67]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201 = {8{f_reqs_rv[68]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198 = {8{f_reqs_rv[69]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194 = {8{f_reqs_rv[70]}} ; - assign SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191 = {8{f_reqs_rv[71]}} ; - assign exit_value__h7860 = { 1'd0, f_reqs_rv[63:1] } ; - assign f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1 = - f_reqs_rv[164:101] - rg_addr_base ; - assign f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 = - f_reqs_rv[164:101] < rg_addr_lim ; - assign f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 = - f_reqs_rv[92:90] == 3'b0 || - f_reqs_rv[92:90] == 3'b001 && !f_reqs_rv[101] || - f_reqs_rv[92:90] == 3'b010 && f_reqs_rv[102:101] == 2'h0 || - f_reqs_rv[92:90] == 3'b011 && f_reqs_rv[103:101] == 3'h0 || - f_reqs_rv[92:90] == 3'b100 && f_reqs_rv[104:101] == 4'h0 || - f_reqs_rv[92:90] == 3'b101 && f_reqs_rv[105:101] == 5'h0 || - f_reqs_rv[92:90] == 3'b110 && f_reqs_rv[106:101] == 6'h0 || - f_reqs_rv[92:90] == 3'b111 && f_reqs_rv[107:101] == 7'h0 ; - assign mask__h5867 = - { SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - assign n__h5067 = { 3'd0, f_reqs_rv[105:104] } ; - assign req_raw_mem_addr__h3314 = - { 5'd0, - f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1[63:5] } ; - assign rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 = - rg_addr_base <= f_reqs_rv[164:101] ; - assign rg_cached_raw_mem_addr_1_EQ_0_CONCAT_f_reqs_rv_ETC___d135 = - rg_cached_raw_mem_addr == req_raw_mem_addr__h3314 ; - assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d284 = - rg_state == 2'd3 && - (NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279 || - !rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 || - !f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128) ; - assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__3_B_ETC___d131 = - rg_state == 2'd3 && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123 && - rg_addr_base_24_ULE_f_reqs_rv_port0__read__3_B_ETC___d126 && - f_reqs_rv_port0__read__3_BITS_164_TO_101_25_UL_ETC___d128 ; - assign rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 = - rg_watch_tohost && f_reqs_rv[164:101] == rg_tohost_addr && - f_reqs_rv[63:0] != 64'd0 ; - assign updated_word64__h5868 = x__h6241 | y__h6242 ; - assign x__h6241 = word64_old__h5862 & y__h6243 ; - assign y__h6242 = f_reqs_rv[63:0] & mask__h5867 ; - assign y__h6243 = - { ~SEXT_f_reqs_rv_port0__read__3_BIT_71_90___d191, - ~SEXT_f_reqs_rv_port0__read__3_BIT_70_93___d194, - ~SEXT_f_reqs_rv_port0__read__3_BIT_69_97___d198, - ~SEXT_f_reqs_rv_port0__read__3_BIT_68_00___d201, - ~SEXT_f_reqs_rv_port0__read__3_BIT_67_04___d205, - ~SEXT_f_reqs_rv_port0__read__3_BIT_66_07___d208, - ~SEXT_f_reqs_rv_port0__read__3_BIT_65_11___d212, - ~SEXT_f_reqs_rv_port0__read__3_BIT_64_14___d215 } ; - always@(f_reqs_rv or rg_cached_raw_mem_word) - begin - case (f_reqs_rv[105:104]) - 2'd0: word64_old__h5862 = rg_cached_raw_mem_word[63:0]; - 2'd1: word64_old__h5862 = rg_cached_raw_mem_word[127:64]; - 2'd2: word64_old__h5862 = rg_cached_raw_mem_word[191:128]; - 2'd3: word64_old__h5862 = rg_cached_raw_mem_word[255:192]; - endcase - end - always@(n__h5067 or rg_cached_raw_mem_word) - begin - case (n__h5067) - 5'd0: rdata__h5068 = rg_cached_raw_mem_word[63:0]; - 5'd1: rdata__h5068 = rg_cached_raw_mem_word[127:64]; - 5'd2: rdata__h5068 = rg_cached_raw_mem_word[191:128]; - 5'd3: rdata__h5068 = rg_cached_raw_mem_word[255:192]; - default: rdata__h5068 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv <= `BSV_ASSIGNMENT_DELAY - 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - rg_status <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000; - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (f_raw_mem_reqs_rv$EN) - f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_reqs_rv$D_IN; - if (f_raw_mem_rsps_rv$EN) - f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_rsps_rv$D_IN; - if (f_reqs_rv$EN) f_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_reqs_rv$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_status$EN) rg_status <= `BSV_ASSIGNMENT_DELAY rg_status$D_IN; - if (rg_tohost_addr$EN) - rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN; - if (rg_watch_tohost$EN) - rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_cached_clean$EN) - rg_cached_clean <= `BSV_ASSIGNMENT_DELAY rg_cached_clean$D_IN; - if (rg_cached_raw_mem_addr$EN) - rg_cached_raw_mem_addr <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_addr$D_IN; - if (rg_cached_raw_mem_word$EN) - rg_cached_raw_mem_word <= `BSV_ASSIGNMENT_DELAY - rg_cached_raw_mem_word$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - f_raw_mem_reqs_rv = - 354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_raw_mem_rsps_rv = - 257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - f_reqs_rv = 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_cached_clean = 1'h0; - rg_cached_raw_mem_addr = 64'hAAAAAAAAAAAAAAAA; - rg_cached_raw_mem_word = - 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - rg_state = 2'h2; - rg_status = 8'hAA; - rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA; - rg_watch_tohost = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2538 = $stime; - #0; - end - v__h2532 = v__h2538 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_reload_cache && - NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING", - v__h2532); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3481 = $stime; - #0; - end - v__h3475 = v__h3481 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty_idle && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h", - v__h3475, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3974 = $stime; - #0; - end - v__h3968 = v__h3974 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_writeback_dirty && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h", - v__h3968, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4443 = $stime; - #0; - end - v__h4437 = v__h4443 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_miss_clean_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h", - v__h4437, - req_raw_mem_addr__h3314); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_reload: raw addr 0x%0h", - v__h4700, - rg_cached_raw_mem_addr); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", f_raw_mem_rsps_rv[255:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h5425 = $stime; - #0; - end - v__h5419 = v__h5425 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5419); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", rdata__h5068); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h7622 = $stime; - #0; - end - v__h7616 = v__h7622 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7616); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 2'b0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - begin - v__h7823 = $stime; - #0; - end - v__h7817 = v__h7823 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243) - $display("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h () data 0x%0h", - v__h7817, - f_reqs_rv[164:101], - f_reqs_rv[63:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] == 63'd0) - $display("PASS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - rg_watch_tohost_37_AND_f_reqs_rv_port0__read___ETC___d243 && - f_reqs_rv[63:1] != 63'd0) - $display("FAIL %0d", exit_value__h7860); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - begin - v__h8335 = $stime; - #0; - end - v__h8329 = v__h8335 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("%0d: ERROR: Mem_Controller:", v__h8329); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" read-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" read-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("REQ_OP_RD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - begin - v__h9119 = $stime; - #0; - end - v__h9113 = v__h9119 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("%0d: ERROR: Mem_Controller:", v__h9113); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - NOT_f_reqs_rv_port0__read__3_BITS_92_TO_90_7_E_ETC___d279) - $display(" write-addr is misaligned"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address && - f_reqs_rv_port0__read__3_BITS_92_TO_90_7_EQ_0b_ETC___d123) - $display(" write-addr is out of bounds"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h", - rg_addr_base, - rg_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("Req { ", "req_op: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("REQ_OP_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "id: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[164:101]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "len: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[100:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "size: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[92:90]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "burst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[89:88]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "lock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", f_reqs_rv[87]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "cache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[86:83]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "prot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[82:80]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "qos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[79:76]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "region: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[75:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "user: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[71:64]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "data: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[63:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" => "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) - $write("'h%h", f_reqs_rv[168:165]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 2'b10); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - begin - v__h9714 = $stime; - #0; - end - v__h9708 = v__h9714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map) - $display("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9708, - set_addr_map_addr_base, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h2853 = $stime; - #0; - end - v__h2847 = v__h2853 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_rd_req", v__h2847); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_rd_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - begin - v__h3193 = $stime; - #0; - end - v__h3187 = v__h3193 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $display("%0d: Mem_Controller.rl_merge_wr_req", v__h3187); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_merge_wr_req && - NOT_cfg_verbosity_read_ULE_2_2___d33) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h1743 = $stime; - #0; - end - v__h1737 = v__h1743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_power_on_reset", v__h1737); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - begin - v__h2088 = $stime; - #0; - end - v__h2082 = v__h2088 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5) - $display("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE", - v__h2082); - end - // synopsys translate_on -endmodule // mkMem_Controller - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v deleted file mode 100644 index 104c51b0..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkMem_Model.v +++ /dev/null @@ -1,192 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_mem_server_request_put O 1 reg -// mem_server_response_get O 256 reg -// RDY_mem_server_response_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// mem_server_request_put I 353 -// EN_mem_server_request_put I 1 -// EN_mem_server_response_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkMem_Model(CLK, - RST_N, - - mem_server_request_put, - EN_mem_server_request_put, - RDY_mem_server_request_put, - - EN_mem_server_response_get, - mem_server_response_get, - RDY_mem_server_response_get); - input CLK; - input RST_N; - - // action method mem_server_request_put - input [352 : 0] mem_server_request_put; - input EN_mem_server_request_put; - output RDY_mem_server_request_put; - - // actionvalue method mem_server_response_get - input EN_mem_server_response_get; - output [255 : 0] mem_server_response_get; - output RDY_mem_server_response_get; - - // signals for module outputs - wire [255 : 0] mem_server_response_get; - wire RDY_mem_server_request_put, RDY_mem_server_response_get; - - // ports of submodule f_raw_mem_rsps - wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT; - wire f_raw_mem_rsps$CLR, - f_raw_mem_rsps$DEQ, - f_raw_mem_rsps$EMPTY_N, - f_raw_mem_rsps$ENQ, - f_raw_mem_rsps$FULL_N; - - // ports of submodule rf - wire [255 : 0] rf$D_IN, rf$D_OUT_1; - wire [63 : 0] rf$ADDR_1, - rf$ADDR_2, - rf$ADDR_3, - rf$ADDR_4, - rf$ADDR_5, - rf$ADDR_IN; - wire rf$WE; - - // rule scheduling signals - wire CAN_FIRE_mem_server_request_put, - CAN_FIRE_mem_server_response_get, - WILL_FIRE_mem_server_request_put, - WILL_FIRE_mem_server_response_get; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h371; - reg [31 : 0] v__h365; - // synopsys translate_on - - // remaining internal signals - wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2; - - // action method mem_server_request_put - assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ; - assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ; - - // actionvalue method mem_server_response_get - assign mem_server_response_get = f_raw_mem_rsps$D_OUT ; - assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ; - assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ; - - // submodule f_raw_mem_rsps - FIFO2 #(.width(32'd256), .guarded(32'd1)) f_raw_mem_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_raw_mem_rsps$D_IN), - .ENQ(f_raw_mem_rsps$ENQ), - .DEQ(f_raw_mem_rsps$DEQ), - .CLR(f_raw_mem_rsps$CLR), - .D_OUT(f_raw_mem_rsps$D_OUT), - .FULL_N(f_raw_mem_rsps$FULL_N), - .EMPTY_N(f_raw_mem_rsps$EMPTY_N)); - - // submodule rf - RegFileLoad #(.file("Mem.hex"), - .addr_width(32'd64), - .data_width(32'd256), - .lo(64'd0), - .hi(64'd8388607), - .binary(1'd0)) rf(.CLK(CLK), - .ADDR_1(rf$ADDR_1), - .ADDR_2(rf$ADDR_2), - .ADDR_3(rf$ADDR_3), - .ADDR_4(rf$ADDR_4), - .ADDR_5(rf$ADDR_5), - .ADDR_IN(rf$ADDR_IN), - .D_IN(rf$D_IN), - .WE(rf$WE), - .D_OUT_1(rf$D_OUT_1), - .D_OUT_2(), - .D_OUT_3(), - .D_OUT_4(), - .D_OUT_5()); - - // submodule f_raw_mem_rsps - assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ; - assign f_raw_mem_rsps$ENQ = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - !mem_server_request_put[352] ; - assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ; - assign f_raw_mem_rsps$CLR = 1'b0 ; - - // submodule rf - assign rf$ADDR_1 = mem_server_request_put[319:256] ; - assign rf$ADDR_2 = 64'h0 ; - assign rf$ADDR_3 = 64'h0 ; - assign rf$ADDR_4 = 64'h0 ; - assign rf$ADDR_5 = 64'h0 ; - assign rf$ADDR_IN = mem_server_request_put[319:256] ; - assign rf$D_IN = mem_server_request_put[255:0] ; - assign rf$WE = - EN_mem_server_request_put && - mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 && - mem_server_request_put[352] ; - - // remaining internal signals - assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 = - mem_server_request_put[319:256] < 64'h0000000000800000 ; - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - begin - v__h371 = $stime; - #0; - end - v__h365 = v__h371 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)", - v__h365, - mem_server_request_put[319:256], - 64'h0000000000800000); - if (RST_N != `BSV_RESET_VALUE) - if (EN_mem_server_request_put && - !mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkMem_Model - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v deleted file mode 100644 index 5e2773cc..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem.v +++ /dev/null @@ -1,1654 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 -// RDY_server_reset_response_get O 1 reg -// imem_valid O 1 -// imem_is_i32_not_i16 O 1 const -// imem_pc O 64 reg -// imem_instr O 32 -// imem_exc O 1 -// imem_exc_code O 4 reg -// imem_tval O 64 reg -// imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg -// imem_master_wvalid O 1 -// imem_master_wid O 4 reg -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg -// imem_master_bready O 1 -// imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg -// imem_master_rready O 1 -// dmem_valid O 1 -// dmem_word64 O 64 -// dmem_st_amo_val O 64 -// dmem_exc O 1 -// dmem_exc_code O 4 reg -// dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg -// dmem_master_wvalid O 1 -// dmem_master_wid O 4 reg -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg -// dmem_master_bready O 1 -// dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg -// dmem_master_rready O 1 -// RDY_server_fence_i_request_put O 1 -// RDY_server_fence_i_response_get O 1 -// RDY_server_fence_request_put O 1 reg -// RDY_server_fence_response_get O 1 -// RDY_sfence_vma O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// imem_req_f3 I 3 -// imem_req_addr I 64 -// imem_req_priv I 2 unused -// imem_req_sstatus_SUM I 1 unused -// imem_req_mstatus_MXR I 1 unused -// imem_req_satp I 64 unused -// imem_master_awready I 1 -// imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg -// imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg -// dmem_req_op I 2 -// dmem_req_f3 I 3 -// dmem_req_amo_funct7 I 7 reg -// dmem_req_addr I 64 -// dmem_req_store_value I 64 -// dmem_req_priv I 2 unused -// dmem_req_sstatus_SUM I 1 unused -// dmem_req_mstatus_MXR I 1 unused -// dmem_req_satp I 64 unused -// dmem_master_awready I 1 -// dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg -// dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg -// server_fence_request_put I 8 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_imem_req I 1 -// EN_dmem_req I 1 -// EN_server_fence_i_request_put I 1 -// EN_server_fence_i_response_get I 1 -// EN_server_fence_request_put I 1 -// EN_server_fence_response_get I 1 -// EN_sfence_vma I 1 unused -// -// Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_valid -// (imem_master_awready, imem_master_wready) -> imem_instr -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, imem_master_wready, EN_imem_req) -> imem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_valid -// (dmem_master_awready, dmem_master_wready) -> dmem_word64 -// (dmem_master_awready, dmem_master_wready) -> dmem_st_amo_val -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// (dmem_master_awready, dmem_master_wready, EN_dmem_req) -> dmem_master_rready -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - imem_req_f3, - imem_req_addr, - imem_req_priv, - imem_req_sstatus_SUM, - imem_req_mstatus_MXR, - imem_req_satp, - EN_imem_req, - - imem_valid, - - imem_is_i32_not_i16, - - imem_pc, - - imem_instr, - - imem_exc, - - imem_exc_code, - - imem_tval, - - imem_master_awvalid, - - imem_master_awid, - - imem_master_awaddr, - - imem_master_awlen, - - imem_master_awsize, - - imem_master_awburst, - - imem_master_awlock, - - imem_master_awcache, - - imem_master_awprot, - - imem_master_awqos, - - imem_master_awregion, - - imem_master_awready, - - imem_master_wvalid, - - imem_master_wid, - - imem_master_wdata, - - imem_master_wstrb, - - imem_master_wlast, - - imem_master_wready, - - imem_master_bvalid, - imem_master_bid, - imem_master_bresp, - - imem_master_bready, - - imem_master_arvalid, - - imem_master_arid, - - imem_master_araddr, - - imem_master_arlen, - - imem_master_arsize, - - imem_master_arburst, - - imem_master_arlock, - - imem_master_arcache, - - imem_master_arprot, - - imem_master_arqos, - - imem_master_arregion, - - imem_master_arready, - - imem_master_rvalid, - imem_master_rid, - imem_master_rdata, - imem_master_rresp, - imem_master_rlast, - - imem_master_rready, - - dmem_req_op, - dmem_req_f3, - dmem_req_amo_funct7, - dmem_req_addr, - dmem_req_store_value, - dmem_req_priv, - dmem_req_sstatus_SUM, - dmem_req_mstatus_MXR, - dmem_req_satp, - EN_dmem_req, - - dmem_valid, - - dmem_word64, - - dmem_st_amo_val, - - dmem_exc, - - dmem_exc_code, - - dmem_master_awvalid, - - dmem_master_awid, - - dmem_master_awaddr, - - dmem_master_awlen, - - dmem_master_awsize, - - dmem_master_awburst, - - dmem_master_awlock, - - dmem_master_awcache, - - dmem_master_awprot, - - dmem_master_awqos, - - dmem_master_awregion, - - dmem_master_awready, - - dmem_master_wvalid, - - dmem_master_wid, - - dmem_master_wdata, - - dmem_master_wstrb, - - dmem_master_wlast, - - dmem_master_wready, - - dmem_master_bvalid, - dmem_master_bid, - dmem_master_bresp, - - dmem_master_bready, - - dmem_master_arvalid, - - dmem_master_arid, - - dmem_master_araddr, - - dmem_master_arlen, - - dmem_master_arsize, - - dmem_master_arburst, - - dmem_master_arlock, - - dmem_master_arcache, - - dmem_master_arprot, - - dmem_master_arqos, - - dmem_master_arregion, - - dmem_master_arready, - - dmem_master_rvalid, - dmem_master_rid, - dmem_master_rdata, - dmem_master_rresp, - dmem_master_rlast, - - dmem_master_rready, - - EN_server_fence_i_request_put, - RDY_server_fence_i_request_put, - - EN_server_fence_i_response_get, - RDY_server_fence_i_response_get, - - server_fence_request_put, - EN_server_fence_request_put, - RDY_server_fence_request_put, - - EN_server_fence_response_get, - RDY_server_fence_response_get, - - EN_sfence_vma, - RDY_sfence_vma); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method imem_req - input [2 : 0] imem_req_f3; - input [63 : 0] imem_req_addr; - input [1 : 0] imem_req_priv; - input imem_req_sstatus_SUM; - input imem_req_mstatus_MXR; - input [63 : 0] imem_req_satp; - input EN_imem_req; - - // value method imem_valid - output imem_valid; - - // value method imem_is_i32_not_i16 - output imem_is_i32_not_i16; - - // value method imem_pc - output [63 : 0] imem_pc; - - // value method imem_instr - output [31 : 0] imem_instr; - - // value method imem_exc - output imem_exc; - - // value method imem_exc_code - output [3 : 0] imem_exc_code; - - // value method imem_tval - output [63 : 0] imem_tval; - - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; - - // value method imem_master_m_awaddr - output [63 : 0] imem_master_awaddr; - - // value method imem_master_m_awlen - output [7 : 0] imem_master_awlen; - - // value method imem_master_m_awsize - output [2 : 0] imem_master_awsize; - - // value method imem_master_m_awburst - output [1 : 0] imem_master_awburst; - - // value method imem_master_m_awlock - output imem_master_awlock; - - // value method imem_master_m_awcache - output [3 : 0] imem_master_awcache; - - // value method imem_master_m_awprot - output [2 : 0] imem_master_awprot; - - // value method imem_master_m_awqos - output [3 : 0] imem_master_awqos; - - // value method imem_master_m_awregion - output [3 : 0] imem_master_awregion; - - // value method imem_master_m_awuser - - // action method imem_master_m_awready - input imem_master_awready; - - // value method imem_master_m_wvalid - output imem_master_wvalid; - - // value method imem_master_m_wid - output [3 : 0] imem_master_wid; - - // value method imem_master_m_wdata - output [63 : 0] imem_master_wdata; - - // value method imem_master_m_wstrb - output [7 : 0] imem_master_wstrb; - - // value method imem_master_m_wlast - output imem_master_wlast; - - // value method imem_master_m_wuser - - // action method imem_master_m_wready - input imem_master_wready; - - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; - input [1 : 0] imem_master_bresp; - - // value method imem_master_m_bready - output imem_master_bready; - - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; - - // value method imem_master_m_araddr - output [63 : 0] imem_master_araddr; - - // value method imem_master_m_arlen - output [7 : 0] imem_master_arlen; - - // value method imem_master_m_arsize - output [2 : 0] imem_master_arsize; - - // value method imem_master_m_arburst - output [1 : 0] imem_master_arburst; - - // value method imem_master_m_arlock - output imem_master_arlock; - - // value method imem_master_m_arcache - output [3 : 0] imem_master_arcache; - - // value method imem_master_m_arprot - output [2 : 0] imem_master_arprot; - - // value method imem_master_m_arqos - output [3 : 0] imem_master_arqos; - - // value method imem_master_m_arregion - output [3 : 0] imem_master_arregion; - - // value method imem_master_m_aruser - - // action method imem_master_m_arready - input imem_master_arready; - - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; - input [63 : 0] imem_master_rdata; - input [1 : 0] imem_master_rresp; - input imem_master_rlast; - - // value method imem_master_m_rready - output imem_master_rready; - - // action method dmem_req - input [1 : 0] dmem_req_op; - input [2 : 0] dmem_req_f3; - input [6 : 0] dmem_req_amo_funct7; - input [63 : 0] dmem_req_addr; - input [63 : 0] dmem_req_store_value; - input [1 : 0] dmem_req_priv; - input dmem_req_sstatus_SUM; - input dmem_req_mstatus_MXR; - input [63 : 0] dmem_req_satp; - input EN_dmem_req; - - // value method dmem_valid - output dmem_valid; - - // value method dmem_word64 - output [63 : 0] dmem_word64; - - // value method dmem_st_amo_val - output [63 : 0] dmem_st_amo_val; - - // value method dmem_exc - output dmem_exc; - - // value method dmem_exc_code - output [3 : 0] dmem_exc_code; - - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid - output [3 : 0] dmem_master_awid; - - // value method dmem_master_m_awaddr - output [63 : 0] dmem_master_awaddr; - - // value method dmem_master_m_awlen - output [7 : 0] dmem_master_awlen; - - // value method dmem_master_m_awsize - output [2 : 0] dmem_master_awsize; - - // value method dmem_master_m_awburst - output [1 : 0] dmem_master_awburst; - - // value method dmem_master_m_awlock - output dmem_master_awlock; - - // value method dmem_master_m_awcache - output [3 : 0] dmem_master_awcache; - - // value method dmem_master_m_awprot - output [2 : 0] dmem_master_awprot; - - // value method dmem_master_m_awqos - output [3 : 0] dmem_master_awqos; - - // value method dmem_master_m_awregion - output [3 : 0] dmem_master_awregion; - - // value method dmem_master_m_awuser - - // action method dmem_master_m_awready - input dmem_master_awready; - - // value method dmem_master_m_wvalid - output dmem_master_wvalid; - - // value method dmem_master_m_wid - output [3 : 0] dmem_master_wid; - - // value method dmem_master_m_wdata - output [63 : 0] dmem_master_wdata; - - // value method dmem_master_m_wstrb - output [7 : 0] dmem_master_wstrb; - - // value method dmem_master_m_wlast - output dmem_master_wlast; - - // value method dmem_master_m_wuser - - // action method dmem_master_m_wready - input dmem_master_wready; - - // action method dmem_master_m_bvalid - input dmem_master_bvalid; - input [3 : 0] dmem_master_bid; - input [1 : 0] dmem_master_bresp; - - // value method dmem_master_m_bready - output dmem_master_bready; - - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid - output [3 : 0] dmem_master_arid; - - // value method dmem_master_m_araddr - output [63 : 0] dmem_master_araddr; - - // value method dmem_master_m_arlen - output [7 : 0] dmem_master_arlen; - - // value method dmem_master_m_arsize - output [2 : 0] dmem_master_arsize; - - // value method dmem_master_m_arburst - output [1 : 0] dmem_master_arburst; - - // value method dmem_master_m_arlock - output dmem_master_arlock; - - // value method dmem_master_m_arcache - output [3 : 0] dmem_master_arcache; - - // value method dmem_master_m_arprot - output [2 : 0] dmem_master_arprot; - - // value method dmem_master_m_arqos - output [3 : 0] dmem_master_arqos; - - // value method dmem_master_m_arregion - output [3 : 0] dmem_master_arregion; - - // value method dmem_master_m_aruser - - // action method dmem_master_m_arready - input dmem_master_arready; - - // action method dmem_master_m_rvalid - input dmem_master_rvalid; - input [3 : 0] dmem_master_rid; - input [63 : 0] dmem_master_rdata; - input [1 : 0] dmem_master_rresp; - input dmem_master_rlast; - - // value method dmem_master_m_rready - output dmem_master_rready; - - // action method server_fence_i_request_put - input EN_server_fence_i_request_put; - output RDY_server_fence_i_request_put; - - // action method server_fence_i_response_get - input EN_server_fence_i_response_get; - output RDY_server_fence_i_response_get; - - // action method server_fence_request_put - input [7 : 0] server_fence_request_put; - input EN_server_fence_request_put; - output RDY_server_fence_request_put; - - // action method server_fence_response_get - input EN_server_fence_response_get; - output RDY_server_fence_response_get; - - // action method sfence_vma - input EN_sfence_vma; - output RDY_sfence_vma; - - // signals for module outputs - wire [63 : 0] dmem_master_araddr, - dmem_master_awaddr, - dmem_master_wdata, - dmem_st_amo_val, - dmem_word64, - imem_master_araddr, - imem_master_awaddr, - imem_master_wdata, - imem_pc, - imem_tval; - wire [31 : 0] imem_instr; - wire [7 : 0] dmem_master_arlen, - dmem_master_awlen, - dmem_master_wstrb, - imem_master_arlen, - imem_master_awlen, - imem_master_wstrb; - wire [3 : 0] dmem_exc_code, - dmem_master_arcache, - dmem_master_arid, - dmem_master_arqos, - dmem_master_arregion, - dmem_master_awcache, - dmem_master_awid, - dmem_master_awqos, - dmem_master_awregion, - dmem_master_wid, - imem_exc_code, - imem_master_arcache, - imem_master_arid, - imem_master_arqos, - imem_master_arregion, - imem_master_awcache, - imem_master_awid, - imem_master_awqos, - imem_master_awregion, - imem_master_wid; - wire [2 : 0] dmem_master_arprot, - dmem_master_arsize, - dmem_master_awprot, - dmem_master_awsize, - imem_master_arprot, - imem_master_arsize, - imem_master_awprot, - imem_master_awsize; - wire [1 : 0] dmem_master_arburst, - dmem_master_awburst, - imem_master_arburst, - imem_master_awburst; - wire RDY_server_fence_i_request_put, - RDY_server_fence_i_response_get, - RDY_server_fence_request_put, - RDY_server_fence_response_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_sfence_vma, - dmem_exc, - dmem_master_arlock, - dmem_master_arvalid, - dmem_master_awlock, - dmem_master_awvalid, - dmem_master_bready, - dmem_master_rready, - dmem_master_wlast, - dmem_master_wvalid, - dmem_valid, - imem_exc, - imem_is_i32_not_i16, - imem_master_arlock, - imem_master_arvalid, - imem_master_awlock, - imem_master_awvalid, - imem_master_bready, - imem_master_rready, - imem_master_wlast, - imem_master_wvalid, - imem_valid; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_state - reg [1 : 0] rg_state; - reg [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule dcache - wire [63 : 0] dcache$mem_master_araddr, - dcache$mem_master_awaddr, - dcache$mem_master_rdata, - dcache$mem_master_wdata, - dcache$req_addr, - dcache$req_satp, - dcache$req_st_value, - dcache$st_amo_val, - dcache$word64; - wire [7 : 0] dcache$mem_master_arlen, - dcache$mem_master_awlen, - dcache$mem_master_wstrb; - wire [6 : 0] dcache$req_amo_funct7; - wire [3 : 0] dcache$exc_code, - dcache$mem_master_arcache, - dcache$mem_master_arid, - dcache$mem_master_arqos, - dcache$mem_master_arregion, - dcache$mem_master_awcache, - dcache$mem_master_awid, - dcache$mem_master_awqos, - dcache$mem_master_awregion, - dcache$mem_master_bid, - dcache$mem_master_rid, - dcache$mem_master_wid, - dcache$set_verbosity_verbosity; - wire [2 : 0] dcache$mem_master_arprot, - dcache$mem_master_arsize, - dcache$mem_master_awprot, - dcache$mem_master_awsize, - dcache$req_f3; - wire [1 : 0] dcache$mem_master_arburst, - dcache$mem_master_awburst, - dcache$mem_master_bresp, - dcache$mem_master_rresp, - dcache$req_op, - dcache$req_priv; - wire dcache$EN_req, - dcache$EN_server_flush_request_put, - dcache$EN_server_flush_response_get, - dcache$EN_server_reset_request_put, - dcache$EN_server_reset_response_get, - dcache$EN_set_verbosity, - dcache$EN_tlb_flush, - dcache$RDY_server_flush_request_put, - dcache$RDY_server_flush_response_get, - dcache$RDY_server_reset_request_put, - dcache$RDY_server_reset_response_get, - dcache$exc, - dcache$mem_master_arlock, - dcache$mem_master_arready, - dcache$mem_master_arvalid, - dcache$mem_master_awlock, - dcache$mem_master_awready, - dcache$mem_master_awvalid, - dcache$mem_master_bready, - dcache$mem_master_bvalid, - dcache$mem_master_rlast, - dcache$mem_master_rready, - dcache$mem_master_rvalid, - dcache$mem_master_wlast, - dcache$mem_master_wready, - dcache$mem_master_wvalid, - dcache$req_mstatus_MXR, - dcache$req_sstatus_SUM, - dcache$valid; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule icache - wire [63 : 0] icache$addr, - icache$mem_master_araddr, - icache$mem_master_awaddr, - icache$mem_master_rdata, - icache$mem_master_wdata, - icache$req_addr, - icache$req_satp, - icache$req_st_value, - icache$word64; - wire [7 : 0] icache$mem_master_arlen, - icache$mem_master_awlen, - icache$mem_master_wstrb; - wire [6 : 0] icache$req_amo_funct7; - wire [3 : 0] icache$exc_code, - icache$mem_master_arcache, - icache$mem_master_arid, - icache$mem_master_arqos, - icache$mem_master_arregion, - icache$mem_master_awcache, - icache$mem_master_awid, - icache$mem_master_awqos, - icache$mem_master_awregion, - icache$mem_master_bid, - icache$mem_master_rid, - icache$mem_master_wid, - icache$set_verbosity_verbosity; - wire [2 : 0] icache$mem_master_arprot, - icache$mem_master_arsize, - icache$mem_master_awprot, - icache$mem_master_awsize, - icache$req_f3; - wire [1 : 0] icache$mem_master_arburst, - icache$mem_master_awburst, - icache$mem_master_bresp, - icache$mem_master_rresp, - icache$req_op, - icache$req_priv; - wire icache$EN_req, - icache$EN_server_flush_request_put, - icache$EN_server_flush_response_get, - icache$EN_server_reset_request_put, - icache$EN_server_reset_response_get, - icache$EN_set_verbosity, - icache$EN_tlb_flush, - icache$RDY_server_flush_request_put, - icache$RDY_server_flush_response_get, - icache$RDY_server_reset_request_put, - icache$RDY_server_reset_response_get, - icache$exc, - icache$mem_master_arlock, - icache$mem_master_arready, - icache$mem_master_arvalid, - icache$mem_master_awlock, - icache$mem_master_awready, - icache$mem_master_awvalid, - icache$mem_master_bready, - icache$mem_master_bvalid, - icache$mem_master_rlast, - icache$mem_master_rready, - icache$mem_master_rvalid, - icache$mem_master_wlast, - icache$mem_master_wready, - icache$mem_master_wvalid, - icache$req_mstatus_MXR, - icache$req_sstatus_SUM, - icache$valid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, - CAN_FIRE_dmem_req, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, - CAN_FIRE_imem_req, - CAN_FIRE_server_fence_i_request_put, - CAN_FIRE_server_fence_i_response_get, - CAN_FIRE_server_fence_request_put, - CAN_FIRE_server_fence_response_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_sfence_vma, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, - WILL_FIRE_dmem_req, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, - WILL_FIRE_imem_req, - WILL_FIRE_server_fence_i_request_put, - WILL_FIRE_server_fence_i_response_get, - WILL_FIRE_server_fence_request_put, - WILL_FIRE_server_fence_response_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_sfence_vma; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h1675; - reg [31 : 0] v__h1826; - reg [31 : 0] v__h1669; - reg [31 : 0] v__h1820; - // synopsys translate_on - - // remaining internal signals - wire NOT_cfg_verbosity_read_ULE_1___d9; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = rg_state == 2'd2 ; - assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method imem_req - assign CAN_FIRE_imem_req = 1'd1 ; - assign WILL_FIRE_imem_req = EN_imem_req ; - - // value method imem_valid - assign imem_valid = icache$valid ; - - // value method imem_is_i32_not_i16 - assign imem_is_i32_not_i16 = 1'd1 ; - - // value method imem_pc - assign imem_pc = icache$addr ; - - // value method imem_instr - assign imem_instr = icache$word64[31:0] ; - - // value method imem_exc - assign imem_exc = icache$exc ; - - // value method imem_exc_code - assign imem_exc_code = icache$exc_code ; - - // value method imem_tval - assign imem_tval = icache$addr ; - - // value method imem_master_m_awvalid - assign imem_master_awvalid = icache$mem_master_awvalid ; - - // value method imem_master_m_awid - assign imem_master_awid = icache$mem_master_awid ; - - // value method imem_master_m_awaddr - assign imem_master_awaddr = icache$mem_master_awaddr ; - - // value method imem_master_m_awlen - assign imem_master_awlen = icache$mem_master_awlen ; - - // value method imem_master_m_awsize - assign imem_master_awsize = icache$mem_master_awsize ; - - // value method imem_master_m_awburst - assign imem_master_awburst = icache$mem_master_awburst ; - - // value method imem_master_m_awlock - assign imem_master_awlock = icache$mem_master_awlock ; - - // value method imem_master_m_awcache - assign imem_master_awcache = icache$mem_master_awcache ; - - // value method imem_master_m_awprot - assign imem_master_awprot = icache$mem_master_awprot ; - - // value method imem_master_m_awqos - assign imem_master_awqos = icache$mem_master_awqos ; - - // value method imem_master_m_awregion - assign imem_master_awregion = icache$mem_master_awregion ; - - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; - - // value method imem_master_m_wvalid - assign imem_master_wvalid = icache$mem_master_wvalid ; - - // value method imem_master_m_wid - assign imem_master_wid = icache$mem_master_wid ; - - // value method imem_master_m_wdata - assign imem_master_wdata = icache$mem_master_wdata ; - - // value method imem_master_m_wstrb - assign imem_master_wstrb = icache$mem_master_wstrb ; - - // value method imem_master_m_wlast - assign imem_master_wlast = icache$mem_master_wlast ; - - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; - - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; - - // value method imem_master_m_bready - assign imem_master_bready = icache$mem_master_bready ; - - // value method imem_master_m_arvalid - assign imem_master_arvalid = icache$mem_master_arvalid ; - - // value method imem_master_m_arid - assign imem_master_arid = icache$mem_master_arid ; - - // value method imem_master_m_araddr - assign imem_master_araddr = icache$mem_master_araddr ; - - // value method imem_master_m_arlen - assign imem_master_arlen = icache$mem_master_arlen ; - - // value method imem_master_m_arsize - assign imem_master_arsize = icache$mem_master_arsize ; - - // value method imem_master_m_arburst - assign imem_master_arburst = icache$mem_master_arburst ; - - // value method imem_master_m_arlock - assign imem_master_arlock = icache$mem_master_arlock ; - - // value method imem_master_m_arcache - assign imem_master_arcache = icache$mem_master_arcache ; - - // value method imem_master_m_arprot - assign imem_master_arprot = icache$mem_master_arprot ; - - // value method imem_master_m_arqos - assign imem_master_arqos = icache$mem_master_arqos ; - - // value method imem_master_m_arregion - assign imem_master_arregion = icache$mem_master_arregion ; - - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; - - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; - - // value method imem_master_m_rready - assign imem_master_rready = icache$mem_master_rready ; - - // action method dmem_req - assign CAN_FIRE_dmem_req = 1'd1 ; - assign WILL_FIRE_dmem_req = EN_dmem_req ; - - // value method dmem_valid - assign dmem_valid = dcache$valid ; - - // value method dmem_word64 - assign dmem_word64 = dcache$word64 ; - - // value method dmem_st_amo_val - assign dmem_st_amo_val = dcache$st_amo_val ; - - // value method dmem_exc - assign dmem_exc = dcache$exc ; - - // value method dmem_exc_code - assign dmem_exc_code = dcache$exc_code ; - - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = dcache$mem_master_awvalid ; - - // value method dmem_master_m_awid - assign dmem_master_awid = dcache$mem_master_awid ; - - // value method dmem_master_m_awaddr - assign dmem_master_awaddr = dcache$mem_master_awaddr ; - - // value method dmem_master_m_awlen - assign dmem_master_awlen = dcache$mem_master_awlen ; - - // value method dmem_master_m_awsize - assign dmem_master_awsize = dcache$mem_master_awsize ; - - // value method dmem_master_m_awburst - assign dmem_master_awburst = dcache$mem_master_awburst ; - - // value method dmem_master_m_awlock - assign dmem_master_awlock = dcache$mem_master_awlock ; - - // value method dmem_master_m_awcache - assign dmem_master_awcache = dcache$mem_master_awcache ; - - // value method dmem_master_m_awprot - assign dmem_master_awprot = dcache$mem_master_awprot ; - - // value method dmem_master_m_awqos - assign dmem_master_awqos = dcache$mem_master_awqos ; - - // value method dmem_master_m_awregion - assign dmem_master_awregion = dcache$mem_master_awregion ; - - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; - - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = dcache$mem_master_wvalid ; - - // value method dmem_master_m_wid - assign dmem_master_wid = dcache$mem_master_wid ; - - // value method dmem_master_m_wdata - assign dmem_master_wdata = dcache$mem_master_wdata ; - - // value method dmem_master_m_wstrb - assign dmem_master_wstrb = dcache$mem_master_wstrb ; - - // value method dmem_master_m_wlast - assign dmem_master_wlast = dcache$mem_master_wlast ; - - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; - - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; - - // value method dmem_master_m_bready - assign dmem_master_bready = dcache$mem_master_bready ; - - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = dcache$mem_master_arvalid ; - - // value method dmem_master_m_arid - assign dmem_master_arid = dcache$mem_master_arid ; - - // value method dmem_master_m_araddr - assign dmem_master_araddr = dcache$mem_master_araddr ; - - // value method dmem_master_m_arlen - assign dmem_master_arlen = dcache$mem_master_arlen ; - - // value method dmem_master_m_arsize - assign dmem_master_arsize = dcache$mem_master_arsize ; - - // value method dmem_master_m_arburst - assign dmem_master_arburst = dcache$mem_master_arburst ; - - // value method dmem_master_m_arlock - assign dmem_master_arlock = dcache$mem_master_arlock ; - - // value method dmem_master_m_arcache - assign dmem_master_arcache = dcache$mem_master_arcache ; - - // value method dmem_master_m_arprot - assign dmem_master_arprot = dcache$mem_master_arprot ; - - // value method dmem_master_m_arqos - assign dmem_master_arqos = dcache$mem_master_arqos ; - - // value method dmem_master_m_arregion - assign dmem_master_arregion = dcache$mem_master_arregion ; - - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; - - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; - - // value method dmem_master_m_rready - assign dmem_master_rready = dcache$mem_master_rready ; - - // action method server_fence_i_request_put - assign RDY_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_i_request_put = - dcache$RDY_server_flush_request_put && - icache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_i_request_put = - EN_server_fence_i_request_put ; - - // action method server_fence_i_response_get - assign RDY_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_i_response_get = - dcache$RDY_server_flush_response_get && - icache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_i_response_get = - EN_server_fence_i_response_get ; - - // action method server_fence_request_put - assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ; - assign CAN_FIRE_server_fence_request_put = - dcache$RDY_server_flush_request_put ; - assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ; - - // action method server_fence_response_get - assign RDY_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign CAN_FIRE_server_fence_response_get = - dcache$RDY_server_flush_response_get ; - assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ; - - // action method sfence_vma - assign RDY_sfence_vma = 1'd1 ; - assign CAN_FIRE_sfence_vma = 1'd1 ; - assign WILL_FIRE_sfence_vma = EN_sfence_vma ; - - // submodule dcache - mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(dcache$mem_master_arready), - .mem_master_awready(dcache$mem_master_awready), - .mem_master_bid(dcache$mem_master_bid), - .mem_master_bresp(dcache$mem_master_bresp), - .mem_master_bvalid(dcache$mem_master_bvalid), - .mem_master_rdata(dcache$mem_master_rdata), - .mem_master_rid(dcache$mem_master_rid), - .mem_master_rlast(dcache$mem_master_rlast), - .mem_master_rresp(dcache$mem_master_rresp), - .mem_master_rvalid(dcache$mem_master_rvalid), - .mem_master_wready(dcache$mem_master_wready), - .req_addr(dcache$req_addr), - .req_amo_funct7(dcache$req_amo_funct7), - .req_f3(dcache$req_f3), - .req_mstatus_MXR(dcache$req_mstatus_MXR), - .req_op(dcache$req_op), - .req_priv(dcache$req_priv), - .req_satp(dcache$req_satp), - .req_sstatus_SUM(dcache$req_sstatus_SUM), - .req_st_value(dcache$req_st_value), - .set_verbosity_verbosity(dcache$set_verbosity_verbosity), - .EN_set_verbosity(dcache$EN_set_verbosity), - .EN_server_reset_request_put(dcache$EN_server_reset_request_put), - .EN_server_reset_response_get(dcache$EN_server_reset_response_get), - .EN_req(dcache$EN_req), - .EN_server_flush_request_put(dcache$EN_server_flush_request_put), - .EN_server_flush_response_get(dcache$EN_server_flush_response_get), - .EN_tlb_flush(dcache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), - .valid(dcache$valid), - .addr(), - .word64(dcache$word64), - .st_amo_val(dcache$st_amo_val), - .exc(dcache$exc), - .exc_code(dcache$exc_code), - .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(dcache$mem_master_awvalid), - .mem_master_awid(dcache$mem_master_awid), - .mem_master_awaddr(dcache$mem_master_awaddr), - .mem_master_awlen(dcache$mem_master_awlen), - .mem_master_awsize(dcache$mem_master_awsize), - .mem_master_awburst(dcache$mem_master_awburst), - .mem_master_awlock(dcache$mem_master_awlock), - .mem_master_awcache(dcache$mem_master_awcache), - .mem_master_awprot(dcache$mem_master_awprot), - .mem_master_awqos(dcache$mem_master_awqos), - .mem_master_awregion(dcache$mem_master_awregion), - .mem_master_wvalid(dcache$mem_master_wvalid), - .mem_master_wid(dcache$mem_master_wid), - .mem_master_wdata(dcache$mem_master_wdata), - .mem_master_wstrb(dcache$mem_master_wstrb), - .mem_master_wlast(dcache$mem_master_wlast), - .mem_master_bready(dcache$mem_master_bready), - .mem_master_arvalid(dcache$mem_master_arvalid), - .mem_master_arid(dcache$mem_master_arid), - .mem_master_araddr(dcache$mem_master_araddr), - .mem_master_arlen(dcache$mem_master_arlen), - .mem_master_arsize(dcache$mem_master_arsize), - .mem_master_arburst(dcache$mem_master_arburst), - .mem_master_arlock(dcache$mem_master_arlock), - .mem_master_arcache(dcache$mem_master_arcache), - .mem_master_arprot(dcache$mem_master_arprot), - .mem_master_arqos(dcache$mem_master_arqos), - .mem_master_arregion(dcache$mem_master_arregion), - .mem_master_rready(dcache$mem_master_rready)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule icache - mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(icache$mem_master_arready), - .mem_master_awready(icache$mem_master_awready), - .mem_master_bid(icache$mem_master_bid), - .mem_master_bresp(icache$mem_master_bresp), - .mem_master_bvalid(icache$mem_master_bvalid), - .mem_master_rdata(icache$mem_master_rdata), - .mem_master_rid(icache$mem_master_rid), - .mem_master_rlast(icache$mem_master_rlast), - .mem_master_rresp(icache$mem_master_rresp), - .mem_master_rvalid(icache$mem_master_rvalid), - .mem_master_wready(icache$mem_master_wready), - .req_addr(icache$req_addr), - .req_amo_funct7(icache$req_amo_funct7), - .req_f3(icache$req_f3), - .req_mstatus_MXR(icache$req_mstatus_MXR), - .req_op(icache$req_op), - .req_priv(icache$req_priv), - .req_satp(icache$req_satp), - .req_sstatus_SUM(icache$req_sstatus_SUM), - .req_st_value(icache$req_st_value), - .set_verbosity_verbosity(icache$set_verbosity_verbosity), - .EN_set_verbosity(icache$EN_set_verbosity), - .EN_server_reset_request_put(icache$EN_server_reset_request_put), - .EN_server_reset_response_get(icache$EN_server_reset_response_get), - .EN_req(icache$EN_req), - .EN_server_flush_request_put(icache$EN_server_flush_request_put), - .EN_server_flush_response_get(icache$EN_server_flush_response_get), - .EN_tlb_flush(icache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), - .valid(icache$valid), - .addr(icache$addr), - .word64(icache$word64), - .st_amo_val(), - .exc(icache$exc), - .exc_code(icache$exc_code), - .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(icache$mem_master_awvalid), - .mem_master_awid(icache$mem_master_awid), - .mem_master_awaddr(icache$mem_master_awaddr), - .mem_master_awlen(icache$mem_master_awlen), - .mem_master_awsize(icache$mem_master_awsize), - .mem_master_awburst(icache$mem_master_awburst), - .mem_master_awlock(icache$mem_master_awlock), - .mem_master_awcache(icache$mem_master_awcache), - .mem_master_awprot(icache$mem_master_awprot), - .mem_master_awqos(icache$mem_master_awqos), - .mem_master_awregion(icache$mem_master_awregion), - .mem_master_wvalid(icache$mem_master_wvalid), - .mem_master_wid(icache$mem_master_wid), - .mem_master_wdata(icache$mem_master_wdata), - .mem_master_wstrb(icache$mem_master_wstrb), - .mem_master_wlast(icache$mem_master_wlast), - .mem_master_bready(icache$mem_master_bready), - .mem_master_arvalid(icache$mem_master_arvalid), - .mem_master_arid(icache$mem_master_arid), - .mem_master_araddr(icache$mem_master_araddr), - .mem_master_arlen(icache$mem_master_arlen), - .mem_master_arsize(icache$mem_master_arsize), - .mem_master_arburst(icache$mem_master_arburst), - .mem_master_arlock(icache$mem_master_arlock), - .mem_master_arcache(icache$mem_master_arcache), - .mem_master_arprot(icache$mem_master_arprot), - .mem_master_arqos(icache$mem_master_arqos), - .mem_master_arregion(icache$mem_master_arregion), - .mem_master_rready(icache$mem_master_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(), - .m_uart0_addr_size(), - .m_uart0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_mem0_controller_addr_base(), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - dcache$RDY_server_reset_request_put && - icache$RDY_server_reset_request_put && - rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_reset_complete - assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && - !EN_server_fence_i_request_put ; - assign MUX_rg_state$write_1__SEL_3 = - dcache$RDY_server_reset_response_get && - icache$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - rg_state == 2'd1 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_state - always@(EN_server_reset_request_put or - WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete) - begin - case (1'b1) // synopsys parallel_case - EN_server_reset_request_put: rg_state$D_IN = 2'd0; - WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1; - WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2; - default: rg_state$D_IN = 2'b10 /* unspecified value */ ; - endcase - end - assign rg_state$EN = - EN_server_reset_request_put || WILL_FIRE_RL_rl_reset || - WILL_FIRE_RL_rl_reset_complete ; - - // submodule dcache - assign dcache$mem_master_arready = dmem_master_arready ; - assign dcache$mem_master_awready = dmem_master_awready ; - assign dcache$mem_master_bid = dmem_master_bid ; - assign dcache$mem_master_bresp = dmem_master_bresp ; - assign dcache$mem_master_bvalid = dmem_master_bvalid ; - assign dcache$mem_master_rdata = dmem_master_rdata ; - assign dcache$mem_master_rid = dmem_master_rid ; - assign dcache$mem_master_rlast = dmem_master_rlast ; - assign dcache$mem_master_rresp = dmem_master_rresp ; - assign dcache$mem_master_rvalid = dmem_master_rvalid ; - assign dcache$mem_master_wready = dmem_master_wready ; - assign dcache$req_addr = dmem_req_addr ; - assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ; - assign dcache$req_f3 = dmem_req_f3 ; - assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ; - assign dcache$req_op = dmem_req_op ; - assign dcache$req_priv = dmem_req_priv ; - assign dcache$req_satp = dmem_req_satp ; - assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ; - assign dcache$req_st_value = dmem_req_store_value ; - assign dcache$set_verbosity_verbosity = 4'h0 ; - assign dcache$EN_set_verbosity = 1'b0 ; - assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign dcache$EN_req = EN_dmem_req ; - assign dcache$EN_server_flush_request_put = - EN_server_fence_i_request_put || EN_server_fence_request_put ; - assign dcache$EN_server_flush_response_get = - EN_server_fence_i_response_get || EN_server_fence_response_get ; - assign dcache$EN_tlb_flush = EN_sfence_vma ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule icache - assign icache$mem_master_arready = imem_master_arready ; - assign icache$mem_master_awready = imem_master_awready ; - assign icache$mem_master_bid = imem_master_bid ; - assign icache$mem_master_bresp = imem_master_bresp ; - assign icache$mem_master_bvalid = imem_master_bvalid ; - assign icache$mem_master_rdata = imem_master_rdata ; - assign icache$mem_master_rid = imem_master_rid ; - assign icache$mem_master_rlast = imem_master_rlast ; - assign icache$mem_master_rresp = imem_master_rresp ; - assign icache$mem_master_rvalid = imem_master_rvalid ; - assign icache$mem_master_wready = imem_master_wready ; - assign icache$req_addr = imem_req_addr ; - assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ; - assign icache$req_f3 = imem_req_f3 ; - assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ; - assign icache$req_op = 2'd0 ; - assign icache$req_priv = imem_req_priv ; - assign icache$req_satp = imem_req_satp ; - assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ; - assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign icache$set_verbosity_verbosity = 4'h0 ; - assign icache$EN_set_verbosity = 1'b0 ; - assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; - assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; - assign icache$EN_req = EN_imem_req ; - assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ; - assign icache$EN_server_flush_response_get = - EN_server_fence_i_response_get ; - assign icache$EN_tlb_flush = EN_sfence_vma ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1675 = $stime; - #0; - end - v__h1669 = v__h1675 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset", v__h1669); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - begin - v__h1826 = $stime; - #0; - end - v__h1820 = v__h1826 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset_complete", v__h1820); - end - // synopsys translate_on -endmodule // mkNear_Mem - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v deleted file mode 100644 index 32e93584..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO.v +++ /dev/null @@ -1,1308 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// RDY_server_request_put O 1 reg -// server_response_get O 66 reg -// RDY_server_response_get O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// server_request_put I 137 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_server_request_put I 1 -// EN_server_response_get I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - server_request_put, - EN_server_request_put, - RDY_server_request_put, - - EN_server_response_get, - server_response_get, - RDY_server_response_get, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method server_request_put - input [136 : 0] server_request_put; - input EN_server_request_put; - output RDY_server_request_put; - - // actionvalue method server_response_get - input EN_server_response_get; - output [65 : 0] server_response_get; - output RDY_server_response_get; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [65 : 0] server_response_get; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_request_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_server_response_get, - RDY_set_addr_map, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reqs - wire [136 : 0] f_reqs$D_IN, f_reqs$D_OUT; - wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_rsps - wire [65 : 0] f_rsps$D_IN, f_rsps$D_OUT; - wire f_rsps$CLR, f_rsps$DEQ, f_rsps$EMPTY_N, f_rsps$ENQ, f_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_request_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_server_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_request_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_server_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire [65 : 0] MUX_f_rsps$enq_1__VAL_1, MUX_f_rsps$enq_1__VAL_2; - wire [63 : 0] MUX_crg_time$port1__write_1__VAL_1, - MUX_crg_timecmp$port1__write_1__VAL_1; - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8676; - reg [31 : 0] v__h8808; - reg [31 : 0] v__h1471; - reg [31 : 0] v__h1868; - reg [31 : 0] v__h2065; - reg [31 : 0] v__h1714; - reg [31 : 0] v__h2442; - reg [31 : 0] v__h7890; - reg [31 : 0] v__h8258; - reg [31 : 0] v__h8368; - reg [31 : 0] v__h8475; - reg [31 : 0] v__h1465; - reg [31 : 0] v__h1708; - reg [31 : 0] v__h1862; - reg [31 : 0] v__h2059; - reg [31 : 0] v__h2436; - reg [31 : 0] v__h7884; - reg [31 : 0] v__h8252; - reg [31 : 0] v__h8362; - reg [31 : 0] v__h8469; - reg [31 : 0] v__h8670; - reg [31 : 0] v__h8802; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rsp_rdata__h2209; - wire [63 : 0] byte_addr__h1981, - mask__h2865, - mask__h5362, - new_data__h5360, - new_time__h4107, - new_time__h6632, - new_timecmp__h2834, - new_timecmp__h5331, - old_time__h6631, - rdata__h1996, - rdata__h2020, - rdata__h2026, - x__h2876, - x__h4149, - x__h5373, - x__h6674, - y__h2877, - y__h2878, - y__h5374, - y__h5375; - wire [7 : 0] SEXT_f_reqs_first__8_BIT_0_31___d132, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_7_07___d108; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method server_request_put - assign RDY_server_request_put = f_reqs$FULL_N ; - assign CAN_FIRE_server_request_put = f_reqs$FULL_N ; - assign WILL_FIRE_server_request_put = EN_server_request_put ; - - // actionvalue method server_response_get - assign server_response_get = f_rsps$D_OUT ; - assign RDY_server_response_get = f_rsps$EMPTY_N ; - assign CAN_FIRE_server_response_get = f_rsps$EMPTY_N ; - assign WILL_FIRE_server_response_get = EN_server_response_get ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reqs - FIFO2 #(.width(32'd137), .guarded(32'd1)) f_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reqs$D_IN), - .ENQ(f_reqs$ENQ), - .DEQ(f_reqs$DEQ), - .CLR(f_reqs$CLR), - .D_OUT(f_reqs$D_OUT), - .FULL_N(f_reqs$FULL_N), - .EMPTY_N(f_reqs$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_rsps - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_rsps$D_IN), - .ENQ(f_rsps$ENQ), - .DEQ(f_rsps$DEQ), - .CLR(f_rsps$CLR), - .D_OUT(f_rsps$D_OUT), - .FULL_N(f_rsps$FULL_N), - .EMPTY_N(f_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && rg_state && - !f_reset_reqs$EMPTY_N && - f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && - (byte_addr__h1981 != 64'h0 || - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - f_sw_interrupt_req$FULL_N) && - rg_state && - !f_reset_reqs$EMPTY_N && - !f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign MUX_crg_time$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h000000000000BFF8) ? - new_time__h4107 : - new_time__h6632 ; - assign MUX_crg_timecmp$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h0000000000004000) ? - new_timecmp__h2834 : - new_timecmp__h5331 ; - assign MUX_f_rsps$enq_1__VAL_1 = - { 1'd1, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - rsp_rdata__h2209 } ; - assign MUX_f_rsps$enq_1__VAL_2 = - { 1'd0, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - 64'hAAAAAAAAAAAAAAAA } ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? - MUX_crg_time$port1__write_1__VAL_1 : - 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h6631 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - MUX_crg_timecmp$port1__write_1__VAL_1 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = MUX_rg_msip$write_1__SEL_1 && f_reqs$D_OUT[8] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reqs - assign f_reqs$D_IN = server_request_put ; - assign f_reqs$ENQ = EN_server_request_put ; - assign f_reqs$DEQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_rsps - assign f_rsps$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_f_rsps$enq_1__VAL_1 : - MUX_f_rsps$enq_1__VAL_2 ; - assign f_rsps$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_process_wr_req ; - assign f_rsps$DEQ = EN_server_response_get ; - assign f_rsps$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = f_reqs$D_OUT[8] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_f_reqs_first__8_BIT_0_31___d132 = {8{f_reqs$D_OUT[0]}} ; - assign SEXT_f_reqs_first__8_BIT_1_28___d129 = {8{f_reqs$D_OUT[1]}} ; - assign SEXT_f_reqs_first__8_BIT_2_24___d125 = {8{f_reqs$D_OUT[2]}} ; - assign SEXT_f_reqs_first__8_BIT_3_21___d122 = {8{f_reqs$D_OUT[3]}} ; - assign SEXT_f_reqs_first__8_BIT_4_17___d118 = {8{f_reqs$D_OUT[4]}} ; - assign SEXT_f_reqs_first__8_BIT_5_14___d115 = {8{f_reqs$D_OUT[5]}} ; - assign SEXT_f_reqs_first__8_BIT_6_10___d111 = {8{f_reqs$D_OUT[6]}} ; - assign SEXT_f_reqs_first__8_BIT_7_07___d108 = {8{f_reqs$D_OUT[7]}} ; - assign byte_addr__h1981 = f_reqs$D_OUT[135:72] - rg_addr_base ; - assign mask__h2865 = - { SEXT_f_reqs_first__8_BIT_7_07___d108, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign mask__h5362 = - { SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'd0 } ; - assign new_data__h5360 = { f_reqs$D_OUT[39:8], 32'h0 } ; - assign new_time__h4107 = x__h4149 | y__h2877 ; - assign new_time__h6632 = x__h6674 | y__h5374 ; - assign new_timecmp__h2834 = x__h2876 | y__h2877 ; - assign new_timecmp__h5331 = x__h5373 | y__h5374 ; - assign old_time__h6631 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata__h1996 = { 63'd0, rg_msip } ; - assign rdata__h2020 = { 32'd0, crg_timecmp[63:32] } ; - assign rdata__h2026 = { 32'd0, crg_time[63:32] } ; - assign rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 = - rg_msip == f_reqs$D_OUT[8] ; - assign x__h2876 = crg_timecmp & y__h2878 ; - assign x__h4149 = old_time__h6631 & y__h2878 ; - assign x__h5373 = crg_timecmp & y__h5375 ; - assign x__h6674 = old_time__h6631 & y__h5375 ; - assign y__h2877 = f_reqs$D_OUT[71:8] & mask__h2865 ; - assign y__h2878 = - { ~SEXT_f_reqs_first__8_BIT_7_07___d108, - ~SEXT_f_reqs_first__8_BIT_6_10___d111, - ~SEXT_f_reqs_first__8_BIT_5_14___d115, - ~SEXT_f_reqs_first__8_BIT_4_17___d118, - ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign y__h5374 = new_data__h5360 & mask__h5362 ; - assign y__h5375 = - { ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'hFFFFFFFF } ; - always@(byte_addr__h1981 or - rdata__h1996 or - crg_timecmp or rdata__h2020 or crg_time or rdata__h2026) - begin - case (byte_addr__h1981) - 64'h0: rsp_rdata__h2209 = rdata__h1996; - 64'h0000000000000004: rsp_rdata__h2209 = 64'd0; - 64'h0000000000004000: rsp_rdata__h2209 = crg_timecmp; - 64'h0000000000004004: rsp_rdata__h2209 = rdata__h2020; - 64'h000000000000BFF8: rsp_rdata__h2209 = crg_time; - 64'h000000000000BFFC: rsp_rdata__h2209 = rdata__h2026; - default: rsp_rdata__h2209 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8676 = $stime; - #0; - end - v__h8670 = v__h8676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_timer_interrupt_req: %x", - v__h8670, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8808 = $stime; - #0; - end - v__h8802 = v__h8808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_sw_interrupt_req: %x", - v__h8802, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1471 = $stime; - #0; - end - v__h1465 = v__h1471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO.rl_reset", v__h1465); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1868 = $stime; - #0; - end - v__h1862 = v__h1868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_rd_req: rg_mtip = %0d", - v__h1862, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h2065 = $stime; - #0; - end - v__h2059 = v__h2065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_rd_req: unrecognized addr", - v__h2059); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rsp_rdata__h2209, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1714 = $stime; - #0; - end - v__h1708 = v__h1714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h1708, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2442 = $stime; - #0; - end - v__h2436 = v__h2442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_wr_req: rg_mtip = %0d", - v__h2436, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", f_reqs$D_OUT[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h2834); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h2834 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h4107); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h5331); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h5331 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h6632); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h7890 = $stime; - #0; - end - v__h7884 = v__h7890 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_wr_req: unrecognized addr", - v__h7884); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 64'hAAAAAAAAAAAAAAAA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h8258 = $stime; - #0; - end - v__h8252 = v__h8258 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h8252, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h8368 = $stime; - #0; - end - v__h8362 = v__h8368 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h8362, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h8475 = $stime; - #0; - end - v__h8469 = v__h8475 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h8469, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v deleted file mode 100644 index 0883c8da..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkNear_Mem_IO_AXI4.v +++ /dev/null @@ -1,2812 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO_AXI4(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_state$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h10065; - reg [31 : 0] v__h10197; - reg [31 : 0] v__h1852; - reg [31 : 0] v__h2269; - reg [31 : 0] v__h2453; - reg [31 : 0] v__h2640; - reg [31 : 0] v__h2878; - reg [31 : 0] v__h2095; - reg [31 : 0] v__h3161; - reg [31 : 0] v__h3391; - reg [31 : 0] v__h8927; - reg [31 : 0] v__h9148; - reg [31 : 0] v__h9475; - reg [31 : 0] v__h9585; - reg [31 : 0] v__h9692; - reg [31 : 0] v__h1846; - reg [31 : 0] v__h2089; - reg [31 : 0] v__h2263; - reg [31 : 0] v__h2447; - reg [31 : 0] v__h2634; - reg [31 : 0] v__h2872; - reg [31 : 0] v__h3155; - reg [31 : 0] v__h3385; - reg [31 : 0] v__h8921; - reg [31 : 0] v__h9142; - reg [31 : 0] v__h9469; - reg [31 : 0] v__h9579; - reg [31 : 0] v__h9686; - reg [31 : 0] v__h10059; - reg [31 : 0] v__h10191; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] _theResult___fst__h2566; - reg [1 : 0] _theResult___snd__h2567, v__h3517; - wire [63 : 0] byte_addr__h2405, - byte_addr__h3353, - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190, - mask__h3798, - new_time__h5056, - new_timecmp__h3767, - old_time__h7614, - rdata___1__h2562, - x__h2751, - x__h3809, - x__h5098, - y__h3810, - y__h3811; - wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153; - wire [1 : 0] rresp__h2548, v__h3357; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108, - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53, - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102, - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 && - rg_state && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_rg_state$write_1__SEL_2 = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h000000000000BFF8 || - byte_addr__h3353 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? new_time__h5056 : 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h7614 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3353 == 64'h0000000000004000 || - byte_addr__h3353 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - new_timecmp__h3767 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = - MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; - assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - x__h2751, - rresp__h2548, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_2 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3357 } ; - assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_2 ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = - crg_time >= crg_timecmp ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 = - {8{slave_xactor_f_wr_data$D_OUT[1]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174 = - {8{slave_xactor_f_wr_data$D_OUT[2]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170 = - {8{slave_xactor_f_wr_data$D_OUT[3]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167 = - {8{slave_xactor_f_wr_data$D_OUT[4]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163 = - {8{slave_xactor_f_wr_data$D_OUT[5]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160 = - {8{slave_xactor_f_wr_data$D_OUT[6]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156 = - {8{slave_xactor_f_wr_data$D_OUT[7]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153 = - {8{slave_xactor_f_wr_data$D_OUT[8]}} ; - assign byte_addr__h2405 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign byte_addr__h3353 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190 = - new_timecmp__h3767 - old_time__h7614 ; - assign mask__h3798 = - { SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - assign new_time__h5056 = x__h5098 | y__h3810 ; - assign new_timecmp__h3767 = x__h3809 | y__h3810 ; - assign old_time__h7614 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata___1__h2562 = { 63'd0, rg_msip } ; - assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 = - rg_msip == slave_xactor_f_wr_data$D_OUT[9] ; - assign rresp__h2548 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 2'b11 : - _theResult___snd__h2567 ; - assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 = - slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 = - slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 || - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - f_sw_interrupt_req$FULL_N) ; - assign v__h3357 = - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ? - 2'b11 : - v__h3517 ; - assign x__h2751 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 64'd0 : - _theResult___fst__h2566 ; - assign x__h3809 = crg_timecmp & y__h3811 ; - assign x__h5098 = old_time__h7614 & y__h3811 ; - assign y__h3810 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3798 ; - assign y__h3811 = - { ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_52___d153, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_55___d156, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_59___d160, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_62___d163, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_66___d167, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_69___d170, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_73___d174, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_76___d177 } ; - always@(byte_addr__h2405) - begin - case (byte_addr__h2405) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - _theResult___snd__h2567 = 2'b0; - default: _theResult___snd__h2567 = 2'b11; - endcase - end - always@(byte_addr__h2405 or rdata___1__h2562 or crg_timecmp or crg_time) - begin - case (byte_addr__h2405) - 64'h0: _theResult___fst__h2566 = rdata___1__h2562; - 64'h0000000000000004: _theResult___fst__h2566 = 64'd0; - 64'h0000000000004000, 64'h0000000000004004: - _theResult___fst__h2566 = crg_timecmp; - 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___fst__h2566 = crg_time; - default: _theResult___fst__h2566 = 64'd0; - endcase - end - always@(byte_addr__h3353) - begin - case (byte_addr__h3353) - 64'h0, - 64'h0000000000000004, - 64'h0000000000004000, - 64'h0000000000004004, - 64'h000000000000BFF8, - 64'h000000000000BFFC: - v__h3517 = 2'b0; - default: v__h3517 = 2'b11; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10065 = $stime; - #0; - end - v__h10059 = v__h10065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x", - v__h10059, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h10197 = $stime; - #0; - end - v__h10191 = v__h10197 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x", - v__h10191, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1852 = $stime; - #0; - end - v__h1846 = v__h1852 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1846); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2269 = $stime; - #0; - end - v__h2263 = v__h2269 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", - v__h2263, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - begin - v__h2453 = $stime; - #0; - end - v__h2447 = v__h2453 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2447); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - begin - v__h2640 = $stime; - #0; - end - v__h2634 = v__h2640 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2634); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2878 = $stime; - #0; - end - v__h2872 = v__h2878 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2872); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", x__h2751); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rresp__h2548); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2095 = $stime; - #0; - end - v__h2089 = v__h2095 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h2089, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h3161 = $stime; - #0; - end - v__h3155 = v__h3161 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", - v__h3155, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - begin - v__h3391 = $stime; - #0; - end - v__h3385 = v__h3391 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h3385); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__51_AND_INV_SEXT_slave_ETC___d190); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7614); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3353 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - begin - v__h8927 = $stime; - #0; - end - v__h8921 = v__h8927 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h8921); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3353 != 64'h0 && - byte_addr__h3353 != 64'h0000000000004000 && - byte_addr__h3353 != 64'h000000000000BFF8 && - byte_addr__h3353 != 64'h0000000000000004 && - byte_addr__h3353 != 64'h0000000000004004 && - byte_addr__h3353 != 64'h000000000000BFFC)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h9148 = $stime; - #0; - end - v__h9142 = v__h9148 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9142); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", v__h3357); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h9475 = $stime; - #0; - end - v__h9469 = v__h9475 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9469, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h9585 = $stime; - #0; - end - v__h9579 = v__h9585 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9579, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h9692 = $stime; - #0; - end - v__h9686 = v__h9692 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9686, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO_AXI4 - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v deleted file mode 100644 index f74de61e..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkPLIC_16_2_7.v +++ /dev/null @@ -1,26991 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_show_PLIC_state O 1 const -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg -// v_targets_0_m_eip O 1 -// v_targets_1_m_eip O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wid I 4 reg -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg -// axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg -// axi4_slave_rready I 1 -// v_sources_0_m_interrupt_req_set_not_clear I 1 -// v_sources_1_m_interrupt_req_set_not_clear I 1 -// v_sources_2_m_interrupt_req_set_not_clear I 1 -// v_sources_3_m_interrupt_req_set_not_clear I 1 -// v_sources_4_m_interrupt_req_set_not_clear I 1 -// v_sources_5_m_interrupt_req_set_not_clear I 1 -// v_sources_6_m_interrupt_req_set_not_clear I 1 -// v_sources_7_m_interrupt_req_set_not_clear I 1 -// v_sources_8_m_interrupt_req_set_not_clear I 1 -// v_sources_9_m_interrupt_req_set_not_clear I 1 -// v_sources_10_m_interrupt_req_set_not_clear I 1 -// v_sources_11_m_interrupt_req_set_not_clear I 1 -// v_sources_12_m_interrupt_req_set_not_clear I 1 -// v_sources_13_m_interrupt_req_set_not_clear I 1 -// v_sources_14_m_interrupt_req_set_not_clear I 1 -// v_sources_15_m_interrupt_req_set_not_clear I 1 -// EN_set_verbosity I 1 -// EN_show_PLIC_state I 1 unused -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkPLIC_16_2_7(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_show_PLIC_state, - RDY_show_PLIC_state, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - axi4_slave_awvalid, - axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion, - - axi4_slave_awready, - - axi4_slave_wvalid, - axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast, - - axi4_slave_wready, - - axi4_slave_bvalid, - - axi4_slave_bid, - - axi4_slave_bresp, - - axi4_slave_bready, - - axi4_slave_arvalid, - axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion, - - axi4_slave_arready, - - axi4_slave_rvalid, - - axi4_slave_rid, - - axi4_slave_rdata, - - axi4_slave_rresp, - - axi4_slave_rlast, - - axi4_slave_rready, - - v_sources_0_m_interrupt_req_set_not_clear, - - v_sources_1_m_interrupt_req_set_not_clear, - - v_sources_2_m_interrupt_req_set_not_clear, - - v_sources_3_m_interrupt_req_set_not_clear, - - v_sources_4_m_interrupt_req_set_not_clear, - - v_sources_5_m_interrupt_req_set_not_clear, - - v_sources_6_m_interrupt_req_set_not_clear, - - v_sources_7_m_interrupt_req_set_not_clear, - - v_sources_8_m_interrupt_req_set_not_clear, - - v_sources_9_m_interrupt_req_set_not_clear, - - v_sources_10_m_interrupt_req_set_not_clear, - - v_sources_11_m_interrupt_req_set_not_clear, - - v_sources_12_m_interrupt_req_set_not_clear, - - v_sources_13_m_interrupt_req_set_not_clear, - - v_sources_14_m_interrupt_req_set_not_clear, - - v_sources_15_m_interrupt_req_set_not_clear, - - v_targets_0_m_eip, - - v_targets_1_m_eip); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method show_PLIC_state - input EN_show_PLIC_state; - output RDY_show_PLIC_state; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; - input [63 : 0] axi4_slave_awaddr; - input [7 : 0] axi4_slave_awlen; - input [2 : 0] axi4_slave_awsize; - input [1 : 0] axi4_slave_awburst; - input axi4_slave_awlock; - input [3 : 0] axi4_slave_awcache; - input [2 : 0] axi4_slave_awprot; - input [3 : 0] axi4_slave_awqos; - input [3 : 0] axi4_slave_awregion; - - // value method axi4_slave_m_awready - output axi4_slave_awready; - - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; - input [3 : 0] axi4_slave_wid; - input [63 : 0] axi4_slave_wdata; - input [7 : 0] axi4_slave_wstrb; - input axi4_slave_wlast; - - // value method axi4_slave_m_wready - output axi4_slave_wready; - - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; - - // value method axi4_slave_m_bresp - output [1 : 0] axi4_slave_bresp; - - // value method axi4_slave_m_buser - - // action method axi4_slave_m_bready - input axi4_slave_bready; - - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; - input [63 : 0] axi4_slave_araddr; - input [7 : 0] axi4_slave_arlen; - input [2 : 0] axi4_slave_arsize; - input [1 : 0] axi4_slave_arburst; - input axi4_slave_arlock; - input [3 : 0] axi4_slave_arcache; - input [2 : 0] axi4_slave_arprot; - input [3 : 0] axi4_slave_arqos; - input [3 : 0] axi4_slave_arregion; - - // value method axi4_slave_m_arready - output axi4_slave_arready; - - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata - output [63 : 0] axi4_slave_rdata; - - // value method axi4_slave_m_rresp - output [1 : 0] axi4_slave_rresp; - - // value method axi4_slave_m_rlast - output axi4_slave_rlast; - - // value method axi4_slave_m_ruser - - // action method axi4_slave_m_rready - input axi4_slave_rready; - - // action method v_sources_0_m_interrupt_req - input v_sources_0_m_interrupt_req_set_not_clear; - - // action method v_sources_1_m_interrupt_req - input v_sources_1_m_interrupt_req_set_not_clear; - - // action method v_sources_2_m_interrupt_req - input v_sources_2_m_interrupt_req_set_not_clear; - - // action method v_sources_3_m_interrupt_req - input v_sources_3_m_interrupt_req_set_not_clear; - - // action method v_sources_4_m_interrupt_req - input v_sources_4_m_interrupt_req_set_not_clear; - - // action method v_sources_5_m_interrupt_req - input v_sources_5_m_interrupt_req_set_not_clear; - - // action method v_sources_6_m_interrupt_req - input v_sources_6_m_interrupt_req_set_not_clear; - - // action method v_sources_7_m_interrupt_req - input v_sources_7_m_interrupt_req_set_not_clear; - - // action method v_sources_8_m_interrupt_req - input v_sources_8_m_interrupt_req_set_not_clear; - - // action method v_sources_9_m_interrupt_req - input v_sources_9_m_interrupt_req_set_not_clear; - - // action method v_sources_10_m_interrupt_req - input v_sources_10_m_interrupt_req_set_not_clear; - - // action method v_sources_11_m_interrupt_req - input v_sources_11_m_interrupt_req_set_not_clear; - - // action method v_sources_12_m_interrupt_req - input v_sources_12_m_interrupt_req_set_not_clear; - - // action method v_sources_13_m_interrupt_req - input v_sources_13_m_interrupt_req_set_not_clear; - - // action method v_sources_14_m_interrupt_req - input v_sources_14_m_interrupt_req_set_not_clear; - - // action method v_sources_15_m_interrupt_req - input v_sources_15_m_interrupt_req_set_not_clear; - - // value method v_targets_0_m_eip - output v_targets_0_m_eip; - - // value method v_targets_1_m_eip - output v_targets_1_m_eip; - - // signals for module outputs - wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; - wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; - wire RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - RDY_set_verbosity, - RDY_show_PLIC_state, - axi4_slave_arready, - axi4_slave_awready, - axi4_slave_bvalid, - axi4_slave_rlast, - axi4_slave_rvalid, - axi4_slave_wready, - v_targets_0_m_eip, - v_targets_1_m_eip; - - // register m_cfg_verbosity - reg [3 : 0] m_cfg_verbosity; - wire [3 : 0] m_cfg_verbosity$D_IN; - wire m_cfg_verbosity$EN; - - // register m_rg_addr_base - reg [63 : 0] m_rg_addr_base; - wire [63 : 0] m_rg_addr_base$D_IN; - wire m_rg_addr_base$EN; - - // register m_rg_addr_lim - reg [63 : 0] m_rg_addr_lim; - wire [63 : 0] m_rg_addr_lim$D_IN; - wire m_rg_addr_lim$EN; - - // register m_vrg_servicing_source_0 - reg [4 : 0] m_vrg_servicing_source_0; - wire [4 : 0] m_vrg_servicing_source_0$D_IN; - wire m_vrg_servicing_source_0$EN; - - // register m_vrg_servicing_source_1 - reg [4 : 0] m_vrg_servicing_source_1; - wire [4 : 0] m_vrg_servicing_source_1$D_IN; - wire m_vrg_servicing_source_1$EN; - - // register m_vrg_source_busy_0 - reg m_vrg_source_busy_0; - wire m_vrg_source_busy_0$D_IN, m_vrg_source_busy_0$EN; - - // register m_vrg_source_busy_1 - reg m_vrg_source_busy_1; - wire m_vrg_source_busy_1$D_IN, m_vrg_source_busy_1$EN; - - // register m_vrg_source_busy_10 - reg m_vrg_source_busy_10; - wire m_vrg_source_busy_10$D_IN, m_vrg_source_busy_10$EN; - - // register m_vrg_source_busy_11 - reg m_vrg_source_busy_11; - wire m_vrg_source_busy_11$D_IN, m_vrg_source_busy_11$EN; - - // register m_vrg_source_busy_12 - reg m_vrg_source_busy_12; - wire m_vrg_source_busy_12$D_IN, m_vrg_source_busy_12$EN; - - // register m_vrg_source_busy_13 - reg m_vrg_source_busy_13; - wire m_vrg_source_busy_13$D_IN, m_vrg_source_busy_13$EN; - - // register m_vrg_source_busy_14 - reg m_vrg_source_busy_14; - wire m_vrg_source_busy_14$D_IN, m_vrg_source_busy_14$EN; - - // register m_vrg_source_busy_15 - reg m_vrg_source_busy_15; - wire m_vrg_source_busy_15$D_IN, m_vrg_source_busy_15$EN; - - // register m_vrg_source_busy_16 - reg m_vrg_source_busy_16; - wire m_vrg_source_busy_16$D_IN, m_vrg_source_busy_16$EN; - - // register m_vrg_source_busy_2 - reg m_vrg_source_busy_2; - wire m_vrg_source_busy_2$D_IN, m_vrg_source_busy_2$EN; - - // register m_vrg_source_busy_3 - reg m_vrg_source_busy_3; - wire m_vrg_source_busy_3$D_IN, m_vrg_source_busy_3$EN; - - // register m_vrg_source_busy_4 - reg m_vrg_source_busy_4; - wire m_vrg_source_busy_4$D_IN, m_vrg_source_busy_4$EN; - - // register m_vrg_source_busy_5 - reg m_vrg_source_busy_5; - wire m_vrg_source_busy_5$D_IN, m_vrg_source_busy_5$EN; - - // register m_vrg_source_busy_6 - reg m_vrg_source_busy_6; - wire m_vrg_source_busy_6$D_IN, m_vrg_source_busy_6$EN; - - // register m_vrg_source_busy_7 - reg m_vrg_source_busy_7; - wire m_vrg_source_busy_7$D_IN, m_vrg_source_busy_7$EN; - - // register m_vrg_source_busy_8 - reg m_vrg_source_busy_8; - wire m_vrg_source_busy_8$D_IN, m_vrg_source_busy_8$EN; - - // register m_vrg_source_busy_9 - reg m_vrg_source_busy_9; - wire m_vrg_source_busy_9$D_IN, m_vrg_source_busy_9$EN; - - // register m_vrg_source_ip_0 - reg m_vrg_source_ip_0; - wire m_vrg_source_ip_0$D_IN, m_vrg_source_ip_0$EN; - - // register m_vrg_source_ip_1 - reg m_vrg_source_ip_1; - wire m_vrg_source_ip_1$D_IN, m_vrg_source_ip_1$EN; - - // register m_vrg_source_ip_10 - reg m_vrg_source_ip_10; - wire m_vrg_source_ip_10$D_IN, m_vrg_source_ip_10$EN; - - // register m_vrg_source_ip_11 - reg m_vrg_source_ip_11; - wire m_vrg_source_ip_11$D_IN, m_vrg_source_ip_11$EN; - - // register m_vrg_source_ip_12 - reg m_vrg_source_ip_12; - wire m_vrg_source_ip_12$D_IN, m_vrg_source_ip_12$EN; - - // register m_vrg_source_ip_13 - reg m_vrg_source_ip_13; - wire m_vrg_source_ip_13$D_IN, m_vrg_source_ip_13$EN; - - // register m_vrg_source_ip_14 - reg m_vrg_source_ip_14; - wire m_vrg_source_ip_14$D_IN, m_vrg_source_ip_14$EN; - - // register m_vrg_source_ip_15 - reg m_vrg_source_ip_15; - wire m_vrg_source_ip_15$D_IN, m_vrg_source_ip_15$EN; - - // register m_vrg_source_ip_16 - reg m_vrg_source_ip_16; - wire m_vrg_source_ip_16$D_IN, m_vrg_source_ip_16$EN; - - // register m_vrg_source_ip_2 - reg m_vrg_source_ip_2; - wire m_vrg_source_ip_2$D_IN, m_vrg_source_ip_2$EN; - - // register m_vrg_source_ip_3 - reg m_vrg_source_ip_3; - wire m_vrg_source_ip_3$D_IN, m_vrg_source_ip_3$EN; - - // register m_vrg_source_ip_4 - reg m_vrg_source_ip_4; - wire m_vrg_source_ip_4$D_IN, m_vrg_source_ip_4$EN; - - // register m_vrg_source_ip_5 - reg m_vrg_source_ip_5; - wire m_vrg_source_ip_5$D_IN, m_vrg_source_ip_5$EN; - - // register m_vrg_source_ip_6 - reg m_vrg_source_ip_6; - wire m_vrg_source_ip_6$D_IN, m_vrg_source_ip_6$EN; - - // register m_vrg_source_ip_7 - reg m_vrg_source_ip_7; - wire m_vrg_source_ip_7$D_IN, m_vrg_source_ip_7$EN; - - // register m_vrg_source_ip_8 - reg m_vrg_source_ip_8; - wire m_vrg_source_ip_8$D_IN, m_vrg_source_ip_8$EN; - - // register m_vrg_source_ip_9 - reg m_vrg_source_ip_9; - wire m_vrg_source_ip_9$D_IN, m_vrg_source_ip_9$EN; - - // register m_vrg_source_prio_0 - reg [2 : 0] m_vrg_source_prio_0; - wire [2 : 0] m_vrg_source_prio_0$D_IN; - wire m_vrg_source_prio_0$EN; - - // register m_vrg_source_prio_1 - reg [2 : 0] m_vrg_source_prio_1; - wire [2 : 0] m_vrg_source_prio_1$D_IN; - wire m_vrg_source_prio_1$EN; - - // register m_vrg_source_prio_10 - reg [2 : 0] m_vrg_source_prio_10; - wire [2 : 0] m_vrg_source_prio_10$D_IN; - wire m_vrg_source_prio_10$EN; - - // register m_vrg_source_prio_11 - reg [2 : 0] m_vrg_source_prio_11; - wire [2 : 0] m_vrg_source_prio_11$D_IN; - wire m_vrg_source_prio_11$EN; - - // register m_vrg_source_prio_12 - reg [2 : 0] m_vrg_source_prio_12; - wire [2 : 0] m_vrg_source_prio_12$D_IN; - wire m_vrg_source_prio_12$EN; - - // register m_vrg_source_prio_13 - reg [2 : 0] m_vrg_source_prio_13; - wire [2 : 0] m_vrg_source_prio_13$D_IN; - wire m_vrg_source_prio_13$EN; - - // register m_vrg_source_prio_14 - reg [2 : 0] m_vrg_source_prio_14; - wire [2 : 0] m_vrg_source_prio_14$D_IN; - wire m_vrg_source_prio_14$EN; - - // register m_vrg_source_prio_15 - reg [2 : 0] m_vrg_source_prio_15; - wire [2 : 0] m_vrg_source_prio_15$D_IN; - wire m_vrg_source_prio_15$EN; - - // register m_vrg_source_prio_16 - reg [2 : 0] m_vrg_source_prio_16; - wire [2 : 0] m_vrg_source_prio_16$D_IN; - wire m_vrg_source_prio_16$EN; - - // register m_vrg_source_prio_2 - reg [2 : 0] m_vrg_source_prio_2; - wire [2 : 0] m_vrg_source_prio_2$D_IN; - wire m_vrg_source_prio_2$EN; - - // register m_vrg_source_prio_3 - reg [2 : 0] m_vrg_source_prio_3; - wire [2 : 0] m_vrg_source_prio_3$D_IN; - wire m_vrg_source_prio_3$EN; - - // register m_vrg_source_prio_4 - reg [2 : 0] m_vrg_source_prio_4; - wire [2 : 0] m_vrg_source_prio_4$D_IN; - wire m_vrg_source_prio_4$EN; - - // register m_vrg_source_prio_5 - reg [2 : 0] m_vrg_source_prio_5; - wire [2 : 0] m_vrg_source_prio_5$D_IN; - wire m_vrg_source_prio_5$EN; - - // register m_vrg_source_prio_6 - reg [2 : 0] m_vrg_source_prio_6; - wire [2 : 0] m_vrg_source_prio_6$D_IN; - wire m_vrg_source_prio_6$EN; - - // register m_vrg_source_prio_7 - reg [2 : 0] m_vrg_source_prio_7; - wire [2 : 0] m_vrg_source_prio_7$D_IN; - wire m_vrg_source_prio_7$EN; - - // register m_vrg_source_prio_8 - reg [2 : 0] m_vrg_source_prio_8; - wire [2 : 0] m_vrg_source_prio_8$D_IN; - wire m_vrg_source_prio_8$EN; - - // register m_vrg_source_prio_9 - reg [2 : 0] m_vrg_source_prio_9; - wire [2 : 0] m_vrg_source_prio_9$D_IN; - wire m_vrg_source_prio_9$EN; - - // register m_vrg_target_threshold_0 - reg [2 : 0] m_vrg_target_threshold_0; - wire [2 : 0] m_vrg_target_threshold_0$D_IN; - wire m_vrg_target_threshold_0$EN; - - // register m_vrg_target_threshold_1 - reg [2 : 0] m_vrg_target_threshold_1; - wire [2 : 0] m_vrg_target_threshold_1$D_IN; - wire m_vrg_target_threshold_1$EN; - - // register m_vvrg_ie_0_0 - reg m_vvrg_ie_0_0; - wire m_vvrg_ie_0_0$D_IN, m_vvrg_ie_0_0$EN; - - // register m_vvrg_ie_0_1 - reg m_vvrg_ie_0_1; - wire m_vvrg_ie_0_1$D_IN, m_vvrg_ie_0_1$EN; - - // register m_vvrg_ie_0_10 - reg m_vvrg_ie_0_10; - wire m_vvrg_ie_0_10$D_IN, m_vvrg_ie_0_10$EN; - - // register m_vvrg_ie_0_11 - reg m_vvrg_ie_0_11; - wire m_vvrg_ie_0_11$D_IN, m_vvrg_ie_0_11$EN; - - // register m_vvrg_ie_0_12 - reg m_vvrg_ie_0_12; - wire m_vvrg_ie_0_12$D_IN, m_vvrg_ie_0_12$EN; - - // register m_vvrg_ie_0_13 - reg m_vvrg_ie_0_13; - wire m_vvrg_ie_0_13$D_IN, m_vvrg_ie_0_13$EN; - - // register m_vvrg_ie_0_14 - reg m_vvrg_ie_0_14; - wire m_vvrg_ie_0_14$D_IN, m_vvrg_ie_0_14$EN; - - // register m_vvrg_ie_0_15 - reg m_vvrg_ie_0_15; - wire m_vvrg_ie_0_15$D_IN, m_vvrg_ie_0_15$EN; - - // register m_vvrg_ie_0_16 - reg m_vvrg_ie_0_16; - wire m_vvrg_ie_0_16$D_IN, m_vvrg_ie_0_16$EN; - - // register m_vvrg_ie_0_2 - reg m_vvrg_ie_0_2; - wire m_vvrg_ie_0_2$D_IN, m_vvrg_ie_0_2$EN; - - // register m_vvrg_ie_0_3 - reg m_vvrg_ie_0_3; - wire m_vvrg_ie_0_3$D_IN, m_vvrg_ie_0_3$EN; - - // register m_vvrg_ie_0_4 - reg m_vvrg_ie_0_4; - wire m_vvrg_ie_0_4$D_IN, m_vvrg_ie_0_4$EN; - - // register m_vvrg_ie_0_5 - reg m_vvrg_ie_0_5; - wire m_vvrg_ie_0_5$D_IN, m_vvrg_ie_0_5$EN; - - // register m_vvrg_ie_0_6 - reg m_vvrg_ie_0_6; - wire m_vvrg_ie_0_6$D_IN, m_vvrg_ie_0_6$EN; - - // register m_vvrg_ie_0_7 - reg m_vvrg_ie_0_7; - wire m_vvrg_ie_0_7$D_IN, m_vvrg_ie_0_7$EN; - - // register m_vvrg_ie_0_8 - reg m_vvrg_ie_0_8; - wire m_vvrg_ie_0_8$D_IN, m_vvrg_ie_0_8$EN; - - // register m_vvrg_ie_0_9 - reg m_vvrg_ie_0_9; - wire m_vvrg_ie_0_9$D_IN, m_vvrg_ie_0_9$EN; - - // register m_vvrg_ie_1_0 - reg m_vvrg_ie_1_0; - wire m_vvrg_ie_1_0$D_IN, m_vvrg_ie_1_0$EN; - - // register m_vvrg_ie_1_1 - reg m_vvrg_ie_1_1; - wire m_vvrg_ie_1_1$D_IN, m_vvrg_ie_1_1$EN; - - // register m_vvrg_ie_1_10 - reg m_vvrg_ie_1_10; - wire m_vvrg_ie_1_10$D_IN, m_vvrg_ie_1_10$EN; - - // register m_vvrg_ie_1_11 - reg m_vvrg_ie_1_11; - wire m_vvrg_ie_1_11$D_IN, m_vvrg_ie_1_11$EN; - - // register m_vvrg_ie_1_12 - reg m_vvrg_ie_1_12; - wire m_vvrg_ie_1_12$D_IN, m_vvrg_ie_1_12$EN; - - // register m_vvrg_ie_1_13 - reg m_vvrg_ie_1_13; - wire m_vvrg_ie_1_13$D_IN, m_vvrg_ie_1_13$EN; - - // register m_vvrg_ie_1_14 - reg m_vvrg_ie_1_14; - wire m_vvrg_ie_1_14$D_IN, m_vvrg_ie_1_14$EN; - - // register m_vvrg_ie_1_15 - reg m_vvrg_ie_1_15; - wire m_vvrg_ie_1_15$D_IN, m_vvrg_ie_1_15$EN; - - // register m_vvrg_ie_1_16 - reg m_vvrg_ie_1_16; - wire m_vvrg_ie_1_16$D_IN, m_vvrg_ie_1_16$EN; - - // register m_vvrg_ie_1_2 - reg m_vvrg_ie_1_2; - wire m_vvrg_ie_1_2$D_IN, m_vvrg_ie_1_2$EN; - - // register m_vvrg_ie_1_3 - reg m_vvrg_ie_1_3; - wire m_vvrg_ie_1_3$D_IN, m_vvrg_ie_1_3$EN; - - // register m_vvrg_ie_1_4 - reg m_vvrg_ie_1_4; - wire m_vvrg_ie_1_4$D_IN, m_vvrg_ie_1_4$EN; - - // register m_vvrg_ie_1_5 - reg m_vvrg_ie_1_5; - wire m_vvrg_ie_1_5$D_IN, m_vvrg_ie_1_5$EN; - - // register m_vvrg_ie_1_6 - reg m_vvrg_ie_1_6; - wire m_vvrg_ie_1_6$D_IN, m_vvrg_ie_1_6$EN; - - // register m_vvrg_ie_1_7 - reg m_vvrg_ie_1_7; - wire m_vvrg_ie_1_7$D_IN, m_vvrg_ie_1_7$EN; - - // register m_vvrg_ie_1_8 - reg m_vvrg_ie_1_8; - wire m_vvrg_ie_1_8$D_IN, m_vvrg_ie_1_8$EN; - - // register m_vvrg_ie_1_9 - reg m_vvrg_ie_1_9; - wire m_vvrg_ie_1_9$D_IN, m_vvrg_ie_1_9$EN; - - // ports of submodule m_f_reset_reqs - wire m_f_reset_reqs$CLR, - m_f_reset_reqs$DEQ, - m_f_reset_reqs$EMPTY_N, - m_f_reset_reqs$ENQ, - m_f_reset_reqs$FULL_N; - - // ports of submodule m_f_reset_rsps - wire m_f_reset_rsps$CLR, - m_f_reset_rsps$DEQ, - m_f_reset_rsps$EMPTY_N, - m_f_reset_rsps$ENQ, - m_f_reset_rsps$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_addr - wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT; - wire m_slave_xactor_f_rd_addr$CLR, - m_slave_xactor_f_rd_addr$DEQ, - m_slave_xactor_f_rd_addr$EMPTY_N, - m_slave_xactor_f_rd_addr$ENQ, - m_slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_data - wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT; - wire m_slave_xactor_f_rd_data$CLR, - m_slave_xactor_f_rd_data$DEQ, - m_slave_xactor_f_rd_data$EMPTY_N, - m_slave_xactor_f_rd_data$ENQ, - m_slave_xactor_f_rd_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_addr - wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT; - wire m_slave_xactor_f_wr_addr$CLR, - m_slave_xactor_f_wr_addr$DEQ, - m_slave_xactor_f_wr_addr$EMPTY_N, - m_slave_xactor_f_wr_addr$ENQ, - m_slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_data - wire [76 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; - wire m_slave_xactor_f_wr_data$CLR, - m_slave_xactor_f_wr_data$DEQ, - m_slave_xactor_f_wr_data$EMPTY_N, - m_slave_xactor_f_wr_data$ENQ, - m_slave_xactor_f_wr_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_resp - wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT; - wire m_slave_xactor_f_wr_resp$CLR, - m_slave_xactor_f_wr_resp$DEQ, - m_slave_xactor_f_wr_resp$EMPTY_N, - m_slave_xactor_f_wr_resp$ENQ, - m_slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_m_rl_process_rd_req, - CAN_FIRE_RL_m_rl_process_wr_req, - CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_set_verbosity, - CAN_FIRE_show_PLIC_state, - CAN_FIRE_v_sources_0_m_interrupt_req, - CAN_FIRE_v_sources_10_m_interrupt_req, - CAN_FIRE_v_sources_11_m_interrupt_req, - CAN_FIRE_v_sources_12_m_interrupt_req, - CAN_FIRE_v_sources_13_m_interrupt_req, - CAN_FIRE_v_sources_14_m_interrupt_req, - CAN_FIRE_v_sources_15_m_interrupt_req, - CAN_FIRE_v_sources_1_m_interrupt_req, - CAN_FIRE_v_sources_2_m_interrupt_req, - CAN_FIRE_v_sources_3_m_interrupt_req, - CAN_FIRE_v_sources_4_m_interrupt_req, - CAN_FIRE_v_sources_5_m_interrupt_req, - CAN_FIRE_v_sources_6_m_interrupt_req, - CAN_FIRE_v_sources_7_m_interrupt_req, - CAN_FIRE_v_sources_8_m_interrupt_req, - CAN_FIRE_v_sources_9_m_interrupt_req, - WILL_FIRE_RL_m_rl_process_rd_req, - WILL_FIRE_RL_m_rl_process_wr_req, - WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_set_verbosity, - WILL_FIRE_show_PLIC_state, - WILL_FIRE_v_sources_0_m_interrupt_req, - WILL_FIRE_v_sources_10_m_interrupt_req, - WILL_FIRE_v_sources_11_m_interrupt_req, - WILL_FIRE_v_sources_12_m_interrupt_req, - WILL_FIRE_v_sources_13_m_interrupt_req, - WILL_FIRE_v_sources_14_m_interrupt_req, - WILL_FIRE_v_sources_15_m_interrupt_req, - WILL_FIRE_v_sources_1_m_interrupt_req, - WILL_FIRE_v_sources_2_m_interrupt_req, - WILL_FIRE_v_sources_3_m_interrupt_req, - WILL_FIRE_v_sources_4_m_interrupt_req, - WILL_FIRE_v_sources_5_m_interrupt_req, - WILL_FIRE_v_sources_6_m_interrupt_req, - WILL_FIRE_v_sources_7_m_interrupt_req, - WILL_FIRE_v_sources_8_m_interrupt_req, - WILL_FIRE_v_sources_9_m_interrupt_req; - - // inputs to muxes for submodule ports - wire MUX_m_vrg_servicing_source_0$write_1__SEL_1, - MUX_m_vrg_servicing_source_1$write_1__SEL_1, - MUX_m_vrg_source_busy_0$write_1__SEL_2, - MUX_m_vrg_source_busy_1$write_1__SEL_1, - MUX_m_vrg_source_busy_1$write_1__SEL_2, - MUX_m_vrg_source_busy_10$write_1__SEL_1, - MUX_m_vrg_source_busy_10$write_1__SEL_2, - MUX_m_vrg_source_busy_11$write_1__SEL_1, - MUX_m_vrg_source_busy_11$write_1__SEL_2, - MUX_m_vrg_source_busy_12$write_1__SEL_1, - MUX_m_vrg_source_busy_12$write_1__SEL_2, - MUX_m_vrg_source_busy_13$write_1__SEL_1, - MUX_m_vrg_source_busy_13$write_1__SEL_2, - MUX_m_vrg_source_busy_14$write_1__SEL_1, - MUX_m_vrg_source_busy_14$write_1__SEL_2, - MUX_m_vrg_source_busy_15$write_1__SEL_1, - MUX_m_vrg_source_busy_15$write_1__SEL_2, - MUX_m_vrg_source_busy_16$write_1__SEL_1, - MUX_m_vrg_source_busy_16$write_1__SEL_2, - MUX_m_vrg_source_busy_2$write_1__SEL_1, - MUX_m_vrg_source_busy_2$write_1__SEL_2, - MUX_m_vrg_source_busy_3$write_1__SEL_1, - MUX_m_vrg_source_busy_3$write_1__SEL_2, - MUX_m_vrg_source_busy_4$write_1__SEL_1, - MUX_m_vrg_source_busy_4$write_1__SEL_2, - MUX_m_vrg_source_busy_5$write_1__SEL_1, - MUX_m_vrg_source_busy_5$write_1__SEL_2, - MUX_m_vrg_source_busy_6$write_1__SEL_1, - MUX_m_vrg_source_busy_6$write_1__SEL_2, - MUX_m_vrg_source_busy_7$write_1__SEL_1, - MUX_m_vrg_source_busy_7$write_1__SEL_2, - MUX_m_vrg_source_busy_8$write_1__SEL_1, - MUX_m_vrg_source_busy_8$write_1__SEL_2, - MUX_m_vrg_source_busy_9$write_1__SEL_1, - MUX_m_vrg_source_busy_9$write_1__SEL_2, - MUX_m_vrg_source_prio_0$write_1__SEL_1, - MUX_m_vrg_source_prio_1$write_1__SEL_1, - MUX_m_vrg_source_prio_10$write_1__SEL_1, - MUX_m_vrg_source_prio_11$write_1__SEL_1, - MUX_m_vrg_source_prio_12$write_1__SEL_1, - MUX_m_vrg_source_prio_13$write_1__SEL_1, - MUX_m_vrg_source_prio_14$write_1__SEL_1, - MUX_m_vrg_source_prio_15$write_1__SEL_1, - MUX_m_vrg_source_prio_16$write_1__SEL_1, - MUX_m_vrg_source_prio_2$write_1__SEL_1, - MUX_m_vrg_source_prio_3$write_1__SEL_1, - MUX_m_vrg_source_prio_4$write_1__SEL_1, - MUX_m_vrg_source_prio_5$write_1__SEL_1, - MUX_m_vrg_source_prio_6$write_1__SEL_1, - MUX_m_vrg_source_prio_7$write_1__SEL_1, - MUX_m_vrg_source_prio_8$write_1__SEL_1, - MUX_m_vrg_source_prio_9$write_1__SEL_1, - MUX_m_vrg_target_threshold_0$write_1__SEL_1, - MUX_m_vrg_target_threshold_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__SEL_1, - MUX_m_vvrg_ie_0_0$write_1__VAL_1, - MUX_m_vvrg_ie_0_1$write_1__SEL_1, - MUX_m_vvrg_ie_0_1$write_1__VAL_1, - MUX_m_vvrg_ie_0_10$write_1__SEL_1, - MUX_m_vvrg_ie_0_10$write_1__VAL_1, - MUX_m_vvrg_ie_0_11$write_1__SEL_1, - MUX_m_vvrg_ie_0_11$write_1__VAL_1, - MUX_m_vvrg_ie_0_12$write_1__SEL_1, - MUX_m_vvrg_ie_0_12$write_1__VAL_1, - MUX_m_vvrg_ie_0_13$write_1__SEL_1, - MUX_m_vvrg_ie_0_13$write_1__VAL_1, - MUX_m_vvrg_ie_0_14$write_1__SEL_1, - MUX_m_vvrg_ie_0_14$write_1__VAL_1, - MUX_m_vvrg_ie_0_15$write_1__SEL_1, - MUX_m_vvrg_ie_0_15$write_1__VAL_1, - MUX_m_vvrg_ie_0_16$write_1__SEL_1, - MUX_m_vvrg_ie_0_16$write_1__VAL_1, - MUX_m_vvrg_ie_0_2$write_1__SEL_1, - MUX_m_vvrg_ie_0_2$write_1__VAL_1, - MUX_m_vvrg_ie_0_3$write_1__SEL_1, - MUX_m_vvrg_ie_0_3$write_1__VAL_1, - MUX_m_vvrg_ie_0_4$write_1__SEL_1, - MUX_m_vvrg_ie_0_4$write_1__VAL_1, - MUX_m_vvrg_ie_0_5$write_1__SEL_1, - MUX_m_vvrg_ie_0_5$write_1__VAL_1, - MUX_m_vvrg_ie_0_6$write_1__SEL_1, - MUX_m_vvrg_ie_0_6$write_1__VAL_1, - MUX_m_vvrg_ie_0_7$write_1__SEL_1, - MUX_m_vvrg_ie_0_7$write_1__VAL_1, - MUX_m_vvrg_ie_0_8$write_1__SEL_1, - MUX_m_vvrg_ie_0_8$write_1__VAL_1, - MUX_m_vvrg_ie_0_9$write_1__SEL_1, - MUX_m_vvrg_ie_0_9$write_1__VAL_1, - MUX_m_vvrg_ie_1_0$write_1__SEL_1, - MUX_m_vvrg_ie_1_0$write_1__VAL_1, - MUX_m_vvrg_ie_1_1$write_1__SEL_1, - MUX_m_vvrg_ie_1_1$write_1__VAL_1, - MUX_m_vvrg_ie_1_10$write_1__SEL_1, - MUX_m_vvrg_ie_1_10$write_1__VAL_1, - MUX_m_vvrg_ie_1_11$write_1__SEL_1, - MUX_m_vvrg_ie_1_11$write_1__VAL_1, - MUX_m_vvrg_ie_1_12$write_1__SEL_1, - MUX_m_vvrg_ie_1_12$write_1__VAL_1, - MUX_m_vvrg_ie_1_13$write_1__SEL_1, - MUX_m_vvrg_ie_1_13$write_1__VAL_1, - MUX_m_vvrg_ie_1_14$write_1__SEL_1, - MUX_m_vvrg_ie_1_14$write_1__VAL_1, - MUX_m_vvrg_ie_1_15$write_1__SEL_1, - MUX_m_vvrg_ie_1_15$write_1__VAL_1, - MUX_m_vvrg_ie_1_16$write_1__SEL_1, - MUX_m_vvrg_ie_1_16$write_1__VAL_1, - MUX_m_vvrg_ie_1_2$write_1__SEL_1, - MUX_m_vvrg_ie_1_2$write_1__VAL_1, - MUX_m_vvrg_ie_1_3$write_1__SEL_1, - MUX_m_vvrg_ie_1_3$write_1__VAL_1, - MUX_m_vvrg_ie_1_4$write_1__SEL_1, - MUX_m_vvrg_ie_1_4$write_1__VAL_1, - MUX_m_vvrg_ie_1_5$write_1__SEL_1, - MUX_m_vvrg_ie_1_5$write_1__VAL_1, - MUX_m_vvrg_ie_1_6$write_1__SEL_1, - MUX_m_vvrg_ie_1_6$write_1__VAL_1, - MUX_m_vvrg_ie_1_7$write_1__SEL_1, - MUX_m_vvrg_ie_1_7$write_1__VAL_1, - MUX_m_vvrg_ie_1_8$write_1__SEL_1, - MUX_m_vvrg_ie_1_8$write_1__VAL_1, - MUX_m_vvrg_ie_1_9$write_1__SEL_1, - MUX_m_vvrg_ie_1_9$write_1__VAL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h75676; - reg [31 : 0] v__h75874; - reg [31 : 0] v__h76072; - reg [31 : 0] v__h76270; - reg [31 : 0] v__h76468; - reg [31 : 0] v__h76666; - reg [31 : 0] v__h76864; - reg [31 : 0] v__h77062; - reg [31 : 0] v__h77260; - reg [31 : 0] v__h77458; - reg [31 : 0] v__h77656; - reg [31 : 0] v__h77854; - reg [31 : 0] v__h78052; - reg [31 : 0] v__h78250; - reg [31 : 0] v__h78448; - reg [31 : 0] v__h78646; - reg [31 : 0] v__h6144; - reg [31 : 0] v__h13080; - reg [31 : 0] v__h13265; - reg [31 : 0] v__h13463; - reg [31 : 0] v__h13713; - reg [31 : 0] v__h18186; - reg [31 : 0] v__h23802; - reg [31 : 0] v__h25975; - reg [31 : 0] v__h24056; - reg [31 : 0] v__h26250; - reg [31 : 0] v__h26463; - reg [31 : 0] v__h26740; - reg [31 : 0] v__h26968; - reg [31 : 0] v__h27865; - reg [31 : 0] v__h28048; - reg [31 : 0] v__h67030; - reg [31 : 0] v__h67318; - reg [31 : 0] v__h67847; - reg [31 : 0] v__h67933; - reg [31 : 0] v__h68132; - reg [31 : 0] v__h68353; - reg [31 : 0] v__h74690; - reg [31 : 0] v__h74800; - reg [31 : 0] v__h74913; - reg [31 : 0] v__h6138; - reg [31 : 0] v__h13074; - reg [31 : 0] v__h13259; - reg [31 : 0] v__h13457; - reg [31 : 0] v__h13707; - reg [31 : 0] v__h18180; - reg [31 : 0] v__h23796; - reg [31 : 0] v__h24050; - reg [31 : 0] v__h25969; - reg [31 : 0] v__h26244; - reg [31 : 0] v__h26457; - reg [31 : 0] v__h26734; - reg [31 : 0] v__h26962; - reg [31 : 0] v__h27859; - reg [31 : 0] v__h28042; - reg [31 : 0] v__h67024; - reg [31 : 0] v__h67312; - reg [31 : 0] v__h67841; - reg [31 : 0] v__h67927; - reg [31 : 0] v__h68126; - reg [31 : 0] v__h68347; - reg [31 : 0] v__h74684; - reg [31 : 0] v__h74794; - reg [31 : 0] v__h74907; - reg [31 : 0] v__h75670; - reg [31 : 0] v__h75868; - reg [31 : 0] v__h76066; - reg [31 : 0] v__h76264; - reg [31 : 0] v__h76462; - reg [31 : 0] v__h76660; - reg [31 : 0] v__h76858; - reg [31 : 0] v__h77056; - reg [31 : 0] v__h77254; - reg [31 : 0] v__h77452; - reg [31 : 0] v__h77650; - reg [31 : 0] v__h77848; - reg [31 : 0] v__h78046; - reg [31 : 0] v__h78244; - reg [31 : 0] v__h78442; - reg [31 : 0] v__h78640; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] y_avValue_fst__h26148; - reg [4 : 0] x__h24011, x__h67487; - reg [2 : 0] x__h13493, x__h23832; - reg [1 : 0] v__h67107, y_avValue_snd__h26149; - reg CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - wire [63 : 0] addr_offset__h13216, - addr_offset__h26929, - rdata___1__h26404, - rdata__h26202, - v__h13422, - v__h13671, - v__h18144, - v__h23761, - v__h25455, - v__h25474, - x__h26361, - y_avValue_fst__h26094, - y_avValue_fst__h26115, - y_avValue_fst__h26127, - y_avValue_fst__h26143, - y_avValue_fst__h26159, - y_avValue_fst__h26164, - y_avValue_fst__h26175, - y_avValue_fst__h26180, - y_avValue_fst__h26194; - wire [31 : 0] v_ie__h18147, - v_ip__h13674, - wdata32__h26930, - x__h23673, - x__h67110; - wire [9 : 0] source_id__h15665, - source_id__h15772, - source_id__h15845, - source_id__h15918, - source_id__h15991, - source_id__h16064, - source_id__h16137, - source_id__h16210, - source_id__h16283, - source_id__h16356, - source_id__h16429, - source_id__h16502, - source_id__h16575, - source_id__h16648, - source_id__h16721, - source_id__h16794, - source_id__h16867, - source_id__h16940, - source_id__h17013, - source_id__h17086, - source_id__h17159, - source_id__h17232, - source_id__h17305, - source_id__h17378, - source_id__h17451, - source_id__h17524, - source_id__h17597, - source_id__h17670, - source_id__h17743, - source_id__h17816, - source_id__h17889, - source_id__h20137, - source_id__h20313, - source_id__h20421, - source_id__h20529, - source_id__h20637, - source_id__h20745, - source_id__h20853, - source_id__h20961, - source_id__h21069, - source_id__h21177, - source_id__h21285, - source_id__h21393, - source_id__h21501, - source_id__h21609, - source_id__h21717, - source_id__h21825, - source_id__h21933, - source_id__h22041, - source_id__h22149, - source_id__h22257, - source_id__h22365, - source_id__h22473, - source_id__h22581, - source_id__h22689, - source_id__h22797, - source_id__h22905, - source_id__h23013, - source_id__h23121, - source_id__h23229, - source_id__h23337, - source_id__h23445, - source_id__h29475, - source_id__h30685, - source_id__h31895, - source_id__h33105, - source_id__h34315, - source_id__h35525, - source_id__h36735, - source_id__h37945, - source_id__h39155, - source_id__h40365, - source_id__h41575, - source_id__h42785, - source_id__h43995, - source_id__h45205, - source_id__h46415, - source_id__h47625, - source_id__h48835, - source_id__h50045, - source_id__h51255, - source_id__h52465, - source_id__h53675, - source_id__h54885, - source_id__h56095, - source_id__h57305, - source_id__h58515, - source_id__h59725, - source_id__h60935, - source_id__h62145, - source_id__h63355, - source_id__h64565, - source_id__h65775, - source_id__h67436, - source_id_base__h13630, - source_id_base__h28148; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71313, - b__h73318, - max_id__h23959; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71312, - a__h73317; - wire [1 : 0] rresp__h26203, - v__h26934, - v__h27094, - v__h27107, - v__h27942, - v__h27961, - v__h28125, - v__h28144, - v__h67144, - v__h67432, - v__h67476, - y_avValue_snd__h26095, - y_avValue_snd__h26116, - y_avValue_snd__h26128, - y_avValue_snd__h26144, - y_avValue_snd__h26160, - y_avValue_snd__h26165, - y_avValue_snd__h26176, - y_avValue_snd__h26181, - y_avValue_snd__h26195; - wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991, - NOT_m_cfg_verbosity_read_ULE_1_5___d16, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982, - NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313, - NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321, - NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329, - NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337, - NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345, - NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353, - NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361, - NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242, - NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249, - NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257, - NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265, - NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273, - NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281, - NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289, - NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297, - NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305, - _dfoo1, - _dfoo10, - _dfoo100, - _dfoo1000, - _dfoo1001, - _dfoo1002, - _dfoo1003, - _dfoo1004, - _dfoo1005, - _dfoo1006, - _dfoo1007, - _dfoo1008, - _dfoo1009, - _dfoo1010, - _dfoo1011, - _dfoo1012, - _dfoo1013, - _dfoo1014, - _dfoo1015, - _dfoo1016, - _dfoo1017, - _dfoo1018, - _dfoo1019, - _dfoo102, - _dfoo1020, - _dfoo1022, - _dfoo1024, - _dfoo1026, - _dfoo1028, - _dfoo1030, - _dfoo1032, - _dfoo1034, - _dfoo1036, - _dfoo1038, - _dfoo104, - _dfoo1040, - _dfoo1042, - _dfoo1044, - _dfoo1046, - _dfoo1048, - _dfoo1050, - _dfoo1052, - _dfoo1054, - _dfoo1056, - _dfoo1058, - _dfoo106, - _dfoo1060, - _dfoo1062, - _dfoo1064, - _dfoo1066, - _dfoo1068, - _dfoo1070, - _dfoo1072, - _dfoo1074, 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_dfoo1154, - _dfoo1155, - _dfoo1156, - _dfoo1158, - _dfoo116, - _dfoo1160, - _dfoo1162, - _dfoo1164, - _dfoo1166, - _dfoo1168, - _dfoo1170, - _dfoo1172, - _dfoo1174, - _dfoo1176, - _dfoo1178, - _dfoo118, - _dfoo1180, - _dfoo1182, - _dfoo1184, - _dfoo1186, - _dfoo1188, - _dfoo1190, - _dfoo1192, - _dfoo1194, - _dfoo1196, - _dfoo1198, - _dfoo12, - _dfoo120, - _dfoo1200, - _dfoo1202, - _dfoo1204, - _dfoo1206, - _dfoo1208, - _dfoo1210, - _dfoo1212, - _dfoo1214, - _dfoo1216, - _dfoo1218, - _dfoo122, - _dfoo1220, - _dfoo1222, - _dfoo1224, - _dfoo1225, - _dfoo1226, - _dfoo1227, - _dfoo1228, - _dfoo1229, - _dfoo1230, - _dfoo1231, - _dfoo1232, - _dfoo1233, - _dfoo1234, - _dfoo1235, - _dfoo1236, - _dfoo1237, - _dfoo1238, - _dfoo1239, - _dfoo124, - _dfoo1240, - _dfoo1241, - _dfoo1242, - _dfoo1243, - _dfoo1244, - _dfoo1245, - _dfoo1246, - _dfoo1247, - _dfoo1248, - _dfoo1249, - _dfoo1250, - _dfoo1251, - _dfoo1252, - _dfoo1253, - _dfoo1254, - _dfoo1255, - _dfoo1256, - _dfoo1257, - _dfoo1258, - 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_dfoo1363, - _dfoo1364, - _dfoo1365, - _dfoo1366, - _dfoo1367, - _dfoo1368, - _dfoo1369, - _dfoo137, - _dfoo1370, - _dfoo1371, - _dfoo1372, - _dfoo1373, - _dfoo1374, - _dfoo1375, - _dfoo1376, - _dfoo1377, - _dfoo1378, - _dfoo1379, - _dfoo138, - _dfoo1380, - _dfoo1381, - _dfoo1382, - _dfoo1383, - _dfoo1384, - _dfoo1385, - _dfoo1386, - _dfoo1387, - _dfoo1388, - _dfoo1389, - _dfoo139, - _dfoo1390, - _dfoo1391, - _dfoo1392, - _dfoo1393, - _dfoo1394, - _dfoo1395, - _dfoo1396, - _dfoo1397, - _dfoo1398, - _dfoo1399, - _dfoo14, - _dfoo140, - _dfoo1400, - _dfoo1401, - _dfoo1402, - _dfoo1403, - _dfoo1404, - _dfoo1405, - _dfoo1406, - _dfoo1407, - _dfoo1408, - _dfoo1409, - _dfoo141, - _dfoo1410, - _dfoo1411, - _dfoo1412, - _dfoo1413, - _dfoo1414, - _dfoo1415, - _dfoo1416, - _dfoo1417, - _dfoo1418, - _dfoo1419, - _dfoo142, - _dfoo1420, - _dfoo1421, - _dfoo1422, - _dfoo1423, - _dfoo1424, - _dfoo1425, - _dfoo1426, - _dfoo1427, - _dfoo1428, - _dfoo143, - _dfoo1430, - _dfoo1432, - _dfoo1434, - _dfoo1436, - _dfoo1438, - _dfoo144, - _dfoo1440, - _dfoo1442, - _dfoo1444, - _dfoo1446, - _dfoo1448, - _dfoo145, - _dfoo1450, - _dfoo1452, - _dfoo1454, - _dfoo1456, - _dfoo1458, - _dfoo146, - _dfoo1460, - _dfoo1462, - _dfoo1464, - _dfoo1466, - _dfoo1468, - _dfoo147, - _dfoo1470, - _dfoo1472, - _dfoo1474, - _dfoo1476, - _dfoo1478, - _dfoo148, - _dfoo1480, - _dfoo1482, - _dfoo1484, - _dfoo1486, - _dfoo1488, - _dfoo149, - _dfoo1490, - _dfoo1492, - _dfoo1494, - _dfoo1496, - _dfoo1497, - _dfoo1498, - _dfoo1499, - _dfoo15, - _dfoo150, - _dfoo1500, - _dfoo1501, - _dfoo1502, - _dfoo1503, - _dfoo1504, - _dfoo1505, - _dfoo1506, - _dfoo1507, - _dfoo1508, - _dfoo1509, - _dfoo151, - _dfoo1510, - _dfoo1511, - _dfoo1512, - _dfoo1513, - _dfoo1514, - _dfoo1515, - _dfoo1516, - _dfoo1517, - _dfoo1518, - _dfoo1519, - _dfoo152, - _dfoo1520, - _dfoo1521, - _dfoo1522, - _dfoo1523, - _dfoo1524, - _dfoo1525, - _dfoo1526, - _dfoo1527, - _dfoo1528, - _dfoo1529, - _dfoo153, - _dfoo1530, - _dfoo1531, - _dfoo1532, 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m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, - m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method show_PLIC_state - assign RDY_show_PLIC_state = 1'd1 ; - assign CAN_FIRE_show_PLIC_state = 1'd1 ; - assign WILL_FIRE_show_PLIC_state = EN_show_PLIC_state ; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = m_f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = m_f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; - - // value method axi4_slave_m_awready - assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ; - - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; - - // value method axi4_slave_m_wready - assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ; - - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ; - - // value method axi4_slave_m_bid - assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; - - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; - - // value method axi4_slave_m_arready - assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ; - - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ; - - // value method axi4_slave_m_rid - assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ; - - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; - - // action method v_sources_0_m_interrupt_req - assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; - - // action method v_sources_1_m_interrupt_req - assign CAN_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_1_m_interrupt_req = 1'd1 ; - - // action method v_sources_2_m_interrupt_req - assign CAN_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_2_m_interrupt_req = 1'd1 ; - - // action method v_sources_3_m_interrupt_req - assign CAN_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_3_m_interrupt_req = 1'd1 ; - - // action method v_sources_4_m_interrupt_req - assign CAN_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_4_m_interrupt_req = 1'd1 ; - - // action method v_sources_5_m_interrupt_req - assign CAN_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_5_m_interrupt_req = 1'd1 ; - - // action method v_sources_6_m_interrupt_req - assign CAN_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_6_m_interrupt_req = 1'd1 ; - - // action method v_sources_7_m_interrupt_req - assign CAN_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_7_m_interrupt_req = 1'd1 ; - - // action method v_sources_8_m_interrupt_req - assign CAN_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_8_m_interrupt_req = 1'd1 ; - - // action method v_sources_9_m_interrupt_req - assign CAN_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_9_m_interrupt_req = 1'd1 ; - - // action method v_sources_10_m_interrupt_req - assign CAN_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_10_m_interrupt_req = 1'd1 ; - - // action method v_sources_11_m_interrupt_req - assign CAN_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_11_m_interrupt_req = 1'd1 ; - - // action method v_sources_12_m_interrupt_req - assign CAN_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_12_m_interrupt_req = 1'd1 ; - - // action method v_sources_13_m_interrupt_req - assign CAN_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_13_m_interrupt_req = 1'd1 ; - - // action method v_sources_14_m_interrupt_req - assign CAN_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_14_m_interrupt_req = 1'd1 ; - - // action method v_sources_15_m_interrupt_req - assign CAN_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; - - // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71312 > m_vrg_target_threshold_0 ; - - // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73317 > m_vrg_target_threshold_1 ; - - // submodule m_f_reset_reqs - FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_reqs$ENQ), - .DEQ(m_f_reset_reqs$DEQ), - .CLR(m_f_reset_reqs$CLR), - .FULL_N(m_f_reset_reqs$FULL_N), - .EMPTY_N(m_f_reset_reqs$EMPTY_N)); - - // submodule m_f_reset_rsps - FIFO20 #(.guarded(32'd1)) m_f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(m_f_reset_rsps$ENQ), - .DEQ(m_f_reset_rsps$DEQ), - .CLR(m_f_reset_rsps$CLR), - .FULL_N(m_f_reset_rsps$FULL_N), - .EMPTY_N(m_f_reset_rsps$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_addr$D_IN), - .ENQ(m_slave_xactor_f_rd_addr$ENQ), - .DEQ(m_slave_xactor_f_rd_addr$DEQ), - .CLR(m_slave_xactor_f_rd_addr$CLR), - .D_OUT(m_slave_xactor_f_rd_addr$D_OUT), - .FULL_N(m_slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_data$D_IN), - .ENQ(m_slave_xactor_f_rd_data$ENQ), - .DEQ(m_slave_xactor_f_rd_data$DEQ), - .CLR(m_slave_xactor_f_rd_data$CLR), - .D_OUT(m_slave_xactor_f_rd_data$D_OUT), - .FULL_N(m_slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_addr$D_IN), - .ENQ(m_slave_xactor_f_wr_addr$ENQ), - .DEQ(m_slave_xactor_f_wr_addr$DEQ), - .CLR(m_slave_xactor_f_wr_addr$CLR), - .D_OUT(m_slave_xactor_f_wr_addr$D_OUT), - .FULL_N(m_slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_data$D_IN), - .ENQ(m_slave_xactor_f_wr_data$ENQ), - .DEQ(m_slave_xactor_f_wr_data$DEQ), - .CLR(m_slave_xactor_f_wr_data$CLR), - .D_OUT(m_slave_xactor_f_wr_data$D_OUT), - .FULL_N(m_slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_resp$D_IN), - .ENQ(m_slave_xactor_f_wr_resp$ENQ), - .DEQ(m_slave_xactor_f_wr_resp$DEQ), - .CLR(m_slave_xactor_f_wr_resp$CLR), - .D_OUT(m_slave_xactor_f_wr_resp$D_OUT), - .FULL_N(m_slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_m_rl_reset - assign CAN_FIRE_RL_m_rl_reset = - m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; - - // rule RL_m_rl_process_rd_req - assign CAN_FIRE_RL_m_rl_process_rd_req = - m_slave_xactor_f_rd_addr$EMPTY_N && - m_slave_xactor_f_rd_data$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; - - // rule RL_m_rl_process_wr_req - assign CAN_FIRE_RL_m_rl_process_wr_req = - m_slave_xactor_f_wr_addr$EMPTY_N && - m_slave_xactor_f_wr_data$EMPTY_N && - m_slave_xactor_f_wr_resp$FULL_N && - !m_f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_m_rl_process_wr_req = - CAN_FIRE_RL_m_rl_process_wr_req && - !WILL_FIRE_RL_m_rl_process_rd_req ; - - // inputs to muxes for submodule ports - assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; - assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 ; - assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 ; - assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 ; - assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 ; - assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 ; - assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 ; - assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 ; - assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 ; - assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 ; - assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 ; - assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 ; - assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 ; - assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 ; - assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 ; - assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 ; - assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 ; - assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 ; - assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 ; - assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 ; - assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 ; - assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; - assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ; - assign MUX_m_vvrg_ie_0_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ; - assign MUX_m_vvrg_ie_0_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ; - assign MUX_m_vvrg_ie_0_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ; - assign MUX_m_vvrg_ie_0_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ; - assign MUX_m_vvrg_ie_0_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ; - assign MUX_m_vvrg_ie_0_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ; - assign MUX_m_vvrg_ie_0_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ; - assign MUX_m_vvrg_ie_0_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ; - assign MUX_m_vvrg_ie_0_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ; - assign MUX_m_vvrg_ie_0_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ; - assign MUX_m_vvrg_ie_0_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ; - assign MUX_m_vvrg_ie_0_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ; - assign MUX_m_vvrg_ie_0_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ; - assign MUX_m_vvrg_ie_0_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ; - assign MUX_m_vvrg_ie_0_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ; - assign MUX_m_vvrg_ie_1_0$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ; - assign MUX_m_vvrg_ie_1_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ; - assign MUX_m_vvrg_ie_1_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ; - assign MUX_m_vvrg_ie_1_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ; - assign MUX_m_vvrg_ie_1_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ; - assign MUX_m_vvrg_ie_1_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ; - assign MUX_m_vvrg_ie_1_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ; - assign MUX_m_vvrg_ie_1_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ; - assign MUX_m_vvrg_ie_1_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ; - assign MUX_m_vvrg_ie_1_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ; - assign MUX_m_vvrg_ie_1_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ; - assign MUX_m_vvrg_ie_1_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ; - assign MUX_m_vvrg_ie_1_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ; - assign MUX_m_vvrg_ie_1_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ; - assign MUX_m_vvrg_ie_1_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ; - assign MUX_m_vvrg_ie_1_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ; - assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; - assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2040 ; - assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2038 ; - assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2020 ; - assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2018 ; - assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2016 ; - assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2014 ; - assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2012 ; - assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2010 ; - assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2008 ; - assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2036 ; - assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2034 ; - assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2032 ; - assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2030 ; - assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2028 ; - assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2026 ; - assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2024 ; - assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921) ? - wdata32__h26930[0] : - _dfoo2022 ; - assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2006 ; - assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2004 ; - assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1986 ; - assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1984 ; - assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1982 ; - assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1980 ; - assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1978 ; - assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1976 ; - assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1974 ; - assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2002 ; - assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo2000 ; - assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1998 ; - assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1996 ; - assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1994 ; - assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1992 ; - assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1990 ; - assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957) ? - wdata32__h26930[0] : - _dfoo1988 ; - - // register m_cfg_verbosity - assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign m_cfg_verbosity$EN = EN_set_verbosity ; - - // register m_rg_addr_base - assign m_rg_addr_base$D_IN = set_addr_map_addr_base ; - assign m_rg_addr_base$EN = EN_set_addr_map ; - - // register m_rg_addr_lim - assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign m_rg_addr_lim$EN = EN_set_addr_map ; - - // register m_vrg_servicing_source_0 - assign m_vrg_servicing_source_0$D_IN = - MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_servicing_source_1 - assign m_vrg_servicing_source_1$D_IN = - MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h23959 : - 5'd0 ; - assign m_vrg_servicing_source_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13216[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_0 - assign m_vrg_source_busy_0$D_IN = - !MUX_m_vrg_source_busy_0$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_1 - assign m_vrg_source_busy_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_10 - assign m_vrg_source_busy_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_11 - assign m_vrg_source_busy_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_12 - assign m_vrg_source_busy_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_13 - assign m_vrg_source_busy_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_14 - assign m_vrg_source_busy_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_15 - assign m_vrg_source_busy_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_16 - assign m_vrg_source_busy_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67436 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_2 - assign m_vrg_source_busy_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_3 - assign m_vrg_source_busy_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_4 - assign m_vrg_source_busy_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_5 - assign m_vrg_source_busy_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_6 - assign m_vrg_source_busy_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_7 - assign m_vrg_source_busy_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_8 - assign m_vrg_source_busy_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_busy_9 - assign m_vrg_source_busy_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_2 && - !WILL_FIRE_RL_m_rl_reset ; - assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67436 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_0 - assign m_vrg_source_ip_0$D_IN = 1'd0 ; - assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_1 - assign m_vrg_source_ip_1$D_IN = - !MUX_m_vrg_source_busy_1$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_0_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_1$EN = - !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_10 - assign m_vrg_source_ip_10$D_IN = - !MUX_m_vrg_source_busy_10$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_9_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_10$EN = - !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_11 - assign m_vrg_source_ip_11$D_IN = - !MUX_m_vrg_source_busy_11$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_10_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_11$EN = - !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_12 - assign m_vrg_source_ip_12$D_IN = - !MUX_m_vrg_source_busy_12$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_11_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_12$EN = - !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_13 - assign m_vrg_source_ip_13$D_IN = - !MUX_m_vrg_source_busy_13$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_12_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_13$EN = - !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_14 - assign m_vrg_source_ip_14$D_IN = - !MUX_m_vrg_source_busy_14$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_13_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_14$EN = - !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_15 - assign m_vrg_source_ip_15$D_IN = - !MUX_m_vrg_source_busy_15$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_14_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_15$EN = - !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_16 - assign m_vrg_source_ip_16$D_IN = - !MUX_m_vrg_source_busy_16$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_15_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_16$EN = - !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_2 - assign m_vrg_source_ip_2$D_IN = - !MUX_m_vrg_source_busy_2$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_1_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_2$EN = - !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_3 - assign m_vrg_source_ip_3$D_IN = - !MUX_m_vrg_source_busy_3$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_2_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_3$EN = - !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_4 - assign m_vrg_source_ip_4$D_IN = - !MUX_m_vrg_source_busy_4$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_3_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_4$EN = - !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_5 - assign m_vrg_source_ip_5$D_IN = - !MUX_m_vrg_source_busy_5$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_4_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_5$EN = - !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_6 - assign m_vrg_source_ip_6$D_IN = - !MUX_m_vrg_source_busy_6$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_5_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_6$EN = - !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_7 - assign m_vrg_source_ip_7$D_IN = - !MUX_m_vrg_source_busy_7$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_6_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_7$EN = - !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_8 - assign m_vrg_source_ip_8$D_IN = - !MUX_m_vrg_source_busy_8$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_7_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_8$EN = - !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_ip_9 - assign m_vrg_source_ip_9$D_IN = - !MUX_m_vrg_source_busy_9$write_1__SEL_1 && - !WILL_FIRE_RL_m_rl_reset && - v_sources_8_m_interrupt_req_set_not_clear ; - assign m_vrg_source_ip_9$EN = - !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23959 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_0 - assign m_vrg_source_prio_0$D_IN = - MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26929[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_1 - assign m_vrg_source_prio_1$D_IN = - MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_10 - assign m_vrg_source_prio_10$D_IN = - MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_11 - assign m_vrg_source_prio_11$D_IN = - MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_12 - assign m_vrg_source_prio_12$D_IN = - MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_13 - assign m_vrg_source_prio_13$D_IN = - MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_14 - assign m_vrg_source_prio_14$D_IN = - MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_15 - assign m_vrg_source_prio_15$D_IN = - MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_16 - assign m_vrg_source_prio_16$D_IN = - MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_2 - assign m_vrg_source_prio_2$D_IN = - MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_3 - assign m_vrg_source_prio_3$D_IN = - MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_4 - assign m_vrg_source_prio_4$D_IN = - MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_5 - assign m_vrg_source_prio_5$D_IN = - MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_6 - assign m_vrg_source_prio_6$D_IN = - MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_7 - assign m_vrg_source_prio_7$D_IN = - MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_8 - assign m_vrg_source_prio_8$D_IN = - MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_source_prio_9 - assign m_vrg_source_prio_9$D_IN = - MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd0 ; - assign m_vrg_source_prio_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_0 - assign m_vrg_target_threshold_0$D_IN = - MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vrg_target_threshold_1 - assign m_vrg_target_threshold_1$D_IN = - MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26930[2:0] : - 3'd7 ; - assign m_vrg_target_threshold_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_0 - assign m_vvrg_ie_0_0$D_IN = - MUX_m_vvrg_ie_0_0$write_1__SEL_1 && - MUX_m_vvrg_ie_0_0$write_1__VAL_1 ; - assign m_vvrg_ie_0_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_1 - assign m_vvrg_ie_0_1$D_IN = - MUX_m_vvrg_ie_0_1$write_1__SEL_1 && - MUX_m_vvrg_ie_0_1$write_1__VAL_1 ; - assign m_vvrg_ie_0_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_10 - assign m_vvrg_ie_0_10$D_IN = - MUX_m_vvrg_ie_0_10$write_1__SEL_1 && - MUX_m_vvrg_ie_0_10$write_1__VAL_1 ; - assign m_vvrg_ie_0_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_11 - assign m_vvrg_ie_0_11$D_IN = - MUX_m_vvrg_ie_0_11$write_1__SEL_1 && - MUX_m_vvrg_ie_0_11$write_1__VAL_1 ; - assign m_vvrg_ie_0_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_12 - assign m_vvrg_ie_0_12$D_IN = - MUX_m_vvrg_ie_0_12$write_1__SEL_1 && - MUX_m_vvrg_ie_0_12$write_1__VAL_1 ; - assign m_vvrg_ie_0_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_13 - assign m_vvrg_ie_0_13$D_IN = - MUX_m_vvrg_ie_0_13$write_1__SEL_1 && - MUX_m_vvrg_ie_0_13$write_1__VAL_1 ; - assign m_vvrg_ie_0_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_14 - assign m_vvrg_ie_0_14$D_IN = - MUX_m_vvrg_ie_0_14$write_1__SEL_1 && - MUX_m_vvrg_ie_0_14$write_1__VAL_1 ; - assign m_vvrg_ie_0_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_15 - assign m_vvrg_ie_0_15$D_IN = - MUX_m_vvrg_ie_0_15$write_1__SEL_1 && - MUX_m_vvrg_ie_0_15$write_1__VAL_1 ; - assign m_vvrg_ie_0_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_16 - assign m_vvrg_ie_0_16$D_IN = - MUX_m_vvrg_ie_0_16$write_1__SEL_1 && - MUX_m_vvrg_ie_0_16$write_1__VAL_1 ; - assign m_vvrg_ie_0_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_2 - assign m_vvrg_ie_0_2$D_IN = - MUX_m_vvrg_ie_0_2$write_1__SEL_1 && - MUX_m_vvrg_ie_0_2$write_1__VAL_1 ; - assign m_vvrg_ie_0_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_3 - assign m_vvrg_ie_0_3$D_IN = - MUX_m_vvrg_ie_0_3$write_1__SEL_1 && - MUX_m_vvrg_ie_0_3$write_1__VAL_1 ; - assign m_vvrg_ie_0_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_4 - assign m_vvrg_ie_0_4$D_IN = - MUX_m_vvrg_ie_0_4$write_1__SEL_1 && - MUX_m_vvrg_ie_0_4$write_1__VAL_1 ; - assign m_vvrg_ie_0_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_5 - assign m_vvrg_ie_0_5$D_IN = - MUX_m_vvrg_ie_0_5$write_1__SEL_1 && - MUX_m_vvrg_ie_0_5$write_1__VAL_1 ; - assign m_vvrg_ie_0_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_6 - assign m_vvrg_ie_0_6$D_IN = - MUX_m_vvrg_ie_0_6$write_1__SEL_1 && - MUX_m_vvrg_ie_0_6$write_1__VAL_1 ; - assign m_vvrg_ie_0_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_7 - assign m_vvrg_ie_0_7$D_IN = - MUX_m_vvrg_ie_0_7$write_1__SEL_1 && - MUX_m_vvrg_ie_0_7$write_1__VAL_1 ; - assign m_vvrg_ie_0_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_8 - assign m_vvrg_ie_0_8$D_IN = - MUX_m_vvrg_ie_0_8$write_1__SEL_1 && - MUX_m_vvrg_ie_0_8$write_1__VAL_1 ; - assign m_vvrg_ie_0_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_0_9 - assign m_vvrg_ie_0_9$D_IN = - MUX_m_vvrg_ie_0_9$write_1__SEL_1 && - MUX_m_vvrg_ie_0_9$write_1__VAL_1 ; - assign m_vvrg_ie_0_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_0 - assign m_vvrg_ie_1_0$D_IN = - MUX_m_vvrg_ie_1_0$write_1__SEL_1 && - MUX_m_vvrg_ie_1_0$write_1__VAL_1 ; - assign m_vvrg_ie_1_0$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_1 - assign m_vvrg_ie_1_1$D_IN = - MUX_m_vvrg_ie_1_1$write_1__SEL_1 && - MUX_m_vvrg_ie_1_1$write_1__VAL_1 ; - assign m_vvrg_ie_1_1$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_10 - assign m_vvrg_ie_1_10$D_IN = - MUX_m_vvrg_ie_1_10$write_1__SEL_1 && - MUX_m_vvrg_ie_1_10$write_1__VAL_1 ; - assign m_vvrg_ie_1_10$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_11 - assign m_vvrg_ie_1_11$D_IN = - MUX_m_vvrg_ie_1_11$write_1__SEL_1 && - MUX_m_vvrg_ie_1_11$write_1__VAL_1 ; - assign m_vvrg_ie_1_11$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_12 - assign m_vvrg_ie_1_12$D_IN = - MUX_m_vvrg_ie_1_12$write_1__SEL_1 && - MUX_m_vvrg_ie_1_12$write_1__VAL_1 ; - assign m_vvrg_ie_1_12$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_13 - assign m_vvrg_ie_1_13$D_IN = - MUX_m_vvrg_ie_1_13$write_1__SEL_1 && - MUX_m_vvrg_ie_1_13$write_1__VAL_1 ; - assign m_vvrg_ie_1_13$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_14 - assign m_vvrg_ie_1_14$D_IN = - MUX_m_vvrg_ie_1_14$write_1__SEL_1 && - MUX_m_vvrg_ie_1_14$write_1__VAL_1 ; - assign m_vvrg_ie_1_14$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_15 - assign m_vvrg_ie_1_15$D_IN = - MUX_m_vvrg_ie_1_15$write_1__SEL_1 && - MUX_m_vvrg_ie_1_15$write_1__VAL_1 ; - assign m_vvrg_ie_1_15$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_16 - assign m_vvrg_ie_1_16$D_IN = - MUX_m_vvrg_ie_1_16$write_1__SEL_1 && - MUX_m_vvrg_ie_1_16$write_1__VAL_1 ; - assign m_vvrg_ie_1_16$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_2 - assign m_vvrg_ie_1_2$D_IN = - MUX_m_vvrg_ie_1_2$write_1__SEL_1 && - MUX_m_vvrg_ie_1_2$write_1__VAL_1 ; - assign m_vvrg_ie_1_2$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_3 - assign m_vvrg_ie_1_3$D_IN = - MUX_m_vvrg_ie_1_3$write_1__SEL_1 && - MUX_m_vvrg_ie_1_3$write_1__VAL_1 ; - assign m_vvrg_ie_1_3$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_4 - assign m_vvrg_ie_1_4$D_IN = - MUX_m_vvrg_ie_1_4$write_1__SEL_1 && - MUX_m_vvrg_ie_1_4$write_1__VAL_1 ; - assign m_vvrg_ie_1_4$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_5 - assign m_vvrg_ie_1_5$D_IN = - MUX_m_vvrg_ie_1_5$write_1__SEL_1 && - MUX_m_vvrg_ie_1_5$write_1__VAL_1 ; - assign m_vvrg_ie_1_5$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_6 - assign m_vvrg_ie_1_6$D_IN = - MUX_m_vvrg_ie_1_6$write_1__SEL_1 && - MUX_m_vvrg_ie_1_6$write_1__VAL_1 ; - assign m_vvrg_ie_1_6$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_7 - assign m_vvrg_ie_1_7$D_IN = - MUX_m_vvrg_ie_1_7$write_1__SEL_1 && - MUX_m_vvrg_ie_1_7$write_1__VAL_1 ; - assign m_vvrg_ie_1_7$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_8 - assign m_vvrg_ie_1_8$D_IN = - MUX_m_vvrg_ie_1_8$write_1__SEL_1 && - MUX_m_vvrg_ie_1_8$write_1__VAL_1 ; - assign m_vvrg_ie_1_8$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 || - WILL_FIRE_RL_m_rl_reset ; - - // register m_vvrg_ie_1_9 - assign m_vvrg_ie_1_9$D_IN = - MUX_m_vvrg_ie_1_9$write_1__SEL_1 && - MUX_m_vvrg_ie_1_9$write_1__VAL_1 ; - assign m_vvrg_ie_1_9$EN = - WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 || - WILL_FIRE_RL_m_rl_reset ; - - // submodule m_f_reset_reqs - assign m_f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign m_f_reset_reqs$DEQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_reqs$CLR = 1'b0 ; - - // submodule m_f_reset_rsps - assign m_f_reset_rsps$ENQ = CAN_FIRE_RL_m_rl_reset ; - assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign m_f_reset_rsps$CLR = 1'b0 ; - - // submodule m_slave_xactor_f_rd_addr - assign m_slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign m_slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ; - assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_rd_data - assign m_slave_xactor_f_rd_data$D_IN = - { m_slave_xactor_f_rd_addr$D_OUT[96:93], - x__h26361, - rresp__h26203, - 1'd1 } ; - assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ; - assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_addr - assign m_slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign m_slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ; - assign m_slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_data - assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wid, - axi4_slave_wdata, - axi4_slave_wstrb, - axi4_slave_wlast } ; - assign m_slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; - assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_resp - assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26934 } ; - assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; - assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ; - - // remaining internal signals - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 : - ((x__h23673 == 32'h00200000) ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 : - x__h23673 != 32'h00200004 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 || - x__h24011 != 5'd0) ; - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - addr_offset__h13216[11:2] == 10'd0 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 : - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 : - ((x__h67110 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 : - x__h67110 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 || - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - addr_offset__h26929[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2989) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? - 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? - 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3102) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3196) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? - 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? - 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3104) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3198) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? - 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 = - (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 = - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - m_vrg_source_prio_1 : - 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_0_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 ? - 5'd2 : - ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - m_vvrg_ie_1_1) ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? - 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? - 5'd2 : - (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? - 5'd1 : - 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3094) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3188) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? - 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? - 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3096) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3190) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? - 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? - 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3100 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3098) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3194 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3192) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? - 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? - 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ; - assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200000 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23673 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24011 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h30685 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h31895 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h33105 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h34315 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h35525 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h36735 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h37945 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h39155 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h40365 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h41575 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h42785 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h43995 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h45205 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h46415 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h47625 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h48835 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h50045 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h51255 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h52465 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h53675 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h54885 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h56095 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h57305 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h58515 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h59725 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h60935 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h62145 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h63355 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h64565 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h65775 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2925 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - x__h67110 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 && - !SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d852 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 && - source_id__h29475 <= 10'd16 ; - assign NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313 = - !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321 = - !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_11 != - v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329 = - !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_12 != - v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337 = - !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_13 != - v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345 = - !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_14 != - v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353 = - !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_15 != - v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361 = - !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_16 != - v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242 = - !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249 = - !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257 = - !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265 = - !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273 = - !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281 = - !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289 = - !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297 = - !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305 = - !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && - m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; - assign _dfoo1 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo10 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo100 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo32 ; - assign _dfoo1000 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo932 ; - assign _dfoo1001 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo865 ; - assign _dfoo1002 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo934 ; - assign _dfoo1003 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo867 ; - assign _dfoo1004 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo936 ; - assign _dfoo1005 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo869 ; - assign _dfoo1006 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo938 ; - assign _dfoo1007 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo871 ; - assign _dfoo1008 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo940 ; - assign _dfoo1009 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo873 ; - assign _dfoo1010 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo942 ; - assign _dfoo1011 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo875 ; - assign _dfoo1012 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo944 ; - assign _dfoo1013 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo877 ; - assign _dfoo1014 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo946 ; - assign _dfoo1015 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo879 ; - assign _dfoo1016 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo948 ; - assign _dfoo1017 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo881 ; - assign _dfoo1018 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo950 ; - assign _dfoo1019 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo883 ; - assign _dfoo102 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo34 ; - assign _dfoo1020 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo952 ; - assign _dfoo1022 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo954 ; - assign _dfoo1024 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo956 ; - assign _dfoo1026 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo958 ; - assign _dfoo1028 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo960 ; - assign _dfoo1030 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo962 ; - assign _dfoo1032 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo964 ; - assign _dfoo1034 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo966 ; - assign _dfoo1036 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo968 ; - assign _dfoo1038 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo970 ; - assign _dfoo104 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo36 ; - assign _dfoo1040 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo972 ; - assign _dfoo1042 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo974 ; - assign _dfoo1044 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo976 ; - assign _dfoo1046 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo978 ; - assign _dfoo1048 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo980 ; - assign _dfoo1050 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo982 ; - assign _dfoo1052 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo984 ; - assign _dfoo1054 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo986 ; - assign _dfoo1056 = - (source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo988 ; - assign _dfoo1058 = - (source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo990 ; - assign _dfoo106 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo38 ; - assign _dfoo1060 = - (source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo992 ; - assign _dfoo1062 = - (source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo994 ; - assign _dfoo1064 = - (source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo996 ; - assign _dfoo1066 = - (source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo998 ; - assign _dfoo1068 = - (source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1000 ; - assign _dfoo1070 = - (source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1002 ; - assign _dfoo1072 = - (source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1004 ; - assign _dfoo1074 = - (source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1006 ; - assign _dfoo1076 = - (source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1008 ; - assign _dfoo1078 = - (source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1010 ; - assign _dfoo108 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo40 ; - assign _dfoo1080 = - (source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1012 ; - assign _dfoo1082 = - (source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1014 ; - assign _dfoo1084 = - (source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1016 ; - assign _dfoo1086 = - (source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1018 ; - assign _dfoo1088 = - (source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836) ? - wdata32__h26930[15] : - _dfoo1020 ; - assign _dfoo1089 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo953 ; - assign _dfoo1090 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1022 ; - assign _dfoo1091 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo955 ; - assign _dfoo1092 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1024 ; - assign _dfoo1093 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo957 ; - assign _dfoo1094 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1026 ; - assign _dfoo1095 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo959 ; - assign _dfoo1096 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1028 ; - assign _dfoo1097 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo961 ; - assign _dfoo1098 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1030 ; - assign _dfoo1099 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo963 ; - assign _dfoo11 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo110 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo42 ; - assign _dfoo1100 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1032 ; - assign _dfoo1101 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo965 ; - assign _dfoo1102 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1034 ; - assign _dfoo1103 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo967 ; - assign _dfoo1104 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1036 ; - assign _dfoo1105 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo969 ; - assign _dfoo1106 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1038 ; - assign _dfoo1107 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo971 ; - assign _dfoo1108 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1040 ; - assign _dfoo1109 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo973 ; - assign _dfoo1110 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1042 ; - assign _dfoo1111 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo975 ; - assign _dfoo1112 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1044 ; - assign _dfoo1113 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo977 ; - assign _dfoo1114 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1046 ; - assign _dfoo1115 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo979 ; - assign _dfoo1116 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1048 ; - assign _dfoo1117 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo981 ; - assign _dfoo1118 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1050 ; - assign _dfoo1119 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo983 ; - assign _dfoo112 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo44 ; - assign _dfoo1120 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1052 ; - assign _dfoo1121 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo985 ; - assign _dfoo1122 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1054 ; - assign _dfoo1123 = - source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo987 ; - assign _dfoo1124 = - (source_id__h45205 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1056 ; - assign _dfoo1125 = - source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo989 ; - assign _dfoo1126 = - (source_id__h45205 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1058 ; - assign _dfoo1127 = - source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo991 ; - assign _dfoo1128 = - (source_id__h45205 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1060 ; - assign _dfoo1129 = - source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo993 ; - assign _dfoo1130 = - (source_id__h45205 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1062 ; - assign _dfoo1131 = - source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo995 ; - assign _dfoo1132 = - (source_id__h45205 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1064 ; - assign _dfoo1133 = - source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo997 ; - assign _dfoo1134 = - (source_id__h45205 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1066 ; - assign _dfoo1135 = - source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo999 ; - assign _dfoo1136 = - (source_id__h45205 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1068 ; - assign _dfoo1137 = - source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1001 ; - assign _dfoo1138 = - (source_id__h45205 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1070 ; - assign _dfoo1139 = - source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1003 ; - assign _dfoo114 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo46 ; - assign _dfoo1140 = - (source_id__h45205 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1072 ; - assign _dfoo1141 = - source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1005 ; - assign _dfoo1142 = - (source_id__h45205 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1074 ; - assign _dfoo1143 = - source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1007 ; - assign _dfoo1144 = - (source_id__h45205 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1076 ; - assign _dfoo1145 = - source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1009 ; - assign _dfoo1146 = - (source_id__h45205 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1078 ; - assign _dfoo1147 = - source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1011 ; - assign _dfoo1148 = - (source_id__h45205 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1080 ; - assign _dfoo1149 = - source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1013 ; - assign _dfoo1150 = - (source_id__h45205 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1082 ; - assign _dfoo1151 = - source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1015 ; - assign _dfoo1152 = - (source_id__h45205 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1084 ; - assign _dfoo1153 = - source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1017 ; - assign _dfoo1154 = - (source_id__h45205 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1086 ; - assign _dfoo1155 = - source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775 || - source_id__h46415 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1836 || - _dfoo1019 ; - assign _dfoo1156 = - (source_id__h45205 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1775) ? - wdata32__h26930[14] : - _dfoo1088 ; - assign _dfoo1158 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1090 ; - assign _dfoo116 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo48 ; - assign _dfoo1160 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1092 ; - assign _dfoo1162 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1094 ; - assign _dfoo1164 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1096 ; - assign _dfoo1166 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1098 ; - assign _dfoo1168 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1100 ; - assign _dfoo1170 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1102 ; - assign _dfoo1172 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1104 ; - assign _dfoo1174 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1106 ; - assign _dfoo1176 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1108 ; - assign _dfoo1178 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1110 ; - assign _dfoo118 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo50 ; - assign _dfoo1180 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1112 ; - assign _dfoo1182 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1114 ; - assign _dfoo1184 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1116 ; - assign _dfoo1186 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1118 ; - assign _dfoo1188 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1120 ; - assign _dfoo1190 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1122 ; - assign _dfoo1192 = - (source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1124 ; - assign _dfoo1194 = - (source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1126 ; - assign _dfoo1196 = - (source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1128 ; - assign _dfoo1198 = - (source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1130 ; - assign _dfoo12 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo120 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo52 ; - assign _dfoo1200 = - (source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1132 ; - assign _dfoo1202 = - (source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1134 ; - assign _dfoo1204 = - (source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1136 ; - assign _dfoo1206 = - (source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1138 ; - assign _dfoo1208 = - (source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1140 ; - assign _dfoo1210 = - (source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1142 ; - assign _dfoo1212 = - (source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1144 ; - assign _dfoo1214 = - (source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1146 ; - assign _dfoo1216 = - (source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1148 ; - assign _dfoo1218 = - (source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1150 ; - assign _dfoo122 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo54 ; - assign _dfoo1220 = - (source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1152 ; - assign _dfoo1222 = - (source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1154 ; - assign _dfoo1224 = - (source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714) ? - wdata32__h26930[13] : - _dfoo1156 ; - assign _dfoo1225 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1089 ; - assign _dfoo1226 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1158 ; - assign _dfoo1227 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1091 ; - assign _dfoo1228 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1160 ; - assign _dfoo1229 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1093 ; - assign _dfoo1230 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1162 ; - assign _dfoo1231 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1095 ; - assign _dfoo1232 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1164 ; - assign _dfoo1233 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1097 ; - assign _dfoo1234 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1166 ; - assign _dfoo1235 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1099 ; - assign _dfoo1236 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1168 ; - assign _dfoo1237 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1101 ; - assign _dfoo1238 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1170 ; - assign _dfoo1239 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1103 ; - assign _dfoo124 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo56 ; - assign _dfoo1240 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1172 ; - assign _dfoo1241 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1105 ; - assign _dfoo1242 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1174 ; - assign _dfoo1243 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1107 ; - assign _dfoo1244 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1176 ; - assign _dfoo1245 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1109 ; - assign _dfoo1246 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1178 ; - assign _dfoo1247 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1111 ; - assign _dfoo1248 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1180 ; - assign _dfoo1249 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1113 ; - assign _dfoo1250 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1182 ; - assign _dfoo1251 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1115 ; - assign _dfoo1252 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1184 ; - assign _dfoo1253 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1117 ; - assign _dfoo1254 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1186 ; - assign _dfoo1255 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1119 ; - assign _dfoo1256 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1188 ; - assign _dfoo1257 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1121 ; - assign _dfoo1258 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1190 ; - assign _dfoo1259 = - source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1123 ; - assign _dfoo126 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo58 ; - assign _dfoo1260 = - (source_id__h42785 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1192 ; - assign _dfoo1261 = - source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1125 ; - assign _dfoo1262 = - (source_id__h42785 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1194 ; - assign _dfoo1263 = - source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1127 ; - assign _dfoo1264 = - (source_id__h42785 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1196 ; - assign _dfoo1265 = - source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1129 ; - assign _dfoo1266 = - (source_id__h42785 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1198 ; - assign _dfoo1267 = - source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1131 ; - assign _dfoo1268 = - (source_id__h42785 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1200 ; - assign _dfoo1269 = - source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1133 ; - assign _dfoo1270 = - (source_id__h42785 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1202 ; - assign _dfoo1271 = - source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1135 ; - assign _dfoo1272 = - (source_id__h42785 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1204 ; - assign _dfoo1273 = - source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1137 ; - assign _dfoo1274 = - (source_id__h42785 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1206 ; - assign _dfoo1275 = - source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1139 ; - assign _dfoo1276 = - (source_id__h42785 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1208 ; - assign _dfoo1277 = - source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1141 ; - assign _dfoo1278 = - (source_id__h42785 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1210 ; - assign _dfoo1279 = - source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1143 ; - assign _dfoo128 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo60 ; - assign _dfoo1280 = - (source_id__h42785 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1212 ; - assign _dfoo1281 = - source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1145 ; - assign _dfoo1282 = - (source_id__h42785 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1214 ; - assign _dfoo1283 = - source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1147 ; - assign _dfoo1284 = - (source_id__h42785 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1216 ; - assign _dfoo1285 = - source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1149 ; - assign _dfoo1286 = - (source_id__h42785 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1218 ; - assign _dfoo1287 = - source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1151 ; - assign _dfoo1288 = - (source_id__h42785 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1220 ; - assign _dfoo1289 = - source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1153 ; - assign _dfoo1290 = - (source_id__h42785 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1222 ; - assign _dfoo1291 = - source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653 || - source_id__h43995 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1714 || - _dfoo1155 ; - assign _dfoo1292 = - (source_id__h42785 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1653) ? - wdata32__h26930[12] : - _dfoo1224 ; - assign _dfoo1294 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1226 ; - assign _dfoo1296 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1228 ; - assign _dfoo1298 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1230 ; - assign _dfoo13 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo130 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo62 ; - assign _dfoo1300 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1232 ; - assign _dfoo1302 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1234 ; - assign _dfoo1304 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1236 ; - assign _dfoo1306 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1238 ; - assign _dfoo1308 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1240 ; - assign _dfoo1310 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1242 ; - assign _dfoo1312 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1244 ; - assign _dfoo1314 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1246 ; - assign _dfoo1316 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1248 ; - assign _dfoo1318 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1250 ; - assign _dfoo132 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo64 ; - assign _dfoo1320 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1252 ; - assign _dfoo1322 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1254 ; - assign _dfoo1324 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1256 ; - assign _dfoo1326 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1258 ; - assign _dfoo1328 = - (source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1260 ; - assign _dfoo1330 = - (source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1262 ; - assign _dfoo1332 = - (source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1264 ; - assign _dfoo1334 = - (source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1266 ; - assign _dfoo1336 = - (source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1268 ; - assign _dfoo1338 = - (source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1270 ; - assign _dfoo134 = - (source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo66 ; - assign _dfoo1340 = - (source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1272 ; - assign _dfoo1342 = - (source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1274 ; - assign _dfoo1344 = - (source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1276 ; - assign _dfoo1346 = - (source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1278 ; - assign _dfoo1348 = - (source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1280 ; - assign _dfoo1350 = - (source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1282 ; - assign _dfoo1352 = - (source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1284 ; - assign _dfoo1354 = - (source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1286 ; - assign _dfoo1356 = - (source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1288 ; - assign _dfoo1358 = - (source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1290 ; - assign _dfoo136 = - (source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo68 ; - assign _dfoo1360 = - (source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592) ? - wdata32__h26930[11] : - _dfoo1292 ; - assign _dfoo1361 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1225 ; - assign _dfoo1362 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1294 ; - assign _dfoo1363 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1227 ; - assign _dfoo1364 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1296 ; - assign _dfoo1365 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1229 ; - assign _dfoo1366 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1298 ; - assign _dfoo1367 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1231 ; - assign _dfoo1368 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1300 ; - assign _dfoo1369 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1233 ; - assign _dfoo137 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo1 ; - assign _dfoo1370 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1302 ; - assign _dfoo1371 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1235 ; - assign _dfoo1372 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1304 ; - assign _dfoo1373 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1237 ; - assign _dfoo1374 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1306 ; - assign _dfoo1375 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1239 ; - assign _dfoo1376 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1308 ; - assign _dfoo1377 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1241 ; - assign _dfoo1378 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1310 ; - assign _dfoo1379 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1243 ; - assign _dfoo138 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo70 ; - assign _dfoo1380 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1312 ; - assign _dfoo1381 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1245 ; - assign _dfoo1382 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1314 ; - assign _dfoo1383 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1247 ; - assign _dfoo1384 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1316 ; - assign _dfoo1385 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1249 ; - assign _dfoo1386 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1318 ; - assign _dfoo1387 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1251 ; - assign _dfoo1388 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1320 ; - assign _dfoo1389 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1253 ; - assign _dfoo139 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo3 ; - assign _dfoo1390 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1322 ; - assign _dfoo1391 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1255 ; - assign _dfoo1392 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1324 ; - assign _dfoo1393 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1257 ; - assign _dfoo1394 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1326 ; - assign _dfoo1395 = - source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1259 ; - assign _dfoo1396 = - (source_id__h40365 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1328 ; - assign _dfoo1397 = - source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1261 ; - assign _dfoo1398 = - (source_id__h40365 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1330 ; - assign _dfoo1399 = - source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1263 ; - assign _dfoo14 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo140 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo72 ; - assign _dfoo1400 = - (source_id__h40365 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1332 ; - assign _dfoo1401 = - source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1265 ; - assign _dfoo1402 = - (source_id__h40365 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1334 ; - assign _dfoo1403 = - source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1267 ; - assign _dfoo1404 = - (source_id__h40365 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1336 ; - assign _dfoo1405 = - source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1269 ; - assign _dfoo1406 = - (source_id__h40365 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1338 ; - assign _dfoo1407 = - source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1271 ; - assign _dfoo1408 = - (source_id__h40365 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1340 ; - assign _dfoo1409 = - source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1273 ; - assign _dfoo141 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo5 ; - assign _dfoo1410 = - (source_id__h40365 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1342 ; - assign _dfoo1411 = - source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1275 ; - assign _dfoo1412 = - (source_id__h40365 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1344 ; - assign _dfoo1413 = - source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1277 ; - assign _dfoo1414 = - (source_id__h40365 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1346 ; - assign _dfoo1415 = - source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1279 ; - assign _dfoo1416 = - (source_id__h40365 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1348 ; - assign _dfoo1417 = - source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1281 ; - assign _dfoo1418 = - (source_id__h40365 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1350 ; - assign _dfoo1419 = - source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1283 ; - assign _dfoo142 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo74 ; - assign _dfoo1420 = - (source_id__h40365 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1352 ; - assign _dfoo1421 = - source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1285 ; - assign _dfoo1422 = - (source_id__h40365 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1354 ; - assign _dfoo1423 = - source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1287 ; - assign _dfoo1424 = - (source_id__h40365 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1356 ; - assign _dfoo1425 = - source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1289 ; - assign _dfoo1426 = - (source_id__h40365 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1358 ; - assign _dfoo1427 = - source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531 || - source_id__h41575 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1592 || - _dfoo1291 ; - assign _dfoo1428 = - (source_id__h40365 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1531) ? - wdata32__h26930[10] : - _dfoo1360 ; - assign _dfoo143 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo7 ; - assign _dfoo1430 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1362 ; - assign _dfoo1432 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1364 ; - assign _dfoo1434 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1366 ; - assign _dfoo1436 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1368 ; - assign _dfoo1438 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1370 ; - assign _dfoo144 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo76 ; - assign _dfoo1440 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1372 ; - assign _dfoo1442 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1374 ; - assign _dfoo1444 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1376 ; - assign _dfoo1446 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1378 ; - assign _dfoo1448 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1380 ; - assign _dfoo145 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo9 ; - assign _dfoo1450 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1382 ; - assign _dfoo1452 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1384 ; - assign _dfoo1454 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1386 ; - assign _dfoo1456 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1388 ; - assign _dfoo1458 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1390 ; - assign _dfoo146 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo78 ; - assign _dfoo1460 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1392 ; - assign _dfoo1462 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1394 ; - assign _dfoo1464 = - (source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1396 ; - assign _dfoo1466 = - (source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1398 ; - assign _dfoo1468 = - (source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1400 ; - assign _dfoo147 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo11 ; - assign _dfoo1470 = - (source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1402 ; - assign _dfoo1472 = - (source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1404 ; - assign _dfoo1474 = - (source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1406 ; - assign _dfoo1476 = - (source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1408 ; - assign _dfoo1478 = - (source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1410 ; - assign _dfoo148 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo80 ; - assign _dfoo1480 = - (source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1412 ; - assign _dfoo1482 = - (source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1414 ; - assign _dfoo1484 = - (source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1416 ; - assign _dfoo1486 = - (source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1418 ; - assign _dfoo1488 = - (source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1420 ; - assign _dfoo149 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo13 ; - assign _dfoo1490 = - (source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1422 ; - assign _dfoo1492 = - (source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1424 ; - assign _dfoo1494 = - (source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1426 ; - assign _dfoo1496 = - (source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470) ? - wdata32__h26930[9] : - _dfoo1428 ; - assign _dfoo1497 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1361 ; - assign _dfoo1498 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1430 ; - assign _dfoo1499 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1363 ; - assign _dfoo15 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo150 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo82 ; - assign _dfoo1500 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1432 ; - assign _dfoo1501 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1365 ; - assign _dfoo1502 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1434 ; - assign _dfoo1503 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1367 ; - assign _dfoo1504 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1436 ; - assign _dfoo1505 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1369 ; - assign _dfoo1506 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1438 ; - assign _dfoo1507 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1371 ; - assign _dfoo1508 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1440 ; - assign _dfoo1509 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1373 ; - assign _dfoo151 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo15 ; - assign _dfoo1510 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1442 ; - assign _dfoo1511 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1375 ; - assign _dfoo1512 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1444 ; - assign _dfoo1513 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1377 ; - assign _dfoo1514 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1446 ; - assign _dfoo1515 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1379 ; - assign _dfoo1516 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1448 ; - assign _dfoo1517 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1381 ; - assign _dfoo1518 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1450 ; - assign _dfoo1519 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1383 ; - assign _dfoo152 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo84 ; - assign _dfoo1520 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1452 ; - assign _dfoo1521 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1385 ; - assign _dfoo1522 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1454 ; - assign _dfoo1523 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1387 ; - assign _dfoo1524 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1456 ; - assign _dfoo1525 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1389 ; - assign _dfoo1526 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1458 ; - assign _dfoo1527 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1391 ; - assign _dfoo1528 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1460 ; - assign _dfoo1529 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1393 ; - assign _dfoo153 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo17 ; - assign _dfoo1530 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1462 ; - assign _dfoo1531 = - source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1395 ; - assign _dfoo1532 = - (source_id__h37945 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1464 ; - assign _dfoo1533 = - source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1397 ; - assign _dfoo1534 = - (source_id__h37945 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1466 ; - assign _dfoo1535 = - source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1399 ; - assign _dfoo1536 = - (source_id__h37945 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1468 ; - assign _dfoo1537 = - source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1401 ; - assign _dfoo1538 = - (source_id__h37945 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1470 ; - assign _dfoo1539 = - source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1403 ; - assign _dfoo154 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo86 ; - assign _dfoo1540 = - (source_id__h37945 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1472 ; - assign _dfoo1541 = - source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1405 ; - assign _dfoo1542 = - (source_id__h37945 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1474 ; - assign _dfoo1543 = - source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1407 ; - assign _dfoo1544 = - (source_id__h37945 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1476 ; - assign _dfoo1545 = - source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1409 ; - assign _dfoo1546 = - (source_id__h37945 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1478 ; - assign _dfoo1547 = - source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1411 ; - assign _dfoo1548 = - (source_id__h37945 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1480 ; - assign _dfoo1549 = - source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1413 ; - assign _dfoo155 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo19 ; - assign _dfoo1550 = - (source_id__h37945 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1482 ; - assign _dfoo1551 = - source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1415 ; - assign _dfoo1552 = - (source_id__h37945 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1484 ; - assign _dfoo1553 = - source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1417 ; - assign _dfoo1554 = - (source_id__h37945 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1486 ; - assign _dfoo1555 = - source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1419 ; - assign _dfoo1556 = - (source_id__h37945 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1488 ; - assign _dfoo1557 = - source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1421 ; - assign _dfoo1558 = - (source_id__h37945 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1490 ; - assign _dfoo1559 = - source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1423 ; - assign _dfoo156 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo88 ; - assign _dfoo1560 = - (source_id__h37945 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1492 ; - assign _dfoo1561 = - source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1425 ; - assign _dfoo1562 = - (source_id__h37945 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1494 ; - assign _dfoo1563 = - source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409 || - source_id__h39155 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1470 || - _dfoo1427 ; - assign _dfoo1564 = - (source_id__h37945 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1409) ? - wdata32__h26930[8] : - _dfoo1496 ; - assign _dfoo1566 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1498 ; - assign _dfoo1568 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1500 ; - assign _dfoo157 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo21 ; - assign _dfoo1570 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1502 ; - assign _dfoo1572 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1504 ; - assign _dfoo1574 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1506 ; - assign _dfoo1576 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1508 ; - assign _dfoo1578 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1510 ; - assign _dfoo158 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo90 ; - assign _dfoo1580 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1512 ; - assign _dfoo1582 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1514 ; - assign _dfoo1584 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1516 ; - assign _dfoo1586 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1518 ; - assign _dfoo1588 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1520 ; - assign _dfoo159 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo23 ; - assign _dfoo1590 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1522 ; - assign _dfoo1592 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1524 ; - assign _dfoo1594 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1526 ; - assign _dfoo1596 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1528 ; - assign _dfoo1598 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1530 ; - assign _dfoo16 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo160 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo92 ; - assign _dfoo1600 = - (source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1532 ; - assign _dfoo1602 = - (source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1534 ; - assign _dfoo1604 = - (source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1536 ; - assign _dfoo1606 = - (source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1538 ; - assign _dfoo1608 = - (source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1540 ; - assign _dfoo161 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo25 ; - assign _dfoo1610 = - (source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1542 ; - assign _dfoo1612 = - (source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1544 ; - assign _dfoo1614 = - (source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1546 ; - assign _dfoo1616 = - (source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1548 ; - assign _dfoo1618 = - (source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1550 ; - assign _dfoo162 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo94 ; - assign _dfoo1620 = - (source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1552 ; - assign _dfoo1622 = - (source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1554 ; - assign _dfoo1624 = - (source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1556 ; - assign _dfoo1626 = - (source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1558 ; - assign _dfoo1628 = - (source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1560 ; - assign _dfoo163 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo27 ; - assign _dfoo1630 = - (source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1562 ; - assign _dfoo1632 = - (source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348) ? - wdata32__h26930[7] : - _dfoo1564 ; - assign _dfoo1633 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1497 ; - assign _dfoo1634 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1566 ; - assign _dfoo1635 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1499 ; - assign _dfoo1636 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1568 ; - assign _dfoo1637 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1501 ; - assign _dfoo1638 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1570 ; - assign _dfoo1639 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1503 ; - assign _dfoo164 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo96 ; - assign _dfoo1640 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1572 ; - assign _dfoo1641 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1505 ; - assign _dfoo1642 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1574 ; - assign _dfoo1643 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1507 ; - assign _dfoo1644 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1576 ; - assign _dfoo1645 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1509 ; - assign _dfoo1646 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1578 ; - assign _dfoo1647 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1511 ; - assign _dfoo1648 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1580 ; - assign _dfoo1649 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1513 ; - assign _dfoo165 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo29 ; - assign _dfoo1650 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1582 ; - assign _dfoo1651 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1515 ; - assign _dfoo1652 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1584 ; - assign _dfoo1653 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1517 ; - assign _dfoo1654 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1586 ; - assign _dfoo1655 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1519 ; - assign _dfoo1656 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1588 ; - assign _dfoo1657 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1521 ; - assign _dfoo1658 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1590 ; - assign _dfoo1659 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1523 ; - assign _dfoo166 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo98 ; - assign _dfoo1660 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1592 ; - assign _dfoo1661 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1525 ; - assign _dfoo1662 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1594 ; - assign _dfoo1663 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1527 ; - assign _dfoo1664 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1596 ; - assign _dfoo1665 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1529 ; - assign _dfoo1666 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1598 ; - assign _dfoo1667 = - source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1531 ; - assign _dfoo1668 = - (source_id__h35525 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1600 ; - assign _dfoo1669 = - source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1533 ; - assign _dfoo167 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo31 ; - assign _dfoo1670 = - (source_id__h35525 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1602 ; - assign _dfoo1671 = - source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1535 ; - assign _dfoo1672 = - (source_id__h35525 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1604 ; - assign _dfoo1673 = - source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1537 ; - assign _dfoo1674 = - (source_id__h35525 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1606 ; - assign _dfoo1675 = - source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1539 ; - assign _dfoo1676 = - (source_id__h35525 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1608 ; - assign _dfoo1677 = - source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1541 ; - assign _dfoo1678 = - (source_id__h35525 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1610 ; - assign _dfoo1679 = - source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1543 ; - assign _dfoo168 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo100 ; - assign _dfoo1680 = - (source_id__h35525 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1612 ; - assign _dfoo1681 = - source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1545 ; - assign _dfoo1682 = - (source_id__h35525 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1614 ; - assign _dfoo1683 = - source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1547 ; - assign _dfoo1684 = - (source_id__h35525 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1616 ; - assign _dfoo1685 = - source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1549 ; - assign _dfoo1686 = - (source_id__h35525 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1618 ; - assign _dfoo1687 = - source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1551 ; - assign _dfoo1688 = - (source_id__h35525 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1620 ; - assign _dfoo1689 = - source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1553 ; - assign _dfoo169 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo33 ; - assign _dfoo1690 = - (source_id__h35525 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1622 ; - assign _dfoo1691 = - source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1555 ; - assign _dfoo1692 = - (source_id__h35525 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1624 ; - assign _dfoo1693 = - source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1557 ; - assign _dfoo1694 = - (source_id__h35525 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1626 ; - assign _dfoo1695 = - source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1559 ; - assign _dfoo1696 = - (source_id__h35525 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1628 ; - assign _dfoo1697 = - source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1561 ; - assign _dfoo1698 = - (source_id__h35525 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1630 ; - assign _dfoo1699 = - source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287 || - source_id__h36735 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1348 || - _dfoo1563 ; - assign _dfoo17 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo170 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo102 ; - assign _dfoo1700 = - (source_id__h35525 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1287) ? - wdata32__h26930[6] : - _dfoo1632 ; - assign _dfoo1702 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1634 ; - assign _dfoo1704 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1636 ; - assign _dfoo1706 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1638 ; - assign _dfoo1708 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1640 ; - assign _dfoo171 = - source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo35 ; - assign _dfoo1710 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1642 ; - assign _dfoo1712 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1644 ; - assign _dfoo1714 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1646 ; - assign _dfoo1716 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1648 ; - assign _dfoo1718 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1650 ; - assign _dfoo172 = - (source_id__h62145 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo104 ; - assign _dfoo1720 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1652 ; - assign _dfoo1722 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1654 ; - assign _dfoo1724 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1656 ; - assign _dfoo1726 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1658 ; - assign _dfoo1728 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1660 ; - assign _dfoo173 = - source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo37 ; - assign _dfoo1730 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1662 ; - assign _dfoo1732 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1664 ; - assign _dfoo1734 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1666 ; - assign _dfoo1736 = - (source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1668 ; - assign _dfoo1738 = - (source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1670 ; - assign _dfoo174 = - (source_id__h62145 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo106 ; - assign _dfoo1740 = - (source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1672 ; - assign _dfoo1742 = - (source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1674 ; - assign _dfoo1744 = - (source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1676 ; - assign _dfoo1746 = - (source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1678 ; - assign _dfoo1748 = - (source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1680 ; - assign _dfoo175 = - source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo39 ; - assign _dfoo1750 = - (source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1682 ; - assign _dfoo1752 = - (source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1684 ; - assign _dfoo1754 = - (source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1686 ; - assign _dfoo1756 = - (source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1688 ; - assign _dfoo1758 = - (source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1690 ; - assign _dfoo176 = - (source_id__h62145 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo108 ; - assign _dfoo1760 = - (source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1692 ; - assign _dfoo1762 = - (source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1694 ; - assign _dfoo1764 = - (source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1696 ; - assign _dfoo1766 = - (source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1698 ; - assign _dfoo1768 = - (source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226) ? - wdata32__h26930[5] : - _dfoo1700 ; - assign _dfoo1769 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1633 ; - assign _dfoo177 = - source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo41 ; - assign _dfoo1770 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1702 ; - assign _dfoo1771 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1635 ; - assign _dfoo1772 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1704 ; - assign _dfoo1773 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1637 ; - assign _dfoo1774 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1706 ; - assign _dfoo1775 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1639 ; - assign _dfoo1776 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1708 ; - assign _dfoo1777 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1641 ; - assign _dfoo1778 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1710 ; - assign _dfoo1779 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1643 ; - assign _dfoo178 = - (source_id__h62145 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo110 ; - assign _dfoo1780 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1712 ; - assign _dfoo1781 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1645 ; - assign _dfoo1782 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1714 ; - assign _dfoo1783 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1647 ; - assign _dfoo1784 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1716 ; - assign _dfoo1785 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1649 ; - assign _dfoo1786 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1718 ; - assign _dfoo1787 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1651 ; - assign _dfoo1788 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1720 ; - assign _dfoo1789 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1653 ; - assign _dfoo179 = - source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo43 ; - assign _dfoo1790 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1722 ; - assign _dfoo1791 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1655 ; - assign _dfoo1792 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1724 ; - assign _dfoo1793 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1657 ; - assign _dfoo1794 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1726 ; - assign _dfoo1795 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1659 ; - assign _dfoo1796 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1728 ; - assign _dfoo1797 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1661 ; - assign _dfoo1798 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1730 ; - assign _dfoo1799 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1663 ; - assign _dfoo18 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo180 = - (source_id__h62145 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo112 ; - assign _dfoo1800 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1732 ; - assign _dfoo1801 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1665 ; - assign _dfoo1802 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1734 ; - assign _dfoo1803 = - source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1667 ; - assign _dfoo1804 = - (source_id__h33105 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1736 ; - assign _dfoo1805 = - source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1669 ; - assign _dfoo1806 = - (source_id__h33105 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1738 ; - assign _dfoo1807 = - source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1671 ; - assign _dfoo1808 = - (source_id__h33105 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1740 ; - assign _dfoo1809 = - source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1673 ; - assign _dfoo181 = - source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo45 ; - assign _dfoo1810 = - (source_id__h33105 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1742 ; - assign _dfoo1811 = - source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1675 ; - assign _dfoo1812 = - (source_id__h33105 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1744 ; - assign _dfoo1813 = - source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1677 ; - assign _dfoo1814 = - (source_id__h33105 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1746 ; - assign _dfoo1815 = - source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1679 ; - assign _dfoo1816 = - (source_id__h33105 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1748 ; - assign _dfoo1817 = - source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1681 ; - assign _dfoo1818 = - (source_id__h33105 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1750 ; - assign _dfoo1819 = - source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1683 ; - assign _dfoo182 = - (source_id__h62145 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo114 ; - assign _dfoo1820 = - (source_id__h33105 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1752 ; - assign _dfoo1821 = - source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1685 ; - assign _dfoo1822 = - (source_id__h33105 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1754 ; - assign _dfoo1823 = - source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1687 ; - assign _dfoo1824 = - (source_id__h33105 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1756 ; - assign _dfoo1825 = - source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1689 ; - assign _dfoo1826 = - (source_id__h33105 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1758 ; - assign _dfoo1827 = - source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1691 ; - assign _dfoo1828 = - (source_id__h33105 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1760 ; - assign _dfoo1829 = - source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1693 ; - assign _dfoo183 = - source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo47 ; - assign _dfoo1830 = - (source_id__h33105 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1762 ; - assign _dfoo1831 = - source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1695 ; - assign _dfoo1832 = - (source_id__h33105 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1764 ; - assign _dfoo1833 = - source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1697 ; - assign _dfoo1834 = - (source_id__h33105 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1766 ; - assign _dfoo1835 = - source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165 || - source_id__h34315 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1226 || - _dfoo1699 ; - assign _dfoo1836 = - (source_id__h33105 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1165) ? - wdata32__h26930[4] : - _dfoo1768 ; - assign _dfoo1838 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1770 ; - assign _dfoo184 = - (source_id__h62145 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo116 ; - assign _dfoo1840 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1772 ; - assign _dfoo1842 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1774 ; - assign _dfoo1844 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1776 ; - assign _dfoo1846 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1778 ; - assign _dfoo1848 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1780 ; - assign _dfoo185 = - source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo49 ; - assign _dfoo1850 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1782 ; - assign _dfoo1852 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1784 ; - assign _dfoo1854 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1786 ; - assign _dfoo1856 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1788 ; - assign _dfoo1858 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1790 ; - assign _dfoo186 = - (source_id__h62145 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo118 ; - assign _dfoo1860 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1792 ; - assign _dfoo1862 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1794 ; - assign _dfoo1864 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1796 ; - assign _dfoo1866 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1798 ; - assign _dfoo1868 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1800 ; - assign _dfoo187 = - source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo51 ; - assign _dfoo1870 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1802 ; - assign _dfoo1872 = - (source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1804 ; - assign _dfoo1874 = - (source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1806 ; - assign _dfoo1876 = - (source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1808 ; - assign _dfoo1878 = - (source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1810 ; - assign _dfoo188 = - (source_id__h62145 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo120 ; - assign _dfoo1880 = - (source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1812 ; - assign _dfoo1882 = - (source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1814 ; - assign _dfoo1884 = - (source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1816 ; - assign _dfoo1886 = - (source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1818 ; - assign _dfoo1888 = - (source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1820 ; - assign _dfoo189 = - source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo53 ; - assign _dfoo1890 = - (source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1822 ; - assign _dfoo1892 = - (source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1824 ; - assign _dfoo1894 = - (source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1826 ; - assign _dfoo1896 = - (source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1828 ; - assign _dfoo1898 = - (source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1830 ; - assign _dfoo19 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo190 = - (source_id__h62145 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo122 ; - assign _dfoo1900 = - (source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1832 ; - assign _dfoo1902 = - (source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1834 ; - assign _dfoo1904 = - (source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104) ? - wdata32__h26930[3] : - _dfoo1836 ; - assign _dfoo1905 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1769 ; - assign _dfoo1906 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1838 ; - assign _dfoo1907 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1771 ; - assign _dfoo1908 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1840 ; - assign _dfoo1909 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1773 ; - assign _dfoo191 = - source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo55 ; - assign _dfoo1910 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1842 ; - assign _dfoo1911 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1775 ; - assign _dfoo1912 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1844 ; - assign _dfoo1913 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1777 ; - assign _dfoo1914 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1846 ; - assign _dfoo1915 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1779 ; - assign _dfoo1916 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1848 ; - assign _dfoo1917 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1781 ; - assign _dfoo1918 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1850 ; - assign _dfoo1919 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1783 ; - assign _dfoo192 = - (source_id__h62145 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo124 ; - assign _dfoo1920 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1852 ; - assign _dfoo1921 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1785 ; - assign _dfoo1922 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1854 ; - assign _dfoo1923 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1787 ; - assign _dfoo1924 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1856 ; - assign _dfoo1925 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1789 ; - assign _dfoo1926 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1858 ; - assign _dfoo1927 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1791 ; - assign _dfoo1928 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1860 ; - assign _dfoo1929 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1793 ; - assign _dfoo193 = - source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo57 ; - assign _dfoo1930 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1862 ; - assign _dfoo1931 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1795 ; - assign _dfoo1932 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1864 ; - assign _dfoo1933 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1797 ; - assign _dfoo1934 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1866 ; - assign _dfoo1935 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1799 ; - assign _dfoo1936 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1868 ; - assign _dfoo1937 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1801 ; - assign _dfoo1938 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1870 ; - assign _dfoo1939 = - source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1803 ; - assign _dfoo194 = - (source_id__h62145 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo126 ; - assign _dfoo1940 = - (source_id__h30685 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1872 ; - assign _dfoo1941 = - source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1805 ; - assign _dfoo1942 = - (source_id__h30685 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1874 ; - assign _dfoo1943 = - source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1807 ; - assign _dfoo1944 = - (source_id__h30685 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1876 ; - assign _dfoo1945 = - source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1809 ; - assign _dfoo1946 = - (source_id__h30685 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1878 ; - assign _dfoo1947 = - source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1811 ; - assign _dfoo1948 = - (source_id__h30685 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1880 ; - assign _dfoo1949 = - source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1813 ; - assign _dfoo195 = - source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo59 ; - assign _dfoo1950 = - (source_id__h30685 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1882 ; - assign _dfoo1951 = - source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1815 ; - assign _dfoo1952 = - (source_id__h30685 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1884 ; - assign _dfoo1953 = - source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1817 ; - assign _dfoo1954 = - (source_id__h30685 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1886 ; - assign _dfoo1955 = - source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1819 ; - assign _dfoo1956 = - (source_id__h30685 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1888 ; - assign _dfoo1957 = - source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1821 ; - assign _dfoo1958 = - (source_id__h30685 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1890 ; - assign _dfoo1959 = - source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1823 ; - assign _dfoo196 = - (source_id__h62145 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo128 ; - assign _dfoo1960 = - (source_id__h30685 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1892 ; - assign _dfoo1961 = - source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1825 ; - assign _dfoo1962 = - (source_id__h30685 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1894 ; - assign _dfoo1963 = - source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1827 ; - assign _dfoo1964 = - (source_id__h30685 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1896 ; - assign _dfoo1965 = - source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1829 ; - assign _dfoo1966 = - (source_id__h30685 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1898 ; - assign _dfoo1967 = - source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1831 ; - assign _dfoo1968 = - (source_id__h30685 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1900 ; - assign _dfoo1969 = - source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1833 ; - assign _dfoo197 = - source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo61 ; - assign _dfoo1970 = - (source_id__h30685 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1902 ; - assign _dfoo1971 = - source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043 || - source_id__h31895 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1104 || - _dfoo1835 ; - assign _dfoo1972 = - (source_id__h30685 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1043) ? - wdata32__h26930[2] : - _dfoo1904 ; - assign _dfoo1974 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1906 ; - assign _dfoo1976 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1908 ; - assign _dfoo1978 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1910 ; - assign _dfoo198 = - (source_id__h62145 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo130 ; - assign _dfoo1980 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1912 ; - assign _dfoo1982 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1914 ; - assign _dfoo1984 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1916 ; - assign _dfoo1986 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1918 ; - assign _dfoo1988 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1920 ; - assign _dfoo199 = - source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo63 ; - assign _dfoo1990 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1922 ; - assign _dfoo1992 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1924 ; - assign _dfoo1994 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1926 ; - assign _dfoo1996 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1928 ; - assign _dfoo1998 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1930 ; - assign _dfoo2 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo20 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo200 = - (source_id__h62145 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo132 ; - assign _dfoo2000 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1932 ; - assign _dfoo2002 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1934 ; - assign _dfoo2004 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1936 ; - assign _dfoo2006 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1938 ; - assign _dfoo2008 = - (source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1940 ; - assign _dfoo201 = - source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo65 ; - assign _dfoo2010 = - (source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1942 ; - assign _dfoo2012 = - (source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1944 ; - assign _dfoo2014 = - (source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1946 ; - assign _dfoo2016 = - (source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1948 ; - assign _dfoo2018 = - (source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1950 ; - assign _dfoo202 = - (source_id__h62145 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo134 ; - assign _dfoo2020 = - (source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1952 ; - assign _dfoo2022 = - (source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1954 ; - assign _dfoo2024 = - (source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1956 ; - assign _dfoo2026 = - (source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1958 ; - assign _dfoo2028 = - (source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1960 ; - assign _dfoo203 = - source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629 || - source_id__h63355 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690 || - _dfoo67 ; - assign _dfoo2030 = - (source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1962 ; - assign _dfoo2032 = - (source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1964 ; - assign _dfoo2034 = - (source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1966 ; - assign _dfoo2036 = - (source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1968 ; - assign _dfoo2038 = - (source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1970 ; - assign _dfoo204 = - (source_id__h62145 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2629) ? - wdata32__h26930[28] : - _dfoo136 ; - assign _dfoo2040 = - (source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982) ? - wdata32__h26930[1] : - _dfoo1972 ; - assign _dfoo2041 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1905 ; - assign _dfoo2043 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1907 ; - assign _dfoo2045 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1909 ; - assign _dfoo2047 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1911 ; - assign _dfoo2049 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1913 ; - assign _dfoo2051 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1915 ; - assign _dfoo2053 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1917 ; - assign _dfoo2055 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1919 ; - assign _dfoo2057 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1921 ; - assign _dfoo2059 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1923 ; - assign _dfoo206 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo138 ; - assign _dfoo2061 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1925 ; - assign _dfoo2063 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1927 ; - assign _dfoo2065 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1929 ; - assign _dfoo2067 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1931 ; - assign _dfoo2069 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1933 ; - assign _dfoo2071 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1935 ; - assign _dfoo2073 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1937 ; - assign _dfoo2075 = - source_id_base__h28148 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1939 ; - assign _dfoo2077 = - source_id_base__h28148 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1941 ; - assign _dfoo2079 = - source_id_base__h28148 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1943 ; - assign _dfoo208 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo140 ; - assign _dfoo2081 = - source_id_base__h28148 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1945 ; - assign _dfoo2083 = - source_id_base__h28148 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1947 ; - assign _dfoo2085 = - source_id_base__h28148 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1949 ; - assign _dfoo2087 = - source_id_base__h28148 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1951 ; - assign _dfoo2089 = - source_id_base__h28148 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1953 ; - assign _dfoo2091 = - source_id_base__h28148 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1955 ; - assign _dfoo2093 = - source_id_base__h28148 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1957 ; - assign _dfoo2095 = - source_id_base__h28148 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1959 ; - assign _dfoo2097 = - source_id_base__h28148 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1961 ; - assign _dfoo2099 = - source_id_base__h28148 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1963 ; - assign _dfoo21 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo210 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo142 ; - assign _dfoo2101 = - source_id_base__h28148 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1965 ; - assign _dfoo2103 = - source_id_base__h28148 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1967 ; - assign _dfoo2105 = - source_id_base__h28148 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1969 ; - assign _dfoo2107 = - source_id_base__h28148 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 || - source_id__h29475 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d982 || - _dfoo1971 ; - assign _dfoo212 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo144 ; - assign _dfoo214 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo146 ; - assign _dfoo216 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo148 ; - assign _dfoo218 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo150 ; - assign _dfoo22 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo220 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo152 ; - assign _dfoo222 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo154 ; - assign _dfoo224 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo156 ; - assign _dfoo226 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo158 ; - assign _dfoo228 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo160 ; - assign _dfoo23 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo230 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo162 ; - assign _dfoo232 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo164 ; - assign _dfoo234 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo166 ; - assign _dfoo236 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo168 ; - assign _dfoo238 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo170 ; - assign _dfoo24 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo240 = - (source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo172 ; - assign _dfoo242 = - (source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo174 ; - assign _dfoo244 = - (source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo176 ; - assign _dfoo246 = - (source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo178 ; - assign _dfoo248 = - (source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo180 ; - assign _dfoo25 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo250 = - (source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo182 ; - assign _dfoo252 = - (source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo184 ; - assign _dfoo254 = - (source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo186 ; - assign _dfoo256 = - (source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo188 ; - assign _dfoo258 = - (source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo190 ; - assign _dfoo26 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo260 = - (source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo192 ; - assign _dfoo262 = - (source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo194 ; - assign _dfoo264 = - (source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo196 ; - assign _dfoo266 = - (source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo198 ; - assign _dfoo268 = - (source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo200 ; - assign _dfoo27 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo270 = - (source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo202 ; - assign _dfoo272 = - (source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568) ? - wdata32__h26930[27] : - _dfoo204 ; - assign _dfoo273 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo137 ; - assign _dfoo274 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo206 ; - assign _dfoo275 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo139 ; - assign _dfoo276 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo208 ; - assign _dfoo277 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo141 ; - assign _dfoo278 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo210 ; - assign _dfoo279 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo143 ; - assign _dfoo28 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo280 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo212 ; - assign _dfoo281 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo145 ; - assign _dfoo282 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo214 ; - assign _dfoo283 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo147 ; - assign _dfoo284 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo216 ; - assign _dfoo285 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo149 ; - assign _dfoo286 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo218 ; - assign _dfoo287 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo151 ; - assign _dfoo288 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo220 ; - assign _dfoo289 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo153 ; - assign _dfoo29 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo290 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo222 ; - assign _dfoo291 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo155 ; - assign _dfoo292 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo224 ; - assign _dfoo293 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo157 ; - assign _dfoo294 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo226 ; - assign _dfoo295 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo159 ; - assign _dfoo296 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo228 ; - assign _dfoo297 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo161 ; - assign _dfoo298 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo230 ; - assign _dfoo299 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo163 ; - assign _dfoo3 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo30 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo300 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo232 ; - assign _dfoo301 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo165 ; - assign _dfoo302 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo234 ; - assign _dfoo303 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo167 ; - assign _dfoo304 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo236 ; - assign _dfoo305 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo169 ; - assign _dfoo306 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo238 ; - assign _dfoo307 = - source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo171 ; - assign _dfoo308 = - (source_id__h59725 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo240 ; - assign _dfoo309 = - source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo173 ; - assign _dfoo31 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo310 = - (source_id__h59725 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo242 ; - assign _dfoo311 = - source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo175 ; - assign _dfoo312 = - (source_id__h59725 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo244 ; - assign _dfoo313 = - source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo177 ; - assign _dfoo314 = - (source_id__h59725 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo246 ; - assign _dfoo315 = - source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo179 ; - assign _dfoo316 = - (source_id__h59725 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo248 ; - assign _dfoo317 = - source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo181 ; - assign _dfoo318 = - (source_id__h59725 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo250 ; - assign _dfoo319 = - source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo183 ; - assign _dfoo32 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo320 = - (source_id__h59725 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo252 ; - assign _dfoo321 = - source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo185 ; - assign _dfoo322 = - (source_id__h59725 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo254 ; - assign _dfoo323 = - source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo187 ; - assign _dfoo324 = - (source_id__h59725 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo256 ; - assign _dfoo325 = - source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo189 ; - assign _dfoo326 = - (source_id__h59725 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo258 ; - assign _dfoo327 = - source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo191 ; - assign _dfoo328 = - (source_id__h59725 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo260 ; - assign _dfoo329 = - source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo193 ; - assign _dfoo33 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo330 = - (source_id__h59725 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo262 ; - assign _dfoo331 = - source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo195 ; - assign _dfoo332 = - (source_id__h59725 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo264 ; - assign _dfoo333 = - source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo197 ; - assign _dfoo334 = - (source_id__h59725 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo266 ; - assign _dfoo335 = - source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo199 ; - assign _dfoo336 = - (source_id__h59725 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo268 ; - assign _dfoo337 = - source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo201 ; - assign _dfoo338 = - (source_id__h59725 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo270 ; - assign _dfoo339 = - source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507 || - source_id__h60935 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2568 || - _dfoo203 ; - assign _dfoo34 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo340 = - (source_id__h59725 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2507) ? - wdata32__h26930[26] : - _dfoo272 ; - assign _dfoo342 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo274 ; - assign _dfoo344 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo276 ; - assign _dfoo346 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo278 ; - assign _dfoo348 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo280 ; - assign _dfoo35 = - source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo350 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo282 ; - assign _dfoo352 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo284 ; - assign _dfoo354 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo286 ; - assign _dfoo356 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo288 ; - assign _dfoo358 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo290 ; - assign _dfoo36 = - (source_id__h64565 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo360 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo292 ; - assign _dfoo362 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo294 ; - assign _dfoo364 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo296 ; - assign _dfoo366 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo298 ; - assign _dfoo368 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo300 ; - assign _dfoo37 = - source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo370 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo302 ; - assign _dfoo372 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo304 ; - assign _dfoo374 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo306 ; - assign _dfoo376 = - (source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo308 ; - assign _dfoo378 = - (source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo310 ; - assign _dfoo38 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo380 = - (source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo312 ; - assign _dfoo382 = - (source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo314 ; - assign _dfoo384 = - (source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo316 ; - assign _dfoo386 = - (source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo318 ; - assign _dfoo388 = - (source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo320 ; - assign _dfoo39 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo390 = - (source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo322 ; - assign _dfoo392 = - (source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo324 ; - assign _dfoo394 = - (source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo326 ; - assign _dfoo396 = - (source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo328 ; - assign _dfoo398 = - (source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo330 ; - assign _dfoo4 = - (source_id__h64565 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo40 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo400 = - (source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo332 ; - assign _dfoo402 = - (source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo334 ; - assign _dfoo404 = - (source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo336 ; - assign _dfoo406 = - (source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo338 ; - assign _dfoo408 = - (source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446) ? - wdata32__h26930[25] : - _dfoo340 ; - assign _dfoo409 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo273 ; - assign _dfoo41 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo410 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo342 ; - assign _dfoo411 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo275 ; - assign _dfoo412 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo344 ; - assign _dfoo413 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo277 ; - assign _dfoo414 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo346 ; - assign _dfoo415 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo279 ; - assign _dfoo416 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo348 ; - assign _dfoo417 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo281 ; - assign _dfoo418 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo350 ; - assign _dfoo419 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo283 ; - assign _dfoo42 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo420 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo352 ; - assign _dfoo421 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo285 ; - assign _dfoo422 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo354 ; - assign _dfoo423 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo287 ; - assign _dfoo424 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo356 ; - assign _dfoo425 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo289 ; - assign _dfoo426 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo358 ; - assign _dfoo427 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo291 ; - assign _dfoo428 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo360 ; - assign _dfoo429 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo293 ; - assign _dfoo43 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo430 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo362 ; - assign _dfoo431 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo295 ; - assign _dfoo432 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo364 ; - assign _dfoo433 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo297 ; - assign _dfoo434 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo366 ; - assign _dfoo435 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo299 ; - assign _dfoo436 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo368 ; - assign _dfoo437 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo301 ; - assign _dfoo438 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo370 ; - assign _dfoo439 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo303 ; - assign _dfoo44 = - (source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo440 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo372 ; - assign _dfoo441 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo305 ; - assign _dfoo442 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo374 ; - assign _dfoo443 = - source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo307 ; - assign _dfoo444 = - (source_id__h57305 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo376 ; - assign _dfoo445 = - source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo309 ; - assign _dfoo446 = - (source_id__h57305 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo378 ; - assign _dfoo447 = - source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo311 ; - assign _dfoo448 = - (source_id__h57305 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo380 ; - assign _dfoo449 = - source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo313 ; - assign _dfoo45 = - source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo450 = - (source_id__h57305 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo382 ; - assign _dfoo451 = - source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo315 ; - assign _dfoo452 = - (source_id__h57305 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo384 ; - assign _dfoo453 = - source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo317 ; - assign _dfoo454 = - (source_id__h57305 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo386 ; - assign _dfoo455 = - source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo319 ; - assign _dfoo456 = - (source_id__h57305 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo388 ; - assign _dfoo457 = - source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo321 ; - assign _dfoo458 = - (source_id__h57305 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo390 ; - assign _dfoo459 = - source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo323 ; - assign _dfoo46 = - (source_id__h64565 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo460 = - (source_id__h57305 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo392 ; - assign _dfoo461 = - source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo325 ; - assign _dfoo462 = - (source_id__h57305 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo394 ; - assign _dfoo463 = - source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo327 ; - assign _dfoo464 = - (source_id__h57305 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo396 ; - assign _dfoo465 = - source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo329 ; - assign _dfoo466 = - (source_id__h57305 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo398 ; - assign _dfoo467 = - source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo331 ; - assign _dfoo468 = - (source_id__h57305 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo400 ; - assign _dfoo469 = - source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo333 ; - assign _dfoo47 = - source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo470 = - (source_id__h57305 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo402 ; - assign _dfoo471 = - source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo335 ; - assign _dfoo472 = - (source_id__h57305 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo404 ; - assign _dfoo473 = - source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo337 ; - assign _dfoo474 = - (source_id__h57305 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo406 ; - assign _dfoo475 = - source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385 || - source_id__h58515 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2446 || - _dfoo339 ; - assign _dfoo476 = - (source_id__h57305 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2385) ? - wdata32__h26930[24] : - _dfoo408 ; - assign _dfoo478 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo410 ; - assign _dfoo48 = - (source_id__h64565 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo480 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo412 ; - assign _dfoo482 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo414 ; - assign _dfoo484 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo416 ; - assign _dfoo486 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo418 ; - assign _dfoo488 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo420 ; - assign _dfoo49 = - source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo490 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo422 ; - assign _dfoo492 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo424 ; - assign _dfoo494 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo426 ; - assign _dfoo496 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo428 ; - assign _dfoo498 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo430 ; - assign _dfoo5 = - source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo50 = - (source_id__h64565 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo500 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo432 ; - assign _dfoo502 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo434 ; - assign _dfoo504 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo436 ; - assign _dfoo506 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo438 ; - assign _dfoo508 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo440 ; - assign _dfoo51 = - source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo510 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo442 ; - assign _dfoo512 = - (source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo444 ; - assign _dfoo514 = - (source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo446 ; - assign _dfoo516 = - (source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo448 ; - assign _dfoo518 = - (source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo450 ; - assign _dfoo52 = - (source_id__h64565 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo520 = - (source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo452 ; - assign _dfoo522 = - (source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo454 ; - assign _dfoo524 = - (source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo456 ; - assign _dfoo526 = - (source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo458 ; - assign _dfoo528 = - (source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo460 ; - assign _dfoo53 = - source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo530 = - (source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo462 ; - assign _dfoo532 = - (source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo464 ; - assign _dfoo534 = - (source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo466 ; - assign _dfoo536 = - (source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo468 ; - assign _dfoo538 = - (source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo470 ; - assign _dfoo54 = - (source_id__h64565 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo540 = - (source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo472 ; - assign _dfoo542 = - (source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo474 ; - assign _dfoo544 = - (source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324) ? - wdata32__h26930[23] : - _dfoo476 ; - assign _dfoo545 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo409 ; - assign _dfoo546 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo478 ; - assign _dfoo547 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo411 ; - assign _dfoo548 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo480 ; - assign _dfoo549 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo413 ; - assign _dfoo55 = - source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo550 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo482 ; - assign _dfoo551 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo415 ; - assign _dfoo552 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo484 ; - assign _dfoo553 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo417 ; - assign _dfoo554 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo486 ; - assign _dfoo555 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo419 ; - assign _dfoo556 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo488 ; - assign _dfoo557 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo421 ; - assign _dfoo558 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo490 ; - assign _dfoo559 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo423 ; - assign _dfoo56 = - (source_id__h64565 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo560 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo492 ; - assign _dfoo561 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo425 ; - assign _dfoo562 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo494 ; - assign _dfoo563 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo427 ; - assign _dfoo564 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo496 ; - assign _dfoo565 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo429 ; - assign _dfoo566 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo498 ; - assign _dfoo567 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo431 ; - assign _dfoo568 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo500 ; - assign _dfoo569 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo433 ; - assign _dfoo57 = - source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo570 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo502 ; - assign _dfoo571 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo435 ; - assign _dfoo572 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo504 ; - assign _dfoo573 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo437 ; - assign _dfoo574 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo506 ; - assign _dfoo575 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo439 ; - assign _dfoo576 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo508 ; - assign _dfoo577 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo441 ; - assign _dfoo578 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo510 ; - assign _dfoo579 = - source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo443 ; - assign _dfoo58 = - (source_id__h64565 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo580 = - (source_id__h54885 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo512 ; - assign _dfoo581 = - source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo445 ; - assign _dfoo582 = - (source_id__h54885 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo514 ; - assign _dfoo583 = - source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo447 ; - assign _dfoo584 = - (source_id__h54885 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo516 ; - assign _dfoo585 = - source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo449 ; - assign _dfoo586 = - (source_id__h54885 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo518 ; - assign _dfoo587 = - source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo451 ; - assign _dfoo588 = - (source_id__h54885 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo520 ; - assign _dfoo589 = - source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo453 ; - assign _dfoo59 = - source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo590 = - (source_id__h54885 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo522 ; - assign _dfoo591 = - source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo455 ; - assign _dfoo592 = - (source_id__h54885 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo524 ; - assign _dfoo593 = - source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo457 ; - assign _dfoo594 = - (source_id__h54885 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo526 ; - assign _dfoo595 = - source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo459 ; - assign _dfoo596 = - (source_id__h54885 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo528 ; - assign _dfoo597 = - source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo461 ; - assign _dfoo598 = - (source_id__h54885 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo530 ; - assign _dfoo599 = - source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo463 ; - assign _dfoo6 = - (source_id__h64565 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo60 = - (source_id__h64565 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo600 = - (source_id__h54885 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo532 ; - assign _dfoo601 = - source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo465 ; - assign _dfoo602 = - (source_id__h54885 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo534 ; - assign _dfoo603 = - source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo467 ; - assign _dfoo604 = - (source_id__h54885 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo536 ; - assign _dfoo605 = - source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo469 ; - assign _dfoo606 = - (source_id__h54885 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo538 ; - assign _dfoo607 = - source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo471 ; - assign _dfoo608 = - (source_id__h54885 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo540 ; - assign _dfoo609 = - source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo473 ; - assign _dfoo61 = - source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo610 = - (source_id__h54885 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo542 ; - assign _dfoo611 = - source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263 || - source_id__h56095 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2324 || - _dfoo475 ; - assign _dfoo612 = - (source_id__h54885 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2263) ? - wdata32__h26930[22] : - _dfoo544 ; - assign _dfoo614 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo546 ; - assign _dfoo616 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo548 ; - assign _dfoo618 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo550 ; - assign _dfoo62 = - (source_id__h64565 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo620 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo552 ; - assign _dfoo622 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo554 ; - assign _dfoo624 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo556 ; - assign _dfoo626 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo558 ; - assign _dfoo628 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo560 ; - assign _dfoo63 = - source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo630 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo562 ; - assign _dfoo632 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo564 ; - assign _dfoo634 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo566 ; - assign _dfoo636 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo568 ; - assign _dfoo638 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo570 ; - assign _dfoo64 = - (source_id__h64565 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo640 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo572 ; - assign _dfoo642 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo574 ; - assign _dfoo644 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo576 ; - assign _dfoo646 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo578 ; - assign _dfoo648 = - (source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo580 ; - assign _dfoo65 = - source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo650 = - (source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo582 ; - assign _dfoo652 = - (source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo584 ; - assign _dfoo654 = - (source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo586 ; - assign _dfoo656 = - (source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo588 ; - assign _dfoo658 = - (source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo590 ; - assign _dfoo66 = - (source_id__h64565 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo660 = - (source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo592 ; - assign _dfoo662 = - (source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo594 ; - assign _dfoo664 = - (source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo596 ; - assign _dfoo666 = - (source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo598 ; - assign _dfoo668 = - (source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo600 ; - assign _dfoo67 = - source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo670 = - (source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo602 ; - assign _dfoo672 = - (source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo604 ; - assign _dfoo674 = - (source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo606 ; - assign _dfoo676 = - (source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo608 ; - assign _dfoo678 = - (source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo610 ; - assign _dfoo68 = - (source_id__h64565 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo680 = - (source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202) ? - wdata32__h26930[21] : - _dfoo612 ; - assign _dfoo681 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo545 ; - assign _dfoo682 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo614 ; - assign _dfoo683 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo547 ; - assign _dfoo684 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo616 ; - assign _dfoo685 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo549 ; - assign _dfoo686 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo618 ; - assign _dfoo687 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo551 ; - assign _dfoo688 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo620 ; - assign _dfoo689 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo553 ; - assign _dfoo690 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo622 ; - assign _dfoo691 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo555 ; - assign _dfoo692 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo624 ; - assign _dfoo693 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo557 ; - assign _dfoo694 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo626 ; - assign _dfoo695 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo559 ; - assign _dfoo696 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo628 ; - assign _dfoo697 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo561 ; - assign _dfoo698 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo630 ; - assign _dfoo699 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo563 ; - assign _dfoo7 = - source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo70 = - (source_id__h63355 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo2 ; - assign _dfoo700 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo632 ; - assign _dfoo701 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo565 ; - assign _dfoo702 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo634 ; - assign _dfoo703 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo567 ; - assign _dfoo704 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo636 ; - assign _dfoo705 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo569 ; - assign _dfoo706 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo638 ; - assign _dfoo707 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo571 ; - assign _dfoo708 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo640 ; - assign _dfoo709 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo573 ; - assign _dfoo710 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo642 ; - assign _dfoo711 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo575 ; - assign _dfoo712 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo644 ; - assign _dfoo713 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo577 ; - assign _dfoo714 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo646 ; - assign _dfoo715 = - source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo579 ; - assign _dfoo716 = - (source_id__h52465 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo648 ; - assign _dfoo717 = - source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo581 ; - assign _dfoo718 = - (source_id__h52465 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo650 ; - assign _dfoo719 = - source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo583 ; - assign _dfoo72 = - (source_id__h63355 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo4 ; - assign _dfoo720 = - (source_id__h52465 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo652 ; - assign _dfoo721 = - source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo585 ; - assign _dfoo722 = - (source_id__h52465 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo654 ; - assign _dfoo723 = - source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo587 ; - assign _dfoo724 = - (source_id__h52465 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo656 ; - assign _dfoo725 = - source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo589 ; - assign _dfoo726 = - (source_id__h52465 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo658 ; - assign _dfoo727 = - source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo591 ; - assign _dfoo728 = - (source_id__h52465 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo660 ; - assign _dfoo729 = - source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo593 ; - assign _dfoo730 = - (source_id__h52465 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo662 ; - assign _dfoo731 = - source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo595 ; - assign _dfoo732 = - (source_id__h52465 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo664 ; - assign _dfoo733 = - source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo597 ; - assign _dfoo734 = - (source_id__h52465 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo666 ; - assign _dfoo735 = - source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo599 ; - assign _dfoo736 = - (source_id__h52465 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo668 ; - assign _dfoo737 = - source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo601 ; - assign _dfoo738 = - (source_id__h52465 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo670 ; - assign _dfoo739 = - source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo603 ; - assign _dfoo74 = - (source_id__h63355 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo6 ; - assign _dfoo740 = - (source_id__h52465 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo672 ; - assign _dfoo741 = - source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo605 ; - assign _dfoo742 = - (source_id__h52465 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo674 ; - assign _dfoo743 = - source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo607 ; - assign _dfoo744 = - (source_id__h52465 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo676 ; - assign _dfoo745 = - source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo609 ; - assign _dfoo746 = - (source_id__h52465 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo678 ; - assign _dfoo747 = - source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141 || - source_id__h53675 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2202 || - _dfoo611 ; - assign _dfoo748 = - (source_id__h52465 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2141) ? - wdata32__h26930[20] : - _dfoo680 ; - assign _dfoo750 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo682 ; - assign _dfoo752 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo684 ; - assign _dfoo754 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo686 ; - assign _dfoo756 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo688 ; - assign _dfoo758 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo690 ; - assign _dfoo76 = - (source_id__h63355 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo8 ; - assign _dfoo760 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo692 ; - assign _dfoo762 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo694 ; - assign _dfoo764 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo696 ; - assign _dfoo766 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo698 ; - assign _dfoo768 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo700 ; - assign _dfoo770 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo702 ; - assign _dfoo772 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo704 ; - assign _dfoo774 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo706 ; - assign _dfoo776 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo708 ; - assign _dfoo778 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo710 ; - assign _dfoo78 = - (source_id__h63355 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo10 ; - assign _dfoo780 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo712 ; - assign _dfoo782 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo714 ; - assign _dfoo784 = - (source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo716 ; - assign _dfoo786 = - (source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo718 ; - assign _dfoo788 = - (source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo720 ; - assign _dfoo790 = - (source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo722 ; - assign _dfoo792 = - (source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo724 ; - assign _dfoo794 = - (source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo726 ; - assign _dfoo796 = - (source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo728 ; - assign _dfoo798 = - (source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo730 ; - assign _dfoo8 = - (source_id__h64565 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751) ? - wdata32__h26930[30] : - wdata32__h26930[31] ; - assign _dfoo80 = - (source_id__h63355 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo12 ; - assign _dfoo800 = - (source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo732 ; - assign _dfoo802 = - (source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo734 ; - assign _dfoo804 = - (source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo736 ; - assign _dfoo806 = - (source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo738 ; - assign _dfoo808 = - (source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo740 ; - assign _dfoo810 = - (source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo742 ; - assign _dfoo812 = - (source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo744 ; - assign _dfoo814 = - (source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo746 ; - assign _dfoo816 = - (source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080) ? - wdata32__h26930[19] : - _dfoo748 ; - assign _dfoo817 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo681 ; - assign _dfoo818 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo750 ; - assign _dfoo819 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo683 ; - assign _dfoo82 = - (source_id__h63355 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo14 ; - assign _dfoo820 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo752 ; - assign _dfoo821 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo685 ; - assign _dfoo822 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo754 ; - assign _dfoo823 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo687 ; - assign _dfoo824 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo756 ; - assign _dfoo825 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo689 ; - assign _dfoo826 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo758 ; - assign _dfoo827 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo691 ; - assign _dfoo828 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo760 ; - assign _dfoo829 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo693 ; - assign _dfoo830 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo762 ; - assign _dfoo831 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo695 ; - assign _dfoo832 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo764 ; - assign _dfoo833 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo697 ; - assign _dfoo834 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo766 ; - assign _dfoo835 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo699 ; - assign _dfoo836 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo768 ; - assign _dfoo837 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo701 ; - assign _dfoo838 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo770 ; - assign _dfoo839 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo703 ; - assign _dfoo84 = - (source_id__h63355 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo16 ; - assign _dfoo840 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo772 ; - assign _dfoo841 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo705 ; - assign _dfoo842 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo774 ; - assign _dfoo843 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo707 ; - assign _dfoo844 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo776 ; - assign _dfoo845 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo709 ; - assign _dfoo846 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo778 ; - assign _dfoo847 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo711 ; - assign _dfoo848 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo780 ; - assign _dfoo849 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo713 ; - assign _dfoo850 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo782 ; - assign _dfoo851 = - source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo715 ; - assign _dfoo852 = - (source_id__h50045 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo784 ; - assign _dfoo853 = - source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo717 ; - assign _dfoo854 = - (source_id__h50045 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo786 ; - assign _dfoo855 = - source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo719 ; - assign _dfoo856 = - (source_id__h50045 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo788 ; - assign _dfoo857 = - source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo721 ; - assign _dfoo858 = - (source_id__h50045 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo790 ; - assign _dfoo859 = - source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo723 ; - assign _dfoo86 = - (source_id__h63355 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo18 ; - assign _dfoo860 = - (source_id__h50045 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo792 ; - assign _dfoo861 = - source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo725 ; - assign _dfoo862 = - (source_id__h50045 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo794 ; - assign _dfoo863 = - source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo727 ; - assign _dfoo864 = - (source_id__h50045 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo796 ; - assign _dfoo865 = - source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo729 ; - assign _dfoo866 = - (source_id__h50045 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo798 ; - assign _dfoo867 = - source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo731 ; - assign _dfoo868 = - (source_id__h50045 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo800 ; - assign _dfoo869 = - source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo733 ; - assign _dfoo870 = - (source_id__h50045 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo802 ; - assign _dfoo871 = - source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo735 ; - assign _dfoo872 = - (source_id__h50045 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo804 ; - assign _dfoo873 = - source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo737 ; - assign _dfoo874 = - (source_id__h50045 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo806 ; - assign _dfoo875 = - source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo739 ; - assign _dfoo876 = - (source_id__h50045 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo808 ; - assign _dfoo877 = - source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo741 ; - assign _dfoo878 = - (source_id__h50045 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo810 ; - assign _dfoo879 = - source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo743 ; - assign _dfoo88 = - (source_id__h63355 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo20 ; - assign _dfoo880 = - (source_id__h50045 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo812 ; - assign _dfoo881 = - source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo745 ; - assign _dfoo882 = - (source_id__h50045 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo814 ; - assign _dfoo883 = - source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019 || - source_id__h51255 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2080 || - _dfoo747 ; - assign _dfoo884 = - (source_id__h50045 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2019) ? - wdata32__h26930[18] : - _dfoo816 ; - assign _dfoo886 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo818 ; - assign _dfoo888 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo820 ; - assign _dfoo890 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo822 ; - assign _dfoo892 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo824 ; - assign _dfoo894 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo826 ; - assign _dfoo896 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo828 ; - assign _dfoo898 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo830 ; - assign _dfoo9 = - source_id__h64565 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2751 || - source_id__h65775 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2812 ; - assign _dfoo90 = - (source_id__h63355 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo22 ; - assign _dfoo900 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo832 ; - assign _dfoo902 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo834 ; - assign _dfoo904 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo836 ; - assign _dfoo906 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo838 ; - assign _dfoo908 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo840 ; - assign _dfoo910 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo842 ; - assign _dfoo912 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo844 ; - assign _dfoo914 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo846 ; - assign _dfoo916 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo848 ; - assign _dfoo918 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo850 ; - assign _dfoo92 = - (source_id__h63355 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo24 ; - assign _dfoo920 = - (source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo852 ; - assign _dfoo922 = - (source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo854 ; - assign _dfoo924 = - (source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo856 ; - assign _dfoo926 = - (source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo858 ; - assign _dfoo928 = - (source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo860 ; - assign _dfoo930 = - (source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo862 ; - assign _dfoo932 = - (source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo864 ; - assign _dfoo934 = - (source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo866 ; - assign _dfoo936 = - (source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo868 ; - assign _dfoo938 = - (source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo870 ; - assign _dfoo94 = - (source_id__h63355 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo26 ; - assign _dfoo940 = - (source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo872 ; - assign _dfoo942 = - (source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo874 ; - assign _dfoo944 = - (source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo876 ; - assign _dfoo946 = - (source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo878 ; - assign _dfoo948 = - (source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo880 ; - assign _dfoo950 = - (source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo882 ; - assign _dfoo952 = - (source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958) ? - wdata32__h26930[17] : - _dfoo884 ; - assign _dfoo953 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo817 ; - assign _dfoo954 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo886 ; - assign _dfoo955 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo819 ; - assign _dfoo956 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo888 ; - assign _dfoo957 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo821 ; - assign _dfoo958 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo890 ; - assign _dfoo959 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo823 ; - assign _dfoo96 = - (source_id__h63355 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo28 ; - assign _dfoo960 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo892 ; - assign _dfoo961 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo825 ; - assign _dfoo962 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo894 ; - assign _dfoo963 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo827 ; - assign _dfoo964 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo896 ; - assign _dfoo965 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo829 ; - assign _dfoo966 = - (source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo898 ; - assign _dfoo967 = - source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo831 ; - assign _dfoo968 = - (source_id__h47625 == 10'd9 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo900 ; - assign _dfoo969 = - source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo833 ; - assign _dfoo970 = - (source_id__h47625 == 10'd8 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo902 ; - assign _dfoo971 = - source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo835 ; - assign _dfoo972 = - (source_id__h47625 == 10'd7 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo904 ; - assign _dfoo973 = - source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo837 ; - assign _dfoo974 = - (source_id__h47625 == 10'd6 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo906 ; - assign _dfoo975 = - source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo839 ; - assign _dfoo976 = - (source_id__h47625 == 10'd5 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo908 ; - assign _dfoo977 = - source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo841 ; - assign _dfoo978 = - (source_id__h47625 == 10'd4 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo910 ; - assign _dfoo979 = - source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo843 ; - assign _dfoo98 = - (source_id__h63355 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2690) ? - wdata32__h26930[29] : - _dfoo30 ; - assign _dfoo980 = - (source_id__h47625 == 10'd3 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo912 ; - assign _dfoo981 = - source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo845 ; - assign _dfoo982 = - (source_id__h47625 == 10'd2 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo914 ; - assign _dfoo983 = - source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo847 ; - assign _dfoo984 = - (source_id__h47625 == 10'd1 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo916 ; - assign _dfoo985 = - source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo849 ; - assign _dfoo986 = - (source_id__h47625 == 10'd0 && - addr_offset__h26929[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo918 ; - assign _dfoo987 = - source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo851 ; - assign _dfoo988 = - (source_id__h47625 == 10'd16 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo920 ; - assign _dfoo989 = - source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo853 ; - assign _dfoo990 = - (source_id__h47625 == 10'd15 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo922 ; - assign _dfoo991 = - source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo855 ; - assign _dfoo992 = - (source_id__h47625 == 10'd14 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo924 ; - assign _dfoo993 = - source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo857 ; - assign _dfoo994 = - (source_id__h47625 == 10'd13 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo926 ; - assign _dfoo995 = - source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo859 ; - assign _dfoo996 = - (source_id__h47625 == 10'd12 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo928 ; - assign _dfoo997 = - source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo861 ; - assign _dfoo998 = - (source_id__h47625 == 10'd11 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897) ? - wdata32__h26930[16] : - _dfoo930 ; - assign _dfoo999 = - source_id__h47625 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1897 || - source_id__h48835 == 10'd10 && - addr_offset__h26929[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1958 || - _dfoo863 ; - assign a__h71312 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 ; - assign a__h73317 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 ; - assign addr_offset__h13216 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26929 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71313 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3106 ; - assign b__h73318 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3200 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = - addr_offset__h13216 < 64'h0000000000003000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = - addr_offset__h13216[11:7] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 = - addr_offset__h13216 < 64'h0000000000001000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 = - addr_offset__h13216[11:2] <= 10'd16 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 = - addr_offset__h13216[16:12] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 = - addr_offset__h13216 < 64'h0000000000002000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = - source_id_base__h13630 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 = - addr_offset__h26929[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2886 = - addr_offset__h26929[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2888 = - addr_offset__h26929[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2883 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 = - addr_offset__h26929 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 = - addr_offset__h26929[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d863 = - addr_offset__h26929[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d865 = - addr_offset__h26929[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d867 = - addr_offset__h26929[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d869 = - addr_offset__h26929[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d871 = - addr_offset__h26929[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d873 = - addr_offset__h26929[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d875 = - addr_offset__h26929[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d877 = - addr_offset__h26929[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d879 = - addr_offset__h26929[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d881 = - addr_offset__h26929[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d883 = - addr_offset__h26929[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d885 = - addr_offset__h26929[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d887 = - addr_offset__h26929[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d889 = - addr_offset__h26929[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d891 = - addr_offset__h26929[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d893 = - addr_offset__h26929[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849 && - m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 = - addr_offset__h26929 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 = - source_id_base__h28148 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26929 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915 = - addr_offset__h26929[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d921 = - addr_offset__h26929[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d957 = - addr_offset__h26929[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d918 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3060 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3056 && - m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3154 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3150 && - m_vvrg_ie_1_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = - m_vrg_source_ip_10 && - m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3065 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3061 && - m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3159 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3155 && - m_vvrg_ie_1_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = - m_vrg_source_ip_11 && - m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3070 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3066 && - m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3164 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3160 && - m_vvrg_ie_1_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = - m_vrg_source_ip_12 && - m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3075 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3071 && - m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3169 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3165 && - m_vvrg_ie_1_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = - m_vrg_source_ip_13 && - m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 || - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 || - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 || - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 || - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3080 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3076 && - m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3174 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3170 && - m_vvrg_ie_1_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = - m_vrg_source_ip_14 && - m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3085 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3081 && - m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3179 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3175 && - m_vvrg_ie_1_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = - m_vrg_source_ip_15 && - m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3090 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3086 && - m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3184 = - m_vrg_source_ip_16 && - m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3180 && - m_vvrg_ie_1_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = - m_vrg_source_ip_16 && - !m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 || - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 || - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 || - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 ; - assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = - m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3020 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3016 && - m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3114 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3110 && - m_vvrg_ie_1_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = - m_vrg_source_ip_2 && - m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3025 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3021 && - m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3119 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3115 && - m_vvrg_ie_1_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = - m_vrg_source_ip_3 && - m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3030 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3026 && - m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3124 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3120 && - m_vvrg_ie_1_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = - m_vrg_source_ip_4 && - m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3035 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3031 && - m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3129 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3125 && - m_vvrg_ie_1_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = - m_vrg_source_ip_5 && - m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3040 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3036 && - m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3134 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3130 && - m_vvrg_ie_1_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = - m_vrg_source_ip_6 && - m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3045 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3041 && - m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3139 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3135 && - m_vvrg_ie_1_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = - m_vrg_source_ip_7 && - m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 || - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 || - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 || - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 || - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3050 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3046 && - m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3144 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3140 && - m_vvrg_ie_1_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = - m_vrg_source_ip_8 && - m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3055 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3051 && - m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3149 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3145 && - m_vvrg_ie_1_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = - m_vrg_source_ip_9 && - m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 && - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; - assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 = - m_vrg_source_prio_16 <= - (m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? - m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ; - assign max_id__h23959 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ? - 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ; - assign rdata___1__h26404 = { rdata__h26202[31:0], 32'h0 } ; - assign rdata__h26202 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 64'd0 : - y_avValue_fst__h26194 ; - assign rresp__h26203 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 2'b11 : - y_avValue_snd__h26195 ; - assign source_id__h15665 = { addr_offset__h13216[4:0], 5'd31 } ; - assign source_id__h15772 = { addr_offset__h13216[4:0], 5'd30 } ; - assign source_id__h15845 = { addr_offset__h13216[4:0], 5'd29 } ; - assign source_id__h15918 = { addr_offset__h13216[4:0], 5'd28 } ; - assign source_id__h15991 = { addr_offset__h13216[4:0], 5'd27 } ; - assign source_id__h16064 = { addr_offset__h13216[4:0], 5'd26 } ; - assign source_id__h16137 = { addr_offset__h13216[4:0], 5'd25 } ; - assign source_id__h16210 = { addr_offset__h13216[4:0], 5'd24 } ; - assign source_id__h16283 = { addr_offset__h13216[4:0], 5'd23 } ; - assign source_id__h16356 = { addr_offset__h13216[4:0], 5'd22 } ; - assign source_id__h16429 = { addr_offset__h13216[4:0], 5'd21 } ; - assign source_id__h16502 = { addr_offset__h13216[4:0], 5'd20 } ; - assign source_id__h16575 = { addr_offset__h13216[4:0], 5'd19 } ; - assign source_id__h16648 = { addr_offset__h13216[4:0], 5'd18 } ; - assign source_id__h16721 = { addr_offset__h13216[4:0], 5'd17 } ; - assign source_id__h16794 = { addr_offset__h13216[4:0], 5'd16 } ; - assign source_id__h16867 = { addr_offset__h13216[4:0], 5'd15 } ; - assign source_id__h16940 = { addr_offset__h13216[4:0], 5'd14 } ; - assign source_id__h17013 = { addr_offset__h13216[4:0], 5'd13 } ; - assign source_id__h17086 = { addr_offset__h13216[4:0], 5'd12 } ; - assign source_id__h17159 = { addr_offset__h13216[4:0], 5'd11 } ; - assign source_id__h17232 = { addr_offset__h13216[4:0], 5'd10 } ; - assign source_id__h17305 = { addr_offset__h13216[4:0], 5'd9 } ; - assign source_id__h17378 = { addr_offset__h13216[4:0], 5'd8 } ; - assign source_id__h17451 = { addr_offset__h13216[4:0], 5'd7 } ; - assign source_id__h17524 = { addr_offset__h13216[4:0], 5'd6 } ; - assign source_id__h17597 = { addr_offset__h13216[4:0], 5'd5 } ; - assign source_id__h17670 = { addr_offset__h13216[4:0], 5'd4 } ; - assign source_id__h17743 = { addr_offset__h13216[4:0], 5'd3 } ; - assign source_id__h17816 = { addr_offset__h13216[4:0], 5'd2 } ; - assign source_id__h17889 = { addr_offset__h13216[4:0], 5'd1 } ; - assign source_id__h20137 = 10'd31 + source_id_base__h13630 ; - assign source_id__h20313 = 10'd30 + source_id_base__h13630 ; - assign source_id__h20421 = 10'd29 + source_id_base__h13630 ; - assign source_id__h20529 = 10'd28 + source_id_base__h13630 ; - assign source_id__h20637 = 10'd27 + source_id_base__h13630 ; - assign source_id__h20745 = 10'd26 + source_id_base__h13630 ; - assign source_id__h20853 = 10'd25 + source_id_base__h13630 ; - assign source_id__h20961 = 10'd24 + source_id_base__h13630 ; - assign source_id__h21069 = 10'd23 + source_id_base__h13630 ; - assign source_id__h21177 = 10'd22 + source_id_base__h13630 ; - assign source_id__h21285 = 10'd21 + source_id_base__h13630 ; - assign source_id__h21393 = 10'd20 + source_id_base__h13630 ; - assign source_id__h21501 = 10'd19 + source_id_base__h13630 ; - assign source_id__h21609 = 10'd18 + source_id_base__h13630 ; - assign source_id__h21717 = 10'd17 + source_id_base__h13630 ; - assign source_id__h21825 = 10'd16 + source_id_base__h13630 ; - assign source_id__h21933 = 10'd15 + source_id_base__h13630 ; - assign source_id__h22041 = 10'd14 + source_id_base__h13630 ; - assign source_id__h22149 = 10'd13 + source_id_base__h13630 ; - assign source_id__h22257 = 10'd12 + source_id_base__h13630 ; - assign source_id__h22365 = 10'd11 + source_id_base__h13630 ; - assign source_id__h22473 = 10'd10 + source_id_base__h13630 ; - assign source_id__h22581 = 10'd9 + source_id_base__h13630 ; - assign source_id__h22689 = 10'd8 + source_id_base__h13630 ; - assign source_id__h22797 = 10'd7 + source_id_base__h13630 ; - assign source_id__h22905 = 10'd6 + source_id_base__h13630 ; - assign source_id__h23013 = 10'd5 + source_id_base__h13630 ; - assign source_id__h23121 = 10'd4 + source_id_base__h13630 ; - assign source_id__h23229 = 10'd3 + source_id_base__h13630 ; - assign source_id__h23337 = 10'd2 + source_id_base__h13630 ; - assign source_id__h23445 = 10'd1 + source_id_base__h13630 ; - assign source_id__h29475 = { addr_offset__h26929[4:0], 5'd1 } ; - assign source_id__h30685 = { addr_offset__h26929[4:0], 5'd2 } ; - assign source_id__h31895 = { addr_offset__h26929[4:0], 5'd3 } ; - assign source_id__h33105 = { addr_offset__h26929[4:0], 5'd4 } ; - assign source_id__h34315 = { addr_offset__h26929[4:0], 5'd5 } ; - assign source_id__h35525 = { addr_offset__h26929[4:0], 5'd6 } ; - assign source_id__h36735 = { addr_offset__h26929[4:0], 5'd7 } ; - assign source_id__h37945 = { addr_offset__h26929[4:0], 5'd8 } ; - assign source_id__h39155 = { addr_offset__h26929[4:0], 5'd9 } ; - assign source_id__h40365 = { addr_offset__h26929[4:0], 5'd10 } ; - assign source_id__h41575 = { addr_offset__h26929[4:0], 5'd11 } ; - assign source_id__h42785 = { addr_offset__h26929[4:0], 5'd12 } ; - assign source_id__h43995 = { addr_offset__h26929[4:0], 5'd13 } ; - assign source_id__h45205 = { addr_offset__h26929[4:0], 5'd14 } ; - assign source_id__h46415 = { addr_offset__h26929[4:0], 5'd15 } ; - assign source_id__h47625 = { addr_offset__h26929[4:0], 5'd16 } ; - assign source_id__h48835 = { addr_offset__h26929[4:0], 5'd17 } ; - assign source_id__h50045 = { addr_offset__h26929[4:0], 5'd18 } ; - assign source_id__h51255 = { addr_offset__h26929[4:0], 5'd19 } ; - assign source_id__h52465 = { addr_offset__h26929[4:0], 5'd20 } ; - assign source_id__h53675 = { addr_offset__h26929[4:0], 5'd21 } ; - assign source_id__h54885 = { addr_offset__h26929[4:0], 5'd22 } ; - assign source_id__h56095 = { addr_offset__h26929[4:0], 5'd23 } ; - assign source_id__h57305 = { addr_offset__h26929[4:0], 5'd24 } ; - assign source_id__h58515 = { addr_offset__h26929[4:0], 5'd25 } ; - assign source_id__h59725 = { addr_offset__h26929[4:0], 5'd26 } ; - assign source_id__h60935 = { addr_offset__h26929[4:0], 5'd27 } ; - assign source_id__h62145 = { addr_offset__h26929[4:0], 5'd28 } ; - assign source_id__h63355 = { addr_offset__h26929[4:0], 5'd29 } ; - assign source_id__h64565 = { addr_offset__h26929[4:0], 5'd30 } ; - assign source_id__h65775 = { addr_offset__h26929[4:0], 5'd31 } ; - assign source_id__h67436 = { 5'd0, x__h67487 } ; - assign source_id_base__h13630 = { addr_offset__h13216[4:0], 5'h0 } ; - assign source_id_base__h28148 = { addr_offset__h26929[4:0], 5'h0 } ; - assign v__h13422 = { 61'd0, x__h13493 } ; - assign v__h13671 = { 32'd0, v_ip__h13674 } ; - assign v__h18144 = { 32'd0, v_ie__h18147 } ; - assign v__h23761 = { 61'd0, x__h23832 } ; - assign v__h25455 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ? - v__h25474 : - 64'd0 ; - assign v__h25474 = { 59'd0, max_id__h23959 } ; - assign v__h26934 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 ? - 2'b11 : - v__h27094 ; - assign v__h27094 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 ? - v__h27107 : - v__h27942 ; - assign v__h27107 = - (addr_offset__h26929[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d849) ? - 2'b0 : - 2'b10 ; - assign v__h27942 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d847 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900) ? - v__h27961 : - v__h28125 ; - assign v__h27961 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 ? - 2'b0 : - 2'b10 ; - assign v__h28125 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d900 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - v__h28144 : - v__h67107 ; - assign v__h28144 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d903 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d915) ? - 2'b0 : - 2'b10 ; - assign v__h67144 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - 2'b0 : - 2'b10 ; - assign v__h67432 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2880 ? - v__h67476 : - 2'b10 ; - assign v__h67476 = - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 ? - 2'b0 : - 2'b10 ; - assign v_ie__h18147 = - { source_id__h20137 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h20313 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h20421 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h20529 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h20637 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h20745 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h20853 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h20961 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h21069 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h21177 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h21285 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h21393 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h21501 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h21609 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h21717 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h21825 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h21933 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h22041 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h22149 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h22257 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h22365 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h22473 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h22581 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h22689 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h22797 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h22905 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h23013 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h23121 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h23229 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h23337 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h23445 <= 10'd16 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h13674 = - { source_id__h15665 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - source_id__h15772 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - source_id__h15845 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - source_id__h15918 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - source_id__h15991 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - source_id__h16064 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - source_id__h16137 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - source_id__h16210 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - source_id__h16283 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - source_id__h16356 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - source_id__h16429 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - source_id__h16502 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - source_id__h16575 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - source_id__h16648 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - source_id__h16721 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - source_id__h16794 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - source_id__h16867 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - source_id__h16940 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - source_id__h17013 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - source_id__h17086 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - source_id__h17159 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - source_id__h17232 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - source_id__h17305 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - source_id__h17378 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - source_id__h17451 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - source_id__h17524 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - source_id__h17597 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - source_id__h17670 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - source_id__h17743 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - source_id__h17816 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - source_id__h17889 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26930 = - (addr_offset__h26929[2:0] == 3'd4) ? - m_slave_xactor_f_wr_data$D_OUT[72:41] : - m_slave_xactor_f_wr_data$D_OUT[40:9] ; - assign x__h23673 = - { addr_offset__h13216[31:16], 4'd0, addr_offset__h13216[11:0] } ; - assign x__h26361 = - (addr_offset__h13216[2:0] == 3'd4) ? - rdata___1__h26404 : - rdata__h26202 ; - assign x__h67110 = - { addr_offset__h26929[31:16], 4'd0, addr_offset__h26929[11:0] } ; - assign y_avValue_fst__h26094 = (x__h24011 == 5'd0) ? v__h25455 : 64'd0 ; - assign y_avValue_fst__h26115 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_fst__h26094 : - 64'd0 ; - assign y_avValue_fst__h26127 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - v__h23761 : - 64'd0 ; - assign y_avValue_fst__h26143 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - v__h18144 : - 64'd0 ; - assign y_avValue_fst__h26159 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - v__h13671 : - 64'd0 ; - assign y_avValue_fst__h26164 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_fst__h26143 : - y_avValue_fst__h26148 ; - assign y_avValue_fst__h26175 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - v__h13422 : - 64'd0 ; - assign y_avValue_fst__h26180 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_fst__h26159 : - y_avValue_fst__h26164 ; - assign y_avValue_fst__h26194 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_fst__h26175 : - y_avValue_fst__h26180 ; - assign y_avValue_snd__h26095 = (x__h24011 == 5'd0) ? 2'b0 : 2'b10 ; - assign y_avValue_snd__h26116 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_snd__h26095 : - 2'b10 ; - assign y_avValue_snd__h26128 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26144 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26160 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26165 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_snd__h26144 : - y_avValue_snd__h26149 ; - assign y_avValue_snd__h26176 = - (addr_offset__h13216[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26181 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_snd__h26160 : - y_avValue_snd__h26165 ; - assign y_avValue_snd__h26195 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_snd__h26176 : - y_avValue_snd__h26181 ; - always@(addr_offset__h13216 or - m_vrg_source_prio_0 or - m_vrg_source_prio_1 or - m_vrg_source_prio_2 or - m_vrg_source_prio_3 or - m_vrg_source_prio_4 or - m_vrg_source_prio_5 or - m_vrg_source_prio_6 or - m_vrg_source_prio_7 or - m_vrg_source_prio_8 or - m_vrg_source_prio_9 or - m_vrg_source_prio_10 or - m_vrg_source_prio_11 or - m_vrg_source_prio_12 or - m_vrg_source_prio_13 or - m_vrg_source_prio_14 or - m_vrg_source_prio_15 or m_vrg_source_prio_16) - begin - case (addr_offset__h13216[11:2]) - 10'd0: x__h13493 = m_vrg_source_prio_0; - 10'd1: x__h13493 = m_vrg_source_prio_1; - 10'd2: x__h13493 = m_vrg_source_prio_2; - 10'd3: x__h13493 = m_vrg_source_prio_3; - 10'd4: x__h13493 = m_vrg_source_prio_4; - 10'd5: x__h13493 = m_vrg_source_prio_5; - 10'd6: x__h13493 = m_vrg_source_prio_6; - 10'd7: x__h13493 = m_vrg_source_prio_7; - 10'd8: x__h13493 = m_vrg_source_prio_8; - 10'd9: x__h13493 = m_vrg_source_prio_9; - 10'd10: x__h13493 = m_vrg_source_prio_10; - 10'd11: x__h13493 = m_vrg_source_prio_11; - 10'd12: x__h13493 = m_vrg_source_prio_12; - 10'd13: x__h13493 = m_vrg_source_prio_13; - 10'd14: x__h13493 = m_vrg_source_prio_14; - 10'd15: x__h13493 = m_vrg_source_prio_15; - 10'd16: x__h13493 = m_vrg_source_prio_16; - default: x__h13493 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_target_threshold_0 or m_vrg_target_threshold_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h23832 = m_vrg_target_threshold_0; - 5'd1: x__h23832 = m_vrg_target_threshold_1; - default: x__h23832 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: x__h24011 = m_vrg_servicing_source_0; - 5'd1: x__h24011 = m_vrg_servicing_source_1; - default: x__h24011 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h26929 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h26929[16:12]) - 5'd0: x__h67487 = m_vrg_servicing_source_0; - 5'd1: x__h67487 = m_vrg_servicing_source_1; - default: x__h67487 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20313 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20313) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20137 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20137) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15665 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15665) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20421 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20421) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20529 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20529) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15772 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15772) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20637 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20637) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20745 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20745) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15845 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15845) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15918 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15918) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20853 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20853) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20961 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h20961) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15991 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15991) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16064 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16064) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17159 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17159) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21069 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21069) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21177 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21177) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16137 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16137) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16210 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16210) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21285 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21285) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21393 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21393) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16283 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16283) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16356 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16356) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21501 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21501) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21609 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21609) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16429 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16429) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16502 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16502) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21717 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21717) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21825 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21825) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16575 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16575) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16648 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16648) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21933 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21933) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22041 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22041) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16721 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16721) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16794 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16794) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22149 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22149) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22257 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22257) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16867 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16867) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16940 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16940) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22365 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22365) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22473 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22473) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17013 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17013) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17086 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17086) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22581 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22581) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22689 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22689) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17232 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17232) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22797 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22797) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h22905 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h22905) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17305 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17305) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17378 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17378) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23013 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23013) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23121 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23121) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17451 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17451) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17524 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17524) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23229 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23229) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23337 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23337) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17597 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17597) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17670 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17670) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23445 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h23445) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id_base__h13630 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id_base__h13630) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520) - begin - case (addr_offset__h13216[11:7]) - 5'd0: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519; - 5'd1: - CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - default: CASE_addr_offset3216_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17743 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17743) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17889 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17889) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17816 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17816) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_snd__h26128 or y_avValue_snd__h26116) - begin - case (x__h23673) - 32'h00200000: y_avValue_snd__h26149 = y_avValue_snd__h26128; - 32'h00200004: y_avValue_snd__h26149 = y_avValue_snd__h26116; - default: y_avValue_snd__h26149 = 2'b10; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_0_1; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - m_vvrg_ie_1_1; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_0_2; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - m_vvrg_ie_1_2; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_0_3; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - m_vvrg_ie_1_3; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_0_4; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - m_vvrg_ie_1_4; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_0_5; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - m_vvrg_ie_1_5; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_0_6; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - m_vvrg_ie_1_6; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_0_7; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - m_vvrg_ie_1_7; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_0_8; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - m_vvrg_ie_1_8; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_0_9; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - m_vvrg_ie_1_9; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_0_10; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - m_vvrg_ie_1_10; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_0_11; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - m_vvrg_ie_1_11; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_0_12; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - m_vvrg_ie_1_12; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_0_13; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - m_vvrg_ie_1_13; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_0_14; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - m_vvrg_ie_1_14; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_0_15; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - m_vvrg_ie_1_15; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13216 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) - begin - case (addr_offset__h13216[16:12]) - 5'd0: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_0_16; - 5'd1: - CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - m_vvrg_ie_1_16; - default: CASE_addr_offset3216_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h23673 or y_avValue_fst__h26127 or y_avValue_fst__h26115) - begin - case (x__h23673) - 32'h00200000: y_avValue_fst__h26148 = y_avValue_fst__h26127; - 32'h00200004: y_avValue_fst__h26148 = y_avValue_fst__h26115; - default: y_avValue_fst__h26148 = 64'd0; - endcase - end - always@(source_id__h67436 or - m_vrg_source_busy_0 or - m_vrg_source_busy_1 or - m_vrg_source_busy_2 or - m_vrg_source_busy_3 or - m_vrg_source_busy_4 or - m_vrg_source_busy_5 or - m_vrg_source_busy_6 or - m_vrg_source_busy_7 or - m_vrg_source_busy_8 or - m_vrg_source_busy_9 or - m_vrg_source_busy_10 or - m_vrg_source_busy_11 or - m_vrg_source_busy_12 or - m_vrg_source_busy_13 or - m_vrg_source_busy_14 or - m_vrg_source_busy_15 or m_vrg_source_busy_16) - begin - case (source_id__h67436) - 10'd0: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_0; - 10'd1: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_1; - 10'd2: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_2; - 10'd3: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_3; - 10'd4: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_4; - 10'd5: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_5; - 10'd6: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_6; - 10'd7: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_7; - 10'd8: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_8; - 10'd9: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_9; - 10'd10: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_10; - 10'd11: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_11; - 10'd12: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_12; - 10'd13: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_13; - 10'd14: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_14; - 10'd15: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_15; - 10'd16: - SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_901_m_vrg_source_b_ETC___d2919 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(x__h67110 or v__h67144 or v__h67432) - begin - case (x__h67110) - 32'h00200000: v__h67107 = v__h67144; - 32'h00200004: v__h67107 = v__h67432; - default: v__h67107 = 2'b10; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY 5'd0; - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY 3'd7; - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (m_cfg_verbosity$EN) - m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN; - if (m_vrg_servicing_source_0$EN) - m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_0$D_IN; - if (m_vrg_servicing_source_1$EN) - m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_servicing_source_1$D_IN; - if (m_vrg_source_busy_0$EN) - m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_0$D_IN; - if (m_vrg_source_busy_1$EN) - m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_1$D_IN; - if (m_vrg_source_busy_10$EN) - m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_10$D_IN; - if (m_vrg_source_busy_11$EN) - m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_11$D_IN; - if (m_vrg_source_busy_12$EN) - m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_12$D_IN; - if (m_vrg_source_busy_13$EN) - m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_13$D_IN; - if (m_vrg_source_busy_14$EN) - m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_14$D_IN; - if (m_vrg_source_busy_15$EN) - m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_15$D_IN; - if (m_vrg_source_busy_16$EN) - m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_16$D_IN; - if (m_vrg_source_busy_2$EN) - m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_2$D_IN; - if (m_vrg_source_busy_3$EN) - m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_3$D_IN; - if (m_vrg_source_busy_4$EN) - m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_4$D_IN; - if (m_vrg_source_busy_5$EN) - m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_5$D_IN; - if (m_vrg_source_busy_6$EN) - m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_6$D_IN; - if (m_vrg_source_busy_7$EN) - m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_7$D_IN; - if (m_vrg_source_busy_8$EN) - m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_8$D_IN; - if (m_vrg_source_busy_9$EN) - m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_busy_9$D_IN; - if (m_vrg_source_ip_0$EN) - m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_0$D_IN; - if (m_vrg_source_ip_1$EN) - m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_1$D_IN; - if (m_vrg_source_ip_10$EN) - m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_10$D_IN; - if (m_vrg_source_ip_11$EN) - m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_11$D_IN; - if (m_vrg_source_ip_12$EN) - m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_12$D_IN; - if (m_vrg_source_ip_13$EN) - m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_13$D_IN; - if (m_vrg_source_ip_14$EN) - m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_14$D_IN; - if (m_vrg_source_ip_15$EN) - m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_15$D_IN; - if (m_vrg_source_ip_16$EN) - m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_16$D_IN; - if (m_vrg_source_ip_2$EN) - m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_2$D_IN; - if (m_vrg_source_ip_3$EN) - m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_3$D_IN; - if (m_vrg_source_ip_4$EN) - m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_4$D_IN; - if (m_vrg_source_ip_5$EN) - m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_5$D_IN; - if (m_vrg_source_ip_6$EN) - m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_6$D_IN; - if (m_vrg_source_ip_7$EN) - m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_7$D_IN; - if (m_vrg_source_ip_8$EN) - m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_8$D_IN; - if (m_vrg_source_ip_9$EN) - m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_9$D_IN; - if (m_vrg_source_prio_0$EN) - m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_0$D_IN; - if (m_vrg_source_prio_1$EN) - m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_1$D_IN; - if (m_vrg_source_prio_10$EN) - m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_10$D_IN; - if (m_vrg_source_prio_11$EN) - m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_11$D_IN; - if (m_vrg_source_prio_12$EN) - m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_12$D_IN; - if (m_vrg_source_prio_13$EN) - m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_13$D_IN; - if (m_vrg_source_prio_14$EN) - m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_14$D_IN; - if (m_vrg_source_prio_15$EN) - m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_15$D_IN; - if (m_vrg_source_prio_16$EN) - m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_16$D_IN; - if (m_vrg_source_prio_2$EN) - m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_2$D_IN; - if (m_vrg_source_prio_3$EN) - m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_3$D_IN; - if (m_vrg_source_prio_4$EN) - m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_4$D_IN; - if (m_vrg_source_prio_5$EN) - m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_5$D_IN; - if (m_vrg_source_prio_6$EN) - m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_6$D_IN; - if (m_vrg_source_prio_7$EN) - m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_7$D_IN; - if (m_vrg_source_prio_8$EN) - m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_8$D_IN; - if (m_vrg_source_prio_9$EN) - m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY - m_vrg_source_prio_9$D_IN; - if (m_vrg_target_threshold_0$EN) - m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_0$D_IN; - if (m_vrg_target_threshold_1$EN) - m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY - m_vrg_target_threshold_1$D_IN; - if (m_vvrg_ie_0_0$EN) - m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_0$D_IN; - if (m_vvrg_ie_0_1$EN) - m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_1$D_IN; - if (m_vvrg_ie_0_10$EN) - m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_10$D_IN; - if (m_vvrg_ie_0_11$EN) - m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_11$D_IN; - if (m_vvrg_ie_0_12$EN) - m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_12$D_IN; - if (m_vvrg_ie_0_13$EN) - m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_13$D_IN; - if (m_vvrg_ie_0_14$EN) - m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_14$D_IN; - if (m_vvrg_ie_0_15$EN) - m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_15$D_IN; - if (m_vvrg_ie_0_16$EN) - m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_16$D_IN; - if (m_vvrg_ie_0_2$EN) - m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_2$D_IN; - if (m_vvrg_ie_0_3$EN) - m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_3$D_IN; - if (m_vvrg_ie_0_4$EN) - m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_4$D_IN; - if (m_vvrg_ie_0_5$EN) - m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_5$D_IN; - if (m_vvrg_ie_0_6$EN) - m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_6$D_IN; - if (m_vvrg_ie_0_7$EN) - m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_7$D_IN; - if (m_vvrg_ie_0_8$EN) - m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_8$D_IN; - if (m_vvrg_ie_0_9$EN) - m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_9$D_IN; - if (m_vvrg_ie_1_0$EN) - m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_0$D_IN; - if (m_vvrg_ie_1_1$EN) - m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_1$D_IN; - if (m_vvrg_ie_1_10$EN) - m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_10$D_IN; - if (m_vvrg_ie_1_11$EN) - m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_11$D_IN; - if (m_vvrg_ie_1_12$EN) - m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_12$D_IN; - if (m_vvrg_ie_1_13$EN) - m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_13$D_IN; - if (m_vvrg_ie_1_14$EN) - m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_14$D_IN; - if (m_vvrg_ie_1_15$EN) - m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_15$D_IN; - if (m_vvrg_ie_1_16$EN) - m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_16$D_IN; - if (m_vvrg_ie_1_2$EN) - m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_2$D_IN; - if (m_vvrg_ie_1_3$EN) - m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_3$D_IN; - if (m_vvrg_ie_1_4$EN) - m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_4$D_IN; - if (m_vvrg_ie_1_5$EN) - m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_5$D_IN; - if (m_vvrg_ie_1_6$EN) - m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_6$D_IN; - if (m_vvrg_ie_1_7$EN) - m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_7$D_IN; - if (m_vvrg_ie_1_8$EN) - m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_8$D_IN; - if (m_vvrg_ie_1_9$EN) - m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_9$D_IN; - end - if (m_rg_addr_base$EN) - m_rg_addr_base <= `BSV_ASSIGNMENT_DELAY m_rg_addr_base$D_IN; - if (m_rg_addr_lim$EN) - m_rg_addr_lim <= `BSV_ASSIGNMENT_DELAY m_rg_addr_lim$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - m_cfg_verbosity = 4'hA; - m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - m_vrg_servicing_source_0 = 5'h0A; - m_vrg_servicing_source_1 = 5'h0A; - m_vrg_source_busy_0 = 1'h0; - m_vrg_source_busy_1 = 1'h0; - m_vrg_source_busy_10 = 1'h0; - m_vrg_source_busy_11 = 1'h0; - m_vrg_source_busy_12 = 1'h0; - m_vrg_source_busy_13 = 1'h0; - m_vrg_source_busy_14 = 1'h0; - m_vrg_source_busy_15 = 1'h0; - m_vrg_source_busy_16 = 1'h0; - m_vrg_source_busy_2 = 1'h0; - m_vrg_source_busy_3 = 1'h0; - m_vrg_source_busy_4 = 1'h0; - m_vrg_source_busy_5 = 1'h0; - m_vrg_source_busy_6 = 1'h0; - m_vrg_source_busy_7 = 1'h0; - m_vrg_source_busy_8 = 1'h0; - m_vrg_source_busy_9 = 1'h0; - m_vrg_source_ip_0 = 1'h0; - m_vrg_source_ip_1 = 1'h0; - m_vrg_source_ip_10 = 1'h0; - m_vrg_source_ip_11 = 1'h0; - m_vrg_source_ip_12 = 1'h0; - m_vrg_source_ip_13 = 1'h0; - m_vrg_source_ip_14 = 1'h0; - m_vrg_source_ip_15 = 1'h0; - m_vrg_source_ip_16 = 1'h0; - m_vrg_source_ip_2 = 1'h0; - m_vrg_source_ip_3 = 1'h0; - m_vrg_source_ip_4 = 1'h0; - m_vrg_source_ip_5 = 1'h0; - m_vrg_source_ip_6 = 1'h0; - m_vrg_source_ip_7 = 1'h0; - m_vrg_source_ip_8 = 1'h0; - m_vrg_source_ip_9 = 1'h0; - m_vrg_source_prio_0 = 3'h2; - m_vrg_source_prio_1 = 3'h2; - m_vrg_source_prio_10 = 3'h2; - m_vrg_source_prio_11 = 3'h2; - m_vrg_source_prio_12 = 3'h2; - m_vrg_source_prio_13 = 3'h2; - m_vrg_source_prio_14 = 3'h2; - m_vrg_source_prio_15 = 3'h2; - m_vrg_source_prio_16 = 3'h2; - m_vrg_source_prio_2 = 3'h2; - m_vrg_source_prio_3 = 3'h2; - m_vrg_source_prio_4 = 3'h2; - m_vrg_source_prio_5 = 3'h2; - m_vrg_source_prio_6 = 3'h2; - m_vrg_source_prio_7 = 3'h2; - m_vrg_source_prio_8 = 3'h2; - m_vrg_source_prio_9 = 3'h2; - m_vrg_target_threshold_0 = 3'h2; - m_vrg_target_threshold_1 = 3'h2; - m_vvrg_ie_0_0 = 1'h0; - m_vvrg_ie_0_1 = 1'h0; - m_vvrg_ie_0_10 = 1'h0; - m_vvrg_ie_0_11 = 1'h0; - m_vvrg_ie_0_12 = 1'h0; - m_vvrg_ie_0_13 = 1'h0; - m_vvrg_ie_0_14 = 1'h0; - m_vvrg_ie_0_15 = 1'h0; - m_vvrg_ie_0_16 = 1'h0; - m_vvrg_ie_0_2 = 1'h0; - m_vvrg_ie_0_3 = 1'h0; - m_vvrg_ie_0_4 = 1'h0; - m_vvrg_ie_0_5 = 1'h0; - m_vvrg_ie_0_6 = 1'h0; - m_vvrg_ie_0_7 = 1'h0; - m_vvrg_ie_0_8 = 1'h0; - m_vvrg_ie_0_9 = 1'h0; - m_vvrg_ie_1_0 = 1'h0; - m_vvrg_ie_1_1 = 1'h0; - m_vvrg_ie_1_10 = 1'h0; - m_vvrg_ie_1_11 = 1'h0; - m_vvrg_ie_1_12 = 1'h0; - m_vvrg_ie_1_13 = 1'h0; - m_vvrg_ie_1_14 = 1'h0; - m_vvrg_ie_1_15 = 1'h0; - m_vvrg_ie_1_16 = 1'h0; - m_vvrg_ie_1_2 = 1'h0; - m_vvrg_ie_1_3 = 1'h0; - m_vvrg_ie_1_4 = 1'h0; - m_vvrg_ie_1_5 = 1'h0; - m_vvrg_ie_1_6 = 1'h0; - m_vvrg_ie_1_7 = 1'h0; - m_vvrg_ie_1_8 = 1'h0; - m_vvrg_ie_1_9 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $display("----------------"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src IPs :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src Prios:"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("Src busy :"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_16); - if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71312, - m_vrg_target_threshold_0, - b__h71313, - m_vrg_servicing_source_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_0); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_1); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_2); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_3); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_4); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_5); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_6); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_7); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_8); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_9); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_10); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_11); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_12); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_13); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_14); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_15); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_16); - if (RST_N != `BSV_RESET_VALUE) - if (EN_show_PLIC_state) - $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73317, - m_vrg_target_threshold_1, - b__h73318, - m_vrg_servicing_source_1); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - begin - v__h75676 = $stime; - #0; - end - v__h75670 = v__h75676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_902_238_AND_NOT_m_cfg__ETC___d3242) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75670, - $signed(32'd1), - v_sources_0_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - begin - v__h75874 = $stime; - #0; - end - v__h75868 = v__h75874 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_903_245_AND_NOT_m_cfg__ETC___d3249) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75868, - $signed(32'd2), - v_sources_1_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - begin - v__h76072 = $stime; - #0; - end - v__h76066 = v__h76072 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_904_253_AND_NOT_m_cfg__ETC___d3257) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76066, - $signed(32'd3), - v_sources_2_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - begin - v__h76270 = $stime; - #0; - end - v__h76264 = v__h76270 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_905_261_AND_NOT_m_cfg__ETC___d3265) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76264, - $signed(32'd4), - v_sources_3_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - begin - v__h76468 = $stime; - #0; - end - v__h76462 = v__h76468 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_906_269_AND_NOT_m_cfg__ETC___d3273) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76462, - $signed(32'd5), - v_sources_4_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - begin - v__h76666 = $stime; - #0; - end - v__h76660 = v__h76666 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_907_277_AND_NOT_m_cfg__ETC___d3281) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76660, - $signed(32'd6), - v_sources_5_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - begin - v__h76864 = $stime; - #0; - end - v__h76858 = v__h76864 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_908_285_AND_NOT_m_cfg__ETC___d3289) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76858, - $signed(32'd7), - v_sources_6_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - begin - v__h77062 = $stime; - #0; - end - v__h77056 = v__h77062 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_909_293_AND_NOT_m_cfg__ETC___d3297) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77056, - $signed(32'd8), - v_sources_7_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - begin - v__h77260 = $stime; - #0; - end - v__h77254 = v__h77260 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_910_301_AND_NOT_m_cfg__ETC___d3305) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77254, - $signed(32'd9), - v_sources_8_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - begin - v__h77458 = $stime; - #0; - end - v__h77452 = v__h77458 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_911_309_AND_NOT_m_cfg_ETC___d3313) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77452, - $signed(32'd10), - v_sources_9_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - begin - v__h77656 = $stime; - #0; - end - v__h77650 = v__h77656 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_912_317_AND_NOT_m_cfg_ETC___d3321) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77650, - $signed(32'd11), - v_sources_10_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - begin - v__h77854 = $stime; - #0; - end - v__h77848 = v__h77854 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_913_325_AND_NOT_m_cfg_ETC___d3329) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77848, - $signed(32'd12), - v_sources_11_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - begin - v__h78052 = $stime; - #0; - end - v__h78046 = v__h78052 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_914_333_AND_NOT_m_cfg_ETC___d3337) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78046, - $signed(32'd13), - v_sources_12_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - begin - v__h78250 = $stime; - #0; - end - v__h78244 = v__h78250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_915_341_AND_NOT_m_cfg_ETC___d3345) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78244, - $signed(32'd14), - v_sources_13_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - begin - v__h78448 = $stime; - #0; - end - v__h78442 = v__h78448 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_916_349_AND_NOT_m_cfg_ETC___d3353) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78442, - $signed(32'd15), - v_sources_14_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - begin - v__h78646 = $stime; - #0; - end - v__h78640 = v__h78646 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_917_357_AND_NOT_m_cfg_ETC___d3361) - $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78640, - $signed(32'd16), - v_sources_15_m_interrupt_req_set_not_clear); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - begin - v__h6144 = $stime; - #0; - end - v__h6138 = v__h6144 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h6138); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h13080 = $stime; - #0; - end - v__h13074 = v__h13080 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req:", v__h13074); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - begin - v__h13265 = $stime; - #0; - end - v__h13259 = v__h13265 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h13259); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - begin - v__h13463 = $stime; - #0; - end - v__h13457 = v__h13463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) - $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h13457, - addr_offset__h13216[11:2], - v__h13422); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - begin - v__h13713 = $stime; - #0; - end - v__h13707 = v__h13713 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h13707, - source_id_base__h13630, - v__h13671); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - begin - v__h18186 = $stime; - #0; - end - v__h18180 = v__h18186 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) - $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h18180, - source_id_base__h13630, - v__h18144); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - begin - v__h23802 = $stime; - #0; - end - v__h23796 = v__h23802 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) - $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h23796, - addr_offset__h13216[16:12], - v__h23761); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - begin - v__h25975 = $stime; - #0; - end - v__h25969 = v__h25975 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) - $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h25969, - addr_offset__h13216[16:12], - v__h25474); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - begin - v__h24056 = $stime; - #0; - end - v__h24050 = v__h24056 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h24050, - addr_offset__h13216[16:12]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Still servicing interrupt from source %0d", x__h24011); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Trying to claim service for source %0d", - max_id__h23959); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Ignoring."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - begin - v__h26250 = $stime; - #0; - end - v__h26244 = v__h26250 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h26244); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26463 = $stime; - #0; - end - v__h26457 = v__h26463 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req", v__h26457); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", x__h26361); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", rresp__h26203); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h26740 = $stime; - #0; - end - v__h26734 = v__h26740 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26734); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - begin - v__h26968 = $stime; - #0; - end - v__h26962 = v__h26968 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26962); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - begin - v__h27865 = $stime; - #0; - end - v__h27859 = v__h27865 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d895) - $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27859, - addr_offset__h26929[11:2], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - begin - v__h28048 = $stime; - #0; - end - v__h28042 = v__h28048 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d906) - $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28042, - source_id_base__h28148); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - begin - v__h67030 = $stime; - #0; - end - v__h67024 = v__h67030 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2870) - $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67024, - addr_offset__h26929[11:7], - source_id_base__h28148, - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - begin - v__h67318 = $stime; - #0; - end - v__h67312 = v__h67318 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2894) - $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67312, - addr_offset__h26929[16:12], - wdata32__h26930); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - begin - v__h67847 = $stime; - #0; - end - v__h67841 = v__h67847 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2966) - $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67841, - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - begin - v__h67933 = $stime; - #0; - end - v__h67927 = v__h67933 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67927); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Completion message from target %0d to source %0d", - addr_offset__h26929[16:12], - source_id__h67436); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2976) - $display(" Ignoring"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - begin - v__h68132 = $stime; - #0; - end - v__h68126 = v__h68132 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68126); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991) && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d838 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2991)) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - begin - v__h68353 = $stime; - #0; - end - v__h68347 = v__h68353 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68347); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26934); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h74690 = $stime; - #0; - end - v__h74684 = v__h74690 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74684, - set_addr_map_addr_base); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h74800 = $stime; - #0; - end - v__h74794 = v__h74800 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74794, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - begin - v__h74913 = $stime; - #0; - end - v__h74907 = v__h74913 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_set_addr_map && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74907, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkPLIC_16_2_7 - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v deleted file mode 100644 index f852a5f3..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkRISCV_MBox.v +++ /dev/null @@ -1,734 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// RDY_req_reset O 1 const -// RDY_rsp_reset O 1 const -// valid O 1 -// word O 64 -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// req_is_OP_not_OP_32 I 1 -// req_f3 I 3 -// req_v1 I 64 -// req_v2 I 64 -// EN_set_verbosity I 1 -// EN_req_reset I 1 unused -// EN_rsp_reset I 1 unused -// EN_req I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkRISCV_MBox(CLK, - RST_N, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - EN_req_reset, - RDY_req_reset, - - EN_rsp_reset, - RDY_rsp_reset, - - req_is_OP_not_OP_32, - req_f3, - req_v1, - req_v2, - EN_req, - - valid, - - word); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method req_reset - input EN_req_reset; - output RDY_req_reset; - - // action method rsp_reset - input EN_rsp_reset; - output RDY_rsp_reset; - - // action method req - input req_is_OP_not_OP_32; - input [2 : 0] req_f3; - input [63 : 0] req_v1; - input [63 : 0] req_v2; - input EN_req; - - // value method valid - output valid; - - // value method word - output [63 : 0] word; - - // signals for module outputs - wire [63 : 0] word; - wire RDY_req_reset, RDY_rsp_reset, RDY_set_verbosity, valid; - - // inlined wires - wire dw_valid$whas; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register intDiv_rg_denom2 - reg [63 : 0] intDiv_rg_denom2; - reg [63 : 0] intDiv_rg_denom2$D_IN; - wire intDiv_rg_denom2$EN; - - // register intDiv_rg_denom_is_signed - reg intDiv_rg_denom_is_signed; - wire intDiv_rg_denom_is_signed$D_IN, intDiv_rg_denom_is_signed$EN; - - // register intDiv_rg_n - reg [63 : 0] intDiv_rg_n; - reg [63 : 0] intDiv_rg_n$D_IN; - wire intDiv_rg_n$EN; - - // register intDiv_rg_numer_is_signed - reg intDiv_rg_numer_is_signed; - wire intDiv_rg_numer_is_signed$D_IN, intDiv_rg_numer_is_signed$EN; - - // register intDiv_rg_quo - reg [63 : 0] intDiv_rg_quo; - reg [63 : 0] intDiv_rg_quo$D_IN; - wire intDiv_rg_quo$EN; - - // register intDiv_rg_quoIsNeg - reg intDiv_rg_quoIsNeg; - wire intDiv_rg_quoIsNeg$D_IN, intDiv_rg_quoIsNeg$EN; - - // register intDiv_rg_remIsNeg - reg intDiv_rg_remIsNeg; - wire intDiv_rg_remIsNeg$D_IN, intDiv_rg_remIsNeg$EN; - - // register intDiv_rg_state - reg [2 : 0] intDiv_rg_state; - reg [2 : 0] intDiv_rg_state$D_IN; - wire intDiv_rg_state$EN; - - // register rg_f3 - reg [2 : 0] rg_f3; - wire [2 : 0] rg_f3$D_IN; - wire rg_f3$EN; - - // register rg_is_OP_not_OP_32 - reg rg_is_OP_not_OP_32; - wire rg_is_OP_not_OP_32$D_IN, rg_is_OP_not_OP_32$EN; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // register rg_v1 - reg [63 : 0] rg_v1; - reg [63 : 0] rg_v1$D_IN; - wire rg_v1$EN; - - // register rg_v2 - reg [63 : 0] rg_v2; - wire [63 : 0] rg_v2$D_IN; - wire rg_v2$EN; - - // rule scheduling signals - wire CAN_FIRE_RL_intDiv_rl_loop1, - CAN_FIRE_RL_intDiv_rl_loop2, - CAN_FIRE_RL_intDiv_rl_start_div_by_zero, - CAN_FIRE_RL_intDiv_rl_start_overflow, - CAN_FIRE_RL_intDiv_rl_start_s, - CAN_FIRE_RL_rg_div_rem, - CAN_FIRE_RL_rl_mul, - CAN_FIRE_RL_rl_mul2, - CAN_FIRE_req, - CAN_FIRE_req_reset, - CAN_FIRE_rsp_reset, - CAN_FIRE_set_verbosity, - WILL_FIRE_RL_intDiv_rl_loop1, - WILL_FIRE_RL_intDiv_rl_loop2, - WILL_FIRE_RL_intDiv_rl_start_div_by_zero, - WILL_FIRE_RL_intDiv_rl_start_overflow, - WILL_FIRE_RL_intDiv_rl_start_s, - WILL_FIRE_RL_rg_div_rem, - WILL_FIRE_RL_rl_mul, - WILL_FIRE_RL_rl_mul2, - WILL_FIRE_req, - WILL_FIRE_req_reset, - WILL_FIRE_rsp_reset, - WILL_FIRE_set_verbosity; - - // inputs to muxes for submodule ports - wire [63 : 0] MUX_dw_result$wset_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_1, - MUX_intDiv_rg_denom2$write_1__VAL_2, - MUX_intDiv_rg_denom2$write_1__VAL_3, - MUX_intDiv_rg_n$write_1__VAL_1, - MUX_intDiv_rg_n$write_1__VAL_2, - MUX_intDiv_rg_quo$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_1, - MUX_rg_v1$write_1__VAL_2, - MUX_rg_v1$write_1__VAL_3, - MUX_rg_v1$write_1__VAL_4, - MUX_rg_v2$write_1__VAL_1; - wire [1 : 0] MUX_rg_state$write_1__VAL_1; - wire MUX_intDiv_rg_denom2$write_1__SEL_1, - MUX_intDiv_rg_denom2$write_1__SEL_2, - MUX_intDiv_rg_quo$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_1, - MUX_intDiv_rg_state$write_1__SEL_2, - MUX_intDiv_rg_state$write_1__SEL_3, - MUX_rg_v1$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h4706; - reg [31 : 0] v__h4700; - // synopsys translate_on - - // remaining internal signals - wire [255 : 0] SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118, - SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110, - _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115; - wire [127 : 0] SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125, - SEXT_rg_v1____d108, - rg_v1_MUL_rg_v2___d105, - v1__h4494; - wire [63 : 0] IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138, - _theResult___fst__h5162, - _theResult___fst__h5192, - _theResult___fst__h5218, - _theResult___fst__h787, - _theResult___snd__h5163, - _theResult___snd__h5193, - _theResult___snd__h5219, - _theResult___snd_fst__h782, - denom___1__h729, - numer___1__h728, - result___1__h4957, - v__h4418, - v__h4476, - v__h4527, - v__h4583, - v__h4600, - x__h3955, - x__h4041, - x__h4111, - x__h4126, - y__h3834; - wire [31 : 0] IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3, - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6, - req_v1_BITS_31_TO_0__q1, - req_v2_BITS_31_TO_0__q2, - rg_v1_BITS_31_TO_0__q4, - rg_v2_BITS_31_TO_0__q5; - wire IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39, - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47, - rg_v1_ULT_intDiv_rg_denom2_4___d59, - rg_v1_ULT_rg_v2___d55; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method req_reset - assign RDY_req_reset = 1'd1 ; - assign CAN_FIRE_req_reset = 1'd1 ; - assign WILL_FIRE_req_reset = EN_req_reset ; - - // action method rsp_reset - assign RDY_rsp_reset = 1'd1 ; - assign CAN_FIRE_rsp_reset = 1'd1 ; - assign WILL_FIRE_rsp_reset = EN_rsp_reset ; - - // action method req - assign CAN_FIRE_req = 1'd1 ; - assign WILL_FIRE_req = EN_req ; - - // value method valid - assign valid = dw_valid$whas ; - - // value method word - assign word = WILL_FIRE_RL_rl_mul2 ? rg_v1 : MUX_dw_result$wset_1__VAL_2 ; - - // rule RL_rl_mul2 - assign CAN_FIRE_RL_rl_mul2 = rg_state == 2'd1 ; - assign WILL_FIRE_RL_rl_mul2 = CAN_FIRE_RL_rl_mul2 ; - - // rule RL_rg_div_rem - assign CAN_FIRE_RL_rg_div_rem = - rg_state == 2'd2 && intDiv_rg_state == 3'd4 ; - assign WILL_FIRE_RL_rg_div_rem = CAN_FIRE_RL_rg_div_rem ; - - // rule RL_intDiv_rl_start_div_by_zero - assign CAN_FIRE_RL_intDiv_rl_start_div_by_zero = - intDiv_rg_state == 3'd1 && rg_v2 == 64'd0 ; - assign WILL_FIRE_RL_intDiv_rl_start_div_by_zero = - CAN_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // rule RL_intDiv_rl_start_overflow - assign CAN_FIRE_RL_intDiv_rl_start_overflow = - intDiv_rg_state == 3'd1 && intDiv_rg_numer_is_signed && - rg_v1 == 64'h8000000000000000 && - intDiv_rg_denom_is_signed && - rg_v2 == 64'hFFFFFFFFFFFFFFFF ; - assign WILL_FIRE_RL_intDiv_rl_start_overflow = - CAN_FIRE_RL_intDiv_rl_start_overflow && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_start_s - assign CAN_FIRE_RL_intDiv_rl_start_s = - intDiv_rg_state == 3'd1 && rg_v2 != 64'd0 && - (!intDiv_rg_numer_is_signed || rg_v1 != 64'h8000000000000000 || - !intDiv_rg_denom_is_signed || - rg_v2 != 64'hFFFFFFFFFFFFFFFF) ; - assign WILL_FIRE_RL_intDiv_rl_start_s = - CAN_FIRE_RL_intDiv_rl_start_s && !WILL_FIRE_RL_rl_mul ; - - // rule RL_intDiv_rl_loop1 - assign CAN_FIRE_RL_intDiv_rl_loop1 = intDiv_rg_state == 3'd2 ; - assign WILL_FIRE_RL_intDiv_rl_loop1 = CAN_FIRE_RL_intDiv_rl_loop1 ; - - // rule RL_rl_mul - assign CAN_FIRE_RL_rl_mul = rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_mul = rg_state == 2'd0 ; - - // rule RL_intDiv_rl_loop2 - assign CAN_FIRE_RL_intDiv_rl_loop2 = intDiv_rg_state == 3'd3 ; - assign WILL_FIRE_RL_intDiv_rl_loop2 = - CAN_FIRE_RL_intDiv_rl_loop2 && !WILL_FIRE_RL_rl_mul ; - - // inputs to muxes for submodule ports - assign MUX_intDiv_rg_denom2$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ; - assign MUX_intDiv_rg_denom2$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 ; - assign MUX_intDiv_rg_quo$write_1__SEL_1 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_quoIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_intDiv_rg_state$write_1__SEL_1 = EN_req && req_f3[2] ; - assign MUX_intDiv_rg_state$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 ; - assign MUX_intDiv_rg_state$write_1__SEL_3 = - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ; - assign MUX_rg_v1$write_1__SEL_2 = - WILL_FIRE_RL_intDiv_rl_loop2 && - (rg_v1_ULT_rg_v2___d55 && intDiv_rg_remIsNeg || - !rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ; - assign MUX_dw_result$wset_1__VAL_2 = - rg_is_OP_not_OP_32 ? - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138 : - result___1__h4957 ; - assign MUX_intDiv_rg_denom2$write_1__VAL_1 = - { intDiv_rg_denom2[62:0], 1'd0 } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_2 = - { 1'd0, intDiv_rg_denom2[63:1] } ; - assign MUX_intDiv_rg_denom2$write_1__VAL_3 = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - denom___1__h729 : - _theResult___snd_fst__h782 ; - assign MUX_intDiv_rg_n$write_1__VAL_1 = { intDiv_rg_n[62:0], 1'd0 } ; - assign MUX_intDiv_rg_n$write_1__VAL_2 = { 1'd0, intDiv_rg_n[63:1] } ; - assign MUX_intDiv_rg_quo$write_1__VAL_1 = - rg_v1_ULT_rg_v2___d55 ? x__h4041 : x__h4126 ; - assign MUX_rg_state$write_1__VAL_1 = req_f3[2] ? 2'd2 : 2'd0 ; - assign MUX_rg_v1$write_1__VAL_1 = - req_is_OP_not_OP_32 ? req_v1 : _theResult___fst__h5162 ; - assign MUX_rg_v1$write_1__VAL_2 = - rg_v1_ULT_rg_v2___d55 ? x__h4111 : x__h3955 ; - assign MUX_rg_v1$write_1__VAL_3 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - rg_v1_MUL_rg_v2___d105[63:0] : - v__h4418 ; - assign MUX_rg_v1$write_1__VAL_4 = - intDiv_rg_numer_is_signed ? numer___1__h728 : rg_v1 ; - assign MUX_rg_v2$write_1__VAL_1 = - req_is_OP_not_OP_32 ? req_v2 : _theResult___snd__h5163 ; - - // inlined wires - assign dw_valid$whas = WILL_FIRE_RL_rg_div_rem || WILL_FIRE_RL_rl_mul2 ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign cfg_verbosity$EN = EN_set_verbosity ; - - // register intDiv_rg_denom2 - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_denom2$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_denom2$write_1__VAL_2 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_intDiv_rg_denom2$write_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: - intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_3; - default: intDiv_rg_denom2$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_denom2$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_denom_is_signed - assign intDiv_rg_denom_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_denom_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_n - always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or - MUX_intDiv_rg_n$write_1__VAL_1 or - MUX_intDiv_rg_denom2$write_1__SEL_2 or - MUX_intDiv_rg_n$write_1__VAL_2 or WILL_FIRE_RL_intDiv_rl_start_s) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_denom2$write_1__SEL_1: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_1; - MUX_intDiv_rg_denom2$write_1__SEL_2: - intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_2; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_n$D_IN = 64'd1; - default: intDiv_rg_n$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_n$EN = - WILL_FIRE_RL_intDiv_rl_loop1 && - intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 && - rg_v1_ULT_intDiv_rg_denom2_4___d59 || - WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_numer_is_signed - assign intDiv_rg_numer_is_signed$D_IN = !req_f3[0] ; - assign intDiv_rg_numer_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ; - - // register intDiv_rg_quo - always@(MUX_intDiv_rg_quo$write_1__SEL_1 or - MUX_intDiv_rg_quo$write_1__VAL_1 or - WILL_FIRE_RL_intDiv_rl_start_overflow or - rg_v1 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - begin - case (1'b1) // synopsys parallel_case - MUX_intDiv_rg_quo$write_1__SEL_1: - intDiv_rg_quo$D_IN = MUX_intDiv_rg_quo$write_1__VAL_1; - WILL_FIRE_RL_intDiv_rl_start_overflow: intDiv_rg_quo$D_IN = rg_v1; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_quo$D_IN = 64'd0; - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_quo$D_IN = 64'hFFFFFFFFFFFFFFFF; - default: intDiv_rg_quo$D_IN = - 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign intDiv_rg_quo$EN = - MUX_intDiv_rg_quo$write_1__SEL_1 || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register intDiv_rg_quoIsNeg - assign intDiv_rg_quoIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[63] != rg_v2[63] : - IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39 ; - assign intDiv_rg_quoIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_remIsNeg - assign intDiv_rg_remIsNeg$D_IN = - (intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ? - rg_v1[63] : - intDiv_rg_numer_is_signed && rg_v1[63] ; - assign intDiv_rg_remIsNeg$EN = WILL_FIRE_RL_intDiv_rl_start_s ; - - // register intDiv_rg_state - always@(MUX_intDiv_rg_state$write_1__SEL_1 or - MUX_intDiv_rg_state$write_1__SEL_2 or - MUX_intDiv_rg_state$write_1__SEL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - WILL_FIRE_RL_intDiv_rl_start_overflow or - WILL_FIRE_RL_intDiv_rl_start_div_by_zero) - case (1'b1) - MUX_intDiv_rg_state$write_1__SEL_1: intDiv_rg_state$D_IN = 3'd1; - MUX_intDiv_rg_state$write_1__SEL_2: intDiv_rg_state$D_IN = 3'd4; - MUX_intDiv_rg_state$write_1__SEL_3: intDiv_rg_state$D_IN = 3'd3; - WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_state$D_IN = 3'd2; - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero: - intDiv_rg_state$D_IN = 3'd4; - default: intDiv_rg_state$D_IN = 3'b010 /* unspecified value */ ; - endcase - assign intDiv_rg_state$EN = - WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 || - EN_req && req_f3[2] || - WILL_FIRE_RL_intDiv_rl_loop1 && - !intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow || - WILL_FIRE_RL_intDiv_rl_start_div_by_zero ; - - // register rg_f3 - assign rg_f3$D_IN = req_f3 ; - assign rg_f3$EN = EN_req ; - - // register rg_is_OP_not_OP_32 - assign rg_is_OP_not_OP_32$D_IN = req_is_OP_not_OP_32 ; - assign rg_is_OP_not_OP_32$EN = EN_req ; - - // register rg_state - assign rg_state$D_IN = EN_req ? MUX_rg_state$write_1__VAL_1 : 2'd1 ; - assign rg_state$EN = EN_req || WILL_FIRE_RL_rl_mul ; - - // register rg_v1 - always@(EN_req or - MUX_rg_v1$write_1__VAL_1 or - MUX_rg_v1$write_1__SEL_2 or - MUX_rg_v1$write_1__VAL_2 or - WILL_FIRE_RL_rl_mul or - MUX_rg_v1$write_1__VAL_3 or - WILL_FIRE_RL_intDiv_rl_start_s or - MUX_rg_v1$write_1__VAL_4 or WILL_FIRE_RL_intDiv_rl_start_overflow) - case (1'b1) - EN_req: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_1; - MUX_rg_v1$write_1__SEL_2: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_2; - WILL_FIRE_RL_rl_mul: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_3; - WILL_FIRE_RL_intDiv_rl_start_s: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_4; - WILL_FIRE_RL_intDiv_rl_start_overflow: rg_v1$D_IN = 64'd0; - default: rg_v1$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - assign rg_v1$EN = - MUX_rg_v1$write_1__SEL_2 || WILL_FIRE_RL_rl_mul || EN_req || - WILL_FIRE_RL_intDiv_rl_start_s || - WILL_FIRE_RL_intDiv_rl_start_overflow ; - - // register rg_v2 - assign rg_v2$D_IN = - EN_req ? - MUX_rg_v2$write_1__VAL_1 : - MUX_intDiv_rg_denom2$write_1__VAL_3 ; - assign rg_v2$EN = EN_req || WILL_FIRE_RL_intDiv_rl_start_s ; - - // remaining internal signals - assign IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39 = - intDiv_rg_numer_is_signed ? - rg_v1[63] : - intDiv_rg_denom_is_signed && rg_v2[63] ; - assign IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138 = - rg_f3[1] ? rg_v1 : intDiv_rg_quo ; - assign IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3 = - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC___d138[31:0] ; - assign SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125 = - { {32{rg_v1_BITS_31_TO_0__q4[31]}}, rg_v1_BITS_31_TO_0__q4 } * - { {32{rg_v2_BITS_31_TO_0__q5[31]}}, rg_v2_BITS_31_TO_0__q5 } ; - assign SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6 = - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC___d125[31:0] ; - assign SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118 = - SEXT_rg_v1____d108 * { 64'd0, rg_v2 } ; - assign SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110 = - SEXT_rg_v1____d108 * { {64{rg_v2[63]}}, rg_v2 } ; - assign SEXT_rg_v1____d108 = { {64{rg_v1[63]}}, rg_v1 } ; - assign _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115 = - v1__h4494 * { 64'd0, rg_v2 } ; - assign _theResult___fst__h5162 = - req_f3[0] ? _theResult___fst__h5218 : _theResult___fst__h5192 ; - assign _theResult___fst__h5192 = - { {32{req_v1_BITS_31_TO_0__q1[31]}}, req_v1_BITS_31_TO_0__q1 } ; - assign _theResult___fst__h5218 = { 32'd0, req_v1[31:0] } ; - assign _theResult___fst__h787 = - intDiv_rg_denom_is_signed ? denom___1__h729 : rg_v2 ; - assign _theResult___snd__h5163 = - req_f3[0] ? _theResult___snd__h5219 : _theResult___snd__h5193 ; - assign _theResult___snd__h5193 = - { {32{req_v2_BITS_31_TO_0__q2[31]}}, req_v2_BITS_31_TO_0__q2 } ; - assign _theResult___snd__h5219 = { 32'd0, req_v2[31:0] } ; - assign _theResult___snd_fst__h782 = - intDiv_rg_numer_is_signed ? rg_v2 : _theResult___fst__h787 ; - assign denom___1__h729 = rg_v2[63] ? -rg_v2 : rg_v2 ; - assign intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 = - intDiv_rg_denom2 <= y__h3834 ; - assign numer___1__h728 = rg_v1[63] ? x__h4111 : rg_v1 ; - assign req_v1_BITS_31_TO_0__q1 = req_v1[31:0] ; - assign req_v2_BITS_31_TO_0__q2 = req_v2[31:0] ; - assign result___1__h4957 = - { {32{IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3[31]}}, - IF_rg_f3_4_BIT_1_37_THEN_rg_v1_ELSE_intDiv_rg__ETC__q3 } ; - assign rg_v1_BITS_31_TO_0__q4 = rg_v1[31:0] ; - assign rg_v1_MUL_rg_v2___d105 = rg_v1 * rg_v2 ; - assign rg_v1_ULT_intDiv_rg_denom2_4___d59 = rg_v1 < intDiv_rg_denom2 ; - assign rg_v1_ULT_rg_v2___d55 = rg_v1 < rg_v2 ; - assign rg_v2_BITS_31_TO_0__q5 = rg_v2[31:0] ; - assign v1__h4494 = { 64'd0, rg_v1 } ; - assign v__h4418 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b001) ? - SEXT_rg_v1__08_MUL_SEXT_rg_v2__09___d110[127:64] : - v__h4476 ; - assign v__h4476 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b011) ? - _0_CONCAT_rg_v1_13_MUL_0_CONCAT_rg_v2_14___d115[127:64] : - v__h4527 ; - assign v__h4527 = - (rg_is_OP_not_OP_32 && rg_f3 == 3'b010) ? - SEXT_rg_v1__08_MUL_0_CONCAT_rg_v2_14___d118[127:64] : - v__h4583 ; - assign v__h4583 = - (!rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ? - v__h4600 : - 64'hFFFFFFFFFFFFFFFF ; - assign v__h4600 = - { {32{SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6[31]}}, - SEXT_rg_v1_BITS_31_TO_0_21_22_MUL_SEXT_rg_v2_B_ETC__q6 } ; - assign x__h3955 = rg_v1 - intDiv_rg_denom2 ; - assign x__h4041 = -intDiv_rg_quo ; - assign x__h4111 = -rg_v1 ; - assign x__h4126 = intDiv_rg_quo + intDiv_rg_n ; - assign y__h3834 = { 1'd0, rg_v1[63:1] } ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (intDiv_rg_state$EN) - intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY intDiv_rg_state$D_IN; - end - if (intDiv_rg_denom2$EN) - intDiv_rg_denom2 <= `BSV_ASSIGNMENT_DELAY intDiv_rg_denom2$D_IN; - if (intDiv_rg_denom_is_signed$EN) - intDiv_rg_denom_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_denom_is_signed$D_IN; - if (intDiv_rg_n$EN) intDiv_rg_n <= `BSV_ASSIGNMENT_DELAY intDiv_rg_n$D_IN; - if (intDiv_rg_numer_is_signed$EN) - intDiv_rg_numer_is_signed <= `BSV_ASSIGNMENT_DELAY - intDiv_rg_numer_is_signed$D_IN; - if (intDiv_rg_quo$EN) - intDiv_rg_quo <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quo$D_IN; - if (intDiv_rg_quoIsNeg$EN) - intDiv_rg_quoIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quoIsNeg$D_IN; - if (intDiv_rg_remIsNeg$EN) - intDiv_rg_remIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_remIsNeg$D_IN; - if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN; - if (rg_is_OP_not_OP_32$EN) - rg_is_OP_not_OP_32 <= `BSV_ASSIGNMENT_DELAY rg_is_OP_not_OP_32$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - if (rg_v1$EN) rg_v1 <= `BSV_ASSIGNMENT_DELAY rg_v1$D_IN; - if (rg_v2$EN) rg_v2 <= `BSV_ASSIGNMENT_DELAY rg_v2$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - intDiv_rg_denom2 = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_denom_is_signed = 1'h0; - intDiv_rg_n = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_numer_is_signed = 1'h0; - intDiv_rg_quo = 64'hAAAAAAAAAAAAAAAA; - intDiv_rg_quoIsNeg = 1'h0; - intDiv_rg_remIsNeg = 1'h0; - intDiv_rg_state = 3'h2; - rg_f3 = 3'h2; - rg_is_OP_not_OP_32 = 1'h0; - rg_state = 2'h2; - rg_v1 = 64'hAAAAAAAAAAAAAAAA; - rg_v2 = 64'hAAAAAAAAAAAAAAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && cfg_verbosity > 4'd1) - $display(" RISCV_MBox.rl_mul"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - begin - v__h4706 = $stime; - #0; - end - v__h4700 = v__h4706 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $display("%0d: ERROR: RISCV_MBox.rl_mul: illegal f3.", v__h4700); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $display(" f3 0x%0h v1 0x%0h v2 0x%0h", rg_f3, rg_v1, rg_v2); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) && - (!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) && - (rg_is_OP_not_OP_32 || rg_f3 != 3'b0)) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkRISCV_MBox - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v deleted file mode 100644 index c88e21cd..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Map.v +++ /dev/null @@ -1,298 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// m_near_mem_io_addr_base O 64 const -// m_near_mem_io_addr_size O 64 const -// m_near_mem_io_addr_lim O 64 const -// m_plic_addr_base O 64 const -// m_plic_addr_size O 64 const -// m_plic_addr_lim O 64 const -// m_uart0_addr_base O 64 const -// m_uart0_addr_size O 64 const -// m_uart0_addr_lim O 64 const -// m_boot_rom_addr_base O 64 const -// m_boot_rom_addr_size O 64 const -// m_boot_rom_addr_lim O 64 const -// m_mem0_controller_addr_base O 64 const -// m_mem0_controller_addr_size O 64 const -// m_mem0_controller_addr_lim O 64 const -// m_tcm_addr_base O 64 const -// m_tcm_addr_size O 64 const -// m_tcm_addr_lim O 64 const -// m_is_mem_addr O 1 -// m_is_IO_addr O 1 -// m_is_near_mem_IO_addr O 1 -// m_pc_reset_value O 64 const -// m_mtvec_reset_value O 64 const -// m_nmivec_reset_value O 64 const -// CLK I 1 unused -// RST_N I 1 unused -// m_is_mem_addr_addr I 64 -// m_is_IO_addr_addr I 64 -// m_is_near_mem_IO_addr_addr I 64 -// -// Combinational paths from inputs to outputs: -// m_is_mem_addr_addr -> m_is_mem_addr -// m_is_IO_addr_addr -> m_is_IO_addr -// m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Map(CLK, - RST_N, - - m_near_mem_io_addr_base, - - m_near_mem_io_addr_size, - - m_near_mem_io_addr_lim, - - m_plic_addr_base, - - m_plic_addr_size, - - m_plic_addr_lim, - - m_uart0_addr_base, - - m_uart0_addr_size, - - m_uart0_addr_lim, - - m_boot_rom_addr_base, - - m_boot_rom_addr_size, - - m_boot_rom_addr_lim, - - m_mem0_controller_addr_base, - - m_mem0_controller_addr_size, - - m_mem0_controller_addr_lim, - - m_tcm_addr_base, - - m_tcm_addr_size, - - m_tcm_addr_lim, - - m_is_mem_addr_addr, - m_is_mem_addr, - - m_is_IO_addr_addr, - m_is_IO_addr, - - m_is_near_mem_IO_addr_addr, - m_is_near_mem_IO_addr, - - m_pc_reset_value, - - m_mtvec_reset_value, - - m_nmivec_reset_value); - input CLK; - input RST_N; - - // value method m_near_mem_io_addr_base - output [63 : 0] m_near_mem_io_addr_base; - - // value method m_near_mem_io_addr_size - output [63 : 0] m_near_mem_io_addr_size; - - // value method m_near_mem_io_addr_lim - output [63 : 0] m_near_mem_io_addr_lim; - - // value method m_plic_addr_base - output [63 : 0] m_plic_addr_base; - - // value method m_plic_addr_size - output [63 : 0] m_plic_addr_size; - - // value method m_plic_addr_lim - output [63 : 0] m_plic_addr_lim; - - // value method m_uart0_addr_base - output [63 : 0] m_uart0_addr_base; - - // value method m_uart0_addr_size - output [63 : 0] m_uart0_addr_size; - - // value method m_uart0_addr_lim - output [63 : 0] m_uart0_addr_lim; - - // value method m_boot_rom_addr_base - output [63 : 0] m_boot_rom_addr_base; - - // value method m_boot_rom_addr_size - output [63 : 0] m_boot_rom_addr_size; - - // value method m_boot_rom_addr_lim - output [63 : 0] m_boot_rom_addr_lim; - - // value method m_mem0_controller_addr_base - output [63 : 0] m_mem0_controller_addr_base; - - // value method m_mem0_controller_addr_size - output [63 : 0] m_mem0_controller_addr_size; - - // value method m_mem0_controller_addr_lim - output [63 : 0] m_mem0_controller_addr_lim; - - // value method m_tcm_addr_base - output [63 : 0] m_tcm_addr_base; - - // value method m_tcm_addr_size - output [63 : 0] m_tcm_addr_size; - - // value method m_tcm_addr_lim - output [63 : 0] m_tcm_addr_lim; - - // value method m_is_mem_addr - input [63 : 0] m_is_mem_addr_addr; - output m_is_mem_addr; - - // value method m_is_IO_addr - input [63 : 0] m_is_IO_addr_addr; - output m_is_IO_addr; - - // value method m_is_near_mem_IO_addr - input [63 : 0] m_is_near_mem_IO_addr_addr; - output m_is_near_mem_IO_addr; - - // value method m_pc_reset_value - output [63 : 0] m_pc_reset_value; - - // value method m_mtvec_reset_value - output [63 : 0] m_mtvec_reset_value; - - // value method m_nmivec_reset_value - output [63 : 0] m_nmivec_reset_value; - - // signals for module outputs - wire [63 : 0] m_boot_rom_addr_base, - m_boot_rom_addr_lim, - m_boot_rom_addr_size, - m_mem0_controller_addr_base, - m_mem0_controller_addr_lim, - m_mem0_controller_addr_size, - m_mtvec_reset_value, - m_near_mem_io_addr_base, - m_near_mem_io_addr_lim, - m_near_mem_io_addr_size, - m_nmivec_reset_value, - m_pc_reset_value, - m_plic_addr_base, - m_plic_addr_lim, - m_plic_addr_size, - m_tcm_addr_base, - m_tcm_addr_lim, - m_tcm_addr_size, - m_uart0_addr_base, - m_uart0_addr_lim, - m_uart0_addr_size; - wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; - - // value method m_near_mem_io_addr_base - assign m_near_mem_io_addr_base = 64'h0000000002000000 ; - - // value method m_near_mem_io_addr_size - assign m_near_mem_io_addr_size = 64'h000000000000C000 ; - - // value method m_near_mem_io_addr_lim - assign m_near_mem_io_addr_lim = 64'd33603584 ; - - // value method m_plic_addr_base - assign m_plic_addr_base = 64'h000000000C000000 ; - - // value method m_plic_addr_size - assign m_plic_addr_size = 64'h0000000000400000 ; - - // value method m_plic_addr_lim - assign m_plic_addr_lim = 64'd205520896 ; - - // value method m_uart0_addr_base - assign m_uart0_addr_base = 64'h00000000C0000000 ; - - // value method m_uart0_addr_size - assign m_uart0_addr_size = 64'h0000000000000080 ; - - // value method m_uart0_addr_lim - assign m_uart0_addr_lim = 64'h00000000C0000080 ; - - // value method m_boot_rom_addr_base - assign m_boot_rom_addr_base = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_size - assign m_boot_rom_addr_size = 64'h0000000000001000 ; - - // value method m_boot_rom_addr_lim - assign m_boot_rom_addr_lim = 64'd8192 ; - - // value method m_mem0_controller_addr_base - assign m_mem0_controller_addr_base = 64'h0000000080000000 ; - - // value method m_mem0_controller_addr_size - assign m_mem0_controller_addr_size = 64'h0000000010000000 ; - - // value method m_mem0_controller_addr_lim - assign m_mem0_controller_addr_lim = 64'h0000000090000000 ; - - // value method m_tcm_addr_base - assign m_tcm_addr_base = 64'h0 ; - - // value method m_tcm_addr_size - assign m_tcm_addr_size = 64'd0 ; - - // value method m_tcm_addr_lim - assign m_tcm_addr_lim = 64'd0 ; - - // value method m_is_mem_addr - assign m_is_mem_addr = - m_is_mem_addr_addr >= 64'h0000000000001000 && - m_is_mem_addr_addr < 64'd8192 || - m_is_mem_addr_addr >= 64'h0000000080000000 && - m_is_mem_addr_addr < 64'h0000000090000000 ; - - // value method m_is_IO_addr - assign m_is_IO_addr = - m_is_IO_addr_addr >= 64'h0000000002000000 && - m_is_IO_addr_addr < 64'd33603584 || - m_is_IO_addr_addr >= 64'h000000000C000000 && - m_is_IO_addr_addr < 64'd205520896 || - m_is_IO_addr_addr >= 64'h00000000C0000000 && - m_is_IO_addr_addr < 64'h00000000C0000080 ; - - // value method m_is_near_mem_IO_addr - assign m_is_near_mem_IO_addr = - m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 && - m_is_near_mem_IO_addr_addr < 64'd33603584 ; - - // value method m_pc_reset_value - assign m_pc_reset_value = 64'h0000000000001000 ; - - // value method m_mtvec_reset_value - assign m_mtvec_reset_value = 64'h0000000000001000 ; - - // value method m_nmivec_reset_value - assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ; -endmodule // mkSoC_Map - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v deleted file mode 100644 index 42e03763..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkSoC_Top.v +++ /dev/null @@ -1,2333 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_set_verbosity O 1 const -// to_raw_mem_request_get O 353 -// RDY_to_raw_mem_request_get O 1 -// RDY_to_raw_mem_response_put O 1 -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// status O 8 reg -// RDY_set_watch_tohost O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// set_verbosity_logdelay I 64 reg -// to_raw_mem_response_put I 256 -// put_from_console_put I 8 reg -// set_watch_tohost_watch_tohost I 1 reg -// set_watch_tohost_tohost_addr I 64 reg -// EN_set_verbosity I 1 -// EN_to_raw_mem_response_put I 1 -// EN_put_from_console_put I 1 -// EN_set_watch_tohost I 1 -// EN_to_raw_mem_request_get I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkSoC_Top(CLK, - RST_N, - - set_verbosity_verbosity, - set_verbosity_logdelay, - EN_set_verbosity, - RDY_set_verbosity, - - EN_to_raw_mem_request_get, - to_raw_mem_request_get, - RDY_to_raw_mem_request_get, - - to_raw_mem_response_put, - EN_to_raw_mem_response_put, - RDY_to_raw_mem_response_put, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - status, - - set_watch_tohost_watch_tohost, - set_watch_tohost_tohost_addr, - EN_set_watch_tohost, - RDY_set_watch_tohost); - input CLK; - input RST_N; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input [63 : 0] set_verbosity_logdelay; - input EN_set_verbosity; - output RDY_set_verbosity; - - // actionvalue method to_raw_mem_request_get - input EN_to_raw_mem_request_get; - output [352 : 0] to_raw_mem_request_get; - output RDY_to_raw_mem_request_get; - - // action method to_raw_mem_response_put - input [255 : 0] to_raw_mem_response_put; - input EN_to_raw_mem_response_put; - output RDY_to_raw_mem_response_put; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method status - output [7 : 0] status; - - // action method set_watch_tohost - input set_watch_tohost_watch_tohost; - input [63 : 0] set_watch_tohost_tohost_addr; - input EN_set_watch_tohost; - output RDY_set_watch_tohost; - - // signals for module outputs - wire [352 : 0] to_raw_mem_request_get; - wire [7 : 0] get_to_console_get, status; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_set_verbosity, - RDY_set_watch_tohost, - RDY_to_raw_mem_request_get, - RDY_to_raw_mem_response_put; - - // register rg_state - reg [1 : 0] rg_state; - wire [1 : 0] rg_state$D_IN; - wire rg_state$EN; - - // ports of submodule boot_rom - wire [63 : 0] boot_rom$set_addr_map_addr_base, - boot_rom$set_addr_map_addr_lim, - boot_rom$slave_araddr, - boot_rom$slave_awaddr, - boot_rom$slave_rdata, - boot_rom$slave_wdata; - wire [7 : 0] boot_rom$slave_arlen, - boot_rom$slave_awlen, - boot_rom$slave_wstrb; - wire [3 : 0] boot_rom$slave_arcache, - boot_rom$slave_arid, - boot_rom$slave_arqos, - boot_rom$slave_arregion, - boot_rom$slave_awcache, - boot_rom$slave_awid, - boot_rom$slave_awqos, - boot_rom$slave_awregion, - boot_rom$slave_bid, - boot_rom$slave_rid, - boot_rom$slave_wid; - wire [2 : 0] boot_rom$slave_arprot, - boot_rom$slave_arsize, - boot_rom$slave_awprot, - boot_rom$slave_awsize; - wire [1 : 0] boot_rom$slave_arburst, - boot_rom$slave_awburst, - boot_rom$slave_bresp, - boot_rom$slave_rresp; - wire boot_rom$EN_set_addr_map, - boot_rom$slave_arlock, - boot_rom$slave_arready, - boot_rom$slave_arvalid, - boot_rom$slave_awlock, - boot_rom$slave_awready, - boot_rom$slave_awvalid, - boot_rom$slave_bready, - boot_rom$slave_bvalid, - boot_rom$slave_rlast, - boot_rom$slave_rready, - boot_rom$slave_rvalid, - boot_rom$slave_wlast, - boot_rom$slave_wready, - boot_rom$slave_wvalid; - - // ports of submodule boot_rom_axi4_deburster - wire [63 : 0] boot_rom_axi4_deburster$from_master_araddr, - boot_rom_axi4_deburster$from_master_awaddr, - boot_rom_axi4_deburster$from_master_rdata, - boot_rom_axi4_deburster$from_master_wdata, - boot_rom_axi4_deburster$to_slave_araddr, - boot_rom_axi4_deburster$to_slave_awaddr, - boot_rom_axi4_deburster$to_slave_rdata, - boot_rom_axi4_deburster$to_slave_wdata; - wire [7 : 0] boot_rom_axi4_deburster$from_master_arlen, - boot_rom_axi4_deburster$from_master_awlen, - boot_rom_axi4_deburster$from_master_wstrb, - boot_rom_axi4_deburster$to_slave_arlen, - boot_rom_axi4_deburster$to_slave_awlen, - boot_rom_axi4_deburster$to_slave_wstrb; - wire [3 : 0] boot_rom_axi4_deburster$from_master_arcache, - boot_rom_axi4_deburster$from_master_arid, - boot_rom_axi4_deburster$from_master_arqos, - boot_rom_axi4_deburster$from_master_arregion, - boot_rom_axi4_deburster$from_master_awcache, - boot_rom_axi4_deburster$from_master_awid, - boot_rom_axi4_deburster$from_master_awqos, - boot_rom_axi4_deburster$from_master_awregion, - boot_rom_axi4_deburster$from_master_bid, - boot_rom_axi4_deburster$from_master_rid, - boot_rom_axi4_deburster$from_master_wid, - boot_rom_axi4_deburster$to_slave_arcache, - boot_rom_axi4_deburster$to_slave_arid, - boot_rom_axi4_deburster$to_slave_arqos, - boot_rom_axi4_deburster$to_slave_arregion, - boot_rom_axi4_deburster$to_slave_awcache, - boot_rom_axi4_deburster$to_slave_awid, - boot_rom_axi4_deburster$to_slave_awqos, - boot_rom_axi4_deburster$to_slave_awregion, - boot_rom_axi4_deburster$to_slave_bid, - boot_rom_axi4_deburster$to_slave_rid, - boot_rom_axi4_deburster$to_slave_wid; - wire [2 : 0] boot_rom_axi4_deburster$from_master_arprot, - boot_rom_axi4_deburster$from_master_arsize, - boot_rom_axi4_deburster$from_master_awprot, - boot_rom_axi4_deburster$from_master_awsize, - boot_rom_axi4_deburster$to_slave_arprot, - boot_rom_axi4_deburster$to_slave_arsize, - boot_rom_axi4_deburster$to_slave_awprot, - boot_rom_axi4_deburster$to_slave_awsize; - wire [1 : 0] boot_rom_axi4_deburster$from_master_arburst, - boot_rom_axi4_deburster$from_master_awburst, - boot_rom_axi4_deburster$from_master_bresp, - boot_rom_axi4_deburster$from_master_rresp, - boot_rom_axi4_deburster$to_slave_arburst, - boot_rom_axi4_deburster$to_slave_awburst, - boot_rom_axi4_deburster$to_slave_bresp, - boot_rom_axi4_deburster$to_slave_rresp; - wire boot_rom_axi4_deburster$EN_reset, - boot_rom_axi4_deburster$from_master_arlock, - boot_rom_axi4_deburster$from_master_arready, - boot_rom_axi4_deburster$from_master_arvalid, - boot_rom_axi4_deburster$from_master_awlock, - boot_rom_axi4_deburster$from_master_awready, - boot_rom_axi4_deburster$from_master_awvalid, - boot_rom_axi4_deburster$from_master_bready, - boot_rom_axi4_deburster$from_master_bvalid, - boot_rom_axi4_deburster$from_master_rlast, - boot_rom_axi4_deburster$from_master_rready, - boot_rom_axi4_deburster$from_master_rvalid, - boot_rom_axi4_deburster$from_master_wlast, - boot_rom_axi4_deburster$from_master_wready, - boot_rom_axi4_deburster$from_master_wvalid, - boot_rom_axi4_deburster$to_slave_arlock, - boot_rom_axi4_deburster$to_slave_arready, - boot_rom_axi4_deburster$to_slave_arvalid, - boot_rom_axi4_deburster$to_slave_awlock, - boot_rom_axi4_deburster$to_slave_awready, - boot_rom_axi4_deburster$to_slave_awvalid, - boot_rom_axi4_deburster$to_slave_bready, - boot_rom_axi4_deburster$to_slave_bvalid, - boot_rom_axi4_deburster$to_slave_rlast, - boot_rom_axi4_deburster$to_slave_rready, - boot_rom_axi4_deburster$to_slave_rvalid, - boot_rom_axi4_deburster$to_slave_wlast, - boot_rom_axi4_deburster$to_slave_wready, - boot_rom_axi4_deburster$to_slave_wvalid; - - // ports of submodule core - wire [63 : 0] core$cpu_dmem_master_araddr, - core$cpu_dmem_master_awaddr, - core$cpu_dmem_master_rdata, - core$cpu_dmem_master_wdata, - core$cpu_imem_master_araddr, - core$cpu_imem_master_awaddr, - core$cpu_imem_master_rdata, - core$cpu_imem_master_wdata, - core$set_verbosity_logdelay; - wire [7 : 0] core$cpu_dmem_master_arlen, - core$cpu_dmem_master_awlen, - core$cpu_dmem_master_wstrb, - core$cpu_imem_master_arlen, - core$cpu_imem_master_awlen, - core$cpu_imem_master_wstrb; - wire [3 : 0] core$cpu_dmem_master_arcache, - core$cpu_dmem_master_arid, - core$cpu_dmem_master_arqos, - core$cpu_dmem_master_arregion, - core$cpu_dmem_master_awcache, - core$cpu_dmem_master_awid, - core$cpu_dmem_master_awqos, - core$cpu_dmem_master_awregion, - core$cpu_dmem_master_bid, - core$cpu_dmem_master_rid, - core$cpu_dmem_master_wid, - core$cpu_imem_master_arcache, - core$cpu_imem_master_arid, - core$cpu_imem_master_arqos, - core$cpu_imem_master_arregion, - core$cpu_imem_master_awcache, - core$cpu_imem_master_awid, - core$cpu_imem_master_awqos, - core$cpu_imem_master_awregion, - core$cpu_imem_master_bid, - core$cpu_imem_master_rid, - core$cpu_imem_master_wid, - core$set_verbosity_verbosity; - wire [2 : 0] core$cpu_dmem_master_arprot, - core$cpu_dmem_master_arsize, - core$cpu_dmem_master_awprot, - core$cpu_dmem_master_awsize, - core$cpu_imem_master_arprot, - core$cpu_imem_master_arsize, - core$cpu_imem_master_awprot, - core$cpu_imem_master_awsize; - wire [1 : 0] core$cpu_dmem_master_arburst, - core$cpu_dmem_master_awburst, - core$cpu_dmem_master_bresp, - core$cpu_dmem_master_rresp, - core$cpu_imem_master_arburst, - core$cpu_imem_master_awburst, - core$cpu_imem_master_bresp, - core$cpu_imem_master_rresp; - wire core$EN_cpu_reset_server_request_put, - core$EN_cpu_reset_server_response_get, - core$EN_set_verbosity, - core$RDY_cpu_reset_server_request_put, - core$RDY_cpu_reset_server_response_get, - core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear, - core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear, - core$cpu_dmem_master_arlock, - core$cpu_dmem_master_arready, - core$cpu_dmem_master_arvalid, - core$cpu_dmem_master_awlock, - core$cpu_dmem_master_awready, - core$cpu_dmem_master_awvalid, - core$cpu_dmem_master_bready, - core$cpu_dmem_master_bvalid, - core$cpu_dmem_master_rlast, - core$cpu_dmem_master_rready, - core$cpu_dmem_master_rvalid, - core$cpu_dmem_master_wlast, - core$cpu_dmem_master_wready, - core$cpu_dmem_master_wvalid, - core$cpu_imem_master_arlock, - core$cpu_imem_master_arready, - core$cpu_imem_master_arvalid, - core$cpu_imem_master_awlock, - core$cpu_imem_master_awready, - core$cpu_imem_master_awvalid, - core$cpu_imem_master_bready, - core$cpu_imem_master_bvalid, - core$cpu_imem_master_rlast, - core$cpu_imem_master_rready, - core$cpu_imem_master_rvalid, - core$cpu_imem_master_wlast, - core$cpu_imem_master_wready, - core$cpu_imem_master_wvalid, - core$cpu_reset_server_request_put, - core$nmi_req_set_not_clear; - - // ports of submodule fabric - wire [63 : 0] fabric$v_from_masters_0_araddr, - fabric$v_from_masters_0_awaddr, - fabric$v_from_masters_0_rdata, - fabric$v_from_masters_0_wdata, - fabric$v_from_masters_1_araddr, - fabric$v_from_masters_1_awaddr, - fabric$v_from_masters_1_rdata, - fabric$v_from_masters_1_wdata, - fabric$v_to_slaves_0_araddr, - fabric$v_to_slaves_0_awaddr, - fabric$v_to_slaves_0_rdata, - fabric$v_to_slaves_0_wdata, - fabric$v_to_slaves_1_araddr, - fabric$v_to_slaves_1_awaddr, - fabric$v_to_slaves_1_rdata, - fabric$v_to_slaves_1_wdata, - fabric$v_to_slaves_2_araddr, - fabric$v_to_slaves_2_awaddr, - fabric$v_to_slaves_2_rdata, - fabric$v_to_slaves_2_wdata; - wire [7 : 0] fabric$v_from_masters_0_arlen, - fabric$v_from_masters_0_awlen, - fabric$v_from_masters_0_wstrb, - fabric$v_from_masters_1_arlen, - fabric$v_from_masters_1_awlen, - fabric$v_from_masters_1_wstrb, - fabric$v_to_slaves_0_arlen, - fabric$v_to_slaves_0_awlen, - fabric$v_to_slaves_0_wstrb, - fabric$v_to_slaves_1_arlen, - fabric$v_to_slaves_1_awlen, - fabric$v_to_slaves_1_wstrb, - fabric$v_to_slaves_2_arlen, - fabric$v_to_slaves_2_awlen, - fabric$v_to_slaves_2_wstrb; - wire [3 : 0] fabric$set_verbosity_verbosity, - fabric$v_from_masters_0_arcache, - fabric$v_from_masters_0_arid, - fabric$v_from_masters_0_arqos, - fabric$v_from_masters_0_arregion, - fabric$v_from_masters_0_awcache, - fabric$v_from_masters_0_awid, - fabric$v_from_masters_0_awqos, - fabric$v_from_masters_0_awregion, - fabric$v_from_masters_0_bid, - fabric$v_from_masters_0_rid, - fabric$v_from_masters_0_wid, - fabric$v_from_masters_1_arcache, - fabric$v_from_masters_1_arid, - fabric$v_from_masters_1_arqos, - fabric$v_from_masters_1_arregion, - fabric$v_from_masters_1_awcache, - fabric$v_from_masters_1_awid, - fabric$v_from_masters_1_awqos, - fabric$v_from_masters_1_awregion, - fabric$v_from_masters_1_bid, - fabric$v_from_masters_1_rid, - fabric$v_from_masters_1_wid, - fabric$v_to_slaves_0_arcache, - fabric$v_to_slaves_0_arid, - fabric$v_to_slaves_0_arqos, - fabric$v_to_slaves_0_arregion, - fabric$v_to_slaves_0_awcache, - fabric$v_to_slaves_0_awid, - fabric$v_to_slaves_0_awqos, - fabric$v_to_slaves_0_awregion, - fabric$v_to_slaves_0_bid, - fabric$v_to_slaves_0_rid, - fabric$v_to_slaves_0_wid, - fabric$v_to_slaves_1_arcache, - fabric$v_to_slaves_1_arid, - fabric$v_to_slaves_1_arqos, - fabric$v_to_slaves_1_arregion, - fabric$v_to_slaves_1_awcache, - fabric$v_to_slaves_1_awid, - fabric$v_to_slaves_1_awqos, - fabric$v_to_slaves_1_awregion, - fabric$v_to_slaves_1_bid, - fabric$v_to_slaves_1_rid, - fabric$v_to_slaves_1_wid, - fabric$v_to_slaves_2_arcache, - fabric$v_to_slaves_2_arid, - fabric$v_to_slaves_2_arqos, - fabric$v_to_slaves_2_arregion, - fabric$v_to_slaves_2_awcache, - fabric$v_to_slaves_2_awid, - fabric$v_to_slaves_2_awqos, - fabric$v_to_slaves_2_awregion, - fabric$v_to_slaves_2_bid, - fabric$v_to_slaves_2_rid, - fabric$v_to_slaves_2_wid; - wire [2 : 0] fabric$v_from_masters_0_arprot, - fabric$v_from_masters_0_arsize, - fabric$v_from_masters_0_awprot, - fabric$v_from_masters_0_awsize, - fabric$v_from_masters_1_arprot, - fabric$v_from_masters_1_arsize, - fabric$v_from_masters_1_awprot, - fabric$v_from_masters_1_awsize, - fabric$v_to_slaves_0_arprot, - fabric$v_to_slaves_0_arsize, - fabric$v_to_slaves_0_awprot, - fabric$v_to_slaves_0_awsize, - fabric$v_to_slaves_1_arprot, - fabric$v_to_slaves_1_arsize, - fabric$v_to_slaves_1_awprot, - fabric$v_to_slaves_1_awsize, - fabric$v_to_slaves_2_arprot, - fabric$v_to_slaves_2_arsize, - fabric$v_to_slaves_2_awprot, - fabric$v_to_slaves_2_awsize; - wire [1 : 0] fabric$v_from_masters_0_arburst, - fabric$v_from_masters_0_awburst, - fabric$v_from_masters_0_bresp, - fabric$v_from_masters_0_rresp, - fabric$v_from_masters_1_arburst, - fabric$v_from_masters_1_awburst, - fabric$v_from_masters_1_bresp, - fabric$v_from_masters_1_rresp, - fabric$v_to_slaves_0_arburst, - fabric$v_to_slaves_0_awburst, - fabric$v_to_slaves_0_bresp, - fabric$v_to_slaves_0_rresp, - fabric$v_to_slaves_1_arburst, - fabric$v_to_slaves_1_awburst, - fabric$v_to_slaves_1_bresp, - fabric$v_to_slaves_1_rresp, - fabric$v_to_slaves_2_arburst, - fabric$v_to_slaves_2_awburst, - fabric$v_to_slaves_2_bresp, - fabric$v_to_slaves_2_rresp; - wire fabric$EN_reset, - fabric$EN_set_verbosity, - fabric$RDY_reset, - fabric$v_from_masters_0_arlock, - fabric$v_from_masters_0_arready, - fabric$v_from_masters_0_arvalid, - fabric$v_from_masters_0_awlock, - fabric$v_from_masters_0_awready, - fabric$v_from_masters_0_awvalid, - fabric$v_from_masters_0_bready, - fabric$v_from_masters_0_bvalid, - fabric$v_from_masters_0_rlast, - fabric$v_from_masters_0_rready, - fabric$v_from_masters_0_rvalid, - fabric$v_from_masters_0_wlast, - fabric$v_from_masters_0_wready, - fabric$v_from_masters_0_wvalid, - fabric$v_from_masters_1_arlock, - fabric$v_from_masters_1_arready, - fabric$v_from_masters_1_arvalid, - fabric$v_from_masters_1_awlock, - fabric$v_from_masters_1_awready, - fabric$v_from_masters_1_awvalid, - fabric$v_from_masters_1_bready, - fabric$v_from_masters_1_bvalid, - fabric$v_from_masters_1_rlast, - fabric$v_from_masters_1_rready, - fabric$v_from_masters_1_rvalid, - fabric$v_from_masters_1_wlast, - fabric$v_from_masters_1_wready, - fabric$v_from_masters_1_wvalid, - fabric$v_to_slaves_0_arlock, - fabric$v_to_slaves_0_arready, - fabric$v_to_slaves_0_arvalid, - fabric$v_to_slaves_0_awlock, - fabric$v_to_slaves_0_awready, - fabric$v_to_slaves_0_awvalid, - fabric$v_to_slaves_0_bready, - fabric$v_to_slaves_0_bvalid, - fabric$v_to_slaves_0_rlast, - fabric$v_to_slaves_0_rready, - fabric$v_to_slaves_0_rvalid, - fabric$v_to_slaves_0_wlast, - fabric$v_to_slaves_0_wready, - fabric$v_to_slaves_0_wvalid, - fabric$v_to_slaves_1_arlock, - fabric$v_to_slaves_1_arready, - fabric$v_to_slaves_1_arvalid, - fabric$v_to_slaves_1_awlock, - fabric$v_to_slaves_1_awready, - fabric$v_to_slaves_1_awvalid, - fabric$v_to_slaves_1_bready, - fabric$v_to_slaves_1_bvalid, - fabric$v_to_slaves_1_rlast, - fabric$v_to_slaves_1_rready, - fabric$v_to_slaves_1_rvalid, - fabric$v_to_slaves_1_wlast, - fabric$v_to_slaves_1_wready, - fabric$v_to_slaves_1_wvalid, - fabric$v_to_slaves_2_arlock, - fabric$v_to_slaves_2_arready, - fabric$v_to_slaves_2_arvalid, - fabric$v_to_slaves_2_awlock, - fabric$v_to_slaves_2_awready, - fabric$v_to_slaves_2_awvalid, - fabric$v_to_slaves_2_bready, - fabric$v_to_slaves_2_bvalid, - fabric$v_to_slaves_2_rlast, - fabric$v_to_slaves_2_rready, - fabric$v_to_slaves_2_rvalid, - fabric$v_to_slaves_2_wlast, - fabric$v_to_slaves_2_wready, - fabric$v_to_slaves_2_wvalid; - - // ports of submodule mem0_controller - wire [352 : 0] mem0_controller$to_raw_mem_request_get; - wire [255 : 0] mem0_controller$to_raw_mem_response_put; - wire [63 : 0] mem0_controller$set_addr_map_addr_base, - mem0_controller$set_addr_map_addr_lim, - mem0_controller$set_watch_tohost_tohost_addr, - mem0_controller$slave_araddr, - mem0_controller$slave_awaddr, - mem0_controller$slave_rdata, - mem0_controller$slave_wdata; - wire [7 : 0] mem0_controller$slave_arlen, - mem0_controller$slave_awlen, - mem0_controller$slave_wstrb, - mem0_controller$status; - wire [3 : 0] mem0_controller$slave_arcache, - mem0_controller$slave_arid, - mem0_controller$slave_arqos, - mem0_controller$slave_arregion, - mem0_controller$slave_awcache, - mem0_controller$slave_awid, - mem0_controller$slave_awqos, - mem0_controller$slave_awregion, - mem0_controller$slave_bid, - mem0_controller$slave_rid, - mem0_controller$slave_wid; - wire [2 : 0] mem0_controller$slave_arprot, - mem0_controller$slave_arsize, - mem0_controller$slave_awprot, - mem0_controller$slave_awsize; - wire [1 : 0] mem0_controller$slave_arburst, - mem0_controller$slave_awburst, - mem0_controller$slave_bresp, - mem0_controller$slave_rresp; - wire mem0_controller$EN_server_reset_request_put, - mem0_controller$EN_server_reset_response_get, - mem0_controller$EN_set_addr_map, - mem0_controller$EN_set_watch_tohost, - mem0_controller$EN_to_raw_mem_request_get, - mem0_controller$EN_to_raw_mem_response_put, - mem0_controller$RDY_server_reset_request_put, - mem0_controller$RDY_server_reset_response_get, - mem0_controller$RDY_set_addr_map, - mem0_controller$RDY_to_raw_mem_request_get, - mem0_controller$RDY_to_raw_mem_response_put, - mem0_controller$set_watch_tohost_watch_tohost, - mem0_controller$slave_arlock, - mem0_controller$slave_arready, - mem0_controller$slave_arvalid, - mem0_controller$slave_awlock, - mem0_controller$slave_awready, - mem0_controller$slave_awvalid, - mem0_controller$slave_bready, - mem0_controller$slave_bvalid, - mem0_controller$slave_rlast, - mem0_controller$slave_rready, - mem0_controller$slave_rvalid, - mem0_controller$slave_wlast, - mem0_controller$slave_wready, - mem0_controller$slave_wvalid; - - // ports of submodule mem0_controller_axi4_deburster - wire [63 : 0] mem0_controller_axi4_deburster$from_master_araddr, - mem0_controller_axi4_deburster$from_master_awaddr, - mem0_controller_axi4_deburster$from_master_rdata, - mem0_controller_axi4_deburster$from_master_wdata, - mem0_controller_axi4_deburster$to_slave_araddr, - mem0_controller_axi4_deburster$to_slave_awaddr, - mem0_controller_axi4_deburster$to_slave_rdata, - mem0_controller_axi4_deburster$to_slave_wdata; - wire [7 : 0] mem0_controller_axi4_deburster$from_master_arlen, - mem0_controller_axi4_deburster$from_master_awlen, - mem0_controller_axi4_deburster$from_master_wstrb, - mem0_controller_axi4_deburster$to_slave_arlen, - mem0_controller_axi4_deburster$to_slave_awlen, - mem0_controller_axi4_deburster$to_slave_wstrb; - wire [3 : 0] mem0_controller_axi4_deburster$from_master_arcache, - mem0_controller_axi4_deburster$from_master_arid, - mem0_controller_axi4_deburster$from_master_arqos, - mem0_controller_axi4_deburster$from_master_arregion, - mem0_controller_axi4_deburster$from_master_awcache, - mem0_controller_axi4_deburster$from_master_awid, - mem0_controller_axi4_deburster$from_master_awqos, - mem0_controller_axi4_deburster$from_master_awregion, - mem0_controller_axi4_deburster$from_master_bid, - mem0_controller_axi4_deburster$from_master_rid, - mem0_controller_axi4_deburster$from_master_wid, - mem0_controller_axi4_deburster$to_slave_arcache, - mem0_controller_axi4_deburster$to_slave_arid, - mem0_controller_axi4_deburster$to_slave_arqos, - mem0_controller_axi4_deburster$to_slave_arregion, - mem0_controller_axi4_deburster$to_slave_awcache, - mem0_controller_axi4_deburster$to_slave_awid, - mem0_controller_axi4_deburster$to_slave_awqos, - mem0_controller_axi4_deburster$to_slave_awregion, - mem0_controller_axi4_deburster$to_slave_bid, - mem0_controller_axi4_deburster$to_slave_rid, - mem0_controller_axi4_deburster$to_slave_wid; - wire [2 : 0] mem0_controller_axi4_deburster$from_master_arprot, - mem0_controller_axi4_deburster$from_master_arsize, - mem0_controller_axi4_deburster$from_master_awprot, - mem0_controller_axi4_deburster$from_master_awsize, - mem0_controller_axi4_deburster$to_slave_arprot, - mem0_controller_axi4_deburster$to_slave_arsize, - mem0_controller_axi4_deburster$to_slave_awprot, - mem0_controller_axi4_deburster$to_slave_awsize; - wire [1 : 0] mem0_controller_axi4_deburster$from_master_arburst, - mem0_controller_axi4_deburster$from_master_awburst, - mem0_controller_axi4_deburster$from_master_bresp, - mem0_controller_axi4_deburster$from_master_rresp, - mem0_controller_axi4_deburster$to_slave_arburst, - mem0_controller_axi4_deburster$to_slave_awburst, - mem0_controller_axi4_deburster$to_slave_bresp, - mem0_controller_axi4_deburster$to_slave_rresp; - wire mem0_controller_axi4_deburster$EN_reset, - mem0_controller_axi4_deburster$from_master_arlock, - mem0_controller_axi4_deburster$from_master_arready, - mem0_controller_axi4_deburster$from_master_arvalid, - mem0_controller_axi4_deburster$from_master_awlock, - mem0_controller_axi4_deburster$from_master_awready, - mem0_controller_axi4_deburster$from_master_awvalid, - mem0_controller_axi4_deburster$from_master_bready, - mem0_controller_axi4_deburster$from_master_bvalid, - mem0_controller_axi4_deburster$from_master_rlast, - mem0_controller_axi4_deburster$from_master_rready, - mem0_controller_axi4_deburster$from_master_rvalid, - mem0_controller_axi4_deburster$from_master_wlast, - mem0_controller_axi4_deburster$from_master_wready, - mem0_controller_axi4_deburster$from_master_wvalid, - mem0_controller_axi4_deburster$to_slave_arlock, - mem0_controller_axi4_deburster$to_slave_arready, - mem0_controller_axi4_deburster$to_slave_arvalid, - mem0_controller_axi4_deburster$to_slave_awlock, - mem0_controller_axi4_deburster$to_slave_awready, - mem0_controller_axi4_deburster$to_slave_awvalid, - mem0_controller_axi4_deburster$to_slave_bready, - mem0_controller_axi4_deburster$to_slave_bvalid, - mem0_controller_axi4_deburster$to_slave_rlast, - mem0_controller_axi4_deburster$to_slave_rready, - mem0_controller_axi4_deburster$to_slave_rvalid, - mem0_controller_axi4_deburster$to_slave_wlast, - mem0_controller_axi4_deburster$to_slave_wready, - mem0_controller_axi4_deburster$to_slave_wvalid; - - // ports of submodule soc_map - wire [63 : 0] soc_map$m_boot_rom_addr_base, - soc_map$m_boot_rom_addr_lim, - soc_map$m_is_IO_addr_addr, - soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_mem0_controller_addr_base, - soc_map$m_mem0_controller_addr_lim, - soc_map$m_uart0_addr_base, - soc_map$m_uart0_addr_lim; - - // ports of submodule uart0 - wire [63 : 0] uart0$set_addr_map_addr_base, - uart0$set_addr_map_addr_lim, - uart0$slave_araddr, - uart0$slave_awaddr, - uart0$slave_rdata, - uart0$slave_wdata; - wire [7 : 0] uart0$get_to_console_get, - uart0$put_from_console_put, - uart0$slave_arlen, - uart0$slave_awlen, - uart0$slave_wstrb; - wire [3 : 0] uart0$slave_arcache, - uart0$slave_arid, - uart0$slave_arqos, - uart0$slave_arregion, - uart0$slave_awcache, - uart0$slave_awid, - uart0$slave_awqos, - uart0$slave_awregion, - uart0$slave_bid, - uart0$slave_rid, - uart0$slave_wid; - wire [2 : 0] uart0$slave_arprot, - uart0$slave_arsize, - uart0$slave_awprot, - uart0$slave_awsize; - wire [1 : 0] uart0$slave_arburst, - uart0$slave_awburst, - uart0$slave_bresp, - uart0$slave_rresp; - wire uart0$EN_get_to_console_get, - uart0$EN_put_from_console_put, - uart0$EN_server_reset_request_put, - uart0$EN_server_reset_response_get, - uart0$EN_set_addr_map, - uart0$RDY_get_to_console_get, - uart0$RDY_put_from_console_put, - uart0$RDY_server_reset_request_put, - uart0$RDY_server_reset_response_get, - uart0$intr, - uart0$slave_arlock, - uart0$slave_arready, - uart0$slave_arvalid, - uart0$slave_awlock, - uart0$slave_awready, - uart0$slave_awvalid, - uart0$slave_bready, - uart0$slave_bvalid, - uart0$slave_rlast, - uart0$slave_rready, - uart0$slave_rvalid, - uart0$slave_wlast, - uart0$slave_wready, - uart0$slave_wvalid; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_connect_external_interrupt_requests, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_addr_channel_5, - CAN_FIRE_RL_rl_rd_addr_channel_6, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, - CAN_FIRE_RL_rl_rd_data_channel_5, - CAN_FIRE_RL_rl_rd_data_channel_6, - CAN_FIRE_RL_rl_reset_complete_initial, - CAN_FIRE_RL_rl_reset_start_initial, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_addr_channel_5, - CAN_FIRE_RL_rl_wr_addr_channel_6, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_data_channel_5, - CAN_FIRE_RL_rl_wr_data_channel_6, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, - CAN_FIRE_RL_rl_wr_response_channel_5, - CAN_FIRE_RL_rl_wr_response_channel_6, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_set_verbosity, - CAN_FIRE_set_watch_tohost, - CAN_FIRE_to_raw_mem_request_get, - CAN_FIRE_to_raw_mem_response_put, - WILL_FIRE_RL_rl_connect_external_interrupt_requests, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_addr_channel_5, - WILL_FIRE_RL_rl_rd_addr_channel_6, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, - WILL_FIRE_RL_rl_rd_data_channel_5, - WILL_FIRE_RL_rl_rd_data_channel_6, - WILL_FIRE_RL_rl_reset_complete_initial, - WILL_FIRE_RL_rl_reset_start_initial, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_addr_channel_5, - WILL_FIRE_RL_rl_wr_addr_channel_6, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_data_channel_5, - WILL_FIRE_RL_rl_wr_data_channel_6, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, - WILL_FIRE_RL_rl_wr_response_channel_5, - WILL_FIRE_RL_rl_wr_response_channel_6, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_set_verbosity, - WILL_FIRE_set_watch_tohost, - WILL_FIRE_to_raw_mem_request_get, - WILL_FIRE_to_raw_mem_response_put; - - // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h11286; - reg [31 : 0] v__h11556; - reg [31 : 0] v__h11280; - reg [31 : 0] v__h11550; - // synopsys translate_on - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // actionvalue method to_raw_mem_request_get - assign to_raw_mem_request_get = mem0_controller$to_raw_mem_request_get ; - assign RDY_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign CAN_FIRE_to_raw_mem_request_get = - mem0_controller$RDY_to_raw_mem_request_get ; - assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ; - - // action method to_raw_mem_response_put - assign RDY_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign CAN_FIRE_to_raw_mem_response_put = - mem0_controller$RDY_to_raw_mem_response_put ; - assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ; - - // actionvalue method get_to_console_get - assign get_to_console_get = uart0$get_to_console_get ; - assign RDY_get_to_console_get = uart0$RDY_get_to_console_get ; - assign CAN_FIRE_get_to_console_get = uart0$RDY_get_to_console_get ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = uart0$RDY_put_from_console_put ; - assign CAN_FIRE_put_from_console_put = uart0$RDY_put_from_console_put ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method status - assign status = mem0_controller$status ; - - // action method set_watch_tohost - assign RDY_set_watch_tohost = 1'd1 ; - assign CAN_FIRE_set_watch_tohost = 1'd1 ; - assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ; - - // submodule boot_rom - mkBoot_ROM boot_rom(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(boot_rom$set_addr_map_addr_base), - .set_addr_map_addr_lim(boot_rom$set_addr_map_addr_lim), - .slave_araddr(boot_rom$slave_araddr), - .slave_arburst(boot_rom$slave_arburst), - .slave_arcache(boot_rom$slave_arcache), - .slave_arid(boot_rom$slave_arid), - .slave_arlen(boot_rom$slave_arlen), - .slave_arlock(boot_rom$slave_arlock), - .slave_arprot(boot_rom$slave_arprot), - .slave_arqos(boot_rom$slave_arqos), - .slave_arregion(boot_rom$slave_arregion), - .slave_arsize(boot_rom$slave_arsize), - .slave_arvalid(boot_rom$slave_arvalid), - .slave_awaddr(boot_rom$slave_awaddr), - .slave_awburst(boot_rom$slave_awburst), - .slave_awcache(boot_rom$slave_awcache), - .slave_awid(boot_rom$slave_awid), - .slave_awlen(boot_rom$slave_awlen), - .slave_awlock(boot_rom$slave_awlock), - .slave_awprot(boot_rom$slave_awprot), - .slave_awqos(boot_rom$slave_awqos), - .slave_awregion(boot_rom$slave_awregion), - .slave_awsize(boot_rom$slave_awsize), - .slave_awvalid(boot_rom$slave_awvalid), - .slave_bready(boot_rom$slave_bready), - .slave_rready(boot_rom$slave_rready), - .slave_wdata(boot_rom$slave_wdata), - .slave_wid(boot_rom$slave_wid), - .slave_wlast(boot_rom$slave_wlast), - .slave_wstrb(boot_rom$slave_wstrb), - .slave_wvalid(boot_rom$slave_wvalid), - .EN_set_addr_map(boot_rom$EN_set_addr_map), - .RDY_set_addr_map(), - .slave_awready(boot_rom$slave_awready), - .slave_wready(boot_rom$slave_wready), - .slave_bvalid(boot_rom$slave_bvalid), - .slave_bid(boot_rom$slave_bid), - .slave_bresp(boot_rom$slave_bresp), - .slave_arready(boot_rom$slave_arready), - .slave_rvalid(boot_rom$slave_rvalid), - .slave_rid(boot_rom$slave_rid), - .slave_rdata(boot_rom$slave_rdata), - .slave_rresp(boot_rom$slave_rresp), - .slave_rlast(boot_rom$slave_rlast)); - - // submodule boot_rom_axi4_deburster - mkAXI4_Deburster_A boot_rom_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(boot_rom_axi4_deburster$from_master_araddr), - .from_master_arburst(boot_rom_axi4_deburster$from_master_arburst), - .from_master_arcache(boot_rom_axi4_deburster$from_master_arcache), - .from_master_arid(boot_rom_axi4_deburster$from_master_arid), - .from_master_arlen(boot_rom_axi4_deburster$from_master_arlen), - .from_master_arlock(boot_rom_axi4_deburster$from_master_arlock), - .from_master_arprot(boot_rom_axi4_deburster$from_master_arprot), - .from_master_arqos(boot_rom_axi4_deburster$from_master_arqos), - .from_master_arregion(boot_rom_axi4_deburster$from_master_arregion), - .from_master_arsize(boot_rom_axi4_deburster$from_master_arsize), - .from_master_arvalid(boot_rom_axi4_deburster$from_master_arvalid), - .from_master_awaddr(boot_rom_axi4_deburster$from_master_awaddr), - .from_master_awburst(boot_rom_axi4_deburster$from_master_awburst), - .from_master_awcache(boot_rom_axi4_deburster$from_master_awcache), - .from_master_awid(boot_rom_axi4_deburster$from_master_awid), - .from_master_awlen(boot_rom_axi4_deburster$from_master_awlen), - .from_master_awlock(boot_rom_axi4_deburster$from_master_awlock), - .from_master_awprot(boot_rom_axi4_deburster$from_master_awprot), - .from_master_awqos(boot_rom_axi4_deburster$from_master_awqos), - .from_master_awregion(boot_rom_axi4_deburster$from_master_awregion), - .from_master_awsize(boot_rom_axi4_deburster$from_master_awsize), - .from_master_awvalid(boot_rom_axi4_deburster$from_master_awvalid), - .from_master_bready(boot_rom_axi4_deburster$from_master_bready), - .from_master_rready(boot_rom_axi4_deburster$from_master_rready), - .from_master_wdata(boot_rom_axi4_deburster$from_master_wdata), - .from_master_wid(boot_rom_axi4_deburster$from_master_wid), - .from_master_wlast(boot_rom_axi4_deburster$from_master_wlast), - .from_master_wstrb(boot_rom_axi4_deburster$from_master_wstrb), - .from_master_wvalid(boot_rom_axi4_deburster$from_master_wvalid), - .to_slave_arready(boot_rom_axi4_deburster$to_slave_arready), - .to_slave_awready(boot_rom_axi4_deburster$to_slave_awready), - .to_slave_bid(boot_rom_axi4_deburster$to_slave_bid), - .to_slave_bresp(boot_rom_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(boot_rom_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(boot_rom_axi4_deburster$to_slave_rdata), - .to_slave_rid(boot_rom_axi4_deburster$to_slave_rid), - .to_slave_rlast(boot_rom_axi4_deburster$to_slave_rlast), - .to_slave_rresp(boot_rom_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(boot_rom_axi4_deburster$to_slave_rvalid), - .to_slave_wready(boot_rom_axi4_deburster$to_slave_wready), - .EN_reset(boot_rom_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(boot_rom_axi4_deburster$from_master_awready), - .from_master_wready(boot_rom_axi4_deburster$from_master_wready), - .from_master_bvalid(boot_rom_axi4_deburster$from_master_bvalid), - .from_master_bid(boot_rom_axi4_deburster$from_master_bid), - .from_master_bresp(boot_rom_axi4_deburster$from_master_bresp), - .from_master_arready(boot_rom_axi4_deburster$from_master_arready), - .from_master_rvalid(boot_rom_axi4_deburster$from_master_rvalid), - .from_master_rid(boot_rom_axi4_deburster$from_master_rid), - .from_master_rdata(boot_rom_axi4_deburster$from_master_rdata), - .from_master_rresp(boot_rom_axi4_deburster$from_master_rresp), - .from_master_rlast(boot_rom_axi4_deburster$from_master_rlast), - .to_slave_awvalid(boot_rom_axi4_deburster$to_slave_awvalid), - .to_slave_awid(boot_rom_axi4_deburster$to_slave_awid), - .to_slave_awaddr(boot_rom_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(boot_rom_axi4_deburster$to_slave_awlen), - .to_slave_awsize(boot_rom_axi4_deburster$to_slave_awsize), - .to_slave_awburst(boot_rom_axi4_deburster$to_slave_awburst), - .to_slave_awlock(boot_rom_axi4_deburster$to_slave_awlock), - .to_slave_awcache(boot_rom_axi4_deburster$to_slave_awcache), - .to_slave_awprot(boot_rom_axi4_deburster$to_slave_awprot), - .to_slave_awqos(boot_rom_axi4_deburster$to_slave_awqos), - .to_slave_awregion(boot_rom_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(boot_rom_axi4_deburster$to_slave_wvalid), - .to_slave_wid(boot_rom_axi4_deburster$to_slave_wid), - .to_slave_wdata(boot_rom_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(boot_rom_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(boot_rom_axi4_deburster$to_slave_wlast), - .to_slave_bready(boot_rom_axi4_deburster$to_slave_bready), - .to_slave_arvalid(boot_rom_axi4_deburster$to_slave_arvalid), - .to_slave_arid(boot_rom_axi4_deburster$to_slave_arid), - .to_slave_araddr(boot_rom_axi4_deburster$to_slave_araddr), - .to_slave_arlen(boot_rom_axi4_deburster$to_slave_arlen), - .to_slave_arsize(boot_rom_axi4_deburster$to_slave_arsize), - .to_slave_arburst(boot_rom_axi4_deburster$to_slave_arburst), - .to_slave_arlock(boot_rom_axi4_deburster$to_slave_arlock), - .to_slave_arcache(boot_rom_axi4_deburster$to_slave_arcache), - .to_slave_arprot(boot_rom_axi4_deburster$to_slave_arprot), - .to_slave_arqos(boot_rom_axi4_deburster$to_slave_arqos), - .to_slave_arregion(boot_rom_axi4_deburster$to_slave_arregion), - .to_slave_rready(boot_rom_axi4_deburster$to_slave_rready)); - - // submodule core - mkCore core(.CLK(CLK), - .RST_N(RST_N), - .core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_12_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_13_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_14_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_15_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_1_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_2_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_3_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_4_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_5_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_6_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_7_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_8_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear), - .core_external_interrupt_sources_9_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear), - .cpu_dmem_master_arready(core$cpu_dmem_master_arready), - .cpu_dmem_master_awready(core$cpu_dmem_master_awready), - .cpu_dmem_master_bid(core$cpu_dmem_master_bid), - .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), - .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata), - .cpu_dmem_master_rid(core$cpu_dmem_master_rid), - .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast), - .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), - .cpu_dmem_master_wready(core$cpu_dmem_master_wready), - .cpu_imem_master_arready(core$cpu_imem_master_arready), - .cpu_imem_master_awready(core$cpu_imem_master_awready), - .cpu_imem_master_bid(core$cpu_imem_master_bid), - .cpu_imem_master_bresp(core$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), - .cpu_imem_master_rdata(core$cpu_imem_master_rdata), - .cpu_imem_master_rid(core$cpu_imem_master_rid), - .cpu_imem_master_rlast(core$cpu_imem_master_rlast), - .cpu_imem_master_rresp(core$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), - .cpu_imem_master_wready(core$cpu_imem_master_wready), - .cpu_reset_server_request_put(core$cpu_reset_server_request_put), - .nmi_req_set_not_clear(core$nmi_req_set_not_clear), - .set_verbosity_logdelay(core$set_verbosity_logdelay), - .set_verbosity_verbosity(core$set_verbosity_verbosity), - .EN_set_verbosity(core$EN_set_verbosity), - .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put), - .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get), - .RDY_set_verbosity(), - .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put), - .cpu_reset_server_response_get(), - .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), - .cpu_imem_master_awid(core$cpu_imem_master_awid), - .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr), - .cpu_imem_master_awlen(core$cpu_imem_master_awlen), - .cpu_imem_master_awsize(core$cpu_imem_master_awsize), - .cpu_imem_master_awburst(core$cpu_imem_master_awburst), - .cpu_imem_master_awlock(core$cpu_imem_master_awlock), - .cpu_imem_master_awcache(core$cpu_imem_master_awcache), - .cpu_imem_master_awprot(core$cpu_imem_master_awprot), - .cpu_imem_master_awqos(core$cpu_imem_master_awqos), - .cpu_imem_master_awregion(core$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), - .cpu_imem_master_wid(core$cpu_imem_master_wid), - .cpu_imem_master_wdata(core$cpu_imem_master_wdata), - .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb), - .cpu_imem_master_wlast(core$cpu_imem_master_wlast), - .cpu_imem_master_bready(core$cpu_imem_master_bready), - .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), - .cpu_imem_master_arid(core$cpu_imem_master_arid), - .cpu_imem_master_araddr(core$cpu_imem_master_araddr), - .cpu_imem_master_arlen(core$cpu_imem_master_arlen), - .cpu_imem_master_arsize(core$cpu_imem_master_arsize), - .cpu_imem_master_arburst(core$cpu_imem_master_arburst), - .cpu_imem_master_arlock(core$cpu_imem_master_arlock), - .cpu_imem_master_arcache(core$cpu_imem_master_arcache), - .cpu_imem_master_arprot(core$cpu_imem_master_arprot), - .cpu_imem_master_arqos(core$cpu_imem_master_arqos), - .cpu_imem_master_arregion(core$cpu_imem_master_arregion), - .cpu_imem_master_rready(core$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), - .cpu_dmem_master_awid(core$cpu_dmem_master_awid), - .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr), - .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen), - .cpu_dmem_master_awsize(core$cpu_dmem_master_awsize), - .cpu_dmem_master_awburst(core$cpu_dmem_master_awburst), - .cpu_dmem_master_awlock(core$cpu_dmem_master_awlock), - .cpu_dmem_master_awcache(core$cpu_dmem_master_awcache), - .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot), - .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos), - .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), - .cpu_dmem_master_wid(core$cpu_dmem_master_wid), - .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata), - .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb), - .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast), - .cpu_dmem_master_bready(core$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), - .cpu_dmem_master_arid(core$cpu_dmem_master_arid), - .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr), - .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen), - .cpu_dmem_master_arsize(core$cpu_dmem_master_arsize), - .cpu_dmem_master_arburst(core$cpu_dmem_master_arburst), - .cpu_dmem_master_arlock(core$cpu_dmem_master_arlock), - .cpu_dmem_master_arcache(core$cpu_dmem_master_arcache), - .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot), - .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos), - .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion), - .cpu_dmem_master_rready(core$cpu_dmem_master_rready)); - - // submodule fabric - mkFabric_AXI4 fabric(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric$v_from_masters_0_wdata), - .v_from_masters_0_wid(fabric$v_from_masters_0_wid), - .v_from_masters_0_wlast(fabric$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric$v_from_masters_1_wdata), - .v_from_masters_1_wid(fabric$v_from_masters_1_wid), - .v_from_masters_1_wlast(fabric$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric$v_to_slaves_2_wready), - .EN_reset(fabric$EN_reset), - .EN_set_verbosity(fabric$EN_set_verbosity), - .RDY_reset(fabric$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric$v_to_slaves_0_wvalid), - .v_to_slaves_0_wid(fabric$v_to_slaves_0_wid), - .v_to_slaves_0_wdata(fabric$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric$v_to_slaves_1_wvalid), - .v_to_slaves_1_wid(fabric$v_to_slaves_1_wid), - .v_to_slaves_1_wdata(fabric$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric$v_to_slaves_2_wvalid), - .v_to_slaves_2_wid(fabric$v_to_slaves_2_wid), - .v_to_slaves_2_wdata(fabric$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric$v_to_slaves_2_rready)); - - // submodule mem0_controller - mkMem_Controller mem0_controller(.CLK(CLK), - .RST_N(RST_N), - .set_addr_map_addr_base(mem0_controller$set_addr_map_addr_base), - .set_addr_map_addr_lim(mem0_controller$set_addr_map_addr_lim), - .set_watch_tohost_tohost_addr(mem0_controller$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(mem0_controller$set_watch_tohost_watch_tohost), - .slave_araddr(mem0_controller$slave_araddr), - .slave_arburst(mem0_controller$slave_arburst), - .slave_arcache(mem0_controller$slave_arcache), - .slave_arid(mem0_controller$slave_arid), - .slave_arlen(mem0_controller$slave_arlen), - .slave_arlock(mem0_controller$slave_arlock), - .slave_arprot(mem0_controller$slave_arprot), - .slave_arqos(mem0_controller$slave_arqos), - .slave_arregion(mem0_controller$slave_arregion), - .slave_arsize(mem0_controller$slave_arsize), - .slave_arvalid(mem0_controller$slave_arvalid), - .slave_awaddr(mem0_controller$slave_awaddr), - .slave_awburst(mem0_controller$slave_awburst), - .slave_awcache(mem0_controller$slave_awcache), - .slave_awid(mem0_controller$slave_awid), - .slave_awlen(mem0_controller$slave_awlen), - .slave_awlock(mem0_controller$slave_awlock), - .slave_awprot(mem0_controller$slave_awprot), - .slave_awqos(mem0_controller$slave_awqos), - .slave_awregion(mem0_controller$slave_awregion), - .slave_awsize(mem0_controller$slave_awsize), - .slave_awvalid(mem0_controller$slave_awvalid), - .slave_bready(mem0_controller$slave_bready), - .slave_rready(mem0_controller$slave_rready), - .slave_wdata(mem0_controller$slave_wdata), - .slave_wid(mem0_controller$slave_wid), - .slave_wlast(mem0_controller$slave_wlast), - .slave_wstrb(mem0_controller$slave_wstrb), - .slave_wvalid(mem0_controller$slave_wvalid), - .to_raw_mem_response_put(mem0_controller$to_raw_mem_response_put), - .EN_server_reset_request_put(mem0_controller$EN_server_reset_request_put), - .EN_server_reset_response_get(mem0_controller$EN_server_reset_response_get), - .EN_set_addr_map(mem0_controller$EN_set_addr_map), - .EN_to_raw_mem_request_get(mem0_controller$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(mem0_controller$EN_to_raw_mem_response_put), - .EN_set_watch_tohost(mem0_controller$EN_set_watch_tohost), - .RDY_server_reset_request_put(mem0_controller$RDY_server_reset_request_put), - .RDY_server_reset_response_get(mem0_controller$RDY_server_reset_response_get), - .RDY_set_addr_map(mem0_controller$RDY_set_addr_map), - .slave_awready(mem0_controller$slave_awready), - .slave_wready(mem0_controller$slave_wready), - .slave_bvalid(mem0_controller$slave_bvalid), - .slave_bid(mem0_controller$slave_bid), - .slave_bresp(mem0_controller$slave_bresp), - .slave_arready(mem0_controller$slave_arready), - .slave_rvalid(mem0_controller$slave_rvalid), - .slave_rid(mem0_controller$slave_rid), - .slave_rdata(mem0_controller$slave_rdata), - .slave_rresp(mem0_controller$slave_rresp), - .slave_rlast(mem0_controller$slave_rlast), - .to_raw_mem_request_get(mem0_controller$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(mem0_controller$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(mem0_controller$RDY_to_raw_mem_response_put), - .status(mem0_controller$status), - .RDY_set_watch_tohost()); - - // submodule mem0_controller_axi4_deburster - mkAXI4_Deburster_A mem0_controller_axi4_deburster(.CLK(CLK), - .RST_N(RST_N), - .from_master_araddr(mem0_controller_axi4_deburster$from_master_araddr), - .from_master_arburst(mem0_controller_axi4_deburster$from_master_arburst), - .from_master_arcache(mem0_controller_axi4_deburster$from_master_arcache), - .from_master_arid(mem0_controller_axi4_deburster$from_master_arid), - .from_master_arlen(mem0_controller_axi4_deburster$from_master_arlen), - .from_master_arlock(mem0_controller_axi4_deburster$from_master_arlock), - .from_master_arprot(mem0_controller_axi4_deburster$from_master_arprot), - .from_master_arqos(mem0_controller_axi4_deburster$from_master_arqos), - .from_master_arregion(mem0_controller_axi4_deburster$from_master_arregion), - .from_master_arsize(mem0_controller_axi4_deburster$from_master_arsize), - .from_master_arvalid(mem0_controller_axi4_deburster$from_master_arvalid), - .from_master_awaddr(mem0_controller_axi4_deburster$from_master_awaddr), - .from_master_awburst(mem0_controller_axi4_deburster$from_master_awburst), - .from_master_awcache(mem0_controller_axi4_deburster$from_master_awcache), - .from_master_awid(mem0_controller_axi4_deburster$from_master_awid), - .from_master_awlen(mem0_controller_axi4_deburster$from_master_awlen), - .from_master_awlock(mem0_controller_axi4_deburster$from_master_awlock), - .from_master_awprot(mem0_controller_axi4_deburster$from_master_awprot), - .from_master_awqos(mem0_controller_axi4_deburster$from_master_awqos), - .from_master_awregion(mem0_controller_axi4_deburster$from_master_awregion), - .from_master_awsize(mem0_controller_axi4_deburster$from_master_awsize), - .from_master_awvalid(mem0_controller_axi4_deburster$from_master_awvalid), - .from_master_bready(mem0_controller_axi4_deburster$from_master_bready), - .from_master_rready(mem0_controller_axi4_deburster$from_master_rready), - .from_master_wdata(mem0_controller_axi4_deburster$from_master_wdata), - .from_master_wid(mem0_controller_axi4_deburster$from_master_wid), - .from_master_wlast(mem0_controller_axi4_deburster$from_master_wlast), - .from_master_wstrb(mem0_controller_axi4_deburster$from_master_wstrb), - .from_master_wvalid(mem0_controller_axi4_deburster$from_master_wvalid), - .to_slave_arready(mem0_controller_axi4_deburster$to_slave_arready), - .to_slave_awready(mem0_controller_axi4_deburster$to_slave_awready), - .to_slave_bid(mem0_controller_axi4_deburster$to_slave_bid), - .to_slave_bresp(mem0_controller_axi4_deburster$to_slave_bresp), - .to_slave_bvalid(mem0_controller_axi4_deburster$to_slave_bvalid), - .to_slave_rdata(mem0_controller_axi4_deburster$to_slave_rdata), - .to_slave_rid(mem0_controller_axi4_deburster$to_slave_rid), - .to_slave_rlast(mem0_controller_axi4_deburster$to_slave_rlast), - .to_slave_rresp(mem0_controller_axi4_deburster$to_slave_rresp), - .to_slave_rvalid(mem0_controller_axi4_deburster$to_slave_rvalid), - .to_slave_wready(mem0_controller_axi4_deburster$to_slave_wready), - .EN_reset(mem0_controller_axi4_deburster$EN_reset), - .RDY_reset(), - .from_master_awready(mem0_controller_axi4_deburster$from_master_awready), - .from_master_wready(mem0_controller_axi4_deburster$from_master_wready), - .from_master_bvalid(mem0_controller_axi4_deburster$from_master_bvalid), - .from_master_bid(mem0_controller_axi4_deburster$from_master_bid), - .from_master_bresp(mem0_controller_axi4_deburster$from_master_bresp), - .from_master_arready(mem0_controller_axi4_deburster$from_master_arready), - .from_master_rvalid(mem0_controller_axi4_deburster$from_master_rvalid), - .from_master_rid(mem0_controller_axi4_deburster$from_master_rid), - .from_master_rdata(mem0_controller_axi4_deburster$from_master_rdata), - .from_master_rresp(mem0_controller_axi4_deburster$from_master_rresp), - .from_master_rlast(mem0_controller_axi4_deburster$from_master_rlast), - .to_slave_awvalid(mem0_controller_axi4_deburster$to_slave_awvalid), - .to_slave_awid(mem0_controller_axi4_deburster$to_slave_awid), - .to_slave_awaddr(mem0_controller_axi4_deburster$to_slave_awaddr), - .to_slave_awlen(mem0_controller_axi4_deburster$to_slave_awlen), - .to_slave_awsize(mem0_controller_axi4_deburster$to_slave_awsize), - .to_slave_awburst(mem0_controller_axi4_deburster$to_slave_awburst), - .to_slave_awlock(mem0_controller_axi4_deburster$to_slave_awlock), - .to_slave_awcache(mem0_controller_axi4_deburster$to_slave_awcache), - .to_slave_awprot(mem0_controller_axi4_deburster$to_slave_awprot), - .to_slave_awqos(mem0_controller_axi4_deburster$to_slave_awqos), - .to_slave_awregion(mem0_controller_axi4_deburster$to_slave_awregion), - .to_slave_wvalid(mem0_controller_axi4_deburster$to_slave_wvalid), - .to_slave_wid(mem0_controller_axi4_deburster$to_slave_wid), - .to_slave_wdata(mem0_controller_axi4_deburster$to_slave_wdata), - .to_slave_wstrb(mem0_controller_axi4_deburster$to_slave_wstrb), - .to_slave_wlast(mem0_controller_axi4_deburster$to_slave_wlast), - .to_slave_bready(mem0_controller_axi4_deburster$to_slave_bready), - .to_slave_arvalid(mem0_controller_axi4_deburster$to_slave_arvalid), - .to_slave_arid(mem0_controller_axi4_deburster$to_slave_arid), - .to_slave_araddr(mem0_controller_axi4_deburster$to_slave_araddr), - .to_slave_arlen(mem0_controller_axi4_deburster$to_slave_arlen), - .to_slave_arsize(mem0_controller_axi4_deburster$to_slave_arsize), - .to_slave_arburst(mem0_controller_axi4_deburster$to_slave_arburst), - .to_slave_arlock(mem0_controller_axi4_deburster$to_slave_arlock), - .to_slave_arcache(mem0_controller_axi4_deburster$to_slave_arcache), - .to_slave_arprot(mem0_controller_axi4_deburster$to_slave_arprot), - .to_slave_arqos(mem0_controller_axi4_deburster$to_slave_arqos), - .to_slave_arregion(mem0_controller_axi4_deburster$to_slave_arregion), - .to_slave_rready(mem0_controller_axi4_deburster$to_slave_rready)); - - // submodule soc_map - mkSoC_Map soc_map(.CLK(CLK), - .RST_N(RST_N), - .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), - .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), - .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_uart0_addr_base(soc_map$m_uart0_addr_base), - .m_uart0_addr_size(), - .m_uart0_addr_lim(soc_map$m_uart0_addr_lim), - .m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim), - .m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base), - .m_mem0_controller_addr_size(), - .m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim), - .m_tcm_addr_base(), - .m_tcm_addr_size(), - .m_tcm_addr_lim(), - .m_is_mem_addr(), - .m_is_IO_addr(), - .m_is_near_mem_IO_addr(), - .m_pc_reset_value(), - .m_mtvec_reset_value(), - .m_nmivec_reset_value()); - - // submodule uart0 - mkUART uart0(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(uart0$put_from_console_put), - .set_addr_map_addr_base(uart0$set_addr_map_addr_base), - .set_addr_map_addr_lim(uart0$set_addr_map_addr_lim), - .slave_araddr(uart0$slave_araddr), - .slave_arburst(uart0$slave_arburst), - .slave_arcache(uart0$slave_arcache), - .slave_arid(uart0$slave_arid), - .slave_arlen(uart0$slave_arlen), - .slave_arlock(uart0$slave_arlock), - .slave_arprot(uart0$slave_arprot), - .slave_arqos(uart0$slave_arqos), - .slave_arregion(uart0$slave_arregion), - .slave_arsize(uart0$slave_arsize), - .slave_arvalid(uart0$slave_arvalid), - .slave_awaddr(uart0$slave_awaddr), - .slave_awburst(uart0$slave_awburst), - .slave_awcache(uart0$slave_awcache), - .slave_awid(uart0$slave_awid), - .slave_awlen(uart0$slave_awlen), - .slave_awlock(uart0$slave_awlock), - .slave_awprot(uart0$slave_awprot), - .slave_awqos(uart0$slave_awqos), - .slave_awregion(uart0$slave_awregion), - .slave_awsize(uart0$slave_awsize), - .slave_awvalid(uart0$slave_awvalid), - .slave_bready(uart0$slave_bready), - .slave_rready(uart0$slave_rready), - .slave_wdata(uart0$slave_wdata), - .slave_wid(uart0$slave_wid), - .slave_wlast(uart0$slave_wlast), - .slave_wstrb(uart0$slave_wstrb), - .slave_wvalid(uart0$slave_wvalid), - .EN_server_reset_request_put(uart0$EN_server_reset_request_put), - .EN_server_reset_response_get(uart0$EN_server_reset_response_get), - .EN_set_addr_map(uart0$EN_set_addr_map), - .EN_get_to_console_get(uart0$EN_get_to_console_get), - .EN_put_from_console_put(uart0$EN_put_from_console_put), - .RDY_server_reset_request_put(uart0$RDY_server_reset_request_put), - .RDY_server_reset_response_get(uart0$RDY_server_reset_response_get), - .RDY_set_addr_map(), - .slave_awready(uart0$slave_awready), - .slave_wready(uart0$slave_wready), - .slave_bvalid(uart0$slave_bvalid), - .slave_bid(uart0$slave_bid), - .slave_bresp(uart0$slave_bresp), - .slave_arready(uart0$slave_arready), - .slave_rvalid(uart0$slave_rvalid), - .slave_rid(uart0$slave_rid), - .slave_rdata(uart0$slave_rdata), - .slave_rresp(uart0$slave_rresp), - .slave_rlast(uart0$slave_rlast), - .get_to_console_get(uart0$get_to_console_get), - .RDY_get_to_console_get(uart0$RDY_get_to_console_get), - .RDY_put_from_console_put(uart0$RDY_put_from_console_put), - .intr(uart0$intr)); - - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_5 - assign CAN_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ; - - // rule RL_rl_wr_data_channel_5 - assign CAN_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_response_channel_5 - assign CAN_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_5 - assign CAN_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ; - - // rule RL_rl_rd_data_channel_5 - assign CAN_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_6 - assign CAN_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ; - - // rule RL_rl_wr_data_channel_6 - assign CAN_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ; - - // rule RL_rl_wr_response_channel_6 - assign CAN_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_6 - assign CAN_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ; - - // rule RL_rl_rd_data_channel_6 - assign CAN_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ; - - // rule RL_rl_connect_external_interrupt_requests - assign CAN_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ; - - // rule RL_rl_reset_start_initial - assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_reset_complete_initial - assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ; - assign WILL_FIRE_RL_rl_reset_complete_initial = - MUX_rg_state$write_1__SEL_2 ; - - // inputs to muxes for submodule ports - assign MUX_rg_state$write_1__SEL_1 = - mem0_controller$RDY_server_reset_request_put && - uart0$RDY_server_reset_request_put && - fabric$RDY_reset && - core$RDY_cpu_reset_server_request_put && - rg_state == 2'd0 ; - assign MUX_rg_state$write_1__SEL_2 = - mem0_controller$RDY_set_addr_map && - mem0_controller$RDY_server_reset_response_get && - uart0$RDY_server_reset_response_get && - core$RDY_cpu_reset_server_response_get && - rg_state == 2'd1 ; - - // register rg_state - assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ; - assign rg_state$EN = - WILL_FIRE_RL_rl_reset_start_initial || - WILL_FIRE_RL_rl_reset_complete_initial ; - - // submodule boot_rom - assign boot_rom$set_addr_map_addr_base = soc_map$m_boot_rom_addr_base ; - assign boot_rom$set_addr_map_addr_lim = soc_map$m_boot_rom_addr_lim ; - assign boot_rom$slave_araddr = boot_rom_axi4_deburster$to_slave_araddr ; - assign boot_rom$slave_arburst = boot_rom_axi4_deburster$to_slave_arburst ; - assign boot_rom$slave_arcache = boot_rom_axi4_deburster$to_slave_arcache ; - assign boot_rom$slave_arid = boot_rom_axi4_deburster$to_slave_arid ; - assign boot_rom$slave_arlen = boot_rom_axi4_deburster$to_slave_arlen ; - assign boot_rom$slave_arlock = boot_rom_axi4_deburster$to_slave_arlock ; - assign boot_rom$slave_arprot = boot_rom_axi4_deburster$to_slave_arprot ; - assign boot_rom$slave_arqos = boot_rom_axi4_deburster$to_slave_arqos ; - assign boot_rom$slave_arregion = boot_rom_axi4_deburster$to_slave_arregion ; - assign boot_rom$slave_arsize = boot_rom_axi4_deburster$to_slave_arsize ; - assign boot_rom$slave_arvalid = boot_rom_axi4_deburster$to_slave_arvalid ; - assign boot_rom$slave_awaddr = boot_rom_axi4_deburster$to_slave_awaddr ; - assign boot_rom$slave_awburst = boot_rom_axi4_deburster$to_slave_awburst ; - assign boot_rom$slave_awcache = boot_rom_axi4_deburster$to_slave_awcache ; - assign boot_rom$slave_awid = boot_rom_axi4_deburster$to_slave_awid ; - assign boot_rom$slave_awlen = boot_rom_axi4_deburster$to_slave_awlen ; - assign boot_rom$slave_awlock = boot_rom_axi4_deburster$to_slave_awlock ; - assign boot_rom$slave_awprot = boot_rom_axi4_deburster$to_slave_awprot ; - assign boot_rom$slave_awqos = boot_rom_axi4_deburster$to_slave_awqos ; - assign boot_rom$slave_awregion = boot_rom_axi4_deburster$to_slave_awregion ; - assign boot_rom$slave_awsize = boot_rom_axi4_deburster$to_slave_awsize ; - assign boot_rom$slave_awvalid = boot_rom_axi4_deburster$to_slave_awvalid ; - assign boot_rom$slave_bready = boot_rom_axi4_deburster$to_slave_bready ; - assign boot_rom$slave_rready = boot_rom_axi4_deburster$to_slave_rready ; - assign boot_rom$slave_wdata = boot_rom_axi4_deburster$to_slave_wdata ; - assign boot_rom$slave_wid = boot_rom_axi4_deburster$to_slave_wid ; - assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ; - assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ; - assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ; - assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - - // submodule boot_rom_axi4_deburster - assign boot_rom_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_0_araddr ; - assign boot_rom_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_0_arburst ; - assign boot_rom_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_0_arcache ; - assign boot_rom_axi4_deburster$from_master_arid = - fabric$v_to_slaves_0_arid ; - assign boot_rom_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_0_arlen ; - assign boot_rom_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_0_arlock ; - assign boot_rom_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_0_arprot ; - assign boot_rom_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_0_arqos ; - assign boot_rom_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_0_arregion ; - assign boot_rom_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_0_arsize ; - assign boot_rom_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_0_arvalid ; - assign boot_rom_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_0_awaddr ; - assign boot_rom_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_0_awburst ; - assign boot_rom_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_0_awcache ; - assign boot_rom_axi4_deburster$from_master_awid = - fabric$v_to_slaves_0_awid ; - assign boot_rom_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_0_awlen ; - assign boot_rom_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_0_awlock ; - assign boot_rom_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_0_awprot ; - assign boot_rom_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_0_awqos ; - assign boot_rom_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_0_awregion ; - assign boot_rom_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_0_awsize ; - assign boot_rom_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_0_awvalid ; - assign boot_rom_axi4_deburster$from_master_bready = - fabric$v_to_slaves_0_bready ; - assign boot_rom_axi4_deburster$from_master_rready = - fabric$v_to_slaves_0_rready ; - assign boot_rom_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_0_wdata ; - assign boot_rom_axi4_deburster$from_master_wid = fabric$v_to_slaves_0_wid ; - assign boot_rom_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_0_wlast ; - assign boot_rom_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_0_wstrb ; - assign boot_rom_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_0_wvalid ; - assign boot_rom_axi4_deburster$to_slave_arready = boot_rom$slave_arready ; - assign boot_rom_axi4_deburster$to_slave_awready = boot_rom$slave_awready ; - assign boot_rom_axi4_deburster$to_slave_bid = boot_rom$slave_bid ; - assign boot_rom_axi4_deburster$to_slave_bresp = boot_rom$slave_bresp ; - assign boot_rom_axi4_deburster$to_slave_bvalid = boot_rom$slave_bvalid ; - assign boot_rom_axi4_deburster$to_slave_rdata = boot_rom$slave_rdata ; - assign boot_rom_axi4_deburster$to_slave_rid = boot_rom$slave_rid ; - assign boot_rom_axi4_deburster$to_slave_rlast = boot_rom$slave_rlast ; - assign boot_rom_axi4_deburster$to_slave_rresp = boot_rom$slave_rresp ; - assign boot_rom_axi4_deburster$to_slave_rvalid = boot_rom$slave_rvalid ; - assign boot_rom_axi4_deburster$to_slave_wready = boot_rom$slave_wready ; - assign boot_rom_axi4_deburster$EN_reset = 1'b0 ; - - // submodule core - assign core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear = - uart0$intr ; - assign core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear = - 1'd0 ; - assign core$cpu_dmem_master_arready = fabric$v_from_masters_1_arready ; - assign core$cpu_dmem_master_awready = fabric$v_from_masters_1_awready ; - assign core$cpu_dmem_master_bid = fabric$v_from_masters_1_bid ; - assign core$cpu_dmem_master_bresp = fabric$v_from_masters_1_bresp ; - assign core$cpu_dmem_master_bvalid = fabric$v_from_masters_1_bvalid ; - assign core$cpu_dmem_master_rdata = fabric$v_from_masters_1_rdata ; - assign core$cpu_dmem_master_rid = fabric$v_from_masters_1_rid ; - assign core$cpu_dmem_master_rlast = fabric$v_from_masters_1_rlast ; - assign core$cpu_dmem_master_rresp = fabric$v_from_masters_1_rresp ; - assign core$cpu_dmem_master_rvalid = fabric$v_from_masters_1_rvalid ; - assign core$cpu_dmem_master_wready = fabric$v_from_masters_1_wready ; - assign core$cpu_imem_master_arready = fabric$v_from_masters_0_arready ; - assign core$cpu_imem_master_awready = fabric$v_from_masters_0_awready ; - assign core$cpu_imem_master_bid = fabric$v_from_masters_0_bid ; - assign core$cpu_imem_master_bresp = fabric$v_from_masters_0_bresp ; - assign core$cpu_imem_master_bvalid = fabric$v_from_masters_0_bvalid ; - assign core$cpu_imem_master_rdata = fabric$v_from_masters_0_rdata ; - assign core$cpu_imem_master_rid = fabric$v_from_masters_0_rid ; - assign core$cpu_imem_master_rlast = fabric$v_from_masters_0_rlast ; - assign core$cpu_imem_master_rresp = fabric$v_from_masters_0_rresp ; - assign core$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ; - assign core$cpu_imem_master_wready = fabric$v_from_masters_0_wready ; - assign core$cpu_reset_server_request_put = 1'd1 ; - assign core$nmi_req_set_not_clear = 1'd0 ; - assign core$set_verbosity_logdelay = set_verbosity_logdelay ; - assign core$set_verbosity_verbosity = set_verbosity_verbosity ; - assign core$EN_set_verbosity = EN_set_verbosity ; - assign core$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ; - assign core$EN_cpu_reset_server_response_get = MUX_rg_state$write_1__SEL_2 ; - - // submodule fabric - assign fabric$set_verbosity_verbosity = 4'h0 ; - assign fabric$v_from_masters_0_araddr = core$cpu_imem_master_araddr ; - assign fabric$v_from_masters_0_arburst = core$cpu_imem_master_arburst ; - assign fabric$v_from_masters_0_arcache = core$cpu_imem_master_arcache ; - assign fabric$v_from_masters_0_arid = core$cpu_imem_master_arid ; - assign fabric$v_from_masters_0_arlen = core$cpu_imem_master_arlen ; - assign fabric$v_from_masters_0_arlock = core$cpu_imem_master_arlock ; - assign fabric$v_from_masters_0_arprot = core$cpu_imem_master_arprot ; - assign fabric$v_from_masters_0_arqos = core$cpu_imem_master_arqos ; - assign fabric$v_from_masters_0_arregion = core$cpu_imem_master_arregion ; - assign fabric$v_from_masters_0_arsize = core$cpu_imem_master_arsize ; - assign fabric$v_from_masters_0_arvalid = core$cpu_imem_master_arvalid ; - assign fabric$v_from_masters_0_awaddr = core$cpu_imem_master_awaddr ; - assign fabric$v_from_masters_0_awburst = core$cpu_imem_master_awburst ; - assign fabric$v_from_masters_0_awcache = core$cpu_imem_master_awcache ; - assign fabric$v_from_masters_0_awid = core$cpu_imem_master_awid ; - assign fabric$v_from_masters_0_awlen = core$cpu_imem_master_awlen ; - assign fabric$v_from_masters_0_awlock = core$cpu_imem_master_awlock ; - assign fabric$v_from_masters_0_awprot = core$cpu_imem_master_awprot ; - assign fabric$v_from_masters_0_awqos = core$cpu_imem_master_awqos ; - assign fabric$v_from_masters_0_awregion = core$cpu_imem_master_awregion ; - assign fabric$v_from_masters_0_awsize = core$cpu_imem_master_awsize ; - assign fabric$v_from_masters_0_awvalid = core$cpu_imem_master_awvalid ; - assign fabric$v_from_masters_0_bready = core$cpu_imem_master_bready ; - assign fabric$v_from_masters_0_rready = core$cpu_imem_master_rready ; - assign fabric$v_from_masters_0_wdata = core$cpu_imem_master_wdata ; - assign fabric$v_from_masters_0_wid = core$cpu_imem_master_wid ; - assign fabric$v_from_masters_0_wlast = core$cpu_imem_master_wlast ; - assign fabric$v_from_masters_0_wstrb = core$cpu_imem_master_wstrb ; - assign fabric$v_from_masters_0_wvalid = core$cpu_imem_master_wvalid ; - assign fabric$v_from_masters_1_araddr = core$cpu_dmem_master_araddr ; - assign fabric$v_from_masters_1_arburst = core$cpu_dmem_master_arburst ; - assign fabric$v_from_masters_1_arcache = core$cpu_dmem_master_arcache ; - assign fabric$v_from_masters_1_arid = core$cpu_dmem_master_arid ; - assign fabric$v_from_masters_1_arlen = core$cpu_dmem_master_arlen ; - assign fabric$v_from_masters_1_arlock = core$cpu_dmem_master_arlock ; - assign fabric$v_from_masters_1_arprot = core$cpu_dmem_master_arprot ; - assign fabric$v_from_masters_1_arqos = core$cpu_dmem_master_arqos ; - assign fabric$v_from_masters_1_arregion = core$cpu_dmem_master_arregion ; - assign fabric$v_from_masters_1_arsize = core$cpu_dmem_master_arsize ; - assign fabric$v_from_masters_1_arvalid = core$cpu_dmem_master_arvalid ; - assign fabric$v_from_masters_1_awaddr = core$cpu_dmem_master_awaddr ; - assign fabric$v_from_masters_1_awburst = core$cpu_dmem_master_awburst ; - assign fabric$v_from_masters_1_awcache = core$cpu_dmem_master_awcache ; - assign fabric$v_from_masters_1_awid = core$cpu_dmem_master_awid ; - assign fabric$v_from_masters_1_awlen = core$cpu_dmem_master_awlen ; - assign fabric$v_from_masters_1_awlock = core$cpu_dmem_master_awlock ; - assign fabric$v_from_masters_1_awprot = core$cpu_dmem_master_awprot ; - assign fabric$v_from_masters_1_awqos = core$cpu_dmem_master_awqos ; - assign fabric$v_from_masters_1_awregion = core$cpu_dmem_master_awregion ; - assign fabric$v_from_masters_1_awsize = core$cpu_dmem_master_awsize ; - assign fabric$v_from_masters_1_awvalid = core$cpu_dmem_master_awvalid ; - assign fabric$v_from_masters_1_bready = core$cpu_dmem_master_bready ; - assign fabric$v_from_masters_1_rready = core$cpu_dmem_master_rready ; - assign fabric$v_from_masters_1_wdata = core$cpu_dmem_master_wdata ; - assign fabric$v_from_masters_1_wid = core$cpu_dmem_master_wid ; - assign fabric$v_from_masters_1_wlast = core$cpu_dmem_master_wlast ; - assign fabric$v_from_masters_1_wstrb = core$cpu_dmem_master_wstrb ; - assign fabric$v_from_masters_1_wvalid = core$cpu_dmem_master_wvalid ; - assign fabric$v_to_slaves_0_arready = - boot_rom_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_0_awready = - boot_rom_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_0_bid = boot_rom_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_0_bresp = - boot_rom_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_0_bvalid = - boot_rom_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_0_rdata = - boot_rom_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_0_rid = boot_rom_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_0_rlast = - boot_rom_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_0_rresp = - boot_rom_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_0_rvalid = - boot_rom_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_0_wready = - boot_rom_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_1_arready = - mem0_controller_axi4_deburster$from_master_arready ; - assign fabric$v_to_slaves_1_awready = - mem0_controller_axi4_deburster$from_master_awready ; - assign fabric$v_to_slaves_1_bid = - mem0_controller_axi4_deburster$from_master_bid ; - assign fabric$v_to_slaves_1_bresp = - mem0_controller_axi4_deburster$from_master_bresp ; - assign fabric$v_to_slaves_1_bvalid = - mem0_controller_axi4_deburster$from_master_bvalid ; - assign fabric$v_to_slaves_1_rdata = - mem0_controller_axi4_deburster$from_master_rdata ; - assign fabric$v_to_slaves_1_rid = - mem0_controller_axi4_deburster$from_master_rid ; - assign fabric$v_to_slaves_1_rlast = - mem0_controller_axi4_deburster$from_master_rlast ; - assign fabric$v_to_slaves_1_rresp = - mem0_controller_axi4_deburster$from_master_rresp ; - assign fabric$v_to_slaves_1_rvalid = - mem0_controller_axi4_deburster$from_master_rvalid ; - assign fabric$v_to_slaves_1_wready = - mem0_controller_axi4_deburster$from_master_wready ; - assign fabric$v_to_slaves_2_arready = uart0$slave_arready ; - assign fabric$v_to_slaves_2_awready = uart0$slave_awready ; - assign fabric$v_to_slaves_2_bid = uart0$slave_bid ; - assign fabric$v_to_slaves_2_bresp = uart0$slave_bresp ; - assign fabric$v_to_slaves_2_bvalid = uart0$slave_bvalid ; - assign fabric$v_to_slaves_2_rdata = uart0$slave_rdata ; - assign fabric$v_to_slaves_2_rid = uart0$slave_rid ; - assign fabric$v_to_slaves_2_rlast = uart0$slave_rlast ; - assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ; - assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ; - assign fabric$v_to_slaves_2_wready = uart0$slave_wready ; - assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ; - assign fabric$EN_set_verbosity = 1'b0 ; - - // submodule mem0_controller - assign mem0_controller$set_addr_map_addr_base = - soc_map$m_mem0_controller_addr_base ; - assign mem0_controller$set_addr_map_addr_lim = - soc_map$m_mem0_controller_addr_lim ; - assign mem0_controller$set_watch_tohost_tohost_addr = - set_watch_tohost_tohost_addr ; - assign mem0_controller$set_watch_tohost_watch_tohost = - set_watch_tohost_watch_tohost ; - assign mem0_controller$slave_araddr = - mem0_controller_axi4_deburster$to_slave_araddr ; - assign mem0_controller$slave_arburst = - mem0_controller_axi4_deburster$to_slave_arburst ; - assign mem0_controller$slave_arcache = - mem0_controller_axi4_deburster$to_slave_arcache ; - assign mem0_controller$slave_arid = - mem0_controller_axi4_deburster$to_slave_arid ; - assign mem0_controller$slave_arlen = - mem0_controller_axi4_deburster$to_slave_arlen ; - assign mem0_controller$slave_arlock = - mem0_controller_axi4_deburster$to_slave_arlock ; - assign mem0_controller$slave_arprot = - mem0_controller_axi4_deburster$to_slave_arprot ; - assign mem0_controller$slave_arqos = - mem0_controller_axi4_deburster$to_slave_arqos ; - assign mem0_controller$slave_arregion = - mem0_controller_axi4_deburster$to_slave_arregion ; - assign mem0_controller$slave_arsize = - mem0_controller_axi4_deburster$to_slave_arsize ; - assign mem0_controller$slave_arvalid = - mem0_controller_axi4_deburster$to_slave_arvalid ; - assign mem0_controller$slave_awaddr = - mem0_controller_axi4_deburster$to_slave_awaddr ; - assign mem0_controller$slave_awburst = - mem0_controller_axi4_deburster$to_slave_awburst ; - assign mem0_controller$slave_awcache = - mem0_controller_axi4_deburster$to_slave_awcache ; - assign mem0_controller$slave_awid = - mem0_controller_axi4_deburster$to_slave_awid ; - assign mem0_controller$slave_awlen = - mem0_controller_axi4_deburster$to_slave_awlen ; - assign mem0_controller$slave_awlock = - mem0_controller_axi4_deburster$to_slave_awlock ; - assign mem0_controller$slave_awprot = - mem0_controller_axi4_deburster$to_slave_awprot ; - assign mem0_controller$slave_awqos = - mem0_controller_axi4_deburster$to_slave_awqos ; - assign mem0_controller$slave_awregion = - mem0_controller_axi4_deburster$to_slave_awregion ; - assign mem0_controller$slave_awsize = - mem0_controller_axi4_deburster$to_slave_awsize ; - assign mem0_controller$slave_awvalid = - mem0_controller_axi4_deburster$to_slave_awvalid ; - assign mem0_controller$slave_bready = - mem0_controller_axi4_deburster$to_slave_bready ; - assign mem0_controller$slave_rready = - mem0_controller_axi4_deburster$to_slave_rready ; - assign mem0_controller$slave_wdata = - mem0_controller_axi4_deburster$to_slave_wdata ; - assign mem0_controller$slave_wid = - mem0_controller_axi4_deburster$to_slave_wid ; - assign mem0_controller$slave_wlast = - mem0_controller_axi4_deburster$to_slave_wlast ; - assign mem0_controller$slave_wstrb = - mem0_controller_axi4_deburster$to_slave_wstrb ; - assign mem0_controller$slave_wvalid = - mem0_controller_axi4_deburster$to_slave_wvalid ; - assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ; - assign mem0_controller$EN_server_reset_request_put = - MUX_rg_state$write_1__SEL_1 ; - assign mem0_controller$EN_server_reset_response_get = - MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign mem0_controller$EN_to_raw_mem_request_get = - EN_to_raw_mem_request_get ; - assign mem0_controller$EN_to_raw_mem_response_put = - EN_to_raw_mem_response_put ; - assign mem0_controller$EN_set_watch_tohost = EN_set_watch_tohost ; - - // submodule mem0_controller_axi4_deburster - assign mem0_controller_axi4_deburster$from_master_araddr = - fabric$v_to_slaves_1_araddr ; - assign mem0_controller_axi4_deburster$from_master_arburst = - fabric$v_to_slaves_1_arburst ; - assign mem0_controller_axi4_deburster$from_master_arcache = - fabric$v_to_slaves_1_arcache ; - assign mem0_controller_axi4_deburster$from_master_arid = - fabric$v_to_slaves_1_arid ; - assign mem0_controller_axi4_deburster$from_master_arlen = - fabric$v_to_slaves_1_arlen ; - assign mem0_controller_axi4_deburster$from_master_arlock = - fabric$v_to_slaves_1_arlock ; - assign mem0_controller_axi4_deburster$from_master_arprot = - fabric$v_to_slaves_1_arprot ; - assign mem0_controller_axi4_deburster$from_master_arqos = - fabric$v_to_slaves_1_arqos ; - assign mem0_controller_axi4_deburster$from_master_arregion = - fabric$v_to_slaves_1_arregion ; - assign mem0_controller_axi4_deburster$from_master_arsize = - fabric$v_to_slaves_1_arsize ; - assign mem0_controller_axi4_deburster$from_master_arvalid = - fabric$v_to_slaves_1_arvalid ; - assign mem0_controller_axi4_deburster$from_master_awaddr = - fabric$v_to_slaves_1_awaddr ; - assign mem0_controller_axi4_deburster$from_master_awburst = - fabric$v_to_slaves_1_awburst ; - assign mem0_controller_axi4_deburster$from_master_awcache = - fabric$v_to_slaves_1_awcache ; - assign mem0_controller_axi4_deburster$from_master_awid = - fabric$v_to_slaves_1_awid ; - assign mem0_controller_axi4_deburster$from_master_awlen = - fabric$v_to_slaves_1_awlen ; - assign mem0_controller_axi4_deburster$from_master_awlock = - fabric$v_to_slaves_1_awlock ; - assign mem0_controller_axi4_deburster$from_master_awprot = - fabric$v_to_slaves_1_awprot ; - assign mem0_controller_axi4_deburster$from_master_awqos = - fabric$v_to_slaves_1_awqos ; - assign mem0_controller_axi4_deburster$from_master_awregion = - fabric$v_to_slaves_1_awregion ; - assign mem0_controller_axi4_deburster$from_master_awsize = - fabric$v_to_slaves_1_awsize ; - assign mem0_controller_axi4_deburster$from_master_awvalid = - fabric$v_to_slaves_1_awvalid ; - assign mem0_controller_axi4_deburster$from_master_bready = - fabric$v_to_slaves_1_bready ; - assign mem0_controller_axi4_deburster$from_master_rready = - fabric$v_to_slaves_1_rready ; - assign mem0_controller_axi4_deburster$from_master_wdata = - fabric$v_to_slaves_1_wdata ; - assign mem0_controller_axi4_deburster$from_master_wid = - fabric$v_to_slaves_1_wid ; - assign mem0_controller_axi4_deburster$from_master_wlast = - fabric$v_to_slaves_1_wlast ; - assign mem0_controller_axi4_deburster$from_master_wstrb = - fabric$v_to_slaves_1_wstrb ; - assign mem0_controller_axi4_deburster$from_master_wvalid = - fabric$v_to_slaves_1_wvalid ; - assign mem0_controller_axi4_deburster$to_slave_arready = - mem0_controller$slave_arready ; - assign mem0_controller_axi4_deburster$to_slave_awready = - mem0_controller$slave_awready ; - assign mem0_controller_axi4_deburster$to_slave_bid = - mem0_controller$slave_bid ; - assign mem0_controller_axi4_deburster$to_slave_bresp = - mem0_controller$slave_bresp ; - assign mem0_controller_axi4_deburster$to_slave_bvalid = - mem0_controller$slave_bvalid ; - assign mem0_controller_axi4_deburster$to_slave_rdata = - mem0_controller$slave_rdata ; - assign mem0_controller_axi4_deburster$to_slave_rid = - mem0_controller$slave_rid ; - assign mem0_controller_axi4_deburster$to_slave_rlast = - mem0_controller$slave_rlast ; - assign mem0_controller_axi4_deburster$to_slave_rresp = - mem0_controller$slave_rresp ; - assign mem0_controller_axi4_deburster$to_slave_rvalid = - mem0_controller$slave_rvalid ; - assign mem0_controller_axi4_deburster$to_slave_wready = - mem0_controller$slave_wready ; - assign mem0_controller_axi4_deburster$EN_reset = 1'b0 ; - - // submodule soc_map - assign soc_map$m_is_IO_addr_addr = 64'h0 ; - assign soc_map$m_is_mem_addr_addr = 64'h0 ; - assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; - - // submodule uart0 - assign uart0$put_from_console_put = put_from_console_put ; - assign uart0$set_addr_map_addr_base = soc_map$m_uart0_addr_base ; - assign uart0$set_addr_map_addr_lim = soc_map$m_uart0_addr_lim ; - assign uart0$slave_araddr = fabric$v_to_slaves_2_araddr ; - assign uart0$slave_arburst = fabric$v_to_slaves_2_arburst ; - assign uart0$slave_arcache = fabric$v_to_slaves_2_arcache ; - assign uart0$slave_arid = fabric$v_to_slaves_2_arid ; - assign uart0$slave_arlen = fabric$v_to_slaves_2_arlen ; - assign uart0$slave_arlock = fabric$v_to_slaves_2_arlock ; - assign uart0$slave_arprot = fabric$v_to_slaves_2_arprot ; - assign uart0$slave_arqos = fabric$v_to_slaves_2_arqos ; - assign uart0$slave_arregion = fabric$v_to_slaves_2_arregion ; - assign uart0$slave_arsize = fabric$v_to_slaves_2_arsize ; - assign uart0$slave_arvalid = fabric$v_to_slaves_2_arvalid ; - assign uart0$slave_awaddr = fabric$v_to_slaves_2_awaddr ; - assign uart0$slave_awburst = fabric$v_to_slaves_2_awburst ; - assign uart0$slave_awcache = fabric$v_to_slaves_2_awcache ; - assign uart0$slave_awid = fabric$v_to_slaves_2_awid ; - assign uart0$slave_awlen = fabric$v_to_slaves_2_awlen ; - assign uart0$slave_awlock = fabric$v_to_slaves_2_awlock ; - assign uart0$slave_awprot = fabric$v_to_slaves_2_awprot ; - assign uart0$slave_awqos = fabric$v_to_slaves_2_awqos ; - assign uart0$slave_awregion = fabric$v_to_slaves_2_awregion ; - assign uart0$slave_awsize = fabric$v_to_slaves_2_awsize ; - assign uart0$slave_awvalid = fabric$v_to_slaves_2_awvalid ; - assign uart0$slave_bready = fabric$v_to_slaves_2_bready ; - assign uart0$slave_rready = fabric$v_to_slaves_2_rready ; - assign uart0$slave_wdata = fabric$v_to_slaves_2_wdata ; - assign uart0$slave_wid = fabric$v_to_slaves_2_wid ; - assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ; - assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ; - assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ; - assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ; - assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ; - assign uart0$EN_get_to_console_get = EN_get_to_console_get ; - assign uart0$EN_put_from_console_put = EN_put_from_console_put ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_state = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - begin - v__h11286 = $stime; - #0; - end - v__h11280 = v__h11286 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start_initial) - $display("%0d:%m.rl_reset_start_initial ...", v__h11280); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - begin - v__h11556 = $stime; - #0; - end - v__h11550 = v__h11556 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_complete_initial) - $display("%0d:%m.rl_reset_complete_initial", v__h11550); - end - // synopsys translate_on -endmodule // mkSoC_Top - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v deleted file mode 100644 index 470d28c6..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkTop_HW_Side.v +++ /dev/null @@ -1,328 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// CLK I 1 clock -// RST_N I 1 reset -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTop_HW_Side(CLK, - RST_N); - input CLK; - input RST_N; - - // register rg_banner_printed - reg rg_banner_printed; - wire rg_banner_printed$D_IN, rg_banner_printed$EN; - - // register rg_console_in_poll - reg [11 : 0] rg_console_in_poll; - wire [11 : 0] rg_console_in_poll$D_IN; - wire rg_console_in_poll$EN; - - // ports of submodule mem_model - wire [352 : 0] mem_model$mem_server_request_put; - wire [255 : 0] mem_model$mem_server_response_get; - wire mem_model$EN_mem_server_request_put, - mem_model$EN_mem_server_response_get, - mem_model$RDY_mem_server_request_put, - mem_model$RDY_mem_server_response_get; - - // ports of submodule soc_top - wire [352 : 0] soc_top$to_raw_mem_request_get; - wire [255 : 0] soc_top$to_raw_mem_response_put; - wire [63 : 0] soc_top$set_verbosity_logdelay, - soc_top$set_watch_tohost_tohost_addr; - wire [7 : 0] soc_top$get_to_console_get, - soc_top$put_from_console_put, - soc_top$status; - wire [3 : 0] soc_top$set_verbosity_verbosity; - wire soc_top$EN_get_to_console_get, - soc_top$EN_put_from_console_put, - soc_top$EN_set_verbosity, - soc_top$EN_set_watch_tohost, - soc_top$EN_to_raw_mem_request_get, - soc_top$EN_to_raw_mem_response_put, - soc_top$RDY_get_to_console_get, - soc_top$RDY_put_from_console_put, - soc_top$RDY_to_raw_mem_request_get, - soc_top$RDY_to_raw_mem_response_put, - soc_top$set_watch_tohost_watch_tohost; - - // rule scheduling signals - wire CAN_FIRE_RL_memCnx_ClientServerRequest, - CAN_FIRE_RL_memCnx_ClientServerResponse, - CAN_FIRE_RL_rl_relay_console_in, - CAN_FIRE_RL_rl_relay_console_out, - CAN_FIRE_RL_rl_step0, - CAN_FIRE_RL_rl_terminate, - WILL_FIRE_RL_memCnx_ClientServerRequest, - WILL_FIRE_RL_memCnx_ClientServerResponse, - WILL_FIRE_RL_rl_relay_console_in, - WILL_FIRE_RL_rl_relay_console_out, - WILL_FIRE_RL_rl_step0, - WILL_FIRE_RL_rl_terminate; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h702; - reg [31 : 0] v__h743; - reg TASK_testplusargs___d12; - reg TASK_testplusargs___d11; - reg TASK_testplusargs___d15; - reg [63 : 0] tohost_addr__h571; - reg [31 : 0] v__h633; - reg [7 : 0] v__h941; - reg [31 : 0] v__h627; - reg [31 : 0] v__h737; - reg [31 : 0] v__h696; - // synopsys translate_on - - // submodule mem_model - mkMem_Model mem_model(.CLK(CLK), - .RST_N(RST_N), - .mem_server_request_put(mem_model$mem_server_request_put), - .EN_mem_server_request_put(mem_model$EN_mem_server_request_put), - .EN_mem_server_response_get(mem_model$EN_mem_server_response_get), - .RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put), - .mem_server_response_get(mem_model$mem_server_response_get), - .RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get)); - - // submodule soc_top - mkSoC_Top soc_top(.CLK(CLK), - .RST_N(RST_N), - .put_from_console_put(soc_top$put_from_console_put), - .set_verbosity_logdelay(soc_top$set_verbosity_logdelay), - .set_verbosity_verbosity(soc_top$set_verbosity_verbosity), - .set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr), - .set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost), - .to_raw_mem_response_put(soc_top$to_raw_mem_response_put), - .EN_set_verbosity(soc_top$EN_set_verbosity), - .EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get), - .EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put), - .EN_get_to_console_get(soc_top$EN_get_to_console_get), - .EN_put_from_console_put(soc_top$EN_put_from_console_put), - .EN_set_watch_tohost(soc_top$EN_set_watch_tohost), - .RDY_set_verbosity(), - .to_raw_mem_request_get(soc_top$to_raw_mem_request_get), - .RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get), - .RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put), - .get_to_console_get(soc_top$get_to_console_get), - .RDY_get_to_console_get(soc_top$RDY_get_to_console_get), - .RDY_put_from_console_put(soc_top$RDY_put_from_console_put), - .status(soc_top$status), - .RDY_set_watch_tohost()); - - // rule RL_rl_terminate - assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ; - assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ; - - // rule RL_rl_step0 - assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ; - assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ; - - // rule RL_rl_relay_console_out - assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ; - - // rule RL_rl_relay_console_in - assign CAN_FIRE_RL_rl_relay_console_in = - rg_console_in_poll != 12'd0 || soc_top$RDY_put_from_console_put ; - assign WILL_FIRE_RL_rl_relay_console_in = CAN_FIRE_RL_rl_relay_console_in ; - - // rule RL_memCnx_ClientServerRequest - assign CAN_FIRE_RL_memCnx_ClientServerRequest = - soc_top$RDY_to_raw_mem_request_get && - mem_model$RDY_mem_server_request_put ; - assign WILL_FIRE_RL_memCnx_ClientServerRequest = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - - // rule RL_memCnx_ClientServerResponse - assign CAN_FIRE_RL_memCnx_ClientServerResponse = - soc_top$RDY_to_raw_mem_response_put && - mem_model$RDY_mem_server_response_get ; - assign WILL_FIRE_RL_memCnx_ClientServerResponse = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // register rg_banner_printed - assign rg_banner_printed$D_IN = 1'd1 ; - assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ; - - // register rg_console_in_poll - assign rg_console_in_poll$D_IN = rg_console_in_poll + 12'd1 ; - assign rg_console_in_poll$EN = CAN_FIRE_RL_rl_relay_console_in ; - - // submodule mem_model - assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ; - assign mem_model$EN_mem_server_request_put = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign mem_model$EN_mem_server_response_get = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - - // submodule soc_top - assign soc_top$put_from_console_put = v__h941 ; - assign soc_top$set_verbosity_logdelay = 64'd0 ; - assign soc_top$set_verbosity_verbosity = - TASK_testplusargs___d11 ? - 4'd2 : - (TASK_testplusargs___d12 ? 4'd1 : 4'd0) ; - assign soc_top$set_watch_tohost_tohost_addr = tohost_addr__h571 ; - assign soc_top$set_watch_tohost_watch_tohost = TASK_testplusargs___d15 ; - assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ; - assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ; - assign soc_top$EN_to_raw_mem_request_get = - CAN_FIRE_RL_memCnx_ClientServerRequest ; - assign soc_top$EN_to_raw_mem_response_put = - CAN_FIRE_RL_memCnx_ClientServerResponse ; - assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ; - assign soc_top$EN_put_from_console_put = - WILL_FIRE_RL_rl_relay_console_in && - rg_console_in_poll == 12'd0 && - v__h941 != 8'd0 ; - assign soc_top$EN_set_watch_tohost = CAN_FIRE_RL_rl_step0 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0; - rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY 12'd0; - end - else - begin - if (rg_banner_printed$EN) - rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN; - if (rg_console_in_poll$EN) - rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY rg_console_in_poll$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - rg_banner_printed = 1'h0; - rg_console_in_poll = 12'hAAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h702 = $stime; - #0; - end - v__h696 = v__h702 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $display("%0d: %m:.rl_terminate: soc_top status is 0x%0h (= 0d%0d)", - v__h696, - soc_top$status, - soc_top$status); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - begin - v__h743 = $stime; - #0; - end - v__h737 = v__h743 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) - $imported_c_end_timing({ 32'd0, v__h737 }); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_terminate) $finish(32'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Bluespec RISC-V standalone system simulation v1.2"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved."); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("================================================================"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d12 = $test$plusargs("v1"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d11 = $test$plusargs("v2"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - TASK_testplusargs___d15 = $test$plusargs("tohost"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - tohost_addr__h571 = $imported_c_get_symbol_val("tohost"); - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - $display("INFO: watch_tohost = %0d, tohost_addr = 0x%0h", - TASK_testplusargs___d15, - tohost_addr__h571); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) - begin - v__h633 = $stime; - #0; - end - v__h627 = v__h633 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_step0) $imported_c_start_timing({ 32'd0, v__h627 }); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) - $write("%c", soc_top$get_to_console_get); - if (RST_N != `BSV_RESET_VALUE) - if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_relay_console_in && rg_console_in_poll == 12'd0) - begin - v__h941 = $imported_c_trygetchar(8'hAA); - #0; - end - end - // synopsys translate_on -endmodule // mkTop_HW_Side - diff --git a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkUART.v b/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkUART.v deleted file mode 100644 index 033775ea..00000000 --- a/builds/RV64ACIMU_Piccolo_verilator/Verilog_RTL/mkUART.v +++ /dev/null @@ -1,2925 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// get_to_console_get O 8 reg -// RDY_get_to_console_get O 1 reg -// RDY_put_from_console_put O 1 reg -// intr O 1 -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wid I 4 reg -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg -// slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg -// slave_rready I 1 -// put_from_console_put I 8 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_put_from_console_put I 1 -// EN_get_to_console_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkUART(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - slave_awvalid, - slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion, - - slave_awready, - - slave_wvalid, - slave_wid, - slave_wdata, - slave_wstrb, - slave_wlast, - - slave_wready, - - slave_bvalid, - - slave_bid, - - slave_bresp, - - slave_bready, - - slave_arvalid, - slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion, - - slave_arready, - - slave_rvalid, - - slave_rid, - - slave_rdata, - - slave_rresp, - - slave_rlast, - - slave_rready, - - EN_get_to_console_get, - get_to_console_get, - RDY_get_to_console_get, - - put_from_console_put, - EN_put_from_console_put, - RDY_put_from_console_put, - - intr); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method slave_m_awvalid - input slave_awvalid; - input [3 : 0] slave_awid; - input [63 : 0] slave_awaddr; - input [7 : 0] slave_awlen; - input [2 : 0] slave_awsize; - input [1 : 0] slave_awburst; - input slave_awlock; - input [3 : 0] slave_awcache; - input [2 : 0] slave_awprot; - input [3 : 0] slave_awqos; - input [3 : 0] slave_awregion; - - // value method slave_m_awready - output slave_awready; - - // action method slave_m_wvalid - input slave_wvalid; - input [3 : 0] slave_wid; - input [63 : 0] slave_wdata; - input [7 : 0] slave_wstrb; - input slave_wlast; - - // value method slave_m_wready - output slave_wready; - - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid - output [3 : 0] slave_bid; - - // value method slave_m_bresp - output [1 : 0] slave_bresp; - - // value method slave_m_buser - - // action method slave_m_bready - input slave_bready; - - // action method slave_m_arvalid - input slave_arvalid; - input [3 : 0] slave_arid; - input [63 : 0] slave_araddr; - input [7 : 0] slave_arlen; - input [2 : 0] slave_arsize; - input [1 : 0] slave_arburst; - input slave_arlock; - input [3 : 0] slave_arcache; - input [2 : 0] slave_arprot; - input [3 : 0] slave_arqos; - input [3 : 0] slave_arregion; - - // value method slave_m_arready - output slave_arready; - - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid - output [3 : 0] slave_rid; - - // value method slave_m_rdata - output [63 : 0] slave_rdata; - - // value method slave_m_rresp - output [1 : 0] slave_rresp; - - // value method slave_m_rlast - output slave_rlast; - - // value method slave_m_ruser - - // action method slave_m_rready - input slave_rready; - - // actionvalue method get_to_console_get - input EN_get_to_console_get; - output [7 : 0] get_to_console_get; - output RDY_get_to_console_get; - - // action method put_from_console_put - input [7 : 0] put_from_console_put; - input EN_put_from_console_put; - output RDY_put_from_console_put; - - // value method intr - output intr; - - // signals for module outputs - wire [63 : 0] slave_rdata; - wire [7 : 0] get_to_console_get; - wire [3 : 0] slave_bid, slave_rid; - wire [1 : 0] slave_bresp, slave_rresp; - wire RDY_get_to_console_get, - RDY_put_from_console_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_set_addr_map, - intr, - slave_arready, - slave_awready, - slave_bvalid, - slave_rlast, - slave_rvalid, - slave_wready; - - // register cfg_verbosity - reg [7 : 0] cfg_verbosity; - wire [7 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_dll - reg [7 : 0] rg_dll; - wire [7 : 0] rg_dll$D_IN; - wire rg_dll$EN; - - // register rg_dlm - reg [7 : 0] rg_dlm; - wire [7 : 0] rg_dlm$D_IN; - wire rg_dlm$EN; - - // register rg_fcr - reg [7 : 0] rg_fcr; - wire [7 : 0] rg_fcr$D_IN; - wire rg_fcr$EN; - - // register rg_ier - reg [7 : 0] rg_ier; - wire [7 : 0] rg_ier$D_IN; - wire rg_ier$EN; - - // register rg_lcr - reg [7 : 0] rg_lcr; - wire [7 : 0] rg_lcr$D_IN; - wire rg_lcr$EN; - - // register rg_lsr - reg [7 : 0] rg_lsr; - reg [7 : 0] rg_lsr$D_IN; - wire rg_lsr$EN; - - // register rg_mcr - reg [7 : 0] rg_mcr; - wire [7 : 0] rg_mcr$D_IN; - wire rg_mcr$EN; - - // register rg_msr - reg [7 : 0] rg_msr; - wire [7 : 0] rg_msr$D_IN; - wire rg_msr$EN; - - // register rg_rbr - reg [7 : 0] rg_rbr; - wire [7 : 0] rg_rbr$D_IN; - wire rg_rbr$EN; - - // register rg_scr - reg [7 : 0] rg_scr; - wire [7 : 0] rg_scr$D_IN; - wire rg_scr$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // register rg_thr - reg [7 : 0] rg_thr; - wire [7 : 0] rg_thr$D_IN; - wire rg_thr$EN; - - // ports of submodule f_from_console - wire [7 : 0] f_from_console$D_IN, f_from_console$D_OUT; - wire f_from_console$CLR, - f_from_console$DEQ, - f_from_console$EMPTY_N, - f_from_console$ENQ, - f_from_console$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_to_console - wire [7 : 0] f_to_console$D_IN, f_to_console$D_OUT; - wire f_to_console$CLR, - f_to_console$DEQ, - f_to_console$EMPTY_N, - f_to_console$ENQ, - f_to_console$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_receive, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_get_to_console_get, - CAN_FIRE_put_from_console_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_set_addr_map, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_receive, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_get_to_console_get, - WILL_FIRE_put_from_console_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_set_addr_map, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid; - - // inputs to muxes for submodule ports - wire [7 : 0] MUX_rg_lsr$write_1__VAL_3; - wire MUX_rg_lsr$write_1__SEL_3; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h2519; - reg [31 : 0] v__h2187; - reg [31 : 0] v__h2025; - reg [31 : 0] v__h2898; - reg [31 : 0] v__h3244; - reg [31 : 0] v__h4006; - reg [31 : 0] v__h3449; - reg [31 : 0] v__h4306; - reg [31 : 0] v__h4749; - reg [31 : 0] v__h4859; - reg [31 : 0] v__h1811; - reg [31 : 0] v__h1805; - reg [31 : 0] v__h2019; - reg [31 : 0] v__h2181; - reg [31 : 0] v__h2513; - reg [31 : 0] v__h2892; - reg [31 : 0] v__h3238; - reg [31 : 0] v__h3443; - reg [31 : 0] v__h4000; - reg [31 : 0] v__h4300; - reg [31 : 0] v__h4743; - reg [31 : 0] v__h4853; - // synopsys translate_on - - // remaining internal signals - reg [7 : 0] y_avValue_snd__h2683; - wire [63 : 0] rdata__h2759, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133; - wire [7 : 0] fn_iir__h1356, - new_lsr__h4516, - x__h2797, - y_avValue_snd__h2696, - y_avValue_snd__h2709, - y_avValue_snd__h2724, - y_avValue_snd__h2738; - wire [1 : 0] rdr_rresp__h2792, - v__h3147, - v__h3395, - v__h3575, - y_avValue_fst__h2737, - y_avValue_fst__h2751; - wire NOT_cfg_verbosity_read_ULE_1_24___d125, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231, - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242, - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185, - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188, - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; - - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; - - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; - - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; - - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; - - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; - - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; - - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; - - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; - - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; - - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; - - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; - - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; - - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; - - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; - - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; - - // actionvalue method get_to_console_get - assign get_to_console_get = f_to_console$D_OUT ; - assign RDY_get_to_console_get = f_to_console$EMPTY_N ; - assign CAN_FIRE_get_to_console_get = f_to_console$EMPTY_N ; - assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ; - - // action method put_from_console_put - assign RDY_put_from_console_put = f_from_console$FULL_N ; - assign CAN_FIRE_put_from_console_put = f_from_console$FULL_N ; - assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ; - - // value method intr - assign intr = !fn_iir__h1356[0] ; - - // submodule f_from_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_from_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_from_console$D_IN), - .ENQ(f_from_console$ENQ), - .DEQ(f_from_console$DEQ), - .CLR(f_from_console$CLR), - .D_OUT(f_from_console$D_OUT), - .FULL_N(f_from_console$FULL_N), - .EMPTY_N(f_from_console$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_to_console - FIFO2 #(.width(32'd8), .guarded(32'd1)) f_to_console(.RST(RST_N), - .CLK(CLK), - .D_IN(f_to_console$D_IN), - .ENQ(f_to_console$ENQ), - .DEQ(f_to_console$DEQ), - .CLR(f_to_console$CLR), - .D_OUT(f_to_console$D_OUT), - .FULL_N(f_to_console$FULL_N), - .EMPTY_N(f_to_console$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && - rg_state ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 && - rg_state ; - assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ; - - // rule RL_rl_receive - assign CAN_FIRE_RL_rl_receive = f_from_console$EMPTY_N && !rg_lsr[0] ; - assign WILL_FIRE_RL_rl_receive = - CAN_FIRE_RL_rl_receive && !WILL_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // inputs to muxes for submodule ports - assign MUX_rg_lsr$write_1__SEL_3 = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 ; - assign MUX_rg_lsr$write_1__VAL_3 = { rg_lsr[7:1], 1'd0 } ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 8'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_dll - assign rg_dll$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dll$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 || - WILL_FIRE_RL_rl_reset ; - - // register rg_dlm - assign rg_dlm$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_dlm$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 || - WILL_FIRE_RL_rl_reset ; - - // register rg_fcr - assign rg_fcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_fcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h2 || - WILL_FIRE_RL_rl_reset ; - - // register rg_ier - assign rg_ier$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_ier$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lcr - assign rg_lcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_lcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h3 || - WILL_FIRE_RL_rl_reset ; - - // register rg_lsr - always@(WILL_FIRE_RL_rl_reset or - WILL_FIRE_RL_rl_receive or - new_lsr__h4516 or - MUX_rg_lsr$write_1__SEL_3 or MUX_rg_lsr$write_1__VAL_3) - case (1'b1) - WILL_FIRE_RL_rl_reset: rg_lsr$D_IN = 8'd96; - WILL_FIRE_RL_rl_receive: rg_lsr$D_IN = new_lsr__h4516; - MUX_rg_lsr$write_1__SEL_3: rg_lsr$D_IN = MUX_rg_lsr$write_1__VAL_3; - default: rg_lsr$D_IN = 8'b10101010 /* unspecified value */ ; - endcase - assign rg_lsr$EN = - WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 || - WILL_FIRE_RL_rl_receive || - WILL_FIRE_RL_rl_reset ; - - // register rg_mcr - assign rg_mcr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_mcr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h4 || - WILL_FIRE_RL_rl_reset ; - - // register rg_msr - assign rg_msr$D_IN = 8'd0 ; - assign rg_msr$EN = CAN_FIRE_RL_rl_reset ; - - // register rg_rbr - assign rg_rbr$D_IN = f_from_console$D_OUT ; - assign rg_rbr$EN = WILL_FIRE_RL_rl_receive ; - - // register rg_scr - assign rg_scr$D_IN = - WILL_FIRE_RL_rl_reset ? - 8'd0 : - slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_scr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h7 || - WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = 1'd1 ; - assign rg_state$EN = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // register rg_thr - assign rg_thr$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign rg_thr$EN = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - - // submodule f_from_console - assign f_from_console$D_IN = put_from_console_put ; - assign f_from_console$ENQ = EN_put_from_console_put ; - assign f_from_console$DEQ = WILL_FIRE_RL_rl_receive ; - assign f_from_console$CLR = 1'b0 ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_to_console - assign f_to_console$D_IN = slave_xactor_f_wr_data$D_OUT[16:9] ; - assign f_to_console$ENQ = - WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 ; - assign f_to_console$DEQ = EN_get_to_console_get ; - assign f_to_console$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - rdata__h2759, - rdr_rresp__h2792, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { slave_awid, - slave_awaddr, - slave_awlen, - slave_awsize, - slave_awburst, - slave_awlock, - slave_awcache, - slave_awprot, - slave_awqos, - slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { slave_wid, slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3147 } ; - assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_24___d125 = cfg_verbosity > 8'd1 ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - slave_xactor_f_wr_data$D_OUT[0] ; - assign NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - !rg_lcr[7]) && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h2 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h3 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h4 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h5 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h6 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h7 && - !slave_xactor_f_wr_data$D_OUT[0] ; - assign fn_iir__h1356 = - (rg_ier[0] && rg_lsr[0]) ? 8'h04 : (rg_ier[1] ? 8'h02 : 8'd0) ; - assign new_lsr__h4516 = { rg_lsr[7:1], 1'd1 } ; - assign rdata__h2759 = { 56'd0, x__h2797 } ; - assign rdr_rresp__h2792 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0) ? - y_avValue_fst__h2751 : - 2'b10 ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d29 = - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d177 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d181 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h0 && - rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d185 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - !rg_lcr[7] ; - assign slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d188 = - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] == - 3'h1 && - rg_lcr[7] ; - assign slave_xactor_f_wr_resp_i_notFull__30_AND_NOT_s_ETC___d152 = - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1] || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 || - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7] || - f_to_console$FULL_N) ; - assign v__h3147 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) ? - 2'b10 : - v__h3395 ; - assign v__h3395 = - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0) ? - v__h3575 : - 2'b11 ; - assign v__h3575 = y_avValue_fst__h2737 ; - assign x__h2797 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0 || - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) ? - 8'd0 : - y_avValue_snd__h2738 ; - assign y_avValue_fst__h2737 = 2'b0 ; - assign y_avValue_fst__h2751 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] == - 2'd0) ? - y_avValue_fst__h2737 : - 2'b11 ; - assign y_avValue_snd__h2696 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - rg_lcr[7]) ? - rg_dlm : - y_avValue_snd__h2683 ; - assign y_avValue_snd__h2709 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h1 && - !rg_lcr[7]) ? - rg_ier : - y_avValue_snd__h2696 ; - assign y_avValue_snd__h2724 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - rg_lcr[7]) ? - rg_dll : - y_avValue_snd__h2709 ; - assign y_avValue_snd__h2738 = - (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3] == - 3'h0 && - !rg_lcr[7]) ? - rg_rbr : - y_avValue_snd__h2724 ; - always@(slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17 or - fn_iir__h1356 or rg_lcr or rg_mcr or rg_lsr or rg_msr or rg_scr) - begin - case (slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[5:3]) - 3'h2: y_avValue_snd__h2683 = fn_iir__h1356; - 3'h3: y_avValue_snd__h2683 = rg_lcr; - 3'h4: y_avValue_snd__h2683 = rg_mcr; - 3'h5: y_avValue_snd__h2683 = rg_lsr; - 3'h6: y_avValue_snd__h2683 = rg_msr; - 3'h7: y_avValue_snd__h2683 = rg_scr; - default: y_avValue_snd__h2683 = 8'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dll <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_dlm <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_fcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_ier <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_lsr <= `BSV_ASSIGNMENT_DELAY 8'd96; - rg_mcr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_msr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_scr <= `BSV_ASSIGNMENT_DELAY 8'd0; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (rg_dll$EN) rg_dll <= `BSV_ASSIGNMENT_DELAY rg_dll$D_IN; - if (rg_dlm$EN) rg_dlm <= `BSV_ASSIGNMENT_DELAY rg_dlm$D_IN; - if (rg_fcr$EN) rg_fcr <= `BSV_ASSIGNMENT_DELAY rg_fcr$D_IN; - if (rg_ier$EN) rg_ier <= `BSV_ASSIGNMENT_DELAY rg_ier$D_IN; - if (rg_lcr$EN) rg_lcr <= `BSV_ASSIGNMENT_DELAY rg_lcr$D_IN; - if (rg_lsr$EN) rg_lsr <= `BSV_ASSIGNMENT_DELAY rg_lsr$D_IN; - if (rg_mcr$EN) rg_mcr <= `BSV_ASSIGNMENT_DELAY rg_mcr$D_IN; - if (rg_msr$EN) rg_msr <= `BSV_ASSIGNMENT_DELAY rg_msr$D_IN; - if (rg_scr$EN) rg_scr <= `BSV_ASSIGNMENT_DELAY rg_scr$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_rbr$EN) rg_rbr <= `BSV_ASSIGNMENT_DELAY rg_rbr$D_IN; - if (rg_thr$EN) rg_thr <= `BSV_ASSIGNMENT_DELAY rg_thr$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 8'hAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_dll = 8'hAA; - rg_dlm = 8'hAA; - rg_fcr = 8'hAA; - rg_ier = 8'hAA; - rg_lcr = 8'hAA; - rg_lsr = 8'hAA; - rg_mcr = 8'hAA; - rg_msr = 8'hAA; - rg_rbr = 8'hAA; - rg_scr = 8'hAA; - rg_state = 1'h0; - rg_thr = 8'hAA; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - begin - v__h2519 = $stime; - #0; - end - v__h2513 = v__h2519 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2513); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - begin - v__h2187 = $stime; - #0; - end - v__h2181 = v__h2187 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", - v__h2181); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] == - 3'd0 && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - begin - v__h2025 = $stime; - #0; - end - v__h2019 = v__h2025 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $display("%0d: ERROR: UART.rl_process_rd_req: misaligned addr", - v__h2019); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__4_BITS_92_TO_29__ETC___d17[2:0] != - 3'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h2898 = $stime; - #0; - end - v__h2892 = v__h2898 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_rd_req", v__h2892); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdata__h2759); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", rdr_rresp__h2792); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - begin - v__h3244 = $stime; - #0; - end - v__h3238 = v__h3244 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $display("%0d: ERROR: UART.rl_process_wr_req: misaligned addr", - v__h3238); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1]) && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] != - 3'd0 || - !slave_xactor_f_wr_data$D_OUT[1])) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - begin - v__h4006 = $stime; - #0; - end - v__h4000 = v__h4006 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h4000); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d231) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] == - 2'd0 && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h0 || - !rg_lcr[7]) && - (slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[5:3] != - 3'h1 || - rg_lcr[7]) && - NOT_slave_xactor_f_wr_addr_first__31_BITS_92_T_ETC___d242) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - 1'b0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - begin - v__h3449 = $stime; - #0; - end - v__h3443 = v__h3449 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $display("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", - v__h3443); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[2:0] == - 3'd0 && - slave_xactor_f_wr_data$D_OUT[1] && - slave_xactor_f_wr_addr_first__31_BITS_92_TO_29_ETC___d133[7:6] != - 2'd0) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - begin - v__h4306 = $stime; - #0; - end - v__h4300 = v__h4306 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("%0d: UART.rl_process_wr_req", v__h4300); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - slave_xactor_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125 && - !slave_xactor_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", v__h3147); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_24___d125) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - begin - v__h4749 = $stime; - #0; - end - v__h4743 = v__h4749 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_base 0x%0h is not 8-Byte-aligned", - v__h4743, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - begin - v__h4859 = $stime; - #0; - end - v__h4853 = v__h4859 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0) - $display("%0d: WARNING: UART.set_addr_map: addr_lim 0x%0h is not 8-Byte-aligned", - v__h4853, - set_addr_map_addr_lim); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_receive && NOT_cfg_verbosity_read_ULE_1_24___d125) - $display("UART_Model.rl_receive: received char 0x%0h; new_lsr = 0x%0h", - f_from_console$D_OUT, - new_lsr__h4516); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - begin - v__h1811 = $stime; - #0; - end - v__h1805 = v__h1811 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 8'd0) - $display("%0d: UART.rl_reset", v__h1805); - end - // synopsys translate_on -endmodule // mkUART - diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk index 2dc5a3ee..054c57b2 100644 --- a/builds/Resources/Include_Common.mk +++ b/builds/Resources/Include_Common.mk @@ -36,9 +36,15 @@ all: compile simulator CORE_DIRS = $(REPO)/src_Core/CPU:$(REPO)/src_Core/ISA:$(REPO)/src_Core/RegFiles:$(REPO)/src_Core/Core:$(REPO)/src_Core/Near_Mem_VM:$(REPO)/src_Core/PLIC:$(REPO)/src_Core/Near_Mem_IO:$(REPO)/src_Core/Debug_Module:$(REPO)/src_Core/BSV_Additional_Libs -TESTBENCH_DIRS = $(REPO)/src_Testbench/Top:$(REPO)/src_Testbench/SoC:$(REPO)/src_Testbench/Fabrics/AXI4 +TESTBENCH_DIRS = $(REPO)/src_Testbench/Top:$(REPO)/src_Testbench/SoC -BSC_PATH = $(CUSTOM_DIRS):$(CORE_DIRS):$(TESTBENCH_DIRS):+ +# XXX +# Specify the path to the BlueStuff library (https://github.com/CTSRD-CHERI/BlueStuff) +# What is the best way to distribute this code? currently lives in $(REPO)/libs as a git submodule +# XXX +AXI_DIRS = $(REPO)/libs/BlueStuff/AXI:$(REPO)/libs/BlueStuff/BlueBasics:$(REPO)/libs/BlueStuff/ + +BSC_PATH = $(AXI_DIRS):$(CUSTOM_DIRS):$(CORE_DIRS):$(TESTBENCH_DIRS):+ # ---------------- # Top-level file and module @@ -49,8 +55,15 @@ TOPMODULE ?= mkTop_HW_Side # ================================================================ # bsc compilation flags +# XXX +# Using '-no-show-timestamps' with +# Bluespec Compiler, version 2017.07.A (build 1da80f1, 2017-07-21) +# results in +# Error: Command line: (S0008) +# Unrecognized flag: -no-show-timestamps +# XXX BSC_COMPILATION_FLAGS += \ - -keep-fires -aggressive-conditions -no-warn-action-shadowing -no-show-timestamps -check-assert \ + -keep-fires -aggressive-conditions -no-warn-action-shadowing -check-assert \ -suppress-warnings G0020 \ +RTS -K128M -RTS -show-range-conflict diff --git a/libs/BlueStuff b/libs/BlueStuff new file mode 160000 index 00000000..2c9cae29 --- /dev/null +++ b/libs/BlueStuff @@ -0,0 +1 @@ +Subproject commit 2c9cae299d9410b8e9ce3783a7480118284a5048 diff --git a/src_Core/CPU/CPU.bsv b/src_Core/CPU/CPU.bsv index d24ae36b..37dd3659 100644 --- a/src_Core/CPU/CPU.bsv +++ b/src_Core/CPU/CPU.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package CPU; // ================================================================ @@ -32,12 +45,11 @@ import ConfigReg :: *; import GetPut_Aux :: *; import Semi_FIFOF :: *; +import AXI4 :: *; // ================================================================ // Project imports -import AXI4_Types :: *; - import ISA_Decls :: *; import TV_Info :: *; diff --git a/src_Core/CPU/CPU_IFC.bsv b/src_Core/CPU/CPU_IFC.bsv index 0867322a..45fb6971 100644 --- a/src_Core/CPU/CPU_IFC.bsv +++ b/src_Core/CPU/CPU_IFC.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package CPU_IFC; // ================================================================ @@ -7,6 +20,7 @@ package CPU_IFC; import GetPut :: *; import ClientServer :: *; +import AXI4 :: *; // ================================================================ // Project imports @@ -24,6 +38,8 @@ import DM_CPU_Req_Rsp :: *; import TV_Info :: *; `endif +import Fabric_Defs :: *; + // ================================================================ // CPU interface @@ -35,10 +51,14 @@ interface CPU_IFC; // SoC fabric connections // IMem to Fabric master interface - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) imem_master; + interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) imem_master; // DMem to Fabric master interface - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) dmem_master; + interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) dmem_master; // ---------------- // External interrupts diff --git a/src_Core/Core/Core.bsv b/src_Core/Core/Core.bsv index f13b2792..48078067 100644 --- a/src_Core/Core/Core.bsv +++ b/src_Core/Core/Core.bsv @@ -1,16 +1,27 @@ // Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved. +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package Core; // ================================================================ // This package defines: // Core_IFC // mkCore #(Core_IFC) -// mkFabric_2x3 -- specialized AXI4 fabric used inside this core // // mkCore instantiates: // - mkCPU (the RISC-V CPU) -// - mkFabric_2x3 // - mkNear_Mem_IO_AXI4 // - mkPLIC_16_2_7 // - mkTV_Encode (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF) @@ -31,14 +42,14 @@ import Connectable :: *; import Cur_Cycle :: *; import GetPut_Aux :: *; +import Routable :: *; +import AXI4 :: *; // ================================================================ // Project imports // Main fabric -import AXI4_Types :: *; -import AXI4_Fabric :: *; -import Fabric_Defs :: *; // for Wd_Id, Wd_Addr, Wd_Data, Wd_User +import Fabric_Defs :: *; // for Wd_Id, Wd_Addr, Wd_Data... import SoC_Map :: *; `ifdef INCLUDE_GDB_CONTROL @@ -79,8 +90,8 @@ module mkCore (Core_IFC #(N_External_Interrupt_Sources)); // The CPU CPU_IFC cpu <- mkCPU; - // A 2x3 fabric for connecting {CPU, Debug_Module} to {Fabric, Near_Mem_IO, PLIC} - Fabric_2x3_IFC fabric_2x3 <- mkFabric_2x3; + // AXI4 shim for the default slave + let shim <- mkAXI4ShimUGSizedFIFOF4; // Near_Mem_IO Near_Mem_IO_AXI4_IFC near_mem_io <- mkNear_Mem_IO_AXI4; @@ -125,7 +136,6 @@ module mkCore (Core_IFC #(N_External_Interrupt_Sources)); cpu.hart0_server_reset.request.put (running); // CPU near_mem_io.server_reset.request.put (?); // Near_Mem_IO plic.server_reset.request.put (?); // PLIC - fabric_2x3.reset; // Local 2x3 Fabric `ifdef INCLUDE_GDB_CONTROL // Remember the requestor, so we can respond to it @@ -142,7 +152,6 @@ module mkCore (Core_IFC #(N_External_Interrupt_Sources)); cpu.hart0_server_reset.request.put (running); // CPU near_mem_io.server_reset.request.put (?); // Near_Mem_IO plic.server_reset.request.put (?); // PLIC - fabric_2x3.reset; // Local 2x3 fabric // Remember the requestor, so we can respond to it f_reset_requestor.enq (reset_requestor_dm); @@ -155,11 +164,11 @@ module mkCore (Core_IFC #(N_External_Interrupt_Sources)); let rsp2 <- near_mem_io.server_reset.response.get; // Near_Mem_IO let rsp3 <- plic.server_reset.response.get; // PLIC - near_mem_io.set_addr_map (zeroExtend (soc_map.m_near_mem_io_addr_base), - zeroExtend (soc_map.m_near_mem_io_addr_lim)); + near_mem_io.set_addr_map (rangeBase(soc_map.m_near_mem_io_addr_range), + rangeTop(soc_map.m_near_mem_io_addr_range)); - plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_base), - zeroExtend (soc_map.m_plic_addr_lim)); + plic.set_addr_map (rangeBase(soc_map.m_plic_addr_range), + rangeTop(soc_map.m_plic_addr_range)); Bit #(1) requestor = reset_requestor_soc; `ifdef INCLUDE_GDB_CONTROL @@ -287,8 +296,7 @@ module mkCore (Core_IFC #(N_External_Interrupt_Sources)); // BEGIN SECTION: no GDB // No DM, so 'DM bus master' is dummy - AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) - dm_master_local = dummy_AXI4_Master_ifc; + let dm_master_local = culDeSac; `ifdef INCLUDE_TANDEM_VERIF // ---------------------------------------------------------------- @@ -305,13 +313,37 @@ module mkCore (Core_IFC #(N_External_Interrupt_Sources)); // Connect the local 2x3 fabric // Masters on the local 2x3 fabric - mkConnection (cpu.dmem_master, fabric_2x3.v_from_masters [cpu_dmem_master_num]); - mkConnection (dm_master_local, fabric_2x3.v_from_masters [debug_module_sba_master_num]); + Vector#(Num_Masters_2x3, + AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User)) + master_vector = newVector; + master_vector[cpu_dmem_master_num] = cpu.dmem_master; + master_vector[debug_module_sba_master_num] = dm_master_local; // Slaves on the local 2x3 fabric - // default slave is taken out directly to the Core interface - mkConnection (fabric_2x3.v_to_slaves [near_mem_io_slave_num], near_mem_io.axi4_slave); - mkConnection (fabric_2x3.v_to_slaves [plic_slave_num], plic.axi4_slave); + // default slave is forwarded out directly to the Core interface + Vector#(Num_Slaves_2x3, + AXI4_Slave_Synth #(Wd_SId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User)) + slave_vector = newVector; + slave_vector[default_slave_num] = toAXI4_Slave_Synth(shim.slave); + slave_vector[near_mem_io_slave_num] = near_mem_io.axi4_slave; + slave_vector[plic_slave_num] = plic.axi4_slave; + + function Vector#(Num_Slaves_2x3, Bool) route_2x3 (Bit#(Wd_Addr) addr); + Vector#(Num_Slaves_2x3, Bool) res = replicate(False); + if (inRange(soc_map.m_near_mem_io_addr_range, addr)) + res[near_mem_io_slave_num] = True; + else if (inRange(soc_map.m_plic_addr_range, addr)) + res[plic_slave_num] = True; + else + res[default_slave_num] = True; + return res; + endfunction + + mkAXI4Bus_Synth (route_2x3, master_vector, slave_vector); // ================================================================ // Connect interrupt lines from near_mem_io and PLIC to CPU @@ -358,10 +390,10 @@ module mkCore (Core_IFC #(N_External_Interrupt_Sources)); // AXI4 Fabric interfaces // IMem to Fabric master interface - interface AXI4_Master_IFC cpu_imem_master = cpu.imem_master; + interface cpu_imem_master = cpu.imem_master; // DMem to Fabric master interface - interface AXI4_Master_IFC cpu_dmem_master = fabric_2x3.v_to_slaves [default_slave_num]; + interface cpu_dmem_master = toAXI4_Master_Synth(shim.master); // ---------------------------------------------------------------- // External interrupt sources @@ -412,65 +444,16 @@ endmodule: mkCore // ---------------- // Fabric port numbers for masters -typedef 2 Num_Masters_2x3; - -typedef Bit #(TLog #(Num_Masters_2x3)) Master_Num_2x3; - Master_Num_2x3 cpu_dmem_master_num = 0; Master_Num_2x3 debug_module_sba_master_num = 1; // ---------------- // Fabric port numbers for slaves -typedef 3 Num_Slaves_2x3; - -typedef Bit #(TLog #(Num_Slaves_2x3)) Slave_Num_2x3; - Slave_Num_2x3 default_slave_num = 0; Slave_Num_2x3 near_mem_io_slave_num = 1; Slave_Num_2x3 plic_slave_num = 2; -// ---------------- -// Specialization of parameterized AXI4 fabric for 2x3 Core fabric - -typedef AXI4_Fabric_IFC #(Num_Masters_2x3, - Num_Slaves_2x3, - Wd_Id, - Wd_Addr, - Wd_Data, - Wd_User) Fabric_2x3_IFC; - -// ---------------- - -(* synthesize *) -module mkFabric_2x3 (Fabric_2x3_IFC); - - // System address map - SoC_Map_IFC soc_map <- mkSoC_Map; - - // ---------------- - // Slave address decoder - // Any addr is legal, and there is only one slave to service it. - - function Tuple2 #(Bool, Slave_Num_2x3) fn_addr_to_slave_num_2x3 (Fabric_Addr addr); - if ( (soc_map.m_near_mem_io_addr_base <= addr) - && (addr < soc_map.m_near_mem_io_addr_lim)) - return tuple2 (True, near_mem_io_slave_num); - - else if ( (soc_map.m_plic_addr_base <= addr) - && (addr < soc_map.m_plic_addr_lim)) - return tuple2 (True, plic_slave_num); - - else - return tuple2 (True, default_slave_num); - endfunction - - AXI4_Fabric_IFC #(Num_Masters_2x3, Num_Slaves_2x3, Wd_Id, Wd_Addr, Wd_Data, Wd_User) - fabric <- mkAXI4_Fabric (fn_addr_to_slave_num_2x3); - - return fabric; -endmodule: mkFabric_2x3 - // ================================================================ endpackage diff --git a/src_Core/Core/Core_IFC.bsv b/src_Core/Core/Core_IFC.bsv index 6839ee02..5a049b69 100644 --- a/src_Core/Core/Core_IFC.bsv +++ b/src_Core/Core/Core_IFC.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved. +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package Core_IFC; // ================================================================ @@ -19,11 +32,14 @@ import Vector :: *; import GetPut :: *; import ClientServer :: *; +// ---------------- +// BSV additional libs +import AXI4 :: *; + // ================================================================ // Project imports // Main fabric -import AXI4_Types :: *; import Fabric_Defs :: *; // External interrupt request interface @@ -57,10 +73,14 @@ interface Core_IFC #(numeric type t_n_interrupt_sources); // AXI4 Fabric interfaces // CPU IMem to Fabric master interface - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) cpu_imem_master; + interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) cpu_imem_master; // CPU DMem to Fabric master interface - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) cpu_dmem_master; + interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) cpu_dmem_master; // ---------------------------------------------------------------- // External interrupt sources diff --git a/src_Core/Core/Fabric_Defs.bsv b/src_Core/Core/Fabric_Defs.bsv index fd366a49..f6b5873b 100644 --- a/src_Core/Core/Fabric_Defs.bsv +++ b/src_Core/Core/Fabric_Defs.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package Fabric_Defs; // ================================================================ @@ -19,18 +32,25 @@ package Fabric_Defs; // None -// ================================================================ -// Project imports +// ---------------- +// BSV additional libs -import AXI4_Types :: *; +import AXI4 :: *; // ================================================================ -// Fabric parameters +// Core local Fabric parameters + +typedef 2 Num_Masters_2x3; +typedef 3 Num_Slaves_2x3; + +typedef Bit#(TLog #(Num_Masters_2x3)) Master_Num_2x3; +typedef Bit#(TLog #(Num_Slaves_2x3)) Slave_Num_2x3; // ---------------- -// Width of fabric 'id' buses -typedef 4 Wd_Id; -typedef Bit #(Wd_Id) Fabric_Id; +// Width of fabric 'Id' buses +typedef 4 Wd_MId_2x3; +typedef TAdd#(Wd_MId_2x3, TLog#(Num_Masters_2x3)) Wd_SId_2x3; +typedef Wd_SId_2x3 Wd_MId; // ---------------- // Width of fabric 'addr' buses @@ -61,8 +81,11 @@ Integer bytes_per_fabric_data = valueOf (Bytes_per_Fabric_Data); // ---------------- // Width of fabric 'user' datapaths -typedef 0 Wd_User; -typedef Bit #(Wd_User) Fabric_User; +typedef 0 Wd_AW_User; +typedef 0 Wd_W_User; +typedef 0 Wd_B_User; +typedef 0 Wd_AR_User; +typedef 0 Wd_R_User; // ---------------- // Number of zero LSBs in a fabric address aligned to the fabric data width @@ -72,16 +95,20 @@ Integer zlsbs_aligned_fabric_addr = valueOf (ZLSBs_Aligned_Fabric_Addr); // ================================================================ // AXI4 defaults for this project - -Fabric_Id fabric_default_id = 0; -AXI4_Burst fabric_default_burst = axburst_incr; -AXI4_Lock fabric_default_lock = axlock_normal; -AXI4_Cache fabric_default_arcache = arcache_dev_nonbuf; -AXI4_Cache fabric_default_awcache = awcache_dev_nonbuf; -AXI4_Prot fabric_default_prot = { axprot_2_data, axprot_1_secure, axprot_0_unpriv }; -AXI4_QoS fabric_default_qos = 0; -AXI4_Region fabric_default_region = 0; -Fabric_User fabric_default_user = ?; +Bit#(Wd_MId_2x3) fabric_2x3_default_mid = 0; +Bit#(Wd_MId) fabric_default_mid = 0; +AXI4_Burst fabric_default_burst = INCR; +AXI4_Lock fabric_default_lock = NORMAL; +AXI4_Cache fabric_default_arcache = arcache_dev_nonbuf; +AXI4_Cache fabric_default_awcache = awcache_dev_nonbuf; +AXI4_Prot fabric_default_prot = axi4Prot(DATA, SECURE, UNPRIV); +AXI4_QoS fabric_default_qos = 0; +AXI4_Region fabric_default_region = 0; +Bit#(Wd_AW_User) fabric_default_awuser = ?; +Bit#(Wd_W_User) fabric_default_wuser = ?; +Bit#(Wd_B_User) fabric_default_buser = ?; +Bit#(Wd_AR_User) fabric_default_aruser = ?; +Bit#(Wd_R_User) fabric_default_ruser = ?; // ================================================================ diff --git a/src_Core/Core/TV_Taps.bsv b/src_Core/Core/TV_Taps.bsv index dedd50a3..e6e9ec10 100644 --- a/src_Core/Core/TV_Taps.bsv +++ b/src_Core/Core/TV_Taps.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved. +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package TV_Taps; // ================================================================ @@ -25,6 +38,8 @@ import Connectable :: *; import Semi_FIFOF :: *; import GetPut_Aux :: *; +import SourceSink :: *; +import AXI4 :: *; // ================================================================ // Project imports @@ -33,26 +48,29 @@ import ISA_Decls :: *; import DM_CPU_Req_Rsp :: *; import TV_Info :: *; -import AXI4_Types :: *; import Fabric_Defs :: *; // ================================================================ // DM-to-memory tap interface DM_Mem_Tap_IFC; - interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave; - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master; - interface Get #(Trace_Data) trace_data_out; + interface AXI4_Slave_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) slave; + interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) master; + interface Get #(Trace_Data) trace_data_out; endinterface (* synthesize *) module mkDM_Mem_Tap (DM_Mem_Tap_IFC); // Transactor facing DM - AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave_xactor <- mkAXI4_Slave_Xactor; + let slave_xactor <- mkAXI4_Slave_Xactor; // Transactor facing memory bus - AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master_xactor <- mkAXI4_Master_Xactor; + let master_xactor <- mkAXI4_Master_Xactor; // Tap output FIFOF #(Trace_Data) f_trace_data <- mkFIFOF; @@ -62,15 +80,12 @@ module mkDM_Mem_Tap (DM_Mem_Tap_IFC); // Snoop write requests rule write_reqs; - let wr_addr = slave_xactor.o_wr_addr.first; - slave_xactor.o_wr_addr.deq; - - let wr_data = slave_xactor.o_wr_data.first; - slave_xactor.o_wr_data.deq; + let wr_addr <- get(slave_xactor.master.aw); + let wr_data <- get(slave_xactor.master.w); // Pass-through - master_xactor.i_wr_addr.enq (wr_addr); - master_xactor.i_wr_data.enq (wr_data); + master_xactor.slave.aw.put(wr_addr); + master_xactor.slave.w.put(wr_data); // Tap Bit #(64) paddr = ?; @@ -95,17 +110,17 @@ module mkDM_Mem_Tap (DM_Mem_Tap_IFC); endrule // Read requests, write responses and read responses are not snooped - mkConnection (slave_xactor.o_rd_addr, master_xactor.i_rd_addr); - mkConnection (slave_xactor.i_wr_resp, master_xactor.o_wr_resp); - mkConnection (slave_xactor.i_rd_data, master_xactor.o_rd_data); + mkConnection (slave_xactor.master.ar, master_xactor.slave.ar); + mkConnection (slave_xactor.master.b, master_xactor.slave.b); + mkConnection (slave_xactor.master.r, master_xactor.slave.r); // ================================================================ // INTERFACE // Facing DM - interface slave = slave_xactor.axi_side; + interface slave = slave_xactor.slaveSynth; // Facing bus - interface master = master_xactor.axi_side; + interface master = master_xactor.masterSynth; // Tap towards verifier interface Get trace_data_out = toGet (f_trace_data); diff --git a/src_Core/Debug_Module/DM_System_Bus.bsv b/src_Core/Debug_Module/DM_System_Bus.bsv index e60fd38f..698ca32f 100644 --- a/src_Core/Debug_Module/DM_System_Bus.bsv +++ b/src_Core/Debug_Module/DM_System_Bus.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package DM_System_Bus; // ================================================================ @@ -15,6 +28,8 @@ import FIFOF :: *; // Other library imports import Semi_FIFOF :: *; +import SourceSink :: *; +import AXI4 :: *; // ================================================================ // Project Imports @@ -22,7 +37,6 @@ import Semi_FIFOF :: *; import ISA_Decls :: *; import DM_Common :: *; -import AXI4_Types :: *; import Fabric_Defs :: *; // ================================================================ @@ -38,7 +52,9 @@ interface DM_System_Bus_IFC; // ---------------- // Facing System - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master; + interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) master; endinterface // ================================================================ @@ -49,10 +65,10 @@ endinterface function AXI4_Size fn_DM_sbaccess_to_AXI4_Size (DM_sbaccess sbaccess); AXI4_Size axi4_size = case (sbaccess) - DM_SBACCESS_8_BIT: axsize_1; - DM_SBACCESS_16_BIT: axsize_2; - DM_SBACCESS_32_BIT: axsize_4; - DM_SBACCESS_64_BIT: axsize_8; + DM_SBACCESS_8_BIT: 1; + DM_SBACCESS_16_BIT: 2; + DM_SBACCESS_32_BIT: 4; + DM_SBACCESS_64_BIT: 8; endcase; return axi4_size; endfunction @@ -121,27 +137,27 @@ function Tuple4 #(Fabric_Addr, // addr is 32b- or 64b-aligned Bit #(8) strobe64 = 0; Bit #(3) shift_bytes = addr [2:0]; Bit #(6) shift_bits = { shift_bytes, 3'b0 }; - AXI4_Size axsize = axsize_128; // Will be updated in 'case' below + AXI4_Size axsize = 128; // Will be updated in 'case' below case (sbaccess) DM_SBACCESS_8_BIT: begin word64 = (word64 << shift_bits); strobe64 = ('b_1 << shift_bytes); - axsize = axsize_1; + axsize = 1; end DM_SBACCESS_16_BIT: begin word64 = (word64 << shift_bits); strobe64 = ('b_11 << shift_bytes); - axsize = axsize_2; + axsize = 2; end DM_SBACCESS_32_BIT: begin word64 = (word64 << shift_bits); strobe64 = ('b_1111 << shift_bytes); - axsize = axsize_4; + axsize = 4; end DM_SBACCESS_64_BIT: begin strobe64 = 'b_1111_1111; - axsize = axsize_8; + axsize = 8; end endcase @@ -179,7 +195,10 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // ---------------------------------------------------------------- // Interface to memory fabric - AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master_xactor <- mkAXI4_Master_Xactor; + AXI4_Master_Xactor#(Wd_MId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) + master_xactor <- mkAXI4_Master_Xactor; // ---------------------------------------------------------------- // System Bus state @@ -264,18 +283,18 @@ module mkDM_System_Bus (DM_System_Bus_IFC); function Action fa_fabric_send_read_req (Bit #(64) addr64); action Fabric_Addr fabric_addr = truncate (addr64); - let rda = AXI4_Rd_Addr {arid: fabric_default_id, - araddr: fabric_addr, - arlen: 0, // burst len = arlen+1 - arsize: fn_DM_sbaccess_to_AXI4_Size (rg_sbcs_sbaccess), - arburst: fabric_default_burst, - arlock: fabric_default_lock, - arcache: fabric_default_arcache, - arprot: fabric_default_prot, - arqos: fabric_default_qos, - arregion: fabric_default_region, - aruser: fabric_default_user}; - master_xactor.i_rd_addr.enq (rda); + let rda = AXI4_ARFlit {arid: fabric_2x3_default_mid, + araddr: fabric_addr, + arlen: 0, // burst len = arlen+1 + arsize: fn_DM_sbaccess_to_AXI4_Size (rg_sbcs_sbaccess), + arburst: fabric_default_burst, + arlock: fabric_default_lock, + arcache: fabric_default_arcache, + arprot: fabric_default_prot, + arqos: fabric_default_qos, + arregion: fabric_default_region, + aruser: fabric_default_aruser}; + master_xactor.slave.ar.put(rda); // Save read-address for byte-lane extraction from later response // (since rg_sbaddress may be incremented by then). @@ -305,24 +324,24 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // fabric_strb identifies the lanes to be written // awsize is always the fabric width - let wra = AXI4_Wr_Addr {awid: fabric_default_id, - awaddr: fabric_addr, - awlen: 0, // burst len = awlen+1 - awsize: fabric_size, - awburst: fabric_default_burst, - awlock: fabric_default_lock, - awcache: fabric_default_awcache, - awprot: fabric_default_prot, - awqos: fabric_default_qos, - awregion: fabric_default_region, - awuser: fabric_default_user}; - master_xactor.i_wr_addr.enq (wra); - - let wrd = AXI4_Wr_Data {wdata: fabric_data, - wstrb: fabric_strb, - wlast: True, - wuser: fabric_default_user}; - master_xactor.i_wr_data.enq (wrd); + let wra = AXI4_AWFlit {awid: fabric_2x3_default_mid, + awaddr: fabric_addr, + awlen: 0, // burst len = awlen+1 + awsize: fabric_size, + awburst: fabric_default_burst, + awlock: fabric_default_lock, + awcache: fabric_default_awcache, + awprot: fabric_default_prot, + awqos: fabric_default_qos, + awregion: fabric_default_region, + awuser: fabric_default_awuser}; + master_xactor.slave.aw.put(wra); + + let wrd = AXI4_WFlit {wdata: fabric_data, + wstrb: fabric_strb, + wlast: True, + wuser: fabric_default_wuser}; + master_xactor.slave.w.put(wrd); if (verbosity != 0) begin $display (" DM_System_Bus.fa_fabric_send_write_req:"); @@ -488,7 +507,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); (* descending_urgency = "rl_sb_read_finish, write" *) rule rl_sb_read_finish ( (rg_sb_state == SB_READ_FINISH) && (rg_sbcs_sberror == DM_SBERROR_NONE)); - let rdr <- pop_o (master_xactor.o_rd_data); + let rdr <- get(master_xactor.slave.r); if (verbosity != 0) $display ("DM_System_Bus.rule_sb_read_finish: rdr = ", fshow (rdr)); @@ -496,7 +515,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); Bit #(64) rdata64 = zeroExtend (rdr.rdata); Bit #(64) data = fn_extract_and_extend_bytes (rg_sbcs_sbaccess, rg_sbaddress_reading, rdata64); - if (rdr.rresp != axi4_resp_okay) begin + if (rdr.rresp != OKAY) begin $display ("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n"); $display (" rdr = ", fshow (rdr)); rg_sbcs_sberror <= DM_SBERROR_OTHER; @@ -564,8 +583,8 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // Consume write-responses rule rl_sb_write_response; - let wrr <- pop_o (master_xactor.o_wr_resp); - if (wrr.bresp != axi4_resp_okay) + let wrr <- get(master_xactor.slave.b); + if (wrr.bresp != OKAY) rg_sbcs_sberror <= DM_SBERROR_OTHER; endrule @@ -654,7 +673,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // ---------------- // Facing System - interface AXI4_Master_IFC master = master_xactor.axi_side; + interface AXI4_Master_IFC master = master_xactor.masterSynth; endmodule // ================================================================ diff --git a/src_Core/Debug_Module/Debug_Module.bsv b/src_Core/Debug_Module/Debug_Module.bsv index 63484665..02fd7de0 100644 --- a/src_Core/Debug_Module/Debug_Module.bsv +++ b/src_Core/Debug_Module/Debug_Module.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package Debug_Module; // ================================================================ @@ -62,12 +75,12 @@ import SpecialFIFOs :: *; import Semi_FIFOF :: *; import Cur_Cycle :: *; +import AXI4 :: *; // ================================================================ // Project imports import ISA_Decls :: *; -import AXI4_Types :: *; import Fabric_Defs :: *; import DM_Common :: *; @@ -119,7 +132,9 @@ interface Debug_Module_IFC; interface Client #(Bool, Bool) ndm_reset_client; // Read/Write RISC-V memory - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master; + interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) master; endinterface // ================================================================ diff --git a/src_Core/Near_Mem_IO/Near_Mem_IO_AXI4.bsv b/src_Core/Near_Mem_IO/Near_Mem_IO_AXI4.bsv index d8a8b2d6..69893fc1 100644 --- a/src_Core/Near_Mem_IO/Near_Mem_IO_AXI4.bsv +++ b/src_Core/Near_Mem_IO/Near_Mem_IO_AXI4.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package Near_Mem_IO_AXI4; // ================================================================ @@ -56,14 +69,14 @@ import Cur_Cycle :: *; import GetPut_Aux :: *; import Semi_FIFOF :: *; import ByteLane :: *; +import SourceSink :: *; +import AXI4 :: *; // ================================================================ // Project imports // Main fabric -import AXI4_Types :: *; -import AXI4_Fabric :: *; -import Fabric_Defs :: *; // for Wd_Id, Wd_Addr, Wd_Data, Wd_User +import Fabric_Defs :: *; // for Wd_SId_2x3, Wd_Addr, Wd_Data... // ================================================================ // Local constants and types @@ -83,7 +96,9 @@ interface Near_Mem_IO_AXI4_IFC; method Action set_addr_map (Bit #(64) addr_base, Bit #(64) addr_lim); // Memory-mapped access - interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) axi4_slave; + interface AXI4_Slave_Synth #(Wd_SId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) axi4_slave; // Timer interrupt // True/False = set/clear interrupt-pending in CPU's MTIP @@ -97,6 +112,8 @@ endinterface (* synthesize *) module mkNear_Mem_IO_AXI4 (Near_Mem_IO_AXI4_IFC); +// XXX This module seems to assume the following constraints: +// provisos(Add #(Wd_AW_User, 0, Wd_B_User), Add #(Wd_AR_User, 0, Wd_R_User)); // Verbosity: 0: quiet; 1: reset; 2: timer interrupts, all reads and writes Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0); @@ -116,7 +133,7 @@ module mkNear_Mem_IO_AXI4 (Near_Mem_IO_AXI4_IFC); Reg #(Bit #(64)) rg_addr_lim <- mkRegU; // Connector to AXI4 fabric - AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave_xactor <- mkAXI4_Slave_Xactor; + let slave_xactor <- mkAXI4_Slave_Xactor; // ---------------- // Timer registers @@ -146,7 +163,7 @@ module mkNear_Mem_IO_AXI4 (Near_Mem_IO_AXI4_IFC); rule rl_reset (rg_state == MODULE_STATE_START); f_reset_reqs.deq; - slave_xactor.reset; + slave_xactor.clear; f_timer_interrupt_req.clear; f_sw_interrupt_req.clear; @@ -199,7 +216,7 @@ module mkNear_Mem_IO_AXI4 (Near_Mem_IO_AXI4_IFC); rule rl_process_rd_req ( (rg_state == MODULE_STATE_READY) && (! f_reset_reqs.notEmpty)); - let rda <- pop_o (slave_xactor.o_rd_addr); + let rda <- get(slave_xactor.master.ar); if (cfg_verbosity > 1) begin $display ("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", cur_cycle, rg_mtip); $display (" ", fshow (rda)); @@ -207,12 +224,12 @@ module mkNear_Mem_IO_AXI4 (Near_Mem_IO_AXI4_IFC); let byte_addr = rda.araddr - rg_addr_base; Bit #(64) rdata = 0; - AXI4_Resp rresp = axi4_resp_okay; + AXI4_Resp rresp = OKAY; if (rda.araddr < rg_addr_base) begin $display ("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", cur_cycle); $display (" ", fshow (rda)); - rresp = axi4_resp_decerr; + rresp = DECERR; end else if (byte_addr == 'h_0000) @@ -249,21 +266,21 @@ module mkNear_Mem_IO_AXI4 (Near_Mem_IO_AXI4_IFC); end else - rresp = axi4_resp_decerr; + rresp = DECERR; - if (rresp != axi4_resp_okay) begin + if (rresp != OKAY) begin $display ("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", cur_cycle); $display (" ", fshow (rda)); end // Send read-response to bus Fabric_Data x = truncate (rdata); - let rdr = AXI4_Rd_Data {rid: rda.arid, - rdata: x, - rresp: rresp, - rlast: True, - ruser: rda.aruser}; - slave_xactor.i_rd_data.enq (rdr); + let rdr = AXI4_RFlit {rid: rda.arid, + rdata: x, + rresp: rresp, + rlast: True, + ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User + slave_xactor.master.r.put(rdr); if (cfg_verbosity > 1) begin $display ("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", cur_cycle); @@ -278,8 +295,8 @@ module mkNear_Mem_IO_AXI4 (Near_Mem_IO_AXI4_IFC); rule rl_process_wr_req ( (rg_state == MODULE_STATE_READY) && (! f_reset_reqs.notEmpty)); - let wra <- pop_o (slave_xactor.o_wr_addr); - let wrd <- pop_o (slave_xactor.o_wr_data); + let wra <- get(slave_xactor.master.aw); + let wrd <- get(slave_xactor.master.w); if (cfg_verbosity > 1) begin $display ("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", cur_cycle, rg_mtip); $display (" ", fshow (wra)); @@ -291,13 +308,13 @@ module mkNear_Mem_IO_AXI4 (Near_Mem_IO_AXI4_IFC); Bit #(8) data_byte = wdata [7:0]; let byte_addr = wra.awaddr - rg_addr_base; - AXI4_Resp bresp = axi4_resp_okay; + AXI4_Resp bresp = OKAY; if (wra.awaddr < rg_addr_base) begin $display ("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", cur_cycle); $display (" ", fshow (wra)); $display (" ", fshow (wrd)); - bresp = axi4_resp_decerr; + bresp = DECERR; end else if (byte_addr == 'h_0000) begin @@ -390,19 +407,19 @@ module mkNear_Mem_IO_AXI4 (Near_Mem_IO_AXI4_IFC); end else - bresp = axi4_resp_decerr; + bresp = DECERR; - if (bresp != axi4_resp_okay) begin + if (bresp != OKAY) begin $display ("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", cur_cycle); $display (" ", fshow (wra)); $display (" ", fshow (wrd)); end // Send write-response to bus - let wrr = AXI4_Wr_Resp {bid: wra.awid, - bresp: bresp, - buser: wra.awuser}; - slave_xactor.i_wr_resp.enq (wrr); + let wrr = AXI4_BFlit {bid: wra.awid, + bresp: bresp, + buser: wra.awuser}; // XXX This requires that Wd_AW_User == Wd_B_User + slave_xactor.master.b.put(wrr); if (cfg_verbosity > 1) begin $display ("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", cur_cycle); @@ -435,7 +452,7 @@ module mkNear_Mem_IO_AXI4 (Near_Mem_IO_AXI4_IFC); endmethod // Memory-mapped access - interface axi4_slave = slave_xactor.axi_side; + interface axi4_slave = slave_xactor.slaveSynth; // Timer interrupt interface Get get_timer_interrupt_req; diff --git a/src_Core/Near_Mem_VM/MMU_Cache.bsv b/src_Core/Near_Mem_VM/MMU_Cache.bsv index 54e23502..2708a706 100644 --- a/src_Core/Near_Mem_VM/MMU_Cache.bsv +++ b/src_Core/Near_Mem_VM/MMU_Cache.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved. +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + // A combined MMU and L1 Cache for RISC-V. // The MMU is capable of handling pages, superpages and gigapages. // The cache is simple, in-order, blocking, and has a "write-around" policy: @@ -59,6 +72,8 @@ import Cur_Cycle :: *; import GetPut_Aux :: *; import Semi_FIFOF :: *; import CreditCounter :: *; +import AXI4 :: *; +import SourceSink :: *; // ================================================================ // Project imports @@ -77,17 +92,18 @@ import Cache_Decls_RV64 :: *; `endif import SoC_Map :: *; -import AXI4_Types :: *; import Fabric_Defs :: *; // ================================================================ -export MMU_Cache_IFC (..), mkMMU_Cache; +export MMU_Cache_IFC (..); +export MMU_ICache_IFC (..), mkMMU_ICache; +export MMU_DCache_IFC (..), mkMMU_DCache; // ================================================================ // MMU_Cache interface -interface MMU_Cache_IFC; +interface MMU_Cache_IFC#(numeric type mID); method Action set_verbosity (Bit #(4) verbosity); // Reset request/response @@ -123,9 +139,14 @@ interface MMU_Cache_IFC; method Action tlb_flush; // Fabric master interface - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) mem_master; + interface AXI4_Master_Synth #(mID, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) mem_master; endinterface +typedef MMU_Cache_IFC#(Wd_MId_2x3) MMU_DCache_IFC; +typedef MMU_Cache_IFC#(Wd_MId) MMU_ICache_IFC; + // **************************************************************** // **************************************************************** // **************************************************************** @@ -176,8 +197,6 @@ Bool bram_cmd_write = True; typedef enum {REQUESTOR_RESET_IFC, REQUESTOR_FLUSH_IFC} Requestor deriving (Bits, Eq, FShow); -Bit #(Wd_User) dummy_user = ?; // For AXI4 'user' field (here unused) - `ifndef ISA_PRIV_S // VM Xlate related definitions which are only for the case where there is no @@ -213,10 +232,10 @@ endfunction function AXI4_Size fn_funct3_to_AXI4_Size (Bit #(3) funct3); Bit #(2) x = funct3 [1:0]; AXI4_Size result; - if (x == f3_SIZE_B) result = axsize_1; - else if (x == f3_SIZE_H) result = axsize_2; - else if (x == f3_SIZE_W) result = axsize_4; - else /* if (x == f3_SIZE_D) */ result = axsize_8; + if (x == f3_SIZE_B) result = 1; + else if (x == f3_SIZE_H) result = 2; + else if (x == f3_SIZE_W) result = 4; + else /* if (x == f3_SIZE_D) */ result = 8; return result; endfunction @@ -238,27 +257,27 @@ function Tuple4 #(Fabric_Addr, // addr is 32b- or 64b-aligned Bit #(3) shift_bytes = addr [2:0]; Bit #(6) shift_bits = { shift_bytes, 3'b0 }; Bit #(64) addr64 = zeroExtend (addr); - AXI4_Size axsize = axsize_128; // Will be updated in 'case' below + AXI4_Size axsize = 128; // Will be updated in 'case' below case (f3 [1:0]) f3_SIZE_B: begin word64 = (word64 << shift_bits); strobe64 = ('b_1 << shift_bytes); - axsize = axsize_1; + axsize = 1; end f3_SIZE_H: begin word64 = (word64 << shift_bits); strobe64 = ('b_11 << shift_bytes); - axsize = axsize_2; + axsize = 2; end f3_SIZE_W: begin word64 = (word64 << shift_bits); strobe64 = ('b_1111 << shift_bytes); - axsize = axsize_4; + axsize = 4; end f3_SIZE_D: begin strobe64 = 'b_1111_1111; - axsize = axsize_8; + axsize = 8; end endcase @@ -415,7 +434,17 @@ endfunction // The module implementation (* synthesize *) -module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); +module mkMMU_ICache(MMU_ICache_IFC); + let cache <- mkMMU_Cache(False, fabric_default_mid); + return cache; +endmodule +(* synthesize *) +module mkMMU_DCache(MMU_DCache_IFC); + let cache <- mkMMU_Cache(True, fabric_2x3_default_mid); + return cache; +endmodule +module mkMMU_Cache #(parameter Bool dmem_not_imem, + parameter Bit#(mID) default_mid) (MMU_Cache_IFC#(mID)); String d_or_i = (dmem_not_imem ? "D_MMU_Cache" : "I_MMU_Cache"); @@ -435,7 +464,10 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); FIFOF #(Requestor) f_reset_rsps <- mkFIFOF; // Fabric request/response - AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master_xactor <- mkAXI4_Master_Xactor; + AXI4_Master_Xactor#(mID, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) + master_xactor <- mkAXI4_Master_Xactor; `ifdef ISA_PRIV_S // The TLB @@ -655,19 +687,19 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); // Send a read-request into the fabric function Action fa_fabric_send_read_req (Fabric_Addr addr, AXI4_Size size); action - let mem_req_rd_addr = AXI4_Rd_Addr {arid: fabric_default_id, - araddr: addr, - arlen: 0, // burst len = arlen+1 - arsize: size, - arburst: fabric_default_burst, - arlock: fabric_default_lock, - arcache: fabric_default_arcache, - arprot: fabric_default_prot, - arqos: fabric_default_qos, - arregion: fabric_default_region, - aruser: fabric_default_user}; - - master_xactor.i_rd_addr.enq (mem_req_rd_addr); + let mem_req_rd_addr = AXI4_ARFlit {arid: default_mid, + araddr: addr, + arlen: 0, // burst len = arlen+1 + arsize: size, + arburst: fabric_default_burst, + arlock: fabric_default_lock, + arcache: fabric_default_arcache, + arprot: fabric_default_prot, + arqos: fabric_default_qos, + arregion: fabric_default_region, + aruser: fabric_default_aruser}; + + master_xactor.slave.ar.put(mem_req_rd_addr); // Debugging if (cfg_verbosity > 1) begin @@ -680,23 +712,23 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); // 'addr' is already aligned to a cache-line. function Action fa_fabric_send_read_burst_req (Fabric_Addr addr); action - AXI4_Size size = ((bytes_per_fabric_data == 4) ? axsize_4 : axsize_8); + AXI4_Size size = ((bytes_per_fabric_data == 4) ? 4 : 8); // Note: AXI4 codes a burst length of 'n' as 'n-1' AXI4_Len len = fromInteger ((bytes_per_cline / bytes_per_fabric_data) - 1); - let mem_req_rd_addr = AXI4_Rd_Addr {arid: fabric_default_id, - araddr: addr, - arlen: len, - arsize: size, - arburst: axburst_incr, - arlock: fabric_default_lock, - arcache: fabric_default_arcache, - arprot: fabric_default_prot, - arqos: fabric_default_qos, - arregion: fabric_default_region, - aruser: fabric_default_user}; + let mem_req_rd_addr = AXI4_ARFlit {arid: default_mid, + araddr: addr, + arlen: len, + arsize: size, + arburst: INCR, + arlock: fabric_default_lock, + arcache: fabric_default_arcache, + arprot: fabric_default_prot, + arqos: fabric_default_qos, + arregion: fabric_default_region, + aruser: fabric_default_aruser}; - master_xactor.i_rd_addr.enq (mem_req_rd_addr); + master_xactor.slave.ar.put(mem_req_rd_addr); // Debugging if (cfg_verbosity > 1) begin @@ -718,38 +750,38 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); match { .f3, .pa, .st_val } <- pop (f_fabric_write_reqs); match {.fabric_addr, - .fabric_data, - .fabric_strb, - .fabric_size} = fn_to_fabric_write_fields (f3, pa, st_val); - - let mem_req_wr_addr = AXI4_Wr_Addr {awid: fabric_default_id, - awaddr: fabric_addr, - awlen: 0, // burst len = awlen+1 - awsize: fabric_size, - awburst: fabric_default_burst, - awlock: fabric_default_lock, - awcache: fabric_default_awcache, - awprot: fabric_default_prot, - awqos: fabric_default_qos, - awregion: fabric_default_region, - awuser: fabric_default_user}; - - let mem_req_wr_data = AXI4_Wr_Data {wdata: fabric_data, - wstrb: fabric_strb, - wlast: True, - wuser: fabric_default_user}; - - master_xactor.i_wr_addr.enq (mem_req_wr_addr); - master_xactor.i_wr_data.enq (mem_req_wr_data); - - // Expect a fabric response - ctr_wr_rsps_pending.incr; - - // Debugging - if (cfg_verbosity > 1) begin - $display (" To fabric: ", fshow (mem_req_wr_addr)); - $display (" ", fshow (mem_req_wr_data)); - end + .fabric_data, + .fabric_strb, + .fabric_size} = fn_to_fabric_write_fields (f3, pa, st_val); + + let mem_req_wr_addr = AXI4_AWFlit {awid: default_mid, + awaddr: fabric_addr, + awlen: 0, // burst len = awlen+1 + awsize: fabric_size, + awburst: fabric_default_burst, + awlock: fabric_default_lock, + awcache: fabric_default_awcache, + awprot: fabric_default_prot, + awqos: fabric_default_qos, + awregion: fabric_default_region, + awuser: fabric_default_awuser}; + + let mem_req_wr_data = AXI4_WFlit {wdata: fabric_data, + wstrb: fabric_strb, + wlast: True, + wuser: fabric_default_wuser}; + + master_xactor.slave.aw.put(mem_req_wr_addr); + master_xactor.slave.w.put(mem_req_wr_data); + + // Expect a fabric response + ctr_wr_rsps_pending.incr; + + // Debugging + if (cfg_verbosity > 1) begin + $display (" To fabric: ", fshow (mem_req_wr_addr)); + $display (" ", fshow (mem_req_wr_data)); + end endrule // ================================================================ @@ -804,7 +836,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); `endif if (f_reset_reqs.first == REQUESTOR_RESET_IFC) begin - master_xactor.reset; + master_xactor.clear; ctr_wr_rsps_pending.clear; end @@ -1146,7 +1178,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); PA lev_1_pte_pa = satp_pa + vpn_1_pa; PA lev_1_pte_pa_w64 = { lev_1_pte_pa [pa_sz - 1 : 3], 3'b0 }; // 64b-aligned addr Fabric_Addr lev_1_pte_pa_w64_fa = fn_PA_to_Fabric_Addr (lev_1_pte_pa_w64); - fa_fabric_send_read_req (lev_1_pte_pa_w64_fa, axsize_4); + fa_fabric_send_read_req (lev_1_pte_pa_w64_fa, 4); rg_pte_pa <= lev_1_pte_pa; rg_state <= PTW_LEVEL_1; @@ -1161,7 +1193,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); PA lev_2_pte_pa = satp_pa + vpn_2_pa; PA lev_2_pte_pa_w64 = { lev_2_pte_pa [pa_sz - 1 : 3], 3'b0 }; // 64b-aligned addr Fabric_Addr lev_2_pte_pa_w64_fa = fn_PA_to_Fabric_Addr (lev_2_pte_pa_w64); - fa_fabric_send_read_req (lev_2_pte_pa_w64_fa, axsize_8); + fa_fabric_send_read_req (lev_2_pte_pa_w64_fa, 8); rg_pte_pa <= lev_2_pte_pa; rg_state <= PTW_LEVEL_2; @@ -1175,7 +1207,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); `ifdef SV39 rule rl_ptw_level_2 (rg_state == PTW_LEVEL_2); // Memory read-response is a level 1 PTE - let mem_rsp <- pop_o (master_xactor.o_rd_data); + let mem_rsp <- get(master_xactor.slave.r); Bit #(64) x64 = zeroExtend (mem_rsp.rdata); WordXL pte; @@ -1186,7 +1218,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); pte = mem_rsp.rdata; // Bus error - if (mem_rsp.rresp != axi4_resp_okay) begin + if (mem_rsp.rresp != OKAY) begin rg_exc_code <= access_exc_code; rg_state <= MODULE_EXCEPTION_RSP; if (cfg_verbosity > 1) @@ -1218,7 +1250,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); PA lev_1_pte_pa = lev_1_PTN_pa + vpn_1_pa; PA lev_1_pte_pa_w64 = { lev_1_pte_pa [pa_sz - 1 : 3], 3'b0 }; // 64b-aligned addr Fabric_Addr lev_1_pte_pa_w64_fa = fn_PA_to_Fabric_Addr (lev_1_pte_pa_w64); - fa_fabric_send_read_req (lev_1_pte_pa_w64_fa, axsize_8); + fa_fabric_send_read_req (lev_1_pte_pa_w64_fa, 8); rg_pte_pa <= lev_1_pte_pa; rg_state <= PTW_LEVEL_1; @@ -1262,7 +1294,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); rule rl_ptw_level_1 (rg_state == PTW_LEVEL_1); // Memory read-response is a level 1 PTE - let mem_rsp <- pop_o (master_xactor.o_rd_data); + let mem_rsp <- get(master_xactor.slave.r); Bit #(64) x64 = zeroExtend (mem_rsp.rdata); WordXL pte; @@ -1279,7 +1311,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); `endif // ifndef RV32 // Bus error - if (mem_rsp.rresp != axi4_resp_okay) begin + if (mem_rsp.rresp != OKAY) begin rg_exc_code <= access_exc_code; rg_state <= MODULE_EXCEPTION_RSP; if (cfg_verbosity > 1) @@ -1312,9 +1344,9 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); PA lev_0_pte_pa_w64 = { lev_0_pte_pa [pa_sz - 1 : 3], 3'b0 }; // 64b-aligned addr Fabric_Addr lev_0_pte_pa_w64_fa = fn_PA_to_Fabric_Addr (lev_0_pte_pa_w64); `ifdef Sv32 - AXI4_Size axi4_size = axsize_4; + AXI4_Size axi4_size = 4; `else - AXI4_Size axi4_size = axsize_8; + AXI4_Size axi4_size = 8; `endif fa_fabric_send_read_req (lev_0_pte_pa_w64_fa, axi4_size); @@ -1360,7 +1392,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); rule rl_ptw_level_0 (rg_state == PTW_LEVEL_0); // Memory read-response is a level 0 PTE - let mem_rsp <- pop_o (master_xactor.o_rd_data); + let mem_rsp <- get(master_xactor.slave.r); Bit #(64) x64 = zeroExtend (mem_rsp.rdata); WordXL pte; @@ -1377,7 +1409,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); `endif // ifndef RV32 // Bus error - if (mem_rsp.rresp != axi4_resp_okay) begin + if (mem_rsp.rresp != OKAY) begin rg_exc_code <= access_exc_code; rg_state <= MODULE_EXCEPTION_RSP; if (cfg_verbosity > 1) @@ -1486,7 +1518,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); // Send request into fabric for next fabric-word of cache line PA cline_addr = fn_align_Addr_to_CLine (rg_pa); Fabric_Addr cline_fabric_addr = (fn_PA_to_Fabric_Addr (cline_addr) | rg_req_byte_in_cline); - AXI4_Size axi4_size = ((bytes_per_fabric_data == 4) ? axsize_4 : axsize_8); + AXI4_Size axi4_size = ((bytes_per_fabric_data == 4) ? 4 : 8); fa_fabric_send_read_req (cline_fabric_addr, axi4_size); // Check if end of refill loop (req_byte_in_cline is last one) @@ -1523,14 +1555,14 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); // (for set read-modify-write; not relevant for direct-mapped) rule rl_cache_refill_rsps_loop (rg_state == CACHE_REFILL); - let mem_rsp <- pop_o (master_xactor.o_rd_data); + let mem_rsp <- get(master_xactor.slave.r); if (cfg_verbosity > 2) begin $display ("%0d: %s.rl_cache_refill_rsps_loop:", cur_cycle, d_or_i); $display (" ", fshow (mem_rsp)); end // Bus errors; remember it, and raise exception after all the refill responses - Bool err_rsp = (mem_rsp.rresp != axi4_resp_okay); + Bool err_rsp = (mem_rsp.rresp != OKAY); if (err_rsp) begin rg_error_during_refill <= True; rg_exc_code <= access_exc_code; @@ -1648,7 +1680,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); rule rl_io_read_rsp ((rg_state == IO_AWAITING_READ_RSP)); - let rd_data <- pop_o (master_xactor.o_rd_data); + let rd_data <- get(master_xactor.slave.r); if (cfg_verbosity > 1) begin $display ("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", cur_cycle, d_or_i, rg_addr, rg_pa); $display (" ", fshow (rd_data)); @@ -1658,7 +1690,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); rg_ld_val <= ld_val; // Successful read - if (rd_data.rresp == axi4_resp_okay) begin + if (rd_data.rresp == OKAY) begin fa_drive_IO_read_rsp (rg_f3, rg_addr, ld_val); rg_state <= IO_READ_RSP; end @@ -1750,7 +1782,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); `endif rule rl_io_AMO_read_rsp (rg_state == IO_AWAITING_AMO_READ_RSP); - let rd_data <- pop_o (master_xactor.o_rd_data); + let rd_data <- get(master_xactor.slave.r); if (cfg_verbosity > 1) begin $display ("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", cur_cycle, d_or_i, rg_addr, rg_pa); $display (" ", fshow (rd_data)); @@ -1759,7 +1791,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); let ld_val = fn_extract_and_extend_bytes(rg_f3, rg_addr, zeroExtend (rd_data.rdata)); // Bus error for AMO read - if (rd_data.rresp != axi4_resp_okay) begin + if (rd_data.rresp != OKAY) begin rg_state <= MODULE_EXCEPTION_RSP; rg_exc_code <= exc_code_STORE_AMO_ACCESS_FAULT; if (cfg_verbosity > 1) @@ -1794,7 +1826,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); // NOTE: assuming in-order responses from fabric rule rl_discard_write_rsp; - let wr_resp <- pop_o (master_xactor.o_wr_resp); + let wr_resp <- get(master_xactor.slave.b); if (ctr_wr_rsps_pending.value == 0) begin $display ("%0d: ERROR: %s.rl_discard_write_rsp: unexpected W response (ctr_wr_rsps_pending.value == 0)", @@ -1805,7 +1837,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); ctr_wr_rsps_pending.decr; - if (wr_resp.bresp != axi4_resp_okay) begin + if (wr_resp.bresp != OKAY) begin // TODO: need to raise a non-maskable interrupt (NMI) here $display ("%0d: %s.rl_discard_write_rsp: fabric response error: exit", cur_cycle, d_or_i); $display (" ", fshow (wr_resp)); @@ -1953,7 +1985,7 @@ module mkMMU_Cache #(parameter Bool dmem_not_imem) (MMU_Cache_IFC); endmethod // Fabric interface - interface mem_master = master_xactor.axi_side; + interface mem_master = master_xactor.masterSynth; endmodule: mkMMU_Cache // ================================================================ diff --git a/src_Core/Near_Mem_VM/Near_Mem_Caches.bsv b/src_Core/Near_Mem_VM/Near_Mem_Caches.bsv index 49613bb5..e99104aa 100644 --- a/src_Core/Near_Mem_VM/Near_Mem_Caches.bsv +++ b/src_Core/Near_Mem_VM/Near_Mem_Caches.bsv @@ -33,6 +33,8 @@ import Connectable :: *; import Cur_Cycle :: *; import GetPut_Aux :: *; +import Routable :: *; +import AXI4 :: *; // ================================================================ // Project imports @@ -40,7 +42,6 @@ import GetPut_Aux :: *; import ISA_Decls :: *; import Near_Mem_IFC :: *; import MMU_Cache :: *; -import AXI4_Types :: *; import Fabric_Defs :: *; // System address map and pc_reset value @@ -71,8 +72,8 @@ module mkNear_Mem (Near_Mem_IFC); // Reset response queue FIFOF #(Token) f_reset_rsps <- mkFIFOF; - MMU_Cache_IFC icache <- mkMMU_Cache (False); - MMU_Cache_IFC dcache <- mkMMU_Cache (True); + MMU_ICache_IFC icache <- mkMMU_ICache; + MMU_DCache_IFC dcache <- mkMMU_DCache; // ---------------------------------------------------------------- // BEHAVIOR diff --git a/src_Core/Near_Mem_VM/Near_Mem_IFC.bsv b/src_Core/Near_Mem_VM/Near_Mem_IFC.bsv index b0f1ec12..5113fae4 100644 --- a/src_Core/Near_Mem_VM/Near_Mem_IFC.bsv +++ b/src_Core/Near_Mem_VM/Near_Mem_IFC.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved. +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + // Near_Mem_IFC encapsulates the MMU and L1 cache. // It is 'near' the CPU (1-cycle access in common case). @@ -29,13 +42,13 @@ import ClientServer :: *; // BSV additional libs import Cur_Cycle :: *; +import AXI4 :: *; // ================================================================ // Project imports -import ISA_Decls :: *; +import ISA_Decls :: *; -import AXI4_Types :: *; import Fabric_Defs :: *; // ================================================================ @@ -51,7 +64,9 @@ interface Near_Mem_IFC; interface IMem_IFC imem; // Fabric side - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) imem_master; + interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) imem_master; // ---------------- // DMem @@ -60,7 +75,9 @@ interface Near_Mem_IFC; interface DMem_IFC dmem; // Fabric side - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) dmem_master; + interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) dmem_master; // ---------------- // Fences diff --git a/src_Core/PLIC/PLIC.bsv b/src_Core/PLIC/PLIC.bsv index 25b04818..173e0102 100644 --- a/src_Core/PLIC/PLIC.bsv +++ b/src_Core/PLIC/PLIC.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2019 Bluespec, Inc. All Rights Reserved +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package PLIC; // ================================================================ @@ -25,13 +38,13 @@ import Assert :: *; import Cur_Cycle :: *; import GetPut_Aux :: *; import Semi_FIFOF :: *; +import SourceSink :: *; +import AXI4 :: *; // ================================================================ // Project imports -import AXI4_Types :: *; -import AXI4_Fabric :: *; -import Fabric_Defs :: *; // for Wd_Id, Wd_Addr, Wd_Data, Wd_User +import Fabric_Defs :: *; // for Wd_SId_2x3, Wd_Addr, Wd_Data... // ================================================================ // Change bitwidth without requiring < or > constraints. @@ -84,7 +97,9 @@ interface PLIC_IFC #(numeric type t_n_external_sources, method Action set_addr_map (Bit #(64) addr_base, Bit #(64) addr_lim); // Memory-mapped access - interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) axi4_slave; + interface AXI4_Slave_Synth #(Wd_SId_2x3, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) axi4_slave; // sources interface Vector #(t_n_external_sources, PLIC_Source_IFC) v_sources; @@ -101,6 +116,8 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) Add #(_any_0, TLog #(t_n_sources), T_wd_source_id), Add #(_any_1, TLog #(t_n_targets), T_wd_target_id), Log #(TAdd #(t_max_priority, 1), t_wd_priority)); +// XXX This module seems to assume the following constraints: +// provisos(Add #(Wd_AW_User, 0, Wd_B_User), Add #(Wd_AR_User, 0, Wd_R_User)); // 0 = quiet; 1 = show PLIC transactions; 2 = also show AXI4 transactions Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0); @@ -126,7 +143,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) Reg #(Bit #(64)) rg_addr_lim <- mkRegU; // Connector to AXI4 fabric - AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave_xactor <- mkAXI4_Slave_Xactor; + let slave_xactor <- mkAXI4_Slave_Xactor; // ---------------- // Per-interrupt source state @@ -228,7 +245,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) for (Integer source_id = 0; source_id < n_sources; source_id = source_id + 1) vvrg_ie [target_id][source_id] <= False; - slave_xactor.reset; + slave_xactor.clear; f_reset_rsps.enq (?); endrule @@ -243,7 +260,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) rule rl_process_rd_req (! f_reset_reqs.notEmpty); - let rda <- pop_o (slave_xactor.o_rd_addr); + let rda <- get(slave_xactor.master.ar); if (cfg_verbosity > 1) begin $display ("%0d: PLIC.rl_process_rd_req:", cur_cycle); $display (" ", fshow (rda)); @@ -251,14 +268,14 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) let addr_offset = rda.araddr - rg_addr_base; Bit #(64) rdata = 0; - AXI4_Resp rresp = axi4_resp_okay; + AXI4_Resp rresp = OKAY; if (rda.araddr < rg_addr_base) begin // Technically this should not happen: the fabric should // never have delivered such an addr to this IP. $display ("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", cur_cycle); $display (" ", fshow (rda)); - rresp = axi4_resp_decerr; + rresp = DECERR; end // Source Priority @@ -272,7 +289,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) cur_cycle, source_id, rdata); end else - rresp = axi4_resp_slverr; + rresp = SLVERR; end // Source IPs (interrupt pending). @@ -297,7 +314,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) cur_cycle, source_id_base, rdata); end else - rresp = axi4_resp_slverr; + rresp = SLVERR; end // Source IEs (interrupt enables) for a target @@ -324,7 +341,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) cur_cycle, source_id_base, rdata); end else - rresp = axi4_resp_slverr; + rresp = SLVERR; end // Target threshold @@ -338,7 +355,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) cur_cycle, target_id, rdata); end else - rresp = axi4_resp_slverr; + rresp = SLVERR; end // Interrupt service claim by target @@ -353,7 +370,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) $display (" Still servicing interrupt from source %0d", vrg_servicing_source [target_id]); $display (" Trying to claim service for source %0d", max_id); $display (" Ignoring."); - rresp = axi4_resp_slverr; + rresp = SLVERR; end else begin if (max_id != 0) begin @@ -369,13 +386,13 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) end end else - rresp = axi4_resp_slverr; + rresp = SLVERR; end else - rresp = axi4_resp_slverr; + rresp = SLVERR; - if (rresp != axi4_resp_okay) begin + if (rresp != OKAY) begin $display ("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", cur_cycle); $display (" ", fshow (rda)); end @@ -385,12 +402,12 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) // Send read-response to bus Fabric_Data x = truncate (rdata); - let rdr = AXI4_Rd_Data {rid: rda.arid, - rdata: x, - rresp: rresp, - rlast: True, - ruser: rda.aruser}; - slave_xactor.i_rd_data.enq (rdr); + let rdr = AXI4_RFlit {rid: rda.arid, + rdata: x, + rresp: rresp, + rlast: True, + ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User + slave_xactor.master.r.put(rdr); if (cfg_verbosity > 1) begin $display ("%0d: PLIC.rl_process_rd_req", cur_cycle); @@ -406,8 +423,8 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) rule rl_process_wr_req (! f_reset_reqs.notEmpty); - let wra <- pop_o (slave_xactor.o_wr_addr); - let wrd <- pop_o (slave_xactor.o_wr_data); + let wra <- get(slave_xactor.master.aw); + let wrd <- get(slave_xactor.master.w); if (cfg_verbosity > 1) begin $display ("%0d: PLIC.rl_process_wr_req", cur_cycle); $display (" ", fshow (wra)); @@ -418,7 +435,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) let wdata32 = (((valueOf (Wd_Data) == 64) && ((addr_offset & 'h7) == 'h4)) ? wrd.wdata [63:32] : wrd.wdata [31:0]); - let bresp = axi4_resp_okay; + let bresp = OKAY; if (wra.awaddr < rg_addr_base) begin // Technically this should not happen: the fabric should @@ -426,7 +443,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) $display ("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", cur_cycle); $display (" ", fshow (wra)); $display (" ", fshow (wrd)); - bresp = axi4_resp_decerr; + bresp = DECERR; end // Source priority @@ -441,7 +458,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) end else begin // Note: write to source_id 0 is error; should it just be ignored? - bresp = axi4_resp_slverr; + bresp = SLVERR; end end @@ -456,7 +473,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) cur_cycle, source_id_base); end else - bresp = axi4_resp_slverr; + bresp = SLVERR; end // Source IEs (interrupt enables) for a target @@ -479,7 +496,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) cur_cycle, target_id, source_id_base, wdata32); end else - bresp = axi4_resp_slverr; + bresp = SLVERR; end // Target threshold @@ -493,7 +510,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) cur_cycle, target_id, wdata32); end else - bresp = axi4_resp_slverr; + bresp = SLVERR; end // Interrupt service completion by target @@ -515,27 +532,27 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) cur_cycle); $display (" Completion message from target %0d to source %0d", target_id, source_id); $display (" Ignoring"); - bresp = axi4_resp_slverr; + bresp = SLVERR; end end else - bresp = axi4_resp_slverr; + bresp = SLVERR; end else - bresp = axi4_resp_slverr; + bresp = SLVERR; - if (bresp != axi4_resp_okay) begin + if (bresp != OKAY) begin $display ("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", cur_cycle); $display (" ", fshow (wra)); $display (" ", fshow (wrd)); end // Send write-response to bus - let wrr = AXI4_Wr_Resp {bid: wra.awid, - bresp: bresp, - buser: wra.awuser}; - slave_xactor.i_wr_resp.enq (wrr); + let wrr = AXI4_BFlit {bid: wra.awid, + bresp: bresp, + buser: wra.awuser}; // XXX This requires that Wd_AW_User == Wd_B_User + slave_xactor.master.b.put(wrr); if (cfg_verbosity > 1) begin $display ("%0d: PLIC.AXI4.rl_process_wr_req", cur_cycle); @@ -610,7 +627,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority)) endmethod // Memory-mapped access - interface axi4_slave = slave_xactor.axi_side; + interface axi4_slave = slave_xactor.slaveSynth; // sources interface v_sources = genWith (fn_mk_PLIC_Source_IFC); diff --git a/src_SSITH_P1/Makefile b/src_SSITH_P1/Makefile index 0edf64d3..1ab09117 100644 --- a/src_SSITH_P1/Makefile +++ b/src_SSITH_P1/Makefile @@ -39,9 +39,13 @@ BSC_COMPILATION_FLAGS += \ CORE_DIRS = $(REPO)/src_Core/CPU:$(REPO)/src_Core/ISA:$(REPO)/src_Core/RegFiles:$(REPO)/src_Core/Core:$(REPO)/src_Core/Near_Mem_VM:$(REPO)/src_Core/PLIC:$(REPO)/src_Core/Near_Mem_IO:$(REPO)/src_Core/Debug_Module:$(REPO)/src_Core/BSV_Additional_Libs -TESTBENCH_DIRS = $(REPO)/src_Testbench/Fabrics/AXI4 +# XXX +# Specify the path to the BlueStuff library (https://github.com/CTSRD-CHERI/BlueStuff) +# What is the best way to distribute this code? Currently lives as a git submodule in $(REPO)/libs +# XXX +AXI_DIRS = $(REPO)/libs/BlueStuff/AXI:$(REPO)/libs/BlueStuff/BlueBasics:$(REPO)/libs/BlueStuff/ -BSC_PATH = -p $(CORE_DIRS):src_BSV:$(TESTBENCH_DIRS):+:%/Libraries/TLM3:%/Libraries/Axi:%/Libraries/Axi4 +BSC_PATH = -p $(CORE_DIRS):src_BSV:$(AXI_DIRS):+ # ---------------- # Top-level file and module @@ -52,8 +56,15 @@ TOPMODULE = mkP1_Core # ================================================================ # bsc compilation flags +# XXX +# Using '-no-show-timestamps' with +# Bluespec Compiler, version 2017.07.A (build 1da80f1, 2017-07-21) +# results in +# Error: Command line: (S0008) +# Unrecognized flag: -no-show-timestamps +# XXX BSC_COMPILATION_FLAGS += \ - -keep-fires -aggressive-conditions -no-warn-action-shadowing -no-show-timestamps \ + -keep-fires -aggressive-conditions -no-warn-action-shadowing \ -suppress-warnings G0020 \ +RTS -K128M -RTS -show-range-conflict diff --git a/src_SSITH_P1/Verilog_RTL/mkCPU.v b/src_SSITH_P1/Verilog_RTL/mkCPU.v index cd2a3606..d3c4eaee 100644 --- a/src_SSITH_P1/Verilog_RTL/mkCPU.v +++ b/src_SSITH_P1/Verilog_RTL/mkCPU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:52 BST 2019 // // // Ports: @@ -9,61 +9,61 @@ // RDY_hart0_server_reset_request_put O 1 reg // hart0_server_reset_response_get O 1 reg // RDY_hart0_server_reset_response_get O 1 reg +// imem_master_awid O 5 +// imem_master_awaddr O 64 +// imem_master_awlen O 8 +// imem_master_awsize O 3 +// imem_master_awburst O 2 +// imem_master_awlock O 1 +// imem_master_awcache O 4 +// imem_master_awprot O 3 +// imem_master_awqos O 4 +// imem_master_awregion O 4 // imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg +// imem_master_wdata O 64 +// imem_master_wstrb O 8 +// imem_master_wlast O 1 // imem_master_wvalid O 1 -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg // imem_master_bready O 1 +// imem_master_arid O 5 +// imem_master_araddr O 64 +// imem_master_arlen O 8 +// imem_master_arsize O 3 +// imem_master_arburst O 2 +// imem_master_arlock O 1 +// imem_master_arcache O 4 +// imem_master_arprot O 3 +// imem_master_arqos O 4 +// imem_master_arregion O 4 // imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg // imem_master_rready O 1 +// dmem_master_awid O 4 +// dmem_master_awaddr O 64 +// dmem_master_awlen O 8 +// dmem_master_awsize O 3 +// dmem_master_awburst O 2 +// dmem_master_awlock O 1 +// dmem_master_awcache O 4 +// dmem_master_awprot O 3 +// dmem_master_awqos O 4 +// dmem_master_awregion O 4 // dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg +// dmem_master_wdata O 64 +// dmem_master_wstrb O 8 +// dmem_master_wlast O 1 // dmem_master_wvalid O 1 -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg // dmem_master_bready O 1 +// dmem_master_arid O 4 +// dmem_master_araddr O 64 +// dmem_master_arlen O 8 +// dmem_master_arsize O 3 +// dmem_master_arburst O 2 +// dmem_master_arlock O 1 +// dmem_master_arcache O 4 +// dmem_master_arprot O 3 +// dmem_master_arqos O 4 +// dmem_master_arregion O 4 // dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg // dmem_master_rready O 1 // RDY_set_verbosity O 1 const // trace_data_out_get O 234 reg @@ -83,26 +83,22 @@ // hart0_server_reset_request_put I 1 reg // imem_master_awready I 1 // imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg +// imem_master_bid I 5 +// imem_master_bresp I 2 // imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg +// imem_master_rid I 5 +// imem_master_rdata I 64 +// imem_master_rresp I 2 +// imem_master_rlast I 1 // dmem_master_awready I 1 // dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg +// dmem_master_bid I 4 +// dmem_master_bresp I 2 // dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg +// dmem_master_rid I 4 +// dmem_master_rdata I 64 +// dmem_master_rresp I 2 +// dmem_master_rlast I 1 // m_external_interrupt_req_set_not_clear I 1 reg // s_external_interrupt_req_set_not_clear I 1 reg // software_interrupt_req_set_not_clear I 1 reg @@ -115,6 +111,10 @@ // hart0_gpr_mem_server_request_put I 38 reg // hart0_csr_mem_server_request_put I 45 reg // EN_hart0_server_reset_request_put I 1 +// imem_master_bvalid I 1 +// imem_master_rvalid I 1 +// dmem_master_bvalid I 1 +// dmem_master_rvalid I 1 // EN_set_verbosity I 1 // EN_hart0_server_run_halt_request_put I 1 // EN_hart0_put_other_req_put I 1 @@ -127,16 +127,246 @@ // EN_hart0_csr_mem_server_response_get I 1 // // Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> imem_master_rready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> dmem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arid +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_araddr +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arlen +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arsize +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arburst +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arlock +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arcache +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arprot +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arqos +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arregion +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_aruser +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arvalid +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arid +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_araddr +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arlen +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arsize +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arburst +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arlock +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arcache +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arprot +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arqos +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arregion +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_aruser +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arvalid // // @@ -164,8 +394,6 @@ module mkCPU(CLK, hart0_server_reset_response_get, RDY_hart0_server_reset_response_get, - imem_master_awvalid, - imem_master_awid, imem_master_awaddr, @@ -186,9 +414,9 @@ module mkCPU(CLK, imem_master_awregion, - imem_master_awready, + imem_master_awvalid, - imem_master_wvalid, + imem_master_awready, imem_master_wdata, @@ -196,16 +424,16 @@ module mkCPU(CLK, imem_master_wlast, + imem_master_wvalid, + imem_master_wready, - imem_master_bvalid, imem_master_bid, imem_master_bresp, + imem_master_bvalid, imem_master_bready, - imem_master_arvalid, - imem_master_arid, imem_master_araddr, @@ -226,18 +454,18 @@ module mkCPU(CLK, imem_master_arregion, + imem_master_arvalid, + imem_master_arready, - imem_master_rvalid, imem_master_rid, imem_master_rdata, imem_master_rresp, imem_master_rlast, + imem_master_rvalid, imem_master_rready, - dmem_master_awvalid, - dmem_master_awid, dmem_master_awaddr, @@ -258,9 +486,9 @@ module mkCPU(CLK, dmem_master_awregion, - dmem_master_awready, + dmem_master_awvalid, - dmem_master_wvalid, + dmem_master_awready, dmem_master_wdata, @@ -268,16 +496,16 @@ module mkCPU(CLK, dmem_master_wlast, + dmem_master_wvalid, + dmem_master_wready, - dmem_master_bvalid, dmem_master_bid, dmem_master_bresp, + dmem_master_bvalid, dmem_master_bready, - dmem_master_arvalid, - dmem_master_arid, dmem_master_araddr, @@ -298,13 +526,15 @@ module mkCPU(CLK, dmem_master_arregion, + dmem_master_arvalid, + dmem_master_arready, - dmem_master_rvalid, dmem_master_rid, dmem_master_rdata, dmem_master_rresp, dmem_master_rlast, + dmem_master_rvalid, dmem_master_rready, @@ -367,226 +597,226 @@ module mkCPU(CLK, output hart0_server_reset_response_get; output RDY_hart0_server_reset_response_get; - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; + // value method imem_master_aw_awid + output [4 : 0] imem_master_awid; - // value method imem_master_m_awaddr + // value method imem_master_aw_awaddr output [63 : 0] imem_master_awaddr; - // value method imem_master_m_awlen + // value method imem_master_aw_awlen output [7 : 0] imem_master_awlen; - // value method imem_master_m_awsize + // value method imem_master_aw_awsize output [2 : 0] imem_master_awsize; - // value method imem_master_m_awburst + // value method imem_master_aw_awburst output [1 : 0] imem_master_awburst; - // value method imem_master_m_awlock + // value method imem_master_aw_awlock output imem_master_awlock; - // value method imem_master_m_awcache + // value method imem_master_aw_awcache output [3 : 0] imem_master_awcache; - // value method imem_master_m_awprot + // value method imem_master_aw_awprot output [2 : 0] imem_master_awprot; - // value method imem_master_m_awqos + // value method imem_master_aw_awqos output [3 : 0] imem_master_awqos; - // value method imem_master_m_awregion + // value method imem_master_aw_awregion output [3 : 0] imem_master_awregion; - // value method imem_master_m_awuser + // value method imem_master_aw_awuser - // action method imem_master_m_awready - input imem_master_awready; + // value method imem_master_aw_awvalid + output imem_master_awvalid; - // value method imem_master_m_wvalid - output imem_master_wvalid; + // action method imem_master_aw_awready + input imem_master_awready; - // value method imem_master_m_wdata + // value method imem_master_w_wdata output [63 : 0] imem_master_wdata; - // value method imem_master_m_wstrb + // value method imem_master_w_wstrb output [7 : 0] imem_master_wstrb; - // value method imem_master_m_wlast + // value method imem_master_w_wlast output imem_master_wlast; - // value method imem_master_m_wuser + // value method imem_master_w_wuser + + // value method imem_master_w_wvalid + output imem_master_wvalid; - // action method imem_master_m_wready + // action method imem_master_w_wready input imem_master_wready; - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; + // action method imem_master_b_bflit + input [4 : 0] imem_master_bid; input [1 : 0] imem_master_bresp; + input imem_master_bvalid; - // value method imem_master_m_bready + // value method imem_master_b_bready output imem_master_bready; - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; + // value method imem_master_ar_arid + output [4 : 0] imem_master_arid; - // value method imem_master_m_araddr + // value method imem_master_ar_araddr output [63 : 0] imem_master_araddr; - // value method imem_master_m_arlen + // value method imem_master_ar_arlen output [7 : 0] imem_master_arlen; - // value method imem_master_m_arsize + // value method imem_master_ar_arsize output [2 : 0] imem_master_arsize; - // value method imem_master_m_arburst + // value method imem_master_ar_arburst output [1 : 0] imem_master_arburst; - // value method imem_master_m_arlock + // value method imem_master_ar_arlock output imem_master_arlock; - // value method imem_master_m_arcache + // value method imem_master_ar_arcache output [3 : 0] imem_master_arcache; - // value method imem_master_m_arprot + // value method imem_master_ar_arprot output [2 : 0] imem_master_arprot; - // value method imem_master_m_arqos + // value method imem_master_ar_arqos output [3 : 0] imem_master_arqos; - // value method imem_master_m_arregion + // value method imem_master_ar_arregion output [3 : 0] imem_master_arregion; - // value method imem_master_m_aruser + // value method imem_master_ar_aruser + + // value method imem_master_ar_arvalid + output imem_master_arvalid; - // action method imem_master_m_arready + // action method imem_master_ar_arready input imem_master_arready; - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; + // action method imem_master_r_rflit + input [4 : 0] imem_master_rid; input [63 : 0] imem_master_rdata; input [1 : 0] imem_master_rresp; input imem_master_rlast; + input imem_master_rvalid; - // value method imem_master_m_rready + // value method imem_master_r_rready output imem_master_rready; - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid + // value method dmem_master_aw_awid output [3 : 0] dmem_master_awid; - // value method dmem_master_m_awaddr + // value method dmem_master_aw_awaddr output [63 : 0] dmem_master_awaddr; - // value method dmem_master_m_awlen + // value method dmem_master_aw_awlen output [7 : 0] dmem_master_awlen; - // value method dmem_master_m_awsize + // value method dmem_master_aw_awsize output [2 : 0] dmem_master_awsize; - // value method dmem_master_m_awburst + // value method dmem_master_aw_awburst output [1 : 0] dmem_master_awburst; - // value method dmem_master_m_awlock + // value method dmem_master_aw_awlock output dmem_master_awlock; - // value method dmem_master_m_awcache + // value method dmem_master_aw_awcache output [3 : 0] dmem_master_awcache; - // value method dmem_master_m_awprot + // value method dmem_master_aw_awprot output [2 : 0] dmem_master_awprot; - // value method dmem_master_m_awqos + // value method dmem_master_aw_awqos output [3 : 0] dmem_master_awqos; - // value method dmem_master_m_awregion + // value method dmem_master_aw_awregion output [3 : 0] dmem_master_awregion; - // value method dmem_master_m_awuser + // value method dmem_master_aw_awuser - // action method dmem_master_m_awready - input dmem_master_awready; + // value method dmem_master_aw_awvalid + output dmem_master_awvalid; - // value method dmem_master_m_wvalid - output dmem_master_wvalid; + // action method dmem_master_aw_awready + input dmem_master_awready; - // value method dmem_master_m_wdata + // value method dmem_master_w_wdata output [63 : 0] dmem_master_wdata; - // value method dmem_master_m_wstrb + // value method dmem_master_w_wstrb output [7 : 0] dmem_master_wstrb; - // value method dmem_master_m_wlast + // value method dmem_master_w_wlast output dmem_master_wlast; - // value method dmem_master_m_wuser + // value method dmem_master_w_wuser + + // value method dmem_master_w_wvalid + output dmem_master_wvalid; - // action method dmem_master_m_wready + // action method dmem_master_w_wready input dmem_master_wready; - // action method dmem_master_m_bvalid - input dmem_master_bvalid; + // action method dmem_master_b_bflit input [3 : 0] dmem_master_bid; input [1 : 0] dmem_master_bresp; + input dmem_master_bvalid; - // value method dmem_master_m_bready + // value method dmem_master_b_bready output dmem_master_bready; - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid + // value method dmem_master_ar_arid output [3 : 0] dmem_master_arid; - // value method dmem_master_m_araddr + // value method dmem_master_ar_araddr output [63 : 0] dmem_master_araddr; - // value method dmem_master_m_arlen + // value method dmem_master_ar_arlen output [7 : 0] dmem_master_arlen; - // value method dmem_master_m_arsize + // value method dmem_master_ar_arsize output [2 : 0] dmem_master_arsize; - // value method dmem_master_m_arburst + // value method dmem_master_ar_arburst output [1 : 0] dmem_master_arburst; - // value method dmem_master_m_arlock + // value method dmem_master_ar_arlock output dmem_master_arlock; - // value method dmem_master_m_arcache + // value method dmem_master_ar_arcache output [3 : 0] dmem_master_arcache; - // value method dmem_master_m_arprot + // value method dmem_master_ar_arprot output [2 : 0] dmem_master_arprot; - // value method dmem_master_m_arqos + // value method dmem_master_ar_arqos output [3 : 0] dmem_master_arqos; - // value method dmem_master_m_arregion + // value method dmem_master_ar_arregion output [3 : 0] dmem_master_arregion; - // value method dmem_master_m_aruser + // value method dmem_master_ar_aruser + + // value method dmem_master_ar_arvalid + output dmem_master_arvalid; - // action method dmem_master_m_arready + // action method dmem_master_ar_arready input dmem_master_arready; - // action method dmem_master_m_rvalid - input dmem_master_rvalid; + // action method dmem_master_r_rflit input [3 : 0] dmem_master_rid; input [63 : 0] dmem_master_rdata; input [1 : 0] dmem_master_rresp; input dmem_master_rlast; + input dmem_master_rvalid; - // value method dmem_master_m_rready + // value method dmem_master_r_rready output dmem_master_rready; // action method m_external_interrupt_req @@ -666,6 +896,7 @@ module mkCPU(CLK, imem_master_arlen, imem_master_awlen, imem_master_wstrb; + wire [4 : 0] imem_master_arid, imem_master_awid; wire [3 : 0] dmem_master_arcache, dmem_master_arid, dmem_master_arqos, @@ -675,11 +906,9 @@ module mkCPU(CLK, dmem_master_awqos, dmem_master_awregion, imem_master_arcache, - imem_master_arid, imem_master_arqos, imem_master_arregion, imem_master_awcache, - imem_master_awid, imem_master_awqos, imem_master_awregion; wire [2 : 0] dmem_master_arprot, @@ -822,6 +1051,21 @@ module mkCPU(CLK, reg rg_stop_req; wire rg_stop_req$D_IN, rg_stop_req$EN; + // register rg_trap_info + reg [67 : 0] rg_trap_info; + wire [67 : 0] rg_trap_info$D_IN; + wire rg_trap_info$EN; + + // register rg_trap_instr + reg [31 : 0] rg_trap_instr; + wire [31 : 0] rg_trap_instr$D_IN; + wire rg_trap_instr$EN; + + // register rg_trap_trace_data + reg [233 : 0] rg_trap_trace_data; + wire [233 : 0] rg_trap_trace_data$D_IN; + wire rg_trap_trace_data$EN; + // register stage1_rg_full reg stage1_rg_full; reg stage1_rg_full$D_IN; @@ -1033,6 +1277,10 @@ module mkCPU(CLK, near_mem$imem_master_wstrb, near_mem$server_fence_request_put; wire [6 : 0] near_mem$dmem_req_amo_funct7; + wire [4 : 0] near_mem$imem_master_arid, + near_mem$imem_master_awid, + near_mem$imem_master_bid, + near_mem$imem_master_rid; wire [3 : 0] near_mem$dmem_exc_code, near_mem$dmem_master_arcache, near_mem$dmem_master_arid, @@ -1046,15 +1294,11 @@ module mkCPU(CLK, near_mem$dmem_master_rid, near_mem$imem_exc_code, near_mem$imem_master_arcache, - near_mem$imem_master_arid, near_mem$imem_master_arqos, near_mem$imem_master_arregion, near_mem$imem_master_awcache, - near_mem$imem_master_awid, near_mem$imem_master_awqos, - near_mem$imem_master_awregion, - near_mem$imem_master_bid, - near_mem$imem_master_rid; + near_mem$imem_master_awregion; wire [2 : 0] near_mem$dmem_master_arprot, near_mem$dmem_master_arsize, near_mem$dmem_master_awprot, @@ -1222,17 +1466,18 @@ module mkCPU(CLK, CAN_FIRE_RL_rl_stage1_trap, CAN_FIRE_RL_rl_stage1_xRET, CAN_FIRE_RL_rl_stage2_nonpipe, + CAN_FIRE_RL_rl_trap, CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode, CAN_FIRE_RL_rl_trap_fetch, CAN_FIRE_RL_stage1_rl_reset, CAN_FIRE_RL_stage2_rl_reset_begin, CAN_FIRE_RL_stage2_rl_reset_end, CAN_FIRE_RL_stage3_rl_reset, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, + CAN_FIRE_dmem_master_ar_arready, + CAN_FIRE_dmem_master_aw_awready, + CAN_FIRE_dmem_master_b_bflit, + CAN_FIRE_dmem_master_r_rflit, + CAN_FIRE_dmem_master_w_wready, CAN_FIRE_hart0_csr_mem_server_request_put, CAN_FIRE_hart0_csr_mem_server_response_get, CAN_FIRE_hart0_gpr_mem_server_request_put, @@ -1242,11 +1487,11 @@ module mkCPU(CLK, CAN_FIRE_hart0_server_reset_response_get, CAN_FIRE_hart0_server_run_halt_request_put, CAN_FIRE_hart0_server_run_halt_response_get, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, + CAN_FIRE_imem_master_ar_arready, + CAN_FIRE_imem_master_aw_awready, + CAN_FIRE_imem_master_b_bflit, + CAN_FIRE_imem_master_r_rflit, + CAN_FIRE_imem_master_w_wready, CAN_FIRE_m_external_interrupt_req, CAN_FIRE_nmi_req, CAN_FIRE_s_external_interrupt_req, @@ -1290,17 +1535,18 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_trap, WILL_FIRE_RL_rl_stage1_xRET, WILL_FIRE_RL_rl_stage2_nonpipe, + WILL_FIRE_RL_rl_trap, WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode, WILL_FIRE_RL_rl_trap_fetch, WILL_FIRE_RL_stage1_rl_reset, WILL_FIRE_RL_stage2_rl_reset_begin, WILL_FIRE_RL_stage2_rl_reset_end, WILL_FIRE_RL_stage3_rl_reset, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, + WILL_FIRE_dmem_master_ar_arready, + WILL_FIRE_dmem_master_aw_awready, + WILL_FIRE_dmem_master_b_bflit, + WILL_FIRE_dmem_master_r_rflit, + WILL_FIRE_dmem_master_w_wready, WILL_FIRE_hart0_csr_mem_server_request_put, WILL_FIRE_hart0_csr_mem_server_response_get, WILL_FIRE_hart0_gpr_mem_server_request_put, @@ -1310,11 +1556,11 @@ module mkCPU(CLK, WILL_FIRE_hart0_server_reset_response_get, WILL_FIRE_hart0_server_run_halt_request_put, WILL_FIRE_hart0_server_run_halt_response_get, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, + WILL_FIRE_imem_master_ar_arready, + WILL_FIRE_imem_master_aw_awready, + WILL_FIRE_imem_master_b_bflit, + WILL_FIRE_imem_master_r_rflit, + WILL_FIRE_imem_master_w_wready, WILL_FIRE_m_external_interrupt_req, WILL_FIRE_nmi_req, WILL_FIRE_s_external_interrupt_req, @@ -1338,7 +1584,7 @@ module mkCPU(CLK, MUX_near_mem$imem_req_2__VAL_2, MUX_near_mem$imem_req_2__VAL_5, MUX_near_mem$imem_req_2__VAL_7; - wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_2, + wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1, MUX_rg_state$write_1__VAL_1, MUX_rg_state$write_1__VAL_2, MUX_rg_state$write_1__VAL_3; @@ -1346,6 +1592,7 @@ module mkCPU(CLK, wire MUX_csr_regfile$mav_csr_write_1__SEL_1, MUX_csr_regfile$mav_csr_write_1__SEL_2, MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1, + MUX_csr_regfile$write_dpc_1__SEL_2, MUX_f_run_halt_rsps$enq_1__SEL_1, MUX_f_trace_data$enq_1__SEL_1, MUX_f_trace_data$enq_1__SEL_3, @@ -1353,85 +1600,79 @@ module mkCPU(CLK, MUX_gpr_regfile$write_rd_1__SEL_1, MUX_imem_rg_f3$write_1__SEL_1, MUX_imem_rg_f3$write_1__SEL_2, + MUX_imem_rg_f3$write_1__SEL_3, MUX_imem_rg_mstatus_MXR$write_1__SEL_4, MUX_imem_rg_pc$write_1__SEL_4, MUX_near_mem$imem_req_1__SEL_6, MUX_rg_cur_priv$write_1__SEL_2, MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_11, - MUX_rg_state$write_1__SEL_12, - MUX_rg_state$write_1__SEL_13, MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3, MUX_rg_state$write_1__SEL_4, - MUX_rg_state$write_1__SEL_6, - MUX_rg_state$write_1__SEL_7, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9, MUX_rg_step_count$write_1__PSEL_1, MUX_rg_step_count$write_1__SEL_3, MUX_stage1_rg_full$write_1__VAL_10, MUX_stage2_rg_full$write_1__VAL_3; // remaining internal signals - reg [63 : 0] x_out_data_to_stage2_trace_data_word3__h17728; + reg [63 : 0] x_out_data_to_stage2_trace_data_word3__h17634; reg [31 : 0] CASE_stage2_rg_stage2_BITS_337_TO_335_0_stage2_ETC__q20, - CASE_theResult__437_BITS_6_TO_0_0b10011_rd_val_ETC__q18, + CASE_theResult__320_BITS_6_TO_0_0b10011_rd_val_ETC__q18, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1027, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942, - _theResult_____1_fst__h13643, - rs1_val__h20813, - x__h18327, - x__h18596, - x_out_bypass_rd_val__h6908, - x_out_data_to_stage2_addr__h12532, - x_out_data_to_stage2_val1__h12533, - x_out_data_to_stage3_rd_val__h6557; - reg [4 : 0] x_out_bypass_rd__h6907, - x_out_data_to_stage2_trace_data_rd__h17725, - x_out_data_to_stage3_rd__h6556; + _theResult_____1_fst__h13549, + rs1_val__h20863, + x__h18233, + x__h18502, + x_out_bypass_rd_val__h6814, + x_out_data_to_stage2_addr__h12438, + x_out_data_to_stage2_val1__h12439, + x_out_data_to_stage3_rd_val__h6463; + reg [4 : 0] x_out_bypass_rd__h6813, + x_out_data_to_stage2_trace_data_rd__h17631, + x_out_data_to_stage3_rd__h6462; reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q5, - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12, - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14, - CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13, - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15, - CASE_theResult__437_BITS_31_TO_20_0b0_CASE_rg__ETC__q6, - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19, + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12, + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14, + CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13, + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15, + CASE_theResult__320_BITS_31_TO_20_0b0_CASE_rg__ETC__q6, + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d731, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d750, - alu_outputs_exc_code__h13199; - reg [2 : 0] CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16, + alu_outputs_exc_code__h13105; + reg [2 : 0] CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16, IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831; reg [1 : 0] CASE_stage2_rg_stage2_BITS_337_TO_335_0_2_1_IF_ETC__q1, CASE_stage2_rg_stage2_BITS_337_TO_335_0_2_1_IF_ETC__q2; - reg CASE_theResult__437_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11, - CASE_theResult__437_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9, - CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8, - CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10, + reg CASE_theResult__320_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11, + CASE_theResult__320_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9, + CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8, + CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634, IF_stage2_rg_stage2_4_BITS_337_TO_335_5_EQ_1_7_ETC___d138, IF_stage2_rg_stage2_4_BITS_337_TO_335_5_EQ_1_7_ETC___d147; wire [233 : 0] IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d1240; - wire [127 : 0] csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1478; - wire [63 : 0] _theResult____h27350, - alu_outputs___1_trace_data_word3__h17603, - alu_outputs___1_trace_data_word3__h17622, - cpi__h27352, - cpifrac__h27353, - delta_CPI_cycles__h27348, - delta_CPI_instrs___1__h27385, - delta_CPI_instrs__h27349, - trace_data_word3__h27067, - x__h27351, - x_word3__h19995, - x_word3__h20591; + wire [127 : 0] csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1486; + wire [63 : 0] _theResult____h27400, + alu_outputs___1_trace_data_word3__h17509, + alu_outputs___1_trace_data_word3__h17528, + cpi__h27402, + cpifrac__h27403, + delta_CPI_cycles__h27398, + delta_CPI_instrs___1__h27435, + delta_CPI_instrs__h27399, + trace_data_word3__h27117, + x__h27401, + x_word3__h20017, + x_word3__h20641; wire [31 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1221, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d943, IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875, - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1367, + IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1375, IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d443, IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d445, IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d447, @@ -1452,119 +1693,119 @@ module mkCPU(CLK, IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d465, IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d466, SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d884, - _theResult_____1_fst__h13636, - _theResult_____1_fst__h13671, - _theResult____h12797, - _theResult____h4437, - _theResult___fst__h7235, - _theResult___fst__h7263, - _theResult___snd__h14769, - alu_outputs___1_addr__h12657, - alu_outputs___1_addr__h12678, - alu_outputs___1_addr__h12704, - alu_outputs___1_val1__h13160, - alu_outputs___1_val1__h13181, - branch_target__h12635, - data_to_stage2_addr__h12523, - eaddr__h12887, - eaddr__h12907, - fall_through_pc__h12486, - instr___1__h7068, - instr__h10415, - instr__h10587, - instr__h10760, - instr__h10953, - instr__h11146, - instr__h11263, - instr__h11441, - instr__h11560, - instr__h11655, - instr__h11791, - instr__h11927, - instr__h12063, - instr__h12401, - instr__h4435, - instr__h7335, - instr__h7480, - instr__h7672, - instr__h7867, - instr__h8096, - instr__h8439, - instr__h8829, - instr__h8945, - instr__h9010, - instr__h9327, - instr__h9665, - instr__h9849, - instr__h9978, - instr_out___1__h7205, - instr_out___1__h7237, - instr_out___1__h7265, - next_pc___1__h14311, - next_pc__h14309, - output_stage2___1_bypass_rd_val__h6896, - rd_val___1__h13624, - rd_val___1__h13632, - rd_val___1__h13639, - rd_val___1__h13646, - rd_val___1__h13653, - rd_val___1__h13660, - rd_val__h12443, - rd_val__h12836, - rd_val__h12853, - rd_val__h12869, - rd_val__h14665, - rd_val__h14717, - rd_val__h14739, - rd_val__h7020, - rs1_val__h20224, - rs1_val_bypassed__h4445, - rs2_val__h12631, - trap_info_tval__h14148, - val__h12445, - val__h7022, - value__h14199, - x__h18419, - x__h21266, - x__h21274, - x_out_data_to_stage2_instr__h12529, - x_out_data_to_stage2_val2__h12534, - x_out_next_pc__h12499, - y__h21114; + _theResult_____1_fst__h13542, + _theResult_____1_fst__h13577, + _theResult____h12703, + _theResult____h4320, + _theResult___fst__h7141, + _theResult___fst__h7169, + _theResult___snd__h14675, + alu_outputs___1_addr__h12563, + alu_outputs___1_addr__h12584, + alu_outputs___1_addr__h12610, + alu_outputs___1_val1__h13066, + alu_outputs___1_val1__h13087, + branch_target__h12541, + data_to_stage2_addr__h12429, + eaddr__h12793, + eaddr__h12813, + fall_through_pc__h12392, + instr___1__h6974, + instr__h10321, + instr__h10493, + instr__h10666, + instr__h10859, + instr__h11052, + instr__h11169, + instr__h11347, + instr__h11466, + instr__h11561, + instr__h11697, + instr__h11833, + instr__h11969, + instr__h12307, + instr__h4318, + instr__h7241, + instr__h7386, + instr__h7578, + instr__h7773, + instr__h8002, + instr__h8345, + instr__h8735, + instr__h8851, + instr__h8916, + instr__h9233, + instr__h9571, + instr__h9755, + instr__h9884, + instr_out___1__h7111, + instr_out___1__h7143, + instr_out___1__h7171, + next_pc___1__h14217, + next_pc__h14215, + output_stage2___1_bypass_rd_val__h6802, + rd_val___1__h13530, + rd_val___1__h13538, + rd_val___1__h13545, + rd_val___1__h13552, + rd_val___1__h13559, + rd_val___1__h13566, + rd_val__h12349, + rd_val__h12742, + rd_val__h12759, + rd_val__h12775, + rd_val__h14571, + rd_val__h14623, + rd_val__h14645, + rd_val__h6926, + rs1_val__h20274, + rs1_val_bypassed__h4328, + rs2_val__h12537, + trap_info_tval__h14054, + val__h12351, + val__h6928, + value__h14105, + x__h18325, + x__h21316, + x__h21324, + x_out_data_to_stage2_instr__h12435, + x_out_data_to_stage2_val2__h12440, + x_out_next_pc__h12405, + y__h21164; wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294, - theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q4; - wire [19 : 0] imm20__h9717; + theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q4; + wire [19 : 0] imm20__h9623; wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323, - theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q3; - wire [11 : 0] imm12__h10213, - imm12__h10428, - imm12__h10624, - imm12__h10969, - imm12__h7336, - imm12__h7673, - imm12__h9589, - offset__h8043, - theResult__437_BITS_31_TO_20__q17, - theResult__437_BITS_31_TO_25_CONCAT_theResult__ETC__q7; - wire [9 : 0] nzimm10__h10211, nzimm10__h10426; - wire [8 : 0] offset__h8954; - wire [7 : 0] offset__h7106; - wire [6 : 0] offset__h7615; - wire [5 : 0] imm6__h9587; - wire [4 : 0] offset_BITS_4_TO_0___h7604, - offset_BITS_4_TO_0___h8035, - rd__h7675, - rs1__h7674, - shamt__h12793, - td1_rd__h22143, - trace_data_rd__h27064, - x_out_data_to_stage2_rd__h12531; + theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q3; + wire [11 : 0] imm12__h10119, + imm12__h10334, + imm12__h10530, + imm12__h10875, + imm12__h7242, + imm12__h7579, + imm12__h9495, + offset__h7949, + theResult__320_BITS_31_TO_20__q17, + theResult__320_BITS_31_TO_25_CONCAT_theResult__ETC__q7; + wire [9 : 0] nzimm10__h10117, nzimm10__h10332; + wire [8 : 0] offset__h8860; + wire [7 : 0] offset__h7012; + wire [6 : 0] offset__h7521; + wire [5 : 0] imm6__h9493; + wire [4 : 0] offset_BITS_4_TO_0___h7510, + offset_BITS_4_TO_0___h7941, + rd__h7581, + rs1__h7580, + shamt__h12699, + td1_rd__h22193, + trace_data_rd__h27114, + x_out_data_to_stage2_rd__h12437; wire [3 : 0] IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d696, IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752, IF_rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_E_ETC___d729, - alu_outputs___1_exc_code__h13156, - cur_verbosity__h3142, - x_out_trap_info_exc_code__h14151; + alu_outputs___1_exc_code__h13062, + cur_verbosity__h2930, + x_out_trap_info_exc_code__h14057; wire [1 : 0] IF_NOT_near_mem_dmem_valid__15_34_OR_NOT_near__ETC___d182, IF_near_mem_dmem_valid__15_THEN_IF_near_mem_dm_ETC___d118, IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124, @@ -1591,11 +1832,11 @@ module mkCPU(CLK, NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41, NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1191, NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1321, - NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1319, + NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1329, + NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1327, NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d818, NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d855, - NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1491, + NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1499, NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_ETC___d211, NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_ETC___d216, NOT_near_mem_imem_valid_02_OR_NOT_near_mem_ime_ETC___d1124, @@ -1613,7 +1854,7 @@ module mkCPU(CLK, _0_OR_0_OR_near_mem_imem_exc__91_OR_IF_IF_NOT_n_ETC___d1284, csr_regfile_csr_mip_read__089_EQ_rg_prev_mip_090___d1091, csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1116, - csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1458, + csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1466, csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d308, csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d314, near_mem_RDY_server_reset_request_put__038_AND_ETC___d1050, @@ -1640,12 +1881,11 @@ module mkCPU(CLK, near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d642, near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691, rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_EQ_0_ETC___d727, - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326, - rg_state_2_EQ_4_083_AND_NOT_stage3_rg_full_4_5_ETC___d1299, - rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1474, + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334, + rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1482, rg_state_2_EQ_4_083_AND_stage3_rg_full_4_OR_NO_ETC___d1154, - rg_state_2_EQ_5_428_OR_rg_state_2_EQ_4_083_AND_ETC___d1437, - rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1469, + rg_state_2_EQ_7_436_OR_rg_state_2_EQ_4_083_AND_ETC___d1445, + rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1477, stage1_rg_full_00_AND_near_mem_imem_valid_AND__ETC___d1087, stage1_rg_full_00_AND_near_mem_imem_valid_AND__ETC___d1110, stage1_rg_full_00_AND_near_mem_imem_valid_AND__ETC___d1129, @@ -1665,212 +1905,212 @@ module mkCPU(CLK, assign WILL_FIRE_hart0_server_reset_response_get = EN_hart0_server_reset_response_get ; - // value method imem_master_m_awvalid - assign imem_master_awvalid = near_mem$imem_master_awvalid ; - - // value method imem_master_m_awid + // value method imem_master_aw_awid assign imem_master_awid = near_mem$imem_master_awid ; - // value method imem_master_m_awaddr + // value method imem_master_aw_awaddr assign imem_master_awaddr = near_mem$imem_master_awaddr ; - // value method imem_master_m_awlen + // value method imem_master_aw_awlen assign imem_master_awlen = near_mem$imem_master_awlen ; - // value method imem_master_m_awsize + // value method imem_master_aw_awsize assign imem_master_awsize = near_mem$imem_master_awsize ; - // value method imem_master_m_awburst + // value method imem_master_aw_awburst assign imem_master_awburst = near_mem$imem_master_awburst ; - // value method imem_master_m_awlock + // value method imem_master_aw_awlock assign imem_master_awlock = near_mem$imem_master_awlock ; - // value method imem_master_m_awcache + // value method imem_master_aw_awcache assign imem_master_awcache = near_mem$imem_master_awcache ; - // value method imem_master_m_awprot + // value method imem_master_aw_awprot assign imem_master_awprot = near_mem$imem_master_awprot ; - // value method imem_master_m_awqos + // value method imem_master_aw_awqos assign imem_master_awqos = near_mem$imem_master_awqos ; - // value method imem_master_m_awregion + // value method imem_master_aw_awregion assign imem_master_awregion = near_mem$imem_master_awregion ; - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; + // value method imem_master_aw_awvalid + assign imem_master_awvalid = near_mem$imem_master_awvalid ; - // value method imem_master_m_wvalid - assign imem_master_wvalid = near_mem$imem_master_wvalid ; + // action method imem_master_aw_awready + assign CAN_FIRE_imem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_imem_master_aw_awready = 1'd1 ; - // value method imem_master_m_wdata + // value method imem_master_w_wdata assign imem_master_wdata = near_mem$imem_master_wdata ; - // value method imem_master_m_wstrb + // value method imem_master_w_wstrb assign imem_master_wstrb = near_mem$imem_master_wstrb ; - // value method imem_master_m_wlast + // value method imem_master_w_wlast assign imem_master_wlast = near_mem$imem_master_wlast ; - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; + // value method imem_master_w_wvalid + assign imem_master_wvalid = near_mem$imem_master_wvalid ; - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; + // action method imem_master_w_wready + assign CAN_FIRE_imem_master_w_wready = 1'd1 ; + assign WILL_FIRE_imem_master_w_wready = 1'd1 ; - // value method imem_master_m_bready - assign imem_master_bready = near_mem$imem_master_bready ; + // action method imem_master_b_bflit + assign CAN_FIRE_imem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_imem_master_b_bflit = imem_master_bvalid ; - // value method imem_master_m_arvalid - assign imem_master_arvalid = near_mem$imem_master_arvalid ; + // value method imem_master_b_bready + assign imem_master_bready = near_mem$imem_master_bready ; - // value method imem_master_m_arid + // value method imem_master_ar_arid assign imem_master_arid = near_mem$imem_master_arid ; - // value method imem_master_m_araddr + // value method imem_master_ar_araddr assign imem_master_araddr = near_mem$imem_master_araddr ; - // value method imem_master_m_arlen + // value method imem_master_ar_arlen assign imem_master_arlen = near_mem$imem_master_arlen ; - // value method imem_master_m_arsize + // value method imem_master_ar_arsize assign imem_master_arsize = near_mem$imem_master_arsize ; - // value method imem_master_m_arburst + // value method imem_master_ar_arburst assign imem_master_arburst = near_mem$imem_master_arburst ; - // value method imem_master_m_arlock + // value method imem_master_ar_arlock assign imem_master_arlock = near_mem$imem_master_arlock ; - // value method imem_master_m_arcache + // value method imem_master_ar_arcache assign imem_master_arcache = near_mem$imem_master_arcache ; - // value method imem_master_m_arprot + // value method imem_master_ar_arprot assign imem_master_arprot = near_mem$imem_master_arprot ; - // value method imem_master_m_arqos + // value method imem_master_ar_arqos assign imem_master_arqos = near_mem$imem_master_arqos ; - // value method imem_master_m_arregion + // value method imem_master_ar_arregion assign imem_master_arregion = near_mem$imem_master_arregion ; - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; + // value method imem_master_ar_arvalid + assign imem_master_arvalid = near_mem$imem_master_arvalid ; - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; + // action method imem_master_ar_arready + assign CAN_FIRE_imem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_imem_master_ar_arready = 1'd1 ; - // value method imem_master_m_rready - assign imem_master_rready = near_mem$imem_master_rready ; + // action method imem_master_r_rflit + assign CAN_FIRE_imem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_imem_master_r_rflit = imem_master_rvalid ; - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; + // value method imem_master_r_rready + assign imem_master_rready = near_mem$imem_master_rready ; - // value method dmem_master_m_awid + // value method dmem_master_aw_awid assign dmem_master_awid = near_mem$dmem_master_awid ; - // value method dmem_master_m_awaddr + // value method dmem_master_aw_awaddr assign dmem_master_awaddr = near_mem$dmem_master_awaddr ; - // value method dmem_master_m_awlen + // value method dmem_master_aw_awlen assign dmem_master_awlen = near_mem$dmem_master_awlen ; - // value method dmem_master_m_awsize + // value method dmem_master_aw_awsize assign dmem_master_awsize = near_mem$dmem_master_awsize ; - // value method dmem_master_m_awburst + // value method dmem_master_aw_awburst assign dmem_master_awburst = near_mem$dmem_master_awburst ; - // value method dmem_master_m_awlock + // value method dmem_master_aw_awlock assign dmem_master_awlock = near_mem$dmem_master_awlock ; - // value method dmem_master_m_awcache + // value method dmem_master_aw_awcache assign dmem_master_awcache = near_mem$dmem_master_awcache ; - // value method dmem_master_m_awprot + // value method dmem_master_aw_awprot assign dmem_master_awprot = near_mem$dmem_master_awprot ; - // value method dmem_master_m_awqos + // value method dmem_master_aw_awqos assign dmem_master_awqos = near_mem$dmem_master_awqos ; - // value method dmem_master_m_awregion + // value method dmem_master_aw_awregion assign dmem_master_awregion = near_mem$dmem_master_awregion ; - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; + // value method dmem_master_aw_awvalid + assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; + // action method dmem_master_aw_awready + assign CAN_FIRE_dmem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_dmem_master_aw_awready = 1'd1 ; - // value method dmem_master_m_wdata + // value method dmem_master_w_wdata assign dmem_master_wdata = near_mem$dmem_master_wdata ; - // value method dmem_master_m_wstrb + // value method dmem_master_w_wstrb assign dmem_master_wstrb = near_mem$dmem_master_wstrb ; - // value method dmem_master_m_wlast + // value method dmem_master_w_wlast assign dmem_master_wlast = near_mem$dmem_master_wlast ; - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; + // value method dmem_master_w_wvalid + assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; + // action method dmem_master_w_wready + assign CAN_FIRE_dmem_master_w_wready = 1'd1 ; + assign WILL_FIRE_dmem_master_w_wready = 1'd1 ; - // value method dmem_master_m_bready - assign dmem_master_bready = near_mem$dmem_master_bready ; + // action method dmem_master_b_bflit + assign CAN_FIRE_dmem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_dmem_master_b_bflit = dmem_master_bvalid ; - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; + // value method dmem_master_b_bready + assign dmem_master_bready = near_mem$dmem_master_bready ; - // value method dmem_master_m_arid + // value method dmem_master_ar_arid assign dmem_master_arid = near_mem$dmem_master_arid ; - // value method dmem_master_m_araddr + // value method dmem_master_ar_araddr assign dmem_master_araddr = near_mem$dmem_master_araddr ; - // value method dmem_master_m_arlen + // value method dmem_master_ar_arlen assign dmem_master_arlen = near_mem$dmem_master_arlen ; - // value method dmem_master_m_arsize + // value method dmem_master_ar_arsize assign dmem_master_arsize = near_mem$dmem_master_arsize ; - // value method dmem_master_m_arburst + // value method dmem_master_ar_arburst assign dmem_master_arburst = near_mem$dmem_master_arburst ; - // value method dmem_master_m_arlock + // value method dmem_master_ar_arlock assign dmem_master_arlock = near_mem$dmem_master_arlock ; - // value method dmem_master_m_arcache + // value method dmem_master_ar_arcache assign dmem_master_arcache = near_mem$dmem_master_arcache ; - // value method dmem_master_m_arprot + // value method dmem_master_ar_arprot assign dmem_master_arprot = near_mem$dmem_master_arprot ; - // value method dmem_master_m_arqos + // value method dmem_master_ar_arqos assign dmem_master_arqos = near_mem$dmem_master_arqos ; - // value method dmem_master_m_arregion + // value method dmem_master_ar_arregion assign dmem_master_arregion = near_mem$dmem_master_arregion ; - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; + // value method dmem_master_ar_arvalid + assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; + + // action method dmem_master_ar_arready + assign CAN_FIRE_dmem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_dmem_master_ar_arready = 1'd1 ; - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; + // action method dmem_master_r_rflit + assign CAN_FIRE_dmem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_dmem_master_r_rflit = dmem_master_rvalid ; - // value method dmem_master_m_rready + // value method dmem_master_r_rready assign dmem_master_rready = near_mem$dmem_master_rready ; // action method m_external_interrupt_req @@ -2026,7 +2266,7 @@ module mkCPU(CLK, .RDY_debug()); // submodule f_csr_reqs - FIFO1 #(.width(32'd45), .guarded(32'd1)) f_csr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd45), .guarded(32'd1)) f_csr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_csr_reqs$D_IN), .ENQ(f_csr_reqs$ENQ), @@ -2037,7 +2277,7 @@ module mkCPU(CLK, .EMPTY_N(f_csr_reqs$EMPTY_N)); // submodule f_csr_rsps - FIFO1 #(.width(32'd33), .guarded(32'd1)) f_csr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd33), .guarded(32'd1)) f_csr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_csr_rsps$D_IN), .ENQ(f_csr_rsps$ENQ), @@ -2048,7 +2288,7 @@ module mkCPU(CLK, .EMPTY_N(f_csr_rsps$EMPTY_N)); // submodule f_gpr_reqs - FIFO1 #(.width(32'd38), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd38), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_gpr_reqs$D_IN), .ENQ(f_gpr_reqs$ENQ), @@ -2059,7 +2299,7 @@ module mkCPU(CLK, .EMPTY_N(f_gpr_reqs$EMPTY_N)); // submodule f_gpr_rsps - FIFO1 #(.width(32'd33), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd33), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_gpr_rsps$D_IN), .ENQ(f_gpr_rsps$ENQ), @@ -2148,12 +2388,10 @@ module mkCPU(CLK, .dmem_master_awready(near_mem$dmem_master_awready), .dmem_master_bid(near_mem$dmem_master_bid), .dmem_master_bresp(near_mem$dmem_master_bresp), - .dmem_master_bvalid(near_mem$dmem_master_bvalid), .dmem_master_rdata(near_mem$dmem_master_rdata), .dmem_master_rid(near_mem$dmem_master_rid), .dmem_master_rlast(near_mem$dmem_master_rlast), .dmem_master_rresp(near_mem$dmem_master_rresp), - .dmem_master_rvalid(near_mem$dmem_master_rvalid), .dmem_master_wready(near_mem$dmem_master_wready), .dmem_req_addr(near_mem$dmem_req_addr), .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7), @@ -2168,12 +2406,10 @@ module mkCPU(CLK, .imem_master_awready(near_mem$imem_master_awready), .imem_master_bid(near_mem$imem_master_bid), .imem_master_bresp(near_mem$imem_master_bresp), - .imem_master_bvalid(near_mem$imem_master_bvalid), .imem_master_rdata(near_mem$imem_master_rdata), .imem_master_rid(near_mem$imem_master_rid), .imem_master_rlast(near_mem$imem_master_rlast), .imem_master_rresp(near_mem$imem_master_rresp), - .imem_master_rvalid(near_mem$imem_master_rvalid), .imem_master_wready(near_mem$imem_master_wready), .imem_req_addr(near_mem$imem_req_addr), .imem_req_f3(near_mem$imem_req_f3), @@ -2185,7 +2421,11 @@ module mkCPU(CLK, .EN_server_reset_request_put(near_mem$EN_server_reset_request_put), .EN_server_reset_response_get(near_mem$EN_server_reset_response_get), .EN_imem_req(near_mem$EN_imem_req), + .imem_master_bvalid(near_mem$imem_master_bvalid), + .imem_master_rvalid(near_mem$imem_master_rvalid), .EN_dmem_req(near_mem$EN_dmem_req), + .dmem_master_bvalid(near_mem$dmem_master_bvalid), + .dmem_master_rvalid(near_mem$dmem_master_rvalid), .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put), .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get), .EN_server_fence_request_put(near_mem$EN_server_fence_request_put), @@ -2200,7 +2440,6 @@ module mkCPU(CLK, .imem_exc(near_mem$imem_exc), .imem_exc_code(near_mem$imem_exc_code), .imem_tval(), - .imem_master_awvalid(near_mem$imem_master_awvalid), .imem_master_awid(near_mem$imem_master_awid), .imem_master_awaddr(near_mem$imem_master_awaddr), .imem_master_awlen(near_mem$imem_master_awlen), @@ -2211,12 +2450,12 @@ module mkCPU(CLK, .imem_master_awprot(near_mem$imem_master_awprot), .imem_master_awqos(near_mem$imem_master_awqos), .imem_master_awregion(near_mem$imem_master_awregion), - .imem_master_wvalid(near_mem$imem_master_wvalid), + .imem_master_awvalid(near_mem$imem_master_awvalid), .imem_master_wdata(near_mem$imem_master_wdata), .imem_master_wstrb(near_mem$imem_master_wstrb), .imem_master_wlast(near_mem$imem_master_wlast), + .imem_master_wvalid(near_mem$imem_master_wvalid), .imem_master_bready(near_mem$imem_master_bready), - .imem_master_arvalid(near_mem$imem_master_arvalid), .imem_master_arid(near_mem$imem_master_arid), .imem_master_araddr(near_mem$imem_master_araddr), .imem_master_arlen(near_mem$imem_master_arlen), @@ -2227,13 +2466,13 @@ module mkCPU(CLK, .imem_master_arprot(near_mem$imem_master_arprot), .imem_master_arqos(near_mem$imem_master_arqos), .imem_master_arregion(near_mem$imem_master_arregion), + .imem_master_arvalid(near_mem$imem_master_arvalid), .imem_master_rready(near_mem$imem_master_rready), .dmem_valid(near_mem$dmem_valid), .dmem_word64(near_mem$dmem_word64), .dmem_st_amo_val(), .dmem_exc(near_mem$dmem_exc), .dmem_exc_code(near_mem$dmem_exc_code), - .dmem_master_awvalid(near_mem$dmem_master_awvalid), .dmem_master_awid(near_mem$dmem_master_awid), .dmem_master_awaddr(near_mem$dmem_master_awaddr), .dmem_master_awlen(near_mem$dmem_master_awlen), @@ -2244,12 +2483,12 @@ module mkCPU(CLK, .dmem_master_awprot(near_mem$dmem_master_awprot), .dmem_master_awqos(near_mem$dmem_master_awqos), .dmem_master_awregion(near_mem$dmem_master_awregion), - .dmem_master_wvalid(near_mem$dmem_master_wvalid), + .dmem_master_awvalid(near_mem$dmem_master_awvalid), .dmem_master_wdata(near_mem$dmem_master_wdata), .dmem_master_wstrb(near_mem$dmem_master_wstrb), .dmem_master_wlast(near_mem$dmem_master_wlast), + .dmem_master_wvalid(near_mem$dmem_master_wvalid), .dmem_master_bready(near_mem$dmem_master_bready), - .dmem_master_arvalid(near_mem$dmem_master_arvalid), .dmem_master_arid(near_mem$dmem_master_arid), .dmem_master_araddr(near_mem$dmem_master_araddr), .dmem_master_arlen(near_mem$dmem_master_arlen), @@ -2260,6 +2499,7 @@ module mkCPU(CLK, .dmem_master_arprot(near_mem$dmem_master_arprot), .dmem_master_arqos(near_mem$dmem_master_arqos), .dmem_master_arregion(near_mem$dmem_master_arregion), + .dmem_master_arvalid(near_mem$dmem_master_arvalid), .dmem_master_rready(near_mem$dmem_master_rready), .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put), .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get), @@ -2273,36 +2513,16 @@ module mkCPU(CLK, .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_flash_mem_addr_base(), - .m_flash_mem_addr_size(), - .m_flash_mem_addr_lim(), - .m_ethernet_0_addr_base(), - .m_ethernet_0_addr_size(), - .m_ethernet_0_addr_lim(), - .m_dma_0_addr_base(), - .m_dma_0_addr_size(), - .m_dma_0_addr_lim(), - .m_uart16550_0_addr_base(), - .m_uart16550_0_addr_size(), - .m_uart16550_0_addr_lim(), - .m_gpio_0_addr_base(), - .m_gpio_0_addr_size(), - .m_gpio_0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_ddr4_0_uncached_addr_base(), - .m_ddr4_0_uncached_addr_size(), - .m_ddr4_0_uncached_addr_lim(), - .m_ddr4_0_cached_addr_base(), - .m_ddr4_0_cached_addr_size(), - .m_ddr4_0_cached_addr_lim(), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), @@ -2389,7 +2609,7 @@ module mkCPU(CLK, rg_state != 4'd1 && rg_state != 4'd2 && rg_state != 4'd3 && - rg_state != 4'd11 ; + rg_state != 4'd12 ; assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ; // rule RL_rl_stage1_mip_cmd @@ -2401,8 +2621,13 @@ module mkCPU(CLK, assign WILL_FIRE_RL_rl_stage1_mip_cmd = CAN_FIRE_RL_rl_stage1_mip_cmd ; // rule RL_rl_stage1_SFENCE_VMA - assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_12 ; - assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_12 ; + assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = + f_trace_data$FULL_N && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && + IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == + 4'd6 ; + assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = + CAN_FIRE_RL_rl_stage1_SFENCE_VMA ; // rule RL_rl_debug_run_redundant assign CAN_FIRE_RL_rl_debug_run_redundant = @@ -2452,7 +2677,7 @@ module mkCPU(CLK, // rule RL_rl_debug_run assign CAN_FIRE_RL_rl_debug_run = - NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1491 && + NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1499 && f_run_halt_reqs$D_OUT && rg_state == 4'd3 ; assign WILL_FIRE_RL_rl_debug_run = @@ -2483,7 +2708,7 @@ module mkCPU(CLK, // rule RL_rl_stage1_xRET assign CAN_FIRE_RL_rl_stage1_xRET = f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && (IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == 4'd7 || IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == @@ -2493,31 +2718,43 @@ module mkCPU(CLK, assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ; // rule RL_rl_stage1_FENCE_I - assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_10 ; - assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_10 ; + assign CAN_FIRE_RL_rl_stage1_FENCE_I = + near_mem$RDY_server_fence_i_request_put && f_trace_data$FULL_N && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && + IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == + 4'd5 ; + assign WILL_FIRE_RL_rl_stage1_FENCE_I = CAN_FIRE_RL_rl_stage1_FENCE_I ; // rule RL_rl_stage1_FENCE - assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_11 ; - assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_11 ; + assign CAN_FIRE_RL_rl_stage1_FENCE = + near_mem$RDY_server_fence_request_put && f_trace_data$FULL_N && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && + IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == + 4'd4 ; + assign WILL_FIRE_RL_rl_stage1_FENCE = CAN_FIRE_RL_rl_stage1_FENCE ; // rule RL_rl_stage1_WFI - assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_13 ; - assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_13 ; + assign CAN_FIRE_RL_rl_stage1_WFI = + f_trace_data$FULL_N && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && + IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == + 4'd10 ; + assign WILL_FIRE_RL_rl_stage1_WFI = CAN_FIRE_RL_rl_stage1_WFI ; // rule RL_rl_stage1_trap assign CAN_FIRE_RL_rl_stage1_trap = f_trace_data$FULL_N && - rg_state_2_EQ_5_428_OR_rg_state_2_EQ_4_083_AND_ETC___d1437 ; + rg_state_2_EQ_7_436_OR_rg_state_2_EQ_4_083_AND_ETC___d1445 ; assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ; // rule RL_rl_trap_BREAK_to_Debug_Mode assign CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode = near_mem$RDY_server_fence_i_request_put && f_run_halt_rsps$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == 4'd11 && - x_out_trap_info_exc_code__h14151 == 4'd3 && + x_out_trap_info_exc_code__h14057 == 4'd3 && csr_regfile$dcsr_break_enters_debug ; assign WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode = CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ; @@ -2528,12 +2765,12 @@ module mkCPU(CLK, f_run_halt_rsps$FULL_N && rg_state == 4'd2 ; assign WILL_FIRE_RL_rl_BREAK_cache_flush_finish = - MUX_rg_state$write_1__SEL_7 ; + CAN_FIRE_RL_rl_BREAK_cache_flush_finish ; // rule RL_rl_stage1_stop assign CAN_FIRE_RL_rl_stage1_stop = near_mem$RDY_server_fence_i_request_put && - rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1474 ; + rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1482 ; assign WILL_FIRE_RL_rl_stage1_stop = CAN_FIRE_RL_rl_stage1_stop && !WILL_FIRE_RL_rl_reset_from_Debug_Module ; @@ -2577,21 +2814,29 @@ module mkCPU(CLK, !WILL_FIRE_RL_rl_stage1_FENCE && !WILL_FIRE_RL_rl_stage1_FENCE_I && !WILL_FIRE_RL_rl_stage1_xRET && - !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !WILL_FIRE_RL_rl_stage1_CSRR_W ; + !WILL_FIRE_RL_rl_stage1_CSRR_W && + !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ; // rule RL_rl_stage2_nonpipe assign CAN_FIRE_RL_rl_stage2_nonpipe = - f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_stage3_rg_full_4_5_ETC___d1299 ; + rg_state == 4'd4 && !stage3_rg_full && + IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == + 2'd3 ; assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ; + // rule RL_rl_trap + assign CAN_FIRE_RL_rl_trap = + f_trace_data$FULL_N && rg_state == 4'd5 && + (!stage1_rg_full || + near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d490) ; + assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ; + // rule RL_rl_stage1_restart_after_csrrx assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx = (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd7 ; + rg_state == 4'd8 ; assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx = CAN_FIRE_RL_rl_stage1_restart_after_csrrx ; @@ -2601,7 +2846,7 @@ module mkCPU(CLK, imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && near_mem$RDY_server_fence_i_response_get && - rg_state == 4'd8 ; + rg_state == 4'd9 ; assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ; // rule RL_rl_finish_SFENCE_VMA @@ -2609,7 +2854,7 @@ module mkCPU(CLK, (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd10 ; + rg_state == 4'd11 ; assign WILL_FIRE_RL_rl_finish_SFENCE_VMA = CAN_FIRE_RL_rl_finish_SFENCE_VMA ; @@ -2619,7 +2864,7 @@ module mkCPU(CLK, imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && near_mem$RDY_server_fence_response_get && - rg_state == 4'd9 ; + rg_state == 4'd10 ; assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ; // rule RL_rl_WFI_resume @@ -2627,24 +2872,16 @@ module mkCPU(CLK, (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd11 && + rg_state == 4'd12 && csr_regfile$wfi_resume ; assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ; // rule RL_rl_reset_from_WFI assign CAN_FIRE_RL_rl_reset_from_WFI = - rg_state == 4'd11 && f_reset_reqs$EMPTY_N ; + rg_state == 4'd12 && f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_rl_reset_from_WFI = CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ; - // rule RL_rl_trap_fetch - assign CAN_FIRE_RL_rl_trap_fetch = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; - // rule RL_rl_reset_from_Debug_Module assign CAN_FIRE_RL_rl_reset_from_Debug_Module = f_reset_reqs$EMPTY_N && rg_state != 4'd0 ; @@ -2652,6 +2889,7 @@ module mkCPU(CLK, CAN_FIRE_RL_rl_reset_from_Debug_Module && !WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode && !WILL_FIRE_RL_rl_trap_fetch && + !WILL_FIRE_RL_rl_BREAK_cache_flush_finish && !WILL_FIRE_RL_rl_stage1_trap && !WILL_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume && @@ -2663,14 +2901,23 @@ module mkCPU(CLK, !WILL_FIRE_RL_rl_stage1_FENCE_I && !WILL_FIRE_RL_rl_stage1_xRET && !WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && !WILL_FIRE_RL_rl_stage1_CSRR_W && + !WILL_FIRE_RL_rl_trap && + !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && !WILL_FIRE_RL_rl_stage2_nonpipe ; + // rule RL_rl_trap_fetch + assign CAN_FIRE_RL_rl_trap_fetch = + (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || + imem_rg_pc[1:0] == 2'b0 || + near_mem$imem_instr[17:16] != 2'b11) && + rg_state == 4'd6 ; + assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; + // rule RL_rl_stage1_interrupt assign CAN_FIRE_RL_rl_stage1_interrupt = f_trace_data$FULL_N && - csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1458 ; + csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1466 ; assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt && !WILL_FIRE_RL_rl_reset_from_Debug_Module ; @@ -2716,9 +2963,12 @@ module mkCPU(CLK, assign MUX_csr_regfile$mav_csr_write_1__SEL_2 = WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h12529[19:15] != 5'd0 ; + x_out_data_to_stage2_instr__h12435[19:15] != 5'd0 ; assign MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1 = WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset ; + assign MUX_csr_regfile$write_dpc_1__SEL_2 = + WILL_FIRE_RL_rl_stage1_stop || + WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ; assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halt_redundant || WILL_FIRE_RL_rl_BREAK_cache_flush_finish || @@ -2741,6 +2991,13 @@ module mkCPU(CLK, assign MUX_imem_rg_f3$write_1__SEL_2 = WILL_FIRE_RL_rl_pipe && NOT_stage1_rg_full_00_01_OR_NOT_near_mem_imem__ETC___d1268 ; + assign MUX_imem_rg_f3$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_trap_fetch || + WILL_FIRE_RL_rl_WFI_resume || + WILL_FIRE_RL_rl_finish_SFENCE_VMA || + WILL_FIRE_RL_rl_finish_FENCE || + WILL_FIRE_RL_rl_finish_FENCE_I || + WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 = WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || @@ -2760,62 +3017,29 @@ module mkCPU(CLK, assign MUX_rg_cur_priv$write_1__SEL_2 = WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe ; + WILL_FIRE_RL_rl_trap ; assign MUX_rg_state$write_1__SEL_1 = CAN_FIRE_RL_rl_reset_complete && !WILL_FIRE_RL_imem_rl_fetch_next_32b && !WILL_FIRE_RL_rl_reset_from_Debug_Module ; assign MUX_rg_state$write_1__SEL_2 = (!csr_regfile$access_permitted_1 || f_trace_data$FULL_N) && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == 4'd2 ; assign MUX_rg_state$write_1__SEL_3 = (!csr_regfile$access_permitted_2 || f_trace_data$FULL_N) && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == 4'd3 ; assign MUX_rg_state$write_1__SEL_4 = WILL_FIRE_RL_rl_reset_from_Debug_Module || WILL_FIRE_RL_rl_reset_from_WFI ; - assign MUX_rg_state$write_1__SEL_6 = - WILL_FIRE_RL_rl_stage1_stop || - WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ; - assign MUX_rg_state$write_1__SEL_7 = - CAN_FIRE_RL_rl_BREAK_cache_flush_finish && - !WILL_FIRE_RL_rl_reset_from_Debug_Module ; - assign MUX_rg_state$write_1__SEL_8 = - WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_rg_state$write_1__SEL_9 = + assign MUX_rg_state$write_1__SEL_10 = WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_state$write_1__SEL_10 = - near_mem$RDY_server_fence_i_request_put && f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && - IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == - 4'd5 ; - assign MUX_rg_state$write_1__SEL_11 = - near_mem$RDY_server_fence_request_put && f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && - IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == - 4'd4 ; - assign MUX_rg_state$write_1__SEL_12 = - f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && - IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == - 4'd6 ; - assign MUX_rg_state$write_1__SEL_13 = - f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && - IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == - 4'd10 ; + WILL_FIRE_RL_rl_trap ; assign MUX_rg_step_count$write_1__PSEL_1 = WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || @@ -2825,21 +3049,21 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_pipe ; assign MUX_rg_step_count$write_1__SEL_3 = WILL_FIRE_RL_rl_stage1_stop || WILL_FIRE_RL_rl_reset_start ; - assign MUX_csr_regfile$csr_trap_actions_5__VAL_2 = + assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 = (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ? csr_regfile$interrupt_pending[3:0] : 4'd0 ; - always@(x_out_data_to_stage2_instr__h12529 or + always@(x_out_data_to_stage2_instr__h12435 or csr_regfile$read_csr or - y__h21114 or - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1367) + y__h21164 or + IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1375) begin - case (x_out_data_to_stage2_instr__h12529[14:12]) + case (x_out_data_to_stage2_instr__h12435[14:12]) 3'b010, 3'b110: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1367; + IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1375; default: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - csr_regfile$read_csr[31:0] & y__h21114; + csr_regfile$read_csr[31:0] & y__h21164; endcase end assign MUX_csr_regfile$write_dcsr_cause_priv_1__VAL_2 = @@ -2853,72 +3077,72 @@ module mkCPU(CLK, stage2_rg_stage2[127:0] } ; assign MUX_f_trace_data$enq_1__VAL_2 = { 4'd14, - x__h18327, + x__h18233, near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482, - x__h18419, - x_out_data_to_stage2_instr__h12529[11:7], + x__h18325, + x_out_data_to_stage2_instr__h12435[11:7], csr_regfile$read_csr[31:0], 32'd1, - x_word3__h20591, + x_word3__h20641, csr_regfile$mav_csr_write } ; assign MUX_f_trace_data$enq_1__VAL_3 = { 4'd14, - x__h18327, + x__h18233, near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482, - x__h18419, - x_out_data_to_stage2_instr__h12529[11:7], + x__h18325, + x_out_data_to_stage2_instr__h12435[11:7], csr_regfile$read_csr[31:0], - x__h21266, - x_word3__h20591, - x__h21274 } ; + x__h21316, + x_word3__h20641, + x__h21324 } ; assign MUX_f_trace_data$enq_1__VAL_6 = { 202'h0EAAAAAAA955555554AAAAAAAAAAAAAAAAA0000000000000344, csr_regfile$csr_mip_read } ; assign MUX_f_trace_data$enq_1__VAL_7 = { 4'd12, csr_regfile$csr_trap_actions[97:66], - stage2_rg_stage2[197:165], - trace_data_rd__h27064, + rg_trap_trace_data[197:165], + trace_data_rd__h27114, csr_regfile$csr_trap_actions[65:2], - x_word3__h19995, - stage2_rg_stage2[329:298] } ; + x_word3__h20017, + rg_trap_info[31:0] } ; assign MUX_f_trace_data$enq_1__VAL_8 = { 4'd13, csr_regfile$csr_ret_actions[65:34], near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482, - x__h18419, - td1_rd__h22143, + x__h18325, + td1_rd__h22193, csr_regfile$csr_ret_actions[31:0], 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_f_trace_data$enq_1__VAL_9 = { 4'd12, csr_regfile$csr_trap_actions[97:66], near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482, - x__h18419, - trace_data_rd__h27064, + x__h18325, + trace_data_rd__h27114, csr_regfile$csr_trap_actions[65:2], - trace_data_word3__h27067, - value__h14199 } ; + trace_data_word3__h27117, + value__h14105 } ; assign MUX_f_trace_data$enq_1__VAL_10 = { 4'd15, csr_regfile$csr_trap_actions[97:66], 33'h0AAAAAAAA, - trace_data_rd__h27064, + trace_data_rd__h27114, csr_regfile$csr_trap_actions[65:2], - trace_data_word3__h27067, + trace_data_word3__h27117, 32'd0 } ; assign MUX_near_mem$imem_req_2__VAL_1 = { soc_map$m_pc_reset_value[31:2], 2'b0 } ; assign MUX_near_mem$imem_req_2__VAL_2 = - { x_out_next_pc__h12499[31:2], 2'b0 } ; + { x_out_next_pc__h12405[31:2], 2'b0 } ; assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[31:2], 2'b0 } ; assign MUX_near_mem$imem_req_2__VAL_7 = { csr_regfile$read_dpc[31:2], 2'b0 } ; assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd4 : 4'd3 ; assign MUX_rg_state$write_1__VAL_2 = - csr_regfile$access_permitted_1 ? 4'd7 : 4'd5 ; + csr_regfile$access_permitted_1 ? 4'd8 : 4'd7 ; assign MUX_rg_state$write_1__VAL_3 = - csr_regfile$access_permitted_2 ? 4'd7 : 4'd5 ; + csr_regfile$access_permitted_2 ? 4'd8 : 4'd7 ; assign MUX_stage1_rg_full$write_1__VAL_10 = NOT_stage1_rg_full_00_01_OR_NOT_near_mem_imem__ETC___d1260 && csr_regfile_csr_mip_read__089_EQ_rg_prev_mip_090___d1091 && @@ -2986,7 +3210,7 @@ module mkCPU(CLK, always@(MUX_imem_rg_f3$write_1__SEL_1 or soc_map$m_pc_reset_value or MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h12499 or + x_out_next_pc__h12405 or WILL_FIRE_RL_rl_stage1_restart_after_csrrx or MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc or WILL_FIRE_RL_rl_debug_run or csr_regfile$read_dpc) @@ -2994,9 +3218,9 @@ module mkCPU(CLK, case (1'b1) // synopsys parallel_case MUX_imem_rg_f3$write_1__SEL_1: imem_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0]; - MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h12499; + MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h12405; WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_pc$D_IN = x_out_next_pc__h12499; + imem_rg_pc$D_IN = x_out_next_pc__h12405; MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc; WILL_FIRE_RL_rl_debug_run: imem_rg_pc$D_IN = csr_regfile$read_dpc; default: imem_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; @@ -3061,25 +3285,25 @@ module mkCPU(CLK, always@(MUX_imem_rg_f3$write_1__SEL_1 or soc_map$m_pc_reset_value or MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h12499 or + x_out_next_pc__h12405 or WILL_FIRE_RL_rl_stage1_restart_after_csrrx or MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc or WILL_FIRE_RL_rl_debug_run or csr_regfile$read_dpc or - WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h14311) + WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h14217) begin case (1'b1) // synopsys parallel_case MUX_imem_rg_f3$write_1__SEL_1: imem_rg_tval$D_IN = soc_map$m_pc_reset_value[31:0]; MUX_imem_rg_f3$write_1__SEL_2: - imem_rg_tval$D_IN = x_out_next_pc__h12499; + imem_rg_tval$D_IN = x_out_next_pc__h12405; WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_tval$D_IN = x_out_next_pc__h12499; + imem_rg_tval$D_IN = x_out_next_pc__h12405; MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc; WILL_FIRE_RL_rl_debug_run: imem_rg_tval$D_IN = csr_regfile$read_dpc; WILL_FIRE_RL_imem_rl_fetch_next_32b: - imem_rg_tval$D_IN = next_pc___1__h14311; + imem_rg_tval$D_IN = next_pc___1__h14217; default: imem_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end @@ -3115,7 +3339,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_reset_start ; // register rg_mstatus_MXR @@ -3123,21 +3347,21 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_interrupt ? csr_regfile$csr_trap_actions[53] : csr_regfile$read_mstatus[19] ; - assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_9 ; + assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_10 ; // register rg_next_pc always@(WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions or MUX_rg_cur_priv$write_1__SEL_2 or csr_regfile$csr_trap_actions or - MUX_f_trace_data$enq_1__SEL_4 or x_out_next_pc__h12499) + MUX_f_trace_data$enq_1__SEL_4 or x_out_next_pc__h12405) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_rl_stage1_xRET: rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34]; MUX_rg_cur_priv$write_1__SEL_2: rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66]; - MUX_f_trace_data$enq_1__SEL_4: rg_next_pc$D_IN = x_out_next_pc__h12499; + MUX_f_trace_data$enq_1__SEL_4: rg_next_pc$D_IN = x_out_next_pc__h12405; default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end @@ -3145,7 +3369,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || WILL_FIRE_RL_rl_stage1_FENCE_I || @@ -3167,7 +3391,7 @@ module mkCPU(CLK, assign rg_sstatus_SUM$D_IN = WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$csr_trap_actions[52] ; - assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_9 ; + assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_10 ; // register rg_start_CPI_cycles assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ; @@ -3190,10 +3414,11 @@ module mkCPU(CLK, MUX_rg_state$write_1__VAL_3 or MUX_rg_state$write_1__SEL_4 or WILL_FIRE_RL_rl_reset_start or - MUX_rg_state$write_1__SEL_6 or + MUX_csr_regfile$write_dpc_1__SEL_2 or WILL_FIRE_RL_rl_BREAK_cache_flush_finish or - MUX_rg_state$write_1__SEL_8 or - MUX_rg_state$write_1__SEL_9 or + MUX_imem_rg_f3$write_1__SEL_3 or + WILL_FIRE_RL_rl_stage2_nonpipe or + MUX_rg_state$write_1__SEL_10 or WILL_FIRE_RL_rl_stage1_FENCE_I or WILL_FIRE_RL_rl_stage1_FENCE or WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI) @@ -3207,14 +3432,15 @@ module mkCPU(CLK, rg_state$D_IN = MUX_rg_state$write_1__VAL_3; MUX_rg_state$write_1__SEL_4: rg_state$D_IN = 4'd0; WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1; - MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd2; + MUX_csr_regfile$write_dpc_1__SEL_2: rg_state$D_IN = 4'd2; WILL_FIRE_RL_rl_BREAK_cache_flush_finish: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_8: rg_state$D_IN = 4'd4; - MUX_rg_state$write_1__SEL_9: rg_state$D_IN = 4'd6; - WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd8; - WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd10; - WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd11; + MUX_imem_rg_f3$write_1__SEL_3: rg_state$D_IN = 4'd4; + WILL_FIRE_RL_rl_stage2_nonpipe: rg_state$D_IN = 4'd5; + MUX_rg_state$write_1__SEL_10: rg_state$D_IN = 4'd6; + WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd9; + WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd10; + WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd11; + WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd12; default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; endcase end @@ -3235,10 +3461,11 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_finish_FENCE || WILL_FIRE_RL_rl_finish_FENCE_I || WILL_FIRE_RL_rl_stage1_restart_after_csrrx || + WILL_FIRE_RL_rl_stage2_nonpipe || WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_FENCE_I || WILL_FIRE_RL_rl_stage1_FENCE || WILL_FIRE_RL_rl_stage1_SFENCE_VMA || @@ -3261,6 +3488,21 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_stop || WILL_FIRE_RL_rl_reset_start || WILL_FIRE_RL_rl_debug_halt ; + // register rg_trap_info + assign rg_trap_info$D_IN = + { stage2_rg_stage2[401:370], + near_mem$dmem_exc_code, + stage2_rg_stage2[329:298] } ; + assign rg_trap_info$EN = CAN_FIRE_RL_rl_stage2_nonpipe ; + + // register rg_trap_instr + assign rg_trap_instr$D_IN = stage2_rg_stage2[369:338] ; + assign rg_trap_instr$EN = CAN_FIRE_RL_rl_stage2_nonpipe ; + + // register rg_trap_trace_data + assign rg_trap_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_1 ; + assign rg_trap_trace_data$EN = CAN_FIRE_RL_rl_stage2_nonpipe ; + // register stage1_rg_full always@(WILL_FIRE_RL_stage1_rl_reset or WILL_FIRE_RL_rl_stage1_interrupt or @@ -3270,7 +3512,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_finish_SFENCE_VMA or WILL_FIRE_RL_rl_finish_FENCE_I or WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_stage2_nonpipe or + WILL_FIRE_RL_rl_trap or WILL_FIRE_RL_rl_pipe or MUX_stage1_rg_full$write_1__VAL_10 or MUX_imem_rg_f3$write_1__SEL_1 or @@ -3285,7 +3527,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_finish_FENCE_I || WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0; + WILL_FIRE_RL_rl_trap: stage1_rg_full$D_IN = 1'd0; WILL_FIRE_RL_rl_pipe: stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_10; MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1; @@ -3300,7 +3542,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_stage1_rl_reset || WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_trap_fetch || @@ -3312,12 +3554,12 @@ module mkCPU(CLK, // register stage2_rg_full always@(stage2_f_reset_reqs$EMPTY_N or - WILL_FIRE_RL_rl_stage2_nonpipe or + WILL_FIRE_RL_rl_trap or WILL_FIRE_RL_rl_pipe or MUX_stage2_rg_full$write_1__VAL_3 or MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_debug_run) case (1'b1) - stage2_f_reset_reqs$EMPTY_N || WILL_FIRE_RL_rl_stage2_nonpipe: + stage2_f_reset_reqs$EMPTY_N || WILL_FIRE_RL_rl_trap: stage2_rg_full$D_IN = 1'd0; WILL_FIRE_RL_rl_pipe: stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_3; @@ -3329,7 +3571,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || WILL_FIRE_RL_rl_pipe || WILL_FIRE_RL_rl_debug_run || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || stage2_f_reset_reqs$EMPTY_N ; // register stage2_rg_resetting @@ -3341,12 +3583,12 @@ module mkCPU(CLK, assign stage2_rg_stage2$D_IN = { rg_cur_priv, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831, - x_out_data_to_stage2_rd__h12531, - x_out_data_to_stage2_addr__h12532, - x_out_data_to_stage2_val1__h12533, - x_out_data_to_stage2_val2__h12534, + x_out_data_to_stage2_rd__h12437, + x_out_data_to_stage2_addr__h12438, + x_out_data_to_stage2_val1__h12439, + x_out_data_to_stage2_val2__h12440, IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d1240 } ; assign stage2_rg_stage2$EN = WILL_FIRE_RL_rl_pipe && @@ -3380,20 +3622,20 @@ module mkCPU(CLK, stage2_rg_stage2[403:402], stage2_rg_stage2[337:335] == 3'd0 || IF_stage2_rg_stage2_4_BITS_337_TO_335_5_EQ_1_7_ETC___d147, - x_out_data_to_stage3_rd__h6556, - x_out_data_to_stage3_rd_val__h6557 } ; + x_out_data_to_stage3_rd__h6462, + x_out_data_to_stage3_rd_val__h6463 } ; assign stage3_rg_stage3$EN = MUX_f_trace_data$enq_1__SEL_1 ; // submodule csr_regfile assign csr_regfile$access_permitted_1_csr_addr = - x_out_data_to_stage2_instr__h12529[31:20] ; + x_out_data_to_stage2_instr__h12435[31:20] ; assign csr_regfile$access_permitted_1_priv = rg_cur_priv ; assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ; assign csr_regfile$access_permitted_2_csr_addr = - x_out_data_to_stage2_instr__h12529[31:20] ; + x_out_data_to_stage2_instr__h12435[31:20] ; assign csr_regfile$access_permitted_2_priv = rg_cur_priv ; assign csr_regfile$access_permitted_2_read_not_write = - rs1_val__h20813 == 32'd0 ; + rs1_val__h20863 == 32'd0 ; assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ; assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ; always@(IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752) @@ -3404,21 +3646,21 @@ module mkCPU(CLK, default: csr_regfile$csr_ret_actions_from_priv = 2'b0; endcase end - always@(WILL_FIRE_RL_rl_stage2_nonpipe or - near_mem$dmem_exc_code or - WILL_FIRE_RL_rl_stage1_interrupt or - MUX_csr_regfile$csr_trap_actions_5__VAL_2 or - WILL_FIRE_RL_rl_stage1_trap or x_out_trap_info_exc_code__h14151) + always@(WILL_FIRE_RL_rl_stage1_interrupt or + MUX_csr_regfile$csr_trap_actions_5__VAL_1 or + WILL_FIRE_RL_rl_stage1_trap or + x_out_trap_info_exc_code__h14057 or + WILL_FIRE_RL_rl_trap or rg_trap_info) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_exc_code = near_mem$dmem_exc_code; WILL_FIRE_RL_rl_stage1_interrupt: csr_regfile$csr_trap_actions_exc_code = - MUX_csr_regfile$csr_trap_actions_5__VAL_2; + MUX_csr_regfile$csr_trap_actions_5__VAL_1; WILL_FIRE_RL_rl_stage1_trap: csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h14151; + x_out_trap_info_exc_code__h14057; + WILL_FIRE_RL_rl_trap: + csr_regfile$csr_trap_actions_exc_code = rg_trap_info[35:32]; default: csr_regfile$csr_trap_actions_exc_code = 4'b1010 /* unspecified value */ ; endcase @@ -3429,21 +3671,18 @@ module mkCPU(CLK, assign csr_regfile$csr_trap_actions_nmi = WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ; assign csr_regfile$csr_trap_actions_pc = - WILL_FIRE_RL_rl_stage2_nonpipe ? - stage2_rg_stage2[401:370] : - imem_rg_pc ; - always@(WILL_FIRE_RL_rl_stage2_nonpipe or - stage2_rg_stage2 or - WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_stage1_trap or value__h14199) + WILL_FIRE_RL_rl_trap ? rg_trap_info[67:36] : imem_rg_pc ; + always@(WILL_FIRE_RL_rl_stage1_interrupt or + WILL_FIRE_RL_rl_stage1_trap or + value__h14105 or WILL_FIRE_RL_rl_trap or rg_trap_info) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_xtval = stage2_rg_stage2[329:298]; WILL_FIRE_RL_rl_stage1_interrupt: csr_regfile$csr_trap_actions_xtval = 32'd0; WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_xtval = value__h14199; + csr_regfile$csr_trap_actions_xtval = value__h14105; + WILL_FIRE_RL_rl_trap: + csr_regfile$csr_trap_actions_xtval = rg_trap_info[31:0]; default: csr_regfile$csr_trap_actions_xtval = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -3455,16 +3694,16 @@ module mkCPU(CLK, assign csr_regfile$mav_csr_write_csr_addr = WILL_FIRE_RL_rl_debug_write_csr ? f_csr_reqs$D_OUT[43:32] : - x_out_data_to_stage2_instr__h12529[31:20] ; + x_out_data_to_stage2_instr__h12435[31:20] ; always@(MUX_csr_regfile$mav_csr_write_1__SEL_1 or - rs1_val__h20224 or + rs1_val__h20274 or MUX_csr_regfile$mav_csr_write_1__SEL_2 or MUX_csr_regfile$mav_csr_write_2__VAL_2 or WILL_FIRE_RL_rl_debug_write_csr or f_csr_reqs$D_OUT) begin case (1'b1) // synopsys parallel_case MUX_csr_regfile$mav_csr_write_1__SEL_1: - csr_regfile$mav_csr_write_word = rs1_val__h20224; + csr_regfile$mav_csr_write_word = rs1_val__h20274; MUX_csr_regfile$mav_csr_write_1__SEL_2: csr_regfile$mav_csr_write_word = MUX_csr_regfile$mav_csr_write_2__VAL_2; @@ -3477,7 +3716,7 @@ module mkCPU(CLK, assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ; assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ; assign csr_regfile$read_csr_csr_addr = - x_out_data_to_stage2_instr__h12529[31:20] ; + x_out_data_to_stage2_instr__h12435[31:20] ; assign csr_regfile$read_csr_port2_csr_addr = f_csr_reqs$D_OUT[43:32] ; assign csr_regfile$s_external_interrupt_req_set_not_clear = s_external_interrupt_req_set_not_clear ; @@ -3521,12 +3760,9 @@ module mkCPU(CLK, csr_regfile$access_permitted_1 || WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h12529[19:15] != 5'd0 || + x_out_data_to_stage2_instr__h12435[19:15] != 5'd0 || WILL_FIRE_RL_rl_debug_write_csr ; - assign csr_regfile$EN_csr_trap_actions = - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap ; + assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_2 ; assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ; assign csr_regfile$EN_csr_minstret_incr = WILL_FIRE_RL_rl_pipe && @@ -3540,7 +3776,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_FENCE || WILL_FIRE_RL_rl_stage1_FENCE_I || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; assign csr_regfile$EN_write_dpc = WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset || @@ -3613,10 +3849,7 @@ module mkCPU(CLK, // submodule f_reset_reqs assign f_reset_reqs$D_IN = hart0_server_reset_request_put ; assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = - gpr_regfile$RDY_server_reset_request_put && - near_mem_RDY_server_reset_request_put__038_AND_ETC___d1050 && - rg_state == 4'd0 ; + assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset_start ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps @@ -3658,7 +3891,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_reset_start or WILL_FIRE_RL_rl_stage1_mip_cmd or MUX_f_trace_data$enq_1__VAL_6 or - WILL_FIRE_RL_rl_stage2_nonpipe or + WILL_FIRE_RL_rl_trap or MUX_f_trace_data$enq_1__VAL_7 or WILL_FIRE_RL_rl_stage1_xRET or MUX_f_trace_data$enq_1__VAL_8 or @@ -3681,8 +3914,7 @@ module mkCPU(CLK, 234'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; WILL_FIRE_RL_rl_stage1_mip_cmd: f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_6; - WILL_FIRE_RL_rl_stage2_nonpipe: - f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_7; + WILL_FIRE_RL_rl_trap: f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_7; WILL_FIRE_RL_rl_stage1_xRET: f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_8; WILL_FIRE_RL_rl_stage1_trap: @@ -3707,7 +3939,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_SFENCE_VMA || WILL_FIRE_RL_rl_reset_start || WILL_FIRE_RL_rl_stage1_mip_cmd || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_interrupt ; @@ -3716,14 +3948,14 @@ module mkCPU(CLK, // submodule gpr_regfile assign gpr_regfile$read_rs1_port2_rs1 = f_gpr_reqs$D_OUT[36:32] ; - assign gpr_regfile$read_rs1_rs1 = _theResult____h4437[19:15] ; - assign gpr_regfile$read_rs2_rs2 = _theResult____h4437[24:20] ; + assign gpr_regfile$read_rs1_rs1 = _theResult____h4320[19:15] ; + assign gpr_regfile$read_rs2_rs2 = _theResult____h4320[24:20] ; always@(WILL_FIRE_RL_rl_debug_write_gpr or f_gpr_reqs$D_OUT or MUX_gpr_regfile$write_rd_1__SEL_1 or stage3_rg_stage3 or MUX_csr_regfile$mav_csr_write_1__SEL_1 or - MUX_f_trace_data$enq_1__SEL_3 or x_out_data_to_stage2_instr__h12529) + MUX_f_trace_data$enq_1__SEL_3 or x_out_data_to_stage2_instr__h12435) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_rl_debug_write_gpr: @@ -3731,7 +3963,7 @@ module mkCPU(CLK, MUX_gpr_regfile$write_rd_1__SEL_1: gpr_regfile$write_rd_rd = stage3_rg_stage3[36:32]; MUX_csr_regfile$mav_csr_write_1__SEL_1 || MUX_f_trace_data$enq_1__SEL_3: - gpr_regfile$write_rd_rd = x_out_data_to_stage2_instr__h12529[11:7]; + gpr_regfile$write_rd_rd = x_out_data_to_stage2_instr__h12435[11:7]; default: gpr_regfile$write_rd_rd = 5'b01010 /* unspecified value */ ; endcase end @@ -3770,17 +4002,15 @@ module mkCPU(CLK, assign near_mem$dmem_master_awready = dmem_master_awready ; assign near_mem$dmem_master_bid = dmem_master_bid ; assign near_mem$dmem_master_bresp = dmem_master_bresp ; - assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; assign near_mem$dmem_master_rdata = dmem_master_rdata ; assign near_mem$dmem_master_rid = dmem_master_rid ; assign near_mem$dmem_master_rlast = dmem_master_rlast ; assign near_mem$dmem_master_rresp = dmem_master_rresp ; - assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; assign near_mem$dmem_master_wready = dmem_master_wready ; - assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h12532 ; + assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h12438 ; assign near_mem$dmem_req_amo_funct7 = - x_out_data_to_stage2_val1__h12533[6:0] ; - assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h12529[14:12] ; + x_out_data_to_stage2_val1__h12439[6:0] ; + assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h12435[14:12] ; assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ; always@(IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831) begin @@ -3797,24 +4027,22 @@ module mkCPU(CLK, assign near_mem$dmem_req_satp = csr_regfile$read_satp ; assign near_mem$dmem_req_sstatus_SUM = 1'd0 ; assign near_mem$dmem_req_store_value = - { 32'd0, x_out_data_to_stage2_val2__h12534 } ; + { 32'd0, x_out_data_to_stage2_val2__h12440 } ; assign near_mem$imem_master_arready = imem_master_arready ; assign near_mem$imem_master_awready = imem_master_awready ; assign near_mem$imem_master_bid = imem_master_bid ; assign near_mem$imem_master_bresp = imem_master_bresp ; - assign near_mem$imem_master_bvalid = imem_master_bvalid ; assign near_mem$imem_master_rdata = imem_master_rdata ; assign near_mem$imem_master_rid = imem_master_rid ; assign near_mem$imem_master_rlast = imem_master_rlast ; assign near_mem$imem_master_rresp = imem_master_rresp ; - assign near_mem$imem_master_rvalid = imem_master_rvalid ; assign near_mem$imem_master_wready = imem_master_wready ; always@(MUX_imem_rg_f3$write_1__SEL_1 or MUX_near_mem$imem_req_2__VAL_1 or MUX_imem_rg_f3$write_1__SEL_2 or MUX_near_mem$imem_req_2__VAL_2 or WILL_FIRE_RL_imem_rl_fetch_next_32b or - next_pc___1__h14311 or + next_pc___1__h14217 or WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap_fetch or MUX_near_mem$imem_req_2__VAL_5 or @@ -3827,7 +4055,7 @@ module mkCPU(CLK, MUX_imem_rg_f3$write_1__SEL_2: near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_addr = next_pc___1__h14311; + near_mem$imem_req_addr = next_pc___1__h14217; WILL_FIRE_RL_rl_stage1_restart_after_csrrx: near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; WILL_FIRE_RL_rl_trap_fetch: @@ -3915,6 +4143,8 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_finish_FENCE || WILL_FIRE_RL_rl_finish_FENCE_I || WILL_FIRE_RL_rl_debug_run ; + assign near_mem$imem_master_bvalid = imem_master_bvalid ; + assign near_mem$imem_master_rvalid = imem_master_rvalid ; assign near_mem$EN_dmem_req = WILL_FIRE_RL_rl_pipe && near_mem_imem_exc__91_OR_IF_IF_NOT_near_mem_im_ETC___d1194 && @@ -3926,6 +4156,8 @@ module mkCPU(CLK, 3'd2 || IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831 == 3'd4) ; + assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; + assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; assign near_mem$EN_server_fence_i_request_put = WILL_FIRE_RL_rl_stage1_stop || WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode || @@ -3933,9 +4165,9 @@ module mkCPU(CLK, assign near_mem$EN_server_fence_i_response_get = WILL_FIRE_RL_rl_BREAK_cache_flush_finish || WILL_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_11 ; + assign near_mem$EN_server_fence_request_put = CAN_FIRE_RL_rl_stage1_FENCE ; assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ; - assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_12 ; + assign near_mem$EN_sfence_vma = CAN_FIRE_RL_rl_stage1_SFENCE_VMA ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; @@ -3963,10 +4195,10 @@ module mkCPU(CLK, assign stage2_f_reset_rsps$CLR = 1'b0 ; // submodule stage2_mbox - assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h12529[14:12] ; - assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4437[3] ; - assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h12533 ; - assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h12534 ; + assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h12435[14:12] ; + assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4320[3] ; + assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h12439 ; + assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h12440 ; assign stage2_mbox$set_verbosity_verbosity = 4'h0 ; assign stage2_mbox$EN_set_verbosity = 1'b0 ; assign stage2_mbox$EN_req_reset = 1'b0 ; @@ -4015,12 +4247,12 @@ module mkCPU(CLK, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d639) && stage1_rg_full ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1221 = - ((_theResult____h4437[6:0] == 7'b0010011 || - _theResult____h4437[6:0] == 7'b0110011) && - (_theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101)) ? - _theResult____h12797 : - CASE_theResult__437_BITS_6_TO_0_0b10011_rd_val_ETC__q18 ; + ((_theResult____h4320[6:0] == 7'b0010011 || + _theResult____h4320[6:0] == 7'b0110011) && + (_theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101)) ? + _theResult____h12703 : + CASE_theResult__320_BITS_6_TO_0_0b10011_rd_val_ETC__q18 ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1286 = (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) && @@ -4040,74 +4272,74 @@ module mkCPU(CLK, NOT_near_mem_imem_valid_02_OR_NOT_near_mem_ime_ETC___d1148) && stage1_rg_full ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d529 = - rs1_val_bypassed__h4445 == rs2_val__h12631 ; + rs1_val_bypassed__h4328 == rs2_val__h12537 ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d531 = - (rs1_val_bypassed__h4445 ^ 32'h80000000) < - (rs2_val__h12631 ^ 32'h80000000) ; + (rs1_val_bypassed__h4328 ^ 32'h80000000) < + (rs2_val__h12537 ^ 32'h80000000) ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533 = - rs1_val_bypassed__h4445 < rs2_val__h12631 ; + rs1_val_bypassed__h4328 < rs2_val__h12537 ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - (_theResult____h4437[6:0] == 7'b1100011) ? - _theResult____h4437[14:12] != 3'b0 && - _theResult____h4437[14:12] != 3'b001 && - _theResult____h4437[14:12] != 3'b100 && - _theResult____h4437[14:12] != 3'b101 && - _theResult____h4437[14:12] != 3'b110 && - _theResult____h4437[14:12] != 3'b111 || + (_theResult____h4320[6:0] == 7'b1100011) ? + _theResult____h4320[14:12] != 3'b0 && + _theResult____h4320[14:12] != 3'b001 && + _theResult____h4320[14:12] != 3'b100 && + _theResult____h4320[14:12] != 3'b101 && + _theResult____h4320[14:12] != 3'b110 && + _theResult____h4320[14:12] != 3'b111 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 : - (_theResult____h4437[6:0] != 7'b0110011 || - _theResult____h4437[31:25] != 7'b0000001) && - (((_theResult____h4437[6:0] == 7'b0010011 || - _theResult____h4437[6:0] == 7'b0110011) && - (_theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101)) ? - _theResult____h4437[25] : - CASE_theResult__437_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9) ; + (_theResult____h4320[6:0] != 7'b0110011 || + _theResult____h4320[31:25] != 7'b0000001) && + (((_theResult____h4320[6:0] == 7'b0010011 || + _theResult____h4320[6:0] == 7'b0110011) && + (_theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101)) ? + _theResult____h4320[25] : + CASE_theResult__320_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9) ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d639 = - (_theResult____h4437[6:0] == 7'b1100011) ? - _theResult____h4437[14:12] != 3'b0 && - _theResult____h4437[14:12] != 3'b001 && - _theResult____h4437[14:12] != 3'b100 && - _theResult____h4437[14:12] != 3'b101 && - _theResult____h4437[14:12] != 3'b110 && - _theResult____h4437[14:12] != 3'b111 || + (_theResult____h4320[6:0] == 7'b1100011) ? + _theResult____h4320[14:12] != 3'b0 && + _theResult____h4320[14:12] != 3'b001 && + _theResult____h4320[14:12] != 3'b100 && + _theResult____h4320[14:12] != 3'b101 && + _theResult____h4320[14:12] != 3'b110 && + _theResult____h4320[14:12] != 3'b111 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634 : - _theResult____h4437[6:0] != 7'b1101111 && - _theResult____h4437[6:0] != 7'b1100111 ; + _theResult____h4320[6:0] != 7'b1101111 && + _theResult____h4320[6:0] != 7'b1100111 ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - (_theResult____h4437[6:0] == 7'b1100011) ? - (_theResult____h4437[14:12] == 3'b0 || - _theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b100 || - _theResult____h4437[14:12] == 3'b101 || - _theResult____h4437[14:12] == 3'b110 || - _theResult____h4437[14:12] == 3'b111) && + (_theResult____h4320[6:0] == 7'b1100011) ? + (_theResult____h4320[14:12] == 3'b0 || + _theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b100 || + _theResult____h4320[14:12] == 3'b101 || + _theResult____h4320[14:12] == 3'b110 || + _theResult____h4320[14:12] == 3'b111) && IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634 : - _theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[31:25] == 7'b0000001 || - (((_theResult____h4437[6:0] == 7'b0010011 || - _theResult____h4437[6:0] == 7'b0110011) && - (_theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101)) ? - !_theResult____h4437[25] : - CASE_theResult__437_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11) ; + _theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[31:25] == 7'b0000001 || + (((_theResult____h4320[6:0] == 7'b0010011 || + _theResult____h4320[6:0] == 7'b0110011) && + (_theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101)) ? + !_theResult____h4320[25] : + CASE_theResult__320_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11) ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688 = - (_theResult____h4437[6:0] == 7'b1100011) ? - (_theResult____h4437[14:12] == 3'b0 || - _theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b100 || - _theResult____h4437[14:12] == 3'b101 || - _theResult____h4437[14:12] == 3'b110 || - _theResult____h4437[14:12] == 3'b111) && + (_theResult____h4320[6:0] == 7'b1100011) ? + (_theResult____h4320[14:12] == 3'b0 || + _theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b100 || + _theResult____h4320[14:12] == 3'b101 || + _theResult____h4320[14:12] == 3'b110 || + _theResult____h4320[14:12] == 3'b111) && IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 : - _theResult____h4437[6:0] == 7'b1101111 || - _theResult____h4437[6:0] == 7'b1100111 ; + _theResult____h4320[6:0] == 7'b1101111 || + _theResult____h4320[6:0] == 7'b1100111 ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d943 = - ((_theResult____h4437[6:0] == 7'b0010011 || - _theResult____h4437[6:0] == 7'b0110011) && - (_theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101)) ? - _theResult____h12797 : + ((_theResult____h4320[6:0] == 7'b0010011 || + _theResult____h4320[6:0] == 7'b0110011) && + (_theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101)) ? + _theResult____h12703 : IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 ; assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d696 = NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d570 ? @@ -4118,185 +4350,185 @@ module mkCPU(CLK, IF_stage2_rg_stage2_4_BITS_334_TO_330_54_EQ_0__ETC___d181 : 2'd0 ; assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d659 = - _theResult____h4437[14:12] == 3'b0 && - (_theResult____h4437[6:0] != 7'b0110011 || - !_theResult____h4437[30]) || - _theResult____h4437[14:12] == 3'b0 && - _theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[30] || - _theResult____h4437[14:12] == 3'b010 || - _theResult____h4437[14:12] == 3'b011 || - _theResult____h4437[14:12] == 3'b100 || - _theResult____h4437[14:12] == 3'b110 || - _theResult____h4437[14:12] == 3'b111 ; + _theResult____h4320[14:12] == 3'b0 && + (_theResult____h4320[6:0] != 7'b0110011 || + !_theResult____h4320[30]) || + _theResult____h4320[14:12] == 3'b0 && + _theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[30] || + _theResult____h4320[14:12] == 3'b010 || + _theResult____h4320[14:12] == 3'b011 || + _theResult____h4320[14:12] == 3'b100 || + _theResult____h4320[14:12] == 3'b110 || + _theResult____h4320[14:12] == 3'b111 ; assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875 = NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_ETC___d211 ? - next_pc___1__h14311 : - next_pc__h14309 ; + next_pc___1__h14217 : + next_pc__h14215 ; assign IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d1240 = - { CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19, - x__h18327, + { CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19, + x__h18233, near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482, - x__h18419, - x_out_data_to_stage2_trace_data_rd__h17725, - x__h18596, - rs2_val__h12631, - x_out_data_to_stage2_trace_data_word3__h17728, + x__h18325, + x_out_data_to_stage2_trace_data_rd__h17631, + x__h18502, + rs2_val__h12537, + x_out_data_to_stage2_trace_data_word3__h17634, 32'hAAAAAAAA } ; assign IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 = near_mem$imem_exc ? 4'd11 : IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d750 ; - assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1367 = - csr_regfile$read_csr[31:0] | rs1_val__h20813 ; + assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1375 = + csr_regfile$read_csr[31:0] | rs1_val__h20863 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d443 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:10] == 6'b100011 && - instr__h4435[6:5] == 2'b0) ? - instr__h12063 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[15:12] == 4'b1001 && - instr__h4435[11:7] == 5'd0 && - instr__h4435[6:2] == 5'd0) ? - instr__h12401 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:10] == 6'b100011 && + instr__h4318[6:5] == 2'b0) ? + instr__h11969 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[15:12] == 4'b1001 && + instr__h4318[11:7] == 5'd0 && + instr__h4318[6:2] == 5'd0) ? + instr__h12307 : 32'h0) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d445 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:10] == 6'b100011 && - instr__h4435[6:5] == 2'b10) ? - instr__h11791 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:10] == 6'b100011 && - instr__h4435[6:5] == 2'b01) ? - instr__h11927 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:10] == 6'b100011 && + instr__h4318[6:5] == 2'b10) ? + instr__h11697 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:10] == 6'b100011 && + instr__h4318[6:5] == 2'b01) ? + instr__h11833 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d443) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d447 = (csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d314 && - instr__h4435[6:2] != 5'd0) ? - instr__h11560 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:10] == 6'b100011 && - instr__h4435[6:5] == 2'b11) ? - instr__h11655 : + instr__h4318[6:2] != 5'd0) ? + instr__h11466 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:10] == 6'b100011 && + instr__h4318[6:5] == 2'b11) ? + instr__h11561 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d445) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d448 = (csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d308 && - instr__h4435[6:2] != 5'd0) ? - instr__h11441 : + instr__h4318[6:2] != 5'd0) ? + instr__h11347 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d447 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d450 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b100 && - instr__h4435[11:10] == 2'b01 && - imm6__h9587 != 6'd0 && - !instr__h4435[12]) ? - instr__h11146 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b100 && - instr__h4435[11:10] == 2'b10) ? - instr__h11263 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b100 && + instr__h4318[11:10] == 2'b01 && + imm6__h9493 != 6'd0 && + !instr__h4318[12]) ? + instr__h11052 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b100 && + instr__h4318[11:10] == 2'b10) ? + instr__h11169 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d448) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d451 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b100 && - instr__h4435[11:10] == 2'b0 && - imm6__h9587 != 6'd0 && - !instr__h4435[12]) ? - instr__h10953 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b100 && + instr__h4318[11:10] == 2'b0 && + imm6__h9493 != 6'd0 && + !instr__h4318[12]) ? + instr__h10859 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d450 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d452 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[15:13] == 3'b0 && - instr__h4435[11:7] != 5'd0 && - imm6__h9587 != 6'd0 && - !instr__h4435[12]) ? - instr__h10760 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[15:13] == 3'b0 && + instr__h4318[11:7] != 5'd0 && + imm6__h9493 != 6'd0 && + !instr__h4318[12]) ? + instr__h10666 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d451 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d454 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b011 && - instr__h4435[11:7] == 5'd2 && - nzimm10__h10211 != 10'd0) ? - instr__h10415 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b0 && - instr__h4435[15:13] == 3'b0 && - nzimm10__h10426 != 10'd0) ? - instr__h10587 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b011 && + instr__h4318[11:7] == 5'd2 && + nzimm10__h10117 != 10'd0) ? + instr__h10321 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b0 && + instr__h4318[15:13] == 3'b0 && + nzimm10__h10332 != 10'd0) ? + instr__h10493 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d452) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d455 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b0 && - instr__h4435[11:7] != 5'd0 && - imm6__h9587 != 6'd0 || - csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b0 && - instr__h4435[11:7] == 5'd0 && - imm6__h9587 == 6'd0) ? - instr__h9978 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b0 && + instr__h4318[11:7] != 5'd0 && + imm6__h9493 != 6'd0 || + csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b0 && + instr__h4318[11:7] == 5'd0 && + imm6__h9493 == 6'd0) ? + instr__h9884 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d454 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d456 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b011 && - instr__h4435[11:7] != 5'd0 && - instr__h4435[11:7] != 5'd2 && - imm6__h9587 != 6'd0) ? - instr__h9849 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b011 && + instr__h4318[11:7] != 5'd0 && + instr__h4318[11:7] != 5'd2 && + imm6__h9493 != 6'd0) ? + instr__h9755 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d455 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d458 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b111) ? - instr__h9327 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b010 && - instr__h4435[11:7] != 5'd0) ? - instr__h9665 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b111) ? + instr__h9233 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b010 && + instr__h4318[11:7] != 5'd0) ? + instr__h9571 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d456) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d459 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b110) ? - instr__h9010 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b110) ? + instr__h8916 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d458 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d460 = (csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d314 && - instr__h4435[6:2] == 5'd0) ? - instr__h8945 : + instr__h4318[6:2] == 5'd0) ? + instr__h8851 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d459 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d461 = (csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d308 && - instr__h4435[6:2] == 5'd0) ? - instr__h8829 : + instr__h4318[6:2] == 5'd0) ? + instr__h8735 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d460 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d462 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b001) ? - instr__h8439 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b001) ? + instr__h8345 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d461 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d463 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b101) ? - instr__h8096 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b101) ? + instr__h8002 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d462 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d464 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b0 && - instr__h4435[15:13] == 3'b110) ? - instr__h7867 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b0 && + instr__h4318[15:13] == 3'b110) ? + instr__h7773 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d463 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d465 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b0 && - instr__h4435[15:13] == 3'b010) ? - instr__h7672 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b0 && + instr__h4318[15:13] == 3'b010) ? + instr__h7578 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d464 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d466 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[15:13] == 3'b110) ? - instr__h7480 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[15:13] == 3'b110) ? + instr__h7386 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d465 ; assign IF_near_mem_dmem_valid__15_THEN_IF_near_mem_dm_ETC___d118 = near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ; assign IF_rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_E_ETC___d729 = ((rg_cur_priv == 2'b11 || rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) && - _theResult____h4437[31:20] == 12'b000100000010) ? + _theResult____h4320[31:20] == 12'b000100000010) ? 4'd8 : (rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_EQ_0_ETC___d727 ? 4'd10 : @@ -4310,9 +4542,9 @@ module mkCPU(CLK, CASE_stage2_rg_stage2_BITS_337_TO_335_0_2_1_IF_ETC__q2 : 2'd0 ; assign IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d470 = - x_out_bypass_rd__h6907 == _theResult____h4437[19:15] ; + x_out_bypass_rd__h6813 == _theResult____h4320[19:15] ; assign IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d472 = - x_out_bypass_rd__h6907 == _theResult____h4437[24:20] ; + x_out_bypass_rd__h6813 == _theResult____h4320[24:20] ; assign IF_stage2_rg_stage2_4_BITS_334_TO_330_54_EQ_0__ETC___d181 = (stage2_rg_stage2[334:330] == 5'd0) ? 2'd0 : @@ -4320,19 +4552,19 @@ module mkCPU(CLK, assign IF_stage2_rg_stage2_4_BITS_337_TO_335_5_EQ_3_0_ETC___d121 = stage2_mbox$valid ? 2'd2 : 2'd1 ; assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d570 = - (_theResult____h4437[14:12] != 3'b0 || - _theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[30]) && - (_theResult____h4437[14:12] != 3'b0 || - _theResult____h4437[6:0] != 7'b0110011 || - !_theResult____h4437[30]) && - _theResult____h4437[14:12] != 3'b010 && - _theResult____h4437[14:12] != 3'b011 && - _theResult____h4437[14:12] != 3'b100 && - _theResult____h4437[14:12] != 3'b110 && - _theResult____h4437[14:12] != 3'b111 ; + (_theResult____h4320[14:12] != 3'b0 || + _theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[30]) && + (_theResult____h4320[14:12] != 3'b0 || + _theResult____h4320[6:0] != 7'b0110011 || + !_theResult____h4320[30]) && + _theResult____h4320[14:12] != 3'b010 && + _theResult____h4320[14:12] != 3'b011 && + _theResult____h4320[14:12] != 3'b100 && + _theResult____h4320[14:12] != 3'b110 && + _theResult____h4320[14:12] != 3'b111 ; assign NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 = - cur_verbosity__h3142 > 4'd1 ; + cur_verbosity__h2930 > 4'd1 ; assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1191 = !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || near_mem$imem_exc || @@ -4344,12 +4576,12 @@ module mkCPU(CLK, NOT_near_mem_imem_valid_02_OR_NOT_near_mem_ime_ETC___d1148) && (!stage1_rg_full || NOT_near_mem_imem_valid_02_OR_NOT_near_mem_ime_ETC___d1135) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1321 = + assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1329 = !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || !near_mem$imem_exc && (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) ; - assign NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1319 = + assign NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1327 = !near_mem$imem_exc && (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) || @@ -4392,7 +4624,7 @@ module mkCPU(CLK, 3'd2 && IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831 != 3'd3 ; - assign NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1491 = + assign NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1499 = (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && @@ -4465,12 +4697,12 @@ module mkCPU(CLK, near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691 || !stage1_rg_full) ; assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d884 = - { {20{theResult__437_BITS_31_TO_20__q17[11]}}, - theResult__437_BITS_31_TO_20__q17 } ; + { {20{theResult__320_BITS_31_TO_20__q17[11]}}, + theResult__320_BITS_31_TO_20__q17 } ; assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294 = - { {9{offset__h8043[11]}}, offset__h8043 } ; + { {9{offset__h7949[11]}}, offset__h7949 } ; assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323 = - { {4{offset__h8954[8]}}, offset__h8954 } ; + { {4{offset__h8860[8]}}, offset__h8860 } ; assign _0_OR_0_OR_near_mem_imem_exc__91_OR_IF_IF_NOT_n_ETC___d1274 = near_mem$imem_exc || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 && @@ -4496,69 +4728,69 @@ module mkCPU(CLK, 2'd0) && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691 || !stage1_rg_full ; - assign _theResult_____1_fst__h13636 = - (_theResult____h4437[14:12] == 3'b0 && - _theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[30]) ? - rd_val___1__h13632 : - _theResult_____1_fst__h13643 ; - assign _theResult_____1_fst__h13671 = - rs1_val_bypassed__h4445 & _theResult___snd__h14769 ; - assign _theResult____h12797 = - (_theResult____h4437[14:12] == 3'b001) ? - rd_val__h14665 : - (_theResult____h4437[30] ? rd_val__h14739 : rd_val__h14717) ; - assign _theResult____h27350 = - (delta_CPI_instrs__h27349 == 64'd0) ? - delta_CPI_instrs___1__h27385 : - delta_CPI_instrs__h27349 ; - assign _theResult____h4437 = x_out_data_to_stage2_instr__h12529 ; - assign _theResult___fst__h7235 = + assign _theResult_____1_fst__h13542 = + (_theResult____h4320[14:12] == 3'b0 && + _theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[30]) ? + rd_val___1__h13538 : + _theResult_____1_fst__h13549 ; + assign _theResult_____1_fst__h13577 = + rs1_val_bypassed__h4328 & _theResult___snd__h14675 ; + assign _theResult____h12703 = + (_theResult____h4320[14:12] == 3'b001) ? + rd_val__h14571 : + (_theResult____h4320[30] ? rd_val__h14645 : rd_val__h14623) ; + assign _theResult____h27400 = + (delta_CPI_instrs__h27399 == 64'd0) ? + delta_CPI_instrs___1__h27435 : + delta_CPI_instrs__h27399 ; + assign _theResult____h4320 = x_out_data_to_stage2_instr__h12435 ; + assign _theResult___fst__h7141 = (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && imem_rg_pc[1:0] == 2'b0 && near_mem$imem_instr[1:0] != 2'b11) ? - instr_out___1__h7237 : - _theResult___fst__h7263 ; - assign _theResult___fst__h7263 = + instr_out___1__h7143 : + _theResult___fst__h7169 ; + assign _theResult___fst__h7169 = (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && imem_rg_pc[1:0] != 2'b0 && near_mem$imem_instr[17:16] != 2'b11) ? - instr_out___1__h7265 : + instr_out___1__h7171 : near_mem$imem_instr ; - assign _theResult___snd__h14769 = - (_theResult____h4437[6:0] == 7'b0010011) ? + assign _theResult___snd__h14675 = + (_theResult____h4320[6:0] == 7'b0010011) ? SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d884 : - rs2_val__h12631 ; - assign alu_outputs___1_addr__h12657 = + rs2_val__h12537 ; + assign alu_outputs___1_addr__h12563 = IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 ? - branch_target__h12635 : + branch_target__h12541 : IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875 ; - assign alu_outputs___1_addr__h12678 = + assign alu_outputs___1_addr__h12584 = imem_rg_pc + - { {11{theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q4[20]}}, - theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q4 } ; - assign alu_outputs___1_addr__h12704 = { eaddr__h12887[31:1], 1'd0 } ; - assign alu_outputs___1_exc_code__h13156 = - (_theResult____h4437[14:12] == 3'b0) ? - ((_theResult____h4437[11:7] == 5'd0 && - _theResult____h4437[19:15] == 5'd0) ? - CASE_theResult__437_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 : + { {11{theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q4[20]}}, + theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q4 } ; + assign alu_outputs___1_addr__h12610 = { eaddr__h12793[31:1], 1'd0 } ; + assign alu_outputs___1_exc_code__h13062 = + (_theResult____h4320[14:12] == 3'b0) ? + ((_theResult____h4320[11:7] == 5'd0 && + _theResult____h4320[19:15] == 5'd0) ? + CASE_theResult__320_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 : 4'd2) : 4'd2 ; - assign alu_outputs___1_trace_data_word3__h17603 = { 32'd0, eaddr__h12887 } ; - assign alu_outputs___1_trace_data_word3__h17622 = { 32'd0, eaddr__h12907 } ; - assign alu_outputs___1_val1__h13160 = - _theResult____h4437[14] ? - { 27'd0, _theResult____h4437[19:15] } : - rs1_val_bypassed__h4445 ; - assign alu_outputs___1_val1__h13181 = - { 25'd0, _theResult____h4437[31:25] } ; - assign branch_target__h12635 = + assign alu_outputs___1_trace_data_word3__h17509 = { 32'd0, eaddr__h12793 } ; + assign alu_outputs___1_trace_data_word3__h17528 = { 32'd0, eaddr__h12813 } ; + assign alu_outputs___1_val1__h13066 = + _theResult____h4320[14] ? + { 27'd0, _theResult____h4320[19:15] } : + rs1_val_bypassed__h4328 ; + assign alu_outputs___1_val1__h13087 = + { 25'd0, _theResult____h4320[31:25] } ; + assign branch_target__h12541 = imem_rg_pc + - { {19{theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q3[12]}}, - theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q3 } ; - assign cpi__h27352 = x__h27351 / 64'd10 ; - assign cpifrac__h27353 = x__h27351 % 64'd10 ; + { {19{theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q3[12]}}, + theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q3 } ; + assign cpi__h27402 = x__h27401 / 64'd10 ; + assign cpifrac__h27403 = x__h27401 % 64'd10 ; assign csr_regfile_csr_mip_read__089_EQ_rg_prev_mip_090___d1091 = csr_regfile$csr_mip_read == rg_prev_mip ; assign csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1116 = @@ -4566,180 +4798,180 @@ module mkCPU(CLK, stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1104 && IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1084 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1458 = + assign csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1466 = (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && rg_state == 4'd4 && stage1_rg_full_00_AND_near_mem_imem_valid_AND__ETC___d1087 && !stage3_rg_full && csr_regfile_csr_mip_read__089_EQ_rg_prev_mip_090___d1091 ; - assign csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1478 = - delta_CPI_cycles__h27348 * 64'd10 ; + assign csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1486 = + delta_CPI_cycles__h27398 * 64'd10 ; assign csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d308 = - csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[15:12] == 4'b1000 && - instr__h4435[11:7] != 5'd0 ; + csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[15:12] == 4'b1000 && + instr__h4318[11:7] != 5'd0 ; assign csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d314 = - csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[15:12] == 4'b1001 && - instr__h4435[11:7] != 5'd0 ; - assign cur_verbosity__h3142 = + csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[15:12] == 4'b1001 && + instr__h4318[11:7] != 5'd0 ; + assign cur_verbosity__h2930 = (csr_regfile$read_csr_minstret < cfg_logdelay) ? 4'd0 : cfg_verbosity ; - assign data_to_stage2_addr__h12523 = x_out_data_to_stage2_addr__h12532 ; - assign delta_CPI_cycles__h27348 = + assign data_to_stage2_addr__h12429 = x_out_data_to_stage2_addr__h12438 ; + assign delta_CPI_cycles__h27398 = csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ; - assign delta_CPI_instrs___1__h27385 = delta_CPI_instrs__h27349 + 64'd1 ; - assign delta_CPI_instrs__h27349 = + assign delta_CPI_instrs___1__h27435 = delta_CPI_instrs__h27399 + 64'd1 ; + assign delta_CPI_instrs__h27399 = csr_regfile$read_csr_minstret - rg_start_CPI_instrs ; - assign eaddr__h12887 = - rs1_val_bypassed__h4445 + + assign eaddr__h12793 = + rs1_val_bypassed__h4328 + SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d884 ; - assign eaddr__h12907 = - rs1_val_bypassed__h4445 + - { {20{theResult__437_BITS_31_TO_25_CONCAT_theResult__ETC__q7[11]}}, - theResult__437_BITS_31_TO_25_CONCAT_theResult__ETC__q7 } ; - assign fall_through_pc__h12486 = + assign eaddr__h12813 = + rs1_val_bypassed__h4328 + + { {20{theResult__320_BITS_31_TO_25_CONCAT_theResult__ETC__q7[11]}}, + theResult__320_BITS_31_TO_25_CONCAT_theResult__ETC__q7 } ; + assign fall_through_pc__h12392 = imem_rg_pc + (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482 ? 32'd4 : 32'd2) ; - assign imm12__h10213 = { {2{nzimm10__h10211[9]}}, nzimm10__h10211 } ; - assign imm12__h10428 = { 2'd0, nzimm10__h10426 } ; - assign imm12__h10624 = { 7'b0, instr__h4435[6:2] } ; - assign imm12__h10969 = { 7'b0100000, instr__h4435[6:2] } ; - assign imm12__h7336 = { 4'd0, offset__h7106 } ; - assign imm12__h7673 = { 5'd0, offset__h7615 } ; - assign imm12__h9589 = { {6{imm6__h9587[5]}}, imm6__h9587 } ; - assign imm20__h9717 = { {14{imm6__h9587[5]}}, imm6__h9587 } ; - assign imm6__h9587 = { instr__h4435[12], instr__h4435[6:2] } ; - assign instr___1__h7068 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[11:7] != 5'd0 && - instr__h4435[15:13] == 3'b010) ? - instr__h7335 : + assign imm12__h10119 = { {2{nzimm10__h10117[9]}}, nzimm10__h10117 } ; + assign imm12__h10334 = { 2'd0, nzimm10__h10332 } ; + assign imm12__h10530 = { 7'b0, instr__h4318[6:2] } ; + assign imm12__h10875 = { 7'b0100000, instr__h4318[6:2] } ; + assign imm12__h7242 = { 4'd0, offset__h7012 } ; + assign imm12__h7579 = { 5'd0, offset__h7521 } ; + assign imm12__h9495 = { {6{imm6__h9493[5]}}, imm6__h9493 } ; + assign imm20__h9623 = { {14{imm6__h9493[5]}}, imm6__h9493 } ; + assign imm6__h9493 = { instr__h4318[12], instr__h4318[6:2] } ; + assign instr___1__h6974 = + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[11:7] != 5'd0 && + instr__h4318[15:13] == 3'b010) ? + instr__h7241 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d466 ; - assign instr__h10415 = - { imm12__h10213, - instr__h4435[11:7], + assign instr__h10321 = + { imm12__h10119, + instr__h4318[11:7], 3'b0, - instr__h4435[11:7], + instr__h4318[11:7], 7'b0010011 } ; - assign instr__h10587 = { imm12__h10428, 8'd16, rd__h7675, 7'b0010011 } ; - assign instr__h10760 = - { imm12__h10624, - instr__h4435[11:7], + assign instr__h10493 = { imm12__h10334, 8'd16, rd__h7581, 7'b0010011 } ; + assign instr__h10666 = + { imm12__h10530, + instr__h4318[11:7], 3'b001, - instr__h4435[11:7], + instr__h4318[11:7], 7'b0010011 } ; - assign instr__h10953 = - { imm12__h10624, rs1__h7674, 3'b101, rs1__h7674, 7'b0010011 } ; - assign instr__h11146 = - { imm12__h10969, rs1__h7674, 3'b101, rs1__h7674, 7'b0010011 } ; - assign instr__h11263 = - { imm12__h9589, rs1__h7674, 3'b111, rs1__h7674, 7'b0010011 } ; - assign instr__h11441 = + assign instr__h10859 = + { imm12__h10530, rs1__h7580, 3'b101, rs1__h7580, 7'b0010011 } ; + assign instr__h11052 = + { imm12__h10875, rs1__h7580, 3'b101, rs1__h7580, 7'b0010011 } ; + assign instr__h11169 = + { imm12__h9495, rs1__h7580, 3'b111, rs1__h7580, 7'b0010011 } ; + assign instr__h11347 = { 7'b0, - instr__h4435[6:2], + instr__h4318[6:2], 8'd0, - instr__h4435[11:7], + instr__h4318[11:7], 7'b0110011 } ; - assign instr__h11560 = + assign instr__h11466 = { 7'b0, - instr__h4435[6:2], - instr__h4435[11:7], + instr__h4318[6:2], + instr__h4318[11:7], 3'b0, - instr__h4435[11:7], + instr__h4318[11:7], 7'b0110011 } ; - assign instr__h11655 = - { 7'b0, rd__h7675, rs1__h7674, 3'b111, rs1__h7674, 7'b0110011 } ; - assign instr__h11791 = - { 7'b0, rd__h7675, rs1__h7674, 3'b110, rs1__h7674, 7'b0110011 } ; - assign instr__h11927 = - { 7'b0, rd__h7675, rs1__h7674, 3'b100, rs1__h7674, 7'b0110011 } ; - assign instr__h12063 = + assign instr__h11561 = + { 7'b0, rd__h7581, rs1__h7580, 3'b111, rs1__h7580, 7'b0110011 } ; + assign instr__h11697 = + { 7'b0, rd__h7581, rs1__h7580, 3'b110, rs1__h7580, 7'b0110011 } ; + assign instr__h11833 = + { 7'b0, rd__h7581, rs1__h7580, 3'b100, rs1__h7580, 7'b0110011 } ; + assign instr__h11969 = { 7'b0100000, - rd__h7675, - rs1__h7674, + rd__h7581, + rs1__h7580, 3'b0, - rs1__h7674, + rs1__h7580, 7'b0110011 } ; - assign instr__h12401 = + assign instr__h12307 = { 12'b000000000001, - instr__h4435[11:7], + instr__h4318[11:7], 3'b0, - instr__h4435[11:7], + instr__h4318[11:7], 7'b1110011 } ; - assign instr__h4435 = + assign instr__h4318 = near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d203 ? - instr_out___1__h7205 : - _theResult___fst__h7235 ; - assign instr__h7335 = - { imm12__h7336, 8'd18, instr__h4435[11:7], 7'b0000011 } ; - assign instr__h7480 = + instr_out___1__h7111 : + _theResult___fst__h7141 ; + assign instr__h7241 = + { imm12__h7242, 8'd18, instr__h4318[11:7], 7'b0000011 } ; + assign instr__h7386 = { 4'd0, - instr__h4435[8:7], - instr__h4435[12], - instr__h4435[6:2], + instr__h4318[8:7], + instr__h4318[12], + instr__h4318[6:2], 8'd18, - offset_BITS_4_TO_0___h7604, + offset_BITS_4_TO_0___h7510, 7'b0100011 } ; - assign instr__h7672 = - { imm12__h7673, rs1__h7674, 3'b010, rd__h7675, 7'b0000011 } ; - assign instr__h7867 = + assign instr__h7578 = + { imm12__h7579, rs1__h7580, 3'b010, rd__h7581, 7'b0000011 } ; + assign instr__h7773 = { 5'd0, - instr__h4435[5], - instr__h4435[12], - rd__h7675, - rs1__h7674, + instr__h4318[5], + instr__h4318[12], + rd__h7581, + rs1__h7580, 3'b010, - offset_BITS_4_TO_0___h8035, + offset_BITS_4_TO_0___h7941, 7'b0100011 } ; - assign instr__h8096 = + assign instr__h8002 = { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[20], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[10:1], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[11], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[19:12], 12'd111 } ; - assign instr__h8439 = + assign instr__h8345 = { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[20], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[10:1], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[11], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[19:12], 12'd239 } ; - assign instr__h8829 = { 12'd0, instr__h4435[11:7], 15'd103 } ; - assign instr__h8945 = { 12'd0, instr__h4435[11:7], 15'd231 } ; - assign instr__h9010 = + assign instr__h8735 = { 12'd0, instr__h4318[11:7], 15'd103 } ; + assign instr__h8851 = { 12'd0, instr__h4318[11:7], 15'd231 } ; + assign instr__h8916 = { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[12], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[10:5], 5'd0, - rs1__h7674, + rs1__h7580, 3'b0, SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[4:1], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[11], 7'b1100011 } ; - assign instr__h9327 = + assign instr__h9233 = { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[12], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[10:5], 5'd0, - rs1__h7674, + rs1__h7580, 3'b001, SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[4:1], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[11], 7'b1100011 } ; - assign instr__h9665 = - { imm12__h9589, 8'd0, instr__h4435[11:7], 7'b0010011 } ; - assign instr__h9849 = { imm20__h9717, instr__h4435[11:7], 7'b0110111 } ; - assign instr__h9978 = - { imm12__h9589, - instr__h4435[11:7], + assign instr__h9571 = + { imm12__h9495, 8'd0, instr__h4318[11:7], 7'b0010011 } ; + assign instr__h9755 = { imm20__h9623, instr__h4318[11:7], 7'b0110111 } ; + assign instr__h9884 = + { imm12__h9495, + instr__h4318[11:7], 3'b0, - instr__h4435[11:7], + instr__h4318[11:7], 7'b0010011 } ; - assign instr_out___1__h7205 = + assign instr_out___1__h7111 = { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ; - assign instr_out___1__h7237 = { 16'b0, near_mem$imem_instr[15:0] } ; - assign instr_out___1__h7265 = { 16'b0, near_mem$imem_instr[31:16] } ; + assign instr_out___1__h7143 = { 16'b0, near_mem$imem_instr[15:0] } ; + assign instr_out___1__h7171 = { 16'b0, near_mem$imem_instr[31:16] } ; assign near_mem_RDY_server_reset_request_put__038_AND_ETC___d1050 = near_mem$RDY_server_reset_request_put && csr_regfile$RDY_server_reset_request_put && @@ -4869,7 +5101,7 @@ module mkCPU(CLK, imem_rg_pc[1:0] == 2'b0 && near_mem$imem_instr[1:0] != 2'b11 ; assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d203 = - near_mem$imem_pc == next_pc___1__h14311 ; + near_mem$imem_pc == next_pc___1__h14217 ; assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1104 = near_mem$imem_valid && near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d203 && @@ -4894,120 +5126,114 @@ module mkCPU(CLK, !near_mem$imem_exc && (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) ; - assign next_pc___1__h14311 = imem_rg_pc + 32'd2 ; - assign next_pc__h14309 = imem_rg_pc + 32'd4 ; - assign nzimm10__h10211 = - { instr__h4435[12], - instr__h4435[4:3], - instr__h4435[5], - instr__h4435[2], - instr__h4435[6], + assign next_pc___1__h14217 = imem_rg_pc + 32'd2 ; + assign next_pc__h14215 = imem_rg_pc + 32'd4 ; + assign nzimm10__h10117 = + { instr__h4318[12], + instr__h4318[4:3], + instr__h4318[5], + instr__h4318[2], + instr__h4318[6], 4'b0 } ; - assign nzimm10__h10426 = - { instr__h4435[10:7], - instr__h4435[12:11], - instr__h4435[5], - instr__h4435[6], + assign nzimm10__h10332 = + { instr__h4318[10:7], + instr__h4318[12:11], + instr__h4318[5], + instr__h4318[6], 2'b0 } ; - assign offset_BITS_4_TO_0___h7604 = { instr__h4435[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h8035 = - { instr__h4435[11:10], instr__h4435[6], 2'b0 } ; - assign offset__h7106 = - { instr__h4435[3:2], - instr__h4435[12], - instr__h4435[6:4], + assign offset_BITS_4_TO_0___h7510 = { instr__h4318[11:9], 2'b0 } ; + assign offset_BITS_4_TO_0___h7941 = + { instr__h4318[11:10], instr__h4318[6], 2'b0 } ; + assign offset__h7012 = + { instr__h4318[3:2], + instr__h4318[12], + instr__h4318[6:4], 2'b0 } ; - assign offset__h7615 = - { instr__h4435[5], instr__h4435[12:10], instr__h4435[6], 2'b0 } ; - assign offset__h8043 = - { instr__h4435[12], - instr__h4435[8], - instr__h4435[10:9], - instr__h4435[6], - instr__h4435[7], - instr__h4435[2], - instr__h4435[11], - instr__h4435[5:3], + assign offset__h7521 = + { instr__h4318[5], instr__h4318[12:10], instr__h4318[6], 2'b0 } ; + assign offset__h7949 = + { instr__h4318[12], + instr__h4318[8], + instr__h4318[10:9], + instr__h4318[6], + instr__h4318[7], + instr__h4318[2], + instr__h4318[11], + instr__h4318[5:3], 1'b0 } ; - assign offset__h8954 = - { instr__h4435[12], - instr__h4435[6:5], - instr__h4435[2], - instr__h4435[11:10], - instr__h4435[4:3], + assign offset__h8860 = + { instr__h4318[12], + instr__h4318[6:5], + instr__h4318[2], + instr__h4318[11:10], + instr__h4318[4:3], 1'b0 } ; - assign output_stage2___1_bypass_rd_val__h6896 = + assign output_stage2___1_bypass_rd_val__h6802 = (!near_mem$dmem_valid || !near_mem$dmem_exc) ? ((stage2_rg_stage2[334:330] == 5'd0) ? stage2_rg_stage2[297:266] : near_mem$dmem_word64[31:0]) : stage2_rg_stage2[297:266] ; - assign rd__h7675 = { 2'b01, instr__h4435[4:2] } ; - assign rd_val___1__h13624 = - rs1_val_bypassed__h4445 + _theResult___snd__h14769 ; - assign rd_val___1__h13632 = - rs1_val_bypassed__h4445 - _theResult___snd__h14769 ; - assign rd_val___1__h13639 = - ((rs1_val_bypassed__h4445 ^ 32'h80000000) < - (_theResult___snd__h14769 ^ 32'h80000000)) ? + assign rd__h7581 = { 2'b01, instr__h4318[4:2] } ; + assign rd_val___1__h13530 = + rs1_val_bypassed__h4328 + _theResult___snd__h14675 ; + assign rd_val___1__h13538 = + rs1_val_bypassed__h4328 - _theResult___snd__h14675 ; + assign rd_val___1__h13545 = + ((rs1_val_bypassed__h4328 ^ 32'h80000000) < + (_theResult___snd__h14675 ^ 32'h80000000)) ? 32'd1 : 32'd0 ; - assign rd_val___1__h13646 = - (rs1_val_bypassed__h4445 < _theResult___snd__h14769) ? + assign rd_val___1__h13552 = + (rs1_val_bypassed__h4328 < _theResult___snd__h14675) ? 32'd1 : 32'd0 ; - assign rd_val___1__h13653 = - rs1_val_bypassed__h4445 ^ _theResult___snd__h14769 ; - assign rd_val___1__h13660 = - rs1_val_bypassed__h4445 | _theResult___snd__h14769 ; - assign rd_val__h12443 = + assign rd_val___1__h13559 = + rs1_val_bypassed__h4328 ^ _theResult___snd__h14675 ; + assign rd_val___1__h13566 = + rs1_val_bypassed__h4328 | _theResult___snd__h14675 ; + assign rd_val__h12349 = (stage3_rg_full && stage3_rg_stage3[37] && - stage3_rg_stage3[36:32] == _theResult____h4437[24:20]) ? + stage3_rg_stage3[36:32] == _theResult____h4320[24:20]) ? stage3_rg_stage3[31:0] : gpr_regfile$read_rs2 ; - assign rd_val__h12836 = - (_theResult____h4437[14:12] == 3'b0 && - (_theResult____h4437[6:0] != 7'b0110011 || - !_theResult____h4437[30])) ? - rd_val___1__h13624 : - _theResult_____1_fst__h13636 ; - assign rd_val__h12853 = { _theResult____h4437[31:12], 12'h0 } ; - assign rd_val__h12869 = imem_rg_pc + rd_val__h12853 ; - assign rd_val__h14665 = rs1_val_bypassed__h4445 << shamt__h12793 ; - assign rd_val__h14717 = rs1_val_bypassed__h4445 >> shamt__h12793 ; - assign rd_val__h14739 = - rs1_val_bypassed__h4445 >> shamt__h12793 | - ~(32'hFFFFFFFF >> shamt__h12793) & - {32{rs1_val_bypassed__h4445[31]}} ; - assign rd_val__h7020 = + assign rd_val__h12742 = + (_theResult____h4320[14:12] == 3'b0 && + (_theResult____h4320[6:0] != 7'b0110011 || + !_theResult____h4320[30])) ? + rd_val___1__h13530 : + _theResult_____1_fst__h13542 ; + assign rd_val__h12759 = { _theResult____h4320[31:12], 12'h0 } ; + assign rd_val__h12775 = imem_rg_pc + rd_val__h12759 ; + assign rd_val__h14571 = rs1_val_bypassed__h4328 << shamt__h12699 ; + assign rd_val__h14623 = rs1_val_bypassed__h4328 >> shamt__h12699 ; + assign rd_val__h14645 = + rs1_val_bypassed__h4328 >> shamt__h12699 | + ~(32'hFFFFFFFF >> shamt__h12699) & + {32{rs1_val_bypassed__h4328[31]}} ; + assign rd_val__h6926 = (stage3_rg_full && stage3_rg_stage3[37] && - stage3_rg_stage3[36:32] == _theResult____h4437[19:15]) ? + stage3_rg_stage3[36:32] == _theResult____h4320[19:15]) ? stage3_rg_stage3[31:0] : gpr_regfile$read_rs1 ; assign rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_EQ_0_ETC___d727 = (rg_cur_priv == 2'b11 || rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] || rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) && - _theResult____h4437[31:20] == 12'b000100000101 ; - assign rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 = + _theResult____h4320[31:20] == 12'b000100000101 ; + assign rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 = rg_state == 4'd4 && - NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1319 && + NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1327 && csr_regfile_csr_mip_read__089_EQ_rg_prev_mip_090___d1091 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1321 && + NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1329 && !stage3_rg_full && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd0 && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d642 ; - assign rg_state_2_EQ_4_083_AND_NOT_stage3_rg_full_4_5_ETC___d1299 = - rg_state == 4'd4 && !stage3_rg_full && - IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == - 2'd3 && - (!stage1_rg_full || - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d490) ; - assign rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1474 = + assign rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1482 = rg_state == 4'd4 && - rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1469 && + rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1477 && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd0 && !stage3_rg_full && @@ -5032,30 +5258,30 @@ module mkCPU(CLK, IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 != 2'd0 || stage3_rg_full) ; - assign rg_state_2_EQ_5_428_OR_rg_state_2_EQ_4_083_AND_ETC___d1437 = - rg_state == 4'd5 || - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && + assign rg_state_2_EQ_7_436_OR_rg_state_2_EQ_4_083_AND_ETC___d1445 = + rg_state == 4'd7 || + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == 4'd11 && - (x_out_trap_info_exc_code__h14151 != 4'd3 || + (x_out_trap_info_exc_code__h14057 != 4'd3 || !csr_regfile$dcsr_break_enters_debug) ; - assign rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1469 = + assign rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1477 = (rg_stop_req || rg_step_count) && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d490 && IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1084 ; - assign rs1__h7674 = { 2'b01, instr__h4435[9:7] } ; - assign rs1_val__h20224 = - (x_out_data_to_stage2_instr__h12529[14:12] == 3'b001) ? - x_out_data_to_stage2_val1__h12533 : - { 27'd0, x_out_data_to_stage2_instr__h12529[19:15] } ; - assign rs1_val_bypassed__h4445 = - (_theResult____h4437[19:15] == 5'd0) ? 32'd0 : val__h7022 ; - assign rs2_val__h12631 = - (_theResult____h4437[24:20] == 5'd0) ? 32'd0 : val__h12445 ; - assign shamt__h12793 = - (_theResult____h4437[6:0] == 7'b0010011) ? - _theResult____h4437[24:20] : - rs2_val__h12631[4:0] ; + assign rs1__h7580 = { 2'b01, instr__h4318[9:7] } ; + assign rs1_val__h20274 = + (x_out_data_to_stage2_instr__h12435[14:12] == 3'b001) ? + x_out_data_to_stage2_val1__h12439 : + { 27'd0, x_out_data_to_stage2_instr__h12435[19:15] } ; + assign rs1_val_bypassed__h4328 = + (_theResult____h4320[19:15] == 5'd0) ? 32'd0 : val__h6928 ; + assign rs2_val__h12537 = + (_theResult____h4320[24:20] == 5'd0) ? 32'd0 : val__h12351 ; + assign shamt__h12699 = + (_theResult____h4320[6:0] == 7'b0010011) ? + _theResult____h4320[24:20] : + rs2_val__h12537[4:0] ; assign stage1_rg_full_00_AND_near_mem_imem_valid_AND__ETC___d1087 = stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d490 && @@ -5087,123 +5313,123 @@ module mkCPU(CLK, !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) ; - assign td1_rd__h22143 = { 3'd0, csr_regfile$csr_ret_actions[33:32] } ; - assign theResult__437_BITS_31_TO_20__q17 = _theResult____h4437[31:20] ; - assign theResult__437_BITS_31_TO_25_CONCAT_theResult__ETC__q7 = - { _theResult____h4437[31:25], _theResult____h4437[11:7] } ; - assign theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q3 = - { _theResult____h4437[31], - _theResult____h4437[7], - _theResult____h4437[30:25], - _theResult____h4437[11:8], + assign td1_rd__h22193 = { 3'd0, csr_regfile$csr_ret_actions[33:32] } ; + assign theResult__320_BITS_31_TO_20__q17 = _theResult____h4320[31:20] ; + assign theResult__320_BITS_31_TO_25_CONCAT_theResult__ETC__q7 = + { _theResult____h4320[31:25], _theResult____h4320[11:7] } ; + assign theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q3 = + { _theResult____h4320[31], + _theResult____h4320[7], + _theResult____h4320[30:25], + _theResult____h4320[11:8], 1'b0 } ; - assign theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q4 = - { _theResult____h4437[31], - _theResult____h4437[19:12], - _theResult____h4437[20], - _theResult____h4437[30:21], + assign theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q4 = + { _theResult____h4320[31], + _theResult____h4320[19:12], + _theResult____h4320[20], + _theResult____h4320[30:21], 1'b0 } ; - assign trace_data_rd__h27064 = { 3'd0, csr_regfile$csr_trap_actions[1:0] } ; - assign trace_data_word3__h27067 = { 32'd0, imem_rg_pc } ; - assign trap_info_tval__h14148 = - (_theResult____h4437[6:0] != 7'b1101111 && - _theResult____h4437[6:0] != 7'b1100111 && - (_theResult____h4437[6:0] != 7'b1110011 || - _theResult____h4437[14:12] != 3'b0 || - _theResult____h4437[11:7] != 5'd0 || - _theResult____h4437[19:15] != 5'd0 || - _theResult____h4437[31:20] != 12'b0 && - _theResult____h4437[31:20] != 12'b000000000001)) ? + assign trace_data_rd__h27114 = { 3'd0, csr_regfile$csr_trap_actions[1:0] } ; + assign trace_data_word3__h27117 = { 32'd0, imem_rg_pc } ; + assign trap_info_tval__h14054 = + (_theResult____h4320[6:0] != 7'b1101111 && + _theResult____h4320[6:0] != 7'b1100111 && + (_theResult____h4320[6:0] != 7'b1110011 || + _theResult____h4320[14:12] != 3'b0 || + _theResult____h4320[11:7] != 5'd0 || + _theResult____h4320[19:15] != 5'd0 || + _theResult____h4320[31:20] != 12'b0 && + _theResult____h4320[31:20] != 12'b000000000001)) ? (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482 ? - _theResult____h4437 : - { 16'd0, instr__h4435[15:0] }) : + _theResult____h4320 : + { 16'd0, instr__h4318[15:0] }) : IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1027 ; - assign val__h12445 = + assign val__h12351 = (IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 == 2'd2 && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d472) ? - x_out_bypass_rd_val__h6908 : - rd_val__h12443 ; - assign val__h7022 = + x_out_bypass_rd_val__h6814 : + rd_val__h12349 ; + assign val__h6928 = (IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 == 2'd2 && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d470) ? - x_out_bypass_rd_val__h6908 : - rd_val__h7020 ; - assign value__h14199 = - near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h14148 ; - assign x__h18419 = + x_out_bypass_rd_val__h6814 : + rd_val__h6926 ; + assign value__h14105 = + near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h14054 ; + assign x__h18325 = NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_ETC___d211 ? - { 16'd0, instr__h4435[15:0] } : - _theResult____h4437 ; - assign x__h21266 = - (x_out_data_to_stage2_instr__h12529[19:15] == 5'd0) ? + { 16'd0, instr__h4318[15:0] } : + _theResult____h4320 ; + assign x__h21316 = + (x_out_data_to_stage2_instr__h12435[19:15] == 5'd0) ? 32'd0 : 32'd1 ; - assign x__h21274 = - (x_out_data_to_stage2_instr__h12529[19:15] == 5'd0) ? + assign x__h21324 = + (x_out_data_to_stage2_instr__h12435[19:15] == 5'd0) ? 32'hAAAAAAAA : csr_regfile$mav_csr_write ; - assign x__h27351 = - csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1478[63:0] / - _theResult____h27350 ; - assign x_out_data_to_stage2_instr__h12529 = + assign x__h27401 = + csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1486[63:0] / + _theResult____h27400 ; + assign x_out_data_to_stage2_instr__h12435 = NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_ETC___d211 ? - instr___1__h7068 : - instr__h4435 ; - assign x_out_data_to_stage2_rd__h12531 = - (_theResult____h4437[6:0] == 7'b1100011) ? + instr___1__h6974 : + instr__h4318 ; + assign x_out_data_to_stage2_rd__h12437 = + (_theResult____h4320[6:0] == 7'b1100011) ? 5'd0 : - _theResult____h4437[11:7] ; - assign x_out_data_to_stage2_val2__h12534 = - (_theResult____h4437[6:0] == 7'b1100011) ? - branch_target__h12635 : - rs2_val__h12631 ; - assign x_out_next_pc__h12499 = + _theResult____h4320[11:7] ; + assign x_out_data_to_stage2_val2__h12440 = + (_theResult____h4320[6:0] == 7'b1100011) ? + branch_target__h12541 : + rs2_val__h12537 ; + assign x_out_next_pc__h12405 = IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688 ? - data_to_stage2_addr__h12523 : - fall_through_pc__h12486 ; - assign x_out_trap_info_exc_code__h14151 = + data_to_stage2_addr__h12429 : + fall_through_pc__h12392 ; + assign x_out_trap_info_exc_code__h14057 = near_mem$imem_exc ? near_mem$imem_exc_code : - alu_outputs_exc_code__h13199 ; - assign x_word3__h19995 = { 32'd0, stage2_rg_stage2[401:370] } ; - assign x_word3__h20591 = - { 52'd0, x_out_data_to_stage2_instr__h12529[31:20] } ; - assign y__h21114 = ~rs1_val__h20813 ; + alu_outputs_exc_code__h13105 ; + assign x_word3__h20017 = { 32'd0, rg_trap_info[67:36] } ; + assign x_word3__h20641 = + { 52'd0, x_out_data_to_stage2_instr__h12435[31:20] } ; + assign y__h21164 = ~rs1_val__h20863 ; always@(stage2_rg_stage2) begin case (stage2_rg_stage2[337:335]) 3'd0, 3'd1, 3'd4: - x_out_data_to_stage3_rd__h6556 = stage2_rg_stage2[334:330]; - 3'd2: x_out_data_to_stage3_rd__h6556 = 5'd0; - default: x_out_data_to_stage3_rd__h6556 = stage2_rg_stage2[334:330]; + x_out_data_to_stage3_rd__h6462 = stage2_rg_stage2[334:330]; + 3'd2: x_out_data_to_stage3_rd__h6462 = 5'd0; + default: x_out_data_to_stage3_rd__h6462 = stage2_rg_stage2[334:330]; endcase end always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64) begin case (stage2_rg_stage2[337:335]) - 3'd0: x_out_data_to_stage3_rd_val__h6557 = stage2_rg_stage2[297:266]; + 3'd0: x_out_data_to_stage3_rd_val__h6463 = stage2_rg_stage2[297:266]; 3'd1, 3'd4: - x_out_data_to_stage3_rd_val__h6557 = near_mem$dmem_word64[31:0]; - default: x_out_data_to_stage3_rd_val__h6557 = stage2_mbox$word; + x_out_data_to_stage3_rd_val__h6463 = near_mem$dmem_word64[31:0]; + default: x_out_data_to_stage3_rd_val__h6463 = stage2_mbox$word; endcase end always@(stage2_rg_stage2) begin case (stage2_rg_stage2[337:335]) - 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h6907 = stage2_rg_stage2[334:330]; - default: x_out_bypass_rd__h6907 = stage2_rg_stage2[334:330]; + 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h6813 = stage2_rg_stage2[334:330]; + default: x_out_bypass_rd__h6813 = stage2_rg_stage2[334:330]; endcase end always@(stage2_rg_stage2 or - stage2_mbox$word or output_stage2___1_bypass_rd_val__h6896) + stage2_mbox$word or output_stage2___1_bypass_rd_val__h6802) begin case (stage2_rg_stage2[337:335]) - 3'd0: x_out_bypass_rd_val__h6908 = stage2_rg_stage2[297:266]; + 3'd0: x_out_bypass_rd_val__h6814 = stage2_rg_stage2[297:266]; 3'd1, 3'd4: - x_out_bypass_rd_val__h6908 = output_stage2___1_bypass_rd_val__h6896; - default: x_out_bypass_rd_val__h6908 = stage2_mbox$word; + x_out_bypass_rd_val__h6814 = output_stage2___1_bypass_rd_val__h6802; + default: x_out_bypass_rd_val__h6814 = stage2_mbox$word; endcase end always@(stage2_rg_stage2 or @@ -5255,9 +5481,9 @@ module mkCPU(CLK, IF_stage2_rg_stage2_4_BITS_337_TO_335_5_EQ_3_0_ETC___d121; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011, 7'b0010011, 7'b0010111, @@ -5266,9 +5492,9 @@ module mkCPU(CLK, 7'b0110111, 7'b1100111, 7'b1101111: - x_out_data_to_stage2_trace_data_rd__h17725 = - _theResult____h4437[11:7]; - default: x_out_data_to_stage2_trace_data_rd__h17725 = 5'd2; + x_out_data_to_stage2_trace_data_rd__h17631 = + _theResult____h4320[11:7]; + default: x_out_data_to_stage2_trace_data_rd__h17631 = 5'd2; endcase end always@(rg_cur_priv) @@ -5279,20 +5505,20 @@ module mkCPU(CLK, default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd11; endcase end - always@(_theResult____h4437 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q5) + always@(_theResult____h4320 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q5) begin - case (_theResult____h4437[31:20]) + case (_theResult____h4320[31:20]) 12'b0: - CASE_theResult__437_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = + CASE_theResult__320_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = CASE_rg_cur_priv_0b0_8_0b1_9_11__q5; 12'b000000000001: - CASE_theResult__437_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd3; - default: CASE_theResult__437_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd2; + CASE_theResult__320_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd3; + default: CASE_theResult__320_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd2; endcase end - always@(_theResult____h4437 or alu_outputs___1_exc_code__h13156) + always@(_theResult____h4320 or alu_outputs___1_exc_code__h13062) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011, 7'b0001111, 7'b0010011, @@ -5301,19 +5527,19 @@ module mkCPU(CLK, 7'b0110011, 7'b0110111, 7'b1100011: - alu_outputs_exc_code__h13199 = 4'd2; - 7'b1100111, 7'b1101111: alu_outputs_exc_code__h13199 = 4'd0; + alu_outputs_exc_code__h13105 = 4'd2; + 7'b1100111, 7'b1101111: alu_outputs_exc_code__h13105 = 4'd0; 7'b1110011: - alu_outputs_exc_code__h13199 = alu_outputs___1_exc_code__h13156; - default: alu_outputs_exc_code__h13199 = 4'd2; + alu_outputs_exc_code__h13105 = alu_outputs___1_exc_code__h13062; + default: alu_outputs_exc_code__h13105 = 4'd2; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d529 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d531) begin - case (_theResult____h4437[14:12]) + case (_theResult____h4320[14:12]) 3'b0: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634 = !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d529; @@ -5330,16 +5556,16 @@ module mkCPU(CLK, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634 = !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634 = - _theResult____h4437[14:12] != 3'b111 || + _theResult____h4320[14:12] != 3'b111 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d529 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d531) begin - case (_theResult____h4437[14:12]) + case (_theResult____h4320[14:12]) 3'b0: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 = IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d529; @@ -5356,171 +5582,171 @@ module mkCPU(CLK, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 = IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 = - _theResult____h4437[14:12] == 3'b111 && + _theResult____h4320[14:12] == 3'b111 && !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: - CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4437[14:12] != 3'b0 && - _theResult____h4437[14:12] != 3'b100 && - _theResult____h4437[14:12] != 3'b001 && - _theResult____h4437[14:12] != 3'b101 && - _theResult____h4437[14:12] != 3'b010; + CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = + _theResult____h4320[14:12] != 3'b0 && + _theResult____h4320[14:12] != 3'b100 && + _theResult____h4320[14:12] != 3'b001 && + _theResult____h4320[14:12] != 3'b101 && + _theResult____h4320[14:12] != 3'b010; 7'b0100011: - CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4437[14:12] != 3'b0 && - _theResult____h4437[14:12] != 3'b001 && - _theResult____h4437[14:12] != 3'b010; - default: CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4437[6:0] != 7'b0101111 || - _theResult____h4437[31:27] != 5'b00010 && - _theResult____h4437[31:27] != 5'b00011 && - _theResult____h4437[31:27] != 5'b0 && - _theResult____h4437[31:27] != 5'b00001 && - _theResult____h4437[31:27] != 5'b01100 && - _theResult____h4437[31:27] != 5'b01000 && - _theResult____h4437[31:27] != 5'b00100 && - _theResult____h4437[31:27] != 5'b10000 && - _theResult____h4437[31:27] != 5'b11000 && - _theResult____h4437[31:27] != 5'b10100 && - _theResult____h4437[31:27] != 5'b11100 || - _theResult____h4437[14:12] != 3'b010; + CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = + _theResult____h4320[14:12] != 3'b0 && + _theResult____h4320[14:12] != 3'b001 && + _theResult____h4320[14:12] != 3'b010; + default: CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = + _theResult____h4320[6:0] != 7'b0101111 || + _theResult____h4320[31:27] != 5'b00010 && + _theResult____h4320[31:27] != 5'b00011 && + _theResult____h4320[31:27] != 5'b0 && + _theResult____h4320[31:27] != 5'b00001 && + _theResult____h4320[31:27] != 5'b01100 && + _theResult____h4320[31:27] != 5'b01000 && + _theResult____h4320[31:27] != 5'b00100 && + _theResult____h4320[31:27] != 5'b10000 && + _theResult____h4320[31:27] != 5'b11000 && + _theResult____h4320[31:27] != 5'b10100 && + _theResult____h4320[31:27] != 5'b11100 || + _theResult____h4320[14:12] != 3'b010; endcase end - always@(_theResult____h4437 or - CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 or + always@(_theResult____h4320 or + CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 or NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d570) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0010011, 7'b0110011: - CASE_theResult__437_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = + CASE_theResult__320_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d570; - default: CASE_theResult__437_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = - _theResult____h4437[6:0] != 7'b0110111 && - _theResult____h4437[6:0] != 7'b0010111 && - CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8; + default: CASE_theResult__320_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = + _theResult____h4320[6:0] != 7'b0110111 && + _theResult____h4320[6:0] != 7'b0010111 && + CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: - CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4437[14:12] == 3'b0 || - _theResult____h4437[14:12] == 3'b100 || - _theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101 || - _theResult____h4437[14:12] == 3'b010; + CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10 = + _theResult____h4320[14:12] == 3'b0 || + _theResult____h4320[14:12] == 3'b100 || + _theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101 || + _theResult____h4320[14:12] == 3'b010; 7'b0100011: - CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4437[14:12] == 3'b0 || - _theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b010; - default: CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4437[6:0] == 7'b0101111 && - (_theResult____h4437[31:27] == 5'b00010 || - _theResult____h4437[31:27] == 5'b00011 || - _theResult____h4437[31:27] == 5'b0 || - _theResult____h4437[31:27] == 5'b00001 || - _theResult____h4437[31:27] == 5'b01100 || - _theResult____h4437[31:27] == 5'b01000 || - _theResult____h4437[31:27] == 5'b00100 || - _theResult____h4437[31:27] == 5'b10000 || - _theResult____h4437[31:27] == 5'b11000 || - _theResult____h4437[31:27] == 5'b10100 || - _theResult____h4437[31:27] == 5'b11100) && - _theResult____h4437[14:12] == 3'b010; + CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10 = + _theResult____h4320[14:12] == 3'b0 || + _theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b010; + default: CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10 = + _theResult____h4320[6:0] == 7'b0101111 && + (_theResult____h4320[31:27] == 5'b00010 || + _theResult____h4320[31:27] == 5'b00011 || + _theResult____h4320[31:27] == 5'b0 || + _theResult____h4320[31:27] == 5'b00001 || + _theResult____h4320[31:27] == 5'b01100 || + _theResult____h4320[31:27] == 5'b01000 || + _theResult____h4320[31:27] == 5'b00100 || + _theResult____h4320[31:27] == 5'b10000 || + _theResult____h4320[31:27] == 5'b11000 || + _theResult____h4320[31:27] == 5'b10100 || + _theResult____h4320[31:27] == 5'b11100) && + _theResult____h4320[14:12] == 3'b010; endcase end - always@(_theResult____h4437 or - CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10 or + always@(_theResult____h4320 or + CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10 or IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d659) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0010011, 7'b0110011: - CASE_theResult__437_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = + CASE_theResult__320_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d659; - default: CASE_theResult__437_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = - _theResult____h4437[6:0] == 7'b0110111 || - _theResult____h4437[6:0] == 7'b0010111 || - CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10; + default: CASE_theResult__320_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = + _theResult____h4320[6:0] == 7'b0110111 || + _theResult____h4320[6:0] == 7'b0010111 || + CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or rg_cur_priv or IF_rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_E_ETC___d729) begin - case (_theResult____h4437[31:20]) + case (_theResult____h4320[31:20]) 12'b0, 12'b000000000001: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d731 = 4'd11; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d731 = (rg_cur_priv == 2'b11 && - _theResult____h4437[31:20] == 12'b001100000010) ? + _theResult____h4320[31:20] == 12'b001100000010) ? 4'd7 : IF_rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_E_ETC___d729; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[14:12]) + case (_theResult____h4320[14:12]) 3'b0, 3'b001, 3'b010, 3'b100, 3'b101: - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = 4'd0; - default: CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = 4'd0; + default: CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = 4'd11; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[14:12]) - 3'b0: CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd4; - 3'b001: CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd5; - default: CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd11; + case (_theResult____h4320[14:12]) + 3'b0: CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd4; + 3'b001: CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd5; + default: CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd11; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[14:12]) + case (_theResult____h4320[14:12]) 3'b0, 3'b001, 3'b010: - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd0; - default: CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd0; + default: CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd11; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d731) begin - case (_theResult____h4437[14:12]) + case (_theResult____h4320[14:12]) 3'b0: - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = - (_theResult____h4437[11:7] == 5'd0 && - _theResult____h4437[19:15] == 5'd0) ? + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = + (_theResult____h4320[11:7] == 5'd0 && + _theResult____h4320[19:15] == 5'd0) ? IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d731 : 4'd11; 3'b001, 3'b101: - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd2; + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd2; 3'b010, 3'b011, 3'b110, 3'b111: - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd3; - 3'd4: CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd11; + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd3; + 3'd4: CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd11; endcase end - always@(_theResult____h4437 or - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 or - CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13 or + always@(_theResult____h4320 or + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 or + CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13 or IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d696 or - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 or - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15) + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 or + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12; + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12; 7'b0001111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = - CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13; + CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13; 7'b0010011, 7'b0110011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d696; @@ -5528,43 +5754,43 @@ module mkCPU(CLK, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = 4'd0; 7'b0100011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14; + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14; 7'b0101111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = - ((_theResult____h4437[31:27] == 5'b00010 || - _theResult____h4437[31:27] == 5'b00011 || - _theResult____h4437[31:27] == 5'b0 || - _theResult____h4437[31:27] == 5'b00001 || - _theResult____h4437[31:27] == 5'b01100 || - _theResult____h4437[31:27] == 5'b01000 || - _theResult____h4437[31:27] == 5'b00100 || - _theResult____h4437[31:27] == 5'b10000 || - _theResult____h4437[31:27] == 5'b11000 || - _theResult____h4437[31:27] == 5'b10100 || - _theResult____h4437[31:27] == 5'b11100) && - _theResult____h4437[14:12] == 3'b010) ? + ((_theResult____h4320[31:27] == 5'b00010 || + _theResult____h4320[31:27] == 5'b00011 || + _theResult____h4320[31:27] == 5'b0 || + _theResult____h4320[31:27] == 5'b00001 || + _theResult____h4320[31:27] == 5'b01100 || + _theResult____h4320[31:27] == 5'b01000 || + _theResult____h4320[31:27] == 5'b00100 || + _theResult____h4320[31:27] == 5'b10000 || + _theResult____h4320[31:27] == 5'b11000 || + _theResult____h4320[31:27] == 5'b10100 || + _theResult____h4320[31:27] == 5'b11100) && + _theResult____h4320[14:12] == 3'b010) ? 4'd0 : 4'd11; 7'b1110011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15; + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = 4'd11; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b1100011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d750 = - (_theResult____h4437[14:12] != 3'b0 && - _theResult____h4437[14:12] != 3'b001 && - _theResult____h4437[14:12] != 3'b100 && - _theResult____h4437[14:12] != 3'b101 && - _theResult____h4437[14:12] != 3'b110 && - _theResult____h4437[14:12] != 3'b111) ? + (_theResult____h4320[14:12] != 3'b0 && + _theResult____h4320[14:12] != 3'b001 && + _theResult____h4320[14:12] != 3'b100 && + _theResult____h4320[14:12] != 3'b101 && + _theResult____h4320[14:12] != 3'b110 && + _theResult____h4320[14:12] != 3'b111) ? 4'd11 : (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 ? 4'd1 : @@ -5572,206 +5798,206 @@ module mkCPU(CLK, 7'b1100111, 7'b1101111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d750 = 4'd1; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d750 = - (_theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[31:25] == 7'b0000001) ? + (_theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[31:25] == 7'b0000001) ? 4'd0 : - (((_theResult____h4437[6:0] == 7'b0010011 || - _theResult____h4437[6:0] == 7'b0110011) && - (_theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101)) ? - (_theResult____h4437[25] ? 4'd11 : 4'd0) : + (((_theResult____h4320[6:0] == 7'b0010011 || + _theResult____h4320[6:0] == 7'b0110011) && + (_theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101)) ? + (_theResult____h4320[25] ? 4'd11 : 4'd0) : IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746); endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: - CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd1; + CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd1; 7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111: - CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd0; + CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd0; 7'b0100011: - CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd2; - default: CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd4; + CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd2; + default: CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd4; endcase end - always@(_theResult____h4437 or - CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16) + always@(_theResult____h4320 or + CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b1100011, 7'b1100111, 7'b1101111: IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831 = 3'd0; default: IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831 = - (_theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[31:25] == 7'b0000001) ? + (_theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[31:25] == 7'b0000001) ? 3'd3 : - CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16; + CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16; endcase end - always@(_theResult____h4437 or - rs1_val_bypassed__h4445 or - alu_outputs___1_trace_data_word3__h17603 or - alu_outputs___1_trace_data_word3__h17622) + always@(_theResult____h4320 or + rs1_val_bypassed__h4328 or + alu_outputs___1_trace_data_word3__h17509 or + alu_outputs___1_trace_data_word3__h17528) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: - x_out_data_to_stage2_trace_data_word3__h17728 = - alu_outputs___1_trace_data_word3__h17603; + x_out_data_to_stage2_trace_data_word3__h17634 = + alu_outputs___1_trace_data_word3__h17509; 7'b0100011: - x_out_data_to_stage2_trace_data_word3__h17728 = - alu_outputs___1_trace_data_word3__h17622; - default: x_out_data_to_stage2_trace_data_word3__h17728 = - { 32'd0, rs1_val_bypassed__h4445 }; + x_out_data_to_stage2_trace_data_word3__h17634 = + alu_outputs___1_trace_data_word3__h17528; + default: x_out_data_to_stage2_trace_data_word3__h17634 = + { 32'd0, rs1_val_bypassed__h4328 }; endcase end - always@(_theResult____h4437 or - _theResult_____1_fst__h13671 or - rd_val___1__h13639 or - rd_val___1__h13646 or rd_val___1__h13653 or rd_val___1__h13660) + always@(_theResult____h4320 or + _theResult_____1_fst__h13577 or + rd_val___1__h13545 or + rd_val___1__h13552 or rd_val___1__h13559 or rd_val___1__h13566) begin - case (_theResult____h4437[14:12]) - 3'b010: _theResult_____1_fst__h13643 = rd_val___1__h13639; - 3'b011: _theResult_____1_fst__h13643 = rd_val___1__h13646; - 3'b100: _theResult_____1_fst__h13643 = rd_val___1__h13653; - 3'b110: _theResult_____1_fst__h13643 = rd_val___1__h13660; - default: _theResult_____1_fst__h13643 = _theResult_____1_fst__h13671; + case (_theResult____h4320[14:12]) + 3'b010: _theResult_____1_fst__h13549 = rd_val___1__h13545; + 3'b011: _theResult_____1_fst__h13549 = rd_val___1__h13552; + 3'b100: _theResult_____1_fst__h13549 = rd_val___1__h13559; + 3'b110: _theResult_____1_fst__h13549 = rd_val___1__h13566; + default: _theResult_____1_fst__h13549 = _theResult_____1_fst__h13577; endcase end - always@(_theResult____h4437 or - rs1_val_bypassed__h4445 or - eaddr__h12887 or - eaddr__h12907 or - alu_outputs___1_addr__h12657 or - alu_outputs___1_addr__h12704 or alu_outputs___1_addr__h12678) + always@(_theResult____h4320 or + rs1_val_bypassed__h4328 or + eaddr__h12793 or + eaddr__h12813 or + alu_outputs___1_addr__h12563 or + alu_outputs___1_addr__h12610 or alu_outputs___1_addr__h12584) begin - case (_theResult____h4437[6:0]) - 7'b0000011: x_out_data_to_stage2_addr__h12532 = eaddr__h12887; - 7'b0100011: x_out_data_to_stage2_addr__h12532 = eaddr__h12907; + case (_theResult____h4320[6:0]) + 7'b0000011: x_out_data_to_stage2_addr__h12438 = eaddr__h12793; + 7'b0100011: x_out_data_to_stage2_addr__h12438 = eaddr__h12813; 7'b1100011: - x_out_data_to_stage2_addr__h12532 = alu_outputs___1_addr__h12657; + x_out_data_to_stage2_addr__h12438 = alu_outputs___1_addr__h12563; 7'b1100111: - x_out_data_to_stage2_addr__h12532 = alu_outputs___1_addr__h12704; + x_out_data_to_stage2_addr__h12438 = alu_outputs___1_addr__h12610; 7'b1101111: - x_out_data_to_stage2_addr__h12532 = alu_outputs___1_addr__h12678; - default: x_out_data_to_stage2_addr__h12532 = rs1_val_bypassed__h4445; + x_out_data_to_stage2_addr__h12438 = alu_outputs___1_addr__h12584; + default: x_out_data_to_stage2_addr__h12438 = rs1_val_bypassed__h4328; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875 or - alu_outputs___1_addr__h12657 or - alu_outputs___1_addr__h12704 or alu_outputs___1_addr__h12678) + alu_outputs___1_addr__h12563 or + alu_outputs___1_addr__h12610 or alu_outputs___1_addr__h12584) begin - case (_theResult____h4437[6:0]) - 7'b1100011: x__h18327 = alu_outputs___1_addr__h12657; - 7'b1100111: x__h18327 = alu_outputs___1_addr__h12704; - 7'b1101111: x__h18327 = alu_outputs___1_addr__h12678; - default: x__h18327 = + case (_theResult____h4320[6:0]) + 7'b1100011: x__h18233 = alu_outputs___1_addr__h12563; + 7'b1100111: x__h18233 = alu_outputs___1_addr__h12610; + 7'b1101111: x__h18233 = alu_outputs___1_addr__h12584; + default: x__h18233 = IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875; endcase end - always@(_theResult____h4437 or imem_rg_pc or data_to_stage2_addr__h12523) + always@(_theResult____h4320 or imem_rg_pc or data_to_stage2_addr__h12429) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b1100111, 7'b1101111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1027 = - data_to_stage2_addr__h12523; + data_to_stage2_addr__h12429; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1027 = - (_theResult____h4437[6:0] == 7'b1110011 && - _theResult____h4437[14:12] == 3'b0 && - _theResult____h4437[11:7] == 5'd0 && - _theResult____h4437[19:15] == 5'd0 && - _theResult____h4437[31:20] == 12'b000000000001) ? + (_theResult____h4320[6:0] == 7'b1110011 && + _theResult____h4320[14:12] == 3'b0 && + _theResult____h4320[11:7] == 5'd0 && + _theResult____h4320[19:15] == 5'd0 && + _theResult____h4320[31:20] == 12'b000000000001) ? imem_rg_pc : 32'd0; endcase end - always@(_theResult____h4437 or - alu_outputs___1_val1__h13181 or - rd_val__h12836 or - rd_val__h12869 or rd_val__h12853 or alu_outputs___1_val1__h13160) + always@(_theResult____h4320 or + alu_outputs___1_val1__h13087 or + rd_val__h12742 or + rd_val__h12775 or rd_val__h12759 or alu_outputs___1_val1__h13066) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0010011, 7'b0110011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 = - rd_val__h12836; + rd_val__h12742; 7'b0010111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 = - rd_val__h12869; + rd_val__h12775; 7'b0110111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 = - rd_val__h12853; + rd_val__h12759; 7'b1110011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 = - alu_outputs___1_val1__h13160; + alu_outputs___1_val1__h13066; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 = - alu_outputs___1_val1__h13181; + alu_outputs___1_val1__h13087; endcase end - always@(_theResult____h4437 or - rd_val__h12869 or rd_val__h12836 or rd_val__h12853) + always@(_theResult____h4320 or + rd_val__h12775 or rd_val__h12742 or rd_val__h12759) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0010011, 7'b0110011: - CASE_theResult__437_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = - rd_val__h12836; + CASE_theResult__320_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = + rd_val__h12742; 7'b0110111: - CASE_theResult__437_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = - rd_val__h12853; - default: CASE_theResult__437_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = - rd_val__h12869; + CASE_theResult__320_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = + rd_val__h12759; + default: CASE_theResult__320_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = + rd_val__h12775; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1221 or IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b1100111, 7'b1101111: - x__h18596 = + x__h18502 = IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875; - default: x__h18596 = + default: x__h18502 = IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1221; endcase end - always@(_theResult____h4437 or - rs1_val_bypassed__h4445 or + always@(_theResult____h4320 or + rs1_val_bypassed__h4328 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d943 or IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b1100111, 7'b1101111: - x_out_data_to_stage2_val1__h12533 = + x_out_data_to_stage2_val1__h12439 = IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875; - default: x_out_data_to_stage2_val1__h12533 = - (_theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[31:25] == 7'b0000001) ? - rs1_val_bypassed__h4445 : + default: x_out_data_to_stage2_val1__h12439 = + (_theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[31:25] == 7'b0000001) ? + rs1_val_bypassed__h4328 : IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d943; endcase end - always@(x_out_data_to_stage2_instr__h12529 or - x_out_data_to_stage2_val1__h12533) + always@(x_out_data_to_stage2_instr__h12435 or + x_out_data_to_stage2_val1__h12439) begin - case (x_out_data_to_stage2_instr__h12529[14:12]) - 3'b010, 3'b011: rs1_val__h20813 = x_out_data_to_stage2_val1__h12533; - default: rs1_val__h20813 = - { 27'd0, x_out_data_to_stage2_instr__h12529[19:15] }; + case (x_out_data_to_stage2_instr__h12435[14:12]) + 3'b010, 3'b011: rs1_val__h20863 = x_out_data_to_stage2_val1__h12439; + default: rs1_val__h20863 = + { 27'd0, x_out_data_to_stage2_instr__h12435[19:15] }; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd8; + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd8; 7'b0001111, 7'b1100011, 7'b1110011: - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd5; + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd5; 7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111, 7'b1100111, 7'b1101111: - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd6; + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd6; 7'b0100011: - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd10; + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd10; 7'b0101111: - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd11; - default: CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd11; + default: CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd12; endcase end @@ -5858,6 +6084,12 @@ module mkCPU(CLK, rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN; if (rg_start_CPI_instrs$EN) rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN; + if (rg_trap_info$EN) + rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN; + if (rg_trap_instr$EN) + rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN; + if (rg_trap_trace_data$EN) + rg_trap_trace_data <= `BSV_ASSIGNMENT_DELAY rg_trap_trace_data$D_IN; if (stage2_rg_stage2$EN) stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN; if (stage3_rg_stage3$EN) @@ -5890,6 +6122,10 @@ module mkCPU(CLK, rg_state = 4'hA; rg_step_count = 1'h0; rg_stop_req = 1'h0; + rg_trap_info = 68'hAAAAAAAAAAAAAAAAA; + rg_trap_instr = 32'hAAAAAAAA; + rg_trap_trace_data = + 234'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; stage1_rg_full = 1'h0; stage2_rg_full = 1'h0; stage2_rg_resetting = 1'h0; @@ -6114,8 +6350,8 @@ module mkCPU(CLK, IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 != 2'd1 && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 != 2'd3) $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6556, - x_out_data_to_stage3_rd_val__h6557); + x_out_data_to_stage3_rd__h6462, + x_out_data_to_stage3_rd_val__h6463); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd0) @@ -6363,7 +6599,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 != 2'd0) - $write("Rd %0d ", x_out_bypass_rd__h6907); + $write("Rd %0d ", x_out_bypass_rd__h6813); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 == 2'd0) @@ -6376,7 +6612,7 @@ module mkCPU(CLK, if (WILL_FIRE_RL_rl_show_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 != 2'd0 && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 != 2'd1) - $write("rd_val:%h", x_out_bypass_rd_val__h6908); + $write("rd_val:%h", x_out_bypass_rd_val__h6814); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); @@ -6384,7 +6620,7 @@ module mkCPU(CLK, if (WILL_FIRE_RL_rl_show_pipe) $display(" Stage1: pc 0x%08h instr 0x%08h priv %0d", imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write(" "); @@ -6547,7 +6783,7 @@ module mkCPU(CLK, near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691) $write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n", imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); @@ -6623,7 +6859,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691) - $write(" rd:%0d\n", x_out_data_to_stage2_rd__h12531); + $write(" rd:%0d\n", x_out_data_to_stage2_rd__h12437); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); if (RST_N != `BSV_RESET_VALUE) @@ -6638,9 +6874,9 @@ module mkCPU(CLK, if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691) $write(" addr:%h val1:%h val2:%h}", - x_out_data_to_stage2_addr__h12532, - x_out_data_to_stage2_val1__h12533, - x_out_data_to_stage2_val2__h12534); + x_out_data_to_stage2_addr__h12438, + x_out_data_to_stage2_val1__h12439, + x_out_data_to_stage2_val2__h12440); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); if (RST_N != `BSV_RESET_VALUE) @@ -6790,7 +7026,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d642) - $write("'h%h", x_out_trap_info_exc_code__h14151); + $write("'h%h", x_out_trap_info_exc_code__h14057); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691) @@ -6818,7 +7054,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d642) - $write("'h%h", value__h14199, " }"); + $write("'h%h", value__h14105, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691) @@ -6832,7 +7068,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d490) - $write(" next_pc 0x%08h", x_out_next_pc__h12499); + $write(" next_pc 0x%08h", x_out_next_pc__h12405); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); if (RST_N != `BSV_RESET_VALUE) @@ -6842,44 +7078,42 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_mip_cmd && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_mip_cmd: MIP new 0x%0h, old 0x%0h", + $display("%0d: %m.rl_stage1_mip_cmd: MIP new 0x%0h, old 0x%0h", csr_regfile$read_csr_mcycle, csr_regfile$csr_mip_read, rg_prev_mip); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run_redundant && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_run_redundant", + $display("%0d: %m.rl_debug_run_redundant", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run_redundant) - $display("%0d: CPU.debug_run_redundant: CPU already running.", + $display("%0d: %m.debug_run_redundant: CPU already running.", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_halt_redundant", + $display("%0d: %m.rl_debug_halt_redundant", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant) - $display("%0d: CPU.rl_debug_halt_redundant: CPU already halted.", + $display("%0d: %m.rl_debug_halt_redundant: CPU already halted.", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant) $write(" state = "); @@ -6903,18 +7137,21 @@ module mkCPU(CLK, $write("CPU_TRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd6) - $write("CPU_SPLIT_FETCH"); + $write("CPU_START_TRAP_HANDLER"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd7) - $write("CPU_CSRRX_RESTART"); + $write("CPU_CSRRx_TRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd8) - $write("CPU_FENCE_I"); + $write("CPU_CSRRX_RESTART"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd9) - $write("CPU_FENCE"); + $write("CPU_FENCE_I"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd10) + $write("CPU_FENCE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd11) $write("CPU_SFENCE_VMA"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state != 4'd0 && @@ -6927,59 +7164,60 @@ module mkCPU(CLK, rg_state != 4'd7 && rg_state != 4'd8 && rg_state != 4'd9 && - rg_state != 4'd10) + rg_state != 4'd10 && + rg_state != 4'd11) $write("CPU_WFI_PAUSED"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_read_gpr && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_read_gpr: reg %0d => 0x%0h", + $display("%0d: %m.rl_debug_read_gpr: reg %0d => 0x%0h", csr_regfile$read_csr_mcycle, f_gpr_reqs$D_OUT[36:32], gpr_regfile$read_rs1_port2); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_write_gpr && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_write_gpr: reg %0d <= 0x%0h", + $display("%0d: %m.rl_debug_write_gpr: reg %0d <= 0x%0h", csr_regfile$read_csr_mcycle, f_gpr_reqs$D_OUT[36:32], f_gpr_reqs$D_OUT[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_gpr_access_busy && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_gpr_access_busy", + $display("%0d: %m.rl_debug_gpr_access_busy", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_read_csr && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_read_csr: csr %0d => 0x%0h", + $display("%0d: %m.rl_debug_read_csr: csr %0d => 0x%0h", csr_regfile$read_csr_mcycle, f_csr_reqs$D_OUT[43:32], csr_regfile$read_csr_port2[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_run", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_debug_run", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" CPU_Stage1.enq: 0x%08h", csr_regfile$read_dpc); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run) - $display("%0d: CPU.rl_debug_run: restart at PC = 0x%0h", + $display("%0d: %m.rl_debug_run: restart at PC = 0x%0h", csr_regfile$read_csr_mcycle, csr_regfile$read_dpc); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_run: 'run' from dpc 0x%0h", + $display("%0d: %m.rl_debug_run: 'run' from dpc 0x%0h", csr_regfile$read_csr_mcycle, csr_regfile$read_dpc); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_write_csr && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_write_csr: csr 0x%0h 0x%0h <= 0x%0h", + $display("%0d: %m.rl_debug_write_csr: csr 0x%0h 0x%0h <= 0x%0h", csr_regfile$read_csr_mcycle, f_csr_reqs$D_OUT[43:32], f_csr_reqs$D_OUT[31:0], @@ -6987,100 +7225,100 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_csr_access_busy && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_csr_access_busy", + $display("%0d: %m.rl_debug_csr_access_busy", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_W && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - cur_verbosity__h3142 == 4'd1) + cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12529[19:15], - rs1_val__h20224, - x_out_data_to_stage2_instr__h12529[31:20], + x_out_data_to_stage2_instr__h12435[19:15], + rs1_val__h20274, + x_out_data_to_stage2_instr__h12435[31:20], csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h12529[11:7]); + x_out_data_to_stage2_instr__h12435[11:7]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - cur_verbosity__h3142 == 4'd1) + cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12529[19:15], - rs1_val__h20224, - x_out_data_to_stage2_instr__h12529[31:20], - x_out_data_to_stage2_instr__h12529[11:7]); + x_out_data_to_stage2_instr__h12435[19:15], + rs1_val__h20274, + x_out_data_to_stage2_instr__h12435[31:20], + x_out_data_to_stage2_instr__h12435[11:7]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_S_or_C", + $display("%0d: %m.rl_stage1_CSRR_S_or_C", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && csr_regfile$access_permitted_2 && - cur_verbosity__h3142 == 4'd1) + cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && csr_regfile$access_permitted_2 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12529[19:15], - rs1_val__h20813, - x_out_data_to_stage2_instr__h12529[31:20], + x_out_data_to_stage2_instr__h12435[19:15], + rs1_val__h20863, + x_out_data_to_stage2_instr__h12435[31:20], csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h12529[11:7]); + x_out_data_to_stage2_instr__h12435[11:7]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && !csr_regfile$access_permitted_2 && - cur_verbosity__h3142 == 4'd1) + cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && !csr_regfile$access_permitted_2 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12529[19:15], - rs1_val__h20813, - x_out_data_to_stage2_instr__h12529[31:20], - x_out_data_to_stage2_instr__h12529[11:7]); + x_out_data_to_stage2_instr__h12435[19:15], + rs1_val__h20863, + x_out_data_to_stage2_instr__h12435[31:20], + x_out_data_to_stage2_instr__h12435[11:7]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_xRET && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3142 != 4'd0) + if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2930 != 4'd0) $display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d", csr_regfile$csr_ret_actions[65:34], csr_regfile$csr_ret_actions[31:0], @@ -7088,43 +7326,43 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_FENCE_I && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_FENCE_I && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_FENCE && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_FENCE && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_WFI && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_WFI && @@ -7133,38 +7371,38 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_trap && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3142 != 4'd0) - $display("%0d: CPU.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", + if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2930 != 4'd0) + $display("%0d: %m.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", csr_regfile$read_csr_mcycle, rg_cur_priv, csr_regfile$csr_trap_actions[33:2], imem_rg_pc); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3142 != 4'd0) + if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2930 != 4'd0) $display(" tval:0x%0h new pc:0x%0h new mstatus:0x%0h", - value__h14199, + value__h14105, csr_regfile$csr_trap_actions[97:66], csr_regfile$csr_trap_actions[65:34]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_trap_BREAK_to_Debug_Mode", + $display("%0d: %m.rl_trap_BREAK_to_Debug_Mode", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode) - $display("%0d: CPU.rl_trap_BREAK_to_Debug_Mode: PC 0x%08h instr 0x%08h", + $display("%0d: %m.rl_trap_BREAK_to_Debug_Mode: PC 0x%08h instr 0x%08h", csr_regfile$read_csr_mcycle, imem_rg_pc, - x_out_data_to_stage2_instr__h12529); + x_out_data_to_stage2_instr__h12435); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) @@ -7172,30 +7410,30 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_BREAK_cache_flush_finish && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_BREAK_cache_flush_finish", + $display("%0d: %m.rl_BREAK_cache_flush_finish", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_stop && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_stop", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_stop", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_stop && rg_stop_req) - $display("%0d: CPU.rl_stage1_stop: Stop for debugger. minstret %0d priv %0d PC 0x%0h instr 0x%0h", + $display("%0d: %m.rl_stage1_stop: Stop for debugger. minstret %0d priv %0d PC 0x%0h instr 0x%0h", csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret, rg_cur_priv, imem_rg_pc, - x_out_data_to_stage2_instr__h12529); + x_out_data_to_stage2_instr__h12435); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_stop && rg_stop_req) $display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'", - cpi__h27352, - cpifrac__h27353, - delta_CPI_cycles__h27348, - _theResult____h27350); + cpi__h27402, + cpifrac__h27403, + delta_CPI_cycles__h27398, + _theResult____h27400); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_stop && !rg_stop_req) - $display("%0d: CPU.rl_stage1_stop: Stop after single-step. PC = 0x%08h", + $display("%0d: %m.rl_stage1_stop: Stop after single-step. PC = 0x%08h", csr_regfile$read_csr_mcycle, imem_rg_pc); if (WILL_FIRE_RL_imem_rl_assert_fail) @@ -7208,17 +7446,17 @@ module mkCPU(CLK, soc_map$m_pc_reset_value[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h", + $display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h", csr_regfile$read_csr_mcycle, soc_map$m_pc_reset_value[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE", + $display("%0d: %m.rl_reset_complete: entering DEBUG_MODE", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_pipe && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) @@ -7262,8 +7500,8 @@ module mkCPU(CLK, IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd2 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6556, - x_out_data_to_stage3_rd_val__h6557); + x_out_data_to_stage3_rd__h6462, + x_out_data_to_stage3_rd_val__h6463); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd2 && @@ -7272,7 +7510,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd2 && - cur_verbosity__h3142 == 4'd1) + cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, stage2_rg_stage2[401:370], @@ -7289,50 +7527,50 @@ module mkCPU(CLK, if (WILL_FIRE_RL_rl_pipe && NOT_stage1_rg_full_00_01_OR_NOT_near_mem_imem__ETC___d1268 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12499); + $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12405); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_halt", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_debug_halt", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_halt", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_debug_halt", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage2_nonpipe && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_trap && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, - stage2_rg_stage2[401:370], - stage2_rg_stage2[369:338], + rg_trap_info[67:36], + rg_trap_instr, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3142 != 4'd0) + if (WILL_FIRE_RL_rl_trap && cur_verbosity__h2930 != 4'd0) $display(" mcause:0x%0h epc 0x%0h tval:0x%0h new pc 0x%0h, new mstatus 0x%0h", csr_regfile$csr_trap_actions[33:2], - stage2_rg_stage2[401:370], - stage2_rg_stage2[329:298], + rg_trap_info[67:36], + rg_trap_info[31:0], csr_regfile$csr_trap_actions[97:66], csr_regfile$csr_trap_actions[65:34]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12499); + $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12405); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d pc:%0x cur_priv:%0d", csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret, - x_out_next_pc__h12499, + x_out_next_pc__h12405, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_FENCE_I && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_FENCE_I && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) @@ -7344,8 +7582,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_SFENCE_VMA", - csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_finish_SFENCE_VMA", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) @@ -7357,7 +7594,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_FENCE && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_FENCE && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) @@ -7369,9 +7606,9 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_WFI_resume && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h3142 != 4'd0) + if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h2930 != 4'd0) $display(" WFI resume"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_WFI_resume && @@ -7380,29 +7617,29 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_from_WFI && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_reset_from_Debug_Module) + $display("%0d: %m.rl_reset_from_Debug_Module", + csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_trap_fetch && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_from_Debug_Module) - $display("%0d: CPU.rl_reset_from_Debug_Module", - csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_interrupt && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3142 != 4'd0) - $display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", + if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2930 != 4'd0) + $display("%0d: %m.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", csr_regfile$read_csr_mcycle, imem_rg_pc, csr_regfile$csr_trap_actions[97:66], @@ -7423,8 +7660,8 @@ module mkCPU(CLK, if (WILL_FIRE_RL_rl_reset_start) $display("================================================================"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h3142 != 4'd0) - $display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle); + if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h2930 != 4'd0) + $display("%0d: %m.rl_reset_start", csr_regfile$read_csr_mcycle); end // synopsys translate_on endmodule // mkCPU diff --git a/src_SSITH_P1/Verilog_RTL/mkCSR_MIE.v b/src_SSITH_P1/Verilog_RTL/mkCSR_MIE.v index df80ca60..222c5875 100644 --- a/src_SSITH_P1/Verilog_RTL/mkCSR_MIE.v +++ b/src_SSITH_P1/Verilog_RTL/mkCSR_MIE.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:36 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkCSR_MIP.v b/src_SSITH_P1/Verilog_RTL/mkCSR_MIP.v index fb4847d7..2b0149b4 100644 --- a/src_SSITH_P1/Verilog_RTL/mkCSR_MIP.v +++ b/src_SSITH_P1/Verilog_RTL/mkCSR_MIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:36 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkCSR_RegFile.v b/src_SSITH_P1/Verilog_RTL/mkCSR_RegFile.v index a5b1888f..832615d7 100644 --- a/src_SSITH_P1/Verilog_RTL/mkCSR_RegFile.v +++ b/src_SSITH_P1/Verilog_RTL/mkCSR_RegFile.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:38 BST 2019 // // // Ports: @@ -589,7 +589,6 @@ module mkCSR_RegFile(CLK, MUX_rg_mepc$write_1__SEL_1, MUX_rg_mtval$write_1__SEL_1, MUX_rg_mtvec$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2, MUX_rg_tdata1$write_1__SEL_1, MUX_rw_minstret$wset_1__SEL_1; @@ -598,43 +597,43 @@ module mkCSR_RegFile(CLK, IF_mav_read_csr_csr_addr_EQ_0xC00_67_THEN_rg_m_ETC___d641, IF_read_csr_csr_addr_EQ_0xC00_1_THEN_rg_mcycle_ETC___d247, IF_read_csr_port2_csr_addr_EQ_0xC00_70_THEN_rg_ETC___d444; - wire [63 : 0] x__h5648, x__h5756; + wire [63 : 0] x__h5468, x__h5576; wire [33 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1162; wire [31 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1144, - _theResult___fst__h9063, - _theResult___fst__h9264, + _theResult___fst__h8883, + _theResult___fst__h9084, csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137, - exc_pc___1__h8148, - exc_pc__h7884, - exc_pc__h8095, - mask__h9084, - mask__h9101, - new_dcsr__h5935, - result__h5831, - v__h4998, - v__h5060, - v__h5216, - val__h9102, - vector_offset__h8096, - wordxl1__h4515, - x__h6695, - x__h8919, - x__h8920, - x__h9083, - x__h9096, - x__h9113, - y__h9097, - y__h9114; - wire [22 : 0] fixed_up_val_23__h4556, - fixed_up_val_23__h7323, - fixed_up_val_23__h8982; - wire [5 : 0] ie_from_x__h9047, pie_from_x__h9048; + exc_pc___1__h7968, + exc_pc__h7704, + exc_pc__h7915, + mask__h8904, + mask__h8921, + new_dcsr__h5755, + result__h5651, + v__h4818, + v__h4880, + v__h5036, + val__h8922, + vector_offset__h7916, + wordxl1__h4335, + x__h6515, + x__h8739, + x__h8740, + x__h8903, + x__h8916, + x__h8933, + y__h8917, + y__h8934; + wire [22 : 0] fixed_up_val_23__h4376, + fixed_up_val_23__h7143, + fixed_up_val_23__h8802; + wire [5 : 0] ie_from_x__h8867, pie_from_x__h8868; wire [3 : 0] IF_NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_N_ETC___d1480, IF_NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_N_ETC___d1482, IF_NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_N_ETC___d1484, IF_NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_N_ETC___d1486, - exc_code__h8761; - wire [1 : 0] mpp__h8189, to_y__h9263; + exc_code__h8581; + wire [1 : 0] mpp__h8009, to_y__h9083; wire NOT_access_permitted_1_csr_addr_ULT_0xC03_163__ETC___d1257, NOT_access_permitted_2_csr_addr_ULT_0xC03_262__ETC___d1355, NOT_cfg_verbosity_read__21_ULE_1_22___d823, @@ -647,7 +646,7 @@ module mkCSR_RegFile(CLK, NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_NOT__ETC___d1474, NOT_csr_trap_actions_nmi_91_AND_csr_trap_actio_ETC___d1068, NOT_mav_csr_write_csr_addr_ULT_0xB03_44_25_AND_ETC___d836, - b__h9100, + b__h8920, csr_mip_fv_read__09_BIT_11_387_AND_csr_mie_fv__ETC___d1398, csr_mip_fv_read__09_BIT_11_387_AND_csr_mie_fv__ETC___d1403, csr_mip_fv_read__09_BIT_11_387_AND_csr_mie_fv__ETC___d1408, @@ -866,7 +865,7 @@ module mkCSR_RegFile(CLK, assign read_satp = 32'hAAAAAAAA ; // actionvalue method csr_trap_actions - assign csr_trap_actions = { x__h6695, x__h8919, x__h8920, 2'b11 } ; + assign csr_trap_actions = { x__h6515, x__h8739, x__h8740, 2'b11 } ; assign RDY_csr_trap_actions = 1'd1 ; assign CAN_FIRE_csr_trap_actions = 1'd1 ; assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; @@ -1027,36 +1026,16 @@ module mkCSR_RegFile(CLK, .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_flash_mem_addr_base(), - .m_flash_mem_addr_size(), - .m_flash_mem_addr_lim(), - .m_ethernet_0_addr_base(), - .m_ethernet_0_addr_size(), - .m_ethernet_0_addr_lim(), - .m_dma_0_addr_base(), - .m_dma_0_addr_size(), - .m_dma_0_addr_lim(), - .m_uart16550_0_addr_base(), - .m_uart16550_0_addr_size(), - .m_uart16550_0_addr_lim(), - .m_gpio_0_addr_base(), - .m_gpio_0_addr_size(), - .m_gpio_0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_ddr4_0_uncached_addr_base(), - .m_ddr4_0_uncached_addr_size(), - .m_ddr4_0_uncached_addr_lim(), - .m_ddr4_0_cached_addr_base(), - .m_ddr4_0_cached_addr_size(), - .m_ddr4_0_cached_addr_lim(), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), @@ -1066,7 +1045,8 @@ module mkCSR_RegFile(CLK, // rule RL_rl_reset_start assign CAN_FIRE_RL_rl_reset_start = !rg_state ; - assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; + assign WILL_FIRE_RL_rl_reset_start = + CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; // rule RL_rl_mcycle_incr assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; @@ -1117,8 +1097,6 @@ module mkCSR_RegFile(CLK, EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_44_OR_NOT_mav_ETC___d657 && mav_csr_write_csr_addr == 12'h305 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; assign MUX_rg_tdata1$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_44_OR_NOT_mav_ETC___d657 && @@ -1129,7 +1107,7 @@ module mkCSR_RegFile(CLK, (mav_csr_write_csr_addr == 12'hB02 || mav_csr_write_csr_addr == 12'hB82) ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 = - { 9'd0, fixed_up_val_23__h8982 } ; + { 9'd0, fixed_up_val_23__h8802 } ; assign MUX_rg_dcsr$write_1__VAL_3 = { rg_dcsr[31:9], write_dcsr_cause_priv_cause, @@ -1139,7 +1117,7 @@ module mkCSR_RegFile(CLK, { mav_csr_write_word[31], mav_csr_write_word[3:0] } ; assign MUX_rg_mcause$write_1__VAL_3 = { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - exc_code__h8761 } ; + exc_code__h8581 } ; assign MUX_rg_minstret$write_1__VAL_1 = MUX_rw_minstret$wset_1__SEL_1 ? MUX_rw_minstret$wset_1__VAL_1 : @@ -1151,7 +1129,7 @@ module mkCSR_RegFile(CLK, { soc_map$m_mtvec_reset_value[31:2], soc_map$m_mtvec_reset_value[0] } ; assign MUX_rw_minstret$wset_1__VAL_1 = - (mav_csr_write_csr_addr == 12'hB02) ? x__h5648 : x__h5756 ; + (mav_csr_write_csr_addr == 12'hB02) ? x__h5468 : x__h5576 ; // register cfg_verbosity assign cfg_verbosity$D_IN = 4'h0 ; @@ -1160,18 +1138,18 @@ module mkCSR_RegFile(CLK, // register csr_mstatus_rg_mstatus always@(WILL_FIRE_RL_rl_reset_start or MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 or - wordxl1__h4515 or + wordxl1__h4335 or EN_csr_ret_actions or MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 or - EN_csr_trap_actions or x__h8919) + EN_csr_trap_actions or x__h8739) case (1'b1) WILL_FIRE_RL_rl_reset_start: csr_mstatus_rg_mstatus$D_IN = 32'd0; MUX_csr_mstatus_rg_mstatus$write_1__SEL_2: - csr_mstatus_rg_mstatus$D_IN = wordxl1__h4515; + csr_mstatus_rg_mstatus$D_IN = wordxl1__h4335; EN_csr_ret_actions: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_3; - EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = x__h8919; + EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = x__h8739; default: csr_mstatus_rg_mstatus$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -1186,11 +1164,11 @@ module mkCSR_RegFile(CLK, // register rg_dcsr always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_dcsr$write_1__SEL_2 or - new_dcsr__h5935 or + new_dcsr__h5755 or EN_write_dcsr_cause_priv or MUX_rg_dcsr$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_dcsr$D_IN = 32'd1073741843; - MUX_rg_dcsr$write_1__SEL_2: rg_dcsr$D_IN = new_dcsr__h5935; + MUX_rg_dcsr$write_1__SEL_2: rg_dcsr$D_IN = new_dcsr__h5755; EN_write_dcsr_cause_priv: rg_dcsr$D_IN = MUX_rg_dcsr$write_1__VAL_3; default: rg_dcsr$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -1322,7 +1300,7 @@ module mkCSR_RegFile(CLK, // register rg_nmi_vector assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value[31:0] ; - assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; + assign rg_nmi_vector$EN = WILL_FIRE_RL_rl_reset_start ; // register rg_state assign rg_state$D_IN = !EN_server_reset_request_put ; @@ -1331,7 +1309,7 @@ module mkCSR_RegFile(CLK, // register rg_tdata1 assign rg_tdata1$D_IN = - MUX_rg_tdata1$write_1__SEL_1 ? result__h5831 : 32'd0 ; + MUX_rg_tdata1$write_1__SEL_1 ? result__h5651 : 32'd0 ; assign rg_tdata1$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_44_OR_NOT_mav_ETC___d657 && @@ -1363,7 +1341,7 @@ module mkCSR_RegFile(CLK, // submodule csr_mie assign csr_mie$fav_write_misa = 28'd68161797 ; assign csr_mie$fav_write_wordxl = mav_csr_write_word ; - assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; + assign csr_mie$EN_reset = WILL_FIRE_RL_rl_reset_start ; assign csr_mie$EN_fav_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_44_OR_NOT_mav_ETC___d657 && @@ -1379,7 +1357,7 @@ module mkCSR_RegFile(CLK, assign csr_mip$software_interrupt_req_req = software_interrupt_req_set_not_clear ; assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; - assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; + assign csr_mip$EN_reset = WILL_FIRE_RL_rl_reset_start ; assign csr_mip$EN_fav_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_44_OR_NOT_mav_ETC___d657 && @@ -1422,13 +1400,13 @@ module mkCSR_RegFile(CLK, IF_NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_N_ETC___d1484) ; assign IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1144 = (csr_ret_actions_from_priv == 2'b11) ? - _theResult___fst__h9063 : - _theResult___fst__h9264 ; + _theResult___fst__h8883 : + _theResult___fst__h9084 ; assign IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1162 = (csr_ret_actions_from_priv == 2'b11) ? { csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[12:11], - _theResult___fst__h9063 } : - { to_y__h9263, _theResult___fst__h9264 } ; + _theResult___fst__h8883 } : + { to_y__h9083, _theResult___fst__h9084 } ; assign NOT_access_permitted_1_csr_addr_ULT_0xC03_163__ETC___d1257 = (access_permitted_1_csr_addr >= 12'hC03 && access_permitted_1_csr_addr <= 12'hC1F || @@ -1559,18 +1537,18 @@ module mkCSR_RegFile(CLK, !csr_mstatus_rg_mstatus[3]) ; assign NOT_csr_trap_actions_nmi_91_AND_csr_trap_actio_ETC___d1068 = !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 != 4'd0 && - exc_code__h8761 != 4'd1 && - exc_code__h8761 != 4'd2 && - exc_code__h8761 != 4'd3 && - exc_code__h8761 != 4'd4 && - exc_code__h8761 != 4'd5 && - exc_code__h8761 != 4'd6 && - exc_code__h8761 != 4'd7 && - exc_code__h8761 != 4'd8 && - exc_code__h8761 != 4'd9 && - exc_code__h8761 != 4'd10 && - exc_code__h8761 != 4'd11 ; + exc_code__h8581 != 4'd0 && + exc_code__h8581 != 4'd1 && + exc_code__h8581 != 4'd2 && + exc_code__h8581 != 4'd3 && + exc_code__h8581 != 4'd4 && + exc_code__h8581 != 4'd5 && + exc_code__h8581 != 4'd6 && + exc_code__h8581 != 4'd7 && + exc_code__h8581 != 4'd8 && + exc_code__h8581 != 4'd9 && + exc_code__h8581 != 4'd10 && + exc_code__h8581 != 4'd11 ; assign NOT_mav_csr_write_csr_addr_ULT_0xB03_44_25_AND_ETC___d836 = !mav_csr_write_csr_addr_ULT_0xB03___d644 && mav_csr_write_csr_addr_ULE_0xB1F___d645 || @@ -1582,15 +1560,15 @@ module mkCSR_RegFile(CLK, mav_csr_write_csr_addr == 12'hF12 || mav_csr_write_csr_addr == 12'hF13 || mav_csr_write_csr_addr == 12'hF14 ; - assign _theResult___fst__h9063 = + assign _theResult___fst__h8883 = { csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[31:13], 2'd0, csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[10:0] } ; - assign _theResult___fst__h9264 = + assign _theResult___fst__h9084 = { csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[31:9], 1'd0, csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[7:0] } ; - assign b__h9100 = + assign b__h8920 = csr_mstatus_rg_mstatus[{ 3'd1, csr_ret_actions_from_priv }] ; assign csr_mip_fv_read__09_BIT_11_387_AND_csr_mie_fv__ETC___d1398 = csr_mip$fv_read[11] && csr_mie$fv_read[11] && @@ -1635,30 +1613,30 @@ module mkCSR_RegFile(CLK, (interrupt_pending_cur_priv != 2'b11 || csr_mstatus_rg_mstatus[3]) ; assign csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137 = - x__h9096 | mask__h9084 ; + x__h8916 | mask__h8904 ; assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1119 = (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 != 4'd0 && - exc_code__h8761 != 4'd1 && - exc_code__h8761 != 4'd2 && - exc_code__h8761 != 4'd3 && - exc_code__h8761 != 4'd4 && - exc_code__h8761 != 4'd5 && - exc_code__h8761 != 4'd6 && - exc_code__h8761 != 4'd7 && - exc_code__h8761 != 4'd8 && - exc_code__h8761 != 4'd9 && - exc_code__h8761 != 4'd11 && - exc_code__h8761 != 4'd12 && - exc_code__h8761 != 4'd13 && - exc_code__h8761 != 4'd15 ; - assign exc_code__h8761 = + exc_code__h8581 != 4'd0 && + exc_code__h8581 != 4'd1 && + exc_code__h8581 != 4'd2 && + exc_code__h8581 != 4'd3 && + exc_code__h8581 != 4'd4 && + exc_code__h8581 != 4'd5 && + exc_code__h8581 != 4'd6 && + exc_code__h8581 != 4'd7 && + exc_code__h8581 != 4'd8 && + exc_code__h8581 != 4'd9 && + exc_code__h8581 != 4'd11 && + exc_code__h8581 != 4'd12 && + exc_code__h8581 != 4'd13 && + exc_code__h8581 != 4'd15 ; + assign exc_code__h8581 = csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; - assign exc_pc___1__h8148 = exc_pc__h8095 + vector_offset__h8096 ; - assign exc_pc__h7884 = { rg_mtvec[30:1], 2'd0 } ; - assign exc_pc__h8095 = - csr_trap_actions_nmi ? rg_nmi_vector : exc_pc__h7884 ; - assign fixed_up_val_23__h4556 = + assign exc_pc___1__h7968 = exc_pc__h7915 + vector_offset__h7916 ; + assign exc_pc__h7704 = { rg_mtvec[30:1], 2'd0 } ; + assign exc_pc__h7915 = + csr_trap_actions_nmi ? rg_nmi_vector : exc_pc__h7704 ; + assign fixed_up_val_23__h4376 = { mav_csr_write_word[22:17], 4'd0, (mav_csr_write_word[12:11] == 2'b11) ? @@ -1670,10 +1648,10 @@ module mkCSR_RegFile(CLK, 2'd0, mav_csr_write_word[3:2], 2'd0 } ; - assign fixed_up_val_23__h7323 = + assign fixed_up_val_23__h7143 = { csr_mstatus_rg_mstatus[22:17], 4'd0, - mpp__h8189, + mpp__h8009, csr_mstatus_rg_mstatus[10:9], 1'd0, csr_mstatus_rg_mstatus[3], @@ -1681,7 +1659,7 @@ module mkCSR_RegFile(CLK, 3'd0, csr_mstatus_rg_mstatus[2], 2'd0 } ; - assign fixed_up_val_23__h8982 = + assign fixed_up_val_23__h8802 = { IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1144[22:17], 4'd0, (IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1144[12:11] == @@ -1694,9 +1672,9 @@ module mkCSR_RegFile(CLK, 2'd0, IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1144[3:2], 2'd0 } ; - assign ie_from_x__h9047 = { 4'd0, csr_ret_actions_from_priv } ; - assign mask__h9084 = 32'd1 << pie_from_x__h9048 ; - assign mask__h9101 = 32'd1 << ie_from_x__h9047 ; + assign ie_from_x__h8867 = { 4'd0, csr_ret_actions_from_priv } ; + assign mask__h8904 = 32'd1 << pie_from_x__h8868 ; + assign mask__h8921 = 32'd1 << ie_from_x__h8867 ; assign mav_csr_write_csr_addr_ULE_0x33F___d653 = mav_csr_write_csr_addr <= 12'h33F ; assign mav_csr_write_csr_addr_ULE_0xB1F___d645 = @@ -1762,47 +1740,47 @@ module mkCSR_RegFile(CLK, mav_csr_write_csr_addr < 12'hB03 ; assign mav_csr_write_csr_addr_ULT_0xB83___d648 = mav_csr_write_csr_addr < 12'hB83 ; - assign mpp__h8189 = + assign mpp__h8009 = (csr_trap_actions_from_priv == 2'b11) ? csr_trap_actions_from_priv : 2'b0 ; - assign new_dcsr__h5935 = + assign new_dcsr__h5755 = { rg_dcsr[31:16], mav_csr_write_word[15:9], rg_dcsr[8:5], mav_csr_write_word[4], rg_dcsr[3], mav_csr_write_word[2:0] } ; - assign pie_from_x__h9048 = { 4'd1, csr_ret_actions_from_priv } ; - assign result__h5831 = { 4'd0, mav_csr_write_word[27:0] } ; - assign to_y__h9263 = + assign pie_from_x__h8868 = { 4'd1, csr_ret_actions_from_priv } ; + assign result__h5651 = { 4'd0, mav_csr_write_word[27:0] } ; + assign to_y__h9083 = { 1'b0, csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[8] } ; - assign v__h4998 = + assign v__h4818 = { mav_csr_write_word[31:2], 1'b0, mav_csr_write_word[0] } ; - assign v__h5060 = { 29'd0, mav_csr_write_word[2:0] } ; - assign v__h5216 = + assign v__h4880 = { 29'd0, mav_csr_write_word[2:0] } ; + assign v__h5036 = { mav_csr_write_word[31], 27'd0, mav_csr_write_word[3:0] } ; - assign val__h9102 = { 31'd0, b__h9100 } << ie_from_x__h9047 ; - assign vector_offset__h8096 = { 26'd0, csr_trap_actions_exc_code, 2'd0 } ; - assign wordxl1__h4515 = { 9'd0, fixed_up_val_23__h4556 } ; - assign x__h5648 = { rg_minstret[63:32], mav_csr_write_word } ; - assign x__h5756 = { mav_csr_write_word, rg_minstret[31:0] } ; - assign x__h6695 = + assign val__h8922 = { 31'd0, b__h8920 } << ie_from_x__h8867 ; + assign vector_offset__h7916 = { 26'd0, csr_trap_actions_exc_code, 2'd0 } ; + assign wordxl1__h4335 = { 9'd0, fixed_up_val_23__h4376 } ; + assign x__h5468 = { rg_minstret[63:32], mav_csr_write_word } ; + assign x__h5576 = { mav_csr_write_word, rg_minstret[31:0] } ; + assign x__h6515 = (csr_trap_actions_interrupt && !csr_trap_actions_nmi && rg_mtvec[0]) ? - exc_pc___1__h8148 : - exc_pc__h8095 ; - assign x__h8919 = { 9'd0, fixed_up_val_23__h7323 } ; - assign x__h8920 = + exc_pc___1__h7968 : + exc_pc__h7915 ; + assign x__h8739 = { 9'd0, fixed_up_val_23__h7143 } ; + assign x__h8740 = { !csr_trap_actions_nmi && csr_trap_actions_interrupt, 27'd0, - exc_code__h8761 } ; - assign x__h9083 = x__h9113 | val__h9102 ; - assign x__h9096 = x__h9083 & y__h9097 ; - assign x__h9113 = csr_mstatus_rg_mstatus & y__h9114 ; - assign y__h9097 = ~mask__h9084 ; - assign y__h9114 = ~mask__h9101 ; + exc_code__h8581 } ; + assign x__h8903 = x__h8933 | val__h8922 ; + assign x__h8916 = x__h8903 & y__h8917 ; + assign x__h8933 = csr_mstatus_rg_mstatus & y__h8934 ; + assign y__h8917 = ~mask__h8904 ; + assign y__h8934 = ~mask__h8921 ; always@(read_csr_csr_addr or rg_dscratch1 or csr_mstatus_rg_mstatus or @@ -2062,17 +2040,17 @@ module mkCSR_RegFile(CLK, endcase end always@(mav_csr_write_csr_addr or - wordxl1__h4515 or + wordxl1__h4335 or csr_mie$fav_write or - v__h4998 or - v__h5060 or + v__h4818 or + v__h4880 or mav_csr_write_word or - v__h5216 or csr_mip$fav_write or result__h5831 or new_dcsr__h5935) + v__h5036 or csr_mip$fav_write or result__h5651 or new_dcsr__h5755) begin case (mav_csr_write_csr_addr) 12'h300: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - wordxl1__h4515; + wordxl1__h4335; 12'h301, 12'h7A0: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = 32'd0; 12'h304: @@ -2080,10 +2058,10 @@ module mkCSR_RegFile(CLK, csr_mie$fav_write; 12'h305: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - v__h4998; + v__h4818; 12'h306: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - v__h5060; + v__h4880; 12'h340, 12'h341, 12'h343, @@ -2100,16 +2078,16 @@ module mkCSR_RegFile(CLK, mav_csr_write_word; 12'h342: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - v__h5216; + v__h5036; 12'h344: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = csr_mip$fav_write; 12'h7A1: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - result__h5831; + result__h5651; 12'h7B0: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - new_dcsr__h5935; + new_dcsr__h5755; default: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = 32'd0; endcase @@ -2420,7 +2398,7 @@ module mkCSR_RegFile(CLK, $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823) - $write(" Return: new pc 0x%0h ", x__h6695); + $write(" Return: new pc 0x%0h ", x__h6515); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823) $write(" new mstatus:"); @@ -2456,7 +2434,7 @@ module mkCSR_RegFile(CLK, $write(" fs:%0d", 2'd0); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823) - $write(" mpp:%0d", mpp__h8189); + $write(" mpp:%0d", mpp__h8009); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823) $write(" spp:%0d", 1'd0); @@ -2476,152 +2454,152 @@ module mkCSR_RegFile(CLK, if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd0) + exc_code__h8581 == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd1) + exc_code__h8581 == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd2) + exc_code__h8581 == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd3) + exc_code__h8581 == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd4) + exc_code__h8581 == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd5) + exc_code__h8581 == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd6) + exc_code__h8581 == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd7) + exc_code__h8581 == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd8) + exc_code__h8581 == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd9) + exc_code__h8581 == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd10) + exc_code__h8581 == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd11) + exc_code__h8581 == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && NOT_csr_trap_actions_nmi_91_AND_csr_trap_actio_ETC___d1068) - $write("unknown interrupt Exc_Code %d", exc_code__h8761); + $write("unknown interrupt Exc_Code %d", exc_code__h8581); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd0) + exc_code__h8581 == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd1) + exc_code__h8581 == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd2) + exc_code__h8581 == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd3) + exc_code__h8581 == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd4) + exc_code__h8581 == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd5) + exc_code__h8581 == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd6) + exc_code__h8581 == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd7) + exc_code__h8581 == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd8) + exc_code__h8581 == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd9) + exc_code__h8581 == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd11) + exc_code__h8581 == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd12) + exc_code__h8581 == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd13) + exc_code__h8581 == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd15) + exc_code__h8581 == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1119) - $write("unknown trap Exc_Code %d", exc_code__h8761); + $write("unknown trap Exc_Code %d", exc_code__h8581); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823) $write(" new priv %0d", 2'b11); diff --git a/src_SSITH_P1/Verilog_RTL/mkCore.v b/src_SSITH_P1/Verilog_RTL/mkCore.v index 5373dd59..a7347f18 100644 --- a/src_SSITH_P1/Verilog_RTL/mkCore.v +++ b/src_SSITH_P1/Verilog_RTL/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:57 BST 2019 // // // Ports: @@ -10,36 +10,35 @@ // RDY_cpu_reset_server_request_put O 1 reg // cpu_reset_server_response_get O 1 reg // RDY_cpu_reset_server_response_get O 1 reg +// cpu_imem_master_awid O 5 +// cpu_imem_master_awaddr O 64 +// cpu_imem_master_awlen O 8 +// cpu_imem_master_awsize O 3 +// cpu_imem_master_awburst O 2 +// cpu_imem_master_awlock O 1 +// cpu_imem_master_awcache O 4 +// cpu_imem_master_awprot O 3 +// cpu_imem_master_awqos O 4 +// cpu_imem_master_awregion O 4 // cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg +// cpu_imem_master_wdata O 64 +// cpu_imem_master_wstrb O 8 +// cpu_imem_master_wlast O 1 // cpu_imem_master_wvalid O 1 -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg // cpu_imem_master_bready O 1 +// cpu_imem_master_arid O 5 +// cpu_imem_master_araddr O 64 +// cpu_imem_master_arlen O 8 +// cpu_imem_master_arsize O 3 +// cpu_imem_master_arburst O 2 +// cpu_imem_master_arlock O 1 +// cpu_imem_master_arcache O 4 +// cpu_imem_master_arprot O 3 +// cpu_imem_master_arqos O 4 +// cpu_imem_master_arregion O 4 // cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg // cpu_imem_master_rready O 1 -// cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg +// cpu_dmem_master_awid O 5 reg // cpu_dmem_master_awaddr O 64 reg // cpu_dmem_master_awlen O 8 reg // cpu_dmem_master_awsize O 3 reg @@ -49,13 +48,13 @@ // cpu_dmem_master_awprot O 3 reg // cpu_dmem_master_awqos O 4 reg // cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg +// cpu_dmem_master_awvalid O 1 reg // cpu_dmem_master_wdata O 64 reg // cpu_dmem_master_wstrb O 8 reg // cpu_dmem_master_wlast O 1 reg +// cpu_dmem_master_wvalid O 1 reg // cpu_dmem_master_bready O 1 reg -// cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg +// cpu_dmem_master_arid O 5 reg // cpu_dmem_master_araddr O 64 reg // cpu_dmem_master_arlen O 8 reg // cpu_dmem_master_arsize O 3 reg @@ -65,6 +64,7 @@ // cpu_dmem_master_arprot O 3 reg // cpu_dmem_master_arqos O 4 reg // cpu_dmem_master_arregion O 4 reg +// cpu_dmem_master_arvalid O 1 reg // cpu_dmem_master_rready O 1 reg // tv_verifier_info_get_get O 608 reg // RDY_tv_verifier_info_get_get O 1 reg @@ -82,23 +82,19 @@ // cpu_reset_server_request_put I 1 reg // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg +// cpu_imem_master_bid I 5 +// cpu_imem_master_bresp I 2 // cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg +// cpu_imem_master_rid I 5 +// cpu_imem_master_rdata I 64 +// cpu_imem_master_rresp I 2 +// cpu_imem_master_rlast I 1 // cpu_dmem_master_awready I 1 // cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg +// cpu_dmem_master_bid I 5 reg // cpu_dmem_master_bresp I 2 reg // cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg +// cpu_dmem_master_rid I 5 reg // cpu_dmem_master_rdata I 64 reg // cpu_dmem_master_rresp I 2 reg // cpu_dmem_master_rlast I 1 reg @@ -125,6 +121,10 @@ // ndm_reset_client_response_put I 1 reg // EN_set_verbosity I 1 // EN_cpu_reset_server_request_put I 1 +// cpu_imem_master_bvalid I 1 +// cpu_imem_master_rvalid I 1 +// cpu_dmem_master_bvalid I 1 +// cpu_dmem_master_rvalid I 1 // EN_dm_dmi_read_addr I 1 // EN_dm_dmi_write I 1 // EN_ndm_reset_client_response_put I 1 @@ -134,8 +134,66 @@ // EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_rready +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arid +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_araddr +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arlen +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arsize +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arburst +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arlock +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arcache +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arprot +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arqos +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arregion +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_aruser +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arvalid // (dm_dmi_read_addr_dm_addr, EN_dm_dmi_read_addr) -> RDY_dm_dmi_read_data // (dm_dmi_read_addr_dm_addr, // EN_dm_dmi_read_addr, @@ -172,8 +230,6 @@ module mkCore(CLK, cpu_reset_server_response_get, RDY_cpu_reset_server_response_get, - cpu_imem_master_awvalid, - cpu_imem_master_awid, cpu_imem_master_awaddr, @@ -194,9 +250,9 @@ module mkCore(CLK, cpu_imem_master_awregion, - cpu_imem_master_awready, + cpu_imem_master_awvalid, - cpu_imem_master_wvalid, + cpu_imem_master_awready, cpu_imem_master_wdata, @@ -204,16 +260,16 @@ module mkCore(CLK, cpu_imem_master_wlast, + cpu_imem_master_wvalid, + cpu_imem_master_wready, - cpu_imem_master_bvalid, cpu_imem_master_bid, cpu_imem_master_bresp, + cpu_imem_master_bvalid, cpu_imem_master_bready, - cpu_imem_master_arvalid, - cpu_imem_master_arid, cpu_imem_master_araddr, @@ -234,18 +290,18 @@ module mkCore(CLK, cpu_imem_master_arregion, + cpu_imem_master_arvalid, + cpu_imem_master_arready, - cpu_imem_master_rvalid, cpu_imem_master_rid, cpu_imem_master_rdata, cpu_imem_master_rresp, cpu_imem_master_rlast, + cpu_imem_master_rvalid, cpu_imem_master_rready, - cpu_dmem_master_awvalid, - cpu_dmem_master_awid, cpu_dmem_master_awaddr, @@ -266,9 +322,9 @@ module mkCore(CLK, cpu_dmem_master_awregion, - cpu_dmem_master_awready, + cpu_dmem_master_awvalid, - cpu_dmem_master_wvalid, + cpu_dmem_master_awready, cpu_dmem_master_wdata, @@ -276,16 +332,16 @@ module mkCore(CLK, cpu_dmem_master_wlast, + cpu_dmem_master_wvalid, + cpu_dmem_master_wready, - cpu_dmem_master_bvalid, cpu_dmem_master_bid, cpu_dmem_master_bresp, + cpu_dmem_master_bvalid, cpu_dmem_master_bready, - cpu_dmem_master_arvalid, - cpu_dmem_master_arid, cpu_dmem_master_araddr, @@ -306,13 +362,15 @@ module mkCore(CLK, cpu_dmem_master_arregion, + cpu_dmem_master_arvalid, + cpu_dmem_master_arready, - cpu_dmem_master_rvalid, cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast, + cpu_dmem_master_rvalid, cpu_dmem_master_rready, @@ -393,226 +451,226 @@ module mkCore(CLK, output cpu_reset_server_response_get; output RDY_cpu_reset_server_response_get; - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; + // value method cpu_imem_master_aw_awid + output [4 : 0] cpu_imem_master_awid; - // value method cpu_imem_master_m_awaddr + // value method cpu_imem_master_aw_awaddr output [63 : 0] cpu_imem_master_awaddr; - // value method cpu_imem_master_m_awlen + // value method cpu_imem_master_aw_awlen output [7 : 0] cpu_imem_master_awlen; - // value method cpu_imem_master_m_awsize + // value method cpu_imem_master_aw_awsize output [2 : 0] cpu_imem_master_awsize; - // value method cpu_imem_master_m_awburst + // value method cpu_imem_master_aw_awburst output [1 : 0] cpu_imem_master_awburst; - // value method cpu_imem_master_m_awlock + // value method cpu_imem_master_aw_awlock output cpu_imem_master_awlock; - // value method cpu_imem_master_m_awcache + // value method cpu_imem_master_aw_awcache output [3 : 0] cpu_imem_master_awcache; - // value method cpu_imem_master_m_awprot + // value method cpu_imem_master_aw_awprot output [2 : 0] cpu_imem_master_awprot; - // value method cpu_imem_master_m_awqos + // value method cpu_imem_master_aw_awqos output [3 : 0] cpu_imem_master_awqos; - // value method cpu_imem_master_m_awregion + // value method cpu_imem_master_aw_awregion output [3 : 0] cpu_imem_master_awregion; - // value method cpu_imem_master_m_awuser + // value method cpu_imem_master_aw_awuser - // action method cpu_imem_master_m_awready - input cpu_imem_master_awready; + // value method cpu_imem_master_aw_awvalid + output cpu_imem_master_awvalid; - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; + // action method cpu_imem_master_aw_awready + input cpu_imem_master_awready; - // value method cpu_imem_master_m_wdata + // value method cpu_imem_master_w_wdata output [63 : 0] cpu_imem_master_wdata; - // value method cpu_imem_master_m_wstrb + // value method cpu_imem_master_w_wstrb output [7 : 0] cpu_imem_master_wstrb; - // value method cpu_imem_master_m_wlast + // value method cpu_imem_master_w_wlast output cpu_imem_master_wlast; - // value method cpu_imem_master_m_wuser + // value method cpu_imem_master_w_wuser + + // value method cpu_imem_master_w_wvalid + output cpu_imem_master_wvalid; - // action method cpu_imem_master_m_wready + // action method cpu_imem_master_w_wready input cpu_imem_master_wready; - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; + // action method cpu_imem_master_b_bflit + input [4 : 0] cpu_imem_master_bid; input [1 : 0] cpu_imem_master_bresp; + input cpu_imem_master_bvalid; - // value method cpu_imem_master_m_bready + // value method cpu_imem_master_b_bready output cpu_imem_master_bready; - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; - - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; + // value method cpu_imem_master_ar_arid + output [4 : 0] cpu_imem_master_arid; - // value method cpu_imem_master_m_araddr + // value method cpu_imem_master_ar_araddr output [63 : 0] cpu_imem_master_araddr; - // value method cpu_imem_master_m_arlen + // value method cpu_imem_master_ar_arlen output [7 : 0] cpu_imem_master_arlen; - // value method cpu_imem_master_m_arsize + // value method cpu_imem_master_ar_arsize output [2 : 0] cpu_imem_master_arsize; - // value method cpu_imem_master_m_arburst + // value method cpu_imem_master_ar_arburst output [1 : 0] cpu_imem_master_arburst; - // value method cpu_imem_master_m_arlock + // value method cpu_imem_master_ar_arlock output cpu_imem_master_arlock; - // value method cpu_imem_master_m_arcache + // value method cpu_imem_master_ar_arcache output [3 : 0] cpu_imem_master_arcache; - // value method cpu_imem_master_m_arprot + // value method cpu_imem_master_ar_arprot output [2 : 0] cpu_imem_master_arprot; - // value method cpu_imem_master_m_arqos + // value method cpu_imem_master_ar_arqos output [3 : 0] cpu_imem_master_arqos; - // value method cpu_imem_master_m_arregion + // value method cpu_imem_master_ar_arregion output [3 : 0] cpu_imem_master_arregion; - // value method cpu_imem_master_m_aruser + // value method cpu_imem_master_ar_aruser + + // value method cpu_imem_master_ar_arvalid + output cpu_imem_master_arvalid; - // action method cpu_imem_master_m_arready + // action method cpu_imem_master_ar_arready input cpu_imem_master_arready; - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; + // action method cpu_imem_master_r_rflit + input [4 : 0] cpu_imem_master_rid; input [63 : 0] cpu_imem_master_rdata; input [1 : 0] cpu_imem_master_rresp; input cpu_imem_master_rlast; + input cpu_imem_master_rvalid; - // value method cpu_imem_master_m_rready + // value method cpu_imem_master_r_rready output cpu_imem_master_rready; - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; - - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; + // value method cpu_dmem_master_aw_awid + output [4 : 0] cpu_dmem_master_awid; - // value method cpu_dmem_master_m_awaddr + // value method cpu_dmem_master_aw_awaddr output [63 : 0] cpu_dmem_master_awaddr; - // value method cpu_dmem_master_m_awlen + // value method cpu_dmem_master_aw_awlen output [7 : 0] cpu_dmem_master_awlen; - // value method cpu_dmem_master_m_awsize + // value method cpu_dmem_master_aw_awsize output [2 : 0] cpu_dmem_master_awsize; - // value method cpu_dmem_master_m_awburst + // value method cpu_dmem_master_aw_awburst output [1 : 0] cpu_dmem_master_awburst; - // value method cpu_dmem_master_m_awlock + // value method cpu_dmem_master_aw_awlock output cpu_dmem_master_awlock; - // value method cpu_dmem_master_m_awcache + // value method cpu_dmem_master_aw_awcache output [3 : 0] cpu_dmem_master_awcache; - // value method cpu_dmem_master_m_awprot + // value method cpu_dmem_master_aw_awprot output [2 : 0] cpu_dmem_master_awprot; - // value method cpu_dmem_master_m_awqos + // value method cpu_dmem_master_aw_awqos output [3 : 0] cpu_dmem_master_awqos; - // value method cpu_dmem_master_m_awregion + // value method cpu_dmem_master_aw_awregion output [3 : 0] cpu_dmem_master_awregion; - // value method cpu_dmem_master_m_awuser + // value method cpu_dmem_master_aw_awuser - // action method cpu_dmem_master_m_awready - input cpu_dmem_master_awready; + // value method cpu_dmem_master_aw_awvalid + output cpu_dmem_master_awvalid; - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; + // action method cpu_dmem_master_aw_awready + input cpu_dmem_master_awready; - // value method cpu_dmem_master_m_wdata + // value method cpu_dmem_master_w_wdata output [63 : 0] cpu_dmem_master_wdata; - // value method cpu_dmem_master_m_wstrb + // value method cpu_dmem_master_w_wstrb output [7 : 0] cpu_dmem_master_wstrb; - // value method cpu_dmem_master_m_wlast + // value method cpu_dmem_master_w_wlast output cpu_dmem_master_wlast; - // value method cpu_dmem_master_m_wuser + // value method cpu_dmem_master_w_wuser + + // value method cpu_dmem_master_w_wvalid + output cpu_dmem_master_wvalid; - // action method cpu_dmem_master_m_wready + // action method cpu_dmem_master_w_wready input cpu_dmem_master_wready; - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; + // action method cpu_dmem_master_b_bflit + input [4 : 0] cpu_dmem_master_bid; input [1 : 0] cpu_dmem_master_bresp; + input cpu_dmem_master_bvalid; - // value method cpu_dmem_master_m_bready + // value method cpu_dmem_master_b_bready output cpu_dmem_master_bready; - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; - - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; + // value method cpu_dmem_master_ar_arid + output [4 : 0] cpu_dmem_master_arid; - // value method cpu_dmem_master_m_araddr + // value method cpu_dmem_master_ar_araddr output [63 : 0] cpu_dmem_master_araddr; - // value method cpu_dmem_master_m_arlen + // value method cpu_dmem_master_ar_arlen output [7 : 0] cpu_dmem_master_arlen; - // value method cpu_dmem_master_m_arsize + // value method cpu_dmem_master_ar_arsize output [2 : 0] cpu_dmem_master_arsize; - // value method cpu_dmem_master_m_arburst + // value method cpu_dmem_master_ar_arburst output [1 : 0] cpu_dmem_master_arburst; - // value method cpu_dmem_master_m_arlock + // value method cpu_dmem_master_ar_arlock output cpu_dmem_master_arlock; - // value method cpu_dmem_master_m_arcache + // value method cpu_dmem_master_ar_arcache output [3 : 0] cpu_dmem_master_arcache; - // value method cpu_dmem_master_m_arprot + // value method cpu_dmem_master_ar_arprot output [2 : 0] cpu_dmem_master_arprot; - // value method cpu_dmem_master_m_arqos + // value method cpu_dmem_master_ar_arqos output [3 : 0] cpu_dmem_master_arqos; - // value method cpu_dmem_master_m_arregion + // value method cpu_dmem_master_ar_arregion output [3 : 0] cpu_dmem_master_arregion; - // value method cpu_dmem_master_m_aruser + // value method cpu_dmem_master_ar_aruser + + // value method cpu_dmem_master_ar_arvalid + output cpu_dmem_master_arvalid; - // action method cpu_dmem_master_m_arready + // action method cpu_dmem_master_ar_arready input cpu_dmem_master_arready; - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; + // action method cpu_dmem_master_r_rflit + input [4 : 0] cpu_dmem_master_rid; input [63 : 0] cpu_dmem_master_rdata; input [1 : 0] cpu_dmem_master_rresp; input cpu_dmem_master_rlast; + input cpu_dmem_master_rvalid; - // value method cpu_dmem_master_m_rready + // value method cpu_dmem_master_r_rready output cpu_dmem_master_rready; // action method core_external_interrupt_sources_0_m_interrupt_req @@ -712,20 +770,20 @@ module mkCore(CLK, cpu_imem_master_arlen, cpu_imem_master_awlen, cpu_imem_master_wstrb; + wire [4 : 0] cpu_dmem_master_arid, + cpu_dmem_master_awid, + cpu_imem_master_arid, + cpu_imem_master_awid; wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, cpu_dmem_master_arqos, cpu_dmem_master_arregion, cpu_dmem_master_awcache, - cpu_dmem_master_awid, cpu_dmem_master_awqos, cpu_dmem_master_awregion, cpu_imem_master_arcache, - cpu_imem_master_arid, cpu_imem_master_arqos, cpu_imem_master_arregion, cpu_imem_master_awcache, - cpu_imem_master_awid, cpu_imem_master_awqos, cpu_imem_master_awregion; wire [2 : 0] cpu_dmem_master_arprot, @@ -768,6 +826,293 @@ module mkCore(CLK, cpu_reset_server_response_get, ndm_reset_client_request_get; + // inlined wires + wire [171 : 0] split_0_doPut$wget, split_1_doPut$wget, split_2_doPut$wget; + wire [97 : 0] ssNoSynth_0_ar_buffer_enqw$wget, + ssNoSynth_1_ar_buffer_enqw$wget, + ssNoSynth_1_aw_buffer_enqw$wget, + ssNoSynth_2_ar_buffer_enqw$wget, + ssNoSynth_2_aw_buffer_enqw$wget; + wire [96 : 0] ifcs_0_1_noRoute_currentReq$port0__write_1, + ifcs_0_1_noRoute_currentReq$port1__read, + ifcs_0_noRoute_inner_currentReq$port0__write_1, + ifcs_0_noRoute_inner_currentReq$port1__read, + ifcs_1_1_noRoute_currentReq$port0__write_1, + ifcs_1_1_noRoute_currentReq$port1__read, + ifcs_1_noRoute_inner_currentReq$port0__write_1, + ifcs_1_noRoute_inner_currentReq$port1__read; + wire [72 : 0] ssNoSynth_1_w_buffer_enqw$wget, + ssNoSynth_2_w_buffer_enqw$wget; + wire [70 : 0] msNoSynth_0_r_buffer_enqw$wget, + msNoSynth_1_r_buffer_enqw$wget; + wire [8 : 0] ifcs_0_1_noRoute_flitCount$port0__write_1, + ifcs_0_1_noRoute_flitCount$port1__write_1, + ifcs_0_1_noRoute_flitCount$port2__read, + ifcs_1_1_noRoute_flitCount$port0__write_1, + ifcs_1_1_noRoute_flitCount$port1__write_1, + ifcs_1_1_noRoute_flitCount$port2__read; + wire [5 : 0] msNoSynth_0_b_buffer_enqw$wget, msNoSynth_1_b_buffer_enqw$wget; + wire flitToSink_0$whas, + flitToSink_1$whas, + flitToSink_1_0$whas, + flitToSink_1_0_1$whas, + flitToSink_1_1$whas, + flitToSink_1_1_0$whas, + flitToSink_1_1_1$whas, + flitToSink_1_1_1_1$whas, + flitToSink_1_2$whas, + flitToSink_2$whas, + ifcs_0_noRoute_inner_currentReq$EN_port0__write, + ifcs_0_noRoute_inner_pendingReq$EN_port0__write, + ifcs_0_noRoute_inner_pendingReq$port1__read, + ifcs_0_noRoute_inner_pendingReq$port2__read, + ifcs_1_noRoute_inner_currentReq$EN_port0__write, + ifcs_1_noRoute_inner_pendingReq$EN_port0__write, + ifcs_1_noRoute_inner_pendingReq$port1__read, + ifcs_1_noRoute_inner_pendingReq$port2__read, + merged_0_doDrop$whas, + merged_1_doDrop$whas, + msNoSynth_0_ar_dwReady$whas, + msNoSynth_0_b_buffer_enqw$whas, + msNoSynth_0_r_buffer_enqw$whas, + msNoSynth_0_w_dwReady$whas, + msNoSynth_1_ar_dwReady$whas, + msNoSynth_1_b_buffer_enqw$whas, + msNoSynth_1_r_buffer_enqw$whas, + msNoSynth_1_w_dwReady$whas, + reqWires_0$wget, + reqWires_1$wget, + reqWires_1_0$wget, + reqWires_1_0_1$wget, + reqWires_1_1$wget, + reqWires_1_1_0$wget, + reqWires_1_1_1$wget, + reqWires_1_1_1_1$wget, + reqWires_1_1_2$wget, + reqWires_1_2$wget, + sourceSelect_1_0$whas, + sourceSelect_1_0_1$whas, + sourceSelect_1_1$whas, + sourceSelect_1_1_1$whas, + sourceSelect_1_2$whas, + ssNoSynth_0_b_dwReady$whas, + ssNoSynth_0_r_dwReady$whas, + ssNoSynth_0_w_buffer_enqw$whas, + ssNoSynth_1_b_dwReady$whas, + ssNoSynth_1_r_dwReady$whas, + ssNoSynth_1_w_buffer_enqw$whas, + ssNoSynth_2_b_dwReady$whas, + ssNoSynth_2_r_dwReady$whas, + ssNoSynth_2_w_buffer_enqw$whas; + + // register activeSource_0 + reg activeSource_0; + wire activeSource_0$D_IN, activeSource_0$EN; + + // register activeSource_1 + reg activeSource_1; + wire activeSource_1$D_IN, activeSource_1$EN; + + // register activeSource_1_0 + reg activeSource_1_0; + wire activeSource_1_0$D_IN, activeSource_1_0$EN; + + // register activeSource_1_0_1 + reg activeSource_1_0_1; + wire activeSource_1_0_1$D_IN, activeSource_1_0_1$EN; + + // register activeSource_1_1 + reg activeSource_1_1; + wire activeSource_1_1$D_IN, activeSource_1_1$EN; + + // register activeSource_1_1_0 + reg activeSource_1_1_0; + reg activeSource_1_1_0$D_IN; + wire activeSource_1_1_0$EN; + + // register activeSource_1_1_1 + reg activeSource_1_1_1; + wire activeSource_1_1_1$D_IN, activeSource_1_1_1$EN; + + // register activeSource_1_1_1_1 + reg activeSource_1_1_1_1; + reg activeSource_1_1_1_1$D_IN; + wire activeSource_1_1_1_1$EN; + + // register activeSource_1_1_2 + reg activeSource_1_1_2; + reg activeSource_1_1_2$D_IN; + wire activeSource_1_1_2$EN; + + // register activeSource_1_2 + reg activeSource_1_2; + wire activeSource_1_2$D_IN, activeSource_1_2$EN; + + // register arbiter_1_1_firstHot + reg arbiter_1_1_firstHot; + wire arbiter_1_1_firstHot$D_IN, arbiter_1_1_firstHot$EN; + + // register arbiter_1_1_lastSelect + reg arbiter_1_1_lastSelect; + wire arbiter_1_1_lastSelect$D_IN, arbiter_1_1_lastSelect$EN; + + // register arbiter_1_1_lastSelect_1 + reg arbiter_1_1_lastSelect_1; + wire arbiter_1_1_lastSelect_1$D_IN, arbiter_1_1_lastSelect_1$EN; + + // register arbiter_1_firstHot + reg arbiter_1_firstHot; + wire arbiter_1_firstHot$D_IN, arbiter_1_firstHot$EN; + + // register arbiter_1_firstHot_1 + reg arbiter_1_firstHot_1; + wire arbiter_1_firstHot_1$D_IN, arbiter_1_firstHot_1$EN; + + // register arbiter_1_lastSelect + reg arbiter_1_lastSelect; + wire arbiter_1_lastSelect$D_IN, arbiter_1_lastSelect$EN; + + // register arbiter_1_lastSelect_1 + reg arbiter_1_lastSelect_1; + wire arbiter_1_lastSelect_1$D_IN, arbiter_1_lastSelect_1$EN; + + // register arbiter_1_lastSelect_2 + reg arbiter_1_lastSelect_2; + wire arbiter_1_lastSelect_2$D_IN, arbiter_1_lastSelect_2$EN; + + // register arbiter_firstHot + reg arbiter_firstHot; + wire arbiter_firstHot$D_IN, arbiter_firstHot$EN; + + // register arbiter_lastSelect + reg arbiter_lastSelect; + wire arbiter_lastSelect$D_IN, arbiter_lastSelect$EN; + + // register ifcs_0_1_noRoute_currentReq + reg [96 : 0] ifcs_0_1_noRoute_currentReq; + wire [96 : 0] ifcs_0_1_noRoute_currentReq$D_IN; + wire ifcs_0_1_noRoute_currentReq$EN; + + // register ifcs_0_1_noRoute_flitCount + reg [8 : 0] ifcs_0_1_noRoute_flitCount; + wire [8 : 0] ifcs_0_1_noRoute_flitCount$D_IN; + wire ifcs_0_1_noRoute_flitCount$EN; + + // register ifcs_0_1_state + reg [1 : 0] ifcs_0_1_state; + wire [1 : 0] ifcs_0_1_state$D_IN; + wire ifcs_0_1_state$EN; + + // register ifcs_0_1_state_1 + reg ifcs_0_1_state_1; + wire ifcs_0_1_state_1$D_IN, ifcs_0_1_state_1$EN; + + // register ifcs_0_noRoute_inner_currentReq + reg [96 : 0] ifcs_0_noRoute_inner_currentReq; + wire [96 : 0] ifcs_0_noRoute_inner_currentReq$D_IN; + wire ifcs_0_noRoute_inner_currentReq$EN; + + // register ifcs_0_noRoute_inner_pendingReq + reg ifcs_0_noRoute_inner_pendingReq; + wire ifcs_0_noRoute_inner_pendingReq$D_IN, + ifcs_0_noRoute_inner_pendingReq$EN; + + // register ifcs_0_state + reg [1 : 0] ifcs_0_state; + reg [1 : 0] ifcs_0_state$D_IN; + wire ifcs_0_state$EN; + + // register ifcs_0_state_1 + reg ifcs_0_state_1; + wire ifcs_0_state_1$D_IN, ifcs_0_state_1$EN; + + // register ifcs_1_1_noRoute_currentReq + reg [96 : 0] ifcs_1_1_noRoute_currentReq; + wire [96 : 0] ifcs_1_1_noRoute_currentReq$D_IN; + wire ifcs_1_1_noRoute_currentReq$EN; + + // register ifcs_1_1_noRoute_flitCount + reg [8 : 0] ifcs_1_1_noRoute_flitCount; + wire [8 : 0] ifcs_1_1_noRoute_flitCount$D_IN; + wire ifcs_1_1_noRoute_flitCount$EN; + + // register ifcs_1_1_state + reg [1 : 0] ifcs_1_1_state; + wire [1 : 0] ifcs_1_1_state$D_IN; + wire ifcs_1_1_state$EN; + + // register ifcs_1_1_state_1 + reg ifcs_1_1_state_1; + wire ifcs_1_1_state_1$D_IN, ifcs_1_1_state_1$EN; + + // register ifcs_1_noRoute_inner_currentReq + reg [96 : 0] ifcs_1_noRoute_inner_currentReq; + wire [96 : 0] ifcs_1_noRoute_inner_currentReq$D_IN; + wire ifcs_1_noRoute_inner_currentReq$EN; + + // register ifcs_1_noRoute_inner_pendingReq + reg ifcs_1_noRoute_inner_pendingReq; + wire ifcs_1_noRoute_inner_pendingReq$D_IN, + ifcs_1_noRoute_inner_pendingReq$EN; + + // register ifcs_1_state + reg [1 : 0] ifcs_1_state; + reg [1 : 0] ifcs_1_state$D_IN; + wire ifcs_1_state$EN; + + // register ifcs_1_state_1 + reg ifcs_1_state_1; + wire ifcs_1_state_1$D_IN, ifcs_1_state_1$EN; + + // register ifcs_2_1_state + reg ifcs_2_1_state; + wire ifcs_2_1_state$D_IN, ifcs_2_1_state$EN; + + // register ifcs_2_state + reg ifcs_2_state; + wire ifcs_2_state$D_IN, ifcs_2_state$EN; + + // register merged_0_flitLeft + reg [7 : 0] merged_0_flitLeft; + wire [7 : 0] merged_0_flitLeft$D_IN; + wire merged_0_flitLeft$EN; + + // register merged_1_flitLeft + reg [7 : 0] merged_1_flitLeft; + wire [7 : 0] merged_1_flitLeft$D_IN; + wire merged_1_flitLeft$EN; + + // register split_0_flitLeft + reg [7 : 0] split_0_flitLeft; + wire [7 : 0] split_0_flitLeft$D_IN; + wire split_0_flitLeft$EN; + + // register split_1_flitLeft + reg [7 : 0] split_1_flitLeft; + wire [7 : 0] split_1_flitLeft$D_IN; + wire split_1_flitLeft$EN; + + // register split_2_flitLeft + reg [7 : 0] split_2_flitLeft; + wire [7 : 0] split_2_flitLeft$D_IN; + wire split_2_flitLeft$EN; + + // register state + reg state; + wire state$D_IN, state$EN; + + // register state_1 + reg state_1; + wire state_1$D_IN, state_1$EN; + + // register state_1_1 + reg state_1_1; + wire state_1_1$D_IN, state_1_1$EN; + + // register state_1_1_1 + reg state_1_1_1; + wire state_1_1_1$D_IN, state_1_1_1$EN; + // ports of submodule cpu wire [233 : 0] cpu$trace_data_out_get; wire [63 : 0] cpu$dmem_master_araddr, @@ -789,6 +1134,10 @@ module mkCore(CLK, cpu$imem_master_arlen, cpu$imem_master_awlen, cpu$imem_master_wstrb; + wire [4 : 0] cpu$imem_master_arid, + cpu$imem_master_awid, + cpu$imem_master_bid, + cpu$imem_master_rid; wire [3 : 0] cpu$dmem_master_arcache, cpu$dmem_master_arid, cpu$dmem_master_arqos, @@ -801,15 +1150,11 @@ module mkCore(CLK, cpu$dmem_master_rid, cpu$hart0_put_other_req_put, cpu$imem_master_arcache, - cpu$imem_master_arid, cpu$imem_master_arqos, cpu$imem_master_arregion, cpu$imem_master_awcache, - cpu$imem_master_awid, cpu$imem_master_awqos, cpu$imem_master_awregion, - cpu$imem_master_bid, - cpu$imem_master_rid, cpu$set_verbosity_verbosity; wire [2 : 0] cpu$dmem_master_arprot, cpu$dmem_master_arsize, @@ -1120,206 +1465,249 @@ module mkCore(CLK, f_trace_data_merged$ENQ, f_trace_data_merged$FULL_N; - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_rdata, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_araddr, - fabric_2x3$v_to_slaves_2_awaddr, - fabric_2x3$v_to_slaves_2_rdata, - fabric_2x3$v_to_slaves_2_wdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb, - fabric_2x3$v_to_slaves_2_arlen, - fabric_2x3$v_to_slaves_2_awlen, - fabric_2x3$v_to_slaves_2_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_bid, - fabric_2x3$v_from_masters_1_rid, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_2_arcache, - fabric_2x3$v_to_slaves_2_arid, - fabric_2x3$v_to_slaves_2_arqos, - fabric_2x3$v_to_slaves_2_arregion, - fabric_2x3$v_to_slaves_2_awcache, - fabric_2x3$v_to_slaves_2_awid, - fabric_2x3$v_to_slaves_2_awqos, - fabric_2x3$v_to_slaves_2_awregion, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize, - fabric_2x3$v_to_slaves_2_arprot, - fabric_2x3$v_to_slaves_2_arsize, - fabric_2x3$v_to_slaves_2_awprot, - fabric_2x3$v_to_slaves_2_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_from_masters_1_bresp, - fabric_2x3$v_from_masters_1_rresp, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_arburst, - fabric_2x3$v_to_slaves_2_awburst, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arready, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awready, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_bvalid, - fabric_2x3$v_from_masters_1_rlast, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_rvalid, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wready, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arlock, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_arvalid, - fabric_2x3$v_to_slaves_2_awlock, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_awvalid, - fabric_2x3$v_to_slaves_2_bready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rready, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wlast, - fabric_2x3$v_to_slaves_2_wready, - fabric_2x3$v_to_slaves_2_wvalid; + // ports of submodule ifcs_0_1_innerReq + wire [97 : 0] ifcs_0_1_innerReq$D_IN, ifcs_0_1_innerReq$D_OUT; + wire ifcs_0_1_innerReq$CLR, + ifcs_0_1_innerReq$DEQ, + ifcs_0_1_innerReq$EMPTY_N, + ifcs_0_1_innerReq$ENQ, + ifcs_0_1_innerReq$FULL_N; + + // ports of submodule ifcs_0_1_innerRoute + wire [2 : 0] ifcs_0_1_innerRoute$D_IN, ifcs_0_1_innerRoute$D_OUT; + wire ifcs_0_1_innerRoute$CLR, + ifcs_0_1_innerRoute$DEQ, + ifcs_0_1_innerRoute$EMPTY_N, + ifcs_0_1_innerRoute$ENQ, + ifcs_0_1_innerRoute$FULL_N; + + // ports of submodule ifcs_0_1_noRouteRsp + wire [70 : 0] ifcs_0_1_noRouteRsp$D_IN, ifcs_0_1_noRouteRsp$D_OUT; + wire ifcs_0_1_noRouteRsp$CLR, + ifcs_0_1_noRouteRsp$DEQ, + ifcs_0_1_noRouteRsp$EMPTY_N, + ifcs_0_1_noRouteRsp$ENQ, + ifcs_0_1_noRouteRsp$FULL_N; + + // ports of submodule ifcs_0_1_routeBack + wire [1 : 0] ifcs_0_1_routeBack$D_IN, ifcs_0_1_routeBack$D_OUT; + wire ifcs_0_1_routeBack$CLR, + ifcs_0_1_routeBack$DEQ, + ifcs_0_1_routeBack$EMPTY_N, + ifcs_0_1_routeBack$ENQ, + ifcs_0_1_routeBack$FULL_N; + + // ports of submodule ifcs_0_1_rspBack + wire [70 : 0] ifcs_0_1_rspBack$D_IN, ifcs_0_1_rspBack$D_OUT; + wire ifcs_0_1_rspBack$CLR, + ifcs_0_1_rspBack$DEQ, + ifcs_0_1_rspBack$EMPTY_N, + ifcs_0_1_rspBack$ENQ, + ifcs_0_1_rspBack$FULL_N; + + // ports of submodule ifcs_0_innerReq + wire [171 : 0] ifcs_0_innerReq$D_IN, ifcs_0_innerReq$D_OUT; + wire ifcs_0_innerReq$CLR, + ifcs_0_innerReq$DEQ, + ifcs_0_innerReq$EMPTY_N, + ifcs_0_innerReq$ENQ, + ifcs_0_innerReq$FULL_N; + + // ports of submodule ifcs_0_innerRoute + wire [2 : 0] ifcs_0_innerRoute$D_IN, ifcs_0_innerRoute$D_OUT; + wire ifcs_0_innerRoute$CLR, + ifcs_0_innerRoute$DEQ, + ifcs_0_innerRoute$EMPTY_N, + ifcs_0_innerRoute$ENQ, + ifcs_0_innerRoute$FULL_N; + + // ports of submodule ifcs_0_noRouteRsp + wire [5 : 0] ifcs_0_noRouteRsp$D_IN, ifcs_0_noRouteRsp$D_OUT; + wire ifcs_0_noRouteRsp$CLR, + ifcs_0_noRouteRsp$DEQ, + ifcs_0_noRouteRsp$EMPTY_N, + ifcs_0_noRouteRsp$ENQ, + ifcs_0_noRouteRsp$FULL_N; + + // ports of submodule ifcs_0_routeBack + wire [1 : 0] ifcs_0_routeBack$D_IN, ifcs_0_routeBack$D_OUT; + wire ifcs_0_routeBack$CLR, + ifcs_0_routeBack$DEQ, + ifcs_0_routeBack$EMPTY_N, + ifcs_0_routeBack$ENQ, + ifcs_0_routeBack$FULL_N; + + // ports of submodule ifcs_0_rspBack + wire [5 : 0] ifcs_0_rspBack$D_IN, ifcs_0_rspBack$D_OUT; + wire ifcs_0_rspBack$CLR, + ifcs_0_rspBack$DEQ, + ifcs_0_rspBack$EMPTY_N, + ifcs_0_rspBack$ENQ, + ifcs_0_rspBack$FULL_N; + + // ports of submodule ifcs_1_1_innerReq + wire [97 : 0] ifcs_1_1_innerReq$D_IN, ifcs_1_1_innerReq$D_OUT; + wire ifcs_1_1_innerReq$CLR, + ifcs_1_1_innerReq$DEQ, + ifcs_1_1_innerReq$EMPTY_N, + ifcs_1_1_innerReq$ENQ, + ifcs_1_1_innerReq$FULL_N; + + // ports of submodule ifcs_1_1_innerRoute + wire [2 : 0] ifcs_1_1_innerRoute$D_IN, ifcs_1_1_innerRoute$D_OUT; + wire ifcs_1_1_innerRoute$CLR, + ifcs_1_1_innerRoute$DEQ, + ifcs_1_1_innerRoute$EMPTY_N, + ifcs_1_1_innerRoute$ENQ, + ifcs_1_1_innerRoute$FULL_N; + + // ports of submodule ifcs_1_1_noRouteRsp + wire [70 : 0] ifcs_1_1_noRouteRsp$D_IN, ifcs_1_1_noRouteRsp$D_OUT; + wire ifcs_1_1_noRouteRsp$CLR, + ifcs_1_1_noRouteRsp$DEQ, + ifcs_1_1_noRouteRsp$EMPTY_N, + ifcs_1_1_noRouteRsp$ENQ, + ifcs_1_1_noRouteRsp$FULL_N; + + // ports of submodule ifcs_1_1_routeBack + wire [1 : 0] ifcs_1_1_routeBack$D_IN, ifcs_1_1_routeBack$D_OUT; + wire ifcs_1_1_routeBack$CLR, + ifcs_1_1_routeBack$DEQ, + ifcs_1_1_routeBack$EMPTY_N, + ifcs_1_1_routeBack$ENQ, + ifcs_1_1_routeBack$FULL_N; + + // ports of submodule ifcs_1_1_rspBack + wire [70 : 0] ifcs_1_1_rspBack$D_IN, ifcs_1_1_rspBack$D_OUT; + wire ifcs_1_1_rspBack$CLR, + ifcs_1_1_rspBack$DEQ, + ifcs_1_1_rspBack$EMPTY_N, + ifcs_1_1_rspBack$ENQ, + ifcs_1_1_rspBack$FULL_N; + + // ports of submodule ifcs_1_innerReq + wire [171 : 0] ifcs_1_innerReq$D_IN, ifcs_1_innerReq$D_OUT; + wire ifcs_1_innerReq$CLR, + ifcs_1_innerReq$DEQ, + ifcs_1_innerReq$EMPTY_N, + ifcs_1_innerReq$ENQ, + ifcs_1_innerReq$FULL_N; + + // ports of submodule ifcs_1_innerRoute + wire [2 : 0] ifcs_1_innerRoute$D_IN, ifcs_1_innerRoute$D_OUT; + wire ifcs_1_innerRoute$CLR, + ifcs_1_innerRoute$DEQ, + ifcs_1_innerRoute$EMPTY_N, + ifcs_1_innerRoute$ENQ, + ifcs_1_innerRoute$FULL_N; + + // ports of submodule ifcs_1_noRouteRsp + wire [5 : 0] ifcs_1_noRouteRsp$D_IN, ifcs_1_noRouteRsp$D_OUT; + wire ifcs_1_noRouteRsp$CLR, + ifcs_1_noRouteRsp$DEQ, + ifcs_1_noRouteRsp$EMPTY_N, + ifcs_1_noRouteRsp$ENQ, + ifcs_1_noRouteRsp$FULL_N; + + // ports of submodule ifcs_1_routeBack + wire [1 : 0] ifcs_1_routeBack$D_IN, ifcs_1_routeBack$D_OUT; + wire ifcs_1_routeBack$CLR, + ifcs_1_routeBack$DEQ, + ifcs_1_routeBack$EMPTY_N, + ifcs_1_routeBack$ENQ, + ifcs_1_routeBack$FULL_N; + + // ports of submodule ifcs_1_rspBack + wire [5 : 0] ifcs_1_rspBack$D_IN, ifcs_1_rspBack$D_OUT; + wire ifcs_1_rspBack$CLR, + ifcs_1_rspBack$DEQ, + ifcs_1_rspBack$EMPTY_N, + ifcs_1_rspBack$ENQ, + ifcs_1_rspBack$FULL_N; + + // ports of submodule ifcs_2_1_routeBack + wire [1 : 0] ifcs_2_1_routeBack$D_IN, ifcs_2_1_routeBack$D_OUT; + wire ifcs_2_1_routeBack$CLR, + ifcs_2_1_routeBack$DEQ, + ifcs_2_1_routeBack$EMPTY_N, + ifcs_2_1_routeBack$ENQ, + ifcs_2_1_routeBack$FULL_N; + + // ports of submodule ifcs_2_1_rspBack + wire [70 : 0] ifcs_2_1_rspBack$D_IN, ifcs_2_1_rspBack$D_OUT; + wire ifcs_2_1_rspBack$CLR, + ifcs_2_1_rspBack$DEQ, + ifcs_2_1_rspBack$EMPTY_N, + ifcs_2_1_rspBack$ENQ, + ifcs_2_1_rspBack$FULL_N; + + // ports of submodule ifcs_2_routeBack + wire [1 : 0] ifcs_2_routeBack$D_IN, ifcs_2_routeBack$D_OUT; + wire ifcs_2_routeBack$CLR, + ifcs_2_routeBack$DEQ, + ifcs_2_routeBack$EMPTY_N, + ifcs_2_routeBack$ENQ, + ifcs_2_routeBack$FULL_N; + + // ports of submodule ifcs_2_rspBack + wire [5 : 0] ifcs_2_rspBack$D_IN, ifcs_2_rspBack$D_OUT; + wire ifcs_2_rspBack$CLR, + ifcs_2_rspBack$DEQ, + ifcs_2_rspBack$EMPTY_N, + ifcs_2_rspBack$ENQ, + ifcs_2_rspBack$FULL_N; + + // ports of submodule msNoSynth_0_b_buffer_ff + wire [5 : 0] msNoSynth_0_b_buffer_ff$D_IN, msNoSynth_0_b_buffer_ff$D_OUT; + wire msNoSynth_0_b_buffer_ff$CLR, + msNoSynth_0_b_buffer_ff$DEQ, + msNoSynth_0_b_buffer_ff$EMPTY_N, + msNoSynth_0_b_buffer_ff$ENQ, + msNoSynth_0_b_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_b_buffer_firstValid + wire msNoSynth_0_b_buffer_firstValid$D_IN, + msNoSynth_0_b_buffer_firstValid$EN, + msNoSynth_0_b_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_r_buffer_ff + wire [70 : 0] msNoSynth_0_r_buffer_ff$D_IN, msNoSynth_0_r_buffer_ff$D_OUT; + wire msNoSynth_0_r_buffer_ff$CLR, + msNoSynth_0_r_buffer_ff$DEQ, + msNoSynth_0_r_buffer_ff$EMPTY_N, + msNoSynth_0_r_buffer_ff$ENQ, + msNoSynth_0_r_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_r_buffer_firstValid + wire msNoSynth_0_r_buffer_firstValid$D_IN, + msNoSynth_0_r_buffer_firstValid$EN, + msNoSynth_0_r_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_b_buffer_ff + wire [5 : 0] msNoSynth_1_b_buffer_ff$D_IN, msNoSynth_1_b_buffer_ff$D_OUT; + wire msNoSynth_1_b_buffer_ff$CLR, + msNoSynth_1_b_buffer_ff$DEQ, + msNoSynth_1_b_buffer_ff$EMPTY_N, + msNoSynth_1_b_buffer_ff$ENQ, + msNoSynth_1_b_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_b_buffer_firstValid + wire msNoSynth_1_b_buffer_firstValid$D_IN, + msNoSynth_1_b_buffer_firstValid$EN, + msNoSynth_1_b_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_r_buffer_ff + wire [70 : 0] msNoSynth_1_r_buffer_ff$D_IN, msNoSynth_1_r_buffer_ff$D_OUT; + wire msNoSynth_1_r_buffer_ff$CLR, + msNoSynth_1_r_buffer_ff$DEQ, + msNoSynth_1_r_buffer_ff$EMPTY_N, + msNoSynth_1_r_buffer_ff$ENQ, + msNoSynth_1_r_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_r_buffer_firstValid + wire msNoSynth_1_r_buffer_firstValid$D_IN, + msNoSynth_1_r_buffer_firstValid$EN, + msNoSynth_1_r_buffer_firstValid$Q_OUT; // ports of submodule near_mem_io wire [63 : 0] near_mem_io$axi4_slave_araddr, @@ -1331,16 +1719,16 @@ module mkCore(CLK, wire [7 : 0] near_mem_io$axi4_slave_arlen, near_mem_io$axi4_slave_awlen, near_mem_io$axi4_slave_wstrb; + wire [4 : 0] near_mem_io$axi4_slave_arid, + near_mem_io$axi4_slave_awid, + near_mem_io$axi4_slave_bid, + near_mem_io$axi4_slave_rid; wire [3 : 0] near_mem_io$axi4_slave_arcache, - near_mem_io$axi4_slave_arid, near_mem_io$axi4_slave_arqos, near_mem_io$axi4_slave_arregion, near_mem_io$axi4_slave_awcache, - near_mem_io$axi4_slave_awid, near_mem_io$axi4_slave_awqos, - near_mem_io$axi4_slave_awregion, - near_mem_io$axi4_slave_bid, - near_mem_io$axi4_slave_rid; + near_mem_io$axi4_slave_awregion; wire [2 : 0] near_mem_io$axi4_slave_arprot, near_mem_io$axi4_slave_arsize, near_mem_io$axi4_slave_awprot, @@ -1385,16 +1773,16 @@ module mkCore(CLK, wire [7 : 0] plic$axi4_slave_arlen, plic$axi4_slave_awlen, plic$axi4_slave_wstrb; + wire [4 : 0] plic$axi4_slave_arid, + plic$axi4_slave_awid, + plic$axi4_slave_bid, + plic$axi4_slave_rid; wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, plic$axi4_slave_arqos, plic$axi4_slave_arregion, plic$axi4_slave_awcache, - plic$axi4_slave_awid, plic$axi4_slave_awqos, plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, plic$set_verbosity_verbosity; wire [2 : 0] plic$axi4_slave_arprot, plic$axi4_slave_arsize, @@ -1444,14 +1832,168 @@ module mkCore(CLK, plic$v_targets_0_m_eip, plic$v_targets_1_m_eip; + // ports of submodule shim_arff + wire [97 : 0] shim_arff$D_IN, shim_arff$D_OUT; + wire shim_arff$CLR, + shim_arff$DEQ, + shim_arff$EMPTY_N, + shim_arff$ENQ, + shim_arff$FULL_N; + + // ports of submodule shim_awff + wire [97 : 0] shim_awff$D_IN, shim_awff$D_OUT; + wire shim_awff$CLR, + shim_awff$DEQ, + shim_awff$EMPTY_N, + shim_awff$ENQ, + shim_awff$FULL_N; + + // ports of submodule shim_bff + wire [6 : 0] shim_bff$D_IN, shim_bff$D_OUT; + wire shim_bff$CLR, + shim_bff$DEQ, + shim_bff$EMPTY_N, + shim_bff$ENQ, + shim_bff$FULL_N; + + // ports of submodule shim_rff + wire [71 : 0] shim_rff$D_IN, shim_rff$D_OUT; + wire shim_rff$CLR, + shim_rff$DEQ, + shim_rff$EMPTY_N, + shim_rff$ENQ, + shim_rff$FULL_N; + + // ports of submodule shim_wff + wire [72 : 0] shim_wff$D_IN, shim_wff$D_OUT; + wire shim_wff$CLR, + shim_wff$DEQ, + shim_wff$EMPTY_N, + shim_wff$ENQ, + shim_wff$FULL_N; + // ports of submodule soc_map + wire [127 : 0] soc_map$m_near_mem_io_addr_range, soc_map$m_plic_addr_range; wire [63 : 0] soc_map$m_is_IO_addr_addr, soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; + soc_map$m_is_near_mem_IO_addr_addr; + + // ports of submodule ssNoSynth_0_ar_buffer_ff + wire [97 : 0] ssNoSynth_0_ar_buffer_ff$D_IN, ssNoSynth_0_ar_buffer_ff$D_OUT; + wire ssNoSynth_0_ar_buffer_ff$CLR, + ssNoSynth_0_ar_buffer_ff$DEQ, + ssNoSynth_0_ar_buffer_ff$EMPTY_N, + ssNoSynth_0_ar_buffer_ff$ENQ, + ssNoSynth_0_ar_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_0_ar_buffer_firstValid + wire ssNoSynth_0_ar_buffer_firstValid$D_IN, + ssNoSynth_0_ar_buffer_firstValid$EN, + ssNoSynth_0_ar_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_0_aw_buffer_ff + wire [97 : 0] ssNoSynth_0_aw_buffer_ff$D_IN, ssNoSynth_0_aw_buffer_ff$D_OUT; + wire ssNoSynth_0_aw_buffer_ff$CLR, + ssNoSynth_0_aw_buffer_ff$DEQ, + ssNoSynth_0_aw_buffer_ff$EMPTY_N, + ssNoSynth_0_aw_buffer_ff$ENQ, + ssNoSynth_0_aw_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_0_aw_buffer_firstValid + wire ssNoSynth_0_aw_buffer_firstValid$D_IN, + ssNoSynth_0_aw_buffer_firstValid$EN, + ssNoSynth_0_aw_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_0_w_buffer_ff + wire [72 : 0] ssNoSynth_0_w_buffer_ff$D_IN, ssNoSynth_0_w_buffer_ff$D_OUT; + wire ssNoSynth_0_w_buffer_ff$CLR, + ssNoSynth_0_w_buffer_ff$DEQ, + ssNoSynth_0_w_buffer_ff$EMPTY_N, + ssNoSynth_0_w_buffer_ff$ENQ, + ssNoSynth_0_w_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_0_w_buffer_firstValid + wire ssNoSynth_0_w_buffer_firstValid$D_IN, + ssNoSynth_0_w_buffer_firstValid$EN, + ssNoSynth_0_w_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_ar_buffer_ff + wire [97 : 0] ssNoSynth_1_ar_buffer_ff$D_IN, ssNoSynth_1_ar_buffer_ff$D_OUT; + wire ssNoSynth_1_ar_buffer_ff$CLR, + ssNoSynth_1_ar_buffer_ff$DEQ, + ssNoSynth_1_ar_buffer_ff$EMPTY_N, + ssNoSynth_1_ar_buffer_ff$ENQ, + ssNoSynth_1_ar_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_ar_buffer_firstValid + wire ssNoSynth_1_ar_buffer_firstValid$D_IN, + ssNoSynth_1_ar_buffer_firstValid$EN, + ssNoSynth_1_ar_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_aw_buffer_ff + wire [97 : 0] ssNoSynth_1_aw_buffer_ff$D_IN, ssNoSynth_1_aw_buffer_ff$D_OUT; + wire ssNoSynth_1_aw_buffer_ff$CLR, + ssNoSynth_1_aw_buffer_ff$DEQ, + ssNoSynth_1_aw_buffer_ff$EMPTY_N, + ssNoSynth_1_aw_buffer_ff$ENQ, + ssNoSynth_1_aw_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_aw_buffer_firstValid + wire ssNoSynth_1_aw_buffer_firstValid$D_IN, + ssNoSynth_1_aw_buffer_firstValid$EN, + ssNoSynth_1_aw_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_w_buffer_ff + wire [72 : 0] ssNoSynth_1_w_buffer_ff$D_IN, ssNoSynth_1_w_buffer_ff$D_OUT; + wire ssNoSynth_1_w_buffer_ff$CLR, + ssNoSynth_1_w_buffer_ff$DEQ, + ssNoSynth_1_w_buffer_ff$EMPTY_N, + ssNoSynth_1_w_buffer_ff$ENQ, + ssNoSynth_1_w_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_w_buffer_firstValid + wire ssNoSynth_1_w_buffer_firstValid$D_IN, + ssNoSynth_1_w_buffer_firstValid$EN, + ssNoSynth_1_w_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_ar_buffer_ff + wire [97 : 0] ssNoSynth_2_ar_buffer_ff$D_IN, ssNoSynth_2_ar_buffer_ff$D_OUT; + wire ssNoSynth_2_ar_buffer_ff$CLR, + ssNoSynth_2_ar_buffer_ff$DEQ, + ssNoSynth_2_ar_buffer_ff$EMPTY_N, + ssNoSynth_2_ar_buffer_ff$ENQ, + ssNoSynth_2_ar_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_ar_buffer_firstValid + wire ssNoSynth_2_ar_buffer_firstValid$D_IN, + ssNoSynth_2_ar_buffer_firstValid$EN, + ssNoSynth_2_ar_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_aw_buffer_ff + wire [97 : 0] ssNoSynth_2_aw_buffer_ff$D_IN, ssNoSynth_2_aw_buffer_ff$D_OUT; + wire ssNoSynth_2_aw_buffer_ff$CLR, + ssNoSynth_2_aw_buffer_ff$DEQ, + ssNoSynth_2_aw_buffer_ff$EMPTY_N, + ssNoSynth_2_aw_buffer_ff$ENQ, + ssNoSynth_2_aw_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_aw_buffer_firstValid + wire ssNoSynth_2_aw_buffer_firstValid$D_IN, + ssNoSynth_2_aw_buffer_firstValid$EN, + ssNoSynth_2_aw_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_w_buffer_ff + wire [72 : 0] ssNoSynth_2_w_buffer_ff$D_IN, ssNoSynth_2_w_buffer_ff$D_OUT; + wire ssNoSynth_2_w_buffer_ff$CLR, + ssNoSynth_2_w_buffer_ff$DEQ, + ssNoSynth_2_w_buffer_ff$EMPTY_N, + ssNoSynth_2_w_buffer_ff$ENQ, + ssNoSynth_2_w_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_w_buffer_firstValid + wire ssNoSynth_2_w_buffer_firstValid$D_IN, + ssNoSynth_2_w_buffer_firstValid$EN, + ssNoSynth_2_w_buffer_firstValid$Q_OUT; // ports of submodule tv_encode wire [607 : 0] tv_encode$tv_vb_out_get; @@ -1473,43 +2015,232 @@ module mkCore(CLK, CAN_FIRE_RL_ClientServerResponse_2, CAN_FIRE_RL_ClientServerResponse_3, CAN_FIRE_RL_ClientServerResponse_4, + CAN_FIRE_RL_arbitrate, + CAN_FIRE_RL_arbitrate_1, + CAN_FIRE_RL_arbitrate_2, + CAN_FIRE_RL_arbitrate_3, + CAN_FIRE_RL_burst, + CAN_FIRE_RL_burst_1, + CAN_FIRE_RL_burst_2, + CAN_FIRE_RL_burst_3, + CAN_FIRE_RL_burst_4, + CAN_FIRE_RL_burst_5, + CAN_FIRE_RL_burst_6, + CAN_FIRE_RL_burst_7, + CAN_FIRE_RL_burst_8, + CAN_FIRE_RL_burst_9, + CAN_FIRE_RL_checkSinkReady, + CAN_FIRE_RL_checkSinkReady_1, + CAN_FIRE_RL_checkSinkReady_2, + CAN_FIRE_RL_checkSinkReady_3, + CAN_FIRE_RL_checkSinkReady_4, + CAN_FIRE_RL_checkSinkReady_5, + CAN_FIRE_RL_checkSinkReady_6, + CAN_FIRE_RL_checkSinkReady_7, + CAN_FIRE_RL_checkSinkReady_8, + CAN_FIRE_RL_checkSinkReady_9, + CAN_FIRE_RL_connect_arflit, + CAN_FIRE_RL_connect_arready, + CAN_FIRE_RL_connect_awflit, + CAN_FIRE_RL_connect_awready, + CAN_FIRE_RL_connect_bflit, + CAN_FIRE_RL_connect_bready, + CAN_FIRE_RL_connect_rflit, + CAN_FIRE_RL_connect_rready, + CAN_FIRE_RL_connect_wflit, + CAN_FIRE_RL_connect_wready, + CAN_FIRE_RL_craftReq, + CAN_FIRE_RL_craftReq_1, + CAN_FIRE_RL_craftReq_2, + CAN_FIRE_RL_craftReq_3, + CAN_FIRE_RL_craftReq_4, + CAN_FIRE_RL_craftReq_5, + CAN_FIRE_RL_craftReq_6, + CAN_FIRE_RL_craftReq_7, + CAN_FIRE_RL_craftReq_8, + CAN_FIRE_RL_craftReq_9, + CAN_FIRE_RL_ifcs_0_1_drainFlits, + CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_0_1_firstFlit, + CAN_FIRE_RL_ifcs_0_1_firstFlit_1, + CAN_FIRE_RL_ifcs_0_1_followFlits, + CAN_FIRE_RL_ifcs_0_1_followFlits_1, + CAN_FIRE_RL_ifcs_0_1_forwardRsp, + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit, + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_0_drainFlits, + CAN_FIRE_RL_ifcs_0_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_0_firstFlit, + CAN_FIRE_RL_ifcs_0_firstFlit_1, + CAN_FIRE_RL_ifcs_0_followFlits, + CAN_FIRE_RL_ifcs_0_followFlits_1, + CAN_FIRE_RL_ifcs_0_forwardRsp, + CAN_FIRE_RL_ifcs_0_nonRoutableFlit, + CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_1_drainFlits, + CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_1_1_firstFlit, + CAN_FIRE_RL_ifcs_1_1_firstFlit_1, + CAN_FIRE_RL_ifcs_1_1_followFlits, + CAN_FIRE_RL_ifcs_1_1_followFlits_1, + CAN_FIRE_RL_ifcs_1_1_forwardRsp, + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit, + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_drainFlits, + CAN_FIRE_RL_ifcs_1_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_1_firstFlit, + CAN_FIRE_RL_ifcs_1_firstFlit_1, + CAN_FIRE_RL_ifcs_1_followFlits, + CAN_FIRE_RL_ifcs_1_followFlits_1, + CAN_FIRE_RL_ifcs_1_forwardRsp, + CAN_FIRE_RL_ifcs_1_nonRoutableFlit, + CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_2_1_firstFlit, + CAN_FIRE_RL_ifcs_2_1_followFlits, + CAN_FIRE_RL_ifcs_2_firstFlit, + CAN_FIRE_RL_ifcs_2_followFlits, CAN_FIRE_RL_merge_cpu_trace_data, CAN_FIRE_RL_merge_dm_csr_trace_data, CAN_FIRE_RL_merge_dm_gpr_trace_data, CAN_FIRE_RL_merge_dm_mem_trace_data, + CAN_FIRE_RL_merged_0_genFirst, + CAN_FIRE_RL_merged_0_genOther, + CAN_FIRE_RL_merged_1_genFirst, + CAN_FIRE_RL_merged_1_genOther, CAN_FIRE_RL_mkConnectionGetPut, CAN_FIRE_RL_mkConnectionGetPut_1, + CAN_FIRE_RL_msNoSynth_0_ar_forwardReady, + CAN_FIRE_RL_msNoSynth_0_aw_forwardReady, + CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_b_dropFlit, + CAN_FIRE_RL_msNoSynth_0_b_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_r_dropFlit, + CAN_FIRE_RL_msNoSynth_0_r_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_w_forwardReady, + CAN_FIRE_RL_msNoSynth_1_ar_forwardReady, + CAN_FIRE_RL_msNoSynth_1_aw_forwardReady, + CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_b_dropFlit, + CAN_FIRE_RL_msNoSynth_1_b_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_r_dropFlit, + CAN_FIRE_RL_msNoSynth_1_r_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_w_forwardReady, CAN_FIRE_RL_rl_cpu_hart0_reset_complete, CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, CAN_FIRE_RL_rl_relay_external_interrupts, CAN_FIRE_RL_rl_relay_sw_interrupts, CAN_FIRE_RL_rl_relay_timer_interrupts, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, + CAN_FIRE_RL_sink_selected, + CAN_FIRE_RL_sink_selected_1, + CAN_FIRE_RL_sink_selected_2, + CAN_FIRE_RL_sink_selected_3, + CAN_FIRE_RL_sink_selected_4, + CAN_FIRE_RL_sink_selected_5, + CAN_FIRE_RL_sink_selected_6, + CAN_FIRE_RL_sink_selected_7, + CAN_FIRE_RL_sink_selected_8, + CAN_FIRE_RL_sink_selected_9, + CAN_FIRE_RL_source_selected, + CAN_FIRE_RL_source_selected_1, + CAN_FIRE_RL_source_selected_2, + CAN_FIRE_RL_source_selected_3, + CAN_FIRE_RL_source_selected_4, + CAN_FIRE_RL_source_selected_5, + CAN_FIRE_RL_source_selected_6, + CAN_FIRE_RL_source_selected_7, + CAN_FIRE_RL_source_selected_8, + CAN_FIRE_RL_source_selected_9, + CAN_FIRE_RL_split_0_putFirst, + CAN_FIRE_RL_split_0_putOther, + CAN_FIRE_RL_split_1_putFirst, + CAN_FIRE_RL_split_1_putOther, + CAN_FIRE_RL_split_2_putFirst, + CAN_FIRE_RL_split_2_putOther, + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_b_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_r_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_w_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_b_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_r_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_b_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_r_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit, + CAN_FIRE___me_check_103, + CAN_FIRE___me_check_104, + CAN_FIRE___me_check_105, + CAN_FIRE___me_check_107, + CAN_FIRE___me_check_110, + CAN_FIRE___me_check_111, + CAN_FIRE___me_check_112, + CAN_FIRE___me_check_114, + CAN_FIRE___me_check_117, + CAN_FIRE___me_check_119, + CAN_FIRE___me_check_121, + CAN_FIRE___me_check_129, + CAN_FIRE___me_check_131, + CAN_FIRE___me_check_133, + CAN_FIRE___me_check_142, + CAN_FIRE___me_check_144, + CAN_FIRE___me_check_146, + CAN_FIRE___me_check_148, + CAN_FIRE___me_check_150, + CAN_FIRE___me_check_151, + CAN_FIRE___me_check_152, + CAN_FIRE___me_check_154, + CAN_FIRE___me_check_157, + CAN_FIRE___me_check_158, + CAN_FIRE___me_check_159, + CAN_FIRE___me_check_161, + CAN_FIRE___me_check_164, + CAN_FIRE___me_check_166, + CAN_FIRE___me_check_168, + CAN_FIRE___me_check_176, + CAN_FIRE___me_check_178, + CAN_FIRE___me_check_180, + CAN_FIRE___me_check_189, + CAN_FIRE___me_check_191, + CAN_FIRE___me_check_193, + CAN_FIRE___me_check_195, CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -1526,16 +2257,16 @@ module mkCore(CLK, CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, + CAN_FIRE_cpu_dmem_master_ar_arready, + CAN_FIRE_cpu_dmem_master_aw_awready, + CAN_FIRE_cpu_dmem_master_b_bflit, + CAN_FIRE_cpu_dmem_master_r_rflit, + CAN_FIRE_cpu_dmem_master_w_wready, + CAN_FIRE_cpu_imem_master_ar_arready, + CAN_FIRE_cpu_imem_master_aw_awready, + CAN_FIRE_cpu_imem_master_b_bflit, + CAN_FIRE_cpu_imem_master_r_rflit, + CAN_FIRE_cpu_imem_master_w_wready, CAN_FIRE_cpu_reset_server_request_put, CAN_FIRE_cpu_reset_server_response_get, CAN_FIRE_dm_dmi_read_addr, @@ -1556,43 +2287,232 @@ module mkCore(CLK, WILL_FIRE_RL_ClientServerResponse_2, WILL_FIRE_RL_ClientServerResponse_3, WILL_FIRE_RL_ClientServerResponse_4, + WILL_FIRE_RL_arbitrate, + WILL_FIRE_RL_arbitrate_1, + WILL_FIRE_RL_arbitrate_2, + WILL_FIRE_RL_arbitrate_3, + WILL_FIRE_RL_burst, + WILL_FIRE_RL_burst_1, + WILL_FIRE_RL_burst_2, + WILL_FIRE_RL_burst_3, + WILL_FIRE_RL_burst_4, + WILL_FIRE_RL_burst_5, + WILL_FIRE_RL_burst_6, + WILL_FIRE_RL_burst_7, + WILL_FIRE_RL_burst_8, + WILL_FIRE_RL_burst_9, + WILL_FIRE_RL_checkSinkReady, + WILL_FIRE_RL_checkSinkReady_1, + WILL_FIRE_RL_checkSinkReady_2, + WILL_FIRE_RL_checkSinkReady_3, + WILL_FIRE_RL_checkSinkReady_4, + WILL_FIRE_RL_checkSinkReady_5, + WILL_FIRE_RL_checkSinkReady_6, + WILL_FIRE_RL_checkSinkReady_7, + WILL_FIRE_RL_checkSinkReady_8, + WILL_FIRE_RL_checkSinkReady_9, + WILL_FIRE_RL_connect_arflit, + WILL_FIRE_RL_connect_arready, + WILL_FIRE_RL_connect_awflit, + WILL_FIRE_RL_connect_awready, + WILL_FIRE_RL_connect_bflit, + WILL_FIRE_RL_connect_bready, + WILL_FIRE_RL_connect_rflit, + WILL_FIRE_RL_connect_rready, + WILL_FIRE_RL_connect_wflit, + WILL_FIRE_RL_connect_wready, + WILL_FIRE_RL_craftReq, + WILL_FIRE_RL_craftReq_1, + WILL_FIRE_RL_craftReq_2, + WILL_FIRE_RL_craftReq_3, + WILL_FIRE_RL_craftReq_4, + WILL_FIRE_RL_craftReq_5, + WILL_FIRE_RL_craftReq_6, + WILL_FIRE_RL_craftReq_7, + WILL_FIRE_RL_craftReq_8, + WILL_FIRE_RL_craftReq_9, + WILL_FIRE_RL_ifcs_0_1_drainFlits, + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_0_1_firstFlit, + WILL_FIRE_RL_ifcs_0_1_firstFlit_1, + WILL_FIRE_RL_ifcs_0_1_followFlits, + WILL_FIRE_RL_ifcs_0_1_followFlits_1, + WILL_FIRE_RL_ifcs_0_1_forwardRsp, + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit, + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_0_drainFlits, + WILL_FIRE_RL_ifcs_0_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_0_firstFlit, + WILL_FIRE_RL_ifcs_0_firstFlit_1, + WILL_FIRE_RL_ifcs_0_followFlits, + WILL_FIRE_RL_ifcs_0_followFlits_1, + WILL_FIRE_RL_ifcs_0_forwardRsp, + WILL_FIRE_RL_ifcs_0_nonRoutableFlit, + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_1_drainFlits, + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_1_1_firstFlit, + WILL_FIRE_RL_ifcs_1_1_firstFlit_1, + WILL_FIRE_RL_ifcs_1_1_followFlits, + WILL_FIRE_RL_ifcs_1_1_followFlits_1, + WILL_FIRE_RL_ifcs_1_1_forwardRsp, + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit, + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_drainFlits, + WILL_FIRE_RL_ifcs_1_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_1_firstFlit, + WILL_FIRE_RL_ifcs_1_firstFlit_1, + WILL_FIRE_RL_ifcs_1_followFlits, + WILL_FIRE_RL_ifcs_1_followFlits_1, + WILL_FIRE_RL_ifcs_1_forwardRsp, + WILL_FIRE_RL_ifcs_1_nonRoutableFlit, + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_2_1_firstFlit, + WILL_FIRE_RL_ifcs_2_1_followFlits, + WILL_FIRE_RL_ifcs_2_firstFlit, + WILL_FIRE_RL_ifcs_2_followFlits, WILL_FIRE_RL_merge_cpu_trace_data, WILL_FIRE_RL_merge_dm_csr_trace_data, WILL_FIRE_RL_merge_dm_gpr_trace_data, WILL_FIRE_RL_merge_dm_mem_trace_data, + WILL_FIRE_RL_merged_0_genFirst, + WILL_FIRE_RL_merged_0_genOther, + WILL_FIRE_RL_merged_1_genFirst, + WILL_FIRE_RL_merged_1_genOther, WILL_FIRE_RL_mkConnectionGetPut, WILL_FIRE_RL_mkConnectionGetPut_1, + WILL_FIRE_RL_msNoSynth_0_ar_forwardReady, + WILL_FIRE_RL_msNoSynth_0_aw_forwardReady, + WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_b_dropFlit, + WILL_FIRE_RL_msNoSynth_0_b_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_r_dropFlit, + WILL_FIRE_RL_msNoSynth_0_r_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_w_forwardReady, + WILL_FIRE_RL_msNoSynth_1_ar_forwardReady, + WILL_FIRE_RL_msNoSynth_1_aw_forwardReady, + WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_b_dropFlit, + WILL_FIRE_RL_msNoSynth_1_b_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_r_dropFlit, + WILL_FIRE_RL_msNoSynth_1_r_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_w_forwardReady, WILL_FIRE_RL_rl_cpu_hart0_reset_complete, WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, WILL_FIRE_RL_rl_relay_external_interrupts, WILL_FIRE_RL_rl_relay_sw_interrupts, WILL_FIRE_RL_rl_relay_timer_interrupts, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, + WILL_FIRE_RL_sink_selected, + WILL_FIRE_RL_sink_selected_1, + WILL_FIRE_RL_sink_selected_2, + WILL_FIRE_RL_sink_selected_3, + WILL_FIRE_RL_sink_selected_4, + WILL_FIRE_RL_sink_selected_5, + WILL_FIRE_RL_sink_selected_6, + WILL_FIRE_RL_sink_selected_7, + WILL_FIRE_RL_sink_selected_8, + WILL_FIRE_RL_sink_selected_9, + WILL_FIRE_RL_source_selected, + WILL_FIRE_RL_source_selected_1, + WILL_FIRE_RL_source_selected_2, + WILL_FIRE_RL_source_selected_3, + WILL_FIRE_RL_source_selected_4, + WILL_FIRE_RL_source_selected_5, + WILL_FIRE_RL_source_selected_6, + WILL_FIRE_RL_source_selected_7, + WILL_FIRE_RL_source_selected_8, + WILL_FIRE_RL_source_selected_9, + WILL_FIRE_RL_split_0_putFirst, + WILL_FIRE_RL_split_0_putOther, + WILL_FIRE_RL_split_1_putFirst, + WILL_FIRE_RL_split_1_putOther, + WILL_FIRE_RL_split_2_putFirst, + WILL_FIRE_RL_split_2_putOther, + WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_b_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_r_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_w_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_b_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_r_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_w_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_b_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_r_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_w_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit, + WILL_FIRE___me_check_103, + WILL_FIRE___me_check_104, + WILL_FIRE___me_check_105, + WILL_FIRE___me_check_107, + WILL_FIRE___me_check_110, + WILL_FIRE___me_check_111, + WILL_FIRE___me_check_112, + WILL_FIRE___me_check_114, + WILL_FIRE___me_check_117, + WILL_FIRE___me_check_119, + WILL_FIRE___me_check_121, + WILL_FIRE___me_check_129, + WILL_FIRE___me_check_131, + WILL_FIRE___me_check_133, + WILL_FIRE___me_check_142, + WILL_FIRE___me_check_144, + WILL_FIRE___me_check_146, + WILL_FIRE___me_check_148, + WILL_FIRE___me_check_150, + WILL_FIRE___me_check_151, + WILL_FIRE___me_check_152, + WILL_FIRE___me_check_154, + WILL_FIRE___me_check_157, + WILL_FIRE___me_check_158, + WILL_FIRE___me_check_159, + WILL_FIRE___me_check_161, + WILL_FIRE___me_check_164, + WILL_FIRE___me_check_166, + WILL_FIRE___me_check_168, + WILL_FIRE___me_check_176, + WILL_FIRE___me_check_178, + WILL_FIRE___me_check_180, + WILL_FIRE___me_check_189, + WILL_FIRE___me_check_191, + WILL_FIRE___me_check_193, + WILL_FIRE___me_check_195, WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -1609,16 +2529,16 @@ module mkCore(CLK, WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, + WILL_FIRE_cpu_dmem_master_ar_arready, + WILL_FIRE_cpu_dmem_master_aw_awready, + WILL_FIRE_cpu_dmem_master_b_bflit, + WILL_FIRE_cpu_dmem_master_r_rflit, + WILL_FIRE_cpu_dmem_master_w_wready, + WILL_FIRE_cpu_imem_master_ar_arready, + WILL_FIRE_cpu_imem_master_aw_awready, + WILL_FIRE_cpu_imem_master_b_bflit, + WILL_FIRE_cpu_imem_master_r_rflit, + WILL_FIRE_cpu_imem_master_w_wready, WILL_FIRE_cpu_reset_server_request_put, WILL_FIRE_cpu_reset_server_response_get, WILL_FIRE_dm_dmi_read_addr, @@ -1630,18 +2550,292 @@ module mkCore(CLK, WILL_FIRE_set_verbosity, WILL_FIRE_tv_verifier_info_get_get; + // inputs to muxes for submodule ports + reg [70 : 0] MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1, + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1; + reg [5 : 0] MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1, + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1; + wire [7 : 0] MUX_merged_0_flitLeft$write_1__VAL_1, + MUX_merged_1_flitLeft$write_1__VAL_1, + MUX_split_0_flitLeft$write_1__VAL_1, + MUX_split_1_flitLeft$write_1__VAL_1, + MUX_split_2_flitLeft$write_1__VAL_1; + wire MUX_activeSource_0$write_1__SEL_1, + MUX_activeSource_0$write_1__VAL_1, + MUX_activeSource_1$write_1__VAL_1, + MUX_activeSource_1_1_0$write_1__SEL_1, + MUX_activeSource_1_1_0$write_1__SEL_2, + MUX_activeSource_1_1_0$write_1__SEL_3, + MUX_activeSource_1_1_0$write_1__VAL_1, + MUX_activeSource_1_1_1_1$write_1__VAL_1, + MUX_activeSource_1_1_2$write_1__VAL_1, + MUX_flitToSink_0$wset_1__SEL_1, + MUX_flitToSink_0$wset_1__SEL_3, + MUX_flitToSink_1$wset_1__SEL_1, + MUX_flitToSink_1$wset_1__SEL_3, + MUX_flitToSink_1_0$wset_1__SEL_1, + MUX_flitToSink_1_0$wset_1__SEL_2, + MUX_flitToSink_1_0$wset_1__SEL_3, + MUX_flitToSink_1_0$wset_1__SEL_4, + MUX_flitToSink_1_0$wset_1__SEL_5, + MUX_flitToSink_1_0$wset_1__SEL_6, + MUX_flitToSink_1_0_1$wset_1__SEL_1, + MUX_flitToSink_1_0_1$wset_1__SEL_3, + MUX_flitToSink_1_1$wset_1__SEL_1, + MUX_flitToSink_1_1$wset_1__SEL_2, + MUX_flitToSink_1_1$wset_1__SEL_3, + MUX_flitToSink_1_1$wset_1__SEL_4, + MUX_flitToSink_1_1$wset_1__SEL_5, + MUX_flitToSink_1_1$wset_1__SEL_6, + MUX_flitToSink_1_1_0$wset_1__SEL_1, + MUX_flitToSink_1_1_0$wset_1__SEL_2, + MUX_flitToSink_1_1_0$wset_1__SEL_3, + MUX_flitToSink_1_1_0$wset_1__SEL_4, + MUX_flitToSink_1_1_0$wset_1__SEL_5, + MUX_flitToSink_1_1_0$wset_1__SEL_6, + MUX_flitToSink_1_1_1$wset_1__SEL_1, + MUX_flitToSink_1_1_1$wset_1__SEL_3, + MUX_flitToSink_1_1_1_1$wset_1__SEL_1, + MUX_flitToSink_1_1_1_1$wset_1__SEL_2, + MUX_flitToSink_1_1_1_1$wset_1__SEL_3, + MUX_flitToSink_1_1_1_1$wset_1__SEL_4, + MUX_flitToSink_1_1_1_1$wset_1__SEL_5, + MUX_flitToSink_1_1_1_1$wset_1__SEL_6, + MUX_flitToSink_1_2$wset_1__SEL_1, + MUX_flitToSink_1_2$wset_1__SEL_3, + MUX_flitToSink_2$wset_1__SEL_1, + MUX_flitToSink_2$wset_1__SEL_3, + MUX_ifcs_0_1_state_1$write_1__SEL_1, + MUX_ifcs_0_state$write_1__PSEL_1, + MUX_ifcs_0_state$write_1__SEL_1, + MUX_ifcs_0_state$write_1__SEL_2, + MUX_ifcs_0_state$write_1__SEL_3, + MUX_ifcs_1_1_state_1$write_1__SEL_1, + MUX_ifcs_1_state$write_1__PSEL_1, + MUX_ifcs_1_state$write_1__SEL_1, + MUX_ifcs_1_state$write_1__SEL_2, + MUX_ifcs_1_state$write_1__SEL_3, + MUX_ifcs_2_1_state$write_1__SEL_1, + MUX_split_0_flitLeft$write_1__SEL_1, + MUX_split_0_flitLeft$write_1__SEL_2, + MUX_split_1_flitLeft$write_1__SEL_1, + MUX_split_1_flitLeft$write_1__SEL_2, + MUX_split_2_flitLeft$write_1__SEL_1, + MUX_split_2_flitLeft$write_1__SEL_2, + MUX_state$write_1__SEL_1, + MUX_state$write_1__SEL_2, + MUX_state_1_1_1$write_1__SEL_1, + MUX_state_1_1_1$write_1__SEL_2, + MUX_state_1_1_1$write_1__SEL_3; + // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5074; - reg [31 : 0] v__h5275; - reg [31 : 0] v__h5643; - reg [31 : 0] v__h5068; - reg [31 : 0] v__h5269; - reg [31 : 0] v__h5637; + reg [63 : 0] v__h33674; + reg [63 : 0] v__h33063; + reg [63 : 0] v__h37683; + reg [63 : 0] v__h37072; + reg [63 : 0] v__h67508; + reg [63 : 0] v__h66897; + reg [63 : 0] v__h70401; + reg [63 : 0] v__h69790; + reg [63 : 0] v__h48378; + reg [63 : 0] v__h47997; + reg [63 : 0] v__h50448; + reg [63 : 0] v__h50067; + reg [63 : 0] v__h52347; + reg [63 : 0] v__h51966; + reg [63 : 0] v__h22294; + reg [63 : 0] v__h25002; + reg [63 : 0] v__h79681; + reg [63 : 0] v__h79300; + reg [63 : 0] v__h82172; + reg [63 : 0] v__h81791; + reg [63 : 0] v__h84482; + reg [63 : 0] v__h84101; + reg [63 : 0] v__h56310; + reg [31 : 0] v__h3443; + reg [31 : 0] v__h3620; + reg [31 : 0] v__h3986; + reg [63 : 0] v__h58726; + reg [31 : 0] v__h3437; + reg [31 : 0] v__h3614; + reg [31 : 0] v__h3980; // synopsys translate_on // remaining internal signals - wire fabric_2x3_RDY_reset_AND_cpu_RDY_hart0_server__ETC___d9; + wire [63 : 0] y__h20569, y__h20593; + wire [8 : 0] x_port1__read__h55959, x_port1__read__h58381; + wire [4 : 0] a_awid__h21643, + a_awid__h24357, + fatReq_arid__h55399, + fatReq_arid__h57824; + wire [1 : 0] IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d779, + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d783, + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d787, + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d876, + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d880, + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d884, + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1420, + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1424, + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1428, + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1506, + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1510, + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1514, + SEXT_SEXT_arbiter_1_1_firstHot_877_878_BIT_0_8_ETC__q18, + SEXT_SEXT_arbiter_1_firstHot_1_692_693_BIT_0_6_ETC__q13, + SEXT_SEXT_arbiter_1_firstHot_249_250_BIT_0_251_ETC__q8, + SEXT_SEXT_arbiter_firstHot_054_055_BIT_0_056_A_ETC__q3, + SEXT_arbiter_1_1_firstHot__q15, + SEXT_arbiter_1_1_lastSelect_1__q17, + SEXT_arbiter_1_1_lastSelect__q16, + SEXT_arbiter_1_firstHot_1__q11, + SEXT_arbiter_1_firstHot__q5, + SEXT_arbiter_1_lastSelect_1__q7, + SEXT_arbiter_1_lastSelect_2__q12, + SEXT_arbiter_1_lastSelect__q6, + SEXT_arbiter_firstHot__q1, + SEXT_arbiter_lastSelect__q2, + SEXT_x2193__q4, + SEXT_x6033__q14, + SEXT_x6679__q9, + SEXT_x6713__q10, + SEXT_x7978__q19, + SEXT_x8012__q20; + wire IF_NOT_ifcs_0_1_innerRoute_first__638_BIT_1_64_ETC___d1660, + IF_NOT_ifcs_0_innerRoute_first__000_BIT_1_009__ETC___d1022, + IF_NOT_ifcs_1_1_innerRoute_first__667_BIT_1_67_ETC___d1676, + IF_NOT_ifcs_1_innerRoute_first__029_BIT_1_033__ETC___d1038, + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1912, + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1918, + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1924, + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1284, + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1290, + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1296, + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1712, + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1716, + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1074, + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1078, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d760, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d821, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d857, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d918, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872, + IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992, + IF_split_1_flitLeft_03_EQ_0_04_THEN_ssNoSynth__ETC___d993, + IF_split_2_flitLeft_32_EQ_0_33_THEN_ssNoSynth__ETC___d994, + SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893, + SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887, + SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881, + SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700, + SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265, + SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259, + SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253, + SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696, + SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062, + SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058, + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411, + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412, + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415, + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416, + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497, + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498, + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501, + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502, + plic_RDY_server_reset_request_put_AND_cpu_RDY__ETC___d8, + reqWires_1_0_whas__226_AND_reqWires_1_0_wget___ETC___d1236, + reqWires_1_1_0_whas__854_AND_reqWires_1_1_0_wg_ETC___d1864, + split_0_doPut_whas__66_AND_split_0_doPut_wget__ETC___d673, + split_1_doPut_whas__95_AND_split_1_doPut_wget__ETC___d702, + split_2_doPut_whas__24_AND_split_2_doPut_wget__ETC___d731, + state_047_AND_activeSource_0_120_121_AND_ifcs__ETC___d1123, + state_047_AND_activeSource_1_164_165_AND_ifcs__ETC___d1167, + state_1_1_1_865_AND_activeSource_1_1_0_959_960_ETC___d1962, + state_1_1_1_865_AND_activeSource_1_1_1_1_995_9_ETC___d1998, + state_1_1_1_865_AND_activeSource_1_1_2_031_032_ETC___d2034, + state_1_1_685_AND_activeSource_1_0_1_752_753_A_ETC___d1755, + state_1_1_685_AND_activeSource_1_1_1_792_793_A_ETC___d1795, + state_1_237_AND_activeSource_1_0_325_326_AND_i_ETC___d1328, + state_1_237_AND_activeSource_1_1_358_359_AND_i_ETC___d1361, + state_1_237_AND_activeSource_1_2_392_393_AND_i_ETC___d1395, + x__h31666, + x__h31769, + x__h32134, + x__h32193, + x__h32275, + x__h45858, + x__h45860, + x__h46009, + x__h46011, + x__h46145, + x__h46147, + x__h46617, + x__h46619, + x__h46679, + x__h46713, + x__h46805, + x__h46807, + x__h46986, + x__h46988, + x__h65506, + x__h65609, + x__h65974, + x__h66033, + x__h66115, + x__h77157, + x__h77159, + x__h77308, + x__h77310, + x__h77444, + x__h77446, + x__h77916, + x__h77918, + x__h77978, + x__h78012, + x__h78104, + x__h78106, + x__h78285, + x__h78287, + y__h31667, + y__h31770, + y__h32135, + y__h32276, + y__h45859, + y__h45861, + y__h46010, + y__h46012, + y__h46146, + y__h46148, + y__h46618, + y__h46620, + y__h46806, + y__h46808, + y__h46987, + y__h46989, + y__h65507, + y__h65610, + y__h65975, + y__h66116, + y__h77158, + y__h77160, + y__h77309, + y__h77311, + y__h77445, + y__h77447, + y__h77917, + y__h77919, + y__h78105, + y__h78107, + y__h78286, + y__h78288; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; @@ -1661,213 +2855,213 @@ module mkCore(CLK, assign WILL_FIRE_cpu_reset_server_response_get = EN_cpu_reset_server_response_get ; - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - - // value method cpu_imem_master_m_awid + // value method cpu_imem_master_aw_awid assign cpu_imem_master_awid = cpu$imem_master_awid ; - // value method cpu_imem_master_m_awaddr + // value method cpu_imem_master_aw_awaddr assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; - // value method cpu_imem_master_m_awlen + // value method cpu_imem_master_aw_awlen assign cpu_imem_master_awlen = cpu$imem_master_awlen ; - // value method cpu_imem_master_m_awsize + // value method cpu_imem_master_aw_awsize assign cpu_imem_master_awsize = cpu$imem_master_awsize ; - // value method cpu_imem_master_m_awburst + // value method cpu_imem_master_aw_awburst assign cpu_imem_master_awburst = cpu$imem_master_awburst ; - // value method cpu_imem_master_m_awlock + // value method cpu_imem_master_aw_awlock assign cpu_imem_master_awlock = cpu$imem_master_awlock ; - // value method cpu_imem_master_m_awcache + // value method cpu_imem_master_aw_awcache assign cpu_imem_master_awcache = cpu$imem_master_awcache ; - // value method cpu_imem_master_m_awprot + // value method cpu_imem_master_aw_awprot assign cpu_imem_master_awprot = cpu$imem_master_awprot ; - // value method cpu_imem_master_m_awqos + // value method cpu_imem_master_aw_awqos assign cpu_imem_master_awqos = cpu$imem_master_awqos ; - // value method cpu_imem_master_m_awregion + // value method cpu_imem_master_aw_awregion assign cpu_imem_master_awregion = cpu$imem_master_awregion ; - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; + // value method cpu_imem_master_aw_awvalid + assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; + // action method cpu_imem_master_aw_awready + assign CAN_FIRE_cpu_imem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_aw_awready = 1'd1 ; - // value method cpu_imem_master_m_wdata + // value method cpu_imem_master_w_wdata assign cpu_imem_master_wdata = cpu$imem_master_wdata ; - // value method cpu_imem_master_m_wstrb + // value method cpu_imem_master_w_wstrb assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; - // value method cpu_imem_master_m_wlast + // value method cpu_imem_master_w_wlast assign cpu_imem_master_wlast = cpu$imem_master_wlast ; - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; + // value method cpu_imem_master_w_wvalid + assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; + // action method cpu_imem_master_w_wready + assign CAN_FIRE_cpu_imem_master_w_wready = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_w_wready = 1'd1 ; - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = cpu$imem_master_bready ; + // action method cpu_imem_master_b_bflit + assign CAN_FIRE_cpu_imem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_b_bflit = cpu_imem_master_bvalid ; - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; + // value method cpu_imem_master_b_bready + assign cpu_imem_master_bready = cpu$imem_master_bready ; - // value method cpu_imem_master_m_arid + // value method cpu_imem_master_ar_arid assign cpu_imem_master_arid = cpu$imem_master_arid ; - // value method cpu_imem_master_m_araddr + // value method cpu_imem_master_ar_araddr assign cpu_imem_master_araddr = cpu$imem_master_araddr ; - // value method cpu_imem_master_m_arlen + // value method cpu_imem_master_ar_arlen assign cpu_imem_master_arlen = cpu$imem_master_arlen ; - // value method cpu_imem_master_m_arsize + // value method cpu_imem_master_ar_arsize assign cpu_imem_master_arsize = cpu$imem_master_arsize ; - // value method cpu_imem_master_m_arburst + // value method cpu_imem_master_ar_arburst assign cpu_imem_master_arburst = cpu$imem_master_arburst ; - // value method cpu_imem_master_m_arlock + // value method cpu_imem_master_ar_arlock assign cpu_imem_master_arlock = cpu$imem_master_arlock ; - // value method cpu_imem_master_m_arcache + // value method cpu_imem_master_ar_arcache assign cpu_imem_master_arcache = cpu$imem_master_arcache ; - // value method cpu_imem_master_m_arprot + // value method cpu_imem_master_ar_arprot assign cpu_imem_master_arprot = cpu$imem_master_arprot ; - // value method cpu_imem_master_m_arqos + // value method cpu_imem_master_ar_arqos assign cpu_imem_master_arqos = cpu$imem_master_arqos ; - // value method cpu_imem_master_m_arregion + // value method cpu_imem_master_ar_arregion assign cpu_imem_master_arregion = cpu$imem_master_arregion ; - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; + // value method cpu_imem_master_ar_arvalid + assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; + + // action method cpu_imem_master_ar_arready + assign CAN_FIRE_cpu_imem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_ar_arready = 1'd1 ; - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; + // action method cpu_imem_master_r_rflit + assign CAN_FIRE_cpu_imem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_r_rflit = cpu_imem_master_rvalid ; - // value method cpu_imem_master_m_rready + // value method cpu_imem_master_r_rready assign cpu_imem_master_rready = cpu$imem_master_rready ; - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; + // value method cpu_dmem_master_aw_awid + assign cpu_dmem_master_awid = shim_awff$D_OUT[97:93] ; - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; + // value method cpu_dmem_master_aw_awaddr + assign cpu_dmem_master_awaddr = shim_awff$D_OUT[92:29] ; - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; + // value method cpu_dmem_master_aw_awlen + assign cpu_dmem_master_awlen = shim_awff$D_OUT[28:21] ; - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; + // value method cpu_dmem_master_aw_awsize + assign cpu_dmem_master_awsize = shim_awff$D_OUT[20:18] ; - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; + // value method cpu_dmem_master_aw_awburst + assign cpu_dmem_master_awburst = shim_awff$D_OUT[17:16] ; - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; + // value method cpu_dmem_master_aw_awlock + assign cpu_dmem_master_awlock = shim_awff$D_OUT[15] ; - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; + // value method cpu_dmem_master_aw_awcache + assign cpu_dmem_master_awcache = shim_awff$D_OUT[14:11] ; - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; + // value method cpu_dmem_master_aw_awprot + assign cpu_dmem_master_awprot = shim_awff$D_OUT[10:8] ; - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; + // value method cpu_dmem_master_aw_awqos + assign cpu_dmem_master_awqos = shim_awff$D_OUT[7:4] ; - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; + // value method cpu_dmem_master_aw_awregion + assign cpu_dmem_master_awregion = shim_awff$D_OUT[3:0] ; - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; + // value method cpu_dmem_master_aw_awvalid + assign cpu_dmem_master_awvalid = shim_awff$EMPTY_N ; - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; + // action method cpu_dmem_master_aw_awready + assign CAN_FIRE_cpu_dmem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_aw_awready = 1'd1 ; - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; + // value method cpu_dmem_master_w_wdata + assign cpu_dmem_master_wdata = shim_wff$D_OUT[72:9] ; - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; + // value method cpu_dmem_master_w_wstrb + assign cpu_dmem_master_wstrb = shim_wff$D_OUT[8:1] ; - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; + // value method cpu_dmem_master_w_wlast + assign cpu_dmem_master_wlast = shim_wff$D_OUT[0] ; - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; + // value method cpu_dmem_master_w_wvalid + assign cpu_dmem_master_wvalid = shim_wff$EMPTY_N ; - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; + // action method cpu_dmem_master_w_wready + assign CAN_FIRE_cpu_dmem_master_w_wready = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_w_wready = 1'd1 ; - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; + // action method cpu_dmem_master_b_bflit + assign CAN_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_b_bflit = cpu_dmem_master_bvalid ; - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; + // value method cpu_dmem_master_b_bready + assign cpu_dmem_master_bready = shim_bff$FULL_N ; - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; + // value method cpu_dmem_master_ar_arid + assign cpu_dmem_master_arid = shim_arff$D_OUT[97:93] ; - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; + // value method cpu_dmem_master_ar_araddr + assign cpu_dmem_master_araddr = shim_arff$D_OUT[92:29] ; - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; + // value method cpu_dmem_master_ar_arlen + assign cpu_dmem_master_arlen = shim_arff$D_OUT[28:21] ; - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; + // value method cpu_dmem_master_ar_arsize + assign cpu_dmem_master_arsize = shim_arff$D_OUT[20:18] ; - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; + // value method cpu_dmem_master_ar_arburst + assign cpu_dmem_master_arburst = shim_arff$D_OUT[17:16] ; - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; + // value method cpu_dmem_master_ar_arlock + assign cpu_dmem_master_arlock = shim_arff$D_OUT[15] ; - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; + // value method cpu_dmem_master_ar_arcache + assign cpu_dmem_master_arcache = shim_arff$D_OUT[14:11] ; - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; + // value method cpu_dmem_master_ar_arprot + assign cpu_dmem_master_arprot = shim_arff$D_OUT[10:8] ; - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; + // value method cpu_dmem_master_ar_arqos + assign cpu_dmem_master_arqos = shim_arff$D_OUT[7:4] ; - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; + // value method cpu_dmem_master_ar_arregion + assign cpu_dmem_master_arregion = shim_arff$D_OUT[3:0] ; - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; + // value method cpu_dmem_master_ar_arvalid + assign cpu_dmem_master_arvalid = shim_arff$EMPTY_N ; - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; + // action method cpu_dmem_master_ar_arready + assign CAN_FIRE_cpu_dmem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_ar_arready = 1'd1 ; - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; + // action method cpu_dmem_master_r_rflit + assign CAN_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_r_rflit = cpu_dmem_master_rvalid ; - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; + // value method cpu_dmem_master_r_rready + assign cpu_dmem_master_rready = shim_rff$FULL_N ; // action method core_external_interrupt_sources_0_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; @@ -1984,12 +3178,10 @@ module mkCore(CLK, .dmem_master_awready(cpu$dmem_master_awready), .dmem_master_bid(cpu$dmem_master_bid), .dmem_master_bresp(cpu$dmem_master_bresp), - .dmem_master_bvalid(cpu$dmem_master_bvalid), .dmem_master_rdata(cpu$dmem_master_rdata), .dmem_master_rid(cpu$dmem_master_rid), .dmem_master_rlast(cpu$dmem_master_rlast), .dmem_master_rresp(cpu$dmem_master_rresp), - .dmem_master_rvalid(cpu$dmem_master_rvalid), .dmem_master_wready(cpu$dmem_master_wready), .hart0_csr_mem_server_request_put(cpu$hart0_csr_mem_server_request_put), .hart0_gpr_mem_server_request_put(cpu$hart0_gpr_mem_server_request_put), @@ -2000,12 +3192,10 @@ module mkCore(CLK, .imem_master_awready(cpu$imem_master_awready), .imem_master_bid(cpu$imem_master_bid), .imem_master_bresp(cpu$imem_master_bresp), - .imem_master_bvalid(cpu$imem_master_bvalid), .imem_master_rdata(cpu$imem_master_rdata), .imem_master_rid(cpu$imem_master_rid), .imem_master_rlast(cpu$imem_master_rlast), .imem_master_rresp(cpu$imem_master_rresp), - .imem_master_rvalid(cpu$imem_master_rvalid), .imem_master_wready(cpu$imem_master_wready), .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), @@ -2016,6 +3206,10 @@ module mkCore(CLK, .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), + .imem_master_bvalid(cpu$imem_master_bvalid), + .imem_master_rvalid(cpu$imem_master_rvalid), + .dmem_master_bvalid(cpu$dmem_master_bvalid), + .dmem_master_rvalid(cpu$dmem_master_rvalid), .EN_set_verbosity(cpu$EN_set_verbosity), .EN_trace_data_out_get(cpu$EN_trace_data_out_get), .EN_hart0_server_run_halt_request_put(cpu$EN_hart0_server_run_halt_request_put), @@ -2028,7 +3222,6 @@ module mkCore(CLK, .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), - .imem_master_awvalid(cpu$imem_master_awvalid), .imem_master_awid(cpu$imem_master_awid), .imem_master_awaddr(cpu$imem_master_awaddr), .imem_master_awlen(cpu$imem_master_awlen), @@ -2039,12 +3232,12 @@ module mkCore(CLK, .imem_master_awprot(cpu$imem_master_awprot), .imem_master_awqos(cpu$imem_master_awqos), .imem_master_awregion(cpu$imem_master_awregion), - .imem_master_wvalid(cpu$imem_master_wvalid), + .imem_master_awvalid(cpu$imem_master_awvalid), .imem_master_wdata(cpu$imem_master_wdata), .imem_master_wstrb(cpu$imem_master_wstrb), .imem_master_wlast(cpu$imem_master_wlast), + .imem_master_wvalid(cpu$imem_master_wvalid), .imem_master_bready(cpu$imem_master_bready), - .imem_master_arvalid(cpu$imem_master_arvalid), .imem_master_arid(cpu$imem_master_arid), .imem_master_araddr(cpu$imem_master_araddr), .imem_master_arlen(cpu$imem_master_arlen), @@ -2055,8 +3248,8 @@ module mkCore(CLK, .imem_master_arprot(cpu$imem_master_arprot), .imem_master_arqos(cpu$imem_master_arqos), .imem_master_arregion(cpu$imem_master_arregion), + .imem_master_arvalid(cpu$imem_master_arvalid), .imem_master_rready(cpu$imem_master_rready), - .dmem_master_awvalid(cpu$dmem_master_awvalid), .dmem_master_awid(cpu$dmem_master_awid), .dmem_master_awaddr(cpu$dmem_master_awaddr), .dmem_master_awlen(cpu$dmem_master_awlen), @@ -2067,12 +3260,12 @@ module mkCore(CLK, .dmem_master_awprot(cpu$dmem_master_awprot), .dmem_master_awqos(cpu$dmem_master_awqos), .dmem_master_awregion(cpu$dmem_master_awregion), - .dmem_master_wvalid(cpu$dmem_master_wvalid), + .dmem_master_awvalid(cpu$dmem_master_awvalid), .dmem_master_wdata(cpu$dmem_master_wdata), .dmem_master_wstrb(cpu$dmem_master_wstrb), .dmem_master_wlast(cpu$dmem_master_wlast), + .dmem_master_wvalid(cpu$dmem_master_wvalid), .dmem_master_bready(cpu$dmem_master_bready), - .dmem_master_arvalid(cpu$dmem_master_arvalid), .dmem_master_arid(cpu$dmem_master_arid), .dmem_master_araddr(cpu$dmem_master_araddr), .dmem_master_arlen(cpu$dmem_master_arlen), @@ -2083,6 +3276,7 @@ module mkCore(CLK, .dmem_master_arprot(cpu$dmem_master_arprot), .dmem_master_arqos(cpu$dmem_master_arqos), .dmem_master_arregion(cpu$dmem_master_arregion), + .dmem_master_arvalid(cpu$dmem_master_arvalid), .dmem_master_rready(cpu$dmem_master_rready), .RDY_set_verbosity(), .trace_data_out_get(cpu$trace_data_out_get), @@ -2112,12 +3306,10 @@ module mkCore(CLK, .master_awready(debug_module$master_awready), .master_bid(debug_module$master_bid), .master_bresp(debug_module$master_bresp), - .master_bvalid(debug_module$master_bvalid), .master_rdata(debug_module$master_rdata), .master_rid(debug_module$master_rid), .master_rlast(debug_module$master_rlast), .master_rresp(debug_module$master_rresp), - .master_rvalid(debug_module$master_rvalid), .master_wready(debug_module$master_wready), .ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put), .EN_dmi_read_addr(debug_module$EN_dmi_read_addr), @@ -2134,6 +3326,8 @@ module mkCore(CLK, .EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put), .EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get), .EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put), + .master_bvalid(debug_module$master_bvalid), + .master_rvalid(debug_module$master_rvalid), .RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr), .dmi_read_data(debug_module$dmi_read_data), .RDY_dmi_read_data(debug_module$RDY_dmi_read_data), @@ -2155,7 +3349,6 @@ module mkCore(CLK, .ndm_reset_client_request_get(debug_module$ndm_reset_client_request_get), .RDY_ndm_reset_client_request_get(debug_module$RDY_ndm_reset_client_request_get), .RDY_ndm_reset_client_response_put(debug_module$RDY_ndm_reset_client_response_put), - .master_awvalid(debug_module$master_awvalid), .master_awid(debug_module$master_awid), .master_awaddr(debug_module$master_awaddr), .master_awlen(debug_module$master_awlen), @@ -2166,12 +3359,12 @@ module mkCore(CLK, .master_awprot(debug_module$master_awprot), .master_awqos(debug_module$master_awqos), .master_awregion(debug_module$master_awregion), - .master_wvalid(debug_module$master_wvalid), + .master_awvalid(debug_module$master_awvalid), .master_wdata(debug_module$master_wdata), .master_wstrb(debug_module$master_wstrb), .master_wlast(debug_module$master_wlast), + .master_wvalid(debug_module$master_wvalid), .master_bready(debug_module$master_bready), - .master_arvalid(debug_module$master_arvalid), .master_arid(debug_module$master_arid), .master_araddr(debug_module$master_araddr), .master_arlen(debug_module$master_arlen), @@ -2182,6 +3375,7 @@ module mkCore(CLK, .master_arprot(debug_module$master_arprot), .master_arqos(debug_module$master_arqos), .master_arregion(debug_module$master_arregion), + .master_arvalid(debug_module$master_arvalid), .master_rready(debug_module$master_rready)); // submodule dm_csr_tap @@ -2229,12 +3423,10 @@ module mkCore(CLK, .master_awready(dm_mem_tap$master_awready), .master_bid(dm_mem_tap$master_bid), .master_bresp(dm_mem_tap$master_bresp), - .master_bvalid(dm_mem_tap$master_bvalid), .master_rdata(dm_mem_tap$master_rdata), .master_rid(dm_mem_tap$master_rid), .master_rlast(dm_mem_tap$master_rlast), .master_rresp(dm_mem_tap$master_rresp), - .master_rvalid(dm_mem_tap$master_rvalid), .master_wready(dm_mem_tap$master_wready), .slave_araddr(dm_mem_tap$slave_araddr), .slave_arburst(dm_mem_tap$slave_arburst), @@ -2246,7 +3438,6 @@ module mkCore(CLK, .slave_arqos(dm_mem_tap$slave_arqos), .slave_arregion(dm_mem_tap$slave_arregion), .slave_arsize(dm_mem_tap$slave_arsize), - .slave_arvalid(dm_mem_tap$slave_arvalid), .slave_awaddr(dm_mem_tap$slave_awaddr), .slave_awburst(dm_mem_tap$slave_awburst), .slave_awcache(dm_mem_tap$slave_awcache), @@ -2257,26 +3448,28 @@ module mkCore(CLK, .slave_awqos(dm_mem_tap$slave_awqos), .slave_awregion(dm_mem_tap$slave_awregion), .slave_awsize(dm_mem_tap$slave_awsize), - .slave_awvalid(dm_mem_tap$slave_awvalid), .slave_bready(dm_mem_tap$slave_bready), .slave_rready(dm_mem_tap$slave_rready), .slave_wdata(dm_mem_tap$slave_wdata), .slave_wlast(dm_mem_tap$slave_wlast), .slave_wstrb(dm_mem_tap$slave_wstrb), + .slave_awvalid(dm_mem_tap$slave_awvalid), .slave_wvalid(dm_mem_tap$slave_wvalid), + .slave_arvalid(dm_mem_tap$slave_arvalid), + .master_bvalid(dm_mem_tap$master_bvalid), + .master_rvalid(dm_mem_tap$master_rvalid), .EN_trace_data_out_get(dm_mem_tap$EN_trace_data_out_get), .slave_awready(dm_mem_tap$slave_awready), .slave_wready(dm_mem_tap$slave_wready), - .slave_bvalid(dm_mem_tap$slave_bvalid), .slave_bid(dm_mem_tap$slave_bid), .slave_bresp(dm_mem_tap$slave_bresp), + .slave_bvalid(dm_mem_tap$slave_bvalid), .slave_arready(dm_mem_tap$slave_arready), - .slave_rvalid(dm_mem_tap$slave_rvalid), .slave_rid(dm_mem_tap$slave_rid), .slave_rdata(dm_mem_tap$slave_rdata), .slave_rresp(dm_mem_tap$slave_rresp), .slave_rlast(dm_mem_tap$slave_rlast), - .master_awvalid(dm_mem_tap$master_awvalid), + .slave_rvalid(dm_mem_tap$slave_rvalid), .master_awid(dm_mem_tap$master_awid), .master_awaddr(dm_mem_tap$master_awaddr), .master_awlen(dm_mem_tap$master_awlen), @@ -2287,12 +3480,12 @@ module mkCore(CLK, .master_awprot(dm_mem_tap$master_awprot), .master_awqos(dm_mem_tap$master_awqos), .master_awregion(dm_mem_tap$master_awregion), - .master_wvalid(dm_mem_tap$master_wvalid), + .master_awvalid(dm_mem_tap$master_awvalid), .master_wdata(dm_mem_tap$master_wdata), .master_wstrb(dm_mem_tap$master_wstrb), .master_wlast(dm_mem_tap$master_wlast), + .master_wvalid(dm_mem_tap$master_wvalid), .master_bready(dm_mem_tap$master_bready), - .master_arvalid(dm_mem_tap$master_arvalid), .master_arid(dm_mem_tap$master_arid), .master_araddr(dm_mem_tap$master_araddr), .master_arlen(dm_mem_tap$master_arlen), @@ -2303,6 +3496,7 @@ module mkCore(CLK, .master_arprot(dm_mem_tap$master_arprot), .master_arqos(dm_mem_tap$master_arqos), .master_arregion(dm_mem_tap$master_arregion), + .master_arvalid(dm_mem_tap$master_arvalid), .master_rready(dm_mem_tap$master_rready), .trace_data_out_get(dm_mem_tap$trace_data_out_get), .RDY_trace_data_out_get(dm_mem_tap$RDY_trace_data_out_get)); @@ -2351,209 +3545,343 @@ module mkCore(CLK, .FULL_N(f_trace_data_merged$FULL_N), .EMPTY_N(f_trace_data_merged$EMPTY_N)); - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric_2x3$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric_2x3$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric_2x3$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric_2x3$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric_2x3$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric_2x3$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric_2x3$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric_2x3$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric_2x3$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric_2x3$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric_2x3$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); + // submodule ifcs_0_1_innerReq + FIFO2 #(.width(32'd98), .guarded(32'd1)) ifcs_0_1_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_innerReq$D_IN), + .ENQ(ifcs_0_1_innerReq$ENQ), + .DEQ(ifcs_0_1_innerReq$DEQ), + .CLR(ifcs_0_1_innerReq$CLR), + .D_OUT(ifcs_0_1_innerReq$D_OUT), + .FULL_N(ifcs_0_1_innerReq$FULL_N), + .EMPTY_N(ifcs_0_1_innerReq$EMPTY_N)); + + // submodule ifcs_0_1_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_0_1_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_innerRoute$D_IN), + .ENQ(ifcs_0_1_innerRoute$ENQ), + .DEQ(ifcs_0_1_innerRoute$DEQ), + .CLR(ifcs_0_1_innerRoute$CLR), + .D_OUT(ifcs_0_1_innerRoute$D_OUT), + .FULL_N(ifcs_0_1_innerRoute$FULL_N), + .EMPTY_N(ifcs_0_1_innerRoute$EMPTY_N)); + + // submodule ifcs_0_1_noRouteRsp + FIFO2 #(.width(32'd71), .guarded(32'd1)) ifcs_0_1_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_noRouteRsp$D_IN), + .ENQ(ifcs_0_1_noRouteRsp$ENQ), + .DEQ(ifcs_0_1_noRouteRsp$DEQ), + .CLR(ifcs_0_1_noRouteRsp$CLR), + .D_OUT(ifcs_0_1_noRouteRsp$D_OUT), + .FULL_N(ifcs_0_1_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_0_1_noRouteRsp$EMPTY_N)); + + // submodule ifcs_0_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_0_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_routeBack$D_IN), + .ENQ(ifcs_0_1_routeBack$ENQ), + .DEQ(ifcs_0_1_routeBack$DEQ), + .CLR(ifcs_0_1_routeBack$CLR), + .D_OUT(ifcs_0_1_routeBack$D_OUT), + .FULL_N(ifcs_0_1_routeBack$FULL_N), + .EMPTY_N(ifcs_0_1_routeBack$EMPTY_N)); + + // submodule ifcs_0_1_rspBack + FIFO2 #(.width(32'd71), .guarded(32'd1)) ifcs_0_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_rspBack$D_IN), + .ENQ(ifcs_0_1_rspBack$ENQ), + .DEQ(ifcs_0_1_rspBack$DEQ), + .CLR(ifcs_0_1_rspBack$CLR), + .D_OUT(ifcs_0_1_rspBack$D_OUT), + .FULL_N(ifcs_0_1_rspBack$FULL_N), + .EMPTY_N(ifcs_0_1_rspBack$EMPTY_N)); + + // submodule ifcs_0_innerReq + FIFO2 #(.width(32'd172), .guarded(32'd1)) ifcs_0_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_innerReq$D_IN), + .ENQ(ifcs_0_innerReq$ENQ), + .DEQ(ifcs_0_innerReq$DEQ), + .CLR(ifcs_0_innerReq$CLR), + .D_OUT(ifcs_0_innerReq$D_OUT), + .FULL_N(ifcs_0_innerReq$FULL_N), + .EMPTY_N(ifcs_0_innerReq$EMPTY_N)); + + // submodule ifcs_0_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_0_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_innerRoute$D_IN), + .ENQ(ifcs_0_innerRoute$ENQ), + .DEQ(ifcs_0_innerRoute$DEQ), + .CLR(ifcs_0_innerRoute$CLR), + .D_OUT(ifcs_0_innerRoute$D_OUT), + .FULL_N(ifcs_0_innerRoute$FULL_N), + .EMPTY_N(ifcs_0_innerRoute$EMPTY_N)); + + // submodule ifcs_0_noRouteRsp + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_0_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_noRouteRsp$D_IN), + .ENQ(ifcs_0_noRouteRsp$ENQ), + .DEQ(ifcs_0_noRouteRsp$DEQ), + .CLR(ifcs_0_noRouteRsp$CLR), + .D_OUT(ifcs_0_noRouteRsp$D_OUT), + .FULL_N(ifcs_0_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_0_noRouteRsp$EMPTY_N)); + + // submodule ifcs_0_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_0_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_routeBack$D_IN), + .ENQ(ifcs_0_routeBack$ENQ), + .DEQ(ifcs_0_routeBack$DEQ), + .CLR(ifcs_0_routeBack$CLR), + .D_OUT(ifcs_0_routeBack$D_OUT), + .FULL_N(ifcs_0_routeBack$FULL_N), + .EMPTY_N(ifcs_0_routeBack$EMPTY_N)); + + // submodule ifcs_0_rspBack + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_0_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_rspBack$D_IN), + .ENQ(ifcs_0_rspBack$ENQ), + .DEQ(ifcs_0_rspBack$DEQ), + .CLR(ifcs_0_rspBack$CLR), + .D_OUT(ifcs_0_rspBack$D_OUT), + .FULL_N(ifcs_0_rspBack$FULL_N), + .EMPTY_N(ifcs_0_rspBack$EMPTY_N)); + + // submodule ifcs_1_1_innerReq + FIFO2 #(.width(32'd98), .guarded(32'd1)) ifcs_1_1_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_innerReq$D_IN), + .ENQ(ifcs_1_1_innerReq$ENQ), + .DEQ(ifcs_1_1_innerReq$DEQ), + .CLR(ifcs_1_1_innerReq$CLR), + .D_OUT(ifcs_1_1_innerReq$D_OUT), + .FULL_N(ifcs_1_1_innerReq$FULL_N), + .EMPTY_N(ifcs_1_1_innerReq$EMPTY_N)); + + // submodule ifcs_1_1_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_1_1_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_innerRoute$D_IN), + .ENQ(ifcs_1_1_innerRoute$ENQ), + .DEQ(ifcs_1_1_innerRoute$DEQ), + .CLR(ifcs_1_1_innerRoute$CLR), + .D_OUT(ifcs_1_1_innerRoute$D_OUT), + .FULL_N(ifcs_1_1_innerRoute$FULL_N), + .EMPTY_N(ifcs_1_1_innerRoute$EMPTY_N)); + + // submodule ifcs_1_1_noRouteRsp + FIFO2 #(.width(32'd71), .guarded(32'd1)) ifcs_1_1_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_noRouteRsp$D_IN), + .ENQ(ifcs_1_1_noRouteRsp$ENQ), + .DEQ(ifcs_1_1_noRouteRsp$DEQ), + .CLR(ifcs_1_1_noRouteRsp$CLR), + .D_OUT(ifcs_1_1_noRouteRsp$D_OUT), + .FULL_N(ifcs_1_1_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_1_1_noRouteRsp$EMPTY_N)); + + // submodule ifcs_1_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_1_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_routeBack$D_IN), + .ENQ(ifcs_1_1_routeBack$ENQ), + .DEQ(ifcs_1_1_routeBack$DEQ), + .CLR(ifcs_1_1_routeBack$CLR), + .D_OUT(ifcs_1_1_routeBack$D_OUT), + .FULL_N(ifcs_1_1_routeBack$FULL_N), + .EMPTY_N(ifcs_1_1_routeBack$EMPTY_N)); + + // submodule ifcs_1_1_rspBack + FIFO2 #(.width(32'd71), .guarded(32'd1)) ifcs_1_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_rspBack$D_IN), + .ENQ(ifcs_1_1_rspBack$ENQ), + .DEQ(ifcs_1_1_rspBack$DEQ), + .CLR(ifcs_1_1_rspBack$CLR), + .D_OUT(ifcs_1_1_rspBack$D_OUT), + .FULL_N(ifcs_1_1_rspBack$FULL_N), + .EMPTY_N(ifcs_1_1_rspBack$EMPTY_N)); + + // submodule ifcs_1_innerReq + FIFO2 #(.width(32'd172), .guarded(32'd1)) ifcs_1_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_innerReq$D_IN), + .ENQ(ifcs_1_innerReq$ENQ), + .DEQ(ifcs_1_innerReq$DEQ), + .CLR(ifcs_1_innerReq$CLR), + .D_OUT(ifcs_1_innerReq$D_OUT), + .FULL_N(ifcs_1_innerReq$FULL_N), + .EMPTY_N(ifcs_1_innerReq$EMPTY_N)); + + // submodule ifcs_1_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_1_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_innerRoute$D_IN), + .ENQ(ifcs_1_innerRoute$ENQ), + .DEQ(ifcs_1_innerRoute$DEQ), + .CLR(ifcs_1_innerRoute$CLR), + .D_OUT(ifcs_1_innerRoute$D_OUT), + .FULL_N(ifcs_1_innerRoute$FULL_N), + .EMPTY_N(ifcs_1_innerRoute$EMPTY_N)); + + // submodule ifcs_1_noRouteRsp + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_1_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_noRouteRsp$D_IN), + .ENQ(ifcs_1_noRouteRsp$ENQ), + .DEQ(ifcs_1_noRouteRsp$DEQ), + .CLR(ifcs_1_noRouteRsp$CLR), + .D_OUT(ifcs_1_noRouteRsp$D_OUT), + .FULL_N(ifcs_1_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_1_noRouteRsp$EMPTY_N)); + + // submodule ifcs_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_routeBack$D_IN), + .ENQ(ifcs_1_routeBack$ENQ), + .DEQ(ifcs_1_routeBack$DEQ), + .CLR(ifcs_1_routeBack$CLR), + .D_OUT(ifcs_1_routeBack$D_OUT), + .FULL_N(ifcs_1_routeBack$FULL_N), + .EMPTY_N(ifcs_1_routeBack$EMPTY_N)); + + // submodule ifcs_1_rspBack + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_rspBack$D_IN), + .ENQ(ifcs_1_rspBack$ENQ), + .DEQ(ifcs_1_rspBack$DEQ), + .CLR(ifcs_1_rspBack$CLR), + .D_OUT(ifcs_1_rspBack$D_OUT), + .FULL_N(ifcs_1_rspBack$FULL_N), + .EMPTY_N(ifcs_1_rspBack$EMPTY_N)); + + // submodule ifcs_2_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_2_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_1_routeBack$D_IN), + .ENQ(ifcs_2_1_routeBack$ENQ), + .DEQ(ifcs_2_1_routeBack$DEQ), + .CLR(ifcs_2_1_routeBack$CLR), + .D_OUT(ifcs_2_1_routeBack$D_OUT), + .FULL_N(ifcs_2_1_routeBack$FULL_N), + .EMPTY_N(ifcs_2_1_routeBack$EMPTY_N)); + + // submodule ifcs_2_1_rspBack + FIFO2 #(.width(32'd71), .guarded(32'd1)) ifcs_2_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_1_rspBack$D_IN), + .ENQ(ifcs_2_1_rspBack$ENQ), + .DEQ(ifcs_2_1_rspBack$DEQ), + .CLR(ifcs_2_1_rspBack$CLR), + .D_OUT(ifcs_2_1_rspBack$D_OUT), + .FULL_N(ifcs_2_1_rspBack$FULL_N), + .EMPTY_N(ifcs_2_1_rspBack$EMPTY_N)); + + // submodule ifcs_2_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_2_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_routeBack$D_IN), + .ENQ(ifcs_2_routeBack$ENQ), + .DEQ(ifcs_2_routeBack$DEQ), + .CLR(ifcs_2_routeBack$CLR), + .D_OUT(ifcs_2_routeBack$D_OUT), + .FULL_N(ifcs_2_routeBack$FULL_N), + .EMPTY_N(ifcs_2_routeBack$EMPTY_N)); + + // submodule ifcs_2_rspBack + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_2_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_rspBack$D_IN), + .ENQ(ifcs_2_rspBack$ENQ), + .DEQ(ifcs_2_rspBack$DEQ), + .CLR(ifcs_2_rspBack$CLR), + .D_OUT(ifcs_2_rspBack$D_OUT), + .FULL_N(ifcs_2_rspBack$FULL_N), + .EMPTY_N(ifcs_2_rspBack$EMPTY_N)); + + // submodule msNoSynth_0_b_buffer_ff + FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_0_b_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_b_buffer_ff$D_IN), + .ENQ(msNoSynth_0_b_buffer_ff$ENQ), + .DEQ(msNoSynth_0_b_buffer_ff$DEQ), + .CLR(msNoSynth_0_b_buffer_ff$CLR), + .D_OUT(msNoSynth_0_b_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_b_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_b_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_b_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_b_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_b_buffer_firstValid$D_IN), + .EN(msNoSynth_0_b_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_b_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_0_r_buffer_ff + FIFO1 #(.width(32'd71), + .guarded(32'd0)) msNoSynth_0_r_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_r_buffer_ff$D_IN), + .ENQ(msNoSynth_0_r_buffer_ff$ENQ), + .DEQ(msNoSynth_0_r_buffer_ff$DEQ), + .CLR(msNoSynth_0_r_buffer_ff$CLR), + .D_OUT(msNoSynth_0_r_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_r_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_r_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_r_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_r_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_r_buffer_firstValid$D_IN), + .EN(msNoSynth_0_r_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_r_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_b_buffer_ff + FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_1_b_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_b_buffer_ff$D_IN), + .ENQ(msNoSynth_1_b_buffer_ff$ENQ), + .DEQ(msNoSynth_1_b_buffer_ff$DEQ), + .CLR(msNoSynth_1_b_buffer_ff$CLR), + .D_OUT(msNoSynth_1_b_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_b_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_b_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_b_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_b_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_b_buffer_firstValid$D_IN), + .EN(msNoSynth_1_b_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_b_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_r_buffer_ff + FIFO1 #(.width(32'd71), + .guarded(32'd0)) msNoSynth_1_r_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_r_buffer_ff$D_IN), + .ENQ(msNoSynth_1_r_buffer_ff$ENQ), + .DEQ(msNoSynth_1_r_buffer_ff$DEQ), + .CLR(msNoSynth_1_r_buffer_ff$CLR), + .D_OUT(msNoSynth_1_r_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_r_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_r_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_r_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_r_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_r_buffer_firstValid$D_IN), + .EN(msNoSynth_1_r_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_r_buffer_firstValid$Q_OUT)); // submodule near_mem_io mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), @@ -2568,7 +3896,6 @@ module mkCore(CLK, .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), - .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), @@ -2579,18 +3906,19 @@ module mkCore(CLK, .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), - .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), .axi4_slave_bready(near_mem_io$axi4_slave_bready), .axi4_slave_rready(near_mem_io$axi4_slave_rready), .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), - .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), .EN_set_addr_map(near_mem_io$EN_set_addr_map), + .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), + .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), + .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), @@ -2598,15 +3926,15 @@ module mkCore(CLK, .RDY_set_addr_map(), .axi4_slave_awready(near_mem_io$axi4_slave_awready), .axi4_slave_wready(near_mem_io$axi4_slave_wready), - .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), .axi4_slave_bid(near_mem_io$axi4_slave_bid), .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), + .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), .axi4_slave_arready(near_mem_io$axi4_slave_arready), - .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), .axi4_slave_rid(near_mem_io$axi4_slave_rid), .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), + .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), @@ -2625,7 +3953,6 @@ module mkCore(CLK, .axi4_slave_arqos(plic$axi4_slave_arqos), .axi4_slave_arregion(plic$axi4_slave_arregion), .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), .axi4_slave_awaddr(plic$axi4_slave_awaddr), .axi4_slave_awburst(plic$axi4_slave_awburst), .axi4_slave_awcache(plic$axi4_slave_awcache), @@ -2636,13 +3963,11 @@ module mkCore(CLK, .axi4_slave_awqos(plic$axi4_slave_awqos), .axi4_slave_awregion(plic$axi4_slave_awregion), .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), .set_addr_map_addr_base(plic$set_addr_map_addr_base), .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), .set_verbosity_verbosity(plic$set_verbosity_verbosity), @@ -2667,6 +3992,9 @@ module mkCore(CLK, .EN_server_reset_request_put(plic$EN_server_reset_request_put), .EN_server_reset_response_get(plic$EN_server_reset_response_get), .EN_set_addr_map(plic$EN_set_addr_map), + .axi4_slave_awvalid(plic$axi4_slave_awvalid), + .axi4_slave_wvalid(plic$axi4_slave_wvalid), + .axi4_slave_arvalid(plic$axi4_slave_arvalid), .RDY_set_verbosity(), .RDY_show_PLIC_state(), .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), @@ -2674,54 +4002,104 @@ module mkCore(CLK, .RDY_set_addr_map(), .axi4_slave_awready(plic$axi4_slave_awready), .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), .axi4_slave_bid(plic$axi4_slave_bid), .axi4_slave_bresp(plic$axi4_slave_bresp), + .axi4_slave_bvalid(plic$axi4_slave_bvalid), .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), .axi4_slave_rid(plic$axi4_slave_rid), .axi4_slave_rdata(plic$axi4_slave_rdata), .axi4_slave_rresp(plic$axi4_slave_rresp), .axi4_slave_rlast(plic$axi4_slave_rlast), + .axi4_slave_rvalid(plic$axi4_slave_rvalid), .v_targets_0_m_eip(plic$v_targets_0_m_eip), .v_targets_1_m_eip(plic$v_targets_1_m_eip)); + // submodule shim_arff + SizedFIFO #(.p1width(32'd98), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd0)) shim_arff(.RST(RST_N), + .CLK(CLK), + .D_IN(shim_arff$D_IN), + .ENQ(shim_arff$ENQ), + .DEQ(shim_arff$DEQ), + .CLR(shim_arff$CLR), + .D_OUT(shim_arff$D_OUT), + .FULL_N(shim_arff$FULL_N), + .EMPTY_N(shim_arff$EMPTY_N)); + + // submodule shim_awff + SizedFIFO #(.p1width(32'd98), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd0)) shim_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(shim_awff$D_IN), + .ENQ(shim_awff$ENQ), + .DEQ(shim_awff$DEQ), + .CLR(shim_awff$CLR), + .D_OUT(shim_awff$D_OUT), + .FULL_N(shim_awff$FULL_N), + .EMPTY_N(shim_awff$EMPTY_N)); + + // submodule shim_bff + SizedFIFO #(.p1width(32'd7), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd0)) shim_bff(.RST(RST_N), + .CLK(CLK), + .D_IN(shim_bff$D_IN), + .ENQ(shim_bff$ENQ), + .DEQ(shim_bff$DEQ), + .CLR(shim_bff$CLR), + .D_OUT(shim_bff$D_OUT), + .FULL_N(shim_bff$FULL_N), + .EMPTY_N(shim_bff$EMPTY_N)); + + // submodule shim_rff + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd0)) shim_rff(.RST(RST_N), + .CLK(CLK), + .D_IN(shim_rff$D_IN), + .ENQ(shim_rff$ENQ), + .DEQ(shim_rff$DEQ), + .CLR(shim_rff$CLR), + .D_OUT(shim_rff$D_OUT), + .FULL_N(shim_rff$FULL_N), + .EMPTY_N(shim_rff$EMPTY_N)); + + // submodule shim_wff + SizedFIFO #(.p1width(32'd73), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd0)) shim_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(shim_wff$D_IN), + .ENQ(shim_wff$ENQ), + .DEQ(shim_wff$DEQ), + .CLR(shim_wff$CLR), + .D_OUT(shim_wff$D_OUT), + .FULL_N(shim_wff$FULL_N), + .EMPTY_N(shim_wff$EMPTY_N)); + // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), .RST_N(RST_N), .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_flash_mem_addr_base(), - .m_flash_mem_addr_size(), - .m_flash_mem_addr_lim(), - .m_ethernet_0_addr_base(), - .m_ethernet_0_addr_size(), - .m_ethernet_0_addr_lim(), - .m_dma_0_addr_base(), - .m_dma_0_addr_size(), - .m_dma_0_addr_lim(), - .m_uart16550_0_addr_base(), - .m_uart16550_0_addr_size(), - .m_uart16550_0_addr_lim(), - .m_gpio_0_addr_base(), - .m_gpio_0_addr_size(), - .m_gpio_0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_ddr4_0_uncached_addr_base(), - .m_ddr4_0_uncached_addr_size(), - .m_ddr4_0_uncached_addr_lim(), - .m_ddr4_0_cached_addr_base(), - .m_ddr4_0_cached_addr_size(), - .m_ddr4_0_cached_addr_lim(), + .m_plic_addr_range(soc_map$m_plic_addr_range), + .m_near_mem_io_addr_range(soc_map$m_near_mem_io_addr_range), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), @@ -2729,6 +4107,177 @@ module mkCore(CLK, .m_mtvec_reset_value(), .m_nmivec_reset_value()); + // submodule ssNoSynth_0_ar_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_0_ar_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_ar_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_ar_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_ar_buffer_ff$DEQ), + .CLR(ssNoSynth_0_ar_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_ar_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_ar_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_ar_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_ar_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_ar_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_ar_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_ar_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_ar_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_0_aw_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_0_aw_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_aw_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_aw_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_aw_buffer_ff$DEQ), + .CLR(ssNoSynth_0_aw_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_aw_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_aw_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_aw_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_aw_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_aw_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_aw_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_aw_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_aw_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_0_w_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_0_w_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_w_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_w_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_w_buffer_ff$DEQ), + .CLR(ssNoSynth_0_w_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_w_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_w_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_w_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_w_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_w_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_w_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_w_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_w_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_ar_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_1_ar_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_ar_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_ar_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_ar_buffer_ff$DEQ), + .CLR(ssNoSynth_1_ar_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_ar_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_ar_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_ar_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_ar_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_ar_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_ar_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_ar_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_ar_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_aw_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_1_aw_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_aw_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_aw_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_aw_buffer_ff$DEQ), + .CLR(ssNoSynth_1_aw_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_aw_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_aw_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_aw_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_aw_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_aw_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_aw_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_aw_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_aw_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_w_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_1_w_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_w_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_w_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_w_buffer_ff$DEQ), + .CLR(ssNoSynth_1_w_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_w_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_w_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_w_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_w_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_w_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_w_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_w_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_w_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_ar_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_2_ar_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_ar_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_ar_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_ar_buffer_ff$DEQ), + .CLR(ssNoSynth_2_ar_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_ar_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_ar_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_ar_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_ar_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_ar_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_ar_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_ar_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_ar_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_aw_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_2_aw_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_aw_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_aw_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_aw_buffer_ff$DEQ), + .CLR(ssNoSynth_2_aw_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_aw_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_aw_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_aw_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_aw_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_aw_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_aw_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_aw_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_aw_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_w_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_2_w_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_w_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_w_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_w_buffer_ff$DEQ), + .CLR(ssNoSynth_2_w_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_w_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_w_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_w_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_w_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_w_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_w_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_w_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_w_buffer_firstValid$Q_OUT)); + // submodule tv_encode mkTV_Encode tv_encode(.CLK(CLK), .RST_N(RST_N), @@ -2766,29 +4315,20 @@ module mkCore(CLK, assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - dm_gpr_tap_ifc$RDY_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + dm_gpr_tap_ifc$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; + // rule RL_ClientServerResponse_1 + assign CAN_FIRE_RL_ClientServerResponse_1 = + debug_module$RDY_hart0_gpr_mem_client_response_put && + dm_gpr_tap_ifc$RDY_server_response_get ; + assign WILL_FIRE_RL_ClientServerResponse_1 = + CAN_FIRE_RL_ClientServerResponse_1 ; + // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = dm_gpr_tap_ifc$RDY_client_request_get && @@ -2796,13 +4336,6 @@ module mkCore(CLK, assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; - // rule RL_ClientServerResponse_1 - assign CAN_FIRE_RL_ClientServerResponse_1 = - dm_gpr_tap_ifc$RDY_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; - assign WILL_FIRE_RL_ClientServerResponse_1 = - CAN_FIRE_RL_ClientServerResponse_1 ; - // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = dm_gpr_tap_ifc$RDY_client_response_put && @@ -2819,15 +4352,15 @@ module mkCore(CLK, // rule RL_ClientServerRequest_3 assign CAN_FIRE_RL_ClientServerRequest_3 = - dm_csr_tap$RDY_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + dm_csr_tap$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_3 = CAN_FIRE_RL_ClientServerRequest_3 ; // rule RL_ClientServerResponse_3 assign CAN_FIRE_RL_ClientServerResponse_3 = - dm_csr_tap$RDY_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + dm_csr_tap$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_3 = CAN_FIRE_RL_ClientServerResponse_3 ; @@ -2869,85 +4402,942 @@ module mkCore(CLK, CAN_FIRE_RL_merge_dm_csr_trace_data && !WILL_FIRE_RL_merge_dm_gpr_trace_data ; - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; + // rule RL_checkSinkReady + assign CAN_FIRE_RL_checkSinkReady = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady = 1'd1 ; + + // rule RL_checkSinkReady_1 + assign CAN_FIRE_RL_checkSinkReady_1 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_1 = 1'd1 ; + + // rule RL_checkSinkReady_2 + assign CAN_FIRE_RL_checkSinkReady_2 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_2 = 1'd1 ; + + // rule RL_craftReq + assign CAN_FIRE_RL_craftReq = + ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq = CAN_FIRE_RL_craftReq ; + + // rule RL_craftReq_1 + assign CAN_FIRE_RL_craftReq_1 = + ifcs_1_innerRoute$EMPTY_N && ifcs_1_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_1 = CAN_FIRE_RL_craftReq_1 ; + + // rule RL_arbitrate + assign CAN_FIRE_RL_arbitrate = + (CAN_FIRE_RL_craftReq && reqWires_0$wget || + CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) && + !state ; + assign WILL_FIRE_RL_arbitrate = CAN_FIRE_RL_arbitrate ; + + // rule RL_source_selected + assign CAN_FIRE_RL_source_selected = + (!ifcs_0_innerRoute$EMPTY_N || ifcs_0_innerReq$EMPTY_N) && + !state && + MUX_activeSource_0$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected = CAN_FIRE_RL_source_selected ; + + // rule RL_burst + assign CAN_FIRE_RL_burst = + ifcs_0_innerReq$EMPTY_N && ifcs_0_innerRoute$EMPTY_N && + state_047_AND_activeSource_0_120_121_AND_ifcs__ETC___d1123 ; + assign WILL_FIRE_RL_burst = CAN_FIRE_RL_burst ; + + // rule RL_source_selected_1 + assign CAN_FIRE_RL_source_selected_1 = + (!ifcs_1_innerRoute$EMPTY_N || ifcs_1_innerReq$EMPTY_N) && + !state && + MUX_activeSource_1$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_1 = CAN_FIRE_RL_source_selected_1 ; + + // rule RL_burst_1 + assign CAN_FIRE_RL_burst_1 = + ifcs_1_innerReq$EMPTY_N && ifcs_1_innerRoute$EMPTY_N && + state_047_AND_activeSource_1_164_165_AND_ifcs__ETC___d1167 ; + assign WILL_FIRE_RL_burst_1 = CAN_FIRE_RL_burst_1 ; + + // rule __me_check_129 + assign CAN_FIRE___me_check_129 = 1'b1 ; + assign WILL_FIRE___me_check_129 = 1'b1 ; + + // rule __me_check_131 + assign CAN_FIRE___me_check_131 = 1'b1 ; + assign WILL_FIRE___me_check_131 = 1'b1 ; + + // rule RL_sink_selected + assign CAN_FIRE_RL_sink_selected = + IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992 && + flitToSink_0$whas ; + assign WILL_FIRE_RL_sink_selected = CAN_FIRE_RL_sink_selected ; + + // rule RL_sink_selected_1 + assign CAN_FIRE_RL_sink_selected_1 = + IF_split_1_flitLeft_03_EQ_0_04_THEN_ssNoSynth__ETC___d993 && + flitToSink_1$whas ; + assign WILL_FIRE_RL_sink_selected_1 = CAN_FIRE_RL_sink_selected_1 ; + + // rule RL_sink_selected_2 + assign CAN_FIRE_RL_sink_selected_2 = + IF_split_2_flitLeft_32_EQ_0_33_THEN_ssNoSynth__ETC___d994 && + flitToSink_2$whas ; + assign WILL_FIRE_RL_sink_selected_2 = CAN_FIRE_RL_sink_selected_2 ; + + // rule __me_check_133 + assign CAN_FIRE___me_check_133 = 1'b1 ; + assign WILL_FIRE___me_check_133 = 1'b1 ; + + // rule RL_checkSinkReady_5 + assign CAN_FIRE_RL_checkSinkReady_5 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_5 = 1'd1 ; + + // rule RL_checkSinkReady_6 + assign CAN_FIRE_RL_checkSinkReady_6 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_6 = 1'd1 ; + + // rule RL_checkSinkReady_7 + assign CAN_FIRE_RL_checkSinkReady_7 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_7 = 1'd1 ; + + // rule RL_craftReq_5 + assign CAN_FIRE_RL_craftReq_5 = + ifcs_0_1_innerRoute$EMPTY_N && ifcs_0_1_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_5 = CAN_FIRE_RL_craftReq_5 ; + + // rule RL_craftReq_6 + assign CAN_FIRE_RL_craftReq_6 = + ifcs_1_1_innerRoute$EMPTY_N && ifcs_1_1_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_6 = CAN_FIRE_RL_craftReq_6 ; + + // rule RL_arbitrate_2 + assign CAN_FIRE_RL_arbitrate_2 = + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget || + CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) && + !state_1_1 ; + assign WILL_FIRE_RL_arbitrate_2 = CAN_FIRE_RL_arbitrate_2 ; + + // rule RL_source_selected_5 + assign CAN_FIRE_RL_source_selected_5 = + (!ifcs_0_1_innerRoute$EMPTY_N || ifcs_0_1_innerReq$EMPTY_N) && + !state_1_1 && + sourceSelect_1_0_1$whas ; + assign WILL_FIRE_RL_source_selected_5 = CAN_FIRE_RL_source_selected_5 ; + + // rule RL_burst_5 + assign CAN_FIRE_RL_burst_5 = + ifcs_0_1_innerReq$EMPTY_N && ifcs_0_1_innerRoute$EMPTY_N && + state_1_1_685_AND_activeSource_1_0_1_752_753_A_ETC___d1755 ; + assign WILL_FIRE_RL_burst_5 = CAN_FIRE_RL_burst_5 ; + + // rule RL_source_selected_6 + assign CAN_FIRE_RL_source_selected_6 = + (!ifcs_1_1_innerRoute$EMPTY_N || ifcs_1_1_innerReq$EMPTY_N) && + !state_1_1 && + sourceSelect_1_1_1$whas ; + assign WILL_FIRE_RL_source_selected_6 = CAN_FIRE_RL_source_selected_6 ; + + // rule RL_burst_6 + assign CAN_FIRE_RL_burst_6 = + ifcs_1_1_innerReq$EMPTY_N && ifcs_1_1_innerRoute$EMPTY_N && + state_1_1_685_AND_activeSource_1_1_1_792_793_A_ETC___d1795 ; + assign WILL_FIRE_RL_burst_6 = CAN_FIRE_RL_burst_6 ; + + // rule __me_check_176 + assign CAN_FIRE___me_check_176 = 1'b1 ; + assign WILL_FIRE___me_check_176 = 1'b1 ; + + // rule __me_check_178 + assign CAN_FIRE___me_check_178 = 1'b1 ; + assign WILL_FIRE___me_check_178 = 1'b1 ; + + // rule RL_sink_selected_5 + assign CAN_FIRE_RL_sink_selected_5 = + ssNoSynth_0_ar_buffer_ff$FULL_N && flitToSink_1_0_1$whas ; + assign WILL_FIRE_RL_sink_selected_5 = CAN_FIRE_RL_sink_selected_5 ; + + // rule RL_sink_selected_6 + assign CAN_FIRE_RL_sink_selected_6 = + ssNoSynth_1_ar_buffer_ff$FULL_N && flitToSink_1_1_1$whas ; + assign WILL_FIRE_RL_sink_selected_6 = CAN_FIRE_RL_sink_selected_6 ; + + // rule RL_sink_selected_7 + assign CAN_FIRE_RL_sink_selected_7 = + ssNoSynth_2_ar_buffer_ff$FULL_N && flitToSink_1_2$whas ; + assign WILL_FIRE_RL_sink_selected_7 = CAN_FIRE_RL_sink_selected_7 ; + + // rule __me_check_180 + assign CAN_FIRE___me_check_180 = 1'b1 ; + assign WILL_FIRE___me_check_180 = 1'b1 ; + + // rule RL_ssNoSynth_0_ar_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit = + !shim_arff$FULL_N || + ssNoSynth_0_ar_buffer_firstValid$Q_OUT && + (ssNoSynth_0_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_5) ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit ; + + // rule RL_ssNoSynth_0_ar_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit = + (ssNoSynth_0_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_5) && + shim_arff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit ; + + // rule RL_ssNoSynth_0_ar_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = + CAN_FIRE_RL_sink_selected_5 && + (!CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit || + ssNoSynth_0_ar_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; + + // rule RL_ssNoSynth_0_ar_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit && + ssNoSynth_0_ar_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; + + // rule RL_ssNoSynth_1_ar_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit = + ssNoSynth_1_ar_buffer_firstValid$Q_OUT && + (ssNoSynth_1_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_6) ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; + + // rule RL_ssNoSynth_1_ar_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit = + (ssNoSynth_1_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_6) && + near_mem_io$axi4_slave_arready ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + + // rule RL_ssNoSynth_1_ar_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = + CAN_FIRE_RL_sink_selected_6 && + (!CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit || + ssNoSynth_1_ar_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; + + // rule RL_ssNoSynth_1_ar_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit && + ssNoSynth_1_ar_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; + + // rule RL_ssNoSynth_2_ar_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit = + ssNoSynth_2_ar_buffer_firstValid$Q_OUT && + (ssNoSynth_2_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_7) ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; + + // rule RL_ssNoSynth_2_ar_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit = + (ssNoSynth_2_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_7) && + plic$axi4_slave_arready ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + + // rule RL_ssNoSynth_2_ar_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = + CAN_FIRE_RL_sink_selected_7 && + (!CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit || + ssNoSynth_2_ar_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; + + // rule RL_ssNoSynth_2_ar_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit && + ssNoSynth_2_ar_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; + + // rule RL_split_0_putFirst + assign CAN_FIRE_RL_split_0_putFirst = + split_0_doPut_whas__66_AND_split_0_doPut_wget__ETC___d673 && + split_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_0_putFirst = CAN_FIRE_RL_split_0_putFirst ; + + // rule RL_ssNoSynth_0_aw_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit = + !shim_awff$FULL_N || + ssNoSynth_0_aw_buffer_firstValid$Q_OUT && + (ssNoSynth_0_aw_buffer_ff$EMPTY_N || + MUX_split_0_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit ; + + // rule RL_ssNoSynth_0_aw_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit = + (ssNoSynth_0_aw_buffer_ff$EMPTY_N || + MUX_split_0_flitLeft$write_1__SEL_2) && + shim_awff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit ; + + // rule RL_ssNoSynth_0_aw_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = + MUX_split_0_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit || + ssNoSynth_0_aw_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; + + // rule RL_ssNoSynth_0_aw_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit && + ssNoSynth_0_aw_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; + + // rule RL_split_0_putOther + assign CAN_FIRE_RL_split_0_putOther = + CAN_FIRE_RL_sink_selected && + (!split_0_doPut$wget[171] || ssNoSynth_0_w_buffer_ff$FULL_N) && + split_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_0_putOther = CAN_FIRE_RL_split_0_putOther ; + + // rule RL_ssNoSynth_0_w_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit = + !shim_wff$FULL_N || + ssNoSynth_0_w_buffer_firstValid$Q_OUT && + (ssNoSynth_0_w_buffer_ff$EMPTY_N || + ssNoSynth_0_w_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit ; + + // rule RL_ssNoSynth_0_w_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_w_dropFlit = + (ssNoSynth_0_w_buffer_ff$EMPTY_N || + ssNoSynth_0_w_buffer_enqw$whas) && + shim_wff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_w_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_w_dropFlit ; + + // rule RL_ssNoSynth_0_w_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = + ssNoSynth_0_w_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_0_w_dropFlit || + ssNoSynth_0_w_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; + + // rule RL_ssNoSynth_0_w_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_w_dropFlit && + ssNoSynth_0_w_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; + + // rule RL_split_1_putFirst + assign CAN_FIRE_RL_split_1_putFirst = + split_1_doPut_whas__95_AND_split_1_doPut_wget__ETC___d702 && + split_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_1_putFirst = CAN_FIRE_RL_split_1_putFirst ; + + // rule RL_ssNoSynth_1_aw_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit = + ssNoSynth_1_aw_buffer_firstValid$Q_OUT && + (ssNoSynth_1_aw_buffer_ff$EMPTY_N || + MUX_split_1_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; + + // rule RL_ssNoSynth_1_aw_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit = + (ssNoSynth_1_aw_buffer_ff$EMPTY_N || + MUX_split_1_flitLeft$write_1__SEL_2) && + near_mem_io$axi4_slave_awready ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + + // rule RL_ssNoSynth_1_aw_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = + MUX_split_1_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit || + ssNoSynth_1_aw_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; + + // rule RL_ssNoSynth_1_aw_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit && + ssNoSynth_1_aw_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; + + // rule RL_split_1_putOther + assign CAN_FIRE_RL_split_1_putOther = + CAN_FIRE_RL_sink_selected_1 && + (!split_1_doPut$wget[171] || ssNoSynth_1_w_buffer_ff$FULL_N) && + split_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_1_putOther = CAN_FIRE_RL_split_1_putOther ; + + // rule RL_ssNoSynth_1_w_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit = + ssNoSynth_1_w_buffer_firstValid$Q_OUT && + (ssNoSynth_1_w_buffer_ff$EMPTY_N || + ssNoSynth_1_w_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; + + // rule RL_ssNoSynth_1_w_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_w_dropFlit = + (ssNoSynth_1_w_buffer_ff$EMPTY_N || + ssNoSynth_1_w_buffer_enqw$whas) && + near_mem_io$axi4_slave_wready ; + assign WILL_FIRE_RL_ssNoSynth_1_w_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + + // rule RL_ssNoSynth_1_w_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = + ssNoSynth_1_w_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_1_w_dropFlit || + ssNoSynth_1_w_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; + + // rule RL_ssNoSynth_1_w_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit && + ssNoSynth_1_w_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; + + // rule RL_split_2_putFirst + assign CAN_FIRE_RL_split_2_putFirst = + split_2_doPut_whas__24_AND_split_2_doPut_wget__ETC___d731 && + split_2_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_2_putFirst = CAN_FIRE_RL_split_2_putFirst ; + + // rule RL_ssNoSynth_2_aw_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit = + ssNoSynth_2_aw_buffer_firstValid$Q_OUT && + (ssNoSynth_2_aw_buffer_ff$EMPTY_N || + MUX_split_2_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; + + // rule RL_ssNoSynth_2_aw_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit = + (ssNoSynth_2_aw_buffer_ff$EMPTY_N || + MUX_split_2_flitLeft$write_1__SEL_2) && + plic$axi4_slave_awready ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + + // rule RL_ssNoSynth_2_aw_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = + MUX_split_2_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit || + ssNoSynth_2_aw_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; + + // rule RL_ssNoSynth_2_aw_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit && + ssNoSynth_2_aw_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; + + // rule RL_split_2_putOther + assign CAN_FIRE_RL_split_2_putOther = + CAN_FIRE_RL_sink_selected_2 && + (!split_2_doPut$wget[171] || ssNoSynth_2_w_buffer_ff$FULL_N) && + split_2_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_2_putOther = CAN_FIRE_RL_split_2_putOther ; + + // rule RL_ssNoSynth_2_w_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit = + ssNoSynth_2_w_buffer_firstValid$Q_OUT && + (ssNoSynth_2_w_buffer_ff$EMPTY_N || + ssNoSynth_2_w_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; + + // rule RL_ssNoSynth_2_w_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_w_dropFlit = + (ssNoSynth_2_w_buffer_ff$EMPTY_N || + ssNoSynth_2_w_buffer_enqw$whas) && + plic$axi4_slave_wready ; + assign WILL_FIRE_RL_ssNoSynth_2_w_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + + // rule RL_ssNoSynth_2_w_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = + ssNoSynth_2_w_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_2_w_dropFlit || + ssNoSynth_2_w_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; + + // rule RL_ssNoSynth_2_w_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit && + ssNoSynth_2_w_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; + + // rule RL_ifcs_0_firstFlit + assign CAN_FIRE_RL_ifcs_0_firstFlit = + cpu$dmem_master_wvalid && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 && + ifcs_0_innerReq$FULL_N && + ifcs_0_innerRoute$FULL_N && + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d760 || + cpu$dmem_master_awvalid) && + ifcs_0_state == 2'd0 && + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d783 + + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d787 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_firstFlit = CAN_FIRE_RL_ifcs_0_firstFlit ; + + // rule RL_ifcs_0_followFlits + assign CAN_FIRE_RL_ifcs_0_followFlits = + cpu$dmem_master_wvalid && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 && + ifcs_0_innerReq$FULL_N && + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d760 || + cpu$dmem_master_awvalid) && + ifcs_0_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_followFlits = CAN_FIRE_RL_ifcs_0_followFlits ; + + // rule RL_ifcs_0_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_0_nonRoutableFlit = + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d821 && + ifcs_0_state == 2'd0 && + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d783 + + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d787 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_nonRoutableFlit = + CAN_FIRE_RL_ifcs_0_nonRoutableFlit ; + + // rule RL_ifcs_0_drainFlits + assign CAN_FIRE_RL_ifcs_0_drainFlits = + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 && + cpu$dmem_master_wvalid && + ifcs_0_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_0_drainFlits = CAN_FIRE_RL_ifcs_0_drainFlits ; + + // rule __me_check_105 + assign CAN_FIRE___me_check_105 = 1'b1 ; + assign WILL_FIRE___me_check_105 = 1'b1 ; + + // rule RL_ifcs_0_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_drainNoRouteResponse = + msNoSynth_0_b_buffer_ff$FULL_N && ifcs_0_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + + // rule RL_checkSinkReady_3 + assign CAN_FIRE_RL_checkSinkReady_3 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_3 = 1'd1 ; + + // rule RL_ifcs_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_drainNoRouteResponse = + msNoSynth_1_b_buffer_ff$FULL_N && ifcs_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + + // rule RL_checkSinkReady_4 + assign CAN_FIRE_RL_checkSinkReady_4 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_4 = 1'd1 ; + + // rule RL_craftReq_2 + assign CAN_FIRE_RL_craftReq_2 = + ifcs_0_routeBack$EMPTY_N && ifcs_0_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_2 = CAN_FIRE_RL_craftReq_2 ; + + // rule RL_craftReq_3 + assign CAN_FIRE_RL_craftReq_3 = + ifcs_1_routeBack$EMPTY_N && ifcs_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_3 = CAN_FIRE_RL_craftReq_3 ; + + // rule RL_craftReq_4 + assign CAN_FIRE_RL_craftReq_4 = + ifcs_2_routeBack$EMPTY_N && ifcs_2_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_4 = CAN_FIRE_RL_craftReq_4 ; + + // rule RL_arbitrate_1 + assign CAN_FIRE_RL_arbitrate_1 = + reqWires_1_0_whas__226_AND_reqWires_1_0_wget___ETC___d1236 && + !state_1 ; + assign WILL_FIRE_RL_arbitrate_1 = CAN_FIRE_RL_arbitrate_1 ; + + // rule RL_source_selected_2 + assign CAN_FIRE_RL_source_selected_2 = + (!ifcs_0_routeBack$EMPTY_N || ifcs_0_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_0$whas ; + assign WILL_FIRE_RL_source_selected_2 = CAN_FIRE_RL_source_selected_2 ; + + // rule RL_burst_2 + assign CAN_FIRE_RL_burst_2 = + ifcs_0_rspBack$EMPTY_N && ifcs_0_routeBack$EMPTY_N && + state_1_237_AND_activeSource_1_0_325_326_AND_i_ETC___d1328 ; + assign WILL_FIRE_RL_burst_2 = CAN_FIRE_RL_burst_2 ; + + // rule RL_source_selected_3 + assign CAN_FIRE_RL_source_selected_3 = + (!ifcs_1_routeBack$EMPTY_N || ifcs_1_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_1$whas ; + assign WILL_FIRE_RL_source_selected_3 = CAN_FIRE_RL_source_selected_3 ; + + // rule RL_burst_3 + assign CAN_FIRE_RL_burst_3 = + ifcs_1_rspBack$EMPTY_N && ifcs_1_routeBack$EMPTY_N && + state_1_237_AND_activeSource_1_1_358_359_AND_i_ETC___d1361 ; + assign WILL_FIRE_RL_burst_3 = CAN_FIRE_RL_burst_3 ; + + // rule __me_check_144 + assign CAN_FIRE___me_check_144 = 1'b1 ; + assign WILL_FIRE___me_check_144 = 1'b1 ; + + // rule RL_source_selected_4 + assign CAN_FIRE_RL_source_selected_4 = + (!ifcs_2_routeBack$EMPTY_N || ifcs_2_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_2$whas ; + assign WILL_FIRE_RL_source_selected_4 = CAN_FIRE_RL_source_selected_4 ; + + // rule RL_burst_4 + assign CAN_FIRE_RL_burst_4 = + ifcs_2_rspBack$EMPTY_N && ifcs_2_routeBack$EMPTY_N && + state_1_237_AND_activeSource_1_2_392_393_AND_i_ETC___d1395 ; + assign WILL_FIRE_RL_burst_4 = CAN_FIRE_RL_burst_4 ; + + // rule __me_check_142 + assign CAN_FIRE___me_check_142 = 1'b1 ; + assign WILL_FIRE___me_check_142 = 1'b1 ; + + // rule __me_check_146 + assign CAN_FIRE___me_check_146 = 1'b1 ; + assign WILL_FIRE___me_check_146 = 1'b1 ; + + // rule RL_sink_selected_3 + assign CAN_FIRE_RL_sink_selected_3 = + !CAN_FIRE_RL_ifcs_0_drainNoRouteResponse && flitToSink_1_0$whas ; + assign WILL_FIRE_RL_sink_selected_3 = CAN_FIRE_RL_sink_selected_3 ; + + // rule RL_sink_selected_4 + assign CAN_FIRE_RL_sink_selected_4 = + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse && flitToSink_1_1$whas ; + assign WILL_FIRE_RL_sink_selected_4 = CAN_FIRE_RL_sink_selected_4 ; + + // rule __me_check_148 + assign CAN_FIRE___me_check_148 = 1'b1 ; + assign WILL_FIRE___me_check_148 = 1'b1 ; + + // rule RL_ifcs_0_forwardRsp + assign CAN_FIRE_RL_ifcs_0_forwardRsp = + msNoSynth_0_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_3 && + !ifcs_0_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_forwardRsp = CAN_FIRE_RL_ifcs_0_forwardRsp ; + + // rule RL_msNoSynth_0_b_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_b_forwardFlit = + msNoSynth_0_b_buffer_firstValid$Q_OUT && + (msNoSynth_0_b_buffer_ff$EMPTY_N || + msNoSynth_0_b_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_0_b_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_b_forwardFlit ; + + // rule RL_msNoSynth_0_b_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_b_dropFlit = + (msNoSynth_0_b_buffer_ff$EMPTY_N || + msNoSynth_0_b_buffer_enqw$whas) && + cpu$dmem_master_bready ; + assign WILL_FIRE_RL_msNoSynth_0_b_dropFlit = + CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; + + // rule RL_msNoSynth_0_b_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue = + msNoSynth_0_b_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_0_b_dropFlit || + msNoSynth_0_b_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; + + // rule RL_msNoSynth_0_b_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_b_dropFlit && + msNoSynth_0_b_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; + + // rule RL_ifcs_0_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp = + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 && + ifcs_0_noRoute_inner_pendingReq$port1__read && + ifcs_0_noRouteRsp$FULL_N && + cpu$dmem_master_wvalid ; + assign WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; + + // rule __me_check_103 + assign CAN_FIRE___me_check_103 = 1'b1 ; + assign WILL_FIRE___me_check_103 = 1'b1 ; + + // rule __me_check_104 + assign CAN_FIRE___me_check_104 = 1'b1 ; + assign WILL_FIRE___me_check_104 = 1'b1 ; + + // rule __me_check_107 + assign CAN_FIRE___me_check_107 = 1'b1 ; + assign WILL_FIRE___me_check_107 = 1'b1 ; + + // rule RL_merged_0_genFirst + assign CAN_FIRE_RL_merged_0_genFirst = + cpu$dmem_master_awvalid && cpu$dmem_master_wvalid && + merged_0_doDrop$whas && + merged_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_0_genFirst = CAN_FIRE_RL_merged_0_genFirst ; + + // rule RL_msNoSynth_0_aw_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; + + // rule RL_merged_0_genOther + assign CAN_FIRE_RL_merged_0_genOther = + cpu$dmem_master_wvalid && merged_0_doDrop$whas && + merged_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_0_genOther = CAN_FIRE_RL_merged_0_genOther ; + + // rule RL_msNoSynth_0_w_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_forwardRsp + assign CAN_FIRE_RL_ifcs_1_forwardRsp = + msNoSynth_1_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_4 && + !ifcs_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_forwardRsp = CAN_FIRE_RL_ifcs_1_forwardRsp ; + + // rule RL_msNoSynth_1_b_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_b_forwardFlit = + msNoSynth_1_b_buffer_firstValid$Q_OUT && + (msNoSynth_1_b_buffer_ff$EMPTY_N || + msNoSynth_1_b_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_1_b_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; + + // rule RL_msNoSynth_1_b_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_b_dropFlit = + (msNoSynth_1_b_buffer_ff$EMPTY_N || + msNoSynth_1_b_buffer_enqw$whas) && + dm_mem_tap$master_bready ; + assign WILL_FIRE_RL_msNoSynth_1_b_dropFlit = + CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; + + // rule RL_connect_bflit + assign CAN_FIRE_RL_connect_bflit = dm_mem_tap$slave_bvalid ; + assign WILL_FIRE_RL_connect_bflit = dm_mem_tap$slave_bvalid ; + + // rule RL_connect_bready + assign CAN_FIRE_RL_connect_bready = 1'd1 ; + assign WILL_FIRE_RL_connect_bready = 1'd1 ; + + // rule RL_msNoSynth_1_b_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue = + msNoSynth_1_b_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_1_b_dropFlit || + msNoSynth_1_b_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; + + // rule RL_msNoSynth_1_b_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_b_dropFlit && + msNoSynth_1_b_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; + + // rule RL_ifcs_0_firstFlit_1 + assign CAN_FIRE_RL_ifcs_0_firstFlit_1 = + shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && + ifcs_0_routeBack$FULL_N && + !ifcs_0_state_1 ; + assign WILL_FIRE_RL_ifcs_0_firstFlit_1 = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; + + // rule RL_ifcs_0_followFlits_1 + assign CAN_FIRE_RL_ifcs_0_followFlits_1 = + shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && ifcs_0_state_1 ; + assign WILL_FIRE_RL_ifcs_0_followFlits_1 = + CAN_FIRE_RL_ifcs_0_followFlits_1 ; + + // rule __me_check_117 + assign CAN_FIRE___me_check_117 = 1'b1 ; + assign WILL_FIRE___me_check_117 = 1'b1 ; + + // rule RL_ssNoSynth_0_b_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_firstFlit_1 + assign CAN_FIRE_RL_ifcs_1_firstFlit_1 = + near_mem_io$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ifcs_1_routeBack$FULL_N && + !ifcs_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_firstFlit_1 = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; + + // rule RL_ifcs_1_followFlits_1 + assign CAN_FIRE_RL_ifcs_1_followFlits_1 = + near_mem_io$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ifcs_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_followFlits_1 = + CAN_FIRE_RL_ifcs_1_followFlits_1 ; + + // rule __me_check_119 + assign CAN_FIRE___me_check_119 = 1'b1 ; + assign WILL_FIRE___me_check_119 = 1'b1 ; + + // rule RL_ssNoSynth_1_b_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; + + // rule RL_ifcs_0_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + msNoSynth_0_r_buffer_ff$FULL_N && ifcs_0_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + + // rule RL_checkSinkReady_8 + assign CAN_FIRE_RL_checkSinkReady_8 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_8 = 1'd1 ; + + // rule RL_ifcs_1_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + msNoSynth_1_r_buffer_ff$FULL_N && ifcs_1_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + + // rule RL_checkSinkReady_9 + assign CAN_FIRE_RL_checkSinkReady_9 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_9 = 1'd1 ; + + // rule RL_craftReq_7 + assign CAN_FIRE_RL_craftReq_7 = + ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_7 = CAN_FIRE_RL_craftReq_7 ; + + // rule RL_craftReq_8 + assign CAN_FIRE_RL_craftReq_8 = + ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_8 = CAN_FIRE_RL_craftReq_8 ; + + // rule RL_craftReq_9 + assign CAN_FIRE_RL_craftReq_9 = + ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_9 = CAN_FIRE_RL_craftReq_9 ; + + // rule RL_arbitrate_3 + assign CAN_FIRE_RL_arbitrate_3 = + reqWires_1_1_0_whas__854_AND_reqWires_1_1_0_wg_ETC___d1864 && + !state_1_1_1 ; + assign WILL_FIRE_RL_arbitrate_3 = CAN_FIRE_RL_arbitrate_3 ; + + // rule RL_source_selected_7 + assign CAN_FIRE_RL_source_selected_7 = + (!ifcs_0_1_routeBack$EMPTY_N || ifcs_0_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_0$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_7 = CAN_FIRE_RL_source_selected_7 ; + + // rule RL_burst_7 + assign CAN_FIRE_RL_burst_7 = + ifcs_0_1_rspBack$EMPTY_N && ifcs_0_1_routeBack$EMPTY_N && + state_1_1_1_865_AND_activeSource_1_1_0_959_960_ETC___d1962 ; + assign WILL_FIRE_RL_burst_7 = CAN_FIRE_RL_burst_7 ; + + // rule RL_source_selected_8 + assign CAN_FIRE_RL_source_selected_8 = + (!ifcs_1_1_routeBack$EMPTY_N || ifcs_1_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_1_1$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_8 = CAN_FIRE_RL_source_selected_8 ; + + // rule RL_burst_8 + assign CAN_FIRE_RL_burst_8 = + ifcs_1_1_rspBack$EMPTY_N && ifcs_1_1_routeBack$EMPTY_N && + state_1_1_1_865_AND_activeSource_1_1_1_1_995_9_ETC___d1998 ; + assign WILL_FIRE_RL_burst_8 = CAN_FIRE_RL_burst_8 ; + + // rule __me_check_191 + assign CAN_FIRE___me_check_191 = 1'b1 ; + assign WILL_FIRE___me_check_191 = 1'b1 ; + + // rule RL_source_selected_9 + assign CAN_FIRE_RL_source_selected_9 = + (!ifcs_2_1_routeBack$EMPTY_N || ifcs_2_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_2$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_9 = CAN_FIRE_RL_source_selected_9 ; + + // rule RL_burst_9 + assign CAN_FIRE_RL_burst_9 = + ifcs_2_1_rspBack$EMPTY_N && ifcs_2_1_routeBack$EMPTY_N && + state_1_1_1_865_AND_activeSource_1_1_2_031_032_ETC___d2034 ; + assign WILL_FIRE_RL_burst_9 = CAN_FIRE_RL_burst_9 ; + + // rule __me_check_189 + assign CAN_FIRE___me_check_189 = 1'b1 ; + assign WILL_FIRE___me_check_189 = 1'b1 ; + + // rule __me_check_193 + assign CAN_FIRE___me_check_193 = 1'b1 ; + assign WILL_FIRE___me_check_193 = 1'b1 ; + + // rule RL_sink_selected_8 + assign CAN_FIRE_RL_sink_selected_8 = + !CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse && + flitToSink_1_1_0$whas ; + assign WILL_FIRE_RL_sink_selected_8 = CAN_FIRE_RL_sink_selected_8 ; + + // rule RL_sink_selected_9 + assign CAN_FIRE_RL_sink_selected_9 = + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse && + flitToSink_1_1_1_1$whas ; + assign WILL_FIRE_RL_sink_selected_9 = CAN_FIRE_RL_sink_selected_9 ; + + // rule __me_check_195 + assign CAN_FIRE___me_check_195 = 1'b1 ; + assign WILL_FIRE___me_check_195 = 1'b1 ; + + // rule RL_ifcs_0_1_forwardRsp + assign CAN_FIRE_RL_ifcs_0_1_forwardRsp = + msNoSynth_0_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_8 && + !ifcs_0_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_1_forwardRsp = CAN_FIRE_RL_ifcs_0_1_forwardRsp ; + + // rule RL_msNoSynth_0_r_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_r_forwardFlit = + msNoSynth_0_r_buffer_firstValid$Q_OUT && + (msNoSynth_0_r_buffer_ff$EMPTY_N || + msNoSynth_0_r_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_0_r_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_r_forwardFlit ; + + // rule RL_msNoSynth_0_r_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_r_dropFlit = + (msNoSynth_0_r_buffer_ff$EMPTY_N || + msNoSynth_0_r_buffer_enqw$whas) && + cpu$dmem_master_rready ; + assign WILL_FIRE_RL_msNoSynth_0_r_dropFlit = + CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; // rule RL_rl_relay_sw_interrupts assign CAN_FIRE_RL_rl_relay_sw_interrupts = @@ -2968,17 +5358,15 @@ module mkCore(CLK, // rule RL_rl_cpu_hart0_reset_from_soc_start assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = near_mem_io$RDY_server_reset_request_put && - plic$RDY_server_reset_request_put && - fabric_2x3_RDY_reset_AND_cpu_RDY_hart0_server__ETC___d9 ; + plic_RDY_server_reset_request_put_AND_cpu_RDY__ETC___d8 ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; // rule RL_rl_cpu_hart0_reset_from_dm_start assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = + debug_module$RDY_hart0_reset_client_request_get && near_mem_io$RDY_server_reset_request_put && plic$RDY_server_reset_request_put && - fabric_2x3$RDY_reset && - debug_module$RDY_hart0_reset_client_request_get && cpu$RDY_hart0_server_reset_request_put && f_reset_requestor$FULL_N ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = @@ -2997,50 +5385,1430 @@ module mkCore(CLK, assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // submodule cpu - assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; - assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; - assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; - assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; - assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; - assign cpu$hart0_csr_mem_server_request_put = - dm_csr_tap$client_request_get ; - assign cpu$hart0_gpr_mem_server_request_put = - dm_gpr_tap_ifc$client_request_get ; - assign cpu$hart0_put_other_req_put = debug_module$hart0_get_other_req_get ; - assign cpu$hart0_server_reset_request_put = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ? - f_reset_reqs$D_OUT : - debug_module$hart0_reset_client_request_get ; - assign cpu$hart0_server_run_halt_request_put = - debug_module$hart0_client_run_halt_request_get ; - assign cpu$imem_master_arready = cpu_imem_master_arready ; - assign cpu$imem_master_awready = cpu_imem_master_awready ; - assign cpu$imem_master_bid = cpu_imem_master_bid ; - assign cpu$imem_master_bresp = cpu_imem_master_bresp ; - assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; - assign cpu$imem_master_rdata = cpu_imem_master_rdata ; - assign cpu$imem_master_rid = cpu_imem_master_rid ; - assign cpu$imem_master_rlast = cpu_imem_master_rlast ; - assign cpu$imem_master_rresp = cpu_imem_master_rresp ; - assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; - assign cpu$imem_master_wready = cpu_imem_master_wready ; - assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; - assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; - assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; - assign cpu$software_interrupt_req_set_not_clear = + // rule RL_msNoSynth_0_r_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue = + msNoSynth_0_r_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_0_r_dropFlit || + msNoSynth_0_r_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; + + // rule RL_msNoSynth_0_r_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_r_dropFlit && + msNoSynth_0_r_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; + + // rule RL_ifcs_2_firstFlit + assign CAN_FIRE_RL_ifcs_2_firstFlit = + plic$axi4_slave_bvalid && ifcs_2_rspBack$FULL_N && + ifcs_2_routeBack$FULL_N && + !ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_firstFlit = CAN_FIRE_RL_ifcs_2_firstFlit ; + + // rule RL_ifcs_2_followFlits + assign CAN_FIRE_RL_ifcs_2_followFlits = + plic$axi4_slave_bvalid && ifcs_2_rspBack$FULL_N && ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_followFlits = CAN_FIRE_RL_ifcs_2_followFlits ; + + // rule __me_check_121 + assign CAN_FIRE___me_check_121 = 1'b1 ; + assign WILL_FIRE___me_check_121 = 1'b1 ; + + // rule RL_ssNoSynth_2_b_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; + + // rule RL_ifcs_0_1_firstFlit + assign CAN_FIRE_RL_ifcs_0_1_firstFlit = + cpu$dmem_master_arvalid && ifcs_0_1_innerReq$FULL_N && + ifcs_0_1_innerRoute$FULL_N && + ifcs_0_1_state == 2'd0 && + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1424 + + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1428 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_1_firstFlit = CAN_FIRE_RL_ifcs_0_1_firstFlit ; + + // rule RL_ifcs_0_1_followFlits + assign CAN_FIRE_RL_ifcs_0_1_followFlits = + cpu$dmem_master_arvalid && ifcs_0_1_innerReq$FULL_N && + ifcs_0_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_1_followFlits = + CAN_FIRE_RL_ifcs_0_1_followFlits ; + + // rule RL_ifcs_0_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit = + ifcs_0_1_noRoute_flitCount == 9'd0 && cpu$dmem_master_arvalid && + ifcs_0_1_state == 2'd0 && + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1424 + + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1428 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ; + + // rule RL_ifcs_0_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + x_port1__read__h55959 != 9'd0 && ifcs_0_1_noRouteRsp$FULL_N && + (x_port1__read__h55959 != 9'd1 || cpu$dmem_master_arvalid) ; + assign WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; + + // rule RL_ifcs_0_1_drainFlits + assign CAN_FIRE_RL_ifcs_0_1_drainFlits = + cpu$dmem_master_arvalid && ifcs_0_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_0_1_drainFlits = CAN_FIRE_RL_ifcs_0_1_drainFlits ; + + // rule __me_check_150 + assign CAN_FIRE___me_check_150 = 1'b1 ; + assign WILL_FIRE___me_check_150 = 1'b1 ; + + // rule __me_check_151 + assign CAN_FIRE___me_check_151 = 1'b1 ; + assign WILL_FIRE___me_check_151 = 1'b1 ; + + // rule __me_check_152 + assign CAN_FIRE___me_check_152 = 1'b1 ; + assign WILL_FIRE___me_check_152 = 1'b1 ; + + // rule __me_check_154 + assign CAN_FIRE___me_check_154 = 1'b1 ; + assign WILL_FIRE___me_check_154 = 1'b1 ; + + // rule RL_msNoSynth_0_ar_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_1_forwardRsp + assign CAN_FIRE_RL_ifcs_1_1_forwardRsp = + msNoSynth_1_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_9 && + !ifcs_1_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_1_forwardRsp = CAN_FIRE_RL_ifcs_1_1_forwardRsp ; + + // rule RL_msNoSynth_1_r_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_r_forwardFlit = + msNoSynth_1_r_buffer_firstValid$Q_OUT && + (msNoSynth_1_r_buffer_ff$EMPTY_N || + msNoSynth_1_r_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_1_r_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; + + // rule RL_msNoSynth_1_r_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_r_dropFlit = + (msNoSynth_1_r_buffer_ff$EMPTY_N || + msNoSynth_1_r_buffer_enqw$whas) && + dm_mem_tap$master_rready ; + assign WILL_FIRE_RL_msNoSynth_1_r_dropFlit = + CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; + + // rule RL_connect_rflit + assign CAN_FIRE_RL_connect_rflit = dm_mem_tap$slave_rvalid ; + assign WILL_FIRE_RL_connect_rflit = dm_mem_tap$slave_rvalid ; + + // rule RL_connect_rready + assign CAN_FIRE_RL_connect_rready = 1'd1 ; + assign WILL_FIRE_RL_connect_rready = 1'd1 ; + + // rule RL_connect_awflit + assign CAN_FIRE_RL_connect_awflit = debug_module$master_awvalid ; + assign WILL_FIRE_RL_connect_awflit = debug_module$master_awvalid ; + + // rule RL_connect_awready + assign CAN_FIRE_RL_connect_awready = 1'd1 ; + assign WILL_FIRE_RL_connect_awready = 1'd1 ; + + // rule RL_connect_wflit + assign CAN_FIRE_RL_connect_wflit = debug_module$master_wvalid ; + assign WILL_FIRE_RL_connect_wflit = debug_module$master_wvalid ; + + // rule RL_connect_wready + assign CAN_FIRE_RL_connect_wready = 1'd1 ; + assign WILL_FIRE_RL_connect_wready = 1'd1 ; + + // rule RL_connect_arflit + assign CAN_FIRE_RL_connect_arflit = debug_module$master_arvalid ; + assign WILL_FIRE_RL_connect_arflit = debug_module$master_arvalid ; + + // rule RL_connect_arready + assign CAN_FIRE_RL_connect_arready = 1'd1 ; + assign WILL_FIRE_RL_connect_arready = 1'd1 ; + + // rule RL_msNoSynth_1_r_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue = + msNoSynth_1_r_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_1_r_dropFlit || + msNoSynth_1_r_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; + + // rule RL_msNoSynth_1_r_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_r_dropFlit && + msNoSynth_1_r_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; + + // rule RL_ifcs_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_firstFlit = + dm_mem_tap$master_wvalid && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 && + ifcs_1_innerReq$FULL_N && + ifcs_1_innerRoute$FULL_N && + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d857 || + dm_mem_tap$master_awvalid) && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d880 + + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d884 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_firstFlit = CAN_FIRE_RL_ifcs_1_firstFlit ; + + // rule RL_ifcs_1_followFlits + assign CAN_FIRE_RL_ifcs_1_followFlits = + dm_mem_tap$master_wvalid && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 && + ifcs_1_innerReq$FULL_N && + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d857 || + dm_mem_tap$master_awvalid) && + ifcs_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_followFlits = CAN_FIRE_RL_ifcs_1_followFlits ; + + // rule RL_ifcs_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_nonRoutableFlit = + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d918 && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d880 + + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d884 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_nonRoutableFlit ; + + // rule RL_ifcs_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp = + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 && + ifcs_1_noRoute_inner_pendingReq$port1__read && + ifcs_1_noRouteRsp$FULL_N && + dm_mem_tap$master_wvalid ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; + + // rule RL_ifcs_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_drainFlits = + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 && + dm_mem_tap$master_wvalid && + ifcs_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_drainFlits = CAN_FIRE_RL_ifcs_1_drainFlits ; + + // rule __me_check_110 + assign CAN_FIRE___me_check_110 = 1'b1 ; + assign WILL_FIRE___me_check_110 = 1'b1 ; + + // rule __me_check_111 + assign CAN_FIRE___me_check_111 = 1'b1 ; + assign WILL_FIRE___me_check_111 = 1'b1 ; + + // rule __me_check_112 + assign CAN_FIRE___me_check_112 = 1'b1 ; + assign WILL_FIRE___me_check_112 = 1'b1 ; + + // rule __me_check_114 + assign CAN_FIRE___me_check_114 = 1'b1 ; + assign WILL_FIRE___me_check_114 = 1'b1 ; + + // rule RL_merged_1_genFirst + assign CAN_FIRE_RL_merged_1_genFirst = + dm_mem_tap$master_awvalid && dm_mem_tap$master_wvalid && + merged_1_doDrop$whas && + merged_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_1_genFirst = CAN_FIRE_RL_merged_1_genFirst ; + + // rule RL_msNoSynth_1_aw_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; + + // rule RL_merged_1_genOther + assign CAN_FIRE_RL_merged_1_genOther = + dm_mem_tap$master_wvalid && merged_1_doDrop$whas && + merged_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_1_genOther = CAN_FIRE_RL_merged_1_genOther ; + + // rule RL_msNoSynth_1_w_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_1_firstFlit = + dm_mem_tap$master_arvalid && ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_innerRoute$FULL_N && + ifcs_1_1_state == 2'd0 && + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1510 + + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1514 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_firstFlit = CAN_FIRE_RL_ifcs_1_1_firstFlit ; + + // rule RL_ifcs_1_1_followFlits + assign CAN_FIRE_RL_ifcs_1_1_followFlits = + dm_mem_tap$master_arvalid && ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_followFlits = + CAN_FIRE_RL_ifcs_1_1_followFlits ; + + // rule RL_ifcs_1_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit = + ifcs_1_1_noRoute_flitCount == 9'd0 && + dm_mem_tap$master_arvalid && + ifcs_1_1_state == 2'd0 && + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1510 + + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1514 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ; + + // rule RL_ifcs_1_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + x_port1__read__h58381 != 9'd0 && ifcs_1_1_noRouteRsp$FULL_N && + (x_port1__read__h58381 != 9'd1 || dm_mem_tap$master_arvalid) ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; + + // rule RL_ifcs_1_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_1_drainFlits = + dm_mem_tap$master_arvalid && ifcs_1_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_1_drainFlits = CAN_FIRE_RL_ifcs_1_1_drainFlits ; + + // rule __me_check_157 + assign CAN_FIRE___me_check_157 = 1'b1 ; + assign WILL_FIRE___me_check_157 = 1'b1 ; + + // rule __me_check_158 + assign CAN_FIRE___me_check_158 = 1'b1 ; + assign WILL_FIRE___me_check_158 = 1'b1 ; + + // rule __me_check_159 + assign CAN_FIRE___me_check_159 = 1'b1 ; + assign WILL_FIRE___me_check_159 = 1'b1 ; + + // rule __me_check_161 + assign CAN_FIRE___me_check_161 = 1'b1 ; + assign WILL_FIRE___me_check_161 = 1'b1 ; + + // rule RL_msNoSynth_1_ar_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; + + // rule RL_ifcs_0_1_firstFlit_1 + assign CAN_FIRE_RL_ifcs_0_1_firstFlit_1 = + shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && + ifcs_0_1_routeBack$FULL_N && + !ifcs_0_1_state_1 ; + assign WILL_FIRE_RL_ifcs_0_1_firstFlit_1 = + CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; + + // rule RL_ifcs_0_1_followFlits_1 + assign CAN_FIRE_RL_ifcs_0_1_followFlits_1 = + shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && ifcs_0_1_state_1 ; + assign WILL_FIRE_RL_ifcs_0_1_followFlits_1 = + CAN_FIRE_RL_ifcs_0_1_followFlits_1 ; + + // rule __me_check_164 + assign CAN_FIRE___me_check_164 = 1'b1 ; + assign WILL_FIRE___me_check_164 = 1'b1 ; + + // rule RL_ssNoSynth_0_r_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_1_firstFlit_1 + assign CAN_FIRE_RL_ifcs_1_1_firstFlit_1 = + near_mem_io$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ifcs_1_1_routeBack$FULL_N && + !ifcs_1_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_1_firstFlit_1 = + CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; + + // rule RL_ifcs_1_1_followFlits_1 + assign CAN_FIRE_RL_ifcs_1_1_followFlits_1 = + near_mem_io$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ifcs_1_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_1_followFlits_1 = + CAN_FIRE_RL_ifcs_1_1_followFlits_1 ; + + // rule __me_check_166 + assign CAN_FIRE___me_check_166 = 1'b1 ; + assign WILL_FIRE___me_check_166 = 1'b1 ; + + // rule RL_ssNoSynth_1_r_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; + + // rule RL_ifcs_2_1_firstFlit + assign CAN_FIRE_RL_ifcs_2_1_firstFlit = + plic$axi4_slave_rvalid && ifcs_2_1_rspBack$FULL_N && + ifcs_2_1_routeBack$FULL_N && + !ifcs_2_1_state ; + assign WILL_FIRE_RL_ifcs_2_1_firstFlit = CAN_FIRE_RL_ifcs_2_1_firstFlit ; + + // rule RL_ifcs_2_1_followFlits + assign CAN_FIRE_RL_ifcs_2_1_followFlits = + plic$axi4_slave_rvalid && ifcs_2_1_rspBack$FULL_N && + ifcs_2_1_state ; + assign WILL_FIRE_RL_ifcs_2_1_followFlits = + CAN_FIRE_RL_ifcs_2_1_followFlits ; + + // rule __me_check_168 + assign CAN_FIRE___me_check_168 = 1'b1 ; + assign WILL_FIRE___me_check_168 = 1'b1 ; + + // rule RL_ssNoSynth_2_r_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; + + // inputs to muxes for submodule ports + assign MUX_activeSource_0$write_1__SEL_1 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[0] ; + assign MUX_activeSource_1_1_0$write_1__SEL_1 = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[0] ; + assign MUX_activeSource_1_1_0$write_1__SEL_2 = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[0] ; + assign MUX_activeSource_1_1_0$write_1__SEL_3 = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[0] ; + assign MUX_flitToSink_0$wset_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_0$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1_0$wset_1__SEL_1 = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_2 = + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_3 = + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_1_0_1$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_1_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_2 = + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_3 = + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_1 = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_2 = + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_3 = + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1_1_1$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_2 = + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_3 = + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_2$wset_1__SEL_1 = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[2] ; + assign MUX_flitToSink_1_2$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[2] ; + assign MUX_flitToSink_2$wset_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[2] ; + assign MUX_flitToSink_2$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[2] ; + assign MUX_ifcs_0_1_state_1$write_1__SEL_1 = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 && shim_rff$D_OUT[0] ; + assign MUX_ifcs_0_state$write_1__PSEL_1 = + WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits ; + assign MUX_ifcs_0_state$write_1__SEL_1 = + MUX_ifcs_0_state$write_1__PSEL_1 && cpu$dmem_master_wlast ; + assign MUX_ifcs_0_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_0_firstFlit && !cpu$dmem_master_wlast ; + assign MUX_ifcs_0_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !cpu$dmem_master_wlast ; + assign MUX_ifcs_1_1_state_1$write_1__SEL_1 = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && + near_mem_io$axi4_slave_rlast ; + assign MUX_ifcs_1_state$write_1__PSEL_1 = + WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits ; + assign MUX_ifcs_1_state$write_1__SEL_1 = + MUX_ifcs_1_state$write_1__PSEL_1 && dm_mem_tap$master_wlast ; + assign MUX_ifcs_1_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_1_firstFlit && !dm_mem_tap$master_wlast ; + assign MUX_ifcs_1_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && + !dm_mem_tap$master_wlast ; + assign MUX_ifcs_2_1_state$write_1__SEL_1 = + WILL_FIRE_RL_ifcs_2_1_followFlits && plic$axi4_slave_rlast ; + assign MUX_split_0_flitLeft$write_1__SEL_1 = + WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] ; + assign MUX_split_0_flitLeft$write_1__SEL_2 = + WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[171] ; + assign MUX_split_1_flitLeft$write_1__SEL_1 = + WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] ; + assign MUX_split_1_flitLeft$write_1__SEL_2 = + WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[171] ; + assign MUX_split_2_flitLeft$write_1__SEL_1 = + WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] ; + assign MUX_split_2_flitLeft$write_1__SEL_2 = + WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[171] ; + assign MUX_state$write_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[0] ; + assign MUX_state$write_1__SEL_2 = + WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[0] ; + assign MUX_state_1_1_1$write_1__SEL_1 = + WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[0] ; + assign MUX_state_1_1_1$write_1__SEL_2 = + WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[0] ; + assign MUX_state_1_1_1$write_1__SEL_3 = + WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[0] ; + assign MUX_activeSource_0$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate && + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1074 ; + assign MUX_activeSource_1$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate && + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1078 ; + assign MUX_activeSource_1_1_0$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate_3 && + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1912 ; + assign MUX_activeSource_1_1_1_1$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate_3 && + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1918 ; + assign MUX_activeSource_1_1_2$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate_3 && + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1924 ; + assign MUX_merged_0_flitLeft$write_1__VAL_1 = merged_0_flitLeft - 8'd1 ; + assign MUX_merged_1_flitLeft$write_1__VAL_1 = merged_1_flitLeft - 8'd1 ; + always@(MUX_flitToSink_1_0$wset_1__SEL_1 or + MUX_flitToSink_1_0$wset_1__SEL_4 or + ifcs_0_rspBack$D_OUT or + MUX_flitToSink_1_0$wset_1__SEL_2 or + MUX_flitToSink_1_0$wset_1__SEL_5 or + ifcs_1_rspBack$D_OUT or + MUX_flitToSink_1_0$wset_1__SEL_3 or + MUX_flitToSink_1_0$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_0$wset_1__SEL_1 || MUX_flitToSink_1_0$wset_1__SEL_4: + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_2 || MUX_flitToSink_1_0$wset_1__SEL_5: + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_3 || MUX_flitToSink_1_0$wset_1__SEL_6: + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; + default: MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1 = + 6'b101010 /* unspecified value */ ; + endcase + end + always@(MUX_flitToSink_1_1_0$wset_1__SEL_1 or + MUX_flitToSink_1_1_0$wset_1__SEL_4 or + ifcs_0_1_rspBack$D_OUT or + MUX_flitToSink_1_1_0$wset_1__SEL_2 or + MUX_flitToSink_1_1_0$wset_1__SEL_5 or + ifcs_1_1_rspBack$D_OUT or + MUX_flitToSink_1_1_0$wset_1__SEL_3 or + MUX_flitToSink_1_1_0$wset_1__SEL_6 or ifcs_2_1_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1_0$wset_1__SEL_1 || + MUX_flitToSink_1_1_0$wset_1__SEL_4: + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1 = + ifcs_0_1_rspBack$D_OUT; + MUX_flitToSink_1_1_0$wset_1__SEL_2 || + MUX_flitToSink_1_1_0$wset_1__SEL_5: + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1 = + ifcs_1_1_rspBack$D_OUT; + MUX_flitToSink_1_1_0$wset_1__SEL_3 || + MUX_flitToSink_1_1_0$wset_1__SEL_6: + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1 = + ifcs_2_1_rspBack$D_OUT; + default: MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1 = + 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + always@(MUX_flitToSink_1_1$wset_1__SEL_1 or + MUX_flitToSink_1_1$wset_1__SEL_4 or + ifcs_0_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_2 or + MUX_flitToSink_1_1$wset_1__SEL_5 or + ifcs_1_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_3 or + MUX_flitToSink_1_1$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1$wset_1__SEL_4: + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1$wset_1__SEL_5: + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1$wset_1__SEL_6: + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; + default: MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1 = + 6'b101010 /* unspecified value */ ; + endcase + end + always@(MUX_flitToSink_1_1_1_1$wset_1__SEL_1 or + MUX_flitToSink_1_1_1_1$wset_1__SEL_4 or + ifcs_0_1_rspBack$D_OUT or + MUX_flitToSink_1_1_1_1$wset_1__SEL_2 or + MUX_flitToSink_1_1_1_1$wset_1__SEL_5 or + ifcs_1_1_rspBack$D_OUT or + MUX_flitToSink_1_1_1_1$wset_1__SEL_3 or + MUX_flitToSink_1_1_1_1$wset_1__SEL_6 or ifcs_2_1_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1_1_1$wset_1__SEL_1 || + MUX_flitToSink_1_1_1_1$wset_1__SEL_4: + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1 = + ifcs_0_1_rspBack$D_OUT; + MUX_flitToSink_1_1_1_1$wset_1__SEL_2 || + MUX_flitToSink_1_1_1_1$wset_1__SEL_5: + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1 = + ifcs_1_1_rspBack$D_OUT; + MUX_flitToSink_1_1_1_1$wset_1__SEL_3 || + MUX_flitToSink_1_1_1_1$wset_1__SEL_6: + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1 = + ifcs_2_1_rspBack$D_OUT; + default: MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1 = + 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_split_0_flitLeft$write_1__VAL_1 = split_0_flitLeft - 8'd1 ; + assign MUX_split_1_flitLeft$write_1__VAL_1 = split_1_flitLeft - 8'd1 ; + assign MUX_split_2_flitLeft$write_1__VAL_1 = split_2_flitLeft - 8'd1 ; + + // inlined wires + assign msNoSynth_0_w_dwReady$whas = + WILL_FIRE_RL_merged_0_genOther || + WILL_FIRE_RL_merged_0_genFirst ; + assign msNoSynth_0_b_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_0_forwardRsp ? + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1 : + ifcs_0_noRouteRsp$D_OUT ; + assign msNoSynth_0_b_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_0_forwardRsp || + WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign msNoSynth_0_ar_dwReady$whas = + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp && + x_port1__read__h55959 == 9'd1 || + WILL_FIRE_RL_ifcs_0_1_drainFlits || + WILL_FIRE_RL_ifcs_0_1_followFlits || + WILL_FIRE_RL_ifcs_0_1_firstFlit ; + assign msNoSynth_0_r_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_0_1_forwardRsp ? + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1 : + ifcs_0_1_noRouteRsp$D_OUT ; + assign msNoSynth_0_r_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_0_1_forwardRsp || + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign msNoSynth_1_w_dwReady$whas = + WILL_FIRE_RL_merged_1_genOther || + WILL_FIRE_RL_merged_1_genFirst ; + assign msNoSynth_1_b_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_1_forwardRsp ? + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1 : + ifcs_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_b_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_1_forwardRsp || + WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ; + assign msNoSynth_1_ar_dwReady$whas = + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp && + x_port1__read__h58381 == 9'd1 || + WILL_FIRE_RL_ifcs_1_1_drainFlits || + WILL_FIRE_RL_ifcs_1_1_followFlits || + WILL_FIRE_RL_ifcs_1_1_firstFlit ; + assign msNoSynth_1_r_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_1_1_forwardRsp ? + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1 : + ifcs_1_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_r_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_1_1_forwardRsp || + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + assign ssNoSynth_0_w_buffer_enqw$whas = + WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] || + WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[171] ; + assign ssNoSynth_0_b_dwReady$whas = + WILL_FIRE_RL_ifcs_0_followFlits_1 || + WILL_FIRE_RL_ifcs_0_firstFlit_1 ; + assign ssNoSynth_0_ar_buffer_enqw$wget = + (MUX_flitToSink_1_0_1$wset_1__SEL_1 || + MUX_flitToSink_1_0_1$wset_1__SEL_3) ? + ifcs_0_1_innerReq$D_OUT : + ifcs_1_1_innerReq$D_OUT ; + assign ssNoSynth_0_r_dwReady$whas = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 || + WILL_FIRE_RL_ifcs_0_1_firstFlit_1 ; + assign ssNoSynth_1_aw_buffer_enqw$wget = split_1_doPut$wget[170:73] ; + assign ssNoSynth_1_w_buffer_enqw$wget = split_1_doPut$wget[72:0] ; + assign ssNoSynth_1_w_buffer_enqw$whas = + WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] || + WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[171] ; + assign ssNoSynth_1_b_dwReady$whas = + WILL_FIRE_RL_ifcs_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_firstFlit_1 ; + assign ssNoSynth_1_ar_buffer_enqw$wget = + (MUX_flitToSink_1_1_1$wset_1__SEL_1 || + MUX_flitToSink_1_1_1$wset_1__SEL_3) ? + ifcs_0_1_innerReq$D_OUT : + ifcs_1_1_innerReq$D_OUT ; + assign ssNoSynth_1_r_dwReady$whas = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 ; + assign ssNoSynth_2_aw_buffer_enqw$wget = split_2_doPut$wget[170:73] ; + assign ssNoSynth_2_w_buffer_enqw$wget = split_2_doPut$wget[72:0] ; + assign ssNoSynth_2_w_buffer_enqw$whas = + WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] || + WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[171] ; + assign ssNoSynth_2_b_dwReady$whas = + WILL_FIRE_RL_ifcs_2_followFlits || + WILL_FIRE_RL_ifcs_2_firstFlit ; + assign ssNoSynth_2_ar_buffer_enqw$wget = + (MUX_flitToSink_1_2$wset_1__SEL_1 || + MUX_flitToSink_1_2$wset_1__SEL_3) ? + ifcs_0_1_innerReq$D_OUT : + ifcs_1_1_innerReq$D_OUT ; + assign ssNoSynth_2_r_dwReady$whas = + WILL_FIRE_RL_ifcs_2_1_followFlits || + WILL_FIRE_RL_ifcs_2_1_firstFlit ; + assign split_0_doPut$wget = + (MUX_flitToSink_0$wset_1__SEL_1 || + MUX_flitToSink_0$wset_1__SEL_3) ? + ifcs_0_innerReq$D_OUT : + ifcs_1_innerReq$D_OUT ; + assign split_1_doPut$wget = + (MUX_flitToSink_1$wset_1__SEL_1 || + MUX_flitToSink_1$wset_1__SEL_3) ? + ifcs_0_innerReq$D_OUT : + ifcs_1_innerReq$D_OUT ; + assign split_2_doPut$wget = + (MUX_flitToSink_2$wset_1__SEL_1 || + MUX_flitToSink_2$wset_1__SEL_3) ? + ifcs_0_innerReq$D_OUT : + ifcs_1_innerReq$D_OUT ; + assign reqWires_0$wget = + (!ifcs_0_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992) ? + IF_NOT_ifcs_0_innerRoute_first__000_BIT_1_009__ETC___d1022 : + ifcs_0_innerRoute$D_OUT[0] ; + assign reqWires_1$wget = + (!ifcs_1_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992) ? + IF_NOT_ifcs_1_innerRoute_first__029_BIT_1_033__ETC___d1038 : + ifcs_1_innerRoute$D_OUT[0] ; + assign flitToSink_0$whas = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerRoute$D_OUT[0] ; + assign flitToSink_1$whas = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[1] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerRoute$D_OUT[1] ; + assign flitToSink_2$whas = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[2] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerRoute$D_OUT[2] ; + assign reqWires_1_0$wget = + (!ifcs_0_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_0_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_0_routeBack$D_OUT[0] ; + assign reqWires_1_1$wget = + (!ifcs_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_1_routeBack$D_OUT[0] ; + assign reqWires_1_2$wget = + (!ifcs_2_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_2_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_2_routeBack$D_OUT[0] ; + assign flitToSink_1_0$whas = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[0] ; + assign flitToSink_1_1$whas = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[1] ; + assign reqWires_1_0_1$wget = + (!ifcs_0_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__638_BIT_1_64_ETC___d1660 : + ifcs_0_1_innerRoute$D_OUT[0] ; + assign reqWires_1_1_1$wget = + (!ifcs_1_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__667_BIT_1_67_ETC___d1676 : + ifcs_1_1_innerRoute$D_OUT[0] ; + assign flitToSink_1_0_1$whas = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + ifcs_1_1_innerRoute$D_OUT[0] ; + assign flitToSink_1_1_1$whas = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + ifcs_1_1_innerRoute$D_OUT[1] ; + assign flitToSink_1_2$whas = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + ifcs_1_1_innerRoute$D_OUT[2] ; + assign reqWires_1_1_0$wget = + (!ifcs_0_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_0_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_0_1_routeBack$D_OUT[0] ; + assign reqWires_1_1_1_1$wget = + (!ifcs_1_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_1_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_1_1_routeBack$D_OUT[0] ; + assign reqWires_1_1_2$wget = + (!ifcs_2_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_2_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_2_1_routeBack$D_OUT[0] ; + assign flitToSink_1_1_0$whas = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[0] ; + assign flitToSink_1_1_1_1$whas = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[1] ; + assign merged_0_doDrop$whas = + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp || + WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits || + WILL_FIRE_RL_ifcs_0_firstFlit ; + assign merged_1_doDrop$whas = + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp || + WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits || + WILL_FIRE_RL_ifcs_1_firstFlit ; + assign sourceSelect_1_0$whas = + WILL_FIRE_RL_arbitrate_1 && + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1284 ; + assign sourceSelect_1_1$whas = + WILL_FIRE_RL_arbitrate_1 && + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1290 ; + assign sourceSelect_1_2$whas = + WILL_FIRE_RL_arbitrate_1 && + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1296 ; + assign sourceSelect_1_0_1$whas = + WILL_FIRE_RL_arbitrate_2 && + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1712 ; + assign sourceSelect_1_1_1$whas = + WILL_FIRE_RL_arbitrate_2 && + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1716 ; + assign ifcs_0_noRoute_inner_currentReq$EN_port0__write = + WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + merged_0_flitLeft == 8'd0 ; + assign ifcs_0_noRoute_inner_currentReq$port0__write_1 = + { cpu$dmem_master_awid, + cpu$dmem_master_awaddr, + cpu$dmem_master_awlen, + cpu$dmem_master_awsize, + cpu$dmem_master_awburst, + cpu$dmem_master_awlock, + cpu$dmem_master_awcache, + cpu$dmem_master_awprot, + cpu$dmem_master_awqos, + cpu$dmem_master_awregion } ; + assign ifcs_0_noRoute_inner_currentReq$port1__read = + ifcs_0_noRoute_inner_currentReq$EN_port0__write ? + ifcs_0_noRoute_inner_currentReq$port0__write_1 : + ifcs_0_noRoute_inner_currentReq ; + assign ifcs_0_noRoute_inner_pendingReq$EN_port0__write = + WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + merged_0_flitLeft == 8'd0 ; + assign ifcs_0_noRoute_inner_pendingReq$port1__read = + ifcs_0_noRoute_inner_pendingReq$EN_port0__write || + ifcs_0_noRoute_inner_pendingReq ; + assign ifcs_0_noRoute_inner_pendingReq$port2__read = + !CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp && + ifcs_0_noRoute_inner_pendingReq$port1__read ; + assign ifcs_1_noRoute_inner_currentReq$EN_port0__write = + WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + merged_1_flitLeft == 8'd0 ; + assign ifcs_1_noRoute_inner_currentReq$port0__write_1 = + { dm_mem_tap$master_awid, + dm_mem_tap$master_awaddr, + dm_mem_tap$master_awlen, + dm_mem_tap$master_awsize, + dm_mem_tap$master_awburst, + dm_mem_tap$master_awlock, + dm_mem_tap$master_awcache, + dm_mem_tap$master_awprot, + dm_mem_tap$master_awqos, + dm_mem_tap$master_awregion } ; + assign ifcs_1_noRoute_inner_currentReq$port1__read = + ifcs_1_noRoute_inner_currentReq$EN_port0__write ? + ifcs_1_noRoute_inner_currentReq$port0__write_1 : + ifcs_1_noRoute_inner_currentReq ; + assign ifcs_1_noRoute_inner_pendingReq$EN_port0__write = + WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + merged_1_flitLeft == 8'd0 ; + assign ifcs_1_noRoute_inner_pendingReq$port1__read = + ifcs_1_noRoute_inner_pendingReq$EN_port0__write || + ifcs_1_noRoute_inner_pendingReq ; + assign ifcs_1_noRoute_inner_pendingReq$port2__read = + !CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp && + ifcs_1_noRoute_inner_pendingReq$port1__read ; + assign ifcs_0_1_noRoute_currentReq$port0__write_1 = + { cpu$dmem_master_arid, + cpu$dmem_master_araddr, + cpu$dmem_master_arlen, + cpu$dmem_master_arsize, + cpu$dmem_master_arburst, + cpu$dmem_master_arlock, + cpu$dmem_master_arcache, + cpu$dmem_master_arprot, + cpu$dmem_master_arqos, + cpu$dmem_master_arregion } ; + assign ifcs_0_1_noRoute_currentReq$port1__read = + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? + ifcs_0_1_noRoute_currentReq$port0__write_1 : + ifcs_0_1_noRoute_currentReq ; + assign ifcs_0_1_noRoute_flitCount$port0__write_1 = + { 1'd0, cpu$dmem_master_arlen } + 9'd1 ; + assign ifcs_0_1_noRoute_flitCount$port1__write_1 = + x_port1__read__h55959 - 9'd1 ; + assign ifcs_0_1_noRoute_flitCount$port2__read = + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ? + ifcs_0_1_noRoute_flitCount$port1__write_1 : + x_port1__read__h55959 ; + assign ifcs_1_1_noRoute_currentReq$port0__write_1 = + { dm_mem_tap$master_arid, + dm_mem_tap$master_araddr, + dm_mem_tap$master_arlen, + dm_mem_tap$master_arsize, + dm_mem_tap$master_arburst, + dm_mem_tap$master_arlock, + dm_mem_tap$master_arcache, + dm_mem_tap$master_arprot, + dm_mem_tap$master_arqos, + dm_mem_tap$master_arregion } ; + assign ifcs_1_1_noRoute_currentReq$port1__read = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? + ifcs_1_1_noRoute_currentReq$port0__write_1 : + ifcs_1_1_noRoute_currentReq ; + assign ifcs_1_1_noRoute_flitCount$port0__write_1 = + { 1'd0, dm_mem_tap$master_arlen } + 9'd1 ; + assign ifcs_1_1_noRoute_flitCount$port1__write_1 = + x_port1__read__h58381 - 9'd1 ; + assign ifcs_1_1_noRoute_flitCount$port2__read = + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ? + ifcs_1_1_noRoute_flitCount$port1__write_1 : + x_port1__read__h58381 ; + + // register activeSource_0 + assign activeSource_0$D_IN = + MUX_activeSource_0$write_1__SEL_1 ? + MUX_activeSource_0$write_1__VAL_1 : + MUX_activeSource_0$write_1__VAL_1 ; + assign activeSource_0$EN = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + !ifcs_1_innerReq$D_OUT[0] ; + + // register activeSource_1 + assign activeSource_1$D_IN = + MUX_activeSource_0$write_1__SEL_1 ? + MUX_activeSource_1$write_1__VAL_1 : + MUX_activeSource_1$write_1__VAL_1 ; + assign activeSource_1$EN = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + !ifcs_1_innerReq$D_OUT[0] ; + + // register activeSource_1_0 + assign activeSource_1_0$D_IN = 1'b0 ; + assign activeSource_1_0$EN = 1'b0 ; + + // register activeSource_1_0_1 + assign activeSource_1_0_1$D_IN = 1'b0 ; + assign activeSource_1_0_1$EN = 1'b0 ; + + // register activeSource_1_1 + assign activeSource_1_1$D_IN = 1'b0 ; + assign activeSource_1_1$EN = 1'b0 ; + + // register activeSource_1_1_0 + always@(MUX_activeSource_1_1_0$write_1__SEL_1 or + MUX_activeSource_1_1_0$write_1__VAL_1 or + MUX_activeSource_1_1_0$write_1__SEL_2 or + MUX_activeSource_1_1_0$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_activeSource_1_1_0$write_1__SEL_1: + activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_2: + activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_3: + activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; + default: activeSource_1_1_0$D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign activeSource_1_1_0$EN = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[0] ; + + // register activeSource_1_1_1 + assign activeSource_1_1_1$D_IN = 1'b0 ; + assign activeSource_1_1_1$EN = 1'b0 ; + + // register activeSource_1_1_1_1 + always@(MUX_activeSource_1_1_0$write_1__SEL_1 or + MUX_activeSource_1_1_1_1$write_1__VAL_1 or + MUX_activeSource_1_1_0$write_1__SEL_2 or + MUX_activeSource_1_1_0$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_activeSource_1_1_0$write_1__SEL_1: + activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_2: + activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_3: + activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; + default: activeSource_1_1_1_1$D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign activeSource_1_1_1_1$EN = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[0] ; + + // register activeSource_1_1_2 + always@(MUX_activeSource_1_1_0$write_1__SEL_1 or + MUX_activeSource_1_1_2$write_1__VAL_1 or + MUX_activeSource_1_1_0$write_1__SEL_2 or + MUX_activeSource_1_1_0$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_activeSource_1_1_0$write_1__SEL_1: + activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_2: + activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_3: + activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; + default: activeSource_1_1_2$D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign activeSource_1_1_2$EN = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[0] ; + + // register activeSource_1_2 + assign activeSource_1_2$D_IN = 1'b0 ; + assign activeSource_1_2$EN = 1'b0 ; + + // register arbiter_1_1_firstHot + assign arbiter_1_1_firstHot$D_IN = + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1924 ; + assign arbiter_1_1_firstHot$EN = CAN_FIRE_RL_arbitrate_3 ; + + // register arbiter_1_1_lastSelect + assign arbiter_1_1_lastSelect$D_IN = + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1912 ; + assign arbiter_1_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_3 ; + + // register arbiter_1_1_lastSelect_1 + assign arbiter_1_1_lastSelect_1$D_IN = + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1918 ; + assign arbiter_1_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_3 ; + + // register arbiter_1_firstHot + assign arbiter_1_firstHot$D_IN = + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1296 ; + assign arbiter_1_firstHot$EN = CAN_FIRE_RL_arbitrate_1 ; + + // register arbiter_1_firstHot_1 + assign arbiter_1_firstHot_1$D_IN = + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1716 ; + assign arbiter_1_firstHot_1$EN = CAN_FIRE_RL_arbitrate_2 ; + + // register arbiter_1_lastSelect + assign arbiter_1_lastSelect$D_IN = + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1284 ; + assign arbiter_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_1 ; + + // register arbiter_1_lastSelect_1 + assign arbiter_1_lastSelect_1$D_IN = + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1290 ; + assign arbiter_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_1 ; + + // register arbiter_1_lastSelect_2 + assign arbiter_1_lastSelect_2$D_IN = + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1712 ; + assign arbiter_1_lastSelect_2$EN = CAN_FIRE_RL_arbitrate_2 ; + + // register arbiter_firstHot + assign arbiter_firstHot$D_IN = + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1078 ; + assign arbiter_firstHot$EN = CAN_FIRE_RL_arbitrate ; + + // register arbiter_lastSelect + assign arbiter_lastSelect$D_IN = + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1074 ; + assign arbiter_lastSelect$EN = CAN_FIRE_RL_arbitrate ; + + // register ifcs_0_1_noRoute_currentReq + assign ifcs_0_1_noRoute_currentReq$D_IN = + ifcs_0_1_noRoute_currentReq$port1__read ; + assign ifcs_0_1_noRoute_currentReq$EN = 1'b1 ; + + // register ifcs_0_1_noRoute_flitCount + assign ifcs_0_1_noRoute_flitCount$D_IN = + ifcs_0_1_noRoute_flitCount$port2__read ; + assign ifcs_0_1_noRoute_flitCount$EN = 1'b1 ; + + // register ifcs_0_1_state + assign ifcs_0_1_state$D_IN = 2'd0 ; + assign ifcs_0_1_state$EN = + WILL_FIRE_RL_ifcs_0_1_drainFlits || + WILL_FIRE_RL_ifcs_0_1_followFlits ; + + // register ifcs_0_1_state_1 + assign ifcs_0_1_state_1$D_IN = !MUX_ifcs_0_1_state_1$write_1__SEL_1 ; + assign ifcs_0_1_state_1$EN = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 && shim_rff$D_OUT[0] || + WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && !shim_rff$D_OUT[0] ; + + // register ifcs_0_noRoute_inner_currentReq + assign ifcs_0_noRoute_inner_currentReq$D_IN = + ifcs_0_noRoute_inner_currentReq$port1__read ; + assign ifcs_0_noRoute_inner_currentReq$EN = 1'b1 ; + + // register ifcs_0_noRoute_inner_pendingReq + assign ifcs_0_noRoute_inner_pendingReq$D_IN = + ifcs_0_noRoute_inner_pendingReq$port2__read ; + assign ifcs_0_noRoute_inner_pendingReq$EN = 1'b1 ; + + // register ifcs_0_state + always@(MUX_ifcs_0_state$write_1__SEL_1 or + MUX_ifcs_0_state$write_1__SEL_2 or MUX_ifcs_0_state$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_ifcs_0_state$write_1__SEL_1: ifcs_0_state$D_IN = 2'd0; + MUX_ifcs_0_state$write_1__SEL_2: ifcs_0_state$D_IN = 2'd1; + MUX_ifcs_0_state$write_1__SEL_3: ifcs_0_state$D_IN = 2'd2; + default: ifcs_0_state$D_IN = 2'b10 /* unspecified value */ ; + endcase + end + assign ifcs_0_state$EN = + (WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits) && + cpu$dmem_master_wlast || + WILL_FIRE_RL_ifcs_0_firstFlit && !cpu$dmem_master_wlast || + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !cpu$dmem_master_wlast ; + + // register ifcs_0_state_1 + assign ifcs_0_state_1$D_IN = 1'd0 ; + assign ifcs_0_state_1$EN = CAN_FIRE_RL_ifcs_0_followFlits_1 ; + + // register ifcs_1_1_noRoute_currentReq + assign ifcs_1_1_noRoute_currentReq$D_IN = + ifcs_1_1_noRoute_currentReq$port1__read ; + assign ifcs_1_1_noRoute_currentReq$EN = 1'b1 ; + + // register ifcs_1_1_noRoute_flitCount + assign ifcs_1_1_noRoute_flitCount$D_IN = + ifcs_1_1_noRoute_flitCount$port2__read ; + assign ifcs_1_1_noRoute_flitCount$EN = 1'b1 ; + + // register ifcs_1_1_state + assign ifcs_1_1_state$D_IN = 2'd0 ; + assign ifcs_1_1_state$EN = + WILL_FIRE_RL_ifcs_1_1_drainFlits || + WILL_FIRE_RL_ifcs_1_1_followFlits ; + + // register ifcs_1_1_state_1 + assign ifcs_1_1_state_1$D_IN = !MUX_ifcs_1_1_state_1$write_1__SEL_1 ; + assign ifcs_1_1_state_1$EN = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && + near_mem_io$axi4_slave_rlast || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && + !near_mem_io$axi4_slave_rlast ; + + // register ifcs_1_noRoute_inner_currentReq + assign ifcs_1_noRoute_inner_currentReq$D_IN = + ifcs_1_noRoute_inner_currentReq$port1__read ; + assign ifcs_1_noRoute_inner_currentReq$EN = 1'b1 ; + + // register ifcs_1_noRoute_inner_pendingReq + assign ifcs_1_noRoute_inner_pendingReq$D_IN = + ifcs_1_noRoute_inner_pendingReq$port2__read ; + assign ifcs_1_noRoute_inner_pendingReq$EN = 1'b1 ; + + // register ifcs_1_state + always@(MUX_ifcs_1_state$write_1__SEL_1 or + MUX_ifcs_1_state$write_1__SEL_2 or MUX_ifcs_1_state$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_ifcs_1_state$write_1__SEL_1: ifcs_1_state$D_IN = 2'd0; + MUX_ifcs_1_state$write_1__SEL_2: ifcs_1_state$D_IN = 2'd1; + MUX_ifcs_1_state$write_1__SEL_3: ifcs_1_state$D_IN = 2'd2; + default: ifcs_1_state$D_IN = 2'b10 /* unspecified value */ ; + endcase + end + assign ifcs_1_state$EN = + (WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits) && + dm_mem_tap$master_wlast || + WILL_FIRE_RL_ifcs_1_firstFlit && !dm_mem_tap$master_wlast || + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && + !dm_mem_tap$master_wlast ; + + // register ifcs_1_state_1 + assign ifcs_1_state_1$D_IN = 1'd0 ; + assign ifcs_1_state_1$EN = CAN_FIRE_RL_ifcs_1_followFlits_1 ; + + // register ifcs_2_1_state + assign ifcs_2_1_state$D_IN = !MUX_ifcs_2_1_state$write_1__SEL_1 ; + assign ifcs_2_1_state$EN = + WILL_FIRE_RL_ifcs_2_1_followFlits && plic$axi4_slave_rlast || + WILL_FIRE_RL_ifcs_2_1_firstFlit && !plic$axi4_slave_rlast ; + + // register ifcs_2_state + assign ifcs_2_state$D_IN = 1'd0 ; + assign ifcs_2_state$EN = CAN_FIRE_RL_ifcs_2_followFlits ; + + // register merged_0_flitLeft + assign merged_0_flitLeft$D_IN = + WILL_FIRE_RL_merged_0_genOther ? + MUX_merged_0_flitLeft$write_1__VAL_1 : + cpu$dmem_master_awlen ; + assign merged_0_flitLeft$EN = msNoSynth_0_w_dwReady$whas ; + + // register merged_1_flitLeft + assign merged_1_flitLeft$D_IN = + WILL_FIRE_RL_merged_1_genOther ? + MUX_merged_1_flitLeft$write_1__VAL_1 : + dm_mem_tap$master_awlen ; + assign merged_1_flitLeft$EN = msNoSynth_1_w_dwReady$whas ; + + // register split_0_flitLeft + assign split_0_flitLeft$D_IN = + MUX_split_0_flitLeft$write_1__SEL_1 ? + MUX_split_0_flitLeft$write_1__VAL_1 : + split_0_doPut$wget[101:94] ; + assign split_0_flitLeft$EN = ssNoSynth_0_w_buffer_enqw$whas ; + + // register split_1_flitLeft + assign split_1_flitLeft$D_IN = + MUX_split_1_flitLeft$write_1__SEL_1 ? + MUX_split_1_flitLeft$write_1__VAL_1 : + split_1_doPut$wget[101:94] ; + assign split_1_flitLeft$EN = ssNoSynth_1_w_buffer_enqw$whas ; + + // register split_2_flitLeft + assign split_2_flitLeft$D_IN = + MUX_split_2_flitLeft$write_1__SEL_1 ? + MUX_split_2_flitLeft$write_1__VAL_1 : + split_2_doPut$wget[101:94] ; + assign split_2_flitLeft$EN = ssNoSynth_2_w_buffer_enqw$whas ; + + // register state + assign state$D_IN = !MUX_state$write_1__SEL_1 && !MUX_state$write_1__SEL_2 ; + assign state$EN = + WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[0] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + !ifcs_1_innerReq$D_OUT[0] ; + + // register state_1 + assign state_1$D_IN = 1'd0 ; + assign state_1$EN = + WILL_FIRE_RL_burst_4 || WILL_FIRE_RL_burst_3 || + WILL_FIRE_RL_burst_2 ; + + // register state_1_1 + assign state_1_1$D_IN = 1'd0 ; + assign state_1_1$EN = WILL_FIRE_RL_burst_6 || WILL_FIRE_RL_burst_5 ; + + // register state_1_1_1 + assign state_1_1_1$D_IN = + !MUX_state_1_1_1$write_1__SEL_1 && + !MUX_state_1_1_1$write_1__SEL_2 && + !MUX_state_1_1_1$write_1__SEL_3 ; + assign state_1_1_1$EN = + WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[0] ; + + // submodule cpu + assign cpu$dmem_master_arready = msNoSynth_0_ar_dwReady$whas ; + assign cpu$dmem_master_awready = CAN_FIRE_RL_merged_0_genFirst ; + assign cpu$dmem_master_bid = + msNoSynth_0_b_buffer_ff$EMPTY_N ? + msNoSynth_0_b_buffer_ff$D_OUT[5:2] : + msNoSynth_0_b_buffer_enqw$wget[5:2] ; + assign cpu$dmem_master_bresp = + msNoSynth_0_b_buffer_ff$EMPTY_N ? + msNoSynth_0_b_buffer_ff$D_OUT[1:0] : + msNoSynth_0_b_buffer_enqw$wget[1:0] ; + assign cpu$dmem_master_rdata = + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[66:3] : + msNoSynth_0_r_buffer_enqw$wget[66:3] ; + assign cpu$dmem_master_rid = + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[70:67] : + msNoSynth_0_r_buffer_enqw$wget[70:67] ; + assign cpu$dmem_master_rlast = + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[0] : + msNoSynth_0_r_buffer_enqw$wget[0] ; + assign cpu$dmem_master_rresp = + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[2:1] : + msNoSynth_0_r_buffer_enqw$wget[2:1] ; + assign cpu$dmem_master_wready = msNoSynth_0_w_dwReady$whas ; + assign cpu$hart0_csr_mem_server_request_put = + dm_csr_tap$client_request_get ; + assign cpu$hart0_gpr_mem_server_request_put = + dm_gpr_tap_ifc$client_request_get ; + assign cpu$hart0_put_other_req_put = debug_module$hart0_get_other_req_get ; + assign cpu$hart0_server_reset_request_put = + WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ? + f_reset_reqs$D_OUT : + debug_module$hart0_reset_client_request_get ; + assign cpu$hart0_server_run_halt_request_put = + debug_module$hart0_client_run_halt_request_get ; + assign cpu$imem_master_arready = cpu_imem_master_arready ; + assign cpu$imem_master_awready = cpu_imem_master_awready ; + assign cpu$imem_master_bid = cpu_imem_master_bid ; + assign cpu$imem_master_bresp = cpu_imem_master_bresp ; + assign cpu$imem_master_rdata = cpu_imem_master_rdata ; + assign cpu$imem_master_rid = cpu_imem_master_rid ; + assign cpu$imem_master_rlast = cpu_imem_master_rlast ; + assign cpu$imem_master_rresp = cpu_imem_master_rresp ; + assign cpu$imem_master_wready = cpu_imem_master_wready ; + assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; + assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; + assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; + assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; + assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; + assign cpu$software_interrupt_req_set_not_clear = near_mem_io$get_sw_interrupt_req_get ; assign cpu$timer_interrupt_req_set_not_clear = near_mem_io$get_timer_interrupt_req_get ; @@ -3049,6 +6817,10 @@ module mkCore(CLK, WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ; assign cpu$EN_hart0_server_reset_response_get = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; + assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; + assign cpu$dmem_master_bvalid = CAN_FIRE_RL_msNoSynth_0_b_forwardFlit ; + assign cpu$dmem_master_rvalid = CAN_FIRE_RL_msNoSynth_0_r_forwardFlit ; assign cpu$EN_set_verbosity = EN_set_verbosity ; assign cpu$EN_trace_data_out_get = WILL_FIRE_RL_merge_cpu_trace_data ; assign cpu$EN_hart0_server_run_halt_request_put = @@ -3082,12 +6854,10 @@ module mkCore(CLK, assign debug_module$master_awready = dm_mem_tap$slave_awready ; assign debug_module$master_bid = dm_mem_tap$slave_bid ; assign debug_module$master_bresp = dm_mem_tap$slave_bresp ; - assign debug_module$master_bvalid = dm_mem_tap$slave_bvalid ; assign debug_module$master_rdata = dm_mem_tap$slave_rdata ; assign debug_module$master_rid = dm_mem_tap$slave_rid ; assign debug_module$master_rlast = dm_mem_tap$slave_rlast ; assign debug_module$master_rresp = dm_mem_tap$slave_rresp ; - assign debug_module$master_rvalid = dm_mem_tap$slave_rvalid ; assign debug_module$master_wready = dm_mem_tap$slave_wready ; assign debug_module$ndm_reset_client_response_put = ndm_reset_client_response_put ; @@ -3117,6 +6887,8 @@ module mkCore(CLK, EN_ndm_reset_client_request_get ; assign debug_module$EN_ndm_reset_client_response_put = EN_ndm_reset_client_response_put ; + assign debug_module$master_bvalid = dm_mem_tap$slave_bvalid ; + assign debug_module$master_rvalid = dm_mem_tap$slave_rvalid ; // submodule dm_csr_tap assign dm_csr_tap$client_response_put = @@ -3151,17 +6923,33 @@ module mkCore(CLK, CAN_FIRE_RL_merge_dm_gpr_trace_data ; // submodule dm_mem_tap - assign dm_mem_tap$master_arready = fabric_2x3$v_from_masters_1_arready ; - assign dm_mem_tap$master_awready = fabric_2x3$v_from_masters_1_awready ; - assign dm_mem_tap$master_bid = fabric_2x3$v_from_masters_1_bid ; - assign dm_mem_tap$master_bresp = fabric_2x3$v_from_masters_1_bresp ; - assign dm_mem_tap$master_bvalid = fabric_2x3$v_from_masters_1_bvalid ; - assign dm_mem_tap$master_rdata = fabric_2x3$v_from_masters_1_rdata ; - assign dm_mem_tap$master_rid = fabric_2x3$v_from_masters_1_rid ; - assign dm_mem_tap$master_rlast = fabric_2x3$v_from_masters_1_rlast ; - assign dm_mem_tap$master_rresp = fabric_2x3$v_from_masters_1_rresp ; - assign dm_mem_tap$master_rvalid = fabric_2x3$v_from_masters_1_rvalid ; - assign dm_mem_tap$master_wready = fabric_2x3$v_from_masters_1_wready ; + assign dm_mem_tap$master_arready = msNoSynth_1_ar_dwReady$whas ; + assign dm_mem_tap$master_awready = CAN_FIRE_RL_merged_1_genFirst ; + assign dm_mem_tap$master_bid = + msNoSynth_1_b_buffer_ff$EMPTY_N ? + msNoSynth_1_b_buffer_ff$D_OUT[5:2] : + msNoSynth_1_b_buffer_enqw$wget[5:2] ; + assign dm_mem_tap$master_bresp = + msNoSynth_1_b_buffer_ff$EMPTY_N ? + msNoSynth_1_b_buffer_ff$D_OUT[1:0] : + msNoSynth_1_b_buffer_enqw$wget[1:0] ; + assign dm_mem_tap$master_rdata = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[66:3] : + msNoSynth_1_r_buffer_enqw$wget[66:3] ; + assign dm_mem_tap$master_rid = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[70:67] : + msNoSynth_1_r_buffer_enqw$wget[70:67] ; + assign dm_mem_tap$master_rlast = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[0] : + msNoSynth_1_r_buffer_enqw$wget[0] ; + assign dm_mem_tap$master_rresp = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[2:1] : + msNoSynth_1_r_buffer_enqw$wget[2:1] ; + assign dm_mem_tap$master_wready = msNoSynth_1_w_dwReady$whas ; assign dm_mem_tap$slave_araddr = debug_module$master_araddr ; assign dm_mem_tap$slave_arburst = debug_module$master_arburst ; assign dm_mem_tap$slave_arcache = debug_module$master_arcache ; @@ -3172,7 +6960,6 @@ module mkCore(CLK, assign dm_mem_tap$slave_arqos = debug_module$master_arqos ; assign dm_mem_tap$slave_arregion = debug_module$master_arregion ; assign dm_mem_tap$slave_arsize = debug_module$master_arsize ; - assign dm_mem_tap$slave_arvalid = debug_module$master_arvalid ; assign dm_mem_tap$slave_awaddr = debug_module$master_awaddr ; assign dm_mem_tap$slave_awburst = debug_module$master_awburst ; assign dm_mem_tap$slave_awcache = debug_module$master_awcache ; @@ -3183,13 +6970,16 @@ module mkCore(CLK, assign dm_mem_tap$slave_awqos = debug_module$master_awqos ; assign dm_mem_tap$slave_awregion = debug_module$master_awregion ; assign dm_mem_tap$slave_awsize = debug_module$master_awsize ; - assign dm_mem_tap$slave_awvalid = debug_module$master_awvalid ; assign dm_mem_tap$slave_bready = debug_module$master_bready ; assign dm_mem_tap$slave_rready = debug_module$master_rready ; assign dm_mem_tap$slave_wdata = debug_module$master_wdata ; assign dm_mem_tap$slave_wlast = debug_module$master_wlast ; assign dm_mem_tap$slave_wstrb = debug_module$master_wstrb ; + assign dm_mem_tap$slave_awvalid = debug_module$master_awvalid ; assign dm_mem_tap$slave_wvalid = debug_module$master_wvalid ; + assign dm_mem_tap$slave_arvalid = debug_module$master_arvalid ; + assign dm_mem_tap$master_bvalid = CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; + assign dm_mem_tap$master_rvalid = CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; assign dm_mem_tap$EN_trace_data_out_get = WILL_FIRE_RL_merge_dm_mem_trace_data ; @@ -3198,8 +6988,7 @@ module mkCore(CLK, assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; assign f_reset_reqs$DEQ = near_mem_io$RDY_server_reset_request_put && - plic$RDY_server_reset_request_put && - fabric_2x3_RDY_reset_AND_cpu_RDY_hart0_server__ETC___d9 ; + plic_RDY_server_reset_request_put_AND_cpu_RDY__ETC___d8 ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_requestor @@ -3250,134 +7039,460 @@ module mkCore(CLK, assign f_trace_data_merged$DEQ = CAN_FIRE_RL_mkConnectionGetPut_1 ; assign f_trace_data_merged$CLR = 1'b0 ; - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; - assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; - assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; - assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; - assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; - assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; - assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; - assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = dm_mem_tap$master_araddr ; - assign fabric_2x3$v_from_masters_1_arburst = dm_mem_tap$master_arburst ; - assign fabric_2x3$v_from_masters_1_arcache = dm_mem_tap$master_arcache ; - assign fabric_2x3$v_from_masters_1_arid = dm_mem_tap$master_arid ; - assign fabric_2x3$v_from_masters_1_arlen = dm_mem_tap$master_arlen ; - assign fabric_2x3$v_from_masters_1_arlock = dm_mem_tap$master_arlock ; - assign fabric_2x3$v_from_masters_1_arprot = dm_mem_tap$master_arprot ; - assign fabric_2x3$v_from_masters_1_arqos = dm_mem_tap$master_arqos ; - assign fabric_2x3$v_from_masters_1_arregion = dm_mem_tap$master_arregion ; - assign fabric_2x3$v_from_masters_1_arsize = dm_mem_tap$master_arsize ; - assign fabric_2x3$v_from_masters_1_arvalid = dm_mem_tap$master_arvalid ; - assign fabric_2x3$v_from_masters_1_awaddr = dm_mem_tap$master_awaddr ; - assign fabric_2x3$v_from_masters_1_awburst = dm_mem_tap$master_awburst ; - assign fabric_2x3$v_from_masters_1_awcache = dm_mem_tap$master_awcache ; - assign fabric_2x3$v_from_masters_1_awid = dm_mem_tap$master_awid ; - assign fabric_2x3$v_from_masters_1_awlen = dm_mem_tap$master_awlen ; - assign fabric_2x3$v_from_masters_1_awlock = dm_mem_tap$master_awlock ; - assign fabric_2x3$v_from_masters_1_awprot = dm_mem_tap$master_awprot ; - assign fabric_2x3$v_from_masters_1_awqos = dm_mem_tap$master_awqos ; - assign fabric_2x3$v_from_masters_1_awregion = dm_mem_tap$master_awregion ; - assign fabric_2x3$v_from_masters_1_awsize = dm_mem_tap$master_awsize ; - assign fabric_2x3$v_from_masters_1_awvalid = dm_mem_tap$master_awvalid ; - assign fabric_2x3$v_from_masters_1_bready = dm_mem_tap$master_bready ; - assign fabric_2x3$v_from_masters_1_rready = dm_mem_tap$master_rready ; - assign fabric_2x3$v_from_masters_1_wdata = dm_mem_tap$master_wdata ; - assign fabric_2x3$v_from_masters_1_wlast = dm_mem_tap$master_wlast ; - assign fabric_2x3$v_from_masters_1_wstrb = dm_mem_tap$master_wstrb ; - assign fabric_2x3$v_from_masters_1_wvalid = dm_mem_tap$master_wvalid ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; - assign fabric_2x3$EN_reset = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; + // submodule ifcs_0_1_innerReq + assign ifcs_0_1_innerReq$D_IN = + { fatReq_arid__h55399, + cpu$dmem_master_araddr, + cpu$dmem_master_arlen, + cpu$dmem_master_arsize, + cpu$dmem_master_arburst, + cpu$dmem_master_arlock, + cpu$dmem_master_arcache, + cpu$dmem_master_arprot, + cpu$dmem_master_arqos, + cpu$dmem_master_arregion } ; + assign ifcs_0_1_innerReq$ENQ = + WILL_FIRE_RL_ifcs_0_1_followFlits || + WILL_FIRE_RL_ifcs_0_1_firstFlit ; + assign ifcs_0_1_innerReq$DEQ = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_5 ; + assign ifcs_0_1_innerReq$CLR = 1'b0 ; + + // submodule ifcs_0_1_innerRoute + assign ifcs_0_1_innerRoute$D_IN = + { (cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412) && + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415 && + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416, + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 && + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412, + (cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412) && + (cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416) } ; + assign ifcs_0_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit ; + assign ifcs_0_1_innerRoute$DEQ = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_5 ; + assign ifcs_0_1_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_0_1_noRouteRsp + assign ifcs_0_1_noRouteRsp$D_IN = + { ifcs_0_1_noRoute_currentReq$port1__read[96:93], + 66'h2AAAAAAAAAAAAAAAB, + x_port1__read__h55959 == 9'd1 } ; + assign ifcs_0_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; + assign ifcs_0_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign ifcs_0_1_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_0_1_routeBack + assign ifcs_0_1_routeBack$D_IN = 2'd1 << shim_rff$D_OUT[71] ; + assign ifcs_0_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; + assign ifcs_0_1_routeBack$DEQ = + WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_rspBack$D_OUT[0] ; + assign ifcs_0_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_0_1_rspBack + assign ifcs_0_1_rspBack$D_IN = shim_rff$D_OUT[70:0] ; + assign ifcs_0_1_rspBack$ENQ = ssNoSynth_0_r_dwReady$whas ; + assign ifcs_0_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_7 ; + assign ifcs_0_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_0_innerReq + assign ifcs_0_innerReq$D_IN = + { merged_0_flitLeft != 8'd0, + a_awid__h21643, + cpu$dmem_master_awaddr, + cpu$dmem_master_awlen, + cpu$dmem_master_awsize, + cpu$dmem_master_awburst, + cpu$dmem_master_awlock, + cpu$dmem_master_awcache, + cpu$dmem_master_awprot, + cpu$dmem_master_awqos, + cpu$dmem_master_awregion, + cpu$dmem_master_wdata, + cpu$dmem_master_wstrb, + cpu$dmem_master_wlast } ; + assign ifcs_0_innerReq$ENQ = + WILL_FIRE_RL_ifcs_0_followFlits || + WILL_FIRE_RL_ifcs_0_firstFlit ; + assign ifcs_0_innerReq$DEQ = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst ; + assign ifcs_0_innerReq$CLR = 1'b0 ; + + // submodule ifcs_0_innerRoute + assign ifcs_0_innerRoute$D_IN = + { (IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771) && + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774 && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775, + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771, + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771) && + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775) } ; + assign ifcs_0_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit ; + assign ifcs_0_innerRoute$DEQ = + WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerReq$D_OUT[0] ; + assign ifcs_0_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_0_noRouteRsp + assign ifcs_0_noRouteRsp$D_IN = + { ifcs_0_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; + assign ifcs_0_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; + assign ifcs_0_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign ifcs_0_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_0_routeBack + assign ifcs_0_routeBack$D_IN = 2'd1 << shim_bff$D_OUT[6] ; + assign ifcs_0_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; + assign ifcs_0_routeBack$DEQ = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_2 ; + assign ifcs_0_routeBack$CLR = 1'b0 ; + + // submodule ifcs_0_rspBack + assign ifcs_0_rspBack$D_IN = shim_bff$D_OUT[5:0] ; + assign ifcs_0_rspBack$ENQ = ssNoSynth_0_b_dwReady$whas ; + assign ifcs_0_rspBack$DEQ = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_2 ; + assign ifcs_0_rspBack$CLR = 1'b0 ; + + // submodule ifcs_1_1_innerReq + assign ifcs_1_1_innerReq$D_IN = + { fatReq_arid__h57824, + dm_mem_tap$master_araddr, + dm_mem_tap$master_arlen, + dm_mem_tap$master_arsize, + dm_mem_tap$master_arburst, + dm_mem_tap$master_arlock, + dm_mem_tap$master_arcache, + dm_mem_tap$master_arprot, + dm_mem_tap$master_arqos, + dm_mem_tap$master_arregion } ; + assign ifcs_1_1_innerReq$ENQ = + WILL_FIRE_RL_ifcs_1_1_followFlits || + WILL_FIRE_RL_ifcs_1_1_firstFlit ; + assign ifcs_1_1_innerReq$DEQ = + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_6 ; + assign ifcs_1_1_innerReq$CLR = 1'b0 ; + + // submodule ifcs_1_1_innerRoute + assign ifcs_1_1_innerRoute$D_IN = + { (dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498) && + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501 && + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502, + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 && + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498, + (dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498) && + (dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502) } ; + assign ifcs_1_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit ; + assign ifcs_1_1_innerRoute$DEQ = + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_6 ; + assign ifcs_1_1_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_1_1_noRouteRsp + assign ifcs_1_1_noRouteRsp$D_IN = + { ifcs_1_1_noRoute_currentReq$port1__read[96:93], + 66'h2AAAAAAAAAAAAAAAB, + x_port1__read__h58381 == 9'd1 } ; + assign ifcs_1_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; + assign ifcs_1_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + assign ifcs_1_1_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_1_1_routeBack + assign ifcs_1_1_routeBack$D_IN = 2'd1 << near_mem_io$axi4_slave_rid[4] ; + assign ifcs_1_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; + assign ifcs_1_1_routeBack$DEQ = + WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_rspBack$D_OUT[0] ; + assign ifcs_1_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_1_1_rspBack + assign ifcs_1_1_rspBack$D_IN = + { near_mem_io$axi4_slave_rid[3:0], + near_mem_io$axi4_slave_rdata, + near_mem_io$axi4_slave_rresp, + near_mem_io$axi4_slave_rlast } ; + assign ifcs_1_1_rspBack$ENQ = ssNoSynth_1_r_dwReady$whas ; + assign ifcs_1_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_8 ; + assign ifcs_1_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_1_innerReq + assign ifcs_1_innerReq$D_IN = + { merged_1_flitLeft != 8'd0, + a_awid__h24357, + dm_mem_tap$master_awaddr, + dm_mem_tap$master_awlen, + dm_mem_tap$master_awsize, + dm_mem_tap$master_awburst, + dm_mem_tap$master_awlock, + dm_mem_tap$master_awcache, + dm_mem_tap$master_awprot, + dm_mem_tap$master_awqos, + dm_mem_tap$master_awregion, + dm_mem_tap$master_wdata, + dm_mem_tap$master_wstrb, + dm_mem_tap$master_wlast } ; + assign ifcs_1_innerReq$ENQ = + WILL_FIRE_RL_ifcs_1_followFlits || + WILL_FIRE_RL_ifcs_1_firstFlit ; + assign ifcs_1_innerReq$DEQ = + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_1 ; + assign ifcs_1_innerReq$CLR = 1'b0 ; + + // submodule ifcs_1_innerRoute + assign ifcs_1_innerRoute$D_IN = + { (IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868) && + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871 && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872, + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868, + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868) && + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872) } ; + assign ifcs_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit ; + assign ifcs_1_innerRoute$DEQ = + WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerReq$D_OUT[0] ; + assign ifcs_1_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_1_noRouteRsp + assign ifcs_1_noRouteRsp$D_IN = + { ifcs_1_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; + assign ifcs_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; + assign ifcs_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + assign ifcs_1_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_1_routeBack + assign ifcs_1_routeBack$D_IN = 2'd1 << near_mem_io$axi4_slave_bid[4] ; + assign ifcs_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; + assign ifcs_1_routeBack$DEQ = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_3 ; + assign ifcs_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_1_rspBack + assign ifcs_1_rspBack$D_IN = + { near_mem_io$axi4_slave_bid[3:0], + near_mem_io$axi4_slave_bresp } ; + assign ifcs_1_rspBack$ENQ = ssNoSynth_1_b_dwReady$whas ; + assign ifcs_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_3 ; + assign ifcs_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_2_1_routeBack + assign ifcs_2_1_routeBack$D_IN = 2'd1 << plic$axi4_slave_rid[4] ; + assign ifcs_2_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_1_firstFlit ; + assign ifcs_2_1_routeBack$DEQ = + WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_rspBack$D_OUT[0] ; + assign ifcs_2_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_2_1_rspBack + assign ifcs_2_1_rspBack$D_IN = + { plic$axi4_slave_rid[3:0], + plic$axi4_slave_rdata, + plic$axi4_slave_rresp, + plic$axi4_slave_rlast } ; + assign ifcs_2_1_rspBack$ENQ = ssNoSynth_2_r_dwReady$whas ; + assign ifcs_2_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_9 ; + assign ifcs_2_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_2_routeBack + assign ifcs_2_routeBack$D_IN = 2'd1 << plic$axi4_slave_bid[4] ; + assign ifcs_2_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_firstFlit ; + assign ifcs_2_routeBack$DEQ = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_4 ; + assign ifcs_2_routeBack$CLR = 1'b0 ; + + // submodule ifcs_2_rspBack + assign ifcs_2_rspBack$D_IN = + { plic$axi4_slave_bid[3:0], plic$axi4_slave_bresp } ; + assign ifcs_2_rspBack$ENQ = ssNoSynth_2_b_dwReady$whas ; + assign ifcs_2_rspBack$DEQ = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_4 ; + assign ifcs_2_rspBack$CLR = 1'b0 ; + + // submodule msNoSynth_0_b_buffer_ff + assign msNoSynth_0_b_buffer_ff$D_IN = msNoSynth_0_b_buffer_enqw$wget ; + assign msNoSynth_0_b_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; + assign msNoSynth_0_b_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; + assign msNoSynth_0_b_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_b_buffer_firstValid + assign msNoSynth_0_b_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_b_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; + + // submodule msNoSynth_0_r_buffer_ff + assign msNoSynth_0_r_buffer_ff$D_IN = msNoSynth_0_r_buffer_enqw$wget ; + assign msNoSynth_0_r_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; + assign msNoSynth_0_r_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; + assign msNoSynth_0_r_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_r_buffer_firstValid + assign msNoSynth_0_r_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_r_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; + + // submodule msNoSynth_1_b_buffer_ff + assign msNoSynth_1_b_buffer_ff$D_IN = msNoSynth_1_b_buffer_enqw$wget ; + assign msNoSynth_1_b_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; + assign msNoSynth_1_b_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; + assign msNoSynth_1_b_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_b_buffer_firstValid + assign msNoSynth_1_b_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_b_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; + + // submodule msNoSynth_1_r_buffer_ff + assign msNoSynth_1_r_buffer_ff$D_IN = msNoSynth_1_r_buffer_enqw$wget ; + assign msNoSynth_1_r_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; + assign msNoSynth_1_r_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; + assign msNoSynth_1_r_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_r_buffer_firstValid + assign msNoSynth_1_r_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_r_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; // submodule near_mem_io - assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; + assign near_mem_io$axi4_slave_araddr = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[92:29] : + ssNoSynth_1_ar_buffer_enqw$wget[92:29] ; + assign near_mem_io$axi4_slave_arburst = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[17:16] : + ssNoSynth_1_ar_buffer_enqw$wget[17:16] ; + assign near_mem_io$axi4_slave_arcache = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[14:11] : + ssNoSynth_1_ar_buffer_enqw$wget[14:11] ; + assign near_mem_io$axi4_slave_arid = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[97:93] : + ssNoSynth_1_ar_buffer_enqw$wget[97:93] ; + assign near_mem_io$axi4_slave_arlen = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[28:21] : + ssNoSynth_1_ar_buffer_enqw$wget[28:21] ; + assign near_mem_io$axi4_slave_arlock = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[15] : + ssNoSynth_1_ar_buffer_enqw$wget[15] ; + assign near_mem_io$axi4_slave_arprot = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[10:8] : + ssNoSynth_1_ar_buffer_enqw$wget[10:8] ; + assign near_mem_io$axi4_slave_arqos = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[7:4] : + ssNoSynth_1_ar_buffer_enqw$wget[7:4] ; + assign near_mem_io$axi4_slave_arregion = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[3:0] : + ssNoSynth_1_ar_buffer_enqw$wget[3:0] ; + assign near_mem_io$axi4_slave_arsize = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[20:18] : + ssNoSynth_1_ar_buffer_enqw$wget[20:18] ; + assign near_mem_io$axi4_slave_awaddr = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[92:29] : + ssNoSynth_1_aw_buffer_enqw$wget[92:29] ; + assign near_mem_io$axi4_slave_awburst = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[17:16] : + ssNoSynth_1_aw_buffer_enqw$wget[17:16] ; + assign near_mem_io$axi4_slave_awcache = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[14:11] : + ssNoSynth_1_aw_buffer_enqw$wget[14:11] ; + assign near_mem_io$axi4_slave_awid = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[97:93] : + ssNoSynth_1_aw_buffer_enqw$wget[97:93] ; + assign near_mem_io$axi4_slave_awlen = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[28:21] : + ssNoSynth_1_aw_buffer_enqw$wget[28:21] ; + assign near_mem_io$axi4_slave_awlock = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[15] : + ssNoSynth_1_aw_buffer_enqw$wget[15] ; + assign near_mem_io$axi4_slave_awprot = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[10:8] : + ssNoSynth_1_aw_buffer_enqw$wget[10:8] ; + assign near_mem_io$axi4_slave_awqos = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[7:4] : + ssNoSynth_1_aw_buffer_enqw$wget[7:4] ; + assign near_mem_io$axi4_slave_awregion = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[3:0] : + ssNoSynth_1_aw_buffer_enqw$wget[3:0] ; + assign near_mem_io$axi4_slave_awsize = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[20:18] : + ssNoSynth_1_aw_buffer_enqw$wget[20:18] ; + assign near_mem_io$axi4_slave_bready = ssNoSynth_1_b_dwReady$whas ; + assign near_mem_io$axi4_slave_rready = ssNoSynth_1_r_dwReady$whas ; + assign near_mem_io$axi4_slave_wdata = + ssNoSynth_1_w_buffer_ff$EMPTY_N ? + ssNoSynth_1_w_buffer_ff$D_OUT[72:9] : + ssNoSynth_1_w_buffer_enqw$wget[72:9] ; + assign near_mem_io$axi4_slave_wlast = + ssNoSynth_1_w_buffer_ff$EMPTY_N ? + ssNoSynth_1_w_buffer_ff$D_OUT[0] : + ssNoSynth_1_w_buffer_enqw$wget[0] ; + assign near_mem_io$axi4_slave_wstrb = + ssNoSynth_1_w_buffer_ff$EMPTY_N ? + ssNoSynth_1_w_buffer_ff$D_OUT[8:1] : + ssNoSynth_1_w_buffer_enqw$wget[8:1] ; assign near_mem_io$set_addr_map_addr_base = - soc_map$m_near_mem_io_addr_base ; - assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; + soc_map$m_near_mem_io_addr_range[127:64] ; + assign near_mem_io$set_addr_map_addr_lim = y__h20569 ; assign near_mem_io$EN_server_reset_request_put = WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; @@ -3385,42 +7500,114 @@ module mkCore(CLK, CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign near_mem_io$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign near_mem_io$axi4_slave_awvalid = + CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; + assign near_mem_io$axi4_slave_wvalid = + CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; + assign near_mem_io$axi4_slave_arvalid = + CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; assign near_mem_io$EN_get_timer_interrupt_req_get = near_mem_io$RDY_get_timer_interrupt_req_get ; assign near_mem_io$EN_get_sw_interrupt_req_get = near_mem_io$RDY_get_sw_interrupt_req_get ; // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; + assign plic$axi4_slave_araddr = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[92:29] : + ssNoSynth_2_ar_buffer_enqw$wget[92:29] ; + assign plic$axi4_slave_arburst = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[17:16] : + ssNoSynth_2_ar_buffer_enqw$wget[17:16] ; + assign plic$axi4_slave_arcache = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[14:11] : + ssNoSynth_2_ar_buffer_enqw$wget[14:11] ; + assign plic$axi4_slave_arid = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[97:93] : + ssNoSynth_2_ar_buffer_enqw$wget[97:93] ; + assign plic$axi4_slave_arlen = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[28:21] : + ssNoSynth_2_ar_buffer_enqw$wget[28:21] ; + assign plic$axi4_slave_arlock = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[15] : + ssNoSynth_2_ar_buffer_enqw$wget[15] ; + assign plic$axi4_slave_arprot = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[10:8] : + ssNoSynth_2_ar_buffer_enqw$wget[10:8] ; + assign plic$axi4_slave_arqos = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[7:4] : + ssNoSynth_2_ar_buffer_enqw$wget[7:4] ; + assign plic$axi4_slave_arregion = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[3:0] : + ssNoSynth_2_ar_buffer_enqw$wget[3:0] ; + assign plic$axi4_slave_arsize = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[20:18] : + ssNoSynth_2_ar_buffer_enqw$wget[20:18] ; + assign plic$axi4_slave_awaddr = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[92:29] : + ssNoSynth_2_aw_buffer_enqw$wget[92:29] ; + assign plic$axi4_slave_awburst = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[17:16] : + ssNoSynth_2_aw_buffer_enqw$wget[17:16] ; + assign plic$axi4_slave_awcache = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[14:11] : + ssNoSynth_2_aw_buffer_enqw$wget[14:11] ; + assign plic$axi4_slave_awid = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[97:93] : + ssNoSynth_2_aw_buffer_enqw$wget[97:93] ; + assign plic$axi4_slave_awlen = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[28:21] : + ssNoSynth_2_aw_buffer_enqw$wget[28:21] ; + assign plic$axi4_slave_awlock = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[15] : + ssNoSynth_2_aw_buffer_enqw$wget[15] ; + assign plic$axi4_slave_awprot = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[10:8] : + ssNoSynth_2_aw_buffer_enqw$wget[10:8] ; + assign plic$axi4_slave_awqos = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[7:4] : + ssNoSynth_2_aw_buffer_enqw$wget[7:4] ; + assign plic$axi4_slave_awregion = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[3:0] : + ssNoSynth_2_aw_buffer_enqw$wget[3:0] ; + assign plic$axi4_slave_awsize = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[20:18] : + ssNoSynth_2_aw_buffer_enqw$wget[20:18] ; + assign plic$axi4_slave_bready = ssNoSynth_2_b_dwReady$whas ; + assign plic$axi4_slave_rready = ssNoSynth_2_r_dwReady$whas ; + assign plic$axi4_slave_wdata = + ssNoSynth_2_w_buffer_ff$EMPTY_N ? + ssNoSynth_2_w_buffer_ff$D_OUT[72:9] : + ssNoSynth_2_w_buffer_enqw$wget[72:9] ; + assign plic$axi4_slave_wlast = + ssNoSynth_2_w_buffer_ff$EMPTY_N ? + ssNoSynth_2_w_buffer_ff$D_OUT[0] : + ssNoSynth_2_w_buffer_enqw$wget[0] ; + assign plic$axi4_slave_wstrb = + ssNoSynth_2_w_buffer_ff$EMPTY_N ? + ssNoSynth_2_w_buffer_ff$D_OUT[8:1] : + ssNoSynth_2_w_buffer_enqw$wget[8:1] ; + assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_range[127:64] ; + assign plic$set_addr_map_addr_lim = y__h20593 ; assign plic$set_verbosity_verbosity = 4'h0 ; assign plic$v_sources_0_m_interrupt_req_set_not_clear = core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; @@ -3462,12 +7649,178 @@ module mkCore(CLK, assign plic$EN_server_reset_response_get = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign plic$axi4_slave_awvalid = CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; + assign plic$axi4_slave_wvalid = CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; + assign plic$axi4_slave_arvalid = CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; + + // submodule shim_arff + assign shim_arff$D_IN = + ssNoSynth_0_ar_buffer_ff$EMPTY_N ? + ssNoSynth_0_ar_buffer_ff$D_OUT : + ssNoSynth_0_ar_buffer_enqw$wget ; + assign shim_arff$ENQ = + WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit && shim_arff$FULL_N ; + assign shim_arff$DEQ = shim_arff$EMPTY_N && cpu_dmem_master_arready ; + assign shim_arff$CLR = 1'b0 ; + + // submodule shim_awff + assign shim_awff$D_IN = + ssNoSynth_0_aw_buffer_ff$EMPTY_N ? + ssNoSynth_0_aw_buffer_ff$D_OUT : + split_0_doPut$wget[170:73] ; + assign shim_awff$ENQ = + WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit && shim_awff$FULL_N ; + assign shim_awff$DEQ = shim_awff$EMPTY_N && cpu_dmem_master_awready ; + assign shim_awff$CLR = 1'b0 ; + + // submodule shim_bff + assign shim_bff$D_IN = { cpu_dmem_master_bid, cpu_dmem_master_bresp } ; + assign shim_bff$ENQ = cpu_dmem_master_bvalid && shim_bff$FULL_N ; + assign shim_bff$DEQ = shim_bff$EMPTY_N && ssNoSynth_0_b_dwReady$whas ; + assign shim_bff$CLR = 1'b0 ; + + // submodule shim_rff + assign shim_rff$D_IN = + { cpu_dmem_master_rid, + cpu_dmem_master_rdata, + cpu_dmem_master_rresp, + cpu_dmem_master_rlast } ; + assign shim_rff$ENQ = cpu_dmem_master_rvalid && shim_rff$FULL_N ; + assign shim_rff$DEQ = shim_rff$EMPTY_N && ssNoSynth_0_r_dwReady$whas ; + assign shim_rff$CLR = 1'b0 ; + + // submodule shim_wff + assign shim_wff$D_IN = + ssNoSynth_0_w_buffer_ff$EMPTY_N ? + ssNoSynth_0_w_buffer_ff$D_OUT : + split_0_doPut$wget[72:0] ; + assign shim_wff$ENQ = + WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit && shim_wff$FULL_N ; + assign shim_wff$DEQ = shim_wff$EMPTY_N && cpu_dmem_master_wready ; + assign shim_wff$CLR = 1'b0 ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; + // submodule ssNoSynth_0_ar_buffer_ff + assign ssNoSynth_0_ar_buffer_ff$D_IN = ssNoSynth_0_ar_buffer_enqw$wget ; + assign ssNoSynth_0_ar_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; + assign ssNoSynth_0_ar_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; + assign ssNoSynth_0_ar_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_0_ar_buffer_firstValid + assign ssNoSynth_0_ar_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_ar_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit ; + + // submodule ssNoSynth_0_aw_buffer_ff + assign ssNoSynth_0_aw_buffer_ff$D_IN = split_0_doPut$wget[170:73] ; + assign ssNoSynth_0_aw_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; + assign ssNoSynth_0_aw_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; + assign ssNoSynth_0_aw_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_0_aw_buffer_firstValid + assign ssNoSynth_0_aw_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_aw_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit ; + + // submodule ssNoSynth_0_w_buffer_ff + assign ssNoSynth_0_w_buffer_ff$D_IN = split_0_doPut$wget[72:0] ; + assign ssNoSynth_0_w_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; + assign ssNoSynth_0_w_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; + assign ssNoSynth_0_w_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_0_w_buffer_firstValid + assign ssNoSynth_0_w_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_w_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_w_dropFlit ; + + // submodule ssNoSynth_1_ar_buffer_ff + assign ssNoSynth_1_ar_buffer_ff$D_IN = ssNoSynth_1_ar_buffer_enqw$wget ; + assign ssNoSynth_1_ar_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; + assign ssNoSynth_1_ar_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; + assign ssNoSynth_1_ar_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_ar_buffer_firstValid + assign ssNoSynth_1_ar_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_ar_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + + // submodule ssNoSynth_1_aw_buffer_ff + assign ssNoSynth_1_aw_buffer_ff$D_IN = split_1_doPut$wget[170:73] ; + assign ssNoSynth_1_aw_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; + assign ssNoSynth_1_aw_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; + assign ssNoSynth_1_aw_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_aw_buffer_firstValid + assign ssNoSynth_1_aw_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_aw_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + + // submodule ssNoSynth_1_w_buffer_ff + assign ssNoSynth_1_w_buffer_ff$D_IN = split_1_doPut$wget[72:0] ; + assign ssNoSynth_1_w_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; + assign ssNoSynth_1_w_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; + assign ssNoSynth_1_w_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_w_buffer_firstValid + assign ssNoSynth_1_w_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_w_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + + // submodule ssNoSynth_2_ar_buffer_ff + assign ssNoSynth_2_ar_buffer_ff$D_IN = ssNoSynth_2_ar_buffer_enqw$wget ; + assign ssNoSynth_2_ar_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; + assign ssNoSynth_2_ar_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; + assign ssNoSynth_2_ar_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_ar_buffer_firstValid + assign ssNoSynth_2_ar_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_ar_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + + // submodule ssNoSynth_2_aw_buffer_ff + assign ssNoSynth_2_aw_buffer_ff$D_IN = split_2_doPut$wget[170:73] ; + assign ssNoSynth_2_aw_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; + assign ssNoSynth_2_aw_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; + assign ssNoSynth_2_aw_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_aw_buffer_firstValid + assign ssNoSynth_2_aw_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_aw_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + + // submodule ssNoSynth_2_w_buffer_ff + assign ssNoSynth_2_w_buffer_ff$D_IN = split_2_doPut$wget[72:0] ; + assign ssNoSynth_2_w_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; + assign ssNoSynth_2_w_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; + assign ssNoSynth_2_w_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_w_buffer_firstValid + assign ssNoSynth_2_w_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_w_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + // submodule tv_encode assign tv_encode$trace_data_in_put = f_trace_data_merged$D_OUT ; assign tv_encode$EN_reset = 1'b0 ; @@ -3475,10 +7828,786 @@ module mkCore(CLK, assign tv_encode$EN_tv_vb_out_get = EN_tv_verifier_info_get_get ; // remaining internal signals - assign fabric_2x3_RDY_reset_AND_cpu_RDY_hart0_server__ETC___d9 = - fabric_2x3$RDY_reset && cpu$RDY_hart0_server_reset_request_put && + assign IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d779 = + ((IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771) && + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775)) ? + 2'd1 : + 2'd0 ; + assign IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d783 = + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d779 + + ((!IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771) ? + 2'd1 : + 2'd0) ; + assign IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d787 = + ((IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771) && + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774 && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775) ? + 2'd1 : + 2'd0 ; + assign IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d876 = + ((IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868) && + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872)) ? + 2'd1 : + 2'd0 ; + assign IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d880 = + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d876 + + ((!IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868) ? + 2'd1 : + 2'd0) ; + assign IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d884 = + ((IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868) && + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871 && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872) ? + 2'd1 : + 2'd0 ; + assign IF_NOT_ifcs_0_1_innerRoute_first__638_BIT_1_64_ETC___d1660 = + (!ifcs_0_1_innerRoute$D_OUT[1] || + !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + ifcs_0_1_innerRoute$D_OUT[2] && + ssNoSynth_2_ar_buffer_ff$FULL_N : + ifcs_0_1_innerRoute$D_OUT[1] ; + assign IF_NOT_ifcs_0_innerRoute_first__000_BIT_1_009__ETC___d1022 = + (!ifcs_0_innerRoute$D_OUT[1] || + !IF_split_1_flitLeft_03_EQ_0_04_THEN_ssNoSynth__ETC___d993) ? + ifcs_0_innerRoute$D_OUT[2] && + IF_split_2_flitLeft_32_EQ_0_33_THEN_ssNoSynth__ETC___d994 : + ifcs_0_innerRoute$D_OUT[1] ; + assign IF_NOT_ifcs_1_1_innerRoute_first__667_BIT_1_67_ETC___d1676 = + (!ifcs_1_1_innerRoute$D_OUT[1] || + !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + ifcs_1_1_innerRoute$D_OUT[2] && + ssNoSynth_2_ar_buffer_ff$FULL_N : + ifcs_1_1_innerRoute$D_OUT[1] ; + assign IF_NOT_ifcs_1_innerRoute_first__029_BIT_1_033__ETC___d1038 = + (!ifcs_1_innerRoute$D_OUT[1] || + !IF_split_1_flitLeft_03_EQ_0_04_THEN_ssNoSynth__ETC___d993) ? + ifcs_1_innerRoute$D_OUT[2] && + IF_split_2_flitLeft_32_EQ_0_33_THEN_ssNoSynth__ETC___d994 : + ifcs_1_innerRoute$D_OUT[1] ; + assign IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1912 = + (SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 || + SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 || + SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893) ? + x__h77916 | y__h77917 : + arbiter_1_1_lastSelect ; + assign IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1918 = + (SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 || + SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 || + SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893) ? + x__h78104 | y__h78105 : + arbiter_1_1_lastSelect_1 ; + assign IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1924 = + (SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 || + SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 || + SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893) ? + x__h78285 | y__h78286 : + arbiter_1_1_firstHot ; + assign IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1284 = + (SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 || + SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 || + SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265) ? + x__h46617 | y__h46618 : + arbiter_1_lastSelect ; + assign IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1290 = + (SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 || + SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 || + SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265) ? + x__h46805 | y__h46806 : + arbiter_1_lastSelect_1 ; + assign IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1296 = + (SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 || + SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 || + SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265) ? + x__h46986 | y__h46987 : + arbiter_1_firstHot ; + assign IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1712 = + (SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 || + SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700) ? + x__h65974 | y__h65975 : + arbiter_1_lastSelect_2 ; + assign IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1716 = + (SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 || + SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700) ? + x__h66115 | y__h66116 : + arbiter_1_firstHot_1 ; + assign IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1074 = + (SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 || + SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062) ? + x__h32134 | y__h32135 : + arbiter_lastSelect ; + assign IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1078 = + (SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 || + SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062) ? + x__h32275 | y__h32276 : + arbiter_firstHot ; + assign IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1420 = + ((cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412) && + (cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416)) ? + 2'd1 : + 2'd0 ; + assign IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1424 = + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1420 + + ((!cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 && + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412) ? + 2'd1 : + 2'd0) ; + assign IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1428 = + ((cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412) && + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415 && + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416) ? + 2'd1 : + 2'd0 ; + assign IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1506 = + ((dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498) && + (dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502)) ? + 2'd1 : + 2'd0 ; + assign IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1510 = + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1506 + + ((!dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 && + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498) ? + 2'd1 : + 2'd0) ; + assign IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1514 = + ((dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498) && + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501 && + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502) ? + 2'd1 : + 2'd0 ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d760 = + ((merged_0_flitLeft == 8'd0) ? + !cpu$dmem_master_awvalid || !cpu$dmem_master_wvalid : + !cpu$dmem_master_wvalid) || + merged_0_flitLeft != 8'd0 ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d821 = + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d760 || + cpu$dmem_master_awvalid) && + (merged_0_flitLeft != 8'd0 || + !ifcs_0_noRoute_inner_pendingReq && cpu$dmem_master_awvalid) ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 = + (merged_0_flitLeft == 8'd0) ? + cpu$dmem_master_awvalid && cpu$dmem_master_wvalid : + cpu$dmem_master_wvalid ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 = + cpu$dmem_master_awaddr < + soc_map$m_near_mem_io_addr_range[127:64] ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771 = + cpu$dmem_master_awaddr < y__h20569 ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774 = + cpu$dmem_master_awaddr < soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775 = + cpu$dmem_master_awaddr < y__h20593 ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d857 = + ((merged_1_flitLeft == 8'd0) ? + !dm_mem_tap$master_awvalid || !dm_mem_tap$master_wvalid : + !dm_mem_tap$master_wvalid) || + merged_1_flitLeft != 8'd0 ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d918 = + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d857 || + dm_mem_tap$master_awvalid) && + (merged_1_flitLeft != 8'd0 || + !ifcs_1_noRoute_inner_pendingReq && dm_mem_tap$master_awvalid) ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 = + (merged_1_flitLeft == 8'd0) ? + dm_mem_tap$master_awvalid && dm_mem_tap$master_wvalid : + dm_mem_tap$master_wvalid ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 = + dm_mem_tap$master_awaddr < + soc_map$m_near_mem_io_addr_range[127:64] ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868 = + dm_mem_tap$master_awaddr < y__h20569 ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871 = + dm_mem_tap$master_awaddr < soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872 = + dm_mem_tap$master_awaddr < y__h20593 ; + assign IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992 = + (split_0_flitLeft == 8'd0) ? + ssNoSynth_0_aw_buffer_ff$FULL_N && + ssNoSynth_0_w_buffer_ff$FULL_N : + ssNoSynth_0_w_buffer_ff$FULL_N ; + assign IF_split_1_flitLeft_03_EQ_0_04_THEN_ssNoSynth__ETC___d993 = + (split_1_flitLeft == 8'd0) ? + ssNoSynth_1_aw_buffer_ff$FULL_N && + ssNoSynth_1_w_buffer_ff$FULL_N : + ssNoSynth_1_w_buffer_ff$FULL_N ; + assign IF_split_2_flitLeft_32_EQ_0_33_THEN_ssNoSynth__ETC___d994 = + (split_2_flitLeft == 8'd0) ? + ssNoSynth_2_aw_buffer_ff$FULL_N && + ssNoSynth_2_w_buffer_ff$FULL_N : + ssNoSynth_2_w_buffer_ff$FULL_N ; + assign SEXT_SEXT_arbiter_1_1_firstHot_877_878_BIT_0_8_ETC__q18 = + {2{SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893}} ; + assign SEXT_SEXT_arbiter_1_firstHot_1_692_693_BIT_0_6_ETC__q13 = + {2{SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700}} ; + assign SEXT_SEXT_arbiter_1_firstHot_249_250_BIT_0_251_ETC__q8 = + {2{SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265}} ; + assign SEXT_SEXT_arbiter_firstHot_054_055_BIT_0_056_A_ETC__q3 = + {2{SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062}} ; + assign SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893 = + x__h77444 | y__h77445 ; + assign SEXT_arbiter_1_1_firstHot__q15 = {2{arbiter_1_1_firstHot}} ; + assign SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 = + x__h77308 | y__h77309 ; + assign SEXT_arbiter_1_1_lastSelect_1__q17 = {2{arbiter_1_1_lastSelect_1}} ; + assign SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 = + x__h77157 | y__h77158 ; + assign SEXT_arbiter_1_1_lastSelect__q16 = {2{arbiter_1_1_lastSelect}} ; + assign SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700 = + x__h65609 | y__h65610 ; + assign SEXT_arbiter_1_firstHot_1__q11 = {2{arbiter_1_firstHot_1}} ; + assign SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265 = + x__h46145 | y__h46146 ; + assign SEXT_arbiter_1_firstHot__q5 = {2{arbiter_1_firstHot}} ; + assign SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 = + x__h46009 | y__h46010 ; + assign SEXT_arbiter_1_lastSelect_1__q7 = {2{arbiter_1_lastSelect_1}} ; + assign SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 = + x__h45858 | y__h45859 ; + assign SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 = + x__h65506 | y__h65507 ; + assign SEXT_arbiter_1_lastSelect_2__q12 = {2{arbiter_1_lastSelect_2}} ; + assign SEXT_arbiter_1_lastSelect__q6 = {2{arbiter_1_lastSelect}} ; + assign SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062 = + x__h31769 | y__h31770 ; + assign SEXT_arbiter_firstHot__q1 = {2{arbiter_firstHot}} ; + assign SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 = + x__h31666 | y__h31667 ; + assign SEXT_arbiter_lastSelect__q2 = {2{arbiter_lastSelect}} ; + assign SEXT_x2193__q4 = {2{x__h32193}} ; + assign SEXT_x6033__q14 = {2{x__h66033}} ; + assign SEXT_x6679__q9 = {2{x__h46679}} ; + assign SEXT_x6713__q10 = {2{x__h46713}} ; + assign SEXT_x7978__q19 = {2{x__h77978}} ; + assign SEXT_x8012__q20 = {2{x__h78012}} ; + assign a_awid__h21643 = { 1'd0, cpu$dmem_master_awid } ; + assign a_awid__h24357 = { 1'd1, dm_mem_tap$master_awid } ; + assign cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 = + cpu$dmem_master_araddr < + soc_map$m_near_mem_io_addr_range[127:64] ; + assign cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412 = + cpu$dmem_master_araddr < y__h20569 ; + assign cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415 = + cpu$dmem_master_araddr < soc_map$m_plic_addr_range[127:64] ; + assign cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416 = + cpu$dmem_master_araddr < y__h20593 ; + assign dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 = + dm_mem_tap$master_araddr < + soc_map$m_near_mem_io_addr_range[127:64] ; + assign dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498 = + dm_mem_tap$master_araddr < y__h20569 ; + assign dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501 = + dm_mem_tap$master_araddr < soc_map$m_plic_addr_range[127:64] ; + assign dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502 = + dm_mem_tap$master_araddr < y__h20593 ; + assign fatReq_arid__h55399 = { 1'd0, cpu$dmem_master_arid } ; + assign fatReq_arid__h57824 = { 1'd1, dm_mem_tap$master_arid } ; + assign plic_RDY_server_reset_request_put_AND_cpu_RDY__ETC___d8 = + plic$RDY_server_reset_request_put && + cpu$RDY_hart0_server_reset_request_put && f_reset_reqs$EMPTY_N && f_reset_requestor$FULL_N ; + assign reqWires_1_0_whas__226_AND_reqWires_1_0_wget___ETC___d1236 = + CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget || + CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget || + CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget ; + assign reqWires_1_1_0_whas__854_AND_reqWires_1_1_0_wg_ETC___d1864 = + CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget || + CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget || + CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget ; + assign split_0_doPut_whas__66_AND_split_0_doPut_wget__ETC___d673 = + CAN_FIRE_RL_sink_selected && + (split_0_doPut$wget[171] || + ssNoSynth_0_aw_buffer_ff$FULL_N && + ssNoSynth_0_w_buffer_ff$FULL_N) ; + assign split_1_doPut_whas__95_AND_split_1_doPut_wget__ETC___d702 = + CAN_FIRE_RL_sink_selected_1 && + (split_1_doPut$wget[171] || + ssNoSynth_1_aw_buffer_ff$FULL_N && + ssNoSynth_1_w_buffer_ff$FULL_N) ; + assign split_2_doPut_whas__24_AND_split_2_doPut_wget__ETC___d731 = + CAN_FIRE_RL_sink_selected_2 && + (split_2_doPut$wget[171] || + ssNoSynth_2_aw_buffer_ff$FULL_N && + ssNoSynth_2_w_buffer_ff$FULL_N) ; + assign state_047_AND_activeSource_0_120_121_AND_ifcs__ETC___d1123 = + state && activeSource_0 && ifcs_0_innerRoute$EMPTY_N && + ((!ifcs_0_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992) ? + IF_NOT_ifcs_0_innerRoute_first__000_BIT_1_009__ETC___d1022 : + ifcs_0_innerRoute$D_OUT[0]) ; + assign state_047_AND_activeSource_1_164_165_AND_ifcs__ETC___d1167 = + state && activeSource_1 && ifcs_1_innerRoute$EMPTY_N && + ((!ifcs_1_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992) ? + IF_NOT_ifcs_1_innerRoute_first__029_BIT_1_033__ETC___d1038 : + ifcs_1_innerRoute$D_OUT[0]) ; + assign state_1_1_1_865_AND_activeSource_1_1_0_959_960_ETC___d1962 = + state_1_1_1 && activeSource_1_1_0 && + ifcs_0_1_routeBack$EMPTY_N && + ((!ifcs_0_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_0_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_0_1_routeBack$D_OUT[0]) ; + assign state_1_1_1_865_AND_activeSource_1_1_1_1_995_9_ETC___d1998 = + state_1_1_1 && activeSource_1_1_1_1 && + ifcs_1_1_routeBack$EMPTY_N && + ((!ifcs_1_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_1_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_1_1_routeBack$D_OUT[0]) ; + assign state_1_1_1_865_AND_activeSource_1_1_2_031_032_ETC___d2034 = + state_1_1_1 && activeSource_1_1_2 && + ifcs_2_1_routeBack$EMPTY_N && + ((!ifcs_2_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_2_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_2_1_routeBack$D_OUT[0]) ; + assign state_1_1_685_AND_activeSource_1_0_1_752_753_A_ETC___d1755 = + state_1_1 && activeSource_1_0_1 && ifcs_0_1_innerRoute$EMPTY_N && + ((!ifcs_0_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__638_BIT_1_64_ETC___d1660 : + ifcs_0_1_innerRoute$D_OUT[0]) ; + assign state_1_1_685_AND_activeSource_1_1_1_792_793_A_ETC___d1795 = + state_1_1 && activeSource_1_1_1 && ifcs_1_1_innerRoute$EMPTY_N && + ((!ifcs_1_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__667_BIT_1_67_ETC___d1676 : + ifcs_1_1_innerRoute$D_OUT[0]) ; + assign state_1_237_AND_activeSource_1_0_325_326_AND_i_ETC___d1328 = + state_1 && activeSource_1_0 && ifcs_0_routeBack$EMPTY_N && + ((!ifcs_0_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_0_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_0_routeBack$D_OUT[0]) ; + assign state_1_237_AND_activeSource_1_1_358_359_AND_i_ETC___d1361 = + state_1 && activeSource_1_1 && ifcs_1_routeBack$EMPTY_N && + ((!ifcs_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_1_routeBack$D_OUT[0]) ; + assign state_1_237_AND_activeSource_1_2_392_393_AND_i_ETC___d1395 = + state_1 && activeSource_1_2 && ifcs_2_routeBack$EMPTY_N && + ((!ifcs_2_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_2_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_2_routeBack$D_OUT[0]) ; + assign x__h31666 = + SEXT_arbiter_lastSelect__q2[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h31769 = + SEXT_arbiter_firstHot__q1[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h32134 = + SEXT_SEXT_arbiter_firstHot_054_055_BIT_0_056_A_ETC__q3[0] & + arbiter_firstHot ; + assign x__h32193 = + !SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062 && + SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 ; + assign x__h32275 = SEXT_x2193__q4[0] & arbiter_firstHot ; + assign x__h45858 = x__h45860 | y__h45861 ; + assign x__h45860 = + SEXT_arbiter_1_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h46009 = x__h46011 | y__h46012 ; + assign x__h46011 = + SEXT_arbiter_1_lastSelect_1__q7[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h46145 = x__h46147 | y__h46148 ; + assign x__h46147 = + SEXT_arbiter_1_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h46617 = x__h46619 | y__h46620 ; + assign x__h46619 = + SEXT_SEXT_arbiter_1_firstHot_249_250_BIT_0_251_ETC__q8[0] & + arbiter_1_firstHot ; + assign x__h46679 = + !SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265 && + SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 ; + assign x__h46713 = + !SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 && + !SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265 && + SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 ; + assign x__h46805 = x__h46807 | y__h46808 ; + assign x__h46807 = SEXT_x6679__q9[0] & arbiter_1_firstHot ; + assign x__h46986 = x__h46988 | y__h46989 ; + assign x__h46988 = SEXT_x6713__q10[0] & arbiter_1_firstHot ; + assign x__h65506 = + SEXT_arbiter_1_lastSelect_2__q12[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h65609 = + SEXT_arbiter_1_firstHot_1__q11[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h65974 = + SEXT_SEXT_arbiter_1_firstHot_1_692_693_BIT_0_6_ETC__q13[0] & + arbiter_1_firstHot_1 ; + assign x__h66033 = + !SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700 && + SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 ; + assign x__h66115 = SEXT_x6033__q14[0] & arbiter_1_firstHot_1 ; + assign x__h77157 = x__h77159 | y__h77160 ; + assign x__h77159 = + SEXT_arbiter_1_1_lastSelect__q16[0] & + (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; + assign x__h77308 = x__h77310 | y__h77311 ; + assign x__h77310 = + SEXT_arbiter_1_1_lastSelect_1__q17[0] & + (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; + assign x__h77444 = x__h77446 | y__h77447 ; + assign x__h77446 = + SEXT_arbiter_1_1_firstHot__q15[0] & + (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; + assign x__h77916 = x__h77918 | y__h77919 ; + assign x__h77918 = + SEXT_SEXT_arbiter_1_1_firstHot_877_878_BIT_0_8_ETC__q18[0] & + arbiter_1_1_firstHot ; + assign x__h77978 = + !SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893 && + SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 ; + assign x__h78012 = + !SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 && + !SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893 && + SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 ; + assign x__h78104 = x__h78106 | y__h78107 ; + assign x__h78106 = SEXT_x7978__q19[0] & arbiter_1_1_firstHot ; + assign x__h78285 = x__h78287 | y__h78288 ; + assign x__h78287 = SEXT_x8012__q20[0] & arbiter_1_1_firstHot ; + assign x_port1__read__h55959 = + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? + ifcs_0_1_noRoute_flitCount$port0__write_1 : + ifcs_0_1_noRoute_flitCount ; + assign x_port1__read__h58381 = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? + ifcs_1_1_noRoute_flitCount$port0__write_1 : + ifcs_1_1_noRoute_flitCount ; + assign y__h20569 = + soc_map$m_near_mem_io_addr_range[127:64] + + soc_map$m_near_mem_io_addr_range[63:0] ; + assign y__h20593 = + soc_map$m_plic_addr_range[127:64] + + soc_map$m_plic_addr_range[63:0] ; + assign y__h31667 = + SEXT_arbiter_firstHot__q1[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h31770 = + SEXT_arbiter_lastSelect__q2[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h32135 = SEXT_x2193__q4[0] & arbiter_lastSelect ; + assign y__h32276 = + SEXT_SEXT_arbiter_firstHot_054_055_BIT_0_056_A_ETC__q3[0] & + arbiter_lastSelect ; + assign y__h45859 = + SEXT_arbiter_1_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h45861 = + SEXT_arbiter_1_lastSelect_1__q7[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h46010 = + SEXT_arbiter_1_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h46012 = + SEXT_arbiter_1_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h46146 = + SEXT_arbiter_1_lastSelect_1__q7[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h46148 = + SEXT_arbiter_1_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h46618 = SEXT_x6713__q10[0] & arbiter_1_lastSelect ; + assign y__h46620 = SEXT_x6679__q9[0] & arbiter_1_lastSelect_1 ; + assign y__h46806 = + SEXT_SEXT_arbiter_1_firstHot_249_250_BIT_0_251_ETC__q8[0] & + arbiter_1_lastSelect ; + assign y__h46808 = SEXT_x6713__q10[0] & arbiter_1_lastSelect_1 ; + assign y__h46987 = SEXT_x6679__q9[0] & arbiter_1_lastSelect ; + assign y__h46989 = + SEXT_SEXT_arbiter_1_firstHot_249_250_BIT_0_251_ETC__q8[0] & + arbiter_1_lastSelect_1 ; + assign y__h65507 = + SEXT_arbiter_1_firstHot_1__q11[0] & + (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; + assign y__h65610 = + SEXT_arbiter_1_lastSelect_2__q12[0] & + (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; + assign y__h65975 = SEXT_x6033__q14[0] & arbiter_1_lastSelect_2 ; + assign y__h66116 = + SEXT_SEXT_arbiter_1_firstHot_1_692_693_BIT_0_6_ETC__q13[0] & + arbiter_1_lastSelect_2 ; + assign y__h77158 = + SEXT_arbiter_1_1_firstHot__q15[0] & + (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; + assign y__h77160 = + SEXT_arbiter_1_1_lastSelect_1__q17[0] & + (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; + assign y__h77309 = + SEXT_arbiter_1_1_lastSelect__q16[0] & + (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; + assign y__h77311 = + SEXT_arbiter_1_1_firstHot__q15[0] & + (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; + assign y__h77445 = + SEXT_arbiter_1_1_lastSelect_1__q17[0] & + (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; + assign y__h77447 = + SEXT_arbiter_1_1_lastSelect__q16[0] & + (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; + assign y__h77917 = SEXT_x8012__q20[0] & arbiter_1_1_lastSelect ; + assign y__h77919 = SEXT_x7978__q19[0] & arbiter_1_1_lastSelect_1 ; + assign y__h78105 = + SEXT_SEXT_arbiter_1_1_firstHot_877_878_BIT_0_8_ETC__q18[0] & + arbiter_1_1_lastSelect ; + assign y__h78107 = SEXT_x8012__q20[0] & arbiter_1_1_lastSelect_1 ; + assign y__h78286 = SEXT_x7978__q19[0] & arbiter_1_1_lastSelect ; + assign y__h78288 = + SEXT_SEXT_arbiter_1_1_firstHot_877_878_BIT_0_8_ETC__q18[0] & + arbiter_1_1_lastSelect_1 ; + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + activeSource_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_1_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_1_1_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_1_firstHot_1 <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_1_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_lastSelect_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_0_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY 9'd0; + ifcs_0_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_0_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_0_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_0_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_0_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_1_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY 9'd0; + ifcs_1_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_1_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_1_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_2_1_state <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_2_state <= `BSV_ASSIGNMENT_DELAY 1'd0; + merged_0_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + merged_1_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + split_0_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + split_1_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + split_2_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + state <= `BSV_ASSIGNMENT_DELAY 1'd0; + state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + state_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + state_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + end + else + begin + if (activeSource_0$EN) + activeSource_0 <= `BSV_ASSIGNMENT_DELAY activeSource_0$D_IN; + if (activeSource_1$EN) + activeSource_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1$D_IN; + if (activeSource_1_0$EN) + activeSource_1_0 <= `BSV_ASSIGNMENT_DELAY activeSource_1_0$D_IN; + if (activeSource_1_0_1$EN) + activeSource_1_0_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_0_1$D_IN; + if (activeSource_1_1$EN) + activeSource_1_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1$D_IN; + if (activeSource_1_1_0$EN) + activeSource_1_1_0 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_0$D_IN; + if (activeSource_1_1_1$EN) + activeSource_1_1_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_1$D_IN; + if (activeSource_1_1_1_1$EN) + activeSource_1_1_1_1 <= `BSV_ASSIGNMENT_DELAY + activeSource_1_1_1_1$D_IN; + if (activeSource_1_1_2$EN) + activeSource_1_1_2 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_2$D_IN; + if (activeSource_1_2$EN) + activeSource_1_2 <= `BSV_ASSIGNMENT_DELAY activeSource_1_2$D_IN; + if (arbiter_1_1_firstHot$EN) + arbiter_1_1_firstHot <= `BSV_ASSIGNMENT_DELAY + arbiter_1_1_firstHot$D_IN; + if (arbiter_1_1_lastSelect$EN) + arbiter_1_1_lastSelect <= `BSV_ASSIGNMENT_DELAY + arbiter_1_1_lastSelect$D_IN; + if (arbiter_1_1_lastSelect_1$EN) + arbiter_1_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_1_lastSelect_1$D_IN; + if (arbiter_1_firstHot$EN) + arbiter_1_firstHot <= `BSV_ASSIGNMENT_DELAY arbiter_1_firstHot$D_IN; + if (arbiter_1_firstHot_1$EN) + arbiter_1_firstHot_1 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_firstHot_1$D_IN; + if (arbiter_1_lastSelect$EN) + arbiter_1_lastSelect <= `BSV_ASSIGNMENT_DELAY + arbiter_1_lastSelect$D_IN; + if (arbiter_1_lastSelect_1$EN) + arbiter_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_lastSelect_1$D_IN; + if (arbiter_1_lastSelect_2$EN) + arbiter_1_lastSelect_2 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_lastSelect_2$D_IN; + if (arbiter_firstHot$EN) + arbiter_firstHot <= `BSV_ASSIGNMENT_DELAY arbiter_firstHot$D_IN; + if (arbiter_lastSelect$EN) + arbiter_lastSelect <= `BSV_ASSIGNMENT_DELAY arbiter_lastSelect$D_IN; + if (ifcs_0_1_noRoute_currentReq$EN) + ifcs_0_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_0_1_noRoute_currentReq$D_IN; + if (ifcs_0_1_noRoute_flitCount$EN) + ifcs_0_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY + ifcs_0_1_noRoute_flitCount$D_IN; + if (ifcs_0_1_state$EN) + ifcs_0_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_0_1_state$D_IN; + if (ifcs_0_1_state_1$EN) + ifcs_0_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_0_1_state_1$D_IN; + if (ifcs_0_noRoute_inner_currentReq$EN) + ifcs_0_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_0_noRoute_inner_currentReq$D_IN; + if (ifcs_0_noRoute_inner_pendingReq$EN) + ifcs_0_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY + ifcs_0_noRoute_inner_pendingReq$D_IN; + if (ifcs_0_state$EN) + ifcs_0_state <= `BSV_ASSIGNMENT_DELAY ifcs_0_state$D_IN; + if (ifcs_0_state_1$EN) + ifcs_0_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_0_state_1$D_IN; + if (ifcs_1_1_noRoute_currentReq$EN) + ifcs_1_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_1_1_noRoute_currentReq$D_IN; + if (ifcs_1_1_noRoute_flitCount$EN) + ifcs_1_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY + ifcs_1_1_noRoute_flitCount$D_IN; + if (ifcs_1_1_state$EN) + ifcs_1_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_1_1_state$D_IN; + if (ifcs_1_1_state_1$EN) + ifcs_1_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_1_1_state_1$D_IN; + if (ifcs_1_noRoute_inner_currentReq$EN) + ifcs_1_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_1_noRoute_inner_currentReq$D_IN; + if (ifcs_1_noRoute_inner_pendingReq$EN) + ifcs_1_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY + ifcs_1_noRoute_inner_pendingReq$D_IN; + if (ifcs_1_state$EN) + ifcs_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_1_state$D_IN; + if (ifcs_1_state_1$EN) + ifcs_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_1_state_1$D_IN; + if (ifcs_2_1_state$EN) + ifcs_2_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_2_1_state$D_IN; + if (ifcs_2_state$EN) + ifcs_2_state <= `BSV_ASSIGNMENT_DELAY ifcs_2_state$D_IN; + if (merged_0_flitLeft$EN) + merged_0_flitLeft <= `BSV_ASSIGNMENT_DELAY merged_0_flitLeft$D_IN; + if (merged_1_flitLeft$EN) + merged_1_flitLeft <= `BSV_ASSIGNMENT_DELAY merged_1_flitLeft$D_IN; + if (split_0_flitLeft$EN) + split_0_flitLeft <= `BSV_ASSIGNMENT_DELAY split_0_flitLeft$D_IN; + if (split_1_flitLeft$EN) + split_1_flitLeft <= `BSV_ASSIGNMENT_DELAY split_1_flitLeft$D_IN; + if (split_2_flitLeft$EN) + split_2_flitLeft <= `BSV_ASSIGNMENT_DELAY split_2_flitLeft$D_IN; + if (state$EN) state <= `BSV_ASSIGNMENT_DELAY state$D_IN; + if (state_1$EN) state_1 <= `BSV_ASSIGNMENT_DELAY state_1$D_IN; + if (state_1_1$EN) state_1_1 <= `BSV_ASSIGNMENT_DELAY state_1_1$D_IN; + if (state_1_1_1$EN) + state_1_1_1 <= `BSV_ASSIGNMENT_DELAY state_1_1_1$D_IN; + end + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + activeSource_0 = 1'h0; + activeSource_1 = 1'h0; + activeSource_1_0 = 1'h0; + activeSource_1_0_1 = 1'h0; + activeSource_1_1 = 1'h0; + activeSource_1_1_0 = 1'h0; + activeSource_1_1_1 = 1'h0; + activeSource_1_1_1_1 = 1'h0; + activeSource_1_1_2 = 1'h0; + activeSource_1_2 = 1'h0; + arbiter_1_1_firstHot = 1'h0; + arbiter_1_1_lastSelect = 1'h0; + arbiter_1_1_lastSelect_1 = 1'h0; + arbiter_1_firstHot = 1'h0; + arbiter_1_firstHot_1 = 1'h0; + arbiter_1_lastSelect = 1'h0; + arbiter_1_lastSelect_1 = 1'h0; + arbiter_1_lastSelect_2 = 1'h0; + arbiter_firstHot = 1'h0; + arbiter_lastSelect = 1'h0; + ifcs_0_1_noRoute_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_1_noRoute_flitCount = 9'h0AA; + ifcs_0_1_state = 2'h2; + ifcs_0_1_state_1 = 1'h0; + ifcs_0_noRoute_inner_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_noRoute_inner_pendingReq = 1'h0; + ifcs_0_state = 2'h2; + ifcs_0_state_1 = 1'h0; + ifcs_1_1_noRoute_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_1_noRoute_flitCount = 9'h0AA; + ifcs_1_1_state = 2'h2; + ifcs_1_1_state_1 = 1'h0; + ifcs_1_noRoute_inner_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_noRoute_inner_pendingReq = 1'h0; + ifcs_1_state = 2'h2; + ifcs_1_state_1 = 1'h0; + ifcs_2_1_state = 1'h0; + ifcs_2_state = 1'h0; + merged_0_flitLeft = 8'hAA; + merged_1_flitLeft = 8'hAA; + split_0_flitLeft = 8'hAA; + split_1_flitLeft = 8'hAA; + split_2_flitLeft = 8'hAA; + state = 1'h0; + state_1 = 1'h0; + state_1_1 = 1'h0; + state_1_1_1 = 1'h0; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on // handling of system tasks @@ -3486,36 +8615,1663 @@ module mkCore(CLK, always@(negedge CLK) begin #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate && + !SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 && + !SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate && + !SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 && + !SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h33674 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h33674, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) + begin + v__h33063 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h33063, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h37683 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h37683, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) + begin + v__h37072 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h37072, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && WILL_FIRE_RL_burst) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 113, column 32: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected] and\n [RL_burst] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected || WILL_FIRE_RL_burst) && + (WILL_FIRE_RL_source_selected_1 || WILL_FIRE_RL_burst_1)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected, RL_burst]\n and [RL_source_selected_1, RL_burst_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && WILL_FIRE_RL_burst_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_1] and\n [RL_burst_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected && WILL_FIRE_RL_sink_selected_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected] and\n [RL_sink_selected_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_sink_selected || WILL_FIRE_RL_sink_selected_1) && + WILL_FIRE_RL_sink_selected_2) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected,\n RL_sink_selected_1] and [RL_sink_selected_2] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_2 && + !SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 && + !SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_2 && + !SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 && + !SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h67508 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h67508, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) + begin + v__h66897 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h66897, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h70401 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h70401, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) + begin + v__h69790 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h69790, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && WILL_FIRE_RL_burst_5) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_5] and\n [RL_burst_5] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_5 || WILL_FIRE_RL_burst_5) && + (WILL_FIRE_RL_source_selected_6 || WILL_FIRE_RL_burst_6)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_5,\n RL_burst_5] and [RL_source_selected_6, RL_burst_6] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && WILL_FIRE_RL_burst_6) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_6] and\n [RL_burst_6] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_5 && WILL_FIRE_RL_sink_selected_6) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5] and\n [RL_sink_selected_6] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_sink_selected_5 || WILL_FIRE_RL_sink_selected_6) && + WILL_FIRE_RL_sink_selected_7) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5,\n RL_sink_selected_6] and [RL_sink_selected_7] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[171]) + $display("Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] && + split_0_doPut$wget[0] && + split_0_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] && + split_0_doPut$wget[0] && + split_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] && + !split_0_doPut$wget[0] && + split_0_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] && + !split_0_doPut$wget[0] && + split_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[171]) + $display("Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[171]) + $display("Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] && + split_1_doPut$wget[0] && + split_1_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] && + split_1_doPut$wget[0] && + split_1_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] && + !split_1_doPut$wget[0] && + split_1_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] && + !split_1_doPut$wget[0] && + split_1_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[171]) + $display("Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[171]) + $display("Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] && + split_2_doPut$wget[0] && + split_2_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] && + split_2_doPut$wget[0] && + split_2_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] && + !split_2_doPut$wget[0] && + split_2_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] && + !split_2_doPut$wget[0] && + split_2_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[171]) + $display("Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_nonRoutableFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 && + !SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 && + !SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 && + !SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 && + !SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h48378 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h48378, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + begin + v__h47997 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h47997, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h50448 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h50448, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + begin + v__h50067 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h50067, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && WILL_FIRE_RL_burst_3) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_3] and\n [RL_burst_3] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h52347 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h52347, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + begin + v__h51966 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h51966, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && WILL_FIRE_RL_burst_2) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2] and\n [RL_burst_2] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2) && + (WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2] and [RL_source_selected_3, RL_burst_3] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2 || + WILL_FIRE_RL_source_selected_3 || + WILL_FIRE_RL_burst_3) && + (WILL_FIRE_RL_source_selected_4 || WILL_FIRE_RL_burst_4)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2, RL_source_selected_3, RL_burst_3] and [RL_source_selected_4,\n RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && WILL_FIRE_RL_burst_4) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_4] and\n [RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_3 && WILL_FIRE_RL_sink_selected_4) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_3] and\n [RL_sink_selected_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_forwardRsp) + begin + v__h22294 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_forwardRsp) + $display("%0t: Forwarding 0x%x", + v__h22294, + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_drainFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_drainFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && cpu$dmem_master_wlast && + merged_0_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && cpu$dmem_master_wlast && + merged_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !cpu$dmem_master_wlast && + merged_0_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !cpu$dmem_master_wlast && + merged_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_forwardRsp) + begin + v__h25002 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_forwardRsp) + $display("%0t: Forwarding 0x%x", + v__h25002, + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_followFlits_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 285, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit_1] and\n [RL_ifcs_0_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_1_followFlits_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 285, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit_1] and\n [RL_ifcs_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_3 && + !SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 && + !SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 && + !SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_3 && + !SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 && + !SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 && + !SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h79681 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h79681, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) + begin + v__h79300 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h79300, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h82172 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h82172, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) + begin + v__h81791 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h81791, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && WILL_FIRE_RL_burst_8) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_8] and\n [RL_burst_8] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h84482 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h84482, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) + begin + v__h84101 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h84101, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && WILL_FIRE_RL_burst_7) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7] and\n [RL_burst_7] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_7 || WILL_FIRE_RL_burst_7) && + (WILL_FIRE_RL_source_selected_8 || WILL_FIRE_RL_burst_8)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7,\n RL_burst_7] and [RL_source_selected_8, RL_burst_8] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_7 || WILL_FIRE_RL_burst_7 || + WILL_FIRE_RL_source_selected_8 || + WILL_FIRE_RL_burst_8) && + (WILL_FIRE_RL_source_selected_9 || WILL_FIRE_RL_burst_9)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7,\n RL_burst_7, RL_source_selected_8, RL_burst_8] and [RL_source_selected_9,\n RL_burst_9] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && WILL_FIRE_RL_burst_9) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_9] and\n [RL_burst_9] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_8 && WILL_FIRE_RL_sink_selected_9) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_8] and\n [RL_sink_selected_9] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_forwardRsp) + begin + v__h56310 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_forwardRsp) + $display("%0t: Forwarding 0x%x", + v__h56310, + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) begin - v__h5074 = $stime; + v__h3443 = $stime; #0; end - v__h5068 = v__h5074 / 32'd10; + v__h3437 = v__h3443 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h5068); + $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h3437); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) begin - v__h5275 = $stime; + v__h3620 = $stime; #0; end - v__h5269 = v__h5275 / 32'd10; + v__h3614 = v__h3620 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h5269); + $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h3614); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) begin - v__h5643 = $stime; + v__h3986 = $stime; #0; end - v__h5637 = v__h5643 / 32'd10; + v__h3980 = v__h3986 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h5637); + $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h3980); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_firstFlit && WILL_FIRE_RL_ifcs_2_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 284, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_firstFlit] and\n [RL_ifcs_2_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_nonRoutableFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_drainFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_drainFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_forwardRsp) + begin + v__h58726 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_forwardRsp) + $display("%0t: Forwarding 0x%x", + v__h58726, + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_nonRoutableFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_drainFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_drainFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && dm_mem_tap$master_wlast && + merged_1_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && dm_mem_tap$master_wlast && + merged_1_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && !dm_mem_tap$master_wlast && + merged_1_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && !dm_mem_tap$master_wlast && + merged_1_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_nonRoutableFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_drainFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_drainFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_1_followFlits_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 285, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit_1] and\n [RL_ifcs_0_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_1_1_followFlits_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 285, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit_1] and\n [RL_ifcs_1_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_1_firstFlit && + WILL_FIRE_RL_ifcs_2_1_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 284, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_1_firstFlit] and\n [RL_ifcs_2_1_followFlits] ) fired in the same clock cycle.\n"); end // synopsys translate_on endmodule // mkCore diff --git a/src_SSITH_P1/Verilog_RTL/mkDM_Abstract_Commands.v b/src_SSITH_P1/Verilog_RTL/mkDM_Abstract_Commands.v index f23b0bbc..f66551a0 100644 --- a/src_SSITH_P1/Verilog_RTL/mkDM_Abstract_Commands.v +++ b/src_SSITH_P1/Verilog_RTL/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:15 BST 2019 // // // Ports: @@ -242,26 +242,26 @@ module mkDM_Abstract_Commands(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h2054; - reg [31 : 0] v__h2293; - reg [31 : 0] v__h2418; - reg [31 : 0] v__h2745; - reg [31 : 0] v__h2862; - reg [31 : 0] v__h2575; - reg [31 : 0] v__h3277; - reg [31 : 0] v__h2048; - reg [31 : 0] v__h2287; - reg [31 : 0] v__h2412; - reg [31 : 0] v__h2569; - reg [31 : 0] v__h2739; - reg [31 : 0] v__h2856; - reg [31 : 0] v__h3271; + reg [31 : 0] v__h2078; + reg [31 : 0] v__h2317; + reg [31 : 0] v__h2442; + reg [31 : 0] v__h2769; + reg [31 : 0] v__h2886; + reg [31 : 0] v__h2599; + reg [31 : 0] v__h3301; + reg [31 : 0] v__h2072; + reg [31 : 0] v__h2311; + reg [31 : 0] v__h2436; + reg [31 : 0] v__h2593; + reg [31 : 0] v__h2763; + reg [31 : 0] v__h2880; + reg [31 : 0] v__h3295; // synopsys translate_on // remaining internal signals - wire [31 : 0] virt_rg_abstractcs__h500, virt_rg_command__h564; - wire [15 : 0] regno__h1869; - wire [12 : 0] x__h1051; + wire [31 : 0] virt_rg_abstractcs__h524, virt_rg_command__h588; + wire [15 : 0] regno__h1893; + wire [12 : 0] x__h1075; wire rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d35, rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d46, rg_abstractcs_cmderr_0_EQ_0_4_AND_write_dm_add_ETC___d105, @@ -282,11 +282,11 @@ module mkDM_Abstract_Commands(CLK, // actionvalue method av_read always@(av_read_dm_addr or - rg_data0 or virt_rg_abstractcs__h500 or virt_rg_command__h564) + rg_data0 or virt_rg_abstractcs__h524 or virt_rg_command__h588) begin case (av_read_dm_addr) - 7'h16: av_read = virt_rg_abstractcs__h500; - 7'h17: av_read = virt_rg_command__h564; + 7'h16: av_read = virt_rg_abstractcs__h524; + 7'h17: av_read = virt_rg_command__h588; default: av_read = rg_data0; endcase end @@ -330,7 +330,7 @@ module mkDM_Abstract_Commands(CLK, EN_hart0_csr_mem_client_response_put ; // submodule f_hart0_csr_reqs - FIFO1 #(.width(32'd45), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd45), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_csr_reqs$D_IN), .ENQ(f_hart0_csr_reqs$ENQ), @@ -341,7 +341,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_csr_reqs$EMPTY_N)); // submodule f_hart0_csr_rsps - FIFO1 #(.width(32'd33), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd33), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_csr_rsps$D_IN), .ENQ(f_hart0_csr_rsps$ENQ), @@ -352,7 +352,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_csr_rsps$EMPTY_N)); // submodule f_hart0_gpr_reqs - FIFO1 #(.width(32'd38), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd38), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_gpr_reqs$D_IN), .ENQ(f_hart0_gpr_reqs$ENQ), @@ -363,7 +363,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_gpr_reqs$EMPTY_N)); // submodule f_hart0_gpr_rsps - FIFO1 #(.width(32'd33), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd33), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_gpr_rsps$D_IN), .ENQ(f_hart0_gpr_rsps$ENQ), @@ -470,9 +470,9 @@ module mkDM_Abstract_Commands(CLK, assign MUX_f_hart0_csr_reqs$enq_1__VAL_2 = { 1'd0, rg_command_access_reg_regno[11:0], 32'hAAAAAAAA } ; assign MUX_f_hart0_gpr_reqs$enq_1__VAL_1 = - { 1'd1, x__h1051[4:0], rg_data0 } ; + { 1'd1, x__h1075[4:0], rg_data0 } ; assign MUX_f_hart0_gpr_reqs$enq_1__VAL_2 = - { 1'd0, x__h1051[4:0], 32'hAAAAAAAA } ; + { 1'd0, x__h1075[4:0], 32'hAAAAAAAA } ; assign MUX_rg_abstractcs_cmderr$write_1__VAL_4 = f_hart0_gpr_rsps$D_OUT[32] ? 3'd0 : 3'd4 ; always@(write_dm_addr or rg_abstractcs_busy or write_dm_word) @@ -671,7 +671,7 @@ module mkDM_Abstract_Commands(CLK, assign f_hart0_gpr_rsps$CLR = EN_reset ; // remaining internal signals - assign regno__h1869 = { 3'd0, rg_command_access_reg_regno } ; + assign regno__h1893 = { 3'd0, rg_command_access_reg_regno } ; assign rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d35 = rg_abstractcs_busy && rg_start_reg_access && rg_command_access_reg_write && @@ -697,10 +697,10 @@ module mkDM_Abstract_Commands(CLK, rg_command_access_reg_regno <= 13'h0FFF ; assign rg_command_access_reg_regno_ULT_0x1000___d31 = rg_command_access_reg_regno < 13'h1000 ; - assign virt_rg_abstractcs__h500 = + assign virt_rg_abstractcs__h524 = { 19'd0, rg_abstractcs_busy, 1'b0, rg_abstractcs_cmderr, 8'd1 } ; - assign virt_rg_command__h564 = - { 15'd17, rg_command_access_reg_write, regno__h1869 } ; + assign virt_rg_command__h588 = + { 15'd17, rg_command_access_reg_write, regno__h1893 } ; assign write_dm_addr_EQ_0x16_7_AND_rg_abstractcs_busy_ETC___d79 = write_dm_addr == 7'h16 && (rg_abstractcs_busy || write_dm_word[10:8] != 3'd0) || @@ -733,7 +733,7 @@ module mkDM_Abstract_Commands(CLK, write_dm_word[22:20] != 3'd4 && write_dm_word[22:20] != 3'd5 && write_dm_word[22:20] != 3'd6 ; - assign x__h1051 = rg_command_access_reg_regno - 13'h1000 ; + assign x__h1075 = rg_command_access_reg_regno - 13'h1000 ; // handling of inlined registers @@ -786,14 +786,14 @@ module mkDM_Abstract_Commands(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) begin - v__h2054 = $stime; + v__h2078 = $stime; #0; end - v__h2048 = v__h2054 / 32'd10; + v__h2072 = v__h2078 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) $display("%0d: DM_Abstract_Commands.write: [abstractcs] <= 0x%08h: ERROR", - v__h2048, + v__h2072, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) @@ -803,16 +803,16 @@ module mkDM_Abstract_Commands(CLK, write_dm_addr == 7'h17 && rg_abstractcs_busy) begin - v__h2293 = $stime; + v__h2317 = $stime; #0; end - v__h2287 = v__h2293 / 32'd10; + v__h2311 = v__h2317 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h17 && rg_abstractcs_busy) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h2287, + v__h2311, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -823,15 +823,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr_0_EQ_0_4_AND_write_dm_add_ETC___d105) begin - v__h2418 = $stime; + v__h2442 = $stime; #0; end - v__h2412 = v__h2418 / 32'd10; + v__h2436 = v__h2442 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr_0_EQ_0_4_AND_write_dm_add_ETC___d105) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h2412, + v__h2436, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && @@ -849,15 +849,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_1_AND_NOT_rg_abstractcs__ETC___d112) begin - v__h2745 = $stime; + v__h2769 = $stime; #0; end - v__h2739 = v__h2745 / 32'd10; + v__h2763 = v__h2769 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_1_AND_NOT_rg_abstractcs__ETC___d112) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h2739, + v__h2763, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -867,15 +867,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_1_AND_NOT_rg_abstractcs__ETC___d130) begin - v__h2862 = $stime; + v__h2886 = $stime; #0; end - v__h2856 = v__h2862 / 32'd10; + v__h2880 = v__h2886 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_1_AND_NOT_rg_abstractcs__ETC___d130) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h2856, + v__h2880, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -885,15 +885,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr_0_EQ_0_4_AND_write_dm_add_ETC___d137) begin - v__h2575 = $stime; + v__h2599 = $stime; #0; end - v__h2569 = v__h2575 / 32'd10; + v__h2593 = v__h2599 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr_0_EQ_0_4_AND_write_dm_add_ETC___d137) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h2569, + v__h2593, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && @@ -955,16 +955,16 @@ module mkDM_Abstract_Commands(CLK, write_dm_addr != 7'h17 && write_dm_addr != 7'h04) begin - v__h3277 = $stime; + v__h3301 = $stime; #0; end - v__h3271 = v__h3277 / 32'd10; + v__h3295 = v__h3301 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr != 7'h16 && rg_abstractcs_cmderr == 3'd0 && write_dm_addr != 7'h17 && write_dm_addr != 7'h04) - $write("%0d: DM_Abstract_Commands.write: [", v__h3271); + $write("%0d: DM_Abstract_Commands.write: [", v__h3295); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h10) $write("dm_addr_dmcontrol"); diff --git a/src_SSITH_P1/Verilog_RTL/mkDM_CSR_Tap.v b/src_SSITH_P1/Verilog_RTL/mkDM_CSR_Tap.v index 96cc6fbc..4cf6f74b 100644 --- a/src_SSITH_P1/Verilog_RTL/mkDM_CSR_Tap.v +++ b/src_SSITH_P1/Verilog_RTL/mkDM_CSR_Tap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:32 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkDM_GPR_Tap.v b/src_SSITH_P1/Verilog_RTL/mkDM_GPR_Tap.v index 42f4ad1d..311d9452 100644 --- a/src_SSITH_P1/Verilog_RTL/mkDM_GPR_Tap.v +++ b/src_SSITH_P1/Verilog_RTL/mkDM_GPR_Tap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:32 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkDM_Mem_Tap.v b/src_SSITH_P1/Verilog_RTL/mkDM_Mem_Tap.v index 86b1f78d..a1f6d43d 100644 --- a/src_SSITH_P1/Verilog_RTL/mkDM_Mem_Tap.v +++ b/src_SSITH_P1/Verilog_RTL/mkDM_Mem_Tap.v @@ -1,96 +1,517 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:32 BST 2019 // // // Ports: // Name I/O size props -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// master_awvalid O 1 reg -// master_awid O 4 reg -// master_awaddr O 64 reg -// master_awlen O 8 reg -// master_awsize O 3 reg -// master_awburst O 2 reg -// master_awlock O 1 reg -// master_awcache O 4 reg -// master_awprot O 3 reg -// master_awqos O 4 reg -// master_awregion O 4 reg -// master_wvalid O 1 reg -// master_wdata O 64 reg -// master_wstrb O 8 reg -// master_wlast O 1 reg -// master_bready O 1 reg -// master_arvalid O 1 reg -// master_arid O 4 reg -// master_araddr O 64 reg -// master_arlen O 8 reg -// master_arsize O 3 reg -// master_arburst O 2 reg -// master_arlock O 1 reg -// master_arcache O 4 reg -// master_arprot O 3 reg -// master_arqos O 4 reg -// master_arregion O 4 reg -// master_rready O 1 reg +// slave_awready O 1 +// slave_wready O 1 +// slave_bid O 4 +// slave_bresp O 2 +// slave_bvalid O 1 +// slave_arready O 1 +// slave_rid O 4 +// slave_rdata O 64 +// slave_rresp O 2 +// slave_rlast O 1 +// slave_rvalid O 1 +// master_awid O 4 +// master_awaddr O 64 +// master_awlen O 8 +// master_awsize O 3 +// master_awburst O 2 +// master_awlock O 1 +// master_awcache O 4 +// master_awprot O 3 +// master_awqos O 4 +// master_awregion O 4 +// master_awvalid O 1 +// master_wdata O 64 +// master_wstrb O 8 +// master_wlast O 1 +// master_wvalid O 1 +// master_bready O 1 +// master_arid O 4 +// master_araddr O 64 +// master_arlen O 8 +// master_arsize O 3 +// master_arburst O 2 +// master_arlock O 1 +// master_arcache O 4 +// master_arprot O 3 +// master_arqos O 4 +// master_arregion O 4 +// master_arvalid O 1 +// master_rready O 1 // trace_data_out_get O 234 reg // RDY_trace_data_out_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg +// slave_awid I 4 +// slave_awaddr I 64 +// slave_awlen I 8 +// slave_awsize I 3 +// slave_awburst I 2 +// slave_awlock I 1 +// slave_awcache I 4 +// slave_awprot I 3 +// slave_awqos I 4 +// slave_awregion I 4 +// slave_wdata I 64 +// slave_wstrb I 8 +// slave_wlast I 1 // slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg +// slave_arid I 4 +// slave_araddr I 64 +// slave_arlen I 8 +// slave_arsize I 3 +// slave_arburst I 2 +// slave_arlock I 1 +// slave_arcache I 4 +// slave_arprot I 3 +// slave_arqos I 4 +// slave_arregion I 4 // slave_rready I 1 // master_awready I 1 // master_wready I 1 -// master_bvalid I 1 -// master_bid I 4 reg -// master_bresp I 2 reg +// master_bid I 4 +// master_bresp I 2 // master_arready I 1 +// master_rid I 4 +// master_rdata I 64 +// master_rresp I 2 +// master_rlast I 1 +// slave_awvalid I 1 +// slave_wvalid I 1 +// slave_arvalid I 1 +// master_bvalid I 1 // master_rvalid I 1 -// master_rid I 4 reg -// master_rdata I 64 reg -// master_rresp I 2 reg -// master_rlast I 1 reg // EN_trace_data_out_get I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awid +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awaddr +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awlen +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awsize +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awburst +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awlock +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awcache +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awprot +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awqos +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awregion +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awuser +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awvalid +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_wdata +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_wstrb +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_wlast +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_wuser +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_wvalid +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arid +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_araddr +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arlen +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arsize +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arburst +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arlock +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arcache +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arprot +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arqos +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arregion +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_aruser +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arvalid +// (master_bid, master_bresp, master_bvalid) -> slave_bid +// (master_bid, master_bresp, master_bvalid) -> slave_bresp +// (master_bid, master_bresp, master_bvalid) -> slave_buser +// (master_bid, master_bresp, master_bvalid) -> slave_bvalid +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_rid +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_rdata +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_rresp +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_rlast +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_ruser +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_rvalid // // @@ -110,7 +531,6 @@ module mkDM_Mem_Tap(CLK, RST_N, - slave_awvalid, slave_awid, slave_awaddr, slave_awlen, @@ -121,25 +541,25 @@ module mkDM_Mem_Tap(CLK, slave_awprot, slave_awqos, slave_awregion, + slave_awvalid, slave_awready, - slave_wvalid, slave_wdata, slave_wstrb, slave_wlast, + slave_wvalid, slave_wready, - slave_bvalid, - slave_bid, slave_bresp, + slave_bvalid, + slave_bready, - slave_arvalid, slave_arid, slave_araddr, slave_arlen, @@ -150,11 +570,10 @@ module mkDM_Mem_Tap(CLK, slave_arprot, slave_arqos, slave_arregion, + slave_arvalid, slave_arready, - slave_rvalid, - slave_rid, slave_rdata, @@ -163,9 +582,9 @@ module mkDM_Mem_Tap(CLK, slave_rlast, - slave_rready, + slave_rvalid, - master_awvalid, + slave_rready, master_awid, @@ -187,9 +606,9 @@ module mkDM_Mem_Tap(CLK, master_awregion, - master_awready, + master_awvalid, - master_wvalid, + master_awready, master_wdata, @@ -197,16 +616,16 @@ module mkDM_Mem_Tap(CLK, master_wlast, + master_wvalid, + master_wready, - master_bvalid, master_bid, master_bresp, + master_bvalid, master_bready, - master_arvalid, - master_arid, master_araddr, @@ -227,13 +646,15 @@ module mkDM_Mem_Tap(CLK, master_arregion, + master_arvalid, + master_arready, - master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, + master_rvalid, master_rready, @@ -243,8 +664,7 @@ module mkDM_Mem_Tap(CLK, input CLK; input RST_N; - // action method slave_m_awvalid - input slave_awvalid; + // action method slave_aw_awflit input [3 : 0] slave_awid; input [63 : 0] slave_awaddr; input [7 : 0] slave_awlen; @@ -255,35 +675,35 @@ module mkDM_Mem_Tap(CLK, input [2 : 0] slave_awprot; input [3 : 0] slave_awqos; input [3 : 0] slave_awregion; + input slave_awvalid; - // value method slave_m_awready + // value method slave_aw_awready output slave_awready; - // action method slave_m_wvalid - input slave_wvalid; + // action method slave_w_wflit input [63 : 0] slave_wdata; input [7 : 0] slave_wstrb; input slave_wlast; + input slave_wvalid; - // value method slave_m_wready + // value method slave_w_wready output slave_wready; - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid + // value method slave_b_bid output [3 : 0] slave_bid; - // value method slave_m_bresp + // value method slave_b_bresp output [1 : 0] slave_bresp; - // value method slave_m_buser + // value method slave_b_buser + + // value method slave_b_bvalid + output slave_bvalid; - // action method slave_m_bready + // action method slave_b_bready input slave_bready; - // action method slave_m_arvalid - input slave_arvalid; + // action method slave_ar_arflit input [3 : 0] slave_arid; input [63 : 0] slave_araddr; input [7 : 0] slave_arlen; @@ -294,139 +714,140 @@ module mkDM_Mem_Tap(CLK, input [2 : 0] slave_arprot; input [3 : 0] slave_arqos; input [3 : 0] slave_arregion; + input slave_arvalid; - // value method slave_m_arready + // value method slave_ar_arready output slave_arready; - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid + // value method slave_r_rid output [3 : 0] slave_rid; - // value method slave_m_rdata + // value method slave_r_rdata output [63 : 0] slave_rdata; - // value method slave_m_rresp + // value method slave_r_rresp output [1 : 0] slave_rresp; - // value method slave_m_rlast + // value method slave_r_rlast output slave_rlast; - // value method slave_m_ruser + // value method slave_r_ruser - // action method slave_m_rready - input slave_rready; + // value method slave_r_rvalid + output slave_rvalid; - // value method master_m_awvalid - output master_awvalid; + // action method slave_r_rready + input slave_rready; - // value method master_m_awid + // value method master_aw_awid output [3 : 0] master_awid; - // value method master_m_awaddr + // value method master_aw_awaddr output [63 : 0] master_awaddr; - // value method master_m_awlen + // value method master_aw_awlen output [7 : 0] master_awlen; - // value method master_m_awsize + // value method master_aw_awsize output [2 : 0] master_awsize; - // value method master_m_awburst + // value method master_aw_awburst output [1 : 0] master_awburst; - // value method master_m_awlock + // value method master_aw_awlock output master_awlock; - // value method master_m_awcache + // value method master_aw_awcache output [3 : 0] master_awcache; - // value method master_m_awprot + // value method master_aw_awprot output [2 : 0] master_awprot; - // value method master_m_awqos + // value method master_aw_awqos output [3 : 0] master_awqos; - // value method master_m_awregion + // value method master_aw_awregion output [3 : 0] master_awregion; - // value method master_m_awuser + // value method master_aw_awuser - // action method master_m_awready - input master_awready; + // value method master_aw_awvalid + output master_awvalid; - // value method master_m_wvalid - output master_wvalid; + // action method master_aw_awready + input master_awready; - // value method master_m_wdata + // value method master_w_wdata output [63 : 0] master_wdata; - // value method master_m_wstrb + // value method master_w_wstrb output [7 : 0] master_wstrb; - // value method master_m_wlast + // value method master_w_wlast output master_wlast; - // value method master_m_wuser + // value method master_w_wuser + + // value method master_w_wvalid + output master_wvalid; - // action method master_m_wready + // action method master_w_wready input master_wready; - // action method master_m_bvalid - input master_bvalid; + // action method master_b_bflit input [3 : 0] master_bid; input [1 : 0] master_bresp; + input master_bvalid; - // value method master_m_bready + // value method master_b_bready output master_bready; - // value method master_m_arvalid - output master_arvalid; - - // value method master_m_arid + // value method master_ar_arid output [3 : 0] master_arid; - // value method master_m_araddr + // value method master_ar_araddr output [63 : 0] master_araddr; - // value method master_m_arlen + // value method master_ar_arlen output [7 : 0] master_arlen; - // value method master_m_arsize + // value method master_ar_arsize output [2 : 0] master_arsize; - // value method master_m_arburst + // value method master_ar_arburst output [1 : 0] master_arburst; - // value method master_m_arlock + // value method master_ar_arlock output master_arlock; - // value method master_m_arcache + // value method master_ar_arcache output [3 : 0] master_arcache; - // value method master_m_arprot + // value method master_ar_arprot output [2 : 0] master_arprot; - // value method master_m_arqos + // value method master_ar_arqos output [3 : 0] master_arqos; - // value method master_m_arregion + // value method master_ar_arregion output [3 : 0] master_arregion; - // value method master_m_aruser + // value method master_ar_aruser + + // value method master_ar_arvalid + output master_arvalid; - // action method master_m_arready + // action method master_ar_arready input master_arready; - // action method master_m_rvalid - input master_rvalid; + // action method master_r_rflit input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; + input master_rvalid; - // value method master_m_rready + // value method master_r_rready output master_rready; // actionvalue method trace_data_out_get @@ -466,6 +887,128 @@ module mkDM_Mem_Tap(CLK, slave_rvalid, slave_wready; + // inlined wires + wire [97 : 0] master_xactor_shim_arff_rv$port0__write_1, + master_xactor_shim_arff_rv$port1__read, + master_xactor_shim_arff_rv$port2__read, + master_xactor_shim_arff_rv$port3__read, + master_xactor_shim_awff_rv$port0__write_1, + master_xactor_shim_awff_rv$port1__read, + master_xactor_shim_awff_rv$port2__read, + master_xactor_shim_awff_rv$port3__read, + slave_xactor_shim_arff_rv$port0__write_1, + slave_xactor_shim_arff_rv$port1__read, + slave_xactor_shim_arff_rv$port2__read, + slave_xactor_shim_arff_rv$port3__read, + slave_xactor_shim_awff_rv$port0__write_1, + slave_xactor_shim_awff_rv$port1__read, + slave_xactor_shim_awff_rv$port2__read, + slave_xactor_shim_awff_rv$port3__read; + wire [96 : 0] slave_xactor_ug_slave_u_ar_putWire$wget, + slave_xactor_ug_slave_u_aw_putWire$wget; + wire [73 : 0] master_xactor_shim_wff_rv$port0__write_1, + master_xactor_shim_wff_rv$port1__read, + master_xactor_shim_wff_rv$port2__read, + master_xactor_shim_wff_rv$port3__read, + slave_xactor_shim_wff_rv$port0__write_1, + slave_xactor_shim_wff_rv$port1__read, + slave_xactor_shim_wff_rv$port2__read, + slave_xactor_shim_wff_rv$port3__read; + wire [72 : 0] slave_xactor_ug_slave_u_w_putWire$wget; + wire [71 : 0] master_xactor_shim_rff_rv$port0__write_1, + master_xactor_shim_rff_rv$port1__read, + master_xactor_shim_rff_rv$port2__read, + master_xactor_shim_rff_rv$port3__read, + slave_xactor_shim_rff_rv$port0__write_1, + slave_xactor_shim_rff_rv$port1__read, + slave_xactor_shim_rff_rv$port2__read, + slave_xactor_shim_rff_rv$port3__read; + wire [70 : 0] master_xactor_ug_master_u_r_putWire$wget, + slave_xactor_ug_slave_u_r_peekWire$wget; + wire [6 : 0] master_xactor_shim_bff_rv$port0__write_1, + master_xactor_shim_bff_rv$port1__read, + master_xactor_shim_bff_rv$port2__read, + master_xactor_shim_bff_rv$port3__read, + slave_xactor_shim_bff_rv$port0__write_1, + slave_xactor_shim_bff_rv$port1__read, + slave_xactor_shim_bff_rv$port2__read, + slave_xactor_shim_bff_rv$port3__read; + wire [5 : 0] master_xactor_ug_master_u_b_putWire$wget, + slave_xactor_ug_slave_u_b_peekWire$wget; + wire master_xactor_ug_master_u_ar_dropWire$whas, + master_xactor_ug_master_u_aw_dropWire$whas, + master_xactor_ug_master_u_b_putWire$whas, + master_xactor_ug_master_u_r_putWire$whas, + master_xactor_ug_master_u_w_dropWire$whas, + slave_xactor_shim_arff_rv$EN_port1__write, + slave_xactor_shim_awff_rv$EN_port1__write, + slave_xactor_shim_bff_rv$EN_port0__write, + slave_xactor_shim_rff_rv$EN_port0__write, + slave_xactor_shim_wff_rv$EN_port1__write, + slave_xactor_ug_slave_u_ar_putWire$whas, + slave_xactor_ug_slave_u_aw_putWire$whas, + slave_xactor_ug_slave_u_b_dropWire$whas, + slave_xactor_ug_slave_u_r_dropWire$whas, + slave_xactor_ug_slave_u_w_putWire$whas; + + // register master_xactor_clearing + reg master_xactor_clearing; + wire master_xactor_clearing$D_IN, master_xactor_clearing$EN; + + // register master_xactor_shim_arff_rv + reg [97 : 0] master_xactor_shim_arff_rv; + wire [97 : 0] master_xactor_shim_arff_rv$D_IN; + wire master_xactor_shim_arff_rv$EN; + + // register master_xactor_shim_awff_rv + reg [97 : 0] master_xactor_shim_awff_rv; + wire [97 : 0] master_xactor_shim_awff_rv$D_IN; + wire master_xactor_shim_awff_rv$EN; + + // register master_xactor_shim_bff_rv + reg [6 : 0] master_xactor_shim_bff_rv; + wire [6 : 0] master_xactor_shim_bff_rv$D_IN; + wire master_xactor_shim_bff_rv$EN; + + // register master_xactor_shim_rff_rv + reg [71 : 0] master_xactor_shim_rff_rv; + wire [71 : 0] master_xactor_shim_rff_rv$D_IN; + wire master_xactor_shim_rff_rv$EN; + + // register master_xactor_shim_wff_rv + reg [73 : 0] master_xactor_shim_wff_rv; + wire [73 : 0] master_xactor_shim_wff_rv$D_IN; + wire master_xactor_shim_wff_rv$EN; + + // register slave_xactor_clearing + reg slave_xactor_clearing; + wire slave_xactor_clearing$D_IN, slave_xactor_clearing$EN; + + // register slave_xactor_shim_arff_rv + reg [97 : 0] slave_xactor_shim_arff_rv; + wire [97 : 0] slave_xactor_shim_arff_rv$D_IN; + wire slave_xactor_shim_arff_rv$EN; + + // register slave_xactor_shim_awff_rv + reg [97 : 0] slave_xactor_shim_awff_rv; + wire [97 : 0] slave_xactor_shim_awff_rv$D_IN; + wire slave_xactor_shim_awff_rv$EN; + + // register slave_xactor_shim_bff_rv + reg [6 : 0] slave_xactor_shim_bff_rv; + wire [6 : 0] slave_xactor_shim_bff_rv$D_IN; + wire slave_xactor_shim_bff_rv$EN; + + // register slave_xactor_shim_rff_rv + reg [71 : 0] slave_xactor_shim_rff_rv; + wire [71 : 0] slave_xactor_shim_rff_rv$D_IN; + wire slave_xactor_shim_rff_rv$EN; + + // register slave_xactor_shim_wff_rv + reg [73 : 0] slave_xactor_shim_wff_rv; + wire [73 : 0] slave_xactor_shim_wff_rv$D_IN; + wire slave_xactor_shim_wff_rv$EN; + // ports of submodule f_trace_data wire [233 : 0] f_trace_data$D_IN, f_trace_data$D_OUT; wire f_trace_data$CLR, @@ -474,278 +1017,278 @@ module mkDM_Mem_Tap(CLK, f_trace_data$ENQ, f_trace_data$FULL_N; - // ports of submodule master_xactor_f_rd_addr - wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT; - wire master_xactor_f_rd_addr$CLR, - master_xactor_f_rd_addr$DEQ, - master_xactor_f_rd_addr$EMPTY_N, - master_xactor_f_rd_addr$ENQ, - master_xactor_f_rd_addr$FULL_N; - - // ports of submodule master_xactor_f_rd_data - wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT; - wire master_xactor_f_rd_data$CLR, - master_xactor_f_rd_data$DEQ, - master_xactor_f_rd_data$EMPTY_N, - master_xactor_f_rd_data$ENQ, - master_xactor_f_rd_data$FULL_N; - - // ports of submodule master_xactor_f_wr_addr - wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT; - wire master_xactor_f_wr_addr$CLR, - master_xactor_f_wr_addr$DEQ, - master_xactor_f_wr_addr$EMPTY_N, - master_xactor_f_wr_addr$ENQ, - master_xactor_f_wr_addr$FULL_N; - - // ports of submodule master_xactor_f_wr_data - wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT; - wire master_xactor_f_wr_data$CLR, - master_xactor_f_wr_data$DEQ, - master_xactor_f_wr_data$EMPTY_N, - master_xactor_f_wr_data$ENQ, - master_xactor_f_wr_data$FULL_N; - - // ports of submodule master_xactor_f_wr_resp - wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT; - wire master_xactor_f_wr_resp$CLR, - master_xactor_f_wr_resp$DEQ, - master_xactor_f_wr_resp$EMPTY_N, - master_xactor_f_wr_resp$ENQ, - master_xactor_f_wr_resp$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - // rule scheduling signals - wire CAN_FIRE_RL_rl_connect, - CAN_FIRE_RL_rl_connect_1, - CAN_FIRE_RL_rl_connect_2, + wire CAN_FIRE_RL_master_xactor_do_clear, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut, + CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut, + CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_mkConnectionGetPut, + CAN_FIRE_RL_mkConnectionGetPut_1, + CAN_FIRE_RL_mkConnectionGetPut_2, + CAN_FIRE_RL_slave_xactor_do_clear, + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut, CAN_FIRE_RL_write_reqs, - CAN_FIRE_master_m_arready, - CAN_FIRE_master_m_awready, - CAN_FIRE_master_m_bvalid, - CAN_FIRE_master_m_rvalid, - CAN_FIRE_master_m_wready, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, + CAN_FIRE_master_ar_arready, + CAN_FIRE_master_aw_awready, + CAN_FIRE_master_b_bflit, + CAN_FIRE_master_r_rflit, + CAN_FIRE_master_w_wready, + CAN_FIRE_slave_ar_arflit, + CAN_FIRE_slave_aw_awflit, + CAN_FIRE_slave_b_bready, + CAN_FIRE_slave_r_rready, + CAN_FIRE_slave_w_wflit, CAN_FIRE_trace_data_out_get, - WILL_FIRE_RL_rl_connect, - WILL_FIRE_RL_rl_connect_1, - WILL_FIRE_RL_rl_connect_2, + WILL_FIRE_RL_master_xactor_do_clear, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut, + WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut, + WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_mkConnectionGetPut, + WILL_FIRE_RL_mkConnectionGetPut_1, + WILL_FIRE_RL_mkConnectionGetPut_2, + WILL_FIRE_RL_slave_xactor_do_clear, + WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_w_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut, WILL_FIRE_RL_write_reqs, - WILL_FIRE_master_m_arready, - WILL_FIRE_master_m_awready, - WILL_FIRE_master_m_bvalid, - WILL_FIRE_master_m_rvalid, - WILL_FIRE_master_m_wready, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid, + WILL_FIRE_master_ar_arready, + WILL_FIRE_master_aw_awready, + WILL_FIRE_master_b_bflit, + WILL_FIRE_master_r_rflit, + WILL_FIRE_master_w_wready, + WILL_FIRE_slave_ar_arflit, + WILL_FIRE_slave_aw_awflit, + WILL_FIRE_slave_b_bready, + WILL_FIRE_slave_r_rready, + WILL_FIRE_slave_w_wflit, WILL_FIRE_trace_data_out_get; // remaining internal signals - wire [63 : 0] stval___1__h1520, x__h1518, y_avValue_fst__h1430; - wire slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8; + wire [96 : 0] master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3, + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1; + wire [72 : 0] master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q2; + wire [63 : 0] stval___1__h6721, x__h6719, y_avValue_fst__h6631; + wire slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97; - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; + // action method slave_aw_awflit + assign CAN_FIRE_slave_aw_awflit = 1'd1 ; + assign WILL_FIRE_slave_aw_awflit = slave_awvalid ; - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; + // value method slave_aw_awready + assign slave_awready = !slave_xactor_shim_awff_rv[97] ; - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; + // action method slave_w_wflit + assign CAN_FIRE_slave_w_wflit = 1'd1 ; + assign WILL_FIRE_slave_w_wflit = slave_wvalid ; - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; + // value method slave_w_wready + assign slave_wready = !slave_xactor_shim_wff_rv[73] ; - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; + // value method slave_b_bid + assign slave_bid = slave_xactor_ug_slave_u_b_peekWire$wget[5:2] ; - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; + // value method slave_b_bresp + assign slave_bresp = slave_xactor_ug_slave_u_b_peekWire$wget[1:0] ; - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; + // value method slave_b_bvalid + assign slave_bvalid = CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek ; - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; + // action method slave_b_bready + assign CAN_FIRE_slave_b_bready = 1'd1 ; + assign WILL_FIRE_slave_b_bready = 1'd1 ; - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; + // action method slave_ar_arflit + assign CAN_FIRE_slave_ar_arflit = 1'd1 ; + assign WILL_FIRE_slave_ar_arflit = slave_arvalid ; - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; + // value method slave_ar_arready + assign slave_arready = !slave_xactor_shim_arff_rv[97] ; - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; + // value method slave_r_rid + assign slave_rid = slave_xactor_ug_slave_u_r_peekWire$wget[70:67] ; - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; + // value method slave_r_rdata + assign slave_rdata = slave_xactor_ug_slave_u_r_peekWire$wget[66:3] ; - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; + // value method slave_r_rresp + assign slave_rresp = slave_xactor_ug_slave_u_r_peekWire$wget[2:1] ; - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; + // value method slave_r_rlast + assign slave_rlast = slave_xactor_ug_slave_u_r_peekWire$wget[0] ; - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; + // value method slave_r_rvalid + assign slave_rvalid = CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek ; - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; + // action method slave_r_rready + assign CAN_FIRE_slave_r_rready = 1'd1 ; + assign WILL_FIRE_slave_r_rready = 1'd1 ; - // value method master_m_awvalid - assign master_awvalid = master_xactor_f_wr_addr$EMPTY_N ; + // value method master_aw_awid + assign master_awid = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[96:93] ; - // value method master_m_awid - assign master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ; + // value method master_aw_awaddr + assign master_awaddr = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[92:29] ; - // value method master_m_awaddr - assign master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ; + // value method master_aw_awlen + assign master_awlen = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[28:21] ; - // value method master_m_awlen - assign master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ; + // value method master_aw_awsize + assign master_awsize = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[20:18] ; - // value method master_m_awsize - assign master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ; + // value method master_aw_awburst + assign master_awburst = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[17:16] ; - // value method master_m_awburst - assign master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ; + // value method master_aw_awlock + assign master_awlock = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[15] ; - // value method master_m_awlock - assign master_awlock = master_xactor_f_wr_addr$D_OUT[15] ; + // value method master_aw_awcache + assign master_awcache = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[14:11] ; - // value method master_m_awcache - assign master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ; + // value method master_aw_awprot + assign master_awprot = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[10:8] ; - // value method master_m_awprot - assign master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ; + // value method master_aw_awqos + assign master_awqos = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[7:4] ; - // value method master_m_awqos - assign master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ; + // value method master_aw_awregion + assign master_awregion = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[3:0] ; - // value method master_m_awregion - assign master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ; + // value method master_aw_awvalid + assign master_awvalid = CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; - // action method master_m_awready - assign CAN_FIRE_master_m_awready = 1'd1 ; - assign WILL_FIRE_master_m_awready = 1'd1 ; + // action method master_aw_awready + assign CAN_FIRE_master_aw_awready = 1'd1 ; + assign WILL_FIRE_master_aw_awready = 1'd1 ; - // value method master_m_wvalid - assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ; + // value method master_w_wdata + assign master_wdata = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q2[72:9] ; - // value method master_m_wdata - assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ; + // value method master_w_wstrb + assign master_wstrb = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q2[8:1] ; - // value method master_m_wstrb - assign master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ; + // value method master_w_wlast + assign master_wlast = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q2[0] ; - // value method master_m_wlast - assign master_wlast = master_xactor_f_wr_data$D_OUT[0] ; + // value method master_w_wvalid + assign master_wvalid = CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; - // action method master_m_wready - assign CAN_FIRE_master_m_wready = 1'd1 ; - assign WILL_FIRE_master_m_wready = 1'd1 ; + // action method master_w_wready + assign CAN_FIRE_master_w_wready = 1'd1 ; + assign WILL_FIRE_master_w_wready = 1'd1 ; - // action method master_m_bvalid - assign CAN_FIRE_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_master_m_bvalid = 1'd1 ; + // action method master_b_bflit + assign CAN_FIRE_master_b_bflit = 1'd1 ; + assign WILL_FIRE_master_b_bflit = master_bvalid ; - // value method master_m_bready - assign master_bready = master_xactor_f_wr_resp$FULL_N ; + // value method master_b_bready + assign master_bready = !master_xactor_shim_bff_rv[6] ; - // value method master_m_arvalid - assign master_arvalid = master_xactor_f_rd_addr$EMPTY_N ; + // value method master_ar_arid + assign master_arid = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[96:93] ; - // value method master_m_arid - assign master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ; + // value method master_ar_araddr + assign master_araddr = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[92:29] ; - // value method master_m_araddr - assign master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ; + // value method master_ar_arlen + assign master_arlen = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[28:21] ; - // value method master_m_arlen - assign master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ; + // value method master_ar_arsize + assign master_arsize = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[20:18] ; - // value method master_m_arsize - assign master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ; + // value method master_ar_arburst + assign master_arburst = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[17:16] ; - // value method master_m_arburst - assign master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ; + // value method master_ar_arlock + assign master_arlock = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[15] ; - // value method master_m_arlock - assign master_arlock = master_xactor_f_rd_addr$D_OUT[15] ; + // value method master_ar_arcache + assign master_arcache = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[14:11] ; - // value method master_m_arcache - assign master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ; + // value method master_ar_arprot + assign master_arprot = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[10:8] ; - // value method master_m_arprot - assign master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ; + // value method master_ar_arqos + assign master_arqos = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[7:4] ; - // value method master_m_arqos - assign master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ; + // value method master_ar_arregion + assign master_arregion = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[3:0] ; - // value method master_m_arregion - assign master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ; + // value method master_ar_arvalid + assign master_arvalid = CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; - // action method master_m_arready - assign CAN_FIRE_master_m_arready = 1'd1 ; - assign WILL_FIRE_master_m_arready = 1'd1 ; + // action method master_ar_arready + assign CAN_FIRE_master_ar_arready = 1'd1 ; + assign WILL_FIRE_master_ar_arready = 1'd1 ; - // action method master_m_rvalid - assign CAN_FIRE_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_master_m_rvalid = 1'd1 ; + // action method master_r_rflit + assign CAN_FIRE_master_r_rflit = 1'd1 ; + assign WILL_FIRE_master_r_rflit = master_rvalid ; - // value method master_m_rready - assign master_rready = master_xactor_f_rd_data$FULL_N ; + // value method master_r_rready + assign master_rready = !master_xactor_shim_rff_rv[71] ; // actionvalue method trace_data_out_get assign trace_data_out_get = f_trace_data$D_OUT ; @@ -764,222 +1307,216 @@ module mkDM_Mem_Tap(CLK, .FULL_N(f_trace_data$FULL_N), .EMPTY_N(f_trace_data$EMPTY_N)); - // submodule master_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(master_xactor_f_rd_addr$D_IN), - .ENQ(master_xactor_f_rd_addr$ENQ), - .DEQ(master_xactor_f_rd_addr$DEQ), - .CLR(master_xactor_f_rd_addr$CLR), - .D_OUT(master_xactor_f_rd_addr$D_OUT), - .FULL_N(master_xactor_f_rd_addr$FULL_N), - .EMPTY_N(master_xactor_f_rd_addr$EMPTY_N)); - - // submodule master_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(master_xactor_f_rd_data$D_IN), - .ENQ(master_xactor_f_rd_data$ENQ), - .DEQ(master_xactor_f_rd_data$DEQ), - .CLR(master_xactor_f_rd_data$CLR), - .D_OUT(master_xactor_f_rd_data$D_OUT), - .FULL_N(master_xactor_f_rd_data$FULL_N), - .EMPTY_N(master_xactor_f_rd_data$EMPTY_N)); - - // submodule master_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(master_xactor_f_wr_addr$D_IN), - .ENQ(master_xactor_f_wr_addr$ENQ), - .DEQ(master_xactor_f_wr_addr$DEQ), - .CLR(master_xactor_f_wr_addr$CLR), - .D_OUT(master_xactor_f_wr_addr$D_OUT), - .FULL_N(master_xactor_f_wr_addr$FULL_N), - .EMPTY_N(master_xactor_f_wr_addr$EMPTY_N)); - - // submodule master_xactor_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(master_xactor_f_wr_data$D_IN), - .ENQ(master_xactor_f_wr_data$ENQ), - .DEQ(master_xactor_f_wr_data$DEQ), - .CLR(master_xactor_f_wr_data$CLR), - .D_OUT(master_xactor_f_wr_data$D_OUT), - .FULL_N(master_xactor_f_wr_data$FULL_N), - .EMPTY_N(master_xactor_f_wr_data$EMPTY_N)); - - // submodule master_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(master_xactor_f_wr_resp$D_IN), - .ENQ(master_xactor_f_wr_resp$ENQ), - .DEQ(master_xactor_f_wr_resp$DEQ), - .CLR(master_xactor_f_wr_resp$CLR), - .D_OUT(master_xactor_f_wr_resp$D_OUT), - .FULL_N(master_xactor_f_wr_resp$FULL_N), - .EMPTY_N(master_xactor_f_wr_resp$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); + // rule RL_slave_xactor_ug_slave_u_aw_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut = + slave_xactor_ug_slave_u_aw_putWire$whas && + slave_xactor_shim_awff_rv[97] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_aw_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut = + !slave_xactor_shim_awff_rv[97] && + slave_xactor_ug_slave_u_aw_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut ; + + // rule RL_slave_xactor_ug_slave_u_w_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut = + slave_xactor_ug_slave_u_w_putWire$whas && + slave_xactor_shim_wff_rv[73] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_w_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut = + !slave_xactor_shim_wff_rv[73] && + slave_xactor_ug_slave_u_w_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_w_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut ; // rule RL_write_reqs assign CAN_FIRE_RL_write_reqs = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8 ; + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_awff_rv$port1__read[97] && + slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97 ; assign WILL_FIRE_RL_write_reqs = CAN_FIRE_RL_write_reqs ; - // rule RL_rl_connect - assign CAN_FIRE_RL_rl_connect = - master_xactor_f_rd_addr$FULL_N && - slave_xactor_f_rd_addr$EMPTY_N ; - assign WILL_FIRE_RL_rl_connect = CAN_FIRE_RL_rl_connect ; - - // rule RL_rl_connect_1 - assign CAN_FIRE_RL_rl_connect_1 = - slave_xactor_f_wr_resp$FULL_N && - master_xactor_f_wr_resp$EMPTY_N ; - assign WILL_FIRE_RL_rl_connect_1 = CAN_FIRE_RL_rl_connect_1 ; - - // rule RL_rl_connect_2 - assign CAN_FIRE_RL_rl_connect_2 = - slave_xactor_f_rd_data$FULL_N && - master_xactor_f_rd_data$EMPTY_N ; - assign WILL_FIRE_RL_rl_connect_2 = CAN_FIRE_RL_rl_connect_2 ; - - // submodule f_trace_data - assign f_trace_data$D_IN = - { 106'h12AAAAAAA955555554A00000002, - x__h1518[31:0], - slave_xactor_f_wr_addr$D_OUT[92:29], - 32'hAAAAAAAA } ; - assign f_trace_data$ENQ = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8 ; - assign f_trace_data$DEQ = EN_trace_data_out_get ; - assign f_trace_data$CLR = 1'b0 ; - - // submodule master_xactor_f_rd_addr - assign master_xactor_f_rd_addr$D_IN = slave_xactor_f_rd_addr$D_OUT ; - assign master_xactor_f_rd_addr$ENQ = CAN_FIRE_RL_rl_connect ; - assign master_xactor_f_rd_addr$DEQ = - master_xactor_f_rd_addr$EMPTY_N && master_arready ; - assign master_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule master_xactor_f_rd_data - assign master_xactor_f_rd_data$D_IN = - { master_rid, master_rdata, master_rresp, master_rlast } ; - assign master_xactor_f_rd_data$ENQ = - master_rvalid && master_xactor_f_rd_data$FULL_N ; - assign master_xactor_f_rd_data$DEQ = CAN_FIRE_RL_rl_connect_2 ; - assign master_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule master_xactor_f_wr_addr - assign master_xactor_f_wr_addr$D_IN = slave_xactor_f_wr_addr$D_OUT ; - assign master_xactor_f_wr_addr$ENQ = CAN_FIRE_RL_write_reqs ; - assign master_xactor_f_wr_addr$DEQ = - master_xactor_f_wr_addr$EMPTY_N && master_awready ; - assign master_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule master_xactor_f_wr_data - assign master_xactor_f_wr_data$D_IN = slave_xactor_f_wr_data$D_OUT ; - assign master_xactor_f_wr_data$ENQ = CAN_FIRE_RL_write_reqs ; - assign master_xactor_f_wr_data$DEQ = - master_xactor_f_wr_data$EMPTY_N && master_wready ; - assign master_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule master_xactor_f_wr_resp - assign master_xactor_f_wr_resp$D_IN = { master_bid, master_bresp } ; - assign master_xactor_f_wr_resp$ENQ = - master_bvalid && master_xactor_f_wr_resp$FULL_N ; - assign master_xactor_f_wr_resp$DEQ = CAN_FIRE_RL_rl_connect_1 ; - assign master_xactor_f_wr_resp$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = - master_xactor_f_rd_addr$FULL_N && - slave_xactor_f_rd_addr$EMPTY_N ; - assign slave_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = master_xactor_f_rd_data$D_OUT ; - assign slave_xactor_f_rd_data$ENQ = - slave_xactor_f_rd_data$FULL_N && - master_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = + // rule RL_slave_xactor_ug_slave_u_ar_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut = + slave_xactor_ug_slave_u_ar_putWire$whas && + slave_xactor_shim_arff_rv[97] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_ar_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut = + !slave_xactor_shim_arff_rv[97] && + slave_xactor_ug_slave_u_ar_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut ; + + // rule RL_mkConnectionGetPut + assign CAN_FIRE_RL_mkConnectionGetPut = + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_arff_rv$port1__read[97] && + !master_xactor_shim_arff_rv[97] ; + assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; + + // rule RL_master_xactor_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; + + // rule RL_master_xactor_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = + master_xactor_ug_master_u_aw_dropWire$whas && + !master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + master_xactor_shim_awff_rv$port1__read[97] && + master_xactor_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ; + + // rule RL_master_xactor_ug_master_u_w_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + + // rule RL_master_xactor_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = + master_xactor_ug_master_u_w_dropWire$whas && + !master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_w_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + master_xactor_shim_wff_rv$port1__read[73] && + master_xactor_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ; + + // rule RL_master_xactor_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = + master_xactor_ug_master_u_b_putWire$whas && + master_xactor_shim_bff_rv[6] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut ; + + // rule RL_master_xactor_ug_master_u_b_doPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut = + !master_xactor_shim_bff_rv[6] && + master_xactor_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut = + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ; + + // rule RL_mkConnectionGetPut_1 + assign CAN_FIRE_RL_mkConnectionGetPut_1 = + !slave_xactor_clearing && !master_xactor_clearing && + master_xactor_shim_bff_rv$port1__read[6] && + !slave_xactor_shim_bff_rv[6] ; + assign WILL_FIRE_RL_mkConnectionGetPut_1 = + CAN_FIRE_RL_mkConnectionGetPut_1 ; + + // rule RL_slave_xactor_ug_slave_u_b_setPeek + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek = + slave_xactor_shim_bff_rv$port1__read[6] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek ; + + // rule RL_slave_xactor_ug_slave_u_b_warnDoDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop = + slave_xactor_ug_slave_u_b_dropWire$whas && + !slave_xactor_shim_bff_rv$port1__read[6] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop ; + + // rule RL_slave_xactor_ug_slave_u_b_doDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop = + slave_xactor_shim_bff_rv$port1__read[6] && + slave_xactor_ug_slave_u_b_dropWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop ; + + // rule RL_master_xactor_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + + // rule RL_master_xactor_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = + master_xactor_ug_master_u_ar_dropWire$whas && + !master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + master_xactor_shim_arff_rv$port1__read[97] && + master_xactor_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ; + + // rule RL_master_xactor_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = + master_xactor_ug_master_u_r_putWire$whas && + master_xactor_shim_rff_rv[71] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut ; + + // rule RL_master_xactor_ug_master_u_r_doPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut = + !master_xactor_shim_rff_rv[71] && + master_xactor_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut = + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ; + + // rule RL_mkConnectionGetPut_2 + assign CAN_FIRE_RL_mkConnectionGetPut_2 = + !slave_xactor_clearing && !master_xactor_clearing && + master_xactor_shim_rff_rv$port1__read[71] && + !slave_xactor_shim_rff_rv[71] ; + assign WILL_FIRE_RL_mkConnectionGetPut_2 = + CAN_FIRE_RL_mkConnectionGetPut_2 ; + + // rule RL_slave_xactor_ug_slave_u_r_setPeek + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek = + slave_xactor_shim_rff_rv$port1__read[71] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek ; + + // rule RL_slave_xactor_ug_slave_u_r_warnDoDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop = + slave_xactor_ug_slave_u_r_dropWire$whas && + !slave_xactor_shim_rff_rv$port1__read[71] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop ; + + // rule RL_slave_xactor_ug_slave_u_r_doDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop = + slave_xactor_shim_rff_rv$port1__read[71] && + slave_xactor_ug_slave_u_r_dropWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop ; + + // rule RL_slave_xactor_do_clear + assign CAN_FIRE_RL_slave_xactor_do_clear = slave_xactor_clearing ; + assign WILL_FIRE_RL_slave_xactor_do_clear = slave_xactor_clearing ; + + // rule RL_master_xactor_do_clear + assign CAN_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; + assign WILL_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; + + // inlined wires + assign slave_xactor_ug_slave_u_aw_putWire$wget = { slave_awid, slave_awaddr, slave_awlen, @@ -990,44 +1527,426 @@ module mkDM_Mem_Tap(CLK, slave_awprot, slave_awqos, slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8 ; - assign slave_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = + assign slave_xactor_ug_slave_u_aw_putWire$whas = + slave_awvalid && !slave_xactor_shim_awff_rv[97] ; + assign slave_xactor_ug_slave_u_w_putWire$wget = { slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8 ; - assign slave_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = master_xactor_f_wr_resp$D_OUT ; - assign slave_xactor_f_wr_resp$ENQ = - slave_xactor_f_wr_resp$FULL_N && - master_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = 1'b0 ; + assign slave_xactor_ug_slave_u_w_putWire$whas = + slave_wvalid && !slave_xactor_shim_wff_rv[73] ; + assign slave_xactor_ug_slave_u_b_peekWire$wget = + slave_xactor_shim_bff_rv$port1__read[5:0] ; + assign slave_xactor_ug_slave_u_ar_putWire$wget = + { slave_arid, + slave_araddr, + slave_arlen, + slave_arsize, + slave_arburst, + slave_arlock, + slave_arcache, + slave_arprot, + slave_arqos, + slave_arregion } ; + assign slave_xactor_ug_slave_u_ar_putWire$whas = + slave_arvalid && !slave_xactor_shim_arff_rv[97] ; + assign slave_xactor_ug_slave_u_r_peekWire$wget = + slave_xactor_shim_rff_rv$port1__read[70:0] ; + assign master_xactor_ug_master_u_b_putWire$wget = + { master_bid, master_bresp } ; + assign master_xactor_ug_master_u_b_putWire$whas = + master_bvalid && !master_xactor_shim_bff_rv[6] ; + assign master_xactor_ug_master_u_r_putWire$wget = + { master_rid, master_rdata, master_rresp, master_rlast } ; + assign master_xactor_ug_master_u_r_putWire$whas = + master_rvalid && !master_xactor_shim_rff_rv[71] ; + assign slave_xactor_ug_slave_u_b_dropWire$whas = + slave_xactor_shim_bff_rv$port1__read[6] && slave_bready ; + assign slave_xactor_ug_slave_u_r_dropWire$whas = + slave_xactor_shim_rff_rv$port1__read[71] && slave_rready ; + assign master_xactor_ug_master_u_aw_dropWire$whas = + master_xactor_shim_awff_rv$port1__read[97] && master_awready ; + assign master_xactor_ug_master_u_w_dropWire$whas = + master_xactor_shim_wff_rv$port1__read[73] && master_wready ; + assign master_xactor_ug_master_u_ar_dropWire$whas = + master_xactor_shim_arff_rv$port1__read[97] && master_arready ; + assign slave_xactor_shim_awff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_aw_putWire$wget } ; + assign slave_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut ? + slave_xactor_shim_awff_rv$port0__write_1 : + slave_xactor_shim_awff_rv ; + assign slave_xactor_shim_awff_rv$EN_port1__write = + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_awff_rv$port1__read[97] && + slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97 ; + assign slave_xactor_shim_awff_rv$port2__read = + slave_xactor_shim_awff_rv$EN_port1__write ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_awff_rv$port1__read ; + assign slave_xactor_shim_awff_rv$port3__read = + slave_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_awff_rv$port2__read ; + assign slave_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_w_putWire$wget } ; + assign slave_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut ? + slave_xactor_shim_wff_rv$port0__write_1 : + slave_xactor_shim_wff_rv ; + assign slave_xactor_shim_wff_rv$EN_port1__write = + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_awff_rv$port1__read[97] && + slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97 ; + assign slave_xactor_shim_wff_rv$port2__read = + slave_xactor_shim_wff_rv$EN_port1__write ? + 74'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_wff_rv$port1__read ; + assign slave_xactor_shim_wff_rv$port3__read = + slave_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_wff_rv$port2__read ; + assign slave_xactor_shim_bff_rv$EN_port0__write = + !slave_xactor_clearing && !master_xactor_clearing && + master_xactor_shim_bff_rv$port1__read[6] && + !slave_xactor_shim_bff_rv[6] ; + assign slave_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, master_xactor_shim_bff_rv$port1__read[5:0] } ; + assign slave_xactor_shim_bff_rv$port1__read = + slave_xactor_shim_bff_rv$EN_port0__write ? + slave_xactor_shim_bff_rv$port0__write_1 : + slave_xactor_shim_bff_rv ; + assign slave_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop ? + 7'd42 : + slave_xactor_shim_bff_rv$port1__read ; + assign slave_xactor_shim_bff_rv$port3__read = + slave_xactor_clearing ? + 7'd42 : + slave_xactor_shim_bff_rv$port2__read ; + assign slave_xactor_shim_arff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_ar_putWire$wget } ; + assign slave_xactor_shim_arff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut ? + slave_xactor_shim_arff_rv$port0__write_1 : + slave_xactor_shim_arff_rv ; + assign slave_xactor_shim_arff_rv$EN_port1__write = + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_arff_rv$port1__read[97] && + !master_xactor_shim_arff_rv[97] ; + assign slave_xactor_shim_arff_rv$port2__read = + slave_xactor_shim_arff_rv$EN_port1__write ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_arff_rv$port1__read ; + assign slave_xactor_shim_arff_rv$port3__read = + slave_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_arff_rv$port2__read ; + assign slave_xactor_shim_rff_rv$EN_port0__write = + !slave_xactor_clearing && !master_xactor_clearing && + master_xactor_shim_rff_rv$port1__read[71] && + !slave_xactor_shim_rff_rv[71] ; + assign slave_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, master_xactor_shim_rff_rv$port1__read[70:0] } ; + assign slave_xactor_shim_rff_rv$port1__read = + slave_xactor_shim_rff_rv$EN_port0__write ? + slave_xactor_shim_rff_rv$port0__write_1 : + slave_xactor_shim_rff_rv ; + assign slave_xactor_shim_rff_rv$port2__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop ? + 72'h2AAAAAAAAAAAAAAAAA : + slave_xactor_shim_rff_rv$port1__read ; + assign slave_xactor_shim_rff_rv$port3__read = + slave_xactor_clearing ? + 72'h2AAAAAAAAAAAAAAAAA : + slave_xactor_shim_rff_rv$port2__read ; + assign master_xactor_shim_awff_rv$port0__write_1 = + { 1'd1, slave_xactor_shim_awff_rv$port1__read[96:0] } ; + assign master_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_write_reqs ? + master_xactor_shim_awff_rv$port0__write_1 : + master_xactor_shim_awff_rv ; + assign master_xactor_shim_awff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_awff_rv$port1__read ; + assign master_xactor_shim_awff_rv$port3__read = + master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_awff_rv$port2__read ; + assign master_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, slave_xactor_shim_wff_rv$port1__read[72:0] } ; + assign master_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_write_reqs ? + master_xactor_shim_wff_rv$port0__write_1 : + master_xactor_shim_wff_rv ; + assign master_xactor_shim_wff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + master_xactor_shim_wff_rv$port1__read ; + assign master_xactor_shim_wff_rv$port3__read = + master_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + master_xactor_shim_wff_rv$port2__read ; + assign master_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, master_xactor_ug_master_u_b_putWire$wget } ; + assign master_xactor_shim_bff_rv$port1__read = + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ? + master_xactor_shim_bff_rv$port0__write_1 : + master_xactor_shim_bff_rv ; + assign master_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_mkConnectionGetPut_1 ? + 7'd42 : + master_xactor_shim_bff_rv$port1__read ; + assign master_xactor_shim_bff_rv$port3__read = + master_xactor_clearing ? + 7'd42 : + master_xactor_shim_bff_rv$port2__read ; + assign master_xactor_shim_arff_rv$port0__write_1 = + { 1'd1, slave_xactor_shim_arff_rv$port1__read[96:0] } ; + assign master_xactor_shim_arff_rv$port1__read = + CAN_FIRE_RL_mkConnectionGetPut ? + master_xactor_shim_arff_rv$port0__write_1 : + master_xactor_shim_arff_rv ; + assign master_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_arff_rv$port1__read ; + assign master_xactor_shim_arff_rv$port3__read = + master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_arff_rv$port2__read ; + assign master_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, master_xactor_ug_master_u_r_putWire$wget } ; + assign master_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ? + master_xactor_shim_rff_rv$port0__write_1 : + master_xactor_shim_rff_rv ; + assign master_xactor_shim_rff_rv$port2__read = + CAN_FIRE_RL_mkConnectionGetPut_2 ? + 72'h2AAAAAAAAAAAAAAAAA : + master_xactor_shim_rff_rv$port1__read ; + assign master_xactor_shim_rff_rv$port3__read = + master_xactor_clearing ? + 72'h2AAAAAAAAAAAAAAAAA : + master_xactor_shim_rff_rv$port2__read ; + + // register master_xactor_clearing + assign master_xactor_clearing$D_IN = 1'd0 ; + assign master_xactor_clearing$EN = master_xactor_clearing ; + + // register master_xactor_shim_arff_rv + assign master_xactor_shim_arff_rv$D_IN = + master_xactor_shim_arff_rv$port3__read ; + assign master_xactor_shim_arff_rv$EN = 1'b1 ; + + // register master_xactor_shim_awff_rv + assign master_xactor_shim_awff_rv$D_IN = + master_xactor_shim_awff_rv$port3__read ; + assign master_xactor_shim_awff_rv$EN = 1'b1 ; + + // register master_xactor_shim_bff_rv + assign master_xactor_shim_bff_rv$D_IN = + master_xactor_shim_bff_rv$port3__read ; + assign master_xactor_shim_bff_rv$EN = 1'b1 ; + + // register master_xactor_shim_rff_rv + assign master_xactor_shim_rff_rv$D_IN = + master_xactor_shim_rff_rv$port3__read ; + assign master_xactor_shim_rff_rv$EN = 1'b1 ; + + // register master_xactor_shim_wff_rv + assign master_xactor_shim_wff_rv$D_IN = + master_xactor_shim_wff_rv$port3__read ; + assign master_xactor_shim_wff_rv$EN = 1'b1 ; + + // register slave_xactor_clearing + assign slave_xactor_clearing$D_IN = 1'd0 ; + assign slave_xactor_clearing$EN = slave_xactor_clearing ; + + // register slave_xactor_shim_arff_rv + assign slave_xactor_shim_arff_rv$D_IN = + slave_xactor_shim_arff_rv$port3__read ; + assign slave_xactor_shim_arff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_awff_rv + assign slave_xactor_shim_awff_rv$D_IN = + slave_xactor_shim_awff_rv$port3__read ; + assign slave_xactor_shim_awff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_bff_rv + assign slave_xactor_shim_bff_rv$D_IN = + slave_xactor_shim_bff_rv$port3__read ; + assign slave_xactor_shim_bff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_rff_rv + assign slave_xactor_shim_rff_rv$D_IN = + slave_xactor_shim_rff_rv$port3__read ; + assign slave_xactor_shim_rff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_wff_rv + assign slave_xactor_shim_wff_rv$D_IN = + slave_xactor_shim_wff_rv$port3__read ; + assign slave_xactor_shim_wff_rv$EN = 1'b1 ; + + // submodule f_trace_data + assign f_trace_data$D_IN = + { 106'h12AAAAAAA955555554A00000002, + x__h6719[31:0], + slave_xactor_shim_awff_rv$port1__read[92:29], + 32'hAAAAAAAA } ; + assign f_trace_data$ENQ = + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_awff_rv$port1__read[97] && + slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97 ; + assign f_trace_data$DEQ = EN_trace_data_out_get ; + assign f_trace_data$CLR = 1'b0 ; // remaining internal signals - assign slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8 = - slave_xactor_f_wr_data$EMPTY_N && - master_xactor_f_wr_addr$FULL_N && - master_xactor_f_wr_data$FULL_N && + assign master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3 = + master_xactor_shim_arff_rv$port1__read[96:0] ; + assign master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1 = + master_xactor_shim_awff_rv$port1__read[96:0] ; + assign master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q2 = + master_xactor_shim_wff_rv$port1__read[72:0] ; + assign slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97 = + slave_xactor_shim_wff_rv$port1__read[73] && + !master_xactor_shim_awff_rv[97] && + !master_xactor_shim_wff_rv[73] && f_trace_data$FULL_N ; - assign stval___1__h1520 = { 32'd0, slave_xactor_f_wr_data$D_OUT[40:9] } ; - assign x__h1518 = - (slave_xactor_f_wr_data$D_OUT[8:1] == 8'h0F) ? - stval___1__h1520 : - y_avValue_fst__h1430 ; - assign y_avValue_fst__h1430 = - { 32'd0, slave_xactor_f_wr_data$D_OUT[72:41] } ; + assign stval___1__h6721 = + { 32'd0, slave_xactor_shim_wff_rv$port1__read[40:9] } ; + assign x__h6719 = + (slave_xactor_shim_wff_rv$port1__read[8:1] == 8'h0F) ? + stval___1__h6721 : + y_avValue_fst__h6631 ; + assign y_avValue_fst__h6631 = + { 32'd0, slave_xactor_shim_wff_rv$port1__read[72:41] } ; + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 7'd42; + master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 72'h2AAAAAAAAAAAAAAAAA; + master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 7'd42; + slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 72'h2AAAAAAAAAAAAAAAAA; + slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + end + else + begin + if (master_xactor_clearing$EN) + master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + master_xactor_clearing$D_IN; + if (master_xactor_shim_arff_rv$EN) + master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_arff_rv$D_IN; + if (master_xactor_shim_awff_rv$EN) + master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_awff_rv$D_IN; + if (master_xactor_shim_bff_rv$EN) + master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_bff_rv$D_IN; + if (master_xactor_shim_rff_rv$EN) + master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_rff_rv$D_IN; + if (master_xactor_shim_wff_rv$EN) + master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_wff_rv$D_IN; + if (slave_xactor_clearing$EN) + slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + slave_xactor_clearing$D_IN; + if (slave_xactor_shim_arff_rv$EN) + slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_arff_rv$D_IN; + if (slave_xactor_shim_awff_rv$EN) + slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_awff_rv$D_IN; + if (slave_xactor_shim_bff_rv$EN) + slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_bff_rv$D_IN; + if (slave_xactor_shim_rff_rv$EN) + slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_rff_rv$D_IN; + if (slave_xactor_shim_wff_rv$EN) + slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_wff_rv$D_IN; + end + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + master_xactor_clearing = 1'h0; + master_xactor_shim_arff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_awff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_bff_rv = 7'h2A; + master_xactor_shim_rff_rv = 72'hAAAAAAAAAAAAAAAAAA; + master_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + slave_xactor_clearing = 1'h0; + slave_xactor_shim_arff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_awff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_bff_rv = 7'h2A; + slave_xactor_shim_rff_rv = 72'hAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + end + // synopsys translate_on endmodule // mkDM_Mem_Tap diff --git a/src_SSITH_P1/Verilog_RTL/mkDM_Run_Control.v b/src_SSITH_P1/Verilog_RTL/mkDM_Run_Control.v index e375e3a1..2c0dfcd5 100644 --- a/src_SSITH_P1/Verilog_RTL/mkDM_Run_Control.v +++ b/src_SSITH_P1/Verilog_RTL/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:15 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkDM_System_Bus.v b/src_SSITH_P1/Verilog_RTL/mkDM_System_Bus.v index 2463761c..8ca3c72f 100644 --- a/src_SSITH_P1/Verilog_RTL/mkDM_System_Bus.v +++ b/src_SSITH_P1/Verilog_RTL/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:33 BST 2019 // // // Ports: @@ -10,33 +10,33 @@ // av_read O 32 // RDY_av_read O 1 // RDY_write O 1 +// master_awid O 4 +// master_awaddr O 64 +// master_awlen O 8 +// master_awsize O 3 +// master_awburst O 2 +// master_awlock O 1 +// master_awcache O 4 +// master_awprot O 3 +// master_awqos O 4 +// master_awregion O 4 // master_awvalid O 1 -// master_awid O 4 reg -// master_awaddr O 64 reg -// master_awlen O 8 reg -// master_awsize O 3 reg -// master_awburst O 2 reg -// master_awlock O 1 reg -// master_awcache O 4 reg -// master_awprot O 3 reg -// master_awqos O 4 reg -// master_awregion O 4 reg +// master_wdata O 64 +// master_wstrb O 8 +// master_wlast O 1 // master_wvalid O 1 -// master_wdata O 64 reg -// master_wstrb O 8 reg -// master_wlast O 1 reg -// master_bready O 1 const +// master_bready O 1 +// master_arid O 4 +// master_araddr O 64 +// master_arlen O 8 +// master_arsize O 3 +// master_arburst O 2 +// master_arlock O 1 +// master_arcache O 4 +// master_arprot O 3 +// master_arqos O 4 +// master_arregion O 4 // master_arvalid O 1 -// master_arid O 4 reg -// master_araddr O 64 reg -// master_arlen O 8 reg -// master_arsize O 3 reg -// master_arburst O 2 reg -// master_arlock O 1 reg -// master_arcache O 4 reg -// master_arprot O 3 reg -// master_arqos O 4 reg -// master_arregion O 4 reg // master_rready O 1 // CLK I 1 clock // RST_N I 1 reset @@ -45,23 +45,265 @@ // write_dm_word I 32 // master_awready I 1 // master_wready I 1 -// master_bvalid I 1 -// master_bid I 4 reg -// master_bresp I 2 reg +// master_bid I 4 +// master_bresp I 2 // master_arready I 1 -// master_rvalid I 1 -// master_rid I 4 reg -// master_rdata I 64 reg -// master_rresp I 2 reg -// master_rlast I 1 reg +// master_rid I 4 +// master_rdata I 64 +// master_rresp I 2 +// master_rlast I 1 // EN_reset I 1 // EN_write I 1 +// master_bvalid I 1 +// master_rvalid I 1 // EN_av_read I 1 // // Combinational paths from inputs to outputs: -// (master_awready, master_wready, master_arready) -> RDY_write -// master_arready -> RDY_av_read -// (master_arready, av_read_dm_addr) -> av_read +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awid +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awaddr +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awlen +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awsize +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awburst +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awlock +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awcache +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awprot +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awqos +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awregion +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awuser +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awvalid +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_wdata +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_wstrb +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_wlast +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_wuser +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_wvalid +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arid +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_araddr +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arlen +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arsize +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arburst +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arlock +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arcache +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arprot +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arqos +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arregion +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_aruser +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arvalid +// av_read_dm_addr -> av_read // // @@ -94,8 +336,6 @@ module mkDM_System_Bus(CLK, EN_write, RDY_write, - master_awvalid, - master_awid, master_awaddr, @@ -116,9 +356,9 @@ module mkDM_System_Bus(CLK, master_awregion, - master_awready, + master_awvalid, - master_wvalid, + master_awready, master_wdata, @@ -126,16 +366,16 @@ module mkDM_System_Bus(CLK, master_wlast, + master_wvalid, + master_wready, - master_bvalid, master_bid, master_bresp, + master_bvalid, master_bready, - master_arvalid, - master_arid, master_araddr, @@ -156,13 +396,15 @@ module mkDM_System_Bus(CLK, master_arregion, + master_arvalid, + master_arready, - master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, + master_rvalid, master_rready); input CLK; @@ -184,115 +426,115 @@ module mkDM_System_Bus(CLK, input EN_write; output RDY_write; - // value method master_m_awvalid - output master_awvalid; - - // value method master_m_awid + // value method master_aw_awid output [3 : 0] master_awid; - // value method master_m_awaddr + // value method master_aw_awaddr output [63 : 0] master_awaddr; - // value method master_m_awlen + // value method master_aw_awlen output [7 : 0] master_awlen; - // value method master_m_awsize + // value method master_aw_awsize output [2 : 0] master_awsize; - // value method master_m_awburst + // value method master_aw_awburst output [1 : 0] master_awburst; - // value method master_m_awlock + // value method master_aw_awlock output master_awlock; - // value method master_m_awcache + // value method master_aw_awcache output [3 : 0] master_awcache; - // value method master_m_awprot + // value method master_aw_awprot output [2 : 0] master_awprot; - // value method master_m_awqos + // value method master_aw_awqos output [3 : 0] master_awqos; - // value method master_m_awregion + // value method master_aw_awregion output [3 : 0] master_awregion; - // value method master_m_awuser + // value method master_aw_awuser - // action method master_m_awready - input master_awready; + // value method master_aw_awvalid + output master_awvalid; - // value method master_m_wvalid - output master_wvalid; + // action method master_aw_awready + input master_awready; - // value method master_m_wdata + // value method master_w_wdata output [63 : 0] master_wdata; - // value method master_m_wstrb + // value method master_w_wstrb output [7 : 0] master_wstrb; - // value method master_m_wlast + // value method master_w_wlast output master_wlast; - // value method master_m_wuser + // value method master_w_wuser - // action method master_m_wready + // value method master_w_wvalid + output master_wvalid; + + // action method master_w_wready input master_wready; - // action method master_m_bvalid - input master_bvalid; + // action method master_b_bflit input [3 : 0] master_bid; input [1 : 0] master_bresp; + input master_bvalid; - // value method master_m_bready + // value method master_b_bready output master_bready; - // value method master_m_arvalid - output master_arvalid; - - // value method master_m_arid + // value method master_ar_arid output [3 : 0] master_arid; - // value method master_m_araddr + // value method master_ar_araddr output [63 : 0] master_araddr; - // value method master_m_arlen + // value method master_ar_arlen output [7 : 0] master_arlen; - // value method master_m_arsize + // value method master_ar_arsize output [2 : 0] master_arsize; - // value method master_m_arburst + // value method master_ar_arburst output [1 : 0] master_arburst; - // value method master_m_arlock + // value method master_ar_arlock output master_arlock; - // value method master_m_arcache + // value method master_ar_arcache output [3 : 0] master_arcache; - // value method master_m_arprot + // value method master_ar_arprot output [2 : 0] master_arprot; - // value method master_m_arqos + // value method master_ar_arqos output [3 : 0] master_arqos; - // value method master_m_arregion + // value method master_ar_arregion output [3 : 0] master_arregion; - // value method master_m_aruser + // value method master_ar_aruser + + // value method master_ar_arvalid + output master_arvalid; - // action method master_m_arready + // action method master_ar_arready input master_arready; - // action method master_m_rvalid - input master_rvalid; + // action method master_r_rflit input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; + input master_rvalid; - // value method master_m_rready + // value method master_r_rready output master_rready; // signals for module outputs @@ -322,64 +564,67 @@ module mkDM_System_Bus(CLK, master_wvalid; // inlined wires - wire master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - wire [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - wire [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [72 : 0] master_xactor_rg_wr_data; - wire [72 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; + wire [97 : 0] master_xactor_shim_arff_rv$port0__write_1, + master_xactor_shim_arff_rv$port1__read, + master_xactor_shim_arff_rv$port2__read, + master_xactor_shim_arff_rv$port3__read, + master_xactor_shim_awff_rv$port0__write_1, + master_xactor_shim_awff_rv$port1__read, + master_xactor_shim_awff_rv$port2__read, + master_xactor_shim_awff_rv$port3__read; + wire [73 : 0] master_xactor_shim_wff_rv$port0__write_1, + master_xactor_shim_wff_rv$port1__read, + master_xactor_shim_wff_rv$port2__read, + master_xactor_shim_wff_rv$port3__read; + wire [71 : 0] master_xactor_shim_rff_rv$port0__write_1, + master_xactor_shim_rff_rv$port1__read, + master_xactor_shim_rff_rv$port2__read, + master_xactor_shim_rff_rv$port3__read; + wire [70 : 0] master_xactor_ug_master_u_r_putWire$wget; + wire [6 : 0] master_xactor_shim_bff_rv$port0__write_1, + master_xactor_shim_bff_rv$port1__read, + master_xactor_shim_bff_rv$port2__read, + master_xactor_shim_bff_rv$port3__read; + wire [5 : 0] master_xactor_ug_master_u_b_putWire$wget; + wire master_xactor_shim_arff_rv$EN_port0__write, + master_xactor_shim_awff_rv$EN_port0__write, + master_xactor_shim_bff_rv$EN_port1__write, + master_xactor_shim_rff_rv$EN_port1__write, + master_xactor_shim_wff_rv$EN_port0__write, + master_xactor_ug_master_u_ar_dropWire$whas, + master_xactor_ug_master_u_aw_dropWire$whas, + master_xactor_ug_master_u_b_putWire$whas, + master_xactor_ug_master_u_r_putWire$whas, + master_xactor_ug_master_u_w_dropWire$whas; + + // register master_xactor_clearing + reg master_xactor_clearing; + wire master_xactor_clearing$D_IN, master_xactor_clearing$EN; + + // register master_xactor_shim_arff_rv + reg [97 : 0] master_xactor_shim_arff_rv; + wire [97 : 0] master_xactor_shim_arff_rv$D_IN; + wire master_xactor_shim_arff_rv$EN; + + // register master_xactor_shim_awff_rv + reg [97 : 0] master_xactor_shim_awff_rv; + wire [97 : 0] master_xactor_shim_awff_rv$D_IN; + wire master_xactor_shim_awff_rv$EN; + + // register master_xactor_shim_bff_rv + reg [6 : 0] master_xactor_shim_bff_rv; + wire [6 : 0] master_xactor_shim_bff_rv$D_IN; + wire master_xactor_shim_bff_rv$EN; + + // register master_xactor_shim_rff_rv + reg [71 : 0] master_xactor_shim_rff_rv; + wire [71 : 0] master_xactor_shim_rff_rv$D_IN; + wire master_xactor_shim_rff_rv$EN; + + // register master_xactor_shim_wff_rv + reg [73 : 0] master_xactor_shim_wff_rv; + wire [73 : 0] master_xactor_shim_wff_rv$D_IN; + wire master_xactor_shim_wff_rv$EN; // register rg_sb_state reg [1 : 0] rg_sb_state; @@ -434,33 +679,61 @@ module mkDM_System_Bus(CLK, wire rg_sbdata0$EN; // rule scheduling signals - wire CAN_FIRE_RL_rl_sb_read_finish, + wire CAN_FIRE_RL_master_xactor_do_clear, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut, + CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut, + CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_rl_sb_read_finish, CAN_FIRE_RL_rl_sb_write_response, CAN_FIRE_av_read, - CAN_FIRE_master_m_arready, - CAN_FIRE_master_m_awready, - CAN_FIRE_master_m_bvalid, - CAN_FIRE_master_m_rvalid, - CAN_FIRE_master_m_wready, + CAN_FIRE_master_ar_arready, + CAN_FIRE_master_aw_awready, + CAN_FIRE_master_b_bflit, + CAN_FIRE_master_r_rflit, + CAN_FIRE_master_w_wready, CAN_FIRE_reset, CAN_FIRE_write, + WILL_FIRE_RL_master_xactor_do_clear, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut, + WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut, + WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, WILL_FIRE_RL_rl_sb_read_finish, WILL_FIRE_RL_rl_sb_write_response, WILL_FIRE_av_read, - WILL_FIRE_master_m_arready, - WILL_FIRE_master_m_awready, - WILL_FIRE_master_m_bvalid, - WILL_FIRE_master_m_rvalid, - WILL_FIRE_master_m_wready, + WILL_FIRE_master_ar_arready, + WILL_FIRE_master_aw_awready, + WILL_FIRE_master_b_bflit, + WILL_FIRE_master_r_rflit, + WILL_FIRE_master_w_wready, WILL_FIRE_reset, WILL_FIRE_write; // inputs to muxes for submodule ports reg [31 : 0] MUX_rg_sbaddress0$write_1__VAL_2; reg [2 : 0] MUX_rg_sbcs_sberror$write_1__VAL_4; - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2; - wire MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1, + wire [97 : 0] MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1, + MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2; + wire MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1, MUX_rg_sbaddress0$write_1__SEL_2, MUX_rg_sbaddress0$write_1__SEL_3, MUX_rg_sbaddress1$write_1__SEL_2, @@ -473,48 +746,51 @@ module mkDM_System_Bus(CLK, // remaining internal signals reg [63 : 0] CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1, - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53, - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66, - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103, - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79, - wrd_wdata__h5077; - reg [7 : 0] wrd_wstrb__h5078; - reg [2 : 0] x__h3263, x__h4949; - wire [63 : 0] _theResult___fst__h4987, - addr64310_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2, - addr64__h4310, - result__h1836, - result__h1866, - result__h1893, - result__h1920, - result__h1947, - result__h1974, - result__h2001, - result__h2028, - result__h2073, - result__h2100, - result__h2127, - result__h2154, - result__h2195, - result__h2222, - sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3, - sbaddress__h1228, - word64__h4931; - wire [31 : 0] IF_rg_sbcs_sbreadonaddr_23_THEN_IF_rg_sbcs_sba_ETC___d307, - v__h2727, - v__h2861; - wire [7 : 0] strobe64__h4986, strobe64__h4989, strobe64__h4992; - wire [5 : 0] shift_bits__h4934; - wire rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109, - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313, - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95, - rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291, - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256, - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265, - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271, - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273, - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278, - write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d323; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103, + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116, + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154, + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129, + wrd_wdata__h7216; + reg [7 : 0] wrd_wstrb__h7217; + reg [2 : 0] _theResult___snd_snd_val__h7102, axi4_size_val__h5371; + wire [96 : 0] master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5, + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3; + wire [72 : 0] master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q4; + wire [63 : 0] _theResult___fst__h7087, + addr64393_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2, + addr64__h6393, + result__h3808, + result__h3838, + result__h3865, + result__h3892, + result__h3919, + result__h3946, + result__h3973, + result__h4000, + result__h4045, + result__h4072, + result__h4099, + result__h4126, + result__h4167, + result__h4194, + sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6, + sbaddress__h3099, + word64__h7032; + wire [31 : 0] IF_rg_sbcs_sbreadonaddr_74_THEN_IF_rg_sbcs_sba_ETC___d360, + v__h4783, + v__h4917; + wire [7 : 0] strobe64__h7085, strobe64__h7089, strobe64__h7093; + wire [5 : 0] shift_bits__h7035; + wire rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146, + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160, + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d366, + rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d344, + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309, + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d318, + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d324, + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d326, + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d331, + write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376; // action method reset assign RDY_reset = 1'd1 ; @@ -523,13 +799,13 @@ module mkDM_System_Bus(CLK, // actionvalue method av_read always@(av_read_dm_addr or - v__h2727 or rg_sbaddress0 or rg_sbaddress1 or v__h2861) + v__h4783 or rg_sbaddress0 or rg_sbaddress1 or v__h4917) begin case (av_read_dm_addr) - 7'h38: av_read = v__h2727; + 7'h38: av_read = v__h4783; 7'h39: av_read = rg_sbaddress0; 7'h3A: av_read = rg_sbaddress1; - 7'h3C: av_read = v__h2861; + 7'h3C: av_read = v__h4917; default: av_read = 32'd0; endcase end @@ -537,7 +813,7 @@ module mkDM_System_Bus(CLK, rg_sb_state == 2'd0 && (rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || !rg_sbcs_sbreadondata || - !master_xactor_crg_rd_addr_full$port2__read) ; + !master_xactor_clearing && !master_xactor_shim_arff_rv[97]) ; assign CAN_FIRE_av_read = RDY_av_read ; assign WILL_FIRE_av_read = EN_av_read ; @@ -547,180 +823,304 @@ module mkDM_System_Bus(CLK, (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || !rg_sbcs_sbreadonaddr || - !master_xactor_crg_rd_addr_full$port2__read) && + !master_xactor_clearing && !master_xactor_shim_arff_rv[97]) && (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; + !master_xactor_clearing && !master_xactor_shim_awff_rv[97] && + !master_xactor_shim_wff_rv[73]) ; assign WILL_FIRE_write = EN_write ; - // value method master_m_awvalid - assign master_awvalid = master_xactor_crg_wr_addr_full ; - - // value method master_m_awid - assign master_awid = master_xactor_rg_wr_addr[96:93] ; - - // value method master_m_awaddr - assign master_awaddr = master_xactor_rg_wr_addr[92:29] ; - - // value method master_m_awlen - assign master_awlen = master_xactor_rg_wr_addr[28:21] ; - - // value method master_m_awsize - assign master_awsize = master_xactor_rg_wr_addr[20:18] ; - - // value method master_m_awburst - assign master_awburst = master_xactor_rg_wr_addr[17:16] ; + // value method master_aw_awid + assign master_awid = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[96:93] ; - // value method master_m_awlock - assign master_awlock = master_xactor_rg_wr_addr[15] ; + // value method master_aw_awaddr + assign master_awaddr = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[92:29] ; - // value method master_m_awcache - assign master_awcache = master_xactor_rg_wr_addr[14:11] ; + // value method master_aw_awlen + assign master_awlen = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[28:21] ; - // value method master_m_awprot - assign master_awprot = master_xactor_rg_wr_addr[10:8] ; + // value method master_aw_awsize + assign master_awsize = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[20:18] ; - // value method master_m_awqos - assign master_awqos = master_xactor_rg_wr_addr[7:4] ; + // value method master_aw_awburst + assign master_awburst = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[17:16] ; - // value method master_m_awregion - assign master_awregion = master_xactor_rg_wr_addr[3:0] ; + // value method master_aw_awlock + assign master_awlock = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[15] ; - // action method master_m_awready - assign CAN_FIRE_master_m_awready = 1'd1 ; - assign WILL_FIRE_master_m_awready = 1'd1 ; + // value method master_aw_awcache + assign master_awcache = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[14:11] ; - // value method master_m_wvalid - assign master_wvalid = master_xactor_crg_wr_data_full ; + // value method master_aw_awprot + assign master_awprot = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[10:8] ; - // value method master_m_wdata - assign master_wdata = master_xactor_rg_wr_data[72:9] ; + // value method master_aw_awqos + assign master_awqos = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[7:4] ; - // value method master_m_wstrb - assign master_wstrb = master_xactor_rg_wr_data[8:1] ; + // value method master_aw_awregion + assign master_awregion = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[3:0] ; - // value method master_m_wlast - assign master_wlast = master_xactor_rg_wr_data[0] ; + // value method master_aw_awvalid + assign master_awvalid = CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; - // action method master_m_wready - assign CAN_FIRE_master_m_wready = 1'd1 ; - assign WILL_FIRE_master_m_wready = 1'd1 ; - - // action method master_m_bvalid - assign CAN_FIRE_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_master_m_bvalid = 1'd1 ; - - // value method master_m_bready - assign master_bready = 1'b1 ; - - // value method master_m_arvalid - assign master_arvalid = master_xactor_crg_rd_addr_full ; - - // value method master_m_arid - assign master_arid = master_xactor_rg_rd_addr[96:93] ; - - // value method master_m_araddr - assign master_araddr = master_xactor_rg_rd_addr[92:29] ; - - // value method master_m_arlen - assign master_arlen = master_xactor_rg_rd_addr[28:21] ; - - // value method master_m_arsize - assign master_arsize = master_xactor_rg_rd_addr[20:18] ; - - // value method master_m_arburst - assign master_arburst = master_xactor_rg_rd_addr[17:16] ; - - // value method master_m_arlock - assign master_arlock = master_xactor_rg_rd_addr[15] ; - - // value method master_m_arcache - assign master_arcache = master_xactor_rg_rd_addr[14:11] ; - - // value method master_m_arprot - assign master_arprot = master_xactor_rg_rd_addr[10:8] ; - - // value method master_m_arqos - assign master_arqos = master_xactor_rg_rd_addr[7:4] ; - - // value method master_m_arregion - assign master_arregion = master_xactor_rg_rd_addr[3:0] ; - - // action method master_m_arready - assign CAN_FIRE_master_m_arready = 1'd1 ; - assign WILL_FIRE_master_m_arready = 1'd1 ; - - // action method master_m_rvalid - assign CAN_FIRE_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_master_m_rvalid = 1'd1 ; - - // value method master_m_rready - assign master_rready = !master_xactor_crg_rd_data_full$port2__read ; + // action method master_aw_awready + assign CAN_FIRE_master_aw_awready = 1'd1 ; + assign WILL_FIRE_master_aw_awready = 1'd1 ; + + // value method master_w_wdata + assign master_wdata = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q4[72:9] ; + + // value method master_w_wstrb + assign master_wstrb = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q4[8:1] ; + + // value method master_w_wlast + assign master_wlast = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q4[0] ; + + // value method master_w_wvalid + assign master_wvalid = CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + + // action method master_w_wready + assign CAN_FIRE_master_w_wready = 1'd1 ; + assign WILL_FIRE_master_w_wready = 1'd1 ; + + // action method master_b_bflit + assign CAN_FIRE_master_b_bflit = 1'd1 ; + assign WILL_FIRE_master_b_bflit = master_bvalid ; + + // value method master_b_bready + assign master_bready = !master_xactor_shim_bff_rv[6] ; + + // value method master_ar_arid + assign master_arid = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[96:93] ; + + // value method master_ar_araddr + assign master_araddr = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[92:29] ; + + // value method master_ar_arlen + assign master_arlen = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[28:21] ; + + // value method master_ar_arsize + assign master_arsize = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[20:18] ; + + // value method master_ar_arburst + assign master_arburst = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[17:16] ; + + // value method master_ar_arlock + assign master_arlock = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[15] ; + + // value method master_ar_arcache + assign master_arcache = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[14:11] ; + + // value method master_ar_arprot + assign master_arprot = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[10:8] ; + + // value method master_ar_arqos + assign master_arqos = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[7:4] ; + + // value method master_ar_arregion + assign master_arregion = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[3:0] ; + + // value method master_ar_arvalid + assign master_arvalid = CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + + // action method master_ar_arready + assign CAN_FIRE_master_ar_arready = 1'd1 ; + assign WILL_FIRE_master_ar_arready = 1'd1 ; + + // action method master_r_rflit + assign CAN_FIRE_master_r_rflit = 1'd1 ; + assign WILL_FIRE_master_r_rflit = master_rvalid ; + + // value method master_r_rready + assign master_rready = !master_xactor_shim_rff_rv[71] ; + + // rule RL_master_xactor_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = + master_xactor_ug_master_u_b_putWire$whas && + master_xactor_shim_bff_rv[6] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut ; + + // rule RL_master_xactor_ug_master_u_b_doPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut = + !master_xactor_shim_bff_rv[6] && + master_xactor_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut = + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ; + + // rule RL_master_xactor_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = + master_xactor_ug_master_u_r_putWire$whas && + master_xactor_shim_rff_rv[71] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut ; + + // rule RL_master_xactor_ug_master_u_r_doPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut = + !master_xactor_shim_rff_rv[71] && + master_xactor_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut = + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ; // rule RL_rl_sb_read_finish assign CAN_FIRE_RL_rl_sb_read_finish = - master_xactor_crg_rd_data_full && rg_sb_state == 2'd1 && + !master_xactor_clearing && + master_xactor_shim_rff_rv$port1__read[71] && + rg_sb_state == 2'd1 && rg_sbcs_sberror == 3'd0 ; assign WILL_FIRE_RL_rl_sb_read_finish = CAN_FIRE_RL_rl_sb_read_finish ; // rule RL_rl_sb_write_response - assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ; - assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ; + assign CAN_FIRE_RL_rl_sb_write_response = + !master_xactor_clearing && + master_xactor_shim_bff_rv$port1__read[6] ; + assign WILL_FIRE_RL_rl_sb_write_response = + CAN_FIRE_RL_rl_sb_write_response ; + + // rule RL_master_xactor_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; + + // rule RL_master_xactor_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = + master_xactor_ug_master_u_aw_dropWire$whas && + !master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + master_xactor_shim_awff_rv$port1__read[97] && + master_xactor_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ; + + // rule RL_master_xactor_ug_master_u_w_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + + // rule RL_master_xactor_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = + master_xactor_ug_master_u_w_dropWire$whas && + !master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_w_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + master_xactor_shim_wff_rv$port1__read[73] && + master_xactor_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ; + + // rule RL_master_xactor_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + + // rule RL_master_xactor_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = + master_xactor_ug_master_u_ar_dropWire$whas && + !master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + master_xactor_shim_arff_rv$port1__read[97] && + master_xactor_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ; + + // rule RL_master_xactor_do_clear + assign CAN_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; + assign WILL_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; // inputs to muxes for submodule ports - assign MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 = + assign MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160 ; assign MUX_rg_sbaddress0$write_1__SEL_2 = EN_write && write_dm_addr != 7'h38 && (rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && write_dm_addr == 7'h39 || write_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146) ; assign MUX_rg_sbaddress0$write_1__SEL_3 = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146 ; assign MUX_rg_sbaddress1$write_1__SEL_2 = EN_write && write_dm_addr != 7'h38 && ((write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) && rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && - rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 || + rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d344 || write_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146) ; assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ; + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d318 ; assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_3 = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_1 = - master_xactor_crg_wr_resp_full && - master_xactor_rg_wr_resp[1:0] != 2'b0 ; + WILL_FIRE_RL_rl_sb_write_response && + master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_3 = WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 ; + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_4 = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ; + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d326 ; assign MUX_rg_sbdata0$write_1__SEL_3 = EN_write && - write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d323 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, sbaddress__h1228, 8'd0, x__h3263, 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, addr64__h4310, 8'd0, x__h3263, 18'd65536 } ; + write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376 ; + assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1 = + { 5'd16, + sbaddress__h3099, + 8'd0, + axi4_size_val__h5371, + 18'd65536 } ; + assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2 = + { 5'd16, addr64__h6393, 8'd0, axi4_size_val__h5371, 18'd65536 } ; always@(write_dm_addr or - sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3 or - IF_rg_sbcs_sbreadonaddr_23_THEN_IF_rg_sbcs_sba_ETC___d307) + sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6 or + IF_rg_sbcs_sbreadonaddr_74_THEN_IF_rg_sbcs_sba_ETC___d360) begin case (write_dm_addr) 7'h39, 7'h3A: MUX_rg_sbaddress0$write_1__VAL_2 = - IF_rg_sbcs_sbreadonaddr_23_THEN_IF_rg_sbcs_sba_ETC___d307; + IF_rg_sbcs_sbreadonaddr_74_THEN_IF_rg_sbcs_sba_ETC___d360; default: MUX_rg_sbaddress0$write_1__VAL_2 = - sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3[31:0]; + sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6[31:0]; endcase end always@(write_dm_word) @@ -732,107 +1132,153 @@ module mkDM_System_Bus(CLK, end // inlined wires - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full && master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$port3__read = - MUX_rg_sbdata0$write_1__SEL_3 || - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full && master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$port3__read = - MUX_rg_sbdata0$write_1__SEL_3 || - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full && master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 || - EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313 ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$port2__read = - !CAN_FIRE_RL_rl_sb_read_finish && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - master_rvalid && !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = master_bvalid ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - assign master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 : - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ; - assign master_xactor_rg_rd_addr$EN = + assign master_xactor_ug_master_u_b_putWire$wget = + { master_bid, master_bresp } ; + assign master_xactor_ug_master_u_b_putWire$whas = + master_bvalid && !master_xactor_shim_bff_rv[6] ; + assign master_xactor_ug_master_u_r_putWire$wget = + { master_rid, master_rdata, master_rresp, master_rlast } ; + assign master_xactor_ug_master_u_r_putWire$whas = + master_rvalid && !master_xactor_shim_rff_rv[71] ; + assign master_xactor_ug_master_u_aw_dropWire$whas = + master_xactor_shim_awff_rv$port1__read[97] && master_awready ; + assign master_xactor_ug_master_u_w_dropWire$whas = + master_xactor_shim_wff_rv$port1__read[73] && master_wready ; + assign master_xactor_ug_master_u_ar_dropWire$whas = + master_xactor_shim_arff_rv$port1__read[97] && master_arready ; + assign master_xactor_shim_awff_rv$EN_port0__write = + EN_write && + write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376 ; + assign master_xactor_shim_awff_rv$port0__write_1 = + { 5'd16, + sbaddress__h3099, + 8'd0, + _theResult___snd_snd_val__h7102, + 18'd65536 } ; + assign master_xactor_shim_awff_rv$port1__read = + master_xactor_shim_awff_rv$EN_port0__write ? + master_xactor_shim_awff_rv$port0__write_1 : + master_xactor_shim_awff_rv ; + assign master_xactor_shim_awff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_awff_rv$port1__read ; + assign master_xactor_shim_awff_rv$port3__read = + master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_awff_rv$port2__read ; + assign master_xactor_shim_wff_rv$EN_port0__write = + EN_write && + write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376 ; + assign master_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, wrd_wdata__h7216, wrd_wstrb__h7217, 1'd1 } ; + assign master_xactor_shim_wff_rv$port1__read = + master_xactor_shim_wff_rv$EN_port0__write ? + master_xactor_shim_wff_rv$port0__write_1 : + master_xactor_shim_wff_rv ; + assign master_xactor_shim_wff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + master_xactor_shim_wff_rv$port1__read ; + assign master_xactor_shim_wff_rv$port3__read = + master_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + master_xactor_shim_wff_rv$port2__read ; + assign master_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, master_xactor_ug_master_u_b_putWire$wget } ; + assign master_xactor_shim_bff_rv$port1__read = + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ? + master_xactor_shim_bff_rv$port0__write_1 : + master_xactor_shim_bff_rv ; + assign master_xactor_shim_bff_rv$EN_port1__write = + !master_xactor_clearing && + master_xactor_shim_bff_rv$port1__read[6] ; + assign master_xactor_shim_bff_rv$port2__read = + master_xactor_shim_bff_rv$EN_port1__write ? + 7'd42 : + master_xactor_shim_bff_rv$port1__read ; + assign master_xactor_shim_bff_rv$port3__read = + master_xactor_clearing ? + 7'd42 : + master_xactor_shim_bff_rv$port2__read ; + assign master_xactor_shim_arff_rv$EN_port0__write = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313 ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { master_rid, master_rdata, master_rresp, master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - assign master_xactor_rg_wr_addr$D_IN = - { 4'd0, sbaddress__h1228, 8'd0, x__h4949, 18'd65536 } ; - assign master_xactor_rg_wr_addr$EN = MUX_rg_sbdata0$write_1__SEL_3 ; - - // register master_xactor_rg_wr_data - assign master_xactor_rg_wr_data$D_IN = - { wrd_wdata__h5077, wrd_wstrb__h5078, 1'd1 } ; - assign master_xactor_rg_wr_data$EN = MUX_rg_sbdata0$write_1__SEL_3 ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = { master_bid, master_bresp } ; - assign master_xactor_rg_wr_resp$EN = master_bvalid ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d366 ; + assign master_xactor_shim_arff_rv$port0__write_1 = + MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? + MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1 : + MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2 ; + assign master_xactor_shim_arff_rv$port1__read = + master_xactor_shim_arff_rv$EN_port0__write ? + master_xactor_shim_arff_rv$port0__write_1 : + master_xactor_shim_arff_rv ; + assign master_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_arff_rv$port1__read ; + assign master_xactor_shim_arff_rv$port3__read = + master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_arff_rv$port2__read ; + assign master_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, master_xactor_ug_master_u_r_putWire$wget } ; + assign master_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ? + master_xactor_shim_rff_rv$port0__write_1 : + master_xactor_shim_rff_rv ; + assign master_xactor_shim_rff_rv$EN_port1__write = + !master_xactor_clearing && + master_xactor_shim_rff_rv$port1__read[71] && + rg_sb_state == 2'd1 && + rg_sbcs_sberror == 3'd0 ; + assign master_xactor_shim_rff_rv$port2__read = + master_xactor_shim_rff_rv$EN_port1__write ? + 72'h2AAAAAAAAAAAAAAAAA : + master_xactor_shim_rff_rv$port1__read ; + assign master_xactor_shim_rff_rv$port3__read = + master_xactor_clearing ? + 72'h2AAAAAAAAAAAAAAAAA : + master_xactor_shim_rff_rv$port2__read ; + + // register master_xactor_clearing + assign master_xactor_clearing$D_IN = 1'd0 ; + assign master_xactor_clearing$EN = master_xactor_clearing ; + + // register master_xactor_shim_arff_rv + assign master_xactor_shim_arff_rv$D_IN = + master_xactor_shim_arff_rv$port3__read ; + assign master_xactor_shim_arff_rv$EN = 1'b1 ; + + // register master_xactor_shim_awff_rv + assign master_xactor_shim_awff_rv$D_IN = + master_xactor_shim_awff_rv$port3__read ; + assign master_xactor_shim_awff_rv$EN = 1'b1 ; + + // register master_xactor_shim_bff_rv + assign master_xactor_shim_bff_rv$D_IN = + master_xactor_shim_bff_rv$port3__read ; + assign master_xactor_shim_bff_rv$EN = 1'b1 ; + + // register master_xactor_shim_rff_rv + assign master_xactor_shim_rff_rv$D_IN = + master_xactor_shim_rff_rv$port3__read ; + assign master_xactor_shim_rff_rv$EN = 1'b1 ; + + // register master_xactor_shim_wff_rv + assign master_xactor_shim_wff_rv$D_IN = + master_xactor_shim_wff_rv$port3__read ; + assign master_xactor_shim_wff_rv$EN = 1'b1 ; // register rg_sb_state assign rg_sb_state$D_IN = (EN_reset || WILL_FIRE_RL_rl_sb_read_finish) ? 2'd0 : 2'd1 ; assign rg_sb_state$EN = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d366 || WILL_FIRE_RL_rl_sb_read_finish || EN_reset ; @@ -841,19 +1287,19 @@ module mkDM_System_Bus(CLK, MUX_rg_sbaddress0$write_1__SEL_2 or MUX_rg_sbaddress0$write_1__VAL_2 or MUX_rg_sbaddress0$write_1__SEL_3 or - sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3) + sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6) case (1'b1) EN_reset: rg_sbaddress0$D_IN = 32'd0; MUX_rg_sbaddress0$write_1__SEL_2: rg_sbaddress0$D_IN = MUX_rg_sbaddress0$write_1__VAL_2; MUX_rg_sbaddress0$write_1__SEL_3: rg_sbaddress0$D_IN = - sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3[31:0]; + sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6[31:0]; default: rg_sbaddress0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase assign rg_sbaddress0$EN = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146 || MUX_rg_sbaddress0$write_1__SEL_2 || EN_reset ; @@ -861,33 +1307,33 @@ module mkDM_System_Bus(CLK, assign rg_sbaddress1$D_IN = 32'd0 ; assign rg_sbaddress1$EN = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146 || MUX_rg_sbaddress1$write_1__SEL_2 || EN_reset ; // register rg_sbaddress_reading assign rg_sbaddress_reading$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - sbaddress__h1228 : - addr64__h4310 ; + MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? + sbaddress__h3099 : + addr64__h6393 ; assign rg_sbaddress_reading$EN = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313 ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d366 ; // register rg_sbcs_sbaccess assign rg_sbcs_sbaccess$D_IN = EN_reset ? 3'd2 : write_dm_word[19:17] ; assign rg_sbcs_sbaccess$EN = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 || EN_reset ; // register rg_sbcs_sbautoincrement assign rg_sbcs_sbautoincrement$D_IN = !EN_reset && write_dm_word[16] ; assign rg_sbcs_sbautoincrement$EN = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 || EN_reset ; // register rg_sbcs_sbbusyerror @@ -904,7 +1350,7 @@ module mkDM_System_Bus(CLK, assign rg_sbcs_sbbusyerror$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 || EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d318 || EN_reset ; // register rg_sbcs_sberror @@ -923,97 +1369,117 @@ module mkDM_System_Bus(CLK, endcase assign rg_sbcs_sberror$EN = WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 || - master_xactor_crg_wr_resp_full && - master_xactor_rg_wr_resp[1:0] != 2'b0 || + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_rl_sb_write_response && + master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0 || EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d326 || EN_reset ; // register rg_sbcs_sbreadonaddr assign rg_sbcs_sbreadonaddr$D_IN = !EN_reset && write_dm_word[20] ; assign rg_sbcs_sbreadonaddr$EN = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 || EN_reset ; // register rg_sbcs_sbreadondata assign rg_sbcs_sbreadondata$D_IN = !EN_reset && write_dm_word[15] ; assign rg_sbcs_sbreadondata$EN = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 || EN_reset ; // register rg_sbdata0 always@(EN_reset or WILL_FIRE_RL_rl_sb_read_finish or - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 or + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 or MUX_rg_sbdata0$write_1__SEL_3 or write_dm_word) case (1'b1) EN_reset: rg_sbdata0$D_IN = 32'd0; WILL_FIRE_RL_rl_sb_read_finish: rg_sbdata0$D_IN = - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79[31:0]; + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129[31:0]; MUX_rg_sbdata0$write_1__SEL_3: rg_sbdata0$D_IN = write_dm_word; default: rg_sbdata0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase assign rg_sbdata0$EN = EN_write && - write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d323 || + write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376 || WILL_FIRE_RL_rl_sb_read_finish || EN_reset ; // remaining internal signals - assign IF_rg_sbcs_sbreadonaddr_23_THEN_IF_rg_sbcs_sba_ETC___d307 = + assign IF_rg_sbcs_sbreadonaddr_74_THEN_IF_rg_sbcs_sba_ETC___d360 = rg_sbcs_sbreadonaddr ? (rg_sbcs_sbautoincrement ? - addr64310_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2[31:0] : + addr64393_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2[31:0] : write_dm_word) : write_dm_word ; - assign _theResult___fst__h4987 = word64__h4931 << shift_bits__h4934 ; - assign addr64310_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2 = - addr64__h4310 + - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ; - assign addr64__h4310 = { rg_sbaddress1, write_dm_word } ; - assign result__h1836 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h1866 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h1893 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h1920 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h1947 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h1974 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h2001 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h2028 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h2073 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h2100 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h2127 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h2154 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h2195 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h2222 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; - assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 = + assign _theResult___fst__h7087 = word64__h7032 << shift_bits__h7035 ; + assign addr64393_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2 = + addr64__h6393 + + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 ; + assign addr64__h6393 = { rg_sbaddress1, write_dm_word } ; + assign master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5 = + master_xactor_shim_arff_rv$port1__read[96:0] ; + assign master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3 = + master_xactor_shim_awff_rv$port1__read[96:0] ; + assign master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q4 = + master_xactor_shim_wff_rv$port1__read[72:0] ; + assign result__h3808 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[10:3] } ; + assign result__h3838 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[18:11] } ; + assign result__h3865 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[26:19] } ; + assign result__h3892 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[34:27] } ; + assign result__h3919 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[42:35] } ; + assign result__h3946 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[50:43] } ; + assign result__h3973 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[58:51] } ; + assign result__h4000 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[66:59] } ; + assign result__h4045 = + { 48'd0, master_xactor_shim_rff_rv$port1__read[18:3] } ; + assign result__h4072 = + { 48'd0, master_xactor_shim_rff_rv$port1__read[34:19] } ; + assign result__h4099 = + { 48'd0, master_xactor_shim_rff_rv$port1__read[50:35] } ; + assign result__h4126 = + { 48'd0, master_xactor_shim_rff_rv$port1__read[66:51] } ; + assign result__h4167 = + { 32'd0, master_xactor_shim_rff_rv$port1__read[34:3] } ; + assign result__h4194 = + { 32'd0, master_xactor_shim_rff_rv$port1__read[66:35] } ; + assign rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && - rg_sbcs_sbreadondata ; - assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313 = + rg_sbcs_sbautoincrement ; + assign rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && - rg_sbcs_sbreadonaddr ; - assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 = + rg_sbcs_sbreadondata ; + assign rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d366 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && - rg_sbcs_sbautoincrement ; - assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 = + rg_sbcs_sbreadonaddr ; + assign rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d344 = rg_sbcs_sberror == 3'd0 && (rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement || write_dm_addr != 7'h39) ; - assign sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3 = - sbaddress__h1228 + - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ; - assign sbaddress__h1228 = { rg_sbaddress1, rg_sbaddress0 } ; - assign shift_bits__h4934 = { rg_sbaddress0[2:0], 3'b0 } ; - assign strobe64__h4986 = 8'b00000001 << rg_sbaddress0[2:0] ; - assign strobe64__h4989 = 8'b00000011 << rg_sbaddress0[2:0] ; - assign strobe64__h4992 = 8'b00001111 << rg_sbaddress0[2:0] ; - assign v__h2727 = + assign sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6 = + sbaddress__h3099 + + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 ; + assign sbaddress__h3099 = { rg_sbaddress1, rg_sbaddress0 } ; + assign shift_bits__h7035 = { rg_sbaddress0[2:0], 3'b0 } ; + assign strobe64__h7085 = 8'b00000001 << rg_sbaddress0[2:0] ; + assign strobe64__h7089 = 8'b00000011 << rg_sbaddress0[2:0] ; + assign strobe64__h7093 = 8'b00001111 << rg_sbaddress0[2:0] ; + assign v__h4783 = { 9'd64, rg_sbcs_sbbusyerror, rg_sb_state != 2'd0, @@ -1023,172 +1489,173 @@ module mkDM_System_Bus(CLK, rg_sbcs_sbreadondata, rg_sbcs_sberror, 12'd1031 } ; - assign v__h2861 = + assign v__h4917 = (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0) ? 32'd0 : rg_sbdata0 ; - assign word64__h4931 = { 32'd0, write_dm_word } ; - assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 = + assign word64__h7032 = { 32'd0, write_dm_word } ; + assign write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) && write_dm_word[19:17] != 3'd4 && write_dm_word[19:17] != 3'd3 ; - assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 = - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || + assign write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d318 = + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 || (write_dm_addr == 7'h39 || write_dm_addr == 7'h3A || write_dm_addr == 7'h3C) && rg_sb_state != 2'd0 ; - assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271 = + assign write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d324 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && rg_sbcs_sbbusyerror && !write_dm_word[22] ; - assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 = + assign write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d326 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) ; - assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278 = + assign write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d331 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) && (write_dm_word[19:17] == 3'd4 || write_dm_word[19:17] == 3'd3) ; - assign write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d323 = + assign write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376 = write_dm_addr == 7'h3C && rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 ; always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: x__h3263 = rg_sbcs_sbaccess; - default: x__h3263 = 3'b011; + 3'd0, 3'd1, 3'd2: axi4_size_val__h5371 = rg_sbcs_sbaccess; + default: axi4_size_val__h5371 = 3'b011; endcase end always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2, 3'd3: x__h4949 = rg_sbcs_sbaccess; - default: x__h4949 = 3'b111; + 3'd0, 3'd1, 3'd2, 3'd3: + _theResult___snd_snd_val__h7102 = rg_sbcs_sbaccess; + default: _theResult___snd_snd_val__h7102 = 3'b111; endcase end always@(rg_sbcs_sbaccess or - strobe64__h4986 or strobe64__h4989 or strobe64__h4992) + strobe64__h7085 or strobe64__h7089 or strobe64__h7093) begin case (rg_sbcs_sbaccess) - 3'd0: wrd_wstrb__h5078 = strobe64__h4986; - 3'd1: wrd_wstrb__h5078 = strobe64__h4989; - 3'd2: wrd_wstrb__h5078 = strobe64__h4992; - 3'd3: wrd_wstrb__h5078 = 8'b11111111; - default: wrd_wstrb__h5078 = 8'd0; + 3'd0: wrd_wstrb__h7217 = strobe64__h7085; + 3'd1: wrd_wstrb__h7217 = strobe64__h7089; + 3'd2: wrd_wstrb__h7217 = strobe64__h7093; + 3'd3: wrd_wstrb__h7217 = 8'b11111111; + default: wrd_wstrb__h7217 = 8'd0; endcase end - always@(rg_sbcs_sbaccess or word64__h4931 or _theResult___fst__h4987) + always@(rg_sbcs_sbaccess or word64__h7032 or _theResult___fst__h7087) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: wrd_wdata__h5077 = _theResult___fst__h4987; - default: wrd_wdata__h5077 = word64__h4931; + 3'd0, 3'd1, 3'd2: wrd_wdata__h7216 = _theResult___fst__h7087; + default: wrd_wdata__h7216 = word64__h7032; endcase end always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd1; - 3'd1: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd2; - 3'd2: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd4; - 3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd8; - default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = + 3'd0: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 = 64'd1; + 3'd1: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 = 64'd2; + 3'd2: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 = 64'd4; + 3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 = 64'd8; + default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 = 64'd16; endcase end always@(rg_sbaddress_reading or - result__h1836 or - result__h1866 or - result__h1893 or - result__h1920 or - result__h1947 or result__h1974 or result__h2001 or result__h2028) + result__h3808 or + result__h3838 or + result__h3865 or + result__h3892 or + result__h3919 or result__h3946 or result__h3973 or result__h4000) begin case (rg_sbaddress_reading[2:0]) 3'h0: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1836; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3808; 3'h1: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1866; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3838; 3'h2: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1893; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3865; 3'h3: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1920; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3892; 3'h4: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1947; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3919; 3'h5: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1974; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3946; 3'h6: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h2001; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3973; 3'h7: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h2028; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h4000; endcase end always@(rg_sbaddress_reading or - result__h2073 or result__h2100 or result__h2127 or result__h2154) + result__h4045 or result__h4072 or result__h4099 or result__h4126) begin case (rg_sbaddress_reading[2:0]) 3'h0: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2073; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 = + result__h4045; 3'h2: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2100; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 = + result__h4072; 3'h4: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2127; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 = + result__h4099; 3'h6: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2154; - default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 = + result__h4126; + default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 = 64'd0; endcase end - always@(rg_sbaddress_reading or result__h2195 or result__h2222) + always@(rg_sbaddress_reading or result__h4167 or result__h4194) begin case (rg_sbaddress_reading[2:0]) 3'h0: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = - result__h2195; + result__h4167; 3'h4: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = - result__h2222; + result__h4194; default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = 64'd0; endcase end always@(rg_sbcs_sbaccess or - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 or - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 or + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 or + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 or CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 or - rg_sbaddress_reading or master_xactor_rg_rd_data) + rg_sbaddress_reading or master_xactor_shim_rff_rv$port1__read) begin case (rg_sbcs_sbaccess) 3'd0: - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53; + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 = + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103; 3'd1: - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66; + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 = + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116; 3'd2: - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 = CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1; 3'd3: - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 = (rg_sbaddress_reading[2:0] == 3'h0) ? - master_xactor_rg_rd_data[66:3] : + master_xactor_shim_rff_rv$port1__read[66:3] : 64'd0; - default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = + default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 = 64'd0; endcase end @@ -1199,51 +1666,44 @@ module mkDM_System_Bus(CLK, begin if (RST_N == `BSV_RESET_VALUE) begin - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; + master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 7'd42; + master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 72'h2AAAAAAAAAAAAAAAAA; + master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0; rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY 32'd0; end else begin - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; + if (master_xactor_clearing$EN) + master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + master_xactor_clearing$D_IN; + if (master_xactor_shim_arff_rv$EN) + master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_arff_rv$D_IN; + if (master_xactor_shim_awff_rv$EN) + master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_awff_rv$D_IN; + if (master_xactor_shim_bff_rv$EN) + master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_bff_rv$D_IN; + if (master_xactor_shim_rff_rv$EN) + master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_rff_rv$D_IN; + if (master_xactor_shim_wff_rv$EN) + master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_wff_rv$D_IN; if (rg_sbaddress0$EN) rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress0$D_IN; if (rg_sbaddress1$EN) rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress1$D_IN; end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; if (rg_sb_state$EN) rg_sb_state <= `BSV_ASSIGNMENT_DELAY rg_sb_state$D_IN; if (rg_sbaddress_reading$EN) rg_sbaddress_reading <= `BSV_ASSIGNMENT_DELAY rg_sbaddress_reading$D_IN; @@ -1268,16 +1728,12 @@ module mkDM_System_Bus(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; + master_xactor_clearing = 1'h0; + master_xactor_shim_arff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_awff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_bff_rv = 7'h2A; + master_xactor_shim_rff_rv = 72'hAAAAAAAAAAAAAAAAAA; + master_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; rg_sb_state = 2'h2; rg_sbaddress0 = 32'hAAAAAAAA; rg_sbaddress1 = 32'hAAAAAAAA; @@ -1428,6 +1884,12 @@ module mkDM_System_Bus(CLK, av_read_dm_addr != 7'h3A && av_read_dm_addr != 7'h3C) $write("] not supported", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 && write_dm_word[14:12] == 3'd0) @@ -1443,24 +1905,24 @@ module mkDM_System_Bus(CLK, $display(" Must be cleared to re-enable system bus access."); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d324) $display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d324) $display(" ERROR: existing sbbusyerror (%0d) is not being cleared.", rg_sbcs_sbbusyerror); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d324) $display(" Must be cleared to re-enable system bus access."); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d331) $display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d331) $write(" ERROR: sbaccess "); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h38 && @@ -1476,7 +1938,7 @@ module mkDM_System_Bus(CLK, $write("DM_SBACCESS_128_BIT"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d331) $write(" not supported", "\n"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr != 7'h38 && @@ -1617,62 +2079,81 @@ module mkDM_System_Bus(CLK, $write("] <= 0x%08h; addr not supported", write_dm_word, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $display("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write(" rdr = "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("AXI4_Rd_Data { ", "rid: "); + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) + $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[70:67]); + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) + $write("'h%h", master_xactor_shim_rff_rv$port1__read[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[66:3]); + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) + $write("'h%h", master_xactor_shim_rff_rv$port1__read[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[2:1]); + master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_sb_read_finish && + master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_sb_read_finish && + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 && - master_xactor_rg_rd_data[0]) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + master_xactor_shim_rff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !master_xactor_rg_rd_data[0]) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + !master_xactor_shim_rff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); end // synopsys translate_on endmodule // mkDM_System_Bus diff --git a/src_SSITH_P1/Verilog_RTL/mkDebug_Module.v b/src_SSITH_P1/Verilog_RTL/mkDebug_Module.v index 1688e82e..725db2d0 100644 --- a/src_SSITH_P1/Verilog_RTL/mkDebug_Module.v +++ b/src_SSITH_P1/Verilog_RTL/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:34 BST 2019 // // // Ports: @@ -27,33 +27,33 @@ // ndm_reset_client_request_get O 1 reg // RDY_ndm_reset_client_request_get O 1 reg // RDY_ndm_reset_client_response_put O 1 reg +// master_awid O 4 +// master_awaddr O 64 +// master_awlen O 8 +// master_awsize O 3 +// master_awburst O 2 +// master_awlock O 1 +// master_awcache O 4 +// master_awprot O 3 +// master_awqos O 4 +// master_awregion O 4 // master_awvalid O 1 -// master_awid O 4 reg -// master_awaddr O 64 reg -// master_awlen O 8 reg -// master_awsize O 3 reg -// master_awburst O 2 reg -// master_awlock O 1 reg -// master_awcache O 4 reg -// master_awprot O 3 reg -// master_awqos O 4 reg -// master_awregion O 4 reg +// master_wdata O 64 +// master_wstrb O 8 +// master_wlast O 1 // master_wvalid O 1 -// master_wdata O 64 reg -// master_wstrb O 8 reg -// master_wlast O 1 reg -// master_bready O 1 const +// master_bready O 1 +// master_arid O 4 +// master_araddr O 64 +// master_arlen O 8 +// master_arsize O 3 +// master_arburst O 2 +// master_arlock O 1 +// master_arcache O 4 +// master_arprot O 3 +// master_arqos O 4 +// master_arregion O 4 // master_arvalid O 1 -// master_arid O 4 reg -// master_araddr O 64 reg -// master_arlen O 8 reg -// master_arsize O 3 reg -// master_arburst O 2 reg -// master_arlock O 1 reg -// master_arcache O 4 reg -// master_arprot O 3 reg -// master_arqos O 4 reg -// master_arregion O 4 reg // master_rready O 1 // CLK I 1 clock // RST_N I 1 reset @@ -67,15 +67,13 @@ // ndm_reset_client_response_put I 1 reg // master_awready I 1 // master_wready I 1 -// master_bvalid I 1 -// master_bid I 4 reg -// master_bresp I 2 reg +// master_bid I 4 +// master_bresp I 2 // master_arready I 1 -// master_rvalid I 1 -// master_rid I 4 reg -// master_rdata I 64 reg -// master_rresp I 2 reg -// master_rlast I 1 reg +// master_rid I 4 +// master_rdata I 64 +// master_rresp I 2 +// master_rlast I 1 // EN_dmi_read_addr I 1 // EN_dmi_write I 1 // EN_hart0_reset_client_response_put I 1 @@ -83,6 +81,8 @@ // EN_hart0_gpr_mem_client_response_put I 1 // EN_hart0_csr_mem_client_response_put I 1 // EN_ndm_reset_client_response_put I 1 +// master_bvalid I 1 +// master_rvalid I 1 // EN_dmi_read_data I 1 // EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 @@ -92,14 +92,264 @@ // EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: +// (dmi_read_addr_dm_addr, EN_dmi_read_addr) -> RDY_dmi_read_data // (dmi_read_addr_dm_addr, -// master_arready, -// EN_dmi_read_addr) -> RDY_dmi_read_data +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arid // (dmi_read_addr_dm_addr, -// master_arready, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, // EN_dmi_read_addr, -// EN_dmi_read_data) -> dmi_read_data -// (master_awready, master_wready, master_arready) -> RDY_dmi_write +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_araddr +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arlen +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arsize +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arburst +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arlock +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arcache +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arprot +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arqos +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arregion +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_aruser +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arvalid +// (dmi_read_addr_dm_addr, EN_dmi_read_addr, EN_dmi_read_data) -> dmi_read_data +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awid +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awaddr +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awlen +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awsize +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awburst +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awlock +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awcache +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awprot +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awqos +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awregion +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awuser +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awvalid +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_wdata +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_wstrb +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_wlast +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_wuser +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_wvalid // // @@ -176,8 +426,6 @@ module mkDebug_Module(CLK, EN_ndm_reset_client_response_put, RDY_ndm_reset_client_response_put, - master_awvalid, - master_awid, master_awaddr, @@ -198,9 +446,9 @@ module mkDebug_Module(CLK, master_awregion, - master_awready, + master_awvalid, - master_wvalid, + master_awready, master_wdata, @@ -208,16 +456,16 @@ module mkDebug_Module(CLK, master_wlast, + master_wvalid, + master_wready, - master_bvalid, master_bid, master_bresp, + master_bvalid, master_bready, - master_arvalid, - master_arid, master_araddr, @@ -238,13 +486,15 @@ module mkDebug_Module(CLK, master_arregion, + master_arvalid, + master_arready, - master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, + master_rvalid, master_rready); input CLK; @@ -321,115 +571,115 @@ module mkDebug_Module(CLK, input EN_ndm_reset_client_response_put; output RDY_ndm_reset_client_response_put; - // value method master_m_awvalid - output master_awvalid; - - // value method master_m_awid + // value method master_aw_awid output [3 : 0] master_awid; - // value method master_m_awaddr + // value method master_aw_awaddr output [63 : 0] master_awaddr; - // value method master_m_awlen + // value method master_aw_awlen output [7 : 0] master_awlen; - // value method master_m_awsize + // value method master_aw_awsize output [2 : 0] master_awsize; - // value method master_m_awburst + // value method master_aw_awburst output [1 : 0] master_awburst; - // value method master_m_awlock + // value method master_aw_awlock output master_awlock; - // value method master_m_awcache + // value method master_aw_awcache output [3 : 0] master_awcache; - // value method master_m_awprot + // value method master_aw_awprot output [2 : 0] master_awprot; - // value method master_m_awqos + // value method master_aw_awqos output [3 : 0] master_awqos; - // value method master_m_awregion + // value method master_aw_awregion output [3 : 0] master_awregion; - // value method master_m_awuser + // value method master_aw_awuser - // action method master_m_awready - input master_awready; + // value method master_aw_awvalid + output master_awvalid; - // value method master_m_wvalid - output master_wvalid; + // action method master_aw_awready + input master_awready; - // value method master_m_wdata + // value method master_w_wdata output [63 : 0] master_wdata; - // value method master_m_wstrb + // value method master_w_wstrb output [7 : 0] master_wstrb; - // value method master_m_wlast + // value method master_w_wlast output master_wlast; - // value method master_m_wuser + // value method master_w_wuser + + // value method master_w_wvalid + output master_wvalid; - // action method master_m_wready + // action method master_w_wready input master_wready; - // action method master_m_bvalid - input master_bvalid; + // action method master_b_bflit input [3 : 0] master_bid; input [1 : 0] master_bresp; + input master_bvalid; - // value method master_m_bready + // value method master_b_bready output master_bready; - // value method master_m_arvalid - output master_arvalid; - - // value method master_m_arid + // value method master_ar_arid output [3 : 0] master_arid; - // value method master_m_araddr + // value method master_ar_araddr output [63 : 0] master_araddr; - // value method master_m_arlen + // value method master_ar_arlen output [7 : 0] master_arlen; - // value method master_m_arsize + // value method master_ar_arsize output [2 : 0] master_arsize; - // value method master_m_arburst + // value method master_ar_arburst output [1 : 0] master_arburst; - // value method master_m_arlock + // value method master_ar_arlock output master_arlock; - // value method master_m_arcache + // value method master_ar_arcache output [3 : 0] master_arcache; - // value method master_m_arprot + // value method master_ar_arprot output [2 : 0] master_arprot; - // value method master_m_arqos + // value method master_ar_arqos output [3 : 0] master_arqos; - // value method master_m_arregion + // value method master_ar_arregion output [3 : 0] master_arregion; - // value method master_m_aruser + // value method master_ar_aruser - // action method master_m_arready + // value method master_ar_arvalid + output master_arvalid; + + // action method master_ar_arready input master_arready; - // action method master_m_rvalid - input master_rvalid; + // action method master_r_rflit input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; + input master_rvalid; - // value method master_m_rready + // value method master_r_rready output master_rready; // signals for module outputs @@ -598,11 +848,11 @@ module mkDebug_Module(CLK, CAN_FIRE_hart0_gpr_mem_client_response_put, CAN_FIRE_hart0_reset_client_request_get, CAN_FIRE_hart0_reset_client_response_put, - CAN_FIRE_master_m_arready, - CAN_FIRE_master_m_awready, - CAN_FIRE_master_m_bvalid, - CAN_FIRE_master_m_rvalid, - CAN_FIRE_master_m_wready, + CAN_FIRE_master_ar_arready, + CAN_FIRE_master_aw_awready, + CAN_FIRE_master_b_bflit, + CAN_FIRE_master_r_rflit, + CAN_FIRE_master_w_wready, CAN_FIRE_ndm_reset_client_request_get, CAN_FIRE_ndm_reset_client_response_put, WILL_FIRE_RL_rl_reset, @@ -618,18 +868,18 @@ module mkDebug_Module(CLK, WILL_FIRE_hart0_gpr_mem_client_response_put, WILL_FIRE_hart0_reset_client_request_get, WILL_FIRE_hart0_reset_client_response_put, - WILL_FIRE_master_m_arready, - WILL_FIRE_master_m_awready, - WILL_FIRE_master_m_bvalid, - WILL_FIRE_master_m_rvalid, - WILL_FIRE_master_m_wready, + WILL_FIRE_master_ar_arready, + WILL_FIRE_master_aw_awready, + WILL_FIRE_master_b_bflit, + WILL_FIRE_master_r_rflit, + WILL_FIRE_master_w_wready, WILL_FIRE_ndm_reset_client_request_get, WILL_FIRE_ndm_reset_client_response_put; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h894; - reg [31 : 0] v__h888; + reg [31 : 0] v__h878; + reg [31 : 0] v__h872; // synopsys translate_on // action method dmi_read_addr @@ -804,108 +1054,108 @@ module mkDebug_Module(CLK, assign WILL_FIRE_ndm_reset_client_response_put = EN_ndm_reset_client_response_put ; - // value method master_m_awvalid - assign master_awvalid = dm_system_bus$master_awvalid ; - - // value method master_m_awid + // value method master_aw_awid assign master_awid = dm_system_bus$master_awid ; - // value method master_m_awaddr + // value method master_aw_awaddr assign master_awaddr = dm_system_bus$master_awaddr ; - // value method master_m_awlen + // value method master_aw_awlen assign master_awlen = dm_system_bus$master_awlen ; - // value method master_m_awsize + // value method master_aw_awsize assign master_awsize = dm_system_bus$master_awsize ; - // value method master_m_awburst + // value method master_aw_awburst assign master_awburst = dm_system_bus$master_awburst ; - // value method master_m_awlock + // value method master_aw_awlock assign master_awlock = dm_system_bus$master_awlock ; - // value method master_m_awcache + // value method master_aw_awcache assign master_awcache = dm_system_bus$master_awcache ; - // value method master_m_awprot + // value method master_aw_awprot assign master_awprot = dm_system_bus$master_awprot ; - // value method master_m_awqos + // value method master_aw_awqos assign master_awqos = dm_system_bus$master_awqos ; - // value method master_m_awregion + // value method master_aw_awregion assign master_awregion = dm_system_bus$master_awregion ; - // action method master_m_awready - assign CAN_FIRE_master_m_awready = 1'd1 ; - assign WILL_FIRE_master_m_awready = 1'd1 ; + // value method master_aw_awvalid + assign master_awvalid = dm_system_bus$master_awvalid ; - // value method master_m_wvalid - assign master_wvalid = dm_system_bus$master_wvalid ; + // action method master_aw_awready + assign CAN_FIRE_master_aw_awready = 1'd1 ; + assign WILL_FIRE_master_aw_awready = 1'd1 ; - // value method master_m_wdata + // value method master_w_wdata assign master_wdata = dm_system_bus$master_wdata ; - // value method master_m_wstrb + // value method master_w_wstrb assign master_wstrb = dm_system_bus$master_wstrb ; - // value method master_m_wlast + // value method master_w_wlast assign master_wlast = dm_system_bus$master_wlast ; - // action method master_m_wready - assign CAN_FIRE_master_m_wready = 1'd1 ; - assign WILL_FIRE_master_m_wready = 1'd1 ; + // value method master_w_wvalid + assign master_wvalid = dm_system_bus$master_wvalid ; - // action method master_m_bvalid - assign CAN_FIRE_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_master_m_bvalid = 1'd1 ; + // action method master_w_wready + assign CAN_FIRE_master_w_wready = 1'd1 ; + assign WILL_FIRE_master_w_wready = 1'd1 ; - // value method master_m_bready - assign master_bready = dm_system_bus$master_bready ; + // action method master_b_bflit + assign CAN_FIRE_master_b_bflit = 1'd1 ; + assign WILL_FIRE_master_b_bflit = master_bvalid ; - // value method master_m_arvalid - assign master_arvalid = dm_system_bus$master_arvalid ; + // value method master_b_bready + assign master_bready = dm_system_bus$master_bready ; - // value method master_m_arid + // value method master_ar_arid assign master_arid = dm_system_bus$master_arid ; - // value method master_m_araddr + // value method master_ar_araddr assign master_araddr = dm_system_bus$master_araddr ; - // value method master_m_arlen + // value method master_ar_arlen assign master_arlen = dm_system_bus$master_arlen ; - // value method master_m_arsize + // value method master_ar_arsize assign master_arsize = dm_system_bus$master_arsize ; - // value method master_m_arburst + // value method master_ar_arburst assign master_arburst = dm_system_bus$master_arburst ; - // value method master_m_arlock + // value method master_ar_arlock assign master_arlock = dm_system_bus$master_arlock ; - // value method master_m_arcache + // value method master_ar_arcache assign master_arcache = dm_system_bus$master_arcache ; - // value method master_m_arprot + // value method master_ar_arprot assign master_arprot = dm_system_bus$master_arprot ; - // value method master_m_arqos + // value method master_ar_arqos assign master_arqos = dm_system_bus$master_arqos ; - // value method master_m_arregion + // value method master_ar_arregion assign master_arregion = dm_system_bus$master_arregion ; - // action method master_m_arready - assign CAN_FIRE_master_m_arready = 1'd1 ; - assign WILL_FIRE_master_m_arready = 1'd1 ; + // value method master_ar_arvalid + assign master_arvalid = dm_system_bus$master_arvalid ; + + // action method master_ar_arready + assign CAN_FIRE_master_ar_arready = 1'd1 ; + assign WILL_FIRE_master_ar_arready = 1'd1 ; - // action method master_m_rvalid - assign CAN_FIRE_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_master_m_rvalid = 1'd1 ; + // action method master_r_rflit + assign CAN_FIRE_master_r_rflit = 1'd1 ; + assign WILL_FIRE_master_r_rflit = master_rvalid ; - // value method master_m_rready + // value method master_r_rready assign master_rready = dm_system_bus$master_rready ; // submodule dm_abstract_commands @@ -979,23 +1229,22 @@ module mkDebug_Module(CLK, .master_awready(dm_system_bus$master_awready), .master_bid(dm_system_bus$master_bid), .master_bresp(dm_system_bus$master_bresp), - .master_bvalid(dm_system_bus$master_bvalid), .master_rdata(dm_system_bus$master_rdata), .master_rid(dm_system_bus$master_rid), .master_rlast(dm_system_bus$master_rlast), .master_rresp(dm_system_bus$master_rresp), - .master_rvalid(dm_system_bus$master_rvalid), .master_wready(dm_system_bus$master_wready), .write_dm_addr(dm_system_bus$write_dm_addr), .write_dm_word(dm_system_bus$write_dm_word), .EN_reset(dm_system_bus$EN_reset), .EN_av_read(dm_system_bus$EN_av_read), .EN_write(dm_system_bus$EN_write), + .master_bvalid(dm_system_bus$master_bvalid), + .master_rvalid(dm_system_bus$master_rvalid), .RDY_reset(), .av_read(dm_system_bus$av_read), .RDY_av_read(dm_system_bus$RDY_av_read), .RDY_write(dm_system_bus$RDY_write), - .master_awvalid(dm_system_bus$master_awvalid), .master_awid(dm_system_bus$master_awid), .master_awaddr(dm_system_bus$master_awaddr), .master_awlen(dm_system_bus$master_awlen), @@ -1006,12 +1255,12 @@ module mkDebug_Module(CLK, .master_awprot(dm_system_bus$master_awprot), .master_awqos(dm_system_bus$master_awqos), .master_awregion(dm_system_bus$master_awregion), - .master_wvalid(dm_system_bus$master_wvalid), + .master_awvalid(dm_system_bus$master_awvalid), .master_wdata(dm_system_bus$master_wdata), .master_wstrb(dm_system_bus$master_wstrb), .master_wlast(dm_system_bus$master_wlast), + .master_wvalid(dm_system_bus$master_wvalid), .master_bready(dm_system_bus$master_bready), - .master_arvalid(dm_system_bus$master_arvalid), .master_arid(dm_system_bus$master_arid), .master_araddr(dm_system_bus$master_araddr), .master_arlen(dm_system_bus$master_arlen), @@ -1022,6 +1271,7 @@ module mkDebug_Module(CLK, .master_arprot(dm_system_bus$master_arprot), .master_arqos(dm_system_bus$master_arqos), .master_arregion(dm_system_bus$master_arregion), + .master_arvalid(dm_system_bus$master_arvalid), .master_rready(dm_system_bus$master_rready)); // rule RL_rl_reset @@ -1150,12 +1400,10 @@ module mkDebug_Module(CLK, assign dm_system_bus$master_awready = master_awready ; assign dm_system_bus$master_bid = master_bid ; assign dm_system_bus$master_bresp = master_bresp ; - assign dm_system_bus$master_bvalid = master_bvalid ; assign dm_system_bus$master_rdata = master_rdata ; assign dm_system_bus$master_rid = master_rid ; assign dm_system_bus$master_rlast = master_rlast ; assign dm_system_bus$master_rresp = master_rresp ; - assign dm_system_bus$master_rvalid = master_rvalid ; assign dm_system_bus$master_wready = master_wready ; assign dm_system_bus$write_dm_addr = dmi_write_dm_addr ; assign dm_system_bus$write_dm_word = dmi_write_dm_word ; @@ -1179,6 +1427,8 @@ module mkDebug_Module(CLK, dmi_write_dm_addr == 7'h3D || dmi_write_dm_addr == 7'h3E || dmi_write_dm_addr == 7'h3F) ; + assign dm_system_bus$master_bvalid = master_bvalid ; + assign dm_system_bus$master_rvalid = master_rvalid ; // handling of inlined registers @@ -1214,12 +1464,12 @@ module mkDebug_Module(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset) begin - v__h894 = $stime; + v__h878 = $stime; #0; end - v__h888 = v__h894 / 32'd10; + v__h872 = v__h878 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h888); + if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h872); end // synopsys translate_on endmodule // mkDebug_Module diff --git a/src_SSITH_P1/Verilog_RTL/mkGPR_RegFile.v b/src_SSITH_P1/Verilog_RTL/mkGPR_RegFile.v index cb7b11b7..38844265 100644 --- a/src_SSITH_P1/Verilog_RTL/mkGPR_RegFile.v +++ b/src_SSITH_P1/Verilog_RTL/mkGPR_RegFile.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:16 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkIntMul_32.v b/src_SSITH_P1/Verilog_RTL/mkIntMul_32.v index f4d13fdd..9e92b6b6 100644 --- a/src_SSITH_P1/Verilog_RTL/mkIntMul_32.v +++ b/src_SSITH_P1/Verilog_RTL/mkIntMul_32.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:40 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkIntMul_64.v b/src_SSITH_P1/Verilog_RTL/mkIntMul_64.v index 0b513191..9a7bb9af 100644 --- a/src_SSITH_P1/Verilog_RTL/mkIntMul_64.v +++ b/src_SSITH_P1/Verilog_RTL/mkIntMul_64.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:40 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkJtagTap.v b/src_SSITH_P1/Verilog_RTL/mkJtagTap.v index b462cf5c..5e299150 100644 --- a/src_SSITH_P1/Verilog_RTL/mkJtagTap.v +++ b/src_SSITH_P1/Verilog_RTL/mkJtagTap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:21 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkMMU_DCache.v b/src_SSITH_P1/Verilog_RTL/mkMMU_DCache.v new file mode 100644 index 00000000..312c4441 --- /dev/null +++ b/src_SSITH_P1/Verilog_RTL/mkMMU_DCache.v @@ -0,0 +1,5542 @@ +// +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// +// On Tue Jul 9 16:18:45 BST 2019 +// +// +// Ports: +// Name I/O size props +// RDY_set_verbosity O 1 const +// RDY_server_reset_request_put O 1 reg +// RDY_server_reset_response_get O 1 +// valid O 1 +// addr O 32 reg +// word64 O 64 +// st_amo_val O 64 +// exc O 1 +// exc_code O 4 reg +// RDY_server_flush_request_put O 1 reg +// RDY_server_flush_response_get O 1 +// RDY_tlb_flush O 1 const +// mem_master_awid O 4 +// mem_master_awaddr O 64 +// mem_master_awlen O 8 +// mem_master_awsize O 3 +// mem_master_awburst O 2 +// mem_master_awlock O 1 +// mem_master_awcache O 4 +// mem_master_awprot O 3 +// mem_master_awqos O 4 +// mem_master_awregion O 4 +// mem_master_awvalid O 1 +// mem_master_wdata O 64 +// mem_master_wstrb O 8 +// mem_master_wlast O 1 +// mem_master_wvalid O 1 +// mem_master_bready O 1 +// mem_master_arid O 4 +// mem_master_araddr O 64 +// mem_master_arlen O 8 +// mem_master_arsize O 3 +// mem_master_arburst O 2 +// mem_master_arlock O 1 +// mem_master_arcache O 4 +// mem_master_arprot O 3 +// mem_master_arqos O 4 +// mem_master_arregion O 4 +// mem_master_arvalid O 1 +// mem_master_rready O 1 +// CLK I 1 clock +// RST_N I 1 reset +// set_verbosity_verbosity I 4 reg +// req_op I 2 +// req_f3 I 3 +// req_amo_funct7 I 7 reg +// req_addr I 32 +// req_st_value I 64 +// req_priv I 2 unused +// req_sstatus_SUM I 1 unused +// req_mstatus_MXR I 1 unused +// req_satp I 32 unused +// mem_master_awready I 1 +// mem_master_wready I 1 +// mem_master_bid I 4 +// mem_master_bresp I 2 +// mem_master_arready I 1 +// mem_master_rid I 4 +// mem_master_rdata I 64 +// mem_master_rresp I 2 +// mem_master_rlast I 1 +// EN_set_verbosity I 1 +// EN_server_reset_request_put I 1 +// EN_server_reset_response_get I 1 +// EN_req I 1 +// EN_server_flush_request_put I 1 +// EN_server_flush_response_get I 1 +// EN_tlb_flush I 1 unused +// mem_master_bvalid I 1 +// mem_master_rvalid I 1 +// +// Combinational paths from inputs to outputs: +// (mem_master_rid, +// mem_master_rdata, +// mem_master_rresp, +// mem_master_rlast, +// mem_master_rvalid) -> valid +// (mem_master_rid, +// mem_master_rdata, +// mem_master_rresp, +// mem_master_rlast, +// mem_master_rvalid) -> word64 +// EN_req -> mem_master_arid +// EN_req -> mem_master_araddr +// EN_req -> mem_master_arlen +// EN_req -> mem_master_arsize +// EN_req -> mem_master_arburst +// EN_req -> mem_master_arlock +// EN_req -> mem_master_arcache +// EN_req -> mem_master_arprot +// EN_req -> mem_master_arqos +// EN_req -> mem_master_arregion +// EN_req -> mem_master_aruser +// EN_req -> mem_master_arvalid +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkMMU_DCache(CLK, + RST_N, + + set_verbosity_verbosity, + EN_set_verbosity, + RDY_set_verbosity, + + EN_server_reset_request_put, + RDY_server_reset_request_put, + + EN_server_reset_response_get, + RDY_server_reset_response_get, + + req_op, + req_f3, + req_amo_funct7, + req_addr, + req_st_value, + req_priv, + req_sstatus_SUM, + req_mstatus_MXR, + req_satp, + EN_req, + + valid, + + addr, + + word64, + + st_amo_val, + + exc, + + exc_code, + + EN_server_flush_request_put, + RDY_server_flush_request_put, + + EN_server_flush_response_get, + RDY_server_flush_response_get, + + EN_tlb_flush, + RDY_tlb_flush, + + mem_master_awid, + + mem_master_awaddr, + + mem_master_awlen, + + mem_master_awsize, + + mem_master_awburst, + + mem_master_awlock, + + mem_master_awcache, + + mem_master_awprot, + + mem_master_awqos, + + mem_master_awregion, + + mem_master_awvalid, + + mem_master_awready, + + mem_master_wdata, + + mem_master_wstrb, + + mem_master_wlast, + + mem_master_wvalid, + + mem_master_wready, + + mem_master_bid, + mem_master_bresp, + mem_master_bvalid, + + mem_master_bready, + + mem_master_arid, + + mem_master_araddr, + + mem_master_arlen, + + mem_master_arsize, + + mem_master_arburst, + + mem_master_arlock, + + mem_master_arcache, + + mem_master_arprot, + + mem_master_arqos, + + mem_master_arregion, + + mem_master_arvalid, + + mem_master_arready, + + mem_master_rid, + mem_master_rdata, + mem_master_rresp, + mem_master_rlast, + mem_master_rvalid, + + mem_master_rready); + input CLK; + input RST_N; + + // action method set_verbosity + input [3 : 0] set_verbosity_verbosity; + input EN_set_verbosity; + output RDY_set_verbosity; + + // action method server_reset_request_put + input EN_server_reset_request_put; + output RDY_server_reset_request_put; + + // action method server_reset_response_get + input EN_server_reset_response_get; + output RDY_server_reset_response_get; + + // action method req + input [1 : 0] req_op; + input [2 : 0] req_f3; + input [6 : 0] req_amo_funct7; + input [31 : 0] req_addr; + input [63 : 0] req_st_value; + input [1 : 0] req_priv; + input req_sstatus_SUM; + input req_mstatus_MXR; + input [31 : 0] req_satp; + input EN_req; + + // value method valid + output valid; + + // value method addr + output [31 : 0] addr; + + // value method word64 + output [63 : 0] word64; + + // value method st_amo_val + output [63 : 0] st_amo_val; + + // value method exc + output exc; + + // value method exc_code + output [3 : 0] exc_code; + + // action method server_flush_request_put + input EN_server_flush_request_put; + output RDY_server_flush_request_put; + + // action method server_flush_response_get + input EN_server_flush_response_get; + output RDY_server_flush_response_get; + + // action method tlb_flush + input EN_tlb_flush; + output RDY_tlb_flush; + + // value method mem_master_aw_awid + output [3 : 0] mem_master_awid; + + // value method mem_master_aw_awaddr + output [63 : 0] mem_master_awaddr; + + // value method mem_master_aw_awlen + output [7 : 0] mem_master_awlen; + + // value method mem_master_aw_awsize + output [2 : 0] mem_master_awsize; + + // value method mem_master_aw_awburst + output [1 : 0] mem_master_awburst; + + // value method mem_master_aw_awlock + output mem_master_awlock; + + // value method mem_master_aw_awcache + output [3 : 0] mem_master_awcache; + + // value method mem_master_aw_awprot + output [2 : 0] mem_master_awprot; + + // value method mem_master_aw_awqos + output [3 : 0] mem_master_awqos; + + // value method mem_master_aw_awregion + output [3 : 0] mem_master_awregion; + + // value method mem_master_aw_awuser + + // value method mem_master_aw_awvalid + output mem_master_awvalid; + + // action method mem_master_aw_awready + input mem_master_awready; + + // value method mem_master_w_wdata + output [63 : 0] mem_master_wdata; + + // value method mem_master_w_wstrb + output [7 : 0] mem_master_wstrb; + + // value method mem_master_w_wlast + output mem_master_wlast; + + // value method mem_master_w_wuser + + // value method mem_master_w_wvalid + output mem_master_wvalid; + + // action method mem_master_w_wready + input mem_master_wready; + + // action method mem_master_b_bflit + input [3 : 0] mem_master_bid; + input [1 : 0] mem_master_bresp; + input mem_master_bvalid; + + // value method mem_master_b_bready + output mem_master_bready; + + // value method mem_master_ar_arid + output [3 : 0] mem_master_arid; + + // value method mem_master_ar_araddr + output [63 : 0] mem_master_araddr; + + // value method mem_master_ar_arlen + output [7 : 0] mem_master_arlen; + + // value method mem_master_ar_arsize + output [2 : 0] mem_master_arsize; + + // value method mem_master_ar_arburst + output [1 : 0] mem_master_arburst; + + // value method mem_master_ar_arlock + output mem_master_arlock; + + // value method mem_master_ar_arcache + output [3 : 0] mem_master_arcache; + + // value method mem_master_ar_arprot + output [2 : 0] mem_master_arprot; + + // value method mem_master_ar_arqos + output [3 : 0] mem_master_arqos; + + // value method mem_master_ar_arregion + output [3 : 0] mem_master_arregion; + + // value method mem_master_ar_aruser + + // value method mem_master_ar_arvalid + output mem_master_arvalid; + + // action method mem_master_ar_arready + input mem_master_arready; + + // action method mem_master_r_rflit + input [3 : 0] mem_master_rid; + input [63 : 0] mem_master_rdata; + input [1 : 0] mem_master_rresp; + input mem_master_rlast; + input mem_master_rvalid; + + // value method mem_master_r_rready + output mem_master_rready; + + // signals for module outputs + reg [63 : 0] word64; + wire [63 : 0] mem_master_araddr, + mem_master_awaddr, + mem_master_wdata, + st_amo_val; + wire [31 : 0] addr; + wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; + wire [3 : 0] exc_code, + mem_master_arcache, + mem_master_arid, + mem_master_arqos, + mem_master_arregion, + mem_master_awcache, + mem_master_awid, + mem_master_awqos, + mem_master_awregion; + wire [2 : 0] mem_master_arprot, + mem_master_arsize, + mem_master_awprot, + mem_master_awsize; + wire [1 : 0] mem_master_arburst, mem_master_awburst; + wire RDY_server_flush_request_put, + RDY_server_flush_response_get, + RDY_server_reset_request_put, + RDY_server_reset_response_get, + RDY_set_verbosity, + RDY_tlb_flush, + exc, + mem_master_arlock, + mem_master_arvalid, + mem_master_awlock, + mem_master_awvalid, + mem_master_bready, + mem_master_rready, + mem_master_wlast, + mem_master_wvalid, + valid; + + // inlined wires + wire [97 : 0] cache_master_xactor_shim_arff_rv$port0__write_1, + cache_master_xactor_shim_arff_rv$port1__read, + cache_master_xactor_shim_arff_rv$port2__read, + cache_master_xactor_shim_arff_rv$port3__read, + cache_master_xactor_shim_awff_rv$port0__write_1, + cache_master_xactor_shim_awff_rv$port1__read, + cache_master_xactor_shim_awff_rv$port2__read, + cache_master_xactor_shim_awff_rv$port3__read; + wire [73 : 0] cache_master_xactor_shim_wff_rv$port0__write_1, + cache_master_xactor_shim_wff_rv$port1__read, + cache_master_xactor_shim_wff_rv$port2__read, + cache_master_xactor_shim_wff_rv$port3__read; + wire [71 : 0] cache_master_xactor_shim_rff_rv$port0__write_1, + cache_master_xactor_shim_rff_rv$port1__read, + cache_master_xactor_shim_rff_rv$port2__read, + cache_master_xactor_shim_rff_rv$port3__read; + wire [70 : 0] cache_master_xactor_ug_master_u_r_putWire$wget; + wire [10 : 0] cache_crg_sb_to_load_delay$port0__write_1, + cache_crg_sb_to_load_delay$port2__read; + wire [6 : 0] cache_master_xactor_shim_bff_rv$port0__write_1, + cache_master_xactor_shim_bff_rv$port1__read, + cache_master_xactor_shim_bff_rv$port2__read, + cache_master_xactor_shim_bff_rv$port3__read; + wire [5 : 0] cache_master_xactor_ug_master_u_b_putWire$wget; + wire [3 : 0] cache_ctr_wr_rsps_pending_crg$port0__write_1, + cache_ctr_wr_rsps_pending_crg$port1__read, + cache_ctr_wr_rsps_pending_crg$port1__write_1, + cache_ctr_wr_rsps_pending_crg$port2__read, + cache_ctr_wr_rsps_pending_crg$port3__read; + wire cache_crg_sb_to_load_delay$EN_port1__write, + cache_dw_valid$whas, + cache_master_xactor_shim_arff_rv$EN_port0__write, + cache_master_xactor_shim_rff_rv$EN_port1__write, + cache_master_xactor_ug_master_u_ar_dropWire$whas, + cache_master_xactor_ug_master_u_aw_dropWire$whas, + cache_master_xactor_ug_master_u_b_putWire$whas, + cache_master_xactor_ug_master_u_r_putWire$whas, + cache_master_xactor_ug_master_u_w_dropWire$whas; + + // register cache_cfg_verbosity + reg [3 : 0] cache_cfg_verbosity; + wire [3 : 0] cache_cfg_verbosity$D_IN; + wire cache_cfg_verbosity$EN; + + // register cache_crg_sb_to_load_delay + reg [10 : 0] cache_crg_sb_to_load_delay; + wire [10 : 0] cache_crg_sb_to_load_delay$D_IN; + wire cache_crg_sb_to_load_delay$EN; + + // register cache_ctr_wr_rsps_pending_crg + reg [3 : 0] cache_ctr_wr_rsps_pending_crg; + wire [3 : 0] cache_ctr_wr_rsps_pending_crg$D_IN; + wire cache_ctr_wr_rsps_pending_crg$EN; + + // register cache_master_xactor_clearing + reg cache_master_xactor_clearing; + wire cache_master_xactor_clearing$D_IN, cache_master_xactor_clearing$EN; + + // register cache_master_xactor_shim_arff_rv + reg [97 : 0] cache_master_xactor_shim_arff_rv; + wire [97 : 0] cache_master_xactor_shim_arff_rv$D_IN; + wire cache_master_xactor_shim_arff_rv$EN; + + // register cache_master_xactor_shim_awff_rv + reg [97 : 0] cache_master_xactor_shim_awff_rv; + wire [97 : 0] cache_master_xactor_shim_awff_rv$D_IN; + wire cache_master_xactor_shim_awff_rv$EN; + + // register cache_master_xactor_shim_bff_rv + reg [6 : 0] cache_master_xactor_shim_bff_rv; + wire [6 : 0] cache_master_xactor_shim_bff_rv$D_IN; + wire cache_master_xactor_shim_bff_rv$EN; + + // register cache_master_xactor_shim_rff_rv + reg [71 : 0] cache_master_xactor_shim_rff_rv; + wire [71 : 0] cache_master_xactor_shim_rff_rv$D_IN; + wire cache_master_xactor_shim_rff_rv$EN; + + // register cache_master_xactor_shim_wff_rv + reg [73 : 0] cache_master_xactor_shim_wff_rv; + wire [73 : 0] cache_master_xactor_shim_wff_rv$D_IN; + wire cache_master_xactor_shim_wff_rv$EN; + + // register cache_rg_addr + reg [31 : 0] cache_rg_addr; + wire [31 : 0] cache_rg_addr$D_IN; + wire cache_rg_addr$EN; + + // register cache_rg_amo_funct7 + reg [6 : 0] cache_rg_amo_funct7; + wire [6 : 0] cache_rg_amo_funct7$D_IN; + wire cache_rg_amo_funct7$EN; + + // register cache_rg_cset_in_cache + reg [6 : 0] cache_rg_cset_in_cache; + wire [6 : 0] cache_rg_cset_in_cache$D_IN; + wire cache_rg_cset_in_cache$EN; + + // register cache_rg_error_during_refill + reg cache_rg_error_during_refill; + wire cache_rg_error_during_refill$D_IN, cache_rg_error_during_refill$EN; + + // register cache_rg_exc_code + reg [3 : 0] cache_rg_exc_code; + reg [3 : 0] cache_rg_exc_code$D_IN; + wire cache_rg_exc_code$EN; + + // register cache_rg_f3 + reg [2 : 0] cache_rg_f3; + wire [2 : 0] cache_rg_f3$D_IN; + wire cache_rg_f3$EN; + + // register cache_rg_ld_val + reg [63 : 0] cache_rg_ld_val; + reg [63 : 0] cache_rg_ld_val$D_IN; + wire cache_rg_ld_val$EN; + + // register cache_rg_lower_word32 + reg [31 : 0] cache_rg_lower_word32; + wire [31 : 0] cache_rg_lower_word32$D_IN; + wire cache_rg_lower_word32$EN; + + // register cache_rg_lower_word32_full + reg cache_rg_lower_word32_full; + wire cache_rg_lower_word32_full$D_IN, cache_rg_lower_word32_full$EN; + + // register cache_rg_lrsc_pa + reg [31 : 0] cache_rg_lrsc_pa; + wire [31 : 0] cache_rg_lrsc_pa$D_IN; + wire cache_rg_lrsc_pa$EN; + + // register cache_rg_lrsc_valid + reg cache_rg_lrsc_valid; + wire cache_rg_lrsc_valid$D_IN, cache_rg_lrsc_valid$EN; + + // register cache_rg_op + reg [1 : 0] cache_rg_op; + wire [1 : 0] cache_rg_op$D_IN; + wire cache_rg_op$EN; + + // register cache_rg_pa + reg [31 : 0] cache_rg_pa; + wire [31 : 0] cache_rg_pa$D_IN; + wire cache_rg_pa$EN; + + // register cache_rg_pte_pa + reg [31 : 0] cache_rg_pte_pa; + wire [31 : 0] cache_rg_pte_pa$D_IN; + wire cache_rg_pte_pa$EN; + + // register cache_rg_st_amo_val + reg [63 : 0] cache_rg_st_amo_val; + wire [63 : 0] cache_rg_st_amo_val$D_IN; + wire cache_rg_st_amo_val$EN; + + // register cache_rg_state + reg [3 : 0] cache_rg_state; + reg [3 : 0] cache_rg_state$D_IN; + wire cache_rg_state$EN; + + // register cache_rg_word64_set_in_cache + reg [8 : 0] cache_rg_word64_set_in_cache; + wire [8 : 0] cache_rg_word64_set_in_cache$D_IN; + wire cache_rg_word64_set_in_cache$EN; + + // ports of submodule cache_f_fabric_write_reqs + reg [98 : 0] cache_f_fabric_write_reqs$D_IN; + wire [98 : 0] cache_f_fabric_write_reqs$D_OUT; + wire cache_f_fabric_write_reqs$CLR, + cache_f_fabric_write_reqs$DEQ, + cache_f_fabric_write_reqs$EMPTY_N, + cache_f_fabric_write_reqs$ENQ, + cache_f_fabric_write_reqs$FULL_N; + + // ports of submodule cache_f_reset_reqs + wire cache_f_reset_reqs$CLR, + cache_f_reset_reqs$DEQ, + cache_f_reset_reqs$D_IN, + cache_f_reset_reqs$D_OUT, + cache_f_reset_reqs$EMPTY_N, + cache_f_reset_reqs$ENQ, + cache_f_reset_reqs$FULL_N; + + // ports of submodule cache_f_reset_rsps + wire cache_f_reset_rsps$CLR, + cache_f_reset_rsps$DEQ, + cache_f_reset_rsps$D_IN, + cache_f_reset_rsps$D_OUT, + cache_f_reset_rsps$EMPTY_N, + cache_f_reset_rsps$ENQ, + cache_f_reset_rsps$FULL_N; + + // ports of submodule cache_ram_state_and_ctag_cset + wire [22 : 0] cache_ram_state_and_ctag_cset$DIA, + cache_ram_state_and_ctag_cset$DIB, + cache_ram_state_and_ctag_cset$DOB; + wire [6 : 0] cache_ram_state_and_ctag_cset$ADDRA, + cache_ram_state_and_ctag_cset$ADDRB; + wire cache_ram_state_and_ctag_cset$ENA, + cache_ram_state_and_ctag_cset$ENB, + cache_ram_state_and_ctag_cset$WEA, + cache_ram_state_and_ctag_cset$WEB; + + // ports of submodule cache_ram_word64_set + reg [63 : 0] cache_ram_word64_set$DIB; + reg [8 : 0] cache_ram_word64_set$ADDRB; + wire [63 : 0] cache_ram_word64_set$DIA, cache_ram_word64_set$DOB; + wire [8 : 0] cache_ram_word64_set$ADDRA; + wire cache_ram_word64_set$ENA, + cache_ram_word64_set$ENB, + cache_ram_word64_set$WEA, + cache_ram_word64_set$WEB; + + // ports of submodule cache_soc_map + wire [63 : 0] cache_soc_map$m_is_IO_addr_addr, + cache_soc_map$m_is_mem_addr_addr, + cache_soc_map$m_is_near_mem_IO_addr_addr; + wire cache_soc_map$m_is_mem_addr; + + // rule scheduling signals + wire CAN_FIRE_RL_cache_master_xactor_do_clear, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_cache_rl_ST_AMO_response, + CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop, + CAN_FIRE_RL_cache_rl_discard_write_rsp, + CAN_FIRE_RL_cache_rl_drive_exception_rsp, + CAN_FIRE_RL_cache_rl_fabric_send_write_req, + CAN_FIRE_RL_cache_rl_io_AMO_SC_req, + CAN_FIRE_RL_cache_rl_io_AMO_op_req, + CAN_FIRE_RL_cache_rl_io_AMO_read_rsp, + CAN_FIRE_RL_cache_rl_io_read_req, + CAN_FIRE_RL_cache_rl_io_read_rsp, + CAN_FIRE_RL_cache_rl_io_write_req, + CAN_FIRE_RL_cache_rl_maintain_io_read_rsp, + CAN_FIRE_RL_cache_rl_probe_and_immed_rsp, + CAN_FIRE_RL_cache_rl_rereq, + CAN_FIRE_RL_cache_rl_reset, + CAN_FIRE_RL_cache_rl_shift_sb_to_load_delay, + CAN_FIRE_RL_cache_rl_start_cache_refill, + CAN_FIRE_RL_cache_rl_start_reset, + CAN_FIRE_mem_master_ar_arready, + CAN_FIRE_mem_master_aw_awready, + CAN_FIRE_mem_master_b_bflit, + CAN_FIRE_mem_master_r_rflit, + CAN_FIRE_mem_master_w_wready, + CAN_FIRE_req, + CAN_FIRE_server_flush_request_put, + CAN_FIRE_server_flush_response_get, + CAN_FIRE_server_reset_request_put, + CAN_FIRE_server_reset_response_get, + CAN_FIRE_set_verbosity, + CAN_FIRE_tlb_flush, + WILL_FIRE_RL_cache_master_xactor_do_clear, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_cache_rl_ST_AMO_response, + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop, + WILL_FIRE_RL_cache_rl_discard_write_rsp, + WILL_FIRE_RL_cache_rl_drive_exception_rsp, + WILL_FIRE_RL_cache_rl_fabric_send_write_req, + WILL_FIRE_RL_cache_rl_io_AMO_SC_req, + WILL_FIRE_RL_cache_rl_io_AMO_op_req, + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp, + WILL_FIRE_RL_cache_rl_io_read_req, + WILL_FIRE_RL_cache_rl_io_read_rsp, + WILL_FIRE_RL_cache_rl_io_write_req, + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp, + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp, + WILL_FIRE_RL_cache_rl_rereq, + WILL_FIRE_RL_cache_rl_reset, + WILL_FIRE_RL_cache_rl_shift_sb_to_load_delay, + WILL_FIRE_RL_cache_rl_start_cache_refill, + WILL_FIRE_RL_cache_rl_start_reset, + WILL_FIRE_mem_master_ar_arready, + WILL_FIRE_mem_master_aw_awready, + WILL_FIRE_mem_master_b_bflit, + WILL_FIRE_mem_master_r_rflit, + WILL_FIRE_mem_master_w_wready, + WILL_FIRE_req, + WILL_FIRE_server_flush_request_put, + WILL_FIRE_server_flush_response_get, + WILL_FIRE_server_reset_request_put, + WILL_FIRE_server_reset_response_get, + WILL_FIRE_set_verbosity, + WILL_FIRE_tlb_flush; + + // inputs to muxes for submodule ports + reg [63 : 0] MUX_cache_dw_output_ld_val$wset_1__VAL_1, + MUX_cache_dw_output_ld_val$wset_1__VAL_2; + wire [98 : 0] MUX_cache_f_fabric_write_reqs$enq_1__VAL_1, + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2, + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3; + wire [97 : 0] MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1, + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2; + wire [63 : 0] MUX_cache_dw_output_ld_val$wset_1__VAL_3, + MUX_cache_ram_word64_set$a_put_3__VAL_2, + MUX_cache_rg_ld_val$write_1__VAL_2, + MUX_cache_rg_st_amo_val$write_1__VAL_2; + wire [22 : 0] MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1; + wire [8 : 0] MUX_cache_ram_word64_set$b_put_2__VAL_2, + MUX_cache_ram_word64_set$b_put_2__VAL_4; + wire [6 : 0] MUX_cache_rg_cset_in_cache$write_1__VAL_1; + wire [3 : 0] MUX_cache_rg_exc_code$write_1__VAL_1, + MUX_cache_rg_exc_code$write_1__VAL_4, + MUX_cache_rg_state$write_1__VAL_1, + MUX_cache_rg_state$write_1__VAL_12, + MUX_cache_rg_state$write_1__VAL_2, + MUX_cache_rg_state$write_1__VAL_4; + wire MUX_cache_dw_output_ld_val$wset_1__SEL_1, + MUX_cache_dw_output_ld_val$wset_1__SEL_2, + MUX_cache_dw_output_ld_val$wset_1__SEL_3, + MUX_cache_dw_output_ld_val$wset_1__SEL_4, + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2, + MUX_cache_master_xactor_clearing$write_1__SEL_2, + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1, + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1, + MUX_cache_ram_word64_set$a_put_1__SEL_1, + MUX_cache_ram_word64_set$b_put_1__SEL_2, + MUX_cache_rg_error_during_refill$write_1__SEL_1, + MUX_cache_rg_exc_code$write_1__SEL_1, + MUX_cache_rg_exc_code$write_1__SEL_2, + MUX_cache_rg_exc_code$write_1__SEL_3, + MUX_cache_rg_ld_val$write_1__SEL_2, + MUX_cache_rg_lrsc_valid$write_1__SEL_2, + MUX_cache_rg_lrsc_valid$write_1__VAL_2, + MUX_cache_rg_state$write_1__SEL_12, + MUX_cache_rg_state$write_1__SEL_13, + MUX_cache_rg_state$write_1__SEL_4; + + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h5604; + reg [31 : 0] v__h6425; + reg [31 : 0] v__h6526; + reg [31 : 0] v__h6977; + reg [31 : 0] v__h15442; + reg [31 : 0] v__h19086; + reg [31 : 0] v__h22330; + reg [31 : 0] v__h25145; + reg [31 : 0] v__h26849; + reg [31 : 0] v__h26929; + reg [31 : 0] v__h27139; + reg [31 : 0] v__h27257; + reg [31 : 0] v__h30743; + reg [31 : 0] v__h30704; + reg [31 : 0] v__h6060; + reg [31 : 0] v__h23274; + reg [31 : 0] v__h23536; + reg [31 : 0] v__h25517; + reg [31 : 0] v__h26635; + reg [31 : 0] v__h26742; + reg [31 : 0] v__h27573; + reg [31 : 0] v__h27768; + reg [31 : 0] v__h30027; + reg [31 : 0] v__h27864; + reg [31 : 0] v__h31126; + reg [31 : 0] v__h5598; + reg [31 : 0] v__h6054; + reg [31 : 0] v__h6419; + reg [31 : 0] v__h6520; + reg [31 : 0] v__h6971; + reg [31 : 0] v__h15436; + reg [31 : 0] v__h19080; + reg [31 : 0] v__h22324; + reg [31 : 0] v__h23268; + reg [31 : 0] v__h23530; + reg [31 : 0] v__h25139; + reg [31 : 0] v__h25511; + reg [31 : 0] v__h26629; + reg [31 : 0] v__h26736; + reg [31 : 0] v__h26843; + reg [31 : 0] v__h26923; + reg [31 : 0] v__h27133; + reg [31 : 0] v__h27251; + reg [31 : 0] v__h27567; + reg [31 : 0] v__h27762; + reg [31 : 0] v__h27858; + reg [31 : 0] v__h30021; + reg [31 : 0] v__h30698; + reg [31 : 0] v__h30737; + reg [31 : 0] v__h31120; + // synopsys translate_on + + // remaining internal signals + reg [63 : 0] CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851, + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443, + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517, + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385, + _theResult_____2__h19586, + _theResult_____2__h27940, + mem_req_wr_data_wdata__h5352, + new_value__h18177, + new_value__h8148, + w1__h19578, + w1__h27928, + w1__h27932; + reg [7 : 0] mem_req_wr_data_wstrb__h5353; + reg [2 : 0] _theResult___snd_snd_val__h5236, size_val__h27412; + wire [96 : 0] cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35, + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1; + wire [72 : 0] cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q16; + wire [63 : 0] IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d354, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852, + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449, + IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d531, + _theResult___fst__h5221, + cline_fabric_addr__h22383, + fabric_addr__h27309, + ld_val__h25642, + mem_req_wr_addr_awaddr__h5054, + new_ld_val__h27894, + new_st_val__h19308, + new_st_val__h19590, + new_st_val__h19681, + new_st_val__h20661, + new_st_val__h20665, + new_st_val__h20669, + new_st_val__h20673, + new_st_val__h20678, + new_st_val__h20684, + new_st_val__h20689, + new_st_val__h27944, + new_st_val__h28035, + new_st_val__h29895, + new_st_val__h29899, + new_st_val__h29903, + new_st_val__h29907, + new_st_val__h29912, + new_st_val__h29918, + new_st_val__h29923, + result__h14559, + result__h14587, + result__h14615, + result__h14643, + result__h14671, + result__h14699, + result__h14727, + result__h14772, + result__h14800, + result__h14828, + result__h14856, + result__h14884, + result__h14912, + result__h14940, + result__h14968, + result__h15013, + result__h15041, + result__h15069, + result__h15097, + result__h15138, + result__h15166, + result__h15194, + result__h15222, + result__h15263, + result__h15291, + result__h15330, + result__h15358, + result__h25702, + result__h25732, + result__h25759, + result__h25786, + result__h25813, + result__h25840, + result__h25867, + result__h25894, + result__h25938, + result__h25965, + result__h25992, + result__h26019, + result__h26046, + result__h26073, + result__h26100, + result__h26127, + result__h26171, + result__h26198, + result__h26225, + result__h26252, + result__h26292, + result__h26319, + result__h26346, + result__h26373, + result__h26413, + result__h26440, + result__h26478, + result__h26505, + result__h28123, + result__h29031, + result__h29059, + result__h29087, + result__h29115, + result__h29143, + result__h29171, + result__h29199, + result__h29244, + result__h29272, + result__h29300, + result__h29328, + result__h29356, + result__h29384, + result__h29412, + result__h29440, + result__h29485, + result__h29513, + result__h29541, + result__h29569, + result__h29610, + result__h29638, + result__h29666, + result__h29694, + result__h29735, + result__h29763, + result__h29802, + result__h29830, + result__h8203, + w1___1__h19649, + w1___1__h28003, + w2___1__h28004, + w2__h27934, + word64__h7969, + x__h15829, + x__h27923, + y__h8239; + wire [31 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q11, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q4, + cache_rg_st_amo_val_BITS_31_TO_0__q33, + cline_addr__h22382, + ld_val5642_BITS_31_TO_0__q40, + ld_val5642_BITS_63_TO_32__q47, + new_value148_BITS_31_TO_0__q32, + w17928_BITS_31_TO_0__q53, + word64969_BITS_31_TO_0__q19, + word64969_BITS_63_TO_32__q26; + wire [21 : 0] pa_ctag__h7827; + wire [15 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q10, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q14, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q3, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q7, + ld_val5642_BITS_15_TO_0__q39, + ld_val5642_BITS_31_TO_16__q43, + ld_val5642_BITS_47_TO_32__q46, + ld_val5642_BITS_63_TO_48__q50, + word64969_BITS_15_TO_0__q18, + word64969_BITS_31_TO_16__q22, + word64969_BITS_47_TO_32__q25, + word64969_BITS_63_TO_48__q29; + wire [7 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q12, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q13, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q15, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q2, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q5, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q6, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q8, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q9, + ld_val5642_BITS_15_TO_8__q41, + ld_val5642_BITS_23_TO_16__q42, + ld_val5642_BITS_31_TO_24__q44, + ld_val5642_BITS_39_TO_32__q45, + ld_val5642_BITS_47_TO_40__q48, + ld_val5642_BITS_55_TO_48__q49, + ld_val5642_BITS_63_TO_56__q51, + ld_val5642_BITS_7_TO_0__q38, + strobe64__h5219, + strobe64__h5223, + strobe64__h5227, + word64969_BITS_15_TO_8__q20, + word64969_BITS_23_TO_16__q21, + word64969_BITS_31_TO_24__q23, + word64969_BITS_39_TO_32__q24, + word64969_BITS_47_TO_40__q27, + word64969_BITS_55_TO_48__q28, + word64969_BITS_63_TO_56__q30, + word64969_BITS_7_TO_0__q17; + wire [5 : 0] shift_bits__h5069; + wire [3 : 0] IF_cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_ETC___d196, + IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d195, + access_exc_code__h4779, + b__h22284; + wire IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d164, + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91, + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603, + NOT_cache_ram_state_and_ctag_cset_b_read__54_B_ETC___d202, + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d191, + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d529, + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549, + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d557, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d211, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d389, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d523, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d565, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d568, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d572, + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d387, + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d521, + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d547, + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d551, + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d555, + NOT_req_f3_BITS_1_TO_0_44_EQ_0b0_45_46_AND_NOT_ETC___d965, + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160, + cache_ram_state_and_ctag_cset_b_read__54_BIT_2_ETC___d203, + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200, + cache_rg_amo_funct7_36_BITS_6_TO_2_37_EQ_0b10__ETC___d375, + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148, + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d186, + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d214, + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d219, + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d358, + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d371, + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d212, + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d390, + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d524, + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d527, + cache_rg_op_33_EQ_2_35_AND_cache_rg_amo_funct7_ETC___d561, + cache_rg_state_7_EQ_12_46_AND_cache_rg_op_33_E_ETC___d648, + cache_rg_state_7_EQ_3_67_AND_NOT_cache_rg_op_3_ETC___d176, + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d381, + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d392, + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570, + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d576, + lrsc_result__h15819, + req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974; + + // action method set_verbosity + assign RDY_set_verbosity = 1'd1 ; + assign CAN_FIRE_set_verbosity = 1'd1 ; + assign WILL_FIRE_set_verbosity = EN_set_verbosity ; + + // action method server_reset_request_put + assign RDY_server_reset_request_put = cache_f_reset_reqs$FULL_N ; + assign CAN_FIRE_server_reset_request_put = cache_f_reset_reqs$FULL_N ; + assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; + + // action method server_reset_response_get + assign RDY_server_reset_response_get = + !cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign CAN_FIRE_server_reset_response_get = + !cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; + + // action method req + assign CAN_FIRE_req = 1'd1 ; + assign WILL_FIRE_req = EN_req ; + + // value method valid + assign valid = cache_dw_valid$whas ; + + // value method addr + assign addr = cache_rg_addr ; + + // value method word64 + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_1 or + MUX_cache_dw_output_ld_val$wset_1__VAL_1 or + MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + MUX_cache_dw_output_ld_val$wset_1__VAL_2 or + MUX_cache_dw_output_ld_val$wset_1__SEL_3 or + MUX_cache_dw_output_ld_val$wset_1__VAL_3 or + MUX_cache_dw_output_ld_val$wset_1__SEL_4 or cache_rg_ld_val) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_1: + word64 = MUX_cache_dw_output_ld_val$wset_1__VAL_1; + MUX_cache_dw_output_ld_val$wset_1__SEL_2: + word64 = MUX_cache_dw_output_ld_val$wset_1__VAL_2; + MUX_cache_dw_output_ld_val$wset_1__SEL_3: + word64 = MUX_cache_dw_output_ld_val$wset_1__VAL_3; + MUX_cache_dw_output_ld_val$wset_1__SEL_4: word64 = cache_rg_ld_val; + default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // value method st_amo_val + assign st_amo_val = + MUX_cache_dw_output_ld_val$wset_1__SEL_3 ? + 64'd0 : + cache_rg_st_amo_val ; + + // value method exc + assign exc = cache_rg_state == 4'd4 ; + + // value method exc_code + assign exc_code = cache_rg_exc_code ; + + // action method server_flush_request_put + assign RDY_server_flush_request_put = cache_f_reset_reqs$FULL_N ; + assign CAN_FIRE_server_flush_request_put = cache_f_reset_reqs$FULL_N ; + assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; + + // action method server_flush_response_get + assign RDY_server_flush_response_get = + cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign CAN_FIRE_server_flush_response_get = + cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; + + // action method tlb_flush + assign RDY_tlb_flush = 1'd1 ; + assign CAN_FIRE_tlb_flush = 1'd1 ; + assign WILL_FIRE_tlb_flush = EN_tlb_flush ; + + // value method mem_master_aw_awid + assign mem_master_awid = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[96:93] ; + + // value method mem_master_aw_awaddr + assign mem_master_awaddr = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[92:29] ; + + // value method mem_master_aw_awlen + assign mem_master_awlen = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[28:21] ; + + // value method mem_master_aw_awsize + assign mem_master_awsize = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[20:18] ; + + // value method mem_master_aw_awburst + assign mem_master_awburst = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[17:16] ; + + // value method mem_master_aw_awlock + assign mem_master_awlock = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[15] ; + + // value method mem_master_aw_awcache + assign mem_master_awcache = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[14:11] ; + + // value method mem_master_aw_awprot + assign mem_master_awprot = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[10:8] ; + + // value method mem_master_aw_awqos + assign mem_master_awqos = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[7:4] ; + + // value method mem_master_aw_awregion + assign mem_master_awregion = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[3:0] ; + + // value method mem_master_aw_awvalid + assign mem_master_awvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek ; + + // action method mem_master_aw_awready + assign CAN_FIRE_mem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_mem_master_aw_awready = 1'd1 ; + + // value method mem_master_w_wdata + assign mem_master_wdata = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q16[72:9] ; + + // value method mem_master_w_wstrb + assign mem_master_wstrb = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q16[8:1] ; + + // value method mem_master_w_wlast + assign mem_master_wlast = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q16[0] ; + + // value method mem_master_w_wvalid + assign mem_master_wvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek ; + + // action method mem_master_w_wready + assign CAN_FIRE_mem_master_w_wready = 1'd1 ; + assign WILL_FIRE_mem_master_w_wready = 1'd1 ; + + // action method mem_master_b_bflit + assign CAN_FIRE_mem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_mem_master_b_bflit = mem_master_bvalid ; + + // value method mem_master_b_bready + assign mem_master_bready = !cache_master_xactor_shim_bff_rv[6] ; + + // value method mem_master_ar_arid + assign mem_master_arid = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[96:93] ; + + // value method mem_master_ar_araddr + assign mem_master_araddr = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[92:29] ; + + // value method mem_master_ar_arlen + assign mem_master_arlen = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[28:21] ; + + // value method mem_master_ar_arsize + assign mem_master_arsize = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[20:18] ; + + // value method mem_master_ar_arburst + assign mem_master_arburst = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[17:16] ; + + // value method mem_master_ar_arlock + assign mem_master_arlock = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[15] ; + + // value method mem_master_ar_arcache + assign mem_master_arcache = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[14:11] ; + + // value method mem_master_ar_arprot + assign mem_master_arprot = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[10:8] ; + + // value method mem_master_ar_arqos + assign mem_master_arqos = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[7:4] ; + + // value method mem_master_ar_arregion + assign mem_master_arregion = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[3:0] ; + + // value method mem_master_ar_arvalid + assign mem_master_arvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek ; + + // action method mem_master_ar_arready + assign CAN_FIRE_mem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_mem_master_ar_arready = 1'd1 ; + + // action method mem_master_r_rflit + assign CAN_FIRE_mem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_mem_master_r_rflit = mem_master_rvalid ; + + // value method mem_master_r_rready + assign mem_master_rready = !cache_master_xactor_shim_rff_rv[71] ; + + // submodule cache_f_fabric_write_reqs + FIFO2 #(.width(32'd99), + .guarded(32'd1)) cache_f_fabric_write_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_fabric_write_reqs$D_IN), + .ENQ(cache_f_fabric_write_reqs$ENQ), + .DEQ(cache_f_fabric_write_reqs$DEQ), + .CLR(cache_f_fabric_write_reqs$CLR), + .D_OUT(cache_f_fabric_write_reqs$D_OUT), + .FULL_N(cache_f_fabric_write_reqs$FULL_N), + .EMPTY_N(cache_f_fabric_write_reqs$EMPTY_N)); + + // submodule cache_f_reset_reqs + FIFO2 #(.width(32'd1), .guarded(32'd1)) cache_f_reset_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_reset_reqs$D_IN), + .ENQ(cache_f_reset_reqs$ENQ), + .DEQ(cache_f_reset_reqs$DEQ), + .CLR(cache_f_reset_reqs$CLR), + .D_OUT(cache_f_reset_reqs$D_OUT), + .FULL_N(cache_f_reset_reqs$FULL_N), + .EMPTY_N(cache_f_reset_reqs$EMPTY_N)); + + // submodule cache_f_reset_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) cache_f_reset_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_reset_rsps$D_IN), + .ENQ(cache_f_reset_rsps$ENQ), + .DEQ(cache_f_reset_rsps$DEQ), + .CLR(cache_f_reset_rsps$CLR), + .D_OUT(cache_f_reset_rsps$D_OUT), + .FULL_N(cache_f_reset_rsps$FULL_N), + .EMPTY_N(cache_f_reset_rsps$EMPTY_N)); + + // submodule cache_ram_state_and_ctag_cset + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd7), + .DATA_WIDTH(32'd23), + .MEMSIZE(8'd128)) cache_ram_state_and_ctag_cset(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(cache_ram_state_and_ctag_cset$ADDRA), + .ADDRB(cache_ram_state_and_ctag_cset$ADDRB), + .DIA(cache_ram_state_and_ctag_cset$DIA), + .DIB(cache_ram_state_and_ctag_cset$DIB), + .WEA(cache_ram_state_and_ctag_cset$WEA), + .WEB(cache_ram_state_and_ctag_cset$WEB), + .ENA(cache_ram_state_and_ctag_cset$ENA), + .ENB(cache_ram_state_and_ctag_cset$ENB), + .DOA(), + .DOB(cache_ram_state_and_ctag_cset$DOB)); + + // submodule cache_ram_word64_set + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd9), + .DATA_WIDTH(32'd64), + .MEMSIZE(10'd512)) cache_ram_word64_set(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(cache_ram_word64_set$ADDRA), + .ADDRB(cache_ram_word64_set$ADDRB), + .DIA(cache_ram_word64_set$DIA), + .DIB(cache_ram_word64_set$DIB), + .WEA(cache_ram_word64_set$WEA), + .WEB(cache_ram_word64_set$WEB), + .ENA(cache_ram_word64_set$ENA), + .ENB(cache_ram_word64_set$ENB), + .DOA(), + .DOB(cache_ram_word64_set$DOB)); + + // submodule cache_soc_map + mkSoC_Map cache_soc_map(.CLK(CLK), + .RST_N(RST_N), + .m_is_IO_addr_addr(cache_soc_map$m_is_IO_addr_addr), + .m_is_mem_addr_addr(cache_soc_map$m_is_mem_addr_addr), + .m_is_near_mem_IO_addr_addr(cache_soc_map$m_is_near_mem_IO_addr_addr), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), + .m_is_mem_addr(cache_soc_map$m_is_mem_addr), + .m_is_IO_addr(), + .m_is_near_mem_IO_addr(), + .m_pc_reset_value(), + .m_mtvec_reset_value(), + .m_nmivec_reset_value()); + + // rule RL_cache_rl_fabric_send_write_req + assign CAN_FIRE_RL_cache_rl_fabric_send_write_req = + !cache_master_xactor_clearing && + cache_f_fabric_write_reqs$EMPTY_N && + !cache_master_xactor_shim_awff_rv[97] && + !cache_master_xactor_shim_wff_rv[73] ; + assign WILL_FIRE_RL_cache_rl_fabric_send_write_req = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ; + + // rule RL_cache_rl_reset + assign CAN_FIRE_RL_cache_rl_reset = + (cache_rg_cset_in_cache != 7'd127 || + cache_f_reset_reqs$EMPTY_N && cache_f_reset_rsps$FULL_N) && + cache_rg_state == 4'd1 ; + assign WILL_FIRE_RL_cache_rl_reset = CAN_FIRE_RL_cache_rl_reset ; + + // rule RL_cache_rl_shift_sb_to_load_delay + assign CAN_FIRE_RL_cache_rl_shift_sb_to_load_delay = 1'd1 ; + assign WILL_FIRE_RL_cache_rl_shift_sb_to_load_delay = 1'd1 ; + + // rule RL_cache_rl_probe_and_immed_rsp + assign CAN_FIRE_RL_cache_rl_probe_and_immed_rsp = + (!cache_soc_map$m_is_mem_addr || cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010 || + IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d164) && + cache_rg_state_7_EQ_3_67_AND_NOT_cache_rg_op_3_ETC___d176 ; + assign WILL_FIRE_RL_cache_rl_probe_and_immed_rsp = + CAN_FIRE_RL_cache_rl_probe_and_immed_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_start_cache_refill + assign CAN_FIRE_RL_cache_rl_start_cache_refill = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[97] && + cache_rg_state == 4'd8 && + b__h22284 == 4'd0 ; + assign WILL_FIRE_RL_cache_rl_start_cache_refill = + CAN_FIRE_RL_cache_rl_start_cache_refill && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_rereq + assign CAN_FIRE_RL_cache_rl_rereq = cache_rg_state == 4'd10 ; + assign WILL_FIRE_RL_cache_rl_rereq = + CAN_FIRE_RL_cache_rl_rereq && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_ST_AMO_response + assign CAN_FIRE_RL_cache_rl_ST_AMO_response = cache_rg_state == 4'd11 ; + assign WILL_FIRE_RL_cache_rl_ST_AMO_response = + CAN_FIRE_RL_cache_rl_ST_AMO_response ; + + // rule RL_cache_rl_io_read_req + assign CAN_FIRE_RL_cache_rl_io_read_req = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[97] && + cache_rg_state_7_EQ_12_46_AND_cache_rg_op_33_E_ETC___d648 ; + assign WILL_FIRE_RL_cache_rl_io_read_req = + CAN_FIRE_RL_cache_rl_io_read_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_maintain_io_read_rsp + assign CAN_FIRE_RL_cache_rl_maintain_io_read_rsp = cache_rg_state == 4'd14 ; + assign WILL_FIRE_RL_cache_rl_maintain_io_read_rsp = + CAN_FIRE_RL_cache_rl_maintain_io_read_rsp ; + + // rule RL_cache_rl_io_write_req + assign CAN_FIRE_RL_cache_rl_io_write_req = + cache_f_fabric_write_reqs$FULL_N && cache_rg_state == 4'd12 && + cache_rg_op == 2'd1 ; + assign WILL_FIRE_RL_cache_rl_io_write_req = + CAN_FIRE_RL_cache_rl_io_write_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_SC_req + assign CAN_FIRE_RL_cache_rl_io_AMO_SC_req = + cache_rg_state == 4'd12 && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_SC_req = + CAN_FIRE_RL_cache_rl_io_AMO_SC_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_op_req + assign CAN_FIRE_RL_cache_rl_io_AMO_op_req = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[97] && + cache_rg_state == 4'd12 && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] != 5'b00010 && + cache_rg_amo_funct7[6:2] != 5'b00011 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_op_req = + CAN_FIRE_RL_cache_rl_io_AMO_op_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_drive_exception_rsp + assign CAN_FIRE_RL_cache_rl_drive_exception_rsp = cache_rg_state == 4'd4 ; + assign WILL_FIRE_RL_cache_rl_drive_exception_rsp = cache_rg_state == 4'd4 ; + + // rule RL_cache_master_xactor_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek = + cache_master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop = + cache_master_xactor_ug_master_u_aw_dropWire$whas && + !cache_master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop = + cache_master_xactor_shim_awff_rv$port1__read[97] && + cache_master_xactor_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_w_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek = + cache_master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop = + cache_master_xactor_ug_master_u_w_dropWire$whas && + !cache_master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_w_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop = + cache_master_xactor_shim_wff_rv$port1__read[73] && + cache_master_xactor_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut = + cache_master_xactor_ug_master_u_b_putWire$whas && + cache_master_xactor_shim_bff_rv[6] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut ; + + // rule RL_cache_master_xactor_ug_master_u_b_doPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut = + !cache_master_xactor_shim_bff_rv[6] && + cache_master_xactor_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut ; + + // rule RL_cache_rl_discard_write_rsp + assign CAN_FIRE_RL_cache_rl_discard_write_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_bff_rv$port1__read[6] && + b__h22284 != 4'd0 ; + assign WILL_FIRE_RL_cache_rl_discard_write_rsp = + CAN_FIRE_RL_cache_rl_discard_write_rsp ; + + // rule RL_cache_rl_start_reset + assign CAN_FIRE_RL_cache_rl_start_reset = + cache_f_reset_reqs$EMPTY_N && + (cache_f_reset_reqs$D_OUT || !cache_master_xactor_clearing) && + cache_rg_state != 4'd1 ; + assign WILL_FIRE_RL_cache_rl_start_reset = + CAN_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_master_xactor_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek = + cache_master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop = + cache_master_xactor_ug_master_u_ar_dropWire$whas && + !cache_master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop = + cache_master_xactor_shim_arff_rv$port1__read[97] && + cache_master_xactor_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut = + cache_master_xactor_ug_master_u_r_putWire$whas && + cache_master_xactor_shim_rff_rv[71] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut ; + + // rule RL_cache_master_xactor_ug_master_u_r_doPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut = + !cache_master_xactor_shim_rff_rv[71] && + cache_master_xactor_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut ; + + // rule RL_cache_rl_cache_refill_rsps_loop + assign CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[71] && + cache_rg_state == 4'd9 ; + assign WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop = + CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_io_read_rsp + assign CAN_FIRE_RL_cache_rl_io_read_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[71] && + cache_rg_state == 4'd13 ; + assign WILL_FIRE_RL_cache_rl_io_read_rsp = + CAN_FIRE_RL_cache_rl_io_read_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_read_rsp + assign CAN_FIRE_RL_cache_rl_io_AMO_read_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[71] && + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_f_fabric_write_reqs$FULL_N) && + cache_rg_state == 4'd15 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_read_rsp = + CAN_FIRE_RL_cache_rl_io_AMO_read_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_master_xactor_do_clear + assign CAN_FIRE_RL_cache_master_xactor_do_clear = + cache_master_xactor_clearing ; + assign WILL_FIRE_RL_cache_master_xactor_do_clear = + cache_master_xactor_clearing ; + + // inputs to muxes for submodule ports + assign MUX_cache_dw_output_ld_val$wset_1__SEL_1 = + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_2 = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_3 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d219 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_4 = + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp || + WILL_FIRE_RL_cache_rl_ST_AMO_response ; + assign MUX_cache_f_fabric_write_reqs$enq_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d529 ; + assign MUX_cache_master_xactor_clearing$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_start_reset && !cache_f_reset_reqs$D_OUT ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1 = + WILL_FIRE_RL_cache_rl_io_AMO_op_req || + WILL_FIRE_RL_cache_rl_io_read_req ; + assign MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 = + EN_req && + req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974 ; + assign MUX_cache_ram_word64_set$a_put_1__SEL_1 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_ram_word64_set$b_put_1__SEL_2 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 ; + assign MUX_cache_rg_error_during_refill$write_1__SEL_1 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_exc_code$write_1__SEL_1 = + EN_req && + NOT_req_f3_BITS_1_TO_0_44_EQ_0b0_45_46_AND_NOT_ETC___d965 ; + assign MUX_cache_rg_exc_code$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_exc_code$write_1__SEL_3 = + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_ld_val$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d381 ; + assign MUX_cache_rg_lrsc_valid$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d214 ; + assign MUX_cache_rg_state$write_1__SEL_4 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 ; + assign MUX_cache_rg_state$write_1__SEL_12 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + (cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d186 || + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d191 || + !cache_soc_map$m_is_mem_addr) ; + assign MUX_cache_rg_state$write_1__SEL_13 = + WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 ; + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36 or + cache_rg_addr or + cache_master_xactor_shim_rff_rv$port1__read or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37) + begin + case (cache_rg_f3) + 3'b0: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695; + 3'b001: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723; + 3'b010: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36; + 3'b011: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + (cache_rg_addr[2:0] == 3'h0) ? + cache_master_xactor_shim_rff_rv$port1__read[66:3] : + 64'd0; + 3'b100: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711; + 3'b101: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731; + 3'b110: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37; + 3'd7: MUX_cache_dw_output_ld_val$wset_1__VAL_1 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 or + w17928_BITS_31_TO_0__q53 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851) + begin + case (cache_rg_f3) + 3'b0: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805; + 3'b001: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833; + 3'b010: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + { {32{w17928_BITS_31_TO_0__q53[31]}}, + w17928_BITS_31_TO_0__q53 }; + 3'b011: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852; + 3'b100: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821; + 3'b101: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841; + 3'b110: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851; + 3'd7: MUX_cache_dw_output_ld_val$wset_1__VAL_2 = 64'd0; + endcase + end + assign MUX_cache_dw_output_ld_val$wset_1__VAL_3 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) ? + new_value__h8148 : + new_value__h18177 ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_1 = + { cache_rg_f3, cache_rg_pa, x__h27923 } ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_2 = + { cache_rg_f3, + cache_rg_addr, + IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d531 } ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_3 = + { cache_rg_f3, cache_rg_pa, cache_rg_st_amo_val } ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1 = + { 5'd16, + fabric_addr__h27309, + 8'd0, + size_val__h27412, + 18'd65536 } ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2 = + { 5'd16, cline_fabric_addr__h22383, 29'd7143424 } ; + assign MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1 = + { 3'd4, cache_rg_pa[31:12] } ; + assign MUX_cache_ram_word64_set$a_put_3__VAL_2 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 : + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 ; + assign MUX_cache_ram_word64_set$b_put_2__VAL_2 = + cache_rg_word64_set_in_cache + 9'd1 ; + assign MUX_cache_ram_word64_set$b_put_2__VAL_4 = + { cache_rg_addr[11:5], 2'd0 } ; + assign MUX_cache_rg_cset_in_cache$write_1__VAL_1 = + cache_rg_cset_in_cache + 7'd1 ; + assign MUX_cache_rg_exc_code$write_1__VAL_1 = + (req_op == 2'd0) ? 4'd4 : 4'd6 ; + assign MUX_cache_rg_exc_code$write_1__VAL_4 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) ? + 4'd5 : + 4'd7 ; + assign MUX_cache_rg_ld_val$write_1__VAL_2 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + x__h15829 : + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 ; + assign MUX_cache_rg_lrsc_valid$write_1__VAL_2 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 ; + assign MUX_cache_rg_st_amo_val$write_1__VAL_2 = + (cache_rg_f3 == 3'b010) ? + new_st_val__h19590 : + _theResult_____2__h19586 ; + assign MUX_cache_rg_state$write_1__VAL_1 = + NOT_req_f3_BITS_1_TO_0_44_EQ_0b0_45_46_AND_NOT_ETC___d965 ? + 4'd4 : + 4'd3 ; + assign MUX_cache_rg_state$write_1__VAL_2 = + (cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) ? + 4'd14 : + 4'd4 ; + assign MUX_cache_rg_state$write_1__VAL_4 = + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_rg_error_during_refill) ? + 4'd4 : + 4'd10 ; + assign MUX_cache_rg_state$write_1__VAL_12 = + cache_soc_map$m_is_mem_addr ? + IF_cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_ETC___d196 : + 4'd12 ; + + // inlined wires + assign cache_master_xactor_ug_master_u_b_putWire$wget = + { mem_master_bid, mem_master_bresp } ; + assign cache_master_xactor_ug_master_u_b_putWire$whas = + mem_master_bvalid && !cache_master_xactor_shim_bff_rv[6] ; + assign cache_master_xactor_ug_master_u_r_putWire$wget = + { mem_master_rid, + mem_master_rdata, + mem_master_rresp, + mem_master_rlast } ; + assign cache_master_xactor_ug_master_u_r_putWire$whas = + mem_master_rvalid && !cache_master_xactor_shim_rff_rv[71] ; + assign cache_dw_valid$whas = + (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp) && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d219 || + WILL_FIRE_RL_cache_rl_drive_exception_rsp || + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp || + WILL_FIRE_RL_cache_rl_ST_AMO_response ; + assign cache_master_xactor_ug_master_u_aw_dropWire$whas = + cache_master_xactor_shim_awff_rv$port1__read[97] && + mem_master_awready ; + assign cache_master_xactor_ug_master_u_w_dropWire$whas = + cache_master_xactor_shim_wff_rv$port1__read[73] && + mem_master_wready ; + assign cache_master_xactor_ug_master_u_ar_dropWire$whas = + cache_master_xactor_shim_arff_rv$port1__read[97] && + mem_master_arready ; + assign cache_master_xactor_shim_awff_rv$port0__write_1 = + { 5'd16, + mem_req_wr_addr_awaddr__h5054, + 8'd0, + _theResult___snd_snd_val__h5236, + 18'd65536 } ; + assign cache_master_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_master_xactor_shim_awff_rv$port0__write_1 : + cache_master_xactor_shim_awff_rv ; + assign cache_master_xactor_shim_awff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_awff_rv$port1__read ; + assign cache_master_xactor_shim_awff_rv$port3__read = + cache_master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_awff_rv$port2__read ; + assign cache_master_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, + mem_req_wr_data_wdata__h5352, + mem_req_wr_data_wstrb__h5353, + 1'd1 } ; + assign cache_master_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_master_xactor_shim_wff_rv$port0__write_1 : + cache_master_xactor_shim_wff_rv ; + assign cache_master_xactor_shim_wff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_wff_rv$port1__read ; + assign cache_master_xactor_shim_wff_rv$port3__read = + cache_master_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_wff_rv$port2__read ; + assign cache_master_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, cache_master_xactor_ug_master_u_b_putWire$wget } ; + assign cache_master_xactor_shim_bff_rv$port1__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut ? + cache_master_xactor_shim_bff_rv$port0__write_1 : + cache_master_xactor_shim_bff_rv ; + assign cache_master_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_cache_rl_discard_write_rsp ? + 7'd42 : + cache_master_xactor_shim_bff_rv$port1__read ; + assign cache_master_xactor_shim_bff_rv$port3__read = + cache_master_xactor_clearing ? + 7'd42 : + cache_master_xactor_shim_bff_rv$port2__read ; + assign cache_master_xactor_shim_arff_rv$EN_port0__write = + WILL_FIRE_RL_cache_rl_io_AMO_op_req || + WILL_FIRE_RL_cache_rl_io_read_req || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + assign cache_master_xactor_shim_arff_rv$port0__write_1 = + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1 : + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2 ; + assign cache_master_xactor_shim_arff_rv$port1__read = + cache_master_xactor_shim_arff_rv$EN_port0__write ? + cache_master_xactor_shim_arff_rv$port0__write_1 : + cache_master_xactor_shim_arff_rv ; + assign cache_master_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_arff_rv$port1__read ; + assign cache_master_xactor_shim_arff_rv$port3__read = + cache_master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_arff_rv$port2__read ; + assign cache_master_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, cache_master_xactor_ug_master_u_r_putWire$wget } ; + assign cache_master_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut ? + cache_master_xactor_shim_rff_rv$port0__write_1 : + cache_master_xactor_shim_rff_rv ; + assign cache_master_xactor_shim_rff_rv$EN_port1__write = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop ; + assign cache_master_xactor_shim_rff_rv$port2__read = + cache_master_xactor_shim_rff_rv$EN_port1__write ? + 72'h2AAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_rff_rv$port1__read ; + assign cache_master_xactor_shim_rff_rv$port3__read = + cache_master_xactor_clearing ? + 72'h2AAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_rff_rv$port2__read ; + assign cache_ctr_wr_rsps_pending_crg$port0__write_1 = + cache_ctr_wr_rsps_pending_crg + 4'd1 ; + assign cache_ctr_wr_rsps_pending_crg$port1__read = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_ctr_wr_rsps_pending_crg$port0__write_1 : + cache_ctr_wr_rsps_pending_crg ; + assign cache_ctr_wr_rsps_pending_crg$port1__write_1 = b__h22284 - 4'd1 ; + assign cache_ctr_wr_rsps_pending_crg$port2__read = + CAN_FIRE_RL_cache_rl_discard_write_rsp ? + cache_ctr_wr_rsps_pending_crg$port1__write_1 : + cache_ctr_wr_rsps_pending_crg$port1__read ; + assign cache_ctr_wr_rsps_pending_crg$port3__read = + MUX_cache_master_xactor_clearing$write_1__SEL_2 ? + 4'd0 : + cache_ctr_wr_rsps_pending_crg$port2__read ; + assign cache_crg_sb_to_load_delay$port0__write_1 = + { 1'd0, cache_crg_sb_to_load_delay[10:1] } ; + assign cache_crg_sb_to_load_delay$EN_port1__write = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d524 ; + assign cache_crg_sb_to_load_delay$port2__read = + cache_crg_sb_to_load_delay$EN_port1__write ? + 11'd2047 : + cache_crg_sb_to_load_delay$port0__write_1 ; + + // register cache_cfg_verbosity + assign cache_cfg_verbosity$D_IN = set_verbosity_verbosity ; + assign cache_cfg_verbosity$EN = EN_set_verbosity ; + + // register cache_crg_sb_to_load_delay + assign cache_crg_sb_to_load_delay$D_IN = + cache_crg_sb_to_load_delay$port2__read ; + assign cache_crg_sb_to_load_delay$EN = 1'b1 ; + + // register cache_ctr_wr_rsps_pending_crg + assign cache_ctr_wr_rsps_pending_crg$D_IN = + cache_ctr_wr_rsps_pending_crg$port3__read ; + assign cache_ctr_wr_rsps_pending_crg$EN = 1'b1 ; + + // register cache_master_xactor_clearing + assign cache_master_xactor_clearing$D_IN = !cache_master_xactor_clearing ; + assign cache_master_xactor_clearing$EN = + WILL_FIRE_RL_cache_rl_start_reset && !cache_f_reset_reqs$D_OUT || + cache_master_xactor_clearing ; + + // register cache_master_xactor_shim_arff_rv + assign cache_master_xactor_shim_arff_rv$D_IN = + cache_master_xactor_shim_arff_rv$port3__read ; + assign cache_master_xactor_shim_arff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_awff_rv + assign cache_master_xactor_shim_awff_rv$D_IN = + cache_master_xactor_shim_awff_rv$port3__read ; + assign cache_master_xactor_shim_awff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_bff_rv + assign cache_master_xactor_shim_bff_rv$D_IN = + cache_master_xactor_shim_bff_rv$port3__read ; + assign cache_master_xactor_shim_bff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_rff_rv + assign cache_master_xactor_shim_rff_rv$D_IN = + cache_master_xactor_shim_rff_rv$port3__read ; + assign cache_master_xactor_shim_rff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_wff_rv + assign cache_master_xactor_shim_wff_rv$D_IN = + cache_master_xactor_shim_wff_rv$port3__read ; + assign cache_master_xactor_shim_wff_rv$EN = 1'b1 ; + + // register cache_rg_addr + assign cache_rg_addr$D_IN = req_addr ; + assign cache_rg_addr$EN = EN_req ; + + // register cache_rg_amo_funct7 + assign cache_rg_amo_funct7$D_IN = req_amo_funct7 ; + assign cache_rg_amo_funct7$EN = EN_req ; + + // register cache_rg_cset_in_cache + assign cache_rg_cset_in_cache$D_IN = + WILL_FIRE_RL_cache_rl_reset ? + MUX_cache_rg_cset_in_cache$write_1__VAL_1 : + 7'd0 ; + assign cache_rg_cset_in_cache$EN = + WILL_FIRE_RL_cache_rl_reset || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_error_during_refill + assign cache_rg_error_during_refill$D_IN = + MUX_cache_rg_error_during_refill$write_1__SEL_1 ; + assign cache_rg_error_during_refill$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // register cache_rg_exc_code + always@(MUX_cache_rg_exc_code$write_1__SEL_1 or + MUX_cache_rg_exc_code$write_1__VAL_1 or + MUX_cache_rg_exc_code$write_1__SEL_2 or + MUX_cache_rg_exc_code$write_1__SEL_3 or + MUX_cache_rg_error_during_refill$write_1__SEL_1 or + MUX_cache_rg_exc_code$write_1__VAL_4) + case (1'b1) + MUX_cache_rg_exc_code$write_1__SEL_1: + cache_rg_exc_code$D_IN = MUX_cache_rg_exc_code$write_1__VAL_1; + MUX_cache_rg_exc_code$write_1__SEL_2: cache_rg_exc_code$D_IN = 4'd7; + MUX_cache_rg_exc_code$write_1__SEL_3: cache_rg_exc_code$D_IN = 4'd5; + MUX_cache_rg_error_during_refill$write_1__SEL_1: + cache_rg_exc_code$D_IN = MUX_cache_rg_exc_code$write_1__VAL_4; + default: cache_rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; + endcase + assign cache_rg_exc_code$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + EN_req && + NOT_req_f3_BITS_1_TO_0_44_EQ_0b0_45_46_AND_NOT_ETC___d965 ; + + // register cache_rg_f3 + assign cache_rg_f3$D_IN = req_f3 ; + assign cache_rg_f3$EN = EN_req ; + + // register cache_rg_ld_val + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + MUX_cache_dw_output_ld_val$wset_1__VAL_2 or + MUX_cache_rg_ld_val$write_1__SEL_2 or + MUX_cache_rg_ld_val$write_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_read_rsp or + MUX_cache_dw_output_ld_val$wset_1__VAL_1 or + WILL_FIRE_RL_cache_rl_io_AMO_SC_req) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_2: + cache_rg_ld_val$D_IN = MUX_cache_dw_output_ld_val$wset_1__VAL_2; + MUX_cache_rg_ld_val$write_1__SEL_2: + cache_rg_ld_val$D_IN = MUX_cache_rg_ld_val$write_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_read_rsp: + cache_rg_ld_val$D_IN = MUX_cache_dw_output_ld_val$wset_1__VAL_1; + WILL_FIRE_RL_cache_rl_io_AMO_SC_req: cache_rg_ld_val$D_IN = 64'd1; + default: cache_rg_ld_val$D_IN = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_rg_ld_val$EN = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d381 || + WILL_FIRE_RL_cache_rl_io_read_rsp || + WILL_FIRE_RL_cache_rl_io_AMO_SC_req ; + + // register cache_rg_lower_word32 + assign cache_rg_lower_word32$D_IN = 32'h0 ; + assign cache_rg_lower_word32$EN = 1'b0 ; + + // register cache_rg_lower_word32_full + assign cache_rg_lower_word32_full$D_IN = 1'd0 ; + assign cache_rg_lower_word32_full$EN = + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_lrsc_pa + assign cache_rg_lrsc_pa$D_IN = cache_rg_addr ; + assign cache_rg_lrsc_pa$EN = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 ; + + // register cache_rg_lrsc_valid + assign cache_rg_lrsc_valid$D_IN = + MUX_cache_rg_lrsc_valid$write_1__SEL_2 && + MUX_cache_rg_lrsc_valid$write_1__VAL_2 ; + assign cache_rg_lrsc_valid$EN = + WILL_FIRE_RL_cache_rl_io_read_req && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d214 || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_op + assign cache_rg_op$D_IN = req_op ; + assign cache_rg_op$EN = EN_req ; + + // register cache_rg_pa + assign cache_rg_pa$D_IN = EN_req ? req_addr : cache_rg_addr ; + assign cache_rg_pa$EN = + EN_req || WILL_FIRE_RL_cache_rl_probe_and_immed_rsp ; + + // register cache_rg_pte_pa + assign cache_rg_pte_pa$D_IN = 32'h0 ; + assign cache_rg_pte_pa$EN = 1'b0 ; + + // register cache_rg_st_amo_val + assign cache_rg_st_amo_val$D_IN = + EN_req ? req_st_value : MUX_cache_rg_st_amo_val$write_1__VAL_2 ; + assign cache_rg_st_amo_val$EN = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d576 || + EN_req ; + + // register cache_rg_state + always@(EN_req or + MUX_cache_rg_state$write_1__VAL_1 or + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp or + MUX_cache_rg_state$write_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_read_rsp or + MUX_cache_rg_state$write_1__SEL_4 or + MUX_cache_rg_state$write_1__VAL_4 or + WILL_FIRE_RL_cache_rl_start_reset or + WILL_FIRE_RL_cache_rl_io_AMO_op_req or + WILL_FIRE_RL_cache_rl_io_AMO_SC_req or + WILL_FIRE_RL_cache_rl_io_write_req or + WILL_FIRE_RL_cache_rl_io_read_req or + WILL_FIRE_RL_cache_rl_rereq or + WILL_FIRE_RL_cache_rl_start_cache_refill or + MUX_cache_rg_state$write_1__SEL_12 or + MUX_cache_rg_state$write_1__VAL_12 or + MUX_cache_rg_state$write_1__SEL_13) + case (1'b1) + EN_req: cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_1; + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_read_rsp: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_2; + MUX_cache_rg_state$write_1__SEL_4: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_4; + WILL_FIRE_RL_cache_rl_start_reset: cache_rg_state$D_IN = 4'd1; + WILL_FIRE_RL_cache_rl_io_AMO_op_req: cache_rg_state$D_IN = 4'd15; + WILL_FIRE_RL_cache_rl_io_AMO_SC_req || WILL_FIRE_RL_cache_rl_io_write_req: + cache_rg_state$D_IN = 4'd11; + WILL_FIRE_RL_cache_rl_io_read_req: cache_rg_state$D_IN = 4'd13; + WILL_FIRE_RL_cache_rl_rereq: cache_rg_state$D_IN = 4'd3; + WILL_FIRE_RL_cache_rl_start_cache_refill: cache_rg_state$D_IN = 4'd9; + MUX_cache_rg_state$write_1__SEL_12: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_12; + MUX_cache_rg_state$write_1__SEL_13: cache_rg_state$D_IN = 4'd2; + default: cache_rg_state$D_IN = 4'b1010 /* unspecified value */ ; + endcase + assign cache_rg_state$EN = + WILL_FIRE_RL_cache_rl_reset && + cache_rg_cset_in_cache == 7'd127 || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + (cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d186 || + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d191 || + !cache_soc_map$m_is_mem_addr) || + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp || + EN_req || + WILL_FIRE_RL_cache_rl_start_reset || + WILL_FIRE_RL_cache_rl_rereq || + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_io_AMO_SC_req || + WILL_FIRE_RL_cache_rl_io_write_req || + WILL_FIRE_RL_cache_rl_io_read_req || + WILL_FIRE_RL_cache_rl_io_AMO_op_req ; + + // register cache_rg_word64_set_in_cache + assign cache_rg_word64_set_in_cache$D_IN = + MUX_cache_ram_word64_set$b_put_1__SEL_2 ? + MUX_cache_ram_word64_set$b_put_2__VAL_2 : + MUX_cache_ram_word64_set$b_put_2__VAL_4 ; + assign cache_rg_word64_set_in_cache$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // submodule cache_f_fabric_write_reqs + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_1 or + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2 or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_write_req or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_2: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_1; + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_write_req: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3; + default: cache_f_fabric_write_reqs$D_IN = + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_f_fabric_write_reqs$ENQ = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d529 || + WILL_FIRE_RL_cache_rl_io_write_req ; + assign cache_f_fabric_write_reqs$DEQ = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ; + assign cache_f_fabric_write_reqs$CLR = 1'b0 ; + + // submodule cache_f_reset_reqs + assign cache_f_reset_reqs$D_IN = !EN_server_reset_request_put ; + assign cache_f_reset_reqs$ENQ = + EN_server_reset_request_put || EN_server_flush_request_put ; + assign cache_f_reset_reqs$DEQ = MUX_cache_rg_state$write_1__SEL_13 ; + assign cache_f_reset_reqs$CLR = 1'b0 ; + + // submodule cache_f_reset_rsps + assign cache_f_reset_rsps$D_IN = cache_f_reset_reqs$D_OUT ; + assign cache_f_reset_rsps$ENQ = MUX_cache_rg_state$write_1__SEL_13 ; + assign cache_f_reset_rsps$DEQ = + EN_server_flush_response_get || EN_server_reset_response_get ; + assign cache_f_reset_rsps$CLR = 1'b0 ; + + // submodule cache_ram_state_and_ctag_cset + assign cache_ram_state_and_ctag_cset$ADDRA = + WILL_FIRE_RL_cache_rl_start_cache_refill ? + cache_rg_addr[11:5] : + cache_rg_cset_in_cache ; + assign cache_ram_state_and_ctag_cset$ADDRB = + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 ? + req_addr[11:5] : + cache_rg_addr[11:5] ; + assign cache_ram_state_and_ctag_cset$DIA = + WILL_FIRE_RL_cache_rl_start_cache_refill ? + MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1 : + 23'd2796202 ; + assign cache_ram_state_and_ctag_cset$DIB = + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 ? + 23'b01010101010101010101010 /* unspecified value */ : + 23'b01010101010101010101010 /* unspecified value */ ; + assign cache_ram_state_and_ctag_cset$WEA = 1'd1 ; + assign cache_ram_state_and_ctag_cset$WEB = 1'd0 ; + assign cache_ram_state_and_ctag_cset$ENA = + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_reset ; + assign cache_ram_state_and_ctag_cset$ENB = + EN_req && + req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974 || + WILL_FIRE_RL_cache_rl_rereq ; + + // submodule cache_ram_word64_set + assign cache_ram_word64_set$ADDRA = + MUX_cache_ram_word64_set$a_put_1__SEL_1 ? + cache_rg_word64_set_in_cache : + cache_rg_addr[11:3] ; + always@(MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 or + req_addr or + MUX_cache_ram_word64_set$b_put_1__SEL_2 or + MUX_cache_ram_word64_set$b_put_2__VAL_2 or + WILL_FIRE_RL_cache_rl_rereq or + cache_rg_addr or + WILL_FIRE_RL_cache_rl_start_cache_refill or + MUX_cache_ram_word64_set$b_put_2__VAL_4) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1: + cache_ram_word64_set$ADDRB = req_addr[11:3]; + MUX_cache_ram_word64_set$b_put_1__SEL_2: + cache_ram_word64_set$ADDRB = + MUX_cache_ram_word64_set$b_put_2__VAL_2; + WILL_FIRE_RL_cache_rl_rereq: + cache_ram_word64_set$ADDRB = cache_rg_addr[11:3]; + WILL_FIRE_RL_cache_rl_start_cache_refill: + cache_ram_word64_set$ADDRB = + MUX_cache_ram_word64_set$b_put_2__VAL_4; + default: cache_ram_word64_set$ADDRB = + 9'b010101010 /* unspecified value */ ; + endcase + end + assign cache_ram_word64_set$DIA = + MUX_cache_ram_word64_set$a_put_1__SEL_1 ? + cache_master_xactor_shim_rff_rv$port1__read[66:3] : + MUX_cache_ram_word64_set$a_put_3__VAL_2 ; + always@(MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 or + MUX_cache_ram_word64_set$b_put_1__SEL_2 or + WILL_FIRE_RL_cache_rl_rereq or + WILL_FIRE_RL_cache_rl_start_cache_refill) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_cache_ram_word64_set$b_put_1__SEL_2: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + WILL_FIRE_RL_cache_rl_rereq: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + WILL_FIRE_RL_cache_rl_start_cache_refill: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + default: cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_ram_word64_set$WEA = 1'd1 ; + assign cache_ram_word64_set$WEB = 1'd0 ; + assign cache_ram_word64_set$ENA = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d392 ; + assign cache_ram_word64_set$ENB = + EN_req && + req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974 || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 || + WILL_FIRE_RL_cache_rl_rereq || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // submodule cache_soc_map + assign cache_soc_map$m_is_IO_addr_addr = 64'h0 ; + assign cache_soc_map$m_is_mem_addr_addr = { 32'd0, cache_rg_addr } ; + assign cache_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; + + // remaining internal signals + assign IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340 = + (cache_rg_addr[2:0] == 3'h0) ? word64__h7969 : 64'd0 ; + assign IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d354 = + (cache_rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; + assign IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852 = + (cache_rg_addr[2:0] == 3'h0) ? ld_val__h25642 : 64'd0 ; + assign IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 = + (cache_rg_f3 == 3'b010) ? + { {32{cache_rg_st_amo_val_BITS_31_TO_0__q33[31]}}, + cache_rg_st_amo_val_BITS_31_TO_0__q33 } : + cache_rg_st_amo_val ; + assign IF_cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_ETC___d196 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) ? + 4'd8 : + IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d195 ; + assign IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d164 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15819 || + cache_f_fabric_write_reqs$FULL_N : + !cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 || + cache_f_fabric_write_reqs$FULL_N ; + assign IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d195 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + 4'd11 : + ((!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) ? + 4'd8 : + 4'd11) ; + assign IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d531 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + cache_rg_st_amo_val : + new_st_val__h19308 ; + assign NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 = + cache_cfg_verbosity > 4'd1 ; + assign NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 = + cache_cfg_verbosity > 4'd2 ; + assign NOT_cache_ram_state_and_ctag_cset_b_read__54_B_ETC___d202 = + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 ; + assign NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d191 = + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) ; + assign NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d529 = + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d527 || + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d389) ; + assign NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d547 ; + assign NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d557 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d555 ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d211 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d389 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d523 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + (cache_rg_f3 == 3'b0 || cache_rg_f3 == 3'b001) ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d565 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d568 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d572 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d387 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 ; + assign NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d521 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + (cache_rg_f3 == 3'b0 || cache_rg_f3 == 3'b001) ; + assign NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d547 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d551 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d555 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_req_f3_BITS_1_TO_0_44_EQ_0b0_45_46_AND_NOT_ETC___d965 = + req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && + (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && + (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; + assign _theResult___fst__h5221 = + cache_f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h5069 ; + assign access_exc_code__h4779 = MUX_cache_rg_exc_code$write_1__VAL_4 ; + assign b__h22284 = cache_ctr_wr_rsps_pending_crg$port1__read ; + assign cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35 = + cache_master_xactor_shim_arff_rv$port1__read[96:0] ; + assign cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1 = + cache_master_xactor_shim_awff_rv$port1__read[96:0] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q10 = + cache_master_xactor_shim_rff_rv$port1__read[50:35] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q11 = + cache_master_xactor_shim_rff_rv$port1__read[66:35] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q12 = + cache_master_xactor_shim_rff_rv$port1__read[50:43] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q13 = + cache_master_xactor_shim_rff_rv$port1__read[58:51] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q14 = + cache_master_xactor_shim_rff_rv$port1__read[66:51] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q15 = + cache_master_xactor_shim_rff_rv$port1__read[66:59] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q2 = + cache_master_xactor_shim_rff_rv$port1__read[10:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q3 = + cache_master_xactor_shim_rff_rv$port1__read[18:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q4 = + cache_master_xactor_shim_rff_rv$port1__read[34:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q5 = + cache_master_xactor_shim_rff_rv$port1__read[18:11] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q6 = + cache_master_xactor_shim_rff_rv$port1__read[26:19] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q7 = + cache_master_xactor_shim_rff_rv$port1__read[34:19] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q8 = + cache_master_xactor_shim_rff_rv$port1__read[34:27] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q9 = + cache_master_xactor_shim_rff_rv$port1__read[42:35] ; + assign cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q16 = + cache_master_xactor_shim_wff_rv$port1__read[72:0] ; + assign cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 = + cache_ram_state_and_ctag_cset$DOB[21:0] == pa_ctag__h7827 ; + assign cache_ram_state_and_ctag_cset_b_read__54_BIT_2_ETC___d203 = + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 || + NOT_cache_ram_state_and_ctag_cset_b_read__54_B_ETC___d202 ; + assign cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 = + cache_rg_addr == cache_rg_lrsc_pa ; + assign cache_rg_amo_funct7_36_BITS_6_TO_2_37_EQ_0b10__ETC___d375 = + cache_rg_amo_funct7[6:2] == 5'b00010 && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148 = + cache_rg_lrsc_pa == cache_rg_addr ; + assign cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d186 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) ; + assign cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d214 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset_b_read__54_BIT_2_ETC___d203 || + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d212 ; + assign cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d219 = + MUX_cache_rg_lrsc_valid$write_1__VAL_2 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15819 ; + assign cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d358 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d371 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d212 = + cache_rg_op == 2'd1 && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 || + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d211 ; + assign cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d390 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d387 || + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d389 ; + assign cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d524 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d521 || + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d523 ; + assign cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d527 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) ; + assign cache_rg_op_33_EQ_2_35_AND_cache_rg_amo_funct7_ETC___d561 = + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15819 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_st_amo_val_BITS_31_TO_0__q33 = cache_rg_st_amo_val[31:0] ; + assign cache_rg_state_7_EQ_12_46_AND_cache_rg_op_33_E_ETC___d648 = + cache_rg_state == 4'd12 && + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + b__h22284 == 4'd0 ; + assign cache_rg_state_7_EQ_3_67_AND_NOT_cache_rg_op_3_ETC___d176 = + cache_rg_state == 4'd3 && + (cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) || + cache_crg_sb_to_load_delay$port0__write_1 == 11'd0) ; + assign cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d381 = + cache_soc_map$m_is_mem_addr && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 || + cache_rg_op != 2'd1 && cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) ; + assign cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d392 = + cache_soc_map$m_is_mem_addr && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d390 ; + assign cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570 = + cache_soc_map$m_is_mem_addr && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d568 ; + assign cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d576 = + cache_soc_map$m_is_mem_addr && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d389 ; + assign cline_addr__h22382 = { cache_rg_pa[31:5], 5'd0 } ; + assign cline_fabric_addr__h22383 = { 32'd0, cline_addr__h22382 } ; + assign fabric_addr__h27309 = { 32'd0, cache_rg_pa } ; + assign ld_val5642_BITS_15_TO_0__q39 = ld_val__h25642[15:0] ; + assign ld_val5642_BITS_15_TO_8__q41 = ld_val__h25642[15:8] ; + assign ld_val5642_BITS_23_TO_16__q42 = ld_val__h25642[23:16] ; + assign ld_val5642_BITS_31_TO_0__q40 = ld_val__h25642[31:0] ; + assign ld_val5642_BITS_31_TO_16__q43 = ld_val__h25642[31:16] ; + assign ld_val5642_BITS_31_TO_24__q44 = ld_val__h25642[31:24] ; + assign ld_val5642_BITS_39_TO_32__q45 = ld_val__h25642[39:32] ; + assign ld_val5642_BITS_47_TO_32__q46 = ld_val__h25642[47:32] ; + assign ld_val5642_BITS_47_TO_40__q48 = ld_val__h25642[47:40] ; + assign ld_val5642_BITS_55_TO_48__q49 = ld_val__h25642[55:48] ; + assign ld_val5642_BITS_63_TO_32__q47 = ld_val__h25642[63:32] ; + assign ld_val5642_BITS_63_TO_48__q50 = ld_val__h25642[63:48] ; + assign ld_val5642_BITS_63_TO_56__q51 = ld_val__h25642[63:56] ; + assign ld_val5642_BITS_7_TO_0__q38 = ld_val__h25642[7:0] ; + assign ld_val__h25642 = MUX_cache_dw_output_ld_val$wset_1__VAL_1 ; + assign lrsc_result__h15819 = + !cache_rg_lrsc_valid || + !cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148 ; + assign mem_req_wr_addr_awaddr__h5054 = + { 32'd0, cache_f_fabric_write_reqs$D_OUT[95:64] } ; + assign new_ld_val__h27894 = MUX_cache_dw_output_ld_val$wset_1__VAL_2 ; + assign new_st_val__h19308 = MUX_cache_rg_st_amo_val$write_1__VAL_2 ; + assign new_st_val__h19590 = { 32'd0, _theResult_____2__h19586[31:0] } ; + assign new_st_val__h19681 = + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 + + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ; + assign new_st_val__h20661 = w1__h19578 ^ w2__h27934 ; + assign new_st_val__h20665 = w1__h19578 & w2__h27934 ; + assign new_st_val__h20669 = w1__h19578 | w2__h27934 ; + assign new_st_val__h20673 = + (w1__h19578 < w2__h27934) ? w1__h19578 : w2__h27934 ; + assign new_st_val__h20678 = + (w1__h19578 <= w2__h27934) ? w2__h27934 : w1__h19578 ; + assign new_st_val__h20684 = + ((IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 ^ + 64'h8000000000000000) < + (IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ^ + 64'h8000000000000000)) ? + w1__h19578 : + w2__h27934 ; + assign new_st_val__h20689 = + ((IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 ^ + 64'h8000000000000000) <= + (IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ^ + 64'h8000000000000000)) ? + w2__h27934 : + w1__h19578 ; + assign new_st_val__h27944 = { 32'd0, _theResult_____2__h27940[31:0] } ; + assign new_st_val__h28035 = + new_ld_val__h27894 + + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ; + assign new_st_val__h29895 = w1__h27932 ^ w2__h27934 ; + assign new_st_val__h29899 = w1__h27932 & w2__h27934 ; + assign new_st_val__h29903 = w1__h27932 | w2__h27934 ; + assign new_st_val__h29907 = + (w1__h27932 < w2__h27934) ? w1__h27932 : w2__h27934 ; + assign new_st_val__h29912 = + (w1__h27932 <= w2__h27934) ? w2__h27934 : w1__h27932 ; + assign new_st_val__h29918 = + ((new_ld_val__h27894 ^ 64'h8000000000000000) < + (IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ^ + 64'h8000000000000000)) ? + w1__h27932 : + w2__h27934 ; + assign new_st_val__h29923 = + ((new_ld_val__h27894 ^ 64'h8000000000000000) <= + (IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ^ + 64'h8000000000000000)) ? + w2__h27934 : + w1__h27932 ; + assign new_value148_BITS_31_TO_0__q32 = new_value__h8148[31:0] ; + assign pa_ctag__h7827 = { 2'd0, cache_rg_addr[31:12] } ; + assign req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974 = + req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || + req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || + req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; + assign result__h14559 = + { {56{word64969_BITS_15_TO_8__q20[7]}}, + word64969_BITS_15_TO_8__q20 } ; + assign result__h14587 = + { {56{word64969_BITS_23_TO_16__q21[7]}}, + word64969_BITS_23_TO_16__q21 } ; + assign result__h14615 = + { {56{word64969_BITS_31_TO_24__q23[7]}}, + word64969_BITS_31_TO_24__q23 } ; + assign result__h14643 = + { {56{word64969_BITS_39_TO_32__q24[7]}}, + word64969_BITS_39_TO_32__q24 } ; + assign result__h14671 = + { {56{word64969_BITS_47_TO_40__q27[7]}}, + word64969_BITS_47_TO_40__q27 } ; + assign result__h14699 = + { {56{word64969_BITS_55_TO_48__q28[7]}}, + word64969_BITS_55_TO_48__q28 } ; + assign result__h14727 = + { {56{word64969_BITS_63_TO_56__q30[7]}}, + word64969_BITS_63_TO_56__q30 } ; + assign result__h14772 = { 56'd0, word64__h7969[7:0] } ; + assign result__h14800 = { 56'd0, word64__h7969[15:8] } ; + assign result__h14828 = { 56'd0, word64__h7969[23:16] } ; + assign result__h14856 = { 56'd0, word64__h7969[31:24] } ; + assign result__h14884 = { 56'd0, word64__h7969[39:32] } ; + assign result__h14912 = { 56'd0, word64__h7969[47:40] } ; + assign result__h14940 = { 56'd0, word64__h7969[55:48] } ; + assign result__h14968 = { 56'd0, word64__h7969[63:56] } ; + assign result__h15013 = + { {48{word64969_BITS_15_TO_0__q18[15]}}, + word64969_BITS_15_TO_0__q18 } ; + assign result__h15041 = + { {48{word64969_BITS_31_TO_16__q22[15]}}, + word64969_BITS_31_TO_16__q22 } ; + assign result__h15069 = + { {48{word64969_BITS_47_TO_32__q25[15]}}, + word64969_BITS_47_TO_32__q25 } ; + assign result__h15097 = + { {48{word64969_BITS_63_TO_48__q29[15]}}, + word64969_BITS_63_TO_48__q29 } ; + assign result__h15138 = { 48'd0, word64__h7969[15:0] } ; + assign result__h15166 = { 48'd0, word64__h7969[31:16] } ; + assign result__h15194 = { 48'd0, word64__h7969[47:32] } ; + assign result__h15222 = { 48'd0, word64__h7969[63:48] } ; + assign result__h15263 = + { {32{word64969_BITS_31_TO_0__q19[31]}}, + word64969_BITS_31_TO_0__q19 } ; + assign result__h15291 = + { {32{word64969_BITS_63_TO_32__q26[31]}}, + word64969_BITS_63_TO_32__q26 } ; + assign result__h15330 = { 32'd0, word64__h7969[31:0] } ; + assign result__h15358 = { 32'd0, word64__h7969[63:32] } ; + assign result__h25702 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q2[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q2 } ; + assign result__h25732 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q5[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q5 } ; + assign result__h25759 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q6[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q6 } ; + assign result__h25786 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q8[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q8 } ; + assign result__h25813 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q9[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q9 } ; + assign result__h25840 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q12[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q12 } ; + assign result__h25867 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q13[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q13 } ; + assign result__h25894 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q15[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q15 } ; + assign result__h25938 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[10:3] } ; + assign result__h25965 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[18:11] } ; + assign result__h25992 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[26:19] } ; + assign result__h26019 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[34:27] } ; + assign result__h26046 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[42:35] } ; + assign result__h26073 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[50:43] } ; + assign result__h26100 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[58:51] } ; + assign result__h26127 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[66:59] } ; + assign result__h26171 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q3[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q3 } ; + assign result__h26198 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q7[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q7 } ; + assign result__h26225 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q10[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q10 } ; + assign result__h26252 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q14[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q14 } ; + assign result__h26292 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[18:3] } ; + assign result__h26319 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[34:19] } ; + assign result__h26346 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[50:35] } ; + assign result__h26373 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[66:51] } ; + assign result__h26413 = + { {32{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q4[31]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q4 } ; + assign result__h26440 = + { {32{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q11[31]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q11 } ; + assign result__h26478 = + { 32'd0, cache_master_xactor_shim_rff_rv$port1__read[34:3] } ; + assign result__h26505 = + { 32'd0, cache_master_xactor_shim_rff_rv$port1__read[66:35] } ; + assign result__h28123 = + { {56{ld_val5642_BITS_7_TO_0__q38[7]}}, + ld_val5642_BITS_7_TO_0__q38 } ; + assign result__h29031 = + { {56{ld_val5642_BITS_15_TO_8__q41[7]}}, + ld_val5642_BITS_15_TO_8__q41 } ; + assign result__h29059 = + { {56{ld_val5642_BITS_23_TO_16__q42[7]}}, + ld_val5642_BITS_23_TO_16__q42 } ; + assign result__h29087 = + { {56{ld_val5642_BITS_31_TO_24__q44[7]}}, + ld_val5642_BITS_31_TO_24__q44 } ; + assign result__h29115 = + { {56{ld_val5642_BITS_39_TO_32__q45[7]}}, + ld_val5642_BITS_39_TO_32__q45 } ; + assign result__h29143 = + { {56{ld_val5642_BITS_47_TO_40__q48[7]}}, + ld_val5642_BITS_47_TO_40__q48 } ; + assign result__h29171 = + { {56{ld_val5642_BITS_55_TO_48__q49[7]}}, + ld_val5642_BITS_55_TO_48__q49 } ; + assign result__h29199 = + { {56{ld_val5642_BITS_63_TO_56__q51[7]}}, + ld_val5642_BITS_63_TO_56__q51 } ; + assign result__h29244 = { 56'd0, ld_val__h25642[7:0] } ; + assign result__h29272 = { 56'd0, ld_val__h25642[15:8] } ; + assign result__h29300 = { 56'd0, ld_val__h25642[23:16] } ; + assign result__h29328 = { 56'd0, ld_val__h25642[31:24] } ; + assign result__h29356 = { 56'd0, ld_val__h25642[39:32] } ; + assign result__h29384 = { 56'd0, ld_val__h25642[47:40] } ; + assign result__h29412 = { 56'd0, ld_val__h25642[55:48] } ; + assign result__h29440 = { 56'd0, ld_val__h25642[63:56] } ; + assign result__h29485 = + { {48{ld_val5642_BITS_15_TO_0__q39[15]}}, + ld_val5642_BITS_15_TO_0__q39 } ; + assign result__h29513 = + { {48{ld_val5642_BITS_31_TO_16__q43[15]}}, + ld_val5642_BITS_31_TO_16__q43 } ; + assign result__h29541 = + { {48{ld_val5642_BITS_47_TO_32__q46[15]}}, + ld_val5642_BITS_47_TO_32__q46 } ; + assign result__h29569 = + { {48{ld_val5642_BITS_63_TO_48__q50[15]}}, + ld_val5642_BITS_63_TO_48__q50 } ; + assign result__h29610 = { 48'd0, ld_val__h25642[15:0] } ; + assign result__h29638 = { 48'd0, ld_val__h25642[31:16] } ; + assign result__h29666 = { 48'd0, ld_val__h25642[47:32] } ; + assign result__h29694 = { 48'd0, ld_val__h25642[63:48] } ; + assign result__h29735 = + { {32{ld_val5642_BITS_31_TO_0__q40[31]}}, + ld_val5642_BITS_31_TO_0__q40 } ; + assign result__h29763 = + { {32{ld_val5642_BITS_63_TO_32__q47[31]}}, + ld_val5642_BITS_63_TO_32__q47 } ; + assign result__h29802 = { 32'd0, ld_val__h25642[31:0] } ; + assign result__h29830 = { 32'd0, ld_val__h25642[63:32] } ; + assign result__h8203 = + { {56{word64969_BITS_7_TO_0__q17[7]}}, + word64969_BITS_7_TO_0__q17 } ; + assign shift_bits__h5069 = + { cache_f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ; + assign strobe64__h5219 = + 8'b00000001 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign strobe64__h5223 = + 8'b00000011 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign strobe64__h5227 = + 8'b00001111 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign w17928_BITS_31_TO_0__q53 = w1__h27928[31:0] ; + assign w1___1__h19649 = { 32'd0, new_value__h8148[31:0] } ; + assign w1___1__h28003 = { 32'd0, w1__h27928[31:0] } ; + assign w2___1__h28004 = { 32'd0, cache_rg_st_amo_val[31:0] } ; + assign w2__h27934 = + (cache_rg_f3 == 3'b010) ? w2___1__h28004 : cache_rg_st_amo_val ; + assign word64969_BITS_15_TO_0__q18 = word64__h7969[15:0] ; + assign word64969_BITS_15_TO_8__q20 = word64__h7969[15:8] ; + assign word64969_BITS_23_TO_16__q21 = word64__h7969[23:16] ; + assign word64969_BITS_31_TO_0__q19 = word64__h7969[31:0] ; + assign word64969_BITS_31_TO_16__q22 = word64__h7969[31:16] ; + assign word64969_BITS_31_TO_24__q23 = word64__h7969[31:24] ; + assign word64969_BITS_39_TO_32__q24 = word64__h7969[39:32] ; + assign word64969_BITS_47_TO_32__q25 = word64__h7969[47:32] ; + assign word64969_BITS_47_TO_40__q27 = word64__h7969[47:40] ; + assign word64969_BITS_55_TO_48__q28 = word64__h7969[55:48] ; + assign word64969_BITS_63_TO_32__q26 = word64__h7969[63:32] ; + assign word64969_BITS_63_TO_48__q29 = word64__h7969[63:48] ; + assign word64969_BITS_63_TO_56__q30 = word64__h7969[63:56] ; + assign word64969_BITS_7_TO_0__q17 = word64__h7969[7:0] ; + assign word64__h7969 = cache_ram_word64_set$DOB & y__h8239 ; + assign x__h15829 = { 63'd0, lrsc_result__h15819 } ; + assign x__h27923 = + (cache_rg_f3 == 3'b010) ? + new_st_val__h27944 : + _theResult_____2__h27940 ; + assign y__h8239 = + {64{cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160}} ; + always@(cache_f_fabric_write_reqs$D_OUT) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0: _theResult___snd_snd_val__h5236 = 3'b0; + 2'b01: _theResult___snd_snd_val__h5236 = 3'b001; + 2'b10: _theResult___snd_snd_val__h5236 = 3'b010; + 2'b11: _theResult___snd_snd_val__h5236 = 3'b011; + endcase + end + always@(cache_rg_f3) + begin + case (cache_rg_f3[1:0]) + 2'b0: size_val__h27412 = 3'b0; + 2'b01: size_val__h27412 = 3'b001; + 2'b10: size_val__h27412 = 3'b010; + 2'd3: size_val__h27412 = 3'b011; + endcase + end + always@(cache_f_fabric_write_reqs$D_OUT or + strobe64__h5219 or strobe64__h5223 or strobe64__h5227) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0: mem_req_wr_data_wstrb__h5353 = strobe64__h5219; + 2'b01: mem_req_wr_data_wstrb__h5353 = strobe64__h5223; + 2'b10: mem_req_wr_data_wstrb__h5353 = strobe64__h5227; + 2'b11: mem_req_wr_data_wstrb__h5353 = 8'b11111111; + endcase + end + always@(cache_f_fabric_write_reqs$D_OUT or _theResult___fst__h5221) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0, 2'b01, 2'b10: + mem_req_wr_data_wdata__h5352 = _theResult___fst__h5221; + 2'd3: + mem_req_wr_data_wdata__h5352 = + cache_f_fabric_write_reqs$D_OUT[63:0]; + endcase + end + always@(cache_rg_addr or + result__h8203 or + result__h14559 or + result__h14587 or + result__h14615 or + result__h14643 or + result__h14671 or result__h14699 or result__h14727) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h8203; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14559; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14587; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14615; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14643; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14671; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14699; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14727; + endcase + end + always@(cache_rg_addr or + result__h15013 or + result__h15041 or result__h15069 or result__h15097) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 = + result__h15013; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 = + result__h15041; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 = + result__h15069; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 = + result__h15097; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h14772 or + result__h14800 or + result__h14828 or + result__h14856 or + result__h14884 or + result__h14912 or result__h14940 or result__h14968) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14772; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14800; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14828; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14856; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14884; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14912; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14940; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14968; + endcase + end + always@(cache_rg_addr or + result__h15138 or + result__h15166 or result__h15194 or result__h15222) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 = + result__h15138; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 = + result__h15166; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 = + result__h15194; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 = + result__h15222; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h15330 or result__h15358) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338 = + result__h15330; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338 = + result__h15358; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h15263 or result__h15291) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31 = + result__h15263; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31 = + result__h15291; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31 = + 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338) + begin + case (cache_rg_f3) + 3'b0: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287; + 3'b001: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317; + 3'b010: + new_value__h8148 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31; + 3'b011: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340; + 3'b100: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304; + 3'b101: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326; + 3'b110: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338; + 3'd7: new_value__h8148 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 or + w1___1__h19649 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338) + begin + case (cache_rg_f3) + 3'b0: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287; + 3'b001: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317; + 3'b010: w1__h19578 = w1___1__h19649; + 3'b011: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340; + 3'b100: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304; + 3'b101: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326; + 3'b110: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338; + 3'd7: w1__h19578 = 64'd0; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 = + { cache_ram_word64_set$DOB[63:16], cache_rg_st_amo_val[15:0] }; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 = + { cache_ram_word64_set$DOB[63:32], + cache_rg_st_amo_val[15:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 = + { cache_ram_word64_set$DOB[63:48], + cache_rg_st_amo_val[15:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 = + { cache_rg_st_amo_val[15:0], cache_ram_word64_set$DOB[47:0] }; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:8], cache_rg_st_amo_val[7:0] }; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:16], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[7:0] }; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:24], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:32], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[23:0] }; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:40], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:48], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[39:0] }; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:56], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[47:0] }; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_rg_st_amo_val[7:0], cache_ram_word64_set$DOB[55:0] }; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 or + new_value148_BITS_31_TO_0__q32 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287; + 3'b001: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317; + 3'b010: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + { {32{new_value148_BITS_31_TO_0__q32[31]}}, + new_value148_BITS_31_TO_0__q32 }; + 3'b011: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340; + 3'b100: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304; + 3'b101: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326; + 3'b110: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338; + 3'd7: IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = 64'd0; + endcase + end + always@(cache_rg_amo_funct7 or + new_st_val__h20689 or + new_st_val__h19681 or + w2__h27934 or + new_st_val__h20661 or + new_st_val__h20669 or + new_st_val__h20665 or + new_st_val__h20684 or new_st_val__h20673 or new_st_val__h20678) + begin + case (cache_rg_amo_funct7[6:2]) + 5'b0: _theResult_____2__h19586 = new_st_val__h19681; + 5'b00001: _theResult_____2__h19586 = w2__h27934; + 5'b00100: _theResult_____2__h19586 = new_st_val__h20661; + 5'b01000: _theResult_____2__h19586 = new_st_val__h20669; + 5'b01100: _theResult_____2__h19586 = new_st_val__h20665; + 5'b10000: _theResult_____2__h19586 = new_st_val__h20684; + 5'b11000: _theResult_____2__h19586 = new_st_val__h20673; + 5'b11100: _theResult_____2__h19586 = new_st_val__h20678; + default: _theResult_____2__h19586 = new_st_val__h20689; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19308) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 = + { cache_ram_word64_set$DOB[63:16], new_st_val__h19308[15:0] }; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 = + { cache_ram_word64_set$DOB[63:32], + new_st_val__h19308[15:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 = + { cache_ram_word64_set$DOB[63:48], + new_st_val__h19308[15:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 = + { new_st_val__h19308[15:0], cache_ram_word64_set$DOB[47:0] }; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19308) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:8], new_st_val__h19308[7:0] }; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:16], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[7:0] }; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:24], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:32], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[23:0] }; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:40], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:48], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[39:0] }; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:56], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[47:0] }; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { new_st_val__h19308[7:0], cache_ram_word64_set$DOB[55:0] }; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34 = + { cache_ram_word64_set$DOB[63:32], cache_rg_st_amo_val[31:0] }; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34 = + { cache_rg_st_amo_val[31:0], cache_ram_word64_set$DOB[31:0] }; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + cache_ram_word64_set$DOB or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34 or + cache_rg_st_amo_val) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425; + 3'b001: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434; + 3'b010: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34; + 3'b011: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 = + cache_rg_st_amo_val; + default: IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or + result__h26292 or + result__h26319 or result__h26346 or result__h26373) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 = + result__h26292; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 = + result__h26319; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 = + result__h26346; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 = + result__h26373; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h26171 or + result__h26198 or result__h26225 or result__h26252) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 = + result__h26171; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 = + result__h26198; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 = + result__h26225; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 = + result__h26252; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h25938 or + result__h25965 or + result__h25992 or + result__h26019 or + result__h26046 or + result__h26073 or result__h26100 or result__h26127) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h25938; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h25965; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h25992; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h26019; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h26046; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h26073; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h26100; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h26127; + endcase + end + always@(cache_rg_addr or + result__h25702 or + result__h25732 or + result__h25759 or + result__h25786 or + result__h25813 or + result__h25840 or result__h25867 or result__h25894) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25702; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25732; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25759; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25786; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25813; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25840; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25867; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25894; + endcase + end + always@(cache_rg_addr or result__h26413 or result__h26440) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36 = + result__h26413; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36 = + result__h26440; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h26478 or result__h26505) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37 = + result__h26478; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37 = + result__h26505; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h29802 or result__h29830) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851 = + result__h29802; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851 = + result__h29830; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h29485 or + result__h29513 or result__h29541 or result__h29569) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 = + result__h29485; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 = + result__h29513; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 = + result__h29541; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 = + result__h29569; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h29610 or + result__h29638 or result__h29666 or result__h29694) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 = + result__h29610; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 = + result__h29638; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 = + result__h29666; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 = + result__h29694; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h29244 or + result__h29272 or + result__h29300 or + result__h29328 or + result__h29356 or + result__h29384 or result__h29412 or result__h29440) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29244; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29272; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29300; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29328; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29356; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29384; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29412; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29440; + endcase + end + always@(cache_rg_addr or + result__h28123 or + result__h29031 or + result__h29059 or + result__h29087 or + result__h29115 or + result__h29143 or result__h29171 or result__h29199) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h28123; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29031; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29059; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29087; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29115; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29143; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29171; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29199; + endcase + end + always@(cache_rg_addr or result__h29735 or result__h29763) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52 = + result__h29735; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52 = + result__h29763; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52 = + 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851) + begin + case (cache_rg_f3) + 3'b0: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805; + 3'b001: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833; + 3'b010: + w1__h27928 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52; + 3'b011: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852; + 3'b100: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821; + 3'b101: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841; + 3'b110: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851; + 3'd7: w1__h27928 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 or + w1___1__h28003 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851) + begin + case (cache_rg_f3) + 3'b0: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805; + 3'b001: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833; + 3'b010: w1__h27932 = w1___1__h28003; + 3'b011: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852; + 3'b100: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821; + 3'b101: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841; + 3'b110: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851; + 3'd7: w1__h27932 = 64'd0; + endcase + end + always@(cache_rg_amo_funct7 or + new_st_val__h29923 or + new_st_val__h28035 or + w2__h27934 or + new_st_val__h29895 or + new_st_val__h29903 or + new_st_val__h29899 or + new_st_val__h29918 or new_st_val__h29907 or new_st_val__h29912) + begin + case (cache_rg_amo_funct7[6:2]) + 5'b0: _theResult_____2__h27940 = new_st_val__h28035; + 5'b00001: _theResult_____2__h27940 = w2__h27934; + 5'b00100: _theResult_____2__h27940 = new_st_val__h29895; + 5'b01000: _theResult_____2__h27940 = new_st_val__h29903; + 5'b01100: _theResult_____2__h27940 = new_st_val__h29899; + 5'b10000: _theResult_____2__h27940 = new_st_val__h29918; + 5'b11000: _theResult_____2__h27940 = new_st_val__h29907; + 5'b11100: _theResult_____2__h27940 = new_st_val__h29912; + default: _theResult_____2__h27940 = new_st_val__h29923; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19308) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54 = + { cache_ram_word64_set$DOB[63:32], new_st_val__h19308[31:0] }; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54 = + { new_st_val__h19308[31:0], cache_ram_word64_set$DOB[31:0] }; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + cache_ram_word64_set$DOB or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54 or + new_st_val__h19308) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499; + 3'b001: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508; + 3'b010: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54; + 3'b011: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 = + new_st_val__h19308; + default: IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d354) + begin + case (cache_rg_f3) + 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: + new_value__h18177 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d354; + 3'd7: new_value__h18177 = 64'd0; + endcase + end + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + cache_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; + cache_crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; + cache_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; + cache_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 7'd42; + cache_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 72'h2AAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + cache_rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 7'd0; + cache_rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; + end + else + begin + if (cache_cfg_verbosity$EN) + cache_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY + cache_cfg_verbosity$D_IN; + if (cache_crg_sb_to_load_delay$EN) + cache_crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY + cache_crg_sb_to_load_delay$D_IN; + if (cache_ctr_wr_rsps_pending_crg$EN) + cache_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY + cache_ctr_wr_rsps_pending_crg$D_IN; + if (cache_master_xactor_clearing$EN) + cache_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_clearing$D_IN; + if (cache_master_xactor_shim_arff_rv$EN) + cache_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_arff_rv$D_IN; + if (cache_master_xactor_shim_awff_rv$EN) + cache_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_awff_rv$D_IN; + if (cache_master_xactor_shim_bff_rv$EN) + cache_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_bff_rv$D_IN; + if (cache_master_xactor_shim_rff_rv$EN) + cache_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_rff_rv$D_IN; + if (cache_master_xactor_shim_wff_rv$EN) + cache_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_wff_rv$D_IN; + if (cache_rg_cset_in_cache$EN) + cache_rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY + cache_rg_cset_in_cache$D_IN; + if (cache_rg_lower_word32_full$EN) + cache_rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY + cache_rg_lower_word32_full$D_IN; + if (cache_rg_lrsc_valid$EN) + cache_rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY + cache_rg_lrsc_valid$D_IN; + if (cache_rg_state$EN) + cache_rg_state <= `BSV_ASSIGNMENT_DELAY cache_rg_state$D_IN; + end + if (cache_rg_addr$EN) + cache_rg_addr <= `BSV_ASSIGNMENT_DELAY cache_rg_addr$D_IN; + if (cache_rg_amo_funct7$EN) + cache_rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY cache_rg_amo_funct7$D_IN; + if (cache_rg_error_during_refill$EN) + cache_rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY + cache_rg_error_during_refill$D_IN; + if (cache_rg_exc_code$EN) + cache_rg_exc_code <= `BSV_ASSIGNMENT_DELAY cache_rg_exc_code$D_IN; + if (cache_rg_f3$EN) cache_rg_f3 <= `BSV_ASSIGNMENT_DELAY cache_rg_f3$D_IN; + if (cache_rg_ld_val$EN) + cache_rg_ld_val <= `BSV_ASSIGNMENT_DELAY cache_rg_ld_val$D_IN; + if (cache_rg_lower_word32$EN) + cache_rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY + cache_rg_lower_word32$D_IN; + if (cache_rg_lrsc_pa$EN) + cache_rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_lrsc_pa$D_IN; + if (cache_rg_op$EN) cache_rg_op <= `BSV_ASSIGNMENT_DELAY cache_rg_op$D_IN; + if (cache_rg_pa$EN) cache_rg_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_pa$D_IN; + if (cache_rg_pte_pa$EN) + cache_rg_pte_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_pte_pa$D_IN; + if (cache_rg_st_amo_val$EN) + cache_rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY cache_rg_st_amo_val$D_IN; + if (cache_rg_word64_set_in_cache$EN) + cache_rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY + cache_rg_word64_set_in_cache$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + cache_cfg_verbosity = 4'hA; + cache_crg_sb_to_load_delay = 11'h2AA; + cache_ctr_wr_rsps_pending_crg = 4'hA; + cache_master_xactor_clearing = 1'h0; + cache_master_xactor_shim_arff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_awff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_bff_rv = 7'h2A; + cache_master_xactor_shim_rff_rv = 72'hAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + cache_rg_addr = 32'hAAAAAAAA; + cache_rg_amo_funct7 = 7'h2A; + cache_rg_cset_in_cache = 7'h2A; + cache_rg_error_during_refill = 1'h0; + cache_rg_exc_code = 4'hA; + cache_rg_f3 = 3'h2; + cache_rg_ld_val = 64'hAAAAAAAAAAAAAAAA; + cache_rg_lower_word32 = 32'hAAAAAAAA; + cache_rg_lower_word32_full = 1'h0; + cache_rg_lrsc_pa = 32'hAAAAAAAA; + cache_rg_lrsc_valid = 1'h0; + cache_rg_op = 2'h2; + cache_rg_pa = 32'hAAAAAAAA; + cache_rg_pte_pa = 32'hAAAAAAAA; + cache_rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; + cache_rg_state = 4'hA; + cache_rg_word64_set_in_cache = 9'h0AA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + begin + v__h5604 = $stime; + #0; + end + v__h5598 = v__h5604 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + $display("%0d: ERROR: CreditCounter: overflow", v__h5598); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_AWFlit { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_addr_awaddr__h5054); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", _theResult___snd_snd_val__h5236, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_WFlit { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_data_wdata__h5352); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wstrb: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_data_wstrb__h5353); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + cache_cfg_verbosity != 4'd0 && + !cache_f_reset_reqs$D_OUT) + begin + v__h6425 = $stime; + #0; + end + v__h6419 = v__h6425 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + cache_cfg_verbosity != 4'd0 && + !cache_f_reset_reqs$D_OUT) + $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", + v__h6419, + "D_MMU_Cache", + $signed(32'd128), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_f_reset_reqs$D_OUT) + begin + v__h6526 = $stime; + #0; + end + v__h6520 = v__h6526 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_f_reset_reqs$D_OUT) + $display("%0d: %s.rl_reset: Flushed", v__h6520, "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h6977 = $stime; + #0; + end + v__h6971 = v__h6977 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", + v__h6971, + "D_MMU_Cache", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", + pa_ctag__h7827, + cache_rg_addr[11:5], + cache_rg_addr[4:3], + cache_rg_addr[2:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" CSet 0x%0x: (state, tag):", cache_rg_addr[11:5]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" ("); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_ram_state_and_ctag_cset$DOB[22]) + $write("CTAG_CLEAN"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_ram_state_and_ctag_cset$DOB[22]) + $write("CTAG_EMPTY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_ram_state_and_ctag_cset$DOB[22]) + $write(", 0x%0x", cache_ram_state_and_ctag_cset$DOB[21:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_ram_state_and_ctag_cset$DOB[22]) + $write(", --"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(")"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" 0x%0x", cache_ram_word64_set$DOB); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" TLB result: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("VM_Xlate_Result { ", "outcome: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("VM_XLATE_OK"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "pa: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'hA, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d358) + begin + v__h15442 = $stime; + #0; + end + v__h15436 = v__h15442 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d358) + $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", + v__h15436, + "D_MMU_Cache", + cache_rg_addr, + word64__h7969, + 64'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO LR: reserving PA 0x%0h", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d358) + $display(" Read-hit: addr 0x%0h word64 0x%0h", + cache_rg_addr, + word64__h7969); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d371) + $display(" Read Miss: -> CACHE_START_REFILL."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7_36_BITS_6_TO_2_37_EQ_0b10__ETC___d375) + $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", + cache_rg_lrsc_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd1 && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" ST: cancelling LR/SC reservation for PA", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + cache_rg_lrsc_valid && + !cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", + cache_rg_lrsc_pa, + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + !cache_rg_lrsc_valid && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC: fail due to invalid LR/SC reservation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC result = %0d", lrsc_result__h15819); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549) + $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549) + $write(" New Word64_Set:"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549) + $write(" 0x%0x", + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d551) + $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d557) + $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d557) + $display(" => rl_write_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_2_35_AND_cache_rg_amo_funct7_ETC___d561) + begin + v__h19086 = $stime; + #0; + end + v__h19080 = v__h19086 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_2_35_AND_cache_rg_amo_funct7_ETC___d561) + $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", + v__h19080, + "D_MMU_Cache", + cache_rg_addr, + 64'd1, + 64'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_2_35_AND_cache_rg_amo_funct7_ETC___d561) + $display(" AMO SC: Fail response for addr 0x%0h", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d565) + $display(" AMO Miss: -> CACHE_START_REFILL."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", + cache_rg_addr, + cache_rg_amo_funct7, + cache_rg_f3, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $display(" PA 0x%0h ", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $display(" Cache word64 0x%0h, load-result 0x%0h", + word64__h7969, + word64__h7969); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $display(" 0x%0h op 0x%0h -> 0x%0h", + word64__h7969, + word64__h7969, + new_st_val__h19308); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $write(" New Word64_Set:"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $write(" 0x%0x", + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d572) + $display(" AMO_op: cancelling LR/SC reservation for PA", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + !cache_soc_map$m_is_mem_addr && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => IO_REQ"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h22330 = $stime; + #0; + end + v__h22324 = v__h22330 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_start_cache_refill: ", v__h22324, "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cline_fabric_addr__h22383); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd3); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'b011, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" Victim way %0d; => CACHE_REFILL", 1'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_rereq && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", + cache_rg_addr[11:5], + cache_rg_addr[11:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h25145 = $stime; + #0; + end + v__h25139 = v__h25145 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", + v__h25139, + "D_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", fabric_addr__h27309); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", size_val__h27412, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_maintain_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26849 = $stime; + #0; + end + v__h26843 = v__h26849 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_maintain_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h26843, + "D_MMU_Cache", + cache_rg_addr, + cache_rg_ld_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26929 = $stime; + #0; + end + v__h26923 = v__h26929 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h26923, + "D_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27139 = $stime; + #0; + end + v__h27133 = v__h27139 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h27133, + "D_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" FAIL due to I/O address."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27257 = $stime; + #0; + end + v__h27251 = v__h27257 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", + v__h27251, + "D_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", fabric_addr__h27309); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", size_val__h27412, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h30743 = $stime; + #0; + end + v__h30737 = v__h30743 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("%0d: %s.rl_discard_write_rsp: pending %0d ", + v__h30737, + "D_MMU_Cache", + $unsigned(b__h22284)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_bff_rv$port1__read[5:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + begin + v__h30704 = $stime; + #0; + end + v__h30698 = v__h30704 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", + v__h30698, + "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("'h%h", cache_master_xactor_shim_bff_rv$port1__read[5:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0 && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd1 && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_reset && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h6060 = $stime; + #0; + end + v__h6054 = v__h6060 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_reset && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_start_reset", v__h6054, "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + begin + v__h23274 = $stime; + #0; + end + v__h23268 = v__h23274 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $display("%0d: %s.rl_cache_refill_rsps_loop:", + v__h23268, + "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h23536 = $stime; + #0; + end + v__h23530 = v__h23536 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", + v__h23530, + "D_MMU_Cache", + access_exc_code__h4779); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 && + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_rg_error_during_refill) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => MODULE_EXCEPTION_RSP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + !cache_rg_error_during_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => CACHE_REREQ"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", + cache_rg_word64_set_in_cache, + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(" 0x%0x", cache_ram_word64_set$DOB); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(" 0x%0x", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h25517 = $stime; + #0; + end + v__h25511 = v__h25517 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", + v__h25511, + "D_MMU_Cache", + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26635 = $stime; + #0; + end + v__h26629 = v__h26635 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h26629, + "D_MMU_Cache", + cache_rg_addr, + ld_val__h25642); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26742 = $stime; + #0; + end + v__h26736 = v__h26742 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", + v__h26736, + "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27573 = $stime; + #0; + end + v__h27567 = v__h27573 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", + v__h27567, + "D_MMU_Cache", + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27768 = $stime; + #0; + end + v__h27762 = v__h27768 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h27762, + "D_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h30027 = $stime; + #0; + end + v__h30021 = v__h30027 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h30021, + "D_MMU_Cache", + cache_rg_addr, + new_ld_val__h27894); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27864 = $stime; + #0; + end + v__h27858 = v__h27864 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", + v__h27858, + "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h31126 = $stime; + #0; + end + v__h31120 = v__h31126 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("%0d: %s.req: op:", v__h31120, "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op == 2'd0) + $write("CACHE_LD"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op == 2'd1) + $write("CACHE_ST"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op != 2'd0 && + req_op != 2'd1) + $write("CACHE_AMO"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", + req_f3, + req_addr, + req_st_value); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b0) + $write("U"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b01) + $write("S"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b11) + $write("M"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv != 2'b0 && + req_priv != 2'b01 && + req_priv != 2'b11) + $write("RESERVED"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", + req_sstatus_SUM, + req_mstatus_MXR, + req_satp, + "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" amo_funct7 = 0x%0h", req_amo_funct7); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && + req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", + req_addr[11:5], + req_addr[11:3]); + end + // synopsys translate_on +endmodule // mkMMU_DCache + diff --git a/src_SSITH_P1/Verilog_RTL/mkMMU_ICache.v b/src_SSITH_P1/Verilog_RTL/mkMMU_ICache.v new file mode 100644 index 00000000..9fd496a1 --- /dev/null +++ b/src_SSITH_P1/Verilog_RTL/mkMMU_ICache.v @@ -0,0 +1,5472 @@ +// +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// +// On Tue Jul 9 16:18:43 BST 2019 +// +// +// Ports: +// Name I/O size props +// RDY_set_verbosity O 1 const +// RDY_server_reset_request_put O 1 reg +// RDY_server_reset_response_get O 1 +// valid O 1 +// addr O 32 reg +// word64 O 64 +// st_amo_val O 64 +// exc O 1 +// exc_code O 4 reg +// RDY_server_flush_request_put O 1 reg +// RDY_server_flush_response_get O 1 +// RDY_tlb_flush O 1 const +// mem_master_awid O 5 +// mem_master_awaddr O 64 +// mem_master_awlen O 8 +// mem_master_awsize O 3 +// mem_master_awburst O 2 +// mem_master_awlock O 1 +// mem_master_awcache O 4 +// mem_master_awprot O 3 +// mem_master_awqos O 4 +// mem_master_awregion O 4 +// mem_master_awvalid O 1 +// mem_master_wdata O 64 +// mem_master_wstrb O 8 +// mem_master_wlast O 1 +// mem_master_wvalid O 1 +// mem_master_bready O 1 +// mem_master_arid O 5 +// mem_master_araddr O 64 +// mem_master_arlen O 8 +// mem_master_arsize O 3 +// mem_master_arburst O 2 +// mem_master_arlock O 1 +// mem_master_arcache O 4 +// mem_master_arprot O 3 +// mem_master_arqos O 4 +// mem_master_arregion O 4 +// mem_master_arvalid O 1 +// mem_master_rready O 1 +// CLK I 1 clock +// RST_N I 1 reset +// set_verbosity_verbosity I 4 reg +// req_op I 2 +// req_f3 I 3 +// req_amo_funct7 I 7 reg +// req_addr I 32 +// req_st_value I 64 +// req_priv I 2 unused +// req_sstatus_SUM I 1 unused +// req_mstatus_MXR I 1 unused +// req_satp I 32 unused +// mem_master_awready I 1 +// mem_master_wready I 1 +// mem_master_bid I 5 +// mem_master_bresp I 2 +// mem_master_arready I 1 +// mem_master_rid I 5 +// mem_master_rdata I 64 +// mem_master_rresp I 2 +// mem_master_rlast I 1 +// EN_set_verbosity I 1 +// EN_server_reset_request_put I 1 +// EN_server_reset_response_get I 1 +// EN_req I 1 +// EN_server_flush_request_put I 1 +// EN_server_flush_response_get I 1 +// EN_tlb_flush I 1 unused +// mem_master_bvalid I 1 +// mem_master_rvalid I 1 +// +// Combinational paths from inputs to outputs: +// (mem_master_rid, +// mem_master_rdata, +// mem_master_rresp, +// mem_master_rlast, +// mem_master_rvalid) -> valid +// (mem_master_rid, +// mem_master_rdata, +// mem_master_rresp, +// mem_master_rlast, +// mem_master_rvalid) -> word64 +// EN_req -> mem_master_arid +// EN_req -> mem_master_araddr +// EN_req -> mem_master_arlen +// EN_req -> mem_master_arsize +// EN_req -> mem_master_arburst +// EN_req -> mem_master_arlock +// EN_req -> mem_master_arcache +// EN_req -> mem_master_arprot +// EN_req -> mem_master_arqos +// EN_req -> mem_master_arregion +// EN_req -> mem_master_aruser +// EN_req -> mem_master_arvalid +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkMMU_ICache(CLK, + RST_N, + + set_verbosity_verbosity, + EN_set_verbosity, + RDY_set_verbosity, + + EN_server_reset_request_put, + RDY_server_reset_request_put, + + EN_server_reset_response_get, + RDY_server_reset_response_get, + + req_op, + req_f3, + req_amo_funct7, + req_addr, + req_st_value, + req_priv, + req_sstatus_SUM, + req_mstatus_MXR, + req_satp, + EN_req, + + valid, + + addr, + + word64, + + st_amo_val, + + exc, + + exc_code, + + EN_server_flush_request_put, + RDY_server_flush_request_put, + + EN_server_flush_response_get, + RDY_server_flush_response_get, + + EN_tlb_flush, + RDY_tlb_flush, + + mem_master_awid, + + mem_master_awaddr, + + mem_master_awlen, + + mem_master_awsize, + + mem_master_awburst, + + mem_master_awlock, + + mem_master_awcache, + + mem_master_awprot, + + mem_master_awqos, + + mem_master_awregion, + + mem_master_awvalid, + + mem_master_awready, + + mem_master_wdata, + + mem_master_wstrb, + + mem_master_wlast, + + mem_master_wvalid, + + mem_master_wready, + + mem_master_bid, + mem_master_bresp, + mem_master_bvalid, + + mem_master_bready, + + mem_master_arid, + + mem_master_araddr, + + mem_master_arlen, + + mem_master_arsize, + + mem_master_arburst, + + mem_master_arlock, + + mem_master_arcache, + + mem_master_arprot, + + mem_master_arqos, + + mem_master_arregion, + + mem_master_arvalid, + + mem_master_arready, + + mem_master_rid, + mem_master_rdata, + mem_master_rresp, + mem_master_rlast, + mem_master_rvalid, + + mem_master_rready); + input CLK; + input RST_N; + + // action method set_verbosity + input [3 : 0] set_verbosity_verbosity; + input EN_set_verbosity; + output RDY_set_verbosity; + + // action method server_reset_request_put + input EN_server_reset_request_put; + output RDY_server_reset_request_put; + + // action method server_reset_response_get + input EN_server_reset_response_get; + output RDY_server_reset_response_get; + + // action method req + input [1 : 0] req_op; + input [2 : 0] req_f3; + input [6 : 0] req_amo_funct7; + input [31 : 0] req_addr; + input [63 : 0] req_st_value; + input [1 : 0] req_priv; + input req_sstatus_SUM; + input req_mstatus_MXR; + input [31 : 0] req_satp; + input EN_req; + + // value method valid + output valid; + + // value method addr + output [31 : 0] addr; + + // value method word64 + output [63 : 0] word64; + + // value method st_amo_val + output [63 : 0] st_amo_val; + + // value method exc + output exc; + + // value method exc_code + output [3 : 0] exc_code; + + // action method server_flush_request_put + input EN_server_flush_request_put; + output RDY_server_flush_request_put; + + // action method server_flush_response_get + input EN_server_flush_response_get; + output RDY_server_flush_response_get; + + // action method tlb_flush + input EN_tlb_flush; + output RDY_tlb_flush; + + // value method mem_master_aw_awid + output [4 : 0] mem_master_awid; + + // value method mem_master_aw_awaddr + output [63 : 0] mem_master_awaddr; + + // value method mem_master_aw_awlen + output [7 : 0] mem_master_awlen; + + // value method mem_master_aw_awsize + output [2 : 0] mem_master_awsize; + + // value method mem_master_aw_awburst + output [1 : 0] mem_master_awburst; + + // value method mem_master_aw_awlock + output mem_master_awlock; + + // value method mem_master_aw_awcache + output [3 : 0] mem_master_awcache; + + // value method mem_master_aw_awprot + output [2 : 0] mem_master_awprot; + + // value method mem_master_aw_awqos + output [3 : 0] mem_master_awqos; + + // value method mem_master_aw_awregion + output [3 : 0] mem_master_awregion; + + // value method mem_master_aw_awuser + + // value method mem_master_aw_awvalid + output mem_master_awvalid; + + // action method mem_master_aw_awready + input mem_master_awready; + + // value method mem_master_w_wdata + output [63 : 0] mem_master_wdata; + + // value method mem_master_w_wstrb + output [7 : 0] mem_master_wstrb; + + // value method mem_master_w_wlast + output mem_master_wlast; + + // value method mem_master_w_wuser + + // value method mem_master_w_wvalid + output mem_master_wvalid; + + // action method mem_master_w_wready + input mem_master_wready; + + // action method mem_master_b_bflit + input [4 : 0] mem_master_bid; + input [1 : 0] mem_master_bresp; + input mem_master_bvalid; + + // value method mem_master_b_bready + output mem_master_bready; + + // value method mem_master_ar_arid + output [4 : 0] mem_master_arid; + + // value method mem_master_ar_araddr + output [63 : 0] mem_master_araddr; + + // value method mem_master_ar_arlen + output [7 : 0] mem_master_arlen; + + // value method mem_master_ar_arsize + output [2 : 0] mem_master_arsize; + + // value method mem_master_ar_arburst + output [1 : 0] mem_master_arburst; + + // value method mem_master_ar_arlock + output mem_master_arlock; + + // value method mem_master_ar_arcache + output [3 : 0] mem_master_arcache; + + // value method mem_master_ar_arprot + output [2 : 0] mem_master_arprot; + + // value method mem_master_ar_arqos + output [3 : 0] mem_master_arqos; + + // value method mem_master_ar_arregion + output [3 : 0] mem_master_arregion; + + // value method mem_master_ar_aruser + + // value method mem_master_ar_arvalid + output mem_master_arvalid; + + // action method mem_master_ar_arready + input mem_master_arready; + + // action method mem_master_r_rflit + input [4 : 0] mem_master_rid; + input [63 : 0] mem_master_rdata; + input [1 : 0] mem_master_rresp; + input mem_master_rlast; + input mem_master_rvalid; + + // value method mem_master_r_rready + output mem_master_rready; + + // signals for module outputs + reg [63 : 0] word64; + wire [63 : 0] mem_master_araddr, + mem_master_awaddr, + mem_master_wdata, + st_amo_val; + wire [31 : 0] addr; + wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; + wire [4 : 0] mem_master_arid, mem_master_awid; + wire [3 : 0] exc_code, + mem_master_arcache, + mem_master_arqos, + mem_master_arregion, + mem_master_awcache, + mem_master_awqos, + mem_master_awregion; + wire [2 : 0] mem_master_arprot, + mem_master_arsize, + mem_master_awprot, + mem_master_awsize; + wire [1 : 0] mem_master_arburst, mem_master_awburst; + wire RDY_server_flush_request_put, + RDY_server_flush_response_get, + RDY_server_reset_request_put, + RDY_server_reset_response_get, + RDY_set_verbosity, + RDY_tlb_flush, + exc, + mem_master_arlock, + mem_master_arvalid, + mem_master_awlock, + mem_master_awvalid, + mem_master_bready, + mem_master_rready, + mem_master_wlast, + mem_master_wvalid, + valid; + + // inlined wires + wire [98 : 0] cache_master_xactor_shim_arff_rv$port0__write_1, + cache_master_xactor_shim_arff_rv$port1__read, + cache_master_xactor_shim_arff_rv$port2__read, + cache_master_xactor_shim_arff_rv$port3__read, + cache_master_xactor_shim_awff_rv$port0__write_1, + cache_master_xactor_shim_awff_rv$port1__read, + cache_master_xactor_shim_awff_rv$port2__read, + cache_master_xactor_shim_awff_rv$port3__read; + wire [73 : 0] cache_master_xactor_shim_wff_rv$port0__write_1, + cache_master_xactor_shim_wff_rv$port1__read, + cache_master_xactor_shim_wff_rv$port2__read, + cache_master_xactor_shim_wff_rv$port3__read; + wire [72 : 0] cache_master_xactor_shim_rff_rv$port0__write_1, + cache_master_xactor_shim_rff_rv$port1__read, + cache_master_xactor_shim_rff_rv$port2__read, + cache_master_xactor_shim_rff_rv$port3__read; + wire [71 : 0] cache_master_xactor_ug_master_u_r_putWire$wget; + wire [10 : 0] cache_crg_sb_to_load_delay$port0__write_1, + cache_crg_sb_to_load_delay$port2__read; + wire [7 : 0] cache_master_xactor_shim_bff_rv$port0__write_1, + cache_master_xactor_shim_bff_rv$port1__read, + cache_master_xactor_shim_bff_rv$port2__read, + cache_master_xactor_shim_bff_rv$port3__read; + wire [6 : 0] cache_master_xactor_ug_master_u_b_putWire$wget; + wire [3 : 0] cache_ctr_wr_rsps_pending_crg$port0__write_1, + cache_ctr_wr_rsps_pending_crg$port1__write_1, + cache_ctr_wr_rsps_pending_crg$port2__read, + cache_ctr_wr_rsps_pending_crg$port3__read; + wire cache_crg_sb_to_load_delay$EN_port1__write, + cache_dw_valid$whas, + cache_master_xactor_shim_arff_rv$EN_port0__write, + cache_master_xactor_shim_rff_rv$EN_port1__write, + cache_master_xactor_ug_master_u_ar_dropWire$whas, + cache_master_xactor_ug_master_u_aw_dropWire$whas, + cache_master_xactor_ug_master_u_b_putWire$whas, + cache_master_xactor_ug_master_u_r_putWire$whas, + cache_master_xactor_ug_master_u_w_dropWire$whas; + + // register cache_cfg_verbosity + reg [3 : 0] cache_cfg_verbosity; + wire [3 : 0] cache_cfg_verbosity$D_IN; + wire cache_cfg_verbosity$EN; + + // register cache_crg_sb_to_load_delay + reg [10 : 0] cache_crg_sb_to_load_delay; + wire [10 : 0] cache_crg_sb_to_load_delay$D_IN; + wire cache_crg_sb_to_load_delay$EN; + + // register cache_ctr_wr_rsps_pending_crg + reg [3 : 0] cache_ctr_wr_rsps_pending_crg; + wire [3 : 0] cache_ctr_wr_rsps_pending_crg$D_IN; + wire cache_ctr_wr_rsps_pending_crg$EN; + + // register cache_master_xactor_clearing + reg cache_master_xactor_clearing; + wire cache_master_xactor_clearing$D_IN, cache_master_xactor_clearing$EN; + + // register cache_master_xactor_shim_arff_rv + reg [98 : 0] cache_master_xactor_shim_arff_rv; + wire [98 : 0] cache_master_xactor_shim_arff_rv$D_IN; + wire cache_master_xactor_shim_arff_rv$EN; + + // register cache_master_xactor_shim_awff_rv + reg [98 : 0] cache_master_xactor_shim_awff_rv; + wire [98 : 0] cache_master_xactor_shim_awff_rv$D_IN; + wire cache_master_xactor_shim_awff_rv$EN; + + // register cache_master_xactor_shim_bff_rv + reg [7 : 0] cache_master_xactor_shim_bff_rv; + wire [7 : 0] cache_master_xactor_shim_bff_rv$D_IN; + wire cache_master_xactor_shim_bff_rv$EN; + + // register cache_master_xactor_shim_rff_rv + reg [72 : 0] cache_master_xactor_shim_rff_rv; + wire [72 : 0] cache_master_xactor_shim_rff_rv$D_IN; + wire cache_master_xactor_shim_rff_rv$EN; + + // register cache_master_xactor_shim_wff_rv + reg [73 : 0] cache_master_xactor_shim_wff_rv; + wire [73 : 0] cache_master_xactor_shim_wff_rv$D_IN; + wire cache_master_xactor_shim_wff_rv$EN; + + // register cache_rg_addr + reg [31 : 0] cache_rg_addr; + wire [31 : 0] cache_rg_addr$D_IN; + wire cache_rg_addr$EN; + + // register cache_rg_amo_funct7 + reg [6 : 0] cache_rg_amo_funct7; + wire [6 : 0] cache_rg_amo_funct7$D_IN; + wire cache_rg_amo_funct7$EN; + + // register cache_rg_cset_in_cache + reg [6 : 0] cache_rg_cset_in_cache; + wire [6 : 0] cache_rg_cset_in_cache$D_IN; + wire cache_rg_cset_in_cache$EN; + + // register cache_rg_error_during_refill + reg cache_rg_error_during_refill; + wire cache_rg_error_during_refill$D_IN, cache_rg_error_during_refill$EN; + + // register cache_rg_exc_code + reg [3 : 0] cache_rg_exc_code; + reg [3 : 0] cache_rg_exc_code$D_IN; + wire cache_rg_exc_code$EN; + + // register cache_rg_f3 + reg [2 : 0] cache_rg_f3; + wire [2 : 0] cache_rg_f3$D_IN; + wire cache_rg_f3$EN; + + // register cache_rg_ld_val + reg [63 : 0] cache_rg_ld_val; + reg [63 : 0] cache_rg_ld_val$D_IN; + wire cache_rg_ld_val$EN; + + // register cache_rg_lower_word32 + reg [31 : 0] cache_rg_lower_word32; + wire [31 : 0] cache_rg_lower_word32$D_IN; + wire cache_rg_lower_word32$EN; + + // register cache_rg_lower_word32_full + reg cache_rg_lower_word32_full; + wire cache_rg_lower_word32_full$D_IN, cache_rg_lower_word32_full$EN; + + // register cache_rg_lrsc_pa + reg [31 : 0] cache_rg_lrsc_pa; + wire [31 : 0] cache_rg_lrsc_pa$D_IN; + wire cache_rg_lrsc_pa$EN; + + // register cache_rg_lrsc_valid + reg cache_rg_lrsc_valid; + wire cache_rg_lrsc_valid$D_IN, cache_rg_lrsc_valid$EN; + + // register cache_rg_op + reg [1 : 0] cache_rg_op; + wire [1 : 0] cache_rg_op$D_IN; + wire cache_rg_op$EN; + + // register cache_rg_pa + reg [31 : 0] cache_rg_pa; + wire [31 : 0] cache_rg_pa$D_IN; + wire cache_rg_pa$EN; + + // register cache_rg_pte_pa + reg [31 : 0] cache_rg_pte_pa; + wire [31 : 0] cache_rg_pte_pa$D_IN; + wire cache_rg_pte_pa$EN; + + // register cache_rg_st_amo_val + reg [63 : 0] cache_rg_st_amo_val; + wire [63 : 0] cache_rg_st_amo_val$D_IN; + wire cache_rg_st_amo_val$EN; + + // register cache_rg_state + reg [3 : 0] cache_rg_state; + reg [3 : 0] cache_rg_state$D_IN; + wire cache_rg_state$EN; + + // register cache_rg_word64_set_in_cache + reg [8 : 0] cache_rg_word64_set_in_cache; + wire [8 : 0] cache_rg_word64_set_in_cache$D_IN; + wire cache_rg_word64_set_in_cache$EN; + + // ports of submodule cache_f_fabric_write_reqs + reg [98 : 0] cache_f_fabric_write_reqs$D_IN; + wire [98 : 0] cache_f_fabric_write_reqs$D_OUT; + wire cache_f_fabric_write_reqs$CLR, + cache_f_fabric_write_reqs$DEQ, + cache_f_fabric_write_reqs$EMPTY_N, + cache_f_fabric_write_reqs$ENQ, + cache_f_fabric_write_reqs$FULL_N; + + // ports of submodule cache_f_reset_reqs + wire cache_f_reset_reqs$CLR, + cache_f_reset_reqs$DEQ, + cache_f_reset_reqs$D_IN, + cache_f_reset_reqs$D_OUT, + cache_f_reset_reqs$EMPTY_N, + cache_f_reset_reqs$ENQ, + cache_f_reset_reqs$FULL_N; + + // ports of submodule cache_f_reset_rsps + wire cache_f_reset_rsps$CLR, + cache_f_reset_rsps$DEQ, + cache_f_reset_rsps$D_IN, + cache_f_reset_rsps$D_OUT, + cache_f_reset_rsps$EMPTY_N, + cache_f_reset_rsps$ENQ, + cache_f_reset_rsps$FULL_N; + + // ports of submodule cache_ram_state_and_ctag_cset + wire [22 : 0] cache_ram_state_and_ctag_cset$DIA, + cache_ram_state_and_ctag_cset$DIB, + cache_ram_state_and_ctag_cset$DOB; + wire [6 : 0] cache_ram_state_and_ctag_cset$ADDRA, + cache_ram_state_and_ctag_cset$ADDRB; + wire cache_ram_state_and_ctag_cset$ENA, + cache_ram_state_and_ctag_cset$ENB, + cache_ram_state_and_ctag_cset$WEA, + cache_ram_state_and_ctag_cset$WEB; + + // ports of submodule cache_ram_word64_set + reg [63 : 0] cache_ram_word64_set$DIB; + reg [8 : 0] cache_ram_word64_set$ADDRB; + wire [63 : 0] cache_ram_word64_set$DIA, cache_ram_word64_set$DOB; + wire [8 : 0] cache_ram_word64_set$ADDRA; + wire cache_ram_word64_set$ENA, + cache_ram_word64_set$ENB, + cache_ram_word64_set$WEA, + cache_ram_word64_set$WEB; + + // ports of submodule cache_soc_map + wire [63 : 0] cache_soc_map$m_is_IO_addr_addr, + cache_soc_map$m_is_mem_addr_addr, + cache_soc_map$m_is_near_mem_IO_addr_addr; + + // rule scheduling signals + wire CAN_FIRE_RL_cache_master_xactor_do_clear, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_cache_rl_ST_AMO_response, + CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop, + CAN_FIRE_RL_cache_rl_discard_write_rsp, + CAN_FIRE_RL_cache_rl_drive_exception_rsp, + CAN_FIRE_RL_cache_rl_fabric_send_write_req, + CAN_FIRE_RL_cache_rl_io_AMO_SC_req, + CAN_FIRE_RL_cache_rl_io_AMO_op_req, + CAN_FIRE_RL_cache_rl_io_AMO_read_rsp, + CAN_FIRE_RL_cache_rl_io_read_req, + CAN_FIRE_RL_cache_rl_io_read_rsp, + CAN_FIRE_RL_cache_rl_io_write_req, + CAN_FIRE_RL_cache_rl_maintain_io_read_rsp, + CAN_FIRE_RL_cache_rl_probe_and_immed_rsp, + CAN_FIRE_RL_cache_rl_rereq, + CAN_FIRE_RL_cache_rl_reset, + CAN_FIRE_RL_cache_rl_shift_sb_to_load_delay, + CAN_FIRE_RL_cache_rl_start_cache_refill, + CAN_FIRE_RL_cache_rl_start_reset, + CAN_FIRE_mem_master_ar_arready, + CAN_FIRE_mem_master_aw_awready, + CAN_FIRE_mem_master_b_bflit, + CAN_FIRE_mem_master_r_rflit, + CAN_FIRE_mem_master_w_wready, + CAN_FIRE_req, + CAN_FIRE_server_flush_request_put, + CAN_FIRE_server_flush_response_get, + CAN_FIRE_server_reset_request_put, + CAN_FIRE_server_reset_response_get, + CAN_FIRE_set_verbosity, + CAN_FIRE_tlb_flush, + WILL_FIRE_RL_cache_master_xactor_do_clear, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_cache_rl_ST_AMO_response, + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop, + WILL_FIRE_RL_cache_rl_discard_write_rsp, + WILL_FIRE_RL_cache_rl_drive_exception_rsp, + WILL_FIRE_RL_cache_rl_fabric_send_write_req, + WILL_FIRE_RL_cache_rl_io_AMO_SC_req, + WILL_FIRE_RL_cache_rl_io_AMO_op_req, + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp, + WILL_FIRE_RL_cache_rl_io_read_req, + WILL_FIRE_RL_cache_rl_io_read_rsp, + WILL_FIRE_RL_cache_rl_io_write_req, + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp, + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp, + WILL_FIRE_RL_cache_rl_rereq, + WILL_FIRE_RL_cache_rl_reset, + WILL_FIRE_RL_cache_rl_shift_sb_to_load_delay, + WILL_FIRE_RL_cache_rl_start_cache_refill, + WILL_FIRE_RL_cache_rl_start_reset, + WILL_FIRE_mem_master_ar_arready, + WILL_FIRE_mem_master_aw_awready, + WILL_FIRE_mem_master_b_bflit, + WILL_FIRE_mem_master_r_rflit, + WILL_FIRE_mem_master_w_wready, + WILL_FIRE_req, + WILL_FIRE_server_flush_request_put, + WILL_FIRE_server_flush_response_get, + WILL_FIRE_server_reset_request_put, + WILL_FIRE_server_reset_response_get, + WILL_FIRE_set_verbosity, + WILL_FIRE_tlb_flush; + + // inputs to muxes for submodule ports + wire [98 : 0] MUX_cache_f_fabric_write_reqs$enq_1__VAL_1, + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2, + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3, + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1, + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2; + wire [63 : 0] MUX_cache_dw_output_ld_val$wset_1__VAL_3, + MUX_cache_ram_word64_set$a_put_3__VAL_2, + MUX_cache_rg_ld_val$write_1__VAL_2; + wire [22 : 0] MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1; + wire [8 : 0] MUX_cache_ram_word64_set$b_put_2__VAL_2, + MUX_cache_ram_word64_set$b_put_2__VAL_4; + wire [6 : 0] MUX_cache_rg_cset_in_cache$write_1__VAL_1; + wire [3 : 0] MUX_cache_rg_exc_code$write_1__VAL_1, + MUX_cache_rg_state$write_1__VAL_1, + MUX_cache_rg_state$write_1__VAL_12, + MUX_cache_rg_state$write_1__VAL_2, + MUX_cache_rg_state$write_1__VAL_4; + wire MUX_cache_dw_output_ld_val$wset_1__SEL_1, + MUX_cache_dw_output_ld_val$wset_1__SEL_2, + MUX_cache_dw_output_ld_val$wset_1__SEL_3, + MUX_cache_dw_output_ld_val$wset_1__SEL_4, + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2, + MUX_cache_master_xactor_clearing$write_1__SEL_2, + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1, + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1, + MUX_cache_ram_word64_set$a_put_1__SEL_1, + MUX_cache_ram_word64_set$b_put_1__SEL_2, + MUX_cache_rg_error_during_refill$write_1__SEL_1, + MUX_cache_rg_exc_code$write_1__SEL_1, + MUX_cache_rg_exc_code$write_1__SEL_2, + MUX_cache_rg_exc_code$write_1__SEL_3, + MUX_cache_rg_ld_val$write_1__SEL_2, + MUX_cache_rg_lrsc_valid$write_1__SEL_2, + MUX_cache_rg_state$write_1__SEL_12, + MUX_cache_rg_state$write_1__SEL_13, + MUX_cache_rg_state$write_1__SEL_4; + + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h5641; + reg [31 : 0] v__h6477; + reg [31 : 0] v__h6580; + reg [31 : 0] v__h7034; + reg [31 : 0] v__h15467; + reg [31 : 0] v__h19180; + reg [31 : 0] v__h22537; + reg [31 : 0] v__h25370; + reg [31 : 0] v__h27092; + reg [31 : 0] v__h27175; + reg [31 : 0] v__h27388; + reg [31 : 0] v__h27509; + reg [31 : 0] v__h31052; + reg [31 : 0] v__h31013; + reg [31 : 0] v__h6102; + reg [31 : 0] v__h23486; + reg [31 : 0] v__h23740; + reg [31 : 0] v__h25756; + reg [31 : 0] v__h26874; + reg [31 : 0] v__h26982; + reg [31 : 0] v__h27839; + reg [31 : 0] v__h28034; + reg [31 : 0] v__h30336; + reg [31 : 0] v__h28131; + reg [31 : 0] v__h31440; + reg [31 : 0] v__h5635; + reg [31 : 0] v__h6096; + reg [31 : 0] v__h6471; + reg [31 : 0] v__h6574; + reg [31 : 0] v__h7028; + reg [31 : 0] v__h15461; + reg [31 : 0] v__h19174; + reg [31 : 0] v__h22531; + reg [31 : 0] v__h23480; + reg [31 : 0] v__h23734; + reg [31 : 0] v__h25364; + reg [31 : 0] v__h25750; + reg [31 : 0] v__h26868; + reg [31 : 0] v__h26976; + reg [31 : 0] v__h27086; + reg [31 : 0] v__h27169; + reg [31 : 0] v__h27382; + reg [31 : 0] v__h27503; + reg [31 : 0] v__h27833; + reg [31 : 0] v__h28028; + reg [31 : 0] v__h28125; + reg [31 : 0] v__h30330; + reg [31 : 0] v__h31007; + reg [31 : 0] v__h31046; + reg [31 : 0] v__h31434; + // synopsys translate_on + + // remaining internal signals + reg [63 : 0] CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820, + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428, + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502, + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371, + _theResult_____2__h19690, + _theResult_____2__h28207, + ld_val__h25881, + mem_req_wr_data_wdata__h5366, + new_ld_val__h28161, + new_value__h18271, + new_value__h8173, + w1__h19682, + w1__h28195, + w1__h28199; + reg [7 : 0] mem_req_wr_data_wstrb__h5367; + reg [2 : 0] _theResult___snd_snd_val__h5250, size_val__h27675; + wire [97 : 0] cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22, + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20; + wire [72 : 0] cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q21; + wire [63 : 0] IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d338, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821, + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434, + IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d514, + _theResult___fst__h5232, + b__h19806, + b__h28323, + b__h30158, + cline_fabric_addr__h22590, + fabric_addr__h27561, + mem_req_wr_addr_awaddr__h5054, + new_st_val__h19402, + new_st_val__h19697, + new_st_val__h19798, + new_st_val__h20791, + new_st_val__h20796, + new_st_val__h20801, + new_st_val__h20806, + new_st_val__h20814, + new_st_val__h20823, + new_st_val__h20831, + new_st_val__h28214, + new_st_val__h28315, + new_st_val__h30188, + new_st_val__h30193, + new_st_val__h30198, + new_st_val__h30203, + new_st_val__h30211, + new_st_val__h30220, + new_st_val__h30228, + result__h14584, + result__h14612, + result__h14640, + result__h14668, + result__h14696, + result__h14724, + result__h14752, + result__h14797, + result__h14825, + result__h14853, + result__h14881, + result__h14909, + result__h14937, + result__h14965, + result__h14993, + result__h15038, + result__h15066, + result__h15094, + result__h15122, + result__h15163, + result__h15191, + result__h15219, + result__h15247, + result__h15288, + result__h15316, + result__h15355, + result__h15383, + result__h25941, + result__h25971, + result__h25998, + result__h26025, + result__h26052, + result__h26079, + result__h26106, + result__h26133, + result__h26177, + result__h26204, + result__h26231, + result__h26258, + result__h26285, + result__h26312, + result__h26339, + result__h26366, + result__h26410, + result__h26437, + result__h26464, + result__h26491, + result__h26531, + result__h26558, + result__h26585, + result__h26612, + result__h26652, + result__h26679, + result__h26717, + result__h26744, + result__h28412, + result__h29320, + result__h29348, + result__h29376, + result__h29404, + result__h29432, + result__h29460, + result__h29488, + result__h29533, + result__h29561, + result__h29589, + result__h29617, + result__h29645, + result__h29673, + result__h29701, + result__h29729, + result__h29774, + result__h29802, + result__h29830, + result__h29858, + result__h29899, + result__h29927, + result__h29955, + result__h29983, + result__h30024, + result__h30052, + result__h30091, + result__h30119, + result__h8228, + w1___1__h19764, + w1___1__h28281, + w2___1__h28282, + w2__h28201, + word64__h7992, + x__h15854, + x__h28190, + y__h8264; + wire [31 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q25, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q32, + cache_rg_st_amo_val_BITS_31_TO_0__q1, + cline_addr__h22589, + ld_val5881_BITS_31_TO_0__q41, + ld_val5881_BITS_63_TO_32__q48, + new_value173_BITS_31_TO_0__q17, + w18195_BITS_31_TO_0__q54, + word64992_BITS_31_TO_0__q4, + word64992_BITS_63_TO_32__q11; + wire [21 : 0] pa_ctag__h7888; + wire [15 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q24, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q28, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q31, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q35, + ld_val5881_BITS_15_TO_0__q40, + ld_val5881_BITS_31_TO_16__q44, + ld_val5881_BITS_47_TO_32__q47, + ld_val5881_BITS_63_TO_48__q51, + word64992_BITS_15_TO_0__q3, + word64992_BITS_31_TO_16__q7, + word64992_BITS_47_TO_32__q10, + word64992_BITS_63_TO_48__q14; + wire [7 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q23, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q26, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q27, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q29, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q30, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q33, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q34, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q36, + ld_val5881_BITS_15_TO_8__q42, + ld_val5881_BITS_23_TO_16__q43, + ld_val5881_BITS_31_TO_24__q45, + ld_val5881_BITS_39_TO_32__q46, + ld_val5881_BITS_47_TO_40__q49, + ld_val5881_BITS_55_TO_48__q50, + ld_val5881_BITS_63_TO_56__q52, + ld_val5881_BITS_7_TO_0__q39, + strobe64__h5230, + strobe64__h5237, + strobe64__h5241, + word64992_BITS_15_TO_8__q5, + word64992_BITS_23_TO_16__q6, + word64992_BITS_31_TO_24__q8, + word64992_BITS_39_TO_32__q9, + word64992_BITS_47_TO_40__q12, + word64992_BITS_55_TO_48__q13, + word64992_BITS_63_TO_56__q15, + word64992_BITS_7_TO_0__q2; + wire [5 : 0] shift_bits__h5069; + wire [3 : 0] IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d347, + b__h22491; + wire IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d161, + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91, + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573, + NOT_cache_ram_state_and_ctag_cset_b_read__51_B_ETC___d186, + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d344, + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d513, + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528, + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d534, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d197, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d375, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d508, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d540, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d545, + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d373, + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d506, + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d526, + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d529, + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d532, + NOT_req_f3_BITS_1_TO_0_13_EQ_0b0_14_15_AND_NOT_ETC___d934, + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157, + cache_ram_state_and_ctag_cset_b_read__51_BIT_2_ETC___d187, + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184, + cache_rg_amo_funct7_32_BITS_6_TO_2_33_EQ_0b10__ETC___d363, + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d200, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d201, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d204, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d341, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d350, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d360, + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d198, + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d376, + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d509, + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d511, + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d366, + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d537, + cache_rg_state_7_EQ_12_15_AND_cache_rg_op_29_E_ETC___d617, + cache_rg_state_7_EQ_3_63_AND_NOT_cache_rg_op_2_ETC___d172, + lrsc_result__h15844, + req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943; + + // action method set_verbosity + assign RDY_set_verbosity = 1'd1 ; + assign CAN_FIRE_set_verbosity = 1'd1 ; + assign WILL_FIRE_set_verbosity = EN_set_verbosity ; + + // action method server_reset_request_put + assign RDY_server_reset_request_put = cache_f_reset_reqs$FULL_N ; + assign CAN_FIRE_server_reset_request_put = cache_f_reset_reqs$FULL_N ; + assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; + + // action method server_reset_response_get + assign RDY_server_reset_response_get = + !cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign CAN_FIRE_server_reset_response_get = + !cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; + + // action method req + assign CAN_FIRE_req = 1'd1 ; + assign WILL_FIRE_req = EN_req ; + + // value method valid + assign valid = cache_dw_valid$whas ; + + // value method addr + assign addr = cache_rg_addr ; + + // value method word64 + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_1 or + ld_val__h25881 or + MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + new_ld_val__h28161 or + MUX_cache_dw_output_ld_val$wset_1__SEL_3 or + MUX_cache_dw_output_ld_val$wset_1__VAL_3 or + MUX_cache_dw_output_ld_val$wset_1__SEL_4 or cache_rg_ld_val) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h25881; + MUX_cache_dw_output_ld_val$wset_1__SEL_2: word64 = new_ld_val__h28161; + MUX_cache_dw_output_ld_val$wset_1__SEL_3: + word64 = MUX_cache_dw_output_ld_val$wset_1__VAL_3; + MUX_cache_dw_output_ld_val$wset_1__SEL_4: word64 = cache_rg_ld_val; + default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // value method st_amo_val + assign st_amo_val = + MUX_cache_dw_output_ld_val$wset_1__SEL_3 ? + 64'd0 : + cache_rg_st_amo_val ; + + // value method exc + assign exc = cache_rg_state == 4'd4 ; + + // value method exc_code + assign exc_code = cache_rg_exc_code ; + + // action method server_flush_request_put + assign RDY_server_flush_request_put = cache_f_reset_reqs$FULL_N ; + assign CAN_FIRE_server_flush_request_put = cache_f_reset_reqs$FULL_N ; + assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; + + // action method server_flush_response_get + assign RDY_server_flush_response_get = + cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign CAN_FIRE_server_flush_response_get = + cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; + + // action method tlb_flush + assign RDY_tlb_flush = 1'd1 ; + assign CAN_FIRE_tlb_flush = 1'd1 ; + assign WILL_FIRE_tlb_flush = EN_tlb_flush ; + + // value method mem_master_aw_awid + assign mem_master_awid = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[97:93] ; + + // value method mem_master_aw_awaddr + assign mem_master_awaddr = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[92:29] ; + + // value method mem_master_aw_awlen + assign mem_master_awlen = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[28:21] ; + + // value method mem_master_aw_awsize + assign mem_master_awsize = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[20:18] ; + + // value method mem_master_aw_awburst + assign mem_master_awburst = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[17:16] ; + + // value method mem_master_aw_awlock + assign mem_master_awlock = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[15] ; + + // value method mem_master_aw_awcache + assign mem_master_awcache = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[14:11] ; + + // value method mem_master_aw_awprot + assign mem_master_awprot = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[10:8] ; + + // value method mem_master_aw_awqos + assign mem_master_awqos = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[7:4] ; + + // value method mem_master_aw_awregion + assign mem_master_awregion = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[3:0] ; + + // value method mem_master_aw_awvalid + assign mem_master_awvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek ; + + // action method mem_master_aw_awready + assign CAN_FIRE_mem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_mem_master_aw_awready = 1'd1 ; + + // value method mem_master_w_wdata + assign mem_master_wdata = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q21[72:9] ; + + // value method mem_master_w_wstrb + assign mem_master_wstrb = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q21[8:1] ; + + // value method mem_master_w_wlast + assign mem_master_wlast = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q21[0] ; + + // value method mem_master_w_wvalid + assign mem_master_wvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek ; + + // action method mem_master_w_wready + assign CAN_FIRE_mem_master_w_wready = 1'd1 ; + assign WILL_FIRE_mem_master_w_wready = 1'd1 ; + + // action method mem_master_b_bflit + assign CAN_FIRE_mem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_mem_master_b_bflit = mem_master_bvalid ; + + // value method mem_master_b_bready + assign mem_master_bready = !cache_master_xactor_shim_bff_rv[7] ; + + // value method mem_master_ar_arid + assign mem_master_arid = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[97:93] ; + + // value method mem_master_ar_araddr + assign mem_master_araddr = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[92:29] ; + + // value method mem_master_ar_arlen + assign mem_master_arlen = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[28:21] ; + + // value method mem_master_ar_arsize + assign mem_master_arsize = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[20:18] ; + + // value method mem_master_ar_arburst + assign mem_master_arburst = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[17:16] ; + + // value method mem_master_ar_arlock + assign mem_master_arlock = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[15] ; + + // value method mem_master_ar_arcache + assign mem_master_arcache = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[14:11] ; + + // value method mem_master_ar_arprot + assign mem_master_arprot = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[10:8] ; + + // value method mem_master_ar_arqos + assign mem_master_arqos = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[7:4] ; + + // value method mem_master_ar_arregion + assign mem_master_arregion = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[3:0] ; + + // value method mem_master_ar_arvalid + assign mem_master_arvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek ; + + // action method mem_master_ar_arready + assign CAN_FIRE_mem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_mem_master_ar_arready = 1'd1 ; + + // action method mem_master_r_rflit + assign CAN_FIRE_mem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_mem_master_r_rflit = mem_master_rvalid ; + + // value method mem_master_r_rready + assign mem_master_rready = !cache_master_xactor_shim_rff_rv[72] ; + + // submodule cache_f_fabric_write_reqs + FIFO2 #(.width(32'd99), + .guarded(32'd1)) cache_f_fabric_write_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_fabric_write_reqs$D_IN), + .ENQ(cache_f_fabric_write_reqs$ENQ), + .DEQ(cache_f_fabric_write_reqs$DEQ), + .CLR(cache_f_fabric_write_reqs$CLR), + .D_OUT(cache_f_fabric_write_reqs$D_OUT), + .FULL_N(cache_f_fabric_write_reqs$FULL_N), + .EMPTY_N(cache_f_fabric_write_reqs$EMPTY_N)); + + // submodule cache_f_reset_reqs + FIFO2 #(.width(32'd1), .guarded(32'd1)) cache_f_reset_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_reset_reqs$D_IN), + .ENQ(cache_f_reset_reqs$ENQ), + .DEQ(cache_f_reset_reqs$DEQ), + .CLR(cache_f_reset_reqs$CLR), + .D_OUT(cache_f_reset_reqs$D_OUT), + .FULL_N(cache_f_reset_reqs$FULL_N), + .EMPTY_N(cache_f_reset_reqs$EMPTY_N)); + + // submodule cache_f_reset_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) cache_f_reset_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_reset_rsps$D_IN), + .ENQ(cache_f_reset_rsps$ENQ), + .DEQ(cache_f_reset_rsps$DEQ), + .CLR(cache_f_reset_rsps$CLR), + .D_OUT(cache_f_reset_rsps$D_OUT), + .FULL_N(cache_f_reset_rsps$FULL_N), + .EMPTY_N(cache_f_reset_rsps$EMPTY_N)); + + // submodule cache_ram_state_and_ctag_cset + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd7), + .DATA_WIDTH(32'd23), + .MEMSIZE(8'd128)) cache_ram_state_and_ctag_cset(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(cache_ram_state_and_ctag_cset$ADDRA), + .ADDRB(cache_ram_state_and_ctag_cset$ADDRB), + .DIA(cache_ram_state_and_ctag_cset$DIA), + .DIB(cache_ram_state_and_ctag_cset$DIB), + .WEA(cache_ram_state_and_ctag_cset$WEA), + .WEB(cache_ram_state_and_ctag_cset$WEB), + .ENA(cache_ram_state_and_ctag_cset$ENA), + .ENB(cache_ram_state_and_ctag_cset$ENB), + .DOA(), + .DOB(cache_ram_state_and_ctag_cset$DOB)); + + // submodule cache_ram_word64_set + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd9), + .DATA_WIDTH(32'd64), + .MEMSIZE(10'd512)) cache_ram_word64_set(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(cache_ram_word64_set$ADDRA), + .ADDRB(cache_ram_word64_set$ADDRB), + .DIA(cache_ram_word64_set$DIA), + .DIB(cache_ram_word64_set$DIB), + .WEA(cache_ram_word64_set$WEA), + .WEB(cache_ram_word64_set$WEB), + .ENA(cache_ram_word64_set$ENA), + .ENB(cache_ram_word64_set$ENB), + .DOA(), + .DOB(cache_ram_word64_set$DOB)); + + // submodule cache_soc_map + mkSoC_Map cache_soc_map(.CLK(CLK), + .RST_N(RST_N), + .m_is_IO_addr_addr(cache_soc_map$m_is_IO_addr_addr), + .m_is_mem_addr_addr(cache_soc_map$m_is_mem_addr_addr), + .m_is_near_mem_IO_addr_addr(cache_soc_map$m_is_near_mem_IO_addr_addr), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), + .m_is_mem_addr(), + .m_is_IO_addr(), + .m_is_near_mem_IO_addr(), + .m_pc_reset_value(), + .m_mtvec_reset_value(), + .m_nmivec_reset_value()); + + // rule RL_cache_rl_fabric_send_write_req + assign CAN_FIRE_RL_cache_rl_fabric_send_write_req = + !cache_master_xactor_clearing && + cache_f_fabric_write_reqs$EMPTY_N && + !cache_master_xactor_shim_awff_rv[98] && + !cache_master_xactor_shim_wff_rv[73] ; + assign WILL_FIRE_RL_cache_rl_fabric_send_write_req = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ; + + // rule RL_cache_rl_reset + assign CAN_FIRE_RL_cache_rl_reset = + (cache_rg_cset_in_cache != 7'd127 || + cache_f_reset_reqs$EMPTY_N && cache_f_reset_rsps$FULL_N) && + cache_rg_state == 4'd1 ; + assign WILL_FIRE_RL_cache_rl_reset = CAN_FIRE_RL_cache_rl_reset ; + + // rule RL_cache_rl_shift_sb_to_load_delay + assign CAN_FIRE_RL_cache_rl_shift_sb_to_load_delay = 1'd1 ; + assign WILL_FIRE_RL_cache_rl_shift_sb_to_load_delay = 1'd1 ; + + // rule RL_cache_rl_probe_and_immed_rsp + assign CAN_FIRE_RL_cache_rl_probe_and_immed_rsp = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010 || + IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d161) && + cache_rg_state_7_EQ_3_63_AND_NOT_cache_rg_op_2_ETC___d172 ; + assign WILL_FIRE_RL_cache_rl_probe_and_immed_rsp = + CAN_FIRE_RL_cache_rl_probe_and_immed_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_start_cache_refill + assign CAN_FIRE_RL_cache_rl_start_cache_refill = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[98] && + cache_rg_state == 4'd8 && + b__h22491 == 4'd0 ; + assign WILL_FIRE_RL_cache_rl_start_cache_refill = + CAN_FIRE_RL_cache_rl_start_cache_refill && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_rereq + assign CAN_FIRE_RL_cache_rl_rereq = cache_rg_state == 4'd10 ; + assign WILL_FIRE_RL_cache_rl_rereq = + CAN_FIRE_RL_cache_rl_rereq && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_ST_AMO_response + assign CAN_FIRE_RL_cache_rl_ST_AMO_response = cache_rg_state == 4'd11 ; + assign WILL_FIRE_RL_cache_rl_ST_AMO_response = + CAN_FIRE_RL_cache_rl_ST_AMO_response ; + + // rule RL_cache_rl_io_read_req + assign CAN_FIRE_RL_cache_rl_io_read_req = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[98] && + cache_rg_state_7_EQ_12_15_AND_cache_rg_op_29_E_ETC___d617 ; + assign WILL_FIRE_RL_cache_rl_io_read_req = + CAN_FIRE_RL_cache_rl_io_read_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_maintain_io_read_rsp + assign CAN_FIRE_RL_cache_rl_maintain_io_read_rsp = cache_rg_state == 4'd14 ; + assign WILL_FIRE_RL_cache_rl_maintain_io_read_rsp = + CAN_FIRE_RL_cache_rl_maintain_io_read_rsp ; + + // rule RL_cache_rl_io_write_req + assign CAN_FIRE_RL_cache_rl_io_write_req = + cache_f_fabric_write_reqs$FULL_N && cache_rg_state == 4'd12 && + cache_rg_op == 2'd1 ; + assign WILL_FIRE_RL_cache_rl_io_write_req = + CAN_FIRE_RL_cache_rl_io_write_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_SC_req + assign CAN_FIRE_RL_cache_rl_io_AMO_SC_req = + cache_rg_state == 4'd12 && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_SC_req = + CAN_FIRE_RL_cache_rl_io_AMO_SC_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_op_req + assign CAN_FIRE_RL_cache_rl_io_AMO_op_req = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[98] && + cache_rg_state == 4'd12 && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] != 5'b00010 && + cache_rg_amo_funct7[6:2] != 5'b00011 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_op_req = + CAN_FIRE_RL_cache_rl_io_AMO_op_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_drive_exception_rsp + assign CAN_FIRE_RL_cache_rl_drive_exception_rsp = cache_rg_state == 4'd4 ; + assign WILL_FIRE_RL_cache_rl_drive_exception_rsp = cache_rg_state == 4'd4 ; + + // rule RL_cache_master_xactor_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek = + cache_master_xactor_shim_awff_rv$port1__read[98] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop = + cache_master_xactor_ug_master_u_aw_dropWire$whas && + !cache_master_xactor_shim_awff_rv$port1__read[98] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop = + cache_master_xactor_shim_awff_rv$port1__read[98] && + cache_master_xactor_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_w_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek = + cache_master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop = + cache_master_xactor_ug_master_u_w_dropWire$whas && + !cache_master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_w_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop = + cache_master_xactor_shim_wff_rv$port1__read[73] && + cache_master_xactor_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut = + cache_master_xactor_ug_master_u_b_putWire$whas && + cache_master_xactor_shim_bff_rv[7] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut ; + + // rule RL_cache_master_xactor_ug_master_u_b_doPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut = + !cache_master_xactor_shim_bff_rv[7] && + cache_master_xactor_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut ; + + // rule RL_cache_rl_discard_write_rsp + assign CAN_FIRE_RL_cache_rl_discard_write_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_bff_rv$port1__read[7] && + b__h22491 != 4'd0 ; + assign WILL_FIRE_RL_cache_rl_discard_write_rsp = + CAN_FIRE_RL_cache_rl_discard_write_rsp ; + + // rule RL_cache_rl_start_reset + assign CAN_FIRE_RL_cache_rl_start_reset = + cache_f_reset_reqs$EMPTY_N && + (cache_f_reset_reqs$D_OUT || !cache_master_xactor_clearing) && + cache_rg_state != 4'd1 ; + assign WILL_FIRE_RL_cache_rl_start_reset = + CAN_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_master_xactor_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek = + cache_master_xactor_shim_arff_rv$port1__read[98] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop = + cache_master_xactor_ug_master_u_ar_dropWire$whas && + !cache_master_xactor_shim_arff_rv$port1__read[98] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop = + cache_master_xactor_shim_arff_rv$port1__read[98] && + cache_master_xactor_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut = + cache_master_xactor_ug_master_u_r_putWire$whas && + cache_master_xactor_shim_rff_rv[72] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut ; + + // rule RL_cache_master_xactor_ug_master_u_r_doPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut = + !cache_master_xactor_shim_rff_rv[72] && + cache_master_xactor_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut ; + + // rule RL_cache_rl_cache_refill_rsps_loop + assign CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[72] && + cache_rg_state == 4'd9 ; + assign WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop = + CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_io_read_rsp + assign CAN_FIRE_RL_cache_rl_io_read_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[72] && + cache_rg_state == 4'd13 ; + assign WILL_FIRE_RL_cache_rl_io_read_rsp = + CAN_FIRE_RL_cache_rl_io_read_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_read_rsp + assign CAN_FIRE_RL_cache_rl_io_AMO_read_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[72] && + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_f_fabric_write_reqs$FULL_N) && + cache_rg_state == 4'd15 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_read_rsp = + CAN_FIRE_RL_cache_rl_io_AMO_read_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_master_xactor_do_clear + assign CAN_FIRE_RL_cache_master_xactor_do_clear = + cache_master_xactor_clearing ; + assign WILL_FIRE_RL_cache_master_xactor_do_clear = + cache_master_xactor_clearing ; + + // inputs to muxes for submodule ports + assign MUX_cache_dw_output_ld_val$wset_1__SEL_1 = + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_2 = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_3 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d204 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_4 = + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp || + WILL_FIRE_RL_cache_rl_ST_AMO_response ; + assign MUX_cache_f_fabric_write_reqs$enq_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d513 ; + assign MUX_cache_master_xactor_clearing$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_start_reset && !cache_f_reset_reqs$D_OUT ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1 = + WILL_FIRE_RL_cache_rl_io_AMO_op_req || + WILL_FIRE_RL_cache_rl_io_read_req ; + assign MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 = + EN_req && + req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943 ; + assign MUX_cache_ram_word64_set$a_put_1__SEL_1 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_ram_word64_set$b_put_1__SEL_2 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 ; + assign MUX_cache_rg_error_during_refill$write_1__SEL_1 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_exc_code$write_1__SEL_1 = + EN_req && + NOT_req_f3_BITS_1_TO_0_13_EQ_0b0_14_15_AND_NOT_ETC___d934 ; + assign MUX_cache_rg_exc_code$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_exc_code$write_1__SEL_3 = + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_ld_val$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d366 ; + assign MUX_cache_rg_lrsc_valid$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d200 ; + assign MUX_cache_rg_state$write_1__SEL_4 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 ; + assign MUX_cache_rg_state$write_1__SEL_12 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + (cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d341 || + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d344) ; + assign MUX_cache_rg_state$write_1__SEL_13 = + WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 ; + assign MUX_cache_dw_output_ld_val$wset_1__VAL_3 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) ? + new_value__h8173 : + new_value__h18271 ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_1 = + { cache_rg_f3, cache_rg_pa, x__h28190 } ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_2 = + { cache_rg_f3, + cache_rg_addr, + IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d514 } ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_3 = + { cache_rg_f3, cache_rg_pa, cache_rg_st_amo_val } ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1 = + { 6'd32, + fabric_addr__h27561, + 8'd0, + size_val__h27675, + 18'd65536 } ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2 = + { 6'd32, cline_fabric_addr__h22590, 29'd7143424 } ; + assign MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1 = + { 3'd4, cache_rg_pa[31:12] } ; + assign MUX_cache_ram_word64_set$a_put_3__VAL_2 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 : + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 ; + assign MUX_cache_ram_word64_set$b_put_2__VAL_2 = + cache_rg_word64_set_in_cache + 9'd1 ; + assign MUX_cache_ram_word64_set$b_put_2__VAL_4 = + { cache_rg_addr[11:5], 2'd0 } ; + assign MUX_cache_rg_cset_in_cache$write_1__VAL_1 = + cache_rg_cset_in_cache + 7'd1 ; + assign MUX_cache_rg_exc_code$write_1__VAL_1 = + (req_op == 2'd0) ? 4'd4 : 4'd6 ; + assign MUX_cache_rg_ld_val$write_1__VAL_2 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + x__h15854 : + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 ; + assign MUX_cache_rg_state$write_1__VAL_1 = + NOT_req_f3_BITS_1_TO_0_13_EQ_0b0_14_15_AND_NOT_ETC___d934 ? + 4'd4 : + 4'd3 ; + assign MUX_cache_rg_state$write_1__VAL_2 = + (cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) ? + 4'd14 : + 4'd4 ; + assign MUX_cache_rg_state$write_1__VAL_4 = + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_rg_error_during_refill) ? + 4'd4 : + 4'd10 ; + assign MUX_cache_rg_state$write_1__VAL_12 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) ? + 4'd8 : + IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d347 ; + + // inlined wires + assign cache_master_xactor_ug_master_u_b_putWire$wget = + { mem_master_bid, mem_master_bresp } ; + assign cache_master_xactor_ug_master_u_b_putWire$whas = + mem_master_bvalid && !cache_master_xactor_shim_bff_rv[7] ; + assign cache_master_xactor_ug_master_u_r_putWire$wget = + { mem_master_rid, + mem_master_rdata, + mem_master_rresp, + mem_master_rlast } ; + assign cache_master_xactor_ug_master_u_r_putWire$whas = + mem_master_rvalid && !cache_master_xactor_shim_rff_rv[72] ; + assign cache_dw_valid$whas = + (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp) && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d204 || + WILL_FIRE_RL_cache_rl_drive_exception_rsp || + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp || + WILL_FIRE_RL_cache_rl_ST_AMO_response ; + assign cache_master_xactor_ug_master_u_aw_dropWire$whas = + cache_master_xactor_shim_awff_rv$port1__read[98] && + mem_master_awready ; + assign cache_master_xactor_ug_master_u_w_dropWire$whas = + cache_master_xactor_shim_wff_rv$port1__read[73] && + mem_master_wready ; + assign cache_master_xactor_ug_master_u_ar_dropWire$whas = + cache_master_xactor_shim_arff_rv$port1__read[98] && + mem_master_arready ; + assign cache_master_xactor_shim_awff_rv$port0__write_1 = + { 6'd32, + mem_req_wr_addr_awaddr__h5054, + 8'd0, + _theResult___snd_snd_val__h5250, + 18'd65536 } ; + assign cache_master_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_master_xactor_shim_awff_rv$port0__write_1 : + cache_master_xactor_shim_awff_rv ; + assign cache_master_xactor_shim_awff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_awff_rv$port1__read ; + assign cache_master_xactor_shim_awff_rv$port3__read = + cache_master_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_awff_rv$port2__read ; + assign cache_master_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, + mem_req_wr_data_wdata__h5366, + mem_req_wr_data_wstrb__h5367, + 1'd1 } ; + assign cache_master_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_master_xactor_shim_wff_rv$port0__write_1 : + cache_master_xactor_shim_wff_rv ; + assign cache_master_xactor_shim_wff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_wff_rv$port1__read ; + assign cache_master_xactor_shim_wff_rv$port3__read = + cache_master_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_wff_rv$port2__read ; + assign cache_master_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, cache_master_xactor_ug_master_u_b_putWire$wget } ; + assign cache_master_xactor_shim_bff_rv$port1__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut ? + cache_master_xactor_shim_bff_rv$port0__write_1 : + cache_master_xactor_shim_bff_rv ; + assign cache_master_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_cache_rl_discard_write_rsp ? + 8'd42 : + cache_master_xactor_shim_bff_rv$port1__read ; + assign cache_master_xactor_shim_bff_rv$port3__read = + cache_master_xactor_clearing ? + 8'd42 : + cache_master_xactor_shim_bff_rv$port2__read ; + assign cache_master_xactor_shim_arff_rv$EN_port0__write = + WILL_FIRE_RL_cache_rl_io_AMO_op_req || + WILL_FIRE_RL_cache_rl_io_read_req || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + assign cache_master_xactor_shim_arff_rv$port0__write_1 = + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1 : + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2 ; + assign cache_master_xactor_shim_arff_rv$port1__read = + cache_master_xactor_shim_arff_rv$EN_port0__write ? + cache_master_xactor_shim_arff_rv$port0__write_1 : + cache_master_xactor_shim_arff_rv ; + assign cache_master_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_arff_rv$port1__read ; + assign cache_master_xactor_shim_arff_rv$port3__read = + cache_master_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_arff_rv$port2__read ; + assign cache_master_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, cache_master_xactor_ug_master_u_r_putWire$wget } ; + assign cache_master_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut ? + cache_master_xactor_shim_rff_rv$port0__write_1 : + cache_master_xactor_shim_rff_rv ; + assign cache_master_xactor_shim_rff_rv$EN_port1__write = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop ; + assign cache_master_xactor_shim_rff_rv$port2__read = + cache_master_xactor_shim_rff_rv$EN_port1__write ? + 73'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_rff_rv$port1__read ; + assign cache_master_xactor_shim_rff_rv$port3__read = + cache_master_xactor_clearing ? + 73'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_rff_rv$port2__read ; + assign cache_ctr_wr_rsps_pending_crg$port0__write_1 = + cache_ctr_wr_rsps_pending_crg + 4'd1 ; + assign cache_ctr_wr_rsps_pending_crg$port1__write_1 = b__h22491 - 4'd1 ; + assign cache_ctr_wr_rsps_pending_crg$port2__read = + CAN_FIRE_RL_cache_rl_discard_write_rsp ? + cache_ctr_wr_rsps_pending_crg$port1__write_1 : + b__h22491 ; + assign cache_ctr_wr_rsps_pending_crg$port3__read = + MUX_cache_master_xactor_clearing$write_1__SEL_2 ? + 4'd0 : + cache_ctr_wr_rsps_pending_crg$port2__read ; + assign cache_crg_sb_to_load_delay$port0__write_1 = + { 1'd0, cache_crg_sb_to_load_delay[10:1] } ; + assign cache_crg_sb_to_load_delay$EN_port1__write = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d509 ; + assign cache_crg_sb_to_load_delay$port2__read = + cache_crg_sb_to_load_delay$EN_port1__write ? + 11'd2047 : + cache_crg_sb_to_load_delay$port0__write_1 ; + + // register cache_cfg_verbosity + assign cache_cfg_verbosity$D_IN = set_verbosity_verbosity ; + assign cache_cfg_verbosity$EN = EN_set_verbosity ; + + // register cache_crg_sb_to_load_delay + assign cache_crg_sb_to_load_delay$D_IN = + cache_crg_sb_to_load_delay$port2__read ; + assign cache_crg_sb_to_load_delay$EN = 1'b1 ; + + // register cache_ctr_wr_rsps_pending_crg + assign cache_ctr_wr_rsps_pending_crg$D_IN = + cache_ctr_wr_rsps_pending_crg$port3__read ; + assign cache_ctr_wr_rsps_pending_crg$EN = 1'b1 ; + + // register cache_master_xactor_clearing + assign cache_master_xactor_clearing$D_IN = !cache_master_xactor_clearing ; + assign cache_master_xactor_clearing$EN = + WILL_FIRE_RL_cache_rl_start_reset && !cache_f_reset_reqs$D_OUT || + cache_master_xactor_clearing ; + + // register cache_master_xactor_shim_arff_rv + assign cache_master_xactor_shim_arff_rv$D_IN = + cache_master_xactor_shim_arff_rv$port3__read ; + assign cache_master_xactor_shim_arff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_awff_rv + assign cache_master_xactor_shim_awff_rv$D_IN = + cache_master_xactor_shim_awff_rv$port3__read ; + assign cache_master_xactor_shim_awff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_bff_rv + assign cache_master_xactor_shim_bff_rv$D_IN = + cache_master_xactor_shim_bff_rv$port3__read ; + assign cache_master_xactor_shim_bff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_rff_rv + assign cache_master_xactor_shim_rff_rv$D_IN = + cache_master_xactor_shim_rff_rv$port3__read ; + assign cache_master_xactor_shim_rff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_wff_rv + assign cache_master_xactor_shim_wff_rv$D_IN = + cache_master_xactor_shim_wff_rv$port3__read ; + assign cache_master_xactor_shim_wff_rv$EN = 1'b1 ; + + // register cache_rg_addr + assign cache_rg_addr$D_IN = req_addr ; + assign cache_rg_addr$EN = EN_req ; + + // register cache_rg_amo_funct7 + assign cache_rg_amo_funct7$D_IN = req_amo_funct7 ; + assign cache_rg_amo_funct7$EN = EN_req ; + + // register cache_rg_cset_in_cache + assign cache_rg_cset_in_cache$D_IN = + WILL_FIRE_RL_cache_rl_reset ? + MUX_cache_rg_cset_in_cache$write_1__VAL_1 : + 7'd0 ; + assign cache_rg_cset_in_cache$EN = + WILL_FIRE_RL_cache_rl_reset || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_error_during_refill + assign cache_rg_error_during_refill$D_IN = + MUX_cache_rg_error_during_refill$write_1__SEL_1 ; + assign cache_rg_error_during_refill$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // register cache_rg_exc_code + always@(MUX_cache_rg_exc_code$write_1__SEL_1 or + MUX_cache_rg_exc_code$write_1__VAL_1 or + MUX_cache_rg_exc_code$write_1__SEL_2 or + MUX_cache_rg_exc_code$write_1__SEL_3 or + MUX_cache_rg_error_during_refill$write_1__SEL_1) + case (1'b1) + MUX_cache_rg_exc_code$write_1__SEL_1: + cache_rg_exc_code$D_IN = MUX_cache_rg_exc_code$write_1__VAL_1; + MUX_cache_rg_exc_code$write_1__SEL_2: cache_rg_exc_code$D_IN = 4'd7; + MUX_cache_rg_exc_code$write_1__SEL_3: cache_rg_exc_code$D_IN = 4'd5; + MUX_cache_rg_error_during_refill$write_1__SEL_1: + cache_rg_exc_code$D_IN = 4'd1; + default: cache_rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; + endcase + assign cache_rg_exc_code$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + EN_req && + NOT_req_f3_BITS_1_TO_0_13_EQ_0b0_14_15_AND_NOT_ETC___d934 ; + + // register cache_rg_f3 + assign cache_rg_f3$D_IN = req_f3 ; + assign cache_rg_f3$EN = EN_req ; + + // register cache_rg_ld_val + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + new_ld_val__h28161 or + MUX_cache_rg_ld_val$write_1__SEL_2 or + MUX_cache_rg_ld_val$write_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_read_rsp or + ld_val__h25881 or WILL_FIRE_RL_cache_rl_io_AMO_SC_req) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_2: + cache_rg_ld_val$D_IN = new_ld_val__h28161; + MUX_cache_rg_ld_val$write_1__SEL_2: + cache_rg_ld_val$D_IN = MUX_cache_rg_ld_val$write_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_read_rsp: + cache_rg_ld_val$D_IN = ld_val__h25881; + WILL_FIRE_RL_cache_rl_io_AMO_SC_req: cache_rg_ld_val$D_IN = 64'd1; + default: cache_rg_ld_val$D_IN = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_rg_ld_val$EN = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d366 || + WILL_FIRE_RL_cache_rl_io_read_rsp || + WILL_FIRE_RL_cache_rl_io_AMO_SC_req ; + + // register cache_rg_lower_word32 + assign cache_rg_lower_word32$D_IN = 32'h0 ; + assign cache_rg_lower_word32$EN = 1'b0 ; + + // register cache_rg_lower_word32_full + assign cache_rg_lower_word32_full$D_IN = 1'd0 ; + assign cache_rg_lower_word32_full$EN = + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_lrsc_pa + assign cache_rg_lrsc_pa$D_IN = cache_rg_addr ; + assign cache_rg_lrsc_pa$EN = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 ; + + // register cache_rg_lrsc_valid + assign cache_rg_lrsc_valid$D_IN = + MUX_cache_rg_lrsc_valid$write_1__SEL_2 && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d201 ; + assign cache_rg_lrsc_valid$EN = + WILL_FIRE_RL_cache_rl_io_read_req && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d200 || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_op + assign cache_rg_op$D_IN = req_op ; + assign cache_rg_op$EN = EN_req ; + + // register cache_rg_pa + assign cache_rg_pa$D_IN = EN_req ? req_addr : cache_rg_addr ; + assign cache_rg_pa$EN = + EN_req || WILL_FIRE_RL_cache_rl_probe_and_immed_rsp ; + + // register cache_rg_pte_pa + assign cache_rg_pte_pa$D_IN = 32'h0 ; + assign cache_rg_pte_pa$EN = 1'b0 ; + + // register cache_rg_st_amo_val + assign cache_rg_st_amo_val$D_IN = + EN_req ? req_st_value : new_st_val__h19402 ; + assign cache_rg_st_amo_val$EN = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d375 || + EN_req ; + + // register cache_rg_state + always@(EN_req or + MUX_cache_rg_state$write_1__VAL_1 or + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp or + MUX_cache_rg_state$write_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_read_rsp or + MUX_cache_rg_state$write_1__SEL_4 or + MUX_cache_rg_state$write_1__VAL_4 or + WILL_FIRE_RL_cache_rl_start_reset or + WILL_FIRE_RL_cache_rl_io_AMO_op_req or + WILL_FIRE_RL_cache_rl_io_AMO_SC_req or + WILL_FIRE_RL_cache_rl_io_write_req or + WILL_FIRE_RL_cache_rl_io_read_req or + WILL_FIRE_RL_cache_rl_rereq or + WILL_FIRE_RL_cache_rl_start_cache_refill or + MUX_cache_rg_state$write_1__SEL_12 or + MUX_cache_rg_state$write_1__VAL_12 or + MUX_cache_rg_state$write_1__SEL_13) + case (1'b1) + EN_req: cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_1; + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_read_rsp: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_2; + MUX_cache_rg_state$write_1__SEL_4: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_4; + WILL_FIRE_RL_cache_rl_start_reset: cache_rg_state$D_IN = 4'd1; + WILL_FIRE_RL_cache_rl_io_AMO_op_req: cache_rg_state$D_IN = 4'd15; + WILL_FIRE_RL_cache_rl_io_AMO_SC_req || WILL_FIRE_RL_cache_rl_io_write_req: + cache_rg_state$D_IN = 4'd11; + WILL_FIRE_RL_cache_rl_io_read_req: cache_rg_state$D_IN = 4'd13; + WILL_FIRE_RL_cache_rl_rereq: cache_rg_state$D_IN = 4'd3; + WILL_FIRE_RL_cache_rl_start_cache_refill: cache_rg_state$D_IN = 4'd9; + MUX_cache_rg_state$write_1__SEL_12: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_12; + MUX_cache_rg_state$write_1__SEL_13: cache_rg_state$D_IN = 4'd2; + default: cache_rg_state$D_IN = 4'b1010 /* unspecified value */ ; + endcase + assign cache_rg_state$EN = + WILL_FIRE_RL_cache_rl_reset && + cache_rg_cset_in_cache == 7'd127 || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + (cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d341 || + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d344) || + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp || + EN_req || + WILL_FIRE_RL_cache_rl_start_reset || + WILL_FIRE_RL_cache_rl_rereq || + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_io_AMO_SC_req || + WILL_FIRE_RL_cache_rl_io_write_req || + WILL_FIRE_RL_cache_rl_io_read_req || + WILL_FIRE_RL_cache_rl_io_AMO_op_req ; + + // register cache_rg_word64_set_in_cache + assign cache_rg_word64_set_in_cache$D_IN = + MUX_cache_ram_word64_set$b_put_1__SEL_2 ? + MUX_cache_ram_word64_set$b_put_2__VAL_2 : + MUX_cache_ram_word64_set$b_put_2__VAL_4 ; + assign cache_rg_word64_set_in_cache$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // submodule cache_f_fabric_write_reqs + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_1 or + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2 or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_write_req or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_2: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_1; + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_write_req: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3; + default: cache_f_fabric_write_reqs$D_IN = + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_f_fabric_write_reqs$ENQ = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d513 || + WILL_FIRE_RL_cache_rl_io_write_req ; + assign cache_f_fabric_write_reqs$DEQ = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ; + assign cache_f_fabric_write_reqs$CLR = 1'b0 ; + + // submodule cache_f_reset_reqs + assign cache_f_reset_reqs$D_IN = !EN_server_reset_request_put ; + assign cache_f_reset_reqs$ENQ = + EN_server_reset_request_put || EN_server_flush_request_put ; + assign cache_f_reset_reqs$DEQ = MUX_cache_rg_state$write_1__SEL_13 ; + assign cache_f_reset_reqs$CLR = 1'b0 ; + + // submodule cache_f_reset_rsps + assign cache_f_reset_rsps$D_IN = cache_f_reset_reqs$D_OUT ; + assign cache_f_reset_rsps$ENQ = MUX_cache_rg_state$write_1__SEL_13 ; + assign cache_f_reset_rsps$DEQ = + EN_server_flush_response_get || EN_server_reset_response_get ; + assign cache_f_reset_rsps$CLR = 1'b0 ; + + // submodule cache_ram_state_and_ctag_cset + assign cache_ram_state_and_ctag_cset$ADDRA = + WILL_FIRE_RL_cache_rl_start_cache_refill ? + cache_rg_addr[11:5] : + cache_rg_cset_in_cache ; + assign cache_ram_state_and_ctag_cset$ADDRB = + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 ? + req_addr[11:5] : + cache_rg_addr[11:5] ; + assign cache_ram_state_and_ctag_cset$DIA = + WILL_FIRE_RL_cache_rl_start_cache_refill ? + MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1 : + 23'd2796202 ; + assign cache_ram_state_and_ctag_cset$DIB = + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 ? + 23'b01010101010101010101010 /* unspecified value */ : + 23'b01010101010101010101010 /* unspecified value */ ; + assign cache_ram_state_and_ctag_cset$WEA = 1'd1 ; + assign cache_ram_state_and_ctag_cset$WEB = 1'd0 ; + assign cache_ram_state_and_ctag_cset$ENA = + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_reset ; + assign cache_ram_state_and_ctag_cset$ENB = + EN_req && + req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943 || + WILL_FIRE_RL_cache_rl_rereq ; + + // submodule cache_ram_word64_set + assign cache_ram_word64_set$ADDRA = + MUX_cache_ram_word64_set$a_put_1__SEL_1 ? + cache_rg_word64_set_in_cache : + cache_rg_addr[11:3] ; + always@(MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 or + req_addr or + MUX_cache_ram_word64_set$b_put_1__SEL_2 or + MUX_cache_ram_word64_set$b_put_2__VAL_2 or + WILL_FIRE_RL_cache_rl_rereq or + cache_rg_addr or + WILL_FIRE_RL_cache_rl_start_cache_refill or + MUX_cache_ram_word64_set$b_put_2__VAL_4) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1: + cache_ram_word64_set$ADDRB = req_addr[11:3]; + MUX_cache_ram_word64_set$b_put_1__SEL_2: + cache_ram_word64_set$ADDRB = + MUX_cache_ram_word64_set$b_put_2__VAL_2; + WILL_FIRE_RL_cache_rl_rereq: + cache_ram_word64_set$ADDRB = cache_rg_addr[11:3]; + WILL_FIRE_RL_cache_rl_start_cache_refill: + cache_ram_word64_set$ADDRB = + MUX_cache_ram_word64_set$b_put_2__VAL_4; + default: cache_ram_word64_set$ADDRB = + 9'b010101010 /* unspecified value */ ; + endcase + end + assign cache_ram_word64_set$DIA = + MUX_cache_ram_word64_set$a_put_1__SEL_1 ? + cache_master_xactor_shim_rff_rv$port1__read[66:3] : + MUX_cache_ram_word64_set$a_put_3__VAL_2 ; + always@(MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 or + MUX_cache_ram_word64_set$b_put_1__SEL_2 or + WILL_FIRE_RL_cache_rl_rereq or + WILL_FIRE_RL_cache_rl_start_cache_refill) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_cache_ram_word64_set$b_put_1__SEL_2: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + WILL_FIRE_RL_cache_rl_rereq: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + WILL_FIRE_RL_cache_rl_start_cache_refill: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + default: cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_ram_word64_set$WEA = 1'd1 ; + assign cache_ram_word64_set$WEB = 1'd0 ; + assign cache_ram_word64_set$ENA = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d376 ; + assign cache_ram_word64_set$ENB = + EN_req && + req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943 || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 || + WILL_FIRE_RL_cache_rl_rereq || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // submodule cache_soc_map + assign cache_soc_map$m_is_IO_addr_addr = 64'h0 ; + assign cache_soc_map$m_is_mem_addr_addr = 64'h0 ; + assign cache_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; + + // remaining internal signals + assign IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324 = + (cache_rg_addr[2:0] == 3'h0) ? word64__h7992 : 64'd0 ; + assign IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d338 = + (cache_rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; + assign IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821 = + (cache_rg_addr[2:0] == 3'h0) ? ld_val__h25881 : 64'd0 ; + assign IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 = + (cache_rg_f3 == 3'b010) ? b__h30158 : cache_rg_st_amo_val ; + assign IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d161 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15844 || + cache_f_fabric_write_reqs$FULL_N : + !cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 || + cache_f_fabric_write_reqs$FULL_N ; + assign IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d347 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + 4'd11 : + ((!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) ? + 4'd8 : + 4'd11) ; + assign IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d514 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + cache_rg_st_amo_val : + new_st_val__h19402 ; + assign NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 = + cache_cfg_verbosity > 4'd1 ; + assign NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 = + cache_cfg_verbosity > 4'd2 ; + assign NOT_cache_ram_state_and_ctag_cset_b_read__51_B_ETC___d186 = + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 ; + assign NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d344 = + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) ; + assign NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d513 = + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d511 || + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d375) ; + assign NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d526 ; + assign NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d534 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d532 ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d197 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d375 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d508 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + (cache_rg_f3 == 3'b0 || cache_rg_f3 == 3'b001) ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d540 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d545 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d373 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 ; + assign NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d506 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + (cache_rg_f3 == 3'b0 || cache_rg_f3 == 3'b001) ; + assign NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d526 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d529 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d532 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_req_f3_BITS_1_TO_0_13_EQ_0b0_14_15_AND_NOT_ETC___d934 = + req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && + (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && + (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; + assign _theResult___fst__h5232 = + cache_f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h5069 ; + assign b__h19806 = + { {32{new_value173_BITS_31_TO_0__q17[31]}}, + new_value173_BITS_31_TO_0__q17 } ; + assign b__h22491 = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_ctr_wr_rsps_pending_crg$port0__write_1 : + cache_ctr_wr_rsps_pending_crg ; + assign b__h28323 = + { {32{w18195_BITS_31_TO_0__q54[31]}}, + w18195_BITS_31_TO_0__q54 } ; + assign b__h30158 = + { {32{cache_rg_st_amo_val_BITS_31_TO_0__q1[31]}}, + cache_rg_st_amo_val_BITS_31_TO_0__q1 } ; + assign cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22 = + cache_master_xactor_shim_arff_rv$port1__read[97:0] ; + assign cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20 = + cache_master_xactor_shim_awff_rv$port1__read[97:0] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q23 = + cache_master_xactor_shim_rff_rv$port1__read[10:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q24 = + cache_master_xactor_shim_rff_rv$port1__read[18:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q25 = + cache_master_xactor_shim_rff_rv$port1__read[34:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q26 = + cache_master_xactor_shim_rff_rv$port1__read[18:11] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q27 = + cache_master_xactor_shim_rff_rv$port1__read[26:19] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q28 = + cache_master_xactor_shim_rff_rv$port1__read[34:19] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q29 = + cache_master_xactor_shim_rff_rv$port1__read[34:27] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q30 = + cache_master_xactor_shim_rff_rv$port1__read[42:35] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q31 = + cache_master_xactor_shim_rff_rv$port1__read[50:35] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q32 = + cache_master_xactor_shim_rff_rv$port1__read[66:35] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q33 = + cache_master_xactor_shim_rff_rv$port1__read[50:43] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q34 = + cache_master_xactor_shim_rff_rv$port1__read[58:51] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q35 = + cache_master_xactor_shim_rff_rv$port1__read[66:51] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q36 = + cache_master_xactor_shim_rff_rv$port1__read[66:59] ; + assign cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q21 = + cache_master_xactor_shim_wff_rv$port1__read[72:0] ; + assign cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 = + cache_ram_state_and_ctag_cset$DOB[21:0] == pa_ctag__h7888 ; + assign cache_ram_state_and_ctag_cset_b_read__51_BIT_2_ETC___d187 = + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 || + NOT_cache_ram_state_and_ctag_cset_b_read__51_B_ETC___d186 ; + assign cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 = + cache_rg_addr == cache_rg_lrsc_pa ; + assign cache_rg_amo_funct7_32_BITS_6_TO_2_33_EQ_0b10__ETC___d363 = + cache_rg_amo_funct7[6:2] == 5'b00010 && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145 = + cache_rg_lrsc_pa == cache_rg_addr ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d200 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset_b_read__51_BIT_2_ETC___d187 || + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d198 ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d201 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d204 = + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d201 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15844 ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d341 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d350 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d360 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d198 = + cache_rg_op == 2'd1 && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 || + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d197 ; + assign cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d376 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d373 || + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d375 ; + assign cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d509 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d506 || + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d508 ; + assign cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d511 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) ; + assign cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d366 = + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 || + cache_rg_op != 2'd1 && cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 ; + assign cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d537 = + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15844 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_st_amo_val_BITS_31_TO_0__q1 = cache_rg_st_amo_val[31:0] ; + assign cache_rg_state_7_EQ_12_15_AND_cache_rg_op_29_E_ETC___d617 = + cache_rg_state == 4'd12 && + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + b__h22491 == 4'd0 ; + assign cache_rg_state_7_EQ_3_63_AND_NOT_cache_rg_op_2_ETC___d172 = + cache_rg_state == 4'd3 && + (cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) || + cache_crg_sb_to_load_delay$port0__write_1 == 11'd0) ; + assign cline_addr__h22589 = { cache_rg_pa[31:5], 5'd0 } ; + assign cline_fabric_addr__h22590 = { 32'd0, cline_addr__h22589 } ; + assign fabric_addr__h27561 = { 32'd0, cache_rg_pa } ; + assign ld_val5881_BITS_15_TO_0__q40 = ld_val__h25881[15:0] ; + assign ld_val5881_BITS_15_TO_8__q42 = ld_val__h25881[15:8] ; + assign ld_val5881_BITS_23_TO_16__q43 = ld_val__h25881[23:16] ; + assign ld_val5881_BITS_31_TO_0__q41 = ld_val__h25881[31:0] ; + assign ld_val5881_BITS_31_TO_16__q44 = ld_val__h25881[31:16] ; + assign ld_val5881_BITS_31_TO_24__q45 = ld_val__h25881[31:24] ; + assign ld_val5881_BITS_39_TO_32__q46 = ld_val__h25881[39:32] ; + assign ld_val5881_BITS_47_TO_32__q47 = ld_val__h25881[47:32] ; + assign ld_val5881_BITS_47_TO_40__q49 = ld_val__h25881[47:40] ; + assign ld_val5881_BITS_55_TO_48__q50 = ld_val__h25881[55:48] ; + assign ld_val5881_BITS_63_TO_32__q48 = ld_val__h25881[63:32] ; + assign ld_val5881_BITS_63_TO_48__q51 = ld_val__h25881[63:48] ; + assign ld_val5881_BITS_63_TO_56__q52 = ld_val__h25881[63:56] ; + assign ld_val5881_BITS_7_TO_0__q39 = ld_val__h25881[7:0] ; + assign lrsc_result__h15844 = + !cache_rg_lrsc_valid || + !cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145 ; + assign mem_req_wr_addr_awaddr__h5054 = + { 32'd0, cache_f_fabric_write_reqs$D_OUT[95:64] } ; + assign new_st_val__h19402 = + (cache_rg_f3 == 3'b010) ? + new_st_val__h19697 : + _theResult_____2__h19690 ; + assign new_st_val__h19697 = { 32'd0, _theResult_____2__h19690[31:0] } ; + assign new_st_val__h19798 = + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 + + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ; + assign new_st_val__h20791 = w1__h19682 ^ w2__h28201 ; + assign new_st_val__h20796 = w1__h19682 & w2__h28201 ; + assign new_st_val__h20801 = w1__h19682 | w2__h28201 ; + assign new_st_val__h20806 = + (w1__h19682 < w2__h28201) ? w1__h19682 : w2__h28201 ; + assign new_st_val__h20814 = + (w1__h19682 <= w2__h28201) ? w2__h28201 : w1__h19682 ; + assign new_st_val__h20823 = + ((IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 ^ + 64'h8000000000000000) < + (IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ^ + 64'h8000000000000000)) ? + w1__h19682 : + w2__h28201 ; + assign new_st_val__h20831 = + ((IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 ^ + 64'h8000000000000000) <= + (IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ^ + 64'h8000000000000000)) ? + w2__h28201 : + w1__h19682 ; + assign new_st_val__h28214 = { 32'd0, _theResult_____2__h28207[31:0] } ; + assign new_st_val__h28315 = + new_ld_val__h28161 + + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ; + assign new_st_val__h30188 = w1__h28199 ^ w2__h28201 ; + assign new_st_val__h30193 = w1__h28199 & w2__h28201 ; + assign new_st_val__h30198 = w1__h28199 | w2__h28201 ; + assign new_st_val__h30203 = + (w1__h28199 < w2__h28201) ? w1__h28199 : w2__h28201 ; + assign new_st_val__h30211 = + (w1__h28199 <= w2__h28201) ? w2__h28201 : w1__h28199 ; + assign new_st_val__h30220 = + ((new_ld_val__h28161 ^ 64'h8000000000000000) < + (IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ^ + 64'h8000000000000000)) ? + w1__h28199 : + w2__h28201 ; + assign new_st_val__h30228 = + ((new_ld_val__h28161 ^ 64'h8000000000000000) <= + (IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ^ + 64'h8000000000000000)) ? + w2__h28201 : + w1__h28199 ; + assign new_value173_BITS_31_TO_0__q17 = new_value__h8173[31:0] ; + assign pa_ctag__h7888 = { 2'd0, cache_rg_addr[31:12] } ; + assign req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943 = + req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || + req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || + req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; + assign result__h14584 = + { {56{word64992_BITS_15_TO_8__q5[7]}}, + word64992_BITS_15_TO_8__q5 } ; + assign result__h14612 = + { {56{word64992_BITS_23_TO_16__q6[7]}}, + word64992_BITS_23_TO_16__q6 } ; + assign result__h14640 = + { {56{word64992_BITS_31_TO_24__q8[7]}}, + word64992_BITS_31_TO_24__q8 } ; + assign result__h14668 = + { {56{word64992_BITS_39_TO_32__q9[7]}}, + word64992_BITS_39_TO_32__q9 } ; + assign result__h14696 = + { {56{word64992_BITS_47_TO_40__q12[7]}}, + word64992_BITS_47_TO_40__q12 } ; + assign result__h14724 = + { {56{word64992_BITS_55_TO_48__q13[7]}}, + word64992_BITS_55_TO_48__q13 } ; + assign result__h14752 = + { {56{word64992_BITS_63_TO_56__q15[7]}}, + word64992_BITS_63_TO_56__q15 } ; + assign result__h14797 = { 56'd0, word64__h7992[7:0] } ; + assign result__h14825 = { 56'd0, word64__h7992[15:8] } ; + assign result__h14853 = { 56'd0, word64__h7992[23:16] } ; + assign result__h14881 = { 56'd0, word64__h7992[31:24] } ; + assign result__h14909 = { 56'd0, word64__h7992[39:32] } ; + assign result__h14937 = { 56'd0, word64__h7992[47:40] } ; + assign result__h14965 = { 56'd0, word64__h7992[55:48] } ; + assign result__h14993 = { 56'd0, word64__h7992[63:56] } ; + assign result__h15038 = + { {48{word64992_BITS_15_TO_0__q3[15]}}, + word64992_BITS_15_TO_0__q3 } ; + assign result__h15066 = + { {48{word64992_BITS_31_TO_16__q7[15]}}, + word64992_BITS_31_TO_16__q7 } ; + assign result__h15094 = + { {48{word64992_BITS_47_TO_32__q10[15]}}, + word64992_BITS_47_TO_32__q10 } ; + assign result__h15122 = + { {48{word64992_BITS_63_TO_48__q14[15]}}, + word64992_BITS_63_TO_48__q14 } ; + assign result__h15163 = { 48'd0, word64__h7992[15:0] } ; + assign result__h15191 = { 48'd0, word64__h7992[31:16] } ; + assign result__h15219 = { 48'd0, word64__h7992[47:32] } ; + assign result__h15247 = { 48'd0, word64__h7992[63:48] } ; + assign result__h15288 = + { {32{word64992_BITS_31_TO_0__q4[31]}}, + word64992_BITS_31_TO_0__q4 } ; + assign result__h15316 = + { {32{word64992_BITS_63_TO_32__q11[31]}}, + word64992_BITS_63_TO_32__q11 } ; + assign result__h15355 = { 32'd0, word64__h7992[31:0] } ; + assign result__h15383 = { 32'd0, word64__h7992[63:32] } ; + assign result__h25941 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q23[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q23 } ; + assign result__h25971 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q26[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q26 } ; + assign result__h25998 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q27[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q27 } ; + assign result__h26025 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q29[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q29 } ; + assign result__h26052 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q30[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q30 } ; + assign result__h26079 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q33[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q33 } ; + assign result__h26106 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q34[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q34 } ; + assign result__h26133 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q36[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q36 } ; + assign result__h26177 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[10:3] } ; + assign result__h26204 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[18:11] } ; + assign result__h26231 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[26:19] } ; + assign result__h26258 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[34:27] } ; + assign result__h26285 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[42:35] } ; + assign result__h26312 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[50:43] } ; + assign result__h26339 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[58:51] } ; + assign result__h26366 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[66:59] } ; + assign result__h26410 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q24[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q24 } ; + assign result__h26437 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q28[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q28 } ; + assign result__h26464 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q31[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q31 } ; + assign result__h26491 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q35[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q35 } ; + assign result__h26531 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[18:3] } ; + assign result__h26558 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[34:19] } ; + assign result__h26585 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[50:35] } ; + assign result__h26612 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[66:51] } ; + assign result__h26652 = + { {32{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q25[31]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q25 } ; + assign result__h26679 = + { {32{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q32[31]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q32 } ; + assign result__h26717 = + { 32'd0, cache_master_xactor_shim_rff_rv$port1__read[34:3] } ; + assign result__h26744 = + { 32'd0, cache_master_xactor_shim_rff_rv$port1__read[66:35] } ; + assign result__h28412 = + { {56{ld_val5881_BITS_7_TO_0__q39[7]}}, + ld_val5881_BITS_7_TO_0__q39 } ; + assign result__h29320 = + { {56{ld_val5881_BITS_15_TO_8__q42[7]}}, + ld_val5881_BITS_15_TO_8__q42 } ; + assign result__h29348 = + { {56{ld_val5881_BITS_23_TO_16__q43[7]}}, + ld_val5881_BITS_23_TO_16__q43 } ; + assign result__h29376 = + { {56{ld_val5881_BITS_31_TO_24__q45[7]}}, + ld_val5881_BITS_31_TO_24__q45 } ; + assign result__h29404 = + { {56{ld_val5881_BITS_39_TO_32__q46[7]}}, + ld_val5881_BITS_39_TO_32__q46 } ; + assign result__h29432 = + { {56{ld_val5881_BITS_47_TO_40__q49[7]}}, + ld_val5881_BITS_47_TO_40__q49 } ; + assign result__h29460 = + { {56{ld_val5881_BITS_55_TO_48__q50[7]}}, + ld_val5881_BITS_55_TO_48__q50 } ; + assign result__h29488 = + { {56{ld_val5881_BITS_63_TO_56__q52[7]}}, + ld_val5881_BITS_63_TO_56__q52 } ; + assign result__h29533 = { 56'd0, ld_val__h25881[7:0] } ; + assign result__h29561 = { 56'd0, ld_val__h25881[15:8] } ; + assign result__h29589 = { 56'd0, ld_val__h25881[23:16] } ; + assign result__h29617 = { 56'd0, ld_val__h25881[31:24] } ; + assign result__h29645 = { 56'd0, ld_val__h25881[39:32] } ; + assign result__h29673 = { 56'd0, ld_val__h25881[47:40] } ; + assign result__h29701 = { 56'd0, ld_val__h25881[55:48] } ; + assign result__h29729 = { 56'd0, ld_val__h25881[63:56] } ; + assign result__h29774 = + { {48{ld_val5881_BITS_15_TO_0__q40[15]}}, + ld_val5881_BITS_15_TO_0__q40 } ; + assign result__h29802 = + { {48{ld_val5881_BITS_31_TO_16__q44[15]}}, + ld_val5881_BITS_31_TO_16__q44 } ; + assign result__h29830 = + { {48{ld_val5881_BITS_47_TO_32__q47[15]}}, + ld_val5881_BITS_47_TO_32__q47 } ; + assign result__h29858 = + { {48{ld_val5881_BITS_63_TO_48__q51[15]}}, + ld_val5881_BITS_63_TO_48__q51 } ; + assign result__h29899 = { 48'd0, ld_val__h25881[15:0] } ; + assign result__h29927 = { 48'd0, ld_val__h25881[31:16] } ; + assign result__h29955 = { 48'd0, ld_val__h25881[47:32] } ; + assign result__h29983 = { 48'd0, ld_val__h25881[63:48] } ; + assign result__h30024 = + { {32{ld_val5881_BITS_31_TO_0__q41[31]}}, + ld_val5881_BITS_31_TO_0__q41 } ; + assign result__h30052 = + { {32{ld_val5881_BITS_63_TO_32__q48[31]}}, + ld_val5881_BITS_63_TO_32__q48 } ; + assign result__h30091 = { 32'd0, ld_val__h25881[31:0] } ; + assign result__h30119 = { 32'd0, ld_val__h25881[63:32] } ; + assign result__h8228 = + { {56{word64992_BITS_7_TO_0__q2[7]}}, + word64992_BITS_7_TO_0__q2 } ; + assign shift_bits__h5069 = + { cache_f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ; + assign strobe64__h5230 = + 8'b00000001 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign strobe64__h5237 = + 8'b00000011 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign strobe64__h5241 = + 8'b00001111 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign w18195_BITS_31_TO_0__q54 = w1__h28195[31:0] ; + assign w1___1__h19764 = { 32'd0, new_value__h8173[31:0] } ; + assign w1___1__h28281 = { 32'd0, w1__h28195[31:0] } ; + assign w2___1__h28282 = { 32'd0, cache_rg_st_amo_val[31:0] } ; + assign w2__h28201 = + (cache_rg_f3 == 3'b010) ? w2___1__h28282 : cache_rg_st_amo_val ; + assign word64992_BITS_15_TO_0__q3 = word64__h7992[15:0] ; + assign word64992_BITS_15_TO_8__q5 = word64__h7992[15:8] ; + assign word64992_BITS_23_TO_16__q6 = word64__h7992[23:16] ; + assign word64992_BITS_31_TO_0__q4 = word64__h7992[31:0] ; + assign word64992_BITS_31_TO_16__q7 = word64__h7992[31:16] ; + assign word64992_BITS_31_TO_24__q8 = word64__h7992[31:24] ; + assign word64992_BITS_39_TO_32__q9 = word64__h7992[39:32] ; + assign word64992_BITS_47_TO_32__q10 = word64__h7992[47:32] ; + assign word64992_BITS_47_TO_40__q12 = word64__h7992[47:40] ; + assign word64992_BITS_55_TO_48__q13 = word64__h7992[55:48] ; + assign word64992_BITS_63_TO_32__q11 = word64__h7992[63:32] ; + assign word64992_BITS_63_TO_48__q14 = word64__h7992[63:48] ; + assign word64992_BITS_63_TO_56__q15 = word64__h7992[63:56] ; + assign word64992_BITS_7_TO_0__q2 = word64__h7992[7:0] ; + assign word64__h7992 = cache_ram_word64_set$DOB & y__h8264 ; + assign x__h15854 = { 63'd0, lrsc_result__h15844 } ; + assign x__h28190 = + (cache_rg_f3 == 3'b010) ? + new_st_val__h28214 : + _theResult_____2__h28207 ; + assign y__h8264 = + {64{cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157}} ; + always@(cache_f_fabric_write_reqs$D_OUT) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0: _theResult___snd_snd_val__h5250 = 3'b0; + 2'b01: _theResult___snd_snd_val__h5250 = 3'b001; + 2'b10: _theResult___snd_snd_val__h5250 = 3'b010; + 2'b11: _theResult___snd_snd_val__h5250 = 3'b011; + endcase + end + always@(cache_rg_f3) + begin + case (cache_rg_f3[1:0]) + 2'b0: size_val__h27675 = 3'b0; + 2'b01: size_val__h27675 = 3'b001; + 2'b10: size_val__h27675 = 3'b010; + 2'd3: size_val__h27675 = 3'b011; + endcase + end + always@(cache_f_fabric_write_reqs$D_OUT or + strobe64__h5230 or strobe64__h5237 or strobe64__h5241) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0: mem_req_wr_data_wstrb__h5367 = strobe64__h5230; + 2'b01: mem_req_wr_data_wstrb__h5367 = strobe64__h5237; + 2'b10: mem_req_wr_data_wstrb__h5367 = strobe64__h5241; + 2'b11: mem_req_wr_data_wstrb__h5367 = 8'b11111111; + endcase + end + always@(cache_f_fabric_write_reqs$D_OUT or _theResult___fst__h5232) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0, 2'b01, 2'b10: + mem_req_wr_data_wdata__h5366 = _theResult___fst__h5232; + 2'd3: + mem_req_wr_data_wdata__h5366 = + cache_f_fabric_write_reqs$D_OUT[63:0]; + endcase + end + always@(cache_rg_addr or + result__h14797 or + result__h14825 or + result__h14853 or + result__h14881 or + result__h14909 or + result__h14937 or result__h14965 or result__h14993) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14797; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14825; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14853; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14881; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14909; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14937; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14965; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14993; + endcase + end + always@(cache_rg_addr or + result__h8228 or + result__h14584 or + result__h14612 or + result__h14640 or + result__h14668 or + result__h14696 or result__h14724 or result__h14752) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h8228; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14584; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14612; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14640; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14668; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14696; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14724; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14752; + endcase + end + always@(cache_rg_addr or + result__h15038 or + result__h15066 or result__h15094 or result__h15122) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 = + result__h15038; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 = + result__h15066; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 = + result__h15094; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 = + result__h15122; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h15163 or + result__h15191 or result__h15219 or result__h15247) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 = + result__h15163; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 = + result__h15191; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 = + result__h15219; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 = + result__h15247; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h15355 or result__h15383) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322 = + result__h15355; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322 = + result__h15383; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h15288 or result__h15316) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16 = + result__h15288; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16 = + result__h15316; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16 = + 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322) + begin + case (cache_rg_f3) + 3'b0: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271; + 3'b001: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301; + 3'b010: + new_value__h8173 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16; + 3'b011: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324; + 3'b100: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288; + 3'b101: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310; + 3'b110: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322; + 3'd7: new_value__h8173 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 or + w1___1__h19764 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322) + begin + case (cache_rg_f3) + 3'b0: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271; + 3'b001: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301; + 3'b010: w1__h19682 = w1___1__h19764; + 3'b011: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324; + 3'b100: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288; + 3'b101: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310; + 3'b110: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322; + 3'd7: w1__h19682 = 64'd0; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 = + { cache_ram_word64_set$DOB[63:16], cache_rg_st_amo_val[15:0] }; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 = + { cache_ram_word64_set$DOB[63:32], + cache_rg_st_amo_val[15:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 = + { cache_ram_word64_set$DOB[63:48], + cache_rg_st_amo_val[15:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 = + { cache_rg_st_amo_val[15:0], cache_ram_word64_set$DOB[47:0] }; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:8], cache_rg_st_amo_val[7:0] }; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:16], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[7:0] }; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:24], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:32], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[23:0] }; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:40], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:48], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[39:0] }; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:56], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[47:0] }; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_rg_st_amo_val[7:0], cache_ram_word64_set$DOB[55:0] }; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 or + b__h19806 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271; + 3'b001: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301; + 3'b010: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + b__h19806; + 3'b011: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324; + 3'b100: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288; + 3'b101: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310; + 3'b110: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322; + 3'd7: IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = 64'd0; + endcase + end + always@(cache_rg_amo_funct7 or + new_st_val__h20831 or + new_st_val__h19798 or + w2__h28201 or + new_st_val__h20791 or + new_st_val__h20801 or + new_st_val__h20796 or + new_st_val__h20823 or new_st_val__h20806 or new_st_val__h20814) + begin + case (cache_rg_amo_funct7[6:2]) + 5'b0: _theResult_____2__h19690 = new_st_val__h19798; + 5'b00001: _theResult_____2__h19690 = w2__h28201; + 5'b00100: _theResult_____2__h19690 = new_st_val__h20791; + 5'b01000: _theResult_____2__h19690 = new_st_val__h20801; + 5'b01100: _theResult_____2__h19690 = new_st_val__h20796; + 5'b10000: _theResult_____2__h19690 = new_st_val__h20823; + 5'b11000: _theResult_____2__h19690 = new_st_val__h20806; + 5'b11100: _theResult_____2__h19690 = new_st_val__h20814; + default: _theResult_____2__h19690 = new_st_val__h20831; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19402) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 = + { cache_ram_word64_set$DOB[63:16], new_st_val__h19402[15:0] }; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 = + { cache_ram_word64_set$DOB[63:32], + new_st_val__h19402[15:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 = + { cache_ram_word64_set$DOB[63:48], + new_st_val__h19402[15:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 = + { new_st_val__h19402[15:0], cache_ram_word64_set$DOB[47:0] }; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19402) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:8], new_st_val__h19402[7:0] }; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:16], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[7:0] }; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:24], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:32], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[23:0] }; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:40], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:48], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[39:0] }; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:56], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[47:0] }; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { new_st_val__h19402[7:0], cache_ram_word64_set$DOB[55:0] }; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18 = + { cache_ram_word64_set$DOB[63:32], cache_rg_st_amo_val[31:0] }; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18 = + { cache_rg_st_amo_val[31:0], cache_ram_word64_set$DOB[31:0] }; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + cache_ram_word64_set$DOB or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18 or + cache_rg_st_amo_val) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410; + 3'b001: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419; + 3'b010: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18; + 3'b011: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 = + cache_rg_st_amo_val; + default: IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19402) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19 = + { cache_ram_word64_set$DOB[63:32], new_st_val__h19402[31:0] }; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19 = + { new_st_val__h19402[31:0], cache_ram_word64_set$DOB[31:0] }; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + cache_ram_word64_set$DOB or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19 or + new_st_val__h19402) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484; + 3'b001: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493; + 3'b010: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19; + 3'b011: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 = + new_st_val__h19402; + default: IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d338) + begin + case (cache_rg_f3) + 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: + new_value__h18271 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d338; + 3'd7: new_value__h18271 = 64'd0; + endcase + end + always@(cache_rg_addr or + result__h26531 or + result__h26558 or result__h26585 or result__h26612) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 = + result__h26531; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 = + result__h26558; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 = + result__h26585; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 = + result__h26612; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h26410 or + result__h26437 or result__h26464 or result__h26491) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 = + result__h26410; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 = + result__h26437; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 = + result__h26464; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 = + result__h26491; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h25941 or + result__h25971 or + result__h25998 or + result__h26025 or + result__h26052 or + result__h26079 or result__h26106 or result__h26133) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h25941; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h25971; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h25998; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h26025; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h26052; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h26079; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h26106; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h26133; + endcase + end + always@(cache_rg_addr or + result__h26177 or + result__h26204 or + result__h26231 or + result__h26258 or + result__h26285 or + result__h26312 or result__h26339 or result__h26366) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26177; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26204; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26231; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26258; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26285; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26312; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26339; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26366; + endcase + end + always@(cache_rg_addr or result__h26652 or result__h26679) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37 = + result__h26652; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37 = + result__h26679; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h26717 or result__h26744) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38 = + result__h26717; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38 = + result__h26744; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38 = + 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37 or + cache_rg_addr or + cache_master_xactor_shim_rff_rv$port1__read or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38) + begin + case (cache_rg_f3) + 3'b0: + ld_val__h25881 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664; + 3'b001: + ld_val__h25881 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692; + 3'b010: + ld_val__h25881 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37; + 3'b011: + ld_val__h25881 = + (cache_rg_addr[2:0] == 3'h0) ? + cache_master_xactor_shim_rff_rv$port1__read[66:3] : + 64'd0; + 3'b100: + ld_val__h25881 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680; + 3'b101: + ld_val__h25881 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700; + 3'b110: + ld_val__h25881 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38; + 3'd7: ld_val__h25881 = 64'd0; + endcase + end + always@(cache_rg_addr or result__h30091 or result__h30119) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820 = + result__h30091; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820 = + result__h30119; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h29899 or + result__h29927 or result__h29955 or result__h29983) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 = + result__h29899; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 = + result__h29927; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 = + result__h29955; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 = + result__h29983; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h29774 or + result__h29802 or result__h29830 or result__h29858) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 = + result__h29774; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 = + result__h29802; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 = + result__h29830; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 = + result__h29858; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h28412 or + result__h29320 or + result__h29348 or + result__h29376 or + result__h29404 or + result__h29432 or result__h29460 or result__h29488) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h28412; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29320; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29348; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29376; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29404; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29432; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29460; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29488; + endcase + end + always@(cache_rg_addr or + result__h29533 or + result__h29561 or + result__h29589 or + result__h29617 or + result__h29645 or + result__h29673 or result__h29701 or result__h29729) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29533; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29561; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29589; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29617; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29645; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29673; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29701; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29729; + endcase + end + always@(cache_rg_addr or result__h30024 or result__h30052) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53 = + result__h30024; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53 = + result__h30052; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53 = + 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820) + begin + case (cache_rg_f3) + 3'b0: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774; + 3'b001: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802; + 3'b010: + w1__h28195 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53; + 3'b011: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821; + 3'b100: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790; + 3'b101: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810; + 3'b110: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820; + 3'd7: w1__h28195 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 or + w1___1__h28281 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820) + begin + case (cache_rg_f3) + 3'b0: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774; + 3'b001: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802; + 3'b010: w1__h28199 = w1___1__h28281; + 3'b011: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821; + 3'b100: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790; + 3'b101: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810; + 3'b110: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820; + 3'd7: w1__h28199 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 or + b__h28323 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820) + begin + case (cache_rg_f3) + 3'b0: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774; + 3'b001: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802; + 3'b010: new_ld_val__h28161 = b__h28323; + 3'b011: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821; + 3'b100: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790; + 3'b101: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810; + 3'b110: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820; + 3'd7: new_ld_val__h28161 = 64'd0; + endcase + end + always@(cache_rg_amo_funct7 or + new_st_val__h30228 or + new_st_val__h28315 or + w2__h28201 or + new_st_val__h30188 or + new_st_val__h30198 or + new_st_val__h30193 or + new_st_val__h30220 or new_st_val__h30203 or new_st_val__h30211) + begin + case (cache_rg_amo_funct7[6:2]) + 5'b0: _theResult_____2__h28207 = new_st_val__h28315; + 5'b00001: _theResult_____2__h28207 = w2__h28201; + 5'b00100: _theResult_____2__h28207 = new_st_val__h30188; + 5'b01000: _theResult_____2__h28207 = new_st_val__h30198; + 5'b01100: _theResult_____2__h28207 = new_st_val__h30193; + 5'b10000: _theResult_____2__h28207 = new_st_val__h30220; + 5'b11000: _theResult_____2__h28207 = new_st_val__h30203; + 5'b11100: _theResult_____2__h28207 = new_st_val__h30211; + default: _theResult_____2__h28207 = new_st_val__h30228; + endcase + end + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + cache_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; + cache_crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; + cache_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; + cache_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 8'd42; + cache_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 73'h0AAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + cache_rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 7'd0; + cache_rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; + end + else + begin + if (cache_cfg_verbosity$EN) + cache_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY + cache_cfg_verbosity$D_IN; + if (cache_crg_sb_to_load_delay$EN) + cache_crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY + cache_crg_sb_to_load_delay$D_IN; + if (cache_ctr_wr_rsps_pending_crg$EN) + cache_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY + cache_ctr_wr_rsps_pending_crg$D_IN; + if (cache_master_xactor_clearing$EN) + cache_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_clearing$D_IN; + if (cache_master_xactor_shim_arff_rv$EN) + cache_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_arff_rv$D_IN; + if (cache_master_xactor_shim_awff_rv$EN) + cache_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_awff_rv$D_IN; + if (cache_master_xactor_shim_bff_rv$EN) + cache_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_bff_rv$D_IN; + if (cache_master_xactor_shim_rff_rv$EN) + cache_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_rff_rv$D_IN; + if (cache_master_xactor_shim_wff_rv$EN) + cache_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_wff_rv$D_IN; + if (cache_rg_cset_in_cache$EN) + cache_rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY + cache_rg_cset_in_cache$D_IN; + if (cache_rg_lower_word32_full$EN) + cache_rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY + cache_rg_lower_word32_full$D_IN; + if (cache_rg_lrsc_valid$EN) + cache_rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY + cache_rg_lrsc_valid$D_IN; + if (cache_rg_state$EN) + cache_rg_state <= `BSV_ASSIGNMENT_DELAY cache_rg_state$D_IN; + end + if (cache_rg_addr$EN) + cache_rg_addr <= `BSV_ASSIGNMENT_DELAY cache_rg_addr$D_IN; + if (cache_rg_amo_funct7$EN) + cache_rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY cache_rg_amo_funct7$D_IN; + if (cache_rg_error_during_refill$EN) + cache_rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY + cache_rg_error_during_refill$D_IN; + if (cache_rg_exc_code$EN) + cache_rg_exc_code <= `BSV_ASSIGNMENT_DELAY cache_rg_exc_code$D_IN; + if (cache_rg_f3$EN) cache_rg_f3 <= `BSV_ASSIGNMENT_DELAY cache_rg_f3$D_IN; + if (cache_rg_ld_val$EN) + cache_rg_ld_val <= `BSV_ASSIGNMENT_DELAY cache_rg_ld_val$D_IN; + if (cache_rg_lower_word32$EN) + cache_rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY + cache_rg_lower_word32$D_IN; + if (cache_rg_lrsc_pa$EN) + cache_rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_lrsc_pa$D_IN; + if (cache_rg_op$EN) cache_rg_op <= `BSV_ASSIGNMENT_DELAY cache_rg_op$D_IN; + if (cache_rg_pa$EN) cache_rg_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_pa$D_IN; + if (cache_rg_pte_pa$EN) + cache_rg_pte_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_pte_pa$D_IN; + if (cache_rg_st_amo_val$EN) + cache_rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY cache_rg_st_amo_val$D_IN; + if (cache_rg_word64_set_in_cache$EN) + cache_rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY + cache_rg_word64_set_in_cache$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + cache_cfg_verbosity = 4'hA; + cache_crg_sb_to_load_delay = 11'h2AA; + cache_ctr_wr_rsps_pending_crg = 4'hA; + cache_master_xactor_clearing = 1'h0; + cache_master_xactor_shim_arff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_awff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_bff_rv = 8'hAA; + cache_master_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + cache_rg_addr = 32'hAAAAAAAA; + cache_rg_amo_funct7 = 7'h2A; + cache_rg_cset_in_cache = 7'h2A; + cache_rg_error_during_refill = 1'h0; + cache_rg_exc_code = 4'hA; + cache_rg_f3 = 3'h2; + cache_rg_ld_val = 64'hAAAAAAAAAAAAAAAA; + cache_rg_lower_word32 = 32'hAAAAAAAA; + cache_rg_lower_word32_full = 1'h0; + cache_rg_lrsc_pa = 32'hAAAAAAAA; + cache_rg_lrsc_valid = 1'h0; + cache_rg_op = 2'h2; + cache_rg_pa = 32'hAAAAAAAA; + cache_rg_pte_pa = 32'hAAAAAAAA; + cache_rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; + cache_rg_state = 4'hA; + cache_rg_word64_set_in_cache = 9'h0AA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + begin + v__h5641 = $stime; + #0; + end + v__h5635 = v__h5641 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + $display("%0d: ERROR: CreditCounter: overflow", v__h5635); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_AWFlit { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 5'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_addr_awaddr__h5054); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", _theResult___snd_snd_val__h5250, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_WFlit { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_data_wdata__h5366); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wstrb: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_data_wstrb__h5367); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + cache_cfg_verbosity != 4'd0 && + !cache_f_reset_reqs$D_OUT) + begin + v__h6477 = $stime; + #0; + end + v__h6471 = v__h6477 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + cache_cfg_verbosity != 4'd0 && + !cache_f_reset_reqs$D_OUT) + $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", + v__h6471, + "I_MMU_Cache", + $signed(32'd128), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_f_reset_reqs$D_OUT) + begin + v__h6580 = $stime; + #0; + end + v__h6574 = v__h6580 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_f_reset_reqs$D_OUT) + $display("%0d: %s.rl_reset: Flushed", v__h6574, "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h7034 = $stime; + #0; + end + v__h7028 = v__h7034 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", + v__h7028, + "I_MMU_Cache", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", + pa_ctag__h7888, + cache_rg_addr[11:5], + cache_rg_addr[4:3], + cache_rg_addr[2:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" CSet 0x%0x: (state, tag):", cache_rg_addr[11:5]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" ("); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_ram_state_and_ctag_cset$DOB[22]) + $write("CTAG_CLEAN"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_ram_state_and_ctag_cset$DOB[22]) + $write("CTAG_EMPTY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_ram_state_and_ctag_cset$DOB[22]) + $write(", 0x%0x", cache_ram_state_and_ctag_cset$DOB[21:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_ram_state_and_ctag_cset$DOB[22]) + $write(", --"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(")"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" 0x%0x", cache_ram_word64_set$DOB); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" TLB result: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("VM_Xlate_Result { ", "outcome: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("VM_XLATE_OK"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "pa: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'hA, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d350) + begin + v__h15467 = $stime; + #0; + end + v__h15461 = v__h15467 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d350) + $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", + v__h15461, + "I_MMU_Cache", + cache_rg_addr, + word64__h7992, + 64'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO LR: reserving PA 0x%0h", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d350) + $display(" Read-hit: addr 0x%0h word64 0x%0h", + cache_rg_addr, + word64__h7992); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d360) + $display(" Read Miss: -> CACHE_START_REFILL."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd2 && + cache_rg_amo_funct7_32_BITS_6_TO_2_33_EQ_0b10__ETC___d363) + $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", + cache_rg_lrsc_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd1 && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" ST: cancelling LR/SC reservation for PA", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + cache_rg_lrsc_valid && + !cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", + cache_rg_lrsc_pa, + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + !cache_rg_lrsc_valid && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC: fail due to invalid LR/SC reservation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC result = %0d", lrsc_result__h15844); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528) + $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528) + $write(" New Word64_Set:"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528) + $write(" 0x%0x", + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d529) + $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d534) + $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d534) + $display(" => rl_write_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d537) + begin + v__h19180 = $stime; + #0; + end + v__h19174 = v__h19180 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d537) + $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", + v__h19174, + "I_MMU_Cache", + cache_rg_addr, + 64'd1, + 64'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d537) + $display(" AMO SC: Fail response for addr 0x%0h", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d540) + $display(" AMO Miss: -> CACHE_START_REFILL."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", + cache_rg_addr, + cache_rg_amo_funct7, + cache_rg_f3, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $display(" PA 0x%0h ", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $display(" Cache word64 0x%0h, load-result 0x%0h", + word64__h7992, + word64__h7992); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $display(" 0x%0h op 0x%0h -> 0x%0h", + word64__h7992, + word64__h7992, + new_st_val__h19402); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $write(" New Word64_Set:"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $write(" 0x%0x", + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d545) + $display(" AMO_op: cancelling LR/SC reservation for PA", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h22537 = $stime; + #0; + end + v__h22531 = v__h22537 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_start_cache_refill: ", v__h22531, "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 5'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cline_fabric_addr__h22590); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd3); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'b011, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" Victim way %0d; => CACHE_REFILL", 1'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_rereq && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", + cache_rg_addr[11:5], + cache_rg_addr[11:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h25370 = $stime; + #0; + end + v__h25364 = v__h25370 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", + v__h25364, + "I_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 5'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", fabric_addr__h27561); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", size_val__h27675, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_maintain_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27092 = $stime; + #0; + end + v__h27086 = v__h27092 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_maintain_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h27086, + "I_MMU_Cache", + cache_rg_addr, + cache_rg_ld_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27175 = $stime; + #0; + end + v__h27169 = v__h27175 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h27169, + "I_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27388 = $stime; + #0; + end + v__h27382 = v__h27388 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h27382, + "I_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" FAIL due to I/O address."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27509 = $stime; + #0; + end + v__h27503 = v__h27509 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", + v__h27503, + "I_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 5'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", fabric_addr__h27561); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", size_val__h27675, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h31052 = $stime; + #0; + end + v__h31046 = v__h31052 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("%0d: %s.rl_discard_write_rsp: pending %0d ", + v__h31046, + "I_MMU_Cache", + $unsigned(b__h22491)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_bff_rv$port1__read[6:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + begin + v__h31013 = $stime; + #0; + end + v__h31007 = v__h31013 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", + v__h31007, + "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("'h%h", cache_master_xactor_shim_bff_rv$port1__read[6:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0 && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd1 && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_reset && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h6102 = $stime; + #0; + end + v__h6096 = v__h6102 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_reset && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_start_reset", v__h6096, "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + begin + v__h23486 = $stime; + #0; + end + v__h23480 = v__h23486 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $display("%0d: %s.rl_cache_refill_rsps_loop:", + v__h23480, + "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[71:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h23740 = $stime; + #0; + end + v__h23734 = v__h23740 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", + v__h23734, + "I_MMU_Cache", + 4'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 && + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_rg_error_during_refill) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => MODULE_EXCEPTION_RSP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + !cache_rg_error_during_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => CACHE_REREQ"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", + cache_rg_word64_set_in_cache, + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(" 0x%0x", cache_ram_word64_set$DOB); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(" 0x%0x", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h25756 = $stime; + #0; + end + v__h25750 = v__h25756 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", + v__h25750, + "I_MMU_Cache", + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[71:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26874 = $stime; + #0; + end + v__h26868 = v__h26874 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h26868, + "I_MMU_Cache", + cache_rg_addr, + ld_val__h25881); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26982 = $stime; + #0; + end + v__h26976 = v__h26982 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", + v__h26976, + "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27839 = $stime; + #0; + end + v__h27833 = v__h27839 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", + v__h27833, + "I_MMU_Cache", + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[71:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h28034 = $stime; + #0; + end + v__h28028 = v__h28034 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h28028, + "I_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h30336 = $stime; + #0; + end + v__h30330 = v__h30336 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h30330, + "I_MMU_Cache", + cache_rg_addr, + new_ld_val__h28161); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h28131 = $stime; + #0; + end + v__h28125 = v__h28131 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", + v__h28125, + "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h31440 = $stime; + #0; + end + v__h31434 = v__h31440 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("%0d: %s.req: op:", v__h31434, "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op == 2'd0) + $write("CACHE_LD"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op == 2'd1) + $write("CACHE_ST"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op != 2'd0 && + req_op != 2'd1) + $write("CACHE_AMO"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", + req_f3, + req_addr, + req_st_value); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b0) + $write("U"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b01) + $write("S"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b11) + $write("M"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv != 2'b0 && + req_priv != 2'b01 && + req_priv != 2'b11) + $write("RESERVED"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", + req_sstatus_SUM, + req_mstatus_MXR, + req_satp, + "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" amo_funct7 = 0x%0h", req_amo_funct7); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && + req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", + req_addr[11:5], + req_addr[11:3]); + end + // synopsys translate_on +endmodule // mkMMU_ICache + diff --git a/src_SSITH_P1/Verilog_RTL/mkNear_Mem.v b/src_SSITH_P1/Verilog_RTL/mkNear_Mem.v index 66849c25..be881b5c 100644 --- a/src_SSITH_P1/Verilog_RTL/mkNear_Mem.v +++ b/src_SSITH_P1/Verilog_RTL/mkNear_Mem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:46 BST 2019 // // // Ports: @@ -15,66 +15,66 @@ // imem_exc O 1 // imem_exc_code O 4 reg // imem_tval O 32 reg +// imem_master_awid O 5 +// imem_master_awaddr O 64 +// imem_master_awlen O 8 +// imem_master_awsize O 3 +// imem_master_awburst O 2 +// imem_master_awlock O 1 +// imem_master_awcache O 4 +// imem_master_awprot O 3 +// imem_master_awqos O 4 +// imem_master_awregion O 4 // imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg +// imem_master_wdata O 64 +// imem_master_wstrb O 8 +// imem_master_wlast O 1 // imem_master_wvalid O 1 -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg // imem_master_bready O 1 +// imem_master_arid O 5 +// imem_master_araddr O 64 +// imem_master_arlen O 8 +// imem_master_arsize O 3 +// imem_master_arburst O 2 +// imem_master_arlock O 1 +// imem_master_arcache O 4 +// imem_master_arprot O 3 +// imem_master_arqos O 4 +// imem_master_arregion O 4 // imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg // imem_master_rready O 1 // dmem_valid O 1 // dmem_word64 O 64 // dmem_st_amo_val O 64 // dmem_exc O 1 // dmem_exc_code O 4 reg +// dmem_master_awid O 4 +// dmem_master_awaddr O 64 +// dmem_master_awlen O 8 +// dmem_master_awsize O 3 +// dmem_master_awburst O 2 +// dmem_master_awlock O 1 +// dmem_master_awcache O 4 +// dmem_master_awprot O 3 +// dmem_master_awqos O 4 +// dmem_master_awregion O 4 // dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg +// dmem_master_wdata O 64 +// dmem_master_wstrb O 8 +// dmem_master_wlast O 1 // dmem_master_wvalid O 1 -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg // dmem_master_bready O 1 +// dmem_master_arid O 4 +// dmem_master_araddr O 64 +// dmem_master_arlen O 8 +// dmem_master_arsize O 3 +// dmem_master_arburst O 2 +// dmem_master_arlock O 1 +// dmem_master_arcache O 4 +// dmem_master_arprot O 3 +// dmem_master_arqos O 4 +// dmem_master_arregion O 4 // dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg // dmem_master_rready O 1 // RDY_server_fence_i_request_put O 1 // RDY_server_fence_i_response_get O 1 @@ -91,15 +91,13 @@ // imem_req_satp I 32 unused // imem_master_awready I 1 // imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg +// imem_master_bid I 5 +// imem_master_bresp I 2 // imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg +// imem_master_rid I 5 +// imem_master_rdata I 64 +// imem_master_rresp I 2 +// imem_master_rlast I 1 // dmem_req_op I 2 // dmem_req_f3 I 3 // dmem_req_amo_funct7 I 7 reg @@ -111,20 +109,22 @@ // dmem_req_satp I 32 unused // dmem_master_awready I 1 // dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg +// dmem_master_bid I 4 +// dmem_master_bresp I 2 // dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg +// dmem_master_rid I 4 +// dmem_master_rdata I 64 +// dmem_master_rresp I 2 +// dmem_master_rlast I 1 // server_fence_request_put I 8 unused // EN_server_reset_request_put I 1 // EN_server_reset_response_get I 1 // EN_imem_req I 1 +// imem_master_bvalid I 1 +// imem_master_rvalid I 1 // EN_dmem_req I 1 +// dmem_master_bvalid I 1 +// dmem_master_rvalid I 1 // EN_server_fence_i_request_put I 1 // EN_server_fence_i_response_get I 1 // EN_server_fence_request_put I 1 @@ -132,15 +132,50 @@ // EN_sfence_vma I 1 unused // // Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_valid -// (imem_master_awready, imem_master_wready) -> imem_instr -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, imem_master_wready, EN_imem_req) -> imem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_valid -// (dmem_master_awready, dmem_master_wready) -> dmem_word64 -// (dmem_master_awready, dmem_master_wready) -> dmem_st_amo_val -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// (dmem_master_awready, dmem_master_wready, EN_dmem_req) -> dmem_master_rready +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// imem_master_rvalid) -> imem_valid +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// imem_master_rvalid) -> imem_instr +// (dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// dmem_master_rvalid) -> dmem_valid +// (dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// dmem_master_rvalid) -> dmem_word64 +// EN_imem_req -> imem_master_arid +// EN_imem_req -> imem_master_araddr +// EN_imem_req -> imem_master_arlen +// EN_imem_req -> imem_master_arsize +// EN_imem_req -> imem_master_arburst +// EN_imem_req -> imem_master_arlock +// EN_imem_req -> imem_master_arcache +// EN_imem_req -> imem_master_arprot +// EN_imem_req -> imem_master_arqos +// EN_imem_req -> imem_master_arregion +// EN_imem_req -> imem_master_aruser +// EN_imem_req -> imem_master_arvalid +// EN_dmem_req -> dmem_master_arid +// EN_dmem_req -> dmem_master_araddr +// EN_dmem_req -> dmem_master_arlen +// EN_dmem_req -> dmem_master_arsize +// EN_dmem_req -> dmem_master_arburst +// EN_dmem_req -> dmem_master_arlock +// EN_dmem_req -> dmem_master_arcache +// EN_dmem_req -> dmem_master_arprot +// EN_dmem_req -> dmem_master_arqos +// EN_dmem_req -> dmem_master_arregion +// EN_dmem_req -> dmem_master_aruser +// EN_dmem_req -> dmem_master_arvalid // // @@ -188,8 +223,6 @@ module mkNear_Mem(CLK, imem_tval, - imem_master_awvalid, - imem_master_awid, imem_master_awaddr, @@ -210,9 +243,9 @@ module mkNear_Mem(CLK, imem_master_awregion, - imem_master_awready, + imem_master_awvalid, - imem_master_wvalid, + imem_master_awready, imem_master_wdata, @@ -220,16 +253,16 @@ module mkNear_Mem(CLK, imem_master_wlast, + imem_master_wvalid, + imem_master_wready, - imem_master_bvalid, imem_master_bid, imem_master_bresp, + imem_master_bvalid, imem_master_bready, - imem_master_arvalid, - imem_master_arid, imem_master_araddr, @@ -250,13 +283,15 @@ module mkNear_Mem(CLK, imem_master_arregion, + imem_master_arvalid, + imem_master_arready, - imem_master_rvalid, imem_master_rid, imem_master_rdata, imem_master_rresp, imem_master_rlast, + imem_master_rvalid, imem_master_rready, @@ -281,8 +316,6 @@ module mkNear_Mem(CLK, dmem_exc_code, - dmem_master_awvalid, - dmem_master_awid, dmem_master_awaddr, @@ -303,9 +336,9 @@ module mkNear_Mem(CLK, dmem_master_awregion, - dmem_master_awready, + dmem_master_awvalid, - dmem_master_wvalid, + dmem_master_awready, dmem_master_wdata, @@ -313,16 +346,16 @@ module mkNear_Mem(CLK, dmem_master_wlast, + dmem_master_wvalid, + dmem_master_wready, - dmem_master_bvalid, dmem_master_bid, dmem_master_bresp, + dmem_master_bvalid, dmem_master_bready, - dmem_master_arvalid, - dmem_master_arid, dmem_master_araddr, @@ -343,13 +376,15 @@ module mkNear_Mem(CLK, dmem_master_arregion, + dmem_master_arvalid, + dmem_master_arready, - dmem_master_rvalid, dmem_master_rid, dmem_master_rdata, dmem_master_rresp, dmem_master_rlast, + dmem_master_rvalid, dmem_master_rready, @@ -409,115 +444,115 @@ module mkNear_Mem(CLK, // value method imem_tval output [31 : 0] imem_tval; - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; + // value method imem_master_aw_awid + output [4 : 0] imem_master_awid; - // value method imem_master_m_awaddr + // value method imem_master_aw_awaddr output [63 : 0] imem_master_awaddr; - // value method imem_master_m_awlen + // value method imem_master_aw_awlen output [7 : 0] imem_master_awlen; - // value method imem_master_m_awsize + // value method imem_master_aw_awsize output [2 : 0] imem_master_awsize; - // value method imem_master_m_awburst + // value method imem_master_aw_awburst output [1 : 0] imem_master_awburst; - // value method imem_master_m_awlock + // value method imem_master_aw_awlock output imem_master_awlock; - // value method imem_master_m_awcache + // value method imem_master_aw_awcache output [3 : 0] imem_master_awcache; - // value method imem_master_m_awprot + // value method imem_master_aw_awprot output [2 : 0] imem_master_awprot; - // value method imem_master_m_awqos + // value method imem_master_aw_awqos output [3 : 0] imem_master_awqos; - // value method imem_master_m_awregion + // value method imem_master_aw_awregion output [3 : 0] imem_master_awregion; - // value method imem_master_m_awuser + // value method imem_master_aw_awuser - // action method imem_master_m_awready - input imem_master_awready; + // value method imem_master_aw_awvalid + output imem_master_awvalid; - // value method imem_master_m_wvalid - output imem_master_wvalid; + // action method imem_master_aw_awready + input imem_master_awready; - // value method imem_master_m_wdata + // value method imem_master_w_wdata output [63 : 0] imem_master_wdata; - // value method imem_master_m_wstrb + // value method imem_master_w_wstrb output [7 : 0] imem_master_wstrb; - // value method imem_master_m_wlast + // value method imem_master_w_wlast output imem_master_wlast; - // value method imem_master_m_wuser + // value method imem_master_w_wuser - // action method imem_master_m_wready + // value method imem_master_w_wvalid + output imem_master_wvalid; + + // action method imem_master_w_wready input imem_master_wready; - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; + // action method imem_master_b_bflit + input [4 : 0] imem_master_bid; input [1 : 0] imem_master_bresp; + input imem_master_bvalid; - // value method imem_master_m_bready + // value method imem_master_b_bready output imem_master_bready; - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; + // value method imem_master_ar_arid + output [4 : 0] imem_master_arid; - // value method imem_master_m_araddr + // value method imem_master_ar_araddr output [63 : 0] imem_master_araddr; - // value method imem_master_m_arlen + // value method imem_master_ar_arlen output [7 : 0] imem_master_arlen; - // value method imem_master_m_arsize + // value method imem_master_ar_arsize output [2 : 0] imem_master_arsize; - // value method imem_master_m_arburst + // value method imem_master_ar_arburst output [1 : 0] imem_master_arburst; - // value method imem_master_m_arlock + // value method imem_master_ar_arlock output imem_master_arlock; - // value method imem_master_m_arcache + // value method imem_master_ar_arcache output [3 : 0] imem_master_arcache; - // value method imem_master_m_arprot + // value method imem_master_ar_arprot output [2 : 0] imem_master_arprot; - // value method imem_master_m_arqos + // value method imem_master_ar_arqos output [3 : 0] imem_master_arqos; - // value method imem_master_m_arregion + // value method imem_master_ar_arregion output [3 : 0] imem_master_arregion; - // value method imem_master_m_aruser + // value method imem_master_ar_aruser - // action method imem_master_m_arready + // value method imem_master_ar_arvalid + output imem_master_arvalid; + + // action method imem_master_ar_arready input imem_master_arready; - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; + // action method imem_master_r_rflit + input [4 : 0] imem_master_rid; input [63 : 0] imem_master_rdata; input [1 : 0] imem_master_rresp; input imem_master_rlast; + input imem_master_rvalid; - // value method imem_master_m_rready + // value method imem_master_r_rready output imem_master_rready; // action method dmem_req @@ -547,115 +582,115 @@ module mkNear_Mem(CLK, // value method dmem_exc_code output [3 : 0] dmem_exc_code; - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid + // value method dmem_master_aw_awid output [3 : 0] dmem_master_awid; - // value method dmem_master_m_awaddr + // value method dmem_master_aw_awaddr output [63 : 0] dmem_master_awaddr; - // value method dmem_master_m_awlen + // value method dmem_master_aw_awlen output [7 : 0] dmem_master_awlen; - // value method dmem_master_m_awsize + // value method dmem_master_aw_awsize output [2 : 0] dmem_master_awsize; - // value method dmem_master_m_awburst + // value method dmem_master_aw_awburst output [1 : 0] dmem_master_awburst; - // value method dmem_master_m_awlock + // value method dmem_master_aw_awlock output dmem_master_awlock; - // value method dmem_master_m_awcache + // value method dmem_master_aw_awcache output [3 : 0] dmem_master_awcache; - // value method dmem_master_m_awprot + // value method dmem_master_aw_awprot output [2 : 0] dmem_master_awprot; - // value method dmem_master_m_awqos + // value method dmem_master_aw_awqos output [3 : 0] dmem_master_awqos; - // value method dmem_master_m_awregion + // value method dmem_master_aw_awregion output [3 : 0] dmem_master_awregion; - // value method dmem_master_m_awuser + // value method dmem_master_aw_awuser - // action method dmem_master_m_awready - input dmem_master_awready; + // value method dmem_master_aw_awvalid + output dmem_master_awvalid; - // value method dmem_master_m_wvalid - output dmem_master_wvalid; + // action method dmem_master_aw_awready + input dmem_master_awready; - // value method dmem_master_m_wdata + // value method dmem_master_w_wdata output [63 : 0] dmem_master_wdata; - // value method dmem_master_m_wstrb + // value method dmem_master_w_wstrb output [7 : 0] dmem_master_wstrb; - // value method dmem_master_m_wlast + // value method dmem_master_w_wlast output dmem_master_wlast; - // value method dmem_master_m_wuser + // value method dmem_master_w_wuser + + // value method dmem_master_w_wvalid + output dmem_master_wvalid; - // action method dmem_master_m_wready + // action method dmem_master_w_wready input dmem_master_wready; - // action method dmem_master_m_bvalid - input dmem_master_bvalid; + // action method dmem_master_b_bflit input [3 : 0] dmem_master_bid; input [1 : 0] dmem_master_bresp; + input dmem_master_bvalid; - // value method dmem_master_m_bready + // value method dmem_master_b_bready output dmem_master_bready; - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid + // value method dmem_master_ar_arid output [3 : 0] dmem_master_arid; - // value method dmem_master_m_araddr + // value method dmem_master_ar_araddr output [63 : 0] dmem_master_araddr; - // value method dmem_master_m_arlen + // value method dmem_master_ar_arlen output [7 : 0] dmem_master_arlen; - // value method dmem_master_m_arsize + // value method dmem_master_ar_arsize output [2 : 0] dmem_master_arsize; - // value method dmem_master_m_arburst + // value method dmem_master_ar_arburst output [1 : 0] dmem_master_arburst; - // value method dmem_master_m_arlock + // value method dmem_master_ar_arlock output dmem_master_arlock; - // value method dmem_master_m_arcache + // value method dmem_master_ar_arcache output [3 : 0] dmem_master_arcache; - // value method dmem_master_m_arprot + // value method dmem_master_ar_arprot output [2 : 0] dmem_master_arprot; - // value method dmem_master_m_arqos + // value method dmem_master_ar_arqos output [3 : 0] dmem_master_arqos; - // value method dmem_master_m_arregion + // value method dmem_master_ar_arregion output [3 : 0] dmem_master_arregion; - // value method dmem_master_m_aruser + // value method dmem_master_ar_aruser + + // value method dmem_master_ar_arvalid + output dmem_master_arvalid; - // action method dmem_master_m_arready + // action method dmem_master_ar_arready input dmem_master_arready; - // action method dmem_master_m_rvalid - input dmem_master_rvalid; + // action method dmem_master_r_rflit input [3 : 0] dmem_master_rid; input [63 : 0] dmem_master_rdata; input [1 : 0] dmem_master_rresp; input dmem_master_rlast; + input dmem_master_rvalid; - // value method dmem_master_m_rready + // value method dmem_master_r_rready output dmem_master_rready; // action method server_fence_i_request_put @@ -695,6 +730,7 @@ module mkNear_Mem(CLK, imem_master_arlen, imem_master_awlen, imem_master_wstrb; + wire [4 : 0] imem_master_arid, imem_master_awid; wire [3 : 0] dmem_exc_code, dmem_master_arcache, dmem_master_arid, @@ -706,11 +742,9 @@ module mkNear_Mem(CLK, dmem_master_awregion, imem_exc_code, imem_master_arcache, - imem_master_arid, imem_master_arqos, imem_master_arregion, imem_master_awcache, - imem_master_awid, imem_master_awqos, imem_master_awregion; wire [2 : 0] dmem_master_arprot, @@ -849,17 +883,17 @@ module mkNear_Mem(CLK, icache$mem_master_awlen, icache$mem_master_wstrb; wire [6 : 0] icache$req_amo_funct7; + wire [4 : 0] icache$mem_master_arid, + icache$mem_master_awid, + icache$mem_master_bid, + icache$mem_master_rid; wire [3 : 0] icache$exc_code, icache$mem_master_arcache, - icache$mem_master_arid, icache$mem_master_arqos, icache$mem_master_arregion, icache$mem_master_awcache, - icache$mem_master_awid, icache$mem_master_awqos, icache$mem_master_awregion, - icache$mem_master_bid, - icache$mem_master_rid, icache$set_verbosity_verbosity; wire [2 : 0] icache$mem_master_arprot, icache$mem_master_arsize, @@ -910,17 +944,17 @@ module mkNear_Mem(CLK, // rule scheduling signals wire CAN_FIRE_RL_rl_reset, CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, + CAN_FIRE_dmem_master_ar_arready, + CAN_FIRE_dmem_master_aw_awready, + CAN_FIRE_dmem_master_b_bflit, + CAN_FIRE_dmem_master_r_rflit, + CAN_FIRE_dmem_master_w_wready, CAN_FIRE_dmem_req, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, + CAN_FIRE_imem_master_ar_arready, + CAN_FIRE_imem_master_aw_awready, + CAN_FIRE_imem_master_b_bflit, + CAN_FIRE_imem_master_r_rflit, + CAN_FIRE_imem_master_w_wready, CAN_FIRE_imem_req, CAN_FIRE_server_fence_i_request_put, CAN_FIRE_server_fence_i_response_get, @@ -931,17 +965,17 @@ module mkNear_Mem(CLK, CAN_FIRE_sfence_vma, WILL_FIRE_RL_rl_reset, WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, + WILL_FIRE_dmem_master_ar_arready, + WILL_FIRE_dmem_master_aw_awready, + WILL_FIRE_dmem_master_b_bflit, + WILL_FIRE_dmem_master_r_rflit, + WILL_FIRE_dmem_master_w_wready, WILL_FIRE_dmem_req, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, + WILL_FIRE_imem_master_ar_arready, + WILL_FIRE_imem_master_aw_awready, + WILL_FIRE_imem_master_b_bflit, + WILL_FIRE_imem_master_r_rflit, + WILL_FIRE_imem_master_w_wready, WILL_FIRE_imem_req, WILL_FIRE_server_fence_i_request_put, WILL_FIRE_server_fence_i_response_get, @@ -952,14 +986,14 @@ module mkNear_Mem(CLK, WILL_FIRE_sfence_vma; // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_3; + wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1767; - reg [31 : 0] v__h1918; - reg [31 : 0] v__h1761; - reg [31 : 0] v__h1912; + reg [31 : 0] v__h1541; + reg [31 : 0] v__h1692; + reg [31 : 0] v__h1535; + reg [31 : 0] v__h1686; // synopsys translate_on // remaining internal signals @@ -1000,108 +1034,108 @@ module mkNear_Mem(CLK, // value method imem_tval assign imem_tval = icache$addr ; - // value method imem_master_m_awvalid - assign imem_master_awvalid = icache$mem_master_awvalid ; - - // value method imem_master_m_awid + // value method imem_master_aw_awid assign imem_master_awid = icache$mem_master_awid ; - // value method imem_master_m_awaddr + // value method imem_master_aw_awaddr assign imem_master_awaddr = icache$mem_master_awaddr ; - // value method imem_master_m_awlen + // value method imem_master_aw_awlen assign imem_master_awlen = icache$mem_master_awlen ; - // value method imem_master_m_awsize + // value method imem_master_aw_awsize assign imem_master_awsize = icache$mem_master_awsize ; - // value method imem_master_m_awburst + // value method imem_master_aw_awburst assign imem_master_awburst = icache$mem_master_awburst ; - // value method imem_master_m_awlock + // value method imem_master_aw_awlock assign imem_master_awlock = icache$mem_master_awlock ; - // value method imem_master_m_awcache + // value method imem_master_aw_awcache assign imem_master_awcache = icache$mem_master_awcache ; - // value method imem_master_m_awprot + // value method imem_master_aw_awprot assign imem_master_awprot = icache$mem_master_awprot ; - // value method imem_master_m_awqos + // value method imem_master_aw_awqos assign imem_master_awqos = icache$mem_master_awqos ; - // value method imem_master_m_awregion + // value method imem_master_aw_awregion assign imem_master_awregion = icache$mem_master_awregion ; - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; + // value method imem_master_aw_awvalid + assign imem_master_awvalid = icache$mem_master_awvalid ; - // value method imem_master_m_wvalid - assign imem_master_wvalid = icache$mem_master_wvalid ; + // action method imem_master_aw_awready + assign CAN_FIRE_imem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_imem_master_aw_awready = 1'd1 ; - // value method imem_master_m_wdata + // value method imem_master_w_wdata assign imem_master_wdata = icache$mem_master_wdata ; - // value method imem_master_m_wstrb + // value method imem_master_w_wstrb assign imem_master_wstrb = icache$mem_master_wstrb ; - // value method imem_master_m_wlast + // value method imem_master_w_wlast assign imem_master_wlast = icache$mem_master_wlast ; - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; + // value method imem_master_w_wvalid + assign imem_master_wvalid = icache$mem_master_wvalid ; - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; + // action method imem_master_w_wready + assign CAN_FIRE_imem_master_w_wready = 1'd1 ; + assign WILL_FIRE_imem_master_w_wready = 1'd1 ; - // value method imem_master_m_bready - assign imem_master_bready = icache$mem_master_bready ; + // action method imem_master_b_bflit + assign CAN_FIRE_imem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_imem_master_b_bflit = imem_master_bvalid ; - // value method imem_master_m_arvalid - assign imem_master_arvalid = icache$mem_master_arvalid ; + // value method imem_master_b_bready + assign imem_master_bready = icache$mem_master_bready ; - // value method imem_master_m_arid + // value method imem_master_ar_arid assign imem_master_arid = icache$mem_master_arid ; - // value method imem_master_m_araddr + // value method imem_master_ar_araddr assign imem_master_araddr = icache$mem_master_araddr ; - // value method imem_master_m_arlen + // value method imem_master_ar_arlen assign imem_master_arlen = icache$mem_master_arlen ; - // value method imem_master_m_arsize + // value method imem_master_ar_arsize assign imem_master_arsize = icache$mem_master_arsize ; - // value method imem_master_m_arburst + // value method imem_master_ar_arburst assign imem_master_arburst = icache$mem_master_arburst ; - // value method imem_master_m_arlock + // value method imem_master_ar_arlock assign imem_master_arlock = icache$mem_master_arlock ; - // value method imem_master_m_arcache + // value method imem_master_ar_arcache assign imem_master_arcache = icache$mem_master_arcache ; - // value method imem_master_m_arprot + // value method imem_master_ar_arprot assign imem_master_arprot = icache$mem_master_arprot ; - // value method imem_master_m_arqos + // value method imem_master_ar_arqos assign imem_master_arqos = icache$mem_master_arqos ; - // value method imem_master_m_arregion + // value method imem_master_ar_arregion assign imem_master_arregion = icache$mem_master_arregion ; - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; + // value method imem_master_ar_arvalid + assign imem_master_arvalid = icache$mem_master_arvalid ; + + // action method imem_master_ar_arready + assign CAN_FIRE_imem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_imem_master_ar_arready = 1'd1 ; - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; + // action method imem_master_r_rflit + assign CAN_FIRE_imem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_imem_master_r_rflit = imem_master_rvalid ; - // value method imem_master_m_rready + // value method imem_master_r_rready assign imem_master_rready = icache$mem_master_rready ; // action method dmem_req @@ -1123,108 +1157,108 @@ module mkNear_Mem(CLK, // value method dmem_exc_code assign dmem_exc_code = dcache$exc_code ; - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = dcache$mem_master_awvalid ; - - // value method dmem_master_m_awid + // value method dmem_master_aw_awid assign dmem_master_awid = dcache$mem_master_awid ; - // value method dmem_master_m_awaddr + // value method dmem_master_aw_awaddr assign dmem_master_awaddr = dcache$mem_master_awaddr ; - // value method dmem_master_m_awlen + // value method dmem_master_aw_awlen assign dmem_master_awlen = dcache$mem_master_awlen ; - // value method dmem_master_m_awsize + // value method dmem_master_aw_awsize assign dmem_master_awsize = dcache$mem_master_awsize ; - // value method dmem_master_m_awburst + // value method dmem_master_aw_awburst assign dmem_master_awburst = dcache$mem_master_awburst ; - // value method dmem_master_m_awlock + // value method dmem_master_aw_awlock assign dmem_master_awlock = dcache$mem_master_awlock ; - // value method dmem_master_m_awcache + // value method dmem_master_aw_awcache assign dmem_master_awcache = dcache$mem_master_awcache ; - // value method dmem_master_m_awprot + // value method dmem_master_aw_awprot assign dmem_master_awprot = dcache$mem_master_awprot ; - // value method dmem_master_m_awqos + // value method dmem_master_aw_awqos assign dmem_master_awqos = dcache$mem_master_awqos ; - // value method dmem_master_m_awregion + // value method dmem_master_aw_awregion assign dmem_master_awregion = dcache$mem_master_awregion ; - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; + // value method dmem_master_aw_awvalid + assign dmem_master_awvalid = dcache$mem_master_awvalid ; - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = dcache$mem_master_wvalid ; + // action method dmem_master_aw_awready + assign CAN_FIRE_dmem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_dmem_master_aw_awready = 1'd1 ; - // value method dmem_master_m_wdata + // value method dmem_master_w_wdata assign dmem_master_wdata = dcache$mem_master_wdata ; - // value method dmem_master_m_wstrb + // value method dmem_master_w_wstrb assign dmem_master_wstrb = dcache$mem_master_wstrb ; - // value method dmem_master_m_wlast + // value method dmem_master_w_wlast assign dmem_master_wlast = dcache$mem_master_wlast ; - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; + // value method dmem_master_w_wvalid + assign dmem_master_wvalid = dcache$mem_master_wvalid ; + + // action method dmem_master_w_wready + assign CAN_FIRE_dmem_master_w_wready = 1'd1 ; + assign WILL_FIRE_dmem_master_w_wready = 1'd1 ; - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; + // action method dmem_master_b_bflit + assign CAN_FIRE_dmem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_dmem_master_b_bflit = dmem_master_bvalid ; - // value method dmem_master_m_bready + // value method dmem_master_b_bready assign dmem_master_bready = dcache$mem_master_bready ; - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = dcache$mem_master_arvalid ; - - // value method dmem_master_m_arid + // value method dmem_master_ar_arid assign dmem_master_arid = dcache$mem_master_arid ; - // value method dmem_master_m_araddr + // value method dmem_master_ar_araddr assign dmem_master_araddr = dcache$mem_master_araddr ; - // value method dmem_master_m_arlen + // value method dmem_master_ar_arlen assign dmem_master_arlen = dcache$mem_master_arlen ; - // value method dmem_master_m_arsize + // value method dmem_master_ar_arsize assign dmem_master_arsize = dcache$mem_master_arsize ; - // value method dmem_master_m_arburst + // value method dmem_master_ar_arburst assign dmem_master_arburst = dcache$mem_master_arburst ; - // value method dmem_master_m_arlock + // value method dmem_master_ar_arlock assign dmem_master_arlock = dcache$mem_master_arlock ; - // value method dmem_master_m_arcache + // value method dmem_master_ar_arcache assign dmem_master_arcache = dcache$mem_master_arcache ; - // value method dmem_master_m_arprot + // value method dmem_master_ar_arprot assign dmem_master_arprot = dcache$mem_master_arprot ; - // value method dmem_master_m_arqos + // value method dmem_master_ar_arqos assign dmem_master_arqos = dcache$mem_master_arqos ; - // value method dmem_master_m_arregion + // value method dmem_master_ar_arregion assign dmem_master_arregion = dcache$mem_master_arregion ; - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; + // value method dmem_master_ar_arvalid + assign dmem_master_arvalid = dcache$mem_master_arvalid ; - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; + // action method dmem_master_ar_arready + assign CAN_FIRE_dmem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_dmem_master_ar_arready = 1'd1 ; - // value method dmem_master_m_rready + // action method dmem_master_r_rflit + assign CAN_FIRE_dmem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_dmem_master_r_rflit = dmem_master_rvalid ; + + // value method dmem_master_r_rready assign dmem_master_rready = dcache$mem_master_rready ; // action method server_fence_i_request_put @@ -1266,76 +1300,76 @@ module mkNear_Mem(CLK, assign WILL_FIRE_sfence_vma = EN_sfence_vma ; // submodule dcache - mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(dcache$mem_master_arready), - .mem_master_awready(dcache$mem_master_awready), - .mem_master_bid(dcache$mem_master_bid), - .mem_master_bresp(dcache$mem_master_bresp), - .mem_master_bvalid(dcache$mem_master_bvalid), - .mem_master_rdata(dcache$mem_master_rdata), - .mem_master_rid(dcache$mem_master_rid), - .mem_master_rlast(dcache$mem_master_rlast), - .mem_master_rresp(dcache$mem_master_rresp), - .mem_master_rvalid(dcache$mem_master_rvalid), - .mem_master_wready(dcache$mem_master_wready), - .req_addr(dcache$req_addr), - .req_amo_funct7(dcache$req_amo_funct7), - .req_f3(dcache$req_f3), - .req_mstatus_MXR(dcache$req_mstatus_MXR), - .req_op(dcache$req_op), - .req_priv(dcache$req_priv), - .req_satp(dcache$req_satp), - .req_sstatus_SUM(dcache$req_sstatus_SUM), - .req_st_value(dcache$req_st_value), - .set_verbosity_verbosity(dcache$set_verbosity_verbosity), - .EN_set_verbosity(dcache$EN_set_verbosity), - .EN_server_reset_request_put(dcache$EN_server_reset_request_put), - .EN_server_reset_response_get(dcache$EN_server_reset_response_get), - .EN_req(dcache$EN_req), - .EN_server_flush_request_put(dcache$EN_server_flush_request_put), - .EN_server_flush_response_get(dcache$EN_server_flush_response_get), - .EN_tlb_flush(dcache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), - .valid(dcache$valid), - .addr(), - .word64(dcache$word64), - .st_amo_val(dcache$st_amo_val), - .exc(dcache$exc), - .exc_code(dcache$exc_code), - .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(dcache$mem_master_awvalid), - .mem_master_awid(dcache$mem_master_awid), - .mem_master_awaddr(dcache$mem_master_awaddr), - .mem_master_awlen(dcache$mem_master_awlen), - .mem_master_awsize(dcache$mem_master_awsize), - .mem_master_awburst(dcache$mem_master_awburst), - .mem_master_awlock(dcache$mem_master_awlock), - .mem_master_awcache(dcache$mem_master_awcache), - .mem_master_awprot(dcache$mem_master_awprot), - .mem_master_awqos(dcache$mem_master_awqos), - .mem_master_awregion(dcache$mem_master_awregion), - .mem_master_wvalid(dcache$mem_master_wvalid), - .mem_master_wdata(dcache$mem_master_wdata), - .mem_master_wstrb(dcache$mem_master_wstrb), - .mem_master_wlast(dcache$mem_master_wlast), - .mem_master_bready(dcache$mem_master_bready), - .mem_master_arvalid(dcache$mem_master_arvalid), - .mem_master_arid(dcache$mem_master_arid), - .mem_master_araddr(dcache$mem_master_araddr), - .mem_master_arlen(dcache$mem_master_arlen), - .mem_master_arsize(dcache$mem_master_arsize), - .mem_master_arburst(dcache$mem_master_arburst), - .mem_master_arlock(dcache$mem_master_arlock), - .mem_master_arcache(dcache$mem_master_arcache), - .mem_master_arprot(dcache$mem_master_arprot), - .mem_master_arqos(dcache$mem_master_arqos), - .mem_master_arregion(dcache$mem_master_arregion), - .mem_master_rready(dcache$mem_master_rready)); + mkMMU_DCache dcache(.CLK(CLK), + .RST_N(RST_N), + .mem_master_arready(dcache$mem_master_arready), + .mem_master_awready(dcache$mem_master_awready), + .mem_master_bid(dcache$mem_master_bid), + .mem_master_bresp(dcache$mem_master_bresp), + .mem_master_rdata(dcache$mem_master_rdata), + .mem_master_rid(dcache$mem_master_rid), + .mem_master_rlast(dcache$mem_master_rlast), + .mem_master_rresp(dcache$mem_master_rresp), + .mem_master_wready(dcache$mem_master_wready), + .req_addr(dcache$req_addr), + .req_amo_funct7(dcache$req_amo_funct7), + .req_f3(dcache$req_f3), + .req_mstatus_MXR(dcache$req_mstatus_MXR), + .req_op(dcache$req_op), + .req_priv(dcache$req_priv), + .req_satp(dcache$req_satp), + .req_sstatus_SUM(dcache$req_sstatus_SUM), + .req_st_value(dcache$req_st_value), + .set_verbosity_verbosity(dcache$set_verbosity_verbosity), + .EN_set_verbosity(dcache$EN_set_verbosity), + .EN_server_reset_request_put(dcache$EN_server_reset_request_put), + .EN_server_reset_response_get(dcache$EN_server_reset_response_get), + .EN_req(dcache$EN_req), + .EN_server_flush_request_put(dcache$EN_server_flush_request_put), + .EN_server_flush_response_get(dcache$EN_server_flush_response_get), + .EN_tlb_flush(dcache$EN_tlb_flush), + .mem_master_bvalid(dcache$mem_master_bvalid), + .mem_master_rvalid(dcache$mem_master_rvalid), + .RDY_set_verbosity(), + .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), + .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), + .valid(dcache$valid), + .addr(), + .word64(dcache$word64), + .st_amo_val(dcache$st_amo_val), + .exc(dcache$exc), + .exc_code(dcache$exc_code), + .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), + .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), + .RDY_tlb_flush(), + .mem_master_awid(dcache$mem_master_awid), + .mem_master_awaddr(dcache$mem_master_awaddr), + .mem_master_awlen(dcache$mem_master_awlen), + .mem_master_awsize(dcache$mem_master_awsize), + .mem_master_awburst(dcache$mem_master_awburst), + .mem_master_awlock(dcache$mem_master_awlock), + .mem_master_awcache(dcache$mem_master_awcache), + .mem_master_awprot(dcache$mem_master_awprot), + .mem_master_awqos(dcache$mem_master_awqos), + .mem_master_awregion(dcache$mem_master_awregion), + .mem_master_awvalid(dcache$mem_master_awvalid), + .mem_master_wdata(dcache$mem_master_wdata), + .mem_master_wstrb(dcache$mem_master_wstrb), + .mem_master_wlast(dcache$mem_master_wlast), + .mem_master_wvalid(dcache$mem_master_wvalid), + .mem_master_bready(dcache$mem_master_bready), + .mem_master_arid(dcache$mem_master_arid), + .mem_master_araddr(dcache$mem_master_araddr), + .mem_master_arlen(dcache$mem_master_arlen), + .mem_master_arsize(dcache$mem_master_arsize), + .mem_master_arburst(dcache$mem_master_arburst), + .mem_master_arlock(dcache$mem_master_arlock), + .mem_master_arcache(dcache$mem_master_arcache), + .mem_master_arprot(dcache$mem_master_arprot), + .mem_master_arqos(dcache$mem_master_arqos), + .mem_master_arregion(dcache$mem_master_arregion), + .mem_master_arvalid(dcache$mem_master_arvalid), + .mem_master_rready(dcache$mem_master_rready)); // submodule f_reset_rsps FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), @@ -1347,76 +1381,76 @@ module mkNear_Mem(CLK, .EMPTY_N(f_reset_rsps$EMPTY_N)); // submodule icache - mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(icache$mem_master_arready), - .mem_master_awready(icache$mem_master_awready), - .mem_master_bid(icache$mem_master_bid), - .mem_master_bresp(icache$mem_master_bresp), - .mem_master_bvalid(icache$mem_master_bvalid), - .mem_master_rdata(icache$mem_master_rdata), - .mem_master_rid(icache$mem_master_rid), - .mem_master_rlast(icache$mem_master_rlast), - .mem_master_rresp(icache$mem_master_rresp), - .mem_master_rvalid(icache$mem_master_rvalid), - .mem_master_wready(icache$mem_master_wready), - .req_addr(icache$req_addr), - .req_amo_funct7(icache$req_amo_funct7), - .req_f3(icache$req_f3), - .req_mstatus_MXR(icache$req_mstatus_MXR), - .req_op(icache$req_op), - .req_priv(icache$req_priv), - .req_satp(icache$req_satp), - .req_sstatus_SUM(icache$req_sstatus_SUM), - .req_st_value(icache$req_st_value), - .set_verbosity_verbosity(icache$set_verbosity_verbosity), - .EN_set_verbosity(icache$EN_set_verbosity), - .EN_server_reset_request_put(icache$EN_server_reset_request_put), - .EN_server_reset_response_get(icache$EN_server_reset_response_get), - .EN_req(icache$EN_req), - .EN_server_flush_request_put(icache$EN_server_flush_request_put), - .EN_server_flush_response_get(icache$EN_server_flush_response_get), - .EN_tlb_flush(icache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), - .valid(icache$valid), - .addr(icache$addr), - .word64(icache$word64), - .st_amo_val(), - .exc(icache$exc), - .exc_code(icache$exc_code), - .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(icache$mem_master_awvalid), - .mem_master_awid(icache$mem_master_awid), - .mem_master_awaddr(icache$mem_master_awaddr), - .mem_master_awlen(icache$mem_master_awlen), - .mem_master_awsize(icache$mem_master_awsize), - .mem_master_awburst(icache$mem_master_awburst), - .mem_master_awlock(icache$mem_master_awlock), - .mem_master_awcache(icache$mem_master_awcache), - .mem_master_awprot(icache$mem_master_awprot), - .mem_master_awqos(icache$mem_master_awqos), - .mem_master_awregion(icache$mem_master_awregion), - .mem_master_wvalid(icache$mem_master_wvalid), - .mem_master_wdata(icache$mem_master_wdata), - .mem_master_wstrb(icache$mem_master_wstrb), - .mem_master_wlast(icache$mem_master_wlast), - .mem_master_bready(icache$mem_master_bready), - .mem_master_arvalid(icache$mem_master_arvalid), - .mem_master_arid(icache$mem_master_arid), - .mem_master_araddr(icache$mem_master_araddr), - .mem_master_arlen(icache$mem_master_arlen), - .mem_master_arsize(icache$mem_master_arsize), - .mem_master_arburst(icache$mem_master_arburst), - .mem_master_arlock(icache$mem_master_arlock), - .mem_master_arcache(icache$mem_master_arcache), - .mem_master_arprot(icache$mem_master_arprot), - .mem_master_arqos(icache$mem_master_arqos), - .mem_master_arregion(icache$mem_master_arregion), - .mem_master_rready(icache$mem_master_rready)); + mkMMU_ICache icache(.CLK(CLK), + .RST_N(RST_N), + .mem_master_arready(icache$mem_master_arready), + .mem_master_awready(icache$mem_master_awready), + .mem_master_bid(icache$mem_master_bid), + .mem_master_bresp(icache$mem_master_bresp), + .mem_master_rdata(icache$mem_master_rdata), + .mem_master_rid(icache$mem_master_rid), + .mem_master_rlast(icache$mem_master_rlast), + .mem_master_rresp(icache$mem_master_rresp), + .mem_master_wready(icache$mem_master_wready), + .req_addr(icache$req_addr), + .req_amo_funct7(icache$req_amo_funct7), + .req_f3(icache$req_f3), + .req_mstatus_MXR(icache$req_mstatus_MXR), + .req_op(icache$req_op), + .req_priv(icache$req_priv), + .req_satp(icache$req_satp), + .req_sstatus_SUM(icache$req_sstatus_SUM), + .req_st_value(icache$req_st_value), + .set_verbosity_verbosity(icache$set_verbosity_verbosity), + .EN_set_verbosity(icache$EN_set_verbosity), + .EN_server_reset_request_put(icache$EN_server_reset_request_put), + .EN_server_reset_response_get(icache$EN_server_reset_response_get), + .EN_req(icache$EN_req), + .EN_server_flush_request_put(icache$EN_server_flush_request_put), + .EN_server_flush_response_get(icache$EN_server_flush_response_get), + .EN_tlb_flush(icache$EN_tlb_flush), + .mem_master_bvalid(icache$mem_master_bvalid), + .mem_master_rvalid(icache$mem_master_rvalid), + .RDY_set_verbosity(), + .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), + .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), + .valid(icache$valid), + .addr(icache$addr), + .word64(icache$word64), + .st_amo_val(), + .exc(icache$exc), + .exc_code(icache$exc_code), + .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), + .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), + .RDY_tlb_flush(), + .mem_master_awid(icache$mem_master_awid), + .mem_master_awaddr(icache$mem_master_awaddr), + .mem_master_awlen(icache$mem_master_awlen), + .mem_master_awsize(icache$mem_master_awsize), + .mem_master_awburst(icache$mem_master_awburst), + .mem_master_awlock(icache$mem_master_awlock), + .mem_master_awcache(icache$mem_master_awcache), + .mem_master_awprot(icache$mem_master_awprot), + .mem_master_awqos(icache$mem_master_awqos), + .mem_master_awregion(icache$mem_master_awregion), + .mem_master_awvalid(icache$mem_master_awvalid), + .mem_master_wdata(icache$mem_master_wdata), + .mem_master_wstrb(icache$mem_master_wstrb), + .mem_master_wlast(icache$mem_master_wlast), + .mem_master_wvalid(icache$mem_master_wvalid), + .mem_master_bready(icache$mem_master_bready), + .mem_master_arid(icache$mem_master_arid), + .mem_master_araddr(icache$mem_master_araddr), + .mem_master_arlen(icache$mem_master_arlen), + .mem_master_arsize(icache$mem_master_arsize), + .mem_master_arburst(icache$mem_master_arburst), + .mem_master_arlock(icache$mem_master_arlock), + .mem_master_arcache(icache$mem_master_arcache), + .mem_master_arprot(icache$mem_master_arprot), + .mem_master_arqos(icache$mem_master_arqos), + .mem_master_arregion(icache$mem_master_arregion), + .mem_master_arvalid(icache$mem_master_arvalid), + .mem_master_rready(icache$mem_master_rready)); // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), @@ -1424,36 +1458,16 @@ module mkNear_Mem(CLK, .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_flash_mem_addr_base(), - .m_flash_mem_addr_size(), - .m_flash_mem_addr_lim(), - .m_ethernet_0_addr_base(), - .m_ethernet_0_addr_size(), - .m_ethernet_0_addr_lim(), - .m_dma_0_addr_base(), - .m_dma_0_addr_size(), - .m_dma_0_addr_lim(), - .m_uart16550_0_addr_base(), - .m_uart16550_0_addr_size(), - .m_uart16550_0_addr_lim(), - .m_gpio_0_addr_base(), - .m_gpio_0_addr_size(), - .m_gpio_0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_ddr4_0_uncached_addr_base(), - .m_ddr4_0_uncached_addr_size(), - .m_ddr4_0_uncached_addr_lim(), - .m_ddr4_0_cached_addr_base(), - .m_ddr4_0_cached_addr_size(), - .m_ddr4_0_cached_addr_lim(), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), @@ -1466,15 +1480,16 @@ module mkNear_Mem(CLK, dcache$RDY_server_reset_request_put && icache$RDY_server_reset_request_put && rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset = - CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && - !EN_server_fence_i_request_put ; + assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; // rule RL_rl_reset_complete assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; // inputs to muxes for submodule ports + assign MUX_rg_state$write_1__SEL_2 = + CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && + !EN_server_fence_i_request_put ; assign MUX_rg_state$write_1__SEL_3 = dcache$RDY_server_reset_response_get && icache$RDY_server_reset_response_get && @@ -1505,12 +1520,10 @@ module mkNear_Mem(CLK, assign dcache$mem_master_awready = dmem_master_awready ; assign dcache$mem_master_bid = dmem_master_bid ; assign dcache$mem_master_bresp = dmem_master_bresp ; - assign dcache$mem_master_bvalid = dmem_master_bvalid ; assign dcache$mem_master_rdata = dmem_master_rdata ; assign dcache$mem_master_rid = dmem_master_rid ; assign dcache$mem_master_rlast = dmem_master_rlast ; assign dcache$mem_master_rresp = dmem_master_rresp ; - assign dcache$mem_master_rvalid = dmem_master_rvalid ; assign dcache$mem_master_wready = dmem_master_wready ; assign dcache$req_addr = dmem_req_addr ; assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ; @@ -1523,7 +1536,7 @@ module mkNear_Mem(CLK, assign dcache$req_st_value = dmem_req_store_value ; assign dcache$set_verbosity_verbosity = 4'h0 ; assign dcache$EN_set_verbosity = 1'b0 ; - assign dcache$EN_server_reset_request_put = WILL_FIRE_RL_rl_reset ; + assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; assign dcache$EN_req = EN_dmem_req ; assign dcache$EN_server_flush_request_put = @@ -1531,13 +1544,11 @@ module mkNear_Mem(CLK, assign dcache$EN_server_flush_response_get = EN_server_fence_i_response_get || EN_server_fence_response_get ; assign dcache$EN_tlb_flush = EN_sfence_vma ; + assign dcache$mem_master_bvalid = dmem_master_bvalid ; + assign dcache$mem_master_rvalid = dmem_master_rvalid ; // submodule f_reset_rsps - assign f_reset_rsps$ENQ = - dcache$RDY_server_reset_response_get && - icache$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - rg_state == 2'd1 ; + assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ; assign f_reset_rsps$DEQ = EN_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; @@ -1546,12 +1557,10 @@ module mkNear_Mem(CLK, assign icache$mem_master_awready = imem_master_awready ; assign icache$mem_master_bid = imem_master_bid ; assign icache$mem_master_bresp = imem_master_bresp ; - assign icache$mem_master_bvalid = imem_master_bvalid ; assign icache$mem_master_rdata = imem_master_rdata ; assign icache$mem_master_rid = imem_master_rid ; assign icache$mem_master_rlast = imem_master_rlast ; assign icache$mem_master_rresp = imem_master_rresp ; - assign icache$mem_master_rvalid = imem_master_rvalid ; assign icache$mem_master_wready = imem_master_wready ; assign icache$req_addr = imem_req_addr ; assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ; @@ -1564,13 +1573,15 @@ module mkNear_Mem(CLK, assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; assign icache$set_verbosity_verbosity = 4'h0 ; assign icache$EN_set_verbosity = 1'b0 ; - assign icache$EN_server_reset_request_put = WILL_FIRE_RL_rl_reset ; + assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; assign icache$EN_req = EN_imem_req ; assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ; assign icache$EN_server_flush_response_get = EN_server_fence_i_response_get ; assign icache$EN_tlb_flush = EN_sfence_vma ; + assign icache$mem_master_bvalid = imem_master_bvalid ; + assign icache$mem_master_rvalid = imem_master_rvalid ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; @@ -1617,23 +1628,23 @@ module mkNear_Mem(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) begin - v__h1767 = $stime; + v__h1541 = $stime; #0; end - v__h1761 = v__h1767 / 32'd10; + v__h1535 = v__h1541 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset", v__h1761); + $display("%0d: Near_Mem.rl_reset", v__h1535); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) begin - v__h1918 = $stime; + v__h1692 = $stime; #0; end - v__h1912 = v__h1918 / 32'd10; + v__h1686 = v__h1692 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset_complete", v__h1912); + $display("%0d: Near_Mem.rl_reset_complete", v__h1686); end // synopsys translate_on endmodule // mkNear_Mem diff --git a/src_SSITH_P1/Verilog_RTL/mkNear_Mem_IO_AXI4.v b/src_SSITH_P1/Verilog_RTL/mkNear_Mem_IO_AXI4.v index 44c76846..b7b0d0be 100644 --- a/src_SSITH_P1/Verilog_RTL/mkNear_Mem_IO_AXI4.v +++ b/src_SSITH_P1/Verilog_RTL/mkNear_Mem_IO_AXI4.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:23 BST 2019 // // // Ports: @@ -9,17 +9,17 @@ // RDY_server_reset_request_put O 1 reg // RDY_server_reset_response_get O 1 reg // RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg +// axi4_slave_awready O 1 +// axi4_slave_wready O 1 +// axi4_slave_bid O 5 +// axi4_slave_bresp O 2 +// axi4_slave_bvalid O 1 +// axi4_slave_arready O 1 +// axi4_slave_rid O 5 +// axi4_slave_rdata O 64 +// axi4_slave_rresp O 2 +// axi4_slave_rlast O 1 +// axi4_slave_rvalid O 1 // get_timer_interrupt_req_get O 1 reg // RDY_get_timer_interrupt_req_get O 1 reg // get_sw_interrupt_req_get O 1 reg @@ -28,41 +28,167 @@ // RST_N I 1 reset // set_addr_map_addr_base I 64 reg // set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg +// axi4_slave_awid I 5 +// axi4_slave_awaddr I 64 +// axi4_slave_awlen I 8 +// axi4_slave_awsize I 3 +// axi4_slave_awburst I 2 +// axi4_slave_awlock I 1 +// axi4_slave_awcache I 4 +// axi4_slave_awprot I 3 +// axi4_slave_awqos I 4 +// axi4_slave_awregion I 4 +// axi4_slave_wdata I 64 +// axi4_slave_wstrb I 8 +// axi4_slave_wlast I 1 // axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg +// axi4_slave_arid I 5 +// axi4_slave_araddr I 64 +// axi4_slave_arlen I 8 +// axi4_slave_arsize I 3 +// axi4_slave_arburst I 2 +// axi4_slave_arlock I 1 +// axi4_slave_arcache I 4 +// axi4_slave_arprot I 3 +// axi4_slave_arqos I 4 +// axi4_slave_arregion I 4 // axi4_slave_rready I 1 // EN_server_reset_request_put I 1 // EN_server_reset_response_get I 1 // EN_set_addr_map I 1 +// axi4_slave_awvalid I 1 +// axi4_slave_wvalid I 1 +// axi4_slave_arvalid I 1 // EN_get_timer_interrupt_req_get I 1 // EN_get_sw_interrupt_req_get I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_awvalid, +// axi4_slave_wvalid) -> axi4_slave_bid +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_awvalid, +// axi4_slave_wvalid) -> axi4_slave_bresp +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_awvalid, +// axi4_slave_wvalid) -> axi4_slave_buser +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_awvalid, +// axi4_slave_wvalid) -> axi4_slave_bvalid +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rid +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rdata +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rresp +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rlast +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_ruser +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rvalid // // @@ -93,7 +219,6 @@ module mkNear_Mem_IO_AXI4(CLK, EN_set_addr_map, RDY_set_addr_map, - axi4_slave_awvalid, axi4_slave_awid, axi4_slave_awaddr, axi4_slave_awlen, @@ -104,25 +229,25 @@ module mkNear_Mem_IO_AXI4(CLK, axi4_slave_awprot, axi4_slave_awqos, axi4_slave_awregion, + axi4_slave_awvalid, axi4_slave_awready, - axi4_slave_wvalid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, + axi4_slave_wvalid, axi4_slave_wready, - axi4_slave_bvalid, - axi4_slave_bid, axi4_slave_bresp, + axi4_slave_bvalid, + axi4_slave_bready, - axi4_slave_arvalid, axi4_slave_arid, axi4_slave_araddr, axi4_slave_arlen, @@ -133,11 +258,10 @@ module mkNear_Mem_IO_AXI4(CLK, axi4_slave_arprot, axi4_slave_arqos, axi4_slave_arregion, + axi4_slave_arvalid, axi4_slave_arready, - axi4_slave_rvalid, - axi4_slave_rid, axi4_slave_rdata, @@ -146,6 +270,8 @@ module mkNear_Mem_IO_AXI4(CLK, axi4_slave_rlast, + axi4_slave_rvalid, + axi4_slave_rready, EN_get_timer_interrupt_req_get, @@ -172,9 +298,8 @@ module mkNear_Mem_IO_AXI4(CLK, input EN_set_addr_map; output RDY_set_addr_map; - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; + // action method axi4_slave_aw_awflit + input [4 : 0] axi4_slave_awid; input [63 : 0] axi4_slave_awaddr; input [7 : 0] axi4_slave_awlen; input [2 : 0] axi4_slave_awsize; @@ -184,36 +309,36 @@ module mkNear_Mem_IO_AXI4(CLK, input [2 : 0] axi4_slave_awprot; input [3 : 0] axi4_slave_awqos; input [3 : 0] axi4_slave_awregion; + input axi4_slave_awvalid; - // value method axi4_slave_m_awready + // value method axi4_slave_aw_awready output axi4_slave_awready; - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; + // action method axi4_slave_w_wflit input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; + input axi4_slave_wvalid; - // value method axi4_slave_m_wready + // value method axi4_slave_w_wready output axi4_slave_wready; - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; + // value method axi4_slave_b_bid + output [4 : 0] axi4_slave_bid; - // value method axi4_slave_m_bresp + // value method axi4_slave_b_bresp output [1 : 0] axi4_slave_bresp; - // value method axi4_slave_m_buser + // value method axi4_slave_b_buser + + // value method axi4_slave_b_bvalid + output axi4_slave_bvalid; - // action method axi4_slave_m_bready + // action method axi4_slave_b_bready input axi4_slave_bready; - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; + // action method axi4_slave_ar_arflit + input [4 : 0] axi4_slave_arid; input [63 : 0] axi4_slave_araddr; input [7 : 0] axi4_slave_arlen; input [2 : 0] axi4_slave_arsize; @@ -223,28 +348,29 @@ module mkNear_Mem_IO_AXI4(CLK, input [2 : 0] axi4_slave_arprot; input [3 : 0] axi4_slave_arqos; input [3 : 0] axi4_slave_arregion; + input axi4_slave_arvalid; - // value method axi4_slave_m_arready + // value method axi4_slave_ar_arready output axi4_slave_arready; - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; + // value method axi4_slave_r_rid + output [4 : 0] axi4_slave_rid; - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata + // value method axi4_slave_r_rdata output [63 : 0] axi4_slave_rdata; - // value method axi4_slave_m_rresp + // value method axi4_slave_r_rresp output [1 : 0] axi4_slave_rresp; - // value method axi4_slave_m_rlast + // value method axi4_slave_r_rlast output axi4_slave_rlast; - // value method axi4_slave_m_ruser + // value method axi4_slave_r_ruser + + // value method axi4_slave_r_rvalid + output axi4_slave_rvalid; - // action method axi4_slave_m_rready + // action method axi4_slave_r_rready input axi4_slave_rready; // actionvalue method get_timer_interrupt_req_get @@ -259,7 +385,7 @@ module mkNear_Mem_IO_AXI4(CLK, // signals for module outputs wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; + wire [4 : 0] axi4_slave_bid, axi4_slave_rid; wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; wire RDY_get_sw_interrupt_req_get, RDY_get_timer_interrupt_req_get, @@ -276,12 +402,41 @@ module mkNear_Mem_IO_AXI4(CLK, get_timer_interrupt_req_get; // inlined wires + wire [98 : 0] slave_xactor_shim_arff_rv$port0__write_1, + slave_xactor_shim_arff_rv$port1__read, + slave_xactor_shim_arff_rv$port2__read, + slave_xactor_shim_arff_rv$port3__read, + slave_xactor_shim_awff_rv$port0__write_1, + slave_xactor_shim_awff_rv$port1__read, + slave_xactor_shim_awff_rv$port2__read, + slave_xactor_shim_awff_rv$port3__read; + wire [97 : 0] slave_xactor_ug_slave_u_ar_putWire$wget, + slave_xactor_ug_slave_u_aw_putWire$wget; + wire [73 : 0] slave_xactor_shim_wff_rv$port0__write_1, + slave_xactor_shim_wff_rv$port1__read, + slave_xactor_shim_wff_rv$port2__read, + slave_xactor_shim_wff_rv$port3__read; + wire [72 : 0] slave_xactor_shim_rff_rv$port0__write_1, + slave_xactor_shim_rff_rv$port1__read, + slave_xactor_shim_rff_rv$port2__read, + slave_xactor_shim_rff_rv$port3__read, + slave_xactor_ug_slave_u_w_putWire$wget; wire [63 : 0] crg_time$port0__write_1, crg_time$port1__write_1, crg_time$port2__read, crg_timecmp$port1__write_1, crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; + wire [7 : 0] slave_xactor_shim_bff_rv$port0__write_1, + slave_xactor_shim_bff_rv$port1__read, + slave_xactor_shim_bff_rv$port2__read, + slave_xactor_shim_bff_rv$port3__read; + wire crg_time$EN_port1__write, + crg_timecmp$EN_port1__write, + slave_xactor_ug_slave_u_ar_putWire$whas, + slave_xactor_ug_slave_u_aw_putWire$whas, + slave_xactor_ug_slave_u_b_dropWire$whas, + slave_xactor_ug_slave_u_r_dropWire$whas, + slave_xactor_ug_slave_u_w_putWire$whas; // register cfg_verbosity reg [3 : 0] cfg_verbosity; @@ -320,6 +475,35 @@ module mkNear_Mem_IO_AXI4(CLK, reg rg_state; wire rg_state$D_IN, rg_state$EN; + // register slave_xactor_clearing + reg slave_xactor_clearing; + wire slave_xactor_clearing$D_IN, slave_xactor_clearing$EN; + + // register slave_xactor_shim_arff_rv + reg [98 : 0] slave_xactor_shim_arff_rv; + wire [98 : 0] slave_xactor_shim_arff_rv$D_IN; + wire slave_xactor_shim_arff_rv$EN; + + // register slave_xactor_shim_awff_rv + reg [98 : 0] slave_xactor_shim_awff_rv; + wire [98 : 0] slave_xactor_shim_awff_rv$D_IN; + wire slave_xactor_shim_awff_rv$EN; + + // register slave_xactor_shim_bff_rv + reg [7 : 0] slave_xactor_shim_bff_rv; + wire [7 : 0] slave_xactor_shim_bff_rv$D_IN; + wire slave_xactor_shim_bff_rv$EN; + + // register slave_xactor_shim_rff_rv + reg [72 : 0] slave_xactor_shim_rff_rv; + wire [72 : 0] slave_xactor_shim_rff_rv$D_IN; + wire slave_xactor_shim_rff_rv$EN; + + // register slave_xactor_shim_wff_rv + reg [73 : 0] slave_xactor_shim_wff_rv; + wire [73 : 0] slave_xactor_shim_wff_rv$D_IN; + wire slave_xactor_shim_wff_rv$EN; + // ports of submodule f_reset_reqs wire f_reset_reqs$CLR, f_reset_reqs$DEQ, @@ -352,46 +536,6 @@ module mkNear_Mem_IO_AXI4(CLK, f_timer_interrupt_req$ENQ, f_timer_interrupt_req$FULL_N; - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - // rule scheduling signals wire CAN_FIRE_RL_rl_compare, CAN_FIRE_RL_rl_process_rd_req, @@ -399,11 +543,24 @@ module mkNear_Mem_IO_AXI4(CLK, CAN_FIRE_RL_rl_reset, CAN_FIRE_RL_rl_soft_reset, CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, + CAN_FIRE_RL_slave_xactor_do_clear, + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_axi4_slave_ar_arflit, + CAN_FIRE_axi4_slave_aw_awflit, + CAN_FIRE_axi4_slave_b_bready, + CAN_FIRE_axi4_slave_r_rready, + CAN_FIRE_axi4_slave_w_wflit, CAN_FIRE_get_sw_interrupt_req_get, CAN_FIRE_get_timer_interrupt_req_get, CAN_FIRE_server_reset_request_put, @@ -415,11 +572,24 @@ module mkNear_Mem_IO_AXI4(CLK, WILL_FIRE_RL_rl_reset, WILL_FIRE_RL_rl_soft_reset, WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, + WILL_FIRE_RL_slave_xactor_do_clear, + WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_w_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_axi4_slave_ar_arflit, + WILL_FIRE_axi4_slave_aw_awflit, + WILL_FIRE_axi4_slave_b_bready, + WILL_FIRE_axi4_slave_r_rready, + WILL_FIRE_axi4_slave_w_wflit, WILL_FIRE_get_sw_interrupt_req_get, WILL_FIRE_get_timer_interrupt_req_get, WILL_FIRE_server_reset_request_put, @@ -429,73 +599,80 @@ module mkNear_Mem_IO_AXI4(CLK, // inputs to muxes for submodule ports wire MUX_crg_time$port1__write_1__SEL_1, MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1; + MUX_rg_msip$write_1__SEL_1, + MUX_rg_state$write_1__SEL_1, + MUX_rg_state$write_1__SEL_2; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h10050; - reg [31 : 0] v__h10182; - reg [31 : 0] v__h1852; - reg [31 : 0] v__h2269; - reg [31 : 0] v__h2453; - reg [31 : 0] v__h2640; - reg [31 : 0] v__h2878; - reg [31 : 0] v__h2095; - reg [31 : 0] v__h3158; - reg [31 : 0] v__h3384; - reg [31 : 0] v__h8918; - reg [31 : 0] v__h9137; - reg [31 : 0] v__h9462; - reg [31 : 0] v__h9572; - reg [31 : 0] v__h9679; - reg [31 : 0] v__h1846; - reg [31 : 0] v__h2089; - reg [31 : 0] v__h2263; - reg [31 : 0] v__h2447; - reg [31 : 0] v__h2634; - reg [31 : 0] v__h2872; - reg [31 : 0] v__h3152; - reg [31 : 0] v__h3378; - reg [31 : 0] v__h8912; - reg [31 : 0] v__h9131; - reg [31 : 0] v__h9456; - reg [31 : 0] v__h9566; - reg [31 : 0] v__h9673; - reg [31 : 0] v__h10044; - reg [31 : 0] v__h10176; + reg [31 : 0] v__h13099; + reg [31 : 0] v__h13231; + reg [31 : 0] v__h4164; + reg [31 : 0] v__h4672; + reg [31 : 0] v__h4886; + reg [31 : 0] v__h5109; + reg [31 : 0] v__h5435; + reg [31 : 0] v__h4408; + reg [31 : 0] v__h5925; + reg [31 : 0] v__h6181; + reg [31 : 0] v__h11750; + reg [31 : 0] v__h12059; + reg [31 : 0] v__h12451; + reg [31 : 0] v__h12561; + reg [31 : 0] v__h12668; + reg [31 : 0] v__h4158; + reg [31 : 0] v__h4402; + reg [31 : 0] v__h4666; + reg [31 : 0] v__h4880; + reg [31 : 0] v__h5103; + reg [31 : 0] v__h5429; + reg [31 : 0] v__h5919; + reg [31 : 0] v__h6175; + reg [31 : 0] v__h11744; + reg [31 : 0] v__h12053; + reg [31 : 0] v__h12445; + reg [31 : 0] v__h12555; + reg [31 : 0] v__h12662; + reg [31 : 0] v__h13093; + reg [31 : 0] v__h13225; // synopsys translate_on // remaining internal signals - reg [63 : 0] _theResult___fst__h2566; - reg [1 : 0] _theResult___snd__h2567, v__h3508; - wire [63 : 0] byte_addr__h2405, - byte_addr__h3346, - crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189, - mask__h3789, - new_time__h5047, - new_timecmp__h3758, - old_time__h7605, - rdata___1__h2562, - x__h2751, - x__h3800, - x__h5089, - y__h3801, - y__h3802; - wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155, - SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152; - wire [1 : 0] rresp__h2548, v__h3350; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108, - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53, - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102, - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115; + reg [63 : 0] _theResult___fst__h5030; + reg [1 : 0] CASE_byte_addr142_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q1, + CASE_byte_addr837_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q3; + wire [71 : 0] slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4; + wire [66 : 0] IF_slave_xactor_shim_arff_rv_port1__read__9_BI_ETC___d168; + wire [63 : 0] byte_addr__h4837, + byte_addr__h6142, + crg_timecmp_port1__read__53_AND_INV_SEXT_slave_ETC___d292, + mask__h6615, + new_time__h7873, + new_timecmp__h6584, + old_time__h10432, + rdata___1__h5026, + x__h5248, + x__h6626, + x__h7915, + y__h6627, + y__h6628; + wire [7 : 0] SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d255, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d258, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d262, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d265, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d269, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d272, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d276, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d279; + wire [6 : 0] slave_xactor_shim_bff_rvport1__read_BITS_6_TO_0__q2; + wire IF_slave_xactor_shim_awff_rv_port1__read__76_B_ETC___d193, + NOT_cfg_verbosity_read__2_ULE_1_5___d76, + NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69, + rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189, + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116, + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d149, + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184, + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d324; // action method server_reset_request_put assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; @@ -512,58 +689,64 @@ module mkNear_Mem_IO_AXI4(CLK, assign CAN_FIRE_set_addr_map = 1'd1 ; assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; + // action method axi4_slave_aw_awflit + assign CAN_FIRE_axi4_slave_aw_awflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_aw_awflit = axi4_slave_awvalid ; - // value method axi4_slave_m_awready - assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ; + // value method axi4_slave_aw_awready + assign axi4_slave_awready = !slave_xactor_shim_awff_rv[98] ; - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; + // action method axi4_slave_w_wflit + assign CAN_FIRE_axi4_slave_w_wflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_w_wflit = axi4_slave_wvalid ; - // value method axi4_slave_m_wready - assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ; + // value method axi4_slave_w_wready + assign axi4_slave_wready = !slave_xactor_shim_wff_rv[73] ; - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; + // value method axi4_slave_b_bid + assign axi4_slave_bid = + slave_xactor_shim_bff_rvport1__read_BITS_6_TO_0__q2[6:2] ; - // value method axi4_slave_m_bid - assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; + // value method axi4_slave_b_bresp + assign axi4_slave_bresp = + slave_xactor_shim_bff_rvport1__read_BITS_6_TO_0__q2[1:0] ; - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; + // value method axi4_slave_b_bvalid + assign axi4_slave_bvalid = CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek ; - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; + // action method axi4_slave_b_bready + assign CAN_FIRE_axi4_slave_b_bready = 1'd1 ; + assign WILL_FIRE_axi4_slave_b_bready = 1'd1 ; - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; + // action method axi4_slave_ar_arflit + assign CAN_FIRE_axi4_slave_ar_arflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_ar_arflit = axi4_slave_arvalid ; - // value method axi4_slave_m_arready - assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ; + // value method axi4_slave_ar_arready + assign axi4_slave_arready = !slave_xactor_shim_arff_rv[98] ; - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; + // value method axi4_slave_r_rid + assign axi4_slave_rid = + slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4[71:67] ; - // value method axi4_slave_m_rid - assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; + // value method axi4_slave_r_rdata + assign axi4_slave_rdata = + slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4[66:3] ; - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; + // value method axi4_slave_r_rresp + assign axi4_slave_rresp = + slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4[2:1] ; - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; + // value method axi4_slave_r_rlast + assign axi4_slave_rlast = + slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4[0] ; - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; + // value method axi4_slave_r_rvalid + assign axi4_slave_rvalid = CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek ; - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; + // action method axi4_slave_r_rready + assign CAN_FIRE_axi4_slave_r_rready = 1'd1 ; + assign WILL_FIRE_axi4_slave_r_rready = 1'd1 ; // actionvalue method get_timer_interrupt_req_get assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; @@ -619,75 +802,61 @@ module mkNear_Mem_IO_AXI4(CLK, .FULL_N(f_timer_interrupt_req$FULL_N), .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; + assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; + assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; // rule RL_rl_soft_reset assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; + assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; + + // rule RL_slave_xactor_ug_slave_u_aw_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut = + slave_xactor_ug_slave_u_aw_putWire$whas && + slave_xactor_shim_awff_rv[98] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_aw_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut = + !slave_xactor_shim_awff_rv[98] && + slave_xactor_ug_slave_u_aw_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut ; + + // rule RL_slave_xactor_ug_slave_u_w_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut = + slave_xactor_ug_slave_u_w_putWire$whas && + slave_xactor_shim_wff_rv[73] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_w_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut = + !slave_xactor_shim_wff_rv[73] && + slave_xactor_ug_slave_u_w_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_w_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut ; + + // rule RL_slave_xactor_ug_slave_u_ar_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut = + slave_xactor_ug_slave_u_ar_putWire$whas && + slave_xactor_shim_arff_rv[98] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_ar_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut = + !slave_xactor_shim_arff_rv[98] && + slave_xactor_ug_slave_u_ar_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut ; // rule RL_rl_process_rd_req assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && + !slave_xactor_clearing && + slave_xactor_shim_arff_rv$port1__read[98] && + !slave_xactor_shim_rff_rv[72] && rg_state && !f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; @@ -696,7 +865,7 @@ module mkNear_Mem_IO_AXI4(CLK, assign CAN_FIRE_RL_rl_compare = f_timer_interrupt_req$FULL_N && rg_state && rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && + NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69 && !f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; @@ -708,52 +877,216 @@ module mkNear_Mem_IO_AXI4(CLK, // rule RL_rl_process_wr_req assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 && + !slave_xactor_clearing && + slave_xactor_shim_awff_rv$port1__read[98] && + slave_xactor_shim_wff_rv$port1__read[73] && + !slave_xactor_shim_bff_rv[7] && + IF_slave_xactor_shim_awff_rv_port1__read__76_B_ETC___d193 && rg_state && !f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; + // rule RL_slave_xactor_ug_slave_u_b_setPeek + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek = + slave_xactor_shim_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek ; + + // rule RL_slave_xactor_ug_slave_u_b_warnDoDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop = + slave_xactor_ug_slave_u_b_dropWire$whas && + !slave_xactor_shim_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop ; + + // rule RL_slave_xactor_ug_slave_u_b_doDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop = + slave_xactor_shim_bff_rv$port1__read[7] && + slave_xactor_ug_slave_u_b_dropWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop ; + + // rule RL_slave_xactor_ug_slave_u_r_setPeek + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek = + slave_xactor_shim_rff_rv$port1__read[72] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek ; + + // rule RL_slave_xactor_ug_slave_u_r_warnDoDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop = + slave_xactor_ug_slave_u_r_dropWire$whas && + !slave_xactor_shim_rff_rv$port1__read[72] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop ; + + // rule RL_slave_xactor_ug_slave_u_r_doDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop = + slave_xactor_shim_rff_rv$port1__read[72] && + slave_xactor_ug_slave_u_r_dropWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop ; + + // rule RL_slave_xactor_do_clear + assign CAN_FIRE_RL_slave_xactor_do_clear = slave_xactor_clearing ; + assign WILL_FIRE_RL_slave_xactor_do_clear = slave_xactor_clearing ; + // inputs to muxes for submodule ports assign MUX_crg_time$port1__write_1__SEL_1 = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h000000000000BFF8 || - byte_addr__h3346 == 64'h000000000000BFFC) ; + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + (byte_addr__h6142 == 64'h000000000000BFF8 || + byte_addr__h6142 == 64'h000000000000BFFC) ; assign MUX_crg_timecmp$port1__write_1__SEL_1 = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h0000000000004000 || - byte_addr__h3346 == 64'h0000000000004004) ; + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + (byte_addr__h6142 == 64'h0000000000004000 || + byte_addr__h6142 == 64'h0000000000004004) ; assign MUX_rg_msip$write_1__SEL_1 = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ; + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0 && + !rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189 ; + assign MUX_rg_state$write_1__SEL_1 = + f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; + assign MUX_rg_state$write_1__SEL_2 = + !slave_xactor_clearing && f_reset_reqs$EMPTY_N && + f_reset_rsps$FULL_N && + !rg_state ; // inlined wires + assign slave_xactor_ug_slave_u_aw_putWire$wget = + { axi4_slave_awid, + axi4_slave_awaddr, + axi4_slave_awlen, + axi4_slave_awsize, + axi4_slave_awburst, + axi4_slave_awlock, + axi4_slave_awcache, + axi4_slave_awprot, + axi4_slave_awqos, + axi4_slave_awregion } ; + assign slave_xactor_ug_slave_u_aw_putWire$whas = + axi4_slave_awvalid && !slave_xactor_shim_awff_rv[98] ; + assign slave_xactor_ug_slave_u_w_putWire$wget = + { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; + assign slave_xactor_ug_slave_u_w_putWire$whas = + axi4_slave_wvalid && !slave_xactor_shim_wff_rv[73] ; + assign slave_xactor_ug_slave_u_ar_putWire$wget = + { axi4_slave_arid, + axi4_slave_araddr, + axi4_slave_arlen, + axi4_slave_arsize, + axi4_slave_arburst, + axi4_slave_arlock, + axi4_slave_arcache, + axi4_slave_arprot, + axi4_slave_arqos, + axi4_slave_arregion } ; + assign slave_xactor_ug_slave_u_ar_putWire$whas = + axi4_slave_arvalid && !slave_xactor_shim_arff_rv[98] ; + assign slave_xactor_ug_slave_u_b_dropWire$whas = + slave_xactor_shim_bff_rv$port1__read[7] && axi4_slave_bready ; + assign slave_xactor_ug_slave_u_r_dropWire$whas = + slave_xactor_shim_rff_rv$port1__read[72] && axi4_slave_rready ; + assign slave_xactor_shim_awff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_aw_putWire$wget } ; + assign slave_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut ? + slave_xactor_shim_awff_rv$port0__write_1 : + slave_xactor_shim_awff_rv ; + assign slave_xactor_shim_awff_rv$port2__read = + WILL_FIRE_RL_rl_process_wr_req ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_awff_rv$port1__read ; + assign slave_xactor_shim_awff_rv$port3__read = + slave_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_awff_rv$port2__read ; + assign slave_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_w_putWire$wget } ; + assign slave_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut ? + slave_xactor_shim_wff_rv$port0__write_1 : + slave_xactor_shim_wff_rv ; + assign slave_xactor_shim_wff_rv$port2__read = + WILL_FIRE_RL_rl_process_wr_req ? + 74'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_wff_rv$port1__read ; + assign slave_xactor_shim_wff_rv$port3__read = + slave_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_wff_rv$port2__read ; + assign slave_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, + slave_xactor_shim_awff_rv$port1__read[97:93], + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 ? + 2'd3 : + CASE_byte_addr142_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q1 } ; + assign slave_xactor_shim_bff_rv$port1__read = + WILL_FIRE_RL_rl_process_wr_req ? + slave_xactor_shim_bff_rv$port0__write_1 : + slave_xactor_shim_bff_rv ; + assign slave_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop ? + 8'd42 : + slave_xactor_shim_bff_rv$port1__read ; + assign slave_xactor_shim_bff_rv$port3__read = + slave_xactor_clearing ? + 8'd42 : + slave_xactor_shim_bff_rv$port2__read ; + assign slave_xactor_shim_arff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_ar_putWire$wget } ; + assign slave_xactor_shim_arff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut ? + slave_xactor_shim_arff_rv$port0__write_1 : + slave_xactor_shim_arff_rv ; + assign slave_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_rl_process_rd_req ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_arff_rv$port1__read ; + assign slave_xactor_shim_arff_rv$port3__read = + slave_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_arff_rv$port2__read ; + assign slave_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, + slave_xactor_shim_arff_rv$port1__read[97:93], + IF_slave_xactor_shim_arff_rv_port1__read__9_BI_ETC___d168 } ; + assign slave_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_rl_process_rd_req ? + slave_xactor_shim_rff_rv$port0__write_1 : + slave_xactor_shim_rff_rv ; + assign slave_xactor_shim_rff_rv$port2__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop ? + 73'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_rff_rv$port1__read ; + assign slave_xactor_shim_rff_rv$port3__read = + slave_xactor_clearing ? + 73'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_rff_rv$port2__read ; assign crg_time$port0__write_1 = crg_time + 64'd1 ; assign crg_time$EN_port1__write = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h000000000000BFF8 || - byte_addr__h3346 == 64'h000000000000BFFC) || + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + (byte_addr__h6142 == 64'h000000000000BFF8 || + byte_addr__h6142 == 64'h000000000000BFFC) || WILL_FIRE_RL_rl_reset ; assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? new_time__h5047 : 64'd1 ; + MUX_crg_time$port1__write_1__SEL_1 ? new_time__h7873 : 64'd1 ; assign crg_time$port2__read = crg_time$EN_port1__write ? crg_time$port1__write_1 : - old_time__h7605 ; + old_time__h10432 ; assign crg_timecmp$EN_port1__write = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h0000000000004000 || - byte_addr__h3346 == 64'h0000000000004004) || + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + (byte_addr__h6142 == 64'h0000000000004000 || + byte_addr__h6142 == 64'h0000000000004004) || WILL_FIRE_RL_rl_reset ; assign crg_timecmp$port1__write_1 = MUX_crg_timecmp$port1__write_1__SEL_1 ? - new_timecmp__h3758 : + new_timecmp__h6584 : 64'd0 ; assign crg_timecmp$port2__read = crg_timecmp$EN_port1__write ? @@ -782,222 +1115,214 @@ module mkNear_Mem_IO_AXI4(CLK, // register rg_msip assign rg_msip$D_IN = - MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ; + MUX_rg_msip$write_1__SEL_1 && + slave_xactor_shim_wff_rv$port1__read[9] ; assign rg_msip$EN = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0 && + !rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189 || WILL_FIRE_RL_rl_reset ; // register rg_mtip assign rg_mtip$D_IN = !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; + NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69 ; assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; // register rg_state assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; + // register slave_xactor_clearing + assign slave_xactor_clearing$D_IN = !slave_xactor_clearing ; + assign slave_xactor_clearing$EN = + slave_xactor_clearing || WILL_FIRE_RL_rl_reset ; + + // register slave_xactor_shim_arff_rv + assign slave_xactor_shim_arff_rv$D_IN = + slave_xactor_shim_arff_rv$port3__read ; + assign slave_xactor_shim_arff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_awff_rv + assign slave_xactor_shim_awff_rv$D_IN = + slave_xactor_shim_awff_rv$port3__read ; + assign slave_xactor_shim_awff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_bff_rv + assign slave_xactor_shim_bff_rv$D_IN = + slave_xactor_shim_bff_rv$port3__read ; + assign slave_xactor_shim_bff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_rff_rv + assign slave_xactor_shim_rff_rv$D_IN = + slave_xactor_shim_rff_rv$port3__read ; + assign slave_xactor_shim_rff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_wff_rv + assign slave_xactor_shim_wff_rv$D_IN = + slave_xactor_shim_wff_rv$port3__read ; + assign slave_xactor_shim_wff_rv$EN = 1'b1 ; + // submodule f_reset_reqs assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; + assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; + assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; assign f_reset_rsps$DEQ = EN_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ; + assign f_sw_interrupt_req$D_IN = slave_xactor_shim_wff_rv$port1__read[9] ; assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = CAN_FIRE_RL_rl_reset ; + assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; // submodule f_timer_interrupt_req assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; + NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69 ; assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - x__h2751, - rresp__h2548, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3350 } ; - assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_rl_reset ; + assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = + assign IF_slave_xactor_shim_arff_rv_port1__read__9_BI_ETC___d168 = + { x__h5248, + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 ? + 2'd3 : + CASE_byte_addr837_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q3, + 1'd1 } ; + assign IF_slave_xactor_shim_awff_rv_port1__read__76_B_ETC___d193 = + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 ? + slave_xactor_shim_wff_rv$port1__read[73] : + byte_addr__h6142 != 64'h0 || + rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189 || + f_sw_interrupt_req$FULL_N ; + assign NOT_cfg_verbosity_read__2_ULE_1_5___d76 = cfg_verbosity > 4'd1 ; + assign NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69 = crg_time >= crg_timecmp ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 = - {8{slave_xactor_f_wr_data$D_OUT[1]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173 = - {8{slave_xactor_f_wr_data$D_OUT[2]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169 = - {8{slave_xactor_f_wr_data$D_OUT[3]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166 = - {8{slave_xactor_f_wr_data$D_OUT[4]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162 = - {8{slave_xactor_f_wr_data$D_OUT[5]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159 = - {8{slave_xactor_f_wr_data$D_OUT[6]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155 = - {8{slave_xactor_f_wr_data$D_OUT[7]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152 = - {8{slave_xactor_f_wr_data$D_OUT[8]}} ; - assign byte_addr__h2405 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign byte_addr__h3346 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189 = - new_timecmp__h3758 - old_time__h7605 ; - assign mask__h3789 = - { SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173, - SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 } ; - assign new_time__h5047 = x__h5089 | y__h3801 ; - assign new_timecmp__h3758 = x__h3800 | y__h3801 ; - assign old_time__h7605 = + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d255 = + {8{slave_xactor_shim_wff_rv$port1__read[8]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d258 = + {8{slave_xactor_shim_wff_rv$port1__read[7]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d262 = + {8{slave_xactor_shim_wff_rv$port1__read[6]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d265 = + {8{slave_xactor_shim_wff_rv$port1__read[5]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d269 = + {8{slave_xactor_shim_wff_rv$port1__read[4]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d272 = + {8{slave_xactor_shim_wff_rv$port1__read[3]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d276 = + {8{slave_xactor_shim_wff_rv$port1__read[2]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d279 = + {8{slave_xactor_shim_wff_rv$port1__read[1]}} ; + assign byte_addr__h4837 = + slave_xactor_shim_arff_rv$port1__read[92:29] - rg_addr_base ; + assign byte_addr__h6142 = + slave_xactor_shim_awff_rv$port1__read[92:29] - rg_addr_base ; + assign crg_timecmp_port1__read__53_AND_INV_SEXT_slave_ETC___d292 = + new_timecmp__h6584 - old_time__h10432 ; + assign mask__h6615 = + { SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d255, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d258, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d262, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d265, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d269, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d272, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d276, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d279 } ; + assign new_time__h7873 = x__h7915 | y__h6627 ; + assign new_timecmp__h6584 = x__h6626 | y__h6627 ; + assign old_time__h10432 = CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata___1__h2562 = { 63'd0, rg_msip } ; - assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 = - rg_msip == slave_xactor_f_wr_data$D_OUT[9] ; - assign rresp__h2548 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 2'b11 : - _theResult___snd__h2567 ; - assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 = - slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 = - slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 || - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - f_sw_interrupt_req$FULL_N) ; - assign v__h3350 = - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ? - 2'b11 : - v__h3508 ; - assign x__h2751 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? + assign rdata___1__h5026 = { 63'd0, rg_msip } ; + assign rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189 = + rg_msip == slave_xactor_shim_wff_rv$port1__read[9] ; + assign slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 = + slave_xactor_shim_arff_rv$port1__read[92:29] < rg_addr_base ; + assign slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d149 = + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2 ; + assign slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 = + slave_xactor_shim_awff_rv$port1__read[92:29] < rg_addr_base ; + assign slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d324 = + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2 ; + assign slave_xactor_shim_bff_rvport1__read_BITS_6_TO_0__q2 = + slave_xactor_shim_bff_rv$port1__read[6:0] ; + assign slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4 = + slave_xactor_shim_rff_rv$port1__read[71:0] ; + assign x__h5248 = + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 ? 64'd0 : - _theResult___fst__h2566 ; - assign x__h3800 = crg_timecmp & y__h3802 ; - assign x__h5089 = old_time__h7605 & y__h3802 ; - assign y__h3801 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3789 ; - assign y__h3802 = - { ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 } ; - always@(byte_addr__h2405) + _theResult___fst__h5030 ; + assign x__h6626 = crg_timecmp & y__h6628 ; + assign x__h7915 = old_time__h10432 & y__h6628 ; + assign y__h6627 = slave_xactor_shim_wff_rv$port1__read[72:9] & mask__h6615 ; + assign y__h6628 = + { ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d255, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d258, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d262, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d265, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d269, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d272, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d276, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d279 } ; + always@(byte_addr__h6142) begin - case (byte_addr__h2405) + case (byte_addr__h6142) 64'h0, 64'h0000000000000004, 64'h0000000000004000, 64'h0000000000004004, 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___snd__h2567 = 2'b0; - default: _theResult___snd__h2567 = 2'b11; + CASE_byte_addr142_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q1 = 2'd0; + default: CASE_byte_addr142_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q1 = 2'd3; endcase end - always@(byte_addr__h2405 or rdata___1__h2562 or crg_timecmp or crg_time) + always@(byte_addr__h4837 or rdata___1__h5026 or crg_timecmp or crg_time) begin - case (byte_addr__h2405) - 64'h0: _theResult___fst__h2566 = rdata___1__h2562; - 64'h0000000000000004: _theResult___fst__h2566 = 64'd0; + case (byte_addr__h4837) + 64'h0: _theResult___fst__h5030 = rdata___1__h5026; + 64'h0000000000000004: _theResult___fst__h5030 = 64'd0; 64'h0000000000004000, 64'h0000000000004004: - _theResult___fst__h2566 = crg_timecmp; + _theResult___fst__h5030 = crg_timecmp; 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___fst__h2566 = crg_time; - default: _theResult___fst__h2566 = 64'd0; + _theResult___fst__h5030 = crg_time; + default: _theResult___fst__h5030 = 64'd0; endcase end - always@(byte_addr__h3346) + always@(byte_addr__h4837) begin - case (byte_addr__h3346) + case (byte_addr__h4837) 64'h0, 64'h0000000000000004, 64'h0000000000004000, 64'h0000000000004004, 64'h000000000000BFF8, 64'h000000000000BFFC: - v__h3508 = 2'b0; - default: v__h3508 = 2'b11; + CASE_byte_addr837_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q3 = 2'd0; + default: CASE_byte_addr837_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q3 = 2'd3; endcase end @@ -1012,6 +1337,16 @@ module mkNear_Mem_IO_AXI4(CLK, crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; + slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 8'd42; + slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 73'h0AAAAAAAAAAAAAAAAAA; + slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; end else begin @@ -1022,6 +1357,24 @@ module mkNear_Mem_IO_AXI4(CLK, crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; + if (slave_xactor_clearing$EN) + slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + slave_xactor_clearing$D_IN; + if (slave_xactor_shim_arff_rv$EN) + slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_arff_rv$D_IN; + if (slave_xactor_shim_awff_rv$EN) + slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_awff_rv$D_IN; + if (slave_xactor_shim_bff_rv$EN) + slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_bff_rv$D_IN; + if (slave_xactor_shim_rff_rv$EN) + slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_rff_rv$D_IN; + if (slave_xactor_shim_wff_rv$EN) + slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_wff_rv$D_IN; end if (rg_addr_base$EN) rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; @@ -1042,6 +1395,12 @@ module mkNear_Mem_IO_AXI4(CLK, rg_msip = 1'h0; rg_mtip = 1'h0; rg_state = 1'h0; + slave_xactor_clearing = 1'h0; + slave_xactor_shim_arff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_awff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_bff_rv = 8'hAA; + slave_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA; + slave_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -1054,1704 +1413,2024 @@ module mkNear_Mem_IO_AXI4(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h10050 = $stime; + v__h13099 = $stime; #0; end - v__h10044 = v__h10050 / 32'd10; + v__h13093 = v__h13099 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x", - v__h10044, + v__h13093, f_timer_interrupt_req$D_OUT); if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) + if (EN_get_sw_interrupt_req_get && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h10182 = $stime; + v__h13231 = $stime; #0; end - v__h10176 = v__h10182 / 32'd10; + v__h13225 = v__h13231 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) + if (EN_get_sw_interrupt_req_get && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x", - v__h10176, + v__h13225, f_sw_interrupt_req$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) begin - v__h1852 = $stime; + v__h4164 = $stime; #0; end - v__h1846 = v__h1852 / 32'd10; + v__h4158 = v__h4164 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1846); + $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h4158); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h2269 = $stime; + v__h4672 = $stime; #0; end - v__h2263 = v__h2269 / 32'd10; + v__h4666 = v__h4672 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", - v__h2263, + v__h4666, rg_mtip); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) begin - v__h2453 = $stime; + v__h4886 = $stime; #0; end - v__h2447 = v__h2453 / 32'd10; + v__h4880 = v__h4886 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2447); + v__h4880); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("AXI4_Rd_Addr { ", "arid: "); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + !slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) begin - v__h2640 = $stime; + v__h5109 = $stime; #0; end - v__h2634 = v__h2640 / 32'd10; + v__h5103 = v__h5109 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2634); + v__h5103); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[97:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d149) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + !slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h2878 = $stime; + v__h5435 = $stime; #0; end - v__h2872 = v__h2878 / 32'd10; + v__h5429 = v__h5435 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2872); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h5429); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Data { ", "rid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", x__h2751); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", x__h5248); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rresp__h2548); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + (byte_addr__h4837 == 64'h0 || + byte_addr__h4837 == 64'h0000000000004000 || + byte_addr__h4837 == 64'h000000000000BFF8 || + byte_addr__h4837 == 64'h0000000000000004 || + byte_addr__h4837 == 64'h0000000000004004 || + byte_addr__h4837 == 64'h000000000000BFFC)) + $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) + if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h2095 = $stime; + v__h4408 = $stime; #0; end - v__h2089 = v__h2095 / 32'd10; + v__h4402 = v__h4408 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) + if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h2089, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, + v__h4402, + NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69, crg_time, crg_timecmp); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h3158 = $stime; + v__h5925 = $stime; #0; end - v__h3152 = v__h3158 / 32'd10; + v__h5919 = v__h5925 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", - v__h3152, + v__h5919, rg_mtip); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wdata: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) begin - v__h3384 = $stime; + v__h6181 = $stime; #0; end - v__h3378 = v__h3384 / 32'd10; + v__h6175 = v__h6181 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h3378); + v__h6175); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Addr { ", "awid: "); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + !slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Data { ", "wdata: "); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - slave_xactor_f_wr_data$D_OUT[0]) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - !slave_xactor_f_wr_data$D_OUT[0]) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + !slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0 && + !rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" new MSIP = %0d", + slave_xactor_shim_wff_rv$port1__read[9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004000 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" Writing MTIMECMP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004000 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" old MTIMECMP = 0x%0h", crg_timecmp); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3758); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004000 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" new MTIMECMP = 0x%0h", new_timecmp__h6584); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7605); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004000 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" cur MTIME = 0x%0h", old_time__h10432); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004000 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189); + crg_timecmp_port1__read__53_AND_INV_SEXT_slave_ETC___d292); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFF8 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" Writing MTIME"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7605); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFF8 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" old MTIME = 0x%0h", old_time__h10432); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5047); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFF8 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" new MTIME = 0x%0h", new_time__h7873); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004004 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" Writing MTIMECMP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004004 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" old MTIMECMP = 0x%0h", crg_timecmp); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3758); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004004 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" new MTIMECMP = 0x%0h", new_timecmp__h6584); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7605); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004004 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" cur MTIME = 0x%0h", old_time__h10432); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004004 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189); + crg_timecmp_port1__read__53_AND_INV_SEXT_slave_ETC___d292); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFFC && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" Writing MTIME"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7605); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFFC && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" old MTIME = 0x%0h", old_time__h10432); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5047); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFFC && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" new MTIME = 0x%0h", new_time__h7873); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) begin - v__h8918 = $stime; + v__h11750 = $stime; #0; end - v__h8912 = v__h8918 / 32'd10; + v__h11744 = v__h11750 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h8912); + v__h11744); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("AXI4_AWFlit { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[97:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d324) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + !slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("AXI4_WFlit { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[72:9]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC) && - slave_xactor_f_wr_data$D_OUT[0]) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC) && - !slave_xactor_f_wr_data$D_OUT[0]) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + !slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h9137 = $stime; + v__h12059 = $stime; #0; end - v__h9131 = v__h9137 / 32'd10; + v__h12053 = v__h12059 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9131); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h12053); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wdata: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Resp { ", "bid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_BFlit { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", v__h3350); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + (byte_addr__h6142 == 64'h0 || + byte_addr__h6142 == 64'h0000000000004000 || + byte_addr__h6142 == 64'h000000000000BFF8 || + byte_addr__h6142 == 64'h0000000000000004 || + byte_addr__h6142 == 64'h0000000000004004 || + byte_addr__h6142 == 64'h000000000000BFFC)) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h9462 = $stime; + v__h12451 = $stime; #0; end - v__h9456 = v__h9462 / 32'd10; + v__h12445 = v__h12451 / 32'd10; if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9456, + v__h12445, set_addr_map_addr_base); if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h9572 = $stime; + v__h12561 = $stime; #0; end - v__h9566 = v__h9572 / 32'd10; + v__h12555 = v__h12561 / 32'd10; if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9566, + v__h12555, set_addr_map_addr_lim); if (EN_set_addr_map) begin - v__h9679 = $stime; + v__h12668 = $stime; #0; end - v__h9673 = v__h9679 / 32'd10; + v__h12662 = v__h12668 / 32'd10; if (EN_set_addr_map) $display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9673, + v__h12662, set_addr_map_addr_base, set_addr_map_addr_lim); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); end // synopsys translate_on endmodule // mkNear_Mem_IO_AXI4 diff --git a/src_SSITH_P1/Verilog_RTL/mkP1_Core.v b/src_SSITH_P1/Verilog_RTL/mkP1_Core.v index a06532cb..4ec432f9 100644 --- a/src_SSITH_P1/Verilog_RTL/mkP1_Core.v +++ b/src_SSITH_P1/Verilog_RTL/mkP1_Core.v @@ -1,41 +1,40 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:19:01 BST 2019 // // // Ports: // Name I/O size props +// master0_awid O 5 +// master0_awaddr O 64 +// master0_awlen O 8 +// master0_awsize O 3 +// master0_awburst O 2 +// master0_awlock O 1 +// master0_awcache O 4 +// master0_awprot O 3 +// master0_awqos O 4 +// master0_awregion O 4 // master0_awvalid O 1 -// master0_awid O 4 reg -// master0_awaddr O 64 reg -// master0_awlen O 8 reg -// master0_awsize O 3 reg -// master0_awburst O 2 reg -// master0_awlock O 1 reg -// master0_awcache O 4 reg -// master0_awprot O 3 reg -// master0_awqos O 4 reg -// master0_awregion O 4 reg +// master0_wdata O 64 +// master0_wstrb O 8 +// master0_wlast O 1 // master0_wvalid O 1 -// master0_wdata O 64 reg -// master0_wstrb O 8 reg -// master0_wlast O 1 reg // master0_bready O 1 +// master0_arid O 5 +// master0_araddr O 64 +// master0_arlen O 8 +// master0_arsize O 3 +// master0_arburst O 2 +// master0_arlock O 1 +// master0_arcache O 4 +// master0_arprot O 3 +// master0_arqos O 4 +// master0_arregion O 4 // master0_arvalid O 1 -// master0_arid O 4 reg -// master0_araddr O 64 reg -// master0_arlen O 8 reg -// master0_arsize O 3 reg -// master0_arburst O 2 reg -// master0_arlock O 1 reg -// master0_arcache O 4 reg -// master0_arprot O 3 reg -// master0_arqos O 4 reg -// master0_arregion O 4 reg // master0_rready O 1 -// master1_awvalid O 1 reg -// master1_awid O 4 reg +// master1_awid O 5 reg // master1_awaddr O 64 reg // master1_awlen O 8 reg // master1_awsize O 3 reg @@ -45,13 +44,13 @@ // master1_awprot O 3 reg // master1_awqos O 4 reg // master1_awregion O 4 reg -// master1_wvalid O 1 reg +// master1_awvalid O 1 reg // master1_wdata O 64 reg // master1_wstrb O 8 reg // master1_wlast O 1 reg +// master1_wvalid O 1 reg // master1_bready O 1 reg -// master1_arvalid O 1 reg -// master1_arid O 4 reg +// master1_arid O 5 reg // master1_araddr O 64 reg // master1_arlen O 8 reg // master1_arsize O 3 reg @@ -61,6 +60,7 @@ // master1_arprot O 3 reg // master1_arqos O 4 reg // master1_arregion O 4 reg +// master1_arvalid O 1 reg // master1_rready O 1 reg // tv_verifier_info_tx_tvalid O 1 reg // tv_verifier_info_tx_tdata O 608 reg @@ -74,23 +74,19 @@ // RST_N I 1 reset // master0_awready I 1 // master0_wready I 1 -// master0_bvalid I 1 -// master0_bid I 4 reg -// master0_bresp I 2 reg +// master0_bid I 5 +// master0_bresp I 2 // master0_arready I 1 -// master0_rvalid I 1 -// master0_rid I 4 reg -// master0_rdata I 64 reg -// master0_rresp I 2 reg -// master0_rlast I 1 reg +// master0_rid I 5 +// master0_rdata I 64 +// master0_rresp I 2 +// master0_rlast I 1 // master1_awready I 1 // master1_wready I 1 -// master1_bvalid I 1 -// master1_bid I 4 reg +// master1_bid I 5 reg // master1_bresp I 2 reg // master1_arready I 1 -// master1_rvalid I 1 -// master1_rid I 4 reg +// master1_rid I 5 reg // master1_rdata I 64 reg // master1_rresp I 2 reg // master1_rlast I 1 reg @@ -99,10 +95,72 @@ // jtag_tdi I 1 // jtag_tms I 1 // jtag_tclk I 1 +// master0_bvalid I 1 +// master0_rvalid I 1 +// master1_bvalid I 1 +// master1_rvalid I 1 // // Combinational paths from inputs to outputs: -// (master0_awready, master0_wready) -> master0_bready -// (master0_awready, master0_wready) -> master0_rready +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arid +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_araddr +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arlen +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arsize +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arburst +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arlock +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arcache +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arprot +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arqos +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arregion +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_aruser +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arvalid // // @@ -122,8 +180,6 @@ module mkP1_Core(CLK, RST_N, - master0_awvalid, - master0_awid, master0_awaddr, @@ -144,9 +200,9 @@ module mkP1_Core(CLK, master0_awregion, - master0_awready, + master0_awvalid, - master0_wvalid, + master0_awready, master0_wdata, @@ -154,16 +210,16 @@ module mkP1_Core(CLK, master0_wlast, + master0_wvalid, + master0_wready, - master0_bvalid, master0_bid, master0_bresp, + master0_bvalid, master0_bready, - master0_arvalid, - master0_arid, master0_araddr, @@ -184,18 +240,18 @@ module mkP1_Core(CLK, master0_arregion, + master0_arvalid, + master0_arready, - master0_rvalid, master0_rid, master0_rdata, master0_rresp, master0_rlast, + master0_rvalid, master0_rready, - master1_awvalid, - master1_awid, master1_awaddr, @@ -216,9 +272,9 @@ module mkP1_Core(CLK, master1_awregion, - master1_awready, + master1_awvalid, - master1_wvalid, + master1_awready, master1_wdata, @@ -226,16 +282,16 @@ module mkP1_Core(CLK, master1_wlast, + master1_wvalid, + master1_wready, - master1_bvalid, master1_bid, master1_bresp, + master1_bvalid, master1_bready, - master1_arvalid, - master1_arid, master1_araddr, @@ -256,13 +312,15 @@ module mkP1_Core(CLK, master1_arregion, + master1_arvalid, + master1_arready, - master1_rvalid, master1_rid, master1_rdata, master1_rresp, master1_rlast, + master1_rvalid, master1_rready, @@ -293,226 +351,226 @@ module mkP1_Core(CLK, input CLK; input RST_N; - // value method master0_m_awvalid - output master0_awvalid; - - // value method master0_m_awid - output [3 : 0] master0_awid; + // value method master0_aw_awid + output [4 : 0] master0_awid; - // value method master0_m_awaddr + // value method master0_aw_awaddr output [63 : 0] master0_awaddr; - // value method master0_m_awlen + // value method master0_aw_awlen output [7 : 0] master0_awlen; - // value method master0_m_awsize + // value method master0_aw_awsize output [2 : 0] master0_awsize; - // value method master0_m_awburst + // value method master0_aw_awburst output [1 : 0] master0_awburst; - // value method master0_m_awlock + // value method master0_aw_awlock output master0_awlock; - // value method master0_m_awcache + // value method master0_aw_awcache output [3 : 0] master0_awcache; - // value method master0_m_awprot + // value method master0_aw_awprot output [2 : 0] master0_awprot; - // value method master0_m_awqos + // value method master0_aw_awqos output [3 : 0] master0_awqos; - // value method master0_m_awregion + // value method master0_aw_awregion output [3 : 0] master0_awregion; - // value method master0_m_awuser + // value method master0_aw_awuser - // action method master0_m_awready - input master0_awready; + // value method master0_aw_awvalid + output master0_awvalid; - // value method master0_m_wvalid - output master0_wvalid; + // action method master0_aw_awready + input master0_awready; - // value method master0_m_wdata + // value method master0_w_wdata output [63 : 0] master0_wdata; - // value method master0_m_wstrb + // value method master0_w_wstrb output [7 : 0] master0_wstrb; - // value method master0_m_wlast + // value method master0_w_wlast output master0_wlast; - // value method master0_m_wuser + // value method master0_w_wuser - // action method master0_m_wready + // value method master0_w_wvalid + output master0_wvalid; + + // action method master0_w_wready input master0_wready; - // action method master0_m_bvalid - input master0_bvalid; - input [3 : 0] master0_bid; + // action method master0_b_bflit + input [4 : 0] master0_bid; input [1 : 0] master0_bresp; + input master0_bvalid; - // value method master0_m_bready + // value method master0_b_bready output master0_bready; - // value method master0_m_arvalid - output master0_arvalid; + // value method master0_ar_arid + output [4 : 0] master0_arid; - // value method master0_m_arid - output [3 : 0] master0_arid; - - // value method master0_m_araddr + // value method master0_ar_araddr output [63 : 0] master0_araddr; - // value method master0_m_arlen + // value method master0_ar_arlen output [7 : 0] master0_arlen; - // value method master0_m_arsize + // value method master0_ar_arsize output [2 : 0] master0_arsize; - // value method master0_m_arburst + // value method master0_ar_arburst output [1 : 0] master0_arburst; - // value method master0_m_arlock + // value method master0_ar_arlock output master0_arlock; - // value method master0_m_arcache + // value method master0_ar_arcache output [3 : 0] master0_arcache; - // value method master0_m_arprot + // value method master0_ar_arprot output [2 : 0] master0_arprot; - // value method master0_m_arqos + // value method master0_ar_arqos output [3 : 0] master0_arqos; - // value method master0_m_arregion + // value method master0_ar_arregion output [3 : 0] master0_arregion; - // value method master0_m_aruser + // value method master0_ar_aruser + + // value method master0_ar_arvalid + output master0_arvalid; - // action method master0_m_arready + // action method master0_ar_arready input master0_arready; - // action method master0_m_rvalid - input master0_rvalid; - input [3 : 0] master0_rid; + // action method master0_r_rflit + input [4 : 0] master0_rid; input [63 : 0] master0_rdata; input [1 : 0] master0_rresp; input master0_rlast; + input master0_rvalid; - // value method master0_m_rready + // value method master0_r_rready output master0_rready; - // value method master1_m_awvalid - output master1_awvalid; - - // value method master1_m_awid - output [3 : 0] master1_awid; + // value method master1_aw_awid + output [4 : 0] master1_awid; - // value method master1_m_awaddr + // value method master1_aw_awaddr output [63 : 0] master1_awaddr; - // value method master1_m_awlen + // value method master1_aw_awlen output [7 : 0] master1_awlen; - // value method master1_m_awsize + // value method master1_aw_awsize output [2 : 0] master1_awsize; - // value method master1_m_awburst + // value method master1_aw_awburst output [1 : 0] master1_awburst; - // value method master1_m_awlock + // value method master1_aw_awlock output master1_awlock; - // value method master1_m_awcache + // value method master1_aw_awcache output [3 : 0] master1_awcache; - // value method master1_m_awprot + // value method master1_aw_awprot output [2 : 0] master1_awprot; - // value method master1_m_awqos + // value method master1_aw_awqos output [3 : 0] master1_awqos; - // value method master1_m_awregion + // value method master1_aw_awregion output [3 : 0] master1_awregion; - // value method master1_m_awuser + // value method master1_aw_awuser - // action method master1_m_awready - input master1_awready; + // value method master1_aw_awvalid + output master1_awvalid; - // value method master1_m_wvalid - output master1_wvalid; + // action method master1_aw_awready + input master1_awready; - // value method master1_m_wdata + // value method master1_w_wdata output [63 : 0] master1_wdata; - // value method master1_m_wstrb + // value method master1_w_wstrb output [7 : 0] master1_wstrb; - // value method master1_m_wlast + // value method master1_w_wlast output master1_wlast; - // value method master1_m_wuser + // value method master1_w_wuser - // action method master1_m_wready + // value method master1_w_wvalid + output master1_wvalid; + + // action method master1_w_wready input master1_wready; - // action method master1_m_bvalid - input master1_bvalid; - input [3 : 0] master1_bid; + // action method master1_b_bflit + input [4 : 0] master1_bid; input [1 : 0] master1_bresp; + input master1_bvalid; - // value method master1_m_bready + // value method master1_b_bready output master1_bready; - // value method master1_m_arvalid - output master1_arvalid; - - // value method master1_m_arid - output [3 : 0] master1_arid; + // value method master1_ar_arid + output [4 : 0] master1_arid; - // value method master1_m_araddr + // value method master1_ar_araddr output [63 : 0] master1_araddr; - // value method master1_m_arlen + // value method master1_ar_arlen output [7 : 0] master1_arlen; - // value method master1_m_arsize + // value method master1_ar_arsize output [2 : 0] master1_arsize; - // value method master1_m_arburst + // value method master1_ar_arburst output [1 : 0] master1_arburst; - // value method master1_m_arlock + // value method master1_ar_arlock output master1_arlock; - // value method master1_m_arcache + // value method master1_ar_arcache output [3 : 0] master1_arcache; - // value method master1_m_arprot + // value method master1_ar_arprot output [2 : 0] master1_arprot; - // value method master1_m_arqos + // value method master1_ar_arqos output [3 : 0] master1_arqos; - // value method master1_m_arregion + // value method master1_ar_arregion output [3 : 0] master1_arregion; - // value method master1_m_aruser + // value method master1_ar_aruser - // action method master1_m_arready + // value method master1_ar_arvalid + output master1_arvalid; + + // action method master1_ar_arready input master1_arready; - // action method master1_m_rvalid - input master1_rvalid; - input [3 : 0] master1_rid; + // action method master1_r_rflit + input [4 : 0] master1_rid; input [63 : 0] master1_rdata; input [1 : 0] master1_rresp; input master1_rlast; + input master1_rvalid; - // value method master1_m_rready + // value method master1_r_rready output master1_rready; // action method interrupt_reqs @@ -573,20 +631,17 @@ module mkP1_Core(CLK, master1_arlen, master1_awlen, master1_wstrb; + wire [4 : 0] master0_arid, master0_awid, master1_arid, master1_awid; wire [3 : 0] master0_arcache, - master0_arid, master0_arqos, master0_arregion, master0_awcache, - master0_awid, master0_awqos, master0_awregion, master1_arcache, - master1_arid, master1_arqos, master1_arregion, master1_awcache, - master1_awid, master1_awqos, master1_awregion; wire [2 : 0] master0_arprot, @@ -625,7 +680,7 @@ module mkP1_Core(CLK, // inlined wires wire [40 : 0] bus_dmi_req_data_wire$wget; - wire bus_dmi_rsp_fifof_enqueueing$whas; + wire bus_dmi_rsp_fifof_x_wire$whas; // register bus_dmi_rsp_fifof_cntr_r reg [1 : 0] bus_dmi_rsp_fifof_cntr_r; @@ -678,26 +733,26 @@ module mkP1_Core(CLK, core$cpu_imem_master_awlen, core$cpu_imem_master_wstrb; wire [6 : 0] core$dm_dmi_read_addr_dm_addr, core$dm_dmi_write_dm_addr; + wire [4 : 0] core$cpu_dmem_master_arid, + core$cpu_dmem_master_awid, + core$cpu_dmem_master_bid, + core$cpu_dmem_master_rid, + core$cpu_imem_master_arid, + core$cpu_imem_master_awid, + core$cpu_imem_master_bid, + core$cpu_imem_master_rid; wire [3 : 0] core$cpu_dmem_master_arcache, - core$cpu_dmem_master_arid, core$cpu_dmem_master_arqos, core$cpu_dmem_master_arregion, core$cpu_dmem_master_awcache, - core$cpu_dmem_master_awid, core$cpu_dmem_master_awqos, core$cpu_dmem_master_awregion, - core$cpu_dmem_master_bid, - core$cpu_dmem_master_rid, core$cpu_imem_master_arcache, - core$cpu_imem_master_arid, core$cpu_imem_master_arqos, core$cpu_imem_master_arregion, core$cpu_imem_master_awcache, - core$cpu_imem_master_awid, core$cpu_imem_master_awqos, core$cpu_imem_master_awregion, - core$cpu_imem_master_bid, - core$cpu_imem_master_rid, core$set_verbosity_verbosity; wire [2 : 0] core$cpu_dmem_master_arprot, core$cpu_dmem_master_arsize, @@ -833,16 +888,16 @@ module mkP1_Core(CLK, CAN_FIRE_jtag_tclk, CAN_FIRE_jtag_tdi, CAN_FIRE_jtag_tms, - CAN_FIRE_master0_m_arready, - CAN_FIRE_master0_m_awready, - CAN_FIRE_master0_m_bvalid, - CAN_FIRE_master0_m_rvalid, - CAN_FIRE_master0_m_wready, - CAN_FIRE_master1_m_arready, - CAN_FIRE_master1_m_awready, - CAN_FIRE_master1_m_bvalid, - CAN_FIRE_master1_m_rvalid, - CAN_FIRE_master1_m_wready, + CAN_FIRE_master0_ar_arready, + CAN_FIRE_master0_aw_awready, + CAN_FIRE_master0_b_bflit, + CAN_FIRE_master0_r_rflit, + CAN_FIRE_master0_w_wready, + CAN_FIRE_master1_ar_arready, + CAN_FIRE_master1_aw_awready, + CAN_FIRE_master1_b_bflit, + CAN_FIRE_master1_r_rflit, + CAN_FIRE_master1_w_wready, CAN_FIRE_tv_verifier_info_tx_m_tready, WILL_FIRE_RL_bus_dmi_req_do_enq, WILL_FIRE_RL_bus_dmi_rsp_do_deq, @@ -871,16 +926,16 @@ module mkP1_Core(CLK, WILL_FIRE_jtag_tclk, WILL_FIRE_jtag_tdi, WILL_FIRE_jtag_tms, - WILL_FIRE_master0_m_arready, - WILL_FIRE_master0_m_awready, - WILL_FIRE_master0_m_bvalid, - WILL_FIRE_master0_m_rvalid, - WILL_FIRE_master0_m_wready, - WILL_FIRE_master1_m_arready, - WILL_FIRE_master1_m_awready, - WILL_FIRE_master1_m_bvalid, - WILL_FIRE_master1_m_rvalid, - WILL_FIRE_master1_m_wready, + WILL_FIRE_master0_ar_arready, + WILL_FIRE_master0_aw_awready, + WILL_FIRE_master0_b_bflit, + WILL_FIRE_master0_r_rflit, + WILL_FIRE_master0_w_wready, + WILL_FIRE_master1_ar_arready, + WILL_FIRE_master1_aw_awready, + WILL_FIRE_master1_b_bflit, + WILL_FIRE_master1_r_rflit, + WILL_FIRE_master1_w_wready, WILL_FIRE_tv_verifier_info_tx_m_tready; // inputs to muxes for submodule ports @@ -907,212 +962,212 @@ module mkP1_Core(CLK, assign CLK_jtag_tclk_out = jtagtap$CLK_jtag_tclk_out ; assign CLK_GATE_jtag_tclk_out = 1'b1 ; - // value method master0_m_awvalid - assign master0_awvalid = core$cpu_imem_master_awvalid ; - - // value method master0_m_awid + // value method master0_aw_awid assign master0_awid = core$cpu_imem_master_awid ; - // value method master0_m_awaddr + // value method master0_aw_awaddr assign master0_awaddr = core$cpu_imem_master_awaddr ; - // value method master0_m_awlen + // value method master0_aw_awlen assign master0_awlen = core$cpu_imem_master_awlen ; - // value method master0_m_awsize + // value method master0_aw_awsize assign master0_awsize = core$cpu_imem_master_awsize ; - // value method master0_m_awburst + // value method master0_aw_awburst assign master0_awburst = core$cpu_imem_master_awburst ; - // value method master0_m_awlock + // value method master0_aw_awlock assign master0_awlock = core$cpu_imem_master_awlock ; - // value method master0_m_awcache + // value method master0_aw_awcache assign master0_awcache = core$cpu_imem_master_awcache ; - // value method master0_m_awprot + // value method master0_aw_awprot assign master0_awprot = core$cpu_imem_master_awprot ; - // value method master0_m_awqos + // value method master0_aw_awqos assign master0_awqos = core$cpu_imem_master_awqos ; - // value method master0_m_awregion + // value method master0_aw_awregion assign master0_awregion = core$cpu_imem_master_awregion ; - // action method master0_m_awready - assign CAN_FIRE_master0_m_awready = 1'd1 ; - assign WILL_FIRE_master0_m_awready = 1'd1 ; + // value method master0_aw_awvalid + assign master0_awvalid = core$cpu_imem_master_awvalid ; - // value method master0_m_wvalid - assign master0_wvalid = core$cpu_imem_master_wvalid ; + // action method master0_aw_awready + assign CAN_FIRE_master0_aw_awready = 1'd1 ; + assign WILL_FIRE_master0_aw_awready = 1'd1 ; - // value method master0_m_wdata + // value method master0_w_wdata assign master0_wdata = core$cpu_imem_master_wdata ; - // value method master0_m_wstrb + // value method master0_w_wstrb assign master0_wstrb = core$cpu_imem_master_wstrb ; - // value method master0_m_wlast + // value method master0_w_wlast assign master0_wlast = core$cpu_imem_master_wlast ; - // action method master0_m_wready - assign CAN_FIRE_master0_m_wready = 1'd1 ; - assign WILL_FIRE_master0_m_wready = 1'd1 ; + // value method master0_w_wvalid + assign master0_wvalid = core$cpu_imem_master_wvalid ; - // action method master0_m_bvalid - assign CAN_FIRE_master0_m_bvalid = 1'd1 ; - assign WILL_FIRE_master0_m_bvalid = 1'd1 ; + // action method master0_w_wready + assign CAN_FIRE_master0_w_wready = 1'd1 ; + assign WILL_FIRE_master0_w_wready = 1'd1 ; - // value method master0_m_bready - assign master0_bready = core$cpu_imem_master_bready ; + // action method master0_b_bflit + assign CAN_FIRE_master0_b_bflit = 1'd1 ; + assign WILL_FIRE_master0_b_bflit = master0_bvalid ; - // value method master0_m_arvalid - assign master0_arvalid = core$cpu_imem_master_arvalid ; + // value method master0_b_bready + assign master0_bready = core$cpu_imem_master_bready ; - // value method master0_m_arid + // value method master0_ar_arid assign master0_arid = core$cpu_imem_master_arid ; - // value method master0_m_araddr + // value method master0_ar_araddr assign master0_araddr = core$cpu_imem_master_araddr ; - // value method master0_m_arlen + // value method master0_ar_arlen assign master0_arlen = core$cpu_imem_master_arlen ; - // value method master0_m_arsize + // value method master0_ar_arsize assign master0_arsize = core$cpu_imem_master_arsize ; - // value method master0_m_arburst + // value method master0_ar_arburst assign master0_arburst = core$cpu_imem_master_arburst ; - // value method master0_m_arlock + // value method master0_ar_arlock assign master0_arlock = core$cpu_imem_master_arlock ; - // value method master0_m_arcache + // value method master0_ar_arcache assign master0_arcache = core$cpu_imem_master_arcache ; - // value method master0_m_arprot + // value method master0_ar_arprot assign master0_arprot = core$cpu_imem_master_arprot ; - // value method master0_m_arqos + // value method master0_ar_arqos assign master0_arqos = core$cpu_imem_master_arqos ; - // value method master0_m_arregion + // value method master0_ar_arregion assign master0_arregion = core$cpu_imem_master_arregion ; - // action method master0_m_arready - assign CAN_FIRE_master0_m_arready = 1'd1 ; - assign WILL_FIRE_master0_m_arready = 1'd1 ; + // value method master0_ar_arvalid + assign master0_arvalid = core$cpu_imem_master_arvalid ; - // action method master0_m_rvalid - assign CAN_FIRE_master0_m_rvalid = 1'd1 ; - assign WILL_FIRE_master0_m_rvalid = 1'd1 ; + // action method master0_ar_arready + assign CAN_FIRE_master0_ar_arready = 1'd1 ; + assign WILL_FIRE_master0_ar_arready = 1'd1 ; - // value method master0_m_rready - assign master0_rready = core$cpu_imem_master_rready ; + // action method master0_r_rflit + assign CAN_FIRE_master0_r_rflit = 1'd1 ; + assign WILL_FIRE_master0_r_rflit = master0_rvalid ; - // value method master1_m_awvalid - assign master1_awvalid = core$cpu_dmem_master_awvalid ; + // value method master0_r_rready + assign master0_rready = core$cpu_imem_master_rready ; - // value method master1_m_awid + // value method master1_aw_awid assign master1_awid = core$cpu_dmem_master_awid ; - // value method master1_m_awaddr + // value method master1_aw_awaddr assign master1_awaddr = core$cpu_dmem_master_awaddr ; - // value method master1_m_awlen + // value method master1_aw_awlen assign master1_awlen = core$cpu_dmem_master_awlen ; - // value method master1_m_awsize + // value method master1_aw_awsize assign master1_awsize = core$cpu_dmem_master_awsize ; - // value method master1_m_awburst + // value method master1_aw_awburst assign master1_awburst = core$cpu_dmem_master_awburst ; - // value method master1_m_awlock + // value method master1_aw_awlock assign master1_awlock = core$cpu_dmem_master_awlock ; - // value method master1_m_awcache + // value method master1_aw_awcache assign master1_awcache = core$cpu_dmem_master_awcache ; - // value method master1_m_awprot + // value method master1_aw_awprot assign master1_awprot = core$cpu_dmem_master_awprot ; - // value method master1_m_awqos + // value method master1_aw_awqos assign master1_awqos = core$cpu_dmem_master_awqos ; - // value method master1_m_awregion + // value method master1_aw_awregion assign master1_awregion = core$cpu_dmem_master_awregion ; - // action method master1_m_awready - assign CAN_FIRE_master1_m_awready = 1'd1 ; - assign WILL_FIRE_master1_m_awready = 1'd1 ; + // value method master1_aw_awvalid + assign master1_awvalid = core$cpu_dmem_master_awvalid ; - // value method master1_m_wvalid - assign master1_wvalid = core$cpu_dmem_master_wvalid ; + // action method master1_aw_awready + assign CAN_FIRE_master1_aw_awready = 1'd1 ; + assign WILL_FIRE_master1_aw_awready = 1'd1 ; - // value method master1_m_wdata + // value method master1_w_wdata assign master1_wdata = core$cpu_dmem_master_wdata ; - // value method master1_m_wstrb + // value method master1_w_wstrb assign master1_wstrb = core$cpu_dmem_master_wstrb ; - // value method master1_m_wlast + // value method master1_w_wlast assign master1_wlast = core$cpu_dmem_master_wlast ; - // action method master1_m_wready - assign CAN_FIRE_master1_m_wready = 1'd1 ; - assign WILL_FIRE_master1_m_wready = 1'd1 ; + // value method master1_w_wvalid + assign master1_wvalid = core$cpu_dmem_master_wvalid ; - // action method master1_m_bvalid - assign CAN_FIRE_master1_m_bvalid = 1'd1 ; - assign WILL_FIRE_master1_m_bvalid = 1'd1 ; + // action method master1_w_wready + assign CAN_FIRE_master1_w_wready = 1'd1 ; + assign WILL_FIRE_master1_w_wready = 1'd1 ; - // value method master1_m_bready - assign master1_bready = core$cpu_dmem_master_bready ; + // action method master1_b_bflit + assign CAN_FIRE_master1_b_bflit = 1'd1 ; + assign WILL_FIRE_master1_b_bflit = master1_bvalid ; - // value method master1_m_arvalid - assign master1_arvalid = core$cpu_dmem_master_arvalid ; + // value method master1_b_bready + assign master1_bready = core$cpu_dmem_master_bready ; - // value method master1_m_arid + // value method master1_ar_arid assign master1_arid = core$cpu_dmem_master_arid ; - // value method master1_m_araddr + // value method master1_ar_araddr assign master1_araddr = core$cpu_dmem_master_araddr ; - // value method master1_m_arlen + // value method master1_ar_arlen assign master1_arlen = core$cpu_dmem_master_arlen ; - // value method master1_m_arsize + // value method master1_ar_arsize assign master1_arsize = core$cpu_dmem_master_arsize ; - // value method master1_m_arburst + // value method master1_ar_arburst assign master1_arburst = core$cpu_dmem_master_arburst ; - // value method master1_m_arlock + // value method master1_ar_arlock assign master1_arlock = core$cpu_dmem_master_arlock ; - // value method master1_m_arcache + // value method master1_ar_arcache assign master1_arcache = core$cpu_dmem_master_arcache ; - // value method master1_m_arprot + // value method master1_ar_arprot assign master1_arprot = core$cpu_dmem_master_arprot ; - // value method master1_m_arqos + // value method master1_ar_arqos assign master1_arqos = core$cpu_dmem_master_arqos ; - // value method master1_m_arregion + // value method master1_ar_arregion assign master1_arregion = core$cpu_dmem_master_arregion ; - // action method master1_m_arready - assign CAN_FIRE_master1_m_arready = 1'd1 ; - assign WILL_FIRE_master1_m_arready = 1'd1 ; + // value method master1_ar_arvalid + assign master1_arvalid = core$cpu_dmem_master_arvalid ; - // action method master1_m_rvalid - assign CAN_FIRE_master1_m_rvalid = 1'd1 ; - assign WILL_FIRE_master1_m_rvalid = 1'd1 ; + // action method master1_ar_arready + assign CAN_FIRE_master1_ar_arready = 1'd1 ; + assign WILL_FIRE_master1_ar_arready = 1'd1 ; - // value method master1_m_rready + // action method master1_r_rflit + assign CAN_FIRE_master1_r_rflit = 1'd1 ; + assign WILL_FIRE_master1_r_rflit = master1_rvalid ; + + // value method master1_r_rready assign master1_rready = core$cpu_dmem_master_rready ; // action method interrupt_reqs @@ -1187,23 +1242,19 @@ module mkP1_Core(CLK, .cpu_dmem_master_awready(core$cpu_dmem_master_awready), .cpu_dmem_master_bid(core$cpu_dmem_master_bid), .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata), .cpu_dmem_master_rid(core$cpu_dmem_master_rid), .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast), .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), .cpu_dmem_master_wready(core$cpu_dmem_master_wready), .cpu_imem_master_arready(core$cpu_imem_master_arready), .cpu_imem_master_awready(core$cpu_imem_master_awready), .cpu_imem_master_bid(core$cpu_imem_master_bid), .cpu_imem_master_bresp(core$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), .cpu_imem_master_rdata(core$cpu_imem_master_rdata), .cpu_imem_master_rid(core$cpu_imem_master_rid), .cpu_imem_master_rlast(core$cpu_imem_master_rlast), .cpu_imem_master_rresp(core$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), .cpu_imem_master_wready(core$cpu_imem_master_wready), .cpu_reset_server_request_put(core$cpu_reset_server_request_put), .dm_dmi_read_addr_dm_addr(core$dm_dmi_read_addr_dm_addr), @@ -1216,6 +1267,10 @@ module mkP1_Core(CLK, .EN_set_verbosity(core$EN_set_verbosity), .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put), .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get), + .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), + .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), + .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), + .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), .EN_tv_verifier_info_get_get(core$EN_tv_verifier_info_get_get), .EN_dm_dmi_read_addr(core$EN_dm_dmi_read_addr), .EN_dm_dmi_read_data(core$EN_dm_dmi_read_data), @@ -1226,7 +1281,6 @@ module mkP1_Core(CLK, .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put), .cpu_reset_server_response_get(core$cpu_reset_server_response_get), .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), .cpu_imem_master_awid(core$cpu_imem_master_awid), .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr), .cpu_imem_master_awlen(core$cpu_imem_master_awlen), @@ -1237,12 +1291,12 @@ module mkP1_Core(CLK, .cpu_imem_master_awprot(core$cpu_imem_master_awprot), .cpu_imem_master_awqos(core$cpu_imem_master_awqos), .cpu_imem_master_awregion(core$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), + .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), .cpu_imem_master_wdata(core$cpu_imem_master_wdata), .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb), .cpu_imem_master_wlast(core$cpu_imem_master_wlast), + .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), .cpu_imem_master_bready(core$cpu_imem_master_bready), - .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), .cpu_imem_master_arid(core$cpu_imem_master_arid), .cpu_imem_master_araddr(core$cpu_imem_master_araddr), .cpu_imem_master_arlen(core$cpu_imem_master_arlen), @@ -1253,8 +1307,8 @@ module mkP1_Core(CLK, .cpu_imem_master_arprot(core$cpu_imem_master_arprot), .cpu_imem_master_arqos(core$cpu_imem_master_arqos), .cpu_imem_master_arregion(core$cpu_imem_master_arregion), + .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), .cpu_imem_master_rready(core$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), .cpu_dmem_master_awid(core$cpu_dmem_master_awid), .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr), .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen), @@ -1265,12 +1319,12 @@ module mkP1_Core(CLK, .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot), .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos), .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), + .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata), .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb), .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast), + .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), .cpu_dmem_master_bready(core$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), .cpu_dmem_master_arid(core$cpu_dmem_master_arid), .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr), .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen), @@ -1281,6 +1335,7 @@ module mkP1_Core(CLK, .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot), .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos), .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion), + .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), .cpu_dmem_master_rready(core$cpu_dmem_master_rready), .tv_verifier_info_get_get(core$tv_verifier_info_get_get), .RDY_tv_verifier_info_get_get(core$RDY_tv_verifier_info_get_get), @@ -1417,8 +1472,7 @@ module mkP1_Core(CLK, // rule RL_bus_dmi_rsp_fifof_incCtr assign CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr = - bus_dmi_rsp_fifof_enqueueing$whas && - bus_dmi_rsp_fifof_enqueueing$whas && + bus_dmi_rsp_fifof_x_wire$whas && bus_dmi_rsp_fifof_x_wire$whas && !CAN_FIRE_RL_bus_dmi_rsp_do_deq ; assign WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr = CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr ; @@ -1426,15 +1480,15 @@ module mkP1_Core(CLK, // rule RL_bus_dmi_rsp_fifof_decCtr assign CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr = CAN_FIRE_RL_bus_dmi_rsp_do_deq && - !bus_dmi_rsp_fifof_enqueueing$whas ; + !bus_dmi_rsp_fifof_x_wire$whas ; assign WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr = CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // rule RL_bus_dmi_rsp_fifof_both assign CAN_FIRE_RL_bus_dmi_rsp_fifof_both = - bus_dmi_rsp_fifof_enqueueing$whas && + bus_dmi_rsp_fifof_x_wire$whas && CAN_FIRE_RL_bus_dmi_rsp_do_deq && - bus_dmi_rsp_fifof_enqueueing$whas ; + bus_dmi_rsp_fifof_x_wire$whas ; assign WILL_FIRE_RL_bus_dmi_rsp_fifof_both = CAN_FIRE_RL_bus_dmi_rsp_fifof_both ; @@ -1475,7 +1529,7 @@ module mkP1_Core(CLK, { 1'd1, core$ndm_reset_client_request_get } ; // inlined wires - assign bus_dmi_rsp_fifof_enqueueing$whas = + assign bus_dmi_rsp_fifof_x_wire$whas = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 || WILL_FIRE_RL_rl_dmi_rsp_cpu ; @@ -1600,23 +1654,19 @@ module mkP1_Core(CLK, assign core$cpu_dmem_master_awready = master1_awready ; assign core$cpu_dmem_master_bid = master1_bid ; assign core$cpu_dmem_master_bresp = master1_bresp ; - assign core$cpu_dmem_master_bvalid = master1_bvalid ; assign core$cpu_dmem_master_rdata = master1_rdata ; assign core$cpu_dmem_master_rid = master1_rid ; assign core$cpu_dmem_master_rlast = master1_rlast ; assign core$cpu_dmem_master_rresp = master1_rresp ; - assign core$cpu_dmem_master_rvalid = master1_rvalid ; assign core$cpu_dmem_master_wready = master1_wready ; assign core$cpu_imem_master_arready = master0_arready ; assign core$cpu_imem_master_awready = master0_awready ; assign core$cpu_imem_master_bid = master0_bid ; assign core$cpu_imem_master_bresp = master0_bresp ; - assign core$cpu_imem_master_bvalid = master0_bvalid ; assign core$cpu_imem_master_rdata = master0_rdata ; assign core$cpu_imem_master_rid = master0_rid ; assign core$cpu_imem_master_rlast = master0_rlast ; assign core$cpu_imem_master_rresp = master0_rresp ; - assign core$cpu_imem_master_rvalid = master0_rvalid ; assign core$cpu_imem_master_wready = master0_wready ; assign core$cpu_reset_server_request_put = !rg_ndm_reset[1] || rg_ndm_reset[0] ; @@ -1632,6 +1682,10 @@ module mkP1_Core(CLK, assign core$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; assign core$EN_cpu_reset_server_response_get = CAN_FIRE_RL_rl_reset_response ; + assign core$cpu_imem_master_bvalid = master0_bvalid ; + assign core$cpu_imem_master_rvalid = master0_rvalid ; + assign core$cpu_dmem_master_bvalid = master1_bvalid ; + assign core$cpu_dmem_master_rvalid = master1_rvalid ; assign core$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ; assign core$EN_dm_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && diff --git a/src_SSITH_P1/Verilog_RTL/mkPLIC_16_2_7.v b/src_SSITH_P1/Verilog_RTL/mkPLIC_16_2_7.v index f727e005..2ec7e3a0 100644 --- a/src_SSITH_P1/Verilog_RTL/mkPLIC_16_2_7.v +++ b/src_SSITH_P1/Verilog_RTL/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:26 BST 2019 // // // Ports: @@ -11,17 +11,17 @@ // RDY_server_reset_request_put O 1 reg // RDY_server_reset_response_get O 1 reg // RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg +// axi4_slave_awready O 1 +// axi4_slave_wready O 1 +// axi4_slave_bid O 5 +// axi4_slave_bresp O 2 +// axi4_slave_bvalid O 1 +// axi4_slave_arready O 1 +// axi4_slave_rid O 5 +// axi4_slave_rdata O 64 +// axi4_slave_rresp O 2 +// axi4_slave_rlast O 1 +// axi4_slave_rvalid O 1 // v_targets_0_m_eip O 1 // v_targets_1_m_eip O 1 // CLK I 1 clock @@ -29,33 +29,30 @@ // set_verbosity_verbosity I 4 reg // set_addr_map_addr_base I 64 reg // set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg +// axi4_slave_awid I 5 +// axi4_slave_awaddr I 64 +// axi4_slave_awlen I 8 +// axi4_slave_awsize I 3 +// axi4_slave_awburst I 2 +// axi4_slave_awlock I 1 +// axi4_slave_awcache I 4 +// axi4_slave_awprot I 3 +// axi4_slave_awqos I 4 +// axi4_slave_awregion I 4 +// axi4_slave_wdata I 64 +// axi4_slave_wstrb I 8 +// axi4_slave_wlast I 1 // axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg +// axi4_slave_arid I 5 +// axi4_slave_araddr I 64 +// axi4_slave_arlen I 8 +// axi4_slave_arsize I 3 +// axi4_slave_arburst I 2 +// axi4_slave_arlock I 1 +// axi4_slave_arcache I 4 +// axi4_slave_arprot I 3 +// axi4_slave_arqos I 4 +// axi4_slave_arregion I 4 // axi4_slave_rready I 1 // v_sources_0_m_interrupt_req_set_not_clear I 1 // v_sources_1_m_interrupt_req_set_not_clear I 1 @@ -78,8 +75,181 @@ // EN_server_reset_request_put I 1 // EN_server_reset_response_get I 1 // EN_set_addr_map I 1 +// axi4_slave_awvalid I 1 +// axi4_slave_wvalid I 1 +// axi4_slave_arvalid I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_awvalid, +// axi4_slave_wvalid, +// axi4_slave_arvalid) -> axi4_slave_bid +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_awvalid, +// axi4_slave_wvalid, +// axi4_slave_arvalid) -> axi4_slave_bresp +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_awvalid, +// axi4_slave_wvalid, +// axi4_slave_arvalid) -> axi4_slave_buser +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_awvalid, +// axi4_slave_wvalid, +// axi4_slave_arvalid) -> axi4_slave_bvalid +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rid +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rdata +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rresp +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rlast +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_ruser +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rvalid // // @@ -117,7 +287,6 @@ module mkPLIC_16_2_7(CLK, EN_set_addr_map, RDY_set_addr_map, - axi4_slave_awvalid, axi4_slave_awid, axi4_slave_awaddr, axi4_slave_awlen, @@ -128,25 +297,25 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awprot, axi4_slave_awqos, axi4_slave_awregion, + axi4_slave_awvalid, axi4_slave_awready, - axi4_slave_wvalid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, + axi4_slave_wvalid, axi4_slave_wready, - axi4_slave_bvalid, - axi4_slave_bid, axi4_slave_bresp, + axi4_slave_bvalid, + axi4_slave_bready, - axi4_slave_arvalid, axi4_slave_arid, axi4_slave_araddr, axi4_slave_arlen, @@ -157,11 +326,10 @@ module mkPLIC_16_2_7(CLK, axi4_slave_arprot, axi4_slave_arqos, axi4_slave_arregion, + axi4_slave_arvalid, axi4_slave_arready, - axi4_slave_rvalid, - axi4_slave_rid, axi4_slave_rdata, @@ -170,6 +338,8 @@ module mkPLIC_16_2_7(CLK, axi4_slave_rlast, + axi4_slave_rvalid, + axi4_slave_rready, v_sources_0_m_interrupt_req_set_not_clear, @@ -233,9 +403,8 @@ module mkPLIC_16_2_7(CLK, input EN_set_addr_map; output RDY_set_addr_map; - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; + // action method axi4_slave_aw_awflit + input [4 : 0] axi4_slave_awid; input [63 : 0] axi4_slave_awaddr; input [7 : 0] axi4_slave_awlen; input [2 : 0] axi4_slave_awsize; @@ -245,36 +414,36 @@ module mkPLIC_16_2_7(CLK, input [2 : 0] axi4_slave_awprot; input [3 : 0] axi4_slave_awqos; input [3 : 0] axi4_slave_awregion; + input axi4_slave_awvalid; - // value method axi4_slave_m_awready + // value method axi4_slave_aw_awready output axi4_slave_awready; - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; + // action method axi4_slave_w_wflit input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; + input axi4_slave_wvalid; - // value method axi4_slave_m_wready + // value method axi4_slave_w_wready output axi4_slave_wready; - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; + // value method axi4_slave_b_bid + output [4 : 0] axi4_slave_bid; - // value method axi4_slave_m_bresp + // value method axi4_slave_b_bresp output [1 : 0] axi4_slave_bresp; - // value method axi4_slave_m_buser + // value method axi4_slave_b_buser + + // value method axi4_slave_b_bvalid + output axi4_slave_bvalid; - // action method axi4_slave_m_bready + // action method axi4_slave_b_bready input axi4_slave_bready; - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; + // action method axi4_slave_ar_arflit + input [4 : 0] axi4_slave_arid; input [63 : 0] axi4_slave_araddr; input [7 : 0] axi4_slave_arlen; input [2 : 0] axi4_slave_arsize; @@ -284,28 +453,29 @@ module mkPLIC_16_2_7(CLK, input [2 : 0] axi4_slave_arprot; input [3 : 0] axi4_slave_arqos; input [3 : 0] axi4_slave_arregion; + input axi4_slave_arvalid; - // value method axi4_slave_m_arready + // value method axi4_slave_ar_arready output axi4_slave_arready; - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; + // value method axi4_slave_r_rid + output [4 : 0] axi4_slave_rid; - // value method axi4_slave_m_rdata + // value method axi4_slave_r_rdata output [63 : 0] axi4_slave_rdata; - // value method axi4_slave_m_rresp + // value method axi4_slave_r_rresp output [1 : 0] axi4_slave_rresp; - // value method axi4_slave_m_rlast + // value method axi4_slave_r_rlast output axi4_slave_rlast; - // value method axi4_slave_m_ruser + // value method axi4_slave_r_ruser + + // value method axi4_slave_r_rvalid + output axi4_slave_rvalid; - // action method axi4_slave_m_rready + // action method axi4_slave_r_rready input axi4_slave_rready; // action method v_sources_0_m_interrupt_req @@ -364,7 +534,7 @@ module mkPLIC_16_2_7(CLK, // signals for module outputs wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; + wire [4 : 0] axi4_slave_bid, axi4_slave_rid; wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; wire RDY_server_reset_request_put, RDY_server_reset_response_get, @@ -380,6 +550,36 @@ module mkPLIC_16_2_7(CLK, v_targets_0_m_eip, v_targets_1_m_eip; + // inlined wires + wire [98 : 0] m_slave_xactor_shim_arff_rv$port0__write_1, + m_slave_xactor_shim_arff_rv$port1__read, + m_slave_xactor_shim_arff_rv$port2__read, + m_slave_xactor_shim_arff_rv$port3__read, + m_slave_xactor_shim_awff_rv$port0__write_1, + m_slave_xactor_shim_awff_rv$port1__read, + m_slave_xactor_shim_awff_rv$port2__read, + m_slave_xactor_shim_awff_rv$port3__read; + wire [97 : 0] m_slave_xactor_ug_slave_u_ar_putWire$wget, + m_slave_xactor_ug_slave_u_aw_putWire$wget; + wire [73 : 0] m_slave_xactor_shim_wff_rv$port0__write_1, + m_slave_xactor_shim_wff_rv$port1__read, + m_slave_xactor_shim_wff_rv$port2__read, + m_slave_xactor_shim_wff_rv$port3__read; + wire [72 : 0] m_slave_xactor_shim_rff_rv$port0__write_1, + m_slave_xactor_shim_rff_rv$port1__read, + m_slave_xactor_shim_rff_rv$port2__read, + m_slave_xactor_shim_rff_rv$port3__read, + m_slave_xactor_ug_slave_u_w_putWire$wget; + wire [7 : 0] m_slave_xactor_shim_bff_rv$port0__write_1, + m_slave_xactor_shim_bff_rv$port1__read, + m_slave_xactor_shim_bff_rv$port2__read, + m_slave_xactor_shim_bff_rv$port3__read; + wire m_slave_xactor_ug_slave_u_ar_putWire$whas, + m_slave_xactor_ug_slave_u_aw_putWire$whas, + m_slave_xactor_ug_slave_u_b_dropWire$whas, + m_slave_xactor_ug_slave_u_r_dropWire$whas, + m_slave_xactor_ug_slave_u_w_putWire$whas; + // register m_cfg_verbosity reg [3 : 0] m_cfg_verbosity; wire [3 : 0] m_cfg_verbosity$D_IN; @@ -395,6 +595,35 @@ module mkPLIC_16_2_7(CLK, wire [63 : 0] m_rg_addr_lim$D_IN; wire m_rg_addr_lim$EN; + // register m_slave_xactor_clearing + reg m_slave_xactor_clearing; + wire m_slave_xactor_clearing$D_IN, m_slave_xactor_clearing$EN; + + // register m_slave_xactor_shim_arff_rv + reg [98 : 0] m_slave_xactor_shim_arff_rv; + wire [98 : 0] m_slave_xactor_shim_arff_rv$D_IN; + wire m_slave_xactor_shim_arff_rv$EN; + + // register m_slave_xactor_shim_awff_rv + reg [98 : 0] m_slave_xactor_shim_awff_rv; + wire [98 : 0] m_slave_xactor_shim_awff_rv$D_IN; + wire m_slave_xactor_shim_awff_rv$EN; + + // register m_slave_xactor_shim_bff_rv + reg [7 : 0] m_slave_xactor_shim_bff_rv; + wire [7 : 0] m_slave_xactor_shim_bff_rv$D_IN; + wire m_slave_xactor_shim_bff_rv$EN; + + // register m_slave_xactor_shim_rff_rv + reg [72 : 0] m_slave_xactor_shim_rff_rv; + wire [72 : 0] m_slave_xactor_shim_rff_rv$D_IN; + wire m_slave_xactor_shim_rff_rv$EN; + + // register m_slave_xactor_shim_wff_rv + reg [73 : 0] m_slave_xactor_shim_wff_rv; + wire [73 : 0] m_slave_xactor_shim_wff_rv$D_IN; + wire m_slave_xactor_shim_wff_rv$EN; + // register m_vrg_servicing_source_0 reg [4 : 0] m_vrg_servicing_source_0; wire [4 : 0] m_vrg_servicing_source_0$D_IN; @@ -786,55 +1015,28 @@ module mkPLIC_16_2_7(CLK, m_f_reset_rsps$ENQ, m_f_reset_rsps$FULL_N; - // ports of submodule m_slave_xactor_f_rd_addr - wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT; - wire m_slave_xactor_f_rd_addr$CLR, - m_slave_xactor_f_rd_addr$DEQ, - m_slave_xactor_f_rd_addr$EMPTY_N, - m_slave_xactor_f_rd_addr$ENQ, - m_slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_data - wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT; - wire m_slave_xactor_f_rd_data$CLR, - m_slave_xactor_f_rd_data$DEQ, - m_slave_xactor_f_rd_data$EMPTY_N, - m_slave_xactor_f_rd_data$ENQ, - m_slave_xactor_f_rd_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_addr - wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT; - wire m_slave_xactor_f_wr_addr$CLR, - m_slave_xactor_f_wr_addr$DEQ, - m_slave_xactor_f_wr_addr$EMPTY_N, - m_slave_xactor_f_wr_addr$ENQ, - m_slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_data - wire [72 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; - wire m_slave_xactor_f_wr_data$CLR, - m_slave_xactor_f_wr_data$DEQ, - m_slave_xactor_f_wr_data$EMPTY_N, - m_slave_xactor_f_wr_data$ENQ, - m_slave_xactor_f_wr_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_resp - wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT; - wire m_slave_xactor_f_wr_resp$CLR, - m_slave_xactor_f_wr_resp$DEQ, - m_slave_xactor_f_wr_resp$EMPTY_N, - m_slave_xactor_f_wr_resp$ENQ, - m_slave_xactor_f_wr_resp$FULL_N; - // rule scheduling signals wire CAN_FIRE_RL_m_rl_process_rd_req, CAN_FIRE_RL_m_rl_process_wr_req, CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, + CAN_FIRE_RL_m_slave_xactor_do_clear, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_axi4_slave_ar_arflit, + CAN_FIRE_axi4_slave_aw_awflit, + CAN_FIRE_axi4_slave_b_bready, + CAN_FIRE_axi4_slave_r_rready, + CAN_FIRE_axi4_slave_w_wflit, CAN_FIRE_server_reset_request_put, CAN_FIRE_server_reset_response_get, CAN_FIRE_set_addr_map, @@ -859,11 +1061,24 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req, WILL_FIRE_RL_m_rl_process_wr_req, WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, + WILL_FIRE_RL_m_slave_xactor_do_clear, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_axi4_slave_ar_arflit, + WILL_FIRE_axi4_slave_aw_awflit, + WILL_FIRE_axi4_slave_b_bready, + WILL_FIRE_axi4_slave_r_rready, + WILL_FIRE_axi4_slave_w_wflit, WILL_FIRE_server_reset_request_put, WILL_FIRE_server_reset_response_get, WILL_FIRE_set_addr_map, @@ -1012,516 +1227,509 @@ module mkPLIC_16_2_7(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h75659; - reg [31 : 0] v__h75857; - reg [31 : 0] v__h76055; - reg [31 : 0] v__h76253; - reg [31 : 0] v__h76451; - reg [31 : 0] v__h76649; - reg [31 : 0] v__h76847; - reg [31 : 0] v__h77045; - reg [31 : 0] v__h77243; - reg [31 : 0] v__h77441; - reg [31 : 0] v__h77639; - reg [31 : 0] v__h77837; - reg [31 : 0] v__h78035; - reg [31 : 0] v__h78233; - reg [31 : 0] v__h78431; - reg [31 : 0] v__h78629; - reg [31 : 0] v__h6142; - reg [31 : 0] v__h13078; - reg [31 : 0] v__h13263; - reg [31 : 0] v__h13461; - reg [31 : 0] v__h13711; - reg [31 : 0] v__h18184; - reg [31 : 0] v__h23800; - reg [31 : 0] v__h25973; - reg [31 : 0] v__h24054; - reg [31 : 0] v__h26248; - reg [31 : 0] v__h26461; - reg [31 : 0] v__h26735; - reg [31 : 0] v__h26959; - reg [31 : 0] v__h27854; - reg [31 : 0] v__h28037; - reg [31 : 0] v__h67019; - reg [31 : 0] v__h67307; - reg [31 : 0] v__h67836; - reg [31 : 0] v__h67922; - reg [31 : 0] v__h68121; - reg [31 : 0] v__h68340; - reg [31 : 0] v__h74675; - reg [31 : 0] v__h74785; - reg [31 : 0] v__h74898; - reg [31 : 0] v__h6136; - reg [31 : 0] v__h13072; - reg [31 : 0] v__h13257; - reg [31 : 0] v__h13455; - reg [31 : 0] v__h13705; - reg [31 : 0] v__h18178; - reg [31 : 0] v__h23794; - reg [31 : 0] v__h24048; - reg [31 : 0] v__h25967; - reg [31 : 0] v__h26242; - reg [31 : 0] v__h26455; - reg [31 : 0] v__h26729; - reg [31 : 0] v__h26953; - reg [31 : 0] v__h27848; - reg [31 : 0] v__h28031; - reg [31 : 0] v__h67013; - reg [31 : 0] v__h67301; - reg [31 : 0] v__h67830; - reg [31 : 0] v__h67916; - reg [31 : 0] v__h68115; - reg [31 : 0] v__h68334; - reg [31 : 0] v__h74669; - reg [31 : 0] v__h74779; - reg [31 : 0] v__h74892; - reg [31 : 0] v__h75653; - reg [31 : 0] v__h75851; - reg [31 : 0] v__h76049; - reg [31 : 0] v__h76247; - reg [31 : 0] v__h76445; - reg [31 : 0] v__h76643; - reg [31 : 0] v__h76841; - reg [31 : 0] v__h77039; - reg [31 : 0] v__h77237; - reg [31 : 0] v__h77435; - reg [31 : 0] v__h77633; - reg [31 : 0] v__h77831; - reg [31 : 0] v__h78029; - reg [31 : 0] v__h78227; - reg [31 : 0] v__h78425; - reg [31 : 0] v__h78623; + reg [31 : 0] v__h78778; + reg [31 : 0] v__h78976; + reg [31 : 0] v__h79174; + reg [31 : 0] v__h79372; + reg [31 : 0] v__h79570; + reg [31 : 0] v__h79768; + reg [31 : 0] v__h79966; + reg [31 : 0] v__h80164; + reg [31 : 0] v__h80362; + reg [31 : 0] v__h80560; + reg [31 : 0] v__h80758; + reg [31 : 0] v__h80956; + reg [31 : 0] v__h81154; + reg [31 : 0] v__h81352; + reg [31 : 0] v__h81550; + reg [31 : 0] v__h81748; + reg [31 : 0] v__h8559; + reg [31 : 0] v__h15481; + reg [31 : 0] v__h15696; + reg [31 : 0] v__h15924; + reg [31 : 0] v__h16175; + reg [31 : 0] v__h20649; + reg [31 : 0] v__h26266; + reg [31 : 0] v__h28442; + reg [31 : 0] v__h26522; + reg [31 : 0] v__h28733; + reg [31 : 0] v__h29034; + reg [31 : 0] v__h29518; + reg [31 : 0] v__h29772; + reg [31 : 0] v__h30696; + reg [31 : 0] v__h30882; + reg [31 : 0] v__h69866; + reg [31 : 0] v__h70156; + reg [31 : 0] v__h70688; + reg [31 : 0] v__h70774; + reg [31 : 0] v__h70985; + reg [31 : 0] v__h71294; + reg [31 : 0] v__h77734; + reg [31 : 0] v__h77844; + reg [31 : 0] v__h77957; + reg [31 : 0] v__h8553; + reg [31 : 0] v__h15475; + reg [31 : 0] v__h15690; + reg [31 : 0] v__h15918; + reg [31 : 0] v__h16169; + reg [31 : 0] v__h20643; + reg [31 : 0] v__h26260; + reg [31 : 0] v__h26516; + reg [31 : 0] v__h28436; + reg [31 : 0] v__h28727; + reg [31 : 0] v__h29028; + reg [31 : 0] v__h29512; + reg [31 : 0] v__h29766; + reg [31 : 0] v__h30690; + reg [31 : 0] v__h30876; + reg [31 : 0] v__h69860; + reg [31 : 0] v__h70150; + reg [31 : 0] v__h70682; + reg [31 : 0] v__h70768; + reg [31 : 0] v__h70979; + reg [31 : 0] v__h71288; + reg [31 : 0] v__h77728; + reg [31 : 0] v__h77838; + reg [31 : 0] v__h77951; + reg [31 : 0] v__h78772; + reg [31 : 0] v__h78970; + reg [31 : 0] v__h79168; + reg [31 : 0] v__h79366; + reg [31 : 0] v__h79564; + reg [31 : 0] v__h79762; + reg [31 : 0] v__h79960; + reg [31 : 0] v__h80158; + reg [31 : 0] v__h80356; + reg [31 : 0] v__h80554; + reg [31 : 0] v__h80752; + reg [31 : 0] v__h80950; + reg [31 : 0] v__h81148; + reg [31 : 0] v__h81346; + reg [31 : 0] v__h81544; + reg [31 : 0] v__h81742; // synopsys translate_on // remaining internal signals - reg [63 : 0] y_avValue_fst__h26146; - reg [4 : 0] x__h24009, x__h67476; - reg [2 : 0] x__h13491, x__h23830; - reg [1 : 0] v__h67096, y_avValue_snd__h26147; - reg CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - wire [63 : 0] addr_offset__h13214, - addr_offset__h26920, - rdata___1__h26402, - rdata__h26200, - v__h13420, - v__h13669, - v__h18142, - v__h23759, - v__h25453, - v__h25472, - x__h26359, - y_avValue_fst__h26092, - y_avValue_fst__h26113, - y_avValue_fst__h26125, - y_avValue_fst__h26141, - y_avValue_fst__h26157, - y_avValue_fst__h26162, - y_avValue_fst__h26173, - y_avValue_fst__h26178, - y_avValue_fst__h26192; - wire [31 : 0] v_ie__h18145, - v_ip__h13672, - wdata32__h26921, - x__h23671, - x__h67099; - wire [9 : 0] source_id__h15663, - source_id__h15770, - source_id__h15843, - source_id__h15916, - source_id__h15989, - source_id__h16062, - source_id__h16135, - source_id__h16208, - source_id__h16281, - source_id__h16354, - source_id__h16427, - source_id__h16500, - source_id__h16573, - source_id__h16646, - source_id__h16719, - source_id__h16792, - source_id__h16865, - source_id__h16938, - source_id__h17011, - source_id__h17084, - source_id__h17157, - source_id__h17230, - source_id__h17303, - source_id__h17376, - source_id__h17449, - source_id__h17522, - source_id__h17595, - source_id__h17668, - source_id__h17741, - source_id__h17814, - source_id__h17887, - source_id__h20135, - source_id__h20311, - source_id__h20419, - source_id__h20527, - source_id__h20635, - source_id__h20743, - source_id__h20851, - source_id__h20959, - source_id__h21067, - source_id__h21175, - source_id__h21283, - source_id__h21391, - source_id__h21499, - source_id__h21607, - source_id__h21715, - source_id__h21823, - source_id__h21931, - source_id__h22039, - source_id__h22147, - source_id__h22255, - source_id__h22363, - source_id__h22471, - source_id__h22579, - source_id__h22687, - source_id__h22795, - source_id__h22903, - source_id__h23011, - source_id__h23119, - source_id__h23227, - source_id__h23335, - source_id__h23443, - source_id__h29464, - source_id__h30674, - source_id__h31884, - source_id__h33094, - source_id__h34304, - source_id__h35514, - source_id__h36724, - source_id__h37934, - source_id__h39144, - source_id__h40354, - source_id__h41564, - source_id__h42774, - source_id__h43984, - source_id__h45194, - source_id__h46404, - source_id__h47614, - source_id__h48824, - source_id__h50034, - source_id__h51244, - source_id__h52454, - source_id__h53664, - source_id__h54874, - source_id__h56084, - source_id__h57294, - source_id__h58504, - source_id__h59714, - source_id__h60924, - source_id__h62134, - source_id__h63344, - source_id__h64554, - source_id__h65764, - source_id__h67425, - source_id_base__h13628, - source_id_base__h28137; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71298, - b__h73303, - max_id__h23957; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71297, - a__h73302; - wire [1 : 0] rresp__h26201, - v__h26925, - v__h27083, - v__h27096, - v__h27931, - v__h27950, - v__h28114, - v__h28133, - v__h67133, - v__h67421, - v__h67465, - y_avValue_snd__h26093, - y_avValue_snd__h26114, - y_avValue_snd__h26126, - y_avValue_snd__h26142, - y_avValue_snd__h26158, - y_avValue_snd__h26163, - y_avValue_snd__h26174, - y_avValue_snd__h26179, - y_avValue_snd__h26193; - wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990, - NOT_m_cfg_verbosity_read_ULE_1_5___d16, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981, - NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311, - NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319, - NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327, - NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335, - NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343, - NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351, - NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359, - NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240, - NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247, - NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255, - NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263, - NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271, - NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279, - NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287, - NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295, - NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303, + reg [63 : 0] y_avValue_fst__h28615; + reg [4 : 0] x__h26477, x__h70328; + reg [2 : 0] x__h15954, x__h26296; + reg [1 : 0] CASE_x6136_0x200000_IF_m_slave_xactor_shim_arf_ETC__q50, + CASE_x9947_0x200000_IF_m_slave_xactor_shim_awf_ETC__q1; + reg CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q33, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q49, + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589; + wire [71 : 0] m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52; + wire [63 : 0] addr_offset__h15646, + addr_offset__h29732, + rdata___1__h28973, + rdata__h28669, + v__h15883, + v__h16133, + v__h20607, + v__h26225, + v__h27922, + v__h27941, + x__h28872, + y_avValue_fst__h28561, + y_avValue_fst__h28582, + y_avValue_fst__h28594, + y_avValue_fst__h28610, + y_avValue_fst__h28626, + y_avValue_fst__h28631, + y_avValue_fst__h28642, + y_avValue_fst__h28647, + y_avValue_fst__h28661; + wire [31 : 0] v_ie__h20610, + v_ip__h16136, + wdata32__h29733, + x__h26136, + x__h69947; + wire [9 : 0] source_id__h18127, + source_id__h18234, + source_id__h18307, + source_id__h18380, + source_id__h18453, + source_id__h18526, + source_id__h18599, + source_id__h18672, + source_id__h18745, + source_id__h18818, + source_id__h18891, + source_id__h18964, + source_id__h19037, + source_id__h19110, + source_id__h19183, + source_id__h19256, + source_id__h19329, + source_id__h19402, + source_id__h19475, + source_id__h19548, + source_id__h19621, + source_id__h19694, + source_id__h19767, + source_id__h19840, + source_id__h19913, + source_id__h19986, + source_id__h20059, + source_id__h20132, + source_id__h20205, + source_id__h20278, + source_id__h20351, + source_id__h22600, + source_id__h22776, + source_id__h22884, + source_id__h22992, + source_id__h23100, + source_id__h23208, + source_id__h23316, + source_id__h23424, + source_id__h23532, + source_id__h23640, + source_id__h23748, + source_id__h23856, + source_id__h23964, + source_id__h24072, + source_id__h24180, + source_id__h24288, + source_id__h24396, + source_id__h24504, + source_id__h24612, + source_id__h24720, + source_id__h24828, + source_id__h24936, + source_id__h25044, + source_id__h25152, + source_id__h25260, + source_id__h25368, + source_id__h25476, + source_id__h25584, + source_id__h25692, + source_id__h25800, + source_id__h25908, + source_id__h32311, + source_id__h33521, + source_id__h34731, + source_id__h35941, + source_id__h37151, + source_id__h38361, + source_id__h39571, + source_id__h40781, + source_id__h41991, + source_id__h43201, + source_id__h44411, + source_id__h45621, + source_id__h46831, + source_id__h48041, + source_id__h49251, + source_id__h50461, + source_id__h51671, + source_id__h52881, + source_id__h54091, + source_id__h55301, + source_id__h56511, + source_id__h57721, + source_id__h58931, + source_id__h60141, + source_id__h61351, + source_id__h62561, + source_id__h63771, + source_id__h64981, + source_id__h66191, + source_id__h67401, + source_id__h68611, + source_id__h70276, + source_id_base__h16091, + source_id_base__h30983; + wire [6 : 0] m_slave_xactor_shim_bff_rvport1__read_BITS_6__ETC__q51; + wire [4 : 0] IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3228, + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3322, + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d736, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3230, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3324, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d738, + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3232, + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3326, + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d740, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3220, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3314, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d728, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3222, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3316, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d730, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3224, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3318, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d732, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3226, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3320, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d734, + b__h74357, + b__h76362, + max_id__h26424; + wire [2 : 0] IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3187, + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3281, + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d684, + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3192, + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3286, + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d691, + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3197, + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3291, + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d698, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3202, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3296, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d705, + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3207, + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3301, + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d712, + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3212, + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3306, + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3142, + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3236, + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d621, + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3147, + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3241, + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d628, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3152, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3246, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d635, + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3157, + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3251, + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d642, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3162, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3256, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d649, + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3167, + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3261, + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d656, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3172, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3266, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d663, + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3177, + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3271, + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d670, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3182, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3276, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d677, + a__h74356, + a__h76361; + wire [1 : 0] IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d878, + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d879, + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d880, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3122, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3123, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3124; + wire IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d838, + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840, + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d889, + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d891, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3100, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3130, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3132, + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d143, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d317, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d607, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d813, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1017, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1029, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2981, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2994, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3005, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3077, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d963, + NOT_m_vrg_source_busy_10_022_434_AND_NOT_m_cfg_ETC___d3438, + NOT_m_vrg_source_busy_11_023_442_AND_NOT_m_cfg_ETC___d3446, + NOT_m_vrg_source_busy_12_024_450_AND_NOT_m_cfg_ETC___d3454, + NOT_m_vrg_source_busy_13_025_458_AND_NOT_m_cfg_ETC___d3462, + NOT_m_vrg_source_busy_14_026_466_AND_NOT_m_cfg_ETC___d3470, + NOT_m_vrg_source_busy_15_027_474_AND_NOT_m_cfg_ETC___d3478, + NOT_m_vrg_source_busy_16_028_482_AND_NOT_m_cfg_ETC___d3486, + NOT_m_vrg_source_busy_1_013_363_AND_NOT_m_cfg__ETC___d3367, + NOT_m_vrg_source_busy_2_014_370_AND_NOT_m_cfg__ETC___d3374, + NOT_m_vrg_source_busy_3_015_378_AND_NOT_m_cfg__ETC___d3382, + NOT_m_vrg_source_busy_4_016_386_AND_NOT_m_cfg__ETC___d3390, + NOT_m_vrg_source_busy_5_017_394_AND_NOT_m_cfg__ETC___d3398, + NOT_m_vrg_source_busy_6_018_402_AND_NOT_m_cfg__ETC___d3406, + NOT_m_vrg_source_busy_7_019_410_AND_NOT_m_cfg__ETC___d3414, + NOT_m_vrg_source_busy_8_020_418_AND_NOT_m_cfg__ETC___d3422, + NOT_m_vrg_source_busy_9_021_426_AND_NOT_m_cfg__ETC___d3430, _dfoo1, _dfoo10, _dfoo100, @@ -3086,94 +3294,94 @@ module mkPLIC_16_2_7(CLK, _dfoo997, _dfoo998, _dfoo999, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, - m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d112, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1000, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1002, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1004, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1006, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2997, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2999, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d974, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d976, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d978, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d980, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d982, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d984, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d986, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d988, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d990, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d992, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d994, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d996, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d998, + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3186, + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3280, + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d683, + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3191, + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3285, + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d690, + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3196, + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3290, + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d697, + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3201, + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3295, + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d704, + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d760, + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3206, + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3300, + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d711, + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3211, + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3305, + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d718, + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3216, + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3310, + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d725, + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d763, + m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_sourc_ETC___d620, + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3146, + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3240, + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d627, + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3151, + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3245, + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d634, + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3156, + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3250, + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d641, + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3161, + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3255, + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d648, + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3166, + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3260, + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d655, + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3171, + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3265, + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d662, + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d754, + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3176, + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3270, + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d669, + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3181, + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3275, + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d676, + m_vrg_source_prio_16_32_ULE_IF_m_vrg_source_ip_ETC___d720; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; @@ -3200,58 +3408,64 @@ module mkPLIC_16_2_7(CLK, assign CAN_FIRE_set_addr_map = 1'd1 ; assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; + // action method axi4_slave_aw_awflit + assign CAN_FIRE_axi4_slave_aw_awflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_aw_awflit = axi4_slave_awvalid ; - // value method axi4_slave_m_awready - assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ; + // value method axi4_slave_aw_awready + assign axi4_slave_awready = !m_slave_xactor_shim_awff_rv[98] ; - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; + // action method axi4_slave_w_wflit + assign CAN_FIRE_axi4_slave_w_wflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_w_wflit = axi4_slave_wvalid ; - // value method axi4_slave_m_wready - assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ; + // value method axi4_slave_w_wready + assign axi4_slave_wready = !m_slave_xactor_shim_wff_rv[73] ; - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ; + // value method axi4_slave_b_bid + assign axi4_slave_bid = + m_slave_xactor_shim_bff_rvport1__read_BITS_6__ETC__q51[6:2] ; - // value method axi4_slave_m_bid - assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ; + // value method axi4_slave_b_bresp + assign axi4_slave_bresp = + m_slave_xactor_shim_bff_rvport1__read_BITS_6__ETC__q51[1:0] ; - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ; + // value method axi4_slave_b_bvalid + assign axi4_slave_bvalid = m_slave_xactor_shim_bff_rv$port1__read[7] ; - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; + // action method axi4_slave_b_bready + assign CAN_FIRE_axi4_slave_b_bready = 1'd1 ; + assign WILL_FIRE_axi4_slave_b_bready = 1'd1 ; - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; + // action method axi4_slave_ar_arflit + assign CAN_FIRE_axi4_slave_ar_arflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_ar_arflit = axi4_slave_arvalid ; - // value method axi4_slave_m_arready - assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ; + // value method axi4_slave_ar_arready + assign axi4_slave_arready = !m_slave_xactor_shim_arff_rv[98] ; - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ; + // value method axi4_slave_r_rid + assign axi4_slave_rid = + m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52[71:67] ; - // value method axi4_slave_m_rid - assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ; + // value method axi4_slave_r_rdata + assign axi4_slave_rdata = + m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52[66:3] ; - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ; + // value method axi4_slave_r_rresp + assign axi4_slave_rresp = + m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52[2:1] ; - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ; + // value method axi4_slave_r_rlast + assign axi4_slave_rlast = + m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52[0] ; - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ; + // value method axi4_slave_r_rvalid + assign axi4_slave_rvalid = m_slave_xactor_shim_rff_rv$port1__read[72] ; - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; + // action method axi4_slave_r_rready + assign CAN_FIRE_axi4_slave_r_rready = 1'd1 ; + assign WILL_FIRE_axi4_slave_r_rready = 1'd1 ; // action method v_sources_0_m_interrupt_req assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; @@ -3318,10 +3532,10 @@ module mkPLIC_16_2_7(CLK, assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71297 > m_vrg_target_threshold_0 ; + assign v_targets_0_m_eip = a__h74356 > m_vrg_target_threshold_0 ; // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73302 > m_vrg_target_threshold_1 ; + assign v_targets_1_m_eip = a__h76361 > m_vrg_target_threshold_1 ; // submodule m_f_reset_reqs FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), @@ -3341,279 +3555,308 @@ module mkPLIC_16_2_7(CLK, .FULL_N(m_f_reset_rsps$FULL_N), .EMPTY_N(m_f_reset_rsps$EMPTY_N)); - // submodule m_slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_addr$D_IN), - .ENQ(m_slave_xactor_f_rd_addr$ENQ), - .DEQ(m_slave_xactor_f_rd_addr$DEQ), - .CLR(m_slave_xactor_f_rd_addr$CLR), - .D_OUT(m_slave_xactor_f_rd_addr$D_OUT), - .FULL_N(m_slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_data$D_IN), - .ENQ(m_slave_xactor_f_rd_data$ENQ), - .DEQ(m_slave_xactor_f_rd_data$DEQ), - .CLR(m_slave_xactor_f_rd_data$CLR), - .D_OUT(m_slave_xactor_f_rd_data$D_OUT), - .FULL_N(m_slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_addr$D_IN), - .ENQ(m_slave_xactor_f_wr_addr$ENQ), - .DEQ(m_slave_xactor_f_wr_addr$DEQ), - .CLR(m_slave_xactor_f_wr_addr$CLR), - .D_OUT(m_slave_xactor_f_wr_addr$D_OUT), - .FULL_N(m_slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_data$D_IN), - .ENQ(m_slave_xactor_f_wr_data$ENQ), - .DEQ(m_slave_xactor_f_wr_data$DEQ), - .CLR(m_slave_xactor_f_wr_data$CLR), - .D_OUT(m_slave_xactor_f_wr_data$D_OUT), - .FULL_N(m_slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_resp$D_IN), - .ENQ(m_slave_xactor_f_wr_resp$ENQ), - .DEQ(m_slave_xactor_f_wr_resp$DEQ), - .CLR(m_slave_xactor_f_wr_resp$CLR), - .D_OUT(m_slave_xactor_f_wr_resp$D_OUT), - .FULL_N(m_slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N)); - // rule RL_m_rl_reset assign CAN_FIRE_RL_m_rl_reset = - m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ; + !m_slave_xactor_clearing && m_f_reset_reqs$EMPTY_N && + m_f_reset_rsps$FULL_N ; assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; + // rule RL_m_slave_xactor_ug_slave_u_aw_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut = + m_slave_xactor_ug_slave_u_aw_putWire$whas && + m_slave_xactor_shim_awff_rv[98] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut ; + + // rule RL_m_slave_xactor_ug_slave_u_aw_doPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut = + !m_slave_xactor_shim_awff_rv[98] && + m_slave_xactor_ug_slave_u_aw_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut ; + + // rule RL_m_slave_xactor_ug_slave_u_w_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut = + m_slave_xactor_ug_slave_u_w_putWire$whas && + m_slave_xactor_shim_wff_rv[73] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut ; + + // rule RL_m_slave_xactor_ug_slave_u_w_doPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut = + !m_slave_xactor_shim_wff_rv[73] && + m_slave_xactor_ug_slave_u_w_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut ; + + // rule RL_m_slave_xactor_ug_slave_u_ar_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut = + m_slave_xactor_ug_slave_u_ar_putWire$whas && + m_slave_xactor_shim_arff_rv[98] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut ; + + // rule RL_m_slave_xactor_ug_slave_u_ar_doPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut = + !m_slave_xactor_shim_arff_rv[98] && + m_slave_xactor_ug_slave_u_ar_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut ; + // rule RL_m_rl_process_rd_req assign CAN_FIRE_RL_m_rl_process_rd_req = - m_slave_xactor_f_rd_addr$EMPTY_N && - m_slave_xactor_f_rd_data$FULL_N && + !m_slave_xactor_clearing && + m_slave_xactor_shim_arff_rv$port1__read[98] && + !m_slave_xactor_shim_rff_rv[72] && !m_f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; // rule RL_m_rl_process_wr_req assign CAN_FIRE_RL_m_rl_process_wr_req = - m_slave_xactor_f_wr_addr$EMPTY_N && - m_slave_xactor_f_wr_data$EMPTY_N && - m_slave_xactor_f_wr_resp$FULL_N && + !m_slave_xactor_clearing && + m_slave_xactor_shim_awff_rv$port1__read[98] && + m_slave_xactor_shim_wff_rv$port1__read[73] && + !m_slave_xactor_shim_bff_rv[7] && !m_f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_m_rl_process_wr_req = CAN_FIRE_RL_m_rl_process_wr_req && !WILL_FIRE_RL_m_rl_process_rd_req ; + // rule RL_m_slave_xactor_ug_slave_u_b_setPeek + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek = + m_slave_xactor_shim_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek = + m_slave_xactor_shim_bff_rv$port1__read[7] ; + + // rule RL_m_slave_xactor_ug_slave_u_b_warnDoDrop + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop = + m_slave_xactor_ug_slave_u_b_dropWire$whas && + !m_slave_xactor_shim_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop ; + + // rule RL_m_slave_xactor_ug_slave_u_b_doDrop + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop = + m_slave_xactor_shim_bff_rv$port1__read[7] && + m_slave_xactor_ug_slave_u_b_dropWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop ; + + // rule RL_m_slave_xactor_ug_slave_u_r_setPeek + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek = + m_slave_xactor_shim_rff_rv$port1__read[72] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek = + m_slave_xactor_shim_rff_rv$port1__read[72] ; + + // rule RL_m_slave_xactor_ug_slave_u_r_warnDoDrop + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop = + m_slave_xactor_ug_slave_u_r_dropWire$whas && + !m_slave_xactor_shim_rff_rv$port1__read[72] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop ; + + // rule RL_m_slave_xactor_ug_slave_u_r_doDrop + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop = + m_slave_xactor_shim_rff_rv$port1__read[72] && + m_slave_xactor_ug_slave_u_r_dropWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop ; + + // rule RL_m_slave_xactor_do_clear + assign CAN_FIRE_RL_m_slave_xactor_do_clear = m_slave_xactor_clearing ; + assign WILL_FIRE_RL_m_slave_xactor_do_clear = m_slave_xactor_clearing ; + // inputs to muxes for submodule ports assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13214[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + addr_offset__h15646[16:12] == 5'd0 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13214[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + addr_offset__h15646[16:12] == 5'd1 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd1 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd10 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd10 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd11 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd11 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd12 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd12 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd13 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd13 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd14 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd14 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd15 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd15 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd16 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd16 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd2 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd2 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd3 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd3 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd4 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd4 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd5 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd5 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd6 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd6 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd7 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd7 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd8 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd8 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd9 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd9 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26920[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 ; + addr_offset__h29732[11:2] == 10'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d963 ; assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d974 ; assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d992 ; assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d994 ; assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d996 ; assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d998 ; assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1000 ; assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1002 ; assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1004 ; assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d976 ; assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d978 ; assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d980 ; assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d982 ; assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d984 ; assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d986 ; assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d988 ; assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d990 ; assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2997 ; assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2999 ; assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = @@ -3683,176 +3926,292 @@ module mkPLIC_16_2_7(CLK, assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28137 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2040 ; assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28137 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd1 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2038 ; assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28137 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd10 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2020 ; assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28137 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd11 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2018 ; assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28137 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd12 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2016 ; assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28137 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd13 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2014 ; assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28137 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd14 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2012 ; assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28137 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd15 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2010 ; assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28137 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd16 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2008 ; assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28137 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd2 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2036 ; assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28137 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd3 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2034 ; assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28137 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd4 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2032 ; assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28137 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd5 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2030 ; assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28137 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd6 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2028 ; assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28137 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd7 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2026 ; assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28137 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd8 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2024 ; assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28137 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd9 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2022 ; assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28137 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo2006 ; assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28137 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd1 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo2004 ; assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28137 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd10 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1986 ; assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28137 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd11 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1984 ; assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28137 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd12 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1982 ; assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28137 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd13 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1980 ; assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28137 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd14 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1978 ; assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28137 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd15 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1976 ; assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28137 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd16 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1974 ; assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28137 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd2 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo2002 ; assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28137 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd3 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo2000 ; assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28137 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd4 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1998 ; assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28137 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd5 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1996 ; assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28137 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd6 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1994 ; assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28137 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd7 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1992 ; assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28137 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd8 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1990 ; assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28137 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd9 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1988 ; + // inlined wires + assign m_slave_xactor_ug_slave_u_aw_putWire$wget = + { axi4_slave_awid, + axi4_slave_awaddr, + axi4_slave_awlen, + axi4_slave_awsize, + axi4_slave_awburst, + axi4_slave_awlock, + axi4_slave_awcache, + axi4_slave_awprot, + axi4_slave_awqos, + axi4_slave_awregion } ; + assign m_slave_xactor_ug_slave_u_aw_putWire$whas = + axi4_slave_awvalid && !m_slave_xactor_shim_awff_rv[98] ; + assign m_slave_xactor_ug_slave_u_w_putWire$wget = + { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; + assign m_slave_xactor_ug_slave_u_w_putWire$whas = + axi4_slave_wvalid && !m_slave_xactor_shim_wff_rv[73] ; + assign m_slave_xactor_ug_slave_u_ar_putWire$wget = + { axi4_slave_arid, + axi4_slave_araddr, + axi4_slave_arlen, + axi4_slave_arsize, + axi4_slave_arburst, + axi4_slave_arlock, + axi4_slave_arcache, + axi4_slave_arprot, + axi4_slave_arqos, + axi4_slave_arregion } ; + assign m_slave_xactor_ug_slave_u_ar_putWire$whas = + axi4_slave_arvalid && !m_slave_xactor_shim_arff_rv[98] ; + assign m_slave_xactor_ug_slave_u_b_dropWire$whas = + m_slave_xactor_shim_bff_rv$port1__read[7] && axi4_slave_bready ; + assign m_slave_xactor_ug_slave_u_r_dropWire$whas = + m_slave_xactor_shim_rff_rv$port1__read[72] && axi4_slave_rready ; + assign m_slave_xactor_shim_awff_rv$port0__write_1 = + { 1'd1, m_slave_xactor_ug_slave_u_aw_putWire$wget } ; + assign m_slave_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut ? + m_slave_xactor_shim_awff_rv$port0__write_1 : + m_slave_xactor_shim_awff_rv ; + assign m_slave_xactor_shim_awff_rv$port2__read = + WILL_FIRE_RL_m_rl_process_wr_req ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_awff_rv$port1__read ; + assign m_slave_xactor_shim_awff_rv$port3__read = + m_slave_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_awff_rv$port2__read ; + assign m_slave_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, m_slave_xactor_ug_slave_u_w_putWire$wget } ; + assign m_slave_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut ? + m_slave_xactor_shim_wff_rv$port0__write_1 : + m_slave_xactor_shim_wff_rv ; + assign m_slave_xactor_shim_wff_rv$port2__read = + WILL_FIRE_RL_m_rl_process_wr_req ? + 74'h0AAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_wff_rv$port1__read ; + assign m_slave_xactor_shim_wff_rv$port3__read = + m_slave_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_wff_rv$port2__read ; + assign m_slave_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, + m_slave_xactor_shim_awff_rv$port1__read[97:93], + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 ? + 2'd3 : + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3124 } ; + assign m_slave_xactor_shim_bff_rv$port1__read = + WILL_FIRE_RL_m_rl_process_wr_req ? + m_slave_xactor_shim_bff_rv$port0__write_1 : + m_slave_xactor_shim_bff_rv ; + assign m_slave_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop ? + 8'd42 : + m_slave_xactor_shim_bff_rv$port1__read ; + assign m_slave_xactor_shim_bff_rv$port3__read = + m_slave_xactor_clearing ? + 8'd42 : + m_slave_xactor_shim_bff_rv$port2__read ; + assign m_slave_xactor_shim_arff_rv$port0__write_1 = + { 1'd1, m_slave_xactor_ug_slave_u_ar_putWire$wget } ; + assign m_slave_xactor_shim_arff_rv$port1__read = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut ? + m_slave_xactor_shim_arff_rv$port0__write_1 : + m_slave_xactor_shim_arff_rv ; + assign m_slave_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_m_rl_process_rd_req ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_arff_rv$port1__read ; + assign m_slave_xactor_shim_arff_rv$port3__read = + m_slave_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_arff_rv$port2__read ; + assign m_slave_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, + m_slave_xactor_shim_arff_rv$port1__read[97:93], + x__h28872, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 ? + 2'd3 : + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d880, + 1'd1 } ; + assign m_slave_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_m_rl_process_rd_req ? + m_slave_xactor_shim_rff_rv$port0__write_1 : + m_slave_xactor_shim_rff_rv ; + assign m_slave_xactor_shim_rff_rv$port2__read = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop ? + 73'h0AAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_rff_rv$port1__read ; + assign m_slave_xactor_shim_rff_rv$port3__read = + m_slave_xactor_clearing ? + 73'h0AAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_rff_rv$port2__read ; + // register m_cfg_verbosity assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ; assign m_cfg_verbosity$EN = EN_set_verbosity ; @@ -3865,34 +4224,64 @@ module mkPLIC_16_2_7(CLK, assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ; assign m_rg_addr_lim$EN = EN_set_addr_map ; + // register m_slave_xactor_clearing + assign m_slave_xactor_clearing$D_IN = !m_slave_xactor_clearing ; + assign m_slave_xactor_clearing$EN = + m_slave_xactor_clearing || WILL_FIRE_RL_m_rl_reset ; + + // register m_slave_xactor_shim_arff_rv + assign m_slave_xactor_shim_arff_rv$D_IN = + m_slave_xactor_shim_arff_rv$port3__read ; + assign m_slave_xactor_shim_arff_rv$EN = 1'b1 ; + + // register m_slave_xactor_shim_awff_rv + assign m_slave_xactor_shim_awff_rv$D_IN = + m_slave_xactor_shim_awff_rv$port3__read ; + assign m_slave_xactor_shim_awff_rv$EN = 1'b1 ; + + // register m_slave_xactor_shim_bff_rv + assign m_slave_xactor_shim_bff_rv$D_IN = + m_slave_xactor_shim_bff_rv$port3__read ; + assign m_slave_xactor_shim_bff_rv$EN = 1'b1 ; + + // register m_slave_xactor_shim_rff_rv + assign m_slave_xactor_shim_rff_rv$D_IN = + m_slave_xactor_shim_rff_rv$port3__read ; + assign m_slave_xactor_shim_rff_rv$EN = 1'b1 ; + + // register m_slave_xactor_shim_wff_rv + assign m_slave_xactor_shim_wff_rv$D_IN = + m_slave_xactor_shim_wff_rv$port3__read ; + assign m_slave_xactor_shim_wff_rv$EN = 1'b1 ; + // register m_vrg_servicing_source_0 assign m_vrg_servicing_source_0$D_IN = MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h23957 : + max_id__h26424 : 5'd0 ; assign m_vrg_servicing_source_0$EN = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13214[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + addr_offset__h15646[16:12] == 5'd0 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26920[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + addr_offset__h29732[16:12] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_servicing_source_1 assign m_vrg_servicing_source_1$D_IN = MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h23957 : + max_id__h26424 : 5'd0 ; assign m_vrg_servicing_source_1$EN = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13214[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + addr_offset__h15646[16:12] == 5'd1 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26920[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + addr_offset__h29732[16:12] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_0 @@ -3900,11 +4289,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_0$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd0 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_1 @@ -3912,11 +4301,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_1$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd1 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_10 @@ -3924,12 +4313,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_10$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd10 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd10 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_11 @@ -3937,12 +4326,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_11$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd11 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd11 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_12 @@ -3950,12 +4339,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_12$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd12 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd12 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_13 @@ -3963,12 +4352,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_13$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd13 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd13 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_14 @@ -3976,12 +4365,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_14$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd14 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd14 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_15 @@ -3989,12 +4378,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_15$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd15 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd15 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_16 @@ -4002,12 +4391,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_16$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd16 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd16 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_2 @@ -4015,11 +4404,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_2$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd2 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd2 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_3 @@ -4027,11 +4416,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_3$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd3 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd3 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_4 @@ -4039,11 +4428,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_4$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd4 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd4 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_5 @@ -4051,11 +4440,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_5$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd5 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd5 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_6 @@ -4063,11 +4452,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_6$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd6 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd6 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_7 @@ -4075,11 +4464,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_7$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd7 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd7 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_8 @@ -4087,11 +4476,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_8$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd8 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd8 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_9 @@ -4099,19 +4488,19 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_9$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd9 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd9 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_0 assign m_vrg_source_ip_0$D_IN = 1'd0 ; assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd0 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_1 @@ -4121,9 +4510,9 @@ module mkPLIC_16_2_7(CLK, v_sources_0_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_1$EN = !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd1 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_10 @@ -4133,9 +4522,9 @@ module mkPLIC_16_2_7(CLK, v_sources_9_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_10$EN = !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd10 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_11 @@ -4145,9 +4534,9 @@ module mkPLIC_16_2_7(CLK, v_sources_10_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_11$EN = !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd11 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_12 @@ -4157,9 +4546,9 @@ module mkPLIC_16_2_7(CLK, v_sources_11_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_12$EN = !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd12 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_13 @@ -4169,9 +4558,9 @@ module mkPLIC_16_2_7(CLK, v_sources_12_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_13$EN = !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd13 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_14 @@ -4181,9 +4570,9 @@ module mkPLIC_16_2_7(CLK, v_sources_13_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_14$EN = !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd14 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_15 @@ -4193,9 +4582,9 @@ module mkPLIC_16_2_7(CLK, v_sources_14_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_15$EN = !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd15 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_16 @@ -4205,9 +4594,9 @@ module mkPLIC_16_2_7(CLK, v_sources_15_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_16$EN = !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd16 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_2 @@ -4217,9 +4606,9 @@ module mkPLIC_16_2_7(CLK, v_sources_1_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_2$EN = !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd2 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_3 @@ -4229,9 +4618,9 @@ module mkPLIC_16_2_7(CLK, v_sources_2_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_3$EN = !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd3 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_4 @@ -4241,9 +4630,9 @@ module mkPLIC_16_2_7(CLK, v_sources_3_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_4$EN = !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd4 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_5 @@ -4253,9 +4642,9 @@ module mkPLIC_16_2_7(CLK, v_sources_4_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_5$EN = !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd5 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_6 @@ -4265,9 +4654,9 @@ module mkPLIC_16_2_7(CLK, v_sources_5_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_6$EN = !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd6 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_7 @@ -4277,9 +4666,9 @@ module mkPLIC_16_2_7(CLK, v_sources_6_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_7$EN = !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd7 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_8 @@ -4289,9 +4678,9 @@ module mkPLIC_16_2_7(CLK, v_sources_7_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_8$EN = !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd8 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_9 @@ -4301,200 +4690,200 @@ module mkPLIC_16_2_7(CLK, v_sources_8_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_9$EN = !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd9 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_0 assign m_vrg_source_prio_0$D_IN = MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26920[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 || + addr_offset__h29732[11:2] == 10'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d963 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_1 assign m_vrg_source_prio_1$D_IN = MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d974 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_10 assign m_vrg_source_prio_10$D_IN = MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_10$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d992 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_11 assign m_vrg_source_prio_11$D_IN = MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_11$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d994 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_12 assign m_vrg_source_prio_12$D_IN = MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_12$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d996 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_13 assign m_vrg_source_prio_13$D_IN = MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_13$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d998 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_14 assign m_vrg_source_prio_14$D_IN = MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_14$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1000 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_15 assign m_vrg_source_prio_15$D_IN = MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_15$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1002 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_16 assign m_vrg_source_prio_16$D_IN = MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_16$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1004 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_2 assign m_vrg_source_prio_2$D_IN = MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_2$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d976 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_3 assign m_vrg_source_prio_3$D_IN = MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_3$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d978 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_4 assign m_vrg_source_prio_4$D_IN = MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_4$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d980 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_5 assign m_vrg_source_prio_5$D_IN = MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_5$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d982 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_6 assign m_vrg_source_prio_6$D_IN = MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_6$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d984 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_7 assign m_vrg_source_prio_7$D_IN = MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_7$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d986 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_8 assign m_vrg_source_prio_8$D_IN = MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_8$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d988 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_9 assign m_vrg_source_prio_9$D_IN = MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_9$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d990 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_0 assign m_vrg_target_threshold_0$D_IN = MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd7 ; assign m_vrg_target_threshold_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2997 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_1 assign m_vrg_target_threshold_1$D_IN = MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd7 ; assign m_vrg_target_threshold_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2999 || WILL_FIRE_RL_m_rl_reset ; // register m_vvrg_ie_0_0 @@ -4779,12018 +5168,12051 @@ module mkPLIC_16_2_7(CLK, assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ; assign m_f_reset_rsps$CLR = 1'b0 ; - // submodule m_slave_xactor_f_rd_addr - assign m_slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign m_slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ; - assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_rd_data - assign m_slave_xactor_f_rd_data$D_IN = - { m_slave_xactor_f_rd_addr$D_OUT[96:93], - x__h26359, - rresp__h26201, - 1'd1 } ; - assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ; - assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_addr - assign m_slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign m_slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ; - assign m_slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_data - assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; - assign m_slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; - assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_resp - assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26925 } ; - assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; - assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ; - // remaining internal signals - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 : - ((x__h23671 == 32'h00200000) ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 : - x__h23671 != 32'h00200004 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 || - x__h24009 != 5'd0) ; - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - addr_offset__h13214[11:2] == 10'd0 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 : - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 : - ((x__h67099 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 : - x__h67099 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 || - !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? - addr_offset__h26920[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d838 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 ? + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 || + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311 : + ((x__h26136 == 32'h00200000) ? + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 : + x__h26136 != 32'h00200004 || + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 || + x__h26477 != 5'd0) ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 ? + addr_offset__h15646[11:2] == 10'd0 || + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109 : + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 ? + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 : + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d838) ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d878 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 ? + ((m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311) ? + 2'd0 : + 2'd2) : + CASE_x6136_0x200000_IF_m_slave_xactor_shim_arf_ETC__q50 ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d879 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 ? + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 ? + 2'd0 : + 2'd2) : + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d878 ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d880 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 ? + ((addr_offset__h15646[11:2] != 10'd0 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109) ? + 2'd0 : + 2'd2) : + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d879 ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d889 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 ? + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311 : + ((x__h26136 == 32'h00200000) ? + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 : + x__h26136 == 32'h00200004 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 && + x__h26477 == 5'd0) ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d891 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 ? + addr_offset__h15646[11:2] != 10'd0 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109 : + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 ? + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 : + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d889) ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3100 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 ? + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 || + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 : + ((x__h69947 == 32'h00200000) ? + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 : + x__h69947 != 32'h00200004 || + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 || + !SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030) ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 ? + addr_offset__h29732[11:2] == 10'd0 || + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 : + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 ? + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 : + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3100) ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3122 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 ? + ((m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026) ? + 2'd0 : + 2'd2) : + CASE_x9947_0x200000_IF_m_slave_xactor_shim_awf_ETC__q1 ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3123 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 ? + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 ? + 2'd0 : + 2'd2) : + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3122 ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3124 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 ? + ((addr_offset__h29732[11:2] != 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960) ? + 2'd0 : + 2'd2) : + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3123 ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3130 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 ? + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 : + ((x__h69947 == 32'h00200000) ? + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 : + x__h69947 == 32'h00200004 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 && + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030) ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3132 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 ? + addr_offset__h29732[11:2] != 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 : + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 ? + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 : + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3130) ; + assign IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3187 = + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3186 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3182 ; + assign IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3281 = + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3280 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3276 ; + assign IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d684 = + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d683 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d677 ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3192 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3191 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3187 ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3228 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3191 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? + (m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3186 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3226) ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3286 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3285 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3281 ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3322 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3285 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? + (m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3280 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3320) ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d691 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d690 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d684 ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d736 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d690 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? + (m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d683 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d734) ; + assign IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3197 = + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3196 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3192 ; + assign IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3291 = + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3290 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3286 ; + assign IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d698 = + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d697 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d691 ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3202 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3201 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3197 ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3230 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3201 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? + (m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3196 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3228) ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3296 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3295 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3291 ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3324 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3295 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? + (m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3290 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3322) ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d705 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d704 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d698 ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d738 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d704 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? + (m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d697 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d736) ; + assign IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3207 = + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3206 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3202 ; + assign IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3301 = + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3300 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3296 ; + assign IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d712 = + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d711 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d705 ; + assign IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3212 = + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3211 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3207 ; + assign IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3232 = + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3211 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? + (m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3206 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3230) ; + assign IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3306 = + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3305 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3301 ; + assign IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3326 = + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3305 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? + (m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3300 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3324) ; + assign IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d740 = + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d718 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? + (m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d711 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 = + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d738) ; + assign IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3142 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 = + assign IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3236 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 = - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? + assign IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d621 = + m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_sourc_ETC___d620 ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? + assign IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3147 = + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3146 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3142 ; + assign IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3241 = + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3240 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3236 ; + assign IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d628 = + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d627 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d621 ; + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3152 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3151 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3147 ; + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3220 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3151 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? + (m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3146 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3246 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3245 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3241 ; + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3314 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3245 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? + (m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3240 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d635 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d634 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d628 ; + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d728 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d634 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? + (m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d627 ? 5'd2 : - (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? + (m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_sourc_ETC___d620 ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? + assign IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3157 = + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3156 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3152 ; + assign IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3251 = + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3250 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3246 ; + assign IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d642 = + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d641 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d635 ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3162 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3161 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3157 ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3222 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3161 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? + (m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3156 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3220) ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3256 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3255 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3251 ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3316 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3255 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? + (m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3250 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3314) ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d649 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d648 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d642 ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d730 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d648 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? + (m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d641 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d728) ; + assign IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3167 = + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3166 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3162 ; + assign IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3261 = + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3260 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3256 ; + assign IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d656 = + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d655 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d649 ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3172 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3171 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3167 ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3224 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3171 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? + (m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3166 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3222) ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3266 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3265 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3261 ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3318 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3265 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? + (m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3260 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3316) ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d663 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d662 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d656 ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d732 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d662 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? + (m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d655 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d730) ; + assign IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3177 = + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3176 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3172 ; + assign IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3271 = + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3270 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3266 ; + assign IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d670 = + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d669 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d663 ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3182 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3181 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3177 ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3226 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3181 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? + (m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3176 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3224) ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3276 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3275 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3271 ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3320 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3275 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? + (m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3270 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3318) ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d677 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d676 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d670 ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d734 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d676 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? + (m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d669 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ; - assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 && + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d732) ; + assign NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 = m_cfg_verbosity > 4'd1 ; + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d143 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23671 == 32'h00200000 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d317 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23671 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24009 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d607 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 && + x__h26136 == 32'h00200000 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23671 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24009 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 && + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 && + x__h26136 == 32'h00200004 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 && + x__h26477 == 5'd0 && + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d763 ; + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d813 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 && + x__h26136 == 32'h00200004 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 && + x__h26477 == 5'd0 && + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d763 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23671 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24009 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h30674 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h31884 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h33094 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h34304 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h35514 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h36724 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h37934 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h39144 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h40354 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h41564 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h42774 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h43984 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h45194 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h46404 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h47614 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h48824 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h50034 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h51244 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h52454 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h53664 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h54874 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h56084 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h57294 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h58504 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h59714 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h60924 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h62134 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h63344 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h64554 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h65764 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 && + x__h26136 == 32'h00200004 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 && + x__h26477 != 5'd0 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1017 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67099 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67099 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1029 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h32311 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h33521 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h34731 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h35941 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h37151 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h38361 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h39571 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h40781 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h41991 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h43201 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h44411 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h45621 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h46831 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h48041 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h49251 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h50461 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h51671 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h52881 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h54091 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h55301 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h56511 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h57721 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h58931 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h60141 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h61351 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h62561 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h63771 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h64981 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h66191 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h67401 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h68611 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2981 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67099 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67099 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 && + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2994 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + x__h69947 == 32'h00200000 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3005 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + x__h69947 == 32'h00200000 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67099 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && - !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - addr_offset__h26920[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + x__h69947 == 32'h00200004 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 && + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3077 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + x__h69947 == 32'h00200004 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 && + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h29464 <= 10'd16 ; - assign NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311 = + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + x__h69947 == 32'h00200004 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 && + !SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d963 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + addr_offset__h29732[11:2] != 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign NOT_m_vrg_source_busy_10_022_434_AND_NOT_m_cfg_ETC___d3438 = !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319 = + assign NOT_m_vrg_source_busy_11_023_442_AND_NOT_m_cfg_ETC___d3446 = !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_11 != v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327 = + assign NOT_m_vrg_source_busy_12_024_450_AND_NOT_m_cfg_ETC___d3454 = !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_12 != v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335 = + assign NOT_m_vrg_source_busy_13_025_458_AND_NOT_m_cfg_ETC___d3462 = !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_13 != v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343 = + assign NOT_m_vrg_source_busy_14_026_466_AND_NOT_m_cfg_ETC___d3470 = !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_14 != v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351 = + assign NOT_m_vrg_source_busy_15_027_474_AND_NOT_m_cfg_ETC___d3478 = !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_15 != v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359 = + assign NOT_m_vrg_source_busy_16_028_482_AND_NOT_m_cfg_ETC___d3486 = !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_16 != v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240 = + assign NOT_m_vrg_source_busy_1_013_363_AND_NOT_m_cfg__ETC___d3367 = !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247 = + assign NOT_m_vrg_source_busy_2_014_370_AND_NOT_m_cfg__ETC___d3374 = !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255 = + assign NOT_m_vrg_source_busy_3_015_378_AND_NOT_m_cfg__ETC___d3382 = !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263 = + assign NOT_m_vrg_source_busy_4_016_386_AND_NOT_m_cfg__ETC___d3390 = !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271 = + assign NOT_m_vrg_source_busy_5_017_394_AND_NOT_m_cfg__ETC___d3398 = !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279 = + assign NOT_m_vrg_source_busy_6_018_402_AND_NOT_m_cfg__ETC___d3406 = !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287 = + assign NOT_m_vrg_source_busy_7_019_410_AND_NOT_m_cfg__ETC___d3414 = !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295 = + assign NOT_m_vrg_source_busy_8_020_418_AND_NOT_m_cfg__ETC___d3422 = !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303 = + assign NOT_m_vrg_source_busy_9_021_426_AND_NOT_m_cfg__ETC___d3430 = !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; assign _dfoo1 = - source_id__h64554 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo10 = - (source_id__h64554 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo100 = - (source_id__h63344 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo32 ; assign _dfoo1000 = - (source_id__h47614 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo932 ; assign _dfoo1001 = - source_id__h47614 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo865 ; assign _dfoo1002 = - (source_id__h47614 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo934 ; assign _dfoo1003 = - source_id__h47614 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo867 ; assign _dfoo1004 = - (source_id__h47614 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo936 ; assign _dfoo1005 = - source_id__h47614 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo869 ; assign _dfoo1006 = - (source_id__h47614 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo938 ; assign _dfoo1007 = - source_id__h47614 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo871 ; assign _dfoo1008 = - (source_id__h47614 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo940 ; assign _dfoo1009 = - source_id__h47614 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo873 ; assign _dfoo1010 = - (source_id__h47614 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo942 ; assign _dfoo1011 = - source_id__h47614 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo875 ; assign _dfoo1012 = - (source_id__h47614 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo944 ; assign _dfoo1013 = - source_id__h47614 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo877 ; assign _dfoo1014 = - (source_id__h47614 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo946 ; assign _dfoo1015 = - source_id__h47614 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo879 ; assign _dfoo1016 = - (source_id__h47614 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo948 ; assign _dfoo1017 = - source_id__h47614 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo881 ; assign _dfoo1018 = - (source_id__h47614 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo950 ; assign _dfoo1019 = - source_id__h47614 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo883 ; assign _dfoo102 = - (source_id__h63344 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo34 ; assign _dfoo1020 = - (source_id__h47614 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo952 ; assign _dfoo1022 = - (source_id__h46404 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo954 ; assign _dfoo1024 = - (source_id__h46404 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo956 ; assign _dfoo1026 = - (source_id__h46404 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo958 ; assign _dfoo1028 = - (source_id__h46404 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo960 ; assign _dfoo1030 = - (source_id__h46404 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo962 ; assign _dfoo1032 = - (source_id__h46404 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo964 ; assign _dfoo1034 = - (source_id__h46404 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo966 ; assign _dfoo1036 = - (source_id__h46404 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo968 ; assign _dfoo1038 = - (source_id__h46404 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo970 ; assign _dfoo104 = - (source_id__h63344 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo36 ; assign _dfoo1040 = - (source_id__h46404 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo972 ; assign _dfoo1042 = - (source_id__h46404 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo974 ; assign _dfoo1044 = - (source_id__h46404 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo976 ; assign _dfoo1046 = - (source_id__h46404 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo978 ; assign _dfoo1048 = - (source_id__h46404 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo980 ; assign _dfoo1050 = - (source_id__h46404 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo982 ; assign _dfoo1052 = - (source_id__h46404 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo984 ; assign _dfoo1054 = - (source_id__h46404 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo986 ; assign _dfoo1056 = - (source_id__h46404 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo988 ; assign _dfoo1058 = - (source_id__h46404 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo990 ; assign _dfoo106 = - (source_id__h63344 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo38 ; assign _dfoo1060 = - (source_id__h46404 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo992 ; assign _dfoo1062 = - (source_id__h46404 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo994 ; assign _dfoo1064 = - (source_id__h46404 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo996 ; assign _dfoo1066 = - (source_id__h46404 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo998 ; assign _dfoo1068 = - (source_id__h46404 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1000 ; assign _dfoo1070 = - (source_id__h46404 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1002 ; assign _dfoo1072 = - (source_id__h46404 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1004 ; assign _dfoo1074 = - (source_id__h46404 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1006 ; assign _dfoo1076 = - (source_id__h46404 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1008 ; assign _dfoo1078 = - (source_id__h46404 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1010 ; assign _dfoo108 = - (source_id__h63344 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo40 ; assign _dfoo1080 = - (source_id__h46404 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1012 ; assign _dfoo1082 = - (source_id__h46404 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1014 ; assign _dfoo1084 = - (source_id__h46404 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1016 ; assign _dfoo1086 = - (source_id__h46404 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1018 ; assign _dfoo1088 = - (source_id__h46404 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1020 ; assign _dfoo1089 = - source_id__h45194 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo953 ; assign _dfoo1090 = - (source_id__h45194 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1022 ; assign _dfoo1091 = - source_id__h45194 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo955 ; assign _dfoo1092 = - (source_id__h45194 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1024 ; assign _dfoo1093 = - source_id__h45194 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo957 ; assign _dfoo1094 = - (source_id__h45194 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1026 ; assign _dfoo1095 = - source_id__h45194 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo959 ; assign _dfoo1096 = - (source_id__h45194 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1028 ; assign _dfoo1097 = - source_id__h45194 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo961 ; assign _dfoo1098 = - (source_id__h45194 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1030 ; assign _dfoo1099 = - source_id__h45194 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo963 ; assign _dfoo11 = - source_id__h64554 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo110 = - (source_id__h63344 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo42 ; assign _dfoo1100 = - (source_id__h45194 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1032 ; assign _dfoo1101 = - source_id__h45194 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo965 ; assign _dfoo1102 = - (source_id__h45194 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1034 ; assign _dfoo1103 = - source_id__h45194 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo967 ; assign _dfoo1104 = - (source_id__h45194 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1036 ; assign _dfoo1105 = - source_id__h45194 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo969 ; assign _dfoo1106 = - (source_id__h45194 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1038 ; assign _dfoo1107 = - source_id__h45194 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo971 ; assign _dfoo1108 = - (source_id__h45194 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1040 ; assign _dfoo1109 = - source_id__h45194 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo973 ; assign _dfoo1110 = - (source_id__h45194 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1042 ; assign _dfoo1111 = - source_id__h45194 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo975 ; assign _dfoo1112 = - (source_id__h45194 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1044 ; assign _dfoo1113 = - source_id__h45194 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo977 ; assign _dfoo1114 = - (source_id__h45194 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1046 ; assign _dfoo1115 = - source_id__h45194 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo979 ; assign _dfoo1116 = - (source_id__h45194 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1048 ; assign _dfoo1117 = - source_id__h45194 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo981 ; assign _dfoo1118 = - (source_id__h45194 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1050 ; assign _dfoo1119 = - source_id__h45194 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo983 ; assign _dfoo112 = - (source_id__h63344 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo44 ; assign _dfoo1120 = - (source_id__h45194 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1052 ; assign _dfoo1121 = - source_id__h45194 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo985 ; assign _dfoo1122 = - (source_id__h45194 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1054 ; assign _dfoo1123 = - source_id__h45194 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo987 ; assign _dfoo1124 = - (source_id__h45194 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1056 ; assign _dfoo1125 = - source_id__h45194 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo989 ; assign _dfoo1126 = - (source_id__h45194 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1058 ; assign _dfoo1127 = - source_id__h45194 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo991 ; assign _dfoo1128 = - (source_id__h45194 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1060 ; assign _dfoo1129 = - source_id__h45194 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo993 ; assign _dfoo1130 = - (source_id__h45194 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1062 ; assign _dfoo1131 = - source_id__h45194 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo995 ; assign _dfoo1132 = - (source_id__h45194 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1064 ; assign _dfoo1133 = - source_id__h45194 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo997 ; assign _dfoo1134 = - (source_id__h45194 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1066 ; assign _dfoo1135 = - source_id__h45194 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo999 ; assign _dfoo1136 = - (source_id__h45194 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1068 ; assign _dfoo1137 = - source_id__h45194 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1001 ; assign _dfoo1138 = - (source_id__h45194 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1070 ; assign _dfoo1139 = - source_id__h45194 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1003 ; assign _dfoo114 = - (source_id__h63344 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo46 ; assign _dfoo1140 = - (source_id__h45194 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1072 ; assign _dfoo1141 = - source_id__h45194 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1005 ; assign _dfoo1142 = - (source_id__h45194 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1074 ; assign _dfoo1143 = - source_id__h45194 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1007 ; assign _dfoo1144 = - (source_id__h45194 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1076 ; assign _dfoo1145 = - source_id__h45194 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1009 ; assign _dfoo1146 = - (source_id__h45194 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1078 ; assign _dfoo1147 = - source_id__h45194 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1011 ; assign _dfoo1148 = - (source_id__h45194 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1080 ; assign _dfoo1149 = - source_id__h45194 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1013 ; assign _dfoo1150 = - (source_id__h45194 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1082 ; assign _dfoo1151 = - source_id__h45194 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1015 ; assign _dfoo1152 = - (source_id__h45194 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1084 ; assign _dfoo1153 = - source_id__h45194 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1017 ; assign _dfoo1154 = - (source_id__h45194 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1086 ; assign _dfoo1155 = - source_id__h45194 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1019 ; assign _dfoo1156 = - (source_id__h45194 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1088 ; assign _dfoo1158 = - (source_id__h43984 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1090 ; assign _dfoo116 = - (source_id__h63344 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo48 ; assign _dfoo1160 = - (source_id__h43984 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1092 ; assign _dfoo1162 = - (source_id__h43984 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1094 ; assign _dfoo1164 = - (source_id__h43984 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1096 ; assign _dfoo1166 = - (source_id__h43984 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1098 ; assign _dfoo1168 = - (source_id__h43984 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1100 ; assign _dfoo1170 = - (source_id__h43984 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1102 ; assign _dfoo1172 = - (source_id__h43984 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1104 ; assign _dfoo1174 = - (source_id__h43984 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1106 ; assign _dfoo1176 = - (source_id__h43984 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1108 ; assign _dfoo1178 = - (source_id__h43984 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1110 ; assign _dfoo118 = - (source_id__h63344 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo50 ; assign _dfoo1180 = - (source_id__h43984 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1112 ; assign _dfoo1182 = - (source_id__h43984 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1114 ; assign _dfoo1184 = - (source_id__h43984 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1116 ; assign _dfoo1186 = - (source_id__h43984 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1118 ; assign _dfoo1188 = - (source_id__h43984 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1120 ; assign _dfoo1190 = - (source_id__h43984 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1122 ; assign _dfoo1192 = - (source_id__h43984 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1124 ; assign _dfoo1194 = - (source_id__h43984 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1126 ; assign _dfoo1196 = - (source_id__h43984 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1128 ; assign _dfoo1198 = - (source_id__h43984 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1130 ; assign _dfoo12 = - (source_id__h64554 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo120 = - (source_id__h63344 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo52 ; assign _dfoo1200 = - (source_id__h43984 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1132 ; assign _dfoo1202 = - (source_id__h43984 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1134 ; assign _dfoo1204 = - (source_id__h43984 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1136 ; assign _dfoo1206 = - (source_id__h43984 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1138 ; assign _dfoo1208 = - (source_id__h43984 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1140 ; assign _dfoo1210 = - (source_id__h43984 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1142 ; assign _dfoo1212 = - (source_id__h43984 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1144 ; assign _dfoo1214 = - (source_id__h43984 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1146 ; assign _dfoo1216 = - (source_id__h43984 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1148 ; assign _dfoo1218 = - (source_id__h43984 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1150 ; assign _dfoo122 = - (source_id__h63344 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo54 ; assign _dfoo1220 = - (source_id__h43984 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1152 ; assign _dfoo1222 = - (source_id__h43984 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1154 ; assign _dfoo1224 = - (source_id__h43984 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1156 ; assign _dfoo1225 = - source_id__h42774 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1089 ; assign _dfoo1226 = - (source_id__h42774 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1158 ; assign _dfoo1227 = - source_id__h42774 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1091 ; assign _dfoo1228 = - (source_id__h42774 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1160 ; assign _dfoo1229 = - source_id__h42774 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1093 ; assign _dfoo1230 = - (source_id__h42774 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1162 ; assign _dfoo1231 = - source_id__h42774 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1095 ; assign _dfoo1232 = - (source_id__h42774 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1164 ; assign _dfoo1233 = - source_id__h42774 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1097 ; assign _dfoo1234 = - (source_id__h42774 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1166 ; assign _dfoo1235 = - source_id__h42774 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1099 ; assign _dfoo1236 = - (source_id__h42774 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1168 ; assign _dfoo1237 = - source_id__h42774 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1101 ; assign _dfoo1238 = - (source_id__h42774 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1170 ; assign _dfoo1239 = - source_id__h42774 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1103 ; assign _dfoo124 = - (source_id__h63344 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo56 ; assign _dfoo1240 = - (source_id__h42774 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1172 ; assign _dfoo1241 = - source_id__h42774 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1105 ; assign _dfoo1242 = - (source_id__h42774 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1174 ; assign _dfoo1243 = - source_id__h42774 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1107 ; assign _dfoo1244 = - (source_id__h42774 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1176 ; assign _dfoo1245 = - source_id__h42774 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1109 ; assign _dfoo1246 = - (source_id__h42774 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1178 ; assign _dfoo1247 = - source_id__h42774 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1111 ; assign _dfoo1248 = - (source_id__h42774 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1180 ; assign _dfoo1249 = - source_id__h42774 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1113 ; assign _dfoo1250 = - (source_id__h42774 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1182 ; assign _dfoo1251 = - source_id__h42774 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1115 ; assign _dfoo1252 = - (source_id__h42774 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1184 ; assign _dfoo1253 = - source_id__h42774 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1117 ; assign _dfoo1254 = - (source_id__h42774 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1186 ; assign _dfoo1255 = - source_id__h42774 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1119 ; assign _dfoo1256 = - (source_id__h42774 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1188 ; assign _dfoo1257 = - source_id__h42774 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1121 ; assign _dfoo1258 = - (source_id__h42774 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1190 ; assign _dfoo1259 = - source_id__h42774 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1123 ; assign _dfoo126 = - (source_id__h63344 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo58 ; assign _dfoo1260 = - (source_id__h42774 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1192 ; assign _dfoo1261 = - source_id__h42774 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1125 ; assign _dfoo1262 = - (source_id__h42774 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1194 ; assign _dfoo1263 = - source_id__h42774 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1127 ; assign _dfoo1264 = - (source_id__h42774 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1196 ; assign _dfoo1265 = - source_id__h42774 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1129 ; assign _dfoo1266 = - (source_id__h42774 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1198 ; assign _dfoo1267 = - source_id__h42774 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1131 ; assign _dfoo1268 = - (source_id__h42774 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1200 ; assign _dfoo1269 = - source_id__h42774 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1133 ; assign _dfoo1270 = - (source_id__h42774 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1202 ; assign _dfoo1271 = - source_id__h42774 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1135 ; assign _dfoo1272 = - (source_id__h42774 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1204 ; assign _dfoo1273 = - source_id__h42774 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1137 ; assign _dfoo1274 = - (source_id__h42774 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1206 ; assign _dfoo1275 = - source_id__h42774 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1139 ; assign _dfoo1276 = - (source_id__h42774 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1208 ; assign _dfoo1277 = - source_id__h42774 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1141 ; assign _dfoo1278 = - (source_id__h42774 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1210 ; assign _dfoo1279 = - source_id__h42774 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1143 ; assign _dfoo128 = - (source_id__h63344 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo60 ; assign _dfoo1280 = - (source_id__h42774 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1212 ; assign _dfoo1281 = - source_id__h42774 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1145 ; assign _dfoo1282 = - (source_id__h42774 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1214 ; assign _dfoo1283 = - source_id__h42774 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1147 ; assign _dfoo1284 = - (source_id__h42774 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1216 ; assign _dfoo1285 = - source_id__h42774 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1149 ; assign _dfoo1286 = - (source_id__h42774 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1218 ; assign _dfoo1287 = - source_id__h42774 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1151 ; assign _dfoo1288 = - (source_id__h42774 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1220 ; assign _dfoo1289 = - source_id__h42774 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1153 ; assign _dfoo1290 = - (source_id__h42774 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1222 ; assign _dfoo1291 = - source_id__h42774 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1155 ; assign _dfoo1292 = - (source_id__h42774 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1224 ; assign _dfoo1294 = - (source_id__h41564 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1226 ; assign _dfoo1296 = - (source_id__h41564 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1228 ; assign _dfoo1298 = - (source_id__h41564 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1230 ; assign _dfoo13 = - source_id__h64554 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo130 = - (source_id__h63344 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo62 ; assign _dfoo1300 = - (source_id__h41564 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1232 ; assign _dfoo1302 = - (source_id__h41564 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1234 ; assign _dfoo1304 = - (source_id__h41564 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1236 ; assign _dfoo1306 = - (source_id__h41564 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1238 ; assign _dfoo1308 = - (source_id__h41564 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1240 ; assign _dfoo1310 = - (source_id__h41564 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1242 ; assign _dfoo1312 = - (source_id__h41564 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1244 ; assign _dfoo1314 = - (source_id__h41564 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1246 ; assign _dfoo1316 = - (source_id__h41564 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1248 ; assign _dfoo1318 = - (source_id__h41564 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1250 ; assign _dfoo132 = - (source_id__h63344 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo64 ; assign _dfoo1320 = - (source_id__h41564 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1252 ; assign _dfoo1322 = - (source_id__h41564 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1254 ; assign _dfoo1324 = - (source_id__h41564 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1256 ; assign _dfoo1326 = - (source_id__h41564 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1258 ; assign _dfoo1328 = - (source_id__h41564 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1260 ; assign _dfoo1330 = - (source_id__h41564 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1262 ; assign _dfoo1332 = - (source_id__h41564 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1264 ; assign _dfoo1334 = - (source_id__h41564 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1266 ; assign _dfoo1336 = - (source_id__h41564 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1268 ; assign _dfoo1338 = - (source_id__h41564 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1270 ; assign _dfoo134 = - (source_id__h63344 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo66 ; assign _dfoo1340 = - (source_id__h41564 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1272 ; assign _dfoo1342 = - (source_id__h41564 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1274 ; assign _dfoo1344 = - (source_id__h41564 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1276 ; assign _dfoo1346 = - (source_id__h41564 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1278 ; assign _dfoo1348 = - (source_id__h41564 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1280 ; assign _dfoo1350 = - (source_id__h41564 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1282 ; assign _dfoo1352 = - (source_id__h41564 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1284 ; assign _dfoo1354 = - (source_id__h41564 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1286 ; assign _dfoo1356 = - (source_id__h41564 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1288 ; assign _dfoo1358 = - (source_id__h41564 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1290 ; assign _dfoo136 = - (source_id__h63344 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo68 ; assign _dfoo1360 = - (source_id__h41564 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1292 ; assign _dfoo1361 = - source_id__h40354 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1225 ; assign _dfoo1362 = - (source_id__h40354 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1294 ; assign _dfoo1363 = - source_id__h40354 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1227 ; assign _dfoo1364 = - (source_id__h40354 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1296 ; assign _dfoo1365 = - source_id__h40354 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1229 ; assign _dfoo1366 = - (source_id__h40354 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1298 ; assign _dfoo1367 = - source_id__h40354 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1231 ; assign _dfoo1368 = - (source_id__h40354 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1300 ; assign _dfoo1369 = - source_id__h40354 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1233 ; assign _dfoo137 = - source_id__h62134 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo1 ; assign _dfoo1370 = - (source_id__h40354 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1302 ; assign _dfoo1371 = - source_id__h40354 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1235 ; assign _dfoo1372 = - (source_id__h40354 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1304 ; assign _dfoo1373 = - source_id__h40354 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1237 ; assign _dfoo1374 = - (source_id__h40354 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1306 ; assign _dfoo1375 = - source_id__h40354 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1239 ; assign _dfoo1376 = - (source_id__h40354 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1308 ; assign _dfoo1377 = - source_id__h40354 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1241 ; assign _dfoo1378 = - (source_id__h40354 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1310 ; assign _dfoo1379 = - source_id__h40354 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1243 ; assign _dfoo138 = - (source_id__h62134 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo70 ; assign _dfoo1380 = - (source_id__h40354 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1312 ; assign _dfoo1381 = - source_id__h40354 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1245 ; assign _dfoo1382 = - (source_id__h40354 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1314 ; assign _dfoo1383 = - source_id__h40354 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1247 ; assign _dfoo1384 = - (source_id__h40354 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1316 ; assign _dfoo1385 = - source_id__h40354 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1249 ; assign _dfoo1386 = - (source_id__h40354 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1318 ; assign _dfoo1387 = - source_id__h40354 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1251 ; assign _dfoo1388 = - (source_id__h40354 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1320 ; assign _dfoo1389 = - source_id__h40354 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1253 ; assign _dfoo139 = - source_id__h62134 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo3 ; assign _dfoo1390 = - (source_id__h40354 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1322 ; assign _dfoo1391 = - source_id__h40354 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1255 ; assign _dfoo1392 = - (source_id__h40354 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1324 ; assign _dfoo1393 = - source_id__h40354 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1257 ; assign _dfoo1394 = - (source_id__h40354 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1326 ; assign _dfoo1395 = - source_id__h40354 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1259 ; assign _dfoo1396 = - (source_id__h40354 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1328 ; assign _dfoo1397 = - source_id__h40354 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1261 ; assign _dfoo1398 = - (source_id__h40354 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1330 ; assign _dfoo1399 = - source_id__h40354 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1263 ; assign _dfoo14 = - (source_id__h64554 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo140 = - (source_id__h62134 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo72 ; assign _dfoo1400 = - (source_id__h40354 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1332 ; assign _dfoo1401 = - source_id__h40354 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1265 ; assign _dfoo1402 = - (source_id__h40354 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1334 ; assign _dfoo1403 = - source_id__h40354 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1267 ; assign _dfoo1404 = - (source_id__h40354 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1336 ; assign _dfoo1405 = - source_id__h40354 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1269 ; assign _dfoo1406 = - (source_id__h40354 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1338 ; assign _dfoo1407 = - source_id__h40354 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1271 ; assign _dfoo1408 = - (source_id__h40354 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1340 ; assign _dfoo1409 = - source_id__h40354 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1273 ; assign _dfoo141 = - source_id__h62134 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo5 ; assign _dfoo1410 = - (source_id__h40354 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1342 ; assign _dfoo1411 = - source_id__h40354 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1275 ; assign _dfoo1412 = - (source_id__h40354 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1344 ; assign _dfoo1413 = - source_id__h40354 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1277 ; assign _dfoo1414 = - (source_id__h40354 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1346 ; assign _dfoo1415 = - source_id__h40354 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1279 ; assign _dfoo1416 = - (source_id__h40354 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1348 ; assign _dfoo1417 = - source_id__h40354 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1281 ; assign _dfoo1418 = - (source_id__h40354 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1350 ; assign _dfoo1419 = - source_id__h40354 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1283 ; assign _dfoo142 = - (source_id__h62134 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo74 ; assign _dfoo1420 = - (source_id__h40354 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1352 ; assign _dfoo1421 = - source_id__h40354 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1285 ; assign _dfoo1422 = - (source_id__h40354 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1354 ; assign _dfoo1423 = - source_id__h40354 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1287 ; assign _dfoo1424 = - (source_id__h40354 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1356 ; assign _dfoo1425 = - source_id__h40354 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1289 ; assign _dfoo1426 = - (source_id__h40354 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1358 ; assign _dfoo1427 = - source_id__h40354 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1291 ; assign _dfoo1428 = - (source_id__h40354 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1360 ; assign _dfoo143 = - source_id__h62134 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo7 ; assign _dfoo1430 = - (source_id__h39144 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1362 ; assign _dfoo1432 = - (source_id__h39144 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1364 ; assign _dfoo1434 = - (source_id__h39144 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1366 ; assign _dfoo1436 = - (source_id__h39144 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1368 ; assign _dfoo1438 = - (source_id__h39144 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1370 ; assign _dfoo144 = - (source_id__h62134 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo76 ; assign _dfoo1440 = - (source_id__h39144 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1372 ; assign _dfoo1442 = - (source_id__h39144 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1374 ; assign _dfoo1444 = - (source_id__h39144 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1376 ; assign _dfoo1446 = - (source_id__h39144 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1378 ; assign _dfoo1448 = - (source_id__h39144 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1380 ; assign _dfoo145 = - source_id__h62134 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo9 ; assign _dfoo1450 = - (source_id__h39144 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1382 ; assign _dfoo1452 = - (source_id__h39144 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1384 ; assign _dfoo1454 = - (source_id__h39144 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1386 ; assign _dfoo1456 = - (source_id__h39144 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1388 ; assign _dfoo1458 = - (source_id__h39144 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1390 ; assign _dfoo146 = - (source_id__h62134 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo78 ; assign _dfoo1460 = - (source_id__h39144 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1392 ; assign _dfoo1462 = - (source_id__h39144 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1394 ; assign _dfoo1464 = - (source_id__h39144 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1396 ; assign _dfoo1466 = - (source_id__h39144 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1398 ; assign _dfoo1468 = - (source_id__h39144 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1400 ; assign _dfoo147 = - source_id__h62134 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo11 ; assign _dfoo1470 = - (source_id__h39144 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1402 ; assign _dfoo1472 = - (source_id__h39144 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1404 ; assign _dfoo1474 = - (source_id__h39144 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1406 ; assign _dfoo1476 = - (source_id__h39144 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1408 ; assign _dfoo1478 = - (source_id__h39144 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1410 ; assign _dfoo148 = - (source_id__h62134 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo80 ; assign _dfoo1480 = - (source_id__h39144 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1412 ; assign _dfoo1482 = - (source_id__h39144 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1414 ; assign _dfoo1484 = - (source_id__h39144 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1416 ; assign _dfoo1486 = - (source_id__h39144 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1418 ; assign _dfoo1488 = - (source_id__h39144 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1420 ; assign _dfoo149 = - source_id__h62134 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo13 ; assign _dfoo1490 = - (source_id__h39144 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1422 ; assign _dfoo1492 = - (source_id__h39144 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1424 ; assign _dfoo1494 = - (source_id__h39144 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1426 ; assign _dfoo1496 = - (source_id__h39144 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1428 ; assign _dfoo1497 = - source_id__h37934 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1361 ; assign _dfoo1498 = - (source_id__h37934 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1430 ; assign _dfoo1499 = - source_id__h37934 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1363 ; assign _dfoo15 = - source_id__h64554 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo150 = - (source_id__h62134 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo82 ; assign _dfoo1500 = - (source_id__h37934 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1432 ; assign _dfoo1501 = - source_id__h37934 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1365 ; assign _dfoo1502 = - (source_id__h37934 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1434 ; assign _dfoo1503 = - source_id__h37934 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1367 ; assign _dfoo1504 = - (source_id__h37934 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1436 ; assign _dfoo1505 = - source_id__h37934 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1369 ; assign _dfoo1506 = - (source_id__h37934 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1438 ; assign _dfoo1507 = - source_id__h37934 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1371 ; assign _dfoo1508 = - (source_id__h37934 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1440 ; assign _dfoo1509 = - source_id__h37934 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1373 ; assign _dfoo151 = - source_id__h62134 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo15 ; assign _dfoo1510 = - (source_id__h37934 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1442 ; assign _dfoo1511 = - source_id__h37934 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1375 ; assign _dfoo1512 = - (source_id__h37934 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1444 ; assign _dfoo1513 = - source_id__h37934 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1377 ; assign _dfoo1514 = - (source_id__h37934 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1446 ; assign _dfoo1515 = - source_id__h37934 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1379 ; assign _dfoo1516 = - (source_id__h37934 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1448 ; assign _dfoo1517 = - source_id__h37934 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1381 ; assign _dfoo1518 = - (source_id__h37934 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1450 ; assign _dfoo1519 = - source_id__h37934 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1383 ; assign _dfoo152 = - (source_id__h62134 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo84 ; assign _dfoo1520 = - (source_id__h37934 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1452 ; assign _dfoo1521 = - source_id__h37934 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1385 ; assign _dfoo1522 = - (source_id__h37934 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1454 ; assign _dfoo1523 = - source_id__h37934 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1387 ; assign _dfoo1524 = - (source_id__h37934 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1456 ; assign _dfoo1525 = - source_id__h37934 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1389 ; assign _dfoo1526 = - (source_id__h37934 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1458 ; assign _dfoo1527 = - source_id__h37934 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1391 ; assign _dfoo1528 = - (source_id__h37934 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1460 ; assign _dfoo1529 = - source_id__h37934 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1393 ; assign _dfoo153 = - source_id__h62134 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo17 ; assign _dfoo1530 = - (source_id__h37934 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1462 ; assign _dfoo1531 = - source_id__h37934 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1395 ; assign _dfoo1532 = - (source_id__h37934 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1464 ; assign _dfoo1533 = - source_id__h37934 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1397 ; assign _dfoo1534 = - (source_id__h37934 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1466 ; assign _dfoo1535 = - source_id__h37934 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1399 ; assign _dfoo1536 = - (source_id__h37934 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1468 ; assign _dfoo1537 = - source_id__h37934 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1401 ; assign _dfoo1538 = - (source_id__h37934 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1470 ; assign _dfoo1539 = - source_id__h37934 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1403 ; assign _dfoo154 = - (source_id__h62134 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo86 ; assign _dfoo1540 = - (source_id__h37934 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1472 ; assign _dfoo1541 = - source_id__h37934 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1405 ; assign _dfoo1542 = - (source_id__h37934 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1474 ; assign _dfoo1543 = - source_id__h37934 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1407 ; assign _dfoo1544 = - (source_id__h37934 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1476 ; assign _dfoo1545 = - source_id__h37934 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1409 ; assign _dfoo1546 = - (source_id__h37934 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1478 ; assign _dfoo1547 = - source_id__h37934 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1411 ; assign _dfoo1548 = - (source_id__h37934 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1480 ; assign _dfoo1549 = - source_id__h37934 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1413 ; assign _dfoo155 = - source_id__h62134 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo19 ; assign _dfoo1550 = - (source_id__h37934 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1482 ; assign _dfoo1551 = - source_id__h37934 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1415 ; assign _dfoo1552 = - (source_id__h37934 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1484 ; assign _dfoo1553 = - source_id__h37934 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1417 ; assign _dfoo1554 = - (source_id__h37934 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1486 ; assign _dfoo1555 = - source_id__h37934 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1419 ; assign _dfoo1556 = - (source_id__h37934 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1488 ; assign _dfoo1557 = - source_id__h37934 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1421 ; assign _dfoo1558 = - (source_id__h37934 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1490 ; assign _dfoo1559 = - source_id__h37934 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1423 ; assign _dfoo156 = - (source_id__h62134 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo88 ; assign _dfoo1560 = - (source_id__h37934 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1492 ; assign _dfoo1561 = - source_id__h37934 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1425 ; assign _dfoo1562 = - (source_id__h37934 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1494 ; assign _dfoo1563 = - source_id__h37934 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1427 ; assign _dfoo1564 = - (source_id__h37934 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1496 ; assign _dfoo1566 = - (source_id__h36724 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1498 ; assign _dfoo1568 = - (source_id__h36724 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1500 ; assign _dfoo157 = - source_id__h62134 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo21 ; assign _dfoo1570 = - (source_id__h36724 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1502 ; assign _dfoo1572 = - (source_id__h36724 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1504 ; assign _dfoo1574 = - (source_id__h36724 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1506 ; assign _dfoo1576 = - (source_id__h36724 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1508 ; assign _dfoo1578 = - (source_id__h36724 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1510 ; assign _dfoo158 = - (source_id__h62134 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo90 ; assign _dfoo1580 = - (source_id__h36724 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1512 ; assign _dfoo1582 = - (source_id__h36724 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1514 ; assign _dfoo1584 = - (source_id__h36724 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1516 ; assign _dfoo1586 = - (source_id__h36724 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1518 ; assign _dfoo1588 = - (source_id__h36724 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1520 ; assign _dfoo159 = - source_id__h62134 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo23 ; assign _dfoo1590 = - (source_id__h36724 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1522 ; assign _dfoo1592 = - (source_id__h36724 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1524 ; assign _dfoo1594 = - (source_id__h36724 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1526 ; assign _dfoo1596 = - (source_id__h36724 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1528 ; assign _dfoo1598 = - (source_id__h36724 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1530 ; assign _dfoo16 = - (source_id__h64554 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo160 = - (source_id__h62134 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo92 ; assign _dfoo1600 = - (source_id__h36724 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1532 ; assign _dfoo1602 = - (source_id__h36724 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1534 ; assign _dfoo1604 = - (source_id__h36724 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1536 ; assign _dfoo1606 = - (source_id__h36724 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1538 ; assign _dfoo1608 = - (source_id__h36724 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1540 ; assign _dfoo161 = - source_id__h62134 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo25 ; assign _dfoo1610 = - (source_id__h36724 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1542 ; assign _dfoo1612 = - (source_id__h36724 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1544 ; assign _dfoo1614 = - (source_id__h36724 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1546 ; assign _dfoo1616 = - (source_id__h36724 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1548 ; assign _dfoo1618 = - (source_id__h36724 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1550 ; assign _dfoo162 = - (source_id__h62134 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo94 ; assign _dfoo1620 = - (source_id__h36724 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1552 ; assign _dfoo1622 = - (source_id__h36724 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1554 ; assign _dfoo1624 = - (source_id__h36724 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1556 ; assign _dfoo1626 = - (source_id__h36724 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1558 ; assign _dfoo1628 = - (source_id__h36724 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1560 ; assign _dfoo163 = - source_id__h62134 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo27 ; assign _dfoo1630 = - (source_id__h36724 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1562 ; assign _dfoo1632 = - (source_id__h36724 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1564 ; assign _dfoo1633 = - source_id__h35514 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1497 ; assign _dfoo1634 = - (source_id__h35514 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1566 ; assign _dfoo1635 = - source_id__h35514 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1499 ; assign _dfoo1636 = - (source_id__h35514 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1568 ; assign _dfoo1637 = - source_id__h35514 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1501 ; assign _dfoo1638 = - (source_id__h35514 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1570 ; assign _dfoo1639 = - source_id__h35514 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1503 ; assign _dfoo164 = - (source_id__h62134 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo96 ; assign _dfoo1640 = - (source_id__h35514 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1572 ; assign _dfoo1641 = - source_id__h35514 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1505 ; assign _dfoo1642 = - (source_id__h35514 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1574 ; assign _dfoo1643 = - source_id__h35514 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1507 ; assign _dfoo1644 = - (source_id__h35514 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1576 ; assign _dfoo1645 = - source_id__h35514 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1509 ; assign _dfoo1646 = - (source_id__h35514 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1578 ; assign _dfoo1647 = - source_id__h35514 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1511 ; assign _dfoo1648 = - (source_id__h35514 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1580 ; assign _dfoo1649 = - source_id__h35514 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1513 ; assign _dfoo165 = - source_id__h62134 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo29 ; assign _dfoo1650 = - (source_id__h35514 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1582 ; assign _dfoo1651 = - source_id__h35514 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1515 ; assign _dfoo1652 = - (source_id__h35514 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1584 ; assign _dfoo1653 = - source_id__h35514 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1517 ; assign _dfoo1654 = - (source_id__h35514 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1586 ; assign _dfoo1655 = - source_id__h35514 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1519 ; assign _dfoo1656 = - (source_id__h35514 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1588 ; assign _dfoo1657 = - source_id__h35514 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1521 ; assign _dfoo1658 = - (source_id__h35514 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1590 ; assign _dfoo1659 = - source_id__h35514 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1523 ; assign _dfoo166 = - (source_id__h62134 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo98 ; assign _dfoo1660 = - (source_id__h35514 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1592 ; assign _dfoo1661 = - source_id__h35514 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1525 ; assign _dfoo1662 = - (source_id__h35514 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1594 ; assign _dfoo1663 = - source_id__h35514 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1527 ; assign _dfoo1664 = - (source_id__h35514 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1596 ; assign _dfoo1665 = - source_id__h35514 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1529 ; assign _dfoo1666 = - (source_id__h35514 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1598 ; assign _dfoo1667 = - source_id__h35514 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1531 ; assign _dfoo1668 = - (source_id__h35514 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1600 ; assign _dfoo1669 = - source_id__h35514 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1533 ; assign _dfoo167 = - source_id__h62134 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo31 ; assign _dfoo1670 = - (source_id__h35514 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1602 ; assign _dfoo1671 = - source_id__h35514 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1535 ; assign _dfoo1672 = - (source_id__h35514 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1604 ; assign _dfoo1673 = - source_id__h35514 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1537 ; assign _dfoo1674 = - (source_id__h35514 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1606 ; assign _dfoo1675 = - source_id__h35514 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1539 ; assign _dfoo1676 = - (source_id__h35514 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1608 ; assign _dfoo1677 = - source_id__h35514 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1541 ; assign _dfoo1678 = - (source_id__h35514 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1610 ; assign _dfoo1679 = - source_id__h35514 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1543 ; assign _dfoo168 = - (source_id__h62134 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo100 ; assign _dfoo1680 = - (source_id__h35514 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1612 ; assign _dfoo1681 = - source_id__h35514 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1545 ; assign _dfoo1682 = - (source_id__h35514 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1614 ; assign _dfoo1683 = - source_id__h35514 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1547 ; assign _dfoo1684 = - (source_id__h35514 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1616 ; assign _dfoo1685 = - source_id__h35514 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1549 ; assign _dfoo1686 = - (source_id__h35514 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1618 ; assign _dfoo1687 = - source_id__h35514 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1551 ; assign _dfoo1688 = - (source_id__h35514 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1620 ; assign _dfoo1689 = - source_id__h35514 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1553 ; assign _dfoo169 = - source_id__h62134 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo33 ; assign _dfoo1690 = - (source_id__h35514 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1622 ; assign _dfoo1691 = - source_id__h35514 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1555 ; assign _dfoo1692 = - (source_id__h35514 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1624 ; assign _dfoo1693 = - source_id__h35514 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1557 ; assign _dfoo1694 = - (source_id__h35514 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1626 ; assign _dfoo1695 = - source_id__h35514 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1559 ; assign _dfoo1696 = - (source_id__h35514 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1628 ; assign _dfoo1697 = - source_id__h35514 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1561 ; assign _dfoo1698 = - (source_id__h35514 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1630 ; assign _dfoo1699 = - source_id__h35514 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1563 ; assign _dfoo17 = - source_id__h64554 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo170 = - (source_id__h62134 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo102 ; assign _dfoo1700 = - (source_id__h35514 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1632 ; assign _dfoo1702 = - (source_id__h34304 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1634 ; assign _dfoo1704 = - (source_id__h34304 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1636 ; assign _dfoo1706 = - (source_id__h34304 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1638 ; assign _dfoo1708 = - (source_id__h34304 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1640 ; assign _dfoo171 = - source_id__h62134 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo35 ; assign _dfoo1710 = - (source_id__h34304 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1642 ; assign _dfoo1712 = - (source_id__h34304 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1644 ; assign _dfoo1714 = - (source_id__h34304 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1646 ; assign _dfoo1716 = - (source_id__h34304 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1648 ; assign _dfoo1718 = - (source_id__h34304 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1650 ; assign _dfoo172 = - (source_id__h62134 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo104 ; assign _dfoo1720 = - (source_id__h34304 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1652 ; assign _dfoo1722 = - (source_id__h34304 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1654 ; assign _dfoo1724 = - (source_id__h34304 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1656 ; assign _dfoo1726 = - (source_id__h34304 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1658 ; assign _dfoo1728 = - (source_id__h34304 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1660 ; assign _dfoo173 = - source_id__h62134 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo37 ; assign _dfoo1730 = - (source_id__h34304 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1662 ; assign _dfoo1732 = - (source_id__h34304 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1664 ; assign _dfoo1734 = - (source_id__h34304 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1666 ; assign _dfoo1736 = - (source_id__h34304 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1668 ; assign _dfoo1738 = - (source_id__h34304 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1670 ; assign _dfoo174 = - (source_id__h62134 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo106 ; assign _dfoo1740 = - (source_id__h34304 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1672 ; assign _dfoo1742 = - (source_id__h34304 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1674 ; assign _dfoo1744 = - (source_id__h34304 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1676 ; assign _dfoo1746 = - (source_id__h34304 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1678 ; assign _dfoo1748 = - (source_id__h34304 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1680 ; assign _dfoo175 = - source_id__h62134 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo39 ; assign _dfoo1750 = - (source_id__h34304 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1682 ; assign _dfoo1752 = - (source_id__h34304 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1684 ; assign _dfoo1754 = - (source_id__h34304 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1686 ; assign _dfoo1756 = - (source_id__h34304 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1688 ; assign _dfoo1758 = - (source_id__h34304 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1690 ; assign _dfoo176 = - (source_id__h62134 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo108 ; assign _dfoo1760 = - (source_id__h34304 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1692 ; assign _dfoo1762 = - (source_id__h34304 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1694 ; assign _dfoo1764 = - (source_id__h34304 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1696 ; assign _dfoo1766 = - (source_id__h34304 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1698 ; assign _dfoo1768 = - (source_id__h34304 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1700 ; assign _dfoo1769 = - source_id__h33094 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1633 ; assign _dfoo177 = - source_id__h62134 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo41 ; assign _dfoo1770 = - (source_id__h33094 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1702 ; assign _dfoo1771 = - source_id__h33094 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1635 ; assign _dfoo1772 = - (source_id__h33094 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1704 ; assign _dfoo1773 = - source_id__h33094 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1637 ; assign _dfoo1774 = - (source_id__h33094 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1706 ; assign _dfoo1775 = - source_id__h33094 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1639 ; assign _dfoo1776 = - (source_id__h33094 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1708 ; assign _dfoo1777 = - source_id__h33094 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1641 ; assign _dfoo1778 = - (source_id__h33094 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1710 ; assign _dfoo1779 = - source_id__h33094 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1643 ; assign _dfoo178 = - (source_id__h62134 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo110 ; assign _dfoo1780 = - (source_id__h33094 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1712 ; assign _dfoo1781 = - source_id__h33094 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1645 ; assign _dfoo1782 = - (source_id__h33094 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1714 ; assign _dfoo1783 = - source_id__h33094 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1647 ; assign _dfoo1784 = - (source_id__h33094 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1716 ; assign _dfoo1785 = - source_id__h33094 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1649 ; assign _dfoo1786 = - (source_id__h33094 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1718 ; assign _dfoo1787 = - source_id__h33094 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1651 ; assign _dfoo1788 = - (source_id__h33094 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1720 ; assign _dfoo1789 = - source_id__h33094 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1653 ; assign _dfoo179 = - source_id__h62134 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo43 ; assign _dfoo1790 = - (source_id__h33094 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1722 ; assign _dfoo1791 = - source_id__h33094 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1655 ; assign _dfoo1792 = - (source_id__h33094 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1724 ; assign _dfoo1793 = - source_id__h33094 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1657 ; assign _dfoo1794 = - (source_id__h33094 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1726 ; assign _dfoo1795 = - source_id__h33094 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1659 ; assign _dfoo1796 = - (source_id__h33094 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1728 ; assign _dfoo1797 = - source_id__h33094 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1661 ; assign _dfoo1798 = - (source_id__h33094 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1730 ; assign _dfoo1799 = - source_id__h33094 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1663 ; assign _dfoo18 = - (source_id__h64554 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo180 = - (source_id__h62134 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo112 ; assign _dfoo1800 = - (source_id__h33094 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1732 ; assign _dfoo1801 = - source_id__h33094 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1665 ; assign _dfoo1802 = - (source_id__h33094 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1734 ; assign _dfoo1803 = - source_id__h33094 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1667 ; assign _dfoo1804 = - (source_id__h33094 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1736 ; assign _dfoo1805 = - source_id__h33094 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1669 ; assign _dfoo1806 = - (source_id__h33094 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1738 ; assign _dfoo1807 = - source_id__h33094 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1671 ; assign _dfoo1808 = - (source_id__h33094 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1740 ; assign _dfoo1809 = - source_id__h33094 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1673 ; assign _dfoo181 = - source_id__h62134 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo45 ; assign _dfoo1810 = - (source_id__h33094 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1742 ; assign _dfoo1811 = - source_id__h33094 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1675 ; assign _dfoo1812 = - (source_id__h33094 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1744 ; assign _dfoo1813 = - source_id__h33094 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1677 ; assign _dfoo1814 = - (source_id__h33094 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1746 ; assign _dfoo1815 = - source_id__h33094 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1679 ; assign _dfoo1816 = - (source_id__h33094 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1748 ; assign _dfoo1817 = - source_id__h33094 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1681 ; assign _dfoo1818 = - (source_id__h33094 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1750 ; assign _dfoo1819 = - source_id__h33094 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1683 ; assign _dfoo182 = - (source_id__h62134 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo114 ; assign _dfoo1820 = - (source_id__h33094 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1752 ; assign _dfoo1821 = - source_id__h33094 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1685 ; assign _dfoo1822 = - (source_id__h33094 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1754 ; assign _dfoo1823 = - source_id__h33094 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1687 ; assign _dfoo1824 = - (source_id__h33094 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1756 ; assign _dfoo1825 = - source_id__h33094 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1689 ; assign _dfoo1826 = - (source_id__h33094 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1758 ; assign _dfoo1827 = - source_id__h33094 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1691 ; assign _dfoo1828 = - (source_id__h33094 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1760 ; assign _dfoo1829 = - source_id__h33094 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1693 ; assign _dfoo183 = - source_id__h62134 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo47 ; assign _dfoo1830 = - (source_id__h33094 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1762 ; assign _dfoo1831 = - source_id__h33094 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1695 ; assign _dfoo1832 = - (source_id__h33094 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1764 ; assign _dfoo1833 = - source_id__h33094 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1697 ; assign _dfoo1834 = - (source_id__h33094 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1766 ; assign _dfoo1835 = - source_id__h33094 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1699 ; assign _dfoo1836 = - (source_id__h33094 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1768 ; assign _dfoo1838 = - (source_id__h31884 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1770 ; assign _dfoo184 = - (source_id__h62134 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo116 ; assign _dfoo1840 = - (source_id__h31884 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1772 ; assign _dfoo1842 = - (source_id__h31884 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1774 ; assign _dfoo1844 = - (source_id__h31884 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1776 ; assign _dfoo1846 = - (source_id__h31884 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1778 ; assign _dfoo1848 = - (source_id__h31884 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1780 ; assign _dfoo185 = - source_id__h62134 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo49 ; assign _dfoo1850 = - (source_id__h31884 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1782 ; assign _dfoo1852 = - (source_id__h31884 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1784 ; assign _dfoo1854 = - (source_id__h31884 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1786 ; assign _dfoo1856 = - (source_id__h31884 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1788 ; assign _dfoo1858 = - (source_id__h31884 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1790 ; assign _dfoo186 = - (source_id__h62134 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo118 ; assign _dfoo1860 = - (source_id__h31884 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1792 ; assign _dfoo1862 = - (source_id__h31884 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1794 ; assign _dfoo1864 = - (source_id__h31884 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1796 ; assign _dfoo1866 = - (source_id__h31884 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1798 ; assign _dfoo1868 = - (source_id__h31884 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1800 ; assign _dfoo187 = - source_id__h62134 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo51 ; assign _dfoo1870 = - (source_id__h31884 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1802 ; assign _dfoo1872 = - (source_id__h31884 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1804 ; assign _dfoo1874 = - (source_id__h31884 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1806 ; assign _dfoo1876 = - (source_id__h31884 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1808 ; assign _dfoo1878 = - (source_id__h31884 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1810 ; assign _dfoo188 = - (source_id__h62134 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo120 ; assign _dfoo1880 = - (source_id__h31884 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1812 ; assign _dfoo1882 = - (source_id__h31884 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1814 ; assign _dfoo1884 = - (source_id__h31884 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1816 ; assign _dfoo1886 = - (source_id__h31884 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1818 ; assign _dfoo1888 = - (source_id__h31884 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1820 ; assign _dfoo189 = - source_id__h62134 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo53 ; assign _dfoo1890 = - (source_id__h31884 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1822 ; assign _dfoo1892 = - (source_id__h31884 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1824 ; assign _dfoo1894 = - (source_id__h31884 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1826 ; assign _dfoo1896 = - (source_id__h31884 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1828 ; assign _dfoo1898 = - (source_id__h31884 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1830 ; assign _dfoo19 = - source_id__h64554 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo190 = - (source_id__h62134 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo122 ; assign _dfoo1900 = - (source_id__h31884 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1832 ; assign _dfoo1902 = - (source_id__h31884 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1834 ; assign _dfoo1904 = - (source_id__h31884 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1836 ; assign _dfoo1905 = - source_id__h30674 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1769 ; assign _dfoo1906 = - (source_id__h30674 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1838 ; assign _dfoo1907 = - source_id__h30674 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1771 ; assign _dfoo1908 = - (source_id__h30674 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1840 ; assign _dfoo1909 = - source_id__h30674 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1773 ; assign _dfoo191 = - source_id__h62134 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo55 ; assign _dfoo1910 = - (source_id__h30674 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1842 ; assign _dfoo1911 = - source_id__h30674 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1775 ; assign _dfoo1912 = - (source_id__h30674 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1844 ; assign _dfoo1913 = - source_id__h30674 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1777 ; assign _dfoo1914 = - (source_id__h30674 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1846 ; assign _dfoo1915 = - source_id__h30674 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1779 ; assign _dfoo1916 = - (source_id__h30674 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1848 ; assign _dfoo1917 = - source_id__h30674 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1781 ; assign _dfoo1918 = - (source_id__h30674 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1850 ; assign _dfoo1919 = - source_id__h30674 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1783 ; assign _dfoo192 = - (source_id__h62134 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo124 ; assign _dfoo1920 = - (source_id__h30674 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1852 ; assign _dfoo1921 = - source_id__h30674 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1785 ; assign _dfoo1922 = - (source_id__h30674 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1854 ; assign _dfoo1923 = - source_id__h30674 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1787 ; assign _dfoo1924 = - (source_id__h30674 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1856 ; assign _dfoo1925 = - source_id__h30674 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1789 ; assign _dfoo1926 = - (source_id__h30674 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1858 ; assign _dfoo1927 = - source_id__h30674 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1791 ; assign _dfoo1928 = - (source_id__h30674 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1860 ; assign _dfoo1929 = - source_id__h30674 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1793 ; assign _dfoo193 = - source_id__h62134 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo57 ; assign _dfoo1930 = - (source_id__h30674 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1862 ; assign _dfoo1931 = - source_id__h30674 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1795 ; assign _dfoo1932 = - (source_id__h30674 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1864 ; assign _dfoo1933 = - source_id__h30674 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1797 ; assign _dfoo1934 = - (source_id__h30674 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1866 ; assign _dfoo1935 = - source_id__h30674 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1799 ; assign _dfoo1936 = - (source_id__h30674 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1868 ; assign _dfoo1937 = - source_id__h30674 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1801 ; assign _dfoo1938 = - (source_id__h30674 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1870 ; assign _dfoo1939 = - source_id__h30674 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1803 ; assign _dfoo194 = - (source_id__h62134 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo126 ; assign _dfoo1940 = - (source_id__h30674 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1872 ; assign _dfoo1941 = - source_id__h30674 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1805 ; assign _dfoo1942 = - (source_id__h30674 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1874 ; assign _dfoo1943 = - source_id__h30674 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1807 ; assign _dfoo1944 = - (source_id__h30674 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1876 ; assign _dfoo1945 = - source_id__h30674 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1809 ; assign _dfoo1946 = - (source_id__h30674 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1878 ; assign _dfoo1947 = - source_id__h30674 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1811 ; assign _dfoo1948 = - (source_id__h30674 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1880 ; assign _dfoo1949 = - source_id__h30674 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1813 ; assign _dfoo195 = - source_id__h62134 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo59 ; assign _dfoo1950 = - (source_id__h30674 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1882 ; assign _dfoo1951 = - source_id__h30674 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1815 ; assign _dfoo1952 = - (source_id__h30674 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1884 ; assign _dfoo1953 = - source_id__h30674 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1817 ; assign _dfoo1954 = - (source_id__h30674 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1886 ; assign _dfoo1955 = - source_id__h30674 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1819 ; assign _dfoo1956 = - (source_id__h30674 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1888 ; assign _dfoo1957 = - source_id__h30674 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1821 ; assign _dfoo1958 = - (source_id__h30674 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1890 ; assign _dfoo1959 = - source_id__h30674 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1823 ; assign _dfoo196 = - (source_id__h62134 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo128 ; assign _dfoo1960 = - (source_id__h30674 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1892 ; assign _dfoo1961 = - source_id__h30674 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1825 ; assign _dfoo1962 = - (source_id__h30674 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1894 ; assign _dfoo1963 = - source_id__h30674 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1827 ; assign _dfoo1964 = - (source_id__h30674 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1896 ; assign _dfoo1965 = - source_id__h30674 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1829 ; assign _dfoo1966 = - (source_id__h30674 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1898 ; assign _dfoo1967 = - source_id__h30674 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1831 ; assign _dfoo1968 = - (source_id__h30674 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1900 ; assign _dfoo1969 = - source_id__h30674 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1833 ; assign _dfoo197 = - source_id__h62134 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo61 ; assign _dfoo1970 = - (source_id__h30674 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1902 ; assign _dfoo1971 = - source_id__h30674 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1835 ; assign _dfoo1972 = - (source_id__h30674 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1904 ; assign _dfoo1974 = - (source_id__h29464 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1906 ; assign _dfoo1976 = - (source_id__h29464 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1908 ; assign _dfoo1978 = - (source_id__h29464 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1910 ; assign _dfoo198 = - (source_id__h62134 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo130 ; assign _dfoo1980 = - (source_id__h29464 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1912 ; assign _dfoo1982 = - (source_id__h29464 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1914 ; assign _dfoo1984 = - (source_id__h29464 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1916 ; assign _dfoo1986 = - (source_id__h29464 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1918 ; assign _dfoo1988 = - (source_id__h29464 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1920 ; assign _dfoo199 = - source_id__h62134 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo63 ; assign _dfoo1990 = - (source_id__h29464 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1922 ; assign _dfoo1992 = - (source_id__h29464 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1924 ; assign _dfoo1994 = - (source_id__h29464 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1926 ; assign _dfoo1996 = - (source_id__h29464 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1928 ; assign _dfoo1998 = - (source_id__h29464 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1930 ; assign _dfoo2 = - (source_id__h64554 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo20 = - (source_id__h64554 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo200 = - (source_id__h62134 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo132 ; assign _dfoo2000 = - (source_id__h29464 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1932 ; assign _dfoo2002 = - (source_id__h29464 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1934 ; assign _dfoo2004 = - (source_id__h29464 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1936 ; assign _dfoo2006 = - (source_id__h29464 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1938 ; assign _dfoo2008 = - (source_id__h29464 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1940 ; assign _dfoo201 = - source_id__h62134 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo65 ; assign _dfoo2010 = - (source_id__h29464 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1942 ; assign _dfoo2012 = - (source_id__h29464 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1944 ; assign _dfoo2014 = - (source_id__h29464 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1946 ; assign _dfoo2016 = - (source_id__h29464 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1948 ; assign _dfoo2018 = - (source_id__h29464 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1950 ; assign _dfoo202 = - (source_id__h62134 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo134 ; assign _dfoo2020 = - (source_id__h29464 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1952 ; assign _dfoo2022 = - (source_id__h29464 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1954 ; assign _dfoo2024 = - (source_id__h29464 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1956 ; assign _dfoo2026 = - (source_id__h29464 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1958 ; assign _dfoo2028 = - (source_id__h29464 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1960 ; assign _dfoo203 = - source_id__h62134 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo67 ; assign _dfoo2030 = - (source_id__h29464 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1962 ; assign _dfoo2032 = - (source_id__h29464 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1964 ; assign _dfoo2034 = - (source_id__h29464 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1966 ; assign _dfoo2036 = - (source_id__h29464 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1968 ; assign _dfoo2038 = - (source_id__h29464 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1970 ; assign _dfoo204 = - (source_id__h62134 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo136 ; assign _dfoo2040 = - (source_id__h29464 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1972 ; assign _dfoo2041 = - source_id_base__h28137 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd16 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1905 ; assign _dfoo2043 = - source_id_base__h28137 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd15 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1907 ; assign _dfoo2045 = - source_id_base__h28137 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd14 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1909 ; assign _dfoo2047 = - source_id_base__h28137 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd13 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1911 ; assign _dfoo2049 = - source_id_base__h28137 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd12 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1913 ; assign _dfoo2051 = - source_id_base__h28137 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd11 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1915 ; assign _dfoo2053 = - source_id_base__h28137 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd10 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1917 ; assign _dfoo2055 = - source_id_base__h28137 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd9 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1919 ; assign _dfoo2057 = - source_id_base__h28137 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd8 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1921 ; assign _dfoo2059 = - source_id_base__h28137 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd7 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1923 ; assign _dfoo206 = - (source_id__h60924 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo138 ; assign _dfoo2061 = - source_id_base__h28137 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd6 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1925 ; assign _dfoo2063 = - source_id_base__h28137 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd5 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1927 ; assign _dfoo2065 = - source_id_base__h28137 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd4 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1929 ; assign _dfoo2067 = - source_id_base__h28137 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd3 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1931 ; assign _dfoo2069 = - source_id_base__h28137 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd2 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1933 ; assign _dfoo2071 = - source_id_base__h28137 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd1 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1935 ; assign _dfoo2073 = - source_id_base__h28137 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1937 ; assign _dfoo2075 = - source_id_base__h28137 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd16 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1939 ; assign _dfoo2077 = - source_id_base__h28137 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd15 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1941 ; assign _dfoo2079 = - source_id_base__h28137 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd14 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1943 ; assign _dfoo208 = - (source_id__h60924 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo140 ; assign _dfoo2081 = - source_id_base__h28137 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd13 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1945 ; assign _dfoo2083 = - source_id_base__h28137 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd12 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1947 ; assign _dfoo2085 = - source_id_base__h28137 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd11 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1949 ; assign _dfoo2087 = - source_id_base__h28137 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd10 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1951 ; assign _dfoo2089 = - source_id_base__h28137 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd9 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1953 ; assign _dfoo2091 = - source_id_base__h28137 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd8 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1955 ; assign _dfoo2093 = - source_id_base__h28137 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd7 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1957 ; assign _dfoo2095 = - source_id_base__h28137 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd6 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1959 ; assign _dfoo2097 = - source_id_base__h28137 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd5 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1961 ; assign _dfoo2099 = - source_id_base__h28137 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd4 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1963 ; assign _dfoo21 = - source_id__h64554 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo210 = - (source_id__h60924 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo142 ; assign _dfoo2101 = - source_id_base__h28137 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd3 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1965 ; assign _dfoo2103 = - source_id_base__h28137 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd2 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1967 ; assign _dfoo2105 = - source_id_base__h28137 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd1 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1969 ; assign _dfoo2107 = - source_id_base__h28137 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1971 ; assign _dfoo212 = - (source_id__h60924 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo144 ; assign _dfoo214 = - (source_id__h60924 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo146 ; assign _dfoo216 = - (source_id__h60924 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo148 ; assign _dfoo218 = - (source_id__h60924 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo150 ; assign _dfoo22 = - (source_id__h64554 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo220 = - (source_id__h60924 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo152 ; assign _dfoo222 = - (source_id__h60924 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo154 ; assign _dfoo224 = - (source_id__h60924 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo156 ; assign _dfoo226 = - (source_id__h60924 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo158 ; assign _dfoo228 = - (source_id__h60924 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo160 ; assign _dfoo23 = - source_id__h64554 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo230 = - (source_id__h60924 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo162 ; assign _dfoo232 = - (source_id__h60924 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo164 ; assign _dfoo234 = - (source_id__h60924 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo166 ; assign _dfoo236 = - (source_id__h60924 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo168 ; assign _dfoo238 = - (source_id__h60924 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo170 ; assign _dfoo24 = - (source_id__h64554 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo240 = - (source_id__h60924 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo172 ; assign _dfoo242 = - (source_id__h60924 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo174 ; assign _dfoo244 = - (source_id__h60924 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo176 ; assign _dfoo246 = - (source_id__h60924 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo178 ; assign _dfoo248 = - (source_id__h60924 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo180 ; assign _dfoo25 = - source_id__h64554 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo250 = - (source_id__h60924 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo182 ; assign _dfoo252 = - (source_id__h60924 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo184 ; assign _dfoo254 = - (source_id__h60924 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo186 ; assign _dfoo256 = - (source_id__h60924 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo188 ; assign _dfoo258 = - (source_id__h60924 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo190 ; assign _dfoo26 = - (source_id__h64554 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo260 = - (source_id__h60924 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo192 ; assign _dfoo262 = - (source_id__h60924 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo194 ; assign _dfoo264 = - (source_id__h60924 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo196 ; assign _dfoo266 = - (source_id__h60924 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo198 ; assign _dfoo268 = - (source_id__h60924 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo200 ; assign _dfoo27 = - source_id__h64554 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo270 = - (source_id__h60924 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo202 ; assign _dfoo272 = - (source_id__h60924 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo204 ; assign _dfoo273 = - source_id__h59714 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo137 ; assign _dfoo274 = - (source_id__h59714 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo206 ; assign _dfoo275 = - source_id__h59714 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo139 ; assign _dfoo276 = - (source_id__h59714 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo208 ; assign _dfoo277 = - source_id__h59714 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo141 ; assign _dfoo278 = - (source_id__h59714 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo210 ; assign _dfoo279 = - source_id__h59714 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo143 ; assign _dfoo28 = - (source_id__h64554 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo280 = - (source_id__h59714 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo212 ; assign _dfoo281 = - source_id__h59714 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo145 ; assign _dfoo282 = - (source_id__h59714 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo214 ; assign _dfoo283 = - source_id__h59714 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo147 ; assign _dfoo284 = - (source_id__h59714 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo216 ; assign _dfoo285 = - source_id__h59714 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo149 ; assign _dfoo286 = - (source_id__h59714 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo218 ; assign _dfoo287 = - source_id__h59714 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo151 ; assign _dfoo288 = - (source_id__h59714 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo220 ; assign _dfoo289 = - source_id__h59714 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo153 ; assign _dfoo29 = - source_id__h64554 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo290 = - (source_id__h59714 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo222 ; assign _dfoo291 = - source_id__h59714 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo155 ; assign _dfoo292 = - (source_id__h59714 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo224 ; assign _dfoo293 = - source_id__h59714 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo157 ; assign _dfoo294 = - (source_id__h59714 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo226 ; assign _dfoo295 = - source_id__h59714 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo159 ; assign _dfoo296 = - (source_id__h59714 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo228 ; assign _dfoo297 = - source_id__h59714 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo161 ; assign _dfoo298 = - (source_id__h59714 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo230 ; assign _dfoo299 = - source_id__h59714 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo163 ; assign _dfoo3 = - source_id__h64554 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo30 = - (source_id__h64554 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo300 = - (source_id__h59714 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo232 ; assign _dfoo301 = - source_id__h59714 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo165 ; assign _dfoo302 = - (source_id__h59714 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo234 ; assign _dfoo303 = - source_id__h59714 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo167 ; assign _dfoo304 = - (source_id__h59714 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo236 ; assign _dfoo305 = - source_id__h59714 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo169 ; assign _dfoo306 = - (source_id__h59714 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo238 ; assign _dfoo307 = - source_id__h59714 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo171 ; assign _dfoo308 = - (source_id__h59714 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo240 ; assign _dfoo309 = - source_id__h59714 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo173 ; assign _dfoo31 = - source_id__h64554 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo310 = - (source_id__h59714 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo242 ; assign _dfoo311 = - source_id__h59714 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo175 ; assign _dfoo312 = - (source_id__h59714 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo244 ; assign _dfoo313 = - source_id__h59714 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo177 ; assign _dfoo314 = - (source_id__h59714 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo246 ; assign _dfoo315 = - source_id__h59714 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo179 ; assign _dfoo316 = - (source_id__h59714 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo248 ; assign _dfoo317 = - source_id__h59714 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo181 ; assign _dfoo318 = - (source_id__h59714 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo250 ; assign _dfoo319 = - source_id__h59714 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo183 ; assign _dfoo32 = - (source_id__h64554 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo320 = - (source_id__h59714 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo252 ; assign _dfoo321 = - source_id__h59714 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo185 ; assign _dfoo322 = - (source_id__h59714 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo254 ; assign _dfoo323 = - source_id__h59714 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo187 ; assign _dfoo324 = - (source_id__h59714 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo256 ; assign _dfoo325 = - source_id__h59714 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo189 ; assign _dfoo326 = - (source_id__h59714 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo258 ; assign _dfoo327 = - source_id__h59714 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo191 ; assign _dfoo328 = - (source_id__h59714 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo260 ; assign _dfoo329 = - source_id__h59714 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo193 ; assign _dfoo33 = - source_id__h64554 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo330 = - (source_id__h59714 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo262 ; assign _dfoo331 = - source_id__h59714 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo195 ; assign _dfoo332 = - (source_id__h59714 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo264 ; assign _dfoo333 = - source_id__h59714 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo197 ; assign _dfoo334 = - (source_id__h59714 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo266 ; assign _dfoo335 = - source_id__h59714 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo199 ; assign _dfoo336 = - (source_id__h59714 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo268 ; assign _dfoo337 = - source_id__h59714 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo201 ; assign _dfoo338 = - (source_id__h59714 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo270 ; assign _dfoo339 = - source_id__h59714 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo203 ; assign _dfoo34 = - (source_id__h64554 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo340 = - (source_id__h59714 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo272 ; assign _dfoo342 = - (source_id__h58504 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo274 ; assign _dfoo344 = - (source_id__h58504 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo276 ; assign _dfoo346 = - (source_id__h58504 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo278 ; assign _dfoo348 = - (source_id__h58504 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo280 ; assign _dfoo35 = - source_id__h64554 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo350 = - (source_id__h58504 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo282 ; assign _dfoo352 = - (source_id__h58504 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo284 ; assign _dfoo354 = - (source_id__h58504 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo286 ; assign _dfoo356 = - (source_id__h58504 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo288 ; assign _dfoo358 = - (source_id__h58504 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo290 ; assign _dfoo36 = - (source_id__h64554 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo360 = - (source_id__h58504 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo292 ; assign _dfoo362 = - (source_id__h58504 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo294 ; assign _dfoo364 = - (source_id__h58504 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo296 ; assign _dfoo366 = - (source_id__h58504 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo298 ; assign _dfoo368 = - (source_id__h58504 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo300 ; assign _dfoo37 = - source_id__h64554 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo370 = - (source_id__h58504 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo302 ; assign _dfoo372 = - (source_id__h58504 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo304 ; assign _dfoo374 = - (source_id__h58504 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo306 ; assign _dfoo376 = - (source_id__h58504 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo308 ; assign _dfoo378 = - (source_id__h58504 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo310 ; assign _dfoo38 = - (source_id__h64554 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo380 = - (source_id__h58504 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo312 ; assign _dfoo382 = - (source_id__h58504 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo314 ; assign _dfoo384 = - (source_id__h58504 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo316 ; assign _dfoo386 = - (source_id__h58504 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo318 ; assign _dfoo388 = - (source_id__h58504 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo320 ; assign _dfoo39 = - source_id__h64554 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo390 = - (source_id__h58504 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo322 ; assign _dfoo392 = - (source_id__h58504 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo324 ; assign _dfoo394 = - (source_id__h58504 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo326 ; assign _dfoo396 = - (source_id__h58504 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo328 ; assign _dfoo398 = - (source_id__h58504 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo330 ; assign _dfoo4 = - (source_id__h64554 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo40 = - (source_id__h64554 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo400 = - (source_id__h58504 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo332 ; assign _dfoo402 = - (source_id__h58504 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo334 ; assign _dfoo404 = - (source_id__h58504 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo336 ; assign _dfoo406 = - (source_id__h58504 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo338 ; assign _dfoo408 = - (source_id__h58504 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo340 ; assign _dfoo409 = - source_id__h57294 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo273 ; assign _dfoo41 = - source_id__h64554 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo410 = - (source_id__h57294 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo342 ; assign _dfoo411 = - source_id__h57294 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo275 ; assign _dfoo412 = - (source_id__h57294 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo344 ; assign _dfoo413 = - source_id__h57294 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo277 ; assign _dfoo414 = - (source_id__h57294 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo346 ; assign _dfoo415 = - source_id__h57294 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo279 ; assign _dfoo416 = - (source_id__h57294 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo348 ; assign _dfoo417 = - source_id__h57294 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo281 ; assign _dfoo418 = - (source_id__h57294 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo350 ; assign _dfoo419 = - source_id__h57294 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo283 ; assign _dfoo42 = - (source_id__h64554 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo420 = - (source_id__h57294 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo352 ; assign _dfoo421 = - source_id__h57294 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo285 ; assign _dfoo422 = - (source_id__h57294 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo354 ; assign _dfoo423 = - source_id__h57294 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo287 ; assign _dfoo424 = - (source_id__h57294 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo356 ; assign _dfoo425 = - source_id__h57294 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo289 ; assign _dfoo426 = - (source_id__h57294 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo358 ; assign _dfoo427 = - source_id__h57294 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo291 ; assign _dfoo428 = - (source_id__h57294 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo360 ; assign _dfoo429 = - source_id__h57294 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo293 ; assign _dfoo43 = - source_id__h64554 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo430 = - (source_id__h57294 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo362 ; assign _dfoo431 = - source_id__h57294 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo295 ; assign _dfoo432 = - (source_id__h57294 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo364 ; assign _dfoo433 = - source_id__h57294 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo297 ; assign _dfoo434 = - (source_id__h57294 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo366 ; assign _dfoo435 = - source_id__h57294 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo299 ; assign _dfoo436 = - (source_id__h57294 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo368 ; assign _dfoo437 = - source_id__h57294 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo301 ; assign _dfoo438 = - (source_id__h57294 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo370 ; assign _dfoo439 = - source_id__h57294 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo303 ; assign _dfoo44 = - (source_id__h64554 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo440 = - (source_id__h57294 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo372 ; assign _dfoo441 = - source_id__h57294 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo305 ; assign _dfoo442 = - (source_id__h57294 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo374 ; assign _dfoo443 = - source_id__h57294 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo307 ; assign _dfoo444 = - (source_id__h57294 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo376 ; assign _dfoo445 = - source_id__h57294 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo309 ; assign _dfoo446 = - (source_id__h57294 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo378 ; assign _dfoo447 = - source_id__h57294 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo311 ; assign _dfoo448 = - (source_id__h57294 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo380 ; assign _dfoo449 = - source_id__h57294 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo313 ; assign _dfoo45 = - source_id__h64554 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo450 = - (source_id__h57294 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo382 ; assign _dfoo451 = - source_id__h57294 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo315 ; assign _dfoo452 = - (source_id__h57294 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo384 ; assign _dfoo453 = - source_id__h57294 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo317 ; assign _dfoo454 = - (source_id__h57294 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo386 ; assign _dfoo455 = - source_id__h57294 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo319 ; assign _dfoo456 = - (source_id__h57294 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo388 ; assign _dfoo457 = - source_id__h57294 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo321 ; assign _dfoo458 = - (source_id__h57294 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo390 ; assign _dfoo459 = - source_id__h57294 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo323 ; assign _dfoo46 = - (source_id__h64554 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo460 = - (source_id__h57294 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo392 ; assign _dfoo461 = - source_id__h57294 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo325 ; assign _dfoo462 = - (source_id__h57294 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo394 ; assign _dfoo463 = - source_id__h57294 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo327 ; assign _dfoo464 = - (source_id__h57294 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo396 ; assign _dfoo465 = - source_id__h57294 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo329 ; assign _dfoo466 = - (source_id__h57294 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo398 ; assign _dfoo467 = - source_id__h57294 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo331 ; assign _dfoo468 = - (source_id__h57294 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo400 ; assign _dfoo469 = - source_id__h57294 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo333 ; assign _dfoo47 = - source_id__h64554 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo470 = - (source_id__h57294 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo402 ; assign _dfoo471 = - source_id__h57294 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo335 ; assign _dfoo472 = - (source_id__h57294 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo404 ; assign _dfoo473 = - source_id__h57294 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo337 ; assign _dfoo474 = - (source_id__h57294 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo406 ; assign _dfoo475 = - source_id__h57294 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo339 ; assign _dfoo476 = - (source_id__h57294 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo408 ; assign _dfoo478 = - (source_id__h56084 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo410 ; assign _dfoo48 = - (source_id__h64554 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo480 = - (source_id__h56084 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo412 ; assign _dfoo482 = - (source_id__h56084 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo414 ; assign _dfoo484 = - (source_id__h56084 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo416 ; assign _dfoo486 = - (source_id__h56084 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo418 ; assign _dfoo488 = - (source_id__h56084 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo420 ; assign _dfoo49 = - source_id__h64554 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo490 = - (source_id__h56084 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo422 ; assign _dfoo492 = - (source_id__h56084 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo424 ; assign _dfoo494 = - (source_id__h56084 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo426 ; assign _dfoo496 = - (source_id__h56084 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo428 ; assign _dfoo498 = - (source_id__h56084 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo430 ; assign _dfoo5 = - source_id__h64554 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo50 = - (source_id__h64554 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo500 = - (source_id__h56084 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo432 ; assign _dfoo502 = - (source_id__h56084 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo434 ; assign _dfoo504 = - (source_id__h56084 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo436 ; assign _dfoo506 = - (source_id__h56084 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo438 ; assign _dfoo508 = - (source_id__h56084 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo440 ; assign _dfoo51 = - source_id__h64554 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo510 = - (source_id__h56084 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo442 ; assign _dfoo512 = - (source_id__h56084 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo444 ; assign _dfoo514 = - (source_id__h56084 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo446 ; assign _dfoo516 = - (source_id__h56084 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo448 ; assign _dfoo518 = - (source_id__h56084 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo450 ; assign _dfoo52 = - (source_id__h64554 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo520 = - (source_id__h56084 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo452 ; assign _dfoo522 = - (source_id__h56084 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo454 ; assign _dfoo524 = - (source_id__h56084 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo456 ; assign _dfoo526 = - (source_id__h56084 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo458 ; assign _dfoo528 = - (source_id__h56084 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo460 ; assign _dfoo53 = - source_id__h64554 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo530 = - (source_id__h56084 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo462 ; assign _dfoo532 = - (source_id__h56084 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo464 ; assign _dfoo534 = - (source_id__h56084 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo466 ; assign _dfoo536 = - (source_id__h56084 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo468 ; assign _dfoo538 = - (source_id__h56084 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo470 ; assign _dfoo54 = - (source_id__h64554 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo540 = - (source_id__h56084 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo472 ; assign _dfoo542 = - (source_id__h56084 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo474 ; assign _dfoo544 = - (source_id__h56084 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo476 ; assign _dfoo545 = - source_id__h54874 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo409 ; assign _dfoo546 = - (source_id__h54874 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo478 ; assign _dfoo547 = - source_id__h54874 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo411 ; assign _dfoo548 = - (source_id__h54874 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo480 ; assign _dfoo549 = - source_id__h54874 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo413 ; assign _dfoo55 = - source_id__h64554 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo550 = - (source_id__h54874 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo482 ; assign _dfoo551 = - source_id__h54874 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo415 ; assign _dfoo552 = - (source_id__h54874 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo484 ; assign _dfoo553 = - source_id__h54874 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo417 ; assign _dfoo554 = - (source_id__h54874 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo486 ; assign _dfoo555 = - source_id__h54874 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo419 ; assign _dfoo556 = - (source_id__h54874 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo488 ; assign _dfoo557 = - source_id__h54874 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo421 ; assign _dfoo558 = - (source_id__h54874 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo490 ; assign _dfoo559 = - source_id__h54874 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo423 ; assign _dfoo56 = - (source_id__h64554 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo560 = - (source_id__h54874 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo492 ; assign _dfoo561 = - source_id__h54874 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo425 ; assign _dfoo562 = - (source_id__h54874 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo494 ; assign _dfoo563 = - source_id__h54874 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo427 ; assign _dfoo564 = - (source_id__h54874 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo496 ; assign _dfoo565 = - source_id__h54874 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo429 ; assign _dfoo566 = - (source_id__h54874 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo498 ; assign _dfoo567 = - source_id__h54874 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo431 ; assign _dfoo568 = - (source_id__h54874 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo500 ; assign _dfoo569 = - source_id__h54874 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo433 ; assign _dfoo57 = - source_id__h64554 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo570 = - (source_id__h54874 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo502 ; assign _dfoo571 = - source_id__h54874 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo435 ; assign _dfoo572 = - (source_id__h54874 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo504 ; assign _dfoo573 = - source_id__h54874 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo437 ; assign _dfoo574 = - (source_id__h54874 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo506 ; assign _dfoo575 = - source_id__h54874 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo439 ; assign _dfoo576 = - (source_id__h54874 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo508 ; assign _dfoo577 = - source_id__h54874 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo441 ; assign _dfoo578 = - (source_id__h54874 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo510 ; assign _dfoo579 = - source_id__h54874 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo443 ; assign _dfoo58 = - (source_id__h64554 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo580 = - (source_id__h54874 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo512 ; assign _dfoo581 = - source_id__h54874 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo445 ; assign _dfoo582 = - (source_id__h54874 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo514 ; assign _dfoo583 = - source_id__h54874 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo447 ; assign _dfoo584 = - (source_id__h54874 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo516 ; assign _dfoo585 = - source_id__h54874 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo449 ; assign _dfoo586 = - (source_id__h54874 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo518 ; assign _dfoo587 = - source_id__h54874 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo451 ; assign _dfoo588 = - (source_id__h54874 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo520 ; assign _dfoo589 = - source_id__h54874 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo453 ; assign _dfoo59 = - source_id__h64554 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo590 = - (source_id__h54874 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo522 ; assign _dfoo591 = - source_id__h54874 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo455 ; assign _dfoo592 = - (source_id__h54874 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo524 ; assign _dfoo593 = - source_id__h54874 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo457 ; assign _dfoo594 = - (source_id__h54874 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo526 ; assign _dfoo595 = - source_id__h54874 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo459 ; assign _dfoo596 = - (source_id__h54874 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo528 ; assign _dfoo597 = - source_id__h54874 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo461 ; assign _dfoo598 = - (source_id__h54874 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo530 ; assign _dfoo599 = - source_id__h54874 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo463 ; assign _dfoo6 = - (source_id__h64554 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo60 = - (source_id__h64554 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo600 = - (source_id__h54874 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo532 ; assign _dfoo601 = - source_id__h54874 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo465 ; assign _dfoo602 = - (source_id__h54874 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo534 ; assign _dfoo603 = - source_id__h54874 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo467 ; assign _dfoo604 = - (source_id__h54874 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo536 ; assign _dfoo605 = - source_id__h54874 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo469 ; assign _dfoo606 = - (source_id__h54874 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo538 ; assign _dfoo607 = - source_id__h54874 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo471 ; assign _dfoo608 = - (source_id__h54874 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo540 ; assign _dfoo609 = - source_id__h54874 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo473 ; assign _dfoo61 = - source_id__h64554 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo610 = - (source_id__h54874 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo542 ; assign _dfoo611 = - source_id__h54874 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo475 ; assign _dfoo612 = - (source_id__h54874 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo544 ; assign _dfoo614 = - (source_id__h53664 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo546 ; assign _dfoo616 = - (source_id__h53664 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo548 ; assign _dfoo618 = - (source_id__h53664 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo550 ; assign _dfoo62 = - (source_id__h64554 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo620 = - (source_id__h53664 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo552 ; assign _dfoo622 = - (source_id__h53664 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo554 ; assign _dfoo624 = - (source_id__h53664 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo556 ; assign _dfoo626 = - (source_id__h53664 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo558 ; assign _dfoo628 = - (source_id__h53664 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo560 ; assign _dfoo63 = - source_id__h64554 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo630 = - (source_id__h53664 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo562 ; assign _dfoo632 = - (source_id__h53664 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo564 ; assign _dfoo634 = - (source_id__h53664 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo566 ; assign _dfoo636 = - (source_id__h53664 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo568 ; assign _dfoo638 = - (source_id__h53664 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo570 ; assign _dfoo64 = - (source_id__h64554 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo640 = - (source_id__h53664 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo572 ; assign _dfoo642 = - (source_id__h53664 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo574 ; assign _dfoo644 = - (source_id__h53664 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo576 ; assign _dfoo646 = - (source_id__h53664 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo578 ; assign _dfoo648 = - (source_id__h53664 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo580 ; assign _dfoo65 = - source_id__h64554 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo650 = - (source_id__h53664 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo582 ; assign _dfoo652 = - (source_id__h53664 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo584 ; assign _dfoo654 = - (source_id__h53664 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo586 ; assign _dfoo656 = - (source_id__h53664 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo588 ; assign _dfoo658 = - (source_id__h53664 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo590 ; assign _dfoo66 = - (source_id__h64554 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo660 = - (source_id__h53664 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo592 ; assign _dfoo662 = - (source_id__h53664 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo594 ; assign _dfoo664 = - (source_id__h53664 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo596 ; assign _dfoo666 = - (source_id__h53664 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo598 ; assign _dfoo668 = - (source_id__h53664 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo600 ; assign _dfoo67 = - source_id__h64554 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo670 = - (source_id__h53664 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo602 ; assign _dfoo672 = - (source_id__h53664 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo604 ; assign _dfoo674 = - (source_id__h53664 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo606 ; assign _dfoo676 = - (source_id__h53664 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo608 ; assign _dfoo678 = - (source_id__h53664 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo610 ; assign _dfoo68 = - (source_id__h64554 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo680 = - (source_id__h53664 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo612 ; assign _dfoo681 = - source_id__h52454 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo545 ; assign _dfoo682 = - (source_id__h52454 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo614 ; assign _dfoo683 = - source_id__h52454 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo547 ; assign _dfoo684 = - (source_id__h52454 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo616 ; assign _dfoo685 = - source_id__h52454 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo549 ; assign _dfoo686 = - (source_id__h52454 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo618 ; assign _dfoo687 = - source_id__h52454 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo551 ; assign _dfoo688 = - (source_id__h52454 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo620 ; assign _dfoo689 = - source_id__h52454 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo553 ; assign _dfoo690 = - (source_id__h52454 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo622 ; assign _dfoo691 = - source_id__h52454 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo555 ; assign _dfoo692 = - (source_id__h52454 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo624 ; assign _dfoo693 = - source_id__h52454 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo557 ; assign _dfoo694 = - (source_id__h52454 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo626 ; assign _dfoo695 = - source_id__h52454 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo559 ; assign _dfoo696 = - (source_id__h52454 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo628 ; assign _dfoo697 = - source_id__h52454 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo561 ; assign _dfoo698 = - (source_id__h52454 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo630 ; assign _dfoo699 = - source_id__h52454 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo563 ; assign _dfoo7 = - source_id__h64554 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo70 = - (source_id__h63344 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo2 ; assign _dfoo700 = - (source_id__h52454 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo632 ; assign _dfoo701 = - source_id__h52454 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo565 ; assign _dfoo702 = - (source_id__h52454 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo634 ; assign _dfoo703 = - source_id__h52454 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo567 ; assign _dfoo704 = - (source_id__h52454 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo636 ; assign _dfoo705 = - source_id__h52454 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo569 ; assign _dfoo706 = - (source_id__h52454 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo638 ; assign _dfoo707 = - source_id__h52454 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo571 ; assign _dfoo708 = - (source_id__h52454 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo640 ; assign _dfoo709 = - source_id__h52454 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo573 ; assign _dfoo710 = - (source_id__h52454 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo642 ; assign _dfoo711 = - source_id__h52454 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo575 ; assign _dfoo712 = - (source_id__h52454 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo644 ; assign _dfoo713 = - source_id__h52454 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo577 ; assign _dfoo714 = - (source_id__h52454 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo646 ; assign _dfoo715 = - source_id__h52454 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo579 ; assign _dfoo716 = - (source_id__h52454 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo648 ; assign _dfoo717 = - source_id__h52454 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo581 ; assign _dfoo718 = - (source_id__h52454 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo650 ; assign _dfoo719 = - source_id__h52454 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo583 ; assign _dfoo72 = - (source_id__h63344 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo4 ; assign _dfoo720 = - (source_id__h52454 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo652 ; assign _dfoo721 = - source_id__h52454 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo585 ; assign _dfoo722 = - (source_id__h52454 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo654 ; assign _dfoo723 = - source_id__h52454 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo587 ; assign _dfoo724 = - (source_id__h52454 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo656 ; assign _dfoo725 = - source_id__h52454 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo589 ; assign _dfoo726 = - (source_id__h52454 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo658 ; assign _dfoo727 = - source_id__h52454 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo591 ; assign _dfoo728 = - (source_id__h52454 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo660 ; assign _dfoo729 = - source_id__h52454 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo593 ; assign _dfoo730 = - (source_id__h52454 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo662 ; assign _dfoo731 = - source_id__h52454 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo595 ; assign _dfoo732 = - (source_id__h52454 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo664 ; assign _dfoo733 = - source_id__h52454 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo597 ; assign _dfoo734 = - (source_id__h52454 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo666 ; assign _dfoo735 = - source_id__h52454 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo599 ; assign _dfoo736 = - (source_id__h52454 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo668 ; assign _dfoo737 = - source_id__h52454 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo601 ; assign _dfoo738 = - (source_id__h52454 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo670 ; assign _dfoo739 = - source_id__h52454 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo603 ; assign _dfoo74 = - (source_id__h63344 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo6 ; assign _dfoo740 = - (source_id__h52454 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo672 ; assign _dfoo741 = - source_id__h52454 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo605 ; assign _dfoo742 = - (source_id__h52454 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo674 ; assign _dfoo743 = - source_id__h52454 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo607 ; assign _dfoo744 = - (source_id__h52454 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo676 ; assign _dfoo745 = - source_id__h52454 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo609 ; assign _dfoo746 = - (source_id__h52454 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo678 ; assign _dfoo747 = - source_id__h52454 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo611 ; assign _dfoo748 = - (source_id__h52454 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo680 ; assign _dfoo750 = - (source_id__h51244 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo682 ; assign _dfoo752 = - (source_id__h51244 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo684 ; assign _dfoo754 = - (source_id__h51244 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo686 ; assign _dfoo756 = - (source_id__h51244 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo688 ; assign _dfoo758 = - (source_id__h51244 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo690 ; assign _dfoo76 = - (source_id__h63344 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo8 ; assign _dfoo760 = - (source_id__h51244 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo692 ; assign _dfoo762 = - (source_id__h51244 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo694 ; assign _dfoo764 = - (source_id__h51244 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo696 ; assign _dfoo766 = - (source_id__h51244 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo698 ; assign _dfoo768 = - (source_id__h51244 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo700 ; assign _dfoo770 = - (source_id__h51244 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo702 ; assign _dfoo772 = - (source_id__h51244 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo704 ; assign _dfoo774 = - (source_id__h51244 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo706 ; assign _dfoo776 = - (source_id__h51244 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo708 ; assign _dfoo778 = - (source_id__h51244 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo710 ; assign _dfoo78 = - (source_id__h63344 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo10 ; assign _dfoo780 = - (source_id__h51244 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo712 ; assign _dfoo782 = - (source_id__h51244 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo714 ; assign _dfoo784 = - (source_id__h51244 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo716 ; assign _dfoo786 = - (source_id__h51244 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo718 ; assign _dfoo788 = - (source_id__h51244 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo720 ; assign _dfoo790 = - (source_id__h51244 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo722 ; assign _dfoo792 = - (source_id__h51244 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo724 ; assign _dfoo794 = - (source_id__h51244 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo726 ; assign _dfoo796 = - (source_id__h51244 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo728 ; assign _dfoo798 = - (source_id__h51244 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo730 ; assign _dfoo8 = - (source_id__h64554 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo80 = - (source_id__h63344 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo12 ; assign _dfoo800 = - (source_id__h51244 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo732 ; assign _dfoo802 = - (source_id__h51244 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo734 ; assign _dfoo804 = - (source_id__h51244 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo736 ; assign _dfoo806 = - (source_id__h51244 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo738 ; assign _dfoo808 = - (source_id__h51244 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo740 ; assign _dfoo810 = - (source_id__h51244 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo742 ; assign _dfoo812 = - (source_id__h51244 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo744 ; assign _dfoo814 = - (source_id__h51244 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo746 ; assign _dfoo816 = - (source_id__h51244 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo748 ; assign _dfoo817 = - source_id__h50034 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo681 ; assign _dfoo818 = - (source_id__h50034 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo750 ; assign _dfoo819 = - source_id__h50034 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo683 ; assign _dfoo82 = - (source_id__h63344 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo14 ; assign _dfoo820 = - (source_id__h50034 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo752 ; assign _dfoo821 = - source_id__h50034 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo685 ; assign _dfoo822 = - (source_id__h50034 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo754 ; assign _dfoo823 = - source_id__h50034 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo687 ; assign _dfoo824 = - (source_id__h50034 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo756 ; assign _dfoo825 = - source_id__h50034 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo689 ; assign _dfoo826 = - (source_id__h50034 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo758 ; assign _dfoo827 = - source_id__h50034 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo691 ; assign _dfoo828 = - (source_id__h50034 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo760 ; assign _dfoo829 = - source_id__h50034 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo693 ; assign _dfoo830 = - (source_id__h50034 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo762 ; assign _dfoo831 = - source_id__h50034 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo695 ; assign _dfoo832 = - (source_id__h50034 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo764 ; assign _dfoo833 = - source_id__h50034 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo697 ; assign _dfoo834 = - (source_id__h50034 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo766 ; assign _dfoo835 = - source_id__h50034 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo699 ; assign _dfoo836 = - (source_id__h50034 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo768 ; assign _dfoo837 = - source_id__h50034 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo701 ; assign _dfoo838 = - (source_id__h50034 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo770 ; assign _dfoo839 = - source_id__h50034 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo703 ; assign _dfoo84 = - (source_id__h63344 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo16 ; assign _dfoo840 = - (source_id__h50034 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo772 ; assign _dfoo841 = - source_id__h50034 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo705 ; assign _dfoo842 = - (source_id__h50034 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo774 ; assign _dfoo843 = - source_id__h50034 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo707 ; assign _dfoo844 = - (source_id__h50034 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo776 ; assign _dfoo845 = - source_id__h50034 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo709 ; assign _dfoo846 = - (source_id__h50034 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo778 ; assign _dfoo847 = - source_id__h50034 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo711 ; assign _dfoo848 = - (source_id__h50034 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo780 ; assign _dfoo849 = - source_id__h50034 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo713 ; assign _dfoo850 = - (source_id__h50034 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo782 ; assign _dfoo851 = - source_id__h50034 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo715 ; assign _dfoo852 = - (source_id__h50034 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo784 ; assign _dfoo853 = - source_id__h50034 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo717 ; assign _dfoo854 = - (source_id__h50034 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo786 ; assign _dfoo855 = - source_id__h50034 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo719 ; assign _dfoo856 = - (source_id__h50034 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo788 ; assign _dfoo857 = - source_id__h50034 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo721 ; assign _dfoo858 = - (source_id__h50034 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo790 ; assign _dfoo859 = - source_id__h50034 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo723 ; assign _dfoo86 = - (source_id__h63344 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo18 ; assign _dfoo860 = - (source_id__h50034 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo792 ; assign _dfoo861 = - source_id__h50034 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo725 ; assign _dfoo862 = - (source_id__h50034 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo794 ; assign _dfoo863 = - source_id__h50034 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo727 ; assign _dfoo864 = - (source_id__h50034 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo796 ; assign _dfoo865 = - source_id__h50034 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo729 ; assign _dfoo866 = - (source_id__h50034 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo798 ; assign _dfoo867 = - source_id__h50034 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo731 ; assign _dfoo868 = - (source_id__h50034 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo800 ; assign _dfoo869 = - source_id__h50034 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo733 ; assign _dfoo870 = - (source_id__h50034 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo802 ; assign _dfoo871 = - source_id__h50034 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo735 ; assign _dfoo872 = - (source_id__h50034 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo804 ; assign _dfoo873 = - source_id__h50034 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo737 ; assign _dfoo874 = - (source_id__h50034 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo806 ; assign _dfoo875 = - source_id__h50034 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo739 ; assign _dfoo876 = - (source_id__h50034 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo808 ; assign _dfoo877 = - source_id__h50034 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo741 ; assign _dfoo878 = - (source_id__h50034 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo810 ; assign _dfoo879 = - source_id__h50034 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo743 ; assign _dfoo88 = - (source_id__h63344 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo20 ; assign _dfoo880 = - (source_id__h50034 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo812 ; assign _dfoo881 = - source_id__h50034 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo745 ; assign _dfoo882 = - (source_id__h50034 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo814 ; assign _dfoo883 = - source_id__h50034 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo747 ; assign _dfoo884 = - (source_id__h50034 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo816 ; assign _dfoo886 = - (source_id__h48824 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo818 ; assign _dfoo888 = - (source_id__h48824 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo820 ; assign _dfoo890 = - (source_id__h48824 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo822 ; assign _dfoo892 = - (source_id__h48824 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo824 ; assign _dfoo894 = - (source_id__h48824 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo826 ; assign _dfoo896 = - (source_id__h48824 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo828 ; assign _dfoo898 = - (source_id__h48824 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo830 ; assign _dfoo9 = - source_id__h64554 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo90 = - (source_id__h63344 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo22 ; assign _dfoo900 = - (source_id__h48824 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo832 ; assign _dfoo902 = - (source_id__h48824 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo834 ; assign _dfoo904 = - (source_id__h48824 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo836 ; assign _dfoo906 = - (source_id__h48824 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo838 ; assign _dfoo908 = - (source_id__h48824 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo840 ; assign _dfoo910 = - (source_id__h48824 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo842 ; assign _dfoo912 = - (source_id__h48824 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo844 ; assign _dfoo914 = - (source_id__h48824 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo846 ; assign _dfoo916 = - (source_id__h48824 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo848 ; assign _dfoo918 = - (source_id__h48824 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo850 ; assign _dfoo92 = - (source_id__h63344 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo24 ; assign _dfoo920 = - (source_id__h48824 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo852 ; assign _dfoo922 = - (source_id__h48824 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo854 ; assign _dfoo924 = - (source_id__h48824 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo856 ; assign _dfoo926 = - (source_id__h48824 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo858 ; assign _dfoo928 = - (source_id__h48824 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo860 ; assign _dfoo930 = - (source_id__h48824 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo862 ; assign _dfoo932 = - (source_id__h48824 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo864 ; assign _dfoo934 = - (source_id__h48824 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo866 ; assign _dfoo936 = - (source_id__h48824 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo868 ; assign _dfoo938 = - (source_id__h48824 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo870 ; assign _dfoo94 = - (source_id__h63344 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo26 ; assign _dfoo940 = - (source_id__h48824 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo872 ; assign _dfoo942 = - (source_id__h48824 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo874 ; assign _dfoo944 = - (source_id__h48824 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo876 ; assign _dfoo946 = - (source_id__h48824 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo878 ; assign _dfoo948 = - (source_id__h48824 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo880 ; assign _dfoo950 = - (source_id__h48824 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo882 ; assign _dfoo952 = - (source_id__h48824 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo884 ; assign _dfoo953 = - source_id__h47614 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo817 ; assign _dfoo954 = - (source_id__h47614 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo886 ; assign _dfoo955 = - source_id__h47614 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo819 ; assign _dfoo956 = - (source_id__h47614 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo888 ; assign _dfoo957 = - source_id__h47614 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo821 ; assign _dfoo958 = - (source_id__h47614 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo890 ; assign _dfoo959 = - source_id__h47614 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo823 ; assign _dfoo96 = - (source_id__h63344 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo28 ; assign _dfoo960 = - (source_id__h47614 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo892 ; assign _dfoo961 = - source_id__h47614 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo825 ; assign _dfoo962 = - (source_id__h47614 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo894 ; assign _dfoo963 = - source_id__h47614 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo827 ; assign _dfoo964 = - (source_id__h47614 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo896 ; assign _dfoo965 = - source_id__h47614 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo829 ; assign _dfoo966 = - (source_id__h47614 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo898 ; assign _dfoo967 = - source_id__h47614 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo831 ; assign _dfoo968 = - (source_id__h47614 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo900 ; assign _dfoo969 = - source_id__h47614 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo833 ; assign _dfoo970 = - (source_id__h47614 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo902 ; assign _dfoo971 = - source_id__h47614 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo835 ; assign _dfoo972 = - (source_id__h47614 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo904 ; assign _dfoo973 = - source_id__h47614 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo837 ; assign _dfoo974 = - (source_id__h47614 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo906 ; assign _dfoo975 = - source_id__h47614 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo839 ; assign _dfoo976 = - (source_id__h47614 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo908 ; assign _dfoo977 = - source_id__h47614 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo841 ; assign _dfoo978 = - (source_id__h47614 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo910 ; assign _dfoo979 = - source_id__h47614 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo843 ; assign _dfoo98 = - (source_id__h63344 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo30 ; assign _dfoo980 = - (source_id__h47614 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo912 ; assign _dfoo981 = - source_id__h47614 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo845 ; assign _dfoo982 = - (source_id__h47614 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo914 ; assign _dfoo983 = - source_id__h47614 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo847 ; assign _dfoo984 = - (source_id__h47614 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo916 ; assign _dfoo985 = - source_id__h47614 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo849 ; assign _dfoo986 = - (source_id__h47614 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo918 ; assign _dfoo987 = - source_id__h47614 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo851 ; assign _dfoo988 = - (source_id__h47614 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo920 ; assign _dfoo989 = - source_id__h47614 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo853 ; assign _dfoo990 = - (source_id__h47614 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo922 ; assign _dfoo991 = - source_id__h47614 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo855 ; assign _dfoo992 = - (source_id__h47614 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo924 ; assign _dfoo993 = - source_id__h47614 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo857 ; assign _dfoo994 = - (source_id__h47614 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo926 ; assign _dfoo995 = - source_id__h47614 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo859 ; assign _dfoo996 = - (source_id__h47614 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo928 ; assign _dfoo997 = - source_id__h47614 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo861 ; assign _dfoo998 = - (source_id__h47614 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo930 ; assign _dfoo999 = - source_id__h47614 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo863 ; - assign a__h71297 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? + assign a__h74356 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3216 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 ; - assign a__h73302 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3212 ; + assign a__h76361 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3310 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 ; - assign addr_offset__h13214 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26920 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71298 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3306 ; + assign addr_offset__h15646 = + m_slave_xactor_shim_arff_rv$port1__read[92:29] - m_rg_addr_base ; + assign addr_offset__h29732 = + m_slave_xactor_shim_awff_rv$port1__read[92:29] - m_rg_addr_base ; + assign b__h74357 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3216 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 ; - assign b__h73303 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3232 ; + assign b__h76362 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3310 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = - addr_offset__h13214 < 64'h0000000000003000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = - addr_offset__h13214[11:7] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 = - addr_offset__h13214 < 64'h0000000000001000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 = - addr_offset__h13214[11:2] <= 10'd16 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - addr_offset__h13214[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 && + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3326 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 = + addr_offset__h15646 < 64'h0000000000001000 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109 = + addr_offset__h15646[11:2] <= 10'd16 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d112 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + addr_offset__h15646[11:2] != 10'd0 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109 && m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 = - addr_offset__h13214[16:12] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 = - addr_offset__h13214 < 64'h0000000000002000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = - source_id_base__h13628 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 = - addr_offset__h26920[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 = - addr_offset__h26920[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 = - addr_offset__h26920[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 = - addr_offset__h26920 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 = - addr_offset__h26920[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 = - addr_offset__h26920[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 = - addr_offset__h26920[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 = - addr_offset__h26920[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 = - addr_offset__h26920[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 = - addr_offset__h26920[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 = - addr_offset__h26920[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 = - addr_offset__h26920[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 = - addr_offset__h26920[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 = - addr_offset__h26920[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 = - addr_offset__h26920[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 = - addr_offset__h26920[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 = - addr_offset__h26920[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 = - addr_offset__h26920[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 = - addr_offset__h26920[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 = - addr_offset__h26920[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 = - addr_offset__h26920[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - addr_offset__h26920[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 && + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 = + addr_offset__h15646 < 64'h0000000000002000 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 = + source_id_base__h16091 <= 10'd16 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 = + addr_offset__h15646 < 64'h0000000000003000 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311 = + addr_offset__h15646[11:7] <= 5'd1 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 = + addr_offset__h15646[16:12] <= 5'd1 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 = + m_slave_xactor_shim_arff_rv$port1__read[92:29] < m_rg_addr_base ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1000 = + addr_offset__h29732[11:2] == 10'd14 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1002 = + addr_offset__h29732[11:2] == 10'd15 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1004 = + addr_offset__h29732[11:2] == 10'd16 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1006 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + addr_offset__h29732[11:2] != 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 && m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 = - addr_offset__h26920 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 = - source_id_base__h28137 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 = - addr_offset__h26920 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26920[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 = - addr_offset__h26920[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 = - addr_offset__h26920[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 = + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 = + addr_offset__h29732 < 64'h0000000000002000 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 = + source_id_base__h30983 <= 10'd16 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 = + addr_offset__h29732 < 64'h0000000000003000 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 = + addr_offset__h29732[11:7] <= 5'd1 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 = + addr_offset__h29732[11:7] == 5'd0 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1029 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 = + addr_offset__h29732[11:7] == 5'd1 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1029 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 = + addr_offset__h29732[16:12] <= 5'd1 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2997 = + addr_offset__h29732[16:12] == 5'd0 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2994 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2999 = + addr_offset__h29732[16:12] == 5'd1 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2994 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 = + m_slave_xactor_shim_awff_rv$port1__read[92:29] < m_rg_addr_base ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 = + addr_offset__h29732 < 64'h0000000000001000 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 = + addr_offset__h29732[11:2] <= 10'd16 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d974 = + addr_offset__h29732[11:2] == 10'd1 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d976 = + addr_offset__h29732[11:2] == 10'd2 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d978 = + addr_offset__h29732[11:2] == 10'd3 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d980 = + addr_offset__h29732[11:2] == 10'd4 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d982 = + addr_offset__h29732[11:2] == 10'd5 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d984 = + addr_offset__h29732[11:2] == 10'd6 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d986 = + addr_offset__h29732[11:2] == 10'd7 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d988 = + addr_offset__h29732[11:2] == 10'd8 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d990 = + addr_offset__h29732[11:2] == 10'd9 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d992 = + addr_offset__h29732[11:2] == 10'd10 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d994 = + addr_offset__h29732[11:2] == 10'd11 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d996 = + addr_offset__h29732[11:2] == 10'd12 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d998 = + addr_offset__h29732[11:2] == 10'd13 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_bff_rvport1__read_BITS_6__ETC__q51 = + m_slave_xactor_shim_bff_rv$port1__read[6:0] ; + assign m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52 = + m_slave_xactor_shim_rff_rv$port1__read[71:0] ; + assign m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3186 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 && + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3182 && m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 = + assign m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3280 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 && + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3276 && m_vvrg_ie_1_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = + assign m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d683 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 = + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d677 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; + assign m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3191 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 && + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3187 && m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 = + assign m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3285 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 && + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3281 && m_vvrg_ie_1_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = + assign m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d690 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 = + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d684 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; + assign m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3196 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 && + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3192 && m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 = + assign m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3290 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 && + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3286 && m_vvrg_ie_1_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = + assign m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d697 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 = + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d691 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; + assign m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3201 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 && + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3197 && m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 = + assign m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3295 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 && + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3291 && m_vvrg_ie_1_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = + assign m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d704 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 || - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 || - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 || - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 || - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 = + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d698 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; + assign m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d760 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d704 || + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d697 || + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d690 || + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d683 || + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d676 || + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d669 || + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d754 ; + assign m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3206 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 && + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3202 && m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 = + assign m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3300 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 && + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3296 && m_vvrg_ie_1_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = + assign m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d711 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 = + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d705 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; + assign m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3211 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 && + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3207 && m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 = + assign m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3305 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 && + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3301 && m_vvrg_ie_1_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = + assign m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d718 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 = + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d712 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; + assign m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3216 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 && + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3212 && m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 = + assign m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3310 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 && + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3306 && m_vvrg_ie_1_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = + assign m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d725 = m_vrg_source_ip_16 && - !m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 || - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 || - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 || - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 ; - assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = + !m_vrg_source_prio_16_32_ULE_IF_m_vrg_source_ip_ETC___d720 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q49 ; + assign m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d763 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d725 || + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d718 || + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d711 || + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d760 ; + assign m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_sourc_ETC___d620 = m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; + assign m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3146 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 && + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3142 && m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 = + assign m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3240 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 && + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3236 && m_vvrg_ie_1_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = + assign m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d627 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 = + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d621 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; + assign m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3151 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 && + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3147 && m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 = + assign m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3245 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 && + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3241 && m_vvrg_ie_1_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = + assign m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d634 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 = + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d628 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; + assign m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3156 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 && + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3152 && m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 = + assign m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3250 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 && + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3246 && m_vvrg_ie_1_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = + assign m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d641 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 = + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d635 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; + assign m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3161 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 && + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3157 && m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 = + assign m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3255 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 && + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3251 && m_vvrg_ie_1_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = + assign m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d648 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 = + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d642 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; + assign m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3166 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 && + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3162 && m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 = + assign m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3260 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 && + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3256 && m_vvrg_ie_1_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = + assign m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d655 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 = + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d649 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; + assign m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3171 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 && + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3167 && m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 = + assign m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3265 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 && + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3261 && m_vvrg_ie_1_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = + assign m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d662 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 || - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 || - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 || - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 || - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 = + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d656 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; + assign m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d754 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d662 || + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d655 || + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d648 || + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d641 || + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d634 || + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d627 || + m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_sourc_ETC___d620 ; + assign m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3176 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 && + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3172 && m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 = + assign m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3270 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 && + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3266 && m_vvrg_ie_1_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = + assign m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d669 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 = + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d663 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; + assign m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3181 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 && + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3177 && m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 = + assign m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3275 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 && + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3271 && m_vvrg_ie_1_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = + assign m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d676 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; - assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 = + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d670 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; + assign m_vrg_source_prio_16_32_ULE_IF_m_vrg_source_ip_ETC___d720 = m_vrg_source_prio_16 <= - (m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? + (m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d718 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ; - assign max_id__h23957 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ? + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d712) ; + assign max_id__h26424 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d725 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ; - assign rdata___1__h26402 = { rdata__h26200[31:0], 32'h0 } ; - assign rdata__h26200 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d740 ; + assign rdata___1__h28973 = { rdata__h28669[31:0], 32'h0 } ; + assign rdata__h28669 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 ? 64'd0 : - y_avValue_fst__h26192 ; - assign rresp__h26201 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 2'b11 : - y_avValue_snd__h26193 ; - assign source_id__h15663 = { addr_offset__h13214[4:0], 5'd31 } ; - assign source_id__h15770 = { addr_offset__h13214[4:0], 5'd30 } ; - assign source_id__h15843 = { addr_offset__h13214[4:0], 5'd29 } ; - assign source_id__h15916 = { addr_offset__h13214[4:0], 5'd28 } ; - assign source_id__h15989 = { addr_offset__h13214[4:0], 5'd27 } ; - assign source_id__h16062 = { addr_offset__h13214[4:0], 5'd26 } ; - assign source_id__h16135 = { addr_offset__h13214[4:0], 5'd25 } ; - assign source_id__h16208 = { addr_offset__h13214[4:0], 5'd24 } ; - assign source_id__h16281 = { addr_offset__h13214[4:0], 5'd23 } ; - assign source_id__h16354 = { addr_offset__h13214[4:0], 5'd22 } ; - assign source_id__h16427 = { addr_offset__h13214[4:0], 5'd21 } ; - assign source_id__h16500 = { addr_offset__h13214[4:0], 5'd20 } ; - assign source_id__h16573 = { addr_offset__h13214[4:0], 5'd19 } ; - assign source_id__h16646 = { addr_offset__h13214[4:0], 5'd18 } ; - assign source_id__h16719 = { addr_offset__h13214[4:0], 5'd17 } ; - assign source_id__h16792 = { addr_offset__h13214[4:0], 5'd16 } ; - assign source_id__h16865 = { addr_offset__h13214[4:0], 5'd15 } ; - assign source_id__h16938 = { addr_offset__h13214[4:0], 5'd14 } ; - assign source_id__h17011 = { addr_offset__h13214[4:0], 5'd13 } ; - assign source_id__h17084 = { addr_offset__h13214[4:0], 5'd12 } ; - assign source_id__h17157 = { addr_offset__h13214[4:0], 5'd11 } ; - assign source_id__h17230 = { addr_offset__h13214[4:0], 5'd10 } ; - assign source_id__h17303 = { addr_offset__h13214[4:0], 5'd9 } ; - assign source_id__h17376 = { addr_offset__h13214[4:0], 5'd8 } ; - assign source_id__h17449 = { addr_offset__h13214[4:0], 5'd7 } ; - assign source_id__h17522 = { addr_offset__h13214[4:0], 5'd6 } ; - assign source_id__h17595 = { addr_offset__h13214[4:0], 5'd5 } ; - assign source_id__h17668 = { addr_offset__h13214[4:0], 5'd4 } ; - assign source_id__h17741 = { addr_offset__h13214[4:0], 5'd3 } ; - assign source_id__h17814 = { addr_offset__h13214[4:0], 5'd2 } ; - assign source_id__h17887 = { addr_offset__h13214[4:0], 5'd1 } ; - assign source_id__h20135 = 10'd31 + source_id_base__h13628 ; - assign source_id__h20311 = 10'd30 + source_id_base__h13628 ; - assign source_id__h20419 = 10'd29 + source_id_base__h13628 ; - assign source_id__h20527 = 10'd28 + source_id_base__h13628 ; - assign source_id__h20635 = 10'd27 + source_id_base__h13628 ; - assign source_id__h20743 = 10'd26 + source_id_base__h13628 ; - assign source_id__h20851 = 10'd25 + source_id_base__h13628 ; - assign source_id__h20959 = 10'd24 + source_id_base__h13628 ; - assign source_id__h21067 = 10'd23 + source_id_base__h13628 ; - assign source_id__h21175 = 10'd22 + source_id_base__h13628 ; - assign source_id__h21283 = 10'd21 + source_id_base__h13628 ; - assign source_id__h21391 = 10'd20 + source_id_base__h13628 ; - assign source_id__h21499 = 10'd19 + source_id_base__h13628 ; - assign source_id__h21607 = 10'd18 + source_id_base__h13628 ; - assign source_id__h21715 = 10'd17 + source_id_base__h13628 ; - assign source_id__h21823 = 10'd16 + source_id_base__h13628 ; - assign source_id__h21931 = 10'd15 + source_id_base__h13628 ; - assign source_id__h22039 = 10'd14 + source_id_base__h13628 ; - assign source_id__h22147 = 10'd13 + source_id_base__h13628 ; - assign source_id__h22255 = 10'd12 + source_id_base__h13628 ; - assign source_id__h22363 = 10'd11 + source_id_base__h13628 ; - assign source_id__h22471 = 10'd10 + source_id_base__h13628 ; - assign source_id__h22579 = 10'd9 + source_id_base__h13628 ; - assign source_id__h22687 = 10'd8 + source_id_base__h13628 ; - assign source_id__h22795 = 10'd7 + source_id_base__h13628 ; - assign source_id__h22903 = 10'd6 + source_id_base__h13628 ; - assign source_id__h23011 = 10'd5 + source_id_base__h13628 ; - assign source_id__h23119 = 10'd4 + source_id_base__h13628 ; - assign source_id__h23227 = 10'd3 + source_id_base__h13628 ; - assign source_id__h23335 = 10'd2 + source_id_base__h13628 ; - assign source_id__h23443 = 10'd1 + source_id_base__h13628 ; - assign source_id__h29464 = { addr_offset__h26920[4:0], 5'd1 } ; - assign source_id__h30674 = { addr_offset__h26920[4:0], 5'd2 } ; - assign source_id__h31884 = { addr_offset__h26920[4:0], 5'd3 } ; - assign source_id__h33094 = { addr_offset__h26920[4:0], 5'd4 } ; - assign source_id__h34304 = { addr_offset__h26920[4:0], 5'd5 } ; - assign source_id__h35514 = { addr_offset__h26920[4:0], 5'd6 } ; - assign source_id__h36724 = { addr_offset__h26920[4:0], 5'd7 } ; - assign source_id__h37934 = { addr_offset__h26920[4:0], 5'd8 } ; - assign source_id__h39144 = { addr_offset__h26920[4:0], 5'd9 } ; - assign source_id__h40354 = { addr_offset__h26920[4:0], 5'd10 } ; - assign source_id__h41564 = { addr_offset__h26920[4:0], 5'd11 } ; - assign source_id__h42774 = { addr_offset__h26920[4:0], 5'd12 } ; - assign source_id__h43984 = { addr_offset__h26920[4:0], 5'd13 } ; - assign source_id__h45194 = { addr_offset__h26920[4:0], 5'd14 } ; - assign source_id__h46404 = { addr_offset__h26920[4:0], 5'd15 } ; - assign source_id__h47614 = { addr_offset__h26920[4:0], 5'd16 } ; - assign source_id__h48824 = { addr_offset__h26920[4:0], 5'd17 } ; - assign source_id__h50034 = { addr_offset__h26920[4:0], 5'd18 } ; - assign source_id__h51244 = { addr_offset__h26920[4:0], 5'd19 } ; - assign source_id__h52454 = { addr_offset__h26920[4:0], 5'd20 } ; - assign source_id__h53664 = { addr_offset__h26920[4:0], 5'd21 } ; - assign source_id__h54874 = { addr_offset__h26920[4:0], 5'd22 } ; - assign source_id__h56084 = { addr_offset__h26920[4:0], 5'd23 } ; - assign source_id__h57294 = { addr_offset__h26920[4:0], 5'd24 } ; - assign source_id__h58504 = { addr_offset__h26920[4:0], 5'd25 } ; - assign source_id__h59714 = { addr_offset__h26920[4:0], 5'd26 } ; - assign source_id__h60924 = { addr_offset__h26920[4:0], 5'd27 } ; - assign source_id__h62134 = { addr_offset__h26920[4:0], 5'd28 } ; - assign source_id__h63344 = { addr_offset__h26920[4:0], 5'd29 } ; - assign source_id__h64554 = { addr_offset__h26920[4:0], 5'd30 } ; - assign source_id__h65764 = { addr_offset__h26920[4:0], 5'd31 } ; - assign source_id__h67425 = { 5'd0, x__h67476 } ; - assign source_id_base__h13628 = { addr_offset__h13214[4:0], 5'h0 } ; - assign source_id_base__h28137 = { addr_offset__h26920[4:0], 5'h0 } ; - assign v__h13420 = { 61'd0, x__h13491 } ; - assign v__h13669 = { 32'd0, v_ip__h13672 } ; - assign v__h18142 = { 32'd0, v_ie__h18145 } ; - assign v__h23759 = { 61'd0, x__h23830 } ; - assign v__h25453 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ? - v__h25472 : + y_avValue_fst__h28661 ; + assign source_id__h18127 = { addr_offset__h15646[4:0], 5'd31 } ; + assign source_id__h18234 = { addr_offset__h15646[4:0], 5'd30 } ; + assign source_id__h18307 = { addr_offset__h15646[4:0], 5'd29 } ; + assign source_id__h18380 = { addr_offset__h15646[4:0], 5'd28 } ; + assign source_id__h18453 = { addr_offset__h15646[4:0], 5'd27 } ; + assign source_id__h18526 = { addr_offset__h15646[4:0], 5'd26 } ; + assign source_id__h18599 = { addr_offset__h15646[4:0], 5'd25 } ; + assign source_id__h18672 = { addr_offset__h15646[4:0], 5'd24 } ; + assign source_id__h18745 = { addr_offset__h15646[4:0], 5'd23 } ; + assign source_id__h18818 = { addr_offset__h15646[4:0], 5'd22 } ; + assign source_id__h18891 = { addr_offset__h15646[4:0], 5'd21 } ; + assign source_id__h18964 = { addr_offset__h15646[4:0], 5'd20 } ; + assign source_id__h19037 = { addr_offset__h15646[4:0], 5'd19 } ; + assign source_id__h19110 = { addr_offset__h15646[4:0], 5'd18 } ; + assign source_id__h19183 = { addr_offset__h15646[4:0], 5'd17 } ; + assign source_id__h19256 = { addr_offset__h15646[4:0], 5'd16 } ; + assign source_id__h19329 = { addr_offset__h15646[4:0], 5'd15 } ; + assign source_id__h19402 = { addr_offset__h15646[4:0], 5'd14 } ; + assign source_id__h19475 = { addr_offset__h15646[4:0], 5'd13 } ; + assign source_id__h19548 = { addr_offset__h15646[4:0], 5'd12 } ; + assign source_id__h19621 = { addr_offset__h15646[4:0], 5'd11 } ; + assign source_id__h19694 = { addr_offset__h15646[4:0], 5'd10 } ; + assign source_id__h19767 = { addr_offset__h15646[4:0], 5'd9 } ; + assign source_id__h19840 = { addr_offset__h15646[4:0], 5'd8 } ; + assign source_id__h19913 = { addr_offset__h15646[4:0], 5'd7 } ; + assign source_id__h19986 = { addr_offset__h15646[4:0], 5'd6 } ; + assign source_id__h20059 = { addr_offset__h15646[4:0], 5'd5 } ; + assign source_id__h20132 = { addr_offset__h15646[4:0], 5'd4 } ; + assign source_id__h20205 = { addr_offset__h15646[4:0], 5'd3 } ; + assign source_id__h20278 = { addr_offset__h15646[4:0], 5'd2 } ; + assign source_id__h20351 = { addr_offset__h15646[4:0], 5'd1 } ; + assign source_id__h22600 = 10'd31 + source_id_base__h16091 ; + assign source_id__h22776 = 10'd30 + source_id_base__h16091 ; + assign source_id__h22884 = 10'd29 + source_id_base__h16091 ; + assign source_id__h22992 = 10'd28 + source_id_base__h16091 ; + assign source_id__h23100 = 10'd27 + source_id_base__h16091 ; + assign source_id__h23208 = 10'd26 + source_id_base__h16091 ; + assign source_id__h23316 = 10'd25 + source_id_base__h16091 ; + assign source_id__h23424 = 10'd24 + source_id_base__h16091 ; + assign source_id__h23532 = 10'd23 + source_id_base__h16091 ; + assign source_id__h23640 = 10'd22 + source_id_base__h16091 ; + assign source_id__h23748 = 10'd21 + source_id_base__h16091 ; + assign source_id__h23856 = 10'd20 + source_id_base__h16091 ; + assign source_id__h23964 = 10'd19 + source_id_base__h16091 ; + assign source_id__h24072 = 10'd18 + source_id_base__h16091 ; + assign source_id__h24180 = 10'd17 + source_id_base__h16091 ; + assign source_id__h24288 = 10'd16 + source_id_base__h16091 ; + assign source_id__h24396 = 10'd15 + source_id_base__h16091 ; + assign source_id__h24504 = 10'd14 + source_id_base__h16091 ; + assign source_id__h24612 = 10'd13 + source_id_base__h16091 ; + assign source_id__h24720 = 10'd12 + source_id_base__h16091 ; + assign source_id__h24828 = 10'd11 + source_id_base__h16091 ; + assign source_id__h24936 = 10'd10 + source_id_base__h16091 ; + assign source_id__h25044 = 10'd9 + source_id_base__h16091 ; + assign source_id__h25152 = 10'd8 + source_id_base__h16091 ; + assign source_id__h25260 = 10'd7 + source_id_base__h16091 ; + assign source_id__h25368 = 10'd6 + source_id_base__h16091 ; + assign source_id__h25476 = 10'd5 + source_id_base__h16091 ; + assign source_id__h25584 = 10'd4 + source_id_base__h16091 ; + assign source_id__h25692 = 10'd3 + source_id_base__h16091 ; + assign source_id__h25800 = 10'd2 + source_id_base__h16091 ; + assign source_id__h25908 = 10'd1 + source_id_base__h16091 ; + assign source_id__h32311 = { addr_offset__h29732[4:0], 5'd1 } ; + assign source_id__h33521 = { addr_offset__h29732[4:0], 5'd2 } ; + assign source_id__h34731 = { addr_offset__h29732[4:0], 5'd3 } ; + assign source_id__h35941 = { addr_offset__h29732[4:0], 5'd4 } ; + assign source_id__h37151 = { addr_offset__h29732[4:0], 5'd5 } ; + assign source_id__h38361 = { addr_offset__h29732[4:0], 5'd6 } ; + assign source_id__h39571 = { addr_offset__h29732[4:0], 5'd7 } ; + assign source_id__h40781 = { addr_offset__h29732[4:0], 5'd8 } ; + assign source_id__h41991 = { addr_offset__h29732[4:0], 5'd9 } ; + assign source_id__h43201 = { addr_offset__h29732[4:0], 5'd10 } ; + assign source_id__h44411 = { addr_offset__h29732[4:0], 5'd11 } ; + assign source_id__h45621 = { addr_offset__h29732[4:0], 5'd12 } ; + assign source_id__h46831 = { addr_offset__h29732[4:0], 5'd13 } ; + assign source_id__h48041 = { addr_offset__h29732[4:0], 5'd14 } ; + assign source_id__h49251 = { addr_offset__h29732[4:0], 5'd15 } ; + assign source_id__h50461 = { addr_offset__h29732[4:0], 5'd16 } ; + assign source_id__h51671 = { addr_offset__h29732[4:0], 5'd17 } ; + assign source_id__h52881 = { addr_offset__h29732[4:0], 5'd18 } ; + assign source_id__h54091 = { addr_offset__h29732[4:0], 5'd19 } ; + assign source_id__h55301 = { addr_offset__h29732[4:0], 5'd20 } ; + assign source_id__h56511 = { addr_offset__h29732[4:0], 5'd21 } ; + assign source_id__h57721 = { addr_offset__h29732[4:0], 5'd22 } ; + assign source_id__h58931 = { addr_offset__h29732[4:0], 5'd23 } ; + assign source_id__h60141 = { addr_offset__h29732[4:0], 5'd24 } ; + assign source_id__h61351 = { addr_offset__h29732[4:0], 5'd25 } ; + assign source_id__h62561 = { addr_offset__h29732[4:0], 5'd26 } ; + assign source_id__h63771 = { addr_offset__h29732[4:0], 5'd27 } ; + assign source_id__h64981 = { addr_offset__h29732[4:0], 5'd28 } ; + assign source_id__h66191 = { addr_offset__h29732[4:0], 5'd29 } ; + assign source_id__h67401 = { addr_offset__h29732[4:0], 5'd30 } ; + assign source_id__h68611 = { addr_offset__h29732[4:0], 5'd31 } ; + assign source_id__h70276 = { 5'd0, x__h70328 } ; + assign source_id_base__h16091 = { addr_offset__h15646[4:0], 5'h0 } ; + assign source_id_base__h30983 = { addr_offset__h29732[4:0], 5'h0 } ; + assign v__h15883 = { 61'd0, x__h15954 } ; + assign v__h16133 = { 32'd0, v_ip__h16136 } ; + assign v__h20607 = { 32'd0, v_ie__h20610 } ; + assign v__h26225 = { 61'd0, x__h26296 } ; + assign v__h27922 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d763 ? + v__h27941 : 64'd0 ; - assign v__h25472 = { 59'd0, max_id__h23957 } ; - assign v__h26925 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 ? - 2'b11 : - v__h27083 ; - assign v__h27083 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? - v__h27096 : - v__h27931 ; - assign v__h27096 = - (addr_offset__h26920[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848) ? - 2'b0 : - 2'b10 ; - assign v__h27931 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899) ? - v__h27950 : - v__h28114 ; - assign v__h27950 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 ? - 2'b0 : - 2'b10 ; - assign v__h28114 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913) ? - v__h28133 : - v__h67096 ; - assign v__h28133 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - 2'b0 : - 2'b10 ; - assign v__h67133 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? - 2'b0 : - 2'b10 ; - assign v__h67421 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? - v__h67465 : - 2'b10 ; - assign v__h67465 = - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ? - 2'b0 : - 2'b10 ; - assign v_ie__h18145 = - { source_id__h20135 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h20311 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h20419 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h20527 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h20635 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h20743 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h20851 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h20959 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h21067 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h21175 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h21283 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h21391 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h21499 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h21607 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h21715 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h21823 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h21931 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h22039 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h22147 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h22255 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h22363 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h22471 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h22579 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h22687 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h22795 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h22903 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h23011 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h23119 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h23227 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h23335 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h23443 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h13672 = - { source_id__h15663 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - source_id__h15770 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - source_id__h15843 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - source_id__h15916 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - source_id__h15989 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - source_id__h16062 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - source_id__h16135 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - source_id__h16208 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - source_id__h16281 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - source_id__h16354 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - source_id__h16427 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - source_id__h16500 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - source_id__h16573 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - source_id__h16646 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - source_id__h16719 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - source_id__h16792 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - source_id__h16865 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - source_id__h16938 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - source_id__h17011 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - source_id__h17084 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - source_id__h17157 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - source_id__h17230 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - source_id__h17303 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - source_id__h17376 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - source_id__h17449 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - source_id__h17522 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - source_id__h17595 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - source_id__h17668 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - source_id__h17741 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - source_id__h17814 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - source_id__h17887 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26921 = - (addr_offset__h26920[2:0] == 3'd4) ? - m_slave_xactor_f_wr_data$D_OUT[72:41] : - m_slave_xactor_f_wr_data$D_OUT[40:9] ; - assign x__h23671 = - { addr_offset__h13214[31:16], 4'd0, addr_offset__h13214[11:0] } ; - assign x__h26359 = - (addr_offset__h13214[2:0] == 3'd4) ? - rdata___1__h26402 : - rdata__h26200 ; - assign x__h67099 = - { addr_offset__h26920[31:16], 4'd0, addr_offset__h26920[11:0] } ; - assign y_avValue_fst__h26092 = (x__h24009 == 5'd0) ? v__h25453 : 64'd0 ; - assign y_avValue_fst__h26113 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_fst__h26092 : + assign v__h27941 = { 59'd0, max_id__h26424 } ; + assign v_ie__h20610 = + { source_id__h22600 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, + source_id__h22776 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, + source_id__h22884 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, + source_id__h22992 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, + source_id__h23100 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, + source_id__h23208 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, + source_id__h23316 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, + source_id__h23424 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, + source_id__h23532 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, + source_id__h23640 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, + source_id__h23748 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, + source_id__h23856 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, + source_id__h23964 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, + source_id__h24072 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, + source_id__h24180 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, + source_id__h24288 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, + source_id__h24396 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, + source_id__h24504 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, + source_id__h24612 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, + source_id__h24720 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, + source_id__h24828 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, + source_id__h24936 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, + source_id__h25044 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, + source_id__h25152 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, + source_id__h25260 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, + source_id__h25368 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, + source_id__h25476 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, + source_id__h25584 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, + source_id__h25692 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, + source_id__h25800 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, + source_id__h25908 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q33 } ; + assign v_ip__h16136 = + { source_id__h18127 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167, + source_id__h18234 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171, + source_id__h18307 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176, + source_id__h18380 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180, + source_id__h18453 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185, + source_id__h18526 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189, + source_id__h18599 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194, + source_id__h18672 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198, + source_id__h18745 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203, + source_id__h18818 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207, + source_id__h18891 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212, + source_id__h18964 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216, + source_id__h19037 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221, + source_id__h19110 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225, + source_id__h19183 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230, + source_id__h19256 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234, + source_id__h19329 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239, + source_id__h19402 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243, + source_id__h19475 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248, + source_id__h19548 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252, + source_id__h19621 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257, + source_id__h19694 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261, + source_id__h19767 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266, + source_id__h19840 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270, + source_id__h19913 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275, + source_id__h19986 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279, + source_id__h20059 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284, + source_id__h20132 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288, + source_id__h20205 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293, + source_id__h20278 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297, + source_id__h20351 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 } ; + assign wdata32__h29733 = + (addr_offset__h29732[2:0] == 3'd4) ? + m_slave_xactor_shim_wff_rv$port1__read[72:41] : + m_slave_xactor_shim_wff_rv$port1__read[40:9] ; + assign x__h26136 = + { addr_offset__h15646[31:16], 4'd0, addr_offset__h15646[11:0] } ; + assign x__h28872 = + (addr_offset__h15646[2:0] == 3'd4) ? + rdata___1__h28973 : + rdata__h28669 ; + assign x__h69947 = + { addr_offset__h29732[31:16], 4'd0, addr_offset__h29732[11:0] } ; + assign y_avValue_fst__h28561 = (x__h26477 == 5'd0) ? v__h27922 : 64'd0 ; + assign y_avValue_fst__h28582 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 ? + y_avValue_fst__h28561 : 64'd0 ; - assign y_avValue_fst__h26125 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - v__h23759 : + assign y_avValue_fst__h28594 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 ? + v__h26225 : 64'd0 ; - assign y_avValue_fst__h26141 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - v__h18142 : + assign y_avValue_fst__h28610 = + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311) ? + v__h20607 : 64'd0 ; - assign y_avValue_fst__h26157 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - v__h13669 : + assign y_avValue_fst__h28626 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 ? + v__h16133 : 64'd0 ; - assign y_avValue_fst__h26162 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_fst__h26141 : - y_avValue_fst__h26146 ; - assign y_avValue_fst__h26173 = - (addr_offset__h13214[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - v__h13420 : + assign y_avValue_fst__h28631 = + (!m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309) ? + y_avValue_fst__h28610 : + y_avValue_fst__h28615 ; + assign y_avValue_fst__h28642 = + (addr_offset__h15646[11:2] != 10'd0 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109) ? + v__h15883 : 64'd0 ; - assign y_avValue_fst__h26178 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_fst__h26157 : - y_avValue_fst__h26162 ; - assign y_avValue_fst__h26192 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_fst__h26173 : - y_avValue_fst__h26178 ; - assign y_avValue_snd__h26093 = (x__h24009 == 5'd0) ? 2'b0 : 2'b10 ; - assign y_avValue_snd__h26114 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_snd__h26093 : - 2'b10 ; - assign y_avValue_snd__h26126 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26142 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26158 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26163 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_snd__h26142 : - y_avValue_snd__h26147 ; - assign y_avValue_snd__h26174 = - (addr_offset__h13214[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26179 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_snd__h26158 : - y_avValue_snd__h26163 ; - assign y_avValue_snd__h26193 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_snd__h26174 : - y_avValue_snd__h26179 ; - always@(addr_offset__h13214 or + assign y_avValue_fst__h28647 = + (!m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137) ? + y_avValue_fst__h28626 : + y_avValue_fst__h28631 ; + assign y_avValue_fst__h28661 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 ? + y_avValue_fst__h28642 : + y_avValue_fst__h28647 ; + always@(addr_offset__h29732 or + m_vrg_servicing_source_0 or m_vrg_servicing_source_1) + begin + case (addr_offset__h29732[16:12]) + 5'd0: x__h70328 = m_vrg_servicing_source_0; + 5'd1: x__h70328 = m_vrg_servicing_source_1; + default: x__h70328 = 5'b01010 /* unspecified value */ ; + endcase + end + always@(source_id__h70276 or + m_vrg_source_busy_0 or + m_vrg_source_busy_1 or + m_vrg_source_busy_2 or + m_vrg_source_busy_3 or + m_vrg_source_busy_4 or + m_vrg_source_busy_5 or + m_vrg_source_busy_6 or + m_vrg_source_busy_7 or + m_vrg_source_busy_8 or + m_vrg_source_busy_9 or + m_vrg_source_busy_10 or + m_vrg_source_busy_11 or + m_vrg_source_busy_12 or + m_vrg_source_busy_13 or + m_vrg_source_busy_14 or + m_vrg_source_busy_15 or m_vrg_source_busy_16) + begin + case (source_id__h70276) + 10'd0: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_0; + 10'd1: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_1; + 10'd2: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_2; + 10'd3: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_3; + 10'd4: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_4; + 10'd5: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_5; + 10'd6: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_6; + 10'd7: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_7; + 10'd8: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_8; + 10'd9: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_9; + 10'd10: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_10; + 10'd11: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_11; + 10'd12: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_12; + 10'd13: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_13; + 10'd14: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_14; + 10'd15: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_15; + 10'd16: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_16; + default: SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(x__h69947 or + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 or + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030) + begin + case (x__h69947) + 32'h00200000: + CASE_x9947_0x200000_IF_m_slave_xactor_shim_awf_ETC__q1 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 ? + 2'd0 : + 2'd2; + 32'h00200004: + CASE_x9947_0x200000_IF_m_slave_xactor_shim_awf_ETC__q1 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 ? + (SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 ? + 2'd0 : + 2'd2) : + 2'd2; + default: CASE_x9947_0x200000_IF_m_slave_xactor_shim_awf_ETC__q1 = 2'd2; + endcase + end + always@(addr_offset__h15646 or m_vrg_source_prio_0 or m_vrg_source_prio_1 or m_vrg_source_prio_2 or @@ -16808,128 +17230,46 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_prio_14 or m_vrg_source_prio_15 or m_vrg_source_prio_16) begin - case (addr_offset__h13214[11:2]) - 10'd0: x__h13491 = m_vrg_source_prio_0; - 10'd1: x__h13491 = m_vrg_source_prio_1; - 10'd2: x__h13491 = m_vrg_source_prio_2; - 10'd3: x__h13491 = m_vrg_source_prio_3; - 10'd4: x__h13491 = m_vrg_source_prio_4; - 10'd5: x__h13491 = m_vrg_source_prio_5; - 10'd6: x__h13491 = m_vrg_source_prio_6; - 10'd7: x__h13491 = m_vrg_source_prio_7; - 10'd8: x__h13491 = m_vrg_source_prio_8; - 10'd9: x__h13491 = m_vrg_source_prio_9; - 10'd10: x__h13491 = m_vrg_source_prio_10; - 10'd11: x__h13491 = m_vrg_source_prio_11; - 10'd12: x__h13491 = m_vrg_source_prio_12; - 10'd13: x__h13491 = m_vrg_source_prio_13; - 10'd14: x__h13491 = m_vrg_source_prio_14; - 10'd15: x__h13491 = m_vrg_source_prio_15; - 10'd16: x__h13491 = m_vrg_source_prio_16; - default: x__h13491 = 3'b010 /* unspecified value */ ; + case (addr_offset__h15646[11:2]) + 10'd0: x__h15954 = m_vrg_source_prio_0; + 10'd1: x__h15954 = m_vrg_source_prio_1; + 10'd2: x__h15954 = m_vrg_source_prio_2; + 10'd3: x__h15954 = m_vrg_source_prio_3; + 10'd4: x__h15954 = m_vrg_source_prio_4; + 10'd5: x__h15954 = m_vrg_source_prio_5; + 10'd6: x__h15954 = m_vrg_source_prio_6; + 10'd7: x__h15954 = m_vrg_source_prio_7; + 10'd8: x__h15954 = m_vrg_source_prio_8; + 10'd9: x__h15954 = m_vrg_source_prio_9; + 10'd10: x__h15954 = m_vrg_source_prio_10; + 10'd11: x__h15954 = m_vrg_source_prio_11; + 10'd12: x__h15954 = m_vrg_source_prio_12; + 10'd13: x__h15954 = m_vrg_source_prio_13; + 10'd14: x__h15954 = m_vrg_source_prio_14; + 10'd15: x__h15954 = m_vrg_source_prio_15; + 10'd16: x__h15954 = m_vrg_source_prio_16; + default: x__h15954 = 3'b010 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or + always@(addr_offset__h15646 or m_vrg_target_threshold_0 or m_vrg_target_threshold_1) begin - case (addr_offset__h13214[16:12]) - 5'd0: x__h23830 = m_vrg_target_threshold_0; - 5'd1: x__h23830 = m_vrg_target_threshold_1; - default: x__h23830 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13214 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h13214[16:12]) - 5'd0: x__h24009 = m_vrg_servicing_source_0; - 5'd1: x__h24009 = m_vrg_servicing_source_1; - default: x__h24009 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h15646[16:12]) + 5'd0: x__h26296 = m_vrg_target_threshold_0; + 5'd1: x__h26296 = m_vrg_target_threshold_1; + default: x__h26296 = 3'b010 /* unspecified value */ ; endcase end - always@(addr_offset__h26920 or + always@(addr_offset__h15646 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h26920[16:12]) - 5'd0: x__h67476 = m_vrg_servicing_source_0; - 5'd1: x__h67476 = m_vrg_servicing_source_1; - default: x__h67476 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id__h16208 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16208) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; + case (addr_offset__h15646[16:12]) + 5'd0: x__h26477 = m_vrg_servicing_source_0; + 5'd1: x__h26477 = m_vrg_servicing_source_1; + default: x__h26477 = 5'b01010 /* unspecified value */ ; endcase end - always@(source_id_base__h13628 or + always@(source_id_base__h16091 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -16946,63 +17286,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id_base__h13628) + case (source_id_base__h16091) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20311 or + always@(source_id__h22776 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17019,63 +17359,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20311) + case (source_id__h22776) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20311 or + always@(source_id__h22776 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17092,63 +17432,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20311) + case (source_id__h22776) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20135 or + always@(source_id__h22600 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17165,63 +17505,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20135) + case (source_id__h22600) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20135 or + always@(source_id__h22600 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17238,63 +17578,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20135) + case (source_id__h22600) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h15663 or + always@(source_id__h18127 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17311,63 +17651,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h15663) + case (source_id__h18127) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20419 or + always@(source_id__h22884 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17384,63 +17724,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20419) + case (source_id__h22884) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20419 or + always@(source_id__h22884 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17457,63 +17797,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20419) + case (source_id__h22884) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20527 or + always@(source_id__h22992 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17530,63 +17870,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20527) + case (source_id__h22992) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20527 or + always@(source_id__h22992 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17603,63 +17943,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20527) + case (source_id__h22992) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h15770 or + always@(source_id__h18234 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17676,63 +18016,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h15770) + case (source_id__h18234) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20635 or + always@(source_id__h23100 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17749,63 +18089,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20635) + case (source_id__h23100) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20635 or + always@(source_id__h23100 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17822,63 +18162,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20635) + case (source_id__h23100) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20743 or + always@(source_id__h23208 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17895,63 +18235,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20743) + case (source_id__h23208) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20743 or + always@(source_id__h23208 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17968,63 +18308,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20743) + case (source_id__h23208) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h15843 or + always@(source_id__h18380 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18041,63 +18381,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h15843) + case (source_id__h18380) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h15916 or + always@(source_id__h18307 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18114,355 +18454,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h15916) + case (source_id__h18307) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20851 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + always@(source_id__h23316 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20851) + case (source_id__h23316) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_0; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = + m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_1; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = + m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_2; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = + m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_3; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = + m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20851 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20851) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20959 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20959) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15989 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15989) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20959 or + always@(source_id__h23316 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18479,136 +18600,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20959) + case (source_id__h23316) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16062 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16062) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21067 or + always@(source_id__h23424 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18625,63 +18673,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21067) + case (source_id__h23424) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21067 or + always@(source_id__h23424 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18698,136 +18746,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21067) + case (source_id__h23424) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21175 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21175) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16135 or + always@(source_id__h18453 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18844,136 +18819,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16135) + case (source_id__h18453) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21175 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + always@(source_id__h18526 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h21175) + case (source_id__h18526) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21283 or + always@(source_id__h23532 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18990,63 +18965,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21283) + case (source_id__h23532) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21283 or + always@(source_id__h23532 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19063,63 +19038,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21283) + case (source_id__h23532) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21391 or + always@(source_id__h23640 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19136,63 +19111,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21391) + case (source_id__h23640) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21391 or + always@(source_id__h23640 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19209,63 +19184,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21391) + case (source_id__h23640) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16281 or + always@(source_id__h18599 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19282,63 +19257,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16281) + case (source_id__h18599) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16354 or + always@(source_id__h18672 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19355,63 +19330,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16354) + case (source_id__h18672) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_1; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h23748 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h23748) + 10'd0: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_0; + 10'd1: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_2; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_3; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_4; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_5; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_6; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_7; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_8; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_9; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_10; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_11; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_12; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_13; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_14; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_15; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21499 or + always@(source_id__h23748 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19428,63 +19476,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21499) + case (source_id__h23748) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21499 or + always@(source_id__h23856 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19501,136 +19549,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21499) + case (source_id__h23856) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21607 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + always@(source_id__h23856 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21607) + case (source_id__h23856) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_0; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_1; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_2; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_3; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_4; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_5; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_6; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_7; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_8; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_9; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_10; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_11; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_12; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_13; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_14; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_15; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16427 or + always@(source_id__h18818 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19647,136 +19695,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16427) + case (source_id__h18818) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21607 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21607) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16500 or + always@(source_id__h18745 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19793,63 +19768,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16500) + case (source_id__h18745) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21715 or + always@(source_id__h23964 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19866,63 +19841,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21715) + case (source_id__h23964) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21715 or + always@(source_id__h23964 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19939,63 +19914,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21715) + case (source_id__h23964) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21823 or + always@(source_id__h24072 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20012,136 +19987,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21823) + case (source_id__h24072) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16573 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16573) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21823 or + always@(source_id__h24072 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20158,63 +20060,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21823) + case (source_id__h24072) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h18891 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h18891) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16646 or + always@(source_id__h18964 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20231,63 +20206,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16646) + case (source_id__h18964) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21931 or + always@(source_id__h24180 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20304,63 +20279,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21931) + case (source_id__h24180) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21931 or + always@(source_id__h24180 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20377,63 +20352,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21931) + case (source_id__h24180) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22039 or + always@(source_id__h24288 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20450,63 +20425,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22039) + case (source_id__h24288) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22039 or + always@(source_id__h24288 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20523,63 +20498,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22039) + case (source_id__h24288) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16719 or + always@(source_id__h19037 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20596,63 +20571,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16719) + case (source_id__h19037) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16792 or + always@(source_id__h24396 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h24396) + 10'd0: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_0; + 10'd1: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_1; + 10'd2: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_2; + 10'd3: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_3; + 10'd4: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_4; + 10'd5: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_5; + 10'd6: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_6; + 10'd7: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_7; + 10'd8: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_8; + 10'd9: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_9; + 10'd10: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_10; + 10'd11: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_11; + 10'd12: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_12; + 10'd13: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_13; + 10'd14: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_14; + 10'd15: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_15; + 10'd16: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h19110 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20669,63 +20717,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16792) + case (source_id__h19110) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22147 or + always@(source_id__h24396 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20742,63 +20790,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22147) + case (source_id__h24396) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22147 or + always@(source_id__h24504 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20815,63 +20863,209 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22147) + case (source_id__h24504) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h24504 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h24504) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h19183 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h19183) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22255 or + always@(source_id__h24612 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20888,63 +21082,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22255) + case (source_id__h24612) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16865 or + always@(source_id__h19256 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20961,63 +21155,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16865) + case (source_id__h19256) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h24612 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h24612) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22255 or + always@(source_id__h24720 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21034,63 +21301,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22255) + case (source_id__h24720) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h24720 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h24720) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_0; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_1; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_2; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_3; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_4; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_5; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_6; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_7; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_8; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_9; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_10; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_11; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_12; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_13; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_14; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_15; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16938 or + always@(source_id__h19329 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21107,63 +21447,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16938) + case (source_id__h19329) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22363 or + always@(source_id__h24828 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21180,63 +21520,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22363) + case (source_id__h24828) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h19402 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h19402) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22363 or + always@(source_id__h24828 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21253,63 +21666,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22363) + case (source_id__h24828) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22471 or + always@(source_id__h24936 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21326,136 +21739,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22471) + case (source_id__h24936) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17011 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17011) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22471 or + always@(source_id__h24936 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21472,63 +21812,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22471) + case (source_id__h24936) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17084 or + always@(source_id__h19475 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21545,63 +21885,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17084) + case (source_id__h19475) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22579 or + always@(source_id__h25044 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21618,63 +21958,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22579) + case (source_id__h25044) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h19548 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h19548) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22579 or + always@(source_id__h25044 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21691,63 +22104,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22579) + case (source_id__h25044) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22687 or + always@(source_id__h25152 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21764,63 +22177,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22687) + case (source_id__h25152) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22687 or + always@(source_id__h25152 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21837,63 +22250,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22687) + case (source_id__h25152) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17157 or + always@(source_id__h19621 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21910,63 +22323,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17157) + case (source_id__h19621) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17230 or + always@(source_id__h19694 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21983,63 +22396,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17230) + case (source_id__h19694) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22795 or + always@(source_id__h25260 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22056,63 +22469,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22795) + case (source_id__h25260) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22795 or + always@(source_id__h25260 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22129,63 +22542,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22795) + case (source_id__h25260) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22903 or + always@(source_id__h25368 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22202,136 +22615,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22903) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17303 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17303) + case (source_id__h25368) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22903 or + always@(source_id__h25368 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22348,63 +22688,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22903) + case (source_id__h25368) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17376 or + always@(source_id__h19767 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22421,136 +22761,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17376) + case (source_id__h19767) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23011 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + always@(source_id__h19840 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h23011) + case (source_id__h19840) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_0; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_1; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_2; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_3; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_4; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_5; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_6; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_7; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_8; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_9; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_10; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_11; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_12; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_13; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_14; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_15; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23011 or + always@(source_id__h25476 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22567,63 +22907,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23011) + case (source_id__h25476) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h25476 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h25476) + 10'd0: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_0; + 10'd1: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_1; + 10'd2: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_2; + 10'd3: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_3; + 10'd4: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_4; + 10'd5: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_5; + 10'd6: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_6; + 10'd7: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_7; + 10'd8: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_8; + 10'd9: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_9; + 10'd10: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_10; + 10'd11: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_11; + 10'd12: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_12; + 10'd13: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_13; + 10'd14: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_14; + 10'd15: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_15; + 10'd16: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23119 or + always@(source_id__h25584 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22640,63 +23053,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23119) + case (source_id__h25584) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17449 or + always@(source_id__h19913 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22713,63 +23126,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17449) + case (source_id__h19913) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23119 or + always@(source_id__h25584 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22786,63 +23199,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23119) + case (source_id__h25584) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17522 or + always@(source_id__h19986 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22859,136 +23272,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17522) + case (source_id__h19986) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23227 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23227) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23227 or + always@(source_id__h25692 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23005,63 +23345,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23227) + case (source_id__h25692) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h25692 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h25692) + 10'd0: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_0; + 10'd1: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_1; + 10'd2: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_2; + 10'd3: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_3; + 10'd4: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_4; + 10'd5: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_5; + 10'd6: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_6; + 10'd7: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_7; + 10'd8: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_8; + 10'd9: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_9; + 10'd10: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_10; + 10'd11: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_11; + 10'd12: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_12; + 10'd13: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_13; + 10'd14: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23335 or + always@(source_id__h25800 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23078,63 +23491,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23335) + case (source_id__h25800) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23335 or + always@(source_id__h25800 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23151,63 +23564,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23335) + case (source_id__h25800) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17595 or + always@(source_id__h20059 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23224,63 +23637,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17595) + case (source_id__h20059) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17668 or + always@(source_id__h20132 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23297,63 +23710,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17668) + case (source_id__h20132) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23443 or + always@(source_id__h25908 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23370,63 +23783,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23443) + case (source_id__h25908) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23443 or + always@(source_id__h25908 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23443,63 +23856,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23443) + case (source_id__h25908) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id_base__h13628 or + always@(source_id_base__h16091 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23516,136 +23929,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id_base__h13628) + case (source_id_base__h16091) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17741 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17741) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id_base__h13628 or + always@(source_id_base__h16091 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23662,543 +24002,543 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id_base__h13628) + case (source_id_base__h16091) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q33 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q33 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q33 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17814 or + always@(source_id__h20205 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24215,63 +24555,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17814) + case (source_id__h20205) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17887 or + always@(source_id__h20278 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24288,366 +24628,367 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17887) + case (source_id__h20278) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h23671 or y_avValue_snd__h26126 or y_avValue_snd__h26114) + always@(source_id__h20351 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (x__h23671) - 32'h00200000: y_avValue_snd__h26147 = y_avValue_snd__h26126; - 32'h00200004: y_avValue_snd__h26147 = y_avValue_snd__h26114; - default: y_avValue_snd__h26147 = 2'b10; + case (source_id__h20351) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) + always@(addr_offset__h15646 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = m_vvrg_ie_0_1; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = m_vvrg_ie_1_1; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) + always@(addr_offset__h15646 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = m_vvrg_ie_0_2; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = m_vvrg_ie_1_2; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) + always@(addr_offset__h15646 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = m_vvrg_ie_0_3; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = m_vvrg_ie_1_3; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) + always@(addr_offset__h15646 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = m_vvrg_ie_0_4; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = m_vvrg_ie_1_4; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) + always@(addr_offset__h15646 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = m_vvrg_ie_0_5; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = m_vvrg_ie_1_5; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) + always@(addr_offset__h15646 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = m_vvrg_ie_0_6; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = m_vvrg_ie_1_6; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) + always@(addr_offset__h15646 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = m_vvrg_ie_0_7; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = m_vvrg_ie_1_7; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) + always@(addr_offset__h15646 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = m_vvrg_ie_0_8; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = m_vvrg_ie_1_8; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) + always@(addr_offset__h15646 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = m_vvrg_ie_0_9; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = m_vvrg_ie_1_9; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) + always@(addr_offset__h15646 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = m_vvrg_ie_0_10; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = m_vvrg_ie_1_10; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) + always@(addr_offset__h15646 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = m_vvrg_ie_0_11; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = m_vvrg_ie_1_11; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) + always@(addr_offset__h15646 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = m_vvrg_ie_0_12; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = m_vvrg_ie_1_12; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) + always@(addr_offset__h15646 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = m_vvrg_ie_0_13; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = m_vvrg_ie_1_13; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) + always@(addr_offset__h15646 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = m_vvrg_ie_0_14; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = m_vvrg_ie_1_14; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) + always@(addr_offset__h15646 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = m_vvrg_ie_0_15; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = m_vvrg_ie_1_15; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) + always@(addr_offset__h15646 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q49 = m_vvrg_ie_0_16; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q49 = m_vvrg_ie_1_16; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q49 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h23671 or y_avValue_fst__h26125 or y_avValue_fst__h26113) - begin - case (x__h23671) - 32'h00200000: y_avValue_fst__h26146 = y_avValue_fst__h26125; - 32'h00200004: y_avValue_fst__h26146 = y_avValue_fst__h26113; - default: y_avValue_fst__h26146 = 64'd0; - endcase - end - always@(source_id__h67425 or - m_vrg_source_busy_0 or - m_vrg_source_busy_1 or - m_vrg_source_busy_2 or - m_vrg_source_busy_3 or - m_vrg_source_busy_4 or - m_vrg_source_busy_5 or - m_vrg_source_busy_6 or - m_vrg_source_busy_7 or - m_vrg_source_busy_8 or - m_vrg_source_busy_9 or - m_vrg_source_busy_10 or - m_vrg_source_busy_11 or - m_vrg_source_busy_12 or - m_vrg_source_busy_13 or - m_vrg_source_busy_14 or - m_vrg_source_busy_15 or m_vrg_source_busy_16) + always@(x__h26136 or y_avValue_fst__h28594 or y_avValue_fst__h28582) begin - case (source_id__h67425) - 10'd0: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_0; - 10'd1: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_1; - 10'd2: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_2; - 10'd3: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_3; - 10'd4: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_4; - 10'd5: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_5; - 10'd6: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_6; - 10'd7: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_7; - 10'd8: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_8; - 10'd9: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_9; - 10'd10: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_10; - 10'd11: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_11; - 10'd12: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_12; - 10'd13: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_13; - 10'd14: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_14; - 10'd15: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_15; - 10'd16: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - 1'b0 /* unspecified value */ ; + case (x__h26136) + 32'h00200000: y_avValue_fst__h28615 = y_avValue_fst__h28594; + 32'h00200004: y_avValue_fst__h28615 = y_avValue_fst__h28582; + default: y_avValue_fst__h28615 = 64'd0; endcase end - always@(x__h67099 or v__h67133 or v__h67421) + always@(x__h26136 or + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 or + x__h26477) begin - case (x__h67099) - 32'h00200000: v__h67096 = v__h67133; - 32'h00200004: v__h67096 = v__h67421; - default: v__h67096 = 2'b10; + case (x__h26136) + 32'h00200000: + CASE_x6136_0x200000_IF_m_slave_xactor_shim_arf_ETC__q50 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 ? + 2'd0 : + 2'd2; + 32'h00200004: + CASE_x6136_0x200000_IF_m_slave_xactor_shim_arf_ETC__q50 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 ? + ((x__h26477 == 5'd0) ? 2'd0 : 2'd2) : + 2'd2; + default: CASE_x6136_0x200000_IF_m_slave_xactor_shim_arf_ETC__q50 = 2'd2; endcase end @@ -24658,6 +24999,16 @@ module mkPLIC_16_2_7(CLK, if (RST_N == `BSV_RESET_VALUE) begin m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; + m_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + m_slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 8'd42; + m_slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 73'h0AAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY 5'd0; m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY 5'd0; m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -24752,6 +25103,24 @@ module mkPLIC_16_2_7(CLK, begin if (m_cfg_verbosity$EN) m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN; + if (m_slave_xactor_clearing$EN) + m_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_clearing$D_IN; + if (m_slave_xactor_shim_arff_rv$EN) + m_slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_shim_arff_rv$D_IN; + if (m_slave_xactor_shim_awff_rv$EN) + m_slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_shim_awff_rv$D_IN; + if (m_slave_xactor_shim_bff_rv$EN) + m_slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_shim_bff_rv$D_IN; + if (m_slave_xactor_shim_rff_rv$EN) + m_slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_shim_rff_rv$D_IN; + if (m_slave_xactor_shim_wff_rv$EN) + m_slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_shim_wff_rv$D_IN; if (m_vrg_servicing_source_0$EN) m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_servicing_source_0$D_IN; @@ -24983,6 +25352,12 @@ module mkPLIC_16_2_7(CLK, m_cfg_verbosity = 4'hA; m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA; m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; + m_slave_xactor_clearing = 1'h0; + m_slave_xactor_shim_arff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_awff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_bff_rv = 8'hAA; + m_slave_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; m_vrg_servicing_source_0 = 5'h0A; m_vrg_servicing_source_1 = 5'h0A; m_vrg_source_busy_0 = 1'h0; @@ -25234,9 +25609,9 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71297, + a__h74356, m_vrg_target_threshold_0, - b__h71298, + b__h74357, m_vrg_servicing_source_0); if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); @@ -25277,1674 +25652,1955 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73302, + a__h76361, m_vrg_target_threshold_1, - b__h73303, + b__h76362, m_vrg_servicing_source_1); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240) + if (NOT_m_vrg_source_busy_1_013_363_AND_NOT_m_cfg__ETC___d3367) begin - v__h75659 = $stime; + v__h78778 = $stime; #0; end - v__h75653 = v__h75659 / 32'd10; + v__h78772 = v__h78778 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240) + if (NOT_m_vrg_source_busy_1_013_363_AND_NOT_m_cfg__ETC___d3367) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75653, + v__h78772, $signed(32'd1), v_sources_0_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247) + if (NOT_m_vrg_source_busy_2_014_370_AND_NOT_m_cfg__ETC___d3374) begin - v__h75857 = $stime; + v__h78976 = $stime; #0; end - v__h75851 = v__h75857 / 32'd10; + v__h78970 = v__h78976 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247) + if (NOT_m_vrg_source_busy_2_014_370_AND_NOT_m_cfg__ETC___d3374) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75851, + v__h78970, $signed(32'd2), v_sources_1_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255) + if (NOT_m_vrg_source_busy_3_015_378_AND_NOT_m_cfg__ETC___d3382) begin - v__h76055 = $stime; + v__h79174 = $stime; #0; end - v__h76049 = v__h76055 / 32'd10; + v__h79168 = v__h79174 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255) + if (NOT_m_vrg_source_busy_3_015_378_AND_NOT_m_cfg__ETC___d3382) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76049, + v__h79168, $signed(32'd3), v_sources_2_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263) + if (NOT_m_vrg_source_busy_4_016_386_AND_NOT_m_cfg__ETC___d3390) begin - v__h76253 = $stime; + v__h79372 = $stime; #0; end - v__h76247 = v__h76253 / 32'd10; + v__h79366 = v__h79372 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263) + if (NOT_m_vrg_source_busy_4_016_386_AND_NOT_m_cfg__ETC___d3390) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76247, + v__h79366, $signed(32'd4), v_sources_3_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271) + if (NOT_m_vrg_source_busy_5_017_394_AND_NOT_m_cfg__ETC___d3398) begin - v__h76451 = $stime; + v__h79570 = $stime; #0; end - v__h76445 = v__h76451 / 32'd10; + v__h79564 = v__h79570 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271) + if (NOT_m_vrg_source_busy_5_017_394_AND_NOT_m_cfg__ETC___d3398) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76445, + v__h79564, $signed(32'd5), v_sources_4_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279) + if (NOT_m_vrg_source_busy_6_018_402_AND_NOT_m_cfg__ETC___d3406) begin - v__h76649 = $stime; + v__h79768 = $stime; #0; end - v__h76643 = v__h76649 / 32'd10; + v__h79762 = v__h79768 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279) + if (NOT_m_vrg_source_busy_6_018_402_AND_NOT_m_cfg__ETC___d3406) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76643, + v__h79762, $signed(32'd6), v_sources_5_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287) + if (NOT_m_vrg_source_busy_7_019_410_AND_NOT_m_cfg__ETC___d3414) begin - v__h76847 = $stime; + v__h79966 = $stime; #0; end - v__h76841 = v__h76847 / 32'd10; + v__h79960 = v__h79966 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287) + if (NOT_m_vrg_source_busy_7_019_410_AND_NOT_m_cfg__ETC___d3414) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76841, + v__h79960, $signed(32'd7), v_sources_6_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295) + if (NOT_m_vrg_source_busy_8_020_418_AND_NOT_m_cfg__ETC___d3422) begin - v__h77045 = $stime; + v__h80164 = $stime; #0; end - v__h77039 = v__h77045 / 32'd10; + v__h80158 = v__h80164 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295) + if (NOT_m_vrg_source_busy_8_020_418_AND_NOT_m_cfg__ETC___d3422) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77039, + v__h80158, $signed(32'd8), v_sources_7_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303) + if (NOT_m_vrg_source_busy_9_021_426_AND_NOT_m_cfg__ETC___d3430) begin - v__h77243 = $stime; + v__h80362 = $stime; #0; end - v__h77237 = v__h77243 / 32'd10; + v__h80356 = v__h80362 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303) + if (NOT_m_vrg_source_busy_9_021_426_AND_NOT_m_cfg__ETC___d3430) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77237, + v__h80356, $signed(32'd9), v_sources_8_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311) + if (NOT_m_vrg_source_busy_10_022_434_AND_NOT_m_cfg_ETC___d3438) begin - v__h77441 = $stime; + v__h80560 = $stime; #0; end - v__h77435 = v__h77441 / 32'd10; + v__h80554 = v__h80560 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311) + if (NOT_m_vrg_source_busy_10_022_434_AND_NOT_m_cfg_ETC___d3438) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77435, + v__h80554, $signed(32'd10), v_sources_9_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319) + if (NOT_m_vrg_source_busy_11_023_442_AND_NOT_m_cfg_ETC___d3446) begin - v__h77639 = $stime; + v__h80758 = $stime; #0; end - v__h77633 = v__h77639 / 32'd10; + v__h80752 = v__h80758 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319) + if (NOT_m_vrg_source_busy_11_023_442_AND_NOT_m_cfg_ETC___d3446) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77633, + v__h80752, $signed(32'd11), v_sources_10_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327) + if (NOT_m_vrg_source_busy_12_024_450_AND_NOT_m_cfg_ETC___d3454) begin - v__h77837 = $stime; + v__h80956 = $stime; #0; end - v__h77831 = v__h77837 / 32'd10; + v__h80950 = v__h80956 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327) + if (NOT_m_vrg_source_busy_12_024_450_AND_NOT_m_cfg_ETC___d3454) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77831, + v__h80950, $signed(32'd12), v_sources_11_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335) + if (NOT_m_vrg_source_busy_13_025_458_AND_NOT_m_cfg_ETC___d3462) begin - v__h78035 = $stime; + v__h81154 = $stime; #0; end - v__h78029 = v__h78035 / 32'd10; + v__h81148 = v__h81154 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335) + if (NOT_m_vrg_source_busy_13_025_458_AND_NOT_m_cfg_ETC___d3462) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78029, + v__h81148, $signed(32'd13), v_sources_12_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343) + if (NOT_m_vrg_source_busy_14_026_466_AND_NOT_m_cfg_ETC___d3470) begin - v__h78233 = $stime; + v__h81352 = $stime; #0; end - v__h78227 = v__h78233 / 32'd10; + v__h81346 = v__h81352 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343) + if (NOT_m_vrg_source_busy_14_026_466_AND_NOT_m_cfg_ETC___d3470) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78227, + v__h81346, $signed(32'd14), v_sources_13_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351) + if (NOT_m_vrg_source_busy_15_027_474_AND_NOT_m_cfg_ETC___d3478) begin - v__h78431 = $stime; + v__h81550 = $stime; #0; end - v__h78425 = v__h78431 / 32'd10; + v__h81544 = v__h81550 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351) + if (NOT_m_vrg_source_busy_15_027_474_AND_NOT_m_cfg_ETC___d3478) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78425, + v__h81544, $signed(32'd15), v_sources_14_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359) + if (NOT_m_vrg_source_busy_16_028_482_AND_NOT_m_cfg_ETC___d3486) begin - v__h78629 = $stime; + v__h81748 = $stime; #0; end - v__h78623 = v__h78629 / 32'd10; + v__h81742 = v__h81748 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359) + if (NOT_m_vrg_source_busy_16_028_482_AND_NOT_m_cfg_ETC___d3486) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78623, + v__h81742, $signed(32'd16), v_sources_15_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) begin - v__h6142 = $stime; + v__h8559 = $stime; #0; end - v__h6136 = v__h6142 / 32'd10; + v__h8553 = v__h8559 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h6136); + $display("%0d: PLIC.rl_reset", v__h8553); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) begin - v__h13078 = $stime; + v__h15481 = $stime; #0; end - v__h13072 = v__h13078 / 32'd10; + v__h15475 = v__h15481 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req:", v__h13072); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $display("%0d: PLIC.rl_process_rd_req:", v__h15475); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) begin - v__h13263 = $stime; + v__h15696 = $stime; #0; end - v__h13257 = v__h13263 / 32'd10; + v__h15690 = v__h15696 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h13257); + v__h15690); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("AXI4_Rd_Addr { ", "arid: "); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d112) begin - v__h13461 = $stime; + v__h15924 = $stime; #0; end - v__h13455 = v__h13461 / 32'd10; + v__h15918 = v__h15924 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d112) $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h13455, - addr_offset__h13214[11:2], - v__h13420); + v__h15918, + addr_offset__h15646[11:2], + v__h15883); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d143) begin - v__h13711 = $stime; + v__h16175 = $stime; #0; end - v__h13705 = v__h13711 / 32'd10; + v__h16169 = v__h16175 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d143) $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h13705, - source_id_base__h13628, - v__h13669); + v__h16169, + source_id_base__h16091, + v__h16133); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d317) begin - v__h18184 = $stime; + v__h20649 = $stime; #0; end - v__h18178 = v__h18184 / 32'd10; + v__h20643 = v__h20649 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d317) $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h18178, - source_id_base__h13628, - v__h18142); + v__h20643, + source_id_base__h16091, + v__h20607); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d607) begin - v__h23800 = $stime; + v__h26266 = $stime; #0; end - v__h23794 = v__h23800 / 32'd10; + v__h26260 = v__h26266 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d607) $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h23794, - addr_offset__h13214[16:12], - v__h23759); + v__h26260, + addr_offset__h15646[16:12], + v__h26225); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d813) begin - v__h25973 = $stime; + v__h28442 = $stime; #0; end - v__h25967 = v__h25973 / 32'd10; + v__h28436 = v__h28442 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d813) $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h25967, - addr_offset__h13214[16:12], - v__h25472); + v__h28436, + addr_offset__h15646[16:12], + v__h27941); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825) begin - v__h24054 = $stime; + v__h26522 = $stime; #0; end - v__h24048 = v__h24054 / 32'd10; + v__h26516 = v__h26522 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825) $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h24048, - addr_offset__h13214[16:12]); + v__h26516, + addr_offset__h15646[16:12]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Still servicing interrupt from source %0d", x__h24009); + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825) + $display(" Still servicing interrupt from source %0d", x__h26477); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825) $display(" Trying to claim service for source %0d", - max_id__h23957); + max_id__h26424); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825) $display(" Ignoring."); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) begin - v__h26248 = $stime; + v__h28733 = $stime; #0; end - v__h26242 = v__h26248 / 32'd10; + v__h28727 = v__h28733 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h26242); + v__h28727); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("AXI4_Rd_Addr { ", "arid: "); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + !m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) begin - v__h26461 = $stime; + v__h29034 = $stime; #0; end - v__h26455 = v__h26461 / 32'd10; + v__h29028 = v__h29034 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req", v__h26455); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $display("%0d: PLIC.rl_process_rd_req", v__h29028); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Data { ", "rid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", x__h26359); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", x__h28872); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", rresp__h26201); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d891) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) + $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d891)) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) begin - v__h26735 = $stime; + v__h29518 = $stime; #0; end - v__h26729 = v__h26735 / 32'd10; + v__h29512 = v__h29518 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26729); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $display("%0d: PLIC.rl_process_wr_req", v__h29512); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wdata: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) begin - v__h26959 = $stime; + v__h29772 = $stime; #0; end - v__h26953 = v__h26959 / 32'd10; + v__h29766 = v__h29772 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26953); + v__h29766); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("AXI4_Wr_Addr { ", "awid: "); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("AXI4_Wr_Data { ", "wdata: "); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_data$D_OUT[0]) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_data$D_OUT[0]) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1006) begin - v__h27854 = $stime; + v__h30696 = $stime; #0; end - v__h27848 = v__h27854 / 32'd10; + v__h30690 = v__h30696 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1006) $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27848, - addr_offset__h26920[11:2], - wdata32__h26921); + v__h30690, + addr_offset__h29732[11:2], + wdata32__h29733); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1017) begin - v__h28037 = $stime; + v__h30882 = $stime; #0; end - v__h28031 = v__h28037 / 32'd10; + v__h30876 = v__h30882 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1017) $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28031, - source_id_base__h28137); + v__h30876, + source_id_base__h30983); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2981) begin - v__h67019 = $stime; + v__h69866 = $stime; #0; end - v__h67013 = v__h67019 / 32'd10; + v__h69860 = v__h69866 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2981) $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67013, - addr_offset__h26920[11:7], - source_id_base__h28137, - wdata32__h26921); + v__h69860, + addr_offset__h29732[11:7], + source_id_base__h30983, + wdata32__h29733); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3005) begin - v__h67307 = $stime; + v__h70156 = $stime; #0; end - v__h67301 = v__h67307 / 32'd10; + v__h70150 = v__h70156 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3005) $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67301, - addr_offset__h26920[16:12], - wdata32__h26921); + v__h70150, + addr_offset__h29732[16:12], + wdata32__h29733); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3077) begin - v__h67836 = $stime; + v__h70688 = $stime; #0; end - v__h67830 = v__h67836 / 32'd10; + v__h70682 = v__h70688 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3077) $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67830, - addr_offset__h26920[16:12], - source_id__h67425); + v__h70682, + addr_offset__h29732[16:12], + source_id__h70276); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087) begin - v__h67922 = $stime; + v__h70774 = $stime; #0; end - v__h67916 = v__h67922 / 32'd10; + v__h70768 = v__h70774 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087) $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67916); + v__h70768); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087) $display(" Completion message from target %0d to source %0d", - addr_offset__h26920[16:12], - source_id__h67425); + addr_offset__h29732[16:12], + source_id__h70276); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087) $display(" Ignoring"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) begin - v__h68121 = $stime; + v__h70985 = $stime; #0; end - v__h68115 = v__h68121 / 32'd10; + v__h70979 = v__h70985 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68115); + v__h70979); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("AXI4_Wr_Addr { ", "awid: "); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + !m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("AXI4_Wr_Data { ", "wdata: "); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && - m_slave_xactor_f_wr_data$D_OUT[0]) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && - !m_slave_xactor_f_wr_data$D_OUT[0]) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + !m_slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) begin - v__h68340 = $stime; + v__h71294 = $stime; #0; end - v__h68334 = v__h68340 / 32'd10; + v__h71288 = v__h71294 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68334); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h71288); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wdata: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Resp { ", "bid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_BFlit { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26925); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3132) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) + $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3132)) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h74675 = $stime; + v__h77734 = $stime; #0; end - v__h74669 = v__h74675 / 32'd10; + v__h77728 = v__h77734 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74669, + v__h77728, set_addr_map_addr_base); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h74785 = $stime; + v__h77844 = $stime; #0; end - v__h74779 = v__h74785 / 32'd10; + v__h77838 = v__h77844 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74779, + v__h77838, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) begin - v__h74898 = $stime; + v__h77957 = $stime; #0; end - v__h74892 = v__h74898 / 32'd10; + v__h77951 = v__h77957 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74892, + v__h77951, set_addr_map_addr_base, set_addr_map_addr_lim); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); end // synopsys translate_on endmodule // mkPLIC_16_2_7 diff --git a/src_SSITH_P1/Verilog_RTL/mkRISCV_MBox.v b/src_SSITH_P1/Verilog_RTL/mkRISCV_MBox.v index 570d9b06..89427fb9 100644 --- a/src_SSITH_P1/Verilog_RTL/mkRISCV_MBox.v +++ b/src_SSITH_P1/Verilog_RTL/mkRISCV_MBox.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:40 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkSoC_Map.v b/src_SSITH_P1/Verilog_RTL/mkSoC_Map.v index a1384976..fad8016c 100644 --- a/src_SSITH_P1/Verilog_RTL/mkSoC_Map.v +++ b/src_SSITH_P1/Verilog_RTL/mkSoC_Map.v @@ -1,41 +1,21 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:19 BST 2019 // // // Ports: // Name I/O size props -// m_plic_addr_base O 64 const -// m_plic_addr_size O 64 const -// m_plic_addr_lim O 64 const -// m_near_mem_io_addr_base O 64 const -// m_near_mem_io_addr_size O 64 const -// m_near_mem_io_addr_lim O 64 const -// m_flash_mem_addr_base O 64 const -// m_flash_mem_addr_size O 64 const -// m_flash_mem_addr_lim O 64 const -// m_ethernet_0_addr_base O 64 const -// m_ethernet_0_addr_size O 64 const -// m_ethernet_0_addr_lim O 64 const -// m_dma_0_addr_base O 64 const -// m_dma_0_addr_size O 64 const -// m_dma_0_addr_lim O 64 const -// m_uart16550_0_addr_base O 64 const -// m_uart16550_0_addr_size O 64 const -// m_uart16550_0_addr_lim O 64 const -// m_gpio_0_addr_base O 64 const -// m_gpio_0_addr_size O 64 const -// m_gpio_0_addr_lim O 64 const -// m_boot_rom_addr_base O 64 const -// m_boot_rom_addr_size O 64 const -// m_boot_rom_addr_lim O 64 const -// m_ddr4_0_uncached_addr_base O 64 const -// m_ddr4_0_uncached_addr_size O 64 const -// m_ddr4_0_uncached_addr_lim O 64 const -// m_ddr4_0_cached_addr_base O 64 const -// m_ddr4_0_cached_addr_size O 64 const -// m_ddr4_0_cached_addr_lim O 64 const +// m_plic_addr_range O 128 const +// m_near_mem_io_addr_range O 128 const +// m_flash_mem_addr_range O 128 const +// m_ethernet_0_addr_range O 128 const +// m_dma_0_addr_range O 128 const +// m_uart16550_0_addr_range O 128 const +// m_gpio_0_addr_range O 128 const +// m_boot_rom_addr_range O 128 const +// m_ddr4_0_uncached_addr_range O 128 const +// m_ddr4_0_cached_addr_range O 128 const // m_is_mem_addr O 1 // m_is_IO_addr O 1 // m_is_near_mem_IO_addr O 1 @@ -71,65 +51,25 @@ module mkSoC_Map(CLK, RST_N, - m_plic_addr_base, - - m_plic_addr_size, - - m_plic_addr_lim, - - m_near_mem_io_addr_base, - - m_near_mem_io_addr_size, - - m_near_mem_io_addr_lim, - - m_flash_mem_addr_base, - - m_flash_mem_addr_size, - - m_flash_mem_addr_lim, - - m_ethernet_0_addr_base, - - m_ethernet_0_addr_size, - - m_ethernet_0_addr_lim, - - m_dma_0_addr_base, - - m_dma_0_addr_size, - - m_dma_0_addr_lim, - - m_uart16550_0_addr_base, + m_plic_addr_range, - m_uart16550_0_addr_size, + m_near_mem_io_addr_range, - m_uart16550_0_addr_lim, + m_flash_mem_addr_range, - m_gpio_0_addr_base, + m_ethernet_0_addr_range, - m_gpio_0_addr_size, + m_dma_0_addr_range, - m_gpio_0_addr_lim, + m_uart16550_0_addr_range, - m_boot_rom_addr_base, + m_gpio_0_addr_range, - m_boot_rom_addr_size, + m_boot_rom_addr_range, - m_boot_rom_addr_lim, + m_ddr4_0_uncached_addr_range, - m_ddr4_0_uncached_addr_base, - - m_ddr4_0_uncached_addr_size, - - m_ddr4_0_uncached_addr_lim, - - m_ddr4_0_cached_addr_base, - - m_ddr4_0_cached_addr_size, - - m_ddr4_0_cached_addr_lim, + m_ddr4_0_cached_addr_range, m_is_mem_addr_addr, m_is_mem_addr, @@ -148,95 +88,35 @@ module mkSoC_Map(CLK, input CLK; input RST_N; - // value method m_plic_addr_base - output [63 : 0] m_plic_addr_base; - - // value method m_plic_addr_size - output [63 : 0] m_plic_addr_size; - - // value method m_plic_addr_lim - output [63 : 0] m_plic_addr_lim; - - // value method m_near_mem_io_addr_base - output [63 : 0] m_near_mem_io_addr_base; - - // value method m_near_mem_io_addr_size - output [63 : 0] m_near_mem_io_addr_size; - - // value method m_near_mem_io_addr_lim - output [63 : 0] m_near_mem_io_addr_lim; - - // value method m_flash_mem_addr_base - output [63 : 0] m_flash_mem_addr_base; - - // value method m_flash_mem_addr_size - output [63 : 0] m_flash_mem_addr_size; - - // value method m_flash_mem_addr_lim - output [63 : 0] m_flash_mem_addr_lim; - - // value method m_ethernet_0_addr_base - output [63 : 0] m_ethernet_0_addr_base; - - // value method m_ethernet_0_addr_size - output [63 : 0] m_ethernet_0_addr_size; + // value method m_plic_addr_range + output [127 : 0] m_plic_addr_range; - // value method m_ethernet_0_addr_lim - output [63 : 0] m_ethernet_0_addr_lim; + // value method m_near_mem_io_addr_range + output [127 : 0] m_near_mem_io_addr_range; - // value method m_dma_0_addr_base - output [63 : 0] m_dma_0_addr_base; + // value method m_flash_mem_addr_range + output [127 : 0] m_flash_mem_addr_range; - // value method m_dma_0_addr_size - output [63 : 0] m_dma_0_addr_size; + // value method m_ethernet_0_addr_range + output [127 : 0] m_ethernet_0_addr_range; - // value method m_dma_0_addr_lim - output [63 : 0] m_dma_0_addr_lim; + // value method m_dma_0_addr_range + output [127 : 0] m_dma_0_addr_range; - // value method m_uart16550_0_addr_base - output [63 : 0] m_uart16550_0_addr_base; + // value method m_uart16550_0_addr_range + output [127 : 0] m_uart16550_0_addr_range; - // value method m_uart16550_0_addr_size - output [63 : 0] m_uart16550_0_addr_size; + // value method m_gpio_0_addr_range + output [127 : 0] m_gpio_0_addr_range; - // value method m_uart16550_0_addr_lim - output [63 : 0] m_uart16550_0_addr_lim; + // value method m_boot_rom_addr_range + output [127 : 0] m_boot_rom_addr_range; - // value method m_gpio_0_addr_base - output [63 : 0] m_gpio_0_addr_base; + // value method m_ddr4_0_uncached_addr_range + output [127 : 0] m_ddr4_0_uncached_addr_range; - // value method m_gpio_0_addr_size - output [63 : 0] m_gpio_0_addr_size; - - // value method m_gpio_0_addr_lim - output [63 : 0] m_gpio_0_addr_lim; - - // value method m_boot_rom_addr_base - output [63 : 0] m_boot_rom_addr_base; - - // value method m_boot_rom_addr_size - output [63 : 0] m_boot_rom_addr_size; - - // value method m_boot_rom_addr_lim - output [63 : 0] m_boot_rom_addr_lim; - - // value method m_ddr4_0_uncached_addr_base - output [63 : 0] m_ddr4_0_uncached_addr_base; - - // value method m_ddr4_0_uncached_addr_size - output [63 : 0] m_ddr4_0_uncached_addr_size; - - // value method m_ddr4_0_uncached_addr_lim - output [63 : 0] m_ddr4_0_uncached_addr_lim; - - // value method m_ddr4_0_cached_addr_base - output [63 : 0] m_ddr4_0_cached_addr_base; - - // value method m_ddr4_0_cached_addr_size - output [63 : 0] m_ddr4_0_cached_addr_size; - - // value method m_ddr4_0_cached_addr_lim - output [63 : 0] m_ddr4_0_cached_addr_lim; + // value method m_ddr4_0_cached_addr_range + output [127 : 0] m_ddr4_0_cached_addr_range; // value method m_is_mem_addr input [63 : 0] m_is_mem_addr_addr; @@ -260,133 +140,52 @@ module mkSoC_Map(CLK, output [63 : 0] m_nmivec_reset_value; // signals for module outputs - wire [63 : 0] m_boot_rom_addr_base, - m_boot_rom_addr_lim, - m_boot_rom_addr_size, - m_ddr4_0_cached_addr_base, - m_ddr4_0_cached_addr_lim, - m_ddr4_0_cached_addr_size, - m_ddr4_0_uncached_addr_base, - m_ddr4_0_uncached_addr_lim, - m_ddr4_0_uncached_addr_size, - m_dma_0_addr_base, - m_dma_0_addr_lim, - m_dma_0_addr_size, - m_ethernet_0_addr_base, - m_ethernet_0_addr_lim, - m_ethernet_0_addr_size, - m_flash_mem_addr_base, - m_flash_mem_addr_lim, - m_flash_mem_addr_size, - m_gpio_0_addr_base, - m_gpio_0_addr_lim, - m_gpio_0_addr_size, - m_mtvec_reset_value, - m_near_mem_io_addr_base, - m_near_mem_io_addr_lim, - m_near_mem_io_addr_size, - m_nmivec_reset_value, - m_pc_reset_value, - m_plic_addr_base, - m_plic_addr_lim, - m_plic_addr_size, - m_uart16550_0_addr_base, - m_uart16550_0_addr_lim, - m_uart16550_0_addr_size; + wire [127 : 0] m_boot_rom_addr_range, + m_ddr4_0_cached_addr_range, + m_ddr4_0_uncached_addr_range, + m_dma_0_addr_range, + m_ethernet_0_addr_range, + m_flash_mem_addr_range, + m_gpio_0_addr_range, + m_near_mem_io_addr_range, + m_plic_addr_range, + m_uart16550_0_addr_range; + wire [63 : 0] m_mtvec_reset_value, m_nmivec_reset_value, m_pc_reset_value; wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; // remaining internal signals wire m_is_IO_addr_addr_ULT_0x70000000___d35; - // value method m_plic_addr_base - assign m_plic_addr_base = 64'h000000000C000000 ; - - // value method m_plic_addr_size - assign m_plic_addr_size = 64'h0000000000400000 ; - - // value method m_plic_addr_lim - assign m_plic_addr_lim = 64'd205520896 ; - - // value method m_near_mem_io_addr_base - assign m_near_mem_io_addr_base = 64'h0000000010000000 ; - - // value method m_near_mem_io_addr_size - assign m_near_mem_io_addr_size = 64'h0000000000010000 ; - - // value method m_near_mem_io_addr_lim - assign m_near_mem_io_addr_lim = 64'd268500992 ; - - // value method m_flash_mem_addr_base - assign m_flash_mem_addr_base = 64'h0000000040000000 ; - - // value method m_flash_mem_addr_size - assign m_flash_mem_addr_size = 64'h0000000008000000 ; - - // value method m_flash_mem_addr_lim - assign m_flash_mem_addr_lim = 64'd1207959552 ; - - // value method m_ethernet_0_addr_base - assign m_ethernet_0_addr_base = 64'h0000000062100000 ; - - // value method m_ethernet_0_addr_size - assign m_ethernet_0_addr_size = 64'h0000000000040000 ; - - // value method m_ethernet_0_addr_lim - assign m_ethernet_0_addr_lim = 64'd1645477888 ; - - // value method m_dma_0_addr_base - assign m_dma_0_addr_base = 64'h0000000062200000 ; - - // value method m_dma_0_addr_size - assign m_dma_0_addr_size = 64'h0000000000010000 ; - - // value method m_dma_0_addr_lim - assign m_dma_0_addr_lim = 64'd1646329856 ; - - // value method m_uart16550_0_addr_base - assign m_uart16550_0_addr_base = 64'h0000000062300000 ; - - // value method m_uart16550_0_addr_size - assign m_uart16550_0_addr_size = 64'h0000000000001000 ; - - // value method m_uart16550_0_addr_lim - assign m_uart16550_0_addr_lim = 64'd1647316992 ; - - // value method m_gpio_0_addr_base - assign m_gpio_0_addr_base = 64'h000000006FFF0000 ; - - // value method m_gpio_0_addr_size - assign m_gpio_0_addr_size = 64'h0000000000010000 ; - - // value method m_gpio_0_addr_lim - assign m_gpio_0_addr_lim = 64'd1879048192 ; + // value method m_plic_addr_range + assign m_plic_addr_range = 128'h000000000C0000000000000000400000 ; - // value method m_boot_rom_addr_base - assign m_boot_rom_addr_base = 64'h0000000070000000 ; + // value method m_near_mem_io_addr_range + assign m_near_mem_io_addr_range = 128'h00000000100000000000000000010000 ; - // value method m_boot_rom_addr_size - assign m_boot_rom_addr_size = 64'h0000000000001000 ; + // value method m_flash_mem_addr_range + assign m_flash_mem_addr_range = 128'h00000000400000000000000008000000 ; - // value method m_boot_rom_addr_lim - assign m_boot_rom_addr_lim = 64'd1879052288 ; + // value method m_ethernet_0_addr_range + assign m_ethernet_0_addr_range = 128'h00000000621000000000000000040000 ; - // value method m_ddr4_0_uncached_addr_base - assign m_ddr4_0_uncached_addr_base = 64'h0000000080000000 ; + // value method m_dma_0_addr_range + assign m_dma_0_addr_range = 128'h00000000622000000000000000010000 ; - // value method m_ddr4_0_uncached_addr_size - assign m_ddr4_0_uncached_addr_size = 64'h0000000040000000 ; + // value method m_uart16550_0_addr_range + assign m_uart16550_0_addr_range = 128'h00000000623000000000000000001000 ; - // value method m_ddr4_0_uncached_addr_lim - assign m_ddr4_0_uncached_addr_lim = 64'h00000000C0000000 ; + // value method m_gpio_0_addr_range + assign m_gpio_0_addr_range = 128'h000000006FFF00000000000000010000 ; - // value method m_ddr4_0_cached_addr_base - assign m_ddr4_0_cached_addr_base = 64'h00000000C0000000 ; + // value method m_boot_rom_addr_range + assign m_boot_rom_addr_range = 128'h00000000700000000000000000001000 ; - // value method m_ddr4_0_cached_addr_size - assign m_ddr4_0_cached_addr_size = 64'h0000000040000000 ; + // value method m_ddr4_0_uncached_addr_range + assign m_ddr4_0_uncached_addr_range = + 128'h00000000800000000000000040000000 ; - // value method m_ddr4_0_cached_addr_lim - assign m_ddr4_0_cached_addr_lim = 64'h0000000100000000 ; + // value method m_ddr4_0_cached_addr_range + assign m_ddr4_0_cached_addr_range = 128'h00000000C00000000000000040000000 ; // value method m_is_mem_addr assign m_is_mem_addr = diff --git a/src_SSITH_P1/Verilog_RTL/mkTV_Encode.v b/src_SSITH_P1/Verilog_RTL/mkTV_Encode.v index 1371994a..786b6910 100644 --- a/src_SSITH_P1/Verilog_RTL/mkTV_Encode.v +++ b/src_SSITH_P1/Verilog_RTL/mkTV_Encode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:11 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/Verilog_RTL/mkTV_Xactor.v b/src_SSITH_P1/Verilog_RTL/mkTV_Xactor.v index 4ce5fb1c..4c550bcf 100644 --- a/src_SSITH_P1/Verilog_RTL/mkTV_Xactor.v +++ b/src_SSITH_P1/Verilog_RTL/mkTV_Xactor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:19:01 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/src_BSV/Giraffe.defines b/src_SSITH_P1/src_BSV/Giraffe.defines index cf370507..92111f11 100644 --- a/src_SSITH_P1/src_BSV/Giraffe.defines +++ b/src_SSITH_P1/src_BSV/Giraffe.defines @@ -1,2 +1,3 @@ `define TLM_PRM_Giraffe 4, 64, 64, 8, 0 +`define AXI4_PARAMS_Giraffe 4, 64, 64, 0, 0, 0, 0, 0 diff --git a/src_SSITH_P1/src_BSV/Giraffe_IFC.bsv b/src_SSITH_P1/src_BSV/Giraffe_IFC.bsv index 34d25031..d3bf3444 100644 --- a/src_SSITH_P1/src_BSV/Giraffe_IFC.bsv +++ b/src_SSITH_P1/src_BSV/Giraffe_IFC.bsv @@ -1,12 +1,23 @@ +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package Giraffe_IFC; -import Axi ::*; -import Axi4 ::*; +import AXI4 ::*; import Bus ::*; import Connectable ::*; -`include "TLM.defines" `include "Giraffe.defines" (* always_ready, always_enabled *) @@ -107,10 +118,10 @@ instance Connectable#(DMI_IFC, DMI_Master_IFC); endinstance interface Core_IFC; - interface Axi4LRdWrMaster#(`TLM_PRM_Giraffe) master0; - interface Axi4LRdWrMaster#(`TLM_PRM_Giraffe) master1; - interface Axi4LRdWrMaster#(`TLM_PRM_Giraffe) master2; - interface Axi4LRdWrMaster#(`TLM_PRM_Giraffe) master3; + interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master0; + interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master1; + interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master2; + interface AXI4_Master_Synth#(`AXI4_PARAMS_Giraffe) master3; (* always_ready, always_enabled *) (* prefix = "", result = "unused0" *) @@ -134,10 +145,10 @@ interface Core_IFC; endinterface interface Platform_IFC; - interface Axi4LRdWrSlave#(`TLM_PRM_Giraffe) slave0; - interface Axi4LRdWrSlave#(`TLM_PRM_Giraffe) slave1; - interface Axi4LRdWrSlave#(`TLM_PRM_Giraffe) slave2; - interface Axi4LRdWrSlave#(`TLM_PRM_Giraffe) slave3; + interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave0; + interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave1; + interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave2; + interface AXI4_Slave_Synth#(`AXI4_PARAMS_Giraffe) slave3; (* always_ready, always_enabled *) method Bit#(1) interrupt0; diff --git a/src_SSITH_P1/src_BSV/P1_Core.bsv b/src_SSITH_P1/src_BSV/P1_Core.bsv index bae5386d..7709fc02 100644 --- a/src_SSITH_P1/src_BSV/P1_Core.bsv +++ b/src_SSITH_P1/src_BSV/P1_Core.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved. +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package P1_Core; // ================================================================ @@ -44,8 +57,7 @@ import Core :: *; import PLIC :: *; // for PLIC_Source_IFC type which is exposed at P2_Core interface // Main Fabric -import AXI4_Types :: *; -import AXI4_Fabric :: *; +import AXI4 :: *; import Fabric_Defs :: *; `ifdef INCLUDE_TANDEM_VERIF @@ -68,10 +80,14 @@ interface P1_Core_IFC; // Core CPU interfaces // CPU IMem to Fabric master interface - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master0; + interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) master0; // CPU DMem (incl. I/O) to Fabric master interface - interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master1; + interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) master1; // External interrupt sources (* always_ready, always_enabled, prefix="" *) diff --git a/src_SSITH_P1/src_BSV/SoC_Map.bsv b/src_SSITH_P1/src_BSV/SoC_Map.bsv index d4802c2e..84d6e7f0 100644 --- a/src_SSITH_P1/src_BSV/SoC_Map.bsv +++ b/src_SSITH_P1/src_BSV/SoC_Map.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2013-2019 Bluespec, Inc. All Rights Reserved +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package SoC_Map; // ================================================================ @@ -36,7 +49,7 @@ export irq_num_uart16550_0; // ================================================================ // Bluespec library imports -// None +import Routable :: *; // ================================================================ // Project imports @@ -53,13 +66,8 @@ endfunction // Interface and module for the address map interface SoC_Map_IFC; - (* always_ready *) method Fabric_Addr m_plic_addr_base; - (* always_ready *) method Fabric_Addr m_plic_addr_size; - (* always_ready *) method Fabric_Addr m_plic_addr_lim; - - (* always_ready *) method Fabric_Addr m_near_mem_io_addr_base; - (* always_ready *) method Fabric_Addr m_near_mem_io_addr_size; - (* always_ready *) method Fabric_Addr m_near_mem_io_addr_lim; + (* always_ready *) method Range#(Wd_Addr) m_plic_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_near_mem_io_addr_range; /* REMOVED? (* always_ready *) method Fabric_Addr m_pcie_ecam_slave_bridge_addr_base; @@ -67,9 +75,7 @@ interface SoC_Map_IFC; (* always_ready *) method Fabric_Addr m_pcie_ecam_slave_bridge_addr_lim; */ - (* always_ready *) method Fabric_Addr m_flash_mem_addr_base; - (* always_ready *) method Fabric_Addr m_flash_mem_addr_size; - (* always_ready *) method Fabric_Addr m_flash_mem_addr_lim; + (* always_ready *) method Range#(Wd_Addr) m_flash_mem_addr_range; /* REMOVED? (* always_ready *) method Fabric_Addr m_pcie_block_registers_addr_base; @@ -77,33 +83,13 @@ interface SoC_Map_IFC; (* always_ready *) method Fabric_Addr m_pcie_block_registers_addr_lim; */ - (* always_ready *) method Fabric_Addr m_ethernet_0_addr_base; - (* always_ready *) method Fabric_Addr m_ethernet_0_addr_size; - (* always_ready *) method Fabric_Addr m_ethernet_0_addr_lim; - - (* always_ready *) method Fabric_Addr m_dma_0_addr_base; - (* always_ready *) method Fabric_Addr m_dma_0_addr_size; - (* always_ready *) method Fabric_Addr m_dma_0_addr_lim; - - (* always_ready *) method Fabric_Addr m_uart16550_0_addr_base; - (* always_ready *) method Fabric_Addr m_uart16550_0_addr_size; - (* always_ready *) method Fabric_Addr m_uart16550_0_addr_lim; - - (* always_ready *) method Fabric_Addr m_gpio_0_addr_base; - (* always_ready *) method Fabric_Addr m_gpio_0_addr_size; - (* always_ready *) method Fabric_Addr m_gpio_0_addr_lim; - - (* always_ready *) method Fabric_Addr m_boot_rom_addr_base; - (* always_ready *) method Fabric_Addr m_boot_rom_addr_size; - (* always_ready *) method Fabric_Addr m_boot_rom_addr_lim; - - (* always_ready *) method Fabric_Addr m_ddr4_0_uncached_addr_base; - (* always_ready *) method Fabric_Addr m_ddr4_0_uncached_addr_size; - (* always_ready *) method Fabric_Addr m_ddr4_0_uncached_addr_lim; - - (* always_ready *) method Fabric_Addr m_ddr4_0_cached_addr_base; - (* always_ready *) method Fabric_Addr m_ddr4_0_cached_addr_size; - (* always_ready *) method Fabric_Addr m_ddr4_0_cached_addr_lim; + (* always_ready *) method Range#(Wd_Addr) m_ethernet_0_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_dma_0_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_uart16550_0_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_gpio_0_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_boot_rom_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_ddr4_0_uncached_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_ddr4_0_cached_addr_range; (* always_ready *) method Bool m_is_mem_addr (Fabric_Addr addr); @@ -127,24 +113,18 @@ module mkSoC_Map (SoC_Map_IFC); // ---------------------------------------------------------------- // PLIC - Fabric_Addr plic_addr_base = 'h_0C00_0000; - Fabric_Addr plic_addr_size = 'h_0040_0000; // 4M - Fabric_Addr plic_addr_lim = plic_addr_base + plic_addr_size; - - function Bool fn_is_plic_addr (Fabric_Addr addr); - return ((plic_addr_base <= addr) && (addr < plic_addr_lim)); - endfunction + let plic_addr_range = Range { + base: 'h_0C00_0000, + size: 'h_0040_0000 // 4M + }; // ---------------------------------------------------------------- // Near_Mem_IO (CLINT) - Fabric_Addr near_mem_io_addr_base = 'h_1000_0000; - Fabric_Addr near_mem_io_addr_size = 'h_0001_0000; // 64K - Fabric_Addr near_mem_io_addr_lim = near_mem_io_addr_base + near_mem_io_addr_size; - - function Bool fn_is_near_mem_io_addr (Fabric_Addr addr); - return ((near_mem_io_addr_base <= addr) && (addr < near_mem_io_addr_lim)); - endfunction + let near_mem_io_addr_range = Range { + base: 'h_1000_0000, + size: 'h_0001_0000 // 64K + }; // ---------------------------------------------------------------- // PCIE_ECAM_SLAVE_BRIDGE @@ -163,13 +143,10 @@ module mkSoC_Map (SoC_Map_IFC); // ---------------------------------------------------------------- // Flash Mem - Fabric_Addr flash_mem_addr_base = 'h_4000_0000; - Fabric_Addr flash_mem_addr_size = 'h_0800_0000; // 128M - Fabric_Addr flash_mem_addr_lim = flash_mem_addr_base + flash_mem_addr_size; - - function Bool fn_is_flash_mem_addr (Fabric_Addr addr); - return ((flash_mem_addr_base <= addr) && (addr < flash_mem_addr_lim)); - endfunction + let flash_mem_addr_range = Range { + base: 'h_4000_0000, + size: 'h_0800_0000 // 128M + }; // ---------------------------------------------------------------- // PCIe Block Registers @@ -188,89 +165,68 @@ module mkSoC_Map (SoC_Map_IFC); // ---------------------------------------------------------------- // Ethernet 0 - Fabric_Addr ethernet_0_addr_base = 'h_6210_0000; - Fabric_Addr ethernet_0_addr_size = 'h_0004_0000; // 256K - Fabric_Addr ethernet_0_addr_lim = ethernet_0_addr_base + ethernet_0_addr_size; - - function Bool fn_is_ethernet_0_addr (Fabric_Addr addr); - return ((ethernet_0_addr_base <= addr) && (addr < ethernet_0_addr_lim)); - endfunction + let ethernet_0_addr_range = Range { + base: 'h_6210_0000, + size: 'h_0004_0000 // 256K + }; // ---------------------------------------------------------------- // DMA 0 - Fabric_Addr dma_0_addr_base = 'h_6220_0000; - Fabric_Addr dma_0_addr_size = 'h_0001_0000; // 64K - Fabric_Addr dma_0_addr_lim = dma_0_addr_base + dma_0_addr_size; - - function Bool fn_is_dma_0_addr (Fabric_Addr addr); - return ((dma_0_addr_base <= addr) && (addr < dma_0_addr_lim)); - endfunction + let dma_0_addr_range = Range { + base: 'h_6220_0000, + size: 'h_0001_0000 // 64K + }; // ---------------------------------------------------------------- // UART 0 - Fabric_Addr uart16550_0_addr_base = 'h_6230_0000; - Fabric_Addr uart16550_0_addr_size = 'h_0000_1000; // 4K - Fabric_Addr uart16550_0_addr_lim = uart16550_0_addr_base + uart16550_0_addr_size; - - function Bool fn_is_uart16550_0_addr (Fabric_Addr addr); - return ((uart16550_0_addr_base <= addr) && (addr < uart16550_0_addr_lim)); - endfunction + let uart16550_0_addr_range = Range { + base: 'h_6230_0000, + size: 'h_0000_1000 // 4K + }; // ---------------------------------------------------------------- // GPIO 0 - Fabric_Addr gpio_0_addr_base = 'h_6FFF_0000; - Fabric_Addr gpio_0_addr_size = 'h_0001_0000; // 64K - Fabric_Addr gpio_0_addr_lim = gpio_0_addr_base + gpio_0_addr_size; - - function Bool fn_is_gpio_0_addr (Fabric_Addr addr); - return ((gpio_0_addr_base <= addr) && (addr < gpio_0_addr_lim)); - endfunction + let gpio_0_addr_range = Range { + base: 'h_6FFF_0000, + size: 'h_0001_0000 // 64K + }; // ---------------------------------------------------------------- // Boot ROM - Fabric_Addr boot_rom_addr_base = 'h_7000_0000; - Fabric_Addr boot_rom_addr_size = 'h_0000_1000; // 4K - Fabric_Addr boot_rom_addr_lim = boot_rom_addr_base + boot_rom_addr_size; - - function Bool fn_is_boot_rom_addr (Fabric_Addr addr); - return ((boot_rom_addr_base <= addr) && (addr < boot_rom_addr_lim)); - endfunction + let boot_rom_addr_range = Range { + base: 'h_7000_0000, + size: 'h_0000_1000 // 4K + }; // ---------------------------------------------------------------- // DDR memory 0 uncached - Fabric_Addr ddr4_0_uncached_addr_base = 'h_8000_0000; - Fabric_Addr ddr4_0_uncached_addr_size = 'h_4000_0000; // 1G - Fabric_Addr ddr4_0_uncached_addr_lim = ddr4_0_uncached_addr_base + ddr4_0_uncached_addr_size; - - function Bool fn_is_ddr4_0_uncached_addr (Fabric_Addr addr); - return ((ddr4_0_uncached_addr_base <= addr) && (addr < ddr4_0_uncached_addr_lim)); - endfunction + let ddr4_0_uncached_addr_range = Range { + base: 'h_8000_0000, + size: 'h_4000_0000 // 1G + }; // ---------------------------------------------------------------- // DDR memory 0 cached - Fabric_Addr ddr4_0_cached_addr_base = 'h_C000_0000; - Fabric_Addr ddr4_0_cached_addr_size = 'h_4000_0000; // 1G - Fabric_Addr ddr4_0_cached_addr_lim = ddr4_0_cached_addr_base + ddr4_0_cached_addr_size; - - function Bool fn_is_ddr4_0_cached_addr (Fabric_Addr addr); - return ((ddr4_0_cached_addr_base <= addr) && (addr < ddr4_0_cached_addr_lim)); - endfunction + let ddr4_0_cached_addr_range = Range { + base: 'h_C000_0000, + size: 'h_4000_0000 // 1G + }; // ---------------------------------------------------------------- - function fn_is_flash_regs_addr = addr_function('h6240_0000, 'h1000); - function fn_is_uart1_addr = addr_function('h6230_0000, 'h1000); - function fn_is_i2c_addr = addr_function('h6231_0000, 'h1000); - function fn_is_spi_addr = addr_function('h6232_0000, 'h1000); - function fn_is_uart2_addr = addr_function('h6236_0000, 'h1000); - function fn_is_gpio1_addr = addr_function('h6233_0000, 'h1000); - function fn_is_gpio2_addr = addr_function('h6237_0000, 'h1000); + let flash_addr_range = Range{base: 'h6240_0000, size: 'h1000}; + let uart1_addr_range = Range{base: 'h6230_0000, size: 'h1000}; + let i2c_addr_range = Range{base: 'h6231_0000, size: 'h1000}; + let spi_addr_range = Range{base: 'h6232_0000, size: 'h1000}; + let uart2_addr_range = Range{base: 'h6236_0000, size: 'h1000}; + let gpio1_addr_range = Range{base: 'h6233_0000, size: 'h1000}; + let gpio2_addr_range = Range{base: 'h6237_0000, size: 'h1000}; // ---------------------------------------------------------------- // Memory address predicate @@ -278,8 +234,7 @@ module mkSoC_Map (SoC_Map_IFC); // (Caches needs this information to cache these addresses.) function Bool fn_is_mem_addr (Fabric_Addr addr); - return ( fn_is_ddr4_0_cached_addr (addr) - ); + return inRange (ddr4_0_cached_addr_range, addr); endfunction // ---------------------------------------------------------------- @@ -288,44 +243,39 @@ module mkSoC_Map (SoC_Map_IFC); // (Caches needs this information to avoid cacheing these addresses.) function Bool fn_is_IO_addr (Fabric_Addr addr); - return ( fn_is_plic_addr (addr) - || fn_is_near_mem_io_addr (addr) + return ( inRange (plic_addr_range, addr) + || inRange (near_mem_io_addr_range, addr) // || fn_is_pcie_ecam_slave_bridge_addr (addr) - || fn_is_flash_mem_addr (addr) + || inRange (flash_mem_addr_range, addr) // || fn_is_pcie_block_registers_addr (addr) - || fn_is_ethernet_0_addr (addr) - || fn_is_dma_0_addr (addr) - || fn_is_uart16550_0_addr (addr) - || fn_is_gpio_0_addr (addr) - || fn_is_boot_rom_addr (addr) - || fn_is_ddr4_0_uncached_addr (addr) - || fn_is_flash_regs_addr (addr) - || fn_is_uart1_addr (addr) - || fn_is_i2c_addr (addr) - || fn_is_spi_addr (addr) - || fn_is_uart2_addr (addr) - || fn_is_gpio1_addr (addr) - || fn_is_gpio2_addr (addr) - ); + || inRange (ethernet_0_addr_range, addr) + || inRange (dma_0_addr_range, addr) + || inRange (uart16550_0_addr_range, addr) + || inRange (gpio_0_addr_range, addr) + || inRange (boot_rom_addr_range, addr) + || inRange (ddr4_0_uncached_addr_range, addr) + || inRange (flash_addr_range, addr) + || inRange (uart1_addr_range, addr) + || inRange (i2c_addr_range, addr) + || inRange (spi_addr_range, addr) + || inRange (uart2_addr_range, addr) + || inRange (gpio1_addr_range, addr) + || inRange (gpio2_addr_range, addr) + ); endfunction // ---------------------------------------------------------------- // PC, MTVEC and NMIVEC reset values - Bit #(64) pc_reset_value = boot_rom_addr_base; + Bit #(64) pc_reset_value = rangeBase(boot_rom_addr_range); Bit #(64) mtvec_reset_value = 'h1000; // TODO Bit #(64) nmivec_reset_value = ?; // TODO // ================================================================ // INTERFACE - method Fabric_Addr m_plic_addr_base = plic_addr_base; - method Fabric_Addr m_plic_addr_size = plic_addr_size; - method Fabric_Addr m_plic_addr_lim = plic_addr_lim; - - method Fabric_Addr m_near_mem_io_addr_base = near_mem_io_addr_base; - method Fabric_Addr m_near_mem_io_addr_size = near_mem_io_addr_size; - method Fabric_Addr m_near_mem_io_addr_lim = near_mem_io_addr_lim; + method Range#(Wd_Addr) m_plic_addr_range = plic_addr_range; + method Range#(Wd_Addr) m_near_mem_io_addr_range = near_mem_io_addr_range; /* REMOVED? method Fabric_Addr m_pcie_ecam_slave_bridge_addr_base = pcie_ecam_slave_bridge_addr_base; @@ -333,9 +283,7 @@ module mkSoC_Map (SoC_Map_IFC); method Fabric_Addr m_pcie_ecam_slave_bridge_addr_lim = pcie_ecam_slave_bridge_addr_lim; */ - method Fabric_Addr m_flash_mem_addr_base = flash_mem_addr_base; - method Fabric_Addr m_flash_mem_addr_size = flash_mem_addr_size; - method Fabric_Addr m_flash_mem_addr_lim = flash_mem_addr_lim; + method Range#(Wd_Addr) m_flash_mem_addr_range = flash_mem_addr_range; /* REMOVED? method Fabric_Addr m_pcie_block_registers_addr_base = pcie_block_registers_addr_base; @@ -343,39 +291,19 @@ module mkSoC_Map (SoC_Map_IFC); method Fabric_Addr m_pcie_block_registers_addr_lim = pcie_block_registers_addr_lim; */ - method Fabric_Addr m_ethernet_0_addr_base = ethernet_0_addr_base; - method Fabric_Addr m_ethernet_0_addr_size = ethernet_0_addr_size; - method Fabric_Addr m_ethernet_0_addr_lim = ethernet_0_addr_lim; - - method Fabric_Addr m_dma_0_addr_base = dma_0_addr_base; - method Fabric_Addr m_dma_0_addr_size = dma_0_addr_size; - method Fabric_Addr m_dma_0_addr_lim = dma_0_addr_lim; - - method Fabric_Addr m_uart16550_0_addr_base = uart16550_0_addr_base; - method Fabric_Addr m_uart16550_0_addr_size = uart16550_0_addr_size; - method Fabric_Addr m_uart16550_0_addr_lim = uart16550_0_addr_lim; - - method Fabric_Addr m_gpio_0_addr_base = gpio_0_addr_base; - method Fabric_Addr m_gpio_0_addr_size = gpio_0_addr_size; - method Fabric_Addr m_gpio_0_addr_lim = gpio_0_addr_lim; - - method Fabric_Addr m_boot_rom_addr_base = boot_rom_addr_base; - method Fabric_Addr m_boot_rom_addr_size = boot_rom_addr_size; - method Fabric_Addr m_boot_rom_addr_lim = boot_rom_addr_lim; - - method Fabric_Addr m_ddr4_0_uncached_addr_base = ddr4_0_uncached_addr_base; - method Fabric_Addr m_ddr4_0_uncached_addr_size = ddr4_0_uncached_addr_size; - method Fabric_Addr m_ddr4_0_uncached_addr_lim = ddr4_0_uncached_addr_lim; - - method Fabric_Addr m_ddr4_0_cached_addr_base = ddr4_0_cached_addr_base; - method Fabric_Addr m_ddr4_0_cached_addr_size = ddr4_0_cached_addr_size; - method Fabric_Addr m_ddr4_0_cached_addr_lim = ddr4_0_cached_addr_lim; + method Range#(Wd_Addr) m_ethernet_0_addr_range = ethernet_0_addr_range; + method Range#(Wd_Addr) m_dma_0_addr_range = dma_0_addr_range; + method Range#(Wd_Addr) m_uart16550_0_addr_range = uart16550_0_addr_range; + method Range#(Wd_Addr) m_gpio_0_addr_range = gpio_0_addr_range; + method Range#(Wd_Addr) m_boot_rom_addr_range = boot_rom_addr_range; + method Range#(Wd_Addr) m_ddr4_0_uncached_addr_range = ddr4_0_uncached_addr_range; + method Range#(Wd_Addr) m_ddr4_0_cached_addr_range = ddr4_0_cached_addr_range; method Bool m_is_mem_addr (Fabric_Addr addr) = fn_is_mem_addr (addr); method Bool m_is_IO_addr (Fabric_Addr addr) = fn_is_IO_addr (addr); - method Bool m_is_near_mem_IO_addr (Fabric_Addr addr) = fn_is_near_mem_io_addr (addr); + method Bool m_is_near_mem_IO_addr (Fabric_Addr addr) = inRange(near_mem_io_addr_range, addr); method Bit #(64) m_pc_reset_value = pc_reset_value; method Bit #(64) m_mtvec_reset_value = mtvec_reset_value; diff --git a/src_SSITH_P1/xilinx_ip/component.xml b/src_SSITH_P1/xilinx_ip/component.xml index a1eba723..85f2de4d 100644 --- a/src_SSITH_P1/xilinx_ip/component.xml +++ b/src_SSITH_P1/xilinx_ip/component.xml @@ -860,7 +860,7 @@ out - 3 + 4 0 @@ -1134,7 +1134,7 @@ in - 3 + 4 0 @@ -1200,7 +1200,7 @@ out - 3 + 4 0 @@ -1398,7 +1398,7 @@ in - 3 + 4 0 @@ -1500,7 +1500,7 @@ out - 3 + 4 0 @@ -1774,7 +1774,7 @@ in - 3 + 4 0 @@ -1840,7 +1840,7 @@ out - 3 + 4 0 @@ -2038,7 +2038,7 @@ in - 3 + 4 0 @@ -2370,6 +2370,10 @@ hdl/SyncResetA.v verilogSource + + hdl/RevertReg.v + verilogSource + hdl/mkCPU.v verilogSource @@ -2407,19 +2411,19 @@ verilogSource - hdl/mkFabric_2x1.v + hdl/mkGPR_RegFile.v verilogSource - hdl/mkGPR_RegFile.v + hdl/mkJtagTap.v verilogSource - hdl/mkJtagTap.v + hdl/mkMMU_DCache.v verilogSource - hdl/mkMMU_Cache.v + hdl/mkMMU_ICache.v verilogSource @@ -2427,7 +2431,7 @@ verilogSource - hdl/mkNear_Mem_IO.v + hdl/mkNear_Mem_IO_AXI4.v verilogSource @@ -2459,12 +2463,6 @@ CHECKSUM_367b68f0 xil_defaultlib - - hdl/mkFabric_2x3.v - verilogSource - CHECKSUM_11c31333 - xil_defaultlib - hdl/mkNear_Mem_IO_AXI4.v verilogSource @@ -2490,173 +2488,6 @@ xil_defaultlib - - xilinx_anylanguagebehavioralsimulation_view_fileset - - hdl/BRAM2.v - verilogSource - - - hdl/FIFO1.v - verilogSource - - - hdl/FIFO2.v - verilogSource - - - hdl/FIFO20.v - verilogSource - - - hdl/MakeClock.v - verilogSource - - - hdl/RegFile.v - verilogSource - - - hdl/SizedFIFO.v - verilogSource - - - hdl/SizedFIFO0.v - verilogSource - - - hdl/SyncFIFOLevel.v - verilogSource - - - hdl/SyncHandshake.v - verilogSource - - - hdl/SyncResetA.v - verilogSource - - - hdl/mkCPU.v - verilogSource - - - hdl/mkCSR_MIE.v - verilogSource - - - hdl/mkCSR_MIP.v - verilogSource - - - hdl/mkCSR_RegFile.v - verilogSource - - - hdl/mkCore.v - verilogSource - - - hdl/mkDM_Abstract_Commands.v - verilogSource - - - hdl/mkDM_Run_Control.v - verilogSource - - - hdl/mkDM_System_Bus.v - verilogSource - - - hdl/mkDebug_Module.v - verilogSource - - - hdl/mkFabric_2x1.v - verilogSource - - - hdl/mkGPR_RegFile.v - verilogSource - - - hdl/mkJtagTap.v - verilogSource - - - hdl/mkMMU_Cache.v - verilogSource - - - hdl/mkNear_Mem.v - verilogSource - - - hdl/mkNear_Mem_IO.v - verilogSource - - - hdl/mkRISCV_MBox.v - verilogSource - - - hdl/mkSoC_Map.v - verilogSource - - - hdl/mkP1_Core.v - verilogSource - - - hdl/mkDM_GPR_Tap.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/mkDM_Mem_Tap.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/mkDM_CSR_Tap.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/mkFabric_2x3.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/mkNear_Mem_IO_AXI4.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/mkPLIC_16_2_7.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/mkTV_Encode.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - - hdl/mkTV_Xactor.v - verilogSource - USED_IN_ipstatic - xil_defaultlib - - xilinx_xpgui_view_fileset diff --git a/src_SSITH_P1/xilinx_ip/hdl/RevertReg.v b/src_SSITH_P1/xilinx_ip/hdl/RevertReg.v new file mode 100644 index 00000000..df45aa6d --- /dev/null +++ b/src_SSITH_P1/xilinx_ip/hdl/RevertReg.v @@ -0,0 +1,41 @@ + +// Copyright (c) 2000-2009 Bluespec, Inc. + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// $Revision$ +// $Date$ + +`ifdef BSV_ASSIGNMENT_DELAY +`else +`define BSV_ASSIGNMENT_DELAY +`endif + +module RevertReg(CLK, Q_OUT, D_IN, EN); + + parameter width = 1; + parameter init = { width {1'b0} } ; + + input CLK; + input EN; + input [width - 1 : 0] D_IN; + output [width - 1 : 0] Q_OUT; + + assign Q_OUT = init; +endmodule diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkCPU.v b/src_SSITH_P1/xilinx_ip/hdl/mkCPU.v index cd2a3606..d3c4eaee 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkCPU.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkCPU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:52 BST 2019 // // // Ports: @@ -9,61 +9,61 @@ // RDY_hart0_server_reset_request_put O 1 reg // hart0_server_reset_response_get O 1 reg // RDY_hart0_server_reset_response_get O 1 reg +// imem_master_awid O 5 +// imem_master_awaddr O 64 +// imem_master_awlen O 8 +// imem_master_awsize O 3 +// imem_master_awburst O 2 +// imem_master_awlock O 1 +// imem_master_awcache O 4 +// imem_master_awprot O 3 +// imem_master_awqos O 4 +// imem_master_awregion O 4 // imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg +// imem_master_wdata O 64 +// imem_master_wstrb O 8 +// imem_master_wlast O 1 // imem_master_wvalid O 1 -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg // imem_master_bready O 1 +// imem_master_arid O 5 +// imem_master_araddr O 64 +// imem_master_arlen O 8 +// imem_master_arsize O 3 +// imem_master_arburst O 2 +// imem_master_arlock O 1 +// imem_master_arcache O 4 +// imem_master_arprot O 3 +// imem_master_arqos O 4 +// imem_master_arregion O 4 // imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg // imem_master_rready O 1 +// dmem_master_awid O 4 +// dmem_master_awaddr O 64 +// dmem_master_awlen O 8 +// dmem_master_awsize O 3 +// dmem_master_awburst O 2 +// dmem_master_awlock O 1 +// dmem_master_awcache O 4 +// dmem_master_awprot O 3 +// dmem_master_awqos O 4 +// dmem_master_awregion O 4 // dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg +// dmem_master_wdata O 64 +// dmem_master_wstrb O 8 +// dmem_master_wlast O 1 // dmem_master_wvalid O 1 -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg // dmem_master_bready O 1 +// dmem_master_arid O 4 +// dmem_master_araddr O 64 +// dmem_master_arlen O 8 +// dmem_master_arsize O 3 +// dmem_master_arburst O 2 +// dmem_master_arlock O 1 +// dmem_master_arcache O 4 +// dmem_master_arprot O 3 +// dmem_master_arqos O 4 +// dmem_master_arregion O 4 // dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg // dmem_master_rready O 1 // RDY_set_verbosity O 1 const // trace_data_out_get O 234 reg @@ -83,26 +83,22 @@ // hart0_server_reset_request_put I 1 reg // imem_master_awready I 1 // imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg +// imem_master_bid I 5 +// imem_master_bresp I 2 // imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg +// imem_master_rid I 5 +// imem_master_rdata I 64 +// imem_master_rresp I 2 +// imem_master_rlast I 1 // dmem_master_awready I 1 // dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg +// dmem_master_bid I 4 +// dmem_master_bresp I 2 // dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg +// dmem_master_rid I 4 +// dmem_master_rdata I 64 +// dmem_master_rresp I 2 +// dmem_master_rlast I 1 // m_external_interrupt_req_set_not_clear I 1 reg // s_external_interrupt_req_set_not_clear I 1 reg // software_interrupt_req_set_not_clear I 1 reg @@ -115,6 +111,10 @@ // hart0_gpr_mem_server_request_put I 38 reg // hart0_csr_mem_server_request_put I 45 reg // EN_hart0_server_reset_request_put I 1 +// imem_master_bvalid I 1 +// imem_master_rvalid I 1 +// dmem_master_bvalid I 1 +// dmem_master_rvalid I 1 // EN_set_verbosity I 1 // EN_hart0_server_run_halt_request_put I 1 // EN_hart0_put_other_req_put I 1 @@ -127,16 +127,246 @@ // EN_hart0_csr_mem_server_response_get I 1 // // Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> imem_master_rready -// (imem_master_awready, -// imem_master_wready, -// dmem_master_awready, -// dmem_master_wready) -> dmem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arid +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_araddr +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arlen +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arsize +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arburst +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arlock +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arcache +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arprot +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arqos +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arregion +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_aruser +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> imem_master_arvalid +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arid +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_araddr +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arlen +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arsize +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arburst +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arlock +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arcache +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arprot +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arqos +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arregion +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_aruser +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// imem_master_rvalid, +// dmem_master_rvalid) -> dmem_master_arvalid // // @@ -164,8 +394,6 @@ module mkCPU(CLK, hart0_server_reset_response_get, RDY_hart0_server_reset_response_get, - imem_master_awvalid, - imem_master_awid, imem_master_awaddr, @@ -186,9 +414,9 @@ module mkCPU(CLK, imem_master_awregion, - imem_master_awready, + imem_master_awvalid, - imem_master_wvalid, + imem_master_awready, imem_master_wdata, @@ -196,16 +424,16 @@ module mkCPU(CLK, imem_master_wlast, + imem_master_wvalid, + imem_master_wready, - imem_master_bvalid, imem_master_bid, imem_master_bresp, + imem_master_bvalid, imem_master_bready, - imem_master_arvalid, - imem_master_arid, imem_master_araddr, @@ -226,18 +454,18 @@ module mkCPU(CLK, imem_master_arregion, + imem_master_arvalid, + imem_master_arready, - imem_master_rvalid, imem_master_rid, imem_master_rdata, imem_master_rresp, imem_master_rlast, + imem_master_rvalid, imem_master_rready, - dmem_master_awvalid, - dmem_master_awid, dmem_master_awaddr, @@ -258,9 +486,9 @@ module mkCPU(CLK, dmem_master_awregion, - dmem_master_awready, + dmem_master_awvalid, - dmem_master_wvalid, + dmem_master_awready, dmem_master_wdata, @@ -268,16 +496,16 @@ module mkCPU(CLK, dmem_master_wlast, + dmem_master_wvalid, + dmem_master_wready, - dmem_master_bvalid, dmem_master_bid, dmem_master_bresp, + dmem_master_bvalid, dmem_master_bready, - dmem_master_arvalid, - dmem_master_arid, dmem_master_araddr, @@ -298,13 +526,15 @@ module mkCPU(CLK, dmem_master_arregion, + dmem_master_arvalid, + dmem_master_arready, - dmem_master_rvalid, dmem_master_rid, dmem_master_rdata, dmem_master_rresp, dmem_master_rlast, + dmem_master_rvalid, dmem_master_rready, @@ -367,226 +597,226 @@ module mkCPU(CLK, output hart0_server_reset_response_get; output RDY_hart0_server_reset_response_get; - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; + // value method imem_master_aw_awid + output [4 : 0] imem_master_awid; - // value method imem_master_m_awaddr + // value method imem_master_aw_awaddr output [63 : 0] imem_master_awaddr; - // value method imem_master_m_awlen + // value method imem_master_aw_awlen output [7 : 0] imem_master_awlen; - // value method imem_master_m_awsize + // value method imem_master_aw_awsize output [2 : 0] imem_master_awsize; - // value method imem_master_m_awburst + // value method imem_master_aw_awburst output [1 : 0] imem_master_awburst; - // value method imem_master_m_awlock + // value method imem_master_aw_awlock output imem_master_awlock; - // value method imem_master_m_awcache + // value method imem_master_aw_awcache output [3 : 0] imem_master_awcache; - // value method imem_master_m_awprot + // value method imem_master_aw_awprot output [2 : 0] imem_master_awprot; - // value method imem_master_m_awqos + // value method imem_master_aw_awqos output [3 : 0] imem_master_awqos; - // value method imem_master_m_awregion + // value method imem_master_aw_awregion output [3 : 0] imem_master_awregion; - // value method imem_master_m_awuser + // value method imem_master_aw_awuser - // action method imem_master_m_awready - input imem_master_awready; + // value method imem_master_aw_awvalid + output imem_master_awvalid; - // value method imem_master_m_wvalid - output imem_master_wvalid; + // action method imem_master_aw_awready + input imem_master_awready; - // value method imem_master_m_wdata + // value method imem_master_w_wdata output [63 : 0] imem_master_wdata; - // value method imem_master_m_wstrb + // value method imem_master_w_wstrb output [7 : 0] imem_master_wstrb; - // value method imem_master_m_wlast + // value method imem_master_w_wlast output imem_master_wlast; - // value method imem_master_m_wuser + // value method imem_master_w_wuser + + // value method imem_master_w_wvalid + output imem_master_wvalid; - // action method imem_master_m_wready + // action method imem_master_w_wready input imem_master_wready; - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; + // action method imem_master_b_bflit + input [4 : 0] imem_master_bid; input [1 : 0] imem_master_bresp; + input imem_master_bvalid; - // value method imem_master_m_bready + // value method imem_master_b_bready output imem_master_bready; - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; + // value method imem_master_ar_arid + output [4 : 0] imem_master_arid; - // value method imem_master_m_araddr + // value method imem_master_ar_araddr output [63 : 0] imem_master_araddr; - // value method imem_master_m_arlen + // value method imem_master_ar_arlen output [7 : 0] imem_master_arlen; - // value method imem_master_m_arsize + // value method imem_master_ar_arsize output [2 : 0] imem_master_arsize; - // value method imem_master_m_arburst + // value method imem_master_ar_arburst output [1 : 0] imem_master_arburst; - // value method imem_master_m_arlock + // value method imem_master_ar_arlock output imem_master_arlock; - // value method imem_master_m_arcache + // value method imem_master_ar_arcache output [3 : 0] imem_master_arcache; - // value method imem_master_m_arprot + // value method imem_master_ar_arprot output [2 : 0] imem_master_arprot; - // value method imem_master_m_arqos + // value method imem_master_ar_arqos output [3 : 0] imem_master_arqos; - // value method imem_master_m_arregion + // value method imem_master_ar_arregion output [3 : 0] imem_master_arregion; - // value method imem_master_m_aruser + // value method imem_master_ar_aruser + + // value method imem_master_ar_arvalid + output imem_master_arvalid; - // action method imem_master_m_arready + // action method imem_master_ar_arready input imem_master_arready; - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; + // action method imem_master_r_rflit + input [4 : 0] imem_master_rid; input [63 : 0] imem_master_rdata; input [1 : 0] imem_master_rresp; input imem_master_rlast; + input imem_master_rvalid; - // value method imem_master_m_rready + // value method imem_master_r_rready output imem_master_rready; - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid + // value method dmem_master_aw_awid output [3 : 0] dmem_master_awid; - // value method dmem_master_m_awaddr + // value method dmem_master_aw_awaddr output [63 : 0] dmem_master_awaddr; - // value method dmem_master_m_awlen + // value method dmem_master_aw_awlen output [7 : 0] dmem_master_awlen; - // value method dmem_master_m_awsize + // value method dmem_master_aw_awsize output [2 : 0] dmem_master_awsize; - // value method dmem_master_m_awburst + // value method dmem_master_aw_awburst output [1 : 0] dmem_master_awburst; - // value method dmem_master_m_awlock + // value method dmem_master_aw_awlock output dmem_master_awlock; - // value method dmem_master_m_awcache + // value method dmem_master_aw_awcache output [3 : 0] dmem_master_awcache; - // value method dmem_master_m_awprot + // value method dmem_master_aw_awprot output [2 : 0] dmem_master_awprot; - // value method dmem_master_m_awqos + // value method dmem_master_aw_awqos output [3 : 0] dmem_master_awqos; - // value method dmem_master_m_awregion + // value method dmem_master_aw_awregion output [3 : 0] dmem_master_awregion; - // value method dmem_master_m_awuser + // value method dmem_master_aw_awuser - // action method dmem_master_m_awready - input dmem_master_awready; + // value method dmem_master_aw_awvalid + output dmem_master_awvalid; - // value method dmem_master_m_wvalid - output dmem_master_wvalid; + // action method dmem_master_aw_awready + input dmem_master_awready; - // value method dmem_master_m_wdata + // value method dmem_master_w_wdata output [63 : 0] dmem_master_wdata; - // value method dmem_master_m_wstrb + // value method dmem_master_w_wstrb output [7 : 0] dmem_master_wstrb; - // value method dmem_master_m_wlast + // value method dmem_master_w_wlast output dmem_master_wlast; - // value method dmem_master_m_wuser + // value method dmem_master_w_wuser + + // value method dmem_master_w_wvalid + output dmem_master_wvalid; - // action method dmem_master_m_wready + // action method dmem_master_w_wready input dmem_master_wready; - // action method dmem_master_m_bvalid - input dmem_master_bvalid; + // action method dmem_master_b_bflit input [3 : 0] dmem_master_bid; input [1 : 0] dmem_master_bresp; + input dmem_master_bvalid; - // value method dmem_master_m_bready + // value method dmem_master_b_bready output dmem_master_bready; - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid + // value method dmem_master_ar_arid output [3 : 0] dmem_master_arid; - // value method dmem_master_m_araddr + // value method dmem_master_ar_araddr output [63 : 0] dmem_master_araddr; - // value method dmem_master_m_arlen + // value method dmem_master_ar_arlen output [7 : 0] dmem_master_arlen; - // value method dmem_master_m_arsize + // value method dmem_master_ar_arsize output [2 : 0] dmem_master_arsize; - // value method dmem_master_m_arburst + // value method dmem_master_ar_arburst output [1 : 0] dmem_master_arburst; - // value method dmem_master_m_arlock + // value method dmem_master_ar_arlock output dmem_master_arlock; - // value method dmem_master_m_arcache + // value method dmem_master_ar_arcache output [3 : 0] dmem_master_arcache; - // value method dmem_master_m_arprot + // value method dmem_master_ar_arprot output [2 : 0] dmem_master_arprot; - // value method dmem_master_m_arqos + // value method dmem_master_ar_arqos output [3 : 0] dmem_master_arqos; - // value method dmem_master_m_arregion + // value method dmem_master_ar_arregion output [3 : 0] dmem_master_arregion; - // value method dmem_master_m_aruser + // value method dmem_master_ar_aruser + + // value method dmem_master_ar_arvalid + output dmem_master_arvalid; - // action method dmem_master_m_arready + // action method dmem_master_ar_arready input dmem_master_arready; - // action method dmem_master_m_rvalid - input dmem_master_rvalid; + // action method dmem_master_r_rflit input [3 : 0] dmem_master_rid; input [63 : 0] dmem_master_rdata; input [1 : 0] dmem_master_rresp; input dmem_master_rlast; + input dmem_master_rvalid; - // value method dmem_master_m_rready + // value method dmem_master_r_rready output dmem_master_rready; // action method m_external_interrupt_req @@ -666,6 +896,7 @@ module mkCPU(CLK, imem_master_arlen, imem_master_awlen, imem_master_wstrb; + wire [4 : 0] imem_master_arid, imem_master_awid; wire [3 : 0] dmem_master_arcache, dmem_master_arid, dmem_master_arqos, @@ -675,11 +906,9 @@ module mkCPU(CLK, dmem_master_awqos, dmem_master_awregion, imem_master_arcache, - imem_master_arid, imem_master_arqos, imem_master_arregion, imem_master_awcache, - imem_master_awid, imem_master_awqos, imem_master_awregion; wire [2 : 0] dmem_master_arprot, @@ -822,6 +1051,21 @@ module mkCPU(CLK, reg rg_stop_req; wire rg_stop_req$D_IN, rg_stop_req$EN; + // register rg_trap_info + reg [67 : 0] rg_trap_info; + wire [67 : 0] rg_trap_info$D_IN; + wire rg_trap_info$EN; + + // register rg_trap_instr + reg [31 : 0] rg_trap_instr; + wire [31 : 0] rg_trap_instr$D_IN; + wire rg_trap_instr$EN; + + // register rg_trap_trace_data + reg [233 : 0] rg_trap_trace_data; + wire [233 : 0] rg_trap_trace_data$D_IN; + wire rg_trap_trace_data$EN; + // register stage1_rg_full reg stage1_rg_full; reg stage1_rg_full$D_IN; @@ -1033,6 +1277,10 @@ module mkCPU(CLK, near_mem$imem_master_wstrb, near_mem$server_fence_request_put; wire [6 : 0] near_mem$dmem_req_amo_funct7; + wire [4 : 0] near_mem$imem_master_arid, + near_mem$imem_master_awid, + near_mem$imem_master_bid, + near_mem$imem_master_rid; wire [3 : 0] near_mem$dmem_exc_code, near_mem$dmem_master_arcache, near_mem$dmem_master_arid, @@ -1046,15 +1294,11 @@ module mkCPU(CLK, near_mem$dmem_master_rid, near_mem$imem_exc_code, near_mem$imem_master_arcache, - near_mem$imem_master_arid, near_mem$imem_master_arqos, near_mem$imem_master_arregion, near_mem$imem_master_awcache, - near_mem$imem_master_awid, near_mem$imem_master_awqos, - near_mem$imem_master_awregion, - near_mem$imem_master_bid, - near_mem$imem_master_rid; + near_mem$imem_master_awregion; wire [2 : 0] near_mem$dmem_master_arprot, near_mem$dmem_master_arsize, near_mem$dmem_master_awprot, @@ -1222,17 +1466,18 @@ module mkCPU(CLK, CAN_FIRE_RL_rl_stage1_trap, CAN_FIRE_RL_rl_stage1_xRET, CAN_FIRE_RL_rl_stage2_nonpipe, + CAN_FIRE_RL_rl_trap, CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode, CAN_FIRE_RL_rl_trap_fetch, CAN_FIRE_RL_stage1_rl_reset, CAN_FIRE_RL_stage2_rl_reset_begin, CAN_FIRE_RL_stage2_rl_reset_end, CAN_FIRE_RL_stage3_rl_reset, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, + CAN_FIRE_dmem_master_ar_arready, + CAN_FIRE_dmem_master_aw_awready, + CAN_FIRE_dmem_master_b_bflit, + CAN_FIRE_dmem_master_r_rflit, + CAN_FIRE_dmem_master_w_wready, CAN_FIRE_hart0_csr_mem_server_request_put, CAN_FIRE_hart0_csr_mem_server_response_get, CAN_FIRE_hart0_gpr_mem_server_request_put, @@ -1242,11 +1487,11 @@ module mkCPU(CLK, CAN_FIRE_hart0_server_reset_response_get, CAN_FIRE_hart0_server_run_halt_request_put, CAN_FIRE_hart0_server_run_halt_response_get, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, + CAN_FIRE_imem_master_ar_arready, + CAN_FIRE_imem_master_aw_awready, + CAN_FIRE_imem_master_b_bflit, + CAN_FIRE_imem_master_r_rflit, + CAN_FIRE_imem_master_w_wready, CAN_FIRE_m_external_interrupt_req, CAN_FIRE_nmi_req, CAN_FIRE_s_external_interrupt_req, @@ -1290,17 +1535,18 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_trap, WILL_FIRE_RL_rl_stage1_xRET, WILL_FIRE_RL_rl_stage2_nonpipe, + WILL_FIRE_RL_rl_trap, WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode, WILL_FIRE_RL_rl_trap_fetch, WILL_FIRE_RL_stage1_rl_reset, WILL_FIRE_RL_stage2_rl_reset_begin, WILL_FIRE_RL_stage2_rl_reset_end, WILL_FIRE_RL_stage3_rl_reset, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, + WILL_FIRE_dmem_master_ar_arready, + WILL_FIRE_dmem_master_aw_awready, + WILL_FIRE_dmem_master_b_bflit, + WILL_FIRE_dmem_master_r_rflit, + WILL_FIRE_dmem_master_w_wready, WILL_FIRE_hart0_csr_mem_server_request_put, WILL_FIRE_hart0_csr_mem_server_response_get, WILL_FIRE_hart0_gpr_mem_server_request_put, @@ -1310,11 +1556,11 @@ module mkCPU(CLK, WILL_FIRE_hart0_server_reset_response_get, WILL_FIRE_hart0_server_run_halt_request_put, WILL_FIRE_hart0_server_run_halt_response_get, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, + WILL_FIRE_imem_master_ar_arready, + WILL_FIRE_imem_master_aw_awready, + WILL_FIRE_imem_master_b_bflit, + WILL_FIRE_imem_master_r_rflit, + WILL_FIRE_imem_master_w_wready, WILL_FIRE_m_external_interrupt_req, WILL_FIRE_nmi_req, WILL_FIRE_s_external_interrupt_req, @@ -1338,7 +1584,7 @@ module mkCPU(CLK, MUX_near_mem$imem_req_2__VAL_2, MUX_near_mem$imem_req_2__VAL_5, MUX_near_mem$imem_req_2__VAL_7; - wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_2, + wire [3 : 0] MUX_csr_regfile$csr_trap_actions_5__VAL_1, MUX_rg_state$write_1__VAL_1, MUX_rg_state$write_1__VAL_2, MUX_rg_state$write_1__VAL_3; @@ -1346,6 +1592,7 @@ module mkCPU(CLK, wire MUX_csr_regfile$mav_csr_write_1__SEL_1, MUX_csr_regfile$mav_csr_write_1__SEL_2, MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1, + MUX_csr_regfile$write_dpc_1__SEL_2, MUX_f_run_halt_rsps$enq_1__SEL_1, MUX_f_trace_data$enq_1__SEL_1, MUX_f_trace_data$enq_1__SEL_3, @@ -1353,85 +1600,79 @@ module mkCPU(CLK, MUX_gpr_regfile$write_rd_1__SEL_1, MUX_imem_rg_f3$write_1__SEL_1, MUX_imem_rg_f3$write_1__SEL_2, + MUX_imem_rg_f3$write_1__SEL_3, MUX_imem_rg_mstatus_MXR$write_1__SEL_4, MUX_imem_rg_pc$write_1__SEL_4, MUX_near_mem$imem_req_1__SEL_6, MUX_rg_cur_priv$write_1__SEL_2, MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_10, - MUX_rg_state$write_1__SEL_11, - MUX_rg_state$write_1__SEL_12, - MUX_rg_state$write_1__SEL_13, MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3, MUX_rg_state$write_1__SEL_4, - MUX_rg_state$write_1__SEL_6, - MUX_rg_state$write_1__SEL_7, - MUX_rg_state$write_1__SEL_8, - MUX_rg_state$write_1__SEL_9, MUX_rg_step_count$write_1__PSEL_1, MUX_rg_step_count$write_1__SEL_3, MUX_stage1_rg_full$write_1__VAL_10, MUX_stage2_rg_full$write_1__VAL_3; // remaining internal signals - reg [63 : 0] x_out_data_to_stage2_trace_data_word3__h17728; + reg [63 : 0] x_out_data_to_stage2_trace_data_word3__h17634; reg [31 : 0] CASE_stage2_rg_stage2_BITS_337_TO_335_0_stage2_ETC__q20, - CASE_theResult__437_BITS_6_TO_0_0b10011_rd_val_ETC__q18, + CASE_theResult__320_BITS_6_TO_0_0b10011_rd_val_ETC__q18, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1027, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942, - _theResult_____1_fst__h13643, - rs1_val__h20813, - x__h18327, - x__h18596, - x_out_bypass_rd_val__h6908, - x_out_data_to_stage2_addr__h12532, - x_out_data_to_stage2_val1__h12533, - x_out_data_to_stage3_rd_val__h6557; - reg [4 : 0] x_out_bypass_rd__h6907, - x_out_data_to_stage2_trace_data_rd__h17725, - x_out_data_to_stage3_rd__h6556; + _theResult_____1_fst__h13549, + rs1_val__h20863, + x__h18233, + x__h18502, + x_out_bypass_rd_val__h6814, + x_out_data_to_stage2_addr__h12438, + x_out_data_to_stage2_val1__h12439, + x_out_data_to_stage3_rd_val__h6463; + reg [4 : 0] x_out_bypass_rd__h6813, + x_out_data_to_stage2_trace_data_rd__h17631, + x_out_data_to_stage3_rd__h6462; reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q5, - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12, - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14, - CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13, - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15, - CASE_theResult__437_BITS_31_TO_20_0b0_CASE_rg__ETC__q6, - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19, + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12, + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14, + CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13, + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15, + CASE_theResult__320_BITS_31_TO_20_0b0_CASE_rg__ETC__q6, + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d731, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d750, - alu_outputs_exc_code__h13199; - reg [2 : 0] CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16, + alu_outputs_exc_code__h13105; + reg [2 : 0] CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16, IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831; reg [1 : 0] CASE_stage2_rg_stage2_BITS_337_TO_335_0_2_1_IF_ETC__q1, CASE_stage2_rg_stage2_BITS_337_TO_335_0_2_1_IF_ETC__q2; - reg CASE_theResult__437_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11, - CASE_theResult__437_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9, - CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8, - CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10, + reg CASE_theResult__320_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11, + CASE_theResult__320_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9, + CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8, + CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634, IF_stage2_rg_stage2_4_BITS_337_TO_335_5_EQ_1_7_ETC___d138, IF_stage2_rg_stage2_4_BITS_337_TO_335_5_EQ_1_7_ETC___d147; wire [233 : 0] IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d1240; - wire [127 : 0] csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1478; - wire [63 : 0] _theResult____h27350, - alu_outputs___1_trace_data_word3__h17603, - alu_outputs___1_trace_data_word3__h17622, - cpi__h27352, - cpifrac__h27353, - delta_CPI_cycles__h27348, - delta_CPI_instrs___1__h27385, - delta_CPI_instrs__h27349, - trace_data_word3__h27067, - x__h27351, - x_word3__h19995, - x_word3__h20591; + wire [127 : 0] csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1486; + wire [63 : 0] _theResult____h27400, + alu_outputs___1_trace_data_word3__h17509, + alu_outputs___1_trace_data_word3__h17528, + cpi__h27402, + cpifrac__h27403, + delta_CPI_cycles__h27398, + delta_CPI_instrs___1__h27435, + delta_CPI_instrs__h27399, + trace_data_word3__h27117, + x__h27401, + x_word3__h20017, + x_word3__h20641; wire [31 : 0] IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1221, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d943, IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875, - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1367, + IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1375, IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d443, IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d445, IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d447, @@ -1452,119 +1693,119 @@ module mkCPU(CLK, IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d465, IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d466, SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d884, - _theResult_____1_fst__h13636, - _theResult_____1_fst__h13671, - _theResult____h12797, - _theResult____h4437, - _theResult___fst__h7235, - _theResult___fst__h7263, - _theResult___snd__h14769, - alu_outputs___1_addr__h12657, - alu_outputs___1_addr__h12678, - alu_outputs___1_addr__h12704, - alu_outputs___1_val1__h13160, - alu_outputs___1_val1__h13181, - branch_target__h12635, - data_to_stage2_addr__h12523, - eaddr__h12887, - eaddr__h12907, - fall_through_pc__h12486, - instr___1__h7068, - instr__h10415, - instr__h10587, - instr__h10760, - instr__h10953, - instr__h11146, - instr__h11263, - instr__h11441, - instr__h11560, - instr__h11655, - instr__h11791, - instr__h11927, - instr__h12063, - instr__h12401, - instr__h4435, - instr__h7335, - instr__h7480, - instr__h7672, - instr__h7867, - instr__h8096, - instr__h8439, - instr__h8829, - instr__h8945, - instr__h9010, - instr__h9327, - instr__h9665, - instr__h9849, - instr__h9978, - instr_out___1__h7205, - instr_out___1__h7237, - instr_out___1__h7265, - next_pc___1__h14311, - next_pc__h14309, - output_stage2___1_bypass_rd_val__h6896, - rd_val___1__h13624, - rd_val___1__h13632, - rd_val___1__h13639, - rd_val___1__h13646, - rd_val___1__h13653, - rd_val___1__h13660, - rd_val__h12443, - rd_val__h12836, - rd_val__h12853, - rd_val__h12869, - rd_val__h14665, - rd_val__h14717, - rd_val__h14739, - rd_val__h7020, - rs1_val__h20224, - rs1_val_bypassed__h4445, - rs2_val__h12631, - trap_info_tval__h14148, - val__h12445, - val__h7022, - value__h14199, - x__h18419, - x__h21266, - x__h21274, - x_out_data_to_stage2_instr__h12529, - x_out_data_to_stage2_val2__h12534, - x_out_next_pc__h12499, - y__h21114; + _theResult_____1_fst__h13542, + _theResult_____1_fst__h13577, + _theResult____h12703, + _theResult____h4320, + _theResult___fst__h7141, + _theResult___fst__h7169, + _theResult___snd__h14675, + alu_outputs___1_addr__h12563, + alu_outputs___1_addr__h12584, + alu_outputs___1_addr__h12610, + alu_outputs___1_val1__h13066, + alu_outputs___1_val1__h13087, + branch_target__h12541, + data_to_stage2_addr__h12429, + eaddr__h12793, + eaddr__h12813, + fall_through_pc__h12392, + instr___1__h6974, + instr__h10321, + instr__h10493, + instr__h10666, + instr__h10859, + instr__h11052, + instr__h11169, + instr__h11347, + instr__h11466, + instr__h11561, + instr__h11697, + instr__h11833, + instr__h11969, + instr__h12307, + instr__h4318, + instr__h7241, + instr__h7386, + instr__h7578, + instr__h7773, + instr__h8002, + instr__h8345, + instr__h8735, + instr__h8851, + instr__h8916, + instr__h9233, + instr__h9571, + instr__h9755, + instr__h9884, + instr_out___1__h7111, + instr_out___1__h7143, + instr_out___1__h7171, + next_pc___1__h14217, + next_pc__h14215, + output_stage2___1_bypass_rd_val__h6802, + rd_val___1__h13530, + rd_val___1__h13538, + rd_val___1__h13545, + rd_val___1__h13552, + rd_val___1__h13559, + rd_val___1__h13566, + rd_val__h12349, + rd_val__h12742, + rd_val__h12759, + rd_val__h12775, + rd_val__h14571, + rd_val__h14623, + rd_val__h14645, + rd_val__h6926, + rs1_val__h20274, + rs1_val_bypassed__h4328, + rs2_val__h12537, + trap_info_tval__h14054, + val__h12351, + val__h6928, + value__h14105, + x__h18325, + x__h21316, + x__h21324, + x_out_data_to_stage2_instr__h12435, + x_out_data_to_stage2_val2__h12440, + x_out_next_pc__h12405, + y__h21164; wire [20 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294, - theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q4; - wire [19 : 0] imm20__h9717; + theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q4; + wire [19 : 0] imm20__h9623; wire [12 : 0] SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323, - theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q3; - wire [11 : 0] imm12__h10213, - imm12__h10428, - imm12__h10624, - imm12__h10969, - imm12__h7336, - imm12__h7673, - imm12__h9589, - offset__h8043, - theResult__437_BITS_31_TO_20__q17, - theResult__437_BITS_31_TO_25_CONCAT_theResult__ETC__q7; - wire [9 : 0] nzimm10__h10211, nzimm10__h10426; - wire [8 : 0] offset__h8954; - wire [7 : 0] offset__h7106; - wire [6 : 0] offset__h7615; - wire [5 : 0] imm6__h9587; - wire [4 : 0] offset_BITS_4_TO_0___h7604, - offset_BITS_4_TO_0___h8035, - rd__h7675, - rs1__h7674, - shamt__h12793, - td1_rd__h22143, - trace_data_rd__h27064, - x_out_data_to_stage2_rd__h12531; + theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q3; + wire [11 : 0] imm12__h10119, + imm12__h10334, + imm12__h10530, + imm12__h10875, + imm12__h7242, + imm12__h7579, + imm12__h9495, + offset__h7949, + theResult__320_BITS_31_TO_20__q17, + theResult__320_BITS_31_TO_25_CONCAT_theResult__ETC__q7; + wire [9 : 0] nzimm10__h10117, nzimm10__h10332; + wire [8 : 0] offset__h8860; + wire [7 : 0] offset__h7012; + wire [6 : 0] offset__h7521; + wire [5 : 0] imm6__h9493; + wire [4 : 0] offset_BITS_4_TO_0___h7510, + offset_BITS_4_TO_0___h7941, + rd__h7581, + rs1__h7580, + shamt__h12699, + td1_rd__h22193, + trace_data_rd__h27114, + x_out_data_to_stage2_rd__h12437; wire [3 : 0] IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d696, IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752, IF_rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_E_ETC___d729, - alu_outputs___1_exc_code__h13156, - cur_verbosity__h3142, - x_out_trap_info_exc_code__h14151; + alu_outputs___1_exc_code__h13062, + cur_verbosity__h2930, + x_out_trap_info_exc_code__h14057; wire [1 : 0] IF_NOT_near_mem_dmem_valid__15_34_OR_NOT_near__ETC___d182, IF_near_mem_dmem_valid__15_THEN_IF_near_mem_dm_ETC___d118, IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124, @@ -1591,11 +1832,11 @@ module mkCPU(CLK, NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41, NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1191, NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1262, - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1321, - NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1319, + NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1329, + NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1327, NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d818, NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d855, - NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1491, + NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1499, NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_ETC___d211, NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_ETC___d216, NOT_near_mem_imem_valid_02_OR_NOT_near_mem_ime_ETC___d1124, @@ -1613,7 +1854,7 @@ module mkCPU(CLK, _0_OR_0_OR_near_mem_imem_exc__91_OR_IF_IF_NOT_n_ETC___d1284, csr_regfile_csr_mip_read__089_EQ_rg_prev_mip_090___d1091, csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1116, - csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1458, + csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1466, csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d308, csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d314, near_mem_RDY_server_reset_request_put__038_AND_ETC___d1050, @@ -1640,12 +1881,11 @@ module mkCPU(CLK, near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d642, near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691, rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_EQ_0_ETC___d727, - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326, - rg_state_2_EQ_4_083_AND_NOT_stage3_rg_full_4_5_ETC___d1299, - rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1474, + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334, + rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1482, rg_state_2_EQ_4_083_AND_stage3_rg_full_4_OR_NO_ETC___d1154, - rg_state_2_EQ_5_428_OR_rg_state_2_EQ_4_083_AND_ETC___d1437, - rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1469, + rg_state_2_EQ_7_436_OR_rg_state_2_EQ_4_083_AND_ETC___d1445, + rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1477, stage1_rg_full_00_AND_near_mem_imem_valid_AND__ETC___d1087, stage1_rg_full_00_AND_near_mem_imem_valid_AND__ETC___d1110, stage1_rg_full_00_AND_near_mem_imem_valid_AND__ETC___d1129, @@ -1665,212 +1905,212 @@ module mkCPU(CLK, assign WILL_FIRE_hart0_server_reset_response_get = EN_hart0_server_reset_response_get ; - // value method imem_master_m_awvalid - assign imem_master_awvalid = near_mem$imem_master_awvalid ; - - // value method imem_master_m_awid + // value method imem_master_aw_awid assign imem_master_awid = near_mem$imem_master_awid ; - // value method imem_master_m_awaddr + // value method imem_master_aw_awaddr assign imem_master_awaddr = near_mem$imem_master_awaddr ; - // value method imem_master_m_awlen + // value method imem_master_aw_awlen assign imem_master_awlen = near_mem$imem_master_awlen ; - // value method imem_master_m_awsize + // value method imem_master_aw_awsize assign imem_master_awsize = near_mem$imem_master_awsize ; - // value method imem_master_m_awburst + // value method imem_master_aw_awburst assign imem_master_awburst = near_mem$imem_master_awburst ; - // value method imem_master_m_awlock + // value method imem_master_aw_awlock assign imem_master_awlock = near_mem$imem_master_awlock ; - // value method imem_master_m_awcache + // value method imem_master_aw_awcache assign imem_master_awcache = near_mem$imem_master_awcache ; - // value method imem_master_m_awprot + // value method imem_master_aw_awprot assign imem_master_awprot = near_mem$imem_master_awprot ; - // value method imem_master_m_awqos + // value method imem_master_aw_awqos assign imem_master_awqos = near_mem$imem_master_awqos ; - // value method imem_master_m_awregion + // value method imem_master_aw_awregion assign imem_master_awregion = near_mem$imem_master_awregion ; - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; + // value method imem_master_aw_awvalid + assign imem_master_awvalid = near_mem$imem_master_awvalid ; - // value method imem_master_m_wvalid - assign imem_master_wvalid = near_mem$imem_master_wvalid ; + // action method imem_master_aw_awready + assign CAN_FIRE_imem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_imem_master_aw_awready = 1'd1 ; - // value method imem_master_m_wdata + // value method imem_master_w_wdata assign imem_master_wdata = near_mem$imem_master_wdata ; - // value method imem_master_m_wstrb + // value method imem_master_w_wstrb assign imem_master_wstrb = near_mem$imem_master_wstrb ; - // value method imem_master_m_wlast + // value method imem_master_w_wlast assign imem_master_wlast = near_mem$imem_master_wlast ; - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; + // value method imem_master_w_wvalid + assign imem_master_wvalid = near_mem$imem_master_wvalid ; - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; + // action method imem_master_w_wready + assign CAN_FIRE_imem_master_w_wready = 1'd1 ; + assign WILL_FIRE_imem_master_w_wready = 1'd1 ; - // value method imem_master_m_bready - assign imem_master_bready = near_mem$imem_master_bready ; + // action method imem_master_b_bflit + assign CAN_FIRE_imem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_imem_master_b_bflit = imem_master_bvalid ; - // value method imem_master_m_arvalid - assign imem_master_arvalid = near_mem$imem_master_arvalid ; + // value method imem_master_b_bready + assign imem_master_bready = near_mem$imem_master_bready ; - // value method imem_master_m_arid + // value method imem_master_ar_arid assign imem_master_arid = near_mem$imem_master_arid ; - // value method imem_master_m_araddr + // value method imem_master_ar_araddr assign imem_master_araddr = near_mem$imem_master_araddr ; - // value method imem_master_m_arlen + // value method imem_master_ar_arlen assign imem_master_arlen = near_mem$imem_master_arlen ; - // value method imem_master_m_arsize + // value method imem_master_ar_arsize assign imem_master_arsize = near_mem$imem_master_arsize ; - // value method imem_master_m_arburst + // value method imem_master_ar_arburst assign imem_master_arburst = near_mem$imem_master_arburst ; - // value method imem_master_m_arlock + // value method imem_master_ar_arlock assign imem_master_arlock = near_mem$imem_master_arlock ; - // value method imem_master_m_arcache + // value method imem_master_ar_arcache assign imem_master_arcache = near_mem$imem_master_arcache ; - // value method imem_master_m_arprot + // value method imem_master_ar_arprot assign imem_master_arprot = near_mem$imem_master_arprot ; - // value method imem_master_m_arqos + // value method imem_master_ar_arqos assign imem_master_arqos = near_mem$imem_master_arqos ; - // value method imem_master_m_arregion + // value method imem_master_ar_arregion assign imem_master_arregion = near_mem$imem_master_arregion ; - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; + // value method imem_master_ar_arvalid + assign imem_master_arvalid = near_mem$imem_master_arvalid ; - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; + // action method imem_master_ar_arready + assign CAN_FIRE_imem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_imem_master_ar_arready = 1'd1 ; - // value method imem_master_m_rready - assign imem_master_rready = near_mem$imem_master_rready ; + // action method imem_master_r_rflit + assign CAN_FIRE_imem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_imem_master_r_rflit = imem_master_rvalid ; - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; + // value method imem_master_r_rready + assign imem_master_rready = near_mem$imem_master_rready ; - // value method dmem_master_m_awid + // value method dmem_master_aw_awid assign dmem_master_awid = near_mem$dmem_master_awid ; - // value method dmem_master_m_awaddr + // value method dmem_master_aw_awaddr assign dmem_master_awaddr = near_mem$dmem_master_awaddr ; - // value method dmem_master_m_awlen + // value method dmem_master_aw_awlen assign dmem_master_awlen = near_mem$dmem_master_awlen ; - // value method dmem_master_m_awsize + // value method dmem_master_aw_awsize assign dmem_master_awsize = near_mem$dmem_master_awsize ; - // value method dmem_master_m_awburst + // value method dmem_master_aw_awburst assign dmem_master_awburst = near_mem$dmem_master_awburst ; - // value method dmem_master_m_awlock + // value method dmem_master_aw_awlock assign dmem_master_awlock = near_mem$dmem_master_awlock ; - // value method dmem_master_m_awcache + // value method dmem_master_aw_awcache assign dmem_master_awcache = near_mem$dmem_master_awcache ; - // value method dmem_master_m_awprot + // value method dmem_master_aw_awprot assign dmem_master_awprot = near_mem$dmem_master_awprot ; - // value method dmem_master_m_awqos + // value method dmem_master_aw_awqos assign dmem_master_awqos = near_mem$dmem_master_awqos ; - // value method dmem_master_m_awregion + // value method dmem_master_aw_awregion assign dmem_master_awregion = near_mem$dmem_master_awregion ; - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; + // value method dmem_master_aw_awvalid + assign dmem_master_awvalid = near_mem$dmem_master_awvalid ; - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; + // action method dmem_master_aw_awready + assign CAN_FIRE_dmem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_dmem_master_aw_awready = 1'd1 ; - // value method dmem_master_m_wdata + // value method dmem_master_w_wdata assign dmem_master_wdata = near_mem$dmem_master_wdata ; - // value method dmem_master_m_wstrb + // value method dmem_master_w_wstrb assign dmem_master_wstrb = near_mem$dmem_master_wstrb ; - // value method dmem_master_m_wlast + // value method dmem_master_w_wlast assign dmem_master_wlast = near_mem$dmem_master_wlast ; - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; + // value method dmem_master_w_wvalid + assign dmem_master_wvalid = near_mem$dmem_master_wvalid ; - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; + // action method dmem_master_w_wready + assign CAN_FIRE_dmem_master_w_wready = 1'd1 ; + assign WILL_FIRE_dmem_master_w_wready = 1'd1 ; - // value method dmem_master_m_bready - assign dmem_master_bready = near_mem$dmem_master_bready ; + // action method dmem_master_b_bflit + assign CAN_FIRE_dmem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_dmem_master_b_bflit = dmem_master_bvalid ; - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; + // value method dmem_master_b_bready + assign dmem_master_bready = near_mem$dmem_master_bready ; - // value method dmem_master_m_arid + // value method dmem_master_ar_arid assign dmem_master_arid = near_mem$dmem_master_arid ; - // value method dmem_master_m_araddr + // value method dmem_master_ar_araddr assign dmem_master_araddr = near_mem$dmem_master_araddr ; - // value method dmem_master_m_arlen + // value method dmem_master_ar_arlen assign dmem_master_arlen = near_mem$dmem_master_arlen ; - // value method dmem_master_m_arsize + // value method dmem_master_ar_arsize assign dmem_master_arsize = near_mem$dmem_master_arsize ; - // value method dmem_master_m_arburst + // value method dmem_master_ar_arburst assign dmem_master_arburst = near_mem$dmem_master_arburst ; - // value method dmem_master_m_arlock + // value method dmem_master_ar_arlock assign dmem_master_arlock = near_mem$dmem_master_arlock ; - // value method dmem_master_m_arcache + // value method dmem_master_ar_arcache assign dmem_master_arcache = near_mem$dmem_master_arcache ; - // value method dmem_master_m_arprot + // value method dmem_master_ar_arprot assign dmem_master_arprot = near_mem$dmem_master_arprot ; - // value method dmem_master_m_arqos + // value method dmem_master_ar_arqos assign dmem_master_arqos = near_mem$dmem_master_arqos ; - // value method dmem_master_m_arregion + // value method dmem_master_ar_arregion assign dmem_master_arregion = near_mem$dmem_master_arregion ; - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; + // value method dmem_master_ar_arvalid + assign dmem_master_arvalid = near_mem$dmem_master_arvalid ; + + // action method dmem_master_ar_arready + assign CAN_FIRE_dmem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_dmem_master_ar_arready = 1'd1 ; - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; + // action method dmem_master_r_rflit + assign CAN_FIRE_dmem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_dmem_master_r_rflit = dmem_master_rvalid ; - // value method dmem_master_m_rready + // value method dmem_master_r_rready assign dmem_master_rready = near_mem$dmem_master_rready ; // action method m_external_interrupt_req @@ -2026,7 +2266,7 @@ module mkCPU(CLK, .RDY_debug()); // submodule f_csr_reqs - FIFO1 #(.width(32'd45), .guarded(32'd1)) f_csr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd45), .guarded(32'd1)) f_csr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_csr_reqs$D_IN), .ENQ(f_csr_reqs$ENQ), @@ -2037,7 +2277,7 @@ module mkCPU(CLK, .EMPTY_N(f_csr_reqs$EMPTY_N)); // submodule f_csr_rsps - FIFO1 #(.width(32'd33), .guarded(32'd1)) f_csr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd33), .guarded(32'd1)) f_csr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_csr_rsps$D_IN), .ENQ(f_csr_rsps$ENQ), @@ -2048,7 +2288,7 @@ module mkCPU(CLK, .EMPTY_N(f_csr_rsps$EMPTY_N)); // submodule f_gpr_reqs - FIFO1 #(.width(32'd38), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd38), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_gpr_reqs$D_IN), .ENQ(f_gpr_reqs$ENQ), @@ -2059,7 +2299,7 @@ module mkCPU(CLK, .EMPTY_N(f_gpr_reqs$EMPTY_N)); // submodule f_gpr_rsps - FIFO1 #(.width(32'd33), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd33), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_gpr_rsps$D_IN), .ENQ(f_gpr_rsps$ENQ), @@ -2148,12 +2388,10 @@ module mkCPU(CLK, .dmem_master_awready(near_mem$dmem_master_awready), .dmem_master_bid(near_mem$dmem_master_bid), .dmem_master_bresp(near_mem$dmem_master_bresp), - .dmem_master_bvalid(near_mem$dmem_master_bvalid), .dmem_master_rdata(near_mem$dmem_master_rdata), .dmem_master_rid(near_mem$dmem_master_rid), .dmem_master_rlast(near_mem$dmem_master_rlast), .dmem_master_rresp(near_mem$dmem_master_rresp), - .dmem_master_rvalid(near_mem$dmem_master_rvalid), .dmem_master_wready(near_mem$dmem_master_wready), .dmem_req_addr(near_mem$dmem_req_addr), .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7), @@ -2168,12 +2406,10 @@ module mkCPU(CLK, .imem_master_awready(near_mem$imem_master_awready), .imem_master_bid(near_mem$imem_master_bid), .imem_master_bresp(near_mem$imem_master_bresp), - .imem_master_bvalid(near_mem$imem_master_bvalid), .imem_master_rdata(near_mem$imem_master_rdata), .imem_master_rid(near_mem$imem_master_rid), .imem_master_rlast(near_mem$imem_master_rlast), .imem_master_rresp(near_mem$imem_master_rresp), - .imem_master_rvalid(near_mem$imem_master_rvalid), .imem_master_wready(near_mem$imem_master_wready), .imem_req_addr(near_mem$imem_req_addr), .imem_req_f3(near_mem$imem_req_f3), @@ -2185,7 +2421,11 @@ module mkCPU(CLK, .EN_server_reset_request_put(near_mem$EN_server_reset_request_put), .EN_server_reset_response_get(near_mem$EN_server_reset_response_get), .EN_imem_req(near_mem$EN_imem_req), + .imem_master_bvalid(near_mem$imem_master_bvalid), + .imem_master_rvalid(near_mem$imem_master_rvalid), .EN_dmem_req(near_mem$EN_dmem_req), + .dmem_master_bvalid(near_mem$dmem_master_bvalid), + .dmem_master_rvalid(near_mem$dmem_master_rvalid), .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put), .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get), .EN_server_fence_request_put(near_mem$EN_server_fence_request_put), @@ -2200,7 +2440,6 @@ module mkCPU(CLK, .imem_exc(near_mem$imem_exc), .imem_exc_code(near_mem$imem_exc_code), .imem_tval(), - .imem_master_awvalid(near_mem$imem_master_awvalid), .imem_master_awid(near_mem$imem_master_awid), .imem_master_awaddr(near_mem$imem_master_awaddr), .imem_master_awlen(near_mem$imem_master_awlen), @@ -2211,12 +2450,12 @@ module mkCPU(CLK, .imem_master_awprot(near_mem$imem_master_awprot), .imem_master_awqos(near_mem$imem_master_awqos), .imem_master_awregion(near_mem$imem_master_awregion), - .imem_master_wvalid(near_mem$imem_master_wvalid), + .imem_master_awvalid(near_mem$imem_master_awvalid), .imem_master_wdata(near_mem$imem_master_wdata), .imem_master_wstrb(near_mem$imem_master_wstrb), .imem_master_wlast(near_mem$imem_master_wlast), + .imem_master_wvalid(near_mem$imem_master_wvalid), .imem_master_bready(near_mem$imem_master_bready), - .imem_master_arvalid(near_mem$imem_master_arvalid), .imem_master_arid(near_mem$imem_master_arid), .imem_master_araddr(near_mem$imem_master_araddr), .imem_master_arlen(near_mem$imem_master_arlen), @@ -2227,13 +2466,13 @@ module mkCPU(CLK, .imem_master_arprot(near_mem$imem_master_arprot), .imem_master_arqos(near_mem$imem_master_arqos), .imem_master_arregion(near_mem$imem_master_arregion), + .imem_master_arvalid(near_mem$imem_master_arvalid), .imem_master_rready(near_mem$imem_master_rready), .dmem_valid(near_mem$dmem_valid), .dmem_word64(near_mem$dmem_word64), .dmem_st_amo_val(), .dmem_exc(near_mem$dmem_exc), .dmem_exc_code(near_mem$dmem_exc_code), - .dmem_master_awvalid(near_mem$dmem_master_awvalid), .dmem_master_awid(near_mem$dmem_master_awid), .dmem_master_awaddr(near_mem$dmem_master_awaddr), .dmem_master_awlen(near_mem$dmem_master_awlen), @@ -2244,12 +2483,12 @@ module mkCPU(CLK, .dmem_master_awprot(near_mem$dmem_master_awprot), .dmem_master_awqos(near_mem$dmem_master_awqos), .dmem_master_awregion(near_mem$dmem_master_awregion), - .dmem_master_wvalid(near_mem$dmem_master_wvalid), + .dmem_master_awvalid(near_mem$dmem_master_awvalid), .dmem_master_wdata(near_mem$dmem_master_wdata), .dmem_master_wstrb(near_mem$dmem_master_wstrb), .dmem_master_wlast(near_mem$dmem_master_wlast), + .dmem_master_wvalid(near_mem$dmem_master_wvalid), .dmem_master_bready(near_mem$dmem_master_bready), - .dmem_master_arvalid(near_mem$dmem_master_arvalid), .dmem_master_arid(near_mem$dmem_master_arid), .dmem_master_araddr(near_mem$dmem_master_araddr), .dmem_master_arlen(near_mem$dmem_master_arlen), @@ -2260,6 +2499,7 @@ module mkCPU(CLK, .dmem_master_arprot(near_mem$dmem_master_arprot), .dmem_master_arqos(near_mem$dmem_master_arqos), .dmem_master_arregion(near_mem$dmem_master_arregion), + .dmem_master_arvalid(near_mem$dmem_master_arvalid), .dmem_master_rready(near_mem$dmem_master_rready), .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put), .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get), @@ -2273,36 +2513,16 @@ module mkCPU(CLK, .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_flash_mem_addr_base(), - .m_flash_mem_addr_size(), - .m_flash_mem_addr_lim(), - .m_ethernet_0_addr_base(), - .m_ethernet_0_addr_size(), - .m_ethernet_0_addr_lim(), - .m_dma_0_addr_base(), - .m_dma_0_addr_size(), - .m_dma_0_addr_lim(), - .m_uart16550_0_addr_base(), - .m_uart16550_0_addr_size(), - .m_uart16550_0_addr_lim(), - .m_gpio_0_addr_base(), - .m_gpio_0_addr_size(), - .m_gpio_0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_ddr4_0_uncached_addr_base(), - .m_ddr4_0_uncached_addr_size(), - .m_ddr4_0_uncached_addr_lim(), - .m_ddr4_0_cached_addr_base(), - .m_ddr4_0_cached_addr_size(), - .m_ddr4_0_cached_addr_lim(), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), @@ -2389,7 +2609,7 @@ module mkCPU(CLK, rg_state != 4'd1 && rg_state != 4'd2 && rg_state != 4'd3 && - rg_state != 4'd11 ; + rg_state != 4'd12 ; assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ; // rule RL_rl_stage1_mip_cmd @@ -2401,8 +2621,13 @@ module mkCPU(CLK, assign WILL_FIRE_RL_rl_stage1_mip_cmd = CAN_FIRE_RL_rl_stage1_mip_cmd ; // rule RL_rl_stage1_SFENCE_VMA - assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_12 ; - assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_12 ; + assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = + f_trace_data$FULL_N && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && + IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == + 4'd6 ; + assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = + CAN_FIRE_RL_rl_stage1_SFENCE_VMA ; // rule RL_rl_debug_run_redundant assign CAN_FIRE_RL_rl_debug_run_redundant = @@ -2452,7 +2677,7 @@ module mkCPU(CLK, // rule RL_rl_debug_run assign CAN_FIRE_RL_rl_debug_run = - NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1491 && + NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1499 && f_run_halt_reqs$D_OUT && rg_state == 4'd3 ; assign WILL_FIRE_RL_rl_debug_run = @@ -2483,7 +2708,7 @@ module mkCPU(CLK, // rule RL_rl_stage1_xRET assign CAN_FIRE_RL_rl_stage1_xRET = f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && (IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == 4'd7 || IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == @@ -2493,31 +2718,43 @@ module mkCPU(CLK, assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ; // rule RL_rl_stage1_FENCE_I - assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_10 ; - assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_10 ; + assign CAN_FIRE_RL_rl_stage1_FENCE_I = + near_mem$RDY_server_fence_i_request_put && f_trace_data$FULL_N && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && + IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == + 4'd5 ; + assign WILL_FIRE_RL_rl_stage1_FENCE_I = CAN_FIRE_RL_rl_stage1_FENCE_I ; // rule RL_rl_stage1_FENCE - assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_11 ; - assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_11 ; + assign CAN_FIRE_RL_rl_stage1_FENCE = + near_mem$RDY_server_fence_request_put && f_trace_data$FULL_N && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && + IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == + 4'd4 ; + assign WILL_FIRE_RL_rl_stage1_FENCE = CAN_FIRE_RL_rl_stage1_FENCE ; // rule RL_rl_stage1_WFI - assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_13 ; - assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_13 ; + assign CAN_FIRE_RL_rl_stage1_WFI = + f_trace_data$FULL_N && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && + IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == + 4'd10 ; + assign WILL_FIRE_RL_rl_stage1_WFI = CAN_FIRE_RL_rl_stage1_WFI ; // rule RL_rl_stage1_trap assign CAN_FIRE_RL_rl_stage1_trap = f_trace_data$FULL_N && - rg_state_2_EQ_5_428_OR_rg_state_2_EQ_4_083_AND_ETC___d1437 ; + rg_state_2_EQ_7_436_OR_rg_state_2_EQ_4_083_AND_ETC___d1445 ; assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ; // rule RL_rl_trap_BREAK_to_Debug_Mode assign CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode = near_mem$RDY_server_fence_i_request_put && f_run_halt_rsps$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == 4'd11 && - x_out_trap_info_exc_code__h14151 == 4'd3 && + x_out_trap_info_exc_code__h14057 == 4'd3 && csr_regfile$dcsr_break_enters_debug ; assign WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode = CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ; @@ -2528,12 +2765,12 @@ module mkCPU(CLK, f_run_halt_rsps$FULL_N && rg_state == 4'd2 ; assign WILL_FIRE_RL_rl_BREAK_cache_flush_finish = - MUX_rg_state$write_1__SEL_7 ; + CAN_FIRE_RL_rl_BREAK_cache_flush_finish ; // rule RL_rl_stage1_stop assign CAN_FIRE_RL_rl_stage1_stop = near_mem$RDY_server_fence_i_request_put && - rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1474 ; + rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1482 ; assign WILL_FIRE_RL_rl_stage1_stop = CAN_FIRE_RL_rl_stage1_stop && !WILL_FIRE_RL_rl_reset_from_Debug_Module ; @@ -2577,21 +2814,29 @@ module mkCPU(CLK, !WILL_FIRE_RL_rl_stage1_FENCE && !WILL_FIRE_RL_rl_stage1_FENCE_I && !WILL_FIRE_RL_rl_stage1_xRET && - !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && - !WILL_FIRE_RL_rl_stage1_CSRR_W ; + !WILL_FIRE_RL_rl_stage1_CSRR_W && + !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ; // rule RL_rl_stage2_nonpipe assign CAN_FIRE_RL_rl_stage2_nonpipe = - f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_stage3_rg_full_4_5_ETC___d1299 ; + rg_state == 4'd4 && !stage3_rg_full && + IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == + 2'd3 ; assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ; + // rule RL_rl_trap + assign CAN_FIRE_RL_rl_trap = + f_trace_data$FULL_N && rg_state == 4'd5 && + (!stage1_rg_full || + near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d490) ; + assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ; + // rule RL_rl_stage1_restart_after_csrrx assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx = (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd7 ; + rg_state == 4'd8 ; assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx = CAN_FIRE_RL_rl_stage1_restart_after_csrrx ; @@ -2601,7 +2846,7 @@ module mkCPU(CLK, imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && near_mem$RDY_server_fence_i_response_get && - rg_state == 4'd8 ; + rg_state == 4'd9 ; assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ; // rule RL_rl_finish_SFENCE_VMA @@ -2609,7 +2854,7 @@ module mkCPU(CLK, (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd10 ; + rg_state == 4'd11 ; assign WILL_FIRE_RL_rl_finish_SFENCE_VMA = CAN_FIRE_RL_rl_finish_SFENCE_VMA ; @@ -2619,7 +2864,7 @@ module mkCPU(CLK, imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && near_mem$RDY_server_fence_response_get && - rg_state == 4'd9 ; + rg_state == 4'd10 ; assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ; // rule RL_rl_WFI_resume @@ -2627,24 +2872,16 @@ module mkCPU(CLK, (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd11 && + rg_state == 4'd12 && csr_regfile$wfi_resume ; assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ; // rule RL_rl_reset_from_WFI assign CAN_FIRE_RL_rl_reset_from_WFI = - rg_state == 4'd11 && f_reset_reqs$EMPTY_N ; + rg_state == 4'd12 && f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_rl_reset_from_WFI = CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ; - // rule RL_rl_trap_fetch - assign CAN_FIRE_RL_rl_trap_fetch = - (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || - imem_rg_pc[1:0] == 2'b0 || - near_mem$imem_instr[17:16] != 2'b11) && - rg_state == 4'd6 ; - assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; - // rule RL_rl_reset_from_Debug_Module assign CAN_FIRE_RL_rl_reset_from_Debug_Module = f_reset_reqs$EMPTY_N && rg_state != 4'd0 ; @@ -2652,6 +2889,7 @@ module mkCPU(CLK, CAN_FIRE_RL_rl_reset_from_Debug_Module && !WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode && !WILL_FIRE_RL_rl_trap_fetch && + !WILL_FIRE_RL_rl_BREAK_cache_flush_finish && !WILL_FIRE_RL_rl_stage1_trap && !WILL_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume && @@ -2663,14 +2901,23 @@ module mkCPU(CLK, !WILL_FIRE_RL_rl_stage1_FENCE_I && !WILL_FIRE_RL_rl_stage1_xRET && !WILL_FIRE_RL_rl_stage1_restart_after_csrrx && - !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && !WILL_FIRE_RL_rl_stage1_CSRR_W && + !WILL_FIRE_RL_rl_trap && + !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && !WILL_FIRE_RL_rl_stage2_nonpipe ; + // rule RL_rl_trap_fetch + assign CAN_FIRE_RL_rl_trap_fetch = + (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || + imem_rg_pc[1:0] == 2'b0 || + near_mem$imem_instr[17:16] != 2'b11) && + rg_state == 4'd6 ; + assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ; + // rule RL_rl_stage1_interrupt assign CAN_FIRE_RL_rl_stage1_interrupt = f_trace_data$FULL_N && - csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1458 ; + csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1466 ; assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt && !WILL_FIRE_RL_rl_reset_from_Debug_Module ; @@ -2716,9 +2963,12 @@ module mkCPU(CLK, assign MUX_csr_regfile$mav_csr_write_1__SEL_2 = WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h12529[19:15] != 5'd0 ; + x_out_data_to_stage2_instr__h12435[19:15] != 5'd0 ; assign MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1 = WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset ; + assign MUX_csr_regfile$write_dpc_1__SEL_2 = + WILL_FIRE_RL_rl_stage1_stop || + WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ; assign MUX_f_run_halt_rsps$enq_1__SEL_1 = WILL_FIRE_RL_rl_debug_halt_redundant || WILL_FIRE_RL_rl_BREAK_cache_flush_finish || @@ -2741,6 +2991,13 @@ module mkCPU(CLK, assign MUX_imem_rg_f3$write_1__SEL_2 = WILL_FIRE_RL_rl_pipe && NOT_stage1_rg_full_00_01_OR_NOT_near_mem_imem__ETC___d1268 ; + assign MUX_imem_rg_f3$write_1__SEL_3 = + WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_trap_fetch || + WILL_FIRE_RL_rl_WFI_resume || + WILL_FIRE_RL_rl_finish_SFENCE_VMA || + WILL_FIRE_RL_rl_finish_FENCE || + WILL_FIRE_RL_rl_finish_FENCE_I || + WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; assign MUX_imem_rg_mstatus_MXR$write_1__SEL_4 = WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || @@ -2760,62 +3017,29 @@ module mkCPU(CLK, assign MUX_rg_cur_priv$write_1__SEL_2 = WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe ; + WILL_FIRE_RL_rl_trap ; assign MUX_rg_state$write_1__SEL_1 = CAN_FIRE_RL_rl_reset_complete && !WILL_FIRE_RL_imem_rl_fetch_next_32b && !WILL_FIRE_RL_rl_reset_from_Debug_Module ; assign MUX_rg_state$write_1__SEL_2 = (!csr_regfile$access_permitted_1 || f_trace_data$FULL_N) && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == 4'd2 ; assign MUX_rg_state$write_1__SEL_3 = (!csr_regfile$access_permitted_2 || f_trace_data$FULL_N) && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == 4'd3 ; assign MUX_rg_state$write_1__SEL_4 = WILL_FIRE_RL_rl_reset_from_Debug_Module || WILL_FIRE_RL_rl_reset_from_WFI ; - assign MUX_rg_state$write_1__SEL_6 = - WILL_FIRE_RL_rl_stage1_stop || - WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ; - assign MUX_rg_state$write_1__SEL_7 = - CAN_FIRE_RL_rl_BREAK_cache_flush_finish && - !WILL_FIRE_RL_rl_reset_from_Debug_Module ; - assign MUX_rg_state$write_1__SEL_8 = - WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_trap_fetch || - WILL_FIRE_RL_rl_WFI_resume || - WILL_FIRE_RL_rl_finish_SFENCE_VMA || - WILL_FIRE_RL_rl_finish_FENCE || - WILL_FIRE_RL_rl_finish_FENCE_I || - WILL_FIRE_RL_rl_stage1_restart_after_csrrx ; - assign MUX_rg_state$write_1__SEL_9 = + assign MUX_rg_state$write_1__SEL_10 = WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe ; - assign MUX_rg_state$write_1__SEL_10 = - near_mem$RDY_server_fence_i_request_put && f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && - IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == - 4'd5 ; - assign MUX_rg_state$write_1__SEL_11 = - near_mem$RDY_server_fence_request_put && f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && - IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == - 4'd4 ; - assign MUX_rg_state$write_1__SEL_12 = - f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && - IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == - 4'd6 ; - assign MUX_rg_state$write_1__SEL_13 = - f_trace_data$FULL_N && - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && - IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == - 4'd10 ; + WILL_FIRE_RL_rl_trap ; assign MUX_rg_step_count$write_1__PSEL_1 = WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_WFI_resume || WILL_FIRE_RL_rl_finish_SFENCE_VMA || @@ -2825,21 +3049,21 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_pipe ; assign MUX_rg_step_count$write_1__SEL_3 = WILL_FIRE_RL_rl_stage1_stop || WILL_FIRE_RL_rl_reset_start ; - assign MUX_csr_regfile$csr_trap_actions_5__VAL_2 = + assign MUX_csr_regfile$csr_trap_actions_5__VAL_1 = (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ? csr_regfile$interrupt_pending[3:0] : 4'd0 ; - always@(x_out_data_to_stage2_instr__h12529 or + always@(x_out_data_to_stage2_instr__h12435 or csr_regfile$read_csr or - y__h21114 or - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1367) + y__h21164 or + IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1375) begin - case (x_out_data_to_stage2_instr__h12529[14:12]) + case (x_out_data_to_stage2_instr__h12435[14:12]) 3'b010, 3'b110: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1367; + IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1375; default: MUX_csr_regfile$mav_csr_write_2__VAL_2 = - csr_regfile$read_csr[31:0] & y__h21114; + csr_regfile$read_csr[31:0] & y__h21164; endcase end assign MUX_csr_regfile$write_dcsr_cause_priv_1__VAL_2 = @@ -2853,72 +3077,72 @@ module mkCPU(CLK, stage2_rg_stage2[127:0] } ; assign MUX_f_trace_data$enq_1__VAL_2 = { 4'd14, - x__h18327, + x__h18233, near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482, - x__h18419, - x_out_data_to_stage2_instr__h12529[11:7], + x__h18325, + x_out_data_to_stage2_instr__h12435[11:7], csr_regfile$read_csr[31:0], 32'd1, - x_word3__h20591, + x_word3__h20641, csr_regfile$mav_csr_write } ; assign MUX_f_trace_data$enq_1__VAL_3 = { 4'd14, - x__h18327, + x__h18233, near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482, - x__h18419, - x_out_data_to_stage2_instr__h12529[11:7], + x__h18325, + x_out_data_to_stage2_instr__h12435[11:7], csr_regfile$read_csr[31:0], - x__h21266, - x_word3__h20591, - x__h21274 } ; + x__h21316, + x_word3__h20641, + x__h21324 } ; assign MUX_f_trace_data$enq_1__VAL_6 = { 202'h0EAAAAAAA955555554AAAAAAAAAAAAAAAAA0000000000000344, csr_regfile$csr_mip_read } ; assign MUX_f_trace_data$enq_1__VAL_7 = { 4'd12, csr_regfile$csr_trap_actions[97:66], - stage2_rg_stage2[197:165], - trace_data_rd__h27064, + rg_trap_trace_data[197:165], + trace_data_rd__h27114, csr_regfile$csr_trap_actions[65:2], - x_word3__h19995, - stage2_rg_stage2[329:298] } ; + x_word3__h20017, + rg_trap_info[31:0] } ; assign MUX_f_trace_data$enq_1__VAL_8 = { 4'd13, csr_regfile$csr_ret_actions[65:34], near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482, - x__h18419, - td1_rd__h22143, + x__h18325, + td1_rd__h22193, csr_regfile$csr_ret_actions[31:0], 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_f_trace_data$enq_1__VAL_9 = { 4'd12, csr_regfile$csr_trap_actions[97:66], near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482, - x__h18419, - trace_data_rd__h27064, + x__h18325, + trace_data_rd__h27114, csr_regfile$csr_trap_actions[65:2], - trace_data_word3__h27067, - value__h14199 } ; + trace_data_word3__h27117, + value__h14105 } ; assign MUX_f_trace_data$enq_1__VAL_10 = { 4'd15, csr_regfile$csr_trap_actions[97:66], 33'h0AAAAAAAA, - trace_data_rd__h27064, + trace_data_rd__h27114, csr_regfile$csr_trap_actions[65:2], - trace_data_word3__h27067, + trace_data_word3__h27117, 32'd0 } ; assign MUX_near_mem$imem_req_2__VAL_1 = { soc_map$m_pc_reset_value[31:2], 2'b0 } ; assign MUX_near_mem$imem_req_2__VAL_2 = - { x_out_next_pc__h12499[31:2], 2'b0 } ; + { x_out_next_pc__h12405[31:2], 2'b0 } ; assign MUX_near_mem$imem_req_2__VAL_5 = { rg_next_pc[31:2], 2'b0 } ; assign MUX_near_mem$imem_req_2__VAL_7 = { csr_regfile$read_dpc[31:2], 2'b0 } ; assign MUX_rg_state$write_1__VAL_1 = rg_run_on_reset ? 4'd4 : 4'd3 ; assign MUX_rg_state$write_1__VAL_2 = - csr_regfile$access_permitted_1 ? 4'd7 : 4'd5 ; + csr_regfile$access_permitted_1 ? 4'd8 : 4'd7 ; assign MUX_rg_state$write_1__VAL_3 = - csr_regfile$access_permitted_2 ? 4'd7 : 4'd5 ; + csr_regfile$access_permitted_2 ? 4'd8 : 4'd7 ; assign MUX_stage1_rg_full$write_1__VAL_10 = NOT_stage1_rg_full_00_01_OR_NOT_near_mem_imem__ETC___d1260 && csr_regfile_csr_mip_read__089_EQ_rg_prev_mip_090___d1091 && @@ -2986,7 +3210,7 @@ module mkCPU(CLK, always@(MUX_imem_rg_f3$write_1__SEL_1 or soc_map$m_pc_reset_value or MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h12499 or + x_out_next_pc__h12405 or WILL_FIRE_RL_rl_stage1_restart_after_csrrx or MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc or WILL_FIRE_RL_rl_debug_run or csr_regfile$read_dpc) @@ -2994,9 +3218,9 @@ module mkCPU(CLK, case (1'b1) // synopsys parallel_case MUX_imem_rg_f3$write_1__SEL_1: imem_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0]; - MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h12499; + MUX_imem_rg_f3$write_1__SEL_2: imem_rg_pc$D_IN = x_out_next_pc__h12405; WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_pc$D_IN = x_out_next_pc__h12499; + imem_rg_pc$D_IN = x_out_next_pc__h12405; MUX_imem_rg_pc$write_1__SEL_4: imem_rg_pc$D_IN = rg_next_pc; WILL_FIRE_RL_rl_debug_run: imem_rg_pc$D_IN = csr_regfile$read_dpc; default: imem_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; @@ -3061,25 +3285,25 @@ module mkCPU(CLK, always@(MUX_imem_rg_f3$write_1__SEL_1 or soc_map$m_pc_reset_value or MUX_imem_rg_f3$write_1__SEL_2 or - x_out_next_pc__h12499 or + x_out_next_pc__h12405 or WILL_FIRE_RL_rl_stage1_restart_after_csrrx or MUX_imem_rg_pc$write_1__SEL_4 or rg_next_pc or WILL_FIRE_RL_rl_debug_run or csr_regfile$read_dpc or - WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h14311) + WILL_FIRE_RL_imem_rl_fetch_next_32b or next_pc___1__h14217) begin case (1'b1) // synopsys parallel_case MUX_imem_rg_f3$write_1__SEL_1: imem_rg_tval$D_IN = soc_map$m_pc_reset_value[31:0]; MUX_imem_rg_f3$write_1__SEL_2: - imem_rg_tval$D_IN = x_out_next_pc__h12499; + imem_rg_tval$D_IN = x_out_next_pc__h12405; WILL_FIRE_RL_rl_stage1_restart_after_csrrx: - imem_rg_tval$D_IN = x_out_next_pc__h12499; + imem_rg_tval$D_IN = x_out_next_pc__h12405; MUX_imem_rg_pc$write_1__SEL_4: imem_rg_tval$D_IN = rg_next_pc; WILL_FIRE_RL_rl_debug_run: imem_rg_tval$D_IN = csr_regfile$read_dpc; WILL_FIRE_RL_imem_rl_fetch_next_32b: - imem_rg_tval$D_IN = next_pc___1__h14311; + imem_rg_tval$D_IN = next_pc___1__h14217; default: imem_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end @@ -3115,7 +3339,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_reset_start ; // register rg_mstatus_MXR @@ -3123,21 +3347,21 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_interrupt ? csr_regfile$csr_trap_actions[53] : csr_regfile$read_mstatus[19] ; - assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_9 ; + assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_10 ; // register rg_next_pc always@(WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions or MUX_rg_cur_priv$write_1__SEL_2 or csr_regfile$csr_trap_actions or - MUX_f_trace_data$enq_1__SEL_4 or x_out_next_pc__h12499) + MUX_f_trace_data$enq_1__SEL_4 or x_out_next_pc__h12405) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_rl_stage1_xRET: rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34]; MUX_rg_cur_priv$write_1__SEL_2: rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66]; - MUX_f_trace_data$enq_1__SEL_4: rg_next_pc$D_IN = x_out_next_pc__h12499; + MUX_f_trace_data$enq_1__SEL_4: rg_next_pc$D_IN = x_out_next_pc__h12405; default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end @@ -3145,7 +3369,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE || WILL_FIRE_RL_rl_stage1_FENCE_I || @@ -3167,7 +3391,7 @@ module mkCPU(CLK, assign rg_sstatus_SUM$D_IN = WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$csr_trap_actions[52] ; - assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_9 ; + assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_10 ; // register rg_start_CPI_cycles assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ; @@ -3190,10 +3414,11 @@ module mkCPU(CLK, MUX_rg_state$write_1__VAL_3 or MUX_rg_state$write_1__SEL_4 or WILL_FIRE_RL_rl_reset_start or - MUX_rg_state$write_1__SEL_6 or + MUX_csr_regfile$write_dpc_1__SEL_2 or WILL_FIRE_RL_rl_BREAK_cache_flush_finish or - MUX_rg_state$write_1__SEL_8 or - MUX_rg_state$write_1__SEL_9 or + MUX_imem_rg_f3$write_1__SEL_3 or + WILL_FIRE_RL_rl_stage2_nonpipe or + MUX_rg_state$write_1__SEL_10 or WILL_FIRE_RL_rl_stage1_FENCE_I or WILL_FIRE_RL_rl_stage1_FENCE or WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI) @@ -3207,14 +3432,15 @@ module mkCPU(CLK, rg_state$D_IN = MUX_rg_state$write_1__VAL_3; MUX_rg_state$write_1__SEL_4: rg_state$D_IN = 4'd0; WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1; - MUX_rg_state$write_1__SEL_6: rg_state$D_IN = 4'd2; + MUX_csr_regfile$write_dpc_1__SEL_2: rg_state$D_IN = 4'd2; WILL_FIRE_RL_rl_BREAK_cache_flush_finish: rg_state$D_IN = 4'd3; - MUX_rg_state$write_1__SEL_8: rg_state$D_IN = 4'd4; - MUX_rg_state$write_1__SEL_9: rg_state$D_IN = 4'd6; - WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd8; - WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd9; - WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd10; - WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd11; + MUX_imem_rg_f3$write_1__SEL_3: rg_state$D_IN = 4'd4; + WILL_FIRE_RL_rl_stage2_nonpipe: rg_state$D_IN = 4'd5; + MUX_rg_state$write_1__SEL_10: rg_state$D_IN = 4'd6; + WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd9; + WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd10; + WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd11; + WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd12; default: rg_state$D_IN = 4'b1010 /* unspecified value */ ; endcase end @@ -3235,10 +3461,11 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_finish_FENCE || WILL_FIRE_RL_rl_finish_FENCE_I || WILL_FIRE_RL_rl_stage1_restart_after_csrrx || + WILL_FIRE_RL_rl_stage2_nonpipe || WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_FENCE_I || WILL_FIRE_RL_rl_stage1_FENCE || WILL_FIRE_RL_rl_stage1_SFENCE_VMA || @@ -3261,6 +3488,21 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_stop || WILL_FIRE_RL_rl_reset_start || WILL_FIRE_RL_rl_debug_halt ; + // register rg_trap_info + assign rg_trap_info$D_IN = + { stage2_rg_stage2[401:370], + near_mem$dmem_exc_code, + stage2_rg_stage2[329:298] } ; + assign rg_trap_info$EN = CAN_FIRE_RL_rl_stage2_nonpipe ; + + // register rg_trap_instr + assign rg_trap_instr$D_IN = stage2_rg_stage2[369:338] ; + assign rg_trap_instr$EN = CAN_FIRE_RL_rl_stage2_nonpipe ; + + // register rg_trap_trace_data + assign rg_trap_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_1 ; + assign rg_trap_trace_data$EN = CAN_FIRE_RL_rl_stage2_nonpipe ; + // register stage1_rg_full always@(WILL_FIRE_RL_stage1_rl_reset or WILL_FIRE_RL_rl_stage1_interrupt or @@ -3270,7 +3512,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_finish_SFENCE_VMA or WILL_FIRE_RL_rl_finish_FENCE_I or WILL_FIRE_RL_rl_stage1_restart_after_csrrx or - WILL_FIRE_RL_rl_stage2_nonpipe or + WILL_FIRE_RL_rl_trap or WILL_FIRE_RL_rl_pipe or MUX_stage1_rg_full$write_1__VAL_10 or MUX_imem_rg_f3$write_1__SEL_1 or @@ -3285,7 +3527,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_finish_FENCE_I || WILL_FIRE_RL_rl_stage1_restart_after_csrrx: stage1_rg_full$D_IN = 1'd1; - WILL_FIRE_RL_rl_stage2_nonpipe: stage1_rg_full$D_IN = 1'd0; + WILL_FIRE_RL_rl_trap: stage1_rg_full$D_IN = 1'd0; WILL_FIRE_RL_rl_pipe: stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_10; MUX_imem_rg_f3$write_1__SEL_1: stage1_rg_full$D_IN = 1'd1; @@ -3300,7 +3542,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_interrupt || WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_stage1_rl_reset || WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_trap_fetch || @@ -3312,12 +3554,12 @@ module mkCPU(CLK, // register stage2_rg_full always@(stage2_f_reset_reqs$EMPTY_N or - WILL_FIRE_RL_rl_stage2_nonpipe or + WILL_FIRE_RL_rl_trap or WILL_FIRE_RL_rl_pipe or MUX_stage2_rg_full$write_1__VAL_3 or MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_debug_run) case (1'b1) - stage2_f_reset_reqs$EMPTY_N || WILL_FIRE_RL_rl_stage2_nonpipe: + stage2_f_reset_reqs$EMPTY_N || WILL_FIRE_RL_rl_trap: stage2_rg_full$D_IN = 1'd0; WILL_FIRE_RL_rl_pipe: stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_3; @@ -3329,7 +3571,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset || WILL_FIRE_RL_rl_pipe || WILL_FIRE_RL_rl_debug_run || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || stage2_f_reset_reqs$EMPTY_N ; // register stage2_rg_resetting @@ -3341,12 +3583,12 @@ module mkCPU(CLK, assign stage2_rg_stage2$D_IN = { rg_cur_priv, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831, - x_out_data_to_stage2_rd__h12531, - x_out_data_to_stage2_addr__h12532, - x_out_data_to_stage2_val1__h12533, - x_out_data_to_stage2_val2__h12534, + x_out_data_to_stage2_rd__h12437, + x_out_data_to_stage2_addr__h12438, + x_out_data_to_stage2_val1__h12439, + x_out_data_to_stage2_val2__h12440, IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d1240 } ; assign stage2_rg_stage2$EN = WILL_FIRE_RL_rl_pipe && @@ -3380,20 +3622,20 @@ module mkCPU(CLK, stage2_rg_stage2[403:402], stage2_rg_stage2[337:335] == 3'd0 || IF_stage2_rg_stage2_4_BITS_337_TO_335_5_EQ_1_7_ETC___d147, - x_out_data_to_stage3_rd__h6556, - x_out_data_to_stage3_rd_val__h6557 } ; + x_out_data_to_stage3_rd__h6462, + x_out_data_to_stage3_rd_val__h6463 } ; assign stage3_rg_stage3$EN = MUX_f_trace_data$enq_1__SEL_1 ; // submodule csr_regfile assign csr_regfile$access_permitted_1_csr_addr = - x_out_data_to_stage2_instr__h12529[31:20] ; + x_out_data_to_stage2_instr__h12435[31:20] ; assign csr_regfile$access_permitted_1_priv = rg_cur_priv ; assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ; assign csr_regfile$access_permitted_2_csr_addr = - x_out_data_to_stage2_instr__h12529[31:20] ; + x_out_data_to_stage2_instr__h12435[31:20] ; assign csr_regfile$access_permitted_2_priv = rg_cur_priv ; assign csr_regfile$access_permitted_2_read_not_write = - rs1_val__h20813 == 32'd0 ; + rs1_val__h20863 == 32'd0 ; assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ; assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ; always@(IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752) @@ -3404,21 +3646,21 @@ module mkCPU(CLK, default: csr_regfile$csr_ret_actions_from_priv = 2'b0; endcase end - always@(WILL_FIRE_RL_rl_stage2_nonpipe or - near_mem$dmem_exc_code or - WILL_FIRE_RL_rl_stage1_interrupt or - MUX_csr_regfile$csr_trap_actions_5__VAL_2 or - WILL_FIRE_RL_rl_stage1_trap or x_out_trap_info_exc_code__h14151) + always@(WILL_FIRE_RL_rl_stage1_interrupt or + MUX_csr_regfile$csr_trap_actions_5__VAL_1 or + WILL_FIRE_RL_rl_stage1_trap or + x_out_trap_info_exc_code__h14057 or + WILL_FIRE_RL_rl_trap or rg_trap_info) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_exc_code = near_mem$dmem_exc_code; WILL_FIRE_RL_rl_stage1_interrupt: csr_regfile$csr_trap_actions_exc_code = - MUX_csr_regfile$csr_trap_actions_5__VAL_2; + MUX_csr_regfile$csr_trap_actions_5__VAL_1; WILL_FIRE_RL_rl_stage1_trap: csr_regfile$csr_trap_actions_exc_code = - x_out_trap_info_exc_code__h14151; + x_out_trap_info_exc_code__h14057; + WILL_FIRE_RL_rl_trap: + csr_regfile$csr_trap_actions_exc_code = rg_trap_info[35:32]; default: csr_regfile$csr_trap_actions_exc_code = 4'b1010 /* unspecified value */ ; endcase @@ -3429,21 +3671,18 @@ module mkCPU(CLK, assign csr_regfile$csr_trap_actions_nmi = WILL_FIRE_RL_rl_stage1_interrupt && csr_regfile$nmi_pending ; assign csr_regfile$csr_trap_actions_pc = - WILL_FIRE_RL_rl_stage2_nonpipe ? - stage2_rg_stage2[401:370] : - imem_rg_pc ; - always@(WILL_FIRE_RL_rl_stage2_nonpipe or - stage2_rg_stage2 or - WILL_FIRE_RL_rl_stage1_interrupt or - WILL_FIRE_RL_rl_stage1_trap or value__h14199) + WILL_FIRE_RL_rl_trap ? rg_trap_info[67:36] : imem_rg_pc ; + always@(WILL_FIRE_RL_rl_stage1_interrupt or + WILL_FIRE_RL_rl_stage1_trap or + value__h14105 or WILL_FIRE_RL_rl_trap or rg_trap_info) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_rl_stage2_nonpipe: - csr_regfile$csr_trap_actions_xtval = stage2_rg_stage2[329:298]; WILL_FIRE_RL_rl_stage1_interrupt: csr_regfile$csr_trap_actions_xtval = 32'd0; WILL_FIRE_RL_rl_stage1_trap: - csr_regfile$csr_trap_actions_xtval = value__h14199; + csr_regfile$csr_trap_actions_xtval = value__h14105; + WILL_FIRE_RL_rl_trap: + csr_regfile$csr_trap_actions_xtval = rg_trap_info[31:0]; default: csr_regfile$csr_trap_actions_xtval = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -3455,16 +3694,16 @@ module mkCPU(CLK, assign csr_regfile$mav_csr_write_csr_addr = WILL_FIRE_RL_rl_debug_write_csr ? f_csr_reqs$D_OUT[43:32] : - x_out_data_to_stage2_instr__h12529[31:20] ; + x_out_data_to_stage2_instr__h12435[31:20] ; always@(MUX_csr_regfile$mav_csr_write_1__SEL_1 or - rs1_val__h20224 or + rs1_val__h20274 or MUX_csr_regfile$mav_csr_write_1__SEL_2 or MUX_csr_regfile$mav_csr_write_2__VAL_2 or WILL_FIRE_RL_rl_debug_write_csr or f_csr_reqs$D_OUT) begin case (1'b1) // synopsys parallel_case MUX_csr_regfile$mav_csr_write_1__SEL_1: - csr_regfile$mav_csr_write_word = rs1_val__h20224; + csr_regfile$mav_csr_write_word = rs1_val__h20274; MUX_csr_regfile$mav_csr_write_1__SEL_2: csr_regfile$mav_csr_write_word = MUX_csr_regfile$mav_csr_write_2__VAL_2; @@ -3477,7 +3716,7 @@ module mkCPU(CLK, assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ; assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ; assign csr_regfile$read_csr_csr_addr = - x_out_data_to_stage2_instr__h12529[31:20] ; + x_out_data_to_stage2_instr__h12435[31:20] ; assign csr_regfile$read_csr_port2_csr_addr = f_csr_reqs$D_OUT[43:32] ; assign csr_regfile$s_external_interrupt_req_set_not_clear = s_external_interrupt_req_set_not_clear ; @@ -3521,12 +3760,9 @@ module mkCPU(CLK, csr_regfile$access_permitted_1 || WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && csr_regfile$access_permitted_2 && - x_out_data_to_stage2_instr__h12529[19:15] != 5'd0 || + x_out_data_to_stage2_instr__h12435[19:15] != 5'd0 || WILL_FIRE_RL_rl_debug_write_csr ; - assign csr_regfile$EN_csr_trap_actions = - WILL_FIRE_RL_rl_stage2_nonpipe || - WILL_FIRE_RL_rl_stage1_interrupt || - WILL_FIRE_RL_rl_stage1_trap ; + assign csr_regfile$EN_csr_trap_actions = MUX_rg_cur_priv$write_1__SEL_2 ; assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ; assign csr_regfile$EN_csr_minstret_incr = WILL_FIRE_RL_rl_pipe && @@ -3540,7 +3776,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_FENCE || WILL_FIRE_RL_rl_stage1_FENCE_I || WILL_FIRE_RL_rl_stage1_xRET || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_SFENCE_VMA ; assign csr_regfile$EN_write_dpc = WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset || @@ -3613,10 +3849,7 @@ module mkCPU(CLK, // submodule f_reset_reqs assign f_reset_reqs$D_IN = hart0_server_reset_request_put ; assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ; - assign f_reset_reqs$DEQ = - gpr_regfile$RDY_server_reset_request_put && - near_mem_RDY_server_reset_request_put__038_AND_ETC___d1050 && - rg_state == 4'd0 ; + assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset_start ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps @@ -3658,7 +3891,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_reset_start or WILL_FIRE_RL_rl_stage1_mip_cmd or MUX_f_trace_data$enq_1__VAL_6 or - WILL_FIRE_RL_rl_stage2_nonpipe or + WILL_FIRE_RL_rl_trap or MUX_f_trace_data$enq_1__VAL_7 or WILL_FIRE_RL_rl_stage1_xRET or MUX_f_trace_data$enq_1__VAL_8 or @@ -3681,8 +3914,7 @@ module mkCPU(CLK, 234'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; WILL_FIRE_RL_rl_stage1_mip_cmd: f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_6; - WILL_FIRE_RL_rl_stage2_nonpipe: - f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_7; + WILL_FIRE_RL_rl_trap: f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_7; WILL_FIRE_RL_rl_stage1_xRET: f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_8; WILL_FIRE_RL_rl_stage1_trap: @@ -3707,7 +3939,7 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_stage1_SFENCE_VMA || WILL_FIRE_RL_rl_reset_start || WILL_FIRE_RL_rl_stage1_mip_cmd || - WILL_FIRE_RL_rl_stage2_nonpipe || + WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_stage1_trap || WILL_FIRE_RL_rl_stage1_interrupt ; @@ -3716,14 +3948,14 @@ module mkCPU(CLK, // submodule gpr_regfile assign gpr_regfile$read_rs1_port2_rs1 = f_gpr_reqs$D_OUT[36:32] ; - assign gpr_regfile$read_rs1_rs1 = _theResult____h4437[19:15] ; - assign gpr_regfile$read_rs2_rs2 = _theResult____h4437[24:20] ; + assign gpr_regfile$read_rs1_rs1 = _theResult____h4320[19:15] ; + assign gpr_regfile$read_rs2_rs2 = _theResult____h4320[24:20] ; always@(WILL_FIRE_RL_rl_debug_write_gpr or f_gpr_reqs$D_OUT or MUX_gpr_regfile$write_rd_1__SEL_1 or stage3_rg_stage3 or MUX_csr_regfile$mav_csr_write_1__SEL_1 or - MUX_f_trace_data$enq_1__SEL_3 or x_out_data_to_stage2_instr__h12529) + MUX_f_trace_data$enq_1__SEL_3 or x_out_data_to_stage2_instr__h12435) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_rl_debug_write_gpr: @@ -3731,7 +3963,7 @@ module mkCPU(CLK, MUX_gpr_regfile$write_rd_1__SEL_1: gpr_regfile$write_rd_rd = stage3_rg_stage3[36:32]; MUX_csr_regfile$mav_csr_write_1__SEL_1 || MUX_f_trace_data$enq_1__SEL_3: - gpr_regfile$write_rd_rd = x_out_data_to_stage2_instr__h12529[11:7]; + gpr_regfile$write_rd_rd = x_out_data_to_stage2_instr__h12435[11:7]; default: gpr_regfile$write_rd_rd = 5'b01010 /* unspecified value */ ; endcase end @@ -3770,17 +4002,15 @@ module mkCPU(CLK, assign near_mem$dmem_master_awready = dmem_master_awready ; assign near_mem$dmem_master_bid = dmem_master_bid ; assign near_mem$dmem_master_bresp = dmem_master_bresp ; - assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; assign near_mem$dmem_master_rdata = dmem_master_rdata ; assign near_mem$dmem_master_rid = dmem_master_rid ; assign near_mem$dmem_master_rlast = dmem_master_rlast ; assign near_mem$dmem_master_rresp = dmem_master_rresp ; - assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; assign near_mem$dmem_master_wready = dmem_master_wready ; - assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h12532 ; + assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h12438 ; assign near_mem$dmem_req_amo_funct7 = - x_out_data_to_stage2_val1__h12533[6:0] ; - assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h12529[14:12] ; + x_out_data_to_stage2_val1__h12439[6:0] ; + assign near_mem$dmem_req_f3 = x_out_data_to_stage2_instr__h12435[14:12] ; assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ; always@(IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831) begin @@ -3797,24 +4027,22 @@ module mkCPU(CLK, assign near_mem$dmem_req_satp = csr_regfile$read_satp ; assign near_mem$dmem_req_sstatus_SUM = 1'd0 ; assign near_mem$dmem_req_store_value = - { 32'd0, x_out_data_to_stage2_val2__h12534 } ; + { 32'd0, x_out_data_to_stage2_val2__h12440 } ; assign near_mem$imem_master_arready = imem_master_arready ; assign near_mem$imem_master_awready = imem_master_awready ; assign near_mem$imem_master_bid = imem_master_bid ; assign near_mem$imem_master_bresp = imem_master_bresp ; - assign near_mem$imem_master_bvalid = imem_master_bvalid ; assign near_mem$imem_master_rdata = imem_master_rdata ; assign near_mem$imem_master_rid = imem_master_rid ; assign near_mem$imem_master_rlast = imem_master_rlast ; assign near_mem$imem_master_rresp = imem_master_rresp ; - assign near_mem$imem_master_rvalid = imem_master_rvalid ; assign near_mem$imem_master_wready = imem_master_wready ; always@(MUX_imem_rg_f3$write_1__SEL_1 or MUX_near_mem$imem_req_2__VAL_1 or MUX_imem_rg_f3$write_1__SEL_2 or MUX_near_mem$imem_req_2__VAL_2 or WILL_FIRE_RL_imem_rl_fetch_next_32b or - next_pc___1__h14311 or + next_pc___1__h14217 or WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap_fetch or MUX_near_mem$imem_req_2__VAL_5 or @@ -3827,7 +4055,7 @@ module mkCPU(CLK, MUX_imem_rg_f3$write_1__SEL_2: near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; WILL_FIRE_RL_imem_rl_fetch_next_32b: - near_mem$imem_req_addr = next_pc___1__h14311; + near_mem$imem_req_addr = next_pc___1__h14217; WILL_FIRE_RL_rl_stage1_restart_after_csrrx: near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2; WILL_FIRE_RL_rl_trap_fetch: @@ -3915,6 +4143,8 @@ module mkCPU(CLK, WILL_FIRE_RL_rl_finish_FENCE || WILL_FIRE_RL_rl_finish_FENCE_I || WILL_FIRE_RL_rl_debug_run ; + assign near_mem$imem_master_bvalid = imem_master_bvalid ; + assign near_mem$imem_master_rvalid = imem_master_rvalid ; assign near_mem$EN_dmem_req = WILL_FIRE_RL_rl_pipe && near_mem_imem_exc__91_OR_IF_IF_NOT_near_mem_im_ETC___d1194 && @@ -3926,6 +4156,8 @@ module mkCPU(CLK, 3'd2 || IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831 == 3'd4) ; + assign near_mem$dmem_master_bvalid = dmem_master_bvalid ; + assign near_mem$dmem_master_rvalid = dmem_master_rvalid ; assign near_mem$EN_server_fence_i_request_put = WILL_FIRE_RL_rl_stage1_stop || WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode || @@ -3933,9 +4165,9 @@ module mkCPU(CLK, assign near_mem$EN_server_fence_i_response_get = WILL_FIRE_RL_rl_BREAK_cache_flush_finish || WILL_FIRE_RL_rl_finish_FENCE_I ; - assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_11 ; + assign near_mem$EN_server_fence_request_put = CAN_FIRE_RL_rl_stage1_FENCE ; assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ; - assign near_mem$EN_sfence_vma = MUX_rg_state$write_1__SEL_12 ; + assign near_mem$EN_sfence_vma = CAN_FIRE_RL_rl_stage1_SFENCE_VMA ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; @@ -3963,10 +4195,10 @@ module mkCPU(CLK, assign stage2_f_reset_rsps$CLR = 1'b0 ; // submodule stage2_mbox - assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h12529[14:12] ; - assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4437[3] ; - assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h12533 ; - assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h12534 ; + assign stage2_mbox$req_f3 = x_out_data_to_stage2_instr__h12435[14:12] ; + assign stage2_mbox$req_is_OP_not_OP_32 = !_theResult____h4320[3] ; + assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h12439 ; + assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h12440 ; assign stage2_mbox$set_verbosity_verbosity = 4'h0 ; assign stage2_mbox$EN_set_verbosity = 1'b0 ; assign stage2_mbox$EN_req_reset = 1'b0 ; @@ -4015,12 +4247,12 @@ module mkCPU(CLK, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d639) && stage1_rg_full ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1221 = - ((_theResult____h4437[6:0] == 7'b0010011 || - _theResult____h4437[6:0] == 7'b0110011) && - (_theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101)) ? - _theResult____h12797 : - CASE_theResult__437_BITS_6_TO_0_0b10011_rd_val_ETC__q18 ; + ((_theResult____h4320[6:0] == 7'b0010011 || + _theResult____h4320[6:0] == 7'b0110011) && + (_theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101)) ? + _theResult____h12703 : + CASE_theResult__320_BITS_6_TO_0_0b10011_rd_val_ETC__q18 ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1286 = (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) && @@ -4040,74 +4272,74 @@ module mkCPU(CLK, NOT_near_mem_imem_valid_02_OR_NOT_near_mem_ime_ETC___d1148) && stage1_rg_full ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d529 = - rs1_val_bypassed__h4445 == rs2_val__h12631 ; + rs1_val_bypassed__h4328 == rs2_val__h12537 ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d531 = - (rs1_val_bypassed__h4445 ^ 32'h80000000) < - (rs2_val__h12631 ^ 32'h80000000) ; + (rs1_val_bypassed__h4328 ^ 32'h80000000) < + (rs2_val__h12537 ^ 32'h80000000) ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533 = - rs1_val_bypassed__h4445 < rs2_val__h12631 ; + rs1_val_bypassed__h4328 < rs2_val__h12537 ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 = - (_theResult____h4437[6:0] == 7'b1100011) ? - _theResult____h4437[14:12] != 3'b0 && - _theResult____h4437[14:12] != 3'b001 && - _theResult____h4437[14:12] != 3'b100 && - _theResult____h4437[14:12] != 3'b101 && - _theResult____h4437[14:12] != 3'b110 && - _theResult____h4437[14:12] != 3'b111 || + (_theResult____h4320[6:0] == 7'b1100011) ? + _theResult____h4320[14:12] != 3'b0 && + _theResult____h4320[14:12] != 3'b001 && + _theResult____h4320[14:12] != 3'b100 && + _theResult____h4320[14:12] != 3'b101 && + _theResult____h4320[14:12] != 3'b110 && + _theResult____h4320[14:12] != 3'b111 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 : - (_theResult____h4437[6:0] != 7'b0110011 || - _theResult____h4437[31:25] != 7'b0000001) && - (((_theResult____h4437[6:0] == 7'b0010011 || - _theResult____h4437[6:0] == 7'b0110011) && - (_theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101)) ? - _theResult____h4437[25] : - CASE_theResult__437_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9) ; + (_theResult____h4320[6:0] != 7'b0110011 || + _theResult____h4320[31:25] != 7'b0000001) && + (((_theResult____h4320[6:0] == 7'b0010011 || + _theResult____h4320[6:0] == 7'b0110011) && + (_theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101)) ? + _theResult____h4320[25] : + CASE_theResult__320_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9) ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d639 = - (_theResult____h4437[6:0] == 7'b1100011) ? - _theResult____h4437[14:12] != 3'b0 && - _theResult____h4437[14:12] != 3'b001 && - _theResult____h4437[14:12] != 3'b100 && - _theResult____h4437[14:12] != 3'b101 && - _theResult____h4437[14:12] != 3'b110 && - _theResult____h4437[14:12] != 3'b111 || + (_theResult____h4320[6:0] == 7'b1100011) ? + _theResult____h4320[14:12] != 3'b0 && + _theResult____h4320[14:12] != 3'b001 && + _theResult____h4320[14:12] != 3'b100 && + _theResult____h4320[14:12] != 3'b101 && + _theResult____h4320[14:12] != 3'b110 && + _theResult____h4320[14:12] != 3'b111 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634 : - _theResult____h4437[6:0] != 7'b1101111 && - _theResult____h4437[6:0] != 7'b1100111 ; + _theResult____h4320[6:0] != 7'b1101111 && + _theResult____h4320[6:0] != 7'b1100111 ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 = - (_theResult____h4437[6:0] == 7'b1100011) ? - (_theResult____h4437[14:12] == 3'b0 || - _theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b100 || - _theResult____h4437[14:12] == 3'b101 || - _theResult____h4437[14:12] == 3'b110 || - _theResult____h4437[14:12] == 3'b111) && + (_theResult____h4320[6:0] == 7'b1100011) ? + (_theResult____h4320[14:12] == 3'b0 || + _theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b100 || + _theResult____h4320[14:12] == 3'b101 || + _theResult____h4320[14:12] == 3'b110 || + _theResult____h4320[14:12] == 3'b111) && IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634 : - _theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[31:25] == 7'b0000001 || - (((_theResult____h4437[6:0] == 7'b0010011 || - _theResult____h4437[6:0] == 7'b0110011) && - (_theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101)) ? - !_theResult____h4437[25] : - CASE_theResult__437_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11) ; + _theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[31:25] == 7'b0000001 || + (((_theResult____h4320[6:0] == 7'b0010011 || + _theResult____h4320[6:0] == 7'b0110011) && + (_theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101)) ? + !_theResult____h4320[25] : + CASE_theResult__320_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11) ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688 = - (_theResult____h4437[6:0] == 7'b1100011) ? - (_theResult____h4437[14:12] == 3'b0 || - _theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b100 || - _theResult____h4437[14:12] == 3'b101 || - _theResult____h4437[14:12] == 3'b110 || - _theResult____h4437[14:12] == 3'b111) && + (_theResult____h4320[6:0] == 7'b1100011) ? + (_theResult____h4320[14:12] == 3'b0 || + _theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b100 || + _theResult____h4320[14:12] == 3'b101 || + _theResult____h4320[14:12] == 3'b110 || + _theResult____h4320[14:12] == 3'b111) && IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 : - _theResult____h4437[6:0] == 7'b1101111 || - _theResult____h4437[6:0] == 7'b1100111 ; + _theResult____h4320[6:0] == 7'b1101111 || + _theResult____h4320[6:0] == 7'b1100111 ; assign IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d943 = - ((_theResult____h4437[6:0] == 7'b0010011 || - _theResult____h4437[6:0] == 7'b0110011) && - (_theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101)) ? - _theResult____h12797 : + ((_theResult____h4320[6:0] == 7'b0010011 || + _theResult____h4320[6:0] == 7'b0110011) && + (_theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101)) ? + _theResult____h12703 : IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 ; assign IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d696 = NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d570 ? @@ -4118,185 +4350,185 @@ module mkCPU(CLK, IF_stage2_rg_stage2_4_BITS_334_TO_330_54_EQ_0__ETC___d181 : 2'd0 ; assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d659 = - _theResult____h4437[14:12] == 3'b0 && - (_theResult____h4437[6:0] != 7'b0110011 || - !_theResult____h4437[30]) || - _theResult____h4437[14:12] == 3'b0 && - _theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[30] || - _theResult____h4437[14:12] == 3'b010 || - _theResult____h4437[14:12] == 3'b011 || - _theResult____h4437[14:12] == 3'b100 || - _theResult____h4437[14:12] == 3'b110 || - _theResult____h4437[14:12] == 3'b111 ; + _theResult____h4320[14:12] == 3'b0 && + (_theResult____h4320[6:0] != 7'b0110011 || + !_theResult____h4320[30]) || + _theResult____h4320[14:12] == 3'b0 && + _theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[30] || + _theResult____h4320[14:12] == 3'b010 || + _theResult____h4320[14:12] == 3'b011 || + _theResult____h4320[14:12] == 3'b100 || + _theResult____h4320[14:12] == 3'b110 || + _theResult____h4320[14:12] == 3'b111 ; assign IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875 = NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_ETC___d211 ? - next_pc___1__h14311 : - next_pc__h14309 ; + next_pc___1__h14217 : + next_pc__h14215 ; assign IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d1240 = - { CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19, - x__h18327, + { CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19, + x__h18233, near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482, - x__h18419, - x_out_data_to_stage2_trace_data_rd__h17725, - x__h18596, - rs2_val__h12631, - x_out_data_to_stage2_trace_data_word3__h17728, + x__h18325, + x_out_data_to_stage2_trace_data_rd__h17631, + x__h18502, + rs2_val__h12537, + x_out_data_to_stage2_trace_data_word3__h17634, 32'hAAAAAAAA } ; assign IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 = near_mem$imem_exc ? 4'd11 : IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d750 ; - assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1367 = - csr_regfile$read_csr[31:0] | rs1_val__h20813 ; + assign IF_csr_regfile_read_csr_IF_NOT_stage1_rg_full__ETC___d1375 = + csr_regfile$read_csr[31:0] | rs1_val__h20863 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d443 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:10] == 6'b100011 && - instr__h4435[6:5] == 2'b0) ? - instr__h12063 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[15:12] == 4'b1001 && - instr__h4435[11:7] == 5'd0 && - instr__h4435[6:2] == 5'd0) ? - instr__h12401 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:10] == 6'b100011 && + instr__h4318[6:5] == 2'b0) ? + instr__h11969 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[15:12] == 4'b1001 && + instr__h4318[11:7] == 5'd0 && + instr__h4318[6:2] == 5'd0) ? + instr__h12307 : 32'h0) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d445 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:10] == 6'b100011 && - instr__h4435[6:5] == 2'b10) ? - instr__h11791 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:10] == 6'b100011 && - instr__h4435[6:5] == 2'b01) ? - instr__h11927 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:10] == 6'b100011 && + instr__h4318[6:5] == 2'b10) ? + instr__h11697 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:10] == 6'b100011 && + instr__h4318[6:5] == 2'b01) ? + instr__h11833 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d443) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d447 = (csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d314 && - instr__h4435[6:2] != 5'd0) ? - instr__h11560 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:10] == 6'b100011 && - instr__h4435[6:5] == 2'b11) ? - instr__h11655 : + instr__h4318[6:2] != 5'd0) ? + instr__h11466 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:10] == 6'b100011 && + instr__h4318[6:5] == 2'b11) ? + instr__h11561 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d445) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d448 = (csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d308 && - instr__h4435[6:2] != 5'd0) ? - instr__h11441 : + instr__h4318[6:2] != 5'd0) ? + instr__h11347 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d447 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d450 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b100 && - instr__h4435[11:10] == 2'b01 && - imm6__h9587 != 6'd0 && - !instr__h4435[12]) ? - instr__h11146 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b100 && - instr__h4435[11:10] == 2'b10) ? - instr__h11263 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b100 && + instr__h4318[11:10] == 2'b01 && + imm6__h9493 != 6'd0 && + !instr__h4318[12]) ? + instr__h11052 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b100 && + instr__h4318[11:10] == 2'b10) ? + instr__h11169 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d448) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d451 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b100 && - instr__h4435[11:10] == 2'b0 && - imm6__h9587 != 6'd0 && - !instr__h4435[12]) ? - instr__h10953 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b100 && + instr__h4318[11:10] == 2'b0 && + imm6__h9493 != 6'd0 && + !instr__h4318[12]) ? + instr__h10859 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d450 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d452 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[15:13] == 3'b0 && - instr__h4435[11:7] != 5'd0 && - imm6__h9587 != 6'd0 && - !instr__h4435[12]) ? - instr__h10760 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[15:13] == 3'b0 && + instr__h4318[11:7] != 5'd0 && + imm6__h9493 != 6'd0 && + !instr__h4318[12]) ? + instr__h10666 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d451 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d454 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b011 && - instr__h4435[11:7] == 5'd2 && - nzimm10__h10211 != 10'd0) ? - instr__h10415 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b0 && - instr__h4435[15:13] == 3'b0 && - nzimm10__h10426 != 10'd0) ? - instr__h10587 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b011 && + instr__h4318[11:7] == 5'd2 && + nzimm10__h10117 != 10'd0) ? + instr__h10321 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b0 && + instr__h4318[15:13] == 3'b0 && + nzimm10__h10332 != 10'd0) ? + instr__h10493 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d452) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d455 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b0 && - instr__h4435[11:7] != 5'd0 && - imm6__h9587 != 6'd0 || - csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b0 && - instr__h4435[11:7] == 5'd0 && - imm6__h9587 == 6'd0) ? - instr__h9978 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b0 && + instr__h4318[11:7] != 5'd0 && + imm6__h9493 != 6'd0 || + csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b0 && + instr__h4318[11:7] == 5'd0 && + imm6__h9493 == 6'd0) ? + instr__h9884 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d454 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d456 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b011 && - instr__h4435[11:7] != 5'd0 && - instr__h4435[11:7] != 5'd2 && - imm6__h9587 != 6'd0) ? - instr__h9849 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b011 && + instr__h4318[11:7] != 5'd0 && + instr__h4318[11:7] != 5'd2 && + imm6__h9493 != 6'd0) ? + instr__h9755 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d455 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d458 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b111) ? - instr__h9327 : - ((csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b010 && - instr__h4435[11:7] != 5'd0) ? - instr__h9665 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b111) ? + instr__h9233 : + ((csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b010 && + instr__h4318[11:7] != 5'd0) ? + instr__h9571 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d456) ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d459 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b110) ? - instr__h9010 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b110) ? + instr__h8916 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d458 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d460 = (csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d314 && - instr__h4435[6:2] == 5'd0) ? - instr__h8945 : + instr__h4318[6:2] == 5'd0) ? + instr__h8851 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d459 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d461 = (csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d308 && - instr__h4435[6:2] == 5'd0) ? - instr__h8829 : + instr__h4318[6:2] == 5'd0) ? + instr__h8735 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d460 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d462 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b001) ? - instr__h8439 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b001) ? + instr__h8345 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d461 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d463 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b01 && - instr__h4435[15:13] == 3'b101) ? - instr__h8096 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b01 && + instr__h4318[15:13] == 3'b101) ? + instr__h8002 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d462 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d464 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b0 && - instr__h4435[15:13] == 3'b110) ? - instr__h7867 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b0 && + instr__h4318[15:13] == 3'b110) ? + instr__h7773 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d463 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d465 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b0 && - instr__h4435[15:13] == 3'b010) ? - instr__h7672 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b0 && + instr__h4318[15:13] == 3'b010) ? + instr__h7578 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d464 ; assign IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d466 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[15:13] == 3'b110) ? - instr__h7480 : + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[15:13] == 3'b110) ? + instr__h7386 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d465 ; assign IF_near_mem_dmem_valid__15_THEN_IF_near_mem_dm_ETC___d118 = near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ; assign IF_rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_E_ETC___d729 = ((rg_cur_priv == 2'b11 || rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) && - _theResult____h4437[31:20] == 12'b000100000010) ? + _theResult____h4320[31:20] == 12'b000100000010) ? 4'd8 : (rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_EQ_0_ETC___d727 ? 4'd10 : @@ -4310,9 +4542,9 @@ module mkCPU(CLK, CASE_stage2_rg_stage2_BITS_337_TO_335_0_2_1_IF_ETC__q2 : 2'd0 ; assign IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d470 = - x_out_bypass_rd__h6907 == _theResult____h4437[19:15] ; + x_out_bypass_rd__h6813 == _theResult____h4320[19:15] ; assign IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d472 = - x_out_bypass_rd__h6907 == _theResult____h4437[24:20] ; + x_out_bypass_rd__h6813 == _theResult____h4320[24:20] ; assign IF_stage2_rg_stage2_4_BITS_334_TO_330_54_EQ_0__ETC___d181 = (stage2_rg_stage2[334:330] == 5'd0) ? 2'd0 : @@ -4320,19 +4552,19 @@ module mkCPU(CLK, assign IF_stage2_rg_stage2_4_BITS_337_TO_335_5_EQ_3_0_ETC___d121 = stage2_mbox$valid ? 2'd2 : 2'd1 ; assign NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d570 = - (_theResult____h4437[14:12] != 3'b0 || - _theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[30]) && - (_theResult____h4437[14:12] != 3'b0 || - _theResult____h4437[6:0] != 7'b0110011 || - !_theResult____h4437[30]) && - _theResult____h4437[14:12] != 3'b010 && - _theResult____h4437[14:12] != 3'b011 && - _theResult____h4437[14:12] != 3'b100 && - _theResult____h4437[14:12] != 3'b110 && - _theResult____h4437[14:12] != 3'b111 ; + (_theResult____h4320[14:12] != 3'b0 || + _theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[30]) && + (_theResult____h4320[14:12] != 3'b0 || + _theResult____h4320[6:0] != 7'b0110011 || + !_theResult____h4320[30]) && + _theResult____h4320[14:12] != 3'b010 && + _theResult____h4320[14:12] != 3'b011 && + _theResult____h4320[14:12] != 3'b100 && + _theResult____h4320[14:12] != 3'b110 && + _theResult____h4320[14:12] != 3'b111 ; assign NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41 = - cur_verbosity__h3142 > 4'd1 ; + cur_verbosity__h2930 > 4'd1 ; assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1191 = !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || near_mem$imem_exc || @@ -4344,12 +4576,12 @@ module mkCPU(CLK, NOT_near_mem_imem_valid_02_OR_NOT_near_mem_ime_ETC___d1148) && (!stage1_rg_full || NOT_near_mem_imem_valid_02_OR_NOT_near_mem_ime_ETC___d1135) ; - assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1321 = + assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1329 = !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending || !near_mem$imem_exc && (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) ; - assign NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1319 = + assign NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1327 = !near_mem$imem_exc && (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) || @@ -4392,7 +4624,7 @@ module mkCPU(CLK, 3'd2 && IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831 != 3'd3 ; - assign NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1491 = + assign NOT_near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_p_ETC___d1499 = (!near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) && @@ -4465,12 +4697,12 @@ module mkCPU(CLK, near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691 || !stage1_rg_full) ; assign SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d884 = - { {20{theResult__437_BITS_31_TO_20__q17[11]}}, - theResult__437_BITS_31_TO_20__q17 } ; + { {20{theResult__320_BITS_31_TO_20__q17[11]}}, + theResult__320_BITS_31_TO_20__q17 } ; assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294 = - { {9{offset__h8043[11]}}, offset__h8043 } ; + { {9{offset__h7949[11]}}, offset__h7949 } ; assign SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323 = - { {4{offset__h8954[8]}}, offset__h8954 } ; + { {4{offset__h8860[8]}}, offset__h8860 } ; assign _0_OR_0_OR_near_mem_imem_exc__91_OR_IF_IF_NOT_n_ETC___d1274 = near_mem$imem_exc || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d628 && @@ -4496,69 +4728,69 @@ module mkCPU(CLK, 2'd0) && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691 || !stage1_rg_full ; - assign _theResult_____1_fst__h13636 = - (_theResult____h4437[14:12] == 3'b0 && - _theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[30]) ? - rd_val___1__h13632 : - _theResult_____1_fst__h13643 ; - assign _theResult_____1_fst__h13671 = - rs1_val_bypassed__h4445 & _theResult___snd__h14769 ; - assign _theResult____h12797 = - (_theResult____h4437[14:12] == 3'b001) ? - rd_val__h14665 : - (_theResult____h4437[30] ? rd_val__h14739 : rd_val__h14717) ; - assign _theResult____h27350 = - (delta_CPI_instrs__h27349 == 64'd0) ? - delta_CPI_instrs___1__h27385 : - delta_CPI_instrs__h27349 ; - assign _theResult____h4437 = x_out_data_to_stage2_instr__h12529 ; - assign _theResult___fst__h7235 = + assign _theResult_____1_fst__h13542 = + (_theResult____h4320[14:12] == 3'b0 && + _theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[30]) ? + rd_val___1__h13538 : + _theResult_____1_fst__h13549 ; + assign _theResult_____1_fst__h13577 = + rs1_val_bypassed__h4328 & _theResult___snd__h14675 ; + assign _theResult____h12703 = + (_theResult____h4320[14:12] == 3'b001) ? + rd_val__h14571 : + (_theResult____h4320[30] ? rd_val__h14645 : rd_val__h14623) ; + assign _theResult____h27400 = + (delta_CPI_instrs__h27399 == 64'd0) ? + delta_CPI_instrs___1__h27435 : + delta_CPI_instrs__h27399 ; + assign _theResult____h4320 = x_out_data_to_stage2_instr__h12435 ; + assign _theResult___fst__h7141 = (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && imem_rg_pc[1:0] == 2'b0 && near_mem$imem_instr[1:0] != 2'b11) ? - instr_out___1__h7237 : - _theResult___fst__h7263 ; - assign _theResult___fst__h7263 = + instr_out___1__h7143 : + _theResult___fst__h7169 ; + assign _theResult___fst__h7169 = (near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 && imem_rg_pc[1:0] != 2'b0 && near_mem$imem_instr[17:16] != 2'b11) ? - instr_out___1__h7265 : + instr_out___1__h7171 : near_mem$imem_instr ; - assign _theResult___snd__h14769 = - (_theResult____h4437[6:0] == 7'b0010011) ? + assign _theResult___snd__h14675 = + (_theResult____h4320[6:0] == 7'b0010011) ? SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d884 : - rs2_val__h12631 ; - assign alu_outputs___1_addr__h12657 = + rs2_val__h12537 ; + assign alu_outputs___1_addr__h12563 = IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 ? - branch_target__h12635 : + branch_target__h12541 : IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875 ; - assign alu_outputs___1_addr__h12678 = + assign alu_outputs___1_addr__h12584 = imem_rg_pc + - { {11{theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q4[20]}}, - theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q4 } ; - assign alu_outputs___1_addr__h12704 = { eaddr__h12887[31:1], 1'd0 } ; - assign alu_outputs___1_exc_code__h13156 = - (_theResult____h4437[14:12] == 3'b0) ? - ((_theResult____h4437[11:7] == 5'd0 && - _theResult____h4437[19:15] == 5'd0) ? - CASE_theResult__437_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 : + { {11{theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q4[20]}}, + theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q4 } ; + assign alu_outputs___1_addr__h12610 = { eaddr__h12793[31:1], 1'd0 } ; + assign alu_outputs___1_exc_code__h13062 = + (_theResult____h4320[14:12] == 3'b0) ? + ((_theResult____h4320[11:7] == 5'd0 && + _theResult____h4320[19:15] == 5'd0) ? + CASE_theResult__320_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 : 4'd2) : 4'd2 ; - assign alu_outputs___1_trace_data_word3__h17603 = { 32'd0, eaddr__h12887 } ; - assign alu_outputs___1_trace_data_word3__h17622 = { 32'd0, eaddr__h12907 } ; - assign alu_outputs___1_val1__h13160 = - _theResult____h4437[14] ? - { 27'd0, _theResult____h4437[19:15] } : - rs1_val_bypassed__h4445 ; - assign alu_outputs___1_val1__h13181 = - { 25'd0, _theResult____h4437[31:25] } ; - assign branch_target__h12635 = + assign alu_outputs___1_trace_data_word3__h17509 = { 32'd0, eaddr__h12793 } ; + assign alu_outputs___1_trace_data_word3__h17528 = { 32'd0, eaddr__h12813 } ; + assign alu_outputs___1_val1__h13066 = + _theResult____h4320[14] ? + { 27'd0, _theResult____h4320[19:15] } : + rs1_val_bypassed__h4328 ; + assign alu_outputs___1_val1__h13087 = + { 25'd0, _theResult____h4320[31:25] } ; + assign branch_target__h12541 = imem_rg_pc + - { {19{theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q3[12]}}, - theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q3 } ; - assign cpi__h27352 = x__h27351 / 64'd10 ; - assign cpifrac__h27353 = x__h27351 % 64'd10 ; + { {19{theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q3[12]}}, + theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q3 } ; + assign cpi__h27402 = x__h27401 / 64'd10 ; + assign cpifrac__h27403 = x__h27401 % 64'd10 ; assign csr_regfile_csr_mip_read__089_EQ_rg_prev_mip_090___d1091 = csr_regfile$csr_mip_read == rg_prev_mip ; assign csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1116 = @@ -4566,180 +4798,180 @@ module mkCPU(CLK, stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1104 && IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1084 ; - assign csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1458 = + assign csr_regfile_interrupt_pending_rg_cur_priv_9_11_ETC___d1466 = (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) && rg_state == 4'd4 && stage1_rg_full_00_AND_near_mem_imem_valid_AND__ETC___d1087 && !stage3_rg_full && csr_regfile_csr_mip_read__089_EQ_rg_prev_mip_090___d1091 ; - assign csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1478 = - delta_CPI_cycles__h27348 * 64'd10 ; + assign csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1486 = + delta_CPI_cycles__h27398 * 64'd10 ; assign csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d308 = - csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[15:12] == 4'b1000 && - instr__h4435[11:7] != 5'd0 ; + csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[15:12] == 4'b1000 && + instr__h4318[11:7] != 5'd0 ; assign csr_regfile_read_misa__6_BIT_2_18_AND_IF_near__ETC___d314 = - csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[15:12] == 4'b1001 && - instr__h4435[11:7] != 5'd0 ; - assign cur_verbosity__h3142 = + csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[15:12] == 4'b1001 && + instr__h4318[11:7] != 5'd0 ; + assign cur_verbosity__h2930 = (csr_regfile$read_csr_minstret < cfg_logdelay) ? 4'd0 : cfg_verbosity ; - assign data_to_stage2_addr__h12523 = x_out_data_to_stage2_addr__h12532 ; - assign delta_CPI_cycles__h27348 = + assign data_to_stage2_addr__h12429 = x_out_data_to_stage2_addr__h12438 ; + assign delta_CPI_cycles__h27398 = csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ; - assign delta_CPI_instrs___1__h27385 = delta_CPI_instrs__h27349 + 64'd1 ; - assign delta_CPI_instrs__h27349 = + assign delta_CPI_instrs___1__h27435 = delta_CPI_instrs__h27399 + 64'd1 ; + assign delta_CPI_instrs__h27399 = csr_regfile$read_csr_minstret - rg_start_CPI_instrs ; - assign eaddr__h12887 = - rs1_val_bypassed__h4445 + + assign eaddr__h12793 = + rs1_val_bypassed__h4328 + SEXT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLU_ETC___d884 ; - assign eaddr__h12907 = - rs1_val_bypassed__h4445 + - { {20{theResult__437_BITS_31_TO_25_CONCAT_theResult__ETC__q7[11]}}, - theResult__437_BITS_31_TO_25_CONCAT_theResult__ETC__q7 } ; - assign fall_through_pc__h12486 = + assign eaddr__h12813 = + rs1_val_bypassed__h4328 + + { {20{theResult__320_BITS_31_TO_25_CONCAT_theResult__ETC__q7[11]}}, + theResult__320_BITS_31_TO_25_CONCAT_theResult__ETC__q7 } ; + assign fall_through_pc__h12392 = imem_rg_pc + (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482 ? 32'd4 : 32'd2) ; - assign imm12__h10213 = { {2{nzimm10__h10211[9]}}, nzimm10__h10211 } ; - assign imm12__h10428 = { 2'd0, nzimm10__h10426 } ; - assign imm12__h10624 = { 7'b0, instr__h4435[6:2] } ; - assign imm12__h10969 = { 7'b0100000, instr__h4435[6:2] } ; - assign imm12__h7336 = { 4'd0, offset__h7106 } ; - assign imm12__h7673 = { 5'd0, offset__h7615 } ; - assign imm12__h9589 = { {6{imm6__h9587[5]}}, imm6__h9587 } ; - assign imm20__h9717 = { {14{imm6__h9587[5]}}, imm6__h9587 } ; - assign imm6__h9587 = { instr__h4435[12], instr__h4435[6:2] } ; - assign instr___1__h7068 = - (csr_regfile$read_misa[2] && instr__h4435[1:0] == 2'b10 && - instr__h4435[11:7] != 5'd0 && - instr__h4435[15:13] == 3'b010) ? - instr__h7335 : + assign imm12__h10119 = { {2{nzimm10__h10117[9]}}, nzimm10__h10117 } ; + assign imm12__h10334 = { 2'd0, nzimm10__h10332 } ; + assign imm12__h10530 = { 7'b0, instr__h4318[6:2] } ; + assign imm12__h10875 = { 7'b0100000, instr__h4318[6:2] } ; + assign imm12__h7242 = { 4'd0, offset__h7012 } ; + assign imm12__h7579 = { 5'd0, offset__h7521 } ; + assign imm12__h9495 = { {6{imm6__h9493[5]}}, imm6__h9493 } ; + assign imm20__h9623 = { {14{imm6__h9493[5]}}, imm6__h9493 } ; + assign imm6__h9493 = { instr__h4318[12], instr__h4318[6:2] } ; + assign instr___1__h6974 = + (csr_regfile$read_misa[2] && instr__h4318[1:0] == 2'b10 && + instr__h4318[11:7] != 5'd0 && + instr__h4318[15:13] == 3'b010) ? + instr__h7241 : IF_csr_regfile_read_misa__6_BIT_2_18_AND_IF_ne_ETC___d466 ; - assign instr__h10415 = - { imm12__h10213, - instr__h4435[11:7], + assign instr__h10321 = + { imm12__h10119, + instr__h4318[11:7], 3'b0, - instr__h4435[11:7], + instr__h4318[11:7], 7'b0010011 } ; - assign instr__h10587 = { imm12__h10428, 8'd16, rd__h7675, 7'b0010011 } ; - assign instr__h10760 = - { imm12__h10624, - instr__h4435[11:7], + assign instr__h10493 = { imm12__h10334, 8'd16, rd__h7581, 7'b0010011 } ; + assign instr__h10666 = + { imm12__h10530, + instr__h4318[11:7], 3'b001, - instr__h4435[11:7], + instr__h4318[11:7], 7'b0010011 } ; - assign instr__h10953 = - { imm12__h10624, rs1__h7674, 3'b101, rs1__h7674, 7'b0010011 } ; - assign instr__h11146 = - { imm12__h10969, rs1__h7674, 3'b101, rs1__h7674, 7'b0010011 } ; - assign instr__h11263 = - { imm12__h9589, rs1__h7674, 3'b111, rs1__h7674, 7'b0010011 } ; - assign instr__h11441 = + assign instr__h10859 = + { imm12__h10530, rs1__h7580, 3'b101, rs1__h7580, 7'b0010011 } ; + assign instr__h11052 = + { imm12__h10875, rs1__h7580, 3'b101, rs1__h7580, 7'b0010011 } ; + assign instr__h11169 = + { imm12__h9495, rs1__h7580, 3'b111, rs1__h7580, 7'b0010011 } ; + assign instr__h11347 = { 7'b0, - instr__h4435[6:2], + instr__h4318[6:2], 8'd0, - instr__h4435[11:7], + instr__h4318[11:7], 7'b0110011 } ; - assign instr__h11560 = + assign instr__h11466 = { 7'b0, - instr__h4435[6:2], - instr__h4435[11:7], + instr__h4318[6:2], + instr__h4318[11:7], 3'b0, - instr__h4435[11:7], + instr__h4318[11:7], 7'b0110011 } ; - assign instr__h11655 = - { 7'b0, rd__h7675, rs1__h7674, 3'b111, rs1__h7674, 7'b0110011 } ; - assign instr__h11791 = - { 7'b0, rd__h7675, rs1__h7674, 3'b110, rs1__h7674, 7'b0110011 } ; - assign instr__h11927 = - { 7'b0, rd__h7675, rs1__h7674, 3'b100, rs1__h7674, 7'b0110011 } ; - assign instr__h12063 = + assign instr__h11561 = + { 7'b0, rd__h7581, rs1__h7580, 3'b111, rs1__h7580, 7'b0110011 } ; + assign instr__h11697 = + { 7'b0, rd__h7581, rs1__h7580, 3'b110, rs1__h7580, 7'b0110011 } ; + assign instr__h11833 = + { 7'b0, rd__h7581, rs1__h7580, 3'b100, rs1__h7580, 7'b0110011 } ; + assign instr__h11969 = { 7'b0100000, - rd__h7675, - rs1__h7674, + rd__h7581, + rs1__h7580, 3'b0, - rs1__h7674, + rs1__h7580, 7'b0110011 } ; - assign instr__h12401 = + assign instr__h12307 = { 12'b000000000001, - instr__h4435[11:7], + instr__h4318[11:7], 3'b0, - instr__h4435[11:7], + instr__h4318[11:7], 7'b1110011 } ; - assign instr__h4435 = + assign instr__h4318 = near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d203 ? - instr_out___1__h7205 : - _theResult___fst__h7235 ; - assign instr__h7335 = - { imm12__h7336, 8'd18, instr__h4435[11:7], 7'b0000011 } ; - assign instr__h7480 = + instr_out___1__h7111 : + _theResult___fst__h7141 ; + assign instr__h7241 = + { imm12__h7242, 8'd18, instr__h4318[11:7], 7'b0000011 } ; + assign instr__h7386 = { 4'd0, - instr__h4435[8:7], - instr__h4435[12], - instr__h4435[6:2], + instr__h4318[8:7], + instr__h4318[12], + instr__h4318[6:2], 8'd18, - offset_BITS_4_TO_0___h7604, + offset_BITS_4_TO_0___h7510, 7'b0100011 } ; - assign instr__h7672 = - { imm12__h7673, rs1__h7674, 3'b010, rd__h7675, 7'b0000011 } ; - assign instr__h7867 = + assign instr__h7578 = + { imm12__h7579, rs1__h7580, 3'b010, rd__h7581, 7'b0000011 } ; + assign instr__h7773 = { 5'd0, - instr__h4435[5], - instr__h4435[12], - rd__h7675, - rs1__h7674, + instr__h4318[5], + instr__h4318[12], + rd__h7581, + rs1__h7580, 3'b010, - offset_BITS_4_TO_0___h8035, + offset_BITS_4_TO_0___h7941, 7'b0100011 } ; - assign instr__h8096 = + assign instr__h8002 = { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[20], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[10:1], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[11], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[19:12], 12'd111 } ; - assign instr__h8439 = + assign instr__h8345 = { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[20], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[10:1], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[11], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d294[19:12], 12'd239 } ; - assign instr__h8829 = { 12'd0, instr__h4435[11:7], 15'd103 } ; - assign instr__h8945 = { 12'd0, instr__h4435[11:7], 15'd231 } ; - assign instr__h9010 = + assign instr__h8735 = { 12'd0, instr__h4318[11:7], 15'd103 } ; + assign instr__h8851 = { 12'd0, instr__h4318[11:7], 15'd231 } ; + assign instr__h8916 = { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[12], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[10:5], 5'd0, - rs1__h7674, + rs1__h7580, 3'b0, SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[4:1], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[11], 7'b1100011 } ; - assign instr__h9327 = + assign instr__h9233 = { SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[12], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[10:5], 5'd0, - rs1__h7674, + rs1__h7580, 3'b001, SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[4:1], SEXT_IF_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2__ETC___d323[11], 7'b1100011 } ; - assign instr__h9665 = - { imm12__h9589, 8'd0, instr__h4435[11:7], 7'b0010011 } ; - assign instr__h9849 = { imm20__h9717, instr__h4435[11:7], 7'b0110111 } ; - assign instr__h9978 = - { imm12__h9589, - instr__h4435[11:7], + assign instr__h9571 = + { imm12__h9495, 8'd0, instr__h4318[11:7], 7'b0010011 } ; + assign instr__h9755 = { imm20__h9623, instr__h4318[11:7], 7'b0110111 } ; + assign instr__h9884 = + { imm12__h9495, + instr__h4318[11:7], 3'b0, - instr__h4435[11:7], + instr__h4318[11:7], 7'b0010011 } ; - assign instr_out___1__h7205 = + assign instr_out___1__h7111 = { near_mem$imem_instr[15:0], imem_rg_instr_15_0 } ; - assign instr_out___1__h7237 = { 16'b0, near_mem$imem_instr[15:0] } ; - assign instr_out___1__h7265 = { 16'b0, near_mem$imem_instr[31:16] } ; + assign instr_out___1__h7143 = { 16'b0, near_mem$imem_instr[15:0] } ; + assign instr_out___1__h7171 = { 16'b0, near_mem$imem_instr[31:16] } ; assign near_mem_RDY_server_reset_request_put__038_AND_ETC___d1050 = near_mem$RDY_server_reset_request_put && csr_regfile$RDY_server_reset_request_put && @@ -4869,7 +5101,7 @@ module mkCPU(CLK, imem_rg_pc[1:0] == 2'b0 && near_mem$imem_instr[1:0] != 2'b11 ; assign near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d203 = - near_mem$imem_pc == next_pc___1__h14311 ; + near_mem$imem_pc == next_pc___1__h14217 ; assign near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d1104 = near_mem$imem_valid && near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9___d203 && @@ -4894,120 +5126,114 @@ module mkCPU(CLK, !near_mem$imem_exc && (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d686 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688) ; - assign next_pc___1__h14311 = imem_rg_pc + 32'd2 ; - assign next_pc__h14309 = imem_rg_pc + 32'd4 ; - assign nzimm10__h10211 = - { instr__h4435[12], - instr__h4435[4:3], - instr__h4435[5], - instr__h4435[2], - instr__h4435[6], + assign next_pc___1__h14217 = imem_rg_pc + 32'd2 ; + assign next_pc__h14215 = imem_rg_pc + 32'd4 ; + assign nzimm10__h10117 = + { instr__h4318[12], + instr__h4318[4:3], + instr__h4318[5], + instr__h4318[2], + instr__h4318[6], 4'b0 } ; - assign nzimm10__h10426 = - { instr__h4435[10:7], - instr__h4435[12:11], - instr__h4435[5], - instr__h4435[6], + assign nzimm10__h10332 = + { instr__h4318[10:7], + instr__h4318[12:11], + instr__h4318[5], + instr__h4318[6], 2'b0 } ; - assign offset_BITS_4_TO_0___h7604 = { instr__h4435[11:9], 2'b0 } ; - assign offset_BITS_4_TO_0___h8035 = - { instr__h4435[11:10], instr__h4435[6], 2'b0 } ; - assign offset__h7106 = - { instr__h4435[3:2], - instr__h4435[12], - instr__h4435[6:4], + assign offset_BITS_4_TO_0___h7510 = { instr__h4318[11:9], 2'b0 } ; + assign offset_BITS_4_TO_0___h7941 = + { instr__h4318[11:10], instr__h4318[6], 2'b0 } ; + assign offset__h7012 = + { instr__h4318[3:2], + instr__h4318[12], + instr__h4318[6:4], 2'b0 } ; - assign offset__h7615 = - { instr__h4435[5], instr__h4435[12:10], instr__h4435[6], 2'b0 } ; - assign offset__h8043 = - { instr__h4435[12], - instr__h4435[8], - instr__h4435[10:9], - instr__h4435[6], - instr__h4435[7], - instr__h4435[2], - instr__h4435[11], - instr__h4435[5:3], + assign offset__h7521 = + { instr__h4318[5], instr__h4318[12:10], instr__h4318[6], 2'b0 } ; + assign offset__h7949 = + { instr__h4318[12], + instr__h4318[8], + instr__h4318[10:9], + instr__h4318[6], + instr__h4318[7], + instr__h4318[2], + instr__h4318[11], + instr__h4318[5:3], 1'b0 } ; - assign offset__h8954 = - { instr__h4435[12], - instr__h4435[6:5], - instr__h4435[2], - instr__h4435[11:10], - instr__h4435[4:3], + assign offset__h8860 = + { instr__h4318[12], + instr__h4318[6:5], + instr__h4318[2], + instr__h4318[11:10], + instr__h4318[4:3], 1'b0 } ; - assign output_stage2___1_bypass_rd_val__h6896 = + assign output_stage2___1_bypass_rd_val__h6802 = (!near_mem$dmem_valid || !near_mem$dmem_exc) ? ((stage2_rg_stage2[334:330] == 5'd0) ? stage2_rg_stage2[297:266] : near_mem$dmem_word64[31:0]) : stage2_rg_stage2[297:266] ; - assign rd__h7675 = { 2'b01, instr__h4435[4:2] } ; - assign rd_val___1__h13624 = - rs1_val_bypassed__h4445 + _theResult___snd__h14769 ; - assign rd_val___1__h13632 = - rs1_val_bypassed__h4445 - _theResult___snd__h14769 ; - assign rd_val___1__h13639 = - ((rs1_val_bypassed__h4445 ^ 32'h80000000) < - (_theResult___snd__h14769 ^ 32'h80000000)) ? + assign rd__h7581 = { 2'b01, instr__h4318[4:2] } ; + assign rd_val___1__h13530 = + rs1_val_bypassed__h4328 + _theResult___snd__h14675 ; + assign rd_val___1__h13538 = + rs1_val_bypassed__h4328 - _theResult___snd__h14675 ; + assign rd_val___1__h13545 = + ((rs1_val_bypassed__h4328 ^ 32'h80000000) < + (_theResult___snd__h14675 ^ 32'h80000000)) ? 32'd1 : 32'd0 ; - assign rd_val___1__h13646 = - (rs1_val_bypassed__h4445 < _theResult___snd__h14769) ? + assign rd_val___1__h13552 = + (rs1_val_bypassed__h4328 < _theResult___snd__h14675) ? 32'd1 : 32'd0 ; - assign rd_val___1__h13653 = - rs1_val_bypassed__h4445 ^ _theResult___snd__h14769 ; - assign rd_val___1__h13660 = - rs1_val_bypassed__h4445 | _theResult___snd__h14769 ; - assign rd_val__h12443 = + assign rd_val___1__h13559 = + rs1_val_bypassed__h4328 ^ _theResult___snd__h14675 ; + assign rd_val___1__h13566 = + rs1_val_bypassed__h4328 | _theResult___snd__h14675 ; + assign rd_val__h12349 = (stage3_rg_full && stage3_rg_stage3[37] && - stage3_rg_stage3[36:32] == _theResult____h4437[24:20]) ? + stage3_rg_stage3[36:32] == _theResult____h4320[24:20]) ? stage3_rg_stage3[31:0] : gpr_regfile$read_rs2 ; - assign rd_val__h12836 = - (_theResult____h4437[14:12] == 3'b0 && - (_theResult____h4437[6:0] != 7'b0110011 || - !_theResult____h4437[30])) ? - rd_val___1__h13624 : - _theResult_____1_fst__h13636 ; - assign rd_val__h12853 = { _theResult____h4437[31:12], 12'h0 } ; - assign rd_val__h12869 = imem_rg_pc + rd_val__h12853 ; - assign rd_val__h14665 = rs1_val_bypassed__h4445 << shamt__h12793 ; - assign rd_val__h14717 = rs1_val_bypassed__h4445 >> shamt__h12793 ; - assign rd_val__h14739 = - rs1_val_bypassed__h4445 >> shamt__h12793 | - ~(32'hFFFFFFFF >> shamt__h12793) & - {32{rs1_val_bypassed__h4445[31]}} ; - assign rd_val__h7020 = + assign rd_val__h12742 = + (_theResult____h4320[14:12] == 3'b0 && + (_theResult____h4320[6:0] != 7'b0110011 || + !_theResult____h4320[30])) ? + rd_val___1__h13530 : + _theResult_____1_fst__h13542 ; + assign rd_val__h12759 = { _theResult____h4320[31:12], 12'h0 } ; + assign rd_val__h12775 = imem_rg_pc + rd_val__h12759 ; + assign rd_val__h14571 = rs1_val_bypassed__h4328 << shamt__h12699 ; + assign rd_val__h14623 = rs1_val_bypassed__h4328 >> shamt__h12699 ; + assign rd_val__h14645 = + rs1_val_bypassed__h4328 >> shamt__h12699 | + ~(32'hFFFFFFFF >> shamt__h12699) & + {32{rs1_val_bypassed__h4328[31]}} ; + assign rd_val__h6926 = (stage3_rg_full && stage3_rg_stage3[37] && - stage3_rg_stage3[36:32] == _theResult____h4437[19:15]) ? + stage3_rg_stage3[36:32] == _theResult____h4320[19:15]) ? stage3_rg_stage3[31:0] : gpr_regfile$read_rs1 ; assign rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_EQ_0_ETC___d727 = (rg_cur_priv == 2'b11 || rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] || rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) && - _theResult____h4437[31:20] == 12'b000100000101 ; - assign rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 = + _theResult____h4320[31:20] == 12'b000100000101 ; + assign rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 = rg_state == 4'd4 && - NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1319 && + NOT_near_mem_imem_exc__91_44_AND_IF_IF_NOT_nea_ETC___d1327 && csr_regfile_csr_mip_read__089_EQ_rg_prev_mip_090___d1091 && - NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1321 && + NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1329 && !stage3_rg_full && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd0 && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d642 ; - assign rg_state_2_EQ_4_083_AND_NOT_stage3_rg_full_4_5_ETC___d1299 = - rg_state == 4'd4 && !stage3_rg_full && - IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == - 2'd3 && - (!stage1_rg_full || - near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d490) ; - assign rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1474 = + assign rg_state_2_EQ_4_083_AND_rg_stop_req_107_OR_rg__ETC___d1482 = rg_state == 4'd4 && - rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1469 && + rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1477 && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd0 && !stage3_rg_full && @@ -5032,30 +5258,30 @@ module mkCPU(CLK, IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 != 2'd0 || stage3_rg_full) ; - assign rg_state_2_EQ_5_428_OR_rg_state_2_EQ_4_083_AND_ETC___d1437 = - rg_state == 4'd5 || - rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1326 && + assign rg_state_2_EQ_7_436_OR_rg_state_2_EQ_4_083_AND_ETC___d1445 = + rg_state == 4'd7 || + rg_state_2_EQ_4_083_AND_NOT_near_mem_imem_exc__ETC___d1334 && IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d752 == 4'd11 && - (x_out_trap_info_exc_code__h14151 != 4'd3 || + (x_out_trap_info_exc_code__h14057 != 4'd3 || !csr_regfile$dcsr_break_enters_debug) ; - assign rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1469 = + assign rg_stop_req_107_OR_rg_step_count_108_109_AND_s_ETC___d1477 = (rg_stop_req || rg_step_count) && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d490 && IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1084 ; - assign rs1__h7674 = { 2'b01, instr__h4435[9:7] } ; - assign rs1_val__h20224 = - (x_out_data_to_stage2_instr__h12529[14:12] == 3'b001) ? - x_out_data_to_stage2_val1__h12533 : - { 27'd0, x_out_data_to_stage2_instr__h12529[19:15] } ; - assign rs1_val_bypassed__h4445 = - (_theResult____h4437[19:15] == 5'd0) ? 32'd0 : val__h7022 ; - assign rs2_val__h12631 = - (_theResult____h4437[24:20] == 5'd0) ? 32'd0 : val__h12445 ; - assign shamt__h12793 = - (_theResult____h4437[6:0] == 7'b0010011) ? - _theResult____h4437[24:20] : - rs2_val__h12631[4:0] ; + assign rs1__h7580 = { 2'b01, instr__h4318[9:7] } ; + assign rs1_val__h20274 = + (x_out_data_to_stage2_instr__h12435[14:12] == 3'b001) ? + x_out_data_to_stage2_val1__h12439 : + { 27'd0, x_out_data_to_stage2_instr__h12435[19:15] } ; + assign rs1_val_bypassed__h4328 = + (_theResult____h4320[19:15] == 5'd0) ? 32'd0 : val__h6928 ; + assign rs2_val__h12537 = + (_theResult____h4320[24:20] == 5'd0) ? 32'd0 : val__h12351 ; + assign shamt__h12699 = + (_theResult____h4320[6:0] == 7'b0010011) ? + _theResult____h4320[24:20] : + rs2_val__h12537[4:0] ; assign stage1_rg_full_00_AND_near_mem_imem_valid_AND__ETC___d1087 = stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d490 && @@ -5087,123 +5313,123 @@ module mkCPU(CLK, !near_mem_imem_pc_BITS_31_TO_2_EQ_imem_rg_pc_BI_ETC___d8 || imem_rg_pc[1:0] == 2'b0 || near_mem$imem_instr[17:16] != 2'b11) ; - assign td1_rd__h22143 = { 3'd0, csr_regfile$csr_ret_actions[33:32] } ; - assign theResult__437_BITS_31_TO_20__q17 = _theResult____h4437[31:20] ; - assign theResult__437_BITS_31_TO_25_CONCAT_theResult__ETC__q7 = - { _theResult____h4437[31:25], _theResult____h4437[11:7] } ; - assign theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q3 = - { _theResult____h4437[31], - _theResult____h4437[7], - _theResult____h4437[30:25], - _theResult____h4437[11:8], + assign td1_rd__h22193 = { 3'd0, csr_regfile$csr_ret_actions[33:32] } ; + assign theResult__320_BITS_31_TO_20__q17 = _theResult____h4320[31:20] ; + assign theResult__320_BITS_31_TO_25_CONCAT_theResult__ETC__q7 = + { _theResult____h4320[31:25], _theResult____h4320[11:7] } ; + assign theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q3 = + { _theResult____h4320[31], + _theResult____h4320[7], + _theResult____h4320[30:25], + _theResult____h4320[11:8], 1'b0 } ; - assign theResult__437_BIT_31_CONCAT_theResult__437_BI_ETC__q4 = - { _theResult____h4437[31], - _theResult____h4437[19:12], - _theResult____h4437[20], - _theResult____h4437[30:21], + assign theResult__320_BIT_31_CONCAT_theResult__320_BI_ETC__q4 = + { _theResult____h4320[31], + _theResult____h4320[19:12], + _theResult____h4320[20], + _theResult____h4320[30:21], 1'b0 } ; - assign trace_data_rd__h27064 = { 3'd0, csr_regfile$csr_trap_actions[1:0] } ; - assign trace_data_word3__h27067 = { 32'd0, imem_rg_pc } ; - assign trap_info_tval__h14148 = - (_theResult____h4437[6:0] != 7'b1101111 && - _theResult____h4437[6:0] != 7'b1100111 && - (_theResult____h4437[6:0] != 7'b1110011 || - _theResult____h4437[14:12] != 3'b0 || - _theResult____h4437[11:7] != 5'd0 || - _theResult____h4437[19:15] != 5'd0 || - _theResult____h4437[31:20] != 12'b0 && - _theResult____h4437[31:20] != 12'b000000000001)) ? + assign trace_data_rd__h27114 = { 3'd0, csr_regfile$csr_trap_actions[1:0] } ; + assign trace_data_word3__h27117 = { 32'd0, imem_rg_pc } ; + assign trap_info_tval__h14054 = + (_theResult____h4320[6:0] != 7'b1101111 && + _theResult____h4320[6:0] != 7'b1100111 && + (_theResult____h4320[6:0] != 7'b1110011 || + _theResult____h4320[14:12] != 3'b0 || + _theResult____h4320[11:7] != 5'd0 || + _theResult____h4320[19:15] != 5'd0 || + _theResult____h4320[31:20] != 12'b0 && + _theResult____h4320[31:20] != 12'b000000000001)) ? (near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_OR__ETC___d482 ? - _theResult____h4437 : - { 16'd0, instr__h4435[15:0] }) : + _theResult____h4320 : + { 16'd0, instr__h4318[15:0] }) : IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1027 ; - assign val__h12445 = + assign val__h12351 = (IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 == 2'd2 && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d472) ? - x_out_bypass_rd_val__h6908 : - rd_val__h12443 ; - assign val__h7022 = + x_out_bypass_rd_val__h6814 : + rd_val__h12349 ; + assign val__h6928 = (IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 == 2'd2 && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d470) ? - x_out_bypass_rd_val__h6908 : - rd_val__h7020 ; - assign value__h14199 = - near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h14148 ; - assign x__h18419 = + x_out_bypass_rd_val__h6814 : + rd_val__h6926 ; + assign value__h14105 = + near_mem$imem_exc ? imem_rg_tval : trap_info_tval__h14054 ; + assign x__h18325 = NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_ETC___d211 ? - { 16'd0, instr__h4435[15:0] } : - _theResult____h4437 ; - assign x__h21266 = - (x_out_data_to_stage2_instr__h12529[19:15] == 5'd0) ? + { 16'd0, instr__h4318[15:0] } : + _theResult____h4320 ; + assign x__h21316 = + (x_out_data_to_stage2_instr__h12435[19:15] == 5'd0) ? 32'd0 : 32'd1 ; - assign x__h21274 = - (x_out_data_to_stage2_instr__h12529[19:15] == 5'd0) ? + assign x__h21324 = + (x_out_data_to_stage2_instr__h12435[19:15] == 5'd0) ? 32'hAAAAAAAA : csr_regfile$mav_csr_write ; - assign x__h27351 = - csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1478[63:0] / - _theResult____h27350 ; - assign x_out_data_to_stage2_instr__h12529 = + assign x__h27401 = + csr_regfile_read_csr_mcycle__8_MINUS_rg_start__ETC___d1486[63:0] / + _theResult____h27400 ; + assign x_out_data_to_stage2_instr__h12435 = NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_03_ETC___d211 ? - instr___1__h7068 : - instr__h4435 ; - assign x_out_data_to_stage2_rd__h12531 = - (_theResult____h4437[6:0] == 7'b1100011) ? + instr___1__h6974 : + instr__h4318 ; + assign x_out_data_to_stage2_rd__h12437 = + (_theResult____h4320[6:0] == 7'b1100011) ? 5'd0 : - _theResult____h4437[11:7] ; - assign x_out_data_to_stage2_val2__h12534 = - (_theResult____h4437[6:0] == 7'b1100011) ? - branch_target__h12635 : - rs2_val__h12631 ; - assign x_out_next_pc__h12499 = + _theResult____h4320[11:7] ; + assign x_out_data_to_stage2_val2__h12440 = + (_theResult____h4320[6:0] == 7'b1100011) ? + branch_target__h12541 : + rs2_val__h12537 ; + assign x_out_next_pc__h12405 = IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d688 ? - data_to_stage2_addr__h12523 : - fall_through_pc__h12486 ; - assign x_out_trap_info_exc_code__h14151 = + data_to_stage2_addr__h12429 : + fall_through_pc__h12392 ; + assign x_out_trap_info_exc_code__h14057 = near_mem$imem_exc ? near_mem$imem_exc_code : - alu_outputs_exc_code__h13199 ; - assign x_word3__h19995 = { 32'd0, stage2_rg_stage2[401:370] } ; - assign x_word3__h20591 = - { 52'd0, x_out_data_to_stage2_instr__h12529[31:20] } ; - assign y__h21114 = ~rs1_val__h20813 ; + alu_outputs_exc_code__h13105 ; + assign x_word3__h20017 = { 32'd0, rg_trap_info[67:36] } ; + assign x_word3__h20641 = + { 52'd0, x_out_data_to_stage2_instr__h12435[31:20] } ; + assign y__h21164 = ~rs1_val__h20863 ; always@(stage2_rg_stage2) begin case (stage2_rg_stage2[337:335]) 3'd0, 3'd1, 3'd4: - x_out_data_to_stage3_rd__h6556 = stage2_rg_stage2[334:330]; - 3'd2: x_out_data_to_stage3_rd__h6556 = 5'd0; - default: x_out_data_to_stage3_rd__h6556 = stage2_rg_stage2[334:330]; + x_out_data_to_stage3_rd__h6462 = stage2_rg_stage2[334:330]; + 3'd2: x_out_data_to_stage3_rd__h6462 = 5'd0; + default: x_out_data_to_stage3_rd__h6462 = stage2_rg_stage2[334:330]; endcase end always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64) begin case (stage2_rg_stage2[337:335]) - 3'd0: x_out_data_to_stage3_rd_val__h6557 = stage2_rg_stage2[297:266]; + 3'd0: x_out_data_to_stage3_rd_val__h6463 = stage2_rg_stage2[297:266]; 3'd1, 3'd4: - x_out_data_to_stage3_rd_val__h6557 = near_mem$dmem_word64[31:0]; - default: x_out_data_to_stage3_rd_val__h6557 = stage2_mbox$word; + x_out_data_to_stage3_rd_val__h6463 = near_mem$dmem_word64[31:0]; + default: x_out_data_to_stage3_rd_val__h6463 = stage2_mbox$word; endcase end always@(stage2_rg_stage2) begin case (stage2_rg_stage2[337:335]) - 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h6907 = stage2_rg_stage2[334:330]; - default: x_out_bypass_rd__h6907 = stage2_rg_stage2[334:330]; + 3'd0, 3'd1, 3'd4: x_out_bypass_rd__h6813 = stage2_rg_stage2[334:330]; + default: x_out_bypass_rd__h6813 = stage2_rg_stage2[334:330]; endcase end always@(stage2_rg_stage2 or - stage2_mbox$word or output_stage2___1_bypass_rd_val__h6896) + stage2_mbox$word or output_stage2___1_bypass_rd_val__h6802) begin case (stage2_rg_stage2[337:335]) - 3'd0: x_out_bypass_rd_val__h6908 = stage2_rg_stage2[297:266]; + 3'd0: x_out_bypass_rd_val__h6814 = stage2_rg_stage2[297:266]; 3'd1, 3'd4: - x_out_bypass_rd_val__h6908 = output_stage2___1_bypass_rd_val__h6896; - default: x_out_bypass_rd_val__h6908 = stage2_mbox$word; + x_out_bypass_rd_val__h6814 = output_stage2___1_bypass_rd_val__h6802; + default: x_out_bypass_rd_val__h6814 = stage2_mbox$word; endcase end always@(stage2_rg_stage2 or @@ -5255,9 +5481,9 @@ module mkCPU(CLK, IF_stage2_rg_stage2_4_BITS_337_TO_335_5_EQ_3_0_ETC___d121; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011, 7'b0010011, 7'b0010111, @@ -5266,9 +5492,9 @@ module mkCPU(CLK, 7'b0110111, 7'b1100111, 7'b1101111: - x_out_data_to_stage2_trace_data_rd__h17725 = - _theResult____h4437[11:7]; - default: x_out_data_to_stage2_trace_data_rd__h17725 = 5'd2; + x_out_data_to_stage2_trace_data_rd__h17631 = + _theResult____h4320[11:7]; + default: x_out_data_to_stage2_trace_data_rd__h17631 = 5'd2; endcase end always@(rg_cur_priv) @@ -5279,20 +5505,20 @@ module mkCPU(CLK, default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q5 = 4'd11; endcase end - always@(_theResult____h4437 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q5) + always@(_theResult____h4320 or CASE_rg_cur_priv_0b0_8_0b1_9_11__q5) begin - case (_theResult____h4437[31:20]) + case (_theResult____h4320[31:20]) 12'b0: - CASE_theResult__437_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = + CASE_theResult__320_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = CASE_rg_cur_priv_0b0_8_0b1_9_11__q5; 12'b000000000001: - CASE_theResult__437_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd3; - default: CASE_theResult__437_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd2; + CASE_theResult__320_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd3; + default: CASE_theResult__320_BITS_31_TO_20_0b0_CASE_rg__ETC__q6 = 4'd2; endcase end - always@(_theResult____h4437 or alu_outputs___1_exc_code__h13156) + always@(_theResult____h4320 or alu_outputs___1_exc_code__h13062) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011, 7'b0001111, 7'b0010011, @@ -5301,19 +5527,19 @@ module mkCPU(CLK, 7'b0110011, 7'b0110111, 7'b1100011: - alu_outputs_exc_code__h13199 = 4'd2; - 7'b1100111, 7'b1101111: alu_outputs_exc_code__h13199 = 4'd0; + alu_outputs_exc_code__h13105 = 4'd2; + 7'b1100111, 7'b1101111: alu_outputs_exc_code__h13105 = 4'd0; 7'b1110011: - alu_outputs_exc_code__h13199 = alu_outputs___1_exc_code__h13156; - default: alu_outputs_exc_code__h13199 = 4'd2; + alu_outputs_exc_code__h13105 = alu_outputs___1_exc_code__h13062; + default: alu_outputs_exc_code__h13105 = 4'd2; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d529 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d531) begin - case (_theResult____h4437[14:12]) + case (_theResult____h4320[14:12]) 3'b0: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634 = !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d529; @@ -5330,16 +5556,16 @@ module mkCPU(CLK, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634 = !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d634 = - _theResult____h4437[14:12] != 3'b111 || + _theResult____h4320[14:12] != 3'b111 || IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d529 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d531) begin - case (_theResult____h4437[14:12]) + case (_theResult____h4320[14:12]) 3'b0: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 = IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d529; @@ -5356,171 +5582,171 @@ module mkCPU(CLK, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 = IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 = - _theResult____h4437[14:12] == 3'b111 && + _theResult____h4320[14:12] == 3'b111 && !IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d533; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: - CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4437[14:12] != 3'b0 && - _theResult____h4437[14:12] != 3'b100 && - _theResult____h4437[14:12] != 3'b001 && - _theResult____h4437[14:12] != 3'b101 && - _theResult____h4437[14:12] != 3'b010; + CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = + _theResult____h4320[14:12] != 3'b0 && + _theResult____h4320[14:12] != 3'b100 && + _theResult____h4320[14:12] != 3'b001 && + _theResult____h4320[14:12] != 3'b101 && + _theResult____h4320[14:12] != 3'b010; 7'b0100011: - CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4437[14:12] != 3'b0 && - _theResult____h4437[14:12] != 3'b001 && - _theResult____h4437[14:12] != 3'b010; - default: CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = - _theResult____h4437[6:0] != 7'b0101111 || - _theResult____h4437[31:27] != 5'b00010 && - _theResult____h4437[31:27] != 5'b00011 && - _theResult____h4437[31:27] != 5'b0 && - _theResult____h4437[31:27] != 5'b00001 && - _theResult____h4437[31:27] != 5'b01100 && - _theResult____h4437[31:27] != 5'b01000 && - _theResult____h4437[31:27] != 5'b00100 && - _theResult____h4437[31:27] != 5'b10000 && - _theResult____h4437[31:27] != 5'b11000 && - _theResult____h4437[31:27] != 5'b10100 && - _theResult____h4437[31:27] != 5'b11100 || - _theResult____h4437[14:12] != 3'b010; + CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = + _theResult____h4320[14:12] != 3'b0 && + _theResult____h4320[14:12] != 3'b001 && + _theResult____h4320[14:12] != 3'b010; + default: CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 = + _theResult____h4320[6:0] != 7'b0101111 || + _theResult____h4320[31:27] != 5'b00010 && + _theResult____h4320[31:27] != 5'b00011 && + _theResult____h4320[31:27] != 5'b0 && + _theResult____h4320[31:27] != 5'b00001 && + _theResult____h4320[31:27] != 5'b01100 && + _theResult____h4320[31:27] != 5'b01000 && + _theResult____h4320[31:27] != 5'b00100 && + _theResult____h4320[31:27] != 5'b10000 && + _theResult____h4320[31:27] != 5'b11000 && + _theResult____h4320[31:27] != 5'b10100 && + _theResult____h4320[31:27] != 5'b11100 || + _theResult____h4320[14:12] != 3'b010; endcase end - always@(_theResult____h4437 or - CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 or + always@(_theResult____h4320 or + CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8 or NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d570) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0010011, 7'b0110011: - CASE_theResult__437_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = + CASE_theResult__320_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_ETC___d570; - default: CASE_theResult__437_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = - _theResult____h4437[6:0] != 7'b0110111 && - _theResult____h4437[6:0] != 7'b0010111 && - CASE_theResult__437_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8; + default: CASE_theResult__320_BITS_6_TO_0_0b10011_NOT_IF_ETC__q9 = + _theResult____h4320[6:0] != 7'b0110111 && + _theResult____h4320[6:0] != 7'b0010111 && + CASE_theResult__320_BITS_6_TO_0_0b11_NOT_theRe_ETC__q8; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: - CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4437[14:12] == 3'b0 || - _theResult____h4437[14:12] == 3'b100 || - _theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101 || - _theResult____h4437[14:12] == 3'b010; + CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10 = + _theResult____h4320[14:12] == 3'b0 || + _theResult____h4320[14:12] == 3'b100 || + _theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101 || + _theResult____h4320[14:12] == 3'b010; 7'b0100011: - CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4437[14:12] == 3'b0 || - _theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b010; - default: CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10 = - _theResult____h4437[6:0] == 7'b0101111 && - (_theResult____h4437[31:27] == 5'b00010 || - _theResult____h4437[31:27] == 5'b00011 || - _theResult____h4437[31:27] == 5'b0 || - _theResult____h4437[31:27] == 5'b00001 || - _theResult____h4437[31:27] == 5'b01100 || - _theResult____h4437[31:27] == 5'b01000 || - _theResult____h4437[31:27] == 5'b00100 || - _theResult____h4437[31:27] == 5'b10000 || - _theResult____h4437[31:27] == 5'b11000 || - _theResult____h4437[31:27] == 5'b10100 || - _theResult____h4437[31:27] == 5'b11100) && - _theResult____h4437[14:12] == 3'b010; + CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10 = + _theResult____h4320[14:12] == 3'b0 || + _theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b010; + default: CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10 = + _theResult____h4320[6:0] == 7'b0101111 && + (_theResult____h4320[31:27] == 5'b00010 || + _theResult____h4320[31:27] == 5'b00011 || + _theResult____h4320[31:27] == 5'b0 || + _theResult____h4320[31:27] == 5'b00001 || + _theResult____h4320[31:27] == 5'b01100 || + _theResult____h4320[31:27] == 5'b01000 || + _theResult____h4320[31:27] == 5'b00100 || + _theResult____h4320[31:27] == 5'b10000 || + _theResult____h4320[31:27] == 5'b11000 || + _theResult____h4320[31:27] == 5'b10100 || + _theResult____h4320[31:27] == 5'b11100) && + _theResult____h4320[14:12] == 3'b010; endcase end - always@(_theResult____h4437 or - CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10 or + always@(_theResult____h4320 or + CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10 or IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d659) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0010011, 7'b0110011: - CASE_theResult__437_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = + CASE_theResult__320_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d659; - default: CASE_theResult__437_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = - _theResult____h4437[6:0] == 7'b0110111 || - _theResult____h4437[6:0] == 7'b0010111 || - CASE_theResult__437_BITS_6_TO_0_0b11_theResult_ETC__q10; + default: CASE_theResult__320_BITS_6_TO_0_0b10011_IF_NOT_ETC__q11 = + _theResult____h4320[6:0] == 7'b0110111 || + _theResult____h4320[6:0] == 7'b0010111 || + CASE_theResult__320_BITS_6_TO_0_0b11_theResult_ETC__q10; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or rg_cur_priv or IF_rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_E_ETC___d729) begin - case (_theResult____h4437[31:20]) + case (_theResult____h4320[31:20]) 12'b0, 12'b000000000001: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d731 = 4'd11; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d731 = (rg_cur_priv == 2'b11 && - _theResult____h4437[31:20] == 12'b001100000010) ? + _theResult____h4320[31:20] == 12'b001100000010) ? 4'd7 : IF_rg_cur_priv_9_EQ_0b11_10_OR_rg_cur_priv_9_E_ETC___d729; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[14:12]) + case (_theResult____h4320[14:12]) 3'b0, 3'b001, 3'b010, 3'b100, 3'b101: - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = 4'd0; - default: CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = 4'd0; + default: CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 = 4'd11; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[14:12]) - 3'b0: CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd4; - 3'b001: CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd5; - default: CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd11; + case (_theResult____h4320[14:12]) + 3'b0: CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd4; + 3'b001: CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd5; + default: CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13 = 4'd11; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[14:12]) + case (_theResult____h4320[14:12]) 3'b0, 3'b001, 3'b010: - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd0; - default: CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd0; + default: CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 = 4'd11; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d731) begin - case (_theResult____h4437[14:12]) + case (_theResult____h4320[14:12]) 3'b0: - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = - (_theResult____h4437[11:7] == 5'd0 && - _theResult____h4437[19:15] == 5'd0) ? + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = + (_theResult____h4320[11:7] == 5'd0 && + _theResult____h4320[19:15] == 5'd0) ? IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d731 : 4'd11; 3'b001, 3'b101: - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd2; + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd2; 3'b010, 3'b011, 3'b110, 3'b111: - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd3; - 3'd4: CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd11; + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd3; + 3'd4: CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15 = 4'd11; endcase end - always@(_theResult____h4437 or - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 or - CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13 or + always@(_theResult____h4320 or + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12 or + CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13 or IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d696 or - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 or - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15) + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14 or + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12; + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q12; 7'b0001111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = - CASE_theResult__437_BITS_14_TO_12_0b0_4_0b1_5_11__q13; + CASE_theResult__320_BITS_14_TO_12_0b0_4_0b1_5_11__q13; 7'b0010011, 7'b0110011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = IF_NOT_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_P_ETC___d696; @@ -5528,43 +5754,43 @@ module mkCPU(CLK, IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = 4'd0; 7'b0100011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = - CASE_theResult__437_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14; + CASE_theResult__320_BITS_14_TO_12_0b0_0_0b1_0__ETC__q14; 7'b0101111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = - ((_theResult____h4437[31:27] == 5'b00010 || - _theResult____h4437[31:27] == 5'b00011 || - _theResult____h4437[31:27] == 5'b0 || - _theResult____h4437[31:27] == 5'b00001 || - _theResult____h4437[31:27] == 5'b01100 || - _theResult____h4437[31:27] == 5'b01000 || - _theResult____h4437[31:27] == 5'b00100 || - _theResult____h4437[31:27] == 5'b10000 || - _theResult____h4437[31:27] == 5'b11000 || - _theResult____h4437[31:27] == 5'b10100 || - _theResult____h4437[31:27] == 5'b11100) && - _theResult____h4437[14:12] == 3'b010) ? + ((_theResult____h4320[31:27] == 5'b00010 || + _theResult____h4320[31:27] == 5'b00011 || + _theResult____h4320[31:27] == 5'b0 || + _theResult____h4320[31:27] == 5'b00001 || + _theResult____h4320[31:27] == 5'b01100 || + _theResult____h4320[31:27] == 5'b01000 || + _theResult____h4320[31:27] == 5'b00100 || + _theResult____h4320[31:27] == 5'b10000 || + _theResult____h4320[31:27] == 5'b11000 || + _theResult____h4320[31:27] == 5'b10100 || + _theResult____h4320[31:27] == 5'b11100) && + _theResult____h4320[14:12] == 3'b010) ? 4'd0 : 4'd11; 7'b1110011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = - CASE_theResult__437_BITS_14_TO_12_0b0_IF_theRe_ETC__q15; + CASE_theResult__320_BITS_14_TO_12_0b0_IF_theRe_ETC__q15; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 = 4'd11; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b1100011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d750 = - (_theResult____h4437[14:12] != 3'b0 && - _theResult____h4437[14:12] != 3'b001 && - _theResult____h4437[14:12] != 3'b100 && - _theResult____h4437[14:12] != 3'b101 && - _theResult____h4437[14:12] != 3'b110 && - _theResult____h4437[14:12] != 3'b111) ? + (_theResult____h4320[14:12] != 3'b0 && + _theResult____h4320[14:12] != 3'b001 && + _theResult____h4320[14:12] != 3'b100 && + _theResult____h4320[14:12] != 3'b101 && + _theResult____h4320[14:12] != 3'b110 && + _theResult____h4320[14:12] != 3'b111) ? 4'd11 : (IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d540 ? 4'd1 : @@ -5572,206 +5798,206 @@ module mkCPU(CLK, 7'b1100111, 7'b1101111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d750 = 4'd1; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d750 = - (_theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[31:25] == 7'b0000001) ? + (_theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[31:25] == 7'b0000001) ? 4'd0 : - (((_theResult____h4437[6:0] == 7'b0010011 || - _theResult____h4437[6:0] == 7'b0110011) && - (_theResult____h4437[14:12] == 3'b001 || - _theResult____h4437[14:12] == 3'b101)) ? - (_theResult____h4437[25] ? 4'd11 : 4'd0) : + (((_theResult____h4320[6:0] == 7'b0010011 || + _theResult____h4320[6:0] == 7'b0110011) && + (_theResult____h4320[14:12] == 3'b001 || + _theResult____h4320[14:12] == 3'b101)) ? + (_theResult____h4320[25] ? 4'd11 : 4'd0) : IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d746); endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: - CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd1; + CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd1; 7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111: - CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd0; + CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd0; 7'b0100011: - CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd2; - default: CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd4; + CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd2; + default: CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16 = 3'd4; endcase end - always@(_theResult____h4437 or - CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16) + always@(_theResult____h4320 or + CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b1100011, 7'b1100111, 7'b1101111: IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831 = 3'd0; default: IF_NOT_stage1_rg_full_00_01_OR_NOT_near_mem_im_ETC___d831 = - (_theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[31:25] == 7'b0000001) ? + (_theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[31:25] == 7'b0000001) ? 3'd3 : - CASE_theResult__437_BITS_6_TO_0_0b11_1_0b10011_ETC__q16; + CASE_theResult__320_BITS_6_TO_0_0b11_1_0b10011_ETC__q16; endcase end - always@(_theResult____h4437 or - rs1_val_bypassed__h4445 or - alu_outputs___1_trace_data_word3__h17603 or - alu_outputs___1_trace_data_word3__h17622) + always@(_theResult____h4320 or + rs1_val_bypassed__h4328 or + alu_outputs___1_trace_data_word3__h17509 or + alu_outputs___1_trace_data_word3__h17528) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: - x_out_data_to_stage2_trace_data_word3__h17728 = - alu_outputs___1_trace_data_word3__h17603; + x_out_data_to_stage2_trace_data_word3__h17634 = + alu_outputs___1_trace_data_word3__h17509; 7'b0100011: - x_out_data_to_stage2_trace_data_word3__h17728 = - alu_outputs___1_trace_data_word3__h17622; - default: x_out_data_to_stage2_trace_data_word3__h17728 = - { 32'd0, rs1_val_bypassed__h4445 }; + x_out_data_to_stage2_trace_data_word3__h17634 = + alu_outputs___1_trace_data_word3__h17528; + default: x_out_data_to_stage2_trace_data_word3__h17634 = + { 32'd0, rs1_val_bypassed__h4328 }; endcase end - always@(_theResult____h4437 or - _theResult_____1_fst__h13671 or - rd_val___1__h13639 or - rd_val___1__h13646 or rd_val___1__h13653 or rd_val___1__h13660) + always@(_theResult____h4320 or + _theResult_____1_fst__h13577 or + rd_val___1__h13545 or + rd_val___1__h13552 or rd_val___1__h13559 or rd_val___1__h13566) begin - case (_theResult____h4437[14:12]) - 3'b010: _theResult_____1_fst__h13643 = rd_val___1__h13639; - 3'b011: _theResult_____1_fst__h13643 = rd_val___1__h13646; - 3'b100: _theResult_____1_fst__h13643 = rd_val___1__h13653; - 3'b110: _theResult_____1_fst__h13643 = rd_val___1__h13660; - default: _theResult_____1_fst__h13643 = _theResult_____1_fst__h13671; + case (_theResult____h4320[14:12]) + 3'b010: _theResult_____1_fst__h13549 = rd_val___1__h13545; + 3'b011: _theResult_____1_fst__h13549 = rd_val___1__h13552; + 3'b100: _theResult_____1_fst__h13549 = rd_val___1__h13559; + 3'b110: _theResult_____1_fst__h13549 = rd_val___1__h13566; + default: _theResult_____1_fst__h13549 = _theResult_____1_fst__h13577; endcase end - always@(_theResult____h4437 or - rs1_val_bypassed__h4445 or - eaddr__h12887 or - eaddr__h12907 or - alu_outputs___1_addr__h12657 or - alu_outputs___1_addr__h12704 or alu_outputs___1_addr__h12678) + always@(_theResult____h4320 or + rs1_val_bypassed__h4328 or + eaddr__h12793 or + eaddr__h12813 or + alu_outputs___1_addr__h12563 or + alu_outputs___1_addr__h12610 or alu_outputs___1_addr__h12584) begin - case (_theResult____h4437[6:0]) - 7'b0000011: x_out_data_to_stage2_addr__h12532 = eaddr__h12887; - 7'b0100011: x_out_data_to_stage2_addr__h12532 = eaddr__h12907; + case (_theResult____h4320[6:0]) + 7'b0000011: x_out_data_to_stage2_addr__h12438 = eaddr__h12793; + 7'b0100011: x_out_data_to_stage2_addr__h12438 = eaddr__h12813; 7'b1100011: - x_out_data_to_stage2_addr__h12532 = alu_outputs___1_addr__h12657; + x_out_data_to_stage2_addr__h12438 = alu_outputs___1_addr__h12563; 7'b1100111: - x_out_data_to_stage2_addr__h12532 = alu_outputs___1_addr__h12704; + x_out_data_to_stage2_addr__h12438 = alu_outputs___1_addr__h12610; 7'b1101111: - x_out_data_to_stage2_addr__h12532 = alu_outputs___1_addr__h12678; - default: x_out_data_to_stage2_addr__h12532 = rs1_val_bypassed__h4445; + x_out_data_to_stage2_addr__h12438 = alu_outputs___1_addr__h12584; + default: x_out_data_to_stage2_addr__h12438 = rs1_val_bypassed__h4328; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875 or - alu_outputs___1_addr__h12657 or - alu_outputs___1_addr__h12704 or alu_outputs___1_addr__h12678) + alu_outputs___1_addr__h12563 or + alu_outputs___1_addr__h12610 or alu_outputs___1_addr__h12584) begin - case (_theResult____h4437[6:0]) - 7'b1100011: x__h18327 = alu_outputs___1_addr__h12657; - 7'b1100111: x__h18327 = alu_outputs___1_addr__h12704; - 7'b1101111: x__h18327 = alu_outputs___1_addr__h12678; - default: x__h18327 = + case (_theResult____h4320[6:0]) + 7'b1100011: x__h18233 = alu_outputs___1_addr__h12563; + 7'b1100111: x__h18233 = alu_outputs___1_addr__h12610; + 7'b1101111: x__h18233 = alu_outputs___1_addr__h12584; + default: x__h18233 = IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875; endcase end - always@(_theResult____h4437 or imem_rg_pc or data_to_stage2_addr__h12523) + always@(_theResult____h4320 or imem_rg_pc or data_to_stage2_addr__h12429) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b1100111, 7'b1101111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1027 = - data_to_stage2_addr__h12523; + data_to_stage2_addr__h12429; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1027 = - (_theResult____h4437[6:0] == 7'b1110011 && - _theResult____h4437[14:12] == 3'b0 && - _theResult____h4437[11:7] == 5'd0 && - _theResult____h4437[19:15] == 5'd0 && - _theResult____h4437[31:20] == 12'b000000000001) ? + (_theResult____h4320[6:0] == 7'b1110011 && + _theResult____h4320[14:12] == 3'b0 && + _theResult____h4320[11:7] == 5'd0 && + _theResult____h4320[19:15] == 5'd0 && + _theResult____h4320[31:20] == 12'b000000000001) ? imem_rg_pc : 32'd0; endcase end - always@(_theResult____h4437 or - alu_outputs___1_val1__h13181 or - rd_val__h12836 or - rd_val__h12869 or rd_val__h12853 or alu_outputs___1_val1__h13160) + always@(_theResult____h4320 or + alu_outputs___1_val1__h13087 or + rd_val__h12742 or + rd_val__h12775 or rd_val__h12759 or alu_outputs___1_val1__h13066) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0010011, 7'b0110011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 = - rd_val__h12836; + rd_val__h12742; 7'b0010111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 = - rd_val__h12869; + rd_val__h12775; 7'b0110111: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 = - rd_val__h12853; + rd_val__h12759; 7'b1110011: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 = - alu_outputs___1_val1__h13160; + alu_outputs___1_val1__h13066; default: IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d942 = - alu_outputs___1_val1__h13181; + alu_outputs___1_val1__h13087; endcase end - always@(_theResult____h4437 or - rd_val__h12869 or rd_val__h12836 or rd_val__h12853) + always@(_theResult____h4320 or + rd_val__h12775 or rd_val__h12742 or rd_val__h12759) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0010011, 7'b0110011: - CASE_theResult__437_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = - rd_val__h12836; + CASE_theResult__320_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = + rd_val__h12742; 7'b0110111: - CASE_theResult__437_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = - rd_val__h12853; - default: CASE_theResult__437_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = - rd_val__h12869; + CASE_theResult__320_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = + rd_val__h12759; + default: CASE_theResult__320_BITS_6_TO_0_0b10011_rd_val_ETC__q18 = + rd_val__h12775; endcase end - always@(_theResult____h4437 or + always@(_theResult____h4320 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1221 or IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b1100111, 7'b1101111: - x__h18596 = + x__h18502 = IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875; - default: x__h18596 = + default: x__h18502 = IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d1221; endcase end - always@(_theResult____h4437 or - rs1_val_bypassed__h4445 or + always@(_theResult____h4320 or + rs1_val_bypassed__h4328 or IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d943 or IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b1100111, 7'b1101111: - x_out_data_to_stage2_val1__h12533 = + x_out_data_to_stage2_val1__h12439 = IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS_2_9_ETC___d875; - default: x_out_data_to_stage2_val1__h12533 = - (_theResult____h4437[6:0] == 7'b0110011 && - _theResult____h4437[31:25] == 7'b0000001) ? - rs1_val_bypassed__h4445 : + default: x_out_data_to_stage2_val1__h12439 = + (_theResult____h4320[6:0] == 7'b0110011 && + _theResult____h4320[31:25] == 7'b0000001) ? + rs1_val_bypassed__h4328 : IF_IF_NOT_near_mem_imem_pc_EQ_imem_rg_pc_PLUS__ETC___d943; endcase end - always@(x_out_data_to_stage2_instr__h12529 or - x_out_data_to_stage2_val1__h12533) + always@(x_out_data_to_stage2_instr__h12435 or + x_out_data_to_stage2_val1__h12439) begin - case (x_out_data_to_stage2_instr__h12529[14:12]) - 3'b010, 3'b011: rs1_val__h20813 = x_out_data_to_stage2_val1__h12533; - default: rs1_val__h20813 = - { 27'd0, x_out_data_to_stage2_instr__h12529[19:15] }; + case (x_out_data_to_stage2_instr__h12435[14:12]) + 3'b010, 3'b011: rs1_val__h20863 = x_out_data_to_stage2_val1__h12439; + default: rs1_val__h20863 = + { 27'd0, x_out_data_to_stage2_instr__h12435[19:15] }; endcase end - always@(_theResult____h4437) + always@(_theResult____h4320) begin - case (_theResult____h4437[6:0]) + case (_theResult____h4320[6:0]) 7'b0000011: - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd8; + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd8; 7'b0001111, 7'b1100011, 7'b1110011: - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd5; + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd5; 7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111, 7'b1100111, 7'b1101111: - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd6; + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd6; 7'b0100011: - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd10; + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd10; 7'b0101111: - CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd11; - default: CASE_theResult__437_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = + CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd11; + default: CASE_theResult__320_BITS_6_TO_0_0b11_8_0b1111__ETC__q19 = 4'd12; endcase end @@ -5858,6 +6084,12 @@ module mkCPU(CLK, rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN; if (rg_start_CPI_instrs$EN) rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN; + if (rg_trap_info$EN) + rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN; + if (rg_trap_instr$EN) + rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN; + if (rg_trap_trace_data$EN) + rg_trap_trace_data <= `BSV_ASSIGNMENT_DELAY rg_trap_trace_data$D_IN; if (stage2_rg_stage2$EN) stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN; if (stage3_rg_stage3$EN) @@ -5890,6 +6122,10 @@ module mkCPU(CLK, rg_state = 4'hA; rg_step_count = 1'h0; rg_stop_req = 1'h0; + rg_trap_info = 68'hAAAAAAAAAAAAAAAAA; + rg_trap_instr = 32'hAAAAAAAA; + rg_trap_trace_data = + 234'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; stage1_rg_full = 1'h0; stage2_rg_full = 1'h0; stage2_rg_resetting = 1'h0; @@ -6114,8 +6350,8 @@ module mkCPU(CLK, IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 != 2'd1 && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 != 2'd3) $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6556, - x_out_data_to_stage3_rd_val__h6557); + x_out_data_to_stage3_rd__h6462, + x_out_data_to_stage3_rd_val__h6463); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd0) @@ -6363,7 +6599,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 != 2'd0) - $write("Rd %0d ", x_out_bypass_rd__h6907); + $write("Rd %0d ", x_out_bypass_rd__h6813); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 == 2'd0) @@ -6376,7 +6612,7 @@ module mkCPU(CLK, if (WILL_FIRE_RL_rl_show_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 != 2'd0 && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d186 != 2'd1) - $write("rd_val:%h", x_out_bypass_rd_val__h6908); + $write("rd_val:%h", x_out_bypass_rd_val__h6814); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("\n"); @@ -6384,7 +6620,7 @@ module mkCPU(CLK, if (WILL_FIRE_RL_rl_show_pipe) $display(" Stage1: pc 0x%08h instr 0x%08h priv %0d", imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write(" "); @@ -6547,7 +6783,7 @@ module mkCPU(CLK, near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691) $write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n", imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); @@ -6623,7 +6859,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691) - $write(" rd:%0d\n", x_out_data_to_stage2_rd__h12531); + $write(" rd:%0d\n", x_out_data_to_stage2_rd__h12437); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); if (RST_N != `BSV_RESET_VALUE) @@ -6638,9 +6874,9 @@ module mkCPU(CLK, if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691) $write(" addr:%h val1:%h val2:%h}", - x_out_data_to_stage2_addr__h12532, - x_out_data_to_stage2_val1__h12533, - x_out_data_to_stage2_val2__h12534); + x_out_data_to_stage2_addr__h12438, + x_out_data_to_stage2_val1__h12439, + x_out_data_to_stage2_val2__h12440); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); if (RST_N != `BSV_RESET_VALUE) @@ -6790,7 +7026,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d642) - $write("'h%h", x_out_trap_info_exc_code__h14151); + $write("'h%h", x_out_trap_info_exc_code__h14057); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691) @@ -6818,7 +7054,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d642) - $write("'h%h", value__h14199, " }"); + $write("'h%h", value__h14105, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d691) @@ -6832,7 +7068,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full && near_mem_imem_valid_AND_near_mem_imem_pc_EQ_im_ETC___d490) - $write(" next_pc 0x%08h", x_out_next_pc__h12499); + $write(" next_pc 0x%08h", x_out_next_pc__h12405); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write(""); if (RST_N != `BSV_RESET_VALUE) @@ -6842,44 +7078,42 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_mip_cmd && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_mip_cmd: MIP new 0x%0h, old 0x%0h", + $display("%0d: %m.rl_stage1_mip_cmd: MIP new 0x%0h, old 0x%0h", csr_regfile$read_csr_mcycle, csr_regfile$csr_mip_read, rg_prev_mip); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_SFENCE_VMA", - csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run_redundant && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_run_redundant", + $display("%0d: %m.rl_debug_run_redundant", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run_redundant) - $display("%0d: CPU.debug_run_redundant: CPU already running.", + $display("%0d: %m.debug_run_redundant: CPU already running.", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_halt_redundant", + $display("%0d: %m.rl_debug_halt_redundant", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant) - $display("%0d: CPU.rl_debug_halt_redundant: CPU already halted.", + $display("%0d: %m.rl_debug_halt_redundant: CPU already halted.", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant) $write(" state = "); @@ -6903,18 +7137,21 @@ module mkCPU(CLK, $write("CPU_TRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd6) - $write("CPU_SPLIT_FETCH"); + $write("CPU_START_TRAP_HANDLER"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd7) - $write("CPU_CSRRX_RESTART"); + $write("CPU_CSRRx_TRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd8) - $write("CPU_FENCE_I"); + $write("CPU_CSRRX_RESTART"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd9) - $write("CPU_FENCE"); + $write("CPU_FENCE_I"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd10) + $write("CPU_FENCE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd11) $write("CPU_SFENCE_VMA"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state != 4'd0 && @@ -6927,59 +7164,60 @@ module mkCPU(CLK, rg_state != 4'd7 && rg_state != 4'd8 && rg_state != 4'd9 && - rg_state != 4'd10) + rg_state != 4'd10 && + rg_state != 4'd11) $write("CPU_WFI_PAUSED"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt_redundant) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_read_gpr && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_read_gpr: reg %0d => 0x%0h", + $display("%0d: %m.rl_debug_read_gpr: reg %0d => 0x%0h", csr_regfile$read_csr_mcycle, f_gpr_reqs$D_OUT[36:32], gpr_regfile$read_rs1_port2); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_write_gpr && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_write_gpr: reg %0d <= 0x%0h", + $display("%0d: %m.rl_debug_write_gpr: reg %0d <= 0x%0h", csr_regfile$read_csr_mcycle, f_gpr_reqs$D_OUT[36:32], f_gpr_reqs$D_OUT[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_gpr_access_busy && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_gpr_access_busy", + $display("%0d: %m.rl_debug_gpr_access_busy", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_read_csr && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_read_csr: csr %0d => 0x%0h", + $display("%0d: %m.rl_debug_read_csr: csr %0d => 0x%0h", csr_regfile$read_csr_mcycle, f_csr_reqs$D_OUT[43:32], csr_regfile$read_csr_port2[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_run", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_debug_run", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" CPU_Stage1.enq: 0x%08h", csr_regfile$read_dpc); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run) - $display("%0d: CPU.rl_debug_run: restart at PC = 0x%0h", + $display("%0d: %m.rl_debug_run: restart at PC = 0x%0h", csr_regfile$read_csr_mcycle, csr_regfile$read_dpc); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_run && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_run: 'run' from dpc 0x%0h", + $display("%0d: %m.rl_debug_run: 'run' from dpc 0x%0h", csr_regfile$read_csr_mcycle, csr_regfile$read_dpc); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_write_csr && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_write_csr: csr 0x%0h 0x%0h <= 0x%0h", + $display("%0d: %m.rl_debug_write_csr: csr 0x%0h 0x%0h <= 0x%0h", csr_regfile$read_csr_mcycle, f_csr_reqs$D_OUT[43:32], f_csr_reqs$D_OUT[31:0], @@ -6987,100 +7225,100 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_csr_access_busy && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_csr_access_busy", + $display("%0d: %m.rl_debug_csr_access_busy", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_W && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && - cur_verbosity__h3142 == 4'd1) + cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_W && csr_regfile$access_permitted_1 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12529[19:15], - rs1_val__h20224, - x_out_data_to_stage2_instr__h12529[31:20], + x_out_data_to_stage2_instr__h12435[19:15], + rs1_val__h20274, + x_out_data_to_stage2_instr__h12435[31:20], csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h12529[11:7]); + x_out_data_to_stage2_instr__h12435[11:7]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && - cur_verbosity__h3142 == 4'd1) + cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_W && !csr_regfile$access_permitted_1 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" rl_stage1_CSRR_W: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12529[19:15], - rs1_val__h20224, - x_out_data_to_stage2_instr__h12529[31:20], - x_out_data_to_stage2_instr__h12529[11:7]); + x_out_data_to_stage2_instr__h12435[19:15], + rs1_val__h20274, + x_out_data_to_stage2_instr__h12435[31:20], + x_out_data_to_stage2_instr__h12435[11:7]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_CSRR_S_or_C", + $display("%0d: %m.rl_stage1_CSRR_S_or_C", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && csr_regfile$access_permitted_2 && - cur_verbosity__h3142 == 4'd1) + cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && csr_regfile$access_permitted_2 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12529[19:15], - rs1_val__h20813, - x_out_data_to_stage2_instr__h12529[31:20], + x_out_data_to_stage2_instr__h12435[19:15], + rs1_val__h20863, + x_out_data_to_stage2_instr__h12435[31:20], csr_regfile$read_csr[31:0], - x_out_data_to_stage2_instr__h12529[11:7]); + x_out_data_to_stage2_instr__h12435[11:7]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && !csr_regfile$access_permitted_2 && - cur_verbosity__h3142 == 4'd1) + cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C && !csr_regfile$access_permitted_2 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" rl_stage1_CSRR_S_or_C: Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d", - x_out_data_to_stage2_instr__h12529[19:15], - rs1_val__h20813, - x_out_data_to_stage2_instr__h12529[31:20], - x_out_data_to_stage2_instr__h12529[11:7]); + x_out_data_to_stage2_instr__h12435[19:15], + rs1_val__h20863, + x_out_data_to_stage2_instr__h12435[31:20], + x_out_data_to_stage2_instr__h12435[11:7]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_xRET && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_xRET", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3142 != 4'd0) + if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h2930 != 4'd0) $display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d", csr_regfile$csr_ret_actions[65:34], csr_regfile$csr_ret_actions[31:0], @@ -7088,43 +7326,43 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_FENCE_I && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_FENCE_I && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_FENCE && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_FENCE && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_WFI && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_WFI", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_WFI && @@ -7133,38 +7371,38 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_trap && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_trap", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3142 != 4'd0) - $display("%0d: CPU.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", + if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2930 != 4'd0) + $display("%0d: %m.rl_stage1_trap: priv:%0d mcause:0x%0h epc:0x%0h", csr_regfile$read_csr_mcycle, rg_cur_priv, csr_regfile$csr_trap_actions[33:2], imem_rg_pc); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h3142 != 4'd0) + if (WILL_FIRE_RL_rl_stage1_trap && cur_verbosity__h2930 != 4'd0) $display(" tval:0x%0h new pc:0x%0h new mstatus:0x%0h", - value__h14199, + value__h14105, csr_regfile$csr_trap_actions[97:66], csr_regfile$csr_trap_actions[65:34]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_trap_BREAK_to_Debug_Mode", + $display("%0d: %m.rl_trap_BREAK_to_Debug_Mode", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode) - $display("%0d: CPU.rl_trap_BREAK_to_Debug_Mode: PC 0x%08h instr 0x%08h", + $display("%0d: %m.rl_trap_BREAK_to_Debug_Mode: PC 0x%08h instr 0x%08h", csr_regfile$read_csr_mcycle, imem_rg_pc, - x_out_data_to_stage2_instr__h12529); + x_out_data_to_stage2_instr__h12435); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) @@ -7172,30 +7410,30 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_BREAK_cache_flush_finish && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_BREAK_cache_flush_finish", + $display("%0d: %m.rl_BREAK_cache_flush_finish", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_stop && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_stop", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_stop", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_stop && rg_stop_req) - $display("%0d: CPU.rl_stage1_stop: Stop for debugger. minstret %0d priv %0d PC 0x%0h instr 0x%0h", + $display("%0d: %m.rl_stage1_stop: Stop for debugger. minstret %0d priv %0d PC 0x%0h instr 0x%0h", csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret, rg_cur_priv, imem_rg_pc, - x_out_data_to_stage2_instr__h12529); + x_out_data_to_stage2_instr__h12435); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_stop && rg_stop_req) $display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'", - cpi__h27352, - cpifrac__h27353, - delta_CPI_cycles__h27348, - _theResult____h27350); + cpi__h27402, + cpifrac__h27403, + delta_CPI_cycles__h27398, + _theResult____h27400); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_stop && !rg_stop_req) - $display("%0d: CPU.rl_stage1_stop: Stop after single-step. PC = 0x%08h", + $display("%0d: %m.rl_stage1_stop: Stop after single-step. PC = 0x%08h", csr_regfile$read_csr_mcycle, imem_rg_pc); if (WILL_FIRE_RL_imem_rl_assert_fail) @@ -7208,17 +7446,17 @@ module mkCPU(CLK, soc_map$m_pc_reset_value[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: restart at PC = 0x%0h", + $display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h", csr_regfile$read_csr_mcycle, soc_map$m_pc_reset_value[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset) - $display("%0d: CPU.rl_reset_complete: entering DEBUG_MODE", + $display("%0d: %m.rl_reset_complete: entering DEBUG_MODE", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_pipe && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_pipe", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) @@ -7262,8 +7500,8 @@ module mkCPU(CLK, IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd2 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $write(" grd:%0d rd_val:%h\n", - x_out_data_to_stage3_rd__h6556, - x_out_data_to_stage3_rd_val__h6557); + x_out_data_to_stage3_rd__h6462, + x_out_data_to_stage3_rd_val__h6463); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd2 && @@ -7272,7 +7510,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_pipe && IF_stage2_rg_full_3_THEN_IF_stage2_rg_stage2_4_ETC___d124 == 2'd2 && - cur_verbosity__h3142 == 4'd1) + cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, stage2_rg_stage2[401:370], @@ -7289,50 +7527,50 @@ module mkCPU(CLK, if (WILL_FIRE_RL_rl_pipe && NOT_stage1_rg_full_00_01_OR_NOT_near_mem_imem__ETC___d1268 && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12499); + $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12405); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_halt", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_debug_halt", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_debug_halt && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_debug_halt", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_debug_halt", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage2_nonpipe && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_trap && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, - stage2_rg_stage2[401:370], - stage2_rg_stage2[369:338], + rg_trap_info[67:36], + rg_trap_instr, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage2_nonpipe && cur_verbosity__h3142 != 4'd0) + if (WILL_FIRE_RL_rl_trap && cur_verbosity__h2930 != 4'd0) $display(" mcause:0x%0h epc 0x%0h tval:0x%0h new pc 0x%0h, new mstatus 0x%0h", csr_regfile$csr_trap_actions[33:2], - stage2_rg_stage2[401:370], - stage2_rg_stage2[329:298], + rg_trap_info[67:36], + rg_trap_info[31:0], csr_regfile$csr_trap_actions[97:66], csr_regfile$csr_trap_actions[65:34]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12499); + $display(" CPU_Stage1.enq: 0x%08h", x_out_next_pc__h12405); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display("%0d: rl_stage1_restart_after_csrrx: minstret:%0d pc:%0x cur_priv:%0d", csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret, - x_out_next_pc__h12499, + x_out_next_pc__h12405, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_FENCE_I && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_FENCE_I && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) @@ -7344,8 +7582,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_SFENCE_VMA", - csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_finish_SFENCE_VMA", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_SFENCE_VMA && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) @@ -7357,7 +7594,7 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_FENCE && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_finish_FENCE", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_finish_FENCE && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) @@ -7369,9 +7606,9 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_WFI_resume && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_WFI_resume", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h3142 != 4'd0) + if (WILL_FIRE_RL_rl_WFI_resume && cur_verbosity__h2930 != 4'd0) $display(" WFI resume"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_WFI_resume && @@ -7380,29 +7617,29 @@ module mkCPU(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_from_WFI && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_reset_from_Debug_Module) + $display("%0d: %m.rl_reset_from_Debug_Module", + csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_trap_fetch && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) $display(" CPU_Stage1.enq: 0x%08h", rg_next_pc); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_from_Debug_Module) - $display("%0d: CPU.rl_reset_from_Debug_Module", - csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_stage1_interrupt && NOT_IF_csr_regfile_read_csr_minstret__5_ULT_cf_ETC___d41) - $display("%0d: CPU.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); + $display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3142 == 4'd1) + if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2930 == 4'd1) $display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d", csr_regfile$read_csr_minstret, imem_rg_pc, - x_out_data_to_stage2_instr__h12529, + x_out_data_to_stage2_instr__h12435, rg_cur_priv); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h3142 != 4'd0) - $display("%0d: CPU.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", + if (WILL_FIRE_RL_rl_stage1_interrupt && cur_verbosity__h2930 != 4'd0) + $display("%0d: %m.rl_stage1_interrupt: epc 0x%0h next PC 0x%0h new_priv %0d new mstatus 0x%0h", csr_regfile$read_csr_mcycle, imem_rg_pc, csr_regfile$csr_trap_actions[97:66], @@ -7423,8 +7660,8 @@ module mkCPU(CLK, if (WILL_FIRE_RL_rl_reset_start) $display("================================================================"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h3142 != 4'd0) - $display("%0d: CPU.rl_reset_start", csr_regfile$read_csr_mcycle); + if (WILL_FIRE_RL_rl_reset_start && cur_verbosity__h2930 != 4'd0) + $display("%0d: %m.rl_reset_start", csr_regfile$read_csr_mcycle); end // synopsys translate_on endmodule // mkCPU diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkCSR_MIE.v b/src_SSITH_P1/xilinx_ip/hdl/mkCSR_MIE.v index df80ca60..222c5875 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkCSR_MIE.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkCSR_MIE.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:36 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkCSR_MIP.v b/src_SSITH_P1/xilinx_ip/hdl/mkCSR_MIP.v index fb4847d7..2b0149b4 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkCSR_MIP.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkCSR_MIP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:36 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkCSR_RegFile.v b/src_SSITH_P1/xilinx_ip/hdl/mkCSR_RegFile.v index a5b1888f..832615d7 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkCSR_RegFile.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkCSR_RegFile.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:38 BST 2019 // // // Ports: @@ -589,7 +589,6 @@ module mkCSR_RegFile(CLK, MUX_rg_mepc$write_1__SEL_1, MUX_rg_mtval$write_1__SEL_1, MUX_rg_mtvec$write_1__SEL_1, - MUX_rg_state$write_1__SEL_2, MUX_rg_tdata1$write_1__SEL_1, MUX_rw_minstret$wset_1__SEL_1; @@ -598,43 +597,43 @@ module mkCSR_RegFile(CLK, IF_mav_read_csr_csr_addr_EQ_0xC00_67_THEN_rg_m_ETC___d641, IF_read_csr_csr_addr_EQ_0xC00_1_THEN_rg_mcycle_ETC___d247, IF_read_csr_port2_csr_addr_EQ_0xC00_70_THEN_rg_ETC___d444; - wire [63 : 0] x__h5648, x__h5756; + wire [63 : 0] x__h5468, x__h5576; wire [33 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1162; wire [31 : 0] IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1144, - _theResult___fst__h9063, - _theResult___fst__h9264, + _theResult___fst__h8883, + _theResult___fst__h9084, csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137, - exc_pc___1__h8148, - exc_pc__h7884, - exc_pc__h8095, - mask__h9084, - mask__h9101, - new_dcsr__h5935, - result__h5831, - v__h4998, - v__h5060, - v__h5216, - val__h9102, - vector_offset__h8096, - wordxl1__h4515, - x__h6695, - x__h8919, - x__h8920, - x__h9083, - x__h9096, - x__h9113, - y__h9097, - y__h9114; - wire [22 : 0] fixed_up_val_23__h4556, - fixed_up_val_23__h7323, - fixed_up_val_23__h8982; - wire [5 : 0] ie_from_x__h9047, pie_from_x__h9048; + exc_pc___1__h7968, + exc_pc__h7704, + exc_pc__h7915, + mask__h8904, + mask__h8921, + new_dcsr__h5755, + result__h5651, + v__h4818, + v__h4880, + v__h5036, + val__h8922, + vector_offset__h7916, + wordxl1__h4335, + x__h6515, + x__h8739, + x__h8740, + x__h8903, + x__h8916, + x__h8933, + y__h8917, + y__h8934; + wire [22 : 0] fixed_up_val_23__h4376, + fixed_up_val_23__h7143, + fixed_up_val_23__h8802; + wire [5 : 0] ie_from_x__h8867, pie_from_x__h8868; wire [3 : 0] IF_NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_N_ETC___d1480, IF_NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_N_ETC___d1482, IF_NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_N_ETC___d1484, IF_NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_N_ETC___d1486, - exc_code__h8761; - wire [1 : 0] mpp__h8189, to_y__h9263; + exc_code__h8581; + wire [1 : 0] mpp__h8009, to_y__h9083; wire NOT_access_permitted_1_csr_addr_ULT_0xC03_163__ETC___d1257, NOT_access_permitted_2_csr_addr_ULT_0xC03_262__ETC___d1355, NOT_cfg_verbosity_read__21_ULE_1_22___d823, @@ -647,7 +646,7 @@ module mkCSR_RegFile(CLK, NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_NOT__ETC___d1474, NOT_csr_trap_actions_nmi_91_AND_csr_trap_actio_ETC___d1068, NOT_mav_csr_write_csr_addr_ULT_0xB03_44_25_AND_ETC___d836, - b__h9100, + b__h8920, csr_mip_fv_read__09_BIT_11_387_AND_csr_mie_fv__ETC___d1398, csr_mip_fv_read__09_BIT_11_387_AND_csr_mie_fv__ETC___d1403, csr_mip_fv_read__09_BIT_11_387_AND_csr_mie_fv__ETC___d1408, @@ -866,7 +865,7 @@ module mkCSR_RegFile(CLK, assign read_satp = 32'hAAAAAAAA ; // actionvalue method csr_trap_actions - assign csr_trap_actions = { x__h6695, x__h8919, x__h8920, 2'b11 } ; + assign csr_trap_actions = { x__h6515, x__h8739, x__h8740, 2'b11 } ; assign RDY_csr_trap_actions = 1'd1 ; assign CAN_FIRE_csr_trap_actions = 1'd1 ; assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ; @@ -1027,36 +1026,16 @@ module mkCSR_RegFile(CLK, .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_flash_mem_addr_base(), - .m_flash_mem_addr_size(), - .m_flash_mem_addr_lim(), - .m_ethernet_0_addr_base(), - .m_ethernet_0_addr_size(), - .m_ethernet_0_addr_lim(), - .m_dma_0_addr_base(), - .m_dma_0_addr_size(), - .m_dma_0_addr_lim(), - .m_uart16550_0_addr_base(), - .m_uart16550_0_addr_size(), - .m_uart16550_0_addr_lim(), - .m_gpio_0_addr_base(), - .m_gpio_0_addr_size(), - .m_gpio_0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_ddr4_0_uncached_addr_base(), - .m_ddr4_0_uncached_addr_size(), - .m_ddr4_0_uncached_addr_lim(), - .m_ddr4_0_cached_addr_base(), - .m_ddr4_0_cached_addr_size(), - .m_ddr4_0_cached_addr_lim(), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), @@ -1066,7 +1045,8 @@ module mkCSR_RegFile(CLK, // rule RL_rl_reset_start assign CAN_FIRE_RL_rl_reset_start = !rg_state ; - assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ; + assign WILL_FIRE_RL_rl_reset_start = + CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; // rule RL_rl_mcycle_incr assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ; @@ -1117,8 +1097,6 @@ module mkCSR_RegFile(CLK, EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_44_OR_NOT_mav_ETC___d657 && mav_csr_write_csr_addr == 12'h305 ; - assign MUX_rg_state$write_1__SEL_2 = - CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ; assign MUX_rg_tdata1$write_1__SEL_1 = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_44_OR_NOT_mav_ETC___d657 && @@ -1129,7 +1107,7 @@ module mkCSR_RegFile(CLK, (mav_csr_write_csr_addr == 12'hB02 || mav_csr_write_csr_addr == 12'hB82) ; assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 = - { 9'd0, fixed_up_val_23__h8982 } ; + { 9'd0, fixed_up_val_23__h8802 } ; assign MUX_rg_dcsr$write_1__VAL_3 = { rg_dcsr[31:9], write_dcsr_cause_priv_cause, @@ -1139,7 +1117,7 @@ module mkCSR_RegFile(CLK, { mav_csr_write_word[31], mav_csr_write_word[3:0] } ; assign MUX_rg_mcause$write_1__VAL_3 = { !csr_trap_actions_nmi && csr_trap_actions_interrupt, - exc_code__h8761 } ; + exc_code__h8581 } ; assign MUX_rg_minstret$write_1__VAL_1 = MUX_rw_minstret$wset_1__SEL_1 ? MUX_rw_minstret$wset_1__VAL_1 : @@ -1151,7 +1129,7 @@ module mkCSR_RegFile(CLK, { soc_map$m_mtvec_reset_value[31:2], soc_map$m_mtvec_reset_value[0] } ; assign MUX_rw_minstret$wset_1__VAL_1 = - (mav_csr_write_csr_addr == 12'hB02) ? x__h5648 : x__h5756 ; + (mav_csr_write_csr_addr == 12'hB02) ? x__h5468 : x__h5576 ; // register cfg_verbosity assign cfg_verbosity$D_IN = 4'h0 ; @@ -1160,18 +1138,18 @@ module mkCSR_RegFile(CLK, // register csr_mstatus_rg_mstatus always@(WILL_FIRE_RL_rl_reset_start or MUX_csr_mstatus_rg_mstatus$write_1__SEL_2 or - wordxl1__h4515 or + wordxl1__h4335 or EN_csr_ret_actions or MUX_csr_mstatus_rg_mstatus$write_1__VAL_3 or - EN_csr_trap_actions or x__h8919) + EN_csr_trap_actions or x__h8739) case (1'b1) WILL_FIRE_RL_rl_reset_start: csr_mstatus_rg_mstatus$D_IN = 32'd0; MUX_csr_mstatus_rg_mstatus$write_1__SEL_2: - csr_mstatus_rg_mstatus$D_IN = wordxl1__h4515; + csr_mstatus_rg_mstatus$D_IN = wordxl1__h4335; EN_csr_ret_actions: csr_mstatus_rg_mstatus$D_IN = MUX_csr_mstatus_rg_mstatus$write_1__VAL_3; - EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = x__h8919; + EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = x__h8739; default: csr_mstatus_rg_mstatus$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -1186,11 +1164,11 @@ module mkCSR_RegFile(CLK, // register rg_dcsr always@(WILL_FIRE_RL_rl_reset_start or MUX_rg_dcsr$write_1__SEL_2 or - new_dcsr__h5935 or + new_dcsr__h5755 or EN_write_dcsr_cause_priv or MUX_rg_dcsr$write_1__VAL_3) case (1'b1) WILL_FIRE_RL_rl_reset_start: rg_dcsr$D_IN = 32'd1073741843; - MUX_rg_dcsr$write_1__SEL_2: rg_dcsr$D_IN = new_dcsr__h5935; + MUX_rg_dcsr$write_1__SEL_2: rg_dcsr$D_IN = new_dcsr__h5755; EN_write_dcsr_cause_priv: rg_dcsr$D_IN = MUX_rg_dcsr$write_1__VAL_3; default: rg_dcsr$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -1322,7 +1300,7 @@ module mkCSR_RegFile(CLK, // register rg_nmi_vector assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value[31:0] ; - assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ; + assign rg_nmi_vector$EN = WILL_FIRE_RL_rl_reset_start ; // register rg_state assign rg_state$D_IN = !EN_server_reset_request_put ; @@ -1331,7 +1309,7 @@ module mkCSR_RegFile(CLK, // register rg_tdata1 assign rg_tdata1$D_IN = - MUX_rg_tdata1$write_1__SEL_1 ? result__h5831 : 32'd0 ; + MUX_rg_tdata1$write_1__SEL_1 ? result__h5651 : 32'd0 ; assign rg_tdata1$EN = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_44_OR_NOT_mav_ETC___d657 && @@ -1363,7 +1341,7 @@ module mkCSR_RegFile(CLK, // submodule csr_mie assign csr_mie$fav_write_misa = 28'd68161797 ; assign csr_mie$fav_write_wordxl = mav_csr_write_word ; - assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ; + assign csr_mie$EN_reset = WILL_FIRE_RL_rl_reset_start ; assign csr_mie$EN_fav_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_44_OR_NOT_mav_ETC___d657 && @@ -1379,7 +1357,7 @@ module mkCSR_RegFile(CLK, assign csr_mip$software_interrupt_req_req = software_interrupt_req_set_not_clear ; assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ; - assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ; + assign csr_mip$EN_reset = WILL_FIRE_RL_rl_reset_start ; assign csr_mip$EN_fav_write = EN_mav_csr_write && mav_csr_write_csr_addr_ULT_0xB03_44_OR_NOT_mav_ETC___d657 && @@ -1422,13 +1400,13 @@ module mkCSR_RegFile(CLK, IF_NOT_csr_mip_fv_read__09_BIT_11_387_434_OR_N_ETC___d1484) ; assign IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1144 = (csr_ret_actions_from_priv == 2'b11) ? - _theResult___fst__h9063 : - _theResult___fst__h9264 ; + _theResult___fst__h8883 : + _theResult___fst__h9084 ; assign IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1162 = (csr_ret_actions_from_priv == 2'b11) ? { csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[12:11], - _theResult___fst__h9063 } : - { to_y__h9263, _theResult___fst__h9264 } ; + _theResult___fst__h8883 } : + { to_y__h9083, _theResult___fst__h9084 } ; assign NOT_access_permitted_1_csr_addr_ULT_0xC03_163__ETC___d1257 = (access_permitted_1_csr_addr >= 12'hC03 && access_permitted_1_csr_addr <= 12'hC1F || @@ -1559,18 +1537,18 @@ module mkCSR_RegFile(CLK, !csr_mstatus_rg_mstatus[3]) ; assign NOT_csr_trap_actions_nmi_91_AND_csr_trap_actio_ETC___d1068 = !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 != 4'd0 && - exc_code__h8761 != 4'd1 && - exc_code__h8761 != 4'd2 && - exc_code__h8761 != 4'd3 && - exc_code__h8761 != 4'd4 && - exc_code__h8761 != 4'd5 && - exc_code__h8761 != 4'd6 && - exc_code__h8761 != 4'd7 && - exc_code__h8761 != 4'd8 && - exc_code__h8761 != 4'd9 && - exc_code__h8761 != 4'd10 && - exc_code__h8761 != 4'd11 ; + exc_code__h8581 != 4'd0 && + exc_code__h8581 != 4'd1 && + exc_code__h8581 != 4'd2 && + exc_code__h8581 != 4'd3 && + exc_code__h8581 != 4'd4 && + exc_code__h8581 != 4'd5 && + exc_code__h8581 != 4'd6 && + exc_code__h8581 != 4'd7 && + exc_code__h8581 != 4'd8 && + exc_code__h8581 != 4'd9 && + exc_code__h8581 != 4'd10 && + exc_code__h8581 != 4'd11 ; assign NOT_mav_csr_write_csr_addr_ULT_0xB03_44_25_AND_ETC___d836 = !mav_csr_write_csr_addr_ULT_0xB03___d644 && mav_csr_write_csr_addr_ULE_0xB1F___d645 || @@ -1582,15 +1560,15 @@ module mkCSR_RegFile(CLK, mav_csr_write_csr_addr == 12'hF12 || mav_csr_write_csr_addr == 12'hF13 || mav_csr_write_csr_addr == 12'hF14 ; - assign _theResult___fst__h9063 = + assign _theResult___fst__h8883 = { csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[31:13], 2'd0, csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[10:0] } ; - assign _theResult___fst__h9264 = + assign _theResult___fst__h9084 = { csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[31:9], 1'd0, csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[7:0] } ; - assign b__h9100 = + assign b__h8920 = csr_mstatus_rg_mstatus[{ 3'd1, csr_ret_actions_from_priv }] ; assign csr_mip_fv_read__09_BIT_11_387_AND_csr_mie_fv__ETC___d1398 = csr_mip$fv_read[11] && csr_mie$fv_read[11] && @@ -1635,30 +1613,30 @@ module mkCSR_RegFile(CLK, (interrupt_pending_cur_priv != 2'b11 || csr_mstatus_rg_mstatus[3]) ; assign csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137 = - x__h9096 | mask__h9084 ; + x__h8916 | mask__h8904 ; assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1119 = (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 != 4'd0 && - exc_code__h8761 != 4'd1 && - exc_code__h8761 != 4'd2 && - exc_code__h8761 != 4'd3 && - exc_code__h8761 != 4'd4 && - exc_code__h8761 != 4'd5 && - exc_code__h8761 != 4'd6 && - exc_code__h8761 != 4'd7 && - exc_code__h8761 != 4'd8 && - exc_code__h8761 != 4'd9 && - exc_code__h8761 != 4'd11 && - exc_code__h8761 != 4'd12 && - exc_code__h8761 != 4'd13 && - exc_code__h8761 != 4'd15 ; - assign exc_code__h8761 = + exc_code__h8581 != 4'd0 && + exc_code__h8581 != 4'd1 && + exc_code__h8581 != 4'd2 && + exc_code__h8581 != 4'd3 && + exc_code__h8581 != 4'd4 && + exc_code__h8581 != 4'd5 && + exc_code__h8581 != 4'd6 && + exc_code__h8581 != 4'd7 && + exc_code__h8581 != 4'd8 && + exc_code__h8581 != 4'd9 && + exc_code__h8581 != 4'd11 && + exc_code__h8581 != 4'd12 && + exc_code__h8581 != 4'd13 && + exc_code__h8581 != 4'd15 ; + assign exc_code__h8581 = csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ; - assign exc_pc___1__h8148 = exc_pc__h8095 + vector_offset__h8096 ; - assign exc_pc__h7884 = { rg_mtvec[30:1], 2'd0 } ; - assign exc_pc__h8095 = - csr_trap_actions_nmi ? rg_nmi_vector : exc_pc__h7884 ; - assign fixed_up_val_23__h4556 = + assign exc_pc___1__h7968 = exc_pc__h7915 + vector_offset__h7916 ; + assign exc_pc__h7704 = { rg_mtvec[30:1], 2'd0 } ; + assign exc_pc__h7915 = + csr_trap_actions_nmi ? rg_nmi_vector : exc_pc__h7704 ; + assign fixed_up_val_23__h4376 = { mav_csr_write_word[22:17], 4'd0, (mav_csr_write_word[12:11] == 2'b11) ? @@ -1670,10 +1648,10 @@ module mkCSR_RegFile(CLK, 2'd0, mav_csr_write_word[3:2], 2'd0 } ; - assign fixed_up_val_23__h7323 = + assign fixed_up_val_23__h7143 = { csr_mstatus_rg_mstatus[22:17], 4'd0, - mpp__h8189, + mpp__h8009, csr_mstatus_rg_mstatus[10:9], 1'd0, csr_mstatus_rg_mstatus[3], @@ -1681,7 +1659,7 @@ module mkCSR_RegFile(CLK, 3'd0, csr_mstatus_rg_mstatus[2], 2'd0 } ; - assign fixed_up_val_23__h8982 = + assign fixed_up_val_23__h8802 = { IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1144[22:17], 4'd0, (IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1144[12:11] == @@ -1694,9 +1672,9 @@ module mkCSR_RegFile(CLK, 2'd0, IF_csr_ret_actions_from_priv_EQ_0b11_123_THEN__ETC___d1144[3:2], 2'd0 } ; - assign ie_from_x__h9047 = { 4'd0, csr_ret_actions_from_priv } ; - assign mask__h9084 = 32'd1 << pie_from_x__h9048 ; - assign mask__h9101 = 32'd1 << ie_from_x__h9047 ; + assign ie_from_x__h8867 = { 4'd0, csr_ret_actions_from_priv } ; + assign mask__h8904 = 32'd1 << pie_from_x__h8868 ; + assign mask__h8921 = 32'd1 << ie_from_x__h8867 ; assign mav_csr_write_csr_addr_ULE_0x33F___d653 = mav_csr_write_csr_addr <= 12'h33F ; assign mav_csr_write_csr_addr_ULE_0xB1F___d645 = @@ -1762,47 +1740,47 @@ module mkCSR_RegFile(CLK, mav_csr_write_csr_addr < 12'hB03 ; assign mav_csr_write_csr_addr_ULT_0xB83___d648 = mav_csr_write_csr_addr < 12'hB83 ; - assign mpp__h8189 = + assign mpp__h8009 = (csr_trap_actions_from_priv == 2'b11) ? csr_trap_actions_from_priv : 2'b0 ; - assign new_dcsr__h5935 = + assign new_dcsr__h5755 = { rg_dcsr[31:16], mav_csr_write_word[15:9], rg_dcsr[8:5], mav_csr_write_word[4], rg_dcsr[3], mav_csr_write_word[2:0] } ; - assign pie_from_x__h9048 = { 4'd1, csr_ret_actions_from_priv } ; - assign result__h5831 = { 4'd0, mav_csr_write_word[27:0] } ; - assign to_y__h9263 = + assign pie_from_x__h8868 = { 4'd1, csr_ret_actions_from_priv } ; + assign result__h5651 = { 4'd0, mav_csr_write_word[27:0] } ; + assign to_y__h9083 = { 1'b0, csr_mstatus_rg_mstatus_94_AND_INV_1_SL_0_CONCA_ETC___d1137[8] } ; - assign v__h4998 = + assign v__h4818 = { mav_csr_write_word[31:2], 1'b0, mav_csr_write_word[0] } ; - assign v__h5060 = { 29'd0, mav_csr_write_word[2:0] } ; - assign v__h5216 = + assign v__h4880 = { 29'd0, mav_csr_write_word[2:0] } ; + assign v__h5036 = { mav_csr_write_word[31], 27'd0, mav_csr_write_word[3:0] } ; - assign val__h9102 = { 31'd0, b__h9100 } << ie_from_x__h9047 ; - assign vector_offset__h8096 = { 26'd0, csr_trap_actions_exc_code, 2'd0 } ; - assign wordxl1__h4515 = { 9'd0, fixed_up_val_23__h4556 } ; - assign x__h5648 = { rg_minstret[63:32], mav_csr_write_word } ; - assign x__h5756 = { mav_csr_write_word, rg_minstret[31:0] } ; - assign x__h6695 = + assign val__h8922 = { 31'd0, b__h8920 } << ie_from_x__h8867 ; + assign vector_offset__h7916 = { 26'd0, csr_trap_actions_exc_code, 2'd0 } ; + assign wordxl1__h4335 = { 9'd0, fixed_up_val_23__h4376 } ; + assign x__h5468 = { rg_minstret[63:32], mav_csr_write_word } ; + assign x__h5576 = { mav_csr_write_word, rg_minstret[31:0] } ; + assign x__h6515 = (csr_trap_actions_interrupt && !csr_trap_actions_nmi && rg_mtvec[0]) ? - exc_pc___1__h8148 : - exc_pc__h8095 ; - assign x__h8919 = { 9'd0, fixed_up_val_23__h7323 } ; - assign x__h8920 = + exc_pc___1__h7968 : + exc_pc__h7915 ; + assign x__h8739 = { 9'd0, fixed_up_val_23__h7143 } ; + assign x__h8740 = { !csr_trap_actions_nmi && csr_trap_actions_interrupt, 27'd0, - exc_code__h8761 } ; - assign x__h9083 = x__h9113 | val__h9102 ; - assign x__h9096 = x__h9083 & y__h9097 ; - assign x__h9113 = csr_mstatus_rg_mstatus & y__h9114 ; - assign y__h9097 = ~mask__h9084 ; - assign y__h9114 = ~mask__h9101 ; + exc_code__h8581 } ; + assign x__h8903 = x__h8933 | val__h8922 ; + assign x__h8916 = x__h8903 & y__h8917 ; + assign x__h8933 = csr_mstatus_rg_mstatus & y__h8934 ; + assign y__h8917 = ~mask__h8904 ; + assign y__h8934 = ~mask__h8921 ; always@(read_csr_csr_addr or rg_dscratch1 or csr_mstatus_rg_mstatus or @@ -2062,17 +2040,17 @@ module mkCSR_RegFile(CLK, endcase end always@(mav_csr_write_csr_addr or - wordxl1__h4515 or + wordxl1__h4335 or csr_mie$fav_write or - v__h4998 or - v__h5060 or + v__h4818 or + v__h4880 or mav_csr_write_word or - v__h5216 or csr_mip$fav_write or result__h5831 or new_dcsr__h5935) + v__h5036 or csr_mip$fav_write or result__h5651 or new_dcsr__h5755) begin case (mav_csr_write_csr_addr) 12'h300: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - wordxl1__h4515; + wordxl1__h4335; 12'h301, 12'h7A0: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = 32'd0; 12'h304: @@ -2080,10 +2058,10 @@ module mkCSR_RegFile(CLK, csr_mie$fav_write; 12'h305: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - v__h4998; + v__h4818; 12'h306: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - v__h5060; + v__h4880; 12'h340, 12'h341, 12'h343, @@ -2100,16 +2078,16 @@ module mkCSR_RegFile(CLK, mav_csr_write_word; 12'h342: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - v__h5216; + v__h5036; 12'h344: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = csr_mip$fav_write; 12'h7A1: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - result__h5831; + result__h5651; 12'h7B0: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = - new_dcsr__h5935; + new_dcsr__h5755; default: IF_mav_csr_write_csr_addr_EQ_0x300_58_THEN_0_C_ETC___d863 = 32'd0; endcase @@ -2420,7 +2398,7 @@ module mkCSR_RegFile(CLK, $display(""); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823) - $write(" Return: new pc 0x%0h ", x__h6695); + $write(" Return: new pc 0x%0h ", x__h6515); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823) $write(" new mstatus:"); @@ -2456,7 +2434,7 @@ module mkCSR_RegFile(CLK, $write(" fs:%0d", 2'd0); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823) - $write(" mpp:%0d", mpp__h8189); + $write(" mpp:%0d", mpp__h8009); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823) $write(" spp:%0d", 1'd0); @@ -2476,152 +2454,152 @@ module mkCSR_RegFile(CLK, if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd0) + exc_code__h8581 == 4'd0) $write("USER_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd1) + exc_code__h8581 == 4'd1) $write("SUPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd2) + exc_code__h8581 == 4'd2) $write("HYPERVISOR_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd3) + exc_code__h8581 == 4'd3) $write("MACHINE_SW_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd4) + exc_code__h8581 == 4'd4) $write("USER_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd5) + exc_code__h8581 == 4'd5) $write("SUPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd6) + exc_code__h8581 == 4'd6) $write("HYPERVISOR_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd7) + exc_code__h8581 == 4'd7) $write("MACHINE_TIMER_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd8) + exc_code__h8581 == 4'd8) $write("USER_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd9) + exc_code__h8581 == 4'd9) $write("SUPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd10) + exc_code__h8581 == 4'd10) $write("HYPERVISOR_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && !csr_trap_actions_nmi && csr_trap_actions_interrupt && - exc_code__h8761 == 4'd11) + exc_code__h8581 == 4'd11) $write("MACHINE_EXTERNAL_INTERRUPT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && NOT_csr_trap_actions_nmi_91_AND_csr_trap_actio_ETC___d1068) - $write("unknown interrupt Exc_Code %d", exc_code__h8761); + $write("unknown interrupt Exc_Code %d", exc_code__h8581); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd0) + exc_code__h8581 == 4'd0) $write("INSTRUCTION_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd1) + exc_code__h8581 == 4'd1) $write("INSTRUCTION_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd2) + exc_code__h8581 == 4'd2) $write("ILLEGAL_INSTRUCTION"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd3) + exc_code__h8581 == 4'd3) $write("BREAKPOINT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd4) + exc_code__h8581 == 4'd4) $write("LOAD_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd5) + exc_code__h8581 == 4'd5) $write("LOAD_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd6) + exc_code__h8581 == 4'd6) $write("STORE_AMO_ADDR_MISALIGNED"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd7) + exc_code__h8581 == 4'd7) $write("STORE_AMO_ACCESS_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd8) + exc_code__h8581 == 4'd8) $write("ECALL_FROM_U"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd9) + exc_code__h8581 == 4'd9) $write("ECALL_FROM_S"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd11) + exc_code__h8581 == 4'd11) $write("ECALL_FROM_M"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd12) + exc_code__h8581 == 4'd12) $write("INSTRUCTION_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd13) + exc_code__h8581 == 4'd13) $write("LOAD_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && (csr_trap_actions_nmi || !csr_trap_actions_interrupt) && - exc_code__h8761 == 4'd15) + exc_code__h8581 == 4'd15) $write("STORE_AMO_PAGE_FAULT"); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823 && csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1119) - $write("unknown trap Exc_Code %d", exc_code__h8761); + $write("unknown trap Exc_Code %d", exc_code__h8581); if (RST_N != `BSV_RESET_VALUE) if (EN_csr_trap_actions && NOT_cfg_verbosity_read__21_ULE_1_22___d823) $write(" new priv %0d", 2'b11); diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkCore.v b/src_SSITH_P1/xilinx_ip/hdl/mkCore.v index 5373dd59..a7347f18 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:57 BST 2019 // // // Ports: @@ -10,36 +10,35 @@ // RDY_cpu_reset_server_request_put O 1 reg // cpu_reset_server_response_get O 1 reg // RDY_cpu_reset_server_response_get O 1 reg +// cpu_imem_master_awid O 5 +// cpu_imem_master_awaddr O 64 +// cpu_imem_master_awlen O 8 +// cpu_imem_master_awsize O 3 +// cpu_imem_master_awburst O 2 +// cpu_imem_master_awlock O 1 +// cpu_imem_master_awcache O 4 +// cpu_imem_master_awprot O 3 +// cpu_imem_master_awqos O 4 +// cpu_imem_master_awregion O 4 // cpu_imem_master_awvalid O 1 -// cpu_imem_master_awid O 4 reg -// cpu_imem_master_awaddr O 64 reg -// cpu_imem_master_awlen O 8 reg -// cpu_imem_master_awsize O 3 reg -// cpu_imem_master_awburst O 2 reg -// cpu_imem_master_awlock O 1 reg -// cpu_imem_master_awcache O 4 reg -// cpu_imem_master_awprot O 3 reg -// cpu_imem_master_awqos O 4 reg -// cpu_imem_master_awregion O 4 reg +// cpu_imem_master_wdata O 64 +// cpu_imem_master_wstrb O 8 +// cpu_imem_master_wlast O 1 // cpu_imem_master_wvalid O 1 -// cpu_imem_master_wdata O 64 reg -// cpu_imem_master_wstrb O 8 reg -// cpu_imem_master_wlast O 1 reg // cpu_imem_master_bready O 1 +// cpu_imem_master_arid O 5 +// cpu_imem_master_araddr O 64 +// cpu_imem_master_arlen O 8 +// cpu_imem_master_arsize O 3 +// cpu_imem_master_arburst O 2 +// cpu_imem_master_arlock O 1 +// cpu_imem_master_arcache O 4 +// cpu_imem_master_arprot O 3 +// cpu_imem_master_arqos O 4 +// cpu_imem_master_arregion O 4 // cpu_imem_master_arvalid O 1 -// cpu_imem_master_arid O 4 reg -// cpu_imem_master_araddr O 64 reg -// cpu_imem_master_arlen O 8 reg -// cpu_imem_master_arsize O 3 reg -// cpu_imem_master_arburst O 2 reg -// cpu_imem_master_arlock O 1 reg -// cpu_imem_master_arcache O 4 reg -// cpu_imem_master_arprot O 3 reg -// cpu_imem_master_arqos O 4 reg -// cpu_imem_master_arregion O 4 reg // cpu_imem_master_rready O 1 -// cpu_dmem_master_awvalid O 1 reg -// cpu_dmem_master_awid O 4 reg +// cpu_dmem_master_awid O 5 reg // cpu_dmem_master_awaddr O 64 reg // cpu_dmem_master_awlen O 8 reg // cpu_dmem_master_awsize O 3 reg @@ -49,13 +48,13 @@ // cpu_dmem_master_awprot O 3 reg // cpu_dmem_master_awqos O 4 reg // cpu_dmem_master_awregion O 4 reg -// cpu_dmem_master_wvalid O 1 reg +// cpu_dmem_master_awvalid O 1 reg // cpu_dmem_master_wdata O 64 reg // cpu_dmem_master_wstrb O 8 reg // cpu_dmem_master_wlast O 1 reg +// cpu_dmem_master_wvalid O 1 reg // cpu_dmem_master_bready O 1 reg -// cpu_dmem_master_arvalid O 1 reg -// cpu_dmem_master_arid O 4 reg +// cpu_dmem_master_arid O 5 reg // cpu_dmem_master_araddr O 64 reg // cpu_dmem_master_arlen O 8 reg // cpu_dmem_master_arsize O 3 reg @@ -65,6 +64,7 @@ // cpu_dmem_master_arprot O 3 reg // cpu_dmem_master_arqos O 4 reg // cpu_dmem_master_arregion O 4 reg +// cpu_dmem_master_arvalid O 1 reg // cpu_dmem_master_rready O 1 reg // tv_verifier_info_get_get O 608 reg // RDY_tv_verifier_info_get_get O 1 reg @@ -82,23 +82,19 @@ // cpu_reset_server_request_put I 1 reg // cpu_imem_master_awready I 1 // cpu_imem_master_wready I 1 -// cpu_imem_master_bvalid I 1 -// cpu_imem_master_bid I 4 reg -// cpu_imem_master_bresp I 2 reg +// cpu_imem_master_bid I 5 +// cpu_imem_master_bresp I 2 // cpu_imem_master_arready I 1 -// cpu_imem_master_rvalid I 1 -// cpu_imem_master_rid I 4 reg -// cpu_imem_master_rdata I 64 reg -// cpu_imem_master_rresp I 2 reg -// cpu_imem_master_rlast I 1 reg +// cpu_imem_master_rid I 5 +// cpu_imem_master_rdata I 64 +// cpu_imem_master_rresp I 2 +// cpu_imem_master_rlast I 1 // cpu_dmem_master_awready I 1 // cpu_dmem_master_wready I 1 -// cpu_dmem_master_bvalid I 1 -// cpu_dmem_master_bid I 4 reg +// cpu_dmem_master_bid I 5 reg // cpu_dmem_master_bresp I 2 reg // cpu_dmem_master_arready I 1 -// cpu_dmem_master_rvalid I 1 -// cpu_dmem_master_rid I 4 reg +// cpu_dmem_master_rid I 5 reg // cpu_dmem_master_rdata I 64 reg // cpu_dmem_master_rresp I 2 reg // cpu_dmem_master_rlast I 1 reg @@ -125,6 +121,10 @@ // ndm_reset_client_response_put I 1 reg // EN_set_verbosity I 1 // EN_cpu_reset_server_request_put I 1 +// cpu_imem_master_bvalid I 1 +// cpu_imem_master_rvalid I 1 +// cpu_dmem_master_bvalid I 1 +// cpu_dmem_master_rvalid I 1 // EN_dm_dmi_read_addr I 1 // EN_dm_dmi_write I 1 // EN_ndm_reset_client_response_put I 1 @@ -134,8 +134,66 @@ // EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready -// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_rready +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arid +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_araddr +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arlen +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arsize +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arburst +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arlock +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arcache +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arprot +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arqos +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arregion +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_aruser +// (cpu_imem_master_rid, +// cpu_imem_master_rdata, +// cpu_imem_master_rresp, +// cpu_imem_master_rlast, +// cpu_imem_master_rvalid) -> cpu_imem_master_arvalid // (dm_dmi_read_addr_dm_addr, EN_dm_dmi_read_addr) -> RDY_dm_dmi_read_data // (dm_dmi_read_addr_dm_addr, // EN_dm_dmi_read_addr, @@ -172,8 +230,6 @@ module mkCore(CLK, cpu_reset_server_response_get, RDY_cpu_reset_server_response_get, - cpu_imem_master_awvalid, - cpu_imem_master_awid, cpu_imem_master_awaddr, @@ -194,9 +250,9 @@ module mkCore(CLK, cpu_imem_master_awregion, - cpu_imem_master_awready, + cpu_imem_master_awvalid, - cpu_imem_master_wvalid, + cpu_imem_master_awready, cpu_imem_master_wdata, @@ -204,16 +260,16 @@ module mkCore(CLK, cpu_imem_master_wlast, + cpu_imem_master_wvalid, + cpu_imem_master_wready, - cpu_imem_master_bvalid, cpu_imem_master_bid, cpu_imem_master_bresp, + cpu_imem_master_bvalid, cpu_imem_master_bready, - cpu_imem_master_arvalid, - cpu_imem_master_arid, cpu_imem_master_araddr, @@ -234,18 +290,18 @@ module mkCore(CLK, cpu_imem_master_arregion, + cpu_imem_master_arvalid, + cpu_imem_master_arready, - cpu_imem_master_rvalid, cpu_imem_master_rid, cpu_imem_master_rdata, cpu_imem_master_rresp, cpu_imem_master_rlast, + cpu_imem_master_rvalid, cpu_imem_master_rready, - cpu_dmem_master_awvalid, - cpu_dmem_master_awid, cpu_dmem_master_awaddr, @@ -266,9 +322,9 @@ module mkCore(CLK, cpu_dmem_master_awregion, - cpu_dmem_master_awready, + cpu_dmem_master_awvalid, - cpu_dmem_master_wvalid, + cpu_dmem_master_awready, cpu_dmem_master_wdata, @@ -276,16 +332,16 @@ module mkCore(CLK, cpu_dmem_master_wlast, + cpu_dmem_master_wvalid, + cpu_dmem_master_wready, - cpu_dmem_master_bvalid, cpu_dmem_master_bid, cpu_dmem_master_bresp, + cpu_dmem_master_bvalid, cpu_dmem_master_bready, - cpu_dmem_master_arvalid, - cpu_dmem_master_arid, cpu_dmem_master_araddr, @@ -306,13 +362,15 @@ module mkCore(CLK, cpu_dmem_master_arregion, + cpu_dmem_master_arvalid, + cpu_dmem_master_arready, - cpu_dmem_master_rvalid, cpu_dmem_master_rid, cpu_dmem_master_rdata, cpu_dmem_master_rresp, cpu_dmem_master_rlast, + cpu_dmem_master_rvalid, cpu_dmem_master_rready, @@ -393,226 +451,226 @@ module mkCore(CLK, output cpu_reset_server_response_get; output RDY_cpu_reset_server_response_get; - // value method cpu_imem_master_m_awvalid - output cpu_imem_master_awvalid; - - // value method cpu_imem_master_m_awid - output [3 : 0] cpu_imem_master_awid; + // value method cpu_imem_master_aw_awid + output [4 : 0] cpu_imem_master_awid; - // value method cpu_imem_master_m_awaddr + // value method cpu_imem_master_aw_awaddr output [63 : 0] cpu_imem_master_awaddr; - // value method cpu_imem_master_m_awlen + // value method cpu_imem_master_aw_awlen output [7 : 0] cpu_imem_master_awlen; - // value method cpu_imem_master_m_awsize + // value method cpu_imem_master_aw_awsize output [2 : 0] cpu_imem_master_awsize; - // value method cpu_imem_master_m_awburst + // value method cpu_imem_master_aw_awburst output [1 : 0] cpu_imem_master_awburst; - // value method cpu_imem_master_m_awlock + // value method cpu_imem_master_aw_awlock output cpu_imem_master_awlock; - // value method cpu_imem_master_m_awcache + // value method cpu_imem_master_aw_awcache output [3 : 0] cpu_imem_master_awcache; - // value method cpu_imem_master_m_awprot + // value method cpu_imem_master_aw_awprot output [2 : 0] cpu_imem_master_awprot; - // value method cpu_imem_master_m_awqos + // value method cpu_imem_master_aw_awqos output [3 : 0] cpu_imem_master_awqos; - // value method cpu_imem_master_m_awregion + // value method cpu_imem_master_aw_awregion output [3 : 0] cpu_imem_master_awregion; - // value method cpu_imem_master_m_awuser + // value method cpu_imem_master_aw_awuser - // action method cpu_imem_master_m_awready - input cpu_imem_master_awready; + // value method cpu_imem_master_aw_awvalid + output cpu_imem_master_awvalid; - // value method cpu_imem_master_m_wvalid - output cpu_imem_master_wvalid; + // action method cpu_imem_master_aw_awready + input cpu_imem_master_awready; - // value method cpu_imem_master_m_wdata + // value method cpu_imem_master_w_wdata output [63 : 0] cpu_imem_master_wdata; - // value method cpu_imem_master_m_wstrb + // value method cpu_imem_master_w_wstrb output [7 : 0] cpu_imem_master_wstrb; - // value method cpu_imem_master_m_wlast + // value method cpu_imem_master_w_wlast output cpu_imem_master_wlast; - // value method cpu_imem_master_m_wuser + // value method cpu_imem_master_w_wuser + + // value method cpu_imem_master_w_wvalid + output cpu_imem_master_wvalid; - // action method cpu_imem_master_m_wready + // action method cpu_imem_master_w_wready input cpu_imem_master_wready; - // action method cpu_imem_master_m_bvalid - input cpu_imem_master_bvalid; - input [3 : 0] cpu_imem_master_bid; + // action method cpu_imem_master_b_bflit + input [4 : 0] cpu_imem_master_bid; input [1 : 0] cpu_imem_master_bresp; + input cpu_imem_master_bvalid; - // value method cpu_imem_master_m_bready + // value method cpu_imem_master_b_bready output cpu_imem_master_bready; - // value method cpu_imem_master_m_arvalid - output cpu_imem_master_arvalid; - - // value method cpu_imem_master_m_arid - output [3 : 0] cpu_imem_master_arid; + // value method cpu_imem_master_ar_arid + output [4 : 0] cpu_imem_master_arid; - // value method cpu_imem_master_m_araddr + // value method cpu_imem_master_ar_araddr output [63 : 0] cpu_imem_master_araddr; - // value method cpu_imem_master_m_arlen + // value method cpu_imem_master_ar_arlen output [7 : 0] cpu_imem_master_arlen; - // value method cpu_imem_master_m_arsize + // value method cpu_imem_master_ar_arsize output [2 : 0] cpu_imem_master_arsize; - // value method cpu_imem_master_m_arburst + // value method cpu_imem_master_ar_arburst output [1 : 0] cpu_imem_master_arburst; - // value method cpu_imem_master_m_arlock + // value method cpu_imem_master_ar_arlock output cpu_imem_master_arlock; - // value method cpu_imem_master_m_arcache + // value method cpu_imem_master_ar_arcache output [3 : 0] cpu_imem_master_arcache; - // value method cpu_imem_master_m_arprot + // value method cpu_imem_master_ar_arprot output [2 : 0] cpu_imem_master_arprot; - // value method cpu_imem_master_m_arqos + // value method cpu_imem_master_ar_arqos output [3 : 0] cpu_imem_master_arqos; - // value method cpu_imem_master_m_arregion + // value method cpu_imem_master_ar_arregion output [3 : 0] cpu_imem_master_arregion; - // value method cpu_imem_master_m_aruser + // value method cpu_imem_master_ar_aruser + + // value method cpu_imem_master_ar_arvalid + output cpu_imem_master_arvalid; - // action method cpu_imem_master_m_arready + // action method cpu_imem_master_ar_arready input cpu_imem_master_arready; - // action method cpu_imem_master_m_rvalid - input cpu_imem_master_rvalid; - input [3 : 0] cpu_imem_master_rid; + // action method cpu_imem_master_r_rflit + input [4 : 0] cpu_imem_master_rid; input [63 : 0] cpu_imem_master_rdata; input [1 : 0] cpu_imem_master_rresp; input cpu_imem_master_rlast; + input cpu_imem_master_rvalid; - // value method cpu_imem_master_m_rready + // value method cpu_imem_master_r_rready output cpu_imem_master_rready; - // value method cpu_dmem_master_m_awvalid - output cpu_dmem_master_awvalid; - - // value method cpu_dmem_master_m_awid - output [3 : 0] cpu_dmem_master_awid; + // value method cpu_dmem_master_aw_awid + output [4 : 0] cpu_dmem_master_awid; - // value method cpu_dmem_master_m_awaddr + // value method cpu_dmem_master_aw_awaddr output [63 : 0] cpu_dmem_master_awaddr; - // value method cpu_dmem_master_m_awlen + // value method cpu_dmem_master_aw_awlen output [7 : 0] cpu_dmem_master_awlen; - // value method cpu_dmem_master_m_awsize + // value method cpu_dmem_master_aw_awsize output [2 : 0] cpu_dmem_master_awsize; - // value method cpu_dmem_master_m_awburst + // value method cpu_dmem_master_aw_awburst output [1 : 0] cpu_dmem_master_awburst; - // value method cpu_dmem_master_m_awlock + // value method cpu_dmem_master_aw_awlock output cpu_dmem_master_awlock; - // value method cpu_dmem_master_m_awcache + // value method cpu_dmem_master_aw_awcache output [3 : 0] cpu_dmem_master_awcache; - // value method cpu_dmem_master_m_awprot + // value method cpu_dmem_master_aw_awprot output [2 : 0] cpu_dmem_master_awprot; - // value method cpu_dmem_master_m_awqos + // value method cpu_dmem_master_aw_awqos output [3 : 0] cpu_dmem_master_awqos; - // value method cpu_dmem_master_m_awregion + // value method cpu_dmem_master_aw_awregion output [3 : 0] cpu_dmem_master_awregion; - // value method cpu_dmem_master_m_awuser + // value method cpu_dmem_master_aw_awuser - // action method cpu_dmem_master_m_awready - input cpu_dmem_master_awready; + // value method cpu_dmem_master_aw_awvalid + output cpu_dmem_master_awvalid; - // value method cpu_dmem_master_m_wvalid - output cpu_dmem_master_wvalid; + // action method cpu_dmem_master_aw_awready + input cpu_dmem_master_awready; - // value method cpu_dmem_master_m_wdata + // value method cpu_dmem_master_w_wdata output [63 : 0] cpu_dmem_master_wdata; - // value method cpu_dmem_master_m_wstrb + // value method cpu_dmem_master_w_wstrb output [7 : 0] cpu_dmem_master_wstrb; - // value method cpu_dmem_master_m_wlast + // value method cpu_dmem_master_w_wlast output cpu_dmem_master_wlast; - // value method cpu_dmem_master_m_wuser + // value method cpu_dmem_master_w_wuser + + // value method cpu_dmem_master_w_wvalid + output cpu_dmem_master_wvalid; - // action method cpu_dmem_master_m_wready + // action method cpu_dmem_master_w_wready input cpu_dmem_master_wready; - // action method cpu_dmem_master_m_bvalid - input cpu_dmem_master_bvalid; - input [3 : 0] cpu_dmem_master_bid; + // action method cpu_dmem_master_b_bflit + input [4 : 0] cpu_dmem_master_bid; input [1 : 0] cpu_dmem_master_bresp; + input cpu_dmem_master_bvalid; - // value method cpu_dmem_master_m_bready + // value method cpu_dmem_master_b_bready output cpu_dmem_master_bready; - // value method cpu_dmem_master_m_arvalid - output cpu_dmem_master_arvalid; - - // value method cpu_dmem_master_m_arid - output [3 : 0] cpu_dmem_master_arid; + // value method cpu_dmem_master_ar_arid + output [4 : 0] cpu_dmem_master_arid; - // value method cpu_dmem_master_m_araddr + // value method cpu_dmem_master_ar_araddr output [63 : 0] cpu_dmem_master_araddr; - // value method cpu_dmem_master_m_arlen + // value method cpu_dmem_master_ar_arlen output [7 : 0] cpu_dmem_master_arlen; - // value method cpu_dmem_master_m_arsize + // value method cpu_dmem_master_ar_arsize output [2 : 0] cpu_dmem_master_arsize; - // value method cpu_dmem_master_m_arburst + // value method cpu_dmem_master_ar_arburst output [1 : 0] cpu_dmem_master_arburst; - // value method cpu_dmem_master_m_arlock + // value method cpu_dmem_master_ar_arlock output cpu_dmem_master_arlock; - // value method cpu_dmem_master_m_arcache + // value method cpu_dmem_master_ar_arcache output [3 : 0] cpu_dmem_master_arcache; - // value method cpu_dmem_master_m_arprot + // value method cpu_dmem_master_ar_arprot output [2 : 0] cpu_dmem_master_arprot; - // value method cpu_dmem_master_m_arqos + // value method cpu_dmem_master_ar_arqos output [3 : 0] cpu_dmem_master_arqos; - // value method cpu_dmem_master_m_arregion + // value method cpu_dmem_master_ar_arregion output [3 : 0] cpu_dmem_master_arregion; - // value method cpu_dmem_master_m_aruser + // value method cpu_dmem_master_ar_aruser + + // value method cpu_dmem_master_ar_arvalid + output cpu_dmem_master_arvalid; - // action method cpu_dmem_master_m_arready + // action method cpu_dmem_master_ar_arready input cpu_dmem_master_arready; - // action method cpu_dmem_master_m_rvalid - input cpu_dmem_master_rvalid; - input [3 : 0] cpu_dmem_master_rid; + // action method cpu_dmem_master_r_rflit + input [4 : 0] cpu_dmem_master_rid; input [63 : 0] cpu_dmem_master_rdata; input [1 : 0] cpu_dmem_master_rresp; input cpu_dmem_master_rlast; + input cpu_dmem_master_rvalid; - // value method cpu_dmem_master_m_rready + // value method cpu_dmem_master_r_rready output cpu_dmem_master_rready; // action method core_external_interrupt_sources_0_m_interrupt_req @@ -712,20 +770,20 @@ module mkCore(CLK, cpu_imem_master_arlen, cpu_imem_master_awlen, cpu_imem_master_wstrb; + wire [4 : 0] cpu_dmem_master_arid, + cpu_dmem_master_awid, + cpu_imem_master_arid, + cpu_imem_master_awid; wire [3 : 0] cpu_dmem_master_arcache, - cpu_dmem_master_arid, cpu_dmem_master_arqos, cpu_dmem_master_arregion, cpu_dmem_master_awcache, - cpu_dmem_master_awid, cpu_dmem_master_awqos, cpu_dmem_master_awregion, cpu_imem_master_arcache, - cpu_imem_master_arid, cpu_imem_master_arqos, cpu_imem_master_arregion, cpu_imem_master_awcache, - cpu_imem_master_awid, cpu_imem_master_awqos, cpu_imem_master_awregion; wire [2 : 0] cpu_dmem_master_arprot, @@ -768,6 +826,293 @@ module mkCore(CLK, cpu_reset_server_response_get, ndm_reset_client_request_get; + // inlined wires + wire [171 : 0] split_0_doPut$wget, split_1_doPut$wget, split_2_doPut$wget; + wire [97 : 0] ssNoSynth_0_ar_buffer_enqw$wget, + ssNoSynth_1_ar_buffer_enqw$wget, + ssNoSynth_1_aw_buffer_enqw$wget, + ssNoSynth_2_ar_buffer_enqw$wget, + ssNoSynth_2_aw_buffer_enqw$wget; + wire [96 : 0] ifcs_0_1_noRoute_currentReq$port0__write_1, + ifcs_0_1_noRoute_currentReq$port1__read, + ifcs_0_noRoute_inner_currentReq$port0__write_1, + ifcs_0_noRoute_inner_currentReq$port1__read, + ifcs_1_1_noRoute_currentReq$port0__write_1, + ifcs_1_1_noRoute_currentReq$port1__read, + ifcs_1_noRoute_inner_currentReq$port0__write_1, + ifcs_1_noRoute_inner_currentReq$port1__read; + wire [72 : 0] ssNoSynth_1_w_buffer_enqw$wget, + ssNoSynth_2_w_buffer_enqw$wget; + wire [70 : 0] msNoSynth_0_r_buffer_enqw$wget, + msNoSynth_1_r_buffer_enqw$wget; + wire [8 : 0] ifcs_0_1_noRoute_flitCount$port0__write_1, + ifcs_0_1_noRoute_flitCount$port1__write_1, + ifcs_0_1_noRoute_flitCount$port2__read, + ifcs_1_1_noRoute_flitCount$port0__write_1, + ifcs_1_1_noRoute_flitCount$port1__write_1, + ifcs_1_1_noRoute_flitCount$port2__read; + wire [5 : 0] msNoSynth_0_b_buffer_enqw$wget, msNoSynth_1_b_buffer_enqw$wget; + wire flitToSink_0$whas, + flitToSink_1$whas, + flitToSink_1_0$whas, + flitToSink_1_0_1$whas, + flitToSink_1_1$whas, + flitToSink_1_1_0$whas, + flitToSink_1_1_1$whas, + flitToSink_1_1_1_1$whas, + flitToSink_1_2$whas, + flitToSink_2$whas, + ifcs_0_noRoute_inner_currentReq$EN_port0__write, + ifcs_0_noRoute_inner_pendingReq$EN_port0__write, + ifcs_0_noRoute_inner_pendingReq$port1__read, + ifcs_0_noRoute_inner_pendingReq$port2__read, + ifcs_1_noRoute_inner_currentReq$EN_port0__write, + ifcs_1_noRoute_inner_pendingReq$EN_port0__write, + ifcs_1_noRoute_inner_pendingReq$port1__read, + ifcs_1_noRoute_inner_pendingReq$port2__read, + merged_0_doDrop$whas, + merged_1_doDrop$whas, + msNoSynth_0_ar_dwReady$whas, + msNoSynth_0_b_buffer_enqw$whas, + msNoSynth_0_r_buffer_enqw$whas, + msNoSynth_0_w_dwReady$whas, + msNoSynth_1_ar_dwReady$whas, + msNoSynth_1_b_buffer_enqw$whas, + msNoSynth_1_r_buffer_enqw$whas, + msNoSynth_1_w_dwReady$whas, + reqWires_0$wget, + reqWires_1$wget, + reqWires_1_0$wget, + reqWires_1_0_1$wget, + reqWires_1_1$wget, + reqWires_1_1_0$wget, + reqWires_1_1_1$wget, + reqWires_1_1_1_1$wget, + reqWires_1_1_2$wget, + reqWires_1_2$wget, + sourceSelect_1_0$whas, + sourceSelect_1_0_1$whas, + sourceSelect_1_1$whas, + sourceSelect_1_1_1$whas, + sourceSelect_1_2$whas, + ssNoSynth_0_b_dwReady$whas, + ssNoSynth_0_r_dwReady$whas, + ssNoSynth_0_w_buffer_enqw$whas, + ssNoSynth_1_b_dwReady$whas, + ssNoSynth_1_r_dwReady$whas, + ssNoSynth_1_w_buffer_enqw$whas, + ssNoSynth_2_b_dwReady$whas, + ssNoSynth_2_r_dwReady$whas, + ssNoSynth_2_w_buffer_enqw$whas; + + // register activeSource_0 + reg activeSource_0; + wire activeSource_0$D_IN, activeSource_0$EN; + + // register activeSource_1 + reg activeSource_1; + wire activeSource_1$D_IN, activeSource_1$EN; + + // register activeSource_1_0 + reg activeSource_1_0; + wire activeSource_1_0$D_IN, activeSource_1_0$EN; + + // register activeSource_1_0_1 + reg activeSource_1_0_1; + wire activeSource_1_0_1$D_IN, activeSource_1_0_1$EN; + + // register activeSource_1_1 + reg activeSource_1_1; + wire activeSource_1_1$D_IN, activeSource_1_1$EN; + + // register activeSource_1_1_0 + reg activeSource_1_1_0; + reg activeSource_1_1_0$D_IN; + wire activeSource_1_1_0$EN; + + // register activeSource_1_1_1 + reg activeSource_1_1_1; + wire activeSource_1_1_1$D_IN, activeSource_1_1_1$EN; + + // register activeSource_1_1_1_1 + reg activeSource_1_1_1_1; + reg activeSource_1_1_1_1$D_IN; + wire activeSource_1_1_1_1$EN; + + // register activeSource_1_1_2 + reg activeSource_1_1_2; + reg activeSource_1_1_2$D_IN; + wire activeSource_1_1_2$EN; + + // register activeSource_1_2 + reg activeSource_1_2; + wire activeSource_1_2$D_IN, activeSource_1_2$EN; + + // register arbiter_1_1_firstHot + reg arbiter_1_1_firstHot; + wire arbiter_1_1_firstHot$D_IN, arbiter_1_1_firstHot$EN; + + // register arbiter_1_1_lastSelect + reg arbiter_1_1_lastSelect; + wire arbiter_1_1_lastSelect$D_IN, arbiter_1_1_lastSelect$EN; + + // register arbiter_1_1_lastSelect_1 + reg arbiter_1_1_lastSelect_1; + wire arbiter_1_1_lastSelect_1$D_IN, arbiter_1_1_lastSelect_1$EN; + + // register arbiter_1_firstHot + reg arbiter_1_firstHot; + wire arbiter_1_firstHot$D_IN, arbiter_1_firstHot$EN; + + // register arbiter_1_firstHot_1 + reg arbiter_1_firstHot_1; + wire arbiter_1_firstHot_1$D_IN, arbiter_1_firstHot_1$EN; + + // register arbiter_1_lastSelect + reg arbiter_1_lastSelect; + wire arbiter_1_lastSelect$D_IN, arbiter_1_lastSelect$EN; + + // register arbiter_1_lastSelect_1 + reg arbiter_1_lastSelect_1; + wire arbiter_1_lastSelect_1$D_IN, arbiter_1_lastSelect_1$EN; + + // register arbiter_1_lastSelect_2 + reg arbiter_1_lastSelect_2; + wire arbiter_1_lastSelect_2$D_IN, arbiter_1_lastSelect_2$EN; + + // register arbiter_firstHot + reg arbiter_firstHot; + wire arbiter_firstHot$D_IN, arbiter_firstHot$EN; + + // register arbiter_lastSelect + reg arbiter_lastSelect; + wire arbiter_lastSelect$D_IN, arbiter_lastSelect$EN; + + // register ifcs_0_1_noRoute_currentReq + reg [96 : 0] ifcs_0_1_noRoute_currentReq; + wire [96 : 0] ifcs_0_1_noRoute_currentReq$D_IN; + wire ifcs_0_1_noRoute_currentReq$EN; + + // register ifcs_0_1_noRoute_flitCount + reg [8 : 0] ifcs_0_1_noRoute_flitCount; + wire [8 : 0] ifcs_0_1_noRoute_flitCount$D_IN; + wire ifcs_0_1_noRoute_flitCount$EN; + + // register ifcs_0_1_state + reg [1 : 0] ifcs_0_1_state; + wire [1 : 0] ifcs_0_1_state$D_IN; + wire ifcs_0_1_state$EN; + + // register ifcs_0_1_state_1 + reg ifcs_0_1_state_1; + wire ifcs_0_1_state_1$D_IN, ifcs_0_1_state_1$EN; + + // register ifcs_0_noRoute_inner_currentReq + reg [96 : 0] ifcs_0_noRoute_inner_currentReq; + wire [96 : 0] ifcs_0_noRoute_inner_currentReq$D_IN; + wire ifcs_0_noRoute_inner_currentReq$EN; + + // register ifcs_0_noRoute_inner_pendingReq + reg ifcs_0_noRoute_inner_pendingReq; + wire ifcs_0_noRoute_inner_pendingReq$D_IN, + ifcs_0_noRoute_inner_pendingReq$EN; + + // register ifcs_0_state + reg [1 : 0] ifcs_0_state; + reg [1 : 0] ifcs_0_state$D_IN; + wire ifcs_0_state$EN; + + // register ifcs_0_state_1 + reg ifcs_0_state_1; + wire ifcs_0_state_1$D_IN, ifcs_0_state_1$EN; + + // register ifcs_1_1_noRoute_currentReq + reg [96 : 0] ifcs_1_1_noRoute_currentReq; + wire [96 : 0] ifcs_1_1_noRoute_currentReq$D_IN; + wire ifcs_1_1_noRoute_currentReq$EN; + + // register ifcs_1_1_noRoute_flitCount + reg [8 : 0] ifcs_1_1_noRoute_flitCount; + wire [8 : 0] ifcs_1_1_noRoute_flitCount$D_IN; + wire ifcs_1_1_noRoute_flitCount$EN; + + // register ifcs_1_1_state + reg [1 : 0] ifcs_1_1_state; + wire [1 : 0] ifcs_1_1_state$D_IN; + wire ifcs_1_1_state$EN; + + // register ifcs_1_1_state_1 + reg ifcs_1_1_state_1; + wire ifcs_1_1_state_1$D_IN, ifcs_1_1_state_1$EN; + + // register ifcs_1_noRoute_inner_currentReq + reg [96 : 0] ifcs_1_noRoute_inner_currentReq; + wire [96 : 0] ifcs_1_noRoute_inner_currentReq$D_IN; + wire ifcs_1_noRoute_inner_currentReq$EN; + + // register ifcs_1_noRoute_inner_pendingReq + reg ifcs_1_noRoute_inner_pendingReq; + wire ifcs_1_noRoute_inner_pendingReq$D_IN, + ifcs_1_noRoute_inner_pendingReq$EN; + + // register ifcs_1_state + reg [1 : 0] ifcs_1_state; + reg [1 : 0] ifcs_1_state$D_IN; + wire ifcs_1_state$EN; + + // register ifcs_1_state_1 + reg ifcs_1_state_1; + wire ifcs_1_state_1$D_IN, ifcs_1_state_1$EN; + + // register ifcs_2_1_state + reg ifcs_2_1_state; + wire ifcs_2_1_state$D_IN, ifcs_2_1_state$EN; + + // register ifcs_2_state + reg ifcs_2_state; + wire ifcs_2_state$D_IN, ifcs_2_state$EN; + + // register merged_0_flitLeft + reg [7 : 0] merged_0_flitLeft; + wire [7 : 0] merged_0_flitLeft$D_IN; + wire merged_0_flitLeft$EN; + + // register merged_1_flitLeft + reg [7 : 0] merged_1_flitLeft; + wire [7 : 0] merged_1_flitLeft$D_IN; + wire merged_1_flitLeft$EN; + + // register split_0_flitLeft + reg [7 : 0] split_0_flitLeft; + wire [7 : 0] split_0_flitLeft$D_IN; + wire split_0_flitLeft$EN; + + // register split_1_flitLeft + reg [7 : 0] split_1_flitLeft; + wire [7 : 0] split_1_flitLeft$D_IN; + wire split_1_flitLeft$EN; + + // register split_2_flitLeft + reg [7 : 0] split_2_flitLeft; + wire [7 : 0] split_2_flitLeft$D_IN; + wire split_2_flitLeft$EN; + + // register state + reg state; + wire state$D_IN, state$EN; + + // register state_1 + reg state_1; + wire state_1$D_IN, state_1$EN; + + // register state_1_1 + reg state_1_1; + wire state_1_1$D_IN, state_1_1$EN; + + // register state_1_1_1 + reg state_1_1_1; + wire state_1_1_1$D_IN, state_1_1_1$EN; + // ports of submodule cpu wire [233 : 0] cpu$trace_data_out_get; wire [63 : 0] cpu$dmem_master_araddr, @@ -789,6 +1134,10 @@ module mkCore(CLK, cpu$imem_master_arlen, cpu$imem_master_awlen, cpu$imem_master_wstrb; + wire [4 : 0] cpu$imem_master_arid, + cpu$imem_master_awid, + cpu$imem_master_bid, + cpu$imem_master_rid; wire [3 : 0] cpu$dmem_master_arcache, cpu$dmem_master_arid, cpu$dmem_master_arqos, @@ -801,15 +1150,11 @@ module mkCore(CLK, cpu$dmem_master_rid, cpu$hart0_put_other_req_put, cpu$imem_master_arcache, - cpu$imem_master_arid, cpu$imem_master_arqos, cpu$imem_master_arregion, cpu$imem_master_awcache, - cpu$imem_master_awid, cpu$imem_master_awqos, cpu$imem_master_awregion, - cpu$imem_master_bid, - cpu$imem_master_rid, cpu$set_verbosity_verbosity; wire [2 : 0] cpu$dmem_master_arprot, cpu$dmem_master_arsize, @@ -1120,206 +1465,249 @@ module mkCore(CLK, f_trace_data_merged$ENQ, f_trace_data_merged$FULL_N; - // ports of submodule fabric_2x3 - wire [63 : 0] fabric_2x3$v_from_masters_0_araddr, - fabric_2x3$v_from_masters_0_awaddr, - fabric_2x3$v_from_masters_0_rdata, - fabric_2x3$v_from_masters_0_wdata, - fabric_2x3$v_from_masters_1_araddr, - fabric_2x3$v_from_masters_1_awaddr, - fabric_2x3$v_from_masters_1_rdata, - fabric_2x3$v_from_masters_1_wdata, - fabric_2x3$v_to_slaves_0_araddr, - fabric_2x3$v_to_slaves_0_awaddr, - fabric_2x3$v_to_slaves_0_rdata, - fabric_2x3$v_to_slaves_0_wdata, - fabric_2x3$v_to_slaves_1_araddr, - fabric_2x3$v_to_slaves_1_awaddr, - fabric_2x3$v_to_slaves_1_rdata, - fabric_2x3$v_to_slaves_1_wdata, - fabric_2x3$v_to_slaves_2_araddr, - fabric_2x3$v_to_slaves_2_awaddr, - fabric_2x3$v_to_slaves_2_rdata, - fabric_2x3$v_to_slaves_2_wdata; - wire [7 : 0] fabric_2x3$v_from_masters_0_arlen, - fabric_2x3$v_from_masters_0_awlen, - fabric_2x3$v_from_masters_0_wstrb, - fabric_2x3$v_from_masters_1_arlen, - fabric_2x3$v_from_masters_1_awlen, - fabric_2x3$v_from_masters_1_wstrb, - fabric_2x3$v_to_slaves_0_arlen, - fabric_2x3$v_to_slaves_0_awlen, - fabric_2x3$v_to_slaves_0_wstrb, - fabric_2x3$v_to_slaves_1_arlen, - fabric_2x3$v_to_slaves_1_awlen, - fabric_2x3$v_to_slaves_1_wstrb, - fabric_2x3$v_to_slaves_2_arlen, - fabric_2x3$v_to_slaves_2_awlen, - fabric_2x3$v_to_slaves_2_wstrb; - wire [3 : 0] fabric_2x3$set_verbosity_verbosity, - fabric_2x3$v_from_masters_0_arcache, - fabric_2x3$v_from_masters_0_arid, - fabric_2x3$v_from_masters_0_arqos, - fabric_2x3$v_from_masters_0_arregion, - fabric_2x3$v_from_masters_0_awcache, - fabric_2x3$v_from_masters_0_awid, - fabric_2x3$v_from_masters_0_awqos, - fabric_2x3$v_from_masters_0_awregion, - fabric_2x3$v_from_masters_0_bid, - fabric_2x3$v_from_masters_0_rid, - fabric_2x3$v_from_masters_1_arcache, - fabric_2x3$v_from_masters_1_arid, - fabric_2x3$v_from_masters_1_arqos, - fabric_2x3$v_from_masters_1_arregion, - fabric_2x3$v_from_masters_1_awcache, - fabric_2x3$v_from_masters_1_awid, - fabric_2x3$v_from_masters_1_awqos, - fabric_2x3$v_from_masters_1_awregion, - fabric_2x3$v_from_masters_1_bid, - fabric_2x3$v_from_masters_1_rid, - fabric_2x3$v_to_slaves_0_arcache, - fabric_2x3$v_to_slaves_0_arid, - fabric_2x3$v_to_slaves_0_arqos, - fabric_2x3$v_to_slaves_0_arregion, - fabric_2x3$v_to_slaves_0_awcache, - fabric_2x3$v_to_slaves_0_awid, - fabric_2x3$v_to_slaves_0_awqos, - fabric_2x3$v_to_slaves_0_awregion, - fabric_2x3$v_to_slaves_0_bid, - fabric_2x3$v_to_slaves_0_rid, - fabric_2x3$v_to_slaves_1_arcache, - fabric_2x3$v_to_slaves_1_arid, - fabric_2x3$v_to_slaves_1_arqos, - fabric_2x3$v_to_slaves_1_arregion, - fabric_2x3$v_to_slaves_1_awcache, - fabric_2x3$v_to_slaves_1_awid, - fabric_2x3$v_to_slaves_1_awqos, - fabric_2x3$v_to_slaves_1_awregion, - fabric_2x3$v_to_slaves_1_bid, - fabric_2x3$v_to_slaves_1_rid, - fabric_2x3$v_to_slaves_2_arcache, - fabric_2x3$v_to_slaves_2_arid, - fabric_2x3$v_to_slaves_2_arqos, - fabric_2x3$v_to_slaves_2_arregion, - fabric_2x3$v_to_slaves_2_awcache, - fabric_2x3$v_to_slaves_2_awid, - fabric_2x3$v_to_slaves_2_awqos, - fabric_2x3$v_to_slaves_2_awregion, - fabric_2x3$v_to_slaves_2_bid, - fabric_2x3$v_to_slaves_2_rid; - wire [2 : 0] fabric_2x3$v_from_masters_0_arprot, - fabric_2x3$v_from_masters_0_arsize, - fabric_2x3$v_from_masters_0_awprot, - fabric_2x3$v_from_masters_0_awsize, - fabric_2x3$v_from_masters_1_arprot, - fabric_2x3$v_from_masters_1_arsize, - fabric_2x3$v_from_masters_1_awprot, - fabric_2x3$v_from_masters_1_awsize, - fabric_2x3$v_to_slaves_0_arprot, - fabric_2x3$v_to_slaves_0_arsize, - fabric_2x3$v_to_slaves_0_awprot, - fabric_2x3$v_to_slaves_0_awsize, - fabric_2x3$v_to_slaves_1_arprot, - fabric_2x3$v_to_slaves_1_arsize, - fabric_2x3$v_to_slaves_1_awprot, - fabric_2x3$v_to_slaves_1_awsize, - fabric_2x3$v_to_slaves_2_arprot, - fabric_2x3$v_to_slaves_2_arsize, - fabric_2x3$v_to_slaves_2_awprot, - fabric_2x3$v_to_slaves_2_awsize; - wire [1 : 0] fabric_2x3$v_from_masters_0_arburst, - fabric_2x3$v_from_masters_0_awburst, - fabric_2x3$v_from_masters_0_bresp, - fabric_2x3$v_from_masters_0_rresp, - fabric_2x3$v_from_masters_1_arburst, - fabric_2x3$v_from_masters_1_awburst, - fabric_2x3$v_from_masters_1_bresp, - fabric_2x3$v_from_masters_1_rresp, - fabric_2x3$v_to_slaves_0_arburst, - fabric_2x3$v_to_slaves_0_awburst, - fabric_2x3$v_to_slaves_0_bresp, - fabric_2x3$v_to_slaves_0_rresp, - fabric_2x3$v_to_slaves_1_arburst, - fabric_2x3$v_to_slaves_1_awburst, - fabric_2x3$v_to_slaves_1_bresp, - fabric_2x3$v_to_slaves_1_rresp, - fabric_2x3$v_to_slaves_2_arburst, - fabric_2x3$v_to_slaves_2_awburst, - fabric_2x3$v_to_slaves_2_bresp, - fabric_2x3$v_to_slaves_2_rresp; - wire fabric_2x3$EN_reset, - fabric_2x3$EN_set_verbosity, - fabric_2x3$RDY_reset, - fabric_2x3$v_from_masters_0_arlock, - fabric_2x3$v_from_masters_0_arready, - fabric_2x3$v_from_masters_0_arvalid, - fabric_2x3$v_from_masters_0_awlock, - fabric_2x3$v_from_masters_0_awready, - fabric_2x3$v_from_masters_0_awvalid, - fabric_2x3$v_from_masters_0_bready, - fabric_2x3$v_from_masters_0_bvalid, - fabric_2x3$v_from_masters_0_rlast, - fabric_2x3$v_from_masters_0_rready, - fabric_2x3$v_from_masters_0_rvalid, - fabric_2x3$v_from_masters_0_wlast, - fabric_2x3$v_from_masters_0_wready, - fabric_2x3$v_from_masters_0_wvalid, - fabric_2x3$v_from_masters_1_arlock, - fabric_2x3$v_from_masters_1_arready, - fabric_2x3$v_from_masters_1_arvalid, - fabric_2x3$v_from_masters_1_awlock, - fabric_2x3$v_from_masters_1_awready, - fabric_2x3$v_from_masters_1_awvalid, - fabric_2x3$v_from_masters_1_bready, - fabric_2x3$v_from_masters_1_bvalid, - fabric_2x3$v_from_masters_1_rlast, - fabric_2x3$v_from_masters_1_rready, - fabric_2x3$v_from_masters_1_rvalid, - fabric_2x3$v_from_masters_1_wlast, - fabric_2x3$v_from_masters_1_wready, - fabric_2x3$v_from_masters_1_wvalid, - fabric_2x3$v_to_slaves_0_arlock, - fabric_2x3$v_to_slaves_0_arready, - fabric_2x3$v_to_slaves_0_arvalid, - fabric_2x3$v_to_slaves_0_awlock, - fabric_2x3$v_to_slaves_0_awready, - fabric_2x3$v_to_slaves_0_awvalid, - fabric_2x3$v_to_slaves_0_bready, - fabric_2x3$v_to_slaves_0_bvalid, - fabric_2x3$v_to_slaves_0_rlast, - fabric_2x3$v_to_slaves_0_rready, - fabric_2x3$v_to_slaves_0_rvalid, - fabric_2x3$v_to_slaves_0_wlast, - fabric_2x3$v_to_slaves_0_wready, - fabric_2x3$v_to_slaves_0_wvalid, - fabric_2x3$v_to_slaves_1_arlock, - fabric_2x3$v_to_slaves_1_arready, - fabric_2x3$v_to_slaves_1_arvalid, - fabric_2x3$v_to_slaves_1_awlock, - fabric_2x3$v_to_slaves_1_awready, - fabric_2x3$v_to_slaves_1_awvalid, - fabric_2x3$v_to_slaves_1_bready, - fabric_2x3$v_to_slaves_1_bvalid, - fabric_2x3$v_to_slaves_1_rlast, - fabric_2x3$v_to_slaves_1_rready, - fabric_2x3$v_to_slaves_1_rvalid, - fabric_2x3$v_to_slaves_1_wlast, - fabric_2x3$v_to_slaves_1_wready, - fabric_2x3$v_to_slaves_1_wvalid, - fabric_2x3$v_to_slaves_2_arlock, - fabric_2x3$v_to_slaves_2_arready, - fabric_2x3$v_to_slaves_2_arvalid, - fabric_2x3$v_to_slaves_2_awlock, - fabric_2x3$v_to_slaves_2_awready, - fabric_2x3$v_to_slaves_2_awvalid, - fabric_2x3$v_to_slaves_2_bready, - fabric_2x3$v_to_slaves_2_bvalid, - fabric_2x3$v_to_slaves_2_rlast, - fabric_2x3$v_to_slaves_2_rready, - fabric_2x3$v_to_slaves_2_rvalid, - fabric_2x3$v_to_slaves_2_wlast, - fabric_2x3$v_to_slaves_2_wready, - fabric_2x3$v_to_slaves_2_wvalid; + // ports of submodule ifcs_0_1_innerReq + wire [97 : 0] ifcs_0_1_innerReq$D_IN, ifcs_0_1_innerReq$D_OUT; + wire ifcs_0_1_innerReq$CLR, + ifcs_0_1_innerReq$DEQ, + ifcs_0_1_innerReq$EMPTY_N, + ifcs_0_1_innerReq$ENQ, + ifcs_0_1_innerReq$FULL_N; + + // ports of submodule ifcs_0_1_innerRoute + wire [2 : 0] ifcs_0_1_innerRoute$D_IN, ifcs_0_1_innerRoute$D_OUT; + wire ifcs_0_1_innerRoute$CLR, + ifcs_0_1_innerRoute$DEQ, + ifcs_0_1_innerRoute$EMPTY_N, + ifcs_0_1_innerRoute$ENQ, + ifcs_0_1_innerRoute$FULL_N; + + // ports of submodule ifcs_0_1_noRouteRsp + wire [70 : 0] ifcs_0_1_noRouteRsp$D_IN, ifcs_0_1_noRouteRsp$D_OUT; + wire ifcs_0_1_noRouteRsp$CLR, + ifcs_0_1_noRouteRsp$DEQ, + ifcs_0_1_noRouteRsp$EMPTY_N, + ifcs_0_1_noRouteRsp$ENQ, + ifcs_0_1_noRouteRsp$FULL_N; + + // ports of submodule ifcs_0_1_routeBack + wire [1 : 0] ifcs_0_1_routeBack$D_IN, ifcs_0_1_routeBack$D_OUT; + wire ifcs_0_1_routeBack$CLR, + ifcs_0_1_routeBack$DEQ, + ifcs_0_1_routeBack$EMPTY_N, + ifcs_0_1_routeBack$ENQ, + ifcs_0_1_routeBack$FULL_N; + + // ports of submodule ifcs_0_1_rspBack + wire [70 : 0] ifcs_0_1_rspBack$D_IN, ifcs_0_1_rspBack$D_OUT; + wire ifcs_0_1_rspBack$CLR, + ifcs_0_1_rspBack$DEQ, + ifcs_0_1_rspBack$EMPTY_N, + ifcs_0_1_rspBack$ENQ, + ifcs_0_1_rspBack$FULL_N; + + // ports of submodule ifcs_0_innerReq + wire [171 : 0] ifcs_0_innerReq$D_IN, ifcs_0_innerReq$D_OUT; + wire ifcs_0_innerReq$CLR, + ifcs_0_innerReq$DEQ, + ifcs_0_innerReq$EMPTY_N, + ifcs_0_innerReq$ENQ, + ifcs_0_innerReq$FULL_N; + + // ports of submodule ifcs_0_innerRoute + wire [2 : 0] ifcs_0_innerRoute$D_IN, ifcs_0_innerRoute$D_OUT; + wire ifcs_0_innerRoute$CLR, + ifcs_0_innerRoute$DEQ, + ifcs_0_innerRoute$EMPTY_N, + ifcs_0_innerRoute$ENQ, + ifcs_0_innerRoute$FULL_N; + + // ports of submodule ifcs_0_noRouteRsp + wire [5 : 0] ifcs_0_noRouteRsp$D_IN, ifcs_0_noRouteRsp$D_OUT; + wire ifcs_0_noRouteRsp$CLR, + ifcs_0_noRouteRsp$DEQ, + ifcs_0_noRouteRsp$EMPTY_N, + ifcs_0_noRouteRsp$ENQ, + ifcs_0_noRouteRsp$FULL_N; + + // ports of submodule ifcs_0_routeBack + wire [1 : 0] ifcs_0_routeBack$D_IN, ifcs_0_routeBack$D_OUT; + wire ifcs_0_routeBack$CLR, + ifcs_0_routeBack$DEQ, + ifcs_0_routeBack$EMPTY_N, + ifcs_0_routeBack$ENQ, + ifcs_0_routeBack$FULL_N; + + // ports of submodule ifcs_0_rspBack + wire [5 : 0] ifcs_0_rspBack$D_IN, ifcs_0_rspBack$D_OUT; + wire ifcs_0_rspBack$CLR, + ifcs_0_rspBack$DEQ, + ifcs_0_rspBack$EMPTY_N, + ifcs_0_rspBack$ENQ, + ifcs_0_rspBack$FULL_N; + + // ports of submodule ifcs_1_1_innerReq + wire [97 : 0] ifcs_1_1_innerReq$D_IN, ifcs_1_1_innerReq$D_OUT; + wire ifcs_1_1_innerReq$CLR, + ifcs_1_1_innerReq$DEQ, + ifcs_1_1_innerReq$EMPTY_N, + ifcs_1_1_innerReq$ENQ, + ifcs_1_1_innerReq$FULL_N; + + // ports of submodule ifcs_1_1_innerRoute + wire [2 : 0] ifcs_1_1_innerRoute$D_IN, ifcs_1_1_innerRoute$D_OUT; + wire ifcs_1_1_innerRoute$CLR, + ifcs_1_1_innerRoute$DEQ, + ifcs_1_1_innerRoute$EMPTY_N, + ifcs_1_1_innerRoute$ENQ, + ifcs_1_1_innerRoute$FULL_N; + + // ports of submodule ifcs_1_1_noRouteRsp + wire [70 : 0] ifcs_1_1_noRouteRsp$D_IN, ifcs_1_1_noRouteRsp$D_OUT; + wire ifcs_1_1_noRouteRsp$CLR, + ifcs_1_1_noRouteRsp$DEQ, + ifcs_1_1_noRouteRsp$EMPTY_N, + ifcs_1_1_noRouteRsp$ENQ, + ifcs_1_1_noRouteRsp$FULL_N; + + // ports of submodule ifcs_1_1_routeBack + wire [1 : 0] ifcs_1_1_routeBack$D_IN, ifcs_1_1_routeBack$D_OUT; + wire ifcs_1_1_routeBack$CLR, + ifcs_1_1_routeBack$DEQ, + ifcs_1_1_routeBack$EMPTY_N, + ifcs_1_1_routeBack$ENQ, + ifcs_1_1_routeBack$FULL_N; + + // ports of submodule ifcs_1_1_rspBack + wire [70 : 0] ifcs_1_1_rspBack$D_IN, ifcs_1_1_rspBack$D_OUT; + wire ifcs_1_1_rspBack$CLR, + ifcs_1_1_rspBack$DEQ, + ifcs_1_1_rspBack$EMPTY_N, + ifcs_1_1_rspBack$ENQ, + ifcs_1_1_rspBack$FULL_N; + + // ports of submodule ifcs_1_innerReq + wire [171 : 0] ifcs_1_innerReq$D_IN, ifcs_1_innerReq$D_OUT; + wire ifcs_1_innerReq$CLR, + ifcs_1_innerReq$DEQ, + ifcs_1_innerReq$EMPTY_N, + ifcs_1_innerReq$ENQ, + ifcs_1_innerReq$FULL_N; + + // ports of submodule ifcs_1_innerRoute + wire [2 : 0] ifcs_1_innerRoute$D_IN, ifcs_1_innerRoute$D_OUT; + wire ifcs_1_innerRoute$CLR, + ifcs_1_innerRoute$DEQ, + ifcs_1_innerRoute$EMPTY_N, + ifcs_1_innerRoute$ENQ, + ifcs_1_innerRoute$FULL_N; + + // ports of submodule ifcs_1_noRouteRsp + wire [5 : 0] ifcs_1_noRouteRsp$D_IN, ifcs_1_noRouteRsp$D_OUT; + wire ifcs_1_noRouteRsp$CLR, + ifcs_1_noRouteRsp$DEQ, + ifcs_1_noRouteRsp$EMPTY_N, + ifcs_1_noRouteRsp$ENQ, + ifcs_1_noRouteRsp$FULL_N; + + // ports of submodule ifcs_1_routeBack + wire [1 : 0] ifcs_1_routeBack$D_IN, ifcs_1_routeBack$D_OUT; + wire ifcs_1_routeBack$CLR, + ifcs_1_routeBack$DEQ, + ifcs_1_routeBack$EMPTY_N, + ifcs_1_routeBack$ENQ, + ifcs_1_routeBack$FULL_N; + + // ports of submodule ifcs_1_rspBack + wire [5 : 0] ifcs_1_rspBack$D_IN, ifcs_1_rspBack$D_OUT; + wire ifcs_1_rspBack$CLR, + ifcs_1_rspBack$DEQ, + ifcs_1_rspBack$EMPTY_N, + ifcs_1_rspBack$ENQ, + ifcs_1_rspBack$FULL_N; + + // ports of submodule ifcs_2_1_routeBack + wire [1 : 0] ifcs_2_1_routeBack$D_IN, ifcs_2_1_routeBack$D_OUT; + wire ifcs_2_1_routeBack$CLR, + ifcs_2_1_routeBack$DEQ, + ifcs_2_1_routeBack$EMPTY_N, + ifcs_2_1_routeBack$ENQ, + ifcs_2_1_routeBack$FULL_N; + + // ports of submodule ifcs_2_1_rspBack + wire [70 : 0] ifcs_2_1_rspBack$D_IN, ifcs_2_1_rspBack$D_OUT; + wire ifcs_2_1_rspBack$CLR, + ifcs_2_1_rspBack$DEQ, + ifcs_2_1_rspBack$EMPTY_N, + ifcs_2_1_rspBack$ENQ, + ifcs_2_1_rspBack$FULL_N; + + // ports of submodule ifcs_2_routeBack + wire [1 : 0] ifcs_2_routeBack$D_IN, ifcs_2_routeBack$D_OUT; + wire ifcs_2_routeBack$CLR, + ifcs_2_routeBack$DEQ, + ifcs_2_routeBack$EMPTY_N, + ifcs_2_routeBack$ENQ, + ifcs_2_routeBack$FULL_N; + + // ports of submodule ifcs_2_rspBack + wire [5 : 0] ifcs_2_rspBack$D_IN, ifcs_2_rspBack$D_OUT; + wire ifcs_2_rspBack$CLR, + ifcs_2_rspBack$DEQ, + ifcs_2_rspBack$EMPTY_N, + ifcs_2_rspBack$ENQ, + ifcs_2_rspBack$FULL_N; + + // ports of submodule msNoSynth_0_b_buffer_ff + wire [5 : 0] msNoSynth_0_b_buffer_ff$D_IN, msNoSynth_0_b_buffer_ff$D_OUT; + wire msNoSynth_0_b_buffer_ff$CLR, + msNoSynth_0_b_buffer_ff$DEQ, + msNoSynth_0_b_buffer_ff$EMPTY_N, + msNoSynth_0_b_buffer_ff$ENQ, + msNoSynth_0_b_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_b_buffer_firstValid + wire msNoSynth_0_b_buffer_firstValid$D_IN, + msNoSynth_0_b_buffer_firstValid$EN, + msNoSynth_0_b_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_0_r_buffer_ff + wire [70 : 0] msNoSynth_0_r_buffer_ff$D_IN, msNoSynth_0_r_buffer_ff$D_OUT; + wire msNoSynth_0_r_buffer_ff$CLR, + msNoSynth_0_r_buffer_ff$DEQ, + msNoSynth_0_r_buffer_ff$EMPTY_N, + msNoSynth_0_r_buffer_ff$ENQ, + msNoSynth_0_r_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_0_r_buffer_firstValid + wire msNoSynth_0_r_buffer_firstValid$D_IN, + msNoSynth_0_r_buffer_firstValid$EN, + msNoSynth_0_r_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_b_buffer_ff + wire [5 : 0] msNoSynth_1_b_buffer_ff$D_IN, msNoSynth_1_b_buffer_ff$D_OUT; + wire msNoSynth_1_b_buffer_ff$CLR, + msNoSynth_1_b_buffer_ff$DEQ, + msNoSynth_1_b_buffer_ff$EMPTY_N, + msNoSynth_1_b_buffer_ff$ENQ, + msNoSynth_1_b_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_b_buffer_firstValid + wire msNoSynth_1_b_buffer_firstValid$D_IN, + msNoSynth_1_b_buffer_firstValid$EN, + msNoSynth_1_b_buffer_firstValid$Q_OUT; + + // ports of submodule msNoSynth_1_r_buffer_ff + wire [70 : 0] msNoSynth_1_r_buffer_ff$D_IN, msNoSynth_1_r_buffer_ff$D_OUT; + wire msNoSynth_1_r_buffer_ff$CLR, + msNoSynth_1_r_buffer_ff$DEQ, + msNoSynth_1_r_buffer_ff$EMPTY_N, + msNoSynth_1_r_buffer_ff$ENQ, + msNoSynth_1_r_buffer_ff$FULL_N; + + // ports of submodule msNoSynth_1_r_buffer_firstValid + wire msNoSynth_1_r_buffer_firstValid$D_IN, + msNoSynth_1_r_buffer_firstValid$EN, + msNoSynth_1_r_buffer_firstValid$Q_OUT; // ports of submodule near_mem_io wire [63 : 0] near_mem_io$axi4_slave_araddr, @@ -1331,16 +1719,16 @@ module mkCore(CLK, wire [7 : 0] near_mem_io$axi4_slave_arlen, near_mem_io$axi4_slave_awlen, near_mem_io$axi4_slave_wstrb; + wire [4 : 0] near_mem_io$axi4_slave_arid, + near_mem_io$axi4_slave_awid, + near_mem_io$axi4_slave_bid, + near_mem_io$axi4_slave_rid; wire [3 : 0] near_mem_io$axi4_slave_arcache, - near_mem_io$axi4_slave_arid, near_mem_io$axi4_slave_arqos, near_mem_io$axi4_slave_arregion, near_mem_io$axi4_slave_awcache, - near_mem_io$axi4_slave_awid, near_mem_io$axi4_slave_awqos, - near_mem_io$axi4_slave_awregion, - near_mem_io$axi4_slave_bid, - near_mem_io$axi4_slave_rid; + near_mem_io$axi4_slave_awregion; wire [2 : 0] near_mem_io$axi4_slave_arprot, near_mem_io$axi4_slave_arsize, near_mem_io$axi4_slave_awprot, @@ -1385,16 +1773,16 @@ module mkCore(CLK, wire [7 : 0] plic$axi4_slave_arlen, plic$axi4_slave_awlen, plic$axi4_slave_wstrb; + wire [4 : 0] plic$axi4_slave_arid, + plic$axi4_slave_awid, + plic$axi4_slave_bid, + plic$axi4_slave_rid; wire [3 : 0] plic$axi4_slave_arcache, - plic$axi4_slave_arid, plic$axi4_slave_arqos, plic$axi4_slave_arregion, plic$axi4_slave_awcache, - plic$axi4_slave_awid, plic$axi4_slave_awqos, plic$axi4_slave_awregion, - plic$axi4_slave_bid, - plic$axi4_slave_rid, plic$set_verbosity_verbosity; wire [2 : 0] plic$axi4_slave_arprot, plic$axi4_slave_arsize, @@ -1444,14 +1832,168 @@ module mkCore(CLK, plic$v_targets_0_m_eip, plic$v_targets_1_m_eip; + // ports of submodule shim_arff + wire [97 : 0] shim_arff$D_IN, shim_arff$D_OUT; + wire shim_arff$CLR, + shim_arff$DEQ, + shim_arff$EMPTY_N, + shim_arff$ENQ, + shim_arff$FULL_N; + + // ports of submodule shim_awff + wire [97 : 0] shim_awff$D_IN, shim_awff$D_OUT; + wire shim_awff$CLR, + shim_awff$DEQ, + shim_awff$EMPTY_N, + shim_awff$ENQ, + shim_awff$FULL_N; + + // ports of submodule shim_bff + wire [6 : 0] shim_bff$D_IN, shim_bff$D_OUT; + wire shim_bff$CLR, + shim_bff$DEQ, + shim_bff$EMPTY_N, + shim_bff$ENQ, + shim_bff$FULL_N; + + // ports of submodule shim_rff + wire [71 : 0] shim_rff$D_IN, shim_rff$D_OUT; + wire shim_rff$CLR, + shim_rff$DEQ, + shim_rff$EMPTY_N, + shim_rff$ENQ, + shim_rff$FULL_N; + + // ports of submodule shim_wff + wire [72 : 0] shim_wff$D_IN, shim_wff$D_OUT; + wire shim_wff$CLR, + shim_wff$DEQ, + shim_wff$EMPTY_N, + shim_wff$ENQ, + shim_wff$FULL_N; + // ports of submodule soc_map + wire [127 : 0] soc_map$m_near_mem_io_addr_range, soc_map$m_plic_addr_range; wire [63 : 0] soc_map$m_is_IO_addr_addr, soc_map$m_is_mem_addr_addr, - soc_map$m_is_near_mem_IO_addr_addr, - soc_map$m_near_mem_io_addr_base, - soc_map$m_near_mem_io_addr_lim, - soc_map$m_plic_addr_base, - soc_map$m_plic_addr_lim; + soc_map$m_is_near_mem_IO_addr_addr; + + // ports of submodule ssNoSynth_0_ar_buffer_ff + wire [97 : 0] ssNoSynth_0_ar_buffer_ff$D_IN, ssNoSynth_0_ar_buffer_ff$D_OUT; + wire ssNoSynth_0_ar_buffer_ff$CLR, + ssNoSynth_0_ar_buffer_ff$DEQ, + ssNoSynth_0_ar_buffer_ff$EMPTY_N, + ssNoSynth_0_ar_buffer_ff$ENQ, + ssNoSynth_0_ar_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_0_ar_buffer_firstValid + wire ssNoSynth_0_ar_buffer_firstValid$D_IN, + ssNoSynth_0_ar_buffer_firstValid$EN, + ssNoSynth_0_ar_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_0_aw_buffer_ff + wire [97 : 0] ssNoSynth_0_aw_buffer_ff$D_IN, ssNoSynth_0_aw_buffer_ff$D_OUT; + wire ssNoSynth_0_aw_buffer_ff$CLR, + ssNoSynth_0_aw_buffer_ff$DEQ, + ssNoSynth_0_aw_buffer_ff$EMPTY_N, + ssNoSynth_0_aw_buffer_ff$ENQ, + ssNoSynth_0_aw_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_0_aw_buffer_firstValid + wire ssNoSynth_0_aw_buffer_firstValid$D_IN, + ssNoSynth_0_aw_buffer_firstValid$EN, + ssNoSynth_0_aw_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_0_w_buffer_ff + wire [72 : 0] ssNoSynth_0_w_buffer_ff$D_IN, ssNoSynth_0_w_buffer_ff$D_OUT; + wire ssNoSynth_0_w_buffer_ff$CLR, + ssNoSynth_0_w_buffer_ff$DEQ, + ssNoSynth_0_w_buffer_ff$EMPTY_N, + ssNoSynth_0_w_buffer_ff$ENQ, + ssNoSynth_0_w_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_0_w_buffer_firstValid + wire ssNoSynth_0_w_buffer_firstValid$D_IN, + ssNoSynth_0_w_buffer_firstValid$EN, + ssNoSynth_0_w_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_ar_buffer_ff + wire [97 : 0] ssNoSynth_1_ar_buffer_ff$D_IN, ssNoSynth_1_ar_buffer_ff$D_OUT; + wire ssNoSynth_1_ar_buffer_ff$CLR, + ssNoSynth_1_ar_buffer_ff$DEQ, + ssNoSynth_1_ar_buffer_ff$EMPTY_N, + ssNoSynth_1_ar_buffer_ff$ENQ, + ssNoSynth_1_ar_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_ar_buffer_firstValid + wire ssNoSynth_1_ar_buffer_firstValid$D_IN, + ssNoSynth_1_ar_buffer_firstValid$EN, + ssNoSynth_1_ar_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_aw_buffer_ff + wire [97 : 0] ssNoSynth_1_aw_buffer_ff$D_IN, ssNoSynth_1_aw_buffer_ff$D_OUT; + wire ssNoSynth_1_aw_buffer_ff$CLR, + ssNoSynth_1_aw_buffer_ff$DEQ, + ssNoSynth_1_aw_buffer_ff$EMPTY_N, + ssNoSynth_1_aw_buffer_ff$ENQ, + ssNoSynth_1_aw_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_aw_buffer_firstValid + wire ssNoSynth_1_aw_buffer_firstValid$D_IN, + ssNoSynth_1_aw_buffer_firstValid$EN, + ssNoSynth_1_aw_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_1_w_buffer_ff + wire [72 : 0] ssNoSynth_1_w_buffer_ff$D_IN, ssNoSynth_1_w_buffer_ff$D_OUT; + wire ssNoSynth_1_w_buffer_ff$CLR, + ssNoSynth_1_w_buffer_ff$DEQ, + ssNoSynth_1_w_buffer_ff$EMPTY_N, + ssNoSynth_1_w_buffer_ff$ENQ, + ssNoSynth_1_w_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_1_w_buffer_firstValid + wire ssNoSynth_1_w_buffer_firstValid$D_IN, + ssNoSynth_1_w_buffer_firstValid$EN, + ssNoSynth_1_w_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_ar_buffer_ff + wire [97 : 0] ssNoSynth_2_ar_buffer_ff$D_IN, ssNoSynth_2_ar_buffer_ff$D_OUT; + wire ssNoSynth_2_ar_buffer_ff$CLR, + ssNoSynth_2_ar_buffer_ff$DEQ, + ssNoSynth_2_ar_buffer_ff$EMPTY_N, + ssNoSynth_2_ar_buffer_ff$ENQ, + ssNoSynth_2_ar_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_ar_buffer_firstValid + wire ssNoSynth_2_ar_buffer_firstValid$D_IN, + ssNoSynth_2_ar_buffer_firstValid$EN, + ssNoSynth_2_ar_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_aw_buffer_ff + wire [97 : 0] ssNoSynth_2_aw_buffer_ff$D_IN, ssNoSynth_2_aw_buffer_ff$D_OUT; + wire ssNoSynth_2_aw_buffer_ff$CLR, + ssNoSynth_2_aw_buffer_ff$DEQ, + ssNoSynth_2_aw_buffer_ff$EMPTY_N, + ssNoSynth_2_aw_buffer_ff$ENQ, + ssNoSynth_2_aw_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_aw_buffer_firstValid + wire ssNoSynth_2_aw_buffer_firstValid$D_IN, + ssNoSynth_2_aw_buffer_firstValid$EN, + ssNoSynth_2_aw_buffer_firstValid$Q_OUT; + + // ports of submodule ssNoSynth_2_w_buffer_ff + wire [72 : 0] ssNoSynth_2_w_buffer_ff$D_IN, ssNoSynth_2_w_buffer_ff$D_OUT; + wire ssNoSynth_2_w_buffer_ff$CLR, + ssNoSynth_2_w_buffer_ff$DEQ, + ssNoSynth_2_w_buffer_ff$EMPTY_N, + ssNoSynth_2_w_buffer_ff$ENQ, + ssNoSynth_2_w_buffer_ff$FULL_N; + + // ports of submodule ssNoSynth_2_w_buffer_firstValid + wire ssNoSynth_2_w_buffer_firstValid$D_IN, + ssNoSynth_2_w_buffer_firstValid$EN, + ssNoSynth_2_w_buffer_firstValid$Q_OUT; // ports of submodule tv_encode wire [607 : 0] tv_encode$tv_vb_out_get; @@ -1473,43 +2015,232 @@ module mkCore(CLK, CAN_FIRE_RL_ClientServerResponse_2, CAN_FIRE_RL_ClientServerResponse_3, CAN_FIRE_RL_ClientServerResponse_4, + CAN_FIRE_RL_arbitrate, + CAN_FIRE_RL_arbitrate_1, + CAN_FIRE_RL_arbitrate_2, + CAN_FIRE_RL_arbitrate_3, + CAN_FIRE_RL_burst, + CAN_FIRE_RL_burst_1, + CAN_FIRE_RL_burst_2, + CAN_FIRE_RL_burst_3, + CAN_FIRE_RL_burst_4, + CAN_FIRE_RL_burst_5, + CAN_FIRE_RL_burst_6, + CAN_FIRE_RL_burst_7, + CAN_FIRE_RL_burst_8, + CAN_FIRE_RL_burst_9, + CAN_FIRE_RL_checkSinkReady, + CAN_FIRE_RL_checkSinkReady_1, + CAN_FIRE_RL_checkSinkReady_2, + CAN_FIRE_RL_checkSinkReady_3, + CAN_FIRE_RL_checkSinkReady_4, + CAN_FIRE_RL_checkSinkReady_5, + CAN_FIRE_RL_checkSinkReady_6, + CAN_FIRE_RL_checkSinkReady_7, + CAN_FIRE_RL_checkSinkReady_8, + CAN_FIRE_RL_checkSinkReady_9, + CAN_FIRE_RL_connect_arflit, + CAN_FIRE_RL_connect_arready, + CAN_FIRE_RL_connect_awflit, + CAN_FIRE_RL_connect_awready, + CAN_FIRE_RL_connect_bflit, + CAN_FIRE_RL_connect_bready, + CAN_FIRE_RL_connect_rflit, + CAN_FIRE_RL_connect_rready, + CAN_FIRE_RL_connect_wflit, + CAN_FIRE_RL_connect_wready, + CAN_FIRE_RL_craftReq, + CAN_FIRE_RL_craftReq_1, + CAN_FIRE_RL_craftReq_2, + CAN_FIRE_RL_craftReq_3, + CAN_FIRE_RL_craftReq_4, + CAN_FIRE_RL_craftReq_5, + CAN_FIRE_RL_craftReq_6, + CAN_FIRE_RL_craftReq_7, + CAN_FIRE_RL_craftReq_8, + CAN_FIRE_RL_craftReq_9, + CAN_FIRE_RL_ifcs_0_1_drainFlits, + CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_0_1_firstFlit, + CAN_FIRE_RL_ifcs_0_1_firstFlit_1, + CAN_FIRE_RL_ifcs_0_1_followFlits, + CAN_FIRE_RL_ifcs_0_1_followFlits_1, + CAN_FIRE_RL_ifcs_0_1_forwardRsp, + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit, + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_0_drainFlits, + CAN_FIRE_RL_ifcs_0_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_0_firstFlit, + CAN_FIRE_RL_ifcs_0_firstFlit_1, + CAN_FIRE_RL_ifcs_0_followFlits, + CAN_FIRE_RL_ifcs_0_followFlits_1, + CAN_FIRE_RL_ifcs_0_forwardRsp, + CAN_FIRE_RL_ifcs_0_nonRoutableFlit, + CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_1_drainFlits, + CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_1_1_firstFlit, + CAN_FIRE_RL_ifcs_1_1_firstFlit_1, + CAN_FIRE_RL_ifcs_1_1_followFlits, + CAN_FIRE_RL_ifcs_1_1_followFlits_1, + CAN_FIRE_RL_ifcs_1_1_forwardRsp, + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit, + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_1_drainFlits, + CAN_FIRE_RL_ifcs_1_drainNoRouteResponse, + CAN_FIRE_RL_ifcs_1_firstFlit, + CAN_FIRE_RL_ifcs_1_firstFlit_1, + CAN_FIRE_RL_ifcs_1_followFlits, + CAN_FIRE_RL_ifcs_1_followFlits_1, + CAN_FIRE_RL_ifcs_1_forwardRsp, + CAN_FIRE_RL_ifcs_1_nonRoutableFlit, + CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp, + CAN_FIRE_RL_ifcs_2_1_firstFlit, + CAN_FIRE_RL_ifcs_2_1_followFlits, + CAN_FIRE_RL_ifcs_2_firstFlit, + CAN_FIRE_RL_ifcs_2_followFlits, CAN_FIRE_RL_merge_cpu_trace_data, CAN_FIRE_RL_merge_dm_csr_trace_data, CAN_FIRE_RL_merge_dm_gpr_trace_data, CAN_FIRE_RL_merge_dm_mem_trace_data, + CAN_FIRE_RL_merged_0_genFirst, + CAN_FIRE_RL_merged_0_genOther, + CAN_FIRE_RL_merged_1_genFirst, + CAN_FIRE_RL_merged_1_genOther, CAN_FIRE_RL_mkConnectionGetPut, CAN_FIRE_RL_mkConnectionGetPut_1, + CAN_FIRE_RL_msNoSynth_0_ar_forwardReady, + CAN_FIRE_RL_msNoSynth_0_aw_forwardReady, + CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_b_dropFlit, + CAN_FIRE_RL_msNoSynth_0_b_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_0_r_dropFlit, + CAN_FIRE_RL_msNoSynth_0_r_forwardFlit, + CAN_FIRE_RL_msNoSynth_0_w_forwardReady, + CAN_FIRE_RL_msNoSynth_1_ar_forwardReady, + CAN_FIRE_RL_msNoSynth_1_aw_forwardReady, + CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_b_dropFlit, + CAN_FIRE_RL_msNoSynth_1_b_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue, + CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue, + CAN_FIRE_RL_msNoSynth_1_r_dropFlit, + CAN_FIRE_RL_msNoSynth_1_r_forwardFlit, + CAN_FIRE_RL_msNoSynth_1_w_forwardReady, CAN_FIRE_RL_rl_cpu_hart0_reset_complete, CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - CAN_FIRE_RL_rl_rd_addr_channel, - CAN_FIRE_RL_rl_rd_addr_channel_1, - CAN_FIRE_RL_rl_rd_addr_channel_2, - CAN_FIRE_RL_rl_rd_addr_channel_3, - CAN_FIRE_RL_rl_rd_addr_channel_4, - CAN_FIRE_RL_rl_rd_data_channel, - CAN_FIRE_RL_rl_rd_data_channel_1, - CAN_FIRE_RL_rl_rd_data_channel_2, - CAN_FIRE_RL_rl_rd_data_channel_3, - CAN_FIRE_RL_rl_rd_data_channel_4, CAN_FIRE_RL_rl_relay_external_interrupts, CAN_FIRE_RL_rl_relay_sw_interrupts, CAN_FIRE_RL_rl_relay_timer_interrupts, - CAN_FIRE_RL_rl_wr_addr_channel, - CAN_FIRE_RL_rl_wr_addr_channel_1, - CAN_FIRE_RL_rl_wr_addr_channel_2, - CAN_FIRE_RL_rl_wr_addr_channel_3, - CAN_FIRE_RL_rl_wr_addr_channel_4, - CAN_FIRE_RL_rl_wr_data_channel, - CAN_FIRE_RL_rl_wr_data_channel_1, - CAN_FIRE_RL_rl_wr_data_channel_2, - CAN_FIRE_RL_rl_wr_data_channel_3, - CAN_FIRE_RL_rl_wr_data_channel_4, - CAN_FIRE_RL_rl_wr_response_channel, - CAN_FIRE_RL_rl_wr_response_channel_1, - CAN_FIRE_RL_rl_wr_response_channel_2, - CAN_FIRE_RL_rl_wr_response_channel_3, - CAN_FIRE_RL_rl_wr_response_channel_4, + CAN_FIRE_RL_sink_selected, + CAN_FIRE_RL_sink_selected_1, + CAN_FIRE_RL_sink_selected_2, + CAN_FIRE_RL_sink_selected_3, + CAN_FIRE_RL_sink_selected_4, + CAN_FIRE_RL_sink_selected_5, + CAN_FIRE_RL_sink_selected_6, + CAN_FIRE_RL_sink_selected_7, + CAN_FIRE_RL_sink_selected_8, + CAN_FIRE_RL_sink_selected_9, + CAN_FIRE_RL_source_selected, + CAN_FIRE_RL_source_selected_1, + CAN_FIRE_RL_source_selected_2, + CAN_FIRE_RL_source_selected_3, + CAN_FIRE_RL_source_selected_4, + CAN_FIRE_RL_source_selected_5, + CAN_FIRE_RL_source_selected_6, + CAN_FIRE_RL_source_selected_7, + CAN_FIRE_RL_source_selected_8, + CAN_FIRE_RL_source_selected_9, + CAN_FIRE_RL_split_0_putFirst, + CAN_FIRE_RL_split_0_putOther, + CAN_FIRE_RL_split_1_putFirst, + CAN_FIRE_RL_split_1_putOther, + CAN_FIRE_RL_split_2_putFirst, + CAN_FIRE_RL_split_2_putOther, + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit, + CAN_FIRE_RL_ssNoSynth_0_b_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_r_forwardReady, + CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_0_w_dropFlit, + CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit, + CAN_FIRE_RL_ssNoSynth_1_b_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_r_forwardReady, + CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit, + CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit, + CAN_FIRE_RL_ssNoSynth_2_b_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_r_forwardReady, + CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, + CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit, + CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit, + CAN_FIRE___me_check_103, + CAN_FIRE___me_check_104, + CAN_FIRE___me_check_105, + CAN_FIRE___me_check_107, + CAN_FIRE___me_check_110, + CAN_FIRE___me_check_111, + CAN_FIRE___me_check_112, + CAN_FIRE___me_check_114, + CAN_FIRE___me_check_117, + CAN_FIRE___me_check_119, + CAN_FIRE___me_check_121, + CAN_FIRE___me_check_129, + CAN_FIRE___me_check_131, + CAN_FIRE___me_check_133, + CAN_FIRE___me_check_142, + CAN_FIRE___me_check_144, + CAN_FIRE___me_check_146, + CAN_FIRE___me_check_148, + CAN_FIRE___me_check_150, + CAN_FIRE___me_check_151, + CAN_FIRE___me_check_152, + CAN_FIRE___me_check_154, + CAN_FIRE___me_check_157, + CAN_FIRE___me_check_158, + CAN_FIRE___me_check_159, + CAN_FIRE___me_check_161, + CAN_FIRE___me_check_164, + CAN_FIRE___me_check_166, + CAN_FIRE___me_check_168, + CAN_FIRE___me_check_176, + CAN_FIRE___me_check_178, + CAN_FIRE___me_check_180, + CAN_FIRE___me_check_189, + CAN_FIRE___me_check_191, + CAN_FIRE___me_check_193, + CAN_FIRE___me_check_195, CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -1526,16 +2257,16 @@ module mkCore(CLK, CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req, CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - CAN_FIRE_cpu_dmem_master_m_arready, - CAN_FIRE_cpu_dmem_master_m_awready, - CAN_FIRE_cpu_dmem_master_m_bvalid, - CAN_FIRE_cpu_dmem_master_m_rvalid, - CAN_FIRE_cpu_dmem_master_m_wready, - CAN_FIRE_cpu_imem_master_m_arready, - CAN_FIRE_cpu_imem_master_m_awready, - CAN_FIRE_cpu_imem_master_m_bvalid, - CAN_FIRE_cpu_imem_master_m_rvalid, - CAN_FIRE_cpu_imem_master_m_wready, + CAN_FIRE_cpu_dmem_master_ar_arready, + CAN_FIRE_cpu_dmem_master_aw_awready, + CAN_FIRE_cpu_dmem_master_b_bflit, + CAN_FIRE_cpu_dmem_master_r_rflit, + CAN_FIRE_cpu_dmem_master_w_wready, + CAN_FIRE_cpu_imem_master_ar_arready, + CAN_FIRE_cpu_imem_master_aw_awready, + CAN_FIRE_cpu_imem_master_b_bflit, + CAN_FIRE_cpu_imem_master_r_rflit, + CAN_FIRE_cpu_imem_master_w_wready, CAN_FIRE_cpu_reset_server_request_put, CAN_FIRE_cpu_reset_server_response_get, CAN_FIRE_dm_dmi_read_addr, @@ -1556,43 +2287,232 @@ module mkCore(CLK, WILL_FIRE_RL_ClientServerResponse_2, WILL_FIRE_RL_ClientServerResponse_3, WILL_FIRE_RL_ClientServerResponse_4, + WILL_FIRE_RL_arbitrate, + WILL_FIRE_RL_arbitrate_1, + WILL_FIRE_RL_arbitrate_2, + WILL_FIRE_RL_arbitrate_3, + WILL_FIRE_RL_burst, + WILL_FIRE_RL_burst_1, + WILL_FIRE_RL_burst_2, + WILL_FIRE_RL_burst_3, + WILL_FIRE_RL_burst_4, + WILL_FIRE_RL_burst_5, + WILL_FIRE_RL_burst_6, + WILL_FIRE_RL_burst_7, + WILL_FIRE_RL_burst_8, + WILL_FIRE_RL_burst_9, + WILL_FIRE_RL_checkSinkReady, + WILL_FIRE_RL_checkSinkReady_1, + WILL_FIRE_RL_checkSinkReady_2, + WILL_FIRE_RL_checkSinkReady_3, + WILL_FIRE_RL_checkSinkReady_4, + WILL_FIRE_RL_checkSinkReady_5, + WILL_FIRE_RL_checkSinkReady_6, + WILL_FIRE_RL_checkSinkReady_7, + WILL_FIRE_RL_checkSinkReady_8, + WILL_FIRE_RL_checkSinkReady_9, + WILL_FIRE_RL_connect_arflit, + WILL_FIRE_RL_connect_arready, + WILL_FIRE_RL_connect_awflit, + WILL_FIRE_RL_connect_awready, + WILL_FIRE_RL_connect_bflit, + WILL_FIRE_RL_connect_bready, + WILL_FIRE_RL_connect_rflit, + WILL_FIRE_RL_connect_rready, + WILL_FIRE_RL_connect_wflit, + WILL_FIRE_RL_connect_wready, + WILL_FIRE_RL_craftReq, + WILL_FIRE_RL_craftReq_1, + WILL_FIRE_RL_craftReq_2, + WILL_FIRE_RL_craftReq_3, + WILL_FIRE_RL_craftReq_4, + WILL_FIRE_RL_craftReq_5, + WILL_FIRE_RL_craftReq_6, + WILL_FIRE_RL_craftReq_7, + WILL_FIRE_RL_craftReq_8, + WILL_FIRE_RL_craftReq_9, + WILL_FIRE_RL_ifcs_0_1_drainFlits, + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_0_1_firstFlit, + WILL_FIRE_RL_ifcs_0_1_firstFlit_1, + WILL_FIRE_RL_ifcs_0_1_followFlits, + WILL_FIRE_RL_ifcs_0_1_followFlits_1, + WILL_FIRE_RL_ifcs_0_1_forwardRsp, + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit, + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_0_drainFlits, + WILL_FIRE_RL_ifcs_0_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_0_firstFlit, + WILL_FIRE_RL_ifcs_0_firstFlit_1, + WILL_FIRE_RL_ifcs_0_followFlits, + WILL_FIRE_RL_ifcs_0_followFlits_1, + WILL_FIRE_RL_ifcs_0_forwardRsp, + WILL_FIRE_RL_ifcs_0_nonRoutableFlit, + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_1_drainFlits, + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_1_1_firstFlit, + WILL_FIRE_RL_ifcs_1_1_firstFlit_1, + WILL_FIRE_RL_ifcs_1_1_followFlits, + WILL_FIRE_RL_ifcs_1_1_followFlits_1, + WILL_FIRE_RL_ifcs_1_1_forwardRsp, + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit, + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_1_drainFlits, + WILL_FIRE_RL_ifcs_1_drainNoRouteResponse, + WILL_FIRE_RL_ifcs_1_firstFlit, + WILL_FIRE_RL_ifcs_1_firstFlit_1, + WILL_FIRE_RL_ifcs_1_followFlits, + WILL_FIRE_RL_ifcs_1_followFlits_1, + WILL_FIRE_RL_ifcs_1_forwardRsp, + WILL_FIRE_RL_ifcs_1_nonRoutableFlit, + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp, + WILL_FIRE_RL_ifcs_2_1_firstFlit, + WILL_FIRE_RL_ifcs_2_1_followFlits, + WILL_FIRE_RL_ifcs_2_firstFlit, + WILL_FIRE_RL_ifcs_2_followFlits, WILL_FIRE_RL_merge_cpu_trace_data, WILL_FIRE_RL_merge_dm_csr_trace_data, WILL_FIRE_RL_merge_dm_gpr_trace_data, WILL_FIRE_RL_merge_dm_mem_trace_data, + WILL_FIRE_RL_merged_0_genFirst, + WILL_FIRE_RL_merged_0_genOther, + WILL_FIRE_RL_merged_1_genFirst, + WILL_FIRE_RL_merged_1_genOther, WILL_FIRE_RL_mkConnectionGetPut, WILL_FIRE_RL_mkConnectionGetPut_1, + WILL_FIRE_RL_msNoSynth_0_ar_forwardReady, + WILL_FIRE_RL_msNoSynth_0_aw_forwardReady, + WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_b_dropFlit, + WILL_FIRE_RL_msNoSynth_0_b_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_0_r_dropFlit, + WILL_FIRE_RL_msNoSynth_0_r_forwardFlit, + WILL_FIRE_RL_msNoSynth_0_w_forwardReady, + WILL_FIRE_RL_msNoSynth_1_ar_forwardReady, + WILL_FIRE_RL_msNoSynth_1_aw_forwardReady, + WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_b_dropFlit, + WILL_FIRE_RL_msNoSynth_1_b_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue, + WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue, + WILL_FIRE_RL_msNoSynth_1_r_dropFlit, + WILL_FIRE_RL_msNoSynth_1_r_forwardFlit, + WILL_FIRE_RL_msNoSynth_1_w_forwardReady, WILL_FIRE_RL_rl_cpu_hart0_reset_complete, WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start, WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start, - WILL_FIRE_RL_rl_rd_addr_channel, - WILL_FIRE_RL_rl_rd_addr_channel_1, - WILL_FIRE_RL_rl_rd_addr_channel_2, - WILL_FIRE_RL_rl_rd_addr_channel_3, - WILL_FIRE_RL_rl_rd_addr_channel_4, - WILL_FIRE_RL_rl_rd_data_channel, - WILL_FIRE_RL_rl_rd_data_channel_1, - WILL_FIRE_RL_rl_rd_data_channel_2, - WILL_FIRE_RL_rl_rd_data_channel_3, - WILL_FIRE_RL_rl_rd_data_channel_4, WILL_FIRE_RL_rl_relay_external_interrupts, WILL_FIRE_RL_rl_relay_sw_interrupts, WILL_FIRE_RL_rl_relay_timer_interrupts, - WILL_FIRE_RL_rl_wr_addr_channel, - WILL_FIRE_RL_rl_wr_addr_channel_1, - WILL_FIRE_RL_rl_wr_addr_channel_2, - WILL_FIRE_RL_rl_wr_addr_channel_3, - WILL_FIRE_RL_rl_wr_addr_channel_4, - WILL_FIRE_RL_rl_wr_data_channel, - WILL_FIRE_RL_rl_wr_data_channel_1, - WILL_FIRE_RL_rl_wr_data_channel_2, - WILL_FIRE_RL_rl_wr_data_channel_3, - WILL_FIRE_RL_rl_wr_data_channel_4, - WILL_FIRE_RL_rl_wr_response_channel, - WILL_FIRE_RL_rl_wr_response_channel_1, - WILL_FIRE_RL_rl_wr_response_channel_2, - WILL_FIRE_RL_rl_wr_response_channel_3, - WILL_FIRE_RL_rl_wr_response_channel_4, + WILL_FIRE_RL_sink_selected, + WILL_FIRE_RL_sink_selected_1, + WILL_FIRE_RL_sink_selected_2, + WILL_FIRE_RL_sink_selected_3, + WILL_FIRE_RL_sink_selected_4, + WILL_FIRE_RL_sink_selected_5, + WILL_FIRE_RL_sink_selected_6, + WILL_FIRE_RL_sink_selected_7, + WILL_FIRE_RL_sink_selected_8, + WILL_FIRE_RL_sink_selected_9, + WILL_FIRE_RL_source_selected, + WILL_FIRE_RL_source_selected_1, + WILL_FIRE_RL_source_selected_2, + WILL_FIRE_RL_source_selected_3, + WILL_FIRE_RL_source_selected_4, + WILL_FIRE_RL_source_selected_5, + WILL_FIRE_RL_source_selected_6, + WILL_FIRE_RL_source_selected_7, + WILL_FIRE_RL_source_selected_8, + WILL_FIRE_RL_source_selected_9, + WILL_FIRE_RL_split_0_putFirst, + WILL_FIRE_RL_split_0_putOther, + WILL_FIRE_RL_split_1_putFirst, + WILL_FIRE_RL_split_1_putOther, + WILL_FIRE_RL_split_2_putFirst, + WILL_FIRE_RL_split_2_putOther, + WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit, + WILL_FIRE_RL_ssNoSynth_0_b_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_r_forwardReady, + WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_0_w_dropFlit, + WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit, + WILL_FIRE_RL_ssNoSynth_1_b_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_r_forwardReady, + WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_1_w_dropFlit, + WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit, + WILL_FIRE_RL_ssNoSynth_2_b_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_r_forwardReady, + WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue, + WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue, + WILL_FIRE_RL_ssNoSynth_2_w_dropFlit, + WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit, + WILL_FIRE___me_check_103, + WILL_FIRE___me_check_104, + WILL_FIRE___me_check_105, + WILL_FIRE___me_check_107, + WILL_FIRE___me_check_110, + WILL_FIRE___me_check_111, + WILL_FIRE___me_check_112, + WILL_FIRE___me_check_114, + WILL_FIRE___me_check_117, + WILL_FIRE___me_check_119, + WILL_FIRE___me_check_121, + WILL_FIRE___me_check_129, + WILL_FIRE___me_check_131, + WILL_FIRE___me_check_133, + WILL_FIRE___me_check_142, + WILL_FIRE___me_check_144, + WILL_FIRE___me_check_146, + WILL_FIRE___me_check_148, + WILL_FIRE___me_check_150, + WILL_FIRE___me_check_151, + WILL_FIRE___me_check_152, + WILL_FIRE___me_check_154, + WILL_FIRE___me_check_157, + WILL_FIRE___me_check_158, + WILL_FIRE___me_check_159, + WILL_FIRE___me_check_161, + WILL_FIRE___me_check_164, + WILL_FIRE___me_check_166, + WILL_FIRE___me_check_168, + WILL_FIRE___me_check_176, + WILL_FIRE___me_check_178, + WILL_FIRE___me_check_180, + WILL_FIRE___me_check_189, + WILL_FIRE___me_check_191, + WILL_FIRE___me_check_193, + WILL_FIRE___me_check_195, WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req, @@ -1609,16 +2529,16 @@ module mkCore(CLK, WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req, WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req, - WILL_FIRE_cpu_dmem_master_m_arready, - WILL_FIRE_cpu_dmem_master_m_awready, - WILL_FIRE_cpu_dmem_master_m_bvalid, - WILL_FIRE_cpu_dmem_master_m_rvalid, - WILL_FIRE_cpu_dmem_master_m_wready, - WILL_FIRE_cpu_imem_master_m_arready, - WILL_FIRE_cpu_imem_master_m_awready, - WILL_FIRE_cpu_imem_master_m_bvalid, - WILL_FIRE_cpu_imem_master_m_rvalid, - WILL_FIRE_cpu_imem_master_m_wready, + WILL_FIRE_cpu_dmem_master_ar_arready, + WILL_FIRE_cpu_dmem_master_aw_awready, + WILL_FIRE_cpu_dmem_master_b_bflit, + WILL_FIRE_cpu_dmem_master_r_rflit, + WILL_FIRE_cpu_dmem_master_w_wready, + WILL_FIRE_cpu_imem_master_ar_arready, + WILL_FIRE_cpu_imem_master_aw_awready, + WILL_FIRE_cpu_imem_master_b_bflit, + WILL_FIRE_cpu_imem_master_r_rflit, + WILL_FIRE_cpu_imem_master_w_wready, WILL_FIRE_cpu_reset_server_request_put, WILL_FIRE_cpu_reset_server_response_get, WILL_FIRE_dm_dmi_read_addr, @@ -1630,18 +2550,292 @@ module mkCore(CLK, WILL_FIRE_set_verbosity, WILL_FIRE_tv_verifier_info_get_get; + // inputs to muxes for submodule ports + reg [70 : 0] MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1, + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1; + reg [5 : 0] MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1, + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1; + wire [7 : 0] MUX_merged_0_flitLeft$write_1__VAL_1, + MUX_merged_1_flitLeft$write_1__VAL_1, + MUX_split_0_flitLeft$write_1__VAL_1, + MUX_split_1_flitLeft$write_1__VAL_1, + MUX_split_2_flitLeft$write_1__VAL_1; + wire MUX_activeSource_0$write_1__SEL_1, + MUX_activeSource_0$write_1__VAL_1, + MUX_activeSource_1$write_1__VAL_1, + MUX_activeSource_1_1_0$write_1__SEL_1, + MUX_activeSource_1_1_0$write_1__SEL_2, + MUX_activeSource_1_1_0$write_1__SEL_3, + MUX_activeSource_1_1_0$write_1__VAL_1, + MUX_activeSource_1_1_1_1$write_1__VAL_1, + MUX_activeSource_1_1_2$write_1__VAL_1, + MUX_flitToSink_0$wset_1__SEL_1, + MUX_flitToSink_0$wset_1__SEL_3, + MUX_flitToSink_1$wset_1__SEL_1, + MUX_flitToSink_1$wset_1__SEL_3, + MUX_flitToSink_1_0$wset_1__SEL_1, + MUX_flitToSink_1_0$wset_1__SEL_2, + MUX_flitToSink_1_0$wset_1__SEL_3, + MUX_flitToSink_1_0$wset_1__SEL_4, + MUX_flitToSink_1_0$wset_1__SEL_5, + MUX_flitToSink_1_0$wset_1__SEL_6, + MUX_flitToSink_1_0_1$wset_1__SEL_1, + MUX_flitToSink_1_0_1$wset_1__SEL_3, + MUX_flitToSink_1_1$wset_1__SEL_1, + MUX_flitToSink_1_1$wset_1__SEL_2, + MUX_flitToSink_1_1$wset_1__SEL_3, + MUX_flitToSink_1_1$wset_1__SEL_4, + MUX_flitToSink_1_1$wset_1__SEL_5, + MUX_flitToSink_1_1$wset_1__SEL_6, + MUX_flitToSink_1_1_0$wset_1__SEL_1, + MUX_flitToSink_1_1_0$wset_1__SEL_2, + MUX_flitToSink_1_1_0$wset_1__SEL_3, + MUX_flitToSink_1_1_0$wset_1__SEL_4, + MUX_flitToSink_1_1_0$wset_1__SEL_5, + MUX_flitToSink_1_1_0$wset_1__SEL_6, + MUX_flitToSink_1_1_1$wset_1__SEL_1, + MUX_flitToSink_1_1_1$wset_1__SEL_3, + MUX_flitToSink_1_1_1_1$wset_1__SEL_1, + MUX_flitToSink_1_1_1_1$wset_1__SEL_2, + MUX_flitToSink_1_1_1_1$wset_1__SEL_3, + MUX_flitToSink_1_1_1_1$wset_1__SEL_4, + MUX_flitToSink_1_1_1_1$wset_1__SEL_5, + MUX_flitToSink_1_1_1_1$wset_1__SEL_6, + MUX_flitToSink_1_2$wset_1__SEL_1, + MUX_flitToSink_1_2$wset_1__SEL_3, + MUX_flitToSink_2$wset_1__SEL_1, + MUX_flitToSink_2$wset_1__SEL_3, + MUX_ifcs_0_1_state_1$write_1__SEL_1, + MUX_ifcs_0_state$write_1__PSEL_1, + MUX_ifcs_0_state$write_1__SEL_1, + MUX_ifcs_0_state$write_1__SEL_2, + MUX_ifcs_0_state$write_1__SEL_3, + MUX_ifcs_1_1_state_1$write_1__SEL_1, + MUX_ifcs_1_state$write_1__PSEL_1, + MUX_ifcs_1_state$write_1__SEL_1, + MUX_ifcs_1_state$write_1__SEL_2, + MUX_ifcs_1_state$write_1__SEL_3, + MUX_ifcs_2_1_state$write_1__SEL_1, + MUX_split_0_flitLeft$write_1__SEL_1, + MUX_split_0_flitLeft$write_1__SEL_2, + MUX_split_1_flitLeft$write_1__SEL_1, + MUX_split_1_flitLeft$write_1__SEL_2, + MUX_split_2_flitLeft$write_1__SEL_1, + MUX_split_2_flitLeft$write_1__SEL_2, + MUX_state$write_1__SEL_1, + MUX_state$write_1__SEL_2, + MUX_state_1_1_1$write_1__SEL_1, + MUX_state_1_1_1$write_1__SEL_2, + MUX_state_1_1_1$write_1__SEL_3; + // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h5074; - reg [31 : 0] v__h5275; - reg [31 : 0] v__h5643; - reg [31 : 0] v__h5068; - reg [31 : 0] v__h5269; - reg [31 : 0] v__h5637; + reg [63 : 0] v__h33674; + reg [63 : 0] v__h33063; + reg [63 : 0] v__h37683; + reg [63 : 0] v__h37072; + reg [63 : 0] v__h67508; + reg [63 : 0] v__h66897; + reg [63 : 0] v__h70401; + reg [63 : 0] v__h69790; + reg [63 : 0] v__h48378; + reg [63 : 0] v__h47997; + reg [63 : 0] v__h50448; + reg [63 : 0] v__h50067; + reg [63 : 0] v__h52347; + reg [63 : 0] v__h51966; + reg [63 : 0] v__h22294; + reg [63 : 0] v__h25002; + reg [63 : 0] v__h79681; + reg [63 : 0] v__h79300; + reg [63 : 0] v__h82172; + reg [63 : 0] v__h81791; + reg [63 : 0] v__h84482; + reg [63 : 0] v__h84101; + reg [63 : 0] v__h56310; + reg [31 : 0] v__h3443; + reg [31 : 0] v__h3620; + reg [31 : 0] v__h3986; + reg [63 : 0] v__h58726; + reg [31 : 0] v__h3437; + reg [31 : 0] v__h3614; + reg [31 : 0] v__h3980; // synopsys translate_on // remaining internal signals - wire fabric_2x3_RDY_reset_AND_cpu_RDY_hart0_server__ETC___d9; + wire [63 : 0] y__h20569, y__h20593; + wire [8 : 0] x_port1__read__h55959, x_port1__read__h58381; + wire [4 : 0] a_awid__h21643, + a_awid__h24357, + fatReq_arid__h55399, + fatReq_arid__h57824; + wire [1 : 0] IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d779, + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d783, + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d787, + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d876, + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d880, + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d884, + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1420, + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1424, + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1428, + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1506, + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1510, + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1514, + SEXT_SEXT_arbiter_1_1_firstHot_877_878_BIT_0_8_ETC__q18, + SEXT_SEXT_arbiter_1_firstHot_1_692_693_BIT_0_6_ETC__q13, + SEXT_SEXT_arbiter_1_firstHot_249_250_BIT_0_251_ETC__q8, + SEXT_SEXT_arbiter_firstHot_054_055_BIT_0_056_A_ETC__q3, + SEXT_arbiter_1_1_firstHot__q15, + SEXT_arbiter_1_1_lastSelect_1__q17, + SEXT_arbiter_1_1_lastSelect__q16, + SEXT_arbiter_1_firstHot_1__q11, + SEXT_arbiter_1_firstHot__q5, + SEXT_arbiter_1_lastSelect_1__q7, + SEXT_arbiter_1_lastSelect_2__q12, + SEXT_arbiter_1_lastSelect__q6, + SEXT_arbiter_firstHot__q1, + SEXT_arbiter_lastSelect__q2, + SEXT_x2193__q4, + SEXT_x6033__q14, + SEXT_x6679__q9, + SEXT_x6713__q10, + SEXT_x7978__q19, + SEXT_x8012__q20; + wire IF_NOT_ifcs_0_1_innerRoute_first__638_BIT_1_64_ETC___d1660, + IF_NOT_ifcs_0_innerRoute_first__000_BIT_1_009__ETC___d1022, + IF_NOT_ifcs_1_1_innerRoute_first__667_BIT_1_67_ETC___d1676, + IF_NOT_ifcs_1_innerRoute_first__029_BIT_1_033__ETC___d1038, + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1912, + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1918, + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1924, + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1284, + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1290, + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1296, + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1712, + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1716, + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1074, + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1078, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d760, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d821, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774, + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d857, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d918, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871, + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872, + IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992, + IF_split_1_flitLeft_03_EQ_0_04_THEN_ssNoSynth__ETC___d993, + IF_split_2_flitLeft_32_EQ_0_33_THEN_ssNoSynth__ETC___d994, + SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893, + SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887, + SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881, + SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700, + SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265, + SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259, + SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253, + SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696, + SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062, + SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058, + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411, + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412, + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415, + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416, + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497, + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498, + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501, + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502, + plic_RDY_server_reset_request_put_AND_cpu_RDY__ETC___d8, + reqWires_1_0_whas__226_AND_reqWires_1_0_wget___ETC___d1236, + reqWires_1_1_0_whas__854_AND_reqWires_1_1_0_wg_ETC___d1864, + split_0_doPut_whas__66_AND_split_0_doPut_wget__ETC___d673, + split_1_doPut_whas__95_AND_split_1_doPut_wget__ETC___d702, + split_2_doPut_whas__24_AND_split_2_doPut_wget__ETC___d731, + state_047_AND_activeSource_0_120_121_AND_ifcs__ETC___d1123, + state_047_AND_activeSource_1_164_165_AND_ifcs__ETC___d1167, + state_1_1_1_865_AND_activeSource_1_1_0_959_960_ETC___d1962, + state_1_1_1_865_AND_activeSource_1_1_1_1_995_9_ETC___d1998, + state_1_1_1_865_AND_activeSource_1_1_2_031_032_ETC___d2034, + state_1_1_685_AND_activeSource_1_0_1_752_753_A_ETC___d1755, + state_1_1_685_AND_activeSource_1_1_1_792_793_A_ETC___d1795, + state_1_237_AND_activeSource_1_0_325_326_AND_i_ETC___d1328, + state_1_237_AND_activeSource_1_1_358_359_AND_i_ETC___d1361, + state_1_237_AND_activeSource_1_2_392_393_AND_i_ETC___d1395, + x__h31666, + x__h31769, + x__h32134, + x__h32193, + x__h32275, + x__h45858, + x__h45860, + x__h46009, + x__h46011, + x__h46145, + x__h46147, + x__h46617, + x__h46619, + x__h46679, + x__h46713, + x__h46805, + x__h46807, + x__h46986, + x__h46988, + x__h65506, + x__h65609, + x__h65974, + x__h66033, + x__h66115, + x__h77157, + x__h77159, + x__h77308, + x__h77310, + x__h77444, + x__h77446, + x__h77916, + x__h77918, + x__h77978, + x__h78012, + x__h78104, + x__h78106, + x__h78285, + x__h78287, + y__h31667, + y__h31770, + y__h32135, + y__h32276, + y__h45859, + y__h45861, + y__h46010, + y__h46012, + y__h46146, + y__h46148, + y__h46618, + y__h46620, + y__h46806, + y__h46808, + y__h46987, + y__h46989, + y__h65507, + y__h65610, + y__h65975, + y__h66116, + y__h77158, + y__h77160, + y__h77309, + y__h77311, + y__h77445, + y__h77447, + y__h77917, + y__h77919, + y__h78105, + y__h78107, + y__h78286, + y__h78288; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; @@ -1661,213 +2855,213 @@ module mkCore(CLK, assign WILL_FIRE_cpu_reset_server_response_get = EN_cpu_reset_server_response_get ; - // value method cpu_imem_master_m_awvalid - assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - - // value method cpu_imem_master_m_awid + // value method cpu_imem_master_aw_awid assign cpu_imem_master_awid = cpu$imem_master_awid ; - // value method cpu_imem_master_m_awaddr + // value method cpu_imem_master_aw_awaddr assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ; - // value method cpu_imem_master_m_awlen + // value method cpu_imem_master_aw_awlen assign cpu_imem_master_awlen = cpu$imem_master_awlen ; - // value method cpu_imem_master_m_awsize + // value method cpu_imem_master_aw_awsize assign cpu_imem_master_awsize = cpu$imem_master_awsize ; - // value method cpu_imem_master_m_awburst + // value method cpu_imem_master_aw_awburst assign cpu_imem_master_awburst = cpu$imem_master_awburst ; - // value method cpu_imem_master_m_awlock + // value method cpu_imem_master_aw_awlock assign cpu_imem_master_awlock = cpu$imem_master_awlock ; - // value method cpu_imem_master_m_awcache + // value method cpu_imem_master_aw_awcache assign cpu_imem_master_awcache = cpu$imem_master_awcache ; - // value method cpu_imem_master_m_awprot + // value method cpu_imem_master_aw_awprot assign cpu_imem_master_awprot = cpu$imem_master_awprot ; - // value method cpu_imem_master_m_awqos + // value method cpu_imem_master_aw_awqos assign cpu_imem_master_awqos = cpu$imem_master_awqos ; - // value method cpu_imem_master_m_awregion + // value method cpu_imem_master_aw_awregion assign cpu_imem_master_awregion = cpu$imem_master_awregion ; - // action method cpu_imem_master_m_awready - assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ; + // value method cpu_imem_master_aw_awvalid + assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ; - // value method cpu_imem_master_m_wvalid - assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; + // action method cpu_imem_master_aw_awready + assign CAN_FIRE_cpu_imem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_aw_awready = 1'd1 ; - // value method cpu_imem_master_m_wdata + // value method cpu_imem_master_w_wdata assign cpu_imem_master_wdata = cpu$imem_master_wdata ; - // value method cpu_imem_master_m_wstrb + // value method cpu_imem_master_w_wstrb assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ; - // value method cpu_imem_master_m_wlast + // value method cpu_imem_master_w_wlast assign cpu_imem_master_wlast = cpu$imem_master_wlast ; - // action method cpu_imem_master_m_wready - assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ; + // value method cpu_imem_master_w_wvalid + assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ; - // action method cpu_imem_master_m_bvalid - assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ; + // action method cpu_imem_master_w_wready + assign CAN_FIRE_cpu_imem_master_w_wready = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_w_wready = 1'd1 ; - // value method cpu_imem_master_m_bready - assign cpu_imem_master_bready = cpu$imem_master_bready ; + // action method cpu_imem_master_b_bflit + assign CAN_FIRE_cpu_imem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_b_bflit = cpu_imem_master_bvalid ; - // value method cpu_imem_master_m_arvalid - assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; + // value method cpu_imem_master_b_bready + assign cpu_imem_master_bready = cpu$imem_master_bready ; - // value method cpu_imem_master_m_arid + // value method cpu_imem_master_ar_arid assign cpu_imem_master_arid = cpu$imem_master_arid ; - // value method cpu_imem_master_m_araddr + // value method cpu_imem_master_ar_araddr assign cpu_imem_master_araddr = cpu$imem_master_araddr ; - // value method cpu_imem_master_m_arlen + // value method cpu_imem_master_ar_arlen assign cpu_imem_master_arlen = cpu$imem_master_arlen ; - // value method cpu_imem_master_m_arsize + // value method cpu_imem_master_ar_arsize assign cpu_imem_master_arsize = cpu$imem_master_arsize ; - // value method cpu_imem_master_m_arburst + // value method cpu_imem_master_ar_arburst assign cpu_imem_master_arburst = cpu$imem_master_arburst ; - // value method cpu_imem_master_m_arlock + // value method cpu_imem_master_ar_arlock assign cpu_imem_master_arlock = cpu$imem_master_arlock ; - // value method cpu_imem_master_m_arcache + // value method cpu_imem_master_ar_arcache assign cpu_imem_master_arcache = cpu$imem_master_arcache ; - // value method cpu_imem_master_m_arprot + // value method cpu_imem_master_ar_arprot assign cpu_imem_master_arprot = cpu$imem_master_arprot ; - // value method cpu_imem_master_m_arqos + // value method cpu_imem_master_ar_arqos assign cpu_imem_master_arqos = cpu$imem_master_arqos ; - // value method cpu_imem_master_m_arregion + // value method cpu_imem_master_ar_arregion assign cpu_imem_master_arregion = cpu$imem_master_arregion ; - // action method cpu_imem_master_m_arready - assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ; + // value method cpu_imem_master_ar_arvalid + assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ; + + // action method cpu_imem_master_ar_arready + assign CAN_FIRE_cpu_imem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_ar_arready = 1'd1 ; - // action method cpu_imem_master_m_rvalid - assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ; + // action method cpu_imem_master_r_rflit + assign CAN_FIRE_cpu_imem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_cpu_imem_master_r_rflit = cpu_imem_master_rvalid ; - // value method cpu_imem_master_m_rready + // value method cpu_imem_master_r_rready assign cpu_imem_master_rready = cpu$imem_master_rready ; - // value method cpu_dmem_master_m_awvalid - assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ; + // value method cpu_dmem_master_aw_awid + assign cpu_dmem_master_awid = shim_awff$D_OUT[97:93] ; - // value method cpu_dmem_master_m_awid - assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ; + // value method cpu_dmem_master_aw_awaddr + assign cpu_dmem_master_awaddr = shim_awff$D_OUT[92:29] ; - // value method cpu_dmem_master_m_awaddr - assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ; + // value method cpu_dmem_master_aw_awlen + assign cpu_dmem_master_awlen = shim_awff$D_OUT[28:21] ; - // value method cpu_dmem_master_m_awlen - assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ; + // value method cpu_dmem_master_aw_awsize + assign cpu_dmem_master_awsize = shim_awff$D_OUT[20:18] ; - // value method cpu_dmem_master_m_awsize - assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ; + // value method cpu_dmem_master_aw_awburst + assign cpu_dmem_master_awburst = shim_awff$D_OUT[17:16] ; - // value method cpu_dmem_master_m_awburst - assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ; + // value method cpu_dmem_master_aw_awlock + assign cpu_dmem_master_awlock = shim_awff$D_OUT[15] ; - // value method cpu_dmem_master_m_awlock - assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ; + // value method cpu_dmem_master_aw_awcache + assign cpu_dmem_master_awcache = shim_awff$D_OUT[14:11] ; - // value method cpu_dmem_master_m_awcache - assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ; + // value method cpu_dmem_master_aw_awprot + assign cpu_dmem_master_awprot = shim_awff$D_OUT[10:8] ; - // value method cpu_dmem_master_m_awprot - assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ; + // value method cpu_dmem_master_aw_awqos + assign cpu_dmem_master_awqos = shim_awff$D_OUT[7:4] ; - // value method cpu_dmem_master_m_awqos - assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ; + // value method cpu_dmem_master_aw_awregion + assign cpu_dmem_master_awregion = shim_awff$D_OUT[3:0] ; - // value method cpu_dmem_master_m_awregion - assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ; + // value method cpu_dmem_master_aw_awvalid + assign cpu_dmem_master_awvalid = shim_awff$EMPTY_N ; - // action method cpu_dmem_master_m_awready - assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ; + // action method cpu_dmem_master_aw_awready + assign CAN_FIRE_cpu_dmem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_aw_awready = 1'd1 ; - // value method cpu_dmem_master_m_wvalid - assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ; + // value method cpu_dmem_master_w_wdata + assign cpu_dmem_master_wdata = shim_wff$D_OUT[72:9] ; - // value method cpu_dmem_master_m_wdata - assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ; + // value method cpu_dmem_master_w_wstrb + assign cpu_dmem_master_wstrb = shim_wff$D_OUT[8:1] ; - // value method cpu_dmem_master_m_wstrb - assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ; + // value method cpu_dmem_master_w_wlast + assign cpu_dmem_master_wlast = shim_wff$D_OUT[0] ; - // value method cpu_dmem_master_m_wlast - assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ; + // value method cpu_dmem_master_w_wvalid + assign cpu_dmem_master_wvalid = shim_wff$EMPTY_N ; - // action method cpu_dmem_master_m_wready - assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ; + // action method cpu_dmem_master_w_wready + assign CAN_FIRE_cpu_dmem_master_w_wready = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_w_wready = 1'd1 ; - // action method cpu_dmem_master_m_bvalid - assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ; + // action method cpu_dmem_master_b_bflit + assign CAN_FIRE_cpu_dmem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_b_bflit = cpu_dmem_master_bvalid ; - // value method cpu_dmem_master_m_bready - assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ; + // value method cpu_dmem_master_b_bready + assign cpu_dmem_master_bready = shim_bff$FULL_N ; - // value method cpu_dmem_master_m_arvalid - assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ; + // value method cpu_dmem_master_ar_arid + assign cpu_dmem_master_arid = shim_arff$D_OUT[97:93] ; - // value method cpu_dmem_master_m_arid - assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ; + // value method cpu_dmem_master_ar_araddr + assign cpu_dmem_master_araddr = shim_arff$D_OUT[92:29] ; - // value method cpu_dmem_master_m_araddr - assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ; + // value method cpu_dmem_master_ar_arlen + assign cpu_dmem_master_arlen = shim_arff$D_OUT[28:21] ; - // value method cpu_dmem_master_m_arlen - assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ; + // value method cpu_dmem_master_ar_arsize + assign cpu_dmem_master_arsize = shim_arff$D_OUT[20:18] ; - // value method cpu_dmem_master_m_arsize - assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ; + // value method cpu_dmem_master_ar_arburst + assign cpu_dmem_master_arburst = shim_arff$D_OUT[17:16] ; - // value method cpu_dmem_master_m_arburst - assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ; + // value method cpu_dmem_master_ar_arlock + assign cpu_dmem_master_arlock = shim_arff$D_OUT[15] ; - // value method cpu_dmem_master_m_arlock - assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ; + // value method cpu_dmem_master_ar_arcache + assign cpu_dmem_master_arcache = shim_arff$D_OUT[14:11] ; - // value method cpu_dmem_master_m_arcache - assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ; + // value method cpu_dmem_master_ar_arprot + assign cpu_dmem_master_arprot = shim_arff$D_OUT[10:8] ; - // value method cpu_dmem_master_m_arprot - assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ; + // value method cpu_dmem_master_ar_arqos + assign cpu_dmem_master_arqos = shim_arff$D_OUT[7:4] ; - // value method cpu_dmem_master_m_arqos - assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ; + // value method cpu_dmem_master_ar_arregion + assign cpu_dmem_master_arregion = shim_arff$D_OUT[3:0] ; - // value method cpu_dmem_master_m_arregion - assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ; + // value method cpu_dmem_master_ar_arvalid + assign cpu_dmem_master_arvalid = shim_arff$EMPTY_N ; - // action method cpu_dmem_master_m_arready - assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ; + // action method cpu_dmem_master_ar_arready + assign CAN_FIRE_cpu_dmem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_ar_arready = 1'd1 ; - // action method cpu_dmem_master_m_rvalid - assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ; + // action method cpu_dmem_master_r_rflit + assign CAN_FIRE_cpu_dmem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_cpu_dmem_master_r_rflit = cpu_dmem_master_rvalid ; - // value method cpu_dmem_master_m_rready - assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ; + // value method cpu_dmem_master_r_rready + assign cpu_dmem_master_rready = shim_rff$FULL_N ; // action method core_external_interrupt_sources_0_m_interrupt_req assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ; @@ -1984,12 +3178,10 @@ module mkCore(CLK, .dmem_master_awready(cpu$dmem_master_awready), .dmem_master_bid(cpu$dmem_master_bid), .dmem_master_bresp(cpu$dmem_master_bresp), - .dmem_master_bvalid(cpu$dmem_master_bvalid), .dmem_master_rdata(cpu$dmem_master_rdata), .dmem_master_rid(cpu$dmem_master_rid), .dmem_master_rlast(cpu$dmem_master_rlast), .dmem_master_rresp(cpu$dmem_master_rresp), - .dmem_master_rvalid(cpu$dmem_master_rvalid), .dmem_master_wready(cpu$dmem_master_wready), .hart0_csr_mem_server_request_put(cpu$hart0_csr_mem_server_request_put), .hart0_gpr_mem_server_request_put(cpu$hart0_gpr_mem_server_request_put), @@ -2000,12 +3192,10 @@ module mkCore(CLK, .imem_master_awready(cpu$imem_master_awready), .imem_master_bid(cpu$imem_master_bid), .imem_master_bresp(cpu$imem_master_bresp), - .imem_master_bvalid(cpu$imem_master_bvalid), .imem_master_rdata(cpu$imem_master_rdata), .imem_master_rid(cpu$imem_master_rid), .imem_master_rlast(cpu$imem_master_rlast), .imem_master_rresp(cpu$imem_master_rresp), - .imem_master_rvalid(cpu$imem_master_rvalid), .imem_master_wready(cpu$imem_master_wready), .m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear), .nmi_req_set_not_clear(cpu$nmi_req_set_not_clear), @@ -2016,6 +3206,10 @@ module mkCore(CLK, .timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear), .EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put), .EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get), + .imem_master_bvalid(cpu$imem_master_bvalid), + .imem_master_rvalid(cpu$imem_master_rvalid), + .dmem_master_bvalid(cpu$dmem_master_bvalid), + .dmem_master_rvalid(cpu$dmem_master_rvalid), .EN_set_verbosity(cpu$EN_set_verbosity), .EN_trace_data_out_get(cpu$EN_trace_data_out_get), .EN_hart0_server_run_halt_request_put(cpu$EN_hart0_server_run_halt_request_put), @@ -2028,7 +3222,6 @@ module mkCore(CLK, .RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put), .hart0_server_reset_response_get(cpu$hart0_server_reset_response_get), .RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get), - .imem_master_awvalid(cpu$imem_master_awvalid), .imem_master_awid(cpu$imem_master_awid), .imem_master_awaddr(cpu$imem_master_awaddr), .imem_master_awlen(cpu$imem_master_awlen), @@ -2039,12 +3232,12 @@ module mkCore(CLK, .imem_master_awprot(cpu$imem_master_awprot), .imem_master_awqos(cpu$imem_master_awqos), .imem_master_awregion(cpu$imem_master_awregion), - .imem_master_wvalid(cpu$imem_master_wvalid), + .imem_master_awvalid(cpu$imem_master_awvalid), .imem_master_wdata(cpu$imem_master_wdata), .imem_master_wstrb(cpu$imem_master_wstrb), .imem_master_wlast(cpu$imem_master_wlast), + .imem_master_wvalid(cpu$imem_master_wvalid), .imem_master_bready(cpu$imem_master_bready), - .imem_master_arvalid(cpu$imem_master_arvalid), .imem_master_arid(cpu$imem_master_arid), .imem_master_araddr(cpu$imem_master_araddr), .imem_master_arlen(cpu$imem_master_arlen), @@ -2055,8 +3248,8 @@ module mkCore(CLK, .imem_master_arprot(cpu$imem_master_arprot), .imem_master_arqos(cpu$imem_master_arqos), .imem_master_arregion(cpu$imem_master_arregion), + .imem_master_arvalid(cpu$imem_master_arvalid), .imem_master_rready(cpu$imem_master_rready), - .dmem_master_awvalid(cpu$dmem_master_awvalid), .dmem_master_awid(cpu$dmem_master_awid), .dmem_master_awaddr(cpu$dmem_master_awaddr), .dmem_master_awlen(cpu$dmem_master_awlen), @@ -2067,12 +3260,12 @@ module mkCore(CLK, .dmem_master_awprot(cpu$dmem_master_awprot), .dmem_master_awqos(cpu$dmem_master_awqos), .dmem_master_awregion(cpu$dmem_master_awregion), - .dmem_master_wvalid(cpu$dmem_master_wvalid), + .dmem_master_awvalid(cpu$dmem_master_awvalid), .dmem_master_wdata(cpu$dmem_master_wdata), .dmem_master_wstrb(cpu$dmem_master_wstrb), .dmem_master_wlast(cpu$dmem_master_wlast), + .dmem_master_wvalid(cpu$dmem_master_wvalid), .dmem_master_bready(cpu$dmem_master_bready), - .dmem_master_arvalid(cpu$dmem_master_arvalid), .dmem_master_arid(cpu$dmem_master_arid), .dmem_master_araddr(cpu$dmem_master_araddr), .dmem_master_arlen(cpu$dmem_master_arlen), @@ -2083,6 +3276,7 @@ module mkCore(CLK, .dmem_master_arprot(cpu$dmem_master_arprot), .dmem_master_arqos(cpu$dmem_master_arqos), .dmem_master_arregion(cpu$dmem_master_arregion), + .dmem_master_arvalid(cpu$dmem_master_arvalid), .dmem_master_rready(cpu$dmem_master_rready), .RDY_set_verbosity(), .trace_data_out_get(cpu$trace_data_out_get), @@ -2112,12 +3306,10 @@ module mkCore(CLK, .master_awready(debug_module$master_awready), .master_bid(debug_module$master_bid), .master_bresp(debug_module$master_bresp), - .master_bvalid(debug_module$master_bvalid), .master_rdata(debug_module$master_rdata), .master_rid(debug_module$master_rid), .master_rlast(debug_module$master_rlast), .master_rresp(debug_module$master_rresp), - .master_rvalid(debug_module$master_rvalid), .master_wready(debug_module$master_wready), .ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put), .EN_dmi_read_addr(debug_module$EN_dmi_read_addr), @@ -2134,6 +3326,8 @@ module mkCore(CLK, .EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put), .EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get), .EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put), + .master_bvalid(debug_module$master_bvalid), + .master_rvalid(debug_module$master_rvalid), .RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr), .dmi_read_data(debug_module$dmi_read_data), .RDY_dmi_read_data(debug_module$RDY_dmi_read_data), @@ -2155,7 +3349,6 @@ module mkCore(CLK, .ndm_reset_client_request_get(debug_module$ndm_reset_client_request_get), .RDY_ndm_reset_client_request_get(debug_module$RDY_ndm_reset_client_request_get), .RDY_ndm_reset_client_response_put(debug_module$RDY_ndm_reset_client_response_put), - .master_awvalid(debug_module$master_awvalid), .master_awid(debug_module$master_awid), .master_awaddr(debug_module$master_awaddr), .master_awlen(debug_module$master_awlen), @@ -2166,12 +3359,12 @@ module mkCore(CLK, .master_awprot(debug_module$master_awprot), .master_awqos(debug_module$master_awqos), .master_awregion(debug_module$master_awregion), - .master_wvalid(debug_module$master_wvalid), + .master_awvalid(debug_module$master_awvalid), .master_wdata(debug_module$master_wdata), .master_wstrb(debug_module$master_wstrb), .master_wlast(debug_module$master_wlast), + .master_wvalid(debug_module$master_wvalid), .master_bready(debug_module$master_bready), - .master_arvalid(debug_module$master_arvalid), .master_arid(debug_module$master_arid), .master_araddr(debug_module$master_araddr), .master_arlen(debug_module$master_arlen), @@ -2182,6 +3375,7 @@ module mkCore(CLK, .master_arprot(debug_module$master_arprot), .master_arqos(debug_module$master_arqos), .master_arregion(debug_module$master_arregion), + .master_arvalid(debug_module$master_arvalid), .master_rready(debug_module$master_rready)); // submodule dm_csr_tap @@ -2229,12 +3423,10 @@ module mkCore(CLK, .master_awready(dm_mem_tap$master_awready), .master_bid(dm_mem_tap$master_bid), .master_bresp(dm_mem_tap$master_bresp), - .master_bvalid(dm_mem_tap$master_bvalid), .master_rdata(dm_mem_tap$master_rdata), .master_rid(dm_mem_tap$master_rid), .master_rlast(dm_mem_tap$master_rlast), .master_rresp(dm_mem_tap$master_rresp), - .master_rvalid(dm_mem_tap$master_rvalid), .master_wready(dm_mem_tap$master_wready), .slave_araddr(dm_mem_tap$slave_araddr), .slave_arburst(dm_mem_tap$slave_arburst), @@ -2246,7 +3438,6 @@ module mkCore(CLK, .slave_arqos(dm_mem_tap$slave_arqos), .slave_arregion(dm_mem_tap$slave_arregion), .slave_arsize(dm_mem_tap$slave_arsize), - .slave_arvalid(dm_mem_tap$slave_arvalid), .slave_awaddr(dm_mem_tap$slave_awaddr), .slave_awburst(dm_mem_tap$slave_awburst), .slave_awcache(dm_mem_tap$slave_awcache), @@ -2257,26 +3448,28 @@ module mkCore(CLK, .slave_awqos(dm_mem_tap$slave_awqos), .slave_awregion(dm_mem_tap$slave_awregion), .slave_awsize(dm_mem_tap$slave_awsize), - .slave_awvalid(dm_mem_tap$slave_awvalid), .slave_bready(dm_mem_tap$slave_bready), .slave_rready(dm_mem_tap$slave_rready), .slave_wdata(dm_mem_tap$slave_wdata), .slave_wlast(dm_mem_tap$slave_wlast), .slave_wstrb(dm_mem_tap$slave_wstrb), + .slave_awvalid(dm_mem_tap$slave_awvalid), .slave_wvalid(dm_mem_tap$slave_wvalid), + .slave_arvalid(dm_mem_tap$slave_arvalid), + .master_bvalid(dm_mem_tap$master_bvalid), + .master_rvalid(dm_mem_tap$master_rvalid), .EN_trace_data_out_get(dm_mem_tap$EN_trace_data_out_get), .slave_awready(dm_mem_tap$slave_awready), .slave_wready(dm_mem_tap$slave_wready), - .slave_bvalid(dm_mem_tap$slave_bvalid), .slave_bid(dm_mem_tap$slave_bid), .slave_bresp(dm_mem_tap$slave_bresp), + .slave_bvalid(dm_mem_tap$slave_bvalid), .slave_arready(dm_mem_tap$slave_arready), - .slave_rvalid(dm_mem_tap$slave_rvalid), .slave_rid(dm_mem_tap$slave_rid), .slave_rdata(dm_mem_tap$slave_rdata), .slave_rresp(dm_mem_tap$slave_rresp), .slave_rlast(dm_mem_tap$slave_rlast), - .master_awvalid(dm_mem_tap$master_awvalid), + .slave_rvalid(dm_mem_tap$slave_rvalid), .master_awid(dm_mem_tap$master_awid), .master_awaddr(dm_mem_tap$master_awaddr), .master_awlen(dm_mem_tap$master_awlen), @@ -2287,12 +3480,12 @@ module mkCore(CLK, .master_awprot(dm_mem_tap$master_awprot), .master_awqos(dm_mem_tap$master_awqos), .master_awregion(dm_mem_tap$master_awregion), - .master_wvalid(dm_mem_tap$master_wvalid), + .master_awvalid(dm_mem_tap$master_awvalid), .master_wdata(dm_mem_tap$master_wdata), .master_wstrb(dm_mem_tap$master_wstrb), .master_wlast(dm_mem_tap$master_wlast), + .master_wvalid(dm_mem_tap$master_wvalid), .master_bready(dm_mem_tap$master_bready), - .master_arvalid(dm_mem_tap$master_arvalid), .master_arid(dm_mem_tap$master_arid), .master_araddr(dm_mem_tap$master_araddr), .master_arlen(dm_mem_tap$master_arlen), @@ -2303,6 +3496,7 @@ module mkCore(CLK, .master_arprot(dm_mem_tap$master_arprot), .master_arqos(dm_mem_tap$master_arqos), .master_arregion(dm_mem_tap$master_arregion), + .master_arvalid(dm_mem_tap$master_arvalid), .master_rready(dm_mem_tap$master_rready), .trace_data_out_get(dm_mem_tap$trace_data_out_get), .RDY_trace_data_out_get(dm_mem_tap$RDY_trace_data_out_get)); @@ -2351,209 +3545,343 @@ module mkCore(CLK, .FULL_N(f_trace_data_merged$FULL_N), .EMPTY_N(f_trace_data_merged$EMPTY_N)); - // submodule fabric_2x3 - mkFabric_2x3 fabric_2x3(.CLK(CLK), - .RST_N(RST_N), - .set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity), - .v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr), - .v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst), - .v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache), - .v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid), - .v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen), - .v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock), - .v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot), - .v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos), - .v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion), - .v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize), - .v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid), - .v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr), - .v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst), - .v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache), - .v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid), - .v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen), - .v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock), - .v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot), - .v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos), - .v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion), - .v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize), - .v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid), - .v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready), - .v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready), - .v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata), - .v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast), - .v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb), - .v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid), - .v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr), - .v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst), - .v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache), - .v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid), - .v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen), - .v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock), - .v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot), - .v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos), - .v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion), - .v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize), - .v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid), - .v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr), - .v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst), - .v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache), - .v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid), - .v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen), - .v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock), - .v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot), - .v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos), - .v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion), - .v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize), - .v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid), - .v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready), - .v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready), - .v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata), - .v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast), - .v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb), - .v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid), - .v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready), - .v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready), - .v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid), - .v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp), - .v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid), - .v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata), - .v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid), - .v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast), - .v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp), - .v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid), - .v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready), - .v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready), - .v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready), - .v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid), - .v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp), - .v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid), - .v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata), - .v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid), - .v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast), - .v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp), - .v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid), - .v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready), - .v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready), - .v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready), - .v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid), - .v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp), - .v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid), - .v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata), - .v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid), - .v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast), - .v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp), - .v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid), - .v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready), - .EN_reset(fabric_2x3$EN_reset), - .EN_set_verbosity(fabric_2x3$EN_set_verbosity), - .RDY_reset(fabric_2x3$RDY_reset), - .RDY_set_verbosity(), - .v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready), - .v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready), - .v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid), - .v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid), - .v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp), - .v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready), - .v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid), - .v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid), - .v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata), - .v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp), - .v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast), - .v_from_masters_1_awready(fabric_2x3$v_from_masters_1_awready), - .v_from_masters_1_wready(fabric_2x3$v_from_masters_1_wready), - .v_from_masters_1_bvalid(fabric_2x3$v_from_masters_1_bvalid), - .v_from_masters_1_bid(fabric_2x3$v_from_masters_1_bid), - .v_from_masters_1_bresp(fabric_2x3$v_from_masters_1_bresp), - .v_from_masters_1_arready(fabric_2x3$v_from_masters_1_arready), - .v_from_masters_1_rvalid(fabric_2x3$v_from_masters_1_rvalid), - .v_from_masters_1_rid(fabric_2x3$v_from_masters_1_rid), - .v_from_masters_1_rdata(fabric_2x3$v_from_masters_1_rdata), - .v_from_masters_1_rresp(fabric_2x3$v_from_masters_1_rresp), - .v_from_masters_1_rlast(fabric_2x3$v_from_masters_1_rlast), - .v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid), - .v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid), - .v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr), - .v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen), - .v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize), - .v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst), - .v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock), - .v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache), - .v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot), - .v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos), - .v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion), - .v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid), - .v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata), - .v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb), - .v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast), - .v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready), - .v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid), - .v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid), - .v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr), - .v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen), - .v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize), - .v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst), - .v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock), - .v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache), - .v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot), - .v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos), - .v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion), - .v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready), - .v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid), - .v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid), - .v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr), - .v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen), - .v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize), - .v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst), - .v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock), - .v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache), - .v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot), - .v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos), - .v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion), - .v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid), - .v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata), - .v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb), - .v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast), - .v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready), - .v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid), - .v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid), - .v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr), - .v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen), - .v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize), - .v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst), - .v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock), - .v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache), - .v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot), - .v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos), - .v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion), - .v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready), - .v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid), - .v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid), - .v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr), - .v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen), - .v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize), - .v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst), - .v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock), - .v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache), - .v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot), - .v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos), - .v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion), - .v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid), - .v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata), - .v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb), - .v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast), - .v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready), - .v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid), - .v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid), - .v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr), - .v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen), - .v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize), - .v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst), - .v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock), - .v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache), - .v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot), - .v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos), - .v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion), - .v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready)); + // submodule ifcs_0_1_innerReq + FIFO2 #(.width(32'd98), .guarded(32'd1)) ifcs_0_1_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_innerReq$D_IN), + .ENQ(ifcs_0_1_innerReq$ENQ), + .DEQ(ifcs_0_1_innerReq$DEQ), + .CLR(ifcs_0_1_innerReq$CLR), + .D_OUT(ifcs_0_1_innerReq$D_OUT), + .FULL_N(ifcs_0_1_innerReq$FULL_N), + .EMPTY_N(ifcs_0_1_innerReq$EMPTY_N)); + + // submodule ifcs_0_1_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_0_1_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_innerRoute$D_IN), + .ENQ(ifcs_0_1_innerRoute$ENQ), + .DEQ(ifcs_0_1_innerRoute$DEQ), + .CLR(ifcs_0_1_innerRoute$CLR), + .D_OUT(ifcs_0_1_innerRoute$D_OUT), + .FULL_N(ifcs_0_1_innerRoute$FULL_N), + .EMPTY_N(ifcs_0_1_innerRoute$EMPTY_N)); + + // submodule ifcs_0_1_noRouteRsp + FIFO2 #(.width(32'd71), .guarded(32'd1)) ifcs_0_1_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_noRouteRsp$D_IN), + .ENQ(ifcs_0_1_noRouteRsp$ENQ), + .DEQ(ifcs_0_1_noRouteRsp$DEQ), + .CLR(ifcs_0_1_noRouteRsp$CLR), + .D_OUT(ifcs_0_1_noRouteRsp$D_OUT), + .FULL_N(ifcs_0_1_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_0_1_noRouteRsp$EMPTY_N)); + + // submodule ifcs_0_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_0_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_routeBack$D_IN), + .ENQ(ifcs_0_1_routeBack$ENQ), + .DEQ(ifcs_0_1_routeBack$DEQ), + .CLR(ifcs_0_1_routeBack$CLR), + .D_OUT(ifcs_0_1_routeBack$D_OUT), + .FULL_N(ifcs_0_1_routeBack$FULL_N), + .EMPTY_N(ifcs_0_1_routeBack$EMPTY_N)); + + // submodule ifcs_0_1_rspBack + FIFO2 #(.width(32'd71), .guarded(32'd1)) ifcs_0_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_1_rspBack$D_IN), + .ENQ(ifcs_0_1_rspBack$ENQ), + .DEQ(ifcs_0_1_rspBack$DEQ), + .CLR(ifcs_0_1_rspBack$CLR), + .D_OUT(ifcs_0_1_rspBack$D_OUT), + .FULL_N(ifcs_0_1_rspBack$FULL_N), + .EMPTY_N(ifcs_0_1_rspBack$EMPTY_N)); + + // submodule ifcs_0_innerReq + FIFO2 #(.width(32'd172), .guarded(32'd1)) ifcs_0_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_innerReq$D_IN), + .ENQ(ifcs_0_innerReq$ENQ), + .DEQ(ifcs_0_innerReq$DEQ), + .CLR(ifcs_0_innerReq$CLR), + .D_OUT(ifcs_0_innerReq$D_OUT), + .FULL_N(ifcs_0_innerReq$FULL_N), + .EMPTY_N(ifcs_0_innerReq$EMPTY_N)); + + // submodule ifcs_0_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_0_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_innerRoute$D_IN), + .ENQ(ifcs_0_innerRoute$ENQ), + .DEQ(ifcs_0_innerRoute$DEQ), + .CLR(ifcs_0_innerRoute$CLR), + .D_OUT(ifcs_0_innerRoute$D_OUT), + .FULL_N(ifcs_0_innerRoute$FULL_N), + .EMPTY_N(ifcs_0_innerRoute$EMPTY_N)); + + // submodule ifcs_0_noRouteRsp + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_0_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_noRouteRsp$D_IN), + .ENQ(ifcs_0_noRouteRsp$ENQ), + .DEQ(ifcs_0_noRouteRsp$DEQ), + .CLR(ifcs_0_noRouteRsp$CLR), + .D_OUT(ifcs_0_noRouteRsp$D_OUT), + .FULL_N(ifcs_0_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_0_noRouteRsp$EMPTY_N)); + + // submodule ifcs_0_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_0_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_routeBack$D_IN), + .ENQ(ifcs_0_routeBack$ENQ), + .DEQ(ifcs_0_routeBack$DEQ), + .CLR(ifcs_0_routeBack$CLR), + .D_OUT(ifcs_0_routeBack$D_OUT), + .FULL_N(ifcs_0_routeBack$FULL_N), + .EMPTY_N(ifcs_0_routeBack$EMPTY_N)); + + // submodule ifcs_0_rspBack + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_0_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_0_rspBack$D_IN), + .ENQ(ifcs_0_rspBack$ENQ), + .DEQ(ifcs_0_rspBack$DEQ), + .CLR(ifcs_0_rspBack$CLR), + .D_OUT(ifcs_0_rspBack$D_OUT), + .FULL_N(ifcs_0_rspBack$FULL_N), + .EMPTY_N(ifcs_0_rspBack$EMPTY_N)); + + // submodule ifcs_1_1_innerReq + FIFO2 #(.width(32'd98), .guarded(32'd1)) ifcs_1_1_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_innerReq$D_IN), + .ENQ(ifcs_1_1_innerReq$ENQ), + .DEQ(ifcs_1_1_innerReq$DEQ), + .CLR(ifcs_1_1_innerReq$CLR), + .D_OUT(ifcs_1_1_innerReq$D_OUT), + .FULL_N(ifcs_1_1_innerReq$FULL_N), + .EMPTY_N(ifcs_1_1_innerReq$EMPTY_N)); + + // submodule ifcs_1_1_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_1_1_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_innerRoute$D_IN), + .ENQ(ifcs_1_1_innerRoute$ENQ), + .DEQ(ifcs_1_1_innerRoute$DEQ), + .CLR(ifcs_1_1_innerRoute$CLR), + .D_OUT(ifcs_1_1_innerRoute$D_OUT), + .FULL_N(ifcs_1_1_innerRoute$FULL_N), + .EMPTY_N(ifcs_1_1_innerRoute$EMPTY_N)); + + // submodule ifcs_1_1_noRouteRsp + FIFO2 #(.width(32'd71), .guarded(32'd1)) ifcs_1_1_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_noRouteRsp$D_IN), + .ENQ(ifcs_1_1_noRouteRsp$ENQ), + .DEQ(ifcs_1_1_noRouteRsp$DEQ), + .CLR(ifcs_1_1_noRouteRsp$CLR), + .D_OUT(ifcs_1_1_noRouteRsp$D_OUT), + .FULL_N(ifcs_1_1_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_1_1_noRouteRsp$EMPTY_N)); + + // submodule ifcs_1_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_1_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_routeBack$D_IN), + .ENQ(ifcs_1_1_routeBack$ENQ), + .DEQ(ifcs_1_1_routeBack$DEQ), + .CLR(ifcs_1_1_routeBack$CLR), + .D_OUT(ifcs_1_1_routeBack$D_OUT), + .FULL_N(ifcs_1_1_routeBack$FULL_N), + .EMPTY_N(ifcs_1_1_routeBack$EMPTY_N)); + + // submodule ifcs_1_1_rspBack + FIFO2 #(.width(32'd71), .guarded(32'd1)) ifcs_1_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_1_rspBack$D_IN), + .ENQ(ifcs_1_1_rspBack$ENQ), + .DEQ(ifcs_1_1_rspBack$DEQ), + .CLR(ifcs_1_1_rspBack$CLR), + .D_OUT(ifcs_1_1_rspBack$D_OUT), + .FULL_N(ifcs_1_1_rspBack$FULL_N), + .EMPTY_N(ifcs_1_1_rspBack$EMPTY_N)); + + // submodule ifcs_1_innerReq + FIFO2 #(.width(32'd172), .guarded(32'd1)) ifcs_1_innerReq(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_innerReq$D_IN), + .ENQ(ifcs_1_innerReq$ENQ), + .DEQ(ifcs_1_innerReq$DEQ), + .CLR(ifcs_1_innerReq$CLR), + .D_OUT(ifcs_1_innerReq$D_OUT), + .FULL_N(ifcs_1_innerReq$FULL_N), + .EMPTY_N(ifcs_1_innerReq$EMPTY_N)); + + // submodule ifcs_1_innerRoute + FIFO2 #(.width(32'd3), .guarded(32'd1)) ifcs_1_innerRoute(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_innerRoute$D_IN), + .ENQ(ifcs_1_innerRoute$ENQ), + .DEQ(ifcs_1_innerRoute$DEQ), + .CLR(ifcs_1_innerRoute$CLR), + .D_OUT(ifcs_1_innerRoute$D_OUT), + .FULL_N(ifcs_1_innerRoute$FULL_N), + .EMPTY_N(ifcs_1_innerRoute$EMPTY_N)); + + // submodule ifcs_1_noRouteRsp + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_1_noRouteRsp(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_noRouteRsp$D_IN), + .ENQ(ifcs_1_noRouteRsp$ENQ), + .DEQ(ifcs_1_noRouteRsp$DEQ), + .CLR(ifcs_1_noRouteRsp$CLR), + .D_OUT(ifcs_1_noRouteRsp$D_OUT), + .FULL_N(ifcs_1_noRouteRsp$FULL_N), + .EMPTY_N(ifcs_1_noRouteRsp$EMPTY_N)); + + // submodule ifcs_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_routeBack$D_IN), + .ENQ(ifcs_1_routeBack$ENQ), + .DEQ(ifcs_1_routeBack$DEQ), + .CLR(ifcs_1_routeBack$CLR), + .D_OUT(ifcs_1_routeBack$D_OUT), + .FULL_N(ifcs_1_routeBack$FULL_N), + .EMPTY_N(ifcs_1_routeBack$EMPTY_N)); + + // submodule ifcs_1_rspBack + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_1_rspBack$D_IN), + .ENQ(ifcs_1_rspBack$ENQ), + .DEQ(ifcs_1_rspBack$DEQ), + .CLR(ifcs_1_rspBack$CLR), + .D_OUT(ifcs_1_rspBack$D_OUT), + .FULL_N(ifcs_1_rspBack$FULL_N), + .EMPTY_N(ifcs_1_rspBack$EMPTY_N)); + + // submodule ifcs_2_1_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_2_1_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_1_routeBack$D_IN), + .ENQ(ifcs_2_1_routeBack$ENQ), + .DEQ(ifcs_2_1_routeBack$DEQ), + .CLR(ifcs_2_1_routeBack$CLR), + .D_OUT(ifcs_2_1_routeBack$D_OUT), + .FULL_N(ifcs_2_1_routeBack$FULL_N), + .EMPTY_N(ifcs_2_1_routeBack$EMPTY_N)); + + // submodule ifcs_2_1_rspBack + FIFO2 #(.width(32'd71), .guarded(32'd1)) ifcs_2_1_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_1_rspBack$D_IN), + .ENQ(ifcs_2_1_rspBack$ENQ), + .DEQ(ifcs_2_1_rspBack$DEQ), + .CLR(ifcs_2_1_rspBack$CLR), + .D_OUT(ifcs_2_1_rspBack$D_OUT), + .FULL_N(ifcs_2_1_rspBack$FULL_N), + .EMPTY_N(ifcs_2_1_rspBack$EMPTY_N)); + + // submodule ifcs_2_routeBack + FIFO2 #(.width(32'd2), .guarded(32'd1)) ifcs_2_routeBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_routeBack$D_IN), + .ENQ(ifcs_2_routeBack$ENQ), + .DEQ(ifcs_2_routeBack$DEQ), + .CLR(ifcs_2_routeBack$CLR), + .D_OUT(ifcs_2_routeBack$D_OUT), + .FULL_N(ifcs_2_routeBack$FULL_N), + .EMPTY_N(ifcs_2_routeBack$EMPTY_N)); + + // submodule ifcs_2_rspBack + FIFO2 #(.width(32'd6), .guarded(32'd1)) ifcs_2_rspBack(.RST(RST_N), + .CLK(CLK), + .D_IN(ifcs_2_rspBack$D_IN), + .ENQ(ifcs_2_rspBack$ENQ), + .DEQ(ifcs_2_rspBack$DEQ), + .CLR(ifcs_2_rspBack$CLR), + .D_OUT(ifcs_2_rspBack$D_OUT), + .FULL_N(ifcs_2_rspBack$FULL_N), + .EMPTY_N(ifcs_2_rspBack$EMPTY_N)); + + // submodule msNoSynth_0_b_buffer_ff + FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_0_b_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_b_buffer_ff$D_IN), + .ENQ(msNoSynth_0_b_buffer_ff$ENQ), + .DEQ(msNoSynth_0_b_buffer_ff$DEQ), + .CLR(msNoSynth_0_b_buffer_ff$CLR), + .D_OUT(msNoSynth_0_b_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_b_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_b_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_b_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_b_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_b_buffer_firstValid$D_IN), + .EN(msNoSynth_0_b_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_b_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_0_r_buffer_ff + FIFO1 #(.width(32'd71), + .guarded(32'd0)) msNoSynth_0_r_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_0_r_buffer_ff$D_IN), + .ENQ(msNoSynth_0_r_buffer_ff$ENQ), + .DEQ(msNoSynth_0_r_buffer_ff$DEQ), + .CLR(msNoSynth_0_r_buffer_ff$CLR), + .D_OUT(msNoSynth_0_r_buffer_ff$D_OUT), + .FULL_N(msNoSynth_0_r_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_0_r_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_0_r_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_0_r_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_0_r_buffer_firstValid$D_IN), + .EN(msNoSynth_0_r_buffer_firstValid$EN), + .Q_OUT(msNoSynth_0_r_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_b_buffer_ff + FIFO1 #(.width(32'd6), .guarded(32'd0)) msNoSynth_1_b_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_b_buffer_ff$D_IN), + .ENQ(msNoSynth_1_b_buffer_ff$ENQ), + .DEQ(msNoSynth_1_b_buffer_ff$DEQ), + .CLR(msNoSynth_1_b_buffer_ff$CLR), + .D_OUT(msNoSynth_1_b_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_b_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_b_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_b_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_b_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_b_buffer_firstValid$D_IN), + .EN(msNoSynth_1_b_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_b_buffer_firstValid$Q_OUT)); + + // submodule msNoSynth_1_r_buffer_ff + FIFO1 #(.width(32'd71), + .guarded(32'd0)) msNoSynth_1_r_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(msNoSynth_1_r_buffer_ff$D_IN), + .ENQ(msNoSynth_1_r_buffer_ff$ENQ), + .DEQ(msNoSynth_1_r_buffer_ff$DEQ), + .CLR(msNoSynth_1_r_buffer_ff$CLR), + .D_OUT(msNoSynth_1_r_buffer_ff$D_OUT), + .FULL_N(msNoSynth_1_r_buffer_ff$FULL_N), + .EMPTY_N(msNoSynth_1_r_buffer_ff$EMPTY_N)); + + // submodule msNoSynth_1_r_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) msNoSynth_1_r_buffer_firstValid(.CLK(CLK), + .D_IN(msNoSynth_1_r_buffer_firstValid$D_IN), + .EN(msNoSynth_1_r_buffer_firstValid$EN), + .Q_OUT(msNoSynth_1_r_buffer_firstValid$Q_OUT)); // submodule near_mem_io mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK), @@ -2568,7 +3896,6 @@ module mkCore(CLK, .axi4_slave_arqos(near_mem_io$axi4_slave_arqos), .axi4_slave_arregion(near_mem_io$axi4_slave_arregion), .axi4_slave_arsize(near_mem_io$axi4_slave_arsize), - .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), .axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr), .axi4_slave_awburst(near_mem_io$axi4_slave_awburst), .axi4_slave_awcache(near_mem_io$axi4_slave_awcache), @@ -2579,18 +3906,19 @@ module mkCore(CLK, .axi4_slave_awqos(near_mem_io$axi4_slave_awqos), .axi4_slave_awregion(near_mem_io$axi4_slave_awregion), .axi4_slave_awsize(near_mem_io$axi4_slave_awsize), - .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), .axi4_slave_bready(near_mem_io$axi4_slave_bready), .axi4_slave_rready(near_mem_io$axi4_slave_rready), .axi4_slave_wdata(near_mem_io$axi4_slave_wdata), .axi4_slave_wlast(near_mem_io$axi4_slave_wlast), .axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb), - .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), .set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base), .set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim), .EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put), .EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get), .EN_set_addr_map(near_mem_io$EN_set_addr_map), + .axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid), + .axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid), + .axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid), .EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get), .EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get), .RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put), @@ -2598,15 +3926,15 @@ module mkCore(CLK, .RDY_set_addr_map(), .axi4_slave_awready(near_mem_io$axi4_slave_awready), .axi4_slave_wready(near_mem_io$axi4_slave_wready), - .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), .axi4_slave_bid(near_mem_io$axi4_slave_bid), .axi4_slave_bresp(near_mem_io$axi4_slave_bresp), + .axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid), .axi4_slave_arready(near_mem_io$axi4_slave_arready), - .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), .axi4_slave_rid(near_mem_io$axi4_slave_rid), .axi4_slave_rdata(near_mem_io$axi4_slave_rdata), .axi4_slave_rresp(near_mem_io$axi4_slave_rresp), .axi4_slave_rlast(near_mem_io$axi4_slave_rlast), + .axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid), .get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get), .RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get), .get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get), @@ -2625,7 +3953,6 @@ module mkCore(CLK, .axi4_slave_arqos(plic$axi4_slave_arqos), .axi4_slave_arregion(plic$axi4_slave_arregion), .axi4_slave_arsize(plic$axi4_slave_arsize), - .axi4_slave_arvalid(plic$axi4_slave_arvalid), .axi4_slave_awaddr(plic$axi4_slave_awaddr), .axi4_slave_awburst(plic$axi4_slave_awburst), .axi4_slave_awcache(plic$axi4_slave_awcache), @@ -2636,13 +3963,11 @@ module mkCore(CLK, .axi4_slave_awqos(plic$axi4_slave_awqos), .axi4_slave_awregion(plic$axi4_slave_awregion), .axi4_slave_awsize(plic$axi4_slave_awsize), - .axi4_slave_awvalid(plic$axi4_slave_awvalid), .axi4_slave_bready(plic$axi4_slave_bready), .axi4_slave_rready(plic$axi4_slave_rready), .axi4_slave_wdata(plic$axi4_slave_wdata), .axi4_slave_wlast(plic$axi4_slave_wlast), .axi4_slave_wstrb(plic$axi4_slave_wstrb), - .axi4_slave_wvalid(plic$axi4_slave_wvalid), .set_addr_map_addr_base(plic$set_addr_map_addr_base), .set_addr_map_addr_lim(plic$set_addr_map_addr_lim), .set_verbosity_verbosity(plic$set_verbosity_verbosity), @@ -2667,6 +3992,9 @@ module mkCore(CLK, .EN_server_reset_request_put(plic$EN_server_reset_request_put), .EN_server_reset_response_get(plic$EN_server_reset_response_get), .EN_set_addr_map(plic$EN_set_addr_map), + .axi4_slave_awvalid(plic$axi4_slave_awvalid), + .axi4_slave_wvalid(plic$axi4_slave_wvalid), + .axi4_slave_arvalid(plic$axi4_slave_arvalid), .RDY_set_verbosity(), .RDY_show_PLIC_state(), .RDY_server_reset_request_put(plic$RDY_server_reset_request_put), @@ -2674,54 +4002,104 @@ module mkCore(CLK, .RDY_set_addr_map(), .axi4_slave_awready(plic$axi4_slave_awready), .axi4_slave_wready(plic$axi4_slave_wready), - .axi4_slave_bvalid(plic$axi4_slave_bvalid), .axi4_slave_bid(plic$axi4_slave_bid), .axi4_slave_bresp(plic$axi4_slave_bresp), + .axi4_slave_bvalid(plic$axi4_slave_bvalid), .axi4_slave_arready(plic$axi4_slave_arready), - .axi4_slave_rvalid(plic$axi4_slave_rvalid), .axi4_slave_rid(plic$axi4_slave_rid), .axi4_slave_rdata(plic$axi4_slave_rdata), .axi4_slave_rresp(plic$axi4_slave_rresp), .axi4_slave_rlast(plic$axi4_slave_rlast), + .axi4_slave_rvalid(plic$axi4_slave_rvalid), .v_targets_0_m_eip(plic$v_targets_0_m_eip), .v_targets_1_m_eip(plic$v_targets_1_m_eip)); + // submodule shim_arff + SizedFIFO #(.p1width(32'd98), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd0)) shim_arff(.RST(RST_N), + .CLK(CLK), + .D_IN(shim_arff$D_IN), + .ENQ(shim_arff$ENQ), + .DEQ(shim_arff$DEQ), + .CLR(shim_arff$CLR), + .D_OUT(shim_arff$D_OUT), + .FULL_N(shim_arff$FULL_N), + .EMPTY_N(shim_arff$EMPTY_N)); + + // submodule shim_awff + SizedFIFO #(.p1width(32'd98), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd0)) shim_awff(.RST(RST_N), + .CLK(CLK), + .D_IN(shim_awff$D_IN), + .ENQ(shim_awff$ENQ), + .DEQ(shim_awff$DEQ), + .CLR(shim_awff$CLR), + .D_OUT(shim_awff$D_OUT), + .FULL_N(shim_awff$FULL_N), + .EMPTY_N(shim_awff$EMPTY_N)); + + // submodule shim_bff + SizedFIFO #(.p1width(32'd7), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd0)) shim_bff(.RST(RST_N), + .CLK(CLK), + .D_IN(shim_bff$D_IN), + .ENQ(shim_bff$ENQ), + .DEQ(shim_bff$DEQ), + .CLR(shim_bff$CLR), + .D_OUT(shim_bff$D_OUT), + .FULL_N(shim_bff$FULL_N), + .EMPTY_N(shim_bff$EMPTY_N)); + + // submodule shim_rff + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd0)) shim_rff(.RST(RST_N), + .CLK(CLK), + .D_IN(shim_rff$D_IN), + .ENQ(shim_rff$ENQ), + .DEQ(shim_rff$DEQ), + .CLR(shim_rff$CLR), + .D_OUT(shim_rff$D_OUT), + .FULL_N(shim_rff$FULL_N), + .EMPTY_N(shim_rff$EMPTY_N)); + + // submodule shim_wff + SizedFIFO #(.p1width(32'd73), + .p2depth(32'd4), + .p3cntr_width(32'd2), + .guarded(32'd0)) shim_wff(.RST(RST_N), + .CLK(CLK), + .D_IN(shim_wff$D_IN), + .ENQ(shim_wff$ENQ), + .DEQ(shim_wff$DEQ), + .CLR(shim_wff$CLR), + .D_OUT(shim_wff$D_OUT), + .FULL_N(shim_wff$FULL_N), + .EMPTY_N(shim_wff$EMPTY_N)); + // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), .RST_N(RST_N), .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_plic_addr_base(soc_map$m_plic_addr_base), - .m_plic_addr_size(), - .m_plic_addr_lim(soc_map$m_plic_addr_lim), - .m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim), - .m_flash_mem_addr_base(), - .m_flash_mem_addr_size(), - .m_flash_mem_addr_lim(), - .m_ethernet_0_addr_base(), - .m_ethernet_0_addr_size(), - .m_ethernet_0_addr_lim(), - .m_dma_0_addr_base(), - .m_dma_0_addr_size(), - .m_dma_0_addr_lim(), - .m_uart16550_0_addr_base(), - .m_uart16550_0_addr_size(), - .m_uart16550_0_addr_lim(), - .m_gpio_0_addr_base(), - .m_gpio_0_addr_size(), - .m_gpio_0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_ddr4_0_uncached_addr_base(), - .m_ddr4_0_uncached_addr_size(), - .m_ddr4_0_uncached_addr_lim(), - .m_ddr4_0_cached_addr_base(), - .m_ddr4_0_cached_addr_size(), - .m_ddr4_0_cached_addr_lim(), + .m_plic_addr_range(soc_map$m_plic_addr_range), + .m_near_mem_io_addr_range(soc_map$m_near_mem_io_addr_range), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), @@ -2729,6 +4107,177 @@ module mkCore(CLK, .m_mtvec_reset_value(), .m_nmivec_reset_value()); + // submodule ssNoSynth_0_ar_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_0_ar_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_ar_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_ar_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_ar_buffer_ff$DEQ), + .CLR(ssNoSynth_0_ar_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_ar_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_ar_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_ar_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_ar_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_ar_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_ar_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_ar_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_ar_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_0_aw_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_0_aw_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_aw_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_aw_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_aw_buffer_ff$DEQ), + .CLR(ssNoSynth_0_aw_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_aw_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_aw_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_aw_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_aw_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_aw_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_aw_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_aw_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_aw_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_0_w_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_0_w_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_0_w_buffer_ff$D_IN), + .ENQ(ssNoSynth_0_w_buffer_ff$ENQ), + .DEQ(ssNoSynth_0_w_buffer_ff$DEQ), + .CLR(ssNoSynth_0_w_buffer_ff$CLR), + .D_OUT(ssNoSynth_0_w_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_0_w_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_0_w_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_0_w_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_0_w_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_0_w_buffer_firstValid$D_IN), + .EN(ssNoSynth_0_w_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_0_w_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_ar_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_1_ar_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_ar_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_ar_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_ar_buffer_ff$DEQ), + .CLR(ssNoSynth_1_ar_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_ar_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_ar_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_ar_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_ar_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_ar_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_ar_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_ar_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_ar_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_aw_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_1_aw_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_aw_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_aw_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_aw_buffer_ff$DEQ), + .CLR(ssNoSynth_1_aw_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_aw_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_aw_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_aw_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_aw_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_aw_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_aw_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_aw_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_aw_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_1_w_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_1_w_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_1_w_buffer_ff$D_IN), + .ENQ(ssNoSynth_1_w_buffer_ff$ENQ), + .DEQ(ssNoSynth_1_w_buffer_ff$DEQ), + .CLR(ssNoSynth_1_w_buffer_ff$CLR), + .D_OUT(ssNoSynth_1_w_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_1_w_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_1_w_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_1_w_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_1_w_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_1_w_buffer_firstValid$D_IN), + .EN(ssNoSynth_1_w_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_1_w_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_ar_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_2_ar_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_ar_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_ar_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_ar_buffer_ff$DEQ), + .CLR(ssNoSynth_2_ar_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_ar_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_ar_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_ar_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_ar_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_ar_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_ar_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_ar_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_ar_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_aw_buffer_ff + FIFO1 #(.width(32'd98), + .guarded(32'd0)) ssNoSynth_2_aw_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_aw_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_aw_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_aw_buffer_ff$DEQ), + .CLR(ssNoSynth_2_aw_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_aw_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_aw_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_aw_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_aw_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_aw_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_aw_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_aw_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_aw_buffer_firstValid$Q_OUT)); + + // submodule ssNoSynth_2_w_buffer_ff + FIFO1 #(.width(32'd73), + .guarded(32'd0)) ssNoSynth_2_w_buffer_ff(.RST(RST_N), + .CLK(CLK), + .D_IN(ssNoSynth_2_w_buffer_ff$D_IN), + .ENQ(ssNoSynth_2_w_buffer_ff$ENQ), + .DEQ(ssNoSynth_2_w_buffer_ff$DEQ), + .CLR(ssNoSynth_2_w_buffer_ff$CLR), + .D_OUT(ssNoSynth_2_w_buffer_ff$D_OUT), + .FULL_N(ssNoSynth_2_w_buffer_ff$FULL_N), + .EMPTY_N(ssNoSynth_2_w_buffer_ff$EMPTY_N)); + + // submodule ssNoSynth_2_w_buffer_firstValid + RevertReg #(.width(32'd1), + .init(1'd1)) ssNoSynth_2_w_buffer_firstValid(.CLK(CLK), + .D_IN(ssNoSynth_2_w_buffer_firstValid$D_IN), + .EN(ssNoSynth_2_w_buffer_firstValid$EN), + .Q_OUT(ssNoSynth_2_w_buffer_firstValid$Q_OUT)); + // submodule tv_encode mkTV_Encode tv_encode(.CLK(CLK), .RST_N(RST_N), @@ -2766,29 +4315,20 @@ module mkCore(CLK, assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; - // rule RL_rl_wr_addr_channel - assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ; - - // rule RL_rl_wr_data_channel - assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ; - - // rule RL_rl_rd_addr_channel - assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ; - - // rule RL_rl_rd_data_channel - assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ; - // rule RL_ClientServerRequest_1 assign CAN_FIRE_RL_ClientServerRequest_1 = - dm_gpr_tap_ifc$RDY_server_request_put && - debug_module$RDY_hart0_gpr_mem_client_request_get ; + debug_module$RDY_hart0_gpr_mem_client_request_get && + dm_gpr_tap_ifc$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_1 = CAN_FIRE_RL_ClientServerRequest_1 ; + // rule RL_ClientServerResponse_1 + assign CAN_FIRE_RL_ClientServerResponse_1 = + debug_module$RDY_hart0_gpr_mem_client_response_put && + dm_gpr_tap_ifc$RDY_server_response_get ; + assign WILL_FIRE_RL_ClientServerResponse_1 = + CAN_FIRE_RL_ClientServerResponse_1 ; + // rule RL_ClientServerRequest_2 assign CAN_FIRE_RL_ClientServerRequest_2 = dm_gpr_tap_ifc$RDY_client_request_get && @@ -2796,13 +4336,6 @@ module mkCore(CLK, assign WILL_FIRE_RL_ClientServerRequest_2 = CAN_FIRE_RL_ClientServerRequest_2 ; - // rule RL_ClientServerResponse_1 - assign CAN_FIRE_RL_ClientServerResponse_1 = - dm_gpr_tap_ifc$RDY_server_response_get && - debug_module$RDY_hart0_gpr_mem_client_response_put ; - assign WILL_FIRE_RL_ClientServerResponse_1 = - CAN_FIRE_RL_ClientServerResponse_1 ; - // rule RL_ClientServerResponse_2 assign CAN_FIRE_RL_ClientServerResponse_2 = dm_gpr_tap_ifc$RDY_client_response_put && @@ -2819,15 +4352,15 @@ module mkCore(CLK, // rule RL_ClientServerRequest_3 assign CAN_FIRE_RL_ClientServerRequest_3 = - dm_csr_tap$RDY_server_request_put && - debug_module$RDY_hart0_csr_mem_client_request_get ; + debug_module$RDY_hart0_csr_mem_client_request_get && + dm_csr_tap$RDY_server_request_put ; assign WILL_FIRE_RL_ClientServerRequest_3 = CAN_FIRE_RL_ClientServerRequest_3 ; // rule RL_ClientServerResponse_3 assign CAN_FIRE_RL_ClientServerResponse_3 = - dm_csr_tap$RDY_server_response_get && - debug_module$RDY_hart0_csr_mem_client_response_put ; + debug_module$RDY_hart0_csr_mem_client_response_put && + dm_csr_tap$RDY_server_response_get ; assign WILL_FIRE_RL_ClientServerResponse_3 = CAN_FIRE_RL_ClientServerResponse_3 ; @@ -2869,85 +4402,942 @@ module mkCore(CLK, CAN_FIRE_RL_merge_dm_csr_trace_data && !WILL_FIRE_RL_merge_dm_gpr_trace_data ; - // rule RL_rl_wr_addr_channel_1 - assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ; - - // rule RL_rl_wr_data_channel_1 - assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_response_channel_1 - assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_1 - assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ; - - // rule RL_rl_rd_data_channel_1 - assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_2 - assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ; - - // rule RL_rl_wr_data_channel_2 - assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_response_channel_2 - assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_2 - assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ; - - // rule RL_rl_rd_data_channel_2 - assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_3 - assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ; - - // rule RL_rl_wr_data_channel_3 - assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_response_channel_3 - assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_3 - assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ; - - // rule RL_rl_rd_data_channel_3 - assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ; - - // rule RL_rl_wr_addr_channel_4 - assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ; - - // rule RL_rl_wr_data_channel_4 - assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ; - - // rule RL_rl_wr_response_channel_4 - assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ; - - // rule RL_rl_rd_addr_channel_4 - assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ; - - // rule RL_rl_rd_data_channel_4 - assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; - assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ; + // rule RL_checkSinkReady + assign CAN_FIRE_RL_checkSinkReady = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady = 1'd1 ; + + // rule RL_checkSinkReady_1 + assign CAN_FIRE_RL_checkSinkReady_1 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_1 = 1'd1 ; + + // rule RL_checkSinkReady_2 + assign CAN_FIRE_RL_checkSinkReady_2 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_2 = 1'd1 ; + + // rule RL_craftReq + assign CAN_FIRE_RL_craftReq = + ifcs_0_innerRoute$EMPTY_N && ifcs_0_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq = CAN_FIRE_RL_craftReq ; + + // rule RL_craftReq_1 + assign CAN_FIRE_RL_craftReq_1 = + ifcs_1_innerRoute$EMPTY_N && ifcs_1_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_1 = CAN_FIRE_RL_craftReq_1 ; + + // rule RL_arbitrate + assign CAN_FIRE_RL_arbitrate = + (CAN_FIRE_RL_craftReq && reqWires_0$wget || + CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) && + !state ; + assign WILL_FIRE_RL_arbitrate = CAN_FIRE_RL_arbitrate ; + + // rule RL_source_selected + assign CAN_FIRE_RL_source_selected = + (!ifcs_0_innerRoute$EMPTY_N || ifcs_0_innerReq$EMPTY_N) && + !state && + MUX_activeSource_0$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected = CAN_FIRE_RL_source_selected ; + + // rule RL_burst + assign CAN_FIRE_RL_burst = + ifcs_0_innerReq$EMPTY_N && ifcs_0_innerRoute$EMPTY_N && + state_047_AND_activeSource_0_120_121_AND_ifcs__ETC___d1123 ; + assign WILL_FIRE_RL_burst = CAN_FIRE_RL_burst ; + + // rule RL_source_selected_1 + assign CAN_FIRE_RL_source_selected_1 = + (!ifcs_1_innerRoute$EMPTY_N || ifcs_1_innerReq$EMPTY_N) && + !state && + MUX_activeSource_1$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_1 = CAN_FIRE_RL_source_selected_1 ; + + // rule RL_burst_1 + assign CAN_FIRE_RL_burst_1 = + ifcs_1_innerReq$EMPTY_N && ifcs_1_innerRoute$EMPTY_N && + state_047_AND_activeSource_1_164_165_AND_ifcs__ETC___d1167 ; + assign WILL_FIRE_RL_burst_1 = CAN_FIRE_RL_burst_1 ; + + // rule __me_check_129 + assign CAN_FIRE___me_check_129 = 1'b1 ; + assign WILL_FIRE___me_check_129 = 1'b1 ; + + // rule __me_check_131 + assign CAN_FIRE___me_check_131 = 1'b1 ; + assign WILL_FIRE___me_check_131 = 1'b1 ; + + // rule RL_sink_selected + assign CAN_FIRE_RL_sink_selected = + IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992 && + flitToSink_0$whas ; + assign WILL_FIRE_RL_sink_selected = CAN_FIRE_RL_sink_selected ; + + // rule RL_sink_selected_1 + assign CAN_FIRE_RL_sink_selected_1 = + IF_split_1_flitLeft_03_EQ_0_04_THEN_ssNoSynth__ETC___d993 && + flitToSink_1$whas ; + assign WILL_FIRE_RL_sink_selected_1 = CAN_FIRE_RL_sink_selected_1 ; + + // rule RL_sink_selected_2 + assign CAN_FIRE_RL_sink_selected_2 = + IF_split_2_flitLeft_32_EQ_0_33_THEN_ssNoSynth__ETC___d994 && + flitToSink_2$whas ; + assign WILL_FIRE_RL_sink_selected_2 = CAN_FIRE_RL_sink_selected_2 ; + + // rule __me_check_133 + assign CAN_FIRE___me_check_133 = 1'b1 ; + assign WILL_FIRE___me_check_133 = 1'b1 ; + + // rule RL_checkSinkReady_5 + assign CAN_FIRE_RL_checkSinkReady_5 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_5 = 1'd1 ; + + // rule RL_checkSinkReady_6 + assign CAN_FIRE_RL_checkSinkReady_6 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_6 = 1'd1 ; + + // rule RL_checkSinkReady_7 + assign CAN_FIRE_RL_checkSinkReady_7 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_7 = 1'd1 ; + + // rule RL_craftReq_5 + assign CAN_FIRE_RL_craftReq_5 = + ifcs_0_1_innerRoute$EMPTY_N && ifcs_0_1_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_5 = CAN_FIRE_RL_craftReq_5 ; + + // rule RL_craftReq_6 + assign CAN_FIRE_RL_craftReq_6 = + ifcs_1_1_innerRoute$EMPTY_N && ifcs_1_1_innerReq$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_6 = CAN_FIRE_RL_craftReq_6 ; + + // rule RL_arbitrate_2 + assign CAN_FIRE_RL_arbitrate_2 = + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget || + CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) && + !state_1_1 ; + assign WILL_FIRE_RL_arbitrate_2 = CAN_FIRE_RL_arbitrate_2 ; + + // rule RL_source_selected_5 + assign CAN_FIRE_RL_source_selected_5 = + (!ifcs_0_1_innerRoute$EMPTY_N || ifcs_0_1_innerReq$EMPTY_N) && + !state_1_1 && + sourceSelect_1_0_1$whas ; + assign WILL_FIRE_RL_source_selected_5 = CAN_FIRE_RL_source_selected_5 ; + + // rule RL_burst_5 + assign CAN_FIRE_RL_burst_5 = + ifcs_0_1_innerReq$EMPTY_N && ifcs_0_1_innerRoute$EMPTY_N && + state_1_1_685_AND_activeSource_1_0_1_752_753_A_ETC___d1755 ; + assign WILL_FIRE_RL_burst_5 = CAN_FIRE_RL_burst_5 ; + + // rule RL_source_selected_6 + assign CAN_FIRE_RL_source_selected_6 = + (!ifcs_1_1_innerRoute$EMPTY_N || ifcs_1_1_innerReq$EMPTY_N) && + !state_1_1 && + sourceSelect_1_1_1$whas ; + assign WILL_FIRE_RL_source_selected_6 = CAN_FIRE_RL_source_selected_6 ; + + // rule RL_burst_6 + assign CAN_FIRE_RL_burst_6 = + ifcs_1_1_innerReq$EMPTY_N && ifcs_1_1_innerRoute$EMPTY_N && + state_1_1_685_AND_activeSource_1_1_1_792_793_A_ETC___d1795 ; + assign WILL_FIRE_RL_burst_6 = CAN_FIRE_RL_burst_6 ; + + // rule __me_check_176 + assign CAN_FIRE___me_check_176 = 1'b1 ; + assign WILL_FIRE___me_check_176 = 1'b1 ; + + // rule __me_check_178 + assign CAN_FIRE___me_check_178 = 1'b1 ; + assign WILL_FIRE___me_check_178 = 1'b1 ; + + // rule RL_sink_selected_5 + assign CAN_FIRE_RL_sink_selected_5 = + ssNoSynth_0_ar_buffer_ff$FULL_N && flitToSink_1_0_1$whas ; + assign WILL_FIRE_RL_sink_selected_5 = CAN_FIRE_RL_sink_selected_5 ; + + // rule RL_sink_selected_6 + assign CAN_FIRE_RL_sink_selected_6 = + ssNoSynth_1_ar_buffer_ff$FULL_N && flitToSink_1_1_1$whas ; + assign WILL_FIRE_RL_sink_selected_6 = CAN_FIRE_RL_sink_selected_6 ; + + // rule RL_sink_selected_7 + assign CAN_FIRE_RL_sink_selected_7 = + ssNoSynth_2_ar_buffer_ff$FULL_N && flitToSink_1_2$whas ; + assign WILL_FIRE_RL_sink_selected_7 = CAN_FIRE_RL_sink_selected_7 ; + + // rule __me_check_180 + assign CAN_FIRE___me_check_180 = 1'b1 ; + assign WILL_FIRE___me_check_180 = 1'b1 ; + + // rule RL_ssNoSynth_0_ar_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit = + !shim_arff$FULL_N || + ssNoSynth_0_ar_buffer_firstValid$Q_OUT && + (ssNoSynth_0_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_5) ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_ar_forwardFlit ; + + // rule RL_ssNoSynth_0_ar_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit = + (ssNoSynth_0_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_5) && + shim_arff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit ; + + // rule RL_ssNoSynth_0_ar_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = + CAN_FIRE_RL_sink_selected_5 && + (!CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit || + ssNoSynth_0_ar_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; + + // rule RL_ssNoSynth_0_ar_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit && + ssNoSynth_0_ar_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; + + // rule RL_ssNoSynth_1_ar_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit = + ssNoSynth_1_ar_buffer_firstValid$Q_OUT && + (ssNoSynth_1_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_6) ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; + + // rule RL_ssNoSynth_1_ar_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit = + (ssNoSynth_1_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_6) && + near_mem_io$axi4_slave_arready ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + + // rule RL_ssNoSynth_1_ar_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = + CAN_FIRE_RL_sink_selected_6 && + (!CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit || + ssNoSynth_1_ar_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; + + // rule RL_ssNoSynth_1_ar_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit && + ssNoSynth_1_ar_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; + + // rule RL_ssNoSynth_2_ar_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit = + ssNoSynth_2_ar_buffer_firstValid$Q_OUT && + (ssNoSynth_2_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_7) ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; + + // rule RL_ssNoSynth_2_ar_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit = + (ssNoSynth_2_ar_buffer_ff$EMPTY_N || + CAN_FIRE_RL_sink_selected_7) && + plic$axi4_slave_arready ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + + // rule RL_ssNoSynth_2_ar_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = + CAN_FIRE_RL_sink_selected_7 && + (!CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit || + ssNoSynth_2_ar_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; + + // rule RL_ssNoSynth_2_ar_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit && + ssNoSynth_2_ar_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; + + // rule RL_split_0_putFirst + assign CAN_FIRE_RL_split_0_putFirst = + split_0_doPut_whas__66_AND_split_0_doPut_wget__ETC___d673 && + split_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_0_putFirst = CAN_FIRE_RL_split_0_putFirst ; + + // rule RL_ssNoSynth_0_aw_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit = + !shim_awff$FULL_N || + ssNoSynth_0_aw_buffer_firstValid$Q_OUT && + (ssNoSynth_0_aw_buffer_ff$EMPTY_N || + MUX_split_0_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_aw_forwardFlit ; + + // rule RL_ssNoSynth_0_aw_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit = + (ssNoSynth_0_aw_buffer_ff$EMPTY_N || + MUX_split_0_flitLeft$write_1__SEL_2) && + shim_awff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit ; + + // rule RL_ssNoSynth_0_aw_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = + MUX_split_0_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit || + ssNoSynth_0_aw_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; + + // rule RL_ssNoSynth_0_aw_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit && + ssNoSynth_0_aw_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; + + // rule RL_split_0_putOther + assign CAN_FIRE_RL_split_0_putOther = + CAN_FIRE_RL_sink_selected && + (!split_0_doPut$wget[171] || ssNoSynth_0_w_buffer_ff$FULL_N) && + split_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_0_putOther = CAN_FIRE_RL_split_0_putOther ; + + // rule RL_ssNoSynth_0_w_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit = + !shim_wff$FULL_N || + ssNoSynth_0_w_buffer_firstValid$Q_OUT && + (ssNoSynth_0_w_buffer_ff$EMPTY_N || + ssNoSynth_0_w_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit = + CAN_FIRE_RL_ssNoSynth_0_w_forwardFlit ; + + // rule RL_ssNoSynth_0_w_dropFlit + assign CAN_FIRE_RL_ssNoSynth_0_w_dropFlit = + (ssNoSynth_0_w_buffer_ff$EMPTY_N || + ssNoSynth_0_w_buffer_enqw$whas) && + shim_wff$FULL_N ; + assign WILL_FIRE_RL_ssNoSynth_0_w_dropFlit = + CAN_FIRE_RL_ssNoSynth_0_w_dropFlit ; + + // rule RL_ssNoSynth_0_w_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = + ssNoSynth_0_w_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_0_w_dropFlit || + ssNoSynth_0_w_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; + + // rule RL_ssNoSynth_0_w_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_w_dropFlit && + ssNoSynth_0_w_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_0_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; + + // rule RL_split_1_putFirst + assign CAN_FIRE_RL_split_1_putFirst = + split_1_doPut_whas__95_AND_split_1_doPut_wget__ETC___d702 && + split_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_1_putFirst = CAN_FIRE_RL_split_1_putFirst ; + + // rule RL_ssNoSynth_1_aw_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit = + ssNoSynth_1_aw_buffer_firstValid$Q_OUT && + (ssNoSynth_1_aw_buffer_ff$EMPTY_N || + MUX_split_1_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; + + // rule RL_ssNoSynth_1_aw_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit = + (ssNoSynth_1_aw_buffer_ff$EMPTY_N || + MUX_split_1_flitLeft$write_1__SEL_2) && + near_mem_io$axi4_slave_awready ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + + // rule RL_ssNoSynth_1_aw_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = + MUX_split_1_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit || + ssNoSynth_1_aw_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; + + // rule RL_ssNoSynth_1_aw_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit && + ssNoSynth_1_aw_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; + + // rule RL_split_1_putOther + assign CAN_FIRE_RL_split_1_putOther = + CAN_FIRE_RL_sink_selected_1 && + (!split_1_doPut$wget[171] || ssNoSynth_1_w_buffer_ff$FULL_N) && + split_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_1_putOther = CAN_FIRE_RL_split_1_putOther ; + + // rule RL_ssNoSynth_1_w_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit = + ssNoSynth_1_w_buffer_firstValid$Q_OUT && + (ssNoSynth_1_w_buffer_ff$EMPTY_N || + ssNoSynth_1_w_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_1_w_forwardFlit = + CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; + + // rule RL_ssNoSynth_1_w_dropFlit + assign CAN_FIRE_RL_ssNoSynth_1_w_dropFlit = + (ssNoSynth_1_w_buffer_ff$EMPTY_N || + ssNoSynth_1_w_buffer_enqw$whas) && + near_mem_io$axi4_slave_wready ; + assign WILL_FIRE_RL_ssNoSynth_1_w_dropFlit = + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + + // rule RL_ssNoSynth_1_w_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = + ssNoSynth_1_w_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_1_w_dropFlit || + ssNoSynth_1_w_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; + + // rule RL_ssNoSynth_1_w_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit && + ssNoSynth_1_w_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_1_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; + + // rule RL_split_2_putFirst + assign CAN_FIRE_RL_split_2_putFirst = + split_2_doPut_whas__24_AND_split_2_doPut_wget__ETC___d731 && + split_2_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_split_2_putFirst = CAN_FIRE_RL_split_2_putFirst ; + + // rule RL_ssNoSynth_2_aw_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit = + ssNoSynth_2_aw_buffer_firstValid$Q_OUT && + (ssNoSynth_2_aw_buffer_ff$EMPTY_N || + MUX_split_2_flitLeft$write_1__SEL_2) ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; + + // rule RL_ssNoSynth_2_aw_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit = + (ssNoSynth_2_aw_buffer_ff$EMPTY_N || + MUX_split_2_flitLeft$write_1__SEL_2) && + plic$axi4_slave_awready ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + + // rule RL_ssNoSynth_2_aw_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = + MUX_split_2_flitLeft$write_1__SEL_2 && + (!CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit || + ssNoSynth_2_aw_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; + + // rule RL_ssNoSynth_2_aw_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit && + ssNoSynth_2_aw_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; + + // rule RL_split_2_putOther + assign CAN_FIRE_RL_split_2_putOther = + CAN_FIRE_RL_sink_selected_2 && + (!split_2_doPut$wget[171] || ssNoSynth_2_w_buffer_ff$FULL_N) && + split_2_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_split_2_putOther = CAN_FIRE_RL_split_2_putOther ; + + // rule RL_ssNoSynth_2_w_forwardFlit + assign CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit = + ssNoSynth_2_w_buffer_firstValid$Q_OUT && + (ssNoSynth_2_w_buffer_ff$EMPTY_N || + ssNoSynth_2_w_buffer_enqw$whas) ; + assign WILL_FIRE_RL_ssNoSynth_2_w_forwardFlit = + CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; + + // rule RL_ssNoSynth_2_w_dropFlit + assign CAN_FIRE_RL_ssNoSynth_2_w_dropFlit = + (ssNoSynth_2_w_buffer_ff$EMPTY_N || + ssNoSynth_2_w_buffer_enqw$whas) && + plic$axi4_slave_wready ; + assign WILL_FIRE_RL_ssNoSynth_2_w_dropFlit = + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + + // rule RL_ssNoSynth_2_w_buffer_enqueue + assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = + ssNoSynth_2_w_buffer_enqw$whas && + (!CAN_FIRE_RL_ssNoSynth_2_w_dropFlit || + ssNoSynth_2_w_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_enqueue = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; + + // rule RL_ssNoSynth_2_w_buffer_dequeue + assign CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit && + ssNoSynth_2_w_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_ssNoSynth_2_w_buffer_dequeue = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; + + // rule RL_ifcs_0_firstFlit + assign CAN_FIRE_RL_ifcs_0_firstFlit = + cpu$dmem_master_wvalid && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 && + ifcs_0_innerReq$FULL_N && + ifcs_0_innerRoute$FULL_N && + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d760 || + cpu$dmem_master_awvalid) && + ifcs_0_state == 2'd0 && + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d783 + + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d787 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_firstFlit = CAN_FIRE_RL_ifcs_0_firstFlit ; + + // rule RL_ifcs_0_followFlits + assign CAN_FIRE_RL_ifcs_0_followFlits = + cpu$dmem_master_wvalid && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 && + ifcs_0_innerReq$FULL_N && + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d760 || + cpu$dmem_master_awvalid) && + ifcs_0_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_followFlits = CAN_FIRE_RL_ifcs_0_followFlits ; + + // rule RL_ifcs_0_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_0_nonRoutableFlit = + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d821 && + ifcs_0_state == 2'd0 && + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d783 + + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d787 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_nonRoutableFlit = + CAN_FIRE_RL_ifcs_0_nonRoutableFlit ; + + // rule RL_ifcs_0_drainFlits + assign CAN_FIRE_RL_ifcs_0_drainFlits = + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 && + cpu$dmem_master_wvalid && + ifcs_0_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_0_drainFlits = CAN_FIRE_RL_ifcs_0_drainFlits ; + + // rule __me_check_105 + assign CAN_FIRE___me_check_105 = 1'b1 ; + assign WILL_FIRE___me_check_105 = 1'b1 ; + + // rule RL_ifcs_0_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_drainNoRouteResponse = + msNoSynth_0_b_buffer_ff$FULL_N && ifcs_0_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + + // rule RL_checkSinkReady_3 + assign CAN_FIRE_RL_checkSinkReady_3 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_3 = 1'd1 ; + + // rule RL_ifcs_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_drainNoRouteResponse = + msNoSynth_1_b_buffer_ff$FULL_N && ifcs_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + + // rule RL_checkSinkReady_4 + assign CAN_FIRE_RL_checkSinkReady_4 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_4 = 1'd1 ; + + // rule RL_craftReq_2 + assign CAN_FIRE_RL_craftReq_2 = + ifcs_0_routeBack$EMPTY_N && ifcs_0_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_2 = CAN_FIRE_RL_craftReq_2 ; + + // rule RL_craftReq_3 + assign CAN_FIRE_RL_craftReq_3 = + ifcs_1_routeBack$EMPTY_N && ifcs_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_3 = CAN_FIRE_RL_craftReq_3 ; + + // rule RL_craftReq_4 + assign CAN_FIRE_RL_craftReq_4 = + ifcs_2_routeBack$EMPTY_N && ifcs_2_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_4 = CAN_FIRE_RL_craftReq_4 ; + + // rule RL_arbitrate_1 + assign CAN_FIRE_RL_arbitrate_1 = + reqWires_1_0_whas__226_AND_reqWires_1_0_wget___ETC___d1236 && + !state_1 ; + assign WILL_FIRE_RL_arbitrate_1 = CAN_FIRE_RL_arbitrate_1 ; + + // rule RL_source_selected_2 + assign CAN_FIRE_RL_source_selected_2 = + (!ifcs_0_routeBack$EMPTY_N || ifcs_0_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_0$whas ; + assign WILL_FIRE_RL_source_selected_2 = CAN_FIRE_RL_source_selected_2 ; + + // rule RL_burst_2 + assign CAN_FIRE_RL_burst_2 = + ifcs_0_rspBack$EMPTY_N && ifcs_0_routeBack$EMPTY_N && + state_1_237_AND_activeSource_1_0_325_326_AND_i_ETC___d1328 ; + assign WILL_FIRE_RL_burst_2 = CAN_FIRE_RL_burst_2 ; + + // rule RL_source_selected_3 + assign CAN_FIRE_RL_source_selected_3 = + (!ifcs_1_routeBack$EMPTY_N || ifcs_1_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_1$whas ; + assign WILL_FIRE_RL_source_selected_3 = CAN_FIRE_RL_source_selected_3 ; + + // rule RL_burst_3 + assign CAN_FIRE_RL_burst_3 = + ifcs_1_rspBack$EMPTY_N && ifcs_1_routeBack$EMPTY_N && + state_1_237_AND_activeSource_1_1_358_359_AND_i_ETC___d1361 ; + assign WILL_FIRE_RL_burst_3 = CAN_FIRE_RL_burst_3 ; + + // rule __me_check_144 + assign CAN_FIRE___me_check_144 = 1'b1 ; + assign WILL_FIRE___me_check_144 = 1'b1 ; + + // rule RL_source_selected_4 + assign CAN_FIRE_RL_source_selected_4 = + (!ifcs_2_routeBack$EMPTY_N || ifcs_2_rspBack$EMPTY_N) && + !state_1 && + sourceSelect_1_2$whas ; + assign WILL_FIRE_RL_source_selected_4 = CAN_FIRE_RL_source_selected_4 ; + + // rule RL_burst_4 + assign CAN_FIRE_RL_burst_4 = + ifcs_2_rspBack$EMPTY_N && ifcs_2_routeBack$EMPTY_N && + state_1_237_AND_activeSource_1_2_392_393_AND_i_ETC___d1395 ; + assign WILL_FIRE_RL_burst_4 = CAN_FIRE_RL_burst_4 ; + + // rule __me_check_142 + assign CAN_FIRE___me_check_142 = 1'b1 ; + assign WILL_FIRE___me_check_142 = 1'b1 ; + + // rule __me_check_146 + assign CAN_FIRE___me_check_146 = 1'b1 ; + assign WILL_FIRE___me_check_146 = 1'b1 ; + + // rule RL_sink_selected_3 + assign CAN_FIRE_RL_sink_selected_3 = + !CAN_FIRE_RL_ifcs_0_drainNoRouteResponse && flitToSink_1_0$whas ; + assign WILL_FIRE_RL_sink_selected_3 = CAN_FIRE_RL_sink_selected_3 ; + + // rule RL_sink_selected_4 + assign CAN_FIRE_RL_sink_selected_4 = + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse && flitToSink_1_1$whas ; + assign WILL_FIRE_RL_sink_selected_4 = CAN_FIRE_RL_sink_selected_4 ; + + // rule __me_check_148 + assign CAN_FIRE___me_check_148 = 1'b1 ; + assign WILL_FIRE___me_check_148 = 1'b1 ; + + // rule RL_ifcs_0_forwardRsp + assign CAN_FIRE_RL_ifcs_0_forwardRsp = + msNoSynth_0_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_3 && + !ifcs_0_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_forwardRsp = CAN_FIRE_RL_ifcs_0_forwardRsp ; + + // rule RL_msNoSynth_0_b_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_b_forwardFlit = + msNoSynth_0_b_buffer_firstValid$Q_OUT && + (msNoSynth_0_b_buffer_ff$EMPTY_N || + msNoSynth_0_b_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_0_b_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_b_forwardFlit ; + + // rule RL_msNoSynth_0_b_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_b_dropFlit = + (msNoSynth_0_b_buffer_ff$EMPTY_N || + msNoSynth_0_b_buffer_enqw$whas) && + cpu$dmem_master_bready ; + assign WILL_FIRE_RL_msNoSynth_0_b_dropFlit = + CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; + + // rule RL_msNoSynth_0_b_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue = + msNoSynth_0_b_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_0_b_dropFlit || + msNoSynth_0_b_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_b_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; + + // rule RL_msNoSynth_0_b_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_b_dropFlit && + msNoSynth_0_b_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; + + // rule RL_ifcs_0_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp = + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 && + ifcs_0_noRoute_inner_pendingReq$port1__read && + ifcs_0_noRouteRsp$FULL_N && + cpu$dmem_master_wvalid ; + assign WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; + + // rule __me_check_103 + assign CAN_FIRE___me_check_103 = 1'b1 ; + assign WILL_FIRE___me_check_103 = 1'b1 ; + + // rule __me_check_104 + assign CAN_FIRE___me_check_104 = 1'b1 ; + assign WILL_FIRE___me_check_104 = 1'b1 ; + + // rule __me_check_107 + assign CAN_FIRE___me_check_107 = 1'b1 ; + assign WILL_FIRE___me_check_107 = 1'b1 ; + + // rule RL_merged_0_genFirst + assign CAN_FIRE_RL_merged_0_genFirst = + cpu$dmem_master_awvalid && cpu$dmem_master_wvalid && + merged_0_doDrop$whas && + merged_0_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_0_genFirst = CAN_FIRE_RL_merged_0_genFirst ; + + // rule RL_msNoSynth_0_aw_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_aw_forwardReady = 1'd1 ; + + // rule RL_merged_0_genOther + assign CAN_FIRE_RL_merged_0_genOther = + cpu$dmem_master_wvalid && merged_0_doDrop$whas && + merged_0_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_0_genOther = CAN_FIRE_RL_merged_0_genOther ; + + // rule RL_msNoSynth_0_w_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_w_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_forwardRsp + assign CAN_FIRE_RL_ifcs_1_forwardRsp = + msNoSynth_1_b_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_4 && + !ifcs_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_forwardRsp = CAN_FIRE_RL_ifcs_1_forwardRsp ; + + // rule RL_msNoSynth_1_b_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_b_forwardFlit = + msNoSynth_1_b_buffer_firstValid$Q_OUT && + (msNoSynth_1_b_buffer_ff$EMPTY_N || + msNoSynth_1_b_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_1_b_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; + + // rule RL_msNoSynth_1_b_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_b_dropFlit = + (msNoSynth_1_b_buffer_ff$EMPTY_N || + msNoSynth_1_b_buffer_enqw$whas) && + dm_mem_tap$master_bready ; + assign WILL_FIRE_RL_msNoSynth_1_b_dropFlit = + CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; + + // rule RL_connect_bflit + assign CAN_FIRE_RL_connect_bflit = dm_mem_tap$slave_bvalid ; + assign WILL_FIRE_RL_connect_bflit = dm_mem_tap$slave_bvalid ; + + // rule RL_connect_bready + assign CAN_FIRE_RL_connect_bready = 1'd1 ; + assign WILL_FIRE_RL_connect_bready = 1'd1 ; + + // rule RL_msNoSynth_1_b_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue = + msNoSynth_1_b_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_1_b_dropFlit || + msNoSynth_1_b_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_b_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; + + // rule RL_msNoSynth_1_b_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_b_dropFlit && + msNoSynth_1_b_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_b_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; + + // rule RL_ifcs_0_firstFlit_1 + assign CAN_FIRE_RL_ifcs_0_firstFlit_1 = + shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && + ifcs_0_routeBack$FULL_N && + !ifcs_0_state_1 ; + assign WILL_FIRE_RL_ifcs_0_firstFlit_1 = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; + + // rule RL_ifcs_0_followFlits_1 + assign CAN_FIRE_RL_ifcs_0_followFlits_1 = + shim_bff$EMPTY_N && ifcs_0_rspBack$FULL_N && ifcs_0_state_1 ; + assign WILL_FIRE_RL_ifcs_0_followFlits_1 = + CAN_FIRE_RL_ifcs_0_followFlits_1 ; + + // rule __me_check_117 + assign CAN_FIRE___me_check_117 = 1'b1 ; + assign WILL_FIRE___me_check_117 = 1'b1 ; + + // rule RL_ssNoSynth_0_b_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_b_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_firstFlit_1 + assign CAN_FIRE_RL_ifcs_1_firstFlit_1 = + near_mem_io$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ifcs_1_routeBack$FULL_N && + !ifcs_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_firstFlit_1 = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; + + // rule RL_ifcs_1_followFlits_1 + assign CAN_FIRE_RL_ifcs_1_followFlits_1 = + near_mem_io$axi4_slave_bvalid && ifcs_1_rspBack$FULL_N && + ifcs_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_followFlits_1 = + CAN_FIRE_RL_ifcs_1_followFlits_1 ; + + // rule __me_check_119 + assign CAN_FIRE___me_check_119 = 1'b1 ; + assign WILL_FIRE___me_check_119 = 1'b1 ; + + // rule RL_ssNoSynth_1_b_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_b_forwardReady = 1'd1 ; + + // rule RL_ifcs_0_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + msNoSynth_0_r_buffer_ff$FULL_N && ifcs_0_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + + // rule RL_checkSinkReady_8 + assign CAN_FIRE_RL_checkSinkReady_8 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_8 = 1'd1 ; + + // rule RL_ifcs_1_1_drainNoRouteResponse + assign CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + msNoSynth_1_r_buffer_ff$FULL_N && ifcs_1_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse = + CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + + // rule RL_checkSinkReady_9 + assign CAN_FIRE_RL_checkSinkReady_9 = 1'd1 ; + assign WILL_FIRE_RL_checkSinkReady_9 = 1'd1 ; + + // rule RL_craftReq_7 + assign CAN_FIRE_RL_craftReq_7 = + ifcs_0_1_routeBack$EMPTY_N && ifcs_0_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_7 = CAN_FIRE_RL_craftReq_7 ; + + // rule RL_craftReq_8 + assign CAN_FIRE_RL_craftReq_8 = + ifcs_1_1_routeBack$EMPTY_N && ifcs_1_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_8 = CAN_FIRE_RL_craftReq_8 ; + + // rule RL_craftReq_9 + assign CAN_FIRE_RL_craftReq_9 = + ifcs_2_1_routeBack$EMPTY_N && ifcs_2_1_rspBack$EMPTY_N ; + assign WILL_FIRE_RL_craftReq_9 = CAN_FIRE_RL_craftReq_9 ; + + // rule RL_arbitrate_3 + assign CAN_FIRE_RL_arbitrate_3 = + reqWires_1_1_0_whas__854_AND_reqWires_1_1_0_wg_ETC___d1864 && + !state_1_1_1 ; + assign WILL_FIRE_RL_arbitrate_3 = CAN_FIRE_RL_arbitrate_3 ; + + // rule RL_source_selected_7 + assign CAN_FIRE_RL_source_selected_7 = + (!ifcs_0_1_routeBack$EMPTY_N || ifcs_0_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_0$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_7 = CAN_FIRE_RL_source_selected_7 ; + + // rule RL_burst_7 + assign CAN_FIRE_RL_burst_7 = + ifcs_0_1_rspBack$EMPTY_N && ifcs_0_1_routeBack$EMPTY_N && + state_1_1_1_865_AND_activeSource_1_1_0_959_960_ETC___d1962 ; + assign WILL_FIRE_RL_burst_7 = CAN_FIRE_RL_burst_7 ; + + // rule RL_source_selected_8 + assign CAN_FIRE_RL_source_selected_8 = + (!ifcs_1_1_routeBack$EMPTY_N || ifcs_1_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_1_1$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_8 = CAN_FIRE_RL_source_selected_8 ; + + // rule RL_burst_8 + assign CAN_FIRE_RL_burst_8 = + ifcs_1_1_rspBack$EMPTY_N && ifcs_1_1_routeBack$EMPTY_N && + state_1_1_1_865_AND_activeSource_1_1_1_1_995_9_ETC___d1998 ; + assign WILL_FIRE_RL_burst_8 = CAN_FIRE_RL_burst_8 ; + + // rule __me_check_191 + assign CAN_FIRE___me_check_191 = 1'b1 ; + assign WILL_FIRE___me_check_191 = 1'b1 ; + + // rule RL_source_selected_9 + assign CAN_FIRE_RL_source_selected_9 = + (!ifcs_2_1_routeBack$EMPTY_N || ifcs_2_1_rspBack$EMPTY_N) && + !state_1_1_1 && + MUX_activeSource_1_1_2$write_1__VAL_1 ; + assign WILL_FIRE_RL_source_selected_9 = CAN_FIRE_RL_source_selected_9 ; + + // rule RL_burst_9 + assign CAN_FIRE_RL_burst_9 = + ifcs_2_1_rspBack$EMPTY_N && ifcs_2_1_routeBack$EMPTY_N && + state_1_1_1_865_AND_activeSource_1_1_2_031_032_ETC___d2034 ; + assign WILL_FIRE_RL_burst_9 = CAN_FIRE_RL_burst_9 ; + + // rule __me_check_189 + assign CAN_FIRE___me_check_189 = 1'b1 ; + assign WILL_FIRE___me_check_189 = 1'b1 ; + + // rule __me_check_193 + assign CAN_FIRE___me_check_193 = 1'b1 ; + assign WILL_FIRE___me_check_193 = 1'b1 ; + + // rule RL_sink_selected_8 + assign CAN_FIRE_RL_sink_selected_8 = + !CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse && + flitToSink_1_1_0$whas ; + assign WILL_FIRE_RL_sink_selected_8 = CAN_FIRE_RL_sink_selected_8 ; + + // rule RL_sink_selected_9 + assign CAN_FIRE_RL_sink_selected_9 = + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse && + flitToSink_1_1_1_1$whas ; + assign WILL_FIRE_RL_sink_selected_9 = CAN_FIRE_RL_sink_selected_9 ; + + // rule __me_check_195 + assign CAN_FIRE___me_check_195 = 1'b1 ; + assign WILL_FIRE___me_check_195 = 1'b1 ; + + // rule RL_ifcs_0_1_forwardRsp + assign CAN_FIRE_RL_ifcs_0_1_forwardRsp = + msNoSynth_0_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_8 && + !ifcs_0_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_0_1_forwardRsp = CAN_FIRE_RL_ifcs_0_1_forwardRsp ; + + // rule RL_msNoSynth_0_r_forwardFlit + assign CAN_FIRE_RL_msNoSynth_0_r_forwardFlit = + msNoSynth_0_r_buffer_firstValid$Q_OUT && + (msNoSynth_0_r_buffer_ff$EMPTY_N || + msNoSynth_0_r_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_0_r_forwardFlit = + CAN_FIRE_RL_msNoSynth_0_r_forwardFlit ; + + // rule RL_msNoSynth_0_r_dropFlit + assign CAN_FIRE_RL_msNoSynth_0_r_dropFlit = + (msNoSynth_0_r_buffer_ff$EMPTY_N || + msNoSynth_0_r_buffer_enqw$whas) && + cpu$dmem_master_rready ; + assign WILL_FIRE_RL_msNoSynth_0_r_dropFlit = + CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; // rule RL_rl_relay_sw_interrupts assign CAN_FIRE_RL_rl_relay_sw_interrupts = @@ -2968,17 +5358,15 @@ module mkCore(CLK, // rule RL_rl_cpu_hart0_reset_from_soc_start assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = near_mem_io$RDY_server_reset_request_put && - plic$RDY_server_reset_request_put && - fabric_2x3_RDY_reset_AND_cpu_RDY_hart0_server__ETC___d9 ; + plic_RDY_server_reset_request_put_AND_cpu_RDY__ETC___d8 ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; // rule RL_rl_cpu_hart0_reset_from_dm_start assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = + debug_module$RDY_hart0_reset_client_request_get && near_mem_io$RDY_server_reset_request_put && plic$RDY_server_reset_request_put && - fabric_2x3$RDY_reset && - debug_module$RDY_hart0_reset_client_request_get && cpu$RDY_hart0_server_reset_request_put && f_reset_requestor$FULL_N ; assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start = @@ -2997,50 +5385,1430 @@ module mkCore(CLK, assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; - // rule RL_rl_wr_response_channel - assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ; - assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ; - - // submodule cpu - assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ; - assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ; - assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ; - assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ; - assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ; - assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ; - assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ; - assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ; - assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ; - assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ; - assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ; - assign cpu$hart0_csr_mem_server_request_put = - dm_csr_tap$client_request_get ; - assign cpu$hart0_gpr_mem_server_request_put = - dm_gpr_tap_ifc$client_request_get ; - assign cpu$hart0_put_other_req_put = debug_module$hart0_get_other_req_get ; - assign cpu$hart0_server_reset_request_put = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ? - f_reset_reqs$D_OUT : - debug_module$hart0_reset_client_request_get ; - assign cpu$hart0_server_run_halt_request_put = - debug_module$hart0_client_run_halt_request_get ; - assign cpu$imem_master_arready = cpu_imem_master_arready ; - assign cpu$imem_master_awready = cpu_imem_master_awready ; - assign cpu$imem_master_bid = cpu_imem_master_bid ; - assign cpu$imem_master_bresp = cpu_imem_master_bresp ; - assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; - assign cpu$imem_master_rdata = cpu_imem_master_rdata ; - assign cpu$imem_master_rid = cpu_imem_master_rid ; - assign cpu$imem_master_rlast = cpu_imem_master_rlast ; - assign cpu$imem_master_rresp = cpu_imem_master_rresp ; - assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; - assign cpu$imem_master_wready = cpu_imem_master_wready ; - assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; - assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; - assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; - assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; - assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; - assign cpu$software_interrupt_req_set_not_clear = + // rule RL_msNoSynth_0_r_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue = + msNoSynth_0_r_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_0_r_dropFlit || + msNoSynth_0_r_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_0_r_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; + + // rule RL_msNoSynth_0_r_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_r_dropFlit && + msNoSynth_0_r_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_0_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; + + // rule RL_ifcs_2_firstFlit + assign CAN_FIRE_RL_ifcs_2_firstFlit = + plic$axi4_slave_bvalid && ifcs_2_rspBack$FULL_N && + ifcs_2_routeBack$FULL_N && + !ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_firstFlit = CAN_FIRE_RL_ifcs_2_firstFlit ; + + // rule RL_ifcs_2_followFlits + assign CAN_FIRE_RL_ifcs_2_followFlits = + plic$axi4_slave_bvalid && ifcs_2_rspBack$FULL_N && ifcs_2_state ; + assign WILL_FIRE_RL_ifcs_2_followFlits = CAN_FIRE_RL_ifcs_2_followFlits ; + + // rule __me_check_121 + assign CAN_FIRE___me_check_121 = 1'b1 ; + assign WILL_FIRE___me_check_121 = 1'b1 ; + + // rule RL_ssNoSynth_2_b_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_b_forwardReady = 1'd1 ; + + // rule RL_ifcs_0_1_firstFlit + assign CAN_FIRE_RL_ifcs_0_1_firstFlit = + cpu$dmem_master_arvalid && ifcs_0_1_innerReq$FULL_N && + ifcs_0_1_innerRoute$FULL_N && + ifcs_0_1_state == 2'd0 && + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1424 + + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1428 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_1_firstFlit = CAN_FIRE_RL_ifcs_0_1_firstFlit ; + + // rule RL_ifcs_0_1_followFlits + assign CAN_FIRE_RL_ifcs_0_1_followFlits = + cpu$dmem_master_arvalid && ifcs_0_1_innerReq$FULL_N && + ifcs_0_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_1_followFlits = + CAN_FIRE_RL_ifcs_0_1_followFlits ; + + // rule RL_ifcs_0_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit = + ifcs_0_1_noRoute_flitCount == 9'd0 && cpu$dmem_master_arvalid && + ifcs_0_1_state == 2'd0 && + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1424 + + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1428 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ; + + // rule RL_ifcs_0_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + x_port1__read__h55959 != 9'd0 && ifcs_0_1_noRouteRsp$FULL_N && + (x_port1__read__h55959 != 9'd1 || cpu$dmem_master_arvalid) ; + assign WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; + + // rule RL_ifcs_0_1_drainFlits + assign CAN_FIRE_RL_ifcs_0_1_drainFlits = + cpu$dmem_master_arvalid && ifcs_0_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_0_1_drainFlits = CAN_FIRE_RL_ifcs_0_1_drainFlits ; + + // rule __me_check_150 + assign CAN_FIRE___me_check_150 = 1'b1 ; + assign WILL_FIRE___me_check_150 = 1'b1 ; + + // rule __me_check_151 + assign CAN_FIRE___me_check_151 = 1'b1 ; + assign WILL_FIRE___me_check_151 = 1'b1 ; + + // rule __me_check_152 + assign CAN_FIRE___me_check_152 = 1'b1 ; + assign WILL_FIRE___me_check_152 = 1'b1 ; + + // rule __me_check_154 + assign CAN_FIRE___me_check_154 = 1'b1 ; + assign WILL_FIRE___me_check_154 = 1'b1 ; + + // rule RL_msNoSynth_0_ar_forwardReady + assign CAN_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_0_ar_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_1_forwardRsp + assign CAN_FIRE_RL_ifcs_1_1_forwardRsp = + msNoSynth_1_r_buffer_ff$FULL_N && CAN_FIRE_RL_sink_selected_9 && + !ifcs_1_1_noRouteRsp$EMPTY_N ; + assign WILL_FIRE_RL_ifcs_1_1_forwardRsp = CAN_FIRE_RL_ifcs_1_1_forwardRsp ; + + // rule RL_msNoSynth_1_r_forwardFlit + assign CAN_FIRE_RL_msNoSynth_1_r_forwardFlit = + msNoSynth_1_r_buffer_firstValid$Q_OUT && + (msNoSynth_1_r_buffer_ff$EMPTY_N || + msNoSynth_1_r_buffer_enqw$whas) ; + assign WILL_FIRE_RL_msNoSynth_1_r_forwardFlit = + CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; + + // rule RL_msNoSynth_1_r_dropFlit + assign CAN_FIRE_RL_msNoSynth_1_r_dropFlit = + (msNoSynth_1_r_buffer_ff$EMPTY_N || + msNoSynth_1_r_buffer_enqw$whas) && + dm_mem_tap$master_rready ; + assign WILL_FIRE_RL_msNoSynth_1_r_dropFlit = + CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; + + // rule RL_connect_rflit + assign CAN_FIRE_RL_connect_rflit = dm_mem_tap$slave_rvalid ; + assign WILL_FIRE_RL_connect_rflit = dm_mem_tap$slave_rvalid ; + + // rule RL_connect_rready + assign CAN_FIRE_RL_connect_rready = 1'd1 ; + assign WILL_FIRE_RL_connect_rready = 1'd1 ; + + // rule RL_connect_awflit + assign CAN_FIRE_RL_connect_awflit = debug_module$master_awvalid ; + assign WILL_FIRE_RL_connect_awflit = debug_module$master_awvalid ; + + // rule RL_connect_awready + assign CAN_FIRE_RL_connect_awready = 1'd1 ; + assign WILL_FIRE_RL_connect_awready = 1'd1 ; + + // rule RL_connect_wflit + assign CAN_FIRE_RL_connect_wflit = debug_module$master_wvalid ; + assign WILL_FIRE_RL_connect_wflit = debug_module$master_wvalid ; + + // rule RL_connect_wready + assign CAN_FIRE_RL_connect_wready = 1'd1 ; + assign WILL_FIRE_RL_connect_wready = 1'd1 ; + + // rule RL_connect_arflit + assign CAN_FIRE_RL_connect_arflit = debug_module$master_arvalid ; + assign WILL_FIRE_RL_connect_arflit = debug_module$master_arvalid ; + + // rule RL_connect_arready + assign CAN_FIRE_RL_connect_arready = 1'd1 ; + assign WILL_FIRE_RL_connect_arready = 1'd1 ; + + // rule RL_msNoSynth_1_r_buffer_enqueue + assign CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue = + msNoSynth_1_r_buffer_enqw$whas && + (!CAN_FIRE_RL_msNoSynth_1_r_dropFlit || + msNoSynth_1_r_buffer_ff$EMPTY_N) ; + assign WILL_FIRE_RL_msNoSynth_1_r_buffer_enqueue = + CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; + + // rule RL_msNoSynth_1_r_buffer_dequeue + assign CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_r_dropFlit && + msNoSynth_1_r_buffer_ff$EMPTY_N ; + assign WILL_FIRE_RL_msNoSynth_1_r_buffer_dequeue = + CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; + + // rule RL_ifcs_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_firstFlit = + dm_mem_tap$master_wvalid && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 && + ifcs_1_innerReq$FULL_N && + ifcs_1_innerRoute$FULL_N && + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d857 || + dm_mem_tap$master_awvalid) && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d880 + + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d884 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_firstFlit = CAN_FIRE_RL_ifcs_1_firstFlit ; + + // rule RL_ifcs_1_followFlits + assign CAN_FIRE_RL_ifcs_1_followFlits = + dm_mem_tap$master_wvalid && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 && + ifcs_1_innerReq$FULL_N && + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d857 || + dm_mem_tap$master_awvalid) && + ifcs_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_followFlits = CAN_FIRE_RL_ifcs_1_followFlits ; + + // rule RL_ifcs_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_nonRoutableFlit = + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d918 && + ifcs_1_state == 2'd0 && + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d880 + + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d884 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_nonRoutableFlit ; + + // rule RL_ifcs_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp = + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 && + ifcs_1_noRoute_inner_pendingReq$port1__read && + ifcs_1_noRouteRsp$FULL_N && + dm_mem_tap$master_wvalid ; + assign WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; + + // rule RL_ifcs_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_drainFlits = + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 && + dm_mem_tap$master_wvalid && + ifcs_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_drainFlits = CAN_FIRE_RL_ifcs_1_drainFlits ; + + // rule __me_check_110 + assign CAN_FIRE___me_check_110 = 1'b1 ; + assign WILL_FIRE___me_check_110 = 1'b1 ; + + // rule __me_check_111 + assign CAN_FIRE___me_check_111 = 1'b1 ; + assign WILL_FIRE___me_check_111 = 1'b1 ; + + // rule __me_check_112 + assign CAN_FIRE___me_check_112 = 1'b1 ; + assign WILL_FIRE___me_check_112 = 1'b1 ; + + // rule __me_check_114 + assign CAN_FIRE___me_check_114 = 1'b1 ; + assign WILL_FIRE___me_check_114 = 1'b1 ; + + // rule RL_merged_1_genFirst + assign CAN_FIRE_RL_merged_1_genFirst = + dm_mem_tap$master_awvalid && dm_mem_tap$master_wvalid && + merged_1_doDrop$whas && + merged_1_flitLeft == 8'd0 ; + assign WILL_FIRE_RL_merged_1_genFirst = CAN_FIRE_RL_merged_1_genFirst ; + + // rule RL_msNoSynth_1_aw_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_aw_forwardReady = 1'd1 ; + + // rule RL_merged_1_genOther + assign CAN_FIRE_RL_merged_1_genOther = + dm_mem_tap$master_wvalid && merged_1_doDrop$whas && + merged_1_flitLeft != 8'd0 ; + assign WILL_FIRE_RL_merged_1_genOther = CAN_FIRE_RL_merged_1_genOther ; + + // rule RL_msNoSynth_1_w_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_w_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_1_firstFlit + assign CAN_FIRE_RL_ifcs_1_1_firstFlit = + dm_mem_tap$master_arvalid && ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_innerRoute$FULL_N && + ifcs_1_1_state == 2'd0 && + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1510 + + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1514 == + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_firstFlit = CAN_FIRE_RL_ifcs_1_1_firstFlit ; + + // rule RL_ifcs_1_1_followFlits + assign CAN_FIRE_RL_ifcs_1_1_followFlits = + dm_mem_tap$master_arvalid && ifcs_1_1_innerReq$FULL_N && + ifcs_1_1_state == 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_followFlits = + CAN_FIRE_RL_ifcs_1_1_followFlits ; + + // rule RL_ifcs_1_1_nonRoutableFlit + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit = + ifcs_1_1_noRoute_flitCount == 9'd0 && + dm_mem_tap$master_arvalid && + ifcs_1_1_state == 2'd0 && + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1510 + + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1514 != + 2'd1 ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ; + + // rule RL_ifcs_1_1_nonRoutableGenRsp + assign CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + x_port1__read__h58381 != 9'd0 && ifcs_1_1_noRouteRsp$FULL_N && + (x_port1__read__h58381 != 9'd1 || dm_mem_tap$master_arvalid) ; + assign WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp = + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; + + // rule RL_ifcs_1_1_drainFlits + assign CAN_FIRE_RL_ifcs_1_1_drainFlits = + dm_mem_tap$master_arvalid && ifcs_1_1_state == 2'd2 ; + assign WILL_FIRE_RL_ifcs_1_1_drainFlits = CAN_FIRE_RL_ifcs_1_1_drainFlits ; + + // rule __me_check_157 + assign CAN_FIRE___me_check_157 = 1'b1 ; + assign WILL_FIRE___me_check_157 = 1'b1 ; + + // rule __me_check_158 + assign CAN_FIRE___me_check_158 = 1'b1 ; + assign WILL_FIRE___me_check_158 = 1'b1 ; + + // rule __me_check_159 + assign CAN_FIRE___me_check_159 = 1'b1 ; + assign WILL_FIRE___me_check_159 = 1'b1 ; + + // rule __me_check_161 + assign CAN_FIRE___me_check_161 = 1'b1 ; + assign WILL_FIRE___me_check_161 = 1'b1 ; + + // rule RL_msNoSynth_1_ar_forwardReady + assign CAN_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_msNoSynth_1_ar_forwardReady = 1'd1 ; + + // rule RL_ifcs_0_1_firstFlit_1 + assign CAN_FIRE_RL_ifcs_0_1_firstFlit_1 = + shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && + ifcs_0_1_routeBack$FULL_N && + !ifcs_0_1_state_1 ; + assign WILL_FIRE_RL_ifcs_0_1_firstFlit_1 = + CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; + + // rule RL_ifcs_0_1_followFlits_1 + assign CAN_FIRE_RL_ifcs_0_1_followFlits_1 = + shim_rff$EMPTY_N && ifcs_0_1_rspBack$FULL_N && ifcs_0_1_state_1 ; + assign WILL_FIRE_RL_ifcs_0_1_followFlits_1 = + CAN_FIRE_RL_ifcs_0_1_followFlits_1 ; + + // rule __me_check_164 + assign CAN_FIRE___me_check_164 = 1'b1 ; + assign WILL_FIRE___me_check_164 = 1'b1 ; + + // rule RL_ssNoSynth_0_r_forwardReady + assign CAN_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_0_r_forwardReady = 1'd1 ; + + // rule RL_ifcs_1_1_firstFlit_1 + assign CAN_FIRE_RL_ifcs_1_1_firstFlit_1 = + near_mem_io$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ifcs_1_1_routeBack$FULL_N && + !ifcs_1_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_1_firstFlit_1 = + CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; + + // rule RL_ifcs_1_1_followFlits_1 + assign CAN_FIRE_RL_ifcs_1_1_followFlits_1 = + near_mem_io$axi4_slave_rvalid && ifcs_1_1_rspBack$FULL_N && + ifcs_1_1_state_1 ; + assign WILL_FIRE_RL_ifcs_1_1_followFlits_1 = + CAN_FIRE_RL_ifcs_1_1_followFlits_1 ; + + // rule __me_check_166 + assign CAN_FIRE___me_check_166 = 1'b1 ; + assign WILL_FIRE___me_check_166 = 1'b1 ; + + // rule RL_ssNoSynth_1_r_forwardReady + assign CAN_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_1_r_forwardReady = 1'd1 ; + + // rule RL_ifcs_2_1_firstFlit + assign CAN_FIRE_RL_ifcs_2_1_firstFlit = + plic$axi4_slave_rvalid && ifcs_2_1_rspBack$FULL_N && + ifcs_2_1_routeBack$FULL_N && + !ifcs_2_1_state ; + assign WILL_FIRE_RL_ifcs_2_1_firstFlit = CAN_FIRE_RL_ifcs_2_1_firstFlit ; + + // rule RL_ifcs_2_1_followFlits + assign CAN_FIRE_RL_ifcs_2_1_followFlits = + plic$axi4_slave_rvalid && ifcs_2_1_rspBack$FULL_N && + ifcs_2_1_state ; + assign WILL_FIRE_RL_ifcs_2_1_followFlits = + CAN_FIRE_RL_ifcs_2_1_followFlits ; + + // rule __me_check_168 + assign CAN_FIRE___me_check_168 = 1'b1 ; + assign WILL_FIRE___me_check_168 = 1'b1 ; + + // rule RL_ssNoSynth_2_r_forwardReady + assign CAN_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; + assign WILL_FIRE_RL_ssNoSynth_2_r_forwardReady = 1'd1 ; + + // inputs to muxes for submodule ports + assign MUX_activeSource_0$write_1__SEL_1 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[0] ; + assign MUX_activeSource_1_1_0$write_1__SEL_1 = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[0] ; + assign MUX_activeSource_1_1_0$write_1__SEL_2 = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[0] ; + assign MUX_activeSource_1_1_0$write_1__SEL_3 = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[0] ; + assign MUX_flitToSink_0$wset_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_0$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1_0$wset_1__SEL_1 = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_2 = + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_3 = + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_0_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_1_0_1$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[0] ; + assign MUX_flitToSink_1_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_2 = + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_3 = + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_1 = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_2 = + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_3 = + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_0$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[0] ; + assign MUX_flitToSink_1_1_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1_1_1$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_1 = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_2 = + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_3 = + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_4 = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_5 = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_1_1_1$wset_1__SEL_6 = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[1] ; + assign MUX_flitToSink_1_2$wset_1__SEL_1 = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[2] ; + assign MUX_flitToSink_1_2$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[2] ; + assign MUX_flitToSink_2$wset_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[2] ; + assign MUX_flitToSink_2$wset_1__SEL_3 = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[2] ; + assign MUX_ifcs_0_1_state_1$write_1__SEL_1 = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 && shim_rff$D_OUT[0] ; + assign MUX_ifcs_0_state$write_1__PSEL_1 = + WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits ; + assign MUX_ifcs_0_state$write_1__SEL_1 = + MUX_ifcs_0_state$write_1__PSEL_1 && cpu$dmem_master_wlast ; + assign MUX_ifcs_0_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_0_firstFlit && !cpu$dmem_master_wlast ; + assign MUX_ifcs_0_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !cpu$dmem_master_wlast ; + assign MUX_ifcs_1_1_state_1$write_1__SEL_1 = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && + near_mem_io$axi4_slave_rlast ; + assign MUX_ifcs_1_state$write_1__PSEL_1 = + WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits ; + assign MUX_ifcs_1_state$write_1__SEL_1 = + MUX_ifcs_1_state$write_1__PSEL_1 && dm_mem_tap$master_wlast ; + assign MUX_ifcs_1_state$write_1__SEL_2 = + WILL_FIRE_RL_ifcs_1_firstFlit && !dm_mem_tap$master_wlast ; + assign MUX_ifcs_1_state$write_1__SEL_3 = + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && + !dm_mem_tap$master_wlast ; + assign MUX_ifcs_2_1_state$write_1__SEL_1 = + WILL_FIRE_RL_ifcs_2_1_followFlits && plic$axi4_slave_rlast ; + assign MUX_split_0_flitLeft$write_1__SEL_1 = + WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] ; + assign MUX_split_0_flitLeft$write_1__SEL_2 = + WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[171] ; + assign MUX_split_1_flitLeft$write_1__SEL_1 = + WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] ; + assign MUX_split_1_flitLeft$write_1__SEL_2 = + WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[171] ; + assign MUX_split_2_flitLeft$write_1__SEL_1 = + WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] ; + assign MUX_split_2_flitLeft$write_1__SEL_2 = + WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[171] ; + assign MUX_state$write_1__SEL_1 = + WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[0] ; + assign MUX_state$write_1__SEL_2 = + WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[0] ; + assign MUX_state_1_1_1$write_1__SEL_1 = + WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[0] ; + assign MUX_state_1_1_1$write_1__SEL_2 = + WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[0] ; + assign MUX_state_1_1_1$write_1__SEL_3 = + WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[0] ; + assign MUX_activeSource_0$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate && + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1074 ; + assign MUX_activeSource_1$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate && + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1078 ; + assign MUX_activeSource_1_1_0$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate_3 && + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1912 ; + assign MUX_activeSource_1_1_1_1$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate_3 && + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1918 ; + assign MUX_activeSource_1_1_2$write_1__VAL_1 = + WILL_FIRE_RL_arbitrate_3 && + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1924 ; + assign MUX_merged_0_flitLeft$write_1__VAL_1 = merged_0_flitLeft - 8'd1 ; + assign MUX_merged_1_flitLeft$write_1__VAL_1 = merged_1_flitLeft - 8'd1 ; + always@(MUX_flitToSink_1_0$wset_1__SEL_1 or + MUX_flitToSink_1_0$wset_1__SEL_4 or + ifcs_0_rspBack$D_OUT or + MUX_flitToSink_1_0$wset_1__SEL_2 or + MUX_flitToSink_1_0$wset_1__SEL_5 or + ifcs_1_rspBack$D_OUT or + MUX_flitToSink_1_0$wset_1__SEL_3 or + MUX_flitToSink_1_0$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_0$wset_1__SEL_1 || MUX_flitToSink_1_0$wset_1__SEL_4: + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_2 || MUX_flitToSink_1_0$wset_1__SEL_5: + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_0$wset_1__SEL_3 || MUX_flitToSink_1_0$wset_1__SEL_6: + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; + default: MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1 = + 6'b101010 /* unspecified value */ ; + endcase + end + always@(MUX_flitToSink_1_1_0$wset_1__SEL_1 or + MUX_flitToSink_1_1_0$wset_1__SEL_4 or + ifcs_0_1_rspBack$D_OUT or + MUX_flitToSink_1_1_0$wset_1__SEL_2 or + MUX_flitToSink_1_1_0$wset_1__SEL_5 or + ifcs_1_1_rspBack$D_OUT or + MUX_flitToSink_1_1_0$wset_1__SEL_3 or + MUX_flitToSink_1_1_0$wset_1__SEL_6 or ifcs_2_1_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1_0$wset_1__SEL_1 || + MUX_flitToSink_1_1_0$wset_1__SEL_4: + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1 = + ifcs_0_1_rspBack$D_OUT; + MUX_flitToSink_1_1_0$wset_1__SEL_2 || + MUX_flitToSink_1_1_0$wset_1__SEL_5: + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1 = + ifcs_1_1_rspBack$D_OUT; + MUX_flitToSink_1_1_0$wset_1__SEL_3 || + MUX_flitToSink_1_1_0$wset_1__SEL_6: + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1 = + ifcs_2_1_rspBack$D_OUT; + default: MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1 = + 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + always@(MUX_flitToSink_1_1$wset_1__SEL_1 or + MUX_flitToSink_1_1$wset_1__SEL_4 or + ifcs_0_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_2 or + MUX_flitToSink_1_1$wset_1__SEL_5 or + ifcs_1_rspBack$D_OUT or + MUX_flitToSink_1_1$wset_1__SEL_3 or + MUX_flitToSink_1_1$wset_1__SEL_6 or ifcs_2_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1$wset_1__SEL_1 || MUX_flitToSink_1_1$wset_1__SEL_4: + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1 = ifcs_0_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_2 || MUX_flitToSink_1_1$wset_1__SEL_5: + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1 = ifcs_1_rspBack$D_OUT; + MUX_flitToSink_1_1$wset_1__SEL_3 || MUX_flitToSink_1_1$wset_1__SEL_6: + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1 = ifcs_2_rspBack$D_OUT; + default: MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1 = + 6'b101010 /* unspecified value */ ; + endcase + end + always@(MUX_flitToSink_1_1_1_1$wset_1__SEL_1 or + MUX_flitToSink_1_1_1_1$wset_1__SEL_4 or + ifcs_0_1_rspBack$D_OUT or + MUX_flitToSink_1_1_1_1$wset_1__SEL_2 or + MUX_flitToSink_1_1_1_1$wset_1__SEL_5 or + ifcs_1_1_rspBack$D_OUT or + MUX_flitToSink_1_1_1_1$wset_1__SEL_3 or + MUX_flitToSink_1_1_1_1$wset_1__SEL_6 or ifcs_2_1_rspBack$D_OUT) + begin + case (1'b1) // synopsys parallel_case + MUX_flitToSink_1_1_1_1$wset_1__SEL_1 || + MUX_flitToSink_1_1_1_1$wset_1__SEL_4: + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1 = + ifcs_0_1_rspBack$D_OUT; + MUX_flitToSink_1_1_1_1$wset_1__SEL_2 || + MUX_flitToSink_1_1_1_1$wset_1__SEL_5: + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1 = + ifcs_1_1_rspBack$D_OUT; + MUX_flitToSink_1_1_1_1$wset_1__SEL_3 || + MUX_flitToSink_1_1_1_1$wset_1__SEL_6: + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1 = + ifcs_2_1_rspBack$D_OUT; + default: MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1 = + 71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_split_0_flitLeft$write_1__VAL_1 = split_0_flitLeft - 8'd1 ; + assign MUX_split_1_flitLeft$write_1__VAL_1 = split_1_flitLeft - 8'd1 ; + assign MUX_split_2_flitLeft$write_1__VAL_1 = split_2_flitLeft - 8'd1 ; + + // inlined wires + assign msNoSynth_0_w_dwReady$whas = + WILL_FIRE_RL_merged_0_genOther || + WILL_FIRE_RL_merged_0_genFirst ; + assign msNoSynth_0_b_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_0_forwardRsp ? + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1 : + ifcs_0_noRouteRsp$D_OUT ; + assign msNoSynth_0_b_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_0_forwardRsp || + WILL_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign msNoSynth_0_ar_dwReady$whas = + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp && + x_port1__read__h55959 == 9'd1 || + WILL_FIRE_RL_ifcs_0_1_drainFlits || + WILL_FIRE_RL_ifcs_0_1_followFlits || + WILL_FIRE_RL_ifcs_0_1_firstFlit ; + assign msNoSynth_0_r_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_0_1_forwardRsp ? + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1 : + ifcs_0_1_noRouteRsp$D_OUT ; + assign msNoSynth_0_r_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_0_1_forwardRsp || + WILL_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign msNoSynth_1_w_dwReady$whas = + WILL_FIRE_RL_merged_1_genOther || + WILL_FIRE_RL_merged_1_genFirst ; + assign msNoSynth_1_b_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_1_forwardRsp ? + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1 : + ifcs_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_b_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_1_forwardRsp || + WILL_FIRE_RL_ifcs_1_drainNoRouteResponse ; + assign msNoSynth_1_ar_dwReady$whas = + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp && + x_port1__read__h58381 == 9'd1 || + WILL_FIRE_RL_ifcs_1_1_drainFlits || + WILL_FIRE_RL_ifcs_1_1_followFlits || + WILL_FIRE_RL_ifcs_1_1_firstFlit ; + assign msNoSynth_1_r_buffer_enqw$wget = + WILL_FIRE_RL_ifcs_1_1_forwardRsp ? + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1 : + ifcs_1_1_noRouteRsp$D_OUT ; + assign msNoSynth_1_r_buffer_enqw$whas = + WILL_FIRE_RL_ifcs_1_1_forwardRsp || + WILL_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + assign ssNoSynth_0_w_buffer_enqw$whas = + WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] || + WILL_FIRE_RL_split_0_putFirst && !split_0_doPut$wget[171] ; + assign ssNoSynth_0_b_dwReady$whas = + WILL_FIRE_RL_ifcs_0_followFlits_1 || + WILL_FIRE_RL_ifcs_0_firstFlit_1 ; + assign ssNoSynth_0_ar_buffer_enqw$wget = + (MUX_flitToSink_1_0_1$wset_1__SEL_1 || + MUX_flitToSink_1_0_1$wset_1__SEL_3) ? + ifcs_0_1_innerReq$D_OUT : + ifcs_1_1_innerReq$D_OUT ; + assign ssNoSynth_0_r_dwReady$whas = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 || + WILL_FIRE_RL_ifcs_0_1_firstFlit_1 ; + assign ssNoSynth_1_aw_buffer_enqw$wget = split_1_doPut$wget[170:73] ; + assign ssNoSynth_1_w_buffer_enqw$wget = split_1_doPut$wget[72:0] ; + assign ssNoSynth_1_w_buffer_enqw$whas = + WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] || + WILL_FIRE_RL_split_1_putFirst && !split_1_doPut$wget[171] ; + assign ssNoSynth_1_b_dwReady$whas = + WILL_FIRE_RL_ifcs_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_firstFlit_1 ; + assign ssNoSynth_1_ar_buffer_enqw$wget = + (MUX_flitToSink_1_1_1$wset_1__SEL_1 || + MUX_flitToSink_1_1_1$wset_1__SEL_3) ? + ifcs_0_1_innerReq$D_OUT : + ifcs_1_1_innerReq$D_OUT ; + assign ssNoSynth_1_r_dwReady$whas = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 ; + assign ssNoSynth_2_aw_buffer_enqw$wget = split_2_doPut$wget[170:73] ; + assign ssNoSynth_2_w_buffer_enqw$wget = split_2_doPut$wget[72:0] ; + assign ssNoSynth_2_w_buffer_enqw$whas = + WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] || + WILL_FIRE_RL_split_2_putFirst && !split_2_doPut$wget[171] ; + assign ssNoSynth_2_b_dwReady$whas = + WILL_FIRE_RL_ifcs_2_followFlits || + WILL_FIRE_RL_ifcs_2_firstFlit ; + assign ssNoSynth_2_ar_buffer_enqw$wget = + (MUX_flitToSink_1_2$wset_1__SEL_1 || + MUX_flitToSink_1_2$wset_1__SEL_3) ? + ifcs_0_1_innerReq$D_OUT : + ifcs_1_1_innerReq$D_OUT ; + assign ssNoSynth_2_r_dwReady$whas = + WILL_FIRE_RL_ifcs_2_1_followFlits || + WILL_FIRE_RL_ifcs_2_1_firstFlit ; + assign split_0_doPut$wget = + (MUX_flitToSink_0$wset_1__SEL_1 || + MUX_flitToSink_0$wset_1__SEL_3) ? + ifcs_0_innerReq$D_OUT : + ifcs_1_innerReq$D_OUT ; + assign split_1_doPut$wget = + (MUX_flitToSink_1$wset_1__SEL_1 || + MUX_flitToSink_1$wset_1__SEL_3) ? + ifcs_0_innerReq$D_OUT : + ifcs_1_innerReq$D_OUT ; + assign split_2_doPut$wget = + (MUX_flitToSink_2$wset_1__SEL_1 || + MUX_flitToSink_2$wset_1__SEL_3) ? + ifcs_0_innerReq$D_OUT : + ifcs_1_innerReq$D_OUT ; + assign reqWires_0$wget = + (!ifcs_0_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992) ? + IF_NOT_ifcs_0_innerRoute_first__000_BIT_1_009__ETC___d1022 : + ifcs_0_innerRoute$D_OUT[0] ; + assign reqWires_1$wget = + (!ifcs_1_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992) ? + IF_NOT_ifcs_1_innerRoute_first__029_BIT_1_033__ETC___d1038 : + ifcs_1_innerRoute$D_OUT[0] ; + assign flitToSink_0$whas = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[0] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerRoute$D_OUT[0] ; + assign flitToSink_1$whas = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[1] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerRoute$D_OUT[1] ; + assign flitToSink_2$whas = + WILL_FIRE_RL_burst && ifcs_0_innerRoute$D_OUT[2] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerRoute$D_OUT[2] ; + assign reqWires_1_0$wget = + (!ifcs_0_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_0_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_0_routeBack$D_OUT[0] ; + assign reqWires_1_1$wget = + (!ifcs_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_1_routeBack$D_OUT[0] ; + assign reqWires_1_2$wget = + (!ifcs_2_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_2_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_2_routeBack$D_OUT[0] ; + assign flitToSink_1_0$whas = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[0] ; + assign flitToSink_1_1$whas = + WILL_FIRE_RL_burst_2 && ifcs_0_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_3 && ifcs_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_4 && ifcs_2_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + ifcs_0_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + ifcs_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + ifcs_2_routeBack$D_OUT[1] ; + assign reqWires_1_0_1$wget = + (!ifcs_0_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__638_BIT_1_64_ETC___d1660 : + ifcs_0_1_innerRoute$D_OUT[0] ; + assign reqWires_1_1_1$wget = + (!ifcs_1_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__667_BIT_1_67_ETC___d1676 : + ifcs_1_1_innerRoute$D_OUT[0] ; + assign flitToSink_1_0_1$whas = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[0] || + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + ifcs_1_1_innerRoute$D_OUT[0] ; + assign flitToSink_1_1_1$whas = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[1] || + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + ifcs_1_1_innerRoute$D_OUT[1] ; + assign flitToSink_1_2$whas = + WILL_FIRE_RL_burst_5 && ifcs_0_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_burst_6 && ifcs_1_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + ifcs_0_1_innerRoute$D_OUT[2] || + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + ifcs_1_1_innerRoute$D_OUT[2] ; + assign reqWires_1_1_0$wget = + (!ifcs_0_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_0_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_0_1_routeBack$D_OUT[0] ; + assign reqWires_1_1_1_1$wget = + (!ifcs_1_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_1_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_1_1_routeBack$D_OUT[0] ; + assign reqWires_1_1_2$wget = + (!ifcs_2_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_2_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_2_1_routeBack$D_OUT[0] ; + assign flitToSink_1_1_0$whas = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[0] ; + assign flitToSink_1_1_1_1$whas = + WILL_FIRE_RL_burst_7 && ifcs_0_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_8 && ifcs_1_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_burst_9 && ifcs_2_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_routeBack$D_OUT[1] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_routeBack$D_OUT[1] ; + assign merged_0_doDrop$whas = + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp || + WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits || + WILL_FIRE_RL_ifcs_0_firstFlit ; + assign merged_1_doDrop$whas = + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp || + WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits || + WILL_FIRE_RL_ifcs_1_firstFlit ; + assign sourceSelect_1_0$whas = + WILL_FIRE_RL_arbitrate_1 && + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1284 ; + assign sourceSelect_1_1$whas = + WILL_FIRE_RL_arbitrate_1 && + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1290 ; + assign sourceSelect_1_2$whas = + WILL_FIRE_RL_arbitrate_1 && + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1296 ; + assign sourceSelect_1_0_1$whas = + WILL_FIRE_RL_arbitrate_2 && + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1712 ; + assign sourceSelect_1_1_1$whas = + WILL_FIRE_RL_arbitrate_2 && + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1716 ; + assign ifcs_0_noRoute_inner_currentReq$EN_port0__write = + WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + merged_0_flitLeft == 8'd0 ; + assign ifcs_0_noRoute_inner_currentReq$port0__write_1 = + { cpu$dmem_master_awid, + cpu$dmem_master_awaddr, + cpu$dmem_master_awlen, + cpu$dmem_master_awsize, + cpu$dmem_master_awburst, + cpu$dmem_master_awlock, + cpu$dmem_master_awcache, + cpu$dmem_master_awprot, + cpu$dmem_master_awqos, + cpu$dmem_master_awregion } ; + assign ifcs_0_noRoute_inner_currentReq$port1__read = + ifcs_0_noRoute_inner_currentReq$EN_port0__write ? + ifcs_0_noRoute_inner_currentReq$port0__write_1 : + ifcs_0_noRoute_inner_currentReq ; + assign ifcs_0_noRoute_inner_pendingReq$EN_port0__write = + WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + merged_0_flitLeft == 8'd0 ; + assign ifcs_0_noRoute_inner_pendingReq$port1__read = + ifcs_0_noRoute_inner_pendingReq$EN_port0__write || + ifcs_0_noRoute_inner_pendingReq ; + assign ifcs_0_noRoute_inner_pendingReq$port2__read = + !CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp && + ifcs_0_noRoute_inner_pendingReq$port1__read ; + assign ifcs_1_noRoute_inner_currentReq$EN_port0__write = + WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + merged_1_flitLeft == 8'd0 ; + assign ifcs_1_noRoute_inner_currentReq$port0__write_1 = + { dm_mem_tap$master_awid, + dm_mem_tap$master_awaddr, + dm_mem_tap$master_awlen, + dm_mem_tap$master_awsize, + dm_mem_tap$master_awburst, + dm_mem_tap$master_awlock, + dm_mem_tap$master_awcache, + dm_mem_tap$master_awprot, + dm_mem_tap$master_awqos, + dm_mem_tap$master_awregion } ; + assign ifcs_1_noRoute_inner_currentReq$port1__read = + ifcs_1_noRoute_inner_currentReq$EN_port0__write ? + ifcs_1_noRoute_inner_currentReq$port0__write_1 : + ifcs_1_noRoute_inner_currentReq ; + assign ifcs_1_noRoute_inner_pendingReq$EN_port0__write = + WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + merged_1_flitLeft == 8'd0 ; + assign ifcs_1_noRoute_inner_pendingReq$port1__read = + ifcs_1_noRoute_inner_pendingReq$EN_port0__write || + ifcs_1_noRoute_inner_pendingReq ; + assign ifcs_1_noRoute_inner_pendingReq$port2__read = + !CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp && + ifcs_1_noRoute_inner_pendingReq$port1__read ; + assign ifcs_0_1_noRoute_currentReq$port0__write_1 = + { cpu$dmem_master_arid, + cpu$dmem_master_araddr, + cpu$dmem_master_arlen, + cpu$dmem_master_arsize, + cpu$dmem_master_arburst, + cpu$dmem_master_arlock, + cpu$dmem_master_arcache, + cpu$dmem_master_arprot, + cpu$dmem_master_arqos, + cpu$dmem_master_arregion } ; + assign ifcs_0_1_noRoute_currentReq$port1__read = + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? + ifcs_0_1_noRoute_currentReq$port0__write_1 : + ifcs_0_1_noRoute_currentReq ; + assign ifcs_0_1_noRoute_flitCount$port0__write_1 = + { 1'd0, cpu$dmem_master_arlen } + 9'd1 ; + assign ifcs_0_1_noRoute_flitCount$port1__write_1 = + x_port1__read__h55959 - 9'd1 ; + assign ifcs_0_1_noRoute_flitCount$port2__read = + CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ? + ifcs_0_1_noRoute_flitCount$port1__write_1 : + x_port1__read__h55959 ; + assign ifcs_1_1_noRoute_currentReq$port0__write_1 = + { dm_mem_tap$master_arid, + dm_mem_tap$master_araddr, + dm_mem_tap$master_arlen, + dm_mem_tap$master_arsize, + dm_mem_tap$master_arburst, + dm_mem_tap$master_arlock, + dm_mem_tap$master_arcache, + dm_mem_tap$master_arprot, + dm_mem_tap$master_arqos, + dm_mem_tap$master_arregion } ; + assign ifcs_1_1_noRoute_currentReq$port1__read = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? + ifcs_1_1_noRoute_currentReq$port0__write_1 : + ifcs_1_1_noRoute_currentReq ; + assign ifcs_1_1_noRoute_flitCount$port0__write_1 = + { 1'd0, dm_mem_tap$master_arlen } + 9'd1 ; + assign ifcs_1_1_noRoute_flitCount$port1__write_1 = + x_port1__read__h58381 - 9'd1 ; + assign ifcs_1_1_noRoute_flitCount$port2__read = + CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ? + ifcs_1_1_noRoute_flitCount$port1__write_1 : + x_port1__read__h58381 ; + + // register activeSource_0 + assign activeSource_0$D_IN = + MUX_activeSource_0$write_1__SEL_1 ? + MUX_activeSource_0$write_1__VAL_1 : + MUX_activeSource_0$write_1__VAL_1 ; + assign activeSource_0$EN = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + !ifcs_1_innerReq$D_OUT[0] ; + + // register activeSource_1 + assign activeSource_1$D_IN = + MUX_activeSource_0$write_1__SEL_1 ? + MUX_activeSource_1$write_1__VAL_1 : + MUX_activeSource_1$write_1__VAL_1 ; + assign activeSource_1$EN = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + !ifcs_1_innerReq$D_OUT[0] ; + + // register activeSource_1_0 + assign activeSource_1_0$D_IN = 1'b0 ; + assign activeSource_1_0$EN = 1'b0 ; + + // register activeSource_1_0_1 + assign activeSource_1_0_1$D_IN = 1'b0 ; + assign activeSource_1_0_1$EN = 1'b0 ; + + // register activeSource_1_1 + assign activeSource_1_1$D_IN = 1'b0 ; + assign activeSource_1_1$EN = 1'b0 ; + + // register activeSource_1_1_0 + always@(MUX_activeSource_1_1_0$write_1__SEL_1 or + MUX_activeSource_1_1_0$write_1__VAL_1 or + MUX_activeSource_1_1_0$write_1__SEL_2 or + MUX_activeSource_1_1_0$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_activeSource_1_1_0$write_1__SEL_1: + activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_2: + activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_3: + activeSource_1_1_0$D_IN = MUX_activeSource_1_1_0$write_1__VAL_1; + default: activeSource_1_1_0$D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign activeSource_1_1_0$EN = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[0] ; + + // register activeSource_1_1_1 + assign activeSource_1_1_1$D_IN = 1'b0 ; + assign activeSource_1_1_1$EN = 1'b0 ; + + // register activeSource_1_1_1_1 + always@(MUX_activeSource_1_1_0$write_1__SEL_1 or + MUX_activeSource_1_1_1_1$write_1__VAL_1 or + MUX_activeSource_1_1_0$write_1__SEL_2 or + MUX_activeSource_1_1_0$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_activeSource_1_1_0$write_1__SEL_1: + activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_2: + activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_3: + activeSource_1_1_1_1$D_IN = MUX_activeSource_1_1_1_1$write_1__VAL_1; + default: activeSource_1_1_1_1$D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign activeSource_1_1_1_1$EN = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[0] ; + + // register activeSource_1_1_2 + always@(MUX_activeSource_1_1_0$write_1__SEL_1 or + MUX_activeSource_1_1_2$write_1__VAL_1 or + MUX_activeSource_1_1_0$write_1__SEL_2 or + MUX_activeSource_1_1_0$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_activeSource_1_1_0$write_1__SEL_1: + activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_2: + activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; + MUX_activeSource_1_1_0$write_1__SEL_3: + activeSource_1_1_2$D_IN = MUX_activeSource_1_1_2$write_1__VAL_1; + default: activeSource_1_1_2$D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign activeSource_1_1_2$EN = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[0] ; + + // register activeSource_1_2 + assign activeSource_1_2$D_IN = 1'b0 ; + assign activeSource_1_2$EN = 1'b0 ; + + // register arbiter_1_1_firstHot + assign arbiter_1_1_firstHot$D_IN = + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1924 ; + assign arbiter_1_1_firstHot$EN = CAN_FIRE_RL_arbitrate_3 ; + + // register arbiter_1_1_lastSelect + assign arbiter_1_1_lastSelect$D_IN = + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1912 ; + assign arbiter_1_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_3 ; + + // register arbiter_1_1_lastSelect_1 + assign arbiter_1_1_lastSelect_1$D_IN = + IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1918 ; + assign arbiter_1_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_3 ; + + // register arbiter_1_firstHot + assign arbiter_1_firstHot$D_IN = + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1296 ; + assign arbiter_1_firstHot$EN = CAN_FIRE_RL_arbitrate_1 ; + + // register arbiter_1_firstHot_1 + assign arbiter_1_firstHot_1$D_IN = + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1716 ; + assign arbiter_1_firstHot_1$EN = CAN_FIRE_RL_arbitrate_2 ; + + // register arbiter_1_lastSelect + assign arbiter_1_lastSelect$D_IN = + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1284 ; + assign arbiter_1_lastSelect$EN = CAN_FIRE_RL_arbitrate_1 ; + + // register arbiter_1_lastSelect_1 + assign arbiter_1_lastSelect_1$D_IN = + IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1290 ; + assign arbiter_1_lastSelect_1$EN = CAN_FIRE_RL_arbitrate_1 ; + + // register arbiter_1_lastSelect_2 + assign arbiter_1_lastSelect_2$D_IN = + IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1712 ; + assign arbiter_1_lastSelect_2$EN = CAN_FIRE_RL_arbitrate_2 ; + + // register arbiter_firstHot + assign arbiter_firstHot$D_IN = + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1078 ; + assign arbiter_firstHot$EN = CAN_FIRE_RL_arbitrate ; + + // register arbiter_lastSelect + assign arbiter_lastSelect$D_IN = + IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1074 ; + assign arbiter_lastSelect$EN = CAN_FIRE_RL_arbitrate ; + + // register ifcs_0_1_noRoute_currentReq + assign ifcs_0_1_noRoute_currentReq$D_IN = + ifcs_0_1_noRoute_currentReq$port1__read ; + assign ifcs_0_1_noRoute_currentReq$EN = 1'b1 ; + + // register ifcs_0_1_noRoute_flitCount + assign ifcs_0_1_noRoute_flitCount$D_IN = + ifcs_0_1_noRoute_flitCount$port2__read ; + assign ifcs_0_1_noRoute_flitCount$EN = 1'b1 ; + + // register ifcs_0_1_state + assign ifcs_0_1_state$D_IN = 2'd0 ; + assign ifcs_0_1_state$EN = + WILL_FIRE_RL_ifcs_0_1_drainFlits || + WILL_FIRE_RL_ifcs_0_1_followFlits ; + + // register ifcs_0_1_state_1 + assign ifcs_0_1_state_1$D_IN = !MUX_ifcs_0_1_state_1$write_1__SEL_1 ; + assign ifcs_0_1_state_1$EN = + WILL_FIRE_RL_ifcs_0_1_followFlits_1 && shim_rff$D_OUT[0] || + WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && !shim_rff$D_OUT[0] ; + + // register ifcs_0_noRoute_inner_currentReq + assign ifcs_0_noRoute_inner_currentReq$D_IN = + ifcs_0_noRoute_inner_currentReq$port1__read ; + assign ifcs_0_noRoute_inner_currentReq$EN = 1'b1 ; + + // register ifcs_0_noRoute_inner_pendingReq + assign ifcs_0_noRoute_inner_pendingReq$D_IN = + ifcs_0_noRoute_inner_pendingReq$port2__read ; + assign ifcs_0_noRoute_inner_pendingReq$EN = 1'b1 ; + + // register ifcs_0_state + always@(MUX_ifcs_0_state$write_1__SEL_1 or + MUX_ifcs_0_state$write_1__SEL_2 or MUX_ifcs_0_state$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_ifcs_0_state$write_1__SEL_1: ifcs_0_state$D_IN = 2'd0; + MUX_ifcs_0_state$write_1__SEL_2: ifcs_0_state$D_IN = 2'd1; + MUX_ifcs_0_state$write_1__SEL_3: ifcs_0_state$D_IN = 2'd2; + default: ifcs_0_state$D_IN = 2'b10 /* unspecified value */ ; + endcase + end + assign ifcs_0_state$EN = + (WILL_FIRE_RL_ifcs_0_drainFlits || + WILL_FIRE_RL_ifcs_0_followFlits) && + cpu$dmem_master_wlast || + WILL_FIRE_RL_ifcs_0_firstFlit && !cpu$dmem_master_wlast || + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp && !cpu$dmem_master_wlast ; + + // register ifcs_0_state_1 + assign ifcs_0_state_1$D_IN = 1'd0 ; + assign ifcs_0_state_1$EN = CAN_FIRE_RL_ifcs_0_followFlits_1 ; + + // register ifcs_1_1_noRoute_currentReq + assign ifcs_1_1_noRoute_currentReq$D_IN = + ifcs_1_1_noRoute_currentReq$port1__read ; + assign ifcs_1_1_noRoute_currentReq$EN = 1'b1 ; + + // register ifcs_1_1_noRoute_flitCount + assign ifcs_1_1_noRoute_flitCount$D_IN = + ifcs_1_1_noRoute_flitCount$port2__read ; + assign ifcs_1_1_noRoute_flitCount$EN = 1'b1 ; + + // register ifcs_1_1_state + assign ifcs_1_1_state$D_IN = 2'd0 ; + assign ifcs_1_1_state$EN = + WILL_FIRE_RL_ifcs_1_1_drainFlits || + WILL_FIRE_RL_ifcs_1_1_followFlits ; + + // register ifcs_1_1_state_1 + assign ifcs_1_1_state_1$D_IN = !MUX_ifcs_1_1_state_1$write_1__SEL_1 ; + assign ifcs_1_1_state_1$EN = + WILL_FIRE_RL_ifcs_1_1_followFlits_1 && + near_mem_io$axi4_slave_rlast || + WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && + !near_mem_io$axi4_slave_rlast ; + + // register ifcs_1_noRoute_inner_currentReq + assign ifcs_1_noRoute_inner_currentReq$D_IN = + ifcs_1_noRoute_inner_currentReq$port1__read ; + assign ifcs_1_noRoute_inner_currentReq$EN = 1'b1 ; + + // register ifcs_1_noRoute_inner_pendingReq + assign ifcs_1_noRoute_inner_pendingReq$D_IN = + ifcs_1_noRoute_inner_pendingReq$port2__read ; + assign ifcs_1_noRoute_inner_pendingReq$EN = 1'b1 ; + + // register ifcs_1_state + always@(MUX_ifcs_1_state$write_1__SEL_1 or + MUX_ifcs_1_state$write_1__SEL_2 or MUX_ifcs_1_state$write_1__SEL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_ifcs_1_state$write_1__SEL_1: ifcs_1_state$D_IN = 2'd0; + MUX_ifcs_1_state$write_1__SEL_2: ifcs_1_state$D_IN = 2'd1; + MUX_ifcs_1_state$write_1__SEL_3: ifcs_1_state$D_IN = 2'd2; + default: ifcs_1_state$D_IN = 2'b10 /* unspecified value */ ; + endcase + end + assign ifcs_1_state$EN = + (WILL_FIRE_RL_ifcs_1_drainFlits || + WILL_FIRE_RL_ifcs_1_followFlits) && + dm_mem_tap$master_wlast || + WILL_FIRE_RL_ifcs_1_firstFlit && !dm_mem_tap$master_wlast || + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp && + !dm_mem_tap$master_wlast ; + + // register ifcs_1_state_1 + assign ifcs_1_state_1$D_IN = 1'd0 ; + assign ifcs_1_state_1$EN = CAN_FIRE_RL_ifcs_1_followFlits_1 ; + + // register ifcs_2_1_state + assign ifcs_2_1_state$D_IN = !MUX_ifcs_2_1_state$write_1__SEL_1 ; + assign ifcs_2_1_state$EN = + WILL_FIRE_RL_ifcs_2_1_followFlits && plic$axi4_slave_rlast || + WILL_FIRE_RL_ifcs_2_1_firstFlit && !plic$axi4_slave_rlast ; + + // register ifcs_2_state + assign ifcs_2_state$D_IN = 1'd0 ; + assign ifcs_2_state$EN = CAN_FIRE_RL_ifcs_2_followFlits ; + + // register merged_0_flitLeft + assign merged_0_flitLeft$D_IN = + WILL_FIRE_RL_merged_0_genOther ? + MUX_merged_0_flitLeft$write_1__VAL_1 : + cpu$dmem_master_awlen ; + assign merged_0_flitLeft$EN = msNoSynth_0_w_dwReady$whas ; + + // register merged_1_flitLeft + assign merged_1_flitLeft$D_IN = + WILL_FIRE_RL_merged_1_genOther ? + MUX_merged_1_flitLeft$write_1__VAL_1 : + dm_mem_tap$master_awlen ; + assign merged_1_flitLeft$EN = msNoSynth_1_w_dwReady$whas ; + + // register split_0_flitLeft + assign split_0_flitLeft$D_IN = + MUX_split_0_flitLeft$write_1__SEL_1 ? + MUX_split_0_flitLeft$write_1__VAL_1 : + split_0_doPut$wget[101:94] ; + assign split_0_flitLeft$EN = ssNoSynth_0_w_buffer_enqw$whas ; + + // register split_1_flitLeft + assign split_1_flitLeft$D_IN = + MUX_split_1_flitLeft$write_1__SEL_1 ? + MUX_split_1_flitLeft$write_1__VAL_1 : + split_1_doPut$wget[101:94] ; + assign split_1_flitLeft$EN = ssNoSynth_1_w_buffer_enqw$whas ; + + // register split_2_flitLeft + assign split_2_flitLeft$D_IN = + MUX_split_2_flitLeft$write_1__SEL_1 ? + MUX_split_2_flitLeft$write_1__VAL_1 : + split_2_doPut$wget[101:94] ; + assign split_2_flitLeft$EN = ssNoSynth_2_w_buffer_enqw$whas ; + + // register state + assign state$D_IN = !MUX_state$write_1__SEL_1 && !MUX_state$write_1__SEL_2 ; + assign state$EN = + WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[0] || + WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + !ifcs_0_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + !ifcs_1_innerReq$D_OUT[0] ; + + // register state_1 + assign state_1$D_IN = 1'd0 ; + assign state_1$EN = + WILL_FIRE_RL_burst_4 || WILL_FIRE_RL_burst_3 || + WILL_FIRE_RL_burst_2 ; + + // register state_1_1 + assign state_1_1$D_IN = 1'd0 ; + assign state_1_1$EN = WILL_FIRE_RL_burst_6 || WILL_FIRE_RL_burst_5 ; + + // register state_1_1_1 + assign state_1_1_1$D_IN = + !MUX_state_1_1_1$write_1__SEL_1 && + !MUX_state_1_1_1$write_1__SEL_2 && + !MUX_state_1_1_1$write_1__SEL_3 ; + assign state_1_1_1$EN = + WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + !ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + !ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + !ifcs_2_1_rspBack$D_OUT[0] ; + + // submodule cpu + assign cpu$dmem_master_arready = msNoSynth_0_ar_dwReady$whas ; + assign cpu$dmem_master_awready = CAN_FIRE_RL_merged_0_genFirst ; + assign cpu$dmem_master_bid = + msNoSynth_0_b_buffer_ff$EMPTY_N ? + msNoSynth_0_b_buffer_ff$D_OUT[5:2] : + msNoSynth_0_b_buffer_enqw$wget[5:2] ; + assign cpu$dmem_master_bresp = + msNoSynth_0_b_buffer_ff$EMPTY_N ? + msNoSynth_0_b_buffer_ff$D_OUT[1:0] : + msNoSynth_0_b_buffer_enqw$wget[1:0] ; + assign cpu$dmem_master_rdata = + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[66:3] : + msNoSynth_0_r_buffer_enqw$wget[66:3] ; + assign cpu$dmem_master_rid = + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[70:67] : + msNoSynth_0_r_buffer_enqw$wget[70:67] ; + assign cpu$dmem_master_rlast = + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[0] : + msNoSynth_0_r_buffer_enqw$wget[0] ; + assign cpu$dmem_master_rresp = + msNoSynth_0_r_buffer_ff$EMPTY_N ? + msNoSynth_0_r_buffer_ff$D_OUT[2:1] : + msNoSynth_0_r_buffer_enqw$wget[2:1] ; + assign cpu$dmem_master_wready = msNoSynth_0_w_dwReady$whas ; + assign cpu$hart0_csr_mem_server_request_put = + dm_csr_tap$client_request_get ; + assign cpu$hart0_gpr_mem_server_request_put = + dm_gpr_tap_ifc$client_request_get ; + assign cpu$hart0_put_other_req_put = debug_module$hart0_get_other_req_get ; + assign cpu$hart0_server_reset_request_put = + WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ? + f_reset_reqs$D_OUT : + debug_module$hart0_reset_client_request_get ; + assign cpu$hart0_server_run_halt_request_put = + debug_module$hart0_client_run_halt_request_get ; + assign cpu$imem_master_arready = cpu_imem_master_arready ; + assign cpu$imem_master_awready = cpu_imem_master_awready ; + assign cpu$imem_master_bid = cpu_imem_master_bid ; + assign cpu$imem_master_bresp = cpu_imem_master_bresp ; + assign cpu$imem_master_rdata = cpu_imem_master_rdata ; + assign cpu$imem_master_rid = cpu_imem_master_rid ; + assign cpu$imem_master_rlast = cpu_imem_master_rlast ; + assign cpu$imem_master_rresp = cpu_imem_master_rresp ; + assign cpu$imem_master_wready = cpu_imem_master_wready ; + assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ; + assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ; + assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ; + assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ; + assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ; + assign cpu$software_interrupt_req_set_not_clear = near_mem_io$get_sw_interrupt_req_get ; assign cpu$timer_interrupt_req_set_not_clear = near_mem_io$get_timer_interrupt_req_get ; @@ -3049,6 +6817,10 @@ module mkCore(CLK, WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start ; assign cpu$EN_hart0_server_reset_response_get = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ; + assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ; + assign cpu$dmem_master_bvalid = CAN_FIRE_RL_msNoSynth_0_b_forwardFlit ; + assign cpu$dmem_master_rvalid = CAN_FIRE_RL_msNoSynth_0_r_forwardFlit ; assign cpu$EN_set_verbosity = EN_set_verbosity ; assign cpu$EN_trace_data_out_get = WILL_FIRE_RL_merge_cpu_trace_data ; assign cpu$EN_hart0_server_run_halt_request_put = @@ -3082,12 +6854,10 @@ module mkCore(CLK, assign debug_module$master_awready = dm_mem_tap$slave_awready ; assign debug_module$master_bid = dm_mem_tap$slave_bid ; assign debug_module$master_bresp = dm_mem_tap$slave_bresp ; - assign debug_module$master_bvalid = dm_mem_tap$slave_bvalid ; assign debug_module$master_rdata = dm_mem_tap$slave_rdata ; assign debug_module$master_rid = dm_mem_tap$slave_rid ; assign debug_module$master_rlast = dm_mem_tap$slave_rlast ; assign debug_module$master_rresp = dm_mem_tap$slave_rresp ; - assign debug_module$master_rvalid = dm_mem_tap$slave_rvalid ; assign debug_module$master_wready = dm_mem_tap$slave_wready ; assign debug_module$ndm_reset_client_response_put = ndm_reset_client_response_put ; @@ -3117,6 +6887,8 @@ module mkCore(CLK, EN_ndm_reset_client_request_get ; assign debug_module$EN_ndm_reset_client_response_put = EN_ndm_reset_client_response_put ; + assign debug_module$master_bvalid = dm_mem_tap$slave_bvalid ; + assign debug_module$master_rvalid = dm_mem_tap$slave_rvalid ; // submodule dm_csr_tap assign dm_csr_tap$client_response_put = @@ -3151,17 +6923,33 @@ module mkCore(CLK, CAN_FIRE_RL_merge_dm_gpr_trace_data ; // submodule dm_mem_tap - assign dm_mem_tap$master_arready = fabric_2x3$v_from_masters_1_arready ; - assign dm_mem_tap$master_awready = fabric_2x3$v_from_masters_1_awready ; - assign dm_mem_tap$master_bid = fabric_2x3$v_from_masters_1_bid ; - assign dm_mem_tap$master_bresp = fabric_2x3$v_from_masters_1_bresp ; - assign dm_mem_tap$master_bvalid = fabric_2x3$v_from_masters_1_bvalid ; - assign dm_mem_tap$master_rdata = fabric_2x3$v_from_masters_1_rdata ; - assign dm_mem_tap$master_rid = fabric_2x3$v_from_masters_1_rid ; - assign dm_mem_tap$master_rlast = fabric_2x3$v_from_masters_1_rlast ; - assign dm_mem_tap$master_rresp = fabric_2x3$v_from_masters_1_rresp ; - assign dm_mem_tap$master_rvalid = fabric_2x3$v_from_masters_1_rvalid ; - assign dm_mem_tap$master_wready = fabric_2x3$v_from_masters_1_wready ; + assign dm_mem_tap$master_arready = msNoSynth_1_ar_dwReady$whas ; + assign dm_mem_tap$master_awready = CAN_FIRE_RL_merged_1_genFirst ; + assign dm_mem_tap$master_bid = + msNoSynth_1_b_buffer_ff$EMPTY_N ? + msNoSynth_1_b_buffer_ff$D_OUT[5:2] : + msNoSynth_1_b_buffer_enqw$wget[5:2] ; + assign dm_mem_tap$master_bresp = + msNoSynth_1_b_buffer_ff$EMPTY_N ? + msNoSynth_1_b_buffer_ff$D_OUT[1:0] : + msNoSynth_1_b_buffer_enqw$wget[1:0] ; + assign dm_mem_tap$master_rdata = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[66:3] : + msNoSynth_1_r_buffer_enqw$wget[66:3] ; + assign dm_mem_tap$master_rid = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[70:67] : + msNoSynth_1_r_buffer_enqw$wget[70:67] ; + assign dm_mem_tap$master_rlast = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[0] : + msNoSynth_1_r_buffer_enqw$wget[0] ; + assign dm_mem_tap$master_rresp = + msNoSynth_1_r_buffer_ff$EMPTY_N ? + msNoSynth_1_r_buffer_ff$D_OUT[2:1] : + msNoSynth_1_r_buffer_enqw$wget[2:1] ; + assign dm_mem_tap$master_wready = msNoSynth_1_w_dwReady$whas ; assign dm_mem_tap$slave_araddr = debug_module$master_araddr ; assign dm_mem_tap$slave_arburst = debug_module$master_arburst ; assign dm_mem_tap$slave_arcache = debug_module$master_arcache ; @@ -3172,7 +6960,6 @@ module mkCore(CLK, assign dm_mem_tap$slave_arqos = debug_module$master_arqos ; assign dm_mem_tap$slave_arregion = debug_module$master_arregion ; assign dm_mem_tap$slave_arsize = debug_module$master_arsize ; - assign dm_mem_tap$slave_arvalid = debug_module$master_arvalid ; assign dm_mem_tap$slave_awaddr = debug_module$master_awaddr ; assign dm_mem_tap$slave_awburst = debug_module$master_awburst ; assign dm_mem_tap$slave_awcache = debug_module$master_awcache ; @@ -3183,13 +6970,16 @@ module mkCore(CLK, assign dm_mem_tap$slave_awqos = debug_module$master_awqos ; assign dm_mem_tap$slave_awregion = debug_module$master_awregion ; assign dm_mem_tap$slave_awsize = debug_module$master_awsize ; - assign dm_mem_tap$slave_awvalid = debug_module$master_awvalid ; assign dm_mem_tap$slave_bready = debug_module$master_bready ; assign dm_mem_tap$slave_rready = debug_module$master_rready ; assign dm_mem_tap$slave_wdata = debug_module$master_wdata ; assign dm_mem_tap$slave_wlast = debug_module$master_wlast ; assign dm_mem_tap$slave_wstrb = debug_module$master_wstrb ; + assign dm_mem_tap$slave_awvalid = debug_module$master_awvalid ; assign dm_mem_tap$slave_wvalid = debug_module$master_wvalid ; + assign dm_mem_tap$slave_arvalid = debug_module$master_arvalid ; + assign dm_mem_tap$master_bvalid = CAN_FIRE_RL_msNoSynth_1_b_forwardFlit ; + assign dm_mem_tap$master_rvalid = CAN_FIRE_RL_msNoSynth_1_r_forwardFlit ; assign dm_mem_tap$EN_trace_data_out_get = WILL_FIRE_RL_merge_dm_mem_trace_data ; @@ -3198,8 +6988,7 @@ module mkCore(CLK, assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ; assign f_reset_reqs$DEQ = near_mem_io$RDY_server_reset_request_put && - plic$RDY_server_reset_request_put && - fabric_2x3_RDY_reset_AND_cpu_RDY_hart0_server__ETC___d9 ; + plic_RDY_server_reset_request_put_AND_cpu_RDY__ETC___d8 ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_requestor @@ -3250,134 +7039,460 @@ module mkCore(CLK, assign f_trace_data_merged$DEQ = CAN_FIRE_RL_mkConnectionGetPut_1 ; assign f_trace_data_merged$CLR = 1'b0 ; - // submodule fabric_2x3 - assign fabric_2x3$set_verbosity_verbosity = 4'h0 ; - assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ; - assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ; - assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ; - assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ; - assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ; - assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ; - assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ; - assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ; - assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ; - assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ; - assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ; - assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ; - assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ; - assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ; - assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ; - assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ; - assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ; - assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ; - assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ; - assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ; - assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ; - assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ; - assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ; - assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ; - assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ; - assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ; - assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ; - assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ; - assign fabric_2x3$v_from_masters_1_araddr = dm_mem_tap$master_araddr ; - assign fabric_2x3$v_from_masters_1_arburst = dm_mem_tap$master_arburst ; - assign fabric_2x3$v_from_masters_1_arcache = dm_mem_tap$master_arcache ; - assign fabric_2x3$v_from_masters_1_arid = dm_mem_tap$master_arid ; - assign fabric_2x3$v_from_masters_1_arlen = dm_mem_tap$master_arlen ; - assign fabric_2x3$v_from_masters_1_arlock = dm_mem_tap$master_arlock ; - assign fabric_2x3$v_from_masters_1_arprot = dm_mem_tap$master_arprot ; - assign fabric_2x3$v_from_masters_1_arqos = dm_mem_tap$master_arqos ; - assign fabric_2x3$v_from_masters_1_arregion = dm_mem_tap$master_arregion ; - assign fabric_2x3$v_from_masters_1_arsize = dm_mem_tap$master_arsize ; - assign fabric_2x3$v_from_masters_1_arvalid = dm_mem_tap$master_arvalid ; - assign fabric_2x3$v_from_masters_1_awaddr = dm_mem_tap$master_awaddr ; - assign fabric_2x3$v_from_masters_1_awburst = dm_mem_tap$master_awburst ; - assign fabric_2x3$v_from_masters_1_awcache = dm_mem_tap$master_awcache ; - assign fabric_2x3$v_from_masters_1_awid = dm_mem_tap$master_awid ; - assign fabric_2x3$v_from_masters_1_awlen = dm_mem_tap$master_awlen ; - assign fabric_2x3$v_from_masters_1_awlock = dm_mem_tap$master_awlock ; - assign fabric_2x3$v_from_masters_1_awprot = dm_mem_tap$master_awprot ; - assign fabric_2x3$v_from_masters_1_awqos = dm_mem_tap$master_awqos ; - assign fabric_2x3$v_from_masters_1_awregion = dm_mem_tap$master_awregion ; - assign fabric_2x3$v_from_masters_1_awsize = dm_mem_tap$master_awsize ; - assign fabric_2x3$v_from_masters_1_awvalid = dm_mem_tap$master_awvalid ; - assign fabric_2x3$v_from_masters_1_bready = dm_mem_tap$master_bready ; - assign fabric_2x3$v_from_masters_1_rready = dm_mem_tap$master_rready ; - assign fabric_2x3$v_from_masters_1_wdata = dm_mem_tap$master_wdata ; - assign fabric_2x3$v_from_masters_1_wlast = dm_mem_tap$master_wlast ; - assign fabric_2x3$v_from_masters_1_wstrb = dm_mem_tap$master_wstrb ; - assign fabric_2x3$v_from_masters_1_wvalid = dm_mem_tap$master_wvalid ; - assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ; - assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ; - assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ; - assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ; - assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ; - assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ; - assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ; - assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ; - assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ; - assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ; - assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ; - assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ; - assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ; - assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ; - assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ; - assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ; - assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ; - assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ; - assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ; - assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ; - assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ; - assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ; - assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ; - assign fabric_2x3$EN_reset = - WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || - WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; - assign fabric_2x3$EN_set_verbosity = 1'b0 ; + // submodule ifcs_0_1_innerReq + assign ifcs_0_1_innerReq$D_IN = + { fatReq_arid__h55399, + cpu$dmem_master_araddr, + cpu$dmem_master_arlen, + cpu$dmem_master_arsize, + cpu$dmem_master_arburst, + cpu$dmem_master_arlock, + cpu$dmem_master_arcache, + cpu$dmem_master_arprot, + cpu$dmem_master_arqos, + cpu$dmem_master_arregion } ; + assign ifcs_0_1_innerReq$ENQ = + WILL_FIRE_RL_ifcs_0_1_followFlits || + WILL_FIRE_RL_ifcs_0_1_firstFlit ; + assign ifcs_0_1_innerReq$DEQ = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_5 ; + assign ifcs_0_1_innerReq$CLR = 1'b0 ; + + // submodule ifcs_0_1_innerRoute + assign ifcs_0_1_innerRoute$D_IN = + { (cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412) && + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415 && + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416, + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 && + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412, + (cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412) && + (cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416) } ; + assign ifcs_0_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit ; + assign ifcs_0_1_innerRoute$DEQ = + WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_5 ; + assign ifcs_0_1_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_0_1_noRouteRsp + assign ifcs_0_1_noRouteRsp$D_IN = + { ifcs_0_1_noRoute_currentReq$port1__read[96:93], + 66'h2AAAAAAAAAAAAAAAB, + x_port1__read__h55959 == 9'd1 } ; + assign ifcs_0_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_1_nonRoutableGenRsp ; + assign ifcs_0_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse ; + assign ifcs_0_1_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_0_1_routeBack + assign ifcs_0_1_routeBack$D_IN = 2'd1 << shim_rff$D_OUT[71] ; + assign ifcs_0_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_1_firstFlit_1 ; + assign ifcs_0_1_routeBack$DEQ = + WILL_FIRE_RL_burst_7 && ifcs_0_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + ifcs_0_1_rspBack$D_OUT[0] ; + assign ifcs_0_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_0_1_rspBack + assign ifcs_0_1_rspBack$D_IN = shim_rff$D_OUT[70:0] ; + assign ifcs_0_1_rspBack$ENQ = ssNoSynth_0_r_dwReady$whas ; + assign ifcs_0_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_7 ; + assign ifcs_0_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_0_innerReq + assign ifcs_0_innerReq$D_IN = + { merged_0_flitLeft != 8'd0, + a_awid__h21643, + cpu$dmem_master_awaddr, + cpu$dmem_master_awlen, + cpu$dmem_master_awsize, + cpu$dmem_master_awburst, + cpu$dmem_master_awlock, + cpu$dmem_master_awcache, + cpu$dmem_master_awprot, + cpu$dmem_master_awqos, + cpu$dmem_master_awregion, + cpu$dmem_master_wdata, + cpu$dmem_master_wstrb, + cpu$dmem_master_wlast } ; + assign ifcs_0_innerReq$ENQ = + WILL_FIRE_RL_ifcs_0_followFlits || + WILL_FIRE_RL_ifcs_0_firstFlit ; + assign ifcs_0_innerReq$DEQ = + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst ; + assign ifcs_0_innerReq$CLR = 1'b0 ; + + // submodule ifcs_0_innerRoute + assign ifcs_0_innerRoute$D_IN = + { (IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771) && + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774 && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775, + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771, + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771) && + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775) } ; + assign ifcs_0_innerRoute$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit ; + assign ifcs_0_innerRoute$DEQ = + WILL_FIRE_RL_burst && ifcs_0_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + ifcs_0_innerReq$D_OUT[0] ; + assign ifcs_0_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_0_noRouteRsp + assign ifcs_0_noRouteRsp$D_IN = + { ifcs_0_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; + assign ifcs_0_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_0_nonRoutableGenRsp ; + assign ifcs_0_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_0_drainNoRouteResponse ; + assign ifcs_0_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_0_routeBack + assign ifcs_0_routeBack$D_IN = 2'd1 << shim_bff$D_OUT[6] ; + assign ifcs_0_routeBack$ENQ = CAN_FIRE_RL_ifcs_0_firstFlit_1 ; + assign ifcs_0_routeBack$DEQ = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_2 ; + assign ifcs_0_routeBack$CLR = 1'b0 ; + + // submodule ifcs_0_rspBack + assign ifcs_0_rspBack$D_IN = shim_bff$D_OUT[5:0] ; + assign ifcs_0_rspBack$ENQ = ssNoSynth_0_b_dwReady$whas ; + assign ifcs_0_rspBack$DEQ = + WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_2 ; + assign ifcs_0_rspBack$CLR = 1'b0 ; + + // submodule ifcs_1_1_innerReq + assign ifcs_1_1_innerReq$D_IN = + { fatReq_arid__h57824, + dm_mem_tap$master_araddr, + dm_mem_tap$master_arlen, + dm_mem_tap$master_arsize, + dm_mem_tap$master_arburst, + dm_mem_tap$master_arlock, + dm_mem_tap$master_arcache, + dm_mem_tap$master_arprot, + dm_mem_tap$master_arqos, + dm_mem_tap$master_arregion } ; + assign ifcs_1_1_innerReq$ENQ = + WILL_FIRE_RL_ifcs_1_1_followFlits || + WILL_FIRE_RL_ifcs_1_1_firstFlit ; + assign ifcs_1_1_innerReq$DEQ = + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_6 ; + assign ifcs_1_1_innerReq$CLR = 1'b0 ; + + // submodule ifcs_1_1_innerRoute + assign ifcs_1_1_innerRoute$D_IN = + { (dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498) && + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501 && + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502, + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 && + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498, + (dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498) && + (dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502) } ; + assign ifcs_1_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit ; + assign ifcs_1_1_innerRoute$DEQ = + WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_6 ; + assign ifcs_1_1_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_1_1_noRouteRsp + assign ifcs_1_1_noRouteRsp$D_IN = + { ifcs_1_1_noRoute_currentReq$port1__read[96:93], + 66'h2AAAAAAAAAAAAAAAB, + x_port1__read__h58381 == 9'd1 } ; + assign ifcs_1_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_1_nonRoutableGenRsp ; + assign ifcs_1_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse ; + assign ifcs_1_1_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_1_1_routeBack + assign ifcs_1_1_routeBack$D_IN = 2'd1 << near_mem_io$axi4_slave_rid[4] ; + assign ifcs_1_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_1_firstFlit_1 ; + assign ifcs_1_1_routeBack$DEQ = + WILL_FIRE_RL_burst_8 && ifcs_1_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + ifcs_1_1_rspBack$D_OUT[0] ; + assign ifcs_1_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_1_1_rspBack + assign ifcs_1_1_rspBack$D_IN = + { near_mem_io$axi4_slave_rid[3:0], + near_mem_io$axi4_slave_rdata, + near_mem_io$axi4_slave_rresp, + near_mem_io$axi4_slave_rlast } ; + assign ifcs_1_1_rspBack$ENQ = ssNoSynth_1_r_dwReady$whas ; + assign ifcs_1_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_8 ; + assign ifcs_1_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_1_innerReq + assign ifcs_1_innerReq$D_IN = + { merged_1_flitLeft != 8'd0, + a_awid__h24357, + dm_mem_tap$master_awaddr, + dm_mem_tap$master_awlen, + dm_mem_tap$master_awsize, + dm_mem_tap$master_awburst, + dm_mem_tap$master_awlock, + dm_mem_tap$master_awcache, + dm_mem_tap$master_awprot, + dm_mem_tap$master_awqos, + dm_mem_tap$master_awregion, + dm_mem_tap$master_wdata, + dm_mem_tap$master_wstrb, + dm_mem_tap$master_wlast } ; + assign ifcs_1_innerReq$ENQ = + WILL_FIRE_RL_ifcs_1_followFlits || + WILL_FIRE_RL_ifcs_1_firstFlit ; + assign ifcs_1_innerReq$DEQ = + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N || + WILL_FIRE_RL_burst_1 ; + assign ifcs_1_innerReq$CLR = 1'b0 ; + + // submodule ifcs_1_innerRoute + assign ifcs_1_innerRoute$D_IN = + { (IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868) && + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871 && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872, + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868, + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868) && + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872) } ; + assign ifcs_1_innerRoute$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit ; + assign ifcs_1_innerRoute$DEQ = + WILL_FIRE_RL_burst_1 && ifcs_1_innerReq$D_OUT[0] || + WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + ifcs_1_innerReq$D_OUT[0] ; + assign ifcs_1_innerRoute$CLR = 1'b0 ; + + // submodule ifcs_1_noRouteRsp + assign ifcs_1_noRouteRsp$D_IN = + { ifcs_1_noRoute_inner_currentReq$port1__read[96:93], 2'd3 } ; + assign ifcs_1_noRouteRsp$ENQ = CAN_FIRE_RL_ifcs_1_nonRoutableGenRsp ; + assign ifcs_1_noRouteRsp$DEQ = CAN_FIRE_RL_ifcs_1_drainNoRouteResponse ; + assign ifcs_1_noRouteRsp$CLR = 1'b0 ; + + // submodule ifcs_1_routeBack + assign ifcs_1_routeBack$D_IN = 2'd1 << near_mem_io$axi4_slave_bid[4] ; + assign ifcs_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_1_firstFlit_1 ; + assign ifcs_1_routeBack$DEQ = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_3 ; + assign ifcs_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_1_rspBack + assign ifcs_1_rspBack$D_IN = + { near_mem_io$axi4_slave_bid[3:0], + near_mem_io$axi4_slave_bresp } ; + assign ifcs_1_rspBack$ENQ = ssNoSynth_1_b_dwReady$whas ; + assign ifcs_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_3 ; + assign ifcs_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_2_1_routeBack + assign ifcs_2_1_routeBack$D_IN = 2'd1 << plic$axi4_slave_rid[4] ; + assign ifcs_2_1_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_1_firstFlit ; + assign ifcs_2_1_routeBack$DEQ = + WILL_FIRE_RL_burst_9 && ifcs_2_1_rspBack$D_OUT[0] || + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + ifcs_2_1_rspBack$D_OUT[0] ; + assign ifcs_2_1_routeBack$CLR = 1'b0 ; + + // submodule ifcs_2_1_rspBack + assign ifcs_2_1_rspBack$D_IN = + { plic$axi4_slave_rid[3:0], + plic$axi4_slave_rdata, + plic$axi4_slave_rresp, + plic$axi4_slave_rlast } ; + assign ifcs_2_1_rspBack$ENQ = ssNoSynth_2_r_dwReady$whas ; + assign ifcs_2_1_rspBack$DEQ = + WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_9 ; + assign ifcs_2_1_rspBack$CLR = 1'b0 ; + + // submodule ifcs_2_routeBack + assign ifcs_2_routeBack$D_IN = 2'd1 << plic$axi4_slave_bid[4] ; + assign ifcs_2_routeBack$ENQ = CAN_FIRE_RL_ifcs_2_firstFlit ; + assign ifcs_2_routeBack$DEQ = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_4 ; + assign ifcs_2_routeBack$CLR = 1'b0 ; + + // submodule ifcs_2_rspBack + assign ifcs_2_rspBack$D_IN = + { plic$axi4_slave_bid[3:0], plic$axi4_slave_bresp } ; + assign ifcs_2_rspBack$ENQ = ssNoSynth_2_b_dwReady$whas ; + assign ifcs_2_rspBack$DEQ = + WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N || + WILL_FIRE_RL_burst_4 ; + assign ifcs_2_rspBack$CLR = 1'b0 ; + + // submodule msNoSynth_0_b_buffer_ff + assign msNoSynth_0_b_buffer_ff$D_IN = msNoSynth_0_b_buffer_enqw$wget ; + assign msNoSynth_0_b_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_b_buffer_enqueue ; + assign msNoSynth_0_b_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_b_buffer_dequeue ; + assign msNoSynth_0_b_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_b_buffer_firstValid + assign msNoSynth_0_b_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_b_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_b_dropFlit ; + + // submodule msNoSynth_0_r_buffer_ff + assign msNoSynth_0_r_buffer_ff$D_IN = msNoSynth_0_r_buffer_enqw$wget ; + assign msNoSynth_0_r_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_0_r_buffer_enqueue ; + assign msNoSynth_0_r_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_0_r_buffer_dequeue ; + assign msNoSynth_0_r_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_0_r_buffer_firstValid + assign msNoSynth_0_r_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_0_r_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_0_r_dropFlit ; + + // submodule msNoSynth_1_b_buffer_ff + assign msNoSynth_1_b_buffer_ff$D_IN = msNoSynth_1_b_buffer_enqw$wget ; + assign msNoSynth_1_b_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_b_buffer_enqueue ; + assign msNoSynth_1_b_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_b_buffer_dequeue ; + assign msNoSynth_1_b_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_b_buffer_firstValid + assign msNoSynth_1_b_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_b_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_b_dropFlit ; + + // submodule msNoSynth_1_r_buffer_ff + assign msNoSynth_1_r_buffer_ff$D_IN = msNoSynth_1_r_buffer_enqw$wget ; + assign msNoSynth_1_r_buffer_ff$ENQ = + CAN_FIRE_RL_msNoSynth_1_r_buffer_enqueue ; + assign msNoSynth_1_r_buffer_ff$DEQ = + CAN_FIRE_RL_msNoSynth_1_r_buffer_dequeue ; + assign msNoSynth_1_r_buffer_ff$CLR = 1'b0 ; + + // submodule msNoSynth_1_r_buffer_firstValid + assign msNoSynth_1_r_buffer_firstValid$D_IN = 1'd1 ; + assign msNoSynth_1_r_buffer_firstValid$EN = + CAN_FIRE_RL_msNoSynth_1_r_dropFlit ; // submodule near_mem_io - assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ; - assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ; - assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ; - assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ; - assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ; - assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ; - assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ; - assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ; - assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ; - assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ; - assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ; - assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ; - assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ; - assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ; - assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ; - assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ; - assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ; - assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ; - assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ; - assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ; - assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ; - assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ; - assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ; - assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ; - assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ; - assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ; - assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ; - assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ; + assign near_mem_io$axi4_slave_araddr = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[92:29] : + ssNoSynth_1_ar_buffer_enqw$wget[92:29] ; + assign near_mem_io$axi4_slave_arburst = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[17:16] : + ssNoSynth_1_ar_buffer_enqw$wget[17:16] ; + assign near_mem_io$axi4_slave_arcache = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[14:11] : + ssNoSynth_1_ar_buffer_enqw$wget[14:11] ; + assign near_mem_io$axi4_slave_arid = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[97:93] : + ssNoSynth_1_ar_buffer_enqw$wget[97:93] ; + assign near_mem_io$axi4_slave_arlen = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[28:21] : + ssNoSynth_1_ar_buffer_enqw$wget[28:21] ; + assign near_mem_io$axi4_slave_arlock = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[15] : + ssNoSynth_1_ar_buffer_enqw$wget[15] ; + assign near_mem_io$axi4_slave_arprot = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[10:8] : + ssNoSynth_1_ar_buffer_enqw$wget[10:8] ; + assign near_mem_io$axi4_slave_arqos = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[7:4] : + ssNoSynth_1_ar_buffer_enqw$wget[7:4] ; + assign near_mem_io$axi4_slave_arregion = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[3:0] : + ssNoSynth_1_ar_buffer_enqw$wget[3:0] ; + assign near_mem_io$axi4_slave_arsize = + ssNoSynth_1_ar_buffer_ff$EMPTY_N ? + ssNoSynth_1_ar_buffer_ff$D_OUT[20:18] : + ssNoSynth_1_ar_buffer_enqw$wget[20:18] ; + assign near_mem_io$axi4_slave_awaddr = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[92:29] : + ssNoSynth_1_aw_buffer_enqw$wget[92:29] ; + assign near_mem_io$axi4_slave_awburst = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[17:16] : + ssNoSynth_1_aw_buffer_enqw$wget[17:16] ; + assign near_mem_io$axi4_slave_awcache = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[14:11] : + ssNoSynth_1_aw_buffer_enqw$wget[14:11] ; + assign near_mem_io$axi4_slave_awid = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[97:93] : + ssNoSynth_1_aw_buffer_enqw$wget[97:93] ; + assign near_mem_io$axi4_slave_awlen = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[28:21] : + ssNoSynth_1_aw_buffer_enqw$wget[28:21] ; + assign near_mem_io$axi4_slave_awlock = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[15] : + ssNoSynth_1_aw_buffer_enqw$wget[15] ; + assign near_mem_io$axi4_slave_awprot = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[10:8] : + ssNoSynth_1_aw_buffer_enqw$wget[10:8] ; + assign near_mem_io$axi4_slave_awqos = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[7:4] : + ssNoSynth_1_aw_buffer_enqw$wget[7:4] ; + assign near_mem_io$axi4_slave_awregion = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[3:0] : + ssNoSynth_1_aw_buffer_enqw$wget[3:0] ; + assign near_mem_io$axi4_slave_awsize = + ssNoSynth_1_aw_buffer_ff$EMPTY_N ? + ssNoSynth_1_aw_buffer_ff$D_OUT[20:18] : + ssNoSynth_1_aw_buffer_enqw$wget[20:18] ; + assign near_mem_io$axi4_slave_bready = ssNoSynth_1_b_dwReady$whas ; + assign near_mem_io$axi4_slave_rready = ssNoSynth_1_r_dwReady$whas ; + assign near_mem_io$axi4_slave_wdata = + ssNoSynth_1_w_buffer_ff$EMPTY_N ? + ssNoSynth_1_w_buffer_ff$D_OUT[72:9] : + ssNoSynth_1_w_buffer_enqw$wget[72:9] ; + assign near_mem_io$axi4_slave_wlast = + ssNoSynth_1_w_buffer_ff$EMPTY_N ? + ssNoSynth_1_w_buffer_ff$D_OUT[0] : + ssNoSynth_1_w_buffer_enqw$wget[0] ; + assign near_mem_io$axi4_slave_wstrb = + ssNoSynth_1_w_buffer_ff$EMPTY_N ? + ssNoSynth_1_w_buffer_ff$D_OUT[8:1] : + ssNoSynth_1_w_buffer_enqw$wget[8:1] ; assign near_mem_io$set_addr_map_addr_base = - soc_map$m_near_mem_io_addr_base ; - assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ; + soc_map$m_near_mem_io_addr_range[127:64] ; + assign near_mem_io$set_addr_map_addr_lim = y__h20569 ; assign near_mem_io$EN_server_reset_request_put = WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start || WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ; @@ -3385,42 +7500,114 @@ module mkCore(CLK, CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign near_mem_io$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign near_mem_io$axi4_slave_awvalid = + CAN_FIRE_RL_ssNoSynth_1_aw_forwardFlit ; + assign near_mem_io$axi4_slave_wvalid = + CAN_FIRE_RL_ssNoSynth_1_w_forwardFlit ; + assign near_mem_io$axi4_slave_arvalid = + CAN_FIRE_RL_ssNoSynth_1_ar_forwardFlit ; assign near_mem_io$EN_get_timer_interrupt_req_get = near_mem_io$RDY_get_timer_interrupt_req_get ; assign near_mem_io$EN_get_sw_interrupt_req_get = near_mem_io$RDY_get_sw_interrupt_req_get ; // submodule plic - assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ; - assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ; - assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ; - assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ; - assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ; - assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ; - assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ; - assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ; - assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ; - assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ; - assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ; - assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ; - assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ; - assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ; - assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ; - assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ; - assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ; - assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ; - assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ; - assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ; - assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ; - assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ; - assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ; - assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ; - assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ; - assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ; - assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ; - assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ; - assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ; - assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ; + assign plic$axi4_slave_araddr = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[92:29] : + ssNoSynth_2_ar_buffer_enqw$wget[92:29] ; + assign plic$axi4_slave_arburst = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[17:16] : + ssNoSynth_2_ar_buffer_enqw$wget[17:16] ; + assign plic$axi4_slave_arcache = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[14:11] : + ssNoSynth_2_ar_buffer_enqw$wget[14:11] ; + assign plic$axi4_slave_arid = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[97:93] : + ssNoSynth_2_ar_buffer_enqw$wget[97:93] ; + assign plic$axi4_slave_arlen = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[28:21] : + ssNoSynth_2_ar_buffer_enqw$wget[28:21] ; + assign plic$axi4_slave_arlock = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[15] : + ssNoSynth_2_ar_buffer_enqw$wget[15] ; + assign plic$axi4_slave_arprot = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[10:8] : + ssNoSynth_2_ar_buffer_enqw$wget[10:8] ; + assign plic$axi4_slave_arqos = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[7:4] : + ssNoSynth_2_ar_buffer_enqw$wget[7:4] ; + assign plic$axi4_slave_arregion = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[3:0] : + ssNoSynth_2_ar_buffer_enqw$wget[3:0] ; + assign plic$axi4_slave_arsize = + ssNoSynth_2_ar_buffer_ff$EMPTY_N ? + ssNoSynth_2_ar_buffer_ff$D_OUT[20:18] : + ssNoSynth_2_ar_buffer_enqw$wget[20:18] ; + assign plic$axi4_slave_awaddr = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[92:29] : + ssNoSynth_2_aw_buffer_enqw$wget[92:29] ; + assign plic$axi4_slave_awburst = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[17:16] : + ssNoSynth_2_aw_buffer_enqw$wget[17:16] ; + assign plic$axi4_slave_awcache = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[14:11] : + ssNoSynth_2_aw_buffer_enqw$wget[14:11] ; + assign plic$axi4_slave_awid = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[97:93] : + ssNoSynth_2_aw_buffer_enqw$wget[97:93] ; + assign plic$axi4_slave_awlen = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[28:21] : + ssNoSynth_2_aw_buffer_enqw$wget[28:21] ; + assign plic$axi4_slave_awlock = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[15] : + ssNoSynth_2_aw_buffer_enqw$wget[15] ; + assign plic$axi4_slave_awprot = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[10:8] : + ssNoSynth_2_aw_buffer_enqw$wget[10:8] ; + assign plic$axi4_slave_awqos = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[7:4] : + ssNoSynth_2_aw_buffer_enqw$wget[7:4] ; + assign plic$axi4_slave_awregion = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[3:0] : + ssNoSynth_2_aw_buffer_enqw$wget[3:0] ; + assign plic$axi4_slave_awsize = + ssNoSynth_2_aw_buffer_ff$EMPTY_N ? + ssNoSynth_2_aw_buffer_ff$D_OUT[20:18] : + ssNoSynth_2_aw_buffer_enqw$wget[20:18] ; + assign plic$axi4_slave_bready = ssNoSynth_2_b_dwReady$whas ; + assign plic$axi4_slave_rready = ssNoSynth_2_r_dwReady$whas ; + assign plic$axi4_slave_wdata = + ssNoSynth_2_w_buffer_ff$EMPTY_N ? + ssNoSynth_2_w_buffer_ff$D_OUT[72:9] : + ssNoSynth_2_w_buffer_enqw$wget[72:9] ; + assign plic$axi4_slave_wlast = + ssNoSynth_2_w_buffer_ff$EMPTY_N ? + ssNoSynth_2_w_buffer_ff$D_OUT[0] : + ssNoSynth_2_w_buffer_enqw$wget[0] ; + assign plic$axi4_slave_wstrb = + ssNoSynth_2_w_buffer_ff$EMPTY_N ? + ssNoSynth_2_w_buffer_ff$D_OUT[8:1] : + ssNoSynth_2_w_buffer_enqw$wget[8:1] ; + assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_range[127:64] ; + assign plic$set_addr_map_addr_lim = y__h20593 ; assign plic$set_verbosity_verbosity = 4'h0 ; assign plic$v_sources_0_m_interrupt_req_set_not_clear = core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ; @@ -3462,12 +7649,178 @@ module mkCore(CLK, assign plic$EN_server_reset_response_get = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ; + assign plic$axi4_slave_awvalid = CAN_FIRE_RL_ssNoSynth_2_aw_forwardFlit ; + assign plic$axi4_slave_wvalid = CAN_FIRE_RL_ssNoSynth_2_w_forwardFlit ; + assign plic$axi4_slave_arvalid = CAN_FIRE_RL_ssNoSynth_2_ar_forwardFlit ; + + // submodule shim_arff + assign shim_arff$D_IN = + ssNoSynth_0_ar_buffer_ff$EMPTY_N ? + ssNoSynth_0_ar_buffer_ff$D_OUT : + ssNoSynth_0_ar_buffer_enqw$wget ; + assign shim_arff$ENQ = + WILL_FIRE_RL_ssNoSynth_0_ar_forwardFlit && shim_arff$FULL_N ; + assign shim_arff$DEQ = shim_arff$EMPTY_N && cpu_dmem_master_arready ; + assign shim_arff$CLR = 1'b0 ; + + // submodule shim_awff + assign shim_awff$D_IN = + ssNoSynth_0_aw_buffer_ff$EMPTY_N ? + ssNoSynth_0_aw_buffer_ff$D_OUT : + split_0_doPut$wget[170:73] ; + assign shim_awff$ENQ = + WILL_FIRE_RL_ssNoSynth_0_aw_forwardFlit && shim_awff$FULL_N ; + assign shim_awff$DEQ = shim_awff$EMPTY_N && cpu_dmem_master_awready ; + assign shim_awff$CLR = 1'b0 ; + + // submodule shim_bff + assign shim_bff$D_IN = { cpu_dmem_master_bid, cpu_dmem_master_bresp } ; + assign shim_bff$ENQ = cpu_dmem_master_bvalid && shim_bff$FULL_N ; + assign shim_bff$DEQ = shim_bff$EMPTY_N && ssNoSynth_0_b_dwReady$whas ; + assign shim_bff$CLR = 1'b0 ; + + // submodule shim_rff + assign shim_rff$D_IN = + { cpu_dmem_master_rid, + cpu_dmem_master_rdata, + cpu_dmem_master_rresp, + cpu_dmem_master_rlast } ; + assign shim_rff$ENQ = cpu_dmem_master_rvalid && shim_rff$FULL_N ; + assign shim_rff$DEQ = shim_rff$EMPTY_N && ssNoSynth_0_r_dwReady$whas ; + assign shim_rff$CLR = 1'b0 ; + + // submodule shim_wff + assign shim_wff$D_IN = + ssNoSynth_0_w_buffer_ff$EMPTY_N ? + ssNoSynth_0_w_buffer_ff$D_OUT : + split_0_doPut$wget[72:0] ; + assign shim_wff$ENQ = + WILL_FIRE_RL_ssNoSynth_0_w_forwardFlit && shim_wff$FULL_N ; + assign shim_wff$DEQ = shim_wff$EMPTY_N && cpu_dmem_master_wready ; + assign shim_wff$CLR = 1'b0 ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; assign soc_map$m_is_mem_addr_addr = 64'h0 ; assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; + // submodule ssNoSynth_0_ar_buffer_ff + assign ssNoSynth_0_ar_buffer_ff$D_IN = ssNoSynth_0_ar_buffer_enqw$wget ; + assign ssNoSynth_0_ar_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_enqueue ; + assign ssNoSynth_0_ar_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_ar_buffer_dequeue ; + assign ssNoSynth_0_ar_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_0_ar_buffer_firstValid + assign ssNoSynth_0_ar_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_ar_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_ar_dropFlit ; + + // submodule ssNoSynth_0_aw_buffer_ff + assign ssNoSynth_0_aw_buffer_ff$D_IN = split_0_doPut$wget[170:73] ; + assign ssNoSynth_0_aw_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_enqueue ; + assign ssNoSynth_0_aw_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_aw_buffer_dequeue ; + assign ssNoSynth_0_aw_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_0_aw_buffer_firstValid + assign ssNoSynth_0_aw_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_aw_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_aw_dropFlit ; + + // submodule ssNoSynth_0_w_buffer_ff + assign ssNoSynth_0_w_buffer_ff$D_IN = split_0_doPut$wget[72:0] ; + assign ssNoSynth_0_w_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_enqueue ; + assign ssNoSynth_0_w_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_0_w_buffer_dequeue ; + assign ssNoSynth_0_w_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_0_w_buffer_firstValid + assign ssNoSynth_0_w_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_0_w_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_0_w_dropFlit ; + + // submodule ssNoSynth_1_ar_buffer_ff + assign ssNoSynth_1_ar_buffer_ff$D_IN = ssNoSynth_1_ar_buffer_enqw$wget ; + assign ssNoSynth_1_ar_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_enqueue ; + assign ssNoSynth_1_ar_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_ar_buffer_dequeue ; + assign ssNoSynth_1_ar_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_ar_buffer_firstValid + assign ssNoSynth_1_ar_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_ar_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_ar_dropFlit ; + + // submodule ssNoSynth_1_aw_buffer_ff + assign ssNoSynth_1_aw_buffer_ff$D_IN = split_1_doPut$wget[170:73] ; + assign ssNoSynth_1_aw_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_enqueue ; + assign ssNoSynth_1_aw_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_aw_buffer_dequeue ; + assign ssNoSynth_1_aw_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_aw_buffer_firstValid + assign ssNoSynth_1_aw_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_aw_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_aw_dropFlit ; + + // submodule ssNoSynth_1_w_buffer_ff + assign ssNoSynth_1_w_buffer_ff$D_IN = split_1_doPut$wget[72:0] ; + assign ssNoSynth_1_w_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_enqueue ; + assign ssNoSynth_1_w_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_1_w_buffer_dequeue ; + assign ssNoSynth_1_w_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_1_w_buffer_firstValid + assign ssNoSynth_1_w_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_1_w_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_1_w_dropFlit ; + + // submodule ssNoSynth_2_ar_buffer_ff + assign ssNoSynth_2_ar_buffer_ff$D_IN = ssNoSynth_2_ar_buffer_enqw$wget ; + assign ssNoSynth_2_ar_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_enqueue ; + assign ssNoSynth_2_ar_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_ar_buffer_dequeue ; + assign ssNoSynth_2_ar_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_ar_buffer_firstValid + assign ssNoSynth_2_ar_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_ar_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_ar_dropFlit ; + + // submodule ssNoSynth_2_aw_buffer_ff + assign ssNoSynth_2_aw_buffer_ff$D_IN = split_2_doPut$wget[170:73] ; + assign ssNoSynth_2_aw_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_enqueue ; + assign ssNoSynth_2_aw_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_aw_buffer_dequeue ; + assign ssNoSynth_2_aw_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_aw_buffer_firstValid + assign ssNoSynth_2_aw_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_aw_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_aw_dropFlit ; + + // submodule ssNoSynth_2_w_buffer_ff + assign ssNoSynth_2_w_buffer_ff$D_IN = split_2_doPut$wget[72:0] ; + assign ssNoSynth_2_w_buffer_ff$ENQ = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_enqueue ; + assign ssNoSynth_2_w_buffer_ff$DEQ = + CAN_FIRE_RL_ssNoSynth_2_w_buffer_dequeue ; + assign ssNoSynth_2_w_buffer_ff$CLR = 1'b0 ; + + // submodule ssNoSynth_2_w_buffer_firstValid + assign ssNoSynth_2_w_buffer_firstValid$D_IN = 1'd1 ; + assign ssNoSynth_2_w_buffer_firstValid$EN = + CAN_FIRE_RL_ssNoSynth_2_w_dropFlit ; + // submodule tv_encode assign tv_encode$trace_data_in_put = f_trace_data_merged$D_OUT ; assign tv_encode$EN_reset = 1'b0 ; @@ -3475,10 +7828,786 @@ module mkCore(CLK, assign tv_encode$EN_tv_vb_out_get = EN_tv_verifier_info_get_get ; // remaining internal signals - assign fabric_2x3_RDY_reset_AND_cpu_RDY_hart0_server__ETC___d9 = - fabric_2x3$RDY_reset && cpu$RDY_hart0_server_reset_request_put && + assign IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d779 = + ((IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771) && + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775)) ? + 2'd1 : + 2'd0 ; + assign IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d783 = + IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d779 + + ((!IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771) ? + 2'd1 : + 2'd0) ; + assign IF_IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dm_ETC___d787 = + ((IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 || + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771) && + !IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774 && + IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775) ? + 2'd1 : + 2'd0 ; + assign IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d876 = + ((IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868) && + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872)) ? + 2'd1 : + 2'd0 ; + assign IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d880 = + IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d876 + + ((!IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868) ? + 2'd1 : + 2'd0) ; + assign IF_IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ETC___d884 = + ((IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 || + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868) && + !IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871 && + IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872) ? + 2'd1 : + 2'd0 ; + assign IF_NOT_ifcs_0_1_innerRoute_first__638_BIT_1_64_ETC___d1660 = + (!ifcs_0_1_innerRoute$D_OUT[1] || + !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + ifcs_0_1_innerRoute$D_OUT[2] && + ssNoSynth_2_ar_buffer_ff$FULL_N : + ifcs_0_1_innerRoute$D_OUT[1] ; + assign IF_NOT_ifcs_0_innerRoute_first__000_BIT_1_009__ETC___d1022 = + (!ifcs_0_innerRoute$D_OUT[1] || + !IF_split_1_flitLeft_03_EQ_0_04_THEN_ssNoSynth__ETC___d993) ? + ifcs_0_innerRoute$D_OUT[2] && + IF_split_2_flitLeft_32_EQ_0_33_THEN_ssNoSynth__ETC___d994 : + ifcs_0_innerRoute$D_OUT[1] ; + assign IF_NOT_ifcs_1_1_innerRoute_first__667_BIT_1_67_ETC___d1676 = + (!ifcs_1_1_innerRoute$D_OUT[1] || + !ssNoSynth_1_ar_buffer_ff$FULL_N) ? + ifcs_1_1_innerRoute$D_OUT[2] && + ssNoSynth_2_ar_buffer_ff$FULL_N : + ifcs_1_1_innerRoute$D_OUT[1] ; + assign IF_NOT_ifcs_1_innerRoute_first__029_BIT_1_033__ETC___d1038 = + (!ifcs_1_innerRoute$D_OUT[1] || + !IF_split_1_flitLeft_03_EQ_0_04_THEN_ssNoSynth__ETC___d993) ? + ifcs_1_innerRoute$D_OUT[2] && + IF_split_2_flitLeft_32_EQ_0_33_THEN_ssNoSynth__ETC___d994 : + ifcs_1_innerRoute$D_OUT[1] ; + assign IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1912 = + (SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 || + SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 || + SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893) ? + x__h77916 | y__h77917 : + arbiter_1_1_lastSelect ; + assign IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1918 = + (SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 || + SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 || + SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893) ? + x__h78104 | y__h78105 : + arbiter_1_1_lastSelect_1 ; + assign IF_SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_8_ETC___d1924 = + (SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 || + SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 || + SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893) ? + x__h78285 | y__h78286 : + arbiter_1_1_firstHot ; + assign IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1284 = + (SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 || + SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 || + SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265) ? + x__h46617 | y__h46618 : + arbiter_1_lastSelect ; + assign IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1290 = + (SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 || + SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 || + SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265) ? + x__h46805 | y__h46806 : + arbiter_1_lastSelect_1 ; + assign IF_SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_ETC___d1296 = + (SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 || + SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 || + SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265) ? + x__h46986 | y__h46987 : + arbiter_1_firstHot ; + assign IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1712 = + (SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 || + SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700) ? + x__h65974 | y__h65975 : + arbiter_1_lastSelect_2 ; + assign IF_SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_6_ETC___d1716 = + (SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 || + SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700) ? + x__h66115 | y__h66116 : + arbiter_1_firstHot_1 ; + assign IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1074 = + (SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 || + SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062) ? + x__h32134 | y__h32135 : + arbiter_lastSelect ; + assign IF_SEXT_arbiter_lastSelect_050_051_BIT_0_052_A_ETC___d1078 = + (SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 || + SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062) ? + x__h32275 | y__h32276 : + arbiter_firstHot ; + assign IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1420 = + ((cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412) && + (cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416)) ? + 2'd1 : + 2'd0 ; + assign IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1424 = + IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1420 + + ((!cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 && + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412) ? + 2'd1 : + 2'd0) ; + assign IF_cpu_dmem_master_ar_araddr__410_ULT_soc_map__ETC___d1428 = + ((cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 || + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412) && + !cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415 && + cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416) ? + 2'd1 : + 2'd0 ; + assign IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1506 = + ((dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498) && + (dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502)) ? + 2'd1 : + 2'd0 ; + assign IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1510 = + IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1506 + + ((!dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 && + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498) ? + 2'd1 : + 2'd0) ; + assign IF_dm_mem_tap_master_ar_araddr__496_ULT_soc_ma_ETC___d1514 = + ((dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 || + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498) && + !dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501 && + dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502) ? + 2'd1 : + 2'd0 ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d760 = + ((merged_0_flitLeft == 8'd0) ? + !cpu$dmem_master_awvalid || !cpu$dmem_master_wvalid : + !cpu$dmem_master_wvalid) || + merged_0_flitLeft != 8'd0 ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d821 = + (IF_merged_0_flitLeft_30_EQ_0_31_THEN_NOT_cpu_d_ETC___d760 || + cpu$dmem_master_awvalid) && + (merged_0_flitLeft != 8'd0 || + !ifcs_0_noRoute_inner_pendingReq && cpu$dmem_master_awvalid) ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d753 = + (merged_0_flitLeft == 8'd0) ? + cpu$dmem_master_awvalid && cpu$dmem_master_wvalid : + cpu$dmem_master_wvalid ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d770 = + cpu$dmem_master_awaddr < + soc_map$m_near_mem_io_addr_range[127:64] ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d771 = + cpu$dmem_master_awaddr < y__h20569 ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d774 = + cpu$dmem_master_awaddr < soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_0_flitLeft_30_EQ_0_31_THEN_cpu_dmem__ETC___d775 = + cpu$dmem_master_awaddr < y__h20593 ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d857 = + ((merged_1_flitLeft == 8'd0) ? + !dm_mem_tap$master_awvalid || !dm_mem_tap$master_wvalid : + !dm_mem_tap$master_wvalid) || + merged_1_flitLeft != 8'd0 ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d918 = + (IF_merged_1_flitLeft_50_EQ_0_51_THEN_NOT_dm_me_ETC___d857 || + dm_mem_tap$master_awvalid) && + (merged_1_flitLeft != 8'd0 || + !ifcs_1_noRoute_inner_pendingReq && dm_mem_tap$master_awvalid) ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d850 = + (merged_1_flitLeft == 8'd0) ? + dm_mem_tap$master_awvalid && dm_mem_tap$master_wvalid : + dm_mem_tap$master_wvalid ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d867 = + dm_mem_tap$master_awaddr < + soc_map$m_near_mem_io_addr_range[127:64] ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d868 = + dm_mem_tap$master_awaddr < y__h20569 ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d871 = + dm_mem_tap$master_awaddr < soc_map$m_plic_addr_range[127:64] ; + assign IF_merged_1_flitLeft_50_EQ_0_51_THEN_dm_mem_ta_ETC___d872 = + dm_mem_tap$master_awaddr < y__h20593 ; + assign IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992 = + (split_0_flitLeft == 8'd0) ? + ssNoSynth_0_aw_buffer_ff$FULL_N && + ssNoSynth_0_w_buffer_ff$FULL_N : + ssNoSynth_0_w_buffer_ff$FULL_N ; + assign IF_split_1_flitLeft_03_EQ_0_04_THEN_ssNoSynth__ETC___d993 = + (split_1_flitLeft == 8'd0) ? + ssNoSynth_1_aw_buffer_ff$FULL_N && + ssNoSynth_1_w_buffer_ff$FULL_N : + ssNoSynth_1_w_buffer_ff$FULL_N ; + assign IF_split_2_flitLeft_32_EQ_0_33_THEN_ssNoSynth__ETC___d994 = + (split_2_flitLeft == 8'd0) ? + ssNoSynth_2_aw_buffer_ff$FULL_N && + ssNoSynth_2_w_buffer_ff$FULL_N : + ssNoSynth_2_w_buffer_ff$FULL_N ; + assign SEXT_SEXT_arbiter_1_1_firstHot_877_878_BIT_0_8_ETC__q18 = + {2{SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893}} ; + assign SEXT_SEXT_arbiter_1_firstHot_1_692_693_BIT_0_6_ETC__q13 = + {2{SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700}} ; + assign SEXT_SEXT_arbiter_1_firstHot_249_250_BIT_0_251_ETC__q8 = + {2{SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265}} ; + assign SEXT_SEXT_arbiter_firstHot_054_055_BIT_0_056_A_ETC__q3 = + {2{SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062}} ; + assign SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893 = + x__h77444 | y__h77445 ; + assign SEXT_arbiter_1_1_firstHot__q15 = {2{arbiter_1_1_firstHot}} ; + assign SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 = + x__h77308 | y__h77309 ; + assign SEXT_arbiter_1_1_lastSelect_1__q17 = {2{arbiter_1_1_lastSelect_1}} ; + assign SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 = + x__h77157 | y__h77158 ; + assign SEXT_arbiter_1_1_lastSelect__q16 = {2{arbiter_1_1_lastSelect}} ; + assign SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700 = + x__h65609 | y__h65610 ; + assign SEXT_arbiter_1_firstHot_1__q11 = {2{arbiter_1_firstHot_1}} ; + assign SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265 = + x__h46145 | y__h46146 ; + assign SEXT_arbiter_1_firstHot__q5 = {2{arbiter_1_firstHot}} ; + assign SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 = + x__h46009 | y__h46010 ; + assign SEXT_arbiter_1_lastSelect_1__q7 = {2{arbiter_1_lastSelect_1}} ; + assign SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 = + x__h45858 | y__h45859 ; + assign SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 = + x__h65506 | y__h65507 ; + assign SEXT_arbiter_1_lastSelect_2__q12 = {2{arbiter_1_lastSelect_2}} ; + assign SEXT_arbiter_1_lastSelect__q6 = {2{arbiter_1_lastSelect}} ; + assign SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062 = + x__h31769 | y__h31770 ; + assign SEXT_arbiter_firstHot__q1 = {2{arbiter_firstHot}} ; + assign SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 = + x__h31666 | y__h31667 ; + assign SEXT_arbiter_lastSelect__q2 = {2{arbiter_lastSelect}} ; + assign SEXT_x2193__q4 = {2{x__h32193}} ; + assign SEXT_x6033__q14 = {2{x__h66033}} ; + assign SEXT_x6679__q9 = {2{x__h46679}} ; + assign SEXT_x6713__q10 = {2{x__h46713}} ; + assign SEXT_x7978__q19 = {2{x__h77978}} ; + assign SEXT_x8012__q20 = {2{x__h78012}} ; + assign a_awid__h21643 = { 1'd0, cpu$dmem_master_awid } ; + assign a_awid__h24357 = { 1'd1, dm_mem_tap$master_awid } ; + assign cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1411 = + cpu$dmem_master_araddr < + soc_map$m_near_mem_io_addr_range[127:64] ; + assign cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_n_ETC___d1412 = + cpu$dmem_master_araddr < y__h20569 ; + assign cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1415 = + cpu$dmem_master_araddr < soc_map$m_plic_addr_range[127:64] ; + assign cpu_dmem_master_ar_araddr__410_ULT_soc_map_m_p_ETC___d1416 = + cpu$dmem_master_araddr < y__h20593 ; + assign dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1497 = + dm_mem_tap$master_araddr < + soc_map$m_near_mem_io_addr_range[127:64] ; + assign dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1498 = + dm_mem_tap$master_araddr < y__h20569 ; + assign dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1501 = + dm_mem_tap$master_araddr < soc_map$m_plic_addr_range[127:64] ; + assign dm_mem_tap_master_ar_araddr__496_ULT_soc_map_m_ETC___d1502 = + dm_mem_tap$master_araddr < y__h20593 ; + assign fatReq_arid__h55399 = { 1'd0, cpu$dmem_master_arid } ; + assign fatReq_arid__h57824 = { 1'd1, dm_mem_tap$master_arid } ; + assign plic_RDY_server_reset_request_put_AND_cpu_RDY__ETC___d8 = + plic$RDY_server_reset_request_put && + cpu$RDY_hart0_server_reset_request_put && f_reset_reqs$EMPTY_N && f_reset_requestor$FULL_N ; + assign reqWires_1_0_whas__226_AND_reqWires_1_0_wget___ETC___d1236 = + CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget || + CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget || + CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget ; + assign reqWires_1_1_0_whas__854_AND_reqWires_1_1_0_wg_ETC___d1864 = + CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget || + CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget || + CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget ; + assign split_0_doPut_whas__66_AND_split_0_doPut_wget__ETC___d673 = + CAN_FIRE_RL_sink_selected && + (split_0_doPut$wget[171] || + ssNoSynth_0_aw_buffer_ff$FULL_N && + ssNoSynth_0_w_buffer_ff$FULL_N) ; + assign split_1_doPut_whas__95_AND_split_1_doPut_wget__ETC___d702 = + CAN_FIRE_RL_sink_selected_1 && + (split_1_doPut$wget[171] || + ssNoSynth_1_aw_buffer_ff$FULL_N && + ssNoSynth_1_w_buffer_ff$FULL_N) ; + assign split_2_doPut_whas__24_AND_split_2_doPut_wget__ETC___d731 = + CAN_FIRE_RL_sink_selected_2 && + (split_2_doPut$wget[171] || + ssNoSynth_2_aw_buffer_ff$FULL_N && + ssNoSynth_2_w_buffer_ff$FULL_N) ; + assign state_047_AND_activeSource_0_120_121_AND_ifcs__ETC___d1123 = + state && activeSource_0 && ifcs_0_innerRoute$EMPTY_N && + ((!ifcs_0_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992) ? + IF_NOT_ifcs_0_innerRoute_first__000_BIT_1_009__ETC___d1022 : + ifcs_0_innerRoute$D_OUT[0]) ; + assign state_047_AND_activeSource_1_164_165_AND_ifcs__ETC___d1167 = + state && activeSource_1 && ifcs_1_innerRoute$EMPTY_N && + ((!ifcs_1_innerRoute$D_OUT[0] || + !IF_split_0_flitLeft_74_EQ_0_75_THEN_ssNoSynth__ETC___d992) ? + IF_NOT_ifcs_1_innerRoute_first__029_BIT_1_033__ETC___d1038 : + ifcs_1_innerRoute$D_OUT[0]) ; + assign state_1_1_1_865_AND_activeSource_1_1_0_959_960_ETC___d1962 = + state_1_1_1 && activeSource_1_1_0 && + ifcs_0_1_routeBack$EMPTY_N && + ((!ifcs_0_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_0_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_0_1_routeBack$D_OUT[0]) ; + assign state_1_1_1_865_AND_activeSource_1_1_1_1_995_9_ETC___d1998 = + state_1_1_1 && activeSource_1_1_1_1 && + ifcs_1_1_routeBack$EMPTY_N && + ((!ifcs_1_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_1_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_1_1_routeBack$D_OUT[0]) ; + assign state_1_1_1_865_AND_activeSource_1_1_2_031_032_ETC___d2034 = + state_1_1_1 && activeSource_1_1_2 && + ifcs_2_1_routeBack$EMPTY_N && + ((!ifcs_2_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_1_drainNoRouteResponse)) ? + ifcs_2_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_1_drainNoRouteResponse : + ifcs_2_1_routeBack$D_OUT[0]) ; + assign state_1_1_685_AND_activeSource_1_0_1_752_753_A_ETC___d1755 = + state_1_1 && activeSource_1_0_1 && ifcs_0_1_innerRoute$EMPTY_N && + ((!ifcs_0_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_0_1_innerRoute_first__638_BIT_1_64_ETC___d1660 : + ifcs_0_1_innerRoute$D_OUT[0]) ; + assign state_1_1_685_AND_activeSource_1_1_1_792_793_A_ETC___d1795 = + state_1_1 && activeSource_1_1_1 && ifcs_1_1_innerRoute$EMPTY_N && + ((!ifcs_1_1_innerRoute$D_OUT[0] || + !ssNoSynth_0_ar_buffer_ff$FULL_N) ? + IF_NOT_ifcs_1_1_innerRoute_first__667_BIT_1_67_ETC___d1676 : + ifcs_1_1_innerRoute$D_OUT[0]) ; + assign state_1_237_AND_activeSource_1_0_325_326_AND_i_ETC___d1328 = + state_1 && activeSource_1_0 && ifcs_0_routeBack$EMPTY_N && + ((!ifcs_0_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_0_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_0_routeBack$D_OUT[0]) ; + assign state_1_237_AND_activeSource_1_1_358_359_AND_i_ETC___d1361 = + state_1 && activeSource_1_1 && ifcs_1_routeBack$EMPTY_N && + ((!ifcs_1_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_1_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_1_routeBack$D_OUT[0]) ; + assign state_1_237_AND_activeSource_1_2_392_393_AND_i_ETC___d1395 = + state_1 && activeSource_1_2 && ifcs_2_routeBack$EMPTY_N && + ((!ifcs_2_routeBack$D_OUT[0] || + !(!CAN_FIRE_RL_ifcs_0_drainNoRouteResponse)) ? + ifcs_2_routeBack$D_OUT[1] && + !CAN_FIRE_RL_ifcs_1_drainNoRouteResponse : + ifcs_2_routeBack$D_OUT[0]) ; + assign x__h31666 = + SEXT_arbiter_lastSelect__q2[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h31769 = + SEXT_arbiter_firstHot__q1[0] & + (CAN_FIRE_RL_craftReq && reqWires_0$wget) ; + assign x__h32134 = + SEXT_SEXT_arbiter_firstHot_054_055_BIT_0_056_A_ETC__q3[0] & + arbiter_firstHot ; + assign x__h32193 = + !SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062 && + SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 ; + assign x__h32275 = SEXT_x2193__q4[0] & arbiter_firstHot ; + assign x__h45858 = x__h45860 | y__h45861 ; + assign x__h45860 = + SEXT_arbiter_1_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h46009 = x__h46011 | y__h46012 ; + assign x__h46011 = + SEXT_arbiter_1_lastSelect_1__q7[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h46145 = x__h46147 | y__h46148 ; + assign x__h46147 = + SEXT_arbiter_1_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq_2 && reqWires_1_0$wget) ; + assign x__h46617 = x__h46619 | y__h46620 ; + assign x__h46619 = + SEXT_SEXT_arbiter_1_firstHot_249_250_BIT_0_251_ETC__q8[0] & + arbiter_1_firstHot ; + assign x__h46679 = + !SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265 && + SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 ; + assign x__h46713 = + !SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 && + !SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265 && + SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 ; + assign x__h46805 = x__h46807 | y__h46808 ; + assign x__h46807 = SEXT_x6679__q9[0] & arbiter_1_firstHot ; + assign x__h46986 = x__h46988 | y__h46989 ; + assign x__h46988 = SEXT_x6713__q10[0] & arbiter_1_firstHot ; + assign x__h65506 = + SEXT_arbiter_1_lastSelect_2__q12[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h65609 = + SEXT_arbiter_1_firstHot_1__q11[0] & + (CAN_FIRE_RL_craftReq_5 && reqWires_1_0_1$wget) ; + assign x__h65974 = + SEXT_SEXT_arbiter_1_firstHot_1_692_693_BIT_0_6_ETC__q13[0] & + arbiter_1_firstHot_1 ; + assign x__h66033 = + !SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700 && + SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 ; + assign x__h66115 = SEXT_x6033__q14[0] & arbiter_1_firstHot_1 ; + assign x__h77157 = x__h77159 | y__h77160 ; + assign x__h77159 = + SEXT_arbiter_1_1_lastSelect__q16[0] & + (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; + assign x__h77308 = x__h77310 | y__h77311 ; + assign x__h77310 = + SEXT_arbiter_1_1_lastSelect_1__q17[0] & + (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; + assign x__h77444 = x__h77446 | y__h77447 ; + assign x__h77446 = + SEXT_arbiter_1_1_firstHot__q15[0] & + (CAN_FIRE_RL_craftReq_7 && reqWires_1_1_0$wget) ; + assign x__h77916 = x__h77918 | y__h77919 ; + assign x__h77918 = + SEXT_SEXT_arbiter_1_1_firstHot_877_878_BIT_0_8_ETC__q18[0] & + arbiter_1_1_firstHot ; + assign x__h77978 = + !SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893 && + SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 ; + assign x__h78012 = + !SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 && + !SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893 && + SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 ; + assign x__h78104 = x__h78106 | y__h78107 ; + assign x__h78106 = SEXT_x7978__q19[0] & arbiter_1_1_firstHot ; + assign x__h78285 = x__h78287 | y__h78288 ; + assign x__h78287 = SEXT_x8012__q20[0] & arbiter_1_1_firstHot ; + assign x_port1__read__h55959 = + CAN_FIRE_RL_ifcs_0_1_nonRoutableFlit ? + ifcs_0_1_noRoute_flitCount$port0__write_1 : + ifcs_0_1_noRoute_flitCount ; + assign x_port1__read__h58381 = + CAN_FIRE_RL_ifcs_1_1_nonRoutableFlit ? + ifcs_1_1_noRoute_flitCount$port0__write_1 : + ifcs_1_1_noRoute_flitCount ; + assign y__h20569 = + soc_map$m_near_mem_io_addr_range[127:64] + + soc_map$m_near_mem_io_addr_range[63:0] ; + assign y__h20593 = + soc_map$m_plic_addr_range[127:64] + + soc_map$m_plic_addr_range[63:0] ; + assign y__h31667 = + SEXT_arbiter_firstHot__q1[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h31770 = + SEXT_arbiter_lastSelect__q2[0] & + (CAN_FIRE_RL_craftReq_1 && reqWires_1$wget) ; + assign y__h32135 = SEXT_x2193__q4[0] & arbiter_lastSelect ; + assign y__h32276 = + SEXT_SEXT_arbiter_firstHot_054_055_BIT_0_056_A_ETC__q3[0] & + arbiter_lastSelect ; + assign y__h45859 = + SEXT_arbiter_1_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h45861 = + SEXT_arbiter_1_lastSelect_1__q7[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h46010 = + SEXT_arbiter_1_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h46012 = + SEXT_arbiter_1_firstHot__q5[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h46146 = + SEXT_arbiter_1_lastSelect_1__q7[0] & + (CAN_FIRE_RL_craftReq_4 && reqWires_1_2$wget) ; + assign y__h46148 = + SEXT_arbiter_1_lastSelect__q6[0] & + (CAN_FIRE_RL_craftReq_3 && reqWires_1_1$wget) ; + assign y__h46618 = SEXT_x6713__q10[0] & arbiter_1_lastSelect ; + assign y__h46620 = SEXT_x6679__q9[0] & arbiter_1_lastSelect_1 ; + assign y__h46806 = + SEXT_SEXT_arbiter_1_firstHot_249_250_BIT_0_251_ETC__q8[0] & + arbiter_1_lastSelect ; + assign y__h46808 = SEXT_x6713__q10[0] & arbiter_1_lastSelect_1 ; + assign y__h46987 = SEXT_x6679__q9[0] & arbiter_1_lastSelect ; + assign y__h46989 = + SEXT_SEXT_arbiter_1_firstHot_249_250_BIT_0_251_ETC__q8[0] & + arbiter_1_lastSelect_1 ; + assign y__h65507 = + SEXT_arbiter_1_firstHot_1__q11[0] & + (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; + assign y__h65610 = + SEXT_arbiter_1_lastSelect_2__q12[0] & + (CAN_FIRE_RL_craftReq_6 && reqWires_1_1_1$wget) ; + assign y__h65975 = SEXT_x6033__q14[0] & arbiter_1_lastSelect_2 ; + assign y__h66116 = + SEXT_SEXT_arbiter_1_firstHot_1_692_693_BIT_0_6_ETC__q13[0] & + arbiter_1_lastSelect_2 ; + assign y__h77158 = + SEXT_arbiter_1_1_firstHot__q15[0] & + (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; + assign y__h77160 = + SEXT_arbiter_1_1_lastSelect_1__q17[0] & + (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; + assign y__h77309 = + SEXT_arbiter_1_1_lastSelect__q16[0] & + (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; + assign y__h77311 = + SEXT_arbiter_1_1_firstHot__q15[0] & + (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; + assign y__h77445 = + SEXT_arbiter_1_1_lastSelect_1__q17[0] & + (CAN_FIRE_RL_craftReq_9 && reqWires_1_1_2$wget) ; + assign y__h77447 = + SEXT_arbiter_1_1_lastSelect__q16[0] & + (CAN_FIRE_RL_craftReq_8 && reqWires_1_1_1_1$wget) ; + assign y__h77917 = SEXT_x8012__q20[0] & arbiter_1_1_lastSelect ; + assign y__h77919 = SEXT_x7978__q19[0] & arbiter_1_1_lastSelect_1 ; + assign y__h78105 = + SEXT_SEXT_arbiter_1_1_firstHot_877_878_BIT_0_8_ETC__q18[0] & + arbiter_1_1_lastSelect ; + assign y__h78107 = SEXT_x8012__q20[0] & arbiter_1_1_lastSelect_1 ; + assign y__h78286 = SEXT_x7978__q19[0] & arbiter_1_1_lastSelect ; + assign y__h78288 = + SEXT_SEXT_arbiter_1_1_firstHot_877_878_BIT_0_8_ETC__q18[0] & + arbiter_1_1_lastSelect_1 ; + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + activeSource_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; + activeSource_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_1_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_1_1_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_1_firstHot_1 <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_1_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_1_lastSelect_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; + arbiter_firstHot <= `BSV_ASSIGNMENT_DELAY 1'd1; + arbiter_lastSelect <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_0_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY 9'd0; + ifcs_0_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_0_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_0_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_0_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_0_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_1_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY 9'd0; + ifcs_1_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_1_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_1_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_1_state <= `BSV_ASSIGNMENT_DELAY 2'd0; + ifcs_1_state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_2_1_state <= `BSV_ASSIGNMENT_DELAY 1'd0; + ifcs_2_state <= `BSV_ASSIGNMENT_DELAY 1'd0; + merged_0_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + merged_1_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + split_0_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + split_1_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + split_2_flitLeft <= `BSV_ASSIGNMENT_DELAY 8'd0; + state <= `BSV_ASSIGNMENT_DELAY 1'd0; + state_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + state_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + state_1_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + end + else + begin + if (activeSource_0$EN) + activeSource_0 <= `BSV_ASSIGNMENT_DELAY activeSource_0$D_IN; + if (activeSource_1$EN) + activeSource_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1$D_IN; + if (activeSource_1_0$EN) + activeSource_1_0 <= `BSV_ASSIGNMENT_DELAY activeSource_1_0$D_IN; + if (activeSource_1_0_1$EN) + activeSource_1_0_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_0_1$D_IN; + if (activeSource_1_1$EN) + activeSource_1_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1$D_IN; + if (activeSource_1_1_0$EN) + activeSource_1_1_0 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_0$D_IN; + if (activeSource_1_1_1$EN) + activeSource_1_1_1 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_1$D_IN; + if (activeSource_1_1_1_1$EN) + activeSource_1_1_1_1 <= `BSV_ASSIGNMENT_DELAY + activeSource_1_1_1_1$D_IN; + if (activeSource_1_1_2$EN) + activeSource_1_1_2 <= `BSV_ASSIGNMENT_DELAY activeSource_1_1_2$D_IN; + if (activeSource_1_2$EN) + activeSource_1_2 <= `BSV_ASSIGNMENT_DELAY activeSource_1_2$D_IN; + if (arbiter_1_1_firstHot$EN) + arbiter_1_1_firstHot <= `BSV_ASSIGNMENT_DELAY + arbiter_1_1_firstHot$D_IN; + if (arbiter_1_1_lastSelect$EN) + arbiter_1_1_lastSelect <= `BSV_ASSIGNMENT_DELAY + arbiter_1_1_lastSelect$D_IN; + if (arbiter_1_1_lastSelect_1$EN) + arbiter_1_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_1_lastSelect_1$D_IN; + if (arbiter_1_firstHot$EN) + arbiter_1_firstHot <= `BSV_ASSIGNMENT_DELAY arbiter_1_firstHot$D_IN; + if (arbiter_1_firstHot_1$EN) + arbiter_1_firstHot_1 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_firstHot_1$D_IN; + if (arbiter_1_lastSelect$EN) + arbiter_1_lastSelect <= `BSV_ASSIGNMENT_DELAY + arbiter_1_lastSelect$D_IN; + if (arbiter_1_lastSelect_1$EN) + arbiter_1_lastSelect_1 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_lastSelect_1$D_IN; + if (arbiter_1_lastSelect_2$EN) + arbiter_1_lastSelect_2 <= `BSV_ASSIGNMENT_DELAY + arbiter_1_lastSelect_2$D_IN; + if (arbiter_firstHot$EN) + arbiter_firstHot <= `BSV_ASSIGNMENT_DELAY arbiter_firstHot$D_IN; + if (arbiter_lastSelect$EN) + arbiter_lastSelect <= `BSV_ASSIGNMENT_DELAY arbiter_lastSelect$D_IN; + if (ifcs_0_1_noRoute_currentReq$EN) + ifcs_0_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_0_1_noRoute_currentReq$D_IN; + if (ifcs_0_1_noRoute_flitCount$EN) + ifcs_0_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY + ifcs_0_1_noRoute_flitCount$D_IN; + if (ifcs_0_1_state$EN) + ifcs_0_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_0_1_state$D_IN; + if (ifcs_0_1_state_1$EN) + ifcs_0_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_0_1_state_1$D_IN; + if (ifcs_0_noRoute_inner_currentReq$EN) + ifcs_0_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_0_noRoute_inner_currentReq$D_IN; + if (ifcs_0_noRoute_inner_pendingReq$EN) + ifcs_0_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY + ifcs_0_noRoute_inner_pendingReq$D_IN; + if (ifcs_0_state$EN) + ifcs_0_state <= `BSV_ASSIGNMENT_DELAY ifcs_0_state$D_IN; + if (ifcs_0_state_1$EN) + ifcs_0_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_0_state_1$D_IN; + if (ifcs_1_1_noRoute_currentReq$EN) + ifcs_1_1_noRoute_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_1_1_noRoute_currentReq$D_IN; + if (ifcs_1_1_noRoute_flitCount$EN) + ifcs_1_1_noRoute_flitCount <= `BSV_ASSIGNMENT_DELAY + ifcs_1_1_noRoute_flitCount$D_IN; + if (ifcs_1_1_state$EN) + ifcs_1_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_1_1_state$D_IN; + if (ifcs_1_1_state_1$EN) + ifcs_1_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_1_1_state_1$D_IN; + if (ifcs_1_noRoute_inner_currentReq$EN) + ifcs_1_noRoute_inner_currentReq <= `BSV_ASSIGNMENT_DELAY + ifcs_1_noRoute_inner_currentReq$D_IN; + if (ifcs_1_noRoute_inner_pendingReq$EN) + ifcs_1_noRoute_inner_pendingReq <= `BSV_ASSIGNMENT_DELAY + ifcs_1_noRoute_inner_pendingReq$D_IN; + if (ifcs_1_state$EN) + ifcs_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_1_state$D_IN; + if (ifcs_1_state_1$EN) + ifcs_1_state_1 <= `BSV_ASSIGNMENT_DELAY ifcs_1_state_1$D_IN; + if (ifcs_2_1_state$EN) + ifcs_2_1_state <= `BSV_ASSIGNMENT_DELAY ifcs_2_1_state$D_IN; + if (ifcs_2_state$EN) + ifcs_2_state <= `BSV_ASSIGNMENT_DELAY ifcs_2_state$D_IN; + if (merged_0_flitLeft$EN) + merged_0_flitLeft <= `BSV_ASSIGNMENT_DELAY merged_0_flitLeft$D_IN; + if (merged_1_flitLeft$EN) + merged_1_flitLeft <= `BSV_ASSIGNMENT_DELAY merged_1_flitLeft$D_IN; + if (split_0_flitLeft$EN) + split_0_flitLeft <= `BSV_ASSIGNMENT_DELAY split_0_flitLeft$D_IN; + if (split_1_flitLeft$EN) + split_1_flitLeft <= `BSV_ASSIGNMENT_DELAY split_1_flitLeft$D_IN; + if (split_2_flitLeft$EN) + split_2_flitLeft <= `BSV_ASSIGNMENT_DELAY split_2_flitLeft$D_IN; + if (state$EN) state <= `BSV_ASSIGNMENT_DELAY state$D_IN; + if (state_1$EN) state_1 <= `BSV_ASSIGNMENT_DELAY state_1$D_IN; + if (state_1_1$EN) state_1_1 <= `BSV_ASSIGNMENT_DELAY state_1_1$D_IN; + if (state_1_1_1$EN) + state_1_1_1 <= `BSV_ASSIGNMENT_DELAY state_1_1_1$D_IN; + end + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + activeSource_0 = 1'h0; + activeSource_1 = 1'h0; + activeSource_1_0 = 1'h0; + activeSource_1_0_1 = 1'h0; + activeSource_1_1 = 1'h0; + activeSource_1_1_0 = 1'h0; + activeSource_1_1_1 = 1'h0; + activeSource_1_1_1_1 = 1'h0; + activeSource_1_1_2 = 1'h0; + activeSource_1_2 = 1'h0; + arbiter_1_1_firstHot = 1'h0; + arbiter_1_1_lastSelect = 1'h0; + arbiter_1_1_lastSelect_1 = 1'h0; + arbiter_1_firstHot = 1'h0; + arbiter_1_firstHot_1 = 1'h0; + arbiter_1_lastSelect = 1'h0; + arbiter_1_lastSelect_1 = 1'h0; + arbiter_1_lastSelect_2 = 1'h0; + arbiter_firstHot = 1'h0; + arbiter_lastSelect = 1'h0; + ifcs_0_1_noRoute_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_1_noRoute_flitCount = 9'h0AA; + ifcs_0_1_state = 2'h2; + ifcs_0_1_state_1 = 1'h0; + ifcs_0_noRoute_inner_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_0_noRoute_inner_pendingReq = 1'h0; + ifcs_0_state = 2'h2; + ifcs_0_state_1 = 1'h0; + ifcs_1_1_noRoute_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_1_noRoute_flitCount = 9'h0AA; + ifcs_1_1_state = 2'h2; + ifcs_1_1_state_1 = 1'h0; + ifcs_1_noRoute_inner_currentReq = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + ifcs_1_noRoute_inner_pendingReq = 1'h0; + ifcs_1_state = 2'h2; + ifcs_1_state_1 = 1'h0; + ifcs_2_1_state = 1'h0; + ifcs_2_state = 1'h0; + merged_0_flitLeft = 8'hAA; + merged_1_flitLeft = 8'hAA; + split_0_flitLeft = 8'hAA; + split_1_flitLeft = 8'hAA; + split_2_flitLeft = 8'hAA; + state = 1'h0; + state_1 = 1'h0; + state_1_1 = 1'h0; + state_1_1_1 = 1'h0; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on // handling of system tasks @@ -3486,36 +8615,1663 @@ module mkCore(CLK, always@(negedge CLK) begin #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate && + !SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 && + !SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate && + !SEXT_arbiter_lastSelect_050_051_BIT_0_052_AND__ETC___d1058 && + !SEXT_arbiter_firstHot_054_055_BIT_0_056_AND_re_ETC___d1062) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h33674 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h33674, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && ifcs_0_innerRoute$EMPTY_N && + (ifcs_0_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) + begin + v__h33063 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h33063, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && !ifcs_0_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h37683 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h37683, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && ifcs_1_innerRoute$EMPTY_N && + (ifcs_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) + begin + v__h37072 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h37072, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && !ifcs_1_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected && WILL_FIRE_RL_burst) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 113, column 32: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected] and\n [RL_burst] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected || WILL_FIRE_RL_burst) && + (WILL_FIRE_RL_source_selected_1 || WILL_FIRE_RL_burst_1)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected, RL_burst]\n and [RL_source_selected_1, RL_burst_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_1 && WILL_FIRE_RL_burst_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_1] and\n [RL_burst_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected && WILL_FIRE_RL_sink_selected_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected] and\n [RL_sink_selected_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_sink_selected || WILL_FIRE_RL_sink_selected_1) && + WILL_FIRE_RL_sink_selected_2) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected,\n RL_sink_selected_1] and [RL_sink_selected_2] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_2 && + !SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 && + !SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_2 && + !SEXT_arbiter_1_lastSelect_2_688_689_BIT_0_690__ETC___d1696 && + !SEXT_arbiter_1_firstHot_1_692_693_BIT_0_694_AN_ETC___d1700) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h67508 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h67508, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && ifcs_0_1_innerRoute$EMPTY_N && + (ifcs_0_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_0_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) + begin + v__h66897 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h66897, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && !ifcs_0_1_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h70401 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h70401, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && ifcs_1_1_innerRoute$EMPTY_N && + (ifcs_1_1_innerRoute$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[1] ? 2'd1 : 2'd0) + + (ifcs_1_1_innerRoute$D_OUT[2] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) + begin + v__h69790 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h69790, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && !ifcs_1_1_innerRoute$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_5 && WILL_FIRE_RL_burst_5) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_5] and\n [RL_burst_5] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_5 || WILL_FIRE_RL_burst_5) && + (WILL_FIRE_RL_source_selected_6 || WILL_FIRE_RL_burst_6)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_5,\n RL_burst_5] and [RL_source_selected_6, RL_burst_6] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_6 && WILL_FIRE_RL_burst_6) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_6] and\n [RL_burst_6] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_5 && WILL_FIRE_RL_sink_selected_6) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5] and\n [RL_sink_selected_6] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_sink_selected_5 || WILL_FIRE_RL_sink_selected_6) && + WILL_FIRE_RL_sink_selected_7) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_5,\n RL_sink_selected_6] and [RL_sink_selected_7] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[171]) + $display("Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putFirst && split_0_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] && + split_0_doPut$wget[0] && + split_0_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] && + split_0_doPut$wget[0] && + split_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] && + !split_0_doPut$wget[0] && + split_0_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && split_0_doPut$wget[171] && + !split_0_doPut$wget[0] && + split_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[171]) + $display("Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_0_putOther && !split_0_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[171]) + $display("Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putFirst && split_1_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] && + split_1_doPut$wget[0] && + split_1_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] && + split_1_doPut$wget[0] && + split_1_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] && + !split_1_doPut$wget[0] && + split_1_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && split_1_doPut$wget[171] && + !split_1_doPut$wget[0] && + split_1_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[171]) + $display("Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_1_putOther && !split_1_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[171]) + $display("Expecting FirstFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putFirst && split_2_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] && + split_2_doPut$wget[0] && + split_2_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] && + split_2_doPut$wget[0] && + split_2_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] && + !split_2_doPut$wget[0] && + split_2_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && split_2_doPut$wget[171] && + !split_2_doPut$wget[0] && + split_2_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[171]) + $display("Expecting OtherFlit of merged write"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_split_2_putOther && !split_2_doPut$wget[171]) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_nonRoutableFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 && + !SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 && + !SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_1 && + !SEXT_arbiter_1_lastSelect_240_241_BIT_0_242_AN_ETC___d1253 && + !SEXT_arbiter_1_lastSelect_1_244_245_BIT_0_246__ETC___d1259 && + !SEXT_arbiter_1_firstHot_249_250_BIT_0_251_AND__ETC___d1265) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h48378 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h48378, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && ifcs_0_routeBack$EMPTY_N && + (ifcs_0_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + begin + v__h47997 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h47997, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && !ifcs_0_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h50448 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h50448, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && ifcs_1_routeBack$EMPTY_N && + (ifcs_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + begin + v__h50067 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h50067, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && !ifcs_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_3 && WILL_FIRE_RL_burst_3) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_3] and\n [RL_burst_3] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h52347 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h52347, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && ifcs_2_routeBack$EMPTY_N && + (ifcs_2_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + begin + v__h51966 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h51966, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && !ifcs_2_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_2 && WILL_FIRE_RL_burst_2) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2] and\n [RL_burst_2] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2) && + (WILL_FIRE_RL_source_selected_3 || WILL_FIRE_RL_burst_3)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2] and [RL_source_selected_3, RL_burst_3] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_2 || WILL_FIRE_RL_burst_2 || + WILL_FIRE_RL_source_selected_3 || + WILL_FIRE_RL_burst_3) && + (WILL_FIRE_RL_source_selected_4 || WILL_FIRE_RL_burst_4)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_2,\n RL_burst_2, RL_source_selected_3, RL_burst_3] and [RL_source_selected_4,\n RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_4 && WILL_FIRE_RL_burst_4) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_4] and\n [RL_burst_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_3 && WILL_FIRE_RL_sink_selected_4) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_3] and\n [RL_sink_selected_4] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_forwardRsp) + begin + v__h22294 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_forwardRsp) + $display("%0t: Forwarding 0x%x", + v__h22294, + MUX_msNoSynth_0_b_buffer_enqw$wset_1__VAL_1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit && WILL_FIRE_RL_ifcs_0_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit] and\n [RL_ifcs_0_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && WILL_FIRE_RL_ifcs_0_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_followFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_followFlits] and\n [RL_ifcs_0_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_drainFlits && + WILL_FIRE_RL_ifcs_0_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_drainFlits] and\n [RL_ifcs_0_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && cpu$dmem_master_wlast && + merged_0_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && cpu$dmem_master_wlast && + merged_0_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !cpu$dmem_master_wlast && + merged_0_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_0_genOther && !cpu$dmem_master_wlast && + merged_0_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_forwardRsp) + begin + v__h25002 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_forwardRsp) + $display("%0t: Forwarding 0x%x", + v__h25002, + MUX_msNoSynth_1_b_buffer_enqw$wset_1__VAL_1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_followFlits_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 285, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_firstFlit_1] and\n [RL_ifcs_0_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_1_followFlits_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 285, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit_1] and\n [RL_ifcs_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_3 && + !SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 && + !SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 && + !SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893) + $display("mkOneHotArbiter: next method should not be run with no pending request"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_arbitrate_3 && + !SEXT_arbiter_1_1_lastSelect_868_869_BIT_0_870__ETC___d1881 && + !SEXT_arbiter_1_1_lastSelect_1_872_873_BIT_0_87_ETC___d1887 && + !SEXT_arbiter_1_1_firstHot_877_878_BIT_0_879_AN_ETC___d1893) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h79681 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h79681, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && ifcs_0_1_routeBack$EMPTY_N && + (ifcs_0_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_0_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) + begin + v__h79300 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h79300, + $signed(32'd0)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && !ifcs_0_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h82172 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h82172, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && ifcs_1_1_routeBack$EMPTY_N && + (ifcs_1_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_1_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) + begin + v__h81791 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h81791, + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && !ifcs_1_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_8 && WILL_FIRE_RL_burst_8) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_8] and\n [RL_burst_8] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + begin + v__h84482 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write("%0t -- mkOneWayBus error: input %0d was selected but the", + " requested path ", + v__h84482, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $write(" is not a valid one-hot path.", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && ifcs_2_1_routeBack$EMPTY_N && + (ifcs_2_1_routeBack$D_OUT[0] ? 2'd1 : 2'd0) + + (ifcs_2_1_routeBack$D_OUT[1] ? 2'd1 : 2'd0) != + 2'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) + begin + v__h84101 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) + $display("%0t -- mkOneWayBus error: input %0d was selected but there", + " was no requested path.", + v__h84101, + $signed(32'd2)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && !ifcs_2_1_routeBack$EMPTY_N) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_7 && WILL_FIRE_RL_burst_7) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7] and\n [RL_burst_7] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_7 || WILL_FIRE_RL_burst_7) && + (WILL_FIRE_RL_source_selected_8 || WILL_FIRE_RL_burst_8)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7,\n RL_burst_7] and [RL_source_selected_8, RL_burst_8] ) fired in the same clock\n cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if ((WILL_FIRE_RL_source_selected_7 || WILL_FIRE_RL_burst_7 || + WILL_FIRE_RL_source_selected_8 || + WILL_FIRE_RL_burst_8) && + (WILL_FIRE_RL_source_selected_9 || WILL_FIRE_RL_burst_9)) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_7,\n RL_burst_7, RL_source_selected_8, RL_burst_8] and [RL_source_selected_9,\n RL_burst_9] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_source_selected_9 && WILL_FIRE_RL_burst_9) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 114, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_source_selected_9] and\n [RL_burst_9] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_sink_selected_8 && WILL_FIRE_RL_sink_selected_9) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 155, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_sink_selected_8] and\n [RL_sink_selected_9] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_forwardRsp) + begin + v__h56310 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_forwardRsp) + $display("%0t: Forwarding 0x%x", + v__h56310, + MUX_msNoSynth_0_r_buffer_enqw$wset_1__VAL_1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) begin - v__h5074 = $stime; + v__h3443 = $stime; #0; end - v__h5068 = v__h5074 / 32'd10; + v__h3437 = v__h3443 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h5068); + $display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h3437); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) begin - v__h5275 = $stime; + v__h3620 = $stime; #0; end - v__h5269 = v__h5275 / 32'd10; + v__h3614 = v__h3620 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_dm_start) - $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h5269); + $display("%0d: Core.rl_cpu_hart0_reset_from_dm_start", v__h3614); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) begin - v__h5643 = $stime; + v__h3986 = $stime; #0; end - v__h5637 = v__h5643 / 32'd10; + v__h3980 = v__h3986 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete) - $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h5637); + $display("%0d: Core.rl_cpu_hart0_reset_complete", v__h3980); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_firstFlit && WILL_FIRE_RL_ifcs_2_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 284, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_firstFlit] and\n [RL_ifcs_2_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit && + WILL_FIRE_RL_ifcs_0_1_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit] and\n [RL_ifcs_0_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_followFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_followFlits] and\n [RL_ifcs_0_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_0_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_nonRoutableFlit] and\n [RL_ifcs_0_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_drainFlits && + WILL_FIRE_RL_ifcs_0_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_drainFlits] and\n [RL_ifcs_0_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_forwardRsp) + begin + v__h58726 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_forwardRsp) + $display("%0t: Forwarding 0x%x", + v__h58726, + MUX_msNoSynth_1_r_buffer_enqw$wset_1__VAL_1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_firstFlit && WILL_FIRE_RL_ifcs_1_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_firstFlit] and\n [RL_ifcs_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_followFlits && WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_followFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_followFlits] and\n [RL_ifcs_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_nonRoutableFlit] and\n [RL_ifcs_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_drainFlits && + WILL_FIRE_RL_ifcs_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_drainFlits] and\n [RL_ifcs_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && dm_mem_tap$master_wlast && + merged_1_flitLeft > 8'd1) + $display("Expecting more write data flits"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && dm_mem_tap$master_wlast && + merged_1_flitLeft > 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && !dm_mem_tap$master_wlast && + merged_1_flitLeft == 8'd1) + $display("Expecting last write data flit"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_merged_1_genOther && !dm_mem_tap$master_wlast && + merged_1_flitLeft == 8'd1) + $finish(32'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit && + WILL_FIRE_RL_ifcs_1_1_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit] and\n [RL_ifcs_1_1_followFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_followFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 41: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_followFlits] and\n [RL_ifcs_1_1_nonRoutableFlit] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_nonRoutableFlit && + WILL_FIRE_RL_ifcs_1_1_drainFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 216, column 54: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_nonRoutableFlit] and\n [RL_ifcs_1_1_drainFlits] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_drainFlits && + WILL_FIRE_RL_ifcs_1_1_nonRoutableGenRsp) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 217, column 73: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_drainFlits] and\n [RL_ifcs_1_1_nonRoutableGenRsp] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_0_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_0_1_followFlits_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 285, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_0_1_firstFlit_1] and\n [RL_ifcs_0_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_1_1_firstFlit_1 && + WILL_FIRE_RL_ifcs_1_1_followFlits_1) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 285, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_1_1_firstFlit_1] and\n [RL_ifcs_1_1_followFlits_1] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_ifcs_2_1_firstFlit && + WILL_FIRE_RL_ifcs_2_1_followFlits) + $display("Error: \"../libs/BlueStuff//Interconnect.bsv\", line 284, column 30: (R0001)\n Mutually exclusive rules (from the ME sets [RL_ifcs_2_1_firstFlit] and\n [RL_ifcs_2_1_followFlits] ) fired in the same clock cycle.\n"); end // synopsys translate_on endmodule // mkCore diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkDM_Abstract_Commands.v b/src_SSITH_P1/xilinx_ip/hdl/mkDM_Abstract_Commands.v index f23b0bbc..f66551a0 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkDM_Abstract_Commands.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:15 BST 2019 // // // Ports: @@ -242,26 +242,26 @@ module mkDM_Abstract_Commands(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h2054; - reg [31 : 0] v__h2293; - reg [31 : 0] v__h2418; - reg [31 : 0] v__h2745; - reg [31 : 0] v__h2862; - reg [31 : 0] v__h2575; - reg [31 : 0] v__h3277; - reg [31 : 0] v__h2048; - reg [31 : 0] v__h2287; - reg [31 : 0] v__h2412; - reg [31 : 0] v__h2569; - reg [31 : 0] v__h2739; - reg [31 : 0] v__h2856; - reg [31 : 0] v__h3271; + reg [31 : 0] v__h2078; + reg [31 : 0] v__h2317; + reg [31 : 0] v__h2442; + reg [31 : 0] v__h2769; + reg [31 : 0] v__h2886; + reg [31 : 0] v__h2599; + reg [31 : 0] v__h3301; + reg [31 : 0] v__h2072; + reg [31 : 0] v__h2311; + reg [31 : 0] v__h2436; + reg [31 : 0] v__h2593; + reg [31 : 0] v__h2763; + reg [31 : 0] v__h2880; + reg [31 : 0] v__h3295; // synopsys translate_on // remaining internal signals - wire [31 : 0] virt_rg_abstractcs__h500, virt_rg_command__h564; - wire [15 : 0] regno__h1869; - wire [12 : 0] x__h1051; + wire [31 : 0] virt_rg_abstractcs__h524, virt_rg_command__h588; + wire [15 : 0] regno__h1893; + wire [12 : 0] x__h1075; wire rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d35, rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d46, rg_abstractcs_cmderr_0_EQ_0_4_AND_write_dm_add_ETC___d105, @@ -282,11 +282,11 @@ module mkDM_Abstract_Commands(CLK, // actionvalue method av_read always@(av_read_dm_addr or - rg_data0 or virt_rg_abstractcs__h500 or virt_rg_command__h564) + rg_data0 or virt_rg_abstractcs__h524 or virt_rg_command__h588) begin case (av_read_dm_addr) - 7'h16: av_read = virt_rg_abstractcs__h500; - 7'h17: av_read = virt_rg_command__h564; + 7'h16: av_read = virt_rg_abstractcs__h524; + 7'h17: av_read = virt_rg_command__h588; default: av_read = rg_data0; endcase end @@ -330,7 +330,7 @@ module mkDM_Abstract_Commands(CLK, EN_hart0_csr_mem_client_response_put ; // submodule f_hart0_csr_reqs - FIFO1 #(.width(32'd45), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd45), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_csr_reqs$D_IN), .ENQ(f_hart0_csr_reqs$ENQ), @@ -341,7 +341,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_csr_reqs$EMPTY_N)); // submodule f_hart0_csr_rsps - FIFO1 #(.width(32'd33), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd33), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_csr_rsps$D_IN), .ENQ(f_hart0_csr_rsps$ENQ), @@ -352,7 +352,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_csr_rsps$EMPTY_N)); // submodule f_hart0_gpr_reqs - FIFO1 #(.width(32'd38), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N), + FIFO2 #(.width(32'd38), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_gpr_reqs$D_IN), .ENQ(f_hart0_gpr_reqs$ENQ), @@ -363,7 +363,7 @@ module mkDM_Abstract_Commands(CLK, .EMPTY_N(f_hart0_gpr_reqs$EMPTY_N)); // submodule f_hart0_gpr_rsps - FIFO1 #(.width(32'd33), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N), + FIFO2 #(.width(32'd33), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N), .CLK(CLK), .D_IN(f_hart0_gpr_rsps$D_IN), .ENQ(f_hart0_gpr_rsps$ENQ), @@ -470,9 +470,9 @@ module mkDM_Abstract_Commands(CLK, assign MUX_f_hart0_csr_reqs$enq_1__VAL_2 = { 1'd0, rg_command_access_reg_regno[11:0], 32'hAAAAAAAA } ; assign MUX_f_hart0_gpr_reqs$enq_1__VAL_1 = - { 1'd1, x__h1051[4:0], rg_data0 } ; + { 1'd1, x__h1075[4:0], rg_data0 } ; assign MUX_f_hart0_gpr_reqs$enq_1__VAL_2 = - { 1'd0, x__h1051[4:0], 32'hAAAAAAAA } ; + { 1'd0, x__h1075[4:0], 32'hAAAAAAAA } ; assign MUX_rg_abstractcs_cmderr$write_1__VAL_4 = f_hart0_gpr_rsps$D_OUT[32] ? 3'd0 : 3'd4 ; always@(write_dm_addr or rg_abstractcs_busy or write_dm_word) @@ -671,7 +671,7 @@ module mkDM_Abstract_Commands(CLK, assign f_hart0_gpr_rsps$CLR = EN_reset ; // remaining internal signals - assign regno__h1869 = { 3'd0, rg_command_access_reg_regno } ; + assign regno__h1893 = { 3'd0, rg_command_access_reg_regno } ; assign rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d35 = rg_abstractcs_busy && rg_start_reg_access && rg_command_access_reg_write && @@ -697,10 +697,10 @@ module mkDM_Abstract_Commands(CLK, rg_command_access_reg_regno <= 13'h0FFF ; assign rg_command_access_reg_regno_ULT_0x1000___d31 = rg_command_access_reg_regno < 13'h1000 ; - assign virt_rg_abstractcs__h500 = + assign virt_rg_abstractcs__h524 = { 19'd0, rg_abstractcs_busy, 1'b0, rg_abstractcs_cmderr, 8'd1 } ; - assign virt_rg_command__h564 = - { 15'd17, rg_command_access_reg_write, regno__h1869 } ; + assign virt_rg_command__h588 = + { 15'd17, rg_command_access_reg_write, regno__h1893 } ; assign write_dm_addr_EQ_0x16_7_AND_rg_abstractcs_busy_ETC___d79 = write_dm_addr == 7'h16 && (rg_abstractcs_busy || write_dm_word[10:8] != 3'd0) || @@ -733,7 +733,7 @@ module mkDM_Abstract_Commands(CLK, write_dm_word[22:20] != 3'd4 && write_dm_word[22:20] != 3'd5 && write_dm_word[22:20] != 3'd6 ; - assign x__h1051 = rg_command_access_reg_regno - 13'h1000 ; + assign x__h1075 = rg_command_access_reg_regno - 13'h1000 ; // handling of inlined registers @@ -786,14 +786,14 @@ module mkDM_Abstract_Commands(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) begin - v__h2054 = $stime; + v__h2078 = $stime; #0; end - v__h2048 = v__h2054 / 32'd10; + v__h2072 = v__h2078 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) $display("%0d: DM_Abstract_Commands.write: [abstractcs] <= 0x%08h: ERROR", - v__h2048, + v__h2072, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy) @@ -803,16 +803,16 @@ module mkDM_Abstract_Commands(CLK, write_dm_addr == 7'h17 && rg_abstractcs_busy) begin - v__h2293 = $stime; + v__h2317 = $stime; #0; end - v__h2287 = v__h2293 / 32'd10; + v__h2311 = v__h2317 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h17 && rg_abstractcs_busy) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h2287, + v__h2311, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -823,15 +823,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr_0_EQ_0_4_AND_write_dm_add_ETC___d105) begin - v__h2418 = $stime; + v__h2442 = $stime; #0; end - v__h2412 = v__h2418 / 32'd10; + v__h2436 = v__h2442 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr_0_EQ_0_4_AND_write_dm_add_ETC___d105) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h2412, + v__h2436, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && @@ -849,15 +849,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_1_AND_NOT_rg_abstractcs__ETC___d112) begin - v__h2745 = $stime; + v__h2769 = $stime; #0; end - v__h2739 = v__h2745 / 32'd10; + v__h2763 = v__h2769 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_1_AND_NOT_rg_abstractcs__ETC___d112) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h2739, + v__h2763, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -867,15 +867,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_1_AND_NOT_rg_abstractcs__ETC___d130) begin - v__h2862 = $stime; + v__h2886 = $stime; #0; end - v__h2856 = v__h2862 / 32'd10; + v__h2880 = v__h2886 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr_EQ_0x17_1_AND_NOT_rg_abstractcs__ETC___d130) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h2856, + v__h2880, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && @@ -885,15 +885,15 @@ module mkDM_Abstract_Commands(CLK, if (EN_write && rg_abstractcs_cmderr_0_EQ_0_4_AND_write_dm_add_ETC___d137) begin - v__h2575 = $stime; + v__h2599 = $stime; #0; end - v__h2569 = v__h2575 / 32'd10; + v__h2593 = v__h2599 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr_0_EQ_0_4_AND_write_dm_add_ETC___d137) $display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR", - v__h2569, + v__h2593, write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && @@ -955,16 +955,16 @@ module mkDM_Abstract_Commands(CLK, write_dm_addr != 7'h17 && write_dm_addr != 7'h04) begin - v__h3277 = $stime; + v__h3301 = $stime; #0; end - v__h3271 = v__h3277 / 32'd10; + v__h3295 = v__h3301 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr != 7'h16 && rg_abstractcs_cmderr == 3'd0 && write_dm_addr != 7'h17 && write_dm_addr != 7'h04) - $write("%0d: DM_Abstract_Commands.write: [", v__h3271); + $write("%0d: DM_Abstract_Commands.write: [", v__h3295); if (RST_N != `BSV_RESET_VALUE) if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h10) $write("dm_addr_dmcontrol"); diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkDM_CSR_Tap.v b/src_SSITH_P1/xilinx_ip/hdl/mkDM_CSR_Tap.v index 96cc6fbc..4cf6f74b 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkDM_CSR_Tap.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkDM_CSR_Tap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:32 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkDM_GPR_Tap.v b/src_SSITH_P1/xilinx_ip/hdl/mkDM_GPR_Tap.v index 42f4ad1d..311d9452 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkDM_GPR_Tap.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkDM_GPR_Tap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:32 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkDM_Mem_Tap.v b/src_SSITH_P1/xilinx_ip/hdl/mkDM_Mem_Tap.v index 86b1f78d..a1f6d43d 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkDM_Mem_Tap.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkDM_Mem_Tap.v @@ -1,96 +1,517 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:32 BST 2019 // // // Ports: // Name I/O size props -// slave_awready O 1 reg -// slave_wready O 1 reg -// slave_bvalid O 1 reg -// slave_bid O 4 reg -// slave_bresp O 2 reg -// slave_arready O 1 reg -// slave_rvalid O 1 reg -// slave_rid O 4 reg -// slave_rdata O 64 reg -// slave_rresp O 2 reg -// slave_rlast O 1 reg -// master_awvalid O 1 reg -// master_awid O 4 reg -// master_awaddr O 64 reg -// master_awlen O 8 reg -// master_awsize O 3 reg -// master_awburst O 2 reg -// master_awlock O 1 reg -// master_awcache O 4 reg -// master_awprot O 3 reg -// master_awqos O 4 reg -// master_awregion O 4 reg -// master_wvalid O 1 reg -// master_wdata O 64 reg -// master_wstrb O 8 reg -// master_wlast O 1 reg -// master_bready O 1 reg -// master_arvalid O 1 reg -// master_arid O 4 reg -// master_araddr O 64 reg -// master_arlen O 8 reg -// master_arsize O 3 reg -// master_arburst O 2 reg -// master_arlock O 1 reg -// master_arcache O 4 reg -// master_arprot O 3 reg -// master_arqos O 4 reg -// master_arregion O 4 reg -// master_rready O 1 reg +// slave_awready O 1 +// slave_wready O 1 +// slave_bid O 4 +// slave_bresp O 2 +// slave_bvalid O 1 +// slave_arready O 1 +// slave_rid O 4 +// slave_rdata O 64 +// slave_rresp O 2 +// slave_rlast O 1 +// slave_rvalid O 1 +// master_awid O 4 +// master_awaddr O 64 +// master_awlen O 8 +// master_awsize O 3 +// master_awburst O 2 +// master_awlock O 1 +// master_awcache O 4 +// master_awprot O 3 +// master_awqos O 4 +// master_awregion O 4 +// master_awvalid O 1 +// master_wdata O 64 +// master_wstrb O 8 +// master_wlast O 1 +// master_wvalid O 1 +// master_bready O 1 +// master_arid O 4 +// master_araddr O 64 +// master_arlen O 8 +// master_arsize O 3 +// master_arburst O 2 +// master_arlock O 1 +// master_arcache O 4 +// master_arprot O 3 +// master_arqos O 4 +// master_arregion O 4 +// master_arvalid O 1 +// master_rready O 1 // trace_data_out_get O 234 reg // RDY_trace_data_out_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// slave_awvalid I 1 -// slave_awid I 4 reg -// slave_awaddr I 64 reg -// slave_awlen I 8 reg -// slave_awsize I 3 reg -// slave_awburst I 2 reg -// slave_awlock I 1 reg -// slave_awcache I 4 reg -// slave_awprot I 3 reg -// slave_awqos I 4 reg -// slave_awregion I 4 reg -// slave_wvalid I 1 -// slave_wdata I 64 reg -// slave_wstrb I 8 reg -// slave_wlast I 1 reg +// slave_awid I 4 +// slave_awaddr I 64 +// slave_awlen I 8 +// slave_awsize I 3 +// slave_awburst I 2 +// slave_awlock I 1 +// slave_awcache I 4 +// slave_awprot I 3 +// slave_awqos I 4 +// slave_awregion I 4 +// slave_wdata I 64 +// slave_wstrb I 8 +// slave_wlast I 1 // slave_bready I 1 -// slave_arvalid I 1 -// slave_arid I 4 reg -// slave_araddr I 64 reg -// slave_arlen I 8 reg -// slave_arsize I 3 reg -// slave_arburst I 2 reg -// slave_arlock I 1 reg -// slave_arcache I 4 reg -// slave_arprot I 3 reg -// slave_arqos I 4 reg -// slave_arregion I 4 reg +// slave_arid I 4 +// slave_araddr I 64 +// slave_arlen I 8 +// slave_arsize I 3 +// slave_arburst I 2 +// slave_arlock I 1 +// slave_arcache I 4 +// slave_arprot I 3 +// slave_arqos I 4 +// slave_arregion I 4 // slave_rready I 1 // master_awready I 1 // master_wready I 1 -// master_bvalid I 1 -// master_bid I 4 reg -// master_bresp I 2 reg +// master_bid I 4 +// master_bresp I 2 // master_arready I 1 +// master_rid I 4 +// master_rdata I 64 +// master_rresp I 2 +// master_rlast I 1 +// slave_awvalid I 1 +// slave_wvalid I 1 +// slave_arvalid I 1 +// master_bvalid I 1 // master_rvalid I 1 -// master_rid I 4 reg -// master_rdata I 64 reg -// master_rresp I 2 reg -// master_rlast I 1 reg // EN_trace_data_out_get I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awid +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awaddr +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awlen +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awsize +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awburst +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awlock +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awcache +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awprot +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awqos +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awregion +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awuser +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_awvalid +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_wdata +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_wstrb +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_wlast +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_wuser +// (slave_awid, +// slave_awaddr, +// slave_awlen, +// slave_awsize, +// slave_awburst, +// slave_awlock, +// slave_awcache, +// slave_awprot, +// slave_awqos, +// slave_awregion, +// slave_wdata, +// slave_wstrb, +// slave_wlast, +// slave_awvalid, +// slave_wvalid) -> master_wvalid +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arid +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_araddr +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arlen +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arsize +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arburst +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arlock +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arcache +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arprot +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arqos +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arregion +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_aruser +// (slave_arid, +// slave_araddr, +// slave_arlen, +// slave_arsize, +// slave_arburst, +// slave_arlock, +// slave_arcache, +// slave_arprot, +// slave_arqos, +// slave_arregion, +// slave_arvalid) -> master_arvalid +// (master_bid, master_bresp, master_bvalid) -> slave_bid +// (master_bid, master_bresp, master_bvalid) -> slave_bresp +// (master_bid, master_bresp, master_bvalid) -> slave_buser +// (master_bid, master_bresp, master_bvalid) -> slave_bvalid +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_rid +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_rdata +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_rresp +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_rlast +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_ruser +// (master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// master_rvalid) -> slave_rvalid // // @@ -110,7 +531,6 @@ module mkDM_Mem_Tap(CLK, RST_N, - slave_awvalid, slave_awid, slave_awaddr, slave_awlen, @@ -121,25 +541,25 @@ module mkDM_Mem_Tap(CLK, slave_awprot, slave_awqos, slave_awregion, + slave_awvalid, slave_awready, - slave_wvalid, slave_wdata, slave_wstrb, slave_wlast, + slave_wvalid, slave_wready, - slave_bvalid, - slave_bid, slave_bresp, + slave_bvalid, + slave_bready, - slave_arvalid, slave_arid, slave_araddr, slave_arlen, @@ -150,11 +570,10 @@ module mkDM_Mem_Tap(CLK, slave_arprot, slave_arqos, slave_arregion, + slave_arvalid, slave_arready, - slave_rvalid, - slave_rid, slave_rdata, @@ -163,9 +582,9 @@ module mkDM_Mem_Tap(CLK, slave_rlast, - slave_rready, + slave_rvalid, - master_awvalid, + slave_rready, master_awid, @@ -187,9 +606,9 @@ module mkDM_Mem_Tap(CLK, master_awregion, - master_awready, + master_awvalid, - master_wvalid, + master_awready, master_wdata, @@ -197,16 +616,16 @@ module mkDM_Mem_Tap(CLK, master_wlast, + master_wvalid, + master_wready, - master_bvalid, master_bid, master_bresp, + master_bvalid, master_bready, - master_arvalid, - master_arid, master_araddr, @@ -227,13 +646,15 @@ module mkDM_Mem_Tap(CLK, master_arregion, + master_arvalid, + master_arready, - master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, + master_rvalid, master_rready, @@ -243,8 +664,7 @@ module mkDM_Mem_Tap(CLK, input CLK; input RST_N; - // action method slave_m_awvalid - input slave_awvalid; + // action method slave_aw_awflit input [3 : 0] slave_awid; input [63 : 0] slave_awaddr; input [7 : 0] slave_awlen; @@ -255,35 +675,35 @@ module mkDM_Mem_Tap(CLK, input [2 : 0] slave_awprot; input [3 : 0] slave_awqos; input [3 : 0] slave_awregion; + input slave_awvalid; - // value method slave_m_awready + // value method slave_aw_awready output slave_awready; - // action method slave_m_wvalid - input slave_wvalid; + // action method slave_w_wflit input [63 : 0] slave_wdata; input [7 : 0] slave_wstrb; input slave_wlast; + input slave_wvalid; - // value method slave_m_wready + // value method slave_w_wready output slave_wready; - // value method slave_m_bvalid - output slave_bvalid; - - // value method slave_m_bid + // value method slave_b_bid output [3 : 0] slave_bid; - // value method slave_m_bresp + // value method slave_b_bresp output [1 : 0] slave_bresp; - // value method slave_m_buser + // value method slave_b_buser + + // value method slave_b_bvalid + output slave_bvalid; - // action method slave_m_bready + // action method slave_b_bready input slave_bready; - // action method slave_m_arvalid - input slave_arvalid; + // action method slave_ar_arflit input [3 : 0] slave_arid; input [63 : 0] slave_araddr; input [7 : 0] slave_arlen; @@ -294,139 +714,140 @@ module mkDM_Mem_Tap(CLK, input [2 : 0] slave_arprot; input [3 : 0] slave_arqos; input [3 : 0] slave_arregion; + input slave_arvalid; - // value method slave_m_arready + // value method slave_ar_arready output slave_arready; - // value method slave_m_rvalid - output slave_rvalid; - - // value method slave_m_rid + // value method slave_r_rid output [3 : 0] slave_rid; - // value method slave_m_rdata + // value method slave_r_rdata output [63 : 0] slave_rdata; - // value method slave_m_rresp + // value method slave_r_rresp output [1 : 0] slave_rresp; - // value method slave_m_rlast + // value method slave_r_rlast output slave_rlast; - // value method slave_m_ruser + // value method slave_r_ruser - // action method slave_m_rready - input slave_rready; + // value method slave_r_rvalid + output slave_rvalid; - // value method master_m_awvalid - output master_awvalid; + // action method slave_r_rready + input slave_rready; - // value method master_m_awid + // value method master_aw_awid output [3 : 0] master_awid; - // value method master_m_awaddr + // value method master_aw_awaddr output [63 : 0] master_awaddr; - // value method master_m_awlen + // value method master_aw_awlen output [7 : 0] master_awlen; - // value method master_m_awsize + // value method master_aw_awsize output [2 : 0] master_awsize; - // value method master_m_awburst + // value method master_aw_awburst output [1 : 0] master_awburst; - // value method master_m_awlock + // value method master_aw_awlock output master_awlock; - // value method master_m_awcache + // value method master_aw_awcache output [3 : 0] master_awcache; - // value method master_m_awprot + // value method master_aw_awprot output [2 : 0] master_awprot; - // value method master_m_awqos + // value method master_aw_awqos output [3 : 0] master_awqos; - // value method master_m_awregion + // value method master_aw_awregion output [3 : 0] master_awregion; - // value method master_m_awuser + // value method master_aw_awuser - // action method master_m_awready - input master_awready; + // value method master_aw_awvalid + output master_awvalid; - // value method master_m_wvalid - output master_wvalid; + // action method master_aw_awready + input master_awready; - // value method master_m_wdata + // value method master_w_wdata output [63 : 0] master_wdata; - // value method master_m_wstrb + // value method master_w_wstrb output [7 : 0] master_wstrb; - // value method master_m_wlast + // value method master_w_wlast output master_wlast; - // value method master_m_wuser + // value method master_w_wuser + + // value method master_w_wvalid + output master_wvalid; - // action method master_m_wready + // action method master_w_wready input master_wready; - // action method master_m_bvalid - input master_bvalid; + // action method master_b_bflit input [3 : 0] master_bid; input [1 : 0] master_bresp; + input master_bvalid; - // value method master_m_bready + // value method master_b_bready output master_bready; - // value method master_m_arvalid - output master_arvalid; - - // value method master_m_arid + // value method master_ar_arid output [3 : 0] master_arid; - // value method master_m_araddr + // value method master_ar_araddr output [63 : 0] master_araddr; - // value method master_m_arlen + // value method master_ar_arlen output [7 : 0] master_arlen; - // value method master_m_arsize + // value method master_ar_arsize output [2 : 0] master_arsize; - // value method master_m_arburst + // value method master_ar_arburst output [1 : 0] master_arburst; - // value method master_m_arlock + // value method master_ar_arlock output master_arlock; - // value method master_m_arcache + // value method master_ar_arcache output [3 : 0] master_arcache; - // value method master_m_arprot + // value method master_ar_arprot output [2 : 0] master_arprot; - // value method master_m_arqos + // value method master_ar_arqos output [3 : 0] master_arqos; - // value method master_m_arregion + // value method master_ar_arregion output [3 : 0] master_arregion; - // value method master_m_aruser + // value method master_ar_aruser + + // value method master_ar_arvalid + output master_arvalid; - // action method master_m_arready + // action method master_ar_arready input master_arready; - // action method master_m_rvalid - input master_rvalid; + // action method master_r_rflit input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; + input master_rvalid; - // value method master_m_rready + // value method master_r_rready output master_rready; // actionvalue method trace_data_out_get @@ -466,6 +887,128 @@ module mkDM_Mem_Tap(CLK, slave_rvalid, slave_wready; + // inlined wires + wire [97 : 0] master_xactor_shim_arff_rv$port0__write_1, + master_xactor_shim_arff_rv$port1__read, + master_xactor_shim_arff_rv$port2__read, + master_xactor_shim_arff_rv$port3__read, + master_xactor_shim_awff_rv$port0__write_1, + master_xactor_shim_awff_rv$port1__read, + master_xactor_shim_awff_rv$port2__read, + master_xactor_shim_awff_rv$port3__read, + slave_xactor_shim_arff_rv$port0__write_1, + slave_xactor_shim_arff_rv$port1__read, + slave_xactor_shim_arff_rv$port2__read, + slave_xactor_shim_arff_rv$port3__read, + slave_xactor_shim_awff_rv$port0__write_1, + slave_xactor_shim_awff_rv$port1__read, + slave_xactor_shim_awff_rv$port2__read, + slave_xactor_shim_awff_rv$port3__read; + wire [96 : 0] slave_xactor_ug_slave_u_ar_putWire$wget, + slave_xactor_ug_slave_u_aw_putWire$wget; + wire [73 : 0] master_xactor_shim_wff_rv$port0__write_1, + master_xactor_shim_wff_rv$port1__read, + master_xactor_shim_wff_rv$port2__read, + master_xactor_shim_wff_rv$port3__read, + slave_xactor_shim_wff_rv$port0__write_1, + slave_xactor_shim_wff_rv$port1__read, + slave_xactor_shim_wff_rv$port2__read, + slave_xactor_shim_wff_rv$port3__read; + wire [72 : 0] slave_xactor_ug_slave_u_w_putWire$wget; + wire [71 : 0] master_xactor_shim_rff_rv$port0__write_1, + master_xactor_shim_rff_rv$port1__read, + master_xactor_shim_rff_rv$port2__read, + master_xactor_shim_rff_rv$port3__read, + slave_xactor_shim_rff_rv$port0__write_1, + slave_xactor_shim_rff_rv$port1__read, + slave_xactor_shim_rff_rv$port2__read, + slave_xactor_shim_rff_rv$port3__read; + wire [70 : 0] master_xactor_ug_master_u_r_putWire$wget, + slave_xactor_ug_slave_u_r_peekWire$wget; + wire [6 : 0] master_xactor_shim_bff_rv$port0__write_1, + master_xactor_shim_bff_rv$port1__read, + master_xactor_shim_bff_rv$port2__read, + master_xactor_shim_bff_rv$port3__read, + slave_xactor_shim_bff_rv$port0__write_1, + slave_xactor_shim_bff_rv$port1__read, + slave_xactor_shim_bff_rv$port2__read, + slave_xactor_shim_bff_rv$port3__read; + wire [5 : 0] master_xactor_ug_master_u_b_putWire$wget, + slave_xactor_ug_slave_u_b_peekWire$wget; + wire master_xactor_ug_master_u_ar_dropWire$whas, + master_xactor_ug_master_u_aw_dropWire$whas, + master_xactor_ug_master_u_b_putWire$whas, + master_xactor_ug_master_u_r_putWire$whas, + master_xactor_ug_master_u_w_dropWire$whas, + slave_xactor_shim_arff_rv$EN_port1__write, + slave_xactor_shim_awff_rv$EN_port1__write, + slave_xactor_shim_bff_rv$EN_port0__write, + slave_xactor_shim_rff_rv$EN_port0__write, + slave_xactor_shim_wff_rv$EN_port1__write, + slave_xactor_ug_slave_u_ar_putWire$whas, + slave_xactor_ug_slave_u_aw_putWire$whas, + slave_xactor_ug_slave_u_b_dropWire$whas, + slave_xactor_ug_slave_u_r_dropWire$whas, + slave_xactor_ug_slave_u_w_putWire$whas; + + // register master_xactor_clearing + reg master_xactor_clearing; + wire master_xactor_clearing$D_IN, master_xactor_clearing$EN; + + // register master_xactor_shim_arff_rv + reg [97 : 0] master_xactor_shim_arff_rv; + wire [97 : 0] master_xactor_shim_arff_rv$D_IN; + wire master_xactor_shim_arff_rv$EN; + + // register master_xactor_shim_awff_rv + reg [97 : 0] master_xactor_shim_awff_rv; + wire [97 : 0] master_xactor_shim_awff_rv$D_IN; + wire master_xactor_shim_awff_rv$EN; + + // register master_xactor_shim_bff_rv + reg [6 : 0] master_xactor_shim_bff_rv; + wire [6 : 0] master_xactor_shim_bff_rv$D_IN; + wire master_xactor_shim_bff_rv$EN; + + // register master_xactor_shim_rff_rv + reg [71 : 0] master_xactor_shim_rff_rv; + wire [71 : 0] master_xactor_shim_rff_rv$D_IN; + wire master_xactor_shim_rff_rv$EN; + + // register master_xactor_shim_wff_rv + reg [73 : 0] master_xactor_shim_wff_rv; + wire [73 : 0] master_xactor_shim_wff_rv$D_IN; + wire master_xactor_shim_wff_rv$EN; + + // register slave_xactor_clearing + reg slave_xactor_clearing; + wire slave_xactor_clearing$D_IN, slave_xactor_clearing$EN; + + // register slave_xactor_shim_arff_rv + reg [97 : 0] slave_xactor_shim_arff_rv; + wire [97 : 0] slave_xactor_shim_arff_rv$D_IN; + wire slave_xactor_shim_arff_rv$EN; + + // register slave_xactor_shim_awff_rv + reg [97 : 0] slave_xactor_shim_awff_rv; + wire [97 : 0] slave_xactor_shim_awff_rv$D_IN; + wire slave_xactor_shim_awff_rv$EN; + + // register slave_xactor_shim_bff_rv + reg [6 : 0] slave_xactor_shim_bff_rv; + wire [6 : 0] slave_xactor_shim_bff_rv$D_IN; + wire slave_xactor_shim_bff_rv$EN; + + // register slave_xactor_shim_rff_rv + reg [71 : 0] slave_xactor_shim_rff_rv; + wire [71 : 0] slave_xactor_shim_rff_rv$D_IN; + wire slave_xactor_shim_rff_rv$EN; + + // register slave_xactor_shim_wff_rv + reg [73 : 0] slave_xactor_shim_wff_rv; + wire [73 : 0] slave_xactor_shim_wff_rv$D_IN; + wire slave_xactor_shim_wff_rv$EN; + // ports of submodule f_trace_data wire [233 : 0] f_trace_data$D_IN, f_trace_data$D_OUT; wire f_trace_data$CLR, @@ -474,278 +1017,278 @@ module mkDM_Mem_Tap(CLK, f_trace_data$ENQ, f_trace_data$FULL_N; - // ports of submodule master_xactor_f_rd_addr - wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT; - wire master_xactor_f_rd_addr$CLR, - master_xactor_f_rd_addr$DEQ, - master_xactor_f_rd_addr$EMPTY_N, - master_xactor_f_rd_addr$ENQ, - master_xactor_f_rd_addr$FULL_N; - - // ports of submodule master_xactor_f_rd_data - wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT; - wire master_xactor_f_rd_data$CLR, - master_xactor_f_rd_data$DEQ, - master_xactor_f_rd_data$EMPTY_N, - master_xactor_f_rd_data$ENQ, - master_xactor_f_rd_data$FULL_N; - - // ports of submodule master_xactor_f_wr_addr - wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT; - wire master_xactor_f_wr_addr$CLR, - master_xactor_f_wr_addr$DEQ, - master_xactor_f_wr_addr$EMPTY_N, - master_xactor_f_wr_addr$ENQ, - master_xactor_f_wr_addr$FULL_N; - - // ports of submodule master_xactor_f_wr_data - wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT; - wire master_xactor_f_wr_data$CLR, - master_xactor_f_wr_data$DEQ, - master_xactor_f_wr_data$EMPTY_N, - master_xactor_f_wr_data$ENQ, - master_xactor_f_wr_data$FULL_N; - - // ports of submodule master_xactor_f_wr_resp - wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT; - wire master_xactor_f_wr_resp$CLR, - master_xactor_f_wr_resp$DEQ, - master_xactor_f_wr_resp$EMPTY_N, - master_xactor_f_wr_resp$ENQ, - master_xactor_f_wr_resp$FULL_N; - - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - // rule scheduling signals - wire CAN_FIRE_RL_rl_connect, - CAN_FIRE_RL_rl_connect_1, - CAN_FIRE_RL_rl_connect_2, + wire CAN_FIRE_RL_master_xactor_do_clear, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut, + CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut, + CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_mkConnectionGetPut, + CAN_FIRE_RL_mkConnectionGetPut_1, + CAN_FIRE_RL_mkConnectionGetPut_2, + CAN_FIRE_RL_slave_xactor_do_clear, + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut, CAN_FIRE_RL_write_reqs, - CAN_FIRE_master_m_arready, - CAN_FIRE_master_m_awready, - CAN_FIRE_master_m_bvalid, - CAN_FIRE_master_m_rvalid, - CAN_FIRE_master_m_wready, - CAN_FIRE_slave_m_arvalid, - CAN_FIRE_slave_m_awvalid, - CAN_FIRE_slave_m_bready, - CAN_FIRE_slave_m_rready, - CAN_FIRE_slave_m_wvalid, + CAN_FIRE_master_ar_arready, + CAN_FIRE_master_aw_awready, + CAN_FIRE_master_b_bflit, + CAN_FIRE_master_r_rflit, + CAN_FIRE_master_w_wready, + CAN_FIRE_slave_ar_arflit, + CAN_FIRE_slave_aw_awflit, + CAN_FIRE_slave_b_bready, + CAN_FIRE_slave_r_rready, + CAN_FIRE_slave_w_wflit, CAN_FIRE_trace_data_out_get, - WILL_FIRE_RL_rl_connect, - WILL_FIRE_RL_rl_connect_1, - WILL_FIRE_RL_rl_connect_2, + WILL_FIRE_RL_master_xactor_do_clear, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut, + WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut, + WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_mkConnectionGetPut, + WILL_FIRE_RL_mkConnectionGetPut_1, + WILL_FIRE_RL_mkConnectionGetPut_2, + WILL_FIRE_RL_slave_xactor_do_clear, + WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_w_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut, WILL_FIRE_RL_write_reqs, - WILL_FIRE_master_m_arready, - WILL_FIRE_master_m_awready, - WILL_FIRE_master_m_bvalid, - WILL_FIRE_master_m_rvalid, - WILL_FIRE_master_m_wready, - WILL_FIRE_slave_m_arvalid, - WILL_FIRE_slave_m_awvalid, - WILL_FIRE_slave_m_bready, - WILL_FIRE_slave_m_rready, - WILL_FIRE_slave_m_wvalid, + WILL_FIRE_master_ar_arready, + WILL_FIRE_master_aw_awready, + WILL_FIRE_master_b_bflit, + WILL_FIRE_master_r_rflit, + WILL_FIRE_master_w_wready, + WILL_FIRE_slave_ar_arflit, + WILL_FIRE_slave_aw_awflit, + WILL_FIRE_slave_b_bready, + WILL_FIRE_slave_r_rready, + WILL_FIRE_slave_w_wflit, WILL_FIRE_trace_data_out_get; // remaining internal signals - wire [63 : 0] stval___1__h1520, x__h1518, y_avValue_fst__h1430; - wire slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8; + wire [96 : 0] master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3, + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1; + wire [72 : 0] master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q2; + wire [63 : 0] stval___1__h6721, x__h6719, y_avValue_fst__h6631; + wire slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97; - // action method slave_m_awvalid - assign CAN_FIRE_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_slave_m_awvalid = 1'd1 ; + // action method slave_aw_awflit + assign CAN_FIRE_slave_aw_awflit = 1'd1 ; + assign WILL_FIRE_slave_aw_awflit = slave_awvalid ; - // value method slave_m_awready - assign slave_awready = slave_xactor_f_wr_addr$FULL_N ; + // value method slave_aw_awready + assign slave_awready = !slave_xactor_shim_awff_rv[97] ; - // action method slave_m_wvalid - assign CAN_FIRE_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_slave_m_wvalid = 1'd1 ; + // action method slave_w_wflit + assign CAN_FIRE_slave_w_wflit = 1'd1 ; + assign WILL_FIRE_slave_w_wflit = slave_wvalid ; - // value method slave_m_wready - assign slave_wready = slave_xactor_f_wr_data$FULL_N ; + // value method slave_w_wready + assign slave_wready = !slave_xactor_shim_wff_rv[73] ; - // value method slave_m_bvalid - assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; + // value method slave_b_bid + assign slave_bid = slave_xactor_ug_slave_u_b_peekWire$wget[5:2] ; - // value method slave_m_bid - assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; + // value method slave_b_bresp + assign slave_bresp = slave_xactor_ug_slave_u_b_peekWire$wget[1:0] ; - // value method slave_m_bresp - assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; + // value method slave_b_bvalid + assign slave_bvalid = CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek ; - // action method slave_m_bready - assign CAN_FIRE_slave_m_bready = 1'd1 ; - assign WILL_FIRE_slave_m_bready = 1'd1 ; + // action method slave_b_bready + assign CAN_FIRE_slave_b_bready = 1'd1 ; + assign WILL_FIRE_slave_b_bready = 1'd1 ; - // action method slave_m_arvalid - assign CAN_FIRE_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_slave_m_arvalid = 1'd1 ; + // action method slave_ar_arflit + assign CAN_FIRE_slave_ar_arflit = 1'd1 ; + assign WILL_FIRE_slave_ar_arflit = slave_arvalid ; - // value method slave_m_arready - assign slave_arready = slave_xactor_f_rd_addr$FULL_N ; + // value method slave_ar_arready + assign slave_arready = !slave_xactor_shim_arff_rv[97] ; - // value method slave_m_rvalid - assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; + // value method slave_r_rid + assign slave_rid = slave_xactor_ug_slave_u_r_peekWire$wget[70:67] ; - // value method slave_m_rid - assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; + // value method slave_r_rdata + assign slave_rdata = slave_xactor_ug_slave_u_r_peekWire$wget[66:3] ; - // value method slave_m_rdata - assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; + // value method slave_r_rresp + assign slave_rresp = slave_xactor_ug_slave_u_r_peekWire$wget[2:1] ; - // value method slave_m_rresp - assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; + // value method slave_r_rlast + assign slave_rlast = slave_xactor_ug_slave_u_r_peekWire$wget[0] ; - // value method slave_m_rlast - assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; + // value method slave_r_rvalid + assign slave_rvalid = CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek ; - // action method slave_m_rready - assign CAN_FIRE_slave_m_rready = 1'd1 ; - assign WILL_FIRE_slave_m_rready = 1'd1 ; + // action method slave_r_rready + assign CAN_FIRE_slave_r_rready = 1'd1 ; + assign WILL_FIRE_slave_r_rready = 1'd1 ; - // value method master_m_awvalid - assign master_awvalid = master_xactor_f_wr_addr$EMPTY_N ; + // value method master_aw_awid + assign master_awid = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[96:93] ; - // value method master_m_awid - assign master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ; + // value method master_aw_awaddr + assign master_awaddr = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[92:29] ; - // value method master_m_awaddr - assign master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ; + // value method master_aw_awlen + assign master_awlen = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[28:21] ; - // value method master_m_awlen - assign master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ; + // value method master_aw_awsize + assign master_awsize = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[20:18] ; - // value method master_m_awsize - assign master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ; + // value method master_aw_awburst + assign master_awburst = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[17:16] ; - // value method master_m_awburst - assign master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ; + // value method master_aw_awlock + assign master_awlock = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[15] ; - // value method master_m_awlock - assign master_awlock = master_xactor_f_wr_addr$D_OUT[15] ; + // value method master_aw_awcache + assign master_awcache = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[14:11] ; - // value method master_m_awcache - assign master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ; + // value method master_aw_awprot + assign master_awprot = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[10:8] ; - // value method master_m_awprot - assign master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ; + // value method master_aw_awqos + assign master_awqos = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[7:4] ; - // value method master_m_awqos - assign master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ; + // value method master_aw_awregion + assign master_awregion = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1[3:0] ; - // value method master_m_awregion - assign master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ; + // value method master_aw_awvalid + assign master_awvalid = CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; - // action method master_m_awready - assign CAN_FIRE_master_m_awready = 1'd1 ; - assign WILL_FIRE_master_m_awready = 1'd1 ; + // action method master_aw_awready + assign CAN_FIRE_master_aw_awready = 1'd1 ; + assign WILL_FIRE_master_aw_awready = 1'd1 ; - // value method master_m_wvalid - assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ; + // value method master_w_wdata + assign master_wdata = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q2[72:9] ; - // value method master_m_wdata - assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ; + // value method master_w_wstrb + assign master_wstrb = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q2[8:1] ; - // value method master_m_wstrb - assign master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ; + // value method master_w_wlast + assign master_wlast = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q2[0] ; - // value method master_m_wlast - assign master_wlast = master_xactor_f_wr_data$D_OUT[0] ; + // value method master_w_wvalid + assign master_wvalid = CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; - // action method master_m_wready - assign CAN_FIRE_master_m_wready = 1'd1 ; - assign WILL_FIRE_master_m_wready = 1'd1 ; + // action method master_w_wready + assign CAN_FIRE_master_w_wready = 1'd1 ; + assign WILL_FIRE_master_w_wready = 1'd1 ; - // action method master_m_bvalid - assign CAN_FIRE_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_master_m_bvalid = 1'd1 ; + // action method master_b_bflit + assign CAN_FIRE_master_b_bflit = 1'd1 ; + assign WILL_FIRE_master_b_bflit = master_bvalid ; - // value method master_m_bready - assign master_bready = master_xactor_f_wr_resp$FULL_N ; + // value method master_b_bready + assign master_bready = !master_xactor_shim_bff_rv[6] ; - // value method master_m_arvalid - assign master_arvalid = master_xactor_f_rd_addr$EMPTY_N ; + // value method master_ar_arid + assign master_arid = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[96:93] ; - // value method master_m_arid - assign master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ; + // value method master_ar_araddr + assign master_araddr = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[92:29] ; - // value method master_m_araddr - assign master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ; + // value method master_ar_arlen + assign master_arlen = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[28:21] ; - // value method master_m_arlen - assign master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ; + // value method master_ar_arsize + assign master_arsize = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[20:18] ; - // value method master_m_arsize - assign master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ; + // value method master_ar_arburst + assign master_arburst = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[17:16] ; - // value method master_m_arburst - assign master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ; + // value method master_ar_arlock + assign master_arlock = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[15] ; - // value method master_m_arlock - assign master_arlock = master_xactor_f_rd_addr$D_OUT[15] ; + // value method master_ar_arcache + assign master_arcache = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[14:11] ; - // value method master_m_arcache - assign master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ; + // value method master_ar_arprot + assign master_arprot = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[10:8] ; - // value method master_m_arprot - assign master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ; + // value method master_ar_arqos + assign master_arqos = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[7:4] ; - // value method master_m_arqos - assign master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ; + // value method master_ar_arregion + assign master_arregion = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3[3:0] ; - // value method master_m_arregion - assign master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ; + // value method master_ar_arvalid + assign master_arvalid = CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; - // action method master_m_arready - assign CAN_FIRE_master_m_arready = 1'd1 ; - assign WILL_FIRE_master_m_arready = 1'd1 ; + // action method master_ar_arready + assign CAN_FIRE_master_ar_arready = 1'd1 ; + assign WILL_FIRE_master_ar_arready = 1'd1 ; - // action method master_m_rvalid - assign CAN_FIRE_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_master_m_rvalid = 1'd1 ; + // action method master_r_rflit + assign CAN_FIRE_master_r_rflit = 1'd1 ; + assign WILL_FIRE_master_r_rflit = master_rvalid ; - // value method master_m_rready - assign master_rready = master_xactor_f_rd_data$FULL_N ; + // value method master_r_rready + assign master_rready = !master_xactor_shim_rff_rv[71] ; // actionvalue method trace_data_out_get assign trace_data_out_get = f_trace_data$D_OUT ; @@ -764,222 +1307,216 @@ module mkDM_Mem_Tap(CLK, .FULL_N(f_trace_data$FULL_N), .EMPTY_N(f_trace_data$EMPTY_N)); - // submodule master_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(master_xactor_f_rd_addr$D_IN), - .ENQ(master_xactor_f_rd_addr$ENQ), - .DEQ(master_xactor_f_rd_addr$DEQ), - .CLR(master_xactor_f_rd_addr$CLR), - .D_OUT(master_xactor_f_rd_addr$D_OUT), - .FULL_N(master_xactor_f_rd_addr$FULL_N), - .EMPTY_N(master_xactor_f_rd_addr$EMPTY_N)); - - // submodule master_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(master_xactor_f_rd_data$D_IN), - .ENQ(master_xactor_f_rd_data$ENQ), - .DEQ(master_xactor_f_rd_data$DEQ), - .CLR(master_xactor_f_rd_data$CLR), - .D_OUT(master_xactor_f_rd_data$D_OUT), - .FULL_N(master_xactor_f_rd_data$FULL_N), - .EMPTY_N(master_xactor_f_rd_data$EMPTY_N)); - - // submodule master_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(master_xactor_f_wr_addr$D_IN), - .ENQ(master_xactor_f_wr_addr$ENQ), - .DEQ(master_xactor_f_wr_addr$DEQ), - .CLR(master_xactor_f_wr_addr$CLR), - .D_OUT(master_xactor_f_wr_addr$D_OUT), - .FULL_N(master_xactor_f_wr_addr$FULL_N), - .EMPTY_N(master_xactor_f_wr_addr$EMPTY_N)); - - // submodule master_xactor_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(master_xactor_f_wr_data$D_IN), - .ENQ(master_xactor_f_wr_data$ENQ), - .DEQ(master_xactor_f_wr_data$DEQ), - .CLR(master_xactor_f_wr_data$CLR), - .D_OUT(master_xactor_f_wr_data$D_OUT), - .FULL_N(master_xactor_f_wr_data$FULL_N), - .EMPTY_N(master_xactor_f_wr_data$EMPTY_N)); - - // submodule master_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(master_xactor_f_wr_resp$D_IN), - .ENQ(master_xactor_f_wr_resp$ENQ), - .DEQ(master_xactor_f_wr_resp$DEQ), - .CLR(master_xactor_f_wr_resp$CLR), - .D_OUT(master_xactor_f_wr_resp$D_OUT), - .FULL_N(master_xactor_f_wr_resp$FULL_N), - .EMPTY_N(master_xactor_f_wr_resp$EMPTY_N)); - - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); + // rule RL_slave_xactor_ug_slave_u_aw_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut = + slave_xactor_ug_slave_u_aw_putWire$whas && + slave_xactor_shim_awff_rv[97] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_aw_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut = + !slave_xactor_shim_awff_rv[97] && + slave_xactor_ug_slave_u_aw_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut ; + + // rule RL_slave_xactor_ug_slave_u_w_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut = + slave_xactor_ug_slave_u_w_putWire$whas && + slave_xactor_shim_wff_rv[73] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_w_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut = + !slave_xactor_shim_wff_rv[73] && + slave_xactor_ug_slave_u_w_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_w_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut ; // rule RL_write_reqs assign CAN_FIRE_RL_write_reqs = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8 ; + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_awff_rv$port1__read[97] && + slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97 ; assign WILL_FIRE_RL_write_reqs = CAN_FIRE_RL_write_reqs ; - // rule RL_rl_connect - assign CAN_FIRE_RL_rl_connect = - master_xactor_f_rd_addr$FULL_N && - slave_xactor_f_rd_addr$EMPTY_N ; - assign WILL_FIRE_RL_rl_connect = CAN_FIRE_RL_rl_connect ; - - // rule RL_rl_connect_1 - assign CAN_FIRE_RL_rl_connect_1 = - slave_xactor_f_wr_resp$FULL_N && - master_xactor_f_wr_resp$EMPTY_N ; - assign WILL_FIRE_RL_rl_connect_1 = CAN_FIRE_RL_rl_connect_1 ; - - // rule RL_rl_connect_2 - assign CAN_FIRE_RL_rl_connect_2 = - slave_xactor_f_rd_data$FULL_N && - master_xactor_f_rd_data$EMPTY_N ; - assign WILL_FIRE_RL_rl_connect_2 = CAN_FIRE_RL_rl_connect_2 ; - - // submodule f_trace_data - assign f_trace_data$D_IN = - { 106'h12AAAAAAA955555554A00000002, - x__h1518[31:0], - slave_xactor_f_wr_addr$D_OUT[92:29], - 32'hAAAAAAAA } ; - assign f_trace_data$ENQ = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8 ; - assign f_trace_data$DEQ = EN_trace_data_out_get ; - assign f_trace_data$CLR = 1'b0 ; - - // submodule master_xactor_f_rd_addr - assign master_xactor_f_rd_addr$D_IN = slave_xactor_f_rd_addr$D_OUT ; - assign master_xactor_f_rd_addr$ENQ = CAN_FIRE_RL_rl_connect ; - assign master_xactor_f_rd_addr$DEQ = - master_xactor_f_rd_addr$EMPTY_N && master_arready ; - assign master_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule master_xactor_f_rd_data - assign master_xactor_f_rd_data$D_IN = - { master_rid, master_rdata, master_rresp, master_rlast } ; - assign master_xactor_f_rd_data$ENQ = - master_rvalid && master_xactor_f_rd_data$FULL_N ; - assign master_xactor_f_rd_data$DEQ = CAN_FIRE_RL_rl_connect_2 ; - assign master_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule master_xactor_f_wr_addr - assign master_xactor_f_wr_addr$D_IN = slave_xactor_f_wr_addr$D_OUT ; - assign master_xactor_f_wr_addr$ENQ = CAN_FIRE_RL_write_reqs ; - assign master_xactor_f_wr_addr$DEQ = - master_xactor_f_wr_addr$EMPTY_N && master_awready ; - assign master_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule master_xactor_f_wr_data - assign master_xactor_f_wr_data$D_IN = slave_xactor_f_wr_data$D_OUT ; - assign master_xactor_f_wr_data$ENQ = CAN_FIRE_RL_write_reqs ; - assign master_xactor_f_wr_data$DEQ = - master_xactor_f_wr_data$EMPTY_N && master_wready ; - assign master_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule master_xactor_f_wr_resp - assign master_xactor_f_wr_resp$D_IN = { master_bid, master_bresp } ; - assign master_xactor_f_wr_resp$ENQ = - master_bvalid && master_xactor_f_wr_resp$FULL_N ; - assign master_xactor_f_wr_resp$DEQ = CAN_FIRE_RL_rl_connect_1 ; - assign master_xactor_f_wr_resp$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { slave_arid, - slave_araddr, - slave_arlen, - slave_arsize, - slave_arburst, - slave_arlock, - slave_arcache, - slave_arprot, - slave_arqos, - slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = - master_xactor_f_rd_addr$FULL_N && - slave_xactor_f_rd_addr$EMPTY_N ; - assign slave_xactor_f_rd_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = master_xactor_f_rd_data$D_OUT ; - assign slave_xactor_f_rd_data$ENQ = - slave_xactor_f_rd_data$FULL_N && - master_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$DEQ = - slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = + // rule RL_slave_xactor_ug_slave_u_ar_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut = + slave_xactor_ug_slave_u_ar_putWire$whas && + slave_xactor_shim_arff_rv[97] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_ar_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut = + !slave_xactor_shim_arff_rv[97] && + slave_xactor_ug_slave_u_ar_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut ; + + // rule RL_mkConnectionGetPut + assign CAN_FIRE_RL_mkConnectionGetPut = + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_arff_rv$port1__read[97] && + !master_xactor_shim_arff_rv[97] ; + assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; + + // rule RL_master_xactor_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; + + // rule RL_master_xactor_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = + master_xactor_ug_master_u_aw_dropWire$whas && + !master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + master_xactor_shim_awff_rv$port1__read[97] && + master_xactor_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ; + + // rule RL_master_xactor_ug_master_u_w_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + + // rule RL_master_xactor_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = + master_xactor_ug_master_u_w_dropWire$whas && + !master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_w_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + master_xactor_shim_wff_rv$port1__read[73] && + master_xactor_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ; + + // rule RL_master_xactor_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = + master_xactor_ug_master_u_b_putWire$whas && + master_xactor_shim_bff_rv[6] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut ; + + // rule RL_master_xactor_ug_master_u_b_doPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut = + !master_xactor_shim_bff_rv[6] && + master_xactor_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut = + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ; + + // rule RL_mkConnectionGetPut_1 + assign CAN_FIRE_RL_mkConnectionGetPut_1 = + !slave_xactor_clearing && !master_xactor_clearing && + master_xactor_shim_bff_rv$port1__read[6] && + !slave_xactor_shim_bff_rv[6] ; + assign WILL_FIRE_RL_mkConnectionGetPut_1 = + CAN_FIRE_RL_mkConnectionGetPut_1 ; + + // rule RL_slave_xactor_ug_slave_u_b_setPeek + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek = + slave_xactor_shim_bff_rv$port1__read[6] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek ; + + // rule RL_slave_xactor_ug_slave_u_b_warnDoDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop = + slave_xactor_ug_slave_u_b_dropWire$whas && + !slave_xactor_shim_bff_rv$port1__read[6] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop ; + + // rule RL_slave_xactor_ug_slave_u_b_doDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop = + slave_xactor_shim_bff_rv$port1__read[6] && + slave_xactor_ug_slave_u_b_dropWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop ; + + // rule RL_master_xactor_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + + // rule RL_master_xactor_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = + master_xactor_ug_master_u_ar_dropWire$whas && + !master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + master_xactor_shim_arff_rv$port1__read[97] && + master_xactor_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ; + + // rule RL_master_xactor_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = + master_xactor_ug_master_u_r_putWire$whas && + master_xactor_shim_rff_rv[71] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut ; + + // rule RL_master_xactor_ug_master_u_r_doPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut = + !master_xactor_shim_rff_rv[71] && + master_xactor_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut = + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ; + + // rule RL_mkConnectionGetPut_2 + assign CAN_FIRE_RL_mkConnectionGetPut_2 = + !slave_xactor_clearing && !master_xactor_clearing && + master_xactor_shim_rff_rv$port1__read[71] && + !slave_xactor_shim_rff_rv[71] ; + assign WILL_FIRE_RL_mkConnectionGetPut_2 = + CAN_FIRE_RL_mkConnectionGetPut_2 ; + + // rule RL_slave_xactor_ug_slave_u_r_setPeek + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek = + slave_xactor_shim_rff_rv$port1__read[71] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek ; + + // rule RL_slave_xactor_ug_slave_u_r_warnDoDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop = + slave_xactor_ug_slave_u_r_dropWire$whas && + !slave_xactor_shim_rff_rv$port1__read[71] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop ; + + // rule RL_slave_xactor_ug_slave_u_r_doDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop = + slave_xactor_shim_rff_rv$port1__read[71] && + slave_xactor_ug_slave_u_r_dropWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop ; + + // rule RL_slave_xactor_do_clear + assign CAN_FIRE_RL_slave_xactor_do_clear = slave_xactor_clearing ; + assign WILL_FIRE_RL_slave_xactor_do_clear = slave_xactor_clearing ; + + // rule RL_master_xactor_do_clear + assign CAN_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; + assign WILL_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; + + // inlined wires + assign slave_xactor_ug_slave_u_aw_putWire$wget = { slave_awid, slave_awaddr, slave_awlen, @@ -990,44 +1527,426 @@ module mkDM_Mem_Tap(CLK, slave_awprot, slave_awqos, slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8 ; - assign slave_xactor_f_wr_addr$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = + assign slave_xactor_ug_slave_u_aw_putWire$whas = + slave_awvalid && !slave_xactor_shim_awff_rv[97] ; + assign slave_xactor_ug_slave_u_w_putWire$wget = { slave_wdata, slave_wstrb, slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8 ; - assign slave_xactor_f_wr_data$CLR = 1'b0 ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = master_xactor_f_wr_resp$D_OUT ; - assign slave_xactor_f_wr_resp$ENQ = - slave_xactor_f_wr_resp$FULL_N && - master_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$DEQ = - slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = 1'b0 ; + assign slave_xactor_ug_slave_u_w_putWire$whas = + slave_wvalid && !slave_xactor_shim_wff_rv[73] ; + assign slave_xactor_ug_slave_u_b_peekWire$wget = + slave_xactor_shim_bff_rv$port1__read[5:0] ; + assign slave_xactor_ug_slave_u_ar_putWire$wget = + { slave_arid, + slave_araddr, + slave_arlen, + slave_arsize, + slave_arburst, + slave_arlock, + slave_arcache, + slave_arprot, + slave_arqos, + slave_arregion } ; + assign slave_xactor_ug_slave_u_ar_putWire$whas = + slave_arvalid && !slave_xactor_shim_arff_rv[97] ; + assign slave_xactor_ug_slave_u_r_peekWire$wget = + slave_xactor_shim_rff_rv$port1__read[70:0] ; + assign master_xactor_ug_master_u_b_putWire$wget = + { master_bid, master_bresp } ; + assign master_xactor_ug_master_u_b_putWire$whas = + master_bvalid && !master_xactor_shim_bff_rv[6] ; + assign master_xactor_ug_master_u_r_putWire$wget = + { master_rid, master_rdata, master_rresp, master_rlast } ; + assign master_xactor_ug_master_u_r_putWire$whas = + master_rvalid && !master_xactor_shim_rff_rv[71] ; + assign slave_xactor_ug_slave_u_b_dropWire$whas = + slave_xactor_shim_bff_rv$port1__read[6] && slave_bready ; + assign slave_xactor_ug_slave_u_r_dropWire$whas = + slave_xactor_shim_rff_rv$port1__read[71] && slave_rready ; + assign master_xactor_ug_master_u_aw_dropWire$whas = + master_xactor_shim_awff_rv$port1__read[97] && master_awready ; + assign master_xactor_ug_master_u_w_dropWire$whas = + master_xactor_shim_wff_rv$port1__read[73] && master_wready ; + assign master_xactor_ug_master_u_ar_dropWire$whas = + master_xactor_shim_arff_rv$port1__read[97] && master_arready ; + assign slave_xactor_shim_awff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_aw_putWire$wget } ; + assign slave_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut ? + slave_xactor_shim_awff_rv$port0__write_1 : + slave_xactor_shim_awff_rv ; + assign slave_xactor_shim_awff_rv$EN_port1__write = + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_awff_rv$port1__read[97] && + slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97 ; + assign slave_xactor_shim_awff_rv$port2__read = + slave_xactor_shim_awff_rv$EN_port1__write ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_awff_rv$port1__read ; + assign slave_xactor_shim_awff_rv$port3__read = + slave_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_awff_rv$port2__read ; + assign slave_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_w_putWire$wget } ; + assign slave_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut ? + slave_xactor_shim_wff_rv$port0__write_1 : + slave_xactor_shim_wff_rv ; + assign slave_xactor_shim_wff_rv$EN_port1__write = + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_awff_rv$port1__read[97] && + slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97 ; + assign slave_xactor_shim_wff_rv$port2__read = + slave_xactor_shim_wff_rv$EN_port1__write ? + 74'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_wff_rv$port1__read ; + assign slave_xactor_shim_wff_rv$port3__read = + slave_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_wff_rv$port2__read ; + assign slave_xactor_shim_bff_rv$EN_port0__write = + !slave_xactor_clearing && !master_xactor_clearing && + master_xactor_shim_bff_rv$port1__read[6] && + !slave_xactor_shim_bff_rv[6] ; + assign slave_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, master_xactor_shim_bff_rv$port1__read[5:0] } ; + assign slave_xactor_shim_bff_rv$port1__read = + slave_xactor_shim_bff_rv$EN_port0__write ? + slave_xactor_shim_bff_rv$port0__write_1 : + slave_xactor_shim_bff_rv ; + assign slave_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop ? + 7'd42 : + slave_xactor_shim_bff_rv$port1__read ; + assign slave_xactor_shim_bff_rv$port3__read = + slave_xactor_clearing ? + 7'd42 : + slave_xactor_shim_bff_rv$port2__read ; + assign slave_xactor_shim_arff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_ar_putWire$wget } ; + assign slave_xactor_shim_arff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut ? + slave_xactor_shim_arff_rv$port0__write_1 : + slave_xactor_shim_arff_rv ; + assign slave_xactor_shim_arff_rv$EN_port1__write = + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_arff_rv$port1__read[97] && + !master_xactor_shim_arff_rv[97] ; + assign slave_xactor_shim_arff_rv$port2__read = + slave_xactor_shim_arff_rv$EN_port1__write ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_arff_rv$port1__read ; + assign slave_xactor_shim_arff_rv$port3__read = + slave_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_arff_rv$port2__read ; + assign slave_xactor_shim_rff_rv$EN_port0__write = + !slave_xactor_clearing && !master_xactor_clearing && + master_xactor_shim_rff_rv$port1__read[71] && + !slave_xactor_shim_rff_rv[71] ; + assign slave_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, master_xactor_shim_rff_rv$port1__read[70:0] } ; + assign slave_xactor_shim_rff_rv$port1__read = + slave_xactor_shim_rff_rv$EN_port0__write ? + slave_xactor_shim_rff_rv$port0__write_1 : + slave_xactor_shim_rff_rv ; + assign slave_xactor_shim_rff_rv$port2__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop ? + 72'h2AAAAAAAAAAAAAAAAA : + slave_xactor_shim_rff_rv$port1__read ; + assign slave_xactor_shim_rff_rv$port3__read = + slave_xactor_clearing ? + 72'h2AAAAAAAAAAAAAAAAA : + slave_xactor_shim_rff_rv$port2__read ; + assign master_xactor_shim_awff_rv$port0__write_1 = + { 1'd1, slave_xactor_shim_awff_rv$port1__read[96:0] } ; + assign master_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_write_reqs ? + master_xactor_shim_awff_rv$port0__write_1 : + master_xactor_shim_awff_rv ; + assign master_xactor_shim_awff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_awff_rv$port1__read ; + assign master_xactor_shim_awff_rv$port3__read = + master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_awff_rv$port2__read ; + assign master_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, slave_xactor_shim_wff_rv$port1__read[72:0] } ; + assign master_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_write_reqs ? + master_xactor_shim_wff_rv$port0__write_1 : + master_xactor_shim_wff_rv ; + assign master_xactor_shim_wff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + master_xactor_shim_wff_rv$port1__read ; + assign master_xactor_shim_wff_rv$port3__read = + master_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + master_xactor_shim_wff_rv$port2__read ; + assign master_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, master_xactor_ug_master_u_b_putWire$wget } ; + assign master_xactor_shim_bff_rv$port1__read = + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ? + master_xactor_shim_bff_rv$port0__write_1 : + master_xactor_shim_bff_rv ; + assign master_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_mkConnectionGetPut_1 ? + 7'd42 : + master_xactor_shim_bff_rv$port1__read ; + assign master_xactor_shim_bff_rv$port3__read = + master_xactor_clearing ? + 7'd42 : + master_xactor_shim_bff_rv$port2__read ; + assign master_xactor_shim_arff_rv$port0__write_1 = + { 1'd1, slave_xactor_shim_arff_rv$port1__read[96:0] } ; + assign master_xactor_shim_arff_rv$port1__read = + CAN_FIRE_RL_mkConnectionGetPut ? + master_xactor_shim_arff_rv$port0__write_1 : + master_xactor_shim_arff_rv ; + assign master_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_arff_rv$port1__read ; + assign master_xactor_shim_arff_rv$port3__read = + master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_arff_rv$port2__read ; + assign master_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, master_xactor_ug_master_u_r_putWire$wget } ; + assign master_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ? + master_xactor_shim_rff_rv$port0__write_1 : + master_xactor_shim_rff_rv ; + assign master_xactor_shim_rff_rv$port2__read = + CAN_FIRE_RL_mkConnectionGetPut_2 ? + 72'h2AAAAAAAAAAAAAAAAA : + master_xactor_shim_rff_rv$port1__read ; + assign master_xactor_shim_rff_rv$port3__read = + master_xactor_clearing ? + 72'h2AAAAAAAAAAAAAAAAA : + master_xactor_shim_rff_rv$port2__read ; + + // register master_xactor_clearing + assign master_xactor_clearing$D_IN = 1'd0 ; + assign master_xactor_clearing$EN = master_xactor_clearing ; + + // register master_xactor_shim_arff_rv + assign master_xactor_shim_arff_rv$D_IN = + master_xactor_shim_arff_rv$port3__read ; + assign master_xactor_shim_arff_rv$EN = 1'b1 ; + + // register master_xactor_shim_awff_rv + assign master_xactor_shim_awff_rv$D_IN = + master_xactor_shim_awff_rv$port3__read ; + assign master_xactor_shim_awff_rv$EN = 1'b1 ; + + // register master_xactor_shim_bff_rv + assign master_xactor_shim_bff_rv$D_IN = + master_xactor_shim_bff_rv$port3__read ; + assign master_xactor_shim_bff_rv$EN = 1'b1 ; + + // register master_xactor_shim_rff_rv + assign master_xactor_shim_rff_rv$D_IN = + master_xactor_shim_rff_rv$port3__read ; + assign master_xactor_shim_rff_rv$EN = 1'b1 ; + + // register master_xactor_shim_wff_rv + assign master_xactor_shim_wff_rv$D_IN = + master_xactor_shim_wff_rv$port3__read ; + assign master_xactor_shim_wff_rv$EN = 1'b1 ; + + // register slave_xactor_clearing + assign slave_xactor_clearing$D_IN = 1'd0 ; + assign slave_xactor_clearing$EN = slave_xactor_clearing ; + + // register slave_xactor_shim_arff_rv + assign slave_xactor_shim_arff_rv$D_IN = + slave_xactor_shim_arff_rv$port3__read ; + assign slave_xactor_shim_arff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_awff_rv + assign slave_xactor_shim_awff_rv$D_IN = + slave_xactor_shim_awff_rv$port3__read ; + assign slave_xactor_shim_awff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_bff_rv + assign slave_xactor_shim_bff_rv$D_IN = + slave_xactor_shim_bff_rv$port3__read ; + assign slave_xactor_shim_bff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_rff_rv + assign slave_xactor_shim_rff_rv$D_IN = + slave_xactor_shim_rff_rv$port3__read ; + assign slave_xactor_shim_rff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_wff_rv + assign slave_xactor_shim_wff_rv$D_IN = + slave_xactor_shim_wff_rv$port3__read ; + assign slave_xactor_shim_wff_rv$EN = 1'b1 ; + + // submodule f_trace_data + assign f_trace_data$D_IN = + { 106'h12AAAAAAA955555554A00000002, + x__h6719[31:0], + slave_xactor_shim_awff_rv$port1__read[92:29], + 32'hAAAAAAAA } ; + assign f_trace_data$ENQ = + !slave_xactor_clearing && !master_xactor_clearing && + slave_xactor_shim_awff_rv$port1__read[97] && + slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97 ; + assign f_trace_data$DEQ = EN_trace_data_out_get ; + assign f_trace_data$CLR = 1'b0 ; // remaining internal signals - assign slave_xactor_f_wr_data_i_notEmpty_AND_master_x_ETC___d8 = - slave_xactor_f_wr_data$EMPTY_N && - master_xactor_f_wr_addr$FULL_N && - master_xactor_f_wr_data$FULL_N && + assign master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q3 = + master_xactor_shim_arff_rv$port1__read[96:0] ; + assign master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q1 = + master_xactor_shim_awff_rv$port1__read[96:0] ; + assign master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q2 = + master_xactor_shim_wff_rv$port1__read[72:0] ; + assign slave_xactor_shim_wff_rv_port1__read__6_BIT_73_ETC___d97 = + slave_xactor_shim_wff_rv$port1__read[73] && + !master_xactor_shim_awff_rv[97] && + !master_xactor_shim_wff_rv[73] && f_trace_data$FULL_N ; - assign stval___1__h1520 = { 32'd0, slave_xactor_f_wr_data$D_OUT[40:9] } ; - assign x__h1518 = - (slave_xactor_f_wr_data$D_OUT[8:1] == 8'h0F) ? - stval___1__h1520 : - y_avValue_fst__h1430 ; - assign y_avValue_fst__h1430 = - { 32'd0, slave_xactor_f_wr_data$D_OUT[72:41] } ; + assign stval___1__h6721 = + { 32'd0, slave_xactor_shim_wff_rv$port1__read[40:9] } ; + assign x__h6719 = + (slave_xactor_shim_wff_rv$port1__read[8:1] == 8'h0F) ? + stval___1__h6721 : + y_avValue_fst__h6631 ; + assign y_avValue_fst__h6631 = + { 32'd0, slave_xactor_shim_wff_rv$port1__read[72:41] } ; + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 7'd42; + master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 72'h2AAAAAAAAAAAAAAAAA; + master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 7'd42; + slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 72'h2AAAAAAAAAAAAAAAAA; + slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + end + else + begin + if (master_xactor_clearing$EN) + master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + master_xactor_clearing$D_IN; + if (master_xactor_shim_arff_rv$EN) + master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_arff_rv$D_IN; + if (master_xactor_shim_awff_rv$EN) + master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_awff_rv$D_IN; + if (master_xactor_shim_bff_rv$EN) + master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_bff_rv$D_IN; + if (master_xactor_shim_rff_rv$EN) + master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_rff_rv$D_IN; + if (master_xactor_shim_wff_rv$EN) + master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_wff_rv$D_IN; + if (slave_xactor_clearing$EN) + slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + slave_xactor_clearing$D_IN; + if (slave_xactor_shim_arff_rv$EN) + slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_arff_rv$D_IN; + if (slave_xactor_shim_awff_rv$EN) + slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_awff_rv$D_IN; + if (slave_xactor_shim_bff_rv$EN) + slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_bff_rv$D_IN; + if (slave_xactor_shim_rff_rv$EN) + slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_rff_rv$D_IN; + if (slave_xactor_shim_wff_rv$EN) + slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_wff_rv$D_IN; + end + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + master_xactor_clearing = 1'h0; + master_xactor_shim_arff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_awff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_bff_rv = 7'h2A; + master_xactor_shim_rff_rv = 72'hAAAAAAAAAAAAAAAAAA; + master_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + slave_xactor_clearing = 1'h0; + slave_xactor_shim_arff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_awff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_bff_rv = 7'h2A; + slave_xactor_shim_rff_rv = 72'hAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + end + // synopsys translate_on endmodule // mkDM_Mem_Tap diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkDM_Run_Control.v b/src_SSITH_P1/xilinx_ip/hdl/mkDM_Run_Control.v index e375e3a1..2c0dfcd5 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkDM_Run_Control.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:15 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkDM_System_Bus.v b/src_SSITH_P1/xilinx_ip/hdl/mkDM_System_Bus.v index 2463761c..8ca3c72f 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkDM_System_Bus.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:33 BST 2019 // // // Ports: @@ -10,33 +10,33 @@ // av_read O 32 // RDY_av_read O 1 // RDY_write O 1 +// master_awid O 4 +// master_awaddr O 64 +// master_awlen O 8 +// master_awsize O 3 +// master_awburst O 2 +// master_awlock O 1 +// master_awcache O 4 +// master_awprot O 3 +// master_awqos O 4 +// master_awregion O 4 // master_awvalid O 1 -// master_awid O 4 reg -// master_awaddr O 64 reg -// master_awlen O 8 reg -// master_awsize O 3 reg -// master_awburst O 2 reg -// master_awlock O 1 reg -// master_awcache O 4 reg -// master_awprot O 3 reg -// master_awqos O 4 reg -// master_awregion O 4 reg +// master_wdata O 64 +// master_wstrb O 8 +// master_wlast O 1 // master_wvalid O 1 -// master_wdata O 64 reg -// master_wstrb O 8 reg -// master_wlast O 1 reg -// master_bready O 1 const +// master_bready O 1 +// master_arid O 4 +// master_araddr O 64 +// master_arlen O 8 +// master_arsize O 3 +// master_arburst O 2 +// master_arlock O 1 +// master_arcache O 4 +// master_arprot O 3 +// master_arqos O 4 +// master_arregion O 4 // master_arvalid O 1 -// master_arid O 4 reg -// master_araddr O 64 reg -// master_arlen O 8 reg -// master_arsize O 3 reg -// master_arburst O 2 reg -// master_arlock O 1 reg -// master_arcache O 4 reg -// master_arprot O 3 reg -// master_arqos O 4 reg -// master_arregion O 4 reg // master_rready O 1 // CLK I 1 clock // RST_N I 1 reset @@ -45,23 +45,265 @@ // write_dm_word I 32 // master_awready I 1 // master_wready I 1 -// master_bvalid I 1 -// master_bid I 4 reg -// master_bresp I 2 reg +// master_bid I 4 +// master_bresp I 2 // master_arready I 1 -// master_rvalid I 1 -// master_rid I 4 reg -// master_rdata I 64 reg -// master_rresp I 2 reg -// master_rlast I 1 reg +// master_rid I 4 +// master_rdata I 64 +// master_rresp I 2 +// master_rlast I 1 // EN_reset I 1 // EN_write I 1 +// master_bvalid I 1 +// master_rvalid I 1 // EN_av_read I 1 // // Combinational paths from inputs to outputs: -// (master_awready, master_wready, master_arready) -> RDY_write -// master_arready -> RDY_av_read -// (master_arready, av_read_dm_addr) -> av_read +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awid +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awaddr +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awlen +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awsize +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awburst +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awlock +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awcache +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awprot +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awqos +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awregion +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awuser +// (write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_awvalid +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_wdata +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_wstrb +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_wlast +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_wuser +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_write, +// master_rvalid) -> master_wvalid +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arid +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_araddr +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arlen +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arsize +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arburst +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arlock +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arcache +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arprot +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arqos +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arregion +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_aruser +// (write_dm_addr, +// write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// av_read_dm_addr, +// EN_write, +// master_rvalid, +// EN_av_read) -> master_arvalid +// av_read_dm_addr -> av_read // // @@ -94,8 +336,6 @@ module mkDM_System_Bus(CLK, EN_write, RDY_write, - master_awvalid, - master_awid, master_awaddr, @@ -116,9 +356,9 @@ module mkDM_System_Bus(CLK, master_awregion, - master_awready, + master_awvalid, - master_wvalid, + master_awready, master_wdata, @@ -126,16 +366,16 @@ module mkDM_System_Bus(CLK, master_wlast, + master_wvalid, + master_wready, - master_bvalid, master_bid, master_bresp, + master_bvalid, master_bready, - master_arvalid, - master_arid, master_araddr, @@ -156,13 +396,15 @@ module mkDM_System_Bus(CLK, master_arregion, + master_arvalid, + master_arready, - master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, + master_rvalid, master_rready); input CLK; @@ -184,115 +426,115 @@ module mkDM_System_Bus(CLK, input EN_write; output RDY_write; - // value method master_m_awvalid - output master_awvalid; - - // value method master_m_awid + // value method master_aw_awid output [3 : 0] master_awid; - // value method master_m_awaddr + // value method master_aw_awaddr output [63 : 0] master_awaddr; - // value method master_m_awlen + // value method master_aw_awlen output [7 : 0] master_awlen; - // value method master_m_awsize + // value method master_aw_awsize output [2 : 0] master_awsize; - // value method master_m_awburst + // value method master_aw_awburst output [1 : 0] master_awburst; - // value method master_m_awlock + // value method master_aw_awlock output master_awlock; - // value method master_m_awcache + // value method master_aw_awcache output [3 : 0] master_awcache; - // value method master_m_awprot + // value method master_aw_awprot output [2 : 0] master_awprot; - // value method master_m_awqos + // value method master_aw_awqos output [3 : 0] master_awqos; - // value method master_m_awregion + // value method master_aw_awregion output [3 : 0] master_awregion; - // value method master_m_awuser + // value method master_aw_awuser - // action method master_m_awready - input master_awready; + // value method master_aw_awvalid + output master_awvalid; - // value method master_m_wvalid - output master_wvalid; + // action method master_aw_awready + input master_awready; - // value method master_m_wdata + // value method master_w_wdata output [63 : 0] master_wdata; - // value method master_m_wstrb + // value method master_w_wstrb output [7 : 0] master_wstrb; - // value method master_m_wlast + // value method master_w_wlast output master_wlast; - // value method master_m_wuser + // value method master_w_wuser - // action method master_m_wready + // value method master_w_wvalid + output master_wvalid; + + // action method master_w_wready input master_wready; - // action method master_m_bvalid - input master_bvalid; + // action method master_b_bflit input [3 : 0] master_bid; input [1 : 0] master_bresp; + input master_bvalid; - // value method master_m_bready + // value method master_b_bready output master_bready; - // value method master_m_arvalid - output master_arvalid; - - // value method master_m_arid + // value method master_ar_arid output [3 : 0] master_arid; - // value method master_m_araddr + // value method master_ar_araddr output [63 : 0] master_araddr; - // value method master_m_arlen + // value method master_ar_arlen output [7 : 0] master_arlen; - // value method master_m_arsize + // value method master_ar_arsize output [2 : 0] master_arsize; - // value method master_m_arburst + // value method master_ar_arburst output [1 : 0] master_arburst; - // value method master_m_arlock + // value method master_ar_arlock output master_arlock; - // value method master_m_arcache + // value method master_ar_arcache output [3 : 0] master_arcache; - // value method master_m_arprot + // value method master_ar_arprot output [2 : 0] master_arprot; - // value method master_m_arqos + // value method master_ar_arqos output [3 : 0] master_arqos; - // value method master_m_arregion + // value method master_ar_arregion output [3 : 0] master_arregion; - // value method master_m_aruser + // value method master_ar_aruser + + // value method master_ar_arvalid + output master_arvalid; - // action method master_m_arready + // action method master_ar_arready input master_arready; - // action method master_m_rvalid - input master_rvalid; + // action method master_r_rflit input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; + input master_rvalid; - // value method master_m_rready + // value method master_r_rready output master_rready; // signals for module outputs @@ -322,64 +564,67 @@ module mkDM_System_Bus(CLK, master_wvalid; // inlined wires - wire master_xactor_crg_rd_addr_full$EN_port1__write, - master_xactor_crg_rd_addr_full$EN_port2__write, - master_xactor_crg_rd_addr_full$port2__read, - master_xactor_crg_rd_addr_full$port3__read, - master_xactor_crg_rd_data_full$EN_port2__write, - master_xactor_crg_rd_data_full$port2__read, - master_xactor_crg_rd_data_full$port3__read, - master_xactor_crg_wr_addr_full$EN_port1__write, - master_xactor_crg_wr_addr_full$port2__read, - master_xactor_crg_wr_addr_full$port3__read, - master_xactor_crg_wr_data_full$EN_port1__write, - master_xactor_crg_wr_data_full$port2__read, - master_xactor_crg_wr_data_full$port3__read; - - // register master_xactor_crg_rd_addr_full - reg master_xactor_crg_rd_addr_full; - wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN; - - // register master_xactor_crg_rd_data_full - reg master_xactor_crg_rd_data_full; - wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN; - - // register master_xactor_crg_wr_addr_full - reg master_xactor_crg_wr_addr_full; - wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN; - - // register master_xactor_crg_wr_data_full - reg master_xactor_crg_wr_data_full; - wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN; - - // register master_xactor_crg_wr_resp_full - reg master_xactor_crg_wr_resp_full; - wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN; - - // register master_xactor_rg_rd_addr - reg [96 : 0] master_xactor_rg_rd_addr; - wire [96 : 0] master_xactor_rg_rd_addr$D_IN; - wire master_xactor_rg_rd_addr$EN; - - // register master_xactor_rg_rd_data - reg [70 : 0] master_xactor_rg_rd_data; - wire [70 : 0] master_xactor_rg_rd_data$D_IN; - wire master_xactor_rg_rd_data$EN; - - // register master_xactor_rg_wr_addr - reg [96 : 0] master_xactor_rg_wr_addr; - wire [96 : 0] master_xactor_rg_wr_addr$D_IN; - wire master_xactor_rg_wr_addr$EN; - - // register master_xactor_rg_wr_data - reg [72 : 0] master_xactor_rg_wr_data; - wire [72 : 0] master_xactor_rg_wr_data$D_IN; - wire master_xactor_rg_wr_data$EN; - - // register master_xactor_rg_wr_resp - reg [5 : 0] master_xactor_rg_wr_resp; - wire [5 : 0] master_xactor_rg_wr_resp$D_IN; - wire master_xactor_rg_wr_resp$EN; + wire [97 : 0] master_xactor_shim_arff_rv$port0__write_1, + master_xactor_shim_arff_rv$port1__read, + master_xactor_shim_arff_rv$port2__read, + master_xactor_shim_arff_rv$port3__read, + master_xactor_shim_awff_rv$port0__write_1, + master_xactor_shim_awff_rv$port1__read, + master_xactor_shim_awff_rv$port2__read, + master_xactor_shim_awff_rv$port3__read; + wire [73 : 0] master_xactor_shim_wff_rv$port0__write_1, + master_xactor_shim_wff_rv$port1__read, + master_xactor_shim_wff_rv$port2__read, + master_xactor_shim_wff_rv$port3__read; + wire [71 : 0] master_xactor_shim_rff_rv$port0__write_1, + master_xactor_shim_rff_rv$port1__read, + master_xactor_shim_rff_rv$port2__read, + master_xactor_shim_rff_rv$port3__read; + wire [70 : 0] master_xactor_ug_master_u_r_putWire$wget; + wire [6 : 0] master_xactor_shim_bff_rv$port0__write_1, + master_xactor_shim_bff_rv$port1__read, + master_xactor_shim_bff_rv$port2__read, + master_xactor_shim_bff_rv$port3__read; + wire [5 : 0] master_xactor_ug_master_u_b_putWire$wget; + wire master_xactor_shim_arff_rv$EN_port0__write, + master_xactor_shim_awff_rv$EN_port0__write, + master_xactor_shim_bff_rv$EN_port1__write, + master_xactor_shim_rff_rv$EN_port1__write, + master_xactor_shim_wff_rv$EN_port0__write, + master_xactor_ug_master_u_ar_dropWire$whas, + master_xactor_ug_master_u_aw_dropWire$whas, + master_xactor_ug_master_u_b_putWire$whas, + master_xactor_ug_master_u_r_putWire$whas, + master_xactor_ug_master_u_w_dropWire$whas; + + // register master_xactor_clearing + reg master_xactor_clearing; + wire master_xactor_clearing$D_IN, master_xactor_clearing$EN; + + // register master_xactor_shim_arff_rv + reg [97 : 0] master_xactor_shim_arff_rv; + wire [97 : 0] master_xactor_shim_arff_rv$D_IN; + wire master_xactor_shim_arff_rv$EN; + + // register master_xactor_shim_awff_rv + reg [97 : 0] master_xactor_shim_awff_rv; + wire [97 : 0] master_xactor_shim_awff_rv$D_IN; + wire master_xactor_shim_awff_rv$EN; + + // register master_xactor_shim_bff_rv + reg [6 : 0] master_xactor_shim_bff_rv; + wire [6 : 0] master_xactor_shim_bff_rv$D_IN; + wire master_xactor_shim_bff_rv$EN; + + // register master_xactor_shim_rff_rv + reg [71 : 0] master_xactor_shim_rff_rv; + wire [71 : 0] master_xactor_shim_rff_rv$D_IN; + wire master_xactor_shim_rff_rv$EN; + + // register master_xactor_shim_wff_rv + reg [73 : 0] master_xactor_shim_wff_rv; + wire [73 : 0] master_xactor_shim_wff_rv$D_IN; + wire master_xactor_shim_wff_rv$EN; // register rg_sb_state reg [1 : 0] rg_sb_state; @@ -434,33 +679,61 @@ module mkDM_System_Bus(CLK, wire rg_sbdata0$EN; // rule scheduling signals - wire CAN_FIRE_RL_rl_sb_read_finish, + wire CAN_FIRE_RL_master_xactor_do_clear, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut, + CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut, + CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop, + CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek, + CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_rl_sb_read_finish, CAN_FIRE_RL_rl_sb_write_response, CAN_FIRE_av_read, - CAN_FIRE_master_m_arready, - CAN_FIRE_master_m_awready, - CAN_FIRE_master_m_bvalid, - CAN_FIRE_master_m_rvalid, - CAN_FIRE_master_m_wready, + CAN_FIRE_master_ar_arready, + CAN_FIRE_master_aw_awready, + CAN_FIRE_master_b_bflit, + CAN_FIRE_master_r_rflit, + CAN_FIRE_master_w_wready, CAN_FIRE_reset, CAN_FIRE_write, + WILL_FIRE_RL_master_xactor_do_clear, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut, + WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut, + WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop, + WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek, + WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop, WILL_FIRE_RL_rl_sb_read_finish, WILL_FIRE_RL_rl_sb_write_response, WILL_FIRE_av_read, - WILL_FIRE_master_m_arready, - WILL_FIRE_master_m_awready, - WILL_FIRE_master_m_bvalid, - WILL_FIRE_master_m_rvalid, - WILL_FIRE_master_m_wready, + WILL_FIRE_master_ar_arready, + WILL_FIRE_master_aw_awready, + WILL_FIRE_master_b_bflit, + WILL_FIRE_master_r_rflit, + WILL_FIRE_master_w_wready, WILL_FIRE_reset, WILL_FIRE_write; // inputs to muxes for submodule ports reg [31 : 0] MUX_rg_sbaddress0$write_1__VAL_2; reg [2 : 0] MUX_rg_sbcs_sberror$write_1__VAL_4; - wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1, - MUX_master_xactor_rg_rd_addr$write_1__VAL_2; - wire MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1, + wire [97 : 0] MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1, + MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2; + wire MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1, MUX_rg_sbaddress0$write_1__SEL_2, MUX_rg_sbaddress0$write_1__SEL_3, MUX_rg_sbaddress1$write_1__SEL_2, @@ -473,48 +746,51 @@ module mkDM_System_Bus(CLK, // remaining internal signals reg [63 : 0] CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1, - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53, - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66, - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103, - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79, - wrd_wdata__h5077; - reg [7 : 0] wrd_wstrb__h5078; - reg [2 : 0] x__h3263, x__h4949; - wire [63 : 0] _theResult___fst__h4987, - addr64310_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2, - addr64__h4310, - result__h1836, - result__h1866, - result__h1893, - result__h1920, - result__h1947, - result__h1974, - result__h2001, - result__h2028, - result__h2073, - result__h2100, - result__h2127, - result__h2154, - result__h2195, - result__h2222, - sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3, - sbaddress__h1228, - word64__h4931; - wire [31 : 0] IF_rg_sbcs_sbreadonaddr_23_THEN_IF_rg_sbcs_sba_ETC___d307, - v__h2727, - v__h2861; - wire [7 : 0] strobe64__h4986, strobe64__h4989, strobe64__h4992; - wire [5 : 0] shift_bits__h4934; - wire rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109, - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313, - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95, - rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291, - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256, - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265, - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271, - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273, - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278, - write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d323; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103, + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116, + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154, + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129, + wrd_wdata__h7216; + reg [7 : 0] wrd_wstrb__h7217; + reg [2 : 0] _theResult___snd_snd_val__h7102, axi4_size_val__h5371; + wire [96 : 0] master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5, + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3; + wire [72 : 0] master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q4; + wire [63 : 0] _theResult___fst__h7087, + addr64393_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2, + addr64__h6393, + result__h3808, + result__h3838, + result__h3865, + result__h3892, + result__h3919, + result__h3946, + result__h3973, + result__h4000, + result__h4045, + result__h4072, + result__h4099, + result__h4126, + result__h4167, + result__h4194, + sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6, + sbaddress__h3099, + word64__h7032; + wire [31 : 0] IF_rg_sbcs_sbreadonaddr_74_THEN_IF_rg_sbcs_sba_ETC___d360, + v__h4783, + v__h4917; + wire [7 : 0] strobe64__h7085, strobe64__h7089, strobe64__h7093; + wire [5 : 0] shift_bits__h7035; + wire rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146, + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160, + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d366, + rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d344, + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309, + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d318, + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d324, + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d326, + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d331, + write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376; // action method reset assign RDY_reset = 1'd1 ; @@ -523,13 +799,13 @@ module mkDM_System_Bus(CLK, // actionvalue method av_read always@(av_read_dm_addr or - v__h2727 or rg_sbaddress0 or rg_sbaddress1 or v__h2861) + v__h4783 or rg_sbaddress0 or rg_sbaddress1 or v__h4917) begin case (av_read_dm_addr) - 7'h38: av_read = v__h2727; + 7'h38: av_read = v__h4783; 7'h39: av_read = rg_sbaddress0; 7'h3A: av_read = rg_sbaddress1; - 7'h3C: av_read = v__h2861; + 7'h3C: av_read = v__h4917; default: av_read = 32'd0; endcase end @@ -537,7 +813,7 @@ module mkDM_System_Bus(CLK, rg_sb_state == 2'd0 && (rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || !rg_sbcs_sbreadondata || - !master_xactor_crg_rd_addr_full$port2__read) ; + !master_xactor_clearing && !master_xactor_shim_arff_rv[97]) ; assign CAN_FIRE_av_read = RDY_av_read ; assign WILL_FIRE_av_read = EN_av_read ; @@ -547,180 +823,304 @@ module mkDM_System_Bus(CLK, (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || !rg_sbcs_sbreadonaddr || - !master_xactor_crg_rd_addr_full$port2__read) && + !master_xactor_clearing && !master_xactor_shim_arff_rv[97]) && (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 || - !master_xactor_crg_wr_addr_full$port2__read && - !master_xactor_crg_wr_data_full$port2__read) ; + !master_xactor_clearing && !master_xactor_shim_awff_rv[97] && + !master_xactor_shim_wff_rv[73]) ; assign WILL_FIRE_write = EN_write ; - // value method master_m_awvalid - assign master_awvalid = master_xactor_crg_wr_addr_full ; - - // value method master_m_awid - assign master_awid = master_xactor_rg_wr_addr[96:93] ; - - // value method master_m_awaddr - assign master_awaddr = master_xactor_rg_wr_addr[92:29] ; - - // value method master_m_awlen - assign master_awlen = master_xactor_rg_wr_addr[28:21] ; - - // value method master_m_awsize - assign master_awsize = master_xactor_rg_wr_addr[20:18] ; - - // value method master_m_awburst - assign master_awburst = master_xactor_rg_wr_addr[17:16] ; + // value method master_aw_awid + assign master_awid = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[96:93] ; - // value method master_m_awlock - assign master_awlock = master_xactor_rg_wr_addr[15] ; + // value method master_aw_awaddr + assign master_awaddr = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[92:29] ; - // value method master_m_awcache - assign master_awcache = master_xactor_rg_wr_addr[14:11] ; + // value method master_aw_awlen + assign master_awlen = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[28:21] ; - // value method master_m_awprot - assign master_awprot = master_xactor_rg_wr_addr[10:8] ; + // value method master_aw_awsize + assign master_awsize = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[20:18] ; - // value method master_m_awqos - assign master_awqos = master_xactor_rg_wr_addr[7:4] ; + // value method master_aw_awburst + assign master_awburst = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[17:16] ; - // value method master_m_awregion - assign master_awregion = master_xactor_rg_wr_addr[3:0] ; + // value method master_aw_awlock + assign master_awlock = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[15] ; - // action method master_m_awready - assign CAN_FIRE_master_m_awready = 1'd1 ; - assign WILL_FIRE_master_m_awready = 1'd1 ; + // value method master_aw_awcache + assign master_awcache = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[14:11] ; - // value method master_m_wvalid - assign master_wvalid = master_xactor_crg_wr_data_full ; + // value method master_aw_awprot + assign master_awprot = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[10:8] ; - // value method master_m_wdata - assign master_wdata = master_xactor_rg_wr_data[72:9] ; + // value method master_aw_awqos + assign master_awqos = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[7:4] ; - // value method master_m_wstrb - assign master_wstrb = master_xactor_rg_wr_data[8:1] ; + // value method master_aw_awregion + assign master_awregion = + master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3[3:0] ; - // value method master_m_wlast - assign master_wlast = master_xactor_rg_wr_data[0] ; + // value method master_aw_awvalid + assign master_awvalid = CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; - // action method master_m_wready - assign CAN_FIRE_master_m_wready = 1'd1 ; - assign WILL_FIRE_master_m_wready = 1'd1 ; - - // action method master_m_bvalid - assign CAN_FIRE_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_master_m_bvalid = 1'd1 ; - - // value method master_m_bready - assign master_bready = 1'b1 ; - - // value method master_m_arvalid - assign master_arvalid = master_xactor_crg_rd_addr_full ; - - // value method master_m_arid - assign master_arid = master_xactor_rg_rd_addr[96:93] ; - - // value method master_m_araddr - assign master_araddr = master_xactor_rg_rd_addr[92:29] ; - - // value method master_m_arlen - assign master_arlen = master_xactor_rg_rd_addr[28:21] ; - - // value method master_m_arsize - assign master_arsize = master_xactor_rg_rd_addr[20:18] ; - - // value method master_m_arburst - assign master_arburst = master_xactor_rg_rd_addr[17:16] ; - - // value method master_m_arlock - assign master_arlock = master_xactor_rg_rd_addr[15] ; - - // value method master_m_arcache - assign master_arcache = master_xactor_rg_rd_addr[14:11] ; - - // value method master_m_arprot - assign master_arprot = master_xactor_rg_rd_addr[10:8] ; - - // value method master_m_arqos - assign master_arqos = master_xactor_rg_rd_addr[7:4] ; - - // value method master_m_arregion - assign master_arregion = master_xactor_rg_rd_addr[3:0] ; - - // action method master_m_arready - assign CAN_FIRE_master_m_arready = 1'd1 ; - assign WILL_FIRE_master_m_arready = 1'd1 ; - - // action method master_m_rvalid - assign CAN_FIRE_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_master_m_rvalid = 1'd1 ; - - // value method master_m_rready - assign master_rready = !master_xactor_crg_rd_data_full$port2__read ; + // action method master_aw_awready + assign CAN_FIRE_master_aw_awready = 1'd1 ; + assign WILL_FIRE_master_aw_awready = 1'd1 ; + + // value method master_w_wdata + assign master_wdata = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q4[72:9] ; + + // value method master_w_wstrb + assign master_wstrb = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q4[8:1] ; + + // value method master_w_wlast + assign master_wlast = + master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q4[0] ; + + // value method master_w_wvalid + assign master_wvalid = CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + + // action method master_w_wready + assign CAN_FIRE_master_w_wready = 1'd1 ; + assign WILL_FIRE_master_w_wready = 1'd1 ; + + // action method master_b_bflit + assign CAN_FIRE_master_b_bflit = 1'd1 ; + assign WILL_FIRE_master_b_bflit = master_bvalid ; + + // value method master_b_bready + assign master_bready = !master_xactor_shim_bff_rv[6] ; + + // value method master_ar_arid + assign master_arid = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[96:93] ; + + // value method master_ar_araddr + assign master_araddr = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[92:29] ; + + // value method master_ar_arlen + assign master_arlen = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[28:21] ; + + // value method master_ar_arsize + assign master_arsize = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[20:18] ; + + // value method master_ar_arburst + assign master_arburst = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[17:16] ; + + // value method master_ar_arlock + assign master_arlock = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[15] ; + + // value method master_ar_arcache + assign master_arcache = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[14:11] ; + + // value method master_ar_arprot + assign master_arprot = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[10:8] ; + + // value method master_ar_arqos + assign master_arqos = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[7:4] ; + + // value method master_ar_arregion + assign master_arregion = + master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5[3:0] ; + + // value method master_ar_arvalid + assign master_arvalid = CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + + // action method master_ar_arready + assign CAN_FIRE_master_ar_arready = 1'd1 ; + assign WILL_FIRE_master_ar_arready = 1'd1 ; + + // action method master_r_rflit + assign CAN_FIRE_master_r_rflit = 1'd1 ; + assign WILL_FIRE_master_r_rflit = master_rvalid ; + + // value method master_r_rready + assign master_rready = !master_xactor_shim_rff_rv[71] ; + + // rule RL_master_xactor_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = + master_xactor_ug_master_u_b_putWire$whas && + master_xactor_shim_bff_rv[6] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut ; + + // rule RL_master_xactor_ug_master_u_b_doPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut = + !master_xactor_shim_bff_rv[6] && + master_xactor_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_b_doPut = + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ; + + // rule RL_master_xactor_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = + master_xactor_ug_master_u_r_putWire$whas && + master_xactor_shim_rff_rv[71] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut ; + + // rule RL_master_xactor_ug_master_u_r_doPut + assign CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut = + !master_xactor_shim_rff_rv[71] && + master_xactor_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_r_doPut = + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ; // rule RL_rl_sb_read_finish assign CAN_FIRE_RL_rl_sb_read_finish = - master_xactor_crg_rd_data_full && rg_sb_state == 2'd1 && + !master_xactor_clearing && + master_xactor_shim_rff_rv$port1__read[71] && + rg_sb_state == 2'd1 && rg_sbcs_sberror == 3'd0 ; assign WILL_FIRE_RL_rl_sb_read_finish = CAN_FIRE_RL_rl_sb_read_finish ; // rule RL_rl_sb_write_response - assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ; - assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ; + assign CAN_FIRE_RL_rl_sb_write_response = + !master_xactor_clearing && + master_xactor_shim_bff_rv$port1__read[6] ; + assign WILL_FIRE_RL_rl_sb_write_response = + CAN_FIRE_RL_rl_sb_write_response ; + + // rule RL_master_xactor_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_setPeek ; + + // rule RL_master_xactor_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = + master_xactor_ug_master_u_aw_dropWire$whas && + !master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + master_xactor_shim_awff_rv$port1__read[97] && + master_xactor_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_aw_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ; + + // rule RL_master_xactor_ug_master_u_w_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_w_setPeek ; + + // rule RL_master_xactor_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = + master_xactor_ug_master_u_w_dropWire$whas && + !master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_w_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + master_xactor_shim_wff_rv$port1__read[73] && + master_xactor_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_w_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ; + + // rule RL_master_xactor_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_setPeek = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_setPeek ; + + // rule RL_master_xactor_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = + master_xactor_ug_master_u_ar_dropWire$whas && + !master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop ; + + // rule RL_master_xactor_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + master_xactor_shim_arff_rv$port1__read[97] && + master_xactor_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_master_xactor_ug_master_u_ar_doDrop = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ; + + // rule RL_master_xactor_do_clear + assign CAN_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; + assign WILL_FIRE_RL_master_xactor_do_clear = master_xactor_clearing ; // inputs to muxes for submodule ports - assign MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 = + assign MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160 ; assign MUX_rg_sbaddress0$write_1__SEL_2 = EN_write && write_dm_addr != 7'h38 && (rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && write_dm_addr == 7'h39 || write_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146) ; assign MUX_rg_sbaddress0$write_1__SEL_3 = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146 ; assign MUX_rg_sbaddress1$write_1__SEL_2 = EN_write && write_dm_addr != 7'h38 && ((write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) && rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && - rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 || + rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d344 || write_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146) ; assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ; + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d318 ; assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_3 = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_1 = - master_xactor_crg_wr_resp_full && - master_xactor_rg_wr_resp[1:0] != 2'b0 ; + WILL_FIRE_RL_rl_sb_write_response && + master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_3 = WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 ; + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; assign MUX_rg_sbcs_sberror$write_1__SEL_4 = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ; + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d326 ; assign MUX_rg_sbdata0$write_1__SEL_3 = EN_write && - write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d323 ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 = - { 4'd0, sbaddress__h1228, 8'd0, x__h3263, 18'd65536 } ; - assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 = - { 4'd0, addr64__h4310, 8'd0, x__h3263, 18'd65536 } ; + write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376 ; + assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1 = + { 5'd16, + sbaddress__h3099, + 8'd0, + axi4_size_val__h5371, + 18'd65536 } ; + assign MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2 = + { 5'd16, addr64__h6393, 8'd0, axi4_size_val__h5371, 18'd65536 } ; always@(write_dm_addr or - sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3 or - IF_rg_sbcs_sbreadonaddr_23_THEN_IF_rg_sbcs_sba_ETC___d307) + sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6 or + IF_rg_sbcs_sbreadonaddr_74_THEN_IF_rg_sbcs_sba_ETC___d360) begin case (write_dm_addr) 7'h39, 7'h3A: MUX_rg_sbaddress0$write_1__VAL_2 = - IF_rg_sbcs_sbreadonaddr_23_THEN_IF_rg_sbcs_sba_ETC___d307; + IF_rg_sbcs_sbreadonaddr_74_THEN_IF_rg_sbcs_sba_ETC___d360; default: MUX_rg_sbaddress0$write_1__VAL_2 = - sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3[31:0]; + sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6[31:0]; endcase end always@(write_dm_word) @@ -732,107 +1132,153 @@ module mkDM_System_Bus(CLK, end // inlined wires - assign master_xactor_crg_wr_addr_full$EN_port1__write = - master_xactor_crg_wr_addr_full && master_awready ; - assign master_xactor_crg_wr_addr_full$port2__read = - !master_xactor_crg_wr_addr_full$EN_port1__write && - master_xactor_crg_wr_addr_full ; - assign master_xactor_crg_wr_addr_full$port3__read = - MUX_rg_sbdata0$write_1__SEL_3 || - master_xactor_crg_wr_addr_full$port2__read ; - assign master_xactor_crg_wr_data_full$EN_port1__write = - master_xactor_crg_wr_data_full && master_wready ; - assign master_xactor_crg_wr_data_full$port2__read = - !master_xactor_crg_wr_data_full$EN_port1__write && - master_xactor_crg_wr_data_full ; - assign master_xactor_crg_wr_data_full$port3__read = - MUX_rg_sbdata0$write_1__SEL_3 || - master_xactor_crg_wr_data_full$port2__read ; - assign master_xactor_crg_rd_addr_full$EN_port1__write = - master_xactor_crg_rd_addr_full && master_arready ; - assign master_xactor_crg_rd_addr_full$port2__read = - !master_xactor_crg_rd_addr_full$EN_port1__write && - master_xactor_crg_rd_addr_full ; - assign master_xactor_crg_rd_addr_full$EN_port2__write = - EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 || - EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313 ; - assign master_xactor_crg_rd_addr_full$port3__read = - master_xactor_crg_rd_addr_full$EN_port2__write ? - 1'd1 : - master_xactor_crg_rd_addr_full$port2__read ; - assign master_xactor_crg_rd_data_full$port2__read = - !CAN_FIRE_RL_rl_sb_read_finish && - master_xactor_crg_rd_data_full ; - assign master_xactor_crg_rd_data_full$EN_port2__write = - master_rvalid && !master_xactor_crg_rd_data_full$port2__read ; - assign master_xactor_crg_rd_data_full$port3__read = - master_xactor_crg_rd_data_full$EN_port2__write || - master_xactor_crg_rd_data_full$port2__read ; - - // register master_xactor_crg_rd_addr_full - assign master_xactor_crg_rd_addr_full$D_IN = - master_xactor_crg_rd_addr_full$port3__read ; - assign master_xactor_crg_rd_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_rd_data_full - assign master_xactor_crg_rd_data_full$D_IN = - master_xactor_crg_rd_data_full$port3__read ; - assign master_xactor_crg_rd_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_addr_full - assign master_xactor_crg_wr_addr_full$D_IN = - master_xactor_crg_wr_addr_full$port3__read ; - assign master_xactor_crg_wr_addr_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_data_full - assign master_xactor_crg_wr_data_full$D_IN = - master_xactor_crg_wr_data_full$port3__read ; - assign master_xactor_crg_wr_data_full$EN = 1'b1 ; - - // register master_xactor_crg_wr_resp_full - assign master_xactor_crg_wr_resp_full$D_IN = master_bvalid ; - assign master_xactor_crg_wr_resp_full$EN = 1'b1 ; - - // register master_xactor_rg_rd_addr - assign master_xactor_rg_rd_addr$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - MUX_master_xactor_rg_rd_addr$write_1__VAL_1 : - MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ; - assign master_xactor_rg_rd_addr$EN = + assign master_xactor_ug_master_u_b_putWire$wget = + { master_bid, master_bresp } ; + assign master_xactor_ug_master_u_b_putWire$whas = + master_bvalid && !master_xactor_shim_bff_rv[6] ; + assign master_xactor_ug_master_u_r_putWire$wget = + { master_rid, master_rdata, master_rresp, master_rlast } ; + assign master_xactor_ug_master_u_r_putWire$whas = + master_rvalid && !master_xactor_shim_rff_rv[71] ; + assign master_xactor_ug_master_u_aw_dropWire$whas = + master_xactor_shim_awff_rv$port1__read[97] && master_awready ; + assign master_xactor_ug_master_u_w_dropWire$whas = + master_xactor_shim_wff_rv$port1__read[73] && master_wready ; + assign master_xactor_ug_master_u_ar_dropWire$whas = + master_xactor_shim_arff_rv$port1__read[97] && master_arready ; + assign master_xactor_shim_awff_rv$EN_port0__write = + EN_write && + write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376 ; + assign master_xactor_shim_awff_rv$port0__write_1 = + { 5'd16, + sbaddress__h3099, + 8'd0, + _theResult___snd_snd_val__h7102, + 18'd65536 } ; + assign master_xactor_shim_awff_rv$port1__read = + master_xactor_shim_awff_rv$EN_port0__write ? + master_xactor_shim_awff_rv$port0__write_1 : + master_xactor_shim_awff_rv ; + assign master_xactor_shim_awff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_aw_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_awff_rv$port1__read ; + assign master_xactor_shim_awff_rv$port3__read = + master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_awff_rv$port2__read ; + assign master_xactor_shim_wff_rv$EN_port0__write = + EN_write && + write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376 ; + assign master_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, wrd_wdata__h7216, wrd_wstrb__h7217, 1'd1 } ; + assign master_xactor_shim_wff_rv$port1__read = + master_xactor_shim_wff_rv$EN_port0__write ? + master_xactor_shim_wff_rv$port0__write_1 : + master_xactor_shim_wff_rv ; + assign master_xactor_shim_wff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_w_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + master_xactor_shim_wff_rv$port1__read ; + assign master_xactor_shim_wff_rv$port3__read = + master_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + master_xactor_shim_wff_rv$port2__read ; + assign master_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, master_xactor_ug_master_u_b_putWire$wget } ; + assign master_xactor_shim_bff_rv$port1__read = + CAN_FIRE_RL_master_xactor_ug_master_u_b_doPut ? + master_xactor_shim_bff_rv$port0__write_1 : + master_xactor_shim_bff_rv ; + assign master_xactor_shim_bff_rv$EN_port1__write = + !master_xactor_clearing && + master_xactor_shim_bff_rv$port1__read[6] ; + assign master_xactor_shim_bff_rv$port2__read = + master_xactor_shim_bff_rv$EN_port1__write ? + 7'd42 : + master_xactor_shim_bff_rv$port1__read ; + assign master_xactor_shim_bff_rv$port3__read = + master_xactor_clearing ? + 7'd42 : + master_xactor_shim_bff_rv$port2__read ; + assign master_xactor_shim_arff_rv$EN_port0__write = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313 ; - - // register master_xactor_rg_rd_data - assign master_xactor_rg_rd_data$D_IN = - { master_rid, master_rdata, master_rresp, master_rlast } ; - assign master_xactor_rg_rd_data$EN = 1'd1 ; - - // register master_xactor_rg_wr_addr - assign master_xactor_rg_wr_addr$D_IN = - { 4'd0, sbaddress__h1228, 8'd0, x__h4949, 18'd65536 } ; - assign master_xactor_rg_wr_addr$EN = MUX_rg_sbdata0$write_1__SEL_3 ; - - // register master_xactor_rg_wr_data - assign master_xactor_rg_wr_data$D_IN = - { wrd_wdata__h5077, wrd_wstrb__h5078, 1'd1 } ; - assign master_xactor_rg_wr_data$EN = MUX_rg_sbdata0$write_1__SEL_3 ; - - // register master_xactor_rg_wr_resp - assign master_xactor_rg_wr_resp$D_IN = { master_bid, master_bresp } ; - assign master_xactor_rg_wr_resp$EN = master_bvalid ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d366 ; + assign master_xactor_shim_arff_rv$port0__write_1 = + MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? + MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_1 : + MUX_master_xactor_shim_arff_rv$port0__write_1__VAL_2 ; + assign master_xactor_shim_arff_rv$port1__read = + master_xactor_shim_arff_rv$EN_port0__write ? + master_xactor_shim_arff_rv$port0__write_1 : + master_xactor_shim_arff_rv ; + assign master_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_master_xactor_ug_master_u_ar_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_arff_rv$port1__read ; + assign master_xactor_shim_arff_rv$port3__read = + master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + master_xactor_shim_arff_rv$port2__read ; + assign master_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, master_xactor_ug_master_u_r_putWire$wget } ; + assign master_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_master_xactor_ug_master_u_r_doPut ? + master_xactor_shim_rff_rv$port0__write_1 : + master_xactor_shim_rff_rv ; + assign master_xactor_shim_rff_rv$EN_port1__write = + !master_xactor_clearing && + master_xactor_shim_rff_rv$port1__read[71] && + rg_sb_state == 2'd1 && + rg_sbcs_sberror == 3'd0 ; + assign master_xactor_shim_rff_rv$port2__read = + master_xactor_shim_rff_rv$EN_port1__write ? + 72'h2AAAAAAAAAAAAAAAAA : + master_xactor_shim_rff_rv$port1__read ; + assign master_xactor_shim_rff_rv$port3__read = + master_xactor_clearing ? + 72'h2AAAAAAAAAAAAAAAAA : + master_xactor_shim_rff_rv$port2__read ; + + // register master_xactor_clearing + assign master_xactor_clearing$D_IN = 1'd0 ; + assign master_xactor_clearing$EN = master_xactor_clearing ; + + // register master_xactor_shim_arff_rv + assign master_xactor_shim_arff_rv$D_IN = + master_xactor_shim_arff_rv$port3__read ; + assign master_xactor_shim_arff_rv$EN = 1'b1 ; + + // register master_xactor_shim_awff_rv + assign master_xactor_shim_awff_rv$D_IN = + master_xactor_shim_awff_rv$port3__read ; + assign master_xactor_shim_awff_rv$EN = 1'b1 ; + + // register master_xactor_shim_bff_rv + assign master_xactor_shim_bff_rv$D_IN = + master_xactor_shim_bff_rv$port3__read ; + assign master_xactor_shim_bff_rv$EN = 1'b1 ; + + // register master_xactor_shim_rff_rv + assign master_xactor_shim_rff_rv$D_IN = + master_xactor_shim_rff_rv$port3__read ; + assign master_xactor_shim_rff_rv$EN = 1'b1 ; + + // register master_xactor_shim_wff_rv + assign master_xactor_shim_wff_rv$D_IN = + master_xactor_shim_wff_rv$port3__read ; + assign master_xactor_shim_wff_rv$EN = 1'b1 ; // register rg_sb_state assign rg_sb_state$D_IN = (EN_reset || WILL_FIRE_RL_rl_sb_read_finish) ? 2'd0 : 2'd1 ; assign rg_sb_state$EN = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d366 || WILL_FIRE_RL_rl_sb_read_finish || EN_reset ; @@ -841,19 +1287,19 @@ module mkDM_System_Bus(CLK, MUX_rg_sbaddress0$write_1__SEL_2 or MUX_rg_sbaddress0$write_1__VAL_2 or MUX_rg_sbaddress0$write_1__SEL_3 or - sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3) + sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6) case (1'b1) EN_reset: rg_sbaddress0$D_IN = 32'd0; MUX_rg_sbaddress0$write_1__SEL_2: rg_sbaddress0$D_IN = MUX_rg_sbaddress0$write_1__VAL_2; MUX_rg_sbaddress0$write_1__SEL_3: rg_sbaddress0$D_IN = - sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3[31:0]; + sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6[31:0]; default: rg_sbaddress0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase assign rg_sbaddress0$EN = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146 || MUX_rg_sbaddress0$write_1__SEL_2 || EN_reset ; @@ -861,33 +1307,33 @@ module mkDM_System_Bus(CLK, assign rg_sbaddress1$D_IN = 32'd0 ; assign rg_sbaddress1$EN = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146 || MUX_rg_sbaddress1$write_1__SEL_2 || EN_reset ; // register rg_sbaddress_reading assign rg_sbaddress_reading$D_IN = - MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ? - sbaddress__h1228 : - addr64__h4310 ; + MUX_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? + sbaddress__h3099 : + addr64__h6393 ; assign rg_sbaddress_reading$EN = EN_av_read && av_read_dm_addr == 7'h3C && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 || + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160 || EN_write && write_dm_addr == 7'h39 && - rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313 ; + rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d366 ; // register rg_sbcs_sbaccess assign rg_sbcs_sbaccess$D_IN = EN_reset ? 3'd2 : write_dm_word[19:17] ; assign rg_sbcs_sbaccess$EN = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 || EN_reset ; // register rg_sbcs_sbautoincrement assign rg_sbcs_sbautoincrement$D_IN = !EN_reset && write_dm_word[16] ; assign rg_sbcs_sbautoincrement$EN = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 || EN_reset ; // register rg_sbcs_sbbusyerror @@ -904,7 +1350,7 @@ module mkDM_System_Bus(CLK, assign rg_sbcs_sbbusyerror$EN = EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 || EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d318 || EN_reset ; // register rg_sbcs_sberror @@ -923,97 +1369,117 @@ module mkDM_System_Bus(CLK, endcase assign rg_sbcs_sberror$EN = WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 || - master_xactor_crg_wr_resp_full && - master_xactor_rg_wr_resp[1:0] != 2'b0 || + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_rl_sb_write_response && + master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0 || EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d326 || EN_reset ; // register rg_sbcs_sbreadonaddr assign rg_sbcs_sbreadonaddr$D_IN = !EN_reset && write_dm_word[20] ; assign rg_sbcs_sbreadonaddr$EN = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 || EN_reset ; // register rg_sbcs_sbreadondata assign rg_sbcs_sbreadondata$D_IN = !EN_reset && write_dm_word[15] ; assign rg_sbcs_sbreadondata$EN = EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 || EN_reset ; // register rg_sbdata0 always@(EN_reset or WILL_FIRE_RL_rl_sb_read_finish or - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 or + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 or MUX_rg_sbdata0$write_1__SEL_3 or write_dm_word) case (1'b1) EN_reset: rg_sbdata0$D_IN = 32'd0; WILL_FIRE_RL_rl_sb_read_finish: rg_sbdata0$D_IN = - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79[31:0]; + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129[31:0]; MUX_rg_sbdata0$write_1__SEL_3: rg_sbdata0$D_IN = write_dm_word; default: rg_sbdata0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase assign rg_sbdata0$EN = EN_write && - write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d323 || + write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376 || WILL_FIRE_RL_rl_sb_read_finish || EN_reset ; // remaining internal signals - assign IF_rg_sbcs_sbreadonaddr_23_THEN_IF_rg_sbcs_sba_ETC___d307 = + assign IF_rg_sbcs_sbreadonaddr_74_THEN_IF_rg_sbcs_sba_ETC___d360 = rg_sbcs_sbreadonaddr ? (rg_sbcs_sbautoincrement ? - addr64310_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2[31:0] : + addr64393_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2[31:0] : write_dm_word) : write_dm_word ; - assign _theResult___fst__h4987 = word64__h4931 << shift_bits__h4934 ; - assign addr64310_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2 = - addr64__h4310 + - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ; - assign addr64__h4310 = { rg_sbaddress1, write_dm_word } ; - assign result__h1836 = { 56'd0, master_xactor_rg_rd_data[10:3] } ; - assign result__h1866 = { 56'd0, master_xactor_rg_rd_data[18:11] } ; - assign result__h1893 = { 56'd0, master_xactor_rg_rd_data[26:19] } ; - assign result__h1920 = { 56'd0, master_xactor_rg_rd_data[34:27] } ; - assign result__h1947 = { 56'd0, master_xactor_rg_rd_data[42:35] } ; - assign result__h1974 = { 56'd0, master_xactor_rg_rd_data[50:43] } ; - assign result__h2001 = { 56'd0, master_xactor_rg_rd_data[58:51] } ; - assign result__h2028 = { 56'd0, master_xactor_rg_rd_data[66:59] } ; - assign result__h2073 = { 48'd0, master_xactor_rg_rd_data[18:3] } ; - assign result__h2100 = { 48'd0, master_xactor_rg_rd_data[34:19] } ; - assign result__h2127 = { 48'd0, master_xactor_rg_rd_data[50:35] } ; - assign result__h2154 = { 48'd0, master_xactor_rg_rd_data[66:51] } ; - assign result__h2195 = { 32'd0, master_xactor_rg_rd_data[34:3] } ; - assign result__h2222 = { 32'd0, master_xactor_rg_rd_data[66:35] } ; - assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d109 = + assign _theResult___fst__h7087 = word64__h7032 << shift_bits__h7035 ; + assign addr64393_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_TH_ETC__q2 = + addr64__h6393 + + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 ; + assign addr64__h6393 = { rg_sbaddress1, write_dm_word } ; + assign master_xactor_shim_arff_rvport1__read_BITS_96_ETC__q5 = + master_xactor_shim_arff_rv$port1__read[96:0] ; + assign master_xactor_shim_awff_rvport1__read_BITS_96_ETC__q3 = + master_xactor_shim_awff_rv$port1__read[96:0] ; + assign master_xactor_shim_wff_rvport1__read_BITS_72__ETC__q4 = + master_xactor_shim_wff_rv$port1__read[72:0] ; + assign result__h3808 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[10:3] } ; + assign result__h3838 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[18:11] } ; + assign result__h3865 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[26:19] } ; + assign result__h3892 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[34:27] } ; + assign result__h3919 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[42:35] } ; + assign result__h3946 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[50:43] } ; + assign result__h3973 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[58:51] } ; + assign result__h4000 = + { 56'd0, master_xactor_shim_rff_rv$port1__read[66:59] } ; + assign result__h4045 = + { 48'd0, master_xactor_shim_rff_rv$port1__read[18:3] } ; + assign result__h4072 = + { 48'd0, master_xactor_shim_rff_rv$port1__read[34:19] } ; + assign result__h4099 = + { 48'd0, master_xactor_shim_rff_rv$port1__read[50:35] } ; + assign result__h4126 = + { 48'd0, master_xactor_shim_rff_rv$port1__read[66:51] } ; + assign result__h4167 = + { 32'd0, master_xactor_shim_rff_rv$port1__read[34:3] } ; + assign result__h4194 = + { 32'd0, master_xactor_shim_rff_rv$port1__read[66:35] } ; + assign rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d146 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && - rg_sbcs_sbreadondata ; - assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d313 = + rg_sbcs_sbautoincrement ; + assign rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d160 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && - rg_sbcs_sbreadonaddr ; - assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 = + rg_sbcs_sbreadondata ; + assign rg_sb_state_7_EQ_0_38_AND_NOT_rg_sbcs_sbbusyer_ETC___d366 = rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 && - rg_sbcs_sbautoincrement ; - assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 = + rg_sbcs_sbreadonaddr ; + assign rg_sbcs_sberror_9_EQ_0_0_AND_rg_sbcs_sbreadona_ETC___d344 = rg_sbcs_sberror == 3'd0 && (rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement || write_dm_addr != 7'h39) ; - assign sbaddress228_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q3 = - sbaddress__h1228 + - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ; - assign sbaddress__h1228 = { rg_sbaddress1, rg_sbaddress0 } ; - assign shift_bits__h4934 = { rg_sbaddress0[2:0], 3'b0 } ; - assign strobe64__h4986 = 8'b00000001 << rg_sbaddress0[2:0] ; - assign strobe64__h4989 = 8'b00000011 << rg_sbaddress0[2:0] ; - assign strobe64__h4992 = 8'b00001111 << rg_sbaddress0[2:0] ; - assign v__h2727 = + assign sbaddress099_PLUS_IF_rg_sbcs_sbaccess_8_EQ_0_9_ETC__q6 = + sbaddress__h3099 + + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 ; + assign sbaddress__h3099 = { rg_sbaddress1, rg_sbaddress0 } ; + assign shift_bits__h7035 = { rg_sbaddress0[2:0], 3'b0 } ; + assign strobe64__h7085 = 8'b00000001 << rg_sbaddress0[2:0] ; + assign strobe64__h7089 = 8'b00000011 << rg_sbaddress0[2:0] ; + assign strobe64__h7093 = 8'b00001111 << rg_sbaddress0[2:0] ; + assign v__h4783 = { 9'd64, rg_sbcs_sbbusyerror, rg_sb_state != 2'd0, @@ -1023,172 +1489,173 @@ module mkDM_System_Bus(CLK, rg_sbcs_sbreadondata, rg_sbcs_sberror, 12'd1031 } ; - assign v__h2861 = + assign v__h4917 = (rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0) ? 32'd0 : rg_sbdata0 ; - assign word64__h4931 = { 32'd0, write_dm_word } ; - assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 = + assign word64__h7032 = { 32'd0, write_dm_word } ; + assign write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) && write_dm_word[19:17] != 3'd4 && write_dm_word[19:17] != 3'd3 ; - assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 = - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 || + assign write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d318 = + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d309 || (write_dm_addr == 7'h39 || write_dm_addr == 7'h3A || write_dm_addr == 7'h3C) && rg_sb_state != 2'd0 ; - assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271 = + assign write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d324 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && rg_sbcs_sbbusyerror && !write_dm_word[22] ; - assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 = + assign write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d326 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) ; - assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278 = + assign write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d331 = write_dm_addr == 7'h38 && (rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) && (!rg_sbcs_sbbusyerror || write_dm_word[22]) && (write_dm_word[19:17] == 3'd4 || write_dm_word[19:17] == 3'd3) ; - assign write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d323 = + assign write_dm_addr_EQ_0x3C_14_AND_rg_sb_state_7_EQ__ETC___d376 = write_dm_addr == 7'h3C && rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror && rg_sbcs_sberror == 3'd0 ; always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: x__h3263 = rg_sbcs_sbaccess; - default: x__h3263 = 3'b011; + 3'd0, 3'd1, 3'd2: axi4_size_val__h5371 = rg_sbcs_sbaccess; + default: axi4_size_val__h5371 = 3'b011; endcase end always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2, 3'd3: x__h4949 = rg_sbcs_sbaccess; - default: x__h4949 = 3'b111; + 3'd0, 3'd1, 3'd2, 3'd3: + _theResult___snd_snd_val__h7102 = rg_sbcs_sbaccess; + default: _theResult___snd_snd_val__h7102 = 3'b111; endcase end always@(rg_sbcs_sbaccess or - strobe64__h4986 or strobe64__h4989 or strobe64__h4992) + strobe64__h7085 or strobe64__h7089 or strobe64__h7093) begin case (rg_sbcs_sbaccess) - 3'd0: wrd_wstrb__h5078 = strobe64__h4986; - 3'd1: wrd_wstrb__h5078 = strobe64__h4989; - 3'd2: wrd_wstrb__h5078 = strobe64__h4992; - 3'd3: wrd_wstrb__h5078 = 8'b11111111; - default: wrd_wstrb__h5078 = 8'd0; + 3'd0: wrd_wstrb__h7217 = strobe64__h7085; + 3'd1: wrd_wstrb__h7217 = strobe64__h7089; + 3'd2: wrd_wstrb__h7217 = strobe64__h7093; + 3'd3: wrd_wstrb__h7217 = 8'b11111111; + default: wrd_wstrb__h7217 = 8'd0; endcase end - always@(rg_sbcs_sbaccess or word64__h4931 or _theResult___fst__h4987) + always@(rg_sbcs_sbaccess or word64__h7032 or _theResult___fst__h7087) begin case (rg_sbcs_sbaccess) - 3'd0, 3'd1, 3'd2: wrd_wdata__h5077 = _theResult___fst__h4987; - default: wrd_wdata__h5077 = word64__h4931; + 3'd0, 3'd1, 3'd2: wrd_wdata__h7216 = _theResult___fst__h7087; + default: wrd_wdata__h7216 = word64__h7032; endcase end always@(rg_sbcs_sbaccess) begin case (rg_sbcs_sbaccess) - 3'd0: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd1; - 3'd1: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd2; - 3'd2: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd4; - 3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd8; - default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = + 3'd0: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 = 64'd1; + 3'd1: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 = 64'd2; + 3'd2: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 = 64'd4; + 3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 = 64'd8; + default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d154 = 64'd16; endcase end always@(rg_sbaddress_reading or - result__h1836 or - result__h1866 or - result__h1893 or - result__h1920 or - result__h1947 or result__h1974 or result__h2001 or result__h2028) + result__h3808 or + result__h3838 or + result__h3865 or + result__h3892 or + result__h3919 or result__h3946 or result__h3973 or result__h4000) begin case (rg_sbaddress_reading[2:0]) 3'h0: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1836; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3808; 3'h1: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1866; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3838; 3'h2: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1893; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3865; 3'h3: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1920; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3892; 3'h4: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1947; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3919; 3'h5: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h1974; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3946; 3'h6: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h2001; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h3973; 3'h7: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 = - result__h2028; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 = + result__h4000; endcase end always@(rg_sbaddress_reading or - result__h2073 or result__h2100 or result__h2127 or result__h2154) + result__h4045 or result__h4072 or result__h4099 or result__h4126) begin case (rg_sbaddress_reading[2:0]) 3'h0: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2073; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 = + result__h4045; 3'h2: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2100; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 = + result__h4072; 3'h4: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2127; + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 = + result__h4099; 3'h6: - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = - result__h2154; - default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 = + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 = + result__h4126; + default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 = 64'd0; endcase end - always@(rg_sbaddress_reading or result__h2195 or result__h2222) + always@(rg_sbaddress_reading or result__h4167 or result__h4194) begin case (rg_sbaddress_reading[2:0]) 3'h0: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = - result__h2195; + result__h4167; 3'h4: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = - result__h2222; + result__h4194; default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = 64'd0; endcase end always@(rg_sbcs_sbaccess or - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 or - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 or + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103 or + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116 or CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 or - rg_sbaddress_reading or master_xactor_rg_rd_data) + rg_sbaddress_reading or master_xactor_shim_rff_rv$port1__read) begin case (rg_sbcs_sbaccess) 3'd0: - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53; + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 = + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d103; 3'd1: - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = - IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66; + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 = + IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d116; 3'd2: - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 = CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1; 3'd3: - IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = + IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 = (rg_sbaddress_reading[2:0] == 3'h0) ? - master_xactor_rg_rd_data[66:3] : + master_xactor_shim_rff_rv$port1__read[66:3] : 64'd0; - default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 = + default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d129 = 64'd0; endcase end @@ -1199,51 +1666,44 @@ module mkDM_System_Bus(CLK, begin if (RST_N == `BSV_RESET_VALUE) begin - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0; - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0; + master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 7'd42; + master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 72'h2AAAAAAAAAAAAAAAAA; + master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0; rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY 32'd0; end else begin - if (master_xactor_crg_rd_addr_full$EN) - master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_addr_full$D_IN; - if (master_xactor_crg_rd_data_full$EN) - master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_rd_data_full$D_IN; - if (master_xactor_crg_wr_addr_full$EN) - master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_addr_full$D_IN; - if (master_xactor_crg_wr_data_full$EN) - master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_data_full$D_IN; - if (master_xactor_crg_wr_resp_full$EN) - master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY - master_xactor_crg_wr_resp_full$D_IN; + if (master_xactor_clearing$EN) + master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + master_xactor_clearing$D_IN; + if (master_xactor_shim_arff_rv$EN) + master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_arff_rv$D_IN; + if (master_xactor_shim_awff_rv$EN) + master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_awff_rv$D_IN; + if (master_xactor_shim_bff_rv$EN) + master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_bff_rv$D_IN; + if (master_xactor_shim_rff_rv$EN) + master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_rff_rv$D_IN; + if (master_xactor_shim_wff_rv$EN) + master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + master_xactor_shim_wff_rv$D_IN; if (rg_sbaddress0$EN) rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress0$D_IN; if (rg_sbaddress1$EN) rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress1$D_IN; end - if (master_xactor_rg_rd_addr$EN) - master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_addr$D_IN; - if (master_xactor_rg_rd_data$EN) - master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_rd_data$D_IN; - if (master_xactor_rg_wr_addr$EN) - master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_addr$D_IN; - if (master_xactor_rg_wr_data$EN) - master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_data$D_IN; - if (master_xactor_rg_wr_resp$EN) - master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY - master_xactor_rg_wr_resp$D_IN; if (rg_sb_state$EN) rg_sb_state <= `BSV_ASSIGNMENT_DELAY rg_sb_state$D_IN; if (rg_sbaddress_reading$EN) rg_sbaddress_reading <= `BSV_ASSIGNMENT_DELAY rg_sbaddress_reading$D_IN; @@ -1268,16 +1728,12 @@ module mkDM_System_Bus(CLK, `else // not BSV_NO_INITIAL_BLOCKS initial begin - master_xactor_crg_rd_addr_full = 1'h0; - master_xactor_crg_rd_data_full = 1'h0; - master_xactor_crg_wr_addr_full = 1'h0; - master_xactor_crg_wr_data_full = 1'h0; - master_xactor_crg_wr_resp_full = 1'h0; - master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA; - master_xactor_rg_wr_resp = 6'h2A; + master_xactor_clearing = 1'h0; + master_xactor_shim_arff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_awff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + master_xactor_shim_bff_rv = 7'h2A; + master_xactor_shim_rff_rv = 72'hAAAAAAAAAAAAAAAAAA; + master_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; rg_sb_state = 2'h2; rg_sbaddress0 = 32'hAAAAAAAA; rg_sbaddress1 = 32'hAAAAAAAA; @@ -1428,6 +1884,12 @@ module mkDM_System_Bus(CLK, av_read_dm_addr != 7'h3A && av_read_dm_addr != 7'h3C) $write("] not supported", "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 && write_dm_word[14:12] == 3'd0) @@ -1443,24 +1905,24 @@ module mkDM_System_Bus(CLK, $display(" Must be cleared to re-enable system bus access."); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d324) $display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d324) $display(" ERROR: existing sbbusyerror (%0d) is not being cleared.", rg_sbcs_sbbusyerror); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d324) $display(" Must be cleared to re-enable system bus access."); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d331) $display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d331) $write(" ERROR: sbaccess "); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr == 7'h38 && @@ -1476,7 +1938,7 @@ module mkDM_System_Bus(CLK, $write("DM_SBACCESS_128_BIT"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && - write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278) + write_dm_addr_EQ_0x38_94_AND_rg_sbcs_sberror_9_ETC___d331) $write(" not supported", "\n"); if (RST_N != `BSV_RESET_VALUE) if (EN_write && write_dm_addr != 7'h38 && @@ -1617,62 +2079,81 @@ module mkDM_System_Bus(CLK, $write("] <= 0x%08h; addr not supported", write_dm_word, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $display("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write(" rdr = "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("AXI4_Rd_Data { ", "rid: "); + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) + $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[70:67]); + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) + $write("'h%h", master_xactor_shim_rff_rv$port1__read[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[66:3]); + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) + $write("'h%h", master_xactor_shim_rff_rv$port1__read[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) - $write("'h%h", master_xactor_rg_rd_data[2:1]); + master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_sb_read_finish && + master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_sb_read_finish && + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 && - master_xactor_rg_rd_data[0]) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + master_xactor_shim_rff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0 && - !master_xactor_rg_rd_data[0]) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + !master_xactor_shim_rff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_sb_read_finish && - master_xactor_rg_rd_data[2:1] != 2'b0) + master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0) $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_master_xactor_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); end // synopsys translate_on endmodule // mkDM_System_Bus diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkDebug_Module.v b/src_SSITH_P1/xilinx_ip/hdl/mkDebug_Module.v index 1688e82e..725db2d0 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkDebug_Module.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:34 BST 2019 // // // Ports: @@ -27,33 +27,33 @@ // ndm_reset_client_request_get O 1 reg // RDY_ndm_reset_client_request_get O 1 reg // RDY_ndm_reset_client_response_put O 1 reg +// master_awid O 4 +// master_awaddr O 64 +// master_awlen O 8 +// master_awsize O 3 +// master_awburst O 2 +// master_awlock O 1 +// master_awcache O 4 +// master_awprot O 3 +// master_awqos O 4 +// master_awregion O 4 // master_awvalid O 1 -// master_awid O 4 reg -// master_awaddr O 64 reg -// master_awlen O 8 reg -// master_awsize O 3 reg -// master_awburst O 2 reg -// master_awlock O 1 reg -// master_awcache O 4 reg -// master_awprot O 3 reg -// master_awqos O 4 reg -// master_awregion O 4 reg +// master_wdata O 64 +// master_wstrb O 8 +// master_wlast O 1 // master_wvalid O 1 -// master_wdata O 64 reg -// master_wstrb O 8 reg -// master_wlast O 1 reg -// master_bready O 1 const +// master_bready O 1 +// master_arid O 4 +// master_araddr O 64 +// master_arlen O 8 +// master_arsize O 3 +// master_arburst O 2 +// master_arlock O 1 +// master_arcache O 4 +// master_arprot O 3 +// master_arqos O 4 +// master_arregion O 4 // master_arvalid O 1 -// master_arid O 4 reg -// master_araddr O 64 reg -// master_arlen O 8 reg -// master_arsize O 3 reg -// master_arburst O 2 reg -// master_arlock O 1 reg -// master_arcache O 4 reg -// master_arprot O 3 reg -// master_arqos O 4 reg -// master_arregion O 4 reg // master_rready O 1 // CLK I 1 clock // RST_N I 1 reset @@ -67,15 +67,13 @@ // ndm_reset_client_response_put I 1 reg // master_awready I 1 // master_wready I 1 -// master_bvalid I 1 -// master_bid I 4 reg -// master_bresp I 2 reg +// master_bid I 4 +// master_bresp I 2 // master_arready I 1 -// master_rvalid I 1 -// master_rid I 4 reg -// master_rdata I 64 reg -// master_rresp I 2 reg -// master_rlast I 1 reg +// master_rid I 4 +// master_rdata I 64 +// master_rresp I 2 +// master_rlast I 1 // EN_dmi_read_addr I 1 // EN_dmi_write I 1 // EN_hart0_reset_client_response_put I 1 @@ -83,6 +81,8 @@ // EN_hart0_gpr_mem_client_response_put I 1 // EN_hart0_csr_mem_client_response_put I 1 // EN_ndm_reset_client_response_put I 1 +// master_bvalid I 1 +// master_rvalid I 1 // EN_dmi_read_data I 1 // EN_hart0_reset_client_request_get I 1 // EN_hart0_client_run_halt_request_get I 1 @@ -92,14 +92,264 @@ // EN_ndm_reset_client_request_get I 1 // // Combinational paths from inputs to outputs: +// (dmi_read_addr_dm_addr, EN_dmi_read_addr) -> RDY_dmi_read_data // (dmi_read_addr_dm_addr, -// master_arready, -// EN_dmi_read_addr) -> RDY_dmi_read_data +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arid // (dmi_read_addr_dm_addr, -// master_arready, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, // EN_dmi_read_addr, -// EN_dmi_read_data) -> dmi_read_data -// (master_awready, master_wready, master_arready) -> RDY_dmi_write +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_araddr +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arlen +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arsize +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arburst +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arlock +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arcache +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arprot +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arqos +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arregion +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_aruser +// (dmi_read_addr_dm_addr, +// dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_read_addr, +// EN_dmi_write, +// master_rvalid, +// EN_dmi_read_data) -> master_arvalid +// (dmi_read_addr_dm_addr, EN_dmi_read_addr, EN_dmi_read_data) -> dmi_read_data +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awid +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awaddr +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awlen +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awsize +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awburst +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awlock +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awcache +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awprot +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awqos +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awregion +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awuser +// (dmi_write_dm_addr, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_awvalid +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_wdata +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_wstrb +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_wlast +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_wuser +// (dmi_write_dm_addr, +// dmi_write_dm_word, +// master_rid, +// master_rdata, +// master_rresp, +// master_rlast, +// EN_dmi_write, +// master_rvalid) -> master_wvalid // // @@ -176,8 +426,6 @@ module mkDebug_Module(CLK, EN_ndm_reset_client_response_put, RDY_ndm_reset_client_response_put, - master_awvalid, - master_awid, master_awaddr, @@ -198,9 +446,9 @@ module mkDebug_Module(CLK, master_awregion, - master_awready, + master_awvalid, - master_wvalid, + master_awready, master_wdata, @@ -208,16 +456,16 @@ module mkDebug_Module(CLK, master_wlast, + master_wvalid, + master_wready, - master_bvalid, master_bid, master_bresp, + master_bvalid, master_bready, - master_arvalid, - master_arid, master_araddr, @@ -238,13 +486,15 @@ module mkDebug_Module(CLK, master_arregion, + master_arvalid, + master_arready, - master_rvalid, master_rid, master_rdata, master_rresp, master_rlast, + master_rvalid, master_rready); input CLK; @@ -321,115 +571,115 @@ module mkDebug_Module(CLK, input EN_ndm_reset_client_response_put; output RDY_ndm_reset_client_response_put; - // value method master_m_awvalid - output master_awvalid; - - // value method master_m_awid + // value method master_aw_awid output [3 : 0] master_awid; - // value method master_m_awaddr + // value method master_aw_awaddr output [63 : 0] master_awaddr; - // value method master_m_awlen + // value method master_aw_awlen output [7 : 0] master_awlen; - // value method master_m_awsize + // value method master_aw_awsize output [2 : 0] master_awsize; - // value method master_m_awburst + // value method master_aw_awburst output [1 : 0] master_awburst; - // value method master_m_awlock + // value method master_aw_awlock output master_awlock; - // value method master_m_awcache + // value method master_aw_awcache output [3 : 0] master_awcache; - // value method master_m_awprot + // value method master_aw_awprot output [2 : 0] master_awprot; - // value method master_m_awqos + // value method master_aw_awqos output [3 : 0] master_awqos; - // value method master_m_awregion + // value method master_aw_awregion output [3 : 0] master_awregion; - // value method master_m_awuser + // value method master_aw_awuser - // action method master_m_awready - input master_awready; + // value method master_aw_awvalid + output master_awvalid; - // value method master_m_wvalid - output master_wvalid; + // action method master_aw_awready + input master_awready; - // value method master_m_wdata + // value method master_w_wdata output [63 : 0] master_wdata; - // value method master_m_wstrb + // value method master_w_wstrb output [7 : 0] master_wstrb; - // value method master_m_wlast + // value method master_w_wlast output master_wlast; - // value method master_m_wuser + // value method master_w_wuser + + // value method master_w_wvalid + output master_wvalid; - // action method master_m_wready + // action method master_w_wready input master_wready; - // action method master_m_bvalid - input master_bvalid; + // action method master_b_bflit input [3 : 0] master_bid; input [1 : 0] master_bresp; + input master_bvalid; - // value method master_m_bready + // value method master_b_bready output master_bready; - // value method master_m_arvalid - output master_arvalid; - - // value method master_m_arid + // value method master_ar_arid output [3 : 0] master_arid; - // value method master_m_araddr + // value method master_ar_araddr output [63 : 0] master_araddr; - // value method master_m_arlen + // value method master_ar_arlen output [7 : 0] master_arlen; - // value method master_m_arsize + // value method master_ar_arsize output [2 : 0] master_arsize; - // value method master_m_arburst + // value method master_ar_arburst output [1 : 0] master_arburst; - // value method master_m_arlock + // value method master_ar_arlock output master_arlock; - // value method master_m_arcache + // value method master_ar_arcache output [3 : 0] master_arcache; - // value method master_m_arprot + // value method master_ar_arprot output [2 : 0] master_arprot; - // value method master_m_arqos + // value method master_ar_arqos output [3 : 0] master_arqos; - // value method master_m_arregion + // value method master_ar_arregion output [3 : 0] master_arregion; - // value method master_m_aruser + // value method master_ar_aruser - // action method master_m_arready + // value method master_ar_arvalid + output master_arvalid; + + // action method master_ar_arready input master_arready; - // action method master_m_rvalid - input master_rvalid; + // action method master_r_rflit input [3 : 0] master_rid; input [63 : 0] master_rdata; input [1 : 0] master_rresp; input master_rlast; + input master_rvalid; - // value method master_m_rready + // value method master_r_rready output master_rready; // signals for module outputs @@ -598,11 +848,11 @@ module mkDebug_Module(CLK, CAN_FIRE_hart0_gpr_mem_client_response_put, CAN_FIRE_hart0_reset_client_request_get, CAN_FIRE_hart0_reset_client_response_put, - CAN_FIRE_master_m_arready, - CAN_FIRE_master_m_awready, - CAN_FIRE_master_m_bvalid, - CAN_FIRE_master_m_rvalid, - CAN_FIRE_master_m_wready, + CAN_FIRE_master_ar_arready, + CAN_FIRE_master_aw_awready, + CAN_FIRE_master_b_bflit, + CAN_FIRE_master_r_rflit, + CAN_FIRE_master_w_wready, CAN_FIRE_ndm_reset_client_request_get, CAN_FIRE_ndm_reset_client_response_put, WILL_FIRE_RL_rl_reset, @@ -618,18 +868,18 @@ module mkDebug_Module(CLK, WILL_FIRE_hart0_gpr_mem_client_response_put, WILL_FIRE_hart0_reset_client_request_get, WILL_FIRE_hart0_reset_client_response_put, - WILL_FIRE_master_m_arready, - WILL_FIRE_master_m_awready, - WILL_FIRE_master_m_bvalid, - WILL_FIRE_master_m_rvalid, - WILL_FIRE_master_m_wready, + WILL_FIRE_master_ar_arready, + WILL_FIRE_master_aw_awready, + WILL_FIRE_master_b_bflit, + WILL_FIRE_master_r_rflit, + WILL_FIRE_master_w_wready, WILL_FIRE_ndm_reset_client_request_get, WILL_FIRE_ndm_reset_client_response_put; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h894; - reg [31 : 0] v__h888; + reg [31 : 0] v__h878; + reg [31 : 0] v__h872; // synopsys translate_on // action method dmi_read_addr @@ -804,108 +1054,108 @@ module mkDebug_Module(CLK, assign WILL_FIRE_ndm_reset_client_response_put = EN_ndm_reset_client_response_put ; - // value method master_m_awvalid - assign master_awvalid = dm_system_bus$master_awvalid ; - - // value method master_m_awid + // value method master_aw_awid assign master_awid = dm_system_bus$master_awid ; - // value method master_m_awaddr + // value method master_aw_awaddr assign master_awaddr = dm_system_bus$master_awaddr ; - // value method master_m_awlen + // value method master_aw_awlen assign master_awlen = dm_system_bus$master_awlen ; - // value method master_m_awsize + // value method master_aw_awsize assign master_awsize = dm_system_bus$master_awsize ; - // value method master_m_awburst + // value method master_aw_awburst assign master_awburst = dm_system_bus$master_awburst ; - // value method master_m_awlock + // value method master_aw_awlock assign master_awlock = dm_system_bus$master_awlock ; - // value method master_m_awcache + // value method master_aw_awcache assign master_awcache = dm_system_bus$master_awcache ; - // value method master_m_awprot + // value method master_aw_awprot assign master_awprot = dm_system_bus$master_awprot ; - // value method master_m_awqos + // value method master_aw_awqos assign master_awqos = dm_system_bus$master_awqos ; - // value method master_m_awregion + // value method master_aw_awregion assign master_awregion = dm_system_bus$master_awregion ; - // action method master_m_awready - assign CAN_FIRE_master_m_awready = 1'd1 ; - assign WILL_FIRE_master_m_awready = 1'd1 ; + // value method master_aw_awvalid + assign master_awvalid = dm_system_bus$master_awvalid ; - // value method master_m_wvalid - assign master_wvalid = dm_system_bus$master_wvalid ; + // action method master_aw_awready + assign CAN_FIRE_master_aw_awready = 1'd1 ; + assign WILL_FIRE_master_aw_awready = 1'd1 ; - // value method master_m_wdata + // value method master_w_wdata assign master_wdata = dm_system_bus$master_wdata ; - // value method master_m_wstrb + // value method master_w_wstrb assign master_wstrb = dm_system_bus$master_wstrb ; - // value method master_m_wlast + // value method master_w_wlast assign master_wlast = dm_system_bus$master_wlast ; - // action method master_m_wready - assign CAN_FIRE_master_m_wready = 1'd1 ; - assign WILL_FIRE_master_m_wready = 1'd1 ; + // value method master_w_wvalid + assign master_wvalid = dm_system_bus$master_wvalid ; - // action method master_m_bvalid - assign CAN_FIRE_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_master_m_bvalid = 1'd1 ; + // action method master_w_wready + assign CAN_FIRE_master_w_wready = 1'd1 ; + assign WILL_FIRE_master_w_wready = 1'd1 ; - // value method master_m_bready - assign master_bready = dm_system_bus$master_bready ; + // action method master_b_bflit + assign CAN_FIRE_master_b_bflit = 1'd1 ; + assign WILL_FIRE_master_b_bflit = master_bvalid ; - // value method master_m_arvalid - assign master_arvalid = dm_system_bus$master_arvalid ; + // value method master_b_bready + assign master_bready = dm_system_bus$master_bready ; - // value method master_m_arid + // value method master_ar_arid assign master_arid = dm_system_bus$master_arid ; - // value method master_m_araddr + // value method master_ar_araddr assign master_araddr = dm_system_bus$master_araddr ; - // value method master_m_arlen + // value method master_ar_arlen assign master_arlen = dm_system_bus$master_arlen ; - // value method master_m_arsize + // value method master_ar_arsize assign master_arsize = dm_system_bus$master_arsize ; - // value method master_m_arburst + // value method master_ar_arburst assign master_arburst = dm_system_bus$master_arburst ; - // value method master_m_arlock + // value method master_ar_arlock assign master_arlock = dm_system_bus$master_arlock ; - // value method master_m_arcache + // value method master_ar_arcache assign master_arcache = dm_system_bus$master_arcache ; - // value method master_m_arprot + // value method master_ar_arprot assign master_arprot = dm_system_bus$master_arprot ; - // value method master_m_arqos + // value method master_ar_arqos assign master_arqos = dm_system_bus$master_arqos ; - // value method master_m_arregion + // value method master_ar_arregion assign master_arregion = dm_system_bus$master_arregion ; - // action method master_m_arready - assign CAN_FIRE_master_m_arready = 1'd1 ; - assign WILL_FIRE_master_m_arready = 1'd1 ; + // value method master_ar_arvalid + assign master_arvalid = dm_system_bus$master_arvalid ; + + // action method master_ar_arready + assign CAN_FIRE_master_ar_arready = 1'd1 ; + assign WILL_FIRE_master_ar_arready = 1'd1 ; - // action method master_m_rvalid - assign CAN_FIRE_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_master_m_rvalid = 1'd1 ; + // action method master_r_rflit + assign CAN_FIRE_master_r_rflit = 1'd1 ; + assign WILL_FIRE_master_r_rflit = master_rvalid ; - // value method master_m_rready + // value method master_r_rready assign master_rready = dm_system_bus$master_rready ; // submodule dm_abstract_commands @@ -979,23 +1229,22 @@ module mkDebug_Module(CLK, .master_awready(dm_system_bus$master_awready), .master_bid(dm_system_bus$master_bid), .master_bresp(dm_system_bus$master_bresp), - .master_bvalid(dm_system_bus$master_bvalid), .master_rdata(dm_system_bus$master_rdata), .master_rid(dm_system_bus$master_rid), .master_rlast(dm_system_bus$master_rlast), .master_rresp(dm_system_bus$master_rresp), - .master_rvalid(dm_system_bus$master_rvalid), .master_wready(dm_system_bus$master_wready), .write_dm_addr(dm_system_bus$write_dm_addr), .write_dm_word(dm_system_bus$write_dm_word), .EN_reset(dm_system_bus$EN_reset), .EN_av_read(dm_system_bus$EN_av_read), .EN_write(dm_system_bus$EN_write), + .master_bvalid(dm_system_bus$master_bvalid), + .master_rvalid(dm_system_bus$master_rvalid), .RDY_reset(), .av_read(dm_system_bus$av_read), .RDY_av_read(dm_system_bus$RDY_av_read), .RDY_write(dm_system_bus$RDY_write), - .master_awvalid(dm_system_bus$master_awvalid), .master_awid(dm_system_bus$master_awid), .master_awaddr(dm_system_bus$master_awaddr), .master_awlen(dm_system_bus$master_awlen), @@ -1006,12 +1255,12 @@ module mkDebug_Module(CLK, .master_awprot(dm_system_bus$master_awprot), .master_awqos(dm_system_bus$master_awqos), .master_awregion(dm_system_bus$master_awregion), - .master_wvalid(dm_system_bus$master_wvalid), + .master_awvalid(dm_system_bus$master_awvalid), .master_wdata(dm_system_bus$master_wdata), .master_wstrb(dm_system_bus$master_wstrb), .master_wlast(dm_system_bus$master_wlast), + .master_wvalid(dm_system_bus$master_wvalid), .master_bready(dm_system_bus$master_bready), - .master_arvalid(dm_system_bus$master_arvalid), .master_arid(dm_system_bus$master_arid), .master_araddr(dm_system_bus$master_araddr), .master_arlen(dm_system_bus$master_arlen), @@ -1022,6 +1271,7 @@ module mkDebug_Module(CLK, .master_arprot(dm_system_bus$master_arprot), .master_arqos(dm_system_bus$master_arqos), .master_arregion(dm_system_bus$master_arregion), + .master_arvalid(dm_system_bus$master_arvalid), .master_rready(dm_system_bus$master_rready)); // rule RL_rl_reset @@ -1150,12 +1400,10 @@ module mkDebug_Module(CLK, assign dm_system_bus$master_awready = master_awready ; assign dm_system_bus$master_bid = master_bid ; assign dm_system_bus$master_bresp = master_bresp ; - assign dm_system_bus$master_bvalid = master_bvalid ; assign dm_system_bus$master_rdata = master_rdata ; assign dm_system_bus$master_rid = master_rid ; assign dm_system_bus$master_rlast = master_rlast ; assign dm_system_bus$master_rresp = master_rresp ; - assign dm_system_bus$master_rvalid = master_rvalid ; assign dm_system_bus$master_wready = master_wready ; assign dm_system_bus$write_dm_addr = dmi_write_dm_addr ; assign dm_system_bus$write_dm_word = dmi_write_dm_word ; @@ -1179,6 +1427,8 @@ module mkDebug_Module(CLK, dmi_write_dm_addr == 7'h3D || dmi_write_dm_addr == 7'h3E || dmi_write_dm_addr == 7'h3F) ; + assign dm_system_bus$master_bvalid = master_bvalid ; + assign dm_system_bus$master_rvalid = master_rvalid ; // handling of inlined registers @@ -1214,12 +1464,12 @@ module mkDebug_Module(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset) begin - v__h894 = $stime; + v__h878 = $stime; #0; end - v__h888 = v__h894 / 32'd10; + v__h872 = v__h878 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h888); + if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h872); end // synopsys translate_on endmodule // mkDebug_Module diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkFabric_2x1.v b/src_SSITH_P1/xilinx_ip/hdl/mkFabric_2x1.v deleted file mode 100644 index f80761c3..00000000 --- a/src_SSITH_P1/xilinx_ip/hdl/mkFabric_2x1.v +++ /dev/null @@ -1,3189 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_reset O 1 -// RDY_set_verbosity O 1 const -// v_from_masters_0_awready O 1 reg -// v_from_masters_0_wready O 1 reg -// v_from_masters_0_bvalid O 1 reg -// v_from_masters_0_bid O 4 reg -// v_from_masters_0_bresp O 2 reg -// v_from_masters_0_arready O 1 reg -// v_from_masters_0_rvalid O 1 reg -// v_from_masters_0_rid O 4 reg -// v_from_masters_0_rdata O 64 reg -// v_from_masters_0_rresp O 2 reg -// v_from_masters_0_rlast O 1 reg -// v_from_masters_1_awready O 1 reg -// v_from_masters_1_wready O 1 reg -// v_from_masters_1_bvalid O 1 reg -// v_from_masters_1_bid O 4 reg -// v_from_masters_1_bresp O 2 reg -// v_from_masters_1_arready O 1 reg -// v_from_masters_1_rvalid O 1 reg -// v_from_masters_1_rid O 4 reg -// v_from_masters_1_rdata O 64 reg -// v_from_masters_1_rresp O 2 reg -// v_from_masters_1_rlast O 1 reg -// v_to_slaves_0_awvalid O 1 reg -// v_to_slaves_0_awid O 4 reg -// v_to_slaves_0_awaddr O 64 reg -// v_to_slaves_0_awlen O 8 reg -// v_to_slaves_0_awsize O 3 reg -// v_to_slaves_0_awburst O 2 reg -// v_to_slaves_0_awlock O 1 reg -// v_to_slaves_0_awcache O 4 reg -// v_to_slaves_0_awprot O 3 reg -// v_to_slaves_0_awqos O 4 reg -// v_to_slaves_0_awregion O 4 reg -// v_to_slaves_0_wvalid O 1 reg -// v_to_slaves_0_wid O 4 reg -// v_to_slaves_0_wdata O 64 reg -// v_to_slaves_0_wstrb O 8 reg -// v_to_slaves_0_wlast O 1 reg -// v_to_slaves_0_bready O 1 reg -// v_to_slaves_0_arvalid O 1 reg -// v_to_slaves_0_arid O 4 reg -// v_to_slaves_0_araddr O 64 reg -// v_to_slaves_0_arlen O 8 reg -// v_to_slaves_0_arsize O 3 reg -// v_to_slaves_0_arburst O 2 reg -// v_to_slaves_0_arlock O 1 reg -// v_to_slaves_0_arcache O 4 reg -// v_to_slaves_0_arprot O 3 reg -// v_to_slaves_0_arqos O 4 reg -// v_to_slaves_0_arregion O 4 reg -// v_to_slaves_0_rready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_verbosity_verbosity I 4 reg -// v_from_masters_0_awvalid I 1 -// v_from_masters_0_awid I 4 reg -// v_from_masters_0_awaddr I 64 reg -// v_from_masters_0_awlen I 8 reg -// v_from_masters_0_awsize I 3 reg -// v_from_masters_0_awburst I 2 reg -// v_from_masters_0_awlock I 1 reg -// v_from_masters_0_awcache I 4 reg -// v_from_masters_0_awprot I 3 reg -// v_from_masters_0_awqos I 4 reg -// v_from_masters_0_awregion I 4 reg -// v_from_masters_0_wvalid I 1 -// v_from_masters_0_wid I 4 reg -// v_from_masters_0_wdata I 64 reg -// v_from_masters_0_wstrb I 8 reg -// v_from_masters_0_wlast I 1 reg -// v_from_masters_0_bready I 1 -// v_from_masters_0_arvalid I 1 -// v_from_masters_0_arid I 4 reg -// v_from_masters_0_araddr I 64 reg -// v_from_masters_0_arlen I 8 reg -// v_from_masters_0_arsize I 3 reg -// v_from_masters_0_arburst I 2 reg -// v_from_masters_0_arlock I 1 reg -// v_from_masters_0_arcache I 4 reg -// v_from_masters_0_arprot I 3 reg -// v_from_masters_0_arqos I 4 reg -// v_from_masters_0_arregion I 4 reg -// v_from_masters_0_rready I 1 -// v_from_masters_1_awvalid I 1 -// v_from_masters_1_awid I 4 reg -// v_from_masters_1_awaddr I 64 reg -// v_from_masters_1_awlen I 8 reg -// v_from_masters_1_awsize I 3 reg -// v_from_masters_1_awburst I 2 reg -// v_from_masters_1_awlock I 1 reg -// v_from_masters_1_awcache I 4 reg -// v_from_masters_1_awprot I 3 reg -// v_from_masters_1_awqos I 4 reg -// v_from_masters_1_awregion I 4 reg -// v_from_masters_1_wvalid I 1 -// v_from_masters_1_wid I 4 reg -// v_from_masters_1_wdata I 64 reg -// v_from_masters_1_wstrb I 8 reg -// v_from_masters_1_wlast I 1 reg -// v_from_masters_1_bready I 1 -// v_from_masters_1_arvalid I 1 -// v_from_masters_1_arid I 4 reg -// v_from_masters_1_araddr I 64 reg -// v_from_masters_1_arlen I 8 reg -// v_from_masters_1_arsize I 3 reg -// v_from_masters_1_arburst I 2 reg -// v_from_masters_1_arlock I 1 reg -// v_from_masters_1_arcache I 4 reg -// v_from_masters_1_arprot I 3 reg -// v_from_masters_1_arqos I 4 reg -// v_from_masters_1_arregion I 4 reg -// v_from_masters_1_rready I 1 -// v_to_slaves_0_awready I 1 -// v_to_slaves_0_wready I 1 -// v_to_slaves_0_bvalid I 1 -// v_to_slaves_0_bid I 4 reg -// v_to_slaves_0_bresp I 2 reg -// v_to_slaves_0_arready I 1 -// v_to_slaves_0_rvalid I 1 -// v_to_slaves_0_rid I 4 reg -// v_to_slaves_0_rdata I 64 reg -// v_to_slaves_0_rresp I 2 reg -// v_to_slaves_0_rlast I 1 reg -// EN_reset I 1 -// EN_set_verbosity I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkFabric_2x1(CLK, - RST_N, - - EN_reset, - RDY_reset, - - set_verbosity_verbosity, - EN_set_verbosity, - RDY_set_verbosity, - - v_from_masters_0_awvalid, - v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion, - - v_from_masters_0_awready, - - v_from_masters_0_wvalid, - v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast, - - v_from_masters_0_wready, - - v_from_masters_0_bvalid, - - v_from_masters_0_bid, - - v_from_masters_0_bresp, - - v_from_masters_0_bready, - - v_from_masters_0_arvalid, - v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion, - - v_from_masters_0_arready, - - v_from_masters_0_rvalid, - - v_from_masters_0_rid, - - v_from_masters_0_rdata, - - v_from_masters_0_rresp, - - v_from_masters_0_rlast, - - v_from_masters_0_rready, - - v_from_masters_1_awvalid, - v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion, - - v_from_masters_1_awready, - - v_from_masters_1_wvalid, - v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast, - - v_from_masters_1_wready, - - v_from_masters_1_bvalid, - - v_from_masters_1_bid, - - v_from_masters_1_bresp, - - v_from_masters_1_bready, - - v_from_masters_1_arvalid, - v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion, - - v_from_masters_1_arready, - - v_from_masters_1_rvalid, - - v_from_masters_1_rid, - - v_from_masters_1_rdata, - - v_from_masters_1_rresp, - - v_from_masters_1_rlast, - - v_from_masters_1_rready, - - v_to_slaves_0_awvalid, - - v_to_slaves_0_awid, - - v_to_slaves_0_awaddr, - - v_to_slaves_0_awlen, - - v_to_slaves_0_awsize, - - v_to_slaves_0_awburst, - - v_to_slaves_0_awlock, - - v_to_slaves_0_awcache, - - v_to_slaves_0_awprot, - - v_to_slaves_0_awqos, - - v_to_slaves_0_awregion, - - v_to_slaves_0_awready, - - v_to_slaves_0_wvalid, - - v_to_slaves_0_wid, - - v_to_slaves_0_wdata, - - v_to_slaves_0_wstrb, - - v_to_slaves_0_wlast, - - v_to_slaves_0_wready, - - v_to_slaves_0_bvalid, - v_to_slaves_0_bid, - v_to_slaves_0_bresp, - - v_to_slaves_0_bready, - - v_to_slaves_0_arvalid, - - v_to_slaves_0_arid, - - v_to_slaves_0_araddr, - - v_to_slaves_0_arlen, - - v_to_slaves_0_arsize, - - v_to_slaves_0_arburst, - - v_to_slaves_0_arlock, - - v_to_slaves_0_arcache, - - v_to_slaves_0_arprot, - - v_to_slaves_0_arqos, - - v_to_slaves_0_arregion, - - v_to_slaves_0_arready, - - v_to_slaves_0_rvalid, - v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast, - - v_to_slaves_0_rready); - input CLK; - input RST_N; - - // action method reset - input EN_reset; - output RDY_reset; - - // action method set_verbosity - input [3 : 0] set_verbosity_verbosity; - input EN_set_verbosity; - output RDY_set_verbosity; - - // action method v_from_masters_0_m_awvalid - input v_from_masters_0_awvalid; - input [3 : 0] v_from_masters_0_awid; - input [63 : 0] v_from_masters_0_awaddr; - input [7 : 0] v_from_masters_0_awlen; - input [2 : 0] v_from_masters_0_awsize; - input [1 : 0] v_from_masters_0_awburst; - input v_from_masters_0_awlock; - input [3 : 0] v_from_masters_0_awcache; - input [2 : 0] v_from_masters_0_awprot; - input [3 : 0] v_from_masters_0_awqos; - input [3 : 0] v_from_masters_0_awregion; - - // value method v_from_masters_0_m_awready - output v_from_masters_0_awready; - - // action method v_from_masters_0_m_wvalid - input v_from_masters_0_wvalid; - input [3 : 0] v_from_masters_0_wid; - input [63 : 0] v_from_masters_0_wdata; - input [7 : 0] v_from_masters_0_wstrb; - input v_from_masters_0_wlast; - - // value method v_from_masters_0_m_wready - output v_from_masters_0_wready; - - // value method v_from_masters_0_m_bvalid - output v_from_masters_0_bvalid; - - // value method v_from_masters_0_m_bid - output [3 : 0] v_from_masters_0_bid; - - // value method v_from_masters_0_m_bresp - output [1 : 0] v_from_masters_0_bresp; - - // value method v_from_masters_0_m_buser - - // action method v_from_masters_0_m_bready - input v_from_masters_0_bready; - - // action method v_from_masters_0_m_arvalid - input v_from_masters_0_arvalid; - input [3 : 0] v_from_masters_0_arid; - input [63 : 0] v_from_masters_0_araddr; - input [7 : 0] v_from_masters_0_arlen; - input [2 : 0] v_from_masters_0_arsize; - input [1 : 0] v_from_masters_0_arburst; - input v_from_masters_0_arlock; - input [3 : 0] v_from_masters_0_arcache; - input [2 : 0] v_from_masters_0_arprot; - input [3 : 0] v_from_masters_0_arqos; - input [3 : 0] v_from_masters_0_arregion; - - // value method v_from_masters_0_m_arready - output v_from_masters_0_arready; - - // value method v_from_masters_0_m_rvalid - output v_from_masters_0_rvalid; - - // value method v_from_masters_0_m_rid - output [3 : 0] v_from_masters_0_rid; - - // value method v_from_masters_0_m_rdata - output [63 : 0] v_from_masters_0_rdata; - - // value method v_from_masters_0_m_rresp - output [1 : 0] v_from_masters_0_rresp; - - // value method v_from_masters_0_m_rlast - output v_from_masters_0_rlast; - - // value method v_from_masters_0_m_ruser - - // action method v_from_masters_0_m_rready - input v_from_masters_0_rready; - - // action method v_from_masters_1_m_awvalid - input v_from_masters_1_awvalid; - input [3 : 0] v_from_masters_1_awid; - input [63 : 0] v_from_masters_1_awaddr; - input [7 : 0] v_from_masters_1_awlen; - input [2 : 0] v_from_masters_1_awsize; - input [1 : 0] v_from_masters_1_awburst; - input v_from_masters_1_awlock; - input [3 : 0] v_from_masters_1_awcache; - input [2 : 0] v_from_masters_1_awprot; - input [3 : 0] v_from_masters_1_awqos; - input [3 : 0] v_from_masters_1_awregion; - - // value method v_from_masters_1_m_awready - output v_from_masters_1_awready; - - // action method v_from_masters_1_m_wvalid - input v_from_masters_1_wvalid; - input [3 : 0] v_from_masters_1_wid; - input [63 : 0] v_from_masters_1_wdata; - input [7 : 0] v_from_masters_1_wstrb; - input v_from_masters_1_wlast; - - // value method v_from_masters_1_m_wready - output v_from_masters_1_wready; - - // value method v_from_masters_1_m_bvalid - output v_from_masters_1_bvalid; - - // value method v_from_masters_1_m_bid - output [3 : 0] v_from_masters_1_bid; - - // value method v_from_masters_1_m_bresp - output [1 : 0] v_from_masters_1_bresp; - - // value method v_from_masters_1_m_buser - - // action method v_from_masters_1_m_bready - input v_from_masters_1_bready; - - // action method v_from_masters_1_m_arvalid - input v_from_masters_1_arvalid; - input [3 : 0] v_from_masters_1_arid; - input [63 : 0] v_from_masters_1_araddr; - input [7 : 0] v_from_masters_1_arlen; - input [2 : 0] v_from_masters_1_arsize; - input [1 : 0] v_from_masters_1_arburst; - input v_from_masters_1_arlock; - input [3 : 0] v_from_masters_1_arcache; - input [2 : 0] v_from_masters_1_arprot; - input [3 : 0] v_from_masters_1_arqos; - input [3 : 0] v_from_masters_1_arregion; - - // value method v_from_masters_1_m_arready - output v_from_masters_1_arready; - - // value method v_from_masters_1_m_rvalid - output v_from_masters_1_rvalid; - - // value method v_from_masters_1_m_rid - output [3 : 0] v_from_masters_1_rid; - - // value method v_from_masters_1_m_rdata - output [63 : 0] v_from_masters_1_rdata; - - // value method v_from_masters_1_m_rresp - output [1 : 0] v_from_masters_1_rresp; - - // value method v_from_masters_1_m_rlast - output v_from_masters_1_rlast; - - // value method v_from_masters_1_m_ruser - - // action method v_from_masters_1_m_rready - input v_from_masters_1_rready; - - // value method v_to_slaves_0_m_awvalid - output v_to_slaves_0_awvalid; - - // value method v_to_slaves_0_m_awid - output [3 : 0] v_to_slaves_0_awid; - - // value method v_to_slaves_0_m_awaddr - output [63 : 0] v_to_slaves_0_awaddr; - - // value method v_to_slaves_0_m_awlen - output [7 : 0] v_to_slaves_0_awlen; - - // value method v_to_slaves_0_m_awsize - output [2 : 0] v_to_slaves_0_awsize; - - // value method v_to_slaves_0_m_awburst - output [1 : 0] v_to_slaves_0_awburst; - - // value method v_to_slaves_0_m_awlock - output v_to_slaves_0_awlock; - - // value method v_to_slaves_0_m_awcache - output [3 : 0] v_to_slaves_0_awcache; - - // value method v_to_slaves_0_m_awprot - output [2 : 0] v_to_slaves_0_awprot; - - // value method v_to_slaves_0_m_awqos - output [3 : 0] v_to_slaves_0_awqos; - - // value method v_to_slaves_0_m_awregion - output [3 : 0] v_to_slaves_0_awregion; - - // value method v_to_slaves_0_m_awuser - - // action method v_to_slaves_0_m_awready - input v_to_slaves_0_awready; - - // value method v_to_slaves_0_m_wvalid - output v_to_slaves_0_wvalid; - - // value method v_to_slaves_0_m_wid - output [3 : 0] v_to_slaves_0_wid; - - // value method v_to_slaves_0_m_wdata - output [63 : 0] v_to_slaves_0_wdata; - - // value method v_to_slaves_0_m_wstrb - output [7 : 0] v_to_slaves_0_wstrb; - - // value method v_to_slaves_0_m_wlast - output v_to_slaves_0_wlast; - - // value method v_to_slaves_0_m_wuser - - // action method v_to_slaves_0_m_wready - input v_to_slaves_0_wready; - - // action method v_to_slaves_0_m_bvalid - input v_to_slaves_0_bvalid; - input [3 : 0] v_to_slaves_0_bid; - input [1 : 0] v_to_slaves_0_bresp; - - // value method v_to_slaves_0_m_bready - output v_to_slaves_0_bready; - - // value method v_to_slaves_0_m_arvalid - output v_to_slaves_0_arvalid; - - // value method v_to_slaves_0_m_arid - output [3 : 0] v_to_slaves_0_arid; - - // value method v_to_slaves_0_m_araddr - output [63 : 0] v_to_slaves_0_araddr; - - // value method v_to_slaves_0_m_arlen - output [7 : 0] v_to_slaves_0_arlen; - - // value method v_to_slaves_0_m_arsize - output [2 : 0] v_to_slaves_0_arsize; - - // value method v_to_slaves_0_m_arburst - output [1 : 0] v_to_slaves_0_arburst; - - // value method v_to_slaves_0_m_arlock - output v_to_slaves_0_arlock; - - // value method v_to_slaves_0_m_arcache - output [3 : 0] v_to_slaves_0_arcache; - - // value method v_to_slaves_0_m_arprot - output [2 : 0] v_to_slaves_0_arprot; - - // value method v_to_slaves_0_m_arqos - output [3 : 0] v_to_slaves_0_arqos; - - // value method v_to_slaves_0_m_arregion - output [3 : 0] v_to_slaves_0_arregion; - - // value method v_to_slaves_0_m_aruser - - // action method v_to_slaves_0_m_arready - input v_to_slaves_0_arready; - - // action method v_to_slaves_0_m_rvalid - input v_to_slaves_0_rvalid; - input [3 : 0] v_to_slaves_0_rid; - input [63 : 0] v_to_slaves_0_rdata; - input [1 : 0] v_to_slaves_0_rresp; - input v_to_slaves_0_rlast; - - // value method v_to_slaves_0_m_rready - output v_to_slaves_0_rready; - - // signals for module outputs - wire [63 : 0] v_from_masters_0_rdata, - v_from_masters_1_rdata, - v_to_slaves_0_araddr, - v_to_slaves_0_awaddr, - v_to_slaves_0_wdata; - wire [7 : 0] v_to_slaves_0_arlen, v_to_slaves_0_awlen, v_to_slaves_0_wstrb; - wire [3 : 0] v_from_masters_0_bid, - v_from_masters_0_rid, - v_from_masters_1_bid, - v_from_masters_1_rid, - v_to_slaves_0_arcache, - v_to_slaves_0_arid, - v_to_slaves_0_arqos, - v_to_slaves_0_arregion, - v_to_slaves_0_awcache, - v_to_slaves_0_awid, - v_to_slaves_0_awqos, - v_to_slaves_0_awregion, - v_to_slaves_0_wid; - wire [2 : 0] v_to_slaves_0_arprot, - v_to_slaves_0_arsize, - v_to_slaves_0_awprot, - v_to_slaves_0_awsize; - wire [1 : 0] v_from_masters_0_bresp, - v_from_masters_0_rresp, - v_from_masters_1_bresp, - v_from_masters_1_rresp, - v_to_slaves_0_arburst, - v_to_slaves_0_awburst; - wire RDY_reset, - RDY_set_verbosity, - v_from_masters_0_arready, - v_from_masters_0_awready, - v_from_masters_0_bvalid, - v_from_masters_0_rlast, - v_from_masters_0_rvalid, - v_from_masters_0_wready, - v_from_masters_1_arready, - v_from_masters_1_awready, - v_from_masters_1_bvalid, - v_from_masters_1_rlast, - v_from_masters_1_rvalid, - v_from_masters_1_wready, - v_to_slaves_0_arlock, - v_to_slaves_0_arvalid, - v_to_slaves_0_awlock, - v_to_slaves_0_awvalid, - v_to_slaves_0_bready, - v_to_slaves_0_rready, - v_to_slaves_0_wlast, - v_to_slaves_0_wvalid; - - // register fabric_cfg_verbosity - reg [3 : 0] fabric_cfg_verbosity; - wire [3 : 0] fabric_cfg_verbosity$D_IN; - wire fabric_cfg_verbosity$EN; - - // register fabric_rg_reset - reg fabric_rg_reset; - wire fabric_rg_reset$D_IN, fabric_rg_reset$EN; - - // ports of submodule fabric_v_f_rd_err_id_0 - wire [3 : 0] fabric_v_f_rd_err_id_0$D_IN, fabric_v_f_rd_err_id_0$D_OUT; - wire fabric_v_f_rd_err_id_0$CLR, - fabric_v_f_rd_err_id_0$DEQ, - fabric_v_f_rd_err_id_0$EMPTY_N, - fabric_v_f_rd_err_id_0$ENQ; - - // ports of submodule fabric_v_f_rd_err_id_1 - wire [3 : 0] fabric_v_f_rd_err_id_1$D_IN, fabric_v_f_rd_err_id_1$D_OUT; - wire fabric_v_f_rd_err_id_1$CLR, - fabric_v_f_rd_err_id_1$DEQ, - fabric_v_f_rd_err_id_1$EMPTY_N, - fabric_v_f_rd_err_id_1$ENQ; - - // ports of submodule fabric_v_f_rd_err_user_0 - wire fabric_v_f_rd_err_user_0$CLR, - fabric_v_f_rd_err_user_0$DEQ, - fabric_v_f_rd_err_user_0$EMPTY_N, - fabric_v_f_rd_err_user_0$ENQ; - - // ports of submodule fabric_v_f_rd_err_user_1 - wire fabric_v_f_rd_err_user_1$CLR, - fabric_v_f_rd_err_user_1$DEQ, - fabric_v_f_rd_err_user_1$EMPTY_N, - fabric_v_f_rd_err_user_1$ENQ; - - // ports of submodule fabric_v_f_rd_mis_0 - wire [1 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT; - wire fabric_v_f_rd_mis_0$CLR, - fabric_v_f_rd_mis_0$DEQ, - fabric_v_f_rd_mis_0$EMPTY_N, - fabric_v_f_rd_mis_0$ENQ, - fabric_v_f_rd_mis_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_0 - wire fabric_v_f_rd_sjs_0$CLR, - fabric_v_f_rd_sjs_0$DEQ, - fabric_v_f_rd_sjs_0$D_IN, - fabric_v_f_rd_sjs_0$D_OUT, - fabric_v_f_rd_sjs_0$EMPTY_N, - fabric_v_f_rd_sjs_0$ENQ, - fabric_v_f_rd_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_rd_sjs_1 - wire fabric_v_f_rd_sjs_1$CLR, - fabric_v_f_rd_sjs_1$DEQ, - fabric_v_f_rd_sjs_1$D_IN, - fabric_v_f_rd_sjs_1$D_OUT, - fabric_v_f_rd_sjs_1$EMPTY_N, - fabric_v_f_rd_sjs_1$ENQ, - fabric_v_f_rd_sjs_1$FULL_N; - - // ports of submodule fabric_v_f_wr_err_id_0 - wire [3 : 0] fabric_v_f_wr_err_id_0$D_IN, fabric_v_f_wr_err_id_0$D_OUT; - wire fabric_v_f_wr_err_id_0$CLR, - fabric_v_f_wr_err_id_0$DEQ, - fabric_v_f_wr_err_id_0$EMPTY_N, - fabric_v_f_wr_err_id_0$ENQ; - - // ports of submodule fabric_v_f_wr_err_id_1 - wire [3 : 0] fabric_v_f_wr_err_id_1$D_IN, fabric_v_f_wr_err_id_1$D_OUT; - wire fabric_v_f_wr_err_id_1$CLR, - fabric_v_f_wr_err_id_1$DEQ, - fabric_v_f_wr_err_id_1$EMPTY_N, - fabric_v_f_wr_err_id_1$ENQ; - - // ports of submodule fabric_v_f_wr_err_user_0 - wire fabric_v_f_wr_err_user_0$CLR, - fabric_v_f_wr_err_user_0$DEQ, - fabric_v_f_wr_err_user_0$EMPTY_N, - fabric_v_f_wr_err_user_0$ENQ; - - // ports of submodule fabric_v_f_wr_err_user_1 - wire fabric_v_f_wr_err_user_1$CLR, - fabric_v_f_wr_err_user_1$DEQ, - fabric_v_f_wr_err_user_1$EMPTY_N, - fabric_v_f_wr_err_user_1$ENQ; - - // ports of submodule fabric_v_f_wr_mis_0 - wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT; - wire fabric_v_f_wr_mis_0$CLR, - fabric_v_f_wr_mis_0$DEQ, - fabric_v_f_wr_mis_0$EMPTY_N, - fabric_v_f_wr_mis_0$ENQ, - fabric_v_f_wr_mis_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_0 - wire fabric_v_f_wr_sjs_0$CLR, - fabric_v_f_wr_sjs_0$DEQ, - fabric_v_f_wr_sjs_0$D_IN, - fabric_v_f_wr_sjs_0$D_OUT, - fabric_v_f_wr_sjs_0$EMPTY_N, - fabric_v_f_wr_sjs_0$ENQ, - fabric_v_f_wr_sjs_0$FULL_N; - - // ports of submodule fabric_v_f_wr_sjs_1 - wire fabric_v_f_wr_sjs_1$CLR, - fabric_v_f_wr_sjs_1$DEQ, - fabric_v_f_wr_sjs_1$D_IN, - fabric_v_f_wr_sjs_1$D_OUT, - fabric_v_f_wr_sjs_1$EMPTY_N, - fabric_v_f_wr_sjs_1$ENQ, - fabric_v_f_wr_sjs_1$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN, - fabric_xactors_from_masters_0_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_addr$CLR, - fabric_xactors_from_masters_0_f_rd_addr$DEQ, - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_addr$ENQ, - fabric_xactors_from_masters_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_rd_data - wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN, - fabric_xactors_from_masters_0_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_0_f_rd_data$CLR, - fabric_xactors_from_masters_0_f_rd_data$DEQ, - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_0_f_rd_data$ENQ, - fabric_xactors_from_masters_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN, - fabric_xactors_from_masters_0_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_addr$CLR, - fabric_xactors_from_masters_0_f_wr_addr$DEQ, - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_addr$ENQ, - fabric_xactors_from_masters_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN, - fabric_xactors_from_masters_0_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_data$CLR, - fabric_xactors_from_masters_0_f_wr_data$DEQ, - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_data$ENQ, - fabric_xactors_from_masters_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_0_f_wr_resp - wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN, - fabric_xactors_from_masters_0_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_0_f_wr_resp$CLR, - fabric_xactors_from_masters_0_f_wr_resp$DEQ, - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_0_f_wr_resp$ENQ, - fabric_xactors_from_masters_0_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN, - fabric_xactors_from_masters_1_f_rd_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_addr$CLR, - fabric_xactors_from_masters_1_f_rd_addr$DEQ, - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_addr$ENQ, - fabric_xactors_from_masters_1_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_rd_data - wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN, - fabric_xactors_from_masters_1_f_rd_data$D_OUT; - wire fabric_xactors_from_masters_1_f_rd_data$CLR, - fabric_xactors_from_masters_1_f_rd_data$DEQ, - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N, - fabric_xactors_from_masters_1_f_rd_data$ENQ, - fabric_xactors_from_masters_1_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_addr - wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN, - fabric_xactors_from_masters_1_f_wr_addr$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_addr$CLR, - fabric_xactors_from_masters_1_f_wr_addr$DEQ, - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_addr$ENQ, - fabric_xactors_from_masters_1_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_data - wire [76 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN, - fabric_xactors_from_masters_1_f_wr_data$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_data$CLR, - fabric_xactors_from_masters_1_f_wr_data$DEQ, - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_data$ENQ, - fabric_xactors_from_masters_1_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_from_masters_1_f_wr_resp - wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN, - fabric_xactors_from_masters_1_f_wr_resp$D_OUT; - wire fabric_xactors_from_masters_1_f_wr_resp$CLR, - fabric_xactors_from_masters_1_f_wr_resp$DEQ, - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N, - fabric_xactors_from_masters_1_f_wr_resp$ENQ, - fabric_xactors_from_masters_1_f_wr_resp$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN, - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_addr$CLR, - fabric_xactors_to_slaves_0_f_rd_addr$DEQ, - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_addr$ENQ, - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_rd_data - wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_rd_data$CLR, - fabric_xactors_to_slaves_0_f_rd_data$DEQ, - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_rd_data$ENQ, - fabric_xactors_to_slaves_0_f_rd_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_addr - wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN, - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_addr$CLR, - fabric_xactors_to_slaves_0_f_wr_addr$DEQ, - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_addr$ENQ, - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_data - wire [76 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN, - fabric_xactors_to_slaves_0_f_wr_data$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_data$CLR, - fabric_xactors_to_slaves_0_f_wr_data$DEQ, - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_data$ENQ, - fabric_xactors_to_slaves_0_f_wr_data$FULL_N; - - // ports of submodule fabric_xactors_to_slaves_0_f_wr_resp - wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN, - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT; - wire fabric_xactors_to_slaves_0_f_wr_resp$CLR, - fabric_xactors_to_slaves_0_f_wr_resp$DEQ, - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N, - fabric_xactors_to_slaves_0_f_wr_resp$ENQ, - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - CAN_FIRE_RL_fabric_rl_reset, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - CAN_FIRE_reset, - CAN_FIRE_set_verbosity, - CAN_FIRE_v_from_masters_0_m_arvalid, - CAN_FIRE_v_from_masters_0_m_awvalid, - CAN_FIRE_v_from_masters_0_m_bready, - CAN_FIRE_v_from_masters_0_m_rready, - CAN_FIRE_v_from_masters_0_m_wvalid, - CAN_FIRE_v_from_masters_1_m_arvalid, - CAN_FIRE_v_from_masters_1_m_awvalid, - CAN_FIRE_v_from_masters_1_m_bready, - CAN_FIRE_v_from_masters_1_m_rready, - CAN_FIRE_v_from_masters_1_m_wvalid, - CAN_FIRE_v_to_slaves_0_m_arready, - CAN_FIRE_v_to_slaves_0_m_awready, - CAN_FIRE_v_to_slaves_0_m_bvalid, - CAN_FIRE_v_to_slaves_0_m_rvalid, - CAN_FIRE_v_to_slaves_0_m_wready, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1, - WILL_FIRE_RL_fabric_rl_reset, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master, - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave, - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1, - WILL_FIRE_reset, - WILL_FIRE_set_verbosity, - WILL_FIRE_v_from_masters_0_m_arvalid, - WILL_FIRE_v_from_masters_0_m_awvalid, - WILL_FIRE_v_from_masters_0_m_bready, - WILL_FIRE_v_from_masters_0_m_rready, - WILL_FIRE_v_from_masters_0_m_wvalid, - WILL_FIRE_v_from_masters_1_m_arvalid, - WILL_FIRE_v_from_masters_1_m_awvalid, - WILL_FIRE_v_from_masters_1_m_bready, - WILL_FIRE_v_from_masters_1_m_rready, - WILL_FIRE_v_from_masters_1_m_wvalid, - WILL_FIRE_v_to_slaves_0_m_arready, - WILL_FIRE_v_to_slaves_0_m_awready, - WILL_FIRE_v_to_slaves_0_m_bvalid, - WILL_FIRE_v_to_slaves_0_m_rvalid, - WILL_FIRE_v_to_slaves_0_m_wready; - - // inputs to muxes for submodule ports - wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_2; - wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_2, - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_2; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h5877; - reg [31 : 0] v__h6412; - reg [31 : 0] v__h7535; - reg [31 : 0] v__h7914; - reg [31 : 0] v__h8844; - reg [31 : 0] v__h9150; - reg [31 : 0] v__h9457; - reg [31 : 0] v__h9724; - reg [31 : 0] v__h10071; - reg [31 : 0] v__h10398; - reg [31 : 0] v__h10723; - reg [31 : 0] v__h10997; - reg [31 : 0] v__h3699; - reg [31 : 0] v__h3693; - reg [31 : 0] v__h5871; - reg [31 : 0] v__h6406; - reg [31 : 0] v__h7529; - reg [31 : 0] v__h7908; - reg [31 : 0] v__h8838; - reg [31 : 0] v__h9144; - reg [31 : 0] v__h9451; - reg [31 : 0] v__h9718; - reg [31 : 0] v__h10065; - reg [31 : 0] v__h10392; - reg [31 : 0] v__h10717; - reg [31 : 0] v__h10991; - // synopsys translate_on - - // remaining internal signals - wire NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19; - - // action method reset - assign RDY_reset = !fabric_rg_reset ; - assign CAN_FIRE_reset = !fabric_rg_reset ; - assign WILL_FIRE_reset = EN_reset ; - - // action method set_verbosity - assign RDY_set_verbosity = 1'd1 ; - assign CAN_FIRE_set_verbosity = 1'd1 ; - assign WILL_FIRE_set_verbosity = EN_set_verbosity ; - - // action method v_from_masters_0_m_awvalid - assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ; - - // value method v_from_masters_0_m_awready - assign v_from_masters_0_awready = - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - - // action method v_from_masters_0_m_wvalid - assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ; - - // value method v_from_masters_0_m_wready - assign v_from_masters_0_wready = - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - - // value method v_from_masters_0_m_bvalid - assign v_from_masters_0_bvalid = - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_0_m_bid - assign v_from_masters_0_bid = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_0_m_bresp - assign v_from_masters_0_bresp = - fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_0_m_bready - assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ; - - // action method v_from_masters_0_m_arvalid - assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ; - - // value method v_from_masters_0_m_arready - assign v_from_masters_0_arready = - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - - // value method v_from_masters_0_m_rvalid - assign v_from_masters_0_rvalid = - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - - // value method v_from_masters_0_m_rid - assign v_from_masters_0_rid = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_0_m_rdata - assign v_from_masters_0_rdata = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_0_m_rresp - assign v_from_masters_0_rresp = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_0_m_rlast - assign v_from_masters_0_rlast = - fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_0_m_rready - assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ; - - // action method v_from_masters_1_m_awvalid - assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ; - - // value method v_from_masters_1_m_awready - assign v_from_masters_1_awready = - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - - // action method v_from_masters_1_m_wvalid - assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ; - - // value method v_from_masters_1_m_wready - assign v_from_masters_1_wready = - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - - // value method v_from_masters_1_m_bvalid - assign v_from_masters_1_bvalid = - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - - // value method v_from_masters_1_m_bid - assign v_from_masters_1_bid = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ; - - // value method v_from_masters_1_m_bresp - assign v_from_masters_1_bresp = - fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ; - - // action method v_from_masters_1_m_bready - assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ; - - // action method v_from_masters_1_m_arvalid - assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ; - - // value method v_from_masters_1_m_arready - assign v_from_masters_1_arready = - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - - // value method v_from_masters_1_m_rvalid - assign v_from_masters_1_rvalid = - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - - // value method v_from_masters_1_m_rid - assign v_from_masters_1_rid = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ; - - // value method v_from_masters_1_m_rdata - assign v_from_masters_1_rdata = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ; - - // value method v_from_masters_1_m_rresp - assign v_from_masters_1_rresp = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ; - - // value method v_from_masters_1_m_rlast - assign v_from_masters_1_rlast = - fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ; - - // action method v_from_masters_1_m_rready - assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ; - assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ; - - // value method v_to_slaves_0_m_awvalid - assign v_to_slaves_0_awvalid = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_awid - assign v_to_slaves_0_awid = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_awaddr - assign v_to_slaves_0_awaddr = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_awlen - assign v_to_slaves_0_awlen = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_awsize - assign v_to_slaves_0_awsize = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_awburst - assign v_to_slaves_0_awburst = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_awlock - assign v_to_slaves_0_awlock = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_awcache - assign v_to_slaves_0_awcache = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_awprot - assign v_to_slaves_0_awprot = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_awqos - assign v_to_slaves_0_awqos = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_awregion - assign v_to_slaves_0_awregion = - fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_awready - assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ; - - // value method v_to_slaves_0_m_wvalid - assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ; - - // value method v_to_slaves_0_m_wid - assign v_to_slaves_0_wid = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[76:73] ; - - // value method v_to_slaves_0_m_wdata - assign v_to_slaves_0_wdata = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ; - - // value method v_to_slaves_0_m_wstrb - assign v_to_slaves_0_wstrb = - fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ; - - // value method v_to_slaves_0_m_wlast - assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ; - - // action method v_to_slaves_0_m_wready - assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ; - - // action method v_to_slaves_0_m_bvalid - assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ; - - // value method v_to_slaves_0_m_bready - assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - - // value method v_to_slaves_0_m_arvalid - assign v_to_slaves_0_arvalid = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ; - - // value method v_to_slaves_0_m_arid - assign v_to_slaves_0_arid = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ; - - // value method v_to_slaves_0_m_araddr - assign v_to_slaves_0_araddr = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ; - - // value method v_to_slaves_0_m_arlen - assign v_to_slaves_0_arlen = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ; - - // value method v_to_slaves_0_m_arsize - assign v_to_slaves_0_arsize = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ; - - // value method v_to_slaves_0_m_arburst - assign v_to_slaves_0_arburst = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ; - - // value method v_to_slaves_0_m_arlock - assign v_to_slaves_0_arlock = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ; - - // value method v_to_slaves_0_m_arcache - assign v_to_slaves_0_arcache = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ; - - // value method v_to_slaves_0_m_arprot - assign v_to_slaves_0_arprot = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ; - - // value method v_to_slaves_0_m_arqos - assign v_to_slaves_0_arqos = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ; - - // value method v_to_slaves_0_m_arregion - assign v_to_slaves_0_arregion = - fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ; - - // action method v_to_slaves_0_m_arready - assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ; - - // action method v_to_slaves_0_m_rvalid - assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ; - - // value method v_to_slaves_0_m_rready - assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - - // submodule fabric_v_f_rd_err_id_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_0$D_IN), - .ENQ(fabric_v_f_rd_err_id_0$ENQ), - .DEQ(fabric_v_f_rd_err_id_0$DEQ), - .CLR(fabric_v_f_rd_err_id_0$CLR), - .D_OUT(fabric_v_f_rd_err_id_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_id_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_id_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_err_id_1$D_IN), - .ENQ(fabric_v_f_rd_err_id_1$ENQ), - .DEQ(fabric_v_f_rd_err_id_1$DEQ), - .CLR(fabric_v_f_rd_err_id_1$CLR), - .D_OUT(fabric_v_f_rd_err_id_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_0$ENQ), - .DEQ(fabric_v_f_rd_err_user_0$DEQ), - .CLR(fabric_v_f_rd_err_user_0$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_rd_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_rd_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_rd_err_user_1$ENQ), - .DEQ(fabric_v_f_rd_err_user_1$DEQ), - .CLR(fabric_v_f_rd_err_user_1$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_rd_err_user_1$EMPTY_N)); - - // submodule fabric_v_f_rd_mis_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_mis_0$D_IN), - .ENQ(fabric_v_f_rd_mis_0$ENQ), - .DEQ(fabric_v_f_rd_mis_0$DEQ), - .CLR(fabric_v_f_rd_mis_0$CLR), - .D_OUT(fabric_v_f_rd_mis_0$D_OUT), - .FULL_N(fabric_v_f_rd_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_0$D_IN), - .ENQ(fabric_v_f_rd_sjs_0$ENQ), - .DEQ(fabric_v_f_rd_sjs_0$DEQ), - .CLR(fabric_v_f_rd_sjs_0$CLR), - .D_OUT(fabric_v_f_rd_sjs_0$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_rd_sjs_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_rd_sjs_1$D_IN), - .ENQ(fabric_v_f_rd_sjs_1$ENQ), - .DEQ(fabric_v_f_rd_sjs_1$DEQ), - .CLR(fabric_v_f_rd_sjs_1$CLR), - .D_OUT(fabric_v_f_rd_sjs_1$D_OUT), - .FULL_N(fabric_v_f_rd_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_id_0 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_0$D_IN), - .ENQ(fabric_v_f_wr_err_id_0$ENQ), - .DEQ(fabric_v_f_wr_err_id_0$DEQ), - .CLR(fabric_v_f_wr_err_id_0$CLR), - .D_OUT(fabric_v_f_wr_err_id_0$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_id_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_id_1 - SizedFIFO #(.p1width(32'd4), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_err_id_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_err_id_1$D_IN), - .ENQ(fabric_v_f_wr_err_id_1$ENQ), - .DEQ(fabric_v_f_wr_err_id_1$DEQ), - .CLR(fabric_v_f_wr_err_id_1$CLR), - .D_OUT(fabric_v_f_wr_err_id_1$D_OUT), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_id_1$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_0 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_0(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_0$ENQ), - .DEQ(fabric_v_f_wr_err_user_0$DEQ), - .CLR(fabric_v_f_wr_err_user_0$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_user_0$EMPTY_N)); - - // submodule fabric_v_f_wr_err_user_1 - SizedFIFO0 #(.p1depth(32'd8), - .p2cntr_width(32'd4), - .guarded(32'd1)) fabric_v_f_wr_err_user_1(.RST(RST_N), - .CLK(CLK), - .ENQ(fabric_v_f_wr_err_user_1$ENQ), - .DEQ(fabric_v_f_wr_err_user_1$DEQ), - .CLR(fabric_v_f_wr_err_user_1$CLR), - .FULL_N(), - .EMPTY_N(fabric_v_f_wr_err_user_1$EMPTY_N)); - - // submodule fabric_v_f_wr_mis_0 - SizedFIFO #(.p1width(32'd2), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_mis_0$D_IN), - .ENQ(fabric_v_f_wr_mis_0$ENQ), - .DEQ(fabric_v_f_wr_mis_0$DEQ), - .CLR(fabric_v_f_wr_mis_0$CLR), - .D_OUT(fabric_v_f_wr_mis_0$D_OUT), - .FULL_N(fabric_v_f_wr_mis_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_0 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_0$D_IN), - .ENQ(fabric_v_f_wr_sjs_0$ENQ), - .DEQ(fabric_v_f_wr_sjs_0$DEQ), - .CLR(fabric_v_f_wr_sjs_0$CLR), - .D_OUT(fabric_v_f_wr_sjs_0$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_0$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N)); - - // submodule fabric_v_f_wr_sjs_1 - SizedFIFO #(.p1width(32'd1), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_v_f_wr_sjs_1$D_IN), - .ENQ(fabric_v_f_wr_sjs_1$ENQ), - .DEQ(fabric_v_f_wr_sjs_1$DEQ), - .CLR(fabric_v_f_wr_sjs_1$CLR), - .D_OUT(fabric_v_f_wr_sjs_1$D_OUT), - .FULL_N(fabric_v_f_wr_sjs_1$FULL_N), - .EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_rd_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_data$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_from_masters_1_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN), - .ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ), - .DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ), - .CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR), - .D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_data - FIFO2 #(.width(32'd77), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N)); - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN), - .ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ), - .DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ), - .CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR), - .D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT), - .FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N), - .EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N)); - - // rule RL_fabric_rl_wr_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_data$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_v_f_wr_sjs_0$FULL_N ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - fabric_xactors_to_slaves_0_f_wr_addr$FULL_N && - fabric_xactors_to_slaves_0_f_wr_data$FULL_N && - fabric_v_f_wr_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_data$EMPTY_N && - fabric_v_f_wr_sjs_1$FULL_N ; - assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - !WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_v_f_rd_sjs_0$FULL_N ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_rd_xaction_master_to_slave_1 - assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - fabric_xactors_to_slaves_0_f_rd_addr$FULL_N && - fabric_v_f_rd_mis_0$FULL_N && - fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N && - fabric_v_f_rd_sjs_1$FULL_N ; - assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - !WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - - // rule RL_fabric_rl_wr_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd0 && - !fabric_v_f_wr_sjs_0$D_OUT ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - - // rule RL_fabric_rl_wr_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - fabric_v_f_wr_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N && - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_mis_0$D_OUT == 2'd1 && - !fabric_v_f_wr_sjs_1$D_OUT ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_wr_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master = - fabric_v_f_wr_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_0$EMPTY_N && - fabric_v_f_wr_err_user_0$EMPTY_N && - fabric_v_f_wr_sjs_0$D_OUT ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - - // rule RL_fabric_rl_wr_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - fabric_v_f_wr_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_wr_resp$FULL_N && - fabric_v_f_wr_err_id_1$EMPTY_N && - fabric_v_f_wr_err_user_1$EMPTY_N && - fabric_v_f_wr_sjs_1$D_OUT ; - assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_slave_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - fabric_v_f_rd_mis_0$EMPTY_N && fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd0 && - !fabric_v_f_rd_sjs_0$D_OUT ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - - // rule RL_fabric_rl_rd_resp_slave_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - fabric_v_f_rd_mis_0$EMPTY_N && - fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N && - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_mis_0$D_OUT == 2'd1 && - !fabric_v_f_rd_sjs_1$D_OUT ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - - // rule RL_fabric_rl_rd_resp_err_to_master - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master = - fabric_v_f_rd_sjs_0$EMPTY_N && - fabric_xactors_from_masters_0_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_0$EMPTY_N && - fabric_v_f_rd_err_user_0$EMPTY_N && - fabric_v_f_rd_sjs_0$D_OUT ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - - // rule RL_fabric_rl_rd_resp_err_to_master_1 - assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - fabric_v_f_rd_sjs_1$EMPTY_N && - fabric_xactors_from_masters_1_f_rd_data$FULL_N && - fabric_v_f_rd_err_id_1$EMPTY_N && - fabric_v_f_rd_err_user_1$EMPTY_N && - fabric_v_f_rd_sjs_1$D_OUT ; - assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - - // rule RL_fabric_rl_reset - assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ; - - // inputs to muxes for submodule ports - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = - { fabric_v_f_rd_err_id_0$D_OUT, 67'd7 } ; - assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_2 = - { fabric_v_f_wr_err_id_0$D_OUT, 2'b11 } ; - assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_2 = - { fabric_v_f_rd_err_id_1$D_OUT, 67'd7 } ; - assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_2 = - { fabric_v_f_wr_err_id_1$D_OUT, 2'b11 } ; - - // register fabric_cfg_verbosity - assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ; - assign fabric_cfg_verbosity$EN = EN_set_verbosity ; - - // register fabric_rg_reset - assign fabric_rg_reset$D_IN = !fabric_rg_reset ; - assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ; - - // submodule fabric_v_f_rd_err_id_0 - assign fabric_v_f_rd_err_id_0$D_IN = 4'h0 ; - assign fabric_v_f_rd_err_id_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_id_0$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_id_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_id_1 - assign fabric_v_f_rd_err_id_1$D_IN = 4'h0 ; - assign fabric_v_f_rd_err_id_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_id_1$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_id_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_user_0 - assign fabric_v_f_rd_err_user_0$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_v_f_rd_err_user_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_err_user_1 - assign fabric_v_f_rd_err_user_1$ENQ = 1'b0 ; - assign fabric_v_f_rd_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_v_f_rd_err_user_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_mis_0 - assign fabric_v_f_rd_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? 2'd0 : 2'd1 ; - assign fabric_v_f_rd_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - assign fabric_v_f_rd_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_0 - assign fabric_v_f_rd_sjs_0$D_IN = 1'd0 ; - assign fabric_v_f_rd_sjs_0$ENQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_v_f_rd_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_rd_sjs_1 - assign fabric_v_f_rd_sjs_1$D_IN = 1'd0 ; - assign fabric_v_f_rd_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - assign fabric_v_f_rd_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ; - assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_id_0 - assign fabric_v_f_wr_err_id_0$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_id_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_id_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_id_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_id_1 - assign fabric_v_f_wr_err_id_1$D_IN = 4'h0 ; - assign fabric_v_f_wr_err_id_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_id_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_id_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_0 - assign fabric_v_f_wr_err_user_0$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_user_0$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_v_f_wr_err_user_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_err_user_1 - assign fabric_v_f_wr_err_user_1$ENQ = 1'b0 ; - assign fabric_v_f_wr_err_user_1$DEQ = - CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_v_f_wr_err_user_1$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_mis_0 - assign fabric_v_f_wr_mis_0$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ; - assign fabric_v_f_wr_mis_0$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_mis_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_0 - assign fabric_v_f_wr_sjs_0$D_IN = 1'd0 ; - assign fabric_v_f_wr_sjs_0$ENQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_v_f_wr_sjs_0$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ; - - // submodule fabric_v_f_wr_sjs_1 - assign fabric_v_f_wr_sjs_1$D_IN = 1'd0 ; - assign fabric_v_f_wr_sjs_1$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_v_f_wr_sjs_1$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ; - assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_addr - assign fabric_xactors_from_masters_0_f_rd_addr$D_IN = - { v_from_masters_0_arid, - v_from_masters_0_araddr, - v_from_masters_0_arlen, - v_from_masters_0_arsize, - v_from_masters_0_arburst, - v_from_masters_0_arlock, - v_from_masters_0_arcache, - v_from_masters_0_arprot, - v_from_masters_0_arqos, - v_from_masters_0_arregion } ; - assign fabric_xactors_from_masters_0_f_rd_addr$ENQ = - v_from_masters_0_arvalid && - fabric_xactors_from_masters_0_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_rd_addr$DEQ = - CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_rd_data - assign fabric_xactors_from_masters_0_f_rd_data$D_IN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ? - fabric_xactors_to_slaves_0_f_rd_data$D_OUT : - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 ; - assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_rd_data$DEQ = - v_from_masters_0_rready && - fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_addr - assign fabric_xactors_from_masters_0_f_wr_addr$D_IN = - { v_from_masters_0_awid, - v_from_masters_0_awaddr, - v_from_masters_0_awlen, - v_from_masters_0_awsize, - v_from_masters_0_awburst, - v_from_masters_0_awlock, - v_from_masters_0_awcache, - v_from_masters_0_awprot, - v_from_masters_0_awqos, - v_from_masters_0_awregion } ; - assign fabric_xactors_from_masters_0_f_wr_addr$ENQ = - v_from_masters_0_awvalid && - fabric_xactors_from_masters_0_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_addr$DEQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_data - assign fabric_xactors_from_masters_0_f_wr_data$D_IN = - { v_from_masters_0_wid, - v_from_masters_0_wdata, - v_from_masters_0_wstrb, - v_from_masters_0_wlast } ; - assign fabric_xactors_from_masters_0_f_wr_data$ENQ = - v_from_masters_0_wvalid && - fabric_xactors_from_masters_0_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_0_f_wr_data$DEQ = - CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ; - assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_0_f_wr_resp - assign fabric_xactors_from_masters_0_f_wr_resp$D_IN = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ? - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT : - MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_2 ; - assign fabric_xactors_from_masters_0_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ; - assign fabric_xactors_from_masters_0_f_wr_resp$DEQ = - v_from_masters_0_bready && - fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_addr - assign fabric_xactors_from_masters_1_f_rd_addr$D_IN = - { v_from_masters_1_arid, - v_from_masters_1_araddr, - v_from_masters_1_arlen, - v_from_masters_1_arsize, - v_from_masters_1_arburst, - v_from_masters_1_arlock, - v_from_masters_1_arcache, - v_from_masters_1_arprot, - v_from_masters_1_arqos, - v_from_masters_1_arregion } ; - assign fabric_xactors_from_masters_1_f_rd_addr$ENQ = - v_from_masters_1_arvalid && - fabric_xactors_from_masters_1_f_rd_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_rd_addr$DEQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_rd_data - assign fabric_xactors_from_masters_1_f_rd_data$D_IN = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ? - fabric_xactors_to_slaves_0_f_rd_data$D_OUT : - MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_2 ; - assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_rd_data$DEQ = - v_from_masters_1_rready && - fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_addr - assign fabric_xactors_from_masters_1_f_wr_addr$D_IN = - { v_from_masters_1_awid, - v_from_masters_1_awaddr, - v_from_masters_1_awlen, - v_from_masters_1_awsize, - v_from_masters_1_awburst, - v_from_masters_1_awlock, - v_from_masters_1_awcache, - v_from_masters_1_awprot, - v_from_masters_1_awqos, - v_from_masters_1_awregion } ; - assign fabric_xactors_from_masters_1_f_wr_addr$ENQ = - v_from_masters_1_awvalid && - fabric_xactors_from_masters_1_f_wr_addr$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_addr$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_data - assign fabric_xactors_from_masters_1_f_wr_data$D_IN = - { v_from_masters_1_wid, - v_from_masters_1_wdata, - v_from_masters_1_wstrb, - v_from_masters_1_wlast } ; - assign fabric_xactors_from_masters_1_f_wr_data$ENQ = - v_from_masters_1_wvalid && - fabric_xactors_from_masters_1_f_wr_data$FULL_N ; - assign fabric_xactors_from_masters_1_f_wr_data$DEQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_from_masters_1_f_wr_resp - assign fabric_xactors_from_masters_1_f_wr_resp$D_IN = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ? - fabric_xactors_to_slaves_0_f_wr_resp$D_OUT : - MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_2 ; - assign fabric_xactors_from_masters_1_f_wr_resp$ENQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ; - assign fabric_xactors_from_masters_1_f_wr_resp$DEQ = - v_from_masters_1_bready && - fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ; - assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_addr - assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_rd_addr$D_OUT : - fabric_xactors_from_masters_1_f_rd_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ = - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ; - assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ = - fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N && - v_to_slaves_0_arready ; - assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_rd_data - assign fabric_xactors_to_slaves_0_f_rd_data$D_IN = - { v_to_slaves_0_rid, - v_to_slaves_0_rdata, - v_to_slaves_0_rresp, - v_to_slaves_0_rlast } ; - assign fabric_xactors_to_slaves_0_f_rd_data$ENQ = - v_to_slaves_0_rvalid && - fabric_xactors_to_slaves_0_f_rd_data$FULL_N ; - assign fabric_xactors_to_slaves_0_f_rd_data$DEQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_addr - assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_addr$D_OUT : - fabric_xactors_from_masters_1_f_wr_addr$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ = - fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N && - v_to_slaves_0_awready ; - assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_data - assign fabric_xactors_to_slaves_0_f_wr_data$D_IN = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? - fabric_xactors_from_masters_0_f_wr_data$D_OUT : - fabric_xactors_from_masters_1_f_wr_data$D_OUT ; - assign fabric_xactors_to_slaves_0_f_wr_data$ENQ = - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave || - WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ; - assign fabric_xactors_to_slaves_0_f_wr_data$DEQ = - fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N && - v_to_slaves_0_wready ; - assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ; - - // submodule fabric_xactors_to_slaves_0_f_wr_resp - assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN = - { v_to_slaves_0_bid, v_to_slaves_0_bresp } ; - assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ = - v_to_slaves_0_bvalid && - fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ; - assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ = - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 || - WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ; - assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ; - - // remaining internal signals - assign NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19 = - fabric_cfg_verbosity > 4'd1 ; - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; - end - else - begin - if (fabric_cfg_verbosity$EN) - fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY - fabric_cfg_verbosity$D_IN; - if (fabric_rg_reset$EN) - fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - fabric_cfg_verbosity = 4'hA; - fabric_rg_reset = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h5877 = $stime; - #0; - end - v__h5871 = v__h5877 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h5871, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19 && - fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19 && - !fabric_xactors_from_masters_0_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h6412 = $stime; - #0; - end - v__h6406 = v__h6412 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", - v__h6406, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awaddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "awuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Wr_Data { ", "wid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[76:73]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "wlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19 && - fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19 && - !fabric_xactors_from_masters_1_f_wr_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "wuser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h7535 = $stime; - #0; - end - v__h7529 = v__h7535 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h7529, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h7914 = $stime; - #0; - end - v__h7908 = v__h7914 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", - v__h7908, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "araddr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arlen: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arsize: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arburst: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arlock: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arcache: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arprot: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arqos: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "arregion: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "aruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h8844 = $stime; - #0; - end - v__h8838 = v__h8844 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h8838, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h9150 = $stime; - #0; - end - v__h9144 = v__h9150 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", - v__h9144, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h9457 = $stime; - #0; - end - v__h9451 = v__h9457 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h9451, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_v_f_wr_err_id_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h9724 = $stime; - #0; - end - v__h9718 = v__h9724 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: wr master [%0d] <- error", - v__h9718, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Wr_Resp { ", "bid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_v_f_wr_err_id_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "bresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "buser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h10071 = $stime; - #0; - end - v__h10065 = v__h10071 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h10065, - $signed(32'd0), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h10398 = $stime; - #0; - end - v__h10392 = v__h10398 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", - v__h10392, - $signed(32'd1), - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19 && - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19 && - !fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'd0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h10723 = $stime; - #0; - end - v__h10717 = v__h10723 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h10717, - $signed(32'd0)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_v_f_rd_err_id_0$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - begin - v__h10997 = $stime; - #0; - end - v__h10991 = v__h10997 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $display("%0d: AXI4_Fabric: rd master [%0d] <- error", - v__h10991, - $signed(32'd1)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("AXI4_Rd_Data { ", "rid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", fabric_v_f_rd_err_id_1$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 64'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rresp: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 2'b11); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "rlast: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write(", ", "ruser: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("'h%h", 1'h0, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 && - NOT_fabric_cfg_verbosity_read__7_ULE_1_8___d19) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) - begin - v__h3699 = $stime; - #0; - end - v__h3693 = v__h3699 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (fabric_rg_reset) $display("%0d: AXI4_Fabric.rl_reset", v__h3693); - end - // synopsys translate_on -endmodule // mkFabric_2x1 - diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkGPR_RegFile.v b/src_SSITH_P1/xilinx_ip/hdl/mkGPR_RegFile.v index cb7b11b7..38844265 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkGPR_RegFile.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkGPR_RegFile.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:16 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkIntMul_32.v b/src_SSITH_P1/xilinx_ip/hdl/mkIntMul_32.v index f4d13fdd..9e92b6b6 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkIntMul_32.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkIntMul_32.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:40 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkIntMul_64.v b/src_SSITH_P1/xilinx_ip/hdl/mkIntMul_64.v index 0b513191..9a7bb9af 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkIntMul_64.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkIntMul_64.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:40 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkJtagTap.v b/src_SSITH_P1/xilinx_ip/hdl/mkJtagTap.v index b462cf5c..5e299150 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkJtagTap.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkJtagTap.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:21 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkMMU_DCache.v b/src_SSITH_P1/xilinx_ip/hdl/mkMMU_DCache.v new file mode 100644 index 00000000..312c4441 --- /dev/null +++ b/src_SSITH_P1/xilinx_ip/hdl/mkMMU_DCache.v @@ -0,0 +1,5542 @@ +// +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// +// On Tue Jul 9 16:18:45 BST 2019 +// +// +// Ports: +// Name I/O size props +// RDY_set_verbosity O 1 const +// RDY_server_reset_request_put O 1 reg +// RDY_server_reset_response_get O 1 +// valid O 1 +// addr O 32 reg +// word64 O 64 +// st_amo_val O 64 +// exc O 1 +// exc_code O 4 reg +// RDY_server_flush_request_put O 1 reg +// RDY_server_flush_response_get O 1 +// RDY_tlb_flush O 1 const +// mem_master_awid O 4 +// mem_master_awaddr O 64 +// mem_master_awlen O 8 +// mem_master_awsize O 3 +// mem_master_awburst O 2 +// mem_master_awlock O 1 +// mem_master_awcache O 4 +// mem_master_awprot O 3 +// mem_master_awqos O 4 +// mem_master_awregion O 4 +// mem_master_awvalid O 1 +// mem_master_wdata O 64 +// mem_master_wstrb O 8 +// mem_master_wlast O 1 +// mem_master_wvalid O 1 +// mem_master_bready O 1 +// mem_master_arid O 4 +// mem_master_araddr O 64 +// mem_master_arlen O 8 +// mem_master_arsize O 3 +// mem_master_arburst O 2 +// mem_master_arlock O 1 +// mem_master_arcache O 4 +// mem_master_arprot O 3 +// mem_master_arqos O 4 +// mem_master_arregion O 4 +// mem_master_arvalid O 1 +// mem_master_rready O 1 +// CLK I 1 clock +// RST_N I 1 reset +// set_verbosity_verbosity I 4 reg +// req_op I 2 +// req_f3 I 3 +// req_amo_funct7 I 7 reg +// req_addr I 32 +// req_st_value I 64 +// req_priv I 2 unused +// req_sstatus_SUM I 1 unused +// req_mstatus_MXR I 1 unused +// req_satp I 32 unused +// mem_master_awready I 1 +// mem_master_wready I 1 +// mem_master_bid I 4 +// mem_master_bresp I 2 +// mem_master_arready I 1 +// mem_master_rid I 4 +// mem_master_rdata I 64 +// mem_master_rresp I 2 +// mem_master_rlast I 1 +// EN_set_verbosity I 1 +// EN_server_reset_request_put I 1 +// EN_server_reset_response_get I 1 +// EN_req I 1 +// EN_server_flush_request_put I 1 +// EN_server_flush_response_get I 1 +// EN_tlb_flush I 1 unused +// mem_master_bvalid I 1 +// mem_master_rvalid I 1 +// +// Combinational paths from inputs to outputs: +// (mem_master_rid, +// mem_master_rdata, +// mem_master_rresp, +// mem_master_rlast, +// mem_master_rvalid) -> valid +// (mem_master_rid, +// mem_master_rdata, +// mem_master_rresp, +// mem_master_rlast, +// mem_master_rvalid) -> word64 +// EN_req -> mem_master_arid +// EN_req -> mem_master_araddr +// EN_req -> mem_master_arlen +// EN_req -> mem_master_arsize +// EN_req -> mem_master_arburst +// EN_req -> mem_master_arlock +// EN_req -> mem_master_arcache +// EN_req -> mem_master_arprot +// EN_req -> mem_master_arqos +// EN_req -> mem_master_arregion +// EN_req -> mem_master_aruser +// EN_req -> mem_master_arvalid +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkMMU_DCache(CLK, + RST_N, + + set_verbosity_verbosity, + EN_set_verbosity, + RDY_set_verbosity, + + EN_server_reset_request_put, + RDY_server_reset_request_put, + + EN_server_reset_response_get, + RDY_server_reset_response_get, + + req_op, + req_f3, + req_amo_funct7, + req_addr, + req_st_value, + req_priv, + req_sstatus_SUM, + req_mstatus_MXR, + req_satp, + EN_req, + + valid, + + addr, + + word64, + + st_amo_val, + + exc, + + exc_code, + + EN_server_flush_request_put, + RDY_server_flush_request_put, + + EN_server_flush_response_get, + RDY_server_flush_response_get, + + EN_tlb_flush, + RDY_tlb_flush, + + mem_master_awid, + + mem_master_awaddr, + + mem_master_awlen, + + mem_master_awsize, + + mem_master_awburst, + + mem_master_awlock, + + mem_master_awcache, + + mem_master_awprot, + + mem_master_awqos, + + mem_master_awregion, + + mem_master_awvalid, + + mem_master_awready, + + mem_master_wdata, + + mem_master_wstrb, + + mem_master_wlast, + + mem_master_wvalid, + + mem_master_wready, + + mem_master_bid, + mem_master_bresp, + mem_master_bvalid, + + mem_master_bready, + + mem_master_arid, + + mem_master_araddr, + + mem_master_arlen, + + mem_master_arsize, + + mem_master_arburst, + + mem_master_arlock, + + mem_master_arcache, + + mem_master_arprot, + + mem_master_arqos, + + mem_master_arregion, + + mem_master_arvalid, + + mem_master_arready, + + mem_master_rid, + mem_master_rdata, + mem_master_rresp, + mem_master_rlast, + mem_master_rvalid, + + mem_master_rready); + input CLK; + input RST_N; + + // action method set_verbosity + input [3 : 0] set_verbosity_verbosity; + input EN_set_verbosity; + output RDY_set_verbosity; + + // action method server_reset_request_put + input EN_server_reset_request_put; + output RDY_server_reset_request_put; + + // action method server_reset_response_get + input EN_server_reset_response_get; + output RDY_server_reset_response_get; + + // action method req + input [1 : 0] req_op; + input [2 : 0] req_f3; + input [6 : 0] req_amo_funct7; + input [31 : 0] req_addr; + input [63 : 0] req_st_value; + input [1 : 0] req_priv; + input req_sstatus_SUM; + input req_mstatus_MXR; + input [31 : 0] req_satp; + input EN_req; + + // value method valid + output valid; + + // value method addr + output [31 : 0] addr; + + // value method word64 + output [63 : 0] word64; + + // value method st_amo_val + output [63 : 0] st_amo_val; + + // value method exc + output exc; + + // value method exc_code + output [3 : 0] exc_code; + + // action method server_flush_request_put + input EN_server_flush_request_put; + output RDY_server_flush_request_put; + + // action method server_flush_response_get + input EN_server_flush_response_get; + output RDY_server_flush_response_get; + + // action method tlb_flush + input EN_tlb_flush; + output RDY_tlb_flush; + + // value method mem_master_aw_awid + output [3 : 0] mem_master_awid; + + // value method mem_master_aw_awaddr + output [63 : 0] mem_master_awaddr; + + // value method mem_master_aw_awlen + output [7 : 0] mem_master_awlen; + + // value method mem_master_aw_awsize + output [2 : 0] mem_master_awsize; + + // value method mem_master_aw_awburst + output [1 : 0] mem_master_awburst; + + // value method mem_master_aw_awlock + output mem_master_awlock; + + // value method mem_master_aw_awcache + output [3 : 0] mem_master_awcache; + + // value method mem_master_aw_awprot + output [2 : 0] mem_master_awprot; + + // value method mem_master_aw_awqos + output [3 : 0] mem_master_awqos; + + // value method mem_master_aw_awregion + output [3 : 0] mem_master_awregion; + + // value method mem_master_aw_awuser + + // value method mem_master_aw_awvalid + output mem_master_awvalid; + + // action method mem_master_aw_awready + input mem_master_awready; + + // value method mem_master_w_wdata + output [63 : 0] mem_master_wdata; + + // value method mem_master_w_wstrb + output [7 : 0] mem_master_wstrb; + + // value method mem_master_w_wlast + output mem_master_wlast; + + // value method mem_master_w_wuser + + // value method mem_master_w_wvalid + output mem_master_wvalid; + + // action method mem_master_w_wready + input mem_master_wready; + + // action method mem_master_b_bflit + input [3 : 0] mem_master_bid; + input [1 : 0] mem_master_bresp; + input mem_master_bvalid; + + // value method mem_master_b_bready + output mem_master_bready; + + // value method mem_master_ar_arid + output [3 : 0] mem_master_arid; + + // value method mem_master_ar_araddr + output [63 : 0] mem_master_araddr; + + // value method mem_master_ar_arlen + output [7 : 0] mem_master_arlen; + + // value method mem_master_ar_arsize + output [2 : 0] mem_master_arsize; + + // value method mem_master_ar_arburst + output [1 : 0] mem_master_arburst; + + // value method mem_master_ar_arlock + output mem_master_arlock; + + // value method mem_master_ar_arcache + output [3 : 0] mem_master_arcache; + + // value method mem_master_ar_arprot + output [2 : 0] mem_master_arprot; + + // value method mem_master_ar_arqos + output [3 : 0] mem_master_arqos; + + // value method mem_master_ar_arregion + output [3 : 0] mem_master_arregion; + + // value method mem_master_ar_aruser + + // value method mem_master_ar_arvalid + output mem_master_arvalid; + + // action method mem_master_ar_arready + input mem_master_arready; + + // action method mem_master_r_rflit + input [3 : 0] mem_master_rid; + input [63 : 0] mem_master_rdata; + input [1 : 0] mem_master_rresp; + input mem_master_rlast; + input mem_master_rvalid; + + // value method mem_master_r_rready + output mem_master_rready; + + // signals for module outputs + reg [63 : 0] word64; + wire [63 : 0] mem_master_araddr, + mem_master_awaddr, + mem_master_wdata, + st_amo_val; + wire [31 : 0] addr; + wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; + wire [3 : 0] exc_code, + mem_master_arcache, + mem_master_arid, + mem_master_arqos, + mem_master_arregion, + mem_master_awcache, + mem_master_awid, + mem_master_awqos, + mem_master_awregion; + wire [2 : 0] mem_master_arprot, + mem_master_arsize, + mem_master_awprot, + mem_master_awsize; + wire [1 : 0] mem_master_arburst, mem_master_awburst; + wire RDY_server_flush_request_put, + RDY_server_flush_response_get, + RDY_server_reset_request_put, + RDY_server_reset_response_get, + RDY_set_verbosity, + RDY_tlb_flush, + exc, + mem_master_arlock, + mem_master_arvalid, + mem_master_awlock, + mem_master_awvalid, + mem_master_bready, + mem_master_rready, + mem_master_wlast, + mem_master_wvalid, + valid; + + // inlined wires + wire [97 : 0] cache_master_xactor_shim_arff_rv$port0__write_1, + cache_master_xactor_shim_arff_rv$port1__read, + cache_master_xactor_shim_arff_rv$port2__read, + cache_master_xactor_shim_arff_rv$port3__read, + cache_master_xactor_shim_awff_rv$port0__write_1, + cache_master_xactor_shim_awff_rv$port1__read, + cache_master_xactor_shim_awff_rv$port2__read, + cache_master_xactor_shim_awff_rv$port3__read; + wire [73 : 0] cache_master_xactor_shim_wff_rv$port0__write_1, + cache_master_xactor_shim_wff_rv$port1__read, + cache_master_xactor_shim_wff_rv$port2__read, + cache_master_xactor_shim_wff_rv$port3__read; + wire [71 : 0] cache_master_xactor_shim_rff_rv$port0__write_1, + cache_master_xactor_shim_rff_rv$port1__read, + cache_master_xactor_shim_rff_rv$port2__read, + cache_master_xactor_shim_rff_rv$port3__read; + wire [70 : 0] cache_master_xactor_ug_master_u_r_putWire$wget; + wire [10 : 0] cache_crg_sb_to_load_delay$port0__write_1, + cache_crg_sb_to_load_delay$port2__read; + wire [6 : 0] cache_master_xactor_shim_bff_rv$port0__write_1, + cache_master_xactor_shim_bff_rv$port1__read, + cache_master_xactor_shim_bff_rv$port2__read, + cache_master_xactor_shim_bff_rv$port3__read; + wire [5 : 0] cache_master_xactor_ug_master_u_b_putWire$wget; + wire [3 : 0] cache_ctr_wr_rsps_pending_crg$port0__write_1, + cache_ctr_wr_rsps_pending_crg$port1__read, + cache_ctr_wr_rsps_pending_crg$port1__write_1, + cache_ctr_wr_rsps_pending_crg$port2__read, + cache_ctr_wr_rsps_pending_crg$port3__read; + wire cache_crg_sb_to_load_delay$EN_port1__write, + cache_dw_valid$whas, + cache_master_xactor_shim_arff_rv$EN_port0__write, + cache_master_xactor_shim_rff_rv$EN_port1__write, + cache_master_xactor_ug_master_u_ar_dropWire$whas, + cache_master_xactor_ug_master_u_aw_dropWire$whas, + cache_master_xactor_ug_master_u_b_putWire$whas, + cache_master_xactor_ug_master_u_r_putWire$whas, + cache_master_xactor_ug_master_u_w_dropWire$whas; + + // register cache_cfg_verbosity + reg [3 : 0] cache_cfg_verbosity; + wire [3 : 0] cache_cfg_verbosity$D_IN; + wire cache_cfg_verbosity$EN; + + // register cache_crg_sb_to_load_delay + reg [10 : 0] cache_crg_sb_to_load_delay; + wire [10 : 0] cache_crg_sb_to_load_delay$D_IN; + wire cache_crg_sb_to_load_delay$EN; + + // register cache_ctr_wr_rsps_pending_crg + reg [3 : 0] cache_ctr_wr_rsps_pending_crg; + wire [3 : 0] cache_ctr_wr_rsps_pending_crg$D_IN; + wire cache_ctr_wr_rsps_pending_crg$EN; + + // register cache_master_xactor_clearing + reg cache_master_xactor_clearing; + wire cache_master_xactor_clearing$D_IN, cache_master_xactor_clearing$EN; + + // register cache_master_xactor_shim_arff_rv + reg [97 : 0] cache_master_xactor_shim_arff_rv; + wire [97 : 0] cache_master_xactor_shim_arff_rv$D_IN; + wire cache_master_xactor_shim_arff_rv$EN; + + // register cache_master_xactor_shim_awff_rv + reg [97 : 0] cache_master_xactor_shim_awff_rv; + wire [97 : 0] cache_master_xactor_shim_awff_rv$D_IN; + wire cache_master_xactor_shim_awff_rv$EN; + + // register cache_master_xactor_shim_bff_rv + reg [6 : 0] cache_master_xactor_shim_bff_rv; + wire [6 : 0] cache_master_xactor_shim_bff_rv$D_IN; + wire cache_master_xactor_shim_bff_rv$EN; + + // register cache_master_xactor_shim_rff_rv + reg [71 : 0] cache_master_xactor_shim_rff_rv; + wire [71 : 0] cache_master_xactor_shim_rff_rv$D_IN; + wire cache_master_xactor_shim_rff_rv$EN; + + // register cache_master_xactor_shim_wff_rv + reg [73 : 0] cache_master_xactor_shim_wff_rv; + wire [73 : 0] cache_master_xactor_shim_wff_rv$D_IN; + wire cache_master_xactor_shim_wff_rv$EN; + + // register cache_rg_addr + reg [31 : 0] cache_rg_addr; + wire [31 : 0] cache_rg_addr$D_IN; + wire cache_rg_addr$EN; + + // register cache_rg_amo_funct7 + reg [6 : 0] cache_rg_amo_funct7; + wire [6 : 0] cache_rg_amo_funct7$D_IN; + wire cache_rg_amo_funct7$EN; + + // register cache_rg_cset_in_cache + reg [6 : 0] cache_rg_cset_in_cache; + wire [6 : 0] cache_rg_cset_in_cache$D_IN; + wire cache_rg_cset_in_cache$EN; + + // register cache_rg_error_during_refill + reg cache_rg_error_during_refill; + wire cache_rg_error_during_refill$D_IN, cache_rg_error_during_refill$EN; + + // register cache_rg_exc_code + reg [3 : 0] cache_rg_exc_code; + reg [3 : 0] cache_rg_exc_code$D_IN; + wire cache_rg_exc_code$EN; + + // register cache_rg_f3 + reg [2 : 0] cache_rg_f3; + wire [2 : 0] cache_rg_f3$D_IN; + wire cache_rg_f3$EN; + + // register cache_rg_ld_val + reg [63 : 0] cache_rg_ld_val; + reg [63 : 0] cache_rg_ld_val$D_IN; + wire cache_rg_ld_val$EN; + + // register cache_rg_lower_word32 + reg [31 : 0] cache_rg_lower_word32; + wire [31 : 0] cache_rg_lower_word32$D_IN; + wire cache_rg_lower_word32$EN; + + // register cache_rg_lower_word32_full + reg cache_rg_lower_word32_full; + wire cache_rg_lower_word32_full$D_IN, cache_rg_lower_word32_full$EN; + + // register cache_rg_lrsc_pa + reg [31 : 0] cache_rg_lrsc_pa; + wire [31 : 0] cache_rg_lrsc_pa$D_IN; + wire cache_rg_lrsc_pa$EN; + + // register cache_rg_lrsc_valid + reg cache_rg_lrsc_valid; + wire cache_rg_lrsc_valid$D_IN, cache_rg_lrsc_valid$EN; + + // register cache_rg_op + reg [1 : 0] cache_rg_op; + wire [1 : 0] cache_rg_op$D_IN; + wire cache_rg_op$EN; + + // register cache_rg_pa + reg [31 : 0] cache_rg_pa; + wire [31 : 0] cache_rg_pa$D_IN; + wire cache_rg_pa$EN; + + // register cache_rg_pte_pa + reg [31 : 0] cache_rg_pte_pa; + wire [31 : 0] cache_rg_pte_pa$D_IN; + wire cache_rg_pte_pa$EN; + + // register cache_rg_st_amo_val + reg [63 : 0] cache_rg_st_amo_val; + wire [63 : 0] cache_rg_st_amo_val$D_IN; + wire cache_rg_st_amo_val$EN; + + // register cache_rg_state + reg [3 : 0] cache_rg_state; + reg [3 : 0] cache_rg_state$D_IN; + wire cache_rg_state$EN; + + // register cache_rg_word64_set_in_cache + reg [8 : 0] cache_rg_word64_set_in_cache; + wire [8 : 0] cache_rg_word64_set_in_cache$D_IN; + wire cache_rg_word64_set_in_cache$EN; + + // ports of submodule cache_f_fabric_write_reqs + reg [98 : 0] cache_f_fabric_write_reqs$D_IN; + wire [98 : 0] cache_f_fabric_write_reqs$D_OUT; + wire cache_f_fabric_write_reqs$CLR, + cache_f_fabric_write_reqs$DEQ, + cache_f_fabric_write_reqs$EMPTY_N, + cache_f_fabric_write_reqs$ENQ, + cache_f_fabric_write_reqs$FULL_N; + + // ports of submodule cache_f_reset_reqs + wire cache_f_reset_reqs$CLR, + cache_f_reset_reqs$DEQ, + cache_f_reset_reqs$D_IN, + cache_f_reset_reqs$D_OUT, + cache_f_reset_reqs$EMPTY_N, + cache_f_reset_reqs$ENQ, + cache_f_reset_reqs$FULL_N; + + // ports of submodule cache_f_reset_rsps + wire cache_f_reset_rsps$CLR, + cache_f_reset_rsps$DEQ, + cache_f_reset_rsps$D_IN, + cache_f_reset_rsps$D_OUT, + cache_f_reset_rsps$EMPTY_N, + cache_f_reset_rsps$ENQ, + cache_f_reset_rsps$FULL_N; + + // ports of submodule cache_ram_state_and_ctag_cset + wire [22 : 0] cache_ram_state_and_ctag_cset$DIA, + cache_ram_state_and_ctag_cset$DIB, + cache_ram_state_and_ctag_cset$DOB; + wire [6 : 0] cache_ram_state_and_ctag_cset$ADDRA, + cache_ram_state_and_ctag_cset$ADDRB; + wire cache_ram_state_and_ctag_cset$ENA, + cache_ram_state_and_ctag_cset$ENB, + cache_ram_state_and_ctag_cset$WEA, + cache_ram_state_and_ctag_cset$WEB; + + // ports of submodule cache_ram_word64_set + reg [63 : 0] cache_ram_word64_set$DIB; + reg [8 : 0] cache_ram_word64_set$ADDRB; + wire [63 : 0] cache_ram_word64_set$DIA, cache_ram_word64_set$DOB; + wire [8 : 0] cache_ram_word64_set$ADDRA; + wire cache_ram_word64_set$ENA, + cache_ram_word64_set$ENB, + cache_ram_word64_set$WEA, + cache_ram_word64_set$WEB; + + // ports of submodule cache_soc_map + wire [63 : 0] cache_soc_map$m_is_IO_addr_addr, + cache_soc_map$m_is_mem_addr_addr, + cache_soc_map$m_is_near_mem_IO_addr_addr; + wire cache_soc_map$m_is_mem_addr; + + // rule scheduling signals + wire CAN_FIRE_RL_cache_master_xactor_do_clear, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_cache_rl_ST_AMO_response, + CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop, + CAN_FIRE_RL_cache_rl_discard_write_rsp, + CAN_FIRE_RL_cache_rl_drive_exception_rsp, + CAN_FIRE_RL_cache_rl_fabric_send_write_req, + CAN_FIRE_RL_cache_rl_io_AMO_SC_req, + CAN_FIRE_RL_cache_rl_io_AMO_op_req, + CAN_FIRE_RL_cache_rl_io_AMO_read_rsp, + CAN_FIRE_RL_cache_rl_io_read_req, + CAN_FIRE_RL_cache_rl_io_read_rsp, + CAN_FIRE_RL_cache_rl_io_write_req, + CAN_FIRE_RL_cache_rl_maintain_io_read_rsp, + CAN_FIRE_RL_cache_rl_probe_and_immed_rsp, + CAN_FIRE_RL_cache_rl_rereq, + CAN_FIRE_RL_cache_rl_reset, + CAN_FIRE_RL_cache_rl_shift_sb_to_load_delay, + CAN_FIRE_RL_cache_rl_start_cache_refill, + CAN_FIRE_RL_cache_rl_start_reset, + CAN_FIRE_mem_master_ar_arready, + CAN_FIRE_mem_master_aw_awready, + CAN_FIRE_mem_master_b_bflit, + CAN_FIRE_mem_master_r_rflit, + CAN_FIRE_mem_master_w_wready, + CAN_FIRE_req, + CAN_FIRE_server_flush_request_put, + CAN_FIRE_server_flush_response_get, + CAN_FIRE_server_reset_request_put, + CAN_FIRE_server_reset_response_get, + CAN_FIRE_set_verbosity, + CAN_FIRE_tlb_flush, + WILL_FIRE_RL_cache_master_xactor_do_clear, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_cache_rl_ST_AMO_response, + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop, + WILL_FIRE_RL_cache_rl_discard_write_rsp, + WILL_FIRE_RL_cache_rl_drive_exception_rsp, + WILL_FIRE_RL_cache_rl_fabric_send_write_req, + WILL_FIRE_RL_cache_rl_io_AMO_SC_req, + WILL_FIRE_RL_cache_rl_io_AMO_op_req, + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp, + WILL_FIRE_RL_cache_rl_io_read_req, + WILL_FIRE_RL_cache_rl_io_read_rsp, + WILL_FIRE_RL_cache_rl_io_write_req, + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp, + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp, + WILL_FIRE_RL_cache_rl_rereq, + WILL_FIRE_RL_cache_rl_reset, + WILL_FIRE_RL_cache_rl_shift_sb_to_load_delay, + WILL_FIRE_RL_cache_rl_start_cache_refill, + WILL_FIRE_RL_cache_rl_start_reset, + WILL_FIRE_mem_master_ar_arready, + WILL_FIRE_mem_master_aw_awready, + WILL_FIRE_mem_master_b_bflit, + WILL_FIRE_mem_master_r_rflit, + WILL_FIRE_mem_master_w_wready, + WILL_FIRE_req, + WILL_FIRE_server_flush_request_put, + WILL_FIRE_server_flush_response_get, + WILL_FIRE_server_reset_request_put, + WILL_FIRE_server_reset_response_get, + WILL_FIRE_set_verbosity, + WILL_FIRE_tlb_flush; + + // inputs to muxes for submodule ports + reg [63 : 0] MUX_cache_dw_output_ld_val$wset_1__VAL_1, + MUX_cache_dw_output_ld_val$wset_1__VAL_2; + wire [98 : 0] MUX_cache_f_fabric_write_reqs$enq_1__VAL_1, + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2, + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3; + wire [97 : 0] MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1, + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2; + wire [63 : 0] MUX_cache_dw_output_ld_val$wset_1__VAL_3, + MUX_cache_ram_word64_set$a_put_3__VAL_2, + MUX_cache_rg_ld_val$write_1__VAL_2, + MUX_cache_rg_st_amo_val$write_1__VAL_2; + wire [22 : 0] MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1; + wire [8 : 0] MUX_cache_ram_word64_set$b_put_2__VAL_2, + MUX_cache_ram_word64_set$b_put_2__VAL_4; + wire [6 : 0] MUX_cache_rg_cset_in_cache$write_1__VAL_1; + wire [3 : 0] MUX_cache_rg_exc_code$write_1__VAL_1, + MUX_cache_rg_exc_code$write_1__VAL_4, + MUX_cache_rg_state$write_1__VAL_1, + MUX_cache_rg_state$write_1__VAL_12, + MUX_cache_rg_state$write_1__VAL_2, + MUX_cache_rg_state$write_1__VAL_4; + wire MUX_cache_dw_output_ld_val$wset_1__SEL_1, + MUX_cache_dw_output_ld_val$wset_1__SEL_2, + MUX_cache_dw_output_ld_val$wset_1__SEL_3, + MUX_cache_dw_output_ld_val$wset_1__SEL_4, + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2, + MUX_cache_master_xactor_clearing$write_1__SEL_2, + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1, + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1, + MUX_cache_ram_word64_set$a_put_1__SEL_1, + MUX_cache_ram_word64_set$b_put_1__SEL_2, + MUX_cache_rg_error_during_refill$write_1__SEL_1, + MUX_cache_rg_exc_code$write_1__SEL_1, + MUX_cache_rg_exc_code$write_1__SEL_2, + MUX_cache_rg_exc_code$write_1__SEL_3, + MUX_cache_rg_ld_val$write_1__SEL_2, + MUX_cache_rg_lrsc_valid$write_1__SEL_2, + MUX_cache_rg_lrsc_valid$write_1__VAL_2, + MUX_cache_rg_state$write_1__SEL_12, + MUX_cache_rg_state$write_1__SEL_13, + MUX_cache_rg_state$write_1__SEL_4; + + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h5604; + reg [31 : 0] v__h6425; + reg [31 : 0] v__h6526; + reg [31 : 0] v__h6977; + reg [31 : 0] v__h15442; + reg [31 : 0] v__h19086; + reg [31 : 0] v__h22330; + reg [31 : 0] v__h25145; + reg [31 : 0] v__h26849; + reg [31 : 0] v__h26929; + reg [31 : 0] v__h27139; + reg [31 : 0] v__h27257; + reg [31 : 0] v__h30743; + reg [31 : 0] v__h30704; + reg [31 : 0] v__h6060; + reg [31 : 0] v__h23274; + reg [31 : 0] v__h23536; + reg [31 : 0] v__h25517; + reg [31 : 0] v__h26635; + reg [31 : 0] v__h26742; + reg [31 : 0] v__h27573; + reg [31 : 0] v__h27768; + reg [31 : 0] v__h30027; + reg [31 : 0] v__h27864; + reg [31 : 0] v__h31126; + reg [31 : 0] v__h5598; + reg [31 : 0] v__h6054; + reg [31 : 0] v__h6419; + reg [31 : 0] v__h6520; + reg [31 : 0] v__h6971; + reg [31 : 0] v__h15436; + reg [31 : 0] v__h19080; + reg [31 : 0] v__h22324; + reg [31 : 0] v__h23268; + reg [31 : 0] v__h23530; + reg [31 : 0] v__h25139; + reg [31 : 0] v__h25511; + reg [31 : 0] v__h26629; + reg [31 : 0] v__h26736; + reg [31 : 0] v__h26843; + reg [31 : 0] v__h26923; + reg [31 : 0] v__h27133; + reg [31 : 0] v__h27251; + reg [31 : 0] v__h27567; + reg [31 : 0] v__h27762; + reg [31 : 0] v__h27858; + reg [31 : 0] v__h30021; + reg [31 : 0] v__h30698; + reg [31 : 0] v__h30737; + reg [31 : 0] v__h31120; + // synopsys translate_on + + // remaining internal signals + reg [63 : 0] CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851, + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443, + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517, + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385, + _theResult_____2__h19586, + _theResult_____2__h27940, + mem_req_wr_data_wdata__h5352, + new_value__h18177, + new_value__h8148, + w1__h19578, + w1__h27928, + w1__h27932; + reg [7 : 0] mem_req_wr_data_wstrb__h5353; + reg [2 : 0] _theResult___snd_snd_val__h5236, size_val__h27412; + wire [96 : 0] cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35, + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1; + wire [72 : 0] cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q16; + wire [63 : 0] IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d354, + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852, + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449, + IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d531, + _theResult___fst__h5221, + cline_fabric_addr__h22383, + fabric_addr__h27309, + ld_val__h25642, + mem_req_wr_addr_awaddr__h5054, + new_ld_val__h27894, + new_st_val__h19308, + new_st_val__h19590, + new_st_val__h19681, + new_st_val__h20661, + new_st_val__h20665, + new_st_val__h20669, + new_st_val__h20673, + new_st_val__h20678, + new_st_val__h20684, + new_st_val__h20689, + new_st_val__h27944, + new_st_val__h28035, + new_st_val__h29895, + new_st_val__h29899, + new_st_val__h29903, + new_st_val__h29907, + new_st_val__h29912, + new_st_val__h29918, + new_st_val__h29923, + result__h14559, + result__h14587, + result__h14615, + result__h14643, + result__h14671, + result__h14699, + result__h14727, + result__h14772, + result__h14800, + result__h14828, + result__h14856, + result__h14884, + result__h14912, + result__h14940, + result__h14968, + result__h15013, + result__h15041, + result__h15069, + result__h15097, + result__h15138, + result__h15166, + result__h15194, + result__h15222, + result__h15263, + result__h15291, + result__h15330, + result__h15358, + result__h25702, + result__h25732, + result__h25759, + result__h25786, + result__h25813, + result__h25840, + result__h25867, + result__h25894, + result__h25938, + result__h25965, + result__h25992, + result__h26019, + result__h26046, + result__h26073, + result__h26100, + result__h26127, + result__h26171, + result__h26198, + result__h26225, + result__h26252, + result__h26292, + result__h26319, + result__h26346, + result__h26373, + result__h26413, + result__h26440, + result__h26478, + result__h26505, + result__h28123, + result__h29031, + result__h29059, + result__h29087, + result__h29115, + result__h29143, + result__h29171, + result__h29199, + result__h29244, + result__h29272, + result__h29300, + result__h29328, + result__h29356, + result__h29384, + result__h29412, + result__h29440, + result__h29485, + result__h29513, + result__h29541, + result__h29569, + result__h29610, + result__h29638, + result__h29666, + result__h29694, + result__h29735, + result__h29763, + result__h29802, + result__h29830, + result__h8203, + w1___1__h19649, + w1___1__h28003, + w2___1__h28004, + w2__h27934, + word64__h7969, + x__h15829, + x__h27923, + y__h8239; + wire [31 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q11, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q4, + cache_rg_st_amo_val_BITS_31_TO_0__q33, + cline_addr__h22382, + ld_val5642_BITS_31_TO_0__q40, + ld_val5642_BITS_63_TO_32__q47, + new_value148_BITS_31_TO_0__q32, + w17928_BITS_31_TO_0__q53, + word64969_BITS_31_TO_0__q19, + word64969_BITS_63_TO_32__q26; + wire [21 : 0] pa_ctag__h7827; + wire [15 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q10, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q14, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q3, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q7, + ld_val5642_BITS_15_TO_0__q39, + ld_val5642_BITS_31_TO_16__q43, + ld_val5642_BITS_47_TO_32__q46, + ld_val5642_BITS_63_TO_48__q50, + word64969_BITS_15_TO_0__q18, + word64969_BITS_31_TO_16__q22, + word64969_BITS_47_TO_32__q25, + word64969_BITS_63_TO_48__q29; + wire [7 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q12, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q13, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q15, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q2, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q5, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q6, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q8, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q9, + ld_val5642_BITS_15_TO_8__q41, + ld_val5642_BITS_23_TO_16__q42, + ld_val5642_BITS_31_TO_24__q44, + ld_val5642_BITS_39_TO_32__q45, + ld_val5642_BITS_47_TO_40__q48, + ld_val5642_BITS_55_TO_48__q49, + ld_val5642_BITS_63_TO_56__q51, + ld_val5642_BITS_7_TO_0__q38, + strobe64__h5219, + strobe64__h5223, + strobe64__h5227, + word64969_BITS_15_TO_8__q20, + word64969_BITS_23_TO_16__q21, + word64969_BITS_31_TO_24__q23, + word64969_BITS_39_TO_32__q24, + word64969_BITS_47_TO_40__q27, + word64969_BITS_55_TO_48__q28, + word64969_BITS_63_TO_56__q30, + word64969_BITS_7_TO_0__q17; + wire [5 : 0] shift_bits__h5069; + wire [3 : 0] IF_cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_ETC___d196, + IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d195, + access_exc_code__h4779, + b__h22284; + wire IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d164, + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91, + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603, + NOT_cache_ram_state_and_ctag_cset_b_read__54_B_ETC___d202, + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d191, + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d529, + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549, + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d557, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d211, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d389, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d523, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d565, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d568, + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d572, + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d387, + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d521, + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d547, + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d551, + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d555, + NOT_req_f3_BITS_1_TO_0_44_EQ_0b0_45_46_AND_NOT_ETC___d965, + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160, + cache_ram_state_and_ctag_cset_b_read__54_BIT_2_ETC___d203, + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200, + cache_rg_amo_funct7_36_BITS_6_TO_2_37_EQ_0b10__ETC___d375, + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148, + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d186, + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d214, + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d219, + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d358, + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d371, + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d212, + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d390, + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d524, + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d527, + cache_rg_op_33_EQ_2_35_AND_cache_rg_amo_funct7_ETC___d561, + cache_rg_state_7_EQ_12_46_AND_cache_rg_op_33_E_ETC___d648, + cache_rg_state_7_EQ_3_67_AND_NOT_cache_rg_op_3_ETC___d176, + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d381, + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d392, + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570, + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d576, + lrsc_result__h15819, + req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974; + + // action method set_verbosity + assign RDY_set_verbosity = 1'd1 ; + assign CAN_FIRE_set_verbosity = 1'd1 ; + assign WILL_FIRE_set_verbosity = EN_set_verbosity ; + + // action method server_reset_request_put + assign RDY_server_reset_request_put = cache_f_reset_reqs$FULL_N ; + assign CAN_FIRE_server_reset_request_put = cache_f_reset_reqs$FULL_N ; + assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; + + // action method server_reset_response_get + assign RDY_server_reset_response_get = + !cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign CAN_FIRE_server_reset_response_get = + !cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; + + // action method req + assign CAN_FIRE_req = 1'd1 ; + assign WILL_FIRE_req = EN_req ; + + // value method valid + assign valid = cache_dw_valid$whas ; + + // value method addr + assign addr = cache_rg_addr ; + + // value method word64 + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_1 or + MUX_cache_dw_output_ld_val$wset_1__VAL_1 or + MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + MUX_cache_dw_output_ld_val$wset_1__VAL_2 or + MUX_cache_dw_output_ld_val$wset_1__SEL_3 or + MUX_cache_dw_output_ld_val$wset_1__VAL_3 or + MUX_cache_dw_output_ld_val$wset_1__SEL_4 or cache_rg_ld_val) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_1: + word64 = MUX_cache_dw_output_ld_val$wset_1__VAL_1; + MUX_cache_dw_output_ld_val$wset_1__SEL_2: + word64 = MUX_cache_dw_output_ld_val$wset_1__VAL_2; + MUX_cache_dw_output_ld_val$wset_1__SEL_3: + word64 = MUX_cache_dw_output_ld_val$wset_1__VAL_3; + MUX_cache_dw_output_ld_val$wset_1__SEL_4: word64 = cache_rg_ld_val; + default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // value method st_amo_val + assign st_amo_val = + MUX_cache_dw_output_ld_val$wset_1__SEL_3 ? + 64'd0 : + cache_rg_st_amo_val ; + + // value method exc + assign exc = cache_rg_state == 4'd4 ; + + // value method exc_code + assign exc_code = cache_rg_exc_code ; + + // action method server_flush_request_put + assign RDY_server_flush_request_put = cache_f_reset_reqs$FULL_N ; + assign CAN_FIRE_server_flush_request_put = cache_f_reset_reqs$FULL_N ; + assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; + + // action method server_flush_response_get + assign RDY_server_flush_response_get = + cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign CAN_FIRE_server_flush_response_get = + cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; + + // action method tlb_flush + assign RDY_tlb_flush = 1'd1 ; + assign CAN_FIRE_tlb_flush = 1'd1 ; + assign WILL_FIRE_tlb_flush = EN_tlb_flush ; + + // value method mem_master_aw_awid + assign mem_master_awid = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[96:93] ; + + // value method mem_master_aw_awaddr + assign mem_master_awaddr = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[92:29] ; + + // value method mem_master_aw_awlen + assign mem_master_awlen = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[28:21] ; + + // value method mem_master_aw_awsize + assign mem_master_awsize = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[20:18] ; + + // value method mem_master_aw_awburst + assign mem_master_awburst = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[17:16] ; + + // value method mem_master_aw_awlock + assign mem_master_awlock = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[15] ; + + // value method mem_master_aw_awcache + assign mem_master_awcache = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[14:11] ; + + // value method mem_master_aw_awprot + assign mem_master_awprot = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[10:8] ; + + // value method mem_master_aw_awqos + assign mem_master_awqos = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[7:4] ; + + // value method mem_master_aw_awregion + assign mem_master_awregion = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1[3:0] ; + + // value method mem_master_aw_awvalid + assign mem_master_awvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek ; + + // action method mem_master_aw_awready + assign CAN_FIRE_mem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_mem_master_aw_awready = 1'd1 ; + + // value method mem_master_w_wdata + assign mem_master_wdata = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q16[72:9] ; + + // value method mem_master_w_wstrb + assign mem_master_wstrb = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q16[8:1] ; + + // value method mem_master_w_wlast + assign mem_master_wlast = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q16[0] ; + + // value method mem_master_w_wvalid + assign mem_master_wvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek ; + + // action method mem_master_w_wready + assign CAN_FIRE_mem_master_w_wready = 1'd1 ; + assign WILL_FIRE_mem_master_w_wready = 1'd1 ; + + // action method mem_master_b_bflit + assign CAN_FIRE_mem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_mem_master_b_bflit = mem_master_bvalid ; + + // value method mem_master_b_bready + assign mem_master_bready = !cache_master_xactor_shim_bff_rv[6] ; + + // value method mem_master_ar_arid + assign mem_master_arid = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[96:93] ; + + // value method mem_master_ar_araddr + assign mem_master_araddr = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[92:29] ; + + // value method mem_master_ar_arlen + assign mem_master_arlen = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[28:21] ; + + // value method mem_master_ar_arsize + assign mem_master_arsize = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[20:18] ; + + // value method mem_master_ar_arburst + assign mem_master_arburst = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[17:16] ; + + // value method mem_master_ar_arlock + assign mem_master_arlock = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[15] ; + + // value method mem_master_ar_arcache + assign mem_master_arcache = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[14:11] ; + + // value method mem_master_ar_arprot + assign mem_master_arprot = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[10:8] ; + + // value method mem_master_ar_arqos + assign mem_master_arqos = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[7:4] ; + + // value method mem_master_ar_arregion + assign mem_master_arregion = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35[3:0] ; + + // value method mem_master_ar_arvalid + assign mem_master_arvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek ; + + // action method mem_master_ar_arready + assign CAN_FIRE_mem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_mem_master_ar_arready = 1'd1 ; + + // action method mem_master_r_rflit + assign CAN_FIRE_mem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_mem_master_r_rflit = mem_master_rvalid ; + + // value method mem_master_r_rready + assign mem_master_rready = !cache_master_xactor_shim_rff_rv[71] ; + + // submodule cache_f_fabric_write_reqs + FIFO2 #(.width(32'd99), + .guarded(32'd1)) cache_f_fabric_write_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_fabric_write_reqs$D_IN), + .ENQ(cache_f_fabric_write_reqs$ENQ), + .DEQ(cache_f_fabric_write_reqs$DEQ), + .CLR(cache_f_fabric_write_reqs$CLR), + .D_OUT(cache_f_fabric_write_reqs$D_OUT), + .FULL_N(cache_f_fabric_write_reqs$FULL_N), + .EMPTY_N(cache_f_fabric_write_reqs$EMPTY_N)); + + // submodule cache_f_reset_reqs + FIFO2 #(.width(32'd1), .guarded(32'd1)) cache_f_reset_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_reset_reqs$D_IN), + .ENQ(cache_f_reset_reqs$ENQ), + .DEQ(cache_f_reset_reqs$DEQ), + .CLR(cache_f_reset_reqs$CLR), + .D_OUT(cache_f_reset_reqs$D_OUT), + .FULL_N(cache_f_reset_reqs$FULL_N), + .EMPTY_N(cache_f_reset_reqs$EMPTY_N)); + + // submodule cache_f_reset_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) cache_f_reset_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_reset_rsps$D_IN), + .ENQ(cache_f_reset_rsps$ENQ), + .DEQ(cache_f_reset_rsps$DEQ), + .CLR(cache_f_reset_rsps$CLR), + .D_OUT(cache_f_reset_rsps$D_OUT), + .FULL_N(cache_f_reset_rsps$FULL_N), + .EMPTY_N(cache_f_reset_rsps$EMPTY_N)); + + // submodule cache_ram_state_and_ctag_cset + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd7), + .DATA_WIDTH(32'd23), + .MEMSIZE(8'd128)) cache_ram_state_and_ctag_cset(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(cache_ram_state_and_ctag_cset$ADDRA), + .ADDRB(cache_ram_state_and_ctag_cset$ADDRB), + .DIA(cache_ram_state_and_ctag_cset$DIA), + .DIB(cache_ram_state_and_ctag_cset$DIB), + .WEA(cache_ram_state_and_ctag_cset$WEA), + .WEB(cache_ram_state_and_ctag_cset$WEB), + .ENA(cache_ram_state_and_ctag_cset$ENA), + .ENB(cache_ram_state_and_ctag_cset$ENB), + .DOA(), + .DOB(cache_ram_state_and_ctag_cset$DOB)); + + // submodule cache_ram_word64_set + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd9), + .DATA_WIDTH(32'd64), + .MEMSIZE(10'd512)) cache_ram_word64_set(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(cache_ram_word64_set$ADDRA), + .ADDRB(cache_ram_word64_set$ADDRB), + .DIA(cache_ram_word64_set$DIA), + .DIB(cache_ram_word64_set$DIB), + .WEA(cache_ram_word64_set$WEA), + .WEB(cache_ram_word64_set$WEB), + .ENA(cache_ram_word64_set$ENA), + .ENB(cache_ram_word64_set$ENB), + .DOA(), + .DOB(cache_ram_word64_set$DOB)); + + // submodule cache_soc_map + mkSoC_Map cache_soc_map(.CLK(CLK), + .RST_N(RST_N), + .m_is_IO_addr_addr(cache_soc_map$m_is_IO_addr_addr), + .m_is_mem_addr_addr(cache_soc_map$m_is_mem_addr_addr), + .m_is_near_mem_IO_addr_addr(cache_soc_map$m_is_near_mem_IO_addr_addr), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), + .m_is_mem_addr(cache_soc_map$m_is_mem_addr), + .m_is_IO_addr(), + .m_is_near_mem_IO_addr(), + .m_pc_reset_value(), + .m_mtvec_reset_value(), + .m_nmivec_reset_value()); + + // rule RL_cache_rl_fabric_send_write_req + assign CAN_FIRE_RL_cache_rl_fabric_send_write_req = + !cache_master_xactor_clearing && + cache_f_fabric_write_reqs$EMPTY_N && + !cache_master_xactor_shim_awff_rv[97] && + !cache_master_xactor_shim_wff_rv[73] ; + assign WILL_FIRE_RL_cache_rl_fabric_send_write_req = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ; + + // rule RL_cache_rl_reset + assign CAN_FIRE_RL_cache_rl_reset = + (cache_rg_cset_in_cache != 7'd127 || + cache_f_reset_reqs$EMPTY_N && cache_f_reset_rsps$FULL_N) && + cache_rg_state == 4'd1 ; + assign WILL_FIRE_RL_cache_rl_reset = CAN_FIRE_RL_cache_rl_reset ; + + // rule RL_cache_rl_shift_sb_to_load_delay + assign CAN_FIRE_RL_cache_rl_shift_sb_to_load_delay = 1'd1 ; + assign WILL_FIRE_RL_cache_rl_shift_sb_to_load_delay = 1'd1 ; + + // rule RL_cache_rl_probe_and_immed_rsp + assign CAN_FIRE_RL_cache_rl_probe_and_immed_rsp = + (!cache_soc_map$m_is_mem_addr || cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010 || + IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d164) && + cache_rg_state_7_EQ_3_67_AND_NOT_cache_rg_op_3_ETC___d176 ; + assign WILL_FIRE_RL_cache_rl_probe_and_immed_rsp = + CAN_FIRE_RL_cache_rl_probe_and_immed_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_start_cache_refill + assign CAN_FIRE_RL_cache_rl_start_cache_refill = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[97] && + cache_rg_state == 4'd8 && + b__h22284 == 4'd0 ; + assign WILL_FIRE_RL_cache_rl_start_cache_refill = + CAN_FIRE_RL_cache_rl_start_cache_refill && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_rereq + assign CAN_FIRE_RL_cache_rl_rereq = cache_rg_state == 4'd10 ; + assign WILL_FIRE_RL_cache_rl_rereq = + CAN_FIRE_RL_cache_rl_rereq && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_ST_AMO_response + assign CAN_FIRE_RL_cache_rl_ST_AMO_response = cache_rg_state == 4'd11 ; + assign WILL_FIRE_RL_cache_rl_ST_AMO_response = + CAN_FIRE_RL_cache_rl_ST_AMO_response ; + + // rule RL_cache_rl_io_read_req + assign CAN_FIRE_RL_cache_rl_io_read_req = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[97] && + cache_rg_state_7_EQ_12_46_AND_cache_rg_op_33_E_ETC___d648 ; + assign WILL_FIRE_RL_cache_rl_io_read_req = + CAN_FIRE_RL_cache_rl_io_read_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_maintain_io_read_rsp + assign CAN_FIRE_RL_cache_rl_maintain_io_read_rsp = cache_rg_state == 4'd14 ; + assign WILL_FIRE_RL_cache_rl_maintain_io_read_rsp = + CAN_FIRE_RL_cache_rl_maintain_io_read_rsp ; + + // rule RL_cache_rl_io_write_req + assign CAN_FIRE_RL_cache_rl_io_write_req = + cache_f_fabric_write_reqs$FULL_N && cache_rg_state == 4'd12 && + cache_rg_op == 2'd1 ; + assign WILL_FIRE_RL_cache_rl_io_write_req = + CAN_FIRE_RL_cache_rl_io_write_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_SC_req + assign CAN_FIRE_RL_cache_rl_io_AMO_SC_req = + cache_rg_state == 4'd12 && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_SC_req = + CAN_FIRE_RL_cache_rl_io_AMO_SC_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_op_req + assign CAN_FIRE_RL_cache_rl_io_AMO_op_req = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[97] && + cache_rg_state == 4'd12 && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] != 5'b00010 && + cache_rg_amo_funct7[6:2] != 5'b00011 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_op_req = + CAN_FIRE_RL_cache_rl_io_AMO_op_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_drive_exception_rsp + assign CAN_FIRE_RL_cache_rl_drive_exception_rsp = cache_rg_state == 4'd4 ; + assign WILL_FIRE_RL_cache_rl_drive_exception_rsp = cache_rg_state == 4'd4 ; + + // rule RL_cache_master_xactor_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek = + cache_master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop = + cache_master_xactor_ug_master_u_aw_dropWire$whas && + !cache_master_xactor_shim_awff_rv$port1__read[97] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop = + cache_master_xactor_shim_awff_rv$port1__read[97] && + cache_master_xactor_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_w_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek = + cache_master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop = + cache_master_xactor_ug_master_u_w_dropWire$whas && + !cache_master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_w_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop = + cache_master_xactor_shim_wff_rv$port1__read[73] && + cache_master_xactor_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut = + cache_master_xactor_ug_master_u_b_putWire$whas && + cache_master_xactor_shim_bff_rv[6] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut ; + + // rule RL_cache_master_xactor_ug_master_u_b_doPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut = + !cache_master_xactor_shim_bff_rv[6] && + cache_master_xactor_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut ; + + // rule RL_cache_rl_discard_write_rsp + assign CAN_FIRE_RL_cache_rl_discard_write_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_bff_rv$port1__read[6] && + b__h22284 != 4'd0 ; + assign WILL_FIRE_RL_cache_rl_discard_write_rsp = + CAN_FIRE_RL_cache_rl_discard_write_rsp ; + + // rule RL_cache_rl_start_reset + assign CAN_FIRE_RL_cache_rl_start_reset = + cache_f_reset_reqs$EMPTY_N && + (cache_f_reset_reqs$D_OUT || !cache_master_xactor_clearing) && + cache_rg_state != 4'd1 ; + assign WILL_FIRE_RL_cache_rl_start_reset = + CAN_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_master_xactor_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek = + cache_master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop = + cache_master_xactor_ug_master_u_ar_dropWire$whas && + !cache_master_xactor_shim_arff_rv$port1__read[97] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop = + cache_master_xactor_shim_arff_rv$port1__read[97] && + cache_master_xactor_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut = + cache_master_xactor_ug_master_u_r_putWire$whas && + cache_master_xactor_shim_rff_rv[71] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut ; + + // rule RL_cache_master_xactor_ug_master_u_r_doPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut = + !cache_master_xactor_shim_rff_rv[71] && + cache_master_xactor_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut ; + + // rule RL_cache_rl_cache_refill_rsps_loop + assign CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[71] && + cache_rg_state == 4'd9 ; + assign WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop = + CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_io_read_rsp + assign CAN_FIRE_RL_cache_rl_io_read_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[71] && + cache_rg_state == 4'd13 ; + assign WILL_FIRE_RL_cache_rl_io_read_rsp = + CAN_FIRE_RL_cache_rl_io_read_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_read_rsp + assign CAN_FIRE_RL_cache_rl_io_AMO_read_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[71] && + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_f_fabric_write_reqs$FULL_N) && + cache_rg_state == 4'd15 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_read_rsp = + CAN_FIRE_RL_cache_rl_io_AMO_read_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_master_xactor_do_clear + assign CAN_FIRE_RL_cache_master_xactor_do_clear = + cache_master_xactor_clearing ; + assign WILL_FIRE_RL_cache_master_xactor_do_clear = + cache_master_xactor_clearing ; + + // inputs to muxes for submodule ports + assign MUX_cache_dw_output_ld_val$wset_1__SEL_1 = + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_2 = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_3 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d219 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_4 = + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp || + WILL_FIRE_RL_cache_rl_ST_AMO_response ; + assign MUX_cache_f_fabric_write_reqs$enq_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d529 ; + assign MUX_cache_master_xactor_clearing$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_start_reset && !cache_f_reset_reqs$D_OUT ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1 = + WILL_FIRE_RL_cache_rl_io_AMO_op_req || + WILL_FIRE_RL_cache_rl_io_read_req ; + assign MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 = + EN_req && + req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974 ; + assign MUX_cache_ram_word64_set$a_put_1__SEL_1 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_ram_word64_set$b_put_1__SEL_2 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 ; + assign MUX_cache_rg_error_during_refill$write_1__SEL_1 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_exc_code$write_1__SEL_1 = + EN_req && + NOT_req_f3_BITS_1_TO_0_44_EQ_0b0_45_46_AND_NOT_ETC___d965 ; + assign MUX_cache_rg_exc_code$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_exc_code$write_1__SEL_3 = + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_ld_val$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d381 ; + assign MUX_cache_rg_lrsc_valid$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d214 ; + assign MUX_cache_rg_state$write_1__SEL_4 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 ; + assign MUX_cache_rg_state$write_1__SEL_12 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + (cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d186 || + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d191 || + !cache_soc_map$m_is_mem_addr) ; + assign MUX_cache_rg_state$write_1__SEL_13 = + WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 ; + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36 or + cache_rg_addr or + cache_master_xactor_shim_rff_rv$port1__read or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37) + begin + case (cache_rg_f3) + 3'b0: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695; + 3'b001: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723; + 3'b010: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36; + 3'b011: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + (cache_rg_addr[2:0] == 3'h0) ? + cache_master_xactor_shim_rff_rv$port1__read[66:3] : + 64'd0; + 3'b100: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711; + 3'b101: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731; + 3'b110: + MUX_cache_dw_output_ld_val$wset_1__VAL_1 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37; + 3'd7: MUX_cache_dw_output_ld_val$wset_1__VAL_1 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 or + w17928_BITS_31_TO_0__q53 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851) + begin + case (cache_rg_f3) + 3'b0: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805; + 3'b001: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833; + 3'b010: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + { {32{w17928_BITS_31_TO_0__q53[31]}}, + w17928_BITS_31_TO_0__q53 }; + 3'b011: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852; + 3'b100: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821; + 3'b101: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841; + 3'b110: + MUX_cache_dw_output_ld_val$wset_1__VAL_2 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851; + 3'd7: MUX_cache_dw_output_ld_val$wset_1__VAL_2 = 64'd0; + endcase + end + assign MUX_cache_dw_output_ld_val$wset_1__VAL_3 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) ? + new_value__h8148 : + new_value__h18177 ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_1 = + { cache_rg_f3, cache_rg_pa, x__h27923 } ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_2 = + { cache_rg_f3, + cache_rg_addr, + IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d531 } ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_3 = + { cache_rg_f3, cache_rg_pa, cache_rg_st_amo_val } ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1 = + { 5'd16, + fabric_addr__h27309, + 8'd0, + size_val__h27412, + 18'd65536 } ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2 = + { 5'd16, cline_fabric_addr__h22383, 29'd7143424 } ; + assign MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1 = + { 3'd4, cache_rg_pa[31:12] } ; + assign MUX_cache_ram_word64_set$a_put_3__VAL_2 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 : + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 ; + assign MUX_cache_ram_word64_set$b_put_2__VAL_2 = + cache_rg_word64_set_in_cache + 9'd1 ; + assign MUX_cache_ram_word64_set$b_put_2__VAL_4 = + { cache_rg_addr[11:5], 2'd0 } ; + assign MUX_cache_rg_cset_in_cache$write_1__VAL_1 = + cache_rg_cset_in_cache + 7'd1 ; + assign MUX_cache_rg_exc_code$write_1__VAL_1 = + (req_op == 2'd0) ? 4'd4 : 4'd6 ; + assign MUX_cache_rg_exc_code$write_1__VAL_4 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) ? + 4'd5 : + 4'd7 ; + assign MUX_cache_rg_ld_val$write_1__VAL_2 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + x__h15829 : + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 ; + assign MUX_cache_rg_lrsc_valid$write_1__VAL_2 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 ; + assign MUX_cache_rg_st_amo_val$write_1__VAL_2 = + (cache_rg_f3 == 3'b010) ? + new_st_val__h19590 : + _theResult_____2__h19586 ; + assign MUX_cache_rg_state$write_1__VAL_1 = + NOT_req_f3_BITS_1_TO_0_44_EQ_0b0_45_46_AND_NOT_ETC___d965 ? + 4'd4 : + 4'd3 ; + assign MUX_cache_rg_state$write_1__VAL_2 = + (cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) ? + 4'd14 : + 4'd4 ; + assign MUX_cache_rg_state$write_1__VAL_4 = + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_rg_error_during_refill) ? + 4'd4 : + 4'd10 ; + assign MUX_cache_rg_state$write_1__VAL_12 = + cache_soc_map$m_is_mem_addr ? + IF_cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_ETC___d196 : + 4'd12 ; + + // inlined wires + assign cache_master_xactor_ug_master_u_b_putWire$wget = + { mem_master_bid, mem_master_bresp } ; + assign cache_master_xactor_ug_master_u_b_putWire$whas = + mem_master_bvalid && !cache_master_xactor_shim_bff_rv[6] ; + assign cache_master_xactor_ug_master_u_r_putWire$wget = + { mem_master_rid, + mem_master_rdata, + mem_master_rresp, + mem_master_rlast } ; + assign cache_master_xactor_ug_master_u_r_putWire$whas = + mem_master_rvalid && !cache_master_xactor_shim_rff_rv[71] ; + assign cache_dw_valid$whas = + (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp) && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d219 || + WILL_FIRE_RL_cache_rl_drive_exception_rsp || + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp || + WILL_FIRE_RL_cache_rl_ST_AMO_response ; + assign cache_master_xactor_ug_master_u_aw_dropWire$whas = + cache_master_xactor_shim_awff_rv$port1__read[97] && + mem_master_awready ; + assign cache_master_xactor_ug_master_u_w_dropWire$whas = + cache_master_xactor_shim_wff_rv$port1__read[73] && + mem_master_wready ; + assign cache_master_xactor_ug_master_u_ar_dropWire$whas = + cache_master_xactor_shim_arff_rv$port1__read[97] && + mem_master_arready ; + assign cache_master_xactor_shim_awff_rv$port0__write_1 = + { 5'd16, + mem_req_wr_addr_awaddr__h5054, + 8'd0, + _theResult___snd_snd_val__h5236, + 18'd65536 } ; + assign cache_master_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_master_xactor_shim_awff_rv$port0__write_1 : + cache_master_xactor_shim_awff_rv ; + assign cache_master_xactor_shim_awff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_awff_rv$port1__read ; + assign cache_master_xactor_shim_awff_rv$port3__read = + cache_master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_awff_rv$port2__read ; + assign cache_master_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, + mem_req_wr_data_wdata__h5352, + mem_req_wr_data_wstrb__h5353, + 1'd1 } ; + assign cache_master_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_master_xactor_shim_wff_rv$port0__write_1 : + cache_master_xactor_shim_wff_rv ; + assign cache_master_xactor_shim_wff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_wff_rv$port1__read ; + assign cache_master_xactor_shim_wff_rv$port3__read = + cache_master_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_wff_rv$port2__read ; + assign cache_master_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, cache_master_xactor_ug_master_u_b_putWire$wget } ; + assign cache_master_xactor_shim_bff_rv$port1__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut ? + cache_master_xactor_shim_bff_rv$port0__write_1 : + cache_master_xactor_shim_bff_rv ; + assign cache_master_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_cache_rl_discard_write_rsp ? + 7'd42 : + cache_master_xactor_shim_bff_rv$port1__read ; + assign cache_master_xactor_shim_bff_rv$port3__read = + cache_master_xactor_clearing ? + 7'd42 : + cache_master_xactor_shim_bff_rv$port2__read ; + assign cache_master_xactor_shim_arff_rv$EN_port0__write = + WILL_FIRE_RL_cache_rl_io_AMO_op_req || + WILL_FIRE_RL_cache_rl_io_read_req || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + assign cache_master_xactor_shim_arff_rv$port0__write_1 = + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1 : + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2 ; + assign cache_master_xactor_shim_arff_rv$port1__read = + cache_master_xactor_shim_arff_rv$EN_port0__write ? + cache_master_xactor_shim_arff_rv$port0__write_1 : + cache_master_xactor_shim_arff_rv ; + assign cache_master_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_arff_rv$port1__read ; + assign cache_master_xactor_shim_arff_rv$port3__read = + cache_master_xactor_clearing ? + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_arff_rv$port2__read ; + assign cache_master_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, cache_master_xactor_ug_master_u_r_putWire$wget } ; + assign cache_master_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut ? + cache_master_xactor_shim_rff_rv$port0__write_1 : + cache_master_xactor_shim_rff_rv ; + assign cache_master_xactor_shim_rff_rv$EN_port1__write = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop ; + assign cache_master_xactor_shim_rff_rv$port2__read = + cache_master_xactor_shim_rff_rv$EN_port1__write ? + 72'h2AAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_rff_rv$port1__read ; + assign cache_master_xactor_shim_rff_rv$port3__read = + cache_master_xactor_clearing ? + 72'h2AAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_rff_rv$port2__read ; + assign cache_ctr_wr_rsps_pending_crg$port0__write_1 = + cache_ctr_wr_rsps_pending_crg + 4'd1 ; + assign cache_ctr_wr_rsps_pending_crg$port1__read = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_ctr_wr_rsps_pending_crg$port0__write_1 : + cache_ctr_wr_rsps_pending_crg ; + assign cache_ctr_wr_rsps_pending_crg$port1__write_1 = b__h22284 - 4'd1 ; + assign cache_ctr_wr_rsps_pending_crg$port2__read = + CAN_FIRE_RL_cache_rl_discard_write_rsp ? + cache_ctr_wr_rsps_pending_crg$port1__write_1 : + cache_ctr_wr_rsps_pending_crg$port1__read ; + assign cache_ctr_wr_rsps_pending_crg$port3__read = + MUX_cache_master_xactor_clearing$write_1__SEL_2 ? + 4'd0 : + cache_ctr_wr_rsps_pending_crg$port2__read ; + assign cache_crg_sb_to_load_delay$port0__write_1 = + { 1'd0, cache_crg_sb_to_load_delay[10:1] } ; + assign cache_crg_sb_to_load_delay$EN_port1__write = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d524 ; + assign cache_crg_sb_to_load_delay$port2__read = + cache_crg_sb_to_load_delay$EN_port1__write ? + 11'd2047 : + cache_crg_sb_to_load_delay$port0__write_1 ; + + // register cache_cfg_verbosity + assign cache_cfg_verbosity$D_IN = set_verbosity_verbosity ; + assign cache_cfg_verbosity$EN = EN_set_verbosity ; + + // register cache_crg_sb_to_load_delay + assign cache_crg_sb_to_load_delay$D_IN = + cache_crg_sb_to_load_delay$port2__read ; + assign cache_crg_sb_to_load_delay$EN = 1'b1 ; + + // register cache_ctr_wr_rsps_pending_crg + assign cache_ctr_wr_rsps_pending_crg$D_IN = + cache_ctr_wr_rsps_pending_crg$port3__read ; + assign cache_ctr_wr_rsps_pending_crg$EN = 1'b1 ; + + // register cache_master_xactor_clearing + assign cache_master_xactor_clearing$D_IN = !cache_master_xactor_clearing ; + assign cache_master_xactor_clearing$EN = + WILL_FIRE_RL_cache_rl_start_reset && !cache_f_reset_reqs$D_OUT || + cache_master_xactor_clearing ; + + // register cache_master_xactor_shim_arff_rv + assign cache_master_xactor_shim_arff_rv$D_IN = + cache_master_xactor_shim_arff_rv$port3__read ; + assign cache_master_xactor_shim_arff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_awff_rv + assign cache_master_xactor_shim_awff_rv$D_IN = + cache_master_xactor_shim_awff_rv$port3__read ; + assign cache_master_xactor_shim_awff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_bff_rv + assign cache_master_xactor_shim_bff_rv$D_IN = + cache_master_xactor_shim_bff_rv$port3__read ; + assign cache_master_xactor_shim_bff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_rff_rv + assign cache_master_xactor_shim_rff_rv$D_IN = + cache_master_xactor_shim_rff_rv$port3__read ; + assign cache_master_xactor_shim_rff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_wff_rv + assign cache_master_xactor_shim_wff_rv$D_IN = + cache_master_xactor_shim_wff_rv$port3__read ; + assign cache_master_xactor_shim_wff_rv$EN = 1'b1 ; + + // register cache_rg_addr + assign cache_rg_addr$D_IN = req_addr ; + assign cache_rg_addr$EN = EN_req ; + + // register cache_rg_amo_funct7 + assign cache_rg_amo_funct7$D_IN = req_amo_funct7 ; + assign cache_rg_amo_funct7$EN = EN_req ; + + // register cache_rg_cset_in_cache + assign cache_rg_cset_in_cache$D_IN = + WILL_FIRE_RL_cache_rl_reset ? + MUX_cache_rg_cset_in_cache$write_1__VAL_1 : + 7'd0 ; + assign cache_rg_cset_in_cache$EN = + WILL_FIRE_RL_cache_rl_reset || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_error_during_refill + assign cache_rg_error_during_refill$D_IN = + MUX_cache_rg_error_during_refill$write_1__SEL_1 ; + assign cache_rg_error_during_refill$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // register cache_rg_exc_code + always@(MUX_cache_rg_exc_code$write_1__SEL_1 or + MUX_cache_rg_exc_code$write_1__VAL_1 or + MUX_cache_rg_exc_code$write_1__SEL_2 or + MUX_cache_rg_exc_code$write_1__SEL_3 or + MUX_cache_rg_error_during_refill$write_1__SEL_1 or + MUX_cache_rg_exc_code$write_1__VAL_4) + case (1'b1) + MUX_cache_rg_exc_code$write_1__SEL_1: + cache_rg_exc_code$D_IN = MUX_cache_rg_exc_code$write_1__VAL_1; + MUX_cache_rg_exc_code$write_1__SEL_2: cache_rg_exc_code$D_IN = 4'd7; + MUX_cache_rg_exc_code$write_1__SEL_3: cache_rg_exc_code$D_IN = 4'd5; + MUX_cache_rg_error_during_refill$write_1__SEL_1: + cache_rg_exc_code$D_IN = MUX_cache_rg_exc_code$write_1__VAL_4; + default: cache_rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; + endcase + assign cache_rg_exc_code$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + EN_req && + NOT_req_f3_BITS_1_TO_0_44_EQ_0b0_45_46_AND_NOT_ETC___d965 ; + + // register cache_rg_f3 + assign cache_rg_f3$D_IN = req_f3 ; + assign cache_rg_f3$EN = EN_req ; + + // register cache_rg_ld_val + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + MUX_cache_dw_output_ld_val$wset_1__VAL_2 or + MUX_cache_rg_ld_val$write_1__SEL_2 or + MUX_cache_rg_ld_val$write_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_read_rsp or + MUX_cache_dw_output_ld_val$wset_1__VAL_1 or + WILL_FIRE_RL_cache_rl_io_AMO_SC_req) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_2: + cache_rg_ld_val$D_IN = MUX_cache_dw_output_ld_val$wset_1__VAL_2; + MUX_cache_rg_ld_val$write_1__SEL_2: + cache_rg_ld_val$D_IN = MUX_cache_rg_ld_val$write_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_read_rsp: + cache_rg_ld_val$D_IN = MUX_cache_dw_output_ld_val$wset_1__VAL_1; + WILL_FIRE_RL_cache_rl_io_AMO_SC_req: cache_rg_ld_val$D_IN = 64'd1; + default: cache_rg_ld_val$D_IN = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_rg_ld_val$EN = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d381 || + WILL_FIRE_RL_cache_rl_io_read_rsp || + WILL_FIRE_RL_cache_rl_io_AMO_SC_req ; + + // register cache_rg_lower_word32 + assign cache_rg_lower_word32$D_IN = 32'h0 ; + assign cache_rg_lower_word32$EN = 1'b0 ; + + // register cache_rg_lower_word32_full + assign cache_rg_lower_word32_full$D_IN = 1'd0 ; + assign cache_rg_lower_word32_full$EN = + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_lrsc_pa + assign cache_rg_lrsc_pa$D_IN = cache_rg_addr ; + assign cache_rg_lrsc_pa$EN = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 ; + + // register cache_rg_lrsc_valid + assign cache_rg_lrsc_valid$D_IN = + MUX_cache_rg_lrsc_valid$write_1__SEL_2 && + MUX_cache_rg_lrsc_valid$write_1__VAL_2 ; + assign cache_rg_lrsc_valid$EN = + WILL_FIRE_RL_cache_rl_io_read_req && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d214 || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_op + assign cache_rg_op$D_IN = req_op ; + assign cache_rg_op$EN = EN_req ; + + // register cache_rg_pa + assign cache_rg_pa$D_IN = EN_req ? req_addr : cache_rg_addr ; + assign cache_rg_pa$EN = + EN_req || WILL_FIRE_RL_cache_rl_probe_and_immed_rsp ; + + // register cache_rg_pte_pa + assign cache_rg_pte_pa$D_IN = 32'h0 ; + assign cache_rg_pte_pa$EN = 1'b0 ; + + // register cache_rg_st_amo_val + assign cache_rg_st_amo_val$D_IN = + EN_req ? req_st_value : MUX_cache_rg_st_amo_val$write_1__VAL_2 ; + assign cache_rg_st_amo_val$EN = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d576 || + EN_req ; + + // register cache_rg_state + always@(EN_req or + MUX_cache_rg_state$write_1__VAL_1 or + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp or + MUX_cache_rg_state$write_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_read_rsp or + MUX_cache_rg_state$write_1__SEL_4 or + MUX_cache_rg_state$write_1__VAL_4 or + WILL_FIRE_RL_cache_rl_start_reset or + WILL_FIRE_RL_cache_rl_io_AMO_op_req or + WILL_FIRE_RL_cache_rl_io_AMO_SC_req or + WILL_FIRE_RL_cache_rl_io_write_req or + WILL_FIRE_RL_cache_rl_io_read_req or + WILL_FIRE_RL_cache_rl_rereq or + WILL_FIRE_RL_cache_rl_start_cache_refill or + MUX_cache_rg_state$write_1__SEL_12 or + MUX_cache_rg_state$write_1__VAL_12 or + MUX_cache_rg_state$write_1__SEL_13) + case (1'b1) + EN_req: cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_1; + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_read_rsp: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_2; + MUX_cache_rg_state$write_1__SEL_4: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_4; + WILL_FIRE_RL_cache_rl_start_reset: cache_rg_state$D_IN = 4'd1; + WILL_FIRE_RL_cache_rl_io_AMO_op_req: cache_rg_state$D_IN = 4'd15; + WILL_FIRE_RL_cache_rl_io_AMO_SC_req || WILL_FIRE_RL_cache_rl_io_write_req: + cache_rg_state$D_IN = 4'd11; + WILL_FIRE_RL_cache_rl_io_read_req: cache_rg_state$D_IN = 4'd13; + WILL_FIRE_RL_cache_rl_rereq: cache_rg_state$D_IN = 4'd3; + WILL_FIRE_RL_cache_rl_start_cache_refill: cache_rg_state$D_IN = 4'd9; + MUX_cache_rg_state$write_1__SEL_12: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_12; + MUX_cache_rg_state$write_1__SEL_13: cache_rg_state$D_IN = 4'd2; + default: cache_rg_state$D_IN = 4'b1010 /* unspecified value */ ; + endcase + assign cache_rg_state$EN = + WILL_FIRE_RL_cache_rl_reset && + cache_rg_cset_in_cache == 7'd127 || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + (cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d186 || + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d191 || + !cache_soc_map$m_is_mem_addr) || + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp || + EN_req || + WILL_FIRE_RL_cache_rl_start_reset || + WILL_FIRE_RL_cache_rl_rereq || + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_io_AMO_SC_req || + WILL_FIRE_RL_cache_rl_io_write_req || + WILL_FIRE_RL_cache_rl_io_read_req || + WILL_FIRE_RL_cache_rl_io_AMO_op_req ; + + // register cache_rg_word64_set_in_cache + assign cache_rg_word64_set_in_cache$D_IN = + MUX_cache_ram_word64_set$b_put_1__SEL_2 ? + MUX_cache_ram_word64_set$b_put_2__VAL_2 : + MUX_cache_ram_word64_set$b_put_2__VAL_4 ; + assign cache_rg_word64_set_in_cache$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // submodule cache_f_fabric_write_reqs + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_1 or + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2 or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_write_req or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_2: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_1; + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_write_req: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3; + default: cache_f_fabric_write_reqs$D_IN = + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_f_fabric_write_reqs$ENQ = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d529 || + WILL_FIRE_RL_cache_rl_io_write_req ; + assign cache_f_fabric_write_reqs$DEQ = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ; + assign cache_f_fabric_write_reqs$CLR = 1'b0 ; + + // submodule cache_f_reset_reqs + assign cache_f_reset_reqs$D_IN = !EN_server_reset_request_put ; + assign cache_f_reset_reqs$ENQ = + EN_server_reset_request_put || EN_server_flush_request_put ; + assign cache_f_reset_reqs$DEQ = MUX_cache_rg_state$write_1__SEL_13 ; + assign cache_f_reset_reqs$CLR = 1'b0 ; + + // submodule cache_f_reset_rsps + assign cache_f_reset_rsps$D_IN = cache_f_reset_reqs$D_OUT ; + assign cache_f_reset_rsps$ENQ = MUX_cache_rg_state$write_1__SEL_13 ; + assign cache_f_reset_rsps$DEQ = + EN_server_flush_response_get || EN_server_reset_response_get ; + assign cache_f_reset_rsps$CLR = 1'b0 ; + + // submodule cache_ram_state_and_ctag_cset + assign cache_ram_state_and_ctag_cset$ADDRA = + WILL_FIRE_RL_cache_rl_start_cache_refill ? + cache_rg_addr[11:5] : + cache_rg_cset_in_cache ; + assign cache_ram_state_and_ctag_cset$ADDRB = + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 ? + req_addr[11:5] : + cache_rg_addr[11:5] ; + assign cache_ram_state_and_ctag_cset$DIA = + WILL_FIRE_RL_cache_rl_start_cache_refill ? + MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1 : + 23'd2796202 ; + assign cache_ram_state_and_ctag_cset$DIB = + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 ? + 23'b01010101010101010101010 /* unspecified value */ : + 23'b01010101010101010101010 /* unspecified value */ ; + assign cache_ram_state_and_ctag_cset$WEA = 1'd1 ; + assign cache_ram_state_and_ctag_cset$WEB = 1'd0 ; + assign cache_ram_state_and_ctag_cset$ENA = + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_reset ; + assign cache_ram_state_and_ctag_cset$ENB = + EN_req && + req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974 || + WILL_FIRE_RL_cache_rl_rereq ; + + // submodule cache_ram_word64_set + assign cache_ram_word64_set$ADDRA = + MUX_cache_ram_word64_set$a_put_1__SEL_1 ? + cache_rg_word64_set_in_cache : + cache_rg_addr[11:3] ; + always@(MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 or + req_addr or + MUX_cache_ram_word64_set$b_put_1__SEL_2 or + MUX_cache_ram_word64_set$b_put_2__VAL_2 or + WILL_FIRE_RL_cache_rl_rereq or + cache_rg_addr or + WILL_FIRE_RL_cache_rl_start_cache_refill or + MUX_cache_ram_word64_set$b_put_2__VAL_4) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1: + cache_ram_word64_set$ADDRB = req_addr[11:3]; + MUX_cache_ram_word64_set$b_put_1__SEL_2: + cache_ram_word64_set$ADDRB = + MUX_cache_ram_word64_set$b_put_2__VAL_2; + WILL_FIRE_RL_cache_rl_rereq: + cache_ram_word64_set$ADDRB = cache_rg_addr[11:3]; + WILL_FIRE_RL_cache_rl_start_cache_refill: + cache_ram_word64_set$ADDRB = + MUX_cache_ram_word64_set$b_put_2__VAL_4; + default: cache_ram_word64_set$ADDRB = + 9'b010101010 /* unspecified value */ ; + endcase + end + assign cache_ram_word64_set$DIA = + MUX_cache_ram_word64_set$a_put_1__SEL_1 ? + cache_master_xactor_shim_rff_rv$port1__read[66:3] : + MUX_cache_ram_word64_set$a_put_3__VAL_2 ; + always@(MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 or + MUX_cache_ram_word64_set$b_put_1__SEL_2 or + WILL_FIRE_RL_cache_rl_rereq or + WILL_FIRE_RL_cache_rl_start_cache_refill) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_cache_ram_word64_set$b_put_1__SEL_2: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + WILL_FIRE_RL_cache_rl_rereq: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + WILL_FIRE_RL_cache_rl_start_cache_refill: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + default: cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_ram_word64_set$WEA = 1'd1 ; + assign cache_ram_word64_set$WEB = 1'd0 ; + assign cache_ram_word64_set$ENA = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d392 ; + assign cache_ram_word64_set$ENB = + EN_req && + req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974 || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 || + WILL_FIRE_RL_cache_rl_rereq || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // submodule cache_soc_map + assign cache_soc_map$m_is_IO_addr_addr = 64'h0 ; + assign cache_soc_map$m_is_mem_addr_addr = { 32'd0, cache_rg_addr } ; + assign cache_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; + + // remaining internal signals + assign IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340 = + (cache_rg_addr[2:0] == 3'h0) ? word64__h7969 : 64'd0 ; + assign IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d354 = + (cache_rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; + assign IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852 = + (cache_rg_addr[2:0] == 3'h0) ? ld_val__h25642 : 64'd0 ; + assign IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 = + (cache_rg_f3 == 3'b010) ? + { {32{cache_rg_st_amo_val_BITS_31_TO_0__q33[31]}}, + cache_rg_st_amo_val_BITS_31_TO_0__q33 } : + cache_rg_st_amo_val ; + assign IF_cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_ETC___d196 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) ? + 4'd8 : + IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d195 ; + assign IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d164 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15819 || + cache_f_fabric_write_reqs$FULL_N : + !cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 || + cache_f_fabric_write_reqs$FULL_N ; + assign IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d195 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + 4'd11 : + ((!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) ? + 4'd8 : + 4'd11) ; + assign IF_cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_ETC___d531 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + cache_rg_st_amo_val : + new_st_val__h19308 ; + assign NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 = + cache_cfg_verbosity > 4'd1 ; + assign NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 = + cache_cfg_verbosity > 4'd2 ; + assign NOT_cache_ram_state_and_ctag_cset_b_read__54_B_ETC___d202 = + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 ; + assign NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d191 = + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) ; + assign NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d529 = + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d527 || + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d389) ; + assign NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d547 ; + assign NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d557 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d555 ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d211 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d389 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d523 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + (cache_rg_f3 == 3'b0 || cache_rg_f3 == 3'b001) ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d565 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d568 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d572 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d387 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 ; + assign NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d521 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + (cache_rg_f3 == 3'b0 || cache_rg_f3 == 3'b001) ; + assign NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d547 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d551 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d555 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_req_f3_BITS_1_TO_0_44_EQ_0b0_45_46_AND_NOT_ETC___d965 = + req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && + (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && + (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; + assign _theResult___fst__h5221 = + cache_f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h5069 ; + assign access_exc_code__h4779 = MUX_cache_rg_exc_code$write_1__VAL_4 ; + assign b__h22284 = cache_ctr_wr_rsps_pending_crg$port1__read ; + assign cache_master_xactor_shim_arff_rvport1__read_B_ETC__q35 = + cache_master_xactor_shim_arff_rv$port1__read[96:0] ; + assign cache_master_xactor_shim_awff_rvport1__read_B_ETC__q1 = + cache_master_xactor_shim_awff_rv$port1__read[96:0] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q10 = + cache_master_xactor_shim_rff_rv$port1__read[50:35] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q11 = + cache_master_xactor_shim_rff_rv$port1__read[66:35] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q12 = + cache_master_xactor_shim_rff_rv$port1__read[50:43] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q13 = + cache_master_xactor_shim_rff_rv$port1__read[58:51] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q14 = + cache_master_xactor_shim_rff_rv$port1__read[66:51] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q15 = + cache_master_xactor_shim_rff_rv$port1__read[66:59] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q2 = + cache_master_xactor_shim_rff_rv$port1__read[10:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q3 = + cache_master_xactor_shim_rff_rv$port1__read[18:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q4 = + cache_master_xactor_shim_rff_rv$port1__read[34:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q5 = + cache_master_xactor_shim_rff_rv$port1__read[18:11] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q6 = + cache_master_xactor_shim_rff_rv$port1__read[26:19] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q7 = + cache_master_xactor_shim_rff_rv$port1__read[34:19] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q8 = + cache_master_xactor_shim_rff_rv$port1__read[34:27] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q9 = + cache_master_xactor_shim_rff_rv$port1__read[42:35] ; + assign cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q16 = + cache_master_xactor_shim_wff_rv$port1__read[72:0] ; + assign cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 = + cache_ram_state_and_ctag_cset$DOB[21:0] == pa_ctag__h7827 ; + assign cache_ram_state_and_ctag_cset_b_read__54_BIT_2_ETC___d203 = + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 || + NOT_cache_ram_state_and_ctag_cset_b_read__54_B_ETC___d202 ; + assign cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 = + cache_rg_addr == cache_rg_lrsc_pa ; + assign cache_rg_amo_funct7_36_BITS_6_TO_2_37_EQ_0b10__ETC___d375 = + cache_rg_amo_funct7[6:2] == 5'b00010 && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148 = + cache_rg_lrsc_pa == cache_rg_addr ; + assign cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d186 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) ; + assign cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d214 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset_b_read__54_BIT_2_ETC___d203 || + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d212 ; + assign cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d219 = + MUX_cache_rg_lrsc_valid$write_1__VAL_2 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15819 ; + assign cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d358 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d371 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d212 = + cache_rg_op == 2'd1 && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 || + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d211 ; + assign cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d390 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d387 || + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d389 ; + assign cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d524 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d521 || + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d523 ; + assign cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d527 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148) ; + assign cache_rg_op_33_EQ_2_35_AND_cache_rg_amo_funct7_ETC___d561 = + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15819 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_st_amo_val_BITS_31_TO_0__q33 = cache_rg_st_amo_val[31:0] ; + assign cache_rg_state_7_EQ_12_46_AND_cache_rg_op_33_E_ETC___d648 = + cache_rg_state == 4'd12 && + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + b__h22284 == 4'd0 ; + assign cache_rg_state_7_EQ_3_67_AND_NOT_cache_rg_op_3_ETC___d176 = + cache_rg_state == 4'd3 && + (cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) || + cache_crg_sb_to_load_delay$port0__write_1 == 11'd0) ; + assign cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d381 = + cache_soc_map$m_is_mem_addr && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 || + cache_rg_op != 2'd1 && cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160) ; + assign cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d392 = + cache_soc_map$m_is_mem_addr && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_33_EQ_1_41_OR_cache_rg_op_33_EQ_2__ETC___d390 ; + assign cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570 = + cache_soc_map$m_is_mem_addr && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d568 ; + assign cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d576 = + cache_soc_map$m_is_mem_addr && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d389 ; + assign cline_addr__h22382 = { cache_rg_pa[31:5], 5'd0 } ; + assign cline_fabric_addr__h22383 = { 32'd0, cline_addr__h22382 } ; + assign fabric_addr__h27309 = { 32'd0, cache_rg_pa } ; + assign ld_val5642_BITS_15_TO_0__q39 = ld_val__h25642[15:0] ; + assign ld_val5642_BITS_15_TO_8__q41 = ld_val__h25642[15:8] ; + assign ld_val5642_BITS_23_TO_16__q42 = ld_val__h25642[23:16] ; + assign ld_val5642_BITS_31_TO_0__q40 = ld_val__h25642[31:0] ; + assign ld_val5642_BITS_31_TO_16__q43 = ld_val__h25642[31:16] ; + assign ld_val5642_BITS_31_TO_24__q44 = ld_val__h25642[31:24] ; + assign ld_val5642_BITS_39_TO_32__q45 = ld_val__h25642[39:32] ; + assign ld_val5642_BITS_47_TO_32__q46 = ld_val__h25642[47:32] ; + assign ld_val5642_BITS_47_TO_40__q48 = ld_val__h25642[47:40] ; + assign ld_val5642_BITS_55_TO_48__q49 = ld_val__h25642[55:48] ; + assign ld_val5642_BITS_63_TO_32__q47 = ld_val__h25642[63:32] ; + assign ld_val5642_BITS_63_TO_48__q50 = ld_val__h25642[63:48] ; + assign ld_val5642_BITS_63_TO_56__q51 = ld_val__h25642[63:56] ; + assign ld_val5642_BITS_7_TO_0__q38 = ld_val__h25642[7:0] ; + assign ld_val__h25642 = MUX_cache_dw_output_ld_val$wset_1__VAL_1 ; + assign lrsc_result__h15819 = + !cache_rg_lrsc_valid || + !cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148 ; + assign mem_req_wr_addr_awaddr__h5054 = + { 32'd0, cache_f_fabric_write_reqs$D_OUT[95:64] } ; + assign new_ld_val__h27894 = MUX_cache_dw_output_ld_val$wset_1__VAL_2 ; + assign new_st_val__h19308 = MUX_cache_rg_st_amo_val$write_1__VAL_2 ; + assign new_st_val__h19590 = { 32'd0, _theResult_____2__h19586[31:0] } ; + assign new_st_val__h19681 = + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 + + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ; + assign new_st_val__h20661 = w1__h19578 ^ w2__h27934 ; + assign new_st_val__h20665 = w1__h19578 & w2__h27934 ; + assign new_st_val__h20669 = w1__h19578 | w2__h27934 ; + assign new_st_val__h20673 = + (w1__h19578 < w2__h27934) ? w1__h19578 : w2__h27934 ; + assign new_st_val__h20678 = + (w1__h19578 <= w2__h27934) ? w2__h27934 : w1__h19578 ; + assign new_st_val__h20684 = + ((IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 ^ + 64'h8000000000000000) < + (IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ^ + 64'h8000000000000000)) ? + w1__h19578 : + w2__h27934 ; + assign new_st_val__h20689 = + ((IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 ^ + 64'h8000000000000000) <= + (IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ^ + 64'h8000000000000000)) ? + w2__h27934 : + w1__h19578 ; + assign new_st_val__h27944 = { 32'd0, _theResult_____2__h27940[31:0] } ; + assign new_st_val__h28035 = + new_ld_val__h27894 + + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ; + assign new_st_val__h29895 = w1__h27932 ^ w2__h27934 ; + assign new_st_val__h29899 = w1__h27932 & w2__h27934 ; + assign new_st_val__h29903 = w1__h27932 | w2__h27934 ; + assign new_st_val__h29907 = + (w1__h27932 < w2__h27934) ? w1__h27932 : w2__h27934 ; + assign new_st_val__h29912 = + (w1__h27932 <= w2__h27934) ? w2__h27934 : w1__h27932 ; + assign new_st_val__h29918 = + ((new_ld_val__h27894 ^ 64'h8000000000000000) < + (IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ^ + 64'h8000000000000000)) ? + w1__h27932 : + w2__h27934 ; + assign new_st_val__h29923 = + ((new_ld_val__h27894 ^ 64'h8000000000000000) <= + (IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_cache_r_ETC___d449 ^ + 64'h8000000000000000)) ? + w2__h27934 : + w1__h27932 ; + assign new_value148_BITS_31_TO_0__q32 = new_value__h8148[31:0] ; + assign pa_ctag__h7827 = { 2'd0, cache_rg_addr[31:12] } ; + assign req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974 = + req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || + req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || + req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; + assign result__h14559 = + { {56{word64969_BITS_15_TO_8__q20[7]}}, + word64969_BITS_15_TO_8__q20 } ; + assign result__h14587 = + { {56{word64969_BITS_23_TO_16__q21[7]}}, + word64969_BITS_23_TO_16__q21 } ; + assign result__h14615 = + { {56{word64969_BITS_31_TO_24__q23[7]}}, + word64969_BITS_31_TO_24__q23 } ; + assign result__h14643 = + { {56{word64969_BITS_39_TO_32__q24[7]}}, + word64969_BITS_39_TO_32__q24 } ; + assign result__h14671 = + { {56{word64969_BITS_47_TO_40__q27[7]}}, + word64969_BITS_47_TO_40__q27 } ; + assign result__h14699 = + { {56{word64969_BITS_55_TO_48__q28[7]}}, + word64969_BITS_55_TO_48__q28 } ; + assign result__h14727 = + { {56{word64969_BITS_63_TO_56__q30[7]}}, + word64969_BITS_63_TO_56__q30 } ; + assign result__h14772 = { 56'd0, word64__h7969[7:0] } ; + assign result__h14800 = { 56'd0, word64__h7969[15:8] } ; + assign result__h14828 = { 56'd0, word64__h7969[23:16] } ; + assign result__h14856 = { 56'd0, word64__h7969[31:24] } ; + assign result__h14884 = { 56'd0, word64__h7969[39:32] } ; + assign result__h14912 = { 56'd0, word64__h7969[47:40] } ; + assign result__h14940 = { 56'd0, word64__h7969[55:48] } ; + assign result__h14968 = { 56'd0, word64__h7969[63:56] } ; + assign result__h15013 = + { {48{word64969_BITS_15_TO_0__q18[15]}}, + word64969_BITS_15_TO_0__q18 } ; + assign result__h15041 = + { {48{word64969_BITS_31_TO_16__q22[15]}}, + word64969_BITS_31_TO_16__q22 } ; + assign result__h15069 = + { {48{word64969_BITS_47_TO_32__q25[15]}}, + word64969_BITS_47_TO_32__q25 } ; + assign result__h15097 = + { {48{word64969_BITS_63_TO_48__q29[15]}}, + word64969_BITS_63_TO_48__q29 } ; + assign result__h15138 = { 48'd0, word64__h7969[15:0] } ; + assign result__h15166 = { 48'd0, word64__h7969[31:16] } ; + assign result__h15194 = { 48'd0, word64__h7969[47:32] } ; + assign result__h15222 = { 48'd0, word64__h7969[63:48] } ; + assign result__h15263 = + { {32{word64969_BITS_31_TO_0__q19[31]}}, + word64969_BITS_31_TO_0__q19 } ; + assign result__h15291 = + { {32{word64969_BITS_63_TO_32__q26[31]}}, + word64969_BITS_63_TO_32__q26 } ; + assign result__h15330 = { 32'd0, word64__h7969[31:0] } ; + assign result__h15358 = { 32'd0, word64__h7969[63:32] } ; + assign result__h25702 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q2[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q2 } ; + assign result__h25732 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q5[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q5 } ; + assign result__h25759 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q6[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q6 } ; + assign result__h25786 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q8[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q8 } ; + assign result__h25813 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q9[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q9 } ; + assign result__h25840 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q12[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q12 } ; + assign result__h25867 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q13[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q13 } ; + assign result__h25894 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q15[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q15 } ; + assign result__h25938 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[10:3] } ; + assign result__h25965 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[18:11] } ; + assign result__h25992 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[26:19] } ; + assign result__h26019 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[34:27] } ; + assign result__h26046 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[42:35] } ; + assign result__h26073 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[50:43] } ; + assign result__h26100 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[58:51] } ; + assign result__h26127 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[66:59] } ; + assign result__h26171 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q3[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q3 } ; + assign result__h26198 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q7[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q7 } ; + assign result__h26225 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q10[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q10 } ; + assign result__h26252 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q14[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q14 } ; + assign result__h26292 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[18:3] } ; + assign result__h26319 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[34:19] } ; + assign result__h26346 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[50:35] } ; + assign result__h26373 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[66:51] } ; + assign result__h26413 = + { {32{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q4[31]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q4 } ; + assign result__h26440 = + { {32{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q11[31]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q11 } ; + assign result__h26478 = + { 32'd0, cache_master_xactor_shim_rff_rv$port1__read[34:3] } ; + assign result__h26505 = + { 32'd0, cache_master_xactor_shim_rff_rv$port1__read[66:35] } ; + assign result__h28123 = + { {56{ld_val5642_BITS_7_TO_0__q38[7]}}, + ld_val5642_BITS_7_TO_0__q38 } ; + assign result__h29031 = + { {56{ld_val5642_BITS_15_TO_8__q41[7]}}, + ld_val5642_BITS_15_TO_8__q41 } ; + assign result__h29059 = + { {56{ld_val5642_BITS_23_TO_16__q42[7]}}, + ld_val5642_BITS_23_TO_16__q42 } ; + assign result__h29087 = + { {56{ld_val5642_BITS_31_TO_24__q44[7]}}, + ld_val5642_BITS_31_TO_24__q44 } ; + assign result__h29115 = + { {56{ld_val5642_BITS_39_TO_32__q45[7]}}, + ld_val5642_BITS_39_TO_32__q45 } ; + assign result__h29143 = + { {56{ld_val5642_BITS_47_TO_40__q48[7]}}, + ld_val5642_BITS_47_TO_40__q48 } ; + assign result__h29171 = + { {56{ld_val5642_BITS_55_TO_48__q49[7]}}, + ld_val5642_BITS_55_TO_48__q49 } ; + assign result__h29199 = + { {56{ld_val5642_BITS_63_TO_56__q51[7]}}, + ld_val5642_BITS_63_TO_56__q51 } ; + assign result__h29244 = { 56'd0, ld_val__h25642[7:0] } ; + assign result__h29272 = { 56'd0, ld_val__h25642[15:8] } ; + assign result__h29300 = { 56'd0, ld_val__h25642[23:16] } ; + assign result__h29328 = { 56'd0, ld_val__h25642[31:24] } ; + assign result__h29356 = { 56'd0, ld_val__h25642[39:32] } ; + assign result__h29384 = { 56'd0, ld_val__h25642[47:40] } ; + assign result__h29412 = { 56'd0, ld_val__h25642[55:48] } ; + assign result__h29440 = { 56'd0, ld_val__h25642[63:56] } ; + assign result__h29485 = + { {48{ld_val5642_BITS_15_TO_0__q39[15]}}, + ld_val5642_BITS_15_TO_0__q39 } ; + assign result__h29513 = + { {48{ld_val5642_BITS_31_TO_16__q43[15]}}, + ld_val5642_BITS_31_TO_16__q43 } ; + assign result__h29541 = + { {48{ld_val5642_BITS_47_TO_32__q46[15]}}, + ld_val5642_BITS_47_TO_32__q46 } ; + assign result__h29569 = + { {48{ld_val5642_BITS_63_TO_48__q50[15]}}, + ld_val5642_BITS_63_TO_48__q50 } ; + assign result__h29610 = { 48'd0, ld_val__h25642[15:0] } ; + assign result__h29638 = { 48'd0, ld_val__h25642[31:16] } ; + assign result__h29666 = { 48'd0, ld_val__h25642[47:32] } ; + assign result__h29694 = { 48'd0, ld_val__h25642[63:48] } ; + assign result__h29735 = + { {32{ld_val5642_BITS_31_TO_0__q40[31]}}, + ld_val5642_BITS_31_TO_0__q40 } ; + assign result__h29763 = + { {32{ld_val5642_BITS_63_TO_32__q47[31]}}, + ld_val5642_BITS_63_TO_32__q47 } ; + assign result__h29802 = { 32'd0, ld_val__h25642[31:0] } ; + assign result__h29830 = { 32'd0, ld_val__h25642[63:32] } ; + assign result__h8203 = + { {56{word64969_BITS_7_TO_0__q17[7]}}, + word64969_BITS_7_TO_0__q17 } ; + assign shift_bits__h5069 = + { cache_f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ; + assign strobe64__h5219 = + 8'b00000001 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign strobe64__h5223 = + 8'b00000011 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign strobe64__h5227 = + 8'b00001111 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign w17928_BITS_31_TO_0__q53 = w1__h27928[31:0] ; + assign w1___1__h19649 = { 32'd0, new_value__h8148[31:0] } ; + assign w1___1__h28003 = { 32'd0, w1__h27928[31:0] } ; + assign w2___1__h28004 = { 32'd0, cache_rg_st_amo_val[31:0] } ; + assign w2__h27934 = + (cache_rg_f3 == 3'b010) ? w2___1__h28004 : cache_rg_st_amo_val ; + assign word64969_BITS_15_TO_0__q18 = word64__h7969[15:0] ; + assign word64969_BITS_15_TO_8__q20 = word64__h7969[15:8] ; + assign word64969_BITS_23_TO_16__q21 = word64__h7969[23:16] ; + assign word64969_BITS_31_TO_0__q19 = word64__h7969[31:0] ; + assign word64969_BITS_31_TO_16__q22 = word64__h7969[31:16] ; + assign word64969_BITS_31_TO_24__q23 = word64__h7969[31:24] ; + assign word64969_BITS_39_TO_32__q24 = word64__h7969[39:32] ; + assign word64969_BITS_47_TO_32__q25 = word64__h7969[47:32] ; + assign word64969_BITS_47_TO_40__q27 = word64__h7969[47:40] ; + assign word64969_BITS_55_TO_48__q28 = word64__h7969[55:48] ; + assign word64969_BITS_63_TO_32__q26 = word64__h7969[63:32] ; + assign word64969_BITS_63_TO_48__q29 = word64__h7969[63:48] ; + assign word64969_BITS_63_TO_56__q30 = word64__h7969[63:56] ; + assign word64969_BITS_7_TO_0__q17 = word64__h7969[7:0] ; + assign word64__h7969 = cache_ram_word64_set$DOB & y__h8239 ; + assign x__h15829 = { 63'd0, lrsc_result__h15819 } ; + assign x__h27923 = + (cache_rg_f3 == 3'b010) ? + new_st_val__h27944 : + _theResult_____2__h27940 ; + assign y__h8239 = + {64{cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160}} ; + always@(cache_f_fabric_write_reqs$D_OUT) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0: _theResult___snd_snd_val__h5236 = 3'b0; + 2'b01: _theResult___snd_snd_val__h5236 = 3'b001; + 2'b10: _theResult___snd_snd_val__h5236 = 3'b010; + 2'b11: _theResult___snd_snd_val__h5236 = 3'b011; + endcase + end + always@(cache_rg_f3) + begin + case (cache_rg_f3[1:0]) + 2'b0: size_val__h27412 = 3'b0; + 2'b01: size_val__h27412 = 3'b001; + 2'b10: size_val__h27412 = 3'b010; + 2'd3: size_val__h27412 = 3'b011; + endcase + end + always@(cache_f_fabric_write_reqs$D_OUT or + strobe64__h5219 or strobe64__h5223 or strobe64__h5227) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0: mem_req_wr_data_wstrb__h5353 = strobe64__h5219; + 2'b01: mem_req_wr_data_wstrb__h5353 = strobe64__h5223; + 2'b10: mem_req_wr_data_wstrb__h5353 = strobe64__h5227; + 2'b11: mem_req_wr_data_wstrb__h5353 = 8'b11111111; + endcase + end + always@(cache_f_fabric_write_reqs$D_OUT or _theResult___fst__h5221) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0, 2'b01, 2'b10: + mem_req_wr_data_wdata__h5352 = _theResult___fst__h5221; + 2'd3: + mem_req_wr_data_wdata__h5352 = + cache_f_fabric_write_reqs$D_OUT[63:0]; + endcase + end + always@(cache_rg_addr or + result__h8203 or + result__h14559 or + result__h14587 or + result__h14615 or + result__h14643 or + result__h14671 or result__h14699 or result__h14727) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h8203; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14559; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14587; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14615; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14643; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14671; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14699; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 = + result__h14727; + endcase + end + always@(cache_rg_addr or + result__h15013 or + result__h15041 or result__h15069 or result__h15097) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 = + result__h15013; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 = + result__h15041; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 = + result__h15069; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 = + result__h15097; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h14772 or + result__h14800 or + result__h14828 or + result__h14856 or + result__h14884 or + result__h14912 or result__h14940 or result__h14968) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14772; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14800; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14828; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14856; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14884; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14912; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14940; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 = + result__h14968; + endcase + end + always@(cache_rg_addr or + result__h15138 or + result__h15166 or result__h15194 or result__h15222) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 = + result__h15138; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 = + result__h15166; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 = + result__h15194; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 = + result__h15222; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h15330 or result__h15358) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338 = + result__h15330; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338 = + result__h15358; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h15263 or result__h15291) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31 = + result__h15263; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31 = + result__h15291; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31 = + 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338) + begin + case (cache_rg_f3) + 3'b0: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287; + 3'b001: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317; + 3'b010: + new_value__h8148 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5263__ETC__q31; + 3'b011: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340; + 3'b100: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304; + 3'b101: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326; + 3'b110: + new_value__h8148 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338; + 3'd7: new_value__h8148 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 or + w1___1__h19649 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338) + begin + case (cache_rg_f3) + 3'b0: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287; + 3'b001: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317; + 3'b010: w1__h19578 = w1___1__h19649; + 3'b011: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340; + 3'b100: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304; + 3'b101: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326; + 3'b110: + w1__h19578 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338; + 3'd7: w1__h19578 = 64'd0; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 = + { cache_ram_word64_set$DOB[63:16], cache_rg_st_amo_val[15:0] }; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 = + { cache_ram_word64_set$DOB[63:32], + cache_rg_st_amo_val[15:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 = + { cache_ram_word64_set$DOB[63:48], + cache_rg_st_amo_val[15:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 = + { cache_rg_st_amo_val[15:0], cache_ram_word64_set$DOB[47:0] }; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:8], cache_rg_st_amo_val[7:0] }; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:16], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[7:0] }; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:24], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:32], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[23:0] }; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:40], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:48], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[39:0] }; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_ram_word64_set$DOB[63:56], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[47:0] }; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 = + { cache_rg_st_amo_val[7:0], cache_ram_word64_set$DOB[55:0] }; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317 or + new_value148_BITS_31_TO_0__q32 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d287; + 3'b001: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d317; + 3'b010: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + { {32{new_value148_BITS_31_TO_0__q32[31]}}, + new_value148_BITS_31_TO_0__q32 }; + 3'b011: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d340; + 3'b100: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d304; + 3'b101: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d326; + 3'b110: + IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d338; + 3'd7: IF_cache_rg_f3_21_EQ_0b10_27_THEN_SEXT_IF_cach_ETC___d385 = 64'd0; + endcase + end + always@(cache_rg_amo_funct7 or + new_st_val__h20689 or + new_st_val__h19681 or + w2__h27934 or + new_st_val__h20661 or + new_st_val__h20669 or + new_st_val__h20665 or + new_st_val__h20684 or new_st_val__h20673 or new_st_val__h20678) + begin + case (cache_rg_amo_funct7[6:2]) + 5'b0: _theResult_____2__h19586 = new_st_val__h19681; + 5'b00001: _theResult_____2__h19586 = w2__h27934; + 5'b00100: _theResult_____2__h19586 = new_st_val__h20661; + 5'b01000: _theResult_____2__h19586 = new_st_val__h20669; + 5'b01100: _theResult_____2__h19586 = new_st_val__h20665; + 5'b10000: _theResult_____2__h19586 = new_st_val__h20684; + 5'b11000: _theResult_____2__h19586 = new_st_val__h20673; + 5'b11100: _theResult_____2__h19586 = new_st_val__h20678; + default: _theResult_____2__h19586 = new_st_val__h20689; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19308) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 = + { cache_ram_word64_set$DOB[63:16], new_st_val__h19308[15:0] }; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 = + { cache_ram_word64_set$DOB[63:32], + new_st_val__h19308[15:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 = + { cache_ram_word64_set$DOB[63:48], + new_st_val__h19308[15:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 = + { new_st_val__h19308[15:0], cache_ram_word64_set$DOB[47:0] }; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19308) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:8], new_st_val__h19308[7:0] }; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:16], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[7:0] }; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:24], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:32], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[23:0] }; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:40], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:48], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[39:0] }; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { cache_ram_word64_set$DOB[63:56], + new_st_val__h19308[7:0], + cache_ram_word64_set$DOB[47:0] }; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 = + { new_st_val__h19308[7:0], cache_ram_word64_set$DOB[55:0] }; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34 = + { cache_ram_word64_set$DOB[63:32], cache_rg_st_amo_val[31:0] }; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34 = + { cache_rg_st_amo_val[31:0], cache_ram_word64_set$DOB[31:0] }; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + cache_ram_word64_set$DOB or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34 or + cache_rg_st_amo_val) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d425; + 3'b001: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d434; + 3'b010: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q34; + 3'b011: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 = + cache_rg_st_amo_val; + default: IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or + result__h26292 or + result__h26319 or result__h26346 or result__h26373) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 = + result__h26292; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 = + result__h26319; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 = + result__h26346; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 = + result__h26373; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d731 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h26171 or + result__h26198 or result__h26225 or result__h26252) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 = + result__h26171; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 = + result__h26198; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 = + result__h26225; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 = + result__h26252; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d723 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h25938 or + result__h25965 or + result__h25992 or + result__h26019 or + result__h26046 or + result__h26073 or result__h26100 or result__h26127) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h25938; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h25965; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h25992; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h26019; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h26046; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h26073; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h26100; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d711 = + result__h26127; + endcase + end + always@(cache_rg_addr or + result__h25702 or + result__h25732 or + result__h25759 or + result__h25786 or + result__h25813 or + result__h25840 or result__h25867 or result__h25894) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25702; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25732; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25759; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25786; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25813; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25840; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25867; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d695 = + result__h25894; + endcase + end + always@(cache_rg_addr or result__h26413 or result__h26440) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36 = + result__h26413; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36 = + result__h26440; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6413__ETC__q36 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h26478 or result__h26505) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37 = + result__h26478; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37 = + result__h26505; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6478__ETC__q37 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h29802 or result__h29830) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851 = + result__h29802; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851 = + result__h29830; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h29485 or + result__h29513 or result__h29541 or result__h29569) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 = + result__h29485; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 = + result__h29513; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 = + result__h29541; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 = + result__h29569; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h29610 or + result__h29638 or result__h29666 or result__h29694) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 = + result__h29610; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 = + result__h29638; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 = + result__h29666; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 = + result__h29694; + default: IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h29244 or + result__h29272 or + result__h29300 or + result__h29328 or + result__h29356 or + result__h29384 or result__h29412 or result__h29440) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29244; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29272; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29300; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29328; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29356; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29384; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29412; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 = + result__h29440; + endcase + end + always@(cache_rg_addr or + result__h28123 or + result__h29031 or + result__h29059 or + result__h29087 or + result__h29115 or + result__h29143 or result__h29171 or result__h29199) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h28123; + 3'h1: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29031; + 3'h2: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29059; + 3'h3: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29087; + 3'h4: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29115; + 3'h5: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29143; + 3'h6: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29171; + 3'h7: + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 = + result__h29199; + endcase + end + always@(cache_rg_addr or result__h29735 or result__h29763) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52 = + result__h29735; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52 = + result__h29763; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52 = + 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851) + begin + case (cache_rg_f3) + 3'b0: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805; + 3'b001: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833; + 3'b010: + w1__h27928 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result9735__ETC__q52; + 3'b011: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852; + 3'b100: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821; + 3'b101: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841; + 3'b110: + w1__h27928 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851; + 3'd7: w1__h27928 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833 or + w1___1__h28003 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851) + begin + case (cache_rg_f3) + 3'b0: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d805; + 3'b001: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d833; + 3'b010: w1__h27932 = w1___1__h28003; + 3'b011: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d852; + 3'b100: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d821; + 3'b101: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d841; + 3'b110: + w1__h27932 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d851; + 3'd7: w1__h27932 = 64'd0; + endcase + end + always@(cache_rg_amo_funct7 or + new_st_val__h29923 or + new_st_val__h28035 or + w2__h27934 or + new_st_val__h29895 or + new_st_val__h29903 or + new_st_val__h29899 or + new_st_val__h29918 or new_st_val__h29907 or new_st_val__h29912) + begin + case (cache_rg_amo_funct7[6:2]) + 5'b0: _theResult_____2__h27940 = new_st_val__h28035; + 5'b00001: _theResult_____2__h27940 = w2__h27934; + 5'b00100: _theResult_____2__h27940 = new_st_val__h29895; + 5'b01000: _theResult_____2__h27940 = new_st_val__h29903; + 5'b01100: _theResult_____2__h27940 = new_st_val__h29899; + 5'b10000: _theResult_____2__h27940 = new_st_val__h29918; + 5'b11000: _theResult_____2__h27940 = new_st_val__h29907; + 5'b11100: _theResult_____2__h27940 = new_st_val__h29912; + default: _theResult_____2__h27940 = new_st_val__h29923; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19308) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54 = + { cache_ram_word64_set$DOB[63:32], new_st_val__h19308[31:0] }; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54 = + { new_st_val__h19308[31:0], cache_ram_word64_set$DOB[31:0] }; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + cache_ram_word64_set$DOB or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54 or + new_st_val__h19308) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d499; + 3'b001: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d508; + 3'b010: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q54; + 3'b011: + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 = + new_st_val__h19308; + default: IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d354) + begin + case (cache_rg_f3) + 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: + new_value__h18177 = + IF_cache_rg_addr_29_BITS_2_TO_0_82_EQ_0x0_23_T_ETC___d354; + 3'd7: new_value__h18177 = 64'd0; + endcase + end + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + cache_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; + cache_crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; + cache_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; + cache_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 98'h0AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 7'd42; + cache_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 72'h2AAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + cache_rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 7'd0; + cache_rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; + end + else + begin + if (cache_cfg_verbosity$EN) + cache_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY + cache_cfg_verbosity$D_IN; + if (cache_crg_sb_to_load_delay$EN) + cache_crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY + cache_crg_sb_to_load_delay$D_IN; + if (cache_ctr_wr_rsps_pending_crg$EN) + cache_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY + cache_ctr_wr_rsps_pending_crg$D_IN; + if (cache_master_xactor_clearing$EN) + cache_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_clearing$D_IN; + if (cache_master_xactor_shim_arff_rv$EN) + cache_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_arff_rv$D_IN; + if (cache_master_xactor_shim_awff_rv$EN) + cache_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_awff_rv$D_IN; + if (cache_master_xactor_shim_bff_rv$EN) + cache_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_bff_rv$D_IN; + if (cache_master_xactor_shim_rff_rv$EN) + cache_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_rff_rv$D_IN; + if (cache_master_xactor_shim_wff_rv$EN) + cache_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_wff_rv$D_IN; + if (cache_rg_cset_in_cache$EN) + cache_rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY + cache_rg_cset_in_cache$D_IN; + if (cache_rg_lower_word32_full$EN) + cache_rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY + cache_rg_lower_word32_full$D_IN; + if (cache_rg_lrsc_valid$EN) + cache_rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY + cache_rg_lrsc_valid$D_IN; + if (cache_rg_state$EN) + cache_rg_state <= `BSV_ASSIGNMENT_DELAY cache_rg_state$D_IN; + end + if (cache_rg_addr$EN) + cache_rg_addr <= `BSV_ASSIGNMENT_DELAY cache_rg_addr$D_IN; + if (cache_rg_amo_funct7$EN) + cache_rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY cache_rg_amo_funct7$D_IN; + if (cache_rg_error_during_refill$EN) + cache_rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY + cache_rg_error_during_refill$D_IN; + if (cache_rg_exc_code$EN) + cache_rg_exc_code <= `BSV_ASSIGNMENT_DELAY cache_rg_exc_code$D_IN; + if (cache_rg_f3$EN) cache_rg_f3 <= `BSV_ASSIGNMENT_DELAY cache_rg_f3$D_IN; + if (cache_rg_ld_val$EN) + cache_rg_ld_val <= `BSV_ASSIGNMENT_DELAY cache_rg_ld_val$D_IN; + if (cache_rg_lower_word32$EN) + cache_rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY + cache_rg_lower_word32$D_IN; + if (cache_rg_lrsc_pa$EN) + cache_rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_lrsc_pa$D_IN; + if (cache_rg_op$EN) cache_rg_op <= `BSV_ASSIGNMENT_DELAY cache_rg_op$D_IN; + if (cache_rg_pa$EN) cache_rg_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_pa$D_IN; + if (cache_rg_pte_pa$EN) + cache_rg_pte_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_pte_pa$D_IN; + if (cache_rg_st_amo_val$EN) + cache_rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY cache_rg_st_amo_val$D_IN; + if (cache_rg_word64_set_in_cache$EN) + cache_rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY + cache_rg_word64_set_in_cache$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + cache_cfg_verbosity = 4'hA; + cache_crg_sb_to_load_delay = 11'h2AA; + cache_ctr_wr_rsps_pending_crg = 4'hA; + cache_master_xactor_clearing = 1'h0; + cache_master_xactor_shim_arff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_awff_rv = 98'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_bff_rv = 7'h2A; + cache_master_xactor_shim_rff_rv = 72'hAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + cache_rg_addr = 32'hAAAAAAAA; + cache_rg_amo_funct7 = 7'h2A; + cache_rg_cset_in_cache = 7'h2A; + cache_rg_error_during_refill = 1'h0; + cache_rg_exc_code = 4'hA; + cache_rg_f3 = 3'h2; + cache_rg_ld_val = 64'hAAAAAAAAAAAAAAAA; + cache_rg_lower_word32 = 32'hAAAAAAAA; + cache_rg_lower_word32_full = 1'h0; + cache_rg_lrsc_pa = 32'hAAAAAAAA; + cache_rg_lrsc_valid = 1'h0; + cache_rg_op = 2'h2; + cache_rg_pa = 32'hAAAAAAAA; + cache_rg_pte_pa = 32'hAAAAAAAA; + cache_rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; + cache_rg_state = 4'hA; + cache_rg_word64_set_in_cache = 9'h0AA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + begin + v__h5604 = $stime; + #0; + end + v__h5598 = v__h5604 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + $display("%0d: ERROR: CreditCounter: overflow", v__h5598); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_AWFlit { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_addr_awaddr__h5054); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", _theResult___snd_snd_val__h5236, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_WFlit { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_data_wdata__h5352); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wstrb: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_data_wstrb__h5353); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + cache_cfg_verbosity != 4'd0 && + !cache_f_reset_reqs$D_OUT) + begin + v__h6425 = $stime; + #0; + end + v__h6419 = v__h6425 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + cache_cfg_verbosity != 4'd0 && + !cache_f_reset_reqs$D_OUT) + $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", + v__h6419, + "D_MMU_Cache", + $signed(32'd128), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_f_reset_reqs$D_OUT) + begin + v__h6526 = $stime; + #0; + end + v__h6520 = v__h6526 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_f_reset_reqs$D_OUT) + $display("%0d: %s.rl_reset: Flushed", v__h6520, "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h6977 = $stime; + #0; + end + v__h6971 = v__h6977 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", + v__h6971, + "D_MMU_Cache", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", + pa_ctag__h7827, + cache_rg_addr[11:5], + cache_rg_addr[4:3], + cache_rg_addr[2:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" CSet 0x%0x: (state, tag):", cache_rg_addr[11:5]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" ("); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_ram_state_and_ctag_cset$DOB[22]) + $write("CTAG_CLEAN"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_ram_state_and_ctag_cset$DOB[22]) + $write("CTAG_EMPTY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_ram_state_and_ctag_cset$DOB[22]) + $write(", 0x%0x", cache_ram_state_and_ctag_cset$DOB[21:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_ram_state_and_ctag_cset$DOB[22]) + $write(", --"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(")"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" 0x%0x", cache_ram_word64_set$DOB); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" TLB result: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("VM_Xlate_Result { ", "outcome: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("VM_XLATE_OK"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "pa: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'hA, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d358) + begin + v__h15442 = $stime; + #0; + end + v__h15436 = v__h15442 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d358) + $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", + v__h15436, + "D_MMU_Cache", + cache_rg_addr, + word64__h7969, + 64'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__54_BITS__ETC___d160 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO LR: reserving PA 0x%0h", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d358) + $display(" Read-hit: addr 0x%0h word64 0x%0h", + cache_rg_addr, + word64__h7969); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_0_34_OR_cache_rg_op_33_EQ_2__ETC___d371) + $display(" Read Miss: -> CACHE_START_REFILL."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7_36_BITS_6_TO_2_37_EQ_0b10__ETC___d375) + $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", + cache_rg_lrsc_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd1 && + cache_rg_addr_29_EQ_cache_rg_lrsc_pa_47___d200 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" ST: cancelling LR/SC reservation for PA", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + cache_rg_lrsc_valid && + !cache_rg_lrsc_pa_47_EQ_cache_rg_addr_29___d148 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", + cache_rg_lrsc_pa, + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + !cache_rg_lrsc_valid && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC: fail due to invalid LR/SC reservation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC result = %0d", lrsc_result__h15819); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549) + $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549) + $write(" New Word64_Set:"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549) + $write(" 0x%0x", + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d443); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d549) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_33_EQ_2_35_69_OR_NOT_cache_rg__ETC___d551) + $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d557) + $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + NOT_cache_rg_op_33_EQ_0_34_68_AND_NOT_cache_rg_ETC___d557) + $display(" => rl_write_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_2_35_AND_cache_rg_amo_funct7_ETC___d561) + begin + v__h19086 = $stime; + #0; + end + v__h19080 = v__h19086 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_2_35_AND_cache_rg_amo_funct7_ETC___d561) + $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", + v__h19080, + "D_MMU_Cache", + cache_rg_addr, + 64'd1, + 64'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op_33_EQ_2_35_AND_cache_rg_amo_funct7_ETC___d561) + $display(" AMO SC: Fail response for addr 0x%0h", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d565) + $display(" AMO Miss: -> CACHE_START_REFILL."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", + cache_rg_addr, + cache_rg_amo_funct7, + cache_rg_f3, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $display(" PA 0x%0h ", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $display(" Cache word64 0x%0h, load-result 0x%0h", + word64__h7969, + word64__h7969); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $display(" 0x%0h op 0x%0h -> 0x%0h", + word64__h7969, + word64__h7969, + new_st_val__h19308); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $write(" New Word64_Set:"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $write(" 0x%0x", + IF_cache_rg_f3_21_EQ_0b0_22_THEN_IF_cache_rg_a_ETC___d517); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map_m_is_mem_addr_0_CONCAT_cache_rg__ETC___d570) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_soc_map$m_is_mem_addr && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_33_EQ_1_41_08_AND_NOT_cache_rg_ETC___d572) + $display(" AMO_op: cancelling LR/SC reservation for PA", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + !cache_soc_map$m_is_mem_addr && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => IO_REQ"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h22330 = $stime; + #0; + end + v__h22324 = v__h22330 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_start_cache_refill: ", v__h22324, "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cline_fabric_addr__h22383); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd3); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'b011, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" Victim way %0d; => CACHE_REFILL", 1'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_rereq && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", + cache_rg_addr[11:5], + cache_rg_addr[11:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h25145 = $stime; + #0; + end + v__h25139 = v__h25145 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", + v__h25139, + "D_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", fabric_addr__h27309); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", size_val__h27412, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_maintain_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26849 = $stime; + #0; + end + v__h26843 = v__h26849 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_maintain_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h26843, + "D_MMU_Cache", + cache_rg_addr, + cache_rg_ld_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26929 = $stime; + #0; + end + v__h26923 = v__h26929 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h26923, + "D_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27139 = $stime; + #0; + end + v__h27133 = v__h27139 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h27133, + "D_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" FAIL due to I/O address."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27257 = $stime; + #0; + end + v__h27251 = v__h27257 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", + v__h27251, + "D_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", fabric_addr__h27309); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", size_val__h27412, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h30743 = $stime; + #0; + end + v__h30737 = v__h30743 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("%0d: %s.rl_discard_write_rsp: pending %0d ", + v__h30737, + "D_MMU_Cache", + $unsigned(b__h22284)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_bff_rv$port1__read[5:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + begin + v__h30704 = $stime; + #0; + end + v__h30698 = v__h30704 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", + v__h30698, + "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("'h%h", cache_master_xactor_shim_bff_rv$port1__read[5:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0 && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd1 && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_reset && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h6060 = $stime; + #0; + end + v__h6054 = v__h6060 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_reset && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_start_reset", v__h6054, "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + begin + v__h23274 = $stime; + #0; + end + v__h23268 = v__h23274 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $display("%0d: %s.rl_cache_refill_rsps_loop:", + v__h23268, + "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h23536 = $stime; + #0; + end + v__h23530 = v__h23536 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", + v__h23530, + "D_MMU_Cache", + access_exc_code__h4779); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 && + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_rg_error_during_refill) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => MODULE_EXCEPTION_RSP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + !cache_rg_error_during_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => CACHE_REREQ"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", + cache_rg_word64_set_in_cache, + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(" 0x%0x", cache_ram_word64_set$DOB); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write(" 0x%0x", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_02___d603) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h25517 = $stime; + #0; + end + v__h25511 = v__h25517 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", + v__h25511, + "D_MMU_Cache", + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26635 = $stime; + #0; + end + v__h26629 = v__h26635 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h26629, + "D_MMU_Cache", + cache_rg_addr, + ld_val__h25642); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26742 = $stime; + #0; + end + v__h26736 = v__h26742 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", + v__h26736, + "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27573 = $stime; + #0; + end + v__h27567 = v__h27573 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", + v__h27567, + "D_MMU_Cache", + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[70:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27768 = $stime; + #0; + end + v__h27762 = v__h27768 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h27762, + "D_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h30027 = $stime; + #0; + end + v__h30021 = v__h30027 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h30021, + "D_MMU_Cache", + cache_rg_addr, + new_ld_val__h27894); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27864 = $stime; + #0; + end + v__h27858 = v__h27864 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", + v__h27858, + "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h31126 = $stime; + #0; + end + v__h31120 = v__h31126 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("%0d: %s.req: op:", v__h31120, "D_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op == 2'd0) + $write("CACHE_LD"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op == 2'd1) + $write("CACHE_ST"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op != 2'd0 && + req_op != 2'd1) + $write("CACHE_AMO"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", + req_f3, + req_addr, + req_st_value); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b0) + $write("U"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b01) + $write("S"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b11) + $write("M"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv != 2'b0 && + req_priv != 2'b01 && + req_priv != 2'b11) + $write("RESERVED"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", + req_sstatus_SUM, + req_mstatus_MXR, + req_satp, + "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" amo_funct7 = 0x%0h", req_amo_funct7); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && + req_f3_BITS_1_TO_0_44_EQ_0b0_45_OR_req_f3_BITS_ETC___d974 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", + req_addr[11:5], + req_addr[11:3]); + end + // synopsys translate_on +endmodule // mkMMU_DCache + diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkMMU_ICache.v b/src_SSITH_P1/xilinx_ip/hdl/mkMMU_ICache.v new file mode 100644 index 00000000..9fd496a1 --- /dev/null +++ b/src_SSITH_P1/xilinx_ip/hdl/mkMMU_ICache.v @@ -0,0 +1,5472 @@ +// +// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) +// +// On Tue Jul 9 16:18:43 BST 2019 +// +// +// Ports: +// Name I/O size props +// RDY_set_verbosity O 1 const +// RDY_server_reset_request_put O 1 reg +// RDY_server_reset_response_get O 1 +// valid O 1 +// addr O 32 reg +// word64 O 64 +// st_amo_val O 64 +// exc O 1 +// exc_code O 4 reg +// RDY_server_flush_request_put O 1 reg +// RDY_server_flush_response_get O 1 +// RDY_tlb_flush O 1 const +// mem_master_awid O 5 +// mem_master_awaddr O 64 +// mem_master_awlen O 8 +// mem_master_awsize O 3 +// mem_master_awburst O 2 +// mem_master_awlock O 1 +// mem_master_awcache O 4 +// mem_master_awprot O 3 +// mem_master_awqos O 4 +// mem_master_awregion O 4 +// mem_master_awvalid O 1 +// mem_master_wdata O 64 +// mem_master_wstrb O 8 +// mem_master_wlast O 1 +// mem_master_wvalid O 1 +// mem_master_bready O 1 +// mem_master_arid O 5 +// mem_master_araddr O 64 +// mem_master_arlen O 8 +// mem_master_arsize O 3 +// mem_master_arburst O 2 +// mem_master_arlock O 1 +// mem_master_arcache O 4 +// mem_master_arprot O 3 +// mem_master_arqos O 4 +// mem_master_arregion O 4 +// mem_master_arvalid O 1 +// mem_master_rready O 1 +// CLK I 1 clock +// RST_N I 1 reset +// set_verbosity_verbosity I 4 reg +// req_op I 2 +// req_f3 I 3 +// req_amo_funct7 I 7 reg +// req_addr I 32 +// req_st_value I 64 +// req_priv I 2 unused +// req_sstatus_SUM I 1 unused +// req_mstatus_MXR I 1 unused +// req_satp I 32 unused +// mem_master_awready I 1 +// mem_master_wready I 1 +// mem_master_bid I 5 +// mem_master_bresp I 2 +// mem_master_arready I 1 +// mem_master_rid I 5 +// mem_master_rdata I 64 +// mem_master_rresp I 2 +// mem_master_rlast I 1 +// EN_set_verbosity I 1 +// EN_server_reset_request_put I 1 +// EN_server_reset_response_get I 1 +// EN_req I 1 +// EN_server_flush_request_put I 1 +// EN_server_flush_response_get I 1 +// EN_tlb_flush I 1 unused +// mem_master_bvalid I 1 +// mem_master_rvalid I 1 +// +// Combinational paths from inputs to outputs: +// (mem_master_rid, +// mem_master_rdata, +// mem_master_rresp, +// mem_master_rlast, +// mem_master_rvalid) -> valid +// (mem_master_rid, +// mem_master_rdata, +// mem_master_rresp, +// mem_master_rlast, +// mem_master_rvalid) -> word64 +// EN_req -> mem_master_arid +// EN_req -> mem_master_araddr +// EN_req -> mem_master_arlen +// EN_req -> mem_master_arsize +// EN_req -> mem_master_arburst +// EN_req -> mem_master_arlock +// EN_req -> mem_master_arcache +// EN_req -> mem_master_arprot +// EN_req -> mem_master_arqos +// EN_req -> mem_master_arregion +// EN_req -> mem_master_aruser +// EN_req -> mem_master_arvalid +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkMMU_ICache(CLK, + RST_N, + + set_verbosity_verbosity, + EN_set_verbosity, + RDY_set_verbosity, + + EN_server_reset_request_put, + RDY_server_reset_request_put, + + EN_server_reset_response_get, + RDY_server_reset_response_get, + + req_op, + req_f3, + req_amo_funct7, + req_addr, + req_st_value, + req_priv, + req_sstatus_SUM, + req_mstatus_MXR, + req_satp, + EN_req, + + valid, + + addr, + + word64, + + st_amo_val, + + exc, + + exc_code, + + EN_server_flush_request_put, + RDY_server_flush_request_put, + + EN_server_flush_response_get, + RDY_server_flush_response_get, + + EN_tlb_flush, + RDY_tlb_flush, + + mem_master_awid, + + mem_master_awaddr, + + mem_master_awlen, + + mem_master_awsize, + + mem_master_awburst, + + mem_master_awlock, + + mem_master_awcache, + + mem_master_awprot, + + mem_master_awqos, + + mem_master_awregion, + + mem_master_awvalid, + + mem_master_awready, + + mem_master_wdata, + + mem_master_wstrb, + + mem_master_wlast, + + mem_master_wvalid, + + mem_master_wready, + + mem_master_bid, + mem_master_bresp, + mem_master_bvalid, + + mem_master_bready, + + mem_master_arid, + + mem_master_araddr, + + mem_master_arlen, + + mem_master_arsize, + + mem_master_arburst, + + mem_master_arlock, + + mem_master_arcache, + + mem_master_arprot, + + mem_master_arqos, + + mem_master_arregion, + + mem_master_arvalid, + + mem_master_arready, + + mem_master_rid, + mem_master_rdata, + mem_master_rresp, + mem_master_rlast, + mem_master_rvalid, + + mem_master_rready); + input CLK; + input RST_N; + + // action method set_verbosity + input [3 : 0] set_verbosity_verbosity; + input EN_set_verbosity; + output RDY_set_verbosity; + + // action method server_reset_request_put + input EN_server_reset_request_put; + output RDY_server_reset_request_put; + + // action method server_reset_response_get + input EN_server_reset_response_get; + output RDY_server_reset_response_get; + + // action method req + input [1 : 0] req_op; + input [2 : 0] req_f3; + input [6 : 0] req_amo_funct7; + input [31 : 0] req_addr; + input [63 : 0] req_st_value; + input [1 : 0] req_priv; + input req_sstatus_SUM; + input req_mstatus_MXR; + input [31 : 0] req_satp; + input EN_req; + + // value method valid + output valid; + + // value method addr + output [31 : 0] addr; + + // value method word64 + output [63 : 0] word64; + + // value method st_amo_val + output [63 : 0] st_amo_val; + + // value method exc + output exc; + + // value method exc_code + output [3 : 0] exc_code; + + // action method server_flush_request_put + input EN_server_flush_request_put; + output RDY_server_flush_request_put; + + // action method server_flush_response_get + input EN_server_flush_response_get; + output RDY_server_flush_response_get; + + // action method tlb_flush + input EN_tlb_flush; + output RDY_tlb_flush; + + // value method mem_master_aw_awid + output [4 : 0] mem_master_awid; + + // value method mem_master_aw_awaddr + output [63 : 0] mem_master_awaddr; + + // value method mem_master_aw_awlen + output [7 : 0] mem_master_awlen; + + // value method mem_master_aw_awsize + output [2 : 0] mem_master_awsize; + + // value method mem_master_aw_awburst + output [1 : 0] mem_master_awburst; + + // value method mem_master_aw_awlock + output mem_master_awlock; + + // value method mem_master_aw_awcache + output [3 : 0] mem_master_awcache; + + // value method mem_master_aw_awprot + output [2 : 0] mem_master_awprot; + + // value method mem_master_aw_awqos + output [3 : 0] mem_master_awqos; + + // value method mem_master_aw_awregion + output [3 : 0] mem_master_awregion; + + // value method mem_master_aw_awuser + + // value method mem_master_aw_awvalid + output mem_master_awvalid; + + // action method mem_master_aw_awready + input mem_master_awready; + + // value method mem_master_w_wdata + output [63 : 0] mem_master_wdata; + + // value method mem_master_w_wstrb + output [7 : 0] mem_master_wstrb; + + // value method mem_master_w_wlast + output mem_master_wlast; + + // value method mem_master_w_wuser + + // value method mem_master_w_wvalid + output mem_master_wvalid; + + // action method mem_master_w_wready + input mem_master_wready; + + // action method mem_master_b_bflit + input [4 : 0] mem_master_bid; + input [1 : 0] mem_master_bresp; + input mem_master_bvalid; + + // value method mem_master_b_bready + output mem_master_bready; + + // value method mem_master_ar_arid + output [4 : 0] mem_master_arid; + + // value method mem_master_ar_araddr + output [63 : 0] mem_master_araddr; + + // value method mem_master_ar_arlen + output [7 : 0] mem_master_arlen; + + // value method mem_master_ar_arsize + output [2 : 0] mem_master_arsize; + + // value method mem_master_ar_arburst + output [1 : 0] mem_master_arburst; + + // value method mem_master_ar_arlock + output mem_master_arlock; + + // value method mem_master_ar_arcache + output [3 : 0] mem_master_arcache; + + // value method mem_master_ar_arprot + output [2 : 0] mem_master_arprot; + + // value method mem_master_ar_arqos + output [3 : 0] mem_master_arqos; + + // value method mem_master_ar_arregion + output [3 : 0] mem_master_arregion; + + // value method mem_master_ar_aruser + + // value method mem_master_ar_arvalid + output mem_master_arvalid; + + // action method mem_master_ar_arready + input mem_master_arready; + + // action method mem_master_r_rflit + input [4 : 0] mem_master_rid; + input [63 : 0] mem_master_rdata; + input [1 : 0] mem_master_rresp; + input mem_master_rlast; + input mem_master_rvalid; + + // value method mem_master_r_rready + output mem_master_rready; + + // signals for module outputs + reg [63 : 0] word64; + wire [63 : 0] mem_master_araddr, + mem_master_awaddr, + mem_master_wdata, + st_amo_val; + wire [31 : 0] addr; + wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb; + wire [4 : 0] mem_master_arid, mem_master_awid; + wire [3 : 0] exc_code, + mem_master_arcache, + mem_master_arqos, + mem_master_arregion, + mem_master_awcache, + mem_master_awqos, + mem_master_awregion; + wire [2 : 0] mem_master_arprot, + mem_master_arsize, + mem_master_awprot, + mem_master_awsize; + wire [1 : 0] mem_master_arburst, mem_master_awburst; + wire RDY_server_flush_request_put, + RDY_server_flush_response_get, + RDY_server_reset_request_put, + RDY_server_reset_response_get, + RDY_set_verbosity, + RDY_tlb_flush, + exc, + mem_master_arlock, + mem_master_arvalid, + mem_master_awlock, + mem_master_awvalid, + mem_master_bready, + mem_master_rready, + mem_master_wlast, + mem_master_wvalid, + valid; + + // inlined wires + wire [98 : 0] cache_master_xactor_shim_arff_rv$port0__write_1, + cache_master_xactor_shim_arff_rv$port1__read, + cache_master_xactor_shim_arff_rv$port2__read, + cache_master_xactor_shim_arff_rv$port3__read, + cache_master_xactor_shim_awff_rv$port0__write_1, + cache_master_xactor_shim_awff_rv$port1__read, + cache_master_xactor_shim_awff_rv$port2__read, + cache_master_xactor_shim_awff_rv$port3__read; + wire [73 : 0] cache_master_xactor_shim_wff_rv$port0__write_1, + cache_master_xactor_shim_wff_rv$port1__read, + cache_master_xactor_shim_wff_rv$port2__read, + cache_master_xactor_shim_wff_rv$port3__read; + wire [72 : 0] cache_master_xactor_shim_rff_rv$port0__write_1, + cache_master_xactor_shim_rff_rv$port1__read, + cache_master_xactor_shim_rff_rv$port2__read, + cache_master_xactor_shim_rff_rv$port3__read; + wire [71 : 0] cache_master_xactor_ug_master_u_r_putWire$wget; + wire [10 : 0] cache_crg_sb_to_load_delay$port0__write_1, + cache_crg_sb_to_load_delay$port2__read; + wire [7 : 0] cache_master_xactor_shim_bff_rv$port0__write_1, + cache_master_xactor_shim_bff_rv$port1__read, + cache_master_xactor_shim_bff_rv$port2__read, + cache_master_xactor_shim_bff_rv$port3__read; + wire [6 : 0] cache_master_xactor_ug_master_u_b_putWire$wget; + wire [3 : 0] cache_ctr_wr_rsps_pending_crg$port0__write_1, + cache_ctr_wr_rsps_pending_crg$port1__write_1, + cache_ctr_wr_rsps_pending_crg$port2__read, + cache_ctr_wr_rsps_pending_crg$port3__read; + wire cache_crg_sb_to_load_delay$EN_port1__write, + cache_dw_valid$whas, + cache_master_xactor_shim_arff_rv$EN_port0__write, + cache_master_xactor_shim_rff_rv$EN_port1__write, + cache_master_xactor_ug_master_u_ar_dropWire$whas, + cache_master_xactor_ug_master_u_aw_dropWire$whas, + cache_master_xactor_ug_master_u_b_putWire$whas, + cache_master_xactor_ug_master_u_r_putWire$whas, + cache_master_xactor_ug_master_u_w_dropWire$whas; + + // register cache_cfg_verbosity + reg [3 : 0] cache_cfg_verbosity; + wire [3 : 0] cache_cfg_verbosity$D_IN; + wire cache_cfg_verbosity$EN; + + // register cache_crg_sb_to_load_delay + reg [10 : 0] cache_crg_sb_to_load_delay; + wire [10 : 0] cache_crg_sb_to_load_delay$D_IN; + wire cache_crg_sb_to_load_delay$EN; + + // register cache_ctr_wr_rsps_pending_crg + reg [3 : 0] cache_ctr_wr_rsps_pending_crg; + wire [3 : 0] cache_ctr_wr_rsps_pending_crg$D_IN; + wire cache_ctr_wr_rsps_pending_crg$EN; + + // register cache_master_xactor_clearing + reg cache_master_xactor_clearing; + wire cache_master_xactor_clearing$D_IN, cache_master_xactor_clearing$EN; + + // register cache_master_xactor_shim_arff_rv + reg [98 : 0] cache_master_xactor_shim_arff_rv; + wire [98 : 0] cache_master_xactor_shim_arff_rv$D_IN; + wire cache_master_xactor_shim_arff_rv$EN; + + // register cache_master_xactor_shim_awff_rv + reg [98 : 0] cache_master_xactor_shim_awff_rv; + wire [98 : 0] cache_master_xactor_shim_awff_rv$D_IN; + wire cache_master_xactor_shim_awff_rv$EN; + + // register cache_master_xactor_shim_bff_rv + reg [7 : 0] cache_master_xactor_shim_bff_rv; + wire [7 : 0] cache_master_xactor_shim_bff_rv$D_IN; + wire cache_master_xactor_shim_bff_rv$EN; + + // register cache_master_xactor_shim_rff_rv + reg [72 : 0] cache_master_xactor_shim_rff_rv; + wire [72 : 0] cache_master_xactor_shim_rff_rv$D_IN; + wire cache_master_xactor_shim_rff_rv$EN; + + // register cache_master_xactor_shim_wff_rv + reg [73 : 0] cache_master_xactor_shim_wff_rv; + wire [73 : 0] cache_master_xactor_shim_wff_rv$D_IN; + wire cache_master_xactor_shim_wff_rv$EN; + + // register cache_rg_addr + reg [31 : 0] cache_rg_addr; + wire [31 : 0] cache_rg_addr$D_IN; + wire cache_rg_addr$EN; + + // register cache_rg_amo_funct7 + reg [6 : 0] cache_rg_amo_funct7; + wire [6 : 0] cache_rg_amo_funct7$D_IN; + wire cache_rg_amo_funct7$EN; + + // register cache_rg_cset_in_cache + reg [6 : 0] cache_rg_cset_in_cache; + wire [6 : 0] cache_rg_cset_in_cache$D_IN; + wire cache_rg_cset_in_cache$EN; + + // register cache_rg_error_during_refill + reg cache_rg_error_during_refill; + wire cache_rg_error_during_refill$D_IN, cache_rg_error_during_refill$EN; + + // register cache_rg_exc_code + reg [3 : 0] cache_rg_exc_code; + reg [3 : 0] cache_rg_exc_code$D_IN; + wire cache_rg_exc_code$EN; + + // register cache_rg_f3 + reg [2 : 0] cache_rg_f3; + wire [2 : 0] cache_rg_f3$D_IN; + wire cache_rg_f3$EN; + + // register cache_rg_ld_val + reg [63 : 0] cache_rg_ld_val; + reg [63 : 0] cache_rg_ld_val$D_IN; + wire cache_rg_ld_val$EN; + + // register cache_rg_lower_word32 + reg [31 : 0] cache_rg_lower_word32; + wire [31 : 0] cache_rg_lower_word32$D_IN; + wire cache_rg_lower_word32$EN; + + // register cache_rg_lower_word32_full + reg cache_rg_lower_word32_full; + wire cache_rg_lower_word32_full$D_IN, cache_rg_lower_word32_full$EN; + + // register cache_rg_lrsc_pa + reg [31 : 0] cache_rg_lrsc_pa; + wire [31 : 0] cache_rg_lrsc_pa$D_IN; + wire cache_rg_lrsc_pa$EN; + + // register cache_rg_lrsc_valid + reg cache_rg_lrsc_valid; + wire cache_rg_lrsc_valid$D_IN, cache_rg_lrsc_valid$EN; + + // register cache_rg_op + reg [1 : 0] cache_rg_op; + wire [1 : 0] cache_rg_op$D_IN; + wire cache_rg_op$EN; + + // register cache_rg_pa + reg [31 : 0] cache_rg_pa; + wire [31 : 0] cache_rg_pa$D_IN; + wire cache_rg_pa$EN; + + // register cache_rg_pte_pa + reg [31 : 0] cache_rg_pte_pa; + wire [31 : 0] cache_rg_pte_pa$D_IN; + wire cache_rg_pte_pa$EN; + + // register cache_rg_st_amo_val + reg [63 : 0] cache_rg_st_amo_val; + wire [63 : 0] cache_rg_st_amo_val$D_IN; + wire cache_rg_st_amo_val$EN; + + // register cache_rg_state + reg [3 : 0] cache_rg_state; + reg [3 : 0] cache_rg_state$D_IN; + wire cache_rg_state$EN; + + // register cache_rg_word64_set_in_cache + reg [8 : 0] cache_rg_word64_set_in_cache; + wire [8 : 0] cache_rg_word64_set_in_cache$D_IN; + wire cache_rg_word64_set_in_cache$EN; + + // ports of submodule cache_f_fabric_write_reqs + reg [98 : 0] cache_f_fabric_write_reqs$D_IN; + wire [98 : 0] cache_f_fabric_write_reqs$D_OUT; + wire cache_f_fabric_write_reqs$CLR, + cache_f_fabric_write_reqs$DEQ, + cache_f_fabric_write_reqs$EMPTY_N, + cache_f_fabric_write_reqs$ENQ, + cache_f_fabric_write_reqs$FULL_N; + + // ports of submodule cache_f_reset_reqs + wire cache_f_reset_reqs$CLR, + cache_f_reset_reqs$DEQ, + cache_f_reset_reqs$D_IN, + cache_f_reset_reqs$D_OUT, + cache_f_reset_reqs$EMPTY_N, + cache_f_reset_reqs$ENQ, + cache_f_reset_reqs$FULL_N; + + // ports of submodule cache_f_reset_rsps + wire cache_f_reset_rsps$CLR, + cache_f_reset_rsps$DEQ, + cache_f_reset_rsps$D_IN, + cache_f_reset_rsps$D_OUT, + cache_f_reset_rsps$EMPTY_N, + cache_f_reset_rsps$ENQ, + cache_f_reset_rsps$FULL_N; + + // ports of submodule cache_ram_state_and_ctag_cset + wire [22 : 0] cache_ram_state_and_ctag_cset$DIA, + cache_ram_state_and_ctag_cset$DIB, + cache_ram_state_and_ctag_cset$DOB; + wire [6 : 0] cache_ram_state_and_ctag_cset$ADDRA, + cache_ram_state_and_ctag_cset$ADDRB; + wire cache_ram_state_and_ctag_cset$ENA, + cache_ram_state_and_ctag_cset$ENB, + cache_ram_state_and_ctag_cset$WEA, + cache_ram_state_and_ctag_cset$WEB; + + // ports of submodule cache_ram_word64_set + reg [63 : 0] cache_ram_word64_set$DIB; + reg [8 : 0] cache_ram_word64_set$ADDRB; + wire [63 : 0] cache_ram_word64_set$DIA, cache_ram_word64_set$DOB; + wire [8 : 0] cache_ram_word64_set$ADDRA; + wire cache_ram_word64_set$ENA, + cache_ram_word64_set$ENB, + cache_ram_word64_set$WEA, + cache_ram_word64_set$WEB; + + // ports of submodule cache_soc_map + wire [63 : 0] cache_soc_map$m_is_IO_addr_addr, + cache_soc_map$m_is_mem_addr_addr, + cache_soc_map$m_is_near_mem_IO_addr_addr; + + // rule scheduling signals + wire CAN_FIRE_RL_cache_master_xactor_do_clear, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek, + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop, + CAN_FIRE_RL_cache_rl_ST_AMO_response, + CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop, + CAN_FIRE_RL_cache_rl_discard_write_rsp, + CAN_FIRE_RL_cache_rl_drive_exception_rsp, + CAN_FIRE_RL_cache_rl_fabric_send_write_req, + CAN_FIRE_RL_cache_rl_io_AMO_SC_req, + CAN_FIRE_RL_cache_rl_io_AMO_op_req, + CAN_FIRE_RL_cache_rl_io_AMO_read_rsp, + CAN_FIRE_RL_cache_rl_io_read_req, + CAN_FIRE_RL_cache_rl_io_read_rsp, + CAN_FIRE_RL_cache_rl_io_write_req, + CAN_FIRE_RL_cache_rl_maintain_io_read_rsp, + CAN_FIRE_RL_cache_rl_probe_and_immed_rsp, + CAN_FIRE_RL_cache_rl_rereq, + CAN_FIRE_RL_cache_rl_reset, + CAN_FIRE_RL_cache_rl_shift_sb_to_load_delay, + CAN_FIRE_RL_cache_rl_start_cache_refill, + CAN_FIRE_RL_cache_rl_start_reset, + CAN_FIRE_mem_master_ar_arready, + CAN_FIRE_mem_master_aw_awready, + CAN_FIRE_mem_master_b_bflit, + CAN_FIRE_mem_master_r_rflit, + CAN_FIRE_mem_master_w_wready, + CAN_FIRE_req, + CAN_FIRE_server_flush_request_put, + CAN_FIRE_server_flush_response_get, + CAN_FIRE_server_reset_request_put, + CAN_FIRE_server_reset_response_get, + CAN_FIRE_set_verbosity, + CAN_FIRE_tlb_flush, + WILL_FIRE_RL_cache_master_xactor_do_clear, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek, + WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop, + WILL_FIRE_RL_cache_rl_ST_AMO_response, + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop, + WILL_FIRE_RL_cache_rl_discard_write_rsp, + WILL_FIRE_RL_cache_rl_drive_exception_rsp, + WILL_FIRE_RL_cache_rl_fabric_send_write_req, + WILL_FIRE_RL_cache_rl_io_AMO_SC_req, + WILL_FIRE_RL_cache_rl_io_AMO_op_req, + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp, + WILL_FIRE_RL_cache_rl_io_read_req, + WILL_FIRE_RL_cache_rl_io_read_rsp, + WILL_FIRE_RL_cache_rl_io_write_req, + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp, + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp, + WILL_FIRE_RL_cache_rl_rereq, + WILL_FIRE_RL_cache_rl_reset, + WILL_FIRE_RL_cache_rl_shift_sb_to_load_delay, + WILL_FIRE_RL_cache_rl_start_cache_refill, + WILL_FIRE_RL_cache_rl_start_reset, + WILL_FIRE_mem_master_ar_arready, + WILL_FIRE_mem_master_aw_awready, + WILL_FIRE_mem_master_b_bflit, + WILL_FIRE_mem_master_r_rflit, + WILL_FIRE_mem_master_w_wready, + WILL_FIRE_req, + WILL_FIRE_server_flush_request_put, + WILL_FIRE_server_flush_response_get, + WILL_FIRE_server_reset_request_put, + WILL_FIRE_server_reset_response_get, + WILL_FIRE_set_verbosity, + WILL_FIRE_tlb_flush; + + // inputs to muxes for submodule ports + wire [98 : 0] MUX_cache_f_fabric_write_reqs$enq_1__VAL_1, + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2, + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3, + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1, + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2; + wire [63 : 0] MUX_cache_dw_output_ld_val$wset_1__VAL_3, + MUX_cache_ram_word64_set$a_put_3__VAL_2, + MUX_cache_rg_ld_val$write_1__VAL_2; + wire [22 : 0] MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1; + wire [8 : 0] MUX_cache_ram_word64_set$b_put_2__VAL_2, + MUX_cache_ram_word64_set$b_put_2__VAL_4; + wire [6 : 0] MUX_cache_rg_cset_in_cache$write_1__VAL_1; + wire [3 : 0] MUX_cache_rg_exc_code$write_1__VAL_1, + MUX_cache_rg_state$write_1__VAL_1, + MUX_cache_rg_state$write_1__VAL_12, + MUX_cache_rg_state$write_1__VAL_2, + MUX_cache_rg_state$write_1__VAL_4; + wire MUX_cache_dw_output_ld_val$wset_1__SEL_1, + MUX_cache_dw_output_ld_val$wset_1__SEL_2, + MUX_cache_dw_output_ld_val$wset_1__SEL_3, + MUX_cache_dw_output_ld_val$wset_1__SEL_4, + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2, + MUX_cache_master_xactor_clearing$write_1__SEL_2, + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1, + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1, + MUX_cache_ram_word64_set$a_put_1__SEL_1, + MUX_cache_ram_word64_set$b_put_1__SEL_2, + MUX_cache_rg_error_during_refill$write_1__SEL_1, + MUX_cache_rg_exc_code$write_1__SEL_1, + MUX_cache_rg_exc_code$write_1__SEL_2, + MUX_cache_rg_exc_code$write_1__SEL_3, + MUX_cache_rg_ld_val$write_1__SEL_2, + MUX_cache_rg_lrsc_valid$write_1__SEL_2, + MUX_cache_rg_state$write_1__SEL_12, + MUX_cache_rg_state$write_1__SEL_13, + MUX_cache_rg_state$write_1__SEL_4; + + // declarations used by system tasks + // synopsys translate_off + reg [31 : 0] v__h5641; + reg [31 : 0] v__h6477; + reg [31 : 0] v__h6580; + reg [31 : 0] v__h7034; + reg [31 : 0] v__h15467; + reg [31 : 0] v__h19180; + reg [31 : 0] v__h22537; + reg [31 : 0] v__h25370; + reg [31 : 0] v__h27092; + reg [31 : 0] v__h27175; + reg [31 : 0] v__h27388; + reg [31 : 0] v__h27509; + reg [31 : 0] v__h31052; + reg [31 : 0] v__h31013; + reg [31 : 0] v__h6102; + reg [31 : 0] v__h23486; + reg [31 : 0] v__h23740; + reg [31 : 0] v__h25756; + reg [31 : 0] v__h26874; + reg [31 : 0] v__h26982; + reg [31 : 0] v__h27839; + reg [31 : 0] v__h28034; + reg [31 : 0] v__h30336; + reg [31 : 0] v__h28131; + reg [31 : 0] v__h31440; + reg [31 : 0] v__h5635; + reg [31 : 0] v__h6096; + reg [31 : 0] v__h6471; + reg [31 : 0] v__h6574; + reg [31 : 0] v__h7028; + reg [31 : 0] v__h15461; + reg [31 : 0] v__h19174; + reg [31 : 0] v__h22531; + reg [31 : 0] v__h23480; + reg [31 : 0] v__h23734; + reg [31 : 0] v__h25364; + reg [31 : 0] v__h25750; + reg [31 : 0] v__h26868; + reg [31 : 0] v__h26976; + reg [31 : 0] v__h27086; + reg [31 : 0] v__h27169; + reg [31 : 0] v__h27382; + reg [31 : 0] v__h27503; + reg [31 : 0] v__h27833; + reg [31 : 0] v__h28028; + reg [31 : 0] v__h28125; + reg [31 : 0] v__h30330; + reg [31 : 0] v__h31007; + reg [31 : 0] v__h31046; + reg [31 : 0] v__h31434; + // synopsys translate_on + + // remaining internal signals + reg [63 : 0] CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37, + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820, + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428, + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502, + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371, + _theResult_____2__h19690, + _theResult_____2__h28207, + ld_val__h25881, + mem_req_wr_data_wdata__h5366, + new_ld_val__h28161, + new_value__h18271, + new_value__h8173, + w1__h19682, + w1__h28195, + w1__h28199; + reg [7 : 0] mem_req_wr_data_wstrb__h5367; + reg [2 : 0] _theResult___snd_snd_val__h5250, size_val__h27675; + wire [97 : 0] cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22, + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20; + wire [72 : 0] cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q21; + wire [63 : 0] IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d338, + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821, + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434, + IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d514, + _theResult___fst__h5232, + b__h19806, + b__h28323, + b__h30158, + cline_fabric_addr__h22590, + fabric_addr__h27561, + mem_req_wr_addr_awaddr__h5054, + new_st_val__h19402, + new_st_val__h19697, + new_st_val__h19798, + new_st_val__h20791, + new_st_val__h20796, + new_st_val__h20801, + new_st_val__h20806, + new_st_val__h20814, + new_st_val__h20823, + new_st_val__h20831, + new_st_val__h28214, + new_st_val__h28315, + new_st_val__h30188, + new_st_val__h30193, + new_st_val__h30198, + new_st_val__h30203, + new_st_val__h30211, + new_st_val__h30220, + new_st_val__h30228, + result__h14584, + result__h14612, + result__h14640, + result__h14668, + result__h14696, + result__h14724, + result__h14752, + result__h14797, + result__h14825, + result__h14853, + result__h14881, + result__h14909, + result__h14937, + result__h14965, + result__h14993, + result__h15038, + result__h15066, + result__h15094, + result__h15122, + result__h15163, + result__h15191, + result__h15219, + result__h15247, + result__h15288, + result__h15316, + result__h15355, + result__h15383, + result__h25941, + result__h25971, + result__h25998, + result__h26025, + result__h26052, + result__h26079, + result__h26106, + result__h26133, + result__h26177, + result__h26204, + result__h26231, + result__h26258, + result__h26285, + result__h26312, + result__h26339, + result__h26366, + result__h26410, + result__h26437, + result__h26464, + result__h26491, + result__h26531, + result__h26558, + result__h26585, + result__h26612, + result__h26652, + result__h26679, + result__h26717, + result__h26744, + result__h28412, + result__h29320, + result__h29348, + result__h29376, + result__h29404, + result__h29432, + result__h29460, + result__h29488, + result__h29533, + result__h29561, + result__h29589, + result__h29617, + result__h29645, + result__h29673, + result__h29701, + result__h29729, + result__h29774, + result__h29802, + result__h29830, + result__h29858, + result__h29899, + result__h29927, + result__h29955, + result__h29983, + result__h30024, + result__h30052, + result__h30091, + result__h30119, + result__h8228, + w1___1__h19764, + w1___1__h28281, + w2___1__h28282, + w2__h28201, + word64__h7992, + x__h15854, + x__h28190, + y__h8264; + wire [31 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q25, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q32, + cache_rg_st_amo_val_BITS_31_TO_0__q1, + cline_addr__h22589, + ld_val5881_BITS_31_TO_0__q41, + ld_val5881_BITS_63_TO_32__q48, + new_value173_BITS_31_TO_0__q17, + w18195_BITS_31_TO_0__q54, + word64992_BITS_31_TO_0__q4, + word64992_BITS_63_TO_32__q11; + wire [21 : 0] pa_ctag__h7888; + wire [15 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q24, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q28, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q31, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q35, + ld_val5881_BITS_15_TO_0__q40, + ld_val5881_BITS_31_TO_16__q44, + ld_val5881_BITS_47_TO_32__q47, + ld_val5881_BITS_63_TO_48__q51, + word64992_BITS_15_TO_0__q3, + word64992_BITS_31_TO_16__q7, + word64992_BITS_47_TO_32__q10, + word64992_BITS_63_TO_48__q14; + wire [7 : 0] cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q23, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q26, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q27, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q29, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q30, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q33, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q34, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q36, + ld_val5881_BITS_15_TO_8__q42, + ld_val5881_BITS_23_TO_16__q43, + ld_val5881_BITS_31_TO_24__q45, + ld_val5881_BITS_39_TO_32__q46, + ld_val5881_BITS_47_TO_40__q49, + ld_val5881_BITS_55_TO_48__q50, + ld_val5881_BITS_63_TO_56__q52, + ld_val5881_BITS_7_TO_0__q39, + strobe64__h5230, + strobe64__h5237, + strobe64__h5241, + word64992_BITS_15_TO_8__q5, + word64992_BITS_23_TO_16__q6, + word64992_BITS_31_TO_24__q8, + word64992_BITS_39_TO_32__q9, + word64992_BITS_47_TO_40__q12, + word64992_BITS_55_TO_48__q13, + word64992_BITS_63_TO_56__q15, + word64992_BITS_7_TO_0__q2; + wire [5 : 0] shift_bits__h5069; + wire [3 : 0] IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d347, + b__h22491; + wire IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d161, + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91, + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573, + NOT_cache_ram_state_and_ctag_cset_b_read__51_B_ETC___d186, + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d344, + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d513, + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528, + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d534, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d197, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d375, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d508, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d540, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542, + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d545, + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d373, + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d506, + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d526, + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d529, + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d532, + NOT_req_f3_BITS_1_TO_0_13_EQ_0b0_14_15_AND_NOT_ETC___d934, + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157, + cache_ram_state_and_ctag_cset_b_read__51_BIT_2_ETC___d187, + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184, + cache_rg_amo_funct7_32_BITS_6_TO_2_33_EQ_0b10__ETC___d363, + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d200, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d201, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d204, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d341, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d350, + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d360, + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d198, + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d376, + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d509, + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d511, + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d366, + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d537, + cache_rg_state_7_EQ_12_15_AND_cache_rg_op_29_E_ETC___d617, + cache_rg_state_7_EQ_3_63_AND_NOT_cache_rg_op_2_ETC___d172, + lrsc_result__h15844, + req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943; + + // action method set_verbosity + assign RDY_set_verbosity = 1'd1 ; + assign CAN_FIRE_set_verbosity = 1'd1 ; + assign WILL_FIRE_set_verbosity = EN_set_verbosity ; + + // action method server_reset_request_put + assign RDY_server_reset_request_put = cache_f_reset_reqs$FULL_N ; + assign CAN_FIRE_server_reset_request_put = cache_f_reset_reqs$FULL_N ; + assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; + + // action method server_reset_response_get + assign RDY_server_reset_response_get = + !cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign CAN_FIRE_server_reset_response_get = + !cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; + + // action method req + assign CAN_FIRE_req = 1'd1 ; + assign WILL_FIRE_req = EN_req ; + + // value method valid + assign valid = cache_dw_valid$whas ; + + // value method addr + assign addr = cache_rg_addr ; + + // value method word64 + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_1 or + ld_val__h25881 or + MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + new_ld_val__h28161 or + MUX_cache_dw_output_ld_val$wset_1__SEL_3 or + MUX_cache_dw_output_ld_val$wset_1__VAL_3 or + MUX_cache_dw_output_ld_val$wset_1__SEL_4 or cache_rg_ld_val) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h25881; + MUX_cache_dw_output_ld_val$wset_1__SEL_2: word64 = new_ld_val__h28161; + MUX_cache_dw_output_ld_val$wset_1__SEL_3: + word64 = MUX_cache_dw_output_ld_val$wset_1__VAL_3; + MUX_cache_dw_output_ld_val$wset_1__SEL_4: word64 = cache_rg_ld_val; + default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // value method st_amo_val + assign st_amo_val = + MUX_cache_dw_output_ld_val$wset_1__SEL_3 ? + 64'd0 : + cache_rg_st_amo_val ; + + // value method exc + assign exc = cache_rg_state == 4'd4 ; + + // value method exc_code + assign exc_code = cache_rg_exc_code ; + + // action method server_flush_request_put + assign RDY_server_flush_request_put = cache_f_reset_reqs$FULL_N ; + assign CAN_FIRE_server_flush_request_put = cache_f_reset_reqs$FULL_N ; + assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ; + + // action method server_flush_response_get + assign RDY_server_flush_response_get = + cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign CAN_FIRE_server_flush_response_get = + cache_f_reset_rsps$D_OUT && cache_f_reset_rsps$EMPTY_N ; + assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ; + + // action method tlb_flush + assign RDY_tlb_flush = 1'd1 ; + assign CAN_FIRE_tlb_flush = 1'd1 ; + assign WILL_FIRE_tlb_flush = EN_tlb_flush ; + + // value method mem_master_aw_awid + assign mem_master_awid = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[97:93] ; + + // value method mem_master_aw_awaddr + assign mem_master_awaddr = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[92:29] ; + + // value method mem_master_aw_awlen + assign mem_master_awlen = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[28:21] ; + + // value method mem_master_aw_awsize + assign mem_master_awsize = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[20:18] ; + + // value method mem_master_aw_awburst + assign mem_master_awburst = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[17:16] ; + + // value method mem_master_aw_awlock + assign mem_master_awlock = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[15] ; + + // value method mem_master_aw_awcache + assign mem_master_awcache = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[14:11] ; + + // value method mem_master_aw_awprot + assign mem_master_awprot = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[10:8] ; + + // value method mem_master_aw_awqos + assign mem_master_awqos = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[7:4] ; + + // value method mem_master_aw_awregion + assign mem_master_awregion = + cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20[3:0] ; + + // value method mem_master_aw_awvalid + assign mem_master_awvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek ; + + // action method mem_master_aw_awready + assign CAN_FIRE_mem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_mem_master_aw_awready = 1'd1 ; + + // value method mem_master_w_wdata + assign mem_master_wdata = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q21[72:9] ; + + // value method mem_master_w_wstrb + assign mem_master_wstrb = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q21[8:1] ; + + // value method mem_master_w_wlast + assign mem_master_wlast = + cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q21[0] ; + + // value method mem_master_w_wvalid + assign mem_master_wvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek ; + + // action method mem_master_w_wready + assign CAN_FIRE_mem_master_w_wready = 1'd1 ; + assign WILL_FIRE_mem_master_w_wready = 1'd1 ; + + // action method mem_master_b_bflit + assign CAN_FIRE_mem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_mem_master_b_bflit = mem_master_bvalid ; + + // value method mem_master_b_bready + assign mem_master_bready = !cache_master_xactor_shim_bff_rv[7] ; + + // value method mem_master_ar_arid + assign mem_master_arid = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[97:93] ; + + // value method mem_master_ar_araddr + assign mem_master_araddr = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[92:29] ; + + // value method mem_master_ar_arlen + assign mem_master_arlen = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[28:21] ; + + // value method mem_master_ar_arsize + assign mem_master_arsize = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[20:18] ; + + // value method mem_master_ar_arburst + assign mem_master_arburst = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[17:16] ; + + // value method mem_master_ar_arlock + assign mem_master_arlock = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[15] ; + + // value method mem_master_ar_arcache + assign mem_master_arcache = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[14:11] ; + + // value method mem_master_ar_arprot + assign mem_master_arprot = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[10:8] ; + + // value method mem_master_ar_arqos + assign mem_master_arqos = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[7:4] ; + + // value method mem_master_ar_arregion + assign mem_master_arregion = + cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22[3:0] ; + + // value method mem_master_ar_arvalid + assign mem_master_arvalid = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek ; + + // action method mem_master_ar_arready + assign CAN_FIRE_mem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_mem_master_ar_arready = 1'd1 ; + + // action method mem_master_r_rflit + assign CAN_FIRE_mem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_mem_master_r_rflit = mem_master_rvalid ; + + // value method mem_master_r_rready + assign mem_master_rready = !cache_master_xactor_shim_rff_rv[72] ; + + // submodule cache_f_fabric_write_reqs + FIFO2 #(.width(32'd99), + .guarded(32'd1)) cache_f_fabric_write_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_fabric_write_reqs$D_IN), + .ENQ(cache_f_fabric_write_reqs$ENQ), + .DEQ(cache_f_fabric_write_reqs$DEQ), + .CLR(cache_f_fabric_write_reqs$CLR), + .D_OUT(cache_f_fabric_write_reqs$D_OUT), + .FULL_N(cache_f_fabric_write_reqs$FULL_N), + .EMPTY_N(cache_f_fabric_write_reqs$EMPTY_N)); + + // submodule cache_f_reset_reqs + FIFO2 #(.width(32'd1), .guarded(32'd1)) cache_f_reset_reqs(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_reset_reqs$D_IN), + .ENQ(cache_f_reset_reqs$ENQ), + .DEQ(cache_f_reset_reqs$DEQ), + .CLR(cache_f_reset_reqs$CLR), + .D_OUT(cache_f_reset_reqs$D_OUT), + .FULL_N(cache_f_reset_reqs$FULL_N), + .EMPTY_N(cache_f_reset_reqs$EMPTY_N)); + + // submodule cache_f_reset_rsps + FIFO2 #(.width(32'd1), .guarded(32'd1)) cache_f_reset_rsps(.RST(RST_N), + .CLK(CLK), + .D_IN(cache_f_reset_rsps$D_IN), + .ENQ(cache_f_reset_rsps$ENQ), + .DEQ(cache_f_reset_rsps$DEQ), + .CLR(cache_f_reset_rsps$CLR), + .D_OUT(cache_f_reset_rsps$D_OUT), + .FULL_N(cache_f_reset_rsps$FULL_N), + .EMPTY_N(cache_f_reset_rsps$EMPTY_N)); + + // submodule cache_ram_state_and_ctag_cset + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd7), + .DATA_WIDTH(32'd23), + .MEMSIZE(8'd128)) cache_ram_state_and_ctag_cset(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(cache_ram_state_and_ctag_cset$ADDRA), + .ADDRB(cache_ram_state_and_ctag_cset$ADDRB), + .DIA(cache_ram_state_and_ctag_cset$DIA), + .DIB(cache_ram_state_and_ctag_cset$DIB), + .WEA(cache_ram_state_and_ctag_cset$WEA), + .WEB(cache_ram_state_and_ctag_cset$WEB), + .ENA(cache_ram_state_and_ctag_cset$ENA), + .ENB(cache_ram_state_and_ctag_cset$ENB), + .DOA(), + .DOB(cache_ram_state_and_ctag_cset$DOB)); + + // submodule cache_ram_word64_set + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd9), + .DATA_WIDTH(32'd64), + .MEMSIZE(10'd512)) cache_ram_word64_set(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(cache_ram_word64_set$ADDRA), + .ADDRB(cache_ram_word64_set$ADDRB), + .DIA(cache_ram_word64_set$DIA), + .DIB(cache_ram_word64_set$DIB), + .WEA(cache_ram_word64_set$WEA), + .WEB(cache_ram_word64_set$WEB), + .ENA(cache_ram_word64_set$ENA), + .ENB(cache_ram_word64_set$ENB), + .DOA(), + .DOB(cache_ram_word64_set$DOB)); + + // submodule cache_soc_map + mkSoC_Map cache_soc_map(.CLK(CLK), + .RST_N(RST_N), + .m_is_IO_addr_addr(cache_soc_map$m_is_IO_addr_addr), + .m_is_mem_addr_addr(cache_soc_map$m_is_mem_addr_addr), + .m_is_near_mem_IO_addr_addr(cache_soc_map$m_is_near_mem_IO_addr_addr), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), + .m_is_mem_addr(), + .m_is_IO_addr(), + .m_is_near_mem_IO_addr(), + .m_pc_reset_value(), + .m_mtvec_reset_value(), + .m_nmivec_reset_value()); + + // rule RL_cache_rl_fabric_send_write_req + assign CAN_FIRE_RL_cache_rl_fabric_send_write_req = + !cache_master_xactor_clearing && + cache_f_fabric_write_reqs$EMPTY_N && + !cache_master_xactor_shim_awff_rv[98] && + !cache_master_xactor_shim_wff_rv[73] ; + assign WILL_FIRE_RL_cache_rl_fabric_send_write_req = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ; + + // rule RL_cache_rl_reset + assign CAN_FIRE_RL_cache_rl_reset = + (cache_rg_cset_in_cache != 7'd127 || + cache_f_reset_reqs$EMPTY_N && cache_f_reset_rsps$FULL_N) && + cache_rg_state == 4'd1 ; + assign WILL_FIRE_RL_cache_rl_reset = CAN_FIRE_RL_cache_rl_reset ; + + // rule RL_cache_rl_shift_sb_to_load_delay + assign CAN_FIRE_RL_cache_rl_shift_sb_to_load_delay = 1'd1 ; + assign WILL_FIRE_RL_cache_rl_shift_sb_to_load_delay = 1'd1 ; + + // rule RL_cache_rl_probe_and_immed_rsp + assign CAN_FIRE_RL_cache_rl_probe_and_immed_rsp = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010 || + IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d161) && + cache_rg_state_7_EQ_3_63_AND_NOT_cache_rg_op_2_ETC___d172 ; + assign WILL_FIRE_RL_cache_rl_probe_and_immed_rsp = + CAN_FIRE_RL_cache_rl_probe_and_immed_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_start_cache_refill + assign CAN_FIRE_RL_cache_rl_start_cache_refill = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[98] && + cache_rg_state == 4'd8 && + b__h22491 == 4'd0 ; + assign WILL_FIRE_RL_cache_rl_start_cache_refill = + CAN_FIRE_RL_cache_rl_start_cache_refill && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_rereq + assign CAN_FIRE_RL_cache_rl_rereq = cache_rg_state == 4'd10 ; + assign WILL_FIRE_RL_cache_rl_rereq = + CAN_FIRE_RL_cache_rl_rereq && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_ST_AMO_response + assign CAN_FIRE_RL_cache_rl_ST_AMO_response = cache_rg_state == 4'd11 ; + assign WILL_FIRE_RL_cache_rl_ST_AMO_response = + CAN_FIRE_RL_cache_rl_ST_AMO_response ; + + // rule RL_cache_rl_io_read_req + assign CAN_FIRE_RL_cache_rl_io_read_req = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[98] && + cache_rg_state_7_EQ_12_15_AND_cache_rg_op_29_E_ETC___d617 ; + assign WILL_FIRE_RL_cache_rl_io_read_req = + CAN_FIRE_RL_cache_rl_io_read_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_maintain_io_read_rsp + assign CAN_FIRE_RL_cache_rl_maintain_io_read_rsp = cache_rg_state == 4'd14 ; + assign WILL_FIRE_RL_cache_rl_maintain_io_read_rsp = + CAN_FIRE_RL_cache_rl_maintain_io_read_rsp ; + + // rule RL_cache_rl_io_write_req + assign CAN_FIRE_RL_cache_rl_io_write_req = + cache_f_fabric_write_reqs$FULL_N && cache_rg_state == 4'd12 && + cache_rg_op == 2'd1 ; + assign WILL_FIRE_RL_cache_rl_io_write_req = + CAN_FIRE_RL_cache_rl_io_write_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_SC_req + assign CAN_FIRE_RL_cache_rl_io_AMO_SC_req = + cache_rg_state == 4'd12 && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_SC_req = + CAN_FIRE_RL_cache_rl_io_AMO_SC_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_op_req + assign CAN_FIRE_RL_cache_rl_io_AMO_op_req = + !cache_master_xactor_clearing && + !cache_master_xactor_shim_arff_rv[98] && + cache_rg_state == 4'd12 && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] != 5'b00010 && + cache_rg_amo_funct7[6:2] != 5'b00011 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_op_req = + CAN_FIRE_RL_cache_rl_io_AMO_op_req && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_drive_exception_rsp + assign CAN_FIRE_RL_cache_rl_drive_exception_rsp = cache_rg_state == 4'd4 ; + assign WILL_FIRE_RL_cache_rl_drive_exception_rsp = cache_rg_state == 4'd4 ; + + // rule RL_cache_master_xactor_ug_master_u_aw_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek = + cache_master_xactor_shim_awff_rv$port1__read[98] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_aw_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop = + cache_master_xactor_ug_master_u_aw_dropWire$whas && + !cache_master_xactor_shim_awff_rv$port1__read[98] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_aw_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop = + cache_master_xactor_shim_awff_rv$port1__read[98] && + cache_master_xactor_ug_master_u_aw_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_w_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek = + cache_master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_w_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop = + cache_master_xactor_ug_master_u_w_dropWire$whas && + !cache_master_xactor_shim_wff_rv$port1__read[73] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_w_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop = + cache_master_xactor_shim_wff_rv$port1__read[73] && + cache_master_xactor_ug_master_u_w_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_b_warnDoPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut = + cache_master_xactor_ug_master_u_b_putWire$whas && + cache_master_xactor_shim_bff_rv[7] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut ; + + // rule RL_cache_master_xactor_ug_master_u_b_doPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut = + !cache_master_xactor_shim_bff_rv[7] && + cache_master_xactor_ug_master_u_b_putWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut ; + + // rule RL_cache_rl_discard_write_rsp + assign CAN_FIRE_RL_cache_rl_discard_write_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_bff_rv$port1__read[7] && + b__h22491 != 4'd0 ; + assign WILL_FIRE_RL_cache_rl_discard_write_rsp = + CAN_FIRE_RL_cache_rl_discard_write_rsp ; + + // rule RL_cache_rl_start_reset + assign CAN_FIRE_RL_cache_rl_start_reset = + cache_f_reset_reqs$EMPTY_N && + (cache_f_reset_reqs$D_OUT || !cache_master_xactor_clearing) && + cache_rg_state != 4'd1 ; + assign WILL_FIRE_RL_cache_rl_start_reset = + CAN_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_master_xactor_ug_master_u_ar_setPeek + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek = + cache_master_xactor_shim_arff_rv$port1__read[98] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_setPeek ; + + // rule RL_cache_master_xactor_ug_master_u_ar_warnDoDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop = + cache_master_xactor_ug_master_u_ar_dropWire$whas && + !cache_master_xactor_shim_arff_rv$port1__read[98] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop ; + + // rule RL_cache_master_xactor_ug_master_u_ar_doDrop + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop = + cache_master_xactor_shim_arff_rv$port1__read[98] && + cache_master_xactor_ug_master_u_ar_dropWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop ; + + // rule RL_cache_master_xactor_ug_master_u_r_warnDoPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut = + cache_master_xactor_ug_master_u_r_putWire$whas && + cache_master_xactor_shim_rff_rv[72] ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut ; + + // rule RL_cache_master_xactor_ug_master_u_r_doPut + assign CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut = + !cache_master_xactor_shim_rff_rv[72] && + cache_master_xactor_ug_master_u_r_putWire$whas ; + assign WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut ; + + // rule RL_cache_rl_cache_refill_rsps_loop + assign CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[72] && + cache_rg_state == 4'd9 ; + assign WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop = + CAN_FIRE_RL_cache_rl_cache_refill_rsps_loop && + !WILL_FIRE_RL_cache_rl_start_reset && + !EN_req ; + + // rule RL_cache_rl_io_read_rsp + assign CAN_FIRE_RL_cache_rl_io_read_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[72] && + cache_rg_state == 4'd13 ; + assign WILL_FIRE_RL_cache_rl_io_read_rsp = + CAN_FIRE_RL_cache_rl_io_read_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_rl_io_AMO_read_rsp + assign CAN_FIRE_RL_cache_rl_io_AMO_read_rsp = + !cache_master_xactor_clearing && + cache_master_xactor_shim_rff_rv$port1__read[72] && + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_f_fabric_write_reqs$FULL_N) && + cache_rg_state == 4'd15 ; + assign WILL_FIRE_RL_cache_rl_io_AMO_read_rsp = + CAN_FIRE_RL_cache_rl_io_AMO_read_rsp && + !WILL_FIRE_RL_cache_rl_start_reset ; + + // rule RL_cache_master_xactor_do_clear + assign CAN_FIRE_RL_cache_master_xactor_do_clear = + cache_master_xactor_clearing ; + assign WILL_FIRE_RL_cache_master_xactor_do_clear = + cache_master_xactor_clearing ; + + // inputs to muxes for submodule ports + assign MUX_cache_dw_output_ld_val$wset_1__SEL_1 = + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_2 = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_3 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d204 ; + assign MUX_cache_dw_output_ld_val$wset_1__SEL_4 = + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp || + WILL_FIRE_RL_cache_rl_ST_AMO_response ; + assign MUX_cache_f_fabric_write_reqs$enq_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d513 ; + assign MUX_cache_master_xactor_clearing$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_start_reset && !cache_f_reset_reqs$D_OUT ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1 = + WILL_FIRE_RL_cache_rl_io_AMO_op_req || + WILL_FIRE_RL_cache_rl_io_read_req ; + assign MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 = + EN_req && + req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943 ; + assign MUX_cache_ram_word64_set$a_put_1__SEL_1 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 ; + assign MUX_cache_ram_word64_set$b_put_1__SEL_2 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 ; + assign MUX_cache_rg_error_during_refill$write_1__SEL_1 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_exc_code$write_1__SEL_1 = + EN_req && + NOT_req_f3_BITS_1_TO_0_13_EQ_0b0_14_15_AND_NOT_ETC___d934 ; + assign MUX_cache_rg_exc_code$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_exc_code$write_1__SEL_3 = + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 ; + assign MUX_cache_rg_ld_val$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d366 ; + assign MUX_cache_rg_lrsc_valid$write_1__SEL_2 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d200 ; + assign MUX_cache_rg_state$write_1__SEL_4 = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 ; + assign MUX_cache_rg_state$write_1__SEL_12 = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + (cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d341 || + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d344) ; + assign MUX_cache_rg_state$write_1__SEL_13 = + WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 ; + assign MUX_cache_dw_output_ld_val$wset_1__VAL_3 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) ? + new_value__h8173 : + new_value__h18271 ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_1 = + { cache_rg_f3, cache_rg_pa, x__h28190 } ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_2 = + { cache_rg_f3, + cache_rg_addr, + IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d514 } ; + assign MUX_cache_f_fabric_write_reqs$enq_1__VAL_3 = + { cache_rg_f3, cache_rg_pa, cache_rg_st_amo_val } ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1 = + { 6'd32, + fabric_addr__h27561, + 8'd0, + size_val__h27675, + 18'd65536 } ; + assign MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2 = + { 6'd32, cline_fabric_addr__h22590, 29'd7143424 } ; + assign MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1 = + { 3'd4, cache_rg_pa[31:12] } ; + assign MUX_cache_ram_word64_set$a_put_3__VAL_2 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 : + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 ; + assign MUX_cache_ram_word64_set$b_put_2__VAL_2 = + cache_rg_word64_set_in_cache + 9'd1 ; + assign MUX_cache_ram_word64_set$b_put_2__VAL_4 = + { cache_rg_addr[11:5], 2'd0 } ; + assign MUX_cache_rg_cset_in_cache$write_1__VAL_1 = + cache_rg_cset_in_cache + 7'd1 ; + assign MUX_cache_rg_exc_code$write_1__VAL_1 = + (req_op == 2'd0) ? 4'd4 : 4'd6 ; + assign MUX_cache_rg_ld_val$write_1__VAL_2 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + x__h15854 : + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 ; + assign MUX_cache_rg_state$write_1__VAL_1 = + NOT_req_f3_BITS_1_TO_0_13_EQ_0b0_14_15_AND_NOT_ETC___d934 ? + 4'd4 : + 4'd3 ; + assign MUX_cache_rg_state$write_1__VAL_2 = + (cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) ? + 4'd14 : + 4'd4 ; + assign MUX_cache_rg_state$write_1__VAL_4 = + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_rg_error_during_refill) ? + 4'd4 : + 4'd10 ; + assign MUX_cache_rg_state$write_1__VAL_12 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) ? + 4'd8 : + IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d347 ; + + // inlined wires + assign cache_master_xactor_ug_master_u_b_putWire$wget = + { mem_master_bid, mem_master_bresp } ; + assign cache_master_xactor_ug_master_u_b_putWire$whas = + mem_master_bvalid && !cache_master_xactor_shim_bff_rv[7] ; + assign cache_master_xactor_ug_master_u_r_putWire$wget = + { mem_master_rid, + mem_master_rdata, + mem_master_rresp, + mem_master_rlast } ; + assign cache_master_xactor_ug_master_u_r_putWire$whas = + mem_master_rvalid && !cache_master_xactor_shim_rff_rv[72] ; + assign cache_dw_valid$whas = + (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp) && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d204 || + WILL_FIRE_RL_cache_rl_drive_exception_rsp || + WILL_FIRE_RL_cache_rl_maintain_io_read_rsp || + WILL_FIRE_RL_cache_rl_ST_AMO_response ; + assign cache_master_xactor_ug_master_u_aw_dropWire$whas = + cache_master_xactor_shim_awff_rv$port1__read[98] && + mem_master_awready ; + assign cache_master_xactor_ug_master_u_w_dropWire$whas = + cache_master_xactor_shim_wff_rv$port1__read[73] && + mem_master_wready ; + assign cache_master_xactor_ug_master_u_ar_dropWire$whas = + cache_master_xactor_shim_arff_rv$port1__read[98] && + mem_master_arready ; + assign cache_master_xactor_shim_awff_rv$port0__write_1 = + { 6'd32, + mem_req_wr_addr_awaddr__h5054, + 8'd0, + _theResult___snd_snd_val__h5250, + 18'd65536 } ; + assign cache_master_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_master_xactor_shim_awff_rv$port0__write_1 : + cache_master_xactor_shim_awff_rv ; + assign cache_master_xactor_shim_awff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_aw_doDrop ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_awff_rv$port1__read ; + assign cache_master_xactor_shim_awff_rv$port3__read = + cache_master_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_awff_rv$port2__read ; + assign cache_master_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, + mem_req_wr_data_wdata__h5366, + mem_req_wr_data_wstrb__h5367, + 1'd1 } ; + assign cache_master_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_master_xactor_shim_wff_rv$port0__write_1 : + cache_master_xactor_shim_wff_rv ; + assign cache_master_xactor_shim_wff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_w_doDrop ? + 74'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_wff_rv$port1__read ; + assign cache_master_xactor_shim_wff_rv$port3__read = + cache_master_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_wff_rv$port2__read ; + assign cache_master_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, cache_master_xactor_ug_master_u_b_putWire$wget } ; + assign cache_master_xactor_shim_bff_rv$port1__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_b_doPut ? + cache_master_xactor_shim_bff_rv$port0__write_1 : + cache_master_xactor_shim_bff_rv ; + assign cache_master_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_cache_rl_discard_write_rsp ? + 8'd42 : + cache_master_xactor_shim_bff_rv$port1__read ; + assign cache_master_xactor_shim_bff_rv$port3__read = + cache_master_xactor_clearing ? + 8'd42 : + cache_master_xactor_shim_bff_rv$port2__read ; + assign cache_master_xactor_shim_arff_rv$EN_port0__write = + WILL_FIRE_RL_cache_rl_io_AMO_op_req || + WILL_FIRE_RL_cache_rl_io_read_req || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + assign cache_master_xactor_shim_arff_rv$port0__write_1 = + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__SEL_1 ? + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_1 : + MUX_cache_master_xactor_shim_arff_rv$port0__write_1__VAL_2 ; + assign cache_master_xactor_shim_arff_rv$port1__read = + cache_master_xactor_shim_arff_rv$EN_port0__write ? + cache_master_xactor_shim_arff_rv$port0__write_1 : + cache_master_xactor_shim_arff_rv ; + assign cache_master_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_ar_doDrop ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_arff_rv$port1__read ; + assign cache_master_xactor_shim_arff_rv$port3__read = + cache_master_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_arff_rv$port2__read ; + assign cache_master_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, cache_master_xactor_ug_master_u_r_putWire$wget } ; + assign cache_master_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_cache_master_xactor_ug_master_u_r_doPut ? + cache_master_xactor_shim_rff_rv$port0__write_1 : + cache_master_xactor_shim_rff_rv ; + assign cache_master_xactor_shim_rff_rv$EN_port1__write = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop ; + assign cache_master_xactor_shim_rff_rv$port2__read = + cache_master_xactor_shim_rff_rv$EN_port1__write ? + 73'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_rff_rv$port1__read ; + assign cache_master_xactor_shim_rff_rv$port3__read = + cache_master_xactor_clearing ? + 73'h0AAAAAAAAAAAAAAAAAA : + cache_master_xactor_shim_rff_rv$port2__read ; + assign cache_ctr_wr_rsps_pending_crg$port0__write_1 = + cache_ctr_wr_rsps_pending_crg + 4'd1 ; + assign cache_ctr_wr_rsps_pending_crg$port1__write_1 = b__h22491 - 4'd1 ; + assign cache_ctr_wr_rsps_pending_crg$port2__read = + CAN_FIRE_RL_cache_rl_discard_write_rsp ? + cache_ctr_wr_rsps_pending_crg$port1__write_1 : + b__h22491 ; + assign cache_ctr_wr_rsps_pending_crg$port3__read = + MUX_cache_master_xactor_clearing$write_1__SEL_2 ? + 4'd0 : + cache_ctr_wr_rsps_pending_crg$port2__read ; + assign cache_crg_sb_to_load_delay$port0__write_1 = + { 1'd0, cache_crg_sb_to_load_delay[10:1] } ; + assign cache_crg_sb_to_load_delay$EN_port1__write = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d509 ; + assign cache_crg_sb_to_load_delay$port2__read = + cache_crg_sb_to_load_delay$EN_port1__write ? + 11'd2047 : + cache_crg_sb_to_load_delay$port0__write_1 ; + + // register cache_cfg_verbosity + assign cache_cfg_verbosity$D_IN = set_verbosity_verbosity ; + assign cache_cfg_verbosity$EN = EN_set_verbosity ; + + // register cache_crg_sb_to_load_delay + assign cache_crg_sb_to_load_delay$D_IN = + cache_crg_sb_to_load_delay$port2__read ; + assign cache_crg_sb_to_load_delay$EN = 1'b1 ; + + // register cache_ctr_wr_rsps_pending_crg + assign cache_ctr_wr_rsps_pending_crg$D_IN = + cache_ctr_wr_rsps_pending_crg$port3__read ; + assign cache_ctr_wr_rsps_pending_crg$EN = 1'b1 ; + + // register cache_master_xactor_clearing + assign cache_master_xactor_clearing$D_IN = !cache_master_xactor_clearing ; + assign cache_master_xactor_clearing$EN = + WILL_FIRE_RL_cache_rl_start_reset && !cache_f_reset_reqs$D_OUT || + cache_master_xactor_clearing ; + + // register cache_master_xactor_shim_arff_rv + assign cache_master_xactor_shim_arff_rv$D_IN = + cache_master_xactor_shim_arff_rv$port3__read ; + assign cache_master_xactor_shim_arff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_awff_rv + assign cache_master_xactor_shim_awff_rv$D_IN = + cache_master_xactor_shim_awff_rv$port3__read ; + assign cache_master_xactor_shim_awff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_bff_rv + assign cache_master_xactor_shim_bff_rv$D_IN = + cache_master_xactor_shim_bff_rv$port3__read ; + assign cache_master_xactor_shim_bff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_rff_rv + assign cache_master_xactor_shim_rff_rv$D_IN = + cache_master_xactor_shim_rff_rv$port3__read ; + assign cache_master_xactor_shim_rff_rv$EN = 1'b1 ; + + // register cache_master_xactor_shim_wff_rv + assign cache_master_xactor_shim_wff_rv$D_IN = + cache_master_xactor_shim_wff_rv$port3__read ; + assign cache_master_xactor_shim_wff_rv$EN = 1'b1 ; + + // register cache_rg_addr + assign cache_rg_addr$D_IN = req_addr ; + assign cache_rg_addr$EN = EN_req ; + + // register cache_rg_amo_funct7 + assign cache_rg_amo_funct7$D_IN = req_amo_funct7 ; + assign cache_rg_amo_funct7$EN = EN_req ; + + // register cache_rg_cset_in_cache + assign cache_rg_cset_in_cache$D_IN = + WILL_FIRE_RL_cache_rl_reset ? + MUX_cache_rg_cset_in_cache$write_1__VAL_1 : + 7'd0 ; + assign cache_rg_cset_in_cache$EN = + WILL_FIRE_RL_cache_rl_reset || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_error_during_refill + assign cache_rg_error_during_refill$D_IN = + MUX_cache_rg_error_during_refill$write_1__SEL_1 ; + assign cache_rg_error_during_refill$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // register cache_rg_exc_code + always@(MUX_cache_rg_exc_code$write_1__SEL_1 or + MUX_cache_rg_exc_code$write_1__VAL_1 or + MUX_cache_rg_exc_code$write_1__SEL_2 or + MUX_cache_rg_exc_code$write_1__SEL_3 or + MUX_cache_rg_error_during_refill$write_1__SEL_1) + case (1'b1) + MUX_cache_rg_exc_code$write_1__SEL_1: + cache_rg_exc_code$D_IN = MUX_cache_rg_exc_code$write_1__VAL_1; + MUX_cache_rg_exc_code$write_1__SEL_2: cache_rg_exc_code$D_IN = 4'd7; + MUX_cache_rg_exc_code$write_1__SEL_3: cache_rg_exc_code$D_IN = 4'd5; + MUX_cache_rg_error_during_refill$write_1__SEL_1: + cache_rg_exc_code$D_IN = 4'd1; + default: cache_rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ; + endcase + assign cache_rg_exc_code$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + EN_req && + NOT_req_f3_BITS_1_TO_0_13_EQ_0b0_14_15_AND_NOT_ETC___d934 ; + + // register cache_rg_f3 + assign cache_rg_f3$D_IN = req_f3 ; + assign cache_rg_f3$EN = EN_req ; + + // register cache_rg_ld_val + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + new_ld_val__h28161 or + MUX_cache_rg_ld_val$write_1__SEL_2 or + MUX_cache_rg_ld_val$write_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_read_rsp or + ld_val__h25881 or WILL_FIRE_RL_cache_rl_io_AMO_SC_req) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_2: + cache_rg_ld_val$D_IN = new_ld_val__h28161; + MUX_cache_rg_ld_val$write_1__SEL_2: + cache_rg_ld_val$D_IN = MUX_cache_rg_ld_val$write_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_read_rsp: + cache_rg_ld_val$D_IN = ld_val__h25881; + WILL_FIRE_RL_cache_rl_io_AMO_SC_req: cache_rg_ld_val$D_IN = 64'd1; + default: cache_rg_ld_val$D_IN = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_rg_ld_val$EN = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d366 || + WILL_FIRE_RL_cache_rl_io_read_rsp || + WILL_FIRE_RL_cache_rl_io_AMO_SC_req ; + + // register cache_rg_lower_word32 + assign cache_rg_lower_word32$D_IN = 32'h0 ; + assign cache_rg_lower_word32$EN = 1'b0 ; + + // register cache_rg_lower_word32_full + assign cache_rg_lower_word32_full$D_IN = 1'd0 ; + assign cache_rg_lower_word32_full$EN = + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_lrsc_pa + assign cache_rg_lrsc_pa$D_IN = cache_rg_addr ; + assign cache_rg_lrsc_pa$EN = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 ; + + // register cache_rg_lrsc_valid + assign cache_rg_lrsc_valid$D_IN = + MUX_cache_rg_lrsc_valid$write_1__SEL_2 && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d201 ; + assign cache_rg_lrsc_valid$EN = + WILL_FIRE_RL_cache_rl_io_read_req && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d200 || + WILL_FIRE_RL_cache_rl_start_reset ; + + // register cache_rg_op + assign cache_rg_op$D_IN = req_op ; + assign cache_rg_op$EN = EN_req ; + + // register cache_rg_pa + assign cache_rg_pa$D_IN = EN_req ? req_addr : cache_rg_addr ; + assign cache_rg_pa$EN = + EN_req || WILL_FIRE_RL_cache_rl_probe_and_immed_rsp ; + + // register cache_rg_pte_pa + assign cache_rg_pte_pa$D_IN = 32'h0 ; + assign cache_rg_pte_pa$EN = 1'b0 ; + + // register cache_rg_st_amo_val + assign cache_rg_st_amo_val$D_IN = + EN_req ? req_st_value : new_st_val__h19402 ; + assign cache_rg_st_amo_val$EN = + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d375 || + EN_req ; + + // register cache_rg_state + always@(EN_req or + MUX_cache_rg_state$write_1__VAL_1 or + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp or + MUX_cache_rg_state$write_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_read_rsp or + MUX_cache_rg_state$write_1__SEL_4 or + MUX_cache_rg_state$write_1__VAL_4 or + WILL_FIRE_RL_cache_rl_start_reset or + WILL_FIRE_RL_cache_rl_io_AMO_op_req or + WILL_FIRE_RL_cache_rl_io_AMO_SC_req or + WILL_FIRE_RL_cache_rl_io_write_req or + WILL_FIRE_RL_cache_rl_io_read_req or + WILL_FIRE_RL_cache_rl_rereq or + WILL_FIRE_RL_cache_rl_start_cache_refill or + MUX_cache_rg_state$write_1__SEL_12 or + MUX_cache_rg_state$write_1__VAL_12 or + MUX_cache_rg_state$write_1__SEL_13) + case (1'b1) + EN_req: cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_1; + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_read_rsp: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_2; + MUX_cache_rg_state$write_1__SEL_4: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_4; + WILL_FIRE_RL_cache_rl_start_reset: cache_rg_state$D_IN = 4'd1; + WILL_FIRE_RL_cache_rl_io_AMO_op_req: cache_rg_state$D_IN = 4'd15; + WILL_FIRE_RL_cache_rl_io_AMO_SC_req || WILL_FIRE_RL_cache_rl_io_write_req: + cache_rg_state$D_IN = 4'd11; + WILL_FIRE_RL_cache_rl_io_read_req: cache_rg_state$D_IN = 4'd13; + WILL_FIRE_RL_cache_rl_rereq: cache_rg_state$D_IN = 4'd3; + WILL_FIRE_RL_cache_rl_start_cache_refill: cache_rg_state$D_IN = 4'd9; + MUX_cache_rg_state$write_1__SEL_12: + cache_rg_state$D_IN = MUX_cache_rg_state$write_1__VAL_12; + MUX_cache_rg_state$write_1__SEL_13: cache_rg_state$D_IN = 4'd2; + default: cache_rg_state$D_IN = 4'b1010 /* unspecified value */ ; + endcase + assign cache_rg_state$EN = + WILL_FIRE_RL_cache_rl_reset && + cache_rg_cset_in_cache == 7'd127 || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + (cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d341 || + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d344) || + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp || + WILL_FIRE_RL_cache_rl_io_read_rsp || + EN_req || + WILL_FIRE_RL_cache_rl_start_reset || + WILL_FIRE_RL_cache_rl_rereq || + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_io_AMO_SC_req || + WILL_FIRE_RL_cache_rl_io_write_req || + WILL_FIRE_RL_cache_rl_io_read_req || + WILL_FIRE_RL_cache_rl_io_AMO_op_req ; + + // register cache_rg_word64_set_in_cache + assign cache_rg_word64_set_in_cache$D_IN = + MUX_cache_ram_word64_set$b_put_1__SEL_2 ? + MUX_cache_ram_word64_set$b_put_2__VAL_2 : + MUX_cache_ram_word64_set$b_put_2__VAL_4 ; + assign cache_rg_word64_set_in_cache$EN = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // submodule cache_f_fabric_write_reqs + always@(MUX_cache_dw_output_ld_val$wset_1__SEL_2 or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_1 or + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2 or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2 or + WILL_FIRE_RL_cache_rl_io_write_req or + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_dw_output_ld_val$wset_1__SEL_2: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_1; + MUX_cache_f_fabric_write_reqs$enq_1__SEL_2: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_2; + WILL_FIRE_RL_cache_rl_io_write_req: + cache_f_fabric_write_reqs$D_IN = + MUX_cache_f_fabric_write_reqs$enq_1__VAL_3; + default: cache_f_fabric_write_reqs$D_IN = + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_f_fabric_write_reqs$ENQ = + WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d513 || + WILL_FIRE_RL_cache_rl_io_write_req ; + assign cache_f_fabric_write_reqs$DEQ = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ; + assign cache_f_fabric_write_reqs$CLR = 1'b0 ; + + // submodule cache_f_reset_reqs + assign cache_f_reset_reqs$D_IN = !EN_server_reset_request_put ; + assign cache_f_reset_reqs$ENQ = + EN_server_reset_request_put || EN_server_flush_request_put ; + assign cache_f_reset_reqs$DEQ = MUX_cache_rg_state$write_1__SEL_13 ; + assign cache_f_reset_reqs$CLR = 1'b0 ; + + // submodule cache_f_reset_rsps + assign cache_f_reset_rsps$D_IN = cache_f_reset_reqs$D_OUT ; + assign cache_f_reset_rsps$ENQ = MUX_cache_rg_state$write_1__SEL_13 ; + assign cache_f_reset_rsps$DEQ = + EN_server_flush_response_get || EN_server_reset_response_get ; + assign cache_f_reset_rsps$CLR = 1'b0 ; + + // submodule cache_ram_state_and_ctag_cset + assign cache_ram_state_and_ctag_cset$ADDRA = + WILL_FIRE_RL_cache_rl_start_cache_refill ? + cache_rg_addr[11:5] : + cache_rg_cset_in_cache ; + assign cache_ram_state_and_ctag_cset$ADDRB = + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 ? + req_addr[11:5] : + cache_rg_addr[11:5] ; + assign cache_ram_state_and_ctag_cset$DIA = + WILL_FIRE_RL_cache_rl_start_cache_refill ? + MUX_cache_ram_state_and_ctag_cset$a_put_3__VAL_1 : + 23'd2796202 ; + assign cache_ram_state_and_ctag_cset$DIB = + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 ? + 23'b01010101010101010101010 /* unspecified value */ : + 23'b01010101010101010101010 /* unspecified value */ ; + assign cache_ram_state_and_ctag_cset$WEA = 1'd1 ; + assign cache_ram_state_and_ctag_cset$WEB = 1'd0 ; + assign cache_ram_state_and_ctag_cset$ENA = + WILL_FIRE_RL_cache_rl_start_cache_refill || + WILL_FIRE_RL_cache_rl_reset ; + assign cache_ram_state_and_ctag_cset$ENB = + EN_req && + req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943 || + WILL_FIRE_RL_cache_rl_rereq ; + + // submodule cache_ram_word64_set + assign cache_ram_word64_set$ADDRA = + MUX_cache_ram_word64_set$a_put_1__SEL_1 ? + cache_rg_word64_set_in_cache : + cache_rg_addr[11:3] ; + always@(MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 or + req_addr or + MUX_cache_ram_word64_set$b_put_1__SEL_2 or + MUX_cache_ram_word64_set$b_put_2__VAL_2 or + WILL_FIRE_RL_cache_rl_rereq or + cache_rg_addr or + WILL_FIRE_RL_cache_rl_start_cache_refill or + MUX_cache_ram_word64_set$b_put_2__VAL_4) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1: + cache_ram_word64_set$ADDRB = req_addr[11:3]; + MUX_cache_ram_word64_set$b_put_1__SEL_2: + cache_ram_word64_set$ADDRB = + MUX_cache_ram_word64_set$b_put_2__VAL_2; + WILL_FIRE_RL_cache_rl_rereq: + cache_ram_word64_set$ADDRB = cache_rg_addr[11:3]; + WILL_FIRE_RL_cache_rl_start_cache_refill: + cache_ram_word64_set$ADDRB = + MUX_cache_ram_word64_set$b_put_2__VAL_4; + default: cache_ram_word64_set$ADDRB = + 9'b010101010 /* unspecified value */ ; + endcase + end + assign cache_ram_word64_set$DIA = + MUX_cache_ram_word64_set$a_put_1__SEL_1 ? + cache_master_xactor_shim_rff_rv$port1__read[66:3] : + MUX_cache_ram_word64_set$a_put_3__VAL_2 ; + always@(MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1 or + MUX_cache_ram_word64_set$b_put_1__SEL_2 or + WILL_FIRE_RL_cache_rl_rereq or + WILL_FIRE_RL_cache_rl_start_cache_refill) + begin + case (1'b1) // synopsys parallel_case + MUX_cache_ram_state_and_ctag_cset$b_put_1__SEL_1: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_cache_ram_word64_set$b_put_1__SEL_2: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + WILL_FIRE_RL_cache_rl_rereq: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + WILL_FIRE_RL_cache_rl_start_cache_refill: + cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + default: cache_ram_word64_set$DIB = + 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign cache_ram_word64_set$WEA = 1'd1 ; + assign cache_ram_word64_set$WEB = 1'd0 ; + assign cache_ram_word64_set$ENA = + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 || + WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d376 ; + assign cache_ram_word64_set$ENB = + EN_req && + req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943 || + WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] != 2'd3 || + WILL_FIRE_RL_cache_rl_rereq || + WILL_FIRE_RL_cache_rl_start_cache_refill ; + + // submodule cache_soc_map + assign cache_soc_map$m_is_IO_addr_addr = 64'h0 ; + assign cache_soc_map$m_is_mem_addr_addr = 64'h0 ; + assign cache_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; + + // remaining internal signals + assign IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324 = + (cache_rg_addr[2:0] == 3'h0) ? word64__h7992 : 64'd0 ; + assign IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d338 = + (cache_rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ; + assign IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821 = + (cache_rg_addr[2:0] == 3'h0) ? ld_val__h25881 : 64'd0 ; + assign IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 = + (cache_rg_f3 == 3'b010) ? b__h30158 : cache_rg_st_amo_val ; + assign IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d161 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15844 || + cache_f_fabric_write_reqs$FULL_N : + !cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 || + cache_f_fabric_write_reqs$FULL_N ; + assign IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d347 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + 4'd11 : + ((!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) ? + 4'd8 : + 4'd11) ; + assign IF_cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_ETC___d514 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) ? + cache_rg_st_amo_val : + new_st_val__h19402 ; + assign NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 = + cache_cfg_verbosity > 4'd1 ; + assign NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 = + cache_cfg_verbosity > 4'd2 ; + assign NOT_cache_ram_state_and_ctag_cset_b_read__51_B_ETC___d186 = + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 ; + assign NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d344 = + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) ; + assign NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d513 = + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d511 || + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d375) ; + assign NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d526 ; + assign NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d534 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d532 ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d197 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d375 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d508 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + (cache_rg_f3 == 3'b0 || cache_rg_f3 == 3'b001) ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d540 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d545 = + cache_rg_op != 2'd1 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d373 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 ; + assign NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d506 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + (cache_rg_f3 == 3'b0 || cache_rg_f3 == 3'b001) ; + assign NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d526 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d529 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d532 = + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign NOT_req_f3_BITS_1_TO_0_13_EQ_0b0_14_15_AND_NOT_ETC___d934 = + req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) && + (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) && + (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ; + assign _theResult___fst__h5232 = + cache_f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h5069 ; + assign b__h19806 = + { {32{new_value173_BITS_31_TO_0__q17[31]}}, + new_value173_BITS_31_TO_0__q17 } ; + assign b__h22491 = + CAN_FIRE_RL_cache_rl_fabric_send_write_req ? + cache_ctr_wr_rsps_pending_crg$port0__write_1 : + cache_ctr_wr_rsps_pending_crg ; + assign b__h28323 = + { {32{w18195_BITS_31_TO_0__q54[31]}}, + w18195_BITS_31_TO_0__q54 } ; + assign b__h30158 = + { {32{cache_rg_st_amo_val_BITS_31_TO_0__q1[31]}}, + cache_rg_st_amo_val_BITS_31_TO_0__q1 } ; + assign cache_master_xactor_shim_arff_rvport1__read_B_ETC__q22 = + cache_master_xactor_shim_arff_rv$port1__read[97:0] ; + assign cache_master_xactor_shim_awff_rvport1__read_B_ETC__q20 = + cache_master_xactor_shim_awff_rv$port1__read[97:0] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q23 = + cache_master_xactor_shim_rff_rv$port1__read[10:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q24 = + cache_master_xactor_shim_rff_rv$port1__read[18:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q25 = + cache_master_xactor_shim_rff_rv$port1__read[34:3] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q26 = + cache_master_xactor_shim_rff_rv$port1__read[18:11] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q27 = + cache_master_xactor_shim_rff_rv$port1__read[26:19] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q28 = + cache_master_xactor_shim_rff_rv$port1__read[34:19] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q29 = + cache_master_xactor_shim_rff_rv$port1__read[34:27] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q30 = + cache_master_xactor_shim_rff_rv$port1__read[42:35] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q31 = + cache_master_xactor_shim_rff_rv$port1__read[50:35] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q32 = + cache_master_xactor_shim_rff_rv$port1__read[66:35] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q33 = + cache_master_xactor_shim_rff_rv$port1__read[50:43] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q34 = + cache_master_xactor_shim_rff_rv$port1__read[58:51] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q35 = + cache_master_xactor_shim_rff_rv$port1__read[66:51] ; + assign cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q36 = + cache_master_xactor_shim_rff_rv$port1__read[66:59] ; + assign cache_master_xactor_shim_wff_rvport1__read_BI_ETC__q21 = + cache_master_xactor_shim_wff_rv$port1__read[72:0] ; + assign cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 = + cache_ram_state_and_ctag_cset$DOB[21:0] == pa_ctag__h7888 ; + assign cache_ram_state_and_ctag_cset_b_read__51_BIT_2_ETC___d187 = + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 || + NOT_cache_ram_state_and_ctag_cset_b_read__51_B_ETC___d186 ; + assign cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 = + cache_rg_addr == cache_rg_lrsc_pa ; + assign cache_rg_amo_funct7_32_BITS_6_TO_2_33_EQ_0b10__ETC___d363 = + cache_rg_amo_funct7[6:2] == 5'b00010 && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145 = + cache_rg_lrsc_pa == cache_rg_addr ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d200 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset_b_read__51_BIT_2_ETC___d187 || + cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d198 ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d201 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d204 = + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d201 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15844 ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d341 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d350 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d360 = + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + (!cache_ram_state_and_ctag_cset$DOB[22] || + !cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d198 = + cache_rg_op == 2'd1 && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 || + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d197 ; + assign cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d376 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d373 || + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d375 ; + assign cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d509 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d506 || + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d508 ; + assign cache_rg_op_29_EQ_1_37_OR_cache_rg_op_29_EQ_2__ETC___d511 = + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00011 || + cache_rg_lrsc_valid && + cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145) ; + assign cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d366 = + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 || + cache_rg_op != 2'd1 && cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 ; + assign cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d537 = + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011 && + lrsc_result__h15844 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 ; + assign cache_rg_st_amo_val_BITS_31_TO_0__q1 = cache_rg_st_amo_val[31:0] ; + assign cache_rg_state_7_EQ_12_15_AND_cache_rg_op_29_E_ETC___d617 = + cache_rg_state == 4'd12 && + (cache_rg_op == 2'd0 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00010) && + b__h22491 == 4'd0 ; + assign cache_rg_state_7_EQ_3_63_AND_NOT_cache_rg_op_2_ETC___d172 = + cache_rg_state == 4'd3 && + (cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) || + cache_crg_sb_to_load_delay$port0__write_1 == 11'd0) ; + assign cline_addr__h22589 = { cache_rg_pa[31:5], 5'd0 } ; + assign cline_fabric_addr__h22590 = { 32'd0, cline_addr__h22589 } ; + assign fabric_addr__h27561 = { 32'd0, cache_rg_pa } ; + assign ld_val5881_BITS_15_TO_0__q40 = ld_val__h25881[15:0] ; + assign ld_val5881_BITS_15_TO_8__q42 = ld_val__h25881[15:8] ; + assign ld_val5881_BITS_23_TO_16__q43 = ld_val__h25881[23:16] ; + assign ld_val5881_BITS_31_TO_0__q41 = ld_val__h25881[31:0] ; + assign ld_val5881_BITS_31_TO_16__q44 = ld_val__h25881[31:16] ; + assign ld_val5881_BITS_31_TO_24__q45 = ld_val__h25881[31:24] ; + assign ld_val5881_BITS_39_TO_32__q46 = ld_val__h25881[39:32] ; + assign ld_val5881_BITS_47_TO_32__q47 = ld_val__h25881[47:32] ; + assign ld_val5881_BITS_47_TO_40__q49 = ld_val__h25881[47:40] ; + assign ld_val5881_BITS_55_TO_48__q50 = ld_val__h25881[55:48] ; + assign ld_val5881_BITS_63_TO_32__q48 = ld_val__h25881[63:32] ; + assign ld_val5881_BITS_63_TO_48__q51 = ld_val__h25881[63:48] ; + assign ld_val5881_BITS_63_TO_56__q52 = ld_val__h25881[63:56] ; + assign ld_val5881_BITS_7_TO_0__q39 = ld_val__h25881[7:0] ; + assign lrsc_result__h15844 = + !cache_rg_lrsc_valid || + !cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145 ; + assign mem_req_wr_addr_awaddr__h5054 = + { 32'd0, cache_f_fabric_write_reqs$D_OUT[95:64] } ; + assign new_st_val__h19402 = + (cache_rg_f3 == 3'b010) ? + new_st_val__h19697 : + _theResult_____2__h19690 ; + assign new_st_val__h19697 = { 32'd0, _theResult_____2__h19690[31:0] } ; + assign new_st_val__h19798 = + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 + + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ; + assign new_st_val__h20791 = w1__h19682 ^ w2__h28201 ; + assign new_st_val__h20796 = w1__h19682 & w2__h28201 ; + assign new_st_val__h20801 = w1__h19682 | w2__h28201 ; + assign new_st_val__h20806 = + (w1__h19682 < w2__h28201) ? w1__h19682 : w2__h28201 ; + assign new_st_val__h20814 = + (w1__h19682 <= w2__h28201) ? w2__h28201 : w1__h19682 ; + assign new_st_val__h20823 = + ((IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 ^ + 64'h8000000000000000) < + (IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ^ + 64'h8000000000000000)) ? + w1__h19682 : + w2__h28201 ; + assign new_st_val__h20831 = + ((IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 ^ + 64'h8000000000000000) <= + (IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ^ + 64'h8000000000000000)) ? + w2__h28201 : + w1__h19682 ; + assign new_st_val__h28214 = { 32'd0, _theResult_____2__h28207[31:0] } ; + assign new_st_val__h28315 = + new_ld_val__h28161 + + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ; + assign new_st_val__h30188 = w1__h28199 ^ w2__h28201 ; + assign new_st_val__h30193 = w1__h28199 & w2__h28201 ; + assign new_st_val__h30198 = w1__h28199 | w2__h28201 ; + assign new_st_val__h30203 = + (w1__h28199 < w2__h28201) ? w1__h28199 : w2__h28201 ; + assign new_st_val__h30211 = + (w1__h28199 <= w2__h28201) ? w2__h28201 : w1__h28199 ; + assign new_st_val__h30220 = + ((new_ld_val__h28161 ^ 64'h8000000000000000) < + (IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ^ + 64'h8000000000000000)) ? + w1__h28199 : + w2__h28201 ; + assign new_st_val__h30228 = + ((new_ld_val__h28161 ^ 64'h8000000000000000) <= + (IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_cache_r_ETC___d434 ^ + 64'h8000000000000000)) ? + w2__h28201 : + w1__h28199 ; + assign new_value173_BITS_31_TO_0__q17 = new_value__h8173[31:0] ; + assign pa_ctag__h7888 = { 2'd0, cache_rg_addr[31:12] } ; + assign req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943 = + req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] || + req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 || + req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ; + assign result__h14584 = + { {56{word64992_BITS_15_TO_8__q5[7]}}, + word64992_BITS_15_TO_8__q5 } ; + assign result__h14612 = + { {56{word64992_BITS_23_TO_16__q6[7]}}, + word64992_BITS_23_TO_16__q6 } ; + assign result__h14640 = + { {56{word64992_BITS_31_TO_24__q8[7]}}, + word64992_BITS_31_TO_24__q8 } ; + assign result__h14668 = + { {56{word64992_BITS_39_TO_32__q9[7]}}, + word64992_BITS_39_TO_32__q9 } ; + assign result__h14696 = + { {56{word64992_BITS_47_TO_40__q12[7]}}, + word64992_BITS_47_TO_40__q12 } ; + assign result__h14724 = + { {56{word64992_BITS_55_TO_48__q13[7]}}, + word64992_BITS_55_TO_48__q13 } ; + assign result__h14752 = + { {56{word64992_BITS_63_TO_56__q15[7]}}, + word64992_BITS_63_TO_56__q15 } ; + assign result__h14797 = { 56'd0, word64__h7992[7:0] } ; + assign result__h14825 = { 56'd0, word64__h7992[15:8] } ; + assign result__h14853 = { 56'd0, word64__h7992[23:16] } ; + assign result__h14881 = { 56'd0, word64__h7992[31:24] } ; + assign result__h14909 = { 56'd0, word64__h7992[39:32] } ; + assign result__h14937 = { 56'd0, word64__h7992[47:40] } ; + assign result__h14965 = { 56'd0, word64__h7992[55:48] } ; + assign result__h14993 = { 56'd0, word64__h7992[63:56] } ; + assign result__h15038 = + { {48{word64992_BITS_15_TO_0__q3[15]}}, + word64992_BITS_15_TO_0__q3 } ; + assign result__h15066 = + { {48{word64992_BITS_31_TO_16__q7[15]}}, + word64992_BITS_31_TO_16__q7 } ; + assign result__h15094 = + { {48{word64992_BITS_47_TO_32__q10[15]}}, + word64992_BITS_47_TO_32__q10 } ; + assign result__h15122 = + { {48{word64992_BITS_63_TO_48__q14[15]}}, + word64992_BITS_63_TO_48__q14 } ; + assign result__h15163 = { 48'd0, word64__h7992[15:0] } ; + assign result__h15191 = { 48'd0, word64__h7992[31:16] } ; + assign result__h15219 = { 48'd0, word64__h7992[47:32] } ; + assign result__h15247 = { 48'd0, word64__h7992[63:48] } ; + assign result__h15288 = + { {32{word64992_BITS_31_TO_0__q4[31]}}, + word64992_BITS_31_TO_0__q4 } ; + assign result__h15316 = + { {32{word64992_BITS_63_TO_32__q11[31]}}, + word64992_BITS_63_TO_32__q11 } ; + assign result__h15355 = { 32'd0, word64__h7992[31:0] } ; + assign result__h15383 = { 32'd0, word64__h7992[63:32] } ; + assign result__h25941 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q23[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q23 } ; + assign result__h25971 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q26[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q26 } ; + assign result__h25998 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q27[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q27 } ; + assign result__h26025 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q29[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q29 } ; + assign result__h26052 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q30[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q30 } ; + assign result__h26079 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q33[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q33 } ; + assign result__h26106 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q34[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q34 } ; + assign result__h26133 = + { {56{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q36[7]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q36 } ; + assign result__h26177 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[10:3] } ; + assign result__h26204 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[18:11] } ; + assign result__h26231 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[26:19] } ; + assign result__h26258 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[34:27] } ; + assign result__h26285 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[42:35] } ; + assign result__h26312 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[50:43] } ; + assign result__h26339 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[58:51] } ; + assign result__h26366 = + { 56'd0, cache_master_xactor_shim_rff_rv$port1__read[66:59] } ; + assign result__h26410 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q24[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q24 } ; + assign result__h26437 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q28[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q28 } ; + assign result__h26464 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q31[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q31 } ; + assign result__h26491 = + { {48{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q35[15]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q35 } ; + assign result__h26531 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[18:3] } ; + assign result__h26558 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[34:19] } ; + assign result__h26585 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[50:35] } ; + assign result__h26612 = + { 48'd0, cache_master_xactor_shim_rff_rv$port1__read[66:51] } ; + assign result__h26652 = + { {32{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q25[31]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q25 } ; + assign result__h26679 = + { {32{cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q32[31]}}, + cache_master_xactor_shim_rff_rvport1__read_BI_ETC__q32 } ; + assign result__h26717 = + { 32'd0, cache_master_xactor_shim_rff_rv$port1__read[34:3] } ; + assign result__h26744 = + { 32'd0, cache_master_xactor_shim_rff_rv$port1__read[66:35] } ; + assign result__h28412 = + { {56{ld_val5881_BITS_7_TO_0__q39[7]}}, + ld_val5881_BITS_7_TO_0__q39 } ; + assign result__h29320 = + { {56{ld_val5881_BITS_15_TO_8__q42[7]}}, + ld_val5881_BITS_15_TO_8__q42 } ; + assign result__h29348 = + { {56{ld_val5881_BITS_23_TO_16__q43[7]}}, + ld_val5881_BITS_23_TO_16__q43 } ; + assign result__h29376 = + { {56{ld_val5881_BITS_31_TO_24__q45[7]}}, + ld_val5881_BITS_31_TO_24__q45 } ; + assign result__h29404 = + { {56{ld_val5881_BITS_39_TO_32__q46[7]}}, + ld_val5881_BITS_39_TO_32__q46 } ; + assign result__h29432 = + { {56{ld_val5881_BITS_47_TO_40__q49[7]}}, + ld_val5881_BITS_47_TO_40__q49 } ; + assign result__h29460 = + { {56{ld_val5881_BITS_55_TO_48__q50[7]}}, + ld_val5881_BITS_55_TO_48__q50 } ; + assign result__h29488 = + { {56{ld_val5881_BITS_63_TO_56__q52[7]}}, + ld_val5881_BITS_63_TO_56__q52 } ; + assign result__h29533 = { 56'd0, ld_val__h25881[7:0] } ; + assign result__h29561 = { 56'd0, ld_val__h25881[15:8] } ; + assign result__h29589 = { 56'd0, ld_val__h25881[23:16] } ; + assign result__h29617 = { 56'd0, ld_val__h25881[31:24] } ; + assign result__h29645 = { 56'd0, ld_val__h25881[39:32] } ; + assign result__h29673 = { 56'd0, ld_val__h25881[47:40] } ; + assign result__h29701 = { 56'd0, ld_val__h25881[55:48] } ; + assign result__h29729 = { 56'd0, ld_val__h25881[63:56] } ; + assign result__h29774 = + { {48{ld_val5881_BITS_15_TO_0__q40[15]}}, + ld_val5881_BITS_15_TO_0__q40 } ; + assign result__h29802 = + { {48{ld_val5881_BITS_31_TO_16__q44[15]}}, + ld_val5881_BITS_31_TO_16__q44 } ; + assign result__h29830 = + { {48{ld_val5881_BITS_47_TO_32__q47[15]}}, + ld_val5881_BITS_47_TO_32__q47 } ; + assign result__h29858 = + { {48{ld_val5881_BITS_63_TO_48__q51[15]}}, + ld_val5881_BITS_63_TO_48__q51 } ; + assign result__h29899 = { 48'd0, ld_val__h25881[15:0] } ; + assign result__h29927 = { 48'd0, ld_val__h25881[31:16] } ; + assign result__h29955 = { 48'd0, ld_val__h25881[47:32] } ; + assign result__h29983 = { 48'd0, ld_val__h25881[63:48] } ; + assign result__h30024 = + { {32{ld_val5881_BITS_31_TO_0__q41[31]}}, + ld_val5881_BITS_31_TO_0__q41 } ; + assign result__h30052 = + { {32{ld_val5881_BITS_63_TO_32__q48[31]}}, + ld_val5881_BITS_63_TO_32__q48 } ; + assign result__h30091 = { 32'd0, ld_val__h25881[31:0] } ; + assign result__h30119 = { 32'd0, ld_val__h25881[63:32] } ; + assign result__h8228 = + { {56{word64992_BITS_7_TO_0__q2[7]}}, + word64992_BITS_7_TO_0__q2 } ; + assign shift_bits__h5069 = + { cache_f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ; + assign strobe64__h5230 = + 8'b00000001 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign strobe64__h5237 = + 8'b00000011 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign strobe64__h5241 = + 8'b00001111 << cache_f_fabric_write_reqs$D_OUT[66:64] ; + assign w18195_BITS_31_TO_0__q54 = w1__h28195[31:0] ; + assign w1___1__h19764 = { 32'd0, new_value__h8173[31:0] } ; + assign w1___1__h28281 = { 32'd0, w1__h28195[31:0] } ; + assign w2___1__h28282 = { 32'd0, cache_rg_st_amo_val[31:0] } ; + assign w2__h28201 = + (cache_rg_f3 == 3'b010) ? w2___1__h28282 : cache_rg_st_amo_val ; + assign word64992_BITS_15_TO_0__q3 = word64__h7992[15:0] ; + assign word64992_BITS_15_TO_8__q5 = word64__h7992[15:8] ; + assign word64992_BITS_23_TO_16__q6 = word64__h7992[23:16] ; + assign word64992_BITS_31_TO_0__q4 = word64__h7992[31:0] ; + assign word64992_BITS_31_TO_16__q7 = word64__h7992[31:16] ; + assign word64992_BITS_31_TO_24__q8 = word64__h7992[31:24] ; + assign word64992_BITS_39_TO_32__q9 = word64__h7992[39:32] ; + assign word64992_BITS_47_TO_32__q10 = word64__h7992[47:32] ; + assign word64992_BITS_47_TO_40__q12 = word64__h7992[47:40] ; + assign word64992_BITS_55_TO_48__q13 = word64__h7992[55:48] ; + assign word64992_BITS_63_TO_32__q11 = word64__h7992[63:32] ; + assign word64992_BITS_63_TO_48__q14 = word64__h7992[63:48] ; + assign word64992_BITS_63_TO_56__q15 = word64__h7992[63:56] ; + assign word64992_BITS_7_TO_0__q2 = word64__h7992[7:0] ; + assign word64__h7992 = cache_ram_word64_set$DOB & y__h8264 ; + assign x__h15854 = { 63'd0, lrsc_result__h15844 } ; + assign x__h28190 = + (cache_rg_f3 == 3'b010) ? + new_st_val__h28214 : + _theResult_____2__h28207 ; + assign y__h8264 = + {64{cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157}} ; + always@(cache_f_fabric_write_reqs$D_OUT) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0: _theResult___snd_snd_val__h5250 = 3'b0; + 2'b01: _theResult___snd_snd_val__h5250 = 3'b001; + 2'b10: _theResult___snd_snd_val__h5250 = 3'b010; + 2'b11: _theResult___snd_snd_val__h5250 = 3'b011; + endcase + end + always@(cache_rg_f3) + begin + case (cache_rg_f3[1:0]) + 2'b0: size_val__h27675 = 3'b0; + 2'b01: size_val__h27675 = 3'b001; + 2'b10: size_val__h27675 = 3'b010; + 2'd3: size_val__h27675 = 3'b011; + endcase + end + always@(cache_f_fabric_write_reqs$D_OUT or + strobe64__h5230 or strobe64__h5237 or strobe64__h5241) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0: mem_req_wr_data_wstrb__h5367 = strobe64__h5230; + 2'b01: mem_req_wr_data_wstrb__h5367 = strobe64__h5237; + 2'b10: mem_req_wr_data_wstrb__h5367 = strobe64__h5241; + 2'b11: mem_req_wr_data_wstrb__h5367 = 8'b11111111; + endcase + end + always@(cache_f_fabric_write_reqs$D_OUT or _theResult___fst__h5232) + begin + case (cache_f_fabric_write_reqs$D_OUT[97:96]) + 2'b0, 2'b01, 2'b10: + mem_req_wr_data_wdata__h5366 = _theResult___fst__h5232; + 2'd3: + mem_req_wr_data_wdata__h5366 = + cache_f_fabric_write_reqs$D_OUT[63:0]; + endcase + end + always@(cache_rg_addr or + result__h14797 or + result__h14825 or + result__h14853 or + result__h14881 or + result__h14909 or + result__h14937 or result__h14965 or result__h14993) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14797; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14825; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14853; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14881; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14909; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14937; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14965; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 = + result__h14993; + endcase + end + always@(cache_rg_addr or + result__h8228 or + result__h14584 or + result__h14612 or + result__h14640 or + result__h14668 or + result__h14696 or result__h14724 or result__h14752) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h8228; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14584; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14612; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14640; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14668; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14696; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14724; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 = + result__h14752; + endcase + end + always@(cache_rg_addr or + result__h15038 or + result__h15066 or result__h15094 or result__h15122) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 = + result__h15038; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 = + result__h15066; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 = + result__h15094; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 = + result__h15122; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h15163 or + result__h15191 or result__h15219 or result__h15247) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 = + result__h15163; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 = + result__h15191; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 = + result__h15219; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 = + result__h15247; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h15355 or result__h15383) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322 = + result__h15355; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322 = + result__h15383; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h15288 or result__h15316) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16 = + result__h15288; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16 = + result__h15316; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16 = + 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322) + begin + case (cache_rg_f3) + 3'b0: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271; + 3'b001: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301; + 3'b010: + new_value__h8173 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result5288__ETC__q16; + 3'b011: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324; + 3'b100: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288; + 3'b101: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310; + 3'b110: + new_value__h8173 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322; + 3'd7: new_value__h8173 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 or + w1___1__h19764 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322) + begin + case (cache_rg_f3) + 3'b0: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271; + 3'b001: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301; + 3'b010: w1__h19682 = w1___1__h19764; + 3'b011: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324; + 3'b100: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288; + 3'b101: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310; + 3'b110: + w1__h19682 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322; + 3'd7: w1__h19682 = 64'd0; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 = + { cache_ram_word64_set$DOB[63:16], cache_rg_st_amo_val[15:0] }; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 = + { cache_ram_word64_set$DOB[63:32], + cache_rg_st_amo_val[15:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 = + { cache_ram_word64_set$DOB[63:48], + cache_rg_st_amo_val[15:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 = + { cache_rg_st_amo_val[15:0], cache_ram_word64_set$DOB[47:0] }; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:8], cache_rg_st_amo_val[7:0] }; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:16], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[7:0] }; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:24], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:32], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[23:0] }; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:40], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:48], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[39:0] }; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_ram_word64_set$DOB[63:56], + cache_rg_st_amo_val[7:0], + cache_ram_word64_set$DOB[47:0] }; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 = + { cache_rg_st_amo_val[7:0], cache_ram_word64_set$DOB[55:0] }; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301 or + b__h19806 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d271; + 3'b001: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d301; + 3'b010: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + b__h19806; + 3'b011: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d324; + 3'b100: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d288; + 3'b101: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d310; + 3'b110: + IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d322; + 3'd7: IF_cache_rg_f3_05_EQ_0b10_11_THEN_SEXT_IF_cach_ETC___d371 = 64'd0; + endcase + end + always@(cache_rg_amo_funct7 or + new_st_val__h20831 or + new_st_val__h19798 or + w2__h28201 or + new_st_val__h20791 or + new_st_val__h20801 or + new_st_val__h20796 or + new_st_val__h20823 or new_st_val__h20806 or new_st_val__h20814) + begin + case (cache_rg_amo_funct7[6:2]) + 5'b0: _theResult_____2__h19690 = new_st_val__h19798; + 5'b00001: _theResult_____2__h19690 = w2__h28201; + 5'b00100: _theResult_____2__h19690 = new_st_val__h20791; + 5'b01000: _theResult_____2__h19690 = new_st_val__h20801; + 5'b01100: _theResult_____2__h19690 = new_st_val__h20796; + 5'b10000: _theResult_____2__h19690 = new_st_val__h20823; + 5'b11000: _theResult_____2__h19690 = new_st_val__h20806; + 5'b11100: _theResult_____2__h19690 = new_st_val__h20814; + default: _theResult_____2__h19690 = new_st_val__h20831; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19402) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 = + { cache_ram_word64_set$DOB[63:16], new_st_val__h19402[15:0] }; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 = + { cache_ram_word64_set$DOB[63:32], + new_st_val__h19402[15:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 = + { cache_ram_word64_set$DOB[63:48], + new_st_val__h19402[15:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 = + { new_st_val__h19402[15:0], cache_ram_word64_set$DOB[47:0] }; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19402) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:8], new_st_val__h19402[7:0] }; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:16], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[7:0] }; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:24], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[15:0] }; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:32], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[23:0] }; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:40], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[31:0] }; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:48], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[39:0] }; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { cache_ram_word64_set$DOB[63:56], + new_st_val__h19402[7:0], + cache_ram_word64_set$DOB[47:0] }; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 = + { new_st_val__h19402[7:0], cache_ram_word64_set$DOB[55:0] }; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or cache_rg_st_amo_val) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18 = + { cache_ram_word64_set$DOB[63:32], cache_rg_st_amo_val[31:0] }; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18 = + { cache_rg_st_amo_val[31:0], cache_ram_word64_set$DOB[31:0] }; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + cache_ram_word64_set$DOB or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18 or + cache_rg_st_amo_val) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d410; + 3'b001: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d419; + 3'b010: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q18; + 3'b011: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 = + cache_rg_st_amo_val; + default: IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_addr or cache_ram_word64_set$DOB or new_st_val__h19402) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19 = + { cache_ram_word64_set$DOB[63:32], new_st_val__h19402[31:0] }; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19 = + { new_st_val__h19402[31:0], cache_ram_word64_set$DOB[31:0] }; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + cache_ram_word64_set$DOB or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19 or + new_st_val__h19402) + begin + case (cache_rg_f3) + 3'b0: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d484; + 3'b001: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d493; + 3'b010: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_cache_ram_w_ETC__q19; + 3'b011: + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 = + new_st_val__h19402; + default: IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502 = + cache_ram_word64_set$DOB; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d338) + begin + case (cache_rg_f3) + 3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110: + new_value__h18271 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d338; + 3'd7: new_value__h18271 = 64'd0; + endcase + end + always@(cache_rg_addr or + result__h26531 or + result__h26558 or result__h26585 or result__h26612) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 = + result__h26531; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 = + result__h26558; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 = + result__h26585; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 = + result__h26612; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h26410 or + result__h26437 or result__h26464 or result__h26491) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 = + result__h26410; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 = + result__h26437; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 = + result__h26464; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 = + result__h26491; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h25941 or + result__h25971 or + result__h25998 or + result__h26025 or + result__h26052 or + result__h26079 or result__h26106 or result__h26133) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h25941; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h25971; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h25998; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h26025; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h26052; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h26079; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h26106; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 = + result__h26133; + endcase + end + always@(cache_rg_addr or + result__h26177 or + result__h26204 or + result__h26231 or + result__h26258 or + result__h26285 or + result__h26312 or result__h26339 or result__h26366) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26177; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26204; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26231; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26258; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26285; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26312; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26339; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 = + result__h26366; + endcase + end + always@(cache_rg_addr or result__h26652 or result__h26679) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37 = + result__h26652; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37 = + result__h26679; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37 = + 64'd0; + endcase + end + always@(cache_rg_addr or result__h26717 or result__h26744) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38 = + result__h26717; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38 = + result__h26744; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38 = + 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37 or + cache_rg_addr or + cache_master_xactor_shim_rff_rv$port1__read or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38) + begin + case (cache_rg_f3) + 3'b0: + ld_val__h25881 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d664; + 3'b001: + ld_val__h25881 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d692; + 3'b010: + ld_val__h25881 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6652__ETC__q37; + 3'b011: + ld_val__h25881 = + (cache_rg_addr[2:0] == 3'h0) ? + cache_master_xactor_shim_rff_rv$port1__read[66:3] : + 64'd0; + 3'b100: + ld_val__h25881 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d680; + 3'b101: + ld_val__h25881 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d700; + 3'b110: + ld_val__h25881 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result6717__ETC__q38; + 3'd7: ld_val__h25881 = 64'd0; + endcase + end + always@(cache_rg_addr or result__h30091 or result__h30119) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820 = + result__h30091; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820 = + result__h30119; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h29899 or + result__h29927 or result__h29955 or result__h29983) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 = + result__h29899; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 = + result__h29927; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 = + result__h29955; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 = + result__h29983; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h29774 or + result__h29802 or result__h29830 or result__h29858) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 = + result__h29774; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 = + result__h29802; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 = + result__h29830; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 = + result__h29858; + default: IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 = + 64'd0; + endcase + end + always@(cache_rg_addr or + result__h28412 or + result__h29320 or + result__h29348 or + result__h29376 or + result__h29404 or + result__h29432 or result__h29460 or result__h29488) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h28412; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29320; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29348; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29376; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29404; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29432; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29460; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 = + result__h29488; + endcase + end + always@(cache_rg_addr or + result__h29533 or + result__h29561 or + result__h29589 or + result__h29617 or + result__h29645 or + result__h29673 or result__h29701 or result__h29729) + begin + case (cache_rg_addr[2:0]) + 3'h0: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29533; + 3'h1: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29561; + 3'h2: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29589; + 3'h3: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29617; + 3'h4: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29645; + 3'h5: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29673; + 3'h6: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29701; + 3'h7: + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 = + result__h29729; + endcase + end + always@(cache_rg_addr or result__h30024 or result__h30052) + begin + case (cache_rg_addr[2:0]) + 3'h0: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53 = + result__h30024; + 3'h4: + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53 = + result__h30052; + default: CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53 = + 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 or + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820) + begin + case (cache_rg_f3) + 3'b0: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774; + 3'b001: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802; + 3'b010: + w1__h28195 = + CASE_cache_rg_addr_BITS_2_TO_0_0x0_result0024__ETC__q53; + 3'b011: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821; + 3'b100: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790; + 3'b101: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810; + 3'b110: + w1__h28195 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820; + 3'd7: w1__h28195 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 or + w1___1__h28281 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820) + begin + case (cache_rg_f3) + 3'b0: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774; + 3'b001: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802; + 3'b010: w1__h28199 = w1___1__h28281; + 3'b011: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821; + 3'b100: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790; + 3'b101: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810; + 3'b110: + w1__h28199 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820; + 3'd7: w1__h28199 = 64'd0; + endcase + end + always@(cache_rg_f3 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802 or + b__h28323 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810 or + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820) + begin + case (cache_rg_f3) + 3'b0: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d774; + 3'b001: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d802; + 3'b010: new_ld_val__h28161 = b__h28323; + 3'b011: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d821; + 3'b100: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d790; + 3'b101: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d810; + 3'b110: + new_ld_val__h28161 = + IF_cache_rg_addr_44_BITS_2_TO_0_78_EQ_0x0_07_T_ETC___d820; + 3'd7: new_ld_val__h28161 = 64'd0; + endcase + end + always@(cache_rg_amo_funct7 or + new_st_val__h30228 or + new_st_val__h28315 or + w2__h28201 or + new_st_val__h30188 or + new_st_val__h30198 or + new_st_val__h30193 or + new_st_val__h30220 or new_st_val__h30203 or new_st_val__h30211) + begin + case (cache_rg_amo_funct7[6:2]) + 5'b0: _theResult_____2__h28207 = new_st_val__h28315; + 5'b00001: _theResult_____2__h28207 = w2__h28201; + 5'b00100: _theResult_____2__h28207 = new_st_val__h30188; + 5'b01000: _theResult_____2__h28207 = new_st_val__h30198; + 5'b01100: _theResult_____2__h28207 = new_st_val__h30193; + 5'b10000: _theResult_____2__h28207 = new_st_val__h30220; + 5'b11000: _theResult_____2__h28207 = new_st_val__h30203; + 5'b11100: _theResult_____2__h28207 = new_st_val__h30211; + default: _theResult_____2__h28207 = new_st_val__h30228; + endcase + end + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + cache_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; + cache_crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY 11'd0; + cache_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0; + cache_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 8'd42; + cache_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 73'h0AAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; + cache_rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 7'd0; + cache_rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0; + cache_rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0; + end + else + begin + if (cache_cfg_verbosity$EN) + cache_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY + cache_cfg_verbosity$D_IN; + if (cache_crg_sb_to_load_delay$EN) + cache_crg_sb_to_load_delay <= `BSV_ASSIGNMENT_DELAY + cache_crg_sb_to_load_delay$D_IN; + if (cache_ctr_wr_rsps_pending_crg$EN) + cache_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY + cache_ctr_wr_rsps_pending_crg$D_IN; + if (cache_master_xactor_clearing$EN) + cache_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_clearing$D_IN; + if (cache_master_xactor_shim_arff_rv$EN) + cache_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_arff_rv$D_IN; + if (cache_master_xactor_shim_awff_rv$EN) + cache_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_awff_rv$D_IN; + if (cache_master_xactor_shim_bff_rv$EN) + cache_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_bff_rv$D_IN; + if (cache_master_xactor_shim_rff_rv$EN) + cache_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_rff_rv$D_IN; + if (cache_master_xactor_shim_wff_rv$EN) + cache_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + cache_master_xactor_shim_wff_rv$D_IN; + if (cache_rg_cset_in_cache$EN) + cache_rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY + cache_rg_cset_in_cache$D_IN; + if (cache_rg_lower_word32_full$EN) + cache_rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY + cache_rg_lower_word32_full$D_IN; + if (cache_rg_lrsc_valid$EN) + cache_rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY + cache_rg_lrsc_valid$D_IN; + if (cache_rg_state$EN) + cache_rg_state <= `BSV_ASSIGNMENT_DELAY cache_rg_state$D_IN; + end + if (cache_rg_addr$EN) + cache_rg_addr <= `BSV_ASSIGNMENT_DELAY cache_rg_addr$D_IN; + if (cache_rg_amo_funct7$EN) + cache_rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY cache_rg_amo_funct7$D_IN; + if (cache_rg_error_during_refill$EN) + cache_rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY + cache_rg_error_during_refill$D_IN; + if (cache_rg_exc_code$EN) + cache_rg_exc_code <= `BSV_ASSIGNMENT_DELAY cache_rg_exc_code$D_IN; + if (cache_rg_f3$EN) cache_rg_f3 <= `BSV_ASSIGNMENT_DELAY cache_rg_f3$D_IN; + if (cache_rg_ld_val$EN) + cache_rg_ld_val <= `BSV_ASSIGNMENT_DELAY cache_rg_ld_val$D_IN; + if (cache_rg_lower_word32$EN) + cache_rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY + cache_rg_lower_word32$D_IN; + if (cache_rg_lrsc_pa$EN) + cache_rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_lrsc_pa$D_IN; + if (cache_rg_op$EN) cache_rg_op <= `BSV_ASSIGNMENT_DELAY cache_rg_op$D_IN; + if (cache_rg_pa$EN) cache_rg_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_pa$D_IN; + if (cache_rg_pte_pa$EN) + cache_rg_pte_pa <= `BSV_ASSIGNMENT_DELAY cache_rg_pte_pa$D_IN; + if (cache_rg_st_amo_val$EN) + cache_rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY cache_rg_st_amo_val$D_IN; + if (cache_rg_word64_set_in_cache$EN) + cache_rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY + cache_rg_word64_set_in_cache$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + cache_cfg_verbosity = 4'hA; + cache_crg_sb_to_load_delay = 11'h2AA; + cache_ctr_wr_rsps_pending_crg = 4'hA; + cache_master_xactor_clearing = 1'h0; + cache_master_xactor_shim_arff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_awff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_bff_rv = 8'hAA; + cache_master_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA; + cache_master_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; + cache_rg_addr = 32'hAAAAAAAA; + cache_rg_amo_funct7 = 7'h2A; + cache_rg_cset_in_cache = 7'h2A; + cache_rg_error_during_refill = 1'h0; + cache_rg_exc_code = 4'hA; + cache_rg_f3 = 3'h2; + cache_rg_ld_val = 64'hAAAAAAAAAAAAAAAA; + cache_rg_lower_word32 = 32'hAAAAAAAA; + cache_rg_lower_word32_full = 1'h0; + cache_rg_lrsc_pa = 32'hAAAAAAAA; + cache_rg_lrsc_valid = 1'h0; + cache_rg_op = 2'h2; + cache_rg_pa = 32'hAAAAAAAA; + cache_rg_pte_pa = 32'hAAAAAAAA; + cache_rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA; + cache_rg_state = 4'hA; + cache_rg_word64_set_in_cache = 9'h0AA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + begin + v__h5641 = $stime; + #0; + end + v__h5635 = v__h5641 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + $display("%0d: ERROR: CreditCounter: overflow", v__h5635); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + cache_ctr_wr_rsps_pending_crg == 4'd15) + $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_AWFlit { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 5'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awaddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_addr_awaddr__h5054); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", _theResult___snd_snd_val__h5250, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "awuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_WFlit { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_data_wdata__h5366); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wstrb: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", mem_req_wr_data_wstrb__h5367); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "wuser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_fabric_send_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + cache_cfg_verbosity != 4'd0 && + !cache_f_reset_reqs$D_OUT) + begin + v__h6477 = $stime; + #0; + end + v__h6471 = v__h6477 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + cache_cfg_verbosity != 4'd0 && + !cache_f_reset_reqs$D_OUT) + $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY", + v__h6471, + "I_MMU_Cache", + $signed(32'd128), + $signed(32'd1)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_f_reset_reqs$D_OUT) + begin + v__h6580 = $stime; + #0; + end + v__h6574 = v__h6580 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_reset && cache_rg_cset_in_cache == 7'd127 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_f_reset_reqs$D_OUT) + $display("%0d: %s.rl_reset: Flushed", v__h6574, "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h7034 = $stime; + #0; + end + v__h7028 = v__h7034 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h", + v__h7028, + "I_MMU_Cache", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}", + pa_ctag__h7888, + cache_rg_addr[11:5], + cache_rg_addr[4:3], + cache_rg_addr[2:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" CSet 0x%0x: (state, tag):", cache_rg_addr[11:5]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" ("); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_ram_state_and_ctag_cset$DOB[22]) + $write("CTAG_CLEAN"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_ram_state_and_ctag_cset$DOB[22]) + $write("CTAG_EMPTY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_ram_state_and_ctag_cset$DOB[22]) + $write(", 0x%0x", cache_ram_state_and_ctag_cset$DOB[21:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_ram_state_and_ctag_cset$DOB[22]) + $write(", --"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(")"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" 0x%0x", cache_ram_word64_set$DOB); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" TLB result: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("VM_Xlate_Result { ", "outcome: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("VM_XLATE_OK"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "pa: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "exc_code: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'hA, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d350) + begin + v__h15467 = $stime; + #0; + end + v__h15461 = v__h15467 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d350) + $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", + v__h15461, + "I_MMU_Cache", + cache_rg_addr, + word64__h7992, + 64'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00010 && + cache_ram_state_and_ctag_cset$DOB[22] && + cache_ram_state_and_ctag_cset_b_read__51_BITS__ETC___d157 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO LR: reserving PA 0x%0h", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d350) + $display(" Read-hit: addr 0x%0h word64 0x%0h", + cache_rg_addr, + word64__h7992); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_0_30_OR_cache_rg_op_29_EQ_2__ETC___d360) + $display(" Read Miss: -> CACHE_START_REFILL."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd2 && + cache_rg_amo_funct7_32_BITS_6_TO_2_33_EQ_0b10__ETC___d363) + $display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h", + cache_rg_lrsc_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd1 && + cache_rg_addr_44_EQ_cache_rg_lrsc_pa_43___d184 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" ST: cancelling LR/SC reservation for PA", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + cache_rg_lrsc_valid && + !cache_rg_lrsc_pa_43_EQ_cache_rg_addr_44___d145 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h", + cache_rg_lrsc_pa, + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + !cache_rg_lrsc_valid && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC: fail due to invalid LR/SC reservation"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op == 2'd2 && + cache_rg_amo_funct7[6:2] == 5'b00011 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" AMO SC result = %0d", lrsc_result__h15844); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528) + $display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528) + $write(" New Word64_Set:"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528) + $write(" 0x%0x", + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d428); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d528) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + (cache_rg_op == 2'd1 || + cache_rg_op == 2'd2 && cache_rg_amo_funct7[6:2] == 5'b00011) && + NOT_cache_rg_op_29_EQ_2_31_65_OR_NOT_cache_rg__ETC___d529) + $display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d534) + $display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h", + cache_rg_addr, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + NOT_cache_rg_op_29_EQ_0_30_64_AND_NOT_cache_rg_ETC___d534) + $display(" => rl_write_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d537) + begin + v__h19180 = $stime; + #0; + end + v__h19174 = v__h19180 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d537) + $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h", + v__h19174, + "I_MMU_Cache", + cache_rg_addr, + 64'd1, + 64'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && + cache_rg_op_29_EQ_2_31_AND_cache_rg_amo_funct7_ETC___d537) + $display(" AMO SC: Fail response for addr 0x%0h", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d540) + $display(" AMO Miss: -> CACHE_START_REFILL."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h", + cache_rg_addr, + cache_rg_amo_funct7, + cache_rg_f3, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $display(" PA 0x%0h ", cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $display(" Cache word64 0x%0h, load-result 0x%0h", + word64__h7992, + word64__h7992); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $display(" 0x%0h op 0x%0h -> 0x%0h", + word64__h7992, + word64__h7992, + new_st_val__h19402); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $write(" New Word64_Set:"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_addr[4:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $write(" 0x%0x", + IF_cache_rg_f3_05_EQ_0b0_06_THEN_IF_cache_rg_a_ETC___d502); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d542) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_probe_and_immed_rsp && cache_rg_op != 2'd0 && + (cache_rg_op != 2'd2 || cache_rg_amo_funct7[6:2] != 5'b00010) && + NOT_cache_rg_op_29_EQ_1_37_92_AND_NOT_cache_rg_ETC___d545) + $display(" AMO_op: cancelling LR/SC reservation for PA", + cache_rg_addr); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h22537 = $stime; + #0; + end + v__h22531 = v__h22537 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_start_cache_refill: ", v__h22531, "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 5'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cline_fabric_addr__h22590); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd3); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'b011, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_cache_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" Victim way %0d; => CACHE_REFILL", 1'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_rereq && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", + cache_rg_addr[11:5], + cache_rg_addr[11:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h25370 = $stime; + #0; + end + v__h25364 = v__h25370 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h", + v__h25364, + "I_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 5'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", fabric_addr__h27561); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", size_val__h27675, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_maintain_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27092 = $stime; + #0; + end + v__h27086 = v__h27092 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_maintain_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h27086, + "I_MMU_Cache", + cache_rg_addr, + cache_rg_ld_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27175 = $stime; + #0; + end + v__h27169 = v__h27175 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h27169, + "I_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_write_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27388 = $stime; + #0; + end + v__h27382 = v__h27388 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h27382, + "I_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" FAIL due to I/O address."); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_SC_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27509 = $stime; + #0; + end + v__h27503 = v__h27509 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h", + v__h27503, + "I_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" To fabric: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 5'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "araddr: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", fabric_addr__h27561); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlen: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arsize: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", size_val__h27675, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arburst: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arlock: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arcache: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'b0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arprot: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 3'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arqos: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "arregion: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 4'd0); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "aruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'h0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_op_req && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_aw_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_w_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_b_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h31052 = $stime; + #0; + end + v__h31046 = v__h31052 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("%0d: %s.rl_discard_write_rsp: pending %0d ", + v__h31046, + "I_MMU_Cache", + $unsigned(b__h22491)); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_bff_rv$port1__read[6:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + begin + v__h31013 = $stime; + #0; + end + v__h31007 = v__h31013 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit", + v__h31007, + "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("AXI4_BFlit { ", "bid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("'h%h", cache_master_xactor_shim_bff_rv$port1__read[6:2]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(", ", "bresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0 && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd1 && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write(", ", "buser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_discard_write_rsp && + cache_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_reset && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h6102 = $stime; + #0; + end + v__h6096 = v__h6102 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_start_reset && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_start_reset", v__h6096, "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_ar_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_master_xactor_ug_master_u_r_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + begin + v__h23486 = $stime; + #0; + end + v__h23480 = v__h23486 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $display("%0d: %s.rl_cache_refill_rsps_loop:", + v__h23480, + "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[71:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h23740 = $stime; + #0; + end + v__h23734 = v__h23740 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d", + v__h23734, + "I_MMU_Cache", + 4'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 && + (cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 || + cache_rg_error_during_refill) && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => MODULE_EXCEPTION_RSP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + cache_rg_word64_set_in_cache[1:0] == 2'd3 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + !cache_rg_error_during_refill && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => CACHE_REREQ"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new", + cache_rg_word64_set_in_cache, + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(" 0x%0x", cache_ram_word64_set$DOB); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(" CSet 0x%0x, Word64 0x%0x: ", + cache_rg_addr[11:5], + cache_rg_word64_set_in_cache[1:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write(" 0x%0x", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_cache_refill_rsps_loop && + NOT_cache_cfg_verbosity_read__9_ULE_2_72___d573) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h25756 = $stime; + #0; + end + v__h25750 = v__h25756 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h", + v__h25750, + "I_MMU_Cache", + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[71:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26874 = $stime; + #0; + end + v__h26868 = v__h26874 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h26868, + "I_MMU_Cache", + cache_rg_addr, + ld_val__h25881); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h26982 = $stime; + #0; + end + v__h26976 = v__h26982 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT", + v__h26976, + "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h27839 = $stime; + #0; + end + v__h27833 = v__h27839 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h", + v__h27833, + "I_MMU_Cache", + cache_rg_addr, + cache_rg_pa); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("AXI4_RFlit { ", "rid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[71:67]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", cache_master_xactor_shim_rff_rv$port1__read[66:3]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rresp: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd1) + $write("EXOKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd2) + $write("SLVERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd1 && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd2) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "rlast: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("True"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + !cache_master_xactor_shim_rff_rv$port1__read[0]) + $write("False"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(", ", "ruser: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("'h%h", 1'd0, " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h28034 = $stime; + #0; + end + v__h28028 = v__h28034 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h", + v__h28028, + "I_MMU_Cache", + cache_rg_f3, + cache_rg_addr, + cache_rg_pa, + cache_rg_st_amo_val); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h30336 = $stime; + #0; + end + v__h30330 = v__h30336 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h", + v__h30330, + "I_MMU_Cache", + cache_rg_addr, + new_ld_val__h28161); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] == 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" => rl_ST_AMO_response"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h28131 = $stime; + #0; + end + v__h28125 = v__h28131 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cache_rl_io_AMO_read_rsp && + cache_master_xactor_shim_rff_rv$port1__read[2:1] != 2'd0 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT", + v__h28125, + "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + begin + v__h31440 = $stime; + #0; + end + v__h31434 = v__h31440 / 32'd10; + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write("%0d: %s.req: op:", v__h31434, "I_MMU_Cache"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op == 2'd0) + $write("CACHE_LD"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op == 2'd1) + $write("CACHE_ST"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_op != 2'd0 && + req_op != 2'd1) + $write("CACHE_AMO"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" f3:%0d addr:0x%0h st_value:0x%0h priv:", + req_f3, + req_addr, + req_st_value); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b0) + $write("U"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b01) + $write("S"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv == 2'b11) + $write("M"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91 && + req_priv != 2'b0 && + req_priv != 2'b01 && + req_priv != 2'b11) + $write("RESERVED"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h", + req_sstatus_SUM, + req_mstatus_MXR, + req_satp, + "\n"); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" amo_funct7 = 0x%0h", req_amo_funct7); + if (RST_N != `BSV_RESET_VALUE) + if (EN_req && + req_f3_BITS_1_TO_0_13_EQ_0b0_14_OR_req_f3_BITS_ETC___d943 && + NOT_cache_cfg_verbosity_read__9_ULE_1_0___d91) + $display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]", + req_addr[11:5], + req_addr[11:3]); + end + // synopsys translate_on +endmodule // mkMMU_ICache + diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem.v b/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem.v index 66849c25..be881b5c 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:46 BST 2019 // // // Ports: @@ -15,66 +15,66 @@ // imem_exc O 1 // imem_exc_code O 4 reg // imem_tval O 32 reg +// imem_master_awid O 5 +// imem_master_awaddr O 64 +// imem_master_awlen O 8 +// imem_master_awsize O 3 +// imem_master_awburst O 2 +// imem_master_awlock O 1 +// imem_master_awcache O 4 +// imem_master_awprot O 3 +// imem_master_awqos O 4 +// imem_master_awregion O 4 // imem_master_awvalid O 1 -// imem_master_awid O 4 reg -// imem_master_awaddr O 64 reg -// imem_master_awlen O 8 reg -// imem_master_awsize O 3 reg -// imem_master_awburst O 2 reg -// imem_master_awlock O 1 reg -// imem_master_awcache O 4 reg -// imem_master_awprot O 3 reg -// imem_master_awqos O 4 reg -// imem_master_awregion O 4 reg +// imem_master_wdata O 64 +// imem_master_wstrb O 8 +// imem_master_wlast O 1 // imem_master_wvalid O 1 -// imem_master_wdata O 64 reg -// imem_master_wstrb O 8 reg -// imem_master_wlast O 1 reg // imem_master_bready O 1 +// imem_master_arid O 5 +// imem_master_araddr O 64 +// imem_master_arlen O 8 +// imem_master_arsize O 3 +// imem_master_arburst O 2 +// imem_master_arlock O 1 +// imem_master_arcache O 4 +// imem_master_arprot O 3 +// imem_master_arqos O 4 +// imem_master_arregion O 4 // imem_master_arvalid O 1 -// imem_master_arid O 4 reg -// imem_master_araddr O 64 reg -// imem_master_arlen O 8 reg -// imem_master_arsize O 3 reg -// imem_master_arburst O 2 reg -// imem_master_arlock O 1 reg -// imem_master_arcache O 4 reg -// imem_master_arprot O 3 reg -// imem_master_arqos O 4 reg -// imem_master_arregion O 4 reg // imem_master_rready O 1 // dmem_valid O 1 // dmem_word64 O 64 // dmem_st_amo_val O 64 // dmem_exc O 1 // dmem_exc_code O 4 reg +// dmem_master_awid O 4 +// dmem_master_awaddr O 64 +// dmem_master_awlen O 8 +// dmem_master_awsize O 3 +// dmem_master_awburst O 2 +// dmem_master_awlock O 1 +// dmem_master_awcache O 4 +// dmem_master_awprot O 3 +// dmem_master_awqos O 4 +// dmem_master_awregion O 4 // dmem_master_awvalid O 1 -// dmem_master_awid O 4 reg -// dmem_master_awaddr O 64 reg -// dmem_master_awlen O 8 reg -// dmem_master_awsize O 3 reg -// dmem_master_awburst O 2 reg -// dmem_master_awlock O 1 reg -// dmem_master_awcache O 4 reg -// dmem_master_awprot O 3 reg -// dmem_master_awqos O 4 reg -// dmem_master_awregion O 4 reg +// dmem_master_wdata O 64 +// dmem_master_wstrb O 8 +// dmem_master_wlast O 1 // dmem_master_wvalid O 1 -// dmem_master_wdata O 64 reg -// dmem_master_wstrb O 8 reg -// dmem_master_wlast O 1 reg // dmem_master_bready O 1 +// dmem_master_arid O 4 +// dmem_master_araddr O 64 +// dmem_master_arlen O 8 +// dmem_master_arsize O 3 +// dmem_master_arburst O 2 +// dmem_master_arlock O 1 +// dmem_master_arcache O 4 +// dmem_master_arprot O 3 +// dmem_master_arqos O 4 +// dmem_master_arregion O 4 // dmem_master_arvalid O 1 -// dmem_master_arid O 4 reg -// dmem_master_araddr O 64 reg -// dmem_master_arlen O 8 reg -// dmem_master_arsize O 3 reg -// dmem_master_arburst O 2 reg -// dmem_master_arlock O 1 reg -// dmem_master_arcache O 4 reg -// dmem_master_arprot O 3 reg -// dmem_master_arqos O 4 reg -// dmem_master_arregion O 4 reg // dmem_master_rready O 1 // RDY_server_fence_i_request_put O 1 // RDY_server_fence_i_response_get O 1 @@ -91,15 +91,13 @@ // imem_req_satp I 32 unused // imem_master_awready I 1 // imem_master_wready I 1 -// imem_master_bvalid I 1 -// imem_master_bid I 4 reg -// imem_master_bresp I 2 reg +// imem_master_bid I 5 +// imem_master_bresp I 2 // imem_master_arready I 1 -// imem_master_rvalid I 1 -// imem_master_rid I 4 reg -// imem_master_rdata I 64 reg -// imem_master_rresp I 2 reg -// imem_master_rlast I 1 reg +// imem_master_rid I 5 +// imem_master_rdata I 64 +// imem_master_rresp I 2 +// imem_master_rlast I 1 // dmem_req_op I 2 // dmem_req_f3 I 3 // dmem_req_amo_funct7 I 7 reg @@ -111,20 +109,22 @@ // dmem_req_satp I 32 unused // dmem_master_awready I 1 // dmem_master_wready I 1 -// dmem_master_bvalid I 1 -// dmem_master_bid I 4 reg -// dmem_master_bresp I 2 reg +// dmem_master_bid I 4 +// dmem_master_bresp I 2 // dmem_master_arready I 1 -// dmem_master_rvalid I 1 -// dmem_master_rid I 4 reg -// dmem_master_rdata I 64 reg -// dmem_master_rresp I 2 reg -// dmem_master_rlast I 1 reg +// dmem_master_rid I 4 +// dmem_master_rdata I 64 +// dmem_master_rresp I 2 +// dmem_master_rlast I 1 // server_fence_request_put I 8 unused // EN_server_reset_request_put I 1 // EN_server_reset_response_get I 1 // EN_imem_req I 1 +// imem_master_bvalid I 1 +// imem_master_rvalid I 1 // EN_dmem_req I 1 +// dmem_master_bvalid I 1 +// dmem_master_rvalid I 1 // EN_server_fence_i_request_put I 1 // EN_server_fence_i_response_get I 1 // EN_server_fence_request_put I 1 @@ -132,15 +132,50 @@ // EN_sfence_vma I 1 unused // // Combinational paths from inputs to outputs: -// (imem_master_awready, imem_master_wready) -> imem_valid -// (imem_master_awready, imem_master_wready) -> imem_instr -// (imem_master_awready, imem_master_wready) -> imem_master_bready -// (imem_master_awready, imem_master_wready, EN_imem_req) -> imem_master_rready -// (dmem_master_awready, dmem_master_wready) -> dmem_valid -// (dmem_master_awready, dmem_master_wready) -> dmem_word64 -// (dmem_master_awready, dmem_master_wready) -> dmem_st_amo_val -// (dmem_master_awready, dmem_master_wready) -> dmem_master_bready -// (dmem_master_awready, dmem_master_wready, EN_dmem_req) -> dmem_master_rready +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// imem_master_rvalid) -> imem_valid +// (imem_master_rid, +// imem_master_rdata, +// imem_master_rresp, +// imem_master_rlast, +// imem_master_rvalid) -> imem_instr +// (dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// dmem_master_rvalid) -> dmem_valid +// (dmem_master_rid, +// dmem_master_rdata, +// dmem_master_rresp, +// dmem_master_rlast, +// dmem_master_rvalid) -> dmem_word64 +// EN_imem_req -> imem_master_arid +// EN_imem_req -> imem_master_araddr +// EN_imem_req -> imem_master_arlen +// EN_imem_req -> imem_master_arsize +// EN_imem_req -> imem_master_arburst +// EN_imem_req -> imem_master_arlock +// EN_imem_req -> imem_master_arcache +// EN_imem_req -> imem_master_arprot +// EN_imem_req -> imem_master_arqos +// EN_imem_req -> imem_master_arregion +// EN_imem_req -> imem_master_aruser +// EN_imem_req -> imem_master_arvalid +// EN_dmem_req -> dmem_master_arid +// EN_dmem_req -> dmem_master_araddr +// EN_dmem_req -> dmem_master_arlen +// EN_dmem_req -> dmem_master_arsize +// EN_dmem_req -> dmem_master_arburst +// EN_dmem_req -> dmem_master_arlock +// EN_dmem_req -> dmem_master_arcache +// EN_dmem_req -> dmem_master_arprot +// EN_dmem_req -> dmem_master_arqos +// EN_dmem_req -> dmem_master_arregion +// EN_dmem_req -> dmem_master_aruser +// EN_dmem_req -> dmem_master_arvalid // // @@ -188,8 +223,6 @@ module mkNear_Mem(CLK, imem_tval, - imem_master_awvalid, - imem_master_awid, imem_master_awaddr, @@ -210,9 +243,9 @@ module mkNear_Mem(CLK, imem_master_awregion, - imem_master_awready, + imem_master_awvalid, - imem_master_wvalid, + imem_master_awready, imem_master_wdata, @@ -220,16 +253,16 @@ module mkNear_Mem(CLK, imem_master_wlast, + imem_master_wvalid, + imem_master_wready, - imem_master_bvalid, imem_master_bid, imem_master_bresp, + imem_master_bvalid, imem_master_bready, - imem_master_arvalid, - imem_master_arid, imem_master_araddr, @@ -250,13 +283,15 @@ module mkNear_Mem(CLK, imem_master_arregion, + imem_master_arvalid, + imem_master_arready, - imem_master_rvalid, imem_master_rid, imem_master_rdata, imem_master_rresp, imem_master_rlast, + imem_master_rvalid, imem_master_rready, @@ -281,8 +316,6 @@ module mkNear_Mem(CLK, dmem_exc_code, - dmem_master_awvalid, - dmem_master_awid, dmem_master_awaddr, @@ -303,9 +336,9 @@ module mkNear_Mem(CLK, dmem_master_awregion, - dmem_master_awready, + dmem_master_awvalid, - dmem_master_wvalid, + dmem_master_awready, dmem_master_wdata, @@ -313,16 +346,16 @@ module mkNear_Mem(CLK, dmem_master_wlast, + dmem_master_wvalid, + dmem_master_wready, - dmem_master_bvalid, dmem_master_bid, dmem_master_bresp, + dmem_master_bvalid, dmem_master_bready, - dmem_master_arvalid, - dmem_master_arid, dmem_master_araddr, @@ -343,13 +376,15 @@ module mkNear_Mem(CLK, dmem_master_arregion, + dmem_master_arvalid, + dmem_master_arready, - dmem_master_rvalid, dmem_master_rid, dmem_master_rdata, dmem_master_rresp, dmem_master_rlast, + dmem_master_rvalid, dmem_master_rready, @@ -409,115 +444,115 @@ module mkNear_Mem(CLK, // value method imem_tval output [31 : 0] imem_tval; - // value method imem_master_m_awvalid - output imem_master_awvalid; - - // value method imem_master_m_awid - output [3 : 0] imem_master_awid; + // value method imem_master_aw_awid + output [4 : 0] imem_master_awid; - // value method imem_master_m_awaddr + // value method imem_master_aw_awaddr output [63 : 0] imem_master_awaddr; - // value method imem_master_m_awlen + // value method imem_master_aw_awlen output [7 : 0] imem_master_awlen; - // value method imem_master_m_awsize + // value method imem_master_aw_awsize output [2 : 0] imem_master_awsize; - // value method imem_master_m_awburst + // value method imem_master_aw_awburst output [1 : 0] imem_master_awburst; - // value method imem_master_m_awlock + // value method imem_master_aw_awlock output imem_master_awlock; - // value method imem_master_m_awcache + // value method imem_master_aw_awcache output [3 : 0] imem_master_awcache; - // value method imem_master_m_awprot + // value method imem_master_aw_awprot output [2 : 0] imem_master_awprot; - // value method imem_master_m_awqos + // value method imem_master_aw_awqos output [3 : 0] imem_master_awqos; - // value method imem_master_m_awregion + // value method imem_master_aw_awregion output [3 : 0] imem_master_awregion; - // value method imem_master_m_awuser + // value method imem_master_aw_awuser - // action method imem_master_m_awready - input imem_master_awready; + // value method imem_master_aw_awvalid + output imem_master_awvalid; - // value method imem_master_m_wvalid - output imem_master_wvalid; + // action method imem_master_aw_awready + input imem_master_awready; - // value method imem_master_m_wdata + // value method imem_master_w_wdata output [63 : 0] imem_master_wdata; - // value method imem_master_m_wstrb + // value method imem_master_w_wstrb output [7 : 0] imem_master_wstrb; - // value method imem_master_m_wlast + // value method imem_master_w_wlast output imem_master_wlast; - // value method imem_master_m_wuser + // value method imem_master_w_wuser - // action method imem_master_m_wready + // value method imem_master_w_wvalid + output imem_master_wvalid; + + // action method imem_master_w_wready input imem_master_wready; - // action method imem_master_m_bvalid - input imem_master_bvalid; - input [3 : 0] imem_master_bid; + // action method imem_master_b_bflit + input [4 : 0] imem_master_bid; input [1 : 0] imem_master_bresp; + input imem_master_bvalid; - // value method imem_master_m_bready + // value method imem_master_b_bready output imem_master_bready; - // value method imem_master_m_arvalid - output imem_master_arvalid; - - // value method imem_master_m_arid - output [3 : 0] imem_master_arid; + // value method imem_master_ar_arid + output [4 : 0] imem_master_arid; - // value method imem_master_m_araddr + // value method imem_master_ar_araddr output [63 : 0] imem_master_araddr; - // value method imem_master_m_arlen + // value method imem_master_ar_arlen output [7 : 0] imem_master_arlen; - // value method imem_master_m_arsize + // value method imem_master_ar_arsize output [2 : 0] imem_master_arsize; - // value method imem_master_m_arburst + // value method imem_master_ar_arburst output [1 : 0] imem_master_arburst; - // value method imem_master_m_arlock + // value method imem_master_ar_arlock output imem_master_arlock; - // value method imem_master_m_arcache + // value method imem_master_ar_arcache output [3 : 0] imem_master_arcache; - // value method imem_master_m_arprot + // value method imem_master_ar_arprot output [2 : 0] imem_master_arprot; - // value method imem_master_m_arqos + // value method imem_master_ar_arqos output [3 : 0] imem_master_arqos; - // value method imem_master_m_arregion + // value method imem_master_ar_arregion output [3 : 0] imem_master_arregion; - // value method imem_master_m_aruser + // value method imem_master_ar_aruser - // action method imem_master_m_arready + // value method imem_master_ar_arvalid + output imem_master_arvalid; + + // action method imem_master_ar_arready input imem_master_arready; - // action method imem_master_m_rvalid - input imem_master_rvalid; - input [3 : 0] imem_master_rid; + // action method imem_master_r_rflit + input [4 : 0] imem_master_rid; input [63 : 0] imem_master_rdata; input [1 : 0] imem_master_rresp; input imem_master_rlast; + input imem_master_rvalid; - // value method imem_master_m_rready + // value method imem_master_r_rready output imem_master_rready; // action method dmem_req @@ -547,115 +582,115 @@ module mkNear_Mem(CLK, // value method dmem_exc_code output [3 : 0] dmem_exc_code; - // value method dmem_master_m_awvalid - output dmem_master_awvalid; - - // value method dmem_master_m_awid + // value method dmem_master_aw_awid output [3 : 0] dmem_master_awid; - // value method dmem_master_m_awaddr + // value method dmem_master_aw_awaddr output [63 : 0] dmem_master_awaddr; - // value method dmem_master_m_awlen + // value method dmem_master_aw_awlen output [7 : 0] dmem_master_awlen; - // value method dmem_master_m_awsize + // value method dmem_master_aw_awsize output [2 : 0] dmem_master_awsize; - // value method dmem_master_m_awburst + // value method dmem_master_aw_awburst output [1 : 0] dmem_master_awburst; - // value method dmem_master_m_awlock + // value method dmem_master_aw_awlock output dmem_master_awlock; - // value method dmem_master_m_awcache + // value method dmem_master_aw_awcache output [3 : 0] dmem_master_awcache; - // value method dmem_master_m_awprot + // value method dmem_master_aw_awprot output [2 : 0] dmem_master_awprot; - // value method dmem_master_m_awqos + // value method dmem_master_aw_awqos output [3 : 0] dmem_master_awqos; - // value method dmem_master_m_awregion + // value method dmem_master_aw_awregion output [3 : 0] dmem_master_awregion; - // value method dmem_master_m_awuser + // value method dmem_master_aw_awuser - // action method dmem_master_m_awready - input dmem_master_awready; + // value method dmem_master_aw_awvalid + output dmem_master_awvalid; - // value method dmem_master_m_wvalid - output dmem_master_wvalid; + // action method dmem_master_aw_awready + input dmem_master_awready; - // value method dmem_master_m_wdata + // value method dmem_master_w_wdata output [63 : 0] dmem_master_wdata; - // value method dmem_master_m_wstrb + // value method dmem_master_w_wstrb output [7 : 0] dmem_master_wstrb; - // value method dmem_master_m_wlast + // value method dmem_master_w_wlast output dmem_master_wlast; - // value method dmem_master_m_wuser + // value method dmem_master_w_wuser + + // value method dmem_master_w_wvalid + output dmem_master_wvalid; - // action method dmem_master_m_wready + // action method dmem_master_w_wready input dmem_master_wready; - // action method dmem_master_m_bvalid - input dmem_master_bvalid; + // action method dmem_master_b_bflit input [3 : 0] dmem_master_bid; input [1 : 0] dmem_master_bresp; + input dmem_master_bvalid; - // value method dmem_master_m_bready + // value method dmem_master_b_bready output dmem_master_bready; - // value method dmem_master_m_arvalid - output dmem_master_arvalid; - - // value method dmem_master_m_arid + // value method dmem_master_ar_arid output [3 : 0] dmem_master_arid; - // value method dmem_master_m_araddr + // value method dmem_master_ar_araddr output [63 : 0] dmem_master_araddr; - // value method dmem_master_m_arlen + // value method dmem_master_ar_arlen output [7 : 0] dmem_master_arlen; - // value method dmem_master_m_arsize + // value method dmem_master_ar_arsize output [2 : 0] dmem_master_arsize; - // value method dmem_master_m_arburst + // value method dmem_master_ar_arburst output [1 : 0] dmem_master_arburst; - // value method dmem_master_m_arlock + // value method dmem_master_ar_arlock output dmem_master_arlock; - // value method dmem_master_m_arcache + // value method dmem_master_ar_arcache output [3 : 0] dmem_master_arcache; - // value method dmem_master_m_arprot + // value method dmem_master_ar_arprot output [2 : 0] dmem_master_arprot; - // value method dmem_master_m_arqos + // value method dmem_master_ar_arqos output [3 : 0] dmem_master_arqos; - // value method dmem_master_m_arregion + // value method dmem_master_ar_arregion output [3 : 0] dmem_master_arregion; - // value method dmem_master_m_aruser + // value method dmem_master_ar_aruser + + // value method dmem_master_ar_arvalid + output dmem_master_arvalid; - // action method dmem_master_m_arready + // action method dmem_master_ar_arready input dmem_master_arready; - // action method dmem_master_m_rvalid - input dmem_master_rvalid; + // action method dmem_master_r_rflit input [3 : 0] dmem_master_rid; input [63 : 0] dmem_master_rdata; input [1 : 0] dmem_master_rresp; input dmem_master_rlast; + input dmem_master_rvalid; - // value method dmem_master_m_rready + // value method dmem_master_r_rready output dmem_master_rready; // action method server_fence_i_request_put @@ -695,6 +730,7 @@ module mkNear_Mem(CLK, imem_master_arlen, imem_master_awlen, imem_master_wstrb; + wire [4 : 0] imem_master_arid, imem_master_awid; wire [3 : 0] dmem_exc_code, dmem_master_arcache, dmem_master_arid, @@ -706,11 +742,9 @@ module mkNear_Mem(CLK, dmem_master_awregion, imem_exc_code, imem_master_arcache, - imem_master_arid, imem_master_arqos, imem_master_arregion, imem_master_awcache, - imem_master_awid, imem_master_awqos, imem_master_awregion; wire [2 : 0] dmem_master_arprot, @@ -849,17 +883,17 @@ module mkNear_Mem(CLK, icache$mem_master_awlen, icache$mem_master_wstrb; wire [6 : 0] icache$req_amo_funct7; + wire [4 : 0] icache$mem_master_arid, + icache$mem_master_awid, + icache$mem_master_bid, + icache$mem_master_rid; wire [3 : 0] icache$exc_code, icache$mem_master_arcache, - icache$mem_master_arid, icache$mem_master_arqos, icache$mem_master_arregion, icache$mem_master_awcache, - icache$mem_master_awid, icache$mem_master_awqos, icache$mem_master_awregion, - icache$mem_master_bid, - icache$mem_master_rid, icache$set_verbosity_verbosity; wire [2 : 0] icache$mem_master_arprot, icache$mem_master_arsize, @@ -910,17 +944,17 @@ module mkNear_Mem(CLK, // rule scheduling signals wire CAN_FIRE_RL_rl_reset, CAN_FIRE_RL_rl_reset_complete, - CAN_FIRE_dmem_master_m_arready, - CAN_FIRE_dmem_master_m_awready, - CAN_FIRE_dmem_master_m_bvalid, - CAN_FIRE_dmem_master_m_rvalid, - CAN_FIRE_dmem_master_m_wready, + CAN_FIRE_dmem_master_ar_arready, + CAN_FIRE_dmem_master_aw_awready, + CAN_FIRE_dmem_master_b_bflit, + CAN_FIRE_dmem_master_r_rflit, + CAN_FIRE_dmem_master_w_wready, CAN_FIRE_dmem_req, - CAN_FIRE_imem_master_m_arready, - CAN_FIRE_imem_master_m_awready, - CAN_FIRE_imem_master_m_bvalid, - CAN_FIRE_imem_master_m_rvalid, - CAN_FIRE_imem_master_m_wready, + CAN_FIRE_imem_master_ar_arready, + CAN_FIRE_imem_master_aw_awready, + CAN_FIRE_imem_master_b_bflit, + CAN_FIRE_imem_master_r_rflit, + CAN_FIRE_imem_master_w_wready, CAN_FIRE_imem_req, CAN_FIRE_server_fence_i_request_put, CAN_FIRE_server_fence_i_response_get, @@ -931,17 +965,17 @@ module mkNear_Mem(CLK, CAN_FIRE_sfence_vma, WILL_FIRE_RL_rl_reset, WILL_FIRE_RL_rl_reset_complete, - WILL_FIRE_dmem_master_m_arready, - WILL_FIRE_dmem_master_m_awready, - WILL_FIRE_dmem_master_m_bvalid, - WILL_FIRE_dmem_master_m_rvalid, - WILL_FIRE_dmem_master_m_wready, + WILL_FIRE_dmem_master_ar_arready, + WILL_FIRE_dmem_master_aw_awready, + WILL_FIRE_dmem_master_b_bflit, + WILL_FIRE_dmem_master_r_rflit, + WILL_FIRE_dmem_master_w_wready, WILL_FIRE_dmem_req, - WILL_FIRE_imem_master_m_arready, - WILL_FIRE_imem_master_m_awready, - WILL_FIRE_imem_master_m_bvalid, - WILL_FIRE_imem_master_m_rvalid, - WILL_FIRE_imem_master_m_wready, + WILL_FIRE_imem_master_ar_arready, + WILL_FIRE_imem_master_aw_awready, + WILL_FIRE_imem_master_b_bflit, + WILL_FIRE_imem_master_r_rflit, + WILL_FIRE_imem_master_w_wready, WILL_FIRE_imem_req, WILL_FIRE_server_fence_i_request_put, WILL_FIRE_server_fence_i_response_get, @@ -952,14 +986,14 @@ module mkNear_Mem(CLK, WILL_FIRE_sfence_vma; // inputs to muxes for submodule ports - wire MUX_rg_state$write_1__SEL_3; + wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h1767; - reg [31 : 0] v__h1918; - reg [31 : 0] v__h1761; - reg [31 : 0] v__h1912; + reg [31 : 0] v__h1541; + reg [31 : 0] v__h1692; + reg [31 : 0] v__h1535; + reg [31 : 0] v__h1686; // synopsys translate_on // remaining internal signals @@ -1000,108 +1034,108 @@ module mkNear_Mem(CLK, // value method imem_tval assign imem_tval = icache$addr ; - // value method imem_master_m_awvalid - assign imem_master_awvalid = icache$mem_master_awvalid ; - - // value method imem_master_m_awid + // value method imem_master_aw_awid assign imem_master_awid = icache$mem_master_awid ; - // value method imem_master_m_awaddr + // value method imem_master_aw_awaddr assign imem_master_awaddr = icache$mem_master_awaddr ; - // value method imem_master_m_awlen + // value method imem_master_aw_awlen assign imem_master_awlen = icache$mem_master_awlen ; - // value method imem_master_m_awsize + // value method imem_master_aw_awsize assign imem_master_awsize = icache$mem_master_awsize ; - // value method imem_master_m_awburst + // value method imem_master_aw_awburst assign imem_master_awburst = icache$mem_master_awburst ; - // value method imem_master_m_awlock + // value method imem_master_aw_awlock assign imem_master_awlock = icache$mem_master_awlock ; - // value method imem_master_m_awcache + // value method imem_master_aw_awcache assign imem_master_awcache = icache$mem_master_awcache ; - // value method imem_master_m_awprot + // value method imem_master_aw_awprot assign imem_master_awprot = icache$mem_master_awprot ; - // value method imem_master_m_awqos + // value method imem_master_aw_awqos assign imem_master_awqos = icache$mem_master_awqos ; - // value method imem_master_m_awregion + // value method imem_master_aw_awregion assign imem_master_awregion = icache$mem_master_awregion ; - // action method imem_master_m_awready - assign CAN_FIRE_imem_master_m_awready = 1'd1 ; - assign WILL_FIRE_imem_master_m_awready = 1'd1 ; + // value method imem_master_aw_awvalid + assign imem_master_awvalid = icache$mem_master_awvalid ; - // value method imem_master_m_wvalid - assign imem_master_wvalid = icache$mem_master_wvalid ; + // action method imem_master_aw_awready + assign CAN_FIRE_imem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_imem_master_aw_awready = 1'd1 ; - // value method imem_master_m_wdata + // value method imem_master_w_wdata assign imem_master_wdata = icache$mem_master_wdata ; - // value method imem_master_m_wstrb + // value method imem_master_w_wstrb assign imem_master_wstrb = icache$mem_master_wstrb ; - // value method imem_master_m_wlast + // value method imem_master_w_wlast assign imem_master_wlast = icache$mem_master_wlast ; - // action method imem_master_m_wready - assign CAN_FIRE_imem_master_m_wready = 1'd1 ; - assign WILL_FIRE_imem_master_m_wready = 1'd1 ; + // value method imem_master_w_wvalid + assign imem_master_wvalid = icache$mem_master_wvalid ; - // action method imem_master_m_bvalid - assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ; + // action method imem_master_w_wready + assign CAN_FIRE_imem_master_w_wready = 1'd1 ; + assign WILL_FIRE_imem_master_w_wready = 1'd1 ; - // value method imem_master_m_bready - assign imem_master_bready = icache$mem_master_bready ; + // action method imem_master_b_bflit + assign CAN_FIRE_imem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_imem_master_b_bflit = imem_master_bvalid ; - // value method imem_master_m_arvalid - assign imem_master_arvalid = icache$mem_master_arvalid ; + // value method imem_master_b_bready + assign imem_master_bready = icache$mem_master_bready ; - // value method imem_master_m_arid + // value method imem_master_ar_arid assign imem_master_arid = icache$mem_master_arid ; - // value method imem_master_m_araddr + // value method imem_master_ar_araddr assign imem_master_araddr = icache$mem_master_araddr ; - // value method imem_master_m_arlen + // value method imem_master_ar_arlen assign imem_master_arlen = icache$mem_master_arlen ; - // value method imem_master_m_arsize + // value method imem_master_ar_arsize assign imem_master_arsize = icache$mem_master_arsize ; - // value method imem_master_m_arburst + // value method imem_master_ar_arburst assign imem_master_arburst = icache$mem_master_arburst ; - // value method imem_master_m_arlock + // value method imem_master_ar_arlock assign imem_master_arlock = icache$mem_master_arlock ; - // value method imem_master_m_arcache + // value method imem_master_ar_arcache assign imem_master_arcache = icache$mem_master_arcache ; - // value method imem_master_m_arprot + // value method imem_master_ar_arprot assign imem_master_arprot = icache$mem_master_arprot ; - // value method imem_master_m_arqos + // value method imem_master_ar_arqos assign imem_master_arqos = icache$mem_master_arqos ; - // value method imem_master_m_arregion + // value method imem_master_ar_arregion assign imem_master_arregion = icache$mem_master_arregion ; - // action method imem_master_m_arready - assign CAN_FIRE_imem_master_m_arready = 1'd1 ; - assign WILL_FIRE_imem_master_m_arready = 1'd1 ; + // value method imem_master_ar_arvalid + assign imem_master_arvalid = icache$mem_master_arvalid ; + + // action method imem_master_ar_arready + assign CAN_FIRE_imem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_imem_master_ar_arready = 1'd1 ; - // action method imem_master_m_rvalid - assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ; + // action method imem_master_r_rflit + assign CAN_FIRE_imem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_imem_master_r_rflit = imem_master_rvalid ; - // value method imem_master_m_rready + // value method imem_master_r_rready assign imem_master_rready = icache$mem_master_rready ; // action method dmem_req @@ -1123,108 +1157,108 @@ module mkNear_Mem(CLK, // value method dmem_exc_code assign dmem_exc_code = dcache$exc_code ; - // value method dmem_master_m_awvalid - assign dmem_master_awvalid = dcache$mem_master_awvalid ; - - // value method dmem_master_m_awid + // value method dmem_master_aw_awid assign dmem_master_awid = dcache$mem_master_awid ; - // value method dmem_master_m_awaddr + // value method dmem_master_aw_awaddr assign dmem_master_awaddr = dcache$mem_master_awaddr ; - // value method dmem_master_m_awlen + // value method dmem_master_aw_awlen assign dmem_master_awlen = dcache$mem_master_awlen ; - // value method dmem_master_m_awsize + // value method dmem_master_aw_awsize assign dmem_master_awsize = dcache$mem_master_awsize ; - // value method dmem_master_m_awburst + // value method dmem_master_aw_awburst assign dmem_master_awburst = dcache$mem_master_awburst ; - // value method dmem_master_m_awlock + // value method dmem_master_aw_awlock assign dmem_master_awlock = dcache$mem_master_awlock ; - // value method dmem_master_m_awcache + // value method dmem_master_aw_awcache assign dmem_master_awcache = dcache$mem_master_awcache ; - // value method dmem_master_m_awprot + // value method dmem_master_aw_awprot assign dmem_master_awprot = dcache$mem_master_awprot ; - // value method dmem_master_m_awqos + // value method dmem_master_aw_awqos assign dmem_master_awqos = dcache$mem_master_awqos ; - // value method dmem_master_m_awregion + // value method dmem_master_aw_awregion assign dmem_master_awregion = dcache$mem_master_awregion ; - // action method dmem_master_m_awready - assign CAN_FIRE_dmem_master_m_awready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_awready = 1'd1 ; + // value method dmem_master_aw_awvalid + assign dmem_master_awvalid = dcache$mem_master_awvalid ; - // value method dmem_master_m_wvalid - assign dmem_master_wvalid = dcache$mem_master_wvalid ; + // action method dmem_master_aw_awready + assign CAN_FIRE_dmem_master_aw_awready = 1'd1 ; + assign WILL_FIRE_dmem_master_aw_awready = 1'd1 ; - // value method dmem_master_m_wdata + // value method dmem_master_w_wdata assign dmem_master_wdata = dcache$mem_master_wdata ; - // value method dmem_master_m_wstrb + // value method dmem_master_w_wstrb assign dmem_master_wstrb = dcache$mem_master_wstrb ; - // value method dmem_master_m_wlast + // value method dmem_master_w_wlast assign dmem_master_wlast = dcache$mem_master_wlast ; - // action method dmem_master_m_wready - assign CAN_FIRE_dmem_master_m_wready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_wready = 1'd1 ; + // value method dmem_master_w_wvalid + assign dmem_master_wvalid = dcache$mem_master_wvalid ; + + // action method dmem_master_w_wready + assign CAN_FIRE_dmem_master_w_wready = 1'd1 ; + assign WILL_FIRE_dmem_master_w_wready = 1'd1 ; - // action method dmem_master_m_bvalid - assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ; + // action method dmem_master_b_bflit + assign CAN_FIRE_dmem_master_b_bflit = 1'd1 ; + assign WILL_FIRE_dmem_master_b_bflit = dmem_master_bvalid ; - // value method dmem_master_m_bready + // value method dmem_master_b_bready assign dmem_master_bready = dcache$mem_master_bready ; - // value method dmem_master_m_arvalid - assign dmem_master_arvalid = dcache$mem_master_arvalid ; - - // value method dmem_master_m_arid + // value method dmem_master_ar_arid assign dmem_master_arid = dcache$mem_master_arid ; - // value method dmem_master_m_araddr + // value method dmem_master_ar_araddr assign dmem_master_araddr = dcache$mem_master_araddr ; - // value method dmem_master_m_arlen + // value method dmem_master_ar_arlen assign dmem_master_arlen = dcache$mem_master_arlen ; - // value method dmem_master_m_arsize + // value method dmem_master_ar_arsize assign dmem_master_arsize = dcache$mem_master_arsize ; - // value method dmem_master_m_arburst + // value method dmem_master_ar_arburst assign dmem_master_arburst = dcache$mem_master_arburst ; - // value method dmem_master_m_arlock + // value method dmem_master_ar_arlock assign dmem_master_arlock = dcache$mem_master_arlock ; - // value method dmem_master_m_arcache + // value method dmem_master_ar_arcache assign dmem_master_arcache = dcache$mem_master_arcache ; - // value method dmem_master_m_arprot + // value method dmem_master_ar_arprot assign dmem_master_arprot = dcache$mem_master_arprot ; - // value method dmem_master_m_arqos + // value method dmem_master_ar_arqos assign dmem_master_arqos = dcache$mem_master_arqos ; - // value method dmem_master_m_arregion + // value method dmem_master_ar_arregion assign dmem_master_arregion = dcache$mem_master_arregion ; - // action method dmem_master_m_arready - assign CAN_FIRE_dmem_master_m_arready = 1'd1 ; - assign WILL_FIRE_dmem_master_m_arready = 1'd1 ; + // value method dmem_master_ar_arvalid + assign dmem_master_arvalid = dcache$mem_master_arvalid ; - // action method dmem_master_m_rvalid - assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ; - assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ; + // action method dmem_master_ar_arready + assign CAN_FIRE_dmem_master_ar_arready = 1'd1 ; + assign WILL_FIRE_dmem_master_ar_arready = 1'd1 ; - // value method dmem_master_m_rready + // action method dmem_master_r_rflit + assign CAN_FIRE_dmem_master_r_rflit = 1'd1 ; + assign WILL_FIRE_dmem_master_r_rflit = dmem_master_rvalid ; + + // value method dmem_master_r_rready assign dmem_master_rready = dcache$mem_master_rready ; // action method server_fence_i_request_put @@ -1266,76 +1300,76 @@ module mkNear_Mem(CLK, assign WILL_FIRE_sfence_vma = EN_sfence_vma ; // submodule dcache - mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(dcache$mem_master_arready), - .mem_master_awready(dcache$mem_master_awready), - .mem_master_bid(dcache$mem_master_bid), - .mem_master_bresp(dcache$mem_master_bresp), - .mem_master_bvalid(dcache$mem_master_bvalid), - .mem_master_rdata(dcache$mem_master_rdata), - .mem_master_rid(dcache$mem_master_rid), - .mem_master_rlast(dcache$mem_master_rlast), - .mem_master_rresp(dcache$mem_master_rresp), - .mem_master_rvalid(dcache$mem_master_rvalid), - .mem_master_wready(dcache$mem_master_wready), - .req_addr(dcache$req_addr), - .req_amo_funct7(dcache$req_amo_funct7), - .req_f3(dcache$req_f3), - .req_mstatus_MXR(dcache$req_mstatus_MXR), - .req_op(dcache$req_op), - .req_priv(dcache$req_priv), - .req_satp(dcache$req_satp), - .req_sstatus_SUM(dcache$req_sstatus_SUM), - .req_st_value(dcache$req_st_value), - .set_verbosity_verbosity(dcache$set_verbosity_verbosity), - .EN_set_verbosity(dcache$EN_set_verbosity), - .EN_server_reset_request_put(dcache$EN_server_reset_request_put), - .EN_server_reset_response_get(dcache$EN_server_reset_response_get), - .EN_req(dcache$EN_req), - .EN_server_flush_request_put(dcache$EN_server_flush_request_put), - .EN_server_flush_response_get(dcache$EN_server_flush_response_get), - .EN_tlb_flush(dcache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), - .valid(dcache$valid), - .addr(), - .word64(dcache$word64), - .st_amo_val(dcache$st_amo_val), - .exc(dcache$exc), - .exc_code(dcache$exc_code), - .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(dcache$mem_master_awvalid), - .mem_master_awid(dcache$mem_master_awid), - .mem_master_awaddr(dcache$mem_master_awaddr), - .mem_master_awlen(dcache$mem_master_awlen), - .mem_master_awsize(dcache$mem_master_awsize), - .mem_master_awburst(dcache$mem_master_awburst), - .mem_master_awlock(dcache$mem_master_awlock), - .mem_master_awcache(dcache$mem_master_awcache), - .mem_master_awprot(dcache$mem_master_awprot), - .mem_master_awqos(dcache$mem_master_awqos), - .mem_master_awregion(dcache$mem_master_awregion), - .mem_master_wvalid(dcache$mem_master_wvalid), - .mem_master_wdata(dcache$mem_master_wdata), - .mem_master_wstrb(dcache$mem_master_wstrb), - .mem_master_wlast(dcache$mem_master_wlast), - .mem_master_bready(dcache$mem_master_bready), - .mem_master_arvalid(dcache$mem_master_arvalid), - .mem_master_arid(dcache$mem_master_arid), - .mem_master_araddr(dcache$mem_master_araddr), - .mem_master_arlen(dcache$mem_master_arlen), - .mem_master_arsize(dcache$mem_master_arsize), - .mem_master_arburst(dcache$mem_master_arburst), - .mem_master_arlock(dcache$mem_master_arlock), - .mem_master_arcache(dcache$mem_master_arcache), - .mem_master_arprot(dcache$mem_master_arprot), - .mem_master_arqos(dcache$mem_master_arqos), - .mem_master_arregion(dcache$mem_master_arregion), - .mem_master_rready(dcache$mem_master_rready)); + mkMMU_DCache dcache(.CLK(CLK), + .RST_N(RST_N), + .mem_master_arready(dcache$mem_master_arready), + .mem_master_awready(dcache$mem_master_awready), + .mem_master_bid(dcache$mem_master_bid), + .mem_master_bresp(dcache$mem_master_bresp), + .mem_master_rdata(dcache$mem_master_rdata), + .mem_master_rid(dcache$mem_master_rid), + .mem_master_rlast(dcache$mem_master_rlast), + .mem_master_rresp(dcache$mem_master_rresp), + .mem_master_wready(dcache$mem_master_wready), + .req_addr(dcache$req_addr), + .req_amo_funct7(dcache$req_amo_funct7), + .req_f3(dcache$req_f3), + .req_mstatus_MXR(dcache$req_mstatus_MXR), + .req_op(dcache$req_op), + .req_priv(dcache$req_priv), + .req_satp(dcache$req_satp), + .req_sstatus_SUM(dcache$req_sstatus_SUM), + .req_st_value(dcache$req_st_value), + .set_verbosity_verbosity(dcache$set_verbosity_verbosity), + .EN_set_verbosity(dcache$EN_set_verbosity), + .EN_server_reset_request_put(dcache$EN_server_reset_request_put), + .EN_server_reset_response_get(dcache$EN_server_reset_response_get), + .EN_req(dcache$EN_req), + .EN_server_flush_request_put(dcache$EN_server_flush_request_put), + .EN_server_flush_response_get(dcache$EN_server_flush_response_get), + .EN_tlb_flush(dcache$EN_tlb_flush), + .mem_master_bvalid(dcache$mem_master_bvalid), + .mem_master_rvalid(dcache$mem_master_rvalid), + .RDY_set_verbosity(), + .RDY_server_reset_request_put(dcache$RDY_server_reset_request_put), + .RDY_server_reset_response_get(dcache$RDY_server_reset_response_get), + .valid(dcache$valid), + .addr(), + .word64(dcache$word64), + .st_amo_val(dcache$st_amo_val), + .exc(dcache$exc), + .exc_code(dcache$exc_code), + .RDY_server_flush_request_put(dcache$RDY_server_flush_request_put), + .RDY_server_flush_response_get(dcache$RDY_server_flush_response_get), + .RDY_tlb_flush(), + .mem_master_awid(dcache$mem_master_awid), + .mem_master_awaddr(dcache$mem_master_awaddr), + .mem_master_awlen(dcache$mem_master_awlen), + .mem_master_awsize(dcache$mem_master_awsize), + .mem_master_awburst(dcache$mem_master_awburst), + .mem_master_awlock(dcache$mem_master_awlock), + .mem_master_awcache(dcache$mem_master_awcache), + .mem_master_awprot(dcache$mem_master_awprot), + .mem_master_awqos(dcache$mem_master_awqos), + .mem_master_awregion(dcache$mem_master_awregion), + .mem_master_awvalid(dcache$mem_master_awvalid), + .mem_master_wdata(dcache$mem_master_wdata), + .mem_master_wstrb(dcache$mem_master_wstrb), + .mem_master_wlast(dcache$mem_master_wlast), + .mem_master_wvalid(dcache$mem_master_wvalid), + .mem_master_bready(dcache$mem_master_bready), + .mem_master_arid(dcache$mem_master_arid), + .mem_master_araddr(dcache$mem_master_araddr), + .mem_master_arlen(dcache$mem_master_arlen), + .mem_master_arsize(dcache$mem_master_arsize), + .mem_master_arburst(dcache$mem_master_arburst), + .mem_master_arlock(dcache$mem_master_arlock), + .mem_master_arcache(dcache$mem_master_arcache), + .mem_master_arprot(dcache$mem_master_arprot), + .mem_master_arqos(dcache$mem_master_arqos), + .mem_master_arregion(dcache$mem_master_arregion), + .mem_master_arvalid(dcache$mem_master_arvalid), + .mem_master_rready(dcache$mem_master_rready)); // submodule f_reset_rsps FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), @@ -1347,76 +1381,76 @@ module mkNear_Mem(CLK, .EMPTY_N(f_reset_rsps$EMPTY_N)); // submodule icache - mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK), - .RST_N(RST_N), - .mem_master_arready(icache$mem_master_arready), - .mem_master_awready(icache$mem_master_awready), - .mem_master_bid(icache$mem_master_bid), - .mem_master_bresp(icache$mem_master_bresp), - .mem_master_bvalid(icache$mem_master_bvalid), - .mem_master_rdata(icache$mem_master_rdata), - .mem_master_rid(icache$mem_master_rid), - .mem_master_rlast(icache$mem_master_rlast), - .mem_master_rresp(icache$mem_master_rresp), - .mem_master_rvalid(icache$mem_master_rvalid), - .mem_master_wready(icache$mem_master_wready), - .req_addr(icache$req_addr), - .req_amo_funct7(icache$req_amo_funct7), - .req_f3(icache$req_f3), - .req_mstatus_MXR(icache$req_mstatus_MXR), - .req_op(icache$req_op), - .req_priv(icache$req_priv), - .req_satp(icache$req_satp), - .req_sstatus_SUM(icache$req_sstatus_SUM), - .req_st_value(icache$req_st_value), - .set_verbosity_verbosity(icache$set_verbosity_verbosity), - .EN_set_verbosity(icache$EN_set_verbosity), - .EN_server_reset_request_put(icache$EN_server_reset_request_put), - .EN_server_reset_response_get(icache$EN_server_reset_response_get), - .EN_req(icache$EN_req), - .EN_server_flush_request_put(icache$EN_server_flush_request_put), - .EN_server_flush_response_get(icache$EN_server_flush_response_get), - .EN_tlb_flush(icache$EN_tlb_flush), - .RDY_set_verbosity(), - .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), - .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), - .valid(icache$valid), - .addr(icache$addr), - .word64(icache$word64), - .st_amo_val(), - .exc(icache$exc), - .exc_code(icache$exc_code), - .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), - .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), - .RDY_tlb_flush(), - .mem_master_awvalid(icache$mem_master_awvalid), - .mem_master_awid(icache$mem_master_awid), - .mem_master_awaddr(icache$mem_master_awaddr), - .mem_master_awlen(icache$mem_master_awlen), - .mem_master_awsize(icache$mem_master_awsize), - .mem_master_awburst(icache$mem_master_awburst), - .mem_master_awlock(icache$mem_master_awlock), - .mem_master_awcache(icache$mem_master_awcache), - .mem_master_awprot(icache$mem_master_awprot), - .mem_master_awqos(icache$mem_master_awqos), - .mem_master_awregion(icache$mem_master_awregion), - .mem_master_wvalid(icache$mem_master_wvalid), - .mem_master_wdata(icache$mem_master_wdata), - .mem_master_wstrb(icache$mem_master_wstrb), - .mem_master_wlast(icache$mem_master_wlast), - .mem_master_bready(icache$mem_master_bready), - .mem_master_arvalid(icache$mem_master_arvalid), - .mem_master_arid(icache$mem_master_arid), - .mem_master_araddr(icache$mem_master_araddr), - .mem_master_arlen(icache$mem_master_arlen), - .mem_master_arsize(icache$mem_master_arsize), - .mem_master_arburst(icache$mem_master_arburst), - .mem_master_arlock(icache$mem_master_arlock), - .mem_master_arcache(icache$mem_master_arcache), - .mem_master_arprot(icache$mem_master_arprot), - .mem_master_arqos(icache$mem_master_arqos), - .mem_master_arregion(icache$mem_master_arregion), - .mem_master_rready(icache$mem_master_rready)); + mkMMU_ICache icache(.CLK(CLK), + .RST_N(RST_N), + .mem_master_arready(icache$mem_master_arready), + .mem_master_awready(icache$mem_master_awready), + .mem_master_bid(icache$mem_master_bid), + .mem_master_bresp(icache$mem_master_bresp), + .mem_master_rdata(icache$mem_master_rdata), + .mem_master_rid(icache$mem_master_rid), + .mem_master_rlast(icache$mem_master_rlast), + .mem_master_rresp(icache$mem_master_rresp), + .mem_master_wready(icache$mem_master_wready), + .req_addr(icache$req_addr), + .req_amo_funct7(icache$req_amo_funct7), + .req_f3(icache$req_f3), + .req_mstatus_MXR(icache$req_mstatus_MXR), + .req_op(icache$req_op), + .req_priv(icache$req_priv), + .req_satp(icache$req_satp), + .req_sstatus_SUM(icache$req_sstatus_SUM), + .req_st_value(icache$req_st_value), + .set_verbosity_verbosity(icache$set_verbosity_verbosity), + .EN_set_verbosity(icache$EN_set_verbosity), + .EN_server_reset_request_put(icache$EN_server_reset_request_put), + .EN_server_reset_response_get(icache$EN_server_reset_response_get), + .EN_req(icache$EN_req), + .EN_server_flush_request_put(icache$EN_server_flush_request_put), + .EN_server_flush_response_get(icache$EN_server_flush_response_get), + .EN_tlb_flush(icache$EN_tlb_flush), + .mem_master_bvalid(icache$mem_master_bvalid), + .mem_master_rvalid(icache$mem_master_rvalid), + .RDY_set_verbosity(), + .RDY_server_reset_request_put(icache$RDY_server_reset_request_put), + .RDY_server_reset_response_get(icache$RDY_server_reset_response_get), + .valid(icache$valid), + .addr(icache$addr), + .word64(icache$word64), + .st_amo_val(), + .exc(icache$exc), + .exc_code(icache$exc_code), + .RDY_server_flush_request_put(icache$RDY_server_flush_request_put), + .RDY_server_flush_response_get(icache$RDY_server_flush_response_get), + .RDY_tlb_flush(), + .mem_master_awid(icache$mem_master_awid), + .mem_master_awaddr(icache$mem_master_awaddr), + .mem_master_awlen(icache$mem_master_awlen), + .mem_master_awsize(icache$mem_master_awsize), + .mem_master_awburst(icache$mem_master_awburst), + .mem_master_awlock(icache$mem_master_awlock), + .mem_master_awcache(icache$mem_master_awcache), + .mem_master_awprot(icache$mem_master_awprot), + .mem_master_awqos(icache$mem_master_awqos), + .mem_master_awregion(icache$mem_master_awregion), + .mem_master_awvalid(icache$mem_master_awvalid), + .mem_master_wdata(icache$mem_master_wdata), + .mem_master_wstrb(icache$mem_master_wstrb), + .mem_master_wlast(icache$mem_master_wlast), + .mem_master_wvalid(icache$mem_master_wvalid), + .mem_master_bready(icache$mem_master_bready), + .mem_master_arid(icache$mem_master_arid), + .mem_master_araddr(icache$mem_master_araddr), + .mem_master_arlen(icache$mem_master_arlen), + .mem_master_arsize(icache$mem_master_arsize), + .mem_master_arburst(icache$mem_master_arburst), + .mem_master_arlock(icache$mem_master_arlock), + .mem_master_arcache(icache$mem_master_arcache), + .mem_master_arprot(icache$mem_master_arprot), + .mem_master_arqos(icache$mem_master_arqos), + .mem_master_arregion(icache$mem_master_arregion), + .mem_master_arvalid(icache$mem_master_arvalid), + .mem_master_rready(icache$mem_master_rready)); // submodule soc_map mkSoC_Map soc_map(.CLK(CLK), @@ -1424,36 +1458,16 @@ module mkNear_Mem(CLK, .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr), .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr), .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr), - .m_plic_addr_base(), - .m_plic_addr_size(), - .m_plic_addr_lim(), - .m_near_mem_io_addr_base(), - .m_near_mem_io_addr_size(), - .m_near_mem_io_addr_lim(), - .m_flash_mem_addr_base(), - .m_flash_mem_addr_size(), - .m_flash_mem_addr_lim(), - .m_ethernet_0_addr_base(), - .m_ethernet_0_addr_size(), - .m_ethernet_0_addr_lim(), - .m_dma_0_addr_base(), - .m_dma_0_addr_size(), - .m_dma_0_addr_lim(), - .m_uart16550_0_addr_base(), - .m_uart16550_0_addr_size(), - .m_uart16550_0_addr_lim(), - .m_gpio_0_addr_base(), - .m_gpio_0_addr_size(), - .m_gpio_0_addr_lim(), - .m_boot_rom_addr_base(), - .m_boot_rom_addr_size(), - .m_boot_rom_addr_lim(), - .m_ddr4_0_uncached_addr_base(), - .m_ddr4_0_uncached_addr_size(), - .m_ddr4_0_uncached_addr_lim(), - .m_ddr4_0_cached_addr_base(), - .m_ddr4_0_cached_addr_size(), - .m_ddr4_0_cached_addr_lim(), + .m_plic_addr_range(), + .m_near_mem_io_addr_range(), + .m_flash_mem_addr_range(), + .m_ethernet_0_addr_range(), + .m_dma_0_addr_range(), + .m_uart16550_0_addr_range(), + .m_gpio_0_addr_range(), + .m_boot_rom_addr_range(), + .m_ddr4_0_uncached_addr_range(), + .m_ddr4_0_cached_addr_range(), .m_is_mem_addr(), .m_is_IO_addr(), .m_is_near_mem_IO_addr(), @@ -1466,15 +1480,16 @@ module mkNear_Mem(CLK, dcache$RDY_server_reset_request_put && icache$RDY_server_reset_request_put && rg_state == 2'd0 ; - assign WILL_FIRE_RL_rl_reset = - CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && - !EN_server_fence_i_request_put ; + assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; // rule RL_rl_reset_complete assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ; // inputs to muxes for submodule ports + assign MUX_rg_state$write_1__SEL_2 = + CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put && + !EN_server_fence_i_request_put ; assign MUX_rg_state$write_1__SEL_3 = dcache$RDY_server_reset_response_get && icache$RDY_server_reset_response_get && @@ -1505,12 +1520,10 @@ module mkNear_Mem(CLK, assign dcache$mem_master_awready = dmem_master_awready ; assign dcache$mem_master_bid = dmem_master_bid ; assign dcache$mem_master_bresp = dmem_master_bresp ; - assign dcache$mem_master_bvalid = dmem_master_bvalid ; assign dcache$mem_master_rdata = dmem_master_rdata ; assign dcache$mem_master_rid = dmem_master_rid ; assign dcache$mem_master_rlast = dmem_master_rlast ; assign dcache$mem_master_rresp = dmem_master_rresp ; - assign dcache$mem_master_rvalid = dmem_master_rvalid ; assign dcache$mem_master_wready = dmem_master_wready ; assign dcache$req_addr = dmem_req_addr ; assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ; @@ -1523,7 +1536,7 @@ module mkNear_Mem(CLK, assign dcache$req_st_value = dmem_req_store_value ; assign dcache$set_verbosity_verbosity = 4'h0 ; assign dcache$EN_set_verbosity = 1'b0 ; - assign dcache$EN_server_reset_request_put = WILL_FIRE_RL_rl_reset ; + assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; assign dcache$EN_req = EN_dmem_req ; assign dcache$EN_server_flush_request_put = @@ -1531,13 +1544,11 @@ module mkNear_Mem(CLK, assign dcache$EN_server_flush_response_get = EN_server_fence_i_response_get || EN_server_fence_response_get ; assign dcache$EN_tlb_flush = EN_sfence_vma ; + assign dcache$mem_master_bvalid = dmem_master_bvalid ; + assign dcache$mem_master_rvalid = dmem_master_rvalid ; // submodule f_reset_rsps - assign f_reset_rsps$ENQ = - dcache$RDY_server_reset_response_get && - icache$RDY_server_reset_response_get && - f_reset_rsps$FULL_N && - rg_state == 2'd1 ; + assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ; assign f_reset_rsps$DEQ = EN_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; @@ -1546,12 +1557,10 @@ module mkNear_Mem(CLK, assign icache$mem_master_awready = imem_master_awready ; assign icache$mem_master_bid = imem_master_bid ; assign icache$mem_master_bresp = imem_master_bresp ; - assign icache$mem_master_bvalid = imem_master_bvalid ; assign icache$mem_master_rdata = imem_master_rdata ; assign icache$mem_master_rid = imem_master_rid ; assign icache$mem_master_rlast = imem_master_rlast ; assign icache$mem_master_rresp = imem_master_rresp ; - assign icache$mem_master_rvalid = imem_master_rvalid ; assign icache$mem_master_wready = imem_master_wready ; assign icache$req_addr = imem_req_addr ; assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ; @@ -1564,13 +1573,15 @@ module mkNear_Mem(CLK, assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ; assign icache$set_verbosity_verbosity = 4'h0 ; assign icache$EN_set_verbosity = 1'b0 ; - assign icache$EN_server_reset_request_put = WILL_FIRE_RL_rl_reset ; + assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ; assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ; assign icache$EN_req = EN_imem_req ; assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ; assign icache$EN_server_flush_response_get = EN_server_fence_i_response_get ; assign icache$EN_tlb_flush = EN_sfence_vma ; + assign icache$mem_master_bvalid = imem_master_bvalid ; + assign icache$mem_master_rvalid = imem_master_rvalid ; // submodule soc_map assign soc_map$m_is_IO_addr_addr = 64'h0 ; @@ -1617,23 +1628,23 @@ module mkNear_Mem(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) begin - v__h1767 = $stime; + v__h1541 = $stime; #0; end - v__h1761 = v__h1767 / 32'd10; + v__h1535 = v__h1541 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset", v__h1761); + $display("%0d: Near_Mem.rl_reset", v__h1535); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) begin - v__h1918 = $stime; + v__h1692 = $stime; #0; end - v__h1912 = v__h1918 / 32'd10; + v__h1686 = v__h1692 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9) - $display("%0d: Near_Mem.rl_reset_complete", v__h1912); + $display("%0d: Near_Mem.rl_reset_complete", v__h1686); end // synopsys translate_on endmodule // mkNear_Mem diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem_IO.v b/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem_IO.v deleted file mode 100644 index cb2fdba3..00000000 --- a/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem_IO.v +++ /dev/null @@ -1,1304 +0,0 @@ -// -// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) -// -// -// -// -// Ports: -// Name I/O size props -// RDY_server_reset_request_put O 1 reg -// RDY_server_reset_response_get O 1 reg -// RDY_set_addr_map O 1 const -// RDY_server_request_put O 1 reg -// server_response_get O 66 reg -// RDY_server_response_get O 1 reg -// get_timer_interrupt_req_get O 1 reg -// RDY_get_timer_interrupt_req_get O 1 reg -// get_sw_interrupt_req_get O 1 reg -// RDY_get_sw_interrupt_req_get O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// set_addr_map_addr_base I 64 reg -// set_addr_map_addr_lim I 64 reg -// server_request_put I 137 reg -// EN_server_reset_request_put I 1 -// EN_server_reset_response_get I 1 -// EN_set_addr_map I 1 -// EN_server_request_put I 1 -// EN_server_response_get I 1 -// EN_get_timer_interrupt_req_get I 1 -// EN_get_sw_interrupt_req_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkNear_Mem_IO(CLK, - RST_N, - - EN_server_reset_request_put, - RDY_server_reset_request_put, - - EN_server_reset_response_get, - RDY_server_reset_response_get, - - set_addr_map_addr_base, - set_addr_map_addr_lim, - EN_set_addr_map, - RDY_set_addr_map, - - server_request_put, - EN_server_request_put, - RDY_server_request_put, - - EN_server_response_get, - server_response_get, - RDY_server_response_get, - - EN_get_timer_interrupt_req_get, - get_timer_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - - EN_get_sw_interrupt_req_get, - get_sw_interrupt_req_get, - RDY_get_sw_interrupt_req_get); - input CLK; - input RST_N; - - // action method server_reset_request_put - input EN_server_reset_request_put; - output RDY_server_reset_request_put; - - // action method server_reset_response_get - input EN_server_reset_response_get; - output RDY_server_reset_response_get; - - // action method set_addr_map - input [63 : 0] set_addr_map_addr_base; - input [63 : 0] set_addr_map_addr_lim; - input EN_set_addr_map; - output RDY_set_addr_map; - - // action method server_request_put - input [136 : 0] server_request_put; - input EN_server_request_put; - output RDY_server_request_put; - - // actionvalue method server_response_get - input EN_server_response_get; - output [65 : 0] server_response_get; - output RDY_server_response_get; - - // actionvalue method get_timer_interrupt_req_get - input EN_get_timer_interrupt_req_get; - output get_timer_interrupt_req_get; - output RDY_get_timer_interrupt_req_get; - - // actionvalue method get_sw_interrupt_req_get - input EN_get_sw_interrupt_req_get; - output get_sw_interrupt_req_get; - output RDY_get_sw_interrupt_req_get; - - // signals for module outputs - wire [65 : 0] server_response_get; - wire RDY_get_sw_interrupt_req_get, - RDY_get_timer_interrupt_req_get, - RDY_server_request_put, - RDY_server_reset_request_put, - RDY_server_reset_response_get, - RDY_server_response_get, - RDY_set_addr_map, - get_sw_interrupt_req_get, - get_timer_interrupt_req_get; - - // inlined wires - wire [63 : 0] crg_time$port0__write_1, - crg_time$port1__write_1, - crg_time$port2__read, - crg_timecmp$port1__write_1, - crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; - - // register cfg_verbosity - reg [3 : 0] cfg_verbosity; - wire [3 : 0] cfg_verbosity$D_IN; - wire cfg_verbosity$EN; - - // register crg_time - reg [63 : 0] crg_time; - wire [63 : 0] crg_time$D_IN; - wire crg_time$EN; - - // register crg_timecmp - reg [63 : 0] crg_timecmp; - wire [63 : 0] crg_timecmp$D_IN; - wire crg_timecmp$EN; - - // register rg_addr_base - reg [63 : 0] rg_addr_base; - wire [63 : 0] rg_addr_base$D_IN; - wire rg_addr_base$EN; - - // register rg_addr_lim - reg [63 : 0] rg_addr_lim; - wire [63 : 0] rg_addr_lim$D_IN; - wire rg_addr_lim$EN; - - // register rg_msip - reg rg_msip; - wire rg_msip$D_IN, rg_msip$EN; - - // register rg_mtip - reg rg_mtip; - wire rg_mtip$D_IN, rg_mtip$EN; - - // register rg_state - reg rg_state; - wire rg_state$D_IN, rg_state$EN; - - // ports of submodule f_reqs - wire [136 : 0] f_reqs$D_IN, f_reqs$D_OUT; - wire f_reqs$CLR, f_reqs$DEQ, f_reqs$EMPTY_N, f_reqs$ENQ, f_reqs$FULL_N; - - // ports of submodule f_reset_reqs - wire f_reset_reqs$CLR, - f_reset_reqs$DEQ, - f_reset_reqs$EMPTY_N, - f_reset_reqs$ENQ, - f_reset_reqs$FULL_N; - - // ports of submodule f_reset_rsps - wire f_reset_rsps$CLR, - f_reset_rsps$DEQ, - f_reset_rsps$EMPTY_N, - f_reset_rsps$ENQ, - f_reset_rsps$FULL_N; - - // ports of submodule f_rsps - wire [65 : 0] f_rsps$D_IN, f_rsps$D_OUT; - wire f_rsps$CLR, f_rsps$DEQ, f_rsps$EMPTY_N, f_rsps$ENQ, f_rsps$FULL_N; - - // ports of submodule f_sw_interrupt_req - wire f_sw_interrupt_req$CLR, - f_sw_interrupt_req$DEQ, - f_sw_interrupt_req$D_IN, - f_sw_interrupt_req$D_OUT, - f_sw_interrupt_req$EMPTY_N, - f_sw_interrupt_req$ENQ, - f_sw_interrupt_req$FULL_N; - - // ports of submodule f_timer_interrupt_req - wire f_timer_interrupt_req$CLR, - f_timer_interrupt_req$DEQ, - f_timer_interrupt_req$D_IN, - f_timer_interrupt_req$D_OUT, - f_timer_interrupt_req$EMPTY_N, - f_timer_interrupt_req$ENQ, - f_timer_interrupt_req$FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_rl_compare, - CAN_FIRE_RL_rl_process_rd_req, - CAN_FIRE_RL_rl_process_wr_req, - CAN_FIRE_RL_rl_reset, - CAN_FIRE_RL_rl_soft_reset, - CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_get_sw_interrupt_req_get, - CAN_FIRE_get_timer_interrupt_req_get, - CAN_FIRE_server_request_put, - CAN_FIRE_server_reset_request_put, - CAN_FIRE_server_reset_response_get, - CAN_FIRE_server_response_get, - CAN_FIRE_set_addr_map, - WILL_FIRE_RL_rl_compare, - WILL_FIRE_RL_rl_process_rd_req, - WILL_FIRE_RL_rl_process_wr_req, - WILL_FIRE_RL_rl_reset, - WILL_FIRE_RL_rl_soft_reset, - WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_get_sw_interrupt_req_get, - WILL_FIRE_get_timer_interrupt_req_get, - WILL_FIRE_server_request_put, - WILL_FIRE_server_reset_request_put, - WILL_FIRE_server_reset_response_get, - WILL_FIRE_server_response_get, - WILL_FIRE_set_addr_map; - - // inputs to muxes for submodule ports - wire [65 : 0] MUX_f_rsps$enq_1__VAL_1, MUX_f_rsps$enq_1__VAL_2; - wire [63 : 0] MUX_crg_time$port1__write_1__VAL_1, - MUX_crg_timecmp$port1__write_1__VAL_1; - wire MUX_crg_time$port1__write_1__SEL_1, - MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1, - MUX_rg_mtip$write_1__SEL_1, - MUX_rg_mtip$write_1__VAL_1, - MUX_rg_state$write_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [31 : 0] v__h8676; - reg [31 : 0] v__h8808; - reg [31 : 0] v__h1471; - reg [31 : 0] v__h1868; - reg [31 : 0] v__h2065; - reg [31 : 0] v__h1714; - reg [31 : 0] v__h2442; - reg [31 : 0] v__h7890; - reg [31 : 0] v__h8258; - reg [31 : 0] v__h8368; - reg [31 : 0] v__h8475; - reg [31 : 0] v__h1465; - reg [31 : 0] v__h1708; - reg [31 : 0] v__h1862; - reg [31 : 0] v__h2059; - reg [31 : 0] v__h2436; - reg [31 : 0] v__h7884; - reg [31 : 0] v__h8252; - reg [31 : 0] v__h8362; - reg [31 : 0] v__h8469; - reg [31 : 0] v__h8670; - reg [31 : 0] v__h8802; - // synopsys translate_on - - // remaining internal signals - reg [63 : 0] rsp_rdata__h2209; - wire [63 : 0] byte_addr__h1981, - mask__h2865, - mask__h5362, - new_data__h5360, - new_time__h4107, - new_time__h6632, - new_timecmp__h2834, - new_timecmp__h5331, - old_time__h6631, - rdata__h1996, - rdata__h2020, - rdata__h2026, - x__h2876, - x__h4149, - x__h5373, - x__h6674, - y__h2877, - y__h2878, - y__h5374, - y__h5375; - wire [7 : 0] SEXT_f_reqs_first__8_BIT_0_31___d132, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_7_07___d108; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89; - - // action method server_reset_request_put - assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; - assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ; - assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ; - - // action method server_reset_response_get - assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ; - assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ; - - // action method set_addr_map - assign RDY_set_addr_map = 1'd1 ; - assign CAN_FIRE_set_addr_map = 1'd1 ; - assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - - // action method server_request_put - assign RDY_server_request_put = f_reqs$FULL_N ; - assign CAN_FIRE_server_request_put = f_reqs$FULL_N ; - assign WILL_FIRE_server_request_put = EN_server_request_put ; - - // actionvalue method server_response_get - assign server_response_get = f_rsps$D_OUT ; - assign RDY_server_response_get = f_rsps$EMPTY_N ; - assign CAN_FIRE_server_response_get = f_rsps$EMPTY_N ; - assign WILL_FIRE_server_response_get = EN_server_response_get ; - - // actionvalue method get_timer_interrupt_req_get - assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; - assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_timer_interrupt_req_get = - f_timer_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_timer_interrupt_req_get = - EN_get_timer_interrupt_req_get ; - - // actionvalue method get_sw_interrupt_req_get - assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ; - assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ; - assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ; - - // submodule f_reqs - FIFO2 #(.width(32'd137), .guarded(32'd1)) f_reqs(.RST(RST_N), - .CLK(CLK), - .D_IN(f_reqs$D_IN), - .ENQ(f_reqs$ENQ), - .DEQ(f_reqs$DEQ), - .CLR(f_reqs$CLR), - .D_OUT(f_reqs$D_OUT), - .FULL_N(f_reqs$FULL_N), - .EMPTY_N(f_reqs$EMPTY_N)); - - // submodule f_reset_reqs - FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_reqs$ENQ), - .DEQ(f_reset_reqs$DEQ), - .CLR(f_reset_reqs$CLR), - .FULL_N(f_reset_reqs$FULL_N), - .EMPTY_N(f_reset_reqs$EMPTY_N)); - - // submodule f_reset_rsps - FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N), - .CLK(CLK), - .ENQ(f_reset_rsps$ENQ), - .DEQ(f_reset_rsps$DEQ), - .CLR(f_reset_rsps$CLR), - .FULL_N(f_reset_rsps$FULL_N), - .EMPTY_N(f_reset_rsps$EMPTY_N)); - - // submodule f_rsps - FIFO2 #(.width(32'd66), .guarded(32'd1)) f_rsps(.RST(RST_N), - .CLK(CLK), - .D_IN(f_rsps$D_IN), - .ENQ(f_rsps$ENQ), - .DEQ(f_rsps$DEQ), - .CLR(f_rsps$CLR), - .D_OUT(f_rsps$D_OUT), - .FULL_N(f_rsps$FULL_N), - .EMPTY_N(f_rsps$EMPTY_N)); - - // submodule f_sw_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_sw_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_sw_interrupt_req$D_IN), - .ENQ(f_sw_interrupt_req$ENQ), - .DEQ(f_sw_interrupt_req$DEQ), - .CLR(f_sw_interrupt_req$CLR), - .D_OUT(f_sw_interrupt_req$D_OUT), - .FULL_N(f_sw_interrupt_req$FULL_N), - .EMPTY_N(f_sw_interrupt_req$EMPTY_N)); - - // submodule f_timer_interrupt_req - FIFO2 #(.width(32'd1), .guarded(32'd1)) f_timer_interrupt_req(.RST(RST_N), - .CLK(CLK), - .D_IN(f_timer_interrupt_req$D_IN), - .ENQ(f_timer_interrupt_req$ENQ), - .DEQ(f_timer_interrupt_req$DEQ), - .CLR(f_timer_interrupt_req$CLR), - .D_OUT(f_timer_interrupt_req$D_OUT), - .FULL_N(f_timer_interrupt_req$FULL_N), - .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; - - // rule RL_rl_soft_reset - assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; - - // rule RL_rl_process_rd_req - assign CAN_FIRE_RL_rl_process_rd_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && rg_state && - !f_reset_reqs$EMPTY_N && - f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; - - // rule RL_rl_compare - assign CAN_FIRE_RL_rl_compare = MUX_rg_mtip$write_1__SEL_1 ; - assign WILL_FIRE_RL_rl_compare = MUX_rg_mtip$write_1__SEL_1 ; - - // rule RL_rl_tick_timer - assign CAN_FIRE_RL_rl_tick_timer = - rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF && - !f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ; - - // rule RL_rl_process_wr_req - assign CAN_FIRE_RL_rl_process_wr_req = - f_reqs$EMPTY_N && f_rsps$FULL_N && - (byte_addr__h1981 != 64'h0 || - rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - f_sw_interrupt_req$FULL_N) && - rg_state && - !f_reset_reqs$EMPTY_N && - !f_reqs$D_OUT[136] ; - assign WILL_FIRE_RL_rl_process_wr_req = - CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; - - // inputs to muxes for submodule ports - assign MUX_crg_time$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) ; - assign MUX_crg_timecmp$port1__write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) ; - assign MUX_rg_msip$write_1__SEL_1 = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 ; - assign MUX_rg_mtip$write_1__SEL_1 = - f_timer_interrupt_req$FULL_N && rg_state && - rg_mtip != MUX_rg_mtip$write_1__VAL_1 && - !f_reset_reqs$EMPTY_N ; - assign MUX_rg_state$write_1__SEL_1 = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; - assign MUX_crg_time$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h000000000000BFF8) ? - new_time__h4107 : - new_time__h6632 ; - assign MUX_crg_timecmp$port1__write_1__VAL_1 = - (byte_addr__h1981 == 64'h0000000000004000) ? - new_timecmp__h2834 : - new_timecmp__h5331 ; - assign MUX_f_rsps$enq_1__VAL_1 = - { 1'd1, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - rsp_rdata__h2209 } ; - assign MUX_f_rsps$enq_1__VAL_2 = - { 1'd0, - byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC, - 64'hAAAAAAAAAAAAAAAA } ; - assign MUX_rg_mtip$write_1__VAL_1 = crg_time >= crg_timecmp ; - - // inlined wires - assign crg_time$port0__write_1 = crg_time + 64'd1 ; - assign crg_time$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h000000000000BFFC) || - WILL_FIRE_RL_rl_reset ; - assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? - MUX_crg_time$port1__write_1__VAL_1 : - 64'd1 ; - assign crg_time$port2__read = - crg_time$EN_port1__write ? - crg_time$port1__write_1 : - old_time__h6631 ; - assign crg_timecmp$EN_port1__write = - WILL_FIRE_RL_rl_process_wr_req && - (byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h0000000000004004) || - WILL_FIRE_RL_rl_reset ; - assign crg_timecmp$port1__write_1 = - MUX_crg_timecmp$port1__write_1__SEL_1 ? - MUX_crg_timecmp$port1__write_1__VAL_1 : - 64'd0 ; - assign crg_timecmp$port2__read = - crg_timecmp$EN_port1__write ? - crg_timecmp$port1__write_1 : - crg_timecmp ; - - // register cfg_verbosity - assign cfg_verbosity$D_IN = 4'h0 ; - assign cfg_verbosity$EN = 1'b0 ; - - // register crg_time - assign crg_time$D_IN = crg_time$port2__read ; - assign crg_time$EN = 1'b1 ; - - // register crg_timecmp - assign crg_timecmp$D_IN = crg_timecmp$port2__read ; - assign crg_timecmp$EN = 1'b1 ; - - // register rg_addr_base - assign rg_addr_base$D_IN = set_addr_map_addr_base ; - assign rg_addr_base$EN = EN_set_addr_map ; - - // register rg_addr_lim - assign rg_addr_lim$D_IN = set_addr_map_addr_lim ; - assign rg_addr_lim$EN = EN_set_addr_map ; - - // register rg_msip - assign rg_msip$D_IN = MUX_rg_msip$write_1__SEL_1 && f_reqs$D_OUT[8] ; - assign rg_msip$EN = - WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 || - WILL_FIRE_RL_rl_reset ; - - // register rg_mtip - assign rg_mtip$D_IN = - !WILL_FIRE_RL_rl_compare || MUX_rg_mtip$write_1__VAL_1 ; - assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; - - // register rg_state - assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; - assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; - - // submodule f_reqs - assign f_reqs$D_IN = server_request_put ; - assign f_reqs$ENQ = EN_server_request_put ; - assign f_reqs$DEQ = - WILL_FIRE_RL_rl_process_wr_req || - WILL_FIRE_RL_rl_process_rd_req ; - assign f_reqs$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule f_reset_reqs - assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; - assign f_reset_reqs$CLR = 1'b0 ; - - // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; - assign f_reset_rsps$DEQ = EN_server_reset_response_get ; - assign f_reset_rsps$CLR = 1'b0 ; - - // submodule f_rsps - assign f_rsps$D_IN = - WILL_FIRE_RL_rl_process_rd_req ? - MUX_f_rsps$enq_1__VAL_1 : - MUX_f_rsps$enq_1__VAL_2 ; - assign f_rsps$ENQ = - WILL_FIRE_RL_rl_process_rd_req || - WILL_FIRE_RL_rl_process_wr_req ; - assign f_rsps$DEQ = EN_server_response_get ; - assign f_rsps$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = f_reqs$D_OUT[8] ; - assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; - assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule f_timer_interrupt_req - assign f_timer_interrupt_req$D_IN = MUX_rg_mtip$write_1__VAL_1 ; - assign f_timer_interrupt_req$ENQ = MUX_rg_mtip$write_1__SEL_1 ; - assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = CAN_FIRE_RL_rl_reset ; - - // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign SEXT_f_reqs_first__8_BIT_0_31___d132 = {8{f_reqs$D_OUT[0]}} ; - assign SEXT_f_reqs_first__8_BIT_1_28___d129 = {8{f_reqs$D_OUT[1]}} ; - assign SEXT_f_reqs_first__8_BIT_2_24___d125 = {8{f_reqs$D_OUT[2]}} ; - assign SEXT_f_reqs_first__8_BIT_3_21___d122 = {8{f_reqs$D_OUT[3]}} ; - assign SEXT_f_reqs_first__8_BIT_4_17___d118 = {8{f_reqs$D_OUT[4]}} ; - assign SEXT_f_reqs_first__8_BIT_5_14___d115 = {8{f_reqs$D_OUT[5]}} ; - assign SEXT_f_reqs_first__8_BIT_6_10___d111 = {8{f_reqs$D_OUT[6]}} ; - assign SEXT_f_reqs_first__8_BIT_7_07___d108 = {8{f_reqs$D_OUT[7]}} ; - assign byte_addr__h1981 = f_reqs$D_OUT[135:72] - rg_addr_base ; - assign mask__h2865 = - { SEXT_f_reqs_first__8_BIT_7_07___d108, - SEXT_f_reqs_first__8_BIT_6_10___d111, - SEXT_f_reqs_first__8_BIT_5_14___d115, - SEXT_f_reqs_first__8_BIT_4_17___d118, - SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign mask__h5362 = - { SEXT_f_reqs_first__8_BIT_3_21___d122, - SEXT_f_reqs_first__8_BIT_2_24___d125, - SEXT_f_reqs_first__8_BIT_1_28___d129, - SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'd0 } ; - assign new_data__h5360 = { f_reqs$D_OUT[39:8], 32'h0 } ; - assign new_time__h4107 = x__h4149 | y__h2877 ; - assign new_time__h6632 = x__h6674 | y__h5374 ; - assign new_timecmp__h2834 = x__h2876 | y__h2877 ; - assign new_timecmp__h5331 = x__h5373 | y__h5374 ; - assign old_time__h6631 = - CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata__h1996 = { 63'd0, rg_msip } ; - assign rdata__h2020 = { 32'd0, crg_timecmp[63:32] } ; - assign rdata__h2026 = { 32'd0, crg_time[63:32] } ; - assign rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 = - rg_msip == f_reqs$D_OUT[8] ; - assign x__h2876 = crg_timecmp & y__h2878 ; - assign x__h4149 = old_time__h6631 & y__h2878 ; - assign x__h5373 = crg_timecmp & y__h5375 ; - assign x__h6674 = old_time__h6631 & y__h5375 ; - assign y__h2877 = f_reqs$D_OUT[71:8] & mask__h2865 ; - assign y__h2878 = - { ~SEXT_f_reqs_first__8_BIT_7_07___d108, - ~SEXT_f_reqs_first__8_BIT_6_10___d111, - ~SEXT_f_reqs_first__8_BIT_5_14___d115, - ~SEXT_f_reqs_first__8_BIT_4_17___d118, - ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132 } ; - assign y__h5374 = new_data__h5360 & mask__h5362 ; - assign y__h5375 = - { ~SEXT_f_reqs_first__8_BIT_3_21___d122, - ~SEXT_f_reqs_first__8_BIT_2_24___d125, - ~SEXT_f_reqs_first__8_BIT_1_28___d129, - ~SEXT_f_reqs_first__8_BIT_0_31___d132, - 32'hFFFFFFFF } ; - always@(byte_addr__h1981 or - rdata__h1996 or - crg_timecmp or rdata__h2020 or crg_time or rdata__h2026) - begin - case (byte_addr__h1981) - 64'h0: rsp_rdata__h2209 = rdata__h1996; - 64'h0000000000000004: rsp_rdata__h2209 = 64'd0; - 64'h0000000000004000: rsp_rdata__h2209 = crg_timecmp; - 64'h0000000000004004: rsp_rdata__h2209 = rdata__h2020; - 64'h000000000000BFF8: rsp_rdata__h2209 = crg_time; - 64'h000000000000BFFC: rsp_rdata__h2209 = rdata__h2026; - default: rsp_rdata__h2209 = 64'd0; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd1; - crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1; - crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; - rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; - rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (cfg_verbosity$EN) - cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN; - if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN; - if (crg_timecmp$EN) - crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; - if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; - if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; - end - if (rg_addr_base$EN) - rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; - if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN; - if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cfg_verbosity = 4'hA; - crg_time = 64'hAAAAAAAAAAAAAAAA; - crg_timecmp = 64'hAAAAAAAAAAAAAAAA; - rg_addr_base = 64'hAAAAAAAAAAAAAAAA; - rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; - rg_msip = 1'h0; - rg_mtip = 1'h0; - rg_state = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8676 = $stime; - #0; - end - v__h8670 = v__h8676 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_timer_interrupt_req: %x", - v__h8670, - f_timer_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h8808 = $stime; - #0; - end - v__h8802 = v__h8808 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO: get_sw_interrupt_req: %x", - v__h8802, - f_sw_interrupt_req$D_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - begin - v__h1471 = $stime; - #0; - end - v__h1465 = v__h1471 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO.rl_reset", v__h1465); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1868 = $stime; - #0; - end - v__h1862 = v__h1868 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_rd_req: rg_mtip = %0d", - v__h1862, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h2065 = $stime; - #0; - end - v__h2059 = v__h2065 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_rd_req: unrecognized addr", - v__h2059); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rsp_rdata__h2209, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h1714 = $stime; - #0; - end - v__h1708 = v__h1714 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h1708, - MUX_rg_mtip$write_1__VAL_1, - crg_time, - crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - begin - v__h2442 = $stime; - #0; - end - v__h2436 = v__h2442 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.rl_process_wr_req: rg_mtip = %0d", - v__h2436, - rg_mtip); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 == 64'h0 && - !rg_msip_3_EQ_f_reqs_first__8_BIT_8_8___d89 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", f_reqs$D_OUT[8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h2834); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h2834 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h4107); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIMECMP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIMECMP = 0x%0h", crg_timecmp); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h5331); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP - MTIME = 0x%0h", - new_timecmp__h5331 - old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" Writing MTIME"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h6631); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - byte_addr__h1981 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h6632); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - begin - v__h7890 = $stime; - #0; - end - v__h7884 = v__h7890 / 32'd10; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $display("%0d: ERROR: Near_Mem_IO.rl_process_wr_req: unrecognized addr", - v__h7884); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(" "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("Near_Mem_IO_Req { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "addr: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[135:72]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[71:8]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write(", ", "wstrb: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("'h%h", f_reqs$D_OUT[7:0], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(" <= "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("Near_Mem_IO_Rsp { ", "read_not_write: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "ok: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - byte_addr__h1981 != 64'h0 && - byte_addr__h1981 != 64'h0000000000004000 && - byte_addr__h1981 != 64'h000000000000BFF8 && - byte_addr__h1981 != 64'h0000000000000004 && - byte_addr__h1981 != 64'h0000000000004004 && - byte_addr__h1981 != 64'h000000000000BFFC) - $write("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - (byte_addr__h1981 == 64'h0 || - byte_addr__h1981 == 64'h0000000000004000 || - byte_addr__h1981 == 64'h000000000000BFF8 || - byte_addr__h1981 == 64'h0000000000000004 || - byte_addr__h1981 == 64'h0000000000004004 || - byte_addr__h1981 == 64'h000000000000BFFC)) - $write("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write(", ", "rdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", 64'hAAAAAAAAAAAAAAAA, " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("\n"); - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - begin - v__h8258 = $stime; - #0; - end - v__h8252 = v__h8258 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h8252, - set_addr_map_addr_base); - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - begin - v__h8368 = $stime; - #0; - end - v__h8362 = v__h8368 / 32'd10; - if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) - $display("%0d: WARNING: Near_Mem_IO.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h8362, - set_addr_map_addr_lim); - if (EN_set_addr_map) - begin - v__h8475 = $stime; - #0; - end - v__h8469 = v__h8475 / 32'd10; - if (EN_set_addr_map) - $display("%0d: Near_Mem_IO.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h8469, - set_addr_map_addr_base, - set_addr_map_addr_lim); - end - // synopsys translate_on -endmodule // mkNear_Mem_IO - diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem_IO_AXI4.v b/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem_IO_AXI4.v index 44c76846..b7b0d0be 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem_IO_AXI4.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkNear_Mem_IO_AXI4.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:23 BST 2019 // // // Ports: @@ -9,17 +9,17 @@ // RDY_server_reset_request_put O 1 reg // RDY_server_reset_response_get O 1 reg // RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg +// axi4_slave_awready O 1 +// axi4_slave_wready O 1 +// axi4_slave_bid O 5 +// axi4_slave_bresp O 2 +// axi4_slave_bvalid O 1 +// axi4_slave_arready O 1 +// axi4_slave_rid O 5 +// axi4_slave_rdata O 64 +// axi4_slave_rresp O 2 +// axi4_slave_rlast O 1 +// axi4_slave_rvalid O 1 // get_timer_interrupt_req_get O 1 reg // RDY_get_timer_interrupt_req_get O 1 reg // get_sw_interrupt_req_get O 1 reg @@ -28,41 +28,167 @@ // RST_N I 1 reset // set_addr_map_addr_base I 64 reg // set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg +// axi4_slave_awid I 5 +// axi4_slave_awaddr I 64 +// axi4_slave_awlen I 8 +// axi4_slave_awsize I 3 +// axi4_slave_awburst I 2 +// axi4_slave_awlock I 1 +// axi4_slave_awcache I 4 +// axi4_slave_awprot I 3 +// axi4_slave_awqos I 4 +// axi4_slave_awregion I 4 +// axi4_slave_wdata I 64 +// axi4_slave_wstrb I 8 +// axi4_slave_wlast I 1 // axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg +// axi4_slave_arid I 5 +// axi4_slave_araddr I 64 +// axi4_slave_arlen I 8 +// axi4_slave_arsize I 3 +// axi4_slave_arburst I 2 +// axi4_slave_arlock I 1 +// axi4_slave_arcache I 4 +// axi4_slave_arprot I 3 +// axi4_slave_arqos I 4 +// axi4_slave_arregion I 4 // axi4_slave_rready I 1 // EN_server_reset_request_put I 1 // EN_server_reset_response_get I 1 // EN_set_addr_map I 1 +// axi4_slave_awvalid I 1 +// axi4_slave_wvalid I 1 +// axi4_slave_arvalid I 1 // EN_get_timer_interrupt_req_get I 1 // EN_get_sw_interrupt_req_get I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_awvalid, +// axi4_slave_wvalid) -> axi4_slave_bid +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_awvalid, +// axi4_slave_wvalid) -> axi4_slave_bresp +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_awvalid, +// axi4_slave_wvalid) -> axi4_slave_buser +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_awvalid, +// axi4_slave_wvalid) -> axi4_slave_bvalid +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rid +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rdata +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rresp +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rlast +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_ruser +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rvalid // // @@ -93,7 +219,6 @@ module mkNear_Mem_IO_AXI4(CLK, EN_set_addr_map, RDY_set_addr_map, - axi4_slave_awvalid, axi4_slave_awid, axi4_slave_awaddr, axi4_slave_awlen, @@ -104,25 +229,25 @@ module mkNear_Mem_IO_AXI4(CLK, axi4_slave_awprot, axi4_slave_awqos, axi4_slave_awregion, + axi4_slave_awvalid, axi4_slave_awready, - axi4_slave_wvalid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, + axi4_slave_wvalid, axi4_slave_wready, - axi4_slave_bvalid, - axi4_slave_bid, axi4_slave_bresp, + axi4_slave_bvalid, + axi4_slave_bready, - axi4_slave_arvalid, axi4_slave_arid, axi4_slave_araddr, axi4_slave_arlen, @@ -133,11 +258,10 @@ module mkNear_Mem_IO_AXI4(CLK, axi4_slave_arprot, axi4_slave_arqos, axi4_slave_arregion, + axi4_slave_arvalid, axi4_slave_arready, - axi4_slave_rvalid, - axi4_slave_rid, axi4_slave_rdata, @@ -146,6 +270,8 @@ module mkNear_Mem_IO_AXI4(CLK, axi4_slave_rlast, + axi4_slave_rvalid, + axi4_slave_rready, EN_get_timer_interrupt_req_get, @@ -172,9 +298,8 @@ module mkNear_Mem_IO_AXI4(CLK, input EN_set_addr_map; output RDY_set_addr_map; - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; + // action method axi4_slave_aw_awflit + input [4 : 0] axi4_slave_awid; input [63 : 0] axi4_slave_awaddr; input [7 : 0] axi4_slave_awlen; input [2 : 0] axi4_slave_awsize; @@ -184,36 +309,36 @@ module mkNear_Mem_IO_AXI4(CLK, input [2 : 0] axi4_slave_awprot; input [3 : 0] axi4_slave_awqos; input [3 : 0] axi4_slave_awregion; + input axi4_slave_awvalid; - // value method axi4_slave_m_awready + // value method axi4_slave_aw_awready output axi4_slave_awready; - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; + // action method axi4_slave_w_wflit input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; + input axi4_slave_wvalid; - // value method axi4_slave_m_wready + // value method axi4_slave_w_wready output axi4_slave_wready; - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; + // value method axi4_slave_b_bid + output [4 : 0] axi4_slave_bid; - // value method axi4_slave_m_bresp + // value method axi4_slave_b_bresp output [1 : 0] axi4_slave_bresp; - // value method axi4_slave_m_buser + // value method axi4_slave_b_buser + + // value method axi4_slave_b_bvalid + output axi4_slave_bvalid; - // action method axi4_slave_m_bready + // action method axi4_slave_b_bready input axi4_slave_bready; - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; + // action method axi4_slave_ar_arflit + input [4 : 0] axi4_slave_arid; input [63 : 0] axi4_slave_araddr; input [7 : 0] axi4_slave_arlen; input [2 : 0] axi4_slave_arsize; @@ -223,28 +348,29 @@ module mkNear_Mem_IO_AXI4(CLK, input [2 : 0] axi4_slave_arprot; input [3 : 0] axi4_slave_arqos; input [3 : 0] axi4_slave_arregion; + input axi4_slave_arvalid; - // value method axi4_slave_m_arready + // value method axi4_slave_ar_arready output axi4_slave_arready; - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; + // value method axi4_slave_r_rid + output [4 : 0] axi4_slave_rid; - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; - - // value method axi4_slave_m_rdata + // value method axi4_slave_r_rdata output [63 : 0] axi4_slave_rdata; - // value method axi4_slave_m_rresp + // value method axi4_slave_r_rresp output [1 : 0] axi4_slave_rresp; - // value method axi4_slave_m_rlast + // value method axi4_slave_r_rlast output axi4_slave_rlast; - // value method axi4_slave_m_ruser + // value method axi4_slave_r_ruser + + // value method axi4_slave_r_rvalid + output axi4_slave_rvalid; - // action method axi4_slave_m_rready + // action method axi4_slave_r_rready input axi4_slave_rready; // actionvalue method get_timer_interrupt_req_get @@ -259,7 +385,7 @@ module mkNear_Mem_IO_AXI4(CLK, // signals for module outputs wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; + wire [4 : 0] axi4_slave_bid, axi4_slave_rid; wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; wire RDY_get_sw_interrupt_req_get, RDY_get_timer_interrupt_req_get, @@ -276,12 +402,41 @@ module mkNear_Mem_IO_AXI4(CLK, get_timer_interrupt_req_get; // inlined wires + wire [98 : 0] slave_xactor_shim_arff_rv$port0__write_1, + slave_xactor_shim_arff_rv$port1__read, + slave_xactor_shim_arff_rv$port2__read, + slave_xactor_shim_arff_rv$port3__read, + slave_xactor_shim_awff_rv$port0__write_1, + slave_xactor_shim_awff_rv$port1__read, + slave_xactor_shim_awff_rv$port2__read, + slave_xactor_shim_awff_rv$port3__read; + wire [97 : 0] slave_xactor_ug_slave_u_ar_putWire$wget, + slave_xactor_ug_slave_u_aw_putWire$wget; + wire [73 : 0] slave_xactor_shim_wff_rv$port0__write_1, + slave_xactor_shim_wff_rv$port1__read, + slave_xactor_shim_wff_rv$port2__read, + slave_xactor_shim_wff_rv$port3__read; + wire [72 : 0] slave_xactor_shim_rff_rv$port0__write_1, + slave_xactor_shim_rff_rv$port1__read, + slave_xactor_shim_rff_rv$port2__read, + slave_xactor_shim_rff_rv$port3__read, + slave_xactor_ug_slave_u_w_putWire$wget; wire [63 : 0] crg_time$port0__write_1, crg_time$port1__write_1, crg_time$port2__read, crg_timecmp$port1__write_1, crg_timecmp$port2__read; - wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write; + wire [7 : 0] slave_xactor_shim_bff_rv$port0__write_1, + slave_xactor_shim_bff_rv$port1__read, + slave_xactor_shim_bff_rv$port2__read, + slave_xactor_shim_bff_rv$port3__read; + wire crg_time$EN_port1__write, + crg_timecmp$EN_port1__write, + slave_xactor_ug_slave_u_ar_putWire$whas, + slave_xactor_ug_slave_u_aw_putWire$whas, + slave_xactor_ug_slave_u_b_dropWire$whas, + slave_xactor_ug_slave_u_r_dropWire$whas, + slave_xactor_ug_slave_u_w_putWire$whas; // register cfg_verbosity reg [3 : 0] cfg_verbosity; @@ -320,6 +475,35 @@ module mkNear_Mem_IO_AXI4(CLK, reg rg_state; wire rg_state$D_IN, rg_state$EN; + // register slave_xactor_clearing + reg slave_xactor_clearing; + wire slave_xactor_clearing$D_IN, slave_xactor_clearing$EN; + + // register slave_xactor_shim_arff_rv + reg [98 : 0] slave_xactor_shim_arff_rv; + wire [98 : 0] slave_xactor_shim_arff_rv$D_IN; + wire slave_xactor_shim_arff_rv$EN; + + // register slave_xactor_shim_awff_rv + reg [98 : 0] slave_xactor_shim_awff_rv; + wire [98 : 0] slave_xactor_shim_awff_rv$D_IN; + wire slave_xactor_shim_awff_rv$EN; + + // register slave_xactor_shim_bff_rv + reg [7 : 0] slave_xactor_shim_bff_rv; + wire [7 : 0] slave_xactor_shim_bff_rv$D_IN; + wire slave_xactor_shim_bff_rv$EN; + + // register slave_xactor_shim_rff_rv + reg [72 : 0] slave_xactor_shim_rff_rv; + wire [72 : 0] slave_xactor_shim_rff_rv$D_IN; + wire slave_xactor_shim_rff_rv$EN; + + // register slave_xactor_shim_wff_rv + reg [73 : 0] slave_xactor_shim_wff_rv; + wire [73 : 0] slave_xactor_shim_wff_rv$D_IN; + wire slave_xactor_shim_wff_rv$EN; + // ports of submodule f_reset_reqs wire f_reset_reqs$CLR, f_reset_reqs$DEQ, @@ -352,46 +536,6 @@ module mkNear_Mem_IO_AXI4(CLK, f_timer_interrupt_req$ENQ, f_timer_interrupt_req$FULL_N; - // ports of submodule slave_xactor_f_rd_addr - wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT; - wire slave_xactor_f_rd_addr$CLR, - slave_xactor_f_rd_addr$DEQ, - slave_xactor_f_rd_addr$EMPTY_N, - slave_xactor_f_rd_addr$ENQ, - slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule slave_xactor_f_rd_data - wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT; - wire slave_xactor_f_rd_data$CLR, - slave_xactor_f_rd_data$DEQ, - slave_xactor_f_rd_data$EMPTY_N, - slave_xactor_f_rd_data$ENQ, - slave_xactor_f_rd_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_addr - wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT; - wire slave_xactor_f_wr_addr$CLR, - slave_xactor_f_wr_addr$DEQ, - slave_xactor_f_wr_addr$EMPTY_N, - slave_xactor_f_wr_addr$ENQ, - slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule slave_xactor_f_wr_data - wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT; - wire slave_xactor_f_wr_data$CLR, - slave_xactor_f_wr_data$DEQ, - slave_xactor_f_wr_data$EMPTY_N, - slave_xactor_f_wr_data$ENQ, - slave_xactor_f_wr_data$FULL_N; - - // ports of submodule slave_xactor_f_wr_resp - wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT; - wire slave_xactor_f_wr_resp$CLR, - slave_xactor_f_wr_resp$DEQ, - slave_xactor_f_wr_resp$EMPTY_N, - slave_xactor_f_wr_resp$ENQ, - slave_xactor_f_wr_resp$FULL_N; - // rule scheduling signals wire CAN_FIRE_RL_rl_compare, CAN_FIRE_RL_rl_process_rd_req, @@ -399,11 +543,24 @@ module mkNear_Mem_IO_AXI4(CLK, CAN_FIRE_RL_rl_reset, CAN_FIRE_RL_rl_soft_reset, CAN_FIRE_RL_rl_tick_timer, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, + CAN_FIRE_RL_slave_xactor_do_clear, + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek, + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek, + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop, + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut, + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_axi4_slave_ar_arflit, + CAN_FIRE_axi4_slave_aw_awflit, + CAN_FIRE_axi4_slave_b_bready, + CAN_FIRE_axi4_slave_r_rready, + CAN_FIRE_axi4_slave_w_wflit, CAN_FIRE_get_sw_interrupt_req_get, CAN_FIRE_get_timer_interrupt_req_get, CAN_FIRE_server_reset_request_put, @@ -415,11 +572,24 @@ module mkNear_Mem_IO_AXI4(CLK, WILL_FIRE_RL_rl_reset, WILL_FIRE_RL_rl_soft_reset, WILL_FIRE_RL_rl_tick_timer, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, + WILL_FIRE_RL_slave_xactor_do_clear, + WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek, + WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek, + WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop, + WILL_FIRE_RL_slave_xactor_ug_slave_u_w_doPut, + WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_axi4_slave_ar_arflit, + WILL_FIRE_axi4_slave_aw_awflit, + WILL_FIRE_axi4_slave_b_bready, + WILL_FIRE_axi4_slave_r_rready, + WILL_FIRE_axi4_slave_w_wflit, WILL_FIRE_get_sw_interrupt_req_get, WILL_FIRE_get_timer_interrupt_req_get, WILL_FIRE_server_reset_request_put, @@ -429,73 +599,80 @@ module mkNear_Mem_IO_AXI4(CLK, // inputs to muxes for submodule ports wire MUX_crg_time$port1__write_1__SEL_1, MUX_crg_timecmp$port1__write_1__SEL_1, - MUX_rg_msip$write_1__SEL_1; + MUX_rg_msip$write_1__SEL_1, + MUX_rg_state$write_1__SEL_1, + MUX_rg_state$write_1__SEL_2; // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h10050; - reg [31 : 0] v__h10182; - reg [31 : 0] v__h1852; - reg [31 : 0] v__h2269; - reg [31 : 0] v__h2453; - reg [31 : 0] v__h2640; - reg [31 : 0] v__h2878; - reg [31 : 0] v__h2095; - reg [31 : 0] v__h3158; - reg [31 : 0] v__h3384; - reg [31 : 0] v__h8918; - reg [31 : 0] v__h9137; - reg [31 : 0] v__h9462; - reg [31 : 0] v__h9572; - reg [31 : 0] v__h9679; - reg [31 : 0] v__h1846; - reg [31 : 0] v__h2089; - reg [31 : 0] v__h2263; - reg [31 : 0] v__h2447; - reg [31 : 0] v__h2634; - reg [31 : 0] v__h2872; - reg [31 : 0] v__h3152; - reg [31 : 0] v__h3378; - reg [31 : 0] v__h8912; - reg [31 : 0] v__h9131; - reg [31 : 0] v__h9456; - reg [31 : 0] v__h9566; - reg [31 : 0] v__h9673; - reg [31 : 0] v__h10044; - reg [31 : 0] v__h10176; + reg [31 : 0] v__h13099; + reg [31 : 0] v__h13231; + reg [31 : 0] v__h4164; + reg [31 : 0] v__h4672; + reg [31 : 0] v__h4886; + reg [31 : 0] v__h5109; + reg [31 : 0] v__h5435; + reg [31 : 0] v__h4408; + reg [31 : 0] v__h5925; + reg [31 : 0] v__h6181; + reg [31 : 0] v__h11750; + reg [31 : 0] v__h12059; + reg [31 : 0] v__h12451; + reg [31 : 0] v__h12561; + reg [31 : 0] v__h12668; + reg [31 : 0] v__h4158; + reg [31 : 0] v__h4402; + reg [31 : 0] v__h4666; + reg [31 : 0] v__h4880; + reg [31 : 0] v__h5103; + reg [31 : 0] v__h5429; + reg [31 : 0] v__h5919; + reg [31 : 0] v__h6175; + reg [31 : 0] v__h11744; + reg [31 : 0] v__h12053; + reg [31 : 0] v__h12445; + reg [31 : 0] v__h12555; + reg [31 : 0] v__h12662; + reg [31 : 0] v__h13093; + reg [31 : 0] v__h13225; // synopsys translate_on // remaining internal signals - reg [63 : 0] _theResult___fst__h2566; - reg [1 : 0] _theResult___snd__h2567, v__h3508; - wire [63 : 0] byte_addr__h2405, - byte_addr__h3346, - crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189, - mask__h3789, - new_time__h5047, - new_timecmp__h3758, - old_time__h7605, - rdata___1__h2562, - x__h2751, - x__h3800, - x__h5089, - y__h3801, - y__h3802; - wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155, - SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152; - wire [1 : 0] rresp__h2548, v__h3350; - wire NOT_cfg_verbosity_read_ULE_1_0___d31, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108, - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53, - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102, - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115; + reg [63 : 0] _theResult___fst__h5030; + reg [1 : 0] CASE_byte_addr142_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q1, + CASE_byte_addr837_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q3; + wire [71 : 0] slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4; + wire [66 : 0] IF_slave_xactor_shim_arff_rv_port1__read__9_BI_ETC___d168; + wire [63 : 0] byte_addr__h4837, + byte_addr__h6142, + crg_timecmp_port1__read__53_AND_INV_SEXT_slave_ETC___d292, + mask__h6615, + new_time__h7873, + new_timecmp__h6584, + old_time__h10432, + rdata___1__h5026, + x__h5248, + x__h6626, + x__h7915, + y__h6627, + y__h6628; + wire [7 : 0] SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d255, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d258, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d262, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d265, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d269, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d272, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d276, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d279; + wire [6 : 0] slave_xactor_shim_bff_rvport1__read_BITS_6_TO_0__q2; + wire IF_slave_xactor_shim_awff_rv_port1__read__76_B_ETC___d193, + NOT_cfg_verbosity_read__2_ULE_1_5___d76, + NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69, + rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189, + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116, + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d149, + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184, + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d324; // action method server_reset_request_put assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ; @@ -512,58 +689,64 @@ module mkNear_Mem_IO_AXI4(CLK, assign CAN_FIRE_set_addr_map = 1'd1 ; assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; + // action method axi4_slave_aw_awflit + assign CAN_FIRE_axi4_slave_aw_awflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_aw_awflit = axi4_slave_awvalid ; - // value method axi4_slave_m_awready - assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ; + // value method axi4_slave_aw_awready + assign axi4_slave_awready = !slave_xactor_shim_awff_rv[98] ; - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; + // action method axi4_slave_w_wflit + assign CAN_FIRE_axi4_slave_w_wflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_w_wflit = axi4_slave_wvalid ; - // value method axi4_slave_m_wready - assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ; + // value method axi4_slave_w_wready + assign axi4_slave_wready = !slave_xactor_shim_wff_rv[73] ; - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ; + // value method axi4_slave_b_bid + assign axi4_slave_bid = + slave_xactor_shim_bff_rvport1__read_BITS_6_TO_0__q2[6:2] ; - // value method axi4_slave_m_bid - assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ; + // value method axi4_slave_b_bresp + assign axi4_slave_bresp = + slave_xactor_shim_bff_rvport1__read_BITS_6_TO_0__q2[1:0] ; - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ; + // value method axi4_slave_b_bvalid + assign axi4_slave_bvalid = CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek ; - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; + // action method axi4_slave_b_bready + assign CAN_FIRE_axi4_slave_b_bready = 1'd1 ; + assign WILL_FIRE_axi4_slave_b_bready = 1'd1 ; - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; + // action method axi4_slave_ar_arflit + assign CAN_FIRE_axi4_slave_ar_arflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_ar_arflit = axi4_slave_arvalid ; - // value method axi4_slave_m_arready - assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ; + // value method axi4_slave_ar_arready + assign axi4_slave_arready = !slave_xactor_shim_arff_rv[98] ; - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ; + // value method axi4_slave_r_rid + assign axi4_slave_rid = + slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4[71:67] ; - // value method axi4_slave_m_rid - assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ; + // value method axi4_slave_r_rdata + assign axi4_slave_rdata = + slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4[66:3] ; - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ; + // value method axi4_slave_r_rresp + assign axi4_slave_rresp = + slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4[2:1] ; - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ; + // value method axi4_slave_r_rlast + assign axi4_slave_rlast = + slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4[0] ; - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ; + // value method axi4_slave_r_rvalid + assign axi4_slave_rvalid = CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek ; - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; + // action method axi4_slave_r_rready + assign CAN_FIRE_axi4_slave_r_rready = 1'd1 ; + assign WILL_FIRE_axi4_slave_r_rready = 1'd1 ; // actionvalue method get_timer_interrupt_req_get assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ; @@ -619,75 +802,61 @@ module mkNear_Mem_IO_AXI4(CLK, .FULL_N(f_timer_interrupt_req$FULL_N), .EMPTY_N(f_timer_interrupt_req$EMPTY_N)); - // submodule slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_addr$D_IN), - .ENQ(slave_xactor_f_rd_addr$ENQ), - .DEQ(slave_xactor_f_rd_addr$DEQ), - .CLR(slave_xactor_f_rd_addr$CLR), - .D_OUT(slave_xactor_f_rd_addr$D_OUT), - .FULL_N(slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_rd_data$D_IN), - .ENQ(slave_xactor_f_rd_data$ENQ), - .DEQ(slave_xactor_f_rd_data$DEQ), - .CLR(slave_xactor_f_rd_data$CLR), - .D_OUT(slave_xactor_f_rd_data$D_OUT), - .FULL_N(slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(slave_xactor_f_rd_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_addr$D_IN), - .ENQ(slave_xactor_f_wr_addr$ENQ), - .DEQ(slave_xactor_f_wr_addr$DEQ), - .CLR(slave_xactor_f_wr_addr$CLR), - .D_OUT(slave_xactor_f_wr_addr$D_OUT), - .FULL_N(slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_data$D_IN), - .ENQ(slave_xactor_f_wr_data$ENQ), - .DEQ(slave_xactor_f_wr_data$DEQ), - .CLR(slave_xactor_f_wr_data$CLR), - .D_OUT(slave_xactor_f_wr_data$D_OUT), - .FULL_N(slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(slave_xactor_f_wr_data$EMPTY_N)); - - // submodule slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(slave_xactor_f_wr_resp$D_IN), - .ENQ(slave_xactor_f_wr_resp$ENQ), - .DEQ(slave_xactor_f_wr_resp$DEQ), - .CLR(slave_xactor_f_wr_resp$CLR), - .D_OUT(slave_xactor_f_wr_resp$D_OUT), - .FULL_N(slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N)); - // rule RL_rl_reset - assign CAN_FIRE_RL_rl_reset = - f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ; - assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ; + assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; + assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ; // rule RL_rl_soft_reset assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_soft_reset = - f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; + assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ; + + // rule RL_slave_xactor_ug_slave_u_aw_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut = + slave_xactor_ug_slave_u_aw_putWire$whas && + slave_xactor_shim_awff_rv[98] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_aw_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut = + !slave_xactor_shim_awff_rv[98] && + slave_xactor_ug_slave_u_aw_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut ; + + // rule RL_slave_xactor_ug_slave_u_w_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut = + slave_xactor_ug_slave_u_w_putWire$whas && + slave_xactor_shim_wff_rv[73] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_w_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut = + !slave_xactor_shim_wff_rv[73] && + slave_xactor_ug_slave_u_w_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_w_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut ; + + // rule RL_slave_xactor_ug_slave_u_ar_warnDoPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut = + slave_xactor_ug_slave_u_ar_putWire$whas && + slave_xactor_shim_arff_rv[98] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut ; + + // rule RL_slave_xactor_ug_slave_u_ar_doPut + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut = + !slave_xactor_shim_arff_rv[98] && + slave_xactor_ug_slave_u_ar_putWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut ; // rule RL_rl_process_rd_req assign CAN_FIRE_RL_rl_process_rd_req = - slave_xactor_f_rd_addr$EMPTY_N && - slave_xactor_f_rd_data$FULL_N && + !slave_xactor_clearing && + slave_xactor_shim_arff_rv$port1__read[98] && + !slave_xactor_shim_rff_rv[72] && rg_state && !f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ; @@ -696,7 +865,7 @@ module mkNear_Mem_IO_AXI4(CLK, assign CAN_FIRE_RL_rl_compare = f_timer_interrupt_req$FULL_N && rg_state && rg_mtip != - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 && + NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69 && !f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ; @@ -708,52 +877,216 @@ module mkNear_Mem_IO_AXI4(CLK, // rule RL_rl_process_wr_req assign CAN_FIRE_RL_rl_process_wr_req = - slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 && + !slave_xactor_clearing && + slave_xactor_shim_awff_rv$port1__read[98] && + slave_xactor_shim_wff_rv$port1__read[73] && + !slave_xactor_shim_bff_rv[7] && + IF_slave_xactor_shim_awff_rv_port1__read__76_B_ETC___d193 && rg_state && !f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ; + // rule RL_slave_xactor_ug_slave_u_b_setPeek + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek = + slave_xactor_shim_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_setPeek ; + + // rule RL_slave_xactor_ug_slave_u_b_warnDoDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop = + slave_xactor_ug_slave_u_b_dropWire$whas && + !slave_xactor_shim_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop ; + + // rule RL_slave_xactor_ug_slave_u_b_doDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop = + slave_xactor_shim_bff_rv$port1__read[7] && + slave_xactor_ug_slave_u_b_dropWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop ; + + // rule RL_slave_xactor_ug_slave_u_r_setPeek + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek = + slave_xactor_shim_rff_rv$port1__read[72] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_setPeek ; + + // rule RL_slave_xactor_ug_slave_u_r_warnDoDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop = + slave_xactor_ug_slave_u_r_dropWire$whas && + !slave_xactor_shim_rff_rv$port1__read[72] ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop ; + + // rule RL_slave_xactor_ug_slave_u_r_doDrop + assign CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop = + slave_xactor_shim_rff_rv$port1__read[72] && + slave_xactor_ug_slave_u_r_dropWire$whas ; + assign WILL_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop ; + + // rule RL_slave_xactor_do_clear + assign CAN_FIRE_RL_slave_xactor_do_clear = slave_xactor_clearing ; + assign WILL_FIRE_RL_slave_xactor_do_clear = slave_xactor_clearing ; + // inputs to muxes for submodule ports assign MUX_crg_time$port1__write_1__SEL_1 = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h000000000000BFF8 || - byte_addr__h3346 == 64'h000000000000BFFC) ; + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + (byte_addr__h6142 == 64'h000000000000BFF8 || + byte_addr__h6142 == 64'h000000000000BFFC) ; assign MUX_crg_timecmp$port1__write_1__SEL_1 = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h0000000000004000 || - byte_addr__h3346 == 64'h0000000000004004) ; + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + (byte_addr__h6142 == 64'h0000000000004000 || + byte_addr__h6142 == 64'h0000000000004004) ; assign MUX_rg_msip$write_1__SEL_1 = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ; + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0 && + !rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189 ; + assign MUX_rg_state$write_1__SEL_1 = + f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ; + assign MUX_rg_state$write_1__SEL_2 = + !slave_xactor_clearing && f_reset_reqs$EMPTY_N && + f_reset_rsps$FULL_N && + !rg_state ; // inlined wires + assign slave_xactor_ug_slave_u_aw_putWire$wget = + { axi4_slave_awid, + axi4_slave_awaddr, + axi4_slave_awlen, + axi4_slave_awsize, + axi4_slave_awburst, + axi4_slave_awlock, + axi4_slave_awcache, + axi4_slave_awprot, + axi4_slave_awqos, + axi4_slave_awregion } ; + assign slave_xactor_ug_slave_u_aw_putWire$whas = + axi4_slave_awvalid && !slave_xactor_shim_awff_rv[98] ; + assign slave_xactor_ug_slave_u_w_putWire$wget = + { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; + assign slave_xactor_ug_slave_u_w_putWire$whas = + axi4_slave_wvalid && !slave_xactor_shim_wff_rv[73] ; + assign slave_xactor_ug_slave_u_ar_putWire$wget = + { axi4_slave_arid, + axi4_slave_araddr, + axi4_slave_arlen, + axi4_slave_arsize, + axi4_slave_arburst, + axi4_slave_arlock, + axi4_slave_arcache, + axi4_slave_arprot, + axi4_slave_arqos, + axi4_slave_arregion } ; + assign slave_xactor_ug_slave_u_ar_putWire$whas = + axi4_slave_arvalid && !slave_xactor_shim_arff_rv[98] ; + assign slave_xactor_ug_slave_u_b_dropWire$whas = + slave_xactor_shim_bff_rv$port1__read[7] && axi4_slave_bready ; + assign slave_xactor_ug_slave_u_r_dropWire$whas = + slave_xactor_shim_rff_rv$port1__read[72] && axi4_slave_rready ; + assign slave_xactor_shim_awff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_aw_putWire$wget } ; + assign slave_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_aw_doPut ? + slave_xactor_shim_awff_rv$port0__write_1 : + slave_xactor_shim_awff_rv ; + assign slave_xactor_shim_awff_rv$port2__read = + WILL_FIRE_RL_rl_process_wr_req ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_awff_rv$port1__read ; + assign slave_xactor_shim_awff_rv$port3__read = + slave_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_awff_rv$port2__read ; + assign slave_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_w_putWire$wget } ; + assign slave_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_w_doPut ? + slave_xactor_shim_wff_rv$port0__write_1 : + slave_xactor_shim_wff_rv ; + assign slave_xactor_shim_wff_rv$port2__read = + WILL_FIRE_RL_rl_process_wr_req ? + 74'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_wff_rv$port1__read ; + assign slave_xactor_shim_wff_rv$port3__read = + slave_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_wff_rv$port2__read ; + assign slave_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, + slave_xactor_shim_awff_rv$port1__read[97:93], + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 ? + 2'd3 : + CASE_byte_addr142_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q1 } ; + assign slave_xactor_shim_bff_rv$port1__read = + WILL_FIRE_RL_rl_process_wr_req ? + slave_xactor_shim_bff_rv$port0__write_1 : + slave_xactor_shim_bff_rv ; + assign slave_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_b_doDrop ? + 8'd42 : + slave_xactor_shim_bff_rv$port1__read ; + assign slave_xactor_shim_bff_rv$port3__read = + slave_xactor_clearing ? + 8'd42 : + slave_xactor_shim_bff_rv$port2__read ; + assign slave_xactor_shim_arff_rv$port0__write_1 = + { 1'd1, slave_xactor_ug_slave_u_ar_putWire$wget } ; + assign slave_xactor_shim_arff_rv$port1__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_ar_doPut ? + slave_xactor_shim_arff_rv$port0__write_1 : + slave_xactor_shim_arff_rv ; + assign slave_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_rl_process_rd_req ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_arff_rv$port1__read ; + assign slave_xactor_shim_arff_rv$port3__read = + slave_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + slave_xactor_shim_arff_rv$port2__read ; + assign slave_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, + slave_xactor_shim_arff_rv$port1__read[97:93], + IF_slave_xactor_shim_arff_rv_port1__read__9_BI_ETC___d168 } ; + assign slave_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_rl_process_rd_req ? + slave_xactor_shim_rff_rv$port0__write_1 : + slave_xactor_shim_rff_rv ; + assign slave_xactor_shim_rff_rv$port2__read = + CAN_FIRE_RL_slave_xactor_ug_slave_u_r_doDrop ? + 73'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_rff_rv$port1__read ; + assign slave_xactor_shim_rff_rv$port3__read = + slave_xactor_clearing ? + 73'h0AAAAAAAAAAAAAAAAAA : + slave_xactor_shim_rff_rv$port2__read ; assign crg_time$port0__write_1 = crg_time + 64'd1 ; assign crg_time$EN_port1__write = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h000000000000BFF8 || - byte_addr__h3346 == 64'h000000000000BFFC) || + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + (byte_addr__h6142 == 64'h000000000000BFF8 || + byte_addr__h6142 == 64'h000000000000BFFC) || WILL_FIRE_RL_rl_reset ; assign crg_time$port1__write_1 = - MUX_crg_time$port1__write_1__SEL_1 ? new_time__h5047 : 64'd1 ; + MUX_crg_time$port1__write_1__SEL_1 ? new_time__h7873 : 64'd1 ; assign crg_time$port2__read = crg_time$EN_port1__write ? crg_time$port1__write_1 : - old_time__h7605 ; + old_time__h10432 ; assign crg_timecmp$EN_port1__write = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - (byte_addr__h3346 == 64'h0000000000004000 || - byte_addr__h3346 == 64'h0000000000004004) || + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + (byte_addr__h6142 == 64'h0000000000004000 || + byte_addr__h6142 == 64'h0000000000004004) || WILL_FIRE_RL_rl_reset ; assign crg_timecmp$port1__write_1 = MUX_crg_timecmp$port1__write_1__SEL_1 ? - new_timecmp__h3758 : + new_timecmp__h6584 : 64'd0 ; assign crg_timecmp$port2__read = crg_timecmp$EN_port1__write ? @@ -782,222 +1115,214 @@ module mkNear_Mem_IO_AXI4(CLK, // register rg_msip assign rg_msip$D_IN = - MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ; + MUX_rg_msip$write_1__SEL_1 && + slave_xactor_shim_wff_rv$port1__read[9] ; assign rg_msip$EN = WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0 && + !rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189 || WILL_FIRE_RL_rl_reset ; // register rg_mtip assign rg_mtip$D_IN = !WILL_FIRE_RL_rl_compare || - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; + NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69 ; assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ; // register rg_state assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ; assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ; + // register slave_xactor_clearing + assign slave_xactor_clearing$D_IN = !slave_xactor_clearing ; + assign slave_xactor_clearing$EN = + slave_xactor_clearing || WILL_FIRE_RL_rl_reset ; + + // register slave_xactor_shim_arff_rv + assign slave_xactor_shim_arff_rv$D_IN = + slave_xactor_shim_arff_rv$port3__read ; + assign slave_xactor_shim_arff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_awff_rv + assign slave_xactor_shim_awff_rv$D_IN = + slave_xactor_shim_awff_rv$port3__read ; + assign slave_xactor_shim_awff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_bff_rv + assign slave_xactor_shim_bff_rv$D_IN = + slave_xactor_shim_bff_rv$port3__read ; + assign slave_xactor_shim_bff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_rff_rv + assign slave_xactor_shim_rff_rv$D_IN = + slave_xactor_shim_rff_rv$port3__read ; + assign slave_xactor_shim_rff_rv$EN = 1'b1 ; + + // register slave_xactor_shim_wff_rv + assign slave_xactor_shim_wff_rv$D_IN = + slave_xactor_shim_wff_rv$port3__read ; + assign slave_xactor_shim_wff_rv$EN = 1'b1 ; + // submodule f_reset_reqs assign f_reset_reqs$ENQ = EN_server_reset_request_put ; - assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ; + assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ; assign f_reset_reqs$CLR = 1'b0 ; // submodule f_reset_rsps - assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ; + assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ; assign f_reset_rsps$DEQ = EN_server_reset_response_get ; assign f_reset_rsps$CLR = 1'b0 ; // submodule f_sw_interrupt_req - assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ; + assign f_sw_interrupt_req$D_IN = slave_xactor_shim_wff_rv$port1__read[9] ; assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ; assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ; - assign f_sw_interrupt_req$CLR = CAN_FIRE_RL_rl_reset ; + assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; // submodule f_timer_interrupt_req assign f_timer_interrupt_req$D_IN = - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ; + NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69 ; assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ; assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ; - assign f_timer_interrupt_req$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule slave_xactor_f_rd_addr - assign slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ; - assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule slave_xactor_f_rd_data - assign slave_xactor_f_rd_data$D_IN = - { slave_xactor_f_rd_addr$D_OUT[96:93], - x__h2751, - rresp__h2548, - 1'd1 } ; - assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ; - assign slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ; - assign slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule slave_xactor_f_wr_addr - assign slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ; - assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule slave_xactor_f_wr_data - assign slave_xactor_f_wr_data$D_IN = - { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; - assign slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ; - assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_rl_reset ; - - // submodule slave_xactor_f_wr_resp - assign slave_xactor_f_wr_resp$D_IN = - { slave_xactor_f_wr_addr$D_OUT[96:93], v__h3350 } ; - assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ; - assign slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ; - assign slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_rl_reset ; + assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ; // remaining internal signals - assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ; - assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 = + assign IF_slave_xactor_shim_arff_rv_port1__read__9_BI_ETC___d168 = + { x__h5248, + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 ? + 2'd3 : + CASE_byte_addr837_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q3, + 1'd1 } ; + assign IF_slave_xactor_shim_awff_rv_port1__read__76_B_ETC___d193 = + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 ? + slave_xactor_shim_wff_rv$port1__read[73] : + byte_addr__h6142 != 64'h0 || + rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189 || + f_sw_interrupt_req$FULL_N ; + assign NOT_cfg_verbosity_read__2_ULE_1_5___d76 = cfg_verbosity > 4'd1 ; + assign NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69 = crg_time >= crg_timecmp ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 = - {8{slave_xactor_f_wr_data$D_OUT[1]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173 = - {8{slave_xactor_f_wr_data$D_OUT[2]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169 = - {8{slave_xactor_f_wr_data$D_OUT[3]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166 = - {8{slave_xactor_f_wr_data$D_OUT[4]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162 = - {8{slave_xactor_f_wr_data$D_OUT[5]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159 = - {8{slave_xactor_f_wr_data$D_OUT[6]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155 = - {8{slave_xactor_f_wr_data$D_OUT[7]}} ; - assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152 = - {8{slave_xactor_f_wr_data$D_OUT[8]}} ; - assign byte_addr__h2405 = - slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ; - assign byte_addr__h3346 = - slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ; - assign crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189 = - new_timecmp__h3758 - old_time__h7605 ; - assign mask__h3789 = - { SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152, - SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155, - SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159, - SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162, - SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166, - SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169, - SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173, - SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 } ; - assign new_time__h5047 = x__h5089 | y__h3801 ; - assign new_timecmp__h3758 = x__h3800 | y__h3801 ; - assign old_time__h7605 = + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d255 = + {8{slave_xactor_shim_wff_rv$port1__read[8]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d258 = + {8{slave_xactor_shim_wff_rv$port1__read[7]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d262 = + {8{slave_xactor_shim_wff_rv$port1__read[6]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d265 = + {8{slave_xactor_shim_wff_rv$port1__read[5]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d269 = + {8{slave_xactor_shim_wff_rv$port1__read[4]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d272 = + {8{slave_xactor_shim_wff_rv$port1__read[3]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d276 = + {8{slave_xactor_shim_wff_rv$port1__read[2]}} ; + assign SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d279 = + {8{slave_xactor_shim_wff_rv$port1__read[1]}} ; + assign byte_addr__h4837 = + slave_xactor_shim_arff_rv$port1__read[92:29] - rg_addr_base ; + assign byte_addr__h6142 = + slave_xactor_shim_awff_rv$port1__read[92:29] - rg_addr_base ; + assign crg_timecmp_port1__read__53_AND_INV_SEXT_slave_ETC___d292 = + new_timecmp__h6584 - old_time__h10432 ; + assign mask__h6615 = + { SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d255, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d258, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d262, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d265, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d269, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d272, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d276, + SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d279 } ; + assign new_time__h7873 = x__h7915 | y__h6627 ; + assign new_timecmp__h6584 = x__h6626 | y__h6627 ; + assign old_time__h10432 = CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ; - assign rdata___1__h2562 = { 63'd0, rg_msip } ; - assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 = - rg_msip == slave_xactor_f_wr_data$D_OUT[9] ; - assign rresp__h2548 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? - 2'b11 : - _theResult___snd__h2567 ; - assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 = - slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 = - slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ; - assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 = - slave_xactor_f_wr_addr$EMPTY_N && - slave_xactor_f_wr_data$EMPTY_N && - slave_xactor_f_wr_resp$FULL_N && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 || - rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 || - f_sw_interrupt_req$FULL_N) ; - assign v__h3350 = - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ? - 2'b11 : - v__h3508 ; - assign x__h2751 = - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ? + assign rdata___1__h5026 = { 63'd0, rg_msip } ; + assign rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189 = + rg_msip == slave_xactor_shim_wff_rv$port1__read[9] ; + assign slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 = + slave_xactor_shim_arff_rv$port1__read[92:29] < rg_addr_base ; + assign slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d149 = + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2 ; + assign slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 = + slave_xactor_shim_awff_rv$port1__read[92:29] < rg_addr_base ; + assign slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d324 = + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2 ; + assign slave_xactor_shim_bff_rvport1__read_BITS_6_TO_0__q2 = + slave_xactor_shim_bff_rv$port1__read[6:0] ; + assign slave_xactor_shim_rff_rvport1__read_BITS_71_TO_0__q4 = + slave_xactor_shim_rff_rv$port1__read[71:0] ; + assign x__h5248 = + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 ? 64'd0 : - _theResult___fst__h2566 ; - assign x__h3800 = crg_timecmp & y__h3802 ; - assign x__h5089 = old_time__h7605 & y__h3802 ; - assign y__h3801 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3789 ; - assign y__h3802 = - { ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173, - ~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 } ; - always@(byte_addr__h2405) + _theResult___fst__h5030 ; + assign x__h6626 = crg_timecmp & y__h6628 ; + assign x__h7915 = old_time__h10432 & y__h6628 ; + assign y__h6627 = slave_xactor_shim_wff_rv$port1__read[72:9] & mask__h6615 ; + assign y__h6628 = + { ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d255, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d258, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d262, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d265, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d269, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d272, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d276, + ~SEXT_slave_xactor_shim_wff_rv_port1__read__78__ETC___d279 } ; + always@(byte_addr__h6142) begin - case (byte_addr__h2405) + case (byte_addr__h6142) 64'h0, 64'h0000000000000004, 64'h0000000000004000, 64'h0000000000004004, 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___snd__h2567 = 2'b0; - default: _theResult___snd__h2567 = 2'b11; + CASE_byte_addr142_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q1 = 2'd0; + default: CASE_byte_addr142_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q1 = 2'd3; endcase end - always@(byte_addr__h2405 or rdata___1__h2562 or crg_timecmp or crg_time) + always@(byte_addr__h4837 or rdata___1__h5026 or crg_timecmp or crg_time) begin - case (byte_addr__h2405) - 64'h0: _theResult___fst__h2566 = rdata___1__h2562; - 64'h0000000000000004: _theResult___fst__h2566 = 64'd0; + case (byte_addr__h4837) + 64'h0: _theResult___fst__h5030 = rdata___1__h5026; + 64'h0000000000000004: _theResult___fst__h5030 = 64'd0; 64'h0000000000004000, 64'h0000000000004004: - _theResult___fst__h2566 = crg_timecmp; + _theResult___fst__h5030 = crg_timecmp; 64'h000000000000BFF8, 64'h000000000000BFFC: - _theResult___fst__h2566 = crg_time; - default: _theResult___fst__h2566 = 64'd0; + _theResult___fst__h5030 = crg_time; + default: _theResult___fst__h5030 = 64'd0; endcase end - always@(byte_addr__h3346) + always@(byte_addr__h4837) begin - case (byte_addr__h3346) + case (byte_addr__h4837) 64'h0, 64'h0000000000000004, 64'h0000000000004000, 64'h0000000000004004, 64'h000000000000BFF8, 64'h000000000000BFFC: - v__h3508 = 2'b0; - default: v__h3508 = 2'b11; + CASE_byte_addr837_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q3 = 2'd0; + default: CASE_byte_addr837_0x0_0_0x4_0_0x4000_0_0x4004__ETC__q3 = 2'd3; endcase end @@ -1012,6 +1337,16 @@ module mkNear_Mem_IO_AXI4(CLK, crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0; rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1; rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0; + slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 8'd42; + slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 73'h0AAAAAAAAAAAAAAAAAA; + slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; end else begin @@ -1022,6 +1357,24 @@ module mkNear_Mem_IO_AXI4(CLK, crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN; if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN; if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN; + if (slave_xactor_clearing$EN) + slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + slave_xactor_clearing$D_IN; + if (slave_xactor_shim_arff_rv$EN) + slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_arff_rv$D_IN; + if (slave_xactor_shim_awff_rv$EN) + slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_awff_rv$D_IN; + if (slave_xactor_shim_bff_rv$EN) + slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_bff_rv$D_IN; + if (slave_xactor_shim_rff_rv$EN) + slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_rff_rv$D_IN; + if (slave_xactor_shim_wff_rv$EN) + slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + slave_xactor_shim_wff_rv$D_IN; end if (rg_addr_base$EN) rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN; @@ -1042,6 +1395,12 @@ module mkNear_Mem_IO_AXI4(CLK, rg_msip = 1'h0; rg_mtip = 1'h0; rg_state = 1'h0; + slave_xactor_clearing = 1'h0; + slave_xactor_shim_arff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_awff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + slave_xactor_shim_bff_rv = 8'hAA; + slave_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA; + slave_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on @@ -1054,1704 +1413,2024 @@ module mkNear_Mem_IO_AXI4(CLK, #0; if (RST_N != `BSV_RESET_VALUE) if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h10050 = $stime; + v__h13099 = $stime; #0; end - v__h10044 = v__h10050 / 32'd10; + v__h13093 = v__h13099 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_get_timer_interrupt_req_get && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x", - v__h10044, + v__h13093, f_timer_interrupt_req$D_OUT); if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) + if (EN_get_sw_interrupt_req_get && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h10182 = $stime; + v__h13231 = $stime; #0; end - v__h10176 = v__h10182 / 32'd10; + v__h13225 = v__h13231 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31) + if (EN_get_sw_interrupt_req_get && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x", - v__h10176, + v__h13225, f_sw_interrupt_req$D_OUT); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) begin - v__h1852 = $stime; + v__h4164 = $stime; #0; end - v__h1846 = v__h1852 / 32'd10; + v__h4158 = v__h4164 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0) - $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1846); + $display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h4158); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_aw_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_w_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_ar_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h2269 = $stime; + v__h4672 = $stime; #0; end - v__h2263 = v__h2269 / 32'd10; + v__h4666 = v__h4672 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d", - v__h2263, + v__h4666, rg_mtip); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) begin - v__h2453 = $stime; + v__h4886 = $stime; #0; end - v__h2447 = v__h2453 / 32'd10; + v__h4880 = v__h4886 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2447); + v__h4880); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("AXI4_Rd_Addr { ", "arid: "); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + !slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53) + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) begin - v__h2640 = $stime; + v__h5109 = $stime; #0; end - v__h2634 = v__h2640 / 32'd10; + v__h5103 = v__h5109 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr", - v__h2634); + v__h5103); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("AXI4_Rd_Addr { ", "arid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("AXI4_ARFlit { ", "arid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[97:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d149) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC) && + !slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - (slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 || - byte_addr__h2405 != 64'h0 && - byte_addr__h2405 != 64'h0000000000004000 && - byte_addr__h2405 != 64'h000000000000BFF8 && - byte_addr__h2405 != 64'h0000000000000004 && - byte_addr__h2405 != 64'h0000000000004004 && - byte_addr__h2405 != 64'h000000000000BFFC)) + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h2878 = $stime; + v__h5435 = $stime; #0; end - v__h2872 = v__h2878 / 32'd10; + v__h5429 = v__h5435 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2872); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h5429); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Addr { ", "arid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Rd_Data { ", "rid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", x__h2751); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", x__h5248); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", rresp__h2548); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 && + (byte_addr__h4837 == 64'h0 || + byte_addr__h4837 == 64'h0000000000004000 || + byte_addr__h4837 == 64'h000000000000BFF8 || + byte_addr__h4837 == 64'h0000000000000004 || + byte_addr__h4837 == 64'h0000000000004004 || + byte_addr__h4837 == 64'h000000000000BFFC)) + $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + (slave_xactor_shim_arff_rv_port1__read__9_BITS__ETC___d116 || + byte_addr__h4837 != 64'h0 && + byte_addr__h4837 != 64'h0000000000004000 && + byte_addr__h4837 != 64'h000000000000BFF8 && + byte_addr__h4837 != 64'h0000000000000004 && + byte_addr__h4837 != 64'h0000000000004004 && + byte_addr__h4837 != 64'h000000000000BFFC)) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_rd_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_rd_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) + if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h2095 = $stime; + v__h4408 = $stime; #0; end - v__h2089 = v__h2095 / 32'd10; + v__h4402 = v__h4408 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31) + if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d", - v__h2089, - NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24, + v__h4402, + NOT_crg_time_port0__read__8_ULT_crg_timecmp_po_ETC___d69, crg_time, crg_timecmp); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h3158 = $stime; + v__h5925 = $stime; #0; end - v__h3152 = v__h3158 / 32'd10; + v__h5919 = v__h5925 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d", - v__h3152, + v__h5919, rg_mtip); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wdata: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) begin - v__h3384 = $stime; + v__h6181 = $stime; #0; end - v__h3378 = v__h3384 / 32'd10; + v__h6175 = v__h6181 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h3378); + v__h6175); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Addr { ", "awid: "); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + !slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("AXI4_Wr_Data { ", "wdata: "); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - slave_xactor_f_wr_data$D_OUT[0]) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - !slave_xactor_f_wr_data$D_OUT[0]) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + !slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102) + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0 && - !rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0 && + !rg_msip_52_EQ_slave_xactor_shim_wff_rv_port1___ETC___d189 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" new MSIP = %0d", + slave_xactor_shim_wff_rv$port1__read[9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004000 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" Writing MTIMECMP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004000 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" old MTIMECMP = 0x%0h", crg_timecmp); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3758); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004000 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" new MTIMECMP = 0x%0h", new_timecmp__h6584); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7605); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004000 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" cur MTIME = 0x%0h", old_time__h10432); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004000 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004000 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189); + crg_timecmp_port1__read__53_AND_INV_SEXT_slave_ETC___d292); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFF8 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" Writing MTIME"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7605); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFF8 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" old MTIME = 0x%0h", old_time__h10432); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFF8 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5047); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFF8 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" new MTIME = 0x%0h", new_time__h7873); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004004 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" Writing MTIMECMP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004004 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" old MTIMECMP = 0x%0h", crg_timecmp); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIMECMP = 0x%0h", new_timecmp__h3758); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004004 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" new MTIMECMP = 0x%0h", new_timecmp__h6584); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" cur MTIME = 0x%0h", old_time__h7605); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004004 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" cur MTIME = 0x%0h", old_time__h10432); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h0000000000004004 && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h0000000000004004 && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" new MTIMECMP - MTIME = 0x%0h", - crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189); + crg_timecmp_port1__read__53_AND_INV_SEXT_slave_ETC___d292); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFFC && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $display(" Writing MTIME"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" old MTIME = 0x%0h", old_time__h7605); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFFC && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" old MTIME = 0x%0h", old_time__h10432); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - !slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 && - byte_addr__h3346 == 64'h000000000000BFFC && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display(" new MTIME = 0x%0h", new_time__h5047); + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + byte_addr__h6142 == 64'h000000000000BFFC && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display(" new MTIME = 0x%0h", new_time__h7873); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) begin - v__h8918 = $stime; + v__h11750 = $stime; #0; end - v__h8912 = v__h8918 / 32'd10; + v__h11744 = v__h11750 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr", - v__h8912); + v__h11744); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Addr { ", "awid: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("AXI4_AWFlit { ", "awid: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[97:93]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d324) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + !slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("AXI4_Wr_Data { ", "wdata: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("AXI4_WFlit { ", "wdata: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[72:9]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC) && - slave_xactor_f_wr_data$D_OUT[0]) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC) && - !slave_xactor_f_wr_data$D_OUT[0]) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC) && + !slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - (slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 || - byte_addr__h3346 != 64'h0 && - byte_addr__h3346 != 64'h0000000000004000 && - byte_addr__h3346 != 64'h000000000000BFF8 && - byte_addr__h3346 != 64'h0000000000000004 && - byte_addr__h3346 != 64'h0000000000004004 && - byte_addr__h3346 != 64'h000000000000BFFC)) + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) begin - v__h9137 = $stime; + v__h12059 = $stime; #0; end - v__h9131 = v__h9137 / 32'd10; + v__h12053 = v__h12059 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9131); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h12053); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Addr { ", "awid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Data { ", "wdata: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - slave_xactor_f_wr_data$D_OUT[0]) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31 && - !slave_xactor_f_wr_data$D_OUT[0]) + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("AXI4_Wr_Resp { ", "bid: "); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("AXI4_BFlit { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_cfg_verbosity_read__2_ULE_1_5___d76) + $write("'h%h", slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) - $write("'h%h", v__h3350); + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + !slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 && + (byte_addr__h6142 == 64'h0 || + byte_addr__h6142 == 64'h0000000000004000 || + byte_addr__h6142 == 64'h000000000000BFF8 || + byte_addr__h6142 == 64'h0000000000000004 || + byte_addr__h6142 == 64'h0000000000004004 || + byte_addr__h6142 == 64'h000000000000BFFC)) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_process_wr_req && + NOT_cfg_verbosity_read__2_ULE_1_5___d76 && + (slave_xactor_shim_awff_rv_port1__read__76_BITS_ETC___d184 || + byte_addr__h6142 != 64'h0 && + byte_addr__h6142 != 64'h0000000000004000 && + byte_addr__h6142 != 64'h000000000000BFF8 && + byte_addr__h6142 != 64'h0000000000000004 && + byte_addr__h6142 != 64'h0000000000004004 && + byte_addr__h6142 != 64'h000000000000BFFC)) + $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_process_wr_req && - NOT_cfg_verbosity_read_ULE_1_0___d31) + NOT_cfg_verbosity_read__2_ULE_1_5___d76) $write("\n"); if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h9462 = $stime; + v__h12451 = $stime; #0; end - v__h9456 = v__h9462 / 32'd10; + v__h12445 = v__h12451 / 32'd10; if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h9456, + v__h12445, set_addr_map_addr_base); if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h9572 = $stime; + v__h12561 = $stime; #0; end - v__h9566 = v__h9572 / 32'd10; + v__h12555 = v__h12561 / 32'd10; if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h9566, + v__h12555, set_addr_map_addr_lim); if (EN_set_addr_map) begin - v__h9679 = $stime; + v__h12668 = $stime; #0; end - v__h9673 = v__h9679 / 32'd10; + v__h12662 = v__h12668 / 32'd10; if (EN_set_addr_map) $display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h", - v__h9673, + v__h12662, set_addr_map_addr_base, set_addr_map_addr_lim); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_b_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_slave_xactor_ug_slave_u_r_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); end // synopsys translate_on endmodule // mkNear_Mem_IO_AXI4 diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkP1_Core.v b/src_SSITH_P1/xilinx_ip/hdl/mkP1_Core.v index a06532cb..4ec432f9 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkP1_Core.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkP1_Core.v @@ -1,41 +1,40 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:19:01 BST 2019 // // // Ports: // Name I/O size props +// master0_awid O 5 +// master0_awaddr O 64 +// master0_awlen O 8 +// master0_awsize O 3 +// master0_awburst O 2 +// master0_awlock O 1 +// master0_awcache O 4 +// master0_awprot O 3 +// master0_awqos O 4 +// master0_awregion O 4 // master0_awvalid O 1 -// master0_awid O 4 reg -// master0_awaddr O 64 reg -// master0_awlen O 8 reg -// master0_awsize O 3 reg -// master0_awburst O 2 reg -// master0_awlock O 1 reg -// master0_awcache O 4 reg -// master0_awprot O 3 reg -// master0_awqos O 4 reg -// master0_awregion O 4 reg +// master0_wdata O 64 +// master0_wstrb O 8 +// master0_wlast O 1 // master0_wvalid O 1 -// master0_wdata O 64 reg -// master0_wstrb O 8 reg -// master0_wlast O 1 reg // master0_bready O 1 +// master0_arid O 5 +// master0_araddr O 64 +// master0_arlen O 8 +// master0_arsize O 3 +// master0_arburst O 2 +// master0_arlock O 1 +// master0_arcache O 4 +// master0_arprot O 3 +// master0_arqos O 4 +// master0_arregion O 4 // master0_arvalid O 1 -// master0_arid O 4 reg -// master0_araddr O 64 reg -// master0_arlen O 8 reg -// master0_arsize O 3 reg -// master0_arburst O 2 reg -// master0_arlock O 1 reg -// master0_arcache O 4 reg -// master0_arprot O 3 reg -// master0_arqos O 4 reg -// master0_arregion O 4 reg // master0_rready O 1 -// master1_awvalid O 1 reg -// master1_awid O 4 reg +// master1_awid O 5 reg // master1_awaddr O 64 reg // master1_awlen O 8 reg // master1_awsize O 3 reg @@ -45,13 +44,13 @@ // master1_awprot O 3 reg // master1_awqos O 4 reg // master1_awregion O 4 reg -// master1_wvalid O 1 reg +// master1_awvalid O 1 reg // master1_wdata O 64 reg // master1_wstrb O 8 reg // master1_wlast O 1 reg +// master1_wvalid O 1 reg // master1_bready O 1 reg -// master1_arvalid O 1 reg -// master1_arid O 4 reg +// master1_arid O 5 reg // master1_araddr O 64 reg // master1_arlen O 8 reg // master1_arsize O 3 reg @@ -61,6 +60,7 @@ // master1_arprot O 3 reg // master1_arqos O 4 reg // master1_arregion O 4 reg +// master1_arvalid O 1 reg // master1_rready O 1 reg // tv_verifier_info_tx_tvalid O 1 reg // tv_verifier_info_tx_tdata O 608 reg @@ -74,23 +74,19 @@ // RST_N I 1 reset // master0_awready I 1 // master0_wready I 1 -// master0_bvalid I 1 -// master0_bid I 4 reg -// master0_bresp I 2 reg +// master0_bid I 5 +// master0_bresp I 2 // master0_arready I 1 -// master0_rvalid I 1 -// master0_rid I 4 reg -// master0_rdata I 64 reg -// master0_rresp I 2 reg -// master0_rlast I 1 reg +// master0_rid I 5 +// master0_rdata I 64 +// master0_rresp I 2 +// master0_rlast I 1 // master1_awready I 1 // master1_wready I 1 -// master1_bvalid I 1 -// master1_bid I 4 reg +// master1_bid I 5 reg // master1_bresp I 2 reg // master1_arready I 1 -// master1_rvalid I 1 -// master1_rid I 4 reg +// master1_rid I 5 reg // master1_rdata I 64 reg // master1_rresp I 2 reg // master1_rlast I 1 reg @@ -99,10 +95,72 @@ // jtag_tdi I 1 // jtag_tms I 1 // jtag_tclk I 1 +// master0_bvalid I 1 +// master0_rvalid I 1 +// master1_bvalid I 1 +// master1_rvalid I 1 // // Combinational paths from inputs to outputs: -// (master0_awready, master0_wready) -> master0_bready -// (master0_awready, master0_wready) -> master0_rready +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arid +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_araddr +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arlen +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arsize +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arburst +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arlock +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arcache +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arprot +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arqos +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arregion +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_aruser +// (master0_rid, +// master0_rdata, +// master0_rresp, +// master0_rlast, +// master0_rvalid) -> master0_arvalid // // @@ -122,8 +180,6 @@ module mkP1_Core(CLK, RST_N, - master0_awvalid, - master0_awid, master0_awaddr, @@ -144,9 +200,9 @@ module mkP1_Core(CLK, master0_awregion, - master0_awready, + master0_awvalid, - master0_wvalid, + master0_awready, master0_wdata, @@ -154,16 +210,16 @@ module mkP1_Core(CLK, master0_wlast, + master0_wvalid, + master0_wready, - master0_bvalid, master0_bid, master0_bresp, + master0_bvalid, master0_bready, - master0_arvalid, - master0_arid, master0_araddr, @@ -184,18 +240,18 @@ module mkP1_Core(CLK, master0_arregion, + master0_arvalid, + master0_arready, - master0_rvalid, master0_rid, master0_rdata, master0_rresp, master0_rlast, + master0_rvalid, master0_rready, - master1_awvalid, - master1_awid, master1_awaddr, @@ -216,9 +272,9 @@ module mkP1_Core(CLK, master1_awregion, - master1_awready, + master1_awvalid, - master1_wvalid, + master1_awready, master1_wdata, @@ -226,16 +282,16 @@ module mkP1_Core(CLK, master1_wlast, + master1_wvalid, + master1_wready, - master1_bvalid, master1_bid, master1_bresp, + master1_bvalid, master1_bready, - master1_arvalid, - master1_arid, master1_araddr, @@ -256,13 +312,15 @@ module mkP1_Core(CLK, master1_arregion, + master1_arvalid, + master1_arready, - master1_rvalid, master1_rid, master1_rdata, master1_rresp, master1_rlast, + master1_rvalid, master1_rready, @@ -293,226 +351,226 @@ module mkP1_Core(CLK, input CLK; input RST_N; - // value method master0_m_awvalid - output master0_awvalid; - - // value method master0_m_awid - output [3 : 0] master0_awid; + // value method master0_aw_awid + output [4 : 0] master0_awid; - // value method master0_m_awaddr + // value method master0_aw_awaddr output [63 : 0] master0_awaddr; - // value method master0_m_awlen + // value method master0_aw_awlen output [7 : 0] master0_awlen; - // value method master0_m_awsize + // value method master0_aw_awsize output [2 : 0] master0_awsize; - // value method master0_m_awburst + // value method master0_aw_awburst output [1 : 0] master0_awburst; - // value method master0_m_awlock + // value method master0_aw_awlock output master0_awlock; - // value method master0_m_awcache + // value method master0_aw_awcache output [3 : 0] master0_awcache; - // value method master0_m_awprot + // value method master0_aw_awprot output [2 : 0] master0_awprot; - // value method master0_m_awqos + // value method master0_aw_awqos output [3 : 0] master0_awqos; - // value method master0_m_awregion + // value method master0_aw_awregion output [3 : 0] master0_awregion; - // value method master0_m_awuser + // value method master0_aw_awuser - // action method master0_m_awready - input master0_awready; + // value method master0_aw_awvalid + output master0_awvalid; - // value method master0_m_wvalid - output master0_wvalid; + // action method master0_aw_awready + input master0_awready; - // value method master0_m_wdata + // value method master0_w_wdata output [63 : 0] master0_wdata; - // value method master0_m_wstrb + // value method master0_w_wstrb output [7 : 0] master0_wstrb; - // value method master0_m_wlast + // value method master0_w_wlast output master0_wlast; - // value method master0_m_wuser + // value method master0_w_wuser - // action method master0_m_wready + // value method master0_w_wvalid + output master0_wvalid; + + // action method master0_w_wready input master0_wready; - // action method master0_m_bvalid - input master0_bvalid; - input [3 : 0] master0_bid; + // action method master0_b_bflit + input [4 : 0] master0_bid; input [1 : 0] master0_bresp; + input master0_bvalid; - // value method master0_m_bready + // value method master0_b_bready output master0_bready; - // value method master0_m_arvalid - output master0_arvalid; + // value method master0_ar_arid + output [4 : 0] master0_arid; - // value method master0_m_arid - output [3 : 0] master0_arid; - - // value method master0_m_araddr + // value method master0_ar_araddr output [63 : 0] master0_araddr; - // value method master0_m_arlen + // value method master0_ar_arlen output [7 : 0] master0_arlen; - // value method master0_m_arsize + // value method master0_ar_arsize output [2 : 0] master0_arsize; - // value method master0_m_arburst + // value method master0_ar_arburst output [1 : 0] master0_arburst; - // value method master0_m_arlock + // value method master0_ar_arlock output master0_arlock; - // value method master0_m_arcache + // value method master0_ar_arcache output [3 : 0] master0_arcache; - // value method master0_m_arprot + // value method master0_ar_arprot output [2 : 0] master0_arprot; - // value method master0_m_arqos + // value method master0_ar_arqos output [3 : 0] master0_arqos; - // value method master0_m_arregion + // value method master0_ar_arregion output [3 : 0] master0_arregion; - // value method master0_m_aruser + // value method master0_ar_aruser + + // value method master0_ar_arvalid + output master0_arvalid; - // action method master0_m_arready + // action method master0_ar_arready input master0_arready; - // action method master0_m_rvalid - input master0_rvalid; - input [3 : 0] master0_rid; + // action method master0_r_rflit + input [4 : 0] master0_rid; input [63 : 0] master0_rdata; input [1 : 0] master0_rresp; input master0_rlast; + input master0_rvalid; - // value method master0_m_rready + // value method master0_r_rready output master0_rready; - // value method master1_m_awvalid - output master1_awvalid; - - // value method master1_m_awid - output [3 : 0] master1_awid; + // value method master1_aw_awid + output [4 : 0] master1_awid; - // value method master1_m_awaddr + // value method master1_aw_awaddr output [63 : 0] master1_awaddr; - // value method master1_m_awlen + // value method master1_aw_awlen output [7 : 0] master1_awlen; - // value method master1_m_awsize + // value method master1_aw_awsize output [2 : 0] master1_awsize; - // value method master1_m_awburst + // value method master1_aw_awburst output [1 : 0] master1_awburst; - // value method master1_m_awlock + // value method master1_aw_awlock output master1_awlock; - // value method master1_m_awcache + // value method master1_aw_awcache output [3 : 0] master1_awcache; - // value method master1_m_awprot + // value method master1_aw_awprot output [2 : 0] master1_awprot; - // value method master1_m_awqos + // value method master1_aw_awqos output [3 : 0] master1_awqos; - // value method master1_m_awregion + // value method master1_aw_awregion output [3 : 0] master1_awregion; - // value method master1_m_awuser + // value method master1_aw_awuser - // action method master1_m_awready - input master1_awready; + // value method master1_aw_awvalid + output master1_awvalid; - // value method master1_m_wvalid - output master1_wvalid; + // action method master1_aw_awready + input master1_awready; - // value method master1_m_wdata + // value method master1_w_wdata output [63 : 0] master1_wdata; - // value method master1_m_wstrb + // value method master1_w_wstrb output [7 : 0] master1_wstrb; - // value method master1_m_wlast + // value method master1_w_wlast output master1_wlast; - // value method master1_m_wuser + // value method master1_w_wuser - // action method master1_m_wready + // value method master1_w_wvalid + output master1_wvalid; + + // action method master1_w_wready input master1_wready; - // action method master1_m_bvalid - input master1_bvalid; - input [3 : 0] master1_bid; + // action method master1_b_bflit + input [4 : 0] master1_bid; input [1 : 0] master1_bresp; + input master1_bvalid; - // value method master1_m_bready + // value method master1_b_bready output master1_bready; - // value method master1_m_arvalid - output master1_arvalid; - - // value method master1_m_arid - output [3 : 0] master1_arid; + // value method master1_ar_arid + output [4 : 0] master1_arid; - // value method master1_m_araddr + // value method master1_ar_araddr output [63 : 0] master1_araddr; - // value method master1_m_arlen + // value method master1_ar_arlen output [7 : 0] master1_arlen; - // value method master1_m_arsize + // value method master1_ar_arsize output [2 : 0] master1_arsize; - // value method master1_m_arburst + // value method master1_ar_arburst output [1 : 0] master1_arburst; - // value method master1_m_arlock + // value method master1_ar_arlock output master1_arlock; - // value method master1_m_arcache + // value method master1_ar_arcache output [3 : 0] master1_arcache; - // value method master1_m_arprot + // value method master1_ar_arprot output [2 : 0] master1_arprot; - // value method master1_m_arqos + // value method master1_ar_arqos output [3 : 0] master1_arqos; - // value method master1_m_arregion + // value method master1_ar_arregion output [3 : 0] master1_arregion; - // value method master1_m_aruser + // value method master1_ar_aruser - // action method master1_m_arready + // value method master1_ar_arvalid + output master1_arvalid; + + // action method master1_ar_arready input master1_arready; - // action method master1_m_rvalid - input master1_rvalid; - input [3 : 0] master1_rid; + // action method master1_r_rflit + input [4 : 0] master1_rid; input [63 : 0] master1_rdata; input [1 : 0] master1_rresp; input master1_rlast; + input master1_rvalid; - // value method master1_m_rready + // value method master1_r_rready output master1_rready; // action method interrupt_reqs @@ -573,20 +631,17 @@ module mkP1_Core(CLK, master1_arlen, master1_awlen, master1_wstrb; + wire [4 : 0] master0_arid, master0_awid, master1_arid, master1_awid; wire [3 : 0] master0_arcache, - master0_arid, master0_arqos, master0_arregion, master0_awcache, - master0_awid, master0_awqos, master0_awregion, master1_arcache, - master1_arid, master1_arqos, master1_arregion, master1_awcache, - master1_awid, master1_awqos, master1_awregion; wire [2 : 0] master0_arprot, @@ -625,7 +680,7 @@ module mkP1_Core(CLK, // inlined wires wire [40 : 0] bus_dmi_req_data_wire$wget; - wire bus_dmi_rsp_fifof_enqueueing$whas; + wire bus_dmi_rsp_fifof_x_wire$whas; // register bus_dmi_rsp_fifof_cntr_r reg [1 : 0] bus_dmi_rsp_fifof_cntr_r; @@ -678,26 +733,26 @@ module mkP1_Core(CLK, core$cpu_imem_master_awlen, core$cpu_imem_master_wstrb; wire [6 : 0] core$dm_dmi_read_addr_dm_addr, core$dm_dmi_write_dm_addr; + wire [4 : 0] core$cpu_dmem_master_arid, + core$cpu_dmem_master_awid, + core$cpu_dmem_master_bid, + core$cpu_dmem_master_rid, + core$cpu_imem_master_arid, + core$cpu_imem_master_awid, + core$cpu_imem_master_bid, + core$cpu_imem_master_rid; wire [3 : 0] core$cpu_dmem_master_arcache, - core$cpu_dmem_master_arid, core$cpu_dmem_master_arqos, core$cpu_dmem_master_arregion, core$cpu_dmem_master_awcache, - core$cpu_dmem_master_awid, core$cpu_dmem_master_awqos, core$cpu_dmem_master_awregion, - core$cpu_dmem_master_bid, - core$cpu_dmem_master_rid, core$cpu_imem_master_arcache, - core$cpu_imem_master_arid, core$cpu_imem_master_arqos, core$cpu_imem_master_arregion, core$cpu_imem_master_awcache, - core$cpu_imem_master_awid, core$cpu_imem_master_awqos, core$cpu_imem_master_awregion, - core$cpu_imem_master_bid, - core$cpu_imem_master_rid, core$set_verbosity_verbosity; wire [2 : 0] core$cpu_dmem_master_arprot, core$cpu_dmem_master_arsize, @@ -833,16 +888,16 @@ module mkP1_Core(CLK, CAN_FIRE_jtag_tclk, CAN_FIRE_jtag_tdi, CAN_FIRE_jtag_tms, - CAN_FIRE_master0_m_arready, - CAN_FIRE_master0_m_awready, - CAN_FIRE_master0_m_bvalid, - CAN_FIRE_master0_m_rvalid, - CAN_FIRE_master0_m_wready, - CAN_FIRE_master1_m_arready, - CAN_FIRE_master1_m_awready, - CAN_FIRE_master1_m_bvalid, - CAN_FIRE_master1_m_rvalid, - CAN_FIRE_master1_m_wready, + CAN_FIRE_master0_ar_arready, + CAN_FIRE_master0_aw_awready, + CAN_FIRE_master0_b_bflit, + CAN_FIRE_master0_r_rflit, + CAN_FIRE_master0_w_wready, + CAN_FIRE_master1_ar_arready, + CAN_FIRE_master1_aw_awready, + CAN_FIRE_master1_b_bflit, + CAN_FIRE_master1_r_rflit, + CAN_FIRE_master1_w_wready, CAN_FIRE_tv_verifier_info_tx_m_tready, WILL_FIRE_RL_bus_dmi_req_do_enq, WILL_FIRE_RL_bus_dmi_rsp_do_deq, @@ -871,16 +926,16 @@ module mkP1_Core(CLK, WILL_FIRE_jtag_tclk, WILL_FIRE_jtag_tdi, WILL_FIRE_jtag_tms, - WILL_FIRE_master0_m_arready, - WILL_FIRE_master0_m_awready, - WILL_FIRE_master0_m_bvalid, - WILL_FIRE_master0_m_rvalid, - WILL_FIRE_master0_m_wready, - WILL_FIRE_master1_m_arready, - WILL_FIRE_master1_m_awready, - WILL_FIRE_master1_m_bvalid, - WILL_FIRE_master1_m_rvalid, - WILL_FIRE_master1_m_wready, + WILL_FIRE_master0_ar_arready, + WILL_FIRE_master0_aw_awready, + WILL_FIRE_master0_b_bflit, + WILL_FIRE_master0_r_rflit, + WILL_FIRE_master0_w_wready, + WILL_FIRE_master1_ar_arready, + WILL_FIRE_master1_aw_awready, + WILL_FIRE_master1_b_bflit, + WILL_FIRE_master1_r_rflit, + WILL_FIRE_master1_w_wready, WILL_FIRE_tv_verifier_info_tx_m_tready; // inputs to muxes for submodule ports @@ -907,212 +962,212 @@ module mkP1_Core(CLK, assign CLK_jtag_tclk_out = jtagtap$CLK_jtag_tclk_out ; assign CLK_GATE_jtag_tclk_out = 1'b1 ; - // value method master0_m_awvalid - assign master0_awvalid = core$cpu_imem_master_awvalid ; - - // value method master0_m_awid + // value method master0_aw_awid assign master0_awid = core$cpu_imem_master_awid ; - // value method master0_m_awaddr + // value method master0_aw_awaddr assign master0_awaddr = core$cpu_imem_master_awaddr ; - // value method master0_m_awlen + // value method master0_aw_awlen assign master0_awlen = core$cpu_imem_master_awlen ; - // value method master0_m_awsize + // value method master0_aw_awsize assign master0_awsize = core$cpu_imem_master_awsize ; - // value method master0_m_awburst + // value method master0_aw_awburst assign master0_awburst = core$cpu_imem_master_awburst ; - // value method master0_m_awlock + // value method master0_aw_awlock assign master0_awlock = core$cpu_imem_master_awlock ; - // value method master0_m_awcache + // value method master0_aw_awcache assign master0_awcache = core$cpu_imem_master_awcache ; - // value method master0_m_awprot + // value method master0_aw_awprot assign master0_awprot = core$cpu_imem_master_awprot ; - // value method master0_m_awqos + // value method master0_aw_awqos assign master0_awqos = core$cpu_imem_master_awqos ; - // value method master0_m_awregion + // value method master0_aw_awregion assign master0_awregion = core$cpu_imem_master_awregion ; - // action method master0_m_awready - assign CAN_FIRE_master0_m_awready = 1'd1 ; - assign WILL_FIRE_master0_m_awready = 1'd1 ; + // value method master0_aw_awvalid + assign master0_awvalid = core$cpu_imem_master_awvalid ; - // value method master0_m_wvalid - assign master0_wvalid = core$cpu_imem_master_wvalid ; + // action method master0_aw_awready + assign CAN_FIRE_master0_aw_awready = 1'd1 ; + assign WILL_FIRE_master0_aw_awready = 1'd1 ; - // value method master0_m_wdata + // value method master0_w_wdata assign master0_wdata = core$cpu_imem_master_wdata ; - // value method master0_m_wstrb + // value method master0_w_wstrb assign master0_wstrb = core$cpu_imem_master_wstrb ; - // value method master0_m_wlast + // value method master0_w_wlast assign master0_wlast = core$cpu_imem_master_wlast ; - // action method master0_m_wready - assign CAN_FIRE_master0_m_wready = 1'd1 ; - assign WILL_FIRE_master0_m_wready = 1'd1 ; + // value method master0_w_wvalid + assign master0_wvalid = core$cpu_imem_master_wvalid ; - // action method master0_m_bvalid - assign CAN_FIRE_master0_m_bvalid = 1'd1 ; - assign WILL_FIRE_master0_m_bvalid = 1'd1 ; + // action method master0_w_wready + assign CAN_FIRE_master0_w_wready = 1'd1 ; + assign WILL_FIRE_master0_w_wready = 1'd1 ; - // value method master0_m_bready - assign master0_bready = core$cpu_imem_master_bready ; + // action method master0_b_bflit + assign CAN_FIRE_master0_b_bflit = 1'd1 ; + assign WILL_FIRE_master0_b_bflit = master0_bvalid ; - // value method master0_m_arvalid - assign master0_arvalid = core$cpu_imem_master_arvalid ; + // value method master0_b_bready + assign master0_bready = core$cpu_imem_master_bready ; - // value method master0_m_arid + // value method master0_ar_arid assign master0_arid = core$cpu_imem_master_arid ; - // value method master0_m_araddr + // value method master0_ar_araddr assign master0_araddr = core$cpu_imem_master_araddr ; - // value method master0_m_arlen + // value method master0_ar_arlen assign master0_arlen = core$cpu_imem_master_arlen ; - // value method master0_m_arsize + // value method master0_ar_arsize assign master0_arsize = core$cpu_imem_master_arsize ; - // value method master0_m_arburst + // value method master0_ar_arburst assign master0_arburst = core$cpu_imem_master_arburst ; - // value method master0_m_arlock + // value method master0_ar_arlock assign master0_arlock = core$cpu_imem_master_arlock ; - // value method master0_m_arcache + // value method master0_ar_arcache assign master0_arcache = core$cpu_imem_master_arcache ; - // value method master0_m_arprot + // value method master0_ar_arprot assign master0_arprot = core$cpu_imem_master_arprot ; - // value method master0_m_arqos + // value method master0_ar_arqos assign master0_arqos = core$cpu_imem_master_arqos ; - // value method master0_m_arregion + // value method master0_ar_arregion assign master0_arregion = core$cpu_imem_master_arregion ; - // action method master0_m_arready - assign CAN_FIRE_master0_m_arready = 1'd1 ; - assign WILL_FIRE_master0_m_arready = 1'd1 ; + // value method master0_ar_arvalid + assign master0_arvalid = core$cpu_imem_master_arvalid ; - // action method master0_m_rvalid - assign CAN_FIRE_master0_m_rvalid = 1'd1 ; - assign WILL_FIRE_master0_m_rvalid = 1'd1 ; + // action method master0_ar_arready + assign CAN_FIRE_master0_ar_arready = 1'd1 ; + assign WILL_FIRE_master0_ar_arready = 1'd1 ; - // value method master0_m_rready - assign master0_rready = core$cpu_imem_master_rready ; + // action method master0_r_rflit + assign CAN_FIRE_master0_r_rflit = 1'd1 ; + assign WILL_FIRE_master0_r_rflit = master0_rvalid ; - // value method master1_m_awvalid - assign master1_awvalid = core$cpu_dmem_master_awvalid ; + // value method master0_r_rready + assign master0_rready = core$cpu_imem_master_rready ; - // value method master1_m_awid + // value method master1_aw_awid assign master1_awid = core$cpu_dmem_master_awid ; - // value method master1_m_awaddr + // value method master1_aw_awaddr assign master1_awaddr = core$cpu_dmem_master_awaddr ; - // value method master1_m_awlen + // value method master1_aw_awlen assign master1_awlen = core$cpu_dmem_master_awlen ; - // value method master1_m_awsize + // value method master1_aw_awsize assign master1_awsize = core$cpu_dmem_master_awsize ; - // value method master1_m_awburst + // value method master1_aw_awburst assign master1_awburst = core$cpu_dmem_master_awburst ; - // value method master1_m_awlock + // value method master1_aw_awlock assign master1_awlock = core$cpu_dmem_master_awlock ; - // value method master1_m_awcache + // value method master1_aw_awcache assign master1_awcache = core$cpu_dmem_master_awcache ; - // value method master1_m_awprot + // value method master1_aw_awprot assign master1_awprot = core$cpu_dmem_master_awprot ; - // value method master1_m_awqos + // value method master1_aw_awqos assign master1_awqos = core$cpu_dmem_master_awqos ; - // value method master1_m_awregion + // value method master1_aw_awregion assign master1_awregion = core$cpu_dmem_master_awregion ; - // action method master1_m_awready - assign CAN_FIRE_master1_m_awready = 1'd1 ; - assign WILL_FIRE_master1_m_awready = 1'd1 ; + // value method master1_aw_awvalid + assign master1_awvalid = core$cpu_dmem_master_awvalid ; - // value method master1_m_wvalid - assign master1_wvalid = core$cpu_dmem_master_wvalid ; + // action method master1_aw_awready + assign CAN_FIRE_master1_aw_awready = 1'd1 ; + assign WILL_FIRE_master1_aw_awready = 1'd1 ; - // value method master1_m_wdata + // value method master1_w_wdata assign master1_wdata = core$cpu_dmem_master_wdata ; - // value method master1_m_wstrb + // value method master1_w_wstrb assign master1_wstrb = core$cpu_dmem_master_wstrb ; - // value method master1_m_wlast + // value method master1_w_wlast assign master1_wlast = core$cpu_dmem_master_wlast ; - // action method master1_m_wready - assign CAN_FIRE_master1_m_wready = 1'd1 ; - assign WILL_FIRE_master1_m_wready = 1'd1 ; + // value method master1_w_wvalid + assign master1_wvalid = core$cpu_dmem_master_wvalid ; - // action method master1_m_bvalid - assign CAN_FIRE_master1_m_bvalid = 1'd1 ; - assign WILL_FIRE_master1_m_bvalid = 1'd1 ; + // action method master1_w_wready + assign CAN_FIRE_master1_w_wready = 1'd1 ; + assign WILL_FIRE_master1_w_wready = 1'd1 ; - // value method master1_m_bready - assign master1_bready = core$cpu_dmem_master_bready ; + // action method master1_b_bflit + assign CAN_FIRE_master1_b_bflit = 1'd1 ; + assign WILL_FIRE_master1_b_bflit = master1_bvalid ; - // value method master1_m_arvalid - assign master1_arvalid = core$cpu_dmem_master_arvalid ; + // value method master1_b_bready + assign master1_bready = core$cpu_dmem_master_bready ; - // value method master1_m_arid + // value method master1_ar_arid assign master1_arid = core$cpu_dmem_master_arid ; - // value method master1_m_araddr + // value method master1_ar_araddr assign master1_araddr = core$cpu_dmem_master_araddr ; - // value method master1_m_arlen + // value method master1_ar_arlen assign master1_arlen = core$cpu_dmem_master_arlen ; - // value method master1_m_arsize + // value method master1_ar_arsize assign master1_arsize = core$cpu_dmem_master_arsize ; - // value method master1_m_arburst + // value method master1_ar_arburst assign master1_arburst = core$cpu_dmem_master_arburst ; - // value method master1_m_arlock + // value method master1_ar_arlock assign master1_arlock = core$cpu_dmem_master_arlock ; - // value method master1_m_arcache + // value method master1_ar_arcache assign master1_arcache = core$cpu_dmem_master_arcache ; - // value method master1_m_arprot + // value method master1_ar_arprot assign master1_arprot = core$cpu_dmem_master_arprot ; - // value method master1_m_arqos + // value method master1_ar_arqos assign master1_arqos = core$cpu_dmem_master_arqos ; - // value method master1_m_arregion + // value method master1_ar_arregion assign master1_arregion = core$cpu_dmem_master_arregion ; - // action method master1_m_arready - assign CAN_FIRE_master1_m_arready = 1'd1 ; - assign WILL_FIRE_master1_m_arready = 1'd1 ; + // value method master1_ar_arvalid + assign master1_arvalid = core$cpu_dmem_master_arvalid ; - // action method master1_m_rvalid - assign CAN_FIRE_master1_m_rvalid = 1'd1 ; - assign WILL_FIRE_master1_m_rvalid = 1'd1 ; + // action method master1_ar_arready + assign CAN_FIRE_master1_ar_arready = 1'd1 ; + assign WILL_FIRE_master1_ar_arready = 1'd1 ; - // value method master1_m_rready + // action method master1_r_rflit + assign CAN_FIRE_master1_r_rflit = 1'd1 ; + assign WILL_FIRE_master1_r_rflit = master1_rvalid ; + + // value method master1_r_rready assign master1_rready = core$cpu_dmem_master_rready ; // action method interrupt_reqs @@ -1187,23 +1242,19 @@ module mkP1_Core(CLK, .cpu_dmem_master_awready(core$cpu_dmem_master_awready), .cpu_dmem_master_bid(core$cpu_dmem_master_bid), .cpu_dmem_master_bresp(core$cpu_dmem_master_bresp), - .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), .cpu_dmem_master_rdata(core$cpu_dmem_master_rdata), .cpu_dmem_master_rid(core$cpu_dmem_master_rid), .cpu_dmem_master_rlast(core$cpu_dmem_master_rlast), .cpu_dmem_master_rresp(core$cpu_dmem_master_rresp), - .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), .cpu_dmem_master_wready(core$cpu_dmem_master_wready), .cpu_imem_master_arready(core$cpu_imem_master_arready), .cpu_imem_master_awready(core$cpu_imem_master_awready), .cpu_imem_master_bid(core$cpu_imem_master_bid), .cpu_imem_master_bresp(core$cpu_imem_master_bresp), - .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), .cpu_imem_master_rdata(core$cpu_imem_master_rdata), .cpu_imem_master_rid(core$cpu_imem_master_rid), .cpu_imem_master_rlast(core$cpu_imem_master_rlast), .cpu_imem_master_rresp(core$cpu_imem_master_rresp), - .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), .cpu_imem_master_wready(core$cpu_imem_master_wready), .cpu_reset_server_request_put(core$cpu_reset_server_request_put), .dm_dmi_read_addr_dm_addr(core$dm_dmi_read_addr_dm_addr), @@ -1216,6 +1267,10 @@ module mkP1_Core(CLK, .EN_set_verbosity(core$EN_set_verbosity), .EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put), .EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get), + .cpu_imem_master_bvalid(core$cpu_imem_master_bvalid), + .cpu_imem_master_rvalid(core$cpu_imem_master_rvalid), + .cpu_dmem_master_bvalid(core$cpu_dmem_master_bvalid), + .cpu_dmem_master_rvalid(core$cpu_dmem_master_rvalid), .EN_tv_verifier_info_get_get(core$EN_tv_verifier_info_get_get), .EN_dm_dmi_read_addr(core$EN_dm_dmi_read_addr), .EN_dm_dmi_read_data(core$EN_dm_dmi_read_data), @@ -1226,7 +1281,6 @@ module mkP1_Core(CLK, .RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put), .cpu_reset_server_response_get(core$cpu_reset_server_response_get), .RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get), - .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), .cpu_imem_master_awid(core$cpu_imem_master_awid), .cpu_imem_master_awaddr(core$cpu_imem_master_awaddr), .cpu_imem_master_awlen(core$cpu_imem_master_awlen), @@ -1237,12 +1291,12 @@ module mkP1_Core(CLK, .cpu_imem_master_awprot(core$cpu_imem_master_awprot), .cpu_imem_master_awqos(core$cpu_imem_master_awqos), .cpu_imem_master_awregion(core$cpu_imem_master_awregion), - .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), + .cpu_imem_master_awvalid(core$cpu_imem_master_awvalid), .cpu_imem_master_wdata(core$cpu_imem_master_wdata), .cpu_imem_master_wstrb(core$cpu_imem_master_wstrb), .cpu_imem_master_wlast(core$cpu_imem_master_wlast), + .cpu_imem_master_wvalid(core$cpu_imem_master_wvalid), .cpu_imem_master_bready(core$cpu_imem_master_bready), - .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), .cpu_imem_master_arid(core$cpu_imem_master_arid), .cpu_imem_master_araddr(core$cpu_imem_master_araddr), .cpu_imem_master_arlen(core$cpu_imem_master_arlen), @@ -1253,8 +1307,8 @@ module mkP1_Core(CLK, .cpu_imem_master_arprot(core$cpu_imem_master_arprot), .cpu_imem_master_arqos(core$cpu_imem_master_arqos), .cpu_imem_master_arregion(core$cpu_imem_master_arregion), + .cpu_imem_master_arvalid(core$cpu_imem_master_arvalid), .cpu_imem_master_rready(core$cpu_imem_master_rready), - .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), .cpu_dmem_master_awid(core$cpu_dmem_master_awid), .cpu_dmem_master_awaddr(core$cpu_dmem_master_awaddr), .cpu_dmem_master_awlen(core$cpu_dmem_master_awlen), @@ -1265,12 +1319,12 @@ module mkP1_Core(CLK, .cpu_dmem_master_awprot(core$cpu_dmem_master_awprot), .cpu_dmem_master_awqos(core$cpu_dmem_master_awqos), .cpu_dmem_master_awregion(core$cpu_dmem_master_awregion), - .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), + .cpu_dmem_master_awvalid(core$cpu_dmem_master_awvalid), .cpu_dmem_master_wdata(core$cpu_dmem_master_wdata), .cpu_dmem_master_wstrb(core$cpu_dmem_master_wstrb), .cpu_dmem_master_wlast(core$cpu_dmem_master_wlast), + .cpu_dmem_master_wvalid(core$cpu_dmem_master_wvalid), .cpu_dmem_master_bready(core$cpu_dmem_master_bready), - .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), .cpu_dmem_master_arid(core$cpu_dmem_master_arid), .cpu_dmem_master_araddr(core$cpu_dmem_master_araddr), .cpu_dmem_master_arlen(core$cpu_dmem_master_arlen), @@ -1281,6 +1335,7 @@ module mkP1_Core(CLK, .cpu_dmem_master_arprot(core$cpu_dmem_master_arprot), .cpu_dmem_master_arqos(core$cpu_dmem_master_arqos), .cpu_dmem_master_arregion(core$cpu_dmem_master_arregion), + .cpu_dmem_master_arvalid(core$cpu_dmem_master_arvalid), .cpu_dmem_master_rready(core$cpu_dmem_master_rready), .tv_verifier_info_get_get(core$tv_verifier_info_get_get), .RDY_tv_verifier_info_get_get(core$RDY_tv_verifier_info_get_get), @@ -1417,8 +1472,7 @@ module mkP1_Core(CLK, // rule RL_bus_dmi_rsp_fifof_incCtr assign CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr = - bus_dmi_rsp_fifof_enqueueing$whas && - bus_dmi_rsp_fifof_enqueueing$whas && + bus_dmi_rsp_fifof_x_wire$whas && bus_dmi_rsp_fifof_x_wire$whas && !CAN_FIRE_RL_bus_dmi_rsp_do_deq ; assign WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr = CAN_FIRE_RL_bus_dmi_rsp_fifof_incCtr ; @@ -1426,15 +1480,15 @@ module mkP1_Core(CLK, // rule RL_bus_dmi_rsp_fifof_decCtr assign CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr = CAN_FIRE_RL_bus_dmi_rsp_do_deq && - !bus_dmi_rsp_fifof_enqueueing$whas ; + !bus_dmi_rsp_fifof_x_wire$whas ; assign WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr = CAN_FIRE_RL_bus_dmi_rsp_fifof_decCtr ; // rule RL_bus_dmi_rsp_fifof_both assign CAN_FIRE_RL_bus_dmi_rsp_fifof_both = - bus_dmi_rsp_fifof_enqueueing$whas && + bus_dmi_rsp_fifof_x_wire$whas && CAN_FIRE_RL_bus_dmi_rsp_do_deq && - bus_dmi_rsp_fifof_enqueueing$whas ; + bus_dmi_rsp_fifof_x_wire$whas ; assign WILL_FIRE_RL_bus_dmi_rsp_fifof_both = CAN_FIRE_RL_bus_dmi_rsp_fifof_both ; @@ -1475,7 +1529,7 @@ module mkP1_Core(CLK, { 1'd1, core$ndm_reset_client_request_get } ; // inlined wires - assign bus_dmi_rsp_fifof_enqueueing$whas = + assign bus_dmi_rsp_fifof_x_wire$whas = WILL_FIRE_RL_rl_dmi_req_cpu && bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 || WILL_FIRE_RL_rl_dmi_rsp_cpu ; @@ -1600,23 +1654,19 @@ module mkP1_Core(CLK, assign core$cpu_dmem_master_awready = master1_awready ; assign core$cpu_dmem_master_bid = master1_bid ; assign core$cpu_dmem_master_bresp = master1_bresp ; - assign core$cpu_dmem_master_bvalid = master1_bvalid ; assign core$cpu_dmem_master_rdata = master1_rdata ; assign core$cpu_dmem_master_rid = master1_rid ; assign core$cpu_dmem_master_rlast = master1_rlast ; assign core$cpu_dmem_master_rresp = master1_rresp ; - assign core$cpu_dmem_master_rvalid = master1_rvalid ; assign core$cpu_dmem_master_wready = master1_wready ; assign core$cpu_imem_master_arready = master0_arready ; assign core$cpu_imem_master_awready = master0_awready ; assign core$cpu_imem_master_bid = master0_bid ; assign core$cpu_imem_master_bresp = master0_bresp ; - assign core$cpu_imem_master_bvalid = master0_bvalid ; assign core$cpu_imem_master_rdata = master0_rdata ; assign core$cpu_imem_master_rid = master0_rid ; assign core$cpu_imem_master_rlast = master0_rlast ; assign core$cpu_imem_master_rresp = master0_rresp ; - assign core$cpu_imem_master_rvalid = master0_rvalid ; assign core$cpu_imem_master_wready = master0_wready ; assign core$cpu_reset_server_request_put = !rg_ndm_reset[1] || rg_ndm_reset[0] ; @@ -1632,6 +1682,10 @@ module mkP1_Core(CLK, assign core$EN_cpu_reset_server_request_put = CAN_FIRE_RL_rl_once ; assign core$EN_cpu_reset_server_response_get = CAN_FIRE_RL_rl_reset_response ; + assign core$cpu_imem_master_bvalid = master0_bvalid ; + assign core$cpu_imem_master_rvalid = master0_rvalid ; + assign core$cpu_dmem_master_bvalid = master1_bvalid ; + assign core$cpu_dmem_master_rvalid = master1_rvalid ; assign core$EN_tv_verifier_info_get_get = CAN_FIRE_RL_mkConnectionGetPut ; assign core$EN_dm_dmi_read_addr = WILL_FIRE_RL_rl_dmi_req_cpu && diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkPLIC_16_2_7.v b/src_SSITH_P1/xilinx_ip/hdl/mkPLIC_16_2_7.v index f727e005..2ec7e3a0 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkPLIC_16_2_7.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:26 BST 2019 // // // Ports: @@ -11,17 +11,17 @@ // RDY_server_reset_request_put O 1 reg // RDY_server_reset_response_get O 1 reg // RDY_set_addr_map O 1 const -// axi4_slave_awready O 1 reg -// axi4_slave_wready O 1 reg -// axi4_slave_bvalid O 1 reg -// axi4_slave_bid O 4 reg -// axi4_slave_bresp O 2 reg -// axi4_slave_arready O 1 reg -// axi4_slave_rvalid O 1 reg -// axi4_slave_rid O 4 reg -// axi4_slave_rdata O 64 reg -// axi4_slave_rresp O 2 reg -// axi4_slave_rlast O 1 reg +// axi4_slave_awready O 1 +// axi4_slave_wready O 1 +// axi4_slave_bid O 5 +// axi4_slave_bresp O 2 +// axi4_slave_bvalid O 1 +// axi4_slave_arready O 1 +// axi4_slave_rid O 5 +// axi4_slave_rdata O 64 +// axi4_slave_rresp O 2 +// axi4_slave_rlast O 1 +// axi4_slave_rvalid O 1 // v_targets_0_m_eip O 1 // v_targets_1_m_eip O 1 // CLK I 1 clock @@ -29,33 +29,30 @@ // set_verbosity_verbosity I 4 reg // set_addr_map_addr_base I 64 reg // set_addr_map_addr_lim I 64 reg -// axi4_slave_awvalid I 1 -// axi4_slave_awid I 4 reg -// axi4_slave_awaddr I 64 reg -// axi4_slave_awlen I 8 reg -// axi4_slave_awsize I 3 reg -// axi4_slave_awburst I 2 reg -// axi4_slave_awlock I 1 reg -// axi4_slave_awcache I 4 reg -// axi4_slave_awprot I 3 reg -// axi4_slave_awqos I 4 reg -// axi4_slave_awregion I 4 reg -// axi4_slave_wvalid I 1 -// axi4_slave_wdata I 64 reg -// axi4_slave_wstrb I 8 reg -// axi4_slave_wlast I 1 reg +// axi4_slave_awid I 5 +// axi4_slave_awaddr I 64 +// axi4_slave_awlen I 8 +// axi4_slave_awsize I 3 +// axi4_slave_awburst I 2 +// axi4_slave_awlock I 1 +// axi4_slave_awcache I 4 +// axi4_slave_awprot I 3 +// axi4_slave_awqos I 4 +// axi4_slave_awregion I 4 +// axi4_slave_wdata I 64 +// axi4_slave_wstrb I 8 +// axi4_slave_wlast I 1 // axi4_slave_bready I 1 -// axi4_slave_arvalid I 1 -// axi4_slave_arid I 4 reg -// axi4_slave_araddr I 64 reg -// axi4_slave_arlen I 8 reg -// axi4_slave_arsize I 3 reg -// axi4_slave_arburst I 2 reg -// axi4_slave_arlock I 1 reg -// axi4_slave_arcache I 4 reg -// axi4_slave_arprot I 3 reg -// axi4_slave_arqos I 4 reg -// axi4_slave_arregion I 4 reg +// axi4_slave_arid I 5 +// axi4_slave_araddr I 64 +// axi4_slave_arlen I 8 +// axi4_slave_arsize I 3 +// axi4_slave_arburst I 2 +// axi4_slave_arlock I 1 +// axi4_slave_arcache I 4 +// axi4_slave_arprot I 3 +// axi4_slave_arqos I 4 +// axi4_slave_arregion I 4 // axi4_slave_rready I 1 // v_sources_0_m_interrupt_req_set_not_clear I 1 // v_sources_1_m_interrupt_req_set_not_clear I 1 @@ -78,8 +75,181 @@ // EN_server_reset_request_put I 1 // EN_server_reset_response_get I 1 // EN_set_addr_map I 1 +// axi4_slave_awvalid I 1 +// axi4_slave_wvalid I 1 +// axi4_slave_arvalid I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_awvalid, +// axi4_slave_wvalid, +// axi4_slave_arvalid) -> axi4_slave_bid +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_awvalid, +// axi4_slave_wvalid, +// axi4_slave_arvalid) -> axi4_slave_bresp +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_awvalid, +// axi4_slave_wvalid, +// axi4_slave_arvalid) -> axi4_slave_buser +// (axi4_slave_awid, +// axi4_slave_awaddr, +// axi4_slave_awlen, +// axi4_slave_awsize, +// axi4_slave_awburst, +// axi4_slave_awlock, +// axi4_slave_awcache, +// axi4_slave_awprot, +// axi4_slave_awqos, +// axi4_slave_awregion, +// axi4_slave_wdata, +// axi4_slave_wstrb, +// axi4_slave_wlast, +// axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_awvalid, +// axi4_slave_wvalid, +// axi4_slave_arvalid) -> axi4_slave_bvalid +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rid +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rdata +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rresp +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rlast +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_ruser +// (axi4_slave_arid, +// axi4_slave_araddr, +// axi4_slave_arlen, +// axi4_slave_arsize, +// axi4_slave_arburst, +// axi4_slave_arlock, +// axi4_slave_arcache, +// axi4_slave_arprot, +// axi4_slave_arqos, +// axi4_slave_arregion, +// axi4_slave_arvalid) -> axi4_slave_rvalid // // @@ -117,7 +287,6 @@ module mkPLIC_16_2_7(CLK, EN_set_addr_map, RDY_set_addr_map, - axi4_slave_awvalid, axi4_slave_awid, axi4_slave_awaddr, axi4_slave_awlen, @@ -128,25 +297,25 @@ module mkPLIC_16_2_7(CLK, axi4_slave_awprot, axi4_slave_awqos, axi4_slave_awregion, + axi4_slave_awvalid, axi4_slave_awready, - axi4_slave_wvalid, axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast, + axi4_slave_wvalid, axi4_slave_wready, - axi4_slave_bvalid, - axi4_slave_bid, axi4_slave_bresp, + axi4_slave_bvalid, + axi4_slave_bready, - axi4_slave_arvalid, axi4_slave_arid, axi4_slave_araddr, axi4_slave_arlen, @@ -157,11 +326,10 @@ module mkPLIC_16_2_7(CLK, axi4_slave_arprot, axi4_slave_arqos, axi4_slave_arregion, + axi4_slave_arvalid, axi4_slave_arready, - axi4_slave_rvalid, - axi4_slave_rid, axi4_slave_rdata, @@ -170,6 +338,8 @@ module mkPLIC_16_2_7(CLK, axi4_slave_rlast, + axi4_slave_rvalid, + axi4_slave_rready, v_sources_0_m_interrupt_req_set_not_clear, @@ -233,9 +403,8 @@ module mkPLIC_16_2_7(CLK, input EN_set_addr_map; output RDY_set_addr_map; - // action method axi4_slave_m_awvalid - input axi4_slave_awvalid; - input [3 : 0] axi4_slave_awid; + // action method axi4_slave_aw_awflit + input [4 : 0] axi4_slave_awid; input [63 : 0] axi4_slave_awaddr; input [7 : 0] axi4_slave_awlen; input [2 : 0] axi4_slave_awsize; @@ -245,36 +414,36 @@ module mkPLIC_16_2_7(CLK, input [2 : 0] axi4_slave_awprot; input [3 : 0] axi4_slave_awqos; input [3 : 0] axi4_slave_awregion; + input axi4_slave_awvalid; - // value method axi4_slave_m_awready + // value method axi4_slave_aw_awready output axi4_slave_awready; - // action method axi4_slave_m_wvalid - input axi4_slave_wvalid; + // action method axi4_slave_w_wflit input [63 : 0] axi4_slave_wdata; input [7 : 0] axi4_slave_wstrb; input axi4_slave_wlast; + input axi4_slave_wvalid; - // value method axi4_slave_m_wready + // value method axi4_slave_w_wready output axi4_slave_wready; - // value method axi4_slave_m_bvalid - output axi4_slave_bvalid; - - // value method axi4_slave_m_bid - output [3 : 0] axi4_slave_bid; + // value method axi4_slave_b_bid + output [4 : 0] axi4_slave_bid; - // value method axi4_slave_m_bresp + // value method axi4_slave_b_bresp output [1 : 0] axi4_slave_bresp; - // value method axi4_slave_m_buser + // value method axi4_slave_b_buser + + // value method axi4_slave_b_bvalid + output axi4_slave_bvalid; - // action method axi4_slave_m_bready + // action method axi4_slave_b_bready input axi4_slave_bready; - // action method axi4_slave_m_arvalid - input axi4_slave_arvalid; - input [3 : 0] axi4_slave_arid; + // action method axi4_slave_ar_arflit + input [4 : 0] axi4_slave_arid; input [63 : 0] axi4_slave_araddr; input [7 : 0] axi4_slave_arlen; input [2 : 0] axi4_slave_arsize; @@ -284,28 +453,29 @@ module mkPLIC_16_2_7(CLK, input [2 : 0] axi4_slave_arprot; input [3 : 0] axi4_slave_arqos; input [3 : 0] axi4_slave_arregion; + input axi4_slave_arvalid; - // value method axi4_slave_m_arready + // value method axi4_slave_ar_arready output axi4_slave_arready; - // value method axi4_slave_m_rvalid - output axi4_slave_rvalid; - - // value method axi4_slave_m_rid - output [3 : 0] axi4_slave_rid; + // value method axi4_slave_r_rid + output [4 : 0] axi4_slave_rid; - // value method axi4_slave_m_rdata + // value method axi4_slave_r_rdata output [63 : 0] axi4_slave_rdata; - // value method axi4_slave_m_rresp + // value method axi4_slave_r_rresp output [1 : 0] axi4_slave_rresp; - // value method axi4_slave_m_rlast + // value method axi4_slave_r_rlast output axi4_slave_rlast; - // value method axi4_slave_m_ruser + // value method axi4_slave_r_ruser + + // value method axi4_slave_r_rvalid + output axi4_slave_rvalid; - // action method axi4_slave_m_rready + // action method axi4_slave_r_rready input axi4_slave_rready; // action method v_sources_0_m_interrupt_req @@ -364,7 +534,7 @@ module mkPLIC_16_2_7(CLK, // signals for module outputs wire [63 : 0] axi4_slave_rdata; - wire [3 : 0] axi4_slave_bid, axi4_slave_rid; + wire [4 : 0] axi4_slave_bid, axi4_slave_rid; wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp; wire RDY_server_reset_request_put, RDY_server_reset_response_get, @@ -380,6 +550,36 @@ module mkPLIC_16_2_7(CLK, v_targets_0_m_eip, v_targets_1_m_eip; + // inlined wires + wire [98 : 0] m_slave_xactor_shim_arff_rv$port0__write_1, + m_slave_xactor_shim_arff_rv$port1__read, + m_slave_xactor_shim_arff_rv$port2__read, + m_slave_xactor_shim_arff_rv$port3__read, + m_slave_xactor_shim_awff_rv$port0__write_1, + m_slave_xactor_shim_awff_rv$port1__read, + m_slave_xactor_shim_awff_rv$port2__read, + m_slave_xactor_shim_awff_rv$port3__read; + wire [97 : 0] m_slave_xactor_ug_slave_u_ar_putWire$wget, + m_slave_xactor_ug_slave_u_aw_putWire$wget; + wire [73 : 0] m_slave_xactor_shim_wff_rv$port0__write_1, + m_slave_xactor_shim_wff_rv$port1__read, + m_slave_xactor_shim_wff_rv$port2__read, + m_slave_xactor_shim_wff_rv$port3__read; + wire [72 : 0] m_slave_xactor_shim_rff_rv$port0__write_1, + m_slave_xactor_shim_rff_rv$port1__read, + m_slave_xactor_shim_rff_rv$port2__read, + m_slave_xactor_shim_rff_rv$port3__read, + m_slave_xactor_ug_slave_u_w_putWire$wget; + wire [7 : 0] m_slave_xactor_shim_bff_rv$port0__write_1, + m_slave_xactor_shim_bff_rv$port1__read, + m_slave_xactor_shim_bff_rv$port2__read, + m_slave_xactor_shim_bff_rv$port3__read; + wire m_slave_xactor_ug_slave_u_ar_putWire$whas, + m_slave_xactor_ug_slave_u_aw_putWire$whas, + m_slave_xactor_ug_slave_u_b_dropWire$whas, + m_slave_xactor_ug_slave_u_r_dropWire$whas, + m_slave_xactor_ug_slave_u_w_putWire$whas; + // register m_cfg_verbosity reg [3 : 0] m_cfg_verbosity; wire [3 : 0] m_cfg_verbosity$D_IN; @@ -395,6 +595,35 @@ module mkPLIC_16_2_7(CLK, wire [63 : 0] m_rg_addr_lim$D_IN; wire m_rg_addr_lim$EN; + // register m_slave_xactor_clearing + reg m_slave_xactor_clearing; + wire m_slave_xactor_clearing$D_IN, m_slave_xactor_clearing$EN; + + // register m_slave_xactor_shim_arff_rv + reg [98 : 0] m_slave_xactor_shim_arff_rv; + wire [98 : 0] m_slave_xactor_shim_arff_rv$D_IN; + wire m_slave_xactor_shim_arff_rv$EN; + + // register m_slave_xactor_shim_awff_rv + reg [98 : 0] m_slave_xactor_shim_awff_rv; + wire [98 : 0] m_slave_xactor_shim_awff_rv$D_IN; + wire m_slave_xactor_shim_awff_rv$EN; + + // register m_slave_xactor_shim_bff_rv + reg [7 : 0] m_slave_xactor_shim_bff_rv; + wire [7 : 0] m_slave_xactor_shim_bff_rv$D_IN; + wire m_slave_xactor_shim_bff_rv$EN; + + // register m_slave_xactor_shim_rff_rv + reg [72 : 0] m_slave_xactor_shim_rff_rv; + wire [72 : 0] m_slave_xactor_shim_rff_rv$D_IN; + wire m_slave_xactor_shim_rff_rv$EN; + + // register m_slave_xactor_shim_wff_rv + reg [73 : 0] m_slave_xactor_shim_wff_rv; + wire [73 : 0] m_slave_xactor_shim_wff_rv$D_IN; + wire m_slave_xactor_shim_wff_rv$EN; + // register m_vrg_servicing_source_0 reg [4 : 0] m_vrg_servicing_source_0; wire [4 : 0] m_vrg_servicing_source_0$D_IN; @@ -786,55 +1015,28 @@ module mkPLIC_16_2_7(CLK, m_f_reset_rsps$ENQ, m_f_reset_rsps$FULL_N; - // ports of submodule m_slave_xactor_f_rd_addr - wire [96 : 0] m_slave_xactor_f_rd_addr$D_IN, m_slave_xactor_f_rd_addr$D_OUT; - wire m_slave_xactor_f_rd_addr$CLR, - m_slave_xactor_f_rd_addr$DEQ, - m_slave_xactor_f_rd_addr$EMPTY_N, - m_slave_xactor_f_rd_addr$ENQ, - m_slave_xactor_f_rd_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_rd_data - wire [70 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT; - wire m_slave_xactor_f_rd_data$CLR, - m_slave_xactor_f_rd_data$DEQ, - m_slave_xactor_f_rd_data$EMPTY_N, - m_slave_xactor_f_rd_data$ENQ, - m_slave_xactor_f_rd_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_addr - wire [96 : 0] m_slave_xactor_f_wr_addr$D_IN, m_slave_xactor_f_wr_addr$D_OUT; - wire m_slave_xactor_f_wr_addr$CLR, - m_slave_xactor_f_wr_addr$DEQ, - m_slave_xactor_f_wr_addr$EMPTY_N, - m_slave_xactor_f_wr_addr$ENQ, - m_slave_xactor_f_wr_addr$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_data - wire [72 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT; - wire m_slave_xactor_f_wr_data$CLR, - m_slave_xactor_f_wr_data$DEQ, - m_slave_xactor_f_wr_data$EMPTY_N, - m_slave_xactor_f_wr_data$ENQ, - m_slave_xactor_f_wr_data$FULL_N; - - // ports of submodule m_slave_xactor_f_wr_resp - wire [5 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT; - wire m_slave_xactor_f_wr_resp$CLR, - m_slave_xactor_f_wr_resp$DEQ, - m_slave_xactor_f_wr_resp$EMPTY_N, - m_slave_xactor_f_wr_resp$ENQ, - m_slave_xactor_f_wr_resp$FULL_N; - // rule scheduling signals wire CAN_FIRE_RL_m_rl_process_rd_req, CAN_FIRE_RL_m_rl_process_wr_req, CAN_FIRE_RL_m_rl_reset, - CAN_FIRE_axi4_slave_m_arvalid, - CAN_FIRE_axi4_slave_m_awvalid, - CAN_FIRE_axi4_slave_m_bready, - CAN_FIRE_axi4_slave_m_rready, - CAN_FIRE_axi4_slave_m_wvalid, + CAN_FIRE_RL_m_slave_xactor_do_clear, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut, + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut, + CAN_FIRE_axi4_slave_ar_arflit, + CAN_FIRE_axi4_slave_aw_awflit, + CAN_FIRE_axi4_slave_b_bready, + CAN_FIRE_axi4_slave_r_rready, + CAN_FIRE_axi4_slave_w_wflit, CAN_FIRE_server_reset_request_put, CAN_FIRE_server_reset_response_get, CAN_FIRE_set_addr_map, @@ -859,11 +1061,24 @@ module mkPLIC_16_2_7(CLK, WILL_FIRE_RL_m_rl_process_rd_req, WILL_FIRE_RL_m_rl_process_wr_req, WILL_FIRE_RL_m_rl_reset, - WILL_FIRE_axi4_slave_m_arvalid, - WILL_FIRE_axi4_slave_m_awvalid, - WILL_FIRE_axi4_slave_m_bready, - WILL_FIRE_axi4_slave_m_rready, - WILL_FIRE_axi4_slave_m_wvalid, + WILL_FIRE_RL_m_slave_xactor_do_clear, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut, + WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut, + WILL_FIRE_axi4_slave_ar_arflit, + WILL_FIRE_axi4_slave_aw_awflit, + WILL_FIRE_axi4_slave_b_bready, + WILL_FIRE_axi4_slave_r_rready, + WILL_FIRE_axi4_slave_w_wflit, WILL_FIRE_server_reset_request_put, WILL_FIRE_server_reset_response_get, WILL_FIRE_set_addr_map, @@ -1012,516 +1227,509 @@ module mkPLIC_16_2_7(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h75659; - reg [31 : 0] v__h75857; - reg [31 : 0] v__h76055; - reg [31 : 0] v__h76253; - reg [31 : 0] v__h76451; - reg [31 : 0] v__h76649; - reg [31 : 0] v__h76847; - reg [31 : 0] v__h77045; - reg [31 : 0] v__h77243; - reg [31 : 0] v__h77441; - reg [31 : 0] v__h77639; - reg [31 : 0] v__h77837; - reg [31 : 0] v__h78035; - reg [31 : 0] v__h78233; - reg [31 : 0] v__h78431; - reg [31 : 0] v__h78629; - reg [31 : 0] v__h6142; - reg [31 : 0] v__h13078; - reg [31 : 0] v__h13263; - reg [31 : 0] v__h13461; - reg [31 : 0] v__h13711; - reg [31 : 0] v__h18184; - reg [31 : 0] v__h23800; - reg [31 : 0] v__h25973; - reg [31 : 0] v__h24054; - reg [31 : 0] v__h26248; - reg [31 : 0] v__h26461; - reg [31 : 0] v__h26735; - reg [31 : 0] v__h26959; - reg [31 : 0] v__h27854; - reg [31 : 0] v__h28037; - reg [31 : 0] v__h67019; - reg [31 : 0] v__h67307; - reg [31 : 0] v__h67836; - reg [31 : 0] v__h67922; - reg [31 : 0] v__h68121; - reg [31 : 0] v__h68340; - reg [31 : 0] v__h74675; - reg [31 : 0] v__h74785; - reg [31 : 0] v__h74898; - reg [31 : 0] v__h6136; - reg [31 : 0] v__h13072; - reg [31 : 0] v__h13257; - reg [31 : 0] v__h13455; - reg [31 : 0] v__h13705; - reg [31 : 0] v__h18178; - reg [31 : 0] v__h23794; - reg [31 : 0] v__h24048; - reg [31 : 0] v__h25967; - reg [31 : 0] v__h26242; - reg [31 : 0] v__h26455; - reg [31 : 0] v__h26729; - reg [31 : 0] v__h26953; - reg [31 : 0] v__h27848; - reg [31 : 0] v__h28031; - reg [31 : 0] v__h67013; - reg [31 : 0] v__h67301; - reg [31 : 0] v__h67830; - reg [31 : 0] v__h67916; - reg [31 : 0] v__h68115; - reg [31 : 0] v__h68334; - reg [31 : 0] v__h74669; - reg [31 : 0] v__h74779; - reg [31 : 0] v__h74892; - reg [31 : 0] v__h75653; - reg [31 : 0] v__h75851; - reg [31 : 0] v__h76049; - reg [31 : 0] v__h76247; - reg [31 : 0] v__h76445; - reg [31 : 0] v__h76643; - reg [31 : 0] v__h76841; - reg [31 : 0] v__h77039; - reg [31 : 0] v__h77237; - reg [31 : 0] v__h77435; - reg [31 : 0] v__h77633; - reg [31 : 0] v__h77831; - reg [31 : 0] v__h78029; - reg [31 : 0] v__h78227; - reg [31 : 0] v__h78425; - reg [31 : 0] v__h78623; + reg [31 : 0] v__h78778; + reg [31 : 0] v__h78976; + reg [31 : 0] v__h79174; + reg [31 : 0] v__h79372; + reg [31 : 0] v__h79570; + reg [31 : 0] v__h79768; + reg [31 : 0] v__h79966; + reg [31 : 0] v__h80164; + reg [31 : 0] v__h80362; + reg [31 : 0] v__h80560; + reg [31 : 0] v__h80758; + reg [31 : 0] v__h80956; + reg [31 : 0] v__h81154; + reg [31 : 0] v__h81352; + reg [31 : 0] v__h81550; + reg [31 : 0] v__h81748; + reg [31 : 0] v__h8559; + reg [31 : 0] v__h15481; + reg [31 : 0] v__h15696; + reg [31 : 0] v__h15924; + reg [31 : 0] v__h16175; + reg [31 : 0] v__h20649; + reg [31 : 0] v__h26266; + reg [31 : 0] v__h28442; + reg [31 : 0] v__h26522; + reg [31 : 0] v__h28733; + reg [31 : 0] v__h29034; + reg [31 : 0] v__h29518; + reg [31 : 0] v__h29772; + reg [31 : 0] v__h30696; + reg [31 : 0] v__h30882; + reg [31 : 0] v__h69866; + reg [31 : 0] v__h70156; + reg [31 : 0] v__h70688; + reg [31 : 0] v__h70774; + reg [31 : 0] v__h70985; + reg [31 : 0] v__h71294; + reg [31 : 0] v__h77734; + reg [31 : 0] v__h77844; + reg [31 : 0] v__h77957; + reg [31 : 0] v__h8553; + reg [31 : 0] v__h15475; + reg [31 : 0] v__h15690; + reg [31 : 0] v__h15918; + reg [31 : 0] v__h16169; + reg [31 : 0] v__h20643; + reg [31 : 0] v__h26260; + reg [31 : 0] v__h26516; + reg [31 : 0] v__h28436; + reg [31 : 0] v__h28727; + reg [31 : 0] v__h29028; + reg [31 : 0] v__h29512; + reg [31 : 0] v__h29766; + reg [31 : 0] v__h30690; + reg [31 : 0] v__h30876; + reg [31 : 0] v__h69860; + reg [31 : 0] v__h70150; + reg [31 : 0] v__h70682; + reg [31 : 0] v__h70768; + reg [31 : 0] v__h70979; + reg [31 : 0] v__h71288; + reg [31 : 0] v__h77728; + reg [31 : 0] v__h77838; + reg [31 : 0] v__h77951; + reg [31 : 0] v__h78772; + reg [31 : 0] v__h78970; + reg [31 : 0] v__h79168; + reg [31 : 0] v__h79366; + reg [31 : 0] v__h79564; + reg [31 : 0] v__h79762; + reg [31 : 0] v__h79960; + reg [31 : 0] v__h80158; + reg [31 : 0] v__h80356; + reg [31 : 0] v__h80554; + reg [31 : 0] v__h80752; + reg [31 : 0] v__h80950; + reg [31 : 0] v__h81148; + reg [31 : 0] v__h81346; + reg [31 : 0] v__h81544; + reg [31 : 0] v__h81742; // synopsys translate_on // remaining internal signals - reg [63 : 0] y_avValue_fst__h26146; - reg [4 : 0] x__h24009, x__h67476; - reg [2 : 0] x__h13491, x__h23830; - reg [1 : 0] v__h67096, y_avValue_snd__h26147; - reg CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235, - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514, - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515, - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - wire [63 : 0] addr_offset__h13214, - addr_offset__h26920, - rdata___1__h26402, - rdata__h26200, - v__h13420, - v__h13669, - v__h18142, - v__h23759, - v__h25453, - v__h25472, - x__h26359, - y_avValue_fst__h26092, - y_avValue_fst__h26113, - y_avValue_fst__h26125, - y_avValue_fst__h26141, - y_avValue_fst__h26157, - y_avValue_fst__h26162, - y_avValue_fst__h26173, - y_avValue_fst__h26178, - y_avValue_fst__h26192; - wire [31 : 0] v_ie__h18145, - v_ip__h13672, - wdata32__h26921, - x__h23671, - x__h67099; - wire [9 : 0] source_id__h15663, - source_id__h15770, - source_id__h15843, - source_id__h15916, - source_id__h15989, - source_id__h16062, - source_id__h16135, - source_id__h16208, - source_id__h16281, - source_id__h16354, - source_id__h16427, - source_id__h16500, - source_id__h16573, - source_id__h16646, - source_id__h16719, - source_id__h16792, - source_id__h16865, - source_id__h16938, - source_id__h17011, - source_id__h17084, - source_id__h17157, - source_id__h17230, - source_id__h17303, - source_id__h17376, - source_id__h17449, - source_id__h17522, - source_id__h17595, - source_id__h17668, - source_id__h17741, - source_id__h17814, - source_id__h17887, - source_id__h20135, - source_id__h20311, - source_id__h20419, - source_id__h20527, - source_id__h20635, - source_id__h20743, - source_id__h20851, - source_id__h20959, - source_id__h21067, - source_id__h21175, - source_id__h21283, - source_id__h21391, - source_id__h21499, - source_id__h21607, - source_id__h21715, - source_id__h21823, - source_id__h21931, - source_id__h22039, - source_id__h22147, - source_id__h22255, - source_id__h22363, - source_id__h22471, - source_id__h22579, - source_id__h22687, - source_id__h22795, - source_id__h22903, - source_id__h23011, - source_id__h23119, - source_id__h23227, - source_id__h23335, - source_id__h23443, - source_id__h29464, - source_id__h30674, - source_id__h31884, - source_id__h33094, - source_id__h34304, - source_id__h35514, - source_id__h36724, - source_id__h37934, - source_id__h39144, - source_id__h40354, - source_id__h41564, - source_id__h42774, - source_id__h43984, - source_id__h45194, - source_id__h46404, - source_id__h47614, - source_id__h48824, - source_id__h50034, - source_id__h51244, - source_id__h52454, - source_id__h53664, - source_id__h54874, - source_id__h56084, - source_id__h57294, - source_id__h58504, - source_id__h59714, - source_id__h60924, - source_id__h62134, - source_id__h63344, - source_id__h64554, - source_id__h65764, - source_id__h67425, - source_id_base__h13628, - source_id_base__h28137; - wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665, - b__h71298, - b__h73303, - max_id__h23957; - wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154, - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159, - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164, - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169, - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174, - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085, - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109, - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114, - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119, - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124, - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129, - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134, - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139, - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144, - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149, - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608, - a__h71297, - a__h73302; - wire [1 : 0] rresp__h26201, - v__h26925, - v__h27083, - v__h27096, - v__h27931, - v__h27950, - v__h28114, - v__h28133, - v__h67133, - v__h67421, - v__h67465, - y_avValue_snd__h26093, - y_avValue_snd__h26114, - y_avValue_snd__h26126, - y_avValue_snd__h26142, - y_avValue_snd__h26158, - y_avValue_snd__h26163, - y_avValue_snd__h26174, - y_avValue_snd__h26179, - y_avValue_snd__h26193; - wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769, - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988, - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990, - NOT_m_cfg_verbosity_read_ULE_1_5___d16, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744, - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917, - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981, - NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311, - NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319, - NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327, - NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335, - NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343, - NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351, - NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359, - NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240, - NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247, - NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255, - NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263, - NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271, - NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279, - NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287, - NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295, - NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303, + reg [63 : 0] y_avValue_fst__h28615; + reg [4 : 0] x__h26477, x__h70328; + reg [2 : 0] x__h15954, x__h26296; + reg [1 : 0] CASE_x6136_0x200000_IF_m_slave_xactor_shim_arf_ETC__q50, + CASE_x9947_0x200000_IF_m_slave_xactor_shim_awf_ETC__q1; + reg CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q33, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48, + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q49, + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302, + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583, + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584, + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589; + wire [71 : 0] m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52; + wire [63 : 0] addr_offset__h15646, + addr_offset__h29732, + rdata___1__h28973, + rdata__h28669, + v__h15883, + v__h16133, + v__h20607, + v__h26225, + v__h27922, + v__h27941, + x__h28872, + y_avValue_fst__h28561, + y_avValue_fst__h28582, + y_avValue_fst__h28594, + y_avValue_fst__h28610, + y_avValue_fst__h28626, + y_avValue_fst__h28631, + y_avValue_fst__h28642, + y_avValue_fst__h28647, + y_avValue_fst__h28661; + wire [31 : 0] v_ie__h20610, + v_ip__h16136, + wdata32__h29733, + x__h26136, + x__h69947; + wire [9 : 0] source_id__h18127, + source_id__h18234, + source_id__h18307, + source_id__h18380, + source_id__h18453, + source_id__h18526, + source_id__h18599, + source_id__h18672, + source_id__h18745, + source_id__h18818, + source_id__h18891, + source_id__h18964, + source_id__h19037, + source_id__h19110, + source_id__h19183, + source_id__h19256, + source_id__h19329, + source_id__h19402, + source_id__h19475, + source_id__h19548, + source_id__h19621, + source_id__h19694, + source_id__h19767, + source_id__h19840, + source_id__h19913, + source_id__h19986, + source_id__h20059, + source_id__h20132, + source_id__h20205, + source_id__h20278, + source_id__h20351, + source_id__h22600, + source_id__h22776, + source_id__h22884, + source_id__h22992, + source_id__h23100, + source_id__h23208, + source_id__h23316, + source_id__h23424, + source_id__h23532, + source_id__h23640, + source_id__h23748, + source_id__h23856, + source_id__h23964, + source_id__h24072, + source_id__h24180, + source_id__h24288, + source_id__h24396, + source_id__h24504, + source_id__h24612, + source_id__h24720, + source_id__h24828, + source_id__h24936, + source_id__h25044, + source_id__h25152, + source_id__h25260, + source_id__h25368, + source_id__h25476, + source_id__h25584, + source_id__h25692, + source_id__h25800, + source_id__h25908, + source_id__h32311, + source_id__h33521, + source_id__h34731, + source_id__h35941, + source_id__h37151, + source_id__h38361, + source_id__h39571, + source_id__h40781, + source_id__h41991, + source_id__h43201, + source_id__h44411, + source_id__h45621, + source_id__h46831, + source_id__h48041, + source_id__h49251, + source_id__h50461, + source_id__h51671, + source_id__h52881, + source_id__h54091, + source_id__h55301, + source_id__h56511, + source_id__h57721, + source_id__h58931, + source_id__h60141, + source_id__h61351, + source_id__h62561, + source_id__h63771, + source_id__h64981, + source_id__h66191, + source_id__h67401, + source_id__h68611, + source_id__h70276, + source_id_base__h16091, + source_id_base__h30983; + wire [6 : 0] m_slave_xactor_shim_bff_rvport1__read_BITS_6__ETC__q51; + wire [4 : 0] IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3228, + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3322, + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d736, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3230, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3324, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d738, + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3232, + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3326, + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d740, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3220, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3314, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d728, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3222, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3316, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d730, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3224, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3318, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d732, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3226, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3320, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d734, + b__h74357, + b__h76362, + max_id__h26424; + wire [2 : 0] IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3187, + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3281, + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d684, + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3192, + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3286, + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d691, + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3197, + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3291, + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d698, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3202, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3296, + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d705, + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3207, + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3301, + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d712, + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3212, + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3306, + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3142, + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3236, + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d621, + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3147, + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3241, + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d628, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3152, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3246, + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d635, + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3157, + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3251, + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d642, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3162, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3256, + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d649, + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3167, + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3261, + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d656, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3172, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3266, + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d663, + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3177, + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3271, + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d670, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3182, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3276, + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d677, + a__h74356, + a__h76361; + wire [1 : 0] IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d878, + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d879, + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d880, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3122, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3123, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3124; + wire IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d838, + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840, + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d889, + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d891, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3100, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3130, + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3132, + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d143, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d317, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d607, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d813, + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1017, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1029, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2981, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2994, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3005, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3077, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087, + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d963, + NOT_m_vrg_source_busy_10_022_434_AND_NOT_m_cfg_ETC___d3438, + NOT_m_vrg_source_busy_11_023_442_AND_NOT_m_cfg_ETC___d3446, + NOT_m_vrg_source_busy_12_024_450_AND_NOT_m_cfg_ETC___d3454, + NOT_m_vrg_source_busy_13_025_458_AND_NOT_m_cfg_ETC___d3462, + NOT_m_vrg_source_busy_14_026_466_AND_NOT_m_cfg_ETC___d3470, + NOT_m_vrg_source_busy_15_027_474_AND_NOT_m_cfg_ETC___d3478, + NOT_m_vrg_source_busy_16_028_482_AND_NOT_m_cfg_ETC___d3486, + NOT_m_vrg_source_busy_1_013_363_AND_NOT_m_cfg__ETC___d3367, + NOT_m_vrg_source_busy_2_014_370_AND_NOT_m_cfg__ETC___d3374, + NOT_m_vrg_source_busy_3_015_378_AND_NOT_m_cfg__ETC___d3382, + NOT_m_vrg_source_busy_4_016_386_AND_NOT_m_cfg__ETC___d3390, + NOT_m_vrg_source_busy_5_017_394_AND_NOT_m_cfg__ETC___d3398, + NOT_m_vrg_source_busy_6_018_402_AND_NOT_m_cfg__ETC___d3406, + NOT_m_vrg_source_busy_7_019_410_AND_NOT_m_cfg__ETC___d3414, + NOT_m_vrg_source_busy_8_020_418_AND_NOT_m_cfg__ETC___d3422, + NOT_m_vrg_source_busy_9_021_426_AND_NOT_m_cfg__ETC___d3430, _dfoo1, _dfoo10, _dfoo100, @@ -3086,94 +3294,94 @@ module mkPLIC_16_2_7(CLK, _dfoo997, _dfoo998, _dfoo999, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920, - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153, - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158, - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163, - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635, - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173, - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178, - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656, - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694, - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113, - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118, - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123, - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128, - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133, - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593, - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143, - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148, - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607, - m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651; + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d112, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1000, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1002, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1004, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1006, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2997, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2999, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d974, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d976, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d978, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d980, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d982, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d984, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d986, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d988, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d990, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d992, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d994, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d996, + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d998, + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3186, + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3280, + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d683, + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3191, + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3285, + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d690, + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3196, + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3290, + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d697, + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3201, + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3295, + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d704, + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d760, + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3206, + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3300, + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d711, + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3211, + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3305, + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d718, + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3216, + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3310, + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d725, + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d763, + m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_sourc_ETC___d620, + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3146, + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3240, + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d627, + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3151, + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3245, + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d634, + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3156, + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3250, + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d641, + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3161, + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3255, + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d648, + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3166, + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3260, + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d655, + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3171, + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3265, + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d662, + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d754, + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3176, + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3270, + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d669, + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3181, + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3275, + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d676, + m_vrg_source_prio_16_32_ULE_IF_m_vrg_source_ip_ETC___d720; // action method set_verbosity assign RDY_set_verbosity = 1'd1 ; @@ -3200,58 +3408,64 @@ module mkPLIC_16_2_7(CLK, assign CAN_FIRE_set_addr_map = 1'd1 ; assign WILL_FIRE_set_addr_map = EN_set_addr_map ; - // action method axi4_slave_m_awvalid - assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ; + // action method axi4_slave_aw_awflit + assign CAN_FIRE_axi4_slave_aw_awflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_aw_awflit = axi4_slave_awvalid ; - // value method axi4_slave_m_awready - assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ; + // value method axi4_slave_aw_awready + assign axi4_slave_awready = !m_slave_xactor_shim_awff_rv[98] ; - // action method axi4_slave_m_wvalid - assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ; + // action method axi4_slave_w_wflit + assign CAN_FIRE_axi4_slave_w_wflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_w_wflit = axi4_slave_wvalid ; - // value method axi4_slave_m_wready - assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ; + // value method axi4_slave_w_wready + assign axi4_slave_wready = !m_slave_xactor_shim_wff_rv[73] ; - // value method axi4_slave_m_bvalid - assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ; + // value method axi4_slave_b_bid + assign axi4_slave_bid = + m_slave_xactor_shim_bff_rvport1__read_BITS_6__ETC__q51[6:2] ; - // value method axi4_slave_m_bid - assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[5:2] ; + // value method axi4_slave_b_bresp + assign axi4_slave_bresp = + m_slave_xactor_shim_bff_rvport1__read_BITS_6__ETC__q51[1:0] ; - // value method axi4_slave_m_bresp - assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ; + // value method axi4_slave_b_bvalid + assign axi4_slave_bvalid = m_slave_xactor_shim_bff_rv$port1__read[7] ; - // action method axi4_slave_m_bready - assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ; + // action method axi4_slave_b_bready + assign CAN_FIRE_axi4_slave_b_bready = 1'd1 ; + assign WILL_FIRE_axi4_slave_b_bready = 1'd1 ; - // action method axi4_slave_m_arvalid - assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ; + // action method axi4_slave_ar_arflit + assign CAN_FIRE_axi4_slave_ar_arflit = 1'd1 ; + assign WILL_FIRE_axi4_slave_ar_arflit = axi4_slave_arvalid ; - // value method axi4_slave_m_arready - assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ; + // value method axi4_slave_ar_arready + assign axi4_slave_arready = !m_slave_xactor_shim_arff_rv[98] ; - // value method axi4_slave_m_rvalid - assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ; + // value method axi4_slave_r_rid + assign axi4_slave_rid = + m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52[71:67] ; - // value method axi4_slave_m_rid - assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[70:67] ; + // value method axi4_slave_r_rdata + assign axi4_slave_rdata = + m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52[66:3] ; - // value method axi4_slave_m_rdata - assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ; + // value method axi4_slave_r_rresp + assign axi4_slave_rresp = + m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52[2:1] ; - // value method axi4_slave_m_rresp - assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ; + // value method axi4_slave_r_rlast + assign axi4_slave_rlast = + m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52[0] ; - // value method axi4_slave_m_rlast - assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ; + // value method axi4_slave_r_rvalid + assign axi4_slave_rvalid = m_slave_xactor_shim_rff_rv$port1__read[72] ; - // action method axi4_slave_m_rready - assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ; - assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ; + // action method axi4_slave_r_rready + assign CAN_FIRE_axi4_slave_r_rready = 1'd1 ; + assign WILL_FIRE_axi4_slave_r_rready = 1'd1 ; // action method v_sources_0_m_interrupt_req assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ; @@ -3318,10 +3532,10 @@ module mkPLIC_16_2_7(CLK, assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ; // value method v_targets_0_m_eip - assign v_targets_0_m_eip = a__h71297 > m_vrg_target_threshold_0 ; + assign v_targets_0_m_eip = a__h74356 > m_vrg_target_threshold_0 ; // value method v_targets_1_m_eip - assign v_targets_1_m_eip = a__h73302 > m_vrg_target_threshold_1 ; + assign v_targets_1_m_eip = a__h76361 > m_vrg_target_threshold_1 ; // submodule m_f_reset_reqs FIFO20 #(.guarded(32'd1)) m_f_reset_reqs(.RST(RST_N), @@ -3341,279 +3555,308 @@ module mkPLIC_16_2_7(CLK, .FULL_N(m_f_reset_rsps$FULL_N), .EMPTY_N(m_f_reset_rsps$EMPTY_N)); - // submodule m_slave_xactor_f_rd_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_addr$D_IN), - .ENQ(m_slave_xactor_f_rd_addr$ENQ), - .DEQ(m_slave_xactor_f_rd_addr$DEQ), - .CLR(m_slave_xactor_f_rd_addr$CLR), - .D_OUT(m_slave_xactor_f_rd_addr$D_OUT), - .FULL_N(m_slave_xactor_f_rd_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_rd_data - FIFO2 #(.width(32'd71), - .guarded(32'd1)) m_slave_xactor_f_rd_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_rd_data$D_IN), - .ENQ(m_slave_xactor_f_rd_data$ENQ), - .DEQ(m_slave_xactor_f_rd_data$DEQ), - .CLR(m_slave_xactor_f_rd_data$CLR), - .D_OUT(m_slave_xactor_f_rd_data$D_OUT), - .FULL_N(m_slave_xactor_f_rd_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_addr - FIFO2 #(.width(32'd97), - .guarded(32'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_addr$D_IN), - .ENQ(m_slave_xactor_f_wr_addr$ENQ), - .DEQ(m_slave_xactor_f_wr_addr$DEQ), - .CLR(m_slave_xactor_f_wr_addr$CLR), - .D_OUT(m_slave_xactor_f_wr_addr$D_OUT), - .FULL_N(m_slave_xactor_f_wr_addr$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_data - FIFO2 #(.width(32'd73), - .guarded(32'd1)) m_slave_xactor_f_wr_data(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_data$D_IN), - .ENQ(m_slave_xactor_f_wr_data$ENQ), - .DEQ(m_slave_xactor_f_wr_data$DEQ), - .CLR(m_slave_xactor_f_wr_data$CLR), - .D_OUT(m_slave_xactor_f_wr_data$D_OUT), - .FULL_N(m_slave_xactor_f_wr_data$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N)); - - // submodule m_slave_xactor_f_wr_resp - FIFO2 #(.width(32'd6), - .guarded(32'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N), - .CLK(CLK), - .D_IN(m_slave_xactor_f_wr_resp$D_IN), - .ENQ(m_slave_xactor_f_wr_resp$ENQ), - .DEQ(m_slave_xactor_f_wr_resp$DEQ), - .CLR(m_slave_xactor_f_wr_resp$CLR), - .D_OUT(m_slave_xactor_f_wr_resp$D_OUT), - .FULL_N(m_slave_xactor_f_wr_resp$FULL_N), - .EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N)); - // rule RL_m_rl_reset assign CAN_FIRE_RL_m_rl_reset = - m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ; + !m_slave_xactor_clearing && m_f_reset_reqs$EMPTY_N && + m_f_reset_rsps$FULL_N ; assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ; + // rule RL_m_slave_xactor_ug_slave_u_aw_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut = + m_slave_xactor_ug_slave_u_aw_putWire$whas && + m_slave_xactor_shim_awff_rv[98] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut ; + + // rule RL_m_slave_xactor_ug_slave_u_aw_doPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut = + !m_slave_xactor_shim_awff_rv[98] && + m_slave_xactor_ug_slave_u_aw_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut ; + + // rule RL_m_slave_xactor_ug_slave_u_w_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut = + m_slave_xactor_ug_slave_u_w_putWire$whas && + m_slave_xactor_shim_wff_rv[73] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut ; + + // rule RL_m_slave_xactor_ug_slave_u_w_doPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut = + !m_slave_xactor_shim_wff_rv[73] && + m_slave_xactor_ug_slave_u_w_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut ; + + // rule RL_m_slave_xactor_ug_slave_u_ar_warnDoPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut = + m_slave_xactor_ug_slave_u_ar_putWire$whas && + m_slave_xactor_shim_arff_rv[98] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut ; + + // rule RL_m_slave_xactor_ug_slave_u_ar_doPut + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut = + !m_slave_xactor_shim_arff_rv[98] && + m_slave_xactor_ug_slave_u_ar_putWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut ; + // rule RL_m_rl_process_rd_req assign CAN_FIRE_RL_m_rl_process_rd_req = - m_slave_xactor_f_rd_addr$EMPTY_N && - m_slave_xactor_f_rd_data$FULL_N && + !m_slave_xactor_clearing && + m_slave_xactor_shim_arff_rv$port1__read[98] && + !m_slave_xactor_shim_rff_rv[72] && !m_f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ; // rule RL_m_rl_process_wr_req assign CAN_FIRE_RL_m_rl_process_wr_req = - m_slave_xactor_f_wr_addr$EMPTY_N && - m_slave_xactor_f_wr_data$EMPTY_N && - m_slave_xactor_f_wr_resp$FULL_N && + !m_slave_xactor_clearing && + m_slave_xactor_shim_awff_rv$port1__read[98] && + m_slave_xactor_shim_wff_rv$port1__read[73] && + !m_slave_xactor_shim_bff_rv[7] && !m_f_reset_reqs$EMPTY_N ; assign WILL_FIRE_RL_m_rl_process_wr_req = CAN_FIRE_RL_m_rl_process_wr_req && !WILL_FIRE_RL_m_rl_process_rd_req ; + // rule RL_m_slave_xactor_ug_slave_u_b_setPeek + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek = + m_slave_xactor_shim_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_setPeek = + m_slave_xactor_shim_bff_rv$port1__read[7] ; + + // rule RL_m_slave_xactor_ug_slave_u_b_warnDoDrop + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop = + m_slave_xactor_ug_slave_u_b_dropWire$whas && + !m_slave_xactor_shim_bff_rv$port1__read[7] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop ; + + // rule RL_m_slave_xactor_ug_slave_u_b_doDrop + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop = + m_slave_xactor_shim_bff_rv$port1__read[7] && + m_slave_xactor_ug_slave_u_b_dropWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop ; + + // rule RL_m_slave_xactor_ug_slave_u_r_setPeek + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek = + m_slave_xactor_shim_rff_rv$port1__read[72] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_setPeek = + m_slave_xactor_shim_rff_rv$port1__read[72] ; + + // rule RL_m_slave_xactor_ug_slave_u_r_warnDoDrop + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop = + m_slave_xactor_ug_slave_u_r_dropWire$whas && + !m_slave_xactor_shim_rff_rv$port1__read[72] ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop ; + + // rule RL_m_slave_xactor_ug_slave_u_r_doDrop + assign CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop = + m_slave_xactor_shim_rff_rv$port1__read[72] && + m_slave_xactor_ug_slave_u_r_dropWire$whas ; + assign WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop ; + + // rule RL_m_slave_xactor_do_clear + assign CAN_FIRE_RL_m_slave_xactor_do_clear = m_slave_xactor_clearing ; + assign WILL_FIRE_RL_m_slave_xactor_do_clear = m_slave_xactor_clearing ; + // inputs to muxes for submodule ports assign MUX_m_vrg_servicing_source_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13214[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + addr_offset__h15646[16:12] == 5'd0 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_servicing_source_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13214[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + addr_offset__h15646[16:12] == 5'd1 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_0$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd1 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd10 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_10$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd10 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd11 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_11$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd11 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd12 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_12$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd12 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd13 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_13$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd13 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd14 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_14$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd14 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd15 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_15$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd15 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd16 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_16$write_1__SEL_2 = WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + source_id__h70276 == 10'd16 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd2 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd2 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd3 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd3 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd4 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd4 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd5 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd5 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd6 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd6 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd7 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd7 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd8 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd8 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 ; + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd9 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 ; assign MUX_m_vrg_source_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 ; + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd9 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 ; assign MUX_m_vrg_source_prio_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26920[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 ; + addr_offset__h29732[11:2] == 10'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d963 ; assign MUX_m_vrg_source_prio_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d974 ; assign MUX_m_vrg_source_prio_10$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d992 ; assign MUX_m_vrg_source_prio_11$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d994 ; assign MUX_m_vrg_source_prio_12$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d996 ; assign MUX_m_vrg_source_prio_13$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d998 ; assign MUX_m_vrg_source_prio_14$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1000 ; assign MUX_m_vrg_source_prio_15$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1002 ; assign MUX_m_vrg_source_prio_16$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1004 ; assign MUX_m_vrg_source_prio_2$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d976 ; assign MUX_m_vrg_source_prio_3$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d978 ; assign MUX_m_vrg_source_prio_4$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d980 ; assign MUX_m_vrg_source_prio_5$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d982 ; assign MUX_m_vrg_source_prio_6$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d984 ; assign MUX_m_vrg_source_prio_7$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d986 ; assign MUX_m_vrg_source_prio_8$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d988 ; assign MUX_m_vrg_source_prio_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d990 ; assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2997 ; assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 ; + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2999 ; assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ; assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 = @@ -3683,176 +3926,292 @@ module mkPLIC_16_2_7(CLK, assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 = WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ; assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 = - (source_id_base__h28137 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2040 ; assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 = - (source_id_base__h28137 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd1 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2038 ; assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 = - (source_id_base__h28137 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd10 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2020 ; assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 = - (source_id_base__h28137 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd11 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2018 ; assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 = - (source_id_base__h28137 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd12 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2016 ; assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 = - (source_id_base__h28137 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd13 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2014 ; assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 = - (source_id_base__h28137 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd14 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2012 ; assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 = - (source_id_base__h28137 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd15 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2010 ; assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 = - (source_id_base__h28137 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd16 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2008 ; assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 = - (source_id_base__h28137 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd2 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2036 ; assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 = - (source_id_base__h28137 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd3 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2034 ; assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 = - (source_id_base__h28137 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd4 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2032 ; assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 = - (source_id_base__h28137 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd5 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2030 ; assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 = - (source_id_base__h28137 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd6 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2028 ; assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 = - (source_id_base__h28137 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd7 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2026 ; assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 = - (source_id_base__h28137 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd8 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2024 ; assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 = - (source_id_base__h28137 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd9 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032) ? + wdata32__h29733[0] : _dfoo2022 ; assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 = - (source_id_base__h28137 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo2006 ; assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 = - (source_id_base__h28137 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd1 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo2004 ; assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 = - (source_id_base__h28137 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd10 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1986 ; assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 = - (source_id_base__h28137 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd11 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1984 ; assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 = - (source_id_base__h28137 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd12 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1982 ; assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 = - (source_id_base__h28137 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd13 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1980 ; assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 = - (source_id_base__h28137 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd14 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1978 ; assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 = - (source_id_base__h28137 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd15 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1976 ; assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 = - (source_id_base__h28137 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd16 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1974 ; assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 = - (source_id_base__h28137 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd2 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo2002 ; assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 = - (source_id_base__h28137 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd3 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo2000 ; assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 = - (source_id_base__h28137 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd4 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1998 ; assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 = - (source_id_base__h28137 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd5 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1996 ; assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 = - (source_id_base__h28137 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd6 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1994 ; assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 = - (source_id_base__h28137 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd7 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1992 ; assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 = - (source_id_base__h28137 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd8 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1990 ; assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 = - (source_id_base__h28137 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956) ? - wdata32__h26921[0] : + (source_id_base__h30983 == 10'd9 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068) ? + wdata32__h29733[0] : _dfoo1988 ; + // inlined wires + assign m_slave_xactor_ug_slave_u_aw_putWire$wget = + { axi4_slave_awid, + axi4_slave_awaddr, + axi4_slave_awlen, + axi4_slave_awsize, + axi4_slave_awburst, + axi4_slave_awlock, + axi4_slave_awcache, + axi4_slave_awprot, + axi4_slave_awqos, + axi4_slave_awregion } ; + assign m_slave_xactor_ug_slave_u_aw_putWire$whas = + axi4_slave_awvalid && !m_slave_xactor_shim_awff_rv[98] ; + assign m_slave_xactor_ug_slave_u_w_putWire$wget = + { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; + assign m_slave_xactor_ug_slave_u_w_putWire$whas = + axi4_slave_wvalid && !m_slave_xactor_shim_wff_rv[73] ; + assign m_slave_xactor_ug_slave_u_ar_putWire$wget = + { axi4_slave_arid, + axi4_slave_araddr, + axi4_slave_arlen, + axi4_slave_arsize, + axi4_slave_arburst, + axi4_slave_arlock, + axi4_slave_arcache, + axi4_slave_arprot, + axi4_slave_arqos, + axi4_slave_arregion } ; + assign m_slave_xactor_ug_slave_u_ar_putWire$whas = + axi4_slave_arvalid && !m_slave_xactor_shim_arff_rv[98] ; + assign m_slave_xactor_ug_slave_u_b_dropWire$whas = + m_slave_xactor_shim_bff_rv$port1__read[7] && axi4_slave_bready ; + assign m_slave_xactor_ug_slave_u_r_dropWire$whas = + m_slave_xactor_shim_rff_rv$port1__read[72] && axi4_slave_rready ; + assign m_slave_xactor_shim_awff_rv$port0__write_1 = + { 1'd1, m_slave_xactor_ug_slave_u_aw_putWire$wget } ; + assign m_slave_xactor_shim_awff_rv$port1__read = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_aw_doPut ? + m_slave_xactor_shim_awff_rv$port0__write_1 : + m_slave_xactor_shim_awff_rv ; + assign m_slave_xactor_shim_awff_rv$port2__read = + WILL_FIRE_RL_m_rl_process_wr_req ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_awff_rv$port1__read ; + assign m_slave_xactor_shim_awff_rv$port3__read = + m_slave_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_awff_rv$port2__read ; + assign m_slave_xactor_shim_wff_rv$port0__write_1 = + { 1'd1, m_slave_xactor_ug_slave_u_w_putWire$wget } ; + assign m_slave_xactor_shim_wff_rv$port1__read = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_w_doPut ? + m_slave_xactor_shim_wff_rv$port0__write_1 : + m_slave_xactor_shim_wff_rv ; + assign m_slave_xactor_shim_wff_rv$port2__read = + WILL_FIRE_RL_m_rl_process_wr_req ? + 74'h0AAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_wff_rv$port1__read ; + assign m_slave_xactor_shim_wff_rv$port3__read = + m_slave_xactor_clearing ? + 74'h0AAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_wff_rv$port2__read ; + assign m_slave_xactor_shim_bff_rv$port0__write_1 = + { 1'd1, + m_slave_xactor_shim_awff_rv$port1__read[97:93], + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 ? + 2'd3 : + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3124 } ; + assign m_slave_xactor_shim_bff_rv$port1__read = + WILL_FIRE_RL_m_rl_process_wr_req ? + m_slave_xactor_shim_bff_rv$port0__write_1 : + m_slave_xactor_shim_bff_rv ; + assign m_slave_xactor_shim_bff_rv$port2__read = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_b_doDrop ? + 8'd42 : + m_slave_xactor_shim_bff_rv$port1__read ; + assign m_slave_xactor_shim_bff_rv$port3__read = + m_slave_xactor_clearing ? + 8'd42 : + m_slave_xactor_shim_bff_rv$port2__read ; + assign m_slave_xactor_shim_arff_rv$port0__write_1 = + { 1'd1, m_slave_xactor_ug_slave_u_ar_putWire$wget } ; + assign m_slave_xactor_shim_arff_rv$port1__read = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_ar_doPut ? + m_slave_xactor_shim_arff_rv$port0__write_1 : + m_slave_xactor_shim_arff_rv ; + assign m_slave_xactor_shim_arff_rv$port2__read = + CAN_FIRE_RL_m_rl_process_rd_req ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_arff_rv$port1__read ; + assign m_slave_xactor_shim_arff_rv$port3__read = + m_slave_xactor_clearing ? + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_arff_rv$port2__read ; + assign m_slave_xactor_shim_rff_rv$port0__write_1 = + { 1'd1, + m_slave_xactor_shim_arff_rv$port1__read[97:93], + x__h28872, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 ? + 2'd3 : + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d880, + 1'd1 } ; + assign m_slave_xactor_shim_rff_rv$port1__read = + CAN_FIRE_RL_m_rl_process_rd_req ? + m_slave_xactor_shim_rff_rv$port0__write_1 : + m_slave_xactor_shim_rff_rv ; + assign m_slave_xactor_shim_rff_rv$port2__read = + CAN_FIRE_RL_m_slave_xactor_ug_slave_u_r_doDrop ? + 73'h0AAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_rff_rv$port1__read ; + assign m_slave_xactor_shim_rff_rv$port3__read = + m_slave_xactor_clearing ? + 73'h0AAAAAAAAAAAAAAAAAA : + m_slave_xactor_shim_rff_rv$port2__read ; + // register m_cfg_verbosity assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ; assign m_cfg_verbosity$EN = EN_set_verbosity ; @@ -3865,34 +4224,64 @@ module mkPLIC_16_2_7(CLK, assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ; assign m_rg_addr_lim$EN = EN_set_addr_map ; + // register m_slave_xactor_clearing + assign m_slave_xactor_clearing$D_IN = !m_slave_xactor_clearing ; + assign m_slave_xactor_clearing$EN = + m_slave_xactor_clearing || WILL_FIRE_RL_m_rl_reset ; + + // register m_slave_xactor_shim_arff_rv + assign m_slave_xactor_shim_arff_rv$D_IN = + m_slave_xactor_shim_arff_rv$port3__read ; + assign m_slave_xactor_shim_arff_rv$EN = 1'b1 ; + + // register m_slave_xactor_shim_awff_rv + assign m_slave_xactor_shim_awff_rv$D_IN = + m_slave_xactor_shim_awff_rv$port3__read ; + assign m_slave_xactor_shim_awff_rv$EN = 1'b1 ; + + // register m_slave_xactor_shim_bff_rv + assign m_slave_xactor_shim_bff_rv$D_IN = + m_slave_xactor_shim_bff_rv$port3__read ; + assign m_slave_xactor_shim_bff_rv$EN = 1'b1 ; + + // register m_slave_xactor_shim_rff_rv + assign m_slave_xactor_shim_rff_rv$D_IN = + m_slave_xactor_shim_rff_rv$port3__read ; + assign m_slave_xactor_shim_rff_rv$EN = 1'b1 ; + + // register m_slave_xactor_shim_wff_rv + assign m_slave_xactor_shim_wff_rv$D_IN = + m_slave_xactor_shim_wff_rv$port3__read ; + assign m_slave_xactor_shim_wff_rv$EN = 1'b1 ; + // register m_vrg_servicing_source_0 assign m_vrg_servicing_source_0$D_IN = MUX_m_vrg_servicing_source_0$write_1__SEL_1 ? - max_id__h23957 : + max_id__h26424 : 5'd0 ; assign m_vrg_servicing_source_0$EN = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13214[16:12] == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + addr_offset__h15646[16:12] == 5'd0 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26920[16:12] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + addr_offset__h29732[16:12] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_servicing_source_1 assign m_vrg_servicing_source_1$D_IN = MUX_m_vrg_servicing_source_1$write_1__SEL_1 ? - max_id__h23957 : + max_id__h26424 : 5'd0 ; assign m_vrg_servicing_source_1$EN = WILL_FIRE_RL_m_rl_process_rd_req && - addr_offset__h13214[16:12] == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + addr_offset__h15646[16:12] == 5'd1 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26920[16:12] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + addr_offset__h29732[16:12] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_0 @@ -3900,11 +4289,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_0$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd0 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_1 @@ -3912,11 +4301,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_1$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_1$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd1 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_10 @@ -3924,12 +4313,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_10$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_10$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd10 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd10 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd10 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_11 @@ -3937,12 +4326,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_11$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_11$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd11 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd11 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd11 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_12 @@ -3950,12 +4339,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_12$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_12$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd12 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd12 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd12 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_13 @@ -3963,12 +4352,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_13$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_13$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd13 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd13 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd13 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_14 @@ -3976,12 +4365,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_14$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_14$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd14 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd14 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd14 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_15 @@ -3989,12 +4378,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_15$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_15$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd15 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd15 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd15 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_16 @@ -4002,12 +4391,12 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_16$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_16$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd16 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_process_wr_req && - source_id__h67425 == 10'd16 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + source_id__h70276 == 10'd16 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_2 @@ -4015,11 +4404,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_2$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_2$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd2 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd2 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd2 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_3 @@ -4027,11 +4416,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_3$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_3$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd3 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd3 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd3 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_4 @@ -4039,11 +4428,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_4$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_4$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd4 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd4 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd4 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_5 @@ -4051,11 +4440,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_5$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_5$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd5 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd5 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd5 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_6 @@ -4063,11 +4452,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_6$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_6$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd6 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd6 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd6 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_7 @@ -4075,11 +4464,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_7$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_7$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd7 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd7 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd7 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_8 @@ -4087,11 +4476,11 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_8$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_8$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd8 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd8 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd8 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_busy_9 @@ -4099,19 +4488,19 @@ module mkPLIC_16_2_7(CLK, !MUX_m_vrg_source_busy_9$write_1__SEL_2 && !WILL_FIRE_RL_m_rl_reset ; assign m_vrg_source_busy_9$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || - WILL_FIRE_RL_m_rl_process_wr_req && source_id__h67425 == 10'd9 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd9 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || + WILL_FIRE_RL_m_rl_process_wr_req && source_id__h70276 == 10'd9 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_0 assign m_vrg_source_ip_0$D_IN = 1'd0 ; assign m_vrg_source_ip_0$EN = - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd0 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd0 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_1 @@ -4121,9 +4510,9 @@ module mkPLIC_16_2_7(CLK, v_sources_0_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_1$EN = !m_vrg_source_busy_1 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd1 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd1 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_10 @@ -4133,9 +4522,9 @@ module mkPLIC_16_2_7(CLK, v_sources_9_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_10$EN = !m_vrg_source_busy_10 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd10 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd10 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_11 @@ -4145,9 +4534,9 @@ module mkPLIC_16_2_7(CLK, v_sources_10_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_11$EN = !m_vrg_source_busy_11 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd11 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd11 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_12 @@ -4157,9 +4546,9 @@ module mkPLIC_16_2_7(CLK, v_sources_11_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_12$EN = !m_vrg_source_busy_12 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd12 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd12 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_13 @@ -4169,9 +4558,9 @@ module mkPLIC_16_2_7(CLK, v_sources_12_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_13$EN = !m_vrg_source_busy_13 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd13 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd13 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_14 @@ -4181,9 +4570,9 @@ module mkPLIC_16_2_7(CLK, v_sources_13_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_14$EN = !m_vrg_source_busy_14 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd14 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd14 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_15 @@ -4193,9 +4582,9 @@ module mkPLIC_16_2_7(CLK, v_sources_14_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_15$EN = !m_vrg_source_busy_15 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd15 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd15 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_16 @@ -4205,9 +4594,9 @@ module mkPLIC_16_2_7(CLK, v_sources_15_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_16$EN = !m_vrg_source_busy_16 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd16 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd16 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_2 @@ -4217,9 +4606,9 @@ module mkPLIC_16_2_7(CLK, v_sources_1_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_2$EN = !m_vrg_source_busy_2 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd2 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd2 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_3 @@ -4229,9 +4618,9 @@ module mkPLIC_16_2_7(CLK, v_sources_2_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_3$EN = !m_vrg_source_busy_3 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd3 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd3 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_4 @@ -4241,9 +4630,9 @@ module mkPLIC_16_2_7(CLK, v_sources_3_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_4$EN = !m_vrg_source_busy_4 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd4 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd4 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_5 @@ -4253,9 +4642,9 @@ module mkPLIC_16_2_7(CLK, v_sources_4_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_5$EN = !m_vrg_source_busy_5 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd5 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd5 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_6 @@ -4265,9 +4654,9 @@ module mkPLIC_16_2_7(CLK, v_sources_5_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_6$EN = !m_vrg_source_busy_6 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd6 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd6 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_7 @@ -4277,9 +4666,9 @@ module mkPLIC_16_2_7(CLK, v_sources_6_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_7$EN = !m_vrg_source_busy_7 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd7 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd7 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_8 @@ -4289,9 +4678,9 @@ module mkPLIC_16_2_7(CLK, v_sources_7_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_8$EN = !m_vrg_source_busy_8 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd8 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd8 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_ip_9 @@ -4301,200 +4690,200 @@ module mkPLIC_16_2_7(CLK, v_sources_8_m_interrupt_req_set_not_clear ; assign m_vrg_source_ip_9$EN = !m_vrg_source_busy_9 || - WILL_FIRE_RL_m_rl_process_rd_req && max_id__h23957 == 5'd9 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 || + WILL_FIRE_RL_m_rl_process_rd_req && max_id__h26424 == 5'd9 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_0 assign m_vrg_source_prio_0$D_IN = MUX_m_vrg_source_prio_0$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - addr_offset__h26920[11:2] == 10'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 || + addr_offset__h29732[11:2] == 10'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d963 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_1 assign m_vrg_source_prio_1$D_IN = MUX_m_vrg_source_prio_1$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d974 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_10 assign m_vrg_source_prio_10$D_IN = MUX_m_vrg_source_prio_10$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_10$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d992 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_11 assign m_vrg_source_prio_11$D_IN = MUX_m_vrg_source_prio_11$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_11$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d994 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_12 assign m_vrg_source_prio_12$D_IN = MUX_m_vrg_source_prio_12$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_12$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d996 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_13 assign m_vrg_source_prio_13$D_IN = MUX_m_vrg_source_prio_13$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_13$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d998 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_14 assign m_vrg_source_prio_14$D_IN = MUX_m_vrg_source_prio_14$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_14$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1000 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_15 assign m_vrg_source_prio_15$D_IN = MUX_m_vrg_source_prio_15$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_15$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1002 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_16 assign m_vrg_source_prio_16$D_IN = MUX_m_vrg_source_prio_16$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_16$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1004 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_2 assign m_vrg_source_prio_2$D_IN = MUX_m_vrg_source_prio_2$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_2$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d976 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_3 assign m_vrg_source_prio_3$D_IN = MUX_m_vrg_source_prio_3$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_3$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d978 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_4 assign m_vrg_source_prio_4$D_IN = MUX_m_vrg_source_prio_4$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_4$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d980 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_5 assign m_vrg_source_prio_5$D_IN = MUX_m_vrg_source_prio_5$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_5$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d982 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_6 assign m_vrg_source_prio_6$D_IN = MUX_m_vrg_source_prio_6$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_6$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d984 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_7 assign m_vrg_source_prio_7$D_IN = MUX_m_vrg_source_prio_7$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_7$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d986 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_8 assign m_vrg_source_prio_8$D_IN = MUX_m_vrg_source_prio_8$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_8$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d988 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_source_prio_9 assign m_vrg_source_prio_9$D_IN = MUX_m_vrg_source_prio_9$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd0 ; assign m_vrg_source_prio_9$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d990 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_0 assign m_vrg_target_threshold_0$D_IN = MUX_m_vrg_target_threshold_0$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd7 ; assign m_vrg_target_threshold_0$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2997 || WILL_FIRE_RL_m_rl_reset ; // register m_vrg_target_threshold_1 assign m_vrg_target_threshold_1$D_IN = MUX_m_vrg_target_threshold_1$write_1__SEL_1 ? - wdata32__h26921[2:0] : + wdata32__h29733[2:0] : 3'd7 ; assign m_vrg_target_threshold_1$EN = WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 || + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2999 || WILL_FIRE_RL_m_rl_reset ; // register m_vvrg_ie_0_0 @@ -4779,12018 +5168,12051 @@ module mkPLIC_16_2_7(CLK, assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ; assign m_f_reset_rsps$CLR = 1'b0 ; - // submodule m_slave_xactor_f_rd_addr - assign m_slave_xactor_f_rd_addr$D_IN = - { axi4_slave_arid, - axi4_slave_araddr, - axi4_slave_arlen, - axi4_slave_arsize, - axi4_slave_arburst, - axi4_slave_arlock, - axi4_slave_arcache, - axi4_slave_arprot, - axi4_slave_arqos, - axi4_slave_arregion } ; - assign m_slave_xactor_f_rd_addr$ENQ = - axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ; - assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_rd_data - assign m_slave_xactor_f_rd_data$D_IN = - { m_slave_xactor_f_rd_addr$D_OUT[96:93], - x__h26359, - rresp__h26201, - 1'd1 } ; - assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ; - assign m_slave_xactor_f_rd_data$DEQ = - axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ; - assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_addr - assign m_slave_xactor_f_wr_addr$D_IN = - { axi4_slave_awid, - axi4_slave_awaddr, - axi4_slave_awlen, - axi4_slave_awsize, - axi4_slave_awburst, - axi4_slave_awlock, - axi4_slave_awcache, - axi4_slave_awprot, - axi4_slave_awqos, - axi4_slave_awregion } ; - assign m_slave_xactor_f_wr_addr$ENQ = - axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ; - assign m_slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_data - assign m_slave_xactor_f_wr_data$D_IN = - { axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ; - assign m_slave_xactor_f_wr_data$ENQ = - axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ; - assign m_slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ; - - // submodule m_slave_xactor_f_wr_resp - assign m_slave_xactor_f_wr_resp$D_IN = - { m_slave_xactor_f_wr_addr$D_OUT[96:93], v__h26925 } ; - assign m_slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_m_rl_process_wr_req ; - assign m_slave_xactor_f_wr_resp$DEQ = - axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ; - assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ; - // remaining internal signals - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 : - ((x__h23671 == 32'h00200000) ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 : - x__h23671 != 32'h00200004 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 || - x__h24009 != 5'd0) ; - assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - addr_offset__h13214[11:2] == 10'd0 || - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 : - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ? - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 : - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d769) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 : - ((x__h67099 == 32'h00200000) ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 : - x__h67099 != 32'h00200004 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 || - !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918) ; - assign IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? - addr_offset__h26920[11:2] == 10'd0 || - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 : - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 ? - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 : - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2988) ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d838 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 ? + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 || + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311 : + ((x__h26136 == 32'h00200000) ? + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 : + x__h26136 != 32'h00200004 || + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 || + x__h26477 != 5'd0) ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 ? + addr_offset__h15646[11:2] == 10'd0 || + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109 : + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 ? + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 : + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d838) ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d878 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 ? + ((m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311) ? + 2'd0 : + 2'd2) : + CASE_x6136_0x200000_IF_m_slave_xactor_shim_arf_ETC__q50 ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d879 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 ? + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 ? + 2'd0 : + 2'd2) : + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d878 ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d880 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 ? + ((addr_offset__h15646[11:2] != 10'd0 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109) ? + 2'd0 : + 2'd2) : + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d879 ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d889 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 ? + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311 : + ((x__h26136 == 32'h00200000) ? + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 : + x__h26136 == 32'h00200004 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 && + x__h26477 == 5'd0) ; + assign IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d891 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 ? + addr_offset__h15646[11:2] != 10'd0 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109 : + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 ? + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 : + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d889) ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3100 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 ? + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 || + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 : + ((x__h69947 == 32'h00200000) ? + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 : + x__h69947 != 32'h00200004 || + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 || + !SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030) ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 ? + addr_offset__h29732[11:2] == 10'd0 || + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 : + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 ? + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 : + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3100) ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3122 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 ? + ((m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026) ? + 2'd0 : + 2'd2) : + CASE_x9947_0x200000_IF_m_slave_xactor_shim_awf_ETC__q1 ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3123 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 ? + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 ? + 2'd0 : + 2'd2) : + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3122 ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3124 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 ? + ((addr_offset__h29732[11:2] != 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960) ? + 2'd0 : + 2'd2) : + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3123 ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3130 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 ? + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 : + ((x__h69947 == 32'h00200000) ? + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 : + x__h69947 == 32'h00200004 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 && + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030) ; + assign IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3132 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 ? + addr_offset__h29732[11:2] != 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 : + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 ? + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 : + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3130) ; + assign IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3187 = + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3186 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3182 ; + assign IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3281 = + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3280 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 ; - assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 = - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3276 ; + assign IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d684 = + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d683 ? m_vrg_source_prio_10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d677 ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3192 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3191 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 ? + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3187 ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3228 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3191 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 ? + (m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3186 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3226) ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3286 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3285 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 ? + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3281 ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3322 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3285 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 ? + (m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3280 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193) ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3320) ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d691 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d690 ? m_vrg_source_prio_11 : - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ; - assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 = - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ? + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d684 ; + assign IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d736 = + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d690 ? 5'd11 : - (m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ? + (m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d683 ? 5'd10 : - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d734) ; + assign IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3197 = + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3196 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3192 ; + assign IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3291 = + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3290 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 ; - assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 = - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3286 ; + assign IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d698 = + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d697 ? m_vrg_source_prio_12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d691 ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3202 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3201 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 ? + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3197 ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3230 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3201 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 ? + (m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3196 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3101) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3228) ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3296 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3295 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 ? + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3291 ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3324 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3295 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 ? + (m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3290 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3195) ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3322) ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d705 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d704 ? m_vrg_source_prio_13 : - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ; - assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ? + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d698 ; + assign IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d738 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d704 ? 5'd13 : - (m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ? + (m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d697 ? 5'd12 : - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d736) ; + assign IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3207 = + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3206 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3202 ; + assign IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3301 = + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3300 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 ; - assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 = - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3296 ; + assign IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d712 = + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d711 ? m_vrg_source_prio_14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d705 ; + assign IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3212 = + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3211 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 ? + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3207 ; + assign IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3232 = + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3211 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 ? + (m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3206 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3103) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3230) ; + assign IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3306 = + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3305 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 ? + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3301 ; + assign IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3326 = + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3305 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 ? + (m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3300 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3197) ; - assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 = - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3324) ; + assign IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d740 = + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d718 ? 5'd15 : - (m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ? + (m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d711 ? 5'd14 : - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 = + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d738) ; + assign IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3142 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 = + assign IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3236 = (m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 = - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? + assign IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d621 = + m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_sourc_ETC___d620 ? m_vrg_source_prio_1 : 3'd0 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? + assign IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3147 = + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3146 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3142 ; + assign IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3241 = + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3240 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 ; - assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 = - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3236 ; + assign IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d628 = + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d627 ? m_vrg_source_prio_2 : - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d621 ; + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3152 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3151 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 ? + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3147 ; + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3220 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3151 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 ? + (m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3146 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_0_1) ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3246 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3245 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 ? + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3241 ; + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3314 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3245 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 ? + (m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3240 ? 5'd2 : ((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && m_vvrg_ie_1_1) ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d635 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d634 ? m_vrg_source_prio_3 : - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ; - assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 = - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ? + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d628 ; + assign IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d728 = + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d634 ? 5'd3 : - (m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ? + (m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d627 ? 5'd2 : - (m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ? + (m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_sourc_ETC___d620 ? 5'd1 : 5'd0)) ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? + assign IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3157 = + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3156 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3152 ; + assign IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3251 = + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3250 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 ; - assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 = - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3246 ; + assign IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d642 = + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d641 ? m_vrg_source_prio_4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d635 ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3162 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3161 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 ? + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3157 ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3222 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3161 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 ? + (m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3156 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3093) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3220) ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3256 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3255 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 ? + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3251 ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3316 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3255 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 ? + (m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3250 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3187) ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3314) ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d649 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d648 ? m_vrg_source_prio_5 : - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ; - assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 = - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ? + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d642 ; + assign IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d730 = + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d648 ? 5'd5 : - (m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ? + (m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d641 ? 5'd4 : - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d728) ; + assign IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3167 = + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3166 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3162 ; + assign IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3261 = + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3260 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 ; - assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 = - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3256 ; + assign IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d656 = + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d655 ? m_vrg_source_prio_6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d649 ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3172 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3171 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 ? + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3167 ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3224 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3171 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 ? + (m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3166 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3095) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3222) ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3266 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3265 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 ? + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3261 ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3318 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3265 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 ? + (m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3260 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3189) ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3316) ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d663 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d662 ? m_vrg_source_prio_7 : - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ; - assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ? + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d656 ; + assign IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d732 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d662 ? 5'd7 : - (m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ? + (m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d655 ? 5'd6 : - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d730) ; + assign IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3177 = + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3176 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3172 ; + assign IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3271 = + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3270 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 ; - assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 = - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3266 ; + assign IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d670 = + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d669 ? m_vrg_source_prio_8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d663 ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3182 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3181 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3099 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 ? + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3177 ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3226 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3181 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 ? + (m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3176 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3097) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3224) ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3276 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3275 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3193 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 ? + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3271 ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3320 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3275 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 ? + (m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3270 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3191) ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3318) ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d677 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d676 ? m_vrg_source_prio_9 : - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ; - assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 = - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ? + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d670 ; + assign IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d734 = + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d676 ? 5'd9 : - (m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ? + (m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d669 ? 5'd8 : - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ; - assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 && + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d732) ; + assign NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 = m_cfg_verbosity > 4'd1 ; + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d143 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23671 == 32'h00200000 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d317 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d700 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23671 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24009 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d607 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 && + x__h26136 == 32'h00200000 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23671 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24009 == 5'd0 && - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 && + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d769 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 && + x__h26136 == 32'h00200004 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 && + x__h26477 == 5'd0 && + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d763 ; + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d813 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 && + x__h26136 == 32'h00200004 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 && + x__h26477 == 5'd0 && + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d763 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756 = - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 && - x__h23671 == 32'h00200004 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 && - x__h24009 != 5'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h30674 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h31884 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h33094 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h34304 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h35514 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h36724 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h37934 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h39144 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h40354 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h41564 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h42774 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h43984 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h45194 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h46404 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h47614 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h48824 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h50034 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h51244 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h52454 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h53664 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h54874 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h56084 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h57294 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h58504 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h59714 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h60924 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h62134 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h63344 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h64554 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h65764 <= 10'd16 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && + assign NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825 = + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 && + x__h26136 == 32'h00200004 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 && + x__h26477 != 5'd0 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1017 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67099 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67099 == 32'h00200000 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1029 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h32311 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h33521 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h34731 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h35941 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h37151 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h38361 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h39571 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h40781 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h41991 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h43201 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h44411 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h45621 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h46831 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h48041 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h49251 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h50461 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h51671 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h52881 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h54091 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h55301 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h56511 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h57721 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h58931 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h60141 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h61351 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h62561 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h63771 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h64981 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h66191 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h67401 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && + source_id__h68611 <= 10'd16 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2981 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2924 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67099 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67099 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 && + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2994 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + x__h69947 == 32'h00200000 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3005 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + x__h69947 == 32'h00200000 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - x__h67099 == 32'h00200004 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 && - !SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d851 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - addr_offset__h26920[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3036 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + x__h69947 == 32'h00200004 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 && + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3077 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + x__h69947 == 32'h00200004 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 && + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 && m_cfg_verbosity != 4'd0 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 ; - assign NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 = - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 && - source_id__h29464 <= 10'd16 ; - assign NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311 = + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 && + x__h69947 == 32'h00200004 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 && + !SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 ; + assign NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d963 = + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + addr_offset__h29732[11:2] != 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign NOT_m_vrg_source_busy_10_022_434_AND_NOT_m_cfg_ETC___d3438 = !m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319 = + assign NOT_m_vrg_source_busy_11_023_442_AND_NOT_m_cfg_ETC___d3446 = !m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_11 != v_sources_10_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327 = + assign NOT_m_vrg_source_busy_12_024_450_AND_NOT_m_cfg_ETC___d3454 = !m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_12 != v_sources_11_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335 = + assign NOT_m_vrg_source_busy_13_025_458_AND_NOT_m_cfg_ETC___d3462 = !m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_13 != v_sources_12_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343 = + assign NOT_m_vrg_source_busy_14_026_466_AND_NOT_m_cfg_ETC___d3470 = !m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_14 != v_sources_13_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351 = + assign NOT_m_vrg_source_busy_15_027_474_AND_NOT_m_cfg_ETC___d3478 = !m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_15 != v_sources_14_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359 = + assign NOT_m_vrg_source_busy_16_028_482_AND_NOT_m_cfg_ETC___d3486 = !m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_16 != v_sources_15_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240 = + assign NOT_m_vrg_source_busy_1_013_363_AND_NOT_m_cfg__ETC___d3367 = !m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247 = + assign NOT_m_vrg_source_busy_2_014_370_AND_NOT_m_cfg__ETC___d3374 = !m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255 = + assign NOT_m_vrg_source_busy_3_015_378_AND_NOT_m_cfg__ETC___d3382 = !m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263 = + assign NOT_m_vrg_source_busy_4_016_386_AND_NOT_m_cfg__ETC___d3390 = !m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271 = + assign NOT_m_vrg_source_busy_5_017_394_AND_NOT_m_cfg__ETC___d3398 = !m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279 = + assign NOT_m_vrg_source_busy_6_018_402_AND_NOT_m_cfg__ETC___d3406 = !m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287 = + assign NOT_m_vrg_source_busy_7_019_410_AND_NOT_m_cfg__ETC___d3414 = !m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295 = + assign NOT_m_vrg_source_busy_8_020_418_AND_NOT_m_cfg__ETC___d3422 = !m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ; - assign NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303 = + assign NOT_m_vrg_source_busy_9_021_426_AND_NOT_m_cfg__ETC___d3430 = !m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 && m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ; assign _dfoo1 = - source_id__h64554 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo10 = - (source_id__h64554 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo100 = - (source_id__h63344 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo32 ; assign _dfoo1000 = - (source_id__h47614 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo932 ; assign _dfoo1001 = - source_id__h47614 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo865 ; assign _dfoo1002 = - (source_id__h47614 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo934 ; assign _dfoo1003 = - source_id__h47614 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo867 ; assign _dfoo1004 = - (source_id__h47614 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo936 ; assign _dfoo1005 = - source_id__h47614 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo869 ; assign _dfoo1006 = - (source_id__h47614 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo938 ; assign _dfoo1007 = - source_id__h47614 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo871 ; assign _dfoo1008 = - (source_id__h47614 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo940 ; assign _dfoo1009 = - source_id__h47614 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo873 ; assign _dfoo1010 = - (source_id__h47614 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo942 ; assign _dfoo1011 = - source_id__h47614 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo875 ; assign _dfoo1012 = - (source_id__h47614 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo944 ; assign _dfoo1013 = - source_id__h47614 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo877 ; assign _dfoo1014 = - (source_id__h47614 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo946 ; assign _dfoo1015 = - source_id__h47614 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo879 ; assign _dfoo1016 = - (source_id__h47614 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo948 ; assign _dfoo1017 = - source_id__h47614 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo881 ; assign _dfoo1018 = - (source_id__h47614 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo950 ; assign _dfoo1019 = - source_id__h47614 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo883 ; assign _dfoo102 = - (source_id__h63344 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo34 ; assign _dfoo1020 = - (source_id__h47614 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo952 ; assign _dfoo1022 = - (source_id__h46404 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo954 ; assign _dfoo1024 = - (source_id__h46404 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo956 ; assign _dfoo1026 = - (source_id__h46404 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo958 ; assign _dfoo1028 = - (source_id__h46404 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo960 ; assign _dfoo1030 = - (source_id__h46404 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo962 ; assign _dfoo1032 = - (source_id__h46404 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo964 ; assign _dfoo1034 = - (source_id__h46404 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo966 ; assign _dfoo1036 = - (source_id__h46404 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo968 ; assign _dfoo1038 = - (source_id__h46404 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo970 ; assign _dfoo104 = - (source_id__h63344 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo36 ; assign _dfoo1040 = - (source_id__h46404 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo972 ; assign _dfoo1042 = - (source_id__h46404 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo974 ; assign _dfoo1044 = - (source_id__h46404 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo976 ; assign _dfoo1046 = - (source_id__h46404 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo978 ; assign _dfoo1048 = - (source_id__h46404 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo980 ; assign _dfoo1050 = - (source_id__h46404 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo982 ; assign _dfoo1052 = - (source_id__h46404 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo984 ; assign _dfoo1054 = - (source_id__h46404 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo986 ; assign _dfoo1056 = - (source_id__h46404 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo988 ; assign _dfoo1058 = - (source_id__h46404 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo990 ; assign _dfoo106 = - (source_id__h63344 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo38 ; assign _dfoo1060 = - (source_id__h46404 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo992 ; assign _dfoo1062 = - (source_id__h46404 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo994 ; assign _dfoo1064 = - (source_id__h46404 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo996 ; assign _dfoo1066 = - (source_id__h46404 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo998 ; assign _dfoo1068 = - (source_id__h46404 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1000 ; assign _dfoo1070 = - (source_id__h46404 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1002 ; assign _dfoo1072 = - (source_id__h46404 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1004 ; assign _dfoo1074 = - (source_id__h46404 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1006 ; assign _dfoo1076 = - (source_id__h46404 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1008 ; assign _dfoo1078 = - (source_id__h46404 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1010 ; assign _dfoo108 = - (source_id__h63344 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo40 ; assign _dfoo1080 = - (source_id__h46404 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1012 ; assign _dfoo1082 = - (source_id__h46404 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1014 ; assign _dfoo1084 = - (source_id__h46404 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1016 ; assign _dfoo1086 = - (source_id__h46404 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1018 ; assign _dfoo1088 = - (source_id__h46404 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835) ? - wdata32__h26921[15] : + (source_id__h49251 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947) ? + wdata32__h29733[15] : _dfoo1020 ; assign _dfoo1089 = - source_id__h45194 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo953 ; assign _dfoo1090 = - (source_id__h45194 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1022 ; assign _dfoo1091 = - source_id__h45194 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo955 ; assign _dfoo1092 = - (source_id__h45194 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1024 ; assign _dfoo1093 = - source_id__h45194 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo957 ; assign _dfoo1094 = - (source_id__h45194 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1026 ; assign _dfoo1095 = - source_id__h45194 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo959 ; assign _dfoo1096 = - (source_id__h45194 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1028 ; assign _dfoo1097 = - source_id__h45194 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo961 ; assign _dfoo1098 = - (source_id__h45194 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1030 ; assign _dfoo1099 = - source_id__h45194 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo963 ; assign _dfoo11 = - source_id__h64554 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo110 = - (source_id__h63344 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo42 ; assign _dfoo1100 = - (source_id__h45194 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1032 ; assign _dfoo1101 = - source_id__h45194 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo965 ; assign _dfoo1102 = - (source_id__h45194 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1034 ; assign _dfoo1103 = - source_id__h45194 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo967 ; assign _dfoo1104 = - (source_id__h45194 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1036 ; assign _dfoo1105 = - source_id__h45194 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo969 ; assign _dfoo1106 = - (source_id__h45194 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1038 ; assign _dfoo1107 = - source_id__h45194 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo971 ; assign _dfoo1108 = - (source_id__h45194 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1040 ; assign _dfoo1109 = - source_id__h45194 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo973 ; assign _dfoo1110 = - (source_id__h45194 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1042 ; assign _dfoo1111 = - source_id__h45194 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo975 ; assign _dfoo1112 = - (source_id__h45194 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1044 ; assign _dfoo1113 = - source_id__h45194 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo977 ; assign _dfoo1114 = - (source_id__h45194 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1046 ; assign _dfoo1115 = - source_id__h45194 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo979 ; assign _dfoo1116 = - (source_id__h45194 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1048 ; assign _dfoo1117 = - source_id__h45194 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo981 ; assign _dfoo1118 = - (source_id__h45194 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1050 ; assign _dfoo1119 = - source_id__h45194 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo983 ; assign _dfoo112 = - (source_id__h63344 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo44 ; assign _dfoo1120 = - (source_id__h45194 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1052 ; assign _dfoo1121 = - source_id__h45194 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo985 ; assign _dfoo1122 = - (source_id__h45194 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1054 ; assign _dfoo1123 = - source_id__h45194 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo987 ; assign _dfoo1124 = - (source_id__h45194 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1056 ; assign _dfoo1125 = - source_id__h45194 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo989 ; assign _dfoo1126 = - (source_id__h45194 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1058 ; assign _dfoo1127 = - source_id__h45194 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo991 ; assign _dfoo1128 = - (source_id__h45194 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1060 ; assign _dfoo1129 = - source_id__h45194 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo993 ; assign _dfoo1130 = - (source_id__h45194 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1062 ; assign _dfoo1131 = - source_id__h45194 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo995 ; assign _dfoo1132 = - (source_id__h45194 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1064 ; assign _dfoo1133 = - source_id__h45194 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo997 ; assign _dfoo1134 = - (source_id__h45194 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1066 ; assign _dfoo1135 = - source_id__h45194 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo999 ; assign _dfoo1136 = - (source_id__h45194 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1068 ; assign _dfoo1137 = - source_id__h45194 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1001 ; assign _dfoo1138 = - (source_id__h45194 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1070 ; assign _dfoo1139 = - source_id__h45194 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1003 ; assign _dfoo114 = - (source_id__h63344 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo46 ; assign _dfoo1140 = - (source_id__h45194 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1072 ; assign _dfoo1141 = - source_id__h45194 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1005 ; assign _dfoo1142 = - (source_id__h45194 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1074 ; assign _dfoo1143 = - source_id__h45194 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1007 ; assign _dfoo1144 = - (source_id__h45194 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1076 ; assign _dfoo1145 = - source_id__h45194 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1009 ; assign _dfoo1146 = - (source_id__h45194 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1078 ; assign _dfoo1147 = - source_id__h45194 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1011 ; assign _dfoo1148 = - (source_id__h45194 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1080 ; assign _dfoo1149 = - source_id__h45194 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1013 ; assign _dfoo1150 = - (source_id__h45194 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1082 ; assign _dfoo1151 = - source_id__h45194 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1015 ; assign _dfoo1152 = - (source_id__h45194 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1084 ; assign _dfoo1153 = - source_id__h45194 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1017 ; assign _dfoo1154 = - (source_id__h45194 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1086 ; assign _dfoo1155 = - source_id__h45194 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774 || - source_id__h46404 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1835 || + source_id__h48041 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886 || + source_id__h49251 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1947 || _dfoo1019 ; assign _dfoo1156 = - (source_id__h45194 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1774) ? - wdata32__h26921[14] : + (source_id__h48041 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1886) ? + wdata32__h29733[14] : _dfoo1088 ; assign _dfoo1158 = - (source_id__h43984 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1090 ; assign _dfoo116 = - (source_id__h63344 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo48 ; assign _dfoo1160 = - (source_id__h43984 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1092 ; assign _dfoo1162 = - (source_id__h43984 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1094 ; assign _dfoo1164 = - (source_id__h43984 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1096 ; assign _dfoo1166 = - (source_id__h43984 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1098 ; assign _dfoo1168 = - (source_id__h43984 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1100 ; assign _dfoo1170 = - (source_id__h43984 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1102 ; assign _dfoo1172 = - (source_id__h43984 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1104 ; assign _dfoo1174 = - (source_id__h43984 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1106 ; assign _dfoo1176 = - (source_id__h43984 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1108 ; assign _dfoo1178 = - (source_id__h43984 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1110 ; assign _dfoo118 = - (source_id__h63344 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo50 ; assign _dfoo1180 = - (source_id__h43984 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1112 ; assign _dfoo1182 = - (source_id__h43984 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1114 ; assign _dfoo1184 = - (source_id__h43984 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1116 ; assign _dfoo1186 = - (source_id__h43984 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1118 ; assign _dfoo1188 = - (source_id__h43984 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1120 ; assign _dfoo1190 = - (source_id__h43984 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1122 ; assign _dfoo1192 = - (source_id__h43984 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1124 ; assign _dfoo1194 = - (source_id__h43984 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1126 ; assign _dfoo1196 = - (source_id__h43984 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1128 ; assign _dfoo1198 = - (source_id__h43984 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1130 ; assign _dfoo12 = - (source_id__h64554 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo120 = - (source_id__h63344 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo52 ; assign _dfoo1200 = - (source_id__h43984 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1132 ; assign _dfoo1202 = - (source_id__h43984 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1134 ; assign _dfoo1204 = - (source_id__h43984 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1136 ; assign _dfoo1206 = - (source_id__h43984 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1138 ; assign _dfoo1208 = - (source_id__h43984 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1140 ; assign _dfoo1210 = - (source_id__h43984 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1142 ; assign _dfoo1212 = - (source_id__h43984 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1144 ; assign _dfoo1214 = - (source_id__h43984 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1146 ; assign _dfoo1216 = - (source_id__h43984 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1148 ; assign _dfoo1218 = - (source_id__h43984 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1150 ; assign _dfoo122 = - (source_id__h63344 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo54 ; assign _dfoo1220 = - (source_id__h43984 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1152 ; assign _dfoo1222 = - (source_id__h43984 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1154 ; assign _dfoo1224 = - (source_id__h43984 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713) ? - wdata32__h26921[13] : + (source_id__h46831 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825) ? + wdata32__h29733[13] : _dfoo1156 ; assign _dfoo1225 = - source_id__h42774 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1089 ; assign _dfoo1226 = - (source_id__h42774 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1158 ; assign _dfoo1227 = - source_id__h42774 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1091 ; assign _dfoo1228 = - (source_id__h42774 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1160 ; assign _dfoo1229 = - source_id__h42774 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1093 ; assign _dfoo1230 = - (source_id__h42774 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1162 ; assign _dfoo1231 = - source_id__h42774 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1095 ; assign _dfoo1232 = - (source_id__h42774 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1164 ; assign _dfoo1233 = - source_id__h42774 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1097 ; assign _dfoo1234 = - (source_id__h42774 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1166 ; assign _dfoo1235 = - source_id__h42774 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1099 ; assign _dfoo1236 = - (source_id__h42774 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1168 ; assign _dfoo1237 = - source_id__h42774 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1101 ; assign _dfoo1238 = - (source_id__h42774 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1170 ; assign _dfoo1239 = - source_id__h42774 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1103 ; assign _dfoo124 = - (source_id__h63344 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo56 ; assign _dfoo1240 = - (source_id__h42774 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1172 ; assign _dfoo1241 = - source_id__h42774 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1105 ; assign _dfoo1242 = - (source_id__h42774 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1174 ; assign _dfoo1243 = - source_id__h42774 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1107 ; assign _dfoo1244 = - (source_id__h42774 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1176 ; assign _dfoo1245 = - source_id__h42774 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1109 ; assign _dfoo1246 = - (source_id__h42774 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1178 ; assign _dfoo1247 = - source_id__h42774 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1111 ; assign _dfoo1248 = - (source_id__h42774 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1180 ; assign _dfoo1249 = - source_id__h42774 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1113 ; assign _dfoo1250 = - (source_id__h42774 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1182 ; assign _dfoo1251 = - source_id__h42774 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1115 ; assign _dfoo1252 = - (source_id__h42774 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1184 ; assign _dfoo1253 = - source_id__h42774 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1117 ; assign _dfoo1254 = - (source_id__h42774 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1186 ; assign _dfoo1255 = - source_id__h42774 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1119 ; assign _dfoo1256 = - (source_id__h42774 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1188 ; assign _dfoo1257 = - source_id__h42774 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1121 ; assign _dfoo1258 = - (source_id__h42774 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1190 ; assign _dfoo1259 = - source_id__h42774 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1123 ; assign _dfoo126 = - (source_id__h63344 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo58 ; assign _dfoo1260 = - (source_id__h42774 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1192 ; assign _dfoo1261 = - source_id__h42774 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1125 ; assign _dfoo1262 = - (source_id__h42774 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1194 ; assign _dfoo1263 = - source_id__h42774 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1127 ; assign _dfoo1264 = - (source_id__h42774 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1196 ; assign _dfoo1265 = - source_id__h42774 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1129 ; assign _dfoo1266 = - (source_id__h42774 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1198 ; assign _dfoo1267 = - source_id__h42774 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1131 ; assign _dfoo1268 = - (source_id__h42774 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1200 ; assign _dfoo1269 = - source_id__h42774 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1133 ; assign _dfoo1270 = - (source_id__h42774 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1202 ; assign _dfoo1271 = - source_id__h42774 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1135 ; assign _dfoo1272 = - (source_id__h42774 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1204 ; assign _dfoo1273 = - source_id__h42774 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1137 ; assign _dfoo1274 = - (source_id__h42774 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1206 ; assign _dfoo1275 = - source_id__h42774 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1139 ; assign _dfoo1276 = - (source_id__h42774 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1208 ; assign _dfoo1277 = - source_id__h42774 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1141 ; assign _dfoo1278 = - (source_id__h42774 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1210 ; assign _dfoo1279 = - source_id__h42774 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1143 ; assign _dfoo128 = - (source_id__h63344 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo60 ; assign _dfoo1280 = - (source_id__h42774 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1212 ; assign _dfoo1281 = - source_id__h42774 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1145 ; assign _dfoo1282 = - (source_id__h42774 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1214 ; assign _dfoo1283 = - source_id__h42774 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1147 ; assign _dfoo1284 = - (source_id__h42774 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1216 ; assign _dfoo1285 = - source_id__h42774 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1149 ; assign _dfoo1286 = - (source_id__h42774 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1218 ; assign _dfoo1287 = - source_id__h42774 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1151 ; assign _dfoo1288 = - (source_id__h42774 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1220 ; assign _dfoo1289 = - source_id__h42774 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1153 ; assign _dfoo1290 = - (source_id__h42774 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1222 ; assign _dfoo1291 = - source_id__h42774 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652 || - source_id__h43984 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1713 || + source_id__h45621 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764 || + source_id__h46831 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1825 || _dfoo1155 ; assign _dfoo1292 = - (source_id__h42774 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1652) ? - wdata32__h26921[12] : + (source_id__h45621 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1764) ? + wdata32__h29733[12] : _dfoo1224 ; assign _dfoo1294 = - (source_id__h41564 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1226 ; assign _dfoo1296 = - (source_id__h41564 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1228 ; assign _dfoo1298 = - (source_id__h41564 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1230 ; assign _dfoo13 = - source_id__h64554 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo130 = - (source_id__h63344 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo62 ; assign _dfoo1300 = - (source_id__h41564 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1232 ; assign _dfoo1302 = - (source_id__h41564 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1234 ; assign _dfoo1304 = - (source_id__h41564 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1236 ; assign _dfoo1306 = - (source_id__h41564 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1238 ; assign _dfoo1308 = - (source_id__h41564 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1240 ; assign _dfoo1310 = - (source_id__h41564 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1242 ; assign _dfoo1312 = - (source_id__h41564 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1244 ; assign _dfoo1314 = - (source_id__h41564 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1246 ; assign _dfoo1316 = - (source_id__h41564 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1248 ; assign _dfoo1318 = - (source_id__h41564 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1250 ; assign _dfoo132 = - (source_id__h63344 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo64 ; assign _dfoo1320 = - (source_id__h41564 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1252 ; assign _dfoo1322 = - (source_id__h41564 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1254 ; assign _dfoo1324 = - (source_id__h41564 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1256 ; assign _dfoo1326 = - (source_id__h41564 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1258 ; assign _dfoo1328 = - (source_id__h41564 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1260 ; assign _dfoo1330 = - (source_id__h41564 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1262 ; assign _dfoo1332 = - (source_id__h41564 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1264 ; assign _dfoo1334 = - (source_id__h41564 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1266 ; assign _dfoo1336 = - (source_id__h41564 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1268 ; assign _dfoo1338 = - (source_id__h41564 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1270 ; assign _dfoo134 = - (source_id__h63344 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo66 ; assign _dfoo1340 = - (source_id__h41564 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1272 ; assign _dfoo1342 = - (source_id__h41564 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1274 ; assign _dfoo1344 = - (source_id__h41564 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1276 ; assign _dfoo1346 = - (source_id__h41564 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1278 ; assign _dfoo1348 = - (source_id__h41564 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1280 ; assign _dfoo1350 = - (source_id__h41564 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1282 ; assign _dfoo1352 = - (source_id__h41564 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1284 ; assign _dfoo1354 = - (source_id__h41564 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1286 ; assign _dfoo1356 = - (source_id__h41564 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1288 ; assign _dfoo1358 = - (source_id__h41564 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1290 ; assign _dfoo136 = - (source_id__h63344 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo68 ; assign _dfoo1360 = - (source_id__h41564 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591) ? - wdata32__h26921[11] : + (source_id__h44411 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703) ? + wdata32__h29733[11] : _dfoo1292 ; assign _dfoo1361 = - source_id__h40354 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1225 ; assign _dfoo1362 = - (source_id__h40354 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1294 ; assign _dfoo1363 = - source_id__h40354 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1227 ; assign _dfoo1364 = - (source_id__h40354 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1296 ; assign _dfoo1365 = - source_id__h40354 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1229 ; assign _dfoo1366 = - (source_id__h40354 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1298 ; assign _dfoo1367 = - source_id__h40354 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1231 ; assign _dfoo1368 = - (source_id__h40354 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1300 ; assign _dfoo1369 = - source_id__h40354 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1233 ; assign _dfoo137 = - source_id__h62134 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo1 ; assign _dfoo1370 = - (source_id__h40354 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1302 ; assign _dfoo1371 = - source_id__h40354 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1235 ; assign _dfoo1372 = - (source_id__h40354 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1304 ; assign _dfoo1373 = - source_id__h40354 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1237 ; assign _dfoo1374 = - (source_id__h40354 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1306 ; assign _dfoo1375 = - source_id__h40354 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1239 ; assign _dfoo1376 = - (source_id__h40354 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1308 ; assign _dfoo1377 = - source_id__h40354 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1241 ; assign _dfoo1378 = - (source_id__h40354 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1310 ; assign _dfoo1379 = - source_id__h40354 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1243 ; assign _dfoo138 = - (source_id__h62134 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo70 ; assign _dfoo1380 = - (source_id__h40354 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1312 ; assign _dfoo1381 = - source_id__h40354 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1245 ; assign _dfoo1382 = - (source_id__h40354 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1314 ; assign _dfoo1383 = - source_id__h40354 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1247 ; assign _dfoo1384 = - (source_id__h40354 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1316 ; assign _dfoo1385 = - source_id__h40354 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1249 ; assign _dfoo1386 = - (source_id__h40354 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1318 ; assign _dfoo1387 = - source_id__h40354 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1251 ; assign _dfoo1388 = - (source_id__h40354 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1320 ; assign _dfoo1389 = - source_id__h40354 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1253 ; assign _dfoo139 = - source_id__h62134 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo3 ; assign _dfoo1390 = - (source_id__h40354 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1322 ; assign _dfoo1391 = - source_id__h40354 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1255 ; assign _dfoo1392 = - (source_id__h40354 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1324 ; assign _dfoo1393 = - source_id__h40354 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1257 ; assign _dfoo1394 = - (source_id__h40354 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1326 ; assign _dfoo1395 = - source_id__h40354 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1259 ; assign _dfoo1396 = - (source_id__h40354 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1328 ; assign _dfoo1397 = - source_id__h40354 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1261 ; assign _dfoo1398 = - (source_id__h40354 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1330 ; assign _dfoo1399 = - source_id__h40354 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1263 ; assign _dfoo14 = - (source_id__h64554 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo140 = - (source_id__h62134 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo72 ; assign _dfoo1400 = - (source_id__h40354 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1332 ; assign _dfoo1401 = - source_id__h40354 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1265 ; assign _dfoo1402 = - (source_id__h40354 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1334 ; assign _dfoo1403 = - source_id__h40354 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1267 ; assign _dfoo1404 = - (source_id__h40354 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1336 ; assign _dfoo1405 = - source_id__h40354 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1269 ; assign _dfoo1406 = - (source_id__h40354 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1338 ; assign _dfoo1407 = - source_id__h40354 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1271 ; assign _dfoo1408 = - (source_id__h40354 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1340 ; assign _dfoo1409 = - source_id__h40354 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1273 ; assign _dfoo141 = - source_id__h62134 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo5 ; assign _dfoo1410 = - (source_id__h40354 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1342 ; assign _dfoo1411 = - source_id__h40354 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1275 ; assign _dfoo1412 = - (source_id__h40354 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1344 ; assign _dfoo1413 = - source_id__h40354 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1277 ; assign _dfoo1414 = - (source_id__h40354 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1346 ; assign _dfoo1415 = - source_id__h40354 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1279 ; assign _dfoo1416 = - (source_id__h40354 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1348 ; assign _dfoo1417 = - source_id__h40354 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1281 ; assign _dfoo1418 = - (source_id__h40354 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1350 ; assign _dfoo1419 = - source_id__h40354 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1283 ; assign _dfoo142 = - (source_id__h62134 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo74 ; assign _dfoo1420 = - (source_id__h40354 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1352 ; assign _dfoo1421 = - source_id__h40354 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1285 ; assign _dfoo1422 = - (source_id__h40354 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1354 ; assign _dfoo1423 = - source_id__h40354 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1287 ; assign _dfoo1424 = - (source_id__h40354 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1356 ; assign _dfoo1425 = - source_id__h40354 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1289 ; assign _dfoo1426 = - (source_id__h40354 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1358 ; assign _dfoo1427 = - source_id__h40354 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530 || - source_id__h41564 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1591 || + source_id__h43201 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642 || + source_id__h44411 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1703 || _dfoo1291 ; assign _dfoo1428 = - (source_id__h40354 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1530) ? - wdata32__h26921[10] : + (source_id__h43201 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1642) ? + wdata32__h29733[10] : _dfoo1360 ; assign _dfoo143 = - source_id__h62134 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo7 ; assign _dfoo1430 = - (source_id__h39144 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1362 ; assign _dfoo1432 = - (source_id__h39144 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1364 ; assign _dfoo1434 = - (source_id__h39144 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1366 ; assign _dfoo1436 = - (source_id__h39144 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1368 ; assign _dfoo1438 = - (source_id__h39144 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1370 ; assign _dfoo144 = - (source_id__h62134 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo76 ; assign _dfoo1440 = - (source_id__h39144 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1372 ; assign _dfoo1442 = - (source_id__h39144 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1374 ; assign _dfoo1444 = - (source_id__h39144 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1376 ; assign _dfoo1446 = - (source_id__h39144 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1378 ; assign _dfoo1448 = - (source_id__h39144 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1380 ; assign _dfoo145 = - source_id__h62134 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo9 ; assign _dfoo1450 = - (source_id__h39144 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1382 ; assign _dfoo1452 = - (source_id__h39144 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1384 ; assign _dfoo1454 = - (source_id__h39144 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1386 ; assign _dfoo1456 = - (source_id__h39144 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1388 ; assign _dfoo1458 = - (source_id__h39144 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1390 ; assign _dfoo146 = - (source_id__h62134 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo78 ; assign _dfoo1460 = - (source_id__h39144 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1392 ; assign _dfoo1462 = - (source_id__h39144 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1394 ; assign _dfoo1464 = - (source_id__h39144 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1396 ; assign _dfoo1466 = - (source_id__h39144 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1398 ; assign _dfoo1468 = - (source_id__h39144 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1400 ; assign _dfoo147 = - source_id__h62134 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo11 ; assign _dfoo1470 = - (source_id__h39144 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1402 ; assign _dfoo1472 = - (source_id__h39144 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1404 ; assign _dfoo1474 = - (source_id__h39144 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1406 ; assign _dfoo1476 = - (source_id__h39144 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1408 ; assign _dfoo1478 = - (source_id__h39144 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1410 ; assign _dfoo148 = - (source_id__h62134 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo80 ; assign _dfoo1480 = - (source_id__h39144 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1412 ; assign _dfoo1482 = - (source_id__h39144 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1414 ; assign _dfoo1484 = - (source_id__h39144 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1416 ; assign _dfoo1486 = - (source_id__h39144 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1418 ; assign _dfoo1488 = - (source_id__h39144 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1420 ; assign _dfoo149 = - source_id__h62134 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo13 ; assign _dfoo1490 = - (source_id__h39144 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1422 ; assign _dfoo1492 = - (source_id__h39144 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1424 ; assign _dfoo1494 = - (source_id__h39144 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1426 ; assign _dfoo1496 = - (source_id__h39144 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469) ? - wdata32__h26921[9] : + (source_id__h41991 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581) ? + wdata32__h29733[9] : _dfoo1428 ; assign _dfoo1497 = - source_id__h37934 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1361 ; assign _dfoo1498 = - (source_id__h37934 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1430 ; assign _dfoo1499 = - source_id__h37934 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1363 ; assign _dfoo15 = - source_id__h64554 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo150 = - (source_id__h62134 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo82 ; assign _dfoo1500 = - (source_id__h37934 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1432 ; assign _dfoo1501 = - source_id__h37934 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1365 ; assign _dfoo1502 = - (source_id__h37934 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1434 ; assign _dfoo1503 = - source_id__h37934 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1367 ; assign _dfoo1504 = - (source_id__h37934 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1436 ; assign _dfoo1505 = - source_id__h37934 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1369 ; assign _dfoo1506 = - (source_id__h37934 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1438 ; assign _dfoo1507 = - source_id__h37934 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1371 ; assign _dfoo1508 = - (source_id__h37934 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1440 ; assign _dfoo1509 = - source_id__h37934 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1373 ; assign _dfoo151 = - source_id__h62134 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo15 ; assign _dfoo1510 = - (source_id__h37934 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1442 ; assign _dfoo1511 = - source_id__h37934 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1375 ; assign _dfoo1512 = - (source_id__h37934 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1444 ; assign _dfoo1513 = - source_id__h37934 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1377 ; assign _dfoo1514 = - (source_id__h37934 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1446 ; assign _dfoo1515 = - source_id__h37934 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1379 ; assign _dfoo1516 = - (source_id__h37934 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1448 ; assign _dfoo1517 = - source_id__h37934 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1381 ; assign _dfoo1518 = - (source_id__h37934 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1450 ; assign _dfoo1519 = - source_id__h37934 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1383 ; assign _dfoo152 = - (source_id__h62134 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo84 ; assign _dfoo1520 = - (source_id__h37934 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1452 ; assign _dfoo1521 = - source_id__h37934 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1385 ; assign _dfoo1522 = - (source_id__h37934 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1454 ; assign _dfoo1523 = - source_id__h37934 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1387 ; assign _dfoo1524 = - (source_id__h37934 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1456 ; assign _dfoo1525 = - source_id__h37934 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1389 ; assign _dfoo1526 = - (source_id__h37934 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1458 ; assign _dfoo1527 = - source_id__h37934 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1391 ; assign _dfoo1528 = - (source_id__h37934 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1460 ; assign _dfoo1529 = - source_id__h37934 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1393 ; assign _dfoo153 = - source_id__h62134 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo17 ; assign _dfoo1530 = - (source_id__h37934 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1462 ; assign _dfoo1531 = - source_id__h37934 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1395 ; assign _dfoo1532 = - (source_id__h37934 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1464 ; assign _dfoo1533 = - source_id__h37934 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1397 ; assign _dfoo1534 = - (source_id__h37934 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1466 ; assign _dfoo1535 = - source_id__h37934 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1399 ; assign _dfoo1536 = - (source_id__h37934 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1468 ; assign _dfoo1537 = - source_id__h37934 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1401 ; assign _dfoo1538 = - (source_id__h37934 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1470 ; assign _dfoo1539 = - source_id__h37934 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1403 ; assign _dfoo154 = - (source_id__h62134 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo86 ; assign _dfoo1540 = - (source_id__h37934 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1472 ; assign _dfoo1541 = - source_id__h37934 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1405 ; assign _dfoo1542 = - (source_id__h37934 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1474 ; assign _dfoo1543 = - source_id__h37934 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1407 ; assign _dfoo1544 = - (source_id__h37934 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1476 ; assign _dfoo1545 = - source_id__h37934 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1409 ; assign _dfoo1546 = - (source_id__h37934 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1478 ; assign _dfoo1547 = - source_id__h37934 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1411 ; assign _dfoo1548 = - (source_id__h37934 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1480 ; assign _dfoo1549 = - source_id__h37934 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1413 ; assign _dfoo155 = - source_id__h62134 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo19 ; assign _dfoo1550 = - (source_id__h37934 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1482 ; assign _dfoo1551 = - source_id__h37934 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1415 ; assign _dfoo1552 = - (source_id__h37934 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1484 ; assign _dfoo1553 = - source_id__h37934 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1417 ; assign _dfoo1554 = - (source_id__h37934 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1486 ; assign _dfoo1555 = - source_id__h37934 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1419 ; assign _dfoo1556 = - (source_id__h37934 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1488 ; assign _dfoo1557 = - source_id__h37934 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1421 ; assign _dfoo1558 = - (source_id__h37934 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1490 ; assign _dfoo1559 = - source_id__h37934 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1423 ; assign _dfoo156 = - (source_id__h62134 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo88 ; assign _dfoo1560 = - (source_id__h37934 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1492 ; assign _dfoo1561 = - source_id__h37934 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1425 ; assign _dfoo1562 = - (source_id__h37934 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1494 ; assign _dfoo1563 = - source_id__h37934 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408 || - source_id__h39144 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1469 || + source_id__h40781 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520 || + source_id__h41991 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1581 || _dfoo1427 ; assign _dfoo1564 = - (source_id__h37934 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1408) ? - wdata32__h26921[8] : + (source_id__h40781 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1520) ? + wdata32__h29733[8] : _dfoo1496 ; assign _dfoo1566 = - (source_id__h36724 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1498 ; assign _dfoo1568 = - (source_id__h36724 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1500 ; assign _dfoo157 = - source_id__h62134 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo21 ; assign _dfoo1570 = - (source_id__h36724 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1502 ; assign _dfoo1572 = - (source_id__h36724 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1504 ; assign _dfoo1574 = - (source_id__h36724 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1506 ; assign _dfoo1576 = - (source_id__h36724 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1508 ; assign _dfoo1578 = - (source_id__h36724 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1510 ; assign _dfoo158 = - (source_id__h62134 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo90 ; assign _dfoo1580 = - (source_id__h36724 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1512 ; assign _dfoo1582 = - (source_id__h36724 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1514 ; assign _dfoo1584 = - (source_id__h36724 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1516 ; assign _dfoo1586 = - (source_id__h36724 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1518 ; assign _dfoo1588 = - (source_id__h36724 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1520 ; assign _dfoo159 = - source_id__h62134 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo23 ; assign _dfoo1590 = - (source_id__h36724 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1522 ; assign _dfoo1592 = - (source_id__h36724 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1524 ; assign _dfoo1594 = - (source_id__h36724 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1526 ; assign _dfoo1596 = - (source_id__h36724 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1528 ; assign _dfoo1598 = - (source_id__h36724 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1530 ; assign _dfoo16 = - (source_id__h64554 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo160 = - (source_id__h62134 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo92 ; assign _dfoo1600 = - (source_id__h36724 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1532 ; assign _dfoo1602 = - (source_id__h36724 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1534 ; assign _dfoo1604 = - (source_id__h36724 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1536 ; assign _dfoo1606 = - (source_id__h36724 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1538 ; assign _dfoo1608 = - (source_id__h36724 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1540 ; assign _dfoo161 = - source_id__h62134 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo25 ; assign _dfoo1610 = - (source_id__h36724 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1542 ; assign _dfoo1612 = - (source_id__h36724 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1544 ; assign _dfoo1614 = - (source_id__h36724 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1546 ; assign _dfoo1616 = - (source_id__h36724 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1548 ; assign _dfoo1618 = - (source_id__h36724 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1550 ; assign _dfoo162 = - (source_id__h62134 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo94 ; assign _dfoo1620 = - (source_id__h36724 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1552 ; assign _dfoo1622 = - (source_id__h36724 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1554 ; assign _dfoo1624 = - (source_id__h36724 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1556 ; assign _dfoo1626 = - (source_id__h36724 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1558 ; assign _dfoo1628 = - (source_id__h36724 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1560 ; assign _dfoo163 = - source_id__h62134 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo27 ; assign _dfoo1630 = - (source_id__h36724 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1562 ; assign _dfoo1632 = - (source_id__h36724 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347) ? - wdata32__h26921[7] : + (source_id__h39571 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459) ? + wdata32__h29733[7] : _dfoo1564 ; assign _dfoo1633 = - source_id__h35514 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1497 ; assign _dfoo1634 = - (source_id__h35514 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1566 ; assign _dfoo1635 = - source_id__h35514 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1499 ; assign _dfoo1636 = - (source_id__h35514 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1568 ; assign _dfoo1637 = - source_id__h35514 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1501 ; assign _dfoo1638 = - (source_id__h35514 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1570 ; assign _dfoo1639 = - source_id__h35514 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1503 ; assign _dfoo164 = - (source_id__h62134 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo96 ; assign _dfoo1640 = - (source_id__h35514 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1572 ; assign _dfoo1641 = - source_id__h35514 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1505 ; assign _dfoo1642 = - (source_id__h35514 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1574 ; assign _dfoo1643 = - source_id__h35514 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1507 ; assign _dfoo1644 = - (source_id__h35514 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1576 ; assign _dfoo1645 = - source_id__h35514 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1509 ; assign _dfoo1646 = - (source_id__h35514 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1578 ; assign _dfoo1647 = - source_id__h35514 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1511 ; assign _dfoo1648 = - (source_id__h35514 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1580 ; assign _dfoo1649 = - source_id__h35514 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1513 ; assign _dfoo165 = - source_id__h62134 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo29 ; assign _dfoo1650 = - (source_id__h35514 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1582 ; assign _dfoo1651 = - source_id__h35514 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1515 ; assign _dfoo1652 = - (source_id__h35514 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1584 ; assign _dfoo1653 = - source_id__h35514 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1517 ; assign _dfoo1654 = - (source_id__h35514 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1586 ; assign _dfoo1655 = - source_id__h35514 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1519 ; assign _dfoo1656 = - (source_id__h35514 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1588 ; assign _dfoo1657 = - source_id__h35514 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1521 ; assign _dfoo1658 = - (source_id__h35514 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1590 ; assign _dfoo1659 = - source_id__h35514 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1523 ; assign _dfoo166 = - (source_id__h62134 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo98 ; assign _dfoo1660 = - (source_id__h35514 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1592 ; assign _dfoo1661 = - source_id__h35514 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1525 ; assign _dfoo1662 = - (source_id__h35514 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1594 ; assign _dfoo1663 = - source_id__h35514 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1527 ; assign _dfoo1664 = - (source_id__h35514 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1596 ; assign _dfoo1665 = - source_id__h35514 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1529 ; assign _dfoo1666 = - (source_id__h35514 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1598 ; assign _dfoo1667 = - source_id__h35514 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1531 ; assign _dfoo1668 = - (source_id__h35514 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1600 ; assign _dfoo1669 = - source_id__h35514 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1533 ; assign _dfoo167 = - source_id__h62134 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo31 ; assign _dfoo1670 = - (source_id__h35514 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1602 ; assign _dfoo1671 = - source_id__h35514 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1535 ; assign _dfoo1672 = - (source_id__h35514 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1604 ; assign _dfoo1673 = - source_id__h35514 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1537 ; assign _dfoo1674 = - (source_id__h35514 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1606 ; assign _dfoo1675 = - source_id__h35514 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1539 ; assign _dfoo1676 = - (source_id__h35514 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1608 ; assign _dfoo1677 = - source_id__h35514 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1541 ; assign _dfoo1678 = - (source_id__h35514 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1610 ; assign _dfoo1679 = - source_id__h35514 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1543 ; assign _dfoo168 = - (source_id__h62134 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo100 ; assign _dfoo1680 = - (source_id__h35514 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1612 ; assign _dfoo1681 = - source_id__h35514 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1545 ; assign _dfoo1682 = - (source_id__h35514 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1614 ; assign _dfoo1683 = - source_id__h35514 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1547 ; assign _dfoo1684 = - (source_id__h35514 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1616 ; assign _dfoo1685 = - source_id__h35514 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1549 ; assign _dfoo1686 = - (source_id__h35514 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1618 ; assign _dfoo1687 = - source_id__h35514 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1551 ; assign _dfoo1688 = - (source_id__h35514 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1620 ; assign _dfoo1689 = - source_id__h35514 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1553 ; assign _dfoo169 = - source_id__h62134 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo33 ; assign _dfoo1690 = - (source_id__h35514 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1622 ; assign _dfoo1691 = - source_id__h35514 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1555 ; assign _dfoo1692 = - (source_id__h35514 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1624 ; assign _dfoo1693 = - source_id__h35514 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1557 ; assign _dfoo1694 = - (source_id__h35514 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1626 ; assign _dfoo1695 = - source_id__h35514 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1559 ; assign _dfoo1696 = - (source_id__h35514 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1628 ; assign _dfoo1697 = - source_id__h35514 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1561 ; assign _dfoo1698 = - (source_id__h35514 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1630 ; assign _dfoo1699 = - source_id__h35514 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286 || - source_id__h36724 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1347 || + source_id__h38361 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398 || + source_id__h39571 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1459 || _dfoo1563 ; assign _dfoo17 = - source_id__h64554 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo170 = - (source_id__h62134 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo102 ; assign _dfoo1700 = - (source_id__h35514 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1286) ? - wdata32__h26921[6] : + (source_id__h38361 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1398) ? + wdata32__h29733[6] : _dfoo1632 ; assign _dfoo1702 = - (source_id__h34304 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1634 ; assign _dfoo1704 = - (source_id__h34304 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1636 ; assign _dfoo1706 = - (source_id__h34304 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1638 ; assign _dfoo1708 = - (source_id__h34304 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1640 ; assign _dfoo171 = - source_id__h62134 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo35 ; assign _dfoo1710 = - (source_id__h34304 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1642 ; assign _dfoo1712 = - (source_id__h34304 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1644 ; assign _dfoo1714 = - (source_id__h34304 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1646 ; assign _dfoo1716 = - (source_id__h34304 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1648 ; assign _dfoo1718 = - (source_id__h34304 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1650 ; assign _dfoo172 = - (source_id__h62134 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo104 ; assign _dfoo1720 = - (source_id__h34304 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1652 ; assign _dfoo1722 = - (source_id__h34304 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1654 ; assign _dfoo1724 = - (source_id__h34304 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1656 ; assign _dfoo1726 = - (source_id__h34304 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1658 ; assign _dfoo1728 = - (source_id__h34304 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1660 ; assign _dfoo173 = - source_id__h62134 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo37 ; assign _dfoo1730 = - (source_id__h34304 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1662 ; assign _dfoo1732 = - (source_id__h34304 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1664 ; assign _dfoo1734 = - (source_id__h34304 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1666 ; assign _dfoo1736 = - (source_id__h34304 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1668 ; assign _dfoo1738 = - (source_id__h34304 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1670 ; assign _dfoo174 = - (source_id__h62134 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo106 ; assign _dfoo1740 = - (source_id__h34304 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1672 ; assign _dfoo1742 = - (source_id__h34304 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1674 ; assign _dfoo1744 = - (source_id__h34304 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1676 ; assign _dfoo1746 = - (source_id__h34304 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1678 ; assign _dfoo1748 = - (source_id__h34304 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1680 ; assign _dfoo175 = - source_id__h62134 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo39 ; assign _dfoo1750 = - (source_id__h34304 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1682 ; assign _dfoo1752 = - (source_id__h34304 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1684 ; assign _dfoo1754 = - (source_id__h34304 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1686 ; assign _dfoo1756 = - (source_id__h34304 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1688 ; assign _dfoo1758 = - (source_id__h34304 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1690 ; assign _dfoo176 = - (source_id__h62134 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo108 ; assign _dfoo1760 = - (source_id__h34304 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1692 ; assign _dfoo1762 = - (source_id__h34304 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1694 ; assign _dfoo1764 = - (source_id__h34304 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1696 ; assign _dfoo1766 = - (source_id__h34304 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1698 ; assign _dfoo1768 = - (source_id__h34304 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225) ? - wdata32__h26921[5] : + (source_id__h37151 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337) ? + wdata32__h29733[5] : _dfoo1700 ; assign _dfoo1769 = - source_id__h33094 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1633 ; assign _dfoo177 = - source_id__h62134 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo41 ; assign _dfoo1770 = - (source_id__h33094 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1702 ; assign _dfoo1771 = - source_id__h33094 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1635 ; assign _dfoo1772 = - (source_id__h33094 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1704 ; assign _dfoo1773 = - source_id__h33094 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1637 ; assign _dfoo1774 = - (source_id__h33094 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1706 ; assign _dfoo1775 = - source_id__h33094 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1639 ; assign _dfoo1776 = - (source_id__h33094 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1708 ; assign _dfoo1777 = - source_id__h33094 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1641 ; assign _dfoo1778 = - (source_id__h33094 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1710 ; assign _dfoo1779 = - source_id__h33094 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1643 ; assign _dfoo178 = - (source_id__h62134 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo110 ; assign _dfoo1780 = - (source_id__h33094 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1712 ; assign _dfoo1781 = - source_id__h33094 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1645 ; assign _dfoo1782 = - (source_id__h33094 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1714 ; assign _dfoo1783 = - source_id__h33094 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1647 ; assign _dfoo1784 = - (source_id__h33094 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1716 ; assign _dfoo1785 = - source_id__h33094 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1649 ; assign _dfoo1786 = - (source_id__h33094 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1718 ; assign _dfoo1787 = - source_id__h33094 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1651 ; assign _dfoo1788 = - (source_id__h33094 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1720 ; assign _dfoo1789 = - source_id__h33094 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1653 ; assign _dfoo179 = - source_id__h62134 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo43 ; assign _dfoo1790 = - (source_id__h33094 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1722 ; assign _dfoo1791 = - source_id__h33094 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1655 ; assign _dfoo1792 = - (source_id__h33094 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1724 ; assign _dfoo1793 = - source_id__h33094 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1657 ; assign _dfoo1794 = - (source_id__h33094 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1726 ; assign _dfoo1795 = - source_id__h33094 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1659 ; assign _dfoo1796 = - (source_id__h33094 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1728 ; assign _dfoo1797 = - source_id__h33094 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1661 ; assign _dfoo1798 = - (source_id__h33094 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1730 ; assign _dfoo1799 = - source_id__h33094 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1663 ; assign _dfoo18 = - (source_id__h64554 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo180 = - (source_id__h62134 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo112 ; assign _dfoo1800 = - (source_id__h33094 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1732 ; assign _dfoo1801 = - source_id__h33094 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1665 ; assign _dfoo1802 = - (source_id__h33094 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1734 ; assign _dfoo1803 = - source_id__h33094 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1667 ; assign _dfoo1804 = - (source_id__h33094 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1736 ; assign _dfoo1805 = - source_id__h33094 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1669 ; assign _dfoo1806 = - (source_id__h33094 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1738 ; assign _dfoo1807 = - source_id__h33094 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1671 ; assign _dfoo1808 = - (source_id__h33094 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1740 ; assign _dfoo1809 = - source_id__h33094 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1673 ; assign _dfoo181 = - source_id__h62134 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo45 ; assign _dfoo1810 = - (source_id__h33094 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1742 ; assign _dfoo1811 = - source_id__h33094 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1675 ; assign _dfoo1812 = - (source_id__h33094 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1744 ; assign _dfoo1813 = - source_id__h33094 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1677 ; assign _dfoo1814 = - (source_id__h33094 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1746 ; assign _dfoo1815 = - source_id__h33094 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1679 ; assign _dfoo1816 = - (source_id__h33094 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1748 ; assign _dfoo1817 = - source_id__h33094 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1681 ; assign _dfoo1818 = - (source_id__h33094 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1750 ; assign _dfoo1819 = - source_id__h33094 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1683 ; assign _dfoo182 = - (source_id__h62134 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo114 ; assign _dfoo1820 = - (source_id__h33094 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1752 ; assign _dfoo1821 = - source_id__h33094 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1685 ; assign _dfoo1822 = - (source_id__h33094 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1754 ; assign _dfoo1823 = - source_id__h33094 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1687 ; assign _dfoo1824 = - (source_id__h33094 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1756 ; assign _dfoo1825 = - source_id__h33094 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1689 ; assign _dfoo1826 = - (source_id__h33094 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1758 ; assign _dfoo1827 = - source_id__h33094 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1691 ; assign _dfoo1828 = - (source_id__h33094 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1760 ; assign _dfoo1829 = - source_id__h33094 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1693 ; assign _dfoo183 = - source_id__h62134 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo47 ; assign _dfoo1830 = - (source_id__h33094 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1762 ; assign _dfoo1831 = - source_id__h33094 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1695 ; assign _dfoo1832 = - (source_id__h33094 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1764 ; assign _dfoo1833 = - source_id__h33094 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1697 ; assign _dfoo1834 = - (source_id__h33094 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1766 ; assign _dfoo1835 = - source_id__h33094 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164 || - source_id__h34304 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1225 || + source_id__h35941 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276 || + source_id__h37151 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1337 || _dfoo1699 ; assign _dfoo1836 = - (source_id__h33094 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1164) ? - wdata32__h26921[4] : + (source_id__h35941 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1276) ? + wdata32__h29733[4] : _dfoo1768 ; assign _dfoo1838 = - (source_id__h31884 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1770 ; assign _dfoo184 = - (source_id__h62134 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo116 ; assign _dfoo1840 = - (source_id__h31884 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1772 ; assign _dfoo1842 = - (source_id__h31884 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1774 ; assign _dfoo1844 = - (source_id__h31884 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1776 ; assign _dfoo1846 = - (source_id__h31884 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1778 ; assign _dfoo1848 = - (source_id__h31884 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1780 ; assign _dfoo185 = - source_id__h62134 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo49 ; assign _dfoo1850 = - (source_id__h31884 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1782 ; assign _dfoo1852 = - (source_id__h31884 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1784 ; assign _dfoo1854 = - (source_id__h31884 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1786 ; assign _dfoo1856 = - (source_id__h31884 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1788 ; assign _dfoo1858 = - (source_id__h31884 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1790 ; assign _dfoo186 = - (source_id__h62134 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo118 ; assign _dfoo1860 = - (source_id__h31884 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1792 ; assign _dfoo1862 = - (source_id__h31884 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1794 ; assign _dfoo1864 = - (source_id__h31884 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1796 ; assign _dfoo1866 = - (source_id__h31884 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1798 ; assign _dfoo1868 = - (source_id__h31884 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1800 ; assign _dfoo187 = - source_id__h62134 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo51 ; assign _dfoo1870 = - (source_id__h31884 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1802 ; assign _dfoo1872 = - (source_id__h31884 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1804 ; assign _dfoo1874 = - (source_id__h31884 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1806 ; assign _dfoo1876 = - (source_id__h31884 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1808 ; assign _dfoo1878 = - (source_id__h31884 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1810 ; assign _dfoo188 = - (source_id__h62134 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo120 ; assign _dfoo1880 = - (source_id__h31884 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1812 ; assign _dfoo1882 = - (source_id__h31884 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1814 ; assign _dfoo1884 = - (source_id__h31884 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1816 ; assign _dfoo1886 = - (source_id__h31884 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1818 ; assign _dfoo1888 = - (source_id__h31884 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1820 ; assign _dfoo189 = - source_id__h62134 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo53 ; assign _dfoo1890 = - (source_id__h31884 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1822 ; assign _dfoo1892 = - (source_id__h31884 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1824 ; assign _dfoo1894 = - (source_id__h31884 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1826 ; assign _dfoo1896 = - (source_id__h31884 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1828 ; assign _dfoo1898 = - (source_id__h31884 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1830 ; assign _dfoo19 = - source_id__h64554 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo190 = - (source_id__h62134 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo122 ; assign _dfoo1900 = - (source_id__h31884 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1832 ; assign _dfoo1902 = - (source_id__h31884 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1834 ; assign _dfoo1904 = - (source_id__h31884 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103) ? - wdata32__h26921[3] : + (source_id__h34731 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215) ? + wdata32__h29733[3] : _dfoo1836 ; assign _dfoo1905 = - source_id__h30674 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1769 ; assign _dfoo1906 = - (source_id__h30674 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1838 ; assign _dfoo1907 = - source_id__h30674 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1771 ; assign _dfoo1908 = - (source_id__h30674 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1840 ; assign _dfoo1909 = - source_id__h30674 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1773 ; assign _dfoo191 = - source_id__h62134 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo55 ; assign _dfoo1910 = - (source_id__h30674 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1842 ; assign _dfoo1911 = - source_id__h30674 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1775 ; assign _dfoo1912 = - (source_id__h30674 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1844 ; assign _dfoo1913 = - source_id__h30674 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1777 ; assign _dfoo1914 = - (source_id__h30674 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1846 ; assign _dfoo1915 = - source_id__h30674 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1779 ; assign _dfoo1916 = - (source_id__h30674 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1848 ; assign _dfoo1917 = - source_id__h30674 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1781 ; assign _dfoo1918 = - (source_id__h30674 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1850 ; assign _dfoo1919 = - source_id__h30674 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1783 ; assign _dfoo192 = - (source_id__h62134 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo124 ; assign _dfoo1920 = - (source_id__h30674 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1852 ; assign _dfoo1921 = - source_id__h30674 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1785 ; assign _dfoo1922 = - (source_id__h30674 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1854 ; assign _dfoo1923 = - source_id__h30674 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1787 ; assign _dfoo1924 = - (source_id__h30674 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1856 ; assign _dfoo1925 = - source_id__h30674 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1789 ; assign _dfoo1926 = - (source_id__h30674 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1858 ; assign _dfoo1927 = - source_id__h30674 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1791 ; assign _dfoo1928 = - (source_id__h30674 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1860 ; assign _dfoo1929 = - source_id__h30674 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1793 ; assign _dfoo193 = - source_id__h62134 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo57 ; assign _dfoo1930 = - (source_id__h30674 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1862 ; assign _dfoo1931 = - source_id__h30674 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1795 ; assign _dfoo1932 = - (source_id__h30674 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1864 ; assign _dfoo1933 = - source_id__h30674 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1797 ; assign _dfoo1934 = - (source_id__h30674 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1866 ; assign _dfoo1935 = - source_id__h30674 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1799 ; assign _dfoo1936 = - (source_id__h30674 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1868 ; assign _dfoo1937 = - source_id__h30674 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1801 ; assign _dfoo1938 = - (source_id__h30674 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1870 ; assign _dfoo1939 = - source_id__h30674 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1803 ; assign _dfoo194 = - (source_id__h62134 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo126 ; assign _dfoo1940 = - (source_id__h30674 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1872 ; assign _dfoo1941 = - source_id__h30674 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1805 ; assign _dfoo1942 = - (source_id__h30674 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1874 ; assign _dfoo1943 = - source_id__h30674 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1807 ; assign _dfoo1944 = - (source_id__h30674 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1876 ; assign _dfoo1945 = - source_id__h30674 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1809 ; assign _dfoo1946 = - (source_id__h30674 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1878 ; assign _dfoo1947 = - source_id__h30674 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1811 ; assign _dfoo1948 = - (source_id__h30674 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1880 ; assign _dfoo1949 = - source_id__h30674 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1813 ; assign _dfoo195 = - source_id__h62134 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo59 ; assign _dfoo1950 = - (source_id__h30674 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1882 ; assign _dfoo1951 = - source_id__h30674 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1815 ; assign _dfoo1952 = - (source_id__h30674 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1884 ; assign _dfoo1953 = - source_id__h30674 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1817 ; assign _dfoo1954 = - (source_id__h30674 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1886 ; assign _dfoo1955 = - source_id__h30674 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1819 ; assign _dfoo1956 = - (source_id__h30674 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1888 ; assign _dfoo1957 = - source_id__h30674 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1821 ; assign _dfoo1958 = - (source_id__h30674 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1890 ; assign _dfoo1959 = - source_id__h30674 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1823 ; assign _dfoo196 = - (source_id__h62134 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo128 ; assign _dfoo1960 = - (source_id__h30674 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1892 ; assign _dfoo1961 = - source_id__h30674 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1825 ; assign _dfoo1962 = - (source_id__h30674 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1894 ; assign _dfoo1963 = - source_id__h30674 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1827 ; assign _dfoo1964 = - (source_id__h30674 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1896 ; assign _dfoo1965 = - source_id__h30674 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1829 ; assign _dfoo1966 = - (source_id__h30674 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1898 ; assign _dfoo1967 = - source_id__h30674 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1831 ; assign _dfoo1968 = - (source_id__h30674 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1900 ; assign _dfoo1969 = - source_id__h30674 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1833 ; assign _dfoo197 = - source_id__h62134 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo61 ; assign _dfoo1970 = - (source_id__h30674 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1902 ; assign _dfoo1971 = - source_id__h30674 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042 || - source_id__h31884 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1103 || + source_id__h33521 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154 || + source_id__h34731 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1215 || _dfoo1835 ; assign _dfoo1972 = - (source_id__h30674 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1042) ? - wdata32__h26921[2] : + (source_id__h33521 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1154) ? + wdata32__h29733[2] : _dfoo1904 ; assign _dfoo1974 = - (source_id__h29464 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1906 ; assign _dfoo1976 = - (source_id__h29464 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1908 ; assign _dfoo1978 = - (source_id__h29464 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1910 ; assign _dfoo198 = - (source_id__h62134 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo130 ; assign _dfoo1980 = - (source_id__h29464 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1912 ; assign _dfoo1982 = - (source_id__h29464 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1914 ; assign _dfoo1984 = - (source_id__h29464 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1916 ; assign _dfoo1986 = - (source_id__h29464 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1918 ; assign _dfoo1988 = - (source_id__h29464 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1920 ; assign _dfoo199 = - source_id__h62134 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo63 ; assign _dfoo1990 = - (source_id__h29464 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1922 ; assign _dfoo1992 = - (source_id__h29464 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1924 ; assign _dfoo1994 = - (source_id__h29464 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1926 ; assign _dfoo1996 = - (source_id__h29464 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1928 ; assign _dfoo1998 = - (source_id__h29464 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1930 ; assign _dfoo2 = - (source_id__h64554 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo20 = - (source_id__h64554 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo200 = - (source_id__h62134 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo132 ; assign _dfoo2000 = - (source_id__h29464 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1932 ; assign _dfoo2002 = - (source_id__h29464 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1934 ; assign _dfoo2004 = - (source_id__h29464 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1936 ; assign _dfoo2006 = - (source_id__h29464 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1938 ; assign _dfoo2008 = - (source_id__h29464 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1940 ; assign _dfoo201 = - source_id__h62134 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo65 ; assign _dfoo2010 = - (source_id__h29464 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1942 ; assign _dfoo2012 = - (source_id__h29464 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1944 ; assign _dfoo2014 = - (source_id__h29464 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1946 ; assign _dfoo2016 = - (source_id__h29464 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1948 ; assign _dfoo2018 = - (source_id__h29464 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1950 ; assign _dfoo202 = - (source_id__h62134 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo134 ; assign _dfoo2020 = - (source_id__h29464 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1952 ; assign _dfoo2022 = - (source_id__h29464 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1954 ; assign _dfoo2024 = - (source_id__h29464 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1956 ; assign _dfoo2026 = - (source_id__h29464 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1958 ; assign _dfoo2028 = - (source_id__h29464 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1960 ; assign _dfoo203 = - source_id__h62134 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628 || - source_id__h63344 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689 || + source_id__h64981 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740 || + source_id__h66191 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801 || _dfoo67 ; assign _dfoo2030 = - (source_id__h29464 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1962 ; assign _dfoo2032 = - (source_id__h29464 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1964 ; assign _dfoo2034 = - (source_id__h29464 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1966 ; assign _dfoo2036 = - (source_id__h29464 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1968 ; assign _dfoo2038 = - (source_id__h29464 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1970 ; assign _dfoo204 = - (source_id__h62134 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2628) ? - wdata32__h26921[28] : + (source_id__h64981 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2740) ? + wdata32__h29733[28] : _dfoo136 ; assign _dfoo2040 = - (source_id__h29464 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981) ? - wdata32__h26921[1] : + (source_id__h32311 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093) ? + wdata32__h29733[1] : _dfoo1972 ; assign _dfoo2041 = - source_id_base__h28137 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd16 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1905 ; assign _dfoo2043 = - source_id_base__h28137 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd15 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1907 ; assign _dfoo2045 = - source_id_base__h28137 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd14 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1909 ; assign _dfoo2047 = - source_id_base__h28137 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd13 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1911 ; assign _dfoo2049 = - source_id_base__h28137 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd12 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1913 ; assign _dfoo2051 = - source_id_base__h28137 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd11 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1915 ; assign _dfoo2053 = - source_id_base__h28137 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd10 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1917 ; assign _dfoo2055 = - source_id_base__h28137 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd9 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1919 ; assign _dfoo2057 = - source_id_base__h28137 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd8 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1921 ; assign _dfoo2059 = - source_id_base__h28137 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd7 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1923 ; assign _dfoo206 = - (source_id__h60924 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo138 ; assign _dfoo2061 = - source_id_base__h28137 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd6 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1925 ; assign _dfoo2063 = - source_id_base__h28137 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd5 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1927 ; assign _dfoo2065 = - source_id_base__h28137 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd4 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1929 ; assign _dfoo2067 = - source_id_base__h28137 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd3 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1931 ; assign _dfoo2069 = - source_id_base__h28137 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd2 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1933 ; assign _dfoo2071 = - source_id_base__h28137 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd1 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1935 ; assign _dfoo2073 = - source_id_base__h28137 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 || - source_id__h29464 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 || + source_id__h32311 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1937 ; assign _dfoo2075 = - source_id_base__h28137 == 10'd16 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd16 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1939 ; assign _dfoo2077 = - source_id_base__h28137 == 10'd15 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd15 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1941 ; assign _dfoo2079 = - source_id_base__h28137 == 10'd14 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd14 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1943 ; assign _dfoo208 = - (source_id__h60924 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo140 ; assign _dfoo2081 = - source_id_base__h28137 == 10'd13 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd13 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1945 ; assign _dfoo2083 = - source_id_base__h28137 == 10'd12 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd12 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1947 ; assign _dfoo2085 = - source_id_base__h28137 == 10'd11 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd11 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1949 ; assign _dfoo2087 = - source_id_base__h28137 == 10'd10 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd10 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1951 ; assign _dfoo2089 = - source_id_base__h28137 == 10'd9 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd9 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1953 ; assign _dfoo2091 = - source_id_base__h28137 == 10'd8 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd8 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1955 ; assign _dfoo2093 = - source_id_base__h28137 == 10'd7 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd7 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1957 ; assign _dfoo2095 = - source_id_base__h28137 == 10'd6 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd6 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1959 ; assign _dfoo2097 = - source_id_base__h28137 == 10'd5 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd5 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1961 ; assign _dfoo2099 = - source_id_base__h28137 == 10'd4 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd4 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1963 ; assign _dfoo21 = - source_id__h64554 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo210 = - (source_id__h60924 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo142 ; assign _dfoo2101 = - source_id_base__h28137 == 10'd3 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd3 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1965 ; assign _dfoo2103 = - source_id_base__h28137 == 10'd2 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd2 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1967 ; assign _dfoo2105 = - source_id_base__h28137 == 10'd1 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd1 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1969 ; assign _dfoo2107 = - source_id_base__h28137 == 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 || - source_id__h29464 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d981 || + source_id_base__h30983 == 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 || + source_id__h32311 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1093 || _dfoo1971 ; assign _dfoo212 = - (source_id__h60924 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo144 ; assign _dfoo214 = - (source_id__h60924 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo146 ; assign _dfoo216 = - (source_id__h60924 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo148 ; assign _dfoo218 = - (source_id__h60924 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo150 ; assign _dfoo22 = - (source_id__h64554 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo220 = - (source_id__h60924 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo152 ; assign _dfoo222 = - (source_id__h60924 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo154 ; assign _dfoo224 = - (source_id__h60924 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo156 ; assign _dfoo226 = - (source_id__h60924 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo158 ; assign _dfoo228 = - (source_id__h60924 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo160 ; assign _dfoo23 = - source_id__h64554 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo230 = - (source_id__h60924 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo162 ; assign _dfoo232 = - (source_id__h60924 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo164 ; assign _dfoo234 = - (source_id__h60924 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo166 ; assign _dfoo236 = - (source_id__h60924 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo168 ; assign _dfoo238 = - (source_id__h60924 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo170 ; assign _dfoo24 = - (source_id__h64554 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo240 = - (source_id__h60924 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo172 ; assign _dfoo242 = - (source_id__h60924 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo174 ; assign _dfoo244 = - (source_id__h60924 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo176 ; assign _dfoo246 = - (source_id__h60924 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo178 ; assign _dfoo248 = - (source_id__h60924 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo180 ; assign _dfoo25 = - source_id__h64554 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo250 = - (source_id__h60924 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo182 ; assign _dfoo252 = - (source_id__h60924 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo184 ; assign _dfoo254 = - (source_id__h60924 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo186 ; assign _dfoo256 = - (source_id__h60924 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo188 ; assign _dfoo258 = - (source_id__h60924 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo190 ; assign _dfoo26 = - (source_id__h64554 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo260 = - (source_id__h60924 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo192 ; assign _dfoo262 = - (source_id__h60924 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo194 ; assign _dfoo264 = - (source_id__h60924 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo196 ; assign _dfoo266 = - (source_id__h60924 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo198 ; assign _dfoo268 = - (source_id__h60924 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo200 ; assign _dfoo27 = - source_id__h64554 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo270 = - (source_id__h60924 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo202 ; assign _dfoo272 = - (source_id__h60924 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567) ? - wdata32__h26921[27] : + (source_id__h63771 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679) ? + wdata32__h29733[27] : _dfoo204 ; assign _dfoo273 = - source_id__h59714 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo137 ; assign _dfoo274 = - (source_id__h59714 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo206 ; assign _dfoo275 = - source_id__h59714 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo139 ; assign _dfoo276 = - (source_id__h59714 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo208 ; assign _dfoo277 = - source_id__h59714 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo141 ; assign _dfoo278 = - (source_id__h59714 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo210 ; assign _dfoo279 = - source_id__h59714 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo143 ; assign _dfoo28 = - (source_id__h64554 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo280 = - (source_id__h59714 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo212 ; assign _dfoo281 = - source_id__h59714 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo145 ; assign _dfoo282 = - (source_id__h59714 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo214 ; assign _dfoo283 = - source_id__h59714 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo147 ; assign _dfoo284 = - (source_id__h59714 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo216 ; assign _dfoo285 = - source_id__h59714 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo149 ; assign _dfoo286 = - (source_id__h59714 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo218 ; assign _dfoo287 = - source_id__h59714 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo151 ; assign _dfoo288 = - (source_id__h59714 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo220 ; assign _dfoo289 = - source_id__h59714 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo153 ; assign _dfoo29 = - source_id__h64554 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo290 = - (source_id__h59714 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo222 ; assign _dfoo291 = - source_id__h59714 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo155 ; assign _dfoo292 = - (source_id__h59714 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo224 ; assign _dfoo293 = - source_id__h59714 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo157 ; assign _dfoo294 = - (source_id__h59714 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo226 ; assign _dfoo295 = - source_id__h59714 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo159 ; assign _dfoo296 = - (source_id__h59714 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo228 ; assign _dfoo297 = - source_id__h59714 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo161 ; assign _dfoo298 = - (source_id__h59714 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo230 ; assign _dfoo299 = - source_id__h59714 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo163 ; assign _dfoo3 = - source_id__h64554 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo30 = - (source_id__h64554 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo300 = - (source_id__h59714 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo232 ; assign _dfoo301 = - source_id__h59714 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo165 ; assign _dfoo302 = - (source_id__h59714 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo234 ; assign _dfoo303 = - source_id__h59714 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo167 ; assign _dfoo304 = - (source_id__h59714 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo236 ; assign _dfoo305 = - source_id__h59714 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo169 ; assign _dfoo306 = - (source_id__h59714 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo238 ; assign _dfoo307 = - source_id__h59714 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo171 ; assign _dfoo308 = - (source_id__h59714 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo240 ; assign _dfoo309 = - source_id__h59714 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo173 ; assign _dfoo31 = - source_id__h64554 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo310 = - (source_id__h59714 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo242 ; assign _dfoo311 = - source_id__h59714 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo175 ; assign _dfoo312 = - (source_id__h59714 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo244 ; assign _dfoo313 = - source_id__h59714 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo177 ; assign _dfoo314 = - (source_id__h59714 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo246 ; assign _dfoo315 = - source_id__h59714 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo179 ; assign _dfoo316 = - (source_id__h59714 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo248 ; assign _dfoo317 = - source_id__h59714 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo181 ; assign _dfoo318 = - (source_id__h59714 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo250 ; assign _dfoo319 = - source_id__h59714 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo183 ; assign _dfoo32 = - (source_id__h64554 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo320 = - (source_id__h59714 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo252 ; assign _dfoo321 = - source_id__h59714 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo185 ; assign _dfoo322 = - (source_id__h59714 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo254 ; assign _dfoo323 = - source_id__h59714 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo187 ; assign _dfoo324 = - (source_id__h59714 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo256 ; assign _dfoo325 = - source_id__h59714 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo189 ; assign _dfoo326 = - (source_id__h59714 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo258 ; assign _dfoo327 = - source_id__h59714 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo191 ; assign _dfoo328 = - (source_id__h59714 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo260 ; assign _dfoo329 = - source_id__h59714 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo193 ; assign _dfoo33 = - source_id__h64554 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo330 = - (source_id__h59714 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo262 ; assign _dfoo331 = - source_id__h59714 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo195 ; assign _dfoo332 = - (source_id__h59714 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo264 ; assign _dfoo333 = - source_id__h59714 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo197 ; assign _dfoo334 = - (source_id__h59714 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo266 ; assign _dfoo335 = - source_id__h59714 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo199 ; assign _dfoo336 = - (source_id__h59714 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo268 ; assign _dfoo337 = - source_id__h59714 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo201 ; assign _dfoo338 = - (source_id__h59714 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo270 ; assign _dfoo339 = - source_id__h59714 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506 || - source_id__h60924 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2567 || + source_id__h62561 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618 || + source_id__h63771 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2679 || _dfoo203 ; assign _dfoo34 = - (source_id__h64554 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo340 = - (source_id__h59714 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2506) ? - wdata32__h26921[26] : + (source_id__h62561 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2618) ? + wdata32__h29733[26] : _dfoo272 ; assign _dfoo342 = - (source_id__h58504 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo274 ; assign _dfoo344 = - (source_id__h58504 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo276 ; assign _dfoo346 = - (source_id__h58504 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo278 ; assign _dfoo348 = - (source_id__h58504 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo280 ; assign _dfoo35 = - source_id__h64554 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo350 = - (source_id__h58504 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo282 ; assign _dfoo352 = - (source_id__h58504 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo284 ; assign _dfoo354 = - (source_id__h58504 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo286 ; assign _dfoo356 = - (source_id__h58504 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo288 ; assign _dfoo358 = - (source_id__h58504 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo290 ; assign _dfoo36 = - (source_id__h64554 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo360 = - (source_id__h58504 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo292 ; assign _dfoo362 = - (source_id__h58504 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo294 ; assign _dfoo364 = - (source_id__h58504 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo296 ; assign _dfoo366 = - (source_id__h58504 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo298 ; assign _dfoo368 = - (source_id__h58504 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo300 ; assign _dfoo37 = - source_id__h64554 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo370 = - (source_id__h58504 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo302 ; assign _dfoo372 = - (source_id__h58504 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo304 ; assign _dfoo374 = - (source_id__h58504 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo306 ; assign _dfoo376 = - (source_id__h58504 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo308 ; assign _dfoo378 = - (source_id__h58504 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo310 ; assign _dfoo38 = - (source_id__h64554 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo380 = - (source_id__h58504 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo312 ; assign _dfoo382 = - (source_id__h58504 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo314 ; assign _dfoo384 = - (source_id__h58504 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo316 ; assign _dfoo386 = - (source_id__h58504 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo318 ; assign _dfoo388 = - (source_id__h58504 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo320 ; assign _dfoo39 = - source_id__h64554 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo390 = - (source_id__h58504 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo322 ; assign _dfoo392 = - (source_id__h58504 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo324 ; assign _dfoo394 = - (source_id__h58504 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo326 ; assign _dfoo396 = - (source_id__h58504 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo328 ; assign _dfoo398 = - (source_id__h58504 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo330 ; assign _dfoo4 = - (source_id__h64554 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo40 = - (source_id__h64554 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo400 = - (source_id__h58504 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo332 ; assign _dfoo402 = - (source_id__h58504 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo334 ; assign _dfoo404 = - (source_id__h58504 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo336 ; assign _dfoo406 = - (source_id__h58504 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo338 ; assign _dfoo408 = - (source_id__h58504 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445) ? - wdata32__h26921[25] : + (source_id__h61351 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557) ? + wdata32__h29733[25] : _dfoo340 ; assign _dfoo409 = - source_id__h57294 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo273 ; assign _dfoo41 = - source_id__h64554 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo410 = - (source_id__h57294 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo342 ; assign _dfoo411 = - source_id__h57294 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo275 ; assign _dfoo412 = - (source_id__h57294 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo344 ; assign _dfoo413 = - source_id__h57294 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo277 ; assign _dfoo414 = - (source_id__h57294 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo346 ; assign _dfoo415 = - source_id__h57294 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo279 ; assign _dfoo416 = - (source_id__h57294 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo348 ; assign _dfoo417 = - source_id__h57294 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo281 ; assign _dfoo418 = - (source_id__h57294 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo350 ; assign _dfoo419 = - source_id__h57294 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo283 ; assign _dfoo42 = - (source_id__h64554 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo420 = - (source_id__h57294 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo352 ; assign _dfoo421 = - source_id__h57294 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo285 ; assign _dfoo422 = - (source_id__h57294 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo354 ; assign _dfoo423 = - source_id__h57294 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo287 ; assign _dfoo424 = - (source_id__h57294 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo356 ; assign _dfoo425 = - source_id__h57294 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo289 ; assign _dfoo426 = - (source_id__h57294 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo358 ; assign _dfoo427 = - source_id__h57294 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo291 ; assign _dfoo428 = - (source_id__h57294 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo360 ; assign _dfoo429 = - source_id__h57294 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo293 ; assign _dfoo43 = - source_id__h64554 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo430 = - (source_id__h57294 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo362 ; assign _dfoo431 = - source_id__h57294 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo295 ; assign _dfoo432 = - (source_id__h57294 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo364 ; assign _dfoo433 = - source_id__h57294 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo297 ; assign _dfoo434 = - (source_id__h57294 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo366 ; assign _dfoo435 = - source_id__h57294 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo299 ; assign _dfoo436 = - (source_id__h57294 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo368 ; assign _dfoo437 = - source_id__h57294 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo301 ; assign _dfoo438 = - (source_id__h57294 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo370 ; assign _dfoo439 = - source_id__h57294 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo303 ; assign _dfoo44 = - (source_id__h64554 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo440 = - (source_id__h57294 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo372 ; assign _dfoo441 = - source_id__h57294 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo305 ; assign _dfoo442 = - (source_id__h57294 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo374 ; assign _dfoo443 = - source_id__h57294 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo307 ; assign _dfoo444 = - (source_id__h57294 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo376 ; assign _dfoo445 = - source_id__h57294 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo309 ; assign _dfoo446 = - (source_id__h57294 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo378 ; assign _dfoo447 = - source_id__h57294 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo311 ; assign _dfoo448 = - (source_id__h57294 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo380 ; assign _dfoo449 = - source_id__h57294 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo313 ; assign _dfoo45 = - source_id__h64554 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo450 = - (source_id__h57294 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo382 ; assign _dfoo451 = - source_id__h57294 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo315 ; assign _dfoo452 = - (source_id__h57294 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo384 ; assign _dfoo453 = - source_id__h57294 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo317 ; assign _dfoo454 = - (source_id__h57294 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo386 ; assign _dfoo455 = - source_id__h57294 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo319 ; assign _dfoo456 = - (source_id__h57294 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo388 ; assign _dfoo457 = - source_id__h57294 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo321 ; assign _dfoo458 = - (source_id__h57294 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo390 ; assign _dfoo459 = - source_id__h57294 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo323 ; assign _dfoo46 = - (source_id__h64554 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo460 = - (source_id__h57294 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo392 ; assign _dfoo461 = - source_id__h57294 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo325 ; assign _dfoo462 = - (source_id__h57294 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo394 ; assign _dfoo463 = - source_id__h57294 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo327 ; assign _dfoo464 = - (source_id__h57294 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo396 ; assign _dfoo465 = - source_id__h57294 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo329 ; assign _dfoo466 = - (source_id__h57294 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo398 ; assign _dfoo467 = - source_id__h57294 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo331 ; assign _dfoo468 = - (source_id__h57294 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo400 ; assign _dfoo469 = - source_id__h57294 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo333 ; assign _dfoo47 = - source_id__h64554 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo470 = - (source_id__h57294 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo402 ; assign _dfoo471 = - source_id__h57294 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo335 ; assign _dfoo472 = - (source_id__h57294 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo404 ; assign _dfoo473 = - source_id__h57294 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo337 ; assign _dfoo474 = - (source_id__h57294 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo406 ; assign _dfoo475 = - source_id__h57294 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384 || - source_id__h58504 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2445 || + source_id__h60141 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496 || + source_id__h61351 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2557 || _dfoo339 ; assign _dfoo476 = - (source_id__h57294 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2384) ? - wdata32__h26921[24] : + (source_id__h60141 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2496) ? + wdata32__h29733[24] : _dfoo408 ; assign _dfoo478 = - (source_id__h56084 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo410 ; assign _dfoo48 = - (source_id__h64554 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo480 = - (source_id__h56084 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo412 ; assign _dfoo482 = - (source_id__h56084 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo414 ; assign _dfoo484 = - (source_id__h56084 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo416 ; assign _dfoo486 = - (source_id__h56084 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo418 ; assign _dfoo488 = - (source_id__h56084 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo420 ; assign _dfoo49 = - source_id__h64554 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo490 = - (source_id__h56084 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo422 ; assign _dfoo492 = - (source_id__h56084 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo424 ; assign _dfoo494 = - (source_id__h56084 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo426 ; assign _dfoo496 = - (source_id__h56084 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo428 ; assign _dfoo498 = - (source_id__h56084 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo430 ; assign _dfoo5 = - source_id__h64554 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo50 = - (source_id__h64554 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo500 = - (source_id__h56084 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo432 ; assign _dfoo502 = - (source_id__h56084 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo434 ; assign _dfoo504 = - (source_id__h56084 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo436 ; assign _dfoo506 = - (source_id__h56084 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo438 ; assign _dfoo508 = - (source_id__h56084 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo440 ; assign _dfoo51 = - source_id__h64554 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo510 = - (source_id__h56084 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo442 ; assign _dfoo512 = - (source_id__h56084 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo444 ; assign _dfoo514 = - (source_id__h56084 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo446 ; assign _dfoo516 = - (source_id__h56084 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo448 ; assign _dfoo518 = - (source_id__h56084 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo450 ; assign _dfoo52 = - (source_id__h64554 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo520 = - (source_id__h56084 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo452 ; assign _dfoo522 = - (source_id__h56084 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo454 ; assign _dfoo524 = - (source_id__h56084 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo456 ; assign _dfoo526 = - (source_id__h56084 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo458 ; assign _dfoo528 = - (source_id__h56084 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo460 ; assign _dfoo53 = - source_id__h64554 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo530 = - (source_id__h56084 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo462 ; assign _dfoo532 = - (source_id__h56084 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo464 ; assign _dfoo534 = - (source_id__h56084 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo466 ; assign _dfoo536 = - (source_id__h56084 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo468 ; assign _dfoo538 = - (source_id__h56084 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo470 ; assign _dfoo54 = - (source_id__h64554 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo540 = - (source_id__h56084 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo472 ; assign _dfoo542 = - (source_id__h56084 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo474 ; assign _dfoo544 = - (source_id__h56084 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323) ? - wdata32__h26921[23] : + (source_id__h58931 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435) ? + wdata32__h29733[23] : _dfoo476 ; assign _dfoo545 = - source_id__h54874 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo409 ; assign _dfoo546 = - (source_id__h54874 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo478 ; assign _dfoo547 = - source_id__h54874 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo411 ; assign _dfoo548 = - (source_id__h54874 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo480 ; assign _dfoo549 = - source_id__h54874 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo413 ; assign _dfoo55 = - source_id__h64554 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo550 = - (source_id__h54874 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo482 ; assign _dfoo551 = - source_id__h54874 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo415 ; assign _dfoo552 = - (source_id__h54874 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo484 ; assign _dfoo553 = - source_id__h54874 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo417 ; assign _dfoo554 = - (source_id__h54874 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo486 ; assign _dfoo555 = - source_id__h54874 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo419 ; assign _dfoo556 = - (source_id__h54874 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo488 ; assign _dfoo557 = - source_id__h54874 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo421 ; assign _dfoo558 = - (source_id__h54874 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo490 ; assign _dfoo559 = - source_id__h54874 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo423 ; assign _dfoo56 = - (source_id__h64554 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo560 = - (source_id__h54874 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo492 ; assign _dfoo561 = - source_id__h54874 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo425 ; assign _dfoo562 = - (source_id__h54874 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo494 ; assign _dfoo563 = - source_id__h54874 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo427 ; assign _dfoo564 = - (source_id__h54874 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo496 ; assign _dfoo565 = - source_id__h54874 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo429 ; assign _dfoo566 = - (source_id__h54874 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo498 ; assign _dfoo567 = - source_id__h54874 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo431 ; assign _dfoo568 = - (source_id__h54874 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo500 ; assign _dfoo569 = - source_id__h54874 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo433 ; assign _dfoo57 = - source_id__h64554 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo570 = - (source_id__h54874 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo502 ; assign _dfoo571 = - source_id__h54874 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo435 ; assign _dfoo572 = - (source_id__h54874 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo504 ; assign _dfoo573 = - source_id__h54874 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo437 ; assign _dfoo574 = - (source_id__h54874 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo506 ; assign _dfoo575 = - source_id__h54874 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo439 ; assign _dfoo576 = - (source_id__h54874 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo508 ; assign _dfoo577 = - source_id__h54874 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo441 ; assign _dfoo578 = - (source_id__h54874 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo510 ; assign _dfoo579 = - source_id__h54874 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo443 ; assign _dfoo58 = - (source_id__h64554 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo580 = - (source_id__h54874 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo512 ; assign _dfoo581 = - source_id__h54874 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo445 ; assign _dfoo582 = - (source_id__h54874 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo514 ; assign _dfoo583 = - source_id__h54874 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo447 ; assign _dfoo584 = - (source_id__h54874 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo516 ; assign _dfoo585 = - source_id__h54874 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo449 ; assign _dfoo586 = - (source_id__h54874 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo518 ; assign _dfoo587 = - source_id__h54874 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo451 ; assign _dfoo588 = - (source_id__h54874 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo520 ; assign _dfoo589 = - source_id__h54874 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo453 ; assign _dfoo59 = - source_id__h64554 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo590 = - (source_id__h54874 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo522 ; assign _dfoo591 = - source_id__h54874 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo455 ; assign _dfoo592 = - (source_id__h54874 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo524 ; assign _dfoo593 = - source_id__h54874 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo457 ; assign _dfoo594 = - (source_id__h54874 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo526 ; assign _dfoo595 = - source_id__h54874 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo459 ; assign _dfoo596 = - (source_id__h54874 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo528 ; assign _dfoo597 = - source_id__h54874 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo461 ; assign _dfoo598 = - (source_id__h54874 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo530 ; assign _dfoo599 = - source_id__h54874 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo463 ; assign _dfoo6 = - (source_id__h64554 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo60 = - (source_id__h64554 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo600 = - (source_id__h54874 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo532 ; assign _dfoo601 = - source_id__h54874 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo465 ; assign _dfoo602 = - (source_id__h54874 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo534 ; assign _dfoo603 = - source_id__h54874 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo467 ; assign _dfoo604 = - (source_id__h54874 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo536 ; assign _dfoo605 = - source_id__h54874 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo469 ; assign _dfoo606 = - (source_id__h54874 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo538 ; assign _dfoo607 = - source_id__h54874 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo471 ; assign _dfoo608 = - (source_id__h54874 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo540 ; assign _dfoo609 = - source_id__h54874 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo473 ; assign _dfoo61 = - source_id__h64554 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo610 = - (source_id__h54874 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo542 ; assign _dfoo611 = - source_id__h54874 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262 || - source_id__h56084 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2323 || + source_id__h57721 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374 || + source_id__h58931 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2435 || _dfoo475 ; assign _dfoo612 = - (source_id__h54874 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2262) ? - wdata32__h26921[22] : + (source_id__h57721 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2374) ? + wdata32__h29733[22] : _dfoo544 ; assign _dfoo614 = - (source_id__h53664 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo546 ; assign _dfoo616 = - (source_id__h53664 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo548 ; assign _dfoo618 = - (source_id__h53664 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo550 ; assign _dfoo62 = - (source_id__h64554 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo620 = - (source_id__h53664 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo552 ; assign _dfoo622 = - (source_id__h53664 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo554 ; assign _dfoo624 = - (source_id__h53664 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo556 ; assign _dfoo626 = - (source_id__h53664 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo558 ; assign _dfoo628 = - (source_id__h53664 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo560 ; assign _dfoo63 = - source_id__h64554 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo630 = - (source_id__h53664 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo562 ; assign _dfoo632 = - (source_id__h53664 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo564 ; assign _dfoo634 = - (source_id__h53664 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo566 ; assign _dfoo636 = - (source_id__h53664 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo568 ; assign _dfoo638 = - (source_id__h53664 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo570 ; assign _dfoo64 = - (source_id__h64554 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo640 = - (source_id__h53664 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo572 ; assign _dfoo642 = - (source_id__h53664 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo574 ; assign _dfoo644 = - (source_id__h53664 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo576 ; assign _dfoo646 = - (source_id__h53664 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo578 ; assign _dfoo648 = - (source_id__h53664 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo580 ; assign _dfoo65 = - source_id__h64554 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo650 = - (source_id__h53664 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo582 ; assign _dfoo652 = - (source_id__h53664 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo584 ; assign _dfoo654 = - (source_id__h53664 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo586 ; assign _dfoo656 = - (source_id__h53664 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo588 ; assign _dfoo658 = - (source_id__h53664 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo590 ; assign _dfoo66 = - (source_id__h64554 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo660 = - (source_id__h53664 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo592 ; assign _dfoo662 = - (source_id__h53664 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo594 ; assign _dfoo664 = - (source_id__h53664 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo596 ; assign _dfoo666 = - (source_id__h53664 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo598 ; assign _dfoo668 = - (source_id__h53664 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo600 ; assign _dfoo67 = - source_id__h64554 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo670 = - (source_id__h53664 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo602 ; assign _dfoo672 = - (source_id__h53664 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo604 ; assign _dfoo674 = - (source_id__h53664 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo606 ; assign _dfoo676 = - (source_id__h53664 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo608 ; assign _dfoo678 = - (source_id__h53664 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo610 ; assign _dfoo68 = - (source_id__h64554 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo680 = - (source_id__h53664 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201) ? - wdata32__h26921[21] : + (source_id__h56511 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313) ? + wdata32__h29733[21] : _dfoo612 ; assign _dfoo681 = - source_id__h52454 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo545 ; assign _dfoo682 = - (source_id__h52454 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo614 ; assign _dfoo683 = - source_id__h52454 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo547 ; assign _dfoo684 = - (source_id__h52454 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo616 ; assign _dfoo685 = - source_id__h52454 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo549 ; assign _dfoo686 = - (source_id__h52454 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo618 ; assign _dfoo687 = - source_id__h52454 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo551 ; assign _dfoo688 = - (source_id__h52454 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo620 ; assign _dfoo689 = - source_id__h52454 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo553 ; assign _dfoo690 = - (source_id__h52454 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo622 ; assign _dfoo691 = - source_id__h52454 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo555 ; assign _dfoo692 = - (source_id__h52454 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo624 ; assign _dfoo693 = - source_id__h52454 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo557 ; assign _dfoo694 = - (source_id__h52454 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo626 ; assign _dfoo695 = - source_id__h52454 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo559 ; assign _dfoo696 = - (source_id__h52454 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo628 ; assign _dfoo697 = - source_id__h52454 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo561 ; assign _dfoo698 = - (source_id__h52454 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo630 ; assign _dfoo699 = - source_id__h52454 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo563 ; assign _dfoo7 = - source_id__h64554 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo70 = - (source_id__h63344 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo2 ; assign _dfoo700 = - (source_id__h52454 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo632 ; assign _dfoo701 = - source_id__h52454 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo565 ; assign _dfoo702 = - (source_id__h52454 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo634 ; assign _dfoo703 = - source_id__h52454 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo567 ; assign _dfoo704 = - (source_id__h52454 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo636 ; assign _dfoo705 = - source_id__h52454 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo569 ; assign _dfoo706 = - (source_id__h52454 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo638 ; assign _dfoo707 = - source_id__h52454 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo571 ; assign _dfoo708 = - (source_id__h52454 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo640 ; assign _dfoo709 = - source_id__h52454 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo573 ; assign _dfoo710 = - (source_id__h52454 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo642 ; assign _dfoo711 = - source_id__h52454 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo575 ; assign _dfoo712 = - (source_id__h52454 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo644 ; assign _dfoo713 = - source_id__h52454 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo577 ; assign _dfoo714 = - (source_id__h52454 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo646 ; assign _dfoo715 = - source_id__h52454 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo579 ; assign _dfoo716 = - (source_id__h52454 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo648 ; assign _dfoo717 = - source_id__h52454 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo581 ; assign _dfoo718 = - (source_id__h52454 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo650 ; assign _dfoo719 = - source_id__h52454 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo583 ; assign _dfoo72 = - (source_id__h63344 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo4 ; assign _dfoo720 = - (source_id__h52454 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo652 ; assign _dfoo721 = - source_id__h52454 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo585 ; assign _dfoo722 = - (source_id__h52454 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo654 ; assign _dfoo723 = - source_id__h52454 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo587 ; assign _dfoo724 = - (source_id__h52454 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo656 ; assign _dfoo725 = - source_id__h52454 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo589 ; assign _dfoo726 = - (source_id__h52454 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo658 ; assign _dfoo727 = - source_id__h52454 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo591 ; assign _dfoo728 = - (source_id__h52454 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo660 ; assign _dfoo729 = - source_id__h52454 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo593 ; assign _dfoo730 = - (source_id__h52454 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo662 ; assign _dfoo731 = - source_id__h52454 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo595 ; assign _dfoo732 = - (source_id__h52454 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo664 ; assign _dfoo733 = - source_id__h52454 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo597 ; assign _dfoo734 = - (source_id__h52454 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo666 ; assign _dfoo735 = - source_id__h52454 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo599 ; assign _dfoo736 = - (source_id__h52454 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo668 ; assign _dfoo737 = - source_id__h52454 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo601 ; assign _dfoo738 = - (source_id__h52454 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo670 ; assign _dfoo739 = - source_id__h52454 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo603 ; assign _dfoo74 = - (source_id__h63344 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo6 ; assign _dfoo740 = - (source_id__h52454 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo672 ; assign _dfoo741 = - source_id__h52454 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo605 ; assign _dfoo742 = - (source_id__h52454 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo674 ; assign _dfoo743 = - source_id__h52454 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo607 ; assign _dfoo744 = - (source_id__h52454 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo676 ; assign _dfoo745 = - source_id__h52454 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo609 ; assign _dfoo746 = - (source_id__h52454 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo678 ; assign _dfoo747 = - source_id__h52454 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140 || - source_id__h53664 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2201 || + source_id__h55301 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252 || + source_id__h56511 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2313 || _dfoo611 ; assign _dfoo748 = - (source_id__h52454 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2140) ? - wdata32__h26921[20] : + (source_id__h55301 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2252) ? + wdata32__h29733[20] : _dfoo680 ; assign _dfoo750 = - (source_id__h51244 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo682 ; assign _dfoo752 = - (source_id__h51244 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo684 ; assign _dfoo754 = - (source_id__h51244 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo686 ; assign _dfoo756 = - (source_id__h51244 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo688 ; assign _dfoo758 = - (source_id__h51244 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo690 ; assign _dfoo76 = - (source_id__h63344 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo8 ; assign _dfoo760 = - (source_id__h51244 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo692 ; assign _dfoo762 = - (source_id__h51244 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo694 ; assign _dfoo764 = - (source_id__h51244 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo696 ; assign _dfoo766 = - (source_id__h51244 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo698 ; assign _dfoo768 = - (source_id__h51244 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo700 ; assign _dfoo770 = - (source_id__h51244 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo702 ; assign _dfoo772 = - (source_id__h51244 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo704 ; assign _dfoo774 = - (source_id__h51244 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo706 ; assign _dfoo776 = - (source_id__h51244 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo708 ; assign _dfoo778 = - (source_id__h51244 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo710 ; assign _dfoo78 = - (source_id__h63344 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo10 ; assign _dfoo780 = - (source_id__h51244 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo712 ; assign _dfoo782 = - (source_id__h51244 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo714 ; assign _dfoo784 = - (source_id__h51244 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo716 ; assign _dfoo786 = - (source_id__h51244 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo718 ; assign _dfoo788 = - (source_id__h51244 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo720 ; assign _dfoo790 = - (source_id__h51244 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo722 ; assign _dfoo792 = - (source_id__h51244 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo724 ; assign _dfoo794 = - (source_id__h51244 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo726 ; assign _dfoo796 = - (source_id__h51244 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo728 ; assign _dfoo798 = - (source_id__h51244 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo730 ; assign _dfoo8 = - (source_id__h64554 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750) ? - wdata32__h26921[30] : - wdata32__h26921[31] ; + (source_id__h67401 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862) ? + wdata32__h29733[30] : + wdata32__h29733[31] ; assign _dfoo80 = - (source_id__h63344 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo12 ; assign _dfoo800 = - (source_id__h51244 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo732 ; assign _dfoo802 = - (source_id__h51244 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo734 ; assign _dfoo804 = - (source_id__h51244 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo736 ; assign _dfoo806 = - (source_id__h51244 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo738 ; assign _dfoo808 = - (source_id__h51244 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo740 ; assign _dfoo810 = - (source_id__h51244 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo742 ; assign _dfoo812 = - (source_id__h51244 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo744 ; assign _dfoo814 = - (source_id__h51244 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo746 ; assign _dfoo816 = - (source_id__h51244 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079) ? - wdata32__h26921[19] : + (source_id__h54091 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191) ? + wdata32__h29733[19] : _dfoo748 ; assign _dfoo817 = - source_id__h50034 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo681 ; assign _dfoo818 = - (source_id__h50034 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo750 ; assign _dfoo819 = - source_id__h50034 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo683 ; assign _dfoo82 = - (source_id__h63344 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo14 ; assign _dfoo820 = - (source_id__h50034 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo752 ; assign _dfoo821 = - source_id__h50034 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo685 ; assign _dfoo822 = - (source_id__h50034 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo754 ; assign _dfoo823 = - source_id__h50034 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo687 ; assign _dfoo824 = - (source_id__h50034 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo756 ; assign _dfoo825 = - source_id__h50034 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo689 ; assign _dfoo826 = - (source_id__h50034 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo758 ; assign _dfoo827 = - source_id__h50034 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo691 ; assign _dfoo828 = - (source_id__h50034 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo760 ; assign _dfoo829 = - source_id__h50034 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo693 ; assign _dfoo830 = - (source_id__h50034 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo762 ; assign _dfoo831 = - source_id__h50034 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo695 ; assign _dfoo832 = - (source_id__h50034 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo764 ; assign _dfoo833 = - source_id__h50034 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo697 ; assign _dfoo834 = - (source_id__h50034 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo766 ; assign _dfoo835 = - source_id__h50034 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo699 ; assign _dfoo836 = - (source_id__h50034 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo768 ; assign _dfoo837 = - source_id__h50034 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo701 ; assign _dfoo838 = - (source_id__h50034 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo770 ; assign _dfoo839 = - source_id__h50034 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo703 ; assign _dfoo84 = - (source_id__h63344 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo16 ; assign _dfoo840 = - (source_id__h50034 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo772 ; assign _dfoo841 = - source_id__h50034 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo705 ; assign _dfoo842 = - (source_id__h50034 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo774 ; assign _dfoo843 = - source_id__h50034 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo707 ; assign _dfoo844 = - (source_id__h50034 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo776 ; assign _dfoo845 = - source_id__h50034 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo709 ; assign _dfoo846 = - (source_id__h50034 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo778 ; assign _dfoo847 = - source_id__h50034 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo711 ; assign _dfoo848 = - (source_id__h50034 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo780 ; assign _dfoo849 = - source_id__h50034 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo713 ; assign _dfoo850 = - (source_id__h50034 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo782 ; assign _dfoo851 = - source_id__h50034 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo715 ; assign _dfoo852 = - (source_id__h50034 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo784 ; assign _dfoo853 = - source_id__h50034 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo717 ; assign _dfoo854 = - (source_id__h50034 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo786 ; assign _dfoo855 = - source_id__h50034 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo719 ; assign _dfoo856 = - (source_id__h50034 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo788 ; assign _dfoo857 = - source_id__h50034 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo721 ; assign _dfoo858 = - (source_id__h50034 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo790 ; assign _dfoo859 = - source_id__h50034 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo723 ; assign _dfoo86 = - (source_id__h63344 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo18 ; assign _dfoo860 = - (source_id__h50034 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo792 ; assign _dfoo861 = - source_id__h50034 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo725 ; assign _dfoo862 = - (source_id__h50034 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo794 ; assign _dfoo863 = - source_id__h50034 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo727 ; assign _dfoo864 = - (source_id__h50034 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo796 ; assign _dfoo865 = - source_id__h50034 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo729 ; assign _dfoo866 = - (source_id__h50034 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo798 ; assign _dfoo867 = - source_id__h50034 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo731 ; assign _dfoo868 = - (source_id__h50034 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo800 ; assign _dfoo869 = - source_id__h50034 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo733 ; assign _dfoo870 = - (source_id__h50034 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo802 ; assign _dfoo871 = - source_id__h50034 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo735 ; assign _dfoo872 = - (source_id__h50034 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo804 ; assign _dfoo873 = - source_id__h50034 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo737 ; assign _dfoo874 = - (source_id__h50034 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo806 ; assign _dfoo875 = - source_id__h50034 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo739 ; assign _dfoo876 = - (source_id__h50034 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo808 ; assign _dfoo877 = - source_id__h50034 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo741 ; assign _dfoo878 = - (source_id__h50034 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo810 ; assign _dfoo879 = - source_id__h50034 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo743 ; assign _dfoo88 = - (source_id__h63344 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo20 ; assign _dfoo880 = - (source_id__h50034 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo812 ; assign _dfoo881 = - source_id__h50034 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo745 ; assign _dfoo882 = - (source_id__h50034 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo814 ; assign _dfoo883 = - source_id__h50034 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018 || - source_id__h51244 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2079 || + source_id__h52881 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130 || + source_id__h54091 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2191 || _dfoo747 ; assign _dfoo884 = - (source_id__h50034 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2018) ? - wdata32__h26921[18] : + (source_id__h52881 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2130) ? + wdata32__h29733[18] : _dfoo816 ; assign _dfoo886 = - (source_id__h48824 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo818 ; assign _dfoo888 = - (source_id__h48824 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo820 ; assign _dfoo890 = - (source_id__h48824 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo822 ; assign _dfoo892 = - (source_id__h48824 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo824 ; assign _dfoo894 = - (source_id__h48824 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo826 ; assign _dfoo896 = - (source_id__h48824 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo828 ; assign _dfoo898 = - (source_id__h48824 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo830 ; assign _dfoo9 = - source_id__h64554 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2750 || - source_id__h65764 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2811 ; + source_id__h67401 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2862 || + source_id__h68611 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2923 ; assign _dfoo90 = - (source_id__h63344 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo22 ; assign _dfoo900 = - (source_id__h48824 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo832 ; assign _dfoo902 = - (source_id__h48824 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo834 ; assign _dfoo904 = - (source_id__h48824 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo836 ; assign _dfoo906 = - (source_id__h48824 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo838 ; assign _dfoo908 = - (source_id__h48824 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo840 ; assign _dfoo910 = - (source_id__h48824 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo842 ; assign _dfoo912 = - (source_id__h48824 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo844 ; assign _dfoo914 = - (source_id__h48824 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo846 ; assign _dfoo916 = - (source_id__h48824 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo848 ; assign _dfoo918 = - (source_id__h48824 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo850 ; assign _dfoo92 = - (source_id__h63344 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo24 ; assign _dfoo920 = - (source_id__h48824 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo852 ; assign _dfoo922 = - (source_id__h48824 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo854 ; assign _dfoo924 = - (source_id__h48824 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo856 ; assign _dfoo926 = - (source_id__h48824 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo858 ; assign _dfoo928 = - (source_id__h48824 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo860 ; assign _dfoo930 = - (source_id__h48824 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo862 ; assign _dfoo932 = - (source_id__h48824 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo864 ; assign _dfoo934 = - (source_id__h48824 == 10'd9 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd9 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo866 ; assign _dfoo936 = - (source_id__h48824 == 10'd8 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd8 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo868 ; assign _dfoo938 = - (source_id__h48824 == 10'd7 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd7 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo870 ; assign _dfoo94 = - (source_id__h63344 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo26 ; assign _dfoo940 = - (source_id__h48824 == 10'd6 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd6 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo872 ; assign _dfoo942 = - (source_id__h48824 == 10'd5 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd5 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo874 ; assign _dfoo944 = - (source_id__h48824 == 10'd4 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd4 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo876 ; assign _dfoo946 = - (source_id__h48824 == 10'd3 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd3 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo878 ; assign _dfoo948 = - (source_id__h48824 == 10'd2 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd2 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo880 ; assign _dfoo950 = - (source_id__h48824 == 10'd1 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd1 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo882 ; assign _dfoo952 = - (source_id__h48824 == 10'd0 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957) ? - wdata32__h26921[17] : + (source_id__h51671 == 10'd0 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069) ? + wdata32__h29733[17] : _dfoo884 ; assign _dfoo953 = - source_id__h47614 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo817 ; assign _dfoo954 = - (source_id__h47614 == 10'd16 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd16 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo886 ; assign _dfoo955 = - source_id__h47614 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo819 ; assign _dfoo956 = - (source_id__h47614 == 10'd15 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd15 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo888 ; assign _dfoo957 = - source_id__h47614 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo821 ; assign _dfoo958 = - (source_id__h47614 == 10'd14 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd14 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo890 ; assign _dfoo959 = - source_id__h47614 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo823 ; assign _dfoo96 = - (source_id__h63344 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo28 ; assign _dfoo960 = - (source_id__h47614 == 10'd13 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd13 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo892 ; assign _dfoo961 = - source_id__h47614 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo825 ; assign _dfoo962 = - (source_id__h47614 == 10'd12 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd12 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo894 ; assign _dfoo963 = - source_id__h47614 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo827 ; assign _dfoo964 = - (source_id__h47614 == 10'd11 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd11 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo896 ; assign _dfoo965 = - source_id__h47614 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo829 ; assign _dfoo966 = - (source_id__h47614 == 10'd10 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd10 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo898 ; assign _dfoo967 = - source_id__h47614 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo831 ; assign _dfoo968 = - (source_id__h47614 == 10'd9 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd9 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo900 ; assign _dfoo969 = - source_id__h47614 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo833 ; assign _dfoo970 = - (source_id__h47614 == 10'd8 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd8 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo902 ; assign _dfoo971 = - source_id__h47614 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo835 ; assign _dfoo972 = - (source_id__h47614 == 10'd7 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd7 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo904 ; assign _dfoo973 = - source_id__h47614 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo837 ; assign _dfoo974 = - (source_id__h47614 == 10'd6 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd6 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo906 ; assign _dfoo975 = - source_id__h47614 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo839 ; assign _dfoo976 = - (source_id__h47614 == 10'd5 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd5 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo908 ; assign _dfoo977 = - source_id__h47614 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo841 ; assign _dfoo978 = - (source_id__h47614 == 10'd4 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd4 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo910 ; assign _dfoo979 = - source_id__h47614 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo843 ; assign _dfoo98 = - (source_id__h63344 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2689) ? - wdata32__h26921[29] : + (source_id__h66191 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2801) ? + wdata32__h29733[29] : _dfoo30 ; assign _dfoo980 = - (source_id__h47614 == 10'd3 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd3 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo912 ; assign _dfoo981 = - source_id__h47614 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo845 ; assign _dfoo982 = - (source_id__h47614 == 10'd2 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd2 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo914 ; assign _dfoo983 = - source_id__h47614 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo847 ; assign _dfoo984 = - (source_id__h47614 == 10'd1 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd1 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo916 ; assign _dfoo985 = - source_id__h47614 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo849 ; assign _dfoo986 = - (source_id__h47614 == 10'd0 && - addr_offset__h26920[11:7] == 5'd1 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd0 && + addr_offset__h29732[11:7] == 5'd1 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo918 ; assign _dfoo987 = - source_id__h47614 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo851 ; assign _dfoo988 = - (source_id__h47614 == 10'd16 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd16 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo920 ; assign _dfoo989 = - source_id__h47614 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo853 ; assign _dfoo990 = - (source_id__h47614 == 10'd15 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd15 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo922 ; assign _dfoo991 = - source_id__h47614 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo855 ; assign _dfoo992 = - (source_id__h47614 == 10'd14 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd14 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo924 ; assign _dfoo993 = - source_id__h47614 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo857 ; assign _dfoo994 = - (source_id__h47614 == 10'd13 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd13 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo926 ; assign _dfoo995 = - source_id__h47614 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo859 ; assign _dfoo996 = - (source_id__h47614 == 10'd12 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd12 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo928 ; assign _dfoo997 = - source_id__h47614 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo861 ; assign _dfoo998 = - (source_id__h47614 == 10'd11 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896) ? - wdata32__h26921[16] : + (source_id__h50461 == 10'd11 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008) ? + wdata32__h29733[16] : _dfoo930 ; assign _dfoo999 = - source_id__h47614 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1896 || - source_id__h48824 == 10'd10 && - addr_offset__h26920[11:7] == 5'd0 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d1957 || + source_id__h50461 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2008 || + source_id__h51671 == 10'd10 && + addr_offset__h29732[11:7] == 5'd0 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2069 || _dfoo863 ; - assign a__h71297 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? + assign a__h74356 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3216 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 ; - assign a__h73302 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3212 ; + assign a__h76361 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3310 ? m_vrg_source_prio_16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 ; - assign addr_offset__h13214 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ; - assign addr_offset__h26920 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ; - assign b__h71298 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 ? + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3306 ; + assign addr_offset__h15646 = + m_slave_xactor_shim_arff_rv$port1__read[92:29] - m_rg_addr_base ; + assign addr_offset__h29732 = + m_slave_xactor_shim_awff_rv$port1__read[92:29] - m_rg_addr_base ; + assign b__h74357 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3216 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3105 ; - assign b__h73303 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 ? + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3232 ; + assign b__h76362 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3310 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3199 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 = - addr_offset__h13214 < 64'h0000000000003000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 = - addr_offset__h13214[11:7] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 = - m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 = - addr_offset__h13214 < 64'h0000000000001000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 = - addr_offset__h13214[11:2] <= 10'd16 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - addr_offset__h13214[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 && + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3326 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 = + addr_offset__h15646 < 64'h0000000000001000 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109 = + addr_offset__h15646[11:2] <= 10'd16 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d112 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + addr_offset__h15646[11:2] != 10'd0 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109 && m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 = - addr_offset__h13214[16:12] <= 5'd1 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 = - addr_offset__h13214 < 64'h0000000000002000 ; - assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 = - source_id_base__h13628 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 = - addr_offset__h26920[16:12] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2885 = - addr_offset__h26920[16:12] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2887 = - addr_offset__h26920[16:12] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2882 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 = - m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 = - addr_offset__h26920 < 64'h0000000000001000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 = - addr_offset__h26920[11:2] <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d862 = - addr_offset__h26920[11:2] == 10'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d864 = - addr_offset__h26920[11:2] == 10'd2 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d866 = - addr_offset__h26920[11:2] == 10'd3 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d868 = - addr_offset__h26920[11:2] == 10'd4 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d870 = - addr_offset__h26920[11:2] == 10'd5 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d872 = - addr_offset__h26920[11:2] == 10'd6 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d874 = - addr_offset__h26920[11:2] == 10'd7 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d876 = - addr_offset__h26920[11:2] == 10'd8 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d878 = - addr_offset__h26920[11:2] == 10'd9 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d880 = - addr_offset__h26920[11:2] == 10'd10 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d882 = - addr_offset__h26920[11:2] == 10'd11 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d884 = - addr_offset__h26920[11:2] == 10'd12 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d886 = - addr_offset__h26920[11:2] == 10'd13 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d888 = - addr_offset__h26920[11:2] == 10'd14 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d890 = - addr_offset__h26920[11:2] == 10'd15 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d892 = - addr_offset__h26920[11:2] == 10'd16 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - addr_offset__h26920[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848 && + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 = + addr_offset__h15646 < 64'h0000000000002000 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 = + source_id_base__h16091 <= 10'd16 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309 = + addr_offset__h15646 < 64'h0000000000003000 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311 = + addr_offset__h15646[11:7] <= 5'd1 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 = + addr_offset__h15646[16:12] <= 5'd1 ; + assign m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 = + m_slave_xactor_shim_arff_rv$port1__read[92:29] < m_rg_addr_base ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1000 = + addr_offset__h29732[11:2] == 10'd14 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1002 = + addr_offset__h29732[11:2] == 10'd15 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1004 = + addr_offset__h29732[11:2] == 10'd16 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1006 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + addr_offset__h29732[11:2] != 10'd0 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 && m_cfg_verbosity != 4'd0 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 = - addr_offset__h26920 < 64'h0000000000002000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 = - source_id_base__h28137 <= 10'd16 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913 = - addr_offset__h26920 < 64'h0000000000003000 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914 = - addr_offset__h26920[11:7] <= 5'd1 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d920 = - addr_offset__h26920[11:7] == 5'd0 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; - assign m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d956 = - addr_offset__h26920[11:7] == 5'd1 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d917 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3059 = + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1011 = + addr_offset__h29732 < 64'h0000000000002000 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1014 = + source_id_base__h30983 <= 10'd16 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1025 = + addr_offset__h29732 < 64'h0000000000003000 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1026 = + addr_offset__h29732[11:7] <= 5'd1 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1032 = + addr_offset__h29732[11:7] == 5'd0 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1029 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1068 = + addr_offset__h29732[11:7] == 5'd1 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1029 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 = + addr_offset__h29732[16:12] <= 5'd1 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2997 = + addr_offset__h29732[16:12] == 5'd0 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2994 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2999 = + addr_offset__h29732[16:12] == 5'd1 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2994 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 = + m_slave_xactor_shim_awff_rv$port1__read[92:29] < m_rg_addr_base ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 = + addr_offset__h29732 < 64'h0000000000001000 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 = + addr_offset__h29732[11:2] <= 10'd16 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d974 = + addr_offset__h29732[11:2] == 10'd1 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d976 = + addr_offset__h29732[11:2] == 10'd2 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d978 = + addr_offset__h29732[11:2] == 10'd3 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d980 = + addr_offset__h29732[11:2] == 10'd4 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d982 = + addr_offset__h29732[11:2] == 10'd5 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d984 = + addr_offset__h29732[11:2] == 10'd6 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d986 = + addr_offset__h29732[11:2] == 10'd7 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d988 = + addr_offset__h29732[11:2] == 10'd8 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d990 = + addr_offset__h29732[11:2] == 10'd9 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d992 = + addr_offset__h29732[11:2] == 10'd10 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d994 = + addr_offset__h29732[11:2] == 10'd11 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d996 = + addr_offset__h29732[11:2] == 10'd12 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d998 = + addr_offset__h29732[11:2] == 10'd13 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d958 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d960 ; + assign m_slave_xactor_shim_bff_rvport1__read_BITS_6__ETC__q51 = + m_slave_xactor_shim_bff_rv$port1__read[6:0] ; + assign m_slave_xactor_shim_rff_rvport1__read_BITS_71_ETC__q52 = + m_slave_xactor_shim_rff_rv$port1__read[71:0] ; + assign m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3186 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3055 && + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3182 && m_vvrg_ie_0_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3153 = + assign m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d3280 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3149 && + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d3276 && m_vvrg_ie_1_10 ; - assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 = + assign m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d683 = m_vrg_source_ip_10 && m_vrg_source_prio_10 > - IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3064 = + IF_m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_so_ETC___d677 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; + assign m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3191 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3060 && + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3187 && m_vvrg_ie_0_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3158 = + assign m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d3285 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3154 && + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d3281 && m_vvrg_ie_1_11 ; - assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 = + assign m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d690 = m_vrg_source_ip_11 && m_vrg_source_prio_11 > - IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3069 = + IF_m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_s_ETC___d684 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; + assign m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3196 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3065 && + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3192 && m_vvrg_ie_0_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3163 = + assign m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d3290 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3159 && + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d3286 && m_vvrg_ie_1_12 ; - assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 = + assign m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d697 = m_vrg_source_ip_12 && m_vrg_source_prio_12 > - IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3074 = + IF_m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_s_ETC___d691 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; + assign m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3201 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3070 && + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3197 && m_vvrg_ie_0_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3168 = + assign m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d3295 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3164 && + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d3291 && m_vvrg_ie_1_13 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 = + assign m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d704 = m_vrg_source_ip_13 && m_vrg_source_prio_13 > - IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ; - assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 = - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 || - m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 || - m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 || - m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 || - m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 || - m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 || - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3079 = + IF_m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_s_ETC___d698 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; + assign m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d760 = + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d704 || + m_vrg_source_ip_12_read__61_AND_NOT_m_vrg_sour_ETC___d697 || + m_vrg_source_ip_11_read__60_AND_NOT_m_vrg_sour_ETC___d690 || + m_vrg_source_ip_10_read__59_AND_NOT_m_vrg_sour_ETC___d683 || + m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d676 || + m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d669 || + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d754 ; + assign m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3206 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3075 && + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3202 && m_vvrg_ie_0_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3173 = + assign m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d3300 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3169 && + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d3296 && m_vvrg_ie_1_14 ; - assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 = + assign m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d711 = m_vrg_source_ip_14 && m_vrg_source_prio_14 > - IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3084 = + IF_m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_s_ETC___d705 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; + assign m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3211 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3080 && + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3207 && m_vvrg_ie_0_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3178 = + assign m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d3305 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3174 && + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d3301 && m_vvrg_ie_1_15 ; - assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 = + assign m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d718 = m_vrg_source_ip_15 && m_vrg_source_prio_15 > - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3089 = + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d712 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; + assign m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3216 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3085 && + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3212 && m_vvrg_ie_0_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3183 = + assign m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d3310 = m_vrg_source_ip_16 && m_vrg_source_prio_16 > - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3179 && + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d3306 && m_vvrg_ie_1_16 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 = + assign m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d725 = m_vrg_source_ip_16 && - !m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ; - assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 || - m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 || - m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 || - m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d691 ; - assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 = + !m_vrg_source_prio_16_32_ULE_IF_m_vrg_source_ip_ETC___d720 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q49 ; + assign m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d763 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d725 || + m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d718 || + m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_sour_ETC___d711 || + m_vrg_source_ip_13_read__62_AND_NOT_m_vrg_sour_ETC___d760 ; + assign m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_sourc_ETC___d620 = m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3019 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; + assign m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3146 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3015 && + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3142 && m_vvrg_ie_0_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3113 = + assign m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d3240 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3109 && + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d3236 && m_vvrg_ie_1_2 ; - assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 = + assign m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d627 = m_vrg_source_ip_2 && m_vrg_source_prio_2 > - IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3024 = + IF_m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_so_ETC___d621 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; + assign m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3151 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3020 && + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3147 && m_vvrg_ie_0_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3118 = + assign m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d3245 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3114 && + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d3241 && m_vvrg_ie_1_3 ; - assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 = + assign m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d634 = m_vrg_source_ip_3 && m_vrg_source_prio_3 > - IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3029 = + IF_m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_so_ETC___d628 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; + assign m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3156 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3025 && + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3152 && m_vvrg_ie_0_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3123 = + assign m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d3250 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3119 && + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d3246 && m_vvrg_ie_1_4 ; - assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 = + assign m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d641 = m_vrg_source_ip_4 && m_vrg_source_prio_4 > - IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3034 = + IF_m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_so_ETC___d635 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; + assign m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3161 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3030 && + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3157 && m_vvrg_ie_0_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3128 = + assign m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d3255 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3124 && + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d3251 && m_vvrg_ie_1_5 ; - assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 = + assign m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d648 = m_vrg_source_ip_5 && m_vrg_source_prio_5 > - IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3039 = + IF_m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_so_ETC___d642 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; + assign m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3166 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3035 && + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3162 && m_vvrg_ie_0_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3133 = + assign m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d3260 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3129 && + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d3256 && m_vvrg_ie_1_6 ; - assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 = + assign m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d655 = m_vrg_source_ip_6 && m_vrg_source_prio_6 > - IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3044 = + IF_m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_so_ETC___d649 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; + assign m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3171 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3040 && + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3167 && m_vvrg_ie_0_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3138 = + assign m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d3265 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3134 && + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d3261 && m_vvrg_ie_1_7 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 = + assign m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d662 = m_vrg_source_ip_7 && m_vrg_source_prio_7 > - IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ; - assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d685 = - m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 || - m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 || - m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 || - m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 || - m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 || - m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 || - m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3049 = + IF_m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_so_ETC___d656 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; + assign m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d754 = + m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_sourc_ETC___d662 || + m_vrg_source_ip_6_read__55_AND_NOT_m_vrg_sourc_ETC___d655 || + m_vrg_source_ip_5_read__54_AND_NOT_m_vrg_sourc_ETC___d648 || + m_vrg_source_ip_4_read__53_AND_NOT_m_vrg_sourc_ETC___d641 || + m_vrg_source_ip_3_read__52_AND_NOT_m_vrg_sourc_ETC___d634 || + m_vrg_source_ip_2_read__51_AND_NOT_m_vrg_sourc_ETC___d627 || + m_vrg_source_ip_1_read__50_AND_NOT_m_vrg_sourc_ETC___d620 ; + assign m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3176 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3045 && + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3172 && m_vvrg_ie_0_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3143 = + assign m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d3270 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3139 && + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d3266 && m_vvrg_ie_1_8 ; - assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 = + assign m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_sourc_ETC___d669 = m_vrg_source_ip_8 && m_vrg_source_prio_8 > - IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3054 = + IF_m_vrg_source_ip_7_read__56_AND_NOT_m_vrg_so_ETC___d663 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; + assign m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3181 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3050 && + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3177 && m_vvrg_ie_0_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3148 = + assign m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d3275 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3144 && + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d3271 && m_vvrg_ie_1_9 ; - assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 = + assign m_vrg_source_ip_9_read__58_AND_NOT_m_vrg_sourc_ETC___d676 = m_vrg_source_ip_9 && m_vrg_source_prio_9 > - IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 && - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ; - assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 = + IF_m_vrg_source_ip_8_read__57_AND_NOT_m_vrg_so_ETC___d670 && + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ; + assign m_vrg_source_prio_16_32_ULE_IF_m_vrg_source_ip_ETC___d720 = m_vrg_source_prio_16 <= - (m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ? + (m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_sour_ETC___d718 ? m_vrg_source_prio_15 : - IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ; - assign max_id__h23957 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ? + IF_m_vrg_source_ip_14_read__63_AND_NOT_m_vrg_s_ETC___d712) ; + assign max_id__h26424 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d725 ? 5'd16 : - IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ; - assign rdata___1__h26402 = { rdata__h26200[31:0], 32'h0 } ; - assign rdata__h26200 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? + IF_m_vrg_source_ip_15_read__64_AND_NOT_m_vrg_s_ETC___d740 ; + assign rdata___1__h28973 = { rdata__h28669[31:0], 32'h0 } ; + assign rdata__h28669 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 ? 64'd0 : - y_avValue_fst__h26192 ; - assign rresp__h26201 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ? - 2'b11 : - y_avValue_snd__h26193 ; - assign source_id__h15663 = { addr_offset__h13214[4:0], 5'd31 } ; - assign source_id__h15770 = { addr_offset__h13214[4:0], 5'd30 } ; - assign source_id__h15843 = { addr_offset__h13214[4:0], 5'd29 } ; - assign source_id__h15916 = { addr_offset__h13214[4:0], 5'd28 } ; - assign source_id__h15989 = { addr_offset__h13214[4:0], 5'd27 } ; - assign source_id__h16062 = { addr_offset__h13214[4:0], 5'd26 } ; - assign source_id__h16135 = { addr_offset__h13214[4:0], 5'd25 } ; - assign source_id__h16208 = { addr_offset__h13214[4:0], 5'd24 } ; - assign source_id__h16281 = { addr_offset__h13214[4:0], 5'd23 } ; - assign source_id__h16354 = { addr_offset__h13214[4:0], 5'd22 } ; - assign source_id__h16427 = { addr_offset__h13214[4:0], 5'd21 } ; - assign source_id__h16500 = { addr_offset__h13214[4:0], 5'd20 } ; - assign source_id__h16573 = { addr_offset__h13214[4:0], 5'd19 } ; - assign source_id__h16646 = { addr_offset__h13214[4:0], 5'd18 } ; - assign source_id__h16719 = { addr_offset__h13214[4:0], 5'd17 } ; - assign source_id__h16792 = { addr_offset__h13214[4:0], 5'd16 } ; - assign source_id__h16865 = { addr_offset__h13214[4:0], 5'd15 } ; - assign source_id__h16938 = { addr_offset__h13214[4:0], 5'd14 } ; - assign source_id__h17011 = { addr_offset__h13214[4:0], 5'd13 } ; - assign source_id__h17084 = { addr_offset__h13214[4:0], 5'd12 } ; - assign source_id__h17157 = { addr_offset__h13214[4:0], 5'd11 } ; - assign source_id__h17230 = { addr_offset__h13214[4:0], 5'd10 } ; - assign source_id__h17303 = { addr_offset__h13214[4:0], 5'd9 } ; - assign source_id__h17376 = { addr_offset__h13214[4:0], 5'd8 } ; - assign source_id__h17449 = { addr_offset__h13214[4:0], 5'd7 } ; - assign source_id__h17522 = { addr_offset__h13214[4:0], 5'd6 } ; - assign source_id__h17595 = { addr_offset__h13214[4:0], 5'd5 } ; - assign source_id__h17668 = { addr_offset__h13214[4:0], 5'd4 } ; - assign source_id__h17741 = { addr_offset__h13214[4:0], 5'd3 } ; - assign source_id__h17814 = { addr_offset__h13214[4:0], 5'd2 } ; - assign source_id__h17887 = { addr_offset__h13214[4:0], 5'd1 } ; - assign source_id__h20135 = 10'd31 + source_id_base__h13628 ; - assign source_id__h20311 = 10'd30 + source_id_base__h13628 ; - assign source_id__h20419 = 10'd29 + source_id_base__h13628 ; - assign source_id__h20527 = 10'd28 + source_id_base__h13628 ; - assign source_id__h20635 = 10'd27 + source_id_base__h13628 ; - assign source_id__h20743 = 10'd26 + source_id_base__h13628 ; - assign source_id__h20851 = 10'd25 + source_id_base__h13628 ; - assign source_id__h20959 = 10'd24 + source_id_base__h13628 ; - assign source_id__h21067 = 10'd23 + source_id_base__h13628 ; - assign source_id__h21175 = 10'd22 + source_id_base__h13628 ; - assign source_id__h21283 = 10'd21 + source_id_base__h13628 ; - assign source_id__h21391 = 10'd20 + source_id_base__h13628 ; - assign source_id__h21499 = 10'd19 + source_id_base__h13628 ; - assign source_id__h21607 = 10'd18 + source_id_base__h13628 ; - assign source_id__h21715 = 10'd17 + source_id_base__h13628 ; - assign source_id__h21823 = 10'd16 + source_id_base__h13628 ; - assign source_id__h21931 = 10'd15 + source_id_base__h13628 ; - assign source_id__h22039 = 10'd14 + source_id_base__h13628 ; - assign source_id__h22147 = 10'd13 + source_id_base__h13628 ; - assign source_id__h22255 = 10'd12 + source_id_base__h13628 ; - assign source_id__h22363 = 10'd11 + source_id_base__h13628 ; - assign source_id__h22471 = 10'd10 + source_id_base__h13628 ; - assign source_id__h22579 = 10'd9 + source_id_base__h13628 ; - assign source_id__h22687 = 10'd8 + source_id_base__h13628 ; - assign source_id__h22795 = 10'd7 + source_id_base__h13628 ; - assign source_id__h22903 = 10'd6 + source_id_base__h13628 ; - assign source_id__h23011 = 10'd5 + source_id_base__h13628 ; - assign source_id__h23119 = 10'd4 + source_id_base__h13628 ; - assign source_id__h23227 = 10'd3 + source_id_base__h13628 ; - assign source_id__h23335 = 10'd2 + source_id_base__h13628 ; - assign source_id__h23443 = 10'd1 + source_id_base__h13628 ; - assign source_id__h29464 = { addr_offset__h26920[4:0], 5'd1 } ; - assign source_id__h30674 = { addr_offset__h26920[4:0], 5'd2 } ; - assign source_id__h31884 = { addr_offset__h26920[4:0], 5'd3 } ; - assign source_id__h33094 = { addr_offset__h26920[4:0], 5'd4 } ; - assign source_id__h34304 = { addr_offset__h26920[4:0], 5'd5 } ; - assign source_id__h35514 = { addr_offset__h26920[4:0], 5'd6 } ; - assign source_id__h36724 = { addr_offset__h26920[4:0], 5'd7 } ; - assign source_id__h37934 = { addr_offset__h26920[4:0], 5'd8 } ; - assign source_id__h39144 = { addr_offset__h26920[4:0], 5'd9 } ; - assign source_id__h40354 = { addr_offset__h26920[4:0], 5'd10 } ; - assign source_id__h41564 = { addr_offset__h26920[4:0], 5'd11 } ; - assign source_id__h42774 = { addr_offset__h26920[4:0], 5'd12 } ; - assign source_id__h43984 = { addr_offset__h26920[4:0], 5'd13 } ; - assign source_id__h45194 = { addr_offset__h26920[4:0], 5'd14 } ; - assign source_id__h46404 = { addr_offset__h26920[4:0], 5'd15 } ; - assign source_id__h47614 = { addr_offset__h26920[4:0], 5'd16 } ; - assign source_id__h48824 = { addr_offset__h26920[4:0], 5'd17 } ; - assign source_id__h50034 = { addr_offset__h26920[4:0], 5'd18 } ; - assign source_id__h51244 = { addr_offset__h26920[4:0], 5'd19 } ; - assign source_id__h52454 = { addr_offset__h26920[4:0], 5'd20 } ; - assign source_id__h53664 = { addr_offset__h26920[4:0], 5'd21 } ; - assign source_id__h54874 = { addr_offset__h26920[4:0], 5'd22 } ; - assign source_id__h56084 = { addr_offset__h26920[4:0], 5'd23 } ; - assign source_id__h57294 = { addr_offset__h26920[4:0], 5'd24 } ; - assign source_id__h58504 = { addr_offset__h26920[4:0], 5'd25 } ; - assign source_id__h59714 = { addr_offset__h26920[4:0], 5'd26 } ; - assign source_id__h60924 = { addr_offset__h26920[4:0], 5'd27 } ; - assign source_id__h62134 = { addr_offset__h26920[4:0], 5'd28 } ; - assign source_id__h63344 = { addr_offset__h26920[4:0], 5'd29 } ; - assign source_id__h64554 = { addr_offset__h26920[4:0], 5'd30 } ; - assign source_id__h65764 = { addr_offset__h26920[4:0], 5'd31 } ; - assign source_id__h67425 = { 5'd0, x__h67476 } ; - assign source_id_base__h13628 = { addr_offset__h13214[4:0], 5'h0 } ; - assign source_id_base__h28137 = { addr_offset__h26920[4:0], 5'h0 } ; - assign v__h13420 = { 61'd0, x__h13491 } ; - assign v__h13669 = { 32'd0, v_ip__h13672 } ; - assign v__h18142 = { 32'd0, v_ie__h18145 } ; - assign v__h23759 = { 61'd0, x__h23830 } ; - assign v__h25453 = - m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d694 ? - v__h25472 : + y_avValue_fst__h28661 ; + assign source_id__h18127 = { addr_offset__h15646[4:0], 5'd31 } ; + assign source_id__h18234 = { addr_offset__h15646[4:0], 5'd30 } ; + assign source_id__h18307 = { addr_offset__h15646[4:0], 5'd29 } ; + assign source_id__h18380 = { addr_offset__h15646[4:0], 5'd28 } ; + assign source_id__h18453 = { addr_offset__h15646[4:0], 5'd27 } ; + assign source_id__h18526 = { addr_offset__h15646[4:0], 5'd26 } ; + assign source_id__h18599 = { addr_offset__h15646[4:0], 5'd25 } ; + assign source_id__h18672 = { addr_offset__h15646[4:0], 5'd24 } ; + assign source_id__h18745 = { addr_offset__h15646[4:0], 5'd23 } ; + assign source_id__h18818 = { addr_offset__h15646[4:0], 5'd22 } ; + assign source_id__h18891 = { addr_offset__h15646[4:0], 5'd21 } ; + assign source_id__h18964 = { addr_offset__h15646[4:0], 5'd20 } ; + assign source_id__h19037 = { addr_offset__h15646[4:0], 5'd19 } ; + assign source_id__h19110 = { addr_offset__h15646[4:0], 5'd18 } ; + assign source_id__h19183 = { addr_offset__h15646[4:0], 5'd17 } ; + assign source_id__h19256 = { addr_offset__h15646[4:0], 5'd16 } ; + assign source_id__h19329 = { addr_offset__h15646[4:0], 5'd15 } ; + assign source_id__h19402 = { addr_offset__h15646[4:0], 5'd14 } ; + assign source_id__h19475 = { addr_offset__h15646[4:0], 5'd13 } ; + assign source_id__h19548 = { addr_offset__h15646[4:0], 5'd12 } ; + assign source_id__h19621 = { addr_offset__h15646[4:0], 5'd11 } ; + assign source_id__h19694 = { addr_offset__h15646[4:0], 5'd10 } ; + assign source_id__h19767 = { addr_offset__h15646[4:0], 5'd9 } ; + assign source_id__h19840 = { addr_offset__h15646[4:0], 5'd8 } ; + assign source_id__h19913 = { addr_offset__h15646[4:0], 5'd7 } ; + assign source_id__h19986 = { addr_offset__h15646[4:0], 5'd6 } ; + assign source_id__h20059 = { addr_offset__h15646[4:0], 5'd5 } ; + assign source_id__h20132 = { addr_offset__h15646[4:0], 5'd4 } ; + assign source_id__h20205 = { addr_offset__h15646[4:0], 5'd3 } ; + assign source_id__h20278 = { addr_offset__h15646[4:0], 5'd2 } ; + assign source_id__h20351 = { addr_offset__h15646[4:0], 5'd1 } ; + assign source_id__h22600 = 10'd31 + source_id_base__h16091 ; + assign source_id__h22776 = 10'd30 + source_id_base__h16091 ; + assign source_id__h22884 = 10'd29 + source_id_base__h16091 ; + assign source_id__h22992 = 10'd28 + source_id_base__h16091 ; + assign source_id__h23100 = 10'd27 + source_id_base__h16091 ; + assign source_id__h23208 = 10'd26 + source_id_base__h16091 ; + assign source_id__h23316 = 10'd25 + source_id_base__h16091 ; + assign source_id__h23424 = 10'd24 + source_id_base__h16091 ; + assign source_id__h23532 = 10'd23 + source_id_base__h16091 ; + assign source_id__h23640 = 10'd22 + source_id_base__h16091 ; + assign source_id__h23748 = 10'd21 + source_id_base__h16091 ; + assign source_id__h23856 = 10'd20 + source_id_base__h16091 ; + assign source_id__h23964 = 10'd19 + source_id_base__h16091 ; + assign source_id__h24072 = 10'd18 + source_id_base__h16091 ; + assign source_id__h24180 = 10'd17 + source_id_base__h16091 ; + assign source_id__h24288 = 10'd16 + source_id_base__h16091 ; + assign source_id__h24396 = 10'd15 + source_id_base__h16091 ; + assign source_id__h24504 = 10'd14 + source_id_base__h16091 ; + assign source_id__h24612 = 10'd13 + source_id_base__h16091 ; + assign source_id__h24720 = 10'd12 + source_id_base__h16091 ; + assign source_id__h24828 = 10'd11 + source_id_base__h16091 ; + assign source_id__h24936 = 10'd10 + source_id_base__h16091 ; + assign source_id__h25044 = 10'd9 + source_id_base__h16091 ; + assign source_id__h25152 = 10'd8 + source_id_base__h16091 ; + assign source_id__h25260 = 10'd7 + source_id_base__h16091 ; + assign source_id__h25368 = 10'd6 + source_id_base__h16091 ; + assign source_id__h25476 = 10'd5 + source_id_base__h16091 ; + assign source_id__h25584 = 10'd4 + source_id_base__h16091 ; + assign source_id__h25692 = 10'd3 + source_id_base__h16091 ; + assign source_id__h25800 = 10'd2 + source_id_base__h16091 ; + assign source_id__h25908 = 10'd1 + source_id_base__h16091 ; + assign source_id__h32311 = { addr_offset__h29732[4:0], 5'd1 } ; + assign source_id__h33521 = { addr_offset__h29732[4:0], 5'd2 } ; + assign source_id__h34731 = { addr_offset__h29732[4:0], 5'd3 } ; + assign source_id__h35941 = { addr_offset__h29732[4:0], 5'd4 } ; + assign source_id__h37151 = { addr_offset__h29732[4:0], 5'd5 } ; + assign source_id__h38361 = { addr_offset__h29732[4:0], 5'd6 } ; + assign source_id__h39571 = { addr_offset__h29732[4:0], 5'd7 } ; + assign source_id__h40781 = { addr_offset__h29732[4:0], 5'd8 } ; + assign source_id__h41991 = { addr_offset__h29732[4:0], 5'd9 } ; + assign source_id__h43201 = { addr_offset__h29732[4:0], 5'd10 } ; + assign source_id__h44411 = { addr_offset__h29732[4:0], 5'd11 } ; + assign source_id__h45621 = { addr_offset__h29732[4:0], 5'd12 } ; + assign source_id__h46831 = { addr_offset__h29732[4:0], 5'd13 } ; + assign source_id__h48041 = { addr_offset__h29732[4:0], 5'd14 } ; + assign source_id__h49251 = { addr_offset__h29732[4:0], 5'd15 } ; + assign source_id__h50461 = { addr_offset__h29732[4:0], 5'd16 } ; + assign source_id__h51671 = { addr_offset__h29732[4:0], 5'd17 } ; + assign source_id__h52881 = { addr_offset__h29732[4:0], 5'd18 } ; + assign source_id__h54091 = { addr_offset__h29732[4:0], 5'd19 } ; + assign source_id__h55301 = { addr_offset__h29732[4:0], 5'd20 } ; + assign source_id__h56511 = { addr_offset__h29732[4:0], 5'd21 } ; + assign source_id__h57721 = { addr_offset__h29732[4:0], 5'd22 } ; + assign source_id__h58931 = { addr_offset__h29732[4:0], 5'd23 } ; + assign source_id__h60141 = { addr_offset__h29732[4:0], 5'd24 } ; + assign source_id__h61351 = { addr_offset__h29732[4:0], 5'd25 } ; + assign source_id__h62561 = { addr_offset__h29732[4:0], 5'd26 } ; + assign source_id__h63771 = { addr_offset__h29732[4:0], 5'd27 } ; + assign source_id__h64981 = { addr_offset__h29732[4:0], 5'd28 } ; + assign source_id__h66191 = { addr_offset__h29732[4:0], 5'd29 } ; + assign source_id__h67401 = { addr_offset__h29732[4:0], 5'd30 } ; + assign source_id__h68611 = { addr_offset__h29732[4:0], 5'd31 } ; + assign source_id__h70276 = { 5'd0, x__h70328 } ; + assign source_id_base__h16091 = { addr_offset__h15646[4:0], 5'h0 } ; + assign source_id_base__h30983 = { addr_offset__h29732[4:0], 5'h0 } ; + assign v__h15883 = { 61'd0, x__h15954 } ; + assign v__h16133 = { 32'd0, v_ip__h16136 } ; + assign v__h20607 = { 32'd0, v_ie__h20610 } ; + assign v__h26225 = { 61'd0, x__h26296 } ; + assign v__h27922 = + m_vrg_source_ip_16_read__65_AND_NOT_m_vrg_sour_ETC___d763 ? + v__h27941 : 64'd0 ; - assign v__h25472 = { 59'd0, max_id__h23957 } ; - assign v__h26925 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 ? - 2'b11 : - v__h27083 ; - assign v__h27083 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 ? - v__h27096 : - v__h27931 ; - assign v__h27096 = - (addr_offset__h26920[11:2] != 10'd0 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d848) ? - 2'b0 : - 2'b10 ; - assign v__h27931 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d846 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899) ? - v__h27950 : - v__h28114 ; - assign v__h27950 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 ? - 2'b0 : - 2'b10 ; - assign v__h28114 = - (!m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d899 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d913) ? - v__h28133 : - v__h67096 ; - assign v__h28133 = - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d902 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d914) ? - 2'b0 : - 2'b10 ; - assign v__h67133 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? - 2'b0 : - 2'b10 ; - assign v__h67421 = - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d2879 ? - v__h67465 : - 2'b10 ; - assign v__h67465 = - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 ? - 2'b0 : - 2'b10 ; - assign v_ie__h18145 = - { source_id__h20135 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1, - source_id__h20311 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, - source_id__h20419 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, - source_id__h20527 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, - source_id__h20635 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, - source_id__h20743 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, - source_id__h20851 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, - source_id__h20959 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, - source_id__h21067 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, - source_id__h21175 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, - source_id__h21283 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, - source_id__h21391 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, - source_id__h21499 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, - source_id__h21607 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, - source_id__h21715 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, - source_id__h21823 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, - source_id__h21931 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, - source_id__h22039 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, - source_id__h22147 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, - source_id__h22255 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, - source_id__h22363 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, - source_id__h22471 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, - source_id__h22579 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, - source_id__h22687 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, - source_id__h22795 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, - source_id__h22903 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, - source_id__h23011 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, - source_id__h23119 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, - source_id__h23227 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, - source_id__h23335 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, - source_id__h23443 <= 10'd16 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ; - assign v_ip__h13672 = - { source_id__h15663 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98, - source_id__h15770 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102, - source_id__h15843 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107, - source_id__h15916 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111, - source_id__h15989 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116, - source_id__h16062 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120, - source_id__h16135 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125, - source_id__h16208 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129, - source_id__h16281 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134, - source_id__h16354 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138, - source_id__h16427 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143, - source_id__h16500 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147, - source_id__h16573 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152, - source_id__h16646 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156, - source_id__h16719 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161, - source_id__h16792 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165, - source_id__h16865 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170, - source_id__h16938 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174, - source_id__h17011 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179, - source_id__h17084 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183, - source_id__h17157 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188, - source_id__h17230 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192, - source_id__h17303 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197, - source_id__h17376 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201, - source_id__h17449 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206, - source_id__h17522 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210, - source_id__h17595 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215, - source_id__h17668 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219, - source_id__h17741 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224, - source_id__h17814 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228, - source_id__h17887 <= 10'd16 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233, - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ; - assign wdata32__h26921 = - (addr_offset__h26920[2:0] == 3'd4) ? - m_slave_xactor_f_wr_data$D_OUT[72:41] : - m_slave_xactor_f_wr_data$D_OUT[40:9] ; - assign x__h23671 = - { addr_offset__h13214[31:16], 4'd0, addr_offset__h13214[11:0] } ; - assign x__h26359 = - (addr_offset__h13214[2:0] == 3'd4) ? - rdata___1__h26402 : - rdata__h26200 ; - assign x__h67099 = - { addr_offset__h26920[31:16], 4'd0, addr_offset__h26920[11:0] } ; - assign y_avValue_fst__h26092 = (x__h24009 == 5'd0) ? v__h25453 : 64'd0 ; - assign y_avValue_fst__h26113 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_fst__h26092 : + assign v__h27941 = { 59'd0, max_id__h26424 } ; + assign v_ie__h20610 = + { source_id__h22600 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2, + source_id__h22776 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3, + source_id__h22884 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4, + source_id__h22992 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5, + source_id__h23100 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6, + source_id__h23208 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7, + source_id__h23316 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8, + source_id__h23424 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9, + source_id__h23532 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10, + source_id__h23640 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11, + source_id__h23748 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12, + source_id__h23856 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13, + source_id__h23964 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14, + source_id__h24072 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15, + source_id__h24180 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16, + source_id__h24288 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17, + source_id__h24396 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18, + source_id__h24504 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19, + source_id__h24612 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20, + source_id__h24720 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21, + source_id__h24828 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22, + source_id__h24936 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23, + source_id__h25044 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24, + source_id__h25152 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25, + source_id__h25260 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26, + source_id__h25368 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27, + source_id__h25476 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28, + source_id__h25584 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29, + source_id__h25692 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30, + source_id__h25800 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31, + source_id__h25908 <= 10'd16 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q33 } ; + assign v_ip__h16136 = + { source_id__h18127 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167, + source_id__h18234 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171, + source_id__h18307 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176, + source_id__h18380 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180, + source_id__h18453 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185, + source_id__h18526 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189, + source_id__h18599 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194, + source_id__h18672 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198, + source_id__h18745 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203, + source_id__h18818 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207, + source_id__h18891 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212, + source_id__h18964 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216, + source_id__h19037 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221, + source_id__h19110 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225, + source_id__h19183 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230, + source_id__h19256 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234, + source_id__h19329 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239, + source_id__h19402 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243, + source_id__h19475 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248, + source_id__h19548 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252, + source_id__h19621 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257, + source_id__h19694 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261, + source_id__h19767 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266, + source_id__h19840 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270, + source_id__h19913 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275, + source_id__h19986 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279, + source_id__h20059 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284, + source_id__h20132 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288, + source_id__h20205 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293, + source_id__h20278 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297, + source_id__h20351 <= 10'd16 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302, + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 } ; + assign wdata32__h29733 = + (addr_offset__h29732[2:0] == 3'd4) ? + m_slave_xactor_shim_wff_rv$port1__read[72:41] : + m_slave_xactor_shim_wff_rv$port1__read[40:9] ; + assign x__h26136 = + { addr_offset__h15646[31:16], 4'd0, addr_offset__h15646[11:0] } ; + assign x__h28872 = + (addr_offset__h15646[2:0] == 3'd4) ? + rdata___1__h28973 : + rdata__h28669 ; + assign x__h69947 = + { addr_offset__h29732[31:16], 4'd0, addr_offset__h29732[11:0] } ; + assign y_avValue_fst__h28561 = (x__h26477 == 5'd0) ? v__h27922 : 64'd0 ; + assign y_avValue_fst__h28582 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 ? + y_avValue_fst__h28561 : 64'd0 ; - assign y_avValue_fst__h26125 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - v__h23759 : + assign y_avValue_fst__h28594 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 ? + v__h26225 : 64'd0 ; - assign y_avValue_fst__h26141 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - v__h18142 : + assign y_avValue_fst__h28610 = + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d311) ? + v__h20607 : 64'd0 ; - assign y_avValue_fst__h26157 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - v__h13669 : + assign y_avValue_fst__h28626 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d140 ? + v__h16133 : 64'd0 ; - assign y_avValue_fst__h26162 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_fst__h26141 : - y_avValue_fst__h26146 ; - assign y_avValue_fst__h26173 = - (addr_offset__h13214[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - v__h13420 : + assign y_avValue_fst__h28631 = + (!m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d309) ? + y_avValue_fst__h28610 : + y_avValue_fst__h28615 ; + assign y_avValue_fst__h28642 = + (addr_offset__h15646[11:2] != 10'd0 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d109) ? + v__h15883 : 64'd0 ; - assign y_avValue_fst__h26178 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_fst__h26157 : - y_avValue_fst__h26162 ; - assign y_avValue_fst__h26192 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_fst__h26173 : - y_avValue_fst__h26178 ; - assign y_avValue_snd__h26093 = (x__h24009 == 5'd0) ? 2'b0 : 2'b10 ; - assign y_avValue_snd__h26114 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - y_avValue_snd__h26093 : - 2'b10 ; - assign y_avValue_snd__h26126 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26142 = - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26158 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26163 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ? - y_avValue_snd__h26142 : - y_avValue_snd__h26147 ; - assign y_avValue_snd__h26174 = - (addr_offset__h13214[11:2] != 10'd0 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ? - 2'b0 : - 2'b10 ; - assign y_avValue_snd__h26179 = - (!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ? - y_avValue_snd__h26158 : - y_avValue_snd__h26163 ; - assign y_avValue_snd__h26193 = - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ? - y_avValue_snd__h26174 : - y_avValue_snd__h26179 ; - always@(addr_offset__h13214 or + assign y_avValue_fst__h28647 = + (!m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d137) ? + y_avValue_fst__h28626 : + y_avValue_fst__h28631 ; + assign y_avValue_fst__h28661 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 ? + y_avValue_fst__h28642 : + y_avValue_fst__h28647 ; + always@(addr_offset__h29732 or + m_vrg_servicing_source_0 or m_vrg_servicing_source_1) + begin + case (addr_offset__h29732[16:12]) + 5'd0: x__h70328 = m_vrg_servicing_source_0; + 5'd1: x__h70328 = m_vrg_servicing_source_1; + default: x__h70328 = 5'b01010 /* unspecified value */ ; + endcase + end + always@(source_id__h70276 or + m_vrg_source_busy_0 or + m_vrg_source_busy_1 or + m_vrg_source_busy_2 or + m_vrg_source_busy_3 or + m_vrg_source_busy_4 or + m_vrg_source_busy_5 or + m_vrg_source_busy_6 or + m_vrg_source_busy_7 or + m_vrg_source_busy_8 or + m_vrg_source_busy_9 or + m_vrg_source_busy_10 or + m_vrg_source_busy_11 or + m_vrg_source_busy_12 or + m_vrg_source_busy_13 or + m_vrg_source_busy_14 or + m_vrg_source_busy_15 or m_vrg_source_busy_16) + begin + case (source_id__h70276) + 10'd0: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_0; + 10'd1: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_1; + 10'd2: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_2; + 10'd3: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_3; + 10'd4: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_4; + 10'd5: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_5; + 10'd6: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_6; + 10'd7: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_7; + 10'd8: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_8; + 10'd9: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_9; + 10'd10: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_10; + 10'd11: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_11; + 10'd12: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_12; + 10'd13: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_13; + 10'd14: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_14; + 10'd15: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_15; + 10'd16: + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + m_vrg_source_busy_16; + default: SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(x__h69947 or + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 or + SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030) + begin + case (x__h69947) + 32'h00200000: + CASE_x9947_0x200000_IF_m_slave_xactor_shim_awf_ETC__q1 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 ? + 2'd0 : + 2'd2; + 32'h00200004: + CASE_x9947_0x200000_IF_m_slave_xactor_shim_awf_ETC__q1 = + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d2991 ? + (SEL_ARR_m_vrg_source_busy_0_012_m_vrg_source_b_ETC___d3030 ? + 2'd0 : + 2'd2) : + 2'd2; + default: CASE_x9947_0x200000_IF_m_slave_xactor_shim_awf_ETC__q1 = 2'd2; + endcase + end + always@(addr_offset__h15646 or m_vrg_source_prio_0 or m_vrg_source_prio_1 or m_vrg_source_prio_2 or @@ -16808,128 +17230,46 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_prio_14 or m_vrg_source_prio_15 or m_vrg_source_prio_16) begin - case (addr_offset__h13214[11:2]) - 10'd0: x__h13491 = m_vrg_source_prio_0; - 10'd1: x__h13491 = m_vrg_source_prio_1; - 10'd2: x__h13491 = m_vrg_source_prio_2; - 10'd3: x__h13491 = m_vrg_source_prio_3; - 10'd4: x__h13491 = m_vrg_source_prio_4; - 10'd5: x__h13491 = m_vrg_source_prio_5; - 10'd6: x__h13491 = m_vrg_source_prio_6; - 10'd7: x__h13491 = m_vrg_source_prio_7; - 10'd8: x__h13491 = m_vrg_source_prio_8; - 10'd9: x__h13491 = m_vrg_source_prio_9; - 10'd10: x__h13491 = m_vrg_source_prio_10; - 10'd11: x__h13491 = m_vrg_source_prio_11; - 10'd12: x__h13491 = m_vrg_source_prio_12; - 10'd13: x__h13491 = m_vrg_source_prio_13; - 10'd14: x__h13491 = m_vrg_source_prio_14; - 10'd15: x__h13491 = m_vrg_source_prio_15; - 10'd16: x__h13491 = m_vrg_source_prio_16; - default: x__h13491 = 3'b010 /* unspecified value */ ; + case (addr_offset__h15646[11:2]) + 10'd0: x__h15954 = m_vrg_source_prio_0; + 10'd1: x__h15954 = m_vrg_source_prio_1; + 10'd2: x__h15954 = m_vrg_source_prio_2; + 10'd3: x__h15954 = m_vrg_source_prio_3; + 10'd4: x__h15954 = m_vrg_source_prio_4; + 10'd5: x__h15954 = m_vrg_source_prio_5; + 10'd6: x__h15954 = m_vrg_source_prio_6; + 10'd7: x__h15954 = m_vrg_source_prio_7; + 10'd8: x__h15954 = m_vrg_source_prio_8; + 10'd9: x__h15954 = m_vrg_source_prio_9; + 10'd10: x__h15954 = m_vrg_source_prio_10; + 10'd11: x__h15954 = m_vrg_source_prio_11; + 10'd12: x__h15954 = m_vrg_source_prio_12; + 10'd13: x__h15954 = m_vrg_source_prio_13; + 10'd14: x__h15954 = m_vrg_source_prio_14; + 10'd15: x__h15954 = m_vrg_source_prio_15; + 10'd16: x__h15954 = m_vrg_source_prio_16; + default: x__h15954 = 3'b010 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or + always@(addr_offset__h15646 or m_vrg_target_threshold_0 or m_vrg_target_threshold_1) begin - case (addr_offset__h13214[16:12]) - 5'd0: x__h23830 = m_vrg_target_threshold_0; - 5'd1: x__h23830 = m_vrg_target_threshold_1; - default: x__h23830 = 3'b010 /* unspecified value */ ; - endcase - end - always@(addr_offset__h13214 or - m_vrg_servicing_source_0 or m_vrg_servicing_source_1) - begin - case (addr_offset__h13214[16:12]) - 5'd0: x__h24009 = m_vrg_servicing_source_0; - 5'd1: x__h24009 = m_vrg_servicing_source_1; - default: x__h24009 = 5'b01010 /* unspecified value */ ; + case (addr_offset__h15646[16:12]) + 5'd0: x__h26296 = m_vrg_target_threshold_0; + 5'd1: x__h26296 = m_vrg_target_threshold_1; + default: x__h26296 = 3'b010 /* unspecified value */ ; endcase end - always@(addr_offset__h26920 or + always@(addr_offset__h15646 or m_vrg_servicing_source_0 or m_vrg_servicing_source_1) begin - case (addr_offset__h26920[16:12]) - 5'd0: x__h67476 = m_vrg_servicing_source_0; - 5'd1: x__h67476 = m_vrg_servicing_source_1; - default: x__h67476 = 5'b01010 /* unspecified value */ ; - endcase - end - always@(source_id__h16208 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16208) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 = - 1'b0 /* unspecified value */ ; + case (addr_offset__h15646[16:12]) + 5'd0: x__h26477 = m_vrg_servicing_source_0; + 5'd1: x__h26477 = m_vrg_servicing_source_1; + default: x__h26477 = 5'b01010 /* unspecified value */ ; endcase end - always@(source_id_base__h13628 or + always@(source_id_base__h16091 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -16946,63 +17286,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id_base__h13628) + case (source_id_base__h16091) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d304 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20311 or + always@(source_id__h22776 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17019,63 +17359,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20311) + case (source_id__h22776) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20311 or + always@(source_id__h22776 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17092,63 +17432,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20311) + case (source_id__h22776) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20135 or + always@(source_id__h22600 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17165,63 +17505,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20135) + case (source_id__h22600) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20135 or + always@(source_id__h22600 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17238,63 +17578,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20135) + case (source_id__h22600) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h15663 or + always@(source_id__h18127 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17311,63 +17651,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h15663) + case (source_id__h18127) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d167 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20419 or + always@(source_id__h22884 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17384,63 +17724,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20419) + case (source_id__h22884) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20419 or + always@(source_id__h22884 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17457,63 +17797,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20419) + case (source_id__h22884) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20527 or + always@(source_id__h22992 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17530,63 +17870,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20527) + case (source_id__h22992) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20527 or + always@(source_id__h22992 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17603,63 +17943,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20527) + case (source_id__h22992) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h15770 or + always@(source_id__h18234 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -17676,63 +18016,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h15770) + case (source_id__h18234) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d171 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20635 or + always@(source_id__h23100 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17749,63 +18089,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20635) + case (source_id__h23100) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20635 or + always@(source_id__h23100 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17822,63 +18162,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20635) + case (source_id__h23100) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20743 or + always@(source_id__h23208 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -17895,63 +18235,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20743) + case (source_id__h23208) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20743 or + always@(source_id__h23208 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -17968,63 +18308,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20743) + case (source_id__h23208) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h15843 or + always@(source_id__h18380 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18041,63 +18381,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h15843) + case (source_id__h18380) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d180 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h15916 or + always@(source_id__h18307 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18114,355 +18454,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h15916) + case (source_id__h18307) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d176 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20851 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + always@(source_id__h23316 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h20851) + case (source_id__h23316) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_0; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = + m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_1; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = + m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_2; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = + m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_3; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = + m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20851 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20851) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h20959 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h20959) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h15989 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h15989) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h20959 or + always@(source_id__h23316 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18479,136 +18600,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h20959) + case (source_id__h23316) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16062 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16062) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21067 or + always@(source_id__h23424 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18625,63 +18673,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21067) + case (source_id__h23424) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21067 or + always@(source_id__h23424 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -18698,136 +18746,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21067) + case (source_id__h23424) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21175 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h21175) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16135 or + always@(source_id__h18453 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -18844,136 +18819,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16135) + case (source_id__h18453) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d185 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21175 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + always@(source_id__h18526 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h21175) + case (source_id__h18526) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_0; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_1; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_2; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_3; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_4; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_5; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_6; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_7; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_8; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_9; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_10; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_11; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_12; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_13; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_14; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_15; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d189 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21283 or + always@(source_id__h23532 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -18990,63 +18965,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21283) + case (source_id__h23532) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21283 or + always@(source_id__h23532 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19063,63 +19038,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21283) + case (source_id__h23532) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21391 or + always@(source_id__h23640 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19136,63 +19111,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21391) + case (source_id__h23640) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21391 or + always@(source_id__h23640 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19209,63 +19184,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21391) + case (source_id__h23640) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16281 or + always@(source_id__h18599 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19282,63 +19257,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16281) + case (source_id__h18599) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d194 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16354 or + always@(source_id__h18672 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19355,63 +19330,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16354) + case (source_id__h18672) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_1; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d198 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h23748 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h23748) + 10'd0: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_0; + 10'd1: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_2; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_3; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_4; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_5; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_6; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_7; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_8; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_9; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_10; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_11; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_12; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_13; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_14; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_15; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21499 or + always@(source_id__h23748 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19428,63 +19476,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21499) + case (source_id__h23748) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21499 or + always@(source_id__h23856 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19501,136 +19549,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21499) + case (source_id__h23856) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21607 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + always@(source_id__h23856 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21607) + case (source_id__h23856) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_0; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_1; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_2; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_3; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_4; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_5; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_6; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_7; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_8; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_9; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_10; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_11; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_12; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_13; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_14; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_15; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16427 or + always@(source_id__h18818 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19647,136 +19695,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16427) + case (source_id__h18818) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h21607 or - m_vvrg_ie_1_0 or - m_vvrg_ie_1_1 or - m_vvrg_ie_1_2 or - m_vvrg_ie_1_3 or - m_vvrg_ie_1_4 or - m_vvrg_ie_1_5 or - m_vvrg_ie_1_6 or - m_vvrg_ie_1_7 or - m_vvrg_ie_1_8 or - m_vvrg_ie_1_9 or - m_vvrg_ie_1_10 or - m_vvrg_ie_1_11 or - m_vvrg_ie_1_12 or - m_vvrg_ie_1_13 or - m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) - begin - case (source_id__h21607) - 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_0; - 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_1; - 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_2; - 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_3; - 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_4; - 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_5; - 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_6; - 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_7; - 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_8; - 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_9; - 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_10; - 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_11; - 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_12; - 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_13; - 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_14; - 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_15; - 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d207 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16500 or + always@(source_id__h18745 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -19793,63 +19768,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16500) + case (source_id__h18745) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d203 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21715 or + always@(source_id__h23964 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -19866,63 +19841,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21715) + case (source_id__h23964) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21715 or + always@(source_id__h23964 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -19939,63 +19914,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21715) + case (source_id__h23964) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21823 or + always@(source_id__h24072 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20012,136 +19987,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21823) + case (source_id__h24072) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h16573 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h16573) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21823 or + always@(source_id__h24072 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20158,63 +20060,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21823) + case (source_id__h24072) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h18891 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h18891) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d212 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16646 or + always@(source_id__h18964 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20231,63 +20206,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16646) + case (source_id__h18964) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d216 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21931 or + always@(source_id__h24180 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20304,63 +20279,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h21931) + case (source_id__h24180) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h21931 or + always@(source_id__h24180 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20377,63 +20352,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h21931) + case (source_id__h24180) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22039 or + always@(source_id__h24288 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20450,63 +20425,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22039) + case (source_id__h24288) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22039 or + always@(source_id__h24288 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20523,63 +20498,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22039) + case (source_id__h24288) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16719 or + always@(source_id__h19037 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20596,63 +20571,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16719) + case (source_id__h19037) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d221 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16792 or + always@(source_id__h24396 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h24396) + 10'd0: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_0; + 10'd1: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_1; + 10'd2: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_2; + 10'd3: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_3; + 10'd4: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_4; + 10'd5: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_5; + 10'd6: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_6; + 10'd7: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_7; + 10'd8: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_8; + 10'd9: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_9; + 10'd10: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_10; + 10'd11: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_11; + 10'd12: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_12; + 10'd13: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_13; + 10'd14: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_14; + 10'd15: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_15; + 10'd16: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h19110 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20669,63 +20717,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16792) + case (source_id__h19110) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d225 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22147 or + always@(source_id__h24396 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -20742,63 +20790,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22147) + case (source_id__h24396) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22147 or + always@(source_id__h24504 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20815,63 +20863,209 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22147) + case (source_id__h24504) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h24504 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h24504) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h19183 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h19183) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d230 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22255 or + always@(source_id__h24612 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -20888,63 +21082,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22255) + case (source_id__h24612) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16865 or + always@(source_id__h19256 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -20961,63 +21155,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16865) + case (source_id__h19256) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d234 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h24612 or + m_vvrg_ie_1_0 or + m_vvrg_ie_1_1 or + m_vvrg_ie_1_2 or + m_vvrg_ie_1_3 or + m_vvrg_ie_1_4 or + m_vvrg_ie_1_5 or + m_vvrg_ie_1_6 or + m_vvrg_ie_1_7 or + m_vvrg_ie_1_8 or + m_vvrg_ie_1_9 or + m_vvrg_ie_1_10 or + m_vvrg_ie_1_11 or + m_vvrg_ie_1_12 or + m_vvrg_ie_1_13 or + m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) + begin + case (source_id__h24612) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22255 or + always@(source_id__h24720 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21034,63 +21301,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22255) + case (source_id__h24720) + 10'd0: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_0; + 10'd1: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_1; + 10'd2: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_2; + 10'd3: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_3; + 10'd4: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_4; + 10'd5: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_5; + 10'd6: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_6; + 10'd7: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_7; + 10'd8: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_8; + 10'd9: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_9; + 10'd10: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_10; + 10'd11: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_11; + 10'd12: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_12; + 10'd13: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_13; + 10'd14: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h24720 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h24720) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_0; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_1; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_2; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_3; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_4; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_5; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_6; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_7; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_8; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_9; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_10; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_11; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_12; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_13; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_14; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_15; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h16938 or + always@(source_id__h19329 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21107,63 +21447,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h16938) + case (source_id__h19329) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d239 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22363 or + always@(source_id__h24828 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21180,63 +21520,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22363) + case (source_id__h24828) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h19402 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h19402) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d243 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22363 or + always@(source_id__h24828 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21253,63 +21666,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22363) + case (source_id__h24828) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22471 or + always@(source_id__h24936 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21326,136 +21739,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22471) + case (source_id__h24936) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17011 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17011) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22471 or + always@(source_id__h24936 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21472,63 +21812,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22471) + case (source_id__h24936) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17084 or + always@(source_id__h19475 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21545,63 +21885,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17084) + case (source_id__h19475) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d248 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22579 or + always@(source_id__h25044 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21618,63 +21958,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22579) + case (source_id__h25044) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h19548 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) + begin + case (source_id__h19548) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d252 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22579 or + always@(source_id__h25044 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21691,63 +22104,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22579) + case (source_id__h25044) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22687 or + always@(source_id__h25152 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -21764,63 +22177,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22687) + case (source_id__h25152) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22687 or + always@(source_id__h25152 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -21837,63 +22250,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22687) + case (source_id__h25152) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17157 or + always@(source_id__h19621 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21910,63 +22323,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17157) + case (source_id__h19621) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d257 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17230 or + always@(source_id__h19694 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -21983,63 +22396,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17230) + case (source_id__h19694) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d261 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22795 or + always@(source_id__h25260 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22056,63 +22469,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22795) + case (source_id__h25260) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22795 or + always@(source_id__h25260 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22129,63 +22542,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22795) + case (source_id__h25260) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22903 or + always@(source_id__h25368 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22202,136 +22615,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h22903) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17303 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17303) + case (source_id__h25368) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_0; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_1; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_2; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_3; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_4; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_5; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_6; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_7; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_8; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_9; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_10; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_11; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_12; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_13; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_14; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_15; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h22903 or + always@(source_id__h25368 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22348,63 +22688,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h22903) + case (source_id__h25368) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17376 or + always@(source_id__h19767 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22421,136 +22761,136 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17376) + case (source_id__h19767) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d266 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23011 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + always@(source_id__h19840 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h23011) + case (source_id__h19840) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_0; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_1; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_2; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_3; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_4; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_5; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_6; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_7; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_8; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_9; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_10; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_11; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_12; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_13; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_14; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_15; + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d270 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23011 or + always@(source_id__h25476 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22567,63 +22907,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23011) + case (source_id__h25476) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h25476 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h25476) + 10'd0: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_0; + 10'd1: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_1; + 10'd2: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_2; + 10'd3: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_3; + 10'd4: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_4; + 10'd5: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_5; + 10'd6: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_6; + 10'd7: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_7; + 10'd8: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_8; + 10'd9: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_9; + 10'd10: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_10; + 10'd11: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_11; + 10'd12: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_12; + 10'd13: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_13; + 10'd14: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_14; + 10'd15: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_15; + 10'd16: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23119 or + always@(source_id__h25584 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -22640,63 +23053,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23119) + case (source_id__h25584) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17449 or + always@(source_id__h19913 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22713,63 +23126,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17449) + case (source_id__h19913) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d275 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23119 or + always@(source_id__h25584 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -22786,63 +23199,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23119) + case (source_id__h25584) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17522 or + always@(source_id__h19986 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -22859,136 +23272,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17522) + case (source_id__h19986) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h23227 or - m_vvrg_ie_0_0 or - m_vvrg_ie_0_1 or - m_vvrg_ie_0_2 or - m_vvrg_ie_0_3 or - m_vvrg_ie_0_4 or - m_vvrg_ie_0_5 or - m_vvrg_ie_0_6 or - m_vvrg_ie_0_7 or - m_vvrg_ie_0_8 or - m_vvrg_ie_0_9 or - m_vvrg_ie_0_10 or - m_vvrg_ie_0_11 or - m_vvrg_ie_0_12 or - m_vvrg_ie_0_13 or - m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) - begin - case (source_id__h23227) - 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_0; - 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_1; - 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_2; - 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_3; - 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_4; - 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_5; - 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_6; - 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_7; - 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_8; - 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_9; - 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_10; - 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_11; - 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_12; - 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_13; - 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_14; - 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_15; - 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = - m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d279 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23227 or + always@(source_id__h25692 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23005,63 +23345,136 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23227) + case (source_id__h25692) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_14; + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = + m_vvrg_ie_1_14; + 10'd15: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = + m_vvrg_ie_1_15; + 10'd16: + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = + m_vvrg_ie_1_16; + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(source_id__h25692 or + m_vvrg_ie_0_0 or + m_vvrg_ie_0_1 or + m_vvrg_ie_0_2 or + m_vvrg_ie_0_3 or + m_vvrg_ie_0_4 or + m_vvrg_ie_0_5 or + m_vvrg_ie_0_6 or + m_vvrg_ie_0_7 or + m_vvrg_ie_0_8 or + m_vvrg_ie_0_9 or + m_vvrg_ie_0_10 or + m_vvrg_ie_0_11 or + m_vvrg_ie_0_12 or + m_vvrg_ie_0_13 or + m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) + begin + case (source_id__h25692) + 10'd0: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_0; + 10'd1: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_1; + 10'd2: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_2; + 10'd3: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_3; + 10'd4: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_4; + 10'd5: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_5; + 10'd6: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_6; + 10'd7: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_7; + 10'd8: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_8; + 10'd9: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_9; + 10'd10: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_10; + 10'd11: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_11; + 10'd12: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_12; + 10'd13: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_13; + 10'd14: + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_15; + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = - m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = + m_vvrg_ie_0_16; + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23335 or + always@(source_id__h25800 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23078,63 +23491,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23335) + case (source_id__h25800) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23335 or + always@(source_id__h25800 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23151,63 +23564,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23335) + case (source_id__h25800) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17595 or + always@(source_id__h20059 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23224,63 +23637,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17595) + case (source_id__h20059) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d284 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17668 or + always@(source_id__h20132 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -23297,63 +23710,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17668) + case (source_id__h20132) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d288 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23443 or + always@(source_id__h25908 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23370,63 +23783,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id__h23443) + case (source_id__h25908) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h23443 or + always@(source_id__h25908 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23443,63 +23856,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id__h23443) + case (source_id__h25908) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id_base__h13628 or + always@(source_id_base__h16091 or m_vvrg_ie_0_0 or m_vvrg_ie_0_1 or m_vvrg_ie_0_2 or @@ -23516,136 +23929,63 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_0_13 or m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16) begin - case (source_id_base__h13628) + case (source_id_base__h16091) 10'd0: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_0; 10'd1: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_1; 10'd2: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_2; 10'd3: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_3; 10'd4: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_4; 10'd5: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_5; 10'd6: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_6; 10'd7: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_7; 10'd8: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_8; 10'd9: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_9; 10'd10: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_10; 10'd11: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_11; 10'd12: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_12; 10'd13: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_13; 10'd14: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_14; 10'd15: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_15; 10'd16: - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = m_vvrg_ie_0_16; - default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 = - 1'b0 /* unspecified value */ ; - endcase - end - always@(source_id__h17741 or - m_vrg_source_ip_0 or - m_vrg_source_ip_1 or - m_vrg_source_ip_2 or - m_vrg_source_ip_3 or - m_vrg_source_ip_4 or - m_vrg_source_ip_5 or - m_vrg_source_ip_6 or - m_vrg_source_ip_7 or - m_vrg_source_ip_8 or - m_vrg_source_ip_9 or - m_vrg_source_ip_10 or - m_vrg_source_ip_11 or - m_vrg_source_ip_12 or - m_vrg_source_ip_13 or - m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) - begin - case (source_id__h17741) - 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_0; - 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_1; - 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_2; - 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_3; - 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_4; - 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_5; - 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_6; - 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_7; - 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_8; - 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_9; - 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_10; - 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_11; - 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_12; - 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_13; - 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_14; - 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_15; - 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = - m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 = + default: SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id_base__h13628 or + always@(source_id_base__h16091 or m_vvrg_ie_1_0 or m_vvrg_ie_1_1 or m_vvrg_ie_1_2 or @@ -23662,543 +24002,543 @@ module mkPLIC_16_2_7(CLK, m_vvrg_ie_1_13 or m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16) begin - case (source_id_base__h13628) + case (source_id_base__h16091) 10'd0: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_0; 10'd1: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_1; 10'd2: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_2; 10'd3: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_3; 10'd4: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_4; 10'd5: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_5; 10'd6: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_6; 10'd7: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_7; 10'd8: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_8; 10'd9: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_9; 10'd10: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_10; 10'd11: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_11; 10'd12: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_12; 10'd13: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_13; 10'd14: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_14; 10'd15: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_15; 10'd16: - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = m_vvrg_ie_1_16; - default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 = + default: SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d340; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d359; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d365; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d366; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d373; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d374; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d380; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d381; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d388; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d389; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d395; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d396; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d403; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d404; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d410; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d411; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d418; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d419; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d425; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d426; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d433; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d434; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d440; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d441; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d448; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d449; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d455; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d456; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d463; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d464; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d470; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d471; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d478; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d479; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d485; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d486; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d493; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d494; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d500; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d501; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d508; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d509; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d515; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d516; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d523; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d524; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d530; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d531; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d538; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d539; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d545; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d546; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d553; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d554; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d560; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d561; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d568; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d569; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d575; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d576; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d583; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d584; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520) + always@(addr_offset__h15646 or + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588 or + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589) begin - case (addr_offset__h13214[11:7]) + case (addr_offset__h15646[11:7]) 5'd0: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519; + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q33 = + SEL_ARR_m_vvrg_ie_0_0_22_m_vvrg_ie_0_1_23_m_vv_ETC___d588; 5'd1: - CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = - SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520; - default: CASE_addr_offset3214_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 = + CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q33 = + SEL_ARR_m_vvrg_ie_1_0_41_m_vvrg_ie_1_1_42_m_vv_ETC___d589; + default: CASE_addr_offset5646_BITS_11_TO_7_0_SEL_ARR_m__ETC__q33 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17814 or + always@(source_id__h20205 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24215,63 +24555,63 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17814) + case (source_id__h20205) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d293 = 1'b0 /* unspecified value */ ; endcase end - always@(source_id__h17887 or + always@(source_id__h20278 or m_vrg_source_ip_0 or m_vrg_source_ip_1 or m_vrg_source_ip_2 or @@ -24288,366 +24628,367 @@ module mkPLIC_16_2_7(CLK, m_vrg_source_ip_13 or m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (source_id__h17887) + case (source_id__h20278) 10'd0: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_0; 10'd1: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_1; 10'd2: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_2; 10'd3: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_3; 10'd4: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_4; 10'd5: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_5; 10'd6: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_6; 10'd7: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_7; 10'd8: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_8; 10'd9: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_9; 10'd10: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_10; 10'd11: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_11; 10'd12: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_12; 10'd13: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_13; 10'd14: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_14; 10'd15: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_15; 10'd16: - SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = m_vrg_source_ip_16; - default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 = + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d297 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h23671 or y_avValue_snd__h26126 or y_avValue_snd__h26114) + always@(source_id__h20351 or + m_vrg_source_ip_0 or + m_vrg_source_ip_1 or + m_vrg_source_ip_2 or + m_vrg_source_ip_3 or + m_vrg_source_ip_4 or + m_vrg_source_ip_5 or + m_vrg_source_ip_6 or + m_vrg_source_ip_7 or + m_vrg_source_ip_8 or + m_vrg_source_ip_9 or + m_vrg_source_ip_10 or + m_vrg_source_ip_11 or + m_vrg_source_ip_12 or + m_vrg_source_ip_13 or + m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16) begin - case (x__h23671) - 32'h00200000: y_avValue_snd__h26147 = y_avValue_snd__h26126; - 32'h00200004: y_avValue_snd__h26147 = y_avValue_snd__h26114; - default: y_avValue_snd__h26147 = 2'b10; + case (source_id__h20351) + 10'd0: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_0; + 10'd1: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_1; + 10'd2: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_2; + 10'd3: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_3; + 10'd4: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_4; + 10'd5: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_5; + 10'd6: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_6; + 10'd7: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_7; + 10'd8: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_8; + 10'd9: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_9; + 10'd10: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_10; + 10'd11: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_11; + 10'd12: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_12; + 10'd13: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_13; + 10'd14: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_14; + 10'd15: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_15; + 10'd16: + SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + m_vrg_source_ip_16; + default: SEL_ARR_m_vrg_source_ip_0_read__49_m_vrg_sourc_ETC___d302 = + 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) + always@(addr_offset__h15646 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = m_vvrg_ie_0_1; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = m_vvrg_ie_1_1; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) + always@(addr_offset__h15646 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = m_vvrg_ie_0_2; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = m_vvrg_ie_1_2; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) + always@(addr_offset__h15646 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = m_vvrg_ie_0_3; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = m_vvrg_ie_1_3; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) + always@(addr_offset__h15646 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = m_vvrg_ie_0_4; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = m_vvrg_ie_1_4; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) + always@(addr_offset__h15646 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = m_vvrg_ie_0_5; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = m_vvrg_ie_1_5; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) + always@(addr_offset__h15646 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = m_vvrg_ie_0_6; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = m_vvrg_ie_1_6; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) + always@(addr_offset__h15646 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = m_vvrg_ie_0_7; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = m_vvrg_ie_1_7; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) + always@(addr_offset__h15646 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = m_vvrg_ie_0_8; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = m_vvrg_ie_1_8; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) + always@(addr_offset__h15646 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = m_vvrg_ie_0_9; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = m_vvrg_ie_1_9; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) + always@(addr_offset__h15646 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = m_vvrg_ie_0_10; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = m_vvrg_ie_1_10; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) + always@(addr_offset__h15646 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = m_vvrg_ie_0_11; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = m_vvrg_ie_1_11; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) + always@(addr_offset__h15646 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = m_vvrg_ie_0_12; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = m_vvrg_ie_1_12; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) + always@(addr_offset__h15646 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = m_vvrg_ie_0_13; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = m_vvrg_ie_1_13; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) + always@(addr_offset__h15646 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = m_vvrg_ie_0_14; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = m_vvrg_ie_1_14; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) + always@(addr_offset__h15646 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = m_vvrg_ie_0_15; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = m_vvrg_ie_1_15; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = 1'b0 /* unspecified value */ ; endcase end - always@(addr_offset__h13214 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) + always@(addr_offset__h15646 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16) begin - case (addr_offset__h13214[16:12]) + case (addr_offset__h15646[16:12]) 5'd0: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q49 = m_vvrg_ie_0_16; 5'd1: - CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q49 = m_vvrg_ie_1_16; - default: CASE_addr_offset3214_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 = + default: CASE_addr_offset5646_BITS_16_TO_12_0_m_vvrg_ie_ETC__q49 = 1'b0 /* unspecified value */ ; endcase end - always@(x__h23671 or y_avValue_fst__h26125 or y_avValue_fst__h26113) - begin - case (x__h23671) - 32'h00200000: y_avValue_fst__h26146 = y_avValue_fst__h26125; - 32'h00200004: y_avValue_fst__h26146 = y_avValue_fst__h26113; - default: y_avValue_fst__h26146 = 64'd0; - endcase - end - always@(source_id__h67425 or - m_vrg_source_busy_0 or - m_vrg_source_busy_1 or - m_vrg_source_busy_2 or - m_vrg_source_busy_3 or - m_vrg_source_busy_4 or - m_vrg_source_busy_5 or - m_vrg_source_busy_6 or - m_vrg_source_busy_7 or - m_vrg_source_busy_8 or - m_vrg_source_busy_9 or - m_vrg_source_busy_10 or - m_vrg_source_busy_11 or - m_vrg_source_busy_12 or - m_vrg_source_busy_13 or - m_vrg_source_busy_14 or - m_vrg_source_busy_15 or m_vrg_source_busy_16) + always@(x__h26136 or y_avValue_fst__h28594 or y_avValue_fst__h28582) begin - case (source_id__h67425) - 10'd0: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_0; - 10'd1: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_1; - 10'd2: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_2; - 10'd3: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_3; - 10'd4: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_4; - 10'd5: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_5; - 10'd6: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_6; - 10'd7: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_7; - 10'd8: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_8; - 10'd9: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_9; - 10'd10: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_10; - 10'd11: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_11; - 10'd12: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_12; - 10'd13: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_13; - 10'd14: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_14; - 10'd15: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_15; - 10'd16: - SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - m_vrg_source_busy_16; - default: SEL_ARR_m_vrg_source_busy_0_900_m_vrg_source_b_ETC___d2918 = - 1'b0 /* unspecified value */ ; + case (x__h26136) + 32'h00200000: y_avValue_fst__h28615 = y_avValue_fst__h28594; + 32'h00200004: y_avValue_fst__h28615 = y_avValue_fst__h28582; + default: y_avValue_fst__h28615 = 64'd0; endcase end - always@(x__h67099 or v__h67133 or v__h67421) + always@(x__h26136 or + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 or + x__h26477) begin - case (x__h67099) - 32'h00200000: v__h67096 = v__h67133; - 32'h00200004: v__h67096 = v__h67421; - default: v__h67096 = 2'b10; + case (x__h26136) + 32'h00200000: + CASE_x6136_0x200000_IF_m_slave_xactor_shim_arf_ETC__q50 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 ? + 2'd0 : + 2'd2; + 32'h00200004: + CASE_x6136_0x200000_IF_m_slave_xactor_shim_arf_ETC__q50 = + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d601 ? + ((x__h26477 == 5'd0) ? 2'd0 : 2'd2) : + 2'd2; + default: CASE_x6136_0x200000_IF_m_slave_xactor_shim_arf_ETC__q50 = 2'd2; endcase end @@ -24658,6 +24999,16 @@ module mkPLIC_16_2_7(CLK, if (RST_N == `BSV_RESET_VALUE) begin m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0; + m_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0; + m_slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY 8'd42; + m_slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + 73'h0AAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + 74'h0AAAAAAAAAAAAAAAAAA; m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY 5'd0; m_vrg_servicing_source_1 <= `BSV_ASSIGNMENT_DELAY 5'd0; m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -24752,6 +25103,24 @@ module mkPLIC_16_2_7(CLK, begin if (m_cfg_verbosity$EN) m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN; + if (m_slave_xactor_clearing$EN) + m_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_clearing$D_IN; + if (m_slave_xactor_shim_arff_rv$EN) + m_slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_shim_arff_rv$D_IN; + if (m_slave_xactor_shim_awff_rv$EN) + m_slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_shim_awff_rv$D_IN; + if (m_slave_xactor_shim_bff_rv$EN) + m_slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_shim_bff_rv$D_IN; + if (m_slave_xactor_shim_rff_rv$EN) + m_slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_shim_rff_rv$D_IN; + if (m_slave_xactor_shim_wff_rv$EN) + m_slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY + m_slave_xactor_shim_wff_rv$D_IN; if (m_vrg_servicing_source_0$EN) m_vrg_servicing_source_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_servicing_source_0$D_IN; @@ -24983,6 +25352,12 @@ module mkPLIC_16_2_7(CLK, m_cfg_verbosity = 4'hA; m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA; m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA; + m_slave_xactor_clearing = 1'h0; + m_slave_xactor_shim_arff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_awff_rv = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_bff_rv = 8'hAA; + m_slave_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA; + m_slave_xactor_shim_wff_rv = 74'h2AAAAAAAAAAAAAAAAAA; m_vrg_servicing_source_0 = 5'h0A; m_vrg_servicing_source_1 = 5'h0A; m_vrg_source_busy_0 = 1'h0; @@ -25234,9 +25609,9 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h71297, + a__h74356, m_vrg_target_threshold_0, - b__h71298, + b__h74357, m_vrg_servicing_source_0); if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1)); @@ -25277,1674 +25652,1955 @@ module mkPLIC_16_2_7(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display(" MaxPri %0d, Thresh %0d, MaxId %0d, Svcing %0d", - a__h73302, + a__h76361, m_vrg_target_threshold_1, - b__h73303, + b__h76362, m_vrg_servicing_source_1); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240) + if (NOT_m_vrg_source_busy_1_013_363_AND_NOT_m_cfg__ETC___d3367) begin - v__h75659 = $stime; + v__h78778 = $stime; #0; end - v__h75653 = v__h75659 / 32'd10; + v__h78772 = v__h78778 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_1_901_236_AND_NOT_m_cfg__ETC___d3240) + if (NOT_m_vrg_source_busy_1_013_363_AND_NOT_m_cfg__ETC___d3367) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75653, + v__h78772, $signed(32'd1), v_sources_0_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247) + if (NOT_m_vrg_source_busy_2_014_370_AND_NOT_m_cfg__ETC___d3374) begin - v__h75857 = $stime; + v__h78976 = $stime; #0; end - v__h75851 = v__h75857 / 32'd10; + v__h78970 = v__h78976 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_2_902_243_AND_NOT_m_cfg__ETC___d3247) + if (NOT_m_vrg_source_busy_2_014_370_AND_NOT_m_cfg__ETC___d3374) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h75851, + v__h78970, $signed(32'd2), v_sources_1_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255) + if (NOT_m_vrg_source_busy_3_015_378_AND_NOT_m_cfg__ETC___d3382) begin - v__h76055 = $stime; + v__h79174 = $stime; #0; end - v__h76049 = v__h76055 / 32'd10; + v__h79168 = v__h79174 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_3_903_251_AND_NOT_m_cfg__ETC___d3255) + if (NOT_m_vrg_source_busy_3_015_378_AND_NOT_m_cfg__ETC___d3382) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76049, + v__h79168, $signed(32'd3), v_sources_2_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263) + if (NOT_m_vrg_source_busy_4_016_386_AND_NOT_m_cfg__ETC___d3390) begin - v__h76253 = $stime; + v__h79372 = $stime; #0; end - v__h76247 = v__h76253 / 32'd10; + v__h79366 = v__h79372 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_4_904_259_AND_NOT_m_cfg__ETC___d3263) + if (NOT_m_vrg_source_busy_4_016_386_AND_NOT_m_cfg__ETC___d3390) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76247, + v__h79366, $signed(32'd4), v_sources_3_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271) + if (NOT_m_vrg_source_busy_5_017_394_AND_NOT_m_cfg__ETC___d3398) begin - v__h76451 = $stime; + v__h79570 = $stime; #0; end - v__h76445 = v__h76451 / 32'd10; + v__h79564 = v__h79570 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_5_905_267_AND_NOT_m_cfg__ETC___d3271) + if (NOT_m_vrg_source_busy_5_017_394_AND_NOT_m_cfg__ETC___d3398) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76445, + v__h79564, $signed(32'd5), v_sources_4_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279) + if (NOT_m_vrg_source_busy_6_018_402_AND_NOT_m_cfg__ETC___d3406) begin - v__h76649 = $stime; + v__h79768 = $stime; #0; end - v__h76643 = v__h76649 / 32'd10; + v__h79762 = v__h79768 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_6_906_275_AND_NOT_m_cfg__ETC___d3279) + if (NOT_m_vrg_source_busy_6_018_402_AND_NOT_m_cfg__ETC___d3406) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76643, + v__h79762, $signed(32'd6), v_sources_5_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287) + if (NOT_m_vrg_source_busy_7_019_410_AND_NOT_m_cfg__ETC___d3414) begin - v__h76847 = $stime; + v__h79966 = $stime; #0; end - v__h76841 = v__h76847 / 32'd10; + v__h79960 = v__h79966 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_7_907_283_AND_NOT_m_cfg__ETC___d3287) + if (NOT_m_vrg_source_busy_7_019_410_AND_NOT_m_cfg__ETC___d3414) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h76841, + v__h79960, $signed(32'd7), v_sources_6_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295) + if (NOT_m_vrg_source_busy_8_020_418_AND_NOT_m_cfg__ETC___d3422) begin - v__h77045 = $stime; + v__h80164 = $stime; #0; end - v__h77039 = v__h77045 / 32'd10; + v__h80158 = v__h80164 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_8_908_291_AND_NOT_m_cfg__ETC___d3295) + if (NOT_m_vrg_source_busy_8_020_418_AND_NOT_m_cfg__ETC___d3422) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77039, + v__h80158, $signed(32'd8), v_sources_7_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303) + if (NOT_m_vrg_source_busy_9_021_426_AND_NOT_m_cfg__ETC___d3430) begin - v__h77243 = $stime; + v__h80362 = $stime; #0; end - v__h77237 = v__h77243 / 32'd10; + v__h80356 = v__h80362 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_9_909_299_AND_NOT_m_cfg__ETC___d3303) + if (NOT_m_vrg_source_busy_9_021_426_AND_NOT_m_cfg__ETC___d3430) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77237, + v__h80356, $signed(32'd9), v_sources_8_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311) + if (NOT_m_vrg_source_busy_10_022_434_AND_NOT_m_cfg_ETC___d3438) begin - v__h77441 = $stime; + v__h80560 = $stime; #0; end - v__h77435 = v__h77441 / 32'd10; + v__h80554 = v__h80560 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_10_910_307_AND_NOT_m_cfg_ETC___d3311) + if (NOT_m_vrg_source_busy_10_022_434_AND_NOT_m_cfg_ETC___d3438) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77435, + v__h80554, $signed(32'd10), v_sources_9_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319) + if (NOT_m_vrg_source_busy_11_023_442_AND_NOT_m_cfg_ETC___d3446) begin - v__h77639 = $stime; + v__h80758 = $stime; #0; end - v__h77633 = v__h77639 / 32'd10; + v__h80752 = v__h80758 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_11_911_315_AND_NOT_m_cfg_ETC___d3319) + if (NOT_m_vrg_source_busy_11_023_442_AND_NOT_m_cfg_ETC___d3446) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77633, + v__h80752, $signed(32'd11), v_sources_10_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327) + if (NOT_m_vrg_source_busy_12_024_450_AND_NOT_m_cfg_ETC___d3454) begin - v__h77837 = $stime; + v__h80956 = $stime; #0; end - v__h77831 = v__h77837 / 32'd10; + v__h80950 = v__h80956 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_12_912_323_AND_NOT_m_cfg_ETC___d3327) + if (NOT_m_vrg_source_busy_12_024_450_AND_NOT_m_cfg_ETC___d3454) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h77831, + v__h80950, $signed(32'd12), v_sources_11_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335) + if (NOT_m_vrg_source_busy_13_025_458_AND_NOT_m_cfg_ETC___d3462) begin - v__h78035 = $stime; + v__h81154 = $stime; #0; end - v__h78029 = v__h78035 / 32'd10; + v__h81148 = v__h81154 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_13_913_331_AND_NOT_m_cfg_ETC___d3335) + if (NOT_m_vrg_source_busy_13_025_458_AND_NOT_m_cfg_ETC___d3462) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78029, + v__h81148, $signed(32'd13), v_sources_12_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343) + if (NOT_m_vrg_source_busy_14_026_466_AND_NOT_m_cfg_ETC___d3470) begin - v__h78233 = $stime; + v__h81352 = $stime; #0; end - v__h78227 = v__h78233 / 32'd10; + v__h81346 = v__h81352 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_14_914_339_AND_NOT_m_cfg_ETC___d3343) + if (NOT_m_vrg_source_busy_14_026_466_AND_NOT_m_cfg_ETC___d3470) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78227, + v__h81346, $signed(32'd14), v_sources_13_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351) + if (NOT_m_vrg_source_busy_15_027_474_AND_NOT_m_cfg_ETC___d3478) begin - v__h78431 = $stime; + v__h81550 = $stime; #0; end - v__h78425 = v__h78431 / 32'd10; + v__h81544 = v__h81550 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_15_915_347_AND_NOT_m_cfg_ETC___d3351) + if (NOT_m_vrg_source_busy_15_027_474_AND_NOT_m_cfg_ETC___d3478) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78425, + v__h81544, $signed(32'd15), v_sources_14_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359) + if (NOT_m_vrg_source_busy_16_028_482_AND_NOT_m_cfg_ETC___d3486) begin - v__h78629 = $stime; + v__h81748 = $stime; #0; end - v__h78623 = v__h78629 / 32'd10; + v__h81742 = v__h81748 / 32'd10; if (RST_N != `BSV_RESET_VALUE) - if (NOT_m_vrg_source_busy_16_916_355_AND_NOT_m_cfg_ETC___d3359) + if (NOT_m_vrg_source_busy_16_028_482_AND_NOT_m_cfg_ETC___d3486) $display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d", - v__h78623, + v__h81742, $signed(32'd16), v_sources_15_m_interrupt_req_set_not_clear); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) begin - v__h6142 = $stime; + v__h8559 = $stime; #0; end - v__h6136 = v__h6142 / 32'd10; + v__h8553 = v__h8559 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0) - $display("%0d: PLIC.rl_reset", v__h6136); + $display("%0d: PLIC.rl_reset", v__h8553); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_aw_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_w_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_ar_warnDoPut) + $display("WARNING: putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) begin - v__h13078 = $stime; + v__h15481 = $stime; #0; end - v__h13072 = v__h13078 / 32'd10; + v__h15475 = v__h15481 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req:", v__h13072); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $display("%0d: PLIC.rl_process_rd_req:", v__h15475); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) begin - v__h13263 = $stime; + v__h15696 = $stime; #0; end - v__h13257 = v__h13263 / 32'd10; + v__h15690 = v__h15696 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h13257); + v__h15690); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("AXI4_Rd_Addr { ", "arid: "); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31) + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d112) begin - v__h13461 = $stime; + v__h15924 = $stime; #0; end - v__h13455 = v__h13461 / 32'd10; + v__h15918 = v__h15924 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d112) $display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h", - v__h13455, - addr_offset__h13214[11:2], - v__h13420); + v__h15918, + addr_offset__h15646[11:2], + v__h15883); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d143) begin - v__h13711 = $stime; + v__h16175 = $stime; #0; end - v__h13705 = v__h13711 / 32'd10; + v__h16169 = v__h16175 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d143) $display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h", - v__h13705, - source_id_base__h13628, - v__h13669); + v__h16169, + source_id_base__h16091, + v__h16133); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d317) begin - v__h18184 = $stime; + v__h20649 = $stime; #0; end - v__h18178 = v__h18184 / 32'd10; + v__h20643 = v__h20649 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d317) $display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h", - v__h18178, - source_id_base__h13628, - v__h18142); + v__h20643, + source_id_base__h16091, + v__h20607); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d607) begin - v__h23800 = $stime; + v__h26266 = $stime; #0; end - v__h23794 = v__h23800 / 32'd10; + v__h26260 = v__h26266 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d607) $display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h", - v__h23794, - addr_offset__h13214[16:12], - v__h23759); + v__h26260, + addr_offset__h15646[16:12], + v__h26225); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d813) begin - v__h25973 = $stime; + v__h28442 = $stime; #0; end - v__h25967 = v__h25973 / 32'd10; + v__h28436 = v__h28442 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 && - !m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d744) + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d105 && + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d813) $display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h", - v__h25967, - addr_offset__h13214[16:12], - v__h25472); + v__h28436, + addr_offset__h15646[16:12], + v__h27941); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825) begin - v__h24054 = $stime; + v__h26522 = $stime; #0; end - v__h24048 = v__h24054 / 32'd10; + v__h26516 = v__h26522 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825) $display("%0d: ERROR: PLIC: target %0d claiming without prior completion", - v__h24048, - addr_offset__h13214[16:12]); + v__h26516, + addr_offset__h15646[16:12]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) - $display(" Still servicing interrupt from source %0d", x__h24009); + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825) + $display(" Still servicing interrupt from source %0d", x__h26477); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825) $display(" Trying to claim service for source %0d", - max_id__h23957); + max_id__h26424); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d756) + NOT_m_slave_xactor_shim_arff_rv_port1__read__4_ETC___d825) $display(" Ignoring."); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) begin - v__h26248 = $stime; + v__h28733 = $stime; #0; end - v__h26242 = v__h26248 / 32'd10; + v__h28727 = v__h28733 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr", - v__h26242); + v__h28727); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("AXI4_Rd_Addr { ", "arid: "); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + !m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - (m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 || - IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d771)) + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) begin - v__h26461 = $stime; + v__h29034 = $stime; #0; end - v__h26455 = v__h26461 / 32'd10; + v__h29028 = v__h29034 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_rd_req", v__h26455); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $display("%0d: PLIC.rl_process_rd_req", v__h29028); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Addr { ", "arid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_arff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_arff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Rd_Data { ", "rid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_arff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", x__h26359); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", x__h28872); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", rresp__h26201); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d891) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 && + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) + $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d840) && + (m_slave_xactor_shim_arff_rv_port1__read__4_BIT_ETC___d94 || + IF_m_slave_xactor_shim_arff_rv_port1__read__4__ETC___d891)) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_rd_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_rd_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) begin - v__h26735 = $stime; + v__h29518 = $stime; #0; end - v__h26729 = v__h26735 / 32'd10; + v__h29512 = v__h29518 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.rl_process_wr_req", v__h26729); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $display("%0d: PLIC.rl_process_wr_req", v__h29512); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wdata: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) begin - v__h26959 = $stime; + v__h29772 = $stime; #0; end - v__h26953 = v__h26959 / 32'd10; + v__h29766 = v__h29772 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h26953); + v__h29766); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("AXI4_Wr_Addr { ", "awid: "); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("AXI4_Wr_Data { ", "wdata: "); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_data$D_OUT[0]) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - !m_slave_xactor_f_wr_data$D_OUT[0]) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + !m_slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837) + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1006) begin - v__h27854 = $stime; + v__h30696 = $stime; #0; end - v__h27848 = v__h27854 / 32'd10; + v__h30690 = v__h30696 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d894) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d1006) $display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h", - v__h27848, - addr_offset__h26920[11:2], - wdata32__h26921); + v__h30690, + addr_offset__h29732[11:2], + wdata32__h29733); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1017) begin - v__h28037 = $stime; + v__h30882 = $stime; #0; end - v__h28031 = v__h28037 / 32'd10; + v__h30876 = v__h30882 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d905) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d1017) $display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d", - v__h28031, - source_id_base__h28137); + v__h30876, + source_id_base__h30983); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2981) begin - v__h67019 = $stime; + v__h69866 = $stime; #0; end - v__h67013 = v__h67019 / 32'd10; + v__h69860 = v__h69866 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2869) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d2981) $display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h", - v__h67013, - addr_offset__h26920[11:7], - source_id_base__h28137, - wdata32__h26921); + v__h69860, + addr_offset__h29732[11:7], + source_id_base__h30983, + wdata32__h29733); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3005) begin - v__h67307 = $stime; + v__h70156 = $stime; #0; end - v__h67301 = v__h67307 / 32'd10; + v__h70150 = v__h70156 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2893) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3005) $display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h", - v__h67301, - addr_offset__h26920[16:12], - wdata32__h26921); + v__h70150, + addr_offset__h29732[16:12], + wdata32__h29733); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3077) begin - v__h67836 = $stime; + v__h70688 = $stime; #0; end - v__h67830 = v__h67836 / 32'd10; + v__h70682 = v__h70688 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - !m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2965) + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3077) $display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h", - v__h67830, - addr_offset__h26920[16:12], - source_id__h67425); + v__h70682, + addr_offset__h29732[16:12], + source_id__h70276); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087) begin - v__h67922 = $stime; + v__h70774 = $stime; #0; end - v__h67916 = v__h67922 / 32'd10; + v__h70768 = v__h70774 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087) $display("%0d: ERROR: PLIC: interrupt completion to source that is not being serviced", - v__h67916); + v__h70768); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087) $display(" Completion message from target %0d to source %0d", - addr_offset__h26920[16:12], - source_id__h67425); + addr_offset__h29732[16:12], + source_id__h70276); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_slave_xactor_f_wr_addr_first__19_BITS_92_ETC___d2975) + NOT_m_slave_xactor_shim_awff_rv_port1__read__9_ETC___d3087) $display(" Ignoring"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) begin - v__h68121 = $stime; + v__h70985 = $stime; #0; end - v__h68115 = v__h68121 / 32'd10; + v__h70979 = v__h70985 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr", - v__h68115); + v__h70979); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("AXI4_Wr_Addr { ", "awid: "); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("AXI4_Size { ", "val: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[20:18], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + !m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("AXI4_Wr_Data { ", "wdata: "); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && - m_slave_xactor_f_wr_data$D_OUT[0]) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + m_slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990) && - !m_slave_xactor_f_wr_data$D_OUT[0]) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + !m_slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - (m_slave_xactor_f_wr_addr_first__19_BITS_92_TO__ETC___d837 || - IF_m_slave_xactor_f_wr_addr_first__19_BITS_92__ETC___d2990)) + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102)) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) begin - v__h68340 = $stime; + v__h71294 = $stime; #0; end - v__h68334 = v__h68340 / 32'd10; + v__h71288 = v__h71294 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h68334); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $display("%0d: PLIC.AXI4.rl_process_wr_req", v__h71288); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Addr { ", "awid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[92:29]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[28:21]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[20:18], " }"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd0) + $write("FIXED"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd1) + $write("INCR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] == 2'd2) + $write("WRAP"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd0 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd1 && + m_slave_xactor_shim_awff_rv$port1__read[17:16] != 2'd2) + $write("Res"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("EXCLUSIVE"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_awff_rv$port1__read[15]) + $write("NORMAL"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[14:11]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[10:8]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[7:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[3:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Data { ", "wdata: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_WFlit { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[72:9]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_wff_rv$port1__read[8:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - m_slave_xactor_f_wr_data$D_OUT[0]) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + m_slave_xactor_shim_wff_rv$port1__read[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16 && - !m_slave_xactor_f_wr_data$D_OUT[0]) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_wff_rv$port1__read[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("AXI4_Wr_Resp { ", "bid: "); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("AXI4_BFlit { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[96:93]); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) + $write("'h%h", m_slave_xactor_shim_awff_rv$port1__read[97:93]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) - $write("'h%h", v__h26925); + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3132) + $write("OKAY"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + !m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 && + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) + $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65 && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3102) && + (m_slave_xactor_shim_awff_rv_port1__read__99_BI_ETC___d943 || + IF_m_slave_xactor_shim_awff_rv_port1__read__99_ETC___d3132)) + $write("DECERR"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_rl_process_wr_req && + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_m_rl_process_wr_req && - NOT_m_cfg_verbosity_read_ULE_1_5___d16) + NOT_m_cfg_verbosity_read__9_ULE_1_4___d65) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) begin - v__h74675 = $stime; + v__h77734 = $stime; #0; end - v__h74669 = v__h74675 / 32'd10; + v__h77728 = v__h77734 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned", - v__h74669, + v__h77728, set_addr_map_addr_base); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) begin - v__h74785 = $stime; + v__h77844 = $stime; #0; end - v__h74779 = v__h74785 / 32'd10; + v__h77838 = v__h77844 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0) $display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned", - v__h74779, + v__h77838, set_addr_map_addr_lim); if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) begin - v__h74898 = $stime; + v__h77957 = $stime; #0; end - v__h74892 = v__h74898 / 32'd10; + v__h77951 = v__h77957 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_set_addr_map && m_cfg_verbosity != 4'd0) $display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h", - v__h74892, + v__h77951, set_addr_map_addr_base, set_addr_map_addr_lim); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_b_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_m_slave_xactor_ug_slave_u_r_warnDoDrop) + $display("WARNING: dropping from Source that can't be dropped from"); end // synopsys translate_on endmodule // mkPLIC_16_2_7 diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkRISCV_MBox.v b/src_SSITH_P1/xilinx_ip/hdl/mkRISCV_MBox.v index 570d9b06..89427fb9 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkRISCV_MBox.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkRISCV_MBox.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:40 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkSoC_Map.v b/src_SSITH_P1/xilinx_ip/hdl/mkSoC_Map.v index a1384976..fad8016c 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkSoC_Map.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkSoC_Map.v @@ -1,41 +1,21 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:19 BST 2019 // // // Ports: // Name I/O size props -// m_plic_addr_base O 64 const -// m_plic_addr_size O 64 const -// m_plic_addr_lim O 64 const -// m_near_mem_io_addr_base O 64 const -// m_near_mem_io_addr_size O 64 const -// m_near_mem_io_addr_lim O 64 const -// m_flash_mem_addr_base O 64 const -// m_flash_mem_addr_size O 64 const -// m_flash_mem_addr_lim O 64 const -// m_ethernet_0_addr_base O 64 const -// m_ethernet_0_addr_size O 64 const -// m_ethernet_0_addr_lim O 64 const -// m_dma_0_addr_base O 64 const -// m_dma_0_addr_size O 64 const -// m_dma_0_addr_lim O 64 const -// m_uart16550_0_addr_base O 64 const -// m_uart16550_0_addr_size O 64 const -// m_uart16550_0_addr_lim O 64 const -// m_gpio_0_addr_base O 64 const -// m_gpio_0_addr_size O 64 const -// m_gpio_0_addr_lim O 64 const -// m_boot_rom_addr_base O 64 const -// m_boot_rom_addr_size O 64 const -// m_boot_rom_addr_lim O 64 const -// m_ddr4_0_uncached_addr_base O 64 const -// m_ddr4_0_uncached_addr_size O 64 const -// m_ddr4_0_uncached_addr_lim O 64 const -// m_ddr4_0_cached_addr_base O 64 const -// m_ddr4_0_cached_addr_size O 64 const -// m_ddr4_0_cached_addr_lim O 64 const +// m_plic_addr_range O 128 const +// m_near_mem_io_addr_range O 128 const +// m_flash_mem_addr_range O 128 const +// m_ethernet_0_addr_range O 128 const +// m_dma_0_addr_range O 128 const +// m_uart16550_0_addr_range O 128 const +// m_gpio_0_addr_range O 128 const +// m_boot_rom_addr_range O 128 const +// m_ddr4_0_uncached_addr_range O 128 const +// m_ddr4_0_cached_addr_range O 128 const // m_is_mem_addr O 1 // m_is_IO_addr O 1 // m_is_near_mem_IO_addr O 1 @@ -71,65 +51,25 @@ module mkSoC_Map(CLK, RST_N, - m_plic_addr_base, - - m_plic_addr_size, - - m_plic_addr_lim, - - m_near_mem_io_addr_base, - - m_near_mem_io_addr_size, - - m_near_mem_io_addr_lim, - - m_flash_mem_addr_base, - - m_flash_mem_addr_size, - - m_flash_mem_addr_lim, - - m_ethernet_0_addr_base, - - m_ethernet_0_addr_size, - - m_ethernet_0_addr_lim, - - m_dma_0_addr_base, - - m_dma_0_addr_size, - - m_dma_0_addr_lim, - - m_uart16550_0_addr_base, + m_plic_addr_range, - m_uart16550_0_addr_size, + m_near_mem_io_addr_range, - m_uart16550_0_addr_lim, + m_flash_mem_addr_range, - m_gpio_0_addr_base, + m_ethernet_0_addr_range, - m_gpio_0_addr_size, + m_dma_0_addr_range, - m_gpio_0_addr_lim, + m_uart16550_0_addr_range, - m_boot_rom_addr_base, + m_gpio_0_addr_range, - m_boot_rom_addr_size, + m_boot_rom_addr_range, - m_boot_rom_addr_lim, + m_ddr4_0_uncached_addr_range, - m_ddr4_0_uncached_addr_base, - - m_ddr4_0_uncached_addr_size, - - m_ddr4_0_uncached_addr_lim, - - m_ddr4_0_cached_addr_base, - - m_ddr4_0_cached_addr_size, - - m_ddr4_0_cached_addr_lim, + m_ddr4_0_cached_addr_range, m_is_mem_addr_addr, m_is_mem_addr, @@ -148,95 +88,35 @@ module mkSoC_Map(CLK, input CLK; input RST_N; - // value method m_plic_addr_base - output [63 : 0] m_plic_addr_base; - - // value method m_plic_addr_size - output [63 : 0] m_plic_addr_size; - - // value method m_plic_addr_lim - output [63 : 0] m_plic_addr_lim; - - // value method m_near_mem_io_addr_base - output [63 : 0] m_near_mem_io_addr_base; - - // value method m_near_mem_io_addr_size - output [63 : 0] m_near_mem_io_addr_size; - - // value method m_near_mem_io_addr_lim - output [63 : 0] m_near_mem_io_addr_lim; - - // value method m_flash_mem_addr_base - output [63 : 0] m_flash_mem_addr_base; - - // value method m_flash_mem_addr_size - output [63 : 0] m_flash_mem_addr_size; - - // value method m_flash_mem_addr_lim - output [63 : 0] m_flash_mem_addr_lim; - - // value method m_ethernet_0_addr_base - output [63 : 0] m_ethernet_0_addr_base; - - // value method m_ethernet_0_addr_size - output [63 : 0] m_ethernet_0_addr_size; + // value method m_plic_addr_range + output [127 : 0] m_plic_addr_range; - // value method m_ethernet_0_addr_lim - output [63 : 0] m_ethernet_0_addr_lim; + // value method m_near_mem_io_addr_range + output [127 : 0] m_near_mem_io_addr_range; - // value method m_dma_0_addr_base - output [63 : 0] m_dma_0_addr_base; + // value method m_flash_mem_addr_range + output [127 : 0] m_flash_mem_addr_range; - // value method m_dma_0_addr_size - output [63 : 0] m_dma_0_addr_size; + // value method m_ethernet_0_addr_range + output [127 : 0] m_ethernet_0_addr_range; - // value method m_dma_0_addr_lim - output [63 : 0] m_dma_0_addr_lim; + // value method m_dma_0_addr_range + output [127 : 0] m_dma_0_addr_range; - // value method m_uart16550_0_addr_base - output [63 : 0] m_uart16550_0_addr_base; + // value method m_uart16550_0_addr_range + output [127 : 0] m_uart16550_0_addr_range; - // value method m_uart16550_0_addr_size - output [63 : 0] m_uart16550_0_addr_size; + // value method m_gpio_0_addr_range + output [127 : 0] m_gpio_0_addr_range; - // value method m_uart16550_0_addr_lim - output [63 : 0] m_uart16550_0_addr_lim; + // value method m_boot_rom_addr_range + output [127 : 0] m_boot_rom_addr_range; - // value method m_gpio_0_addr_base - output [63 : 0] m_gpio_0_addr_base; + // value method m_ddr4_0_uncached_addr_range + output [127 : 0] m_ddr4_0_uncached_addr_range; - // value method m_gpio_0_addr_size - output [63 : 0] m_gpio_0_addr_size; - - // value method m_gpio_0_addr_lim - output [63 : 0] m_gpio_0_addr_lim; - - // value method m_boot_rom_addr_base - output [63 : 0] m_boot_rom_addr_base; - - // value method m_boot_rom_addr_size - output [63 : 0] m_boot_rom_addr_size; - - // value method m_boot_rom_addr_lim - output [63 : 0] m_boot_rom_addr_lim; - - // value method m_ddr4_0_uncached_addr_base - output [63 : 0] m_ddr4_0_uncached_addr_base; - - // value method m_ddr4_0_uncached_addr_size - output [63 : 0] m_ddr4_0_uncached_addr_size; - - // value method m_ddr4_0_uncached_addr_lim - output [63 : 0] m_ddr4_0_uncached_addr_lim; - - // value method m_ddr4_0_cached_addr_base - output [63 : 0] m_ddr4_0_cached_addr_base; - - // value method m_ddr4_0_cached_addr_size - output [63 : 0] m_ddr4_0_cached_addr_size; - - // value method m_ddr4_0_cached_addr_lim - output [63 : 0] m_ddr4_0_cached_addr_lim; + // value method m_ddr4_0_cached_addr_range + output [127 : 0] m_ddr4_0_cached_addr_range; // value method m_is_mem_addr input [63 : 0] m_is_mem_addr_addr; @@ -260,133 +140,52 @@ module mkSoC_Map(CLK, output [63 : 0] m_nmivec_reset_value; // signals for module outputs - wire [63 : 0] m_boot_rom_addr_base, - m_boot_rom_addr_lim, - m_boot_rom_addr_size, - m_ddr4_0_cached_addr_base, - m_ddr4_0_cached_addr_lim, - m_ddr4_0_cached_addr_size, - m_ddr4_0_uncached_addr_base, - m_ddr4_0_uncached_addr_lim, - m_ddr4_0_uncached_addr_size, - m_dma_0_addr_base, - m_dma_0_addr_lim, - m_dma_0_addr_size, - m_ethernet_0_addr_base, - m_ethernet_0_addr_lim, - m_ethernet_0_addr_size, - m_flash_mem_addr_base, - m_flash_mem_addr_lim, - m_flash_mem_addr_size, - m_gpio_0_addr_base, - m_gpio_0_addr_lim, - m_gpio_0_addr_size, - m_mtvec_reset_value, - m_near_mem_io_addr_base, - m_near_mem_io_addr_lim, - m_near_mem_io_addr_size, - m_nmivec_reset_value, - m_pc_reset_value, - m_plic_addr_base, - m_plic_addr_lim, - m_plic_addr_size, - m_uart16550_0_addr_base, - m_uart16550_0_addr_lim, - m_uart16550_0_addr_size; + wire [127 : 0] m_boot_rom_addr_range, + m_ddr4_0_cached_addr_range, + m_ddr4_0_uncached_addr_range, + m_dma_0_addr_range, + m_ethernet_0_addr_range, + m_flash_mem_addr_range, + m_gpio_0_addr_range, + m_near_mem_io_addr_range, + m_plic_addr_range, + m_uart16550_0_addr_range; + wire [63 : 0] m_mtvec_reset_value, m_nmivec_reset_value, m_pc_reset_value; wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr; // remaining internal signals wire m_is_IO_addr_addr_ULT_0x70000000___d35; - // value method m_plic_addr_base - assign m_plic_addr_base = 64'h000000000C000000 ; - - // value method m_plic_addr_size - assign m_plic_addr_size = 64'h0000000000400000 ; - - // value method m_plic_addr_lim - assign m_plic_addr_lim = 64'd205520896 ; - - // value method m_near_mem_io_addr_base - assign m_near_mem_io_addr_base = 64'h0000000010000000 ; - - // value method m_near_mem_io_addr_size - assign m_near_mem_io_addr_size = 64'h0000000000010000 ; - - // value method m_near_mem_io_addr_lim - assign m_near_mem_io_addr_lim = 64'd268500992 ; - - // value method m_flash_mem_addr_base - assign m_flash_mem_addr_base = 64'h0000000040000000 ; - - // value method m_flash_mem_addr_size - assign m_flash_mem_addr_size = 64'h0000000008000000 ; - - // value method m_flash_mem_addr_lim - assign m_flash_mem_addr_lim = 64'd1207959552 ; - - // value method m_ethernet_0_addr_base - assign m_ethernet_0_addr_base = 64'h0000000062100000 ; - - // value method m_ethernet_0_addr_size - assign m_ethernet_0_addr_size = 64'h0000000000040000 ; - - // value method m_ethernet_0_addr_lim - assign m_ethernet_0_addr_lim = 64'd1645477888 ; - - // value method m_dma_0_addr_base - assign m_dma_0_addr_base = 64'h0000000062200000 ; - - // value method m_dma_0_addr_size - assign m_dma_0_addr_size = 64'h0000000000010000 ; - - // value method m_dma_0_addr_lim - assign m_dma_0_addr_lim = 64'd1646329856 ; - - // value method m_uart16550_0_addr_base - assign m_uart16550_0_addr_base = 64'h0000000062300000 ; - - // value method m_uart16550_0_addr_size - assign m_uart16550_0_addr_size = 64'h0000000000001000 ; - - // value method m_uart16550_0_addr_lim - assign m_uart16550_0_addr_lim = 64'd1647316992 ; - - // value method m_gpio_0_addr_base - assign m_gpio_0_addr_base = 64'h000000006FFF0000 ; - - // value method m_gpio_0_addr_size - assign m_gpio_0_addr_size = 64'h0000000000010000 ; - - // value method m_gpio_0_addr_lim - assign m_gpio_0_addr_lim = 64'd1879048192 ; + // value method m_plic_addr_range + assign m_plic_addr_range = 128'h000000000C0000000000000000400000 ; - // value method m_boot_rom_addr_base - assign m_boot_rom_addr_base = 64'h0000000070000000 ; + // value method m_near_mem_io_addr_range + assign m_near_mem_io_addr_range = 128'h00000000100000000000000000010000 ; - // value method m_boot_rom_addr_size - assign m_boot_rom_addr_size = 64'h0000000000001000 ; + // value method m_flash_mem_addr_range + assign m_flash_mem_addr_range = 128'h00000000400000000000000008000000 ; - // value method m_boot_rom_addr_lim - assign m_boot_rom_addr_lim = 64'd1879052288 ; + // value method m_ethernet_0_addr_range + assign m_ethernet_0_addr_range = 128'h00000000621000000000000000040000 ; - // value method m_ddr4_0_uncached_addr_base - assign m_ddr4_0_uncached_addr_base = 64'h0000000080000000 ; + // value method m_dma_0_addr_range + assign m_dma_0_addr_range = 128'h00000000622000000000000000010000 ; - // value method m_ddr4_0_uncached_addr_size - assign m_ddr4_0_uncached_addr_size = 64'h0000000040000000 ; + // value method m_uart16550_0_addr_range + assign m_uart16550_0_addr_range = 128'h00000000623000000000000000001000 ; - // value method m_ddr4_0_uncached_addr_lim - assign m_ddr4_0_uncached_addr_lim = 64'h00000000C0000000 ; + // value method m_gpio_0_addr_range + assign m_gpio_0_addr_range = 128'h000000006FFF00000000000000010000 ; - // value method m_ddr4_0_cached_addr_base - assign m_ddr4_0_cached_addr_base = 64'h00000000C0000000 ; + // value method m_boot_rom_addr_range + assign m_boot_rom_addr_range = 128'h00000000700000000000000000001000 ; - // value method m_ddr4_0_cached_addr_size - assign m_ddr4_0_cached_addr_size = 64'h0000000040000000 ; + // value method m_ddr4_0_uncached_addr_range + assign m_ddr4_0_uncached_addr_range = + 128'h00000000800000000000000040000000 ; - // value method m_ddr4_0_cached_addr_lim - assign m_ddr4_0_cached_addr_lim = 64'h0000000100000000 ; + // value method m_ddr4_0_cached_addr_range + assign m_ddr4_0_cached_addr_range = 128'h00000000C00000000000000040000000 ; // value method m_is_mem_addr assign m_is_mem_addr = diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkTV_Encode.v b/src_SSITH_P1/xilinx_ip/hdl/mkTV_Encode.v index 1371994a..786b6910 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkTV_Encode.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkTV_Encode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:18:11 BST 2019 // // // Ports: diff --git a/src_SSITH_P1/xilinx_ip/hdl/mkTV_Xactor.v b/src_SSITH_P1/xilinx_ip/hdl/mkTV_Xactor.v index 4ce5fb1c..4c550bcf 100644 --- a/src_SSITH_P1/xilinx_ip/hdl/mkTV_Xactor.v +++ b/src_SSITH_P1/xilinx_ip/hdl/mkTV_Xactor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17) // -// +// On Tue Jul 9 16:19:01 BST 2019 // // // Ports: diff --git a/src_Testbench/Fabrics/AXI4_Lite/AXI4_Lite_Fabric.bsv b/src_Testbench/Fabrics/AXI4_Lite/AXI4_Lite_Fabric.bsv deleted file mode 100644 index 13384be5..00000000 --- a/src_Testbench/Fabrics/AXI4_Lite/AXI4_Lite_Fabric.bsv +++ /dev/null @@ -1,322 +0,0 @@ -// Copyright (c) 2013-2019 Bluespec, Inc. All Rights Reserved - -package AXI4_Lite_Fabric; - -// ================================================================ -// This package defines a fabric connecting CPUs, Memories and DMAs -// and other IP blocks. - -// ================================================================ -// Bluespec library imports - -import Vector :: *; -import FIFOF :: *; -import SpecialFIFOs :: *; -import ConfigReg :: *; - -// ---------------- -// BSV additional libs - -import Cur_Cycle :: *; - -// ================================================================ -// Project imports - -import Semi_FIFOF :: *; -import AXI4_Lite_Types :: *; - -// ================================================================ -// The interface for the fabric module - -interface AXI4_Lite_Fabric_IFC #(numeric type num_masters, - numeric type num_slaves, - numeric type wd_addr, - numeric type wd_data, - numeric type wd_user); - method Action reset; - method Action set_verbosity (Bit #(4) verbosity); - - // From masters - interface Vector #(num_masters, AXI4_Lite_Slave_IFC #(wd_addr, wd_data, wd_user)) v_from_masters; - - // To slaves - interface Vector #(num_slaves, AXI4_Lite_Master_IFC #(wd_addr, wd_data, wd_user)) v_to_slaves; -endinterface - -// ================================================================ -// The Fabric module -// The function parameter is an address-decode function, which returns -// returns (True, slave-port-num) if address is mapped to slave-port-num -// (False, ?) if address is unmapped to any port - -module mkAXI4_Lite_Fabric #(function Tuple2 #(Bool, Bit #(TLog #(num_slaves))) - fn_addr_to_slave_num (Bit #(wd_addr) addr)) - (AXI4_Lite_Fabric_IFC #(num_masters, num_slaves, wd_addr, wd_data, wd_user)) - - provisos (Log #(num_masters, log_nm), - Log #(num_slaves, log_ns), - Log #(TAdd #(num_masters, 1), log_nm_plus_1), - Log #(TAdd #(num_slaves, 1), log_ns_plus_1), - Add #(_dummy, TLog #(num_slaves), log_ns_plus_1)); - - Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0); - - Reg #(Bool) rg_reset <- mkReg (True); - - // Transactors facing masters - Vector #(num_masters, AXI4_Lite_Slave_Xactor_IFC #(wd_addr, wd_data, wd_user)) - xactors_from_masters <- replicateM (mkAXI4_Lite_Slave_Xactor); - - // Transactors facing slaves - Vector #(num_slaves, AXI4_Lite_Master_Xactor_IFC #(wd_addr, wd_data, wd_user)) - xactors_to_slaves <- replicateM (mkAXI4_Lite_Master_Xactor); - - // FIFOs to keep track of which master originated a transaction, in - // order to route corresponding responses back to that master. - // Legal masters are 0..(num_masters-1) - // The value of 'num_masters' is used for decode errors (no such slave) - - Vector #(num_masters, FIFOF #(Bit #(log_ns_plus_1))) v_f_wr_sjs <- replicateM (mkSizedFIFOF (8)); - Vector #(num_masters, FIFOF #(Bit #(wd_user))) v_f_wr_err_user <- replicateM (mkSizedFIFOF (8)); - Vector #(num_slaves, FIFOF #(Bit #(log_nm_plus_1))) v_f_wr_mis <- replicateM (mkSizedFIFOF (8)); - - Vector #(num_masters, FIFOF #(Bit #(log_ns_plus_1))) v_f_rd_sjs <- replicateM (mkSizedFIFOF (8)); - Vector #(num_masters, FIFOF #(Bit #(wd_user))) v_f_rd_err_user <- replicateM (mkSizedFIFOF (8)); - Vector #(num_slaves, FIFOF #(Bit #(log_nm_plus_1))) v_f_rd_mis <- replicateM (mkSizedFIFOF (8)); - - // ---------------------------------------------------------------- - // BEHAVIOR - - rule rl_reset (rg_reset); - $display ("%0d: AXI4_Lite_Fabric.rl_reset", cur_cycle); - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) begin - xactors_from_masters [mi].reset; - - v_f_wr_sjs [mi].clear; - v_f_wr_err_user [mi].clear; - - v_f_rd_sjs [mi].clear; - v_f_rd_err_user [mi].clear; - end - - for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) begin - xactors_to_slaves [sj].reset; - v_f_wr_mis [sj].clear; - v_f_rd_mis [sj].clear; - end - rg_reset <= False; - endrule - - // ---------------------------------------------------------------- - // Help functions for moving data from masters to slaves - - Integer num_slaves_i = valueOf (num_slaves); - - function Bool wr_move_from_mi_to_sj (Integer mi, Integer sj); - let addr = xactors_from_masters [mi].o_wr_addr.first.awaddr; - match { .legal, .slave_num } = fn_addr_to_slave_num (addr); - return (legal - && ( (num_slaves_i == 1) - || (slave_num == fromInteger (sj)))); - endfunction - - function Bool wr_illegal_sj (Integer mi); - let addr = xactors_from_masters [mi].o_wr_addr.first.awaddr; - match { .legal, ._ } = fn_addr_to_slave_num (addr); - return (! legal); - endfunction - - function Bool rd_move_from_mi_to_sj (Integer mi, Integer sj); - let addr = xactors_from_masters [mi].o_rd_addr.first.araddr; - match { .legal, .slave_num } = fn_addr_to_slave_num (addr); - return (legal - && ( (num_slaves_i == 1) - || (slave_num == fromInteger (sj)))); - endfunction - - function Bool rd_illegal_sj (Integer mi); - let addr = xactors_from_masters [mi].o_rd_addr.first.araddr; - match { .legal, ._ } = fn_addr_to_slave_num (addr); - return (! legal); - endfunction - - // ---------------- - // Wr requests from masters to slaves - - // Legal destination slaves - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) - - rule rl_wr_xaction_master_to_slave (wr_move_from_mi_to_sj (mi, sj)); - AXI4_Lite_Wr_Addr #(wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_wr_addr); - AXI4_Lite_Wr_Data #(wd_data) d <- pop_o (xactors_from_masters [mi].o_wr_data); - - xactors_to_slaves [sj].i_wr_addr.enq (a); - xactors_to_slaves [sj].i_wr_data.enq (d); - - v_f_wr_mis [sj].enq (fromInteger (mi)); - v_f_wr_sjs [mi].enq (fromInteger (sj)); - - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Lite_Fabric: wr master [%0d] -> slave [%0d]", cur_cycle, mi, sj); - $display (" ", fshow (a)); - $display (" ", fshow (d)); - end - endrule - - // Non-existent destination slaves - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - rule rl_wr_xaction_no_such_slave (wr_illegal_sj (mi)); - AXI4_Lite_Wr_Addr #(wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_wr_addr); - AXI4_Lite_Wr_Data #(wd_data) d <- pop_o (xactors_from_masters [mi].o_wr_data); - - v_f_wr_sjs [mi].enq (fromInteger (valueOf (num_slaves))); - v_f_wr_err_user [mi].enq (a.awuser); - - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Lite_Fabric: wr master [%0d] -> illegal addr", cur_cycle, mi); - $display (" ", fshow (a)); - end - endrule - - // ---------------- - // Rd requests from masters to slaves - - // Legal destination slaves - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) - - rule rl_rd_xaction_master_to_slave (rd_move_from_mi_to_sj (mi, sj)); - AXI4_Lite_Rd_Addr #(wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_rd_addr); - - xactors_to_slaves [sj].i_rd_addr.enq (a); - - v_f_rd_mis [sj].enq (fromInteger (mi)); - v_f_rd_sjs [mi].enq (fromInteger (sj)); - - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Lite_Fabric: rd master [%0d] -> slave [%0d]", cur_cycle, mi, sj); - $display (" ", fshow (a)); - end - endrule - - // Non-existent destination slaves - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - rule rl_rd_xaction_no_such_slave (rd_illegal_sj (mi)); - AXI4_Lite_Rd_Addr #(wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_rd_addr); - - v_f_rd_sjs [mi].enq (fromInteger (valueOf (num_slaves))); - v_f_rd_err_user [mi].enq (a.aruser); - - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Lite_Fabric: rd master [%0d] -> illegal addr", cur_cycle, mi); - $display (" ", fshow (a)); - end - endrule - - // ---------------- - // Wr responses from slaves to masters - - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) - - rule rl_wr_resp_slave_to_master ( (v_f_wr_mis [sj].first == fromInteger (mi)) - && (v_f_wr_sjs [mi].first == fromInteger (sj))); - v_f_wr_mis [sj].deq; - v_f_wr_sjs [mi].deq; - AXI4_Lite_Wr_Resp #(wd_user) b <- pop_o (xactors_to_slaves [sj].o_wr_resp); - - xactors_from_masters [mi].i_wr_resp.enq (b); - - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Lite_Fabric: wr master [%0d] <- slave [%0d]", cur_cycle, mi, sj); - $display (" ", fshow (b)); - end - endrule - - // ---------------- - // Wr error responses to masters - // v_f_wr_sjs [mi].first has value num_slaves (illegal value) - // v_f_wr_err_user [mi].first contains the request's 'user' data - - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - - rule rl_wr_resp_err_to_master (v_f_wr_sjs [mi].first == fromInteger (valueOf (num_slaves))); - v_f_wr_sjs [mi].deq; - v_f_wr_err_user [mi].deq; - - let b = AXI4_Lite_Wr_Resp {bresp: AXI4_LITE_DECERR, buser: v_f_wr_err_user [mi].first}; - - xactors_from_masters [mi].i_wr_resp.enq (b); - - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Lite_Fabric: wr master [%0d] <- error", cur_cycle, mi); - $display (" ", fshow (b)); - end - endrule - - // ---------------- - // Rd responses from slaves to masters - - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) - - rule rl_rd_resp_slave_to_master ( (v_f_rd_mis [sj].first == fromInteger (mi)) - && (v_f_rd_sjs [mi].first == fromInteger (sj))); - v_f_rd_mis [sj].deq; - v_f_rd_sjs [mi].deq; - AXI4_Lite_Rd_Data #(wd_data, wd_user) r <- pop_o (xactors_to_slaves [sj].o_rd_data); - - xactors_from_masters [mi].i_rd_data.enq (r); - - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Lite_Fabric: rd master [%0d] <- slave [%0d]", cur_cycle, mi, sj); - $display (" ", fshow (r)); - end - endrule - - // ---------------- - // Rd error responses to masters - // v_f_rd_sjs [mi].first has value num_slaves (illegal value) - // v_f_rd_err_user [mi].first contains the request's 'user' data - - for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) - - rule rl_rd_resp_err_to_master (v_f_rd_sjs [mi].first == fromInteger (valueOf (num_slaves))); - v_f_rd_sjs [mi].deq; - v_f_rd_err_user [mi].deq; - - Bit #(wd_data) data = 0; - let r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_DECERR, ruser: v_f_rd_err_user [mi].first, rdata: data}; - - xactors_from_masters [mi].i_rd_data.enq (r); - - if (cfg_verbosity > 1) begin - $display ("%0d: AXI4_Lite_Fabric: rd master [%0d] <- error", cur_cycle, mi); - $display (" ", fshow (r)); - end - endrule - - // ---------------------------------------------------------------- - // INTERFACE - - function AXI4_Lite_Slave_IFC #(wd_addr, wd_data, wd_user) f1 (Integer j) - = xactors_from_masters [j].axi_side; - function AXI4_Lite_Master_IFC #(wd_addr, wd_data, wd_user) f2 (Integer j) - = xactors_to_slaves [j].axi_side; - - method Action reset () if (! rg_reset); - rg_reset <= True; - endmethod - - method Action set_verbosity (Bit #(4) verbosity); - cfg_verbosity <= verbosity; - endmethod - - interface v_from_masters = genWith (f1); - interface v_to_slaves = genWith (f2); -endmodule - -// ================================================================ - -endpackage: AXI4_Lite_Fabric diff --git a/src_Testbench/Fabrics/AXI4_Lite/AXI4_Lite_Types.bsv b/src_Testbench/Fabrics/AXI4_Lite/AXI4_Lite_Types.bsv deleted file mode 100644 index 13840625..00000000 --- a/src_Testbench/Fabrics/AXI4_Lite/AXI4_Lite_Types.bsv +++ /dev/null @@ -1,1020 +0,0 @@ -// Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved - -package AXI4_Lite_Types; - -// ================================================================ -// Facilities for ARM AXI4-Lite, consisting of 5 independent channels: -// Write Address, Write Data, Write Response, Read Address and Read Data - -// Ref: ARM document: -// AMBA AXI and ACE Protocol Specification -// AXI3, AXI4, and AXI4-Lite -// ACE and ACE-Lite -// ARM IHI 0022E (ID022613) -// Issue E, 22 Feb 2013 - -// See export list below - -// ================================================================ -// Exports - -export - -// RTL-level interfaces (signals/buses) -AXI4_Lite_Master_IFC (..), -AXI4_Lite_Slave_IFC (..), - -// Dummy master that generates no request and accepts no response. -// Used for tying-off unused master interfaces on fabrics. -dummy_AXI4_Lite_Master_ifc, - -// Dummy slave that accepts no request and generates no response. -// Used for tying-off unused slave interfaces on fabrics. -dummy_AXI4_Lite_Slave_ifc, - -// Higher-level enums and structs for the 5 AXI4 channel payloads -AXI4_Lite_Resp (..), - -AXI4_Lite_Wr_Addr (..), -AXI4_Lite_Wr_Data (..), -AXI4_Lite_Wr_Resp (..), -AXI4_Lite_Rd_Addr (..), -AXI4_Lite_Rd_Data (..), - -// Higher-level FIFO-like interfaces for the 5 AXI4 channels, -AXI4_Lite_Server_IFC (..), -AXI4_Lite_Client_IFC (..), -AXI4_Lite_Buffer_IFC (..), -mkAXI4_Lite_Buffer, -mkAXI4_Lite_Buffer_2, - -// Transactors from RTL-level interfacecs to FIFO-like interfaces. -AXI4_Lite_Master_Xactor_IFC (..), -mkAXI4_Lite_Master_Xactor, // Using standard mkGFIFOFs -mkAXI4_Lite_Master_Xactor_2, // Using cregs/regs instead of mkGFIFOFs - -AXI4_Lite_Slave_Xactor_IFC (..), -mkAXI4_Lite_Slave_Xactor, // Using standard mkGFIFOFs -mkAXI4_Lite_Slave_Xactor_2; // Using cregs/regs instead of mkGFIFOFs - -// ================================================================ -// BSV library imports - -import FIFOF :: *; -import Connectable :: *; - -// ---------------- -// BSV additional libs - -import Semi_FIFOF :: *; -import EdgeFIFOFs :: *; - -// **************************************************************** -// **************************************************************** -// Section: RTL-level interfaces -// **************************************************************** -// **************************************************************** - -// ================================================================ -// These are the signal-level interfaces for an AXI4-Lite master. -// The (*..*) attributes ensure that when bsc compiles this to Verilog, -// we get exactly the signals specified in the ARM spec. - -interface AXI4_Lite_Master_IFC #(numeric type wd_addr, - numeric type wd_data, - numeric type wd_user); - // Wr Addr channel - (* always_ready, result="awvalid" *) method Bool m_awvalid; // out - (* always_ready, result="awaddr" *) method Bit #(wd_addr) m_awaddr; // out - (* always_ready, result="awprot" *) method Bit #(3) m_awprot; // out - (* always_ready, result="awuser" *) method Bit #(wd_user) m_awuser; // out - (* always_ready, always_enabled, prefix="" *) - method Action m_awready ((* port="awready" *) Bool awready); // in - - // Wr Data channel - (* always_ready, result="wvalid" *) method Bool m_wvalid; // out - (* always_ready, result="wdata" *) method Bit #(wd_data) m_wdata; // out - (* always_ready, result="wstrb" *) method Bit #(TDiv #(wd_data, 8)) m_wstrb; // out - (* always_ready, always_enabled, prefix = "" *) - method Action m_wready ((* port="wready" *) Bool wready); // in - - // Wr Response channel - (* always_ready, always_enabled, prefix = "" *) - method Action m_bvalid ((* port="bvalid" *) Bool bvalid, // in - (* port="bresp" *) Bit #(2) bresp, // in - (* port="buser" *) Bit #(wd_user) buser); // in - (* always_ready, prefix = "", result="bready" *) - method Bool m_bready; // out - - // Rd Addr channel - (* always_ready, result="arvalid", prefix = "" *) - method Bool m_arvalid; // out - (* always_ready, result="araddr" *) method Bit #(wd_addr) m_araddr; // out - (* always_ready, result="arprot" *) method Bit #(3) m_arprot; // out - (* always_ready, result="aruser" *) method Bit #(wd_user) m_aruser; // out - (* always_ready, always_enabled, prefix="" *) - method Action m_arready ((* port="arready" *) Bool arready); // in - - // Rd Data channel - (* always_ready, always_enabled, prefix = "" *) - method Action m_rvalid ((* port="rvalid" *) Bool rvalid, // in - (* port="rresp" *) Bit #(2) rresp, // in - (* port="rdata" *) Bit #(wd_data) rdata, // in - (* port="ruser" *) Bit #(wd_user) ruser); // in - (* always_ready, result="rready" *) - method Bool m_rready; // out -endinterface: AXI4_Lite_Master_IFC - -// ================================================================ -// These are the signal-level interfaces for an AXI4-Lite slave. -// The (*..*) attributes ensure that when bsc compiles this to Verilog, -// we get exactly the signals specified in the ARM spec. - -interface AXI4_Lite_Slave_IFC #(numeric type wd_addr, - numeric type wd_data, - numeric type wd_user); - // Wr Addr channel - (* always_ready, always_enabled, prefix = "" *) - method Action m_awvalid ((* port="awvalid" *) Bool awvalid, // in - (* port="awaddr" *) Bit #(wd_addr) awaddr, // in - (* port="awprot" *) Bit #(3) awprot, // in - (* port="awuser" *) Bit #(wd_user) awuser); // in - (* always_ready, result="awready" *) - method Bool m_awready; // out - - // Wr Data channel - (* always_ready, always_enabled, prefix = "" *) - method Action m_wvalid ((* port="wvalid" *) Bool wvalid, // in - (* port="wdata" *) Bit #(wd_data) wdata, // in - (* port="wstrb" *) Bit #(TDiv #(wd_data,8)) wstrb); // in - (* always_ready, result="wready" *) - method Bool m_wready; // out - - // Wr Response channel - (* always_ready, result="bvalid" *) method Bool m_bvalid; // out - (* always_ready, result="bresp" *) method Bit #(2) m_bresp; // out - (* always_ready, result="buser" *) method Bit #(wd_user) m_buser; // out - (* always_ready, always_enabled, prefix="" *) - method Action m_bready ((* port="bready" *) Bool bready); // in - - // Rd Addr channel - (* always_ready, always_enabled, prefix = "" *) - method Action m_arvalid ((* port="arvalid" *) Bool arvalid, // in - (* port="araddr" *) Bit #(wd_addr) araddr, // in - (* port="arprot" *) Bit #(3) arprot, // in - (* port="aruser" *) Bit #(wd_user) aruser); // in - (* always_ready, result="arready" *) - method Bool m_arready; // out - - // Rd Data channel - (* always_ready, result="rvalid" *) method Bool m_rvalid; // out - (* always_ready, result="rresp" *) method Bit #(2) m_rresp; // out - (* always_ready, result="rdata" *) method Bit #(wd_data) m_rdata; // out - (* always_ready, result="ruser" *) method Bit #(wd_user) m_ruser; // out - (* always_ready, always_enabled, prefix="" *) - method Action m_rready ((* port="rready" *) Bool rready); // in -endinterface: AXI4_Lite_Slave_IFC - -// ================================================================ -// Connecting signal-level interfaces - -instance Connectable #(AXI4_Lite_Master_IFC #(wd_addr, wd_data, wd_user), - AXI4_Lite_Slave_IFC #(wd_addr, wd_data, wd_user)); - - module mkConnection #(AXI4_Lite_Master_IFC #(wd_addr, wd_data, wd_user) axim, - AXI4_Lite_Slave_IFC #(wd_addr, wd_data, wd_user) axis) - (Empty); - - (* fire_when_enabled, no_implicit_conditions *) - rule rl_wr_addr_channel; - axis.m_awvalid (axim.m_awvalid, axim.m_awaddr, axim.m_awprot, axim.m_awuser); - axim.m_awready (axis.m_awready); - endrule - - (* fire_when_enabled, no_implicit_conditions *) - rule rl_wr_data_channel; - axis.m_wvalid (axim.m_wvalid, axim.m_wdata, axim.m_wstrb); - axim.m_wready (axis.m_wready); - endrule - - (* fire_when_enabled, no_implicit_conditions *) - rule rl_wr_response_channel; - axim.m_bvalid (axis.m_bvalid, axis.m_bresp, axis.m_buser); - axis.m_bready (axim.m_bready); - endrule - - (* fire_when_enabled, no_implicit_conditions *) - rule rl_rd_addr_channel; - axis.m_arvalid (axim.m_arvalid, axim.m_araddr, axim.m_arprot, axim.m_aruser); - axim.m_arready (axis.m_arready); - endrule - - (* fire_when_enabled, no_implicit_conditions *) - rule rl_rd_data_channel; - axim.m_rvalid (axis.m_rvalid, axis.m_rresp, axis.m_rdata, axis.m_ruser); - axis.m_rready (axim.m_rready); - endrule - endmodule -endinstance - -// ================================================================ -// AXI4-Lite dummy master: never produces requests, never accepts responses - -AXI4_Lite_Master_IFC #(wd_addr, wd_data, wd_user) - dummy_AXI4_Lite_Master_ifc = interface AXI4_Lite_Master_IFC - // Wr Addr channel - method Bool m_awvalid = False; // out - method Bit #(wd_addr) m_awaddr = ?; // out - method Bit #(3) m_awprot = ?; // out - method Bit #(wd_user) m_awuser = ?; // out - method Action m_awready (Bool awready) = noAction; // in - - // Wr Data channel - method Bool m_wvalid = False; // out - method Bit #(wd_data) m_wdata = ?; // out - method Bit #(TDiv #(wd_data, 8)) m_wstrb = ?; // out - method Action m_wready (Bool wready) = noAction; // in - - // Wr Response channel - method Action m_bvalid (Bool bvalid, // in - Bit #(2) bresp, // in - Bit #(wd_user) buser); // in - noAction; - endmethod - method Bool m_bready = False; // out - - // Rd Addr channel - method Bool m_arvalid = False; // out - method Bit #(wd_addr) m_araddr = ?; // out - method Bit #(3) m_arprot = ?; // out - method Bit #(wd_user) m_aruser = ?; // out - method Action m_arready (Bool arready) = noAction; // in - - // Rd Data channel - method Action m_rvalid (Bool rvalid, // in - Bit #(2) rresp, // in - Bit #(wd_data) rdata, // in - Bit #(wd_user) ruser); // in - noAction; - endmethod - method Bool m_rready = False; // out - endinterface; - -// ================================================================ -// AXI4-Lite dummy slave: never accepts requests, never produces responses - -AXI4_Lite_Slave_IFC #(wd_addr, wd_data, wd_user) - dummy_AXI4_Lite_Slave_ifc = interface AXI4_Lite_Slave_IFC - // Wr Addr channel - method Action m_awvalid (Bool awvalid, - Bit #(wd_addr) awaddr, - Bit #(3) awprot, - Bit #(wd_user) awuser); - noAction; - endmethod - - method Bool m_awready; - return False; - endmethod - - // Wr Data channel - method Action m_wvalid (Bool wvalid, - Bit #(wd_data) wdata, - Bit #(TDiv #(wd_data,8)) wstrb); - noAction; - endmethod - - method Bool m_wready; - return False; - endmethod - - // Wr Response channel - method Bool m_bvalid; - return False; - endmethod - - method Bit #(2) m_bresp; - return 0; - endmethod - - method Bit #(wd_user) m_buser; - return ?; - endmethod - - method Action m_bready (Bool bready); - noAction; - endmethod - - // Rd Addr channel - method Action m_arvalid (Bool arvalid, - Bit #(wd_addr) araddr, - Bit #(3) arprot, - Bit #(wd_user) aruser); - noAction; - endmethod - - method Bool m_arready; - return False; - endmethod - - // Rd Data channel - method Bool m_rvalid; - return False; - endmethod - - method Bit #(2) m_rresp; - return 0; - endmethod - - method Bit #(wd_data) m_rdata; - return 0; - endmethod - - method Bit #(wd_user) m_ruser; - return ?; - endmethod - - method Action m_rready (Bool rready); - noAction; - endmethod - endinterface; - -// **************************************************************** -// **************************************************************** -// Section: Higher-level FIFO-like interfaces and transactors -// **************************************************************** -// **************************************************************** - -// ================================================================ -// Help function: fn_crg_and_rg_to_FIFOF_I -// In the modules below, we use a crg_full and a rg_data to represent a fifo. -// These functions convert these to FIFOF_I and FIFOF_O interfaces. - -function FIFOF_I #(t) fn_crg_and_rg_to_FIFOF_I (Reg #(Bool) rg_full, Reg #(t) rg_data); - return interface FIFOF_I; - method Action enq (t x) if (! rg_full); - rg_full <= True; - rg_data <= x; - endmethod - method Bool notFull; - return (! rg_full); - endmethod - endinterface; -endfunction - -function FIFOF_O #(t) fn_crg_and_rg_to_FIFOF_O (Reg #(Bool) rg_full, Reg #(t) rg_data); - return interface FIFOF_O; - method t first () if (rg_full); - return rg_data; - endmethod - method Action deq () if (rg_full); - rg_full <= False; - endmethod - method notEmpty; - return rg_full; - endmethod - endinterface; -endfunction - -// ================================================================ -// Higher-level types for payloads (rather than just bits) - -typedef enum { AXI4_LITE_OKAY, AXI4_LITE_EXOKAY, AXI4_LITE_SLVERR, AXI4_LITE_DECERR } AXI4_Lite_Resp -deriving (Bits, Eq, FShow); - -// Write Address channel - -typedef struct { - Bit #(wd_addr) awaddr; - Bit #(3) awprot; - Bit #(wd_user) awuser; - } AXI4_Lite_Wr_Addr #(numeric type wd_addr, numeric type wd_user) -deriving (Bits, FShow); - -// Write Data channel - -typedef struct { - Bit #(wd_data) wdata; - Bit #(TDiv #(wd_data, 8)) wstrb; - } AXI4_Lite_Wr_Data #(numeric type wd_data) -deriving (Bits, FShow); - -// Write Response channel - -typedef struct { - AXI4_Lite_Resp bresp; - Bit #(wd_user) buser; - } AXI4_Lite_Wr_Resp #(numeric type wd_user) -deriving (Bits, FShow); - -// Read Address channel - -typedef struct { - Bit #(wd_addr) araddr; - Bit #(3) arprot; - Bit #(wd_user) aruser; - } AXI4_Lite_Rd_Addr #(numeric type wd_addr, numeric type wd_user) -deriving (Bits, FShow); - -// Read Data channel - -typedef struct { - AXI4_Lite_Resp rresp; - Bit #(wd_data) rdata; - Bit #(wd_user) ruser; - } AXI4_Lite_Rd_Data #(numeric type wd_data, numeric type wd_user) -deriving (Bits, FShow); - -// ================================================================ -// AXI4-Lite buffer - -// ---------------- -// Server-side interface accepts requests and yields responses - -interface AXI4_Lite_Server_IFC #(numeric type wd_addr, - numeric type wd_data, - numeric type wd_user); - - interface FIFOF_I #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) i_wr_addr; - interface FIFOF_I #(AXI4_Lite_Wr_Data #(wd_data)) i_wr_data; - interface FIFOF_O #(AXI4_Lite_Wr_Resp #(wd_user)) o_wr_resp; - - interface FIFOF_I #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) i_rd_addr; - interface FIFOF_O #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) o_rd_data; -endinterface - -// ---------------- -// Client-side interface yields requests and accepts responses - -interface AXI4_Lite_Client_IFC #(numeric type wd_addr, - numeric type wd_data, - numeric type wd_user); - - interface FIFOF_O #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) o_wr_addr; - interface FIFOF_O #(AXI4_Lite_Wr_Data #(wd_data)) o_wr_data; - interface FIFOF_I #(AXI4_Lite_Wr_Resp #(wd_user)) i_wr_resp; - - interface FIFOF_O #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) o_rd_addr; - interface FIFOF_I #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) i_rd_data; -endinterface - -// ---------------- -// A Buffer has a server-side and a client-side, and a reset - -interface AXI4_Lite_Buffer_IFC #(numeric type wd_addr, - numeric type wd_data, - numeric type wd_user); - method Action reset; - interface AXI4_Lite_Server_IFC #(wd_addr, wd_data, wd_user) server_side; - interface AXI4_Lite_Client_IFC #(wd_addr, wd_data, wd_user) client_side; -endinterface - -// ---------------------------------------------------------------- - -module mkAXI4_Lite_Buffer (AXI4_Lite_Buffer_IFC #(wd_addr, wd_data, wd_user)); - - FIFOF #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkFIFOF; - FIFOF #(AXI4_Lite_Wr_Data #(wd_data)) f_wr_data <- mkFIFOF; - FIFOF #(AXI4_Lite_Wr_Resp #(wd_user)) f_wr_resp <- mkFIFOF; - - FIFOF #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkFIFOF; - FIFOF #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkFIFOF; - - method Action reset; - f_wr_addr.clear; - f_wr_data.clear; - f_wr_resp.clear; - - f_rd_addr.clear; - f_rd_data.clear; - endmethod - - interface AXI4_Lite_Server_IFC server_side; - interface i_wr_addr = to_FIFOF_I (f_wr_addr); - interface i_wr_data = to_FIFOF_I (f_wr_data); - interface o_wr_resp = to_FIFOF_O (f_wr_resp); - - interface i_rd_addr = to_FIFOF_I (f_rd_addr); - interface o_rd_data = to_FIFOF_O (f_rd_data); - endinterface - - interface AXI4_Lite_Client_IFC client_side; - interface o_wr_addr = to_FIFOF_O (f_wr_addr); - interface o_wr_data = to_FIFOF_O (f_wr_data); - interface i_wr_resp = to_FIFOF_I (f_wr_resp); - - interface o_rd_addr = to_FIFOF_O (f_rd_addr); - interface i_rd_data = to_FIFOF_I (f_rd_data); - endinterface -endmodule - -module mkAXI4_Lite_Buffer_2 (AXI4_Lite_Buffer_IFC #(wd_addr, wd_data, wd_user)); - - FIFOF #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkMaster_EdgeFIFOF; - FIFOF #(AXI4_Lite_Wr_Data #(wd_data)) f_wr_data <- mkMaster_EdgeFIFOF; - FIFOF #(AXI4_Lite_Wr_Resp #(wd_user)) f_wr_resp <- mkSlave_EdgeFIFOF; - - FIFOF #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkMaster_EdgeFIFOF; - FIFOF #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkSlave_EdgeFIFOF; - - method Action reset; - f_wr_addr.clear; - f_wr_data.clear; - f_wr_resp.clear; - - f_rd_addr.clear; - f_rd_data.clear; - endmethod - - interface AXI4_Lite_Server_IFC server_side; - interface i_wr_addr = to_FIFOF_I (f_wr_addr); - interface i_wr_data = to_FIFOF_I (f_wr_data); - interface o_wr_resp = to_FIFOF_O (f_wr_resp); - - interface i_rd_addr = to_FIFOF_I (f_rd_addr); - interface o_rd_data = to_FIFOF_O (f_rd_data); - endinterface - - interface AXI4_Lite_Client_IFC client_side; - interface o_wr_addr = to_FIFOF_O (f_wr_addr); - interface o_wr_data = to_FIFOF_O (f_wr_data); - interface i_wr_resp = to_FIFOF_I (f_wr_resp); - - interface o_rd_addr = to_FIFOF_O (f_rd_addr); - interface i_rd_data = to_FIFOF_I (f_rd_data); - endinterface -endmodule - -// ================================================================ -// Master transactor interface - -interface AXI4_Lite_Master_Xactor_IFC #(numeric type wd_addr, - numeric type wd_data, - numeric type wd_user); - method Action reset; - - // AXI side - interface AXI4_Lite_Master_IFC #(wd_addr, wd_data, wd_user) axi_side; - - // FIFOF side - interface FIFOF_I #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) i_wr_addr; - interface FIFOF_I #(AXI4_Lite_Wr_Data #(wd_data)) i_wr_data; - interface FIFOF_O #(AXI4_Lite_Wr_Resp #(wd_user)) o_wr_resp; - - interface FIFOF_I #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) i_rd_addr; - interface FIFOF_O #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) o_rd_data; -endinterface: AXI4_Lite_Master_Xactor_IFC - -// ---------------------------------------------------------------- -// Master transactor -// This version uses FIFOFs for total decoupling. - -module mkAXI4_Lite_Master_Xactor (AXI4_Lite_Master_Xactor_IFC #(wd_addr, wd_data, wd_user)); - - Bool unguarded = True; - Bool guarded = False; - - // These FIFOs are guarded on BSV side, unguarded on AXI side - FIFOF #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (guarded, unguarded); - FIFOF #(AXI4_Lite_Wr_Data #(wd_data)) f_wr_data <- mkGFIFOF (guarded, unguarded); - FIFOF #(AXI4_Lite_Wr_Resp #(wd_user)) f_wr_resp <- mkGFIFOF (unguarded, guarded); - - FIFOF #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (guarded, unguarded); - FIFOF #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkGFIFOF (unguarded, guarded); - - // ---------------------------------------------------------------- - // INTERFACE - - method Action reset; - f_wr_addr.clear; - f_wr_data.clear; - f_wr_resp.clear; - f_rd_addr.clear; - f_rd_data.clear; - endmethod - - // AXI side - interface axi_side = interface AXI4_Lite_Master_IFC; - // Wr Addr channel - method Bool m_awvalid = f_wr_addr.notEmpty; - method Bit #(wd_addr) m_awaddr = f_wr_addr.first.awaddr; - method Bit #(3) m_awprot = f_wr_addr.first.awprot; - method Bit #(wd_user) m_awuser = f_wr_addr.first.awuser; - method Action m_awready (Bool awready); - if (f_wr_addr.notEmpty && awready) f_wr_addr.deq; - endmethod - - // Wr Data channel - method Bool m_wvalid = f_wr_data.notEmpty; - method Bit #(wd_data) m_wdata = f_wr_data.first.wdata; - method Bit #(TDiv #(wd_data, 8)) m_wstrb = f_wr_data.first.wstrb; - method Action m_wready (Bool wready); - if (f_wr_data.notEmpty && wready) f_wr_data.deq; - endmethod - - // Wr Response channel - method Action m_bvalid (Bool bvalid, Bit #(2) bresp, Bit #(wd_user) buser); - if (bvalid && f_wr_resp.notFull) - f_wr_resp.enq (AXI4_Lite_Wr_Resp {bresp: unpack (bresp), buser: buser}); - endmethod - - method Bool m_bready; - return f_wr_resp.notFull; - endmethod - - // Rd Addr channel - method Bool m_arvalid = f_rd_addr.notEmpty; - method Bit #(wd_addr) m_araddr = f_rd_addr.first.araddr; - method Bit #(3) m_arprot = f_rd_addr.first.arprot; - method Bit #(wd_user) m_aruser = f_rd_addr.first.aruser; - method Action m_arready (Bool arready); - if (f_rd_addr.notEmpty && arready) f_rd_addr.deq; - endmethod - - // Rd Data channel - method Action m_rvalid (Bool rvalid, - Bit #(2) rresp, - Bit #(wd_data) rdata, - Bit #(wd_user) ruser); - if (rvalid && f_rd_data.notFull) - f_rd_data.enq (AXI4_Lite_Rd_Data {rresp: unpack (rresp), - rdata: rdata, - ruser: ruser}); - endmethod - - method Bool m_rready; - return f_rd_data.notFull; - endmethod - - endinterface; - - // FIFOF side - interface i_wr_addr = to_FIFOF_I (f_wr_addr); - interface i_wr_data = to_FIFOF_I (f_wr_data); - interface o_wr_resp = to_FIFOF_O (f_wr_resp); - - interface i_rd_addr = to_FIFOF_I (f_rd_addr); - interface o_rd_data = to_FIFOF_O (f_rd_data); -endmodule: mkAXI4_Lite_Master_Xactor - -// ---------------------------------------------------------------- -// Master transactor -// This version uses crgs and regs instead of FIFOFs. -// This uses 1/2 the resources, but introduces scheduling dependencies. - -module mkAXI4_Lite_Master_Xactor_2 (AXI4_Lite_Master_Xactor_IFC #(wd_addr, wd_data, wd_user)); - - // Each crg_full, rg_data pair below represents a 1-element fifo. - - Array #(Reg #(Bool)) crg_wr_addr_full <- mkCReg (3, False); - Reg #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) rg_wr_addr <- mkRegU; - - Array #(Reg #(Bool)) crg_wr_data_full <- mkCReg (3, False); - Reg #(AXI4_Lite_Wr_Data #(wd_data)) rg_wr_data <- mkRegU; - - Array #(Reg #(Bool)) crg_wr_resp_full <- mkCReg (3, False); - Reg #(AXI4_Lite_Wr_Resp #(wd_user)) rg_wr_resp <- mkRegU; - - Array #(Reg #(Bool)) crg_rd_addr_full <- mkCReg (3, False); - Reg #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) rg_rd_addr <- mkRegU; - - Array #(Reg #(Bool)) crg_rd_data_full <- mkCReg (3, False); - Reg #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) rg_rd_data <- mkRegU; - - // The following CReg port indexes specify the relative scheduling of: - // {first,deq,notEmpty} {enq,notFull} clear - - // TODO: 'deq/enq/clear = 1/2/0' is unusual, but eliminates a - // scheduling cycle in Piccolo's DCache. Normally should be 0/1/2. - - Integer port_deq = 1; - Integer port_enq = 2; - Integer port_clear = 0; - - // ---------------------------------------------------------------- - // INTERFACE - - method Action reset; - crg_wr_addr_full [port_clear] <= False; - crg_wr_data_full [port_clear] <= False; - crg_wr_resp_full [port_clear] <= False; - crg_rd_addr_full [port_clear] <= False; - crg_rd_data_full [port_clear] <= False; - endmethod - - // AXI side - interface axi_side = interface AXI4_Lite_Master_IFC; - // Wr Addr channel - method Bool m_awvalid = crg_wr_addr_full [port_deq]; - method Bit #(wd_addr) m_awaddr = rg_wr_addr.awaddr; - method Bit #(3) m_awprot = rg_wr_addr.awprot; - method Bit #(wd_user) m_awuser = rg_wr_addr.awuser; - method Action m_awready (Bool awready); - if (crg_wr_addr_full [port_deq] && awready) - crg_wr_addr_full [port_deq] <= False; // deq - endmethod - - // Wr Data channel - method Bool m_wvalid = crg_wr_data_full [port_deq]; - method Bit #(wd_data) m_wdata = rg_wr_data.wdata; - method Bit #(TDiv #(wd_data, 8)) m_wstrb = rg_wr_data.wstrb; - method Action m_wready (Bool wready); - if (crg_wr_data_full [port_deq] && wready) - crg_wr_data_full [port_deq] <= False; - endmethod - - // Wr Response channel - method Action m_bvalid (Bool bvalid, Bit #(2) bresp, Bit #(wd_user) buser); - if (bvalid && (! (crg_wr_resp_full [port_enq]))) begin - crg_wr_resp_full [port_enq] <= True; - rg_wr_resp <= AXI4_Lite_Wr_Resp {bresp: unpack (bresp), - buser: buser}; - end - endmethod - - method Bool m_bready; - return (! (crg_wr_resp_full [port_enq])); - endmethod - - // Rd Addr channel - method Bool m_arvalid = crg_rd_addr_full [port_deq]; - method Bit #(wd_addr) m_araddr = rg_rd_addr.araddr; - method Bit #(3) m_arprot = rg_rd_addr.arprot; - method Bit #(wd_user) m_aruser = rg_rd_addr.aruser; - method Action m_arready (Bool arready); - if (crg_rd_addr_full [port_deq] && arready) - crg_rd_addr_full [port_deq] <= False; // deq - endmethod - - // Rd Data channel - method Action m_rvalid (Bool rvalid, - Bit #(2) rresp, - Bit #(wd_data) rdata, - Bit #(wd_user) ruser); - if (rvalid && (! (crg_rd_data_full [port_enq]))) - crg_rd_data_full [port_enq] <= True; - rg_rd_data <= (AXI4_Lite_Rd_Data {rresp: unpack (rresp), - rdata: rdata, - ruser: ruser}); - endmethod - - method Bool m_rready; - return (! (crg_rd_data_full [port_enq])); - endmethod - - endinterface; - - // FIFOF side - interface i_wr_addr = fn_crg_and_rg_to_FIFOF_I (crg_wr_addr_full [port_enq], rg_wr_addr); - interface i_wr_data = fn_crg_and_rg_to_FIFOF_I (crg_wr_data_full [port_enq], rg_wr_data); - interface o_wr_resp = fn_crg_and_rg_to_FIFOF_O (crg_wr_resp_full [port_deq], rg_wr_resp); - - interface i_rd_addr = fn_crg_and_rg_to_FIFOF_I (crg_rd_addr_full [port_enq], rg_rd_addr); - interface o_rd_data = fn_crg_and_rg_to_FIFOF_O (crg_rd_data_full [port_deq], rg_rd_data); -endmodule: mkAXI4_Lite_Master_Xactor_2 - -// ================================================================ -// Slave transactor interface - -interface AXI4_Lite_Slave_Xactor_IFC #(numeric type wd_addr, - numeric type wd_data, - numeric type wd_user); - method Action reset; - - // AXI side - interface AXI4_Lite_Slave_IFC #(wd_addr, wd_data, wd_user) axi_side; - - // FIFOF side - interface FIFOF_O #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) o_wr_addr; - interface FIFOF_O #(AXI4_Lite_Wr_Data #(wd_data)) o_wr_data; - interface FIFOF_I #(AXI4_Lite_Wr_Resp #(wd_user)) i_wr_resp; - - interface FIFOF_O #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) o_rd_addr; - interface FIFOF_I #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) i_rd_data; -endinterface: AXI4_Lite_Slave_Xactor_IFC - -// ---------------------------------------------------------------- -// Slave transactor -// This version uses FIFOFs for total decoupling. - -module mkAXI4_Lite_Slave_Xactor (AXI4_Lite_Slave_Xactor_IFC #(wd_addr, wd_data, wd_user)); - - Bool unguarded = True; - Bool guarded = False; - - // These FIFOs are guarded on BSV side, unguarded on AXI side - FIFOF #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (unguarded, guarded); - FIFOF #(AXI4_Lite_Wr_Data #(wd_data)) f_wr_data <- mkGFIFOF (unguarded, guarded); - FIFOF #(AXI4_Lite_Wr_Resp #(wd_user)) f_wr_resp <- mkGFIFOF (guarded, unguarded); - - FIFOF #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (unguarded, guarded); - FIFOF #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkGFIFOF (guarded, unguarded); - - // ---------------------------------------------------------------- - // INTERFACE - - method Action reset; - f_wr_addr.clear; - f_wr_data.clear; - f_wr_resp.clear; - f_rd_addr.clear; - f_rd_data.clear; - endmethod - - // AXI side - interface axi_side = interface AXI4_Lite_Slave_IFC; - // Wr Addr channel - method Action m_awvalid (Bool awvalid, - Bit #(wd_addr) awaddr, - Bit #(3) awprot, - Bit #(wd_user) awuser); - if (awvalid && f_wr_addr.notFull) - f_wr_addr.enq (AXI4_Lite_Wr_Addr {awaddr: awaddr, - awprot: awprot, - awuser: awuser}); - endmethod - - method Bool m_awready; - return f_wr_addr.notFull; - endmethod - - // Wr Data channel - method Action m_wvalid (Bool wvalid, - Bit #(wd_data) wdata, - Bit #(TDiv #(wd_data, 8)) wstrb); - if (wvalid && f_wr_data.notFull) - f_wr_data.enq (AXI4_Lite_Wr_Data {wdata: wdata, wstrb: wstrb}); - endmethod - - method Bool m_wready; - return f_wr_data.notFull; - endmethod - - // Wr Response channel - method Bool m_bvalid = f_wr_resp.notEmpty; - method Bit #(2) m_bresp = pack (f_wr_resp.first.bresp); - method Bit #(wd_user) m_buser = f_wr_resp.first.buser; - method Action m_bready (Bool bready); - if (bready && f_wr_resp.notEmpty) - f_wr_resp.deq; - endmethod - - // Rd Addr channel - method Action m_arvalid (Bool arvalid, - Bit #(wd_addr) araddr, - Bit #(3) arprot, - Bit #(wd_user) aruser); - if (arvalid && f_rd_addr.notFull) - f_rd_addr.enq (AXI4_Lite_Rd_Addr {araddr: araddr, - arprot: arprot, - aruser: aruser}); - endmethod - - method Bool m_arready; - return f_rd_addr.notFull; - endmethod - - // Rd Data channel - method Bool m_rvalid = f_rd_data.notEmpty; - method Bit #(2) m_rresp = pack (f_rd_data.first.rresp); - method Bit #(wd_data) m_rdata = f_rd_data.first.rdata; - method Bit #(wd_user) m_ruser = f_rd_data.first.ruser; - method Action m_rready (Bool rready); - if (rready && f_rd_data.notEmpty) - f_rd_data.deq; - endmethod - endinterface; - - // FIFOF side - interface o_wr_addr = to_FIFOF_O (f_wr_addr); - interface o_wr_data = to_FIFOF_O (f_wr_data); - interface i_wr_resp = to_FIFOF_I (f_wr_resp); - - interface o_rd_addr = to_FIFOF_O (f_rd_addr); - interface i_rd_data = to_FIFOF_I (f_rd_data); -endmodule: mkAXI4_Lite_Slave_Xactor - -// ---------------------------------------------------------------- -// Slave transactor -// This version uses crgs and regs instead of FIFOFs. -// This uses 1/2 the resources, but introduces scheduling dependencies. - -module mkAXI4_Lite_Slave_Xactor_2 (AXI4_Lite_Slave_Xactor_IFC #(wd_addr, wd_data, wd_user)); - - // Each crg_full, rg_data pair below represents a 1-element fifo. - - // These FIFOs are guarded on BSV side, unguarded on AXI side - Array #(Reg #(Bool)) crg_wr_addr_full <- mkCReg (3, False); - Reg #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) rg_wr_addr <- mkRegU; - - Array #(Reg #(Bool)) crg_wr_data_full <- mkCReg (3, False); - Reg #(AXI4_Lite_Wr_Data #(wd_data)) rg_wr_data <- mkRegU; - - Array #(Reg #(Bool)) crg_wr_resp_full <- mkCReg (3, False); - Reg #(AXI4_Lite_Wr_Resp #(wd_user)) rg_wr_resp <- mkRegU; - - Array #(Reg #(Bool)) crg_rd_addr_full <- mkCReg (3, False); - Reg #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) rg_rd_addr <- mkRegU; - - Array #(Reg #(Bool)) crg_rd_data_full <- mkCReg (3, False); - Reg #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) rg_rd_data <- mkRegU; - - // The following CReg port indexes specify the relative scheduling of: - // {first,deq,notEmpty} {enq,notFull} clear - Integer port_deq = 0; - Integer port_enq = 1; - Integer port_clear = 2; - - // ---------------------------------------------------------------- - // INTERFACE - - method Action reset; - crg_wr_addr_full [port_clear] <= False; - crg_wr_data_full [port_clear] <= False; - crg_wr_resp_full [port_clear] <= False; - crg_rd_addr_full [port_clear] <= False; - crg_rd_data_full [port_clear] <= False; - endmethod - - // AXI side - interface axi_side = interface AXI4_Lite_Slave_IFC; - // Wr Addr channel - method Action m_awvalid (Bool awvalid, - Bit #(wd_addr) awaddr, - Bit #(3) awprot, - Bit #(wd_user) awuser); - if (awvalid && (! crg_wr_addr_full [port_enq])) begin - crg_wr_addr_full [port_enq] <= True; // enq - rg_wr_addr <= AXI4_Lite_Wr_Addr {awaddr: awaddr, - awprot: awprot, - awuser: awuser}; - end - endmethod - - method Bool m_awready; - return (! crg_wr_addr_full [port_enq]); - endmethod - - // Wr Data channel - method Action m_wvalid (Bool wvalid, - Bit #(wd_data) wdata, - Bit #(TDiv #(wd_data, 8)) wstrb); - if (wvalid && (! crg_wr_data_full [port_enq])) begin - crg_wr_data_full [port_enq] <= True; // enq - rg_wr_data <= AXI4_Lite_Wr_Data {wdata: wdata, wstrb: wstrb}; - end - endmethod - - method Bool m_wready; - return (! crg_wr_data_full [port_enq]); - endmethod - - // Wr Response channel - method Bool m_bvalid = crg_wr_resp_full [port_deq]; - method Bit #(2) m_bresp = pack (rg_wr_resp.bresp); - method Bit #(wd_user) m_buser = rg_wr_resp.buser; - method Action m_bready (Bool bready); - if (bready && crg_wr_resp_full [port_deq]) - crg_wr_resp_full [port_deq] <= False; // deq - endmethod - - // Rd Addr channel - method Action m_arvalid (Bool arvalid, - Bit #(wd_addr) araddr, - Bit #(3) arprot, - Bit #(wd_user) aruser); - if (arvalid && (! crg_rd_addr_full [port_enq])) begin - crg_rd_addr_full [port_enq] <= True; // enq - rg_rd_addr <= AXI4_Lite_Rd_Addr {araddr: araddr, - arprot: arprot, - aruser: aruser}; - end - endmethod - - method Bool m_arready; - return (! crg_rd_addr_full [port_enq]); - endmethod - - // Rd Data channel - method Bool m_rvalid = crg_rd_data_full [port_deq]; - method Bit #(2) m_rresp = pack (rg_rd_data.rresp); - method Bit #(wd_data) m_rdata = rg_rd_data.rdata; - method Bit #(wd_user) m_ruser = rg_rd_data.ruser; - method Action m_rready (Bool rready); - if (rready && crg_rd_data_full [port_deq]) - crg_rd_data_full [port_deq] <= False; // deq - endmethod - endinterface; - - // FIFOF side - interface o_wr_addr = fn_crg_and_rg_to_FIFOF_O (crg_wr_addr_full [port_deq], rg_wr_addr); - interface o_wr_data = fn_crg_and_rg_to_FIFOF_O (crg_wr_data_full [port_deq], rg_wr_data); - interface i_wr_resp = fn_crg_and_rg_to_FIFOF_I (crg_wr_resp_full [port_enq], rg_wr_resp); - - interface o_rd_addr = fn_crg_and_rg_to_FIFOF_O (crg_rd_addr_full [port_deq], rg_rd_addr); - interface i_rd_data = fn_crg_and_rg_to_FIFOF_I (crg_rd_data_full [port_enq], rg_rd_data); -endmodule: mkAXI4_Lite_Slave_Xactor_2 - -// ================================================================ - -endpackage diff --git a/src_Testbench/Fabrics/Adapters/AXI4_AXI4_Lite_Adapters.bsv b/src_Testbench/Fabrics/Adapters/AXI4_AXI4_Lite_Adapters.bsv deleted file mode 100644 index 8bb8a19d..00000000 --- a/src_Testbench/Fabrics/Adapters/AXI4_AXI4_Lite_Adapters.bsv +++ /dev/null @@ -1,151 +0,0 @@ -// Copyright (c) 2019 Bluespec, Inc. All Rights Reserved - -package AXI4_AXI4_Lite_Adapters; - -// ================================================================ -// Adapters for interconnecting AXI4 and AXI4_Lite. - -// Ref: ARM document: -// AMBA AXI and ACE Protocol Specification -// AXI3, AXI4, and AXI4-Lite -// ACE and ACE-Lite -// ARM IHI 0022E (ID022613) -// Issue E, 22 Feb 2013 - -// See export list below - -// ================================================================ -// Exports - -export - -fn_AXI4_Lite_Master_IFC_to_AXI4_Master_IFC; - -// ================================================================ -// BSV library imports - -import FIFOF :: *; -import Connectable :: *; - -// ---------------- -// BSV additional libs - -import Semi_FIFOF :: *; -import EdgeFIFOFs :: *; - -// ================================================================ -// Project imports - -import AXI4_Lite_Types :: *; -import AXI4_Types :: *; - -// ================================================================ -// Compute the encoding of AWSIZE/ARSIZE - -function Bit #(3) wd_data_to_axsize (Integer wd_data_i); - Bit #(3) axsize = ( (wd_data_i == 32) - ? 3'b_010 - : ( (wd_data_i == 64) - ? 3'b_011 - : 3'b_000)); - return axsize; -endfunction - -// ================================================================ - -function AXI4_Master_IFC #(wd_id, wd_addr, wd_data, wd_user) - fn_AXI4_Lite_Master_IFC_to_AXI4_Master_IFC - (AXI4_Lite_Master_IFC #(wd_addr, wd_data, wd_user) axi4_lite); - - return - interface AXI4_Master_IFC; - - // ---------------- - // Wr Addr channel - // output buses - method Bool m_awvalid = axi4_lite.m_awvalid; - - method Bit #(wd_id) m_awid = 0; - method Bit #(wd_addr) m_awaddr = axi4_lite.m_awaddr; - method Bit #(8) m_awlen = 0; // burst length = awlen+1 - method Bit #(3) m_awsize = wd_data_to_axsize (valueOf (wd_data)); - method Bit #(2) m_awburst = 2'b_00; // FIXED - method Bit #(1) m_awlock = 0; // NORMAL - method Bit #(4) m_awcache = 4'b_0000; // Device Non-Bufferable - method Bit #(3) m_awprot = axi4_lite.m_awprot; - method Bit #(4) m_awqos = 4'b_0000; - method Bit #(4) m_awregion = 4'b_0000; - method Bit #(wd_user) m_awuser = 0; - - // input buses - method Action m_awready (Bool awready) = axi4_lite.m_awready (awready); - - // ---------------- - // Wr Data channel - // output buses - method Bool m_wvalid = axi4_lite.m_wvalid; - - method Bit #(wd_id) m_wid = 0; - method Bit #(wd_data) m_wdata = axi4_lite.m_wdata; - method Bit #(TDiv #(wd_data, 8)) m_wstrb = axi4_lite.m_wstrb; - method Bool m_wlast = True; - method Bit #(wd_user) m_wuser = 0; - - // input buses - method Action m_wready (Bool wready) = axi4_lite.m_wready (wready); - - // ---------------- - // Wr Response channel - // input buses - method Action m_bvalid (Bool bvalid, - Bit #(wd_id) bid, - Bit #(2) bresp, - Bit #(wd_user) buser) = axi4_lite.m_bvalid (bvalid, - bresp, - 0); - - // output buses - method Bool m_bready = axi4_lite.m_bready; - - // ---------------- - // Rd Addr channel - // output buses - method Bool m_arvalid = axi4_lite.m_arvalid; - - method Bit #(wd_id) m_arid = 0; - method Bit #(wd_addr) m_araddr = axi4_lite.m_araddr; - method Bit #(8) m_arlen = 0; // burst length = awlen+1 - method Bit #(3) m_arsize = wd_data_to_axsize (valueOf (wd_data)); - method Bit #(2) m_arburst = 2'b_00; // FIXED - method Bit #(1) m_arlock = 0; // NORMAL - method Bit #(4) m_arcache = 4'b_0000; // Device Non-Bufferable - method Bit #(3) m_arprot = axi4_lite.m_arprot; - method Bit #(4) m_arqos = 4'b_0000; - method Bit #(4) m_arregion = 4'b_0000; - method Bit #(wd_user) m_aruser = axi4_lite.m_aruser; - - // input buses - method Action m_arready (Bool arready) = axi4_lite.m_arready (arready); - - // ---------------- - // Rd Data channel - // input buses - method Action m_rvalid (Bool rvalid, - Bit #(wd_id) rid, - Bit #(wd_data) rdata, - Bit #(2) rresp, - Bool rlast, - Bit #(wd_user) ruser) = axi4_lite.m_rvalid (rvalid, - rresp, - rdata, - 0); - - // output buses - method Bool m_rready = axi4_lite.m_rready; - - endinterface; -endfunction - -// ================================================================ - -endpackage diff --git a/src_Testbench/SoC/Boot_ROM.bsv b/src_Testbench/SoC/Boot_ROM.bsv index 56c4fd62..ba9f1e89 100644 --- a/src_Testbench/SoC/Boot_ROM.bsv +++ b/src_Testbench/SoC/Boot_ROM.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package Boot_ROM; // ================================================================ @@ -23,12 +36,14 @@ import ConfigReg :: *; import Cur_Cycle :: *; import GetPut_Aux :: *; import Semi_FIFOF :: *; +import AXI4 :: *; +import SourceSink :: *; // ================================================================ // Project imports -import AXI4_Types :: *; import Fabric_Defs :: *; +import SoC_Map :: *; // ================================================================ // Include the auto-generated BSV-include file with the ROM function @@ -49,13 +64,17 @@ interface Boot_ROM_IFC; method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim); // Main Fabric Reqs/Rsps - interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave; + interface AXI4_Slave_Synth #(Wd_SId, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) slave; endinterface // ================================================================ (* synthesize *) module mkBoot_ROM (Boot_ROM_IFC); +// XXX This module seems to assume the following constraints: +// provisos(Add #(Wd_AW_User, 0, Wd_B_User), Add #(Wd_AR_User, 0, Wd_R_User)); // Verbosity: 0: quiet; 1: reads/writes Integer verbosity = 0; @@ -68,7 +87,7 @@ module mkBoot_ROM (Boot_ROM_IFC); // ---------------- // Connector to fabric - AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave_xactor <- mkAXI4_Slave_Xactor; + let slave_xactor <- mkAXI4_Slave_Xactor; // ---------------- @@ -97,14 +116,14 @@ module mkBoot_ROM (Boot_ROM_IFC); // Handle fabric read requests rule rl_process_rd_req (rg_module_ready); - let rda <- pop_o (slave_xactor.o_rd_addr); + let rda <- get(slave_xactor.master.ar); let byte_addr = rda.araddr - rg_addr_base; - AXI4_Resp rresp = axi4_resp_okay; + AXI4_Resp rresp = OKAY; Bit #(64) data64 = 0; if (! fn_addr_is_ok (rg_addr_base, rda.araddr, rg_addr_lim)) begin - rresp = axi4_resp_slverr; + rresp = SLVERR; $display ("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", cur_cycle); $display (" ", fshow (rda)); end @@ -119,12 +138,12 @@ module mkBoot_ROM (Boot_ROM_IFC); end Bit #(Wd_Data) rdata = truncate (data64); - let rdr = AXI4_Rd_Data {rid: rda.arid, - rdata: rdata, - rresp: rresp, - rlast: True, - ruser: rda.aruser}; - slave_xactor.i_rd_data.enq (rdr); + let rdr = AXI4_RFlit {rid: rda.arid, + rdata: rdata, + rresp: rresp, + rlast: True, + ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User + slave_xactor.master.r.put(rdr); if (verbosity > 0) begin $display ("%0d: Boot_ROM.rl_process_rd_req: ", cur_cycle); @@ -137,20 +156,20 @@ module mkBoot_ROM (Boot_ROM_IFC); // Handle fabric write requests: ignore all of them (this is a ROM) rule rl_process_wr_req (rg_module_ready); - let wra <- pop_o (slave_xactor.o_wr_addr); - let wrd <- pop_o (slave_xactor.o_wr_data); + let wra <- get(slave_xactor.master.aw); + let wrd <- get(slave_xactor.master.w); - AXI4_Resp bresp = axi4_resp_okay; + AXI4_Resp bresp = OKAY; if (! fn_addr_is_ok (rg_addr_base, wra.awaddr, rg_addr_lim)) begin - bresp = axi4_resp_slverr; + bresp = SLVERR; $display ("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", cur_cycle); $display (" ", fshow (wra)); end - let wrr = AXI4_Wr_Resp {bid: wra.awid, - bresp: bresp, - buser: wra.awuser}; - slave_xactor.i_wr_resp.enq (wrr); + let wrr = AXI4_BFlit {bid: wra.awid, + bresp: bresp, + buser: wra.awuser}; // XXX This requires that Wd_AW_User == Wd_B_User + slave_xactor.master.b.put(wrr); if (verbosity > 0) begin $display ("%0d: Boot_ROM.rl_process_wr_req; ignoring all writes", cur_cycle); @@ -193,7 +212,7 @@ module mkBoot_ROM (Boot_ROM_IFC); endmethod // Main Fabric Reqs/Rsps - interface slave = slave_xactor.axi_side; + interface slave = slave_xactor.slaveSynth; endmodule // ================================================================ diff --git a/src_Testbench/SoC/Mem_Controller.bsv b/src_Testbench/SoC/Mem_Controller.bsv index 06982cb1..84894d7a 100644 --- a/src_Testbench/SoC/Mem_Controller.bsv +++ b/src_Testbench/SoC/Mem_Controller.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package Mem_Controller; // ================================================================ @@ -69,13 +82,14 @@ import Cur_Cycle :: *; import GetPut_Aux :: *; import Semi_FIFOF :: *; import ByteLane :: *; +import AXI4 :: *; +import SourceSink :: *; // ================================================================ // Project imports import Fabric_Defs :: *; import SoC_Map :: *; -import AXI4_Types :: *; // ================================================================ // Raw mem data width: 256 (bits/ 32 x Byte/ 8 x Word32/ 4 x Word64) @@ -126,14 +140,14 @@ Integer lo_fabric_data = 3; // ================================================================ function Bool fn_addr_is_aligned (Fabric_Addr addr, AXI4_Size size); - Bool is_aligned = ( (size == axsize_1) - || ((size == axsize_2) && (addr [0] == 1'h0)) - || ((size == axsize_4) && (addr [1:0] == 2'h0)) - || ((size == axsize_8) && (addr [2:0] == 3'h0)) - || ((size == axsize_16) && (addr [3:0] == 4'h0)) - || ((size == axsize_32) && (addr [4:0] == 5'h0)) - || ((size == axsize_64) && (addr [5:0] == 6'h0)) - || ((size == axsize_128) && (addr [6:0] == 7'h0))); + Bool is_aligned = ( (size == 1) + || ((size == 2) && (addr [0] == 1'h0)) + || ((size == 4) && (addr [1:0] == 2'h0)) + || ((size == 8) && (addr [2:0] == 3'h0)) + || ((size == 16) && (addr [3:0] == 4'h0)) + || ((size == 32) && (addr [4:0] == 5'h0)) + || ((size == 64) && (addr [5:0] == 6'h0)) + || ((size == 128) && (addr [6:0] == 7'h0))); return is_aligned; endfunction @@ -183,6 +197,17 @@ Integer status_mem_controller_terminated = 1; // ================================================================ // Interface +// XXX TODO FIXME XXX +// This module seems to assume that +// - user fields will be mirrored from AW to B and from AR to R +// - the wuser field can be ignored +// - awuser, buser, aruser, ruser are of the same width +// We temporarily redefine the Wd_User width to be the same as that of +// Wd_AW_User as defined in Fabric_Defs. +typedef Wd_AW_User Wd_User; +export Wd_User; +// XXX TODO FIXME XXX + interface Mem_Controller_IFC; // Reset interface Server #(Bit #(0), Bit #(0)) server_reset; @@ -191,7 +216,8 @@ interface Mem_Controller_IFC; method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim); // Main Fabric Reqs/Rsps - interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave; + interface AXI4_Slave_Synth #(Wd_SId, Wd_Addr, Wd_Data, + Wd_User, Wd_User, Wd_User, Wd_User, Wd_User) slave; // To raw memory (outside the SoC) interface MemoryClient #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word) to_raw_mem; @@ -215,7 +241,7 @@ deriving (Bits, Eq, FShow); typedef struct {Req_Op req_op; // AW and AR channel info - Fabric_Id id; + Bit#(Wd_SId) id; Fabric_Addr addr; AXI4_Len len; AXI4_Size size; @@ -237,6 +263,8 @@ deriving (Bits, FShow); (* synthesize *) module mkMem_Controller (Mem_Controller_IFC); +// XXX This module seems to assume the following constraints: +// provisos(Add #(Wd_AW_User, 0, Wd_B_User), Add #(Wd_AR_User, 0, Wd_R_User)); // verbosity 0: quiet // verbosity 1: reset, initialized @@ -252,7 +280,7 @@ module mkMem_Controller (Mem_Controller_IFC); FIFOF #(Bit #(0)) f_reset_rsps <- mkFIFOF; // Communication with fabric - AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave_xactor <- mkAXI4_Slave_Xactor; + let slave_xactor <- mkAXI4_Slave_Xactor; // Requests merged from the (WrA, WrD) and RdA channels FIFOF #(Req) f_reqs <- mkPipelineFIFOF; @@ -285,7 +313,7 @@ module mkMem_Controller (Mem_Controller_IFC); function Action fa_reset_actions; action - slave_xactor.reset; + slave_xactor.clear; f_raw_mem_reqs.clear; f_raw_mem_rsps.clear; rg_status <= 0; @@ -326,7 +354,7 @@ module mkMem_Controller (Mem_Controller_IFC); // Merge requests into a single queue, prioritizing reads over writes rule rl_merge_rd_req; - let rda <- pop_o (slave_xactor.o_rd_addr); + let rda <- get(slave_xactor.master.ar); let req = Req {req_op: REQ_OP_RD, id: rda.arid, addr: rda.araddr, @@ -351,8 +379,8 @@ module mkMem_Controller (Mem_Controller_IFC); (* descending_urgency = "rl_merge_rd_req, rl_merge_wr_req" *) rule rl_merge_wr_req; - let wra <- pop_o (slave_xactor.o_wr_addr); - let wrd <- pop_o (slave_xactor.o_wr_data); + let wra <- get(slave_xactor.master.aw); + let wrd <- get(slave_xactor.master.w); let req = Req {req_op: REQ_OP_WR, id: wra.awid, addr: wra.awaddr, @@ -481,12 +509,12 @@ module mkMem_Controller (Mem_Controller_IFC); // Select the fabric data word of interest Bit #(Wd_Data) rdata = raw_mem_word_V_fabric_data [n]; - let rdr = AXI4_Rd_Data {rid: f_reqs.first.id, - rdata: rdata, - rresp: axi4_resp_okay, - rlast: True, - ruser: f_reqs.first.user}; - slave_xactor.i_rd_data.enq (rdr); + let rdr = AXI4_RFlit {rid: f_reqs.first.id, + rdata: rdata, + rresp: OKAY, + rlast: True, + ruser: f_reqs.first.user}; // XXX This requires that Wd_AR_User == Wd_R_User + slave_xactor.master.r.put(rdr); f_reqs.deq; if (cfg_verbosity > 1) begin @@ -525,10 +553,10 @@ module mkMem_Controller (Mem_Controller_IFC); rg_cached_raw_mem_word <= pack (raw_mem_word_V_Word64); rg_cached_clean <= False; - let wrr = AXI4_Wr_Resp {bid: f_reqs.first.id, - bresp: axi4_resp_okay, - buser: f_reqs.first.user}; - slave_xactor.i_wr_resp.enq (wrr); + let wrr = AXI4_BFlit {bid: f_reqs.first.id, + bresp: OKAY, + buser: f_reqs.first.user}; // XXX This requires that Wd_AW_User == Wd_B_User + slave_xactor.master.b.put(wrr); f_reqs.deq; if (cfg_verbosity > 1) begin @@ -593,12 +621,12 @@ module mkMem_Controller (Mem_Controller_IFC); && (! fn_addr_is_ok (rg_addr_base, f_reqs.first.addr, rg_addr_lim, f_reqs.first.size)) && (f_reqs.first.req_op == REQ_OP_RD)); Fabric_Data rdata = zeroExtend (f_reqs.first.addr); - let rdr = AXI4_Rd_Data {rid: f_reqs.first.id, - rdata: rdata, // for debugging only - rresp: axi4_resp_slverr, - rlast: True, - ruser: f_reqs.first.user}; - slave_xactor.i_rd_data.enq (rdr); + let rdr = AXI4_RFlit {rid: f_reqs.first.id, + rdata: rdata, // for debugging only + rresp: SLVERR, + rlast: True, + ruser: f_reqs.first.user}; // XXX This requires that Wd_AR_User == Wd_R_User + slave_xactor.master.r.put(rdr); f_reqs.deq; $write ("%0d: ERROR: Mem_Controller:", cur_cycle); @@ -614,10 +642,10 @@ module mkMem_Controller (Mem_Controller_IFC); rule rl_invalid_wr_address ( (rg_state == STATE_READY) && (! fn_addr_is_ok (rg_addr_base, f_reqs.first.addr, rg_addr_lim, f_reqs.first.size)) && (f_reqs.first.req_op == REQ_OP_WR)); - let wrr = AXI4_Wr_Resp {bid: f_reqs.first.id, - bresp: axi4_resp_slverr, - buser: f_reqs.first.user}; - slave_xactor.i_wr_resp.enq (wrr); + let wrr = AXI4_BFlit {bid: f_reqs.first.id, + bresp: SLVERR, + buser: f_reqs.first.user}; // XXX This requires that Wd_AW_User == Wd_B_User + slave_xactor.master.b.put(wrr); f_reqs.deq; $write ("%0d: ERROR: Mem_Controller:", cur_cycle); @@ -652,7 +680,7 @@ module mkMem_Controller (Mem_Controller_IFC); endmethod // Main Fabric Reqs/Rsps - interface slave = slave_xactor.axi_side; + interface slave = slave_xactor.slaveSynth; // To raw memory (outside the SoC) interface to_raw_mem = toGPClient (f_raw_mem_reqs, f_raw_mem_rsps); diff --git a/src_Testbench/SoC/SoC_Fabric.bsv b/src_Testbench/SoC/SoC_Fabric.bsv deleted file mode 100644 index e2115a78..00000000 --- a/src_Testbench/SoC/SoC_Fabric.bsv +++ /dev/null @@ -1,90 +0,0 @@ -// Copyright (c) 2013-2019 Bluespec, Inc. All Rights Reserved - -package SoC_Fabric; - -// ================================================================ -// Defines a SoC Fabric that is a specialization of AXI4_Lite_Fabric -// for this particular SoC. - -// ================================================================ -// Project imports - -import AXI4_Types :: *; -import AXI4_Fabric :: *; - -import Fabric_Defs :: *; // for Wd_Addr, Wd_Data, Wd_User -import SoC_Map :: *; // for Num_Masters, Num_Slaves - -// ================================================================ -// Slave address decoder -// Identifies whether a given addr is legal and, if so, which slave services it. - -typedef Bit #(TLog #(Num_Slaves)) Slave_Num; - -// ================================================================ -// Specialization of parameterized AXI4 fabric for this SoC. - -typedef AXI4_Fabric_IFC #(Num_Masters, - Num_Slaves, - Wd_Id, - Wd_Addr, - Wd_Data, - Wd_User) Fabric_AXI4_IFC; - -// ---------------- - -(* synthesize *) -module mkFabric_AXI4 (Fabric_AXI4_IFC); - - SoC_Map_IFC soc_map <- mkSoC_Map; - - function Tuple2 #(Bool, Slave_Num) fn_addr_to_slave_num (Fabric_Addr addr); - - // Main Mem - if ( (soc_map.m_mem0_controller_addr_base <= addr) - && (addr < soc_map.m_mem0_controller_addr_lim)) - return tuple2 (True, fromInteger (mem0_controller_slave_num)); - - // Boot ROM - else if ( (soc_map.m_boot_rom_addr_base <= addr) - && (addr < soc_map.m_boot_rom_addr_lim)) - return tuple2 (True, fromInteger (boot_rom_slave_num)); - -`ifdef Near_Mem_TCM - // TCM - else if ( (soc_map.m_tcm_addr_base <= addr) - && (addr < soc_map.m_tcm_addr_lim)) - return tuple2 (True, fromInteger (tcm_back_door_slave_num)); -`endif - - // UART - else if ( (soc_map.m_uart0_addr_base <= addr) - && (addr < soc_map.m_uart0_addr_lim)) - return tuple2 (True, fromInteger (uart0_slave_num)); - -`ifdef HTIF_MEMORY - else if ( (soc_map.m_htif_addr_base <= addr) - && (addr < soc_map.m_htif_addr_lim)) - return tuple2 (True, fromInteger (htif_slave_num)); -`endif - -`ifdef INCLUDE_ACCEL0 - // Accelerator 0 - else if ( (soc_map.m_accel0_addr_base <= addr) - && (addr < soc_map.m_accel0_addr_lim)) - return tuple2 (True, fromInteger (accel0_slave_num)); -`endif - - else - return tuple2 (False, ?); - endfunction - - AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, Wd_Id, Wd_Addr, Wd_Data, Wd_User) - fabric <- mkAXI4_Fabric (fn_addr_to_slave_num); - - return fabric; -endmodule - -// ================================================================ - -endpackage diff --git a/src_Testbench/SoC/SoC_Map.bsv b/src_Testbench/SoC/SoC_Map.bsv index 4042041a..fc7e72c2 100644 --- a/src_Testbench/SoC/SoC_Map.bsv +++ b/src_Testbench/SoC/SoC_Map.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2013-2019 Bluespec, Inc. All Rights Reserved +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package SoC_Map; // ================================================================ @@ -32,6 +45,7 @@ export dmem_master_num; export accel0_master_num; export Num_Slaves; +export Wd_SId; export boot_rom_slave_num; export mem0_controller_slave_num; export uart0_slave_num; @@ -45,7 +59,7 @@ export irq_num_accel0; // ================================================================ // Bluespec library imports -// None +import Routable :: *; // For Range // ================================================================ // Project imports @@ -56,35 +70,15 @@ import Fabric_Defs :: *; // Only for type Fabric_Addr // Interface and module for the address map interface SoC_Map_IFC; - (* always_ready *) method Fabric_Addr m_near_mem_io_addr_base; - (* always_ready *) method Fabric_Addr m_near_mem_io_addr_size; - (* always_ready *) method Fabric_Addr m_near_mem_io_addr_lim; - - (* always_ready *) method Fabric_Addr m_plic_addr_base; - (* always_ready *) method Fabric_Addr m_plic_addr_size; - (* always_ready *) method Fabric_Addr m_plic_addr_lim; - - (* always_ready *) method Fabric_Addr m_uart0_addr_base; - (* always_ready *) method Fabric_Addr m_uart0_addr_size; - (* always_ready *) method Fabric_Addr m_uart0_addr_lim; - + (* always_ready *) method Range#(Wd_Addr) m_near_mem_io_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_plic_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_uart0_addr_range; `ifdef INCLUDE_ACCEL0 - (* always_ready *) method Fabric_Addr m_accel0_addr_base; - (* always_ready *) method Fabric_Addr m_accel0_addr_size; - (* always_ready *) method Fabric_Addr m_accel0_addr_lim; + (* always_ready *) method Range#(Wd_Addr) m_accel0_addr_range; `endif - - (* always_ready *) method Fabric_Addr m_boot_rom_addr_base; - (* always_ready *) method Fabric_Addr m_boot_rom_addr_size; - (* always_ready *) method Fabric_Addr m_boot_rom_addr_lim; - - (* always_ready *) method Fabric_Addr m_mem0_controller_addr_base; - (* always_ready *) method Fabric_Addr m_mem0_controller_addr_size; - (* always_ready *) method Fabric_Addr m_mem0_controller_addr_lim; - - (* always_ready *) method Fabric_Addr m_tcm_addr_base; - (* always_ready *) method Fabric_Addr m_tcm_addr_size; - (* always_ready *) method Fabric_Addr m_tcm_addr_lim; + (* always_ready *) method Range#(Wd_Addr) m_boot_rom_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_mem0_controller_addr_range; + (* always_ready *) method Range#(Wd_Addr) m_tcm_addr_range; (* always_ready *) method Bool m_is_mem_addr (Fabric_Addr addr); @@ -110,35 +104,26 @@ module mkSoC_Map (SoC_Map_IFC); // ---------------------------------------------------------------- // Near_Mem_IO (including CLINT, the core-local interruptor) - Fabric_Addr near_mem_io_addr_base = 'h_0200_0000; - Fabric_Addr near_mem_io_addr_size = 'h_0000_C000; // 48K - Fabric_Addr near_mem_io_addr_lim = near_mem_io_addr_base + near_mem_io_addr_size; - - function Bool fn_is_near_mem_io_addr (Fabric_Addr addr); - return ((near_mem_io_addr_base <= addr) && (addr < near_mem_io_addr_lim)); - endfunction + let near_mem_io_addr_range = Range { + base: 'h_0200_0000, + size: 'h_0000_C000 // 48K + }; // ---------------------------------------------------------------- // PLIC - Fabric_Addr plic_addr_base = 'h_0C00_0000; - Fabric_Addr plic_addr_size = 'h_0040_0000; // 4M - Fabric_Addr plic_addr_lim = plic_addr_base + plic_addr_size; - - function Bool fn_is_plic_addr (Fabric_Addr addr); - return ((plic_addr_base <= addr) && (addr < plic_addr_lim)); - endfunction + let plic_addr_range = Range { + base: 'h0C00_0000, + size: 'h0040_0000 // 4M + }; // ---------------------------------------------------------------- // UART 0 - Fabric_Addr uart0_addr_base = 'hC000_0000; - Fabric_Addr uart0_addr_size = 'h0000_0080; // 128 - Fabric_Addr uart0_addr_lim = uart0_addr_base + uart0_addr_size; - - function Bool fn_is_uart0_addr (Fabric_Addr addr); - return ((uart0_addr_base <= addr) && (addr < uart0_addr_lim)); - endfunction + let uart0_addr_range = Range { + base: 'hC000_0000, + size: 'h0000_0080 // 128 + }; // ---------------------------------------------------------------- // ACCEL 0 @@ -156,24 +141,18 @@ module mkSoC_Map (SoC_Map_IFC); // ---------------------------------------------------------------- // Boot ROM - Fabric_Addr boot_rom_addr_base = 'h_0000_1000; - Fabric_Addr boot_rom_addr_size = 'h_0000_1000; // 4K - Fabric_Addr boot_rom_addr_lim = boot_rom_addr_base + boot_rom_addr_size; - - function Bool fn_is_boot_rom_addr (Fabric_Addr addr); - return ((boot_rom_addr_base <= addr) && (addr < boot_rom_addr_lim)); - endfunction + let boot_rom_addr_range = Range { + base: 'h_0000_1000, + size: 'h_0000_1000 // 4K + }; // ---------------------------------------------------------------- // Main Mem Controller 0 - Fabric_Addr mem0_controller_addr_base = 'h_8000_0000; - Fabric_Addr mem0_controller_addr_size = 'h_1000_0000; // 256 MB - Fabric_Addr mem0_controller_addr_lim = mem0_controller_addr_base + mem0_controller_addr_size; - - function Bool fn_is_mem0_controller_addr (Fabric_Addr addr); - return ((mem0_controller_addr_base <= addr) && (addr < mem0_controller_addr_lim)); - endfunction + let mem0_controller_addr_range = Range { + base: 'h_8000_0000, + size: 'h_0FFF_FFFF // 256 MB + }; // ---------------------------------------------------------------- // Tightly-coupled memory ('TCM'; optional) @@ -189,13 +168,10 @@ module mkSoC_Map (SoC_Map_IFC); `endif Integer bytes_per_TCM = kB_per_TCM * 'h400; - Fabric_Addr tcm_addr_base = 'h_0000_0000; - Fabric_Addr tcm_addr_size = fromInteger (bytes_per_TCM); - Fabric_Addr tcm_addr_lim = tcm_addr_base + tcm_addr_size; - - function Bool fn_is_tcm_addr (Fabric_Addr addr); - return ((tcm_addr_base <= addr) && (addr < tcm_addr_lim)); - endfunction + let tcm_addr_range = Range { + base: 'h_0000_0000, + size: fromInteger (bytes_per_TCM) + }; // ---------------------------------------------------------------- // Memory address predicate @@ -203,9 +179,9 @@ module mkSoC_Map (SoC_Map_IFC); // (Caches need this information to cache these addresses.) function Bool fn_is_mem_addr (Fabric_Addr addr); - return ( fn_is_boot_rom_addr (addr) - || fn_is_mem0_controller_addr (addr) - || fn_is_tcm_addr (addr) + return ( inRange(boot_rom_addr_range, addr) + || inRange(mem0_controller_addr_range, addr) + || inRange(tcm_addr_range, addr) ); endfunction @@ -215,19 +191,19 @@ module mkSoC_Map (SoC_Map_IFC); // (Caches need this information to avoid cacheing these addresses.) function Bool fn_is_IO_addr (Fabric_Addr addr); - return ( fn_is_near_mem_io_addr (addr) - || fn_is_plic_addr (addr) - || fn_is_uart0_addr (addr) + return ( inRange(near_mem_io_addr_range, addr) + || inRange(plic_addr_range, addr) + || inRange(uart0_addr_range, addr) `ifdef INCLUDE_ACCEL0 - || fn_is_accel0_addr (addr) + || inRange(accel0_addr_range, addr) `endif - ); + ); endfunction // ---------------------------------------------------------------- // PC, MTVEC and NMIVEC reset values - Bit #(64) pc_reset_value = boot_rom_addr_base; + Bit #(64) pc_reset_value = rangeBase(boot_rom_addr_range); Bit #(64) mtvec_reset_value = 'h1000; // TODO // Non-maskable interrupt vector @@ -236,41 +212,24 @@ module mkSoC_Map (SoC_Map_IFC); // ================================================================ // INTERFACE - method Fabric_Addr m_near_mem_io_addr_base = near_mem_io_addr_base; - method Fabric_Addr m_near_mem_io_addr_size = near_mem_io_addr_size; - method Fabric_Addr m_near_mem_io_addr_lim = near_mem_io_addr_lim; - - method Fabric_Addr m_plic_addr_base = plic_addr_base; - method Fabric_Addr m_plic_addr_size = plic_addr_size; - method Fabric_Addr m_plic_addr_lim = plic_addr_lim; - - method Fabric_Addr m_uart0_addr_base = uart0_addr_base; - method Fabric_Addr m_uart0_addr_size = uart0_addr_size; - method Fabric_Addr m_uart0_addr_lim = uart0_addr_lim; + method Range#(Wd_Addr) m_near_mem_io_addr_range = near_mem_io_addr_range; + method Range#(Wd_Addr) m_plic_addr_range = plic_addr_range; + method Range#(Wd_Addr) m_uart0_addr_range = uart0_addr_range; + method Range#(Wd_Addr) m_boot_rom_addr_range = boot_rom_addr_range; `ifdef INCLUDE_ACCEL0 - method Fabric_Addr m_accel0_addr_base = accel0_addr_base; - method Fabric_Addr m_accel0_addr_size = accel0_addr_size; - method Fabric_Addr m_accel0_addr_lim = accel0_addr_lim; + method Range#(Wd_Addr) m_accel0_addr_range = accel0_addr_range; `endif - method Fabric_Addr m_boot_rom_addr_base = boot_rom_addr_base; - method Fabric_Addr m_boot_rom_addr_size = boot_rom_addr_size; - method Fabric_Addr m_boot_rom_addr_lim = boot_rom_addr_lim; + method Range#(Wd_Addr) m_mem0_controller_addr_range = mem0_controller_addr_range; - method Fabric_Addr m_mem0_controller_addr_base = mem0_controller_addr_base; - method Fabric_Addr m_mem0_controller_addr_size = mem0_controller_addr_size; - method Fabric_Addr m_mem0_controller_addr_lim = mem0_controller_addr_lim; - - method Fabric_Addr m_tcm_addr_base = tcm_addr_base; - method Fabric_Addr m_tcm_addr_size = tcm_addr_size; - method Fabric_Addr m_tcm_addr_lim = tcm_addr_lim; + method Range#(Wd_Addr) m_tcm_addr_range = tcm_addr_range; method Bool m_is_mem_addr (Fabric_Addr addr) = fn_is_mem_addr (addr); method Bool m_is_IO_addr (Fabric_Addr addr) = fn_is_IO_addr (addr); - method Bool m_is_near_mem_IO_addr (Fabric_Addr addr) = fn_is_near_mem_io_addr (addr); + method Bool m_is_near_mem_IO_addr (Fabric_Addr addr) = inRange (near_mem_io_addr_range, addr); method Bit #(64) m_pc_reset_value = pc_reset_value; method Bit #(64) m_mtvec_reset_value = mtvec_reset_value; @@ -315,6 +274,10 @@ Integer mem0_controller_slave_num = 1; Integer uart0_slave_num = 2; Integer accel0_slave_num = 3; +// ================================================================ +// Width of fabric 'id' buses +typedef TAdd#(Wd_MId, TLog#(Num_Masters)) Wd_SId; + // ================================================================ // Interrupt request numbers (== index in to vector of // interrupt-request lines in Core) diff --git a/src_Testbench/SoC/SoC_Top.bsv b/src_Testbench/SoC/SoC_Top.bsv index 2778ab0b..0d9d7f45 100644 --- a/src_Testbench/SoC/SoC_Top.bsv +++ b/src_Testbench/SoC/SoC_Top.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved. +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package SoC_Top; // ================================================================ @@ -21,24 +34,21 @@ import GetPut :: *; import ClientServer :: *; import Connectable :: *; import Memory :: *; +import Vector :: *; // ---------------- // BSV additional libs import Cur_Cycle :: *; import GetPut_Aux :: *; +import Routable :: *; +import AXI4 :: *; // ================================================================ // Project imports -// Main fabric -import AXI4_Types :: *; -import AXI4_Fabric :: *; -import AXI4_Deburster :: *; - import Fabric_Defs :: *; import SoC_Map :: *; -import SoC_Fabric :: *; // SoC components (CPU, mem, and IPs) @@ -126,24 +136,19 @@ module mkSoC_Top (SoC_Top_IFC); // Core: CPU + Near_Mem_IO (CLINT) + PLIC + Debug module (optional) + TV (optional) Core_IFC #(N_External_Interrupt_Sources) core <- mkCore; - // SoC Fabric - Fabric_AXI4_IFC fabric <- mkFabric_AXI4; - // SoC Boot ROM Boot_ROM_IFC boot_rom <- mkBoot_ROM; // AXI4 Deburster in front of Boot_ROM - AXI4_Deburster_IFC #(Wd_Id, - Wd_Addr, - Wd_Data, - Wd_User) boot_rom_axi4_deburster <- mkAXI4_Deburster_A; + AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User) + boot_rom_axi4_deburster <- mkBurstToNoBurst; // SoC Memory Mem_Controller_IFC mem0_controller <- mkMem_Controller; // AXI4 Deburster in front of SoC Memory - AXI4_Deburster_IFC #(Wd_Id, - Wd_Addr, - Wd_Data, - Wd_User) mem0_controller_axi4_deburster <- mkAXI4_Deburster_A; + AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User) + mem0_controller_axi4_deburster <- mkBurstToNoBurst; // SoC IPs UART_IFC uart0 <- mkUART; @@ -157,43 +162,67 @@ module mkSoC_Top (SoC_Top_IFC); // SoC fabric master connections // Note: see 'SoC_Map' for 'master_num' definitions + Vector#(Num_Masters, AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data, + Wd_User, Wd_User, Wd_User, + Wd_User, Wd_User)) + master_vector = newVector; + // CPU IMem master to fabric - mkConnection (core.cpu_imem_master, fabric.v_from_masters [imem_master_num]); + master_vector[imem_master_num] = core.cpu_imem_master; // CPU DMem master to fabric - mkConnection (core.cpu_dmem_master, fabric.v_from_masters [dmem_master_num]); + master_vector[dmem_master_num] = core.cpu_dmem_master; `ifdef INCLUDE_ACCEL0 // accel_aes0 to fabric - mkConnection (accel0.master, fabric.v_from_masters [accel0_master_num]); + master_vector[accel0_master_num] = accel_aes0.master; `endif // ---------------- // SoC fabric slave connections // Note: see 'SoC_Map' for 'slave_num' definitions - // Fabric to Boot ROM - mkConnection (fabric.v_to_slaves [boot_rom_slave_num], boot_rom_axi4_deburster.from_master); - mkConnection (boot_rom_axi4_deburster.to_slave, boot_rom.slave); + Vector#(Num_Slaves, AXI4_Slave_Synth #(Wd_SId, Wd_Addr, Wd_Data, + Wd_User, Wd_User, Wd_User, + Wd_User, Wd_User)) + slave_vector = newVector; + Vector#(Num_Slaves, Range#(Wd_Addr)) route_vector = newVector; - // Fabric to Deburster to Mem Controller - mkConnection (fabric.v_to_slaves [mem0_controller_slave_num], mem0_controller_axi4_deburster.from_master); - mkConnection (mem0_controller_axi4_deburster.to_slave, mem0_controller.slave); + // Fabric to Boot ROM + let br <- fromAXI4_Slave_Synth(boot_rom.slave); + mkConnection(boot_rom_axi4_deburster.master, br); + let ug_boot_rom_slave <- toUnguarded_AXI4_Slave(boot_rom_axi4_deburster.slave); + slave_vector[boot_rom_slave_num] = toAXI4_Slave_Synth(ug_boot_rom_slave); + route_vector[boot_rom_slave_num] = soc_map.m_boot_rom_addr_range; + + // Fabric to Mem Controller + let mem <- fromAXI4_Slave_Synth(mem0_controller.slave); + mkConnection(mem0_controller_axi4_deburster.master, mem); + let ug_mem0_slave <- toUnguarded_AXI4_Slave(mem0_controller_axi4_deburster.slave); + slave_vector[mem0_controller_slave_num] = toAXI4_Slave_Synth(ug_mem0_slave); + route_vector[mem0_controller_slave_num] = soc_map.m_mem0_controller_addr_range; // Fabric to UART0 - mkConnection (fabric.v_to_slaves [uart0_slave_num], uart0.slave); + slave_vector[uart0_slave_num] = uart0.slave; + route_vector[uart0_slave_num] = soc_map.m_uart0_addr_range; `ifdef INCLUDE_ACCEL0 - // Fabric to accel0 - mkConnection (fabric.v_to_slaves [accel0_slave_num], accel0.slave); + // Fabric to accel_aes0 + slave_vector[accel0_slave_num] = accel_aes0.slave); + route_vector[accel0_slave_num] = soc_map.m_accel0_addr_range; `endif `ifdef HTIF_MEMORY AXI4_Slave_IFC#(Wd_Id, Wd_Addr, Wd_Data, Wd_User) htif <- mkAxi4LRegFile(bytes_per_htif); - mkConnection (fabric.v_to_slaves [htif_slave_num], htif); + slave_vector[htif_slave_num] = htif; + route_vector[htif_slave_num] = soc_map.m_htif_addr_range; `endif + // SoC Fabric + let bus <- mkAXI4Bus_Synth (routeFromMappingTable(route_vector), + master_vector, slave_vector); + // ---------------- // Connect interrupt sources for CPU external interrupt request inputs. @@ -238,7 +267,6 @@ module mkSoC_Top (SoC_Top_IFC); core.cpu_reset_server.request.put (running); mem0_controller.server_reset.request.put (?); uart0.server_reset.request.put (?); - fabric.reset; endaction endfunction @@ -249,13 +277,14 @@ module mkSoC_Top (SoC_Top_IFC); let uart0_rsp <- uart0.server_reset.response.get; // Initialize address maps of slave IPs - boot_rom.set_addr_map (soc_map.m_boot_rom_addr_base, - soc_map.m_boot_rom_addr_lim); + boot_rom.set_addr_map (rangeBase(soc_map.m_boot_rom_addr_range), + rangeTop(soc_map.m_boot_rom_addr_range)); - mem0_controller.set_addr_map (soc_map.m_mem0_controller_addr_base, - soc_map.m_mem0_controller_addr_lim); + mem0_controller.set_addr_map (rangeBase(soc_map.m_mem0_controller_addr_range), + rangeTop(soc_map.m_mem0_controller_addr_range)); - uart0.set_addr_map (soc_map.m_uart0_addr_base, soc_map.m_uart0_addr_lim); + uart0.set_addr_map (rangeBase(soc_map.m_uart0_addr_range), + rangeTop(soc_map.m_uart0_addr_range)); `ifdef INCLUDE_ACCEL0 accel0.init (fabric_default_id, @@ -266,14 +295,14 @@ module mkSoC_Top (SoC_Top_IFC); if (verbosity != 0) begin $display (" SoC address map:"); $display (" Boot ROM: 0x%0h .. 0x%0h", - soc_map.m_boot_rom_addr_base, - soc_map.m_boot_rom_addr_lim); + rangeBase(soc_map.m_boot_rom_addr_range), + rangeTop(soc_map.m_boot_rom_addr_range)); $display (" Mem0 Controller: 0x%0h .. 0x%0h", - soc_map.m_mem0_controller_addr_base, - soc_map.m_mem0_controller_addr_lim); + rangeBase(soc_map.m_mem0_controller_addr_range), + rangeTop(soc_map.m_mem0_controller_addr_range)); $display (" UART0: 0x%0h .. 0x%0h", - soc_map.m_uart0_addr_base, - soc_map.m_uart0_addr_lim); + rangeBase(soc_map.m_uart0_addr_range), + rangeTop(soc_map.m_uart0_addr_range)); end endaction endfunction @@ -376,8 +405,64 @@ module mkSoC_Top (SoC_Top_IFC); $display ("%0d:%m.rl_handle_external_req_err: unknown req.op", cur_cycle); $display (" ", fshow (req)); endrule + + // ---------------------------------------------------------------- + // NDM reset (all except Debug Module) request from debug module + + rule rl_reset_start (rg_state != SOC_RESETTING); + let req <- core.dm_ndm_reset_req_get.get; + + core.cpu_reset_server.request.put (?); + mem0_controller.server_reset.request.put (?); + uart0.server_reset.request.put (?); + + boot_rom_axi4_deburster.clear; + mem0_controller_axi4_deburster.clear; + + rg_state <= SOC_RESETTING; + + $display ("%0d: SoC_Top.rl_reset_start (Debug Module NDM reset, all except debug module) ...", + cur_cycle); + endrule `endif + rule rl_reset_complete (rg_state == SOC_RESETTING); + let cpu_rsp <- core.cpu_reset_server.response.get; + let mem0_controller_rsp <- mem0_controller.server_reset.response.get; + let uart0_rsp <- uart0.server_reset.response.get; + + // Initialize address maps of slave IPs + boot_rom.set_addr_map (rangeBase(soc_map.m_boot_rom_addr_range), + rangeTop(soc_map.m_boot_rom_addr_range)); + + mem0_controller.set_addr_map (rangeBase(soc_map.m_mem0_controller_addr_range), + rangeTop(soc_map.m_mem0_controller_addr_range)); + + uart0.set_addr_map (rangeBase(soc_map.m_uart0_addr_range), + rangeTop(soc_map.m_uart0_addr_range)); + + rg_state <= SOC_IDLE; + +`ifdef INCLUDE_GDB_CONTROL + $display ("%0d: SoC_Top: NDM reset complete (all except debug module)", cur_cycle); +`else + $display ("%0d: SoC_Top. Reset complete ...", cur_cycle); +`endif + + if (verbosity != 0) begin + $display (" SoC address map:"); + $display (" Boot ROM: 0x%0h .. 0x%0h", + rangeBase(soc_map.m_boot_rom_addr_range), + rangeTop(soc_map.m_boot_rom_addr_range)); + $display (" Mem0 Controller: 0x%0h .. 0x%0h", + rangeBase(soc_map.m_mem0_controller_addr_range), + rangeTop(soc_map.m_mem0_controller_addr_range)); + $display (" UART0: 0x%0h .. 0x%0h", + rangeBase(soc_map.m_uart0_addr_range), + rangeTop(soc_map.m_uart0_addr_range)); + end + endrule + // ================================================================ // INTERFACE @@ -413,18 +498,6 @@ module mkSoC_Top (SoC_Top_IFC); endmethod endmodule: mkSoC_Top -// ================================================================ -// Specialization of parameterized AXI4 Deburster for this SoC. - -(* synthesize *) -module mkAXI4_Deburster_A (AXI4_Deburster_IFC #(Wd_Id, - Wd_Addr, - Wd_Data, - Wd_User)); - let m <- mkAXI4_Deburster; - return m; -endmodule - // ================================================================ endpackage diff --git a/src_Testbench/SoC/UART_Model.bsv b/src_Testbench/SoC/UART_Model.bsv index f6fded84..cdea8ea5 100644 --- a/src_Testbench/SoC/UART_Model.bsv +++ b/src_Testbench/SoC/UART_Model.bsv @@ -1,5 +1,18 @@ // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved +//- +// AXI (user fields) modifications: +// Copyright (c) 2019 Alexandre Joannou +// Copyright (c) 2019 Peter Rugg +// Copyright (c) 2019 Jonathan Woodruff +// All rights reserved. +// +// This software was developed by SRI International and the University of +// Cambridge Computer Laboratory (Department of Computer Science and +// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +// DARPA SSITH research programme. +//- + package UART_Model; // ================================================================ @@ -38,12 +51,14 @@ import ConfigReg :: *; import Cur_Cycle :: *; import GetPut_Aux :: *; import Semi_FIFOF :: *; +import AXI4 :: *; +import SourceSink :: *; // ================================================================ // Project imports -import AXI4_Types :: *; import Fabric_Defs :: *; +import SoC_Map :: *; // ================================================================ // UART registers and their address offsets @@ -109,7 +124,9 @@ interface UART_IFC; method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim); // Main Fabric Reqs/Rsps - interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave; + interface AXI4_Slave_Synth #(Wd_SId, Wd_Addr, Wd_Data, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) slave; // To external console interface Get #(Bit #(8)) get_to_console; @@ -145,6 +162,8 @@ endfunction (* synthesize *) module mkUART (UART_IFC); +// XXX This module seems to assume the following constraints: +// provisos(Add #(Wd_AW_User, 0, Wd_B_User), Add #(Wd_AR_User, 0, Wd_R_User)); Reg #(Bit #(8)) cfg_verbosity <- mkConfigReg (0); @@ -158,7 +177,7 @@ module mkUART (UART_IFC); // ---------------- // Connector to fabric - AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave_xactor <- mkAXI4_Slave_Xactor; + let slave_xactor <- mkAXI4_Slave_Xactor; // ---------------- // character queues to and from the console @@ -230,7 +249,7 @@ module mkUART (UART_IFC); rg_msr <= 0; rg_scr <= 0; - slave_xactor.reset; + slave_xactor.clear; rg_state <= STATE_READY; f_reset_rsps.enq (?); @@ -243,23 +262,23 @@ module mkUART (UART_IFC); // Handle fabric read requests rule rl_process_rd_req (rg_state == STATE_READY); - let rda <- pop_o (slave_xactor.o_rd_addr); + let rda <- get(slave_xactor.master.ar); let byte_addr = rda.araddr - rg_addr_base; let { msbs, offset, lsbs } = split_addr (zeroExtend (byte_addr)); Bit #(8) rdata_byte = 0; - AXI4_Resp rresp = axi4_resp_okay; + AXI4_Resp rresp = OKAY; if (lsbs != 0) begin $display ("%0d: ERROR: UART.rl_process_rd_req: misaligned addr", cur_cycle); $display (" ", fshow (rda)); - rresp = axi4_resp_slverr; + rresp = SLVERR; end else if (msbs != 0) begin $display ("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", cur_cycle); $display (" ", fshow (rda)); - rresp = axi4_resp_decerr; + rresp = DECERR; end // offset 0: RBR @@ -296,17 +315,17 @@ module mkUART (UART_IFC); else begin $display ("%0d: ERROR: UART.rl_process_rd_req: unrecognized addr", cur_cycle); $display (" ", fshow (rda)); - rresp = axi4_resp_decerr; + rresp = DECERR; end // Send read-response to bus Fabric_Data rdata = zeroExtend (rdata_byte); - let rdr = AXI4_Rd_Data {rid: rda.arid, - rdata: rdata, - rresp: rresp, - rlast: True, - ruser: rda.aruser}; - slave_xactor.i_rd_data.enq (rdr); + let rdr = AXI4_RFlit {rid: rda.arid, + rdata: rdata, + rresp: rresp, + rlast: True, + ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User + slave_xactor.master.r.put(rdr); if (cfg_verbosity > 1) begin $display ("%0d: UART.rl_process_rd_req", cur_cycle); @@ -319,8 +338,8 @@ module mkUART (UART_IFC); // Handle fabric write requests rule rl_process_wr_req (rg_state == STATE_READY); - let wra <- pop_o (slave_xactor.o_wr_addr); - let wrd <- pop_o (slave_xactor.o_wr_data); + let wra <- get(slave_xactor.master.aw); + let wrd <- get(slave_xactor.master.w); Bit #(64) wdata = zeroExtend (wrd.wdata); Bit #(8) wstrb = zeroExtend (wrd.wstrb); @@ -329,19 +348,19 @@ module mkUART (UART_IFC); let byte_addr = wra.awaddr - rg_addr_base; let { msbs, offset, lsbs } = split_addr (zeroExtend (byte_addr)); - AXI4_Resp bresp = axi4_resp_okay; + AXI4_Resp bresp = OKAY; if ((lsbs != 0) || (wstrb [0] == 1'b0)) begin $display ("%0d: ERROR: UART.rl_process_wr_req: misaligned addr", cur_cycle); $display (" ", fshow (wra)); $display (" ", fshow (wrd)); - bresp = axi4_resp_slverr; + bresp = SLVERR; end else if (msbs != 0) begin $display ("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", cur_cycle); $display (" ", fshow (wra)); $display (" ", fshow (wrd)); - bresp = axi4_resp_decerr; + bresp = DECERR; end // offset 0: THR @@ -379,14 +398,14 @@ module mkUART (UART_IFC); $display ("%0d: ERROR: UART.rl_process_wr_req: unrecognized addr", cur_cycle); $display (" ", fshow (wra)); $display (" ", fshow (wrd)); - bresp = axi4_resp_decerr; + bresp = DECERR; end // Send write-response to bus - let wrr = AXI4_Wr_Resp {bid: wra.awid, - bresp: bresp, - buser: wra.awuser}; - slave_xactor.i_wr_resp.enq (wrr); + let wrr = AXI4_BFlit {bid: wra.awid, + bresp: bresp, + buser: wra.awuser}; // XXX This requires that Wd_AW_User == Wd_B_User + slave_xactor.master.b.put(wrr); if (cfg_verbosity > 1) begin $display ("%0d: UART.rl_process_wr_req", cur_cycle); @@ -434,7 +453,7 @@ module mkUART (UART_IFC); endmethod // Main Fabric Reqs/Rsps - interface slave = slave_xactor.axi_side; + interface slave = slave_xactor.slaveSynth; // To external console interface put_from_console = toPut (f_from_console);